openbcm

Git mirror of https://github.com/Broadcom-Network-Switching-Software/OpenBCM
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bcm.soc (4178B)


      1 # 
      2 # This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file.
      3 # 
      4 # Copyright 2007-2019 Broadcom Inc. All rights reserved.
      5 
      6 # Initialization RC (run commands) file
      7 #
      8 # These are default commands that are read and executed by default
      9 # when BCM boots up.  Typically this file is called rc.soc and resides
     10 # in the flash filesystem, NVRAM, or disk.
     11 #
     12 
     13 if $?1 "echo bcm.soc: arguments not supported; exit"
     14 
     15 # On 48-port, set PCI retries to infinite to get around PCI bridge
     16 # fairness bug in IDTRC3233x.
     17 if $?p48 "s pcic 0x40 0x0080"
     18 
     19 # Be sure linkscan is off before doing init. 
     20 linkscan off
     21 
     22 # Set convenience local variables
     23 
     24 if $?quickturn || $?plisim \
     25 	"local simulator 1"
     26 
     27 # Set software's wait for S-Channel response to 3 seconds for QuickTurn
     28 # (Recommend at least 10 seconds if the ARL is 100% busy with inserts.)
     29 if $?quickturn	"stimeout 3000000"
     30 
     31 # Reset chip, initialize for most basic operation
     32 init soc
     33 
     34 # Initialize miscellaneous chip registers
     35 init misc
     36 
     37 # Program the SDRAM timing and MMU switch configuration registers
     38 init mmu
     39 
     40 # Determine and configure the GBP size
     41 if !$?gsl && !$?drac "sizegbp size=auto quiet=yes"
     42 
     43 # Initialize the Slot Free Address Pool in the GBP
     44 if !$?gsl && !$?drac && !$?herc "sfapinit"
     45 
     46 # Turn on mirroring of hardware ARL operations into software ARL table.
     47 if !$?drac && !$?herc && !$?simulator "arlmode intr_dma"
     48 if $?drac && !$?simulator "l2mode interval=3000000"
     49 
     50 # Enable caching of some tables.  Caching uses memory, but reduces or
     51 # eliminates table reads.  When a cache is enabled on a table, the whole
     52 # table is read in.  Note: L3 usually can't be cached because the
     53 # hardware can update the hit bits.
     54 if !$?gsl && !$?drac && !$?herc "cache imask irule"
     55 if                      !$?herc "cache gimask girule"
     56 if           !$?drac && !$?herc "cache marl ptable vtable"
     57 if           !$?drac && !$?herc "cache l3intf def_ip"
     58 if            $?drac            "cache port vlan trunk_bitmap trunk_group"
     59 if                       $?herc "cache uc mc vid"
     60 echo "Table caches enabled"
     61 
     62 # Initialize the BCM driver layer
     63 init bcm
     64 echo "BCM Driver Enabled"
     65 
     66 # Configure ports and turn enable automatic link scanning
     67 linkscan 250000
     68 port * linkscan=on autoneg=on \
     69 	speed=0 fullduplex=true txpause=true rxpause=true
     70 
     71 stg stp 1 all forward
     72 
     73 # Clear counters and enable counter collection
     74 clear counters
     75 if  $?quickturn "local cint 1000"
     76 if !$?quickturn "local cint 1000000"
     77 if  $?plisim    "local cdma false"
     78 if !$?plisim    "local cdma true"
     79 counter Interval=$cint Pbm=all DMA=$cdma
     80 
     81 # Set default mode for packet watcher
     82 pw report +raw
     83 
     84 # Default LED processor program for 5605 SDK
     85 
     86 if !$?p48 "local ledcode '\
     87  E0 28 60 7F 67 2F 67 6B 06 7F 80 D2 1A 74 01 12 \
     88  7E 85 05 D2 0F 71 19 52 00 12 7D 85 05 D2 1F 71 \
     89  23 52 00 12 7C 85 05 D2 05 71 2D 52 00 3A 68 32 \
     90  00 97 75 3B 12 A0 FE 7F 02 0A 50 32 01 97 75 47 \
     91  12 BA FE 7F 02 0A 50 12 BA FE 7F 95 75 59 85 12 \
     92  A0 FE 7F 95 75 A8 85 77 9A 12 A0 FE 7F 95 75 63 \
     93  85 77 A1 16 7C DA 02 71 A1 77 A8 32 05 97 71 76 \
     94  06 7D D2 01 71 9A 06 7F 67 93 75 9A 32 02 97 71 \
     95  9A 32 03 97 71 A8 32 04 97 75 A1 06 7E D2 07 71 \
     96  A1 77 A8 12 80 F8 15 1A 00 57 32 0E 87 32 0E 87 \
     97  57 32 0E 87 32 0F 87 57 32 0F 87 32 0E 87 57'"
     98 
     99 # Default LED processor program for 48-port SDK
    100 
    101 if $?p48 "local ledcode '\
    102  E0 28 60 7F 67 43 67 3C 67 35 67 2F 06 7F 80 D2 \
    103  18 74 01 28 60 7F 67 9B 67 89 67 BF 67 83 67 3C \
    104  67 73 67 68 67 5D 06 7F 80 D2 1A 74 13 3A 70 67 \
    105  AD 71 C3 77 BF 32 03 97 71 C3 77 BF 32 05 97 71 \
    106  C3 77 BF 12 BA FE 7F 32 01 97 75 4F 02 06 50 32 \
    107  00 97 75 57 02 06 50 95 75 C3 85 77 BF 67 AD 75 \
    108  BF 32 04 97 71 C3 77 BF 67 AD 75 BF 32 03 97 71 \
    109  C3 77 BF 67 AD 75 BF 32 03 97 71 BF 32 04 97 71 \
    110  BF 77 C3 67 B6 71 C3 77 BF 12 A0 FE 7F 32 00 97 \
    111  75 95 02 06 50 95 75 C3 85 77 BF 12 BA FE 7F 32 \
    112  01 97 75 A7 02 06 50 95 75 C3 85 77 BF 06 7F 12 \
    113  80 F8 15 1A 00 57 06 7F 12 80 F8 15 1A 07 57 32 \
    114  0F 87 57 32 0E 87 57'"
    115 
    116 # Download LED code into LED process and enable (if applicable)
    117 
    118 if $?BCM5605_A0 || $?ul \
    119 	"led prog $ledcode; \
    120 	 led auto on; \
    121 	 led start"
    122 
    123 echo "Initialization complete."