bcmi_tscf_xgxs_sym.c (484938B)
1 /******************************************************************************* 2 * 3 * 4 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 5 * 6 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 7 * 8 * DO NOT EDIT THIS FILE! 9 * This file is auto-generated from the registers file. 10 * Edits to this file will be lost when it is regenerated. 11 * 12 * Symbol table file for the BCMI_TSCF_XGXS. 13 * This symbol table is used by the Broadcom debug shell. 14 */ 15 16 17 #include <phymod/chip/bcmi_tscf_xgxs_defs.h> 18 #include <phymod/phymod_symbols.h> 19 20 /* No symbols will be compiled unless this is defined. */ 21 #if PHYMOD_CONFIG_INCLUDE_CHIP_SYMBOLS == 1 22 /******************************************************************************* 23 * 24 * If PHYMOD_CONFIG_INCLUDE_FIELD_INFO is 1, then symbol information 25 * necessary to encode and decode the individual fields of a register or memory 26 * will be available. 27 * 28 * Without it, only the register and memory names will be symbolically available 29 * and their values will be displayed as raw data only. 30 * 31 * Field information can be compiled out in the interest of saving code space. 32 */ 33 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 34 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 35 36 static uint32_t BCMI_TSCF_XGXS_ACC_ADDR_DATAr_fields[] = 37 { 38 /* MDIO_ADDR_DATA:0:15 */ 39 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(835, 15, 0) 40 }; 41 static uint32_t BCMI_TSCF_XGXS_ACC_CTLr_fields[] = 42 { 43 /* MDIO_DEVAD:0:4 */ 44 PHYMOD_SYMBOL_FIELD_ENCODE(839, 4, 0), 45 /* MDIO_FUNCTION:14:15 */ 46 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(846, 15, 14) 47 }; 48 static uint32_t BCMI_TSCF_XGXS_AMS_PLL_CTL0r_fields[] = 49 { 50 /* AMS_PLL_SET_CLK4TSC:0:1 */ 51 PHYMOD_SYMBOL_FIELD_ENCODE(83, 1, 0), 52 /* AMS_PLL_IMIN_ICLKINT:2:2 */ 53 PHYMOD_SYMBOL_FIELD_ENCODE(52, 2, 2), 54 /* AMS_PLL_IMAX_ICLKINT:3:3 */ 55 PHYMOD_SYMBOL_FIELD_ENCODE(41, 3, 3), 56 /* AMS_PLL_IMODE_ICLKINT:4:4 */ 57 PHYMOD_SYMBOL_FIELD_ENCODE(63, 4, 4), 58 /* AMS_PLL_IMIN_ICLKODRV1:5:5 */ 59 PHYMOD_SYMBOL_FIELD_ENCODE(53, 5, 5), 60 /* AMS_PLL_IMAX_ICLKODRV1:6:6 */ 61 PHYMOD_SYMBOL_FIELD_ENCODE(42, 6, 6), 62 /* AMS_PLL_IMODE_ICLKODRV1:7:7 */ 63 PHYMOD_SYMBOL_FIELD_ENCODE(64, 7, 7), 64 /* AMS_PLL_IMIN_ICLKIDRV1:8:8 */ 65 PHYMOD_SYMBOL_FIELD_ENCODE(51, 8, 8), 66 /* AMS_PLL_IMAX_ICLKIDRV1:9:9 */ 67 PHYMOD_SYMBOL_FIELD_ENCODE(40, 9, 9), 68 /* AMS_PLL_IMODE_ICLKIDRV1:10:10 */ 69 PHYMOD_SYMBOL_FIELD_ENCODE(62, 10, 10), 70 /* AMS_PLL_CAL_OFF:11:11 */ 71 PHYMOD_SYMBOL_FIELD_ENCODE(30, 11, 11), 72 /* AMS_PLL_CAL_AUX:12:15 */ 73 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(29, 15, 12) 74 }; 75 static uint32_t BCMI_TSCF_XGXS_AMS_PLL_CTL1r_fields[] = 76 { 77 /* AMS_PLL_IMIN_ICKGEN:0:0 */ 78 PHYMOD_SYMBOL_FIELD_ENCODE(50, 0, 0), 79 /* AMS_PLL_IMAX_ICKGEN:1:1 */ 80 PHYMOD_SYMBOL_FIELD_ENCODE(39, 1, 1), 81 /* AMS_PLL_IMODE_ICKGEN:2:2 */ 82 PHYMOD_SYMBOL_FIELD_ENCODE(61, 2, 2), 83 /* AMS_PLL_DRV_HV_DISABLE:3:3 */ 84 PHYMOD_SYMBOL_FIELD_ENCODE(32, 3, 3), 85 /* AMS_PLL_TEST_BG_OPAMP_BIAS:4:5 */ 86 PHYMOD_SYMBOL_FIELD_ENCODE(88, 5, 4), 87 /* AMS_PLL_SPARE_23_22:6:7 */ 88 PHYMOD_SYMBOL_FIELD_ENCODE(86, 7, 6), 89 /* AMS_PLL_VCOICTRL:8:9 */ 90 PHYMOD_SYMBOL_FIELD_ENCODE(96, 9, 8), 91 /* AMS_PLL_VCO_INDICATOR:10:10 */ 92 PHYMOD_SYMBOL_FIELD_ENCODE(97, 10, 10), 93 /* AMS_PLL_IVCO:11:13 */ 94 PHYMOD_SYMBOL_FIELD_ENCODE(71, 13, 11), 95 /* AMS_PLL_RESET:14:14 */ 96 PHYMOD_SYMBOL_FIELD_ENCODE(82, 14, 14), 97 /* AMS_PLL_ENABLE_FTUNE:15:15 */ 98 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(33, 15, 15) 99 }; 100 static uint32_t BCMI_TSCF_XGXS_AMS_PLL_CTL2r_fields[] = 101 { 102 /* AMS_PLL_EN_HRZ:0:0 */ 103 PHYMOD_SYMBOL_FIELD_ENCODE(34, 0, 0), 104 /* AMS_PLL_IQP:1:4 */ 105 PHYMOD_SYMBOL_FIELD_ENCODE(70, 4, 1), 106 /* AMS_PLL_REFL_PLL:5:5 */ 107 PHYMOD_SYMBOL_FIELD_ENCODE(81, 5, 5), 108 /* AMS_PLL_REFH_PLL:6:6 */ 109 PHYMOD_SYMBOL_FIELD_ENCODE(80, 6, 6), 110 /* AMS_PLL_IMIN_IBIAS:7:7 */ 111 PHYMOD_SYMBOL_FIELD_ENCODE(48, 7, 7), 112 /* AMS_PLL_IMODE_IBIAS:8:8 */ 113 PHYMOD_SYMBOL_FIELD_ENCODE(59, 8, 8), 114 /* AMS_PLL_IMAX_IBIAS:9:9 */ 115 PHYMOD_SYMBOL_FIELD_ENCODE(37, 9, 9), 116 /* AMS_PLL_IMIN_ICP:10:10 */ 117 PHYMOD_SYMBOL_FIELD_ENCODE(56, 10, 10), 118 /* AMS_PLL_IMODE_ICP:11:11 */ 119 PHYMOD_SYMBOL_FIELD_ENCODE(67, 11, 11), 120 /* AMS_PLL_IMAX_ICP:12:12 */ 121 PHYMOD_SYMBOL_FIELD_ENCODE(45, 12, 12), 122 /* AMS_PLL_IMIN_ICK:13:13 */ 123 PHYMOD_SYMBOL_FIELD_ENCODE(49, 13, 13), 124 /* AMS_PLL_IMODE_ICK:14:14 */ 125 PHYMOD_SYMBOL_FIELD_ENCODE(60, 14, 14), 126 /* AMS_PLL_IMAX_ICK:15:15 */ 127 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(38, 15, 15) 128 }; 129 static uint32_t BCMI_TSCF_XGXS_AMS_PLL_CTL3r_fields[] = 130 { 131 /* AMS_PLL_IMIN_IRXCLKBUF:0:0 */ 132 PHYMOD_SYMBOL_FIELD_ENCODE(58, 0, 0), 133 /* AMS_PLL_IMODE_IRXCLKBUF:1:1 */ 134 PHYMOD_SYMBOL_FIELD_ENCODE(69, 1, 1), 135 /* AMS_PLL_IMAX_IRXCLKBUF:2:2 */ 136 PHYMOD_SYMBOL_FIELD_ENCODE(47, 2, 2), 137 /* AMS_PLL_IMIN_ICMLDIV:3:3 */ 138 PHYMOD_SYMBOL_FIELD_ENCODE(54, 3, 3), 139 /* AMS_PLL_IMODE_ICMLDIV:4:4 */ 140 PHYMOD_SYMBOL_FIELD_ENCODE(65, 4, 4), 141 /* AMS_PLL_IMAX_ICMLDIV:5:5 */ 142 PHYMOD_SYMBOL_FIELD_ENCODE(43, 5, 5), 143 /* AMS_PLL_IMIN_ICOMP:6:6 */ 144 PHYMOD_SYMBOL_FIELD_ENCODE(55, 6, 6), 145 /* AMS_PLL_IMODE_ICOMP:7:7 */ 146 PHYMOD_SYMBOL_FIELD_ENCODE(66, 7, 7), 147 /* AMS_PLL_IMAX_ICOMP:8:8 */ 148 PHYMOD_SYMBOL_FIELD_ENCODE(44, 8, 8), 149 /* AMS_PLL_IMIN_IOP:9:9 */ 150 PHYMOD_SYMBOL_FIELD_ENCODE(57, 9, 9), 151 /* AMS_PLL_IMODE_IOP:10:10 */ 152 PHYMOD_SYMBOL_FIELD_ENCODE(68, 10, 10), 153 /* AMS_PLL_IMAX_IOP:11:11 */ 154 PHYMOD_SYMBOL_FIELD_ENCODE(46, 11, 11), 155 /* AMS_PLL_TEST_VREF:12:12 */ 156 PHYMOD_SYMBOL_FIELD_ENCODE(94, 12, 12), 157 /* AMS_PLL_TEST_VC:13:13 */ 158 PHYMOD_SYMBOL_FIELD_ENCODE(93, 13, 13), 159 /* AMS_PLL_TEST_PLL:14:14 */ 160 PHYMOD_SYMBOL_FIELD_ENCODE(89, 14, 14), 161 /* AMS_PLL_TEST_RX:15:15 */ 162 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(92, 15, 15) 163 }; 164 static uint32_t BCMI_TSCF_XGXS_AMS_PLL_CTL4r_fields[] = 165 { 166 /* AMS_PLL_BGR_PTATADJ:0:3 */ 167 PHYMOD_SYMBOL_FIELD_ENCODE(28, 3, 0), 168 /* AMS_PLL_BGR_CTATADJ:4:7 */ 169 PHYMOD_SYMBOL_FIELD_ENCODE(27, 7, 4), 170 /* AMS_PLL_PLL2RX_CLKBW:8:9 */ 171 PHYMOD_SYMBOL_FIELD_ENCODE(79, 9, 8), 172 /* AMS_PLL_COMP_VTH:10:10 */ 173 PHYMOD_SYMBOL_FIELD_ENCODE(31, 10, 10), 174 /* AMS_PLL_VDDR_BGB:11:11 */ 175 PHYMOD_SYMBOL_FIELD_ENCODE(98, 11, 11), 176 /* AMS_PLL_KVH_FORCE:12:13 */ 177 PHYMOD_SYMBOL_FIELD_ENCODE(72, 13, 12), 178 /* AMS_PLL_FORCE_KVH_BW:14:14 */ 179 PHYMOD_SYMBOL_FIELD_ENCODE(35, 14, 14), 180 /* AMS_PLL_FORCE_RESCAL:15:15 */ 181 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(36, 15, 15) 182 }; 183 static uint32_t BCMI_TSCF_XGXS_AMS_PLL_CTL5r_fields[] = 184 { 185 /* AMS_PLL_TEST_PORT_MAX_AMPLITUDE:0:0 */ 186 PHYMOD_SYMBOL_FIELD_ENCODE(91, 0, 0), 187 /* AMS_PLL_BGIP:1:1 */ 188 PHYMOD_SYMBOL_FIELD_ENCODE(26, 1, 1), 189 /* AMS_PLL_BGINT:2:2 */ 190 PHYMOD_SYMBOL_FIELD_ENCODE(25, 2, 2), 191 /* AMS_PLL_VBYPASS:3:3 */ 192 PHYMOD_SYMBOL_FIELD_ENCODE(95, 3, 3), 193 /* AMS_PLL_TEST_PNP:4:5 */ 194 PHYMOD_SYMBOL_FIELD_ENCODE(90, 5, 4), 195 /* AMS_PLL_MIX3P1C_CALR_CTATADJ:6:10 */ 196 PHYMOD_SYMBOL_FIELD_ENCODE(77, 10, 6), 197 /* AMS_PLL_MIX3P1C_CALR_PTATADJ:11:15 */ 198 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(78, 15, 11) 199 }; 200 static uint32_t BCMI_TSCF_XGXS_AMS_PLL_CTL6r_fields[] = 201 { 202 /* AMS_PLL_SPARE_101_96:0:5 */ 203 PHYMOD_SYMBOL_FIELD_ENCODE(84, 5, 0), 204 /* AMS_PLL_MIX1P2CR_CTATADJ:6:10 */ 205 PHYMOD_SYMBOL_FIELD_ENCODE(73, 10, 6), 206 /* AMS_PLL_MIX1P2CR_PTATADJ:11:15 */ 207 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(74, 15, 11) 208 }; 209 static uint32_t BCMI_TSCF_XGXS_AMS_PLL_CTL7r_fields[] = 210 { 211 /* AMS_PLL_SPARE_117_112:0:5 */ 212 PHYMOD_SYMBOL_FIELD_ENCODE(85, 5, 0), 213 /* AMS_PLL_MIX3P1CR_CTATADJ:6:10 */ 214 PHYMOD_SYMBOL_FIELD_ENCODE(75, 10, 6), 215 /* AMS_PLL_MIX3P1CR_PTATADJ:11:15 */ 216 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(76, 15, 11) 217 }; 218 static uint32_t BCMI_TSCF_XGXS_AMS_PLL_STSr_fields[] = 219 { 220 /* AMS_PLL_STS:0:15 */ 221 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(87, 15, 0) 222 }; 223 static uint32_t BCMI_TSCF_XGXS_AMS_RX_CTL0r_fields[] = 224 { 225 /* AMS_RX_MASTER_DIODES_IBIAS:0:2 */ 226 PHYMOD_SYMBOL_FIELD_ENCODE(117, 2, 0), 227 /* AMS_RX_SIGDET_THRESHOLD:3:5 */ 228 PHYMOD_SYMBOL_FIELD_ENCODE(135, 5, 3), 229 /* AMS_RX_SIGDET_PWRDN:6:6 */ 230 PHYMOD_SYMBOL_FIELD_ENCODE(134, 6, 6), 231 /* AMS_RX_SIGDET_BYPASS:7:7 */ 232 PHYMOD_SYMBOL_FIELD_ENCODE(131, 7, 7), 233 /* AMS_RX_TPORT_EN:8:8 */ 234 PHYMOD_SYMBOL_FIELD_ENCODE(148, 8, 8), 235 /* AMS_RX_VGA_10G_BW:9:9 */ 236 PHYMOD_SYMBOL_FIELD_ENCODE(157, 9, 9), 237 /* AMS_RX_EQ_LZ_EN:10:10 */ 238 PHYMOD_SYMBOL_FIELD_ENCODE(115, 10, 10), 239 /* AMS_RX_DFE_HGAIN_EN:11:11 */ 240 PHYMOD_SYMBOL_FIELD_ENCODE(108, 11, 11), 241 /* AMS_RX_DC_COUPLE:12:12 */ 242 PHYMOD_SYMBOL_FIELD_ENCODE(105, 12, 12), 243 /* AMS_RX_PEAKING_FILTER_IBIAS:13:15 */ 244 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(122, 15, 13) 245 }; 246 static uint32_t BCMI_TSCF_XGXS_AMS_RX_CTL1r_fields[] = 247 { 248 /* AMS_RX_SPARE_16:0:0 */ 249 PHYMOD_SYMBOL_FIELD_ENCODE(142, 0, 0), 250 /* AMS_RX_VGA0_IBIAS:1:3 */ 251 PHYMOD_SYMBOL_FIELD_ENCODE(149, 3, 1), 252 /* AMS_RX_VGA1_IBIAS:4:6 */ 253 PHYMOD_SYMBOL_FIELD_ENCODE(151, 6, 4), 254 /* AMS_RX_VGA2_IBIAS:7:9 */ 255 PHYMOD_SYMBOL_FIELD_ENCODE(153, 9, 7), 256 /* AMS_RX_VGA3_IBIAS:10:12 */ 257 PHYMOD_SYMBOL_FIELD_ENCODE(155, 12, 10), 258 /* AMS_RX_CM_VOLTAGE_IBIAS:13:15 */ 259 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(100, 15, 13) 260 }; 261 static uint32_t BCMI_TSCF_XGXS_AMS_RX_CTL2r_fields[] = 262 { 263 /* AMS_RX_SIGDET_IBIAS:0:2 */ 264 PHYMOD_SYMBOL_FIELD_ENCODE(132, 2, 0), 265 /* AMS_RX_PHASE_INTERPOLATORS_IBIAS:3:5 */ 266 PHYMOD_SYMBOL_FIELD_ENCODE(124, 5, 3), 267 /* AMS_RX_DFE_TAP_WEIGHT_IBIAS:6:8 */ 268 PHYMOD_SYMBOL_FIELD_ENCODE(112, 8, 6), 269 /* AMS_RX_SEL_UGBW:9:10 */ 270 PHYMOD_SYMBOL_FIELD_ENCODE(129, 10, 9), 271 /* AMS_RX_SEL_TH4DFE:11:12 */ 272 PHYMOD_SYMBOL_FIELD_ENCODE(128, 12, 11), 273 /* AMS_RX_PD_CH_P1:13:13 */ 274 PHYMOD_SYMBOL_FIELD_ENCODE(121, 13, 13), 275 /* AMS_RX_SIGDET_POWER_SAVE:14:14 */ 276 PHYMOD_SYMBOL_FIELD_ENCODE(133, 14, 14), 277 /* AMS_RX_PWRDN_FTAP:15:15 */ 278 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(125, 15, 15) 279 }; 280 static uint32_t BCMI_TSCF_XGXS_AMS_RX_CTL3r_fields[] = 281 { 282 /* AMS_RX_MET_R_IBIAS:0:2 */ 283 PHYMOD_SYMBOL_FIELD_ENCODE(118, 2, 0), 284 /* AMS_RX_DLL_IBIAS:3:5 */ 285 PHYMOD_SYMBOL_FIELD_ENCODE(113, 5, 3), 286 /* AMS_RX_OFFSET_CORRECTION_IBIAS:6:8 */ 287 PHYMOD_SYMBOL_FIELD_ENCODE(119, 8, 6), 288 /* AMS_RX_DFE_SUM_BUF_IBIAS:9:11 */ 289 PHYMOD_SYMBOL_FIELD_ENCODE(111, 11, 9), 290 /* AMS_RX_DFE_SLICER_IBIAS:12:14 */ 291 PHYMOD_SYMBOL_FIELD_ENCODE(110, 14, 12), 292 /* AMS_RX_SPARE_63:15:15 */ 293 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(143, 15, 15) 294 }; 295 static uint32_t BCMI_TSCF_XGXS_AMS_RX_CTL4r_fields[] = 296 { 297 /* AMS_RX_DFE_SLICER_CAL_IBIAS:0:2 */ 298 PHYMOD_SYMBOL_FIELD_ENCODE(109, 2, 0), 299 /* AMS_RX_TBD_IBIAS:3:5 */ 300 PHYMOD_SYMBOL_FIELD_ENCODE(146, 5, 3), 301 /* AMS_RX_VGA0_RESCAL_MUX:6:10 */ 302 PHYMOD_SYMBOL_FIELD_ENCODE(150, 10, 6), 303 /* AMS_RX_VGA1_RESCAL_MUX:11:15 */ 304 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(152, 15, 11) 305 }; 306 static uint32_t BCMI_TSCF_XGXS_AMS_RX_CTL5r_fields[] = 307 { 308 /* AMS_RX_VGA2_RESCAL_MUX:0:4 */ 309 PHYMOD_SYMBOL_FIELD_ENCODE(154, 4, 0), 310 /* AMS_RX_VGA3_RESCAL_MUX:5:9 */ 311 PHYMOD_SYMBOL_FIELD_ENCODE(156, 9, 5), 312 /* AMS_RX_TERMINATION_RESISTOR_RESCAL_MUX:10:14 */ 313 PHYMOD_SYMBOL_FIELD_ENCODE(147, 14, 10), 314 /* AMS_RX_SPARE_95:15:15 */ 315 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(144, 15, 15) 316 }; 317 static uint32_t BCMI_TSCF_XGXS_AMS_RX_CTL6r_fields[] = 318 { 319 /* AMS_RX_PEAKING_FILTER_RESCAL_MUX:0:3 */ 320 PHYMOD_SYMBOL_FIELD_ENCODE(123, 3, 0), 321 /* AMS_RX_OFFSET_CORRECTION_RESCAL_MUX:4:7 */ 322 PHYMOD_SYMBOL_FIELD_ENCODE(120, 7, 4), 323 /* AMS_RX_SPARE_111_104:8:15 */ 324 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(136, 15, 8) 325 }; 326 static uint32_t BCMI_TSCF_XGXS_AMS_RX_CTL7r_fields[] = 327 { 328 /* AMS_RX_DC_OFFSET:0:6 */ 329 PHYMOD_SYMBOL_FIELD_ENCODE(106, 6, 0), 330 /* AMS_RX_FORCE_DC_OFFSET:7:7 */ 331 PHYMOD_SYMBOL_FIELD_ENCODE(116, 7, 7), 332 /* AMS_RX_DC_OFFSET_RANGE:8:8 */ 333 PHYMOD_SYMBOL_FIELD_ENCODE(107, 8, 8), 334 /* AMS_RX_RX_OFFSET_PD:9:9 */ 335 PHYMOD_SYMBOL_FIELD_ENCODE(126, 9, 9), 336 /* AMS_RX_SHORT_VGA_OUTPUT:10:10 */ 337 PHYMOD_SYMBOL_FIELD_ENCODE(130, 10, 10), 338 /* AMS_RX_SPARE_123:11:11 */ 339 PHYMOD_SYMBOL_FIELD_ENCODE(137, 11, 11), 340 /* AMS_RX_VGA_LOW_GAIN:12:13 */ 341 PHYMOD_SYMBOL_FIELD_ENCODE(158, 13, 12), 342 /* AMS_RX_VGA_STEP_MODE:14:15 */ 343 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(159, 15, 14) 344 }; 345 static uint32_t BCMI_TSCF_XGXS_AMS_RX_CTL8r_fields[] = 346 { 347 /* AMS_RX_DAC4CK_LMS:0:5 */ 348 PHYMOD_SYMBOL_FIELD_ENCODE(103, 5, 0), 349 /* AMS_RX_SPARE_135_134:6:7 */ 350 PHYMOD_SYMBOL_FIELD_ENCODE(138, 7, 6), 351 /* AMS_RX_DAC4CK_PHS:8:13 */ 352 PHYMOD_SYMBOL_FIELD_ENCODE(104, 13, 8), 353 /* AMS_RX_SPARE_143_142:14:15 */ 354 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(139, 15, 14) 355 }; 356 static uint32_t BCMI_TSCF_XGXS_AMS_RX_CTL9r_fields[] = 357 { 358 /* AMS_RX_DAC4CK_DAT:0:5 */ 359 PHYMOD_SYMBOL_FIELD_ENCODE(102, 5, 0), 360 /* AMS_RX_SPARE_151_150:6:7 */ 361 PHYMOD_SYMBOL_FIELD_ENCODE(140, 7, 6), 362 /* AMS_RX_CLK_BW_CTRL:8:9 */ 363 PHYMOD_SYMBOL_FIELD_ENCODE(99, 9, 8), 364 /* AMS_RX_EN_TAP9DELAY:10:10 */ 365 PHYMOD_SYMBOL_FIELD_ENCODE(114, 10, 10), 366 /* AMS_RX_SEL_D2CLP:11:11 */ 367 PHYMOD_SYMBOL_FIELD_ENCODE(127, 11, 11), 368 /* AMS_RX_D2C_CLKBUF_IBIAS:12:14 */ 369 PHYMOD_SYMBOL_FIELD_ENCODE(101, 14, 12), 370 /* AMS_RX_SPARE_159:15:15 */ 371 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(141, 15, 15) 372 }; 373 static uint32_t BCMI_TSCF_XGXS_AMS_RX_STSr_fields[] = 374 { 375 /* AMS_RX_STS:0:15 */ 376 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(145, 15, 0) 377 }; 378 static uint32_t BCMI_TSCF_XGXS_AMS_TX_CTL0r_fields[] = 379 { 380 /* AMS_TX_SPARE_0:0:0 */ 381 PHYMOD_SYMBOL_FIELD_ENCODE(176, 0, 0), 382 /* AMS_TX_SPARE_3_1:1:3 */ 383 PHYMOD_SYMBOL_FIELD_ENCODE(179, 3, 1), 384 /* AMS_TX_TEST_DATA:4:5 */ 385 PHYMOD_SYMBOL_FIELD_ENCODE(182, 5, 4), 386 /* AMS_TX_TICKSEL:6:7 */ 387 PHYMOD_SYMBOL_FIELD_ENCODE(183, 7, 6), 388 /* AMS_TX_VDDR_BGB:8:8 */ 389 PHYMOD_SYMBOL_FIELD_ENCODE(184, 8, 8), 390 /* AMS_TX_DCC_SEL:9:9 */ 391 PHYMOD_SYMBOL_FIELD_ENCODE(164, 9, 9), 392 /* AMS_TX_DCC_DIS:10:10 */ 393 PHYMOD_SYMBOL_FIELD_ENCODE(163, 10, 10), 394 /* AMS_TX_CAL_OFF:11:11 */ 395 PHYMOD_SYMBOL_FIELD_ENCODE(162, 11, 11), 396 /* AMS_TX_CAL_AUX:12:15 */ 397 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(161, 15, 12) 398 }; 399 static uint32_t BCMI_TSCF_XGXS_AMS_TX_CTL1r_fields[] = 400 { 401 /* AMS_TX_IBIAS:0:2 */ 402 PHYMOD_SYMBOL_FIELD_ENCODE(167, 2, 0), 403 /* AMS_TX_SPARE_21_19:3:5 */ 404 PHYMOD_SYMBOL_FIELD_ENCODE(177, 5, 3), 405 /* AMS_TX_ICML:6:8 */ 406 PHYMOD_SYMBOL_FIELD_ENCODE(168, 8, 6), 407 /* AMS_TX_ILDO:9:11 */ 408 PHYMOD_SYMBOL_FIELD_ENCODE(169, 11, 9), 409 /* AMS_TX_LDO_VREF:12:13 */ 410 PHYMOD_SYMBOL_FIELD_ENCODE(170, 13, 12), 411 /* AMS_TX_SEL_EMPH_MODE:14:14 */ 412 PHYMOD_SYMBOL_FIELD_ENCODE(173, 14, 14), 413 /* AMS_TX_SPARE_31:15:15 */ 414 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(178, 15, 15) 415 }; 416 static uint32_t BCMI_TSCF_XGXS_AMS_TX_CTL2r_fields[] = 417 { 418 /* AMS_TX_AMP_CTL:0:3 */ 419 PHYMOD_SYMBOL_FIELD_ENCODE(160, 3, 0), 420 /* AMS_TX_POST3_COEF:4:6 */ 421 PHYMOD_SYMBOL_FIELD_ENCODE(172, 6, 4), 422 /* AMS_TX_SIGN_POST3:7:7 */ 423 PHYMOD_SYMBOL_FIELD_ENCODE(175, 7, 7), 424 /* AMS_TX_POST2_COEF:8:11 */ 425 PHYMOD_SYMBOL_FIELD_ENCODE(171, 11, 8), 426 /* AMS_TX_SIGN_POST2:12:12 */ 427 PHYMOD_SYMBOL_FIELD_ENCODE(174, 12, 12), 428 /* AMS_TX_DRIVERMODE:13:14 */ 429 PHYMOD_SYMBOL_FIELD_ENCODE(165, 14, 13), 430 /* AMS_TX_ELEC_IDLE_AUX:15:15 */ 431 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(166, 15, 15) 432 }; 433 static uint32_t BCMI_TSCF_XGXS_AMS_TX_CTL3r_fields[] = 434 { 435 /* AMS_TX_SPARE_63_48:0:15 */ 436 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(180, 15, 0) 437 }; 438 static uint32_t BCMI_TSCF_XGXS_AMS_TX_STSr_fields[] = 439 { 440 /* AMS_TX_STS:0:15 */ 441 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(181, 15, 0) 442 }; 443 static uint32_t BCMI_TSCF_XGXS_AN_X1_BAM_SPD_PRI0r_fields[] = 444 { 445 /* AN_PRIORITY_100G_CR4:0:1 */ 446 PHYMOD_SYMBOL_FIELD_ENCODE(231, 1, 0), 447 /* AN_PRIORITY_100G_HG2_CR4:2:3 */ 448 PHYMOD_SYMBOL_FIELD_ENCODE(232, 3, 2), 449 /* AN_PRIORITY_100G_KR4:4:5 */ 450 PHYMOD_SYMBOL_FIELD_ENCODE(234, 5, 4), 451 /* AN_PRIORITY_100G_HG2_KR4:6:7 */ 452 PHYMOD_SYMBOL_FIELD_ENCODE(233, 7, 6), 453 /* AN_PRIORITY_40G_CR4:8:9 */ 454 PHYMOD_SYMBOL_FIELD_ENCODE(251, 9, 8), 455 /* AN_PRIORITY_40G_HG2_CR4:10:11 */ 456 PHYMOD_SYMBOL_FIELD_ENCODE(253, 11, 10), 457 /* AN_PRIORITY_40G_KR4:12:13 */ 458 PHYMOD_SYMBOL_FIELD_ENCODE(257, 13, 12), 459 /* AN_PRIORITY_40G_HG2_KR4:14:15 */ 460 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(255, 15, 14) 461 }; 462 static uint32_t BCMI_TSCF_XGXS_AN_X1_BAM_SPD_PRI1r_fields[] = 463 { 464 /* AN_PRIORITY_50G_CR4:0:1 */ 465 PHYMOD_SYMBOL_FIELD_ENCODE(259, 1, 0), 466 /* AN_PRIORITY_50G_HG2_CR4:2:3 */ 467 PHYMOD_SYMBOL_FIELD_ENCODE(261, 3, 2), 468 /* AN_PRIORITY_50G_KR4:4:5 */ 469 PHYMOD_SYMBOL_FIELD_ENCODE(265, 5, 4), 470 /* AN_PRIORITY_50G_HG2_KR4:6:7 */ 471 PHYMOD_SYMBOL_FIELD_ENCODE(263, 7, 6), 472 /* AN_PRIORITY_50G_CR2:8:9 */ 473 PHYMOD_SYMBOL_FIELD_ENCODE(258, 9, 8), 474 /* AN_PRIORITY_50G_HG2_CR2:10:11 */ 475 PHYMOD_SYMBOL_FIELD_ENCODE(260, 11, 10), 476 /* AN_PRIORITY_50G_KR2:12:13 */ 477 PHYMOD_SYMBOL_FIELD_ENCODE(264, 13, 12), 478 /* AN_PRIORITY_50G_HG2_KR2:14:15 */ 479 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(262, 15, 14) 480 }; 481 static uint32_t BCMI_TSCF_XGXS_AN_X1_BAM_SPD_PRI2r_fields[] = 482 { 483 /* AN_PRIORITY_40G_CR2:0:1 */ 484 PHYMOD_SYMBOL_FIELD_ENCODE(250, 1, 0), 485 /* AN_PRIORITY_40G_HG2_CR2:2:3 */ 486 PHYMOD_SYMBOL_FIELD_ENCODE(252, 3, 2), 487 /* AN_PRIORITY_40G_KR2:4:5 */ 488 PHYMOD_SYMBOL_FIELD_ENCODE(256, 5, 4), 489 /* AN_PRIORITY_40G_HG2_KR2:6:7 */ 490 PHYMOD_SYMBOL_FIELD_ENCODE(254, 7, 6), 491 /* AN_PRIORITY_25G_CR1:8:9 */ 492 PHYMOD_SYMBOL_FIELD_ENCODE(246, 9, 8), 493 /* AN_PRIORITY_25G_HG2_CR1:10:11 */ 494 PHYMOD_SYMBOL_FIELD_ENCODE(247, 11, 10), 495 /* AN_PRIORITY_25G_KR1:12:13 */ 496 PHYMOD_SYMBOL_FIELD_ENCODE(249, 13, 12), 497 /* AN_PRIORITY_25G_HG2_KR1:14:15 */ 498 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(248, 15, 14) 499 }; 500 static uint32_t BCMI_TSCF_XGXS_AN_X1_BAM_SPD_PRI3r_fields[] = 501 { 502 /* AN_PRIORITY_20G_CR1:0:1 */ 503 PHYMOD_SYMBOL_FIELD_ENCODE(238, 1, 0), 504 /* AN_PRIORITY_20G_HG2_CR1:2:3 */ 505 PHYMOD_SYMBOL_FIELD_ENCODE(240, 3, 2), 506 /* AN_PRIORITY_20G_KR1:4:5 */ 507 PHYMOD_SYMBOL_FIELD_ENCODE(244, 5, 4), 508 /* AN_PRIORITY_20G_HG2_KR1:6:7 */ 509 PHYMOD_SYMBOL_FIELD_ENCODE(242, 7, 6), 510 /* AN_PRIORITY_20G_CR2:8:9 */ 511 PHYMOD_SYMBOL_FIELD_ENCODE(239, 9, 8), 512 /* AN_PRIORITY_20G_HG2_CR2:10:11 */ 513 PHYMOD_SYMBOL_FIELD_ENCODE(241, 11, 10), 514 /* AN_PRIORITY_20G_KR2:12:13 */ 515 PHYMOD_SYMBOL_FIELD_ENCODE(245, 13, 12), 516 /* AN_PRIORITY_20G_HG2_KR2:14:15 */ 517 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(243, 15, 14) 518 }; 519 static uint32_t BCMI_TSCF_XGXS_AN_X1_BAM_SPD_PRI4r_fields[] = 520 { 521 /* AN_PRIORITY_10G_KR1:0:1 */ 522 PHYMOD_SYMBOL_FIELD_ENCODE(236, 1, 0), 523 /* AN_PRIORITY_10G_HG2_KR1:2:3 */ 524 PHYMOD_SYMBOL_FIELD_ENCODE(235, 3, 2), 525 /* AN_PRIORITY_1G_KX1:4:5 */ 526 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(237, 5, 4) 527 }; 528 static uint32_t BCMI_TSCF_XGXS_AN_X1_CL73_BRK_LNKr_fields[] = 529 { 530 /* CL73_BREAK_TIMER_PERIOD:0:15 */ 531 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(417, 15, 0) 532 }; 533 static uint32_t BCMI_TSCF_XGXS_AN_X1_CL73_DME_LOCKr_fields[] = 534 { 535 /* PD_DME_LOCK_TIMER_PERIOD:0:15 */ 536 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(968, 15, 0) 537 }; 538 static uint32_t BCMI_TSCF_XGXS_AN_X1_CL73_ERRr_fields[] = 539 { 540 /* CL73_ERROR_TIMER_PERIOD:0:15 */ 541 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(419, 15, 0) 542 }; 543 static uint32_t BCMI_TSCF_XGXS_AN_X1_DME_PAGE_TMR_TYPEr_fields[] = 544 { 545 /* CL73_PAGE_TEST_MIN_TIMER:0:6 */ 546 PHYMOD_SYMBOL_FIELD_ENCODE(425, 6, 0), 547 /* CL73_PAGE_TEST_MAX_TIMER:7:13 */ 548 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(424, 13, 7) 549 }; 550 static uint32_t BCMI_TSCF_XGXS_AN_X1_IGNORE_LNK_TMRr_fields[] = 551 { 552 /* IGNORE_LINK_TIMER_PERIOD:0:15 */ 553 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(744, 15, 0) 554 }; 555 static uint32_t BCMI_TSCF_XGXS_AN_X1_LNK_FAIL_INHBT_TMR_CL72r_fields[] = 556 { 557 /* LINK_FAIL_INHIBIT_TIMER_CL72_PERIOD:0:15 */ 558 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(778, 15, 0) 559 }; 560 static uint32_t BCMI_TSCF_XGXS_AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72r_fields[] = 561 { 562 /* LINK_FAIL_INHIBIT_TIMER_NCL72_PERIOD:0:15 */ 563 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(779, 15, 0) 564 }; 565 static uint32_t BCMI_TSCF_XGXS_AN_X1_OUI_LWRr_fields[] = 566 { 567 /* OUI_LOWER_DATA:0:15 */ 568 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(943, 15, 0) 569 }; 570 static uint32_t BCMI_TSCF_XGXS_AN_X1_OUI_UPRr_fields[] = 571 { 572 /* OUI_UPPER_DATA:0:7 */ 573 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(944, 7, 0) 574 }; 575 static uint32_t BCMI_TSCF_XGXS_AN_X1_PD_SD_TMRr_fields[] = 576 { 577 /* PD_SD_TIMER_PERIOD:0:15 */ 578 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(971, 15, 0) 579 }; 580 static uint32_t BCMI_TSCF_XGXS_AN_X4_AN_ABIL_RESOLUTION_STSr_fields[] = 581 { 582 /* AN_HCD_CL72:0:0 */ 583 PHYMOD_SYMBOL_FIELD_ENCODE(221, 0, 0), 584 /* AN_HCD_FEC:1:1 */ 585 PHYMOD_SYMBOL_FIELD_ENCODE(223, 1, 1), 586 /* AN_HCD_SPEED:2:9 */ 587 PHYMOD_SYMBOL_FIELD_ENCODE(226, 9, 2), 588 /* AN_HCD_PAUSE:10:11 */ 589 PHYMOD_SYMBOL_FIELD_ENCODE(224, 11, 10), 590 /* AN_HCD_DUPLEX:12:12 */ 591 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(222, 12, 12) 592 }; 593 static uint32_t BCMI_TSCF_XGXS_AN_X4_AN_MISC_STSr_fields[] = 594 { 595 /* PD_IN_PROGRESS:1:1 */ 596 PHYMOD_SYMBOL_FIELD_ENCODE(969, 1, 1), 597 /* AN_FAIL_COUNT:2:5 */ 598 PHYMOD_SYMBOL_FIELD_ENCODE(216, 5, 2), 599 /* AN_ACTIVE:6:6 */ 600 PHYMOD_SYMBOL_FIELD_ENCODE(212, 6, 6), 601 /* PD_COMPLETED:7:7 */ 602 PHYMOD_SYMBOL_FIELD_ENCODE(967, 7, 7), 603 /* SPEED_FORCE:8:8 */ 604 PHYMOD_SYMBOL_FIELD_ENCODE(1317, 8, 8), 605 /* AN_RETRY_COUNT:9:14 */ 606 PHYMOD_SYMBOL_FIELD_ENCODE(266, 14, 9), 607 /* AN_COMPLETE:15:15 */ 608 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(213, 15, 15) 609 }; 610 static uint32_t BCMI_TSCF_XGXS_AN_X4_CL73_CFGr_fields[] = 611 { 612 /* CL73_AN_RESTART:0:0 */ 613 PHYMOD_SYMBOL_FIELD_ENCODE(413, 0, 0), 614 /* AD_TO_CL73_EN:2:2 */ 615 PHYMOD_SYMBOL_FIELD_ENCODE(3, 2, 2), 616 /* BAM_TO_HPAM_AD_EN:3:3 */ 617 PHYMOD_SYMBOL_FIELD_ENCODE(281, 3, 3), 618 /* CL73_NONCE_MATCH_VAL:5:5 */ 619 PHYMOD_SYMBOL_FIELD_ENCODE(423, 5, 5), 620 /* CL73_NONCE_MATCH_OVER:6:6 */ 621 PHYMOD_SYMBOL_FIELD_ENCODE(422, 6, 6), 622 /* CL73_ENABLE:8:8 */ 623 PHYMOD_SYMBOL_FIELD_ENCODE(418, 8, 8), 624 /* CL73_HPAM_ENABLE:9:9 */ 625 PHYMOD_SYMBOL_FIELD_ENCODE(421, 9, 9), 626 /* CL73_BAM_ENABLE:10:10 */ 627 PHYMOD_SYMBOL_FIELD_ENCODE(415, 10, 10), 628 /* NUM_ADVERTISED_LANES:11:12 */ 629 PHYMOD_SYMBOL_FIELD_ENCODE(922, 12, 11), 630 /* DISABLE_REMOTE_FAULT:13:13 */ 631 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(625, 13, 13) 632 }; 633 static uint32_t BCMI_TSCF_XGXS_AN_X4_CL73_CTLSr_fields[] = 634 { 635 /* PD_KX_EN:1:1 */ 636 PHYMOD_SYMBOL_FIELD_ENCODE(970, 1, 1), 637 /* AN_GOOD_TRAP:2:2 */ 638 PHYMOD_SYMBOL_FIELD_ENCODE(220, 2, 2), 639 /* AN_GOOD_CHECK_TRAP:3:3 */ 640 PHYMOD_SYMBOL_FIELD_ENCODE(219, 3, 3), 641 /* LINKFAILTIMER_DIS:4:4 */ 642 PHYMOD_SYMBOL_FIELD_ENCODE(777, 4, 4), 643 /* LINKFAILTIMERQUAL_EN:5:5 */ 644 PHYMOD_SYMBOL_FIELD_ENCODE(776, 5, 5), 645 /* AN_FAIL_COUNT_LIMIT:6:9 */ 646 PHYMOD_SYMBOL_FIELD_ENCODE(217, 9, 6), 647 /* AN_OUI_OVERRIDE_HPAM_DET:12:12 */ 648 PHYMOD_SYMBOL_FIELD_ENCODE(230, 12, 12), 649 /* AN_OUI_OVERRIDE_HPAM_ADV:13:13 */ 650 PHYMOD_SYMBOL_FIELD_ENCODE(229, 13, 13), 651 /* AN_OUI_OVERRIDE_BAM73_DET:14:14 */ 652 PHYMOD_SYMBOL_FIELD_ENCODE(228, 14, 14), 653 /* AN_OUI_OVERRIDE_BAM73_ADV:15:15 */ 654 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(227, 15, 15) 655 }; 656 static uint32_t BCMI_TSCF_XGXS_AN_X4_LD_BAM_ABILr_fields[] = 657 { 658 /* CL73_BAM_CODE:0:8 */ 659 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(414, 8, 0) 660 }; 661 static uint32_t BCMI_TSCF_XGXS_AN_X4_LD_BASE_ABIL0r_fields[] = 662 { 663 /* CL73_BASE_SELECTOR:0:4 */ 664 PHYMOD_SYMBOL_FIELD_ENCODE(416, 4, 0), 665 /* TX_NONCE:5:9 */ 666 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1446, 9, 5) 667 }; 668 static uint32_t BCMI_TSCF_XGXS_AN_X4_LD_BASE_ABIL1r_fields[] = 669 { 670 /* BASE_10G_KR1:0:0 */ 671 PHYMOD_SYMBOL_FIELD_ENCODE(284, 0, 0), 672 /* BASE_40G_KR4:1:1 */ 673 PHYMOD_SYMBOL_FIELD_ENCODE(287, 1, 1), 674 /* BASE_40G_CR4:2:2 */ 675 PHYMOD_SYMBOL_FIELD_ENCODE(286, 2, 2), 676 /* BASE_100G_KR4:3:3 */ 677 PHYMOD_SYMBOL_FIELD_ENCODE(283, 3, 3), 678 /* BASE_100G_CR4:4:4 */ 679 PHYMOD_SYMBOL_FIELD_ENCODE(282, 4, 4), 680 /* BASE_1G_KX1:5:5 */ 681 PHYMOD_SYMBOL_FIELD_ENCODE(285, 5, 5), 682 /* CL73_PAUSE:6:7 */ 683 PHYMOD_SYMBOL_FIELD_ENCODE(426, 7, 6), 684 /* FEC_REQ:8:9 */ 685 PHYMOD_SYMBOL_FIELD_ENCODE(712, 9, 8), 686 /* NEXT_PAGE:10:10 */ 687 PHYMOD_SYMBOL_FIELD_ENCODE(919, 10, 10), 688 /* CL73_REMOTE_FAULT:11:11 */ 689 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(427, 11, 11) 690 }; 691 static uint32_t BCMI_TSCF_XGXS_AN_X4_LD_CTLr_fields[] = 692 { 693 /* AN_HCD_RES_DISABLE:0:0 */ 694 PHYMOD_SYMBOL_FIELD_ENCODE(225, 0, 0), 695 /* AN_TYPE_SW:1:1 */ 696 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(267, 1, 1) 697 }; 698 static uint32_t BCMI_TSCF_XGXS_AN_X4_LD_PAGE0r_fields[] = 699 { 700 /* LD_PAGE_0:0:15 */ 701 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(773, 15, 0) 702 }; 703 static uint32_t BCMI_TSCF_XGXS_AN_X4_LD_PAGE1r_fields[] = 704 { 705 /* LD_PAGE_1:0:15 */ 706 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(774, 15, 0) 707 }; 708 static uint32_t BCMI_TSCF_XGXS_AN_X4_LD_PAGE2r_fields[] = 709 { 710 /* LD_PAGE_2:0:15 */ 711 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(775, 15, 0) 712 }; 713 static uint32_t BCMI_TSCF_XGXS_AN_X4_LD_UP1_ABIL0r_fields[] = 714 { 715 /* BAM_20G_KR2:0:0 */ 716 PHYMOD_SYMBOL_FIELD_ENCODE(271, 0, 0), 717 /* BAM_20G_CR2:1:1 */ 718 PHYMOD_SYMBOL_FIELD_ENCODE(269, 1, 1), 719 /* BAM_40G_KR2:2:2 */ 720 PHYMOD_SYMBOL_FIELD_ENCODE(275, 2, 2), 721 /* BAM_40G_CR2:3:3 */ 722 PHYMOD_SYMBOL_FIELD_ENCODE(274, 3, 3), 723 /* BAM_50G_KR2:6:6 */ 724 PHYMOD_SYMBOL_FIELD_ENCODE(278, 6, 6), 725 /* BAM_50G_CR2:7:7 */ 726 PHYMOD_SYMBOL_FIELD_ENCODE(276, 7, 7), 727 /* BAM_50G_KR4:8:8 */ 728 PHYMOD_SYMBOL_FIELD_ENCODE(279, 8, 8), 729 /* BAM_50G_CR4:9:9 */ 730 PHYMOD_SYMBOL_FIELD_ENCODE(277, 9, 9), 731 /* BAM_HG2:15:15 */ 732 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(280, 15, 15) 733 }; 734 static uint32_t BCMI_TSCF_XGXS_AN_X4_LD_UP1_ABIL1r_fields[] = 735 { 736 /* BAM_20G_KR1:1:1 */ 737 PHYMOD_SYMBOL_FIELD_ENCODE(270, 1, 1), 738 /* BAM_20G_CR1:2:2 */ 739 PHYMOD_SYMBOL_FIELD_ENCODE(268, 2, 2), 740 /* BAM_25G_KR1:3:3 */ 741 PHYMOD_SYMBOL_FIELD_ENCODE(273, 3, 3), 742 /* BAM_25G_CR1:4:4 */ 743 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(272, 4, 4) 744 }; 745 static uint32_t BCMI_TSCF_XGXS_AN_X4_LP_BASE1r_fields[] = 746 { 747 /* LP_BASE1:0:15 */ 748 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(819, 15, 0) 749 }; 750 static uint32_t BCMI_TSCF_XGXS_AN_X4_LP_BASE2r_fields[] = 751 { 752 /* LP_BASE2:0:15 */ 753 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(820, 15, 0) 754 }; 755 static uint32_t BCMI_TSCF_XGXS_AN_X4_LP_BASE3r_fields[] = 756 { 757 /* LP_BASE3:0:15 */ 758 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(821, 15, 0) 759 }; 760 static uint32_t BCMI_TSCF_XGXS_AN_X4_LP_OUI_UP1r_fields[] = 761 { 762 /* LP_OUI_UP1:0:15 */ 763 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(822, 15, 0) 764 }; 765 static uint32_t BCMI_TSCF_XGXS_AN_X4_LP_OUI_UP2r_fields[] = 766 { 767 /* LP_OUI_UP2:0:15 */ 768 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(823, 15, 0) 769 }; 770 static uint32_t BCMI_TSCF_XGXS_AN_X4_LP_OUI_UP3r_fields[] = 771 { 772 /* LP_OUI_UP3:0:15 */ 773 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(824, 15, 0) 774 }; 775 static uint32_t BCMI_TSCF_XGXS_AN_X4_LP_OUI_UP4r_fields[] = 776 { 777 /* LP_OUI_UP4:0:15 */ 778 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(825, 15, 0) 779 }; 780 static uint32_t BCMI_TSCF_XGXS_AN_X4_LP_OUI_UP5r_fields[] = 781 { 782 /* LP_OUI_UP5:0:10 */ 783 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(826, 10, 0) 784 }; 785 static uint32_t BCMI_TSCF_XGXS_AN_X4_LP_PAGE0r_fields[] = 786 { 787 /* LP_PAGE_0:0:15 */ 788 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(827, 15, 0) 789 }; 790 static uint32_t BCMI_TSCF_XGXS_AN_X4_LP_PAGE1r_fields[] = 791 { 792 /* LP_PAGE_1:0:15 */ 793 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(828, 15, 0) 794 }; 795 static uint32_t BCMI_TSCF_XGXS_AN_X4_LP_PAGE2r_fields[] = 796 { 797 /* LP_PAGE_2:0:15 */ 798 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(829, 15, 0) 799 }; 800 static uint32_t BCMI_TSCF_XGXS_AN_X4_PSEQ_RFr_fields[] = 801 { 802 /* REMOTE_FAULT_SET:0:0 */ 803 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1067, 0, 0) 804 }; 805 static uint32_t BCMI_TSCF_XGXS_AN_X4_PSEQ_STSr_fields[] = 806 { 807 /* HP_MODE:0:0 */ 808 PHYMOD_SYMBOL_FIELD_ENCODE(740, 0, 0), 809 /* RX_BP:1:1 */ 810 PHYMOD_SYMBOL_FIELD_ENCODE(1216, 1, 1), 811 /* RX_NP:2:2 */ 812 PHYMOD_SYMBOL_FIELD_ENCODE(1239, 2, 2), 813 /* RX_MP_NULL:3:3 */ 814 PHYMOD_SYMBOL_FIELD_ENCODE(1236, 3, 3), 815 /* RX_MP_OUI:4:4 */ 816 PHYMOD_SYMBOL_FIELD_ENCODE(1237, 4, 4), 817 /* RX_MP_MISMATCH:5:5 */ 818 PHYMOD_SYMBOL_FIELD_ENCODE(1235, 5, 5), 819 /* RX_UP_OUI_MISMATCH:6:6 */ 820 PHYMOD_SYMBOL_FIELD_ENCODE(1267, 6, 6), 821 /* RX_UP_OUI_MATCH:7:7 */ 822 PHYMOD_SYMBOL_FIELD_ENCODE(1266, 7, 7), 823 /* RX_INVALID_SEQ:8:8 */ 824 PHYMOD_SYMBOL_FIELD_ENCODE(1228, 8, 8), 825 /* RX_NP_TOGGLE_ERR:9:9 */ 826 PHYMOD_SYMBOL_FIELD_ENCODE(1240, 9, 9), 827 /* CL73_AN_COMPLETE:10:10 */ 828 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(412, 10, 10) 829 }; 830 static uint32_t BCMI_TSCF_XGXS_AN_X4_PXNG_STSr_fields[] = 831 { 832 /* CONSISTENCY_MISMATCH:0:0 */ 833 PHYMOD_SYMBOL_FIELD_ENCODE(512, 0, 0), 834 /* COMPLETE_ACK:1:1 */ 835 PHYMOD_SYMBOL_FIELD_ENCODE(511, 1, 1), 836 /* ACK_DETECT:2:2 */ 837 PHYMOD_SYMBOL_FIELD_ENCODE(1, 2, 2), 838 /* ABILITY_DETECT:3:3 */ 839 PHYMOD_SYMBOL_FIELD_ENCODE(0, 3, 3), 840 /* AN_ENABLE:4:4 */ 841 PHYMOD_SYMBOL_FIELD_ENCODE(215, 4, 4), 842 /* ERROR_STATE:5:5 */ 843 PHYMOD_SYMBOL_FIELD_ENCODE(672, 5, 5), 844 /* TRANSMIT_DISABLE:6:6 */ 845 PHYMOD_SYMBOL_FIELD_ENCODE(1358, 6, 6), 846 /* NEXT_PAGE_WAIT:7:7 */ 847 PHYMOD_SYMBOL_FIELD_ENCODE(920, 7, 7), 848 /* AN_GOOD_CHECK:8:8 */ 849 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(218, 8, 8) 850 }; 851 static uint32_t BCMI_TSCF_XGXS_AN_X4_RES_ERRr_fields[] = 852 { 853 /* RESOLUTION_ERROR:0:0 */ 854 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1072, 0, 0) 855 }; 856 static uint32_t BCMI_TSCF_XGXS_AN_X4_R_CL73_STSr_fields[] = 857 { 858 /* DME_STATE:0:1 */ 859 PHYMOD_SYMBOL_FIELD_ENCODE(630, 1, 0), 860 /* DME_PAGE:2:2 */ 861 PHYMOD_SYMBOL_FIELD_ENCODE(629, 2, 2), 862 /* DME_MV_PAIR:3:3 */ 863 PHYMOD_SYMBOL_FIELD_ENCODE(628, 3, 3), 864 /* CLK_TRANS_MISS:4:4 */ 865 PHYMOD_SYMBOL_FIELD_ENCODE(503, 4, 4), 866 /* PAGE_TOO_LONG:5:5 */ 867 PHYMOD_SYMBOL_FIELD_ENCODE(945, 5, 5), 868 /* PAGE_TOO_SHORT:6:6 */ 869 PHYMOD_SYMBOL_FIELD_ENCODE(946, 6, 6), 870 /* PULSE_TOO_LONG:7:7 */ 871 PHYMOD_SYMBOL_FIELD_ENCODE(1056, 7, 7), 872 /* PULSE_TOO_MODERATE:8:8 */ 873 PHYMOD_SYMBOL_FIELD_ENCODE(1057, 8, 8), 874 /* PULSE_TOO_SHORT:9:9 */ 875 PHYMOD_SYMBOL_FIELD_ENCODE(1058, 9, 9), 876 /* DME_LOCKED:10:10 */ 877 PHYMOD_SYMBOL_FIELD_ENCODE(627, 10, 10), 878 /* CL73_FIFO_FULL:11:11 */ 879 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(420, 11, 11) 880 }; 881 static uint32_t BCMI_TSCF_XGXS_AN_X4_SW_CTL_STSr_fields[] = 882 { 883 /* SW_LP_PAGE_PENDING:0:0 */ 884 PHYMOD_SYMBOL_FIELD_ENCODE(1322, 0, 0), 885 /* SW_LD_PAGE_PENDING:1:1 */ 886 PHYMOD_SYMBOL_FIELD_ENCODE(1321, 1, 1), 887 /* AN_COMPLETED_SW:2:2 */ 888 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(214, 2, 2) 889 }; 890 static uint32_t BCMI_TSCF_XGXS_AN_X4_TLA_SEQUENCER_STSr_fields[] = 891 { 892 /* TLA_SEQ_FSM_STATUS:0:15 */ 893 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1355, 15, 0) 894 }; 895 static uint32_t BCMI_TSCF_XGXS_AN_X4_UNEXP_PAGEr_fields[] = 896 { 897 /* RX_UNEXPECTED_PAGE:0:15 */ 898 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1265, 15, 0) 899 }; 900 static uint32_t BCMI_TSCF_XGXS_CKRST_CLK_N_RST_DBG_CTLr_fields[] = 901 { 902 /* LN_RX_S_CLKGATE_FRC_ON:0:0 */ 903 PHYMOD_SYMBOL_FIELD_ENCODE(791, 0, 0), 904 /* LN_RX_S_COMCLK_SEL:1:1 */ 905 PHYMOD_SYMBOL_FIELD_ENCODE(793, 1, 1), 906 /* LN_RX_S_COMCLK_FRC_ON:2:2 */ 907 PHYMOD_SYMBOL_FIELD_ENCODE(792, 2, 2), 908 /* PMD_RX_CLK_VLD_FRC:3:3 */ 909 PHYMOD_SYMBOL_FIELD_ENCODE(1012, 3, 3), 910 /* PMD_RX_CLK_VLD_FRC_VAL:4:4 */ 911 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1013, 4, 4) 912 }; 913 static uint32_t BCMI_TSCF_XGXS_CKRST_LN_AFE_RST_PWRDWN_CTLr_fields[] = 914 { 915 /* AFE_RX_PWRDN_FRC:0:0 */ 916 PHYMOD_SYMBOL_FIELD_ENCODE(4, 0, 0), 917 /* AFE_RX_PWRDN_FRC_VAL:1:1 */ 918 PHYMOD_SYMBOL_FIELD_ENCODE(5, 1, 1), 919 /* AFE_RX_RESET_FRC:2:2 */ 920 PHYMOD_SYMBOL_FIELD_ENCODE(8, 2, 2), 921 /* AFE_RX_RESET_FRC_VAL:3:3 */ 922 PHYMOD_SYMBOL_FIELD_ENCODE(9, 3, 3), 923 /* AFE_TX_PWRDN_FRC:4:4 */ 924 PHYMOD_SYMBOL_FIELD_ENCODE(16, 4, 4), 925 /* AFE_TX_PWRDN_FRC_VAL:5:5 */ 926 PHYMOD_SYMBOL_FIELD_ENCODE(17, 5, 5), 927 /* AFE_TX_RESET_FRC:6:6 */ 928 PHYMOD_SYMBOL_FIELD_ENCODE(18, 6, 6), 929 /* AFE_TX_RESET_FRC_VAL:7:7 */ 930 PHYMOD_SYMBOL_FIELD_ENCODE(19, 7, 7), 931 /* AFE_RX_RCLK20_PWRDN_FRC:8:8 */ 932 PHYMOD_SYMBOL_FIELD_ENCODE(6, 8, 8), 933 /* AFE_RX_RCLK20_PWRDN_FRC_VAL:9:9 */ 934 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(7, 9, 9) 935 }; 936 static uint32_t BCMI_TSCF_XGXS_CKRST_LN_CLK_RST_N_PWRDWN_CTLr_fields[] = 937 { 938 /* LN_DP_S_RSTB:1:1 */ 939 PHYMOD_SYMBOL_FIELD_ENCODE(787, 1, 1), 940 /* LN_RX_S_PWRDN:2:2 */ 941 PHYMOD_SYMBOL_FIELD_ENCODE(794, 2, 2), 942 /* LN_TX_S_PWRDN:3:3 */ 943 PHYMOD_SYMBOL_FIELD_ENCODE(799, 3, 3), 944 /* AFE_SIGDET_PWRDN:4:4 */ 945 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(10, 4, 4) 946 }; 947 static uint32_t BCMI_TSCF_XGXS_CKRST_LN_DBG_RST_CTLr_fields[] = 948 { 949 /* LN_RX_S_RSTB:0:0 */ 950 PHYMOD_SYMBOL_FIELD_ENCODE(795, 0, 0), 951 /* LN_RX_DP_S_RSTB:1:1 */ 952 PHYMOD_SYMBOL_FIELD_ENCODE(789, 1, 1), 953 /* SIGDET_DP_RSTB_EN:2:2 */ 954 PHYMOD_SYMBOL_FIELD_ENCODE(1293, 2, 2), 955 /* LN_TX_S_RSTB:8:8 */ 956 PHYMOD_SYMBOL_FIELD_ENCODE(800, 8, 8), 957 /* LN_TX_DP_S_RSTB:9:9 */ 958 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(797, 9, 9) 959 }; 960 static uint32_t BCMI_TSCF_XGXS_CKRST_LN_DP_RST_ST_STSr_fields[] = 961 { 962 /* LANE_DP_RESET_STATE:0:2 */ 963 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(765, 2, 0) 964 }; 965 static uint32_t BCMI_TSCF_XGXS_CKRST_LN_MASKr_fields[] = 966 { 967 /* LANE_MULTICAST_MASK_CONTROL:0:0 */ 968 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(768, 0, 0) 969 }; 970 static uint32_t BCMI_TSCF_XGXS_CKRST_LN_RST_N_PWRDN_PIN_KILL_CTLr_fields[] = 971 { 972 /* PMD_LN_H_RSTB_PKILL:0:0 */ 973 PHYMOD_SYMBOL_FIELD_ENCODE(1006, 0, 0), 974 /* PMD_LN_DP_H_RSTB_PKILL:1:1 */ 975 PHYMOD_SYMBOL_FIELD_ENCODE(1005, 1, 1), 976 /* PMD_LN_RX_H_PWRDN_PKILL:2:2 */ 977 PHYMOD_SYMBOL_FIELD_ENCODE(1007, 2, 2), 978 /* PMD_LN_TX_H_PWRDN_PKILL:3:3 */ 979 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1008, 3, 3) 980 }; 981 static uint32_t BCMI_TSCF_XGXS_CKRST_LN_RST_OCC_CTLr_fields[] = 982 { 983 /* LANE_REG_RESET_OCCURRED:0:0 */ 984 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(769, 0, 0) 985 }; 986 static uint32_t BCMI_TSCF_XGXS_CKRST_LN_S_RSTB_CTLr_fields[] = 987 { 988 /* LN_S_RSTB:0:0 */ 989 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(796, 0, 0) 990 }; 991 static uint32_t BCMI_TSCF_XGXS_CKRST_OSR_MODE_CTLr_fields[] = 992 { 993 /* OSR_MODE_FRC_VAL:0:3 */ 994 PHYMOD_SYMBOL_FIELD_ENCODE(936, 3, 0), 995 /* OSR_MODE_FRC:15:15 */ 996 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(935, 15, 15) 997 }; 998 static uint32_t BCMI_TSCF_XGXS_CKRST_OSR_MODE_PIN_STSr_fields[] = 999 { 1000 /* OSR_MODE_PIN:0:3 */ 1001 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(938, 3, 0) 1002 }; 1003 static uint32_t BCMI_TSCF_XGXS_CKRST_OSR_MODE_STSr_fields[] = 1004 { 1005 /* OSR_MODE:0:3 */ 1006 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(934, 3, 0) 1007 }; 1008 static uint32_t BCMI_TSCF_XGXS_CKRST_PMD_LN_MODE_STSr_fields[] = 1009 { 1010 /* PMD_LANE_MODE:0:15 */ 1011 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1004, 15, 0) 1012 }; 1013 static uint32_t BCMI_TSCF_XGXS_CKRST_UC_ACK_LN_CTLr_fields[] = 1014 { 1015 /* UC_ACK_LANE_CFG_DONE:0:0 */ 1016 PHYMOD_SYMBOL_FIELD_ENCODE(1506, 0, 0), 1017 /* UC_ACK_LANE_DP_RESET:1:1 */ 1018 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1507, 1, 1) 1019 }; 1020 static uint32_t BCMI_TSCF_XGXS_CL82_BER_HOr_fields[] = 1021 { 1022 /* BER_HO:0:13 */ 1023 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(290, 13, 0) 1024 }; 1025 static uint32_t BCMI_TSCF_XGXS_CL82_BER_LOr_fields[] = 1026 { 1027 /* BER_LO:0:7 */ 1028 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(291, 7, 0) 1029 }; 1030 static uint32_t BCMI_TSCF_XGXS_CL82_ERRED_BLKS_HOr_fields[] = 1031 { 1032 /* ERRORED_BLOCKS_HO:0:13 */ 1033 PHYMOD_SYMBOL_FIELD_ENCODE(663, 13, 0), 1034 /* ERRORED_BLOCKS_HO_PRESENT:15:15 */ 1035 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(664, 15, 15) 1036 }; 1037 static uint32_t BCMI_TSCF_XGXS_CL82_LANES_1_0_AM_BYTE2r_fields[] = 1038 { 1039 /* LANE_0_AM_2:0:7 */ 1040 PHYMOD_SYMBOL_FIELD_ENCODE(758, 7, 0), 1041 /* LANE_1_AM_2:8:15 */ 1042 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(760, 15, 8) 1043 }; 1044 static uint32_t BCMI_TSCF_XGXS_CL82_LN_0_AM_BYTE10r_fields[] = 1045 { 1046 /* LANE_0_AM_1_0:0:15 */ 1047 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(757, 15, 0) 1048 }; 1049 static uint32_t BCMI_TSCF_XGXS_CL82_LN_1_AM_BYTE10r_fields[] = 1050 { 1051 /* LANE_1_AM_1_0:0:15 */ 1052 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(759, 15, 0) 1053 }; 1054 static uint32_t BCMI_TSCF_XGXS_CL82_RX_AM_TMRr_fields[] = 1055 { 1056 /* AM_TIMER_INIT_RX_VAL:0:15 */ 1057 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(210, 15, 0) 1058 }; 1059 static uint32_t BCMI_TSCF_XGXS_CL82_RX_LATCH_STSr_fields[] = 1060 { 1061 /* DESKEW_HIS_STATE:0:1 */ 1062 PHYMOD_SYMBOL_FIELD_ENCODE(587, 1, 0), 1063 /* HISTORY_RXSM_STATE:2:8 */ 1064 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(731, 8, 2) 1065 }; 1066 static uint32_t BCMI_TSCF_XGXS_CL82_RX_LIVE_STSr_fields[] = 1067 { 1068 /* CURRENT_RXSM_STATE:0:6 */ 1069 PHYMOD_SYMBOL_FIELD_ENCODE(544, 6, 0), 1070 /* R_TYPE_CODED:7:12 */ 1071 PHYMOD_SYMBOL_FIELD_ENCODE(1275, 12, 7), 1072 /* DESKEW_STATE:13:14 */ 1073 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(607, 14, 13) 1074 }; 1075 static uint32_t BCMI_TSCF_XGXS_CL93N72_IR_BASE_R_LP_COEFF_UPDr_fields[] = 1076 { 1077 /* CL93N72_IEEE_LP_COEFF_UPDATE:0:15 */ 1078 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(470, 15, 0) 1079 }; 1080 static uint32_t BCMI_TSCF_XGXS_CL93N72_IR_BASE_R_LP_STS_REPr_fields[] = 1081 { 1082 /* CL93N72_IEEE_LP_STATUS_REPORT:0:15 */ 1083 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(471, 15, 0) 1084 }; 1085 static uint32_t BCMI_TSCF_XGXS_CL93N72_IT_BASE_R_LD_COEFF_UPDr_fields[] = 1086 { 1087 /* CL93N72_IEEE_LD_COEFF_UPDATE:0:15 */ 1088 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(468, 15, 0) 1089 }; 1090 static uint32_t BCMI_TSCF_XGXS_CL93N72_IT_BASE_R_LD_STS_REPr_fields[] = 1091 { 1092 /* CL93N72_IEEE_LD_STATUS_REPORT:0:15 */ 1093 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(469, 15, 0) 1094 }; 1095 static uint32_t BCMI_TSCF_XGXS_CL93N72_IT_BASE_R_PMD_CTLr_fields[] = 1096 { 1097 /* CL93N72_IEEE_RESTART_TRAINING:0:0 */ 1098 PHYMOD_SYMBOL_FIELD_ENCODE(473, 0, 0), 1099 /* CL93N72_IEEE_TRAINING_ENABLE:1:1 */ 1100 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(474, 1, 1) 1101 }; 1102 static uint32_t BCMI_TSCF_XGXS_CL93N72_IT_BASE_R_PMD_STSr_fields[] = 1103 { 1104 /* CL93N72_IEEE_RECEIVER_STATUS:0:0 */ 1105 PHYMOD_SYMBOL_FIELD_ENCODE(472, 0, 0), 1106 /* CL93N72_IEEE_FRAME_LOCK:1:1 */ 1107 PHYMOD_SYMBOL_FIELD_ENCODE(467, 1, 1), 1108 /* CL93N72_IEEE_TRAINING_STATUS:2:2 */ 1109 PHYMOD_SYMBOL_FIELD_ENCODE(476, 2, 2), 1110 /* CL93N72_IEEE_TRAINING_FAILURE:3:3 */ 1111 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(475, 3, 3) 1112 }; 1113 static uint32_t BCMI_TSCF_XGXS_CL93N72_UR_CTL0r_fields[] = 1114 { 1115 /* CL93N72_RX_TRAINING_EN:0:0 */ 1116 PHYMOD_SYMBOL_FIELD_ENCODE(489, 0, 0), 1117 /* CL93N72_TR_COARSE_LOCK:1:1 */ 1118 PHYMOD_SYMBOL_FIELD_ENCODE(496, 1, 1), 1119 /* CL93N72_RX_SIGNAL_OK:2:2 */ 1120 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(488, 2, 2) 1121 }; 1122 static uint32_t BCMI_TSCF_XGXS_CL93N72_UR_CTL1r_fields[] = 1123 { 1124 /* CL93N72_GOOD_MARKER_CNT:0:1 */ 1125 PHYMOD_SYMBOL_FIELD_ENCODE(466, 1, 0), 1126 /* CL93N72_BAD_MARKER_CNT:4:6 */ 1127 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(457, 6, 4) 1128 }; 1129 static uint32_t BCMI_TSCF_XGXS_CL93N72_UR_CTL2r_fields[] = 1130 { 1131 /* CL93N72_CTRL_FRAME_DLY:0:3 */ 1132 PHYMOD_SYMBOL_FIELD_ENCODE(461, 3, 0), 1133 /* CL93N72_DME_CELL_BOUNDARY_CHK:4:4 */ 1134 PHYMOD_SYMBOL_FIELD_ENCODE(463, 4, 4), 1135 /* CL93N72_STRICT_DME_CHK:5:5 */ 1136 PHYMOD_SYMBOL_FIELD_ENCODE(490, 5, 5), 1137 /* CL93N72_STRICT_MARKER_CHK:6:6 */ 1138 PHYMOD_SYMBOL_FIELD_ENCODE(491, 6, 6), 1139 /* CL93N72_PPM_OFFSET_EN:7:7 */ 1140 PHYMOD_SYMBOL_FIELD_ENCODE(485, 7, 7), 1141 /* CL93N72_RX_DP_LN_CLK_EN:8:8 */ 1142 PHYMOD_SYMBOL_FIELD_ENCODE(487, 8, 8), 1143 /* CL93N72_FRAME_CONSISTENCY_CHK_EN:9:9 */ 1144 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(464, 9, 9) 1145 }; 1146 static uint32_t BCMI_TSCF_XGXS_CL93N72_UR_STS0r_fields[] = 1147 { 1148 /* CL93N72_FRAME_LOCK:0:0 */ 1149 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(465, 0, 0) 1150 }; 1151 static uint32_t BCMI_TSCF_XGXS_CL93N72_UR_UC_INTR_CTL0r_fields[] = 1152 { 1153 /* CL93N72_MICRO_UPDATE_CHG_INT_EN:0:0 */ 1154 PHYMOD_SYMBOL_FIELD_ENCODE(483, 0, 0), 1155 /* CL93N72_MICRO_STATUS_CHG_INT_EN:1:1 */ 1156 PHYMOD_SYMBOL_FIELD_ENCODE(481, 1, 1), 1157 /* CL93N72_MICRO_FRAME_LOCK_INT_EN:2:2 */ 1158 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(479, 2, 2) 1159 }; 1160 static uint32_t BCMI_TSCF_XGXS_CL93N72_UR_UC_STS0r_fields[] = 1161 { 1162 /* CL93N72_MICRO_UPDATE_CHG_LSTATUS:0:0 */ 1163 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(484, 0, 0) 1164 }; 1165 static uint32_t BCMI_TSCF_XGXS_CL93N72_UR_UC_STS1r_fields[] = 1166 { 1167 /* CL93N72_MICRO_STATUS_CHG_LSTATUS:0:0 */ 1168 PHYMOD_SYMBOL_FIELD_ENCODE(482, 0, 0), 1169 /* CL93N72_MICRO_FRAME_LOCK_LSTATUS:1:1 */ 1170 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(480, 1, 1) 1171 }; 1172 static uint32_t BCMI_TSCF_XGXS_CL93N72_UT_CTL0r_fields[] = 1173 { 1174 /* CL93N72_SW_RX_TRAINED:0:0 */ 1175 PHYMOD_SYMBOL_FIELD_ENCODE(494, 0, 0), 1176 /* CL93N72_SW_FRAME_LOCK:1:1 */ 1177 PHYMOD_SYMBOL_FIELD_ENCODE(492, 1, 1), 1178 /* CL93N72_SW_REMOTE_RX_READY:2:2 */ 1179 PHYMOD_SYMBOL_FIELD_ENCODE(493, 2, 2), 1180 /* CL93N72_PRBS_SEL:4:6 */ 1181 PHYMOD_SYMBOL_FIELD_ENCODE(486, 6, 4), 1182 /* CL93N72_CL93PRBSSEED_ORDER:7:7 */ 1183 PHYMOD_SYMBOL_FIELD_ENCODE(459, 7, 7), 1184 /* CL93N72_CL93PRBSSEED_RANDOM:8:8 */ 1185 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(460, 8, 8) 1186 }; 1187 static uint32_t BCMI_TSCF_XGXS_CL93N72_UT_CTL1r_fields[] = 1188 { 1189 /* CL93N72_BRK_RING_OSC:0:0 */ 1190 PHYMOD_SYMBOL_FIELD_ENCODE(458, 0, 0), 1191 /* CL93N72_DIS_MAX_WAIT_TIMER:1:1 */ 1192 PHYMOD_SYMBOL_FIELD_ENCODE(462, 1, 1), 1193 /* CL93N72_TX_DP_LN_CLK_EN:2:2 */ 1194 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(500, 2, 2) 1195 }; 1196 static uint32_t BCMI_TSCF_XGXS_CL93N72_UT_CTL2r_fields[] = 1197 { 1198 /* CL93N72_TXFIR_PRE:0:4 */ 1199 PHYMOD_SYMBOL_FIELD_ENCODE(499, 4, 0), 1200 /* CL93N72_TXFIR_POST:8:13 */ 1201 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(498, 13, 8) 1202 }; 1203 static uint32_t BCMI_TSCF_XGXS_CL93N72_UT_CTL3r_fields[] = 1204 { 1205 /* CL93N72_TXFIR_MAIN:0:6 */ 1206 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(497, 6, 0) 1207 }; 1208 static uint32_t BCMI_TSCF_XGXS_CL93N72_UT_LD_XMT_STS_PAGEr_fields[] = 1209 { 1210 /* CL93N72_LD_XMT_STATUS_PAGE:0:15 */ 1211 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(477, 15, 0) 1212 }; 1213 static uint32_t BCMI_TSCF_XGXS_CL93N72_UT_STS0r_fields[] = 1214 { 1215 /* CL93N72_LOCAL_RX_READY:0:0 */ 1216 PHYMOD_SYMBOL_FIELD_ENCODE(478, 0, 0), 1217 /* CL93N72_TRAINING_FSM_SIGNAL_DETECT:1:1 */ 1218 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(495, 1, 1) 1219 }; 1220 static uint32_t BCMI_TSCF_XGXS_CL93N72_UT_XMT_UPD_PAGEr_fields[] = 1221 { 1222 /* CL93N72_XMT_UPDATE_PAGE:0:15 */ 1223 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(501, 15, 0) 1224 }; 1225 static uint32_t BCMI_TSCF_XGXS_DIG_CORE_DP_RST_ST_STSr_fields[] = 1226 { 1227 /* CORE_DP_RESET_STATE:0:2 */ 1228 PHYMOD_SYMBOL_FIELD_ENCODE(525, 2, 0), 1229 /* LANE_RESET_RELEASED_INDEX:8:12 */ 1230 PHYMOD_SYMBOL_FIELD_ENCODE(771, 12, 8), 1231 /* LANE_RESET_RELEASED:14:14 */ 1232 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(770, 14, 14) 1233 }; 1234 static uint32_t BCMI_TSCF_XGXS_DIG_CORE_RST_OCC_CTLr_fields[] = 1235 { 1236 /* CORE_REG_RESET_OCCURRED:0:0 */ 1237 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(530, 0, 0) 1238 }; 1239 static uint32_t BCMI_TSCF_XGXS_DIG_LN_ADDR_2_3r_fields[] = 1240 { 1241 /* LANE_ADDR_2:0:4 */ 1242 PHYMOD_SYMBOL_FIELD_ENCODE(763, 4, 0), 1243 /* LANE_ADDR_3:8:12 */ 1244 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(764, 12, 8) 1245 }; 1246 static uint32_t BCMI_TSCF_XGXS_DIG_LN_MASKr_fields[] = 1247 { 1248 /* CORE_MULTICAST_MASK_CONTROL:0:3 */ 1249 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(529, 3, 0) 1250 }; 1251 static uint32_t BCMI_TSCF_XGXS_DIG_PMD_CORE_MODE_STSr_fields[] = 1252 { 1253 /* PMD_CORE_MODE:0:15 */ 1254 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1003, 15, 0) 1255 }; 1256 static uint32_t BCMI_TSCF_XGXS_DIG_REVID0r_fields[] = 1257 { 1258 /* REVID_MODEL:0:5 */ 1259 PHYMOD_SYMBOL_FIELD_ENCODE(1089, 5, 0), 1260 /* REVID_PROCESS:6:8 */ 1261 PHYMOD_SYMBOL_FIELD_ENCODE(1092, 8, 6), 1262 /* REVID_BONDING:9:10 */ 1263 PHYMOD_SYMBOL_FIELD_ENCODE(1083, 10, 9), 1264 /* REVID_REV_NUMBER:11:13 */ 1265 PHYMOD_SYMBOL_FIELD_ENCODE(1094, 13, 11), 1266 /* REVID_REV_LETTER:14:15 */ 1267 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1093, 15, 14) 1268 }; 1269 static uint32_t BCMI_TSCF_XGXS_DIG_REVID1r_fields[] = 1270 { 1271 /* REVID_EEE:0:0 */ 1272 PHYMOD_SYMBOL_FIELD_ENCODE(1085, 0, 0), 1273 /* REVID_LLP:1:1 */ 1274 PHYMOD_SYMBOL_FIELD_ENCODE(1086, 1, 1), 1275 /* REVID_PIR:2:2 */ 1276 PHYMOD_SYMBOL_FIELD_ENCODE(1091, 2, 2), 1277 /* REVID_CL72:3:3 */ 1278 PHYMOD_SYMBOL_FIELD_ENCODE(1084, 3, 3), 1279 /* REVID_MICRO:4:4 */ 1280 PHYMOD_SYMBOL_FIELD_ENCODE(1088, 4, 4), 1281 /* REVID_MDIO:5:5 */ 1282 PHYMOD_SYMBOL_FIELD_ENCODE(1087, 5, 5), 1283 /* REVID_MULTIPLICITY:12:15 */ 1284 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1090, 15, 12) 1285 }; 1286 static uint32_t BCMI_TSCF_XGXS_DIG_REVID2r_fields[] = 1287 { 1288 /* REVID2:0:3 */ 1289 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1082, 3, 0) 1290 }; 1291 static uint32_t BCMI_TSCF_XGXS_DIG_RST_CTL_CORE_DPr_fields[] = 1292 { 1293 /* PMD_CORE_DP_H_RSTB_PKILL:1:1 */ 1294 PHYMOD_SYMBOL_FIELD_ENCODE(1002, 1, 1), 1295 /* SUP_RST_SEQ_FRC_VAL:3:3 */ 1296 PHYMOD_SYMBOL_FIELD_ENCODE(1320, 3, 3), 1297 /* SUP_RST_SEQ_FRC:4:4 */ 1298 PHYMOD_SYMBOL_FIELD_ENCODE(1319, 4, 4), 1299 /* PMD_MDIO_TRANS_PKILL:5:5 */ 1300 PHYMOD_SYMBOL_FIELD_ENCODE(1011, 5, 5), 1301 /* PMD_TX_CLK_VLD_FRC:7:7 */ 1302 PHYMOD_SYMBOL_FIELD_ENCODE(1016, 7, 7), 1303 /* PMD_TX_CLK_VLD_FRC_VAL:8:8 */ 1304 PHYMOD_SYMBOL_FIELD_ENCODE(1017, 8, 8), 1305 /* TX_S_COMCLK_SEL:9:9 */ 1306 PHYMOD_SYMBOL_FIELD_ENCODE(1484, 9, 9), 1307 /* TX_S_COMCLK_FRC_ON:10:10 */ 1308 PHYMOD_SYMBOL_FIELD_ENCODE(1483, 10, 10), 1309 /* TX_S_CLKGATE_FRC_ON:11:11 */ 1310 PHYMOD_SYMBOL_FIELD_ENCODE(1482, 11, 11), 1311 /* AFE_S_PLL_RESET_FRC_VAL:12:12 */ 1312 PHYMOD_SYMBOL_FIELD_ENCODE(15, 12, 12), 1313 /* AFE_S_PLL_RESET_FRC:13:13 */ 1314 PHYMOD_SYMBOL_FIELD_ENCODE(14, 13, 13), 1315 /* TX_PI_LOOP_FILTER_STABLE:14:14 */ 1316 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1463, 14, 14) 1317 }; 1318 static uint32_t BCMI_TSCF_XGXS_DIG_RST_CTL_PMDr_fields[] = 1319 { 1320 /* CORE_S_RSTB:0:0 */ 1321 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(531, 0, 0) 1322 }; 1323 static uint32_t BCMI_TSCF_XGXS_DIG_RST_SEQ_TMR_CTLr_fields[] = 1324 { 1325 /* RST_SEQ_TIMER:0:2 */ 1326 PHYMOD_SYMBOL_FIELD_ENCODE(1105, 2, 0), 1327 /* PWRDN_SEQ_TIMER:8:10 */ 1328 PHYMOD_SYMBOL_FIELD_ENCODE(1059, 10, 8), 1329 /* RST_SEQ_DIS_FLT_MODE:14:15 */ 1330 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1104, 15, 14) 1331 }; 1332 static uint32_t BCMI_TSCF_XGXS_DIG_TOP_USER_CTL0r_fields[] = 1333 { 1334 /* HEARTBEAT_COUNT_1US:0:9 */ 1335 PHYMOD_SYMBOL_FIELD_ENCODE(727, 9, 0), 1336 /* CORE_DP_S_RSTB:13:13 */ 1337 PHYMOD_SYMBOL_FIELD_ENCODE(526, 13, 13), 1338 /* AFE_S_PLL_PWRDN:14:14 */ 1339 PHYMOD_SYMBOL_FIELD_ENCODE(13, 14, 14), 1340 /* UC_ACTIVE:15:15 */ 1341 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1508, 15, 15) 1342 }; 1343 static uint32_t BCMI_TSCF_XGXS_DIG_TX_LN_MAP_0_1_2r_fields[] = 1344 { 1345 /* TX_LANE_MAP_0:0:4 */ 1346 PHYMOD_SYMBOL_FIELD_ENCODE(1436, 4, 0), 1347 /* TX_LANE_MAP_1:5:9 */ 1348 PHYMOD_SYMBOL_FIELD_ENCODE(1437, 9, 5), 1349 /* TX_LANE_MAP_2:10:14 */ 1350 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1438, 14, 10) 1351 }; 1352 static uint32_t BCMI_TSCF_XGXS_DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r_fields[] = 1353 { 1354 /* TX_LANE_MAP_3:0:4 */ 1355 PHYMOD_SYMBOL_FIELD_ENCODE(1439, 4, 0), 1356 /* LANE_ADDR_0:5:9 */ 1357 PHYMOD_SYMBOL_FIELD_ENCODE(761, 9, 5), 1358 /* LANE_ADDR_1:10:14 */ 1359 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(762, 14, 10) 1360 }; 1361 static uint32_t BCMI_TSCF_XGXS_DIG_UC_ACK_CORE_CTLr_fields[] = 1362 { 1363 /* UC_ACK_CORE_CFG_DONE:0:0 */ 1364 PHYMOD_SYMBOL_FIELD_ENCODE(1501, 0, 0), 1365 /* UC_ACK_CORE_DP_RESET:1:1 */ 1366 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1502, 1, 1) 1367 }; 1368 static uint32_t BCMI_TSCF_XGXS_DSC_CDR_1G_STSr_fields[] = 1369 { 1370 /* CDR_1G_PHASE_POINTER:0:7 */ 1371 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(355, 7, 0) 1372 }; 1373 static uint32_t BCMI_TSCF_XGXS_DSC_CDR_CTL0r_fields[] = 1374 { 1375 /* OS_ALL_EDGES:0:0 */ 1376 PHYMOD_SYMBOL_FIELD_ENCODE(939, 0, 0), 1377 /* BR_PD_EN:1:1 */ 1378 PHYMOD_SYMBOL_FIELD_ENCODE(313, 1, 1), 1379 /* OS_PATTERN_ENHANCED:2:2 */ 1380 PHYMOD_SYMBOL_FIELD_ENCODE(942, 2, 2), 1381 /* CDR_FREQ_EN:3:3 */ 1382 PHYMOD_SYMBOL_FIELD_ENCODE(364, 3, 3), 1383 /* CDR_INTEG_REG_CLR:5:5 */ 1384 PHYMOD_SYMBOL_FIELD_ENCODE(370, 5, 5), 1385 /* CDR_PHASE_ERR_FRZ:6:6 */ 1386 PHYMOD_SYMBOL_FIELD_ENCODE(375, 6, 6), 1387 /* CDR_INTEG_SAT_SEL:7:7 */ 1388 PHYMOD_SYMBOL_FIELD_ENCODE(371, 7, 7), 1389 /* CDR_FREQ_OVERRIDE_EN:8:8 */ 1390 PHYMOD_SYMBOL_FIELD_ENCODE(365, 8, 8), 1391 /* CDR_ZERO_POLARITY:9:9 */ 1392 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(378, 9, 9) 1393 }; 1394 static uint32_t BCMI_TSCF_XGXS_DSC_CDR_CTL1r_fields[] = 1395 { 1396 /* CDR_FREQ_OVERRIDE_VAL:5:15 */ 1397 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(366, 15, 5) 1398 }; 1399 static uint32_t BCMI_TSCF_XGXS_DSC_CDR_CTL2r_fields[] = 1400 { 1401 /* CDR_LM_THR_SEL:0:3 */ 1402 PHYMOD_SYMBOL_FIELD_ENCODE(373, 3, 0), 1403 /* CDR_1G_SWAP_PZ:4:4 */ 1404 PHYMOD_SYMBOL_FIELD_ENCODE(356, 4, 4), 1405 /* CDR_1G_FORCE_EN:5:5 */ 1406 PHYMOD_SYMBOL_FIELD_ENCODE(352, 5, 5), 1407 /* TX_PI_LOOP_TIMING_SRC_SEL:6:6 */ 1408 PHYMOD_SYMBOL_FIELD_ENCODE(1464, 6, 6), 1409 /* PHS_SUM_IGNORE_DSC_LOCK:7:7 */ 1410 PHYMOD_SYMBOL_FIELD_ENCODE(974, 7, 7), 1411 /* CDR_1G_MANUAL_MODE:8:8 */ 1412 PHYMOD_SYMBOL_FIELD_ENCODE(353, 8, 8), 1413 /* CDR_1G_MANUAL_STROBE:9:9 */ 1414 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(354, 9, 9) 1415 }; 1416 static uint32_t BCMI_TSCF_XGXS_DSC_CDR_STS_INTEGr_fields[] = 1417 { 1418 /* CDR_INTEG_REG:0:15 */ 1419 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(369, 15, 0) 1420 }; 1421 static uint32_t BCMI_TSCF_XGXS_DSC_CDR_STS_MISCr_fields[] = 1422 { 1423 /* CDR_LM_OUTOFLOCK:0:0 */ 1424 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(372, 0, 0) 1425 }; 1426 static uint32_t BCMI_TSCF_XGXS_DSC_CDR_STS_PHASE_ERRr_fields[] = 1427 { 1428 /* CDR_PHASE_ERROR:0:5 */ 1429 PHYMOD_SYMBOL_FIELD_ENCODE(374, 5, 0), 1430 /* CDR_VCO_REG:12:15 */ 1431 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(377, 15, 12) 1432 }; 1433 static uint32_t BCMI_TSCF_XGXS_DSC_DATA_SLCR_THR_CTLr_fields[] = 1434 { 1435 /* THRESH_TIMER_T1:0:1 */ 1436 PHYMOD_SYMBOL_FIELD_ENCODE(1346, 1, 0), 1437 /* THRESH_STEP_SIZE:4:5 */ 1438 PHYMOD_SYMBOL_FIELD_ENCODE(1345, 5, 4), 1439 /* DATA_THRESH_SEL_VAL:8:14 */ 1440 PHYMOD_SYMBOL_FIELD_ENCODE(545, 14, 8), 1441 /* DATA_THRESH_WRITE:15:15 */ 1442 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(546, 15, 15) 1443 }; 1444 static uint32_t BCMI_TSCF_XGXS_DSC_DC_OFFS_CTLr_fields[] = 1445 { 1446 /* DC_OFFS_EN:0:0 */ 1447 PHYMOD_SYMBOL_FIELD_ENCODE(567, 0, 0), 1448 /* DC_OFFS_HYS_EN:2:2 */ 1449 PHYMOD_SYMBOL_FIELD_ENCODE(570, 2, 2), 1450 /* DC_OFFS_HYS_MAG:3:3 */ 1451 PHYMOD_SYMBOL_FIELD_ENCODE(571, 3, 3), 1452 /* DC_OFFS_GRADIENT_INVERT:4:4 */ 1453 PHYMOD_SYMBOL_FIELD_ENCODE(569, 4, 4), 1454 /* DC_OFFS_GAIN:5:6 */ 1455 PHYMOD_SYMBOL_FIELD_ENCODE(568, 6, 5), 1456 /* DC_OFFS_ACC_CLR:7:7 */ 1457 PHYMOD_SYMBOL_FIELD_ENCODE(566, 7, 7), 1458 /* DC_OFFS_WRITE_VAL:8:14 */ 1459 PHYMOD_SYMBOL_FIELD_ENCODE(574, 14, 8), 1460 /* DC_OFFS_WRITE_FRC_EN:15:15 */ 1461 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(573, 15, 15) 1462 }; 1463 static uint32_t BCMI_TSCF_XGXS_DSC_DC_OFFS_STSr_fields[] = 1464 { 1465 /* DC_OFFSET_BIN:0:6 */ 1466 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(565, 6, 0) 1467 }; 1468 static uint32_t BCMI_TSCF_XGXS_DSC_LOAD_PRESETSr_fields[] = 1469 { 1470 /* PRESET_DSC_AFE_BANK:0:0 */ 1471 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1042, 0, 0) 1472 }; 1473 static uint32_t BCMI_TSCF_XGXS_DSC_PRESETr_fields[] = 1474 { 1475 /* PRESET_DSC_C_BANK:0:0 */ 1476 PHYMOD_SYMBOL_FIELD_ENCODE(1044, 0, 0), 1477 /* PRESET_DSC_D_BANK:1:1 */ 1478 PHYMOD_SYMBOL_FIELD_ENCODE(1045, 1, 1), 1479 /* PRESET_DSC_A_BANK:2:2 */ 1480 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1043, 2, 2) 1481 }; 1482 static uint32_t BCMI_TSCF_XGXS_DSC_RXAB_SLCR_OFFS_ADJ_LMSr_fields[] = 1483 { 1484 /* RXB_SLICER_OFFSET_ADJ_LMS:0:5 */ 1485 PHYMOD_SYMBOL_FIELD_ENCODE(1155, 5, 0), 1486 /* RXA_SLICER_OFFSET_ADJ_LMS:8:13 */ 1487 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1129, 13, 8) 1488 }; 1489 static uint32_t BCMI_TSCF_XGXS_DSC_RXA_SLCR_OFFS_ADJ_DN_DPr_fields[] = 1490 { 1491 /* RXA_SLICER_OFFSET_ADJ_DP:0:5 */ 1492 PHYMOD_SYMBOL_FIELD_ENCODE(1128, 5, 0), 1493 /* RXA_SLICER_OFFSET_ADJ_DN:8:13 */ 1494 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1127, 13, 8) 1495 }; 1496 static uint32_t BCMI_TSCF_XGXS_DSC_RXA_SLCR_OFFS_ADJ_ZN_ZPr_fields[] = 1497 { 1498 /* RXA_SLICER_OFFSET_ADJ_ZP:0:5 */ 1499 PHYMOD_SYMBOL_FIELD_ENCODE(1131, 5, 0), 1500 /* RXA_SLICER_OFFSET_ADJ_ZN:8:13 */ 1501 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1130, 13, 8) 1502 }; 1503 static uint32_t BCMI_TSCF_XGXS_DSC_RXB_SLCR_OFFS_ADJ_DN_DPr_fields[] = 1504 { 1505 /* RXB_SLICER_OFFSET_ADJ_DP:0:5 */ 1506 PHYMOD_SYMBOL_FIELD_ENCODE(1154, 5, 0), 1507 /* RXB_SLICER_OFFSET_ADJ_DN:8:13 */ 1508 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1153, 13, 8) 1509 }; 1510 static uint32_t BCMI_TSCF_XGXS_DSC_RXB_SLCR_OFFS_ADJ_ZN_ZPr_fields[] = 1511 { 1512 /* RXB_SLICER_OFFSET_ADJ_ZP:0:5 */ 1513 PHYMOD_SYMBOL_FIELD_ENCODE(1157, 5, 0), 1514 /* RXB_SLICER_OFFSET_ADJ_ZN:8:13 */ 1515 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1156, 13, 8) 1516 }; 1517 static uint32_t BCMI_TSCF_XGXS_DSC_RXCD_SLCR_OFFS_ADJ_LMSr_fields[] = 1518 { 1519 /* RXD_SLICER_OFFSET_ADJ_LMS:0:5 */ 1520 PHYMOD_SYMBOL_FIELD_ENCODE(1207, 5, 0), 1521 /* RXC_SLICER_OFFSET_ADJ_LMS:8:13 */ 1522 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1181, 13, 8) 1523 }; 1524 static uint32_t BCMI_TSCF_XGXS_DSC_RXC_SLCR_OFFS_ADJ_DN_DPr_fields[] = 1525 { 1526 /* RXC_SLICER_OFFSET_ADJ_DP:0:5 */ 1527 PHYMOD_SYMBOL_FIELD_ENCODE(1180, 5, 0), 1528 /* RXC_SLICER_OFFSET_ADJ_DN:8:13 */ 1529 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1179, 13, 8) 1530 }; 1531 static uint32_t BCMI_TSCF_XGXS_DSC_RXC_SLCR_OFFS_ADJ_ZN_ZPr_fields[] = 1532 { 1533 /* RXC_SLICER_OFFSET_ADJ_ZP:0:5 */ 1534 PHYMOD_SYMBOL_FIELD_ENCODE(1183, 5, 0), 1535 /* RXC_SLICER_OFFSET_ADJ_ZN:8:13 */ 1536 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1182, 13, 8) 1537 }; 1538 static uint32_t BCMI_TSCF_XGXS_DSC_RXD_SLCR_OFFS_ADJ_DN_DPr_fields[] = 1539 { 1540 /* RXD_SLICER_OFFSET_ADJ_DP:0:5 */ 1541 PHYMOD_SYMBOL_FIELD_ENCODE(1206, 5, 0), 1542 /* RXD_SLICER_OFFSET_ADJ_DN:8:13 */ 1543 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1205, 13, 8) 1544 }; 1545 static uint32_t BCMI_TSCF_XGXS_DSC_RXD_SLCR_OFFS_ADJ_ZN_ZPr_fields[] = 1546 { 1547 /* RXD_SLICER_OFFSET_ADJ_ZP:0:5 */ 1548 PHYMOD_SYMBOL_FIELD_ENCODE(1209, 5, 0), 1549 /* RXD_SLICER_OFFSET_ADJ_ZN:8:13 */ 1550 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1208, 13, 8) 1551 }; 1552 static uint32_t BCMI_TSCF_XGXS_DSC_RX_DATA_15_TO0r_fields[] = 1553 { 1554 /* RX_DATA_15_TO_0:0:15 */ 1555 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1222, 15, 0) 1556 }; 1557 static uint32_t BCMI_TSCF_XGXS_DSC_RX_DATA_35_TO_20r_fields[] = 1558 { 1559 /* RX_DATA_35_TO_20:0:15 */ 1560 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1223, 15, 0) 1561 }; 1562 static uint32_t BCMI_TSCF_XGXS_DSC_RX_DFE_TAP10_ABCDr_fields[] = 1563 { 1564 /* RXD_DFE_TAP10:0:3 */ 1565 PHYMOD_SYMBOL_FIELD_ENCODE(1184, 3, 0), 1566 /* RXC_DFE_TAP10:4:7 */ 1567 PHYMOD_SYMBOL_FIELD_ENCODE(1158, 7, 4), 1568 /* RXB_DFE_TAP10:8:11 */ 1569 PHYMOD_SYMBOL_FIELD_ENCODE(1132, 11, 8), 1570 /* RXA_DFE_TAP10:12:15 */ 1571 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1106, 15, 12) 1572 }; 1573 static uint32_t BCMI_TSCF_XGXS_DSC_RX_DFE_TAP11_12_MUX_ABCDr_fields[] = 1574 { 1575 /* RXD_DFE_TAP12_MUX:0:1 */ 1576 PHYMOD_SYMBOL_FIELD_ENCODE(1189, 1, 0), 1577 /* RXD_DFE_TAP11_MUX:2:3 */ 1578 PHYMOD_SYMBOL_FIELD_ENCODE(1187, 3, 2), 1579 /* RXC_DFE_TAP12_MUX:4:5 */ 1580 PHYMOD_SYMBOL_FIELD_ENCODE(1163, 5, 4), 1581 /* RXC_DFE_TAP11_MUX:6:7 */ 1582 PHYMOD_SYMBOL_FIELD_ENCODE(1161, 7, 6), 1583 /* RXB_DFE_TAP12_MUX:8:9 */ 1584 PHYMOD_SYMBOL_FIELD_ENCODE(1137, 9, 8), 1585 /* RXB_DFE_TAP11_MUX:10:11 */ 1586 PHYMOD_SYMBOL_FIELD_ENCODE(1135, 11, 10), 1587 /* RXA_DFE_TAP12_MUX:12:13 */ 1588 PHYMOD_SYMBOL_FIELD_ENCODE(1111, 13, 12), 1589 /* RXA_DFE_TAP11_MUX:14:15 */ 1590 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1109, 15, 14) 1591 }; 1592 static uint32_t BCMI_TSCF_XGXS_DSC_RX_DFE_TAP11_ABCDr_fields[] = 1593 { 1594 /* RXD_DFE_TAP11:0:3 */ 1595 PHYMOD_SYMBOL_FIELD_ENCODE(1186, 3, 0), 1596 /* RXC_DFE_TAP11:4:7 */ 1597 PHYMOD_SYMBOL_FIELD_ENCODE(1160, 7, 4), 1598 /* RXB_DFE_TAP11:8:11 */ 1599 PHYMOD_SYMBOL_FIELD_ENCODE(1134, 11, 8), 1600 /* RXA_DFE_TAP11:12:15 */ 1601 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1108, 15, 12) 1602 }; 1603 static uint32_t BCMI_TSCF_XGXS_DSC_RX_DFE_TAP12_ABCDr_fields[] = 1604 { 1605 /* RXD_DFE_TAP12:0:3 */ 1606 PHYMOD_SYMBOL_FIELD_ENCODE(1188, 3, 0), 1607 /* RXC_DFE_TAP12:4:7 */ 1608 PHYMOD_SYMBOL_FIELD_ENCODE(1162, 7, 4), 1609 /* RXB_DFE_TAP12:8:11 */ 1610 PHYMOD_SYMBOL_FIELD_ENCODE(1136, 11, 8), 1611 /* RXA_DFE_TAP12:12:15 */ 1612 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1110, 15, 12) 1613 }; 1614 static uint32_t BCMI_TSCF_XGXS_DSC_RX_DFE_TAP13_14_MUX_ABCDr_fields[] = 1615 { 1616 /* RXD_DFE_TAP14_MUX:0:1 */ 1617 PHYMOD_SYMBOL_FIELD_ENCODE(1193, 1, 0), 1618 /* RXD_DFE_TAP13_MUX:2:3 */ 1619 PHYMOD_SYMBOL_FIELD_ENCODE(1191, 3, 2), 1620 /* RXC_DFE_TAP14_MUX:4:5 */ 1621 PHYMOD_SYMBOL_FIELD_ENCODE(1167, 5, 4), 1622 /* RXC_DFE_TAP13_MUX:6:7 */ 1623 PHYMOD_SYMBOL_FIELD_ENCODE(1165, 7, 6), 1624 /* RXB_DFE_TAP14_MUX:8:9 */ 1625 PHYMOD_SYMBOL_FIELD_ENCODE(1141, 9, 8), 1626 /* RXB_DFE_TAP13_MUX:10:11 */ 1627 PHYMOD_SYMBOL_FIELD_ENCODE(1139, 11, 10), 1628 /* RXA_DFE_TAP14_MUX:12:13 */ 1629 PHYMOD_SYMBOL_FIELD_ENCODE(1115, 13, 12), 1630 /* RXA_DFE_TAP13_MUX:14:15 */ 1631 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1113, 15, 14) 1632 }; 1633 static uint32_t BCMI_TSCF_XGXS_DSC_RX_DFE_TAP13_ABCDr_fields[] = 1634 { 1635 /* RXD_DFE_TAP13:0:3 */ 1636 PHYMOD_SYMBOL_FIELD_ENCODE(1190, 3, 0), 1637 /* RXC_DFE_TAP13:4:7 */ 1638 PHYMOD_SYMBOL_FIELD_ENCODE(1164, 7, 4), 1639 /* RXB_DFE_TAP13:8:11 */ 1640 PHYMOD_SYMBOL_FIELD_ENCODE(1138, 11, 8), 1641 /* RXA_DFE_TAP13:12:15 */ 1642 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1112, 15, 12) 1643 }; 1644 static uint32_t BCMI_TSCF_XGXS_DSC_RX_DFE_TAP14_ABCDr_fields[] = 1645 { 1646 /* RXD_DFE_TAP14:0:3 */ 1647 PHYMOD_SYMBOL_FIELD_ENCODE(1192, 3, 0), 1648 /* RXC_DFE_TAP14:4:7 */ 1649 PHYMOD_SYMBOL_FIELD_ENCODE(1166, 7, 4), 1650 /* RXB_DFE_TAP14:8:11 */ 1651 PHYMOD_SYMBOL_FIELD_ENCODE(1140, 11, 8), 1652 /* RXA_DFE_TAP14:12:15 */ 1653 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1114, 15, 12) 1654 }; 1655 static uint32_t BCMI_TSCF_XGXS_DSC_RX_DFE_TAP2_ABr_fields[] = 1656 { 1657 /* RXB_DFE_TAP2:0:4 */ 1658 PHYMOD_SYMBOL_FIELD_ENCODE(1142, 4, 0), 1659 /* RXA_DFE_TAP2:8:12 */ 1660 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1116, 12, 8) 1661 }; 1662 static uint32_t BCMI_TSCF_XGXS_DSC_RX_DFE_TAP2_CDr_fields[] = 1663 { 1664 /* RXD_DFE_TAP2:0:4 */ 1665 PHYMOD_SYMBOL_FIELD_ENCODE(1194, 4, 0), 1666 /* RXC_DFE_TAP2:8:12 */ 1667 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1168, 12, 8) 1668 }; 1669 static uint32_t BCMI_TSCF_XGXS_DSC_RX_DFE_TAP3_ABr_fields[] = 1670 { 1671 /* RXB_DFE_TAP3:0:4 */ 1672 PHYMOD_SYMBOL_FIELD_ENCODE(1143, 4, 0), 1673 /* RXA_DFE_TAP3:8:12 */ 1674 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1117, 12, 8) 1675 }; 1676 static uint32_t BCMI_TSCF_XGXS_DSC_RX_DFE_TAP3_CDr_fields[] = 1677 { 1678 /* RXD_DFE_TAP3:0:4 */ 1679 PHYMOD_SYMBOL_FIELD_ENCODE(1195, 4, 0), 1680 /* RXC_DFE_TAP3:8:12 */ 1681 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1169, 12, 8) 1682 }; 1683 static uint32_t BCMI_TSCF_XGXS_DSC_RX_DFE_TAP4_ABCDr_fields[] = 1684 { 1685 /* RXD_DFE_TAP4:0:3 */ 1686 PHYMOD_SYMBOL_FIELD_ENCODE(1196, 3, 0), 1687 /* RXC_DFE_TAP4:4:7 */ 1688 PHYMOD_SYMBOL_FIELD_ENCODE(1170, 7, 4), 1689 /* RXB_DFE_TAP4:8:11 */ 1690 PHYMOD_SYMBOL_FIELD_ENCODE(1144, 11, 8), 1691 /* RXA_DFE_TAP4:12:15 */ 1692 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1118, 15, 12) 1693 }; 1694 static uint32_t BCMI_TSCF_XGXS_DSC_RX_DFE_TAP5_ABCDr_fields[] = 1695 { 1696 /* RXD_DFE_TAP5:0:3 */ 1697 PHYMOD_SYMBOL_FIELD_ENCODE(1197, 3, 0), 1698 /* RXC_DFE_TAP5:4:7 */ 1699 PHYMOD_SYMBOL_FIELD_ENCODE(1171, 7, 4), 1700 /* RXB_DFE_TAP5:8:11 */ 1701 PHYMOD_SYMBOL_FIELD_ENCODE(1145, 11, 8), 1702 /* RXA_DFE_TAP5:12:15 */ 1703 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1119, 15, 12) 1704 }; 1705 static uint32_t BCMI_TSCF_XGXS_DSC_RX_DFE_TAP6_ABCDr_fields[] = 1706 { 1707 /* RXD_DFE_TAP6:0:3 */ 1708 PHYMOD_SYMBOL_FIELD_ENCODE(1198, 3, 0), 1709 /* RXC_DFE_TAP6:4:7 */ 1710 PHYMOD_SYMBOL_FIELD_ENCODE(1172, 7, 4), 1711 /* RXB_DFE_TAP6:8:11 */ 1712 PHYMOD_SYMBOL_FIELD_ENCODE(1146, 11, 8), 1713 /* RXA_DFE_TAP6:12:15 */ 1714 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1120, 15, 12) 1715 }; 1716 static uint32_t BCMI_TSCF_XGXS_DSC_RX_DFE_TAP7_8_MUX_ABCDr_fields[] = 1717 { 1718 /* RXD_DFE_TAP8_MUX:0:1 */ 1719 PHYMOD_SYMBOL_FIELD_ENCODE(1202, 1, 0), 1720 /* RXD_DFE_TAP7_MUX:2:3 */ 1721 PHYMOD_SYMBOL_FIELD_ENCODE(1200, 3, 2), 1722 /* RXC_DFE_TAP8_MUX:4:5 */ 1723 PHYMOD_SYMBOL_FIELD_ENCODE(1176, 5, 4), 1724 /* RXC_DFE_TAP7_MUX:6:7 */ 1725 PHYMOD_SYMBOL_FIELD_ENCODE(1174, 7, 6), 1726 /* RXB_DFE_TAP8_MUX:8:9 */ 1727 PHYMOD_SYMBOL_FIELD_ENCODE(1150, 9, 8), 1728 /* RXB_DFE_TAP7_MUX:10:11 */ 1729 PHYMOD_SYMBOL_FIELD_ENCODE(1148, 11, 10), 1730 /* RXA_DFE_TAP8_MUX:12:13 */ 1731 PHYMOD_SYMBOL_FIELD_ENCODE(1124, 13, 12), 1732 /* RXA_DFE_TAP7_MUX:14:15 */ 1733 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1122, 15, 14) 1734 }; 1735 static uint32_t BCMI_TSCF_XGXS_DSC_RX_DFE_TAP7_ABCDr_fields[] = 1736 { 1737 /* RXD_DFE_TAP7:0:3 */ 1738 PHYMOD_SYMBOL_FIELD_ENCODE(1199, 3, 0), 1739 /* RXC_DFE_TAP7:4:7 */ 1740 PHYMOD_SYMBOL_FIELD_ENCODE(1173, 7, 4), 1741 /* RXB_DFE_TAP7:8:11 */ 1742 PHYMOD_SYMBOL_FIELD_ENCODE(1147, 11, 8), 1743 /* RXA_DFE_TAP7:12:15 */ 1744 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1121, 15, 12) 1745 }; 1746 static uint32_t BCMI_TSCF_XGXS_DSC_RX_DFE_TAP8_ABCDr_fields[] = 1747 { 1748 /* RXD_DFE_TAP8:0:3 */ 1749 PHYMOD_SYMBOL_FIELD_ENCODE(1201, 3, 0), 1750 /* RXC_DFE_TAP8:4:7 */ 1751 PHYMOD_SYMBOL_FIELD_ENCODE(1175, 7, 4), 1752 /* RXB_DFE_TAP8:8:11 */ 1753 PHYMOD_SYMBOL_FIELD_ENCODE(1149, 11, 8), 1754 /* RXA_DFE_TAP8:12:15 */ 1755 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1123, 15, 12) 1756 }; 1757 static uint32_t BCMI_TSCF_XGXS_DSC_RX_DFE_TAP9_10_MUX_ABCDr_fields[] = 1758 { 1759 /* RXD_DFE_TAP10_MUX:0:1 */ 1760 PHYMOD_SYMBOL_FIELD_ENCODE(1185, 1, 0), 1761 /* RXD_DFE_TAP9_MUX:2:3 */ 1762 PHYMOD_SYMBOL_FIELD_ENCODE(1204, 3, 2), 1763 /* RXC_DFE_TAP10_MUX:4:5 */ 1764 PHYMOD_SYMBOL_FIELD_ENCODE(1159, 5, 4), 1765 /* RXC_DFE_TAP9_MUX:6:7 */ 1766 PHYMOD_SYMBOL_FIELD_ENCODE(1178, 7, 6), 1767 /* RXB_DFE_TAP10_MUX:8:9 */ 1768 PHYMOD_SYMBOL_FIELD_ENCODE(1133, 9, 8), 1769 /* RXB_DFE_TAP9_MUX:10:11 */ 1770 PHYMOD_SYMBOL_FIELD_ENCODE(1152, 11, 10), 1771 /* RXA_DFE_TAP10_MUX:12:13 */ 1772 PHYMOD_SYMBOL_FIELD_ENCODE(1107, 13, 12), 1773 /* RXA_DFE_TAP9_MUX:14:15 */ 1774 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1126, 15, 14) 1775 }; 1776 static uint32_t BCMI_TSCF_XGXS_DSC_RX_DFE_TAP9_ABCDr_fields[] = 1777 { 1778 /* RXD_DFE_TAP9:0:3 */ 1779 PHYMOD_SYMBOL_FIELD_ENCODE(1203, 3, 0), 1780 /* RXC_DFE_TAP9:4:7 */ 1781 PHYMOD_SYMBOL_FIELD_ENCODE(1177, 7, 4), 1782 /* RXB_DFE_TAP9:8:11 */ 1783 PHYMOD_SYMBOL_FIELD_ENCODE(1151, 11, 8), 1784 /* RXA_DFE_TAP9:12:15 */ 1785 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1125, 15, 12) 1786 }; 1787 static uint32_t BCMI_TSCF_XGXS_DSC_RX_PF_CTL_DC_OFFSr_fields[] = 1788 { 1789 /* RX_PF2_CTRL:8:10 */ 1790 PHYMOD_SYMBOL_FIELD_ENCODE(1241, 10, 8), 1791 /* RX_PF_CTRL:11:14 */ 1792 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1242, 14, 11) 1793 }; 1794 static uint32_t BCMI_TSCF_XGXS_DSC_RX_PHASE_LMS_THR_SELr_fields[] = 1795 { 1796 /* RX_LMS_THRESH_SEL:0:7 */ 1797 PHYMOD_SYMBOL_FIELD_ENCODE(1229, 7, 0), 1798 /* RX_PHASE_THRESH_SEL:8:14 */ 1799 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1243, 14, 8) 1800 }; 1801 static uint32_t BCMI_TSCF_XGXS_DSC_RX_PI_CNT_BIN_Dr_fields[] = 1802 { 1803 /* RX_PI_CNT_BIN_D:0:7 */ 1804 PHYMOD_SYMBOL_FIELD_ENCODE(1244, 7, 0), 1805 /* RX_PI_CNT_BIN_DQ:8:15 */ 1806 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1245, 15, 8) 1807 }; 1808 static uint32_t BCMI_TSCF_XGXS_DSC_RX_PI_CNT_BIN_Lr_fields[] = 1809 { 1810 /* RX_PI_CNT_BIN_L:0:7 */ 1811 PHYMOD_SYMBOL_FIELD_ENCODE(1248, 7, 0), 1812 /* RX_PI_CNT_BIN_LQ:8:15 */ 1813 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1249, 15, 8) 1814 }; 1815 static uint32_t BCMI_TSCF_XGXS_DSC_RX_PI_CNT_BIN_LDr_fields[] = 1816 { 1817 /* RX_PI_CNT_BIN_L_LD:0:7 */ 1818 PHYMOD_SYMBOL_FIELD_ENCODE(1250, 7, 0), 1819 /* RX_PI_CNT_BIN_D_LD:8:15 */ 1820 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1246, 15, 8) 1821 }; 1822 static uint32_t BCMI_TSCF_XGXS_DSC_RX_PI_CNT_BIN_Pr_fields[] = 1823 { 1824 /* RX_PI_CNT_BIN_P:0:7 */ 1825 PHYMOD_SYMBOL_FIELD_ENCODE(1251, 7, 0), 1826 /* RX_PI_CNT_BIN_PQ:8:15 */ 1827 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1252, 15, 8) 1828 }; 1829 static uint32_t BCMI_TSCF_XGXS_DSC_RX_PI_CNT_BIN_PDr_fields[] = 1830 { 1831 /* RX_PI_CNT_BIN_P_PD:0:7 */ 1832 PHYMOD_SYMBOL_FIELD_ENCODE(1253, 7, 0), 1833 /* RX_PI_CNT_BIN_D_PD:8:15 */ 1834 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1247, 15, 8) 1835 }; 1836 static uint32_t BCMI_TSCF_XGXS_DSC_RX_PI_CTLr_fields[] = 1837 { 1838 /* RX_PI_SLICERS_EN:0:5 */ 1839 PHYMOD_SYMBOL_FIELD_ENCODE(1258, 5, 0), 1840 /* RX_PI_PHASE_STEP_CNT:6:8 */ 1841 PHYMOD_SYMBOL_FIELD_ENCODE(1256, 8, 6), 1842 /* RX_PI_PHASE_STEP_DIR:9:9 */ 1843 PHYMOD_SYMBOL_FIELD_ENCODE(1257, 9, 9), 1844 /* RX_PI_MANUAL_MODE:10:10 */ 1845 PHYMOD_SYMBOL_FIELD_ENCODE(1254, 10, 10), 1846 /* RX_PI_MANUAL_STROBE:11:11 */ 1847 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1255, 11, 11) 1848 }; 1849 static uint32_t BCMI_TSCF_XGXS_DSC_SCRATCHr_fields[] = 1850 { 1851 /* UC_DSC_SCRATCH:0:15 */ 1852 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1512, 15, 0) 1853 }; 1854 static uint32_t BCMI_TSCF_XGXS_DSC_SM_CTL0r_fields[] = 1855 { 1856 /* EEE_MODE_EN:1:1 */ 1857 PHYMOD_SYMBOL_FIELD_ENCODE(648, 1, 1), 1858 /* EEE_QUIET_RX_AFE_PWRDWN_VAL:2:2 */ 1859 PHYMOD_SYMBOL_FIELD_ENCODE(652, 2, 2), 1860 /* IGNORE_RX_MODE:3:3 */ 1861 PHYMOD_SYMBOL_FIELD_ENCODE(746, 3, 3), 1862 /* CL72_TIMER_EN:4:4 */ 1863 PHYMOD_SYMBOL_FIELD_ENCODE(411, 4, 4), 1864 /* UC_TUNE_EN:5:5 */ 1865 PHYMOD_SYMBOL_FIELD_ENCODE(1515, 5, 5), 1866 /* HW_TUNE_EN:6:6 */ 1867 PHYMOD_SYMBOL_FIELD_ENCODE(741, 6, 6), 1868 /* EEE_MEASURE_EN:8:8 */ 1869 PHYMOD_SYMBOL_FIELD_ENCODE(647, 8, 8), 1870 /* UC_ACK_DSC_EEE_DONE:11:11 */ 1871 PHYMOD_SYMBOL_FIELD_ENCODE(1504, 11, 11), 1872 /* UC_ACK_DSC_RESTART:13:13 */ 1873 PHYMOD_SYMBOL_FIELD_ENCODE(1505, 13, 13), 1874 /* UC_ACK_DSC_CONFIG:14:14 */ 1875 PHYMOD_SYMBOL_FIELD_ENCODE(1503, 14, 14), 1876 /* SET_MEAS_INCOMPLETE:15:15 */ 1877 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1291, 15, 15) 1878 }; 1879 static uint32_t BCMI_TSCF_XGXS_DSC_SM_CTL1r_fields[] = 1880 { 1881 /* RX_DSC_LOCK_FRC:0:0 */ 1882 PHYMOD_SYMBOL_FIELD_ENCODE(1226, 0, 0), 1883 /* RX_DSC_LOCK_FRC_VAL:1:1 */ 1884 PHYMOD_SYMBOL_FIELD_ENCODE(1227, 1, 1), 1885 /* DSC_CLR_FRC:2:2 */ 1886 PHYMOD_SYMBOL_FIELD_ENCODE(632, 2, 2), 1887 /* DSC_CLR_FRC_VAL:3:3 */ 1888 PHYMOD_SYMBOL_FIELD_ENCODE(633, 3, 3), 1889 /* TRNSUM_FRZ_FRC:4:4 */ 1890 PHYMOD_SYMBOL_FIELD_ENCODE(1375, 4, 4), 1891 /* TRNSUM_FRZ_FRC_VAL:5:5 */ 1892 PHYMOD_SYMBOL_FIELD_ENCODE(1376, 5, 5), 1893 /* TIMER_DONE_FRC:6:6 */ 1894 PHYMOD_SYMBOL_FIELD_ENCODE(1353, 6, 6), 1895 /* TIMER_DONE_FRC_VAL:7:7 */ 1896 PHYMOD_SYMBOL_FIELD_ENCODE(1354, 7, 7), 1897 /* FREQ_UPD_EN_FRC:8:8 */ 1898 PHYMOD_SYMBOL_FIELD_ENCODE(724, 8, 8), 1899 /* FREQ_UPD_EN_FRC_VAL:9:9 */ 1900 PHYMOD_SYMBOL_FIELD_ENCODE(725, 9, 9), 1901 /* CDR_FRZ_FRC:10:10 */ 1902 PHYMOD_SYMBOL_FIELD_ENCODE(367, 10, 10), 1903 /* CDR_FRZ_FRC_VAL:11:11 */ 1904 PHYMOD_SYMBOL_FIELD_ENCODE(368, 11, 11), 1905 /* TRNSUM_CLR_FRC:12:12 */ 1906 PHYMOD_SYMBOL_FIELD_ENCODE(1365, 12, 12), 1907 /* TRNSUM_CLR_FRC_VAL:13:13 */ 1908 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1366, 13, 13) 1909 }; 1910 static uint32_t BCMI_TSCF_XGXS_DSC_SM_CTL2r_fields[] = 1911 { 1912 /* EEE_LFSR_CNT:0:12 */ 1913 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(645, 12, 0) 1914 }; 1915 static uint32_t BCMI_TSCF_XGXS_DSC_SM_CTL3r_fields[] = 1916 { 1917 /* MEASURE_LFSR_CNT:0:12 */ 1918 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(850, 12, 0) 1919 }; 1920 static uint32_t BCMI_TSCF_XGXS_DSC_SM_CTL4r_fields[] = 1921 { 1922 /* ACQ_CDR_TIMEOUT:0:4 */ 1923 PHYMOD_SYMBOL_FIELD_ENCODE(2, 4, 0), 1924 /* CDR_SETTLE_TIMEOUT:5:9 */ 1925 PHYMOD_SYMBOL_FIELD_ENCODE(376, 9, 5), 1926 /* HW_TUNE_TIMEOUT:10:14 */ 1927 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(742, 14, 10) 1928 }; 1929 static uint32_t BCMI_TSCF_XGXS_DSC_SM_CTL5r_fields[] = 1930 { 1931 /* MEASURE_TIMEOUT:0:4 */ 1932 PHYMOD_SYMBOL_FIELD_ENCODE(851, 4, 0), 1933 /* EEE_ACQ_CDR_TIMEOUT:5:9 */ 1934 PHYMOD_SYMBOL_FIELD_ENCODE(641, 9, 5), 1935 /* EEE_CDR_SETTLE_TIMEOUT:10:14 */ 1936 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(643, 14, 10) 1937 }; 1938 static uint32_t BCMI_TSCF_XGXS_DSC_SM_CTL6r_fields[] = 1939 { 1940 /* EEE_HW_TUNE_TIMEOUT:0:4 */ 1941 PHYMOD_SYMBOL_FIELD_ENCODE(644, 4, 0), 1942 /* EEE_ANA_PWR_TIMEOUT:10:14 */ 1943 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(642, 14, 10) 1944 }; 1945 static uint32_t BCMI_TSCF_XGXS_DSC_SM_CTL7r_fields[] = 1946 { 1947 /* CDR_BWSEL_INTEG_ACQCDR:0:3 */ 1948 PHYMOD_SYMBOL_FIELD_ENCODE(358, 3, 0), 1949 /* CDR_BWSEL_INTEG_EEE_ACQCDR:4:7 */ 1950 PHYMOD_SYMBOL_FIELD_ENCODE(359, 7, 4), 1951 /* CDR_BWSEL_INTEG_NORM:8:11 */ 1952 PHYMOD_SYMBOL_FIELD_ENCODE(360, 11, 8), 1953 /* CDR_BWSEL_PROP_ACQCDR:12:12 */ 1954 PHYMOD_SYMBOL_FIELD_ENCODE(361, 12, 12), 1955 /* CDR_BWSEL_PROP_NORM:14:14 */ 1956 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(363, 14, 14) 1957 }; 1958 static uint32_t BCMI_TSCF_XGXS_DSC_SM_CTL8r_fields[] = 1959 { 1960 /* PHASE_ERR_OFFSET:0:3 */ 1961 PHYMOD_SYMBOL_FIELD_ENCODE(972, 3, 0), 1962 /* EEE_PHASE_ERR_OFFSET:4:7 */ 1963 PHYMOD_SYMBOL_FIELD_ENCODE(649, 7, 4), 1964 /* PHASE_ERR_OFFSET_EN:8:9 */ 1965 PHYMOD_SYMBOL_FIELD_ENCODE(973, 9, 8), 1966 /* EEE_PHASE_ERR_OFFSET_EN:10:11 */ 1967 PHYMOD_SYMBOL_FIELD_ENCODE(650, 11, 10), 1968 /* CDR_BWSEL_PROP_EEE_ACQCDR:14:14 */ 1969 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(362, 14, 14) 1970 }; 1971 static uint32_t BCMI_TSCF_XGXS_DSC_SM_CTL9r_fields[] = 1972 { 1973 /* RX_RESTART_PMD:0:0 */ 1974 PHYMOD_SYMBOL_FIELD_ENCODE(1263, 0, 0), 1975 /* RX_RESTART_PMD_HOLD:1:1 */ 1976 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1264, 1, 1) 1977 }; 1978 static uint32_t BCMI_TSCF_XGXS_DSC_SM_STS_DSC_LOCKr_fields[] = 1979 { 1980 /* RX_DSC_LOCK:0:0 */ 1981 PHYMOD_SYMBOL_FIELD_ENCODE(1225, 0, 0), 1982 /* MEAS_INCOMPLETE:1:1 */ 1983 PHYMOD_SYMBOL_FIELD_ENCODE(852, 1, 1), 1984 /* EEE_MEASURE_CNT:7:15 */ 1985 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(646, 15, 7) 1986 }; 1987 static uint32_t BCMI_TSCF_XGXS_DSC_SM_STS_DSC_STr_fields[] = 1988 { 1989 /* DSC_SM_SCRATCH:0:3 */ 1990 PHYMOD_SYMBOL_FIELD_ENCODE(636, 3, 0), 1991 /* DSC_SM_READY_FOR_CMD:4:4 */ 1992 PHYMOD_SYMBOL_FIELD_ENCODE(635, 4, 4), 1993 /* DSC_SM_GP_UC_REQ:5:10 */ 1994 PHYMOD_SYMBOL_FIELD_ENCODE(634, 10, 5), 1995 /* DSC_STATE:11:15 */ 1996 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(637, 15, 11) 1997 }; 1998 static uint32_t BCMI_TSCF_XGXS_DSC_SM_STS_DSC_ST_EEE_ONE_HOTr_fields[] = 1999 { 2000 /* DSC_STATE_EEE_ONE_HOT:0:6 */ 2001 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(638, 6, 0) 2002 }; 2003 static uint32_t BCMI_TSCF_XGXS_DSC_SM_STS_DSC_ST_ONE_HOTr_fields[] = 2004 { 2005 /* DSC_STATE_ONE_HOT:0:9 */ 2006 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(639, 9, 0) 2007 }; 2008 static uint32_t BCMI_TSCF_XGXS_DSC_SM_STS_RESTARTr_fields[] = 2009 { 2010 /* RESTART_PI_EXT_MODE:0:0 */ 2011 PHYMOD_SYMBOL_FIELD_ENCODE(1077, 0, 0), 2012 /* RESTART_SIGDET:1:1 */ 2013 PHYMOD_SYMBOL_FIELD_ENCODE(1079, 1, 1), 2014 /* RESTART_PMD_RESTART:2:2 */ 2015 PHYMOD_SYMBOL_FIELD_ENCODE(1078, 2, 2), 2016 /* EEE_QUIET_FROM_EEE_STATES:3:3 */ 2017 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(651, 3, 3) 2018 }; 2019 static uint32_t BCMI_TSCF_XGXS_DSC_TRNSUMr_fields[] = 2020 { 2021 /* TRNSUM:0:15 */ 2022 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1359, 15, 0) 2023 }; 2024 static uint32_t BCMI_TSCF_XGXS_DSC_TRNSUM_Ar_fields[] = 2025 { 2026 /* TRNSUM_A:0:15 */ 2027 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1360, 15, 0) 2028 }; 2029 static uint32_t BCMI_TSCF_XGXS_DSC_TRNSUM_A_LOr_fields[] = 2030 { 2031 /* TRNSUM_A_LOW:8:15 */ 2032 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1361, 15, 8) 2033 }; 2034 static uint32_t BCMI_TSCF_XGXS_DSC_TRNSUM_Br_fields[] = 2035 { 2036 /* TRNSUM_B:0:15 */ 2037 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1362, 15, 0) 2038 }; 2039 static uint32_t BCMI_TSCF_XGXS_DSC_TRNSUM_B_LOr_fields[] = 2040 { 2041 /* TRNSUM_B_LOW:8:15 */ 2042 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1363, 15, 8) 2043 }; 2044 static uint32_t BCMI_TSCF_XGXS_DSC_TRNSUM_Cr_fields[] = 2045 { 2046 /* TRNSUM_C:0:15 */ 2047 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1364, 15, 0) 2048 }; 2049 static uint32_t BCMI_TSCF_XGXS_DSC_TRNSUM_CTLr_fields[] = 2050 { 2051 /* TRNSUM_GAIN:0:1 */ 2052 PHYMOD_SYMBOL_FIELD_ENCODE(1377, 1, 0), 2053 /* TRNSUM_SEL_EMUX:2:2 */ 2054 PHYMOD_SYMBOL_FIELD_ENCODE(1385, 2, 2), 2055 /* TRNSUM_TAP_RANGE_SEL:4:6 */ 2056 PHYMOD_SYMBOL_FIELD_ENCODE(1387, 6, 4), 2057 /* TRNSUM_COR_SEL:8:9 */ 2058 PHYMOD_SYMBOL_FIELD_ENCODE(1367, 9, 8), 2059 /* TRNSUM_QPHASE_MULT_EN:12:12 */ 2060 PHYMOD_SYMBOL_FIELD_ENCODE(1383, 12, 12), 2061 /* TRNSUM_RANDOM_TAPSEL_DISABLE:13:13 */ 2062 PHYMOD_SYMBOL_FIELD_ENCODE(1384, 13, 13), 2063 /* TRNSUM_EYE_CLOSURE_EN:14:14 */ 2064 PHYMOD_SYMBOL_FIELD_ENCODE(1374, 14, 14), 2065 /* TRNSUM_EN:15:15 */ 2066 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1372, 15, 15) 2067 }; 2068 static uint32_t BCMI_TSCF_XGXS_DSC_TRNSUM_C_LOr_fields[] = 2069 { 2070 /* TRNSUM_C_LOW:8:15 */ 2071 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1368, 15, 8) 2072 }; 2073 static uint32_t BCMI_TSCF_XGXS_DSC_TRNSUM_Dr_fields[] = 2074 { 2075 /* TRNSUM_D:0:15 */ 2076 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1369, 15, 0) 2077 }; 2078 static uint32_t BCMI_TSCF_XGXS_DSC_TRNSUM_D_LOr_fields[] = 2079 { 2080 /* TRNSUM_D_LOW:8:15 */ 2081 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1370, 15, 8) 2082 }; 2083 static uint32_t BCMI_TSCF_XGXS_DSC_TRNSUM_LOr_fields[] = 2084 { 2085 /* TRNSUM_LOW:6:15 */ 2086 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1379, 15, 6) 2087 }; 2088 static uint32_t BCMI_TSCF_XGXS_DSC_TRNSUM_MISCr_fields[] = 2089 { 2090 /* TDT_PRBS_SLIP:0:0 */ 2091 PHYMOD_SYMBOL_FIELD_ENCODE(1342, 0, 0), 2092 /* CDR_1G_TRNSUM_EN:1:1 */ 2093 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(357, 1, 1) 2094 }; 2095 static uint32_t BCMI_TSCF_XGXS_DSC_TRNSUM_PAT_CTL1r_fields[] = 2096 { 2097 /* TRNSUM_PATTERN:0:9 */ 2098 PHYMOD_SYMBOL_FIELD_ENCODE(1380, 9, 0), 2099 /* TRNSUM_PATTERN_FULL_CHECK_OFF:12:12 */ 2100 PHYMOD_SYMBOL_FIELD_ENCODE(1382, 12, 12), 2101 /* TRNSUM_EDGE_PATTERN_EN:14:14 */ 2102 PHYMOD_SYMBOL_FIELD_ENCODE(1371, 14, 14), 2103 /* TRNSUM_INV_PATTERN_EN:15:15 */ 2104 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1378, 15, 15) 2105 }; 2106 static uint32_t BCMI_TSCF_XGXS_DSC_TRNSUM_PAT_CTL2r_fields[] = 2107 { 2108 /* TRNSUM_PATTERN_BIT_EN:0:9 */ 2109 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1381, 9, 0) 2110 }; 2111 static uint32_t BCMI_TSCF_XGXS_DSC_TRNSUM_TAP_CTLr_fields[] = 2112 { 2113 /* TRNSUM_TAP_EN:0:7 */ 2114 PHYMOD_SYMBOL_FIELD_ENCODE(1386, 7, 0), 2115 /* TRNSUM_TAP_SIGN:8:15 */ 2116 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1388, 15, 8) 2117 }; 2118 static uint32_t BCMI_TSCF_XGXS_DSC_TRNSUM_TDT_CTLr_fields[] = 2119 { 2120 /* TDT_BIT_SEL:0:5 */ 2121 PHYMOD_SYMBOL_FIELD_ENCODE(1338, 5, 0), 2122 /* TDT_PRBS_MODE:6:6 */ 2123 PHYMOD_SYMBOL_FIELD_ENCODE(1341, 6, 6), 2124 /* TDT_TRNSUM_EN:7:7 */ 2125 PHYMOD_SYMBOL_FIELD_ENCODE(1343, 7, 7), 2126 /* TDT_CYCLE_SEL:8:11 */ 2127 PHYMOD_SYMBOL_FIELD_ENCODE(1340, 11, 8), 2128 /* TDT_CYCLE_BIN:12:15 */ 2129 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1339, 15, 12) 2130 }; 2131 static uint32_t BCMI_TSCF_XGXS_DSC_UC_CTLr_fields[] = 2132 { 2133 /* UC_DSC_GP_UC_REQ:0:5 */ 2134 PHYMOD_SYMBOL_FIELD_ENCODE(1510, 5, 0), 2135 /* UC_DSC_ERROR_FOUND:6:6 */ 2136 PHYMOD_SYMBOL_FIELD_ENCODE(1509, 6, 6), 2137 /* UC_DSC_READY_FOR_CMD:7:7 */ 2138 PHYMOD_SYMBOL_FIELD_ENCODE(1511, 7, 7), 2139 /* UC_DSC_SUPP_INFO:8:15 */ 2140 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1513, 15, 8) 2141 }; 2142 static uint32_t BCMI_TSCF_XGXS_DSC_VGA_CTL1r_fields[] = 2143 { 2144 /* VGA_TIMER_T2:0:2 */ 2145 PHYMOD_SYMBOL_FIELD_ENCODE(1533, 2, 0), 2146 /* UC_TRNSUM_EN:3:3 */ 2147 PHYMOD_SYMBOL_FIELD_ENCODE(1514, 3, 3), 2148 /* DC_OFFS_WRITE_EN:4:4 */ 2149 PHYMOD_SYMBOL_FIELD_ENCODE(572, 4, 4), 2150 /* VGA_DEC:5:5 */ 2151 PHYMOD_SYMBOL_FIELD_ENCODE(1531, 5, 5), 2152 /* VGA_INC:7:7 */ 2153 PHYMOD_SYMBOL_FIELD_ENCODE(1532, 7, 7), 2154 /* RX_VGA_CTRL_VAL:8:14 */ 2155 PHYMOD_SYMBOL_FIELD_ENCODE(1269, 14, 8), 2156 /* VGA_WRITE:15:15 */ 2157 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1534, 15, 15) 2158 }; 2159 static uint32_t BCMI_TSCF_XGXS_DSC_VGA_D_THR_STSr_fields[] = 2160 { 2161 /* RX_DATA_THRESH_SEL:0:6 */ 2162 PHYMOD_SYMBOL_FIELD_ENCODE(1224, 6, 0), 2163 /* RX_VGA_CTRL:8:14 */ 2164 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1268, 14, 8) 2165 }; 2166 static uint32_t BCMI_TSCF_XGXS_ILKN_CTL0r_fields[] = 2167 { 2168 /* WM:0:2 */ 2169 PHYMOD_SYMBOL_FIELD_ENCODE(1537, 2, 0), 2170 /* ILKN_SEL:3:3 */ 2171 PHYMOD_SYMBOL_FIELD_ENCODE(747, 3, 3), 2172 /* INV_TX_ORDER:6:6 */ 2173 PHYMOD_SYMBOL_FIELD_ENCODE(750, 6, 6), 2174 /* INV_RX_ORDER:7:7 */ 2175 PHYMOD_SYMBOL_FIELD_ENCODE(749, 7, 7), 2176 /* SOFT_RST_TX:8:8 */ 2177 PHYMOD_SYMBOL_FIELD_ENCODE(1312, 8, 8), 2178 /* SOFT_RST_RX:9:9 */ 2179 PHYMOD_SYMBOL_FIELD_ENCODE(1311, 9, 9), 2180 /* CREDIT_EN:15:15 */ 2181 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(543, 15, 15) 2182 }; 2183 static uint32_t BCMI_TSCF_XGXS_ILKN_STS0r_fields[] = 2184 { 2185 /* RXFIFO_EMPTY:0:0 */ 2186 PHYMOD_SYMBOL_FIELD_ENCODE(1210, 0, 0), 2187 /* RXFIFO_FULL:1:1 */ 2188 PHYMOD_SYMBOL_FIELD_ENCODE(1211, 1, 1), 2189 /* RXFIFO_OVERRUN:2:2 */ 2190 PHYMOD_SYMBOL_FIELD_ENCODE(1212, 2, 2), 2191 /* RXFIFO_UNDERRUN:3:3 */ 2192 PHYMOD_SYMBOL_FIELD_ENCODE(1213, 3, 3), 2193 /* TXFIFO_EMPTY:4:4 */ 2194 PHYMOD_SYMBOL_FIELD_ENCODE(1405, 4, 4), 2195 /* TXFIFO_FULL:5:5 */ 2196 PHYMOD_SYMBOL_FIELD_ENCODE(1406, 5, 5), 2197 /* TXFIFO_OVERRUN:6:6 */ 2198 PHYMOD_SYMBOL_FIELD_ENCODE(1407, 6, 6), 2199 /* TXFIFO_UNDERRUN:7:7 */ 2200 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1408, 7, 7) 2201 }; 2202 static uint32_t BCMI_TSCF_XGXS_MAIN0ACC_TMOUTr_fields[] = 2203 { 2204 /* TIMEOUT_COUNT:0:7 */ 2205 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1351, 7, 0) 2206 }; 2207 static uint32_t BCMI_TSCF_XGXS_MAIN0ACC_TMOUT_STSr_fields[] = 2208 { 2209 /* TIMEOUT_ERROR:0:0 */ 2210 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1352, 0, 0) 2211 }; 2212 static uint32_t BCMI_TSCF_XGXS_MAIN0_DEVINPKG5r_fields[] = 2213 { 2214 /* CLAUSE22:0:0 */ 2215 PHYMOD_SYMBOL_FIELD_ENCODE(502, 0, 0), 2216 /* PMA_PMD:1:1 */ 2217 PHYMOD_SYMBOL_FIELD_ENCODE(1001, 1, 1), 2218 /* WIS:2:2 */ 2219 PHYMOD_SYMBOL_FIELD_ENCODE(1536, 2, 2), 2220 /* PCS_XS:3:3 */ 2221 PHYMOD_SYMBOL_FIELD_ENCODE(966, 3, 3), 2222 /* PHY_XS:4:4 */ 2223 PHYMOD_SYMBOL_FIELD_ENCODE(975, 4, 4), 2224 /* DTE_XS:5:5 */ 2225 PHYMOD_SYMBOL_FIELD_ENCODE(640, 5, 5), 2226 /* TC:6:6 */ 2227 PHYMOD_SYMBOL_FIELD_ENCODE(1337, 6, 6), 2228 /* AN:7:7 */ 2229 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(211, 7, 7) 2230 }; 2231 static uint32_t BCMI_TSCF_XGXS_MAIN0_LN_SWPr_fields[] = 2232 { 2233 /* LOGICAL0_TO_PHY_SEL:0:1 */ 2234 PHYMOD_SYMBOL_FIELD_ENCODE(804, 1, 0), 2235 /* LOGICAL1_TO_PHY_SEL:2:3 */ 2236 PHYMOD_SYMBOL_FIELD_ENCODE(805, 3, 2), 2237 /* LOGICAL2_TO_PHY_SEL:4:5 */ 2238 PHYMOD_SYMBOL_FIELD_ENCODE(806, 5, 4), 2239 /* LOGICAL3_TO_PHY_SEL:6:7 */ 2240 PHYMOD_SYMBOL_FIELD_ENCODE(807, 7, 6), 2241 /* PLL_RESET_EN:8:8 */ 2242 PHYMOD_SYMBOL_FIELD_ENCODE(995, 8, 8), 2243 /* SPEED_100G_FEC_SEL:9:10 */ 2244 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1316, 10, 9) 2245 }; 2246 static uint32_t BCMI_TSCF_XGXS_MAIN0_LPBK_CTLr_fields[] = 2247 { 2248 /* LOCAL_PCS_LOOPBACK_ENABLE:0:3 */ 2249 PHYMOD_SYMBOL_FIELD_ENCODE(803, 3, 0), 2250 /* REMOTE_PCS_LOOPBACK_ENABLE:4:7 */ 2251 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1068, 7, 4) 2252 }; 2253 static uint32_t BCMI_TSCF_XGXS_MAIN0_MDIO_BCSTr_fields[] = 2254 { 2255 /* MULTIPRTS_EN:7:10 */ 2256 PHYMOD_SYMBOL_FIELD_ENCODE(918, 10, 7), 2257 /* PRTAD_BCST:11:15 */ 2258 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1047, 15, 11) 2259 }; 2260 static uint32_t BCMI_TSCF_XGXS_MAIN0_SERDESIDr_fields[] = 2261 { 2262 /* MODEL_NUMBER:0:5 */ 2263 PHYMOD_SYMBOL_FIELD_ENCODE(917, 5, 0), 2264 /* TECH_PROC:6:8 */ 2265 PHYMOD_SYMBOL_FIELD_ENCODE(1344, 8, 6), 2266 /* BONDING:9:10 */ 2267 PHYMOD_SYMBOL_FIELD_ENCODE(312, 10, 9), 2268 /* REV_NUMBER:11:13 */ 2269 PHYMOD_SYMBOL_FIELD_ENCODE(1096, 13, 11), 2270 /* REV_LETTER:14:15 */ 2271 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1095, 15, 14) 2272 }; 2273 static uint32_t BCMI_TSCF_XGXS_MAIN0_SETUPr_fields[] = 2274 { 2275 /* TSC_CLK_CTRL:0:0 */ 2276 PHYMOD_SYMBOL_FIELD_ENCODE(1389, 0, 0), 2277 /* CL73_VCO:1:1 */ 2278 PHYMOD_SYMBOL_FIELD_ENCODE(428, 1, 1), 2279 /* STAND_ALONE_MODE:2:2 */ 2280 PHYMOD_SYMBOL_FIELD_ENCODE(1318, 2, 2), 2281 /* SINGLE_PORT_MODE:3:3 */ 2282 PHYMOD_SYMBOL_FIELD_ENCODE(1309, 3, 3), 2283 /* PORT_MODE_SEL:4:6 */ 2284 PHYMOD_SYMBOL_FIELD_ENCODE(1019, 6, 4), 2285 /* REFCLK_SEL:7:9 */ 2286 PHYMOD_SYMBOL_FIELD_ENCODE(1062, 9, 7), 2287 /* CL72_EN:10:13 */ 2288 PHYMOD_SYMBOL_FIELD_ENCODE(409, 13, 10), 2289 /* MASTER_PORT_NUM:14:15 */ 2290 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(833, 15, 14) 2291 }; 2292 static uint32_t BCMI_TSCF_XGXS_MAIN0_SYNCE_CTLr_fields[] = 2293 { 2294 /* SYNCE_MODE_PHY_LANE0:0:1 */ 2295 PHYMOD_SYMBOL_FIELD_ENCODE(1329, 1, 0), 2296 /* SYNCE_MODE_PHY_LANE1:2:3 */ 2297 PHYMOD_SYMBOL_FIELD_ENCODE(1330, 3, 2), 2298 /* SYNCE_MODE_PHY_LANE2:4:5 */ 2299 PHYMOD_SYMBOL_FIELD_ENCODE(1331, 5, 4), 2300 /* SYNCE_MODE_PHY_LANE3:6:7 */ 2301 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1332, 7, 6) 2302 }; 2303 static uint32_t BCMI_TSCF_XGXS_MAIN0_SYNCE_CTL_STAGE0r_fields[] = 2304 { 2305 /* SYNCE_STAGE0_MODE_PHY_LANE0:0:1 */ 2306 PHYMOD_SYMBOL_FIELD_ENCODE(1333, 1, 0), 2307 /* SYNCE_STAGE0_MODE_PHY_LANE1:2:3 */ 2308 PHYMOD_SYMBOL_FIELD_ENCODE(1334, 3, 2), 2309 /* SYNCE_STAGE0_MODE_PHY_LANE2:4:5 */ 2310 PHYMOD_SYMBOL_FIELD_ENCODE(1335, 5, 4), 2311 /* SYNCE_STAGE0_MODE_PHY_LANE3:6:7 */ 2312 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1336, 7, 6) 2313 }; 2314 static uint32_t BCMI_TSCF_XGXS_MAIN0_TICK_CTL0r_fields[] = 2315 { 2316 /* TICK_DENOMINATOR:2:11 */ 2317 PHYMOD_SYMBOL_FIELD_ENCODE(1347, 11, 2), 2318 /* TICK_NUMERATOR_LOWER:12:15 */ 2319 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1348, 15, 12) 2320 }; 2321 static uint32_t BCMI_TSCF_XGXS_MAIN0_TICK_CTL1r_fields[] = 2322 { 2323 /* TICK_NUMERATOR_UPPER:0:14 */ 2324 PHYMOD_SYMBOL_FIELD_ENCODE(1349, 14, 0), 2325 /* TICK_OVERRIDE:15:15 */ 2326 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1350, 15, 15) 2327 }; 2328 static uint32_t BCMI_TSCF_XGXS_MDIO_AERr_fields[] = 2329 { 2330 /* MDIO_AER:0:15 */ 2331 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(836, 15, 0) 2332 }; 2333 static uint32_t BCMI_TSCF_XGXS_MDIO_BCST_PORT_ADDRr_fields[] = 2334 { 2335 /* MDIO_BRCST_PORT_ADDR:0:4 */ 2336 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(838, 4, 0) 2337 }; 2338 static uint32_t BCMI_TSCF_XGXS_MDIO_BLK_ADDRr_fields[] = 2339 { 2340 /* MDIO_BLK_ADDR:4:14 */ 2341 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(837, 14, 4) 2342 }; 2343 static uint32_t BCMI_TSCF_XGXS_MDIO_MASKDATAr_fields[] = 2344 { 2345 /* MDIO_MASKDATA:0:15 */ 2346 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(847, 15, 0) 2347 }; 2348 static uint32_t BCMI_TSCF_XGXS_MDIO_MMD_SELr_fields[] = 2349 { 2350 /* MDIO_DEV_CL22_EN:0:0 */ 2351 PHYMOD_SYMBOL_FIELD_ENCODE(841, 0, 0), 2352 /* MDIO_DEV_PMD_EN:2:2 */ 2353 PHYMOD_SYMBOL_FIELD_ENCODE(845, 2, 2), 2354 /* MDIO_DEV_AN_EN:3:3 */ 2355 PHYMOD_SYMBOL_FIELD_ENCODE(840, 3, 3), 2356 /* MDIO_DEV_PHY_EN:4:4 */ 2357 PHYMOD_SYMBOL_FIELD_ENCODE(844, 4, 4), 2358 /* MDIO_DEV_DTE_EN:5:5 */ 2359 PHYMOD_SYMBOL_FIELD_ENCODE(842, 5, 5), 2360 /* MDIO_DEV_PCS_EN:6:6 */ 2361 PHYMOD_SYMBOL_FIELD_ENCODE(843, 6, 6), 2362 /* MDIO_MULTI_MMDS_EN:14:14 */ 2363 PHYMOD_SYMBOL_FIELD_ENCODE(848, 14, 14), 2364 /* MDIO_MULTI_PRTS_EN:15:15 */ 2365 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(849, 15, 15) 2366 }; 2367 static uint32_t BCMI_TSCF_XGXS_PATT_GEN_SEQ0r_fields[] = 2368 { 2369 /* PATT_GEN_SEQ_0:0:15 */ 2370 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(948, 15, 0) 2371 }; 2372 static uint32_t BCMI_TSCF_XGXS_PATT_GEN_SEQ1r_fields[] = 2373 { 2374 /* PATT_GEN_SEQ_1:0:15 */ 2375 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(949, 15, 0) 2376 }; 2377 static uint32_t BCMI_TSCF_XGXS_PATT_GEN_SEQ2r_fields[] = 2378 { 2379 /* PATT_GEN_SEQ_2:0:15 */ 2380 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(955, 15, 0) 2381 }; 2382 static uint32_t BCMI_TSCF_XGXS_PATT_GEN_SEQ3r_fields[] = 2383 { 2384 /* PATT_GEN_SEQ_3:0:15 */ 2385 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(956, 15, 0) 2386 }; 2387 static uint32_t BCMI_TSCF_XGXS_PATT_GEN_SEQ4r_fields[] = 2388 { 2389 /* PATT_GEN_SEQ_4:0:15 */ 2390 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(957, 15, 0) 2391 }; 2392 static uint32_t BCMI_TSCF_XGXS_PATT_GEN_SEQ5r_fields[] = 2393 { 2394 /* PATT_GEN_SEQ_5:0:15 */ 2395 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(958, 15, 0) 2396 }; 2397 static uint32_t BCMI_TSCF_XGXS_PATT_GEN_SEQ6r_fields[] = 2398 { 2399 /* PATT_GEN_SEQ_6:0:15 */ 2400 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(959, 15, 0) 2401 }; 2402 static uint32_t BCMI_TSCF_XGXS_PATT_GEN_SEQ7r_fields[] = 2403 { 2404 /* PATT_GEN_SEQ_7:0:15 */ 2405 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(960, 15, 0) 2406 }; 2407 static uint32_t BCMI_TSCF_XGXS_PATT_GEN_SEQ8r_fields[] = 2408 { 2409 /* PATT_GEN_SEQ_8:0:15 */ 2410 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(961, 15, 0) 2411 }; 2412 static uint32_t BCMI_TSCF_XGXS_PATT_GEN_SEQ9r_fields[] = 2413 { 2414 /* PATT_GEN_SEQ_9:0:15 */ 2415 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(962, 15, 0) 2416 }; 2417 static uint32_t BCMI_TSCF_XGXS_PATT_GEN_SEQ_10r_fields[] = 2418 { 2419 /* PATT_GEN_SEQ_10:0:15 */ 2420 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(950, 15, 0) 2421 }; 2422 static uint32_t BCMI_TSCF_XGXS_PATT_GEN_SEQ_11r_fields[] = 2423 { 2424 /* PATT_GEN_SEQ_11:0:15 */ 2425 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(951, 15, 0) 2426 }; 2427 static uint32_t BCMI_TSCF_XGXS_PATT_GEN_SEQ_12r_fields[] = 2428 { 2429 /* PATT_GEN_SEQ_12:0:15 */ 2430 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(952, 15, 0) 2431 }; 2432 static uint32_t BCMI_TSCF_XGXS_PATT_GEN_SEQ_13r_fields[] = 2433 { 2434 /* PATT_GEN_SEQ_13:0:15 */ 2435 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(953, 15, 0) 2436 }; 2437 static uint32_t BCMI_TSCF_XGXS_PATT_GEN_SEQ_14r_fields[] = 2438 { 2439 /* PATT_GEN_SEQ_14:0:15 */ 2440 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(954, 15, 0) 2441 }; 2442 static uint32_t BCMI_TSCF_XGXS_PHYID2r_fields[] = 2443 { 2444 /* REGID1:0:15 */ 2445 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1063, 15, 0) 2446 }; 2447 static uint32_t BCMI_TSCF_XGXS_PHYID3r_fields[] = 2448 { 2449 /* REGID2:0:15 */ 2450 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1064, 15, 0) 2451 }; 2452 static uint32_t BCMI_TSCF_XGXS_PKTGEN_CRCERRCNTr_fields[] = 2453 { 2454 /* CRCERRCNT:0:15 */ 2455 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(540, 15, 0) 2456 }; 2457 static uint32_t BCMI_TSCF_XGXS_PKTGEN_CTL1r_fields[] = 2458 { 2459 /* TX_TEST_PORT_SEL:0:1 */ 2460 PHYMOD_SYMBOL_FIELD_ENCODE(1485, 1, 0), 2461 /* LPI_EN:2:2 */ 2462 PHYMOD_SYMBOL_FIELD_ENCODE(815, 2, 2), 2463 /* PRTP_DATA_PATTERN_SEL:3:6 */ 2464 PHYMOD_SYMBOL_FIELD_ENCODE(1048, 6, 3), 2465 /* RX_PORT_SEL:7:8 */ 2466 PHYMOD_SYMBOL_FIELD_ENCODE(1261, 8, 7), 2467 /* CLR_CRCCNT:9:9 */ 2468 PHYMOD_SYMBOL_FIELD_ENCODE(508, 9, 9), 2469 /* RX_MSBUS_TYPE:10:10 */ 2470 PHYMOD_SYMBOL_FIELD_ENCODE(1238, 10, 10), 2471 /* RX_PKT_CHECK_EN:11:11 */ 2472 PHYMOD_SYMBOL_FIELD_ENCODE(1259, 11, 11), 2473 /* NUMBER_PKT:12:15 */ 2474 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(921, 15, 12) 2475 }; 2476 static uint32_t BCMI_TSCF_XGXS_PKTGEN_CTL2r_fields[] = 2477 { 2478 /* IPG_SIZE:0:4 */ 2479 PHYMOD_SYMBOL_FIELD_ENCODE(751, 4, 0), 2480 /* PKT_SIZE:5:10 */ 2481 PHYMOD_SYMBOL_FIELD_ENCODE(978, 10, 5), 2482 /* PAYLOAD_TYPE:11:13 */ 2483 PHYMOD_SYMBOL_FIELD_ENCODE(965, 13, 11), 2484 /* TX_MSBUS_TYPE:14:14 */ 2485 PHYMOD_SYMBOL_FIELD_ENCODE(1444, 14, 14), 2486 /* PKTGEN_EN:15:15 */ 2487 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(977, 15, 15) 2488 }; 2489 static uint32_t BCMI_TSCF_XGXS_PKTGEN_CTL3r_fields[] = 2490 { 2491 /* CLR_TXCNT:1:4 */ 2492 PHYMOD_SYMBOL_FIELD_ENCODE(510, 4, 1), 2493 /* CLR_RXCNT:5:8 */ 2494 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(509, 8, 5) 2495 }; 2496 static uint32_t BCMI_TSCF_XGXS_PKTGEN_ERRMASK0r_fields[] = 2497 { 2498 /* ERROR_MASK_15_0:0:15 */ 2499 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(667, 15, 0) 2500 }; 2501 static uint32_t BCMI_TSCF_XGXS_PKTGEN_ERRMASK1r_fields[] = 2502 { 2503 /* ERROR_MASK_31_16:0:15 */ 2504 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(668, 15, 0) 2505 }; 2506 static uint32_t BCMI_TSCF_XGXS_PKTGEN_ERRMASK2r_fields[] = 2507 { 2508 /* ERROR_MASK_47_32:0:15 */ 2509 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(669, 15, 0) 2510 }; 2511 static uint32_t BCMI_TSCF_XGXS_PKTGEN_ERRMASK3r_fields[] = 2512 { 2513 /* ERROR_MASK_63_48:0:15 */ 2514 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(670, 15, 0) 2515 }; 2516 static uint32_t BCMI_TSCF_XGXS_PKTGEN_ERRMASK4r_fields[] = 2517 { 2518 /* ERROR_MASK_65_64:0:1 */ 2519 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(671, 1, 0) 2520 }; 2521 static uint32_t BCMI_TSCF_XGXS_PKTGEN_ERR_INJ_EN0r_fields[] = 2522 { 2523 /* ERRGEN_EN_PH0:0:4 */ 2524 PHYMOD_SYMBOL_FIELD_ENCODE(659, 4, 0), 2525 /* ERRGEN_EN_PH1:5:9 */ 2526 PHYMOD_SYMBOL_FIELD_ENCODE(660, 9, 5), 2527 /* ERRGEN_EN_PH2:10:14 */ 2528 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(661, 14, 10) 2529 }; 2530 static uint32_t BCMI_TSCF_XGXS_PKTGEN_ERR_INJ_EN1r_fields[] = 2531 { 2532 /* ERRGEN_EN_PH3:0:4 */ 2533 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(662, 4, 0) 2534 }; 2535 static uint32_t BCMI_TSCF_XGXS_PKTGEN_PAYLOADBYTESr_fields[] = 2536 { 2537 /* BYTE0:0:7 */ 2538 PHYMOD_SYMBOL_FIELD_ENCODE(337, 7, 0), 2539 /* BYTE1:8:15 */ 2540 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(338, 15, 8) 2541 }; 2542 static uint32_t BCMI_TSCF_XGXS_PKTGEN_PCS_SEEDA0r_fields[] = 2543 { 2544 /* SEEDA0:0:15 */ 2545 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1282, 15, 0) 2546 }; 2547 static uint32_t BCMI_TSCF_XGXS_PKTGEN_PCS_SEEDA1r_fields[] = 2548 { 2549 /* SEEDA1:0:15 */ 2550 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1283, 15, 0) 2551 }; 2552 static uint32_t BCMI_TSCF_XGXS_PKTGEN_PCS_SEEDA2r_fields[] = 2553 { 2554 /* SEEDA2:0:15 */ 2555 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1284, 15, 0) 2556 }; 2557 static uint32_t BCMI_TSCF_XGXS_PKTGEN_PCS_SEEDA3r_fields[] = 2558 { 2559 /* SEEDA3:0:9 */ 2560 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1285, 9, 0) 2561 }; 2562 static uint32_t BCMI_TSCF_XGXS_PKTGEN_PCS_SEEDB0r_fields[] = 2563 { 2564 /* SEEDB0:0:15 */ 2565 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1286, 15, 0) 2566 }; 2567 static uint32_t BCMI_TSCF_XGXS_PKTGEN_PCS_SEEDB1r_fields[] = 2568 { 2569 /* SEEDB1:0:15 */ 2570 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1287, 15, 0) 2571 }; 2572 static uint32_t BCMI_TSCF_XGXS_PKTGEN_PCS_SEEDB2r_fields[] = 2573 { 2574 /* SEEDB2:0:15 */ 2575 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1288, 15, 0) 2576 }; 2577 static uint32_t BCMI_TSCF_XGXS_PKTGEN_PCS_SEEDB3r_fields[] = 2578 { 2579 /* SEEDB3:0:9 */ 2580 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1289, 9, 0) 2581 }; 2582 static uint32_t BCMI_TSCF_XGXS_PKTGEN_PRTPCTLr_fields[] = 2583 { 2584 /* RX_PRTP_EN:8:11 */ 2585 PHYMOD_SYMBOL_FIELD_ENCODE(1262, 11, 8), 2586 /* TX_PRTP_EN:12:15 */ 2587 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1479, 15, 12) 2588 }; 2589 static uint32_t BCMI_TSCF_XGXS_PLL_CAL_CTL0r_fields[] = 2590 { 2591 /* VCO_STEP_TIME:0:7 */ 2592 PHYMOD_SYMBOL_FIELD_ENCODE(1530, 7, 0), 2593 /* VCO_START_TIME:8:15 */ 2594 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1529, 15, 8) 2595 }; 2596 static uint32_t BCMI_TSCF_XGXS_PLL_CAL_CTL1r_fields[] = 2597 { 2598 /* RETRY_TIME:0:7 */ 2599 PHYMOD_SYMBOL_FIELD_ENCODE(1081, 7, 0), 2600 /* PRE_FREQ_DET_TIME:8:15 */ 2601 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1046, 15, 8) 2602 }; 2603 static uint32_t BCMI_TSCF_XGXS_PLL_CAL_CTL2r_fields[] = 2604 { 2605 /* WIN_CAL_CNTR:0:7 */ 2606 PHYMOD_SYMBOL_FIELD_ENCODE(1535, 7, 0), 2607 /* RES_CAL_CNTR:8:15 */ 2608 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1080, 15, 8) 2609 }; 2610 static uint32_t BCMI_TSCF_XGXS_PLL_CAL_CTL3r_fields[] = 2611 { 2612 /* FAST_SEARCH_MODE:0:0 */ 2613 PHYMOD_SYMBOL_FIELD_ENCODE(683, 0, 0), 2614 /* CAP_CNT_MASK_EN:1:1 */ 2615 PHYMOD_SYMBOL_FIELD_ENCODE(339, 1, 1), 2616 /* CAP_SEQ_CYA:2:2 */ 2617 PHYMOD_SYMBOL_FIELD_ENCODE(351, 2, 2), 2618 /* CAP_RESTART:3:3 */ 2619 PHYMOD_SYMBOL_FIELD_ENCODE(346, 3, 3), 2620 /* CAP_RETRY_EN:4:4 */ 2621 PHYMOD_SYMBOL_FIELD_ENCODE(347, 4, 4), 2622 /* CAP_FORCE_SLOWDOWN:5:5 */ 2623 PHYMOD_SYMBOL_FIELD_ENCODE(342, 5, 5), 2624 /* CAP_FORCE_SLOWDOWN_EN:6:6 */ 2625 PHYMOD_SYMBOL_FIELD_ENCODE(343, 6, 6), 2626 /* CAP_SELECT_M_EN:7:7 */ 2627 PHYMOD_SYMBOL_FIELD_ENCODE(350, 7, 7), 2628 /* CAP_SELECT_M:8:15 */ 2629 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(349, 15, 8) 2630 }; 2631 static uint32_t BCMI_TSCF_XGXS_PLL_CAL_CTL4r_fields[] = 2632 { 2633 /* PLL_LOCK_FRC_VAL:0:0 */ 2634 PHYMOD_SYMBOL_FIELD_ENCODE(988, 0, 0), 2635 /* PLL_LOCK_FRC:1:1 */ 2636 PHYMOD_SYMBOL_FIELD_ENCODE(987, 1, 1), 2637 /* PLL_FORCE_CAP_PASS:2:2 */ 2638 PHYMOD_SYMBOL_FIELD_ENCODE(981, 2, 2), 2639 /* PLL_FORCE_CAP_PASS_EN:3:3 */ 2640 PHYMOD_SYMBOL_FIELD_ENCODE(982, 3, 3), 2641 /* PLL_FORCE_CAP_DONE:4:4 */ 2642 PHYMOD_SYMBOL_FIELD_ENCODE(979, 4, 4), 2643 /* PLL_FORCE_CAP_DONE_EN:5:5 */ 2644 PHYMOD_SYMBOL_FIELD_ENCODE(980, 5, 5), 2645 /* PLL_FORCE_FPASS:6:6 */ 2646 PHYMOD_SYMBOL_FIELD_ENCODE(985, 6, 6), 2647 /* PLL_FORCE_FDONE:7:7 */ 2648 PHYMOD_SYMBOL_FIELD_ENCODE(983, 7, 7), 2649 /* PLL_FORCE_FDONE_EN:8:8 */ 2650 PHYMOD_SYMBOL_FIELD_ENCODE(984, 8, 8), 2651 /* VCO_RST_EN:9:9 */ 2652 PHYMOD_SYMBOL_FIELD_ENCODE(1528, 9, 9), 2653 /* SLOWDN_XOR:10:10 */ 2654 PHYMOD_SYMBOL_FIELD_ENCODE(1310, 10, 10), 2655 /* FREQ_MONITOR_EN:11:11 */ 2656 PHYMOD_SYMBOL_FIELD_ENCODE(721, 11, 11), 2657 /* FREQ_DET_RESTART_EN:12:12 */ 2658 PHYMOD_SYMBOL_FIELD_ENCODE(717, 12, 12), 2659 /* FREQ_DET_RETRY_EN:13:13 */ 2660 PHYMOD_SYMBOL_FIELD_ENCODE(718, 13, 13), 2661 /* VCO_DONE_EN:14:14 */ 2662 PHYMOD_SYMBOL_FIELD_ENCODE(1526, 14, 14), 2663 /* PLL_SEQ_START:15:15 */ 2664 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1000, 15, 15) 2665 }; 2666 static uint32_t BCMI_TSCF_XGXS_PLL_CAL_CTL5r_fields[] = 2667 { 2668 /* REFCLK_DIVCNT:0:13 */ 2669 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1060, 13, 0) 2670 }; 2671 static uint32_t BCMI_TSCF_XGXS_PLL_CAL_CTL6r_fields[] = 2672 { 2673 /* REFCLK_DIVCNT_SEL:0:2 */ 2674 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1061, 2, 0) 2675 }; 2676 static uint32_t BCMI_TSCF_XGXS_PLL_CAL_CTL7r_fields[] = 2677 { 2678 /* PLL_MODE:0:3 */ 2679 PHYMOD_SYMBOL_FIELD_ENCODE(994, 3, 0), 2680 /* RESCAL_FRC_VAL:4:7 */ 2681 PHYMOD_SYMBOL_FIELD_ENCODE(1070, 7, 4), 2682 /* RESCAL_FRC:8:8 */ 2683 PHYMOD_SYMBOL_FIELD_ENCODE(1069, 8, 8), 2684 /* VCO_RANGE_ADJUST:9:13 */ 2685 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1527, 13, 9) 2686 }; 2687 static uint32_t BCMI_TSCF_XGXS_PLL_CAL_CTL_STS0r_fields[] = 2688 { 2689 /* PLL_LOCK_LH_LL:0:0 */ 2690 PHYMOD_SYMBOL_FIELD_ENCODE(989, 0, 0), 2691 /* PLL_SEQ_PASS_LH_LL:1:1 */ 2692 PHYMOD_SYMBOL_FIELD_ENCODE(999, 1, 1), 2693 /* PLL_SEQ_DONE_LH_LL:2:2 */ 2694 PHYMOD_SYMBOL_FIELD_ENCODE(997, 2, 2), 2695 /* FREQ_PASS_SM_LH_LL:3:3 */ 2696 PHYMOD_SYMBOL_FIELD_ENCODE(723, 3, 3), 2697 /* FREQ_DONE_SM_LH_LL:4:4 */ 2698 PHYMOD_SYMBOL_FIELD_ENCODE(720, 4, 4), 2699 /* CAP_PASS_LH_LL:5:5 */ 2700 PHYMOD_SYMBOL_FIELD_ENCODE(345, 5, 5), 2701 /* CAP_DONE_LH_LL:6:6 */ 2702 PHYMOD_SYMBOL_FIELD_ENCODE(341, 6, 6), 2703 /* PLL_LOCK:8:8 */ 2704 PHYMOD_SYMBOL_FIELD_ENCODE(986, 8, 8), 2705 /* PLL_SEQ_PASS:9:9 */ 2706 PHYMOD_SYMBOL_FIELD_ENCODE(998, 9, 9), 2707 /* PLL_SEQ_DONE:10:10 */ 2708 PHYMOD_SYMBOL_FIELD_ENCODE(996, 10, 10), 2709 /* FREQ_PASS_SM:11:11 */ 2710 PHYMOD_SYMBOL_FIELD_ENCODE(722, 11, 11), 2711 /* FREQ_DONE_SM:12:12 */ 2712 PHYMOD_SYMBOL_FIELD_ENCODE(719, 12, 12), 2713 /* CAP_PASS:13:13 */ 2714 PHYMOD_SYMBOL_FIELD_ENCODE(344, 13, 13), 2715 /* CAP_DONE:14:14 */ 2716 PHYMOD_SYMBOL_FIELD_ENCODE(340, 14, 14), 2717 /* LOST_PLL_LOCK_SM:15:15 */ 2718 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(812, 15, 15) 2719 }; 2720 static uint32_t BCMI_TSCF_XGXS_PLL_CAL_CTL_STS1r_fields[] = 2721 { 2722 /* CAP_SELECT:0:7 */ 2723 PHYMOD_SYMBOL_FIELD_ENCODE(348, 7, 0), 2724 /* RESCAL_IN:8:11 */ 2725 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1071, 11, 8) 2726 }; 2727 static uint32_t BCMI_TSCF_XGXS_PLL_CAL_CTL_STS_DBGr_fields[] = 2728 { 2729 /* DBG_SLOWDN:0:0 */ 2730 PHYMOD_SYMBOL_FIELD_ENCODE(563, 0, 0), 2731 /* DBG_SLOWDN_CHANGE:1:1 */ 2732 PHYMOD_SYMBOL_FIELD_ENCODE(564, 1, 1), 2733 /* DBG_FDBCK:2:2 */ 2734 PHYMOD_SYMBOL_FIELD_ENCODE(560, 2, 2), 2735 /* DBG_CAP_STATE_ONE_HOT:3:7 */ 2736 PHYMOD_SYMBOL_FIELD_ENCODE(547, 7, 3), 2737 /* DBG_PLL_STATE_ONE_HOT:8:15 */ 2738 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(562, 15, 8) 2739 }; 2740 static uint32_t BCMI_TSCF_XGXS_PMD_X1_CTLr_fields[] = 2741 { 2742 /* CORE_DP_H_RSTB:0:0 */ 2743 PHYMOD_SYMBOL_FIELD_ENCODE(523, 0, 0), 2744 /* POR_H_RSTB:1:1 */ 2745 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1020, 1, 1) 2746 }; 2747 static uint32_t BCMI_TSCF_XGXS_PMD_X1_MODEr_fields[] = 2748 { 2749 /* CORE_MODE:0:15 */ 2750 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(527, 15, 0) 2751 }; 2752 static uint32_t BCMI_TSCF_XGXS_PMD_X1_OVRRr_fields[] = 2753 { 2754 /* PLL_LOCK_OVRD:0:0 */ 2755 PHYMOD_SYMBOL_FIELD_ENCODE(990, 0, 0), 2756 /* TX_CLK_VLD_OVRD:1:1 */ 2757 PHYMOD_SYMBOL_FIELD_ENCODE(1428, 1, 1), 2758 /* CORE_MODE_OEN:2:2 */ 2759 PHYMOD_SYMBOL_FIELD_ENCODE(528, 2, 2), 2760 /* CORE_DP_H_RSTB_OEN:3:3 */ 2761 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(524, 3, 3) 2762 }; 2763 static uint32_t BCMI_TSCF_XGXS_PMD_X1_STSr_fields[] = 2764 { 2765 /* PLL_LOCK_STS:0:0 */ 2766 PHYMOD_SYMBOL_FIELD_ENCODE(991, 0, 0), 2767 /* TX_CLK_VLD_STS:1:1 */ 2768 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1429, 1, 1) 2769 }; 2770 static uint32_t BCMI_TSCF_XGXS_PMD_X4_CTLr_fields[] = 2771 { 2772 /* LN_DP_H_RSTB:0:0 */ 2773 PHYMOD_SYMBOL_FIELD_ENCODE(785, 0, 0), 2774 /* LN_H_RSTB:1:1 */ 2775 PHYMOD_SYMBOL_FIELD_ENCODE(788, 1, 1), 2776 /* LN_TX_H_PWRDN:2:2 */ 2777 PHYMOD_SYMBOL_FIELD_ENCODE(798, 2, 2), 2778 /* LN_RX_H_PWRDN:3:3 */ 2779 PHYMOD_SYMBOL_FIELD_ENCODE(790, 3, 3), 2780 /* TX_DISABLE:8:8 */ 2781 PHYMOD_SYMBOL_FIELD_ENCODE(1430, 8, 8), 2782 /* OSR_MODE:9:12 */ 2783 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(934, 12, 9) 2784 }; 2785 static uint32_t BCMI_TSCF_XGXS_PMD_X4_EEE_CTLr_fields[] = 2786 { 2787 /* TX_MODE:0:1 */ 2788 PHYMOD_SYMBOL_FIELD_ENCODE(1443, 1, 0), 2789 /* RX_MODE:2:2 */ 2790 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1234, 2, 2) 2791 }; 2792 static uint32_t BCMI_TSCF_XGXS_PMD_X4_EEE_STSr_fields[] = 2793 { 2794 /* ENERGY_DETECT:0:0 */ 2795 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(654, 0, 0) 2796 }; 2797 static uint32_t BCMI_TSCF_XGXS_PMD_X4_LATCH_STSr_fields[] = 2798 { 2799 /* RX_LOCK_LL:0:0 */ 2800 PHYMOD_SYMBOL_FIELD_ENCODE(1231, 0, 0), 2801 /* RX_LOCK_LH:1:1 */ 2802 PHYMOD_SYMBOL_FIELD_ENCODE(1230, 1, 1), 2803 /* SIGNAL_DETECT_LL:2:2 */ 2804 PHYMOD_SYMBOL_FIELD_ENCODE(1301, 2, 2), 2805 /* SIGNAL_DETECT_LH:3:3 */ 2806 PHYMOD_SYMBOL_FIELD_ENCODE(1300, 3, 3), 2807 /* RX_CLK_VLD_LL:4:4 */ 2808 PHYMOD_SYMBOL_FIELD_ENCODE(1219, 4, 4), 2809 /* RX_CLK_VLD_LH:5:5 */ 2810 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1218, 5, 5) 2811 }; 2812 static uint32_t BCMI_TSCF_XGXS_PMD_X4_MODEr_fields[] = 2813 { 2814 /* LANE_MODE:0:15 */ 2815 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(766, 15, 0) 2816 }; 2817 static uint32_t BCMI_TSCF_XGXS_PMD_X4_OVRRr_fields[] = 2818 { 2819 /* RX_LOCK_OVRD:0:0 */ 2820 PHYMOD_SYMBOL_FIELD_ENCODE(1232, 0, 0), 2821 /* SIGNAL_DETECT_OVRD:1:1 */ 2822 PHYMOD_SYMBOL_FIELD_ENCODE(1302, 1, 1), 2823 /* RX_CLK_VLD_OVRD:2:2 */ 2824 PHYMOD_SYMBOL_FIELD_ENCODE(1220, 2, 2), 2825 /* LANE_MODE_OEN:3:3 */ 2826 PHYMOD_SYMBOL_FIELD_ENCODE(767, 3, 3), 2827 /* OSR_MODE_OEN:4:4 */ 2828 PHYMOD_SYMBOL_FIELD_ENCODE(937, 4, 4), 2829 /* TX_DISABLE_OEN:5:5 */ 2830 PHYMOD_SYMBOL_FIELD_ENCODE(1431, 5, 5), 2831 /* LN_DP_H_RSTB_OEN:6:6 */ 2832 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(786, 6, 6) 2833 }; 2834 static uint32_t BCMI_TSCF_XGXS_PMD_X4_STSr_fields[] = 2835 { 2836 /* RX_LOCK_STS:0:0 */ 2837 PHYMOD_SYMBOL_FIELD_ENCODE(1233, 0, 0), 2838 /* SIGNAL_DETECT_STS:1:1 */ 2839 PHYMOD_SYMBOL_FIELD_ENCODE(1305, 1, 1), 2840 /* RX_CLK_VLD_STS:2:2 */ 2841 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1221, 2, 2) 2842 }; 2843 static uint32_t BCMI_TSCF_XGXS_RX_X1_CL91_CFGr_fields[] = 2844 { 2845 /* RX_CL91_FEC_EN:0:0 */ 2846 PHYMOD_SYMBOL_FIELD_ENCODE(1217, 0, 0), 2847 /* SET_SYMB_ERR_WINDOW_128:1:1 */ 2848 PHYMOD_SYMBOL_FIELD_ENCODE(1292, 1, 1), 2849 /* FEC_BYP_CORR_EN:2:2 */ 2850 PHYMOD_SYMBOL_FIELD_ENCODE(688, 2, 2), 2851 /* FEC_BYP_IND_EN:3:3 */ 2852 PHYMOD_SYMBOL_FIELD_ENCODE(690, 3, 3), 2853 /* FEC_DBG_BYP_CORR:4:4 */ 2854 PHYMOD_SYMBOL_FIELD_ENCODE(691, 4, 4), 2855 /* CL91_AM_SPACING_1024:5:5 */ 2856 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(444, 5, 5) 2857 }; 2858 static uint32_t BCMI_TSCF_XGXS_RX_X1_CL91_RXP_STSr_fields[] = 2859 { 2860 /* RESTART_LOCK_LIVE:0:0 */ 2861 PHYMOD_SYMBOL_FIELD_ENCODE(1075, 0, 0), 2862 /* RESTART_LOCK_LL:1:1 */ 2863 PHYMOD_SYMBOL_FIELD_ENCODE(1076, 1, 1), 2864 /* RESTART_LOCK_LH:2:2 */ 2865 PHYMOD_SYMBOL_FIELD_ENCODE(1074, 2, 2), 2866 /* FEC_ALIGN_STATUS_LIVE:3:3 */ 2867 PHYMOD_SYMBOL_FIELD_ENCODE(685, 3, 3), 2868 /* FEC_ALIGN_STATUS_LL:4:4 */ 2869 PHYMOD_SYMBOL_FIELD_ENCODE(686, 4, 4), 2870 /* FEC_ALIGN_STATUS_LH:5:5 */ 2871 PHYMOD_SYMBOL_FIELD_ENCODE(684, 5, 5), 2872 /* HI_SER_LIVE:6:6 */ 2873 PHYMOD_SYMBOL_FIELD_ENCODE(736, 6, 6), 2874 /* HI_SER_LL:7:7 */ 2875 PHYMOD_SYMBOL_FIELD_ENCODE(737, 7, 7), 2876 /* HI_SER_LH:8:8 */ 2877 PHYMOD_SYMBOL_FIELD_ENCODE(735, 8, 8), 2878 /* FEC_BYP_CORR_ABILITY:9:9 */ 2879 PHYMOD_SYMBOL_FIELD_ENCODE(687, 9, 9), 2880 /* FEC_BYP_IND_ABILITY:10:10 */ 2881 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(689, 10, 10) 2882 }; 2883 static uint32_t BCMI_TSCF_XGXS_RX_X1_CL91_THRr_fields[] = 2884 { 2885 /* SYMBOL_ERR_CNT_THRESHOLD:0:10 */ 2886 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1327, 10, 0) 2887 }; 2888 static uint32_t BCMI_TSCF_XGXS_RX_X1_CL91_TMRr_fields[] = 2889 { 2890 /* SYMBOL_ERROR_TMR_PERIOD:0:12 */ 2891 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1326, 12, 0) 2892 }; 2893 static uint32_t BCMI_TSCF_XGXS_RX_X1_DEC_CTL1r_fields[] = 2894 { 2895 /* CL49_BER_LIMIT:2:7 */ 2896 PHYMOD_SYMBOL_FIELD_ENCODE(393, 7, 2), 2897 /* CL82_BER_LIMIT:8:14 */ 2898 PHYMOD_SYMBOL_FIELD_ENCODE(429, 14, 8), 2899 /* SET_BER_WINDOW_512:15:15 */ 2900 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1290, 15, 15) 2901 }; 2902 static uint32_t BCMI_TSCF_XGXS_RX_X1_DESKEW_WINSr_fields[] = 2903 { 2904 /* CL82_DSWIN_100G_CL91:0:6 */ 2905 PHYMOD_SYMBOL_FIELD_ENCODE(433, 6, 0), 2906 /* CL82_DSWIN:7:11 */ 2907 PHYMOD_SYMBOL_FIELD_ENCODE(431, 11, 7), 2908 /* CL82_DSWIN_100G:12:15 */ 2909 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(432, 15, 12) 2910 }; 2911 static uint32_t BCMI_TSCF_XGXS_RX_X1_ECC_CORRUPTr_fields[] = 2912 { 2913 /* CORRUPT_ECC_FEC_MEM_0:0:1 */ 2914 PHYMOD_SYMBOL_FIELD_ENCODE(536, 1, 0), 2915 /* CORRUPT_ECC_FEC_MEM_1:2:3 */ 2916 PHYMOD_SYMBOL_FIELD_ENCODE(537, 3, 2), 2917 /* CORRUPT_ECC_FEC_MEM_2:4:5 */ 2918 PHYMOD_SYMBOL_FIELD_ENCODE(538, 5, 4), 2919 /* CORRUPT_ECC_FEC_MEM_3:6:7 */ 2920 PHYMOD_SYMBOL_FIELD_ENCODE(539, 7, 6), 2921 /* CORRUPT_ECC_DESKEW_MEM_0:8:9 */ 2922 PHYMOD_SYMBOL_FIELD_ENCODE(532, 9, 8), 2923 /* CORRUPT_ECC_DESKEW_MEM_1:10:11 */ 2924 PHYMOD_SYMBOL_FIELD_ENCODE(533, 11, 10), 2925 /* CORRUPT_ECC_DESKEW_MEM_2:12:13 */ 2926 PHYMOD_SYMBOL_FIELD_ENCODE(534, 13, 12), 2927 /* CORRUPT_ECC_DESKEW_MEM_3:14:15 */ 2928 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(535, 15, 14) 2929 }; 2930 static uint32_t BCMI_TSCF_XGXS_RX_X1_ECC_DIS_ECC_MEMr_fields[] = 2931 { 2932 /* DISABLE_ECC_FEC_MEM_0:0:0 */ 2933 PHYMOD_SYMBOL_FIELD_ENCODE(621, 0, 0), 2934 /* DISABLE_ECC_FEC_MEM_1:1:1 */ 2935 PHYMOD_SYMBOL_FIELD_ENCODE(622, 1, 1), 2936 /* DISABLE_ECC_FEC_MEM_2:2:2 */ 2937 PHYMOD_SYMBOL_FIELD_ENCODE(623, 2, 2), 2938 /* DISABLE_ECC_FEC_MEM_3:3:3 */ 2939 PHYMOD_SYMBOL_FIELD_ENCODE(624, 3, 3), 2940 /* DISABLE_ECC_DESKEW_MEM_0:4:4 */ 2941 PHYMOD_SYMBOL_FIELD_ENCODE(617, 4, 4), 2942 /* DISABLE_ECC_DESKEW_MEM_1:5:5 */ 2943 PHYMOD_SYMBOL_FIELD_ENCODE(618, 5, 5), 2944 /* DISABLE_ECC_DESKEW_MEM_2:6:6 */ 2945 PHYMOD_SYMBOL_FIELD_ENCODE(619, 6, 6), 2946 /* DISABLE_ECC_DESKEW_MEM_3:7:7 */ 2947 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(620, 7, 7) 2948 }; 2949 static uint32_t BCMI_TSCF_XGXS_RX_X1_ECC_INTR_EN_1BITr_fields[] = 2950 { 2951 /* FEC_MEM_0_1BIT_INT_EN:0:0 */ 2952 PHYMOD_SYMBOL_FIELD_ENCODE(695, 0, 0), 2953 /* FEC_MEM_1_1BIT_INT_EN:1:1 */ 2954 PHYMOD_SYMBOL_FIELD_ENCODE(699, 1, 1), 2955 /* FEC_MEM_2_1BIT_INT_EN:2:2 */ 2956 PHYMOD_SYMBOL_FIELD_ENCODE(703, 2, 2), 2957 /* FEC_MEM_3_1BIT_INT_EN:3:3 */ 2958 PHYMOD_SYMBOL_FIELD_ENCODE(707, 3, 3), 2959 /* DESKEW_MEM_0_1BIT_INT_EN:4:4 */ 2960 PHYMOD_SYMBOL_FIELD_ENCODE(588, 4, 4), 2961 /* DESKEW_MEM_1_1BIT_INT_EN:5:5 */ 2962 PHYMOD_SYMBOL_FIELD_ENCODE(592, 5, 5), 2963 /* DESKEW_MEM_2_1BIT_INT_EN:6:6 */ 2964 PHYMOD_SYMBOL_FIELD_ENCODE(596, 6, 6), 2965 /* DESKEW_MEM_3_1BIT_INT_EN:7:7 */ 2966 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(600, 7, 7) 2967 }; 2968 static uint32_t BCMI_TSCF_XGXS_RX_X1_ECC_INTR_EN_2BITr_fields[] = 2969 { 2970 /* FEC_MEM_0_2BIT_INT_EN:0:0 */ 2971 PHYMOD_SYMBOL_FIELD_ENCODE(697, 0, 0), 2972 /* FEC_MEM_1_2BIT_INT_EN:1:1 */ 2973 PHYMOD_SYMBOL_FIELD_ENCODE(701, 1, 1), 2974 /* FEC_MEM_2_2BIT_INT_EN:2:2 */ 2975 PHYMOD_SYMBOL_FIELD_ENCODE(705, 2, 2), 2976 /* FEC_MEM_3_2BIT_INT_EN:3:3 */ 2977 PHYMOD_SYMBOL_FIELD_ENCODE(709, 3, 3), 2978 /* DESKEW_MEM_0_2BIT_INT_EN:4:4 */ 2979 PHYMOD_SYMBOL_FIELD_ENCODE(590, 4, 4), 2980 /* DESKEW_MEM_1_2BIT_INT_EN:5:5 */ 2981 PHYMOD_SYMBOL_FIELD_ENCODE(594, 5, 5), 2982 /* DESKEW_MEM_2_2BIT_INT_EN:6:6 */ 2983 PHYMOD_SYMBOL_FIELD_ENCODE(598, 6, 6), 2984 /* DESKEW_MEM_3_2BIT_INT_EN:7:7 */ 2985 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(602, 7, 7) 2986 }; 2987 static uint32_t BCMI_TSCF_XGXS_RX_X1_ECC_INTR_STS_1BITr_fields[] = 2988 { 2989 /* FEC_MEM_0_1BIT_INT_STATUS:0:0 */ 2990 PHYMOD_SYMBOL_FIELD_ENCODE(696, 0, 0), 2991 /* FEC_MEM_1_1BIT_INT_STATUS:1:1 */ 2992 PHYMOD_SYMBOL_FIELD_ENCODE(700, 1, 1), 2993 /* FEC_MEM_2_1BIT_INT_STATUS:2:2 */ 2994 PHYMOD_SYMBOL_FIELD_ENCODE(704, 2, 2), 2995 /* FEC_MEM_3_1BIT_INT_STATUS:3:3 */ 2996 PHYMOD_SYMBOL_FIELD_ENCODE(708, 3, 3), 2997 /* DESKEW_MEM_0_1BIT_INT_STATUS:4:4 */ 2998 PHYMOD_SYMBOL_FIELD_ENCODE(589, 4, 4), 2999 /* DESKEW_MEM_1_1BIT_INT_STATUS:5:5 */ 3000 PHYMOD_SYMBOL_FIELD_ENCODE(593, 5, 5), 3001 /* DESKEW_MEM_2_1BIT_INT_STATUS:6:6 */ 3002 PHYMOD_SYMBOL_FIELD_ENCODE(597, 6, 6), 3003 /* DESKEW_MEM_3_1BIT_INT_STATUS:7:7 */ 3004 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(601, 7, 7) 3005 }; 3006 static uint32_t BCMI_TSCF_XGXS_RX_X1_ECC_INTR_STS_2BITr_fields[] = 3007 { 3008 /* FEC_MEM_0_2BIT_INT_STATUS:0:0 */ 3009 PHYMOD_SYMBOL_FIELD_ENCODE(698, 0, 0), 3010 /* FEC_MEM_1_2BIT_INT_STATUS:1:1 */ 3011 PHYMOD_SYMBOL_FIELD_ENCODE(702, 1, 1), 3012 /* FEC_MEM_2_2BIT_INT_STATUS:2:2 */ 3013 PHYMOD_SYMBOL_FIELD_ENCODE(706, 2, 2), 3014 /* FEC_MEM_3_2BIT_INT_STATUS:3:3 */ 3015 PHYMOD_SYMBOL_FIELD_ENCODE(710, 3, 3), 3016 /* DESKEW_MEM_0_2BIT_INT_STATUS:4:4 */ 3017 PHYMOD_SYMBOL_FIELD_ENCODE(591, 4, 4), 3018 /* DESKEW_MEM_1_2BIT_INT_STATUS:5:5 */ 3019 PHYMOD_SYMBOL_FIELD_ENCODE(595, 5, 5), 3020 /* DESKEW_MEM_2_2BIT_INT_STATUS:6:6 */ 3021 PHYMOD_SYMBOL_FIELD_ENCODE(599, 6, 6), 3022 /* DESKEW_MEM_3_2BIT_INT_STATUS:7:7 */ 3023 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(603, 7, 7) 3024 }; 3025 static uint32_t BCMI_TSCF_XGXS_RX_X1_ECC_STS_DESKEW_MEM0r_fields[] = 3026 { 3027 /* ERR_EVENT_ADDRESS_DESKEW_0:0:13 */ 3028 PHYMOD_SYMBOL_FIELD_ENCODE(673, 13, 0), 3029 /* ONE_BIT_ERR_EVENT_DESKEW_0:14:14 */ 3030 PHYMOD_SYMBOL_FIELD_ENCODE(926, 14, 14), 3031 /* TWO_BIT_ERR_EVENT_DESKEW_0:15:15 */ 3032 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1390, 15, 15) 3033 }; 3034 static uint32_t BCMI_TSCF_XGXS_RX_X1_ECC_STS_DESKEW_MEM1r_fields[] = 3035 { 3036 /* ERR_EVENT_ADDRESS_DESKEW_1:0:13 */ 3037 PHYMOD_SYMBOL_FIELD_ENCODE(674, 13, 0), 3038 /* ONE_BIT_ERR_EVENT_DESKEW_1:14:14 */ 3039 PHYMOD_SYMBOL_FIELD_ENCODE(927, 14, 14), 3040 /* TWO_BIT_ERR_EVENT_DESKEW_1:15:15 */ 3041 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1391, 15, 15) 3042 }; 3043 static uint32_t BCMI_TSCF_XGXS_RX_X1_ECC_STS_DESKEW_MEM2r_fields[] = 3044 { 3045 /* ERR_EVENT_ADDRESS_DESKEW_2:0:13 */ 3046 PHYMOD_SYMBOL_FIELD_ENCODE(675, 13, 0), 3047 /* ONE_BIT_ERR_EVENT_DESKEW_2:14:14 */ 3048 PHYMOD_SYMBOL_FIELD_ENCODE(928, 14, 14), 3049 /* TWO_BIT_ERR_EVENT_DESKEW_2:15:15 */ 3050 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1392, 15, 15) 3051 }; 3052 static uint32_t BCMI_TSCF_XGXS_RX_X1_ECC_STS_DESKEW_MEM3r_fields[] = 3053 { 3054 /* ERR_EVENT_ADDRESS_DESKEW_3:0:13 */ 3055 PHYMOD_SYMBOL_FIELD_ENCODE(676, 13, 0), 3056 /* ONE_BIT_ERR_EVENT_DESKEW_3:14:14 */ 3057 PHYMOD_SYMBOL_FIELD_ENCODE(929, 14, 14), 3058 /* TWO_BIT_ERR_EVENT_DESKEW_3:15:15 */ 3059 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1393, 15, 15) 3060 }; 3061 static uint32_t BCMI_TSCF_XGXS_RX_X1_ECC_STS_FEC_MEM0r_fields[] = 3062 { 3063 /* ERR_EVENT_ADDRESS_FEC_0:0:13 */ 3064 PHYMOD_SYMBOL_FIELD_ENCODE(677, 13, 0), 3065 /* ONE_BIT_ERR_EVENT_FEC_0:14:14 */ 3066 PHYMOD_SYMBOL_FIELD_ENCODE(930, 14, 14), 3067 /* TWO_BIT_ERR_EVENT_FEC_0:15:15 */ 3068 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1394, 15, 15) 3069 }; 3070 static uint32_t BCMI_TSCF_XGXS_RX_X1_ECC_STS_FEC_MEM1r_fields[] = 3071 { 3072 /* ERR_EVENT_ADDRESS_FEC_1:0:13 */ 3073 PHYMOD_SYMBOL_FIELD_ENCODE(678, 13, 0), 3074 /* ONE_BIT_ERR_EVENT_FEC_1:14:14 */ 3075 PHYMOD_SYMBOL_FIELD_ENCODE(931, 14, 14), 3076 /* TWO_BIT_ERR_EVENT_FEC_1:15:15 */ 3077 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1395, 15, 15) 3078 }; 3079 static uint32_t BCMI_TSCF_XGXS_RX_X1_ECC_STS_FEC_MEM2r_fields[] = 3080 { 3081 /* ERR_EVENT_ADDRESS_FEC_2:0:13 */ 3082 PHYMOD_SYMBOL_FIELD_ENCODE(679, 13, 0), 3083 /* ONE_BIT_ERR_EVENT_FEC_2:14:14 */ 3084 PHYMOD_SYMBOL_FIELD_ENCODE(932, 14, 14), 3085 /* TWO_BIT_ERR_EVENT_FEC_2:15:15 */ 3086 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1396, 15, 15) 3087 }; 3088 static uint32_t BCMI_TSCF_XGXS_RX_X1_ECC_STS_FEC_MEM3r_fields[] = 3089 { 3090 /* ERR_EVENT_ADDRESS_FEC_3:0:13 */ 3091 PHYMOD_SYMBOL_FIELD_ENCODE(680, 13, 0), 3092 /* ONE_BIT_ERR_EVENT_FEC_3:14:14 */ 3093 PHYMOD_SYMBOL_FIELD_ENCODE(933, 14, 14), 3094 /* TWO_BIT_ERR_EVENT_FEC_3:15:15 */ 3095 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1397, 15, 15) 3096 }; 3097 static uint32_t BCMI_TSCF_XGXS_RX_X1_FEC_ALGN_FSM_STr_fields[] = 3098 { 3099 /* CL91_FEC_ALGN_FSM_LIVE_STATE:0:2 */ 3100 PHYMOD_SYMBOL_FIELD_ENCODE(446, 2, 0), 3101 /* CL91_FEC_ALGN_FSM_LATCHED_STATE:3:9 */ 3102 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(445, 9, 3) 3103 }; 3104 static uint32_t BCMI_TSCF_XGXS_RX_X1_FEC_BIT_ERR_CTR0r_fields[] = 3105 { 3106 /* CL91_FEC_CORR_BIT_CNTR_LOWER:0:15 */ 3107 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(447, 15, 0) 3108 }; 3109 static uint32_t BCMI_TSCF_XGXS_RX_X1_FEC_BIT_ERR_CTR1r_fields[] = 3110 { 3111 /* CL91_FEC_CORR_BIT_CNTR_UPPER:0:15 */ 3112 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(448, 15, 0) 3113 }; 3114 static uint32_t BCMI_TSCF_XGXS_RX_X1_FEC_CORR_CTR0r_fields[] = 3115 { 3116 /* CL91_FEC_CORR_CW_CNTR_LOWER:0:15 */ 3117 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(449, 15, 0) 3118 }; 3119 static uint32_t BCMI_TSCF_XGXS_RX_X1_FEC_CORR_CTR1r_fields[] = 3120 { 3121 /* CL91_FEC_CORR_CW_CNTR_UPPER:0:15 */ 3122 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(450, 15, 0) 3123 }; 3124 static uint32_t BCMI_TSCF_XGXS_RX_X1_FEC_UNCORR_CTR0r_fields[] = 3125 { 3126 /* CL91_FEC_UNCORR_CW_CNTR_LOWER:0:15 */ 3127 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(455, 15, 0) 3128 }; 3129 static uint32_t BCMI_TSCF_XGXS_RX_X1_FEC_UNCORR_CTR1r_fields[] = 3130 { 3131 /* CL91_FEC_UNCORR_CW_CNTR_UPPER:0:15 */ 3132 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(456, 15, 0) 3133 }; 3134 static uint32_t BCMI_TSCF_XGXS_RX_X2_MISC0r_fields[] = 3135 { 3136 /* BYPASS_CL82RXSM:0:0 */ 3137 PHYMOD_SYMBOL_FIELD_ENCODE(336, 0, 0), 3138 /* DIS_CL82_BERMON:1:1 */ 3139 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(626, 1, 1) 3140 }; 3141 static uint32_t BCMI_TSCF_XGXS_RX_X2_MISC1r_fields[] = 3142 { 3143 /* CL82_RX_RF_ENABLE:0:0 */ 3144 PHYMOD_SYMBOL_FIELD_ENCODE(437, 0, 0), 3145 /* CL82_RX_LF_ENABLE:1:1 */ 3146 PHYMOD_SYMBOL_FIELD_ENCODE(435, 1, 1), 3147 /* CL82_RX_LI_ENABLE:9:9 */ 3148 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(436, 9, 9) 3149 }; 3150 static uint32_t BCMI_TSCF_XGXS_RX_X4_AM_LOCK_LATCH_STSr_fields[] = 3151 { 3152 /* AM_LOCK_LL_0:0:0 */ 3153 PHYMOD_SYMBOL_FIELD_ENCODE(200, 0, 0), 3154 /* AM_LOCK_LH_0:1:1 */ 3155 PHYMOD_SYMBOL_FIELD_ENCODE(195, 1, 1), 3156 /* AM_LOCK_LL_1:2:2 */ 3157 PHYMOD_SYMBOL_FIELD_ENCODE(201, 2, 2), 3158 /* AM_LOCK_LH_1:3:3 */ 3159 PHYMOD_SYMBOL_FIELD_ENCODE(196, 3, 3), 3160 /* AM_LOCK_LL_2:4:4 */ 3161 PHYMOD_SYMBOL_FIELD_ENCODE(202, 4, 4), 3162 /* AM_LOCK_LH_2:5:5 */ 3163 PHYMOD_SYMBOL_FIELD_ENCODE(197, 5, 5), 3164 /* AM_LOCK_LL_3:6:6 */ 3165 PHYMOD_SYMBOL_FIELD_ENCODE(203, 6, 6), 3166 /* AM_LOCK_LH_3:7:7 */ 3167 PHYMOD_SYMBOL_FIELD_ENCODE(198, 7, 7), 3168 /* AM_LOCK_LL_4:8:8 */ 3169 PHYMOD_SYMBOL_FIELD_ENCODE(204, 8, 8), 3170 /* AM_LOCK_LH_4:9:9 */ 3171 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(199, 9, 9) 3172 }; 3173 static uint32_t BCMI_TSCF_XGXS_RX_X4_BIPCNT0r_fields[] = 3174 { 3175 /* BIP_ERROR_COUNT_0:0:7 */ 3176 PHYMOD_SYMBOL_FIELD_ENCODE(292, 7, 0), 3177 /* BIP_ERROR_COUNT_1:8:15 */ 3178 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(293, 15, 8) 3179 }; 3180 static uint32_t BCMI_TSCF_XGXS_RX_X4_BIPCNT1r_fields[] = 3181 { 3182 /* BIP_ERROR_COUNT_2:0:7 */ 3183 PHYMOD_SYMBOL_FIELD_ENCODE(294, 7, 0), 3184 /* BIP_ERROR_COUNT_3:8:15 */ 3185 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(295, 15, 8) 3186 }; 3187 static uint32_t BCMI_TSCF_XGXS_RX_X4_BIPCNT2r_fields[] = 3188 { 3189 /* BIP_ERROR_COUNT_4:0:7 */ 3190 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(296, 7, 0) 3191 }; 3192 static uint32_t BCMI_TSCF_XGXS_RX_X4_BLKSYNC_CFGr_fields[] = 3193 { 3194 /* BS_BTMX_MODE:0:1 */ 3195 PHYMOD_SYMBOL_FIELD_ENCODE(314, 1, 0), 3196 /* BS_DIST_MODE:2:3 */ 3197 PHYMOD_SYMBOL_FIELD_ENCODE(316, 3, 2), 3198 /* BS_SYNC_EN:4:4 */ 3199 PHYMOD_SYMBOL_FIELD_ENCODE(322, 4, 4), 3200 /* BS_SM_SYNC_MODE:5:5 */ 3201 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(319, 5, 5) 3202 }; 3203 static uint32_t BCMI_TSCF_XGXS_RX_X4_BLKSYNC_DBG0r_fields[] = 3204 { 3205 /* LANE0_DEBUG_INFO:0:7 */ 3206 PHYMOD_SYMBOL_FIELD_ENCODE(752, 7, 0), 3207 /* LANE1_DEBUG_INFO:8:15 */ 3208 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(753, 15, 8) 3209 }; 3210 static uint32_t BCMI_TSCF_XGXS_RX_X4_BLKSYNC_DBG1r_fields[] = 3211 { 3212 /* LANE2_DEBUG_INFO:0:7 */ 3213 PHYMOD_SYMBOL_FIELD_ENCODE(754, 7, 0), 3214 /* LANE3_DEBUG_INFO:8:15 */ 3215 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(755, 15, 8) 3216 }; 3217 static uint32_t BCMI_TSCF_XGXS_RX_X4_BLKSYNC_DBG2r_fields[] = 3218 { 3219 /* LANE4_DEBUG_INFO:0:7 */ 3220 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(756, 7, 0) 3221 }; 3222 static uint32_t BCMI_TSCF_XGXS_RX_X4_BLKSYNC_STSr_fields[] = 3223 { 3224 /* BS_STATUS:0:4 */ 3225 PHYMOD_SYMBOL_FIELD_ENCODE(321, 4, 0), 3226 /* BS_PMD_LOCK:5:5 */ 3227 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(318, 5, 5) 3228 }; 3229 static uint32_t BCMI_TSCF_XGXS_RX_X4_BLK_LOCK_LATCH_STSr_fields[] = 3230 { 3231 /* BLOCK_LOCK_LL_0:0:0 */ 3232 PHYMOD_SYMBOL_FIELD_ENCODE(307, 0, 0), 3233 /* BLOCK_LOCK_LH_0:1:1 */ 3234 PHYMOD_SYMBOL_FIELD_ENCODE(302, 1, 1), 3235 /* BLOCK_LOCK_LL_1:2:2 */ 3236 PHYMOD_SYMBOL_FIELD_ENCODE(308, 2, 2), 3237 /* BLOCK_LOCK_LH_1:3:3 */ 3238 PHYMOD_SYMBOL_FIELD_ENCODE(303, 3, 3), 3239 /* BLOCK_LOCK_LL_2:4:4 */ 3240 PHYMOD_SYMBOL_FIELD_ENCODE(309, 4, 4), 3241 /* BLOCK_LOCK_LH_2:5:5 */ 3242 PHYMOD_SYMBOL_FIELD_ENCODE(304, 5, 5), 3243 /* BLOCK_LOCK_LL_3:6:6 */ 3244 PHYMOD_SYMBOL_FIELD_ENCODE(310, 6, 6), 3245 /* BLOCK_LOCK_LH_3:7:7 */ 3246 PHYMOD_SYMBOL_FIELD_ENCODE(305, 7, 7), 3247 /* BLOCK_LOCK_LL_4:8:8 */ 3248 PHYMOD_SYMBOL_FIELD_ENCODE(311, 8, 8), 3249 /* BLOCK_LOCK_LH_4:9:9 */ 3250 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(306, 9, 9) 3251 }; 3252 static uint32_t BCMI_TSCF_XGXS_RX_X4_CL36_BERCNTr_fields[] = 3253 { 3254 /* CL36RX_BER_COUNT_PER_LN:0:7 */ 3255 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(379, 7, 0) 3256 }; 3257 static uint32_t BCMI_TSCF_XGXS_RX_X4_CL36_CTLr_fields[] = 3258 { 3259 /* CL36RX_EN:0:0 */ 3260 PHYMOD_SYMBOL_FIELD_ENCODE(382, 0, 0), 3261 /* CL36RX_LPI_EN:1:1 */ 3262 PHYMOD_SYMBOL_FIELD_ENCODE(385, 1, 1), 3263 /* CL36RX_DISABLE_CARRIER_EXTEND:2:2 */ 3264 PHYMOD_SYMBOL_FIELD_ENCODE(381, 2, 2), 3265 /* CL36RX_FORCE_COMMA_ALIGN_ENABLE:3:3 */ 3266 PHYMOD_SYMBOL_FIELD_ENCODE(384, 3, 3), 3267 /* CL36RX_BER_EN:4:4 */ 3268 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(380, 4, 4) 3269 }; 3270 static uint32_t BCMI_TSCF_XGXS_RX_X4_CL36_SYNCACQ_STS0r_fields[] = 3271 { 3272 /* CL36RX_SYNCACQ_STATE_CODED_PER_LN:0:3 */ 3273 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(387, 3, 0) 3274 }; 3275 static uint32_t BCMI_TSCF_XGXS_RX_X4_CL36_SYNCACQ_STS1r_fields[] = 3276 { 3277 /* CL36RX_SYNCACQ_HIS_STATE_PER_LN:0:12 */ 3278 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(386, 12, 0) 3279 }; 3280 static uint32_t BCMI_TSCF_XGXS_RX_X4_CL82_AM_LATCH_STS_PSLL0r_fields[] = 3281 { 3282 /* AM_LOCK_HIS_STATE_PSLL_0:0:9 */ 3283 PHYMOD_SYMBOL_FIELD_ENCODE(190, 9, 0), 3284 /* AMRKR_SPACING_ERR_LATCH_MUX_PSLL_0:10:10 */ 3285 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(20, 10, 10) 3286 }; 3287 static uint32_t BCMI_TSCF_XGXS_RX_X4_CL82_AM_LATCH_STS_PSLL1r_fields[] = 3288 { 3289 /* AM_LOCK_HIS_STATE_PSLL_1:0:9 */ 3290 PHYMOD_SYMBOL_FIELD_ENCODE(191, 9, 0), 3291 /* AMRKR_SPACING_ERR_LATCH_MUX_PSLL_1:10:10 */ 3292 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(21, 10, 10) 3293 }; 3294 static uint32_t BCMI_TSCF_XGXS_RX_X4_CL82_AM_LATCH_STS_PSLL2r_fields[] = 3295 { 3296 /* AM_LOCK_HIS_STATE_PSLL_2:0:9 */ 3297 PHYMOD_SYMBOL_FIELD_ENCODE(192, 9, 0), 3298 /* AMRKR_SPACING_ERR_LATCH_MUX_PSLL_2:10:10 */ 3299 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(22, 10, 10) 3300 }; 3301 static uint32_t BCMI_TSCF_XGXS_RX_X4_CL82_AM_LATCH_STS_PSLL3r_fields[] = 3302 { 3303 /* AM_LOCK_HIS_STATE_PSLL_3:0:9 */ 3304 PHYMOD_SYMBOL_FIELD_ENCODE(193, 9, 0), 3305 /* AMRKR_SPACING_ERR_LATCH_MUX_PSLL_3:10:10 */ 3306 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(23, 10, 10) 3307 }; 3308 static uint32_t BCMI_TSCF_XGXS_RX_X4_CL82_AM_LATCH_STS_PSLL4r_fields[] = 3309 { 3310 /* AM_LOCK_HIS_STATE_PSLL_4:0:9 */ 3311 PHYMOD_SYMBOL_FIELD_ENCODE(194, 9, 0), 3312 /* AMRKR_SPACING_ERR_LATCH_MUX_PSLL_4:10:10 */ 3313 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(24, 10, 10) 3314 }; 3315 static uint32_t BCMI_TSCF_XGXS_RX_X4_CL82_AM_LIVE_STS_PSLL0r_fields[] = 3316 { 3317 /* AM_LOCK_STATE_PSLL_0:0:9 */ 3318 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(205, 9, 0) 3319 }; 3320 static uint32_t BCMI_TSCF_XGXS_RX_X4_CL82_AM_LIVE_STS_PSLL1r_fields[] = 3321 { 3322 /* AM_LOCK_STATE_PSLL_1:0:9 */ 3323 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(206, 9, 0) 3324 }; 3325 static uint32_t BCMI_TSCF_XGXS_RX_X4_CL82_AM_LIVE_STS_PSLL2r_fields[] = 3326 { 3327 /* AM_LOCK_STATE_PSLL_2:0:9 */ 3328 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(207, 9, 0) 3329 }; 3330 static uint32_t BCMI_TSCF_XGXS_RX_X4_CL82_AM_LIVE_STS_PSLL3r_fields[] = 3331 { 3332 /* AM_LOCK_STATE_PSLL_3:0:9 */ 3333 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(208, 9, 0) 3334 }; 3335 static uint32_t BCMI_TSCF_XGXS_RX_X4_CL82_AM_LIVE_STS_PSLL4r_fields[] = 3336 { 3337 /* AM_LOCK_STATE_PSLL_4:0:9 */ 3338 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(209, 9, 0) 3339 }; 3340 static uint32_t BCMI_TSCF_XGXS_RX_X4_CL91_FEC_SYM_ERR_CTR0r_fields[] = 3341 { 3342 /* FEC_SYMBOL_ERROR_COUNTER_LOWER:0:15 */ 3343 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(713, 15, 0) 3344 }; 3345 static uint32_t BCMI_TSCF_XGXS_RX_X4_CL91_FEC_SYM_ERR_CTR1r_fields[] = 3346 { 3347 /* FEC_SYMBOL_ERROR_COUNTER_UPPER:0:15 */ 3348 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(714, 15, 0) 3349 }; 3350 static uint32_t BCMI_TSCF_XGXS_RX_X4_CL91_SYNC_STSr_fields[] = 3351 { 3352 /* CL91_AMPS_LOCK_LIVE:0:0 */ 3353 PHYMOD_SYMBOL_FIELD_ENCODE(442, 0, 0), 3354 /* CL91_AMPS_LOCK_LL:1:1 */ 3355 PHYMOD_SYMBOL_FIELD_ENCODE(443, 1, 1), 3356 /* CL91_AMPS_LOCK_LH:2:2 */ 3357 PHYMOD_SYMBOL_FIELD_ENCODE(441, 2, 2), 3358 /* CL91_FEC_LANE_MAP:3:4 */ 3359 PHYMOD_SYMBOL_FIELD_ENCODE(451, 4, 3), 3360 /* CL91_FEC_LANE_MAP_VALID:5:5 */ 3361 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(452, 5, 5) 3362 }; 3363 static uint32_t BCMI_TSCF_XGXS_RX_X4_DEC_CTL0r_fields[] = 3364 { 3365 /* CL49_RX_RF_ENABLE:4:4 */ 3366 PHYMOD_SYMBOL_FIELD_ENCODE(400, 4, 4), 3367 /* CL49_RX_LF_ENABLE:5:5 */ 3368 PHYMOD_SYMBOL_FIELD_ENCODE(398, 5, 5), 3369 /* CL49_RX_LI_ENABLE:6:6 */ 3370 PHYMOD_SYMBOL_FIELD_ENCODE(399, 6, 6), 3371 /* DISABLE_CL49_BERMON:8:8 */ 3372 PHYMOD_SYMBOL_FIELD_ENCODE(616, 8, 8), 3373 /* HG2_CODEC:9:9 */ 3374 PHYMOD_SYMBOL_FIELD_ENCODE(728, 9, 9), 3375 /* HG2_ENABLE:12:12 */ 3376 PHYMOD_SYMBOL_FIELD_ENCODE(729, 12, 12), 3377 /* HG2_MESSAGE_INVALID_CODE_ENABLE:13:13 */ 3378 PHYMOD_SYMBOL_FIELD_ENCODE(730, 13, 13), 3379 /* R_TEST_MODE_CFG:14:14 */ 3380 PHYMOD_SYMBOL_FIELD_ENCODE(1274, 14, 14), 3381 /* BYPASS_CL49RXSM:15:15 */ 3382 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(335, 15, 15) 3383 }; 3384 static uint32_t BCMI_TSCF_XGXS_RX_X4_DEC_STS0r_fields[] = 3385 { 3386 /* BERMON_CURRENT_STATE:0:4 */ 3387 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(288, 4, 0) 3388 }; 3389 static uint32_t BCMI_TSCF_XGXS_RX_X4_DEC_STS1r_fields[] = 3390 { 3391 /* BERMON_HISTORY_STATE:0:4 */ 3392 PHYMOD_SYMBOL_FIELD_ENCODE(289, 4, 0), 3393 /* CL49_RXSM_HISTORY_STATE:5:12 */ 3394 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(397, 12, 5) 3395 }; 3396 static uint32_t BCMI_TSCF_XGXS_RX_X4_DEC_STS2r_fields[] = 3397 { 3398 /* CL49_RXSM_CURRENT_STATE:0:7 */ 3399 PHYMOD_SYMBOL_FIELD_ENCODE(396, 7, 0), 3400 /* CL49_R_TYPE_CODED:8:11 */ 3401 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(401, 11, 8) 3402 }; 3403 static uint32_t BCMI_TSCF_XGXS_RX_X4_DEC_STS3r_fields[] = 3404 { 3405 /* IEEE_ERRORED_BLOCKS:0:7 */ 3406 PHYMOD_SYMBOL_FIELD_ENCODE(743, 7, 0), 3407 /* CL49_BER_COUNT:8:13 */ 3408 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(392, 13, 8) 3409 }; 3410 static uint32_t BCMI_TSCF_XGXS_RX_X4_DESKEW_MEM_CTLr_fields[] = 3411 { 3412 /* DESKEW_MEM_TM:0:11 */ 3413 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(604, 11, 0) 3414 }; 3415 static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC0r_fields[] = 3416 { 3417 /* DBG_ERR_MODE:0:0 */ 3418 PHYMOD_SYMBOL_FIELD_ENCODE(559, 0, 0), 3419 /* BURST_ERR_STATUS_MODE:1:1 */ 3420 PHYMOD_SYMBOL_FIELD_ENCODE(334, 1, 1), 3421 /* DEC_MAX_PM:2:7 */ 3422 PHYMOD_SYMBOL_FIELD_ENCODE(581, 7, 2), 3423 /* INVALID_PARITY_CNT:8:11 */ 3424 PHYMOD_SYMBOL_FIELD_ENCODE(748, 11, 8), 3425 /* GOOD_PARITY_CNT:12:14 */ 3426 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(726, 14, 12) 3427 }; 3428 static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC1r_fields[] = 3429 { 3430 /* DEC_GAP_COUNT_MODE:1:1 */ 3431 PHYMOD_SYMBOL_FIELD_ENCODE(580, 1, 1), 3432 /* DEC_17B_BURST_GAP_COUNT:2:4 */ 3433 PHYMOD_SYMBOL_FIELD_ENCODE(575, 4, 2), 3434 /* DEC_18B_BURST_GAP_COUNT:5:7 */ 3435 PHYMOD_SYMBOL_FIELD_ENCODE(576, 7, 5), 3436 /* DEC_19B_BURST_GAP_COUNT:8:10 */ 3437 PHYMOD_SYMBOL_FIELD_ENCODE(577, 10, 8), 3438 /* DEC_PM_MODE:11:15 */ 3439 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(582, 15, 11) 3440 }; 3441 static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC2r_fields[] = 3442 { 3443 /* FEC_ERROR_CODE_ALL_PER_STREAM:0:4 */ 3444 PHYMOD_SYMBOL_FIELD_ENCODE(693, 4, 0), 3445 /* DBG_ENABLE_PER_STREAM:5:9 */ 3446 PHYMOD_SYMBOL_FIELD_ENCODE(548, 9, 5), 3447 /* FEC_ERR_ENABLE_PER_STREAM:10:14 */ 3448 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(694, 14, 10) 3449 }; 3450 static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC3r_fields[] = 3451 { 3452 /* ERROR_EN_OVR_PER_STREAM:0:4 */ 3453 PHYMOD_SYMBOL_FIELD_ENCODE(665, 4, 0), 3454 /* ERROR_EN_OVR_VAL_PER_STREAM:5:9 */ 3455 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(666, 9, 5) 3456 }; 3457 static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_BURST_ERR_STSH0r_fields[] = 3458 { 3459 /* BURST_ERR_STATUSH_STREAM0:0:15 */ 3460 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(324, 15, 0) 3461 }; 3462 static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_BURST_ERR_STSH1r_fields[] = 3463 { 3464 /* BURST_ERR_STATUSH_STREAM1:0:15 */ 3465 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(325, 15, 0) 3466 }; 3467 static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_BURST_ERR_STSH2r_fields[] = 3468 { 3469 /* BURST_ERR_STATUSH_STREAM2:0:15 */ 3470 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(326, 15, 0) 3471 }; 3472 static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_BURST_ERR_STSH3r_fields[] = 3473 { 3474 /* BURST_ERR_STATUSH_STREAM3:0:15 */ 3475 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(327, 15, 0) 3476 }; 3477 static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_BURST_ERR_STSH4r_fields[] = 3478 { 3479 /* BURST_ERR_STATUSH_STREAM4:0:15 */ 3480 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(328, 15, 0) 3481 }; 3482 static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_BURST_ERR_STSL0r_fields[] = 3483 { 3484 /* BURST_ERR_STATUSL_STREAM0:0:15 */ 3485 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(329, 15, 0) 3486 }; 3487 static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_BURST_ERR_STSL1r_fields[] = 3488 { 3489 /* BURST_ERR_STATUSL_STREAM1:0:15 */ 3490 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(330, 15, 0) 3491 }; 3492 static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_BURST_ERR_STSL2r_fields[] = 3493 { 3494 /* BURST_ERR_STATUSL_STREAM2:0:15 */ 3495 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(331, 15, 0) 3496 }; 3497 static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_BURST_ERR_STSL3r_fields[] = 3498 { 3499 /* BURST_ERR_STATUSL_STREAM3:0:15 */ 3500 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(332, 15, 0) 3501 }; 3502 static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_BURST_ERR_STSL4r_fields[] = 3503 { 3504 /* BURST_ERR_STATUSL_STREAM4:0:15 */ 3505 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(333, 15, 0) 3506 }; 3507 static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_CORRBLKSH0r_fields[] = 3508 { 3509 /* CORCOUNTH_STREAM0:0:15 */ 3510 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(513, 15, 0) 3511 }; 3512 static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_CORRBLKSH1r_fields[] = 3513 { 3514 /* CORCOUNTH_STREAM1:0:15 */ 3515 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(514, 15, 0) 3516 }; 3517 static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_CORRBLKSH2r_fields[] = 3518 { 3519 /* CORCOUNTH_STREAM2:0:15 */ 3520 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(515, 15, 0) 3521 }; 3522 static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_CORRBLKSH3r_fields[] = 3523 { 3524 /* CORCOUNTH_STREAM3:0:15 */ 3525 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(516, 15, 0) 3526 }; 3527 static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_CORRBLKSH4r_fields[] = 3528 { 3529 /* CORCOUNTH_STREAM4:0:15 */ 3530 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(517, 15, 0) 3531 }; 3532 static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_CORRBLKSL0r_fields[] = 3533 { 3534 /* CORCOUNTL_STREAM0:0:15 */ 3535 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(518, 15, 0) 3536 }; 3537 static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_CORRBLKSL1r_fields[] = 3538 { 3539 /* CORCOUNTL_STREAM1:0:15 */ 3540 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(519, 15, 0) 3541 }; 3542 static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_CORRBLKSL2r_fields[] = 3543 { 3544 /* CORCOUNTL_STREAM2:0:15 */ 3545 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(520, 15, 0) 3546 }; 3547 static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_CORRBLKSL3r_fields[] = 3548 { 3549 /* CORCOUNTL_STREAM3:0:15 */ 3550 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(521, 15, 0) 3551 }; 3552 static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_CORRBLKSL4r_fields[] = 3553 { 3554 /* CORCOUNTL_STREAM4:0:15 */ 3555 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(522, 15, 0) 3556 }; 3557 static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_DBG_ERRAH0r_fields[] = 3558 { 3559 /* DBG_ERRH_STREAM0:0:15 */ 3560 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(549, 15, 0) 3561 }; 3562 static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_DBG_ERRAH1r_fields[] = 3563 { 3564 /* DBG_ERRH_STREAM1:0:15 */ 3565 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(550, 15, 0) 3566 }; 3567 static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_DBG_ERRAH2r_fields[] = 3568 { 3569 /* DBG_ERRH_STREAM2:0:15 */ 3570 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(551, 15, 0) 3571 }; 3572 static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_DBG_ERRAH3r_fields[] = 3573 { 3574 /* DBG_ERRH_STREAM3:0:15 */ 3575 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(552, 15, 0) 3576 }; 3577 static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_DBG_ERRAH4r_fields[] = 3578 { 3579 /* DBG_ERRH_STREAM4:0:15 */ 3580 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(553, 15, 0) 3581 }; 3582 static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_DBG_ERRL0r_fields[] = 3583 { 3584 /* DBG_ERRL_STREAM0:0:15 */ 3585 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(554, 15, 0) 3586 }; 3587 static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_DBG_ERRL1r_fields[] = 3588 { 3589 /* DBG_ERRL_STREAM1:0:15 */ 3590 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(555, 15, 0) 3591 }; 3592 static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_DBG_ERRL2r_fields[] = 3593 { 3594 /* DBG_ERRL_STREAM2:0:15 */ 3595 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(556, 15, 0) 3596 }; 3597 static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_DBG_ERRL3r_fields[] = 3598 { 3599 /* DBG_ERRL_STREAM3:0:15 */ 3600 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(557, 15, 0) 3601 }; 3602 static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_DBG_ERRL4r_fields[] = 3603 { 3604 /* DBG_ERRL_STREAM4:0:15 */ 3605 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(558, 15, 0) 3606 }; 3607 static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_MEM_CTLr_fields[] = 3608 { 3609 /* FEC_MEM_TM:0:11 */ 3610 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(711, 11, 0) 3611 }; 3612 static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_SYNC_FSM_STr_fields[] = 3613 { 3614 /* CL91_FEC_SYNC_FSM_LIVE_STATE:0:1 */ 3615 PHYMOD_SYMBOL_FIELD_ENCODE(454, 1, 0), 3616 /* CL91_FEC_SYNC_FSM_LATCHED_STATE:2:5 */ 3617 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(453, 5, 2) 3618 }; 3619 static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_UNCORRBLKSH0r_fields[] = 3620 { 3621 /* UNCORCOUNTH_STREAM0:0:15 */ 3622 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1516, 15, 0) 3623 }; 3624 static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_UNCORRBLKSH1r_fields[] = 3625 { 3626 /* UNCORCOUNTH_STREAM1:0:15 */ 3627 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1517, 15, 0) 3628 }; 3629 static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_UNCORRBLKSH2r_fields[] = 3630 { 3631 /* UNCORCOUNTH_STREAM2:0:15 */ 3632 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1518, 15, 0) 3633 }; 3634 static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_UNCORRBLKSH3r_fields[] = 3635 { 3636 /* UNCORCOUNTH_STREAM3:0:15 */ 3637 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1519, 15, 0) 3638 }; 3639 static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_UNCORRBLKSH4r_fields[] = 3640 { 3641 /* UNCORCOUNTH_STREAM4:0:15 */ 3642 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1520, 15, 0) 3643 }; 3644 static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_UNCORRBLKSL0r_fields[] = 3645 { 3646 /* UNCORCOUNTL_STREAM0:0:15 */ 3647 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1521, 15, 0) 3648 }; 3649 static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_UNCORRBLKSL1r_fields[] = 3650 { 3651 /* UNCORCOUNTL_STREAM1:0:15 */ 3652 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1522, 15, 0) 3653 }; 3654 static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_UNCORRBLKSL2r_fields[] = 3655 { 3656 /* UNCORCOUNTL_STREAM2:0:15 */ 3657 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1523, 15, 0) 3658 }; 3659 static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_UNCORRBLKSL3r_fields[] = 3660 { 3661 /* UNCORCOUNTL_STREAM3:0:15 */ 3662 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1524, 15, 0) 3663 }; 3664 static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_UNCORRBLKSL4r_fields[] = 3665 { 3666 /* UNCORCOUNTL_STREAM4:0:15 */ 3667 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1525, 15, 0) 3668 }; 3669 static uint32_t BCMI_TSCF_XGXS_RX_X4_LNK_CTLr_fields[] = 3670 { 3671 /* LATCH_LINKDOWN_ENABLE:0:0 */ 3672 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(772, 0, 0) 3673 }; 3674 static uint32_t BCMI_TSCF_XGXS_RX_X4_PCS_CTL0r_fields[] = 3675 { 3676 /* LPI_ENABLE:0:0 */ 3677 PHYMOD_SYMBOL_FIELD_ENCODE(816, 0, 0), 3678 /* FEC_ENABLE:1:1 */ 3679 PHYMOD_SYMBOL_FIELD_ENCODE(692, 1, 1), 3680 /* DEC_FSM_MODE:6:7 */ 3681 PHYMOD_SYMBOL_FIELD_ENCODE(578, 7, 6), 3682 /* DESKEW_MODE:8:10 */ 3683 PHYMOD_SYMBOL_FIELD_ENCODE(605, 10, 8), 3684 /* DEC_TL_MODE:12:13 */ 3685 PHYMOD_SYMBOL_FIELD_ENCODE(583, 13, 12), 3686 /* DESCR_MODE:14:15 */ 3687 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(585, 15, 14) 3688 }; 3689 static uint32_t BCMI_TSCF_XGXS_RX_X4_PCS_LATCH_STS1r_fields[] = 3690 { 3691 /* DESKEW_STATUS_LL:0:0 */ 3692 PHYMOD_SYMBOL_FIELD_ENCODE(610, 0, 0), 3693 /* DESKEW_STATUS_LH:1:1 */ 3694 PHYMOD_SYMBOL_FIELD_ENCODE(609, 1, 1), 3695 /* LINK_STATUS_LL:2:2 */ 3696 PHYMOD_SYMBOL_FIELD_ENCODE(784, 2, 2), 3697 /* LINK_STATUS_LH:3:3 */ 3698 PHYMOD_SYMBOL_FIELD_ENCODE(783, 3, 3), 3699 /* HI_BER_LL:4:4 */ 3700 PHYMOD_SYMBOL_FIELD_ENCODE(734, 4, 4), 3701 /* HI_BER_LH:5:5 */ 3702 PHYMOD_SYMBOL_FIELD_ENCODE(733, 5, 5), 3703 /* LPI_RECEIVED_LH:6:6 */ 3704 PHYMOD_SYMBOL_FIELD_ENCODE(818, 6, 6), 3705 /* LINK_INTERRUPT_LH:7:7 */ 3706 PHYMOD_SYMBOL_FIELD_ENCODE(781, 7, 7), 3707 /* REMOTE_FAULT_LH:8:8 */ 3708 PHYMOD_SYMBOL_FIELD_ENCODE(1066, 8, 8), 3709 /* LOCAL_FAULT_LH:9:9 */ 3710 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(802, 9, 9) 3711 }; 3712 static uint32_t BCMI_TSCF_XGXS_RX_X4_PCS_LIVE_STS0r_fields[] = 3713 { 3714 /* AM_LOCK_0:0:0 */ 3715 PHYMOD_SYMBOL_FIELD_ENCODE(185, 0, 0), 3716 /* AM_LOCK_1:1:1 */ 3717 PHYMOD_SYMBOL_FIELD_ENCODE(186, 1, 1), 3718 /* AM_LOCK_2:2:2 */ 3719 PHYMOD_SYMBOL_FIELD_ENCODE(187, 2, 2), 3720 /* AM_LOCK_3:3:3 */ 3721 PHYMOD_SYMBOL_FIELD_ENCODE(188, 3, 3), 3722 /* AM_LOCK_4:4:4 */ 3723 PHYMOD_SYMBOL_FIELD_ENCODE(189, 4, 4), 3724 /* BLOCK_LOCK_0:5:5 */ 3725 PHYMOD_SYMBOL_FIELD_ENCODE(297, 5, 5), 3726 /* BLOCK_LOCK_1:6:6 */ 3727 PHYMOD_SYMBOL_FIELD_ENCODE(298, 6, 6), 3728 /* BLOCK_LOCK_2:7:7 */ 3729 PHYMOD_SYMBOL_FIELD_ENCODE(299, 7, 7), 3730 /* BLOCK_LOCK_3:8:8 */ 3731 PHYMOD_SYMBOL_FIELD_ENCODE(300, 8, 8), 3732 /* BLOCK_LOCK_4:9:9 */ 3733 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(301, 9, 9) 3734 }; 3735 static uint32_t BCMI_TSCF_XGXS_RX_X4_PCS_LIVE_STS1r_fields[] = 3736 { 3737 /* DESKEW_STATUS:0:0 */ 3738 PHYMOD_SYMBOL_FIELD_ENCODE(608, 0, 0), 3739 /* LINK_STATUS:1:1 */ 3740 PHYMOD_SYMBOL_FIELD_ENCODE(782, 1, 1), 3741 /* HI_BER:2:2 */ 3742 PHYMOD_SYMBOL_FIELD_ENCODE(732, 2, 2), 3743 /* LPI_RECEIVED:3:3 */ 3744 PHYMOD_SYMBOL_FIELD_ENCODE(817, 3, 3), 3745 /* LINK_INTERRUPT:4:4 */ 3746 PHYMOD_SYMBOL_FIELD_ENCODE(780, 4, 4), 3747 /* REMOTE_FAULT:5:5 */ 3748 PHYMOD_SYMBOL_FIELD_ENCODE(1065, 5, 5), 3749 /* LOCAL_FAULT:6:6 */ 3750 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(801, 6, 6) 3751 }; 3752 static uint32_t BCMI_TSCF_XGXS_RX_X4_PMA_CTL0r_fields[] = 3753 { 3754 /* RSTB_LANE:0:0 */ 3755 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1102, 0, 0) 3756 }; 3757 static uint32_t BCMI_TSCF_XGXS_RX_X4_PRTPERRCTRr_fields[] = 3758 { 3759 /* PRTP_ERR_COUNT:0:15 */ 3760 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1049, 15, 0) 3761 }; 3762 static uint32_t BCMI_TSCF_XGXS_RX_X4_PRTPSTSr_fields[] = 3763 { 3764 /* PRTP_LOCK:0:0 */ 3765 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1050, 0, 0) 3766 }; 3767 static uint32_t BCMI_TSCF_XGXS_RX_X4_PSLL_TO_VL_MAP0r_fields[] = 3768 { 3769 /* PSLL0_TO_VL_MAPPING:0:4 */ 3770 PHYMOD_SYMBOL_FIELD_ENCODE(1051, 4, 0), 3771 /* PSLL1_TO_VL_MAPPING:5:9 */ 3772 PHYMOD_SYMBOL_FIELD_ENCODE(1052, 9, 5), 3773 /* PSLL2_TO_VL_MAPPING:10:14 */ 3774 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1053, 14, 10) 3775 }; 3776 static uint32_t BCMI_TSCF_XGXS_RX_X4_PSLL_TO_VL_MAP1r_fields[] = 3777 { 3778 /* PSLL3_TO_VL_MAPPING:0:4 */ 3779 PHYMOD_SYMBOL_FIELD_ENCODE(1054, 4, 0), 3780 /* PSLL4_TO_VL_MAPPING:5:9 */ 3781 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1055, 9, 5) 3782 }; 3783 static uint32_t BCMI_TSCF_XGXS_RX_X4_SYNCE_FRACTIONAL_DIVr_fields[] = 3784 { 3785 /* SYNCE_FRACTIONAL_DIVSOR_CFG:0:15 */ 3786 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1328, 15, 0) 3787 }; 3788 static uint32_t BCMI_TSCF_XGXS_SC_X1_PIPE_RST_CNTr_fields[] = 3789 { 3790 /* PIPELINE_RESET_COUNT:0:15 */ 3791 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(976, 15, 0) 3792 }; 3793 static uint32_t BCMI_TSCF_XGXS_SC_X1_PLL_LOCK_TMRr_fields[] = 3794 { 3795 /* PLL_LOCK_TIMER_PERIOD:0:15 */ 3796 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(993, 15, 0) 3797 }; 3798 static uint32_t BCMI_TSCF_XGXS_SC_X1_PMD_LOCK_TMRr_fields[] = 3799 { 3800 /* PMD_LOCK_TIMER_PERIOD:0:15 */ 3801 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1010, 15, 0) 3802 }; 3803 static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR0_0r_fields[] = 3804 { 3805 /* SCR_MODE:1:3 */ 3806 PHYMOD_SYMBOL_FIELD_ENCODE(1276, 3, 1), 3807 /* T_PMA_BTMX_MODE:4:5 */ 3808 PHYMOD_SYMBOL_FIELD_ENCODE(1496, 5, 4), 3809 /* T_HG2_ENABLE:6:6 */ 3810 PHYMOD_SYMBOL_FIELD_ENCODE(1492, 6, 6), 3811 /* T_ENC_MODE:7:8 */ 3812 PHYMOD_SYMBOL_FIELD_ENCODE(1487, 8, 7), 3813 /* T_FIFO_MODE:9:10 */ 3814 PHYMOD_SYMBOL_FIELD_ENCODE(1490, 10, 9), 3815 /* OS_MODE:11:14 */ 3816 PHYMOD_SYMBOL_FIELD_ENCODE(940, 14, 11), 3817 /* CL72_EN:15:15 */ 3818 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(409, 15, 15) 3819 }; 3820 static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR0_1r_fields[] = 3821 { 3822 /* BS_BTMX_MODE:0:1 */ 3823 PHYMOD_SYMBOL_FIELD_ENCODE(314, 1, 0), 3824 /* BS_DIST_MODE:2:3 */ 3825 PHYMOD_SYMBOL_FIELD_ENCODE(316, 3, 2), 3826 /* BS_SYNC_EN:4:4 */ 3827 PHYMOD_SYMBOL_FIELD_ENCODE(322, 4, 4), 3828 /* BS_SM_SYNC_MODE:5:5 */ 3829 PHYMOD_SYMBOL_FIELD_ENCODE(319, 5, 5), 3830 /* R_HG2_ENABLE:6:6 */ 3831 PHYMOD_SYMBOL_FIELD_ENCODE(1272, 6, 6), 3832 /* DEC_FSM_MODE:7:8 */ 3833 PHYMOD_SYMBOL_FIELD_ENCODE(578, 8, 7), 3834 /* DESKEW_MODE:9:11 */ 3835 PHYMOD_SYMBOL_FIELD_ENCODE(605, 11, 9), 3836 /* DEC_TL_MODE:12:13 */ 3837 PHYMOD_SYMBOL_FIELD_ENCODE(583, 13, 12), 3838 /* DESCR_MODE:14:15 */ 3839 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(585, 15, 14) 3840 }; 3841 static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR0_2r_fields[] = 3842 { 3843 /* CLOCKCNT0:0:13 */ 3844 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(504, 13, 0) 3845 }; 3846 static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR0_3r_fields[] = 3847 { 3848 /* CLOCKCNT1:0:7 */ 3849 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(506, 7, 0) 3850 }; 3851 static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR0_4r_fields[] = 3852 { 3853 /* LOOPCNT1:0:5 */ 3854 PHYMOD_SYMBOL_FIELD_ENCODE(810, 5, 0), 3855 /* LOOPCNT0:6:13 */ 3856 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(808, 13, 6) 3857 }; 3858 static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR0_5r_fields[] = 3859 { 3860 /* MAC_CREDITGENCNT:0:12 */ 3861 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(831, 12, 0) 3862 }; 3863 static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR0_SPDr_fields[] = 3864 { 3865 /* NUM_LANES:0:2 */ 3866 PHYMOD_SYMBOL_FIELD_ENCODE(923, 2, 0), 3867 /* T_PMA_40B_MODE:3:3 */ 3868 PHYMOD_SYMBOL_FIELD_ENCODE(1494, 3, 3), 3869 /* CL36TX_EN:4:4 */ 3870 PHYMOD_SYMBOL_FIELD_ENCODE(389, 4, 4), 3871 /* CL36RX_EN:5:5 */ 3872 PHYMOD_SYMBOL_FIELD_ENCODE(382, 5, 5), 3873 /* SPEED:8:15 */ 3874 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1315, 15, 8) 3875 }; 3876 static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR1_0r_fields[] = 3877 { 3878 /* SCR_MODE:1:3 */ 3879 PHYMOD_SYMBOL_FIELD_ENCODE(1276, 3, 1), 3880 /* T_PMA_BTMX_MODE:4:5 */ 3881 PHYMOD_SYMBOL_FIELD_ENCODE(1496, 5, 4), 3882 /* T_HG2_ENABLE:6:6 */ 3883 PHYMOD_SYMBOL_FIELD_ENCODE(1492, 6, 6), 3884 /* T_ENC_MODE:7:8 */ 3885 PHYMOD_SYMBOL_FIELD_ENCODE(1487, 8, 7), 3886 /* T_FIFO_MODE:9:10 */ 3887 PHYMOD_SYMBOL_FIELD_ENCODE(1490, 10, 9), 3888 /* OS_MODE:11:14 */ 3889 PHYMOD_SYMBOL_FIELD_ENCODE(940, 14, 11), 3890 /* CL72_EN:15:15 */ 3891 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(409, 15, 15) 3892 }; 3893 static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR1_1r_fields[] = 3894 { 3895 /* BS_BTMX_MODE:0:1 */ 3896 PHYMOD_SYMBOL_FIELD_ENCODE(314, 1, 0), 3897 /* BS_DIST_MODE:2:3 */ 3898 PHYMOD_SYMBOL_FIELD_ENCODE(316, 3, 2), 3899 /* BS_SYNC_EN:4:4 */ 3900 PHYMOD_SYMBOL_FIELD_ENCODE(322, 4, 4), 3901 /* BS_SM_SYNC_MODE:5:5 */ 3902 PHYMOD_SYMBOL_FIELD_ENCODE(319, 5, 5), 3903 /* R_HG2_ENABLE:6:6 */ 3904 PHYMOD_SYMBOL_FIELD_ENCODE(1272, 6, 6), 3905 /* DEC_FSM_MODE:7:8 */ 3906 PHYMOD_SYMBOL_FIELD_ENCODE(578, 8, 7), 3907 /* DESKEW_MODE:9:11 */ 3908 PHYMOD_SYMBOL_FIELD_ENCODE(605, 11, 9), 3909 /* DEC_TL_MODE:12:13 */ 3910 PHYMOD_SYMBOL_FIELD_ENCODE(583, 13, 12), 3911 /* DESCR_MODE:14:15 */ 3912 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(585, 15, 14) 3913 }; 3914 static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR1_2r_fields[] = 3915 { 3916 /* CLOCKCNT0:0:13 */ 3917 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(504, 13, 0) 3918 }; 3919 static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR1_3r_fields[] = 3920 { 3921 /* CLOCKCNT1:0:7 */ 3922 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(506, 7, 0) 3923 }; 3924 static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR1_4r_fields[] = 3925 { 3926 /* LOOPCNT1:0:5 */ 3927 PHYMOD_SYMBOL_FIELD_ENCODE(810, 5, 0), 3928 /* LOOPCNT0:6:13 */ 3929 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(808, 13, 6) 3930 }; 3931 static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR1_5r_fields[] = 3932 { 3933 /* MAC_CREDITGENCNT:0:12 */ 3934 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(831, 12, 0) 3935 }; 3936 static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR1_SPDr_fields[] = 3937 { 3938 /* NUM_LANES:0:2 */ 3939 PHYMOD_SYMBOL_FIELD_ENCODE(923, 2, 0), 3940 /* T_PMA_40B_MODE:3:3 */ 3941 PHYMOD_SYMBOL_FIELD_ENCODE(1494, 3, 3), 3942 /* CL36TX_EN:4:4 */ 3943 PHYMOD_SYMBOL_FIELD_ENCODE(389, 4, 4), 3944 /* CL36RX_EN:5:5 */ 3945 PHYMOD_SYMBOL_FIELD_ENCODE(382, 5, 5), 3946 /* SPEED:8:15 */ 3947 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1315, 15, 8) 3948 }; 3949 static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR2_0r_fields[] = 3950 { 3951 /* SCR_MODE:1:3 */ 3952 PHYMOD_SYMBOL_FIELD_ENCODE(1276, 3, 1), 3953 /* T_PMA_BTMX_MODE:4:5 */ 3954 PHYMOD_SYMBOL_FIELD_ENCODE(1496, 5, 4), 3955 /* T_HG2_ENABLE:6:6 */ 3956 PHYMOD_SYMBOL_FIELD_ENCODE(1492, 6, 6), 3957 /* T_ENC_MODE:7:8 */ 3958 PHYMOD_SYMBOL_FIELD_ENCODE(1487, 8, 7), 3959 /* T_FIFO_MODE:9:10 */ 3960 PHYMOD_SYMBOL_FIELD_ENCODE(1490, 10, 9), 3961 /* OS_MODE:11:14 */ 3962 PHYMOD_SYMBOL_FIELD_ENCODE(940, 14, 11), 3963 /* CL72_EN:15:15 */ 3964 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(409, 15, 15) 3965 }; 3966 static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR2_1r_fields[] = 3967 { 3968 /* BS_BTMX_MODE:0:1 */ 3969 PHYMOD_SYMBOL_FIELD_ENCODE(314, 1, 0), 3970 /* BS_DIST_MODE:2:3 */ 3971 PHYMOD_SYMBOL_FIELD_ENCODE(316, 3, 2), 3972 /* BS_SYNC_EN:4:4 */ 3973 PHYMOD_SYMBOL_FIELD_ENCODE(322, 4, 4), 3974 /* BS_SM_SYNC_MODE:5:5 */ 3975 PHYMOD_SYMBOL_FIELD_ENCODE(319, 5, 5), 3976 /* R_HG2_ENABLE:6:6 */ 3977 PHYMOD_SYMBOL_FIELD_ENCODE(1272, 6, 6), 3978 /* DEC_FSM_MODE:7:8 */ 3979 PHYMOD_SYMBOL_FIELD_ENCODE(578, 8, 7), 3980 /* DESKEW_MODE:9:11 */ 3981 PHYMOD_SYMBOL_FIELD_ENCODE(605, 11, 9), 3982 /* DEC_TL_MODE:12:13 */ 3983 PHYMOD_SYMBOL_FIELD_ENCODE(583, 13, 12), 3984 /* DESCR_MODE:14:15 */ 3985 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(585, 15, 14) 3986 }; 3987 static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR2_2r_fields[] = 3988 { 3989 /* CLOCKCNT0:0:13 */ 3990 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(504, 13, 0) 3991 }; 3992 static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR2_3r_fields[] = 3993 { 3994 /* CLOCKCNT1:0:7 */ 3995 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(506, 7, 0) 3996 }; 3997 static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR2_4r_fields[] = 3998 { 3999 /* LOOPCNT1:0:5 */ 4000 PHYMOD_SYMBOL_FIELD_ENCODE(810, 5, 0), 4001 /* LOOPCNT0:6:13 */ 4002 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(808, 13, 6) 4003 }; 4004 static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR2_5r_fields[] = 4005 { 4006 /* MAC_CREDITGENCNT:0:12 */ 4007 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(831, 12, 0) 4008 }; 4009 static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR2_SPDr_fields[] = 4010 { 4011 /* NUM_LANES:0:2 */ 4012 PHYMOD_SYMBOL_FIELD_ENCODE(923, 2, 0), 4013 /* T_PMA_40B_MODE:3:3 */ 4014 PHYMOD_SYMBOL_FIELD_ENCODE(1494, 3, 3), 4015 /* CL36TX_EN:4:4 */ 4016 PHYMOD_SYMBOL_FIELD_ENCODE(389, 4, 4), 4017 /* CL36RX_EN:5:5 */ 4018 PHYMOD_SYMBOL_FIELD_ENCODE(382, 5, 5), 4019 /* SPEED:8:15 */ 4020 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1315, 15, 8) 4021 }; 4022 static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR3_0r_fields[] = 4023 { 4024 /* SCR_MODE:1:3 */ 4025 PHYMOD_SYMBOL_FIELD_ENCODE(1276, 3, 1), 4026 /* T_PMA_BTMX_MODE:4:5 */ 4027 PHYMOD_SYMBOL_FIELD_ENCODE(1496, 5, 4), 4028 /* T_HG2_ENABLE:6:6 */ 4029 PHYMOD_SYMBOL_FIELD_ENCODE(1492, 6, 6), 4030 /* T_ENC_MODE:7:8 */ 4031 PHYMOD_SYMBOL_FIELD_ENCODE(1487, 8, 7), 4032 /* T_FIFO_MODE:9:10 */ 4033 PHYMOD_SYMBOL_FIELD_ENCODE(1490, 10, 9), 4034 /* OS_MODE:11:14 */ 4035 PHYMOD_SYMBOL_FIELD_ENCODE(940, 14, 11), 4036 /* CL72_EN:15:15 */ 4037 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(409, 15, 15) 4038 }; 4039 static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR3_1r_fields[] = 4040 { 4041 /* BS_BTMX_MODE:0:1 */ 4042 PHYMOD_SYMBOL_FIELD_ENCODE(314, 1, 0), 4043 /* BS_DIST_MODE:2:3 */ 4044 PHYMOD_SYMBOL_FIELD_ENCODE(316, 3, 2), 4045 /* BS_SYNC_EN:4:4 */ 4046 PHYMOD_SYMBOL_FIELD_ENCODE(322, 4, 4), 4047 /* BS_SM_SYNC_MODE:5:5 */ 4048 PHYMOD_SYMBOL_FIELD_ENCODE(319, 5, 5), 4049 /* R_HG2_ENABLE:6:6 */ 4050 PHYMOD_SYMBOL_FIELD_ENCODE(1272, 6, 6), 4051 /* DEC_FSM_MODE:7:8 */ 4052 PHYMOD_SYMBOL_FIELD_ENCODE(578, 8, 7), 4053 /* DESKEW_MODE:9:11 */ 4054 PHYMOD_SYMBOL_FIELD_ENCODE(605, 11, 9), 4055 /* DEC_TL_MODE:12:13 */ 4056 PHYMOD_SYMBOL_FIELD_ENCODE(583, 13, 12), 4057 /* DESCR_MODE:14:15 */ 4058 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(585, 15, 14) 4059 }; 4060 static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR3_2r_fields[] = 4061 { 4062 /* CLOCKCNT0:0:13 */ 4063 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(504, 13, 0) 4064 }; 4065 static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR3_3r_fields[] = 4066 { 4067 /* CLOCKCNT1:0:7 */ 4068 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(506, 7, 0) 4069 }; 4070 static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR3_4r_fields[] = 4071 { 4072 /* LOOPCNT1:0:5 */ 4073 PHYMOD_SYMBOL_FIELD_ENCODE(810, 5, 0), 4074 /* LOOPCNT0:6:13 */ 4075 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(808, 13, 6) 4076 }; 4077 static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR3_5r_fields[] = 4078 { 4079 /* MAC_CREDITGENCNT:0:12 */ 4080 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(831, 12, 0) 4081 }; 4082 static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR3_SPDr_fields[] = 4083 { 4084 /* NUM_LANES:0:2 */ 4085 PHYMOD_SYMBOL_FIELD_ENCODE(923, 2, 0), 4086 /* T_PMA_40B_MODE:3:3 */ 4087 PHYMOD_SYMBOL_FIELD_ENCODE(1494, 3, 3), 4088 /* CL36TX_EN:4:4 */ 4089 PHYMOD_SYMBOL_FIELD_ENCODE(389, 4, 4), 4090 /* CL36RX_EN:5:5 */ 4091 PHYMOD_SYMBOL_FIELD_ENCODE(382, 5, 5), 4092 /* SPEED:8:15 */ 4093 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1315, 15, 8) 4094 }; 4095 static uint32_t BCMI_TSCF_XGXS_SC_X1_STSr_fields[] = 4096 { 4097 /* RESOLVED_PORT_MODE:0:2 */ 4098 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1073, 2, 0) 4099 }; 4100 static uint32_t BCMI_TSCF_XGXS_SC_X1_TX_RST_CNTr_fields[] = 4101 { 4102 /* TX_RESET_COUNT:0:15 */ 4103 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1481, 15, 0) 4104 }; 4105 static uint32_t BCMI_TSCF_XGXS_SC_X4_BYPASSr_fields[] = 4106 { 4107 /* SC_BYPASS:0:0 */ 4108 PHYMOD_SYMBOL_FIELD_ENCODE(1278, 0, 0), 4109 /* SC_IGNORE_TX_DATA_VLD:1:1 */ 4110 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1280, 1, 1) 4111 }; 4112 static uint32_t BCMI_TSCF_XGXS_SC_X4_CTLr_fields[] = 4113 { 4114 /* SPEED:0:7 */ 4115 PHYMOD_SYMBOL_FIELD_ENCODE(1315, 7, 0), 4116 /* SW_SPEED_CHANGE:8:8 */ 4117 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1323, 8, 8) 4118 }; 4119 static uint32_t BCMI_TSCF_XGXS_SC_X4_DBGr_fields[] = 4120 { 4121 /* SC_FSM_STATUS:0:15 */ 4122 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1279, 15, 0) 4123 }; 4124 static uint32_t BCMI_TSCF_XGXS_SC_X4_ERRr_fields[] = 4125 { 4126 /* PLL_LOCK_TIMED_OUT:0:0 */ 4127 PHYMOD_SYMBOL_FIELD_ENCODE(992, 0, 0), 4128 /* PMD_LOCK_TIMED_OUT:1:1 */ 4129 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1009, 1, 1) 4130 }; 4131 static uint32_t BCMI_TSCF_XGXS_SC_X4_FEC_STSr_fields[] = 4132 { 4133 /* R_FEC_ENABLE:0:0 */ 4134 PHYMOD_SYMBOL_FIELD_ENCODE(1271, 0, 0), 4135 /* T_FEC_ENABLE:1:1 */ 4136 PHYMOD_SYMBOL_FIELD_ENCODE(1489, 1, 1), 4137 /* R_CL91_FEC_ENABLE:2:2 */ 4138 PHYMOD_SYMBOL_FIELD_ENCODE(1270, 2, 2), 4139 /* T_CL91_FEC_ENABLE:3:3 */ 4140 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1486, 3, 3) 4141 }; 4142 static uint32_t BCMI_TSCF_XGXS_SC_X4_FLD_OVRR_EN0_TYPEr_fields[] = 4143 { 4144 /* CL36RX_EN_OEN:0:0 */ 4145 PHYMOD_SYMBOL_FIELD_ENCODE(383, 0, 0), 4146 /* CL36TX_EN_OEN:1:1 */ 4147 PHYMOD_SYMBOL_FIELD_ENCODE(390, 1, 1), 4148 /* T_PMA_40B_MODE_OEN:2:2 */ 4149 PHYMOD_SYMBOL_FIELD_ENCODE(1495, 2, 2), 4150 /* DEC_FSM_MODE_OEN:3:3 */ 4151 PHYMOD_SYMBOL_FIELD_ENCODE(579, 3, 3), 4152 /* DESKEW_MODE_OEN:4:4 */ 4153 PHYMOD_SYMBOL_FIELD_ENCODE(606, 4, 4), 4154 /* DEC_TL_MODE_OEN:5:5 */ 4155 PHYMOD_SYMBOL_FIELD_ENCODE(584, 5, 5), 4156 /* DESCR_MODE_OEN:6:6 */ 4157 PHYMOD_SYMBOL_FIELD_ENCODE(586, 6, 6), 4158 /* CL72_EN_OEN:7:7 */ 4159 PHYMOD_SYMBOL_FIELD_ENCODE(410, 7, 7), 4160 /* SCR_MODE_OEN:8:8 */ 4161 PHYMOD_SYMBOL_FIELD_ENCODE(1277, 8, 8), 4162 /* T_PMA_BTMX_MODE_OEN:9:9 */ 4163 PHYMOD_SYMBOL_FIELD_ENCODE(1497, 9, 9), 4164 /* T_HG2_ENABLE_OEN:10:10 */ 4165 PHYMOD_SYMBOL_FIELD_ENCODE(1493, 10, 10), 4166 /* T_ENC_MODE_OEN:11:11 */ 4167 PHYMOD_SYMBOL_FIELD_ENCODE(1488, 11, 11), 4168 /* T_FIFO_MODE_OEN:12:12 */ 4169 PHYMOD_SYMBOL_FIELD_ENCODE(1491, 12, 12), 4170 /* OS_MODE_OEN:13:13 */ 4171 PHYMOD_SYMBOL_FIELD_ENCODE(941, 13, 13), 4172 /* NUM_LANES_OEN:14:14 */ 4173 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(924, 14, 14) 4174 }; 4175 static uint32_t BCMI_TSCF_XGXS_SC_X4_FLD_OVRR_EN1_TYPEr_fields[] = 4176 { 4177 /* MAC_CREDITGENCNT_OEN:5:5 */ 4178 PHYMOD_SYMBOL_FIELD_ENCODE(832, 5, 5), 4179 /* LOOPCNT1_OEN:6:6 */ 4180 PHYMOD_SYMBOL_FIELD_ENCODE(811, 6, 6), 4181 /* LOOPCNT0_OEN:7:7 */ 4182 PHYMOD_SYMBOL_FIELD_ENCODE(809, 7, 7), 4183 /* CLOCKCNT1_OEN:8:8 */ 4184 PHYMOD_SYMBOL_FIELD_ENCODE(507, 8, 8), 4185 /* CLOCKCNT0_OEN:9:9 */ 4186 PHYMOD_SYMBOL_FIELD_ENCODE(505, 9, 9), 4187 /* CREDITENABLE_OEN:10:10 */ 4188 PHYMOD_SYMBOL_FIELD_ENCODE(542, 10, 10), 4189 /* BS_BTMX_MODE_OEN:11:11 */ 4190 PHYMOD_SYMBOL_FIELD_ENCODE(315, 11, 11), 4191 /* BS_DIST_MODE_OEN:12:12 */ 4192 PHYMOD_SYMBOL_FIELD_ENCODE(317, 12, 12), 4193 /* BS_SYNC_EN_OEN:13:13 */ 4194 PHYMOD_SYMBOL_FIELD_ENCODE(323, 13, 13), 4195 /* BS_SM_SYNC_MODE_OEN:14:14 */ 4196 PHYMOD_SYMBOL_FIELD_ENCODE(320, 14, 14), 4197 /* R_HG2_ENABLE_OEN:15:15 */ 4198 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1273, 15, 15) 4199 }; 4200 static uint32_t BCMI_TSCF_XGXS_SC_X4_LN_NUM_OVRRr_fields[] = 4201 { 4202 /* NUM_LANES_OVERRIDE_VALUE:0:2 */ 4203 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(925, 2, 0) 4204 }; 4205 static uint32_t BCMI_TSCF_XGXS_SC_X4_RSLVD0r_fields[] = 4206 { 4207 /* SCR_MODE:1:3 */ 4208 PHYMOD_SYMBOL_FIELD_ENCODE(1276, 3, 1), 4209 /* T_PMA_BTMX_MODE:4:5 */ 4210 PHYMOD_SYMBOL_FIELD_ENCODE(1496, 5, 4), 4211 /* T_HG2_ENABLE:6:6 */ 4212 PHYMOD_SYMBOL_FIELD_ENCODE(1492, 6, 6), 4213 /* T_ENC_MODE:7:8 */ 4214 PHYMOD_SYMBOL_FIELD_ENCODE(1487, 8, 7), 4215 /* T_FIFO_MODE:9:10 */ 4216 PHYMOD_SYMBOL_FIELD_ENCODE(1490, 10, 9), 4217 /* OS_MODE:11:14 */ 4218 PHYMOD_SYMBOL_FIELD_ENCODE(940, 14, 11), 4219 /* CL72_EN:15:15 */ 4220 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(409, 15, 15) 4221 }; 4222 static uint32_t BCMI_TSCF_XGXS_SC_X4_RSLVD1r_fields[] = 4223 { 4224 /* BS_BTMX_MODE:0:1 */ 4225 PHYMOD_SYMBOL_FIELD_ENCODE(314, 1, 0), 4226 /* BS_DIST_MODE:2:3 */ 4227 PHYMOD_SYMBOL_FIELD_ENCODE(316, 3, 2), 4228 /* BS_SYNC_EN:4:4 */ 4229 PHYMOD_SYMBOL_FIELD_ENCODE(322, 4, 4), 4230 /* BS_SM_SYNC_MODE:5:5 */ 4231 PHYMOD_SYMBOL_FIELD_ENCODE(319, 5, 5), 4232 /* R_HG2_ENABLE:6:6 */ 4233 PHYMOD_SYMBOL_FIELD_ENCODE(1272, 6, 6), 4234 /* DEC_FSM_MODE:7:8 */ 4235 PHYMOD_SYMBOL_FIELD_ENCODE(578, 8, 7), 4236 /* DESKEW_MODE:9:11 */ 4237 PHYMOD_SYMBOL_FIELD_ENCODE(605, 11, 9), 4238 /* DEC_TL_MODE:12:13 */ 4239 PHYMOD_SYMBOL_FIELD_ENCODE(583, 13, 12), 4240 /* DESCR_MODE:14:15 */ 4241 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(585, 15, 14) 4242 }; 4243 static uint32_t BCMI_TSCF_XGXS_SC_X4_RSLVD2r_fields[] = 4244 { 4245 /* CLOCKCNT0:0:13 */ 4246 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(504, 13, 0) 4247 }; 4248 static uint32_t BCMI_TSCF_XGXS_SC_X4_RSLVD3r_fields[] = 4249 { 4250 /* CLOCKCNT1:0:7 */ 4251 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(506, 7, 0) 4252 }; 4253 static uint32_t BCMI_TSCF_XGXS_SC_X4_RSLVD4r_fields[] = 4254 { 4255 /* LOOPCNT1:0:5 */ 4256 PHYMOD_SYMBOL_FIELD_ENCODE(810, 5, 0), 4257 /* LOOPCNT0:6:13 */ 4258 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(808, 13, 6) 4259 }; 4260 static uint32_t BCMI_TSCF_XGXS_SC_X4_RSLVD5r_fields[] = 4261 { 4262 /* MAC_CREDITGENCNT:0:12 */ 4263 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(831, 12, 0) 4264 }; 4265 static uint32_t BCMI_TSCF_XGXS_SC_X4_RSLVD_SPDr_fields[] = 4266 { 4267 /* NUM_LANES:0:2 */ 4268 PHYMOD_SYMBOL_FIELD_ENCODE(923, 2, 0), 4269 /* T_PMA_40B_MODE:3:3 */ 4270 PHYMOD_SYMBOL_FIELD_ENCODE(1494, 3, 3), 4271 /* CL36TX_EN:4:4 */ 4272 PHYMOD_SYMBOL_FIELD_ENCODE(389, 4, 4), 4273 /* CL36RX_EN:5:5 */ 4274 PHYMOD_SYMBOL_FIELD_ENCODE(382, 5, 5), 4275 /* SPEED:8:15 */ 4276 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1315, 15, 8) 4277 }; 4278 static uint32_t BCMI_TSCF_XGXS_SC_X4_SPARE0r_fields[] = 4279 { 4280 /* SPARE0:0:7 */ 4281 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1313, 7, 0) 4282 }; 4283 static uint32_t BCMI_TSCF_XGXS_SC_X4_SPARE1r_fields[] = 4284 { 4285 /* SPARE1:0:7 */ 4286 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1314, 7, 0) 4287 }; 4288 static uint32_t BCMI_TSCF_XGXS_SC_X4_STSr_fields[] = 4289 { 4290 /* SW_SPEED_CHANGE_DONE:0:0 */ 4291 PHYMOD_SYMBOL_FIELD_ENCODE(1324, 0, 0), 4292 /* SW_SPEED_CONFIG_VLD:1:1 */ 4293 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1325, 1, 1) 4294 }; 4295 static uint32_t BCMI_TSCF_XGXS_SIGDET_CTL0r_fields[] = 4296 { 4297 /* SIGNAL_DETECT_FILTER_COUNT:0:4 */ 4298 PHYMOD_SYMBOL_FIELD_ENCODE(1297, 4, 0), 4299 /* LOS_FILTER_COUNT:8:12 */ 4300 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(813, 12, 8) 4301 }; 4302 static uint32_t BCMI_TSCF_XGXS_SIGDET_CTL1r_fields[] = 4303 { 4304 /* AFE_SIGNAL_DETECT_DIS:0:0 */ 4305 PHYMOD_SYMBOL_FIELD_ENCODE(12, 0, 0), 4306 /* EXT_LOS_EN:1:1 */ 4307 PHYMOD_SYMBOL_FIELD_ENCODE(681, 1, 1), 4308 /* EXT_LOS_INV:2:2 */ 4309 PHYMOD_SYMBOL_FIELD_ENCODE(682, 2, 2), 4310 /* IGNORE_LP_MODE:3:3 */ 4311 PHYMOD_SYMBOL_FIELD_ENCODE(745, 3, 3), 4312 /* SIGNAL_DETECT_FILTER_1US:4:4 */ 4313 PHYMOD_SYMBOL_FIELD_ENCODE(1296, 4, 4), 4314 /* ENERGY_DETECT_FRC:5:5 */ 4315 PHYMOD_SYMBOL_FIELD_ENCODE(656, 5, 5), 4316 /* ENERGY_DETECT_FRC_VAL:6:6 */ 4317 PHYMOD_SYMBOL_FIELD_ENCODE(657, 6, 6), 4318 /* SIGNAL_DETECT_FRC:7:7 */ 4319 PHYMOD_SYMBOL_FIELD_ENCODE(1298, 7, 7), 4320 /* SIGNAL_DETECT_FRC_VAL:8:8 */ 4321 PHYMOD_SYMBOL_FIELD_ENCODE(1299, 8, 8), 4322 /* ENERGY_DETECT_MASK_COUNT:11:15 */ 4323 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(658, 15, 11) 4324 }; 4325 static uint32_t BCMI_TSCF_XGXS_SIGDET_CTL2r_fields[] = 4326 { 4327 /* LOS_THRESH:0:2 */ 4328 PHYMOD_SYMBOL_FIELD_ENCODE(814, 2, 0), 4329 /* SIGNAL_DETECT_THRESH:4:6 */ 4330 PHYMOD_SYMBOL_FIELD_ENCODE(1306, 6, 4), 4331 /* HOLD_LOS_COUNT:8:10 */ 4332 PHYMOD_SYMBOL_FIELD_ENCODE(738, 10, 8), 4333 /* HOLD_SD_COUNT:11:13 */ 4334 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(739, 13, 11) 4335 }; 4336 static uint32_t BCMI_TSCF_XGXS_SIGDET_STS0r_fields[] = 4337 { 4338 /* SIGNAL_DETECT:0:0 */ 4339 PHYMOD_SYMBOL_FIELD_ENCODE(1294, 0, 0), 4340 /* SIGNAL_DETECT_CHANGE:1:1 */ 4341 PHYMOD_SYMBOL_FIELD_ENCODE(1295, 1, 1), 4342 /* ENERGY_DETECT:2:2 */ 4343 PHYMOD_SYMBOL_FIELD_ENCODE(654, 2, 2), 4344 /* ENERGY_DETECT_CHANGE:3:3 */ 4345 PHYMOD_SYMBOL_FIELD_ENCODE(655, 3, 3), 4346 /* SIGNAL_DETECT_RAW:4:4 */ 4347 PHYMOD_SYMBOL_FIELD_ENCODE(1303, 4, 4), 4348 /* SIGNAL_DETECT_RAW_CHANGE:5:5 */ 4349 PHYMOD_SYMBOL_FIELD_ENCODE(1304, 5, 5), 4350 /* AFE_SIGDET_THRESH:8:10 */ 4351 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(11, 10, 8) 4352 }; 4353 static uint32_t BCMI_TSCF_XGXS_TEST1_RXPKTCNT_Lr_fields[] = 4354 { 4355 /* RXPKTCNT_L:0:15 */ 4356 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1214, 15, 0) 4357 }; 4358 static uint32_t BCMI_TSCF_XGXS_TEST1_RXPKTCNT_Ur_fields[] = 4359 { 4360 /* RXPKTCNT_U:0:15 */ 4361 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1215, 15, 0) 4362 }; 4363 static uint32_t BCMI_TSCF_XGXS_TEST1_TXPKTCNT_Lr_fields[] = 4364 { 4365 /* TXPKTCNT_L:0:15 */ 4366 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1424, 15, 0) 4367 }; 4368 static uint32_t BCMI_TSCF_XGXS_TEST1_TXPKTCNT_Ur_fields[] = 4369 { 4370 /* TXPKTCNT_U:0:15 */ 4371 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1425, 15, 0) 4372 }; 4373 static uint32_t BCMI_TSCF_XGXS_TLB_RX_DIG_LPBK_CFGr_fields[] = 4374 { 4375 /* DIG_LPBK_EN:0:0 */ 4376 PHYMOD_SYMBOL_FIELD_ENCODE(611, 0, 0), 4377 /* DIG_LPBK_PD_MODE:1:1 */ 4378 PHYMOD_SYMBOL_FIELD_ENCODE(615, 1, 1), 4379 /* DIG_LPBK_PD_BIAS_EN:3:3 */ 4380 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(612, 3, 3) 4381 }; 4382 static uint32_t BCMI_TSCF_XGXS_TLB_RX_DIG_LPBK_PD_STSr_fields[] = 4383 { 4384 /* DIG_LPBK_PD_LATE_IND:0:0 */ 4385 PHYMOD_SYMBOL_FIELD_ENCODE(614, 0, 0), 4386 /* DIG_LPBK_PD_EARLY_IND:1:1 */ 4387 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(613, 1, 1) 4388 }; 4389 static uint32_t BCMI_TSCF_XGXS_TLB_RX_MAX_PRBS_BURST_ERR_LEN_STSr_fields[] = 4390 { 4391 /* MAX_PRBS_BURST_ERR_LENGTH_STATUS:0:5 */ 4392 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(834, 5, 0) 4393 }; 4394 static uint32_t BCMI_TSCF_XGXS_TLB_RX_MISC_CFGr_fields[] = 4395 { 4396 /* RX_PMD_DP_INVERT:0:0 */ 4397 PHYMOD_SYMBOL_FIELD_ENCODE(1260, 0, 0), 4398 /* DBG_MASK_DIG_LPBK_EN:2:2 */ 4399 PHYMOD_SYMBOL_FIELD_ENCODE(561, 2, 2), 4400 /* TLB_RX_DIFF_DEC_EN:3:3 */ 4401 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1356, 3, 3) 4402 }; 4403 static uint32_t BCMI_TSCF_XGXS_TLB_RX_PMD_RX_LOCK_STSr_fields[] = 4404 { 4405 /* PMD_RX_LOCK:0:0 */ 4406 PHYMOD_SYMBOL_FIELD_ENCODE(1014, 0, 0), 4407 /* PMD_RX_LOCK_CHANGE:1:1 */ 4408 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1015, 1, 1) 4409 }; 4410 static uint32_t BCMI_TSCF_XGXS_TLB_RX_PRBS_BURST_ERR_LEN_STSr_fields[] = 4411 { 4412 /* PRBS_BURST_ERR_LENGTH_STATUS:0:5 */ 4413 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1021, 5, 0) 4414 }; 4415 static uint32_t BCMI_TSCF_XGXS_TLB_RX_PRBS_CHK_CFGr_fields[] = 4416 { 4417 /* PRBS_CHK_EN:0:0 */ 4418 PHYMOD_SYMBOL_FIELD_ENCODE(1024, 0, 0), 4419 /* PRBS_CHK_MODE_SEL:1:3 */ 4420 PHYMOD_SYMBOL_FIELD_ENCODE(1036, 3, 1), 4421 /* PRBS_CHK_INV:4:4 */ 4422 PHYMOD_SYMBOL_FIELD_ENCODE(1031, 4, 4), 4423 /* PRBS_CHK_MODE:5:6 */ 4424 PHYMOD_SYMBOL_FIELD_ENCODE(1035, 6, 5), 4425 /* PRBS_CHK_EN_AUTO_MODE:7:7 */ 4426 PHYMOD_SYMBOL_FIELD_ENCODE(1025, 7, 7), 4427 /* PRBS_BURST_LEN_CHK_EN:8:8 */ 4428 PHYMOD_SYMBOL_FIELD_ENCODE(1022, 8, 8), 4429 /* PRBS_CHK_ERR_CNT_BURST_MODE:9:9 */ 4430 PHYMOD_SYMBOL_FIELD_ENCODE(1028, 9, 9), 4431 /* TRNSUM_ERROR_COUNT_EN:10:10 */ 4432 PHYMOD_SYMBOL_FIELD_ENCODE(1373, 10, 10), 4433 /* PRBS_CHK_CLK_EN_FRC_ON:11:11 */ 4434 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1023, 11, 11) 4435 }; 4436 static uint32_t BCMI_TSCF_XGXS_TLB_RX_PRBS_CHK_CNT_CFGr_fields[] = 4437 { 4438 /* PRBS_CHK_LOCK_CNT:0:4 */ 4439 PHYMOD_SYMBOL_FIELD_ENCODE(1033, 4, 0), 4440 /* PRBS_CHK_OOL_CNT:8:12 */ 4441 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1037, 12, 8) 4442 }; 4443 static uint32_t BCMI_TSCF_XGXS_TLB_RX_PRBS_CHK_EN_TMR_CTLr_fields[] = 4444 { 4445 /* PRBS_CHK_EN_TIMER_MODE:0:1 */ 4446 PHYMOD_SYMBOL_FIELD_ENCODE(1027, 1, 0), 4447 /* PRBS_CHK_EN_TIMEOUT:8:12 */ 4448 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1026, 12, 8) 4449 }; 4450 static uint32_t BCMI_TSCF_XGXS_TLB_RX_PRBS_CHK_ERR_CNT_LSB_STSr_fields[] = 4451 { 4452 /* PRBS_CHK_ERR_CNT_LSB:0:15 */ 4453 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1029, 15, 0) 4454 }; 4455 static uint32_t BCMI_TSCF_XGXS_TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr_fields[] = 4456 { 4457 /* PRBS_CHK_ERR_CNT_MSB:0:14 */ 4458 PHYMOD_SYMBOL_FIELD_ENCODE(1030, 14, 0), 4459 /* PRBS_CHK_LOCK_LOST_LH:15:15 */ 4460 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1034, 15, 15) 4461 }; 4462 static uint32_t BCMI_TSCF_XGXS_TLB_RX_PRBS_CHK_LOCK_STSr_fields[] = 4463 { 4464 /* PRBS_CHK_LOCK:0:0 */ 4465 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1032, 0, 0) 4466 }; 4467 static uint32_t BCMI_TSCF_XGXS_TLB_TX_MISC_CFGr_fields[] = 4468 { 4469 /* TX_PMD_DP_INVERT:0:0 */ 4470 PHYMOD_SYMBOL_FIELD_ENCODE(1478, 0, 0), 4471 /* TX_PCS_NATIVE_ANA_FRMT_EN:1:1 */ 4472 PHYMOD_SYMBOL_FIELD_ENCODE(1447, 1, 1), 4473 /* TX_MUX_SEL_ORDER:2:2 */ 4474 PHYMOD_SYMBOL_FIELD_ENCODE(1445, 2, 2), 4475 /* TLB_TX_DIFF_ENC_EN:3:3 */ 4476 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1357, 3, 3) 4477 }; 4478 static uint32_t BCMI_TSCF_XGXS_TLB_TX_PATT_GEN_CFGr_fields[] = 4479 { 4480 /* PATT_GEN_EN:0:0 */ 4481 PHYMOD_SYMBOL_FIELD_ENCODE(947, 0, 0), 4482 /* PATT_GEN_STOP_POS:8:11 */ 4483 PHYMOD_SYMBOL_FIELD_ENCODE(964, 11, 8), 4484 /* PATT_GEN_START_POS:12:15 */ 4485 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(963, 15, 12) 4486 }; 4487 static uint32_t BCMI_TSCF_XGXS_TLB_TX_PRBS_GEN_CFGr_fields[] = 4488 { 4489 /* PRBS_GEN_EN:0:0 */ 4490 PHYMOD_SYMBOL_FIELD_ENCODE(1038, 0, 0), 4491 /* PRBS_GEN_MODE_SEL:1:3 */ 4492 PHYMOD_SYMBOL_FIELD_ENCODE(1041, 3, 1), 4493 /* PRBS_GEN_INV:4:4 */ 4494 PHYMOD_SYMBOL_FIELD_ENCODE(1040, 4, 4), 4495 /* PRBS_GEN_ERR_INS:5:5 */ 4496 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1039, 5, 5) 4497 }; 4498 static uint32_t BCMI_TSCF_XGXS_TLB_TX_RMT_LPBK_CFGr_fields[] = 4499 { 4500 /* RMT_LPBK_EN:0:0 */ 4501 PHYMOD_SYMBOL_FIELD_ENCODE(1097, 0, 0), 4502 /* RMT_LPBK_PD_MODE:1:1 */ 4503 PHYMOD_SYMBOL_FIELD_ENCODE(1101, 1, 1), 4504 /* RMT_LPBK_PD_FRC_ON:2:2 */ 4505 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1099, 2, 2) 4506 }; 4507 static uint32_t BCMI_TSCF_XGXS_TLB_TX_RMT_LPBK_PD_STSr_fields[] = 4508 { 4509 /* RMT_LPBK_PD_LATE_IND:0:0 */ 4510 PHYMOD_SYMBOL_FIELD_ENCODE(1100, 0, 0), 4511 /* RMT_LPBK_PD_EARLY_IND:1:1 */ 4512 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1098, 1, 1) 4513 }; 4514 static uint32_t BCMI_TSCF_XGXS_TXFIR_CTL0r_fields[] = 4515 { 4516 /* TXFIR_PRE_OFFSET:0:3 */ 4517 PHYMOD_SYMBOL_FIELD_ENCODE(1423, 3, 0), 4518 /* TXFIR_MAIN_OFFSET:4:7 */ 4519 PHYMOD_SYMBOL_FIELD_ENCODE(1411, 7, 4), 4520 /* TXFIR_POST_OFFSET:8:11 */ 4521 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1420, 11, 8) 4522 }; 4523 static uint32_t BCMI_TSCF_XGXS_TXFIR_CTL1r_fields[] = 4524 { 4525 /* TXFIR_POST2:0:4 */ 4526 PHYMOD_SYMBOL_FIELD_ENCODE(1412, 4, 0), 4527 /* TXFIR_POST2_OFFSET:8:11 */ 4528 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1414, 11, 8) 4529 }; 4530 static uint32_t BCMI_TSCF_XGXS_TXFIR_CTL2r_fields[] = 4531 { 4532 /* TXFIR_POST3:0:3 */ 4533 PHYMOD_SYMBOL_FIELD_ENCODE(1415, 3, 0), 4534 /* TXFIR_POST3_OFFSET:8:11 */ 4535 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1417, 11, 8) 4536 }; 4537 static uint32_t BCMI_TSCF_XGXS_TXFIR_MISC_CTL1r_fields[] = 4538 { 4539 /* SDK_TX_DISABLE:0:0 */ 4540 PHYMOD_SYMBOL_FIELD_ENCODE(1281, 0, 0), 4541 /* PMD_TX_DISABLE_PIN_DIS:1:1 */ 4542 PHYMOD_SYMBOL_FIELD_ENCODE(1018, 1, 1), 4543 /* TX_DISABLE_TIMER_CTRL:2:7 */ 4544 PHYMOD_SYMBOL_FIELD_ENCODE(1433, 7, 2), 4545 /* TX_EEE_QUIET_EN:8:8 */ 4546 PHYMOD_SYMBOL_FIELD_ENCODE(1435, 8, 8), 4547 /* TX_EEE_ALERT_EN:9:9 */ 4548 PHYMOD_SYMBOL_FIELD_ENCODE(1434, 9, 9), 4549 /* TX_DISABLE_OUTPUT_SEL:10:11 */ 4550 PHYMOD_SYMBOL_FIELD_ENCODE(1432, 11, 10), 4551 /* DP_RESET_TX_DISABLE_DIS:12:12 */ 4552 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(631, 12, 12) 4553 }; 4554 static uint32_t BCMI_TSCF_XGXS_TXFIR_STS0r_fields[] = 4555 { 4556 /* TXFIR_PRE_AFTER_OVR:0:4 */ 4557 PHYMOD_SYMBOL_FIELD_ENCODE(1422, 4, 0), 4558 /* TXFIR_POST_AFTER_OVR:8:13 */ 4559 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1419, 13, 8) 4560 }; 4561 static uint32_t BCMI_TSCF_XGXS_TXFIR_STS1r_fields[] = 4562 { 4563 /* TXFIR_MAIN_AFTER_OVR:0:6 */ 4564 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1410, 6, 0) 4565 }; 4566 static uint32_t BCMI_TSCF_XGXS_TXFIR_STS2r_fields[] = 4567 { 4568 /* TXFIR_PRE_ADJUSTED:0:4 */ 4569 PHYMOD_SYMBOL_FIELD_ENCODE(1421, 4, 0), 4570 /* TXFIR_POST_ADJUSTED:8:13 */ 4571 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1418, 13, 8) 4572 }; 4573 static uint32_t BCMI_TSCF_XGXS_TXFIR_STS3r_fields[] = 4574 { 4575 /* TXFIR_MAIN_ADJUSTED:0:6 */ 4576 PHYMOD_SYMBOL_FIELD_ENCODE(1409, 6, 0), 4577 /* TXFIR_POST2_ADJUSTED:8:12 */ 4578 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1413, 12, 8) 4579 }; 4580 static uint32_t BCMI_TSCF_XGXS_TXFIR_STS4r_fields[] = 4581 { 4582 /* TXFIR_POST3_ADJUSTED:0:3 */ 4583 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1416, 3, 0) 4584 }; 4585 static uint32_t BCMI_TSCF_XGXS_TXFIR_UC_CTL0r_fields[] = 4586 { 4587 /* MICRO_TX_DISABLE:0:0 */ 4588 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(915, 0, 0) 4589 }; 4590 static uint32_t BCMI_TSCF_XGXS_TX_CTL0r_fields[] = 4591 { 4592 /* TXCOM_POST_TAP_ALERT_VAL:0:5 */ 4593 PHYMOD_SYMBOL_FIELD_ENCODE(1403, 5, 0), 4594 /* TXCOM_PRE_TAP_ALERT_VAL:8:12 */ 4595 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1404, 12, 8) 4596 }; 4597 static uint32_t BCMI_TSCF_XGXS_TX_CTL1r_fields[] = 4598 { 4599 /* TXCOM_MAIN_TAP_ALERT_VAL:0:6 */ 4600 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1402, 6, 0) 4601 }; 4602 static uint32_t BCMI_TSCF_XGXS_TX_CTL2r_fields[] = 4603 { 4604 /* TXCOM_CL93N72_MAX_WAIT_TIMER_PERIOD:0:15 */ 4605 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1400, 15, 0) 4606 }; 4607 static uint32_t BCMI_TSCF_XGXS_TX_CTL3r_fields[] = 4608 { 4609 /* TXCOM_CL93N72_WAIT_CNTR_LIMIT:0:8 */ 4610 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1401, 8, 0) 4611 }; 4612 static uint32_t BCMI_TSCF_XGXS_TX_PI_PMD_CTL0r_fields[] = 4613 { 4614 /* TX_PI_EN:0:0 */ 4615 PHYMOD_SYMBOL_FIELD_ENCODE(1448, 0, 0), 4616 /* TX_PI_JITTER_FILTER_EN:1:1 */ 4617 PHYMOD_SYMBOL_FIELD_ENCODE(1459, 1, 1), 4618 /* TX_PI_EXT_CTRL_EN:2:2 */ 4619 PHYMOD_SYMBOL_FIELD_ENCODE(1449, 2, 2), 4620 /* TX_PI_FREQ_OVERRIDE_EN:3:3 */ 4621 PHYMOD_SYMBOL_FIELD_ENCODE(1452, 3, 3), 4622 /* TX_PI_SJ_GEN_EN:4:4 */ 4623 PHYMOD_SYMBOL_FIELD_ENCODE(1476, 4, 4), 4624 /* TX_PI_SSC_GEN_EN:5:5 */ 4625 PHYMOD_SYMBOL_FIELD_ENCODE(1477, 5, 5), 4626 /* TX_PI_JIT_SSC_FREQ_MODE:6:6 */ 4627 PHYMOD_SYMBOL_FIELD_ENCODE(1462, 6, 6), 4628 /* TX_PI_SECOND_ORDER_LOOP_EN:7:7 */ 4629 PHYMOD_SYMBOL_FIELD_ENCODE(1475, 7, 7), 4630 /* TX_PI_FIRST_ORDER_BWSEL_INTEG:8:9 */ 4631 PHYMOD_SYMBOL_FIELD_ENCODE(1451, 9, 8), 4632 /* TX_PI_SECOND_ORDER_BWSEL_INTEG:10:11 */ 4633 PHYMOD_SYMBOL_FIELD_ENCODE(1474, 11, 10), 4634 /* TX_PI_EXT_PHASE_BWSEL_INTEG:12:14 */ 4635 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1450, 14, 12) 4636 }; 4637 static uint32_t BCMI_TSCF_XGXS_TX_PI_PMD_CTL1r_fields[] = 4638 { 4639 /* TX_PI_FREQ_OVERRIDE_VAL:0:14 */ 4640 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1453, 14, 0) 4641 }; 4642 static uint32_t BCMI_TSCF_XGXS_TX_PI_PMD_CTL2r_fields[] = 4643 { 4644 /* TX_PI_JIT_FREQ_IDX:0:5 */ 4645 PHYMOD_SYMBOL_FIELD_ENCODE(1461, 5, 0), 4646 /* TX_PI_JIT_AMP:8:13 */ 4647 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1460, 13, 8) 4648 }; 4649 static uint32_t BCMI_TSCF_XGXS_TX_PI_PMD_CTL3r_fields[] = 4650 { 4651 /* TX_PI_PHASE_OVERRIDE:0:0 */ 4652 PHYMOD_SYMBOL_FIELD_ENCODE(1468, 0, 0), 4653 /* TX_PI_PHASE_STROBE:1:1 */ 4654 PHYMOD_SYMBOL_FIELD_ENCODE(1471, 1, 1), 4655 /* TX_PI_PHASE_STEP_DIR:2:2 */ 4656 PHYMOD_SYMBOL_FIELD_ENCODE(1469, 2, 2), 4657 /* TX_PI_PHASE_INVERT:4:4 */ 4658 PHYMOD_SYMBOL_FIELD_ENCODE(1467, 4, 4), 4659 /* TX_PI_PHASE_STEP_NUM:8:11 */ 4660 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1470, 11, 8) 4661 }; 4662 static uint32_t BCMI_TSCF_XGXS_TX_PI_PMD_CTL4r_fields[] = 4663 { 4664 /* TX_PI_FRZ_FRC:0:0 */ 4665 PHYMOD_SYMBOL_FIELD_ENCODE(1454, 0, 0), 4666 /* TX_PI_FRZ_FRC_VAL:1:1 */ 4667 PHYMOD_SYMBOL_FIELD_ENCODE(1455, 1, 1), 4668 /* TX_PI_FRZ_MODE:2:2 */ 4669 PHYMOD_SYMBOL_FIELD_ENCODE(1456, 2, 2), 4670 /* TX_PI_RESET_CODE_DBG:3:3 */ 4671 PHYMOD_SYMBOL_FIELD_ENCODE(1472, 3, 3), 4672 /* TX_PI_RMT_LPBK_BYPASS_FLT:4:4 */ 4673 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1473, 4, 4) 4674 }; 4675 static uint32_t BCMI_TSCF_XGXS_TX_PI_PMD_STS0r_fields[] = 4676 { 4677 /* TX_PI_PHASE_CNTR:0:6 */ 4678 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1465, 6, 0) 4679 }; 4680 static uint32_t BCMI_TSCF_XGXS_TX_PI_PMD_STS1r_fields[] = 4681 { 4682 /* TX_PI_INTEG1_REG:0:13 */ 4683 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1457, 13, 0) 4684 }; 4685 static uint32_t BCMI_TSCF_XGXS_TX_PI_PMD_STS2r_fields[] = 4686 { 4687 /* TX_PI_INTEG2_REG:0:14 */ 4688 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1458, 14, 0) 4689 }; 4690 static uint32_t BCMI_TSCF_XGXS_TX_PI_PMD_STS3r_fields[] = 4691 { 4692 /* TX_PI_PHASE_ERR:0:5 */ 4693 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1466, 5, 0) 4694 }; 4695 static uint32_t BCMI_TSCF_XGXS_TX_X1_T_CL91_FECr_fields[] = 4696 { 4697 /* TX_CL91_FEC_EN:0:0 */ 4698 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1427, 0, 0) 4699 }; 4700 static uint32_t BCMI_TSCF_XGXS_TX_X1_T_PMA_DELAYr_fields[] = 4701 { 4702 /* SINGLE_LANE_BITMUX_DELAY:0:1 */ 4703 PHYMOD_SYMBOL_FIELD_ENCODE(1307, 1, 0), 4704 /* TWO_LANE_BITMUX_DELAY:2:3 */ 4705 PHYMOD_SYMBOL_FIELD_ENCODE(1398, 3, 2), 4706 /* FIVE_LANE_BITMUX_DELAY:4:5 */ 4707 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(715, 5, 4) 4708 }; 4709 static uint32_t BCMI_TSCF_XGXS_TX_X1_T_PMA_WTRMKr_fields[] = 4710 { 4711 /* SINGLE_LANE_BITMUX_WATERMARK:0:3 */ 4712 PHYMOD_SYMBOL_FIELD_ENCODE(1308, 3, 0), 4713 /* TWO_LANE_BITMUX_WATERMARK:4:7 */ 4714 PHYMOD_SYMBOL_FIELD_ENCODE(1399, 7, 4), 4715 /* FIVE_LANE_BITMUX_WATERMARK:8:11 */ 4716 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(716, 11, 8) 4717 }; 4718 static uint32_t BCMI_TSCF_XGXS_TX_X2_CL82_0r_fields[] = 4719 { 4720 /* T_FIFO_MODE:0:1 */ 4721 PHYMOD_SYMBOL_FIELD_ENCODE(1490, 1, 0), 4722 /* CL82_TX_RF_ENABLE:4:4 */ 4723 PHYMOD_SYMBOL_FIELD_ENCODE(440, 4, 4), 4724 /* CL82_TX_LF_ENABLE:5:5 */ 4725 PHYMOD_SYMBOL_FIELD_ENCODE(438, 5, 5), 4726 /* CL82_TX_LI_ENABLE:6:6 */ 4727 PHYMOD_SYMBOL_FIELD_ENCODE(439, 6, 6), 4728 /* CL82_BYPASS_TXSM:10:10 */ 4729 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(430, 10, 10) 4730 }; 4731 static uint32_t BCMI_TSCF_XGXS_TX_X2_CL82_TX_STS0r_fields[] = 4732 { 4733 /* TXSM_STATE:0:2 */ 4734 PHYMOD_SYMBOL_FIELD_ENCODE(1426, 2, 0), 4735 /* T_TYPE_CODED:3:5 */ 4736 PHYMOD_SYMBOL_FIELD_ENCODE(1500, 5, 3), 4737 /* CL82_IDLE_DELETION_UNDERFLOW:6:6 */ 4738 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(434, 6, 6) 4739 }; 4740 static uint32_t BCMI_TSCF_XGXS_TX_X2_CL82_TX_STS1r_fields[] = 4741 { 4742 /* LTXSM_STATE:0:6 */ 4743 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(830, 6, 0) 4744 }; 4745 static uint32_t BCMI_TSCF_XGXS_TX_X2_MLD_SWP_CNTr_fields[] = 4746 { 4747 /* MLD_SWAP_COUNT:0:15 */ 4748 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(916, 15, 0) 4749 }; 4750 static uint32_t BCMI_TSCF_XGXS_TX_X4_CL36_CTLr_fields[] = 4751 { 4752 /* CL36TX_EN:0:0 */ 4753 PHYMOD_SYMBOL_FIELD_ENCODE(389, 0, 0), 4754 /* CL36TX_LPI_EN:1:1 */ 4755 PHYMOD_SYMBOL_FIELD_ENCODE(391, 1, 1), 4756 /* CL36TX_CATCH_ALL_8B10B_DIS:2:2 */ 4757 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(388, 2, 2) 4758 }; 4759 static uint32_t BCMI_TSCF_XGXS_TX_X4_CRED0r_fields[] = 4760 { 4761 /* CLOCKCNT0:0:13 */ 4762 PHYMOD_SYMBOL_FIELD_ENCODE(504, 13, 0), 4763 /* CREDITENABLE:14:14 */ 4764 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(541, 14, 14) 4765 }; 4766 static uint32_t BCMI_TSCF_XGXS_TX_X4_CRED1r_fields[] = 4767 { 4768 /* CLOCKCNT1:0:7 */ 4769 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(506, 7, 0) 4770 }; 4771 static uint32_t BCMI_TSCF_XGXS_TX_X4_ENC0r_fields[] = 4772 { 4773 /* T_ENC_MODE:0:1 */ 4774 PHYMOD_SYMBOL_FIELD_ENCODE(1487, 1, 0), 4775 /* CL49_TX_TL_MODE:5:6 */ 4776 PHYMOD_SYMBOL_FIELD_ENCODE(407, 6, 5), 4777 /* CL49_BYPASS_TXSM:9:9 */ 4778 PHYMOD_SYMBOL_FIELD_ENCODE(394, 9, 9), 4779 /* HG2_ENABLE:10:10 */ 4780 PHYMOD_SYMBOL_FIELD_ENCODE(729, 10, 10), 4781 /* HG2_MESSAGE_INVALID_CODE_ENABLE:11:11 */ 4782 PHYMOD_SYMBOL_FIELD_ENCODE(730, 11, 11), 4783 /* HG2_CODEC:12:12 */ 4784 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(728, 12, 12) 4785 }; 4786 static uint32_t BCMI_TSCF_XGXS_TX_X4_ENC_STS0r_fields[] = 4787 { 4788 /* CL49_TXSM_STATE:0:2 */ 4789 PHYMOD_SYMBOL_FIELD_ENCODE(402, 2, 0), 4790 /* CL49_T_TYPE_CODED:3:6 */ 4791 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(408, 6, 3) 4792 }; 4793 static uint32_t BCMI_TSCF_XGXS_TX_X4_ENC_STS1r_fields[] = 4794 { 4795 /* CL49_LTXSM_STATE:0:7 */ 4796 PHYMOD_SYMBOL_FIELD_ENCODE(395, 7, 0), 4797 /* CL49_TX_FAULT_DET:8:8 */ 4798 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(403, 8, 8) 4799 }; 4800 static uint32_t BCMI_TSCF_XGXS_TX_X4_LOOPCNTr_fields[] = 4801 { 4802 /* LOOPCNT1:0:5 */ 4803 PHYMOD_SYMBOL_FIELD_ENCODE(810, 5, 0), 4804 /* LOOPCNT0:6:13 */ 4805 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(808, 13, 6) 4806 }; 4807 static uint32_t BCMI_TSCF_XGXS_TX_X4_MAC_CREDGENCNTr_fields[] = 4808 { 4809 /* MAC_CREDITGENCNT:0:12 */ 4810 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(831, 12, 0) 4811 }; 4812 static uint32_t BCMI_TSCF_XGXS_TX_X4_MISCr_fields[] = 4813 { 4814 /* ENABLE_TX_LANE:0:0 */ 4815 PHYMOD_SYMBOL_FIELD_ENCODE(653, 0, 0), 4816 /* RSTB_TX_LANE:1:1 */ 4817 PHYMOD_SYMBOL_FIELD_ENCODE(1103, 1, 1), 4818 /* OS_MODE:2:5 */ 4819 PHYMOD_SYMBOL_FIELD_ENCODE(940, 5, 2), 4820 /* CL49_TX_RF_ENABLE:6:6 */ 4821 PHYMOD_SYMBOL_FIELD_ENCODE(406, 6, 6), 4822 /* CL49_TX_LF_ENABLE:7:7 */ 4823 PHYMOD_SYMBOL_FIELD_ENCODE(404, 7, 7), 4824 /* CL49_TX_LI_ENABLE:8:8 */ 4825 PHYMOD_SYMBOL_FIELD_ENCODE(405, 8, 8), 4826 /* T_PMA_40B_MODE:9:9 */ 4827 PHYMOD_SYMBOL_FIELD_ENCODE(1494, 9, 9), 4828 /* FEC_ENABLE:10:10 */ 4829 PHYMOD_SYMBOL_FIELD_ENCODE(692, 10, 10), 4830 /* T_PMA_BTMX_MODE:11:12 */ 4831 PHYMOD_SYMBOL_FIELD_ENCODE(1496, 12, 11), 4832 /* SCR_MODE:13:15 */ 4833 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1276, 15, 13) 4834 }; 4835 static uint32_t BCMI_TSCF_XGXS_TX_X4_PCS_STS_LATCHr_fields[] = 4836 { 4837 /* LPI_RECEIVED_LH:0:0 */ 4838 PHYMOD_SYMBOL_FIELD_ENCODE(818, 0, 0), 4839 /* REMOTE_FAULT_LH:1:1 */ 4840 PHYMOD_SYMBOL_FIELD_ENCODE(1066, 1, 1), 4841 /* LOCAL_FAULT_LH:2:2 */ 4842 PHYMOD_SYMBOL_FIELD_ENCODE(802, 2, 2), 4843 /* LINK_INTERRUPT_LH:3:3 */ 4844 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(781, 3, 3) 4845 }; 4846 static uint32_t BCMI_TSCF_XGXS_TX_X4_PCS_STS_LIVEr_fields[] = 4847 { 4848 /* TX_LPI_RECEIVED:0:0 */ 4849 PHYMOD_SYMBOL_FIELD_ENCODE(1442, 0, 0), 4850 /* TX_LINK_INTERRUPT:1:1 */ 4851 PHYMOD_SYMBOL_FIELD_ENCODE(1440, 1, 1), 4852 /* TX_REMOTE_FAULT:2:2 */ 4853 PHYMOD_SYMBOL_FIELD_ENCODE(1480, 2, 2), 4854 /* TX_LOCAL_FAULT:3:3 */ 4855 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1441, 3, 3) 4856 }; 4857 static uint32_t BCMI_TSCF_XGXS_TX_X4_PMA_STSr_fields[] = 4858 { 4859 /* T_PMA_OVERFLOW:0:0 */ 4860 PHYMOD_SYMBOL_FIELD_ENCODE(1498, 0, 0), 4861 /* T_PMA_UNDERFLOW:1:1 */ 4862 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1499, 1, 1) 4863 }; 4864 static uint32_t BCMI_TSCF_XGXS_UC_AHB_CTL0r_fields[] = 4865 { 4866 /* MICRO_RA_WRDATASIZE:0:1 */ 4867 PHYMOD_SYMBOL_FIELD_ENCODE(892, 1, 0), 4868 /* MICRO_RA_RDDATASIZE:4:5 */ 4869 PHYMOD_SYMBOL_FIELD_ENCODE(887, 5, 4), 4870 /* MICRO_RA_INIT:8:9 */ 4871 PHYMOD_SYMBOL_FIELD_ENCODE(883, 9, 8), 4872 /* MICRO_AUTOINC_WRADDR_EN:12:12 */ 4873 PHYMOD_SYMBOL_FIELD_ENCODE(854, 12, 12), 4874 /* MICRO_AUTOINC_RDADDR_EN:13:13 */ 4875 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(853, 13, 13) 4876 }; 4877 static uint32_t BCMI_TSCF_XGXS_UC_AHB_RDADDR_LSWr_fields[] = 4878 { 4879 /* MICRO_RA_RDADDR_LSW:0:15 */ 4880 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(885, 15, 0) 4881 }; 4882 static uint32_t BCMI_TSCF_XGXS_UC_AHB_RDADDR_MSWr_fields[] = 4883 { 4884 /* MICRO_RA_RDADDR_MSW:0:15 */ 4885 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(886, 15, 0) 4886 }; 4887 static uint32_t BCMI_TSCF_XGXS_UC_AHB_RDDATA_LSWr_fields[] = 4888 { 4889 /* MICRO_RA_RDDATA_LSW:0:15 */ 4890 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(888, 15, 0) 4891 }; 4892 static uint32_t BCMI_TSCF_XGXS_UC_AHB_RDDATA_MSWr_fields[] = 4893 { 4894 /* MICRO_RA_RDDATA_MSW:0:15 */ 4895 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(889, 15, 0) 4896 }; 4897 static uint32_t BCMI_TSCF_XGXS_UC_AHB_STS0r_fields[] = 4898 { 4899 /* MICRO_RA_INITDONE:0:0 */ 4900 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(884, 0, 0) 4901 }; 4902 static uint32_t BCMI_TSCF_XGXS_UC_AHB_WRADDR_LSWr_fields[] = 4903 { 4904 /* MICRO_RA_WRADDR_LSW:0:15 */ 4905 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(890, 15, 0) 4906 }; 4907 static uint32_t BCMI_TSCF_XGXS_UC_AHB_WRADDR_MSWr_fields[] = 4908 { 4909 /* MICRO_RA_WRADDR_MSW:0:15 */ 4910 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(891, 15, 0) 4911 }; 4912 static uint32_t BCMI_TSCF_XGXS_UC_AHB_WRDATA_LSWr_fields[] = 4913 { 4914 /* MICRO_RA_WRDATA_LSW:0:15 */ 4915 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(893, 15, 0) 4916 }; 4917 static uint32_t BCMI_TSCF_XGXS_UC_AHB_WRDATA_MSWr_fields[] = 4918 { 4919 /* MICRO_RA_WRDATA_MSW:0:15 */ 4920 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(894, 15, 0) 4921 }; 4922 static uint32_t BCMI_TSCF_XGXS_UC_CLK_CTL0r_fields[] = 4923 { 4924 /* MICRO_MASTER_CLK_EN:0:0 */ 4925 PHYMOD_SYMBOL_FIELD_ENCODE(868, 0, 0), 4926 /* MICRO_CORE_CLK_EN:1:1 */ 4927 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(857, 1, 1) 4928 }; 4929 static uint32_t BCMI_TSCF_XGXS_UC_CODE_RAM_ECCCONTRO1r_fields[] = 4930 { 4931 /* MICRO_RA_ECC_WRDATA:0:6 */ 4932 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(882, 6, 0) 4933 }; 4934 static uint32_t BCMI_TSCF_XGXS_UC_CODE_RAM_ECCCTL0r_fields[] = 4935 { 4936 /* MICRO_ECCG_MODE:0:0 */ 4937 PHYMOD_SYMBOL_FIELD_ENCODE(861, 0, 0), 4938 /* MICRO_ECC_FRC_DISABLE:1:1 */ 4939 PHYMOD_SYMBOL_FIELD_ENCODE(863, 1, 1), 4940 /* MICRO_ECC_CORRUPT:4:5 */ 4941 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(862, 5, 4) 4942 }; 4943 static uint32_t BCMI_TSCF_XGXS_UC_CODE_RAM_ECCSTS0r_fields[] = 4944 { 4945 /* MICRO_CODE_RAM_ECC_ADDRESS:0:14 */ 4946 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(855, 14, 0) 4947 }; 4948 static uint32_t BCMI_TSCF_XGXS_UC_CODE_RAM_ECCSTS1r_fields[] = 4949 { 4950 /* MICRO_RA_ECC_RDDATA:0:6 */ 4951 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(881, 6, 0) 4952 }; 4953 static uint32_t BCMI_TSCF_XGXS_UC_CODE_RAM_TESTIFCTL0r_fields[] = 4954 { 4955 /* MICRO_CODE_RAM_TM:0:13 */ 4956 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(856, 13, 0) 4957 }; 4958 static uint32_t BCMI_TSCF_XGXS_UC_PRAMIF_AHB_WRADDR_LSWr_fields[] = 4959 { 4960 /* MICRO_PRAMIF_AHB_WRADDR_LSW:2:15 */ 4961 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(870, 15, 2) 4962 }; 4963 static uint32_t BCMI_TSCF_XGXS_UC_PRAMIF_AHB_WRADDR_MSWr_fields[] = 4964 { 4965 /* MICRO_PRAMIF_AHB_WRADDR_MSW:0:15 */ 4966 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(871, 15, 0) 4967 }; 4968 static uint32_t BCMI_TSCF_XGXS_UC_PRAMIF_CTL0r_fields[] = 4969 { 4970 /* MICRO_PRAMIF_EN:0:0 */ 4971 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(872, 0, 0) 4972 }; 4973 static uint32_t BCMI_TSCF_XGXS_UC_PVT_STS0r_fields[] = 4974 { 4975 /* MICRO_PVT_TEMPDATA_RMI:0:9 */ 4976 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(878, 9, 0) 4977 }; 4978 static uint32_t BCMI_TSCF_XGXS_UC_RAM_CTL0r_fields[] = 4979 { 4980 /* MICRO_DR_LOOKTAB_EN:0:0 */ 4981 PHYMOD_SYMBOL_FIELD_ENCODE(859, 0, 0), 4982 /* MICRO_DR_SIZE:8:13 */ 4983 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(860, 13, 8) 4984 }; 4985 static uint32_t BCMI_TSCF_XGXS_UC_RMI_AHB_CTL1r_fields[] = 4986 { 4987 /* MICRO_M0_HRESP_EN:0:0 */ 4988 PHYMOD_SYMBOL_FIELD_ENCODE(867, 0, 0), 4989 /* MICRO_SW_PMI_HP_RSTB:1:1 */ 4990 PHYMOD_SYMBOL_FIELD_ENCODE(912, 1, 1), 4991 /* MICRO_SW_PMI_HP_EXT_RSTB:2:2 */ 4992 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(911, 2, 2) 4993 }; 4994 static uint32_t BCMI_TSCF_XGXS_UC_RMI_AHB_STS1r_fields[] = 4995 { 4996 /* MICRO_M0_DEFAULT_SLAVE_ERROR:0:0 */ 4997 PHYMOD_SYMBOL_FIELD_ENCODE(866, 0, 0), 4998 /* MICRO_RMI_DEFAULT_SLAVE_ERROR:1:1 */ 4999 PHYMOD_SYMBOL_FIELD_ENCODE(895, 1, 1), 5000 /* MICRO_PR_DEFAULT_SLAVE_ERROR:2:2 */ 5001 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(875, 2, 2) 5002 }; 5003 static uint32_t BCMI_TSCF_XGXS_UC_RMI_EXT_INTR_CTL0r_fields[] = 5004 { 5005 /* MICRO_RMI_MBOX_MSGOUT_INTR_EN:0:0 */ 5006 PHYMOD_SYMBOL_FIELD_ENCODE(906, 0, 0), 5007 /* MICRO_RMI_ECC_CORR_ERR_INTR_EN:4:4 */ 5008 PHYMOD_SYMBOL_FIELD_ENCODE(896, 4, 4), 5009 /* MICRO_RMI_ECC_UNCORR_ERR_INTR_EN:5:5 */ 5010 PHYMOD_SYMBOL_FIELD_ENCODE(900, 5, 5), 5011 /* MICRO_RMI_ECC_MULTIROW_ERR_INTR_EN:6:6 */ 5012 PHYMOD_SYMBOL_FIELD_ENCODE(898, 6, 6), 5013 /* MICRO_RMI_M0_LOCKUP_INTR_EN:8:8 */ 5014 PHYMOD_SYMBOL_FIELD_ENCODE(902, 8, 8), 5015 /* MICRO_RMI_M0_SYSTEMRESETREQ_INTR_EN:9:9 */ 5016 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(904, 9, 9) 5017 }; 5018 static uint32_t BCMI_TSCF_XGXS_UC_RMI_EXT_INTR_STS0r_fields[] = 5019 { 5020 /* MICRO_RMI_MBOX_MSGOUT_STATUS:0:0 */ 5021 PHYMOD_SYMBOL_FIELD_ENCODE(907, 0, 0), 5022 /* MICRO_RMI_ECC_CORR_ERR_STATUS:4:4 */ 5023 PHYMOD_SYMBOL_FIELD_ENCODE(897, 4, 4), 5024 /* MICRO_RMI_ECC_UNCORR_ERR_STATUS:5:5 */ 5025 PHYMOD_SYMBOL_FIELD_ENCODE(901, 5, 5), 5026 /* MICRO_RMI_ECC_MULTIROW_ERR_STATUS:6:6 */ 5027 PHYMOD_SYMBOL_FIELD_ENCODE(899, 6, 6), 5028 /* MICRO_RMI_M0_LOCKUP_STATUS:8:8 */ 5029 PHYMOD_SYMBOL_FIELD_ENCODE(903, 8, 8), 5030 /* MICRO_RMI_M0_SYSTEMRESETREQ_STATUS:9:9 */ 5031 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(905, 9, 9) 5032 }; 5033 static uint32_t BCMI_TSCF_XGXS_UC_RMI_MBOX_CTL0r_fields[] = 5034 { 5035 /* MICRO_RMI_MBOX_SEND_MSGIN:0:0 */ 5036 PHYMOD_SYMBOL_FIELD_ENCODE(908, 0, 0), 5037 /* MICRO_GEN_INTR_RMI_MBOX0WR:1:1 */ 5038 PHYMOD_SYMBOL_FIELD_ENCODE(864, 1, 1), 5039 /* MICRO_GEN_INTR_RMI_MBOX1WR:2:2 */ 5040 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(865, 2, 2) 5041 }; 5042 static uint32_t BCMI_TSCF_XGXS_UC_RMI_PR_AINC_NXT_WRADDR_LSWr_fields[] = 5043 { 5044 /* MICRO_PR_AUTOINC_NXT_WRADDR_LSW:0:15 */ 5045 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(874, 15, 0) 5046 }; 5047 static uint32_t BCMI_TSCF_XGXS_UC_RMI_PVT_CTL0r_fields[] = 5048 { 5049 /* MICRO_PVT_TEMPDATA_FRCVAL:0:9 */ 5050 PHYMOD_SYMBOL_FIELD_ENCODE(877, 9, 0), 5051 /* MICRO_PVT_TEMPDATA_FRC:12:12 */ 5052 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(876, 12, 12) 5053 }; 5054 static uint32_t BCMI_TSCF_XGXS_UC_RMI_RA_AINC_NXT_RDADDR_LSWr_fields[] = 5055 { 5056 /* MICRO_RA_AUTOINC_NXT_RDADDR_LSW:0:15 */ 5057 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(879, 15, 0) 5058 }; 5059 static uint32_t BCMI_TSCF_XGXS_UC_RMI_RA_AINC_NXT_WRADDR_LSWr_fields[] = 5060 { 5061 /* MICRO_RA_AUTOINC_NXT_WRADDR_LSW:0:15 */ 5062 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(880, 15, 0) 5063 }; 5064 static uint32_t BCMI_TSCF_XGXS_UC_RMI_TO_UC_MBOX0r_fields[] = 5065 { 5066 /* MICRO_RMI_TO_MICRO_MBOX0:0:15 */ 5067 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(909, 15, 0) 5068 }; 5069 static uint32_t BCMI_TSCF_XGXS_UC_RMI_TO_UC_MBOX1r_fields[] = 5070 { 5071 /* MICRO_RMI_TO_MICRO_MBOX1:0:15 */ 5072 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(910, 15, 0) 5073 }; 5074 static uint32_t BCMI_TSCF_XGXS_UC_RST_CTL0r_fields[] = 5075 { 5076 /* MICRO_MASTER_RSTB:0:0 */ 5077 PHYMOD_SYMBOL_FIELD_ENCODE(869, 0, 0), 5078 /* MICRO_CORE_RSTB:1:1 */ 5079 PHYMOD_SYMBOL_FIELD_ENCODE(858, 1, 1), 5080 /* MICRO_PRAM_IF_RSTB:3:3 */ 5081 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(873, 3, 3) 5082 }; 5083 static uint32_t BCMI_TSCF_XGXS_UC_UC_TO_RMI_MBOX0r_fields[] = 5084 { 5085 /* MICRO_TO_RMI_MBOX0:0:15 */ 5086 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(913, 15, 0) 5087 }; 5088 static uint32_t BCMI_TSCF_XGXS_UC_UC_TO_RMI_MBOX1r_fields[] = 5089 { 5090 /* MICRO_TO_RMI_MBOX1:0:15 */ 5091 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(914, 15, 0) 5092 }; 5093 5094 5095 5096 /******************************************************************************* 5097 * 5098 * The following is the field name table. 5099 */ 5100 #if PHYMOD_CONFIG_INCLUDE_FIELD_NAMES == 1 5101 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_NAMES_BCMI_TSCF_XGXS 5102 const char* bcmi_tscf_xgxs_fields[] = 5103 { 5104 "ABILITY_DETECT", 5105 "ACK_DETECT", 5106 "ACQ_CDR_TIMEOUT", 5107 "AD_TO_CL73_EN", 5108 "AFE_RX_PWRDN_FRC", 5109 "AFE_RX_PWRDN_FRC_VAL", 5110 "AFE_RX_RCLK20_PWRDN_FRC", 5111 "AFE_RX_RCLK20_PWRDN_FRC_VAL", 5112 "AFE_RX_RESET_FRC", 5113 "AFE_RX_RESET_FRC_VAL", 5114 "AFE_SIGDET_PWRDN", 5115 "AFE_SIGDET_THRESH", 5116 "AFE_SIGNAL_DETECT_DIS", 5117 "AFE_S_PLL_PWRDN", 5118 "AFE_S_PLL_RESET_FRC", 5119 "AFE_S_PLL_RESET_FRC_VAL", 5120 "AFE_TX_PWRDN_FRC", 5121 "AFE_TX_PWRDN_FRC_VAL", 5122 "AFE_TX_RESET_FRC", 5123 "AFE_TX_RESET_FRC_VAL", 5124 "AMRKR_SPACING_ERR_LATCH_MUX_PSLL_0", 5125 "AMRKR_SPACING_ERR_LATCH_MUX_PSLL_1", 5126 "AMRKR_SPACING_ERR_LATCH_MUX_PSLL_2", 5127 "AMRKR_SPACING_ERR_LATCH_MUX_PSLL_3", 5128 "AMRKR_SPACING_ERR_LATCH_MUX_PSLL_4", 5129 "AMS_PLL_BGINT", 5130 "AMS_PLL_BGIP", 5131 "AMS_PLL_BGR_CTATADJ", 5132 "AMS_PLL_BGR_PTATADJ", 5133 "AMS_PLL_CAL_AUX", 5134 "AMS_PLL_CAL_OFF", 5135 "AMS_PLL_COMP_VTH", 5136 "AMS_PLL_DRV_HV_DISABLE", 5137 "AMS_PLL_ENABLE_FTUNE", 5138 "AMS_PLL_EN_HRZ", 5139 "AMS_PLL_FORCE_KVH_BW", 5140 "AMS_PLL_FORCE_RESCAL", 5141 "AMS_PLL_IMAX_IBIAS", 5142 "AMS_PLL_IMAX_ICK", 5143 "AMS_PLL_IMAX_ICKGEN", 5144 "AMS_PLL_IMAX_ICLKIDRV1", 5145 "AMS_PLL_IMAX_ICLKINT", 5146 "AMS_PLL_IMAX_ICLKODRV1", 5147 "AMS_PLL_IMAX_ICMLDIV", 5148 "AMS_PLL_IMAX_ICOMP", 5149 "AMS_PLL_IMAX_ICP", 5150 "AMS_PLL_IMAX_IOP", 5151 "AMS_PLL_IMAX_IRXCLKBUF", 5152 "AMS_PLL_IMIN_IBIAS", 5153 "AMS_PLL_IMIN_ICK", 5154 "AMS_PLL_IMIN_ICKGEN", 5155 "AMS_PLL_IMIN_ICLKIDRV1", 5156 "AMS_PLL_IMIN_ICLKINT", 5157 "AMS_PLL_IMIN_ICLKODRV1", 5158 "AMS_PLL_IMIN_ICMLDIV", 5159 "AMS_PLL_IMIN_ICOMP", 5160 "AMS_PLL_IMIN_ICP", 5161 "AMS_PLL_IMIN_IOP", 5162 "AMS_PLL_IMIN_IRXCLKBUF", 5163 "AMS_PLL_IMODE_IBIAS", 5164 "AMS_PLL_IMODE_ICK", 5165 "AMS_PLL_IMODE_ICKGEN", 5166 "AMS_PLL_IMODE_ICLKIDRV1", 5167 "AMS_PLL_IMODE_ICLKINT", 5168 "AMS_PLL_IMODE_ICLKODRV1", 5169 "AMS_PLL_IMODE_ICMLDIV", 5170 "AMS_PLL_IMODE_ICOMP", 5171 "AMS_PLL_IMODE_ICP", 5172 "AMS_PLL_IMODE_IOP", 5173 "AMS_PLL_IMODE_IRXCLKBUF", 5174 "AMS_PLL_IQP", 5175 "AMS_PLL_IVCO", 5176 "AMS_PLL_KVH_FORCE", 5177 "AMS_PLL_MIX1P2CR_CTATADJ", 5178 "AMS_PLL_MIX1P2CR_PTATADJ", 5179 "AMS_PLL_MIX3P1CR_CTATADJ", 5180 "AMS_PLL_MIX3P1CR_PTATADJ", 5181 "AMS_PLL_MIX3P1C_CALR_CTATADJ", 5182 "AMS_PLL_MIX3P1C_CALR_PTATADJ", 5183 "AMS_PLL_PLL2RX_CLKBW", 5184 "AMS_PLL_REFH_PLL", 5185 "AMS_PLL_REFL_PLL", 5186 "AMS_PLL_RESET", 5187 "AMS_PLL_SET_CLK4TSC", 5188 "AMS_PLL_SPARE_101_96", 5189 "AMS_PLL_SPARE_117_112", 5190 "AMS_PLL_SPARE_23_22", 5191 "AMS_PLL_STS", 5192 "AMS_PLL_TEST_BG_OPAMP_BIAS", 5193 "AMS_PLL_TEST_PLL", 5194 "AMS_PLL_TEST_PNP", 5195 "AMS_PLL_TEST_PORT_MAX_AMPLITUDE", 5196 "AMS_PLL_TEST_RX", 5197 "AMS_PLL_TEST_VC", 5198 "AMS_PLL_TEST_VREF", 5199 "AMS_PLL_VBYPASS", 5200 "AMS_PLL_VCOICTRL", 5201 "AMS_PLL_VCO_INDICATOR", 5202 "AMS_PLL_VDDR_BGB", 5203 "AMS_RX_CLK_BW_CTRL", 5204 "AMS_RX_CM_VOLTAGE_IBIAS", 5205 "AMS_RX_D2C_CLKBUF_IBIAS", 5206 "AMS_RX_DAC4CK_DAT", 5207 "AMS_RX_DAC4CK_LMS", 5208 "AMS_RX_DAC4CK_PHS", 5209 "AMS_RX_DC_COUPLE", 5210 "AMS_RX_DC_OFFSET", 5211 "AMS_RX_DC_OFFSET_RANGE", 5212 "AMS_RX_DFE_HGAIN_EN", 5213 "AMS_RX_DFE_SLICER_CAL_IBIAS", 5214 "AMS_RX_DFE_SLICER_IBIAS", 5215 "AMS_RX_DFE_SUM_BUF_IBIAS", 5216 "AMS_RX_DFE_TAP_WEIGHT_IBIAS", 5217 "AMS_RX_DLL_IBIAS", 5218 "AMS_RX_EN_TAP9DELAY", 5219 "AMS_RX_EQ_LZ_EN", 5220 "AMS_RX_FORCE_DC_OFFSET", 5221 "AMS_RX_MASTER_DIODES_IBIAS", 5222 "AMS_RX_MET_R_IBIAS", 5223 "AMS_RX_OFFSET_CORRECTION_IBIAS", 5224 "AMS_RX_OFFSET_CORRECTION_RESCAL_MUX", 5225 "AMS_RX_PD_CH_P1", 5226 "AMS_RX_PEAKING_FILTER_IBIAS", 5227 "AMS_RX_PEAKING_FILTER_RESCAL_MUX", 5228 "AMS_RX_PHASE_INTERPOLATORS_IBIAS", 5229 "AMS_RX_PWRDN_FTAP", 5230 "AMS_RX_RX_OFFSET_PD", 5231 "AMS_RX_SEL_D2CLP", 5232 "AMS_RX_SEL_TH4DFE", 5233 "AMS_RX_SEL_UGBW", 5234 "AMS_RX_SHORT_VGA_OUTPUT", 5235 "AMS_RX_SIGDET_BYPASS", 5236 "AMS_RX_SIGDET_IBIAS", 5237 "AMS_RX_SIGDET_POWER_SAVE", 5238 "AMS_RX_SIGDET_PWRDN", 5239 "AMS_RX_SIGDET_THRESHOLD", 5240 "AMS_RX_SPARE_111_104", 5241 "AMS_RX_SPARE_123", 5242 "AMS_RX_SPARE_135_134", 5243 "AMS_RX_SPARE_143_142", 5244 "AMS_RX_SPARE_151_150", 5245 "AMS_RX_SPARE_159", 5246 "AMS_RX_SPARE_16", 5247 "AMS_RX_SPARE_63", 5248 "AMS_RX_SPARE_95", 5249 "AMS_RX_STS", 5250 "AMS_RX_TBD_IBIAS", 5251 "AMS_RX_TERMINATION_RESISTOR_RESCAL_MUX", 5252 "AMS_RX_TPORT_EN", 5253 "AMS_RX_VGA0_IBIAS", 5254 "AMS_RX_VGA0_RESCAL_MUX", 5255 "AMS_RX_VGA1_IBIAS", 5256 "AMS_RX_VGA1_RESCAL_MUX", 5257 "AMS_RX_VGA2_IBIAS", 5258 "AMS_RX_VGA2_RESCAL_MUX", 5259 "AMS_RX_VGA3_IBIAS", 5260 "AMS_RX_VGA3_RESCAL_MUX", 5261 "AMS_RX_VGA_10G_BW", 5262 "AMS_RX_VGA_LOW_GAIN", 5263 "AMS_RX_VGA_STEP_MODE", 5264 "AMS_TX_AMP_CTL", 5265 "AMS_TX_CAL_AUX", 5266 "AMS_TX_CAL_OFF", 5267 "AMS_TX_DCC_DIS", 5268 "AMS_TX_DCC_SEL", 5269 "AMS_TX_DRIVERMODE", 5270 "AMS_TX_ELEC_IDLE_AUX", 5271 "AMS_TX_IBIAS", 5272 "AMS_TX_ICML", 5273 "AMS_TX_ILDO", 5274 "AMS_TX_LDO_VREF", 5275 "AMS_TX_POST2_COEF", 5276 "AMS_TX_POST3_COEF", 5277 "AMS_TX_SEL_EMPH_MODE", 5278 "AMS_TX_SIGN_POST2", 5279 "AMS_TX_SIGN_POST3", 5280 "AMS_TX_SPARE_0", 5281 "AMS_TX_SPARE_21_19", 5282 "AMS_TX_SPARE_31", 5283 "AMS_TX_SPARE_3_1", 5284 "AMS_TX_SPARE_63_48", 5285 "AMS_TX_STS", 5286 "AMS_TX_TEST_DATA", 5287 "AMS_TX_TICKSEL", 5288 "AMS_TX_VDDR_BGB", 5289 "AM_LOCK_0", 5290 "AM_LOCK_1", 5291 "AM_LOCK_2", 5292 "AM_LOCK_3", 5293 "AM_LOCK_4", 5294 "AM_LOCK_HIS_STATE_PSLL_0", 5295 "AM_LOCK_HIS_STATE_PSLL_1", 5296 "AM_LOCK_HIS_STATE_PSLL_2", 5297 "AM_LOCK_HIS_STATE_PSLL_3", 5298 "AM_LOCK_HIS_STATE_PSLL_4", 5299 "AM_LOCK_LH_0", 5300 "AM_LOCK_LH_1", 5301 "AM_LOCK_LH_2", 5302 "AM_LOCK_LH_3", 5303 "AM_LOCK_LH_4", 5304 "AM_LOCK_LL_0", 5305 "AM_LOCK_LL_1", 5306 "AM_LOCK_LL_2", 5307 "AM_LOCK_LL_3", 5308 "AM_LOCK_LL_4", 5309 "AM_LOCK_STATE_PSLL_0", 5310 "AM_LOCK_STATE_PSLL_1", 5311 "AM_LOCK_STATE_PSLL_2", 5312 "AM_LOCK_STATE_PSLL_3", 5313 "AM_LOCK_STATE_PSLL_4", 5314 "AM_TIMER_INIT_RX_VAL", 5315 "AN", 5316 "AN_ACTIVE", 5317 "AN_COMPLETE", 5318 "AN_COMPLETED_SW", 5319 "AN_ENABLE", 5320 "AN_FAIL_COUNT", 5321 "AN_FAIL_COUNT_LIMIT", 5322 "AN_GOOD_CHECK", 5323 "AN_GOOD_CHECK_TRAP", 5324 "AN_GOOD_TRAP", 5325 "AN_HCD_CL72", 5326 "AN_HCD_DUPLEX", 5327 "AN_HCD_FEC", 5328 "AN_HCD_PAUSE", 5329 "AN_HCD_RES_DISABLE", 5330 "AN_HCD_SPEED", 5331 "AN_OUI_OVERRIDE_BAM73_ADV", 5332 "AN_OUI_OVERRIDE_BAM73_DET", 5333 "AN_OUI_OVERRIDE_HPAM_ADV", 5334 "AN_OUI_OVERRIDE_HPAM_DET", 5335 "AN_PRIORITY_100G_CR4", 5336 "AN_PRIORITY_100G_HG2_CR4", 5337 "AN_PRIORITY_100G_HG2_KR4", 5338 "AN_PRIORITY_100G_KR4", 5339 "AN_PRIORITY_10G_HG2_KR1", 5340 "AN_PRIORITY_10G_KR1", 5341 "AN_PRIORITY_1G_KX1", 5342 "AN_PRIORITY_20G_CR1", 5343 "AN_PRIORITY_20G_CR2", 5344 "AN_PRIORITY_20G_HG2_CR1", 5345 "AN_PRIORITY_20G_HG2_CR2", 5346 "AN_PRIORITY_20G_HG2_KR1", 5347 "AN_PRIORITY_20G_HG2_KR2", 5348 "AN_PRIORITY_20G_KR1", 5349 "AN_PRIORITY_20G_KR2", 5350 "AN_PRIORITY_25G_CR1", 5351 "AN_PRIORITY_25G_HG2_CR1", 5352 "AN_PRIORITY_25G_HG2_KR1", 5353 "AN_PRIORITY_25G_KR1", 5354 "AN_PRIORITY_40G_CR2", 5355 "AN_PRIORITY_40G_CR4", 5356 "AN_PRIORITY_40G_HG2_CR2", 5357 "AN_PRIORITY_40G_HG2_CR4", 5358 "AN_PRIORITY_40G_HG2_KR2", 5359 "AN_PRIORITY_40G_HG2_KR4", 5360 "AN_PRIORITY_40G_KR2", 5361 "AN_PRIORITY_40G_KR4", 5362 "AN_PRIORITY_50G_CR2", 5363 "AN_PRIORITY_50G_CR4", 5364 "AN_PRIORITY_50G_HG2_CR2", 5365 "AN_PRIORITY_50G_HG2_CR4", 5366 "AN_PRIORITY_50G_HG2_KR2", 5367 "AN_PRIORITY_50G_HG2_KR4", 5368 "AN_PRIORITY_50G_KR2", 5369 "AN_PRIORITY_50G_KR4", 5370 "AN_RETRY_COUNT", 5371 "AN_TYPE_SW", 5372 "BAM_20G_CR1", 5373 "BAM_20G_CR2", 5374 "BAM_20G_KR1", 5375 "BAM_20G_KR2", 5376 "BAM_25G_CR1", 5377 "BAM_25G_KR1", 5378 "BAM_40G_CR2", 5379 "BAM_40G_KR2", 5380 "BAM_50G_CR2", 5381 "BAM_50G_CR4", 5382 "BAM_50G_KR2", 5383 "BAM_50G_KR4", 5384 "BAM_HG2", 5385 "BAM_TO_HPAM_AD_EN", 5386 "BASE_100G_CR4", 5387 "BASE_100G_KR4", 5388 "BASE_10G_KR1", 5389 "BASE_1G_KX1", 5390 "BASE_40G_CR4", 5391 "BASE_40G_KR4", 5392 "BERMON_CURRENT_STATE", 5393 "BERMON_HISTORY_STATE", 5394 "BER_HO", 5395 "BER_LO", 5396 "BIP_ERROR_COUNT_0", 5397 "BIP_ERROR_COUNT_1", 5398 "BIP_ERROR_COUNT_2", 5399 "BIP_ERROR_COUNT_3", 5400 "BIP_ERROR_COUNT_4", 5401 "BLOCK_LOCK_0", 5402 "BLOCK_LOCK_1", 5403 "BLOCK_LOCK_2", 5404 "BLOCK_LOCK_3", 5405 "BLOCK_LOCK_4", 5406 "BLOCK_LOCK_LH_0", 5407 "BLOCK_LOCK_LH_1", 5408 "BLOCK_LOCK_LH_2", 5409 "BLOCK_LOCK_LH_3", 5410 "BLOCK_LOCK_LH_4", 5411 "BLOCK_LOCK_LL_0", 5412 "BLOCK_LOCK_LL_1", 5413 "BLOCK_LOCK_LL_2", 5414 "BLOCK_LOCK_LL_3", 5415 "BLOCK_LOCK_LL_4", 5416 "BONDING", 5417 "BR_PD_EN", 5418 "BS_BTMX_MODE", 5419 "BS_BTMX_MODE_OEN", 5420 "BS_DIST_MODE", 5421 "BS_DIST_MODE_OEN", 5422 "BS_PMD_LOCK", 5423 "BS_SM_SYNC_MODE", 5424 "BS_SM_SYNC_MODE_OEN", 5425 "BS_STATUS", 5426 "BS_SYNC_EN", 5427 "BS_SYNC_EN_OEN", 5428 "BURST_ERR_STATUSH_STREAM0", 5429 "BURST_ERR_STATUSH_STREAM1", 5430 "BURST_ERR_STATUSH_STREAM2", 5431 "BURST_ERR_STATUSH_STREAM3", 5432 "BURST_ERR_STATUSH_STREAM4", 5433 "BURST_ERR_STATUSL_STREAM0", 5434 "BURST_ERR_STATUSL_STREAM1", 5435 "BURST_ERR_STATUSL_STREAM2", 5436 "BURST_ERR_STATUSL_STREAM3", 5437 "BURST_ERR_STATUSL_STREAM4", 5438 "BURST_ERR_STATUS_MODE", 5439 "BYPASS_CL49RXSM", 5440 "BYPASS_CL82RXSM", 5441 "BYTE0", 5442 "BYTE1", 5443 "CAP_CNT_MASK_EN", 5444 "CAP_DONE", 5445 "CAP_DONE_LH_LL", 5446 "CAP_FORCE_SLOWDOWN", 5447 "CAP_FORCE_SLOWDOWN_EN", 5448 "CAP_PASS", 5449 "CAP_PASS_LH_LL", 5450 "CAP_RESTART", 5451 "CAP_RETRY_EN", 5452 "CAP_SELECT", 5453 "CAP_SELECT_M", 5454 "CAP_SELECT_M_EN", 5455 "CAP_SEQ_CYA", 5456 "CDR_1G_FORCE_EN", 5457 "CDR_1G_MANUAL_MODE", 5458 "CDR_1G_MANUAL_STROBE", 5459 "CDR_1G_PHASE_POINTER", 5460 "CDR_1G_SWAP_PZ", 5461 "CDR_1G_TRNSUM_EN", 5462 "CDR_BWSEL_INTEG_ACQCDR", 5463 "CDR_BWSEL_INTEG_EEE_ACQCDR", 5464 "CDR_BWSEL_INTEG_NORM", 5465 "CDR_BWSEL_PROP_ACQCDR", 5466 "CDR_BWSEL_PROP_EEE_ACQCDR", 5467 "CDR_BWSEL_PROP_NORM", 5468 "CDR_FREQ_EN", 5469 "CDR_FREQ_OVERRIDE_EN", 5470 "CDR_FREQ_OVERRIDE_VAL", 5471 "CDR_FRZ_FRC", 5472 "CDR_FRZ_FRC_VAL", 5473 "CDR_INTEG_REG", 5474 "CDR_INTEG_REG_CLR", 5475 "CDR_INTEG_SAT_SEL", 5476 "CDR_LM_OUTOFLOCK", 5477 "CDR_LM_THR_SEL", 5478 "CDR_PHASE_ERROR", 5479 "CDR_PHASE_ERR_FRZ", 5480 "CDR_SETTLE_TIMEOUT", 5481 "CDR_VCO_REG", 5482 "CDR_ZERO_POLARITY", 5483 "CL36RX_BER_COUNT_PER_LN", 5484 "CL36RX_BER_EN", 5485 "CL36RX_DISABLE_CARRIER_EXTEND", 5486 "CL36RX_EN", 5487 "CL36RX_EN_OEN", 5488 "CL36RX_FORCE_COMMA_ALIGN_ENABLE", 5489 "CL36RX_LPI_EN", 5490 "CL36RX_SYNCACQ_HIS_STATE_PER_LN", 5491 "CL36RX_SYNCACQ_STATE_CODED_PER_LN", 5492 "CL36TX_CATCH_ALL_8B10B_DIS", 5493 "CL36TX_EN", 5494 "CL36TX_EN_OEN", 5495 "CL36TX_LPI_EN", 5496 "CL49_BER_COUNT", 5497 "CL49_BER_LIMIT", 5498 "CL49_BYPASS_TXSM", 5499 "CL49_LTXSM_STATE", 5500 "CL49_RXSM_CURRENT_STATE", 5501 "CL49_RXSM_HISTORY_STATE", 5502 "CL49_RX_LF_ENABLE", 5503 "CL49_RX_LI_ENABLE", 5504 "CL49_RX_RF_ENABLE", 5505 "CL49_R_TYPE_CODED", 5506 "CL49_TXSM_STATE", 5507 "CL49_TX_FAULT_DET", 5508 "CL49_TX_LF_ENABLE", 5509 "CL49_TX_LI_ENABLE", 5510 "CL49_TX_RF_ENABLE", 5511 "CL49_TX_TL_MODE", 5512 "CL49_T_TYPE_CODED", 5513 "CL72_EN", 5514 "CL72_EN_OEN", 5515 "CL72_TIMER_EN", 5516 "CL73_AN_COMPLETE", 5517 "CL73_AN_RESTART", 5518 "CL73_BAM_CODE", 5519 "CL73_BAM_ENABLE", 5520 "CL73_BASE_SELECTOR", 5521 "CL73_BREAK_TIMER_PERIOD", 5522 "CL73_ENABLE", 5523 "CL73_ERROR_TIMER_PERIOD", 5524 "CL73_FIFO_FULL", 5525 "CL73_HPAM_ENABLE", 5526 "CL73_NONCE_MATCH_OVER", 5527 "CL73_NONCE_MATCH_VAL", 5528 "CL73_PAGE_TEST_MAX_TIMER", 5529 "CL73_PAGE_TEST_MIN_TIMER", 5530 "CL73_PAUSE", 5531 "CL73_REMOTE_FAULT", 5532 "CL73_VCO", 5533 "CL82_BER_LIMIT", 5534 "CL82_BYPASS_TXSM", 5535 "CL82_DSWIN", 5536 "CL82_DSWIN_100G", 5537 "CL82_DSWIN_100G_CL91", 5538 "CL82_IDLE_DELETION_UNDERFLOW", 5539 "CL82_RX_LF_ENABLE", 5540 "CL82_RX_LI_ENABLE", 5541 "CL82_RX_RF_ENABLE", 5542 "CL82_TX_LF_ENABLE", 5543 "CL82_TX_LI_ENABLE", 5544 "CL82_TX_RF_ENABLE", 5545 "CL91_AMPS_LOCK_LH", 5546 "CL91_AMPS_LOCK_LIVE", 5547 "CL91_AMPS_LOCK_LL", 5548 "CL91_AM_SPACING_1024", 5549 "CL91_FEC_ALGN_FSM_LATCHED_STATE", 5550 "CL91_FEC_ALGN_FSM_LIVE_STATE", 5551 "CL91_FEC_CORR_BIT_CNTR_LOWER", 5552 "CL91_FEC_CORR_BIT_CNTR_UPPER", 5553 "CL91_FEC_CORR_CW_CNTR_LOWER", 5554 "CL91_FEC_CORR_CW_CNTR_UPPER", 5555 "CL91_FEC_LANE_MAP", 5556 "CL91_FEC_LANE_MAP_VALID", 5557 "CL91_FEC_SYNC_FSM_LATCHED_STATE", 5558 "CL91_FEC_SYNC_FSM_LIVE_STATE", 5559 "CL91_FEC_UNCORR_CW_CNTR_LOWER", 5560 "CL91_FEC_UNCORR_CW_CNTR_UPPER", 5561 "CL93N72_BAD_MARKER_CNT", 5562 "CL93N72_BRK_RING_OSC", 5563 "CL93N72_CL93PRBSSEED_ORDER", 5564 "CL93N72_CL93PRBSSEED_RANDOM", 5565 "CL93N72_CTRL_FRAME_DLY", 5566 "CL93N72_DIS_MAX_WAIT_TIMER", 5567 "CL93N72_DME_CELL_BOUNDARY_CHK", 5568 "CL93N72_FRAME_CONSISTENCY_CHK_EN", 5569 "CL93N72_FRAME_LOCK", 5570 "CL93N72_GOOD_MARKER_CNT", 5571 "CL93N72_IEEE_FRAME_LOCK", 5572 "CL93N72_IEEE_LD_COEFF_UPDATE", 5573 "CL93N72_IEEE_LD_STATUS_REPORT", 5574 "CL93N72_IEEE_LP_COEFF_UPDATE", 5575 "CL93N72_IEEE_LP_STATUS_REPORT", 5576 "CL93N72_IEEE_RECEIVER_STATUS", 5577 "CL93N72_IEEE_RESTART_TRAINING", 5578 "CL93N72_IEEE_TRAINING_ENABLE", 5579 "CL93N72_IEEE_TRAINING_FAILURE", 5580 "CL93N72_IEEE_TRAINING_STATUS", 5581 "CL93N72_LD_XMT_STATUS_PAGE", 5582 "CL93N72_LOCAL_RX_READY", 5583 "CL93N72_MICRO_FRAME_LOCK_INT_EN", 5584 "CL93N72_MICRO_FRAME_LOCK_LSTATUS", 5585 "CL93N72_MICRO_STATUS_CHG_INT_EN", 5586 "CL93N72_MICRO_STATUS_CHG_LSTATUS", 5587 "CL93N72_MICRO_UPDATE_CHG_INT_EN", 5588 "CL93N72_MICRO_UPDATE_CHG_LSTATUS", 5589 "CL93N72_PPM_OFFSET_EN", 5590 "CL93N72_PRBS_SEL", 5591 "CL93N72_RX_DP_LN_CLK_EN", 5592 "CL93N72_RX_SIGNAL_OK", 5593 "CL93N72_RX_TRAINING_EN", 5594 "CL93N72_STRICT_DME_CHK", 5595 "CL93N72_STRICT_MARKER_CHK", 5596 "CL93N72_SW_FRAME_LOCK", 5597 "CL93N72_SW_REMOTE_RX_READY", 5598 "CL93N72_SW_RX_TRAINED", 5599 "CL93N72_TRAINING_FSM_SIGNAL_DETECT", 5600 "CL93N72_TR_COARSE_LOCK", 5601 "CL93N72_TXFIR_MAIN", 5602 "CL93N72_TXFIR_POST", 5603 "CL93N72_TXFIR_PRE", 5604 "CL93N72_TX_DP_LN_CLK_EN", 5605 "CL93N72_XMT_UPDATE_PAGE", 5606 "CLAUSE22", 5607 "CLK_TRANS_MISS", 5608 "CLOCKCNT0", 5609 "CLOCKCNT0_OEN", 5610 "CLOCKCNT1", 5611 "CLOCKCNT1_OEN", 5612 "CLR_CRCCNT", 5613 "CLR_RXCNT", 5614 "CLR_TXCNT", 5615 "COMPLETE_ACK", 5616 "CONSISTENCY_MISMATCH", 5617 "CORCOUNTH_STREAM0", 5618 "CORCOUNTH_STREAM1", 5619 "CORCOUNTH_STREAM2", 5620 "CORCOUNTH_STREAM3", 5621 "CORCOUNTH_STREAM4", 5622 "CORCOUNTL_STREAM0", 5623 "CORCOUNTL_STREAM1", 5624 "CORCOUNTL_STREAM2", 5625 "CORCOUNTL_STREAM3", 5626 "CORCOUNTL_STREAM4", 5627 "CORE_DP_H_RSTB", 5628 "CORE_DP_H_RSTB_OEN", 5629 "CORE_DP_RESET_STATE", 5630 "CORE_DP_S_RSTB", 5631 "CORE_MODE", 5632 "CORE_MODE_OEN", 5633 "CORE_MULTICAST_MASK_CONTROL", 5634 "CORE_REG_RESET_OCCURRED", 5635 "CORE_S_RSTB", 5636 "CORRUPT_ECC_DESKEW_MEM_0", 5637 "CORRUPT_ECC_DESKEW_MEM_1", 5638 "CORRUPT_ECC_DESKEW_MEM_2", 5639 "CORRUPT_ECC_DESKEW_MEM_3", 5640 "CORRUPT_ECC_FEC_MEM_0", 5641 "CORRUPT_ECC_FEC_MEM_1", 5642 "CORRUPT_ECC_FEC_MEM_2", 5643 "CORRUPT_ECC_FEC_MEM_3", 5644 "CRCERRCNT", 5645 "CREDITENABLE", 5646 "CREDITENABLE_OEN", 5647 "CREDIT_EN", 5648 "CURRENT_RXSM_STATE", 5649 "DATA_THRESH_SEL_VAL", 5650 "DATA_THRESH_WRITE", 5651 "DBG_CAP_STATE_ONE_HOT", 5652 "DBG_ENABLE_PER_STREAM", 5653 "DBG_ERRH_STREAM0", 5654 "DBG_ERRH_STREAM1", 5655 "DBG_ERRH_STREAM2", 5656 "DBG_ERRH_STREAM3", 5657 "DBG_ERRH_STREAM4", 5658 "DBG_ERRL_STREAM0", 5659 "DBG_ERRL_STREAM1", 5660 "DBG_ERRL_STREAM2", 5661 "DBG_ERRL_STREAM3", 5662 "DBG_ERRL_STREAM4", 5663 "DBG_ERR_MODE", 5664 "DBG_FDBCK", 5665 "DBG_MASK_DIG_LPBK_EN", 5666 "DBG_PLL_STATE_ONE_HOT", 5667 "DBG_SLOWDN", 5668 "DBG_SLOWDN_CHANGE", 5669 "DC_OFFSET_BIN", 5670 "DC_OFFS_ACC_CLR", 5671 "DC_OFFS_EN", 5672 "DC_OFFS_GAIN", 5673 "DC_OFFS_GRADIENT_INVERT", 5674 "DC_OFFS_HYS_EN", 5675 "DC_OFFS_HYS_MAG", 5676 "DC_OFFS_WRITE_EN", 5677 "DC_OFFS_WRITE_FRC_EN", 5678 "DC_OFFS_WRITE_VAL", 5679 "DEC_17B_BURST_GAP_COUNT", 5680 "DEC_18B_BURST_GAP_COUNT", 5681 "DEC_19B_BURST_GAP_COUNT", 5682 "DEC_FSM_MODE", 5683 "DEC_FSM_MODE_OEN", 5684 "DEC_GAP_COUNT_MODE", 5685 "DEC_MAX_PM", 5686 "DEC_PM_MODE", 5687 "DEC_TL_MODE", 5688 "DEC_TL_MODE_OEN", 5689 "DESCR_MODE", 5690 "DESCR_MODE_OEN", 5691 "DESKEW_HIS_STATE", 5692 "DESKEW_MEM_0_1BIT_INT_EN", 5693 "DESKEW_MEM_0_1BIT_INT_STATUS", 5694 "DESKEW_MEM_0_2BIT_INT_EN", 5695 "DESKEW_MEM_0_2BIT_INT_STATUS", 5696 "DESKEW_MEM_1_1BIT_INT_EN", 5697 "DESKEW_MEM_1_1BIT_INT_STATUS", 5698 "DESKEW_MEM_1_2BIT_INT_EN", 5699 "DESKEW_MEM_1_2BIT_INT_STATUS", 5700 "DESKEW_MEM_2_1BIT_INT_EN", 5701 "DESKEW_MEM_2_1BIT_INT_STATUS", 5702 "DESKEW_MEM_2_2BIT_INT_EN", 5703 "DESKEW_MEM_2_2BIT_INT_STATUS", 5704 "DESKEW_MEM_3_1BIT_INT_EN", 5705 "DESKEW_MEM_3_1BIT_INT_STATUS", 5706 "DESKEW_MEM_3_2BIT_INT_EN", 5707 "DESKEW_MEM_3_2BIT_INT_STATUS", 5708 "DESKEW_MEM_TM", 5709 "DESKEW_MODE", 5710 "DESKEW_MODE_OEN", 5711 "DESKEW_STATE", 5712 "DESKEW_STATUS", 5713 "DESKEW_STATUS_LH", 5714 "DESKEW_STATUS_LL", 5715 "DIG_LPBK_EN", 5716 "DIG_LPBK_PD_BIAS_EN", 5717 "DIG_LPBK_PD_EARLY_IND", 5718 "DIG_LPBK_PD_LATE_IND", 5719 "DIG_LPBK_PD_MODE", 5720 "DISABLE_CL49_BERMON", 5721 "DISABLE_ECC_DESKEW_MEM_0", 5722 "DISABLE_ECC_DESKEW_MEM_1", 5723 "DISABLE_ECC_DESKEW_MEM_2", 5724 "DISABLE_ECC_DESKEW_MEM_3", 5725 "DISABLE_ECC_FEC_MEM_0", 5726 "DISABLE_ECC_FEC_MEM_1", 5727 "DISABLE_ECC_FEC_MEM_2", 5728 "DISABLE_ECC_FEC_MEM_3", 5729 "DISABLE_REMOTE_FAULT", 5730 "DIS_CL82_BERMON", 5731 "DME_LOCKED", 5732 "DME_MV_PAIR", 5733 "DME_PAGE", 5734 "DME_STATE", 5735 "DP_RESET_TX_DISABLE_DIS", 5736 "DSC_CLR_FRC", 5737 "DSC_CLR_FRC_VAL", 5738 "DSC_SM_GP_UC_REQ", 5739 "DSC_SM_READY_FOR_CMD", 5740 "DSC_SM_SCRATCH", 5741 "DSC_STATE", 5742 "DSC_STATE_EEE_ONE_HOT", 5743 "DSC_STATE_ONE_HOT", 5744 "DTE_XS", 5745 "EEE_ACQ_CDR_TIMEOUT", 5746 "EEE_ANA_PWR_TIMEOUT", 5747 "EEE_CDR_SETTLE_TIMEOUT", 5748 "EEE_HW_TUNE_TIMEOUT", 5749 "EEE_LFSR_CNT", 5750 "EEE_MEASURE_CNT", 5751 "EEE_MEASURE_EN", 5752 "EEE_MODE_EN", 5753 "EEE_PHASE_ERR_OFFSET", 5754 "EEE_PHASE_ERR_OFFSET_EN", 5755 "EEE_QUIET_FROM_EEE_STATES", 5756 "EEE_QUIET_RX_AFE_PWRDWN_VAL", 5757 "ENABLE_TX_LANE", 5758 "ENERGY_DETECT", 5759 "ENERGY_DETECT_CHANGE", 5760 "ENERGY_DETECT_FRC", 5761 "ENERGY_DETECT_FRC_VAL", 5762 "ENERGY_DETECT_MASK_COUNT", 5763 "ERRGEN_EN_PH0", 5764 "ERRGEN_EN_PH1", 5765 "ERRGEN_EN_PH2", 5766 "ERRGEN_EN_PH3", 5767 "ERRORED_BLOCKS_HO", 5768 "ERRORED_BLOCKS_HO_PRESENT", 5769 "ERROR_EN_OVR_PER_STREAM", 5770 "ERROR_EN_OVR_VAL_PER_STREAM", 5771 "ERROR_MASK_15_0", 5772 "ERROR_MASK_31_16", 5773 "ERROR_MASK_47_32", 5774 "ERROR_MASK_63_48", 5775 "ERROR_MASK_65_64", 5776 "ERROR_STATE", 5777 "ERR_EVENT_ADDRESS_DESKEW_0", 5778 "ERR_EVENT_ADDRESS_DESKEW_1", 5779 "ERR_EVENT_ADDRESS_DESKEW_2", 5780 "ERR_EVENT_ADDRESS_DESKEW_3", 5781 "ERR_EVENT_ADDRESS_FEC_0", 5782 "ERR_EVENT_ADDRESS_FEC_1", 5783 "ERR_EVENT_ADDRESS_FEC_2", 5784 "ERR_EVENT_ADDRESS_FEC_3", 5785 "EXT_LOS_EN", 5786 "EXT_LOS_INV", 5787 "FAST_SEARCH_MODE", 5788 "FEC_ALIGN_STATUS_LH", 5789 "FEC_ALIGN_STATUS_LIVE", 5790 "FEC_ALIGN_STATUS_LL", 5791 "FEC_BYP_CORR_ABILITY", 5792 "FEC_BYP_CORR_EN", 5793 "FEC_BYP_IND_ABILITY", 5794 "FEC_BYP_IND_EN", 5795 "FEC_DBG_BYP_CORR", 5796 "FEC_ENABLE", 5797 "FEC_ERROR_CODE_ALL_PER_STREAM", 5798 "FEC_ERR_ENABLE_PER_STREAM", 5799 "FEC_MEM_0_1BIT_INT_EN", 5800 "FEC_MEM_0_1BIT_INT_STATUS", 5801 "FEC_MEM_0_2BIT_INT_EN", 5802 "FEC_MEM_0_2BIT_INT_STATUS", 5803 "FEC_MEM_1_1BIT_INT_EN", 5804 "FEC_MEM_1_1BIT_INT_STATUS", 5805 "FEC_MEM_1_2BIT_INT_EN", 5806 "FEC_MEM_1_2BIT_INT_STATUS", 5807 "FEC_MEM_2_1BIT_INT_EN", 5808 "FEC_MEM_2_1BIT_INT_STATUS", 5809 "FEC_MEM_2_2BIT_INT_EN", 5810 "FEC_MEM_2_2BIT_INT_STATUS", 5811 "FEC_MEM_3_1BIT_INT_EN", 5812 "FEC_MEM_3_1BIT_INT_STATUS", 5813 "FEC_MEM_3_2BIT_INT_EN", 5814 "FEC_MEM_3_2BIT_INT_STATUS", 5815 "FEC_MEM_TM", 5816 "FEC_REQ", 5817 "FEC_SYMBOL_ERROR_COUNTER_LOWER", 5818 "FEC_SYMBOL_ERROR_COUNTER_UPPER", 5819 "FIVE_LANE_BITMUX_DELAY", 5820 "FIVE_LANE_BITMUX_WATERMARK", 5821 "FREQ_DET_RESTART_EN", 5822 "FREQ_DET_RETRY_EN", 5823 "FREQ_DONE_SM", 5824 "FREQ_DONE_SM_LH_LL", 5825 "FREQ_MONITOR_EN", 5826 "FREQ_PASS_SM", 5827 "FREQ_PASS_SM_LH_LL", 5828 "FREQ_UPD_EN_FRC", 5829 "FREQ_UPD_EN_FRC_VAL", 5830 "GOOD_PARITY_CNT", 5831 "HEARTBEAT_COUNT_1US", 5832 "HG2_CODEC", 5833 "HG2_ENABLE", 5834 "HG2_MESSAGE_INVALID_CODE_ENABLE", 5835 "HISTORY_RXSM_STATE", 5836 "HI_BER", 5837 "HI_BER_LH", 5838 "HI_BER_LL", 5839 "HI_SER_LH", 5840 "HI_SER_LIVE", 5841 "HI_SER_LL", 5842 "HOLD_LOS_COUNT", 5843 "HOLD_SD_COUNT", 5844 "HP_MODE", 5845 "HW_TUNE_EN", 5846 "HW_TUNE_TIMEOUT", 5847 "IEEE_ERRORED_BLOCKS", 5848 "IGNORE_LINK_TIMER_PERIOD", 5849 "IGNORE_LP_MODE", 5850 "IGNORE_RX_MODE", 5851 "ILKN_SEL", 5852 "INVALID_PARITY_CNT", 5853 "INV_RX_ORDER", 5854 "INV_TX_ORDER", 5855 "IPG_SIZE", 5856 "LANE0_DEBUG_INFO", 5857 "LANE1_DEBUG_INFO", 5858 "LANE2_DEBUG_INFO", 5859 "LANE3_DEBUG_INFO", 5860 "LANE4_DEBUG_INFO", 5861 "LANE_0_AM_1_0", 5862 "LANE_0_AM_2", 5863 "LANE_1_AM_1_0", 5864 "LANE_1_AM_2", 5865 "LANE_ADDR_0", 5866 "LANE_ADDR_1", 5867 "LANE_ADDR_2", 5868 "LANE_ADDR_3", 5869 "LANE_DP_RESET_STATE", 5870 "LANE_MODE", 5871 "LANE_MODE_OEN", 5872 "LANE_MULTICAST_MASK_CONTROL", 5873 "LANE_REG_RESET_OCCURRED", 5874 "LANE_RESET_RELEASED", 5875 "LANE_RESET_RELEASED_INDEX", 5876 "LATCH_LINKDOWN_ENABLE", 5877 "LD_PAGE_0", 5878 "LD_PAGE_1", 5879 "LD_PAGE_2", 5880 "LINKFAILTIMERQUAL_EN", 5881 "LINKFAILTIMER_DIS", 5882 "LINK_FAIL_INHIBIT_TIMER_CL72_PERIOD", 5883 "LINK_FAIL_INHIBIT_TIMER_NCL72_PERIOD", 5884 "LINK_INTERRUPT", 5885 "LINK_INTERRUPT_LH", 5886 "LINK_STATUS", 5887 "LINK_STATUS_LH", 5888 "LINK_STATUS_LL", 5889 "LN_DP_H_RSTB", 5890 "LN_DP_H_RSTB_OEN", 5891 "LN_DP_S_RSTB", 5892 "LN_H_RSTB", 5893 "LN_RX_DP_S_RSTB", 5894 "LN_RX_H_PWRDN", 5895 "LN_RX_S_CLKGATE_FRC_ON", 5896 "LN_RX_S_COMCLK_FRC_ON", 5897 "LN_RX_S_COMCLK_SEL", 5898 "LN_RX_S_PWRDN", 5899 "LN_RX_S_RSTB", 5900 "LN_S_RSTB", 5901 "LN_TX_DP_S_RSTB", 5902 "LN_TX_H_PWRDN", 5903 "LN_TX_S_PWRDN", 5904 "LN_TX_S_RSTB", 5905 "LOCAL_FAULT", 5906 "LOCAL_FAULT_LH", 5907 "LOCAL_PCS_LOOPBACK_ENABLE", 5908 "LOGICAL0_TO_PHY_SEL", 5909 "LOGICAL1_TO_PHY_SEL", 5910 "LOGICAL2_TO_PHY_SEL", 5911 "LOGICAL3_TO_PHY_SEL", 5912 "LOOPCNT0", 5913 "LOOPCNT0_OEN", 5914 "LOOPCNT1", 5915 "LOOPCNT1_OEN", 5916 "LOST_PLL_LOCK_SM", 5917 "LOS_FILTER_COUNT", 5918 "LOS_THRESH", 5919 "LPI_EN", 5920 "LPI_ENABLE", 5921 "LPI_RECEIVED", 5922 "LPI_RECEIVED_LH", 5923 "LP_BASE1", 5924 "LP_BASE2", 5925 "LP_BASE3", 5926 "LP_OUI_UP1", 5927 "LP_OUI_UP2", 5928 "LP_OUI_UP3", 5929 "LP_OUI_UP4", 5930 "LP_OUI_UP5", 5931 "LP_PAGE_0", 5932 "LP_PAGE_1", 5933 "LP_PAGE_2", 5934 "LTXSM_STATE", 5935 "MAC_CREDITGENCNT", 5936 "MAC_CREDITGENCNT_OEN", 5937 "MASTER_PORT_NUM", 5938 "MAX_PRBS_BURST_ERR_LENGTH_STATUS", 5939 "MDIO_ADDR_DATA", 5940 "MDIO_AER", 5941 "MDIO_BLK_ADDR", 5942 "MDIO_BRCST_PORT_ADDR", 5943 "MDIO_DEVAD", 5944 "MDIO_DEV_AN_EN", 5945 "MDIO_DEV_CL22_EN", 5946 "MDIO_DEV_DTE_EN", 5947 "MDIO_DEV_PCS_EN", 5948 "MDIO_DEV_PHY_EN", 5949 "MDIO_DEV_PMD_EN", 5950 "MDIO_FUNCTION", 5951 "MDIO_MASKDATA", 5952 "MDIO_MULTI_MMDS_EN", 5953 "MDIO_MULTI_PRTS_EN", 5954 "MEASURE_LFSR_CNT", 5955 "MEASURE_TIMEOUT", 5956 "MEAS_INCOMPLETE", 5957 "MICRO_AUTOINC_RDADDR_EN", 5958 "MICRO_AUTOINC_WRADDR_EN", 5959 "MICRO_CODE_RAM_ECC_ADDRESS", 5960 "MICRO_CODE_RAM_TM", 5961 "MICRO_CORE_CLK_EN", 5962 "MICRO_CORE_RSTB", 5963 "MICRO_DR_LOOKTAB_EN", 5964 "MICRO_DR_SIZE", 5965 "MICRO_ECCG_MODE", 5966 "MICRO_ECC_CORRUPT", 5967 "MICRO_ECC_FRC_DISABLE", 5968 "MICRO_GEN_INTR_RMI_MBOX0WR", 5969 "MICRO_GEN_INTR_RMI_MBOX1WR", 5970 "MICRO_M0_DEFAULT_SLAVE_ERROR", 5971 "MICRO_M0_HRESP_EN", 5972 "MICRO_MASTER_CLK_EN", 5973 "MICRO_MASTER_RSTB", 5974 "MICRO_PRAMIF_AHB_WRADDR_LSW", 5975 "MICRO_PRAMIF_AHB_WRADDR_MSW", 5976 "MICRO_PRAMIF_EN", 5977 "MICRO_PRAM_IF_RSTB", 5978 "MICRO_PR_AUTOINC_NXT_WRADDR_LSW", 5979 "MICRO_PR_DEFAULT_SLAVE_ERROR", 5980 "MICRO_PVT_TEMPDATA_FRC", 5981 "MICRO_PVT_TEMPDATA_FRCVAL", 5982 "MICRO_PVT_TEMPDATA_RMI", 5983 "MICRO_RA_AUTOINC_NXT_RDADDR_LSW", 5984 "MICRO_RA_AUTOINC_NXT_WRADDR_LSW", 5985 "MICRO_RA_ECC_RDDATA", 5986 "MICRO_RA_ECC_WRDATA", 5987 "MICRO_RA_INIT", 5988 "MICRO_RA_INITDONE", 5989 "MICRO_RA_RDADDR_LSW", 5990 "MICRO_RA_RDADDR_MSW", 5991 "MICRO_RA_RDDATASIZE", 5992 "MICRO_RA_RDDATA_LSW", 5993 "MICRO_RA_RDDATA_MSW", 5994 "MICRO_RA_WRADDR_LSW", 5995 "MICRO_RA_WRADDR_MSW", 5996 "MICRO_RA_WRDATASIZE", 5997 "MICRO_RA_WRDATA_LSW", 5998 "MICRO_RA_WRDATA_MSW", 5999 "MICRO_RMI_DEFAULT_SLAVE_ERROR", 6000 "MICRO_RMI_ECC_CORR_ERR_INTR_EN", 6001 "MICRO_RMI_ECC_CORR_ERR_STATUS", 6002 "MICRO_RMI_ECC_MULTIROW_ERR_INTR_EN", 6003 "MICRO_RMI_ECC_MULTIROW_ERR_STATUS", 6004 "MICRO_RMI_ECC_UNCORR_ERR_INTR_EN", 6005 "MICRO_RMI_ECC_UNCORR_ERR_STATUS", 6006 "MICRO_RMI_M0_LOCKUP_INTR_EN", 6007 "MICRO_RMI_M0_LOCKUP_STATUS", 6008 "MICRO_RMI_M0_SYSTEMRESETREQ_INTR_EN", 6009 "MICRO_RMI_M0_SYSTEMRESETREQ_STATUS", 6010 "MICRO_RMI_MBOX_MSGOUT_INTR_EN", 6011 "MICRO_RMI_MBOX_MSGOUT_STATUS", 6012 "MICRO_RMI_MBOX_SEND_MSGIN", 6013 "MICRO_RMI_TO_MICRO_MBOX0", 6014 "MICRO_RMI_TO_MICRO_MBOX1", 6015 "MICRO_SW_PMI_HP_EXT_RSTB", 6016 "MICRO_SW_PMI_HP_RSTB", 6017 "MICRO_TO_RMI_MBOX0", 6018 "MICRO_TO_RMI_MBOX1", 6019 "MICRO_TX_DISABLE", 6020 "MLD_SWAP_COUNT", 6021 "MODEL_NUMBER", 6022 "MULTIPRTS_EN", 6023 "NEXT_PAGE", 6024 "NEXT_PAGE_WAIT", 6025 "NUMBER_PKT", 6026 "NUM_ADVERTISED_LANES", 6027 "NUM_LANES", 6028 "NUM_LANES_OEN", 6029 "NUM_LANES_OVERRIDE_VALUE", 6030 "ONE_BIT_ERR_EVENT_DESKEW_0", 6031 "ONE_BIT_ERR_EVENT_DESKEW_1", 6032 "ONE_BIT_ERR_EVENT_DESKEW_2", 6033 "ONE_BIT_ERR_EVENT_DESKEW_3", 6034 "ONE_BIT_ERR_EVENT_FEC_0", 6035 "ONE_BIT_ERR_EVENT_FEC_1", 6036 "ONE_BIT_ERR_EVENT_FEC_2", 6037 "ONE_BIT_ERR_EVENT_FEC_3", 6038 "OSR_MODE", 6039 "OSR_MODE_FRC", 6040 "OSR_MODE_FRC_VAL", 6041 "OSR_MODE_OEN", 6042 "OSR_MODE_PIN", 6043 "OS_ALL_EDGES", 6044 "OS_MODE", 6045 "OS_MODE_OEN", 6046 "OS_PATTERN_ENHANCED", 6047 "OUI_LOWER_DATA", 6048 "OUI_UPPER_DATA", 6049 "PAGE_TOO_LONG", 6050 "PAGE_TOO_SHORT", 6051 "PATT_GEN_EN", 6052 "PATT_GEN_SEQ_0", 6053 "PATT_GEN_SEQ_1", 6054 "PATT_GEN_SEQ_10", 6055 "PATT_GEN_SEQ_11", 6056 "PATT_GEN_SEQ_12", 6057 "PATT_GEN_SEQ_13", 6058 "PATT_GEN_SEQ_14", 6059 "PATT_GEN_SEQ_2", 6060 "PATT_GEN_SEQ_3", 6061 "PATT_GEN_SEQ_4", 6062 "PATT_GEN_SEQ_5", 6063 "PATT_GEN_SEQ_6", 6064 "PATT_GEN_SEQ_7", 6065 "PATT_GEN_SEQ_8", 6066 "PATT_GEN_SEQ_9", 6067 "PATT_GEN_START_POS", 6068 "PATT_GEN_STOP_POS", 6069 "PAYLOAD_TYPE", 6070 "PCS_XS", 6071 "PD_COMPLETED", 6072 "PD_DME_LOCK_TIMER_PERIOD", 6073 "PD_IN_PROGRESS", 6074 "PD_KX_EN", 6075 "PD_SD_TIMER_PERIOD", 6076 "PHASE_ERR_OFFSET", 6077 "PHASE_ERR_OFFSET_EN", 6078 "PHS_SUM_IGNORE_DSC_LOCK", 6079 "PHY_XS", 6080 "PIPELINE_RESET_COUNT", 6081 "PKTGEN_EN", 6082 "PKT_SIZE", 6083 "PLL_FORCE_CAP_DONE", 6084 "PLL_FORCE_CAP_DONE_EN", 6085 "PLL_FORCE_CAP_PASS", 6086 "PLL_FORCE_CAP_PASS_EN", 6087 "PLL_FORCE_FDONE", 6088 "PLL_FORCE_FDONE_EN", 6089 "PLL_FORCE_FPASS", 6090 "PLL_LOCK", 6091 "PLL_LOCK_FRC", 6092 "PLL_LOCK_FRC_VAL", 6093 "PLL_LOCK_LH_LL", 6094 "PLL_LOCK_OVRD", 6095 "PLL_LOCK_STS", 6096 "PLL_LOCK_TIMED_OUT", 6097 "PLL_LOCK_TIMER_PERIOD", 6098 "PLL_MODE", 6099 "PLL_RESET_EN", 6100 "PLL_SEQ_DONE", 6101 "PLL_SEQ_DONE_LH_LL", 6102 "PLL_SEQ_PASS", 6103 "PLL_SEQ_PASS_LH_LL", 6104 "PLL_SEQ_START", 6105 "PMA_PMD", 6106 "PMD_CORE_DP_H_RSTB_PKILL", 6107 "PMD_CORE_MODE", 6108 "PMD_LANE_MODE", 6109 "PMD_LN_DP_H_RSTB_PKILL", 6110 "PMD_LN_H_RSTB_PKILL", 6111 "PMD_LN_RX_H_PWRDN_PKILL", 6112 "PMD_LN_TX_H_PWRDN_PKILL", 6113 "PMD_LOCK_TIMED_OUT", 6114 "PMD_LOCK_TIMER_PERIOD", 6115 "PMD_MDIO_TRANS_PKILL", 6116 "PMD_RX_CLK_VLD_FRC", 6117 "PMD_RX_CLK_VLD_FRC_VAL", 6118 "PMD_RX_LOCK", 6119 "PMD_RX_LOCK_CHANGE", 6120 "PMD_TX_CLK_VLD_FRC", 6121 "PMD_TX_CLK_VLD_FRC_VAL", 6122 "PMD_TX_DISABLE_PIN_DIS", 6123 "PORT_MODE_SEL", 6124 "POR_H_RSTB", 6125 "PRBS_BURST_ERR_LENGTH_STATUS", 6126 "PRBS_BURST_LEN_CHK_EN", 6127 "PRBS_CHK_CLK_EN_FRC_ON", 6128 "PRBS_CHK_EN", 6129 "PRBS_CHK_EN_AUTO_MODE", 6130 "PRBS_CHK_EN_TIMEOUT", 6131 "PRBS_CHK_EN_TIMER_MODE", 6132 "PRBS_CHK_ERR_CNT_BURST_MODE", 6133 "PRBS_CHK_ERR_CNT_LSB", 6134 "PRBS_CHK_ERR_CNT_MSB", 6135 "PRBS_CHK_INV", 6136 "PRBS_CHK_LOCK", 6137 "PRBS_CHK_LOCK_CNT", 6138 "PRBS_CHK_LOCK_LOST_LH", 6139 "PRBS_CHK_MODE", 6140 "PRBS_CHK_MODE_SEL", 6141 "PRBS_CHK_OOL_CNT", 6142 "PRBS_GEN_EN", 6143 "PRBS_GEN_ERR_INS", 6144 "PRBS_GEN_INV", 6145 "PRBS_GEN_MODE_SEL", 6146 "PRESET_DSC_AFE_BANK", 6147 "PRESET_DSC_A_BANK", 6148 "PRESET_DSC_C_BANK", 6149 "PRESET_DSC_D_BANK", 6150 "PRE_FREQ_DET_TIME", 6151 "PRTAD_BCST", 6152 "PRTP_DATA_PATTERN_SEL", 6153 "PRTP_ERR_COUNT", 6154 "PRTP_LOCK", 6155 "PSLL0_TO_VL_MAPPING", 6156 "PSLL1_TO_VL_MAPPING", 6157 "PSLL2_TO_VL_MAPPING", 6158 "PSLL3_TO_VL_MAPPING", 6159 "PSLL4_TO_VL_MAPPING", 6160 "PULSE_TOO_LONG", 6161 "PULSE_TOO_MODERATE", 6162 "PULSE_TOO_SHORT", 6163 "PWRDN_SEQ_TIMER", 6164 "REFCLK_DIVCNT", 6165 "REFCLK_DIVCNT_SEL", 6166 "REFCLK_SEL", 6167 "REGID1", 6168 "REGID2", 6169 "REMOTE_FAULT", 6170 "REMOTE_FAULT_LH", 6171 "REMOTE_FAULT_SET", 6172 "REMOTE_PCS_LOOPBACK_ENABLE", 6173 "RESCAL_FRC", 6174 "RESCAL_FRC_VAL", 6175 "RESCAL_IN", 6176 "RESOLUTION_ERROR", 6177 "RESOLVED_PORT_MODE", 6178 "RESTART_LOCK_LH", 6179 "RESTART_LOCK_LIVE", 6180 "RESTART_LOCK_LL", 6181 "RESTART_PI_EXT_MODE", 6182 "RESTART_PMD_RESTART", 6183 "RESTART_SIGDET", 6184 "RES_CAL_CNTR", 6185 "RETRY_TIME", 6186 "REVID2", 6187 "REVID_BONDING", 6188 "REVID_CL72", 6189 "REVID_EEE", 6190 "REVID_LLP", 6191 "REVID_MDIO", 6192 "REVID_MICRO", 6193 "REVID_MODEL", 6194 "REVID_MULTIPLICITY", 6195 "REVID_PIR", 6196 "REVID_PROCESS", 6197 "REVID_REV_LETTER", 6198 "REVID_REV_NUMBER", 6199 "REV_LETTER", 6200 "REV_NUMBER", 6201 "RMT_LPBK_EN", 6202 "RMT_LPBK_PD_EARLY_IND", 6203 "RMT_LPBK_PD_FRC_ON", 6204 "RMT_LPBK_PD_LATE_IND", 6205 "RMT_LPBK_PD_MODE", 6206 "RSTB_LANE", 6207 "RSTB_TX_LANE", 6208 "RST_SEQ_DIS_FLT_MODE", 6209 "RST_SEQ_TIMER", 6210 "RXA_DFE_TAP10", 6211 "RXA_DFE_TAP10_MUX", 6212 "RXA_DFE_TAP11", 6213 "RXA_DFE_TAP11_MUX", 6214 "RXA_DFE_TAP12", 6215 "RXA_DFE_TAP12_MUX", 6216 "RXA_DFE_TAP13", 6217 "RXA_DFE_TAP13_MUX", 6218 "RXA_DFE_TAP14", 6219 "RXA_DFE_TAP14_MUX", 6220 "RXA_DFE_TAP2", 6221 "RXA_DFE_TAP3", 6222 "RXA_DFE_TAP4", 6223 "RXA_DFE_TAP5", 6224 "RXA_DFE_TAP6", 6225 "RXA_DFE_TAP7", 6226 "RXA_DFE_TAP7_MUX", 6227 "RXA_DFE_TAP8", 6228 "RXA_DFE_TAP8_MUX", 6229 "RXA_DFE_TAP9", 6230 "RXA_DFE_TAP9_MUX", 6231 "RXA_SLICER_OFFSET_ADJ_DN", 6232 "RXA_SLICER_OFFSET_ADJ_DP", 6233 "RXA_SLICER_OFFSET_ADJ_LMS", 6234 "RXA_SLICER_OFFSET_ADJ_ZN", 6235 "RXA_SLICER_OFFSET_ADJ_ZP", 6236 "RXB_DFE_TAP10", 6237 "RXB_DFE_TAP10_MUX", 6238 "RXB_DFE_TAP11", 6239 "RXB_DFE_TAP11_MUX", 6240 "RXB_DFE_TAP12", 6241 "RXB_DFE_TAP12_MUX", 6242 "RXB_DFE_TAP13", 6243 "RXB_DFE_TAP13_MUX", 6244 "RXB_DFE_TAP14", 6245 "RXB_DFE_TAP14_MUX", 6246 "RXB_DFE_TAP2", 6247 "RXB_DFE_TAP3", 6248 "RXB_DFE_TAP4", 6249 "RXB_DFE_TAP5", 6250 "RXB_DFE_TAP6", 6251 "RXB_DFE_TAP7", 6252 "RXB_DFE_TAP7_MUX", 6253 "RXB_DFE_TAP8", 6254 "RXB_DFE_TAP8_MUX", 6255 "RXB_DFE_TAP9", 6256 "RXB_DFE_TAP9_MUX", 6257 "RXB_SLICER_OFFSET_ADJ_DN", 6258 "RXB_SLICER_OFFSET_ADJ_DP", 6259 "RXB_SLICER_OFFSET_ADJ_LMS", 6260 "RXB_SLICER_OFFSET_ADJ_ZN", 6261 "RXB_SLICER_OFFSET_ADJ_ZP", 6262 "RXC_DFE_TAP10", 6263 "RXC_DFE_TAP10_MUX", 6264 "RXC_DFE_TAP11", 6265 "RXC_DFE_TAP11_MUX", 6266 "RXC_DFE_TAP12", 6267 "RXC_DFE_TAP12_MUX", 6268 "RXC_DFE_TAP13", 6269 "RXC_DFE_TAP13_MUX", 6270 "RXC_DFE_TAP14", 6271 "RXC_DFE_TAP14_MUX", 6272 "RXC_DFE_TAP2", 6273 "RXC_DFE_TAP3", 6274 "RXC_DFE_TAP4", 6275 "RXC_DFE_TAP5", 6276 "RXC_DFE_TAP6", 6277 "RXC_DFE_TAP7", 6278 "RXC_DFE_TAP7_MUX", 6279 "RXC_DFE_TAP8", 6280 "RXC_DFE_TAP8_MUX", 6281 "RXC_DFE_TAP9", 6282 "RXC_DFE_TAP9_MUX", 6283 "RXC_SLICER_OFFSET_ADJ_DN", 6284 "RXC_SLICER_OFFSET_ADJ_DP", 6285 "RXC_SLICER_OFFSET_ADJ_LMS", 6286 "RXC_SLICER_OFFSET_ADJ_ZN", 6287 "RXC_SLICER_OFFSET_ADJ_ZP", 6288 "RXD_DFE_TAP10", 6289 "RXD_DFE_TAP10_MUX", 6290 "RXD_DFE_TAP11", 6291 "RXD_DFE_TAP11_MUX", 6292 "RXD_DFE_TAP12", 6293 "RXD_DFE_TAP12_MUX", 6294 "RXD_DFE_TAP13", 6295 "RXD_DFE_TAP13_MUX", 6296 "RXD_DFE_TAP14", 6297 "RXD_DFE_TAP14_MUX", 6298 "RXD_DFE_TAP2", 6299 "RXD_DFE_TAP3", 6300 "RXD_DFE_TAP4", 6301 "RXD_DFE_TAP5", 6302 "RXD_DFE_TAP6", 6303 "RXD_DFE_TAP7", 6304 "RXD_DFE_TAP7_MUX", 6305 "RXD_DFE_TAP8", 6306 "RXD_DFE_TAP8_MUX", 6307 "RXD_DFE_TAP9", 6308 "RXD_DFE_TAP9_MUX", 6309 "RXD_SLICER_OFFSET_ADJ_DN", 6310 "RXD_SLICER_OFFSET_ADJ_DP", 6311 "RXD_SLICER_OFFSET_ADJ_LMS", 6312 "RXD_SLICER_OFFSET_ADJ_ZN", 6313 "RXD_SLICER_OFFSET_ADJ_ZP", 6314 "RXFIFO_EMPTY", 6315 "RXFIFO_FULL", 6316 "RXFIFO_OVERRUN", 6317 "RXFIFO_UNDERRUN", 6318 "RXPKTCNT_L", 6319 "RXPKTCNT_U", 6320 "RX_BP", 6321 "RX_CL91_FEC_EN", 6322 "RX_CLK_VLD_LH", 6323 "RX_CLK_VLD_LL", 6324 "RX_CLK_VLD_OVRD", 6325 "RX_CLK_VLD_STS", 6326 "RX_DATA_15_TO_0", 6327 "RX_DATA_35_TO_20", 6328 "RX_DATA_THRESH_SEL", 6329 "RX_DSC_LOCK", 6330 "RX_DSC_LOCK_FRC", 6331 "RX_DSC_LOCK_FRC_VAL", 6332 "RX_INVALID_SEQ", 6333 "RX_LMS_THRESH_SEL", 6334 "RX_LOCK_LH", 6335 "RX_LOCK_LL", 6336 "RX_LOCK_OVRD", 6337 "RX_LOCK_STS", 6338 "RX_MODE", 6339 "RX_MP_MISMATCH", 6340 "RX_MP_NULL", 6341 "RX_MP_OUI", 6342 "RX_MSBUS_TYPE", 6343 "RX_NP", 6344 "RX_NP_TOGGLE_ERR", 6345 "RX_PF2_CTRL", 6346 "RX_PF_CTRL", 6347 "RX_PHASE_THRESH_SEL", 6348 "RX_PI_CNT_BIN_D", 6349 "RX_PI_CNT_BIN_DQ", 6350 "RX_PI_CNT_BIN_D_LD", 6351 "RX_PI_CNT_BIN_D_PD", 6352 "RX_PI_CNT_BIN_L", 6353 "RX_PI_CNT_BIN_LQ", 6354 "RX_PI_CNT_BIN_L_LD", 6355 "RX_PI_CNT_BIN_P", 6356 "RX_PI_CNT_BIN_PQ", 6357 "RX_PI_CNT_BIN_P_PD", 6358 "RX_PI_MANUAL_MODE", 6359 "RX_PI_MANUAL_STROBE", 6360 "RX_PI_PHASE_STEP_CNT", 6361 "RX_PI_PHASE_STEP_DIR", 6362 "RX_PI_SLICERS_EN", 6363 "RX_PKT_CHECK_EN", 6364 "RX_PMD_DP_INVERT", 6365 "RX_PORT_SEL", 6366 "RX_PRTP_EN", 6367 "RX_RESTART_PMD", 6368 "RX_RESTART_PMD_HOLD", 6369 "RX_UNEXPECTED_PAGE", 6370 "RX_UP_OUI_MATCH", 6371 "RX_UP_OUI_MISMATCH", 6372 "RX_VGA_CTRL", 6373 "RX_VGA_CTRL_VAL", 6374 "R_CL91_FEC_ENABLE", 6375 "R_FEC_ENABLE", 6376 "R_HG2_ENABLE", 6377 "R_HG2_ENABLE_OEN", 6378 "R_TEST_MODE_CFG", 6379 "R_TYPE_CODED", 6380 "SCR_MODE", 6381 "SCR_MODE_OEN", 6382 "SC_BYPASS", 6383 "SC_FSM_STATUS", 6384 "SC_IGNORE_TX_DATA_VLD", 6385 "SDK_TX_DISABLE", 6386 "SEEDA0", 6387 "SEEDA1", 6388 "SEEDA2", 6389 "SEEDA3", 6390 "SEEDB0", 6391 "SEEDB1", 6392 "SEEDB2", 6393 "SEEDB3", 6394 "SET_BER_WINDOW_512", 6395 "SET_MEAS_INCOMPLETE", 6396 "SET_SYMB_ERR_WINDOW_128", 6397 "SIGDET_DP_RSTB_EN", 6398 "SIGNAL_DETECT", 6399 "SIGNAL_DETECT_CHANGE", 6400 "SIGNAL_DETECT_FILTER_1US", 6401 "SIGNAL_DETECT_FILTER_COUNT", 6402 "SIGNAL_DETECT_FRC", 6403 "SIGNAL_DETECT_FRC_VAL", 6404 "SIGNAL_DETECT_LH", 6405 "SIGNAL_DETECT_LL", 6406 "SIGNAL_DETECT_OVRD", 6407 "SIGNAL_DETECT_RAW", 6408 "SIGNAL_DETECT_RAW_CHANGE", 6409 "SIGNAL_DETECT_STS", 6410 "SIGNAL_DETECT_THRESH", 6411 "SINGLE_LANE_BITMUX_DELAY", 6412 "SINGLE_LANE_BITMUX_WATERMARK", 6413 "SINGLE_PORT_MODE", 6414 "SLOWDN_XOR", 6415 "SOFT_RST_RX", 6416 "SOFT_RST_TX", 6417 "SPARE0", 6418 "SPARE1", 6419 "SPEED", 6420 "SPEED_100G_FEC_SEL", 6421 "SPEED_FORCE", 6422 "STAND_ALONE_MODE", 6423 "SUP_RST_SEQ_FRC", 6424 "SUP_RST_SEQ_FRC_VAL", 6425 "SW_LD_PAGE_PENDING", 6426 "SW_LP_PAGE_PENDING", 6427 "SW_SPEED_CHANGE", 6428 "SW_SPEED_CHANGE_DONE", 6429 "SW_SPEED_CONFIG_VLD", 6430 "SYMBOL_ERROR_TMR_PERIOD", 6431 "SYMBOL_ERR_CNT_THRESHOLD", 6432 "SYNCE_FRACTIONAL_DIVSOR_CFG", 6433 "SYNCE_MODE_PHY_LANE0", 6434 "SYNCE_MODE_PHY_LANE1", 6435 "SYNCE_MODE_PHY_LANE2", 6436 "SYNCE_MODE_PHY_LANE3", 6437 "SYNCE_STAGE0_MODE_PHY_LANE0", 6438 "SYNCE_STAGE0_MODE_PHY_LANE1", 6439 "SYNCE_STAGE0_MODE_PHY_LANE2", 6440 "SYNCE_STAGE0_MODE_PHY_LANE3", 6441 "TC", 6442 "TDT_BIT_SEL", 6443 "TDT_CYCLE_BIN", 6444 "TDT_CYCLE_SEL", 6445 "TDT_PRBS_MODE", 6446 "TDT_PRBS_SLIP", 6447 "TDT_TRNSUM_EN", 6448 "TECH_PROC", 6449 "THRESH_STEP_SIZE", 6450 "THRESH_TIMER_T1", 6451 "TICK_DENOMINATOR", 6452 "TICK_NUMERATOR_LOWER", 6453 "TICK_NUMERATOR_UPPER", 6454 "TICK_OVERRIDE", 6455 "TIMEOUT_COUNT", 6456 "TIMEOUT_ERROR", 6457 "TIMER_DONE_FRC", 6458 "TIMER_DONE_FRC_VAL", 6459 "TLA_SEQ_FSM_STATUS", 6460 "TLB_RX_DIFF_DEC_EN", 6461 "TLB_TX_DIFF_ENC_EN", 6462 "TRANSMIT_DISABLE", 6463 "TRNSUM", 6464 "TRNSUM_A", 6465 "TRNSUM_A_LOW", 6466 "TRNSUM_B", 6467 "TRNSUM_B_LOW", 6468 "TRNSUM_C", 6469 "TRNSUM_CLR_FRC", 6470 "TRNSUM_CLR_FRC_VAL", 6471 "TRNSUM_COR_SEL", 6472 "TRNSUM_C_LOW", 6473 "TRNSUM_D", 6474 "TRNSUM_D_LOW", 6475 "TRNSUM_EDGE_PATTERN_EN", 6476 "TRNSUM_EN", 6477 "TRNSUM_ERROR_COUNT_EN", 6478 "TRNSUM_EYE_CLOSURE_EN", 6479 "TRNSUM_FRZ_FRC", 6480 "TRNSUM_FRZ_FRC_VAL", 6481 "TRNSUM_GAIN", 6482 "TRNSUM_INV_PATTERN_EN", 6483 "TRNSUM_LOW", 6484 "TRNSUM_PATTERN", 6485 "TRNSUM_PATTERN_BIT_EN", 6486 "TRNSUM_PATTERN_FULL_CHECK_OFF", 6487 "TRNSUM_QPHASE_MULT_EN", 6488 "TRNSUM_RANDOM_TAPSEL_DISABLE", 6489 "TRNSUM_SEL_EMUX", 6490 "TRNSUM_TAP_EN", 6491 "TRNSUM_TAP_RANGE_SEL", 6492 "TRNSUM_TAP_SIGN", 6493 "TSC_CLK_CTRL", 6494 "TWO_BIT_ERR_EVENT_DESKEW_0", 6495 "TWO_BIT_ERR_EVENT_DESKEW_1", 6496 "TWO_BIT_ERR_EVENT_DESKEW_2", 6497 "TWO_BIT_ERR_EVENT_DESKEW_3", 6498 "TWO_BIT_ERR_EVENT_FEC_0", 6499 "TWO_BIT_ERR_EVENT_FEC_1", 6500 "TWO_BIT_ERR_EVENT_FEC_2", 6501 "TWO_BIT_ERR_EVENT_FEC_3", 6502 "TWO_LANE_BITMUX_DELAY", 6503 "TWO_LANE_BITMUX_WATERMARK", 6504 "TXCOM_CL93N72_MAX_WAIT_TIMER_PERIOD", 6505 "TXCOM_CL93N72_WAIT_CNTR_LIMIT", 6506 "TXCOM_MAIN_TAP_ALERT_VAL", 6507 "TXCOM_POST_TAP_ALERT_VAL", 6508 "TXCOM_PRE_TAP_ALERT_VAL", 6509 "TXFIFO_EMPTY", 6510 "TXFIFO_FULL", 6511 "TXFIFO_OVERRUN", 6512 "TXFIFO_UNDERRUN", 6513 "TXFIR_MAIN_ADJUSTED", 6514 "TXFIR_MAIN_AFTER_OVR", 6515 "TXFIR_MAIN_OFFSET", 6516 "TXFIR_POST2", 6517 "TXFIR_POST2_ADJUSTED", 6518 "TXFIR_POST2_OFFSET", 6519 "TXFIR_POST3", 6520 "TXFIR_POST3_ADJUSTED", 6521 "TXFIR_POST3_OFFSET", 6522 "TXFIR_POST_ADJUSTED", 6523 "TXFIR_POST_AFTER_OVR", 6524 "TXFIR_POST_OFFSET", 6525 "TXFIR_PRE_ADJUSTED", 6526 "TXFIR_PRE_AFTER_OVR", 6527 "TXFIR_PRE_OFFSET", 6528 "TXPKTCNT_L", 6529 "TXPKTCNT_U", 6530 "TXSM_STATE", 6531 "TX_CL91_FEC_EN", 6532 "TX_CLK_VLD_OVRD", 6533 "TX_CLK_VLD_STS", 6534 "TX_DISABLE", 6535 "TX_DISABLE_OEN", 6536 "TX_DISABLE_OUTPUT_SEL", 6537 "TX_DISABLE_TIMER_CTRL", 6538 "TX_EEE_ALERT_EN", 6539 "TX_EEE_QUIET_EN", 6540 "TX_LANE_MAP_0", 6541 "TX_LANE_MAP_1", 6542 "TX_LANE_MAP_2", 6543 "TX_LANE_MAP_3", 6544 "TX_LINK_INTERRUPT", 6545 "TX_LOCAL_FAULT", 6546 "TX_LPI_RECEIVED", 6547 "TX_MODE", 6548 "TX_MSBUS_TYPE", 6549 "TX_MUX_SEL_ORDER", 6550 "TX_NONCE", 6551 "TX_PCS_NATIVE_ANA_FRMT_EN", 6552 "TX_PI_EN", 6553 "TX_PI_EXT_CTRL_EN", 6554 "TX_PI_EXT_PHASE_BWSEL_INTEG", 6555 "TX_PI_FIRST_ORDER_BWSEL_INTEG", 6556 "TX_PI_FREQ_OVERRIDE_EN", 6557 "TX_PI_FREQ_OVERRIDE_VAL", 6558 "TX_PI_FRZ_FRC", 6559 "TX_PI_FRZ_FRC_VAL", 6560 "TX_PI_FRZ_MODE", 6561 "TX_PI_INTEG1_REG", 6562 "TX_PI_INTEG2_REG", 6563 "TX_PI_JITTER_FILTER_EN", 6564 "TX_PI_JIT_AMP", 6565 "TX_PI_JIT_FREQ_IDX", 6566 "TX_PI_JIT_SSC_FREQ_MODE", 6567 "TX_PI_LOOP_FILTER_STABLE", 6568 "TX_PI_LOOP_TIMING_SRC_SEL", 6569 "TX_PI_PHASE_CNTR", 6570 "TX_PI_PHASE_ERR", 6571 "TX_PI_PHASE_INVERT", 6572 "TX_PI_PHASE_OVERRIDE", 6573 "TX_PI_PHASE_STEP_DIR", 6574 "TX_PI_PHASE_STEP_NUM", 6575 "TX_PI_PHASE_STROBE", 6576 "TX_PI_RESET_CODE_DBG", 6577 "TX_PI_RMT_LPBK_BYPASS_FLT", 6578 "TX_PI_SECOND_ORDER_BWSEL_INTEG", 6579 "TX_PI_SECOND_ORDER_LOOP_EN", 6580 "TX_PI_SJ_GEN_EN", 6581 "TX_PI_SSC_GEN_EN", 6582 "TX_PMD_DP_INVERT", 6583 "TX_PRTP_EN", 6584 "TX_REMOTE_FAULT", 6585 "TX_RESET_COUNT", 6586 "TX_S_CLKGATE_FRC_ON", 6587 "TX_S_COMCLK_FRC_ON", 6588 "TX_S_COMCLK_SEL", 6589 "TX_TEST_PORT_SEL", 6590 "T_CL91_FEC_ENABLE", 6591 "T_ENC_MODE", 6592 "T_ENC_MODE_OEN", 6593 "T_FEC_ENABLE", 6594 "T_FIFO_MODE", 6595 "T_FIFO_MODE_OEN", 6596 "T_HG2_ENABLE", 6597 "T_HG2_ENABLE_OEN", 6598 "T_PMA_40B_MODE", 6599 "T_PMA_40B_MODE_OEN", 6600 "T_PMA_BTMX_MODE", 6601 "T_PMA_BTMX_MODE_OEN", 6602 "T_PMA_OVERFLOW", 6603 "T_PMA_UNDERFLOW", 6604 "T_TYPE_CODED", 6605 "UC_ACK_CORE_CFG_DONE", 6606 "UC_ACK_CORE_DP_RESET", 6607 "UC_ACK_DSC_CONFIG", 6608 "UC_ACK_DSC_EEE_DONE", 6609 "UC_ACK_DSC_RESTART", 6610 "UC_ACK_LANE_CFG_DONE", 6611 "UC_ACK_LANE_DP_RESET", 6612 "UC_ACTIVE", 6613 "UC_DSC_ERROR_FOUND", 6614 "UC_DSC_GP_UC_REQ", 6615 "UC_DSC_READY_FOR_CMD", 6616 "UC_DSC_SCRATCH", 6617 "UC_DSC_SUPP_INFO", 6618 "UC_TRNSUM_EN", 6619 "UC_TUNE_EN", 6620 "UNCORCOUNTH_STREAM0", 6621 "UNCORCOUNTH_STREAM1", 6622 "UNCORCOUNTH_STREAM2", 6623 "UNCORCOUNTH_STREAM3", 6624 "UNCORCOUNTH_STREAM4", 6625 "UNCORCOUNTL_STREAM0", 6626 "UNCORCOUNTL_STREAM1", 6627 "UNCORCOUNTL_STREAM2", 6628 "UNCORCOUNTL_STREAM3", 6629 "UNCORCOUNTL_STREAM4", 6630 "VCO_DONE_EN", 6631 "VCO_RANGE_ADJUST", 6632 "VCO_RST_EN", 6633 "VCO_START_TIME", 6634 "VCO_STEP_TIME", 6635 "VGA_DEC", 6636 "VGA_INC", 6637 "VGA_TIMER_T2", 6638 "VGA_WRITE", 6639 "WIN_CAL_CNTR", 6640 "WIS", 6641 "WM", 6642 }; 6643 6644 #endif 6645 #endif 6646 #endif 6647 #endif /* PHYMOD_CONFIG_INCLUDE_FIELD_INFO */ 6648 6649 6650 6651 /******************************************************************************* 6652 * 6653 * The following is the symbol table itself. 6654 * It defines the entries for all registers and memories. 6655 * It also incorporates the field information for each register and memory if 6656 * applicable. 6657 */ 6658 static const phymod_symbol_t bcmi_tscf_xgxs_syms[] = { 6659 #ifndef PHYMOD_CONFIG_EXCLUDE_CHIP_SYMBOLS_BCMI_TSCF_XGXS 6660 { 6661 BCMI_TSCF_XGXS_PHYID2r, 6662 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6663 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 6664 BCMI_TSCF_XGXS_PHYID2r_fields, 6665 #else 6666 0, 6667 #endif 6668 #endif 6669 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6670 PHYMOD_SYMBOL_FLAG_REGISTER, 6671 "PHYID2r", 6672 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6673 "CL22_B0_PHYID2", 6674 NULL, 6675 #endif 6676 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6677 0x600d, /* 24589 */ 6678 0, 6679 #endif 6680 }, 6681 { 6682 BCMI_TSCF_XGXS_PHYID3r, 6683 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6684 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 6685 BCMI_TSCF_XGXS_PHYID3r_fields, 6686 #else 6687 0, 6688 #endif 6689 #endif 6690 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6691 PHYMOD_SYMBOL_FLAG_REGISTER, 6692 "PHYID3r", 6693 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6694 "CL22_B0_PHYID3", 6695 NULL, 6696 #endif 6697 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6698 0x8770, /* 34672 */ 6699 0, 6700 #endif 6701 }, 6702 { 6703 BCMI_TSCF_XGXS_MAIN0_SETUPr, 6704 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6705 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 6706 BCMI_TSCF_XGXS_MAIN0_SETUPr_fields, 6707 #else 6708 0, 6709 #endif 6710 #endif 6711 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6712 PHYMOD_SYMBOL_FLAG_REGISTER, 6713 "MAIN0_SETUPr", 6714 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6715 NULL, 6716 NULL, 6717 #endif 6718 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6719 0x180, /* 384 */ 6720 0, 6721 #endif 6722 }, 6723 { 6724 BCMI_TSCF_XGXS_MAIN0_SYNCE_CTLr, 6725 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6726 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 6727 BCMI_TSCF_XGXS_MAIN0_SYNCE_CTLr_fields, 6728 #else 6729 0, 6730 #endif 6731 #endif 6732 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6733 PHYMOD_SYMBOL_FLAG_REGISTER, 6734 "MAIN0_SYNCE_CTLr", 6735 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6736 "MAIN0_SYNCE_CONTROL", 6737 NULL, 6738 #endif 6739 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6740 0xaa, /* 170 */ 6741 0, 6742 #endif 6743 }, 6744 { 6745 BCMI_TSCF_XGXS_MAIN0_SYNCE_CTL_STAGE0r, 6746 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6747 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 6748 BCMI_TSCF_XGXS_MAIN0_SYNCE_CTL_STAGE0r_fields, 6749 #else 6750 0, 6751 #endif 6752 #endif 6753 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6754 PHYMOD_SYMBOL_FLAG_REGISTER, 6755 "MAIN0_SYNCE_CTL_STAGE0r", 6756 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6757 "MAIN0_SYNCE_CONTROL_STAGE0", 6758 NULL, 6759 #endif 6760 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6761 0x0, /* 0 */ 6762 0, 6763 #endif 6764 }, 6765 { 6766 BCMI_TSCF_XGXS_MAIN0_LN_SWPr, 6767 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6768 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 6769 BCMI_TSCF_XGXS_MAIN0_LN_SWPr_fields, 6770 #else 6771 0, 6772 #endif 6773 #endif 6774 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6775 PHYMOD_SYMBOL_FLAG_REGISTER, 6776 "MAIN0_LN_SWPr", 6777 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6778 "MAIN0_LANE_SWAP", 6779 NULL, 6780 #endif 6781 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6782 0x4e4, /* 1252 */ 6783 0, 6784 #endif 6785 }, 6786 { 6787 BCMI_TSCF_XGXS_MAIN0_DEVINPKG5r, 6788 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6789 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 6790 BCMI_TSCF_XGXS_MAIN0_DEVINPKG5r_fields, 6791 #else 6792 0, 6793 #endif 6794 #endif 6795 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6796 PHYMOD_SYMBOL_FLAG_REGISTER, 6797 "MAIN0_DEVINPKG5r", 6798 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6799 "MAIN0_DEVICEINPKG5", 6800 NULL, 6801 #endif 6802 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6803 0x83, /* 131 */ 6804 0, 6805 #endif 6806 }, 6807 { 6808 BCMI_TSCF_XGXS_MAIN0_TICK_CTL1r, 6809 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6810 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 6811 BCMI_TSCF_XGXS_MAIN0_TICK_CTL1r_fields, 6812 #else 6813 0, 6814 #endif 6815 #endif 6816 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6817 PHYMOD_SYMBOL_FLAG_REGISTER, 6818 "MAIN0_TICK_CTL1r", 6819 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6820 "MAIN0_TICK_CONTROL_1", 6821 NULL, 6822 #endif 6823 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6824 0x0, /* 0 */ 6825 0, 6826 #endif 6827 }, 6828 { 6829 BCMI_TSCF_XGXS_MAIN0_TICK_CTL0r, 6830 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6831 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 6832 BCMI_TSCF_XGXS_MAIN0_TICK_CTL0r_fields, 6833 #else 6834 0, 6835 #endif 6836 #endif 6837 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6838 PHYMOD_SYMBOL_FLAG_REGISTER, 6839 "MAIN0_TICK_CTL0r", 6840 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6841 "MAIN0_TICK_CONTROL_0", 6842 NULL, 6843 #endif 6844 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6845 0x0, /* 0 */ 6846 0, 6847 #endif 6848 }, 6849 { 6850 BCMI_TSCF_XGXS_MAIN0_LPBK_CTLr, 6851 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6852 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 6853 BCMI_TSCF_XGXS_MAIN0_LPBK_CTLr_fields, 6854 #else 6855 0, 6856 #endif 6857 #endif 6858 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6859 PHYMOD_SYMBOL_FLAG_REGISTER, 6860 "MAIN0_LPBK_CTLr", 6861 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6862 "MAIN0_LOOPBACK_CONTROL", 6863 NULL, 6864 #endif 6865 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6866 0x0, /* 0 */ 6867 0, 6868 #endif 6869 }, 6870 { 6871 BCMI_TSCF_XGXS_MAIN0_MDIO_BCSTr, 6872 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6873 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 6874 BCMI_TSCF_XGXS_MAIN0_MDIO_BCSTr_fields, 6875 #else 6876 0, 6877 #endif 6878 #endif 6879 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6880 PHYMOD_SYMBOL_FLAG_REGISTER, 6881 "MAIN0_MDIO_BCSTr", 6882 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6883 "MAIN0_MDIO_BROADCAST", 6884 NULL, 6885 #endif 6886 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6887 0xf800, /* 63488 */ 6888 0, 6889 #endif 6890 }, 6891 { 6892 BCMI_TSCF_XGXS_MAIN0ACC_TMOUTr, 6893 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6894 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 6895 BCMI_TSCF_XGXS_MAIN0ACC_TMOUTr_fields, 6896 #else 6897 0, 6898 #endif 6899 #endif 6900 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6901 PHYMOD_SYMBOL_FLAG_REGISTER, 6902 "MAIN0ACC_TMOUTr", 6903 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6904 "MAIN0_REGACCESS_TIMEOUT", 6905 NULL, 6906 #endif 6907 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6908 0x50, /* 80 */ 6909 0, 6910 #endif 6911 }, 6912 { 6913 BCMI_TSCF_XGXS_MAIN0ACC_TMOUT_STSr, 6914 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6915 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 6916 BCMI_TSCF_XGXS_MAIN0ACC_TMOUT_STSr_fields, 6917 #else 6918 0, 6919 #endif 6920 #endif 6921 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6922 PHYMOD_SYMBOL_FLAG_REGISTER, 6923 "MAIN0ACC_TMOUT_STSr", 6924 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6925 "MAIN0_REGACCESS_TIMEOUT_STATUS", 6926 NULL, 6927 #endif 6928 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6929 0x0, /* 0 */ 6930 0, 6931 #endif 6932 }, 6933 { 6934 BCMI_TSCF_XGXS_MAIN0_SERDESIDr, 6935 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6936 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 6937 BCMI_TSCF_XGXS_MAIN0_SERDESIDr_fields, 6938 #else 6939 0, 6940 #endif 6941 #endif 6942 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6943 PHYMOD_SYMBOL_FLAG_REGISTER, 6944 "MAIN0_SERDESIDr", 6945 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6946 NULL, 6947 NULL, 6948 #endif 6949 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6950 0x2d4, /* 724 */ 6951 0, 6952 #endif 6953 }, 6954 { 6955 BCMI_TSCF_XGXS_PMD_X1_CTLr, 6956 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6957 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 6958 BCMI_TSCF_XGXS_PMD_X1_CTLr_fields, 6959 #else 6960 0, 6961 #endif 6962 #endif 6963 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6964 PHYMOD_SYMBOL_FLAG_REGISTER, 6965 "PMD_X1_CTLr", 6966 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6967 "PMD_X1_CONTROL", 6968 NULL, 6969 #endif 6970 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6971 0x0, /* 0 */ 6972 0, 6973 #endif 6974 }, 6975 { 6976 BCMI_TSCF_XGXS_PMD_X1_MODEr, 6977 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6978 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 6979 BCMI_TSCF_XGXS_PMD_X1_MODEr_fields, 6980 #else 6981 0, 6982 #endif 6983 #endif 6984 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6985 PHYMOD_SYMBOL_FLAG_REGISTER, 6986 "PMD_X1_MODEr", 6987 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6988 NULL, 6989 NULL, 6990 #endif 6991 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6992 0x0, /* 0 */ 6993 0, 6994 #endif 6995 }, 6996 { 6997 BCMI_TSCF_XGXS_PMD_X1_STSr, 6998 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6999 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 7000 BCMI_TSCF_XGXS_PMD_X1_STSr_fields, 7001 #else 7002 0, 7003 #endif 7004 #endif 7005 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7006 PHYMOD_SYMBOL_FLAG_REGISTER, 7007 "PMD_X1_STSr", 7008 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7009 "PMD_X1_STATUS", 7010 NULL, 7011 #endif 7012 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7013 0x0, /* 0 */ 7014 0, 7015 #endif 7016 }, 7017 { 7018 BCMI_TSCF_XGXS_PMD_X1_OVRRr, 7019 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7020 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 7021 BCMI_TSCF_XGXS_PMD_X1_OVRRr_fields, 7022 #else 7023 0, 7024 #endif 7025 #endif 7026 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7027 PHYMOD_SYMBOL_FLAG_REGISTER, 7028 "PMD_X1_OVRRr", 7029 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7030 "PMD_X1_OVERRIDE", 7031 NULL, 7032 #endif 7033 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7034 0x0, /* 0 */ 7035 0, 7036 #endif 7037 }, 7038 { 7039 BCMI_TSCF_XGXS_PKTGEN_CTL1r, 7040 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7041 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 7042 BCMI_TSCF_XGXS_PKTGEN_CTL1r_fields, 7043 #else 7044 0, 7045 #endif 7046 #endif 7047 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7048 PHYMOD_SYMBOL_FLAG_REGISTER, 7049 "PKTGEN_CTL1r", 7050 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7051 "PKTGEN0_PKTGENCTRL1", 7052 NULL, 7053 #endif 7054 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7055 0x0, /* 0 */ 7056 0, 7057 #endif 7058 }, 7059 { 7060 BCMI_TSCF_XGXS_PKTGEN_CTL2r, 7061 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7062 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 7063 BCMI_TSCF_XGXS_PKTGEN_CTL2r_fields, 7064 #else 7065 0, 7066 #endif 7067 #endif 7068 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7069 PHYMOD_SYMBOL_FLAG_REGISTER, 7070 "PKTGEN_CTL2r", 7071 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7072 "PKTGEN0_PKTGENCTRL2", 7073 NULL, 7074 #endif 7075 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7076 0x28, /* 40 */ 7077 0, 7078 #endif 7079 }, 7080 { 7081 BCMI_TSCF_XGXS_PKTGEN_CTL3r, 7082 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7083 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 7084 BCMI_TSCF_XGXS_PKTGEN_CTL3r_fields, 7085 #else 7086 0, 7087 #endif 7088 #endif 7089 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7090 PHYMOD_SYMBOL_FLAG_REGISTER, 7091 "PKTGEN_CTL3r", 7092 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7093 "PKTGEN0_PKTGENCTRL3", 7094 NULL, 7095 #endif 7096 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7097 0x0, /* 0 */ 7098 0, 7099 #endif 7100 }, 7101 { 7102 BCMI_TSCF_XGXS_PKTGEN_PRTPCTLr, 7103 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7104 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 7105 BCMI_TSCF_XGXS_PKTGEN_PRTPCTLr_fields, 7106 #else 7107 0, 7108 #endif 7109 #endif 7110 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7111 PHYMOD_SYMBOL_FLAG_REGISTER, 7112 "PKTGEN_PRTPCTLr", 7113 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7114 "PKTGEN0_PRTPCONTROL", 7115 NULL, 7116 #endif 7117 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7118 0x0, /* 0 */ 7119 0, 7120 #endif 7121 }, 7122 { 7123 BCMI_TSCF_XGXS_PKTGEN_CRCERRCNTr, 7124 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7125 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 7126 BCMI_TSCF_XGXS_PKTGEN_CRCERRCNTr_fields, 7127 #else 7128 0, 7129 #endif 7130 #endif 7131 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7132 PHYMOD_SYMBOL_FLAG_REGISTER, 7133 "PKTGEN_CRCERRCNTr", 7134 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7135 "PKTGEN0_CRCERRORCOUNT", 7136 NULL, 7137 #endif 7138 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7139 0x0, /* 0 */ 7140 0, 7141 #endif 7142 }, 7143 { 7144 BCMI_TSCF_XGXS_PKTGEN_PCS_SEEDA0r, 7145 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7146 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 7147 BCMI_TSCF_XGXS_PKTGEN_PCS_SEEDA0r_fields, 7148 #else 7149 0, 7150 #endif 7151 #endif 7152 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7153 PHYMOD_SYMBOL_FLAG_REGISTER, 7154 "PKTGEN_PCS_SEEDA0r", 7155 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7156 "PKTGEN0_PCS_SEEDA0", 7157 NULL, 7158 #endif 7159 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7160 0x0, /* 0 */ 7161 0, 7162 #endif 7163 }, 7164 { 7165 BCMI_TSCF_XGXS_PKTGEN_PCS_SEEDA1r, 7166 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7167 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 7168 BCMI_TSCF_XGXS_PKTGEN_PCS_SEEDA1r_fields, 7169 #else 7170 0, 7171 #endif 7172 #endif 7173 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7174 PHYMOD_SYMBOL_FLAG_REGISTER, 7175 "PKTGEN_PCS_SEEDA1r", 7176 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7177 "PKTGEN0_PCS_SEEDA1", 7178 NULL, 7179 #endif 7180 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7181 0x0, /* 0 */ 7182 0, 7183 #endif 7184 }, 7185 { 7186 BCMI_TSCF_XGXS_PKTGEN_PCS_SEEDA2r, 7187 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7188 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 7189 BCMI_TSCF_XGXS_PKTGEN_PCS_SEEDA2r_fields, 7190 #else 7191 0, 7192 #endif 7193 #endif 7194 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7195 PHYMOD_SYMBOL_FLAG_REGISTER, 7196 "PKTGEN_PCS_SEEDA2r", 7197 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7198 "PKTGEN0_PCS_SEEDA2", 7199 NULL, 7200 #endif 7201 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7202 0x0, /* 0 */ 7203 0, 7204 #endif 7205 }, 7206 { 7207 BCMI_TSCF_XGXS_PKTGEN_PCS_SEEDA3r, 7208 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7209 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 7210 BCMI_TSCF_XGXS_PKTGEN_PCS_SEEDA3r_fields, 7211 #else 7212 0, 7213 #endif 7214 #endif 7215 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7216 PHYMOD_SYMBOL_FLAG_REGISTER, 7217 "PKTGEN_PCS_SEEDA3r", 7218 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7219 "PKTGEN0_PCS_SEEDA3", 7220 NULL, 7221 #endif 7222 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7223 0x0, /* 0 */ 7224 0, 7225 #endif 7226 }, 7227 { 7228 BCMI_TSCF_XGXS_PKTGEN_PCS_SEEDB0r, 7229 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7230 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 7231 BCMI_TSCF_XGXS_PKTGEN_PCS_SEEDB0r_fields, 7232 #else 7233 0, 7234 #endif 7235 #endif 7236 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7237 PHYMOD_SYMBOL_FLAG_REGISTER, 7238 "PKTGEN_PCS_SEEDB0r", 7239 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7240 "PKTGEN0_PCS_SEEDB0", 7241 NULL, 7242 #endif 7243 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7244 0x0, /* 0 */ 7245 0, 7246 #endif 7247 }, 7248 { 7249 BCMI_TSCF_XGXS_PKTGEN_PCS_SEEDB1r, 7250 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7251 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 7252 BCMI_TSCF_XGXS_PKTGEN_PCS_SEEDB1r_fields, 7253 #else 7254 0, 7255 #endif 7256 #endif 7257 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7258 PHYMOD_SYMBOL_FLAG_REGISTER, 7259 "PKTGEN_PCS_SEEDB1r", 7260 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7261 "PKTGEN0_PCS_SEEDB1", 7262 NULL, 7263 #endif 7264 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7265 0x0, /* 0 */ 7266 0, 7267 #endif 7268 }, 7269 { 7270 BCMI_TSCF_XGXS_PKTGEN_PCS_SEEDB2r, 7271 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7272 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 7273 BCMI_TSCF_XGXS_PKTGEN_PCS_SEEDB2r_fields, 7274 #else 7275 0, 7276 #endif 7277 #endif 7278 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7279 PHYMOD_SYMBOL_FLAG_REGISTER, 7280 "PKTGEN_PCS_SEEDB2r", 7281 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7282 "PKTGEN0_PCS_SEEDB2", 7283 NULL, 7284 #endif 7285 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7286 0x0, /* 0 */ 7287 0, 7288 #endif 7289 }, 7290 { 7291 BCMI_TSCF_XGXS_PKTGEN_PCS_SEEDB3r, 7292 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7293 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 7294 BCMI_TSCF_XGXS_PKTGEN_PCS_SEEDB3r_fields, 7295 #else 7296 0, 7297 #endif 7298 #endif 7299 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7300 PHYMOD_SYMBOL_FLAG_REGISTER, 7301 "PKTGEN_PCS_SEEDB3r", 7302 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7303 "PKTGEN0_PCS_SEEDB3", 7304 NULL, 7305 #endif 7306 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7307 0x0, /* 0 */ 7308 0, 7309 #endif 7310 }, 7311 { 7312 BCMI_TSCF_XGXS_PKTGEN_PAYLOADBYTESr, 7313 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7314 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 7315 BCMI_TSCF_XGXS_PKTGEN_PAYLOADBYTESr_fields, 7316 #else 7317 0, 7318 #endif 7319 #endif 7320 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7321 PHYMOD_SYMBOL_FLAG_REGISTER, 7322 "PKTGEN_PAYLOADBYTESr", 7323 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7324 "PKTGEN1_PAYLOADBYTES", 7325 NULL, 7326 #endif 7327 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7328 0x0, /* 0 */ 7329 0, 7330 #endif 7331 }, 7332 { 7333 BCMI_TSCF_XGXS_PKTGEN_ERRMASK4r, 7334 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7335 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 7336 BCMI_TSCF_XGXS_PKTGEN_ERRMASK4r_fields, 7337 #else 7338 0, 7339 #endif 7340 #endif 7341 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7342 PHYMOD_SYMBOL_FLAG_REGISTER, 7343 "PKTGEN_ERRMASK4r", 7344 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7345 "PKTGEN1_ERRORMASK4", 7346 NULL, 7347 #endif 7348 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7349 0x0, /* 0 */ 7350 0, 7351 #endif 7352 }, 7353 { 7354 BCMI_TSCF_XGXS_PKTGEN_ERRMASK3r, 7355 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7356 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 7357 BCMI_TSCF_XGXS_PKTGEN_ERRMASK3r_fields, 7358 #else 7359 0, 7360 #endif 7361 #endif 7362 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7363 PHYMOD_SYMBOL_FLAG_REGISTER, 7364 "PKTGEN_ERRMASK3r", 7365 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7366 "PKTGEN1_ERRORMASK3", 7367 NULL, 7368 #endif 7369 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7370 0x0, /* 0 */ 7371 0, 7372 #endif 7373 }, 7374 { 7375 BCMI_TSCF_XGXS_PKTGEN_ERRMASK2r, 7376 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7377 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 7378 BCMI_TSCF_XGXS_PKTGEN_ERRMASK2r_fields, 7379 #else 7380 0, 7381 #endif 7382 #endif 7383 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7384 PHYMOD_SYMBOL_FLAG_REGISTER, 7385 "PKTGEN_ERRMASK2r", 7386 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7387 "PKTGEN1_ERRORMASK2", 7388 NULL, 7389 #endif 7390 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7391 0x0, /* 0 */ 7392 0, 7393 #endif 7394 }, 7395 { 7396 BCMI_TSCF_XGXS_PKTGEN_ERRMASK1r, 7397 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7398 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 7399 BCMI_TSCF_XGXS_PKTGEN_ERRMASK1r_fields, 7400 #else 7401 0, 7402 #endif 7403 #endif 7404 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7405 PHYMOD_SYMBOL_FLAG_REGISTER, 7406 "PKTGEN_ERRMASK1r", 7407 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7408 "PKTGEN1_ERRORMASK1", 7409 NULL, 7410 #endif 7411 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7412 0x0, /* 0 */ 7413 0, 7414 #endif 7415 }, 7416 { 7417 BCMI_TSCF_XGXS_PKTGEN_ERRMASK0r, 7418 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7419 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 7420 BCMI_TSCF_XGXS_PKTGEN_ERRMASK0r_fields, 7421 #else 7422 0, 7423 #endif 7424 #endif 7425 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7426 PHYMOD_SYMBOL_FLAG_REGISTER, 7427 "PKTGEN_ERRMASK0r", 7428 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7429 "PKTGEN1_ERRORMASK0", 7430 NULL, 7431 #endif 7432 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7433 0x0, /* 0 */ 7434 0, 7435 #endif 7436 }, 7437 { 7438 BCMI_TSCF_XGXS_PKTGEN_ERR_INJ_EN0r, 7439 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7440 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 7441 BCMI_TSCF_XGXS_PKTGEN_ERR_INJ_EN0r_fields, 7442 #else 7443 0, 7444 #endif 7445 #endif 7446 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7447 PHYMOD_SYMBOL_FLAG_REGISTER, 7448 "PKTGEN_ERR_INJ_EN0r", 7449 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7450 "PKTGEN1_ERR_INJ_EN0", 7451 NULL, 7452 #endif 7453 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7454 0x0, /* 0 */ 7455 0, 7456 #endif 7457 }, 7458 { 7459 BCMI_TSCF_XGXS_PKTGEN_ERR_INJ_EN1r, 7460 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7461 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 7462 BCMI_TSCF_XGXS_PKTGEN_ERR_INJ_EN1r_fields, 7463 #else 7464 0, 7465 #endif 7466 #endif 7467 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7468 PHYMOD_SYMBOL_FLAG_REGISTER, 7469 "PKTGEN_ERR_INJ_EN1r", 7470 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7471 "PKTGEN1_ERR_INJ_EN1", 7472 NULL, 7473 #endif 7474 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7475 0x0, /* 0 */ 7476 0, 7477 #endif 7478 }, 7479 { 7480 BCMI_TSCF_XGXS_CL82_RX_AM_TMRr, 7481 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7482 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 7483 BCMI_TSCF_XGXS_CL82_RX_AM_TMRr_fields, 7484 #else 7485 0, 7486 #endif 7487 #endif 7488 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7489 PHYMOD_SYMBOL_FLAG_REGISTER, 7490 "CL82_RX_AM_TMRr", 7491 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7492 "CL82_SHARED_CL82_RX_AM_TIMER", 7493 NULL, 7494 #endif 7495 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7496 0x3fff, /* 16383 */ 7497 0, 7498 #endif 7499 }, 7500 { 7501 BCMI_TSCF_XGXS_CL82_LN_0_AM_BYTE10r, 7502 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7503 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 7504 BCMI_TSCF_XGXS_CL82_LN_0_AM_BYTE10r_fields, 7505 #else 7506 0, 7507 #endif 7508 #endif 7509 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7510 PHYMOD_SYMBOL_FLAG_REGISTER, 7511 "CL82_LN_0_AM_BYTE10r", 7512 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7513 "CL82_AM_REGS_LANE_0_AM_BYTE10", 7514 NULL, 7515 #endif 7516 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7517 0x7690, /* 30352 */ 7518 0, 7519 #endif 7520 }, 7521 { 7522 BCMI_TSCF_XGXS_CL82_LN_1_AM_BYTE10r, 7523 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7524 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 7525 BCMI_TSCF_XGXS_CL82_LN_1_AM_BYTE10r_fields, 7526 #else 7527 0, 7528 #endif 7529 #endif 7530 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7531 PHYMOD_SYMBOL_FLAG_REGISTER, 7532 "CL82_LN_1_AM_BYTE10r", 7533 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7534 "CL82_AM_REGS_LANE_1_AM_BYTE10", 7535 NULL, 7536 #endif 7537 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7538 0xc4f0, /* 50416 */ 7539 0, 7540 #endif 7541 }, 7542 { 7543 BCMI_TSCF_XGXS_CL82_LANES_1_0_AM_BYTE2r, 7544 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7545 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 7546 BCMI_TSCF_XGXS_CL82_LANES_1_0_AM_BYTE2r_fields, 7547 #else 7548 0, 7549 #endif 7550 #endif 7551 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7552 PHYMOD_SYMBOL_FLAG_REGISTER, 7553 "CL82_LANES_1_0_AM_BYTE2r", 7554 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7555 "CL82_AM_REGS_LANES_1_0_AM_BYTE2", 7556 NULL, 7557 #endif 7558 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7559 0xe647, /* 58951 */ 7560 0, 7561 #endif 7562 }, 7563 { 7564 BCMI_TSCF_XGXS_TX_X1_T_PMA_WTRMKr, 7565 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7566 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 7567 BCMI_TSCF_XGXS_TX_X1_T_PMA_WTRMKr_fields, 7568 #else 7569 0, 7570 #endif 7571 #endif 7572 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7573 PHYMOD_SYMBOL_FLAG_REGISTER, 7574 "TX_X1_T_PMA_WTRMKr", 7575 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7576 "TX_X1_CONTROL0_T_PMA_WATERMARK", 7577 NULL, 7578 #endif 7579 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7580 0x744, /* 1860 */ 7581 0, 7582 #endif 7583 }, 7584 { 7585 BCMI_TSCF_XGXS_TX_X1_T_PMA_DELAYr, 7586 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7587 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 7588 BCMI_TSCF_XGXS_TX_X1_T_PMA_DELAYr_fields, 7589 #else 7590 0, 7591 #endif 7592 #endif 7593 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7594 PHYMOD_SYMBOL_FLAG_REGISTER, 7595 "TX_X1_T_PMA_DELAYr", 7596 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7597 "TX_X1_CONTROL0_T_PMA_DELAY", 7598 NULL, 7599 #endif 7600 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7601 0x15, /* 21 */ 7602 0, 7603 #endif 7604 }, 7605 { 7606 BCMI_TSCF_XGXS_TX_X1_T_CL91_FECr, 7607 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7608 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 7609 BCMI_TSCF_XGXS_TX_X1_T_CL91_FECr_fields, 7610 #else 7611 0, 7612 #endif 7613 #endif 7614 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7615 PHYMOD_SYMBOL_FLAG_REGISTER, 7616 "TX_X1_T_CL91_FECr", 7617 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7618 "TX_X1_CONTROL0_T_CL91_FEC", 7619 NULL, 7620 #endif 7621 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7622 0x0, /* 0 */ 7623 0, 7624 #endif 7625 }, 7626 { 7627 BCMI_TSCF_XGXS_RX_X1_DEC_CTL1r, 7628 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7629 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 7630 BCMI_TSCF_XGXS_RX_X1_DEC_CTL1r_fields, 7631 #else 7632 0, 7633 #endif 7634 #endif 7635 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7636 PHYMOD_SYMBOL_FLAG_REGISTER, 7637 "RX_X1_DEC_CTL1r", 7638 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7639 "RX_X1_CONTROL0_DECODE_CONTROL_1", 7640 NULL, 7641 #endif 7642 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7643 0x6140, /* 24896 */ 7644 0, 7645 #endif 7646 }, 7647 { 7648 BCMI_TSCF_XGXS_RX_X1_DESKEW_WINSr, 7649 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7650 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 7651 BCMI_TSCF_XGXS_RX_X1_DESKEW_WINSr_fields, 7652 #else 7653 0, 7654 #endif 7655 #endif 7656 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7657 PHYMOD_SYMBOL_FLAG_REGISTER, 7658 "RX_X1_DESKEW_WINSr", 7659 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7660 "RX_X1_CONTROL0_DESKEW_WINDOWS", 7661 NULL, 7662 #endif 7663 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7664 0xee4e, /* 61006 */ 7665 0, 7666 #endif 7667 }, 7668 { 7669 BCMI_TSCF_XGXS_RX_X1_CL91_CFGr, 7670 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7671 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 7672 BCMI_TSCF_XGXS_RX_X1_CL91_CFGr_fields, 7673 #else 7674 0, 7675 #endif 7676 #endif 7677 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7678 PHYMOD_SYMBOL_FLAG_REGISTER, 7679 "RX_X1_CL91_CFGr", 7680 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7681 "RX_X1_CONTROL0_CL91_CONFIG", 7682 NULL, 7683 #endif 7684 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7685 0x0, /* 0 */ 7686 0, 7687 #endif 7688 }, 7689 { 7690 BCMI_TSCF_XGXS_RX_X1_CL91_THRr, 7691 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7692 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 7693 BCMI_TSCF_XGXS_RX_X1_CL91_THRr_fields, 7694 #else 7695 0, 7696 #endif 7697 #endif 7698 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7699 PHYMOD_SYMBOL_FLAG_REGISTER, 7700 "RX_X1_CL91_THRr", 7701 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7702 "RX_X1_CONTROL0_CL91_THRESHOLD", 7703 NULL, 7704 #endif 7705 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7706 0x1a1, /* 417 */ 7707 0, 7708 #endif 7709 }, 7710 { 7711 BCMI_TSCF_XGXS_RX_X1_CL91_TMRr, 7712 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7713 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 7714 BCMI_TSCF_XGXS_RX_X1_CL91_TMRr_fields, 7715 #else 7716 0, 7717 #endif 7718 #endif 7719 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7720 PHYMOD_SYMBOL_FLAG_REGISTER, 7721 "RX_X1_CL91_TMRr", 7722 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7723 "RX_X1_CONTROL0_CL91_TIMER", 7724 NULL, 7725 #endif 7726 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7727 0xfa0, /* 4000 */ 7728 0, 7729 #endif 7730 }, 7731 { 7732 BCMI_TSCF_XGXS_RX_X1_ECC_STS_FEC_MEM0r, 7733 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7734 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 7735 BCMI_TSCF_XGXS_RX_X1_ECC_STS_FEC_MEM0r_fields, 7736 #else 7737 0, 7738 #endif 7739 #endif 7740 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7741 PHYMOD_SYMBOL_FLAG_REGISTER, 7742 "RX_X1_ECC_STS_FEC_MEM0r", 7743 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7744 "RX_X1_ECC_STATUS_FEC_MEM_0", 7745 NULL, 7746 #endif 7747 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7748 0x0, /* 0 */ 7749 0, 7750 #endif 7751 }, 7752 { 7753 BCMI_TSCF_XGXS_RX_X1_ECC_STS_FEC_MEM1r, 7754 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7755 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 7756 BCMI_TSCF_XGXS_RX_X1_ECC_STS_FEC_MEM1r_fields, 7757 #else 7758 0, 7759 #endif 7760 #endif 7761 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7762 PHYMOD_SYMBOL_FLAG_REGISTER, 7763 "RX_X1_ECC_STS_FEC_MEM1r", 7764 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7765 "RX_X1_ECC_STATUS_FEC_MEM_1", 7766 NULL, 7767 #endif 7768 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7769 0x0, /* 0 */ 7770 0, 7771 #endif 7772 }, 7773 { 7774 BCMI_TSCF_XGXS_RX_X1_ECC_STS_FEC_MEM2r, 7775 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7776 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 7777 BCMI_TSCF_XGXS_RX_X1_ECC_STS_FEC_MEM2r_fields, 7778 #else 7779 0, 7780 #endif 7781 #endif 7782 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7783 PHYMOD_SYMBOL_FLAG_REGISTER, 7784 "RX_X1_ECC_STS_FEC_MEM2r", 7785 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7786 "RX_X1_ECC_STATUS_FEC_MEM_2", 7787 NULL, 7788 #endif 7789 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7790 0x0, /* 0 */ 7791 0, 7792 #endif 7793 }, 7794 { 7795 BCMI_TSCF_XGXS_RX_X1_ECC_STS_FEC_MEM3r, 7796 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7797 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 7798 BCMI_TSCF_XGXS_RX_X1_ECC_STS_FEC_MEM3r_fields, 7799 #else 7800 0, 7801 #endif 7802 #endif 7803 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7804 PHYMOD_SYMBOL_FLAG_REGISTER, 7805 "RX_X1_ECC_STS_FEC_MEM3r", 7806 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7807 "RX_X1_ECC_STATUS_FEC_MEM_3", 7808 NULL, 7809 #endif 7810 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7811 0x0, /* 0 */ 7812 0, 7813 #endif 7814 }, 7815 { 7816 BCMI_TSCF_XGXS_RX_X1_ECC_STS_DESKEW_MEM0r, 7817 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7818 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 7819 BCMI_TSCF_XGXS_RX_X1_ECC_STS_DESKEW_MEM0r_fields, 7820 #else 7821 0, 7822 #endif 7823 #endif 7824 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7825 PHYMOD_SYMBOL_FLAG_REGISTER, 7826 "RX_X1_ECC_STS_DESKEW_MEM0r", 7827 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7828 "RX_X1_ECC_STATUS_DESKEW_MEM_0", 7829 NULL, 7830 #endif 7831 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7832 0x0, /* 0 */ 7833 0, 7834 #endif 7835 }, 7836 { 7837 BCMI_TSCF_XGXS_RX_X1_ECC_STS_DESKEW_MEM1r, 7838 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7839 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 7840 BCMI_TSCF_XGXS_RX_X1_ECC_STS_DESKEW_MEM1r_fields, 7841 #else 7842 0, 7843 #endif 7844 #endif 7845 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7846 PHYMOD_SYMBOL_FLAG_REGISTER, 7847 "RX_X1_ECC_STS_DESKEW_MEM1r", 7848 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7849 "RX_X1_ECC_STATUS_DESKEW_MEM_1", 7850 NULL, 7851 #endif 7852 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7853 0x0, /* 0 */ 7854 0, 7855 #endif 7856 }, 7857 { 7858 BCMI_TSCF_XGXS_RX_X1_ECC_STS_DESKEW_MEM2r, 7859 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7860 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 7861 BCMI_TSCF_XGXS_RX_X1_ECC_STS_DESKEW_MEM2r_fields, 7862 #else 7863 0, 7864 #endif 7865 #endif 7866 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7867 PHYMOD_SYMBOL_FLAG_REGISTER, 7868 "RX_X1_ECC_STS_DESKEW_MEM2r", 7869 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7870 "RX_X1_ECC_STATUS_DESKEW_MEM_2", 7871 NULL, 7872 #endif 7873 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7874 0x0, /* 0 */ 7875 0, 7876 #endif 7877 }, 7878 { 7879 BCMI_TSCF_XGXS_RX_X1_ECC_STS_DESKEW_MEM3r, 7880 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7881 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 7882 BCMI_TSCF_XGXS_RX_X1_ECC_STS_DESKEW_MEM3r_fields, 7883 #else 7884 0, 7885 #endif 7886 #endif 7887 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7888 PHYMOD_SYMBOL_FLAG_REGISTER, 7889 "RX_X1_ECC_STS_DESKEW_MEM3r", 7890 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7891 "RX_X1_ECC_STATUS_DESKEW_MEM_3", 7892 NULL, 7893 #endif 7894 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7895 0x0, /* 0 */ 7896 0, 7897 #endif 7898 }, 7899 { 7900 BCMI_TSCF_XGXS_RX_X1_ECC_INTR_STS_1BITr, 7901 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7902 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 7903 BCMI_TSCF_XGXS_RX_X1_ECC_INTR_STS_1BITr_fields, 7904 #else 7905 0, 7906 #endif 7907 #endif 7908 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7909 PHYMOD_SYMBOL_FLAG_REGISTER, 7910 "RX_X1_ECC_INTR_STS_1BITr", 7911 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7912 "RX_X1_ECC_INTERRUPT_STATUS_1BIT", 7913 NULL, 7914 #endif 7915 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7916 0x0, /* 0 */ 7917 0, 7918 #endif 7919 }, 7920 { 7921 BCMI_TSCF_XGXS_RX_X1_ECC_INTR_STS_2BITr, 7922 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7923 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 7924 BCMI_TSCF_XGXS_RX_X1_ECC_INTR_STS_2BITr_fields, 7925 #else 7926 0, 7927 #endif 7928 #endif 7929 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7930 PHYMOD_SYMBOL_FLAG_REGISTER, 7931 "RX_X1_ECC_INTR_STS_2BITr", 7932 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7933 "RX_X1_ECC_INTERRUPT_STATUS_2BIT", 7934 NULL, 7935 #endif 7936 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7937 0x0, /* 0 */ 7938 0, 7939 #endif 7940 }, 7941 { 7942 BCMI_TSCF_XGXS_RX_X1_ECC_INTR_EN_1BITr, 7943 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7944 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 7945 BCMI_TSCF_XGXS_RX_X1_ECC_INTR_EN_1BITr_fields, 7946 #else 7947 0, 7948 #endif 7949 #endif 7950 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7951 PHYMOD_SYMBOL_FLAG_REGISTER, 7952 "RX_X1_ECC_INTR_EN_1BITr", 7953 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7954 "RX_X1_ECC_INTERRUPT_EN_1BIT", 7955 NULL, 7956 #endif 7957 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7958 0xff, /* 255 */ 7959 0, 7960 #endif 7961 }, 7962 { 7963 BCMI_TSCF_XGXS_RX_X1_ECC_INTR_EN_2BITr, 7964 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7965 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 7966 BCMI_TSCF_XGXS_RX_X1_ECC_INTR_EN_2BITr_fields, 7967 #else 7968 0, 7969 #endif 7970 #endif 7971 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7972 PHYMOD_SYMBOL_FLAG_REGISTER, 7973 "RX_X1_ECC_INTR_EN_2BITr", 7974 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7975 "RX_X1_ECC_INTERRUPT_EN_2BIT", 7976 NULL, 7977 #endif 7978 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7979 0xff, /* 255 */ 7980 0, 7981 #endif 7982 }, 7983 { 7984 BCMI_TSCF_XGXS_RX_X1_ECC_DIS_ECC_MEMr, 7985 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7986 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 7987 BCMI_TSCF_XGXS_RX_X1_ECC_DIS_ECC_MEMr_fields, 7988 #else 7989 0, 7990 #endif 7991 #endif 7992 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7993 PHYMOD_SYMBOL_FLAG_REGISTER, 7994 "RX_X1_ECC_DIS_ECC_MEMr", 7995 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7996 "RX_X1_ECC_DISABLE_ECC_MEM", 7997 NULL, 7998 #endif 7999 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8000 0x0, /* 0 */ 8001 0, 8002 #endif 8003 }, 8004 { 8005 BCMI_TSCF_XGXS_RX_X1_ECC_CORRUPTr, 8006 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8007 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 8008 BCMI_TSCF_XGXS_RX_X1_ECC_CORRUPTr_fields, 8009 #else 8010 0, 8011 #endif 8012 #endif 8013 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8014 PHYMOD_SYMBOL_FLAG_REGISTER, 8015 "RX_X1_ECC_CORRUPTr", 8016 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8017 NULL, 8018 NULL, 8019 #endif 8020 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8021 0x0, /* 0 */ 8022 0, 8023 #endif 8024 }, 8025 { 8026 BCMI_TSCF_XGXS_AN_X1_OUI_UPRr, 8027 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8028 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 8029 BCMI_TSCF_XGXS_AN_X1_OUI_UPRr_fields, 8030 #else 8031 0, 8032 #endif 8033 #endif 8034 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8035 PHYMOD_SYMBOL_FLAG_REGISTER, 8036 "AN_X1_OUI_UPRr", 8037 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8038 "AN_X1_CONTROL_OUI_UPPER", 8039 NULL, 8040 #endif 8041 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8042 0x0, /* 0 */ 8043 0, 8044 #endif 8045 }, 8046 { 8047 BCMI_TSCF_XGXS_AN_X1_OUI_LWRr, 8048 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8049 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 8050 BCMI_TSCF_XGXS_AN_X1_OUI_LWRr_fields, 8051 #else 8052 0, 8053 #endif 8054 #endif 8055 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8056 PHYMOD_SYMBOL_FLAG_REGISTER, 8057 "AN_X1_OUI_LWRr", 8058 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8059 "AN_X1_CONTROL_OUI_LOWER", 8060 NULL, 8061 #endif 8062 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8063 0x0, /* 0 */ 8064 0, 8065 #endif 8066 }, 8067 { 8068 BCMI_TSCF_XGXS_AN_X1_BAM_SPD_PRI0r, 8069 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8070 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 8071 BCMI_TSCF_XGXS_AN_X1_BAM_SPD_PRI0r_fields, 8072 #else 8073 0, 8074 #endif 8075 #endif 8076 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8077 PHYMOD_SYMBOL_FLAG_REGISTER, 8078 "AN_X1_BAM_SPD_PRI0r", 8079 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8080 "AN_X1_CONTROL_BAM_SPEED_PRI_0", 8081 NULL, 8082 #endif 8083 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8084 0x0, /* 0 */ 8085 0, 8086 #endif 8087 }, 8088 { 8089 BCMI_TSCF_XGXS_AN_X1_BAM_SPD_PRI1r, 8090 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8091 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 8092 BCMI_TSCF_XGXS_AN_X1_BAM_SPD_PRI1r_fields, 8093 #else 8094 0, 8095 #endif 8096 #endif 8097 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8098 PHYMOD_SYMBOL_FLAG_REGISTER, 8099 "AN_X1_BAM_SPD_PRI1r", 8100 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8101 "AN_X1_CONTROL_BAM_SPEED_PRI_1", 8102 NULL, 8103 #endif 8104 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8105 0x0, /* 0 */ 8106 0, 8107 #endif 8108 }, 8109 { 8110 BCMI_TSCF_XGXS_AN_X1_BAM_SPD_PRI2r, 8111 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8112 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 8113 BCMI_TSCF_XGXS_AN_X1_BAM_SPD_PRI2r_fields, 8114 #else 8115 0, 8116 #endif 8117 #endif 8118 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8119 PHYMOD_SYMBOL_FLAG_REGISTER, 8120 "AN_X1_BAM_SPD_PRI2r", 8121 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8122 "AN_X1_CONTROL_BAM_SPEED_PRI_2", 8123 NULL, 8124 #endif 8125 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8126 0x0, /* 0 */ 8127 0, 8128 #endif 8129 }, 8130 { 8131 BCMI_TSCF_XGXS_AN_X1_BAM_SPD_PRI3r, 8132 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8133 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 8134 BCMI_TSCF_XGXS_AN_X1_BAM_SPD_PRI3r_fields, 8135 #else 8136 0, 8137 #endif 8138 #endif 8139 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8140 PHYMOD_SYMBOL_FLAG_REGISTER, 8141 "AN_X1_BAM_SPD_PRI3r", 8142 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8143 "AN_X1_CONTROL_BAM_SPEED_PRI_3", 8144 NULL, 8145 #endif 8146 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8147 0x0, /* 0 */ 8148 0, 8149 #endif 8150 }, 8151 { 8152 BCMI_TSCF_XGXS_AN_X1_BAM_SPD_PRI4r, 8153 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8154 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 8155 BCMI_TSCF_XGXS_AN_X1_BAM_SPD_PRI4r_fields, 8156 #else 8157 0, 8158 #endif 8159 #endif 8160 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8161 PHYMOD_SYMBOL_FLAG_REGISTER, 8162 "AN_X1_BAM_SPD_PRI4r", 8163 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8164 "AN_X1_CONTROL_BAM_SPEED_PRI_4", 8165 NULL, 8166 #endif 8167 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8168 0x0, /* 0 */ 8169 0, 8170 #endif 8171 }, 8172 { 8173 BCMI_TSCF_XGXS_AN_X1_CL73_BRK_LNKr, 8174 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8175 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 8176 BCMI_TSCF_XGXS_AN_X1_CL73_BRK_LNKr_fields, 8177 #else 8178 0, 8179 #endif 8180 #endif 8181 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8182 PHYMOD_SYMBOL_FLAG_REGISTER, 8183 "AN_X1_CL73_BRK_LNKr", 8184 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8185 "AN_X1_TIMERS_CL73_BREAK_LINK", 8186 NULL, 8187 #endif 8188 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8189 0x0, /* 0 */ 8190 0, 8191 #endif 8192 }, 8193 { 8194 BCMI_TSCF_XGXS_AN_X1_CL73_ERRr, 8195 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8196 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 8197 BCMI_TSCF_XGXS_AN_X1_CL73_ERRr_fields, 8198 #else 8199 0, 8200 #endif 8201 #endif 8202 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8203 PHYMOD_SYMBOL_FLAG_REGISTER, 8204 "AN_X1_CL73_ERRr", 8205 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8206 "AN_X1_TIMERS_CL73_ERROR", 8207 NULL, 8208 #endif 8209 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8210 0x0, /* 0 */ 8211 0, 8212 #endif 8213 }, 8214 { 8215 BCMI_TSCF_XGXS_AN_X1_CL73_DME_LOCKr, 8216 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8217 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 8218 BCMI_TSCF_XGXS_AN_X1_CL73_DME_LOCKr_fields, 8219 #else 8220 0, 8221 #endif 8222 #endif 8223 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8224 PHYMOD_SYMBOL_FLAG_REGISTER, 8225 "AN_X1_CL73_DME_LOCKr", 8226 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8227 "AN_X1_TIMERS_CL73_DME_LOCK", 8228 NULL, 8229 #endif 8230 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8231 0x0, /* 0 */ 8232 0, 8233 #endif 8234 }, 8235 { 8236 BCMI_TSCF_XGXS_AN_X1_PD_SD_TMRr, 8237 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8238 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 8239 BCMI_TSCF_XGXS_AN_X1_PD_SD_TMRr_fields, 8240 #else 8241 0, 8242 #endif 8243 #endif 8244 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8245 PHYMOD_SYMBOL_FLAG_REGISTER, 8246 "AN_X1_PD_SD_TMRr", 8247 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8248 "AN_X1_TIMERS_PD_SD_TIMER", 8249 NULL, 8250 #endif 8251 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8252 0x0, /* 0 */ 8253 0, 8254 #endif 8255 }, 8256 { 8257 BCMI_TSCF_XGXS_AN_X1_IGNORE_LNK_TMRr, 8258 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8259 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 8260 BCMI_TSCF_XGXS_AN_X1_IGNORE_LNK_TMRr_fields, 8261 #else 8262 0, 8263 #endif 8264 #endif 8265 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8266 PHYMOD_SYMBOL_FLAG_REGISTER, 8267 "AN_X1_IGNORE_LNK_TMRr", 8268 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8269 "AN_X1_TIMERS_IGNORE_LINK_TIMER", 8270 NULL, 8271 #endif 8272 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8273 0x0, /* 0 */ 8274 0, 8275 #endif 8276 }, 8277 { 8278 BCMI_TSCF_XGXS_AN_X1_LNK_FAIL_INHBT_TMR_CL72r, 8279 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8280 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 8281 BCMI_TSCF_XGXS_AN_X1_LNK_FAIL_INHBT_TMR_CL72r_fields, 8282 #else 8283 0, 8284 #endif 8285 #endif 8286 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8287 PHYMOD_SYMBOL_FLAG_REGISTER, 8288 "AN_X1_LNK_FAIL_INHBT_TMR_CL72r", 8289 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8290 "AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_CL72", 8291 NULL, 8292 #endif 8293 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8294 0x0, /* 0 */ 8295 0, 8296 #endif 8297 }, 8298 { 8299 BCMI_TSCF_XGXS_AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72r, 8300 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8301 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 8302 BCMI_TSCF_XGXS_AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72r_fields, 8303 #else 8304 0, 8305 #endif 8306 #endif 8307 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8308 PHYMOD_SYMBOL_FLAG_REGISTER, 8309 "AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72r", 8310 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8311 "AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_NOT_CL72", 8312 NULL, 8313 #endif 8314 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8315 0x0, /* 0 */ 8316 0, 8317 #endif 8318 }, 8319 { 8320 BCMI_TSCF_XGXS_AN_X1_DME_PAGE_TMR_TYPEr, 8321 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8322 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 8323 BCMI_TSCF_XGXS_AN_X1_DME_PAGE_TMR_TYPEr_fields, 8324 #else 8325 0, 8326 #endif 8327 #endif 8328 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8329 PHYMOD_SYMBOL_FLAG_REGISTER, 8330 "AN_X1_DME_PAGE_TMR_TYPEr", 8331 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8332 "AN_X1_TIMERS_DME_PAGE_TIMER_TYPE", 8333 NULL, 8334 #endif 8335 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8336 0x3b5f, /* 15199 */ 8337 0, 8338 #endif 8339 }, 8340 { 8341 BCMI_TSCF_XGXS_SC_X1_PLL_LOCK_TMRr, 8342 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8343 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 8344 BCMI_TSCF_XGXS_SC_X1_PLL_LOCK_TMRr_fields, 8345 #else 8346 0, 8347 #endif 8348 #endif 8349 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8350 PHYMOD_SYMBOL_FLAG_REGISTER, 8351 "SC_X1_PLL_LOCK_TMRr", 8352 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8353 "SC_X1_CONTROL_PLL_LOCK_TIMER", 8354 NULL, 8355 #endif 8356 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8357 0x0, /* 0 */ 8358 0, 8359 #endif 8360 }, 8361 { 8362 BCMI_TSCF_XGXS_SC_X1_PMD_LOCK_TMRr, 8363 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8364 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 8365 BCMI_TSCF_XGXS_SC_X1_PMD_LOCK_TMRr_fields, 8366 #else 8367 0, 8368 #endif 8369 #endif 8370 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8371 PHYMOD_SYMBOL_FLAG_REGISTER, 8372 "SC_X1_PMD_LOCK_TMRr", 8373 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8374 "SC_X1_CONTROL_PMD_LOCK_TIMER", 8375 NULL, 8376 #endif 8377 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8378 0x0, /* 0 */ 8379 0, 8380 #endif 8381 }, 8382 { 8383 BCMI_TSCF_XGXS_SC_X1_PIPE_RST_CNTr, 8384 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8385 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 8386 BCMI_TSCF_XGXS_SC_X1_PIPE_RST_CNTr_fields, 8387 #else 8388 0, 8389 #endif 8390 #endif 8391 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8392 PHYMOD_SYMBOL_FLAG_REGISTER, 8393 "SC_X1_PIPE_RST_CNTr", 8394 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8395 "SC_X1_CONTROL_PIPELINE_RESET_COUNT", 8396 NULL, 8397 #endif 8398 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8399 0xff, /* 255 */ 8400 0, 8401 #endif 8402 }, 8403 { 8404 BCMI_TSCF_XGXS_SC_X1_TX_RST_CNTr, 8405 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8406 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 8407 BCMI_TSCF_XGXS_SC_X1_TX_RST_CNTr_fields, 8408 #else 8409 0, 8410 #endif 8411 #endif 8412 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8413 PHYMOD_SYMBOL_FLAG_REGISTER, 8414 "SC_X1_TX_RST_CNTr", 8415 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8416 "SC_X1_CONTROL_TX_RESET_COUNT", 8417 NULL, 8418 #endif 8419 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8420 0x2, /* 2 */ 8421 0, 8422 #endif 8423 }, 8424 { 8425 BCMI_TSCF_XGXS_SC_X1_STSr, 8426 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8427 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 8428 BCMI_TSCF_XGXS_SC_X1_STSr_fields, 8429 #else 8430 0, 8431 #endif 8432 #endif 8433 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8434 PHYMOD_SYMBOL_FLAG_REGISTER, 8435 "SC_X1_STSr", 8436 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8437 "SC_X1_CONTROL_STATUS", 8438 NULL, 8439 #endif 8440 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8441 0x0, /* 0 */ 8442 0, 8443 #endif 8444 }, 8445 { 8446 BCMI_TSCF_XGXS_SC_X1_SPD_OVRR0_SPDr, 8447 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8448 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 8449 BCMI_TSCF_XGXS_SC_X1_SPD_OVRR0_SPDr_fields, 8450 #else 8451 0, 8452 #endif 8453 #endif 8454 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8455 PHYMOD_SYMBOL_FLAG_REGISTER, 8456 "SC_X1_SPD_OVRR0_SPDr", 8457 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8458 "SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED", 8459 NULL, 8460 #endif 8461 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8462 0xff00, /* 65280 */ 8463 0, 8464 #endif 8465 }, 8466 { 8467 BCMI_TSCF_XGXS_SC_X1_SPD_OVRR0_0r, 8468 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8469 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 8470 BCMI_TSCF_XGXS_SC_X1_SPD_OVRR0_0r_fields, 8471 #else 8472 0, 8473 #endif 8474 #endif 8475 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8476 PHYMOD_SYMBOL_FLAG_REGISTER, 8477 "SC_X1_SPD_OVRR0_0r", 8478 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8479 "SC_X1_SPEED_OVERRIDE0_OVERRIDE_0", 8480 NULL, 8481 #endif 8482 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8483 0x0, /* 0 */ 8484 0, 8485 #endif 8486 }, 8487 { 8488 BCMI_TSCF_XGXS_SC_X1_SPD_OVRR0_1r, 8489 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8490 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 8491 BCMI_TSCF_XGXS_SC_X1_SPD_OVRR0_1r_fields, 8492 #else 8493 0, 8494 #endif 8495 #endif 8496 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8497 PHYMOD_SYMBOL_FLAG_REGISTER, 8498 "SC_X1_SPD_OVRR0_1r", 8499 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8500 "SC_X1_SPEED_OVERRIDE0_OVERRIDE_1", 8501 NULL, 8502 #endif 8503 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8504 0x0, /* 0 */ 8505 0, 8506 #endif 8507 }, 8508 { 8509 BCMI_TSCF_XGXS_SC_X1_SPD_OVRR0_2r, 8510 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8511 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 8512 BCMI_TSCF_XGXS_SC_X1_SPD_OVRR0_2r_fields, 8513 #else 8514 0, 8515 #endif 8516 #endif 8517 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8518 PHYMOD_SYMBOL_FLAG_REGISTER, 8519 "SC_X1_SPD_OVRR0_2r", 8520 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8521 "SC_X1_SPEED_OVERRIDE0_OVERRIDE_2", 8522 NULL, 8523 #endif 8524 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8525 0x0, /* 0 */ 8526 0, 8527 #endif 8528 }, 8529 { 8530 BCMI_TSCF_XGXS_SC_X1_SPD_OVRR0_3r, 8531 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8532 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 8533 BCMI_TSCF_XGXS_SC_X1_SPD_OVRR0_3r_fields, 8534 #else 8535 0, 8536 #endif 8537 #endif 8538 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8539 PHYMOD_SYMBOL_FLAG_REGISTER, 8540 "SC_X1_SPD_OVRR0_3r", 8541 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8542 "SC_X1_SPEED_OVERRIDE0_OVERRIDE_3", 8543 NULL, 8544 #endif 8545 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8546 0x0, /* 0 */ 8547 0, 8548 #endif 8549 }, 8550 { 8551 BCMI_TSCF_XGXS_SC_X1_SPD_OVRR0_4r, 8552 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8553 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 8554 BCMI_TSCF_XGXS_SC_X1_SPD_OVRR0_4r_fields, 8555 #else 8556 0, 8557 #endif 8558 #endif 8559 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8560 PHYMOD_SYMBOL_FLAG_REGISTER, 8561 "SC_X1_SPD_OVRR0_4r", 8562 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8563 "SC_X1_SPEED_OVERRIDE0_OVERRIDE_4", 8564 NULL, 8565 #endif 8566 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8567 0x0, /* 0 */ 8568 0, 8569 #endif 8570 }, 8571 { 8572 BCMI_TSCF_XGXS_SC_X1_SPD_OVRR0_5r, 8573 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8574 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 8575 BCMI_TSCF_XGXS_SC_X1_SPD_OVRR0_5r_fields, 8576 #else 8577 0, 8578 #endif 8579 #endif 8580 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8581 PHYMOD_SYMBOL_FLAG_REGISTER, 8582 "SC_X1_SPD_OVRR0_5r", 8583 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8584 "SC_X1_SPEED_OVERRIDE0_OVERRIDE_5", 8585 NULL, 8586 #endif 8587 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8588 0x0, /* 0 */ 8589 0, 8590 #endif 8591 }, 8592 { 8593 BCMI_TSCF_XGXS_SC_X1_SPD_OVRR1_SPDr, 8594 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8595 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 8596 BCMI_TSCF_XGXS_SC_X1_SPD_OVRR1_SPDr_fields, 8597 #else 8598 0, 8599 #endif 8600 #endif 8601 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8602 PHYMOD_SYMBOL_FLAG_REGISTER, 8603 "SC_X1_SPD_OVRR1_SPDr", 8604 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8605 "SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED", 8606 NULL, 8607 #endif 8608 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8609 0xff00, /* 65280 */ 8610 0, 8611 #endif 8612 }, 8613 { 8614 BCMI_TSCF_XGXS_SC_X1_SPD_OVRR1_0r, 8615 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8616 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 8617 BCMI_TSCF_XGXS_SC_X1_SPD_OVRR1_0r_fields, 8618 #else 8619 0, 8620 #endif 8621 #endif 8622 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8623 PHYMOD_SYMBOL_FLAG_REGISTER, 8624 "SC_X1_SPD_OVRR1_0r", 8625 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8626 "SC_X1_SPEED_OVERRIDE1_OVERRIDE_0", 8627 NULL, 8628 #endif 8629 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8630 0x0, /* 0 */ 8631 0, 8632 #endif 8633 }, 8634 { 8635 BCMI_TSCF_XGXS_SC_X1_SPD_OVRR1_1r, 8636 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8637 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 8638 BCMI_TSCF_XGXS_SC_X1_SPD_OVRR1_1r_fields, 8639 #else 8640 0, 8641 #endif 8642 #endif 8643 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8644 PHYMOD_SYMBOL_FLAG_REGISTER, 8645 "SC_X1_SPD_OVRR1_1r", 8646 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8647 "SC_X1_SPEED_OVERRIDE1_OVERRIDE_1", 8648 NULL, 8649 #endif 8650 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8651 0x0, /* 0 */ 8652 0, 8653 #endif 8654 }, 8655 { 8656 BCMI_TSCF_XGXS_SC_X1_SPD_OVRR1_2r, 8657 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8658 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 8659 BCMI_TSCF_XGXS_SC_X1_SPD_OVRR1_2r_fields, 8660 #else 8661 0, 8662 #endif 8663 #endif 8664 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8665 PHYMOD_SYMBOL_FLAG_REGISTER, 8666 "SC_X1_SPD_OVRR1_2r", 8667 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8668 "SC_X1_SPEED_OVERRIDE1_OVERRIDE_2", 8669 NULL, 8670 #endif 8671 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8672 0x0, /* 0 */ 8673 0, 8674 #endif 8675 }, 8676 { 8677 BCMI_TSCF_XGXS_SC_X1_SPD_OVRR1_3r, 8678 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8679 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 8680 BCMI_TSCF_XGXS_SC_X1_SPD_OVRR1_3r_fields, 8681 #else 8682 0, 8683 #endif 8684 #endif 8685 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8686 PHYMOD_SYMBOL_FLAG_REGISTER, 8687 "SC_X1_SPD_OVRR1_3r", 8688 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8689 "SC_X1_SPEED_OVERRIDE1_OVERRIDE_3", 8690 NULL, 8691 #endif 8692 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8693 0x0, /* 0 */ 8694 0, 8695 #endif 8696 }, 8697 { 8698 BCMI_TSCF_XGXS_SC_X1_SPD_OVRR1_4r, 8699 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8700 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 8701 BCMI_TSCF_XGXS_SC_X1_SPD_OVRR1_4r_fields, 8702 #else 8703 0, 8704 #endif 8705 #endif 8706 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8707 PHYMOD_SYMBOL_FLAG_REGISTER, 8708 "SC_X1_SPD_OVRR1_4r", 8709 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8710 "SC_X1_SPEED_OVERRIDE1_OVERRIDE_4", 8711 NULL, 8712 #endif 8713 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8714 0x0, /* 0 */ 8715 0, 8716 #endif 8717 }, 8718 { 8719 BCMI_TSCF_XGXS_SC_X1_SPD_OVRR1_5r, 8720 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8721 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 8722 BCMI_TSCF_XGXS_SC_X1_SPD_OVRR1_5r_fields, 8723 #else 8724 0, 8725 #endif 8726 #endif 8727 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8728 PHYMOD_SYMBOL_FLAG_REGISTER, 8729 "SC_X1_SPD_OVRR1_5r", 8730 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8731 "SC_X1_SPEED_OVERRIDE1_OVERRIDE_5", 8732 NULL, 8733 #endif 8734 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8735 0x0, /* 0 */ 8736 0, 8737 #endif 8738 }, 8739 { 8740 BCMI_TSCF_XGXS_SC_X1_SPD_OVRR2_SPDr, 8741 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8742 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 8743 BCMI_TSCF_XGXS_SC_X1_SPD_OVRR2_SPDr_fields, 8744 #else 8745 0, 8746 #endif 8747 #endif 8748 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8749 PHYMOD_SYMBOL_FLAG_REGISTER, 8750 "SC_X1_SPD_OVRR2_SPDr", 8751 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8752 "SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED", 8753 NULL, 8754 #endif 8755 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8756 0xff00, /* 65280 */ 8757 0, 8758 #endif 8759 }, 8760 { 8761 BCMI_TSCF_XGXS_SC_X1_SPD_OVRR2_0r, 8762 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8763 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 8764 BCMI_TSCF_XGXS_SC_X1_SPD_OVRR2_0r_fields, 8765 #else 8766 0, 8767 #endif 8768 #endif 8769 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8770 PHYMOD_SYMBOL_FLAG_REGISTER, 8771 "SC_X1_SPD_OVRR2_0r", 8772 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8773 "SC_X1_SPEED_OVERRIDE2_OVERRIDE_0", 8774 NULL, 8775 #endif 8776 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8777 0x0, /* 0 */ 8778 0, 8779 #endif 8780 }, 8781 { 8782 BCMI_TSCF_XGXS_SC_X1_SPD_OVRR2_1r, 8783 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8784 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 8785 BCMI_TSCF_XGXS_SC_X1_SPD_OVRR2_1r_fields, 8786 #else 8787 0, 8788 #endif 8789 #endif 8790 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8791 PHYMOD_SYMBOL_FLAG_REGISTER, 8792 "SC_X1_SPD_OVRR2_1r", 8793 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8794 "SC_X1_SPEED_OVERRIDE2_OVERRIDE_1", 8795 NULL, 8796 #endif 8797 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8798 0x0, /* 0 */ 8799 0, 8800 #endif 8801 }, 8802 { 8803 BCMI_TSCF_XGXS_SC_X1_SPD_OVRR2_2r, 8804 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8805 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 8806 BCMI_TSCF_XGXS_SC_X1_SPD_OVRR2_2r_fields, 8807 #else 8808 0, 8809 #endif 8810 #endif 8811 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8812 PHYMOD_SYMBOL_FLAG_REGISTER, 8813 "SC_X1_SPD_OVRR2_2r", 8814 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8815 "SC_X1_SPEED_OVERRIDE2_OVERRIDE_2", 8816 NULL, 8817 #endif 8818 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8819 0x0, /* 0 */ 8820 0, 8821 #endif 8822 }, 8823 { 8824 BCMI_TSCF_XGXS_SC_X1_SPD_OVRR2_3r, 8825 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8826 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 8827 BCMI_TSCF_XGXS_SC_X1_SPD_OVRR2_3r_fields, 8828 #else 8829 0, 8830 #endif 8831 #endif 8832 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8833 PHYMOD_SYMBOL_FLAG_REGISTER, 8834 "SC_X1_SPD_OVRR2_3r", 8835 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8836 "SC_X1_SPEED_OVERRIDE2_OVERRIDE_3", 8837 NULL, 8838 #endif 8839 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8840 0x0, /* 0 */ 8841 0, 8842 #endif 8843 }, 8844 { 8845 BCMI_TSCF_XGXS_SC_X1_SPD_OVRR2_4r, 8846 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8847 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 8848 BCMI_TSCF_XGXS_SC_X1_SPD_OVRR2_4r_fields, 8849 #else 8850 0, 8851 #endif 8852 #endif 8853 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8854 PHYMOD_SYMBOL_FLAG_REGISTER, 8855 "SC_X1_SPD_OVRR2_4r", 8856 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8857 "SC_X1_SPEED_OVERRIDE2_OVERRIDE_4", 8858 NULL, 8859 #endif 8860 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8861 0x0, /* 0 */ 8862 0, 8863 #endif 8864 }, 8865 { 8866 BCMI_TSCF_XGXS_SC_X1_SPD_OVRR2_5r, 8867 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8868 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 8869 BCMI_TSCF_XGXS_SC_X1_SPD_OVRR2_5r_fields, 8870 #else 8871 0, 8872 #endif 8873 #endif 8874 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8875 PHYMOD_SYMBOL_FLAG_REGISTER, 8876 "SC_X1_SPD_OVRR2_5r", 8877 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8878 "SC_X1_SPEED_OVERRIDE2_OVERRIDE_5", 8879 NULL, 8880 #endif 8881 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8882 0x0, /* 0 */ 8883 0, 8884 #endif 8885 }, 8886 { 8887 BCMI_TSCF_XGXS_SC_X1_SPD_OVRR3_SPDr, 8888 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8889 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 8890 BCMI_TSCF_XGXS_SC_X1_SPD_OVRR3_SPDr_fields, 8891 #else 8892 0, 8893 #endif 8894 #endif 8895 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8896 PHYMOD_SYMBOL_FLAG_REGISTER, 8897 "SC_X1_SPD_OVRR3_SPDr", 8898 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8899 "SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED", 8900 NULL, 8901 #endif 8902 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8903 0xff00, /* 65280 */ 8904 0, 8905 #endif 8906 }, 8907 { 8908 BCMI_TSCF_XGXS_SC_X1_SPD_OVRR3_0r, 8909 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8910 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 8911 BCMI_TSCF_XGXS_SC_X1_SPD_OVRR3_0r_fields, 8912 #else 8913 0, 8914 #endif 8915 #endif 8916 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8917 PHYMOD_SYMBOL_FLAG_REGISTER, 8918 "SC_X1_SPD_OVRR3_0r", 8919 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8920 "SC_X1_SPEED_OVERRIDE3_OVERRIDE_0", 8921 NULL, 8922 #endif 8923 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8924 0x0, /* 0 */ 8925 0, 8926 #endif 8927 }, 8928 { 8929 BCMI_TSCF_XGXS_SC_X1_SPD_OVRR3_1r, 8930 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8931 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 8932 BCMI_TSCF_XGXS_SC_X1_SPD_OVRR3_1r_fields, 8933 #else 8934 0, 8935 #endif 8936 #endif 8937 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8938 PHYMOD_SYMBOL_FLAG_REGISTER, 8939 "SC_X1_SPD_OVRR3_1r", 8940 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8941 "SC_X1_SPEED_OVERRIDE3_OVERRIDE_1", 8942 NULL, 8943 #endif 8944 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8945 0x0, /* 0 */ 8946 0, 8947 #endif 8948 }, 8949 { 8950 BCMI_TSCF_XGXS_SC_X1_SPD_OVRR3_2r, 8951 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8952 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 8953 BCMI_TSCF_XGXS_SC_X1_SPD_OVRR3_2r_fields, 8954 #else 8955 0, 8956 #endif 8957 #endif 8958 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8959 PHYMOD_SYMBOL_FLAG_REGISTER, 8960 "SC_X1_SPD_OVRR3_2r", 8961 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8962 "SC_X1_SPEED_OVERRIDE3_OVERRIDE_2", 8963 NULL, 8964 #endif 8965 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8966 0x0, /* 0 */ 8967 0, 8968 #endif 8969 }, 8970 { 8971 BCMI_TSCF_XGXS_SC_X1_SPD_OVRR3_3r, 8972 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8973 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 8974 BCMI_TSCF_XGXS_SC_X1_SPD_OVRR3_3r_fields, 8975 #else 8976 0, 8977 #endif 8978 #endif 8979 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8980 PHYMOD_SYMBOL_FLAG_REGISTER, 8981 "SC_X1_SPD_OVRR3_3r", 8982 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8983 "SC_X1_SPEED_OVERRIDE3_OVERRIDE_3", 8984 NULL, 8985 #endif 8986 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8987 0x0, /* 0 */ 8988 0, 8989 #endif 8990 }, 8991 { 8992 BCMI_TSCF_XGXS_SC_X1_SPD_OVRR3_4r, 8993 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8994 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 8995 BCMI_TSCF_XGXS_SC_X1_SPD_OVRR3_4r_fields, 8996 #else 8997 0, 8998 #endif 8999 #endif 9000 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9001 PHYMOD_SYMBOL_FLAG_REGISTER, 9002 "SC_X1_SPD_OVRR3_4r", 9003 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9004 "SC_X1_SPEED_OVERRIDE3_OVERRIDE_4", 9005 NULL, 9006 #endif 9007 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9008 0x0, /* 0 */ 9009 0, 9010 #endif 9011 }, 9012 { 9013 BCMI_TSCF_XGXS_SC_X1_SPD_OVRR3_5r, 9014 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9015 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 9016 BCMI_TSCF_XGXS_SC_X1_SPD_OVRR3_5r_fields, 9017 #else 9018 0, 9019 #endif 9020 #endif 9021 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9022 PHYMOD_SYMBOL_FLAG_REGISTER, 9023 "SC_X1_SPD_OVRR3_5r", 9024 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9025 "SC_X1_SPEED_OVERRIDE3_OVERRIDE_5", 9026 NULL, 9027 #endif 9028 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9029 0x0, /* 0 */ 9030 0, 9031 #endif 9032 }, 9033 { 9034 BCMI_TSCF_XGXS_RX_X1_FEC_ALGN_FSM_STr, 9035 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9036 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 9037 BCMI_TSCF_XGXS_RX_X1_FEC_ALGN_FSM_STr_fields, 9038 #else 9039 0, 9040 #endif 9041 #endif 9042 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9043 PHYMOD_SYMBOL_FLAG_REGISTER, 9044 "RX_X1_FEC_ALGN_FSM_STr", 9045 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9046 "RX_X1_STATUS0_FEC_ALGN_FSM_STATE", 9047 NULL, 9048 #endif 9049 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9050 0x8, /* 8 */ 9051 0, 9052 #endif 9053 }, 9054 { 9055 BCMI_TSCF_XGXS_RX_X1_CL91_RXP_STSr, 9056 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9057 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 9058 BCMI_TSCF_XGXS_RX_X1_CL91_RXP_STSr_fields, 9059 #else 9060 0, 9061 #endif 9062 #endif 9063 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9064 PHYMOD_SYMBOL_FLAG_REGISTER, 9065 "RX_X1_CL91_RXP_STSr", 9066 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9067 "RX_X1_STATUS0_CL91_RXP_STATUS", 9068 NULL, 9069 #endif 9070 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9071 0x600, /* 1536 */ 9072 0, 9073 #endif 9074 }, 9075 { 9076 BCMI_TSCF_XGXS_RX_X1_FEC_CORR_CTR0r, 9077 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9078 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 9079 BCMI_TSCF_XGXS_RX_X1_FEC_CORR_CTR0r_fields, 9080 #else 9081 0, 9082 #endif 9083 #endif 9084 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9085 PHYMOD_SYMBOL_FLAG_REGISTER, 9086 "RX_X1_FEC_CORR_CTR0r", 9087 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9088 "RX_X1_STATUS0_FEC_CORRECTED_COUNTER_0", 9089 NULL, 9090 #endif 9091 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9092 0x0, /* 0 */ 9093 0, 9094 #endif 9095 }, 9096 { 9097 BCMI_TSCF_XGXS_RX_X1_FEC_CORR_CTR1r, 9098 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9099 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 9100 BCMI_TSCF_XGXS_RX_X1_FEC_CORR_CTR1r_fields, 9101 #else 9102 0, 9103 #endif 9104 #endif 9105 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9106 PHYMOD_SYMBOL_FLAG_REGISTER, 9107 "RX_X1_FEC_CORR_CTR1r", 9108 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9109 "RX_X1_STATUS0_FEC_CORRECTED_COUNTER_1", 9110 NULL, 9111 #endif 9112 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9113 0x0, /* 0 */ 9114 0, 9115 #endif 9116 }, 9117 { 9118 BCMI_TSCF_XGXS_RX_X1_FEC_UNCORR_CTR0r, 9119 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9120 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 9121 BCMI_TSCF_XGXS_RX_X1_FEC_UNCORR_CTR0r_fields, 9122 #else 9123 0, 9124 #endif 9125 #endif 9126 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9127 PHYMOD_SYMBOL_FLAG_REGISTER, 9128 "RX_X1_FEC_UNCORR_CTR0r", 9129 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9130 "RX_X1_STATUS0_FEC_UNCORRECTED_COUNTER_0", 9131 NULL, 9132 #endif 9133 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9134 0x0, /* 0 */ 9135 0, 9136 #endif 9137 }, 9138 { 9139 BCMI_TSCF_XGXS_RX_X1_FEC_UNCORR_CTR1r, 9140 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9141 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 9142 BCMI_TSCF_XGXS_RX_X1_FEC_UNCORR_CTR1r_fields, 9143 #else 9144 0, 9145 #endif 9146 #endif 9147 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9148 PHYMOD_SYMBOL_FLAG_REGISTER, 9149 "RX_X1_FEC_UNCORR_CTR1r", 9150 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9151 "RX_X1_STATUS0_FEC_UNCORRECTED_COUNTER_1", 9152 NULL, 9153 #endif 9154 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9155 0x0, /* 0 */ 9156 0, 9157 #endif 9158 }, 9159 { 9160 BCMI_TSCF_XGXS_RX_X1_FEC_BIT_ERR_CTR0r, 9161 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9162 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 9163 BCMI_TSCF_XGXS_RX_X1_FEC_BIT_ERR_CTR0r_fields, 9164 #else 9165 0, 9166 #endif 9167 #endif 9168 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9169 PHYMOD_SYMBOL_FLAG_REGISTER, 9170 "RX_X1_FEC_BIT_ERR_CTR0r", 9171 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9172 "RX_X1_STATUS0_FEC_BIT_ERROR_COUNTER_0", 9173 NULL, 9174 #endif 9175 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9176 0x0, /* 0 */ 9177 0, 9178 #endif 9179 }, 9180 { 9181 BCMI_TSCF_XGXS_RX_X1_FEC_BIT_ERR_CTR1r, 9182 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9183 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 9184 BCMI_TSCF_XGXS_RX_X1_FEC_BIT_ERR_CTR1r_fields, 9185 #else 9186 0, 9187 #endif 9188 #endif 9189 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9190 PHYMOD_SYMBOL_FLAG_REGISTER, 9191 "RX_X1_FEC_BIT_ERR_CTR1r", 9192 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9193 "RX_X1_STATUS0_FEC_BIT_ERROR_COUNTER_1", 9194 NULL, 9195 #endif 9196 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9197 0x0, /* 0 */ 9198 0, 9199 #endif 9200 }, 9201 { 9202 BCMI_TSCF_XGXS_TX_X2_MLD_SWP_CNTr, 9203 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9204 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 9205 BCMI_TSCF_XGXS_TX_X2_MLD_SWP_CNTr_fields, 9206 #else 9207 0, 9208 #endif 9209 #endif 9210 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9211 PHYMOD_SYMBOL_FLAG_REGISTER, 9212 "TX_X2_MLD_SWP_CNTr", 9213 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9214 "TX_X2_CONTROL0_MLD_SWAP_COUNT", 9215 NULL, 9216 #endif 9217 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9218 0xfffc, /* 65532 */ 9219 0, 9220 #endif 9221 }, 9222 { 9223 BCMI_TSCF_XGXS_TX_X2_CL82_0r, 9224 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9225 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 9226 BCMI_TSCF_XGXS_TX_X2_CL82_0r_fields, 9227 #else 9228 0, 9229 #endif 9230 #endif 9231 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9232 PHYMOD_SYMBOL_FLAG_REGISTER, 9233 "TX_X2_CL82_0r", 9234 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9235 "TX_X2_CONTROL0_CL82_0", 9236 NULL, 9237 #endif 9238 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9239 0x70, /* 112 */ 9240 0, 9241 #endif 9242 }, 9243 { 9244 BCMI_TSCF_XGXS_TX_X2_CL82_TX_STS0r, 9245 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9246 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 9247 BCMI_TSCF_XGXS_TX_X2_CL82_TX_STS0r_fields, 9248 #else 9249 0, 9250 #endif 9251 #endif 9252 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9253 PHYMOD_SYMBOL_FLAG_REGISTER, 9254 "TX_X2_CL82_TX_STS0r", 9255 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9256 "TX_X2_STATUS0_CL82_TX_STATUS_0", 9257 NULL, 9258 #endif 9259 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9260 0x0, /* 0 */ 9261 0, 9262 #endif 9263 }, 9264 { 9265 BCMI_TSCF_XGXS_TX_X2_CL82_TX_STS1r, 9266 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9267 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 9268 BCMI_TSCF_XGXS_TX_X2_CL82_TX_STS1r_fields, 9269 #else 9270 0, 9271 #endif 9272 #endif 9273 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9274 PHYMOD_SYMBOL_FLAG_REGISTER, 9275 "TX_X2_CL82_TX_STS1r", 9276 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9277 "TX_X2_STATUS0_CL82_TX_STATUS_1", 9278 NULL, 9279 #endif 9280 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9281 0x0, /* 0 */ 9282 0, 9283 #endif 9284 }, 9285 { 9286 BCMI_TSCF_XGXS_RX_X2_MISC0r, 9287 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9288 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 9289 BCMI_TSCF_XGXS_RX_X2_MISC0r_fields, 9290 #else 9291 0, 9292 #endif 9293 #endif 9294 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9295 PHYMOD_SYMBOL_FLAG_REGISTER, 9296 "RX_X2_MISC0r", 9297 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9298 "RX_X2_CONTROL0_MISC_0", 9299 NULL, 9300 #endif 9301 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9302 0x0, /* 0 */ 9303 0, 9304 #endif 9305 }, 9306 { 9307 BCMI_TSCF_XGXS_RX_X2_MISC1r, 9308 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9309 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 9310 BCMI_TSCF_XGXS_RX_X2_MISC1r_fields, 9311 #else 9312 0, 9313 #endif 9314 #endif 9315 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9316 PHYMOD_SYMBOL_FLAG_REGISTER, 9317 "RX_X2_MISC1r", 9318 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9319 "RX_X2_CONTROL0_MISC_1", 9320 NULL, 9321 #endif 9322 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9323 0x203, /* 515 */ 9324 0, 9325 #endif 9326 }, 9327 { 9328 BCMI_TSCF_XGXS_CL82_RX_LIVE_STSr, 9329 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9330 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 9331 BCMI_TSCF_XGXS_CL82_RX_LIVE_STSr_fields, 9332 #else 9333 0, 9334 #endif 9335 #endif 9336 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9337 PHYMOD_SYMBOL_FLAG_REGISTER, 9338 "CL82_RX_LIVE_STSr", 9339 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9340 "CL82_RX_LIVE_STATUS", 9341 NULL, 9342 #endif 9343 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9344 0x2000, /* 8192 */ 9345 0, 9346 #endif 9347 }, 9348 { 9349 BCMI_TSCF_XGXS_CL82_RX_LATCH_STSr, 9350 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9351 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 9352 BCMI_TSCF_XGXS_CL82_RX_LATCH_STSr_fields, 9353 #else 9354 0, 9355 #endif 9356 #endif 9357 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9358 PHYMOD_SYMBOL_FLAG_REGISTER, 9359 "CL82_RX_LATCH_STSr", 9360 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9361 "CL82_RX_LATCHED_STATUS", 9362 NULL, 9363 #endif 9364 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9365 0x1, /* 1 */ 9366 0, 9367 #endif 9368 }, 9369 { 9370 BCMI_TSCF_XGXS_CL82_BER_LOr, 9371 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9372 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 9373 BCMI_TSCF_XGXS_CL82_BER_LOr_fields, 9374 #else 9375 0, 9376 #endif 9377 #endif 9378 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9379 PHYMOD_SYMBOL_FLAG_REGISTER, 9380 "CL82_BER_LOr", 9381 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9382 NULL, 9383 NULL, 9384 #endif 9385 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9386 0x0, /* 0 */ 9387 0, 9388 #endif 9389 }, 9390 { 9391 BCMI_TSCF_XGXS_CL82_BER_HOr, 9392 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9393 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 9394 BCMI_TSCF_XGXS_CL82_BER_HOr_fields, 9395 #else 9396 0, 9397 #endif 9398 #endif 9399 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9400 PHYMOD_SYMBOL_FLAG_REGISTER, 9401 "CL82_BER_HOr", 9402 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9403 NULL, 9404 NULL, 9405 #endif 9406 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9407 0x0, /* 0 */ 9408 0, 9409 #endif 9410 }, 9411 { 9412 BCMI_TSCF_XGXS_CL82_ERRED_BLKS_HOr, 9413 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9414 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 9415 BCMI_TSCF_XGXS_CL82_ERRED_BLKS_HOr_fields, 9416 #else 9417 0, 9418 #endif 9419 #endif 9420 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9421 PHYMOD_SYMBOL_FLAG_REGISTER, 9422 "CL82_ERRED_BLKS_HOr", 9423 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9424 "CL82_ERRORED_BLOCKS_HO", 9425 NULL, 9426 #endif 9427 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9428 0x8000, /* 32768 */ 9429 0, 9430 #endif 9431 }, 9432 { 9433 BCMI_TSCF_XGXS_PMD_X4_CTLr, 9434 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9435 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 9436 BCMI_TSCF_XGXS_PMD_X4_CTLr_fields, 9437 #else 9438 0, 9439 #endif 9440 #endif 9441 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9442 PHYMOD_SYMBOL_FLAG_REGISTER, 9443 "PMD_X4_CTLr", 9444 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9445 "PMD_X4_CONTROL", 9446 NULL, 9447 #endif 9448 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9449 0x0, /* 0 */ 9450 0, 9451 #endif 9452 }, 9453 { 9454 BCMI_TSCF_XGXS_PMD_X4_MODEr, 9455 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9456 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 9457 BCMI_TSCF_XGXS_PMD_X4_MODEr_fields, 9458 #else 9459 0, 9460 #endif 9461 #endif 9462 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9463 PHYMOD_SYMBOL_FLAG_REGISTER, 9464 "PMD_X4_MODEr", 9465 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9466 NULL, 9467 NULL, 9468 #endif 9469 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9470 0x0, /* 0 */ 9471 0, 9472 #endif 9473 }, 9474 { 9475 BCMI_TSCF_XGXS_PMD_X4_STSr, 9476 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9477 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 9478 BCMI_TSCF_XGXS_PMD_X4_STSr_fields, 9479 #else 9480 0, 9481 #endif 9482 #endif 9483 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9484 PHYMOD_SYMBOL_FLAG_REGISTER, 9485 "PMD_X4_STSr", 9486 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9487 "PMD_X4_STATUS", 9488 NULL, 9489 #endif 9490 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9491 0x0, /* 0 */ 9492 0, 9493 #endif 9494 }, 9495 { 9496 BCMI_TSCF_XGXS_PMD_X4_LATCH_STSr, 9497 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9498 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 9499 BCMI_TSCF_XGXS_PMD_X4_LATCH_STSr_fields, 9500 #else 9501 0, 9502 #endif 9503 #endif 9504 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9505 PHYMOD_SYMBOL_FLAG_REGISTER, 9506 "PMD_X4_LATCH_STSr", 9507 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9508 "PMD_X4_LATCH_STATUS", 9509 NULL, 9510 #endif 9511 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9512 0x0, /* 0 */ 9513 0, 9514 #endif 9515 }, 9516 { 9517 BCMI_TSCF_XGXS_PMD_X4_OVRRr, 9518 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9519 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 9520 BCMI_TSCF_XGXS_PMD_X4_OVRRr_fields, 9521 #else 9522 0, 9523 #endif 9524 #endif 9525 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9526 PHYMOD_SYMBOL_FLAG_REGISTER, 9527 "PMD_X4_OVRRr", 9528 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9529 "PMD_X4_OVERRIDE", 9530 NULL, 9531 #endif 9532 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9533 0x0, /* 0 */ 9534 0, 9535 #endif 9536 }, 9537 { 9538 BCMI_TSCF_XGXS_PMD_X4_EEE_CTLr, 9539 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9540 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 9541 BCMI_TSCF_XGXS_PMD_X4_EEE_CTLr_fields, 9542 #else 9543 0, 9544 #endif 9545 #endif 9546 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9547 PHYMOD_SYMBOL_FLAG_REGISTER, 9548 "PMD_X4_EEE_CTLr", 9549 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9550 "PMD_X4_EEE_CONTROL", 9551 NULL, 9552 #endif 9553 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9554 0x0, /* 0 */ 9555 0, 9556 #endif 9557 }, 9558 { 9559 BCMI_TSCF_XGXS_PMD_X4_EEE_STSr, 9560 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9561 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 9562 BCMI_TSCF_XGXS_PMD_X4_EEE_STSr_fields, 9563 #else 9564 0, 9565 #endif 9566 #endif 9567 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9568 PHYMOD_SYMBOL_FLAG_REGISTER, 9569 "PMD_X4_EEE_STSr", 9570 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9571 "PMD_X4_EEE_STATUS", 9572 NULL, 9573 #endif 9574 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9575 0x0, /* 0 */ 9576 0, 9577 #endif 9578 }, 9579 { 9580 BCMI_TSCF_XGXS_SC_X4_CTLr, 9581 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9582 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 9583 BCMI_TSCF_XGXS_SC_X4_CTLr_fields, 9584 #else 9585 0, 9586 #endif 9587 #endif 9588 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9589 PHYMOD_SYMBOL_FLAG_REGISTER, 9590 "SC_X4_CTLr", 9591 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9592 "SC_X4_CONTROL_CONTROL", 9593 NULL, 9594 #endif 9595 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9596 0x0, /* 0 */ 9597 0, 9598 #endif 9599 }, 9600 { 9601 BCMI_TSCF_XGXS_SC_X4_STSr, 9602 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9603 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 9604 BCMI_TSCF_XGXS_SC_X4_STSr_fields, 9605 #else 9606 0, 9607 #endif 9608 #endif 9609 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9610 PHYMOD_SYMBOL_FLAG_REGISTER, 9611 "SC_X4_STSr", 9612 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9613 "SC_X4_CONTROL_STATUS", 9614 NULL, 9615 #endif 9616 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9617 0x0, /* 0 */ 9618 0, 9619 #endif 9620 }, 9621 { 9622 BCMI_TSCF_XGXS_SC_X4_ERRr, 9623 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9624 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 9625 BCMI_TSCF_XGXS_SC_X4_ERRr_fields, 9626 #else 9627 0, 9628 #endif 9629 #endif 9630 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9631 PHYMOD_SYMBOL_FLAG_REGISTER, 9632 "SC_X4_ERRr", 9633 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9634 "SC_X4_CONTROL_ERROR", 9635 NULL, 9636 #endif 9637 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9638 0x0, /* 0 */ 9639 0, 9640 #endif 9641 }, 9642 { 9643 BCMI_TSCF_XGXS_SC_X4_DBGr, 9644 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9645 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 9646 BCMI_TSCF_XGXS_SC_X4_DBGr_fields, 9647 #else 9648 0, 9649 #endif 9650 #endif 9651 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9652 PHYMOD_SYMBOL_FLAG_REGISTER, 9653 "SC_X4_DBGr", 9654 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9655 "SC_X4_CONTROL_DEBUG", 9656 NULL, 9657 #endif 9658 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9659 0x8000, /* 32768 */ 9660 0, 9661 #endif 9662 }, 9663 { 9664 BCMI_TSCF_XGXS_SC_X4_LN_NUM_OVRRr, 9665 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9666 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 9667 BCMI_TSCF_XGXS_SC_X4_LN_NUM_OVRRr_fields, 9668 #else 9669 0, 9670 #endif 9671 #endif 9672 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9673 PHYMOD_SYMBOL_FLAG_REGISTER, 9674 "SC_X4_LN_NUM_OVRRr", 9675 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9676 "SC_X4_CONTROL_LANE_NUM_OVERRIDE", 9677 NULL, 9678 #endif 9679 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9680 0x0, /* 0 */ 9681 0, 9682 #endif 9683 }, 9684 { 9685 BCMI_TSCF_XGXS_SC_X4_BYPASSr, 9686 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9687 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 9688 BCMI_TSCF_XGXS_SC_X4_BYPASSr_fields, 9689 #else 9690 0, 9691 #endif 9692 #endif 9693 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9694 PHYMOD_SYMBOL_FLAG_REGISTER, 9695 "SC_X4_BYPASSr", 9696 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9697 "SC_X4_CONTROL_BYPASS", 9698 NULL, 9699 #endif 9700 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9701 0x0, /* 0 */ 9702 0, 9703 #endif 9704 }, 9705 { 9706 BCMI_TSCF_XGXS_SC_X4_SPARE0r, 9707 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9708 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 9709 BCMI_TSCF_XGXS_SC_X4_SPARE0r_fields, 9710 #else 9711 0, 9712 #endif 9713 #endif 9714 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9715 PHYMOD_SYMBOL_FLAG_REGISTER, 9716 "SC_X4_SPARE0r", 9717 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9718 "SC_X4_CONTROL_SPARE0", 9719 NULL, 9720 #endif 9721 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9722 0x0, /* 0 */ 9723 0, 9724 #endif 9725 }, 9726 { 9727 BCMI_TSCF_XGXS_SC_X4_SPARE1r, 9728 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9729 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 9730 BCMI_TSCF_XGXS_SC_X4_SPARE1r_fields, 9731 #else 9732 0, 9733 #endif 9734 #endif 9735 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9736 PHYMOD_SYMBOL_FLAG_REGISTER, 9737 "SC_X4_SPARE1r", 9738 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9739 "SC_X4_CONTROL_SPARE1", 9740 NULL, 9741 #endif 9742 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9743 0x0, /* 0 */ 9744 0, 9745 #endif 9746 }, 9747 { 9748 BCMI_TSCF_XGXS_SC_X4_FLD_OVRR_EN0_TYPEr, 9749 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9750 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 9751 BCMI_TSCF_XGXS_SC_X4_FLD_OVRR_EN0_TYPEr_fields, 9752 #else 9753 0, 9754 #endif 9755 #endif 9756 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9757 PHYMOD_SYMBOL_FLAG_REGISTER, 9758 "SC_X4_FLD_OVRR_EN0_TYPEr", 9759 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9760 "SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE", 9761 NULL, 9762 #endif 9763 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9764 0x0, /* 0 */ 9765 0, 9766 #endif 9767 }, 9768 { 9769 BCMI_TSCF_XGXS_SC_X4_FLD_OVRR_EN1_TYPEr, 9770 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9771 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 9772 BCMI_TSCF_XGXS_SC_X4_FLD_OVRR_EN1_TYPEr_fields, 9773 #else 9774 0, 9775 #endif 9776 #endif 9777 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9778 PHYMOD_SYMBOL_FLAG_REGISTER, 9779 "SC_X4_FLD_OVRR_EN1_TYPEr", 9780 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9781 "SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE", 9782 NULL, 9783 #endif 9784 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9785 0x0, /* 0 */ 9786 0, 9787 #endif 9788 }, 9789 { 9790 BCMI_TSCF_XGXS_SC_X4_RSLVD_SPDr, 9791 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9792 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 9793 BCMI_TSCF_XGXS_SC_X4_RSLVD_SPDr_fields, 9794 #else 9795 0, 9796 #endif 9797 #endif 9798 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9799 PHYMOD_SYMBOL_FLAG_REGISTER, 9800 "SC_X4_RSLVD_SPDr", 9801 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9802 "SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED", 9803 NULL, 9804 #endif 9805 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9806 0xff00, /* 65280 */ 9807 0, 9808 #endif 9809 }, 9810 { 9811 BCMI_TSCF_XGXS_SC_X4_RSLVD0r, 9812 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9813 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 9814 BCMI_TSCF_XGXS_SC_X4_RSLVD0r_fields, 9815 #else 9816 0, 9817 #endif 9818 #endif 9819 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9820 PHYMOD_SYMBOL_FLAG_REGISTER, 9821 "SC_X4_RSLVD0r", 9822 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9823 "SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0", 9824 NULL, 9825 #endif 9826 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9827 0x0, /* 0 */ 9828 0, 9829 #endif 9830 }, 9831 { 9832 BCMI_TSCF_XGXS_SC_X4_RSLVD1r, 9833 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9834 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 9835 BCMI_TSCF_XGXS_SC_X4_RSLVD1r_fields, 9836 #else 9837 0, 9838 #endif 9839 #endif 9840 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9841 PHYMOD_SYMBOL_FLAG_REGISTER, 9842 "SC_X4_RSLVD1r", 9843 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9844 "SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1", 9845 NULL, 9846 #endif 9847 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9848 0x0, /* 0 */ 9849 0, 9850 #endif 9851 }, 9852 { 9853 BCMI_TSCF_XGXS_SC_X4_RSLVD2r, 9854 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9855 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 9856 BCMI_TSCF_XGXS_SC_X4_RSLVD2r_fields, 9857 #else 9858 0, 9859 #endif 9860 #endif 9861 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9862 PHYMOD_SYMBOL_FLAG_REGISTER, 9863 "SC_X4_RSLVD2r", 9864 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9865 "SC_X4_FINAL_CONFIG_STATUS_RESOLVED_2", 9866 NULL, 9867 #endif 9868 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9869 0x0, /* 0 */ 9870 0, 9871 #endif 9872 }, 9873 { 9874 BCMI_TSCF_XGXS_SC_X4_RSLVD3r, 9875 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9876 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 9877 BCMI_TSCF_XGXS_SC_X4_RSLVD3r_fields, 9878 #else 9879 0, 9880 #endif 9881 #endif 9882 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9883 PHYMOD_SYMBOL_FLAG_REGISTER, 9884 "SC_X4_RSLVD3r", 9885 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9886 "SC_X4_FINAL_CONFIG_STATUS_RESOLVED_3", 9887 NULL, 9888 #endif 9889 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9890 0x0, /* 0 */ 9891 0, 9892 #endif 9893 }, 9894 { 9895 BCMI_TSCF_XGXS_SC_X4_RSLVD4r, 9896 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9897 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 9898 BCMI_TSCF_XGXS_SC_X4_RSLVD4r_fields, 9899 #else 9900 0, 9901 #endif 9902 #endif 9903 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9904 PHYMOD_SYMBOL_FLAG_REGISTER, 9905 "SC_X4_RSLVD4r", 9906 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9907 "SC_X4_FINAL_CONFIG_STATUS_RESOLVED_4", 9908 NULL, 9909 #endif 9910 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9911 0x0, /* 0 */ 9912 0, 9913 #endif 9914 }, 9915 { 9916 BCMI_TSCF_XGXS_SC_X4_RSLVD5r, 9917 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9918 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 9919 BCMI_TSCF_XGXS_SC_X4_RSLVD5r_fields, 9920 #else 9921 0, 9922 #endif 9923 #endif 9924 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9925 PHYMOD_SYMBOL_FLAG_REGISTER, 9926 "SC_X4_RSLVD5r", 9927 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9928 "SC_X4_FINAL_CONFIG_STATUS_RESOLVED_5", 9929 NULL, 9930 #endif 9931 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9932 0x0, /* 0 */ 9933 0, 9934 #endif 9935 }, 9936 { 9937 BCMI_TSCF_XGXS_SC_X4_FEC_STSr, 9938 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9939 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 9940 BCMI_TSCF_XGXS_SC_X4_FEC_STSr_fields, 9941 #else 9942 0, 9943 #endif 9944 #endif 9945 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9946 PHYMOD_SYMBOL_FLAG_REGISTER, 9947 "SC_X4_FEC_STSr", 9948 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9949 "SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS", 9950 NULL, 9951 #endif 9952 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9953 0x0, /* 0 */ 9954 0, 9955 #endif 9956 }, 9957 { 9958 BCMI_TSCF_XGXS_TX_X4_CRED0r, 9959 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9960 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 9961 BCMI_TSCF_XGXS_TX_X4_CRED0r_fields, 9962 #else 9963 0, 9964 #endif 9965 #endif 9966 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9967 PHYMOD_SYMBOL_FLAG_REGISTER, 9968 "TX_X4_CRED0r", 9969 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9970 "TX_X4_CREDIT0_CREDIT0", 9971 NULL, 9972 #endif 9973 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9974 0x0, /* 0 */ 9975 0, 9976 #endif 9977 }, 9978 { 9979 BCMI_TSCF_XGXS_TX_X4_CRED1r, 9980 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9981 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 9982 BCMI_TSCF_XGXS_TX_X4_CRED1r_fields, 9983 #else 9984 0, 9985 #endif 9986 #endif 9987 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9988 PHYMOD_SYMBOL_FLAG_REGISTER, 9989 "TX_X4_CRED1r", 9990 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9991 "TX_X4_CREDIT0_CREDIT1", 9992 NULL, 9993 #endif 9994 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9995 0x0, /* 0 */ 9996 0, 9997 #endif 9998 }, 9999 { 10000 BCMI_TSCF_XGXS_TX_X4_LOOPCNTr, 10001 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10002 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 10003 BCMI_TSCF_XGXS_TX_X4_LOOPCNTr_fields, 10004 #else 10005 0, 10006 #endif 10007 #endif 10008 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10009 PHYMOD_SYMBOL_FLAG_REGISTER, 10010 "TX_X4_LOOPCNTr", 10011 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10012 "TX_X4_CREDIT0_LOOPCNT", 10013 NULL, 10014 #endif 10015 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10016 0x0, /* 0 */ 10017 0, 10018 #endif 10019 }, 10020 { 10021 BCMI_TSCF_XGXS_TX_X4_MAC_CREDGENCNTr, 10022 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10023 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 10024 BCMI_TSCF_XGXS_TX_X4_MAC_CREDGENCNTr_fields, 10025 #else 10026 0, 10027 #endif 10028 #endif 10029 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10030 PHYMOD_SYMBOL_FLAG_REGISTER, 10031 "TX_X4_MAC_CREDGENCNTr", 10032 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10033 "TX_X4_CREDIT0_MAC_CREDITGENCNT", 10034 NULL, 10035 #endif 10036 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10037 0x0, /* 0 */ 10038 0, 10039 #endif 10040 }, 10041 { 10042 BCMI_TSCF_XGXS_TX_X4_ENC0r, 10043 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10044 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 10045 BCMI_TSCF_XGXS_TX_X4_ENC0r_fields, 10046 #else 10047 0, 10048 #endif 10049 #endif 10050 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10051 PHYMOD_SYMBOL_FLAG_REGISTER, 10052 "TX_X4_ENC0r", 10053 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10054 "TX_X4_CONTROL0_ENCODE_0", 10055 NULL, 10056 #endif 10057 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10058 0x1800, /* 6144 */ 10059 0, 10060 #endif 10061 }, 10062 { 10063 BCMI_TSCF_XGXS_TX_X4_MISCr, 10064 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10065 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 10066 BCMI_TSCF_XGXS_TX_X4_MISCr_fields, 10067 #else 10068 0, 10069 #endif 10070 #endif 10071 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10072 PHYMOD_SYMBOL_FLAG_REGISTER, 10073 "TX_X4_MISCr", 10074 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10075 "TX_X4_CONTROL0_MISC", 10076 NULL, 10077 #endif 10078 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10079 0x1c0, /* 448 */ 10080 0, 10081 #endif 10082 }, 10083 { 10084 BCMI_TSCF_XGXS_TX_X4_CL36_CTLr, 10085 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10086 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 10087 BCMI_TSCF_XGXS_TX_X4_CL36_CTLr_fields, 10088 #else 10089 0, 10090 #endif 10091 #endif 10092 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10093 PHYMOD_SYMBOL_FLAG_REGISTER, 10094 "TX_X4_CL36_CTLr", 10095 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10096 "TX_X4_CONTROL0_CL36TX_CONTROL", 10097 NULL, 10098 #endif 10099 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10100 0x0, /* 0 */ 10101 0, 10102 #endif 10103 }, 10104 { 10105 BCMI_TSCF_XGXS_TX_X4_ENC_STS0r, 10106 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10107 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 10108 BCMI_TSCF_XGXS_TX_X4_ENC_STS0r_fields, 10109 #else 10110 0, 10111 #endif 10112 #endif 10113 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10114 PHYMOD_SYMBOL_FLAG_REGISTER, 10115 "TX_X4_ENC_STS0r", 10116 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10117 "TX_X4_STATUS0_ENCODE_STATUS_0", 10118 NULL, 10119 #endif 10120 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10121 0x0, /* 0 */ 10122 0, 10123 #endif 10124 }, 10125 { 10126 BCMI_TSCF_XGXS_TX_X4_ENC_STS1r, 10127 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10128 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 10129 BCMI_TSCF_XGXS_TX_X4_ENC_STS1r_fields, 10130 #else 10131 0, 10132 #endif 10133 #endif 10134 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10135 PHYMOD_SYMBOL_FLAG_REGISTER, 10136 "TX_X4_ENC_STS1r", 10137 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10138 "TX_X4_STATUS0_ENCODE_STATUS_1", 10139 NULL, 10140 #endif 10141 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10142 0x0, /* 0 */ 10143 0, 10144 #endif 10145 }, 10146 { 10147 BCMI_TSCF_XGXS_TX_X4_PCS_STS_LIVEr, 10148 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10149 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 10150 BCMI_TSCF_XGXS_TX_X4_PCS_STS_LIVEr_fields, 10151 #else 10152 0, 10153 #endif 10154 #endif 10155 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10156 PHYMOD_SYMBOL_FLAG_REGISTER, 10157 "TX_X4_PCS_STS_LIVEr", 10158 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10159 "TX_X4_STATUS0_PCS_STATUS_LIVE", 10160 NULL, 10161 #endif 10162 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10163 0x0, /* 0 */ 10164 0, 10165 #endif 10166 }, 10167 { 10168 BCMI_TSCF_XGXS_TX_X4_PCS_STS_LATCHr, 10169 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10170 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 10171 BCMI_TSCF_XGXS_TX_X4_PCS_STS_LATCHr_fields, 10172 #else 10173 0, 10174 #endif 10175 #endif 10176 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10177 PHYMOD_SYMBOL_FLAG_REGISTER, 10178 "TX_X4_PCS_STS_LATCHr", 10179 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10180 "TX_X4_STATUS0_PCS_STATUS_LATCHED", 10181 NULL, 10182 #endif 10183 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10184 0x0, /* 0 */ 10185 0, 10186 #endif 10187 }, 10188 { 10189 BCMI_TSCF_XGXS_TX_X4_PMA_STSr, 10190 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10191 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 10192 BCMI_TSCF_XGXS_TX_X4_PMA_STSr_fields, 10193 #else 10194 0, 10195 #endif 10196 #endif 10197 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10198 PHYMOD_SYMBOL_FLAG_REGISTER, 10199 "TX_X4_PMA_STSr", 10200 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10201 "TX_X4_STATUS0_PMA_STATUS", 10202 NULL, 10203 #endif 10204 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10205 0x0, /* 0 */ 10206 0, 10207 #endif 10208 }, 10209 { 10210 BCMI_TSCF_XGXS_RX_X4_PCS_CTL0r, 10211 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10212 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 10213 BCMI_TSCF_XGXS_RX_X4_PCS_CTL0r_fields, 10214 #else 10215 0, 10216 #endif 10217 #endif 10218 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10219 PHYMOD_SYMBOL_FLAG_REGISTER, 10220 "RX_X4_PCS_CTL0r", 10221 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10222 "RX_X4_CONTROL0_PCS_CONTROL_0", 10223 NULL, 10224 #endif 10225 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10226 0x0, /* 0 */ 10227 0, 10228 #endif 10229 }, 10230 { 10231 BCMI_TSCF_XGXS_RX_X4_DEC_CTL0r, 10232 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10233 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 10234 BCMI_TSCF_XGXS_RX_X4_DEC_CTL0r_fields, 10235 #else 10236 0, 10237 #endif 10238 #endif 10239 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10240 PHYMOD_SYMBOL_FLAG_REGISTER, 10241 "RX_X4_DEC_CTL0r", 10242 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10243 "RX_X4_CONTROL0_DECODE_CONTROL_0", 10244 NULL, 10245 #endif 10246 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10247 0x2270, /* 8816 */ 10248 0, 10249 #endif 10250 }, 10251 { 10252 BCMI_TSCF_XGXS_RX_X4_BLKSYNC_CFGr, 10253 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10254 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 10255 BCMI_TSCF_XGXS_RX_X4_BLKSYNC_CFGr_fields, 10256 #else 10257 0, 10258 #endif 10259 #endif 10260 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10261 PHYMOD_SYMBOL_FLAG_REGISTER, 10262 "RX_X4_BLKSYNC_CFGr", 10263 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10264 "RX_X4_CONTROL0_BLKSYNC_CONFIG", 10265 NULL, 10266 #endif 10267 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10268 0x0, /* 0 */ 10269 0, 10270 #endif 10271 }, 10272 { 10273 BCMI_TSCF_XGXS_RX_X4_PMA_CTL0r, 10274 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10275 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 10276 BCMI_TSCF_XGXS_RX_X4_PMA_CTL0r_fields, 10277 #else 10278 0, 10279 #endif 10280 #endif 10281 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10282 PHYMOD_SYMBOL_FLAG_REGISTER, 10283 "RX_X4_PMA_CTL0r", 10284 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10285 "RX_X4_CONTROL0_PMA_CONTROL_0", 10286 NULL, 10287 #endif 10288 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10289 0x0, /* 0 */ 10290 0, 10291 #endif 10292 }, 10293 { 10294 BCMI_TSCF_XGXS_RX_X4_LNK_CTLr, 10295 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10296 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 10297 BCMI_TSCF_XGXS_RX_X4_LNK_CTLr_fields, 10298 #else 10299 0, 10300 #endif 10301 #endif 10302 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10303 PHYMOD_SYMBOL_FLAG_REGISTER, 10304 "RX_X4_LNK_CTLr", 10305 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10306 "RX_X4_CONTROL0_LINK_CONTROL", 10307 NULL, 10308 #endif 10309 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10310 0x0, /* 0 */ 10311 0, 10312 #endif 10313 }, 10314 { 10315 BCMI_TSCF_XGXS_RX_X4_DESKEW_MEM_CTLr, 10316 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10317 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 10318 BCMI_TSCF_XGXS_RX_X4_DESKEW_MEM_CTLr_fields, 10319 #else 10320 0, 10321 #endif 10322 #endif 10323 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10324 PHYMOD_SYMBOL_FLAG_REGISTER, 10325 "RX_X4_DESKEW_MEM_CTLr", 10326 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10327 "RX_X4_CONTROL0_DESKEW_MEM_CTRL", 10328 NULL, 10329 #endif 10330 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10331 0x0, /* 0 */ 10332 0, 10333 #endif 10334 }, 10335 { 10336 BCMI_TSCF_XGXS_RX_X4_FEC_MEM_CTLr, 10337 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10338 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 10339 BCMI_TSCF_XGXS_RX_X4_FEC_MEM_CTLr_fields, 10340 #else 10341 0, 10342 #endif 10343 #endif 10344 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10345 PHYMOD_SYMBOL_FLAG_REGISTER, 10346 "RX_X4_FEC_MEM_CTLr", 10347 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10348 "RX_X4_CONTROL0_FEC_MEM_CTRL", 10349 NULL, 10350 #endif 10351 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10352 0x0, /* 0 */ 10353 0, 10354 #endif 10355 }, 10356 { 10357 BCMI_TSCF_XGXS_RX_X4_CL36_CTLr, 10358 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10359 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 10360 BCMI_TSCF_XGXS_RX_X4_CL36_CTLr_fields, 10361 #else 10362 0, 10363 #endif 10364 #endif 10365 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10366 PHYMOD_SYMBOL_FLAG_REGISTER, 10367 "RX_X4_CL36_CTLr", 10368 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10369 "RX_X4_CONTROL0_CL36RX_CONTROL", 10370 NULL, 10371 #endif 10372 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10373 0x0, /* 0 */ 10374 0, 10375 #endif 10376 }, 10377 { 10378 BCMI_TSCF_XGXS_RX_X4_SYNCE_FRACTIONAL_DIVr, 10379 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10380 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 10381 BCMI_TSCF_XGXS_RX_X4_SYNCE_FRACTIONAL_DIVr_fields, 10382 #else 10383 0, 10384 #endif 10385 #endif 10386 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10387 PHYMOD_SYMBOL_FLAG_REGISTER, 10388 "RX_X4_SYNCE_FRACTIONAL_DIVr", 10389 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10390 "RX_X4_CONTROL0_SYNCE_FRACTIONAL_DIV", 10391 NULL, 10392 #endif 10393 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10394 0x14a0, /* 5280 */ 10395 0, 10396 #endif 10397 }, 10398 { 10399 BCMI_TSCF_XGXS_RX_X4_FEC0r, 10400 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10401 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 10402 BCMI_TSCF_XGXS_RX_X4_FEC0r_fields, 10403 #else 10404 0, 10405 #endif 10406 #endif 10407 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10408 PHYMOD_SYMBOL_FLAG_REGISTER, 10409 "RX_X4_FEC0r", 10410 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10411 "RX_X4_FEC_CONTROL_FEC_0", 10412 NULL, 10413 #endif 10414 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10415 0x4478, /* 17528 */ 10416 0, 10417 #endif 10418 }, 10419 { 10420 BCMI_TSCF_XGXS_RX_X4_FEC1r, 10421 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10422 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 10423 BCMI_TSCF_XGXS_RX_X4_FEC1r_fields, 10424 #else 10425 0, 10426 #endif 10427 #endif 10428 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10429 PHYMOD_SYMBOL_FLAG_REGISTER, 10430 "RX_X4_FEC1r", 10431 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10432 "RX_X4_FEC_CONTROL_FEC_1", 10433 NULL, 10434 #endif 10435 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10436 0x7828, /* 30760 */ 10437 0, 10438 #endif 10439 }, 10440 { 10441 BCMI_TSCF_XGXS_RX_X4_FEC2r, 10442 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10443 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 10444 BCMI_TSCF_XGXS_RX_X4_FEC2r_fields, 10445 #else 10446 0, 10447 #endif 10448 #endif 10449 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10450 PHYMOD_SYMBOL_FLAG_REGISTER, 10451 "RX_X4_FEC2r", 10452 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10453 "RX_X4_FEC_CONTROL_FEC_2", 10454 NULL, 10455 #endif 10456 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10457 0x0, /* 0 */ 10458 0, 10459 #endif 10460 }, 10461 { 10462 BCMI_TSCF_XGXS_RX_X4_FEC3r, 10463 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10464 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 10465 BCMI_TSCF_XGXS_RX_X4_FEC3r_fields, 10466 #else 10467 0, 10468 #endif 10469 #endif 10470 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10471 PHYMOD_SYMBOL_FLAG_REGISTER, 10472 "RX_X4_FEC3r", 10473 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10474 "RX_X4_FEC_CONTROL_FEC_3", 10475 NULL, 10476 #endif 10477 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10478 0x0, /* 0 */ 10479 0, 10480 #endif 10481 }, 10482 { 10483 BCMI_TSCF_XGXS_RX_X4_BLKSYNC_STSr, 10484 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10485 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 10486 BCMI_TSCF_XGXS_RX_X4_BLKSYNC_STSr_fields, 10487 #else 10488 0, 10489 #endif 10490 #endif 10491 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10492 PHYMOD_SYMBOL_FLAG_REGISTER, 10493 "RX_X4_BLKSYNC_STSr", 10494 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10495 "RX_X4_STATUS0_BLKSYNC_STATUS", 10496 NULL, 10497 #endif 10498 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10499 0x0, /* 0 */ 10500 0, 10501 #endif 10502 }, 10503 { 10504 BCMI_TSCF_XGXS_RX_X4_BLKSYNC_DBG0r, 10505 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10506 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 10507 BCMI_TSCF_XGXS_RX_X4_BLKSYNC_DBG0r_fields, 10508 #else 10509 0, 10510 #endif 10511 #endif 10512 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10513 PHYMOD_SYMBOL_FLAG_REGISTER, 10514 "RX_X4_BLKSYNC_DBG0r", 10515 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10516 "RX_X4_STATUS0_BLKSYNC_DBG0", 10517 NULL, 10518 #endif 10519 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10520 0x0, /* 0 */ 10521 0, 10522 #endif 10523 }, 10524 { 10525 BCMI_TSCF_XGXS_RX_X4_BLKSYNC_DBG1r, 10526 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10527 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 10528 BCMI_TSCF_XGXS_RX_X4_BLKSYNC_DBG1r_fields, 10529 #else 10530 0, 10531 #endif 10532 #endif 10533 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10534 PHYMOD_SYMBOL_FLAG_REGISTER, 10535 "RX_X4_BLKSYNC_DBG1r", 10536 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10537 "RX_X4_STATUS0_BLKSYNC_DBG1", 10538 NULL, 10539 #endif 10540 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10541 0x0, /* 0 */ 10542 0, 10543 #endif 10544 }, 10545 { 10546 BCMI_TSCF_XGXS_RX_X4_BLKSYNC_DBG2r, 10547 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10548 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 10549 BCMI_TSCF_XGXS_RX_X4_BLKSYNC_DBG2r_fields, 10550 #else 10551 0, 10552 #endif 10553 #endif 10554 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10555 PHYMOD_SYMBOL_FLAG_REGISTER, 10556 "RX_X4_BLKSYNC_DBG2r", 10557 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10558 "RX_X4_STATUS0_BLKSYNC_DBG2", 10559 NULL, 10560 #endif 10561 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10562 0x0, /* 0 */ 10563 0, 10564 #endif 10565 }, 10566 { 10567 BCMI_TSCF_XGXS_RX_X4_BLK_LOCK_LATCH_STSr, 10568 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10569 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 10570 BCMI_TSCF_XGXS_RX_X4_BLK_LOCK_LATCH_STSr_fields, 10571 #else 10572 0, 10573 #endif 10574 #endif 10575 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10576 PHYMOD_SYMBOL_FLAG_REGISTER, 10577 "RX_X4_BLK_LOCK_LATCH_STSr", 10578 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10579 "RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS", 10580 NULL, 10581 #endif 10582 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10583 0x0, /* 0 */ 10584 0, 10585 #endif 10586 }, 10587 { 10588 BCMI_TSCF_XGXS_RX_X4_AM_LOCK_LATCH_STSr, 10589 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10590 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 10591 BCMI_TSCF_XGXS_RX_X4_AM_LOCK_LATCH_STSr_fields, 10592 #else 10593 0, 10594 #endif 10595 #endif 10596 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10597 PHYMOD_SYMBOL_FLAG_REGISTER, 10598 "RX_X4_AM_LOCK_LATCH_STSr", 10599 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10600 "RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS", 10601 NULL, 10602 #endif 10603 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10604 0x0, /* 0 */ 10605 0, 10606 #endif 10607 }, 10608 { 10609 BCMI_TSCF_XGXS_RX_X4_PCS_LIVE_STS0r, 10610 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10611 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 10612 BCMI_TSCF_XGXS_RX_X4_PCS_LIVE_STS0r_fields, 10613 #else 10614 0, 10615 #endif 10616 #endif 10617 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10618 PHYMOD_SYMBOL_FLAG_REGISTER, 10619 "RX_X4_PCS_LIVE_STS0r", 10620 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10621 "RX_X4_STATUS0_PCS_LIVE_STATUS_0", 10622 NULL, 10623 #endif 10624 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10625 0x0, /* 0 */ 10626 0, 10627 #endif 10628 }, 10629 { 10630 BCMI_TSCF_XGXS_RX_X4_BIPCNT0r, 10631 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10632 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 10633 BCMI_TSCF_XGXS_RX_X4_BIPCNT0r_fields, 10634 #else 10635 0, 10636 #endif 10637 #endif 10638 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10639 PHYMOD_SYMBOL_FLAG_REGISTER, 10640 "RX_X4_BIPCNT0r", 10641 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10642 "RX_X4_STATUS0_BIPCOUNT_0", 10643 NULL, 10644 #endif 10645 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10646 0x0, /* 0 */ 10647 0, 10648 #endif 10649 }, 10650 { 10651 BCMI_TSCF_XGXS_RX_X4_BIPCNT1r, 10652 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10653 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 10654 BCMI_TSCF_XGXS_RX_X4_BIPCNT1r_fields, 10655 #else 10656 0, 10657 #endif 10658 #endif 10659 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10660 PHYMOD_SYMBOL_FLAG_REGISTER, 10661 "RX_X4_BIPCNT1r", 10662 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10663 "RX_X4_STATUS0_BIPCOUNT_1", 10664 NULL, 10665 #endif 10666 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10667 0x0, /* 0 */ 10668 0, 10669 #endif 10670 }, 10671 { 10672 BCMI_TSCF_XGXS_RX_X4_BIPCNT2r, 10673 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10674 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 10675 BCMI_TSCF_XGXS_RX_X4_BIPCNT2r_fields, 10676 #else 10677 0, 10678 #endif 10679 #endif 10680 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10681 PHYMOD_SYMBOL_FLAG_REGISTER, 10682 "RX_X4_BIPCNT2r", 10683 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10684 "RX_X4_STATUS0_BIPCOUNT_2", 10685 NULL, 10686 #endif 10687 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10688 0x0, /* 0 */ 10689 0, 10690 #endif 10691 }, 10692 { 10693 BCMI_TSCF_XGXS_RX_X4_PSLL_TO_VL_MAP0r, 10694 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10695 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 10696 BCMI_TSCF_XGXS_RX_X4_PSLL_TO_VL_MAP0r_fields, 10697 #else 10698 0, 10699 #endif 10700 #endif 10701 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10702 PHYMOD_SYMBOL_FLAG_REGISTER, 10703 "RX_X4_PSLL_TO_VL_MAP0r", 10704 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10705 "RX_X4_STATUS0_PSLL_TO_VL_MAPPING_0", 10706 NULL, 10707 #endif 10708 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10709 0x0, /* 0 */ 10710 0, 10711 #endif 10712 }, 10713 { 10714 BCMI_TSCF_XGXS_RX_X4_PSLL_TO_VL_MAP1r, 10715 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10716 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 10717 BCMI_TSCF_XGXS_RX_X4_PSLL_TO_VL_MAP1r_fields, 10718 #else 10719 0, 10720 #endif 10721 #endif 10722 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10723 PHYMOD_SYMBOL_FLAG_REGISTER, 10724 "RX_X4_PSLL_TO_VL_MAP1r", 10725 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10726 "RX_X4_STATUS0_PSLL_TO_VL_MAPPING_1", 10727 NULL, 10728 #endif 10729 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10730 0x0, /* 0 */ 10731 0, 10732 #endif 10733 }, 10734 { 10735 BCMI_TSCF_XGXS_RX_X4_PRTPERRCTRr, 10736 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10737 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 10738 BCMI_TSCF_XGXS_RX_X4_PRTPERRCTRr_fields, 10739 #else 10740 0, 10741 #endif 10742 #endif 10743 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10744 PHYMOD_SYMBOL_FLAG_REGISTER, 10745 "RX_X4_PRTPERRCTRr", 10746 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10747 "RX_X4_STATUS0_PRTPERRORCOUNTER", 10748 NULL, 10749 #endif 10750 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10751 0x0, /* 0 */ 10752 0, 10753 #endif 10754 }, 10755 { 10756 BCMI_TSCF_XGXS_RX_X4_PRTPSTSr, 10757 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10758 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 10759 BCMI_TSCF_XGXS_RX_X4_PRTPSTSr_fields, 10760 #else 10761 0, 10762 #endif 10763 #endif 10764 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10765 PHYMOD_SYMBOL_FLAG_REGISTER, 10766 "RX_X4_PRTPSTSr", 10767 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10768 "RX_X4_STATUS0_PRTPSTATUS", 10769 NULL, 10770 #endif 10771 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10772 0x0, /* 0 */ 10773 0, 10774 #endif 10775 }, 10776 { 10777 BCMI_TSCF_XGXS_RX_X4_PCS_LATCH_STS1r, 10778 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10779 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 10780 BCMI_TSCF_XGXS_RX_X4_PCS_LATCH_STS1r_fields, 10781 #else 10782 0, 10783 #endif 10784 #endif 10785 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10786 PHYMOD_SYMBOL_FLAG_REGISTER, 10787 "RX_X4_PCS_LATCH_STS1r", 10788 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10789 "RX_X4_STATUS1_PCS_LATCHED_STATUS_1", 10790 NULL, 10791 #endif 10792 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10793 0x0, /* 0 */ 10794 0, 10795 #endif 10796 }, 10797 { 10798 BCMI_TSCF_XGXS_RX_X4_PCS_LIVE_STS1r, 10799 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10800 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 10801 BCMI_TSCF_XGXS_RX_X4_PCS_LIVE_STS1r_fields, 10802 #else 10803 0, 10804 #endif 10805 #endif 10806 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10807 PHYMOD_SYMBOL_FLAG_REGISTER, 10808 "RX_X4_PCS_LIVE_STS1r", 10809 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10810 "RX_X4_STATUS1_PCS_LIVE_STATUS_1", 10811 NULL, 10812 #endif 10813 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10814 0x0, /* 0 */ 10815 0, 10816 #endif 10817 }, 10818 { 10819 BCMI_TSCF_XGXS_RX_X4_DEC_STS0r, 10820 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10821 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 10822 BCMI_TSCF_XGXS_RX_X4_DEC_STS0r_fields, 10823 #else 10824 0, 10825 #endif 10826 #endif 10827 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10828 PHYMOD_SYMBOL_FLAG_REGISTER, 10829 "RX_X4_DEC_STS0r", 10830 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10831 "RX_X4_STATUS1_DECODE_STATUS_0", 10832 NULL, 10833 #endif 10834 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10835 0x0, /* 0 */ 10836 0, 10837 #endif 10838 }, 10839 { 10840 BCMI_TSCF_XGXS_RX_X4_DEC_STS1r, 10841 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10842 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 10843 BCMI_TSCF_XGXS_RX_X4_DEC_STS1r_fields, 10844 #else 10845 0, 10846 #endif 10847 #endif 10848 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10849 PHYMOD_SYMBOL_FLAG_REGISTER, 10850 "RX_X4_DEC_STS1r", 10851 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10852 "RX_X4_STATUS1_DECODE_STATUS_1", 10853 NULL, 10854 #endif 10855 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10856 0x0, /* 0 */ 10857 0, 10858 #endif 10859 }, 10860 { 10861 BCMI_TSCF_XGXS_RX_X4_DEC_STS2r, 10862 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10863 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 10864 BCMI_TSCF_XGXS_RX_X4_DEC_STS2r_fields, 10865 #else 10866 0, 10867 #endif 10868 #endif 10869 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10870 PHYMOD_SYMBOL_FLAG_REGISTER, 10871 "RX_X4_DEC_STS2r", 10872 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10873 "RX_X4_STATUS1_DECODE_STATUS_2", 10874 NULL, 10875 #endif 10876 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10877 0x0, /* 0 */ 10878 0, 10879 #endif 10880 }, 10881 { 10882 BCMI_TSCF_XGXS_RX_X4_DEC_STS3r, 10883 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10884 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 10885 BCMI_TSCF_XGXS_RX_X4_DEC_STS3r_fields, 10886 #else 10887 0, 10888 #endif 10889 #endif 10890 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10891 PHYMOD_SYMBOL_FLAG_REGISTER, 10892 "RX_X4_DEC_STS3r", 10893 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10894 "RX_X4_STATUS1_DECODE_STATUS_3", 10895 NULL, 10896 #endif 10897 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10898 0x0, /* 0 */ 10899 0, 10900 #endif 10901 }, 10902 { 10903 BCMI_TSCF_XGXS_RX_X4_CL91_FEC_SYM_ERR_CTR0r, 10904 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10905 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 10906 BCMI_TSCF_XGXS_RX_X4_CL91_FEC_SYM_ERR_CTR0r_fields, 10907 #else 10908 0, 10909 #endif 10910 #endif 10911 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10912 PHYMOD_SYMBOL_FLAG_REGISTER, 10913 "RX_X4_CL91_FEC_SYM_ERR_CTR0r", 10914 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10915 "RX_X4_STATUS1_CL91_FEC_SYMB_ERR_CNTR_0", 10916 NULL, 10917 #endif 10918 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10919 0x0, /* 0 */ 10920 0, 10921 #endif 10922 }, 10923 { 10924 BCMI_TSCF_XGXS_RX_X4_CL91_FEC_SYM_ERR_CTR1r, 10925 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10926 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 10927 BCMI_TSCF_XGXS_RX_X4_CL91_FEC_SYM_ERR_CTR1r_fields, 10928 #else 10929 0, 10930 #endif 10931 #endif 10932 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10933 PHYMOD_SYMBOL_FLAG_REGISTER, 10934 "RX_X4_CL91_FEC_SYM_ERR_CTR1r", 10935 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10936 "RX_X4_STATUS1_CL91_FEC_SYMB_ERR_CNTR_1", 10937 NULL, 10938 #endif 10939 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10940 0x0, /* 0 */ 10941 0, 10942 #endif 10943 }, 10944 { 10945 BCMI_TSCF_XGXS_RX_X4_CL36_SYNCACQ_STS0r, 10946 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10947 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 10948 BCMI_TSCF_XGXS_RX_X4_CL36_SYNCACQ_STS0r_fields, 10949 #else 10950 0, 10951 #endif 10952 #endif 10953 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10954 PHYMOD_SYMBOL_FLAG_REGISTER, 10955 "RX_X4_CL36_SYNCACQ_STS0r", 10956 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10957 "RX_X4_STATUS1_CL36RX_SYNCACQ_STATUS_0", 10958 NULL, 10959 #endif 10960 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10961 0x0, /* 0 */ 10962 0, 10963 #endif 10964 }, 10965 { 10966 BCMI_TSCF_XGXS_RX_X4_CL36_SYNCACQ_STS1r, 10967 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10968 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 10969 BCMI_TSCF_XGXS_RX_X4_CL36_SYNCACQ_STS1r_fields, 10970 #else 10971 0, 10972 #endif 10973 #endif 10974 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10975 PHYMOD_SYMBOL_FLAG_REGISTER, 10976 "RX_X4_CL36_SYNCACQ_STS1r", 10977 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10978 "RX_X4_STATUS1_CL36RX_SYNCACQ_STATUS_1", 10979 NULL, 10980 #endif 10981 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10982 0x0, /* 0 */ 10983 0, 10984 #endif 10985 }, 10986 { 10987 BCMI_TSCF_XGXS_RX_X4_CL36_BERCNTr, 10988 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10989 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 10990 BCMI_TSCF_XGXS_RX_X4_CL36_BERCNTr_fields, 10991 #else 10992 0, 10993 #endif 10994 #endif 10995 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10996 PHYMOD_SYMBOL_FLAG_REGISTER, 10997 "RX_X4_CL36_BERCNTr", 10998 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10999 "RX_X4_STATUS1_CL36RX_BERCOUNT", 11000 NULL, 11001 #endif 11002 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11003 0x0, /* 0 */ 11004 0, 11005 #endif 11006 }, 11007 { 11008 BCMI_TSCF_XGXS_RX_X4_CL82_AM_LATCH_STS_PSLL0r, 11009 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11010 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 11011 BCMI_TSCF_XGXS_RX_X4_CL82_AM_LATCH_STS_PSLL0r_fields, 11012 #else 11013 0, 11014 #endif 11015 #endif 11016 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11017 PHYMOD_SYMBOL_FLAG_REGISTER, 11018 "RX_X4_CL82_AM_LATCH_STS_PSLL0r", 11019 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11020 "RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_0", 11021 NULL, 11022 #endif 11023 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11024 0x0, /* 0 */ 11025 0, 11026 #endif 11027 }, 11028 { 11029 BCMI_TSCF_XGXS_RX_X4_CL82_AM_LATCH_STS_PSLL1r, 11030 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11031 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 11032 BCMI_TSCF_XGXS_RX_X4_CL82_AM_LATCH_STS_PSLL1r_fields, 11033 #else 11034 0, 11035 #endif 11036 #endif 11037 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11038 PHYMOD_SYMBOL_FLAG_REGISTER, 11039 "RX_X4_CL82_AM_LATCH_STS_PSLL1r", 11040 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11041 "RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_1", 11042 NULL, 11043 #endif 11044 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11045 0x0, /* 0 */ 11046 0, 11047 #endif 11048 }, 11049 { 11050 BCMI_TSCF_XGXS_RX_X4_CL82_AM_LATCH_STS_PSLL2r, 11051 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11052 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 11053 BCMI_TSCF_XGXS_RX_X4_CL82_AM_LATCH_STS_PSLL2r_fields, 11054 #else 11055 0, 11056 #endif 11057 #endif 11058 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11059 PHYMOD_SYMBOL_FLAG_REGISTER, 11060 "RX_X4_CL82_AM_LATCH_STS_PSLL2r", 11061 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11062 "RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_2", 11063 NULL, 11064 #endif 11065 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11066 0x0, /* 0 */ 11067 0, 11068 #endif 11069 }, 11070 { 11071 BCMI_TSCF_XGXS_RX_X4_CL82_AM_LATCH_STS_PSLL3r, 11072 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11073 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 11074 BCMI_TSCF_XGXS_RX_X4_CL82_AM_LATCH_STS_PSLL3r_fields, 11075 #else 11076 0, 11077 #endif 11078 #endif 11079 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11080 PHYMOD_SYMBOL_FLAG_REGISTER, 11081 "RX_X4_CL82_AM_LATCH_STS_PSLL3r", 11082 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11083 "RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_3", 11084 NULL, 11085 #endif 11086 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11087 0x0, /* 0 */ 11088 0, 11089 #endif 11090 }, 11091 { 11092 BCMI_TSCF_XGXS_RX_X4_CL82_AM_LATCH_STS_PSLL4r, 11093 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11094 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 11095 BCMI_TSCF_XGXS_RX_X4_CL82_AM_LATCH_STS_PSLL4r_fields, 11096 #else 11097 0, 11098 #endif 11099 #endif 11100 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11101 PHYMOD_SYMBOL_FLAG_REGISTER, 11102 "RX_X4_CL82_AM_LATCH_STS_PSLL4r", 11103 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11104 "RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_4", 11105 NULL, 11106 #endif 11107 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11108 0x0, /* 0 */ 11109 0, 11110 #endif 11111 }, 11112 { 11113 BCMI_TSCF_XGXS_RX_X4_CL82_AM_LIVE_STS_PSLL0r, 11114 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11115 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 11116 BCMI_TSCF_XGXS_RX_X4_CL82_AM_LIVE_STS_PSLL0r_fields, 11117 #else 11118 0, 11119 #endif 11120 #endif 11121 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11122 PHYMOD_SYMBOL_FLAG_REGISTER, 11123 "RX_X4_CL82_AM_LIVE_STS_PSLL0r", 11124 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11125 "RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_0", 11126 NULL, 11127 #endif 11128 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11129 0x0, /* 0 */ 11130 0, 11131 #endif 11132 }, 11133 { 11134 BCMI_TSCF_XGXS_RX_X4_CL82_AM_LIVE_STS_PSLL1r, 11135 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11136 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 11137 BCMI_TSCF_XGXS_RX_X4_CL82_AM_LIVE_STS_PSLL1r_fields, 11138 #else 11139 0, 11140 #endif 11141 #endif 11142 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11143 PHYMOD_SYMBOL_FLAG_REGISTER, 11144 "RX_X4_CL82_AM_LIVE_STS_PSLL1r", 11145 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11146 "RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_1", 11147 NULL, 11148 #endif 11149 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11150 0x0, /* 0 */ 11151 0, 11152 #endif 11153 }, 11154 { 11155 BCMI_TSCF_XGXS_RX_X4_CL82_AM_LIVE_STS_PSLL2r, 11156 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11157 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 11158 BCMI_TSCF_XGXS_RX_X4_CL82_AM_LIVE_STS_PSLL2r_fields, 11159 #else 11160 0, 11161 #endif 11162 #endif 11163 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11164 PHYMOD_SYMBOL_FLAG_REGISTER, 11165 "RX_X4_CL82_AM_LIVE_STS_PSLL2r", 11166 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11167 "RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_2", 11168 NULL, 11169 #endif 11170 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11171 0x0, /* 0 */ 11172 0, 11173 #endif 11174 }, 11175 { 11176 BCMI_TSCF_XGXS_RX_X4_CL82_AM_LIVE_STS_PSLL3r, 11177 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11178 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 11179 BCMI_TSCF_XGXS_RX_X4_CL82_AM_LIVE_STS_PSLL3r_fields, 11180 #else 11181 0, 11182 #endif 11183 #endif 11184 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11185 PHYMOD_SYMBOL_FLAG_REGISTER, 11186 "RX_X4_CL82_AM_LIVE_STS_PSLL3r", 11187 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11188 "RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_3", 11189 NULL, 11190 #endif 11191 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11192 0x0, /* 0 */ 11193 0, 11194 #endif 11195 }, 11196 { 11197 BCMI_TSCF_XGXS_RX_X4_CL82_AM_LIVE_STS_PSLL4r, 11198 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11199 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 11200 BCMI_TSCF_XGXS_RX_X4_CL82_AM_LIVE_STS_PSLL4r_fields, 11201 #else 11202 0, 11203 #endif 11204 #endif 11205 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11206 PHYMOD_SYMBOL_FLAG_REGISTER, 11207 "RX_X4_CL82_AM_LIVE_STS_PSLL4r", 11208 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11209 "RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_4", 11210 NULL, 11211 #endif 11212 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11213 0x0, /* 0 */ 11214 0, 11215 #endif 11216 }, 11217 { 11218 BCMI_TSCF_XGXS_RX_X4_CL91_SYNC_STSr, 11219 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11220 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 11221 BCMI_TSCF_XGXS_RX_X4_CL91_SYNC_STSr_fields, 11222 #else 11223 0, 11224 #endif 11225 #endif 11226 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11227 PHYMOD_SYMBOL_FLAG_REGISTER, 11228 "RX_X4_CL91_SYNC_STSr", 11229 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11230 "RX_X4_STATUS2_CL91_SYNC_STATUS", 11231 NULL, 11232 #endif 11233 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11234 0x0, /* 0 */ 11235 0, 11236 #endif 11237 }, 11238 { 11239 BCMI_TSCF_XGXS_RX_X4_FEC_SYNC_FSM_STr, 11240 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11241 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 11242 BCMI_TSCF_XGXS_RX_X4_FEC_SYNC_FSM_STr_fields, 11243 #else 11244 0, 11245 #endif 11246 #endif 11247 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11248 PHYMOD_SYMBOL_FLAG_REGISTER, 11249 "RX_X4_FEC_SYNC_FSM_STr", 11250 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11251 "RX_X4_STATUS2_FEC_SYNC_FSM_STATE", 11252 NULL, 11253 #endif 11254 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11255 0x4, /* 4 */ 11256 0, 11257 #endif 11258 }, 11259 { 11260 BCMI_TSCF_XGXS_RX_X4_FEC_DBG_ERRL0r, 11261 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11262 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 11263 BCMI_TSCF_XGXS_RX_X4_FEC_DBG_ERRL0r_fields, 11264 #else 11265 0, 11266 #endif 11267 #endif 11268 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11269 PHYMOD_SYMBOL_FLAG_REGISTER, 11270 "RX_X4_FEC_DBG_ERRL0r", 11271 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11272 "RX_X4_STATUS3_FEC_DBG_ERRL_0", 11273 NULL, 11274 #endif 11275 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11276 0x0, /* 0 */ 11277 0, 11278 #endif 11279 }, 11280 { 11281 BCMI_TSCF_XGXS_RX_X4_FEC_DBG_ERRL1r, 11282 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11283 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 11284 BCMI_TSCF_XGXS_RX_X4_FEC_DBG_ERRL1r_fields, 11285 #else 11286 0, 11287 #endif 11288 #endif 11289 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11290 PHYMOD_SYMBOL_FLAG_REGISTER, 11291 "RX_X4_FEC_DBG_ERRL1r", 11292 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11293 "RX_X4_STATUS3_FEC_DBG_ERRL_1", 11294 NULL, 11295 #endif 11296 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11297 0x0, /* 0 */ 11298 0, 11299 #endif 11300 }, 11301 { 11302 BCMI_TSCF_XGXS_RX_X4_FEC_DBG_ERRL2r, 11303 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11304 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 11305 BCMI_TSCF_XGXS_RX_X4_FEC_DBG_ERRL2r_fields, 11306 #else 11307 0, 11308 #endif 11309 #endif 11310 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11311 PHYMOD_SYMBOL_FLAG_REGISTER, 11312 "RX_X4_FEC_DBG_ERRL2r", 11313 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11314 "RX_X4_STATUS3_FEC_DBG_ERRL_2", 11315 NULL, 11316 #endif 11317 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11318 0x0, /* 0 */ 11319 0, 11320 #endif 11321 }, 11322 { 11323 BCMI_TSCF_XGXS_RX_X4_FEC_DBG_ERRL3r, 11324 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11325 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 11326 BCMI_TSCF_XGXS_RX_X4_FEC_DBG_ERRL3r_fields, 11327 #else 11328 0, 11329 #endif 11330 #endif 11331 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11332 PHYMOD_SYMBOL_FLAG_REGISTER, 11333 "RX_X4_FEC_DBG_ERRL3r", 11334 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11335 "RX_X4_STATUS3_FEC_DBG_ERRL_3", 11336 NULL, 11337 #endif 11338 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11339 0x0, /* 0 */ 11340 0, 11341 #endif 11342 }, 11343 { 11344 BCMI_TSCF_XGXS_RX_X4_FEC_DBG_ERRL4r, 11345 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11346 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 11347 BCMI_TSCF_XGXS_RX_X4_FEC_DBG_ERRL4r_fields, 11348 #else 11349 0, 11350 #endif 11351 #endif 11352 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11353 PHYMOD_SYMBOL_FLAG_REGISTER, 11354 "RX_X4_FEC_DBG_ERRL4r", 11355 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11356 "RX_X4_STATUS3_FEC_DBG_ERRL_4", 11357 NULL, 11358 #endif 11359 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11360 0x0, /* 0 */ 11361 0, 11362 #endif 11363 }, 11364 { 11365 BCMI_TSCF_XGXS_RX_X4_FEC_DBG_ERRAH0r, 11366 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11367 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 11368 BCMI_TSCF_XGXS_RX_X4_FEC_DBG_ERRAH0r_fields, 11369 #else 11370 0, 11371 #endif 11372 #endif 11373 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11374 PHYMOD_SYMBOL_FLAG_REGISTER, 11375 "RX_X4_FEC_DBG_ERRAH0r", 11376 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11377 "RX_X4_STATUS3_FEC_DBG_ERRAH_0", 11378 NULL, 11379 #endif 11380 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11381 0x0, /* 0 */ 11382 0, 11383 #endif 11384 }, 11385 { 11386 BCMI_TSCF_XGXS_RX_X4_FEC_DBG_ERRAH1r, 11387 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11388 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 11389 BCMI_TSCF_XGXS_RX_X4_FEC_DBG_ERRAH1r_fields, 11390 #else 11391 0, 11392 #endif 11393 #endif 11394 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11395 PHYMOD_SYMBOL_FLAG_REGISTER, 11396 "RX_X4_FEC_DBG_ERRAH1r", 11397 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11398 "RX_X4_STATUS3_FEC_DBG_ERRAH_1", 11399 NULL, 11400 #endif 11401 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11402 0x0, /* 0 */ 11403 0, 11404 #endif 11405 }, 11406 { 11407 BCMI_TSCF_XGXS_RX_X4_FEC_DBG_ERRAH2r, 11408 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11409 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 11410 BCMI_TSCF_XGXS_RX_X4_FEC_DBG_ERRAH2r_fields, 11411 #else 11412 0, 11413 #endif 11414 #endif 11415 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11416 PHYMOD_SYMBOL_FLAG_REGISTER, 11417 "RX_X4_FEC_DBG_ERRAH2r", 11418 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11419 "RX_X4_STATUS3_FEC_DBG_ERRAH_2", 11420 NULL, 11421 #endif 11422 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11423 0x0, /* 0 */ 11424 0, 11425 #endif 11426 }, 11427 { 11428 BCMI_TSCF_XGXS_RX_X4_FEC_DBG_ERRAH3r, 11429 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11430 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 11431 BCMI_TSCF_XGXS_RX_X4_FEC_DBG_ERRAH3r_fields, 11432 #else 11433 0, 11434 #endif 11435 #endif 11436 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11437 PHYMOD_SYMBOL_FLAG_REGISTER, 11438 "RX_X4_FEC_DBG_ERRAH3r", 11439 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11440 "RX_X4_STATUS3_FEC_DBG_ERRAH_3", 11441 NULL, 11442 #endif 11443 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11444 0x0, /* 0 */ 11445 0, 11446 #endif 11447 }, 11448 { 11449 BCMI_TSCF_XGXS_RX_X4_FEC_DBG_ERRAH4r, 11450 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11451 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 11452 BCMI_TSCF_XGXS_RX_X4_FEC_DBG_ERRAH4r_fields, 11453 #else 11454 0, 11455 #endif 11456 #endif 11457 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11458 PHYMOD_SYMBOL_FLAG_REGISTER, 11459 "RX_X4_FEC_DBG_ERRAH4r", 11460 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11461 "RX_X4_STATUS3_FEC_DBG_ERRAH_4", 11462 NULL, 11463 #endif 11464 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11465 0x0, /* 0 */ 11466 0, 11467 #endif 11468 }, 11469 { 11470 BCMI_TSCF_XGXS_RX_X4_FEC_BURST_ERR_STSL0r, 11471 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11472 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 11473 BCMI_TSCF_XGXS_RX_X4_FEC_BURST_ERR_STSL0r_fields, 11474 #else 11475 0, 11476 #endif 11477 #endif 11478 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11479 PHYMOD_SYMBOL_FLAG_REGISTER, 11480 "RX_X4_FEC_BURST_ERR_STSL0r", 11481 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11482 "RX_X4_STATUS3_FEC_BURST_ERR_STATUSL_0", 11483 NULL, 11484 #endif 11485 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11486 0x0, /* 0 */ 11487 0, 11488 #endif 11489 }, 11490 { 11491 BCMI_TSCF_XGXS_RX_X4_FEC_BURST_ERR_STSL1r, 11492 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11493 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 11494 BCMI_TSCF_XGXS_RX_X4_FEC_BURST_ERR_STSL1r_fields, 11495 #else 11496 0, 11497 #endif 11498 #endif 11499 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11500 PHYMOD_SYMBOL_FLAG_REGISTER, 11501 "RX_X4_FEC_BURST_ERR_STSL1r", 11502 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11503 "RX_X4_STATUS3_FEC_BURST_ERR_STATUSL_1", 11504 NULL, 11505 #endif 11506 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11507 0x0, /* 0 */ 11508 0, 11509 #endif 11510 }, 11511 { 11512 BCMI_TSCF_XGXS_RX_X4_FEC_BURST_ERR_STSL2r, 11513 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11514 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 11515 BCMI_TSCF_XGXS_RX_X4_FEC_BURST_ERR_STSL2r_fields, 11516 #else 11517 0, 11518 #endif 11519 #endif 11520 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11521 PHYMOD_SYMBOL_FLAG_REGISTER, 11522 "RX_X4_FEC_BURST_ERR_STSL2r", 11523 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11524 "RX_X4_STATUS3_FEC_BURST_ERR_STATUSL_2", 11525 NULL, 11526 #endif 11527 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11528 0x0, /* 0 */ 11529 0, 11530 #endif 11531 }, 11532 { 11533 BCMI_TSCF_XGXS_RX_X4_FEC_BURST_ERR_STSL3r, 11534 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11535 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 11536 BCMI_TSCF_XGXS_RX_X4_FEC_BURST_ERR_STSL3r_fields, 11537 #else 11538 0, 11539 #endif 11540 #endif 11541 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11542 PHYMOD_SYMBOL_FLAG_REGISTER, 11543 "RX_X4_FEC_BURST_ERR_STSL3r", 11544 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11545 "RX_X4_STATUS3_FEC_BURST_ERR_STATUSL_3", 11546 NULL, 11547 #endif 11548 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11549 0x0, /* 0 */ 11550 0, 11551 #endif 11552 }, 11553 { 11554 BCMI_TSCF_XGXS_RX_X4_FEC_BURST_ERR_STSL4r, 11555 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11556 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 11557 BCMI_TSCF_XGXS_RX_X4_FEC_BURST_ERR_STSL4r_fields, 11558 #else 11559 0, 11560 #endif 11561 #endif 11562 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11563 PHYMOD_SYMBOL_FLAG_REGISTER, 11564 "RX_X4_FEC_BURST_ERR_STSL4r", 11565 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11566 "RX_X4_STATUS3_FEC_BURST_ERR_STATUSL_4", 11567 NULL, 11568 #endif 11569 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11570 0x0, /* 0 */ 11571 0, 11572 #endif 11573 }, 11574 { 11575 BCMI_TSCF_XGXS_RX_X4_FEC_BURST_ERR_STSH0r, 11576 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11577 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 11578 BCMI_TSCF_XGXS_RX_X4_FEC_BURST_ERR_STSH0r_fields, 11579 #else 11580 0, 11581 #endif 11582 #endif 11583 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11584 PHYMOD_SYMBOL_FLAG_REGISTER, 11585 "RX_X4_FEC_BURST_ERR_STSH0r", 11586 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11587 "RX_X4_STATUS4_FEC_BURST_ERR_STATUSH_0", 11588 NULL, 11589 #endif 11590 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11591 0x0, /* 0 */ 11592 0, 11593 #endif 11594 }, 11595 { 11596 BCMI_TSCF_XGXS_RX_X4_FEC_BURST_ERR_STSH1r, 11597 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11598 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 11599 BCMI_TSCF_XGXS_RX_X4_FEC_BURST_ERR_STSH1r_fields, 11600 #else 11601 0, 11602 #endif 11603 #endif 11604 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11605 PHYMOD_SYMBOL_FLAG_REGISTER, 11606 "RX_X4_FEC_BURST_ERR_STSH1r", 11607 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11608 "RX_X4_STATUS4_FEC_BURST_ERR_STATUSH_1", 11609 NULL, 11610 #endif 11611 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11612 0x0, /* 0 */ 11613 0, 11614 #endif 11615 }, 11616 { 11617 BCMI_TSCF_XGXS_RX_X4_FEC_BURST_ERR_STSH2r, 11618 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11619 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 11620 BCMI_TSCF_XGXS_RX_X4_FEC_BURST_ERR_STSH2r_fields, 11621 #else 11622 0, 11623 #endif 11624 #endif 11625 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11626 PHYMOD_SYMBOL_FLAG_REGISTER, 11627 "RX_X4_FEC_BURST_ERR_STSH2r", 11628 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11629 "RX_X4_STATUS4_FEC_BURST_ERR_STATUSH_2", 11630 NULL, 11631 #endif 11632 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11633 0x0, /* 0 */ 11634 0, 11635 #endif 11636 }, 11637 { 11638 BCMI_TSCF_XGXS_RX_X4_FEC_BURST_ERR_STSH3r, 11639 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11640 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 11641 BCMI_TSCF_XGXS_RX_X4_FEC_BURST_ERR_STSH3r_fields, 11642 #else 11643 0, 11644 #endif 11645 #endif 11646 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11647 PHYMOD_SYMBOL_FLAG_REGISTER, 11648 "RX_X4_FEC_BURST_ERR_STSH3r", 11649 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11650 "RX_X4_STATUS4_FEC_BURST_ERR_STATUSH_3", 11651 NULL, 11652 #endif 11653 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11654 0x0, /* 0 */ 11655 0, 11656 #endif 11657 }, 11658 { 11659 BCMI_TSCF_XGXS_RX_X4_FEC_BURST_ERR_STSH4r, 11660 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11661 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 11662 BCMI_TSCF_XGXS_RX_X4_FEC_BURST_ERR_STSH4r_fields, 11663 #else 11664 0, 11665 #endif 11666 #endif 11667 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11668 PHYMOD_SYMBOL_FLAG_REGISTER, 11669 "RX_X4_FEC_BURST_ERR_STSH4r", 11670 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11671 "RX_X4_STATUS4_FEC_BURST_ERR_STATUSH_4", 11672 NULL, 11673 #endif 11674 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11675 0x0, /* 0 */ 11676 0, 11677 #endif 11678 }, 11679 { 11680 BCMI_TSCF_XGXS_RX_X4_FEC_CORRBLKSL0r, 11681 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11682 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 11683 BCMI_TSCF_XGXS_RX_X4_FEC_CORRBLKSL0r_fields, 11684 #else 11685 0, 11686 #endif 11687 #endif 11688 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11689 PHYMOD_SYMBOL_FLAG_REGISTER, 11690 "RX_X4_FEC_CORRBLKSL0r", 11691 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11692 "RX_X4_STATUS4_FEC_CORRECTEDBLKSL_0", 11693 NULL, 11694 #endif 11695 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11696 0x0, /* 0 */ 11697 0, 11698 #endif 11699 }, 11700 { 11701 BCMI_TSCF_XGXS_RX_X4_FEC_CORRBLKSL1r, 11702 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11703 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 11704 BCMI_TSCF_XGXS_RX_X4_FEC_CORRBLKSL1r_fields, 11705 #else 11706 0, 11707 #endif 11708 #endif 11709 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11710 PHYMOD_SYMBOL_FLAG_REGISTER, 11711 "RX_X4_FEC_CORRBLKSL1r", 11712 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11713 "RX_X4_STATUS4_FEC_CORRECTEDBLKSL_1", 11714 NULL, 11715 #endif 11716 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11717 0x0, /* 0 */ 11718 0, 11719 #endif 11720 }, 11721 { 11722 BCMI_TSCF_XGXS_RX_X4_FEC_CORRBLKSL2r, 11723 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11724 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 11725 BCMI_TSCF_XGXS_RX_X4_FEC_CORRBLKSL2r_fields, 11726 #else 11727 0, 11728 #endif 11729 #endif 11730 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11731 PHYMOD_SYMBOL_FLAG_REGISTER, 11732 "RX_X4_FEC_CORRBLKSL2r", 11733 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11734 "RX_X4_STATUS4_FEC_CORRECTEDBLKSL_2", 11735 NULL, 11736 #endif 11737 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11738 0x0, /* 0 */ 11739 0, 11740 #endif 11741 }, 11742 { 11743 BCMI_TSCF_XGXS_RX_X4_FEC_CORRBLKSL3r, 11744 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11745 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 11746 BCMI_TSCF_XGXS_RX_X4_FEC_CORRBLKSL3r_fields, 11747 #else 11748 0, 11749 #endif 11750 #endif 11751 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11752 PHYMOD_SYMBOL_FLAG_REGISTER, 11753 "RX_X4_FEC_CORRBLKSL3r", 11754 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11755 "RX_X4_STATUS4_FEC_CORRECTEDBLKSL_3", 11756 NULL, 11757 #endif 11758 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11759 0x0, /* 0 */ 11760 0, 11761 #endif 11762 }, 11763 { 11764 BCMI_TSCF_XGXS_RX_X4_FEC_CORRBLKSL4r, 11765 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11766 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 11767 BCMI_TSCF_XGXS_RX_X4_FEC_CORRBLKSL4r_fields, 11768 #else 11769 0, 11770 #endif 11771 #endif 11772 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11773 PHYMOD_SYMBOL_FLAG_REGISTER, 11774 "RX_X4_FEC_CORRBLKSL4r", 11775 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11776 "RX_X4_STATUS4_FEC_CORRECTEDBLKSL_4", 11777 NULL, 11778 #endif 11779 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11780 0x0, /* 0 */ 11781 0, 11782 #endif 11783 }, 11784 { 11785 BCMI_TSCF_XGXS_RX_X4_FEC_CORRBLKSH0r, 11786 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11787 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 11788 BCMI_TSCF_XGXS_RX_X4_FEC_CORRBLKSH0r_fields, 11789 #else 11790 0, 11791 #endif 11792 #endif 11793 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11794 PHYMOD_SYMBOL_FLAG_REGISTER, 11795 "RX_X4_FEC_CORRBLKSH0r", 11796 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11797 "RX_X4_STATUS4_FEC_CORRECTEDBLKSH_0", 11798 NULL, 11799 #endif 11800 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11801 0x0, /* 0 */ 11802 0, 11803 #endif 11804 }, 11805 { 11806 BCMI_TSCF_XGXS_RX_X4_FEC_CORRBLKSH1r, 11807 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11808 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 11809 BCMI_TSCF_XGXS_RX_X4_FEC_CORRBLKSH1r_fields, 11810 #else 11811 0, 11812 #endif 11813 #endif 11814 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11815 PHYMOD_SYMBOL_FLAG_REGISTER, 11816 "RX_X4_FEC_CORRBLKSH1r", 11817 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11818 "RX_X4_STATUS4_FEC_CORRECTEDBLKSH_1", 11819 NULL, 11820 #endif 11821 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11822 0x0, /* 0 */ 11823 0, 11824 #endif 11825 }, 11826 { 11827 BCMI_TSCF_XGXS_RX_X4_FEC_CORRBLKSH2r, 11828 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11829 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 11830 BCMI_TSCF_XGXS_RX_X4_FEC_CORRBLKSH2r_fields, 11831 #else 11832 0, 11833 #endif 11834 #endif 11835 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11836 PHYMOD_SYMBOL_FLAG_REGISTER, 11837 "RX_X4_FEC_CORRBLKSH2r", 11838 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11839 "RX_X4_STATUS4_FEC_CORRECTEDBLKSH_2", 11840 NULL, 11841 #endif 11842 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11843 0x0, /* 0 */ 11844 0, 11845 #endif 11846 }, 11847 { 11848 BCMI_TSCF_XGXS_RX_X4_FEC_CORRBLKSH3r, 11849 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11850 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 11851 BCMI_TSCF_XGXS_RX_X4_FEC_CORRBLKSH3r_fields, 11852 #else 11853 0, 11854 #endif 11855 #endif 11856 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11857 PHYMOD_SYMBOL_FLAG_REGISTER, 11858 "RX_X4_FEC_CORRBLKSH3r", 11859 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11860 "RX_X4_STATUS4_FEC_CORRECTEDBLKSH_3", 11861 NULL, 11862 #endif 11863 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11864 0x0, /* 0 */ 11865 0, 11866 #endif 11867 }, 11868 { 11869 BCMI_TSCF_XGXS_RX_X4_FEC_CORRBLKSH4r, 11870 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11871 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 11872 BCMI_TSCF_XGXS_RX_X4_FEC_CORRBLKSH4r_fields, 11873 #else 11874 0, 11875 #endif 11876 #endif 11877 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11878 PHYMOD_SYMBOL_FLAG_REGISTER, 11879 "RX_X4_FEC_CORRBLKSH4r", 11880 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11881 "RX_X4_STATUS4_FEC_CORRECTEDBLKSH_4", 11882 NULL, 11883 #endif 11884 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11885 0x0, /* 0 */ 11886 0, 11887 #endif 11888 }, 11889 { 11890 BCMI_TSCF_XGXS_RX_X4_FEC_UNCORRBLKSL0r, 11891 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11892 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 11893 BCMI_TSCF_XGXS_RX_X4_FEC_UNCORRBLKSL0r_fields, 11894 #else 11895 0, 11896 #endif 11897 #endif 11898 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11899 PHYMOD_SYMBOL_FLAG_REGISTER, 11900 "RX_X4_FEC_UNCORRBLKSL0r", 11901 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11902 "RX_X4_STATUS5_FEC_UNCORRECTEDBLKSL_0", 11903 NULL, 11904 #endif 11905 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11906 0x0, /* 0 */ 11907 0, 11908 #endif 11909 }, 11910 { 11911 BCMI_TSCF_XGXS_RX_X4_FEC_UNCORRBLKSL1r, 11912 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11913 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 11914 BCMI_TSCF_XGXS_RX_X4_FEC_UNCORRBLKSL1r_fields, 11915 #else 11916 0, 11917 #endif 11918 #endif 11919 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11920 PHYMOD_SYMBOL_FLAG_REGISTER, 11921 "RX_X4_FEC_UNCORRBLKSL1r", 11922 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11923 "RX_X4_STATUS5_FEC_UNCORRECTEDBLKSL_1", 11924 NULL, 11925 #endif 11926 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11927 0x0, /* 0 */ 11928 0, 11929 #endif 11930 }, 11931 { 11932 BCMI_TSCF_XGXS_RX_X4_FEC_UNCORRBLKSL2r, 11933 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11934 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 11935 BCMI_TSCF_XGXS_RX_X4_FEC_UNCORRBLKSL2r_fields, 11936 #else 11937 0, 11938 #endif 11939 #endif 11940 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11941 PHYMOD_SYMBOL_FLAG_REGISTER, 11942 "RX_X4_FEC_UNCORRBLKSL2r", 11943 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11944 "RX_X4_STATUS5_FEC_UNCORRECTEDBLKSL_2", 11945 NULL, 11946 #endif 11947 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11948 0x0, /* 0 */ 11949 0, 11950 #endif 11951 }, 11952 { 11953 BCMI_TSCF_XGXS_RX_X4_FEC_UNCORRBLKSL3r, 11954 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11955 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 11956 BCMI_TSCF_XGXS_RX_X4_FEC_UNCORRBLKSL3r_fields, 11957 #else 11958 0, 11959 #endif 11960 #endif 11961 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11962 PHYMOD_SYMBOL_FLAG_REGISTER, 11963 "RX_X4_FEC_UNCORRBLKSL3r", 11964 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11965 "RX_X4_STATUS5_FEC_UNCORRECTEDBLKSL_3", 11966 NULL, 11967 #endif 11968 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11969 0x0, /* 0 */ 11970 0, 11971 #endif 11972 }, 11973 { 11974 BCMI_TSCF_XGXS_RX_X4_FEC_UNCORRBLKSL4r, 11975 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11976 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 11977 BCMI_TSCF_XGXS_RX_X4_FEC_UNCORRBLKSL4r_fields, 11978 #else 11979 0, 11980 #endif 11981 #endif 11982 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11983 PHYMOD_SYMBOL_FLAG_REGISTER, 11984 "RX_X4_FEC_UNCORRBLKSL4r", 11985 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11986 "RX_X4_STATUS5_FEC_UNCORRECTEDBLKSL_4", 11987 NULL, 11988 #endif 11989 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11990 0x0, /* 0 */ 11991 0, 11992 #endif 11993 }, 11994 { 11995 BCMI_TSCF_XGXS_RX_X4_FEC_UNCORRBLKSH0r, 11996 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11997 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 11998 BCMI_TSCF_XGXS_RX_X4_FEC_UNCORRBLKSH0r_fields, 11999 #else 12000 0, 12001 #endif 12002 #endif 12003 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12004 PHYMOD_SYMBOL_FLAG_REGISTER, 12005 "RX_X4_FEC_UNCORRBLKSH0r", 12006 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12007 "RX_X4_STATUS5_FEC_UNCORRECTEDBLKSH_0", 12008 NULL, 12009 #endif 12010 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12011 0x0, /* 0 */ 12012 0, 12013 #endif 12014 }, 12015 { 12016 BCMI_TSCF_XGXS_RX_X4_FEC_UNCORRBLKSH1r, 12017 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12018 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 12019 BCMI_TSCF_XGXS_RX_X4_FEC_UNCORRBLKSH1r_fields, 12020 #else 12021 0, 12022 #endif 12023 #endif 12024 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12025 PHYMOD_SYMBOL_FLAG_REGISTER, 12026 "RX_X4_FEC_UNCORRBLKSH1r", 12027 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12028 "RX_X4_STATUS5_FEC_UNCORRECTEDBLKSH_1", 12029 NULL, 12030 #endif 12031 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12032 0x0, /* 0 */ 12033 0, 12034 #endif 12035 }, 12036 { 12037 BCMI_TSCF_XGXS_RX_X4_FEC_UNCORRBLKSH2r, 12038 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12039 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 12040 BCMI_TSCF_XGXS_RX_X4_FEC_UNCORRBLKSH2r_fields, 12041 #else 12042 0, 12043 #endif 12044 #endif 12045 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12046 PHYMOD_SYMBOL_FLAG_REGISTER, 12047 "RX_X4_FEC_UNCORRBLKSH2r", 12048 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12049 "RX_X4_STATUS5_FEC_UNCORRECTEDBLKSH_2", 12050 NULL, 12051 #endif 12052 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12053 0x0, /* 0 */ 12054 0, 12055 #endif 12056 }, 12057 { 12058 BCMI_TSCF_XGXS_RX_X4_FEC_UNCORRBLKSH3r, 12059 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12060 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 12061 BCMI_TSCF_XGXS_RX_X4_FEC_UNCORRBLKSH3r_fields, 12062 #else 12063 0, 12064 #endif 12065 #endif 12066 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12067 PHYMOD_SYMBOL_FLAG_REGISTER, 12068 "RX_X4_FEC_UNCORRBLKSH3r", 12069 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12070 "RX_X4_STATUS5_FEC_UNCORRECTEDBLKSH_3", 12071 NULL, 12072 #endif 12073 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12074 0x0, /* 0 */ 12075 0, 12076 #endif 12077 }, 12078 { 12079 BCMI_TSCF_XGXS_RX_X4_FEC_UNCORRBLKSH4r, 12080 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12081 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 12082 BCMI_TSCF_XGXS_RX_X4_FEC_UNCORRBLKSH4r_fields, 12083 #else 12084 0, 12085 #endif 12086 #endif 12087 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12088 PHYMOD_SYMBOL_FLAG_REGISTER, 12089 "RX_X4_FEC_UNCORRBLKSH4r", 12090 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12091 "RX_X4_STATUS5_FEC_UNCORRECTEDBLKSH_4", 12092 NULL, 12093 #endif 12094 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12095 0x0, /* 0 */ 12096 0, 12097 #endif 12098 }, 12099 { 12100 BCMI_TSCF_XGXS_TEST1_TXPKTCNT_Ur, 12101 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12102 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 12103 BCMI_TSCF_XGXS_TEST1_TXPKTCNT_Ur_fields, 12104 #else 12105 0, 12106 #endif 12107 #endif 12108 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12109 PHYMOD_SYMBOL_FLAG_REGISTER, 12110 "TEST1_TXPKTCNT_Ur", 12111 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12112 NULL, 12113 NULL, 12114 #endif 12115 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12116 0x0, /* 0 */ 12117 0, 12118 #endif 12119 }, 12120 { 12121 BCMI_TSCF_XGXS_TEST1_TXPKTCNT_Lr, 12122 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12123 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 12124 BCMI_TSCF_XGXS_TEST1_TXPKTCNT_Lr_fields, 12125 #else 12126 0, 12127 #endif 12128 #endif 12129 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12130 PHYMOD_SYMBOL_FLAG_REGISTER, 12131 "TEST1_TXPKTCNT_Lr", 12132 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12133 NULL, 12134 NULL, 12135 #endif 12136 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12137 0x0, /* 0 */ 12138 0, 12139 #endif 12140 }, 12141 { 12142 BCMI_TSCF_XGXS_TEST1_RXPKTCNT_Ur, 12143 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12144 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 12145 BCMI_TSCF_XGXS_TEST1_RXPKTCNT_Ur_fields, 12146 #else 12147 0, 12148 #endif 12149 #endif 12150 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12151 PHYMOD_SYMBOL_FLAG_REGISTER, 12152 "TEST1_RXPKTCNT_Ur", 12153 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12154 NULL, 12155 NULL, 12156 #endif 12157 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12158 0x0, /* 0 */ 12159 0, 12160 #endif 12161 }, 12162 { 12163 BCMI_TSCF_XGXS_TEST1_RXPKTCNT_Lr, 12164 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12165 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 12166 BCMI_TSCF_XGXS_TEST1_RXPKTCNT_Lr_fields, 12167 #else 12168 0, 12169 #endif 12170 #endif 12171 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12172 PHYMOD_SYMBOL_FLAG_REGISTER, 12173 "TEST1_RXPKTCNT_Lr", 12174 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12175 NULL, 12176 NULL, 12177 #endif 12178 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12179 0x0, /* 0 */ 12180 0, 12181 #endif 12182 }, 12183 { 12184 BCMI_TSCF_XGXS_AN_X4_CL73_CFGr, 12185 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12186 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 12187 BCMI_TSCF_XGXS_AN_X4_CL73_CFGr_fields, 12188 #else 12189 0, 12190 #endif 12191 #endif 12192 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12193 PHYMOD_SYMBOL_FLAG_REGISTER, 12194 "AN_X4_CL73_CFGr", 12195 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12196 "AN_X4_ABILITIES_CL73_CFG", 12197 NULL, 12198 #endif 12199 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12200 0x0, /* 0 */ 12201 0, 12202 #endif 12203 }, 12204 { 12205 BCMI_TSCF_XGXS_AN_X4_LD_UP1_ABIL0r, 12206 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12207 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 12208 BCMI_TSCF_XGXS_AN_X4_LD_UP1_ABIL0r_fields, 12209 #else 12210 0, 12211 #endif 12212 #endif 12213 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12214 PHYMOD_SYMBOL_FLAG_REGISTER, 12215 "AN_X4_LD_UP1_ABIL0r", 12216 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12217 "AN_X4_ABILITIES_LD_UP1_ABILITIES_0", 12218 NULL, 12219 #endif 12220 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12221 0x0, /* 0 */ 12222 0, 12223 #endif 12224 }, 12225 { 12226 BCMI_TSCF_XGXS_AN_X4_LD_UP1_ABIL1r, 12227 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12228 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 12229 BCMI_TSCF_XGXS_AN_X4_LD_UP1_ABIL1r_fields, 12230 #else 12231 0, 12232 #endif 12233 #endif 12234 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12235 PHYMOD_SYMBOL_FLAG_REGISTER, 12236 "AN_X4_LD_UP1_ABIL1r", 12237 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12238 "AN_X4_ABILITIES_LD_UP1_ABILITIES_1", 12239 NULL, 12240 #endif 12241 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12242 0x0, /* 0 */ 12243 0, 12244 #endif 12245 }, 12246 { 12247 BCMI_TSCF_XGXS_AN_X4_LD_BASE_ABIL0r, 12248 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12249 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 12250 BCMI_TSCF_XGXS_AN_X4_LD_BASE_ABIL0r_fields, 12251 #else 12252 0, 12253 #endif 12254 #endif 12255 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12256 PHYMOD_SYMBOL_FLAG_REGISTER, 12257 "AN_X4_LD_BASE_ABIL0r", 12258 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12259 "AN_X4_ABILITIES_LD_BASE_ABILITIES_0", 12260 NULL, 12261 #endif 12262 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12263 0x2a1, /* 673 */ 12264 0, 12265 #endif 12266 }, 12267 { 12268 BCMI_TSCF_XGXS_AN_X4_LD_BASE_ABIL1r, 12269 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12270 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 12271 BCMI_TSCF_XGXS_AN_X4_LD_BASE_ABIL1r_fields, 12272 #else 12273 0, 12274 #endif 12275 #endif 12276 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12277 PHYMOD_SYMBOL_FLAG_REGISTER, 12278 "AN_X4_LD_BASE_ABIL1r", 12279 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12280 "AN_X4_ABILITIES_LD_BASE_ABILITIES_1", 12281 NULL, 12282 #endif 12283 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12284 0x0, /* 0 */ 12285 0, 12286 #endif 12287 }, 12288 { 12289 BCMI_TSCF_XGXS_AN_X4_LD_BAM_ABILr, 12290 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12291 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 12292 BCMI_TSCF_XGXS_AN_X4_LD_BAM_ABILr_fields, 12293 #else 12294 0, 12295 #endif 12296 #endif 12297 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12298 PHYMOD_SYMBOL_FLAG_REGISTER, 12299 "AN_X4_LD_BAM_ABILr", 12300 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12301 "AN_X4_ABILITIES_LD_BAM_ABILITIES", 12302 NULL, 12303 #endif 12304 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12305 0x0, /* 0 */ 12306 0, 12307 #endif 12308 }, 12309 { 12310 BCMI_TSCF_XGXS_AN_X4_CL73_CTLSr, 12311 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12312 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 12313 BCMI_TSCF_XGXS_AN_X4_CL73_CTLSr_fields, 12314 #else 12315 0, 12316 #endif 12317 #endif 12318 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12319 PHYMOD_SYMBOL_FLAG_REGISTER, 12320 "AN_X4_CL73_CTLSr", 12321 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12322 "AN_X4_ABILITIES_CL73_CONTROLS", 12323 NULL, 12324 #endif 12325 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12326 0x0, /* 0 */ 12327 0, 12328 #endif 12329 }, 12330 { 12331 BCMI_TSCF_XGXS_AN_X4_R_CL73_STSr, 12332 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12333 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 12334 BCMI_TSCF_XGXS_AN_X4_R_CL73_STSr_fields, 12335 #else 12336 0, 12337 #endif 12338 #endif 12339 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12340 PHYMOD_SYMBOL_FLAG_REGISTER, 12341 "AN_X4_R_CL73_STSr", 12342 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12343 "AN_X4_STATUS_R_CL73_STATUS", 12344 NULL, 12345 #endif 12346 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12347 0x0, /* 0 */ 12348 0, 12349 #endif 12350 }, 12351 { 12352 BCMI_TSCF_XGXS_AN_X4_PXNG_STSr, 12353 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12354 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 12355 BCMI_TSCF_XGXS_AN_X4_PXNG_STSr_fields, 12356 #else 12357 0, 12358 #endif 12359 #endif 12360 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12361 PHYMOD_SYMBOL_FLAG_REGISTER, 12362 "AN_X4_PXNG_STSr", 12363 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12364 "AN_X4_STATUS_PXNG_STATUS", 12365 NULL, 12366 #endif 12367 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12368 0x0, /* 0 */ 12369 0, 12370 #endif 12371 }, 12372 { 12373 BCMI_TSCF_XGXS_AN_X4_PSEQ_STSr, 12374 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12375 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 12376 BCMI_TSCF_XGXS_AN_X4_PSEQ_STSr_fields, 12377 #else 12378 0, 12379 #endif 12380 #endif 12381 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12382 PHYMOD_SYMBOL_FLAG_REGISTER, 12383 "AN_X4_PSEQ_STSr", 12384 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12385 "AN_X4_STATUS_PSEQ_STATUS", 12386 NULL, 12387 #endif 12388 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12389 0x0, /* 0 */ 12390 0, 12391 #endif 12392 }, 12393 { 12394 BCMI_TSCF_XGXS_AN_X4_PSEQ_RFr, 12395 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12396 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 12397 BCMI_TSCF_XGXS_AN_X4_PSEQ_RFr_fields, 12398 #else 12399 0, 12400 #endif 12401 #endif 12402 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12403 PHYMOD_SYMBOL_FLAG_REGISTER, 12404 "AN_X4_PSEQ_RFr", 12405 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12406 "AN_X4_STATUS_PSEQ_RF", 12407 NULL, 12408 #endif 12409 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12410 0x0, /* 0 */ 12411 0, 12412 #endif 12413 }, 12414 { 12415 BCMI_TSCF_XGXS_AN_X4_UNEXP_PAGEr, 12416 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12417 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 12418 BCMI_TSCF_XGXS_AN_X4_UNEXP_PAGEr_fields, 12419 #else 12420 0, 12421 #endif 12422 #endif 12423 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12424 PHYMOD_SYMBOL_FLAG_REGISTER, 12425 "AN_X4_UNEXP_PAGEr", 12426 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12427 "AN_X4_STATUS_UNEXP_PAGE", 12428 NULL, 12429 #endif 12430 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12431 0x0, /* 0 */ 12432 0, 12433 #endif 12434 }, 12435 { 12436 BCMI_TSCF_XGXS_AN_X4_LP_BASE1r, 12437 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12438 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 12439 BCMI_TSCF_XGXS_AN_X4_LP_BASE1r_fields, 12440 #else 12441 0, 12442 #endif 12443 #endif 12444 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12445 PHYMOD_SYMBOL_FLAG_REGISTER, 12446 "AN_X4_LP_BASE1r", 12447 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12448 "AN_X4_STATUS_LP_BASE1", 12449 NULL, 12450 #endif 12451 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12452 0x0, /* 0 */ 12453 0, 12454 #endif 12455 }, 12456 { 12457 BCMI_TSCF_XGXS_AN_X4_LP_BASE2r, 12458 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12459 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 12460 BCMI_TSCF_XGXS_AN_X4_LP_BASE2r_fields, 12461 #else 12462 0, 12463 #endif 12464 #endif 12465 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12466 PHYMOD_SYMBOL_FLAG_REGISTER, 12467 "AN_X4_LP_BASE2r", 12468 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12469 "AN_X4_STATUS_LP_BASE2", 12470 NULL, 12471 #endif 12472 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12473 0x0, /* 0 */ 12474 0, 12475 #endif 12476 }, 12477 { 12478 BCMI_TSCF_XGXS_AN_X4_LP_BASE3r, 12479 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12480 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 12481 BCMI_TSCF_XGXS_AN_X4_LP_BASE3r_fields, 12482 #else 12483 0, 12484 #endif 12485 #endif 12486 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12487 PHYMOD_SYMBOL_FLAG_REGISTER, 12488 "AN_X4_LP_BASE3r", 12489 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12490 "AN_X4_STATUS_LP_BASE3", 12491 NULL, 12492 #endif 12493 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12494 0x0, /* 0 */ 12495 0, 12496 #endif 12497 }, 12498 { 12499 BCMI_TSCF_XGXS_AN_X4_LP_OUI_UP1r, 12500 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12501 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 12502 BCMI_TSCF_XGXS_AN_X4_LP_OUI_UP1r_fields, 12503 #else 12504 0, 12505 #endif 12506 #endif 12507 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12508 PHYMOD_SYMBOL_FLAG_REGISTER, 12509 "AN_X4_LP_OUI_UP1r", 12510 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12511 "AN_X4_STATUS_LP_OUI_UP1", 12512 NULL, 12513 #endif 12514 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12515 0x0, /* 0 */ 12516 0, 12517 #endif 12518 }, 12519 { 12520 BCMI_TSCF_XGXS_AN_X4_LP_OUI_UP2r, 12521 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12522 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 12523 BCMI_TSCF_XGXS_AN_X4_LP_OUI_UP2r_fields, 12524 #else 12525 0, 12526 #endif 12527 #endif 12528 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12529 PHYMOD_SYMBOL_FLAG_REGISTER, 12530 "AN_X4_LP_OUI_UP2r", 12531 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12532 "AN_X4_STATUS_LP_OUI_UP2", 12533 NULL, 12534 #endif 12535 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12536 0x0, /* 0 */ 12537 0, 12538 #endif 12539 }, 12540 { 12541 BCMI_TSCF_XGXS_AN_X4_LP_OUI_UP3r, 12542 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12543 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 12544 BCMI_TSCF_XGXS_AN_X4_LP_OUI_UP3r_fields, 12545 #else 12546 0, 12547 #endif 12548 #endif 12549 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12550 PHYMOD_SYMBOL_FLAG_REGISTER, 12551 "AN_X4_LP_OUI_UP3r", 12552 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12553 "AN_X4_STATUS_LP_OUI_UP3", 12554 NULL, 12555 #endif 12556 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12557 0x0, /* 0 */ 12558 0, 12559 #endif 12560 }, 12561 { 12562 BCMI_TSCF_XGXS_AN_X4_LP_OUI_UP4r, 12563 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12564 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 12565 BCMI_TSCF_XGXS_AN_X4_LP_OUI_UP4r_fields, 12566 #else 12567 0, 12568 #endif 12569 #endif 12570 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12571 PHYMOD_SYMBOL_FLAG_REGISTER, 12572 "AN_X4_LP_OUI_UP4r", 12573 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12574 "AN_X4_STATUS_LP_OUI_UP4", 12575 NULL, 12576 #endif 12577 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12578 0x0, /* 0 */ 12579 0, 12580 #endif 12581 }, 12582 { 12583 BCMI_TSCF_XGXS_AN_X4_LP_OUI_UP5r, 12584 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12585 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 12586 BCMI_TSCF_XGXS_AN_X4_LP_OUI_UP5r_fields, 12587 #else 12588 0, 12589 #endif 12590 #endif 12591 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12592 PHYMOD_SYMBOL_FLAG_REGISTER, 12593 "AN_X4_LP_OUI_UP5r", 12594 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12595 "AN_X4_STATUS_LP_OUI_UP5", 12596 NULL, 12597 #endif 12598 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12599 0x0, /* 0 */ 12600 0, 12601 #endif 12602 }, 12603 { 12604 BCMI_TSCF_XGXS_AN_X4_RES_ERRr, 12605 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12606 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 12607 BCMI_TSCF_XGXS_AN_X4_RES_ERRr_fields, 12608 #else 12609 0, 12610 #endif 12611 #endif 12612 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12613 PHYMOD_SYMBOL_FLAG_REGISTER, 12614 "AN_X4_RES_ERRr", 12615 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12616 "AN_X4_STATUS_RES_ERR", 12617 NULL, 12618 #endif 12619 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12620 0x0, /* 0 */ 12621 0, 12622 #endif 12623 }, 12624 { 12625 BCMI_TSCF_XGXS_AN_X4_LD_PAGE2r, 12626 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12627 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 12628 BCMI_TSCF_XGXS_AN_X4_LD_PAGE2r_fields, 12629 #else 12630 0, 12631 #endif 12632 #endif 12633 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12634 PHYMOD_SYMBOL_FLAG_REGISTER, 12635 "AN_X4_LD_PAGE2r", 12636 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12637 "AN_X4_SW_MGMT_LD_PAGE_2", 12638 NULL, 12639 #endif 12640 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12641 0x0, /* 0 */ 12642 0, 12643 #endif 12644 }, 12645 { 12646 BCMI_TSCF_XGXS_AN_X4_LD_PAGE1r, 12647 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12648 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 12649 BCMI_TSCF_XGXS_AN_X4_LD_PAGE1r_fields, 12650 #else 12651 0, 12652 #endif 12653 #endif 12654 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12655 PHYMOD_SYMBOL_FLAG_REGISTER, 12656 "AN_X4_LD_PAGE1r", 12657 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12658 "AN_X4_SW_MGMT_LD_PAGE_1", 12659 NULL, 12660 #endif 12661 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12662 0x0, /* 0 */ 12663 0, 12664 #endif 12665 }, 12666 { 12667 BCMI_TSCF_XGXS_AN_X4_LD_PAGE0r, 12668 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12669 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 12670 BCMI_TSCF_XGXS_AN_X4_LD_PAGE0r_fields, 12671 #else 12672 0, 12673 #endif 12674 #endif 12675 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12676 PHYMOD_SYMBOL_FLAG_REGISTER, 12677 "AN_X4_LD_PAGE0r", 12678 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12679 "AN_X4_SW_MGMT_LD_PAGE_0", 12680 NULL, 12681 #endif 12682 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12683 0x0, /* 0 */ 12684 0, 12685 #endif 12686 }, 12687 { 12688 BCMI_TSCF_XGXS_AN_X4_LP_PAGE2r, 12689 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12690 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 12691 BCMI_TSCF_XGXS_AN_X4_LP_PAGE2r_fields, 12692 #else 12693 0, 12694 #endif 12695 #endif 12696 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12697 PHYMOD_SYMBOL_FLAG_REGISTER, 12698 "AN_X4_LP_PAGE2r", 12699 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12700 "AN_X4_SW_MGMT_LP_PAGE_2", 12701 NULL, 12702 #endif 12703 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12704 0x0, /* 0 */ 12705 0, 12706 #endif 12707 }, 12708 { 12709 BCMI_TSCF_XGXS_AN_X4_LP_PAGE1r, 12710 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12711 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 12712 BCMI_TSCF_XGXS_AN_X4_LP_PAGE1r_fields, 12713 #else 12714 0, 12715 #endif 12716 #endif 12717 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12718 PHYMOD_SYMBOL_FLAG_REGISTER, 12719 "AN_X4_LP_PAGE1r", 12720 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12721 "AN_X4_SW_MGMT_LP_PAGE_1", 12722 NULL, 12723 #endif 12724 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12725 0x0, /* 0 */ 12726 0, 12727 #endif 12728 }, 12729 { 12730 BCMI_TSCF_XGXS_AN_X4_LP_PAGE0r, 12731 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12732 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 12733 BCMI_TSCF_XGXS_AN_X4_LP_PAGE0r_fields, 12734 #else 12735 0, 12736 #endif 12737 #endif 12738 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12739 PHYMOD_SYMBOL_FLAG_REGISTER, 12740 "AN_X4_LP_PAGE0r", 12741 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12742 "AN_X4_SW_MGMT_LP_PAGE_0", 12743 NULL, 12744 #endif 12745 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12746 0x0, /* 0 */ 12747 0, 12748 #endif 12749 }, 12750 { 12751 BCMI_TSCF_XGXS_AN_X4_SW_CTL_STSr, 12752 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12753 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 12754 BCMI_TSCF_XGXS_AN_X4_SW_CTL_STSr_fields, 12755 #else 12756 0, 12757 #endif 12758 #endif 12759 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12760 PHYMOD_SYMBOL_FLAG_REGISTER, 12761 "AN_X4_SW_CTL_STSr", 12762 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12763 "AN_X4_SW_MGMT_SW_CONTROL_STATUS", 12764 NULL, 12765 #endif 12766 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12767 0x0, /* 0 */ 12768 0, 12769 #endif 12770 }, 12771 { 12772 BCMI_TSCF_XGXS_AN_X4_LD_CTLr, 12773 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12774 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 12775 BCMI_TSCF_XGXS_AN_X4_LD_CTLr_fields, 12776 #else 12777 0, 12778 #endif 12779 #endif 12780 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12781 PHYMOD_SYMBOL_FLAG_REGISTER, 12782 "AN_X4_LD_CTLr", 12783 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12784 "AN_X4_SW_MGMT_LD_CONTROL", 12785 NULL, 12786 #endif 12787 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12788 0x0, /* 0 */ 12789 0, 12790 #endif 12791 }, 12792 { 12793 BCMI_TSCF_XGXS_AN_X4_AN_ABIL_RESOLUTION_STSr, 12794 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12795 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 12796 BCMI_TSCF_XGXS_AN_X4_AN_ABIL_RESOLUTION_STSr_fields, 12797 #else 12798 0, 12799 #endif 12800 #endif 12801 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12802 PHYMOD_SYMBOL_FLAG_REGISTER, 12803 "AN_X4_AN_ABIL_RESOLUTION_STSr", 12804 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12805 "AN_X4_SW_MGMT_AN_ABILITY_RESOLUTION_STATUS", 12806 NULL, 12807 #endif 12808 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12809 0x120, /* 288 */ 12810 0, 12811 #endif 12812 }, 12813 { 12814 BCMI_TSCF_XGXS_AN_X4_AN_MISC_STSr, 12815 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12816 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 12817 BCMI_TSCF_XGXS_AN_X4_AN_MISC_STSr_fields, 12818 #else 12819 0, 12820 #endif 12821 #endif 12822 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12823 PHYMOD_SYMBOL_FLAG_REGISTER, 12824 "AN_X4_AN_MISC_STSr", 12825 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12826 "AN_X4_SW_MGMT_AN_MISC_STATUS", 12827 NULL, 12828 #endif 12829 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12830 0x0, /* 0 */ 12831 0, 12832 #endif 12833 }, 12834 { 12835 BCMI_TSCF_XGXS_AN_X4_TLA_SEQUENCER_STSr, 12836 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12837 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 12838 BCMI_TSCF_XGXS_AN_X4_TLA_SEQUENCER_STSr_fields, 12839 #else 12840 0, 12841 #endif 12842 #endif 12843 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12844 PHYMOD_SYMBOL_FLAG_REGISTER, 12845 "AN_X4_TLA_SEQUENCER_STSr", 12846 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12847 "AN_X4_SW_MGMT_TLA_SEQUENCER_STATUS", 12848 NULL, 12849 #endif 12850 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12851 0x1, /* 1 */ 12852 0, 12853 #endif 12854 }, 12855 { 12856 BCMI_TSCF_XGXS_ILKN_CTL0r, 12857 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12858 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 12859 BCMI_TSCF_XGXS_ILKN_CTL0r_fields, 12860 #else 12861 0, 12862 #endif 12863 #endif 12864 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12865 PHYMOD_SYMBOL_FLAG_REGISTER, 12866 "ILKN_CTL0r", 12867 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12868 "ILKN_CONTROL0_ILKN_CONTROL0", 12869 NULL, 12870 #endif 12871 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12872 0x4, /* 4 */ 12873 0, 12874 #endif 12875 }, 12876 { 12877 BCMI_TSCF_XGXS_ILKN_STS0r, 12878 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12879 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 12880 BCMI_TSCF_XGXS_ILKN_STS0r_fields, 12881 #else 12882 0, 12883 #endif 12884 #endif 12885 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12886 PHYMOD_SYMBOL_FLAG_REGISTER, 12887 "ILKN_STS0r", 12888 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12889 "ILKN_STATUS0_ILKN_STATUS0", 12890 NULL, 12891 #endif 12892 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12893 0x11, /* 17 */ 12894 0, 12895 #endif 12896 }, 12897 { 12898 BCMI_TSCF_XGXS_ACC_CTLr, 12899 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12900 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 12901 BCMI_TSCF_XGXS_ACC_CTLr_fields, 12902 #else 12903 0, 12904 #endif 12905 #endif 12906 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12907 PHYMOD_SYMBOL_FLAG_REGISTER, 12908 "ACC_CTLr", 12909 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12910 "MDIO_CL22_IEEE_COM_ACC_CTRL", 12911 NULL, 12912 #endif 12913 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12914 0x0, /* 0 */ 12915 0, 12916 #endif 12917 }, 12918 { 12919 BCMI_TSCF_XGXS_ACC_ADDR_DATAr, 12920 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12921 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 12922 BCMI_TSCF_XGXS_ACC_ADDR_DATAr_fields, 12923 #else 12924 0, 12925 #endif 12926 #endif 12927 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12928 PHYMOD_SYMBOL_FLAG_REGISTER, 12929 "ACC_ADDR_DATAr", 12930 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12931 "MDIO_CL22_IEEE_COM_ACC_ADDR_DATA", 12932 NULL, 12933 #endif 12934 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12935 0x0, /* 0 */ 12936 0, 12937 #endif 12938 }, 12939 { 12940 BCMI_TSCF_XGXS_CL93N72_IT_BASE_R_PMD_CTLr, 12941 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12942 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 12943 BCMI_TSCF_XGXS_CL93N72_IT_BASE_R_PMD_CTLr_fields, 12944 #else 12945 0, 12946 #endif 12947 #endif 12948 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12949 PHYMOD_SYMBOL_FLAG_REGISTER, 12950 "CL93N72_IT_BASE_R_PMD_CTLr", 12951 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12952 "CL93N72_IEEE_TX_CL93N72IT_BASE_R_PMD_CONTROL_REGISTER_150", 12953 NULL, 12954 #endif 12955 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12956 0x0, /* 0 */ 12957 0, 12958 #endif 12959 }, 12960 { 12961 BCMI_TSCF_XGXS_CL93N72_IT_BASE_R_PMD_STSr, 12962 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12963 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 12964 BCMI_TSCF_XGXS_CL93N72_IT_BASE_R_PMD_STSr_fields, 12965 #else 12966 0, 12967 #endif 12968 #endif 12969 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12970 PHYMOD_SYMBOL_FLAG_REGISTER, 12971 "CL93N72_IT_BASE_R_PMD_STSr", 12972 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12973 "CL93N72_IEEE_TX_CL93N72IT_BASE_R_PMD_STATUS_REGISTER_151", 12974 NULL, 12975 #endif 12976 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12977 0x0, /* 0 */ 12978 0, 12979 #endif 12980 }, 12981 { 12982 BCMI_TSCF_XGXS_CL93N72_IR_BASE_R_LP_COEFF_UPDr, 12983 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12984 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 12985 BCMI_TSCF_XGXS_CL93N72_IR_BASE_R_LP_COEFF_UPDr_fields, 12986 #else 12987 0, 12988 #endif 12989 #endif 12990 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12991 PHYMOD_SYMBOL_FLAG_REGISTER, 12992 "CL93N72_IR_BASE_R_LP_COEFF_UPDr", 12993 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12994 "CL93N72_IEEE_RX_CL93N72IR_BASE_R_LP_COEFF_UPDATE_REGISTER_152", 12995 NULL, 12996 #endif 12997 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12998 0x0, /* 0 */ 12999 0, 13000 #endif 13001 }, 13002 { 13003 BCMI_TSCF_XGXS_CL93N72_IR_BASE_R_LP_STS_REPr, 13004 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13005 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 13006 BCMI_TSCF_XGXS_CL93N72_IR_BASE_R_LP_STS_REPr_fields, 13007 #else 13008 0, 13009 #endif 13010 #endif 13011 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13012 PHYMOD_SYMBOL_FLAG_REGISTER, 13013 "CL93N72_IR_BASE_R_LP_STS_REPr", 13014 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13015 "CL93N72_IEEE_RX_CL93N72IR_BASE_R_LP_STATUS_REPORT_REGISTER_153", 13016 NULL, 13017 #endif 13018 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13019 0x0, /* 0 */ 13020 0, 13021 #endif 13022 }, 13023 { 13024 BCMI_TSCF_XGXS_CL93N72_IT_BASE_R_LD_COEFF_UPDr, 13025 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13026 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 13027 BCMI_TSCF_XGXS_CL93N72_IT_BASE_R_LD_COEFF_UPDr_fields, 13028 #else 13029 0, 13030 #endif 13031 #endif 13032 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13033 PHYMOD_SYMBOL_FLAG_REGISTER, 13034 "CL93N72_IT_BASE_R_LD_COEFF_UPDr", 13035 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13036 "CL93N72_IEEE_TX_CL93N72IT_BASE_R_LD_COEFF_UPDATE_REGISTER_154", 13037 NULL, 13038 #endif 13039 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13040 0x0, /* 0 */ 13041 0, 13042 #endif 13043 }, 13044 { 13045 BCMI_TSCF_XGXS_CL93N72_IT_BASE_R_LD_STS_REPr, 13046 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13047 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 13048 BCMI_TSCF_XGXS_CL93N72_IT_BASE_R_LD_STS_REPr_fields, 13049 #else 13050 0, 13051 #endif 13052 #endif 13053 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13054 PHYMOD_SYMBOL_FLAG_REGISTER, 13055 "CL93N72_IT_BASE_R_LD_STS_REPr", 13056 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13057 "CL93N72_IEEE_TX_CL93N72IT_BASE_R_LD_STATUS_REPORT_REGISTER_155", 13058 NULL, 13059 #endif 13060 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13061 0x0, /* 0 */ 13062 0, 13063 #endif 13064 }, 13065 { 13066 BCMI_TSCF_XGXS_DSC_RX_PF_CTL_DC_OFFSr, 13067 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13068 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 13069 BCMI_TSCF_XGXS_DSC_RX_PF_CTL_DC_OFFSr_fields, 13070 #else 13071 0, 13072 #endif 13073 #endif 13074 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13075 PHYMOD_SYMBOL_FLAG_REGISTER, 13076 "DSC_RX_PF_CTL_DC_OFFSr", 13077 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13078 "DSC_AFE1_RX_PF_CTRL_DC_OFFSET", 13079 NULL, 13080 #endif 13081 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13082 0x0, /* 0 */ 13083 0, 13084 #endif 13085 }, 13086 { 13087 BCMI_TSCF_XGXS_DSC_RXA_SLCR_OFFS_ADJ_DN_DPr, 13088 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13089 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 13090 BCMI_TSCF_XGXS_DSC_RXA_SLCR_OFFS_ADJ_DN_DPr_fields, 13091 #else 13092 0, 13093 #endif 13094 #endif 13095 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13096 PHYMOD_SYMBOL_FLAG_REGISTER, 13097 "DSC_RXA_SLCR_OFFS_ADJ_DN_DPr", 13098 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13099 "DSC_AFE1_RXA_SLICER_OFFSET_ADJ_DN_DP", 13100 NULL, 13101 #endif 13102 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13103 0x0, /* 0 */ 13104 0, 13105 #endif 13106 }, 13107 { 13108 BCMI_TSCF_XGXS_DSC_RXA_SLCR_OFFS_ADJ_ZN_ZPr, 13109 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13110 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 13111 BCMI_TSCF_XGXS_DSC_RXA_SLCR_OFFS_ADJ_ZN_ZPr_fields, 13112 #else 13113 0, 13114 #endif 13115 #endif 13116 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13117 PHYMOD_SYMBOL_FLAG_REGISTER, 13118 "DSC_RXA_SLCR_OFFS_ADJ_ZN_ZPr", 13119 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13120 "DSC_AFE1_RXA_SLICER_OFFSET_ADJ_ZN_ZP", 13121 NULL, 13122 #endif 13123 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13124 0x0, /* 0 */ 13125 0, 13126 #endif 13127 }, 13128 { 13129 BCMI_TSCF_XGXS_DSC_RXAB_SLCR_OFFS_ADJ_LMSr, 13130 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13131 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 13132 BCMI_TSCF_XGXS_DSC_RXAB_SLCR_OFFS_ADJ_LMSr_fields, 13133 #else 13134 0, 13135 #endif 13136 #endif 13137 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13138 PHYMOD_SYMBOL_FLAG_REGISTER, 13139 "DSC_RXAB_SLCR_OFFS_ADJ_LMSr", 13140 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13141 "DSC_AFE1_RXAB_SLICER_OFFSET_ADJ_LMS", 13142 NULL, 13143 #endif 13144 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13145 0x0, /* 0 */ 13146 0, 13147 #endif 13148 }, 13149 { 13150 BCMI_TSCF_XGXS_DSC_RXB_SLCR_OFFS_ADJ_DN_DPr, 13151 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13152 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 13153 BCMI_TSCF_XGXS_DSC_RXB_SLCR_OFFS_ADJ_DN_DPr_fields, 13154 #else 13155 0, 13156 #endif 13157 #endif 13158 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13159 PHYMOD_SYMBOL_FLAG_REGISTER, 13160 "DSC_RXB_SLCR_OFFS_ADJ_DN_DPr", 13161 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13162 "DSC_AFE1_RXB_SLICER_OFFSET_ADJ_DN_DP", 13163 NULL, 13164 #endif 13165 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13166 0x0, /* 0 */ 13167 0, 13168 #endif 13169 }, 13170 { 13171 BCMI_TSCF_XGXS_DSC_RXB_SLCR_OFFS_ADJ_ZN_ZPr, 13172 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13173 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 13174 BCMI_TSCF_XGXS_DSC_RXB_SLCR_OFFS_ADJ_ZN_ZPr_fields, 13175 #else 13176 0, 13177 #endif 13178 #endif 13179 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13180 PHYMOD_SYMBOL_FLAG_REGISTER, 13181 "DSC_RXB_SLCR_OFFS_ADJ_ZN_ZPr", 13182 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13183 "DSC_AFE1_RXB_SLICER_OFFSET_ADJ_ZN_ZP", 13184 NULL, 13185 #endif 13186 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13187 0x0, /* 0 */ 13188 0, 13189 #endif 13190 }, 13191 { 13192 BCMI_TSCF_XGXS_DSC_RXC_SLCR_OFFS_ADJ_DN_DPr, 13193 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13194 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 13195 BCMI_TSCF_XGXS_DSC_RXC_SLCR_OFFS_ADJ_DN_DPr_fields, 13196 #else 13197 0, 13198 #endif 13199 #endif 13200 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13201 PHYMOD_SYMBOL_FLAG_REGISTER, 13202 "DSC_RXC_SLCR_OFFS_ADJ_DN_DPr", 13203 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13204 "DSC_AFE1_RXC_SLICER_OFFSET_ADJ_DN_DP", 13205 NULL, 13206 #endif 13207 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13208 0x0, /* 0 */ 13209 0, 13210 #endif 13211 }, 13212 { 13213 BCMI_TSCF_XGXS_DSC_RXC_SLCR_OFFS_ADJ_ZN_ZPr, 13214 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13215 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 13216 BCMI_TSCF_XGXS_DSC_RXC_SLCR_OFFS_ADJ_ZN_ZPr_fields, 13217 #else 13218 0, 13219 #endif 13220 #endif 13221 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13222 PHYMOD_SYMBOL_FLAG_REGISTER, 13223 "DSC_RXC_SLCR_OFFS_ADJ_ZN_ZPr", 13224 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13225 "DSC_AFE1_RXC_SLICER_OFFSET_ADJ_ZN_ZP", 13226 NULL, 13227 #endif 13228 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13229 0x0, /* 0 */ 13230 0, 13231 #endif 13232 }, 13233 { 13234 BCMI_TSCF_XGXS_DSC_RXCD_SLCR_OFFS_ADJ_LMSr, 13235 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13236 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 13237 BCMI_TSCF_XGXS_DSC_RXCD_SLCR_OFFS_ADJ_LMSr_fields, 13238 #else 13239 0, 13240 #endif 13241 #endif 13242 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13243 PHYMOD_SYMBOL_FLAG_REGISTER, 13244 "DSC_RXCD_SLCR_OFFS_ADJ_LMSr", 13245 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13246 "DSC_AFE1_RXCD_SLICER_OFFSET_ADJ_LMS", 13247 NULL, 13248 #endif 13249 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13250 0x0, /* 0 */ 13251 0, 13252 #endif 13253 }, 13254 { 13255 BCMI_TSCF_XGXS_DSC_RXD_SLCR_OFFS_ADJ_DN_DPr, 13256 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13257 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 13258 BCMI_TSCF_XGXS_DSC_RXD_SLCR_OFFS_ADJ_DN_DPr_fields, 13259 #else 13260 0, 13261 #endif 13262 #endif 13263 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13264 PHYMOD_SYMBOL_FLAG_REGISTER, 13265 "DSC_RXD_SLCR_OFFS_ADJ_DN_DPr", 13266 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13267 "DSC_AFE1_RXD_SLICER_OFFSET_ADJ_DN_DP", 13268 NULL, 13269 #endif 13270 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13271 0x0, /* 0 */ 13272 0, 13273 #endif 13274 }, 13275 { 13276 BCMI_TSCF_XGXS_DSC_RXD_SLCR_OFFS_ADJ_ZN_ZPr, 13277 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13278 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 13279 BCMI_TSCF_XGXS_DSC_RXD_SLCR_OFFS_ADJ_ZN_ZPr_fields, 13280 #else 13281 0, 13282 #endif 13283 #endif 13284 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13285 PHYMOD_SYMBOL_FLAG_REGISTER, 13286 "DSC_RXD_SLCR_OFFS_ADJ_ZN_ZPr", 13287 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13288 "DSC_AFE1_RXD_SLICER_OFFSET_ADJ_ZN_ZP", 13289 NULL, 13290 #endif 13291 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13292 0x0, /* 0 */ 13293 0, 13294 #endif 13295 }, 13296 { 13297 BCMI_TSCF_XGXS_DSC_RX_PHASE_LMS_THR_SELr, 13298 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13299 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 13300 BCMI_TSCF_XGXS_DSC_RX_PHASE_LMS_THR_SELr_fields, 13301 #else 13302 0, 13303 #endif 13304 #endif 13305 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13306 PHYMOD_SYMBOL_FLAG_REGISTER, 13307 "DSC_RX_PHASE_LMS_THR_SELr", 13308 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13309 "DSC_AFE1_RX_PHASE_LMS_THRESH_SEL", 13310 NULL, 13311 #endif 13312 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13313 0x0, /* 0 */ 13314 0, 13315 #endif 13316 }, 13317 { 13318 BCMI_TSCF_XGXS_DSC_RX_DFE_TAP2_ABr, 13319 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13320 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 13321 BCMI_TSCF_XGXS_DSC_RX_DFE_TAP2_ABr_fields, 13322 #else 13323 0, 13324 #endif 13325 #endif 13326 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13327 PHYMOD_SYMBOL_FLAG_REGISTER, 13328 "DSC_RX_DFE_TAP2_ABr", 13329 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13330 "DSC_AFE2_RX_DFE_TAP2_AB", 13331 NULL, 13332 #endif 13333 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13334 0x0, /* 0 */ 13335 0, 13336 #endif 13337 }, 13338 { 13339 BCMI_TSCF_XGXS_DSC_RX_DFE_TAP2_CDr, 13340 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13341 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 13342 BCMI_TSCF_XGXS_DSC_RX_DFE_TAP2_CDr_fields, 13343 #else 13344 0, 13345 #endif 13346 #endif 13347 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13348 PHYMOD_SYMBOL_FLAG_REGISTER, 13349 "DSC_RX_DFE_TAP2_CDr", 13350 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13351 "DSC_AFE2_RX_DFE_TAP2_CD", 13352 NULL, 13353 #endif 13354 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13355 0x0, /* 0 */ 13356 0, 13357 #endif 13358 }, 13359 { 13360 BCMI_TSCF_XGXS_DSC_RX_DFE_TAP3_ABr, 13361 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13362 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 13363 BCMI_TSCF_XGXS_DSC_RX_DFE_TAP3_ABr_fields, 13364 #else 13365 0, 13366 #endif 13367 #endif 13368 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13369 PHYMOD_SYMBOL_FLAG_REGISTER, 13370 "DSC_RX_DFE_TAP3_ABr", 13371 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13372 "DSC_AFE2_RX_DFE_TAP3_AB", 13373 NULL, 13374 #endif 13375 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13376 0x0, /* 0 */ 13377 0, 13378 #endif 13379 }, 13380 { 13381 BCMI_TSCF_XGXS_DSC_RX_DFE_TAP3_CDr, 13382 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13383 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 13384 BCMI_TSCF_XGXS_DSC_RX_DFE_TAP3_CDr_fields, 13385 #else 13386 0, 13387 #endif 13388 #endif 13389 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13390 PHYMOD_SYMBOL_FLAG_REGISTER, 13391 "DSC_RX_DFE_TAP3_CDr", 13392 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13393 "DSC_AFE2_RX_DFE_TAP3_CD", 13394 NULL, 13395 #endif 13396 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13397 0x0, /* 0 */ 13398 0, 13399 #endif 13400 }, 13401 { 13402 BCMI_TSCF_XGXS_DSC_RX_DFE_TAP4_ABCDr, 13403 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13404 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 13405 BCMI_TSCF_XGXS_DSC_RX_DFE_TAP4_ABCDr_fields, 13406 #else 13407 0, 13408 #endif 13409 #endif 13410 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13411 PHYMOD_SYMBOL_FLAG_REGISTER, 13412 "DSC_RX_DFE_TAP4_ABCDr", 13413 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13414 "DSC_AFE2_RX_DFE_TAP4_ABCD", 13415 NULL, 13416 #endif 13417 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13418 0x0, /* 0 */ 13419 0, 13420 #endif 13421 }, 13422 { 13423 BCMI_TSCF_XGXS_DSC_RX_DFE_TAP5_ABCDr, 13424 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13425 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 13426 BCMI_TSCF_XGXS_DSC_RX_DFE_TAP5_ABCDr_fields, 13427 #else 13428 0, 13429 #endif 13430 #endif 13431 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13432 PHYMOD_SYMBOL_FLAG_REGISTER, 13433 "DSC_RX_DFE_TAP5_ABCDr", 13434 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13435 "DSC_AFE2_RX_DFE_TAP5_ABCD", 13436 NULL, 13437 #endif 13438 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13439 0x0, /* 0 */ 13440 0, 13441 #endif 13442 }, 13443 { 13444 BCMI_TSCF_XGXS_DSC_RX_DFE_TAP6_ABCDr, 13445 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13446 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 13447 BCMI_TSCF_XGXS_DSC_RX_DFE_TAP6_ABCDr_fields, 13448 #else 13449 0, 13450 #endif 13451 #endif 13452 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13453 PHYMOD_SYMBOL_FLAG_REGISTER, 13454 "DSC_RX_DFE_TAP6_ABCDr", 13455 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13456 "DSC_AFE2_RX_DFE_TAP6_ABCD", 13457 NULL, 13458 #endif 13459 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13460 0x0, /* 0 */ 13461 0, 13462 #endif 13463 }, 13464 { 13465 BCMI_TSCF_XGXS_DSC_RX_DFE_TAP7_ABCDr, 13466 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13467 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 13468 BCMI_TSCF_XGXS_DSC_RX_DFE_TAP7_ABCDr_fields, 13469 #else 13470 0, 13471 #endif 13472 #endif 13473 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13474 PHYMOD_SYMBOL_FLAG_REGISTER, 13475 "DSC_RX_DFE_TAP7_ABCDr", 13476 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13477 "DSC_AFE2_RX_DFE_TAP7_ABCD", 13478 NULL, 13479 #endif 13480 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13481 0x0, /* 0 */ 13482 0, 13483 #endif 13484 }, 13485 { 13486 BCMI_TSCF_XGXS_DSC_RX_DFE_TAP8_ABCDr, 13487 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13488 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 13489 BCMI_TSCF_XGXS_DSC_RX_DFE_TAP8_ABCDr_fields, 13490 #else 13491 0, 13492 #endif 13493 #endif 13494 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13495 PHYMOD_SYMBOL_FLAG_REGISTER, 13496 "DSC_RX_DFE_TAP8_ABCDr", 13497 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13498 "DSC_AFE2_RX_DFE_TAP8_ABCD", 13499 NULL, 13500 #endif 13501 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13502 0x0, /* 0 */ 13503 0, 13504 #endif 13505 }, 13506 { 13507 BCMI_TSCF_XGXS_DSC_RX_DFE_TAP9_ABCDr, 13508 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13509 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 13510 BCMI_TSCF_XGXS_DSC_RX_DFE_TAP9_ABCDr_fields, 13511 #else 13512 0, 13513 #endif 13514 #endif 13515 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13516 PHYMOD_SYMBOL_FLAG_REGISTER, 13517 "DSC_RX_DFE_TAP9_ABCDr", 13518 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13519 "DSC_AFE2_RX_DFE_TAP9_ABCD", 13520 NULL, 13521 #endif 13522 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13523 0x0, /* 0 */ 13524 0, 13525 #endif 13526 }, 13527 { 13528 BCMI_TSCF_XGXS_DSC_RX_DFE_TAP10_ABCDr, 13529 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13530 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 13531 BCMI_TSCF_XGXS_DSC_RX_DFE_TAP10_ABCDr_fields, 13532 #else 13533 0, 13534 #endif 13535 #endif 13536 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13537 PHYMOD_SYMBOL_FLAG_REGISTER, 13538 "DSC_RX_DFE_TAP10_ABCDr", 13539 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13540 "DSC_AFE3_RX_DFE_TAP10_ABCD", 13541 NULL, 13542 #endif 13543 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13544 0x0, /* 0 */ 13545 0, 13546 #endif 13547 }, 13548 { 13549 BCMI_TSCF_XGXS_DSC_RX_DFE_TAP11_ABCDr, 13550 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13551 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 13552 BCMI_TSCF_XGXS_DSC_RX_DFE_TAP11_ABCDr_fields, 13553 #else 13554 0, 13555 #endif 13556 #endif 13557 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13558 PHYMOD_SYMBOL_FLAG_REGISTER, 13559 "DSC_RX_DFE_TAP11_ABCDr", 13560 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13561 "DSC_AFE3_RX_DFE_TAP11_ABCD", 13562 NULL, 13563 #endif 13564 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13565 0x0, /* 0 */ 13566 0, 13567 #endif 13568 }, 13569 { 13570 BCMI_TSCF_XGXS_DSC_RX_DFE_TAP12_ABCDr, 13571 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13572 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 13573 BCMI_TSCF_XGXS_DSC_RX_DFE_TAP12_ABCDr_fields, 13574 #else 13575 0, 13576 #endif 13577 #endif 13578 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13579 PHYMOD_SYMBOL_FLAG_REGISTER, 13580 "DSC_RX_DFE_TAP12_ABCDr", 13581 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13582 "DSC_AFE3_RX_DFE_TAP12_ABCD", 13583 NULL, 13584 #endif 13585 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13586 0x0, /* 0 */ 13587 0, 13588 #endif 13589 }, 13590 { 13591 BCMI_TSCF_XGXS_DSC_RX_DFE_TAP13_ABCDr, 13592 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13593 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 13594 BCMI_TSCF_XGXS_DSC_RX_DFE_TAP13_ABCDr_fields, 13595 #else 13596 0, 13597 #endif 13598 #endif 13599 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13600 PHYMOD_SYMBOL_FLAG_REGISTER, 13601 "DSC_RX_DFE_TAP13_ABCDr", 13602 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13603 "DSC_AFE3_RX_DFE_TAP13_ABCD", 13604 NULL, 13605 #endif 13606 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13607 0x0, /* 0 */ 13608 0, 13609 #endif 13610 }, 13611 { 13612 BCMI_TSCF_XGXS_DSC_RX_DFE_TAP14_ABCDr, 13613 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13614 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 13615 BCMI_TSCF_XGXS_DSC_RX_DFE_TAP14_ABCDr_fields, 13616 #else 13617 0, 13618 #endif 13619 #endif 13620 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13621 PHYMOD_SYMBOL_FLAG_REGISTER, 13622 "DSC_RX_DFE_TAP14_ABCDr", 13623 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13624 "DSC_AFE3_RX_DFE_TAP14_ABCD", 13625 NULL, 13626 #endif 13627 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13628 0x0, /* 0 */ 13629 0, 13630 #endif 13631 }, 13632 { 13633 BCMI_TSCF_XGXS_DSC_RX_DFE_TAP7_8_MUX_ABCDr, 13634 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13635 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 13636 BCMI_TSCF_XGXS_DSC_RX_DFE_TAP7_8_MUX_ABCDr_fields, 13637 #else 13638 0, 13639 #endif 13640 #endif 13641 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13642 PHYMOD_SYMBOL_FLAG_REGISTER, 13643 "DSC_RX_DFE_TAP7_8_MUX_ABCDr", 13644 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13645 "DSC_AFE3_RX_DFE_TAP7_8_MUX_ABCD", 13646 NULL, 13647 #endif 13648 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13649 0x0, /* 0 */ 13650 0, 13651 #endif 13652 }, 13653 { 13654 BCMI_TSCF_XGXS_DSC_RX_DFE_TAP9_10_MUX_ABCDr, 13655 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13656 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 13657 BCMI_TSCF_XGXS_DSC_RX_DFE_TAP9_10_MUX_ABCDr_fields, 13658 #else 13659 0, 13660 #endif 13661 #endif 13662 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13663 PHYMOD_SYMBOL_FLAG_REGISTER, 13664 "DSC_RX_DFE_TAP9_10_MUX_ABCDr", 13665 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13666 "DSC_AFE3_RX_DFE_TAP9_10_MUX_ABCD", 13667 NULL, 13668 #endif 13669 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13670 0x0, /* 0 */ 13671 0, 13672 #endif 13673 }, 13674 { 13675 BCMI_TSCF_XGXS_DSC_RX_DFE_TAP11_12_MUX_ABCDr, 13676 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13677 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 13678 BCMI_TSCF_XGXS_DSC_RX_DFE_TAP11_12_MUX_ABCDr_fields, 13679 #else 13680 0, 13681 #endif 13682 #endif 13683 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13684 PHYMOD_SYMBOL_FLAG_REGISTER, 13685 "DSC_RX_DFE_TAP11_12_MUX_ABCDr", 13686 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13687 "DSC_AFE3_RX_DFE_TAP11_12_MUX_ABCD", 13688 NULL, 13689 #endif 13690 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13691 0x0, /* 0 */ 13692 0, 13693 #endif 13694 }, 13695 { 13696 BCMI_TSCF_XGXS_DSC_RX_DFE_TAP13_14_MUX_ABCDr, 13697 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13698 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 13699 BCMI_TSCF_XGXS_DSC_RX_DFE_TAP13_14_MUX_ABCDr_fields, 13700 #else 13701 0, 13702 #endif 13703 #endif 13704 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13705 PHYMOD_SYMBOL_FLAG_REGISTER, 13706 "DSC_RX_DFE_TAP13_14_MUX_ABCDr", 13707 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13708 "DSC_AFE3_RX_DFE_TAP13_14_MUX_ABCD", 13709 NULL, 13710 #endif 13711 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13712 0x0, /* 0 */ 13713 0, 13714 #endif 13715 }, 13716 { 13717 BCMI_TSCF_XGXS_DSC_LOAD_PRESETSr, 13718 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13719 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 13720 BCMI_TSCF_XGXS_DSC_LOAD_PRESETSr_fields, 13721 #else 13722 0, 13723 #endif 13724 #endif 13725 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13726 PHYMOD_SYMBOL_FLAG_REGISTER, 13727 "DSC_LOAD_PRESETSr", 13728 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13729 "DSC_AFE3_LOAD_PRESETS", 13730 NULL, 13731 #endif 13732 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13733 0x0, /* 0 */ 13734 0, 13735 #endif 13736 }, 13737 { 13738 BCMI_TSCF_XGXS_DSC_UC_CTLr, 13739 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13740 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 13741 BCMI_TSCF_XGXS_DSC_UC_CTLr_fields, 13742 #else 13743 0, 13744 #endif 13745 #endif 13746 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13747 PHYMOD_SYMBOL_FLAG_REGISTER, 13748 "DSC_UC_CTLr", 13749 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13750 "DSC_A_DSC_UC_CTRL", 13751 NULL, 13752 #endif 13753 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13754 0x0, /* 0 */ 13755 0, 13756 #endif 13757 }, 13758 { 13759 BCMI_TSCF_XGXS_DSC_SCRATCHr, 13760 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13761 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 13762 BCMI_TSCF_XGXS_DSC_SCRATCHr_fields, 13763 #else 13764 0, 13765 #endif 13766 #endif 13767 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13768 PHYMOD_SYMBOL_FLAG_REGISTER, 13769 "DSC_SCRATCHr", 13770 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13771 "DSC_A_DSC_SCRATCH", 13772 NULL, 13773 #endif 13774 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13775 0x0, /* 0 */ 13776 0, 13777 #endif 13778 }, 13779 { 13780 BCMI_TSCF_XGXS_DSC_TRNSUM_A_LOr, 13781 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13782 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 13783 BCMI_TSCF_XGXS_DSC_TRNSUM_A_LOr_fields, 13784 #else 13785 0, 13786 #endif 13787 #endif 13788 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13789 PHYMOD_SYMBOL_FLAG_REGISTER, 13790 "DSC_TRNSUM_A_LOr", 13791 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13792 "DSC_B_TRNSUM_A_LOW", 13793 NULL, 13794 #endif 13795 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13796 0x0, /* 0 */ 13797 0, 13798 #endif 13799 }, 13800 { 13801 BCMI_TSCF_XGXS_DSC_TRNSUM_Ar, 13802 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13803 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 13804 BCMI_TSCF_XGXS_DSC_TRNSUM_Ar_fields, 13805 #else 13806 0, 13807 #endif 13808 #endif 13809 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13810 PHYMOD_SYMBOL_FLAG_REGISTER, 13811 "DSC_TRNSUM_Ar", 13812 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13813 "DSC_B_TRNSUM_A", 13814 NULL, 13815 #endif 13816 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13817 0x0, /* 0 */ 13818 0, 13819 #endif 13820 }, 13821 { 13822 BCMI_TSCF_XGXS_DSC_TRNSUM_B_LOr, 13823 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13824 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 13825 BCMI_TSCF_XGXS_DSC_TRNSUM_B_LOr_fields, 13826 #else 13827 0, 13828 #endif 13829 #endif 13830 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13831 PHYMOD_SYMBOL_FLAG_REGISTER, 13832 "DSC_TRNSUM_B_LOr", 13833 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13834 "DSC_B_TRNSUM_B_LOW", 13835 NULL, 13836 #endif 13837 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13838 0x0, /* 0 */ 13839 0, 13840 #endif 13841 }, 13842 { 13843 BCMI_TSCF_XGXS_DSC_TRNSUM_Br, 13844 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13845 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 13846 BCMI_TSCF_XGXS_DSC_TRNSUM_Br_fields, 13847 #else 13848 0, 13849 #endif 13850 #endif 13851 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13852 PHYMOD_SYMBOL_FLAG_REGISTER, 13853 "DSC_TRNSUM_Br", 13854 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13855 "DSC_B_TRNSUM_B", 13856 NULL, 13857 #endif 13858 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13859 0x0, /* 0 */ 13860 0, 13861 #endif 13862 }, 13863 { 13864 BCMI_TSCF_XGXS_DSC_TRNSUM_C_LOr, 13865 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13866 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 13867 BCMI_TSCF_XGXS_DSC_TRNSUM_C_LOr_fields, 13868 #else 13869 0, 13870 #endif 13871 #endif 13872 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13873 PHYMOD_SYMBOL_FLAG_REGISTER, 13874 "DSC_TRNSUM_C_LOr", 13875 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13876 "DSC_B_TRNSUM_C_LOW", 13877 NULL, 13878 #endif 13879 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13880 0x0, /* 0 */ 13881 0, 13882 #endif 13883 }, 13884 { 13885 BCMI_TSCF_XGXS_DSC_TRNSUM_Cr, 13886 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13887 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 13888 BCMI_TSCF_XGXS_DSC_TRNSUM_Cr_fields, 13889 #else 13890 0, 13891 #endif 13892 #endif 13893 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13894 PHYMOD_SYMBOL_FLAG_REGISTER, 13895 "DSC_TRNSUM_Cr", 13896 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13897 "DSC_B_TRNSUM_C", 13898 NULL, 13899 #endif 13900 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13901 0x0, /* 0 */ 13902 0, 13903 #endif 13904 }, 13905 { 13906 BCMI_TSCF_XGXS_DSC_TRNSUM_D_LOr, 13907 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13908 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 13909 BCMI_TSCF_XGXS_DSC_TRNSUM_D_LOr_fields, 13910 #else 13911 0, 13912 #endif 13913 #endif 13914 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13915 PHYMOD_SYMBOL_FLAG_REGISTER, 13916 "DSC_TRNSUM_D_LOr", 13917 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13918 "DSC_B_TRNSUM_D_LOW", 13919 NULL, 13920 #endif 13921 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13922 0x0, /* 0 */ 13923 0, 13924 #endif 13925 }, 13926 { 13927 BCMI_TSCF_XGXS_DSC_TRNSUM_Dr, 13928 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13929 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 13930 BCMI_TSCF_XGXS_DSC_TRNSUM_Dr_fields, 13931 #else 13932 0, 13933 #endif 13934 #endif 13935 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13936 PHYMOD_SYMBOL_FLAG_REGISTER, 13937 "DSC_TRNSUM_Dr", 13938 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13939 "DSC_B_TRNSUM_D", 13940 NULL, 13941 #endif 13942 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13943 0x0, /* 0 */ 13944 0, 13945 #endif 13946 }, 13947 { 13948 BCMI_TSCF_XGXS_DSC_TRNSUM_LOr, 13949 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13950 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 13951 BCMI_TSCF_XGXS_DSC_TRNSUM_LOr_fields, 13952 #else 13953 0, 13954 #endif 13955 #endif 13956 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13957 PHYMOD_SYMBOL_FLAG_REGISTER, 13958 "DSC_TRNSUM_LOr", 13959 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13960 "DSC_B_TRNSUM_LOW", 13961 NULL, 13962 #endif 13963 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13964 0x0, /* 0 */ 13965 0, 13966 #endif 13967 }, 13968 { 13969 BCMI_TSCF_XGXS_DSC_TRNSUMr, 13970 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13971 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 13972 BCMI_TSCF_XGXS_DSC_TRNSUMr_fields, 13973 #else 13974 0, 13975 #endif 13976 #endif 13977 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13978 PHYMOD_SYMBOL_FLAG_REGISTER, 13979 "DSC_TRNSUMr", 13980 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13981 "DSC_B_TRNSUM", 13982 NULL, 13983 #endif 13984 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13985 0x0, /* 0 */ 13986 0, 13987 #endif 13988 }, 13989 { 13990 BCMI_TSCF_XGXS_DSC_DC_OFFS_STSr, 13991 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13992 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 13993 BCMI_TSCF_XGXS_DSC_DC_OFFS_STSr_fields, 13994 #else 13995 0, 13996 #endif 13997 #endif 13998 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13999 PHYMOD_SYMBOL_FLAG_REGISTER, 14000 "DSC_DC_OFFS_STSr", 14001 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14002 "DSC_B_DC_OFFSET_STATUS", 14003 NULL, 14004 #endif 14005 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14006 0x0, /* 0 */ 14007 0, 14008 #endif 14009 }, 14010 { 14011 BCMI_TSCF_XGXS_DSC_VGA_D_THR_STSr, 14012 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14013 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 14014 BCMI_TSCF_XGXS_DSC_VGA_D_THR_STSr_fields, 14015 #else 14016 0, 14017 #endif 14018 #endif 14019 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14020 PHYMOD_SYMBOL_FLAG_REGISTER, 14021 "DSC_VGA_D_THR_STSr", 14022 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14023 "DSC_B_VGA_D_THRESH_STATUS", 14024 NULL, 14025 #endif 14026 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14027 0x2700, /* 9984 */ 14028 0, 14029 #endif 14030 }, 14031 { 14032 BCMI_TSCF_XGXS_DSC_CDR_CTL0r, 14033 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14034 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 14035 BCMI_TSCF_XGXS_DSC_CDR_CTL0r_fields, 14036 #else 14037 0, 14038 #endif 14039 #endif 14040 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14041 PHYMOD_SYMBOL_FLAG_REGISTER, 14042 "DSC_CDR_CTL0r", 14043 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14044 "DSC_C_CDR_CONTROL_0", 14045 NULL, 14046 #endif 14047 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14048 0x9, /* 9 */ 14049 0, 14050 #endif 14051 }, 14052 { 14053 BCMI_TSCF_XGXS_DSC_CDR_CTL1r, 14054 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14055 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 14056 BCMI_TSCF_XGXS_DSC_CDR_CTL1r_fields, 14057 #else 14058 0, 14059 #endif 14060 #endif 14061 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14062 PHYMOD_SYMBOL_FLAG_REGISTER, 14063 "DSC_CDR_CTL1r", 14064 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14065 "DSC_C_CDR_CONTROL_1", 14066 NULL, 14067 #endif 14068 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14069 0x0, /* 0 */ 14070 0, 14071 #endif 14072 }, 14073 { 14074 BCMI_TSCF_XGXS_DSC_CDR_CTL2r, 14075 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14076 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 14077 BCMI_TSCF_XGXS_DSC_CDR_CTL2r_fields, 14078 #else 14079 0, 14080 #endif 14081 #endif 14082 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14083 PHYMOD_SYMBOL_FLAG_REGISTER, 14084 "DSC_CDR_CTL2r", 14085 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14086 "DSC_C_CDR_CONTROL_2", 14087 NULL, 14088 #endif 14089 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14090 0x80, /* 128 */ 14091 0, 14092 #endif 14093 }, 14094 { 14095 BCMI_TSCF_XGXS_DSC_RX_PI_CTLr, 14096 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14097 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 14098 BCMI_TSCF_XGXS_DSC_RX_PI_CTLr_fields, 14099 #else 14100 0, 14101 #endif 14102 #endif 14103 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14104 PHYMOD_SYMBOL_FLAG_REGISTER, 14105 "DSC_RX_PI_CTLr", 14106 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14107 "DSC_C_RX_PI_CONTROL", 14108 NULL, 14109 #endif 14110 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14111 0x0, /* 0 */ 14112 0, 14113 #endif 14114 }, 14115 { 14116 BCMI_TSCF_XGXS_DSC_TRNSUM_CTLr, 14117 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14118 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 14119 BCMI_TSCF_XGXS_DSC_TRNSUM_CTLr_fields, 14120 #else 14121 0, 14122 #endif 14123 #endif 14124 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14125 PHYMOD_SYMBOL_FLAG_REGISTER, 14126 "DSC_TRNSUM_CTLr", 14127 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14128 "DSC_C_TRNSUM_CONTROL", 14129 NULL, 14130 #endif 14131 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14132 0x0, /* 0 */ 14133 0, 14134 #endif 14135 }, 14136 { 14137 BCMI_TSCF_XGXS_DSC_TRNSUM_PAT_CTL1r, 14138 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14139 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 14140 BCMI_TSCF_XGXS_DSC_TRNSUM_PAT_CTL1r_fields, 14141 #else 14142 0, 14143 #endif 14144 #endif 14145 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14146 PHYMOD_SYMBOL_FLAG_REGISTER, 14147 "DSC_TRNSUM_PAT_CTL1r", 14148 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14149 "DSC_C_TRNSUM_PAT_CTRL_1", 14150 NULL, 14151 #endif 14152 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14153 0x0, /* 0 */ 14154 0, 14155 #endif 14156 }, 14157 { 14158 BCMI_TSCF_XGXS_DSC_TRNSUM_PAT_CTL2r, 14159 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14160 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 14161 BCMI_TSCF_XGXS_DSC_TRNSUM_PAT_CTL2r_fields, 14162 #else 14163 0, 14164 #endif 14165 #endif 14166 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14167 PHYMOD_SYMBOL_FLAG_REGISTER, 14168 "DSC_TRNSUM_PAT_CTL2r", 14169 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14170 "DSC_C_TRNSUM_PAT_CTRL_2", 14171 NULL, 14172 #endif 14173 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14174 0x0, /* 0 */ 14175 0, 14176 #endif 14177 }, 14178 { 14179 BCMI_TSCF_XGXS_DSC_TRNSUM_TAP_CTLr, 14180 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14181 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 14182 BCMI_TSCF_XGXS_DSC_TRNSUM_TAP_CTLr_fields, 14183 #else 14184 0, 14185 #endif 14186 #endif 14187 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14188 PHYMOD_SYMBOL_FLAG_REGISTER, 14189 "DSC_TRNSUM_TAP_CTLr", 14190 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14191 "DSC_C_TRNSUM_TAP_CTRL", 14192 NULL, 14193 #endif 14194 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14195 0x0, /* 0 */ 14196 0, 14197 #endif 14198 }, 14199 { 14200 BCMI_TSCF_XGXS_DSC_TRNSUM_TDT_CTLr, 14201 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14202 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 14203 BCMI_TSCF_XGXS_DSC_TRNSUM_TDT_CTLr_fields, 14204 #else 14205 0, 14206 #endif 14207 #endif 14208 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14209 PHYMOD_SYMBOL_FLAG_REGISTER, 14210 "DSC_TRNSUM_TDT_CTLr", 14211 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14212 "DSC_C_TRNSUM_TDT_CTL", 14213 NULL, 14214 #endif 14215 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14216 0x0, /* 0 */ 14217 0, 14218 #endif 14219 }, 14220 { 14221 BCMI_TSCF_XGXS_DSC_TRNSUM_MISCr, 14222 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14223 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 14224 BCMI_TSCF_XGXS_DSC_TRNSUM_MISCr_fields, 14225 #else 14226 0, 14227 #endif 14228 #endif 14229 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14230 PHYMOD_SYMBOL_FLAG_REGISTER, 14231 "DSC_TRNSUM_MISCr", 14232 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14233 "DSC_C_TRNSUM_MISC", 14234 NULL, 14235 #endif 14236 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14237 0x0, /* 0 */ 14238 0, 14239 #endif 14240 }, 14241 { 14242 BCMI_TSCF_XGXS_DSC_VGA_CTL1r, 14243 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14244 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 14245 BCMI_TSCF_XGXS_DSC_VGA_CTL1r_fields, 14246 #else 14247 0, 14248 #endif 14249 #endif 14250 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14251 PHYMOD_SYMBOL_FLAG_REGISTER, 14252 "DSC_VGA_CTL1r", 14253 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14254 "DSC_C_VGA_CTRL_1", 14255 NULL, 14256 #endif 14257 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14258 0x0, /* 0 */ 14259 0, 14260 #endif 14261 }, 14262 { 14263 BCMI_TSCF_XGXS_DSC_DATA_SLCR_THR_CTLr, 14264 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14265 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 14266 BCMI_TSCF_XGXS_DSC_DATA_SLCR_THR_CTLr_fields, 14267 #else 14268 0, 14269 #endif 14270 #endif 14271 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14272 PHYMOD_SYMBOL_FLAG_REGISTER, 14273 "DSC_DATA_SLCR_THR_CTLr", 14274 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14275 "DSC_C_DATA_SLICER_THRESH_CTRL", 14276 NULL, 14277 #endif 14278 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14279 0x0, /* 0 */ 14280 0, 14281 #endif 14282 }, 14283 { 14284 BCMI_TSCF_XGXS_DSC_DC_OFFS_CTLr, 14285 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14286 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 14287 BCMI_TSCF_XGXS_DSC_DC_OFFS_CTLr_fields, 14288 #else 14289 0, 14290 #endif 14291 #endif 14292 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14293 PHYMOD_SYMBOL_FLAG_REGISTER, 14294 "DSC_DC_OFFS_CTLr", 14295 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14296 "DSC_C_DC_OFFSET_CONTROL", 14297 NULL, 14298 #endif 14299 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14300 0x0, /* 0 */ 14301 0, 14302 #endif 14303 }, 14304 { 14305 BCMI_TSCF_XGXS_DSC_SM_CTL0r, 14306 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14307 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 14308 BCMI_TSCF_XGXS_DSC_SM_CTL0r_fields, 14309 #else 14310 0, 14311 #endif 14312 #endif 14313 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14314 PHYMOD_SYMBOL_FLAG_REGISTER, 14315 "DSC_SM_CTL0r", 14316 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14317 "DSC_D_DSC_SM_CTRL_0", 14318 NULL, 14319 #endif 14320 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14321 0x8, /* 8 */ 14322 0, 14323 #endif 14324 }, 14325 { 14326 BCMI_TSCF_XGXS_DSC_SM_CTL1r, 14327 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14328 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 14329 BCMI_TSCF_XGXS_DSC_SM_CTL1r_fields, 14330 #else 14331 0, 14332 #endif 14333 #endif 14334 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14335 PHYMOD_SYMBOL_FLAG_REGISTER, 14336 "DSC_SM_CTL1r", 14337 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14338 "DSC_D_DSC_SM_CTRL_1", 14339 NULL, 14340 #endif 14341 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14342 0x200, /* 512 */ 14343 0, 14344 #endif 14345 }, 14346 { 14347 BCMI_TSCF_XGXS_DSC_SM_CTL2r, 14348 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14349 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 14350 BCMI_TSCF_XGXS_DSC_SM_CTL2r_fields, 14351 #else 14352 0, 14353 #endif 14354 #endif 14355 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14356 PHYMOD_SYMBOL_FLAG_REGISTER, 14357 "DSC_SM_CTL2r", 14358 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14359 "DSC_D_DSC_SM_CTRL_2", 14360 NULL, 14361 #endif 14362 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14363 0x87, /* 135 */ 14364 0, 14365 #endif 14366 }, 14367 { 14368 BCMI_TSCF_XGXS_DSC_SM_CTL3r, 14369 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14370 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 14371 BCMI_TSCF_XGXS_DSC_SM_CTL3r_fields, 14372 #else 14373 0, 14374 #endif 14375 #endif 14376 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14377 PHYMOD_SYMBOL_FLAG_REGISTER, 14378 "DSC_SM_CTL3r", 14379 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14380 "DSC_D_DSC_SM_CTRL_3", 14381 NULL, 14382 #endif 14383 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14384 0x1c1e, /* 7198 */ 14385 0, 14386 #endif 14387 }, 14388 { 14389 BCMI_TSCF_XGXS_DSC_SM_CTL4r, 14390 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14391 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 14392 BCMI_TSCF_XGXS_DSC_SM_CTL4r_fields, 14393 #else 14394 0, 14395 #endif 14396 #endif 14397 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14398 PHYMOD_SYMBOL_FLAG_REGISTER, 14399 "DSC_SM_CTL4r", 14400 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14401 "DSC_D_DSC_SM_CTRL_4", 14402 NULL, 14403 #endif 14404 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14405 0x0, /* 0 */ 14406 0, 14407 #endif 14408 }, 14409 { 14410 BCMI_TSCF_XGXS_DSC_SM_CTL5r, 14411 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14412 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 14413 BCMI_TSCF_XGXS_DSC_SM_CTL5r_fields, 14414 #else 14415 0, 14416 #endif 14417 #endif 14418 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14419 PHYMOD_SYMBOL_FLAG_REGISTER, 14420 "DSC_SM_CTL5r", 14421 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14422 "DSC_D_DSC_SM_CTRL_5", 14423 NULL, 14424 #endif 14425 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14426 0x35ad, /* 13741 */ 14427 0, 14428 #endif 14429 }, 14430 { 14431 BCMI_TSCF_XGXS_DSC_SM_CTL6r, 14432 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14433 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 14434 BCMI_TSCF_XGXS_DSC_SM_CTL6r_fields, 14435 #else 14436 0, 14437 #endif 14438 #endif 14439 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14440 PHYMOD_SYMBOL_FLAG_REGISTER, 14441 "DSC_SM_CTL6r", 14442 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14443 "DSC_D_DSC_SM_CTRL_6", 14444 NULL, 14445 #endif 14446 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14447 0x340d, /* 13325 */ 14448 0, 14449 #endif 14450 }, 14451 { 14452 BCMI_TSCF_XGXS_DSC_SM_CTL7r, 14453 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14454 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 14455 BCMI_TSCF_XGXS_DSC_SM_CTL7r_fields, 14456 #else 14457 0, 14458 #endif 14459 #endif 14460 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14461 PHYMOD_SYMBOL_FLAG_REGISTER, 14462 "DSC_SM_CTL7r", 14463 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14464 "DSC_D_DSC_SM_CTRL_7", 14465 NULL, 14466 #endif 14467 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14468 0x0, /* 0 */ 14469 0, 14470 #endif 14471 }, 14472 { 14473 BCMI_TSCF_XGXS_DSC_SM_CTL8r, 14474 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14475 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 14476 BCMI_TSCF_XGXS_DSC_SM_CTL8r_fields, 14477 #else 14478 0, 14479 #endif 14480 #endif 14481 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14482 PHYMOD_SYMBOL_FLAG_REGISTER, 14483 "DSC_SM_CTL8r", 14484 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14485 "DSC_D_DSC_SM_CTRL_8", 14486 NULL, 14487 #endif 14488 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14489 0x11, /* 17 */ 14490 0, 14491 #endif 14492 }, 14493 { 14494 BCMI_TSCF_XGXS_DSC_SM_CTL9r, 14495 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14496 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 14497 BCMI_TSCF_XGXS_DSC_SM_CTL9r_fields, 14498 #else 14499 0, 14500 #endif 14501 #endif 14502 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14503 PHYMOD_SYMBOL_FLAG_REGISTER, 14504 "DSC_SM_CTL9r", 14505 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14506 "DSC_D_DSC_SM_CTRL_9", 14507 NULL, 14508 #endif 14509 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14510 0x0, /* 0 */ 14511 0, 14512 #endif 14513 }, 14514 { 14515 BCMI_TSCF_XGXS_DSC_SM_STS_DSC_LOCKr, 14516 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14517 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 14518 BCMI_TSCF_XGXS_DSC_SM_STS_DSC_LOCKr_fields, 14519 #else 14520 0, 14521 #endif 14522 #endif 14523 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14524 PHYMOD_SYMBOL_FLAG_REGISTER, 14525 "DSC_SM_STS_DSC_LOCKr", 14526 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14527 "DSC_D_DSC_SM_STATUS_DSC_LOCK", 14528 NULL, 14529 #endif 14530 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14531 0x0, /* 0 */ 14532 0, 14533 #endif 14534 }, 14535 { 14536 BCMI_TSCF_XGXS_DSC_SM_STS_DSC_ST_ONE_HOTr, 14537 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14538 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 14539 BCMI_TSCF_XGXS_DSC_SM_STS_DSC_ST_ONE_HOTr_fields, 14540 #else 14541 0, 14542 #endif 14543 #endif 14544 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14545 PHYMOD_SYMBOL_FLAG_REGISTER, 14546 "DSC_SM_STS_DSC_ST_ONE_HOTr", 14547 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14548 "DSC_D_DSC_SM_STATUS_DSC_STATE_ONE_HOT", 14549 NULL, 14550 #endif 14551 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14552 0x0, /* 0 */ 14553 0, 14554 #endif 14555 }, 14556 { 14557 BCMI_TSCF_XGXS_DSC_SM_STS_DSC_ST_EEE_ONE_HOTr, 14558 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14559 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 14560 BCMI_TSCF_XGXS_DSC_SM_STS_DSC_ST_EEE_ONE_HOTr_fields, 14561 #else 14562 0, 14563 #endif 14564 #endif 14565 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14566 PHYMOD_SYMBOL_FLAG_REGISTER, 14567 "DSC_SM_STS_DSC_ST_EEE_ONE_HOTr", 14568 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14569 "DSC_D_DSC_SM_STATUS_DSC_STATE_EEE_ONE_HOT", 14570 NULL, 14571 #endif 14572 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14573 0x0, /* 0 */ 14574 0, 14575 #endif 14576 }, 14577 { 14578 BCMI_TSCF_XGXS_DSC_SM_STS_RESTARTr, 14579 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14580 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 14581 BCMI_TSCF_XGXS_DSC_SM_STS_RESTARTr_fields, 14582 #else 14583 0, 14584 #endif 14585 #endif 14586 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14587 PHYMOD_SYMBOL_FLAG_REGISTER, 14588 "DSC_SM_STS_RESTARTr", 14589 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14590 "DSC_D_DSC_SM_STATUS_RESTART", 14591 NULL, 14592 #endif 14593 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14594 0x0, /* 0 */ 14595 0, 14596 #endif 14597 }, 14598 { 14599 BCMI_TSCF_XGXS_DSC_SM_STS_DSC_STr, 14600 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14601 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 14602 BCMI_TSCF_XGXS_DSC_SM_STS_DSC_STr_fields, 14603 #else 14604 0, 14605 #endif 14606 #endif 14607 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14608 PHYMOD_SYMBOL_FLAG_REGISTER, 14609 "DSC_SM_STS_DSC_STr", 14610 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14611 "DSC_D_DSC_SM_STATUS_DSC_STATE", 14612 NULL, 14613 #endif 14614 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14615 0x0, /* 0 */ 14616 0, 14617 #endif 14618 }, 14619 { 14620 BCMI_TSCF_XGXS_DSC_RX_PI_CNT_BIN_PDr, 14621 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14622 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 14623 BCMI_TSCF_XGXS_DSC_RX_PI_CNT_BIN_PDr_fields, 14624 #else 14625 0, 14626 #endif 14627 #endif 14628 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14629 PHYMOD_SYMBOL_FLAG_REGISTER, 14630 "DSC_RX_PI_CNT_BIN_PDr", 14631 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14632 "DSC_E_RX_PI_CNT_BIN_PD", 14633 NULL, 14634 #endif 14635 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14636 0x0, /* 0 */ 14637 0, 14638 #endif 14639 }, 14640 { 14641 BCMI_TSCF_XGXS_DSC_RX_PI_CNT_BIN_LDr, 14642 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14643 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 14644 BCMI_TSCF_XGXS_DSC_RX_PI_CNT_BIN_LDr_fields, 14645 #else 14646 0, 14647 #endif 14648 #endif 14649 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14650 PHYMOD_SYMBOL_FLAG_REGISTER, 14651 "DSC_RX_PI_CNT_BIN_LDr", 14652 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14653 "DSC_E_RX_PI_CNT_BIN_LD", 14654 NULL, 14655 #endif 14656 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14657 0x0, /* 0 */ 14658 0, 14659 #endif 14660 }, 14661 { 14662 BCMI_TSCF_XGXS_DSC_RX_DATA_15_TO0r, 14663 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14664 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 14665 BCMI_TSCF_XGXS_DSC_RX_DATA_15_TO0r_fields, 14666 #else 14667 0, 14668 #endif 14669 #endif 14670 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14671 PHYMOD_SYMBOL_FLAG_REGISTER, 14672 "DSC_RX_DATA_15_TO0r", 14673 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14674 "DSC_E_RX_DATA_15_TO_0", 14675 NULL, 14676 #endif 14677 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14678 0x0, /* 0 */ 14679 0, 14680 #endif 14681 }, 14682 { 14683 BCMI_TSCF_XGXS_DSC_RX_DATA_35_TO_20r, 14684 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14685 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 14686 BCMI_TSCF_XGXS_DSC_RX_DATA_35_TO_20r_fields, 14687 #else 14688 0, 14689 #endif 14690 #endif 14691 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14692 PHYMOD_SYMBOL_FLAG_REGISTER, 14693 "DSC_RX_DATA_35_TO_20r", 14694 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14695 "DSC_E_RX_DATA_35_TO_20", 14696 NULL, 14697 #endif 14698 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14699 0x0, /* 0 */ 14700 0, 14701 #endif 14702 }, 14703 { 14704 BCMI_TSCF_XGXS_DSC_CDR_STS_PHASE_ERRr, 14705 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14706 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 14707 BCMI_TSCF_XGXS_DSC_CDR_STS_PHASE_ERRr_fields, 14708 #else 14709 0, 14710 #endif 14711 #endif 14712 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14713 PHYMOD_SYMBOL_FLAG_REGISTER, 14714 "DSC_CDR_STS_PHASE_ERRr", 14715 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14716 "DSC_E_CDR_STATUS_PHASE_ERROR", 14717 NULL, 14718 #endif 14719 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14720 0x0, /* 0 */ 14721 0, 14722 #endif 14723 }, 14724 { 14725 BCMI_TSCF_XGXS_DSC_RX_PI_CNT_BIN_Dr, 14726 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14727 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 14728 BCMI_TSCF_XGXS_DSC_RX_PI_CNT_BIN_Dr_fields, 14729 #else 14730 0, 14731 #endif 14732 #endif 14733 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14734 PHYMOD_SYMBOL_FLAG_REGISTER, 14735 "DSC_RX_PI_CNT_BIN_Dr", 14736 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14737 "DSC_E_RX_PI_CNT_BIN_D", 14738 NULL, 14739 #endif 14740 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14741 0x0, /* 0 */ 14742 0, 14743 #endif 14744 }, 14745 { 14746 BCMI_TSCF_XGXS_DSC_RX_PI_CNT_BIN_Pr, 14747 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14748 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 14749 BCMI_TSCF_XGXS_DSC_RX_PI_CNT_BIN_Pr_fields, 14750 #else 14751 0, 14752 #endif 14753 #endif 14754 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14755 PHYMOD_SYMBOL_FLAG_REGISTER, 14756 "DSC_RX_PI_CNT_BIN_Pr", 14757 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14758 "DSC_E_RX_PI_CNT_BIN_P", 14759 NULL, 14760 #endif 14761 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14762 0x0, /* 0 */ 14763 0, 14764 #endif 14765 }, 14766 { 14767 BCMI_TSCF_XGXS_DSC_RX_PI_CNT_BIN_Lr, 14768 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14769 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 14770 BCMI_TSCF_XGXS_DSC_RX_PI_CNT_BIN_Lr_fields, 14771 #else 14772 0, 14773 #endif 14774 #endif 14775 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14776 PHYMOD_SYMBOL_FLAG_REGISTER, 14777 "DSC_RX_PI_CNT_BIN_Lr", 14778 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14779 "DSC_E_RX_PI_CNT_BIN_L", 14780 NULL, 14781 #endif 14782 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14783 0x0, /* 0 */ 14784 0, 14785 #endif 14786 }, 14787 { 14788 BCMI_TSCF_XGXS_DSC_CDR_STS_INTEGr, 14789 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14790 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 14791 BCMI_TSCF_XGXS_DSC_CDR_STS_INTEGr_fields, 14792 #else 14793 0, 14794 #endif 14795 #endif 14796 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14797 PHYMOD_SYMBOL_FLAG_REGISTER, 14798 "DSC_CDR_STS_INTEGr", 14799 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14800 "DSC_E_CDR_STATUS_INTEG_REG", 14801 NULL, 14802 #endif 14803 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14804 0x0, /* 0 */ 14805 0, 14806 #endif 14807 }, 14808 { 14809 BCMI_TSCF_XGXS_DSC_CDR_STS_MISCr, 14810 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14811 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 14812 BCMI_TSCF_XGXS_DSC_CDR_STS_MISCr_fields, 14813 #else 14814 0, 14815 #endif 14816 #endif 14817 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14818 PHYMOD_SYMBOL_FLAG_REGISTER, 14819 "DSC_CDR_STS_MISCr", 14820 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14821 "DSC_E_CDR_STATUS_MISC", 14822 NULL, 14823 #endif 14824 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14825 0x1, /* 1 */ 14826 0, 14827 #endif 14828 }, 14829 { 14830 BCMI_TSCF_XGXS_DSC_CDR_1G_STSr, 14831 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14832 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 14833 BCMI_TSCF_XGXS_DSC_CDR_1G_STSr_fields, 14834 #else 14835 0, 14836 #endif 14837 #endif 14838 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14839 PHYMOD_SYMBOL_FLAG_REGISTER, 14840 "DSC_CDR_1G_STSr", 14841 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14842 "DSC_E_CDR_1G_STATUS", 14843 NULL, 14844 #endif 14845 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14846 0x0, /* 0 */ 14847 0, 14848 #endif 14849 }, 14850 { 14851 BCMI_TSCF_XGXS_DSC_PRESETr, 14852 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14853 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 14854 BCMI_TSCF_XGXS_DSC_PRESETr_fields, 14855 #else 14856 0, 14857 #endif 14858 #endif 14859 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14860 PHYMOD_SYMBOL_FLAG_REGISTER, 14861 "DSC_PRESETr", 14862 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14863 "DSC_E_PRESET_REG", 14864 NULL, 14865 #endif 14866 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14867 0x0, /* 0 */ 14868 0, 14869 #endif 14870 }, 14871 { 14872 BCMI_TSCF_XGXS_CL93N72_UR_CTL0r, 14873 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14874 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 14875 BCMI_TSCF_XGXS_CL93N72_UR_CTL0r_fields, 14876 #else 14877 0, 14878 #endif 14879 #endif 14880 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14881 PHYMOD_SYMBOL_FLAG_REGISTER, 14882 "CL93N72_UR_CTL0r", 14883 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14884 "CL93N72_USER_RX_CL93N72UR_CONTROL0_REGISTER", 14885 NULL, 14886 #endif 14887 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14888 0x4, /* 4 */ 14889 0, 14890 #endif 14891 }, 14892 { 14893 BCMI_TSCF_XGXS_CL93N72_UR_CTL1r, 14894 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14895 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 14896 BCMI_TSCF_XGXS_CL93N72_UR_CTL1r_fields, 14897 #else 14898 0, 14899 #endif 14900 #endif 14901 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14902 PHYMOD_SYMBOL_FLAG_REGISTER, 14903 "CL93N72_UR_CTL1r", 14904 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14905 "CL93N72_USER_RX_CL93N72UR_CONTROL1_REGISTER", 14906 NULL, 14907 #endif 14908 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14909 0x52, /* 82 */ 14910 0, 14911 #endif 14912 }, 14913 { 14914 BCMI_TSCF_XGXS_CL93N72_UR_CTL2r, 14915 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14916 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 14917 BCMI_TSCF_XGXS_CL93N72_UR_CTL2r_fields, 14918 #else 14919 0, 14920 #endif 14921 #endif 14922 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14923 PHYMOD_SYMBOL_FLAG_REGISTER, 14924 "CL93N72_UR_CTL2r", 14925 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14926 "CL93N72_USER_RX_CL93N72UR_CONTROL2_REGISTER", 14927 NULL, 14928 #endif 14929 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14930 0x310, /* 784 */ 14931 0, 14932 #endif 14933 }, 14934 { 14935 BCMI_TSCF_XGXS_CL93N72_UR_STS0r, 14936 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14937 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 14938 BCMI_TSCF_XGXS_CL93N72_UR_STS0r_fields, 14939 #else 14940 0, 14941 #endif 14942 #endif 14943 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14944 PHYMOD_SYMBOL_FLAG_REGISTER, 14945 "CL93N72_UR_STS0r", 14946 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14947 "CL93N72_USER_RX_CL93N72UR_STATUS0_REGISTER", 14948 NULL, 14949 #endif 14950 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14951 0x0, /* 0 */ 14952 0, 14953 #endif 14954 }, 14955 { 14956 BCMI_TSCF_XGXS_CL93N72_UR_UC_INTR_CTL0r, 14957 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14958 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 14959 BCMI_TSCF_XGXS_CL93N72_UR_UC_INTR_CTL0r_fields, 14960 #else 14961 0, 14962 #endif 14963 #endif 14964 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14965 PHYMOD_SYMBOL_FLAG_REGISTER, 14966 "CL93N72_UR_UC_INTR_CTL0r", 14967 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14968 "CL93N72_USER_RX_CL93N72UR_MICRO_INTERRUPT_CONTROL0_REGISTER", 14969 NULL, 14970 #endif 14971 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14972 0x0, /* 0 */ 14973 0, 14974 #endif 14975 }, 14976 { 14977 BCMI_TSCF_XGXS_CL93N72_UR_UC_STS0r, 14978 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14979 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 14980 BCMI_TSCF_XGXS_CL93N72_UR_UC_STS0r_fields, 14981 #else 14982 0, 14983 #endif 14984 #endif 14985 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14986 PHYMOD_SYMBOL_FLAG_REGISTER, 14987 "CL93N72_UR_UC_STS0r", 14988 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14989 "CL93N72_USER_RX_CL93N72UR_MICRO_STATUS0_REGISTER", 14990 NULL, 14991 #endif 14992 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14993 0x0, /* 0 */ 14994 0, 14995 #endif 14996 }, 14997 { 14998 BCMI_TSCF_XGXS_CL93N72_UR_UC_STS1r, 14999 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15000 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 15001 BCMI_TSCF_XGXS_CL93N72_UR_UC_STS1r_fields, 15002 #else 15003 0, 15004 #endif 15005 #endif 15006 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15007 PHYMOD_SYMBOL_FLAG_REGISTER, 15008 "CL93N72_UR_UC_STS1r", 15009 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15010 "CL93N72_USER_RX_CL93N72UR_MICRO_STATUS1_REGISTER", 15011 NULL, 15012 #endif 15013 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15014 0x0, /* 0 */ 15015 0, 15016 #endif 15017 }, 15018 { 15019 BCMI_TSCF_XGXS_CL93N72_UT_XMT_UPD_PAGEr, 15020 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15021 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 15022 BCMI_TSCF_XGXS_CL93N72_UT_XMT_UPD_PAGEr_fields, 15023 #else 15024 0, 15025 #endif 15026 #endif 15027 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15028 PHYMOD_SYMBOL_FLAG_REGISTER, 15029 "CL93N72_UT_XMT_UPD_PAGEr", 15030 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15031 "CL93N72_USER_TX_CL93N72UT_XMT_UPDATE_PAGE_REGISTER", 15032 NULL, 15033 #endif 15034 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15035 0x0, /* 0 */ 15036 0, 15037 #endif 15038 }, 15039 { 15040 BCMI_TSCF_XGXS_CL93N72_UT_LD_XMT_STS_PAGEr, 15041 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15042 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 15043 BCMI_TSCF_XGXS_CL93N72_UT_LD_XMT_STS_PAGEr_fields, 15044 #else 15045 0, 15046 #endif 15047 #endif 15048 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15049 PHYMOD_SYMBOL_FLAG_REGISTER, 15050 "CL93N72_UT_LD_XMT_STS_PAGEr", 15051 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15052 "CL93N72_USER_TX_CL93N72UT_LD_XMT_STATUS_PAGE", 15053 NULL, 15054 #endif 15055 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15056 0x0, /* 0 */ 15057 0, 15058 #endif 15059 }, 15060 { 15061 BCMI_TSCF_XGXS_CL93N72_UT_CTL0r, 15062 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15063 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 15064 BCMI_TSCF_XGXS_CL93N72_UT_CTL0r_fields, 15065 #else 15066 0, 15067 #endif 15068 #endif 15069 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15070 PHYMOD_SYMBOL_FLAG_REGISTER, 15071 "CL93N72_UT_CTL0r", 15072 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15073 "CL93N72_USER_TX_CL93N72UT_CONTROL0_REGISTER", 15074 NULL, 15075 #endif 15076 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15077 0x0, /* 0 */ 15078 0, 15079 #endif 15080 }, 15081 { 15082 BCMI_TSCF_XGXS_CL93N72_UT_CTL1r, 15083 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15084 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 15085 BCMI_TSCF_XGXS_CL93N72_UT_CTL1r_fields, 15086 #else 15087 0, 15088 #endif 15089 #endif 15090 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15091 PHYMOD_SYMBOL_FLAG_REGISTER, 15092 "CL93N72_UT_CTL1r", 15093 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15094 "CL93N72_USER_TX_CL93N72UT_CONTROL1_REGISTER", 15095 NULL, 15096 #endif 15097 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15098 0x4, /* 4 */ 15099 0, 15100 #endif 15101 }, 15102 { 15103 BCMI_TSCF_XGXS_CL93N72_UT_CTL2r, 15104 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15105 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 15106 BCMI_TSCF_XGXS_CL93N72_UT_CTL2r_fields, 15107 #else 15108 0, 15109 #endif 15110 #endif 15111 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15112 PHYMOD_SYMBOL_FLAG_REGISTER, 15113 "CL93N72_UT_CTL2r", 15114 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15115 "CL93N72_USER_TX_CL93N72UT_CONTROL2_REGISTER", 15116 NULL, 15117 #endif 15118 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15119 0x2c08, /* 11272 */ 15120 0, 15121 #endif 15122 }, 15123 { 15124 BCMI_TSCF_XGXS_CL93N72_UT_CTL3r, 15125 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15126 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 15127 BCMI_TSCF_XGXS_CL93N72_UT_CTL3r_fields, 15128 #else 15129 0, 15130 #endif 15131 #endif 15132 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15133 PHYMOD_SYMBOL_FLAG_REGISTER, 15134 "CL93N72_UT_CTL3r", 15135 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15136 "CL93N72_USER_TX_CL93N72UT_CONTROL3_REGISTER", 15137 NULL, 15138 #endif 15139 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15140 0x3c, /* 60 */ 15141 0, 15142 #endif 15143 }, 15144 { 15145 BCMI_TSCF_XGXS_CL93N72_UT_STS0r, 15146 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15147 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 15148 BCMI_TSCF_XGXS_CL93N72_UT_STS0r_fields, 15149 #else 15150 0, 15151 #endif 15152 #endif 15153 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15154 PHYMOD_SYMBOL_FLAG_REGISTER, 15155 "CL93N72_UT_STS0r", 15156 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15157 "CL93N72_USER_TX_CL93N72UT_STATUS0_REGISTER", 15158 NULL, 15159 #endif 15160 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15161 0x0, /* 0 */ 15162 0, 15163 #endif 15164 }, 15165 { 15166 BCMI_TSCF_XGXS_TX_PI_PMD_CTL0r, 15167 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15168 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 15169 BCMI_TSCF_XGXS_TX_PI_PMD_CTL0r_fields, 15170 #else 15171 0, 15172 #endif 15173 #endif 15174 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15175 PHYMOD_SYMBOL_FLAG_REGISTER, 15176 "TX_PI_PMD_CTL0r", 15177 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15178 "TX_PI_PMD_COM_CONTROL_0", 15179 NULL, 15180 #endif 15181 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15182 0x7000, /* 28672 */ 15183 0, 15184 #endif 15185 }, 15186 { 15187 BCMI_TSCF_XGXS_TX_PI_PMD_CTL1r, 15188 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15189 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 15190 BCMI_TSCF_XGXS_TX_PI_PMD_CTL1r_fields, 15191 #else 15192 0, 15193 #endif 15194 #endif 15195 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15196 PHYMOD_SYMBOL_FLAG_REGISTER, 15197 "TX_PI_PMD_CTL1r", 15198 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15199 "TX_PI_PMD_COM_CONTROL_1", 15200 NULL, 15201 #endif 15202 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15203 0x0, /* 0 */ 15204 0, 15205 #endif 15206 }, 15207 { 15208 BCMI_TSCF_XGXS_TX_PI_PMD_CTL2r, 15209 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15210 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 15211 BCMI_TSCF_XGXS_TX_PI_PMD_CTL2r_fields, 15212 #else 15213 0, 15214 #endif 15215 #endif 15216 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15217 PHYMOD_SYMBOL_FLAG_REGISTER, 15218 "TX_PI_PMD_CTL2r", 15219 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15220 "TX_PI_PMD_COM_CONTROL_2", 15221 NULL, 15222 #endif 15223 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15224 0x0, /* 0 */ 15225 0, 15226 #endif 15227 }, 15228 { 15229 BCMI_TSCF_XGXS_TX_PI_PMD_CTL3r, 15230 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15231 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 15232 BCMI_TSCF_XGXS_TX_PI_PMD_CTL3r_fields, 15233 #else 15234 0, 15235 #endif 15236 #endif 15237 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15238 PHYMOD_SYMBOL_FLAG_REGISTER, 15239 "TX_PI_PMD_CTL3r", 15240 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15241 "TX_PI_PMD_COM_CONTROL_3", 15242 NULL, 15243 #endif 15244 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15245 0x100, /* 256 */ 15246 0, 15247 #endif 15248 }, 15249 { 15250 BCMI_TSCF_XGXS_TX_PI_PMD_CTL4r, 15251 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15252 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 15253 BCMI_TSCF_XGXS_TX_PI_PMD_CTL4r_fields, 15254 #else 15255 0, 15256 #endif 15257 #endif 15258 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15259 PHYMOD_SYMBOL_FLAG_REGISTER, 15260 "TX_PI_PMD_CTL4r", 15261 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15262 "TX_PI_PMD_COM_CONTROL_4", 15263 NULL, 15264 #endif 15265 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15266 0x4, /* 4 */ 15267 0, 15268 #endif 15269 }, 15270 { 15271 BCMI_TSCF_XGXS_TX_PI_PMD_STS0r, 15272 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15273 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 15274 BCMI_TSCF_XGXS_TX_PI_PMD_STS0r_fields, 15275 #else 15276 0, 15277 #endif 15278 #endif 15279 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15280 PHYMOD_SYMBOL_FLAG_REGISTER, 15281 "TX_PI_PMD_STS0r", 15282 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15283 "TX_PI_PMD_COM_STATUS_0", 15284 NULL, 15285 #endif 15286 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15287 0x0, /* 0 */ 15288 0, 15289 #endif 15290 }, 15291 { 15292 BCMI_TSCF_XGXS_TX_PI_PMD_STS1r, 15293 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15294 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 15295 BCMI_TSCF_XGXS_TX_PI_PMD_STS1r_fields, 15296 #else 15297 0, 15298 #endif 15299 #endif 15300 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15301 PHYMOD_SYMBOL_FLAG_REGISTER, 15302 "TX_PI_PMD_STS1r", 15303 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15304 "TX_PI_PMD_COM_STATUS_1", 15305 NULL, 15306 #endif 15307 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15308 0x0, /* 0 */ 15309 0, 15310 #endif 15311 }, 15312 { 15313 BCMI_TSCF_XGXS_TX_PI_PMD_STS2r, 15314 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15315 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 15316 BCMI_TSCF_XGXS_TX_PI_PMD_STS2r_fields, 15317 #else 15318 0, 15319 #endif 15320 #endif 15321 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15322 PHYMOD_SYMBOL_FLAG_REGISTER, 15323 "TX_PI_PMD_STS2r", 15324 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15325 "TX_PI_PMD_COM_STATUS_2", 15326 NULL, 15327 #endif 15328 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15329 0x0, /* 0 */ 15330 0, 15331 #endif 15332 }, 15333 { 15334 BCMI_TSCF_XGXS_TX_PI_PMD_STS3r, 15335 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15336 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 15337 BCMI_TSCF_XGXS_TX_PI_PMD_STS3r_fields, 15338 #else 15339 0, 15340 #endif 15341 #endif 15342 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15343 PHYMOD_SYMBOL_FLAG_REGISTER, 15344 "TX_PI_PMD_STS3r", 15345 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15346 "TX_PI_PMD_COM_STATUS_3", 15347 NULL, 15348 #endif 15349 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15350 0x0, /* 0 */ 15351 0, 15352 #endif 15353 }, 15354 { 15355 BCMI_TSCF_XGXS_CKRST_OSR_MODE_CTLr, 15356 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15357 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 15358 BCMI_TSCF_XGXS_CKRST_OSR_MODE_CTLr_fields, 15359 #else 15360 0, 15361 #endif 15362 #endif 15363 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15364 PHYMOD_SYMBOL_FLAG_REGISTER, 15365 "CKRST_OSR_MODE_CTLr", 15366 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15367 "CKRST_CTRL_PMD_OSR_MODE_CONTROL", 15368 NULL, 15369 #endif 15370 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15371 0x0, /* 0 */ 15372 0, 15373 #endif 15374 }, 15375 { 15376 BCMI_TSCF_XGXS_CKRST_LN_CLK_RST_N_PWRDWN_CTLr, 15377 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15378 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 15379 BCMI_TSCF_XGXS_CKRST_LN_CLK_RST_N_PWRDWN_CTLr_fields, 15380 #else 15381 0, 15382 #endif 15383 #endif 15384 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15385 PHYMOD_SYMBOL_FLAG_REGISTER, 15386 "CKRST_LN_CLK_RST_N_PWRDWN_CTLr", 15387 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15388 "CKRST_CTRL_PMD_LANE_CLK_RESET_N_POWERDOWN_CONTROL", 15389 NULL, 15390 #endif 15391 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15392 0x0, /* 0 */ 15393 0, 15394 #endif 15395 }, 15396 { 15397 BCMI_TSCF_XGXS_CKRST_LN_AFE_RST_PWRDWN_CTLr, 15398 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15399 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 15400 BCMI_TSCF_XGXS_CKRST_LN_AFE_RST_PWRDWN_CTLr_fields, 15401 #else 15402 0, 15403 #endif 15404 #endif 15405 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15406 PHYMOD_SYMBOL_FLAG_REGISTER, 15407 "CKRST_LN_AFE_RST_PWRDWN_CTLr", 15408 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15409 "CKRST_CTRL_PMD_LANE_AFE_RESET_PWRDWN_CONTROL", 15410 NULL, 15411 #endif 15412 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15413 0x0, /* 0 */ 15414 0, 15415 #endif 15416 }, 15417 { 15418 BCMI_TSCF_XGXS_CKRST_LN_RST_N_PWRDN_PIN_KILL_CTLr, 15419 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15420 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 15421 BCMI_TSCF_XGXS_CKRST_LN_RST_N_PWRDN_PIN_KILL_CTLr_fields, 15422 #else 15423 0, 15424 #endif 15425 #endif 15426 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15427 PHYMOD_SYMBOL_FLAG_REGISTER, 15428 "CKRST_LN_RST_N_PWRDN_PIN_KILL_CTLr", 15429 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15430 "CKRST_CTRL_PMD_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL", 15431 NULL, 15432 #endif 15433 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15434 0x0, /* 0 */ 15435 0, 15436 #endif 15437 }, 15438 { 15439 BCMI_TSCF_XGXS_CKRST_LN_DBG_RST_CTLr, 15440 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15441 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 15442 BCMI_TSCF_XGXS_CKRST_LN_DBG_RST_CTLr_fields, 15443 #else 15444 0, 15445 #endif 15446 #endif 15447 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15448 PHYMOD_SYMBOL_FLAG_REGISTER, 15449 "CKRST_LN_DBG_RST_CTLr", 15450 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15451 "CKRST_CTRL_PMD_LANE_DEBUG_RESET_CONTROL", 15452 NULL, 15453 #endif 15454 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15455 0x303, /* 771 */ 15456 0, 15457 #endif 15458 }, 15459 { 15460 BCMI_TSCF_XGXS_CKRST_UC_ACK_LN_CTLr, 15461 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15462 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 15463 BCMI_TSCF_XGXS_CKRST_UC_ACK_LN_CTLr_fields, 15464 #else 15465 0, 15466 #endif 15467 #endif 15468 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15469 PHYMOD_SYMBOL_FLAG_REGISTER, 15470 "CKRST_UC_ACK_LN_CTLr", 15471 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15472 "CKRST_CTRL_PMD_UC_ACK_LANE_CONTROL", 15473 NULL, 15474 #endif 15475 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15476 0x0, /* 0 */ 15477 0, 15478 #endif 15479 }, 15480 { 15481 BCMI_TSCF_XGXS_CKRST_LN_RST_OCC_CTLr, 15482 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15483 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 15484 BCMI_TSCF_XGXS_CKRST_LN_RST_OCC_CTLr_fields, 15485 #else 15486 0, 15487 #endif 15488 #endif 15489 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15490 PHYMOD_SYMBOL_FLAG_REGISTER, 15491 "CKRST_LN_RST_OCC_CTLr", 15492 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15493 "CKRST_CTRL_PMD_LANE_REG_RESET_OCCURRED_CONTROL", 15494 NULL, 15495 #endif 15496 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15497 0x1, /* 1 */ 15498 0, 15499 #endif 15500 }, 15501 { 15502 BCMI_TSCF_XGXS_CKRST_CLK_N_RST_DBG_CTLr, 15503 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15504 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 15505 BCMI_TSCF_XGXS_CKRST_CLK_N_RST_DBG_CTLr_fields, 15506 #else 15507 0, 15508 #endif 15509 #endif 15510 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15511 PHYMOD_SYMBOL_FLAG_REGISTER, 15512 "CKRST_CLK_N_RST_DBG_CTLr", 15513 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15514 "CKRST_CTRL_PMD_CLOCK_N_RESET_DEBUG_CONTROL", 15515 NULL, 15516 #endif 15517 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15518 0x0, /* 0 */ 15519 0, 15520 #endif 15521 }, 15522 { 15523 BCMI_TSCF_XGXS_CKRST_PMD_LN_MODE_STSr, 15524 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15525 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 15526 BCMI_TSCF_XGXS_CKRST_PMD_LN_MODE_STSr_fields, 15527 #else 15528 0, 15529 #endif 15530 #endif 15531 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15532 PHYMOD_SYMBOL_FLAG_REGISTER, 15533 "CKRST_PMD_LN_MODE_STSr", 15534 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15535 "CKRST_CTRL_PMD_PMD_LANE_MODE_STATUS", 15536 NULL, 15537 #endif 15538 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15539 0x0, /* 0 */ 15540 0, 15541 #endif 15542 }, 15543 { 15544 BCMI_TSCF_XGXS_CKRST_LN_DP_RST_ST_STSr, 15545 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15546 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 15547 BCMI_TSCF_XGXS_CKRST_LN_DP_RST_ST_STSr_fields, 15548 #else 15549 0, 15550 #endif 15551 #endif 15552 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15553 PHYMOD_SYMBOL_FLAG_REGISTER, 15554 "CKRST_LN_DP_RST_ST_STSr", 15555 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15556 "CKRST_CTRL_PMD_LANE_DP_RESET_STATE_STATUS", 15557 NULL, 15558 #endif 15559 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15560 0x7, /* 7 */ 15561 0, 15562 #endif 15563 }, 15564 { 15565 BCMI_TSCF_XGXS_CKRST_LN_MASKr, 15566 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15567 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 15568 BCMI_TSCF_XGXS_CKRST_LN_MASKr_fields, 15569 #else 15570 0, 15571 #endif 15572 #endif 15573 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15574 PHYMOD_SYMBOL_FLAG_REGISTER, 15575 "CKRST_LN_MASKr", 15576 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15577 "CKRST_CTRL_PMD_LN_MASK", 15578 NULL, 15579 #endif 15580 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15581 0x0, /* 0 */ 15582 0, 15583 #endif 15584 }, 15585 { 15586 BCMI_TSCF_XGXS_CKRST_OSR_MODE_STSr, 15587 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15588 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 15589 BCMI_TSCF_XGXS_CKRST_OSR_MODE_STSr_fields, 15590 #else 15591 0, 15592 #endif 15593 #endif 15594 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15595 PHYMOD_SYMBOL_FLAG_REGISTER, 15596 "CKRST_OSR_MODE_STSr", 15597 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15598 "CKRST_CTRL_PMD_OSR_MODE_STATUS", 15599 NULL, 15600 #endif 15601 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15602 0x0, /* 0 */ 15603 0, 15604 #endif 15605 }, 15606 { 15607 BCMI_TSCF_XGXS_CKRST_OSR_MODE_PIN_STSr, 15608 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15609 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 15610 BCMI_TSCF_XGXS_CKRST_OSR_MODE_PIN_STSr_fields, 15611 #else 15612 0, 15613 #endif 15614 #endif 15615 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15616 PHYMOD_SYMBOL_FLAG_REGISTER, 15617 "CKRST_OSR_MODE_PIN_STSr", 15618 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15619 "CKRST_CTRL_PMD_OSR_MODE_PIN_STATUS", 15620 NULL, 15621 #endif 15622 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15623 0x0, /* 0 */ 15624 0, 15625 #endif 15626 }, 15627 { 15628 BCMI_TSCF_XGXS_CKRST_LN_S_RSTB_CTLr, 15629 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15630 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 15631 BCMI_TSCF_XGXS_CKRST_LN_S_RSTB_CTLr_fields, 15632 #else 15633 0, 15634 #endif 15635 #endif 15636 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15637 PHYMOD_SYMBOL_FLAG_REGISTER, 15638 "CKRST_LN_S_RSTB_CTLr", 15639 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15640 "CKRST_CTRL_PMD_LN_S_RSTB_CONTROL", 15641 NULL, 15642 #endif 15643 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15644 0x1, /* 1 */ 15645 0, 15646 #endif 15647 }, 15648 { 15649 BCMI_TSCF_XGXS_AMS_RX_CTL0r, 15650 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15651 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 15652 BCMI_TSCF_XGXS_AMS_RX_CTL0r_fields, 15653 #else 15654 0, 15655 #endif 15656 #endif 15657 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15658 PHYMOD_SYMBOL_FLAG_REGISTER, 15659 "AMS_RX_CTL0r", 15660 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15661 "AMS_RX_CONTROL_0", 15662 NULL, 15663 #endif 15664 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15665 0x10, /* 16 */ 15666 0, 15667 #endif 15668 }, 15669 { 15670 BCMI_TSCF_XGXS_AMS_RX_CTL1r, 15671 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15672 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 15673 BCMI_TSCF_XGXS_AMS_RX_CTL1r_fields, 15674 #else 15675 0, 15676 #endif 15677 #endif 15678 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15679 PHYMOD_SYMBOL_FLAG_REGISTER, 15680 "AMS_RX_CTL1r", 15681 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15682 "AMS_RX_CONTROL_1", 15683 NULL, 15684 #endif 15685 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15686 0x0, /* 0 */ 15687 0, 15688 #endif 15689 }, 15690 { 15691 BCMI_TSCF_XGXS_AMS_RX_CTL2r, 15692 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15693 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 15694 BCMI_TSCF_XGXS_AMS_RX_CTL2r_fields, 15695 #else 15696 0, 15697 #endif 15698 #endif 15699 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15700 PHYMOD_SYMBOL_FLAG_REGISTER, 15701 "AMS_RX_CTL2r", 15702 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15703 "AMS_RX_CONTROL_2", 15704 NULL, 15705 #endif 15706 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15707 0xe00, /* 3584 */ 15708 0, 15709 #endif 15710 }, 15711 { 15712 BCMI_TSCF_XGXS_AMS_RX_CTL3r, 15713 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15714 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 15715 BCMI_TSCF_XGXS_AMS_RX_CTL3r_fields, 15716 #else 15717 0, 15718 #endif 15719 #endif 15720 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15721 PHYMOD_SYMBOL_FLAG_REGISTER, 15722 "AMS_RX_CTL3r", 15723 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15724 "AMS_RX_CONTROL_3", 15725 NULL, 15726 #endif 15727 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15728 0x0, /* 0 */ 15729 0, 15730 #endif 15731 }, 15732 { 15733 BCMI_TSCF_XGXS_AMS_RX_CTL4r, 15734 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15735 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 15736 BCMI_TSCF_XGXS_AMS_RX_CTL4r_fields, 15737 #else 15738 0, 15739 #endif 15740 #endif 15741 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15742 PHYMOD_SYMBOL_FLAG_REGISTER, 15743 "AMS_RX_CTL4r", 15744 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15745 "AMS_RX_CONTROL_4", 15746 NULL, 15747 #endif 15748 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15749 0x0, /* 0 */ 15750 0, 15751 #endif 15752 }, 15753 { 15754 BCMI_TSCF_XGXS_AMS_RX_CTL5r, 15755 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15756 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 15757 BCMI_TSCF_XGXS_AMS_RX_CTL5r_fields, 15758 #else 15759 0, 15760 #endif 15761 #endif 15762 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15763 PHYMOD_SYMBOL_FLAG_REGISTER, 15764 "AMS_RX_CTL5r", 15765 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15766 "AMS_RX_CONTROL_5", 15767 NULL, 15768 #endif 15769 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15770 0x0, /* 0 */ 15771 0, 15772 #endif 15773 }, 15774 { 15775 BCMI_TSCF_XGXS_AMS_RX_CTL6r, 15776 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15777 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 15778 BCMI_TSCF_XGXS_AMS_RX_CTL6r_fields, 15779 #else 15780 0, 15781 #endif 15782 #endif 15783 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15784 PHYMOD_SYMBOL_FLAG_REGISTER, 15785 "AMS_RX_CTL6r", 15786 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15787 "AMS_RX_CONTROL_6", 15788 NULL, 15789 #endif 15790 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15791 0x0, /* 0 */ 15792 0, 15793 #endif 15794 }, 15795 { 15796 BCMI_TSCF_XGXS_AMS_RX_CTL7r, 15797 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15798 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 15799 BCMI_TSCF_XGXS_AMS_RX_CTL7r_fields, 15800 #else 15801 0, 15802 #endif 15803 #endif 15804 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15805 PHYMOD_SYMBOL_FLAG_REGISTER, 15806 "AMS_RX_CTL7r", 15807 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15808 "AMS_RX_CONTROL_7", 15809 NULL, 15810 #endif 15811 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15812 0x0, /* 0 */ 15813 0, 15814 #endif 15815 }, 15816 { 15817 BCMI_TSCF_XGXS_AMS_RX_CTL8r, 15818 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15819 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 15820 BCMI_TSCF_XGXS_AMS_RX_CTL8r_fields, 15821 #else 15822 0, 15823 #endif 15824 #endif 15825 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15826 PHYMOD_SYMBOL_FLAG_REGISTER, 15827 "AMS_RX_CTL8r", 15828 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15829 "AMS_RX_CONTROL_8", 15830 NULL, 15831 #endif 15832 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15833 0x0, /* 0 */ 15834 0, 15835 #endif 15836 }, 15837 { 15838 BCMI_TSCF_XGXS_AMS_RX_CTL9r, 15839 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15840 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 15841 BCMI_TSCF_XGXS_AMS_RX_CTL9r_fields, 15842 #else 15843 0, 15844 #endif 15845 #endif 15846 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15847 PHYMOD_SYMBOL_FLAG_REGISTER, 15848 "AMS_RX_CTL9r", 15849 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15850 "AMS_RX_CONTROL_9", 15851 NULL, 15852 #endif 15853 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15854 0x300, /* 768 */ 15855 0, 15856 #endif 15857 }, 15858 { 15859 BCMI_TSCF_XGXS_AMS_RX_STSr, 15860 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15861 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 15862 BCMI_TSCF_XGXS_AMS_RX_STSr_fields, 15863 #else 15864 0, 15865 #endif 15866 #endif 15867 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15868 PHYMOD_SYMBOL_FLAG_REGISTER, 15869 "AMS_RX_STSr", 15870 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15871 "AMS_RX_STATUS", 15872 NULL, 15873 #endif 15874 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15875 0x8000, /* 32768 */ 15876 0, 15877 #endif 15878 }, 15879 { 15880 BCMI_TSCF_XGXS_AMS_TX_CTL0r, 15881 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15882 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 15883 BCMI_TSCF_XGXS_AMS_TX_CTL0r_fields, 15884 #else 15885 0, 15886 #endif 15887 #endif 15888 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15889 PHYMOD_SYMBOL_FLAG_REGISTER, 15890 "AMS_TX_CTL0r", 15891 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15892 "AMS_TX_CONTROL_0", 15893 NULL, 15894 #endif 15895 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15896 0xc0, /* 192 */ 15897 0, 15898 #endif 15899 }, 15900 { 15901 BCMI_TSCF_XGXS_AMS_TX_CTL1r, 15902 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15903 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 15904 BCMI_TSCF_XGXS_AMS_TX_CTL1r_fields, 15905 #else 15906 0, 15907 #endif 15908 #endif 15909 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15910 PHYMOD_SYMBOL_FLAG_REGISTER, 15911 "AMS_TX_CTL1r", 15912 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15913 "AMS_TX_CONTROL_1", 15914 NULL, 15915 #endif 15916 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15917 0x2000, /* 8192 */ 15918 0, 15919 #endif 15920 }, 15921 { 15922 BCMI_TSCF_XGXS_AMS_TX_CTL2r, 15923 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15924 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 15925 BCMI_TSCF_XGXS_AMS_TX_CTL2r_fields, 15926 #else 15927 0, 15928 #endif 15929 #endif 15930 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15931 PHYMOD_SYMBOL_FLAG_REGISTER, 15932 "AMS_TX_CTL2r", 15933 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15934 "AMS_TX_CONTROL_2", 15935 NULL, 15936 #endif 15937 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15938 0xf, /* 15 */ 15939 0, 15940 #endif 15941 }, 15942 { 15943 BCMI_TSCF_XGXS_AMS_TX_CTL3r, 15944 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15945 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 15946 BCMI_TSCF_XGXS_AMS_TX_CTL3r_fields, 15947 #else 15948 0, 15949 #endif 15950 #endif 15951 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15952 PHYMOD_SYMBOL_FLAG_REGISTER, 15953 "AMS_TX_CTL3r", 15954 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15955 "AMS_TX_CONTROL_3", 15956 NULL, 15957 #endif 15958 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15959 0x0, /* 0 */ 15960 0, 15961 #endif 15962 }, 15963 { 15964 BCMI_TSCF_XGXS_AMS_TX_STSr, 15965 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15966 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 15967 BCMI_TSCF_XGXS_AMS_TX_STSr_fields, 15968 #else 15969 0, 15970 #endif 15971 #endif 15972 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15973 PHYMOD_SYMBOL_FLAG_REGISTER, 15974 "AMS_TX_STSr", 15975 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15976 "AMS_TX_STATUS", 15977 NULL, 15978 #endif 15979 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15980 0xa0, /* 160 */ 15981 0, 15982 #endif 15983 }, 15984 { 15985 BCMI_TSCF_XGXS_SIGDET_CTL0r, 15986 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15987 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 15988 BCMI_TSCF_XGXS_SIGDET_CTL0r_fields, 15989 #else 15990 0, 15991 #endif 15992 #endif 15993 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15994 PHYMOD_SYMBOL_FLAG_REGISTER, 15995 "SIGDET_CTL0r", 15996 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15997 "SIGDET_CTRL_0", 15998 NULL, 15999 #endif 16000 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16001 0x1109, /* 4361 */ 16002 0, 16003 #endif 16004 }, 16005 { 16006 BCMI_TSCF_XGXS_SIGDET_CTL1r, 16007 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16008 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 16009 BCMI_TSCF_XGXS_SIGDET_CTL1r_fields, 16010 #else 16011 0, 16012 #endif 16013 #endif 16014 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16015 PHYMOD_SYMBOL_FLAG_REGISTER, 16016 "SIGDET_CTL1r", 16017 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16018 "SIGDET_CTRL_1", 16019 NULL, 16020 #endif 16021 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16022 0xa008, /* 40968 */ 16023 0, 16024 #endif 16025 }, 16026 { 16027 BCMI_TSCF_XGXS_SIGDET_CTL2r, 16028 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16029 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 16030 BCMI_TSCF_XGXS_SIGDET_CTL2r_fields, 16031 #else 16032 0, 16033 #endif 16034 #endif 16035 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16036 PHYMOD_SYMBOL_FLAG_REGISTER, 16037 "SIGDET_CTL2r", 16038 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16039 "SIGDET_CTRL_2", 16040 NULL, 16041 #endif 16042 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16043 0x3f22, /* 16162 */ 16044 0, 16045 #endif 16046 }, 16047 { 16048 BCMI_TSCF_XGXS_SIGDET_STS0r, 16049 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16050 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 16051 BCMI_TSCF_XGXS_SIGDET_STS0r_fields, 16052 #else 16053 0, 16054 #endif 16055 #endif 16056 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16057 PHYMOD_SYMBOL_FLAG_REGISTER, 16058 "SIGDET_STS0r", 16059 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16060 "SIGDET_STATUS_0", 16061 NULL, 16062 #endif 16063 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16064 0x200, /* 512 */ 16065 0, 16066 #endif 16067 }, 16068 { 16069 BCMI_TSCF_XGXS_DIG_REVID0r, 16070 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16071 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 16072 BCMI_TSCF_XGXS_DIG_REVID0r_fields, 16073 #else 16074 0, 16075 #endif 16076 #endif 16077 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16078 PHYMOD_SYMBOL_FLAG_REGISTER, 16079 "DIG_REVID0r", 16080 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16081 "DIG_COM_REVID0", 16082 NULL, 16083 #endif 16084 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16085 0x2db, /* 731 */ 16086 0, 16087 #endif 16088 }, 16089 { 16090 BCMI_TSCF_XGXS_DIG_RST_CTL_PMDr, 16091 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16092 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 16093 BCMI_TSCF_XGXS_DIG_RST_CTL_PMDr_fields, 16094 #else 16095 0, 16096 #endif 16097 #endif 16098 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16099 PHYMOD_SYMBOL_FLAG_REGISTER, 16100 "DIG_RST_CTL_PMDr", 16101 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16102 "DIG_COM_RESET_CONTROL_PMD", 16103 NULL, 16104 #endif 16105 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16106 0x1, /* 1 */ 16107 0, 16108 #endif 16109 }, 16110 { 16111 BCMI_TSCF_XGXS_DIG_RST_CTL_CORE_DPr, 16112 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16113 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 16114 BCMI_TSCF_XGXS_DIG_RST_CTL_CORE_DPr_fields, 16115 #else 16116 0, 16117 #endif 16118 #endif 16119 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16120 PHYMOD_SYMBOL_FLAG_REGISTER, 16121 "DIG_RST_CTL_CORE_DPr", 16122 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16123 "DIG_COM_RESET_CONTROL_CORE_DP", 16124 NULL, 16125 #endif 16126 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16127 0x4000, /* 16384 */ 16128 0, 16129 #endif 16130 }, 16131 { 16132 BCMI_TSCF_XGXS_DIG_LN_MASKr, 16133 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16134 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 16135 BCMI_TSCF_XGXS_DIG_LN_MASKr_fields, 16136 #else 16137 0, 16138 #endif 16139 #endif 16140 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16141 PHYMOD_SYMBOL_FLAG_REGISTER, 16142 "DIG_LN_MASKr", 16143 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16144 "DIG_COM_LANE_MASK", 16145 NULL, 16146 #endif 16147 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16148 0x0, /* 0 */ 16149 0, 16150 #endif 16151 }, 16152 { 16153 BCMI_TSCF_XGXS_DIG_TOP_USER_CTL0r, 16154 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16155 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 16156 BCMI_TSCF_XGXS_DIG_TOP_USER_CTL0r_fields, 16157 #else 16158 0, 16159 #endif 16160 #endif 16161 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16162 PHYMOD_SYMBOL_FLAG_REGISTER, 16163 "DIG_TOP_USER_CTL0r", 16164 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16165 "DIG_COM_TOP_USER_CONTROL_0", 16166 NULL, 16167 #endif 16168 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16169 0x271, /* 625 */ 16170 0, 16171 #endif 16172 }, 16173 { 16174 BCMI_TSCF_XGXS_DIG_UC_ACK_CORE_CTLr, 16175 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16176 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 16177 BCMI_TSCF_XGXS_DIG_UC_ACK_CORE_CTLr_fields, 16178 #else 16179 0, 16180 #endif 16181 #endif 16182 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16183 PHYMOD_SYMBOL_FLAG_REGISTER, 16184 "DIG_UC_ACK_CORE_CTLr", 16185 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16186 "DIG_COM_UC_ACK_CORE_CONTROL", 16187 NULL, 16188 #endif 16189 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16190 0x0, /* 0 */ 16191 0, 16192 #endif 16193 }, 16194 { 16195 BCMI_TSCF_XGXS_DIG_CORE_RST_OCC_CTLr, 16196 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16197 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 16198 BCMI_TSCF_XGXS_DIG_CORE_RST_OCC_CTLr_fields, 16199 #else 16200 0, 16201 #endif 16202 #endif 16203 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16204 PHYMOD_SYMBOL_FLAG_REGISTER, 16205 "DIG_CORE_RST_OCC_CTLr", 16206 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16207 "DIG_COM_CORE_REG_RESET_OCCURRED_CONTROL", 16208 NULL, 16209 #endif 16210 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16211 0x1, /* 1 */ 16212 0, 16213 #endif 16214 }, 16215 { 16216 BCMI_TSCF_XGXS_DIG_RST_SEQ_TMR_CTLr, 16217 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16218 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 16219 BCMI_TSCF_XGXS_DIG_RST_SEQ_TMR_CTLr_fields, 16220 #else 16221 0, 16222 #endif 16223 #endif 16224 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16225 PHYMOD_SYMBOL_FLAG_REGISTER, 16226 "DIG_RST_SEQ_TMR_CTLr", 16227 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16228 "DIG_COM_RST_SEQ_TIMER_CONTROL", 16229 NULL, 16230 #endif 16231 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16232 0x8304, /* 33540 */ 16233 0, 16234 #endif 16235 }, 16236 { 16237 BCMI_TSCF_XGXS_DIG_CORE_DP_RST_ST_STSr, 16238 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16239 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 16240 BCMI_TSCF_XGXS_DIG_CORE_DP_RST_ST_STSr_fields, 16241 #else 16242 0, 16243 #endif 16244 #endif 16245 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16246 PHYMOD_SYMBOL_FLAG_REGISTER, 16247 "DIG_CORE_DP_RST_ST_STSr", 16248 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16249 "DIG_COM_CORE_DP_RESET_STATE_STATUS", 16250 NULL, 16251 #endif 16252 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16253 0x7, /* 7 */ 16254 0, 16255 #endif 16256 }, 16257 { 16258 BCMI_TSCF_XGXS_DIG_PMD_CORE_MODE_STSr, 16259 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16260 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 16261 BCMI_TSCF_XGXS_DIG_PMD_CORE_MODE_STSr_fields, 16262 #else 16263 0, 16264 #endif 16265 #endif 16266 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16267 PHYMOD_SYMBOL_FLAG_REGISTER, 16268 "DIG_PMD_CORE_MODE_STSr", 16269 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16270 "DIG_COM_PMD_CORE_MODE_STATUS", 16271 NULL, 16272 #endif 16273 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16274 0x0, /* 0 */ 16275 0, 16276 #endif 16277 }, 16278 { 16279 BCMI_TSCF_XGXS_DIG_REVID1r, 16280 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16281 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 16282 BCMI_TSCF_XGXS_DIG_REVID1r_fields, 16283 #else 16284 0, 16285 #endif 16286 #endif 16287 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16288 PHYMOD_SYMBOL_FLAG_REGISTER, 16289 "DIG_REVID1r", 16290 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16291 "DIG_COM_REVID1", 16292 NULL, 16293 #endif 16294 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16295 0x403c, /* 16444 */ 16296 0, 16297 #endif 16298 }, 16299 { 16300 BCMI_TSCF_XGXS_DIG_TX_LN_MAP_0_1_2r, 16301 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16302 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 16303 BCMI_TSCF_XGXS_DIG_TX_LN_MAP_0_1_2r_fields, 16304 #else 16305 0, 16306 #endif 16307 #endif 16308 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16309 PHYMOD_SYMBOL_FLAG_REGISTER, 16310 "DIG_TX_LN_MAP_0_1_2r", 16311 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16312 "DIG_COM_TX_LANE_MAP_0_1_2", 16313 NULL, 16314 #endif 16315 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16316 0x820, /* 2080 */ 16317 0, 16318 #endif 16319 }, 16320 { 16321 BCMI_TSCF_XGXS_DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r, 16322 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16323 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 16324 BCMI_TSCF_XGXS_DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r_fields, 16325 #else 16326 0, 16327 #endif 16328 #endif 16329 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16330 PHYMOD_SYMBOL_FLAG_REGISTER, 16331 "DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r", 16332 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16333 "DIG_COM_TX_LANE_MAP_3_N_LANE_ADDR_0_1", 16334 NULL, 16335 #endif 16336 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16337 0x403, /* 1027 */ 16338 0, 16339 #endif 16340 }, 16341 { 16342 BCMI_TSCF_XGXS_DIG_LN_ADDR_2_3r, 16343 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16344 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 16345 BCMI_TSCF_XGXS_DIG_LN_ADDR_2_3r_fields, 16346 #else 16347 0, 16348 #endif 16349 #endif 16350 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16351 PHYMOD_SYMBOL_FLAG_REGISTER, 16352 "DIG_LN_ADDR_2_3r", 16353 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16354 "DIG_COM_LANE_ADDR_2_3", 16355 NULL, 16356 #endif 16357 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16358 0x302, /* 770 */ 16359 0, 16360 #endif 16361 }, 16362 { 16363 BCMI_TSCF_XGXS_DIG_REVID2r, 16364 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16365 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 16366 BCMI_TSCF_XGXS_DIG_REVID2r_fields, 16367 #else 16368 0, 16369 #endif 16370 #endif 16371 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16372 PHYMOD_SYMBOL_FLAG_REGISTER, 16373 "DIG_REVID2r", 16374 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16375 "DIG_COM_REVID2", 16376 NULL, 16377 #endif 16378 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16379 0x0, /* 0 */ 16380 0, 16381 #endif 16382 }, 16383 { 16384 BCMI_TSCF_XGXS_AMS_PLL_CTL0r, 16385 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16386 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 16387 BCMI_TSCF_XGXS_AMS_PLL_CTL0r_fields, 16388 #else 16389 0, 16390 #endif 16391 #endif 16392 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16393 PHYMOD_SYMBOL_FLAG_REGISTER, 16394 "AMS_PLL_CTL0r", 16395 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16396 "AMS_COM_PLL_CONTROL_0", 16397 NULL, 16398 #endif 16399 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16400 0x0, /* 0 */ 16401 0, 16402 #endif 16403 }, 16404 { 16405 BCMI_TSCF_XGXS_AMS_PLL_CTL1r, 16406 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16407 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 16408 BCMI_TSCF_XGXS_AMS_PLL_CTL1r_fields, 16409 #else 16410 0, 16411 #endif 16412 #endif 16413 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16414 PHYMOD_SYMBOL_FLAG_REGISTER, 16415 "AMS_PLL_CTL1r", 16416 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16417 "AMS_COM_PLL_CONTROL_1", 16418 NULL, 16419 #endif 16420 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16421 0x8000, /* 32768 */ 16422 0, 16423 #endif 16424 }, 16425 { 16426 BCMI_TSCF_XGXS_AMS_PLL_CTL2r, 16427 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16428 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 16429 BCMI_TSCF_XGXS_AMS_PLL_CTL2r_fields, 16430 #else 16431 0, 16432 #endif 16433 #endif 16434 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16435 PHYMOD_SYMBOL_FLAG_REGISTER, 16436 "AMS_PLL_CTL2r", 16437 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16438 "AMS_COM_PLL_CONTROL_2", 16439 NULL, 16440 #endif 16441 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16442 0x1e, /* 30 */ 16443 0, 16444 #endif 16445 }, 16446 { 16447 BCMI_TSCF_XGXS_AMS_PLL_CTL3r, 16448 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16449 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 16450 BCMI_TSCF_XGXS_AMS_PLL_CTL3r_fields, 16451 #else 16452 0, 16453 #endif 16454 #endif 16455 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16456 PHYMOD_SYMBOL_FLAG_REGISTER, 16457 "AMS_PLL_CTL3r", 16458 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16459 "AMS_COM_PLL_CONTROL_3", 16460 NULL, 16461 #endif 16462 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16463 0x0, /* 0 */ 16464 0, 16465 #endif 16466 }, 16467 { 16468 BCMI_TSCF_XGXS_AMS_PLL_CTL4r, 16469 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16470 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 16471 BCMI_TSCF_XGXS_AMS_PLL_CTL4r_fields, 16472 #else 16473 0, 16474 #endif 16475 #endif 16476 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16477 PHYMOD_SYMBOL_FLAG_REGISTER, 16478 "AMS_PLL_CTL4r", 16479 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16480 "AMS_COM_PLL_CONTROL_4", 16481 NULL, 16482 #endif 16483 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16484 0x77, /* 119 */ 16485 0, 16486 #endif 16487 }, 16488 { 16489 BCMI_TSCF_XGXS_AMS_PLL_CTL5r, 16490 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16491 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 16492 BCMI_TSCF_XGXS_AMS_PLL_CTL5r_fields, 16493 #else 16494 0, 16495 #endif 16496 #endif 16497 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16498 PHYMOD_SYMBOL_FLAG_REGISTER, 16499 "AMS_PLL_CTL5r", 16500 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16501 "AMS_COM_PLL_CONTROL_5", 16502 NULL, 16503 #endif 16504 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16505 0x1f00, /* 7936 */ 16506 0, 16507 #endif 16508 }, 16509 { 16510 BCMI_TSCF_XGXS_AMS_PLL_CTL6r, 16511 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16512 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 16513 BCMI_TSCF_XGXS_AMS_PLL_CTL6r_fields, 16514 #else 16515 0, 16516 #endif 16517 #endif 16518 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16519 PHYMOD_SYMBOL_FLAG_REGISTER, 16520 "AMS_PLL_CTL6r", 16521 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16522 "AMS_COM_PLL_CONTROL_6", 16523 NULL, 16524 #endif 16525 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16526 0xc1c0, /* 49600 */ 16527 0, 16528 #endif 16529 }, 16530 { 16531 BCMI_TSCF_XGXS_AMS_PLL_CTL7r, 16532 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16533 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 16534 BCMI_TSCF_XGXS_AMS_PLL_CTL7r_fields, 16535 #else 16536 0, 16537 #endif 16538 #endif 16539 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16540 PHYMOD_SYMBOL_FLAG_REGISTER, 16541 "AMS_PLL_CTL7r", 16542 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16543 "AMS_COM_PLL_CONTROL_7", 16544 NULL, 16545 #endif 16546 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16547 0x1f00, /* 7936 */ 16548 0, 16549 #endif 16550 }, 16551 { 16552 BCMI_TSCF_XGXS_AMS_PLL_STSr, 16553 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16554 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 16555 BCMI_TSCF_XGXS_AMS_PLL_STSr_fields, 16556 #else 16557 0, 16558 #endif 16559 #endif 16560 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16561 PHYMOD_SYMBOL_FLAG_REGISTER, 16562 "AMS_PLL_STSr", 16563 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16564 "AMS_COM_PLL_STATUS", 16565 NULL, 16566 #endif 16567 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16568 0xc007, /* 49159 */ 16569 0, 16570 #endif 16571 }, 16572 { 16573 BCMI_TSCF_XGXS_PATT_GEN_SEQ0r, 16574 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16575 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 16576 BCMI_TSCF_XGXS_PATT_GEN_SEQ0r_fields, 16577 #else 16578 0, 16579 #endif 16580 #endif 16581 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16582 PHYMOD_SYMBOL_FLAG_REGISTER, 16583 "PATT_GEN_SEQ0r", 16584 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16585 "PATT_GEN_COM_SEQ_0", 16586 NULL, 16587 #endif 16588 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16589 0xff00, /* 65280 */ 16590 0, 16591 #endif 16592 }, 16593 { 16594 BCMI_TSCF_XGXS_PATT_GEN_SEQ1r, 16595 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16596 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 16597 BCMI_TSCF_XGXS_PATT_GEN_SEQ1r_fields, 16598 #else 16599 0, 16600 #endif 16601 #endif 16602 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16603 PHYMOD_SYMBOL_FLAG_REGISTER, 16604 "PATT_GEN_SEQ1r", 16605 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16606 "PATT_GEN_COM_SEQ_1", 16607 NULL, 16608 #endif 16609 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16610 0xff00, /* 65280 */ 16611 0, 16612 #endif 16613 }, 16614 { 16615 BCMI_TSCF_XGXS_PATT_GEN_SEQ2r, 16616 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16617 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 16618 BCMI_TSCF_XGXS_PATT_GEN_SEQ2r_fields, 16619 #else 16620 0, 16621 #endif 16622 #endif 16623 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16624 PHYMOD_SYMBOL_FLAG_REGISTER, 16625 "PATT_GEN_SEQ2r", 16626 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16627 "PATT_GEN_COM_SEQ_2", 16628 NULL, 16629 #endif 16630 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16631 0xff00, /* 65280 */ 16632 0, 16633 #endif 16634 }, 16635 { 16636 BCMI_TSCF_XGXS_PATT_GEN_SEQ3r, 16637 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16638 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 16639 BCMI_TSCF_XGXS_PATT_GEN_SEQ3r_fields, 16640 #else 16641 0, 16642 #endif 16643 #endif 16644 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16645 PHYMOD_SYMBOL_FLAG_REGISTER, 16646 "PATT_GEN_SEQ3r", 16647 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16648 "PATT_GEN_COM_SEQ_3", 16649 NULL, 16650 #endif 16651 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16652 0xff00, /* 65280 */ 16653 0, 16654 #endif 16655 }, 16656 { 16657 BCMI_TSCF_XGXS_PATT_GEN_SEQ4r, 16658 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16659 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 16660 BCMI_TSCF_XGXS_PATT_GEN_SEQ4r_fields, 16661 #else 16662 0, 16663 #endif 16664 #endif 16665 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16666 PHYMOD_SYMBOL_FLAG_REGISTER, 16667 "PATT_GEN_SEQ4r", 16668 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16669 "PATT_GEN_COM_SEQ_4", 16670 NULL, 16671 #endif 16672 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16673 0xff00, /* 65280 */ 16674 0, 16675 #endif 16676 }, 16677 { 16678 BCMI_TSCF_XGXS_PATT_GEN_SEQ5r, 16679 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16680 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 16681 BCMI_TSCF_XGXS_PATT_GEN_SEQ5r_fields, 16682 #else 16683 0, 16684 #endif 16685 #endif 16686 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16687 PHYMOD_SYMBOL_FLAG_REGISTER, 16688 "PATT_GEN_SEQ5r", 16689 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16690 "PATT_GEN_COM_SEQ_5", 16691 NULL, 16692 #endif 16693 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16694 0xff00, /* 65280 */ 16695 0, 16696 #endif 16697 }, 16698 { 16699 BCMI_TSCF_XGXS_PATT_GEN_SEQ6r, 16700 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16701 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 16702 BCMI_TSCF_XGXS_PATT_GEN_SEQ6r_fields, 16703 #else 16704 0, 16705 #endif 16706 #endif 16707 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16708 PHYMOD_SYMBOL_FLAG_REGISTER, 16709 "PATT_GEN_SEQ6r", 16710 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16711 "PATT_GEN_COM_SEQ_6", 16712 NULL, 16713 #endif 16714 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16715 0xff00, /* 65280 */ 16716 0, 16717 #endif 16718 }, 16719 { 16720 BCMI_TSCF_XGXS_PATT_GEN_SEQ7r, 16721 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16722 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 16723 BCMI_TSCF_XGXS_PATT_GEN_SEQ7r_fields, 16724 #else 16725 0, 16726 #endif 16727 #endif 16728 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16729 PHYMOD_SYMBOL_FLAG_REGISTER, 16730 "PATT_GEN_SEQ7r", 16731 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16732 "PATT_GEN_COM_SEQ_7", 16733 NULL, 16734 #endif 16735 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16736 0xff00, /* 65280 */ 16737 0, 16738 #endif 16739 }, 16740 { 16741 BCMI_TSCF_XGXS_PATT_GEN_SEQ8r, 16742 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16743 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 16744 BCMI_TSCF_XGXS_PATT_GEN_SEQ8r_fields, 16745 #else 16746 0, 16747 #endif 16748 #endif 16749 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16750 PHYMOD_SYMBOL_FLAG_REGISTER, 16751 "PATT_GEN_SEQ8r", 16752 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16753 "PATT_GEN_COM_SEQ_8", 16754 NULL, 16755 #endif 16756 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16757 0xff00, /* 65280 */ 16758 0, 16759 #endif 16760 }, 16761 { 16762 BCMI_TSCF_XGXS_PATT_GEN_SEQ9r, 16763 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16764 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 16765 BCMI_TSCF_XGXS_PATT_GEN_SEQ9r_fields, 16766 #else 16767 0, 16768 #endif 16769 #endif 16770 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16771 PHYMOD_SYMBOL_FLAG_REGISTER, 16772 "PATT_GEN_SEQ9r", 16773 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16774 "PATT_GEN_COM_SEQ_9", 16775 NULL, 16776 #endif 16777 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16778 0xff00, /* 65280 */ 16779 0, 16780 #endif 16781 }, 16782 { 16783 BCMI_TSCF_XGXS_PATT_GEN_SEQ_10r, 16784 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16785 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 16786 BCMI_TSCF_XGXS_PATT_GEN_SEQ_10r_fields, 16787 #else 16788 0, 16789 #endif 16790 #endif 16791 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16792 PHYMOD_SYMBOL_FLAG_REGISTER, 16793 "PATT_GEN_SEQ_10r", 16794 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16795 "PATT_GEN_COM_SEQ_10", 16796 NULL, 16797 #endif 16798 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16799 0xff00, /* 65280 */ 16800 0, 16801 #endif 16802 }, 16803 { 16804 BCMI_TSCF_XGXS_PATT_GEN_SEQ_11r, 16805 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16806 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 16807 BCMI_TSCF_XGXS_PATT_GEN_SEQ_11r_fields, 16808 #else 16809 0, 16810 #endif 16811 #endif 16812 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16813 PHYMOD_SYMBOL_FLAG_REGISTER, 16814 "PATT_GEN_SEQ_11r", 16815 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16816 "PATT_GEN_COM_SEQ_11", 16817 NULL, 16818 #endif 16819 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16820 0xff00, /* 65280 */ 16821 0, 16822 #endif 16823 }, 16824 { 16825 BCMI_TSCF_XGXS_PATT_GEN_SEQ_12r, 16826 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16827 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 16828 BCMI_TSCF_XGXS_PATT_GEN_SEQ_12r_fields, 16829 #else 16830 0, 16831 #endif 16832 #endif 16833 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16834 PHYMOD_SYMBOL_FLAG_REGISTER, 16835 "PATT_GEN_SEQ_12r", 16836 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16837 "PATT_GEN_COM_SEQ_12", 16838 NULL, 16839 #endif 16840 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16841 0xff00, /* 65280 */ 16842 0, 16843 #endif 16844 }, 16845 { 16846 BCMI_TSCF_XGXS_PATT_GEN_SEQ_13r, 16847 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16848 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 16849 BCMI_TSCF_XGXS_PATT_GEN_SEQ_13r_fields, 16850 #else 16851 0, 16852 #endif 16853 #endif 16854 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16855 PHYMOD_SYMBOL_FLAG_REGISTER, 16856 "PATT_GEN_SEQ_13r", 16857 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16858 "PATT_GEN_COM_SEQ_13", 16859 NULL, 16860 #endif 16861 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16862 0xff00, /* 65280 */ 16863 0, 16864 #endif 16865 }, 16866 { 16867 BCMI_TSCF_XGXS_PATT_GEN_SEQ_14r, 16868 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16869 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 16870 BCMI_TSCF_XGXS_PATT_GEN_SEQ_14r_fields, 16871 #else 16872 0, 16873 #endif 16874 #endif 16875 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16876 PHYMOD_SYMBOL_FLAG_REGISTER, 16877 "PATT_GEN_SEQ_14r", 16878 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16879 "PATT_GEN_COM_SEQ_14", 16880 NULL, 16881 #endif 16882 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16883 0xff00, /* 65280 */ 16884 0, 16885 #endif 16886 }, 16887 { 16888 BCMI_TSCF_XGXS_TXFIR_CTL0r, 16889 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16890 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 16891 BCMI_TSCF_XGXS_TXFIR_CTL0r_fields, 16892 #else 16893 0, 16894 #endif 16895 #endif 16896 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16897 PHYMOD_SYMBOL_FLAG_REGISTER, 16898 "TXFIR_CTL0r", 16899 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16900 "TX_FED_TXFIR_CONTROL0", 16901 NULL, 16902 #endif 16903 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16904 0x0, /* 0 */ 16905 0, 16906 #endif 16907 }, 16908 { 16909 BCMI_TSCF_XGXS_TXFIR_CTL1r, 16910 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16911 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 16912 BCMI_TSCF_XGXS_TXFIR_CTL1r_fields, 16913 #else 16914 0, 16915 #endif 16916 #endif 16917 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16918 PHYMOD_SYMBOL_FLAG_REGISTER, 16919 "TXFIR_CTL1r", 16920 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16921 "TX_FED_TXFIR_CONTROL1", 16922 NULL, 16923 #endif 16924 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16925 0x0, /* 0 */ 16926 0, 16927 #endif 16928 }, 16929 { 16930 BCMI_TSCF_XGXS_TXFIR_CTL2r, 16931 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16932 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 16933 BCMI_TSCF_XGXS_TXFIR_CTL2r_fields, 16934 #else 16935 0, 16936 #endif 16937 #endif 16938 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16939 PHYMOD_SYMBOL_FLAG_REGISTER, 16940 "TXFIR_CTL2r", 16941 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16942 "TX_FED_TXFIR_CONTROL2", 16943 NULL, 16944 #endif 16945 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16946 0x800, /* 2048 */ 16947 0, 16948 #endif 16949 }, 16950 { 16951 BCMI_TSCF_XGXS_TXFIR_STS0r, 16952 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16953 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 16954 BCMI_TSCF_XGXS_TXFIR_STS0r_fields, 16955 #else 16956 0, 16957 #endif 16958 #endif 16959 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16960 PHYMOD_SYMBOL_FLAG_REGISTER, 16961 "TXFIR_STS0r", 16962 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16963 "TX_FED_TXFIR_STATUS0", 16964 NULL, 16965 #endif 16966 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16967 0x2c08, /* 11272 */ 16968 0, 16969 #endif 16970 }, 16971 { 16972 BCMI_TSCF_XGXS_TXFIR_STS1r, 16973 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16974 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 16975 BCMI_TSCF_XGXS_TXFIR_STS1r_fields, 16976 #else 16977 0, 16978 #endif 16979 #endif 16980 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16981 PHYMOD_SYMBOL_FLAG_REGISTER, 16982 "TXFIR_STS1r", 16983 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16984 "TX_FED_TXFIR_STATUS1", 16985 NULL, 16986 #endif 16987 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16988 0x3c, /* 60 */ 16989 0, 16990 #endif 16991 }, 16992 { 16993 BCMI_TSCF_XGXS_TXFIR_STS2r, 16994 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16995 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 16996 BCMI_TSCF_XGXS_TXFIR_STS2r_fields, 16997 #else 16998 0, 16999 #endif 17000 #endif 17001 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17002 PHYMOD_SYMBOL_FLAG_REGISTER, 17003 "TXFIR_STS2r", 17004 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17005 "TX_FED_TXFIR_STATUS2", 17006 NULL, 17007 #endif 17008 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17009 0x2c08, /* 11272 */ 17010 0, 17011 #endif 17012 }, 17013 { 17014 BCMI_TSCF_XGXS_TXFIR_STS3r, 17015 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17016 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 17017 BCMI_TSCF_XGXS_TXFIR_STS3r_fields, 17018 #else 17019 0, 17020 #endif 17021 #endif 17022 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17023 PHYMOD_SYMBOL_FLAG_REGISTER, 17024 "TXFIR_STS3r", 17025 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17026 "TX_FED_TXFIR_STATUS3", 17027 NULL, 17028 #endif 17029 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17030 0x3c, /* 60 */ 17031 0, 17032 #endif 17033 }, 17034 { 17035 BCMI_TSCF_XGXS_TXFIR_STS4r, 17036 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17037 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 17038 BCMI_TSCF_XGXS_TXFIR_STS4r_fields, 17039 #else 17040 0, 17041 #endif 17042 #endif 17043 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17044 PHYMOD_SYMBOL_FLAG_REGISTER, 17045 "TXFIR_STS4r", 17046 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17047 "TX_FED_TXFIR_STATUS4", 17048 NULL, 17049 #endif 17050 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17051 0x8, /* 8 */ 17052 0, 17053 #endif 17054 }, 17055 { 17056 BCMI_TSCF_XGXS_TXFIR_UC_CTL0r, 17057 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17058 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 17059 BCMI_TSCF_XGXS_TXFIR_UC_CTL0r_fields, 17060 #else 17061 0, 17062 #endif 17063 #endif 17064 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17065 PHYMOD_SYMBOL_FLAG_REGISTER, 17066 "TXFIR_UC_CTL0r", 17067 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17068 "TX_FED_TXFIR_MICRO_CONTROL0", 17069 NULL, 17070 #endif 17071 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17072 0x0, /* 0 */ 17073 0, 17074 #endif 17075 }, 17076 { 17077 BCMI_TSCF_XGXS_TXFIR_MISC_CTL1r, 17078 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17079 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 17080 BCMI_TSCF_XGXS_TXFIR_MISC_CTL1r_fields, 17081 #else 17082 0, 17083 #endif 17084 #endif 17085 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17086 PHYMOD_SYMBOL_FLAG_REGISTER, 17087 "TXFIR_MISC_CTL1r", 17088 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17089 "TX_FED_TXFIR_MISC_CONTROL1", 17090 NULL, 17091 #endif 17092 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17093 0x300, /* 768 */ 17094 0, 17095 #endif 17096 }, 17097 { 17098 BCMI_TSCF_XGXS_PLL_CAL_CTL0r, 17099 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17100 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 17101 BCMI_TSCF_XGXS_PLL_CAL_CTL0r_fields, 17102 #else 17103 0, 17104 #endif 17105 #endif 17106 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17107 PHYMOD_SYMBOL_FLAG_REGISTER, 17108 "PLL_CAL_CTL0r", 17109 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17110 "PLL_CAL_COM_CTL_0", 17111 NULL, 17112 #endif 17113 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17114 0xc803, /* 51203 */ 17115 0, 17116 #endif 17117 }, 17118 { 17119 BCMI_TSCF_XGXS_PLL_CAL_CTL1r, 17120 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17121 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 17122 BCMI_TSCF_XGXS_PLL_CAL_CTL1r_fields, 17123 #else 17124 0, 17125 #endif 17126 #endif 17127 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17128 PHYMOD_SYMBOL_FLAG_REGISTER, 17129 "PLL_CAL_CTL1r", 17130 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17131 "PLL_CAL_COM_CTL_1", 17132 NULL, 17133 #endif 17134 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17135 0xc8ff, /* 51455 */ 17136 0, 17137 #endif 17138 }, 17139 { 17140 BCMI_TSCF_XGXS_PLL_CAL_CTL2r, 17141 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17142 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 17143 BCMI_TSCF_XGXS_PLL_CAL_CTL2r_fields, 17144 #else 17145 0, 17146 #endif 17147 #endif 17148 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17149 PHYMOD_SYMBOL_FLAG_REGISTER, 17150 "PLL_CAL_CTL2r", 17151 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17152 "PLL_CAL_COM_CTL_2", 17153 NULL, 17154 #endif 17155 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17156 0xff01, /* 65281 */ 17157 0, 17158 #endif 17159 }, 17160 { 17161 BCMI_TSCF_XGXS_PLL_CAL_CTL3r, 17162 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17163 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 17164 BCMI_TSCF_XGXS_PLL_CAL_CTL3r_fields, 17165 #else 17166 0, 17167 #endif 17168 #endif 17169 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17170 PHYMOD_SYMBOL_FLAG_REGISTER, 17171 "PLL_CAL_CTL3r", 17172 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17173 "PLL_CAL_COM_CTL_3", 17174 NULL, 17175 #endif 17176 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17177 0x0, /* 0 */ 17178 0, 17179 #endif 17180 }, 17181 { 17182 BCMI_TSCF_XGXS_PLL_CAL_CTL4r, 17183 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17184 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 17185 BCMI_TSCF_XGXS_PLL_CAL_CTL4r_fields, 17186 #else 17187 0, 17188 #endif 17189 #endif 17190 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17191 PHYMOD_SYMBOL_FLAG_REGISTER, 17192 "PLL_CAL_CTL4r", 17193 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17194 "PLL_CAL_COM_CTL_4", 17195 NULL, 17196 #endif 17197 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17198 0xa80d, /* 43021 */ 17199 0, 17200 #endif 17201 }, 17202 { 17203 BCMI_TSCF_XGXS_PLL_CAL_CTL5r, 17204 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17205 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 17206 BCMI_TSCF_XGXS_PLL_CAL_CTL5r_fields, 17207 #else 17208 0, 17209 #endif 17210 #endif 17211 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17212 PHYMOD_SYMBOL_FLAG_REGISTER, 17213 "PLL_CAL_CTL5r", 17214 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17215 "PLL_CAL_COM_CTL_5", 17216 NULL, 17217 #endif 17218 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17219 0x27, /* 39 */ 17220 0, 17221 #endif 17222 }, 17223 { 17224 BCMI_TSCF_XGXS_PLL_CAL_CTL6r, 17225 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17226 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 17227 BCMI_TSCF_XGXS_PLL_CAL_CTL6r_fields, 17228 #else 17229 0, 17230 #endif 17231 #endif 17232 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17233 PHYMOD_SYMBOL_FLAG_REGISTER, 17234 "PLL_CAL_CTL6r", 17235 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17236 "PLL_CAL_COM_CTL_6", 17237 NULL, 17238 #endif 17239 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17240 0x7, /* 7 */ 17241 0, 17242 #endif 17243 }, 17244 { 17245 BCMI_TSCF_XGXS_PLL_CAL_CTL7r, 17246 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17247 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 17248 BCMI_TSCF_XGXS_PLL_CAL_CTL7r_fields, 17249 #else 17250 0, 17251 #endif 17252 #endif 17253 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17254 PHYMOD_SYMBOL_FLAG_REGISTER, 17255 "PLL_CAL_CTL7r", 17256 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17257 "PLL_CAL_COM_CTL_7", 17258 NULL, 17259 #endif 17260 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17261 0x7, /* 7 */ 17262 0, 17263 #endif 17264 }, 17265 { 17266 BCMI_TSCF_XGXS_PLL_CAL_CTL_STS0r, 17267 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17268 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 17269 BCMI_TSCF_XGXS_PLL_CAL_CTL_STS0r_fields, 17270 #else 17271 0, 17272 #endif 17273 #endif 17274 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17275 PHYMOD_SYMBOL_FLAG_REGISTER, 17276 "PLL_CAL_CTL_STS0r", 17277 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17278 "PLL_CAL_COM_CTL_STATUS_0", 17279 NULL, 17280 #endif 17281 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17282 0x0, /* 0 */ 17283 0, 17284 #endif 17285 }, 17286 { 17287 BCMI_TSCF_XGXS_PLL_CAL_CTL_STS1r, 17288 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17289 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 17290 BCMI_TSCF_XGXS_PLL_CAL_CTL_STS1r_fields, 17291 #else 17292 0, 17293 #endif 17294 #endif 17295 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17296 PHYMOD_SYMBOL_FLAG_REGISTER, 17297 "PLL_CAL_CTL_STS1r", 17298 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17299 "PLL_CAL_COM_CTL_STATUS_1", 17300 NULL, 17301 #endif 17302 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17303 0x0, /* 0 */ 17304 0, 17305 #endif 17306 }, 17307 { 17308 BCMI_TSCF_XGXS_PLL_CAL_CTL_STS_DBGr, 17309 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17310 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 17311 BCMI_TSCF_XGXS_PLL_CAL_CTL_STS_DBGr_fields, 17312 #else 17313 0, 17314 #endif 17315 #endif 17316 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17317 PHYMOD_SYMBOL_FLAG_REGISTER, 17318 "PLL_CAL_CTL_STS_DBGr", 17319 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17320 "PLL_CAL_COM_CTL_STATUS_DBG", 17321 NULL, 17322 #endif 17323 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17324 0x1, /* 1 */ 17325 0, 17326 #endif 17327 }, 17328 { 17329 BCMI_TSCF_XGXS_TX_CTL0r, 17330 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17331 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 17332 BCMI_TSCF_XGXS_TX_CTL0r_fields, 17333 #else 17334 0, 17335 #endif 17336 #endif 17337 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17338 PHYMOD_SYMBOL_FLAG_REGISTER, 17339 "TX_CTL0r", 17340 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17341 "TX_COM_CONTROL0_REGISTER", 17342 NULL, 17343 #endif 17344 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17345 0x0, /* 0 */ 17346 0, 17347 #endif 17348 }, 17349 { 17350 BCMI_TSCF_XGXS_TX_CTL1r, 17351 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17352 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 17353 BCMI_TSCF_XGXS_TX_CTL1r_fields, 17354 #else 17355 0, 17356 #endif 17357 #endif 17358 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17359 PHYMOD_SYMBOL_FLAG_REGISTER, 17360 "TX_CTL1r", 17361 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17362 "TX_COM_CONTROL1_REGISTER", 17363 NULL, 17364 #endif 17365 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17366 0x70, /* 112 */ 17367 0, 17368 #endif 17369 }, 17370 { 17371 BCMI_TSCF_XGXS_TX_CTL2r, 17372 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17373 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 17374 BCMI_TSCF_XGXS_TX_CTL2r_fields, 17375 #else 17376 0, 17377 #endif 17378 #endif 17379 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17380 PHYMOD_SYMBOL_FLAG_REGISTER, 17381 "TX_CTL2r", 17382 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17383 "TX_COM_CONTROL2_REGISTER", 17384 NULL, 17385 #endif 17386 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17387 0x1f4, /* 500 */ 17388 0, 17389 #endif 17390 }, 17391 { 17392 BCMI_TSCF_XGXS_TX_CTL3r, 17393 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17394 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 17395 BCMI_TSCF_XGXS_TX_CTL3r_fields, 17396 #else 17397 0, 17398 #endif 17399 #endif 17400 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17401 PHYMOD_SYMBOL_FLAG_REGISTER, 17402 "TX_CTL3r", 17403 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17404 "TX_COM_CONTROL3_REGISTER", 17405 NULL, 17406 #endif 17407 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17408 0xc8, /* 200 */ 17409 0, 17410 #endif 17411 }, 17412 { 17413 BCMI_TSCF_XGXS_TLB_RX_PRBS_CHK_CNT_CFGr, 17414 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17415 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 17416 BCMI_TSCF_XGXS_TLB_RX_PRBS_CHK_CNT_CFGr_fields, 17417 #else 17418 0, 17419 #endif 17420 #endif 17421 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17422 PHYMOD_SYMBOL_FLAG_REGISTER, 17423 "TLB_RX_PRBS_CHK_CNT_CFGr", 17424 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17425 "TLB_RX_PRBS_CHK_CNT_CONFIG", 17426 NULL, 17427 #endif 17428 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17429 0x602, /* 1538 */ 17430 0, 17431 #endif 17432 }, 17433 { 17434 BCMI_TSCF_XGXS_TLB_RX_PRBS_CHK_CFGr, 17435 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17436 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 17437 BCMI_TSCF_XGXS_TLB_RX_PRBS_CHK_CFGr_fields, 17438 #else 17439 0, 17440 #endif 17441 #endif 17442 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17443 PHYMOD_SYMBOL_FLAG_REGISTER, 17444 "TLB_RX_PRBS_CHK_CFGr", 17445 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17446 "TLB_RX_PRBS_CHK_CONFIG", 17447 NULL, 17448 #endif 17449 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17450 0x10a, /* 266 */ 17451 0, 17452 #endif 17453 }, 17454 { 17455 BCMI_TSCF_XGXS_TLB_RX_DIG_LPBK_CFGr, 17456 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17457 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 17458 BCMI_TSCF_XGXS_TLB_RX_DIG_LPBK_CFGr_fields, 17459 #else 17460 0, 17461 #endif 17462 #endif 17463 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17464 PHYMOD_SYMBOL_FLAG_REGISTER, 17465 "TLB_RX_DIG_LPBK_CFGr", 17466 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17467 "TLB_RX_DIG_LPBK_CONFIG", 17468 NULL, 17469 #endif 17470 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17471 0xa, /* 10 */ 17472 0, 17473 #endif 17474 }, 17475 { 17476 BCMI_TSCF_XGXS_TLB_RX_MISC_CFGr, 17477 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17478 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 17479 BCMI_TSCF_XGXS_TLB_RX_MISC_CFGr_fields, 17480 #else 17481 0, 17482 #endif 17483 #endif 17484 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17485 PHYMOD_SYMBOL_FLAG_REGISTER, 17486 "TLB_RX_MISC_CFGr", 17487 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17488 "TLB_RX_MISC_CONFIG", 17489 NULL, 17490 #endif 17491 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17492 0x0, /* 0 */ 17493 0, 17494 #endif 17495 }, 17496 { 17497 BCMI_TSCF_XGXS_TLB_RX_PRBS_CHK_EN_TMR_CTLr, 17498 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17499 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 17500 BCMI_TSCF_XGXS_TLB_RX_PRBS_CHK_EN_TMR_CTLr_fields, 17501 #else 17502 0, 17503 #endif 17504 #endif 17505 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17506 PHYMOD_SYMBOL_FLAG_REGISTER, 17507 "TLB_RX_PRBS_CHK_EN_TMR_CTLr", 17508 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17509 "TLB_RX_PRBS_CHK_EN_TIMER_CONTROL", 17510 NULL, 17511 #endif 17512 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17513 0x0, /* 0 */ 17514 0, 17515 #endif 17516 }, 17517 { 17518 BCMI_TSCF_XGXS_TLB_RX_DIG_LPBK_PD_STSr, 17519 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17520 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 17521 BCMI_TSCF_XGXS_TLB_RX_DIG_LPBK_PD_STSr_fields, 17522 #else 17523 0, 17524 #endif 17525 #endif 17526 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17527 PHYMOD_SYMBOL_FLAG_REGISTER, 17528 "TLB_RX_DIG_LPBK_PD_STSr", 17529 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17530 "TLB_RX_DIG_LPBK_PD_STATUS", 17531 NULL, 17532 #endif 17533 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17534 0x2, /* 2 */ 17535 0, 17536 #endif 17537 }, 17538 { 17539 BCMI_TSCF_XGXS_TLB_RX_PRBS_CHK_LOCK_STSr, 17540 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17541 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 17542 BCMI_TSCF_XGXS_TLB_RX_PRBS_CHK_LOCK_STSr_fields, 17543 #else 17544 0, 17545 #endif 17546 #endif 17547 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17548 PHYMOD_SYMBOL_FLAG_REGISTER, 17549 "TLB_RX_PRBS_CHK_LOCK_STSr", 17550 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17551 "TLB_RX_PRBS_CHK_LOCK_STATUS", 17552 NULL, 17553 #endif 17554 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17555 0x0, /* 0 */ 17556 0, 17557 #endif 17558 }, 17559 { 17560 BCMI_TSCF_XGXS_TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr, 17561 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17562 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 17563 BCMI_TSCF_XGXS_TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr_fields, 17564 #else 17565 0, 17566 #endif 17567 #endif 17568 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17569 PHYMOD_SYMBOL_FLAG_REGISTER, 17570 "TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr", 17571 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17572 "TLB_RX_PRBS_CHK_ERR_CNT_MSB_STATUS", 17573 NULL, 17574 #endif 17575 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17576 0x8000, /* 32768 */ 17577 0, 17578 #endif 17579 }, 17580 { 17581 BCMI_TSCF_XGXS_TLB_RX_PRBS_CHK_ERR_CNT_LSB_STSr, 17582 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17583 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 17584 BCMI_TSCF_XGXS_TLB_RX_PRBS_CHK_ERR_CNT_LSB_STSr_fields, 17585 #else 17586 0, 17587 #endif 17588 #endif 17589 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17590 PHYMOD_SYMBOL_FLAG_REGISTER, 17591 "TLB_RX_PRBS_CHK_ERR_CNT_LSB_STSr", 17592 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17593 "TLB_RX_PRBS_CHK_ERR_CNT_LSB_STATUS", 17594 NULL, 17595 #endif 17596 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17597 0x0, /* 0 */ 17598 0, 17599 #endif 17600 }, 17601 { 17602 BCMI_TSCF_XGXS_TLB_RX_PMD_RX_LOCK_STSr, 17603 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17604 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 17605 BCMI_TSCF_XGXS_TLB_RX_PMD_RX_LOCK_STSr_fields, 17606 #else 17607 0, 17608 #endif 17609 #endif 17610 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17611 PHYMOD_SYMBOL_FLAG_REGISTER, 17612 "TLB_RX_PMD_RX_LOCK_STSr", 17613 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17614 "TLB_RX_PMD_RX_LOCK_STATUS", 17615 NULL, 17616 #endif 17617 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17618 0x0, /* 0 */ 17619 0, 17620 #endif 17621 }, 17622 { 17623 BCMI_TSCF_XGXS_TLB_RX_PRBS_BURST_ERR_LEN_STSr, 17624 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17625 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 17626 BCMI_TSCF_XGXS_TLB_RX_PRBS_BURST_ERR_LEN_STSr_fields, 17627 #else 17628 0, 17629 #endif 17630 #endif 17631 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17632 PHYMOD_SYMBOL_FLAG_REGISTER, 17633 "TLB_RX_PRBS_BURST_ERR_LEN_STSr", 17634 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17635 "TLB_RX_PRBS_BURST_ERR_LENGTH_STATUS", 17636 NULL, 17637 #endif 17638 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17639 0x0, /* 0 */ 17640 0, 17641 #endif 17642 }, 17643 { 17644 BCMI_TSCF_XGXS_TLB_RX_MAX_PRBS_BURST_ERR_LEN_STSr, 17645 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17646 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 17647 BCMI_TSCF_XGXS_TLB_RX_MAX_PRBS_BURST_ERR_LEN_STSr_fields, 17648 #else 17649 0, 17650 #endif 17651 #endif 17652 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17653 PHYMOD_SYMBOL_FLAG_REGISTER, 17654 "TLB_RX_MAX_PRBS_BURST_ERR_LEN_STSr", 17655 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17656 "TLB_RX_MAX_PRBS_BURST_ERR_LENGTH_STATUS", 17657 NULL, 17658 #endif 17659 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17660 0x0, /* 0 */ 17661 0, 17662 #endif 17663 }, 17664 { 17665 BCMI_TSCF_XGXS_TLB_TX_PATT_GEN_CFGr, 17666 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17667 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 17668 BCMI_TSCF_XGXS_TLB_TX_PATT_GEN_CFGr_fields, 17669 #else 17670 0, 17671 #endif 17672 #endif 17673 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17674 PHYMOD_SYMBOL_FLAG_REGISTER, 17675 "TLB_TX_PATT_GEN_CFGr", 17676 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17677 "TLB_TX_PATT_GEN_CONFIG", 17678 NULL, 17679 #endif 17680 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17681 0xb000, /* 45056 */ 17682 0, 17683 #endif 17684 }, 17685 { 17686 BCMI_TSCF_XGXS_TLB_TX_PRBS_GEN_CFGr, 17687 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17688 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 17689 BCMI_TSCF_XGXS_TLB_TX_PRBS_GEN_CFGr_fields, 17690 #else 17691 0, 17692 #endif 17693 #endif 17694 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17695 PHYMOD_SYMBOL_FLAG_REGISTER, 17696 "TLB_TX_PRBS_GEN_CFGr", 17697 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17698 "TLB_TX_PRBS_GEN_CONFIG", 17699 NULL, 17700 #endif 17701 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17702 0xa, /* 10 */ 17703 0, 17704 #endif 17705 }, 17706 { 17707 BCMI_TSCF_XGXS_TLB_TX_RMT_LPBK_CFGr, 17708 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17709 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 17710 BCMI_TSCF_XGXS_TLB_TX_RMT_LPBK_CFGr_fields, 17711 #else 17712 0, 17713 #endif 17714 #endif 17715 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17716 PHYMOD_SYMBOL_FLAG_REGISTER, 17717 "TLB_TX_RMT_LPBK_CFGr", 17718 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17719 "TLB_TX_RMT_LPBK_CONFIG", 17720 NULL, 17721 #endif 17722 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17723 0x2, /* 2 */ 17724 0, 17725 #endif 17726 }, 17727 { 17728 BCMI_TSCF_XGXS_TLB_TX_MISC_CFGr, 17729 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17730 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 17731 BCMI_TSCF_XGXS_TLB_TX_MISC_CFGr_fields, 17732 #else 17733 0, 17734 #endif 17735 #endif 17736 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17737 PHYMOD_SYMBOL_FLAG_REGISTER, 17738 "TLB_TX_MISC_CFGr", 17739 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17740 "TLB_TX_MISC_CONFIG", 17741 NULL, 17742 #endif 17743 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17744 0x0, /* 0 */ 17745 0, 17746 #endif 17747 }, 17748 { 17749 BCMI_TSCF_XGXS_TLB_TX_RMT_LPBK_PD_STSr, 17750 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17751 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 17752 BCMI_TSCF_XGXS_TLB_TX_RMT_LPBK_PD_STSr_fields, 17753 #else 17754 0, 17755 #endif 17756 #endif 17757 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17758 PHYMOD_SYMBOL_FLAG_REGISTER, 17759 "TLB_TX_RMT_LPBK_PD_STSr", 17760 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17761 "TLB_TX_RMT_LPBK_PD_STATUS", 17762 NULL, 17763 #endif 17764 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17765 0x2, /* 2 */ 17766 0, 17767 #endif 17768 }, 17769 { 17770 BCMI_TSCF_XGXS_UC_CLK_CTL0r, 17771 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17772 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 17773 BCMI_TSCF_XGXS_UC_CLK_CTL0r_fields, 17774 #else 17775 0, 17776 #endif 17777 #endif 17778 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17779 PHYMOD_SYMBOL_FLAG_REGISTER, 17780 "UC_CLK_CTL0r", 17781 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17782 "MICRO_A_COM_CLOCK_CONTROL0", 17783 NULL, 17784 #endif 17785 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17786 0x0, /* 0 */ 17787 0, 17788 #endif 17789 }, 17790 { 17791 BCMI_TSCF_XGXS_UC_RST_CTL0r, 17792 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17793 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 17794 BCMI_TSCF_XGXS_UC_RST_CTL0r_fields, 17795 #else 17796 0, 17797 #endif 17798 #endif 17799 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17800 PHYMOD_SYMBOL_FLAG_REGISTER, 17801 "UC_RST_CTL0r", 17802 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17803 "MICRO_A_COM_RESET_CONTROL0", 17804 NULL, 17805 #endif 17806 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17807 0x0, /* 0 */ 17808 0, 17809 #endif 17810 }, 17811 { 17812 BCMI_TSCF_XGXS_UC_AHB_CTL0r, 17813 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17814 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 17815 BCMI_TSCF_XGXS_UC_AHB_CTL0r_fields, 17816 #else 17817 0, 17818 #endif 17819 #endif 17820 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17821 PHYMOD_SYMBOL_FLAG_REGISTER, 17822 "UC_AHB_CTL0r", 17823 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17824 "MICRO_A_COM_AHB_CONTROL0", 17825 NULL, 17826 #endif 17827 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17828 0x0, /* 0 */ 17829 0, 17830 #endif 17831 }, 17832 { 17833 BCMI_TSCF_XGXS_UC_AHB_STS0r, 17834 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17835 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 17836 BCMI_TSCF_XGXS_UC_AHB_STS0r_fields, 17837 #else 17838 0, 17839 #endif 17840 #endif 17841 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17842 PHYMOD_SYMBOL_FLAG_REGISTER, 17843 "UC_AHB_STS0r", 17844 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17845 "MICRO_A_COM_AHB_STATUS0", 17846 NULL, 17847 #endif 17848 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17849 0x0, /* 0 */ 17850 0, 17851 #endif 17852 }, 17853 { 17854 BCMI_TSCF_XGXS_UC_AHB_WRADDR_LSWr, 17855 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17856 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 17857 BCMI_TSCF_XGXS_UC_AHB_WRADDR_LSWr_fields, 17858 #else 17859 0, 17860 #endif 17861 #endif 17862 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17863 PHYMOD_SYMBOL_FLAG_REGISTER, 17864 "UC_AHB_WRADDR_LSWr", 17865 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17866 "MICRO_A_COM_AHB_WRADDR_LSW", 17867 NULL, 17868 #endif 17869 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17870 0x0, /* 0 */ 17871 0, 17872 #endif 17873 }, 17874 { 17875 BCMI_TSCF_XGXS_UC_AHB_WRADDR_MSWr, 17876 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17877 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 17878 BCMI_TSCF_XGXS_UC_AHB_WRADDR_MSWr_fields, 17879 #else 17880 0, 17881 #endif 17882 #endif 17883 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17884 PHYMOD_SYMBOL_FLAG_REGISTER, 17885 "UC_AHB_WRADDR_MSWr", 17886 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17887 "MICRO_A_COM_AHB_WRADDR_MSW", 17888 NULL, 17889 #endif 17890 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17891 0x0, /* 0 */ 17892 0, 17893 #endif 17894 }, 17895 { 17896 BCMI_TSCF_XGXS_UC_AHB_WRDATA_LSWr, 17897 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17898 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 17899 BCMI_TSCF_XGXS_UC_AHB_WRDATA_LSWr_fields, 17900 #else 17901 0, 17902 #endif 17903 #endif 17904 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17905 PHYMOD_SYMBOL_FLAG_REGISTER, 17906 "UC_AHB_WRDATA_LSWr", 17907 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17908 "MICRO_A_COM_AHB_WRDATA_LSW", 17909 NULL, 17910 #endif 17911 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17912 0x0, /* 0 */ 17913 0, 17914 #endif 17915 }, 17916 { 17917 BCMI_TSCF_XGXS_UC_AHB_WRDATA_MSWr, 17918 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17919 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 17920 BCMI_TSCF_XGXS_UC_AHB_WRDATA_MSWr_fields, 17921 #else 17922 0, 17923 #endif 17924 #endif 17925 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17926 PHYMOD_SYMBOL_FLAG_REGISTER, 17927 "UC_AHB_WRDATA_MSWr", 17928 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17929 "MICRO_A_COM_AHB_WRDATA_MSW", 17930 NULL, 17931 #endif 17932 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17933 0x0, /* 0 */ 17934 0, 17935 #endif 17936 }, 17937 { 17938 BCMI_TSCF_XGXS_UC_AHB_RDADDR_LSWr, 17939 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17940 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 17941 BCMI_TSCF_XGXS_UC_AHB_RDADDR_LSWr_fields, 17942 #else 17943 0, 17944 #endif 17945 #endif 17946 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17947 PHYMOD_SYMBOL_FLAG_REGISTER, 17948 "UC_AHB_RDADDR_LSWr", 17949 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17950 "MICRO_A_COM_AHB_RDADDR_LSW", 17951 NULL, 17952 #endif 17953 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17954 0x0, /* 0 */ 17955 0, 17956 #endif 17957 }, 17958 { 17959 BCMI_TSCF_XGXS_UC_AHB_RDADDR_MSWr, 17960 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17961 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 17962 BCMI_TSCF_XGXS_UC_AHB_RDADDR_MSWr_fields, 17963 #else 17964 0, 17965 #endif 17966 #endif 17967 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17968 PHYMOD_SYMBOL_FLAG_REGISTER, 17969 "UC_AHB_RDADDR_MSWr", 17970 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17971 "MICRO_A_COM_AHB_RDADDR_MSW", 17972 NULL, 17973 #endif 17974 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17975 0x0, /* 0 */ 17976 0, 17977 #endif 17978 }, 17979 { 17980 BCMI_TSCF_XGXS_UC_AHB_RDDATA_LSWr, 17981 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17982 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 17983 BCMI_TSCF_XGXS_UC_AHB_RDDATA_LSWr_fields, 17984 #else 17985 0, 17986 #endif 17987 #endif 17988 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17989 PHYMOD_SYMBOL_FLAG_REGISTER, 17990 "UC_AHB_RDDATA_LSWr", 17991 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17992 "MICRO_A_COM_AHB_RDDATA_LSW", 17993 NULL, 17994 #endif 17995 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17996 0x0, /* 0 */ 17997 0, 17998 #endif 17999 }, 18000 { 18001 BCMI_TSCF_XGXS_UC_AHB_RDDATA_MSWr, 18002 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18003 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 18004 BCMI_TSCF_XGXS_UC_AHB_RDDATA_MSWr_fields, 18005 #else 18006 0, 18007 #endif 18008 #endif 18009 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18010 PHYMOD_SYMBOL_FLAG_REGISTER, 18011 "UC_AHB_RDDATA_MSWr", 18012 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18013 "MICRO_A_COM_AHB_RDDATA_MSW", 18014 NULL, 18015 #endif 18016 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18017 0x0, /* 0 */ 18018 0, 18019 #endif 18020 }, 18021 { 18022 BCMI_TSCF_XGXS_UC_PRAMIF_CTL0r, 18023 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18024 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 18025 BCMI_TSCF_XGXS_UC_PRAMIF_CTL0r_fields, 18026 #else 18027 0, 18028 #endif 18029 #endif 18030 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18031 PHYMOD_SYMBOL_FLAG_REGISTER, 18032 "UC_PRAMIF_CTL0r", 18033 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18034 "MICRO_A_COM_PRAMIF_CONTROL0", 18035 NULL, 18036 #endif 18037 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18038 0x0, /* 0 */ 18039 0, 18040 #endif 18041 }, 18042 { 18043 BCMI_TSCF_XGXS_UC_PRAMIF_AHB_WRADDR_LSWr, 18044 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18045 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 18046 BCMI_TSCF_XGXS_UC_PRAMIF_AHB_WRADDR_LSWr_fields, 18047 #else 18048 0, 18049 #endif 18050 #endif 18051 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18052 PHYMOD_SYMBOL_FLAG_REGISTER, 18053 "UC_PRAMIF_AHB_WRADDR_LSWr", 18054 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18055 "MICRO_A_COM_PRAMIF_AHB_WRADDR_LSW", 18056 NULL, 18057 #endif 18058 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18059 0x0, /* 0 */ 18060 0, 18061 #endif 18062 }, 18063 { 18064 BCMI_TSCF_XGXS_UC_PRAMIF_AHB_WRADDR_MSWr, 18065 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18066 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 18067 BCMI_TSCF_XGXS_UC_PRAMIF_AHB_WRADDR_MSWr_fields, 18068 #else 18069 0, 18070 #endif 18071 #endif 18072 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18073 PHYMOD_SYMBOL_FLAG_REGISTER, 18074 "UC_PRAMIF_AHB_WRADDR_MSWr", 18075 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18076 "MICRO_A_COM_PRAMIF_AHB_WRADDR_MSW", 18077 NULL, 18078 #endif 18079 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18080 0x0, /* 0 */ 18081 0, 18082 #endif 18083 }, 18084 { 18085 BCMI_TSCF_XGXS_UC_PVT_STS0r, 18086 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18087 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 18088 BCMI_TSCF_XGXS_UC_PVT_STS0r_fields, 18089 #else 18090 0, 18091 #endif 18092 #endif 18093 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18094 PHYMOD_SYMBOL_FLAG_REGISTER, 18095 "UC_PVT_STS0r", 18096 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18097 "MICRO_B_COM_PVT_STATUS0", 18098 NULL, 18099 #endif 18100 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18101 0x0, /* 0 */ 18102 0, 18103 #endif 18104 }, 18105 { 18106 BCMI_TSCF_XGXS_UC_RMI_TO_UC_MBOX0r, 18107 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18108 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 18109 BCMI_TSCF_XGXS_UC_RMI_TO_UC_MBOX0r_fields, 18110 #else 18111 0, 18112 #endif 18113 #endif 18114 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18115 PHYMOD_SYMBOL_FLAG_REGISTER, 18116 "UC_RMI_TO_UC_MBOX0r", 18117 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18118 "MICRO_B_COM_RMI_TO_MICRO_MBOX0", 18119 NULL, 18120 #endif 18121 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18122 0x0, /* 0 */ 18123 0, 18124 #endif 18125 }, 18126 { 18127 BCMI_TSCF_XGXS_UC_RMI_TO_UC_MBOX1r, 18128 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18129 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 18130 BCMI_TSCF_XGXS_UC_RMI_TO_UC_MBOX1r_fields, 18131 #else 18132 0, 18133 #endif 18134 #endif 18135 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18136 PHYMOD_SYMBOL_FLAG_REGISTER, 18137 "UC_RMI_TO_UC_MBOX1r", 18138 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18139 "MICRO_B_COM_RMI_TO_MICRO_MBOX1", 18140 NULL, 18141 #endif 18142 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18143 0x0, /* 0 */ 18144 0, 18145 #endif 18146 }, 18147 { 18148 BCMI_TSCF_XGXS_UC_UC_TO_RMI_MBOX0r, 18149 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18150 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 18151 BCMI_TSCF_XGXS_UC_UC_TO_RMI_MBOX0r_fields, 18152 #else 18153 0, 18154 #endif 18155 #endif 18156 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18157 PHYMOD_SYMBOL_FLAG_REGISTER, 18158 "UC_UC_TO_RMI_MBOX0r", 18159 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18160 "MICRO_B_COM_MICRO_TO_RMI_MBOX0", 18161 NULL, 18162 #endif 18163 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18164 0x0, /* 0 */ 18165 0, 18166 #endif 18167 }, 18168 { 18169 BCMI_TSCF_XGXS_UC_UC_TO_RMI_MBOX1r, 18170 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18171 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 18172 BCMI_TSCF_XGXS_UC_UC_TO_RMI_MBOX1r_fields, 18173 #else 18174 0, 18175 #endif 18176 #endif 18177 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18178 PHYMOD_SYMBOL_FLAG_REGISTER, 18179 "UC_UC_TO_RMI_MBOX1r", 18180 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18181 "MICRO_B_COM_MICRO_TO_RMI_MBOX1", 18182 NULL, 18183 #endif 18184 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18185 0x0, /* 0 */ 18186 0, 18187 #endif 18188 }, 18189 { 18190 BCMI_TSCF_XGXS_UC_RMI_MBOX_CTL0r, 18191 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18192 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 18193 BCMI_TSCF_XGXS_UC_RMI_MBOX_CTL0r_fields, 18194 #else 18195 0, 18196 #endif 18197 #endif 18198 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18199 PHYMOD_SYMBOL_FLAG_REGISTER, 18200 "UC_RMI_MBOX_CTL0r", 18201 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18202 "MICRO_B_COM_RMI_MBOX_CONTROL0", 18203 NULL, 18204 #endif 18205 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18206 0x0, /* 0 */ 18207 0, 18208 #endif 18209 }, 18210 { 18211 BCMI_TSCF_XGXS_UC_RMI_AHB_CTL1r, 18212 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18213 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 18214 BCMI_TSCF_XGXS_UC_RMI_AHB_CTL1r_fields, 18215 #else 18216 0, 18217 #endif 18218 #endif 18219 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18220 PHYMOD_SYMBOL_FLAG_REGISTER, 18221 "UC_RMI_AHB_CTL1r", 18222 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18223 "MICRO_B_COM_RMI_AHB_CONTROL1", 18224 NULL, 18225 #endif 18226 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18227 0x7, /* 7 */ 18228 0, 18229 #endif 18230 }, 18231 { 18232 BCMI_TSCF_XGXS_UC_RMI_AHB_STS1r, 18233 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18234 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 18235 BCMI_TSCF_XGXS_UC_RMI_AHB_STS1r_fields, 18236 #else 18237 0, 18238 #endif 18239 #endif 18240 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18241 PHYMOD_SYMBOL_FLAG_REGISTER, 18242 "UC_RMI_AHB_STS1r", 18243 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18244 "MICRO_B_COM_RMI_AHB_STATUS1", 18245 NULL, 18246 #endif 18247 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18248 0x0, /* 0 */ 18249 0, 18250 #endif 18251 }, 18252 { 18253 BCMI_TSCF_XGXS_UC_RMI_RA_AINC_NXT_WRADDR_LSWr, 18254 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18255 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 18256 BCMI_TSCF_XGXS_UC_RMI_RA_AINC_NXT_WRADDR_LSWr_fields, 18257 #else 18258 0, 18259 #endif 18260 #endif 18261 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18262 PHYMOD_SYMBOL_FLAG_REGISTER, 18263 "UC_RMI_RA_AINC_NXT_WRADDR_LSWr", 18264 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18265 "MICRO_B_COM_RMI_RA_AUTOINC_NXT_WRADDR_LSW", 18266 NULL, 18267 #endif 18268 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18269 0x0, /* 0 */ 18270 0, 18271 #endif 18272 }, 18273 { 18274 BCMI_TSCF_XGXS_UC_RMI_RA_AINC_NXT_RDADDR_LSWr, 18275 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18276 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 18277 BCMI_TSCF_XGXS_UC_RMI_RA_AINC_NXT_RDADDR_LSWr_fields, 18278 #else 18279 0, 18280 #endif 18281 #endif 18282 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18283 PHYMOD_SYMBOL_FLAG_REGISTER, 18284 "UC_RMI_RA_AINC_NXT_RDADDR_LSWr", 18285 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18286 "MICRO_B_COM_RMI_RA_AUTOINC_NXT_RDADDR_LSW", 18287 NULL, 18288 #endif 18289 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18290 0x0, /* 0 */ 18291 0, 18292 #endif 18293 }, 18294 { 18295 BCMI_TSCF_XGXS_UC_RMI_PR_AINC_NXT_WRADDR_LSWr, 18296 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18297 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 18298 BCMI_TSCF_XGXS_UC_RMI_PR_AINC_NXT_WRADDR_LSWr_fields, 18299 #else 18300 0, 18301 #endif 18302 #endif 18303 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18304 PHYMOD_SYMBOL_FLAG_REGISTER, 18305 "UC_RMI_PR_AINC_NXT_WRADDR_LSWr", 18306 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18307 "MICRO_B_COM_RMI_PR_AUTOINC_NXT_WRADDR_LSW", 18308 NULL, 18309 #endif 18310 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18311 0x0, /* 0 */ 18312 0, 18313 #endif 18314 }, 18315 { 18316 BCMI_TSCF_XGXS_UC_RMI_PVT_CTL0r, 18317 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18318 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 18319 BCMI_TSCF_XGXS_UC_RMI_PVT_CTL0r_fields, 18320 #else 18321 0, 18322 #endif 18323 #endif 18324 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18325 PHYMOD_SYMBOL_FLAG_REGISTER, 18326 "UC_RMI_PVT_CTL0r", 18327 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18328 "MICRO_B_COM_RMI_PVT_CONTROL0", 18329 NULL, 18330 #endif 18331 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18332 0x0, /* 0 */ 18333 0, 18334 #endif 18335 }, 18336 { 18337 BCMI_TSCF_XGXS_UC_CODE_RAM_ECCCTL0r, 18338 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18339 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 18340 BCMI_TSCF_XGXS_UC_CODE_RAM_ECCCTL0r_fields, 18341 #else 18342 0, 18343 #endif 18344 #endif 18345 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18346 PHYMOD_SYMBOL_FLAG_REGISTER, 18347 "UC_CODE_RAM_ECCCTL0r", 18348 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18349 "MICRO_C_COM_CODE_RAM_ECCCONTROL0", 18350 NULL, 18351 #endif 18352 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18353 0x0, /* 0 */ 18354 0, 18355 #endif 18356 }, 18357 { 18358 BCMI_TSCF_XGXS_UC_CODE_RAM_ECCCONTRO1r, 18359 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18360 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 18361 BCMI_TSCF_XGXS_UC_CODE_RAM_ECCCONTRO1r_fields, 18362 #else 18363 0, 18364 #endif 18365 #endif 18366 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18367 PHYMOD_SYMBOL_FLAG_REGISTER, 18368 "UC_CODE_RAM_ECCCONTRO1r", 18369 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18370 "MICRO_C_COM_CODE_RAM_ECCCONTRO1", 18371 NULL, 18372 #endif 18373 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18374 0x0, /* 0 */ 18375 0, 18376 #endif 18377 }, 18378 { 18379 BCMI_TSCF_XGXS_UC_CODE_RAM_ECCSTS0r, 18380 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18381 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 18382 BCMI_TSCF_XGXS_UC_CODE_RAM_ECCSTS0r_fields, 18383 #else 18384 0, 18385 #endif 18386 #endif 18387 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18388 PHYMOD_SYMBOL_FLAG_REGISTER, 18389 "UC_CODE_RAM_ECCSTS0r", 18390 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18391 "MICRO_C_COM_CODE_RAM_ECCSTATUS0", 18392 NULL, 18393 #endif 18394 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18395 0x0, /* 0 */ 18396 0, 18397 #endif 18398 }, 18399 { 18400 BCMI_TSCF_XGXS_UC_CODE_RAM_ECCSTS1r, 18401 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18402 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 18403 BCMI_TSCF_XGXS_UC_CODE_RAM_ECCSTS1r_fields, 18404 #else 18405 0, 18406 #endif 18407 #endif 18408 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18409 PHYMOD_SYMBOL_FLAG_REGISTER, 18410 "UC_CODE_RAM_ECCSTS1r", 18411 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18412 "MICRO_C_COM_CODE_RAM_ECCSTATUS1", 18413 NULL, 18414 #endif 18415 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18416 0x0, /* 0 */ 18417 0, 18418 #endif 18419 }, 18420 { 18421 BCMI_TSCF_XGXS_UC_CODE_RAM_TESTIFCTL0r, 18422 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18423 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 18424 BCMI_TSCF_XGXS_UC_CODE_RAM_TESTIFCTL0r_fields, 18425 #else 18426 0, 18427 #endif 18428 #endif 18429 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18430 PHYMOD_SYMBOL_FLAG_REGISTER, 18431 "UC_CODE_RAM_TESTIFCTL0r", 18432 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18433 "MICRO_C_COM_CODE_RAM_TESTIFCONTROL0", 18434 NULL, 18435 #endif 18436 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18437 0x0, /* 0 */ 18438 0, 18439 #endif 18440 }, 18441 { 18442 BCMI_TSCF_XGXS_UC_RAM_CTL0r, 18443 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18444 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 18445 BCMI_TSCF_XGXS_UC_RAM_CTL0r_fields, 18446 #else 18447 0, 18448 #endif 18449 #endif 18450 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18451 PHYMOD_SYMBOL_FLAG_REGISTER, 18452 "UC_RAM_CTL0r", 18453 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18454 "MICRO_C_COM_RAM_CONTROL0", 18455 NULL, 18456 #endif 18457 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18458 0x401, /* 1025 */ 18459 0, 18460 #endif 18461 }, 18462 { 18463 BCMI_TSCF_XGXS_UC_RMI_EXT_INTR_CTL0r, 18464 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18465 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 18466 BCMI_TSCF_XGXS_UC_RMI_EXT_INTR_CTL0r_fields, 18467 #else 18468 0, 18469 #endif 18470 #endif 18471 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18472 PHYMOD_SYMBOL_FLAG_REGISTER, 18473 "UC_RMI_EXT_INTR_CTL0r", 18474 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18475 "MICRO_C_COM_RMI_EXT_INTR_CONTROL0", 18476 NULL, 18477 #endif 18478 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18479 0x0, /* 0 */ 18480 0, 18481 #endif 18482 }, 18483 { 18484 BCMI_TSCF_XGXS_UC_RMI_EXT_INTR_STS0r, 18485 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18486 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 18487 BCMI_TSCF_XGXS_UC_RMI_EXT_INTR_STS0r_fields, 18488 #else 18489 0, 18490 #endif 18491 #endif 18492 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18493 PHYMOD_SYMBOL_FLAG_REGISTER, 18494 "UC_RMI_EXT_INTR_STS0r", 18495 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18496 "MICRO_C_COM_RMI_EXT_INTR_STATUS0", 18497 NULL, 18498 #endif 18499 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18500 0x0, /* 0 */ 18501 0, 18502 #endif 18503 }, 18504 { 18505 BCMI_TSCF_XGXS_MDIO_MASKDATAr, 18506 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18507 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 18508 BCMI_TSCF_XGXS_MDIO_MASKDATAr_fields, 18509 #else 18510 0, 18511 #endif 18512 #endif 18513 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18514 PHYMOD_SYMBOL_FLAG_REGISTER, 18515 "MDIO_MASKDATAr", 18516 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18517 "MDIO_MMDSEL_AER_COM_MDIO_MASKDATA", 18518 NULL, 18519 #endif 18520 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18521 0x0, /* 0 */ 18522 0, 18523 #endif 18524 }, 18525 { 18526 BCMI_TSCF_XGXS_MDIO_BCST_PORT_ADDRr, 18527 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18528 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 18529 BCMI_TSCF_XGXS_MDIO_BCST_PORT_ADDRr_fields, 18530 #else 18531 0, 18532 #endif 18533 #endif 18534 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18535 PHYMOD_SYMBOL_FLAG_REGISTER, 18536 "MDIO_BCST_PORT_ADDRr", 18537 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18538 "MDIO_MMDSEL_AER_COM_MDIO_BRCST_PORT_ADDR", 18539 NULL, 18540 #endif 18541 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18542 0x1f, /* 31 */ 18543 0, 18544 #endif 18545 }, 18546 { 18547 BCMI_TSCF_XGXS_MDIO_MMD_SELr, 18548 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18549 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 18550 BCMI_TSCF_XGXS_MDIO_MMD_SELr_fields, 18551 #else 18552 0, 18553 #endif 18554 #endif 18555 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18556 PHYMOD_SYMBOL_FLAG_REGISTER, 18557 "MDIO_MMD_SELr", 18558 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18559 "MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT", 18560 NULL, 18561 #endif 18562 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18563 0x404d, /* 16461 */ 18564 0, 18565 #endif 18566 }, 18567 { 18568 BCMI_TSCF_XGXS_MDIO_AERr, 18569 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18570 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 18571 BCMI_TSCF_XGXS_MDIO_AERr_fields, 18572 #else 18573 0, 18574 #endif 18575 #endif 18576 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18577 PHYMOD_SYMBOL_FLAG_REGISTER, 18578 "MDIO_AERr", 18579 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18580 "MDIO_MMDSEL_AER_COM_MDIO_AER", 18581 NULL, 18582 #endif 18583 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18584 0x0, /* 0 */ 18585 0, 18586 #endif 18587 }, 18588 { 18589 BCMI_TSCF_XGXS_MDIO_BLK_ADDRr, 18590 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18591 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS 18592 BCMI_TSCF_XGXS_MDIO_BLK_ADDRr_fields, 18593 #else 18594 0, 18595 #endif 18596 #endif 18597 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18598 PHYMOD_SYMBOL_FLAG_REGISTER, 18599 "MDIO_BLK_ADDRr", 18600 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18601 "MDIO_BLK_ADDR_COM_BLK_ADDR", 18602 NULL, 18603 #endif 18604 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18605 0x0, /* 0 */ 18606 0, 18607 #endif 18608 }, 18609 #endif 18610 }; 18611 18612 18613 phymod_symbols_t bcmi_tscf_xgxs_symbols = 18614 { 18615 bcmi_tscf_xgxs_syms, sizeof(bcmi_tscf_xgxs_syms)/sizeof(bcmi_tscf_xgxs_syms[0]), 18616 #if PHYMOD_CONFIG_INCLUDE_FIELD_NAMES == 1 18617 bcmi_tscf_xgxs_fields 18618 #else 18619 NULL 18620 #endif 18621 /* END OF SYMBOL FILE */ 18622 }; 18623 18624 #endif /* PHYMOD_CONFIG_INCLUDE_CHIP_SYMBOLS */