bcmi_tsce_xgxs_sym.c (454555B)
1 /******************************************************************************* 2 * 3 * 4 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 5 * 6 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 7 * 8 * DO NOT EDIT THIS FILE! 9 * This file is auto-generated from the registers file. 10 * Edits to this file will be lost when it is regenerated. 11 * 12 * Symbol table file for the BCMI_TSCE_XGXS. 13 * This symbol table is used by the Broadcom debug shell. 14 */ 15 16 17 #include <phymod/chip/bcmi_tsce_xgxs_defs.h> 18 #include <phymod/phymod_symbols.h> 19 20 /* No symbols will be compiled unless this is defined. */ 21 #if PHYMOD_CONFIG_INCLUDE_CHIP_SYMBOLS == 1 22 /******************************************************************************* 23 * 24 * If PHYMOD_CONFIG_INCLUDE_FIELD_INFO is 1, then symbol information 25 * necessary to encode and decode the individual fields of a register or memory 26 * will be available. 27 * 28 * Without it, only the register and memory names will be symbolically available 29 * and their values will be displayed as raw data only. 30 * 31 * Field information can be compiled out in the interest of saving code space. 32 */ 33 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 34 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 35 36 static uint32_t BCMI_TSCE_XGXS_ACC_ADDR_DATAr_fields[] = 37 { 38 /* MDIO_ADDR_DATA:0:15 */ 39 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(875, 15, 0) 40 }; 41 static uint32_t BCMI_TSCE_XGXS_ACC_CTLr_fields[] = 42 { 43 /* MDIO_DEVAD:0:4 */ 44 PHYMOD_SYMBOL_FIELD_ENCODE(879, 4, 0), 45 /* MDIO_FUNCTION:14:15 */ 46 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(886, 15, 14) 47 }; 48 static uint32_t BCMI_TSCE_XGXS_AMS_CTL0r_fields[] = 49 { 50 /* AMS_PLL_LOWPWR_6G:0:0 */ 51 PHYMOD_SYMBOL_FIELD_ENCODE(75, 0, 0), 52 /* AMS_PLL_TXCG_VDDR_BGB:1:1 */ 53 PHYMOD_SYMBOL_FIELD_ENCODE(95, 1, 1), 54 /* AMS_PLL_IMIN_ICLKINT:2:2 */ 55 PHYMOD_SYMBOL_FIELD_ENCODE(57, 2, 2), 56 /* AMS_PLL_IMAX_ICLKINT:3:3 */ 57 PHYMOD_SYMBOL_FIELD_ENCODE(47, 3, 3), 58 /* AMS_PLL_IMODE_ICLKINT:4:4 */ 59 PHYMOD_SYMBOL_FIELD_ENCODE(67, 4, 4), 60 /* AMS_PLL_IMIN_ICKGEN:5:5 */ 61 PHYMOD_SYMBOL_FIELD_ENCODE(55, 5, 5), 62 /* AMS_PLL_IMAX_ICKGEN:6:6 */ 63 PHYMOD_SYMBOL_FIELD_ENCODE(45, 6, 6), 64 /* AMS_PLL_IMODE_ICKGEN:7:7 */ 65 PHYMOD_SYMBOL_FIELD_ENCODE(65, 7, 7), 66 /* AMS_PLL_IMIN_ICLKIDRV1:8:8 */ 67 PHYMOD_SYMBOL_FIELD_ENCODE(56, 8, 8), 68 /* AMS_PLL_IMAX_ICLKIDRV1:9:9 */ 69 PHYMOD_SYMBOL_FIELD_ENCODE(46, 9, 9), 70 /* AMS_PLL_IMODE_ICLKIDRV1:10:10 */ 71 PHYMOD_SYMBOL_FIELD_ENCODE(66, 10, 10), 72 /* AMS_PLL_CAL_OFF:11:11 */ 73 PHYMOD_SYMBOL_FIELD_ENCODE(26, 11, 11), 74 /* AMS_PLL_CAL_AUX:12:15 */ 75 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(25, 15, 12) 76 }; 77 static uint32_t BCMI_TSCE_XGXS_AMS_CTL1r_fields[] = 78 { 79 /* AMS_PLL_DBLR_CTRL:0:1 */ 80 PHYMOD_SYMBOL_FIELD_ENCODE(28, 1, 0), 81 /* AMS_PLL_SPARE_18:2:2 */ 82 PHYMOD_SYMBOL_FIELD_ENCODE(87, 2, 2), 83 /* AMS_PLL_FP3_RH:3:3 */ 84 PHYMOD_SYMBOL_FIELD_ENCODE(35, 3, 3), 85 /* AMS_PLL_FP3_CTRL:4:5 */ 86 PHYMOD_SYMBOL_FIELD_ENCODE(34, 5, 4), 87 /* AMS_PLL_VCO_DIV2:6:6 */ 88 PHYMOD_SYMBOL_FIELD_ENCODE(99, 6, 6), 89 /* AMS_PLL_VCO_DIV4:7:7 */ 90 PHYMOD_SYMBOL_FIELD_ENCODE(100, 7, 7), 91 /* AMS_PLL_VCOICTRL:8:9 */ 92 PHYMOD_SYMBOL_FIELD_ENCODE(98, 9, 8), 93 /* AMS_PLL_VCO_IMAX:10:10 */ 94 PHYMOD_SYMBOL_FIELD_ENCODE(101, 10, 10), 95 /* AMS_PLL_IVCO:11:13 */ 96 PHYMOD_SYMBOL_FIELD_ENCODE(73, 13, 11), 97 /* AMS_PLL_RESET:14:14 */ 98 PHYMOD_SYMBOL_FIELD_ENCODE(85, 14, 14), 99 /* AMS_PLL_ENABLE_FTUNE:15:15 */ 100 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(30, 15, 15) 101 }; 102 static uint32_t BCMI_TSCE_XGXS_AMS_CTL2r_fields[] = 103 { 104 /* AMS_PLL_EN_HRZ:0:0 */ 105 PHYMOD_SYMBOL_FIELD_ENCODE(31, 0, 0), 106 /* AMS_PLL_IQP:1:4 */ 107 PHYMOD_SYMBOL_FIELD_ENCODE(72, 4, 1), 108 /* AMS_PLL_REFL_PLL:5:5 */ 109 PHYMOD_SYMBOL_FIELD_ENCODE(84, 5, 5), 110 /* AMS_PLL_REFH_PLL:6:6 */ 111 PHYMOD_SYMBOL_FIELD_ENCODE(83, 6, 6), 112 /* AMS_PLL_IMIN_IBIAS:7:7 */ 113 PHYMOD_SYMBOL_FIELD_ENCODE(53, 7, 7), 114 /* AMS_PLL_IMODE_IBIAS:8:8 */ 115 PHYMOD_SYMBOL_FIELD_ENCODE(63, 8, 8), 116 /* AMS_PLL_IMAX_IBIAS:9:9 */ 117 PHYMOD_SYMBOL_FIELD_ENCODE(43, 9, 9), 118 /* AMS_PLL_IMIN_ICP:10:10 */ 119 PHYMOD_SYMBOL_FIELD_ENCODE(60, 10, 10), 120 /* AMS_PLL_IMODE_ICP:11:11 */ 121 PHYMOD_SYMBOL_FIELD_ENCODE(70, 11, 11), 122 /* AMS_PLL_IMAX_ICP:12:12 */ 123 PHYMOD_SYMBOL_FIELD_ENCODE(50, 12, 12), 124 /* AMS_PLL_IMIN_ICK:13:13 */ 125 PHYMOD_SYMBOL_FIELD_ENCODE(54, 13, 13), 126 /* AMS_PLL_IMODE_ICK:14:14 */ 127 PHYMOD_SYMBOL_FIELD_ENCODE(64, 14, 14), 128 /* AMS_PLL_IMAX_ICK:15:15 */ 129 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(44, 15, 15) 130 }; 131 static uint32_t BCMI_TSCE_XGXS_AMS_CTL3r_fields[] = 132 { 133 /* AMS_PLL_IMIN_I10GBUF:0:0 */ 134 PHYMOD_SYMBOL_FIELD_ENCODE(52, 0, 0), 135 /* AMS_PLL_IMODE_I10GBUF:1:1 */ 136 PHYMOD_SYMBOL_FIELD_ENCODE(62, 1, 1), 137 /* AMS_PLL_IMAX_I10GBUF:2:2 */ 138 PHYMOD_SYMBOL_FIELD_ENCODE(42, 2, 2), 139 /* AMS_PLL_IMIN_ICML:3:3 */ 140 PHYMOD_SYMBOL_FIELD_ENCODE(58, 3, 3), 141 /* AMS_PLL_IMODE_ICML:4:4 */ 142 PHYMOD_SYMBOL_FIELD_ENCODE(68, 4, 4), 143 /* AMS_PLL_IMAX_ICML:5:5 */ 144 PHYMOD_SYMBOL_FIELD_ENCODE(48, 5, 5), 145 /* AMS_PLL_IMIN_ICOMP:6:6 */ 146 PHYMOD_SYMBOL_FIELD_ENCODE(59, 6, 6), 147 /* AMS_PLL_IMODE_ICOMP:7:7 */ 148 PHYMOD_SYMBOL_FIELD_ENCODE(69, 7, 7), 149 /* AMS_PLL_IMAX_ICOMP:8:8 */ 150 PHYMOD_SYMBOL_FIELD_ENCODE(49, 8, 8), 151 /* AMS_PLL_IMIN_IOP:9:9 */ 152 PHYMOD_SYMBOL_FIELD_ENCODE(61, 9, 9), 153 /* AMS_PLL_IMODE_IOP:10:10 */ 154 PHYMOD_SYMBOL_FIELD_ENCODE(71, 10, 10), 155 /* AMS_PLL_IMAX_IOP:11:11 */ 156 PHYMOD_SYMBOL_FIELD_ENCODE(51, 11, 11), 157 /* AMS_PLL_TEST_VREF:12:12 */ 158 PHYMOD_SYMBOL_FIELD_ENCODE(94, 12, 12), 159 /* AMS_PLL_TEST_VC:13:13 */ 160 PHYMOD_SYMBOL_FIELD_ENCODE(93, 13, 13), 161 /* AMS_PLL_TEST_PLL:14:14 */ 162 PHYMOD_SYMBOL_FIELD_ENCODE(90, 14, 14), 163 /* AMS_PLL_TEST_RX:15:15 */ 164 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(92, 15, 15) 165 }; 166 static uint32_t BCMI_TSCE_XGXS_AMS_CTL4r_fields[] = 167 { 168 /* AMS_PLL_BGR_PTATADJ:0:3 */ 169 PHYMOD_SYMBOL_FIELD_ENCODE(24, 3, 0), 170 /* AMS_PLL_BGR_CTATADJ:4:7 */ 171 PHYMOD_SYMBOL_FIELD_ENCODE(23, 7, 4), 172 /* AMS_PLL_2RX_CLKBW:8:9 */ 173 PHYMOD_SYMBOL_FIELD_ENCODE(18, 9, 8), 174 /* AMS_PLL_COMP_VTH:10:10 */ 175 PHYMOD_SYMBOL_FIELD_ENCODE(27, 10, 10), 176 /* AMS_PLL_VDDR_BGB:11:11 */ 177 PHYMOD_SYMBOL_FIELD_ENCODE(102, 11, 11), 178 /* AMS_PLL_KVH_FORCE:12:13 */ 179 PHYMOD_SYMBOL_FIELD_ENCODE(74, 13, 12), 180 /* AMS_PLL_FORCE_KVH_BW:14:14 */ 181 PHYMOD_SYMBOL_FIELD_ENCODE(32, 14, 14), 182 /* AMS_PLL_FORCE_RESCAL:15:15 */ 183 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(33, 15, 15) 184 }; 185 static uint32_t BCMI_TSCE_XGXS_AMS_CTL5r_fields[] = 186 { 187 /* AMS_PLL_MAX_TEST_PORT_AMPL:0:0 */ 188 PHYMOD_SYMBOL_FIELD_ENCODE(76, 0, 0), 189 /* AMS_PLL_BGIP:1:1 */ 190 PHYMOD_SYMBOL_FIELD_ENCODE(22, 1, 1), 191 /* AMS_PLL_BGINT:2:2 */ 192 PHYMOD_SYMBOL_FIELD_ENCODE(21, 2, 2), 193 /* AMS_PLL_VBYPASS:3:3 */ 194 PHYMOD_SYMBOL_FIELD_ENCODE(97, 3, 3), 195 /* AMS_PLL_TEST_PNP:4:5 */ 196 PHYMOD_SYMBOL_FIELD_ENCODE(91, 5, 4), 197 /* AMS_PLL_BGCALR_CTATADJ:6:10 */ 198 PHYMOD_SYMBOL_FIELD_ENCODE(19, 10, 6), 199 /* AMS_PLL_BGCALR_PTATADJ:11:15 */ 200 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(20, 15, 11) 201 }; 202 static uint32_t BCMI_TSCE_XGXS_AMS_CTL6r_fields[] = 203 { 204 /* AMS_PLL_TEST_FRACN_EN:0:0 */ 205 PHYMOD_SYMBOL_FIELD_ENCODE(89, 0, 0), 206 /* AMS_PLL_PDF_SKEW_ENLARGE:1:1 */ 207 PHYMOD_SYMBOL_FIELD_ENCODE(81, 1, 1), 208 /* AMS_PLL_PDF_FD_SKEW:2:2 */ 209 PHYMOD_SYMBOL_FIELD_ENCODE(79, 2, 2), 210 /* AMS_PLL_PDF_REF_SKEW:3:3 */ 211 PHYMOD_SYMBOL_FIELD_ENCODE(80, 3, 3), 212 /* AMS_PLL_SPARE_100:4:4 */ 213 PHYMOD_SYMBOL_FIELD_ENCODE(86, 4, 4), 214 /* AMS_PLL_REFCLK_DOUBLER:5:5 */ 215 PHYMOD_SYMBOL_FIELD_ENCODE(82, 5, 5), 216 /* AMS_PLL_MIX2P1CR_CTATADJ:6:10 */ 217 PHYMOD_SYMBOL_FIELD_ENCODE(77, 10, 6), 218 /* AMS_PLL_MIX2P1CR_PTATADJ:11:15 */ 219 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(78, 15, 11) 220 }; 221 static uint32_t BCMI_TSCE_XGXS_AMS_CTL7r_fields[] = 222 { 223 /* AMS_PLL_FRACN_DIV_L:0:15 */ 224 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(39, 15, 0) 225 }; 226 static uint32_t BCMI_TSCE_XGXS_AMS_CTL8r_fields[] = 227 { 228 /* AMS_PLL_FRACN_DIV_H:0:1 */ 229 PHYMOD_SYMBOL_FIELD_ENCODE(38, 1, 0), 230 /* AMS_PLL_FRACN_DIVRANGE:2:2 */ 231 PHYMOD_SYMBOL_FIELD_ENCODE(37, 2, 2), 232 /* AMS_PLL_FRACN_BYPASS:3:3 */ 233 PHYMOD_SYMBOL_FIELD_ENCODE(36, 3, 3), 234 /* AMS_PLL_FRACN_NDIV_INT:4:13 */ 235 PHYMOD_SYMBOL_FIELD_ENCODE(40, 13, 4), 236 /* AMS_PLL_DITHEREN:14:14 */ 237 PHYMOD_SYMBOL_FIELD_ENCODE(29, 14, 14), 238 /* AMS_PLL_FRACN_SEL:15:15 */ 239 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(41, 15, 15) 240 }; 241 static uint32_t BCMI_TSCE_XGXS_AMS_INTCTLr_fields[] = 242 { 243 /* AMS_PLL_TX_LOWPWR_6G:0:0 */ 244 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(96, 0, 0) 245 }; 246 static uint32_t BCMI_TSCE_XGXS_AMS_RX_CTL0r_fields[] = 247 { 248 /* AMS_RX_SEL_DFECKDELAY:0:1 */ 249 PHYMOD_SYMBOL_FIELD_ENCODE(150, 1, 0), 250 /* AMS_RX_PHASE_INT_AMPL_CTRL:2:2 */ 251 PHYMOD_SYMBOL_FIELD_ENCODE(148, 2, 2), 252 /* AMS_RX_SIGDET_THRESHOLD:3:5 */ 253 PHYMOD_SYMBOL_FIELD_ENCODE(155, 5, 3), 254 /* AMS_RX_SIG_PWRDN:6:6 */ 255 PHYMOD_SYMBOL_FIELD_ENCODE(156, 6, 6), 256 /* AMS_RX_VGA_OUTPUT_IDLE:7:7 */ 257 PHYMOD_SYMBOL_FIELD_ENCODE(167, 7, 7), 258 /* AMS_RX_TPORT_EN:8:8 */ 259 PHYMOD_SYMBOL_FIELD_ENCODE(165, 8, 8), 260 /* AMS_RX_SIGDET_BYPASS:9:9 */ 261 PHYMOD_SYMBOL_FIELD_ENCODE(153, 9, 9), 262 /* AMS_RX_SIGDET_LOW_POWER:10:10 */ 263 PHYMOD_SYMBOL_FIELD_ENCODE(154, 10, 10), 264 /* AMS_RX_VGA_BW_EXTENSION:11:11 */ 265 PHYMOD_SYMBOL_FIELD_ENCODE(166, 11, 11), 266 /* AMS_RX_DC_COUPLE:12:12 */ 267 PHYMOD_SYMBOL_FIELD_ENCODE(103, 12, 12), 268 /* AMS_RX_EN_10GMODE:13:13 */ 269 PHYMOD_SYMBOL_FIELD_ENCODE(107, 13, 13), 270 /* AMS_RX_IMIN_COMMONMODE:14:14 */ 271 PHYMOD_SYMBOL_FIELD_ENCODE(124, 14, 14), 272 /* AMS_RX_IMOD_COMMONMODE:15:15 */ 273 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(147, 15, 15) 274 }; 275 static uint32_t BCMI_TSCE_XGXS_AMS_RX_CTL1r_fields[] = 276 { 277 /* AMS_RX_IMAX_COMMONMODE:0:0 */ 278 PHYMOD_SYMBOL_FIELD_ENCODE(112, 0, 0), 279 /* AMS_RX_IMIN_PHASE_INT:1:1 */ 280 PHYMOD_SYMBOL_FIELD_ENCODE(131, 1, 1), 281 /* AMS_RX_IMODE_PHASE_INT:2:2 */ 282 PHYMOD_SYMBOL_FIELD_ENCODE(142, 2, 2), 283 /* AMS_RX_IMAX_PHASE_INT:3:3 */ 284 PHYMOD_SYMBOL_FIELD_ENCODE(119, 3, 3), 285 /* AMS_RX_IMIN_VGA:4:4 */ 286 PHYMOD_SYMBOL_FIELD_ENCODE(135, 4, 4), 287 /* AMS_RX_IMODE_VGA:5:5 */ 288 PHYMOD_SYMBOL_FIELD_ENCODE(146, 5, 5), 289 /* AMS_RX_IMAX_VGA:6:6 */ 290 PHYMOD_SYMBOL_FIELD_ENCODE(123, 6, 6), 291 /* AMS_RX_IMIN_DFE_SUMMER:7:7 */ 292 PHYMOD_SYMBOL_FIELD_ENCODE(127, 7, 7), 293 /* AMS_RX_IMODE_DFE_SUMMER:8:8 */ 294 PHYMOD_SYMBOL_FIELD_ENCODE(138, 8, 8), 295 /* AMS_RX_IMAX_DFE_SUMMER:9:9 */ 296 PHYMOD_SYMBOL_FIELD_ENCODE(115, 9, 9), 297 /* AMS_RX_IMIN_PF:10:10 */ 298 PHYMOD_SYMBOL_FIELD_ENCODE(130, 10, 10), 299 /* AMS_RX_IMODE_PF:11:11 */ 300 PHYMOD_SYMBOL_FIELD_ENCODE(141, 11, 11), 301 /* AMS_RX_IMAX_PF:12:12 */ 302 PHYMOD_SYMBOL_FIELD_ENCODE(118, 12, 12), 303 /* AMS_RX_IMIN_CTAT:13:13 */ 304 PHYMOD_SYMBOL_FIELD_ENCODE(125, 13, 13), 305 /* AMS_RX_IMODE_CTAT:14:14 */ 306 PHYMOD_SYMBOL_FIELD_ENCODE(136, 14, 14), 307 /* AMS_RX_IMAX_CTAT:15:15 */ 308 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(113, 15, 15) 309 }; 310 static uint32_t BCMI_TSCE_XGXS_AMS_RX_CTL2r_fields[] = 311 { 312 /* AMS_RX_SPARE_32:0:0 */ 313 PHYMOD_SYMBOL_FIELD_ENCODE(157, 0, 0), 314 /* AMS_RX_SPARE_33:1:1 */ 315 PHYMOD_SYMBOL_FIELD_ENCODE(158, 1, 1), 316 /* AMS_RX_SPARE_34:2:2 */ 317 PHYMOD_SYMBOL_FIELD_ENCODE(159, 2, 2), 318 /* AMS_RX_IMIN_SLICER:3:3 */ 319 PHYMOD_SYMBOL_FIELD_ENCODE(134, 3, 3), 320 /* AMS_RX_IMODE_SLICER:4:4 */ 321 PHYMOD_SYMBOL_FIELD_ENCODE(145, 4, 4), 322 /* AMS_RX_IMAX_SLICER:5:5 */ 323 PHYMOD_SYMBOL_FIELD_ENCODE(122, 5, 5), 324 /* AMS_RX_IMIN_DFE_TAP_WEIGHT:6:6 */ 325 PHYMOD_SYMBOL_FIELD_ENCODE(128, 6, 6), 326 /* AMS_RX_IMODE_DFE_TAP_WEIGHT:7:7 */ 327 PHYMOD_SYMBOL_FIELD_ENCODE(139, 7, 7), 328 /* AMS_RX_IMAX_DFE_TAP_WEIGHT:8:8 */ 329 PHYMOD_SYMBOL_FIELD_ENCODE(116, 8, 8), 330 /* AMS_RX_SEL_UGBW:9:10 */ 331 PHYMOD_SYMBOL_FIELD_ENCODE(152, 10, 9), 332 /* AMS_RX_SEL_TH4DFE:11:12 */ 333 PHYMOD_SYMBOL_FIELD_ENCODE(151, 12, 11), 334 /* AMS_RX_EN_VCCTRL:13:13 */ 335 PHYMOD_SYMBOL_FIELD_ENCODE(108, 13, 13), 336 /* AMS_RX_SPARE_46:14:14 */ 337 PHYMOD_SYMBOL_FIELD_ENCODE(160, 14, 14), 338 /* AMS_RX_SPARE_47:15:15 */ 339 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(161, 15, 15) 340 }; 341 static uint32_t BCMI_TSCE_XGXS_AMS_RX_CTL3r_fields[] = 342 { 343 /* AMS_RX_IMIN_DC_OFFSET_DAC:0:0 */ 344 PHYMOD_SYMBOL_FIELD_ENCODE(126, 0, 0), 345 /* AMS_RX_IMODE_DC_OFFSET_DAC:1:1 */ 346 PHYMOD_SYMBOL_FIELD_ENCODE(137, 1, 1), 347 /* AMS_RX_IMAX_DC_OFFSET_DAC:2:2 */ 348 PHYMOD_SYMBOL_FIELD_ENCODE(114, 2, 2), 349 /* AMS_RX_IMIN_PHASE_INT_P1:3:3 */ 350 PHYMOD_SYMBOL_FIELD_ENCODE(132, 3, 3), 351 /* AMS_RX_IMODE_PHASE_INT_P1:4:4 */ 352 PHYMOD_SYMBOL_FIELD_ENCODE(143, 4, 4), 353 /* AMS_RX_IMAX_PHASE_INT_P1:5:5 */ 354 PHYMOD_SYMBOL_FIELD_ENCODE(120, 5, 5), 355 /* AMS_RX_IMIN_METRES_EYEDIAG:6:6 */ 356 PHYMOD_SYMBOL_FIELD_ENCODE(129, 6, 6), 357 /* AMS_RX_IMODE_METRES_EYEDIAG:7:7 */ 358 PHYMOD_SYMBOL_FIELD_ENCODE(140, 7, 7), 359 /* AMS_RX_IMAX_METRES_EYEDIAG:8:8 */ 360 PHYMOD_SYMBOL_FIELD_ENCODE(117, 8, 8), 361 /* AMS_RX_IMIN_SIGNAL_DETECT:9:9 */ 362 PHYMOD_SYMBOL_FIELD_ENCODE(133, 9, 9), 363 /* AMS_RX_IMODE_SIGNAL_DETECT:10:10 */ 364 PHYMOD_SYMBOL_FIELD_ENCODE(144, 10, 10), 365 /* AMS_RX_IMAX_SIGNAL_DETECT:11:11 */ 366 PHYMOD_SYMBOL_FIELD_ENCODE(121, 11, 11), 367 /* AMS_RX_I4DEADZONE:12:12 */ 368 PHYMOD_SYMBOL_FIELD_ENCODE(111, 12, 12), 369 /* AMS_RX_I1P25DFE:13:13 */ 370 PHYMOD_SYMBOL_FIELD_ENCODE(110, 13, 13), 371 /* AMS_RX_SPARE_62:14:14 */ 372 PHYMOD_SYMBOL_FIELD_ENCODE(162, 14, 14), 373 /* AMS_RX_SPARE_63:15:15 */ 374 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(163, 15, 15) 375 }; 376 static uint32_t BCMI_TSCE_XGXS_AMS_RX_CTL4r_fields[] = 377 { 378 /* AMS_RX_DC_OFFSET:0:6 */ 379 PHYMOD_SYMBOL_FIELD_ENCODE(104, 6, 0), 380 /* AMS_RX_FORCE_DC_OFFSET:7:7 */ 381 PHYMOD_SYMBOL_FIELD_ENCODE(109, 7, 7), 382 /* AMS_RX_DC_OFFSET_RANGE:8:8 */ 383 PHYMOD_SYMBOL_FIELD_ENCODE(105, 8, 8), 384 /* AMS_RX_VGA_RESCAL_MUX:9:11 */ 385 PHYMOD_SYMBOL_FIELD_ENCODE(168, 11, 9), 386 /* AMS_RX_PHS_INTERP_RESCAL_MUX:12:15 */ 387 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(149, 15, 12) 388 }; 389 static uint32_t BCMI_TSCE_XGXS_AMS_RX_INTCTLr_fields[] = 390 { 391 /* AMS_RX_DFE_OS2X_MODE:0:0 */ 392 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(106, 0, 0) 393 }; 394 static uint32_t BCMI_TSCE_XGXS_AMS_RX_STSr_fields[] = 395 { 396 /* AMS_RX_STS:0:15 */ 397 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(164, 15, 0) 398 }; 399 static uint32_t BCMI_TSCE_XGXS_AMS_STSr_fields[] = 400 { 401 /* AMS_PLL_STS:0:15 */ 402 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(88, 15, 0) 403 }; 404 static uint32_t BCMI_TSCE_XGXS_AMS_TX_CTL0r_fields[] = 405 { 406 /* AMS_TX_OSR4:0:0 */ 407 PHYMOD_SYMBOL_FIELD_ENCODE(181, 0, 0), 408 /* AMS_TX_SPARE_1:1:1 */ 409 PHYMOD_SYMBOL_FIELD_ENCODE(187, 1, 1), 410 /* AMS_TX_SPARE_2:2:2 */ 411 PHYMOD_SYMBOL_FIELD_ENCODE(188, 2, 2), 412 /* AMS_TX_SPARE_3:3:3 */ 413 PHYMOD_SYMBOL_FIELD_ENCODE(189, 3, 3), 414 /* AMS_TX_TEST_DATA:4:5 */ 415 PHYMOD_SYMBOL_FIELD_ENCODE(192, 5, 4), 416 /* AMS_TX_TICKSEL:6:7 */ 417 PHYMOD_SYMBOL_FIELD_ENCODE(193, 7, 6), 418 /* AMS_TX_KR_TEST_MODE:8:8 */ 419 PHYMOD_SYMBOL_FIELD_ENCODE(179, 8, 8), 420 /* AMS_TX_DCC_SEL:9:9 */ 421 PHYMOD_SYMBOL_FIELD_ENCODE(173, 9, 9), 422 /* AMS_TX_DCC_DIS:10:10 */ 423 PHYMOD_SYMBOL_FIELD_ENCODE(172, 10, 10), 424 /* AMS_TX_CAL_OFF:11:11 */ 425 PHYMOD_SYMBOL_FIELD_ENCODE(171, 11, 11), 426 /* AMS_TX_CAL_AUX:12:15 */ 427 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(170, 15, 12) 428 }; 429 static uint32_t BCMI_TSCE_XGXS_AMS_TX_CTL1r_fields[] = 430 { 431 /* AMS_TX_IBIAS:0:2 */ 432 PHYMOD_SYMBOL_FIELD_ENCODE(176, 2, 0), 433 /* AMS_TX_IDCC:3:5 */ 434 PHYMOD_SYMBOL_FIELD_ENCODE(178, 5, 3), 435 /* AMS_TX_ICML:6:8 */ 436 PHYMOD_SYMBOL_FIELD_ENCODE(177, 8, 6), 437 /* AMS_TX_SPARE_30_25:9:14 */ 438 PHYMOD_SYMBOL_FIELD_ENCODE(190, 14, 9), 439 /* AMS_TX_LP_OVRD:15:15 */ 440 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(180, 15, 15) 441 }; 442 static uint32_t BCMI_TSCE_XGXS_AMS_TX_CTL2r_fields[] = 443 { 444 /* AMS_TX_AMP_CTL:0:3 */ 445 PHYMOD_SYMBOL_FIELD_ENCODE(169, 3, 0), 446 /* AMS_TX_POST3_COEF:4:6 */ 447 PHYMOD_SYMBOL_FIELD_ENCODE(183, 6, 4), 448 /* AMS_TX_SIGN_POST3:7:7 */ 449 PHYMOD_SYMBOL_FIELD_ENCODE(186, 7, 7), 450 /* AMS_TX_POST2_COEF:8:11 */ 451 PHYMOD_SYMBOL_FIELD_ENCODE(182, 11, 8), 452 /* AMS_TX_SIGN_POST2:12:12 */ 453 PHYMOD_SYMBOL_FIELD_ENCODE(185, 12, 12), 454 /* AMS_TX_DRIVERMODE:13:14 */ 455 PHYMOD_SYMBOL_FIELD_ENCODE(174, 14, 13), 456 /* AMS_TX_ELEC_IDLE_AUX:15:15 */ 457 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(175, 15, 15) 458 }; 459 static uint32_t BCMI_TSCE_XGXS_AMS_TX_INTCTLr_fields[] = 460 { 461 /* AMS_TX_SEL_HALFRATE:0:0 */ 462 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(184, 0, 0) 463 }; 464 static uint32_t BCMI_TSCE_XGXS_AMS_TX_STSr_fields[] = 465 { 466 /* AMS_TX_STS:0:15 */ 467 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(191, 15, 0) 468 }; 469 static uint32_t BCMI_TSCE_XGXS_AN_X1_BAM_SPD_PRI_11_6r_fields[] = 470 { 471 /* AN_PRIORITY_10GCX4:0:1 */ 472 PHYMOD_SYMBOL_FIELD_ENCODE(222, 1, 0), 473 /* AN_PRIORITY_10GCX1:2:3 */ 474 PHYMOD_SYMBOL_FIELD_ENCODE(220, 3, 2), 475 /* AN_PRIORITY_6GX4:4:5 */ 476 PHYMOD_SYMBOL_FIELD_ENCODE(252, 5, 4), 477 /* AN_PRIORITY_10GX4:6:7 */ 478 PHYMOD_SYMBOL_FIELD_ENCODE(226, 7, 6), 479 /* AN_PRIORITY_10GKX4:8:9 */ 480 PHYMOD_SYMBOL_FIELD_ENCODE(224, 9, 8), 481 /* AN_PRIORITY_10GKR:10:11 */ 482 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(223, 11, 10) 483 }; 484 static uint32_t BCMI_TSCE_XGXS_AN_X1_BAM_SPD_PRI_17_12r_fields[] = 485 { 486 /* AN_PRIORITY_10P5GX2:0:1 */ 487 PHYMOD_SYMBOL_FIELD_ENCODE(228, 1, 0), 488 /* AN_PRIORITY_10GX2:2:3 */ 489 PHYMOD_SYMBOL_FIELD_ENCODE(225, 3, 2), 490 /* AN_PRIORITY_10GCX2:4:5 */ 491 PHYMOD_SYMBOL_FIELD_ENCODE(221, 5, 4), 492 /* AN_PRIORITY_12P7GX2:6:7 */ 493 PHYMOD_SYMBOL_FIELD_ENCODE(231, 7, 6), 494 /* AN_PRIORITY_12P5GX4:8:9 */ 495 PHYMOD_SYMBOL_FIELD_ENCODE(230, 9, 8), 496 /* AN_PRIORITY_12GX4:10:11 */ 497 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(229, 11, 10) 498 }; 499 static uint32_t BCMI_TSCE_XGXS_AN_X1_BAM_SPD_PRI_23_18r_fields[] = 500 { 501 /* AN_PRIORITY_15P75GX2:0:1 */ 502 PHYMOD_SYMBOL_FIELD_ENCODE(234, 1, 0), 503 /* AN_PRIORITY_15GX4:2:3 */ 504 PHYMOD_SYMBOL_FIELD_ENCODE(233, 3, 2), 505 /* AN_PRIORITY_13GX4:4:5 */ 506 PHYMOD_SYMBOL_FIELD_ENCODE(232, 5, 4), 507 /* AN_PRIORITY_100GCR10:6:7 */ 508 PHYMOD_SYMBOL_FIELD_ENCODE(218, 7, 6), 509 /* AN_PRIORITY_40GKR4:8:9 */ 510 PHYMOD_SYMBOL_FIELD_ENCODE(249, 9, 8), 511 /* AN_PRIORITY_40GCR4:10:11 */ 512 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(248, 11, 10) 513 }; 514 static uint32_t BCMI_TSCE_XGXS_AN_X1_BAM_SPD_PRI_29_24r_fields[] = 515 { 516 /* AN_PRIORITY_20GCR2:0:1 */ 517 PHYMOD_SYMBOL_FIELD_ENCODE(237, 1, 0), 518 /* AN_PRIORITY_20GCX2:2:3 */ 519 PHYMOD_SYMBOL_FIELD_ENCODE(238, 3, 2), 520 /* AN_PRIORITY_16GX4:4:5 */ 521 PHYMOD_SYMBOL_FIELD_ENCODE(235, 5, 4), 522 /* AN_PRIORITY_20GX2:6:7 */ 523 PHYMOD_SYMBOL_FIELD_ENCODE(241, 7, 6), 524 /* AN_PRIORITY_20GCX4:8:9 */ 525 PHYMOD_SYMBOL_FIELD_ENCODE(239, 9, 8), 526 /* AN_PRIORITY_20GKR2:10:11 */ 527 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(240, 11, 10) 528 }; 529 static uint32_t BCMI_TSCE_XGXS_AN_X1_BAM_SPD_PRI_35_30r_fields[] = 530 { 531 /* AN_PRIORITY_25P45GX4:0:1 */ 532 PHYMOD_SYMBOL_FIELD_ENCODE(244, 1, 0), 533 /* AN_PRIORITY_21GX4:2:3 */ 534 PHYMOD_SYMBOL_FIELD_ENCODE(243, 3, 2), 535 /* AN_PRIORITY_20GX4:4:5 */ 536 PHYMOD_SYMBOL_FIELD_ENCODE(242, 5, 4), 537 /* AN_PRIORITY_40GX4:6:7 */ 538 PHYMOD_SYMBOL_FIELD_ENCODE(250, 7, 6), 539 /* AN_PRIORITY_32P7G:8:9 */ 540 PHYMOD_SYMBOL_FIELD_ENCODE(247, 9, 8), 541 /* AN_PRIORITY_31P5G:10:11 */ 542 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(246, 11, 10) 543 }; 544 static uint32_t BCMI_TSCE_XGXS_AN_X1_BAM_SPD_PRI_5_0r_fields[] = 545 { 546 /* AN_PRIORITY_1000M:0:1 */ 547 PHYMOD_SYMBOL_FIELD_ENCODE(217, 1, 0), 548 /* AN_PRIORITY_100M:2:3 */ 549 PHYMOD_SYMBOL_FIELD_ENCODE(219, 3, 2), 550 /* AN_PRIORITY_10M:4:5 */ 551 PHYMOD_SYMBOL_FIELD_ENCODE(227, 5, 4), 552 /* AN_PRIORITY_5GX4:6:7 */ 553 PHYMOD_SYMBOL_FIELD_ENCODE(251, 7, 6), 554 /* AN_PRIORITY_2P5GX1:8:9 */ 555 PHYMOD_SYMBOL_FIELD_ENCODE(245, 9, 8), 556 /* AN_PRIORITY_1GKX:10:11 */ 557 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(236, 11, 10) 558 }; 559 static uint32_t BCMI_TSCE_XGXS_AN_X1_CFG_CTLr_fields[] = 560 { 561 /* AN_PD_TO_CL37_RETRY_COUNT:0:7 */ 562 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(216, 7, 0) 563 }; 564 static uint32_t BCMI_TSCE_XGXS_AN_X1_CL37_ACKr_fields[] = 565 { 566 /* CL37_ACK_TIMER_PERIOD:0:15 */ 567 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(403, 15, 0) 568 }; 569 static uint32_t BCMI_TSCE_XGXS_AN_X1_CL37_ERRr_fields[] = 570 { 571 /* CL37_ERROR_TIMER_PERIOD:0:15 */ 572 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(410, 15, 0) 573 }; 574 static uint32_t BCMI_TSCE_XGXS_AN_X1_CL37_RESTARTr_fields[] = 575 { 576 /* CL37_RESTART_TIMER_PERIOD:0:15 */ 577 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(416, 15, 0) 578 }; 579 static uint32_t BCMI_TSCE_XGXS_AN_X1_CL37_SYNC_STS_FILTER_TMRr_fields[] = 580 { 581 /* CL37_SYNC_STATUS_FILTER_TIMER_PERIOD:0:15 */ 582 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(419, 15, 0) 583 }; 584 static uint32_t BCMI_TSCE_XGXS_AN_X1_CL73_BRK_LNKr_fields[] = 585 { 586 /* TX_DISABLE_TIMER_PERIOD:0:15 */ 587 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1355, 15, 0) 588 }; 589 static uint32_t BCMI_TSCE_XGXS_AN_X1_CL73_DME_LOCKr_fields[] = 590 { 591 /* PD_DME_LOCK_TIMER_PERIOD:0:15 */ 592 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1003, 15, 0) 593 }; 594 static uint32_t BCMI_TSCE_XGXS_AN_X1_CL73_ERRr_fields[] = 595 { 596 /* CL73_ERROR_TIMER_PERIOD:0:15 */ 597 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(519, 15, 0) 598 }; 599 static uint32_t BCMI_TSCE_XGXS_AN_X1_DME_PAGE_TMRr_fields[] = 600 { 601 /* CL73_PAGE_TEST_MIN_TIMER:0:6 */ 602 PHYMOD_SYMBOL_FIELD_ENCODE(526, 6, 0), 603 /* CL73_PAGE_TEST_MAX_TIMER:7:13 */ 604 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(525, 13, 7) 605 }; 606 static uint32_t BCMI_TSCE_XGXS_AN_X1_IGNORE_LNK_TMRr_fields[] = 607 { 608 /* IGNORE_LINK_TIMER_PERIOD:0:15 */ 609 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(768, 15, 0) 610 }; 611 static uint32_t BCMI_TSCE_XGXS_AN_X1_LNK_FAIL_INHBT_TMR_CL72r_fields[] = 612 { 613 /* LINK_FAIL_INHIBIT_TIMER_CL72_PERIOD:0:15 */ 614 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(808, 15, 0) 615 }; 616 static uint32_t BCMI_TSCE_XGXS_AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72r_fields[] = 617 { 618 /* LINK_FAIL_INHIBIT_TIMER_NCL72_PERIOD:0:15 */ 619 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(809, 15, 0) 620 }; 621 static uint32_t BCMI_TSCE_XGXS_AN_X1_LNK_UPr_fields[] = 622 { 623 /* CL73_LINK_UP_TIMER_PERIOD:0:15 */ 624 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(521, 15, 0) 625 }; 626 static uint32_t BCMI_TSCE_XGXS_AN_X1_OUI_LWRr_fields[] = 627 { 628 /* OUI_LOWER_DATA:0:15 */ 629 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(963, 15, 0) 630 }; 631 static uint32_t BCMI_TSCE_XGXS_AN_X1_OUI_UPRr_fields[] = 632 { 633 /* OUI_UPPER_DATA:0:7 */ 634 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(964, 7, 0) 635 }; 636 static uint32_t BCMI_TSCE_XGXS_AN_X1_PD_SD_TMRr_fields[] = 637 { 638 /* PD_SD_TIMER_PERIOD:0:15 */ 639 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1008, 15, 0) 640 }; 641 static uint32_t BCMI_TSCE_XGXS_AN_X1_PD_TO_CL37_LNK_WAIT_TMRr_fields[] = 642 { 643 /* PD_TO_CL37_LINK_WAIT_TIMER:0:15 */ 644 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1009, 15, 0) 645 }; 646 static uint32_t BCMI_TSCE_XGXS_AN_X1_SGMII_CL73_TMR_TYPEr_fields[] = 647 { 648 /* SGMII_TIMER:0:15 */ 649 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1237, 15, 0) 650 }; 651 static uint32_t BCMI_TSCE_XGXS_AN_X4_AN_ABIL_RESOLUTION_STSr_fields[] = 652 { 653 /* AN_HCD_SWITCH_TO_CL37:0:0 */ 654 PHYMOD_SYMBOL_FIELD_ENCODE(214, 0, 0), 655 /* AN_HCD_HIGIG2:1:1 */ 656 PHYMOD_SYMBOL_FIELD_ENCODE(211, 1, 1), 657 /* AN_HCD_CL72:2:2 */ 658 PHYMOD_SYMBOL_FIELD_ENCODE(208, 2, 2), 659 /* AN_HCD_FEC:3:3 */ 660 PHYMOD_SYMBOL_FIELD_ENCODE(210, 3, 3), 661 /* AN_HCD_SPEED:4:11 */ 662 PHYMOD_SYMBOL_FIELD_ENCODE(213, 11, 4), 663 /* AN_HCD_PAUSE:12:13 */ 664 PHYMOD_SYMBOL_FIELD_ENCODE(212, 13, 12), 665 /* AN_HCD_DUPLEX:14:14 */ 666 PHYMOD_SYMBOL_FIELD_ENCODE(209, 14, 14), 667 /* AN_ST_RESOLUTION_ERR:15:15 */ 668 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(282, 15, 15) 669 }; 670 static uint32_t BCMI_TSCE_XGXS_AN_X4_AN_MISC_STSr_fields[] = 671 { 672 /* PD_HCD_KX4_OR_KX:0:0 */ 673 PHYMOD_SYMBOL_FIELD_ENCODE(1004, 0, 0), 674 /* PD_IN_PROGRESS:1:1 */ 675 PHYMOD_SYMBOL_FIELD_ENCODE(1005, 1, 1), 676 /* AN_FAIL_COUNT:2:5 */ 677 PHYMOD_SYMBOL_FIELD_ENCODE(204, 5, 2), 678 /* AN_ACTIVE:6:6 */ 679 PHYMOD_SYMBOL_FIELD_ENCODE(201, 6, 6), 680 /* PD_COMPLETED:7:7 */ 681 PHYMOD_SYMBOL_FIELD_ENCODE(1002, 7, 7), 682 /* REMOTE_FAULT_IN_BASE_PAGE:8:8 */ 683 PHYMOD_SYMBOL_FIELD_ENCODE(1108, 8, 8), 684 /* AN_RETRY_COUNT:9:14 */ 685 PHYMOD_SYMBOL_FIELD_ENCODE(253, 14, 9), 686 /* AN_COMPLETE:15:15 */ 687 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(202, 15, 15) 688 }; 689 static uint32_t BCMI_TSCE_XGXS_AN_X4_AN_PAGE_DECR_STSr_fields[] = 690 { 691 /* AN_RX_ST_STATE:0:1 */ 692 PHYMOD_SYMBOL_FIELD_ENCODE(265, 1, 0), 693 /* AN_RX_ST_RUDI_INVALID:2:2 */ 694 PHYMOD_SYMBOL_FIELD_ENCODE(264, 2, 2), 695 /* AN_RX_ST_RUDI_CONFIG:3:3 */ 696 PHYMOD_SYMBOL_FIELD_ENCODE(262, 3, 3), 697 /* AN_RX_ST_RUDI_IDLE:4:4 */ 698 PHYMOD_SYMBOL_FIELD_ENCODE(263, 4, 4), 699 /* AN_RX_ST_PAGE:5:5 */ 700 PHYMOD_SYMBOL_FIELD_ENCODE(256, 5, 5), 701 /* AN_RX_ST_MV_PAIR:6:6 */ 702 PHYMOD_SYMBOL_FIELD_ENCODE(255, 6, 6), 703 /* AN_RX_ST_CLK_TRANS_MISS:7:7 */ 704 PHYMOD_SYMBOL_FIELD_ENCODE(254, 7, 7), 705 /* AN_RX_ST_PAGE_TOO_LONG:8:8 */ 706 PHYMOD_SYMBOL_FIELD_ENCODE(257, 8, 8), 707 /* AN_RX_ST_PAGE_TOO_SHORT:9:9 */ 708 PHYMOD_SYMBOL_FIELD_ENCODE(258, 9, 9), 709 /* AN_RX_ST_PULSE_TOO_LONG:10:10 */ 710 PHYMOD_SYMBOL_FIELD_ENCODE(259, 10, 10), 711 /* AN_RX_ST_PULSE_TOO_SHORT:11:11 */ 712 PHYMOD_SYMBOL_FIELD_ENCODE(261, 11, 11), 713 /* AN_RX_ST_PULSE_TOO_MODERATE:12:12 */ 714 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(260, 12, 12) 715 }; 716 static uint32_t BCMI_TSCE_XGXS_AN_X4_AN_PAGE_EXCHANGEER_STSr_fields[] = 717 { 718 /* AN_ST_CONFIG_RESTART:0:0 */ 719 PHYMOD_SYMBOL_FIELD_ENCODE(274, 0, 0), 720 /* AN_ST_IDLE_DETECT:1:1 */ 721 PHYMOD_SYMBOL_FIELD_ENCODE(279, 1, 1), 722 /* AN_ST_DISABLE_LINK:2:2 */ 723 PHYMOD_SYMBOL_FIELD_ENCODE(276, 2, 2), 724 /* AN_ST_ERROR_STATE:3:3 */ 725 PHYMOD_SYMBOL_FIELD_ENCODE(277, 3, 3), 726 /* AN_ST_AN_ENABLE:4:4 */ 727 PHYMOD_SYMBOL_FIELD_ENCODE(268, 4, 4), 728 /* AN_ST_ABILITY_DETECT:5:5 */ 729 PHYMOD_SYMBOL_FIELD_ENCODE(266, 5, 5), 730 /* AN_ST_ACK_DETECT:6:6 */ 731 PHYMOD_SYMBOL_FIELD_ENCODE(267, 6, 6), 732 /* AN_ST_COMPLETE_ACK:7:7 */ 733 PHYMOD_SYMBOL_FIELD_ENCODE(272, 7, 7), 734 /* AN_ST_CONSISTENCY_MISMATCH:8:8 */ 735 PHYMOD_SYMBOL_FIELD_ENCODE(275, 8, 8), 736 /* AN_ST_CONFIG_NONZERO:9:9 */ 737 PHYMOD_SYMBOL_FIELD_ENCODE(273, 9, 9), 738 /* AN_ST_RESTART:10:10 */ 739 PHYMOD_SYMBOL_FIELD_ENCODE(283, 10, 10), 740 /* AN_ST_AN_GOOD_CHECK:11:11 */ 741 PHYMOD_SYMBOL_FIELD_ENCODE(269, 11, 11), 742 /* AN_ST_LINK_OK:12:12 */ 743 PHYMOD_SYMBOL_FIELD_ENCODE(280, 12, 12), 744 /* AN_ST_NEXT_PAGE_WAIT:13:13 */ 745 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(281, 13, 13) 746 }; 747 static uint32_t BCMI_TSCE_XGXS_AN_X4_AN_PAGE_SEQUENCER_STSr_fields[] = 748 { 749 /* AN_ST_CL73_COMPLETE:0:0 */ 750 PHYMOD_SYMBOL_FIELD_ENCODE(271, 0, 0), 751 /* AN_ST_CL37_COMPLETE:1:1 */ 752 PHYMOD_SYMBOL_FIELD_ENCODE(270, 1, 1), 753 /* AN_ST_RX_NP_TOGGLE_ERR:2:2 */ 754 PHYMOD_SYMBOL_FIELD_ENCODE(291, 2, 2), 755 /* AN_ST_RX_INVALID_SEQ:3:3 */ 756 PHYMOD_SYMBOL_FIELD_ENCODE(285, 3, 3), 757 /* AN_ST_RX_UP_OUI_MATCH:4:4 */ 758 PHYMOD_SYMBOL_FIELD_ENCODE(294, 4, 4), 759 /* AN_ST_RX_UP_OUI_MISMATCH:5:5 */ 760 PHYMOD_SYMBOL_FIELD_ENCODE(295, 5, 5), 761 /* AN_ST_RX_UP_3:6:6 */ 762 PHYMOD_SYMBOL_FIELD_ENCODE(293, 6, 6), 763 /* AN_ST_RX_MP_MISMATCH:7:7 */ 764 PHYMOD_SYMBOL_FIELD_ENCODE(286, 7, 7), 765 /* AN_ST_RX_MP_OVER1G:8:8 */ 766 PHYMOD_SYMBOL_FIELD_ENCODE(289, 8, 8), 767 /* AN_ST_RX_MP_OUI:9:9 */ 768 PHYMOD_SYMBOL_FIELD_ENCODE(288, 9, 9), 769 /* AN_ST_RX_MP_NULL:10:10 */ 770 PHYMOD_SYMBOL_FIELD_ENCODE(287, 10, 10), 771 /* AN_ST_RX_NP:11:11 */ 772 PHYMOD_SYMBOL_FIELD_ENCODE(290, 11, 11), 773 /* AN_ST_RX_BP:12:12 */ 774 PHYMOD_SYMBOL_FIELD_ENCODE(284, 12, 12), 775 /* AN_ST_RX_SGMII_MISMATCH:13:13 */ 776 PHYMOD_SYMBOL_FIELD_ENCODE(292, 13, 13), 777 /* AN_ST_HP_MODE:14:14 */ 778 PHYMOD_SYMBOL_FIELD_ENCODE(278, 14, 14), 779 /* AN_ST_SGMII_MODE:15:15 */ 780 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(296, 15, 15) 781 }; 782 static uint32_t BCMI_TSCE_XGXS_AN_X4_AN_SEQ_UNEXPECTED_PAGEr_fields[] = 783 { 784 /* SEQ_UNEXPECTED_PAGE:0:15 */ 785 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1229, 15, 0) 786 }; 787 static uint32_t BCMI_TSCE_XGXS_AN_X4_CTLSr_fields[] = 788 { 789 /* PD_KX4_EN:0:0 */ 790 PHYMOD_SYMBOL_FIELD_ENCODE(1006, 0, 0), 791 /* PD_KX_EN:1:1 */ 792 PHYMOD_SYMBOL_FIELD_ENCODE(1007, 1, 1), 793 /* AN_GOOD_TRAP:2:2 */ 794 PHYMOD_SYMBOL_FIELD_ENCODE(207, 2, 2), 795 /* AN_GOOD_CHECK_TRAP:3:3 */ 796 PHYMOD_SYMBOL_FIELD_ENCODE(206, 3, 3), 797 /* LINKFAILTIMER_DIS:4:4 */ 798 PHYMOD_SYMBOL_FIELD_ENCODE(805, 4, 4), 799 /* LINKFAILTIMERQUAL_EN:5:5 */ 800 PHYMOD_SYMBOL_FIELD_ENCODE(804, 5, 5), 801 /* AN_FAIL_COUNT_LIMIT:6:9 */ 802 PHYMOD_SYMBOL_FIELD_ENCODE(205, 9, 6), 803 /* OUI_CONTROL:10:15 */ 804 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(962, 15, 10) 805 }; 806 static uint32_t BCMI_TSCE_XGXS_AN_X4_ENSr_fields[] = 807 { 808 /* CL73_AN_RESTART:0:0 */ 809 PHYMOD_SYMBOL_FIELD_ENCODE(514, 0, 0), 810 /* CL37_AN_RESTART:1:1 */ 811 PHYMOD_SYMBOL_FIELD_ENCODE(404, 1, 1), 812 /* HPAM_TO_CL73_AUTO_ENABLE:2:2 */ 813 PHYMOD_SYMBOL_FIELD_ENCODE(764, 2, 2), 814 /* CL73_BAM_TO_HPAM_AUTO_ENABLE:3:3 */ 815 PHYMOD_SYMBOL_FIELD_ENCODE(517, 3, 3), 816 /* SGMII_TO_CL37_AUTO_ENABLE:4:4 */ 817 PHYMOD_SYMBOL_FIELD_ENCODE(1238, 4, 4), 818 /* CL37_BAM_TO_SGMII_AUTO_ENABLE:5:5 */ 819 PHYMOD_SYMBOL_FIELD_ENCODE(408, 5, 5), 820 /* CL37_ENABLE:6:6 */ 821 PHYMOD_SYMBOL_FIELD_ENCODE(409, 6, 6), 822 /* CL37_SGMII_ENABLE:7:7 */ 823 PHYMOD_SYMBOL_FIELD_ENCODE(417, 7, 7), 824 /* CL73_ENABLE:8:8 */ 825 PHYMOD_SYMBOL_FIELD_ENCODE(518, 8, 8), 826 /* CL73_HPAM_ENABLE:9:9 */ 827 PHYMOD_SYMBOL_FIELD_ENCODE(520, 9, 9), 828 /* CL73_BAM_ENABLE:10:10 */ 829 PHYMOD_SYMBOL_FIELD_ENCODE(516, 10, 10), 830 /* CL37_BAM_ENABLE:11:11 */ 831 PHYMOD_SYMBOL_FIELD_ENCODE(407, 11, 11), 832 /* NUM_ADVERTISED_LANES:12:13 */ 833 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(948, 13, 12) 834 }; 835 static uint32_t BCMI_TSCE_XGXS_AN_X4_LD_CTLr_fields[] = 836 { 837 /* SW_HCD:0:0 */ 838 PHYMOD_SYMBOL_FIELD_ENCODE(1267, 0, 0), 839 /* SW_AN:1:1 */ 840 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1266, 1, 1) 841 }; 842 static uint32_t BCMI_TSCE_XGXS_AN_X4_LD_PAGE0r_fields[] = 843 { 844 /* LD_PAGE_0_PAGE_DATA:0:15 */ 845 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(801, 15, 0) 846 }; 847 static uint32_t BCMI_TSCE_XGXS_AN_X4_LD_PAGE1r_fields[] = 848 { 849 /* LD_PAGE_1_PAGE_DATA:0:15 */ 850 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(802, 15, 0) 851 }; 852 static uint32_t BCMI_TSCE_XGXS_AN_X4_LD_PAGE2r_fields[] = 853 { 854 /* LD_PAGE_2_PAGE_DATA:0:15 */ 855 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(803, 15, 0) 856 }; 857 static uint32_t BCMI_TSCE_XGXS_AN_X4_LOC_DEV_CL37_BAM_ABILr_fields[] = 858 { 859 /* OVER1G_PAGE_COUNT:0:1 */ 860 PHYMOD_SYMBOL_FIELD_ENCODE(966, 1, 0), 861 /* OVER1G_ABILITY:2:2 */ 862 PHYMOD_SYMBOL_FIELD_ENCODE(965, 2, 2), 863 /* CL37_BAM_CODE:3:11 */ 864 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(406, 11, 3) 865 }; 866 static uint32_t BCMI_TSCE_XGXS_AN_X4_LOC_DEV_CL37_BASE_ABILr_fields[] = 867 { 868 /* SGMII_SPEED:0:1 */ 869 PHYMOD_SYMBOL_FIELD_ENCODE(1236, 1, 0), 870 /* SGMII_FULL_DUPLEX:2:2 */ 871 PHYMOD_SYMBOL_FIELD_ENCODE(1232, 2, 2), 872 /* CL37_FULL_DUPLEX:4:4 */ 873 PHYMOD_SYMBOL_FIELD_ENCODE(411, 4, 4), 874 /* CL37_HALF_DUPLEX:5:5 */ 875 PHYMOD_SYMBOL_FIELD_ENCODE(412, 5, 5), 876 /* CL37_PAUSE:6:7 */ 877 PHYMOD_SYMBOL_FIELD_ENCODE(415, 7, 6), 878 /* CL37_NEXT_PAGE:8:8 */ 879 PHYMOD_SYMBOL_FIELD_ENCODE(414, 8, 8), 880 /* SGMII_MASTER_MODE:9:9 */ 881 PHYMOD_SYMBOL_FIELD_ENCODE(1233, 9, 9), 882 /* AN_PD_TO_CL37_ENABLE:10:10 */ 883 PHYMOD_SYMBOL_FIELD_ENCODE(215, 10, 10), 884 /* CL37_AN_RESTART_RESET_DISABLE:11:11 */ 885 PHYMOD_SYMBOL_FIELD_ENCODE(405, 11, 11), 886 /* CL37_SW_RESTART_RESET_DISABLE:12:12 */ 887 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(418, 12, 12) 888 }; 889 static uint32_t BCMI_TSCE_XGXS_AN_X4_LOC_DEV_CL73_BAM_ABILr_fields[] = 890 { 891 /* BAM_20GBASE_KR2:0:0 */ 892 PHYMOD_SYMBOL_FIELD_ENCODE(319, 0, 0), 893 /* BAM_20GBASE_CR2:1:1 */ 894 PHYMOD_SYMBOL_FIELD_ENCODE(318, 1, 1), 895 /* CL73_BAM_CODE:2:10 */ 896 PHYMOD_SYMBOL_FIELD_ENCODE(515, 10, 2), 897 /* HPAM_20GKR2:11:11 */ 898 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(763, 11, 11) 899 }; 900 static uint32_t BCMI_TSCE_XGXS_AN_X4_LOC_DEV_CL73_BASE_ABIL0r_fields[] = 901 { 902 /* BASE_100GBASE_CR10:0:0 */ 903 PHYMOD_SYMBOL_FIELD_ENCODE(333, 0, 0), 904 /* BASE_40GBASE_CR4:1:1 */ 905 PHYMOD_SYMBOL_FIELD_ENCODE(336, 1, 1), 906 /* BASE_40GBASE_KR4:2:2 */ 907 PHYMOD_SYMBOL_FIELD_ENCODE(337, 2, 2), 908 /* BASE_10GBASE_KR:3:3 */ 909 PHYMOD_SYMBOL_FIELD_ENCODE(334, 3, 3), 910 /* BASE_10GBASE_KX4:4:4 */ 911 PHYMOD_SYMBOL_FIELD_ENCODE(335, 4, 4), 912 /* BASE_1000BASE_KX:5:5 */ 913 PHYMOD_SYMBOL_FIELD_ENCODE(332, 5, 5), 914 /* CL73_PAUSE:6:7 */ 915 PHYMOD_SYMBOL_FIELD_ENCODE(527, 7, 6), 916 /* FEC:8:9 */ 917 PHYMOD_SYMBOL_FIELD_ENCODE(735, 9, 8), 918 /* NEXT_PAGE:10:10 */ 919 PHYMOD_SYMBOL_FIELD_ENCODE(946, 10, 10), 920 /* CL73_REMOTE_FAULT:11:11 */ 921 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(528, 11, 11) 922 }; 923 static uint32_t BCMI_TSCE_XGXS_AN_X4_LOC_DEV_CL73_BASE_ABIL1r_fields[] = 924 { 925 /* BASE_SELECTOR:0:4 */ 926 PHYMOD_SYMBOL_FIELD_ENCODE(338, 4, 0), 927 /* TRANSMIT_NONCE:5:9 */ 928 PHYMOD_SYMBOL_FIELD_ENCODE(1295, 9, 5), 929 /* CL73_NONCE_MATCH_VAL:10:10 */ 930 PHYMOD_SYMBOL_FIELD_ENCODE(524, 10, 10), 931 /* CL73_NONCE_MATCH_OVER:11:11 */ 932 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(523, 11, 11) 933 }; 934 static uint32_t BCMI_TSCE_XGXS_AN_X4_LOC_DEV_OVER1G_ABIL0r_fields[] = 935 { 936 /* BAM_2P5GBASE_X:0:0 */ 937 PHYMOD_SYMBOL_FIELD_ENCODE(326, 0, 0), 938 /* BAM_5GBASE_X4:1:1 */ 939 PHYMOD_SYMBOL_FIELD_ENCODE(330, 1, 1), 940 /* BAM_6GBASE_X4:2:2 */ 941 PHYMOD_SYMBOL_FIELD_ENCODE(331, 2, 2), 942 /* BAM_10GBASE_X4:3:3 */ 943 PHYMOD_SYMBOL_FIELD_ENCODE(308, 3, 3), 944 /* BAM_10GBASE_X4_CX4:4:4 */ 945 PHYMOD_SYMBOL_FIELD_ENCODE(309, 4, 4), 946 /* BAM_10GBASE_X2:5:5 */ 947 PHYMOD_SYMBOL_FIELD_ENCODE(306, 5, 5), 948 /* BAM_10GBASE_X2_CX4:6:6 */ 949 PHYMOD_SYMBOL_FIELD_ENCODE(307, 6, 6), 950 /* BAM_10P5GBASE_X2:7:7 */ 951 PHYMOD_SYMBOL_FIELD_ENCODE(310, 7, 7), 952 /* BAM_12GBASE_X4:8:8 */ 953 PHYMOD_SYMBOL_FIELD_ENCODE(311, 8, 8), 954 /* BAM_12P5GBASE_X4:9:9 */ 955 PHYMOD_SYMBOL_FIELD_ENCODE(312, 9, 9), 956 /* BAM_12P7GBASE_X2:10:10 */ 957 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(313, 10, 10) 958 }; 959 static uint32_t BCMI_TSCE_XGXS_AN_X4_LOC_DEV_OVER1G_ABIL1r_fields[] = 960 { 961 /* BAM_13GBASE_X4:0:0 */ 962 PHYMOD_SYMBOL_FIELD_ENCODE(314, 0, 0), 963 /* BAM_15GBASE_X4:1:1 */ 964 PHYMOD_SYMBOL_FIELD_ENCODE(315, 1, 1), 965 /* BAM_15P75GBASE_X2:2:2 */ 966 PHYMOD_SYMBOL_FIELD_ENCODE(316, 2, 2), 967 /* BAM_16GBASE_X4:3:3 */ 968 PHYMOD_SYMBOL_FIELD_ENCODE(317, 3, 3), 969 /* BAM_20GBASE_X4_CX4:4:4 */ 970 PHYMOD_SYMBOL_FIELD_ENCODE(323, 4, 4), 971 /* BAM_20GBASE_X4:5:5 */ 972 PHYMOD_SYMBOL_FIELD_ENCODE(322, 5, 5), 973 /* BAM_20GBASE_X2:6:6 */ 974 PHYMOD_SYMBOL_FIELD_ENCODE(320, 6, 6), 975 /* BAM_20GBASE_X2_CX4:7:7 */ 976 PHYMOD_SYMBOL_FIELD_ENCODE(321, 7, 7), 977 /* BAM_21GBASE_X4:8:8 */ 978 PHYMOD_SYMBOL_FIELD_ENCODE(324, 8, 8), 979 /* BAM_25P455GBASE_X4:9:9 */ 980 PHYMOD_SYMBOL_FIELD_ENCODE(325, 9, 9), 981 /* BAM_31P5GBASE_X4:10:10 */ 982 PHYMOD_SYMBOL_FIELD_ENCODE(327, 10, 10), 983 /* BAM_32P7GBASE_X4:11:11 */ 984 PHYMOD_SYMBOL_FIELD_ENCODE(328, 11, 11), 985 /* BAM_40GBASE_X4:12:12 */ 986 PHYMOD_SYMBOL_FIELD_ENCODE(329, 12, 12), 987 /* CL72:13:13 */ 988 PHYMOD_SYMBOL_FIELD_ENCODE(465, 13, 13), 989 /* FEC:14:14 */ 990 PHYMOD_SYMBOL_FIELD_ENCODE(735, 14, 14), 991 /* HG2:15:15 */ 992 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(754, 15, 15) 993 }; 994 static uint32_t BCMI_TSCE_XGXS_AN_X4_LP_BASE_PAGE1r_fields[] = 995 { 996 /* LP_BASE_PAGE1_PAGE_DATA:0:15 */ 997 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(849, 15, 0) 998 }; 999 static uint32_t BCMI_TSCE_XGXS_AN_X4_LP_BASE_PAGE2r_fields[] = 1000 { 1001 /* LP_BASE_PAGE2_PAGE_DATA:0:15 */ 1002 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(850, 15, 0) 1003 }; 1004 static uint32_t BCMI_TSCE_XGXS_AN_X4_LP_BASE_PAGE3r_fields[] = 1005 { 1006 /* LP_BASE_PAGE3_PAGE_DATA:0:15 */ 1007 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(851, 15, 0) 1008 }; 1009 static uint32_t BCMI_TSCE_XGXS_AN_X4_LP_MP1024_UP1r_fields[] = 1010 { 1011 /* LP_MP1024_UP1_PAGE_DATA:0:15 */ 1012 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(852, 15, 0) 1013 }; 1014 static uint32_t BCMI_TSCE_XGXS_AN_X4_LP_MP1024_UP2r_fields[] = 1015 { 1016 /* LP_MP1024_UP2_PAGE_DATA:0:15 */ 1017 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(853, 15, 0) 1018 }; 1019 static uint32_t BCMI_TSCE_XGXS_AN_X4_LP_MP1024_UP3r_fields[] = 1020 { 1021 /* LP_MP1024_UP3_PAGE_DATA:0:15 */ 1022 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(854, 15, 0) 1023 }; 1024 static uint32_t BCMI_TSCE_XGXS_AN_X4_LP_MP1024_UP4r_fields[] = 1025 { 1026 /* LP_MP1024_UP4_PAGE_DATA:0:15 */ 1027 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(855, 15, 0) 1028 }; 1029 static uint32_t BCMI_TSCE_XGXS_AN_X4_LP_MP5_UP1r_fields[] = 1030 { 1031 /* LP_MP5_UP1_PAGE_DATA:0:15 */ 1032 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(856, 15, 0) 1033 }; 1034 static uint32_t BCMI_TSCE_XGXS_AN_X4_LP_MP5_UP2r_fields[] = 1035 { 1036 /* LP_MP5_UP2_PAGE_DATA:0:15 */ 1037 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(857, 15, 0) 1038 }; 1039 static uint32_t BCMI_TSCE_XGXS_AN_X4_LP_MP5_UP3r_fields[] = 1040 { 1041 /* LP_MP5_UP3_PAGE_DATA:0:15 */ 1042 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(858, 15, 0) 1043 }; 1044 static uint32_t BCMI_TSCE_XGXS_AN_X4_LP_MP5_UP4r_fields[] = 1045 { 1046 /* LP_MP5_UP4_PAGE_DATA:0:15 */ 1047 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(859, 15, 0) 1048 }; 1049 static uint32_t BCMI_TSCE_XGXS_AN_X4_LP_PAGE0r_fields[] = 1050 { 1051 /* LP_PAGE_0_PAGE_DATA:0:15 */ 1052 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(860, 15, 0) 1053 }; 1054 static uint32_t BCMI_TSCE_XGXS_AN_X4_LP_PAGE1r_fields[] = 1055 { 1056 /* LP_PAGE_1_PAGE_DATA:0:15 */ 1057 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(861, 15, 0) 1058 }; 1059 static uint32_t BCMI_TSCE_XGXS_AN_X4_LP_PAGE2r_fields[] = 1060 { 1061 /* LP_PAGE_2_PAGE_DATA:0:15 */ 1062 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(862, 15, 0) 1063 }; 1064 static uint32_t BCMI_TSCE_XGXS_AN_X4_SW_CTL_STSr_fields[] = 1065 { 1066 /* TLA_LN_SEQUENCER_FSM_STATUS1:0:7 */ 1067 PHYMOD_SYMBOL_FIELD_ENCODE(1294, 7, 0), 1068 /* PD_CL37_COMPLETED:8:8 */ 1069 PHYMOD_SYMBOL_FIELD_ENCODE(1001, 8, 8), 1070 /* LP_STATUS_VALID:13:13 */ 1071 PHYMOD_SYMBOL_FIELD_ENCODE(863, 13, 13), 1072 /* LD_CONTROL_VALID:14:14 */ 1073 PHYMOD_SYMBOL_FIELD_ENCODE(800, 14, 14), 1074 /* AN_COMPLETED_SW:15:15 */ 1075 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(203, 15, 15) 1076 }; 1077 static uint32_t BCMI_TSCE_XGXS_AN_X4_TLA_SEQUENCER_STSr_fields[] = 1078 { 1079 /* TLA_LN_SEQUENCER_FSM_STATUS:0:15 */ 1080 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1293, 15, 0) 1081 }; 1082 static uint32_t BCMI_TSCE_XGXS_CKRST_CLK_N_RST_DBG_CTLr_fields[] = 1083 { 1084 /* LN_RX_S_CLKGATE_FRC_ON:0:0 */ 1085 PHYMOD_SYMBOL_FIELD_ENCODE(821, 0, 0), 1086 /* LN_RX_S_COMCLK_SEL:1:1 */ 1087 PHYMOD_SYMBOL_FIELD_ENCODE(823, 1, 1), 1088 /* LN_RX_S_COMCLK_FRC_ON:2:2 */ 1089 PHYMOD_SYMBOL_FIELD_ENCODE(822, 2, 2), 1090 /* PMD_RX_CLK_VLD_FRC:3:3 */ 1091 PHYMOD_SYMBOL_FIELD_ENCODE(1056, 3, 3), 1092 /* PMD_RX_CLK_VLD_FRC_VAL:4:4 */ 1093 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1057, 4, 4) 1094 }; 1095 static uint32_t BCMI_TSCE_XGXS_CKRST_LN_AFE_RST_PWRDWN_CTL_CTLr_fields[] = 1096 { 1097 /* AFE_RX_PWRDN_FRC:0:0 */ 1098 PHYMOD_SYMBOL_FIELD_ENCODE(2, 0, 0), 1099 /* AFE_RX_PWRDN_FRC_VAL:1:1 */ 1100 PHYMOD_SYMBOL_FIELD_ENCODE(3, 1, 1), 1101 /* AFE_RX_RESET_FRC:2:2 */ 1102 PHYMOD_SYMBOL_FIELD_ENCODE(4, 2, 2), 1103 /* AFE_RX_RESET_FRC_VAL:3:3 */ 1104 PHYMOD_SYMBOL_FIELD_ENCODE(5, 3, 3), 1105 /* AFE_TX_PWRDN_FRC:4:4 */ 1106 PHYMOD_SYMBOL_FIELD_ENCODE(12, 4, 4), 1107 /* AFE_TX_PWRDN_FRC_VAL:5:5 */ 1108 PHYMOD_SYMBOL_FIELD_ENCODE(13, 5, 5), 1109 /* AFE_TX_RESET_FRC:6:6 */ 1110 PHYMOD_SYMBOL_FIELD_ENCODE(14, 6, 6), 1111 /* AFE_TX_RESET_FRC_VAL:7:7 */ 1112 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(15, 7, 7) 1113 }; 1114 static uint32_t BCMI_TSCE_XGXS_CKRST_LN_CLK_RST_N_PWRDWN_CTLr_fields[] = 1115 { 1116 /* LN_DP_S_RSTB:1:1 */ 1117 PHYMOD_SYMBOL_FIELD_ENCODE(817, 1, 1), 1118 /* LN_RX_S_PWRDN:2:2 */ 1119 PHYMOD_SYMBOL_FIELD_ENCODE(824, 2, 2), 1120 /* LN_TX_S_PWRDN:3:3 */ 1121 PHYMOD_SYMBOL_FIELD_ENCODE(829, 3, 3), 1122 /* AFE_SIGDET_PWRDN:4:4 */ 1123 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(6, 4, 4) 1124 }; 1125 static uint32_t BCMI_TSCE_XGXS_CKRST_LN_DBG_RST_CTLr_fields[] = 1126 { 1127 /* LN_RX_S_RSTB:0:0 */ 1128 PHYMOD_SYMBOL_FIELD_ENCODE(825, 0, 0), 1129 /* LN_RX_DP_S_RSTB:1:1 */ 1130 PHYMOD_SYMBOL_FIELD_ENCODE(819, 1, 1), 1131 /* SIGDET_DP_RSTB_EN:2:2 */ 1132 PHYMOD_SYMBOL_FIELD_ENCODE(1240, 2, 2), 1133 /* LN_TX_S_RSTB:8:8 */ 1134 PHYMOD_SYMBOL_FIELD_ENCODE(830, 8, 8), 1135 /* LN_TX_DP_S_RSTB:9:9 */ 1136 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(827, 9, 9) 1137 }; 1138 static uint32_t BCMI_TSCE_XGXS_CKRST_LN_DP_RST_ST_STSr_fields[] = 1139 { 1140 /* LANE_DP_RESET_STATE:0:2 */ 1141 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(791, 2, 0) 1142 }; 1143 static uint32_t BCMI_TSCE_XGXS_CKRST_LN_MCST_MASK_CTLr_fields[] = 1144 { 1145 /* LANE_MULTICAST_MASK_CONTROL:0:0 */ 1146 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(794, 0, 0) 1147 }; 1148 static uint32_t BCMI_TSCE_XGXS_CKRST_LN_RST_N_PWRDN_PIN_KILL_CTLr_fields[] = 1149 { 1150 /* PMD_LN_H_RSTB_PKILL:0:0 */ 1151 PHYMOD_SYMBOL_FIELD_ENCODE(1050, 0, 0), 1152 /* PMD_LN_DP_H_RSTB_PKILL:1:1 */ 1153 PHYMOD_SYMBOL_FIELD_ENCODE(1049, 1, 1), 1154 /* PMD_LN_RX_H_PWRDN_PKILL:2:2 */ 1155 PHYMOD_SYMBOL_FIELD_ENCODE(1051, 2, 2), 1156 /* PMD_LN_TX_H_PWRDN_PKILL:3:3 */ 1157 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1052, 3, 3) 1158 }; 1159 static uint32_t BCMI_TSCE_XGXS_CKRST_LN_RST_OCC_CTLr_fields[] = 1160 { 1161 /* LANE_REG_RESET_OCCURRED:0:0 */ 1162 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(795, 0, 0) 1163 }; 1164 static uint32_t BCMI_TSCE_XGXS_CKRST_LN_S_RSTB_CTLr_fields[] = 1165 { 1166 /* LN_S_RSTB:0:0 */ 1167 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(826, 0, 0) 1168 }; 1169 static uint32_t BCMI_TSCE_XGXS_CKRST_OSR_MODE_CTLr_fields[] = 1170 { 1171 /* OSR_MODE_FRC_VAL:0:3 */ 1172 PHYMOD_SYMBOL_FIELD_ENCODE(956, 3, 0), 1173 /* OSR_MODE_FRC:15:15 */ 1174 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(955, 15, 15) 1175 }; 1176 static uint32_t BCMI_TSCE_XGXS_CKRST_OSR_MODE_PIN_STSr_fields[] = 1177 { 1178 /* OSR_MODE_PIN:0:3 */ 1179 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(958, 3, 0) 1180 }; 1181 static uint32_t BCMI_TSCE_XGXS_CKRST_OSR_MODE_STSr_fields[] = 1182 { 1183 /* OSR_MODE:0:3 */ 1184 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(954, 3, 0) 1185 }; 1186 static uint32_t BCMI_TSCE_XGXS_CKRST_PMD_LN_MODE_STSr_fields[] = 1187 { 1188 /* PMD_LANE_MODE:0:15 */ 1189 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1048, 15, 0) 1190 }; 1191 static uint32_t BCMI_TSCE_XGXS_CKRST_UC_ACK_LN_CTLr_fields[] = 1192 { 1193 /* UC_ACK_LANE_CFG_DONE:0:0 */ 1194 PHYMOD_SYMBOL_FIELD_ENCODE(1420, 0, 0), 1195 /* UC_ACK_LANE_DP_RESET:1:1 */ 1196 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1421, 1, 1) 1197 }; 1198 static uint32_t BCMI_TSCE_XGXS_CL72_LNK_CTLr_fields[] = 1199 { 1200 /* LINK_CONTROL_FORCEVAL:14:14 */ 1201 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(806, 14, 14) 1202 }; 1203 static uint32_t BCMI_TSCE_XGXS_CL72_RXBASE_R_LD_STS_REPr_fields[] = 1204 { 1205 /* CL72_IEEE_LP_STATUS_REPORT:0:15 */ 1206 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(483, 15, 0) 1207 }; 1208 static uint32_t BCMI_TSCE_XGXS_CL72_RXCL72_LP_CTL_PAGEr_fields[] = 1209 { 1210 /* CL72_LP_CONTROL_PAGE:0:15 */ 1211 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(494, 15, 0) 1212 }; 1213 static uint32_t BCMI_TSCE_XGXS_CL72_RXCL72_STS1r_fields[] = 1214 { 1215 /* CL72_SIGNAL_DETECT:0:0 */ 1216 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(501, 0, 0) 1217 }; 1218 static uint32_t BCMI_TSCE_XGXS_CL72_RXDBG2r_fields[] = 1219 { 1220 /* CL72_GOOD_MARKER_CNT:0:1 */ 1221 PHYMOD_SYMBOL_FIELD_ENCODE(478, 1, 0), 1222 /* CL72_BAD_MARKER_CNT:2:4 */ 1223 PHYMOD_SYMBOL_FIELD_ENCODE(466, 4, 2), 1224 /* CL72_DME_CELL_BOUNDARY_CHK:7:7 */ 1225 PHYMOD_SYMBOL_FIELD_ENCODE(471, 7, 7), 1226 /* CL72_CTRL_FRAME_DLY:8:11 */ 1227 PHYMOD_SYMBOL_FIELD_ENCODE(468, 11, 8), 1228 /* CL72_STRICT_DME_CHK:12:12 */ 1229 PHYMOD_SYMBOL_FIELD_ENCODE(503, 12, 12), 1230 /* CL72_STRICT_MARKER_CHK:13:13 */ 1231 PHYMOD_SYMBOL_FIELD_ENCODE(504, 13, 13), 1232 /* CL72_PPM_OFFSET_EN:14:14 */ 1233 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(496, 14, 14) 1234 }; 1235 static uint32_t BCMI_TSCE_XGXS_CL72_RXMISC1_CTLr_fields[] = 1236 { 1237 /* CL72_TR_COARSE_LOCK:1:1 */ 1238 PHYMOD_SYMBOL_FIELD_ENCODE(507, 1, 1), 1239 /* CL72_RX_DP_LN_CLK_EN:2:2 */ 1240 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(499, 2, 2) 1241 }; 1242 static uint32_t BCMI_TSCE_XGXS_CL72_RXRCVD_STSr_fields[] = 1243 { 1244 /* CL72_RCVD_STATUS_PAGE:0:15 */ 1245 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(497, 15, 0) 1246 }; 1247 static uint32_t BCMI_TSCE_XGXS_CL72_TXBASE_R_LD_COEFF_UPDr_fields[] = 1248 { 1249 /* CL72_IEEE_LD_COEFF_UPDATE:0:15 */ 1250 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(480, 15, 0) 1251 }; 1252 static uint32_t BCMI_TSCE_XGXS_CL72_TXBASE_R_LD_STS_REPr_fields[] = 1253 { 1254 /* CL72_IEEE_LD_STATUS_REPORT:0:15 */ 1255 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(481, 15, 0) 1256 }; 1257 static uint32_t BCMI_TSCE_XGXS_CL72_TXBASE_R_LP_COEFF_UPDr_fields[] = 1258 { 1259 /* CL72_IEEE_LP_COEFF_UPDATE:0:15 */ 1260 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(482, 15, 0) 1261 }; 1262 static uint32_t BCMI_TSCE_XGXS_CL72_TXBASE_R_PMD_CTLr_fields[] = 1263 { 1264 /* CL72_IEEE_RESTART_TRAINING:0:0 */ 1265 PHYMOD_SYMBOL_FIELD_ENCODE(485, 0, 0), 1266 /* CL72_IEEE_TRAINING_ENABLE:1:1 */ 1267 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(486, 1, 1) 1268 }; 1269 static uint32_t BCMI_TSCE_XGXS_CL72_TXBASE_R_PMD_STSr_fields[] = 1270 { 1271 /* CL72_IEEE_RECEIVER_STATUS:0:0 */ 1272 PHYMOD_SYMBOL_FIELD_ENCODE(484, 0, 0), 1273 /* CL72_IEEE_FRAME_LOCK:1:1 */ 1274 PHYMOD_SYMBOL_FIELD_ENCODE(479, 1, 1), 1275 /* CL72_IEEE_TRAINING_STATUS:2:2 */ 1276 PHYMOD_SYMBOL_FIELD_ENCODE(488, 2, 2), 1277 /* CL72_IEEE_TRAINING_FAILURE:3:3 */ 1278 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(487, 3, 3) 1279 }; 1280 static uint32_t BCMI_TSCE_XGXS_CL72_TXCL72_LD_STS_PAGEr_fields[] = 1281 { 1282 /* CL72_LD_STATUS_PAGE:0:15 */ 1283 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(491, 15, 0) 1284 }; 1285 static uint32_t BCMI_TSCE_XGXS_CL72_TXCL72_LD_XMT_STS_PAGE_OVRRr_fields[] = 1286 { 1287 /* CL72_OVERRIDE_LD_STATUS_PAGE:0:15 */ 1288 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(495, 15, 0) 1289 }; 1290 static uint32_t BCMI_TSCE_XGXS_CL72_TXCL72_READY_FOR_CMDr_fields[] = 1291 { 1292 /* CL72_READY_FOR_CMD:0:0 */ 1293 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(498, 0, 0) 1294 }; 1295 static uint32_t BCMI_TSCE_XGXS_CL72_TXCL72_TX_DBG_STSr_fields[] = 1296 { 1297 /* CL72_LD_COEFF_CMD_HIST:0:10 */ 1298 PHYMOD_SYMBOL_FIELD_ENCODE(490, 10, 0), 1299 /* CL72_FRAME_LOCK_LH:11:11 */ 1300 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(476, 11, 11) 1301 }; 1302 static uint32_t BCMI_TSCE_XGXS_CL72_TXC_DBG1r_fields[] = 1303 { 1304 /* MAIN_TAP_MIN_VAL:0:6 */ 1305 PHYMOD_SYMBOL_FIELD_ENCODE(872, 6, 0), 1306 /* TAP_SUM_MAX_VAL:7:14 */ 1307 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1280, 14, 7) 1308 }; 1309 static uint32_t BCMI_TSCE_XGXS_CL72_TXC_MAX_WAIT_TMRr_fields[] = 1310 { 1311 /* MAX_WAIT_TIMER_PERIOD:0:15 */ 1312 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(874, 15, 0) 1313 }; 1314 static uint32_t BCMI_TSCE_XGXS_CL72_TXC_TAP_LIMIT_CTL1r_fields[] = 1315 { 1316 /* PRE_TAP_LIMIT:0:4 */ 1317 PHYMOD_SYMBOL_FIELD_ENCODE(1088, 4, 0), 1318 /* POST_TAP_LIMIT:5:10 */ 1319 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1065, 10, 5) 1320 }; 1321 static uint32_t BCMI_TSCE_XGXS_CL72_TXC_TAP_LIMIT_CTL2r_fields[] = 1322 { 1323 /* MAIN_TAP_LIMIT:0:6 */ 1324 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(871, 6, 0) 1325 }; 1326 static uint32_t BCMI_TSCE_XGXS_CL72_TXC_TAP_PRESET_CTLr_fields[] = 1327 { 1328 /* POST_TAP_PRESET_VAL:0:5 */ 1329 PHYMOD_SYMBOL_FIELD_ENCODE(1066, 5, 0), 1330 /* PRE_TAP_PRESET_VAL:6:10 */ 1331 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1089, 10, 6) 1332 }; 1333 static uint32_t BCMI_TSCE_XGXS_CL72_TXC_WAIT_TMRr_fields[] = 1334 { 1335 /* WAIT_CNTR_LIMIT:0:8 */ 1336 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1453, 8, 0) 1337 }; 1338 static uint32_t BCMI_TSCE_XGXS_CL72_TXDBG3r_fields[] = 1339 { 1340 /* CL72_BRK_RING_OSC:0:0 */ 1341 PHYMOD_SYMBOL_FIELD_ENCODE(467, 0, 0), 1342 /* CL72_FRAME_LOCK_RDY_FOR_CMD_EN:1:1 */ 1343 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(477, 1, 1) 1344 }; 1345 static uint32_t BCMI_TSCE_XGXS_CL72_TXKR_DFLT_CTL1r_fields[] = 1346 { 1347 /* CL72_TX_FIR_TAP_PRE_KR_INIT_VAL:0:4 */ 1348 PHYMOD_SYMBOL_FIELD_ENCODE(511, 4, 0), 1349 /* CL72_TX_FIR_TAP_POST_KR_INIT_VAL:5:10 */ 1350 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(510, 10, 5) 1351 }; 1352 static uint32_t BCMI_TSCE_XGXS_CL72_TXKR_DFLT_CTL2r_fields[] = 1353 { 1354 /* CL72_TX_FIR_TAP_MAIN_KR_INIT_VAL:0:6 */ 1355 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(509, 6, 0) 1356 }; 1357 static uint32_t BCMI_TSCE_XGXS_CL72_TXMISC2_CTLr_fields[] = 1358 { 1359 /* CL72_RX_TRAINED:0:0 */ 1360 PHYMOD_SYMBOL_FIELD_ENCODE(500, 0, 0), 1361 /* CL72_SIGNAL_DET_FRC:1:1 */ 1362 PHYMOD_SYMBOL_FIELD_ENCODE(502, 1, 1), 1363 /* CL72_TX_DP_LN_CLK_EN:2:2 */ 1364 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(508, 2, 2) 1365 }; 1366 static uint32_t BCMI_TSCE_XGXS_CL72_TXMISC_COEFF_CTLr_fields[] = 1367 { 1368 /* CL72_INC_DEC_VAL_SEL:0:1 */ 1369 PHYMOD_SYMBOL_FIELD_ENCODE(489, 1, 0), 1370 /* CL72_TAP_V2_VAL:2:7 */ 1371 PHYMOD_SYMBOL_FIELD_ENCODE(505, 7, 2), 1372 /* CL72_V2_CONSTRAINT_DIS:8:8 */ 1373 PHYMOD_SYMBOL_FIELD_ENCODE(512, 8, 8), 1374 /* CL72_LD_XMT_STATUS_LOAD:9:9 */ 1375 PHYMOD_SYMBOL_FIELD_ENCODE(492, 9, 9), 1376 /* CL72_LD_XMT_STATUS_OVERRIDE:10:10 */ 1377 PHYMOD_SYMBOL_FIELD_ENCODE(493, 10, 10), 1378 /* CL72_DIS_LP_COEFF_UPDATES_TO_LD:11:11 */ 1379 PHYMOD_SYMBOL_FIELD_ENCODE(469, 11, 11), 1380 /* CL72_DOUBLE_CMD_EN:12:12 */ 1381 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(472, 12, 12) 1382 }; 1383 static uint32_t BCMI_TSCE_XGXS_CL72_TXPCS_INTERFACE_CTLr_fields[] = 1384 { 1385 /* CL72_DIS_MAX_WAIT_TIMER:0:0 */ 1386 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(470, 0, 0) 1387 }; 1388 static uint32_t BCMI_TSCE_XGXS_CL72_TXXMT_UPDr_fields[] = 1389 { 1390 /* CL72_XMT_UPDATE_PAGE:0:15 */ 1391 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(513, 15, 0) 1392 }; 1393 static uint32_t BCMI_TSCE_XGXS_CL82_BER_HO_STSr_fields[] = 1394 { 1395 /* BER_HO:0:15 */ 1396 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(341, 15, 0) 1397 }; 1398 static uint32_t BCMI_TSCE_XGXS_CL82_LANES_1_0_AM_BYTE2r_fields[] = 1399 { 1400 /* LANE_0_AM_2:0:7 */ 1401 PHYMOD_SYMBOL_FIELD_ENCODE(780, 7, 0), 1402 /* LANE_1_AM_2:8:15 */ 1403 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(782, 15, 8) 1404 }; 1405 static uint32_t BCMI_TSCE_XGXS_CL82_LANES_3_2_AM_BYTE2r_fields[] = 1406 { 1407 /* LANE_2_AM_2:0:7 */ 1408 PHYMOD_SYMBOL_FIELD_ENCODE(784, 7, 0), 1409 /* LANE_3_AM_2:8:15 */ 1410 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(786, 15, 8) 1411 }; 1412 static uint32_t BCMI_TSCE_XGXS_CL82_LN_0_AM_BYTE10r_fields[] = 1413 { 1414 /* LANE_0_AM_1_0:0:15 */ 1415 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(779, 15, 0) 1416 }; 1417 static uint32_t BCMI_TSCE_XGXS_CL82_LN_1_AM_BYTE10r_fields[] = 1418 { 1419 /* LANE_1_AM_1_0:0:15 */ 1420 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(781, 15, 0) 1421 }; 1422 static uint32_t BCMI_TSCE_XGXS_CL82_LN_2_AM_BYTE10r_fields[] = 1423 { 1424 /* LANE_2_AM_1_0:0:15 */ 1425 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(783, 15, 0) 1426 }; 1427 static uint32_t BCMI_TSCE_XGXS_CL82_LN_3_AM_BYTE10r_fields[] = 1428 { 1429 /* LANE_3_AM_1_0:0:15 */ 1430 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(785, 15, 0) 1431 }; 1432 static uint32_t BCMI_TSCE_XGXS_CL82_PCS_ERRED_BLKS_HOr_fields[] = 1433 { 1434 /* ERRORED_BLOCKS_HO:0:13 */ 1435 PHYMOD_SYMBOL_FIELD_ENCODE(722, 13, 0), 1436 /* ERRORED_BLOCKS_HO_PRESENT:15:15 */ 1437 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(723, 15, 15) 1438 }; 1439 static uint32_t BCMI_TSCE_XGXS_CL82_RX_AM_TMRr_fields[] = 1440 { 1441 /* AM_TIMER_INIT_RX_VAL:0:15 */ 1442 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(199, 15, 0) 1443 }; 1444 static uint32_t BCMI_TSCE_XGXS_CL82_RX_DECR_STSr_fields[] = 1445 { 1446 /* RXSM_STATE:0:6 */ 1447 PHYMOD_SYMBOL_FIELD_ENCODE(1170, 6, 0), 1448 /* R_TYPE_CODED:7:12 */ 1449 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1201, 12, 7) 1450 }; 1451 static uint32_t BCMI_TSCE_XGXS_CL82_RX_DESKEW_BER_STSr_fields[] = 1452 { 1453 /* BERMON_STATE:0:4 */ 1454 PHYMOD_SYMBOL_FIELD_ENCODE(339, 4, 0), 1455 /* LBERMON_STATE:6:10 */ 1456 PHYMOD_SYMBOL_FIELD_ENCODE(799, 10, 6), 1457 /* DESKEW_HIS_STATE:12:13 */ 1458 PHYMOD_SYMBOL_FIELD_ENCODE(603, 13, 12), 1459 /* DESKEW_STATE:14:15 */ 1460 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(604, 15, 14) 1461 }; 1462 static uint32_t BCMI_TSCE_XGXS_DIG_CORE_DP_RST_ST_STSr_fields[] = 1463 { 1464 /* CORE_DP_RESET_STATE:0:2 */ 1465 PHYMOD_SYMBOL_FIELD_ENCODE(562, 2, 0), 1466 /* LANE_RESET_RELEASED_INDEX:8:12 */ 1467 PHYMOD_SYMBOL_FIELD_ENCODE(797, 12, 8), 1468 /* LANE_RESET_RELEASED:14:14 */ 1469 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(796, 14, 14) 1470 }; 1471 static uint32_t BCMI_TSCE_XGXS_DIG_CORE_MCST_MASK_CTLr_fields[] = 1472 { 1473 /* CORE_MULTICAST_MASK_CONTROL:0:3 */ 1474 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(566, 3, 0) 1475 }; 1476 static uint32_t BCMI_TSCE_XGXS_DIG_CORE_RST_OCC_CTLr_fields[] = 1477 { 1478 /* CORE_REG_RESET_OCCURRED:0:0 */ 1479 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(567, 0, 0) 1480 }; 1481 static uint32_t BCMI_TSCE_XGXS_DIG_CTL1000X2r_fields[] = 1482 { 1483 /* DISABLE_REMOTE_FAULT_REPORTING:4:4 */ 1484 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(687, 4, 4) 1485 }; 1486 static uint32_t BCMI_TSCE_XGXS_DIG_LN_ADDR_2_3r_fields[] = 1487 { 1488 /* LANE_ADDR_2:0:4 */ 1489 PHYMOD_SYMBOL_FIELD_ENCODE(789, 4, 0), 1490 /* LANE_ADDR_3:8:12 */ 1491 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(790, 12, 8) 1492 }; 1493 static uint32_t BCMI_TSCE_XGXS_DIG_PMD_CORE_MODE_STSr_fields[] = 1494 { 1495 /* PMD_CORE_MODE:0:15 */ 1496 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1047, 15, 0) 1497 }; 1498 static uint32_t BCMI_TSCE_XGXS_DIG_REVID0r_fields[] = 1499 { 1500 /* REVID_MODEL:0:5 */ 1501 PHYMOD_SYMBOL_FIELD_ENCODE(1134, 5, 0), 1502 /* REVID_PROCESS:6:8 */ 1503 PHYMOD_SYMBOL_FIELD_ENCODE(1137, 8, 6), 1504 /* REVID_BONDING:9:10 */ 1505 PHYMOD_SYMBOL_FIELD_ENCODE(1128, 10, 9), 1506 /* REVID_REV_NUMBER:11:13 */ 1507 PHYMOD_SYMBOL_FIELD_ENCODE(1139, 13, 11), 1508 /* REVID_REV_LETTER:14:15 */ 1509 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1138, 15, 14) 1510 }; 1511 static uint32_t BCMI_TSCE_XGXS_DIG_REVID1r_fields[] = 1512 { 1513 /* REVID_EEE:0:0 */ 1514 PHYMOD_SYMBOL_FIELD_ENCODE(1130, 0, 0), 1515 /* REVID_LLP:1:1 */ 1516 PHYMOD_SYMBOL_FIELD_ENCODE(1131, 1, 1), 1517 /* REVID_PIR:2:2 */ 1518 PHYMOD_SYMBOL_FIELD_ENCODE(1136, 2, 2), 1519 /* REVID_CL72:3:3 */ 1520 PHYMOD_SYMBOL_FIELD_ENCODE(1129, 3, 3), 1521 /* REVID_MICRO:4:4 */ 1522 PHYMOD_SYMBOL_FIELD_ENCODE(1133, 4, 4), 1523 /* REVID_MDIO:5:5 */ 1524 PHYMOD_SYMBOL_FIELD_ENCODE(1132, 5, 5), 1525 /* REVID_MULTIPLICITY:12:15 */ 1526 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1135, 15, 12) 1527 }; 1528 static uint32_t BCMI_TSCE_XGXS_DIG_REVID2r_fields[] = 1529 { 1530 /* REVID2:0:3 */ 1531 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1127, 3, 0) 1532 }; 1533 static uint32_t BCMI_TSCE_XGXS_DIG_RST_CTL_CORE_DPr_fields[] = 1534 { 1535 /* PMD_CORE_DP_H_RSTB_PKILL:1:1 */ 1536 PHYMOD_SYMBOL_FIELD_ENCODE(1046, 1, 1), 1537 /* SUP_RST_SEQ_FRC_VAL:3:3 */ 1538 PHYMOD_SYMBOL_FIELD_ENCODE(1265, 3, 3), 1539 /* SUP_RST_SEQ_FRC:4:4 */ 1540 PHYMOD_SYMBOL_FIELD_ENCODE(1264, 4, 4), 1541 /* PMD_MDIO_TRANS_PKILL:5:5 */ 1542 PHYMOD_SYMBOL_FIELD_ENCODE(1055, 5, 5), 1543 /* PMD_TX_CLK_VLD_FRC:7:7 */ 1544 PHYMOD_SYMBOL_FIELD_ENCODE(1060, 7, 7), 1545 /* PMD_TX_CLK_VLD_FRC_VAL:8:8 */ 1546 PHYMOD_SYMBOL_FIELD_ENCODE(1061, 8, 8), 1547 /* TX_S_COMCLK_SEL:9:9 */ 1548 PHYMOD_SYMBOL_FIELD_ENCODE(1411, 9, 9), 1549 /* TX_S_COMCLK_FRC_ON:10:10 */ 1550 PHYMOD_SYMBOL_FIELD_ENCODE(1410, 10, 10), 1551 /* TX_S_CLKGATE_FRC_ON:11:11 */ 1552 PHYMOD_SYMBOL_FIELD_ENCODE(1409, 11, 11), 1553 /* AFE_S_PLL_RESET_FRC_VAL:12:12 */ 1554 PHYMOD_SYMBOL_FIELD_ENCODE(11, 12, 12), 1555 /* AFE_S_PLL_RESET_FRC:13:13 */ 1556 PHYMOD_SYMBOL_FIELD_ENCODE(10, 13, 13), 1557 /* TX_PI_LOOP_FILTER_STABLE:14:14 */ 1558 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1390, 14, 14) 1559 }; 1560 static uint32_t BCMI_TSCE_XGXS_DIG_RST_CTL_PMDr_fields[] = 1561 { 1562 /* CORE_S_RSTB:0:0 */ 1563 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(568, 0, 0) 1564 }; 1565 static uint32_t BCMI_TSCE_XGXS_DIG_RST_SEQ_TMR_CTLr_fields[] = 1566 { 1567 /* RST_SEQ_TIMER:0:2 */ 1568 PHYMOD_SYMBOL_FIELD_ENCODE(1163, 2, 0), 1569 /* PWRDN_SEQ_TIMER:8:10 */ 1570 PHYMOD_SYMBOL_FIELD_ENCODE(1096, 10, 8), 1571 /* RST_SEQ_DIS_FLT_MODE:14:15 */ 1572 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1162, 15, 14) 1573 }; 1574 static uint32_t BCMI_TSCE_XGXS_DIG_SPARE0r_fields[] = 1575 { 1576 /* SPARE0:0:7 */ 1577 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1259, 7, 0) 1578 }; 1579 static uint32_t BCMI_TSCE_XGXS_DIG_SPARE1r_fields[] = 1580 { 1581 /* SPARE1:0:7 */ 1582 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1260, 7, 0) 1583 }; 1584 static uint32_t BCMI_TSCE_XGXS_DIG_TOP_USER_CTL0r_fields[] = 1585 { 1586 /* HEARTBEAT_COUNT_1US:0:9 */ 1587 PHYMOD_SYMBOL_FIELD_ENCODE(753, 9, 0), 1588 /* CORE_DP_S_RSTB:13:13 */ 1589 PHYMOD_SYMBOL_FIELD_ENCODE(563, 13, 13), 1590 /* AFE_S_PLL_PWRDN:14:14 */ 1591 PHYMOD_SYMBOL_FIELD_ENCODE(9, 14, 14), 1592 /* UC_ACTIVE:15:15 */ 1593 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1422, 15, 15) 1594 }; 1595 static uint32_t BCMI_TSCE_XGXS_DIG_TX_LN_MAP_0_1_2r_fields[] = 1596 { 1597 /* TX_LANE_MAP_0:0:4 */ 1598 PHYMOD_SYMBOL_FIELD_ENCODE(1359, 4, 0), 1599 /* TX_LANE_MAP_1:5:9 */ 1600 PHYMOD_SYMBOL_FIELD_ENCODE(1360, 9, 5), 1601 /* TX_LANE_MAP_2:10:14 */ 1602 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1361, 14, 10) 1603 }; 1604 static uint32_t BCMI_TSCE_XGXS_DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r_fields[] = 1605 { 1606 /* TX_LANE_MAP_3:0:4 */ 1607 PHYMOD_SYMBOL_FIELD_ENCODE(1362, 4, 0), 1608 /* LANE_ADDR_0:5:9 */ 1609 PHYMOD_SYMBOL_FIELD_ENCODE(787, 9, 5), 1610 /* LANE_ADDR_1:10:14 */ 1611 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(788, 14, 10) 1612 }; 1613 static uint32_t BCMI_TSCE_XGXS_DIG_UC_ACK_CORE_CTLr_fields[] = 1614 { 1615 /* UC_ACK_CORE_CFG_DONE:0:0 */ 1616 PHYMOD_SYMBOL_FIELD_ENCODE(1414, 0, 0), 1617 /* UC_ACK_CORE_DP_RESET:1:1 */ 1618 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1415, 1, 1) 1619 }; 1620 static uint32_t BCMI_TSCE_XGXS_DSC_CDR_CTL0r_fields[] = 1621 { 1622 /* CDR_PHASE_SAT_CTRL:0:0 */ 1623 PHYMOD_SYMBOL_FIELD_ENCODE(389, 0, 0), 1624 /* BR_PD_EN:1:1 */ 1625 PHYMOD_SYMBOL_FIELD_ENCODE(349, 1, 1), 1626 /* CDR_FREQ_EN:2:2 */ 1627 PHYMOD_SYMBOL_FIELD_ENCODE(377, 2, 2), 1628 /* CDR_INTEG_REG_CLR:4:4 */ 1629 PHYMOD_SYMBOL_FIELD_ENCODE(383, 4, 4), 1630 /* CDR_PHASE_ERR_FRZ:5:5 */ 1631 PHYMOD_SYMBOL_FIELD_ENCODE(388, 5, 5), 1632 /* CDR_INTEG_SAT_SEL:6:6 */ 1633 PHYMOD_SYMBOL_FIELD_ENCODE(384, 6, 6), 1634 /* CDR_FREQ_OVERRIDE_EN:7:7 */ 1635 PHYMOD_SYMBOL_FIELD_ENCODE(378, 7, 7), 1636 /* CDR_LM_THR_SEL:8:10 */ 1637 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(386, 10, 8) 1638 }; 1639 static uint32_t BCMI_TSCE_XGXS_DSC_CDR_CTL1r_fields[] = 1640 { 1641 /* CDR_FREQ_OVERRIDE_VAL:0:15 */ 1642 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(379, 15, 0) 1643 }; 1644 static uint32_t BCMI_TSCE_XGXS_DSC_CDR_CTL2r_fields[] = 1645 { 1646 /* CDR_ZERO_POLARITY:0:0 */ 1647 PHYMOD_SYMBOL_FIELD_ENCODE(392, 0, 0), 1648 /* PHASE_ERR_OFFSET_MULT_2:1:1 */ 1649 PHYMOD_SYMBOL_FIELD_ENCODE(1015, 1, 1), 1650 /* PATTERN_SEL:4:7 */ 1651 PHYMOD_SYMBOL_FIELD_ENCODE(973, 7, 4), 1652 /* OSX2P_PHERR_GAIN:8:9 */ 1653 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(959, 9, 8) 1654 }; 1655 static uint32_t BCMI_TSCE_XGXS_DSC_CDR_STS_INTEGr_fields[] = 1656 { 1657 /* CDR_INTEG_REG:0:15 */ 1658 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(382, 15, 0) 1659 }; 1660 static uint32_t BCMI_TSCE_XGXS_DSC_CDR_STS_PHASE_ERRr_fields[] = 1661 { 1662 /* CDR_PHASE_ERR:0:4 */ 1663 PHYMOD_SYMBOL_FIELD_ENCODE(387, 4, 0), 1664 /* CDR_LM_OUTOFLOCK:8:8 */ 1665 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(385, 8, 8) 1666 }; 1667 static uint32_t BCMI_TSCE_XGXS_DSC_CTLr_fields[] = 1668 { 1669 /* PD_CH_P1:0:0 */ 1670 PHYMOD_SYMBOL_FIELD_ENCODE(1000, 0, 0), 1671 /* OFFSET_PD:1:1 */ 1672 PHYMOD_SYMBOL_FIELD_ENCODE(953, 1, 1), 1673 /* EN_HGAIN:2:2 */ 1674 PHYMOD_SYMBOL_FIELD_ENCODE(720, 2, 2), 1675 /* P1_THRESH_SEL:3:3 */ 1676 PHYMOD_SYMBOL_FIELD_ENCODE(972, 3, 3), 1677 /* M1_THRESH_ZERO:4:4 */ 1678 PHYMOD_SYMBOL_FIELD_ENCODE(868, 4, 4), 1679 /* M1_THRESH_SEL:5:6 */ 1680 PHYMOD_SYMBOL_FIELD_ENCODE(867, 6, 5), 1681 /* PF_HIZ:7:7 */ 1682 PHYMOD_SYMBOL_FIELD_ENCODE(1012, 7, 7), 1683 /* EN_DFE_CLK:8:8 */ 1684 PHYMOD_SYMBOL_FIELD_ENCODE(719, 8, 8), 1685 /* OFFSET_FASTACQ:9:9 */ 1686 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(952, 9, 9) 1687 }; 1688 static uint32_t BCMI_TSCE_XGXS_DSC_DC_OFFSr_fields[] = 1689 { 1690 /* DC_OFFSET:0:6 */ 1691 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(583, 6, 0) 1692 }; 1693 static uint32_t BCMI_TSCE_XGXS_DSC_DFE_1_CTLr_fields[] = 1694 { 1695 /* DFE_1_ACC_CLR:0:0 */ 1696 PHYMOD_SYMBOL_FIELD_ENCODE(609, 0, 0), 1697 /* DFE_1_CMN_ONLY:1:1 */ 1698 PHYMOD_SYMBOL_FIELD_ENCODE(611, 1, 1), 1699 /* DFE_1_INV_P1:8:8 */ 1700 PHYMOD_SYMBOL_FIELD_ENCODE(618, 8, 8), 1701 /* DFE_1_INV_M1:9:9 */ 1702 PHYMOD_SYMBOL_FIELD_ENCODE(617, 9, 9), 1703 /* DFE_1_ERR_GAIN:10:11 */ 1704 PHYMOD_SYMBOL_FIELD_ENCODE(614, 11, 10), 1705 /* DFE_1_GRADIENT_INVERT:12:12 */ 1706 PHYMOD_SYMBOL_FIELD_ENCODE(616, 12, 12), 1707 /* DFE_1_ERR_SEL:13:14 */ 1708 PHYMOD_SYMBOL_FIELD_ENCODE(615, 14, 13), 1709 /* DFE_1_EN:15:15 */ 1710 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(613, 15, 15) 1711 }; 1712 static uint32_t BCMI_TSCE_XGXS_DSC_DFE_1_PAT_CTLr_fields[] = 1713 { 1714 /* DFE_1_PATTERN:0:5 */ 1715 PHYMOD_SYMBOL_FIELD_ENCODE(620, 5, 0), 1716 /* DFE_1_PATTERN_BIT_EN:8:13 */ 1717 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(621, 13, 8) 1718 }; 1719 static uint32_t BCMI_TSCE_XGXS_DSC_DFE_1_STSr_fields[] = 1720 { 1721 /* DFE_1_CMN:0:5 */ 1722 PHYMOD_SYMBOL_FIELD_ENCODE(610, 5, 0), 1723 /* DFE_1_O:8:10 */ 1724 PHYMOD_SYMBOL_FIELD_ENCODE(619, 10, 8), 1725 /* DFE_1_E:11:13 */ 1726 PHYMOD_SYMBOL_FIELD_ENCODE(612, 13, 11), 1727 /* DFE_1_WANTS_NEGATIVE:15:15 */ 1728 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(622, 15, 15) 1729 }; 1730 static uint32_t BCMI_TSCE_XGXS_DSC_DFE_2_CTLr_fields[] = 1731 { 1732 /* DFE_2_ACC_CLR:0:0 */ 1733 PHYMOD_SYMBOL_FIELD_ENCODE(623, 0, 0), 1734 /* DFE_2_CMN_ONLY:1:1 */ 1735 PHYMOD_SYMBOL_FIELD_ENCODE(625, 1, 1), 1736 /* DFE_2_INV_P1:8:8 */ 1737 PHYMOD_SYMBOL_FIELD_ENCODE(632, 8, 8), 1738 /* DFE_2_INV_M1:9:9 */ 1739 PHYMOD_SYMBOL_FIELD_ENCODE(631, 9, 9), 1740 /* DFE_2_ERR_GAIN:10:11 */ 1741 PHYMOD_SYMBOL_FIELD_ENCODE(628, 11, 10), 1742 /* DFE_2_GRADIENT_INVERT:12:12 */ 1743 PHYMOD_SYMBOL_FIELD_ENCODE(630, 12, 12), 1744 /* DFE_2_ERR_SEL:13:14 */ 1745 PHYMOD_SYMBOL_FIELD_ENCODE(629, 14, 13), 1746 /* DFE_2_EN:15:15 */ 1747 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(627, 15, 15) 1748 }; 1749 static uint32_t BCMI_TSCE_XGXS_DSC_DFE_2_PAT_CTLr_fields[] = 1750 { 1751 /* DFE_2_PATTERN:0:5 */ 1752 PHYMOD_SYMBOL_FIELD_ENCODE(634, 5, 0), 1753 /* DFE_2_PATTERN_BIT_EN:8:13 */ 1754 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(635, 13, 8) 1755 }; 1756 static uint32_t BCMI_TSCE_XGXS_DSC_DFE_2_STSr_fields[] = 1757 { 1758 /* DFE_2_CMN:0:4 */ 1759 PHYMOD_SYMBOL_FIELD_ENCODE(624, 4, 0), 1760 /* DFE_2_SO:5:5 */ 1761 PHYMOD_SYMBOL_FIELD_ENCODE(637, 5, 5), 1762 /* DFE_2_SE:6:6 */ 1763 PHYMOD_SYMBOL_FIELD_ENCODE(636, 6, 6), 1764 /* DFE_2_O:8:10 */ 1765 PHYMOD_SYMBOL_FIELD_ENCODE(633, 10, 8), 1766 /* DFE_2_E:11:13 */ 1767 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(626, 13, 11) 1768 }; 1769 static uint32_t BCMI_TSCE_XGXS_DSC_DFE_3_4_5_STSr_fields[] = 1770 { 1771 /* DFE_3_CMN:0:5 */ 1772 PHYMOD_SYMBOL_FIELD_ENCODE(639, 5, 0), 1773 /* DFE_4_CMN:6:10 */ 1774 PHYMOD_SYMBOL_FIELD_ENCODE(649, 10, 6), 1775 /* DFE_5_CMN:11:15 */ 1776 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(659, 15, 11) 1777 }; 1778 static uint32_t BCMI_TSCE_XGXS_DSC_DFE_3_CTLr_fields[] = 1779 { 1780 /* DFE_3_ACC_CLR:0:0 */ 1781 PHYMOD_SYMBOL_FIELD_ENCODE(638, 0, 0), 1782 /* DFE_3_INV_P1:8:8 */ 1783 PHYMOD_SYMBOL_FIELD_ENCODE(645, 8, 8), 1784 /* DFE_3_INV_M1:9:9 */ 1785 PHYMOD_SYMBOL_FIELD_ENCODE(644, 9, 9), 1786 /* DFE_3_ERR_GAIN:10:11 */ 1787 PHYMOD_SYMBOL_FIELD_ENCODE(641, 11, 10), 1788 /* DFE_3_GRADIENT_INVERT:12:12 */ 1789 PHYMOD_SYMBOL_FIELD_ENCODE(643, 12, 12), 1790 /* DFE_3_ERR_SEL:13:14 */ 1791 PHYMOD_SYMBOL_FIELD_ENCODE(642, 14, 13), 1792 /* DFE_3_EN:15:15 */ 1793 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(640, 15, 15) 1794 }; 1795 static uint32_t BCMI_TSCE_XGXS_DSC_DFE_3_PAT_CTLr_fields[] = 1796 { 1797 /* DFE_3_PATTERN:0:5 */ 1798 PHYMOD_SYMBOL_FIELD_ENCODE(646, 5, 0), 1799 /* DFE_3_PATTERN_BIT_EN:8:13 */ 1800 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(647, 13, 8) 1801 }; 1802 static uint32_t BCMI_TSCE_XGXS_DSC_DFE_4_CTLr_fields[] = 1803 { 1804 /* DFE_4_ACC_CLR:0:0 */ 1805 PHYMOD_SYMBOL_FIELD_ENCODE(648, 0, 0), 1806 /* DFE_4_INV_P1:8:8 */ 1807 PHYMOD_SYMBOL_FIELD_ENCODE(655, 8, 8), 1808 /* DFE_4_INV_M1:9:9 */ 1809 PHYMOD_SYMBOL_FIELD_ENCODE(654, 9, 9), 1810 /* DFE_4_ERR_GAIN:10:11 */ 1811 PHYMOD_SYMBOL_FIELD_ENCODE(651, 11, 10), 1812 /* DFE_4_GRADIENT_INVERT:12:12 */ 1813 PHYMOD_SYMBOL_FIELD_ENCODE(653, 12, 12), 1814 /* DFE_4_ERR_SEL:13:14 */ 1815 PHYMOD_SYMBOL_FIELD_ENCODE(652, 14, 13), 1816 /* DFE_4_EN:15:15 */ 1817 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(650, 15, 15) 1818 }; 1819 static uint32_t BCMI_TSCE_XGXS_DSC_DFE_4_PAT_CTLr_fields[] = 1820 { 1821 /* DFE_4_PATTERN:0:5 */ 1822 PHYMOD_SYMBOL_FIELD_ENCODE(656, 5, 0), 1823 /* DFE_4_PATTERN_BIT_EN:8:13 */ 1824 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(657, 13, 8) 1825 }; 1826 static uint32_t BCMI_TSCE_XGXS_DSC_DFE_5_CTLr_fields[] = 1827 { 1828 /* DFE_5_ACC_CLR:0:0 */ 1829 PHYMOD_SYMBOL_FIELD_ENCODE(658, 0, 0), 1830 /* DFE_5_INV_P1:8:8 */ 1831 PHYMOD_SYMBOL_FIELD_ENCODE(665, 8, 8), 1832 /* DFE_5_INV_M1:9:9 */ 1833 PHYMOD_SYMBOL_FIELD_ENCODE(664, 9, 9), 1834 /* DFE_5_ERR_GAIN:10:11 */ 1835 PHYMOD_SYMBOL_FIELD_ENCODE(661, 11, 10), 1836 /* DFE_5_GRADIENT_INVERT:12:12 */ 1837 PHYMOD_SYMBOL_FIELD_ENCODE(663, 12, 12), 1838 /* DFE_5_ERR_SEL:13:14 */ 1839 PHYMOD_SYMBOL_FIELD_ENCODE(662, 14, 13), 1840 /* DFE_5_EN:15:15 */ 1841 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(660, 15, 15) 1842 }; 1843 static uint32_t BCMI_TSCE_XGXS_DSC_DFE_5_PAT_CTLr_fields[] = 1844 { 1845 /* DFE_5_PATTERN:0:5 */ 1846 PHYMOD_SYMBOL_FIELD_ENCODE(666, 5, 0), 1847 /* DFE_5_PATTERN_BIT_EN:8:13 */ 1848 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(667, 13, 8) 1849 }; 1850 static uint32_t BCMI_TSCE_XGXS_DSC_DFE_COMMON_CTLr_fields[] = 1851 { 1852 /* DFE_UPDATE_GAIN:13:13 */ 1853 PHYMOD_SYMBOL_FIELD_ENCODE(676, 13, 13), 1854 /* DFE_ALLOW_SIMULT:14:14 */ 1855 PHYMOD_SYMBOL_FIELD_ENCODE(669, 14, 14), 1856 /* DFE_ACC_HYS_EN:15:15 */ 1857 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(668, 15, 15) 1858 }; 1859 static uint32_t BCMI_TSCE_XGXS_DSC_DFE_VGA_OVRRr_fields[] = 1860 { 1861 /* DFE_VGA_WRITE_VAL:0:8 */ 1862 PHYMOD_SYMBOL_FIELD_ENCODE(679, 8, 0), 1863 /* DFE_VGA_WRITE_TAPSEL:9:13 */ 1864 PHYMOD_SYMBOL_FIELD_ENCODE(678, 13, 9), 1865 /* DFE_VGA_WRITE_EN:15:15 */ 1866 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(677, 15, 15) 1867 }; 1868 static uint32_t BCMI_TSCE_XGXS_DSC_OFFS_ADJ_DATA_EVENr_fields[] = 1869 { 1870 /* DFE_OFFSET_ADJ_DATA_EVEN:0:5 */ 1871 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(670, 5, 0) 1872 }; 1873 static uint32_t BCMI_TSCE_XGXS_DSC_OFFS_ADJ_DATA_ODDr_fields[] = 1874 { 1875 /* DFE_OFFSET_ADJ_DATA_ODD:0:5 */ 1876 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(671, 5, 0) 1877 }; 1878 static uint32_t BCMI_TSCE_XGXS_DSC_OFFS_ADJ_M1_EVENr_fields[] = 1879 { 1880 /* DFE_OFFSET_ADJ_M1_EVEN:0:5 */ 1881 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(672, 5, 0) 1882 }; 1883 static uint32_t BCMI_TSCE_XGXS_DSC_OFFS_ADJ_M1_ODDr_fields[] = 1884 { 1885 /* DFE_OFFSET_ADJ_M1_ODD:0:5 */ 1886 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(673, 5, 0) 1887 }; 1888 static uint32_t BCMI_TSCE_XGXS_DSC_OFFS_ADJ_P1_EVENr_fields[] = 1889 { 1890 /* DFE_OFFSET_ADJ_P1_EVEN:0:5 */ 1891 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(674, 5, 0) 1892 }; 1893 static uint32_t BCMI_TSCE_XGXS_DSC_OFFS_ADJ_P1_ODDr_fields[] = 1894 { 1895 /* DFE_OFFSET_ADJ_P1_ODD:0:5 */ 1896 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(675, 5, 0) 1897 }; 1898 static uint32_t BCMI_TSCE_XGXS_DSC_P1_FRAC_OFFS_CTLr_fields[] = 1899 { 1900 /* P1_OFFSET:0:6 */ 1901 PHYMOD_SYMBOL_FIELD_ENCODE(969, 6, 0), 1902 /* P1_OFFSET_EN:7:7 */ 1903 PHYMOD_SYMBOL_FIELD_ENCODE(970, 7, 7), 1904 /* P1_OFF_3LEVELQ_EN:8:8 */ 1905 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(971, 8, 8) 1906 }; 1907 static uint32_t BCMI_TSCE_XGXS_DSC_PF2_LOWP_CTLr_fields[] = 1908 { 1909 /* PF2_LOWP_CTRL:0:2 */ 1910 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1010, 2, 0) 1911 }; 1912 static uint32_t BCMI_TSCE_XGXS_DSC_PF_CTLr_fields[] = 1913 { 1914 /* PF_CTRL:0:3 */ 1915 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1011, 3, 0) 1916 }; 1917 static uint32_t BCMI_TSCE_XGXS_DSC_RX_PI_CNT_BIN_Dr_fields[] = 1918 { 1919 /* CNT_BIN_D_DREG:0:6 */ 1920 PHYMOD_SYMBOL_FIELD_ENCODE(550, 6, 0), 1921 /* CNT_BIN_P1_DREG:8:14 */ 1922 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(554, 14, 8) 1923 }; 1924 static uint32_t BCMI_TSCE_XGXS_DSC_RX_PI_CNT_BIN_Mr_fields[] = 1925 { 1926 /* CNT_BIN_M1_MREG:0:6 */ 1927 PHYMOD_SYMBOL_FIELD_ENCODE(552, 6, 0), 1928 /* CNT_BIN_D_MREG:8:14 */ 1929 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(551, 14, 8) 1930 }; 1931 static uint32_t BCMI_TSCE_XGXS_DSC_RX_PI_CNT_BIN_Pr_fields[] = 1932 { 1933 /* CNT_BIN_P1_PREG:0:6 */ 1934 PHYMOD_SYMBOL_FIELD_ENCODE(555, 6, 0), 1935 /* CNT_BIN_M1_PREG:8:14 */ 1936 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(553, 14, 8) 1937 }; 1938 static uint32_t BCMI_TSCE_XGXS_DSC_RX_PI_CTLr_fields[] = 1939 { 1940 /* RX_PI_PHASE_STEP_CNT:0:6 */ 1941 PHYMOD_SYMBOL_FIELD_ENCODE(1191, 6, 0), 1942 /* RX_PI_MANUAL_STROBE:9:9 */ 1943 PHYMOD_SYMBOL_FIELD_ENCODE(1190, 9, 9), 1944 /* RX_PI_PHASE_STEP_DIR:10:10 */ 1945 PHYMOD_SYMBOL_FIELD_ENCODE(1192, 10, 10), 1946 /* RX_PI_MANUAL_MODE:11:11 */ 1947 PHYMOD_SYMBOL_FIELD_ENCODE(1188, 11, 11), 1948 /* RX_PI_SLICERS_EN:12:14 */ 1949 PHYMOD_SYMBOL_FIELD_ENCODE(1193, 14, 12), 1950 /* RX_PI_MANUAL_RESET:15:15 */ 1951 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1189, 15, 15) 1952 }; 1953 static uint32_t BCMI_TSCE_XGXS_DSC_RX_PI_DIFF_BINr_fields[] = 1954 { 1955 /* CNT_D_MINUS_M1:0:7 */ 1956 PHYMOD_SYMBOL_FIELD_ENCODE(556, 7, 0), 1957 /* CNT_D_MINUS_P1:8:15 */ 1958 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(557, 15, 8) 1959 }; 1960 static uint32_t BCMI_TSCE_XGXS_DSC_SCRATCHr_fields[] = 1961 { 1962 /* UC_DSC_SCRATCH:0:15 */ 1963 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1426, 15, 0) 1964 }; 1965 static uint32_t BCMI_TSCE_XGXS_DSC_SM_CTL0r_fields[] = 1966 { 1967 /* EEE_MODE_EN:1:1 */ 1968 PHYMOD_SYMBOL_FIELD_ENCODE(706, 1, 1), 1969 /* EEE_QUIET_RX_AFE_PWRDWN_VAL:2:2 */ 1970 PHYMOD_SYMBOL_FIELD_ENCODE(710, 2, 2), 1971 /* IGNORE_RX_MODE:3:3 */ 1972 PHYMOD_SYMBOL_FIELD_ENCODE(770, 3, 3), 1973 /* CL72_TIMER_EN:4:4 */ 1974 PHYMOD_SYMBOL_FIELD_ENCODE(506, 4, 4), 1975 /* UC_TUNE_EN:5:5 */ 1976 PHYMOD_SYMBOL_FIELD_ENCODE(1429, 5, 5), 1977 /* HW_TUNE_EN:6:6 */ 1978 PHYMOD_SYMBOL_FIELD_ENCODE(765, 6, 6), 1979 /* UC_TRNSUM_EN:7:7 */ 1980 PHYMOD_SYMBOL_FIELD_ENCODE(1428, 7, 7), 1981 /* EEE_MEASURE_EN:8:8 */ 1982 PHYMOD_SYMBOL_FIELD_ENCODE(705, 8, 8), 1983 /* UC_ACK_DSC_EEE_DONE:11:11 */ 1984 PHYMOD_SYMBOL_FIELD_ENCODE(1417, 11, 11), 1985 /* UC_ACK_DSC_RESET:12:12 */ 1986 PHYMOD_SYMBOL_FIELD_ENCODE(1418, 12, 12), 1987 /* UC_ACK_DSC_RESTART:13:13 */ 1988 PHYMOD_SYMBOL_FIELD_ENCODE(1419, 13, 13), 1989 /* UC_ACK_DSC_CONFIG:14:14 */ 1990 PHYMOD_SYMBOL_FIELD_ENCODE(1416, 14, 14), 1991 /* SET_MEAS_INCOMPLETE:15:15 */ 1992 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1231, 15, 15) 1993 }; 1994 static uint32_t BCMI_TSCE_XGXS_DSC_SM_CTL1r_fields[] = 1995 { 1996 /* RX_DSC_LOCK_FRC:0:0 */ 1997 PHYMOD_SYMBOL_FIELD_ENCODE(1179, 0, 0), 1998 /* RX_DSC_LOCK_FRC_VAL:1:1 */ 1999 PHYMOD_SYMBOL_FIELD_ENCODE(1180, 1, 1), 2000 /* DSC_CLR_FRC:2:2 */ 2001 PHYMOD_SYMBOL_FIELD_ENCODE(690, 2, 2), 2002 /* DSC_CLR_FRC_VAL:3:3 */ 2003 PHYMOD_SYMBOL_FIELD_ENCODE(691, 3, 3), 2004 /* TRNSUM_FRZ_FRC:4:4 */ 2005 PHYMOD_SYMBOL_FIELD_ENCODE(1304, 4, 4), 2006 /* TRNSUM_FRZ_FRC_VAL:5:5 */ 2007 PHYMOD_SYMBOL_FIELD_ENCODE(1305, 5, 5), 2008 /* TIMER_DONE_FRC:6:6 */ 2009 PHYMOD_SYMBOL_FIELD_ENCODE(1291, 6, 6), 2010 /* TIMER_DONE_FRC_VAL:7:7 */ 2011 PHYMOD_SYMBOL_FIELD_ENCODE(1292, 7, 7), 2012 /* FREQ_UPD_EN_FRC:8:8 */ 2013 PHYMOD_SYMBOL_FIELD_ENCODE(747, 8, 8), 2014 /* FREQ_UPD_EN_FRC_VAL:9:9 */ 2015 PHYMOD_SYMBOL_FIELD_ENCODE(748, 9, 9), 2016 /* CDR_FRZ_FRC:10:10 */ 2017 PHYMOD_SYMBOL_FIELD_ENCODE(380, 10, 10), 2018 /* CDR_FRZ_FRC_VAL:11:11 */ 2019 PHYMOD_SYMBOL_FIELD_ENCODE(381, 11, 11), 2020 /* TRNSUM_CLR_FRC:12:12 */ 2021 PHYMOD_SYMBOL_FIELD_ENCODE(1296, 12, 12), 2022 /* TRNSUM_CLR_FRC_VAL:13:13 */ 2023 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1297, 13, 13) 2024 }; 2025 static uint32_t BCMI_TSCE_XGXS_DSC_SM_CTL2r_fields[] = 2026 { 2027 /* EEE_LFSR_CNT:0:12 */ 2028 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(703, 12, 0) 2029 }; 2030 static uint32_t BCMI_TSCE_XGXS_DSC_SM_CTL3r_fields[] = 2031 { 2032 /* MEASURE_LFSR_CNT:0:12 */ 2033 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(890, 12, 0) 2034 }; 2035 static uint32_t BCMI_TSCE_XGXS_DSC_SM_CTL4r_fields[] = 2036 { 2037 /* ACQ_CDR_TIMEOUT:0:4 */ 2038 PHYMOD_SYMBOL_FIELD_ENCODE(1, 4, 0), 2039 /* CDR_SETTLE_TIMEOUT:5:9 */ 2040 PHYMOD_SYMBOL_FIELD_ENCODE(391, 9, 5), 2041 /* HW_TUNE_TIMEOUT:10:14 */ 2042 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(766, 14, 10) 2043 }; 2044 static uint32_t BCMI_TSCE_XGXS_DSC_SM_CTL5r_fields[] = 2045 { 2046 /* MEASURE_TIMEOUT:0:4 */ 2047 PHYMOD_SYMBOL_FIELD_ENCODE(891, 4, 0), 2048 /* EEE_ACQ_CDR_TIMEOUT:5:9 */ 2049 PHYMOD_SYMBOL_FIELD_ENCODE(699, 9, 5), 2050 /* EEE_CDR_SETTLE_TIMEOUT:10:14 */ 2051 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(701, 14, 10) 2052 }; 2053 static uint32_t BCMI_TSCE_XGXS_DSC_SM_CTL6r_fields[] = 2054 { 2055 /* EEE_HW_TUNE_TIMEOUT:0:4 */ 2056 PHYMOD_SYMBOL_FIELD_ENCODE(702, 4, 0), 2057 /* EEE_ANA_PWR_TIMEOUT:10:14 */ 2058 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(700, 14, 10) 2059 }; 2060 static uint32_t BCMI_TSCE_XGXS_DSC_SM_CTL7r_fields[] = 2061 { 2062 /* CDR_BWSEL_INTEG_ACQCDR:0:3 */ 2063 PHYMOD_SYMBOL_FIELD_ENCODE(371, 3, 0), 2064 /* CDR_BWSEL_INTEG_EEE_ACQCDR:4:7 */ 2065 PHYMOD_SYMBOL_FIELD_ENCODE(372, 7, 4), 2066 /* CDR_BWSEL_INTEG_NORM:8:11 */ 2067 PHYMOD_SYMBOL_FIELD_ENCODE(373, 11, 8), 2068 /* CDR_BWSEL_PROP_ACQCDR:12:13 */ 2069 PHYMOD_SYMBOL_FIELD_ENCODE(374, 13, 12), 2070 /* CDR_BWSEL_PROP_NORM:14:15 */ 2071 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(376, 15, 14) 2072 }; 2073 static uint32_t BCMI_TSCE_XGXS_DSC_SM_CTL8r_fields[] = 2074 { 2075 /* PHASE_ERR_OFFSET:0:3 */ 2076 PHYMOD_SYMBOL_FIELD_ENCODE(1013, 3, 0), 2077 /* EEE_PHASE_ERR_OFFSET:4:7 */ 2078 PHYMOD_SYMBOL_FIELD_ENCODE(707, 7, 4), 2079 /* PHASE_ERR_OFFSET_EN:8:9 */ 2080 PHYMOD_SYMBOL_FIELD_ENCODE(1014, 9, 8), 2081 /* EEE_PHASE_ERR_OFFSET_EN:10:11 */ 2082 PHYMOD_SYMBOL_FIELD_ENCODE(708, 11, 10), 2083 /* CDR_BWSEL_PROP_EEE_ACQCDR:14:15 */ 2084 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(375, 15, 14) 2085 }; 2086 static uint32_t BCMI_TSCE_XGXS_DSC_SM_CTL9r_fields[] = 2087 { 2088 /* RX_RESTART_PMD:0:0 */ 2089 PHYMOD_SYMBOL_FIELD_ENCODE(1198, 0, 0), 2090 /* RX_RESTART_PMD_HOLD:1:1 */ 2091 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1199, 1, 1) 2092 }; 2093 static uint32_t BCMI_TSCE_XGXS_DSC_SM_STS_DSC_LOCKr_fields[] = 2094 { 2095 /* RX_DSC_LOCK:0:0 */ 2096 PHYMOD_SYMBOL_FIELD_ENCODE(1178, 0, 0), 2097 /* MEAS_INCOMPLETE:1:1 */ 2098 PHYMOD_SYMBOL_FIELD_ENCODE(892, 1, 1), 2099 /* EEE_MEASURE_CNT:7:15 */ 2100 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(704, 15, 7) 2101 }; 2102 static uint32_t BCMI_TSCE_XGXS_DSC_SM_STS_DSC_STr_fields[] = 2103 { 2104 /* DSC_SM_SCRATCH:0:3 */ 2105 PHYMOD_SYMBOL_FIELD_ENCODE(694, 3, 0), 2106 /* DSC_SM_READY_FOR_CMD:4:4 */ 2107 PHYMOD_SYMBOL_FIELD_ENCODE(693, 4, 4), 2108 /* DSC_SM_GP_UC_REQ:5:10 */ 2109 PHYMOD_SYMBOL_FIELD_ENCODE(692, 10, 5), 2110 /* DSC_STATE:11:15 */ 2111 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(695, 15, 11) 2112 }; 2113 static uint32_t BCMI_TSCE_XGXS_DSC_SM_STS_DSC_ST_EEE_ONE_HOTr_fields[] = 2114 { 2115 /* DSC_STATE_EEE_ONE_HOT:0:6 */ 2116 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(696, 6, 0) 2117 }; 2118 static uint32_t BCMI_TSCE_XGXS_DSC_SM_STS_DSC_ST_ONE_HOTr_fields[] = 2119 { 2120 /* DSC_STATE_ONE_HOT:0:9 */ 2121 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(697, 9, 0) 2122 }; 2123 static uint32_t BCMI_TSCE_XGXS_DSC_SM_STS_RESTARTr_fields[] = 2124 { 2125 /* RESTART_PI_EXT_MODE:0:0 */ 2126 PHYMOD_SYMBOL_FIELD_ENCODE(1122, 0, 0), 2127 /* RESTART_SIGDET:1:1 */ 2128 PHYMOD_SYMBOL_FIELD_ENCODE(1124, 1, 1), 2129 /* RESTART_PMD_RESTART:2:2 */ 2130 PHYMOD_SYMBOL_FIELD_ENCODE(1123, 2, 2), 2131 /* EEE_QUIET_FROM_EEE_STATES:3:3 */ 2132 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(709, 3, 3) 2133 }; 2134 static uint32_t BCMI_TSCE_XGXS_DSC_TRNSUM_CTL1r_fields[] = 2135 { 2136 /* TRNSUM_TAP_RANGE_SEL:2:3 */ 2137 PHYMOD_SYMBOL_FIELD_ENCODE(1317, 3, 2), 2138 /* CDR_QPHASE_MULT_EN:4:4 */ 2139 PHYMOD_SYMBOL_FIELD_ENCODE(390, 4, 4), 2140 /* TRNSUM_EYE_CLOSURE_EN:5:5 */ 2141 PHYMOD_SYMBOL_FIELD_ENCODE(1301, 5, 5), 2142 /* TRNSUM_GAIN:6:7 */ 2143 PHYMOD_SYMBOL_FIELD_ENCODE(1306, 7, 6), 2144 /* TRNSUM_PATTERN_FULL_CHECK_OFF:9:9 */ 2145 PHYMOD_SYMBOL_FIELD_ENCODE(1314, 9, 9), 2146 /* TRNSUM_INV_PATTERN_EN:10:10 */ 2147 PHYMOD_SYMBOL_FIELD_ENCODE(1308, 10, 10), 2148 /* TRNSUM_RANDOM_TAPSEL_DISABLE:11:11 */ 2149 PHYMOD_SYMBOL_FIELD_ENCODE(1315, 11, 11), 2150 /* TRNSUM_ERR_SEL:12:14 */ 2151 PHYMOD_SYMBOL_FIELD_ENCODE(1300, 14, 12), 2152 /* TRNSUM_EN:15:15 */ 2153 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1298, 15, 15) 2154 }; 2155 static uint32_t BCMI_TSCE_XGXS_DSC_TRNSUM_CTL2r_fields[] = 2156 { 2157 /* TRNSUM_PATTERN_BIT_EN:0:7 */ 2158 PHYMOD_SYMBOL_FIELD_ENCODE(1313, 7, 0), 2159 /* TRNSUM_PATTERN:8:15 */ 2160 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1312, 15, 8) 2161 }; 2162 static uint32_t BCMI_TSCE_XGXS_DSC_TRNSUM_CTL3r_fields[] = 2163 { 2164 /* TRNSUM_TAP_SIGN:0:7 */ 2165 PHYMOD_SYMBOL_FIELD_ENCODE(1318, 7, 0), 2166 /* TRNSUM_TAP_EN:8:15 */ 2167 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1316, 15, 8) 2168 }; 2169 static uint32_t BCMI_TSCE_XGXS_DSC_TRNSUM_CTL4r_fields[] = 2170 { 2171 /* TRNSUM_UNSIGNED_CORR:0:0 */ 2172 PHYMOD_SYMBOL_FIELD_ENCODE(1319, 0, 0), 2173 /* TRNSUM_UNSIGNED_FLIP:1:1 */ 2174 PHYMOD_SYMBOL_FIELD_ENCODE(1320, 1, 1), 2175 /* TDR_BIT_SEL:2:6 */ 2176 PHYMOD_SYMBOL_FIELD_ENCODE(1282, 6, 2), 2177 /* TDR_TRNSUM_EN:7:7 */ 2178 PHYMOD_SYMBOL_FIELD_ENCODE(1285, 7, 7), 2179 /* TDR_CYCLE_SEL:8:11 */ 2180 PHYMOD_SYMBOL_FIELD_ENCODE(1284, 11, 8), 2181 /* TDR_CYCLE_BIN:12:15 */ 2182 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1283, 15, 12) 2183 }; 2184 static uint32_t BCMI_TSCE_XGXS_DSC_TRNSUM_CTL5r_fields[] = 2185 { 2186 /* SEND_LMS_TO_PCS:14:14 */ 2187 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1228, 14, 14) 2188 }; 2189 static uint32_t BCMI_TSCE_XGXS_DSC_TRNSUM_STS1r_fields[] = 2190 { 2191 /* TRNSUM_E_HIGH:0:15 */ 2192 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1302, 15, 0) 2193 }; 2194 static uint32_t BCMI_TSCE_XGXS_DSC_TRNSUM_STS2r_fields[] = 2195 { 2196 /* TRNSUM_E_LOW:0:7 */ 2197 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1303, 7, 0) 2198 }; 2199 static uint32_t BCMI_TSCE_XGXS_DSC_TRNSUM_STS3r_fields[] = 2200 { 2201 /* TRNSUM_O_HIGH:0:15 */ 2202 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1310, 15, 0) 2203 }; 2204 static uint32_t BCMI_TSCE_XGXS_DSC_TRNSUM_STS4r_fields[] = 2205 { 2206 /* TRNSUM_O_LOW:0:7 */ 2207 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1311, 7, 0) 2208 }; 2209 static uint32_t BCMI_TSCE_XGXS_DSC_TRNSUM_STS5r_fields[] = 2210 { 2211 /* TRNSUM_HIGH:0:15 */ 2212 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1307, 15, 0) 2213 }; 2214 static uint32_t BCMI_TSCE_XGXS_DSC_TRNSUM_STS6r_fields[] = 2215 { 2216 /* TRNSUM_LOW:0:9 */ 2217 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1309, 9, 0) 2218 }; 2219 static uint32_t BCMI_TSCE_XGXS_DSC_UC_CTLr_fields[] = 2220 { 2221 /* UC_DSC_GP_UC_REQ:0:5 */ 2222 PHYMOD_SYMBOL_FIELD_ENCODE(1424, 5, 0), 2223 /* UC_DSC_ERROR_FOUND:6:6 */ 2224 PHYMOD_SYMBOL_FIELD_ENCODE(1423, 6, 6), 2225 /* UC_DSC_READY_FOR_CMD:7:7 */ 2226 PHYMOD_SYMBOL_FIELD_ENCODE(1425, 7, 7), 2227 /* UC_DSC_SUPP_INFO:8:15 */ 2228 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1427, 15, 8) 2229 }; 2230 static uint32_t BCMI_TSCE_XGXS_DSC_VGA_CTLr_fields[] = 2231 { 2232 /* VGA_P1_ACC_CLR:0:0 */ 2233 PHYMOD_SYMBOL_FIELD_ENCODE(1445, 0, 0), 2234 /* VGA_ACC_HYS_EN:1:1 */ 2235 PHYMOD_SYMBOL_FIELD_ENCODE(1437, 1, 1), 2236 /* VGA_TABLEMAP_DISABLE:2:2 */ 2237 PHYMOD_SYMBOL_FIELD_ENCODE(1449, 2, 2), 2238 /* VGA_UPDATE_GAIN:6:7 */ 2239 PHYMOD_SYMBOL_FIELD_ENCODE(1450, 7, 6), 2240 /* VGA_INV_P1:8:8 */ 2241 PHYMOD_SYMBOL_FIELD_ENCODE(1444, 8, 8), 2242 /* VGA_INV_M1:9:9 */ 2243 PHYMOD_SYMBOL_FIELD_ENCODE(1443, 9, 9), 2244 /* VGA_ERR_GAIN:10:11 */ 2245 PHYMOD_SYMBOL_FIELD_ENCODE(1441, 11, 10), 2246 /* VGA_P1_GRADIENT_INVERT:12:12 */ 2247 PHYMOD_SYMBOL_FIELD_ENCODE(1446, 12, 12), 2248 /* VGA_ERR_SEL:13:14 */ 2249 PHYMOD_SYMBOL_FIELD_ENCODE(1442, 14, 13), 2250 /* VGA_EN:15:15 */ 2251 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1440, 15, 15) 2252 }; 2253 static uint32_t BCMI_TSCE_XGXS_DSC_VGA_P1EYEDIAG_STSr_fields[] = 2254 { 2255 /* VGA_BIN:0:5 */ 2256 PHYMOD_SYMBOL_FIELD_ENCODE(1438, 5, 0), 2257 /* P1_EYEDIAG_BIN:8:13 */ 2258 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(967, 13, 8) 2259 }; 2260 static uint32_t BCMI_TSCE_XGXS_DSC_VGA_PAT_EYEDIAG_CTLr_fields[] = 2261 { 2262 /* VGA_PATTERN:0:3 */ 2263 PHYMOD_SYMBOL_FIELD_ENCODE(1447, 3, 0), 2264 /* VGA_PATTERN_BIT_EN:4:7 */ 2265 PHYMOD_SYMBOL_FIELD_ENCODE(1448, 7, 4), 2266 /* P1_EYEDIAG_EN:15:15 */ 2267 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(968, 15, 15) 2268 }; 2269 static uint32_t BCMI_TSCE_XGXS_DSC_VGA_TAP_BINr_fields[] = 2270 { 2271 /* VGA_CTRL_BIN:0:4 */ 2272 PHYMOD_SYMBOL_FIELD_ENCODE(1439, 4, 0), 2273 /* VGA3_CTRL_BIN:8:11 */ 2274 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1436, 11, 8) 2275 }; 2276 static uint32_t BCMI_TSCE_XGXS_ILKN_CTL0r_fields[] = 2277 { 2278 /* WM:0:2 */ 2279 PHYMOD_SYMBOL_FIELD_ENCODE(1456, 2, 0), 2280 /* ILKN_SEL:3:3 */ 2281 PHYMOD_SYMBOL_FIELD_ENCODE(771, 3, 3), 2282 /* INV_TX_ORDER:6:6 */ 2283 PHYMOD_SYMBOL_FIELD_ENCODE(776, 6, 6), 2284 /* INV_RX_ORDER:7:7 */ 2285 PHYMOD_SYMBOL_FIELD_ENCODE(775, 7, 7), 2286 /* SOFT_RST_TX:8:8 */ 2287 PHYMOD_SYMBOL_FIELD_ENCODE(1258, 8, 8), 2288 /* SOFT_RST_RX:9:9 */ 2289 PHYMOD_SYMBOL_FIELD_ENCODE(1257, 9, 9), 2290 /* CREDIT_EN:15:15 */ 2291 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(572, 15, 15) 2292 }; 2293 static uint32_t BCMI_TSCE_XGXS_ILKN_STS0r_fields[] = 2294 { 2295 /* RXFIFO_EMPTY:0:0 */ 2296 PHYMOD_SYMBOL_FIELD_ENCODE(1164, 0, 0), 2297 /* RXFIFO_FULL:1:1 */ 2298 PHYMOD_SYMBOL_FIELD_ENCODE(1165, 1, 1), 2299 /* RXFIFO_OVERRUN:2:2 */ 2300 PHYMOD_SYMBOL_FIELD_ENCODE(1166, 2, 2), 2301 /* RXFIFO_UNDERRUN:3:3 */ 2302 PHYMOD_SYMBOL_FIELD_ENCODE(1167, 3, 3), 2303 /* TXFIFO_EMPTY:4:4 */ 2304 PHYMOD_SYMBOL_FIELD_ENCODE(1321, 4, 4), 2305 /* TXFIFO_FULL:5:5 */ 2306 PHYMOD_SYMBOL_FIELD_ENCODE(1322, 5, 5), 2307 /* TXFIFO_OVERRUN:6:6 */ 2308 PHYMOD_SYMBOL_FIELD_ENCODE(1323, 6, 6), 2309 /* TXFIFO_UNDERRUN:7:7 */ 2310 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1324, 7, 7) 2311 }; 2312 static uint32_t BCMI_TSCE_XGXS_MAIN0_DEVINPKG5r_fields[] = 2313 { 2314 /* CLAUSE22:0:0 */ 2315 PHYMOD_SYMBOL_FIELD_ENCODE(544, 0, 0), 2316 /* PMA_PMD:1:1 */ 2317 PHYMOD_SYMBOL_FIELD_ENCODE(1045, 1, 1), 2318 /* WIS:2:2 */ 2319 PHYMOD_SYMBOL_FIELD_ENCODE(1455, 2, 2), 2320 /* PCS_XS:3:3 */ 2321 PHYMOD_SYMBOL_FIELD_ENCODE(999, 3, 3), 2322 /* PHY_XS:4:4 */ 2323 PHYMOD_SYMBOL_FIELD_ENCODE(1016, 4, 4), 2324 /* DTE_XS:5:5 */ 2325 PHYMOD_SYMBOL_FIELD_ENCODE(698, 5, 5), 2326 /* TC:6:6 */ 2327 PHYMOD_SYMBOL_FIELD_ENCODE(1281, 6, 6), 2328 /* AN:7:7 */ 2329 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(200, 7, 7) 2330 }; 2331 static uint32_t BCMI_TSCE_XGXS_MAIN0_LN_SWPr_fields[] = 2332 { 2333 /* LOG0_TO_PHY_LNSWAP_SEL:0:1 */ 2334 PHYMOD_SYMBOL_FIELD_ENCODE(834, 1, 0), 2335 /* LOG1_TO_PHY_LNSWAP_SEL:2:3 */ 2336 PHYMOD_SYMBOL_FIELD_ENCODE(835, 3, 2), 2337 /* LOG2_TO_PHY_LNSWAP_SEL:4:5 */ 2338 PHYMOD_SYMBOL_FIELD_ENCODE(836, 5, 4), 2339 /* LOG3_TO_PHY_LNSWAP_SEL:6:7 */ 2340 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(837, 7, 6) 2341 }; 2342 static uint32_t BCMI_TSCE_XGXS_MAIN0_LPBK_CTLr_fields[] = 2343 { 2344 /* LOCAL_PCS_LOOPBACK_ENABLE:4:7 */ 2345 PHYMOD_SYMBOL_FIELD_ENCODE(833, 7, 4), 2346 /* REMOTE_PMD_LOOPBACK_ENABLE:8:11 */ 2347 PHYMOD_SYMBOL_FIELD_ENCODE(1111, 11, 8), 2348 /* REMOTE_PCS_LOOPBACK_ENABLE:12:15 */ 2349 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1110, 15, 12) 2350 }; 2351 static uint32_t BCMI_TSCE_XGXS_MAIN0_MDIO_BCSTr_fields[] = 2352 { 2353 /* MULTIPRTS_EN:7:10 */ 2354 PHYMOD_SYMBOL_FIELD_ENCODE(945, 10, 7), 2355 /* PRTAD_BCST:11:15 */ 2356 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1092, 15, 11) 2357 }; 2358 static uint32_t BCMI_TSCE_XGXS_MAIN0_MISCr_fields[] = 2359 { 2360 /* CL82_MLD_PHYS_MAP:7:8 */ 2361 PHYMOD_SYMBOL_FIELD_ENCODE(535, 8, 7), 2362 /* CL82_MULTI_PIPE_MODE:9:10 */ 2363 PHYMOD_SYMBOL_FIELD_ENCODE(536, 10, 9), 2364 /* CL49_LOW_LATENCY_EN:11:11 */ 2365 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(449, 11, 11) 2366 }; 2367 static uint32_t BCMI_TSCE_XGXS_MAIN0_SERDESIDr_fields[] = 2368 { 2369 /* MODEL_NUMBER:0:5 */ 2370 PHYMOD_SYMBOL_FIELD_ENCODE(942, 5, 0), 2371 /* TECH_PROC:6:8 */ 2372 PHYMOD_SYMBOL_FIELD_ENCODE(1286, 8, 6), 2373 /* BONDING:9:10 */ 2374 PHYMOD_SYMBOL_FIELD_ENCODE(345, 10, 9), 2375 /* REV_NUMBER:11:13 */ 2376 PHYMOD_SYMBOL_FIELD_ENCODE(1141, 13, 11), 2377 /* REV_LETTER:14:15 */ 2378 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1140, 15, 14) 2379 }; 2380 static uint32_t BCMI_TSCE_XGXS_MAIN0_SETUPr_fields[] = 2381 { 2382 /* STAND_ALONE_MODE:2:2 */ 2383 PHYMOD_SYMBOL_FIELD_ENCODE(1262, 2, 2), 2384 /* SINGLE_PORT_MODE:3:3 */ 2385 PHYMOD_SYMBOL_FIELD_ENCODE(1254, 3, 3), 2386 /* PORT_MODE_SEL:4:6 */ 2387 PHYMOD_SYMBOL_FIELD_ENCODE(1063, 6, 4), 2388 /* MASTER_PORT_NUM:8:9 */ 2389 PHYMOD_SYMBOL_FIELD_ENCODE(873, 9, 8), 2390 /* PLL_RESET_EN:10:10 */ 2391 PHYMOD_SYMBOL_FIELD_ENCODE(1039, 10, 10), 2392 /* CL73_LOW_VCO:11:11 */ 2393 PHYMOD_SYMBOL_FIELD_ENCODE(522, 11, 11), 2394 /* CL37_HIGH_VCO:12:12 */ 2395 PHYMOD_SYMBOL_FIELD_ENCODE(413, 12, 12), 2396 /* REFCLK_SEL:13:15 */ 2397 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1104, 15, 13) 2398 }; 2399 static uint32_t BCMI_TSCE_XGXS_MAIN0_SYNCE_CTLr_fields[] = 2400 { 2401 /* SYNCE_MODE_PHY_LN0:0:1 */ 2402 PHYMOD_SYMBOL_FIELD_ENCODE(1273, 1, 0), 2403 /* SYNCE_MODE_PHY_LN1:2:3 */ 2404 PHYMOD_SYMBOL_FIELD_ENCODE(1274, 3, 2), 2405 /* SYNCE_MODE_PHY_LN2:4:5 */ 2406 PHYMOD_SYMBOL_FIELD_ENCODE(1275, 5, 4), 2407 /* SYNCE_MODE_PHY_LN3:6:7 */ 2408 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1276, 7, 6) 2409 }; 2410 static uint32_t BCMI_TSCE_XGXS_MAIN0_TICK_CTL0r_fields[] = 2411 { 2412 /* TICK_DENOMINATOR:2:11 */ 2413 PHYMOD_SYMBOL_FIELD_ENCODE(1287, 11, 2), 2414 /* TICK_NUMERATOR_LOWER:12:15 */ 2415 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1288, 15, 12) 2416 }; 2417 static uint32_t BCMI_TSCE_XGXS_MAIN0_TICK_CTL1r_fields[] = 2418 { 2419 /* TICK_NUMERATOR_UPPER:0:14 */ 2420 PHYMOD_SYMBOL_FIELD_ENCODE(1289, 14, 0), 2421 /* TICK_OVERRIDE:15:15 */ 2422 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1290, 15, 15) 2423 }; 2424 static uint32_t BCMI_TSCE_XGXS_MDIO_AERr_fields[] = 2425 { 2426 /* MDIO_AER:0:15 */ 2427 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(876, 15, 0) 2428 }; 2429 static uint32_t BCMI_TSCE_XGXS_MDIO_BCST_PORT_ADDRr_fields[] = 2430 { 2431 /* MDIO_BRCST_PORT_ADDR:0:4 */ 2432 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(878, 4, 0) 2433 }; 2434 static uint32_t BCMI_TSCE_XGXS_MDIO_BLK_ADDRr_fields[] = 2435 { 2436 /* MDIO_BLK_ADDR:4:14 */ 2437 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(877, 14, 4) 2438 }; 2439 static uint32_t BCMI_TSCE_XGXS_MDIO_MASKDATAr_fields[] = 2440 { 2441 /* MDIO_MASKDATA:0:15 */ 2442 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(887, 15, 0) 2443 }; 2444 static uint32_t BCMI_TSCE_XGXS_MDIO_MMD_SELr_fields[] = 2445 { 2446 /* MDIO_DEV_CL22_EN:0:0 */ 2447 PHYMOD_SYMBOL_FIELD_ENCODE(881, 0, 0), 2448 /* MDIO_DEV_PMD_EN:2:2 */ 2449 PHYMOD_SYMBOL_FIELD_ENCODE(885, 2, 2), 2450 /* MDIO_DEV_AN_EN:3:3 */ 2451 PHYMOD_SYMBOL_FIELD_ENCODE(880, 3, 3), 2452 /* MDIO_DEV_PHY_EN:4:4 */ 2453 PHYMOD_SYMBOL_FIELD_ENCODE(884, 4, 4), 2454 /* MDIO_DEV_DTE_EN:5:5 */ 2455 PHYMOD_SYMBOL_FIELD_ENCODE(882, 5, 5), 2456 /* MDIO_DEV_PCS_EN:6:6 */ 2457 PHYMOD_SYMBOL_FIELD_ENCODE(883, 6, 6), 2458 /* MDIO_MULTI_MMDS_EN:14:14 */ 2459 PHYMOD_SYMBOL_FIELD_ENCODE(888, 14, 14), 2460 /* MDIO_MULTI_PRTS_EN:15:15 */ 2461 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(889, 15, 15) 2462 }; 2463 static uint32_t BCMI_TSCE_XGXS_MEM_ECC_CORRUPTr_fields[] = 2464 { 2465 /* DESKEW_ECC_CORRUPT:0:1 */ 2466 PHYMOD_SYMBOL_FIELD_ENCODE(602, 1, 0), 2467 /* RFEC0_ECC_CORRUPT:2:3 */ 2468 PHYMOD_SYMBOL_FIELD_ENCODE(1146, 3, 2), 2469 /* RFEC1_ECC_CORRUPT:4:5 */ 2470 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1152, 5, 4) 2471 }; 2472 static uint32_t BCMI_TSCE_XGXS_MEM_ECC_DESKEW_STSr_fields[] = 2473 { 2474 /* DESKEW_ADDRESS:0:6 */ 2475 PHYMOD_SYMBOL_FIELD_ENCODE(600, 6, 0), 2476 /* DESKEW_2BIT_ERROR:14:14 */ 2477 PHYMOD_SYMBOL_FIELD_ENCODE(599, 14, 14), 2478 /* DESKEW_1BIT_ERROR:15:15 */ 2479 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(598, 15, 15) 2480 }; 2481 static uint32_t BCMI_TSCE_XGXS_MEM_ECC_DISr_fields[] = 2482 { 2483 /* DESKEW_DISABLE_ECC:0:0 */ 2484 PHYMOD_SYMBOL_FIELD_ENCODE(601, 0, 0), 2485 /* RFEC0_DISABLE_ECC:1:1 */ 2486 PHYMOD_SYMBOL_FIELD_ENCODE(1145, 1, 1), 2487 /* RFEC1_DISABLE_ECC:2:2 */ 2488 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1151, 2, 2) 2489 }; 2490 static uint32_t BCMI_TSCE_XGXS_MEM_ECC_INT_1BITr_fields[] = 2491 { 2492 /* INT_1B:0:3 */ 2493 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(772, 3, 0) 2494 }; 2495 static uint32_t BCMI_TSCE_XGXS_MEM_ECC_INT_2BITr_fields[] = 2496 { 2497 /* INT_2B:0:3 */ 2498 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(773, 3, 0) 2499 }; 2500 static uint32_t BCMI_TSCE_XGXS_MEM_ECC_MSK_1BITr_fields[] = 2501 { 2502 /* MSK_1B:0:3 */ 2503 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(943, 3, 0) 2504 }; 2505 static uint32_t BCMI_TSCE_XGXS_MEM_ECC_MSK_2BITr_fields[] = 2506 { 2507 /* MSK_2B:0:3 */ 2508 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(944, 3, 0) 2509 }; 2510 static uint32_t BCMI_TSCE_XGXS_MEM_ECC_RFEC0_STSr_fields[] = 2511 { 2512 /* RFEC0_ADDRESS:0:7 */ 2513 PHYMOD_SYMBOL_FIELD_ENCODE(1144, 7, 0), 2514 /* RFEC0_2BIT_ERROR:14:14 */ 2515 PHYMOD_SYMBOL_FIELD_ENCODE(1143, 14, 14), 2516 /* RFEC0_1BIT_ERROR:15:15 */ 2517 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1142, 15, 15) 2518 }; 2519 static uint32_t BCMI_TSCE_XGXS_MEM_ECC_RFEC1_STSr_fields[] = 2520 { 2521 /* RFEC1_ADDRESS:0:7 */ 2522 PHYMOD_SYMBOL_FIELD_ENCODE(1150, 7, 0), 2523 /* RFEC1_2BIT_ERROR:14:14 */ 2524 PHYMOD_SYMBOL_FIELD_ENCODE(1149, 14, 14), 2525 /* RFEC1_1BIT_ERROR:15:15 */ 2526 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1148, 15, 15) 2527 }; 2528 static uint32_t BCMI_TSCE_XGXS_MEM_TM_DESKEWr_fields[] = 2529 { 2530 /* DESKEW_TM:0:11 */ 2531 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(608, 11, 0) 2532 }; 2533 static uint32_t BCMI_TSCE_XGXS_MEM_TM_RFEC0r_fields[] = 2534 { 2535 /* RFEC0_TM:0:11 */ 2536 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1147, 11, 0) 2537 }; 2538 static uint32_t BCMI_TSCE_XGXS_MEM_TM_RFEC1r_fields[] = 2539 { 2540 /* RFEC1_TM:0:11 */ 2541 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1153, 11, 0) 2542 }; 2543 static uint32_t BCMI_TSCE_XGXS_MISC_CL72_EN_MASKr_fields[] = 2544 { 2545 /* CL72_EN_MASK:0:15 */ 2546 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(474, 15, 0) 2547 }; 2548 static uint32_t BCMI_TSCE_XGXS_MISC_SCRMBLR_CTLr_fields[] = 2549 { 2550 /* SCRAMBLER_EN_MASK:0:4 */ 2551 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1202, 4, 0) 2552 }; 2553 static uint32_t BCMI_TSCE_XGXS_MISC_TX_RATE_MISMATCHr_fields[] = 2554 { 2555 /* TX_LANE_RATE_MISMATCH:0:3 */ 2556 PHYMOD_SYMBOL_FIELD_ENCODE(1363, 3, 0), 2557 /* TX_LANE_RATE_MISMATCH_VL1:4:7 */ 2558 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1364, 7, 4) 2559 }; 2560 static uint32_t BCMI_TSCE_XGXS_MISC_XGXSSTS0r_fields[] = 2561 { 2562 /* SKEW_STATUS:0:0 */ 2563 PHYMOD_SYMBOL_FIELD_ENCODE(1255, 0, 0), 2564 /* STATUS_EN:15:15 */ 2565 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1263, 15, 15) 2566 }; 2567 static uint32_t BCMI_TSCE_XGXS_PATGEN_RXPKTCNT_Lr_fields[] = 2568 { 2569 /* RXPKTCNT_L:0:15 */ 2570 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1168, 15, 0) 2571 }; 2572 static uint32_t BCMI_TSCE_XGXS_PATGEN_RXPKTCNT_Ur_fields[] = 2573 { 2574 /* RXPKTCNT_U:0:15 */ 2575 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1169, 15, 0) 2576 }; 2577 static uint32_t BCMI_TSCE_XGXS_PATGEN_SEQ0r_fields[] = 2578 { 2579 /* PATT_GEN_SEQ_0:0:15 */ 2580 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(975, 15, 0) 2581 }; 2582 static uint32_t BCMI_TSCE_XGXS_PATGEN_SEQ1r_fields[] = 2583 { 2584 /* PATT_GEN_SEQ_1:0:15 */ 2585 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(976, 15, 0) 2586 }; 2587 static uint32_t BCMI_TSCE_XGXS_PATGEN_SEQ2r_fields[] = 2588 { 2589 /* PATT_GEN_SEQ_2:0:15 */ 2590 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(982, 15, 0) 2591 }; 2592 static uint32_t BCMI_TSCE_XGXS_PATGEN_SEQ3r_fields[] = 2593 { 2594 /* PATT_GEN_SEQ_3:0:15 */ 2595 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(983, 15, 0) 2596 }; 2597 static uint32_t BCMI_TSCE_XGXS_PATGEN_SEQ4r_fields[] = 2598 { 2599 /* PATT_GEN_SEQ_4:0:15 */ 2600 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(984, 15, 0) 2601 }; 2602 static uint32_t BCMI_TSCE_XGXS_PATGEN_SEQ5r_fields[] = 2603 { 2604 /* PATT_GEN_SEQ_5:0:15 */ 2605 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(985, 15, 0) 2606 }; 2607 static uint32_t BCMI_TSCE_XGXS_PATGEN_SEQ6r_fields[] = 2608 { 2609 /* PATT_GEN_SEQ_6:0:15 */ 2610 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(986, 15, 0) 2611 }; 2612 static uint32_t BCMI_TSCE_XGXS_PATGEN_SEQ7r_fields[] = 2613 { 2614 /* PATT_GEN_SEQ_7:0:15 */ 2615 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(987, 15, 0) 2616 }; 2617 static uint32_t BCMI_TSCE_XGXS_PATGEN_SEQ8r_fields[] = 2618 { 2619 /* PATT_GEN_SEQ_8:0:15 */ 2620 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(988, 15, 0) 2621 }; 2622 static uint32_t BCMI_TSCE_XGXS_PATGEN_SEQ9r_fields[] = 2623 { 2624 /* PATT_GEN_SEQ_9:0:15 */ 2625 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(989, 15, 0) 2626 }; 2627 static uint32_t BCMI_TSCE_XGXS_PATGEN_SEQ_10r_fields[] = 2628 { 2629 /* PATT_GEN_SEQ_10:0:15 */ 2630 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(977, 15, 0) 2631 }; 2632 static uint32_t BCMI_TSCE_XGXS_PATGEN_SEQ_11r_fields[] = 2633 { 2634 /* PATT_GEN_SEQ_11:0:15 */ 2635 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(978, 15, 0) 2636 }; 2637 static uint32_t BCMI_TSCE_XGXS_PATGEN_SEQ_12r_fields[] = 2638 { 2639 /* PATT_GEN_SEQ_12:0:15 */ 2640 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(979, 15, 0) 2641 }; 2642 static uint32_t BCMI_TSCE_XGXS_PATGEN_SEQ_13r_fields[] = 2643 { 2644 /* PATT_GEN_SEQ_13:0:15 */ 2645 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(980, 15, 0) 2646 }; 2647 static uint32_t BCMI_TSCE_XGXS_PATGEN_SEQ_14r_fields[] = 2648 { 2649 /* PATT_GEN_SEQ_14:0:15 */ 2650 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(981, 15, 0) 2651 }; 2652 static uint32_t BCMI_TSCE_XGXS_PATGEN_TXPKTCNT_Lr_fields[] = 2653 { 2654 /* TXPKTCNT_L:0:15 */ 2655 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1344, 15, 0) 2656 }; 2657 static uint32_t BCMI_TSCE_XGXS_PATGEN_TXPKTCNT_Ur_fields[] = 2658 { 2659 /* TXPKTCNT_U:0:15 */ 2660 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1345, 15, 0) 2661 }; 2662 static uint32_t BCMI_TSCE_XGXS_PHYID2r_fields[] = 2663 { 2664 /* REGID1:0:15 */ 2665 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1105, 15, 0) 2666 }; 2667 static uint32_t BCMI_TSCE_XGXS_PHYID3r_fields[] = 2668 { 2669 /* REGID2:0:15 */ 2670 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1106, 15, 0) 2671 }; 2672 static uint32_t BCMI_TSCE_XGXS_PKTGEN_CRCERRCNTr_fields[] = 2673 { 2674 /* CRCERRCNT:0:15 */ 2675 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(569, 15, 0) 2676 }; 2677 static uint32_t BCMI_TSCE_XGXS_PKTGEN_CTL1r_fields[] = 2678 { 2679 /* PKT_OR_PRTP:0:0 */ 2680 PHYMOD_SYMBOL_FIELD_ENCODE(1019, 0, 0), 2681 /* TX_TEST_PORT_SEL:1:2 */ 2682 PHYMOD_SYMBOL_FIELD_ENCODE(1412, 2, 1), 2683 /* LPI_EN:3:3 */ 2684 PHYMOD_SYMBOL_FIELD_ENCODE(845, 3, 3), 2685 /* PRTP_DATA_PATTERN_SEL:5:5 */ 2686 PHYMOD_SYMBOL_FIELD_ENCODE(1093, 5, 5), 2687 /* TX_PRTP_EN:6:6 */ 2688 PHYMOD_SYMBOL_FIELD_ENCODE(1406, 6, 6), 2689 /* RX_PORT_SEL:7:8 */ 2690 PHYMOD_SYMBOL_FIELD_ENCODE(1196, 8, 7), 2691 /* CLR_CRCCNT:9:9 */ 2692 PHYMOD_SYMBOL_FIELD_ENCODE(549, 9, 9), 2693 /* RX_MSBUS_TYPE:10:10 */ 2694 PHYMOD_SYMBOL_FIELD_ENCODE(1187, 10, 10), 2695 /* RX_PKT_CHECK_EN:11:11 */ 2696 PHYMOD_SYMBOL_FIELD_ENCODE(1194, 11, 11), 2697 /* NUMBER_PKT:12:15 */ 2698 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(947, 15, 12) 2699 }; 2700 static uint32_t BCMI_TSCE_XGXS_PKTGEN_CTL2r_fields[] = 2701 { 2702 /* IPG_SIZE:0:4 */ 2703 PHYMOD_SYMBOL_FIELD_ENCODE(777, 4, 0), 2704 /* PKT_SIZE:5:10 */ 2705 PHYMOD_SYMBOL_FIELD_ENCODE(1020, 10, 5), 2706 /* PAYLOAD_TYPE:11:13 */ 2707 PHYMOD_SYMBOL_FIELD_ENCODE(992, 13, 11), 2708 /* TX_MSBUS_TYPE:14:14 */ 2709 PHYMOD_SYMBOL_FIELD_ENCODE(1369, 14, 14), 2710 /* PKTGEN_EN:15:15 */ 2711 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1018, 15, 15) 2712 }; 2713 static uint32_t BCMI_TSCE_XGXS_PKTGEN_ERRMASK0r_fields[] = 2714 { 2715 /* ERROR_MASK_15_0:0:15 */ 2716 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(726, 15, 0) 2717 }; 2718 static uint32_t BCMI_TSCE_XGXS_PKTGEN_ERRMASK1r_fields[] = 2719 { 2720 /* ERROR_MASK_31_16:0:15 */ 2721 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(727, 15, 0) 2722 }; 2723 static uint32_t BCMI_TSCE_XGXS_PKTGEN_ERRMASK2r_fields[] = 2724 { 2725 /* ERROR_MASK_47_32:0:15 */ 2726 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(728, 15, 0) 2727 }; 2728 static uint32_t BCMI_TSCE_XGXS_PKTGEN_ERRMASK3r_fields[] = 2729 { 2730 /* ERROR_MASK_63_48:0:15 */ 2731 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(729, 15, 0) 2732 }; 2733 static uint32_t BCMI_TSCE_XGXS_PKTGEN_ERRMASK4r_fields[] = 2734 { 2735 /* ERROR_MASK_79_64:0:15 */ 2736 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(730, 15, 0) 2737 }; 2738 static uint32_t BCMI_TSCE_XGXS_PKTGEN_PAYLOADBYTESr_fields[] = 2739 { 2740 /* BYTE0:0:7 */ 2741 PHYMOD_SYMBOL_FIELD_ENCODE(355, 7, 0), 2742 /* BYTE1:8:15 */ 2743 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(356, 15, 8) 2744 }; 2745 static uint32_t BCMI_TSCE_XGXS_PKTGEN_PCS_SEEDA0r_fields[] = 2746 { 2747 /* SEEDA0:0:15 */ 2748 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1220, 15, 0) 2749 }; 2750 static uint32_t BCMI_TSCE_XGXS_PKTGEN_PCS_SEEDA1r_fields[] = 2751 { 2752 /* SEEDA1:0:15 */ 2753 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1221, 15, 0) 2754 }; 2755 static uint32_t BCMI_TSCE_XGXS_PKTGEN_PCS_SEEDA2r_fields[] = 2756 { 2757 /* SEEDA2:0:15 */ 2758 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1222, 15, 0) 2759 }; 2760 static uint32_t BCMI_TSCE_XGXS_PKTGEN_PCS_SEEDA3r_fields[] = 2761 { 2762 /* SEEDA3:0:9 */ 2763 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1223, 9, 0) 2764 }; 2765 static uint32_t BCMI_TSCE_XGXS_PKTGEN_PCS_SEEDB0r_fields[] = 2766 { 2767 /* SEEDB0:0:15 */ 2768 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1224, 15, 0) 2769 }; 2770 static uint32_t BCMI_TSCE_XGXS_PKTGEN_PCS_SEEDB1r_fields[] = 2771 { 2772 /* SEEDB1:0:15 */ 2773 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1225, 15, 0) 2774 }; 2775 static uint32_t BCMI_TSCE_XGXS_PKTGEN_PCS_SEEDB2r_fields[] = 2776 { 2777 /* SEEDB2:0:15 */ 2778 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1226, 15, 0) 2779 }; 2780 static uint32_t BCMI_TSCE_XGXS_PKTGEN_PCS_SEEDB3r_fields[] = 2781 { 2782 /* SEEDB3:0:9 */ 2783 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1227, 9, 0) 2784 }; 2785 static uint32_t BCMI_TSCE_XGXS_PKTGEN_PRTPCTLr_fields[] = 2786 { 2787 /* RX_PRTP_EN:4:4 */ 2788 PHYMOD_SYMBOL_FIELD_ENCODE(1197, 4, 4), 2789 /* ERRGEN_EN:5:8 */ 2790 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(721, 8, 5) 2791 }; 2792 static uint32_t BCMI_TSCE_XGXS_PKTGEN_PRTPERRCTRr_fields[] = 2793 { 2794 /* PRTP_ERR_COUNT:0:15 */ 2795 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1094, 15, 0) 2796 }; 2797 static uint32_t BCMI_TSCE_XGXS_PKTGEN_PRTPLOCKSTSr_fields[] = 2798 { 2799 /* PRTP_LOCK:0:0 */ 2800 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1095, 0, 0) 2801 }; 2802 static uint32_t BCMI_TSCE_XGXS_PLL_CAL_CTL0r_fields[] = 2803 { 2804 /* VCO_STEP_TIME:0:7 */ 2805 PHYMOD_SYMBOL_FIELD_ENCODE(1435, 7, 0), 2806 /* VCO_START_TIME:8:15 */ 2807 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1434, 15, 8) 2808 }; 2809 static uint32_t BCMI_TSCE_XGXS_PLL_CAL_CTL1r_fields[] = 2810 { 2811 /* RETRY_TIME:0:7 */ 2812 PHYMOD_SYMBOL_FIELD_ENCODE(1126, 7, 0), 2813 /* PRE_FREQ_DET_TIME:8:15 */ 2814 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1087, 15, 8) 2815 }; 2816 static uint32_t BCMI_TSCE_XGXS_PLL_CAL_CTL2r_fields[] = 2817 { 2818 /* WIN_CAL_CNTR:0:7 */ 2819 PHYMOD_SYMBOL_FIELD_ENCODE(1454, 7, 0), 2820 /* RES_CAL_CNTR:8:15 */ 2821 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1125, 15, 8) 2822 }; 2823 static uint32_t BCMI_TSCE_XGXS_PLL_CAL_CTL3r_fields[] = 2824 { 2825 /* FAST_SEARCH_MODE:0:0 */ 2826 PHYMOD_SYMBOL_FIELD_ENCODE(734, 0, 0), 2827 /* CAP_CNT_MASK_EN:1:1 */ 2828 PHYMOD_SYMBOL_FIELD_ENCODE(357, 1, 1), 2829 /* CAP_SEQ_CYA:2:2 */ 2830 PHYMOD_SYMBOL_FIELD_ENCODE(369, 2, 2), 2831 /* CAP_RESTART:3:3 */ 2832 PHYMOD_SYMBOL_FIELD_ENCODE(364, 3, 3), 2833 /* CAP_RETRY_EN:4:4 */ 2834 PHYMOD_SYMBOL_FIELD_ENCODE(365, 4, 4), 2835 /* CAP_FORCE_SLOWDOWN:5:5 */ 2836 PHYMOD_SYMBOL_FIELD_ENCODE(360, 5, 5), 2837 /* CAP_FORCE_SLOWDOWN_EN:6:6 */ 2838 PHYMOD_SYMBOL_FIELD_ENCODE(361, 6, 6), 2839 /* CAP_SELECT_M_EN:7:7 */ 2840 PHYMOD_SYMBOL_FIELD_ENCODE(368, 7, 7), 2841 /* CAP_SELECT_M:8:15 */ 2842 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(367, 15, 8) 2843 }; 2844 static uint32_t BCMI_TSCE_XGXS_PLL_CAL_CTL4r_fields[] = 2845 { 2846 /* PLL_LOCK_FRC_VAL:0:0 */ 2847 PHYMOD_SYMBOL_FIELD_ENCODE(1030, 0, 0), 2848 /* PLL_LOCK_FRC:1:1 */ 2849 PHYMOD_SYMBOL_FIELD_ENCODE(1029, 1, 1), 2850 /* PLL_FORCE_CAP_PASS:2:2 */ 2851 PHYMOD_SYMBOL_FIELD_ENCODE(1023, 2, 2), 2852 /* PLL_FORCE_CAP_PASS_EN:3:3 */ 2853 PHYMOD_SYMBOL_FIELD_ENCODE(1024, 3, 3), 2854 /* PLL_FORCE_CAP_DONE:4:4 */ 2855 PHYMOD_SYMBOL_FIELD_ENCODE(1021, 4, 4), 2856 /* PLL_FORCE_CAP_DONE_EN:5:5 */ 2857 PHYMOD_SYMBOL_FIELD_ENCODE(1022, 5, 5), 2858 /* PLL_FORCE_FPASS:6:6 */ 2859 PHYMOD_SYMBOL_FIELD_ENCODE(1027, 6, 6), 2860 /* PLL_FORCE_FDONE:7:7 */ 2861 PHYMOD_SYMBOL_FIELD_ENCODE(1025, 7, 7), 2862 /* PLL_FORCE_FDONE_EN:8:8 */ 2863 PHYMOD_SYMBOL_FIELD_ENCODE(1026, 8, 8), 2864 /* VCO_RST_EN:9:9 */ 2865 PHYMOD_SYMBOL_FIELD_ENCODE(1433, 9, 9), 2866 /* SLOWDN_XOR:10:10 */ 2867 PHYMOD_SYMBOL_FIELD_ENCODE(1256, 10, 10), 2868 /* FREQ_MONITOR_EN:11:11 */ 2869 PHYMOD_SYMBOL_FIELD_ENCODE(744, 11, 11), 2870 /* FREQ_DET_RESTART_EN:12:12 */ 2871 PHYMOD_SYMBOL_FIELD_ENCODE(740, 12, 12), 2872 /* FREQ_DET_RETRY_EN:13:13 */ 2873 PHYMOD_SYMBOL_FIELD_ENCODE(741, 13, 13), 2874 /* VCO_DONE_EN:14:14 */ 2875 PHYMOD_SYMBOL_FIELD_ENCODE(1432, 14, 14), 2876 /* PLL_SEQ_START:15:15 */ 2877 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1044, 15, 15) 2878 }; 2879 static uint32_t BCMI_TSCE_XGXS_PLL_CAL_CTL5r_fields[] = 2880 { 2881 /* REFCLK_DIVCNT:0:13 */ 2882 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1102, 13, 0) 2883 }; 2884 static uint32_t BCMI_TSCE_XGXS_PLL_CAL_CTL6r_fields[] = 2885 { 2886 /* REFCLK_DIVCNT_SEL:0:2 */ 2887 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1103, 2, 0) 2888 }; 2889 static uint32_t BCMI_TSCE_XGXS_PLL_CAL_CTL7r_fields[] = 2890 { 2891 /* PLL_MODE:0:3 */ 2892 PHYMOD_SYMBOL_FIELD_ENCODE(1038, 3, 0), 2893 /* RESCAL_FRC_VAL:4:7 */ 2894 PHYMOD_SYMBOL_FIELD_ENCODE(1117, 7, 4), 2895 /* RESCAL_FRC:8:8 */ 2896 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1116, 8, 8) 2897 }; 2898 static uint32_t BCMI_TSCE_XGXS_PLL_CAL_CTL_STS0r_fields[] = 2899 { 2900 /* PLL_LOCK_LH_LL:0:0 */ 2901 PHYMOD_SYMBOL_FIELD_ENCODE(1032, 0, 0), 2902 /* PLL_SEQ_PASS_LH_LL:1:1 */ 2903 PHYMOD_SYMBOL_FIELD_ENCODE(1043, 1, 1), 2904 /* PLL_SEQ_DONE_LH_LL:2:2 */ 2905 PHYMOD_SYMBOL_FIELD_ENCODE(1041, 2, 2), 2906 /* FREQ_PASS_SM_LH_LL:3:3 */ 2907 PHYMOD_SYMBOL_FIELD_ENCODE(746, 3, 3), 2908 /* FREQ_DONE_SM_LH_LL:4:4 */ 2909 PHYMOD_SYMBOL_FIELD_ENCODE(743, 4, 4), 2910 /* CAP_PASS_LH_LL:5:5 */ 2911 PHYMOD_SYMBOL_FIELD_ENCODE(363, 5, 5), 2912 /* CAP_DONE_LH_LL:6:6 */ 2913 PHYMOD_SYMBOL_FIELD_ENCODE(359, 6, 6), 2914 /* PLL_LOCK:8:8 */ 2915 PHYMOD_SYMBOL_FIELD_ENCODE(1028, 8, 8), 2916 /* PLL_SEQ_PASS:9:9 */ 2917 PHYMOD_SYMBOL_FIELD_ENCODE(1042, 9, 9), 2918 /* PLL_SEQ_DONE:10:10 */ 2919 PHYMOD_SYMBOL_FIELD_ENCODE(1040, 10, 10), 2920 /* FREQ_PASS_SM:11:11 */ 2921 PHYMOD_SYMBOL_FIELD_ENCODE(745, 11, 11), 2922 /* FREQ_DONE_SM:12:12 */ 2923 PHYMOD_SYMBOL_FIELD_ENCODE(742, 12, 12), 2924 /* CAP_PASS:13:13 */ 2925 PHYMOD_SYMBOL_FIELD_ENCODE(362, 13, 13), 2926 /* CAP_DONE:14:14 */ 2927 PHYMOD_SYMBOL_FIELD_ENCODE(358, 14, 14), 2928 /* LOST_PLL_LOCK_SM:15:15 */ 2929 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(842, 15, 15) 2930 }; 2931 static uint32_t BCMI_TSCE_XGXS_PLL_CAL_CTL_STS1r_fields[] = 2932 { 2933 /* CAP_SELECT:0:7 */ 2934 PHYMOD_SYMBOL_FIELD_ENCODE(366, 7, 0), 2935 /* RESCAL_IN:8:11 */ 2936 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1118, 11, 8) 2937 }; 2938 static uint32_t BCMI_TSCE_XGXS_PLL_CAL_CTL_STS_DBGr_fields[] = 2939 { 2940 /* DBG_SLOWDN:0:0 */ 2941 PHYMOD_SYMBOL_FIELD_ENCODE(581, 0, 0), 2942 /* DBG_SLOWDN_CHANGE:1:1 */ 2943 PHYMOD_SYMBOL_FIELD_ENCODE(582, 1, 1), 2944 /* DBG_FDBCK:2:2 */ 2945 PHYMOD_SYMBOL_FIELD_ENCODE(578, 2, 2), 2946 /* DBG_CAP_STATE_ONE_HOT:3:7 */ 2947 PHYMOD_SYMBOL_FIELD_ENCODE(573, 7, 3), 2948 /* DBG_PLL_STATE_ONE_HOT:8:15 */ 2949 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(580, 15, 8) 2950 }; 2951 static uint32_t BCMI_TSCE_XGXS_PMD_X1_CTLr_fields[] = 2952 { 2953 /* CORE_DP_H_RSTB:0:0 */ 2954 PHYMOD_SYMBOL_FIELD_ENCODE(560, 0, 0), 2955 /* POR_H_RSTB:1:1 */ 2956 PHYMOD_SYMBOL_FIELD_ENCODE(1064, 1, 1), 2957 /* PRAM_ABILITY:8:8 */ 2958 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1067, 8, 8) 2959 }; 2960 static uint32_t BCMI_TSCE_XGXS_PMD_X1_LATCH_STSr_fields[] = 2961 { 2962 /* PLL_LOCK_LL:0:0 */ 2963 PHYMOD_SYMBOL_FIELD_ENCODE(1033, 0, 0), 2964 /* PLL_LOCK_LH:1:1 */ 2965 PHYMOD_SYMBOL_FIELD_ENCODE(1031, 1, 1), 2966 /* TX_CLK_VLD_LL:2:2 */ 2967 PHYMOD_SYMBOL_FIELD_ENCODE(1348, 2, 2), 2968 /* TX_CLK_VLD_LH:3:3 */ 2969 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1347, 3, 3) 2970 }; 2971 static uint32_t BCMI_TSCE_XGXS_PMD_X1_MODEr_fields[] = 2972 { 2973 /* CORE_MODE:0:15 */ 2974 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(564, 15, 0) 2975 }; 2976 static uint32_t BCMI_TSCE_XGXS_PMD_X1_OVRRr_fields[] = 2977 { 2978 /* PLL_LOCK_OVRD:0:0 */ 2979 PHYMOD_SYMBOL_FIELD_ENCODE(1034, 0, 0), 2980 /* TX_CLK_VLD_OVRD:1:1 */ 2981 PHYMOD_SYMBOL_FIELD_ENCODE(1349, 1, 1), 2982 /* CORE_MODE_OEN:2:2 */ 2983 PHYMOD_SYMBOL_FIELD_ENCODE(565, 2, 2), 2984 /* CORE_DP_H_RSTB_OEN:3:3 */ 2985 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(561, 3, 3) 2986 }; 2987 static uint32_t BCMI_TSCE_XGXS_PMD_X1_STSr_fields[] = 2988 { 2989 /* PLL_LOCK_STS:0:0 */ 2990 PHYMOD_SYMBOL_FIELD_ENCODE(1035, 0, 0), 2991 /* TX_CLK_VLD_STS:1:1 */ 2992 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1350, 1, 1) 2993 }; 2994 static uint32_t BCMI_TSCE_XGXS_PMD_X4_CTLr_fields[] = 2995 { 2996 /* LN_DP_H_RSTB:0:0 */ 2997 PHYMOD_SYMBOL_FIELD_ENCODE(815, 0, 0), 2998 /* LN_H_RSTB:1:1 */ 2999 PHYMOD_SYMBOL_FIELD_ENCODE(818, 1, 1), 3000 /* LN_TX_H_PWRDN:2:2 */ 3001 PHYMOD_SYMBOL_FIELD_ENCODE(828, 2, 2), 3002 /* LN_RX_H_PWRDN:3:3 */ 3003 PHYMOD_SYMBOL_FIELD_ENCODE(820, 3, 3), 3004 /* TX_DISABLE:8:8 */ 3005 PHYMOD_SYMBOL_FIELD_ENCODE(1351, 8, 8), 3006 /* OSR_MODE:9:12 */ 3007 PHYMOD_SYMBOL_FIELD_ENCODE(954, 12, 9), 3008 /* RX_DME_EN:13:13 */ 3009 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1176, 13, 13) 3010 }; 3011 static uint32_t BCMI_TSCE_XGXS_PMD_X4_EEE_CTLr_fields[] = 3012 { 3013 /* TX_MODE:0:1 */ 3014 PHYMOD_SYMBOL_FIELD_ENCODE(1368, 1, 0), 3015 /* RX_MODE:2:2 */ 3016 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1186, 2, 2) 3017 }; 3018 static uint32_t BCMI_TSCE_XGXS_PMD_X4_EEE_STSr_fields[] = 3019 { 3020 /* ENERGY_DETECT:0:0 */ 3021 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(714, 0, 0) 3022 }; 3023 static uint32_t BCMI_TSCE_XGXS_PMD_X4_LATCH_STSr_fields[] = 3024 { 3025 /* RX_LOCK_LL:0:0 */ 3026 PHYMOD_SYMBOL_FIELD_ENCODE(1183, 0, 0), 3027 /* RX_LOCK_LH:1:1 */ 3028 PHYMOD_SYMBOL_FIELD_ENCODE(1182, 1, 1), 3029 /* SIGNAL_DETECT_LL:2:2 */ 3030 PHYMOD_SYMBOL_FIELD_ENCODE(1248, 2, 2), 3031 /* SIGNAL_DETECT_LH:3:3 */ 3032 PHYMOD_SYMBOL_FIELD_ENCODE(1247, 3, 3), 3033 /* RX_CLK_VLD_LL:4:4 */ 3034 PHYMOD_SYMBOL_FIELD_ENCODE(1173, 4, 4), 3035 /* RX_CLK_VLD_LH:5:5 */ 3036 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1172, 5, 5) 3037 }; 3038 static uint32_t BCMI_TSCE_XGXS_PMD_X4_MODEr_fields[] = 3039 { 3040 /* LANE_MODE:0:15 */ 3041 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(792, 15, 0) 3042 }; 3043 static uint32_t BCMI_TSCE_XGXS_PMD_X4_OVRRr_fields[] = 3044 { 3045 /* RX_LOCK_OVRD:0:0 */ 3046 PHYMOD_SYMBOL_FIELD_ENCODE(1184, 0, 0), 3047 /* SIGNAL_DETECT_OVRD:1:1 */ 3048 PHYMOD_SYMBOL_FIELD_ENCODE(1249, 1, 1), 3049 /* RX_CLK_VLD_OVRD:2:2 */ 3050 PHYMOD_SYMBOL_FIELD_ENCODE(1174, 2, 2), 3051 /* LANE_MODE_OEN:3:3 */ 3052 PHYMOD_SYMBOL_FIELD_ENCODE(793, 3, 3), 3053 /* OSR_MODE_OEN:4:4 */ 3054 PHYMOD_SYMBOL_FIELD_ENCODE(957, 4, 4), 3055 /* RX_DME_EN_OEN:5:5 */ 3056 PHYMOD_SYMBOL_FIELD_ENCODE(1177, 5, 5), 3057 /* TX_DISABLE_OEN:6:6 */ 3058 PHYMOD_SYMBOL_FIELD_ENCODE(1352, 6, 6), 3059 /* LN_DP_H_RSTB_OEN:7:7 */ 3060 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(816, 7, 7) 3061 }; 3062 static uint32_t BCMI_TSCE_XGXS_PMD_X4_STSr_fields[] = 3063 { 3064 /* RX_LOCK_STS:0:0 */ 3065 PHYMOD_SYMBOL_FIELD_ENCODE(1185, 0, 0), 3066 /* SIGNAL_DETECT_STS:1:1 */ 3067 PHYMOD_SYMBOL_FIELD_ENCODE(1252, 1, 1), 3068 /* RX_CLK_VLD_STS:2:2 */ 3069 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1175, 2, 2) 3070 }; 3071 static uint32_t BCMI_TSCE_XGXS_RX_X1_DEC_CTL0r_fields[] = 3072 { 3073 /* HYSTCOUNT:0:3 */ 3074 PHYMOD_SYMBOL_FIELD_ENCODE(767, 3, 0), 3075 /* GCWCOUNT:4:7 */ 3076 PHYMOD_SYMBOL_FIELD_ENCODE(751, 7, 4), 3077 /* SCWCOUNT:8:11 */ 3078 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1215, 11, 8) 3079 }; 3080 static uint32_t BCMI_TSCE_XGXS_RX_X1_DEC_CTL1r_fields[] = 3081 { 3082 /* CL49_BER_LIMIT:2:7 */ 3083 PHYMOD_SYMBOL_FIELD_ENCODE(446, 7, 2), 3084 /* CL82_BER_LIMIT:8:14 */ 3085 PHYMOD_SYMBOL_FIELD_ENCODE(529, 14, 8), 3086 /* SET_BER_WINDOW_512:15:15 */ 3087 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1230, 15, 15) 3088 }; 3089 static uint32_t BCMI_TSCE_XGXS_RX_X1_DESKEW_WINSr_fields[] = 3090 { 3091 /* CL48_DSWIN8B10B:0:3 */ 3092 PHYMOD_SYMBOL_FIELD_ENCODE(422, 3, 0), 3093 /* CL48_DSWIN64B66B:4:6 */ 3094 PHYMOD_SYMBOL_FIELD_ENCODE(421, 6, 4), 3095 /* CL82_DSWIN:7:11 */ 3096 PHYMOD_SYMBOL_FIELD_ENCODE(531, 11, 7), 3097 /* CL82_DSWIN_100G:12:15 */ 3098 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(532, 15, 12) 3099 }; 3100 static uint32_t BCMI_TSCE_XGXS_RX_X1_INVALID_SHCNT_CL82r_fields[] = 3101 { 3102 /* CL82_INVALID_SH_CNT:0:11 */ 3103 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(534, 11, 0) 3104 }; 3105 static uint32_t BCMI_TSCE_XGXS_RX_X1_SCW0r_fields[] = 3106 { 3107 /* SCW0:0:15 */ 3108 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1205, 15, 0) 3109 }; 3110 static uint32_t BCMI_TSCE_XGXS_RX_X1_SCW0_MASKr_fields[] = 3111 { 3112 /* SCW0_MASK:0:15 */ 3113 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1206, 15, 0) 3114 }; 3115 static uint32_t BCMI_TSCE_XGXS_RX_X1_SCW1r_fields[] = 3116 { 3117 /* SCW1:0:15 */ 3118 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1207, 15, 0) 3119 }; 3120 static uint32_t BCMI_TSCE_XGXS_RX_X1_SCW1_MASKr_fields[] = 3121 { 3122 /* SCW1_MASK:0:15 */ 3123 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1208, 15, 0) 3124 }; 3125 static uint32_t BCMI_TSCE_XGXS_RX_X1_SCW2r_fields[] = 3126 { 3127 /* SCW2:0:15 */ 3128 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1209, 15, 0) 3129 }; 3130 static uint32_t BCMI_TSCE_XGXS_RX_X1_SCW2_MASKr_fields[] = 3131 { 3132 /* SCW2_MASK:0:15 */ 3133 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1210, 15, 0) 3134 }; 3135 static uint32_t BCMI_TSCE_XGXS_RX_X1_SCW3r_fields[] = 3136 { 3137 /* SCW3:0:15 */ 3138 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1211, 15, 0) 3139 }; 3140 static uint32_t BCMI_TSCE_XGXS_RX_X1_SCW3_MASKr_fields[] = 3141 { 3142 /* SCW3_MASK:0:15 */ 3143 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1212, 15, 0) 3144 }; 3145 static uint32_t BCMI_TSCE_XGXS_RX_X1_SCW4r_fields[] = 3146 { 3147 /* SCW4:0:1 */ 3148 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1213, 1, 0) 3149 }; 3150 static uint32_t BCMI_TSCE_XGXS_RX_X1_SCW4_MASKr_fields[] = 3151 { 3152 /* SCW4_MASK:0:1 */ 3153 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1214, 1, 0) 3154 }; 3155 static uint32_t BCMI_TSCE_XGXS_RX_X1_SHCNT_CL49r_fields[] = 3156 { 3157 /* CL49_INVALID_SH_CNT:0:7 */ 3158 PHYMOD_SYMBOL_FIELD_ENCODE(448, 7, 0), 3159 /* CL49_VALID_SH_CNT:8:15 */ 3160 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(464, 15, 8) 3161 }; 3162 static uint32_t BCMI_TSCE_XGXS_RX_X1_VALID_SHCNT_CL82r_fields[] = 3163 { 3164 /* CL82_VALID_SH_CNT:0:11 */ 3165 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(543, 11, 0) 3166 }; 3167 static uint32_t BCMI_TSCE_XGXS_RX_X2_MISC0r_fields[] = 3168 { 3169 /* BYPASS_CL82RXSM:0:0 */ 3170 PHYMOD_SYMBOL_FIELD_ENCODE(354, 0, 0), 3171 /* DIS_CL82_BERMON:1:1 */ 3172 PHYMOD_SYMBOL_FIELD_ENCODE(688, 1, 1), 3173 /* BRCM_MODE_USE_K20PT5:8:8 */ 3174 PHYMOD_SYMBOL_FIELD_ENCODE(348, 8, 8), 3175 /* CHK_END_EN:10:10 */ 3176 PHYMOD_SYMBOL_FIELD_ENCODE(393, 10, 10), 3177 /* LINK_EN:12:12 */ 3178 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(807, 12, 12) 3179 }; 3180 static uint32_t BCMI_TSCE_XGXS_RX_X2_MISC1r_fields[] = 3181 { 3182 /* CL82_RX_RF_ENABLE:0:0 */ 3183 PHYMOD_SYMBOL_FIELD_ENCODE(539, 0, 0), 3184 /* CL82_RX_LF_ENABLE:1:1 */ 3185 PHYMOD_SYMBOL_FIELD_ENCODE(537, 1, 1), 3186 /* CL48_RX_RF_ENABLE:2:2 */ 3187 PHYMOD_SYMBOL_FIELD_ENCODE(426, 2, 2), 3188 /* CL48_RX_LF_ENABLE:3:3 */ 3189 PHYMOD_SYMBOL_FIELD_ENCODE(423, 3, 3), 3190 /* CL48_RX_LI_ENABLE:8:8 */ 3191 PHYMOD_SYMBOL_FIELD_ENCODE(424, 8, 8), 3192 /* CL82_RX_LI_ENABLE:9:9 */ 3193 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(538, 9, 9) 3194 }; 3195 static uint32_t BCMI_TSCE_XGXS_RX_X2_QRSVD0r_fields[] = 3196 { 3197 /* CL48_RX_QRSVDCTRL:1:4 */ 3198 PHYMOD_SYMBOL_FIELD_ENCODE(425, 4, 1), 3199 /* QRSVDSWAP:5:14 */ 3200 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1101, 14, 5) 3201 }; 3202 static uint32_t BCMI_TSCE_XGXS_RX_X2_QRSVD1r_fields[] = 3203 { 3204 /* QRSVD2_8_2:0:6 */ 3205 PHYMOD_SYMBOL_FIELD_ENCODE(1099, 6, 0), 3206 /* QRSVD1:7:15 */ 3207 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1097, 15, 7) 3208 }; 3209 static uint32_t BCMI_TSCE_XGXS_RX_X2_QRSVD2r_fields[] = 3210 { 3211 /* QRSVD3:5:13 */ 3212 PHYMOD_SYMBOL_FIELD_ENCODE(1100, 13, 5), 3213 /* QRSVD2_1_0:14:15 */ 3214 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1098, 15, 14) 3215 }; 3216 static uint32_t BCMI_TSCE_XGXS_RX_X2_SKEW_STS0r_fields[] = 3217 { 3218 /* CL48_SKEWACQ_STATE_D_3:3:5 */ 3219 PHYMOD_SYMBOL_FIELD_ENCODE(430, 5, 3), 3220 /* CL48_SKEWACQ_STATE_D_2:6:8 */ 3221 PHYMOD_SYMBOL_FIELD_ENCODE(429, 8, 6), 3222 /* CL48_SKEWACQ_STATE_D_1:9:11 */ 3223 PHYMOD_SYMBOL_FIELD_ENCODE(428, 11, 9), 3224 /* CL48_SKEWACQ_STATE_D_0:12:14 */ 3225 PHYMOD_SYMBOL_FIELD_ENCODE(427, 14, 12), 3226 /* CL48_SKEW_STATUS:15:15 */ 3227 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(432, 15, 15) 3228 }; 3229 static uint32_t BCMI_TSCE_XGXS_RX_X2_SKEW_STS1r_fields[] = 3230 { 3231 /* CL48_SKEWACQ_STATE_L:0:7 */ 3232 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(431, 7, 0) 3233 }; 3234 static uint32_t BCMI_TSCE_XGXS_RX_X4_BARREL_SHIFTER_STr_fields[] = 3235 { 3236 /* SHIFT_AMMOUNT:0:7 */ 3237 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1239, 7, 0) 3238 }; 3239 static uint32_t BCMI_TSCE_XGXS_RX_X4_BERCNTr_fields[] = 3240 { 3241 /* BER_COUNT_PER_LN:0:7 */ 3242 PHYMOD_SYMBOL_FIELD_ENCODE(340, 7, 0), 3243 /* BIP_ERROR_COUNT_PER_LANE:8:15 */ 3244 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(342, 15, 8) 3245 }; 3246 static uint32_t BCMI_TSCE_XGXS_RX_X4_CL36_RX0r_fields[] = 3247 { 3248 /* CL36_EN:0:0 */ 3249 PHYMOD_SYMBOL_FIELD_ENCODE(398, 0, 0), 3250 /* REORDER_EN:1:1 */ 3251 PHYMOD_SYMBOL_FIELD_ENCODE(1112, 1, 1), 3252 /* DISABLE_CARRIER_EXTEND:2:2 */ 3253 PHYMOD_SYMBOL_FIELD_ENCODE(685, 2, 2), 3254 /* CL36_FORCE_COMMA_ALIGN_ENABLE:3:3 */ 3255 PHYMOD_SYMBOL_FIELD_ENCODE(400, 3, 3), 3256 /* CL36_BER_EN:5:5 */ 3257 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(397, 5, 5) 3258 }; 3259 static uint32_t BCMI_TSCE_XGXS_RX_X4_CL49_LOCK_FSM_STSr_fields[] = 3260 { 3261 /* LSM_CURR_STATE:0:1 */ 3262 PHYMOD_SYMBOL_FIELD_ENCODE(864, 1, 0), 3263 /* LSM_HIS_STATE:2:4 */ 3264 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(865, 4, 2) 3265 }; 3266 static uint32_t BCMI_TSCE_XGXS_RX_X4_CL82_AM_LATCH_STSr_fields[] = 3267 { 3268 /* AM_LOCK_HIS_STATE:0:9 */ 3269 PHYMOD_SYMBOL_FIELD_ENCODE(195, 9, 0), 3270 /* AMRKR_SPACING_ERR_LATCH_MUX:10:10 */ 3271 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(17, 10, 10) 3272 }; 3273 static uint32_t BCMI_TSCE_XGXS_RX_X4_CL82_AM_LIVE_STSr_fields[] = 3274 { 3275 /* AM_LOCK_STATE:0:9 */ 3276 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(198, 9, 0) 3277 }; 3278 static uint32_t BCMI_TSCE_XGXS_RX_X4_DEC_CTL0r_fields[] = 3279 { 3280 /* BLOCK_SYNC_MODE:0:2 */ 3281 PHYMOD_SYMBOL_FIELD_ENCODE(343, 2, 0), 3282 /* CL49_RX_RF_ENABLE:4:4 */ 3283 PHYMOD_SYMBOL_FIELD_ENCODE(455, 4, 4), 3284 /* CL49_RX_LF_ENABLE:5:5 */ 3285 PHYMOD_SYMBOL_FIELD_ENCODE(453, 5, 5), 3286 /* CL49_RX_LI_ENABLE:6:6 */ 3287 PHYMOD_SYMBOL_FIELD_ENCODE(454, 6, 6), 3288 /* DISABLE_CL49_BERMON:8:8 */ 3289 PHYMOD_SYMBOL_FIELD_ENCODE(686, 8, 8), 3290 /* HG2_CODEC:9:9 */ 3291 PHYMOD_SYMBOL_FIELD_ENCODE(755, 9, 9), 3292 /* CL48_CGBAD_EN:10:10 */ 3293 PHYMOD_SYMBOL_FIELD_ENCODE(420, 10, 10), 3294 /* CL48_SYNCACQ_EN:11:11 */ 3295 PHYMOD_SYMBOL_FIELD_ENCODE(433, 11, 11), 3296 /* HG2_ENABLE:12:12 */ 3297 PHYMOD_SYMBOL_FIELD_ENCODE(756, 12, 12), 3298 /* HG2_MESSAGE_INVALID_CODE_ENABLE:13:13 */ 3299 PHYMOD_SYMBOL_FIELD_ENCODE(757, 13, 13), 3300 /* R_TEST_MODE_CFG:14:14 */ 3301 PHYMOD_SYMBOL_FIELD_ENCODE(1200, 14, 14), 3302 /* BYPASS_CL49RXSM:15:15 */ 3303 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(353, 15, 15) 3304 }; 3305 static uint32_t BCMI_TSCE_XGXS_RX_X4_DEC_CTL1r_fields[] = 3306 { 3307 /* B66DEC_CGBAD_EN:0:0 */ 3308 PHYMOD_SYMBOL_FIELD_ENCODE(297, 0, 0), 3309 /* B66DEC_SYNCERRCOUNT_EN:1:1 */ 3310 PHYMOD_SYMBOL_FIELD_ENCODE(305, 1, 1), 3311 /* B66DEC_KCODE66ERRCOUNT_EN:2:2 */ 3312 PHYMOD_SYMBOL_FIELD_ENCODE(301, 2, 2), 3313 /* B66DEC_FAULT_DET_EN:3:3 */ 3314 PHYMOD_SYMBOL_FIELD_ENCODE(300, 3, 3), 3315 /* B66DEC_PROG_TL_CHAR:4:11 */ 3316 PHYMOD_SYMBOL_FIELD_ENCODE(303, 11, 4), 3317 /* B66DEC_PROG_TL_EN:12:12 */ 3318 PHYMOD_SYMBOL_FIELD_ENCODE(304, 12, 12), 3319 /* B66DEC_NOBLOCKLOCK_DOUT_SEL:13:14 */ 3320 PHYMOD_SYMBOL_FIELD_ENCODE(302, 14, 13), 3321 /* B66DEC_DOUT_ERRORS_IF_BAD_SYNC:15:15 */ 3322 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(298, 15, 15) 3323 }; 3324 static uint32_t BCMI_TSCE_XGXS_RX_X4_DEC_STS0r_fields[] = 3325 { 3326 /* CL49_RXSM_CURRENT_STATE:0:2 */ 3327 PHYMOD_SYMBOL_FIELD_ENCODE(451, 2, 0), 3328 /* CL49_RXSM_HISTORY_STATE:3:10 */ 3329 PHYMOD_SYMBOL_FIELD_ENCODE(452, 10, 3), 3330 /* CL49_R_TYPE_CODED:12:15 */ 3331 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(456, 15, 12) 3332 }; 3333 static uint32_t BCMI_TSCE_XGXS_RX_X4_DEC_STS1r_fields[] = 3334 { 3335 /* CL49_BERMON_CURRENT_STATE:0:4 */ 3336 PHYMOD_SYMBOL_FIELD_ENCODE(444, 4, 0), 3337 /* CL49_BERMON_HISTORY_STATE:5:9 */ 3338 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(445, 9, 5) 3339 }; 3340 static uint32_t BCMI_TSCE_XGXS_RX_X4_DEC_STS2r_fields[] = 3341 { 3342 /* KCODE66ERRCOUNT:0:7 */ 3343 PHYMOD_SYMBOL_FIELD_ENCODE(778, 7, 0), 3344 /* SYNC66ERRCOUNT:8:15 */ 3345 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1272, 15, 8) 3346 }; 3347 static uint32_t BCMI_TSCE_XGXS_RX_X4_DEC_STS3r_fields[] = 3348 { 3349 /* CL49IEEE_ERRORED_BLOCKS:2:9 */ 3350 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(443, 9, 2) 3351 }; 3352 static uint32_t BCMI_TSCE_XGXS_RX_X4_DEC_STS4r_fields[] = 3353 { 3354 /* CL48_SYNCACQ_STATE_L:4:14 */ 3355 PHYMOD_SYMBOL_FIELD_ENCODE(438, 14, 4), 3356 /* B66DEC_FAULT_DET:15:15 */ 3357 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(299, 15, 15) 3358 }; 3359 static uint32_t BCMI_TSCE_XGXS_RX_X4_DEC_STS5r_fields[] = 3360 { 3361 /* CL48_SYNCACQ_STATE_D_3:0:3 */ 3362 PHYMOD_SYMBOL_FIELD_ENCODE(437, 3, 0), 3363 /* CL48_SYNCACQ_STATE_D_2:4:7 */ 3364 PHYMOD_SYMBOL_FIELD_ENCODE(436, 7, 4), 3365 /* CL48_SYNCACQ_STATE_D_1:8:11 */ 3366 PHYMOD_SYMBOL_FIELD_ENCODE(435, 11, 8), 3367 /* CL48_SYNCACQ_STATE_D_0:12:15 */ 3368 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(434, 15, 12) 3369 }; 3370 static uint32_t BCMI_TSCE_XGXS_RX_X4_FEC0r_fields[] = 3371 { 3372 /* FAST_LOCK_EN:9:9 */ 3373 PHYMOD_SYMBOL_FIELD_ENCODE(733, 9, 9), 3374 /* DBG_ENABLE:10:10 */ 3375 PHYMOD_SYMBOL_FIELD_ENCODE(574, 10, 10), 3376 /* ERROR_EN_OVR_VAL:11:11 */ 3377 PHYMOD_SYMBOL_FIELD_ENCODE(725, 11, 11), 3378 /* ERROR_EN_OVR:12:12 */ 3379 PHYMOD_SYMBOL_FIELD_ENCODE(724, 12, 12), 3380 /* FEC_ERR_ENABLE:13:13 */ 3381 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(739, 13, 13) 3382 }; 3383 static uint32_t BCMI_TSCE_XGXS_RX_X4_FEC1r_fields[] = 3384 { 3385 /* DBG_ERR_MODE:0:0 */ 3386 PHYMOD_SYMBOL_FIELD_ENCODE(577, 0, 0), 3387 /* BURST_ERR_STATUS_MODE:1:1 */ 3388 PHYMOD_SYMBOL_FIELD_ENCODE(352, 1, 1), 3389 /* DEC_MAX_PM:2:7 */ 3390 PHYMOD_SYMBOL_FIELD_ENCODE(590, 7, 2), 3391 /* INVALID_PARITY_CNT:8:11 */ 3392 PHYMOD_SYMBOL_FIELD_ENCODE(774, 11, 8), 3393 /* GOOD_PARITY_CNT:12:14 */ 3394 PHYMOD_SYMBOL_FIELD_ENCODE(752, 14, 12), 3395 /* FEC_ERROR_CODE_ALL:15:15 */ 3396 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(738, 15, 15) 3397 }; 3398 static uint32_t BCMI_TSCE_XGXS_RX_X4_FEC2r_fields[] = 3399 { 3400 /* DEC_GAP_COUNT_MODE:1:1 */ 3401 PHYMOD_SYMBOL_FIELD_ENCODE(589, 1, 1), 3402 /* DEC_17B_BURST_GAP_COUNT:2:4 */ 3403 PHYMOD_SYMBOL_FIELD_ENCODE(586, 4, 2), 3404 /* DEC_18B_BURST_GAP_COUNT:5:7 */ 3405 PHYMOD_SYMBOL_FIELD_ENCODE(587, 7, 5), 3406 /* DEC_19B_BURST_GAP_COUNT:8:10 */ 3407 PHYMOD_SYMBOL_FIELD_ENCODE(588, 10, 8), 3408 /* DEC_PM_MODE:11:15 */ 3409 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(591, 15, 11) 3410 }; 3411 static uint32_t BCMI_TSCE_XGXS_RX_X4_FEC_BURST_ERR_STSHr_fields[] = 3412 { 3413 /* BURST_ERR_STATUSH:0:15 */ 3414 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(350, 15, 0) 3415 }; 3416 static uint32_t BCMI_TSCE_XGXS_RX_X4_FEC_BURST_ERR_STSLr_fields[] = 3417 { 3418 /* BURST_ERR_STATUSL:0:15 */ 3419 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(351, 15, 0) 3420 }; 3421 static uint32_t BCMI_TSCE_XGXS_RX_X4_FEC_CORRBLKSHr_fields[] = 3422 { 3423 /* CORCOUNTH:0:15 */ 3424 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(558, 15, 0) 3425 }; 3426 static uint32_t BCMI_TSCE_XGXS_RX_X4_FEC_CORRBLKSLr_fields[] = 3427 { 3428 /* CORCOUNTL:0:15 */ 3429 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(559, 15, 0) 3430 }; 3431 static uint32_t BCMI_TSCE_XGXS_RX_X4_FEC_DBG_ERRAHr_fields[] = 3432 { 3433 /* DBG_ERRH:0:15 */ 3434 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(575, 15, 0) 3435 }; 3436 static uint32_t BCMI_TSCE_XGXS_RX_X4_FEC_DBG_ERRLr_fields[] = 3437 { 3438 /* DBG_ERRL:0:15 */ 3439 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(576, 15, 0) 3440 }; 3441 static uint32_t BCMI_TSCE_XGXS_RX_X4_FEC_UNCORRBLKSHr_fields[] = 3442 { 3443 /* UNCORCOUNTH:0:15 */ 3444 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1430, 15, 0) 3445 }; 3446 static uint32_t BCMI_TSCE_XGXS_RX_X4_FEC_UNCORRBLKSLr_fields[] = 3447 { 3448 /* UNCORCOUNTL:0:15 */ 3449 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1431, 15, 0) 3450 }; 3451 static uint32_t BCMI_TSCE_XGXS_RX_X4_GBOX_STSr_fields[] = 3452 { 3453 /* GBOX_UNDERFLOW_ERR:0:0 */ 3454 PHYMOD_SYMBOL_FIELD_ENCODE(750, 0, 0), 3455 /* GBOX_OVERFLOW_ERR:1:1 */ 3456 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(749, 1, 1) 3457 }; 3458 static uint32_t BCMI_TSCE_XGXS_RX_X4_LNK_CTLr_fields[] = 3459 { 3460 /* LATCH_LINKDOWN_ENABLE:0:0 */ 3461 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(798, 0, 0) 3462 }; 3463 static uint32_t BCMI_TSCE_XGXS_RX_X4_PCS_CTL0r_fields[] = 3464 { 3465 /* BRCM64B66_DESCRAMBLER_ENABLE:1:1 */ 3466 PHYMOD_SYMBOL_FIELD_ENCODE(346, 1, 1), 3467 /* LPI_ENABLE:2:2 */ 3468 PHYMOD_SYMBOL_FIELD_ENCODE(846, 2, 2), 3469 /* CL36BYTEDELETEMODE:3:4 */ 3470 PHYMOD_SYMBOL_FIELD_ENCODE(395, 4, 3), 3471 /* DESC2_MODE:5:7 */ 3472 PHYMOD_SYMBOL_FIELD_ENCODE(592, 7, 5), 3473 /* DESKEWMODE:8:10 */ 3474 PHYMOD_SYMBOL_FIELD_ENCODE(596, 10, 8), 3475 /* DECODERMODE:11:13 */ 3476 PHYMOD_SYMBOL_FIELD_ENCODE(584, 13, 11), 3477 /* DESCRAMBLERMODE:14:15 */ 3478 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(594, 15, 14) 3479 }; 3480 static uint32_t BCMI_TSCE_XGXS_RX_X4_PCS_LATCH_STS0r_fields[] = 3481 { 3482 /* SYNC_STATUS_LL:6:6 */ 3483 PHYMOD_SYMBOL_FIELD_ENCODE(1279, 6, 6), 3484 /* SYNC_STATUS_LH:7:7 */ 3485 PHYMOD_SYMBOL_FIELD_ENCODE(1278, 7, 7), 3486 /* LINK_STATUS_LL:8:8 */ 3487 PHYMOD_SYMBOL_FIELD_ENCODE(814, 8, 8), 3488 /* LINK_STATUS_LH:9:9 */ 3489 PHYMOD_SYMBOL_FIELD_ENCODE(813, 9, 9), 3490 /* HI_BER_LL:10:10 */ 3491 PHYMOD_SYMBOL_FIELD_ENCODE(760, 10, 10), 3492 /* HI_BER_LH:11:11 */ 3493 PHYMOD_SYMBOL_FIELD_ENCODE(759, 11, 11), 3494 /* DESKEW_STATUS_LL:12:12 */ 3495 PHYMOD_SYMBOL_FIELD_ENCODE(607, 12, 12), 3496 /* DESKEW_STATUS_LH:13:13 */ 3497 PHYMOD_SYMBOL_FIELD_ENCODE(606, 13, 13), 3498 /* AM_LOCK_LL:14:14 */ 3499 PHYMOD_SYMBOL_FIELD_ENCODE(197, 14, 14), 3500 /* AM_LOCK_LH:15:15 */ 3501 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(196, 15, 15) 3502 }; 3503 static uint32_t BCMI_TSCE_XGXS_RX_X4_PCS_LATCH_STS1r_fields[] = 3504 { 3505 /* LPI_RECEIVED_LH:3:3 */ 3506 PHYMOD_SYMBOL_FIELD_ENCODE(848, 3, 3), 3507 /* RESERVED_ORDERED_BYTE_3:4:11 */ 3508 PHYMOD_SYMBOL_FIELD_ENCODE(1119, 11, 4), 3509 /* RESERVED_ORDERED_SET_LH:12:12 */ 3510 PHYMOD_SYMBOL_FIELD_ENCODE(1120, 12, 12), 3511 /* LINK_INTERRUPT_LH:13:13 */ 3512 PHYMOD_SYMBOL_FIELD_ENCODE(811, 13, 13), 3513 /* REMOTE_FAULT_LH:14:14 */ 3514 PHYMOD_SYMBOL_FIELD_ENCODE(1109, 14, 14), 3515 /* LOCAL_FAULT_LH:15:15 */ 3516 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(832, 15, 15) 3517 }; 3518 static uint32_t BCMI_TSCE_XGXS_RX_X4_PCS_LIVE_STSr_fields[] = 3519 { 3520 /* SYNC_STATUS:0:0 */ 3521 PHYMOD_SYMBOL_FIELD_ENCODE(1277, 0, 0), 3522 /* LINK_STATUS:1:1 */ 3523 PHYMOD_SYMBOL_FIELD_ENCODE(812, 1, 1), 3524 /* HI_BER:2:2 */ 3525 PHYMOD_SYMBOL_FIELD_ENCODE(758, 2, 2), 3526 /* DESKEW_STATUS:3:3 */ 3527 PHYMOD_SYMBOL_FIELD_ENCODE(605, 3, 3), 3528 /* AM_LOCK:4:4 */ 3529 PHYMOD_SYMBOL_FIELD_ENCODE(194, 4, 4), 3530 /* LPI_RECEIVED:5:5 */ 3531 PHYMOD_SYMBOL_FIELD_ENCODE(847, 5, 5), 3532 /* LINK_INTERRUPT:6:6 */ 3533 PHYMOD_SYMBOL_FIELD_ENCODE(810, 6, 6), 3534 /* REMOTE_FAULT:7:7 */ 3535 PHYMOD_SYMBOL_FIELD_ENCODE(1107, 7, 7), 3536 /* LOCAL_FAULT:8:8 */ 3537 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(831, 8, 8) 3538 }; 3539 static uint32_t BCMI_TSCE_XGXS_RX_X4_PMA_CTL0r_fields[] = 3540 { 3541 /* RSTB_LANE:0:0 */ 3542 PHYMOD_SYMBOL_FIELD_ENCODE(1160, 0, 0), 3543 /* RX_GBOX_AFRST_EN:1:1 */ 3544 PHYMOD_SYMBOL_FIELD_ENCODE(1181, 1, 1), 3545 /* OS_MODE:3:6 */ 3546 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(960, 6, 3) 3547 }; 3548 static uint32_t BCMI_TSCE_XGXS_RX_X4_SYNCACQ_STS0r_fields[] = 3549 { 3550 /* CL36_SYNCACQ_STATE_CODED_PER_LN:0:3 */ 3551 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(402, 3, 0) 3552 }; 3553 static uint32_t BCMI_TSCE_XGXS_RX_X4_SYNCACQ_STS1r_fields[] = 3554 { 3555 /* CL36_SYNCACQ_HIS_STATE_PER_LN:0:12 */ 3556 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(401, 12, 0) 3557 }; 3558 static uint32_t BCMI_TSCE_XGXS_RX_X4_T12_BARREL_SHIFTER_STr_fields[] = 3559 { 3560 /* SHIFT_AMMOUNT:0:7 */ 3561 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1239, 7, 0) 3562 }; 3563 static uint32_t BCMI_TSCE_XGXS_RX_X4_T12_BERCNTr_fields[] = 3564 { 3565 /* BIP_ERROR_COUNT_PER_LANE:0:7 */ 3566 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(342, 7, 0) 3567 }; 3568 static uint32_t BCMI_TSCE_XGXS_RX_X4_T12_CL49_LOCK_FSM_STSr_fields[] = 3569 { 3570 /* LSM_CURR_STATE:0:1 */ 3571 PHYMOD_SYMBOL_FIELD_ENCODE(864, 1, 0), 3572 /* LSM_HIS_STATE:2:4 */ 3573 PHYMOD_SYMBOL_FIELD_ENCODE(865, 4, 2), 3574 /* ALIGN_STATUS_CL82:7:7 */ 3575 PHYMOD_SYMBOL_FIELD_ENCODE(16, 7, 7), 3576 /* RMLD_STATUS:8:15 */ 3577 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1154, 15, 8) 3578 }; 3579 static uint32_t BCMI_TSCE_XGXS_RX_X4_T12_CL82_PCS_LATCH_STSr_fields[] = 3580 { 3581 /* AM_LOCK_HIS_STATE:0:9 */ 3582 PHYMOD_SYMBOL_FIELD_ENCODE(195, 9, 0), 3583 /* AMRKR_SPACING_ERR_LATCH_MUX:10:10 */ 3584 PHYMOD_SYMBOL_FIELD_ENCODE(17, 10, 10), 3585 /* SYNC_STATUS_LL:12:12 */ 3586 PHYMOD_SYMBOL_FIELD_ENCODE(1279, 12, 12), 3587 /* SYNC_STATUS_LH:13:13 */ 3588 PHYMOD_SYMBOL_FIELD_ENCODE(1278, 13, 13), 3589 /* AM_LOCK_LL:14:14 */ 3590 PHYMOD_SYMBOL_FIELD_ENCODE(197, 14, 14), 3591 /* AM_LOCK_LH:15:15 */ 3592 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(196, 15, 15) 3593 }; 3594 static uint32_t BCMI_TSCE_XGXS_RX_X4_T12_CL82_PCS_LIVE_STSr_fields[] = 3595 { 3596 /* AM_LOCK_STATE:0:9 */ 3597 PHYMOD_SYMBOL_FIELD_ENCODE(198, 9, 0), 3598 /* SYNC_STATUS:14:14 */ 3599 PHYMOD_SYMBOL_FIELD_ENCODE(1277, 14, 14), 3600 /* AM_LOCK:15:15 */ 3601 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(194, 15, 15) 3602 }; 3603 static uint32_t BCMI_TSCE_XGXS_RX_X4_T12_FEC0r_fields[] = 3604 { 3605 /* FAST_LOCK_EN:9:9 */ 3606 PHYMOD_SYMBOL_FIELD_ENCODE(733, 9, 9), 3607 /* DBG_ENABLE:10:10 */ 3608 PHYMOD_SYMBOL_FIELD_ENCODE(574, 10, 10), 3609 /* ERROR_EN_OVR_VAL:11:11 */ 3610 PHYMOD_SYMBOL_FIELD_ENCODE(725, 11, 11), 3611 /* ERROR_EN_OVR:12:12 */ 3612 PHYMOD_SYMBOL_FIELD_ENCODE(724, 12, 12), 3613 /* FEC_ERR_ENABLE:13:13 */ 3614 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(739, 13, 13) 3615 }; 3616 static uint32_t BCMI_TSCE_XGXS_RX_X4_T12_FEC1r_fields[] = 3617 { 3618 /* DBG_ERR_MODE:0:0 */ 3619 PHYMOD_SYMBOL_FIELD_ENCODE(577, 0, 0), 3620 /* BURST_ERR_STATUS_MODE:1:1 */ 3621 PHYMOD_SYMBOL_FIELD_ENCODE(352, 1, 1), 3622 /* DEC_MAX_PM:2:7 */ 3623 PHYMOD_SYMBOL_FIELD_ENCODE(590, 7, 2), 3624 /* INVALID_PARITY_CNT:8:11 */ 3625 PHYMOD_SYMBOL_FIELD_ENCODE(774, 11, 8), 3626 /* GOOD_PARITY_CNT:12:14 */ 3627 PHYMOD_SYMBOL_FIELD_ENCODE(752, 14, 12), 3628 /* FEC_ERROR_CODE_ALL:15:15 */ 3629 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(738, 15, 15) 3630 }; 3631 static uint32_t BCMI_TSCE_XGXS_RX_X4_T12_FEC2r_fields[] = 3632 { 3633 /* DEC_GAP_COUNT_MODE:1:1 */ 3634 PHYMOD_SYMBOL_FIELD_ENCODE(589, 1, 1), 3635 /* DEC_17B_BURST_GAP_COUNT:2:4 */ 3636 PHYMOD_SYMBOL_FIELD_ENCODE(586, 4, 2), 3637 /* DEC_18B_BURST_GAP_COUNT:5:7 */ 3638 PHYMOD_SYMBOL_FIELD_ENCODE(587, 7, 5), 3639 /* DEC_19B_BURST_GAP_COUNT:8:10 */ 3640 PHYMOD_SYMBOL_FIELD_ENCODE(588, 10, 8), 3641 /* DEC_PM_MODE:11:15 */ 3642 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(591, 15, 11) 3643 }; 3644 static uint32_t BCMI_TSCE_XGXS_RX_X4_T12_FEC_BURST_ERR_STSHr_fields[] = 3645 { 3646 /* BURST_ERR_STATUSH:0:15 */ 3647 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(350, 15, 0) 3648 }; 3649 static uint32_t BCMI_TSCE_XGXS_RX_X4_T12_FEC_BURST_ERR_STSLr_fields[] = 3650 { 3651 /* BURST_ERR_STATUSL:0:15 */ 3652 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(351, 15, 0) 3653 }; 3654 static uint32_t BCMI_TSCE_XGXS_RX_X4_T12_FEC_CORRBLKSHr_fields[] = 3655 { 3656 /* CORCOUNTH:0:15 */ 3657 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(558, 15, 0) 3658 }; 3659 static uint32_t BCMI_TSCE_XGXS_RX_X4_T12_FEC_CORRBLKSLr_fields[] = 3660 { 3661 /* CORCOUNTL:0:15 */ 3662 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(559, 15, 0) 3663 }; 3664 static uint32_t BCMI_TSCE_XGXS_RX_X4_T12_FEC_DBG_ERRAHr_fields[] = 3665 { 3666 /* DBG_ERRH:0:15 */ 3667 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(575, 15, 0) 3668 }; 3669 static uint32_t BCMI_TSCE_XGXS_RX_X4_T12_FEC_DBG_ERRLr_fields[] = 3670 { 3671 /* DBG_ERRL:0:15 */ 3672 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(576, 15, 0) 3673 }; 3674 static uint32_t BCMI_TSCE_XGXS_RX_X4_T12_FEC_UNCORRBLKSHr_fields[] = 3675 { 3676 /* UNCORCOUNTH:0:15 */ 3677 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1430, 15, 0) 3678 }; 3679 static uint32_t BCMI_TSCE_XGXS_RX_X4_T12_FEC_UNCORRBLKSLr_fields[] = 3680 { 3681 /* UNCORCOUNTL:0:15 */ 3682 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1431, 15, 0) 3683 }; 3684 static uint32_t BCMI_TSCE_XGXS_RX_X4_T12_MLD_VL_INFO0r_fields[] = 3685 { 3686 /* VL_ON_LL_0:0:4 */ 3687 PHYMOD_SYMBOL_FIELD_ENCODE(1451, 4, 0), 3688 /* VL_ON_LL_1:5:9 */ 3689 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1452, 9, 5) 3690 }; 3691 static uint32_t BCMI_TSCE_XGXS_SC_X1_PIPE_RST_CNTr_fields[] = 3692 { 3693 /* PIPELINE_RESET_COUNT:0:15 */ 3694 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1017, 15, 0) 3695 }; 3696 static uint32_t BCMI_TSCE_XGXS_SC_X1_PLL_LOCK_TMRr_fields[] = 3697 { 3698 /* PLL_LOCK_TIMER_PERIOD:0:15 */ 3699 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1037, 15, 0) 3700 }; 3701 static uint32_t BCMI_TSCE_XGXS_SC_X1_PMD_LOCK_TMRr_fields[] = 3702 { 3703 /* PMD_LOCK_TIMER_PERIOD:0:15 */ 3704 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1054, 15, 0) 3705 }; 3706 static uint32_t BCMI_TSCE_XGXS_SC_X1_SPD_OVRR0_0r_fields[] = 3707 { 3708 /* ENCODEMODE:0:2 */ 3709 PHYMOD_SYMBOL_FIELD_ENCODE(712, 2, 0), 3710 /* FEC_ENABLE:8:8 */ 3711 PHYMOD_SYMBOL_FIELD_ENCODE(736, 8, 8), 3712 /* CL72_ENABLE:9:9 */ 3713 PHYMOD_SYMBOL_FIELD_ENCODE(473, 9, 9), 3714 /* SCR_MODE:10:11 */ 3715 PHYMOD_SYMBOL_FIELD_ENCODE(1203, 11, 10), 3716 /* OS_MODE:12:15 */ 3717 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(960, 15, 12) 3718 }; 3719 static uint32_t BCMI_TSCE_XGXS_SC_X1_SPD_OVRR0_1r_fields[] = 3720 { 3721 /* BRCM64B66_DESCRAMBLER_ENABLE:1:1 */ 3722 PHYMOD_SYMBOL_FIELD_ENCODE(346, 1, 1), 3723 /* CL36BYTEDELETEMODE:3:4 */ 3724 PHYMOD_SYMBOL_FIELD_ENCODE(395, 4, 3), 3725 /* DESC2_MODE:5:7 */ 3726 PHYMOD_SYMBOL_FIELD_ENCODE(592, 7, 5), 3727 /* DESKEWMODE:8:10 */ 3728 PHYMOD_SYMBOL_FIELD_ENCODE(596, 10, 8), 3729 /* DECODERMODE:11:13 */ 3730 PHYMOD_SYMBOL_FIELD_ENCODE(584, 13, 11), 3731 /* DESCRAMBLERMODE:14:15 */ 3732 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(594, 15, 14) 3733 }; 3734 static uint32_t BCMI_TSCE_XGXS_SC_X1_SPD_OVRR0_2r_fields[] = 3735 { 3736 /* CL36_EN:0:0 */ 3737 PHYMOD_SYMBOL_FIELD_ENCODE(398, 0, 0), 3738 /* REORDER_EN:1:1 */ 3739 PHYMOD_SYMBOL_FIELD_ENCODE(1112, 1, 1), 3740 /* BLOCK_SYNC_MODE:4:6 */ 3741 PHYMOD_SYMBOL_FIELD_ENCODE(343, 6, 4), 3742 /* CHK_END_EN:10:10 */ 3743 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(393, 10, 10) 3744 }; 3745 static uint32_t BCMI_TSCE_XGXS_SC_X1_SPD_OVRR0_3r_fields[] = 3746 { 3747 /* CLOCKCNT0:0:13 */ 3748 PHYMOD_SYMBOL_FIELD_ENCODE(545, 13, 0), 3749 /* SGMII_SPD_SWITCH:15:15 */ 3750 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1234, 15, 15) 3751 }; 3752 static uint32_t BCMI_TSCE_XGXS_SC_X1_SPD_OVRR0_4r_fields[] = 3753 { 3754 /* CLOCKCNT1:0:7 */ 3755 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(547, 7, 0) 3756 }; 3757 static uint32_t BCMI_TSCE_XGXS_SC_X1_SPD_OVRR0_5r_fields[] = 3758 { 3759 /* LOOPCNT1:0:5 */ 3760 PHYMOD_SYMBOL_FIELD_ENCODE(840, 5, 0), 3761 /* LOOPCNT0:6:13 */ 3762 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(838, 13, 6) 3763 }; 3764 static uint32_t BCMI_TSCE_XGXS_SC_X1_SPD_OVRR0_6r_fields[] = 3765 { 3766 /* MAC_CREDITGENCNT:0:12 */ 3767 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(869, 12, 0) 3768 }; 3769 static uint32_t BCMI_TSCE_XGXS_SC_X1_SPD_OVRR0_7r_fields[] = 3770 { 3771 /* PCS_CLOCKCNT0:0:13 */ 3772 PHYMOD_SYMBOL_FIELD_ENCODE(993, 13, 0), 3773 /* PCS_CREDITENABLE:14:14 */ 3774 PHYMOD_SYMBOL_FIELD_ENCODE(995, 14, 14), 3775 /* REPLICATION_CNT:15:15 */ 3776 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1114, 15, 15) 3777 }; 3778 static uint32_t BCMI_TSCE_XGXS_SC_X1_SPD_OVRR0_8r_fields[] = 3779 { 3780 /* PCS_CREDITGENCNT:0:12 */ 3781 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(997, 12, 0) 3782 }; 3783 static uint32_t BCMI_TSCE_XGXS_SC_X1_SPD_OVRR0_SPDr_fields[] = 3784 { 3785 /* NUM_LANES:0:2 */ 3786 PHYMOD_SYMBOL_FIELD_ENCODE(949, 2, 0), 3787 /* SPEED:8:15 */ 3788 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1261, 15, 8) 3789 }; 3790 static uint32_t BCMI_TSCE_XGXS_SC_X1_SPD_OVRR1_0r_fields[] = 3791 { 3792 /* ENCODEMODE:0:2 */ 3793 PHYMOD_SYMBOL_FIELD_ENCODE(712, 2, 0), 3794 /* FEC_ENABLE:8:8 */ 3795 PHYMOD_SYMBOL_FIELD_ENCODE(736, 8, 8), 3796 /* CL72_ENABLE:9:9 */ 3797 PHYMOD_SYMBOL_FIELD_ENCODE(473, 9, 9), 3798 /* SCR_MODE:10:11 */ 3799 PHYMOD_SYMBOL_FIELD_ENCODE(1203, 11, 10), 3800 /* OS_MODE:12:15 */ 3801 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(960, 15, 12) 3802 }; 3803 static uint32_t BCMI_TSCE_XGXS_SC_X1_SPD_OVRR1_1r_fields[] = 3804 { 3805 /* BRCM64B66_DESCRAMBLER_ENABLE:1:1 */ 3806 PHYMOD_SYMBOL_FIELD_ENCODE(346, 1, 1), 3807 /* CL36BYTEDELETEMODE:3:4 */ 3808 PHYMOD_SYMBOL_FIELD_ENCODE(395, 4, 3), 3809 /* DESC2_MODE:5:7 */ 3810 PHYMOD_SYMBOL_FIELD_ENCODE(592, 7, 5), 3811 /* DESKEWMODE:8:10 */ 3812 PHYMOD_SYMBOL_FIELD_ENCODE(596, 10, 8), 3813 /* DECODERMODE:11:13 */ 3814 PHYMOD_SYMBOL_FIELD_ENCODE(584, 13, 11), 3815 /* DESCRAMBLERMODE:14:15 */ 3816 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(594, 15, 14) 3817 }; 3818 static uint32_t BCMI_TSCE_XGXS_SC_X1_SPD_OVRR1_2r_fields[] = 3819 { 3820 /* CL36_EN:0:0 */ 3821 PHYMOD_SYMBOL_FIELD_ENCODE(398, 0, 0), 3822 /* REORDER_EN:1:1 */ 3823 PHYMOD_SYMBOL_FIELD_ENCODE(1112, 1, 1), 3824 /* BLOCK_SYNC_MODE:4:6 */ 3825 PHYMOD_SYMBOL_FIELD_ENCODE(343, 6, 4), 3826 /* CHK_END_EN:10:10 */ 3827 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(393, 10, 10) 3828 }; 3829 static uint32_t BCMI_TSCE_XGXS_SC_X1_SPD_OVRR1_3r_fields[] = 3830 { 3831 /* CLOCKCNT0:0:13 */ 3832 PHYMOD_SYMBOL_FIELD_ENCODE(545, 13, 0), 3833 /* SGMII_SPD_SWITCH:15:15 */ 3834 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1234, 15, 15) 3835 }; 3836 static uint32_t BCMI_TSCE_XGXS_SC_X1_SPD_OVRR1_4r_fields[] = 3837 { 3838 /* CLOCKCNT1:0:7 */ 3839 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(547, 7, 0) 3840 }; 3841 static uint32_t BCMI_TSCE_XGXS_SC_X1_SPD_OVRR1_5r_fields[] = 3842 { 3843 /* LOOPCNT1:0:5 */ 3844 PHYMOD_SYMBOL_FIELD_ENCODE(840, 5, 0), 3845 /* LOOPCNT0:6:13 */ 3846 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(838, 13, 6) 3847 }; 3848 static uint32_t BCMI_TSCE_XGXS_SC_X1_SPD_OVRR1_6r_fields[] = 3849 { 3850 /* MAC_CREDITGENCNT:0:12 */ 3851 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(869, 12, 0) 3852 }; 3853 static uint32_t BCMI_TSCE_XGXS_SC_X1_SPD_OVRR1_7r_fields[] = 3854 { 3855 /* PCS_CLOCKCNT0:0:13 */ 3856 PHYMOD_SYMBOL_FIELD_ENCODE(993, 13, 0), 3857 /* PCS_CREDITENABLE:14:14 */ 3858 PHYMOD_SYMBOL_FIELD_ENCODE(995, 14, 14), 3859 /* REPLICATION_CNT:15:15 */ 3860 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1114, 15, 15) 3861 }; 3862 static uint32_t BCMI_TSCE_XGXS_SC_X1_SPD_OVRR1_8r_fields[] = 3863 { 3864 /* PCS_CREDITGENCNT:0:12 */ 3865 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(997, 12, 0) 3866 }; 3867 static uint32_t BCMI_TSCE_XGXS_SC_X1_SPD_OVRR1_SPDr_fields[] = 3868 { 3869 /* NUM_LANES:0:2 */ 3870 PHYMOD_SYMBOL_FIELD_ENCODE(949, 2, 0), 3871 /* SPEED:8:15 */ 3872 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1261, 15, 8) 3873 }; 3874 static uint32_t BCMI_TSCE_XGXS_SC_X1_SPD_OVRR2_0r_fields[] = 3875 { 3876 /* ENCODEMODE:0:2 */ 3877 PHYMOD_SYMBOL_FIELD_ENCODE(712, 2, 0), 3878 /* FEC_ENABLE:8:8 */ 3879 PHYMOD_SYMBOL_FIELD_ENCODE(736, 8, 8), 3880 /* CL72_ENABLE:9:9 */ 3881 PHYMOD_SYMBOL_FIELD_ENCODE(473, 9, 9), 3882 /* SCR_MODE:10:11 */ 3883 PHYMOD_SYMBOL_FIELD_ENCODE(1203, 11, 10), 3884 /* OS_MODE:12:15 */ 3885 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(960, 15, 12) 3886 }; 3887 static uint32_t BCMI_TSCE_XGXS_SC_X1_SPD_OVRR2_1r_fields[] = 3888 { 3889 /* BRCM64B66_DESCRAMBLER_ENABLE:1:1 */ 3890 PHYMOD_SYMBOL_FIELD_ENCODE(346, 1, 1), 3891 /* CL36BYTEDELETEMODE:3:4 */ 3892 PHYMOD_SYMBOL_FIELD_ENCODE(395, 4, 3), 3893 /* DESC2_MODE:5:7 */ 3894 PHYMOD_SYMBOL_FIELD_ENCODE(592, 7, 5), 3895 /* DESKEWMODE:8:10 */ 3896 PHYMOD_SYMBOL_FIELD_ENCODE(596, 10, 8), 3897 /* DECODERMODE:11:13 */ 3898 PHYMOD_SYMBOL_FIELD_ENCODE(584, 13, 11), 3899 /* DESCRAMBLERMODE:14:15 */ 3900 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(594, 15, 14) 3901 }; 3902 static uint32_t BCMI_TSCE_XGXS_SC_X1_SPD_OVRR2_2r_fields[] = 3903 { 3904 /* CL36_EN:0:0 */ 3905 PHYMOD_SYMBOL_FIELD_ENCODE(398, 0, 0), 3906 /* REORDER_EN:1:1 */ 3907 PHYMOD_SYMBOL_FIELD_ENCODE(1112, 1, 1), 3908 /* BLOCK_SYNC_MODE:4:6 */ 3909 PHYMOD_SYMBOL_FIELD_ENCODE(343, 6, 4), 3910 /* CHK_END_EN:10:10 */ 3911 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(393, 10, 10) 3912 }; 3913 static uint32_t BCMI_TSCE_XGXS_SC_X1_SPD_OVRR2_3r_fields[] = 3914 { 3915 /* CLOCKCNT0:0:13 */ 3916 PHYMOD_SYMBOL_FIELD_ENCODE(545, 13, 0), 3917 /* SGMII_SPD_SWITCH:15:15 */ 3918 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1234, 15, 15) 3919 }; 3920 static uint32_t BCMI_TSCE_XGXS_SC_X1_SPD_OVRR2_4r_fields[] = 3921 { 3922 /* CLOCKCNT1:0:7 */ 3923 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(547, 7, 0) 3924 }; 3925 static uint32_t BCMI_TSCE_XGXS_SC_X1_SPD_OVRR2_5r_fields[] = 3926 { 3927 /* LOOPCNT1:0:5 */ 3928 PHYMOD_SYMBOL_FIELD_ENCODE(840, 5, 0), 3929 /* LOOPCNT0:6:13 */ 3930 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(838, 13, 6) 3931 }; 3932 static uint32_t BCMI_TSCE_XGXS_SC_X1_SPD_OVRR2_6r_fields[] = 3933 { 3934 /* MAC_CREDITGENCNT:0:12 */ 3935 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(869, 12, 0) 3936 }; 3937 static uint32_t BCMI_TSCE_XGXS_SC_X1_SPD_OVRR2_7r_fields[] = 3938 { 3939 /* PCS_CLOCKCNT0:0:13 */ 3940 PHYMOD_SYMBOL_FIELD_ENCODE(993, 13, 0), 3941 /* PCS_CREDITENABLE:14:14 */ 3942 PHYMOD_SYMBOL_FIELD_ENCODE(995, 14, 14), 3943 /* REPLICATION_CNT:15:15 */ 3944 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1114, 15, 15) 3945 }; 3946 static uint32_t BCMI_TSCE_XGXS_SC_X1_SPD_OVRR2_8r_fields[] = 3947 { 3948 /* PCS_CREDITGENCNT:0:12 */ 3949 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(997, 12, 0) 3950 }; 3951 static uint32_t BCMI_TSCE_XGXS_SC_X1_SPD_OVRR2_SPDr_fields[] = 3952 { 3953 /* NUM_LANES:0:2 */ 3954 PHYMOD_SYMBOL_FIELD_ENCODE(949, 2, 0), 3955 /* SPEED:8:15 */ 3956 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1261, 15, 8) 3957 }; 3958 static uint32_t BCMI_TSCE_XGXS_SC_X1_SPD_OVRR3_0r_fields[] = 3959 { 3960 /* ENCODEMODE:0:2 */ 3961 PHYMOD_SYMBOL_FIELD_ENCODE(712, 2, 0), 3962 /* FEC_ENABLE:8:8 */ 3963 PHYMOD_SYMBOL_FIELD_ENCODE(736, 8, 8), 3964 /* CL72_ENABLE:9:9 */ 3965 PHYMOD_SYMBOL_FIELD_ENCODE(473, 9, 9), 3966 /* SCR_MODE:10:11 */ 3967 PHYMOD_SYMBOL_FIELD_ENCODE(1203, 11, 10), 3968 /* OS_MODE:12:15 */ 3969 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(960, 15, 12) 3970 }; 3971 static uint32_t BCMI_TSCE_XGXS_SC_X1_SPD_OVRR3_1r_fields[] = 3972 { 3973 /* BRCM64B66_DESCRAMBLER_ENABLE:1:1 */ 3974 PHYMOD_SYMBOL_FIELD_ENCODE(346, 1, 1), 3975 /* CL36BYTEDELETEMODE:3:4 */ 3976 PHYMOD_SYMBOL_FIELD_ENCODE(395, 4, 3), 3977 /* DESC2_MODE:5:7 */ 3978 PHYMOD_SYMBOL_FIELD_ENCODE(592, 7, 5), 3979 /* DESKEWMODE:8:10 */ 3980 PHYMOD_SYMBOL_FIELD_ENCODE(596, 10, 8), 3981 /* DECODERMODE:11:13 */ 3982 PHYMOD_SYMBOL_FIELD_ENCODE(584, 13, 11), 3983 /* DESCRAMBLERMODE:14:15 */ 3984 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(594, 15, 14) 3985 }; 3986 static uint32_t BCMI_TSCE_XGXS_SC_X1_SPD_OVRR3_2r_fields[] = 3987 { 3988 /* CL36_EN:0:0 */ 3989 PHYMOD_SYMBOL_FIELD_ENCODE(398, 0, 0), 3990 /* REORDER_EN:1:1 */ 3991 PHYMOD_SYMBOL_FIELD_ENCODE(1112, 1, 1), 3992 /* BLOCK_SYNC_MODE:4:6 */ 3993 PHYMOD_SYMBOL_FIELD_ENCODE(343, 6, 4), 3994 /* CHK_END_EN:10:10 */ 3995 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(393, 10, 10) 3996 }; 3997 static uint32_t BCMI_TSCE_XGXS_SC_X1_SPD_OVRR3_3r_fields[] = 3998 { 3999 /* CLOCKCNT0:0:13 */ 4000 PHYMOD_SYMBOL_FIELD_ENCODE(545, 13, 0), 4001 /* SGMII_SPD_SWITCH:15:15 */ 4002 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1234, 15, 15) 4003 }; 4004 static uint32_t BCMI_TSCE_XGXS_SC_X1_SPD_OVRR3_4r_fields[] = 4005 { 4006 /* CLOCKCNT1:0:7 */ 4007 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(547, 7, 0) 4008 }; 4009 static uint32_t BCMI_TSCE_XGXS_SC_X1_SPD_OVRR3_5r_fields[] = 4010 { 4011 /* LOOPCNT1:0:5 */ 4012 PHYMOD_SYMBOL_FIELD_ENCODE(840, 5, 0), 4013 /* LOOPCNT0:6:13 */ 4014 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(838, 13, 6) 4015 }; 4016 static uint32_t BCMI_TSCE_XGXS_SC_X1_SPD_OVRR3_6r_fields[] = 4017 { 4018 /* MAC_CREDITGENCNT:0:12 */ 4019 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(869, 12, 0) 4020 }; 4021 static uint32_t BCMI_TSCE_XGXS_SC_X1_SPD_OVRR3_7r_fields[] = 4022 { 4023 /* PCS_CLOCKCNT0:0:13 */ 4024 PHYMOD_SYMBOL_FIELD_ENCODE(993, 13, 0), 4025 /* PCS_CREDITENABLE:14:14 */ 4026 PHYMOD_SYMBOL_FIELD_ENCODE(995, 14, 14), 4027 /* REPLICATION_CNT:15:15 */ 4028 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1114, 15, 15) 4029 }; 4030 static uint32_t BCMI_TSCE_XGXS_SC_X1_SPD_OVRR3_8r_fields[] = 4031 { 4032 /* PCS_CREDITGENCNT:0:12 */ 4033 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(997, 12, 0) 4034 }; 4035 static uint32_t BCMI_TSCE_XGXS_SC_X1_SPD_OVRR3_SPDr_fields[] = 4036 { 4037 /* NUM_LANES:0:2 */ 4038 PHYMOD_SYMBOL_FIELD_ENCODE(949, 2, 0), 4039 /* SPEED:8:15 */ 4040 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1261, 15, 8) 4041 }; 4042 static uint32_t BCMI_TSCE_XGXS_SC_X1_STSr_fields[] = 4043 { 4044 /* RESOLVED_PORT_MODE:0:2 */ 4045 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1121, 2, 0) 4046 }; 4047 static uint32_t BCMI_TSCE_XGXS_SC_X1_TX_RST_CNTr_fields[] = 4048 { 4049 /* TX_RESET_COUNT:0:15 */ 4050 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1408, 15, 0) 4051 }; 4052 static uint32_t BCMI_TSCE_XGXS_SC_X4_BYPASSr_fields[] = 4053 { 4054 /* SC_BYPASS:0:0 */ 4055 PHYMOD_SYMBOL_FIELD_ENCODE(1216, 0, 0), 4056 /* SC_IGNORE_TX_DATA_VLD:1:1 */ 4057 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1218, 1, 1) 4058 }; 4059 static uint32_t BCMI_TSCE_XGXS_SC_X4_CTLr_fields[] = 4060 { 4061 /* SW_SPEED:0:7 */ 4062 PHYMOD_SYMBOL_FIELD_ENCODE(1268, 7, 0), 4063 /* SW_SPEED_CHANGE:8:8 */ 4064 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1269, 8, 8) 4065 }; 4066 static uint32_t BCMI_TSCE_XGXS_SC_X4_DBGr_fields[] = 4067 { 4068 /* SC_FSM_STATUS:0:15 */ 4069 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1217, 15, 0) 4070 }; 4071 static uint32_t BCMI_TSCE_XGXS_SC_X4_ERRr_fields[] = 4072 { 4073 /* PLL_LOCK_TIMED_OUT:0:0 */ 4074 PHYMOD_SYMBOL_FIELD_ENCODE(1036, 0, 0), 4075 /* PMD_LOCK_TIMED_OUT:1:1 */ 4076 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1053, 1, 1) 4077 }; 4078 static uint32_t BCMI_TSCE_XGXS_SC_X4_FLD_OVRR_EN0_TYPEr_fields[] = 4079 { 4080 /* BLOCK_SYNC_MODE_OEN:0:0 */ 4081 PHYMOD_SYMBOL_FIELD_ENCODE(344, 0, 0), 4082 /* CHK_END_EN_OEN:2:2 */ 4083 PHYMOD_SYMBOL_FIELD_ENCODE(394, 2, 2), 4084 /* BRCM64B66_DESCRAMBLER_ENABLE_OEN:3:3 */ 4085 PHYMOD_SYMBOL_FIELD_ENCODE(347, 3, 3), 4086 /* CL36BYTEDELETEMODE_OEN:4:4 */ 4087 PHYMOD_SYMBOL_FIELD_ENCODE(396, 4, 4), 4088 /* DESC2_MODE_OEN:5:5 */ 4089 PHYMOD_SYMBOL_FIELD_ENCODE(593, 5, 5), 4090 /* DESKEWMODE_OEN:6:6 */ 4091 PHYMOD_SYMBOL_FIELD_ENCODE(597, 6, 6), 4092 /* DECODERMODE_OEN:7:7 */ 4093 PHYMOD_SYMBOL_FIELD_ENCODE(585, 7, 7), 4094 /* DESCRAMBLERMODE_OEN:8:8 */ 4095 PHYMOD_SYMBOL_FIELD_ENCODE(595, 8, 8), 4096 /* ENCODEMODE_OEN:9:9 */ 4097 PHYMOD_SYMBOL_FIELD_ENCODE(713, 9, 9), 4098 /* FEC_ENABLE_OEN:10:10 */ 4099 PHYMOD_SYMBOL_FIELD_ENCODE(737, 10, 10), 4100 /* SCR_MODE_OEN:11:11 */ 4101 PHYMOD_SYMBOL_FIELD_ENCODE(1204, 11, 11), 4102 /* OS_MODE_OEN:12:12 */ 4103 PHYMOD_SYMBOL_FIELD_ENCODE(961, 12, 12), 4104 /* NUM_LANES_OEN:14:14 */ 4105 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(950, 14, 14) 4106 }; 4107 static uint32_t BCMI_TSCE_XGXS_SC_X4_FLD_OVRR_EN1_TYPEr_fields[] = 4108 { 4109 /* PCS_CREDITGENCNT_OEN:0:0 */ 4110 PHYMOD_SYMBOL_FIELD_ENCODE(998, 0, 0), 4111 /* PCS_CLOCKCNT0_OEN:1:1 */ 4112 PHYMOD_SYMBOL_FIELD_ENCODE(994, 1, 1), 4113 /* PCS_CREDITENABLE_OEN:2:2 */ 4114 PHYMOD_SYMBOL_FIELD_ENCODE(996, 2, 2), 4115 /* REPLICATION_CNT_OEN:3:3 */ 4116 PHYMOD_SYMBOL_FIELD_ENCODE(1115, 3, 3), 4117 /* MAC_CREDITGENCNT_OEN:4:4 */ 4118 PHYMOD_SYMBOL_FIELD_ENCODE(870, 4, 4), 4119 /* LOOPCNT1_OEN:5:5 */ 4120 PHYMOD_SYMBOL_FIELD_ENCODE(841, 5, 5), 4121 /* LOOPCNT0_OEN:6:6 */ 4122 PHYMOD_SYMBOL_FIELD_ENCODE(839, 6, 6), 4123 /* CLOCKCNT1_OEN:7:7 */ 4124 PHYMOD_SYMBOL_FIELD_ENCODE(548, 7, 7), 4125 /* CLOCKCNT0_OEN:8:8 */ 4126 PHYMOD_SYMBOL_FIELD_ENCODE(546, 8, 8), 4127 /* CREDITENABLE_OEN:9:9 */ 4128 PHYMOD_SYMBOL_FIELD_ENCODE(571, 9, 9), 4129 /* SGMII_SPD_SWITCH_OEN:10:10 */ 4130 PHYMOD_SYMBOL_FIELD_ENCODE(1235, 10, 10), 4131 /* CL36_EN_OEN:11:11 */ 4132 PHYMOD_SYMBOL_FIELD_ENCODE(399, 11, 11), 4133 /* REORDER_EN_OEN:12:12 */ 4134 PHYMOD_SYMBOL_FIELD_ENCODE(1113, 12, 12), 4135 /* CL72_EN_OEN:13:13 */ 4136 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(475, 13, 13) 4137 }; 4138 static uint32_t BCMI_TSCE_XGXS_SC_X4_LN_NUM_OVRRr_fields[] = 4139 { 4140 /* NUM_LANES_OVERRIDE_VALUE:0:2 */ 4141 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(951, 2, 0) 4142 }; 4143 static uint32_t BCMI_TSCE_XGXS_SC_X4_RSLVD0r_fields[] = 4144 { 4145 /* ENCODEMODE:0:2 */ 4146 PHYMOD_SYMBOL_FIELD_ENCODE(712, 2, 0), 4147 /* FEC_ENABLE:8:8 */ 4148 PHYMOD_SYMBOL_FIELD_ENCODE(736, 8, 8), 4149 /* CL72_ENABLE:9:9 */ 4150 PHYMOD_SYMBOL_FIELD_ENCODE(473, 9, 9), 4151 /* SCR_MODE:10:11 */ 4152 PHYMOD_SYMBOL_FIELD_ENCODE(1203, 11, 10), 4153 /* OS_MODE:12:15 */ 4154 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(960, 15, 12) 4155 }; 4156 static uint32_t BCMI_TSCE_XGXS_SC_X4_RSLVD1r_fields[] = 4157 { 4158 /* BRCM64B66_DESCRAMBLER_ENABLE:1:1 */ 4159 PHYMOD_SYMBOL_FIELD_ENCODE(346, 1, 1), 4160 /* CL36BYTEDELETEMODE:3:4 */ 4161 PHYMOD_SYMBOL_FIELD_ENCODE(395, 4, 3), 4162 /* DESC2_MODE:5:7 */ 4163 PHYMOD_SYMBOL_FIELD_ENCODE(592, 7, 5), 4164 /* DESKEWMODE:8:10 */ 4165 PHYMOD_SYMBOL_FIELD_ENCODE(596, 10, 8), 4166 /* DECODERMODE:11:13 */ 4167 PHYMOD_SYMBOL_FIELD_ENCODE(584, 13, 11), 4168 /* DESCRAMBLERMODE:14:15 */ 4169 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(594, 15, 14) 4170 }; 4171 static uint32_t BCMI_TSCE_XGXS_SC_X4_RSLVD2r_fields[] = 4172 { 4173 /* CL36_EN:0:0 */ 4174 PHYMOD_SYMBOL_FIELD_ENCODE(398, 0, 0), 4175 /* REORDER_EN:1:1 */ 4176 PHYMOD_SYMBOL_FIELD_ENCODE(1112, 1, 1), 4177 /* BLOCK_SYNC_MODE:4:6 */ 4178 PHYMOD_SYMBOL_FIELD_ENCODE(343, 6, 4), 4179 /* CHK_END_EN:10:10 */ 4180 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(393, 10, 10) 4181 }; 4182 static uint32_t BCMI_TSCE_XGXS_SC_X4_RSLVD3r_fields[] = 4183 { 4184 /* CLOCKCNT0:0:13 */ 4185 PHYMOD_SYMBOL_FIELD_ENCODE(545, 13, 0), 4186 /* SGMII_SPD_SWITCH:15:15 */ 4187 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1234, 15, 15) 4188 }; 4189 static uint32_t BCMI_TSCE_XGXS_SC_X4_RSLVD4r_fields[] = 4190 { 4191 /* CLOCKCNT1:0:7 */ 4192 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(547, 7, 0) 4193 }; 4194 static uint32_t BCMI_TSCE_XGXS_SC_X4_RSLVD5r_fields[] = 4195 { 4196 /* LOOPCNT1:0:5 */ 4197 PHYMOD_SYMBOL_FIELD_ENCODE(840, 5, 0), 4198 /* LOOPCNT0:6:13 */ 4199 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(838, 13, 6) 4200 }; 4201 static uint32_t BCMI_TSCE_XGXS_SC_X4_RSLVD6r_fields[] = 4202 { 4203 /* MAC_CREDITGENCNT:0:12 */ 4204 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(869, 12, 0) 4205 }; 4206 static uint32_t BCMI_TSCE_XGXS_SC_X4_RSLVD7r_fields[] = 4207 { 4208 /* PCS_CLOCKCNT0:0:13 */ 4209 PHYMOD_SYMBOL_FIELD_ENCODE(993, 13, 0), 4210 /* PCS_CREDITENABLE:14:14 */ 4211 PHYMOD_SYMBOL_FIELD_ENCODE(995, 14, 14), 4212 /* REPLICATION_CNT:15:15 */ 4213 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1114, 15, 15) 4214 }; 4215 static uint32_t BCMI_TSCE_XGXS_SC_X4_RSLVD8r_fields[] = 4216 { 4217 /* PCS_CREDITGENCNT:0:12 */ 4218 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(997, 12, 0) 4219 }; 4220 static uint32_t BCMI_TSCE_XGXS_SC_X4_RSLVD_SPDr_fields[] = 4221 { 4222 /* NUM_LANES:0:2 */ 4223 PHYMOD_SYMBOL_FIELD_ENCODE(949, 2, 0), 4224 /* SPEED:8:15 */ 4225 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1261, 15, 8) 4226 }; 4227 static uint32_t BCMI_TSCE_XGXS_SC_X4_STSr_fields[] = 4228 { 4229 /* SW_SPEED_CHANGE_DONE:0:0 */ 4230 PHYMOD_SYMBOL_FIELD_ENCODE(1270, 0, 0), 4231 /* SW_SPEED_CONFIG_VLD:1:1 */ 4232 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1271, 1, 1) 4233 }; 4234 static uint32_t BCMI_TSCE_XGXS_SIGDET_CTL0r_fields[] = 4235 { 4236 /* SIGNAL_DETECT_FILTER_COUNT:0:4 */ 4237 PHYMOD_SYMBOL_FIELD_ENCODE(1244, 4, 0), 4238 /* LOS_FILTER_COUNT:8:12 */ 4239 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(843, 12, 8) 4240 }; 4241 static uint32_t BCMI_TSCE_XGXS_SIGDET_CTL1r_fields[] = 4242 { 4243 /* AFE_SIGNAL_DETECT_DIS:0:0 */ 4244 PHYMOD_SYMBOL_FIELD_ENCODE(8, 0, 0), 4245 /* EXT_LOS_EN:1:1 */ 4246 PHYMOD_SYMBOL_FIELD_ENCODE(731, 1, 1), 4247 /* EXT_LOS_INV:2:2 */ 4248 PHYMOD_SYMBOL_FIELD_ENCODE(732, 2, 2), 4249 /* IGNORE_LP_MODE:3:3 */ 4250 PHYMOD_SYMBOL_FIELD_ENCODE(769, 3, 3), 4251 /* SIGNAL_DETECT_FILTER_1US:4:4 */ 4252 PHYMOD_SYMBOL_FIELD_ENCODE(1243, 4, 4), 4253 /* ENERGY_DETECT_FRC:5:5 */ 4254 PHYMOD_SYMBOL_FIELD_ENCODE(716, 5, 5), 4255 /* ENERGY_DETECT_FRC_VAL:6:6 */ 4256 PHYMOD_SYMBOL_FIELD_ENCODE(717, 6, 6), 4257 /* SIGNAL_DETECT_FRC:7:7 */ 4258 PHYMOD_SYMBOL_FIELD_ENCODE(1245, 7, 7), 4259 /* SIGNAL_DETECT_FRC_VAL:8:8 */ 4260 PHYMOD_SYMBOL_FIELD_ENCODE(1246, 8, 8), 4261 /* ENERGY_DETECT_MASK_COUNT:11:15 */ 4262 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(718, 15, 11) 4263 }; 4264 static uint32_t BCMI_TSCE_XGXS_SIGDET_CTL2r_fields[] = 4265 { 4266 /* LOS_THRESH:0:2 */ 4267 PHYMOD_SYMBOL_FIELD_ENCODE(844, 2, 0), 4268 /* SIGNAL_DETECT_THRESH:4:6 */ 4269 PHYMOD_SYMBOL_FIELD_ENCODE(1253, 6, 4), 4270 /* HOLD_LOS_COUNT:8:10 */ 4271 PHYMOD_SYMBOL_FIELD_ENCODE(761, 10, 8), 4272 /* HOLD_SD_COUNT:11:13 */ 4273 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(762, 13, 11) 4274 }; 4275 static uint32_t BCMI_TSCE_XGXS_SIGDET_STS0r_fields[] = 4276 { 4277 /* SIGNAL_DETECT:0:0 */ 4278 PHYMOD_SYMBOL_FIELD_ENCODE(1241, 0, 0), 4279 /* SIGNAL_DETECT_CHANGE:1:1 */ 4280 PHYMOD_SYMBOL_FIELD_ENCODE(1242, 1, 1), 4281 /* ENERGY_DETECT:2:2 */ 4282 PHYMOD_SYMBOL_FIELD_ENCODE(714, 2, 2), 4283 /* ENERGY_DETECT_CHANGE:3:3 */ 4284 PHYMOD_SYMBOL_FIELD_ENCODE(715, 3, 3), 4285 /* SIGNAL_DETECT_RAW:4:4 */ 4286 PHYMOD_SYMBOL_FIELD_ENCODE(1250, 4, 4), 4287 /* SIGNAL_DETECT_RAW_CHANGE:5:5 */ 4288 PHYMOD_SYMBOL_FIELD_ENCODE(1251, 5, 5), 4289 /* AFE_SIGDET_THRESH:8:10 */ 4290 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(7, 10, 8) 4291 }; 4292 static uint32_t BCMI_TSCE_XGXS_TLB_RX_DIG_LPBK_CFGr_fields[] = 4293 { 4294 /* DIG_LPBK_EN:0:0 */ 4295 PHYMOD_SYMBOL_FIELD_ENCODE(680, 0, 0), 4296 /* DIG_LPBK_PD_MODE:1:1 */ 4297 PHYMOD_SYMBOL_FIELD_ENCODE(684, 1, 1), 4298 /* DIG_LPBK_PD_FLT_BYPASS:2:2 */ 4299 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(682, 2, 2) 4300 }; 4301 static uint32_t BCMI_TSCE_XGXS_TLB_RX_DIG_LPBK_PD_STSr_fields[] = 4302 { 4303 /* DIG_LPBK_PD_LATE_IND:0:0 */ 4304 PHYMOD_SYMBOL_FIELD_ENCODE(683, 0, 0), 4305 /* DIG_LPBK_PD_EARLY_IND:1:1 */ 4306 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(681, 1, 1) 4307 }; 4308 static uint32_t BCMI_TSCE_XGXS_TLB_RX_PMD_RX_LOCK_STSr_fields[] = 4309 { 4310 /* PMD_RX_LOCK:0:0 */ 4311 PHYMOD_SYMBOL_FIELD_ENCODE(1058, 0, 0), 4312 /* PMD_RX_LOCK_CHANGE:1:1 */ 4313 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1059, 1, 1) 4314 }; 4315 static uint32_t BCMI_TSCE_XGXS_TLB_RX_PRBS_CHK_CFGr_fields[] = 4316 { 4317 /* PRBS_CHK_EN:0:0 */ 4318 PHYMOD_SYMBOL_FIELD_ENCODE(1069, 0, 0), 4319 /* PRBS_CHK_MODE_SEL:1:3 */ 4320 PHYMOD_SYMBOL_FIELD_ENCODE(1081, 3, 1), 4321 /* PRBS_CHK_INV:4:4 */ 4322 PHYMOD_SYMBOL_FIELD_ENCODE(1076, 4, 4), 4323 /* PRBS_CHK_MODE:5:6 */ 4324 PHYMOD_SYMBOL_FIELD_ENCODE(1080, 6, 5), 4325 /* PRBS_CHK_EN_AUTO_MODE:7:7 */ 4326 PHYMOD_SYMBOL_FIELD_ENCODE(1070, 7, 7), 4327 /* PRBS_CHK_ERR_CNT_BURST_MODE:9:9 */ 4328 PHYMOD_SYMBOL_FIELD_ENCODE(1073, 9, 9), 4329 /* TRNSUM_ERROR_COUNT_EN:10:10 */ 4330 PHYMOD_SYMBOL_FIELD_ENCODE(1299, 10, 10), 4331 /* PRBS_CHK_CLK_EN_FRC_ON:11:11 */ 4332 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1068, 11, 11) 4333 }; 4334 static uint32_t BCMI_TSCE_XGXS_TLB_RX_PRBS_CHK_CNT_CFGr_fields[] = 4335 { 4336 /* PRBS_CHK_LOCK_CNT:0:4 */ 4337 PHYMOD_SYMBOL_FIELD_ENCODE(1078, 4, 0), 4338 /* PRBS_CHK_OOL_CNT:8:12 */ 4339 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1082, 12, 8) 4340 }; 4341 static uint32_t BCMI_TSCE_XGXS_TLB_RX_PRBS_CHK_EN_TMR_CTLr_fields[] = 4342 { 4343 /* PRBS_CHK_EN_TIMER_MODE:0:1 */ 4344 PHYMOD_SYMBOL_FIELD_ENCODE(1072, 1, 0), 4345 /* PRBS_CHK_EN_TIMEOUT:8:12 */ 4346 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1071, 12, 8) 4347 }; 4348 static uint32_t BCMI_TSCE_XGXS_TLB_RX_PRBS_CHK_ERR_CNT_LSB_STSr_fields[] = 4349 { 4350 /* PRBS_CHK_ERR_CNT_LSB:0:15 */ 4351 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1074, 15, 0) 4352 }; 4353 static uint32_t BCMI_TSCE_XGXS_TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr_fields[] = 4354 { 4355 /* PRBS_CHK_ERR_CNT_MSB:0:14 */ 4356 PHYMOD_SYMBOL_FIELD_ENCODE(1075, 14, 0), 4357 /* PRBS_CHK_LOCK_LOST_LH:15:15 */ 4358 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1079, 15, 15) 4359 }; 4360 static uint32_t BCMI_TSCE_XGXS_TLB_RX_PRBS_CHK_LOCK_STSr_fields[] = 4361 { 4362 /* PRBS_CHK_LOCK:0:0 */ 4363 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1077, 0, 0) 4364 }; 4365 static uint32_t BCMI_TSCE_XGXS_TLB_RX_TLB_RX_MISC_CFGr_fields[] = 4366 { 4367 /* RX_PMD_DP_INVERT:0:0 */ 4368 PHYMOD_SYMBOL_FIELD_ENCODE(1195, 0, 0), 4369 /* RX_AGGREGATOR_BYPASS_EN:1:1 */ 4370 PHYMOD_SYMBOL_FIELD_ENCODE(1171, 1, 1), 4371 /* DBG_MASK_DIG_LPBK_EN:2:2 */ 4372 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(579, 2, 2) 4373 }; 4374 static uint32_t BCMI_TSCE_XGXS_TLB_TX_PATGEN_CFGr_fields[] = 4375 { 4376 /* PATT_GEN_EN:0:0 */ 4377 PHYMOD_SYMBOL_FIELD_ENCODE(974, 0, 0), 4378 /* PATT_GEN_STOP_POS:8:11 */ 4379 PHYMOD_SYMBOL_FIELD_ENCODE(991, 11, 8), 4380 /* PATT_GEN_START_POS:12:15 */ 4381 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(990, 15, 12) 4382 }; 4383 static uint32_t BCMI_TSCE_XGXS_TLB_TX_PRBS_GEN_CFGr_fields[] = 4384 { 4385 /* PRBS_GEN_EN:0:0 */ 4386 PHYMOD_SYMBOL_FIELD_ENCODE(1083, 0, 0), 4387 /* PRBS_GEN_MODE_SEL:1:3 */ 4388 PHYMOD_SYMBOL_FIELD_ENCODE(1086, 3, 1), 4389 /* PRBS_GEN_INV:4:4 */ 4390 PHYMOD_SYMBOL_FIELD_ENCODE(1085, 4, 4), 4391 /* PRBS_GEN_ERR_INS:5:5 */ 4392 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1084, 5, 5) 4393 }; 4394 static uint32_t BCMI_TSCE_XGXS_TLB_TX_RMT_LPBK_CFGr_fields[] = 4395 { 4396 /* RMT_LPBK_EN:0:0 */ 4397 PHYMOD_SYMBOL_FIELD_ENCODE(1155, 0, 0), 4398 /* RMT_LPBK_PD_MODE:1:1 */ 4399 PHYMOD_SYMBOL_FIELD_ENCODE(1159, 1, 1), 4400 /* RMT_LPBK_PD_FRC_ON:2:2 */ 4401 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1157, 2, 2) 4402 }; 4403 static uint32_t BCMI_TSCE_XGXS_TLB_TX_RMT_LPBK_PD_STSr_fields[] = 4404 { 4405 /* RMT_LPBK_PD_LATE_IND:0:0 */ 4406 PHYMOD_SYMBOL_FIELD_ENCODE(1158, 0, 0), 4407 /* RMT_LPBK_PD_EARLY_IND:1:1 */ 4408 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1156, 1, 1) 4409 }; 4410 static uint32_t BCMI_TSCE_XGXS_TLB_TX_TLB_TX_MISC_CFGr_fields[] = 4411 { 4412 /* TX_PMD_DP_INVERT:0:0 */ 4413 PHYMOD_SYMBOL_FIELD_ENCODE(1405, 0, 0), 4414 /* TX_PCS_NATIVE_ANA_FRMT_EN:1:1 */ 4415 PHYMOD_SYMBOL_FIELD_ENCODE(1371, 1, 1), 4416 /* TX_MUX_SEL_ORDER:2:2 */ 4417 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1370, 2, 2) 4418 }; 4419 static uint32_t BCMI_TSCE_XGXS_TLB_TX_TX_PI_LOOP_TIMING_CFGr_fields[] = 4420 { 4421 /* TX_PI_LOOP_TIMING_SRC_SEL:0:0 */ 4422 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1391, 0, 0) 4423 }; 4424 static uint32_t BCMI_TSCE_XGXS_TXFIR_CTL1r_fields[] = 4425 { 4426 /* TXFIR_PRE_OVERRIDE:0:4 */ 4427 PHYMOD_SYMBOL_FIELD_ENCODE(1343, 4, 0), 4428 /* TXFIR_POST_OVERRIDE:5:10 */ 4429 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1339, 10, 5) 4430 }; 4431 static uint32_t BCMI_TSCE_XGXS_TXFIR_CTL2r_fields[] = 4432 { 4433 /* TXFIR_MAIN_OVERRIDE:0:6 */ 4434 PHYMOD_SYMBOL_FIELD_ENCODE(1328, 6, 0), 4435 /* TXFIR_POST2:7:11 */ 4436 PHYMOD_SYMBOL_FIELD_ENCODE(1330, 11, 7), 4437 /* TXFIR_OVERRIDE_EN:15:15 */ 4438 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1329, 15, 15) 4439 }; 4440 static uint32_t BCMI_TSCE_XGXS_TXFIR_CTL3r_fields[] = 4441 { 4442 /* TXFIR_PRE_OFFSET:0:3 */ 4443 PHYMOD_SYMBOL_FIELD_ENCODE(1342, 3, 0), 4444 /* TXFIR_MAIN_OFFSET:4:7 */ 4445 PHYMOD_SYMBOL_FIELD_ENCODE(1327, 7, 4), 4446 /* TXFIR_POST_OFFSET:8:11 */ 4447 PHYMOD_SYMBOL_FIELD_ENCODE(1338, 11, 8), 4448 /* TXFIR_POST2_OFFSET:12:15 */ 4449 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1332, 15, 12) 4450 }; 4451 static uint32_t BCMI_TSCE_XGXS_TXFIR_CTL4r_fields[] = 4452 { 4453 /* TXFIR_POST3:0:3 */ 4454 PHYMOD_SYMBOL_FIELD_ENCODE(1333, 3, 0), 4455 /* TXFIR_POST3_OFFSET:8:11 */ 4456 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1335, 11, 8) 4457 }; 4458 static uint32_t BCMI_TSCE_XGXS_TXFIR_MISC_CTL1r_fields[] = 4459 { 4460 /* SDK_TX_DISABLE:0:0 */ 4461 PHYMOD_SYMBOL_FIELD_ENCODE(1219, 0, 0), 4462 /* PMD_TX_DISABLE_PIN_DIS:1:1 */ 4463 PHYMOD_SYMBOL_FIELD_ENCODE(1062, 1, 1), 4464 /* TX_DISABLE_TIMER_CTRL:2:7 */ 4465 PHYMOD_SYMBOL_FIELD_ENCODE(1354, 7, 2), 4466 /* TX_EEE_QUIET_EN:8:8 */ 4467 PHYMOD_SYMBOL_FIELD_ENCODE(1357, 8, 8), 4468 /* TX_EEE_ALERT_EN:9:9 */ 4469 PHYMOD_SYMBOL_FIELD_ENCODE(1356, 9, 9), 4470 /* TX_DISABLE_OUTPUT_SEL:10:11 */ 4471 PHYMOD_SYMBOL_FIELD_ENCODE(1353, 11, 10), 4472 /* DP_RESET_TX_DISABLE_DIS:12:12 */ 4473 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(689, 12, 12) 4474 }; 4475 static uint32_t BCMI_TSCE_XGXS_TXFIR_STS1r_fields[] = 4476 { 4477 /* TXFIR_PRE_AFTER_OVR:0:4 */ 4478 PHYMOD_SYMBOL_FIELD_ENCODE(1341, 4, 0), 4479 /* TXFIR_POST_AFTER_OVR:5:10 */ 4480 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1337, 10, 5) 4481 }; 4482 static uint32_t BCMI_TSCE_XGXS_TXFIR_STS2r_fields[] = 4483 { 4484 /* TXFIR_MAIN_AFTER_OVR:0:6 */ 4485 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1326, 6, 0) 4486 }; 4487 static uint32_t BCMI_TSCE_XGXS_TXFIR_STS3r_fields[] = 4488 { 4489 /* TXFIR_PRE_ADJUSTED:0:4 */ 4490 PHYMOD_SYMBOL_FIELD_ENCODE(1340, 4, 0), 4491 /* TXFIR_POST_ADJUSTED:5:10 */ 4492 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1336, 10, 5) 4493 }; 4494 static uint32_t BCMI_TSCE_XGXS_TXFIR_STS4r_fields[] = 4495 { 4496 /* TXFIR_MAIN_ADJUSTED:0:6 */ 4497 PHYMOD_SYMBOL_FIELD_ENCODE(1325, 6, 0), 4498 /* TXFIR_POST2_ADJUSTED:7:11 */ 4499 PHYMOD_SYMBOL_FIELD_ENCODE(1331, 11, 7), 4500 /* TXFIR_POST3_ADJUSTED:12:15 */ 4501 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1334, 15, 12) 4502 }; 4503 static uint32_t BCMI_TSCE_XGXS_TXFIR_UC_CTLr_fields[] = 4504 { 4505 /* MICRO_TX_DISABLE:0:0 */ 4506 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(936, 0, 0) 4507 }; 4508 static uint32_t BCMI_TSCE_XGXS_TX_PI_CTL0r_fields[] = 4509 { 4510 /* TX_PI_EN:0:0 */ 4511 PHYMOD_SYMBOL_FIELD_ENCODE(1372, 0, 0), 4512 /* TX_PI_JITTER_FILTER_EN:1:1 */ 4513 PHYMOD_SYMBOL_FIELD_ENCODE(1384, 1, 1), 4514 /* TX_PI_EXT_CTRL_EN:2:2 */ 4515 PHYMOD_SYMBOL_FIELD_ENCODE(1373, 2, 2), 4516 /* TX_PI_FREQ_OVERRIDE_EN:3:3 */ 4517 PHYMOD_SYMBOL_FIELD_ENCODE(1377, 3, 3), 4518 /* TX_PI_SJ_GEN_EN:4:4 */ 4519 PHYMOD_SYMBOL_FIELD_ENCODE(1403, 4, 4), 4520 /* TX_PI_SSC_GEN_EN:5:5 */ 4521 PHYMOD_SYMBOL_FIELD_ENCODE(1404, 5, 5), 4522 /* TX_PI_JIT_SSC_FREQ_MODE:6:6 */ 4523 PHYMOD_SYMBOL_FIELD_ENCODE(1387, 6, 6), 4524 /* TX_PI_SECOND_ORDER_LOOP_EN:7:7 */ 4525 PHYMOD_SYMBOL_FIELD_ENCODE(1402, 7, 7), 4526 /* TX_PI_FIRST_ORDER_BWSEL_INTEG:8:9 */ 4527 PHYMOD_SYMBOL_FIELD_ENCODE(1375, 9, 8), 4528 /* TX_PI_SECOND_ORDER_BWSEL_INTEG:10:11 */ 4529 PHYMOD_SYMBOL_FIELD_ENCODE(1401, 11, 10), 4530 /* TX_PI_EXT_PHASE_BWSEL_INTEG:12:14 */ 4531 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1374, 14, 12) 4532 }; 4533 static uint32_t BCMI_TSCE_XGXS_TX_PI_CTL1r_fields[] = 4534 { 4535 /* TX_PI_FREQ_OVERRIDE_VAL:0:14 */ 4536 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1378, 14, 0) 4537 }; 4538 static uint32_t BCMI_TSCE_XGXS_TX_PI_CTL2r_fields[] = 4539 { 4540 /* TX_PI_JIT_FREQ_IDX:0:5 */ 4541 PHYMOD_SYMBOL_FIELD_ENCODE(1386, 5, 0), 4542 /* TX_PI_JIT_AMP:8:13 */ 4543 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1385, 13, 8) 4544 }; 4545 static uint32_t BCMI_TSCE_XGXS_TX_PI_CTL3r_fields[] = 4546 { 4547 /* TX_PI_PHASE_OVERRIDE:0:0 */ 4548 PHYMOD_SYMBOL_FIELD_ENCODE(1395, 0, 0), 4549 /* TX_PI_PHASE_STROBE:1:1 */ 4550 PHYMOD_SYMBOL_FIELD_ENCODE(1398, 1, 1), 4551 /* TX_PI_PHASE_STEP_DIR:2:2 */ 4552 PHYMOD_SYMBOL_FIELD_ENCODE(1396, 2, 2), 4553 /* TX_PI_PHASE_INVERT:4:4 */ 4554 PHYMOD_SYMBOL_FIELD_ENCODE(1394, 4, 4), 4555 /* TX_PI_PHASE_STEP_NUM:8:11 */ 4556 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1397, 11, 8) 4557 }; 4558 static uint32_t BCMI_TSCE_XGXS_TX_PI_CTL4r_fields[] = 4559 { 4560 /* TX_PI_FRZ_FRC:0:0 */ 4561 PHYMOD_SYMBOL_FIELD_ENCODE(1379, 0, 0), 4562 /* TX_PI_FRZ_FRC_VAL:1:1 */ 4563 PHYMOD_SYMBOL_FIELD_ENCODE(1380, 1, 1), 4564 /* TX_PI_FRZ_MODE:2:2 */ 4565 PHYMOD_SYMBOL_FIELD_ENCODE(1381, 2, 2), 4566 /* TX_PI_RESET_CODE_DBG:3:3 */ 4567 PHYMOD_SYMBOL_FIELD_ENCODE(1399, 3, 3), 4568 /* TX_PI_RMT_LPBK_BYPASS_FLT:4:4 */ 4569 PHYMOD_SYMBOL_FIELD_ENCODE(1400, 4, 4), 4570 /* TX_PI_FRC_PHASE_STEP_MUX_SEL:5:5 */ 4571 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1376, 5, 5) 4572 }; 4573 static uint32_t BCMI_TSCE_XGXS_TX_PI_CTL6r_fields[] = 4574 { 4575 /* TX_PI_LANE_SEL_FRC_VAL:0:4 */ 4576 PHYMOD_SYMBOL_FIELD_ENCODE(1389, 4, 0), 4577 /* TX_PI_LANE_SEL_FRC:8:8 */ 4578 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1388, 8, 8) 4579 }; 4580 static uint32_t BCMI_TSCE_XGXS_TX_PI_STS0r_fields[] = 4581 { 4582 /* TX_PI_PHASE_CNTR:0:6 */ 4583 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1392, 6, 0) 4584 }; 4585 static uint32_t BCMI_TSCE_XGXS_TX_PI_STS1r_fields[] = 4586 { 4587 /* TX_PI_INTEG1_REG:0:13 */ 4588 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1382, 13, 0) 4589 }; 4590 static uint32_t BCMI_TSCE_XGXS_TX_PI_STS2r_fields[] = 4591 { 4592 /* TX_PI_INTEG2_REG:0:14 */ 4593 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1383, 14, 0) 4594 }; 4595 static uint32_t BCMI_TSCE_XGXS_TX_PI_STS3r_fields[] = 4596 { 4597 /* TX_PI_PHASE_ERR:0:5 */ 4598 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1393, 5, 0) 4599 }; 4600 static uint32_t BCMI_TSCE_XGXS_TX_X2_BRCM_MODEr_fields[] = 4601 { 4602 /* ACOL_SWAP_COUNT64B66B:0:7 */ 4603 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(0, 7, 0) 4604 }; 4605 static uint32_t BCMI_TSCE_XGXS_TX_X2_CL48_0r_fields[] = 4606 { 4607 /* CL48_TX_QRSVDCTRL:0:3 */ 4608 PHYMOD_SYMBOL_FIELD_ENCODE(441, 3, 0), 4609 /* CL48_TX_RF_ENABLE:4:4 */ 4610 PHYMOD_SYMBOL_FIELD_ENCODE(442, 4, 4), 4611 /* CL48_TX_LF_ENABLE:5:5 */ 4612 PHYMOD_SYMBOL_FIELD_ENCODE(439, 5, 5), 4613 /* CL48_TX_LI_ENABLE:6:6 */ 4614 PHYMOD_SYMBOL_FIELD_ENCODE(440, 6, 6), 4615 /* BRCM_MODE_USE_K20PT5:15:15 */ 4616 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(348, 15, 15) 4617 }; 4618 static uint32_t BCMI_TSCE_XGXS_TX_X2_CL82_0r_fields[] = 4619 { 4620 /* CL82_TX_RF_ENABLE:4:4 */ 4621 PHYMOD_SYMBOL_FIELD_ENCODE(542, 4, 4), 4622 /* CL82_TX_LF_ENABLE:5:5 */ 4623 PHYMOD_SYMBOL_FIELD_ENCODE(540, 5, 5), 4624 /* CL82_TX_LI_ENABLE:6:6 */ 4625 PHYMOD_SYMBOL_FIELD_ENCODE(541, 6, 6), 4626 /* CL82_BYPASS_TXSM:10:10 */ 4627 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(530, 10, 10) 4628 }; 4629 static uint32_t BCMI_TSCE_XGXS_TX_X2_CL82_TX_STS0r_fields[] = 4630 { 4631 /* TXSM_STATE:0:2 */ 4632 PHYMOD_SYMBOL_FIELD_ENCODE(1346, 2, 0), 4633 /* LTXSM_STATE:3:9 */ 4634 PHYMOD_SYMBOL_FIELD_ENCODE(866, 9, 3), 4635 /* T_TYPE_CODED:10:12 */ 4636 PHYMOD_SYMBOL_FIELD_ENCODE(1413, 12, 10), 4637 /* CL82_IDLE_DELETION_UNDERFLOW:13:13 */ 4638 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(533, 13, 13) 4639 }; 4640 static uint32_t BCMI_TSCE_XGXS_TX_X2_MLD_SWP_CNTr_fields[] = 4641 { 4642 /* MLD_SWAP_COUNT:0:15 */ 4643 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(941, 15, 0) 4644 }; 4645 static uint32_t BCMI_TSCE_XGXS_TX_X4_CRED0r_fields[] = 4646 { 4647 /* CLOCKCNT0:0:13 */ 4648 PHYMOD_SYMBOL_FIELD_ENCODE(545, 13, 0), 4649 /* CREDITENABLE:14:14 */ 4650 PHYMOD_SYMBOL_FIELD_ENCODE(570, 14, 14), 4651 /* SGMII_SPD_SWITCH:15:15 */ 4652 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1234, 15, 15) 4653 }; 4654 static uint32_t BCMI_TSCE_XGXS_TX_X4_CRED1r_fields[] = 4655 { 4656 /* CLOCKCNT1:0:7 */ 4657 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(547, 7, 0) 4658 }; 4659 static uint32_t BCMI_TSCE_XGXS_TX_X4_ENC0r_fields[] = 4660 { 4661 /* ENCODEMODE:2:4 */ 4662 PHYMOD_SYMBOL_FIELD_ENCODE(712, 4, 2), 4663 /* CL49_TX_TL_MODE:5:6 */ 4664 PHYMOD_SYMBOL_FIELD_ENCODE(462, 6, 5), 4665 /* CL49_BYPASS_TXSM:9:9 */ 4666 PHYMOD_SYMBOL_FIELD_ENCODE(447, 9, 9), 4667 /* HG2_ENABLE:10:10 */ 4668 PHYMOD_SYMBOL_FIELD_ENCODE(756, 10, 10), 4669 /* HG2_MESSAGE_INVALID_CODE_ENABLE:11:11 */ 4670 PHYMOD_SYMBOL_FIELD_ENCODE(757, 11, 11), 4671 /* HG2_CODEC:12:12 */ 4672 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(755, 12, 12) 4673 }; 4674 static uint32_t BCMI_TSCE_XGXS_TX_X4_ENC1r_fields[] = 4675 { 4676 /* PROG_TL_CHAR:0:7 */ 4677 PHYMOD_SYMBOL_FIELD_ENCODE(1090, 7, 0), 4678 /* PROG_TL_EN:8:8 */ 4679 PHYMOD_SYMBOL_FIELD_ENCODE(1091, 8, 8), 4680 /* CATCH_ALL_8B10B_DIS:9:9 */ 4681 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(370, 9, 9) 4682 }; 4683 static uint32_t BCMI_TSCE_XGXS_TX_X4_ENC_STS0r_fields[] = 4684 { 4685 /* CL49_TXSM_STATE:0:2 */ 4686 PHYMOD_SYMBOL_FIELD_ENCODE(457, 2, 0), 4687 /* CL49_LTXSM_STATE:3:10 */ 4688 PHYMOD_SYMBOL_FIELD_ENCODE(450, 10, 3), 4689 /* CL49_TX_FAULT_DET:11:11 */ 4690 PHYMOD_SYMBOL_FIELD_ENCODE(458, 11, 11), 4691 /* CL49_T_TYPE_CODED:12:15 */ 4692 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(463, 15, 12) 4693 }; 4694 static uint32_t BCMI_TSCE_XGXS_TX_X4_LOOPCNTr_fields[] = 4695 { 4696 /* LOOPCNT1:0:5 */ 4697 PHYMOD_SYMBOL_FIELD_ENCODE(840, 5, 0), 4698 /* LOOPCNT0:6:13 */ 4699 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(838, 13, 6) 4700 }; 4701 static uint32_t BCMI_TSCE_XGXS_TX_X4_MAC_CREDGENCNTr_fields[] = 4702 { 4703 /* MAC_CREDITGENCNT:0:12 */ 4704 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(869, 12, 0) 4705 }; 4706 static uint32_t BCMI_TSCE_XGXS_TX_X4_MISCr_fields[] = 4707 { 4708 /* ENABLE_TX_LANE:0:0 */ 4709 PHYMOD_SYMBOL_FIELD_ENCODE(711, 0, 0), 4710 /* RSTB_TX_LANE:1:1 */ 4711 PHYMOD_SYMBOL_FIELD_ENCODE(1161, 1, 1), 4712 /* TX_FIFO_WATERMARK:2:3 */ 4713 PHYMOD_SYMBOL_FIELD_ENCODE(1358, 3, 2), 4714 /* CL49_TX_RF_ENABLE:6:6 */ 4715 PHYMOD_SYMBOL_FIELD_ENCODE(461, 6, 6), 4716 /* CL49_TX_LF_ENABLE:7:7 */ 4717 PHYMOD_SYMBOL_FIELD_ENCODE(459, 7, 7), 4718 /* CL49_TX_LI_ENABLE:8:8 */ 4719 PHYMOD_SYMBOL_FIELD_ENCODE(460, 8, 8), 4720 /* FEC_ENABLE:10:10 */ 4721 PHYMOD_SYMBOL_FIELD_ENCODE(736, 10, 10), 4722 /* SCR_MODE:14:15 */ 4723 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1203, 15, 14) 4724 }; 4725 static uint32_t BCMI_TSCE_XGXS_TX_X4_PCS_CLKCNT0r_fields[] = 4726 { 4727 /* PCS_CLOCKCNT0:0:13 */ 4728 PHYMOD_SYMBOL_FIELD_ENCODE(993, 13, 0), 4729 /* PCS_CREDITENABLE:14:14 */ 4730 PHYMOD_SYMBOL_FIELD_ENCODE(995, 14, 14), 4731 /* REPLICATION_CNT:15:15 */ 4732 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1114, 15, 15) 4733 }; 4734 static uint32_t BCMI_TSCE_XGXS_TX_X4_PCS_CREDGENCNTr_fields[] = 4735 { 4736 /* PCS_CREDITGENCNT:0:12 */ 4737 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(997, 12, 0) 4738 }; 4739 static uint32_t BCMI_TSCE_XGXS_TX_X4_PCS_STSr_fields[] = 4740 { 4741 /* LPI_RECEIVED_LH:0:0 */ 4742 PHYMOD_SYMBOL_FIELD_ENCODE(848, 0, 0), 4743 /* RESERVED_ORDERED_SET_LH:1:1 */ 4744 PHYMOD_SYMBOL_FIELD_ENCODE(1120, 1, 1), 4745 /* REMOTE_FAULT_LH:2:2 */ 4746 PHYMOD_SYMBOL_FIELD_ENCODE(1109, 2, 2), 4747 /* LOCAL_FAULT_LH:3:3 */ 4748 PHYMOD_SYMBOL_FIELD_ENCODE(832, 3, 3), 4749 /* LINK_INTERRUPT_LH:4:4 */ 4750 PHYMOD_SYMBOL_FIELD_ENCODE(811, 4, 4), 4751 /* TX_LPI_RECEIVED:5:5 */ 4752 PHYMOD_SYMBOL_FIELD_ENCODE(1367, 5, 5), 4753 /* TX_LINK_INTERRUPT:6:6 */ 4754 PHYMOD_SYMBOL_FIELD_ENCODE(1365, 6, 6), 4755 /* TX_REMOTE_FAULT:7:7 */ 4756 PHYMOD_SYMBOL_FIELD_ENCODE(1407, 7, 7), 4757 /* TX_LOCAL_FAULT:8:8 */ 4758 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1366, 8, 8) 4759 }; 4760 static uint32_t BCMI_TSCE_XGXS_UC_ADDRr_fields[] = 4761 { 4762 /* MICRO_RAM_ADDRESS:0:15 */ 4763 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(920, 15, 0) 4764 }; 4765 static uint32_t BCMI_TSCE_XGXS_UC_COMMANDr_fields[] = 4766 { 4767 /* MICRO_RUN:0:0 */ 4768 PHYMOD_SYMBOL_FIELD_ENCODE(926, 0, 0), 4769 /* MICRO_STOP:1:1 */ 4770 PHYMOD_SYMBOL_FIELD_ENCODE(932, 1, 1), 4771 /* MICRO_READ:2:2 */ 4772 PHYMOD_SYMBOL_FIELD_ENCODE(925, 2, 2), 4773 /* MICRO_WRITE:3:3 */ 4774 PHYMOD_SYMBOL_FIELD_ENCODE(939, 3, 3), 4775 /* MICRO_MDIO_DW8051_RESET_N:4:4 */ 4776 PHYMOD_SYMBOL_FIELD_ENCODE(906, 4, 4), 4777 /* MICRO_MDIO_RAM_READ_AUTOINC_EN:6:6 */ 4778 PHYMOD_SYMBOL_FIELD_ENCODE(910, 6, 6), 4779 /* MICRO_MDIO_RAM_ACCESS_MODE:7:8 */ 4780 PHYMOD_SYMBOL_FIELD_ENCODE(909, 8, 7), 4781 /* MICRO_BYTE_MODE:9:9 */ 4782 PHYMOD_SYMBOL_FIELD_ENCODE(893, 9, 9), 4783 /* MICRO_MDIO_AUTOWAKEUP:10:10 */ 4784 PHYMOD_SYMBOL_FIELD_ENCODE(905, 10, 10), 4785 /* MICRO_MDIO_PROG_RAM_CS_FRC:11:11 */ 4786 PHYMOD_SYMBOL_FIELD_ENCODE(907, 11, 11), 4787 /* MICRO_MDIO_PROG_RAM_CS_FRC_VAL:12:12 */ 4788 PHYMOD_SYMBOL_FIELD_ENCODE(908, 12, 12), 4789 /* MICRO_PMI_HP_ACK_FRC:13:13 */ 4790 PHYMOD_SYMBOL_FIELD_ENCODE(914, 13, 13), 4791 /* MICRO_PMI_HP_ACK_FRC_VAL:14:14 */ 4792 PHYMOD_SYMBOL_FIELD_ENCODE(915, 14, 14), 4793 /* MICRO_INIT_CMD:15:15 */ 4794 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(900, 15, 15) 4795 }; 4796 static uint32_t BCMI_TSCE_XGXS_UC_COMMAND2r_fields[] = 4797 { 4798 /* MICRO_PMI_ACK_TIMEOUT_VAL:0:3 */ 4799 PHYMOD_SYMBOL_FIELD_ENCODE(913, 3, 0), 4800 /* MICRO_SRST_MDIO_DATARAM_ACCESS:10:10 */ 4801 PHYMOD_SYMBOL_FIELD_ENCODE(928, 10, 10), 4802 /* MICRO_RAM_CLK_INVERT:11:11 */ 4803 PHYMOD_SYMBOL_FIELD_ENCODE(921, 11, 11), 4804 /* MICRO_ZERO_ROM_DATAOUT:12:12 */ 4805 PHYMOD_SYMBOL_FIELD_ENCODE(940, 12, 12), 4806 /* MICRO_SRST_MDIO_LOAD_PROGRAM_RAM:13:13 */ 4807 PHYMOD_SYMBOL_FIELD_ENCODE(929, 13, 13), 4808 /* MICRO_SRST_MDIO_PROGRAM_ACCESS:14:14 */ 4809 PHYMOD_SYMBOL_FIELD_ENCODE(930, 14, 14), 4810 /* MICRO_SRST_DW8051_TO_PMI:15:15 */ 4811 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(927, 15, 15) 4812 }; 4813 static uint32_t BCMI_TSCE_XGXS_UC_COMMAND3r_fields[] = 4814 { 4815 /* MICRO_PRAM_IF_EN:0:0 */ 4816 PHYMOD_SYMBOL_FIELD_ENCODE(916, 0, 0), 4817 /* MICRO_PRAM_IF_FLOP_BYPASS:1:1 */ 4818 PHYMOD_SYMBOL_FIELD_ENCODE(917, 1, 1), 4819 /* MICRO_PRAM_IF_RSTB:2:2 */ 4820 PHYMOD_SYMBOL_FIELD_ENCODE(918, 2, 2), 4821 /* MICRO_INRUSH_CURRENT_FRC:10:10 */ 4822 PHYMOD_SYMBOL_FIELD_ENCODE(902, 10, 10), 4823 /* MICRO_INRUSH_CURRENT_FRC_VAL:11:11 */ 4824 PHYMOD_SYMBOL_FIELD_ENCODE(903, 11, 11), 4825 /* MICRO_DISABLE_ECC:12:12 */ 4826 PHYMOD_SYMBOL_FIELD_ENCODE(895, 12, 12), 4827 /* MICRO_GEN_STATUS_SEL:13:15 */ 4828 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(899, 15, 13) 4829 }; 4830 static uint32_t BCMI_TSCE_XGXS_UC_COMMAND4r_fields[] = 4831 { 4832 /* MICRO_SYSTEM_CLK_EN:0:0 */ 4833 PHYMOD_SYMBOL_FIELD_ENCODE(933, 0, 0), 4834 /* MICRO_SYSTEM_RESET_N:1:1 */ 4835 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(934, 1, 1) 4836 }; 4837 static uint32_t BCMI_TSCE_XGXS_UC_DATARAM_CTL1r_fields[] = 4838 { 4839 /* MICRO_DATARAM_TM:0:9 */ 4840 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(894, 9, 0) 4841 }; 4842 static uint32_t BCMI_TSCE_XGXS_UC_DWNLOAD_STSr_fields[] = 4843 { 4844 /* MICRO_ERR0:0:0 */ 4845 PHYMOD_SYMBOL_FIELD_ENCODE(896, 0, 0), 4846 /* MICRO_ERR1:1:1 */ 4847 PHYMOD_SYMBOL_FIELD_ENCODE(897, 1, 1), 4848 /* MICRO_FSM:2:5 */ 4849 PHYMOD_SYMBOL_FIELD_ENCODE(898, 5, 2), 4850 /* MICRO_INIT_DONE:15:15 */ 4851 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(901, 15, 15) 4852 }; 4853 static uint32_t BCMI_TSCE_XGXS_UC_IRAM_CTL1r_fields[] = 4854 { 4855 /* MICRO_IRAM_TM:0:9 */ 4856 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(904, 9, 0) 4857 }; 4858 static uint32_t BCMI_TSCE_XGXS_UC_MDIO_UC_MAILBOX_LSWr_fields[] = 4859 { 4860 /* MICRO_MDIO_UC_MAILBOX_LSW:0:15 */ 4861 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(911, 15, 0) 4862 }; 4863 static uint32_t BCMI_TSCE_XGXS_UC_MDIO_UC_MAILBOX_MSWr_fields[] = 4864 { 4865 /* MICRO_MDIO_UC_MAILBOX_MSW:0:15 */ 4866 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(912, 15, 0) 4867 }; 4868 static uint32_t BCMI_TSCE_XGXS_UC_PROGRAM_RAM_CTL1r_fields[] = 4869 { 4870 /* MICRO_PROGRAM_RAM_TM:0:13 */ 4871 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(919, 13, 0) 4872 }; 4873 static uint32_t BCMI_TSCE_XGXS_UC_RAMWORDr_fields[] = 4874 { 4875 /* MICRO_RAM_COUNT:0:15 */ 4876 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(922, 15, 0) 4877 }; 4878 static uint32_t BCMI_TSCE_XGXS_UC_RAM_RDDATAr_fields[] = 4879 { 4880 /* MICRO_RAM_RDDATA:0:15 */ 4881 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(923, 15, 0) 4882 }; 4883 static uint32_t BCMI_TSCE_XGXS_UC_RAM_WRDATAr_fields[] = 4884 { 4885 /* MICRO_RAM_WRDATA:0:15 */ 4886 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(924, 15, 0) 4887 }; 4888 static uint32_t BCMI_TSCE_XGXS_UC_SFR_STSr_fields[] = 4889 { 4890 /* MICRO_STATUS_MUXED:0:15 */ 4891 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(931, 15, 0) 4892 }; 4893 static uint32_t BCMI_TSCE_XGXS_UC_TEMPERATURE_STSr_fields[] = 4894 { 4895 /* MICRO_TEMPATURE_DATA:0:15 */ 4896 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(935, 15, 0) 4897 }; 4898 static uint32_t BCMI_TSCE_XGXS_UC_UC_MDIO_MAILBOX_LSWr_fields[] = 4899 { 4900 /* MICRO_UC_MDIO_MAILBOX_LSW:0:15 */ 4901 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(937, 15, 0) 4902 }; 4903 static uint32_t BCMI_TSCE_XGXS_UC_UC_MDIO_MAILBOX_MSWr_fields[] = 4904 { 4905 /* MICRO_UC_MDIO_MAILBOX_MSW:0:15 */ 4906 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(938, 15, 0) 4907 }; 4908 4909 4910 4911 /******************************************************************************* 4912 * 4913 * The following is the field name table. 4914 */ 4915 #if PHYMOD_CONFIG_INCLUDE_FIELD_NAMES == 1 4916 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_NAMES_BCMI_TSCE_XGXS 4917 const char* bcmi_tsce_xgxs_fields[] = 4918 { 4919 "ACOL_SWAP_COUNT64B66B", 4920 "ACQ_CDR_TIMEOUT", 4921 "AFE_RX_PWRDN_FRC", 4922 "AFE_RX_PWRDN_FRC_VAL", 4923 "AFE_RX_RESET_FRC", 4924 "AFE_RX_RESET_FRC_VAL", 4925 "AFE_SIGDET_PWRDN", 4926 "AFE_SIGDET_THRESH", 4927 "AFE_SIGNAL_DETECT_DIS", 4928 "AFE_S_PLL_PWRDN", 4929 "AFE_S_PLL_RESET_FRC", 4930 "AFE_S_PLL_RESET_FRC_VAL", 4931 "AFE_TX_PWRDN_FRC", 4932 "AFE_TX_PWRDN_FRC_VAL", 4933 "AFE_TX_RESET_FRC", 4934 "AFE_TX_RESET_FRC_VAL", 4935 "ALIGN_STATUS_CL82", 4936 "AMRKR_SPACING_ERR_LATCH_MUX", 4937 "AMS_PLL_2RX_CLKBW", 4938 "AMS_PLL_BGCALR_CTATADJ", 4939 "AMS_PLL_BGCALR_PTATADJ", 4940 "AMS_PLL_BGINT", 4941 "AMS_PLL_BGIP", 4942 "AMS_PLL_BGR_CTATADJ", 4943 "AMS_PLL_BGR_PTATADJ", 4944 "AMS_PLL_CAL_AUX", 4945 "AMS_PLL_CAL_OFF", 4946 "AMS_PLL_COMP_VTH", 4947 "AMS_PLL_DBLR_CTRL", 4948 "AMS_PLL_DITHEREN", 4949 "AMS_PLL_ENABLE_FTUNE", 4950 "AMS_PLL_EN_HRZ", 4951 "AMS_PLL_FORCE_KVH_BW", 4952 "AMS_PLL_FORCE_RESCAL", 4953 "AMS_PLL_FP3_CTRL", 4954 "AMS_PLL_FP3_RH", 4955 "AMS_PLL_FRACN_BYPASS", 4956 "AMS_PLL_FRACN_DIVRANGE", 4957 "AMS_PLL_FRACN_DIV_H", 4958 "AMS_PLL_FRACN_DIV_L", 4959 "AMS_PLL_FRACN_NDIV_INT", 4960 "AMS_PLL_FRACN_SEL", 4961 "AMS_PLL_IMAX_I10GBUF", 4962 "AMS_PLL_IMAX_IBIAS", 4963 "AMS_PLL_IMAX_ICK", 4964 "AMS_PLL_IMAX_ICKGEN", 4965 "AMS_PLL_IMAX_ICLKIDRV1", 4966 "AMS_PLL_IMAX_ICLKINT", 4967 "AMS_PLL_IMAX_ICML", 4968 "AMS_PLL_IMAX_ICOMP", 4969 "AMS_PLL_IMAX_ICP", 4970 "AMS_PLL_IMAX_IOP", 4971 "AMS_PLL_IMIN_I10GBUF", 4972 "AMS_PLL_IMIN_IBIAS", 4973 "AMS_PLL_IMIN_ICK", 4974 "AMS_PLL_IMIN_ICKGEN", 4975 "AMS_PLL_IMIN_ICLKIDRV1", 4976 "AMS_PLL_IMIN_ICLKINT", 4977 "AMS_PLL_IMIN_ICML", 4978 "AMS_PLL_IMIN_ICOMP", 4979 "AMS_PLL_IMIN_ICP", 4980 "AMS_PLL_IMIN_IOP", 4981 "AMS_PLL_IMODE_I10GBUF", 4982 "AMS_PLL_IMODE_IBIAS", 4983 "AMS_PLL_IMODE_ICK", 4984 "AMS_PLL_IMODE_ICKGEN", 4985 "AMS_PLL_IMODE_ICLKIDRV1", 4986 "AMS_PLL_IMODE_ICLKINT", 4987 "AMS_PLL_IMODE_ICML", 4988 "AMS_PLL_IMODE_ICOMP", 4989 "AMS_PLL_IMODE_ICP", 4990 "AMS_PLL_IMODE_IOP", 4991 "AMS_PLL_IQP", 4992 "AMS_PLL_IVCO", 4993 "AMS_PLL_KVH_FORCE", 4994 "AMS_PLL_LOWPWR_6G", 4995 "AMS_PLL_MAX_TEST_PORT_AMPL", 4996 "AMS_PLL_MIX2P1CR_CTATADJ", 4997 "AMS_PLL_MIX2P1CR_PTATADJ", 4998 "AMS_PLL_PDF_FD_SKEW", 4999 "AMS_PLL_PDF_REF_SKEW", 5000 "AMS_PLL_PDF_SKEW_ENLARGE", 5001 "AMS_PLL_REFCLK_DOUBLER", 5002 "AMS_PLL_REFH_PLL", 5003 "AMS_PLL_REFL_PLL", 5004 "AMS_PLL_RESET", 5005 "AMS_PLL_SPARE_100", 5006 "AMS_PLL_SPARE_18", 5007 "AMS_PLL_STS", 5008 "AMS_PLL_TEST_FRACN_EN", 5009 "AMS_PLL_TEST_PLL", 5010 "AMS_PLL_TEST_PNP", 5011 "AMS_PLL_TEST_RX", 5012 "AMS_PLL_TEST_VC", 5013 "AMS_PLL_TEST_VREF", 5014 "AMS_PLL_TXCG_VDDR_BGB", 5015 "AMS_PLL_TX_LOWPWR_6G", 5016 "AMS_PLL_VBYPASS", 5017 "AMS_PLL_VCOICTRL", 5018 "AMS_PLL_VCO_DIV2", 5019 "AMS_PLL_VCO_DIV4", 5020 "AMS_PLL_VCO_IMAX", 5021 "AMS_PLL_VDDR_BGB", 5022 "AMS_RX_DC_COUPLE", 5023 "AMS_RX_DC_OFFSET", 5024 "AMS_RX_DC_OFFSET_RANGE", 5025 "AMS_RX_DFE_OS2X_MODE", 5026 "AMS_RX_EN_10GMODE", 5027 "AMS_RX_EN_VCCTRL", 5028 "AMS_RX_FORCE_DC_OFFSET", 5029 "AMS_RX_I1P25DFE", 5030 "AMS_RX_I4DEADZONE", 5031 "AMS_RX_IMAX_COMMONMODE", 5032 "AMS_RX_IMAX_CTAT", 5033 "AMS_RX_IMAX_DC_OFFSET_DAC", 5034 "AMS_RX_IMAX_DFE_SUMMER", 5035 "AMS_RX_IMAX_DFE_TAP_WEIGHT", 5036 "AMS_RX_IMAX_METRES_EYEDIAG", 5037 "AMS_RX_IMAX_PF", 5038 "AMS_RX_IMAX_PHASE_INT", 5039 "AMS_RX_IMAX_PHASE_INT_P1", 5040 "AMS_RX_IMAX_SIGNAL_DETECT", 5041 "AMS_RX_IMAX_SLICER", 5042 "AMS_RX_IMAX_VGA", 5043 "AMS_RX_IMIN_COMMONMODE", 5044 "AMS_RX_IMIN_CTAT", 5045 "AMS_RX_IMIN_DC_OFFSET_DAC", 5046 "AMS_RX_IMIN_DFE_SUMMER", 5047 "AMS_RX_IMIN_DFE_TAP_WEIGHT", 5048 "AMS_RX_IMIN_METRES_EYEDIAG", 5049 "AMS_RX_IMIN_PF", 5050 "AMS_RX_IMIN_PHASE_INT", 5051 "AMS_RX_IMIN_PHASE_INT_P1", 5052 "AMS_RX_IMIN_SIGNAL_DETECT", 5053 "AMS_RX_IMIN_SLICER", 5054 "AMS_RX_IMIN_VGA", 5055 "AMS_RX_IMODE_CTAT", 5056 "AMS_RX_IMODE_DC_OFFSET_DAC", 5057 "AMS_RX_IMODE_DFE_SUMMER", 5058 "AMS_RX_IMODE_DFE_TAP_WEIGHT", 5059 "AMS_RX_IMODE_METRES_EYEDIAG", 5060 "AMS_RX_IMODE_PF", 5061 "AMS_RX_IMODE_PHASE_INT", 5062 "AMS_RX_IMODE_PHASE_INT_P1", 5063 "AMS_RX_IMODE_SIGNAL_DETECT", 5064 "AMS_RX_IMODE_SLICER", 5065 "AMS_RX_IMODE_VGA", 5066 "AMS_RX_IMOD_COMMONMODE", 5067 "AMS_RX_PHASE_INT_AMPL_CTRL", 5068 "AMS_RX_PHS_INTERP_RESCAL_MUX", 5069 "AMS_RX_SEL_DFECKDELAY", 5070 "AMS_RX_SEL_TH4DFE", 5071 "AMS_RX_SEL_UGBW", 5072 "AMS_RX_SIGDET_BYPASS", 5073 "AMS_RX_SIGDET_LOW_POWER", 5074 "AMS_RX_SIGDET_THRESHOLD", 5075 "AMS_RX_SIG_PWRDN", 5076 "AMS_RX_SPARE_32", 5077 "AMS_RX_SPARE_33", 5078 "AMS_RX_SPARE_34", 5079 "AMS_RX_SPARE_46", 5080 "AMS_RX_SPARE_47", 5081 "AMS_RX_SPARE_62", 5082 "AMS_RX_SPARE_63", 5083 "AMS_RX_STS", 5084 "AMS_RX_TPORT_EN", 5085 "AMS_RX_VGA_BW_EXTENSION", 5086 "AMS_RX_VGA_OUTPUT_IDLE", 5087 "AMS_RX_VGA_RESCAL_MUX", 5088 "AMS_TX_AMP_CTL", 5089 "AMS_TX_CAL_AUX", 5090 "AMS_TX_CAL_OFF", 5091 "AMS_TX_DCC_DIS", 5092 "AMS_TX_DCC_SEL", 5093 "AMS_TX_DRIVERMODE", 5094 "AMS_TX_ELEC_IDLE_AUX", 5095 "AMS_TX_IBIAS", 5096 "AMS_TX_ICML", 5097 "AMS_TX_IDCC", 5098 "AMS_TX_KR_TEST_MODE", 5099 "AMS_TX_LP_OVRD", 5100 "AMS_TX_OSR4", 5101 "AMS_TX_POST2_COEF", 5102 "AMS_TX_POST3_COEF", 5103 "AMS_TX_SEL_HALFRATE", 5104 "AMS_TX_SIGN_POST2", 5105 "AMS_TX_SIGN_POST3", 5106 "AMS_TX_SPARE_1", 5107 "AMS_TX_SPARE_2", 5108 "AMS_TX_SPARE_3", 5109 "AMS_TX_SPARE_30_25", 5110 "AMS_TX_STS", 5111 "AMS_TX_TEST_DATA", 5112 "AMS_TX_TICKSEL", 5113 "AM_LOCK", 5114 "AM_LOCK_HIS_STATE", 5115 "AM_LOCK_LH", 5116 "AM_LOCK_LL", 5117 "AM_LOCK_STATE", 5118 "AM_TIMER_INIT_RX_VAL", 5119 "AN", 5120 "AN_ACTIVE", 5121 "AN_COMPLETE", 5122 "AN_COMPLETED_SW", 5123 "AN_FAIL_COUNT", 5124 "AN_FAIL_COUNT_LIMIT", 5125 "AN_GOOD_CHECK_TRAP", 5126 "AN_GOOD_TRAP", 5127 "AN_HCD_CL72", 5128 "AN_HCD_DUPLEX", 5129 "AN_HCD_FEC", 5130 "AN_HCD_HIGIG2", 5131 "AN_HCD_PAUSE", 5132 "AN_HCD_SPEED", 5133 "AN_HCD_SWITCH_TO_CL37", 5134 "AN_PD_TO_CL37_ENABLE", 5135 "AN_PD_TO_CL37_RETRY_COUNT", 5136 "AN_PRIORITY_1000M", 5137 "AN_PRIORITY_100GCR10", 5138 "AN_PRIORITY_100M", 5139 "AN_PRIORITY_10GCX1", 5140 "AN_PRIORITY_10GCX2", 5141 "AN_PRIORITY_10GCX4", 5142 "AN_PRIORITY_10GKR", 5143 "AN_PRIORITY_10GKX4", 5144 "AN_PRIORITY_10GX2", 5145 "AN_PRIORITY_10GX4", 5146 "AN_PRIORITY_10M", 5147 "AN_PRIORITY_10P5GX2", 5148 "AN_PRIORITY_12GX4", 5149 "AN_PRIORITY_12P5GX4", 5150 "AN_PRIORITY_12P7GX2", 5151 "AN_PRIORITY_13GX4", 5152 "AN_PRIORITY_15GX4", 5153 "AN_PRIORITY_15P75GX2", 5154 "AN_PRIORITY_16GX4", 5155 "AN_PRIORITY_1GKX", 5156 "AN_PRIORITY_20GCR2", 5157 "AN_PRIORITY_20GCX2", 5158 "AN_PRIORITY_20GCX4", 5159 "AN_PRIORITY_20GKR2", 5160 "AN_PRIORITY_20GX2", 5161 "AN_PRIORITY_20GX4", 5162 "AN_PRIORITY_21GX4", 5163 "AN_PRIORITY_25P45GX4", 5164 "AN_PRIORITY_2P5GX1", 5165 "AN_PRIORITY_31P5G", 5166 "AN_PRIORITY_32P7G", 5167 "AN_PRIORITY_40GCR4", 5168 "AN_PRIORITY_40GKR4", 5169 "AN_PRIORITY_40GX4", 5170 "AN_PRIORITY_5GX4", 5171 "AN_PRIORITY_6GX4", 5172 "AN_RETRY_COUNT", 5173 "AN_RX_ST_CLK_TRANS_MISS", 5174 "AN_RX_ST_MV_PAIR", 5175 "AN_RX_ST_PAGE", 5176 "AN_RX_ST_PAGE_TOO_LONG", 5177 "AN_RX_ST_PAGE_TOO_SHORT", 5178 "AN_RX_ST_PULSE_TOO_LONG", 5179 "AN_RX_ST_PULSE_TOO_MODERATE", 5180 "AN_RX_ST_PULSE_TOO_SHORT", 5181 "AN_RX_ST_RUDI_CONFIG", 5182 "AN_RX_ST_RUDI_IDLE", 5183 "AN_RX_ST_RUDI_INVALID", 5184 "AN_RX_ST_STATE", 5185 "AN_ST_ABILITY_DETECT", 5186 "AN_ST_ACK_DETECT", 5187 "AN_ST_AN_ENABLE", 5188 "AN_ST_AN_GOOD_CHECK", 5189 "AN_ST_CL37_COMPLETE", 5190 "AN_ST_CL73_COMPLETE", 5191 "AN_ST_COMPLETE_ACK", 5192 "AN_ST_CONFIG_NONZERO", 5193 "AN_ST_CONFIG_RESTART", 5194 "AN_ST_CONSISTENCY_MISMATCH", 5195 "AN_ST_DISABLE_LINK", 5196 "AN_ST_ERROR_STATE", 5197 "AN_ST_HP_MODE", 5198 "AN_ST_IDLE_DETECT", 5199 "AN_ST_LINK_OK", 5200 "AN_ST_NEXT_PAGE_WAIT", 5201 "AN_ST_RESOLUTION_ERR", 5202 "AN_ST_RESTART", 5203 "AN_ST_RX_BP", 5204 "AN_ST_RX_INVALID_SEQ", 5205 "AN_ST_RX_MP_MISMATCH", 5206 "AN_ST_RX_MP_NULL", 5207 "AN_ST_RX_MP_OUI", 5208 "AN_ST_RX_MP_OVER1G", 5209 "AN_ST_RX_NP", 5210 "AN_ST_RX_NP_TOGGLE_ERR", 5211 "AN_ST_RX_SGMII_MISMATCH", 5212 "AN_ST_RX_UP_3", 5213 "AN_ST_RX_UP_OUI_MATCH", 5214 "AN_ST_RX_UP_OUI_MISMATCH", 5215 "AN_ST_SGMII_MODE", 5216 "B66DEC_CGBAD_EN", 5217 "B66DEC_DOUT_ERRORS_IF_BAD_SYNC", 5218 "B66DEC_FAULT_DET", 5219 "B66DEC_FAULT_DET_EN", 5220 "B66DEC_KCODE66ERRCOUNT_EN", 5221 "B66DEC_NOBLOCKLOCK_DOUT_SEL", 5222 "B66DEC_PROG_TL_CHAR", 5223 "B66DEC_PROG_TL_EN", 5224 "B66DEC_SYNCERRCOUNT_EN", 5225 "BAM_10GBASE_X2", 5226 "BAM_10GBASE_X2_CX4", 5227 "BAM_10GBASE_X4", 5228 "BAM_10GBASE_X4_CX4", 5229 "BAM_10P5GBASE_X2", 5230 "BAM_12GBASE_X4", 5231 "BAM_12P5GBASE_X4", 5232 "BAM_12P7GBASE_X2", 5233 "BAM_13GBASE_X4", 5234 "BAM_15GBASE_X4", 5235 "BAM_15P75GBASE_X2", 5236 "BAM_16GBASE_X4", 5237 "BAM_20GBASE_CR2", 5238 "BAM_20GBASE_KR2", 5239 "BAM_20GBASE_X2", 5240 "BAM_20GBASE_X2_CX4", 5241 "BAM_20GBASE_X4", 5242 "BAM_20GBASE_X4_CX4", 5243 "BAM_21GBASE_X4", 5244 "BAM_25P455GBASE_X4", 5245 "BAM_2P5GBASE_X", 5246 "BAM_31P5GBASE_X4", 5247 "BAM_32P7GBASE_X4", 5248 "BAM_40GBASE_X4", 5249 "BAM_5GBASE_X4", 5250 "BAM_6GBASE_X4", 5251 "BASE_1000BASE_KX", 5252 "BASE_100GBASE_CR10", 5253 "BASE_10GBASE_KR", 5254 "BASE_10GBASE_KX4", 5255 "BASE_40GBASE_CR4", 5256 "BASE_40GBASE_KR4", 5257 "BASE_SELECTOR", 5258 "BERMON_STATE", 5259 "BER_COUNT_PER_LN", 5260 "BER_HO", 5261 "BIP_ERROR_COUNT_PER_LANE", 5262 "BLOCK_SYNC_MODE", 5263 "BLOCK_SYNC_MODE_OEN", 5264 "BONDING", 5265 "BRCM64B66_DESCRAMBLER_ENABLE", 5266 "BRCM64B66_DESCRAMBLER_ENABLE_OEN", 5267 "BRCM_MODE_USE_K20PT5", 5268 "BR_PD_EN", 5269 "BURST_ERR_STATUSH", 5270 "BURST_ERR_STATUSL", 5271 "BURST_ERR_STATUS_MODE", 5272 "BYPASS_CL49RXSM", 5273 "BYPASS_CL82RXSM", 5274 "BYTE0", 5275 "BYTE1", 5276 "CAP_CNT_MASK_EN", 5277 "CAP_DONE", 5278 "CAP_DONE_LH_LL", 5279 "CAP_FORCE_SLOWDOWN", 5280 "CAP_FORCE_SLOWDOWN_EN", 5281 "CAP_PASS", 5282 "CAP_PASS_LH_LL", 5283 "CAP_RESTART", 5284 "CAP_RETRY_EN", 5285 "CAP_SELECT", 5286 "CAP_SELECT_M", 5287 "CAP_SELECT_M_EN", 5288 "CAP_SEQ_CYA", 5289 "CATCH_ALL_8B10B_DIS", 5290 "CDR_BWSEL_INTEG_ACQCDR", 5291 "CDR_BWSEL_INTEG_EEE_ACQCDR", 5292 "CDR_BWSEL_INTEG_NORM", 5293 "CDR_BWSEL_PROP_ACQCDR", 5294 "CDR_BWSEL_PROP_EEE_ACQCDR", 5295 "CDR_BWSEL_PROP_NORM", 5296 "CDR_FREQ_EN", 5297 "CDR_FREQ_OVERRIDE_EN", 5298 "CDR_FREQ_OVERRIDE_VAL", 5299 "CDR_FRZ_FRC", 5300 "CDR_FRZ_FRC_VAL", 5301 "CDR_INTEG_REG", 5302 "CDR_INTEG_REG_CLR", 5303 "CDR_INTEG_SAT_SEL", 5304 "CDR_LM_OUTOFLOCK", 5305 "CDR_LM_THR_SEL", 5306 "CDR_PHASE_ERR", 5307 "CDR_PHASE_ERR_FRZ", 5308 "CDR_PHASE_SAT_CTRL", 5309 "CDR_QPHASE_MULT_EN", 5310 "CDR_SETTLE_TIMEOUT", 5311 "CDR_ZERO_POLARITY", 5312 "CHK_END_EN", 5313 "CHK_END_EN_OEN", 5314 "CL36BYTEDELETEMODE", 5315 "CL36BYTEDELETEMODE_OEN", 5316 "CL36_BER_EN", 5317 "CL36_EN", 5318 "CL36_EN_OEN", 5319 "CL36_FORCE_COMMA_ALIGN_ENABLE", 5320 "CL36_SYNCACQ_HIS_STATE_PER_LN", 5321 "CL36_SYNCACQ_STATE_CODED_PER_LN", 5322 "CL37_ACK_TIMER_PERIOD", 5323 "CL37_AN_RESTART", 5324 "CL37_AN_RESTART_RESET_DISABLE", 5325 "CL37_BAM_CODE", 5326 "CL37_BAM_ENABLE", 5327 "CL37_BAM_TO_SGMII_AUTO_ENABLE", 5328 "CL37_ENABLE", 5329 "CL37_ERROR_TIMER_PERIOD", 5330 "CL37_FULL_DUPLEX", 5331 "CL37_HALF_DUPLEX", 5332 "CL37_HIGH_VCO", 5333 "CL37_NEXT_PAGE", 5334 "CL37_PAUSE", 5335 "CL37_RESTART_TIMER_PERIOD", 5336 "CL37_SGMII_ENABLE", 5337 "CL37_SW_RESTART_RESET_DISABLE", 5338 "CL37_SYNC_STATUS_FILTER_TIMER_PERIOD", 5339 "CL48_CGBAD_EN", 5340 "CL48_DSWIN64B66B", 5341 "CL48_DSWIN8B10B", 5342 "CL48_RX_LF_ENABLE", 5343 "CL48_RX_LI_ENABLE", 5344 "CL48_RX_QRSVDCTRL", 5345 "CL48_RX_RF_ENABLE", 5346 "CL48_SKEWACQ_STATE_D_0", 5347 "CL48_SKEWACQ_STATE_D_1", 5348 "CL48_SKEWACQ_STATE_D_2", 5349 "CL48_SKEWACQ_STATE_D_3", 5350 "CL48_SKEWACQ_STATE_L", 5351 "CL48_SKEW_STATUS", 5352 "CL48_SYNCACQ_EN", 5353 "CL48_SYNCACQ_STATE_D_0", 5354 "CL48_SYNCACQ_STATE_D_1", 5355 "CL48_SYNCACQ_STATE_D_2", 5356 "CL48_SYNCACQ_STATE_D_3", 5357 "CL48_SYNCACQ_STATE_L", 5358 "CL48_TX_LF_ENABLE", 5359 "CL48_TX_LI_ENABLE", 5360 "CL48_TX_QRSVDCTRL", 5361 "CL48_TX_RF_ENABLE", 5362 "CL49IEEE_ERRORED_BLOCKS", 5363 "CL49_BERMON_CURRENT_STATE", 5364 "CL49_BERMON_HISTORY_STATE", 5365 "CL49_BER_LIMIT", 5366 "CL49_BYPASS_TXSM", 5367 "CL49_INVALID_SH_CNT", 5368 "CL49_LOW_LATENCY_EN", 5369 "CL49_LTXSM_STATE", 5370 "CL49_RXSM_CURRENT_STATE", 5371 "CL49_RXSM_HISTORY_STATE", 5372 "CL49_RX_LF_ENABLE", 5373 "CL49_RX_LI_ENABLE", 5374 "CL49_RX_RF_ENABLE", 5375 "CL49_R_TYPE_CODED", 5376 "CL49_TXSM_STATE", 5377 "CL49_TX_FAULT_DET", 5378 "CL49_TX_LF_ENABLE", 5379 "CL49_TX_LI_ENABLE", 5380 "CL49_TX_RF_ENABLE", 5381 "CL49_TX_TL_MODE", 5382 "CL49_T_TYPE_CODED", 5383 "CL49_VALID_SH_CNT", 5384 "CL72", 5385 "CL72_BAD_MARKER_CNT", 5386 "CL72_BRK_RING_OSC", 5387 "CL72_CTRL_FRAME_DLY", 5388 "CL72_DIS_LP_COEFF_UPDATES_TO_LD", 5389 "CL72_DIS_MAX_WAIT_TIMER", 5390 "CL72_DME_CELL_BOUNDARY_CHK", 5391 "CL72_DOUBLE_CMD_EN", 5392 "CL72_ENABLE", 5393 "CL72_EN_MASK", 5394 "CL72_EN_OEN", 5395 "CL72_FRAME_LOCK_LH", 5396 "CL72_FRAME_LOCK_RDY_FOR_CMD_EN", 5397 "CL72_GOOD_MARKER_CNT", 5398 "CL72_IEEE_FRAME_LOCK", 5399 "CL72_IEEE_LD_COEFF_UPDATE", 5400 "CL72_IEEE_LD_STATUS_REPORT", 5401 "CL72_IEEE_LP_COEFF_UPDATE", 5402 "CL72_IEEE_LP_STATUS_REPORT", 5403 "CL72_IEEE_RECEIVER_STATUS", 5404 "CL72_IEEE_RESTART_TRAINING", 5405 "CL72_IEEE_TRAINING_ENABLE", 5406 "CL72_IEEE_TRAINING_FAILURE", 5407 "CL72_IEEE_TRAINING_STATUS", 5408 "CL72_INC_DEC_VAL_SEL", 5409 "CL72_LD_COEFF_CMD_HIST", 5410 "CL72_LD_STATUS_PAGE", 5411 "CL72_LD_XMT_STATUS_LOAD", 5412 "CL72_LD_XMT_STATUS_OVERRIDE", 5413 "CL72_LP_CONTROL_PAGE", 5414 "CL72_OVERRIDE_LD_STATUS_PAGE", 5415 "CL72_PPM_OFFSET_EN", 5416 "CL72_RCVD_STATUS_PAGE", 5417 "CL72_READY_FOR_CMD", 5418 "CL72_RX_DP_LN_CLK_EN", 5419 "CL72_RX_TRAINED", 5420 "CL72_SIGNAL_DETECT", 5421 "CL72_SIGNAL_DET_FRC", 5422 "CL72_STRICT_DME_CHK", 5423 "CL72_STRICT_MARKER_CHK", 5424 "CL72_TAP_V2_VAL", 5425 "CL72_TIMER_EN", 5426 "CL72_TR_COARSE_LOCK", 5427 "CL72_TX_DP_LN_CLK_EN", 5428 "CL72_TX_FIR_TAP_MAIN_KR_INIT_VAL", 5429 "CL72_TX_FIR_TAP_POST_KR_INIT_VAL", 5430 "CL72_TX_FIR_TAP_PRE_KR_INIT_VAL", 5431 "CL72_V2_CONSTRAINT_DIS", 5432 "CL72_XMT_UPDATE_PAGE", 5433 "CL73_AN_RESTART", 5434 "CL73_BAM_CODE", 5435 "CL73_BAM_ENABLE", 5436 "CL73_BAM_TO_HPAM_AUTO_ENABLE", 5437 "CL73_ENABLE", 5438 "CL73_ERROR_TIMER_PERIOD", 5439 "CL73_HPAM_ENABLE", 5440 "CL73_LINK_UP_TIMER_PERIOD", 5441 "CL73_LOW_VCO", 5442 "CL73_NONCE_MATCH_OVER", 5443 "CL73_NONCE_MATCH_VAL", 5444 "CL73_PAGE_TEST_MAX_TIMER", 5445 "CL73_PAGE_TEST_MIN_TIMER", 5446 "CL73_PAUSE", 5447 "CL73_REMOTE_FAULT", 5448 "CL82_BER_LIMIT", 5449 "CL82_BYPASS_TXSM", 5450 "CL82_DSWIN", 5451 "CL82_DSWIN_100G", 5452 "CL82_IDLE_DELETION_UNDERFLOW", 5453 "CL82_INVALID_SH_CNT", 5454 "CL82_MLD_PHYS_MAP", 5455 "CL82_MULTI_PIPE_MODE", 5456 "CL82_RX_LF_ENABLE", 5457 "CL82_RX_LI_ENABLE", 5458 "CL82_RX_RF_ENABLE", 5459 "CL82_TX_LF_ENABLE", 5460 "CL82_TX_LI_ENABLE", 5461 "CL82_TX_RF_ENABLE", 5462 "CL82_VALID_SH_CNT", 5463 "CLAUSE22", 5464 "CLOCKCNT0", 5465 "CLOCKCNT0_OEN", 5466 "CLOCKCNT1", 5467 "CLOCKCNT1_OEN", 5468 "CLR_CRCCNT", 5469 "CNT_BIN_D_DREG", 5470 "CNT_BIN_D_MREG", 5471 "CNT_BIN_M1_MREG", 5472 "CNT_BIN_M1_PREG", 5473 "CNT_BIN_P1_DREG", 5474 "CNT_BIN_P1_PREG", 5475 "CNT_D_MINUS_M1", 5476 "CNT_D_MINUS_P1", 5477 "CORCOUNTH", 5478 "CORCOUNTL", 5479 "CORE_DP_H_RSTB", 5480 "CORE_DP_H_RSTB_OEN", 5481 "CORE_DP_RESET_STATE", 5482 "CORE_DP_S_RSTB", 5483 "CORE_MODE", 5484 "CORE_MODE_OEN", 5485 "CORE_MULTICAST_MASK_CONTROL", 5486 "CORE_REG_RESET_OCCURRED", 5487 "CORE_S_RSTB", 5488 "CRCERRCNT", 5489 "CREDITENABLE", 5490 "CREDITENABLE_OEN", 5491 "CREDIT_EN", 5492 "DBG_CAP_STATE_ONE_HOT", 5493 "DBG_ENABLE", 5494 "DBG_ERRH", 5495 "DBG_ERRL", 5496 "DBG_ERR_MODE", 5497 "DBG_FDBCK", 5498 "DBG_MASK_DIG_LPBK_EN", 5499 "DBG_PLL_STATE_ONE_HOT", 5500 "DBG_SLOWDN", 5501 "DBG_SLOWDN_CHANGE", 5502 "DC_OFFSET", 5503 "DECODERMODE", 5504 "DECODERMODE_OEN", 5505 "DEC_17B_BURST_GAP_COUNT", 5506 "DEC_18B_BURST_GAP_COUNT", 5507 "DEC_19B_BURST_GAP_COUNT", 5508 "DEC_GAP_COUNT_MODE", 5509 "DEC_MAX_PM", 5510 "DEC_PM_MODE", 5511 "DESC2_MODE", 5512 "DESC2_MODE_OEN", 5513 "DESCRAMBLERMODE", 5514 "DESCRAMBLERMODE_OEN", 5515 "DESKEWMODE", 5516 "DESKEWMODE_OEN", 5517 "DESKEW_1BIT_ERROR", 5518 "DESKEW_2BIT_ERROR", 5519 "DESKEW_ADDRESS", 5520 "DESKEW_DISABLE_ECC", 5521 "DESKEW_ECC_CORRUPT", 5522 "DESKEW_HIS_STATE", 5523 "DESKEW_STATE", 5524 "DESKEW_STATUS", 5525 "DESKEW_STATUS_LH", 5526 "DESKEW_STATUS_LL", 5527 "DESKEW_TM", 5528 "DFE_1_ACC_CLR", 5529 "DFE_1_CMN", 5530 "DFE_1_CMN_ONLY", 5531 "DFE_1_E", 5532 "DFE_1_EN", 5533 "DFE_1_ERR_GAIN", 5534 "DFE_1_ERR_SEL", 5535 "DFE_1_GRADIENT_INVERT", 5536 "DFE_1_INV_M1", 5537 "DFE_1_INV_P1", 5538 "DFE_1_O", 5539 "DFE_1_PATTERN", 5540 "DFE_1_PATTERN_BIT_EN", 5541 "DFE_1_WANTS_NEGATIVE", 5542 "DFE_2_ACC_CLR", 5543 "DFE_2_CMN", 5544 "DFE_2_CMN_ONLY", 5545 "DFE_2_E", 5546 "DFE_2_EN", 5547 "DFE_2_ERR_GAIN", 5548 "DFE_2_ERR_SEL", 5549 "DFE_2_GRADIENT_INVERT", 5550 "DFE_2_INV_M1", 5551 "DFE_2_INV_P1", 5552 "DFE_2_O", 5553 "DFE_2_PATTERN", 5554 "DFE_2_PATTERN_BIT_EN", 5555 "DFE_2_SE", 5556 "DFE_2_SO", 5557 "DFE_3_ACC_CLR", 5558 "DFE_3_CMN", 5559 "DFE_3_EN", 5560 "DFE_3_ERR_GAIN", 5561 "DFE_3_ERR_SEL", 5562 "DFE_3_GRADIENT_INVERT", 5563 "DFE_3_INV_M1", 5564 "DFE_3_INV_P1", 5565 "DFE_3_PATTERN", 5566 "DFE_3_PATTERN_BIT_EN", 5567 "DFE_4_ACC_CLR", 5568 "DFE_4_CMN", 5569 "DFE_4_EN", 5570 "DFE_4_ERR_GAIN", 5571 "DFE_4_ERR_SEL", 5572 "DFE_4_GRADIENT_INVERT", 5573 "DFE_4_INV_M1", 5574 "DFE_4_INV_P1", 5575 "DFE_4_PATTERN", 5576 "DFE_4_PATTERN_BIT_EN", 5577 "DFE_5_ACC_CLR", 5578 "DFE_5_CMN", 5579 "DFE_5_EN", 5580 "DFE_5_ERR_GAIN", 5581 "DFE_5_ERR_SEL", 5582 "DFE_5_GRADIENT_INVERT", 5583 "DFE_5_INV_M1", 5584 "DFE_5_INV_P1", 5585 "DFE_5_PATTERN", 5586 "DFE_5_PATTERN_BIT_EN", 5587 "DFE_ACC_HYS_EN", 5588 "DFE_ALLOW_SIMULT", 5589 "DFE_OFFSET_ADJ_DATA_EVEN", 5590 "DFE_OFFSET_ADJ_DATA_ODD", 5591 "DFE_OFFSET_ADJ_M1_EVEN", 5592 "DFE_OFFSET_ADJ_M1_ODD", 5593 "DFE_OFFSET_ADJ_P1_EVEN", 5594 "DFE_OFFSET_ADJ_P1_ODD", 5595 "DFE_UPDATE_GAIN", 5596 "DFE_VGA_WRITE_EN", 5597 "DFE_VGA_WRITE_TAPSEL", 5598 "DFE_VGA_WRITE_VAL", 5599 "DIG_LPBK_EN", 5600 "DIG_LPBK_PD_EARLY_IND", 5601 "DIG_LPBK_PD_FLT_BYPASS", 5602 "DIG_LPBK_PD_LATE_IND", 5603 "DIG_LPBK_PD_MODE", 5604 "DISABLE_CARRIER_EXTEND", 5605 "DISABLE_CL49_BERMON", 5606 "DISABLE_REMOTE_FAULT_REPORTING", 5607 "DIS_CL82_BERMON", 5608 "DP_RESET_TX_DISABLE_DIS", 5609 "DSC_CLR_FRC", 5610 "DSC_CLR_FRC_VAL", 5611 "DSC_SM_GP_UC_REQ", 5612 "DSC_SM_READY_FOR_CMD", 5613 "DSC_SM_SCRATCH", 5614 "DSC_STATE", 5615 "DSC_STATE_EEE_ONE_HOT", 5616 "DSC_STATE_ONE_HOT", 5617 "DTE_XS", 5618 "EEE_ACQ_CDR_TIMEOUT", 5619 "EEE_ANA_PWR_TIMEOUT", 5620 "EEE_CDR_SETTLE_TIMEOUT", 5621 "EEE_HW_TUNE_TIMEOUT", 5622 "EEE_LFSR_CNT", 5623 "EEE_MEASURE_CNT", 5624 "EEE_MEASURE_EN", 5625 "EEE_MODE_EN", 5626 "EEE_PHASE_ERR_OFFSET", 5627 "EEE_PHASE_ERR_OFFSET_EN", 5628 "EEE_QUIET_FROM_EEE_STATES", 5629 "EEE_QUIET_RX_AFE_PWRDWN_VAL", 5630 "ENABLE_TX_LANE", 5631 "ENCODEMODE", 5632 "ENCODEMODE_OEN", 5633 "ENERGY_DETECT", 5634 "ENERGY_DETECT_CHANGE", 5635 "ENERGY_DETECT_FRC", 5636 "ENERGY_DETECT_FRC_VAL", 5637 "ENERGY_DETECT_MASK_COUNT", 5638 "EN_DFE_CLK", 5639 "EN_HGAIN", 5640 "ERRGEN_EN", 5641 "ERRORED_BLOCKS_HO", 5642 "ERRORED_BLOCKS_HO_PRESENT", 5643 "ERROR_EN_OVR", 5644 "ERROR_EN_OVR_VAL", 5645 "ERROR_MASK_15_0", 5646 "ERROR_MASK_31_16", 5647 "ERROR_MASK_47_32", 5648 "ERROR_MASK_63_48", 5649 "ERROR_MASK_79_64", 5650 "EXT_LOS_EN", 5651 "EXT_LOS_INV", 5652 "FAST_LOCK_EN", 5653 "FAST_SEARCH_MODE", 5654 "FEC", 5655 "FEC_ENABLE", 5656 "FEC_ENABLE_OEN", 5657 "FEC_ERROR_CODE_ALL", 5658 "FEC_ERR_ENABLE", 5659 "FREQ_DET_RESTART_EN", 5660 "FREQ_DET_RETRY_EN", 5661 "FREQ_DONE_SM", 5662 "FREQ_DONE_SM_LH_LL", 5663 "FREQ_MONITOR_EN", 5664 "FREQ_PASS_SM", 5665 "FREQ_PASS_SM_LH_LL", 5666 "FREQ_UPD_EN_FRC", 5667 "FREQ_UPD_EN_FRC_VAL", 5668 "GBOX_OVERFLOW_ERR", 5669 "GBOX_UNDERFLOW_ERR", 5670 "GCWCOUNT", 5671 "GOOD_PARITY_CNT", 5672 "HEARTBEAT_COUNT_1US", 5673 "HG2", 5674 "HG2_CODEC", 5675 "HG2_ENABLE", 5676 "HG2_MESSAGE_INVALID_CODE_ENABLE", 5677 "HI_BER", 5678 "HI_BER_LH", 5679 "HI_BER_LL", 5680 "HOLD_LOS_COUNT", 5681 "HOLD_SD_COUNT", 5682 "HPAM_20GKR2", 5683 "HPAM_TO_CL73_AUTO_ENABLE", 5684 "HW_TUNE_EN", 5685 "HW_TUNE_TIMEOUT", 5686 "HYSTCOUNT", 5687 "IGNORE_LINK_TIMER_PERIOD", 5688 "IGNORE_LP_MODE", 5689 "IGNORE_RX_MODE", 5690 "ILKN_SEL", 5691 "INT_1B", 5692 "INT_2B", 5693 "INVALID_PARITY_CNT", 5694 "INV_RX_ORDER", 5695 "INV_TX_ORDER", 5696 "IPG_SIZE", 5697 "KCODE66ERRCOUNT", 5698 "LANE_0_AM_1_0", 5699 "LANE_0_AM_2", 5700 "LANE_1_AM_1_0", 5701 "LANE_1_AM_2", 5702 "LANE_2_AM_1_0", 5703 "LANE_2_AM_2", 5704 "LANE_3_AM_1_0", 5705 "LANE_3_AM_2", 5706 "LANE_ADDR_0", 5707 "LANE_ADDR_1", 5708 "LANE_ADDR_2", 5709 "LANE_ADDR_3", 5710 "LANE_DP_RESET_STATE", 5711 "LANE_MODE", 5712 "LANE_MODE_OEN", 5713 "LANE_MULTICAST_MASK_CONTROL", 5714 "LANE_REG_RESET_OCCURRED", 5715 "LANE_RESET_RELEASED", 5716 "LANE_RESET_RELEASED_INDEX", 5717 "LATCH_LINKDOWN_ENABLE", 5718 "LBERMON_STATE", 5719 "LD_CONTROL_VALID", 5720 "LD_PAGE_0_PAGE_DATA", 5721 "LD_PAGE_1_PAGE_DATA", 5722 "LD_PAGE_2_PAGE_DATA", 5723 "LINKFAILTIMERQUAL_EN", 5724 "LINKFAILTIMER_DIS", 5725 "LINK_CONTROL_FORCEVAL", 5726 "LINK_EN", 5727 "LINK_FAIL_INHIBIT_TIMER_CL72_PERIOD", 5728 "LINK_FAIL_INHIBIT_TIMER_NCL72_PERIOD", 5729 "LINK_INTERRUPT", 5730 "LINK_INTERRUPT_LH", 5731 "LINK_STATUS", 5732 "LINK_STATUS_LH", 5733 "LINK_STATUS_LL", 5734 "LN_DP_H_RSTB", 5735 "LN_DP_H_RSTB_OEN", 5736 "LN_DP_S_RSTB", 5737 "LN_H_RSTB", 5738 "LN_RX_DP_S_RSTB", 5739 "LN_RX_H_PWRDN", 5740 "LN_RX_S_CLKGATE_FRC_ON", 5741 "LN_RX_S_COMCLK_FRC_ON", 5742 "LN_RX_S_COMCLK_SEL", 5743 "LN_RX_S_PWRDN", 5744 "LN_RX_S_RSTB", 5745 "LN_S_RSTB", 5746 "LN_TX_DP_S_RSTB", 5747 "LN_TX_H_PWRDN", 5748 "LN_TX_S_PWRDN", 5749 "LN_TX_S_RSTB", 5750 "LOCAL_FAULT", 5751 "LOCAL_FAULT_LH", 5752 "LOCAL_PCS_LOOPBACK_ENABLE", 5753 "LOG0_TO_PHY_LNSWAP_SEL", 5754 "LOG1_TO_PHY_LNSWAP_SEL", 5755 "LOG2_TO_PHY_LNSWAP_SEL", 5756 "LOG3_TO_PHY_LNSWAP_SEL", 5757 "LOOPCNT0", 5758 "LOOPCNT0_OEN", 5759 "LOOPCNT1", 5760 "LOOPCNT1_OEN", 5761 "LOST_PLL_LOCK_SM", 5762 "LOS_FILTER_COUNT", 5763 "LOS_THRESH", 5764 "LPI_EN", 5765 "LPI_ENABLE", 5766 "LPI_RECEIVED", 5767 "LPI_RECEIVED_LH", 5768 "LP_BASE_PAGE1_PAGE_DATA", 5769 "LP_BASE_PAGE2_PAGE_DATA", 5770 "LP_BASE_PAGE3_PAGE_DATA", 5771 "LP_MP1024_UP1_PAGE_DATA", 5772 "LP_MP1024_UP2_PAGE_DATA", 5773 "LP_MP1024_UP3_PAGE_DATA", 5774 "LP_MP1024_UP4_PAGE_DATA", 5775 "LP_MP5_UP1_PAGE_DATA", 5776 "LP_MP5_UP2_PAGE_DATA", 5777 "LP_MP5_UP3_PAGE_DATA", 5778 "LP_MP5_UP4_PAGE_DATA", 5779 "LP_PAGE_0_PAGE_DATA", 5780 "LP_PAGE_1_PAGE_DATA", 5781 "LP_PAGE_2_PAGE_DATA", 5782 "LP_STATUS_VALID", 5783 "LSM_CURR_STATE", 5784 "LSM_HIS_STATE", 5785 "LTXSM_STATE", 5786 "M1_THRESH_SEL", 5787 "M1_THRESH_ZERO", 5788 "MAC_CREDITGENCNT", 5789 "MAC_CREDITGENCNT_OEN", 5790 "MAIN_TAP_LIMIT", 5791 "MAIN_TAP_MIN_VAL", 5792 "MASTER_PORT_NUM", 5793 "MAX_WAIT_TIMER_PERIOD", 5794 "MDIO_ADDR_DATA", 5795 "MDIO_AER", 5796 "MDIO_BLK_ADDR", 5797 "MDIO_BRCST_PORT_ADDR", 5798 "MDIO_DEVAD", 5799 "MDIO_DEV_AN_EN", 5800 "MDIO_DEV_CL22_EN", 5801 "MDIO_DEV_DTE_EN", 5802 "MDIO_DEV_PCS_EN", 5803 "MDIO_DEV_PHY_EN", 5804 "MDIO_DEV_PMD_EN", 5805 "MDIO_FUNCTION", 5806 "MDIO_MASKDATA", 5807 "MDIO_MULTI_MMDS_EN", 5808 "MDIO_MULTI_PRTS_EN", 5809 "MEASURE_LFSR_CNT", 5810 "MEASURE_TIMEOUT", 5811 "MEAS_INCOMPLETE", 5812 "MICRO_BYTE_MODE", 5813 "MICRO_DATARAM_TM", 5814 "MICRO_DISABLE_ECC", 5815 "MICRO_ERR0", 5816 "MICRO_ERR1", 5817 "MICRO_FSM", 5818 "MICRO_GEN_STATUS_SEL", 5819 "MICRO_INIT_CMD", 5820 "MICRO_INIT_DONE", 5821 "MICRO_INRUSH_CURRENT_FRC", 5822 "MICRO_INRUSH_CURRENT_FRC_VAL", 5823 "MICRO_IRAM_TM", 5824 "MICRO_MDIO_AUTOWAKEUP", 5825 "MICRO_MDIO_DW8051_RESET_N", 5826 "MICRO_MDIO_PROG_RAM_CS_FRC", 5827 "MICRO_MDIO_PROG_RAM_CS_FRC_VAL", 5828 "MICRO_MDIO_RAM_ACCESS_MODE", 5829 "MICRO_MDIO_RAM_READ_AUTOINC_EN", 5830 "MICRO_MDIO_UC_MAILBOX_LSW", 5831 "MICRO_MDIO_UC_MAILBOX_MSW", 5832 "MICRO_PMI_ACK_TIMEOUT_VAL", 5833 "MICRO_PMI_HP_ACK_FRC", 5834 "MICRO_PMI_HP_ACK_FRC_VAL", 5835 "MICRO_PRAM_IF_EN", 5836 "MICRO_PRAM_IF_FLOP_BYPASS", 5837 "MICRO_PRAM_IF_RSTB", 5838 "MICRO_PROGRAM_RAM_TM", 5839 "MICRO_RAM_ADDRESS", 5840 "MICRO_RAM_CLK_INVERT", 5841 "MICRO_RAM_COUNT", 5842 "MICRO_RAM_RDDATA", 5843 "MICRO_RAM_WRDATA", 5844 "MICRO_READ", 5845 "MICRO_RUN", 5846 "MICRO_SRST_DW8051_TO_PMI", 5847 "MICRO_SRST_MDIO_DATARAM_ACCESS", 5848 "MICRO_SRST_MDIO_LOAD_PROGRAM_RAM", 5849 "MICRO_SRST_MDIO_PROGRAM_ACCESS", 5850 "MICRO_STATUS_MUXED", 5851 "MICRO_STOP", 5852 "MICRO_SYSTEM_CLK_EN", 5853 "MICRO_SYSTEM_RESET_N", 5854 "MICRO_TEMPATURE_DATA", 5855 "MICRO_TX_DISABLE", 5856 "MICRO_UC_MDIO_MAILBOX_LSW", 5857 "MICRO_UC_MDIO_MAILBOX_MSW", 5858 "MICRO_WRITE", 5859 "MICRO_ZERO_ROM_DATAOUT", 5860 "MLD_SWAP_COUNT", 5861 "MODEL_NUMBER", 5862 "MSK_1B", 5863 "MSK_2B", 5864 "MULTIPRTS_EN", 5865 "NEXT_PAGE", 5866 "NUMBER_PKT", 5867 "NUM_ADVERTISED_LANES", 5868 "NUM_LANES", 5869 "NUM_LANES_OEN", 5870 "NUM_LANES_OVERRIDE_VALUE", 5871 "OFFSET_FASTACQ", 5872 "OFFSET_PD", 5873 "OSR_MODE", 5874 "OSR_MODE_FRC", 5875 "OSR_MODE_FRC_VAL", 5876 "OSR_MODE_OEN", 5877 "OSR_MODE_PIN", 5878 "OSX2P_PHERR_GAIN", 5879 "OS_MODE", 5880 "OS_MODE_OEN", 5881 "OUI_CONTROL", 5882 "OUI_LOWER_DATA", 5883 "OUI_UPPER_DATA", 5884 "OVER1G_ABILITY", 5885 "OVER1G_PAGE_COUNT", 5886 "P1_EYEDIAG_BIN", 5887 "P1_EYEDIAG_EN", 5888 "P1_OFFSET", 5889 "P1_OFFSET_EN", 5890 "P1_OFF_3LEVELQ_EN", 5891 "P1_THRESH_SEL", 5892 "PATTERN_SEL", 5893 "PATT_GEN_EN", 5894 "PATT_GEN_SEQ_0", 5895 "PATT_GEN_SEQ_1", 5896 "PATT_GEN_SEQ_10", 5897 "PATT_GEN_SEQ_11", 5898 "PATT_GEN_SEQ_12", 5899 "PATT_GEN_SEQ_13", 5900 "PATT_GEN_SEQ_14", 5901 "PATT_GEN_SEQ_2", 5902 "PATT_GEN_SEQ_3", 5903 "PATT_GEN_SEQ_4", 5904 "PATT_GEN_SEQ_5", 5905 "PATT_GEN_SEQ_6", 5906 "PATT_GEN_SEQ_7", 5907 "PATT_GEN_SEQ_8", 5908 "PATT_GEN_SEQ_9", 5909 "PATT_GEN_START_POS", 5910 "PATT_GEN_STOP_POS", 5911 "PAYLOAD_TYPE", 5912 "PCS_CLOCKCNT0", 5913 "PCS_CLOCKCNT0_OEN", 5914 "PCS_CREDITENABLE", 5915 "PCS_CREDITENABLE_OEN", 5916 "PCS_CREDITGENCNT", 5917 "PCS_CREDITGENCNT_OEN", 5918 "PCS_XS", 5919 "PD_CH_P1", 5920 "PD_CL37_COMPLETED", 5921 "PD_COMPLETED", 5922 "PD_DME_LOCK_TIMER_PERIOD", 5923 "PD_HCD_KX4_OR_KX", 5924 "PD_IN_PROGRESS", 5925 "PD_KX4_EN", 5926 "PD_KX_EN", 5927 "PD_SD_TIMER_PERIOD", 5928 "PD_TO_CL37_LINK_WAIT_TIMER", 5929 "PF2_LOWP_CTRL", 5930 "PF_CTRL", 5931 "PF_HIZ", 5932 "PHASE_ERR_OFFSET", 5933 "PHASE_ERR_OFFSET_EN", 5934 "PHASE_ERR_OFFSET_MULT_2", 5935 "PHY_XS", 5936 "PIPELINE_RESET_COUNT", 5937 "PKTGEN_EN", 5938 "PKT_OR_PRTP", 5939 "PKT_SIZE", 5940 "PLL_FORCE_CAP_DONE", 5941 "PLL_FORCE_CAP_DONE_EN", 5942 "PLL_FORCE_CAP_PASS", 5943 "PLL_FORCE_CAP_PASS_EN", 5944 "PLL_FORCE_FDONE", 5945 "PLL_FORCE_FDONE_EN", 5946 "PLL_FORCE_FPASS", 5947 "PLL_LOCK", 5948 "PLL_LOCK_FRC", 5949 "PLL_LOCK_FRC_VAL", 5950 "PLL_LOCK_LH", 5951 "PLL_LOCK_LH_LL", 5952 "PLL_LOCK_LL", 5953 "PLL_LOCK_OVRD", 5954 "PLL_LOCK_STS", 5955 "PLL_LOCK_TIMED_OUT", 5956 "PLL_LOCK_TIMER_PERIOD", 5957 "PLL_MODE", 5958 "PLL_RESET_EN", 5959 "PLL_SEQ_DONE", 5960 "PLL_SEQ_DONE_LH_LL", 5961 "PLL_SEQ_PASS", 5962 "PLL_SEQ_PASS_LH_LL", 5963 "PLL_SEQ_START", 5964 "PMA_PMD", 5965 "PMD_CORE_DP_H_RSTB_PKILL", 5966 "PMD_CORE_MODE", 5967 "PMD_LANE_MODE", 5968 "PMD_LN_DP_H_RSTB_PKILL", 5969 "PMD_LN_H_RSTB_PKILL", 5970 "PMD_LN_RX_H_PWRDN_PKILL", 5971 "PMD_LN_TX_H_PWRDN_PKILL", 5972 "PMD_LOCK_TIMED_OUT", 5973 "PMD_LOCK_TIMER_PERIOD", 5974 "PMD_MDIO_TRANS_PKILL", 5975 "PMD_RX_CLK_VLD_FRC", 5976 "PMD_RX_CLK_VLD_FRC_VAL", 5977 "PMD_RX_LOCK", 5978 "PMD_RX_LOCK_CHANGE", 5979 "PMD_TX_CLK_VLD_FRC", 5980 "PMD_TX_CLK_VLD_FRC_VAL", 5981 "PMD_TX_DISABLE_PIN_DIS", 5982 "PORT_MODE_SEL", 5983 "POR_H_RSTB", 5984 "POST_TAP_LIMIT", 5985 "POST_TAP_PRESET_VAL", 5986 "PRAM_ABILITY", 5987 "PRBS_CHK_CLK_EN_FRC_ON", 5988 "PRBS_CHK_EN", 5989 "PRBS_CHK_EN_AUTO_MODE", 5990 "PRBS_CHK_EN_TIMEOUT", 5991 "PRBS_CHK_EN_TIMER_MODE", 5992 "PRBS_CHK_ERR_CNT_BURST_MODE", 5993 "PRBS_CHK_ERR_CNT_LSB", 5994 "PRBS_CHK_ERR_CNT_MSB", 5995 "PRBS_CHK_INV", 5996 "PRBS_CHK_LOCK", 5997 "PRBS_CHK_LOCK_CNT", 5998 "PRBS_CHK_LOCK_LOST_LH", 5999 "PRBS_CHK_MODE", 6000 "PRBS_CHK_MODE_SEL", 6001 "PRBS_CHK_OOL_CNT", 6002 "PRBS_GEN_EN", 6003 "PRBS_GEN_ERR_INS", 6004 "PRBS_GEN_INV", 6005 "PRBS_GEN_MODE_SEL", 6006 "PRE_FREQ_DET_TIME", 6007 "PRE_TAP_LIMIT", 6008 "PRE_TAP_PRESET_VAL", 6009 "PROG_TL_CHAR", 6010 "PROG_TL_EN", 6011 "PRTAD_BCST", 6012 "PRTP_DATA_PATTERN_SEL", 6013 "PRTP_ERR_COUNT", 6014 "PRTP_LOCK", 6015 "PWRDN_SEQ_TIMER", 6016 "QRSVD1", 6017 "QRSVD2_1_0", 6018 "QRSVD2_8_2", 6019 "QRSVD3", 6020 "QRSVDSWAP", 6021 "REFCLK_DIVCNT", 6022 "REFCLK_DIVCNT_SEL", 6023 "REFCLK_SEL", 6024 "REGID1", 6025 "REGID2", 6026 "REMOTE_FAULT", 6027 "REMOTE_FAULT_IN_BASE_PAGE", 6028 "REMOTE_FAULT_LH", 6029 "REMOTE_PCS_LOOPBACK_ENABLE", 6030 "REMOTE_PMD_LOOPBACK_ENABLE", 6031 "REORDER_EN", 6032 "REORDER_EN_OEN", 6033 "REPLICATION_CNT", 6034 "REPLICATION_CNT_OEN", 6035 "RESCAL_FRC", 6036 "RESCAL_FRC_VAL", 6037 "RESCAL_IN", 6038 "RESERVED_ORDERED_BYTE_3", 6039 "RESERVED_ORDERED_SET_LH", 6040 "RESOLVED_PORT_MODE", 6041 "RESTART_PI_EXT_MODE", 6042 "RESTART_PMD_RESTART", 6043 "RESTART_SIGDET", 6044 "RES_CAL_CNTR", 6045 "RETRY_TIME", 6046 "REVID2", 6047 "REVID_BONDING", 6048 "REVID_CL72", 6049 "REVID_EEE", 6050 "REVID_LLP", 6051 "REVID_MDIO", 6052 "REVID_MICRO", 6053 "REVID_MODEL", 6054 "REVID_MULTIPLICITY", 6055 "REVID_PIR", 6056 "REVID_PROCESS", 6057 "REVID_REV_LETTER", 6058 "REVID_REV_NUMBER", 6059 "REV_LETTER", 6060 "REV_NUMBER", 6061 "RFEC0_1BIT_ERROR", 6062 "RFEC0_2BIT_ERROR", 6063 "RFEC0_ADDRESS", 6064 "RFEC0_DISABLE_ECC", 6065 "RFEC0_ECC_CORRUPT", 6066 "RFEC0_TM", 6067 "RFEC1_1BIT_ERROR", 6068 "RFEC1_2BIT_ERROR", 6069 "RFEC1_ADDRESS", 6070 "RFEC1_DISABLE_ECC", 6071 "RFEC1_ECC_CORRUPT", 6072 "RFEC1_TM", 6073 "RMLD_STATUS", 6074 "RMT_LPBK_EN", 6075 "RMT_LPBK_PD_EARLY_IND", 6076 "RMT_LPBK_PD_FRC_ON", 6077 "RMT_LPBK_PD_LATE_IND", 6078 "RMT_LPBK_PD_MODE", 6079 "RSTB_LANE", 6080 "RSTB_TX_LANE", 6081 "RST_SEQ_DIS_FLT_MODE", 6082 "RST_SEQ_TIMER", 6083 "RXFIFO_EMPTY", 6084 "RXFIFO_FULL", 6085 "RXFIFO_OVERRUN", 6086 "RXFIFO_UNDERRUN", 6087 "RXPKTCNT_L", 6088 "RXPKTCNT_U", 6089 "RXSM_STATE", 6090 "RX_AGGREGATOR_BYPASS_EN", 6091 "RX_CLK_VLD_LH", 6092 "RX_CLK_VLD_LL", 6093 "RX_CLK_VLD_OVRD", 6094 "RX_CLK_VLD_STS", 6095 "RX_DME_EN", 6096 "RX_DME_EN_OEN", 6097 "RX_DSC_LOCK", 6098 "RX_DSC_LOCK_FRC", 6099 "RX_DSC_LOCK_FRC_VAL", 6100 "RX_GBOX_AFRST_EN", 6101 "RX_LOCK_LH", 6102 "RX_LOCK_LL", 6103 "RX_LOCK_OVRD", 6104 "RX_LOCK_STS", 6105 "RX_MODE", 6106 "RX_MSBUS_TYPE", 6107 "RX_PI_MANUAL_MODE", 6108 "RX_PI_MANUAL_RESET", 6109 "RX_PI_MANUAL_STROBE", 6110 "RX_PI_PHASE_STEP_CNT", 6111 "RX_PI_PHASE_STEP_DIR", 6112 "RX_PI_SLICERS_EN", 6113 "RX_PKT_CHECK_EN", 6114 "RX_PMD_DP_INVERT", 6115 "RX_PORT_SEL", 6116 "RX_PRTP_EN", 6117 "RX_RESTART_PMD", 6118 "RX_RESTART_PMD_HOLD", 6119 "R_TEST_MODE_CFG", 6120 "R_TYPE_CODED", 6121 "SCRAMBLER_EN_MASK", 6122 "SCR_MODE", 6123 "SCR_MODE_OEN", 6124 "SCW0", 6125 "SCW0_MASK", 6126 "SCW1", 6127 "SCW1_MASK", 6128 "SCW2", 6129 "SCW2_MASK", 6130 "SCW3", 6131 "SCW3_MASK", 6132 "SCW4", 6133 "SCW4_MASK", 6134 "SCWCOUNT", 6135 "SC_BYPASS", 6136 "SC_FSM_STATUS", 6137 "SC_IGNORE_TX_DATA_VLD", 6138 "SDK_TX_DISABLE", 6139 "SEEDA0", 6140 "SEEDA1", 6141 "SEEDA2", 6142 "SEEDA3", 6143 "SEEDB0", 6144 "SEEDB1", 6145 "SEEDB2", 6146 "SEEDB3", 6147 "SEND_LMS_TO_PCS", 6148 "SEQ_UNEXPECTED_PAGE", 6149 "SET_BER_WINDOW_512", 6150 "SET_MEAS_INCOMPLETE", 6151 "SGMII_FULL_DUPLEX", 6152 "SGMII_MASTER_MODE", 6153 "SGMII_SPD_SWITCH", 6154 "SGMII_SPD_SWITCH_OEN", 6155 "SGMII_SPEED", 6156 "SGMII_TIMER", 6157 "SGMII_TO_CL37_AUTO_ENABLE", 6158 "SHIFT_AMMOUNT", 6159 "SIGDET_DP_RSTB_EN", 6160 "SIGNAL_DETECT", 6161 "SIGNAL_DETECT_CHANGE", 6162 "SIGNAL_DETECT_FILTER_1US", 6163 "SIGNAL_DETECT_FILTER_COUNT", 6164 "SIGNAL_DETECT_FRC", 6165 "SIGNAL_DETECT_FRC_VAL", 6166 "SIGNAL_DETECT_LH", 6167 "SIGNAL_DETECT_LL", 6168 "SIGNAL_DETECT_OVRD", 6169 "SIGNAL_DETECT_RAW", 6170 "SIGNAL_DETECT_RAW_CHANGE", 6171 "SIGNAL_DETECT_STS", 6172 "SIGNAL_DETECT_THRESH", 6173 "SINGLE_PORT_MODE", 6174 "SKEW_STATUS", 6175 "SLOWDN_XOR", 6176 "SOFT_RST_RX", 6177 "SOFT_RST_TX", 6178 "SPARE0", 6179 "SPARE1", 6180 "SPEED", 6181 "STAND_ALONE_MODE", 6182 "STATUS_EN", 6183 "SUP_RST_SEQ_FRC", 6184 "SUP_RST_SEQ_FRC_VAL", 6185 "SW_AN", 6186 "SW_HCD", 6187 "SW_SPEED", 6188 "SW_SPEED_CHANGE", 6189 "SW_SPEED_CHANGE_DONE", 6190 "SW_SPEED_CONFIG_VLD", 6191 "SYNC66ERRCOUNT", 6192 "SYNCE_MODE_PHY_LN0", 6193 "SYNCE_MODE_PHY_LN1", 6194 "SYNCE_MODE_PHY_LN2", 6195 "SYNCE_MODE_PHY_LN3", 6196 "SYNC_STATUS", 6197 "SYNC_STATUS_LH", 6198 "SYNC_STATUS_LL", 6199 "TAP_SUM_MAX_VAL", 6200 "TC", 6201 "TDR_BIT_SEL", 6202 "TDR_CYCLE_BIN", 6203 "TDR_CYCLE_SEL", 6204 "TDR_TRNSUM_EN", 6205 "TECH_PROC", 6206 "TICK_DENOMINATOR", 6207 "TICK_NUMERATOR_LOWER", 6208 "TICK_NUMERATOR_UPPER", 6209 "TICK_OVERRIDE", 6210 "TIMER_DONE_FRC", 6211 "TIMER_DONE_FRC_VAL", 6212 "TLA_LN_SEQUENCER_FSM_STATUS", 6213 "TLA_LN_SEQUENCER_FSM_STATUS1", 6214 "TRANSMIT_NONCE", 6215 "TRNSUM_CLR_FRC", 6216 "TRNSUM_CLR_FRC_VAL", 6217 "TRNSUM_EN", 6218 "TRNSUM_ERROR_COUNT_EN", 6219 "TRNSUM_ERR_SEL", 6220 "TRNSUM_EYE_CLOSURE_EN", 6221 "TRNSUM_E_HIGH", 6222 "TRNSUM_E_LOW", 6223 "TRNSUM_FRZ_FRC", 6224 "TRNSUM_FRZ_FRC_VAL", 6225 "TRNSUM_GAIN", 6226 "TRNSUM_HIGH", 6227 "TRNSUM_INV_PATTERN_EN", 6228 "TRNSUM_LOW", 6229 "TRNSUM_O_HIGH", 6230 "TRNSUM_O_LOW", 6231 "TRNSUM_PATTERN", 6232 "TRNSUM_PATTERN_BIT_EN", 6233 "TRNSUM_PATTERN_FULL_CHECK_OFF", 6234 "TRNSUM_RANDOM_TAPSEL_DISABLE", 6235 "TRNSUM_TAP_EN", 6236 "TRNSUM_TAP_RANGE_SEL", 6237 "TRNSUM_TAP_SIGN", 6238 "TRNSUM_UNSIGNED_CORR", 6239 "TRNSUM_UNSIGNED_FLIP", 6240 "TXFIFO_EMPTY", 6241 "TXFIFO_FULL", 6242 "TXFIFO_OVERRUN", 6243 "TXFIFO_UNDERRUN", 6244 "TXFIR_MAIN_ADJUSTED", 6245 "TXFIR_MAIN_AFTER_OVR", 6246 "TXFIR_MAIN_OFFSET", 6247 "TXFIR_MAIN_OVERRIDE", 6248 "TXFIR_OVERRIDE_EN", 6249 "TXFIR_POST2", 6250 "TXFIR_POST2_ADJUSTED", 6251 "TXFIR_POST2_OFFSET", 6252 "TXFIR_POST3", 6253 "TXFIR_POST3_ADJUSTED", 6254 "TXFIR_POST3_OFFSET", 6255 "TXFIR_POST_ADJUSTED", 6256 "TXFIR_POST_AFTER_OVR", 6257 "TXFIR_POST_OFFSET", 6258 "TXFIR_POST_OVERRIDE", 6259 "TXFIR_PRE_ADJUSTED", 6260 "TXFIR_PRE_AFTER_OVR", 6261 "TXFIR_PRE_OFFSET", 6262 "TXFIR_PRE_OVERRIDE", 6263 "TXPKTCNT_L", 6264 "TXPKTCNT_U", 6265 "TXSM_STATE", 6266 "TX_CLK_VLD_LH", 6267 "TX_CLK_VLD_LL", 6268 "TX_CLK_VLD_OVRD", 6269 "TX_CLK_VLD_STS", 6270 "TX_DISABLE", 6271 "TX_DISABLE_OEN", 6272 "TX_DISABLE_OUTPUT_SEL", 6273 "TX_DISABLE_TIMER_CTRL", 6274 "TX_DISABLE_TIMER_PERIOD", 6275 "TX_EEE_ALERT_EN", 6276 "TX_EEE_QUIET_EN", 6277 "TX_FIFO_WATERMARK", 6278 "TX_LANE_MAP_0", 6279 "TX_LANE_MAP_1", 6280 "TX_LANE_MAP_2", 6281 "TX_LANE_MAP_3", 6282 "TX_LANE_RATE_MISMATCH", 6283 "TX_LANE_RATE_MISMATCH_VL1", 6284 "TX_LINK_INTERRUPT", 6285 "TX_LOCAL_FAULT", 6286 "TX_LPI_RECEIVED", 6287 "TX_MODE", 6288 "TX_MSBUS_TYPE", 6289 "TX_MUX_SEL_ORDER", 6290 "TX_PCS_NATIVE_ANA_FRMT_EN", 6291 "TX_PI_EN", 6292 "TX_PI_EXT_CTRL_EN", 6293 "TX_PI_EXT_PHASE_BWSEL_INTEG", 6294 "TX_PI_FIRST_ORDER_BWSEL_INTEG", 6295 "TX_PI_FRC_PHASE_STEP_MUX_SEL", 6296 "TX_PI_FREQ_OVERRIDE_EN", 6297 "TX_PI_FREQ_OVERRIDE_VAL", 6298 "TX_PI_FRZ_FRC", 6299 "TX_PI_FRZ_FRC_VAL", 6300 "TX_PI_FRZ_MODE", 6301 "TX_PI_INTEG1_REG", 6302 "TX_PI_INTEG2_REG", 6303 "TX_PI_JITTER_FILTER_EN", 6304 "TX_PI_JIT_AMP", 6305 "TX_PI_JIT_FREQ_IDX", 6306 "TX_PI_JIT_SSC_FREQ_MODE", 6307 "TX_PI_LANE_SEL_FRC", 6308 "TX_PI_LANE_SEL_FRC_VAL", 6309 "TX_PI_LOOP_FILTER_STABLE", 6310 "TX_PI_LOOP_TIMING_SRC_SEL", 6311 "TX_PI_PHASE_CNTR", 6312 "TX_PI_PHASE_ERR", 6313 "TX_PI_PHASE_INVERT", 6314 "TX_PI_PHASE_OVERRIDE", 6315 "TX_PI_PHASE_STEP_DIR", 6316 "TX_PI_PHASE_STEP_NUM", 6317 "TX_PI_PHASE_STROBE", 6318 "TX_PI_RESET_CODE_DBG", 6319 "TX_PI_RMT_LPBK_BYPASS_FLT", 6320 "TX_PI_SECOND_ORDER_BWSEL_INTEG", 6321 "TX_PI_SECOND_ORDER_LOOP_EN", 6322 "TX_PI_SJ_GEN_EN", 6323 "TX_PI_SSC_GEN_EN", 6324 "TX_PMD_DP_INVERT", 6325 "TX_PRTP_EN", 6326 "TX_REMOTE_FAULT", 6327 "TX_RESET_COUNT", 6328 "TX_S_CLKGATE_FRC_ON", 6329 "TX_S_COMCLK_FRC_ON", 6330 "TX_S_COMCLK_SEL", 6331 "TX_TEST_PORT_SEL", 6332 "T_TYPE_CODED", 6333 "UC_ACK_CORE_CFG_DONE", 6334 "UC_ACK_CORE_DP_RESET", 6335 "UC_ACK_DSC_CONFIG", 6336 "UC_ACK_DSC_EEE_DONE", 6337 "UC_ACK_DSC_RESET", 6338 "UC_ACK_DSC_RESTART", 6339 "UC_ACK_LANE_CFG_DONE", 6340 "UC_ACK_LANE_DP_RESET", 6341 "UC_ACTIVE", 6342 "UC_DSC_ERROR_FOUND", 6343 "UC_DSC_GP_UC_REQ", 6344 "UC_DSC_READY_FOR_CMD", 6345 "UC_DSC_SCRATCH", 6346 "UC_DSC_SUPP_INFO", 6347 "UC_TRNSUM_EN", 6348 "UC_TUNE_EN", 6349 "UNCORCOUNTH", 6350 "UNCORCOUNTL", 6351 "VCO_DONE_EN", 6352 "VCO_RST_EN", 6353 "VCO_START_TIME", 6354 "VCO_STEP_TIME", 6355 "VGA3_CTRL_BIN", 6356 "VGA_ACC_HYS_EN", 6357 "VGA_BIN", 6358 "VGA_CTRL_BIN", 6359 "VGA_EN", 6360 "VGA_ERR_GAIN", 6361 "VGA_ERR_SEL", 6362 "VGA_INV_M1", 6363 "VGA_INV_P1", 6364 "VGA_P1_ACC_CLR", 6365 "VGA_P1_GRADIENT_INVERT", 6366 "VGA_PATTERN", 6367 "VGA_PATTERN_BIT_EN", 6368 "VGA_TABLEMAP_DISABLE", 6369 "VGA_UPDATE_GAIN", 6370 "VL_ON_LL_0", 6371 "VL_ON_LL_1", 6372 "WAIT_CNTR_LIMIT", 6373 "WIN_CAL_CNTR", 6374 "WIS", 6375 "WM", 6376 }; 6377 6378 #endif 6379 #endif 6380 #endif 6381 #endif /* PHYMOD_CONFIG_INCLUDE_FIELD_INFO */ 6382 6383 6384 6385 /******************************************************************************* 6386 * 6387 * The following is the symbol table itself. 6388 * It defines the entries for all registers and memories. 6389 * It also incorporates the field information for each register and memory if 6390 * applicable. 6391 */ 6392 static const phymod_symbol_t bcmi_tsce_xgxs_syms[] = { 6393 #ifndef PHYMOD_CONFIG_EXCLUDE_CHIP_SYMBOLS_BCMI_TSCE_XGXS 6394 { 6395 BCMI_TSCE_XGXS_PHYID2r, 6396 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6397 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 6398 BCMI_TSCE_XGXS_PHYID2r_fields, 6399 #else 6400 0, 6401 #endif 6402 #endif 6403 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6404 PHYMOD_SYMBOL_FLAG_REGISTER, 6405 "PHYID2r", 6406 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6407 "CL22_B0_PHYID2", 6408 NULL, 6409 #endif 6410 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6411 0x600d, /* 24589 */ 6412 0, 6413 #endif 6414 }, 6415 { 6416 BCMI_TSCE_XGXS_PHYID3r, 6417 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6418 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 6419 BCMI_TSCE_XGXS_PHYID3r_fields, 6420 #else 6421 0, 6422 #endif 6423 #endif 6424 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6425 PHYMOD_SYMBOL_FLAG_REGISTER, 6426 "PHYID3r", 6427 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6428 "CL22_B0_PHYID3", 6429 NULL, 6430 #endif 6431 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6432 0x8770, /* 34672 */ 6433 0, 6434 #endif 6435 }, 6436 { 6437 BCMI_TSCE_XGXS_MAIN0_SETUPr, 6438 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6439 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 6440 BCMI_TSCE_XGXS_MAIN0_SETUPr_fields, 6441 #else 6442 0, 6443 #endif 6444 #endif 6445 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6446 PHYMOD_SYMBOL_FLAG_REGISTER, 6447 "MAIN0_SETUPr", 6448 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6449 NULL, 6450 NULL, 6451 #endif 6452 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6453 0x0, /* 0 */ 6454 0, 6455 #endif 6456 }, 6457 { 6458 BCMI_TSCE_XGXS_MAIN0_SYNCE_CTLr, 6459 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6460 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 6461 BCMI_TSCE_XGXS_MAIN0_SYNCE_CTLr_fields, 6462 #else 6463 0, 6464 #endif 6465 #endif 6466 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6467 PHYMOD_SYMBOL_FLAG_REGISTER, 6468 "MAIN0_SYNCE_CTLr", 6469 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6470 "MAIN0_SYNCE_CONTROL", 6471 NULL, 6472 #endif 6473 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6474 0xaa, /* 170 */ 6475 0, 6476 #endif 6477 }, 6478 { 6479 BCMI_TSCE_XGXS_MAIN0_LN_SWPr, 6480 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6481 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 6482 BCMI_TSCE_XGXS_MAIN0_LN_SWPr_fields, 6483 #else 6484 0, 6485 #endif 6486 #endif 6487 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6488 PHYMOD_SYMBOL_FLAG_REGISTER, 6489 "MAIN0_LN_SWPr", 6490 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6491 "MAIN0_LANE_SWAP", 6492 NULL, 6493 #endif 6494 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6495 0xe4, /* 228 */ 6496 0, 6497 #endif 6498 }, 6499 { 6500 BCMI_TSCE_XGXS_MAIN0_DEVINPKG5r, 6501 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6502 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 6503 BCMI_TSCE_XGXS_MAIN0_DEVINPKG5r_fields, 6504 #else 6505 0, 6506 #endif 6507 #endif 6508 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6509 PHYMOD_SYMBOL_FLAG_REGISTER, 6510 "MAIN0_DEVINPKG5r", 6511 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6512 "MAIN0_DEVICEINPKG5", 6513 NULL, 6514 #endif 6515 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6516 0x83, /* 131 */ 6517 0, 6518 #endif 6519 }, 6520 { 6521 BCMI_TSCE_XGXS_MAIN0_MISCr, 6522 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6523 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 6524 BCMI_TSCE_XGXS_MAIN0_MISCr_fields, 6525 #else 6526 0, 6527 #endif 6528 #endif 6529 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6530 PHYMOD_SYMBOL_FLAG_REGISTER, 6531 "MAIN0_MISCr", 6532 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6533 NULL, 6534 NULL, 6535 #endif 6536 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6537 0x0, /* 0 */ 6538 0, 6539 #endif 6540 }, 6541 { 6542 BCMI_TSCE_XGXS_MAIN0_TICK_CTL1r, 6543 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6544 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 6545 BCMI_TSCE_XGXS_MAIN0_TICK_CTL1r_fields, 6546 #else 6547 0, 6548 #endif 6549 #endif 6550 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6551 PHYMOD_SYMBOL_FLAG_REGISTER, 6552 "MAIN0_TICK_CTL1r", 6553 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6554 "MAIN0_TICK_CONTROL_1", 6555 NULL, 6556 #endif 6557 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6558 0x0, /* 0 */ 6559 0, 6560 #endif 6561 }, 6562 { 6563 BCMI_TSCE_XGXS_MAIN0_TICK_CTL0r, 6564 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6565 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 6566 BCMI_TSCE_XGXS_MAIN0_TICK_CTL0r_fields, 6567 #else 6568 0, 6569 #endif 6570 #endif 6571 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6572 PHYMOD_SYMBOL_FLAG_REGISTER, 6573 "MAIN0_TICK_CTL0r", 6574 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6575 "MAIN0_TICK_CONTROL_0", 6576 NULL, 6577 #endif 6578 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6579 0x0, /* 0 */ 6580 0, 6581 #endif 6582 }, 6583 { 6584 BCMI_TSCE_XGXS_MAIN0_LPBK_CTLr, 6585 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6586 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 6587 BCMI_TSCE_XGXS_MAIN0_LPBK_CTLr_fields, 6588 #else 6589 0, 6590 #endif 6591 #endif 6592 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6593 PHYMOD_SYMBOL_FLAG_REGISTER, 6594 "MAIN0_LPBK_CTLr", 6595 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6596 "MAIN0_LOOPBACK_CONTROL", 6597 NULL, 6598 #endif 6599 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6600 0x0, /* 0 */ 6601 0, 6602 #endif 6603 }, 6604 { 6605 BCMI_TSCE_XGXS_MAIN0_MDIO_BCSTr, 6606 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6607 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 6608 BCMI_TSCE_XGXS_MAIN0_MDIO_BCSTr_fields, 6609 #else 6610 0, 6611 #endif 6612 #endif 6613 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6614 PHYMOD_SYMBOL_FLAG_REGISTER, 6615 "MAIN0_MDIO_BCSTr", 6616 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6617 "MAIN0_MDIO_BROADCAST", 6618 NULL, 6619 #endif 6620 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6621 0xf800, /* 63488 */ 6622 0, 6623 #endif 6624 }, 6625 { 6626 BCMI_TSCE_XGXS_MAIN0_SERDESIDr, 6627 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6628 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 6629 BCMI_TSCE_XGXS_MAIN0_SERDESIDr_fields, 6630 #else 6631 0, 6632 #endif 6633 #endif 6634 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6635 PHYMOD_SYMBOL_FLAG_REGISTER, 6636 "MAIN0_SERDESIDr", 6637 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6638 NULL, 6639 NULL, 6640 #endif 6641 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6642 0x2d2, /* 722 */ 6643 0, 6644 #endif 6645 }, 6646 { 6647 BCMI_TSCE_XGXS_PMD_X1_CTLr, 6648 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6649 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 6650 BCMI_TSCE_XGXS_PMD_X1_CTLr_fields, 6651 #else 6652 0, 6653 #endif 6654 #endif 6655 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6656 PHYMOD_SYMBOL_FLAG_REGISTER, 6657 "PMD_X1_CTLr", 6658 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6659 "PMD_X1_CONTROL", 6660 NULL, 6661 #endif 6662 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6663 0x0, /* 0 */ 6664 0, 6665 #endif 6666 }, 6667 { 6668 BCMI_TSCE_XGXS_PMD_X1_MODEr, 6669 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6670 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 6671 BCMI_TSCE_XGXS_PMD_X1_MODEr_fields, 6672 #else 6673 0, 6674 #endif 6675 #endif 6676 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6677 PHYMOD_SYMBOL_FLAG_REGISTER, 6678 "PMD_X1_MODEr", 6679 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6680 NULL, 6681 NULL, 6682 #endif 6683 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6684 0x0, /* 0 */ 6685 0, 6686 #endif 6687 }, 6688 { 6689 BCMI_TSCE_XGXS_PMD_X1_STSr, 6690 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6691 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 6692 BCMI_TSCE_XGXS_PMD_X1_STSr_fields, 6693 #else 6694 0, 6695 #endif 6696 #endif 6697 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6698 PHYMOD_SYMBOL_FLAG_REGISTER, 6699 "PMD_X1_STSr", 6700 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6701 "PMD_X1_STATUS", 6702 NULL, 6703 #endif 6704 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6705 0x0, /* 0 */ 6706 0, 6707 #endif 6708 }, 6709 { 6710 BCMI_TSCE_XGXS_PMD_X1_LATCH_STSr, 6711 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6712 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 6713 BCMI_TSCE_XGXS_PMD_X1_LATCH_STSr_fields, 6714 #else 6715 0, 6716 #endif 6717 #endif 6718 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6719 PHYMOD_SYMBOL_FLAG_REGISTER, 6720 "PMD_X1_LATCH_STSr", 6721 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6722 "PMD_X1_LATCH_STATUS", 6723 NULL, 6724 #endif 6725 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6726 0x0, /* 0 */ 6727 0, 6728 #endif 6729 }, 6730 { 6731 BCMI_TSCE_XGXS_PMD_X1_OVRRr, 6732 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6733 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 6734 BCMI_TSCE_XGXS_PMD_X1_OVRRr_fields, 6735 #else 6736 0, 6737 #endif 6738 #endif 6739 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6740 PHYMOD_SYMBOL_FLAG_REGISTER, 6741 "PMD_X1_OVRRr", 6742 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6743 "PMD_X1_OVERRIDE", 6744 NULL, 6745 #endif 6746 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6747 0x0, /* 0 */ 6748 0, 6749 #endif 6750 }, 6751 { 6752 BCMI_TSCE_XGXS_PKTGEN_CTL1r, 6753 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6754 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 6755 BCMI_TSCE_XGXS_PKTGEN_CTL1r_fields, 6756 #else 6757 0, 6758 #endif 6759 #endif 6760 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6761 PHYMOD_SYMBOL_FLAG_REGISTER, 6762 "PKTGEN_CTL1r", 6763 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6764 "PKTGEN0_PKTGENCTRL1", 6765 NULL, 6766 #endif 6767 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6768 0x0, /* 0 */ 6769 0, 6770 #endif 6771 }, 6772 { 6773 BCMI_TSCE_XGXS_PKTGEN_CTL2r, 6774 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6775 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 6776 BCMI_TSCE_XGXS_PKTGEN_CTL2r_fields, 6777 #else 6778 0, 6779 #endif 6780 #endif 6781 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6782 PHYMOD_SYMBOL_FLAG_REGISTER, 6783 "PKTGEN_CTL2r", 6784 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6785 "PKTGEN0_PKTGENCTRL2", 6786 NULL, 6787 #endif 6788 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6789 0x28, /* 40 */ 6790 0, 6791 #endif 6792 }, 6793 { 6794 BCMI_TSCE_XGXS_PKTGEN_PRTPCTLr, 6795 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6796 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 6797 BCMI_TSCE_XGXS_PKTGEN_PRTPCTLr_fields, 6798 #else 6799 0, 6800 #endif 6801 #endif 6802 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6803 PHYMOD_SYMBOL_FLAG_REGISTER, 6804 "PKTGEN_PRTPCTLr", 6805 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6806 "PKTGEN0_PRTPCONTROL", 6807 NULL, 6808 #endif 6809 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6810 0x0, /* 0 */ 6811 0, 6812 #endif 6813 }, 6814 { 6815 BCMI_TSCE_XGXS_PKTGEN_CRCERRCNTr, 6816 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6817 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 6818 BCMI_TSCE_XGXS_PKTGEN_CRCERRCNTr_fields, 6819 #else 6820 0, 6821 #endif 6822 #endif 6823 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6824 PHYMOD_SYMBOL_FLAG_REGISTER, 6825 "PKTGEN_CRCERRCNTr", 6826 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6827 "PKTGEN0_CRCERRORCOUNT", 6828 NULL, 6829 #endif 6830 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6831 0x0, /* 0 */ 6832 0, 6833 #endif 6834 }, 6835 { 6836 BCMI_TSCE_XGXS_PKTGEN_PRTPERRCTRr, 6837 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6838 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 6839 BCMI_TSCE_XGXS_PKTGEN_PRTPERRCTRr_fields, 6840 #else 6841 0, 6842 #endif 6843 #endif 6844 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6845 PHYMOD_SYMBOL_FLAG_REGISTER, 6846 "PKTGEN_PRTPERRCTRr", 6847 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6848 "PKTGEN0_PRTPERRORCOUNTER", 6849 NULL, 6850 #endif 6851 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6852 0x0, /* 0 */ 6853 0, 6854 #endif 6855 }, 6856 { 6857 BCMI_TSCE_XGXS_PKTGEN_PRTPLOCKSTSr, 6858 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6859 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 6860 BCMI_TSCE_XGXS_PKTGEN_PRTPLOCKSTSr_fields, 6861 #else 6862 0, 6863 #endif 6864 #endif 6865 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6866 PHYMOD_SYMBOL_FLAG_REGISTER, 6867 "PKTGEN_PRTPLOCKSTSr", 6868 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6869 "PKTGEN0_PRTPLOCKSTATUS", 6870 NULL, 6871 #endif 6872 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6873 0x0, /* 0 */ 6874 0, 6875 #endif 6876 }, 6877 { 6878 BCMI_TSCE_XGXS_PKTGEN_PCS_SEEDA0r, 6879 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6880 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 6881 BCMI_TSCE_XGXS_PKTGEN_PCS_SEEDA0r_fields, 6882 #else 6883 0, 6884 #endif 6885 #endif 6886 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6887 PHYMOD_SYMBOL_FLAG_REGISTER, 6888 "PKTGEN_PCS_SEEDA0r", 6889 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6890 "PKTGEN0_PCS_SEEDA0", 6891 NULL, 6892 #endif 6893 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6894 0x0, /* 0 */ 6895 0, 6896 #endif 6897 }, 6898 { 6899 BCMI_TSCE_XGXS_PKTGEN_PCS_SEEDA1r, 6900 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6901 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 6902 BCMI_TSCE_XGXS_PKTGEN_PCS_SEEDA1r_fields, 6903 #else 6904 0, 6905 #endif 6906 #endif 6907 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6908 PHYMOD_SYMBOL_FLAG_REGISTER, 6909 "PKTGEN_PCS_SEEDA1r", 6910 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6911 "PKTGEN0_PCS_SEEDA1", 6912 NULL, 6913 #endif 6914 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6915 0x0, /* 0 */ 6916 0, 6917 #endif 6918 }, 6919 { 6920 BCMI_TSCE_XGXS_PKTGEN_PCS_SEEDA2r, 6921 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6922 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 6923 BCMI_TSCE_XGXS_PKTGEN_PCS_SEEDA2r_fields, 6924 #else 6925 0, 6926 #endif 6927 #endif 6928 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6929 PHYMOD_SYMBOL_FLAG_REGISTER, 6930 "PKTGEN_PCS_SEEDA2r", 6931 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6932 "PKTGEN0_PCS_SEEDA2", 6933 NULL, 6934 #endif 6935 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6936 0x0, /* 0 */ 6937 0, 6938 #endif 6939 }, 6940 { 6941 BCMI_TSCE_XGXS_PKTGEN_PCS_SEEDA3r, 6942 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6943 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 6944 BCMI_TSCE_XGXS_PKTGEN_PCS_SEEDA3r_fields, 6945 #else 6946 0, 6947 #endif 6948 #endif 6949 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6950 PHYMOD_SYMBOL_FLAG_REGISTER, 6951 "PKTGEN_PCS_SEEDA3r", 6952 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6953 "PKTGEN0_PCS_SEEDA3", 6954 NULL, 6955 #endif 6956 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6957 0x0, /* 0 */ 6958 0, 6959 #endif 6960 }, 6961 { 6962 BCMI_TSCE_XGXS_PKTGEN_PCS_SEEDB0r, 6963 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6964 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 6965 BCMI_TSCE_XGXS_PKTGEN_PCS_SEEDB0r_fields, 6966 #else 6967 0, 6968 #endif 6969 #endif 6970 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6971 PHYMOD_SYMBOL_FLAG_REGISTER, 6972 "PKTGEN_PCS_SEEDB0r", 6973 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6974 "PKTGEN0_PCS_SEEDB0", 6975 NULL, 6976 #endif 6977 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6978 0x0, /* 0 */ 6979 0, 6980 #endif 6981 }, 6982 { 6983 BCMI_TSCE_XGXS_PKTGEN_PCS_SEEDB1r, 6984 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6985 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 6986 BCMI_TSCE_XGXS_PKTGEN_PCS_SEEDB1r_fields, 6987 #else 6988 0, 6989 #endif 6990 #endif 6991 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6992 PHYMOD_SYMBOL_FLAG_REGISTER, 6993 "PKTGEN_PCS_SEEDB1r", 6994 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6995 "PKTGEN0_PCS_SEEDB1", 6996 NULL, 6997 #endif 6998 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6999 0x0, /* 0 */ 7000 0, 7001 #endif 7002 }, 7003 { 7004 BCMI_TSCE_XGXS_PKTGEN_PCS_SEEDB2r, 7005 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7006 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 7007 BCMI_TSCE_XGXS_PKTGEN_PCS_SEEDB2r_fields, 7008 #else 7009 0, 7010 #endif 7011 #endif 7012 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7013 PHYMOD_SYMBOL_FLAG_REGISTER, 7014 "PKTGEN_PCS_SEEDB2r", 7015 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7016 "PKTGEN0_PCS_SEEDB2", 7017 NULL, 7018 #endif 7019 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7020 0x0, /* 0 */ 7021 0, 7022 #endif 7023 }, 7024 { 7025 BCMI_TSCE_XGXS_PKTGEN_PCS_SEEDB3r, 7026 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7027 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 7028 BCMI_TSCE_XGXS_PKTGEN_PCS_SEEDB3r_fields, 7029 #else 7030 0, 7031 #endif 7032 #endif 7033 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7034 PHYMOD_SYMBOL_FLAG_REGISTER, 7035 "PKTGEN_PCS_SEEDB3r", 7036 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7037 "PKTGEN0_PCS_SEEDB3", 7038 NULL, 7039 #endif 7040 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7041 0x0, /* 0 */ 7042 0, 7043 #endif 7044 }, 7045 { 7046 BCMI_TSCE_XGXS_PKTGEN_PAYLOADBYTESr, 7047 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7048 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 7049 BCMI_TSCE_XGXS_PKTGEN_PAYLOADBYTESr_fields, 7050 #else 7051 0, 7052 #endif 7053 #endif 7054 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7055 PHYMOD_SYMBOL_FLAG_REGISTER, 7056 "PKTGEN_PAYLOADBYTESr", 7057 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7058 "PKTGEN1_PAYLOADBYTES", 7059 NULL, 7060 #endif 7061 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7062 0x0, /* 0 */ 7063 0, 7064 #endif 7065 }, 7066 { 7067 BCMI_TSCE_XGXS_PKTGEN_ERRMASK4r, 7068 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7069 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 7070 BCMI_TSCE_XGXS_PKTGEN_ERRMASK4r_fields, 7071 #else 7072 0, 7073 #endif 7074 #endif 7075 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7076 PHYMOD_SYMBOL_FLAG_REGISTER, 7077 "PKTGEN_ERRMASK4r", 7078 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7079 "PKTGEN1_ERRORMASK4", 7080 NULL, 7081 #endif 7082 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7083 0x0, /* 0 */ 7084 0, 7085 #endif 7086 }, 7087 { 7088 BCMI_TSCE_XGXS_PKTGEN_ERRMASK3r, 7089 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7090 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 7091 BCMI_TSCE_XGXS_PKTGEN_ERRMASK3r_fields, 7092 #else 7093 0, 7094 #endif 7095 #endif 7096 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7097 PHYMOD_SYMBOL_FLAG_REGISTER, 7098 "PKTGEN_ERRMASK3r", 7099 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7100 "PKTGEN1_ERRORMASK3", 7101 NULL, 7102 #endif 7103 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7104 0x0, /* 0 */ 7105 0, 7106 #endif 7107 }, 7108 { 7109 BCMI_TSCE_XGXS_PKTGEN_ERRMASK2r, 7110 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7111 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 7112 BCMI_TSCE_XGXS_PKTGEN_ERRMASK2r_fields, 7113 #else 7114 0, 7115 #endif 7116 #endif 7117 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7118 PHYMOD_SYMBOL_FLAG_REGISTER, 7119 "PKTGEN_ERRMASK2r", 7120 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7121 "PKTGEN1_ERRORMASK2", 7122 NULL, 7123 #endif 7124 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7125 0x0, /* 0 */ 7126 0, 7127 #endif 7128 }, 7129 { 7130 BCMI_TSCE_XGXS_PKTGEN_ERRMASK1r, 7131 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7132 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 7133 BCMI_TSCE_XGXS_PKTGEN_ERRMASK1r_fields, 7134 #else 7135 0, 7136 #endif 7137 #endif 7138 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7139 PHYMOD_SYMBOL_FLAG_REGISTER, 7140 "PKTGEN_ERRMASK1r", 7141 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7142 "PKTGEN1_ERRORMASK1", 7143 NULL, 7144 #endif 7145 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7146 0x0, /* 0 */ 7147 0, 7148 #endif 7149 }, 7150 { 7151 BCMI_TSCE_XGXS_PKTGEN_ERRMASK0r, 7152 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7153 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 7154 BCMI_TSCE_XGXS_PKTGEN_ERRMASK0r_fields, 7155 #else 7156 0, 7157 #endif 7158 #endif 7159 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7160 PHYMOD_SYMBOL_FLAG_REGISTER, 7161 "PKTGEN_ERRMASK0r", 7162 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7163 "PKTGEN1_ERRORMASK0", 7164 NULL, 7165 #endif 7166 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7167 0x0, /* 0 */ 7168 0, 7169 #endif 7170 }, 7171 { 7172 BCMI_TSCE_XGXS_MEM_ECC_INT_1BITr, 7173 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7174 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 7175 BCMI_TSCE_XGXS_MEM_ECC_INT_1BITr_fields, 7176 #else 7177 0, 7178 #endif 7179 #endif 7180 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7181 PHYMOD_SYMBOL_FLAG_REGISTER, 7182 "MEM_ECC_INT_1BITr", 7183 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7184 "MEM_ECC_ECC_INT_1BIT", 7185 NULL, 7186 #endif 7187 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7188 0x0, /* 0 */ 7189 0, 7190 #endif 7191 }, 7192 { 7193 BCMI_TSCE_XGXS_MEM_ECC_INT_2BITr, 7194 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7195 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 7196 BCMI_TSCE_XGXS_MEM_ECC_INT_2BITr_fields, 7197 #else 7198 0, 7199 #endif 7200 #endif 7201 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7202 PHYMOD_SYMBOL_FLAG_REGISTER, 7203 "MEM_ECC_INT_2BITr", 7204 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7205 "MEM_ECC_ECC_INT_2BIT", 7206 NULL, 7207 #endif 7208 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7209 0x0, /* 0 */ 7210 0, 7211 #endif 7212 }, 7213 { 7214 BCMI_TSCE_XGXS_MEM_ECC_MSK_1BITr, 7215 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7216 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 7217 BCMI_TSCE_XGXS_MEM_ECC_MSK_1BITr_fields, 7218 #else 7219 0, 7220 #endif 7221 #endif 7222 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7223 PHYMOD_SYMBOL_FLAG_REGISTER, 7224 "MEM_ECC_MSK_1BITr", 7225 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7226 "MEM_ECC_ECC_MSK_1BIT", 7227 NULL, 7228 #endif 7229 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7230 0x0, /* 0 */ 7231 0, 7232 #endif 7233 }, 7234 { 7235 BCMI_TSCE_XGXS_MEM_ECC_MSK_2BITr, 7236 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7237 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 7238 BCMI_TSCE_XGXS_MEM_ECC_MSK_2BITr_fields, 7239 #else 7240 0, 7241 #endif 7242 #endif 7243 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7244 PHYMOD_SYMBOL_FLAG_REGISTER, 7245 "MEM_ECC_MSK_2BITr", 7246 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7247 "MEM_ECC_ECC_MSK_2BIT", 7248 NULL, 7249 #endif 7250 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7251 0x0, /* 0 */ 7252 0, 7253 #endif 7254 }, 7255 { 7256 BCMI_TSCE_XGXS_MEM_ECC_DISr, 7257 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7258 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 7259 BCMI_TSCE_XGXS_MEM_ECC_DISr_fields, 7260 #else 7261 0, 7262 #endif 7263 #endif 7264 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7265 PHYMOD_SYMBOL_FLAG_REGISTER, 7266 "MEM_ECC_DISr", 7267 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7268 "MEM_ECC_ECC_DISABLE", 7269 NULL, 7270 #endif 7271 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7272 0x0, /* 0 */ 7273 0, 7274 #endif 7275 }, 7276 { 7277 BCMI_TSCE_XGXS_MEM_ECC_CORRUPTr, 7278 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7279 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 7280 BCMI_TSCE_XGXS_MEM_ECC_CORRUPTr_fields, 7281 #else 7282 0, 7283 #endif 7284 #endif 7285 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7286 PHYMOD_SYMBOL_FLAG_REGISTER, 7287 "MEM_ECC_CORRUPTr", 7288 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7289 "MEM_ECC_ECC_CORRUPT", 7290 NULL, 7291 #endif 7292 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7293 0x0, /* 0 */ 7294 0, 7295 #endif 7296 }, 7297 { 7298 BCMI_TSCE_XGXS_MEM_ECC_DESKEW_STSr, 7299 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7300 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 7301 BCMI_TSCE_XGXS_MEM_ECC_DESKEW_STSr_fields, 7302 #else 7303 0, 7304 #endif 7305 #endif 7306 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7307 PHYMOD_SYMBOL_FLAG_REGISTER, 7308 "MEM_ECC_DESKEW_STSr", 7309 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7310 "MEM_ECC_ECC_DESKEW_STATUS", 7311 NULL, 7312 #endif 7313 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7314 0x0, /* 0 */ 7315 0, 7316 #endif 7317 }, 7318 { 7319 BCMI_TSCE_XGXS_MEM_ECC_RFEC0_STSr, 7320 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7321 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 7322 BCMI_TSCE_XGXS_MEM_ECC_RFEC0_STSr_fields, 7323 #else 7324 0, 7325 #endif 7326 #endif 7327 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7328 PHYMOD_SYMBOL_FLAG_REGISTER, 7329 "MEM_ECC_RFEC0_STSr", 7330 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7331 "MEM_ECC_ECC_RFEC0_STATUS", 7332 NULL, 7333 #endif 7334 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7335 0x0, /* 0 */ 7336 0, 7337 #endif 7338 }, 7339 { 7340 BCMI_TSCE_XGXS_MEM_ECC_RFEC1_STSr, 7341 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7342 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 7343 BCMI_TSCE_XGXS_MEM_ECC_RFEC1_STSr_fields, 7344 #else 7345 0, 7346 #endif 7347 #endif 7348 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7349 PHYMOD_SYMBOL_FLAG_REGISTER, 7350 "MEM_ECC_RFEC1_STSr", 7351 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7352 "MEM_ECC_ECC_RFEC1_STATUS", 7353 NULL, 7354 #endif 7355 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7356 0x0, /* 0 */ 7357 0, 7358 #endif 7359 }, 7360 { 7361 BCMI_TSCE_XGXS_MEM_TM_DESKEWr, 7362 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7363 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 7364 BCMI_TSCE_XGXS_MEM_TM_DESKEWr_fields, 7365 #else 7366 0, 7367 #endif 7368 #endif 7369 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7370 PHYMOD_SYMBOL_FLAG_REGISTER, 7371 "MEM_TM_DESKEWr", 7372 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7373 "MEM_DBG_MEM_TM_DESKEW", 7374 NULL, 7375 #endif 7376 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7377 0x0, /* 0 */ 7378 0, 7379 #endif 7380 }, 7381 { 7382 BCMI_TSCE_XGXS_MEM_TM_RFEC0r, 7383 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7384 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 7385 BCMI_TSCE_XGXS_MEM_TM_RFEC0r_fields, 7386 #else 7387 0, 7388 #endif 7389 #endif 7390 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7391 PHYMOD_SYMBOL_FLAG_REGISTER, 7392 "MEM_TM_RFEC0r", 7393 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7394 "MEM_DBG_MEM_TM_RFEC0", 7395 NULL, 7396 #endif 7397 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7398 0x0, /* 0 */ 7399 0, 7400 #endif 7401 }, 7402 { 7403 BCMI_TSCE_XGXS_MEM_TM_RFEC1r, 7404 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7405 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 7406 BCMI_TSCE_XGXS_MEM_TM_RFEC1r_fields, 7407 #else 7408 0, 7409 #endif 7410 #endif 7411 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7412 PHYMOD_SYMBOL_FLAG_REGISTER, 7413 "MEM_TM_RFEC1r", 7414 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7415 "MEM_DBG_MEM_TM_RFEC1", 7416 NULL, 7417 #endif 7418 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7419 0x0, /* 0 */ 7420 0, 7421 #endif 7422 }, 7423 { 7424 BCMI_TSCE_XGXS_MISC_XGXSSTS0r, 7425 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7426 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 7427 BCMI_TSCE_XGXS_MISC_XGXSSTS0r_fields, 7428 #else 7429 0, 7430 #endif 7431 #endif 7432 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7433 PHYMOD_SYMBOL_FLAG_REGISTER, 7434 "MISC_XGXSSTS0r", 7435 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7436 "MISC_XGXSSTATUS0", 7437 NULL, 7438 #endif 7439 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7440 0x8000, /* 32768 */ 7441 0, 7442 #endif 7443 }, 7444 { 7445 BCMI_TSCE_XGXS_MISC_TX_RATE_MISMATCHr, 7446 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7447 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 7448 BCMI_TSCE_XGXS_MISC_TX_RATE_MISMATCHr_fields, 7449 #else 7450 0, 7451 #endif 7452 #endif 7453 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7454 PHYMOD_SYMBOL_FLAG_REGISTER, 7455 "MISC_TX_RATE_MISMATCHr", 7456 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7457 NULL, 7458 NULL, 7459 #endif 7460 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7461 0x0, /* 0 */ 7462 0, 7463 #endif 7464 }, 7465 { 7466 BCMI_TSCE_XGXS_MISC_SCRMBLR_CTLr, 7467 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7468 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 7469 BCMI_TSCE_XGXS_MISC_SCRMBLR_CTLr_fields, 7470 #else 7471 0, 7472 #endif 7473 #endif 7474 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7475 PHYMOD_SYMBOL_FLAG_REGISTER, 7476 "MISC_SCRMBLR_CTLr", 7477 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7478 "MISC_SCRAMBLER_CONTROL", 7479 NULL, 7480 #endif 7481 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7482 0x1d, /* 29 */ 7483 0, 7484 #endif 7485 }, 7486 { 7487 BCMI_TSCE_XGXS_MISC_CL72_EN_MASKr, 7488 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7489 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 7490 BCMI_TSCE_XGXS_MISC_CL72_EN_MASKr_fields, 7491 #else 7492 0, 7493 #endif 7494 #endif 7495 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7496 PHYMOD_SYMBOL_FLAG_REGISTER, 7497 "MISC_CL72_EN_MASKr", 7498 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7499 "MISC_CL72_ENABLE_MASK", 7500 NULL, 7501 #endif 7502 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7503 0xffff, /* 65535 */ 7504 0, 7505 #endif 7506 }, 7507 { 7508 BCMI_TSCE_XGXS_CL82_RX_AM_TMRr, 7509 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7510 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 7511 BCMI_TSCE_XGXS_CL82_RX_AM_TMRr_fields, 7512 #else 7513 0, 7514 #endif 7515 #endif 7516 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7517 PHYMOD_SYMBOL_FLAG_REGISTER, 7518 "CL82_RX_AM_TMRr", 7519 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7520 "CL82_SHARED_CL82_RX_AM_TIMER", 7521 NULL, 7522 #endif 7523 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7524 0x3fff, /* 16383 */ 7525 0, 7526 #endif 7527 }, 7528 { 7529 BCMI_TSCE_XGXS_CL82_LN_0_AM_BYTE10r, 7530 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7531 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 7532 BCMI_TSCE_XGXS_CL82_LN_0_AM_BYTE10r_fields, 7533 #else 7534 0, 7535 #endif 7536 #endif 7537 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7538 PHYMOD_SYMBOL_FLAG_REGISTER, 7539 "CL82_LN_0_AM_BYTE10r", 7540 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7541 "CL82_AM_REGS_LANE_0_AM_BYTE10", 7542 NULL, 7543 #endif 7544 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7545 0x7690, /* 30352 */ 7546 0, 7547 #endif 7548 }, 7549 { 7550 BCMI_TSCE_XGXS_CL82_LN_1_AM_BYTE10r, 7551 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7552 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 7553 BCMI_TSCE_XGXS_CL82_LN_1_AM_BYTE10r_fields, 7554 #else 7555 0, 7556 #endif 7557 #endif 7558 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7559 PHYMOD_SYMBOL_FLAG_REGISTER, 7560 "CL82_LN_1_AM_BYTE10r", 7561 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7562 "CL82_AM_REGS_LANE_1_AM_BYTE10", 7563 NULL, 7564 #endif 7565 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7566 0xc4f0, /* 50416 */ 7567 0, 7568 #endif 7569 }, 7570 { 7571 BCMI_TSCE_XGXS_CL82_LANES_1_0_AM_BYTE2r, 7572 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7573 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 7574 BCMI_TSCE_XGXS_CL82_LANES_1_0_AM_BYTE2r_fields, 7575 #else 7576 0, 7577 #endif 7578 #endif 7579 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7580 PHYMOD_SYMBOL_FLAG_REGISTER, 7581 "CL82_LANES_1_0_AM_BYTE2r", 7582 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7583 "CL82_AM_REGS_LANES_1_0_AM_BYTE2", 7584 NULL, 7585 #endif 7586 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7587 0xe647, /* 58951 */ 7588 0, 7589 #endif 7590 }, 7591 { 7592 BCMI_TSCE_XGXS_CL82_LN_2_AM_BYTE10r, 7593 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7594 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 7595 BCMI_TSCE_XGXS_CL82_LN_2_AM_BYTE10r_fields, 7596 #else 7597 0, 7598 #endif 7599 #endif 7600 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7601 PHYMOD_SYMBOL_FLAG_REGISTER, 7602 "CL82_LN_2_AM_BYTE10r", 7603 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7604 "CL82_AM_REGS_TSC_12_LANE_2_AM_BYTE10", 7605 NULL, 7606 #endif 7607 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7608 0x65c5, /* 26053 */ 7609 0, 7610 #endif 7611 }, 7612 { 7613 BCMI_TSCE_XGXS_CL82_LN_3_AM_BYTE10r, 7614 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7615 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 7616 BCMI_TSCE_XGXS_CL82_LN_3_AM_BYTE10r_fields, 7617 #else 7618 0, 7619 #endif 7620 #endif 7621 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7622 PHYMOD_SYMBOL_FLAG_REGISTER, 7623 "CL82_LN_3_AM_BYTE10r", 7624 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7625 "CL82_AM_REGS_TSC_12_LANE_3_AM_BYTE10", 7626 NULL, 7627 #endif 7628 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7629 0x79a2, /* 31138 */ 7630 0, 7631 #endif 7632 }, 7633 { 7634 BCMI_TSCE_XGXS_CL82_LANES_3_2_AM_BYTE2r, 7635 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7636 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 7637 BCMI_TSCE_XGXS_CL82_LANES_3_2_AM_BYTE2r_fields, 7638 #else 7639 0, 7640 #endif 7641 #endif 7642 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7643 PHYMOD_SYMBOL_FLAG_REGISTER, 7644 "CL82_LANES_3_2_AM_BYTE2r", 7645 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7646 "CL82_AM_REGS_TSC_12_LANES_3_2_AM_BYTE2", 7647 NULL, 7648 #endif 7649 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7650 0x3d9b, /* 15771 */ 7651 0, 7652 #endif 7653 }, 7654 { 7655 BCMI_TSCE_XGXS_RX_X1_DEC_CTL0r, 7656 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7657 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 7658 BCMI_TSCE_XGXS_RX_X1_DEC_CTL0r_fields, 7659 #else 7660 0, 7661 #endif 7662 #endif 7663 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7664 PHYMOD_SYMBOL_FLAG_REGISTER, 7665 "RX_X1_DEC_CTL0r", 7666 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7667 "RX_X1_CONTROL0_DECODE_CONTROL_0", 7668 NULL, 7669 #endif 7670 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7671 0x101, /* 257 */ 7672 0, 7673 #endif 7674 }, 7675 { 7676 BCMI_TSCE_XGXS_RX_X1_DEC_CTL1r, 7677 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7678 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 7679 BCMI_TSCE_XGXS_RX_X1_DEC_CTL1r_fields, 7680 #else 7681 0, 7682 #endif 7683 #endif 7684 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7685 PHYMOD_SYMBOL_FLAG_REGISTER, 7686 "RX_X1_DEC_CTL1r", 7687 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7688 "RX_X1_CONTROL0_DECODE_CONTROL_1", 7689 NULL, 7690 #endif 7691 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7692 0x6140, /* 24896 */ 7693 0, 7694 #endif 7695 }, 7696 { 7697 BCMI_TSCE_XGXS_RX_X1_DESKEW_WINSr, 7698 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7699 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 7700 BCMI_TSCE_XGXS_RX_X1_DESKEW_WINSr_fields, 7701 #else 7702 0, 7703 #endif 7704 #endif 7705 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7706 PHYMOD_SYMBOL_FLAG_REGISTER, 7707 "RX_X1_DESKEW_WINSr", 7708 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7709 "RX_X1_CONTROL0_DESKEW_WINDOWS", 7710 NULL, 7711 #endif 7712 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7713 0xee17, /* 60951 */ 7714 0, 7715 #endif 7716 }, 7717 { 7718 BCMI_TSCE_XGXS_RX_X1_SHCNT_CL49r, 7719 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7720 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 7721 BCMI_TSCE_XGXS_RX_X1_SHCNT_CL49r_fields, 7722 #else 7723 0, 7724 #endif 7725 #endif 7726 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7727 PHYMOD_SYMBOL_FLAG_REGISTER, 7728 "RX_X1_SHCNT_CL49r", 7729 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7730 "RX_X1_CONTROL1_SHCNT_CL49", 7731 NULL, 7732 #endif 7733 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7734 0x4010, /* 16400 */ 7735 0, 7736 #endif 7737 }, 7738 { 7739 BCMI_TSCE_XGXS_RX_X1_VALID_SHCNT_CL82r, 7740 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7741 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 7742 BCMI_TSCE_XGXS_RX_X1_VALID_SHCNT_CL82r_fields, 7743 #else 7744 0, 7745 #endif 7746 #endif 7747 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7748 PHYMOD_SYMBOL_FLAG_REGISTER, 7749 "RX_X1_VALID_SHCNT_CL82r", 7750 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7751 "RX_X1_CONTROL1_VALID_SHCNT_CL82", 7752 NULL, 7753 #endif 7754 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7755 0x400, /* 1024 */ 7756 0, 7757 #endif 7758 }, 7759 { 7760 BCMI_TSCE_XGXS_RX_X1_INVALID_SHCNT_CL82r, 7761 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7762 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 7763 BCMI_TSCE_XGXS_RX_X1_INVALID_SHCNT_CL82r_fields, 7764 #else 7765 0, 7766 #endif 7767 #endif 7768 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7769 PHYMOD_SYMBOL_FLAG_REGISTER, 7770 "RX_X1_INVALID_SHCNT_CL82r", 7771 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7772 "RX_X1_CONTROL1_INVALID_SHCNT_CL82", 7773 NULL, 7774 #endif 7775 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7776 0x41, /* 65 */ 7777 0, 7778 #endif 7779 }, 7780 { 7781 BCMI_TSCE_XGXS_RX_X1_SCW0r, 7782 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7783 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 7784 BCMI_TSCE_XGXS_RX_X1_SCW0r_fields, 7785 #else 7786 0, 7787 #endif 7788 #endif 7789 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7790 PHYMOD_SYMBOL_FLAG_REGISTER, 7791 "RX_X1_SCW0r", 7792 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7793 "RX_X1_CONTROL1_SCW0", 7794 NULL, 7795 #endif 7796 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7797 0x8090, /* 32912 */ 7798 0, 7799 #endif 7800 }, 7801 { 7802 BCMI_TSCE_XGXS_RX_X1_SCW1r, 7803 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7804 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 7805 BCMI_TSCE_XGXS_RX_X1_SCW1r_fields, 7806 #else 7807 0, 7808 #endif 7809 #endif 7810 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7811 PHYMOD_SYMBOL_FLAG_REGISTER, 7812 "RX_X1_SCW1r", 7813 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7814 "RX_X1_CONTROL1_SCW1", 7815 NULL, 7816 #endif 7817 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7818 0xa0b0, /* 41136 */ 7819 0, 7820 #endif 7821 }, 7822 { 7823 BCMI_TSCE_XGXS_RX_X1_SCW2r, 7824 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7825 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 7826 BCMI_TSCE_XGXS_RX_X1_SCW2r_fields, 7827 #else 7828 0, 7829 #endif 7830 #endif 7831 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7832 PHYMOD_SYMBOL_FLAG_REGISTER, 7833 "RX_X1_SCW2r", 7834 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7835 "RX_X1_CONTROL1_SCW2", 7836 NULL, 7837 #endif 7838 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7839 0xc0d0, /* 49360 */ 7840 0, 7841 #endif 7842 }, 7843 { 7844 BCMI_TSCE_XGXS_RX_X1_SCW3r, 7845 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7846 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 7847 BCMI_TSCE_XGXS_RX_X1_SCW3r_fields, 7848 #else 7849 0, 7850 #endif 7851 #endif 7852 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7853 PHYMOD_SYMBOL_FLAG_REGISTER, 7854 "RX_X1_SCW3r", 7855 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7856 "RX_X1_CONTROL1_SCW3", 7857 NULL, 7858 #endif 7859 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7860 0xe070, /* 57456 */ 7861 0, 7862 #endif 7863 }, 7864 { 7865 BCMI_TSCE_XGXS_RX_X1_SCW4r, 7866 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7867 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 7868 BCMI_TSCE_XGXS_RX_X1_SCW4r_fields, 7869 #else 7870 0, 7871 #endif 7872 #endif 7873 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7874 PHYMOD_SYMBOL_FLAG_REGISTER, 7875 "RX_X1_SCW4r", 7876 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7877 "RX_X1_CONTROL1_SCW4", 7878 NULL, 7879 #endif 7880 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7881 0x1, /* 1 */ 7882 0, 7883 #endif 7884 }, 7885 { 7886 BCMI_TSCE_XGXS_RX_X1_SCW0_MASKr, 7887 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7888 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 7889 BCMI_TSCE_XGXS_RX_X1_SCW0_MASKr_fields, 7890 #else 7891 0, 7892 #endif 7893 #endif 7894 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7895 PHYMOD_SYMBOL_FLAG_REGISTER, 7896 "RX_X1_SCW0_MASKr", 7897 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7898 "RX_X1_CONTROL1_SCW0_MASK", 7899 NULL, 7900 #endif 7901 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7902 0xf0f0, /* 61680 */ 7903 0, 7904 #endif 7905 }, 7906 { 7907 BCMI_TSCE_XGXS_RX_X1_SCW1_MASKr, 7908 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7909 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 7910 BCMI_TSCE_XGXS_RX_X1_SCW1_MASKr_fields, 7911 #else 7912 0, 7913 #endif 7914 #endif 7915 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7916 PHYMOD_SYMBOL_FLAG_REGISTER, 7917 "RX_X1_SCW1_MASKr", 7918 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7919 "RX_X1_CONTROL1_SCW1_MASK", 7920 NULL, 7921 #endif 7922 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7923 0xf0f0, /* 61680 */ 7924 0, 7925 #endif 7926 }, 7927 { 7928 BCMI_TSCE_XGXS_RX_X1_SCW2_MASKr, 7929 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7930 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 7931 BCMI_TSCE_XGXS_RX_X1_SCW2_MASKr_fields, 7932 #else 7933 0, 7934 #endif 7935 #endif 7936 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7937 PHYMOD_SYMBOL_FLAG_REGISTER, 7938 "RX_X1_SCW2_MASKr", 7939 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7940 "RX_X1_CONTROL1_SCW2_MASK", 7941 NULL, 7942 #endif 7943 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7944 0xf0f0, /* 61680 */ 7945 0, 7946 #endif 7947 }, 7948 { 7949 BCMI_TSCE_XGXS_RX_X1_SCW3_MASKr, 7950 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7951 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 7952 BCMI_TSCE_XGXS_RX_X1_SCW3_MASKr_fields, 7953 #else 7954 0, 7955 #endif 7956 #endif 7957 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7958 PHYMOD_SYMBOL_FLAG_REGISTER, 7959 "RX_X1_SCW3_MASKr", 7960 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7961 "RX_X1_CONTROL1_SCW3_MASK", 7962 NULL, 7963 #endif 7964 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7965 0xf0f0, /* 61680 */ 7966 0, 7967 #endif 7968 }, 7969 { 7970 BCMI_TSCE_XGXS_RX_X1_SCW4_MASKr, 7971 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7972 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 7973 BCMI_TSCE_XGXS_RX_X1_SCW4_MASKr_fields, 7974 #else 7975 0, 7976 #endif 7977 #endif 7978 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7979 PHYMOD_SYMBOL_FLAG_REGISTER, 7980 "RX_X1_SCW4_MASKr", 7981 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7982 "RX_X1_CONTROL1_SCW4_MASK", 7983 NULL, 7984 #endif 7985 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7986 0x3, /* 3 */ 7987 0, 7988 #endif 7989 }, 7990 { 7991 BCMI_TSCE_XGXS_AN_X1_OUI_UPRr, 7992 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7993 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 7994 BCMI_TSCE_XGXS_AN_X1_OUI_UPRr_fields, 7995 #else 7996 0, 7997 #endif 7998 #endif 7999 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8000 PHYMOD_SYMBOL_FLAG_REGISTER, 8001 "AN_X1_OUI_UPRr", 8002 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8003 "AN_X1_CONTROL_OUI_UPPER", 8004 NULL, 8005 #endif 8006 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8007 0x0, /* 0 */ 8008 0, 8009 #endif 8010 }, 8011 { 8012 BCMI_TSCE_XGXS_AN_X1_OUI_LWRr, 8013 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8014 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 8015 BCMI_TSCE_XGXS_AN_X1_OUI_LWRr_fields, 8016 #else 8017 0, 8018 #endif 8019 #endif 8020 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8021 PHYMOD_SYMBOL_FLAG_REGISTER, 8022 "AN_X1_OUI_LWRr", 8023 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8024 "AN_X1_CONTROL_OUI_LOWER", 8025 NULL, 8026 #endif 8027 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8028 0x0, /* 0 */ 8029 0, 8030 #endif 8031 }, 8032 { 8033 BCMI_TSCE_XGXS_AN_X1_BAM_SPD_PRI_5_0r, 8034 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8035 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 8036 BCMI_TSCE_XGXS_AN_X1_BAM_SPD_PRI_5_0r_fields, 8037 #else 8038 0, 8039 #endif 8040 #endif 8041 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8042 PHYMOD_SYMBOL_FLAG_REGISTER, 8043 "AN_X1_BAM_SPD_PRI_5_0r", 8044 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8045 "AN_X1_CONTROL_BAM_SPEED_PRI_5_0", 8046 NULL, 8047 #endif 8048 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8049 0x0, /* 0 */ 8050 0, 8051 #endif 8052 }, 8053 { 8054 BCMI_TSCE_XGXS_AN_X1_BAM_SPD_PRI_11_6r, 8055 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8056 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 8057 BCMI_TSCE_XGXS_AN_X1_BAM_SPD_PRI_11_6r_fields, 8058 #else 8059 0, 8060 #endif 8061 #endif 8062 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8063 PHYMOD_SYMBOL_FLAG_REGISTER, 8064 "AN_X1_BAM_SPD_PRI_11_6r", 8065 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8066 "AN_X1_CONTROL_BAM_SPEED_PRI_11_6", 8067 NULL, 8068 #endif 8069 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8070 0x0, /* 0 */ 8071 0, 8072 #endif 8073 }, 8074 { 8075 BCMI_TSCE_XGXS_AN_X1_BAM_SPD_PRI_17_12r, 8076 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8077 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 8078 BCMI_TSCE_XGXS_AN_X1_BAM_SPD_PRI_17_12r_fields, 8079 #else 8080 0, 8081 #endif 8082 #endif 8083 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8084 PHYMOD_SYMBOL_FLAG_REGISTER, 8085 "AN_X1_BAM_SPD_PRI_17_12r", 8086 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8087 "AN_X1_CONTROL_BAM_SPEED_PRI_17_12", 8088 NULL, 8089 #endif 8090 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8091 0x0, /* 0 */ 8092 0, 8093 #endif 8094 }, 8095 { 8096 BCMI_TSCE_XGXS_AN_X1_BAM_SPD_PRI_23_18r, 8097 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8098 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 8099 BCMI_TSCE_XGXS_AN_X1_BAM_SPD_PRI_23_18r_fields, 8100 #else 8101 0, 8102 #endif 8103 #endif 8104 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8105 PHYMOD_SYMBOL_FLAG_REGISTER, 8106 "AN_X1_BAM_SPD_PRI_23_18r", 8107 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8108 "AN_X1_CONTROL_BAM_SPEED_PRI_23_18", 8109 NULL, 8110 #endif 8111 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8112 0x0, /* 0 */ 8113 0, 8114 #endif 8115 }, 8116 { 8117 BCMI_TSCE_XGXS_AN_X1_BAM_SPD_PRI_29_24r, 8118 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8119 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 8120 BCMI_TSCE_XGXS_AN_X1_BAM_SPD_PRI_29_24r_fields, 8121 #else 8122 0, 8123 #endif 8124 #endif 8125 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8126 PHYMOD_SYMBOL_FLAG_REGISTER, 8127 "AN_X1_BAM_SPD_PRI_29_24r", 8128 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8129 "AN_X1_CONTROL_BAM_SPEED_PRI_29_24", 8130 NULL, 8131 #endif 8132 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8133 0x0, /* 0 */ 8134 0, 8135 #endif 8136 }, 8137 { 8138 BCMI_TSCE_XGXS_AN_X1_BAM_SPD_PRI_35_30r, 8139 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8140 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 8141 BCMI_TSCE_XGXS_AN_X1_BAM_SPD_PRI_35_30r_fields, 8142 #else 8143 0, 8144 #endif 8145 #endif 8146 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8147 PHYMOD_SYMBOL_FLAG_REGISTER, 8148 "AN_X1_BAM_SPD_PRI_35_30r", 8149 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8150 "AN_X1_CONTROL_BAM_SPEED_PRI_35_30", 8151 NULL, 8152 #endif 8153 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8154 0x0, /* 0 */ 8155 0, 8156 #endif 8157 }, 8158 { 8159 BCMI_TSCE_XGXS_AN_X1_CFG_CTLr, 8160 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8161 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 8162 BCMI_TSCE_XGXS_AN_X1_CFG_CTLr_fields, 8163 #else 8164 0, 8165 #endif 8166 #endif 8167 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8168 PHYMOD_SYMBOL_FLAG_REGISTER, 8169 "AN_X1_CFG_CTLr", 8170 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8171 "AN_X1_CONTROL_CONFIG_CONTROL", 8172 NULL, 8173 #endif 8174 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8175 0x0, /* 0 */ 8176 0, 8177 #endif 8178 }, 8179 { 8180 BCMI_TSCE_XGXS_AN_X1_CL37_RESTARTr, 8181 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8182 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 8183 BCMI_TSCE_XGXS_AN_X1_CL37_RESTARTr_fields, 8184 #else 8185 0, 8186 #endif 8187 #endif 8188 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8189 PHYMOD_SYMBOL_FLAG_REGISTER, 8190 "AN_X1_CL37_RESTARTr", 8191 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8192 "AN_X1_TIMERS_CL37_RESTART", 8193 NULL, 8194 #endif 8195 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8196 0x0, /* 0 */ 8197 0, 8198 #endif 8199 }, 8200 { 8201 BCMI_TSCE_XGXS_AN_X1_CL37_ACKr, 8202 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8203 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 8204 BCMI_TSCE_XGXS_AN_X1_CL37_ACKr_fields, 8205 #else 8206 0, 8207 #endif 8208 #endif 8209 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8210 PHYMOD_SYMBOL_FLAG_REGISTER, 8211 "AN_X1_CL37_ACKr", 8212 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8213 "AN_X1_TIMERS_CL37_ACK", 8214 NULL, 8215 #endif 8216 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8217 0x0, /* 0 */ 8218 0, 8219 #endif 8220 }, 8221 { 8222 BCMI_TSCE_XGXS_AN_X1_CL37_ERRr, 8223 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8224 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 8225 BCMI_TSCE_XGXS_AN_X1_CL37_ERRr_fields, 8226 #else 8227 0, 8228 #endif 8229 #endif 8230 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8231 PHYMOD_SYMBOL_FLAG_REGISTER, 8232 "AN_X1_CL37_ERRr", 8233 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8234 "AN_X1_TIMERS_CL37_ERROR", 8235 NULL, 8236 #endif 8237 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8238 0x0, /* 0 */ 8239 0, 8240 #endif 8241 }, 8242 { 8243 BCMI_TSCE_XGXS_AN_X1_CL73_BRK_LNKr, 8244 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8245 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 8246 BCMI_TSCE_XGXS_AN_X1_CL73_BRK_LNKr_fields, 8247 #else 8248 0, 8249 #endif 8250 #endif 8251 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8252 PHYMOD_SYMBOL_FLAG_REGISTER, 8253 "AN_X1_CL73_BRK_LNKr", 8254 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8255 "AN_X1_TIMERS_CL73_BREAK_LINK", 8256 NULL, 8257 #endif 8258 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8259 0x0, /* 0 */ 8260 0, 8261 #endif 8262 }, 8263 { 8264 BCMI_TSCE_XGXS_AN_X1_CL73_ERRr, 8265 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8266 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 8267 BCMI_TSCE_XGXS_AN_X1_CL73_ERRr_fields, 8268 #else 8269 0, 8270 #endif 8271 #endif 8272 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8273 PHYMOD_SYMBOL_FLAG_REGISTER, 8274 "AN_X1_CL73_ERRr", 8275 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8276 "AN_X1_TIMERS_CL73_ERROR", 8277 NULL, 8278 #endif 8279 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8280 0x0, /* 0 */ 8281 0, 8282 #endif 8283 }, 8284 { 8285 BCMI_TSCE_XGXS_AN_X1_CL73_DME_LOCKr, 8286 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8287 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 8288 BCMI_TSCE_XGXS_AN_X1_CL73_DME_LOCKr_fields, 8289 #else 8290 0, 8291 #endif 8292 #endif 8293 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8294 PHYMOD_SYMBOL_FLAG_REGISTER, 8295 "AN_X1_CL73_DME_LOCKr", 8296 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8297 "AN_X1_TIMERS_CL73_DME_LOCK", 8298 NULL, 8299 #endif 8300 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8301 0x0, /* 0 */ 8302 0, 8303 #endif 8304 }, 8305 { 8306 BCMI_TSCE_XGXS_AN_X1_LNK_UPr, 8307 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8308 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 8309 BCMI_TSCE_XGXS_AN_X1_LNK_UPr_fields, 8310 #else 8311 0, 8312 #endif 8313 #endif 8314 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8315 PHYMOD_SYMBOL_FLAG_REGISTER, 8316 "AN_X1_LNK_UPr", 8317 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8318 "AN_X1_TIMERS_LINK_UP", 8319 NULL, 8320 #endif 8321 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8322 0x0, /* 0 */ 8323 0, 8324 #endif 8325 }, 8326 { 8327 BCMI_TSCE_XGXS_AN_X1_LNK_FAIL_INHBT_TMR_CL72r, 8328 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8329 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 8330 BCMI_TSCE_XGXS_AN_X1_LNK_FAIL_INHBT_TMR_CL72r_fields, 8331 #else 8332 0, 8333 #endif 8334 #endif 8335 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8336 PHYMOD_SYMBOL_FLAG_REGISTER, 8337 "AN_X1_LNK_FAIL_INHBT_TMR_CL72r", 8338 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8339 "AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_CL72", 8340 NULL, 8341 #endif 8342 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8343 0x0, /* 0 */ 8344 0, 8345 #endif 8346 }, 8347 { 8348 BCMI_TSCE_XGXS_AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72r, 8349 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8350 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 8351 BCMI_TSCE_XGXS_AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72r_fields, 8352 #else 8353 0, 8354 #endif 8355 #endif 8356 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8357 PHYMOD_SYMBOL_FLAG_REGISTER, 8358 "AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72r", 8359 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8360 "AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_NOT_CL72", 8361 NULL, 8362 #endif 8363 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8364 0x0, /* 0 */ 8365 0, 8366 #endif 8367 }, 8368 { 8369 BCMI_TSCE_XGXS_AN_X1_PD_SD_TMRr, 8370 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8371 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 8372 BCMI_TSCE_XGXS_AN_X1_PD_SD_TMRr_fields, 8373 #else 8374 0, 8375 #endif 8376 #endif 8377 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8378 PHYMOD_SYMBOL_FLAG_REGISTER, 8379 "AN_X1_PD_SD_TMRr", 8380 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8381 "AN_X1_TIMERS_PD_SD_TIMER", 8382 NULL, 8383 #endif 8384 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8385 0x0, /* 0 */ 8386 0, 8387 #endif 8388 }, 8389 { 8390 BCMI_TSCE_XGXS_AN_X1_CL37_SYNC_STS_FILTER_TMRr, 8391 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8392 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 8393 BCMI_TSCE_XGXS_AN_X1_CL37_SYNC_STS_FILTER_TMRr_fields, 8394 #else 8395 0, 8396 #endif 8397 #endif 8398 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8399 PHYMOD_SYMBOL_FLAG_REGISTER, 8400 "AN_X1_CL37_SYNC_STS_FILTER_TMRr", 8401 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8402 "AN_X1_TIMERS_CL37_SYNC_STATUS_FILTER_TIMER", 8403 NULL, 8404 #endif 8405 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8406 0x2, /* 2 */ 8407 0, 8408 #endif 8409 }, 8410 { 8411 BCMI_TSCE_XGXS_AN_X1_PD_TO_CL37_LNK_WAIT_TMRr, 8412 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8413 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 8414 BCMI_TSCE_XGXS_AN_X1_PD_TO_CL37_LNK_WAIT_TMRr_fields, 8415 #else 8416 0, 8417 #endif 8418 #endif 8419 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8420 PHYMOD_SYMBOL_FLAG_REGISTER, 8421 "AN_X1_PD_TO_CL37_LNK_WAIT_TMRr", 8422 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8423 "AN_X1_TIMERS_PD_TO_CL37_LINK_WAIT_TIMER", 8424 NULL, 8425 #endif 8426 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8427 0x6b, /* 107 */ 8428 0, 8429 #endif 8430 }, 8431 { 8432 BCMI_TSCE_XGXS_AN_X1_IGNORE_LNK_TMRr, 8433 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8434 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 8435 BCMI_TSCE_XGXS_AN_X1_IGNORE_LNK_TMRr_fields, 8436 #else 8437 0, 8438 #endif 8439 #endif 8440 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8441 PHYMOD_SYMBOL_FLAG_REGISTER, 8442 "AN_X1_IGNORE_LNK_TMRr", 8443 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8444 "AN_X1_TIMERS_IGNORE_LINK_TIMER", 8445 NULL, 8446 #endif 8447 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8448 0x0, /* 0 */ 8449 0, 8450 #endif 8451 }, 8452 { 8453 BCMI_TSCE_XGXS_AN_X1_DME_PAGE_TMRr, 8454 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8455 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 8456 BCMI_TSCE_XGXS_AN_X1_DME_PAGE_TMRr_fields, 8457 #else 8458 0, 8459 #endif 8460 #endif 8461 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8462 PHYMOD_SYMBOL_FLAG_REGISTER, 8463 "AN_X1_DME_PAGE_TMRr", 8464 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8465 "AN_X1_TIMERS_DME_PAGE_TIMER", 8466 NULL, 8467 #endif 8468 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8469 0x3b5f, /* 15199 */ 8470 0, 8471 #endif 8472 }, 8473 { 8474 BCMI_TSCE_XGXS_AN_X1_SGMII_CL73_TMR_TYPEr, 8475 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8476 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 8477 BCMI_TSCE_XGXS_AN_X1_SGMII_CL73_TMR_TYPEr_fields, 8478 #else 8479 0, 8480 #endif 8481 #endif 8482 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8483 PHYMOD_SYMBOL_FLAG_REGISTER, 8484 "AN_X1_SGMII_CL73_TMR_TYPEr", 8485 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8486 "AN_X1_TIMERS_SGMII_CL73_TIMER_TYPE", 8487 NULL, 8488 #endif 8489 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8490 0x6b, /* 107 */ 8491 0, 8492 #endif 8493 }, 8494 { 8495 BCMI_TSCE_XGXS_SC_X1_PLL_LOCK_TMRr, 8496 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8497 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 8498 BCMI_TSCE_XGXS_SC_X1_PLL_LOCK_TMRr_fields, 8499 #else 8500 0, 8501 #endif 8502 #endif 8503 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8504 PHYMOD_SYMBOL_FLAG_REGISTER, 8505 "SC_X1_PLL_LOCK_TMRr", 8506 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8507 "SC_X1_CONTROL_PLL_LOCK_TIMER", 8508 NULL, 8509 #endif 8510 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8511 0x0, /* 0 */ 8512 0, 8513 #endif 8514 }, 8515 { 8516 BCMI_TSCE_XGXS_SC_X1_PMD_LOCK_TMRr, 8517 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8518 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 8519 BCMI_TSCE_XGXS_SC_X1_PMD_LOCK_TMRr_fields, 8520 #else 8521 0, 8522 #endif 8523 #endif 8524 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8525 PHYMOD_SYMBOL_FLAG_REGISTER, 8526 "SC_X1_PMD_LOCK_TMRr", 8527 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8528 "SC_X1_CONTROL_PMD_LOCK_TIMER", 8529 NULL, 8530 #endif 8531 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8532 0x0, /* 0 */ 8533 0, 8534 #endif 8535 }, 8536 { 8537 BCMI_TSCE_XGXS_SC_X1_PIPE_RST_CNTr, 8538 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8539 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 8540 BCMI_TSCE_XGXS_SC_X1_PIPE_RST_CNTr_fields, 8541 #else 8542 0, 8543 #endif 8544 #endif 8545 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8546 PHYMOD_SYMBOL_FLAG_REGISTER, 8547 "SC_X1_PIPE_RST_CNTr", 8548 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8549 "SC_X1_CONTROL_PIPELINE_RESET_COUNT", 8550 NULL, 8551 #endif 8552 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8553 0xff, /* 255 */ 8554 0, 8555 #endif 8556 }, 8557 { 8558 BCMI_TSCE_XGXS_SC_X1_TX_RST_CNTr, 8559 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8560 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 8561 BCMI_TSCE_XGXS_SC_X1_TX_RST_CNTr_fields, 8562 #else 8563 0, 8564 #endif 8565 #endif 8566 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8567 PHYMOD_SYMBOL_FLAG_REGISTER, 8568 "SC_X1_TX_RST_CNTr", 8569 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8570 "SC_X1_CONTROL_TX_RESET_COUNT", 8571 NULL, 8572 #endif 8573 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8574 0x2, /* 2 */ 8575 0, 8576 #endif 8577 }, 8578 { 8579 BCMI_TSCE_XGXS_SC_X1_STSr, 8580 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8581 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 8582 BCMI_TSCE_XGXS_SC_X1_STSr_fields, 8583 #else 8584 0, 8585 #endif 8586 #endif 8587 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8588 PHYMOD_SYMBOL_FLAG_REGISTER, 8589 "SC_X1_STSr", 8590 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8591 "SC_X1_CONTROL_STATUS", 8592 NULL, 8593 #endif 8594 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8595 0x0, /* 0 */ 8596 0, 8597 #endif 8598 }, 8599 { 8600 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR0_SPDr, 8601 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8602 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 8603 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR0_SPDr_fields, 8604 #else 8605 0, 8606 #endif 8607 #endif 8608 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8609 PHYMOD_SYMBOL_FLAG_REGISTER, 8610 "SC_X1_SPD_OVRR0_SPDr", 8611 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8612 "SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED", 8613 NULL, 8614 #endif 8615 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8616 0xff00, /* 65280 */ 8617 0, 8618 #endif 8619 }, 8620 { 8621 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR0_0r, 8622 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8623 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 8624 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR0_0r_fields, 8625 #else 8626 0, 8627 #endif 8628 #endif 8629 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8630 PHYMOD_SYMBOL_FLAG_REGISTER, 8631 "SC_X1_SPD_OVRR0_0r", 8632 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8633 "SC_X1_SPEED_OVERRIDE0_OVERRIDE_0", 8634 NULL, 8635 #endif 8636 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8637 0x0, /* 0 */ 8638 0, 8639 #endif 8640 }, 8641 { 8642 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR0_1r, 8643 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8644 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 8645 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR0_1r_fields, 8646 #else 8647 0, 8648 #endif 8649 #endif 8650 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8651 PHYMOD_SYMBOL_FLAG_REGISTER, 8652 "SC_X1_SPD_OVRR0_1r", 8653 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8654 "SC_X1_SPEED_OVERRIDE0_OVERRIDE_1", 8655 NULL, 8656 #endif 8657 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8658 0x0, /* 0 */ 8659 0, 8660 #endif 8661 }, 8662 { 8663 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR0_2r, 8664 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8665 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 8666 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR0_2r_fields, 8667 #else 8668 0, 8669 #endif 8670 #endif 8671 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8672 PHYMOD_SYMBOL_FLAG_REGISTER, 8673 "SC_X1_SPD_OVRR0_2r", 8674 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8675 "SC_X1_SPEED_OVERRIDE0_OVERRIDE_2", 8676 NULL, 8677 #endif 8678 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8679 0x400, /* 1024 */ 8680 0, 8681 #endif 8682 }, 8683 { 8684 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR0_3r, 8685 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8686 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 8687 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR0_3r_fields, 8688 #else 8689 0, 8690 #endif 8691 #endif 8692 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8693 PHYMOD_SYMBOL_FLAG_REGISTER, 8694 "SC_X1_SPD_OVRR0_3r", 8695 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8696 "SC_X1_SPEED_OVERRIDE0_OVERRIDE_3", 8697 NULL, 8698 #endif 8699 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8700 0x0, /* 0 */ 8701 0, 8702 #endif 8703 }, 8704 { 8705 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR0_4r, 8706 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8707 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 8708 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR0_4r_fields, 8709 #else 8710 0, 8711 #endif 8712 #endif 8713 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8714 PHYMOD_SYMBOL_FLAG_REGISTER, 8715 "SC_X1_SPD_OVRR0_4r", 8716 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8717 "SC_X1_SPEED_OVERRIDE0_OVERRIDE_4", 8718 NULL, 8719 #endif 8720 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8721 0x0, /* 0 */ 8722 0, 8723 #endif 8724 }, 8725 { 8726 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR0_5r, 8727 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8728 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 8729 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR0_5r_fields, 8730 #else 8731 0, 8732 #endif 8733 #endif 8734 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8735 PHYMOD_SYMBOL_FLAG_REGISTER, 8736 "SC_X1_SPD_OVRR0_5r", 8737 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8738 "SC_X1_SPEED_OVERRIDE0_OVERRIDE_5", 8739 NULL, 8740 #endif 8741 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8742 0x0, /* 0 */ 8743 0, 8744 #endif 8745 }, 8746 { 8747 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR0_6r, 8748 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8749 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 8750 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR0_6r_fields, 8751 #else 8752 0, 8753 #endif 8754 #endif 8755 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8756 PHYMOD_SYMBOL_FLAG_REGISTER, 8757 "SC_X1_SPD_OVRR0_6r", 8758 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8759 "SC_X1_SPEED_OVERRIDE0_OVERRIDE_6", 8760 NULL, 8761 #endif 8762 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8763 0x0, /* 0 */ 8764 0, 8765 #endif 8766 }, 8767 { 8768 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR0_7r, 8769 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8770 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 8771 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR0_7r_fields, 8772 #else 8773 0, 8774 #endif 8775 #endif 8776 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8777 PHYMOD_SYMBOL_FLAG_REGISTER, 8778 "SC_X1_SPD_OVRR0_7r", 8779 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8780 "SC_X1_SPEED_OVERRIDE0_OVERRIDE_7", 8781 NULL, 8782 #endif 8783 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8784 0x0, /* 0 */ 8785 0, 8786 #endif 8787 }, 8788 { 8789 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR0_8r, 8790 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8791 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 8792 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR0_8r_fields, 8793 #else 8794 0, 8795 #endif 8796 #endif 8797 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8798 PHYMOD_SYMBOL_FLAG_REGISTER, 8799 "SC_X1_SPD_OVRR0_8r", 8800 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8801 "SC_X1_SPEED_OVERRIDE0_OVERRIDE_8", 8802 NULL, 8803 #endif 8804 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8805 0x0, /* 0 */ 8806 0, 8807 #endif 8808 }, 8809 { 8810 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR1_SPDr, 8811 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8812 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 8813 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR1_SPDr_fields, 8814 #else 8815 0, 8816 #endif 8817 #endif 8818 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8819 PHYMOD_SYMBOL_FLAG_REGISTER, 8820 "SC_X1_SPD_OVRR1_SPDr", 8821 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8822 "SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED", 8823 NULL, 8824 #endif 8825 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8826 0xff00, /* 65280 */ 8827 0, 8828 #endif 8829 }, 8830 { 8831 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR1_0r, 8832 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8833 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 8834 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR1_0r_fields, 8835 #else 8836 0, 8837 #endif 8838 #endif 8839 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8840 PHYMOD_SYMBOL_FLAG_REGISTER, 8841 "SC_X1_SPD_OVRR1_0r", 8842 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8843 "SC_X1_SPEED_OVERRIDE1_OVERRIDE_0", 8844 NULL, 8845 #endif 8846 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8847 0x0, /* 0 */ 8848 0, 8849 #endif 8850 }, 8851 { 8852 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR1_1r, 8853 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8854 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 8855 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR1_1r_fields, 8856 #else 8857 0, 8858 #endif 8859 #endif 8860 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8861 PHYMOD_SYMBOL_FLAG_REGISTER, 8862 "SC_X1_SPD_OVRR1_1r", 8863 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8864 "SC_X1_SPEED_OVERRIDE1_OVERRIDE_1", 8865 NULL, 8866 #endif 8867 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8868 0x0, /* 0 */ 8869 0, 8870 #endif 8871 }, 8872 { 8873 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR1_2r, 8874 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8875 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 8876 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR1_2r_fields, 8877 #else 8878 0, 8879 #endif 8880 #endif 8881 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8882 PHYMOD_SYMBOL_FLAG_REGISTER, 8883 "SC_X1_SPD_OVRR1_2r", 8884 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8885 "SC_X1_SPEED_OVERRIDE1_OVERRIDE_2", 8886 NULL, 8887 #endif 8888 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8889 0x400, /* 1024 */ 8890 0, 8891 #endif 8892 }, 8893 { 8894 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR1_3r, 8895 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8896 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 8897 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR1_3r_fields, 8898 #else 8899 0, 8900 #endif 8901 #endif 8902 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8903 PHYMOD_SYMBOL_FLAG_REGISTER, 8904 "SC_X1_SPD_OVRR1_3r", 8905 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8906 "SC_X1_SPEED_OVERRIDE1_OVERRIDE_3", 8907 NULL, 8908 #endif 8909 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8910 0x0, /* 0 */ 8911 0, 8912 #endif 8913 }, 8914 { 8915 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR1_4r, 8916 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8917 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 8918 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR1_4r_fields, 8919 #else 8920 0, 8921 #endif 8922 #endif 8923 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8924 PHYMOD_SYMBOL_FLAG_REGISTER, 8925 "SC_X1_SPD_OVRR1_4r", 8926 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8927 "SC_X1_SPEED_OVERRIDE1_OVERRIDE_4", 8928 NULL, 8929 #endif 8930 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8931 0x0, /* 0 */ 8932 0, 8933 #endif 8934 }, 8935 { 8936 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR1_5r, 8937 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8938 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 8939 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR1_5r_fields, 8940 #else 8941 0, 8942 #endif 8943 #endif 8944 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8945 PHYMOD_SYMBOL_FLAG_REGISTER, 8946 "SC_X1_SPD_OVRR1_5r", 8947 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8948 "SC_X1_SPEED_OVERRIDE1_OVERRIDE_5", 8949 NULL, 8950 #endif 8951 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8952 0x0, /* 0 */ 8953 0, 8954 #endif 8955 }, 8956 { 8957 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR1_6r, 8958 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8959 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 8960 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR1_6r_fields, 8961 #else 8962 0, 8963 #endif 8964 #endif 8965 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8966 PHYMOD_SYMBOL_FLAG_REGISTER, 8967 "SC_X1_SPD_OVRR1_6r", 8968 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8969 "SC_X1_SPEED_OVERRIDE1_OVERRIDE_6", 8970 NULL, 8971 #endif 8972 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8973 0x0, /* 0 */ 8974 0, 8975 #endif 8976 }, 8977 { 8978 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR1_7r, 8979 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8980 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 8981 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR1_7r_fields, 8982 #else 8983 0, 8984 #endif 8985 #endif 8986 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8987 PHYMOD_SYMBOL_FLAG_REGISTER, 8988 "SC_X1_SPD_OVRR1_7r", 8989 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8990 "SC_X1_SPEED_OVERRIDE1_OVERRIDE_7", 8991 NULL, 8992 #endif 8993 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8994 0x0, /* 0 */ 8995 0, 8996 #endif 8997 }, 8998 { 8999 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR1_8r, 9000 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9001 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 9002 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR1_8r_fields, 9003 #else 9004 0, 9005 #endif 9006 #endif 9007 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9008 PHYMOD_SYMBOL_FLAG_REGISTER, 9009 "SC_X1_SPD_OVRR1_8r", 9010 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9011 "SC_X1_SPEED_OVERRIDE1_OVERRIDE_8", 9012 NULL, 9013 #endif 9014 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9015 0x0, /* 0 */ 9016 0, 9017 #endif 9018 }, 9019 { 9020 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR2_SPDr, 9021 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9022 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 9023 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR2_SPDr_fields, 9024 #else 9025 0, 9026 #endif 9027 #endif 9028 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9029 PHYMOD_SYMBOL_FLAG_REGISTER, 9030 "SC_X1_SPD_OVRR2_SPDr", 9031 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9032 "SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED", 9033 NULL, 9034 #endif 9035 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9036 0xff00, /* 65280 */ 9037 0, 9038 #endif 9039 }, 9040 { 9041 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR2_0r, 9042 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9043 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 9044 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR2_0r_fields, 9045 #else 9046 0, 9047 #endif 9048 #endif 9049 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9050 PHYMOD_SYMBOL_FLAG_REGISTER, 9051 "SC_X1_SPD_OVRR2_0r", 9052 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9053 "SC_X1_SPEED_OVERRIDE2_OVERRIDE_0", 9054 NULL, 9055 #endif 9056 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9057 0x0, /* 0 */ 9058 0, 9059 #endif 9060 }, 9061 { 9062 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR2_1r, 9063 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9064 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 9065 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR2_1r_fields, 9066 #else 9067 0, 9068 #endif 9069 #endif 9070 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9071 PHYMOD_SYMBOL_FLAG_REGISTER, 9072 "SC_X1_SPD_OVRR2_1r", 9073 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9074 "SC_X1_SPEED_OVERRIDE2_OVERRIDE_1", 9075 NULL, 9076 #endif 9077 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9078 0x0, /* 0 */ 9079 0, 9080 #endif 9081 }, 9082 { 9083 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR2_2r, 9084 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9085 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 9086 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR2_2r_fields, 9087 #else 9088 0, 9089 #endif 9090 #endif 9091 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9092 PHYMOD_SYMBOL_FLAG_REGISTER, 9093 "SC_X1_SPD_OVRR2_2r", 9094 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9095 "SC_X1_SPEED_OVERRIDE2_OVERRIDE_2", 9096 NULL, 9097 #endif 9098 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9099 0x400, /* 1024 */ 9100 0, 9101 #endif 9102 }, 9103 { 9104 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR2_3r, 9105 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9106 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 9107 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR2_3r_fields, 9108 #else 9109 0, 9110 #endif 9111 #endif 9112 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9113 PHYMOD_SYMBOL_FLAG_REGISTER, 9114 "SC_X1_SPD_OVRR2_3r", 9115 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9116 "SC_X1_SPEED_OVERRIDE2_OVERRIDE_3", 9117 NULL, 9118 #endif 9119 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9120 0x0, /* 0 */ 9121 0, 9122 #endif 9123 }, 9124 { 9125 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR2_4r, 9126 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9127 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 9128 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR2_4r_fields, 9129 #else 9130 0, 9131 #endif 9132 #endif 9133 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9134 PHYMOD_SYMBOL_FLAG_REGISTER, 9135 "SC_X1_SPD_OVRR2_4r", 9136 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9137 "SC_X1_SPEED_OVERRIDE2_OVERRIDE_4", 9138 NULL, 9139 #endif 9140 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9141 0x0, /* 0 */ 9142 0, 9143 #endif 9144 }, 9145 { 9146 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR2_5r, 9147 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9148 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 9149 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR2_5r_fields, 9150 #else 9151 0, 9152 #endif 9153 #endif 9154 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9155 PHYMOD_SYMBOL_FLAG_REGISTER, 9156 "SC_X1_SPD_OVRR2_5r", 9157 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9158 "SC_X1_SPEED_OVERRIDE2_OVERRIDE_5", 9159 NULL, 9160 #endif 9161 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9162 0x0, /* 0 */ 9163 0, 9164 #endif 9165 }, 9166 { 9167 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR2_6r, 9168 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9169 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 9170 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR2_6r_fields, 9171 #else 9172 0, 9173 #endif 9174 #endif 9175 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9176 PHYMOD_SYMBOL_FLAG_REGISTER, 9177 "SC_X1_SPD_OVRR2_6r", 9178 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9179 "SC_X1_SPEED_OVERRIDE2_OVERRIDE_6", 9180 NULL, 9181 #endif 9182 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9183 0x0, /* 0 */ 9184 0, 9185 #endif 9186 }, 9187 { 9188 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR2_7r, 9189 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9190 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 9191 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR2_7r_fields, 9192 #else 9193 0, 9194 #endif 9195 #endif 9196 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9197 PHYMOD_SYMBOL_FLAG_REGISTER, 9198 "SC_X1_SPD_OVRR2_7r", 9199 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9200 "SC_X1_SPEED_OVERRIDE2_OVERRIDE_7", 9201 NULL, 9202 #endif 9203 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9204 0x0, /* 0 */ 9205 0, 9206 #endif 9207 }, 9208 { 9209 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR2_8r, 9210 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9211 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 9212 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR2_8r_fields, 9213 #else 9214 0, 9215 #endif 9216 #endif 9217 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9218 PHYMOD_SYMBOL_FLAG_REGISTER, 9219 "SC_X1_SPD_OVRR2_8r", 9220 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9221 "SC_X1_SPEED_OVERRIDE2_OVERRIDE_8", 9222 NULL, 9223 #endif 9224 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9225 0x0, /* 0 */ 9226 0, 9227 #endif 9228 }, 9229 { 9230 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR3_SPDr, 9231 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9232 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 9233 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR3_SPDr_fields, 9234 #else 9235 0, 9236 #endif 9237 #endif 9238 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9239 PHYMOD_SYMBOL_FLAG_REGISTER, 9240 "SC_X1_SPD_OVRR3_SPDr", 9241 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9242 "SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED", 9243 NULL, 9244 #endif 9245 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9246 0xff00, /* 65280 */ 9247 0, 9248 #endif 9249 }, 9250 { 9251 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR3_0r, 9252 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9253 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 9254 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR3_0r_fields, 9255 #else 9256 0, 9257 #endif 9258 #endif 9259 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9260 PHYMOD_SYMBOL_FLAG_REGISTER, 9261 "SC_X1_SPD_OVRR3_0r", 9262 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9263 "SC_X1_SPEED_OVERRIDE3_OVERRIDE_0", 9264 NULL, 9265 #endif 9266 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9267 0x0, /* 0 */ 9268 0, 9269 #endif 9270 }, 9271 { 9272 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR3_1r, 9273 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9274 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 9275 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR3_1r_fields, 9276 #else 9277 0, 9278 #endif 9279 #endif 9280 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9281 PHYMOD_SYMBOL_FLAG_REGISTER, 9282 "SC_X1_SPD_OVRR3_1r", 9283 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9284 "SC_X1_SPEED_OVERRIDE3_OVERRIDE_1", 9285 NULL, 9286 #endif 9287 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9288 0x0, /* 0 */ 9289 0, 9290 #endif 9291 }, 9292 { 9293 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR3_2r, 9294 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9295 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 9296 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR3_2r_fields, 9297 #else 9298 0, 9299 #endif 9300 #endif 9301 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9302 PHYMOD_SYMBOL_FLAG_REGISTER, 9303 "SC_X1_SPD_OVRR3_2r", 9304 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9305 "SC_X1_SPEED_OVERRIDE3_OVERRIDE_2", 9306 NULL, 9307 #endif 9308 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9309 0x400, /* 1024 */ 9310 0, 9311 #endif 9312 }, 9313 { 9314 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR3_3r, 9315 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9316 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 9317 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR3_3r_fields, 9318 #else 9319 0, 9320 #endif 9321 #endif 9322 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9323 PHYMOD_SYMBOL_FLAG_REGISTER, 9324 "SC_X1_SPD_OVRR3_3r", 9325 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9326 "SC_X1_SPEED_OVERRIDE3_OVERRIDE_3", 9327 NULL, 9328 #endif 9329 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9330 0x0, /* 0 */ 9331 0, 9332 #endif 9333 }, 9334 { 9335 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR3_4r, 9336 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9337 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 9338 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR3_4r_fields, 9339 #else 9340 0, 9341 #endif 9342 #endif 9343 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9344 PHYMOD_SYMBOL_FLAG_REGISTER, 9345 "SC_X1_SPD_OVRR3_4r", 9346 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9347 "SC_X1_SPEED_OVERRIDE3_OVERRIDE_4", 9348 NULL, 9349 #endif 9350 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9351 0x0, /* 0 */ 9352 0, 9353 #endif 9354 }, 9355 { 9356 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR3_5r, 9357 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9358 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 9359 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR3_5r_fields, 9360 #else 9361 0, 9362 #endif 9363 #endif 9364 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9365 PHYMOD_SYMBOL_FLAG_REGISTER, 9366 "SC_X1_SPD_OVRR3_5r", 9367 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9368 "SC_X1_SPEED_OVERRIDE3_OVERRIDE_5", 9369 NULL, 9370 #endif 9371 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9372 0x0, /* 0 */ 9373 0, 9374 #endif 9375 }, 9376 { 9377 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR3_6r, 9378 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9379 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 9380 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR3_6r_fields, 9381 #else 9382 0, 9383 #endif 9384 #endif 9385 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9386 PHYMOD_SYMBOL_FLAG_REGISTER, 9387 "SC_X1_SPD_OVRR3_6r", 9388 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9389 "SC_X1_SPEED_OVERRIDE3_OVERRIDE_6", 9390 NULL, 9391 #endif 9392 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9393 0x0, /* 0 */ 9394 0, 9395 #endif 9396 }, 9397 { 9398 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR3_7r, 9399 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9400 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 9401 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR3_7r_fields, 9402 #else 9403 0, 9404 #endif 9405 #endif 9406 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9407 PHYMOD_SYMBOL_FLAG_REGISTER, 9408 "SC_X1_SPD_OVRR3_7r", 9409 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9410 "SC_X1_SPEED_OVERRIDE3_OVERRIDE_7", 9411 NULL, 9412 #endif 9413 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9414 0x0, /* 0 */ 9415 0, 9416 #endif 9417 }, 9418 { 9419 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR3_8r, 9420 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9421 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 9422 BCMI_TSCE_XGXS_SC_X1_SPD_OVRR3_8r_fields, 9423 #else 9424 0, 9425 #endif 9426 #endif 9427 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9428 PHYMOD_SYMBOL_FLAG_REGISTER, 9429 "SC_X1_SPD_OVRR3_8r", 9430 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9431 "SC_X1_SPEED_OVERRIDE3_OVERRIDE_8", 9432 NULL, 9433 #endif 9434 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9435 0x0, /* 0 */ 9436 0, 9437 #endif 9438 }, 9439 { 9440 BCMI_TSCE_XGXS_TX_X2_MLD_SWP_CNTr, 9441 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9442 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 9443 BCMI_TSCE_XGXS_TX_X2_MLD_SWP_CNTr_fields, 9444 #else 9445 0, 9446 #endif 9447 #endif 9448 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9449 PHYMOD_SYMBOL_FLAG_REGISTER, 9450 "TX_X2_MLD_SWP_CNTr", 9451 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9452 "TX_X2_CONTROL0_MLD_SWAP_COUNT", 9453 NULL, 9454 #endif 9455 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9456 0x7ffe, /* 32766 */ 9457 0, 9458 #endif 9459 }, 9460 { 9461 BCMI_TSCE_XGXS_TX_X2_CL48_0r, 9462 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9463 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 9464 BCMI_TSCE_XGXS_TX_X2_CL48_0r_fields, 9465 #else 9466 0, 9467 #endif 9468 #endif 9469 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9470 PHYMOD_SYMBOL_FLAG_REGISTER, 9471 "TX_X2_CL48_0r", 9472 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9473 "TX_X2_CONTROL0_CL48_0", 9474 NULL, 9475 #endif 9476 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9477 0x8000, /* 32768 */ 9478 0, 9479 #endif 9480 }, 9481 { 9482 BCMI_TSCE_XGXS_TX_X2_CL82_0r, 9483 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9484 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 9485 BCMI_TSCE_XGXS_TX_X2_CL82_0r_fields, 9486 #else 9487 0, 9488 #endif 9489 #endif 9490 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9491 PHYMOD_SYMBOL_FLAG_REGISTER, 9492 "TX_X2_CL82_0r", 9493 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9494 "TX_X2_CONTROL0_CL82_0", 9495 NULL, 9496 #endif 9497 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9498 0x70, /* 112 */ 9499 0, 9500 #endif 9501 }, 9502 { 9503 BCMI_TSCE_XGXS_TX_X2_BRCM_MODEr, 9504 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9505 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 9506 BCMI_TSCE_XGXS_TX_X2_BRCM_MODEr_fields, 9507 #else 9508 0, 9509 #endif 9510 #endif 9511 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9512 PHYMOD_SYMBOL_FLAG_REGISTER, 9513 "TX_X2_BRCM_MODEr", 9514 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9515 "TX_X2_CONTROL0_BRCM_MODE", 9516 NULL, 9517 #endif 9518 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9519 0x64, /* 100 */ 9520 0, 9521 #endif 9522 }, 9523 { 9524 BCMI_TSCE_XGXS_TX_X2_CL82_TX_STS0r, 9525 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9526 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 9527 BCMI_TSCE_XGXS_TX_X2_CL82_TX_STS0r_fields, 9528 #else 9529 0, 9530 #endif 9531 #endif 9532 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9533 PHYMOD_SYMBOL_FLAG_REGISTER, 9534 "TX_X2_CL82_TX_STS0r", 9535 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9536 "TX_X2_STATUS0_CL82_TX_STATUS_0", 9537 NULL, 9538 #endif 9539 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9540 0x0, /* 0 */ 9541 0, 9542 #endif 9543 }, 9544 { 9545 BCMI_TSCE_XGXS_RX_X2_QRSVD0r, 9546 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9547 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 9548 BCMI_TSCE_XGXS_RX_X2_QRSVD0r_fields, 9549 #else 9550 0, 9551 #endif 9552 #endif 9553 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9554 PHYMOD_SYMBOL_FLAG_REGISTER, 9555 "RX_X2_QRSVD0r", 9556 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9557 "RX_X2_CONTROL0_QRSVD_0", 9558 NULL, 9559 #endif 9560 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9561 0x0, /* 0 */ 9562 0, 9563 #endif 9564 }, 9565 { 9566 BCMI_TSCE_XGXS_RX_X2_QRSVD1r, 9567 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9568 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 9569 BCMI_TSCE_XGXS_RX_X2_QRSVD1r_fields, 9570 #else 9571 0, 9572 #endif 9573 #endif 9574 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9575 PHYMOD_SYMBOL_FLAG_REGISTER, 9576 "RX_X2_QRSVD1r", 9577 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9578 "RX_X2_CONTROL0_QRSVD_1", 9579 NULL, 9580 #endif 9581 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9582 0x0, /* 0 */ 9583 0, 9584 #endif 9585 }, 9586 { 9587 BCMI_TSCE_XGXS_RX_X2_QRSVD2r, 9588 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9589 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 9590 BCMI_TSCE_XGXS_RX_X2_QRSVD2r_fields, 9591 #else 9592 0, 9593 #endif 9594 #endif 9595 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9596 PHYMOD_SYMBOL_FLAG_REGISTER, 9597 "RX_X2_QRSVD2r", 9598 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9599 "RX_X2_CONTROL0_QRSVD_2", 9600 NULL, 9601 #endif 9602 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9603 0x0, /* 0 */ 9604 0, 9605 #endif 9606 }, 9607 { 9608 BCMI_TSCE_XGXS_RX_X2_MISC0r, 9609 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9610 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 9611 BCMI_TSCE_XGXS_RX_X2_MISC0r_fields, 9612 #else 9613 0, 9614 #endif 9615 #endif 9616 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9617 PHYMOD_SYMBOL_FLAG_REGISTER, 9618 "RX_X2_MISC0r", 9619 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9620 "RX_X2_CONTROL0_MISC_0", 9621 NULL, 9622 #endif 9623 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9624 0x1400, /* 5120 */ 9625 0, 9626 #endif 9627 }, 9628 { 9629 BCMI_TSCE_XGXS_RX_X2_MISC1r, 9630 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9631 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 9632 BCMI_TSCE_XGXS_RX_X2_MISC1r_fields, 9633 #else 9634 0, 9635 #endif 9636 #endif 9637 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9638 PHYMOD_SYMBOL_FLAG_REGISTER, 9639 "RX_X2_MISC1r", 9640 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9641 "RX_X2_CONTROL0_MISC_1", 9642 NULL, 9643 #endif 9644 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9645 0x30f, /* 783 */ 9646 0, 9647 #endif 9648 }, 9649 { 9650 BCMI_TSCE_XGXS_RX_X2_SKEW_STS0r, 9651 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9652 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 9653 BCMI_TSCE_XGXS_RX_X2_SKEW_STS0r_fields, 9654 #else 9655 0, 9656 #endif 9657 #endif 9658 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9659 PHYMOD_SYMBOL_FLAG_REGISTER, 9660 "RX_X2_SKEW_STS0r", 9661 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9662 "RX_X2_STATUS0_SKEW_STATUS_0", 9663 NULL, 9664 #endif 9665 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9666 0x0, /* 0 */ 9667 0, 9668 #endif 9669 }, 9670 { 9671 BCMI_TSCE_XGXS_RX_X2_SKEW_STS1r, 9672 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9673 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 9674 BCMI_TSCE_XGXS_RX_X2_SKEW_STS1r_fields, 9675 #else 9676 0, 9677 #endif 9678 #endif 9679 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9680 PHYMOD_SYMBOL_FLAG_REGISTER, 9681 "RX_X2_SKEW_STS1r", 9682 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9683 "RX_X2_STATUS0_SKEW_STATUS_1", 9684 NULL, 9685 #endif 9686 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9687 0x0, /* 0 */ 9688 0, 9689 #endif 9690 }, 9691 { 9692 BCMI_TSCE_XGXS_CL82_RX_DECR_STSr, 9693 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9694 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 9695 BCMI_TSCE_XGXS_CL82_RX_DECR_STSr_fields, 9696 #else 9697 0, 9698 #endif 9699 #endif 9700 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9701 PHYMOD_SYMBOL_FLAG_REGISTER, 9702 "CL82_RX_DECR_STSr", 9703 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9704 "CL82_RX_DECODER_STATUS", 9705 NULL, 9706 #endif 9707 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9708 0x0, /* 0 */ 9709 0, 9710 #endif 9711 }, 9712 { 9713 BCMI_TSCE_XGXS_CL82_RX_DESKEW_BER_STSr, 9714 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9715 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 9716 BCMI_TSCE_XGXS_CL82_RX_DESKEW_BER_STSr_fields, 9717 #else 9718 0, 9719 #endif 9720 #endif 9721 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9722 PHYMOD_SYMBOL_FLAG_REGISTER, 9723 "CL82_RX_DESKEW_BER_STSr", 9724 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9725 "CL82_RX_DESKEW_BER_STATUS", 9726 NULL, 9727 #endif 9728 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9729 0x0, /* 0 */ 9730 0, 9731 #endif 9732 }, 9733 { 9734 BCMI_TSCE_XGXS_CL82_BER_HO_STSr, 9735 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9736 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 9737 BCMI_TSCE_XGXS_CL82_BER_HO_STSr_fields, 9738 #else 9739 0, 9740 #endif 9741 #endif 9742 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9743 PHYMOD_SYMBOL_FLAG_REGISTER, 9744 "CL82_BER_HO_STSr", 9745 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9746 "CL82_BER_HO_STATUS", 9747 NULL, 9748 #endif 9749 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9750 0x0, /* 0 */ 9751 0, 9752 #endif 9753 }, 9754 { 9755 BCMI_TSCE_XGXS_CL82_PCS_ERRED_BLKS_HOr, 9756 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9757 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 9758 BCMI_TSCE_XGXS_CL82_PCS_ERRED_BLKS_HOr_fields, 9759 #else 9760 0, 9761 #endif 9762 #endif 9763 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9764 PHYMOD_SYMBOL_FLAG_REGISTER, 9765 "CL82_PCS_ERRED_BLKS_HOr", 9766 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9767 "CL82_PCS_ERRORED_BLOCKS_HO", 9768 NULL, 9769 #endif 9770 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9771 0x8000, /* 32768 */ 9772 0, 9773 #endif 9774 }, 9775 { 9776 BCMI_TSCE_XGXS_PMD_X4_CTLr, 9777 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9778 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 9779 BCMI_TSCE_XGXS_PMD_X4_CTLr_fields, 9780 #else 9781 0, 9782 #endif 9783 #endif 9784 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9785 PHYMOD_SYMBOL_FLAG_REGISTER, 9786 "PMD_X4_CTLr", 9787 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9788 "PMD_X4_CONTROL", 9789 NULL, 9790 #endif 9791 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9792 0x0, /* 0 */ 9793 0, 9794 #endif 9795 }, 9796 { 9797 BCMI_TSCE_XGXS_PMD_X4_MODEr, 9798 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9799 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 9800 BCMI_TSCE_XGXS_PMD_X4_MODEr_fields, 9801 #else 9802 0, 9803 #endif 9804 #endif 9805 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9806 PHYMOD_SYMBOL_FLAG_REGISTER, 9807 "PMD_X4_MODEr", 9808 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9809 NULL, 9810 NULL, 9811 #endif 9812 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9813 0x0, /* 0 */ 9814 0, 9815 #endif 9816 }, 9817 { 9818 BCMI_TSCE_XGXS_PMD_X4_STSr, 9819 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9820 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 9821 BCMI_TSCE_XGXS_PMD_X4_STSr_fields, 9822 #else 9823 0, 9824 #endif 9825 #endif 9826 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9827 PHYMOD_SYMBOL_FLAG_REGISTER, 9828 "PMD_X4_STSr", 9829 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9830 "PMD_X4_STATUS", 9831 NULL, 9832 #endif 9833 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9834 0x0, /* 0 */ 9835 0, 9836 #endif 9837 }, 9838 { 9839 BCMI_TSCE_XGXS_PMD_X4_LATCH_STSr, 9840 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9841 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 9842 BCMI_TSCE_XGXS_PMD_X4_LATCH_STSr_fields, 9843 #else 9844 0, 9845 #endif 9846 #endif 9847 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9848 PHYMOD_SYMBOL_FLAG_REGISTER, 9849 "PMD_X4_LATCH_STSr", 9850 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9851 "PMD_X4_LATCH_STATUS", 9852 NULL, 9853 #endif 9854 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9855 0x0, /* 0 */ 9856 0, 9857 #endif 9858 }, 9859 { 9860 BCMI_TSCE_XGXS_PMD_X4_OVRRr, 9861 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9862 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 9863 BCMI_TSCE_XGXS_PMD_X4_OVRRr_fields, 9864 #else 9865 0, 9866 #endif 9867 #endif 9868 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9869 PHYMOD_SYMBOL_FLAG_REGISTER, 9870 "PMD_X4_OVRRr", 9871 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9872 "PMD_X4_OVERRIDE", 9873 NULL, 9874 #endif 9875 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9876 0x0, /* 0 */ 9877 0, 9878 #endif 9879 }, 9880 { 9881 BCMI_TSCE_XGXS_PMD_X4_EEE_CTLr, 9882 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9883 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 9884 BCMI_TSCE_XGXS_PMD_X4_EEE_CTLr_fields, 9885 #else 9886 0, 9887 #endif 9888 #endif 9889 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9890 PHYMOD_SYMBOL_FLAG_REGISTER, 9891 "PMD_X4_EEE_CTLr", 9892 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9893 "PMD_X4_EEE_CONTROL", 9894 NULL, 9895 #endif 9896 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9897 0x0, /* 0 */ 9898 0, 9899 #endif 9900 }, 9901 { 9902 BCMI_TSCE_XGXS_PMD_X4_EEE_STSr, 9903 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9904 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 9905 BCMI_TSCE_XGXS_PMD_X4_EEE_STSr_fields, 9906 #else 9907 0, 9908 #endif 9909 #endif 9910 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9911 PHYMOD_SYMBOL_FLAG_REGISTER, 9912 "PMD_X4_EEE_STSr", 9913 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9914 "PMD_X4_EEE_STATUS", 9915 NULL, 9916 #endif 9917 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9918 0x0, /* 0 */ 9919 0, 9920 #endif 9921 }, 9922 { 9923 BCMI_TSCE_XGXS_PATGEN_TXPKTCNT_Ur, 9924 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9925 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 9926 BCMI_TSCE_XGXS_PATGEN_TXPKTCNT_Ur_fields, 9927 #else 9928 0, 9929 #endif 9930 #endif 9931 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9932 PHYMOD_SYMBOL_FLAG_REGISTER, 9933 "PATGEN_TXPKTCNT_Ur", 9934 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9935 "PATGEN1_TXPKTCNT_U", 9936 NULL, 9937 #endif 9938 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9939 0x0, /* 0 */ 9940 0, 9941 #endif 9942 }, 9943 { 9944 BCMI_TSCE_XGXS_PATGEN_TXPKTCNT_Lr, 9945 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9946 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 9947 BCMI_TSCE_XGXS_PATGEN_TXPKTCNT_Lr_fields, 9948 #else 9949 0, 9950 #endif 9951 #endif 9952 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9953 PHYMOD_SYMBOL_FLAG_REGISTER, 9954 "PATGEN_TXPKTCNT_Lr", 9955 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9956 "PATGEN1_TXPKTCNT_L", 9957 NULL, 9958 #endif 9959 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9960 0x0, /* 0 */ 9961 0, 9962 #endif 9963 }, 9964 { 9965 BCMI_TSCE_XGXS_PATGEN_RXPKTCNT_Ur, 9966 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9967 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 9968 BCMI_TSCE_XGXS_PATGEN_RXPKTCNT_Ur_fields, 9969 #else 9970 0, 9971 #endif 9972 #endif 9973 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9974 PHYMOD_SYMBOL_FLAG_REGISTER, 9975 "PATGEN_RXPKTCNT_Ur", 9976 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9977 "PATGEN1_RXPKTCNT_U", 9978 NULL, 9979 #endif 9980 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9981 0x0, /* 0 */ 9982 0, 9983 #endif 9984 }, 9985 { 9986 BCMI_TSCE_XGXS_PATGEN_RXPKTCNT_Lr, 9987 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9988 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 9989 BCMI_TSCE_XGXS_PATGEN_RXPKTCNT_Lr_fields, 9990 #else 9991 0, 9992 #endif 9993 #endif 9994 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9995 PHYMOD_SYMBOL_FLAG_REGISTER, 9996 "PATGEN_RXPKTCNT_Lr", 9997 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9998 "PATGEN1_RXPKTCNT_L", 9999 NULL, 10000 #endif 10001 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10002 0x0, /* 0 */ 10003 0, 10004 #endif 10005 }, 10006 { 10007 BCMI_TSCE_XGXS_SC_X4_CTLr, 10008 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10009 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 10010 BCMI_TSCE_XGXS_SC_X4_CTLr_fields, 10011 #else 10012 0, 10013 #endif 10014 #endif 10015 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10016 PHYMOD_SYMBOL_FLAG_REGISTER, 10017 "SC_X4_CTLr", 10018 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10019 "SC_X4_CONTROL_CONTROL", 10020 NULL, 10021 #endif 10022 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10023 0xff, /* 255 */ 10024 0, 10025 #endif 10026 }, 10027 { 10028 BCMI_TSCE_XGXS_SC_X4_STSr, 10029 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10030 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 10031 BCMI_TSCE_XGXS_SC_X4_STSr_fields, 10032 #else 10033 0, 10034 #endif 10035 #endif 10036 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10037 PHYMOD_SYMBOL_FLAG_REGISTER, 10038 "SC_X4_STSr", 10039 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10040 "SC_X4_CONTROL_STATUS", 10041 NULL, 10042 #endif 10043 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10044 0x0, /* 0 */ 10045 0, 10046 #endif 10047 }, 10048 { 10049 BCMI_TSCE_XGXS_SC_X4_ERRr, 10050 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10051 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 10052 BCMI_TSCE_XGXS_SC_X4_ERRr_fields, 10053 #else 10054 0, 10055 #endif 10056 #endif 10057 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10058 PHYMOD_SYMBOL_FLAG_REGISTER, 10059 "SC_X4_ERRr", 10060 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10061 "SC_X4_CONTROL_ERROR", 10062 NULL, 10063 #endif 10064 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10065 0x0, /* 0 */ 10066 0, 10067 #endif 10068 }, 10069 { 10070 BCMI_TSCE_XGXS_SC_X4_DBGr, 10071 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10072 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 10073 BCMI_TSCE_XGXS_SC_X4_DBGr_fields, 10074 #else 10075 0, 10076 #endif 10077 #endif 10078 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10079 PHYMOD_SYMBOL_FLAG_REGISTER, 10080 "SC_X4_DBGr", 10081 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10082 "SC_X4_CONTROL_DEBUG", 10083 NULL, 10084 #endif 10085 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10086 0x8000, /* 32768 */ 10087 0, 10088 #endif 10089 }, 10090 { 10091 BCMI_TSCE_XGXS_SC_X4_LN_NUM_OVRRr, 10092 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10093 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 10094 BCMI_TSCE_XGXS_SC_X4_LN_NUM_OVRRr_fields, 10095 #else 10096 0, 10097 #endif 10098 #endif 10099 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10100 PHYMOD_SYMBOL_FLAG_REGISTER, 10101 "SC_X4_LN_NUM_OVRRr", 10102 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10103 "SC_X4_CONTROL_LANE_NUM_OVERRIDE", 10104 NULL, 10105 #endif 10106 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10107 0x0, /* 0 */ 10108 0, 10109 #endif 10110 }, 10111 { 10112 BCMI_TSCE_XGXS_SC_X4_BYPASSr, 10113 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10114 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 10115 BCMI_TSCE_XGXS_SC_X4_BYPASSr_fields, 10116 #else 10117 0, 10118 #endif 10119 #endif 10120 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10121 PHYMOD_SYMBOL_FLAG_REGISTER, 10122 "SC_X4_BYPASSr", 10123 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10124 "SC_X4_CONTROL_BYPASS", 10125 NULL, 10126 #endif 10127 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10128 0x0, /* 0 */ 10129 0, 10130 #endif 10131 }, 10132 { 10133 BCMI_TSCE_XGXS_SC_X4_FLD_OVRR_EN0_TYPEr, 10134 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10135 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 10136 BCMI_TSCE_XGXS_SC_X4_FLD_OVRR_EN0_TYPEr_fields, 10137 #else 10138 0, 10139 #endif 10140 #endif 10141 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10142 PHYMOD_SYMBOL_FLAG_REGISTER, 10143 "SC_X4_FLD_OVRR_EN0_TYPEr", 10144 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10145 "SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE", 10146 NULL, 10147 #endif 10148 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10149 0x0, /* 0 */ 10150 0, 10151 #endif 10152 }, 10153 { 10154 BCMI_TSCE_XGXS_SC_X4_FLD_OVRR_EN1_TYPEr, 10155 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10156 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 10157 BCMI_TSCE_XGXS_SC_X4_FLD_OVRR_EN1_TYPEr_fields, 10158 #else 10159 0, 10160 #endif 10161 #endif 10162 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10163 PHYMOD_SYMBOL_FLAG_REGISTER, 10164 "SC_X4_FLD_OVRR_EN1_TYPEr", 10165 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10166 "SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE", 10167 NULL, 10168 #endif 10169 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10170 0x0, /* 0 */ 10171 0, 10172 #endif 10173 }, 10174 { 10175 BCMI_TSCE_XGXS_SC_X4_RSLVD_SPDr, 10176 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10177 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 10178 BCMI_TSCE_XGXS_SC_X4_RSLVD_SPDr_fields, 10179 #else 10180 0, 10181 #endif 10182 #endif 10183 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10184 PHYMOD_SYMBOL_FLAG_REGISTER, 10185 "SC_X4_RSLVD_SPDr", 10186 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10187 "SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED", 10188 NULL, 10189 #endif 10190 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10191 0xff00, /* 65280 */ 10192 0, 10193 #endif 10194 }, 10195 { 10196 BCMI_TSCE_XGXS_SC_X4_RSLVD0r, 10197 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10198 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 10199 BCMI_TSCE_XGXS_SC_X4_RSLVD0r_fields, 10200 #else 10201 0, 10202 #endif 10203 #endif 10204 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10205 PHYMOD_SYMBOL_FLAG_REGISTER, 10206 "SC_X4_RSLVD0r", 10207 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10208 "SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0", 10209 NULL, 10210 #endif 10211 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10212 0x0, /* 0 */ 10213 0, 10214 #endif 10215 }, 10216 { 10217 BCMI_TSCE_XGXS_SC_X4_RSLVD1r, 10218 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10219 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 10220 BCMI_TSCE_XGXS_SC_X4_RSLVD1r_fields, 10221 #else 10222 0, 10223 #endif 10224 #endif 10225 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10226 PHYMOD_SYMBOL_FLAG_REGISTER, 10227 "SC_X4_RSLVD1r", 10228 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10229 "SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1", 10230 NULL, 10231 #endif 10232 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10233 0x0, /* 0 */ 10234 0, 10235 #endif 10236 }, 10237 { 10238 BCMI_TSCE_XGXS_SC_X4_RSLVD2r, 10239 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10240 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 10241 BCMI_TSCE_XGXS_SC_X4_RSLVD2r_fields, 10242 #else 10243 0, 10244 #endif 10245 #endif 10246 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10247 PHYMOD_SYMBOL_FLAG_REGISTER, 10248 "SC_X4_RSLVD2r", 10249 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10250 "SC_X4_FINAL_CONFIG_STATUS_RESOLVED_2", 10251 NULL, 10252 #endif 10253 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10254 0x400, /* 1024 */ 10255 0, 10256 #endif 10257 }, 10258 { 10259 BCMI_TSCE_XGXS_SC_X4_RSLVD3r, 10260 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10261 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 10262 BCMI_TSCE_XGXS_SC_X4_RSLVD3r_fields, 10263 #else 10264 0, 10265 #endif 10266 #endif 10267 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10268 PHYMOD_SYMBOL_FLAG_REGISTER, 10269 "SC_X4_RSLVD3r", 10270 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10271 "SC_X4_FINAL_CONFIG_STATUS_RESOLVED_3", 10272 NULL, 10273 #endif 10274 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10275 0x0, /* 0 */ 10276 0, 10277 #endif 10278 }, 10279 { 10280 BCMI_TSCE_XGXS_SC_X4_RSLVD4r, 10281 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10282 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 10283 BCMI_TSCE_XGXS_SC_X4_RSLVD4r_fields, 10284 #else 10285 0, 10286 #endif 10287 #endif 10288 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10289 PHYMOD_SYMBOL_FLAG_REGISTER, 10290 "SC_X4_RSLVD4r", 10291 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10292 "SC_X4_FINAL_CONFIG_STATUS_RESOLVED_4", 10293 NULL, 10294 #endif 10295 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10296 0x0, /* 0 */ 10297 0, 10298 #endif 10299 }, 10300 { 10301 BCMI_TSCE_XGXS_SC_X4_RSLVD5r, 10302 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10303 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 10304 BCMI_TSCE_XGXS_SC_X4_RSLVD5r_fields, 10305 #else 10306 0, 10307 #endif 10308 #endif 10309 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10310 PHYMOD_SYMBOL_FLAG_REGISTER, 10311 "SC_X4_RSLVD5r", 10312 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10313 "SC_X4_FINAL_CONFIG_STATUS_RESOLVED_5", 10314 NULL, 10315 #endif 10316 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10317 0x0, /* 0 */ 10318 0, 10319 #endif 10320 }, 10321 { 10322 BCMI_TSCE_XGXS_SC_X4_RSLVD6r, 10323 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10324 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 10325 BCMI_TSCE_XGXS_SC_X4_RSLVD6r_fields, 10326 #else 10327 0, 10328 #endif 10329 #endif 10330 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10331 PHYMOD_SYMBOL_FLAG_REGISTER, 10332 "SC_X4_RSLVD6r", 10333 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10334 "SC_X4_FINAL_CONFIG_STATUS_RESOLVED_6", 10335 NULL, 10336 #endif 10337 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10338 0x0, /* 0 */ 10339 0, 10340 #endif 10341 }, 10342 { 10343 BCMI_TSCE_XGXS_SC_X4_RSLVD7r, 10344 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10345 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 10346 BCMI_TSCE_XGXS_SC_X4_RSLVD7r_fields, 10347 #else 10348 0, 10349 #endif 10350 #endif 10351 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10352 PHYMOD_SYMBOL_FLAG_REGISTER, 10353 "SC_X4_RSLVD7r", 10354 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10355 "SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7", 10356 NULL, 10357 #endif 10358 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10359 0x0, /* 0 */ 10360 0, 10361 #endif 10362 }, 10363 { 10364 BCMI_TSCE_XGXS_SC_X4_RSLVD8r, 10365 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10366 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 10367 BCMI_TSCE_XGXS_SC_X4_RSLVD8r_fields, 10368 #else 10369 0, 10370 #endif 10371 #endif 10372 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10373 PHYMOD_SYMBOL_FLAG_REGISTER, 10374 "SC_X4_RSLVD8r", 10375 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10376 "SC_X4_FINAL_CONFIG_STATUS_RESOLVED_8", 10377 NULL, 10378 #endif 10379 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10380 0x0, /* 0 */ 10381 0, 10382 #endif 10383 }, 10384 { 10385 BCMI_TSCE_XGXS_TX_X4_CRED0r, 10386 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10387 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 10388 BCMI_TSCE_XGXS_TX_X4_CRED0r_fields, 10389 #else 10390 0, 10391 #endif 10392 #endif 10393 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10394 PHYMOD_SYMBOL_FLAG_REGISTER, 10395 "TX_X4_CRED0r", 10396 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10397 "TX_X4_CREDIT0_CREDIT0", 10398 NULL, 10399 #endif 10400 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10401 0x0, /* 0 */ 10402 0, 10403 #endif 10404 }, 10405 { 10406 BCMI_TSCE_XGXS_TX_X4_CRED1r, 10407 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10408 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 10409 BCMI_TSCE_XGXS_TX_X4_CRED1r_fields, 10410 #else 10411 0, 10412 #endif 10413 #endif 10414 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10415 PHYMOD_SYMBOL_FLAG_REGISTER, 10416 "TX_X4_CRED1r", 10417 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10418 "TX_X4_CREDIT0_CREDIT1", 10419 NULL, 10420 #endif 10421 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10422 0x0, /* 0 */ 10423 0, 10424 #endif 10425 }, 10426 { 10427 BCMI_TSCE_XGXS_TX_X4_LOOPCNTr, 10428 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10429 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 10430 BCMI_TSCE_XGXS_TX_X4_LOOPCNTr_fields, 10431 #else 10432 0, 10433 #endif 10434 #endif 10435 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10436 PHYMOD_SYMBOL_FLAG_REGISTER, 10437 "TX_X4_LOOPCNTr", 10438 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10439 "TX_X4_CREDIT0_LOOPCNT", 10440 NULL, 10441 #endif 10442 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10443 0x0, /* 0 */ 10444 0, 10445 #endif 10446 }, 10447 { 10448 BCMI_TSCE_XGXS_TX_X4_MAC_CREDGENCNTr, 10449 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10450 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 10451 BCMI_TSCE_XGXS_TX_X4_MAC_CREDGENCNTr_fields, 10452 #else 10453 0, 10454 #endif 10455 #endif 10456 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10457 PHYMOD_SYMBOL_FLAG_REGISTER, 10458 "TX_X4_MAC_CREDGENCNTr", 10459 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10460 "TX_X4_CREDIT0_MAC_CREDITGENCNT", 10461 NULL, 10462 #endif 10463 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10464 0x0, /* 0 */ 10465 0, 10466 #endif 10467 }, 10468 { 10469 BCMI_TSCE_XGXS_TX_X4_PCS_CLKCNT0r, 10470 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10471 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 10472 BCMI_TSCE_XGXS_TX_X4_PCS_CLKCNT0r_fields, 10473 #else 10474 0, 10475 #endif 10476 #endif 10477 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10478 PHYMOD_SYMBOL_FLAG_REGISTER, 10479 "TX_X4_PCS_CLKCNT0r", 10480 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10481 "TX_X4_CREDIT0_PCS_CLOCKCNT0", 10482 NULL, 10483 #endif 10484 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10485 0x0, /* 0 */ 10486 0, 10487 #endif 10488 }, 10489 { 10490 BCMI_TSCE_XGXS_TX_X4_PCS_CREDGENCNTr, 10491 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10492 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 10493 BCMI_TSCE_XGXS_TX_X4_PCS_CREDGENCNTr_fields, 10494 #else 10495 0, 10496 #endif 10497 #endif 10498 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10499 PHYMOD_SYMBOL_FLAG_REGISTER, 10500 "TX_X4_PCS_CREDGENCNTr", 10501 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10502 "TX_X4_CREDIT0_PCS_CREDITGENCNT", 10503 NULL, 10504 #endif 10505 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10506 0x0, /* 0 */ 10507 0, 10508 #endif 10509 }, 10510 { 10511 BCMI_TSCE_XGXS_TX_X4_ENC0r, 10512 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10513 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 10514 BCMI_TSCE_XGXS_TX_X4_ENC0r_fields, 10515 #else 10516 0, 10517 #endif 10518 #endif 10519 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10520 PHYMOD_SYMBOL_FLAG_REGISTER, 10521 "TX_X4_ENC0r", 10522 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10523 "TX_X4_CONTROL0_ENCODE_0", 10524 NULL, 10525 #endif 10526 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10527 0x800, /* 2048 */ 10528 0, 10529 #endif 10530 }, 10531 { 10532 BCMI_TSCE_XGXS_TX_X4_ENC1r, 10533 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10534 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 10535 BCMI_TSCE_XGXS_TX_X4_ENC1r_fields, 10536 #else 10537 0, 10538 #endif 10539 #endif 10540 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10541 PHYMOD_SYMBOL_FLAG_REGISTER, 10542 "TX_X4_ENC1r", 10543 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10544 "TX_X4_CONTROL0_ENCODE_1", 10545 NULL, 10546 #endif 10547 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10548 0x1b4, /* 436 */ 10549 0, 10550 #endif 10551 }, 10552 { 10553 BCMI_TSCE_XGXS_TX_X4_MISCr, 10554 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10555 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 10556 BCMI_TSCE_XGXS_TX_X4_MISCr_fields, 10557 #else 10558 0, 10559 #endif 10560 #endif 10561 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10562 PHYMOD_SYMBOL_FLAG_REGISTER, 10563 "TX_X4_MISCr", 10564 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10565 "TX_X4_CONTROL0_MISC", 10566 NULL, 10567 #endif 10568 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10569 0x1c8, /* 456 */ 10570 0, 10571 #endif 10572 }, 10573 { 10574 BCMI_TSCE_XGXS_TX_X4_ENC_STS0r, 10575 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10576 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 10577 BCMI_TSCE_XGXS_TX_X4_ENC_STS0r_fields, 10578 #else 10579 0, 10580 #endif 10581 #endif 10582 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10583 PHYMOD_SYMBOL_FLAG_REGISTER, 10584 "TX_X4_ENC_STS0r", 10585 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10586 "TX_X4_STATUS0_ENCODE_STATUS_0", 10587 NULL, 10588 #endif 10589 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10590 0x0, /* 0 */ 10591 0, 10592 #endif 10593 }, 10594 { 10595 BCMI_TSCE_XGXS_TX_X4_PCS_STSr, 10596 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10597 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 10598 BCMI_TSCE_XGXS_TX_X4_PCS_STSr_fields, 10599 #else 10600 0, 10601 #endif 10602 #endif 10603 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10604 PHYMOD_SYMBOL_FLAG_REGISTER, 10605 "TX_X4_PCS_STSr", 10606 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10607 "TX_X4_STATUS0_PCS_STATUS", 10608 NULL, 10609 #endif 10610 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10611 0x0, /* 0 */ 10612 0, 10613 #endif 10614 }, 10615 { 10616 BCMI_TSCE_XGXS_RX_X4_PCS_CTL0r, 10617 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10618 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 10619 BCMI_TSCE_XGXS_RX_X4_PCS_CTL0r_fields, 10620 #else 10621 0, 10622 #endif 10623 #endif 10624 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10625 PHYMOD_SYMBOL_FLAG_REGISTER, 10626 "RX_X4_PCS_CTL0r", 10627 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10628 "RX_X4_CONTROL0_PCS_CONTROL_0", 10629 NULL, 10630 #endif 10631 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10632 0x0, /* 0 */ 10633 0, 10634 #endif 10635 }, 10636 { 10637 BCMI_TSCE_XGXS_RX_X4_FEC0r, 10638 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10639 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 10640 BCMI_TSCE_XGXS_RX_X4_FEC0r_fields, 10641 #else 10642 0, 10643 #endif 10644 #endif 10645 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10646 PHYMOD_SYMBOL_FLAG_REGISTER, 10647 "RX_X4_FEC0r", 10648 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10649 "RX_X4_CONTROL0_FEC_0", 10650 NULL, 10651 #endif 10652 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10653 0x0, /* 0 */ 10654 0, 10655 #endif 10656 }, 10657 { 10658 BCMI_TSCE_XGXS_RX_X4_FEC1r, 10659 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10660 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 10661 BCMI_TSCE_XGXS_RX_X4_FEC1r_fields, 10662 #else 10663 0, 10664 #endif 10665 #endif 10666 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10667 PHYMOD_SYMBOL_FLAG_REGISTER, 10668 "RX_X4_FEC1r", 10669 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10670 "RX_X4_CONTROL0_FEC_1", 10671 NULL, 10672 #endif 10673 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10674 0x4478, /* 17528 */ 10675 0, 10676 #endif 10677 }, 10678 { 10679 BCMI_TSCE_XGXS_RX_X4_FEC2r, 10680 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10681 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 10682 BCMI_TSCE_XGXS_RX_X4_FEC2r_fields, 10683 #else 10684 0, 10685 #endif 10686 #endif 10687 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10688 PHYMOD_SYMBOL_FLAG_REGISTER, 10689 "RX_X4_FEC2r", 10690 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10691 "RX_X4_CONTROL0_FEC_2", 10692 NULL, 10693 #endif 10694 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10695 0x7828, /* 30760 */ 10696 0, 10697 #endif 10698 }, 10699 { 10700 BCMI_TSCE_XGXS_RX_X4_DEC_CTL0r, 10701 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10702 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 10703 BCMI_TSCE_XGXS_RX_X4_DEC_CTL0r_fields, 10704 #else 10705 0, 10706 #endif 10707 #endif 10708 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10709 PHYMOD_SYMBOL_FLAG_REGISTER, 10710 "RX_X4_DEC_CTL0r", 10711 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10712 "RX_X4_CONTROL0_DECODE_CONTROL_0", 10713 NULL, 10714 #endif 10715 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10716 0x2870, /* 10352 */ 10717 0, 10718 #endif 10719 }, 10720 { 10721 BCMI_TSCE_XGXS_RX_X4_DEC_CTL1r, 10722 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10723 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 10724 BCMI_TSCE_XGXS_RX_X4_DEC_CTL1r_fields, 10725 #else 10726 0, 10727 #endif 10728 #endif 10729 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10730 PHYMOD_SYMBOL_FLAG_REGISTER, 10731 "RX_X4_DEC_CTL1r", 10732 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10733 "RX_X4_CONTROL0_DECODE_CONTROL_1", 10734 NULL, 10735 #endif 10736 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10737 0x0, /* 0 */ 10738 0, 10739 #endif 10740 }, 10741 { 10742 BCMI_TSCE_XGXS_RX_X4_CL36_RX0r, 10743 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10744 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 10745 BCMI_TSCE_XGXS_RX_X4_CL36_RX0r_fields, 10746 #else 10747 0, 10748 #endif 10749 #endif 10750 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10751 PHYMOD_SYMBOL_FLAG_REGISTER, 10752 "RX_X4_CL36_RX0r", 10753 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10754 "RX_X4_CONTROL0_CL36_RX_0", 10755 NULL, 10756 #endif 10757 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10758 0x0, /* 0 */ 10759 0, 10760 #endif 10761 }, 10762 { 10763 BCMI_TSCE_XGXS_RX_X4_PMA_CTL0r, 10764 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10765 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 10766 BCMI_TSCE_XGXS_RX_X4_PMA_CTL0r_fields, 10767 #else 10768 0, 10769 #endif 10770 #endif 10771 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10772 PHYMOD_SYMBOL_FLAG_REGISTER, 10773 "RX_X4_PMA_CTL0r", 10774 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10775 "RX_X4_CONTROL0_PMA_CONTROL_0", 10776 NULL, 10777 #endif 10778 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10779 0x0, /* 0 */ 10780 0, 10781 #endif 10782 }, 10783 { 10784 BCMI_TSCE_XGXS_RX_X4_LNK_CTLr, 10785 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10786 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 10787 BCMI_TSCE_XGXS_RX_X4_LNK_CTLr_fields, 10788 #else 10789 0, 10790 #endif 10791 #endif 10792 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10793 PHYMOD_SYMBOL_FLAG_REGISTER, 10794 "RX_X4_LNK_CTLr", 10795 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10796 "RX_X4_CONTROL0_LINK_CONTROL", 10797 NULL, 10798 #endif 10799 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10800 0x0, /* 0 */ 10801 0, 10802 #endif 10803 }, 10804 { 10805 BCMI_TSCE_XGXS_RX_X4_FEC_DBG_ERRLr, 10806 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10807 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 10808 BCMI_TSCE_XGXS_RX_X4_FEC_DBG_ERRLr_fields, 10809 #else 10810 0, 10811 #endif 10812 #endif 10813 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10814 PHYMOD_SYMBOL_FLAG_REGISTER, 10815 "RX_X4_FEC_DBG_ERRLr", 10816 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10817 "RX_X4_STATUS0_FEC_DBG_ERRL", 10818 NULL, 10819 #endif 10820 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10821 0x0, /* 0 */ 10822 0, 10823 #endif 10824 }, 10825 { 10826 BCMI_TSCE_XGXS_RX_X4_FEC_DBG_ERRAHr, 10827 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10828 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 10829 BCMI_TSCE_XGXS_RX_X4_FEC_DBG_ERRAHr_fields, 10830 #else 10831 0, 10832 #endif 10833 #endif 10834 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10835 PHYMOD_SYMBOL_FLAG_REGISTER, 10836 "RX_X4_FEC_DBG_ERRAHr", 10837 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10838 "RX_X4_STATUS0_FEC_DBG_ERRAH", 10839 NULL, 10840 #endif 10841 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10842 0x0, /* 0 */ 10843 0, 10844 #endif 10845 }, 10846 { 10847 BCMI_TSCE_XGXS_RX_X4_FEC_BURST_ERR_STSLr, 10848 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10849 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 10850 BCMI_TSCE_XGXS_RX_X4_FEC_BURST_ERR_STSLr_fields, 10851 #else 10852 0, 10853 #endif 10854 #endif 10855 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10856 PHYMOD_SYMBOL_FLAG_REGISTER, 10857 "RX_X4_FEC_BURST_ERR_STSLr", 10858 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10859 "RX_X4_STATUS0_FEC_BURST_ERR_STATUSL", 10860 NULL, 10861 #endif 10862 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10863 0x0, /* 0 */ 10864 0, 10865 #endif 10866 }, 10867 { 10868 BCMI_TSCE_XGXS_RX_X4_FEC_BURST_ERR_STSHr, 10869 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10870 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 10871 BCMI_TSCE_XGXS_RX_X4_FEC_BURST_ERR_STSHr_fields, 10872 #else 10873 0, 10874 #endif 10875 #endif 10876 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10877 PHYMOD_SYMBOL_FLAG_REGISTER, 10878 "RX_X4_FEC_BURST_ERR_STSHr", 10879 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10880 "RX_X4_STATUS0_FEC_BURST_ERR_STATUSH", 10881 NULL, 10882 #endif 10883 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10884 0x0, /* 0 */ 10885 0, 10886 #endif 10887 }, 10888 { 10889 BCMI_TSCE_XGXS_RX_X4_BARREL_SHIFTER_STr, 10890 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10891 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 10892 BCMI_TSCE_XGXS_RX_X4_BARREL_SHIFTER_STr_fields, 10893 #else 10894 0, 10895 #endif 10896 #endif 10897 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10898 PHYMOD_SYMBOL_FLAG_REGISTER, 10899 "RX_X4_BARREL_SHIFTER_STr", 10900 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10901 "RX_X4_STATUS0_BARREL_SHIFTER_STATE", 10902 NULL, 10903 #endif 10904 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10905 0x0, /* 0 */ 10906 0, 10907 #endif 10908 }, 10909 { 10910 BCMI_TSCE_XGXS_RX_X4_CL49_LOCK_FSM_STSr, 10911 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10912 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 10913 BCMI_TSCE_XGXS_RX_X4_CL49_LOCK_FSM_STSr_fields, 10914 #else 10915 0, 10916 #endif 10917 #endif 10918 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10919 PHYMOD_SYMBOL_FLAG_REGISTER, 10920 "RX_X4_CL49_LOCK_FSM_STSr", 10921 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10922 "RX_X4_STATUS0_CL49_LOCK_FSM_STATUS", 10923 NULL, 10924 #endif 10925 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10926 0x0, /* 0 */ 10927 0, 10928 #endif 10929 }, 10930 { 10931 BCMI_TSCE_XGXS_RX_X4_DEC_STS0r, 10932 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10933 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 10934 BCMI_TSCE_XGXS_RX_X4_DEC_STS0r_fields, 10935 #else 10936 0, 10937 #endif 10938 #endif 10939 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10940 PHYMOD_SYMBOL_FLAG_REGISTER, 10941 "RX_X4_DEC_STS0r", 10942 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10943 "RX_X4_STATUS0_DECODE_STATUS_0", 10944 NULL, 10945 #endif 10946 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10947 0x0, /* 0 */ 10948 0, 10949 #endif 10950 }, 10951 { 10952 BCMI_TSCE_XGXS_RX_X4_DEC_STS1r, 10953 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10954 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 10955 BCMI_TSCE_XGXS_RX_X4_DEC_STS1r_fields, 10956 #else 10957 0, 10958 #endif 10959 #endif 10960 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10961 PHYMOD_SYMBOL_FLAG_REGISTER, 10962 "RX_X4_DEC_STS1r", 10963 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10964 "RX_X4_STATUS0_DECODE_STATUS_1", 10965 NULL, 10966 #endif 10967 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10968 0x0, /* 0 */ 10969 0, 10970 #endif 10971 }, 10972 { 10973 BCMI_TSCE_XGXS_RX_X4_DEC_STS2r, 10974 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10975 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 10976 BCMI_TSCE_XGXS_RX_X4_DEC_STS2r_fields, 10977 #else 10978 0, 10979 #endif 10980 #endif 10981 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10982 PHYMOD_SYMBOL_FLAG_REGISTER, 10983 "RX_X4_DEC_STS2r", 10984 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10985 "RX_X4_STATUS0_DECODE_STATUS_2", 10986 NULL, 10987 #endif 10988 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10989 0x0, /* 0 */ 10990 0, 10991 #endif 10992 }, 10993 { 10994 BCMI_TSCE_XGXS_RX_X4_DEC_STS3r, 10995 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10996 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 10997 BCMI_TSCE_XGXS_RX_X4_DEC_STS3r_fields, 10998 #else 10999 0, 11000 #endif 11001 #endif 11002 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11003 PHYMOD_SYMBOL_FLAG_REGISTER, 11004 "RX_X4_DEC_STS3r", 11005 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11006 "RX_X4_STATUS0_DECODE_STATUS_3", 11007 NULL, 11008 #endif 11009 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11010 0x0, /* 0 */ 11011 0, 11012 #endif 11013 }, 11014 { 11015 BCMI_TSCE_XGXS_RX_X4_DEC_STS4r, 11016 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11017 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 11018 BCMI_TSCE_XGXS_RX_X4_DEC_STS4r_fields, 11019 #else 11020 0, 11021 #endif 11022 #endif 11023 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11024 PHYMOD_SYMBOL_FLAG_REGISTER, 11025 "RX_X4_DEC_STS4r", 11026 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11027 "RX_X4_STATUS0_DECODE_STATUS_4", 11028 NULL, 11029 #endif 11030 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11031 0x0, /* 0 */ 11032 0, 11033 #endif 11034 }, 11035 { 11036 BCMI_TSCE_XGXS_RX_X4_DEC_STS5r, 11037 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11038 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 11039 BCMI_TSCE_XGXS_RX_X4_DEC_STS5r_fields, 11040 #else 11041 0, 11042 #endif 11043 #endif 11044 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11045 PHYMOD_SYMBOL_FLAG_REGISTER, 11046 "RX_X4_DEC_STS5r", 11047 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11048 "RX_X4_STATUS0_DECODE_STATUS_5", 11049 NULL, 11050 #endif 11051 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11052 0x0, /* 0 */ 11053 0, 11054 #endif 11055 }, 11056 { 11057 BCMI_TSCE_XGXS_RX_X4_SYNCACQ_STS0r, 11058 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11059 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 11060 BCMI_TSCE_XGXS_RX_X4_SYNCACQ_STS0r_fields, 11061 #else 11062 0, 11063 #endif 11064 #endif 11065 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11066 PHYMOD_SYMBOL_FLAG_REGISTER, 11067 "RX_X4_SYNCACQ_STS0r", 11068 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11069 "RX_X4_STATUS0_SYNCACQ_STATUS_0", 11070 NULL, 11071 #endif 11072 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11073 0x0, /* 0 */ 11074 0, 11075 #endif 11076 }, 11077 { 11078 BCMI_TSCE_XGXS_RX_X4_SYNCACQ_STS1r, 11079 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11080 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 11081 BCMI_TSCE_XGXS_RX_X4_SYNCACQ_STS1r_fields, 11082 #else 11083 0, 11084 #endif 11085 #endif 11086 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11087 PHYMOD_SYMBOL_FLAG_REGISTER, 11088 "RX_X4_SYNCACQ_STS1r", 11089 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11090 "RX_X4_STATUS0_SYNCACQ_STATUS_1", 11091 NULL, 11092 #endif 11093 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11094 0x0, /* 0 */ 11095 0, 11096 #endif 11097 }, 11098 { 11099 BCMI_TSCE_XGXS_RX_X4_BERCNTr, 11100 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11101 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 11102 BCMI_TSCE_XGXS_RX_X4_BERCNTr_fields, 11103 #else 11104 0, 11105 #endif 11106 #endif 11107 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11108 PHYMOD_SYMBOL_FLAG_REGISTER, 11109 "RX_X4_BERCNTr", 11110 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11111 "RX_X4_STATUS0_BERCOUNT", 11112 NULL, 11113 #endif 11114 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11115 0x0, /* 0 */ 11116 0, 11117 #endif 11118 }, 11119 { 11120 BCMI_TSCE_XGXS_RX_X4_PCS_LATCH_STS1r, 11121 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11122 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 11123 BCMI_TSCE_XGXS_RX_X4_PCS_LATCH_STS1r_fields, 11124 #else 11125 0, 11126 #endif 11127 #endif 11128 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11129 PHYMOD_SYMBOL_FLAG_REGISTER, 11130 "RX_X4_PCS_LATCH_STS1r", 11131 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11132 "RX_X4_STATUS1_PCS_LATCHED_STATUS_1", 11133 NULL, 11134 #endif 11135 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11136 0x0, /* 0 */ 11137 0, 11138 #endif 11139 }, 11140 { 11141 BCMI_TSCE_XGXS_RX_X4_PCS_LATCH_STS0r, 11142 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11143 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 11144 BCMI_TSCE_XGXS_RX_X4_PCS_LATCH_STS0r_fields, 11145 #else 11146 0, 11147 #endif 11148 #endif 11149 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11150 PHYMOD_SYMBOL_FLAG_REGISTER, 11151 "RX_X4_PCS_LATCH_STS0r", 11152 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11153 "RX_X4_STATUS1_PCS_LATCHED_STATUS_0", 11154 NULL, 11155 #endif 11156 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11157 0x0, /* 0 */ 11158 0, 11159 #endif 11160 }, 11161 { 11162 BCMI_TSCE_XGXS_RX_X4_PCS_LIVE_STSr, 11163 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11164 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 11165 BCMI_TSCE_XGXS_RX_X4_PCS_LIVE_STSr_fields, 11166 #else 11167 0, 11168 #endif 11169 #endif 11170 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11171 PHYMOD_SYMBOL_FLAG_REGISTER, 11172 "RX_X4_PCS_LIVE_STSr", 11173 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11174 "RX_X4_STATUS1_PCS_LIVE_STATUS", 11175 NULL, 11176 #endif 11177 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11178 0x0, /* 0 */ 11179 0, 11180 #endif 11181 }, 11182 { 11183 BCMI_TSCE_XGXS_RX_X4_CL82_AM_LATCH_STSr, 11184 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11185 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 11186 BCMI_TSCE_XGXS_RX_X4_CL82_AM_LATCH_STSr_fields, 11187 #else 11188 0, 11189 #endif 11190 #endif 11191 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11192 PHYMOD_SYMBOL_FLAG_REGISTER, 11193 "RX_X4_CL82_AM_LATCH_STSr", 11194 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11195 "RX_X4_STATUS1_CL82_RX_AM_LATCHED_STATUS", 11196 NULL, 11197 #endif 11198 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11199 0x0, /* 0 */ 11200 0, 11201 #endif 11202 }, 11203 { 11204 BCMI_TSCE_XGXS_RX_X4_CL82_AM_LIVE_STSr, 11205 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11206 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 11207 BCMI_TSCE_XGXS_RX_X4_CL82_AM_LIVE_STSr_fields, 11208 #else 11209 0, 11210 #endif 11211 #endif 11212 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11213 PHYMOD_SYMBOL_FLAG_REGISTER, 11214 "RX_X4_CL82_AM_LIVE_STSr", 11215 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11216 "RX_X4_STATUS1_CL82_RX_AM_LIVE_STATUS", 11217 NULL, 11218 #endif 11219 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11220 0x0, /* 0 */ 11221 0, 11222 #endif 11223 }, 11224 { 11225 BCMI_TSCE_XGXS_RX_X4_FEC_CORRBLKSLr, 11226 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11227 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 11228 BCMI_TSCE_XGXS_RX_X4_FEC_CORRBLKSLr_fields, 11229 #else 11230 0, 11231 #endif 11232 #endif 11233 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11234 PHYMOD_SYMBOL_FLAG_REGISTER, 11235 "RX_X4_FEC_CORRBLKSLr", 11236 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11237 "RX_X4_STATUS1_FEC_CORRECTEDBLKSL", 11238 NULL, 11239 #endif 11240 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11241 0x0, /* 0 */ 11242 0, 11243 #endif 11244 }, 11245 { 11246 BCMI_TSCE_XGXS_RX_X4_FEC_CORRBLKSHr, 11247 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11248 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 11249 BCMI_TSCE_XGXS_RX_X4_FEC_CORRBLKSHr_fields, 11250 #else 11251 0, 11252 #endif 11253 #endif 11254 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11255 PHYMOD_SYMBOL_FLAG_REGISTER, 11256 "RX_X4_FEC_CORRBLKSHr", 11257 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11258 "RX_X4_STATUS1_FEC_CORRECTEDBLKSH", 11259 NULL, 11260 #endif 11261 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11262 0x0, /* 0 */ 11263 0, 11264 #endif 11265 }, 11266 { 11267 BCMI_TSCE_XGXS_RX_X4_FEC_UNCORRBLKSLr, 11268 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11269 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 11270 BCMI_TSCE_XGXS_RX_X4_FEC_UNCORRBLKSLr_fields, 11271 #else 11272 0, 11273 #endif 11274 #endif 11275 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11276 PHYMOD_SYMBOL_FLAG_REGISTER, 11277 "RX_X4_FEC_UNCORRBLKSLr", 11278 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11279 "RX_X4_STATUS1_FEC_UNCORRECTEDBLKSL", 11280 NULL, 11281 #endif 11282 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11283 0x0, /* 0 */ 11284 0, 11285 #endif 11286 }, 11287 { 11288 BCMI_TSCE_XGXS_RX_X4_FEC_UNCORRBLKSHr, 11289 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11290 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 11291 BCMI_TSCE_XGXS_RX_X4_FEC_UNCORRBLKSHr_fields, 11292 #else 11293 0, 11294 #endif 11295 #endif 11296 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11297 PHYMOD_SYMBOL_FLAG_REGISTER, 11298 "RX_X4_FEC_UNCORRBLKSHr", 11299 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11300 "RX_X4_STATUS1_FEC_UNCORRECTEDBLKSH", 11301 NULL, 11302 #endif 11303 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11304 0x0, /* 0 */ 11305 0, 11306 #endif 11307 }, 11308 { 11309 BCMI_TSCE_XGXS_RX_X4_GBOX_STSr, 11310 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11311 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 11312 BCMI_TSCE_XGXS_RX_X4_GBOX_STSr_fields, 11313 #else 11314 0, 11315 #endif 11316 #endif 11317 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11318 PHYMOD_SYMBOL_FLAG_REGISTER, 11319 "RX_X4_GBOX_STSr", 11320 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11321 "RX_X4_STATUS1_GBOX_STATUS", 11322 NULL, 11323 #endif 11324 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11325 0x0, /* 0 */ 11326 0, 11327 #endif 11328 }, 11329 { 11330 BCMI_TSCE_XGXS_RX_X4_T12_FEC0r, 11331 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11332 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 11333 BCMI_TSCE_XGXS_RX_X4_T12_FEC0r_fields, 11334 #else 11335 0, 11336 #endif 11337 #endif 11338 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11339 PHYMOD_SYMBOL_FLAG_REGISTER, 11340 "RX_X4_T12_FEC0r", 11341 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11342 "RX_X4_CONTROL0_TSC_12_FEC_0", 11343 NULL, 11344 #endif 11345 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11346 0x0, /* 0 */ 11347 0, 11348 #endif 11349 }, 11350 { 11351 BCMI_TSCE_XGXS_RX_X4_T12_FEC1r, 11352 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11353 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 11354 BCMI_TSCE_XGXS_RX_X4_T12_FEC1r_fields, 11355 #else 11356 0, 11357 #endif 11358 #endif 11359 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11360 PHYMOD_SYMBOL_FLAG_REGISTER, 11361 "RX_X4_T12_FEC1r", 11362 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11363 "RX_X4_CONTROL0_TSC_12_FEC_1", 11364 NULL, 11365 #endif 11366 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11367 0x4478, /* 17528 */ 11368 0, 11369 #endif 11370 }, 11371 { 11372 BCMI_TSCE_XGXS_RX_X4_T12_FEC2r, 11373 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11374 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 11375 BCMI_TSCE_XGXS_RX_X4_T12_FEC2r_fields, 11376 #else 11377 0, 11378 #endif 11379 #endif 11380 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11381 PHYMOD_SYMBOL_FLAG_REGISTER, 11382 "RX_X4_T12_FEC2r", 11383 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11384 "RX_X4_CONTROL0_TSC_12_FEC_2", 11385 NULL, 11386 #endif 11387 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11388 0x7828, /* 30760 */ 11389 0, 11390 #endif 11391 }, 11392 { 11393 BCMI_TSCE_XGXS_RX_X4_T12_FEC_DBG_ERRLr, 11394 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11395 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 11396 BCMI_TSCE_XGXS_RX_X4_T12_FEC_DBG_ERRLr_fields, 11397 #else 11398 0, 11399 #endif 11400 #endif 11401 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11402 PHYMOD_SYMBOL_FLAG_REGISTER, 11403 "RX_X4_T12_FEC_DBG_ERRLr", 11404 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11405 "RX_X4_STATUS0_TSC_12_FEC_DBG_ERRL", 11406 NULL, 11407 #endif 11408 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11409 0x0, /* 0 */ 11410 0, 11411 #endif 11412 }, 11413 { 11414 BCMI_TSCE_XGXS_RX_X4_T12_FEC_DBG_ERRAHr, 11415 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11416 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 11417 BCMI_TSCE_XGXS_RX_X4_T12_FEC_DBG_ERRAHr_fields, 11418 #else 11419 0, 11420 #endif 11421 #endif 11422 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11423 PHYMOD_SYMBOL_FLAG_REGISTER, 11424 "RX_X4_T12_FEC_DBG_ERRAHr", 11425 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11426 "RX_X4_STATUS0_TSC_12_FEC_DBG_ERRAH", 11427 NULL, 11428 #endif 11429 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11430 0x0, /* 0 */ 11431 0, 11432 #endif 11433 }, 11434 { 11435 BCMI_TSCE_XGXS_RX_X4_T12_FEC_BURST_ERR_STSLr, 11436 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11437 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 11438 BCMI_TSCE_XGXS_RX_X4_T12_FEC_BURST_ERR_STSLr_fields, 11439 #else 11440 0, 11441 #endif 11442 #endif 11443 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11444 PHYMOD_SYMBOL_FLAG_REGISTER, 11445 "RX_X4_T12_FEC_BURST_ERR_STSLr", 11446 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11447 "RX_X4_STATUS0_TSC_12_FEC_BURST_ERR_STATUSL", 11448 NULL, 11449 #endif 11450 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11451 0x0, /* 0 */ 11452 0, 11453 #endif 11454 }, 11455 { 11456 BCMI_TSCE_XGXS_RX_X4_T12_FEC_BURST_ERR_STSHr, 11457 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11458 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 11459 BCMI_TSCE_XGXS_RX_X4_T12_FEC_BURST_ERR_STSHr_fields, 11460 #else 11461 0, 11462 #endif 11463 #endif 11464 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11465 PHYMOD_SYMBOL_FLAG_REGISTER, 11466 "RX_X4_T12_FEC_BURST_ERR_STSHr", 11467 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11468 "RX_X4_STATUS0_TSC_12_FEC_BURST_ERR_STATUSH", 11469 NULL, 11470 #endif 11471 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11472 0x0, /* 0 */ 11473 0, 11474 #endif 11475 }, 11476 { 11477 BCMI_TSCE_XGXS_RX_X4_T12_BERCNTr, 11478 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11479 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 11480 BCMI_TSCE_XGXS_RX_X4_T12_BERCNTr_fields, 11481 #else 11482 0, 11483 #endif 11484 #endif 11485 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11486 PHYMOD_SYMBOL_FLAG_REGISTER, 11487 "RX_X4_T12_BERCNTr", 11488 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11489 "RX_X4_STATUS0_TSC_12_BERCOUNT", 11490 NULL, 11491 #endif 11492 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11493 0x0, /* 0 */ 11494 0, 11495 #endif 11496 }, 11497 { 11498 BCMI_TSCE_XGXS_RX_X4_T12_CL49_LOCK_FSM_STSr, 11499 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11500 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 11501 BCMI_TSCE_XGXS_RX_X4_T12_CL49_LOCK_FSM_STSr_fields, 11502 #else 11503 0, 11504 #endif 11505 #endif 11506 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11507 PHYMOD_SYMBOL_FLAG_REGISTER, 11508 "RX_X4_T12_CL49_LOCK_FSM_STSr", 11509 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11510 "RX_X4_STATUS0_TSC_12_CL49_LOCK_FSM_STATUS", 11511 NULL, 11512 #endif 11513 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11514 0x0, /* 0 */ 11515 0, 11516 #endif 11517 }, 11518 { 11519 BCMI_TSCE_XGXS_RX_X4_T12_MLD_VL_INFO0r, 11520 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11521 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 11522 BCMI_TSCE_XGXS_RX_X4_T12_MLD_VL_INFO0r_fields, 11523 #else 11524 0, 11525 #endif 11526 #endif 11527 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11528 PHYMOD_SYMBOL_FLAG_REGISTER, 11529 "RX_X4_T12_MLD_VL_INFO0r", 11530 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11531 "RX_X4_STATUS0_TSC_12_MLD_VL_INFO_0", 11532 NULL, 11533 #endif 11534 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11535 0x0, /* 0 */ 11536 0, 11537 #endif 11538 }, 11539 { 11540 BCMI_TSCE_XGXS_RX_X4_T12_BARREL_SHIFTER_STr, 11541 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11542 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 11543 BCMI_TSCE_XGXS_RX_X4_T12_BARREL_SHIFTER_STr_fields, 11544 #else 11545 0, 11546 #endif 11547 #endif 11548 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11549 PHYMOD_SYMBOL_FLAG_REGISTER, 11550 "RX_X4_T12_BARREL_SHIFTER_STr", 11551 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11552 "RX_X4_STATUS0_TSC_12_BARREL_SHIFTER_STATE", 11553 NULL, 11554 #endif 11555 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11556 0x0, /* 0 */ 11557 0, 11558 #endif 11559 }, 11560 { 11561 BCMI_TSCE_XGXS_RX_X4_T12_FEC_CORRBLKSLr, 11562 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11563 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 11564 BCMI_TSCE_XGXS_RX_X4_T12_FEC_CORRBLKSLr_fields, 11565 #else 11566 0, 11567 #endif 11568 #endif 11569 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11570 PHYMOD_SYMBOL_FLAG_REGISTER, 11571 "RX_X4_T12_FEC_CORRBLKSLr", 11572 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11573 "RX_X4_STATUS0_TSC_12_FEC_CORRECTEDBLKSL", 11574 NULL, 11575 #endif 11576 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11577 0x0, /* 0 */ 11578 0, 11579 #endif 11580 }, 11581 { 11582 BCMI_TSCE_XGXS_RX_X4_T12_FEC_CORRBLKSHr, 11583 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11584 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 11585 BCMI_TSCE_XGXS_RX_X4_T12_FEC_CORRBLKSHr_fields, 11586 #else 11587 0, 11588 #endif 11589 #endif 11590 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11591 PHYMOD_SYMBOL_FLAG_REGISTER, 11592 "RX_X4_T12_FEC_CORRBLKSHr", 11593 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11594 "RX_X4_STATUS0_TSC_12_FEC_CORRECTEDBLKSH", 11595 NULL, 11596 #endif 11597 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11598 0x0, /* 0 */ 11599 0, 11600 #endif 11601 }, 11602 { 11603 BCMI_TSCE_XGXS_RX_X4_T12_FEC_UNCORRBLKSLr, 11604 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11605 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 11606 BCMI_TSCE_XGXS_RX_X4_T12_FEC_UNCORRBLKSLr_fields, 11607 #else 11608 0, 11609 #endif 11610 #endif 11611 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11612 PHYMOD_SYMBOL_FLAG_REGISTER, 11613 "RX_X4_T12_FEC_UNCORRBLKSLr", 11614 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11615 "RX_X4_STATUS0_TSC_12_FEC_UNCORRECTEDBLKSL", 11616 NULL, 11617 #endif 11618 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11619 0x0, /* 0 */ 11620 0, 11621 #endif 11622 }, 11623 { 11624 BCMI_TSCE_XGXS_RX_X4_T12_FEC_UNCORRBLKSHr, 11625 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11626 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 11627 BCMI_TSCE_XGXS_RX_X4_T12_FEC_UNCORRBLKSHr_fields, 11628 #else 11629 0, 11630 #endif 11631 #endif 11632 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11633 PHYMOD_SYMBOL_FLAG_REGISTER, 11634 "RX_X4_T12_FEC_UNCORRBLKSHr", 11635 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11636 "RX_X4_STATUS0_TSC_12_FEC_UNCORRECTEDBLKSH", 11637 NULL, 11638 #endif 11639 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11640 0x0, /* 0 */ 11641 0, 11642 #endif 11643 }, 11644 { 11645 BCMI_TSCE_XGXS_RX_X4_T12_CL82_PCS_LATCH_STSr, 11646 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11647 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 11648 BCMI_TSCE_XGXS_RX_X4_T12_CL82_PCS_LATCH_STSr_fields, 11649 #else 11650 0, 11651 #endif 11652 #endif 11653 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11654 PHYMOD_SYMBOL_FLAG_REGISTER, 11655 "RX_X4_T12_CL82_PCS_LATCH_STSr", 11656 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11657 "RX_X4_STATUS0_TSC_12_CL82_PCS_LATCHED_STATUS", 11658 NULL, 11659 #endif 11660 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11661 0x0, /* 0 */ 11662 0, 11663 #endif 11664 }, 11665 { 11666 BCMI_TSCE_XGXS_RX_X4_T12_CL82_PCS_LIVE_STSr, 11667 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11668 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 11669 BCMI_TSCE_XGXS_RX_X4_T12_CL82_PCS_LIVE_STSr_fields, 11670 #else 11671 0, 11672 #endif 11673 #endif 11674 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11675 PHYMOD_SYMBOL_FLAG_REGISTER, 11676 "RX_X4_T12_CL82_PCS_LIVE_STSr", 11677 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11678 "RX_X4_STATUS0_TSC_12_CL82_PCS_LIVE_STATUS", 11679 NULL, 11680 #endif 11681 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11682 0x0, /* 0 */ 11683 0, 11684 #endif 11685 }, 11686 { 11687 BCMI_TSCE_XGXS_AN_X4_ENSr, 11688 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11689 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 11690 BCMI_TSCE_XGXS_AN_X4_ENSr_fields, 11691 #else 11692 0, 11693 #endif 11694 #endif 11695 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11696 PHYMOD_SYMBOL_FLAG_REGISTER, 11697 "AN_X4_ENSr", 11698 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11699 "AN_X4_ABILITIES_ENABLES", 11700 NULL, 11701 #endif 11702 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11703 0x0, /* 0 */ 11704 0, 11705 #endif 11706 }, 11707 { 11708 BCMI_TSCE_XGXS_AN_X4_LOC_DEV_CL37_BASE_ABILr, 11709 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11710 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 11711 BCMI_TSCE_XGXS_AN_X4_LOC_DEV_CL37_BASE_ABILr_fields, 11712 #else 11713 0, 11714 #endif 11715 #endif 11716 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11717 PHYMOD_SYMBOL_FLAG_REGISTER, 11718 "AN_X4_LOC_DEV_CL37_BASE_ABILr", 11719 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11720 "AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES", 11721 NULL, 11722 #endif 11723 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11724 0x0, /* 0 */ 11725 0, 11726 #endif 11727 }, 11728 { 11729 BCMI_TSCE_XGXS_AN_X4_LOC_DEV_CL37_BAM_ABILr, 11730 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11731 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 11732 BCMI_TSCE_XGXS_AN_X4_LOC_DEV_CL37_BAM_ABILr_fields, 11733 #else 11734 0, 11735 #endif 11736 #endif 11737 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11738 PHYMOD_SYMBOL_FLAG_REGISTER, 11739 "AN_X4_LOC_DEV_CL37_BAM_ABILr", 11740 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11741 "AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BAM_ABILITIES", 11742 NULL, 11743 #endif 11744 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11745 0x0, /* 0 */ 11746 0, 11747 #endif 11748 }, 11749 { 11750 BCMI_TSCE_XGXS_AN_X4_LOC_DEV_OVER1G_ABIL1r, 11751 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11752 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 11753 BCMI_TSCE_XGXS_AN_X4_LOC_DEV_OVER1G_ABIL1r_fields, 11754 #else 11755 0, 11756 #endif 11757 #endif 11758 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11759 PHYMOD_SYMBOL_FLAG_REGISTER, 11760 "AN_X4_LOC_DEV_OVER1G_ABIL1r", 11761 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11762 "AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1", 11763 NULL, 11764 #endif 11765 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11766 0x0, /* 0 */ 11767 0, 11768 #endif 11769 }, 11770 { 11771 BCMI_TSCE_XGXS_AN_X4_LOC_DEV_OVER1G_ABIL0r, 11772 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11773 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 11774 BCMI_TSCE_XGXS_AN_X4_LOC_DEV_OVER1G_ABIL0r_fields, 11775 #else 11776 0, 11777 #endif 11778 #endif 11779 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11780 PHYMOD_SYMBOL_FLAG_REGISTER, 11781 "AN_X4_LOC_DEV_OVER1G_ABIL0r", 11782 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11783 "AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0", 11784 NULL, 11785 #endif 11786 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11787 0x0, /* 0 */ 11788 0, 11789 #endif 11790 }, 11791 { 11792 BCMI_TSCE_XGXS_AN_X4_LOC_DEV_CL73_BASE_ABIL1r, 11793 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11794 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 11795 BCMI_TSCE_XGXS_AN_X4_LOC_DEV_CL73_BASE_ABIL1r_fields, 11796 #else 11797 0, 11798 #endif 11799 #endif 11800 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11801 PHYMOD_SYMBOL_FLAG_REGISTER, 11802 "AN_X4_LOC_DEV_CL73_BASE_ABIL1r", 11803 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11804 "AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_1", 11805 NULL, 11806 #endif 11807 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11808 0x2a0, /* 672 */ 11809 0, 11810 #endif 11811 }, 11812 { 11813 BCMI_TSCE_XGXS_AN_X4_LOC_DEV_CL73_BASE_ABIL0r, 11814 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11815 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 11816 BCMI_TSCE_XGXS_AN_X4_LOC_DEV_CL73_BASE_ABIL0r_fields, 11817 #else 11818 0, 11819 #endif 11820 #endif 11821 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11822 PHYMOD_SYMBOL_FLAG_REGISTER, 11823 "AN_X4_LOC_DEV_CL73_BASE_ABIL0r", 11824 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11825 "AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0", 11826 NULL, 11827 #endif 11828 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11829 0x0, /* 0 */ 11830 0, 11831 #endif 11832 }, 11833 { 11834 BCMI_TSCE_XGXS_AN_X4_LOC_DEV_CL73_BAM_ABILr, 11835 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11836 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 11837 BCMI_TSCE_XGXS_AN_X4_LOC_DEV_CL73_BAM_ABILr_fields, 11838 #else 11839 0, 11840 #endif 11841 #endif 11842 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11843 PHYMOD_SYMBOL_FLAG_REGISTER, 11844 "AN_X4_LOC_DEV_CL73_BAM_ABILr", 11845 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11846 "AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BAM_ABILITIES", 11847 NULL, 11848 #endif 11849 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11850 0x0, /* 0 */ 11851 0, 11852 #endif 11853 }, 11854 { 11855 BCMI_TSCE_XGXS_AN_X4_CTLSr, 11856 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11857 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 11858 BCMI_TSCE_XGXS_AN_X4_CTLSr_fields, 11859 #else 11860 0, 11861 #endif 11862 #endif 11863 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11864 PHYMOD_SYMBOL_FLAG_REGISTER, 11865 "AN_X4_CTLSr", 11866 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11867 "AN_X4_ABILITIES_CONTROLS", 11868 NULL, 11869 #endif 11870 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11871 0x0, /* 0 */ 11872 0, 11873 #endif 11874 }, 11875 { 11876 BCMI_TSCE_XGXS_AN_X4_LP_MP5_UP1r, 11877 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11878 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 11879 BCMI_TSCE_XGXS_AN_X4_LP_MP5_UP1r_fields, 11880 #else 11881 0, 11882 #endif 11883 #endif 11884 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11885 PHYMOD_SYMBOL_FLAG_REGISTER, 11886 "AN_X4_LP_MP5_UP1r", 11887 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11888 "AN_X4_HW_LP_PAGES_LP_MP5_UP1", 11889 NULL, 11890 #endif 11891 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11892 0x0, /* 0 */ 11893 0, 11894 #endif 11895 }, 11896 { 11897 BCMI_TSCE_XGXS_AN_X4_LP_MP5_UP2r, 11898 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11899 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 11900 BCMI_TSCE_XGXS_AN_X4_LP_MP5_UP2r_fields, 11901 #else 11902 0, 11903 #endif 11904 #endif 11905 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11906 PHYMOD_SYMBOL_FLAG_REGISTER, 11907 "AN_X4_LP_MP5_UP2r", 11908 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11909 "AN_X4_HW_LP_PAGES_LP_MP5_UP2", 11910 NULL, 11911 #endif 11912 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11913 0x0, /* 0 */ 11914 0, 11915 #endif 11916 }, 11917 { 11918 BCMI_TSCE_XGXS_AN_X4_LP_MP5_UP3r, 11919 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11920 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 11921 BCMI_TSCE_XGXS_AN_X4_LP_MP5_UP3r_fields, 11922 #else 11923 0, 11924 #endif 11925 #endif 11926 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11927 PHYMOD_SYMBOL_FLAG_REGISTER, 11928 "AN_X4_LP_MP5_UP3r", 11929 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11930 "AN_X4_HW_LP_PAGES_LP_MP5_UP3", 11931 NULL, 11932 #endif 11933 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11934 0x0, /* 0 */ 11935 0, 11936 #endif 11937 }, 11938 { 11939 BCMI_TSCE_XGXS_AN_X4_LP_MP5_UP4r, 11940 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11941 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 11942 BCMI_TSCE_XGXS_AN_X4_LP_MP5_UP4r_fields, 11943 #else 11944 0, 11945 #endif 11946 #endif 11947 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11948 PHYMOD_SYMBOL_FLAG_REGISTER, 11949 "AN_X4_LP_MP5_UP4r", 11950 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11951 "AN_X4_HW_LP_PAGES_LP_MP5_UP4", 11952 NULL, 11953 #endif 11954 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11955 0x0, /* 0 */ 11956 0, 11957 #endif 11958 }, 11959 { 11960 BCMI_TSCE_XGXS_AN_X4_LP_MP1024_UP1r, 11961 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11962 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 11963 BCMI_TSCE_XGXS_AN_X4_LP_MP1024_UP1r_fields, 11964 #else 11965 0, 11966 #endif 11967 #endif 11968 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11969 PHYMOD_SYMBOL_FLAG_REGISTER, 11970 "AN_X4_LP_MP1024_UP1r", 11971 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11972 "AN_X4_HW_LP_PAGES_LP_MP1024_UP1", 11973 NULL, 11974 #endif 11975 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11976 0x0, /* 0 */ 11977 0, 11978 #endif 11979 }, 11980 { 11981 BCMI_TSCE_XGXS_AN_X4_LP_MP1024_UP2r, 11982 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11983 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 11984 BCMI_TSCE_XGXS_AN_X4_LP_MP1024_UP2r_fields, 11985 #else 11986 0, 11987 #endif 11988 #endif 11989 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11990 PHYMOD_SYMBOL_FLAG_REGISTER, 11991 "AN_X4_LP_MP1024_UP2r", 11992 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11993 "AN_X4_HW_LP_PAGES_LP_MP1024_UP2", 11994 NULL, 11995 #endif 11996 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11997 0x0, /* 0 */ 11998 0, 11999 #endif 12000 }, 12001 { 12002 BCMI_TSCE_XGXS_AN_X4_LP_MP1024_UP3r, 12003 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12004 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 12005 BCMI_TSCE_XGXS_AN_X4_LP_MP1024_UP3r_fields, 12006 #else 12007 0, 12008 #endif 12009 #endif 12010 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12011 PHYMOD_SYMBOL_FLAG_REGISTER, 12012 "AN_X4_LP_MP1024_UP3r", 12013 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12014 "AN_X4_HW_LP_PAGES_LP_MP1024_UP3", 12015 NULL, 12016 #endif 12017 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12018 0x0, /* 0 */ 12019 0, 12020 #endif 12021 }, 12022 { 12023 BCMI_TSCE_XGXS_AN_X4_LP_MP1024_UP4r, 12024 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12025 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 12026 BCMI_TSCE_XGXS_AN_X4_LP_MP1024_UP4r_fields, 12027 #else 12028 0, 12029 #endif 12030 #endif 12031 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12032 PHYMOD_SYMBOL_FLAG_REGISTER, 12033 "AN_X4_LP_MP1024_UP4r", 12034 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12035 "AN_X4_HW_LP_PAGES_LP_MP1024_UP4", 12036 NULL, 12037 #endif 12038 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12039 0x0, /* 0 */ 12040 0, 12041 #endif 12042 }, 12043 { 12044 BCMI_TSCE_XGXS_AN_X4_LP_BASE_PAGE1r, 12045 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12046 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 12047 BCMI_TSCE_XGXS_AN_X4_LP_BASE_PAGE1r_fields, 12048 #else 12049 0, 12050 #endif 12051 #endif 12052 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12053 PHYMOD_SYMBOL_FLAG_REGISTER, 12054 "AN_X4_LP_BASE_PAGE1r", 12055 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12056 "AN_X4_HW_LP_PAGES_LP_BASE_PAGE1", 12057 NULL, 12058 #endif 12059 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12060 0x0, /* 0 */ 12061 0, 12062 #endif 12063 }, 12064 { 12065 BCMI_TSCE_XGXS_AN_X4_LP_BASE_PAGE2r, 12066 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12067 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 12068 BCMI_TSCE_XGXS_AN_X4_LP_BASE_PAGE2r_fields, 12069 #else 12070 0, 12071 #endif 12072 #endif 12073 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12074 PHYMOD_SYMBOL_FLAG_REGISTER, 12075 "AN_X4_LP_BASE_PAGE2r", 12076 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12077 "AN_X4_HW_LP_PAGES_LP_BASE_PAGE2", 12078 NULL, 12079 #endif 12080 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12081 0x0, /* 0 */ 12082 0, 12083 #endif 12084 }, 12085 { 12086 BCMI_TSCE_XGXS_AN_X4_LP_BASE_PAGE3r, 12087 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12088 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 12089 BCMI_TSCE_XGXS_AN_X4_LP_BASE_PAGE3r_fields, 12090 #else 12091 0, 12092 #endif 12093 #endif 12094 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12095 PHYMOD_SYMBOL_FLAG_REGISTER, 12096 "AN_X4_LP_BASE_PAGE3r", 12097 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12098 "AN_X4_HW_LP_PAGES_LP_BASE_PAGE3", 12099 NULL, 12100 #endif 12101 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12102 0x0, /* 0 */ 12103 0, 12104 #endif 12105 }, 12106 { 12107 BCMI_TSCE_XGXS_AN_X4_LD_PAGE2r, 12108 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12109 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 12110 BCMI_TSCE_XGXS_AN_X4_LD_PAGE2r_fields, 12111 #else 12112 0, 12113 #endif 12114 #endif 12115 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12116 PHYMOD_SYMBOL_FLAG_REGISTER, 12117 "AN_X4_LD_PAGE2r", 12118 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12119 "AN_X4_SW_MANAGEMENT_LD_PAGE_2", 12120 NULL, 12121 #endif 12122 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12123 0x0, /* 0 */ 12124 0, 12125 #endif 12126 }, 12127 { 12128 BCMI_TSCE_XGXS_AN_X4_LD_PAGE1r, 12129 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12130 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 12131 BCMI_TSCE_XGXS_AN_X4_LD_PAGE1r_fields, 12132 #else 12133 0, 12134 #endif 12135 #endif 12136 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12137 PHYMOD_SYMBOL_FLAG_REGISTER, 12138 "AN_X4_LD_PAGE1r", 12139 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12140 "AN_X4_SW_MANAGEMENT_LD_PAGE_1", 12141 NULL, 12142 #endif 12143 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12144 0x0, /* 0 */ 12145 0, 12146 #endif 12147 }, 12148 { 12149 BCMI_TSCE_XGXS_AN_X4_LD_PAGE0r, 12150 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12151 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 12152 BCMI_TSCE_XGXS_AN_X4_LD_PAGE0r_fields, 12153 #else 12154 0, 12155 #endif 12156 #endif 12157 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12158 PHYMOD_SYMBOL_FLAG_REGISTER, 12159 "AN_X4_LD_PAGE0r", 12160 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12161 "AN_X4_SW_MANAGEMENT_LD_PAGE_0", 12162 NULL, 12163 #endif 12164 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12165 0x0, /* 0 */ 12166 0, 12167 #endif 12168 }, 12169 { 12170 BCMI_TSCE_XGXS_AN_X4_LP_PAGE2r, 12171 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12172 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 12173 BCMI_TSCE_XGXS_AN_X4_LP_PAGE2r_fields, 12174 #else 12175 0, 12176 #endif 12177 #endif 12178 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12179 PHYMOD_SYMBOL_FLAG_REGISTER, 12180 "AN_X4_LP_PAGE2r", 12181 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12182 "AN_X4_SW_MANAGEMENT_LP_PAGE_2", 12183 NULL, 12184 #endif 12185 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12186 0x0, /* 0 */ 12187 0, 12188 #endif 12189 }, 12190 { 12191 BCMI_TSCE_XGXS_AN_X4_LP_PAGE1r, 12192 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12193 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 12194 BCMI_TSCE_XGXS_AN_X4_LP_PAGE1r_fields, 12195 #else 12196 0, 12197 #endif 12198 #endif 12199 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12200 PHYMOD_SYMBOL_FLAG_REGISTER, 12201 "AN_X4_LP_PAGE1r", 12202 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12203 "AN_X4_SW_MANAGEMENT_LP_PAGE_1", 12204 NULL, 12205 #endif 12206 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12207 0x0, /* 0 */ 12208 0, 12209 #endif 12210 }, 12211 { 12212 BCMI_TSCE_XGXS_AN_X4_LP_PAGE0r, 12213 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12214 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 12215 BCMI_TSCE_XGXS_AN_X4_LP_PAGE0r_fields, 12216 #else 12217 0, 12218 #endif 12219 #endif 12220 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12221 PHYMOD_SYMBOL_FLAG_REGISTER, 12222 "AN_X4_LP_PAGE0r", 12223 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12224 "AN_X4_SW_MANAGEMENT_LP_PAGE_0", 12225 NULL, 12226 #endif 12227 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12228 0x0, /* 0 */ 12229 0, 12230 #endif 12231 }, 12232 { 12233 BCMI_TSCE_XGXS_AN_X4_SW_CTL_STSr, 12234 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12235 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 12236 BCMI_TSCE_XGXS_AN_X4_SW_CTL_STSr_fields, 12237 #else 12238 0, 12239 #endif 12240 #endif 12241 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12242 PHYMOD_SYMBOL_FLAG_REGISTER, 12243 "AN_X4_SW_CTL_STSr", 12244 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12245 "AN_X4_SW_MANAGEMENT_SW_CONTROL_STATUS", 12246 NULL, 12247 #endif 12248 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12249 0x0, /* 0 */ 12250 0, 12251 #endif 12252 }, 12253 { 12254 BCMI_TSCE_XGXS_AN_X4_LD_CTLr, 12255 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12256 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 12257 BCMI_TSCE_XGXS_AN_X4_LD_CTLr_fields, 12258 #else 12259 0, 12260 #endif 12261 #endif 12262 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12263 PHYMOD_SYMBOL_FLAG_REGISTER, 12264 "AN_X4_LD_CTLr", 12265 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12266 "AN_X4_SW_MANAGEMENT_LD_CONTROL", 12267 NULL, 12268 #endif 12269 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12270 0x0, /* 0 */ 12271 0, 12272 #endif 12273 }, 12274 { 12275 BCMI_TSCE_XGXS_AN_X4_AN_PAGE_SEQUENCER_STSr, 12276 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12277 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 12278 BCMI_TSCE_XGXS_AN_X4_AN_PAGE_SEQUENCER_STSr_fields, 12279 #else 12280 0, 12281 #endif 12282 #endif 12283 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12284 PHYMOD_SYMBOL_FLAG_REGISTER, 12285 "AN_X4_AN_PAGE_SEQUENCER_STSr", 12286 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12287 "AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS", 12288 NULL, 12289 #endif 12290 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12291 0x0, /* 0 */ 12292 0, 12293 #endif 12294 }, 12295 { 12296 BCMI_TSCE_XGXS_AN_X4_AN_PAGE_EXCHANGEER_STSr, 12297 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12298 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 12299 BCMI_TSCE_XGXS_AN_X4_AN_PAGE_EXCHANGEER_STSr_fields, 12300 #else 12301 0, 12302 #endif 12303 #endif 12304 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12305 PHYMOD_SYMBOL_FLAG_REGISTER, 12306 "AN_X4_AN_PAGE_EXCHANGEER_STSr", 12307 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12308 "AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS", 12309 NULL, 12310 #endif 12311 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12312 0x0, /* 0 */ 12313 0, 12314 #endif 12315 }, 12316 { 12317 BCMI_TSCE_XGXS_AN_X4_AN_PAGE_DECR_STSr, 12318 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12319 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 12320 BCMI_TSCE_XGXS_AN_X4_AN_PAGE_DECR_STSr_fields, 12321 #else 12322 0, 12323 #endif 12324 #endif 12325 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12326 PHYMOD_SYMBOL_FLAG_REGISTER, 12327 "AN_X4_AN_PAGE_DECR_STSr", 12328 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12329 "AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS", 12330 NULL, 12331 #endif 12332 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12333 0x0, /* 0 */ 12334 0, 12335 #endif 12336 }, 12337 { 12338 BCMI_TSCE_XGXS_AN_X4_AN_ABIL_RESOLUTION_STSr, 12339 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12340 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 12341 BCMI_TSCE_XGXS_AN_X4_AN_ABIL_RESOLUTION_STSr_fields, 12342 #else 12343 0, 12344 #endif 12345 #endif 12346 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12347 PHYMOD_SYMBOL_FLAG_REGISTER, 12348 "AN_X4_AN_ABIL_RESOLUTION_STSr", 12349 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12350 "AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS", 12351 NULL, 12352 #endif 12353 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12354 0x0, /* 0 */ 12355 0, 12356 #endif 12357 }, 12358 { 12359 BCMI_TSCE_XGXS_AN_X4_AN_MISC_STSr, 12360 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12361 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 12362 BCMI_TSCE_XGXS_AN_X4_AN_MISC_STSr_fields, 12363 #else 12364 0, 12365 #endif 12366 #endif 12367 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12368 PHYMOD_SYMBOL_FLAG_REGISTER, 12369 "AN_X4_AN_MISC_STSr", 12370 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12371 "AN_X4_SW_MANAGEMENT_AN_MISC_STATUS", 12372 NULL, 12373 #endif 12374 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12375 0x0, /* 0 */ 12376 0, 12377 #endif 12378 }, 12379 { 12380 BCMI_TSCE_XGXS_AN_X4_TLA_SEQUENCER_STSr, 12381 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12382 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 12383 BCMI_TSCE_XGXS_AN_X4_TLA_SEQUENCER_STSr_fields, 12384 #else 12385 0, 12386 #endif 12387 #endif 12388 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12389 PHYMOD_SYMBOL_FLAG_REGISTER, 12390 "AN_X4_TLA_SEQUENCER_STSr", 12391 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12392 "AN_X4_SW_MANAGEMENT_TLA_SEQUENCER_STATUS", 12393 NULL, 12394 #endif 12395 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12396 0x1, /* 1 */ 12397 0, 12398 #endif 12399 }, 12400 { 12401 BCMI_TSCE_XGXS_AN_X4_AN_SEQ_UNEXPECTED_PAGEr, 12402 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12403 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 12404 BCMI_TSCE_XGXS_AN_X4_AN_SEQ_UNEXPECTED_PAGEr_fields, 12405 #else 12406 0, 12407 #endif 12408 #endif 12409 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12410 PHYMOD_SYMBOL_FLAG_REGISTER, 12411 "AN_X4_AN_SEQ_UNEXPECTED_PAGEr", 12412 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12413 "AN_X4_SW_MANAGEMENT_AN_SEQ_UNEXPECTED_PAGE", 12414 NULL, 12415 #endif 12416 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12417 0x0, /* 0 */ 12418 0, 12419 #endif 12420 }, 12421 { 12422 BCMI_TSCE_XGXS_CL72_LNK_CTLr, 12423 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12424 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 12425 BCMI_TSCE_XGXS_CL72_LNK_CTLr_fields, 12426 #else 12427 0, 12428 #endif 12429 #endif 12430 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12431 PHYMOD_SYMBOL_FLAG_REGISTER, 12432 "CL72_LNK_CTLr", 12433 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12434 "CL72_LINK_CONTROL", 12435 NULL, 12436 #endif 12437 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12438 0x0, /* 0 */ 12439 0, 12440 #endif 12441 }, 12442 { 12443 BCMI_TSCE_XGXS_DIG_CTL1000X2r, 12444 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12445 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 12446 BCMI_TSCE_XGXS_DIG_CTL1000X2r_fields, 12447 #else 12448 0, 12449 #endif 12450 #endif 12451 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12452 PHYMOD_SYMBOL_FLAG_REGISTER, 12453 "DIG_CTL1000X2r", 12454 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12455 "DIGITAL_CONTROL1000X2", 12456 NULL, 12457 #endif 12458 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12459 0x0, /* 0 */ 12460 0, 12461 #endif 12462 }, 12463 { 12464 BCMI_TSCE_XGXS_DIG_SPARE0r, 12465 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12466 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 12467 BCMI_TSCE_XGXS_DIG_SPARE0r_fields, 12468 #else 12469 0, 12470 #endif 12471 #endif 12472 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12473 PHYMOD_SYMBOL_FLAG_REGISTER, 12474 "DIG_SPARE0r", 12475 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12476 "DIGITAL_SPARE0", 12477 NULL, 12478 #endif 12479 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12480 0x0, /* 0 */ 12481 0, 12482 #endif 12483 }, 12484 { 12485 BCMI_TSCE_XGXS_DIG_SPARE1r, 12486 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12487 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 12488 BCMI_TSCE_XGXS_DIG_SPARE1r_fields, 12489 #else 12490 0, 12491 #endif 12492 #endif 12493 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12494 PHYMOD_SYMBOL_FLAG_REGISTER, 12495 "DIG_SPARE1r", 12496 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12497 "DIGITAL_SPARE1", 12498 NULL, 12499 #endif 12500 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12501 0x0, /* 0 */ 12502 0, 12503 #endif 12504 }, 12505 { 12506 BCMI_TSCE_XGXS_ILKN_CTL0r, 12507 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12508 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 12509 BCMI_TSCE_XGXS_ILKN_CTL0r_fields, 12510 #else 12511 0, 12512 #endif 12513 #endif 12514 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12515 PHYMOD_SYMBOL_FLAG_REGISTER, 12516 "ILKN_CTL0r", 12517 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12518 "ILKN_CONTROL0_ILKN_CONTROL0", 12519 NULL, 12520 #endif 12521 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12522 0x2, /* 2 */ 12523 0, 12524 #endif 12525 }, 12526 { 12527 BCMI_TSCE_XGXS_ILKN_STS0r, 12528 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12529 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 12530 BCMI_TSCE_XGXS_ILKN_STS0r_fields, 12531 #else 12532 0, 12533 #endif 12534 #endif 12535 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12536 PHYMOD_SYMBOL_FLAG_REGISTER, 12537 "ILKN_STS0r", 12538 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12539 "ILKN_STATUS0_ILKN_STATUS0", 12540 NULL, 12541 #endif 12542 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12543 0x11, /* 17 */ 12544 0, 12545 #endif 12546 }, 12547 { 12548 BCMI_TSCE_XGXS_ACC_CTLr, 12549 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12550 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 12551 BCMI_TSCE_XGXS_ACC_CTLr_fields, 12552 #else 12553 0, 12554 #endif 12555 #endif 12556 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12557 PHYMOD_SYMBOL_FLAG_REGISTER, 12558 "ACC_CTLr", 12559 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12560 "MDIO_CL22_IEEE_COM_ACC_CTRL", 12561 NULL, 12562 #endif 12563 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12564 0x0, /* 0 */ 12565 0, 12566 #endif 12567 }, 12568 { 12569 BCMI_TSCE_XGXS_ACC_ADDR_DATAr, 12570 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12571 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 12572 BCMI_TSCE_XGXS_ACC_ADDR_DATAr_fields, 12573 #else 12574 0, 12575 #endif 12576 #endif 12577 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12578 PHYMOD_SYMBOL_FLAG_REGISTER, 12579 "ACC_ADDR_DATAr", 12580 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12581 "MDIO_CL22_IEEE_COM_ACC_ADDR_DATA", 12582 NULL, 12583 #endif 12584 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12585 0x0, /* 0 */ 12586 0, 12587 #endif 12588 }, 12589 { 12590 BCMI_TSCE_XGXS_CL72_TXBASE_R_PMD_CTLr, 12591 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12592 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 12593 BCMI_TSCE_XGXS_CL72_TXBASE_R_PMD_CTLr_fields, 12594 #else 12595 0, 12596 #endif 12597 #endif 12598 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12599 PHYMOD_SYMBOL_FLAG_REGISTER, 12600 "CL72_TXBASE_R_PMD_CTLr", 12601 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12602 "CL72_IEEE_TX_BASE_R_PMD_CONTROL_REGISTER_150", 12603 NULL, 12604 #endif 12605 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12606 0x0, /* 0 */ 12607 0, 12608 #endif 12609 }, 12610 { 12611 BCMI_TSCE_XGXS_CL72_TXBASE_R_PMD_STSr, 12612 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12613 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 12614 BCMI_TSCE_XGXS_CL72_TXBASE_R_PMD_STSr_fields, 12615 #else 12616 0, 12617 #endif 12618 #endif 12619 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12620 PHYMOD_SYMBOL_FLAG_REGISTER, 12621 "CL72_TXBASE_R_PMD_STSr", 12622 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12623 "CL72_IEEE_TX_BASE_R_PMD_STATUS_REGISTER_151", 12624 NULL, 12625 #endif 12626 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12627 0x0, /* 0 */ 12628 0, 12629 #endif 12630 }, 12631 { 12632 BCMI_TSCE_XGXS_CL72_TXBASE_R_LP_COEFF_UPDr, 12633 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12634 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 12635 BCMI_TSCE_XGXS_CL72_TXBASE_R_LP_COEFF_UPDr_fields, 12636 #else 12637 0, 12638 #endif 12639 #endif 12640 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12641 PHYMOD_SYMBOL_FLAG_REGISTER, 12642 "CL72_TXBASE_R_LP_COEFF_UPDr", 12643 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12644 "CL72_IEEE_TX_BASE_R_LP_COEFF_UPDATE_REGISTER_152", 12645 NULL, 12646 #endif 12647 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12648 0x0, /* 0 */ 12649 0, 12650 #endif 12651 }, 12652 { 12653 BCMI_TSCE_XGXS_CL72_RXBASE_R_LD_STS_REPr, 12654 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12655 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 12656 BCMI_TSCE_XGXS_CL72_RXBASE_R_LD_STS_REPr_fields, 12657 #else 12658 0, 12659 #endif 12660 #endif 12661 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12662 PHYMOD_SYMBOL_FLAG_REGISTER, 12663 "CL72_RXBASE_R_LD_STS_REPr", 12664 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12665 "CL72_IEEE_RX_BASE_R_LD_STATUS_REPORT_REGISTER_153", 12666 NULL, 12667 #endif 12668 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12669 0x0, /* 0 */ 12670 0, 12671 #endif 12672 }, 12673 { 12674 BCMI_TSCE_XGXS_CL72_TXBASE_R_LD_COEFF_UPDr, 12675 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12676 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 12677 BCMI_TSCE_XGXS_CL72_TXBASE_R_LD_COEFF_UPDr_fields, 12678 #else 12679 0, 12680 #endif 12681 #endif 12682 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12683 PHYMOD_SYMBOL_FLAG_REGISTER, 12684 "CL72_TXBASE_R_LD_COEFF_UPDr", 12685 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12686 "CL72_IEEE_TX_BASE_R_LD_COEFF_UPDATE_REGISTER_154", 12687 NULL, 12688 #endif 12689 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12690 0x0, /* 0 */ 12691 0, 12692 #endif 12693 }, 12694 { 12695 BCMI_TSCE_XGXS_CL72_TXBASE_R_LD_STS_REPr, 12696 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12697 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 12698 BCMI_TSCE_XGXS_CL72_TXBASE_R_LD_STS_REPr_fields, 12699 #else 12700 0, 12701 #endif 12702 #endif 12703 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12704 PHYMOD_SYMBOL_FLAG_REGISTER, 12705 "CL72_TXBASE_R_LD_STS_REPr", 12706 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12707 "CL72_IEEE_TX_BASE_R_LD_STATUS_REPORT_REGISTER_155", 12708 NULL, 12709 #endif 12710 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12711 0x0, /* 0 */ 12712 0, 12713 #endif 12714 }, 12715 { 12716 BCMI_TSCE_XGXS_DSC_CDR_CTL0r, 12717 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12718 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 12719 BCMI_TSCE_XGXS_DSC_CDR_CTL0r_fields, 12720 #else 12721 0, 12722 #endif 12723 #endif 12724 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12725 PHYMOD_SYMBOL_FLAG_REGISTER, 12726 "DSC_CDR_CTL0r", 12727 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12728 "DSC_A_CDR_CONTROL_0", 12729 NULL, 12730 #endif 12731 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12732 0x4, /* 4 */ 12733 0, 12734 #endif 12735 }, 12736 { 12737 BCMI_TSCE_XGXS_DSC_CDR_CTL1r, 12738 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12739 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 12740 BCMI_TSCE_XGXS_DSC_CDR_CTL1r_fields, 12741 #else 12742 0, 12743 #endif 12744 #endif 12745 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12746 PHYMOD_SYMBOL_FLAG_REGISTER, 12747 "DSC_CDR_CTL1r", 12748 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12749 "DSC_A_CDR_CONTROL_1", 12750 NULL, 12751 #endif 12752 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12753 0x690, /* 1680 */ 12754 0, 12755 #endif 12756 }, 12757 { 12758 BCMI_TSCE_XGXS_DSC_CDR_CTL2r, 12759 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12760 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 12761 BCMI_TSCE_XGXS_DSC_CDR_CTL2r_fields, 12762 #else 12763 0, 12764 #endif 12765 #endif 12766 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12767 PHYMOD_SYMBOL_FLAG_REGISTER, 12768 "DSC_CDR_CTL2r", 12769 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12770 "DSC_A_CDR_CONTROL_2", 12771 NULL, 12772 #endif 12773 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12774 0xf0, /* 240 */ 12775 0, 12776 #endif 12777 }, 12778 { 12779 BCMI_TSCE_XGXS_DSC_RX_PI_CTLr, 12780 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12781 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 12782 BCMI_TSCE_XGXS_DSC_RX_PI_CTLr_fields, 12783 #else 12784 0, 12785 #endif 12786 #endif 12787 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12788 PHYMOD_SYMBOL_FLAG_REGISTER, 12789 "DSC_RX_PI_CTLr", 12790 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12791 "DSC_A_RX_PI_CONTROL", 12792 NULL, 12793 #endif 12794 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12795 0x0, /* 0 */ 12796 0, 12797 #endif 12798 }, 12799 { 12800 BCMI_TSCE_XGXS_DSC_CDR_STS_INTEGr, 12801 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12802 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 12803 BCMI_TSCE_XGXS_DSC_CDR_STS_INTEGr_fields, 12804 #else 12805 0, 12806 #endif 12807 #endif 12808 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12809 PHYMOD_SYMBOL_FLAG_REGISTER, 12810 "DSC_CDR_STS_INTEGr", 12811 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12812 "DSC_A_CDR_STATUS_INTEG_REG", 12813 NULL, 12814 #endif 12815 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12816 0x0, /* 0 */ 12817 0, 12818 #endif 12819 }, 12820 { 12821 BCMI_TSCE_XGXS_DSC_CDR_STS_PHASE_ERRr, 12822 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12823 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 12824 BCMI_TSCE_XGXS_DSC_CDR_STS_PHASE_ERRr_fields, 12825 #else 12826 0, 12827 #endif 12828 #endif 12829 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12830 PHYMOD_SYMBOL_FLAG_REGISTER, 12831 "DSC_CDR_STS_PHASE_ERRr", 12832 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12833 "DSC_A_CDR_STATUS_PHASE_ERROR", 12834 NULL, 12835 #endif 12836 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12837 0x100, /* 256 */ 12838 0, 12839 #endif 12840 }, 12841 { 12842 BCMI_TSCE_XGXS_DSC_RX_PI_CNT_BIN_Dr, 12843 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12844 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 12845 BCMI_TSCE_XGXS_DSC_RX_PI_CNT_BIN_Dr_fields, 12846 #else 12847 0, 12848 #endif 12849 #endif 12850 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12851 PHYMOD_SYMBOL_FLAG_REGISTER, 12852 "DSC_RX_PI_CNT_BIN_Dr", 12853 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12854 "DSC_A_RX_PI_CNT_BIN_D", 12855 NULL, 12856 #endif 12857 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12858 0x0, /* 0 */ 12859 0, 12860 #endif 12861 }, 12862 { 12863 BCMI_TSCE_XGXS_DSC_RX_PI_CNT_BIN_Pr, 12864 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12865 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 12866 BCMI_TSCE_XGXS_DSC_RX_PI_CNT_BIN_Pr_fields, 12867 #else 12868 0, 12869 #endif 12870 #endif 12871 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12872 PHYMOD_SYMBOL_FLAG_REGISTER, 12873 "DSC_RX_PI_CNT_BIN_Pr", 12874 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12875 "DSC_A_RX_PI_CNT_BIN_P", 12876 NULL, 12877 #endif 12878 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12879 0x2000, /* 8192 */ 12880 0, 12881 #endif 12882 }, 12883 { 12884 BCMI_TSCE_XGXS_DSC_RX_PI_CNT_BIN_Mr, 12885 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12886 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 12887 BCMI_TSCE_XGXS_DSC_RX_PI_CNT_BIN_Mr_fields, 12888 #else 12889 0, 12890 #endif 12891 #endif 12892 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12893 PHYMOD_SYMBOL_FLAG_REGISTER, 12894 "DSC_RX_PI_CNT_BIN_Mr", 12895 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12896 "DSC_A_RX_PI_CNT_BIN_M", 12897 NULL, 12898 #endif 12899 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12900 0x20, /* 32 */ 12901 0, 12902 #endif 12903 }, 12904 { 12905 BCMI_TSCE_XGXS_DSC_RX_PI_DIFF_BINr, 12906 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12907 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 12908 BCMI_TSCE_XGXS_DSC_RX_PI_DIFF_BINr_fields, 12909 #else 12910 0, 12911 #endif 12912 #endif 12913 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12914 PHYMOD_SYMBOL_FLAG_REGISTER, 12915 "DSC_RX_PI_DIFF_BINr", 12916 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12917 "DSC_A_RX_PI_DIFF_BIN", 12918 NULL, 12919 #endif 12920 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12921 0x0, /* 0 */ 12922 0, 12923 #endif 12924 }, 12925 { 12926 BCMI_TSCE_XGXS_DSC_TRNSUM_CTL5r, 12927 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12928 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 12929 BCMI_TSCE_XGXS_DSC_TRNSUM_CTL5r_fields, 12930 #else 12931 0, 12932 #endif 12933 #endif 12934 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12935 PHYMOD_SYMBOL_FLAG_REGISTER, 12936 "DSC_TRNSUM_CTL5r", 12937 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12938 "DSC_A_TRNSUM_CNTL_5", 12939 NULL, 12940 #endif 12941 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12942 0x0, /* 0 */ 12943 0, 12944 #endif 12945 }, 12946 { 12947 BCMI_TSCE_XGXS_DSC_UC_CTLr, 12948 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12949 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 12950 BCMI_TSCE_XGXS_DSC_UC_CTLr_fields, 12951 #else 12952 0, 12953 #endif 12954 #endif 12955 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12956 PHYMOD_SYMBOL_FLAG_REGISTER, 12957 "DSC_UC_CTLr", 12958 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12959 "DSC_A_DSC_UC_CTRL", 12960 NULL, 12961 #endif 12962 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12963 0x0, /* 0 */ 12964 0, 12965 #endif 12966 }, 12967 { 12968 BCMI_TSCE_XGXS_DSC_SCRATCHr, 12969 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12970 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 12971 BCMI_TSCE_XGXS_DSC_SCRATCHr_fields, 12972 #else 12973 0, 12974 #endif 12975 #endif 12976 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12977 PHYMOD_SYMBOL_FLAG_REGISTER, 12978 "DSC_SCRATCHr", 12979 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12980 "DSC_A_DSC_SCRATCH", 12981 NULL, 12982 #endif 12983 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12984 0x0, /* 0 */ 12985 0, 12986 #endif 12987 }, 12988 { 12989 BCMI_TSCE_XGXS_DSC_SM_CTL0r, 12990 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12991 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 12992 BCMI_TSCE_XGXS_DSC_SM_CTL0r_fields, 12993 #else 12994 0, 12995 #endif 12996 #endif 12997 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12998 PHYMOD_SYMBOL_FLAG_REGISTER, 12999 "DSC_SM_CTL0r", 13000 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13001 "DSC_B_DSC_SM_CTRL_0", 13002 NULL, 13003 #endif 13004 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13005 0x8, /* 8 */ 13006 0, 13007 #endif 13008 }, 13009 { 13010 BCMI_TSCE_XGXS_DSC_SM_CTL1r, 13011 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13012 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 13013 BCMI_TSCE_XGXS_DSC_SM_CTL1r_fields, 13014 #else 13015 0, 13016 #endif 13017 #endif 13018 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13019 PHYMOD_SYMBOL_FLAG_REGISTER, 13020 "DSC_SM_CTL1r", 13021 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13022 "DSC_B_DSC_SM_CTRL_1", 13023 NULL, 13024 #endif 13025 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13026 0x200, /* 512 */ 13027 0, 13028 #endif 13029 }, 13030 { 13031 BCMI_TSCE_XGXS_DSC_SM_CTL2r, 13032 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13033 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 13034 BCMI_TSCE_XGXS_DSC_SM_CTL2r_fields, 13035 #else 13036 0, 13037 #endif 13038 #endif 13039 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13040 PHYMOD_SYMBOL_FLAG_REGISTER, 13041 "DSC_SM_CTL2r", 13042 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13043 "DSC_B_DSC_SM_CTRL_2", 13044 NULL, 13045 #endif 13046 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13047 0x87, /* 135 */ 13048 0, 13049 #endif 13050 }, 13051 { 13052 BCMI_TSCE_XGXS_DSC_SM_CTL3r, 13053 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13054 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 13055 BCMI_TSCE_XGXS_DSC_SM_CTL3r_fields, 13056 #else 13057 0, 13058 #endif 13059 #endif 13060 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13061 PHYMOD_SYMBOL_FLAG_REGISTER, 13062 "DSC_SM_CTL3r", 13063 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13064 "DSC_B_DSC_SM_CTRL_3", 13065 NULL, 13066 #endif 13067 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13068 0x1c1e, /* 7198 */ 13069 0, 13070 #endif 13071 }, 13072 { 13073 BCMI_TSCE_XGXS_DSC_SM_CTL4r, 13074 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13075 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 13076 BCMI_TSCE_XGXS_DSC_SM_CTL4r_fields, 13077 #else 13078 0, 13079 #endif 13080 #endif 13081 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13082 PHYMOD_SYMBOL_FLAG_REGISTER, 13083 "DSC_SM_CTL4r", 13084 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13085 "DSC_B_DSC_SM_CTRL_4", 13086 NULL, 13087 #endif 13088 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13089 0x35ad, /* 13741 */ 13090 0, 13091 #endif 13092 }, 13093 { 13094 BCMI_TSCE_XGXS_DSC_SM_CTL5r, 13095 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13096 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 13097 BCMI_TSCE_XGXS_DSC_SM_CTL5r_fields, 13098 #else 13099 0, 13100 #endif 13101 #endif 13102 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13103 PHYMOD_SYMBOL_FLAG_REGISTER, 13104 "DSC_SM_CTL5r", 13105 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13106 "DSC_B_DSC_SM_CTRL_5", 13107 NULL, 13108 #endif 13109 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13110 0x35ad, /* 13741 */ 13111 0, 13112 #endif 13113 }, 13114 { 13115 BCMI_TSCE_XGXS_DSC_SM_CTL6r, 13116 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13117 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 13118 BCMI_TSCE_XGXS_DSC_SM_CTL6r_fields, 13119 #else 13120 0, 13121 #endif 13122 #endif 13123 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13124 PHYMOD_SYMBOL_FLAG_REGISTER, 13125 "DSC_SM_CTL6r", 13126 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13127 "DSC_B_DSC_SM_CTRL_6", 13128 NULL, 13129 #endif 13130 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13131 0x340d, /* 13325 */ 13132 0, 13133 #endif 13134 }, 13135 { 13136 BCMI_TSCE_XGXS_DSC_SM_CTL7r, 13137 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13138 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 13139 BCMI_TSCE_XGXS_DSC_SM_CTL7r_fields, 13140 #else 13141 0, 13142 #endif 13143 #endif 13144 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13145 PHYMOD_SYMBOL_FLAG_REGISTER, 13146 "DSC_SM_CTL7r", 13147 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13148 "DSC_B_DSC_SM_CTRL_7", 13149 NULL, 13150 #endif 13151 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13152 0x0, /* 0 */ 13153 0, 13154 #endif 13155 }, 13156 { 13157 BCMI_TSCE_XGXS_DSC_SM_CTL8r, 13158 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13159 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 13160 BCMI_TSCE_XGXS_DSC_SM_CTL8r_fields, 13161 #else 13162 0, 13163 #endif 13164 #endif 13165 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13166 PHYMOD_SYMBOL_FLAG_REGISTER, 13167 "DSC_SM_CTL8r", 13168 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13169 "DSC_B_DSC_SM_CTRL_8", 13170 NULL, 13171 #endif 13172 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13173 0x11, /* 17 */ 13174 0, 13175 #endif 13176 }, 13177 { 13178 BCMI_TSCE_XGXS_DSC_SM_CTL9r, 13179 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13180 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 13181 BCMI_TSCE_XGXS_DSC_SM_CTL9r_fields, 13182 #else 13183 0, 13184 #endif 13185 #endif 13186 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13187 PHYMOD_SYMBOL_FLAG_REGISTER, 13188 "DSC_SM_CTL9r", 13189 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13190 "DSC_B_DSC_SM_CTRL_9", 13191 NULL, 13192 #endif 13193 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13194 0x0, /* 0 */ 13195 0, 13196 #endif 13197 }, 13198 { 13199 BCMI_TSCE_XGXS_DSC_SM_STS_DSC_LOCKr, 13200 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13201 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 13202 BCMI_TSCE_XGXS_DSC_SM_STS_DSC_LOCKr_fields, 13203 #else 13204 0, 13205 #endif 13206 #endif 13207 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13208 PHYMOD_SYMBOL_FLAG_REGISTER, 13209 "DSC_SM_STS_DSC_LOCKr", 13210 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13211 "DSC_B_DSC_SM_STATUS_DSC_LOCK", 13212 NULL, 13213 #endif 13214 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13215 0x0, /* 0 */ 13216 0, 13217 #endif 13218 }, 13219 { 13220 BCMI_TSCE_XGXS_DSC_SM_STS_DSC_ST_ONE_HOTr, 13221 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13222 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 13223 BCMI_TSCE_XGXS_DSC_SM_STS_DSC_ST_ONE_HOTr_fields, 13224 #else 13225 0, 13226 #endif 13227 #endif 13228 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13229 PHYMOD_SYMBOL_FLAG_REGISTER, 13230 "DSC_SM_STS_DSC_ST_ONE_HOTr", 13231 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13232 "DSC_B_DSC_SM_STATUS_DSC_STATE_ONE_HOT", 13233 NULL, 13234 #endif 13235 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13236 0x0, /* 0 */ 13237 0, 13238 #endif 13239 }, 13240 { 13241 BCMI_TSCE_XGXS_DSC_SM_STS_DSC_ST_EEE_ONE_HOTr, 13242 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13243 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 13244 BCMI_TSCE_XGXS_DSC_SM_STS_DSC_ST_EEE_ONE_HOTr_fields, 13245 #else 13246 0, 13247 #endif 13248 #endif 13249 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13250 PHYMOD_SYMBOL_FLAG_REGISTER, 13251 "DSC_SM_STS_DSC_ST_EEE_ONE_HOTr", 13252 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13253 "DSC_B_DSC_SM_STATUS_DSC_STATE_EEE_ONE_HOT", 13254 NULL, 13255 #endif 13256 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13257 0x0, /* 0 */ 13258 0, 13259 #endif 13260 }, 13261 { 13262 BCMI_TSCE_XGXS_DSC_SM_STS_RESTARTr, 13263 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13264 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 13265 BCMI_TSCE_XGXS_DSC_SM_STS_RESTARTr_fields, 13266 #else 13267 0, 13268 #endif 13269 #endif 13270 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13271 PHYMOD_SYMBOL_FLAG_REGISTER, 13272 "DSC_SM_STS_RESTARTr", 13273 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13274 "DSC_B_DSC_SM_STATUS_RESTART", 13275 NULL, 13276 #endif 13277 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13278 0x0, /* 0 */ 13279 0, 13280 #endif 13281 }, 13282 { 13283 BCMI_TSCE_XGXS_DSC_SM_STS_DSC_STr, 13284 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13285 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 13286 BCMI_TSCE_XGXS_DSC_SM_STS_DSC_STr_fields, 13287 #else 13288 0, 13289 #endif 13290 #endif 13291 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13292 PHYMOD_SYMBOL_FLAG_REGISTER, 13293 "DSC_SM_STS_DSC_STr", 13294 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13295 "DSC_B_DSC_SM_STATUS_DSC_STATE", 13296 NULL, 13297 #endif 13298 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13299 0x0, /* 0 */ 13300 0, 13301 #endif 13302 }, 13303 { 13304 BCMI_TSCE_XGXS_DSC_DFE_COMMON_CTLr, 13305 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13306 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 13307 BCMI_TSCE_XGXS_DSC_DFE_COMMON_CTLr_fields, 13308 #else 13309 0, 13310 #endif 13311 #endif 13312 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13313 PHYMOD_SYMBOL_FLAG_REGISTER, 13314 "DSC_DFE_COMMON_CTLr", 13315 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13316 "DSC_C_DFE_COMMON_CTL", 13317 NULL, 13318 #endif 13319 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13320 0x0, /* 0 */ 13321 0, 13322 #endif 13323 }, 13324 { 13325 BCMI_TSCE_XGXS_DSC_DFE_1_CTLr, 13326 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13327 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 13328 BCMI_TSCE_XGXS_DSC_DFE_1_CTLr_fields, 13329 #else 13330 0, 13331 #endif 13332 #endif 13333 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13334 PHYMOD_SYMBOL_FLAG_REGISTER, 13335 "DSC_DFE_1_CTLr", 13336 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13337 "DSC_C_DFE_1_CTL", 13338 NULL, 13339 #endif 13340 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13341 0x0, /* 0 */ 13342 0, 13343 #endif 13344 }, 13345 { 13346 BCMI_TSCE_XGXS_DSC_DFE_1_PAT_CTLr, 13347 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13348 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 13349 BCMI_TSCE_XGXS_DSC_DFE_1_PAT_CTLr_fields, 13350 #else 13351 0, 13352 #endif 13353 #endif 13354 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13355 PHYMOD_SYMBOL_FLAG_REGISTER, 13356 "DSC_DFE_1_PAT_CTLr", 13357 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13358 "DSC_C_DFE_1_PAT_CTL", 13359 NULL, 13360 #endif 13361 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13362 0x0, /* 0 */ 13363 0, 13364 #endif 13365 }, 13366 { 13367 BCMI_TSCE_XGXS_DSC_DFE_2_CTLr, 13368 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13369 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 13370 BCMI_TSCE_XGXS_DSC_DFE_2_CTLr_fields, 13371 #else 13372 0, 13373 #endif 13374 #endif 13375 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13376 PHYMOD_SYMBOL_FLAG_REGISTER, 13377 "DSC_DFE_2_CTLr", 13378 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13379 "DSC_C_DFE_2_CTL", 13380 NULL, 13381 #endif 13382 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13383 0x0, /* 0 */ 13384 0, 13385 #endif 13386 }, 13387 { 13388 BCMI_TSCE_XGXS_DSC_DFE_2_PAT_CTLr, 13389 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13390 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 13391 BCMI_TSCE_XGXS_DSC_DFE_2_PAT_CTLr_fields, 13392 #else 13393 0, 13394 #endif 13395 #endif 13396 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13397 PHYMOD_SYMBOL_FLAG_REGISTER, 13398 "DSC_DFE_2_PAT_CTLr", 13399 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13400 "DSC_C_DFE_2_PAT_CTL", 13401 NULL, 13402 #endif 13403 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13404 0x0, /* 0 */ 13405 0, 13406 #endif 13407 }, 13408 { 13409 BCMI_TSCE_XGXS_DSC_DFE_3_CTLr, 13410 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13411 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 13412 BCMI_TSCE_XGXS_DSC_DFE_3_CTLr_fields, 13413 #else 13414 0, 13415 #endif 13416 #endif 13417 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13418 PHYMOD_SYMBOL_FLAG_REGISTER, 13419 "DSC_DFE_3_CTLr", 13420 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13421 "DSC_C_DFE_3_CTL", 13422 NULL, 13423 #endif 13424 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13425 0x0, /* 0 */ 13426 0, 13427 #endif 13428 }, 13429 { 13430 BCMI_TSCE_XGXS_DSC_DFE_3_PAT_CTLr, 13431 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13432 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 13433 BCMI_TSCE_XGXS_DSC_DFE_3_PAT_CTLr_fields, 13434 #else 13435 0, 13436 #endif 13437 #endif 13438 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13439 PHYMOD_SYMBOL_FLAG_REGISTER, 13440 "DSC_DFE_3_PAT_CTLr", 13441 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13442 "DSC_C_DFE_3_PAT_CTL", 13443 NULL, 13444 #endif 13445 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13446 0x0, /* 0 */ 13447 0, 13448 #endif 13449 }, 13450 { 13451 BCMI_TSCE_XGXS_DSC_DFE_4_CTLr, 13452 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13453 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 13454 BCMI_TSCE_XGXS_DSC_DFE_4_CTLr_fields, 13455 #else 13456 0, 13457 #endif 13458 #endif 13459 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13460 PHYMOD_SYMBOL_FLAG_REGISTER, 13461 "DSC_DFE_4_CTLr", 13462 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13463 "DSC_C_DFE_4_CTL", 13464 NULL, 13465 #endif 13466 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13467 0x0, /* 0 */ 13468 0, 13469 #endif 13470 }, 13471 { 13472 BCMI_TSCE_XGXS_DSC_DFE_4_PAT_CTLr, 13473 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13474 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 13475 BCMI_TSCE_XGXS_DSC_DFE_4_PAT_CTLr_fields, 13476 #else 13477 0, 13478 #endif 13479 #endif 13480 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13481 PHYMOD_SYMBOL_FLAG_REGISTER, 13482 "DSC_DFE_4_PAT_CTLr", 13483 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13484 "DSC_C_DFE_4_PAT_CTL", 13485 NULL, 13486 #endif 13487 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13488 0x0, /* 0 */ 13489 0, 13490 #endif 13491 }, 13492 { 13493 BCMI_TSCE_XGXS_DSC_DFE_5_CTLr, 13494 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13495 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 13496 BCMI_TSCE_XGXS_DSC_DFE_5_CTLr_fields, 13497 #else 13498 0, 13499 #endif 13500 #endif 13501 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13502 PHYMOD_SYMBOL_FLAG_REGISTER, 13503 "DSC_DFE_5_CTLr", 13504 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13505 "DSC_C_DFE_5_CTL", 13506 NULL, 13507 #endif 13508 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13509 0x0, /* 0 */ 13510 0, 13511 #endif 13512 }, 13513 { 13514 BCMI_TSCE_XGXS_DSC_DFE_5_PAT_CTLr, 13515 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13516 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 13517 BCMI_TSCE_XGXS_DSC_DFE_5_PAT_CTLr_fields, 13518 #else 13519 0, 13520 #endif 13521 #endif 13522 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13523 PHYMOD_SYMBOL_FLAG_REGISTER, 13524 "DSC_DFE_5_PAT_CTLr", 13525 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13526 "DSC_C_DFE_5_PAT_CTL", 13527 NULL, 13528 #endif 13529 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13530 0x0, /* 0 */ 13531 0, 13532 #endif 13533 }, 13534 { 13535 BCMI_TSCE_XGXS_DSC_DFE_VGA_OVRRr, 13536 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13537 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 13538 BCMI_TSCE_XGXS_DSC_DFE_VGA_OVRRr_fields, 13539 #else 13540 0, 13541 #endif 13542 #endif 13543 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13544 PHYMOD_SYMBOL_FLAG_REGISTER, 13545 "DSC_DFE_VGA_OVRRr", 13546 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13547 "DSC_C_DFE_VGA_OVERRIDE", 13548 NULL, 13549 #endif 13550 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13551 0x0, /* 0 */ 13552 0, 13553 #endif 13554 }, 13555 { 13556 BCMI_TSCE_XGXS_DSC_VGA_CTLr, 13557 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13558 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 13559 BCMI_TSCE_XGXS_DSC_VGA_CTLr_fields, 13560 #else 13561 0, 13562 #endif 13563 #endif 13564 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13565 PHYMOD_SYMBOL_FLAG_REGISTER, 13566 "DSC_VGA_CTLr", 13567 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13568 "DSC_C_VGA_CTL", 13569 NULL, 13570 #endif 13571 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13572 0x0, /* 0 */ 13573 0, 13574 #endif 13575 }, 13576 { 13577 BCMI_TSCE_XGXS_DSC_VGA_PAT_EYEDIAG_CTLr, 13578 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13579 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 13580 BCMI_TSCE_XGXS_DSC_VGA_PAT_EYEDIAG_CTLr_fields, 13581 #else 13582 0, 13583 #endif 13584 #endif 13585 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13586 PHYMOD_SYMBOL_FLAG_REGISTER, 13587 "DSC_VGA_PAT_EYEDIAG_CTLr", 13588 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13589 "DSC_C_VGA_PAT_EYEDIAG_CTL", 13590 NULL, 13591 #endif 13592 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13593 0x0, /* 0 */ 13594 0, 13595 #endif 13596 }, 13597 { 13598 BCMI_TSCE_XGXS_DSC_P1_FRAC_OFFS_CTLr, 13599 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13600 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 13601 BCMI_TSCE_XGXS_DSC_P1_FRAC_OFFS_CTLr_fields, 13602 #else 13603 0, 13604 #endif 13605 #endif 13606 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13607 PHYMOD_SYMBOL_FLAG_REGISTER, 13608 "DSC_P1_FRAC_OFFS_CTLr", 13609 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13610 "DSC_C_P1_FRAC_OFFS_CTL", 13611 NULL, 13612 #endif 13613 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13614 0x0, /* 0 */ 13615 0, 13616 #endif 13617 }, 13618 { 13619 BCMI_TSCE_XGXS_DSC_TRNSUM_CTL1r, 13620 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13621 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 13622 BCMI_TSCE_XGXS_DSC_TRNSUM_CTL1r_fields, 13623 #else 13624 0, 13625 #endif 13626 #endif 13627 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13628 PHYMOD_SYMBOL_FLAG_REGISTER, 13629 "DSC_TRNSUM_CTL1r", 13630 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13631 "DSC_D_TRNSUM_CTL_1", 13632 NULL, 13633 #endif 13634 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13635 0x0, /* 0 */ 13636 0, 13637 #endif 13638 }, 13639 { 13640 BCMI_TSCE_XGXS_DSC_TRNSUM_CTL2r, 13641 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13642 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 13643 BCMI_TSCE_XGXS_DSC_TRNSUM_CTL2r_fields, 13644 #else 13645 0, 13646 #endif 13647 #endif 13648 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13649 PHYMOD_SYMBOL_FLAG_REGISTER, 13650 "DSC_TRNSUM_CTL2r", 13651 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13652 "DSC_D_TRNSUM_CTL_2", 13653 NULL, 13654 #endif 13655 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13656 0x0, /* 0 */ 13657 0, 13658 #endif 13659 }, 13660 { 13661 BCMI_TSCE_XGXS_DSC_TRNSUM_CTL3r, 13662 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13663 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 13664 BCMI_TSCE_XGXS_DSC_TRNSUM_CTL3r_fields, 13665 #else 13666 0, 13667 #endif 13668 #endif 13669 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13670 PHYMOD_SYMBOL_FLAG_REGISTER, 13671 "DSC_TRNSUM_CTL3r", 13672 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13673 "DSC_D_TRNSUM_CTL_3", 13674 NULL, 13675 #endif 13676 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13677 0x0, /* 0 */ 13678 0, 13679 #endif 13680 }, 13681 { 13682 BCMI_TSCE_XGXS_DSC_TRNSUM_CTL4r, 13683 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13684 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 13685 BCMI_TSCE_XGXS_DSC_TRNSUM_CTL4r_fields, 13686 #else 13687 0, 13688 #endif 13689 #endif 13690 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13691 PHYMOD_SYMBOL_FLAG_REGISTER, 13692 "DSC_TRNSUM_CTL4r", 13693 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13694 "DSC_D_TRNSUM_CTL_4", 13695 NULL, 13696 #endif 13697 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13698 0x0, /* 0 */ 13699 0, 13700 #endif 13701 }, 13702 { 13703 BCMI_TSCE_XGXS_DSC_TRNSUM_STS1r, 13704 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13705 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 13706 BCMI_TSCE_XGXS_DSC_TRNSUM_STS1r_fields, 13707 #else 13708 0, 13709 #endif 13710 #endif 13711 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13712 PHYMOD_SYMBOL_FLAG_REGISTER, 13713 "DSC_TRNSUM_STS1r", 13714 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13715 "DSC_D_TRNSUM_STS_1", 13716 NULL, 13717 #endif 13718 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13719 0x0, /* 0 */ 13720 0, 13721 #endif 13722 }, 13723 { 13724 BCMI_TSCE_XGXS_DSC_TRNSUM_STS2r, 13725 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13726 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 13727 BCMI_TSCE_XGXS_DSC_TRNSUM_STS2r_fields, 13728 #else 13729 0, 13730 #endif 13731 #endif 13732 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13733 PHYMOD_SYMBOL_FLAG_REGISTER, 13734 "DSC_TRNSUM_STS2r", 13735 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13736 "DSC_D_TRNSUM_STS_2", 13737 NULL, 13738 #endif 13739 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13740 0x0, /* 0 */ 13741 0, 13742 #endif 13743 }, 13744 { 13745 BCMI_TSCE_XGXS_DSC_TRNSUM_STS3r, 13746 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13747 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 13748 BCMI_TSCE_XGXS_DSC_TRNSUM_STS3r_fields, 13749 #else 13750 0, 13751 #endif 13752 #endif 13753 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13754 PHYMOD_SYMBOL_FLAG_REGISTER, 13755 "DSC_TRNSUM_STS3r", 13756 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13757 "DSC_D_TRNSUM_STS_3", 13758 NULL, 13759 #endif 13760 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13761 0x0, /* 0 */ 13762 0, 13763 #endif 13764 }, 13765 { 13766 BCMI_TSCE_XGXS_DSC_TRNSUM_STS4r, 13767 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13768 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 13769 BCMI_TSCE_XGXS_DSC_TRNSUM_STS4r_fields, 13770 #else 13771 0, 13772 #endif 13773 #endif 13774 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13775 PHYMOD_SYMBOL_FLAG_REGISTER, 13776 "DSC_TRNSUM_STS4r", 13777 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13778 "DSC_D_TRNSUM_STS_4", 13779 NULL, 13780 #endif 13781 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13782 0x0, /* 0 */ 13783 0, 13784 #endif 13785 }, 13786 { 13787 BCMI_TSCE_XGXS_DSC_TRNSUM_STS5r, 13788 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13789 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 13790 BCMI_TSCE_XGXS_DSC_TRNSUM_STS5r_fields, 13791 #else 13792 0, 13793 #endif 13794 #endif 13795 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13796 PHYMOD_SYMBOL_FLAG_REGISTER, 13797 "DSC_TRNSUM_STS5r", 13798 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13799 "DSC_D_TRNSUM_STS_5", 13800 NULL, 13801 #endif 13802 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13803 0x0, /* 0 */ 13804 0, 13805 #endif 13806 }, 13807 { 13808 BCMI_TSCE_XGXS_DSC_TRNSUM_STS6r, 13809 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13810 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 13811 BCMI_TSCE_XGXS_DSC_TRNSUM_STS6r_fields, 13812 #else 13813 0, 13814 #endif 13815 #endif 13816 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13817 PHYMOD_SYMBOL_FLAG_REGISTER, 13818 "DSC_TRNSUM_STS6r", 13819 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13820 "DSC_D_TRNSUM_STS_6", 13821 NULL, 13822 #endif 13823 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13824 0x0, /* 0 */ 13825 0, 13826 #endif 13827 }, 13828 { 13829 BCMI_TSCE_XGXS_DSC_VGA_P1EYEDIAG_STSr, 13830 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13831 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 13832 BCMI_TSCE_XGXS_DSC_VGA_P1EYEDIAG_STSr_fields, 13833 #else 13834 0, 13835 #endif 13836 #endif 13837 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13838 PHYMOD_SYMBOL_FLAG_REGISTER, 13839 "DSC_VGA_P1EYEDIAG_STSr", 13840 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13841 "DSC_D_VGA_P1EYEDIAG_STS", 13842 NULL, 13843 #endif 13844 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13845 0x0, /* 0 */ 13846 0, 13847 #endif 13848 }, 13849 { 13850 BCMI_TSCE_XGXS_DSC_DFE_1_STSr, 13851 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13852 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 13853 BCMI_TSCE_XGXS_DSC_DFE_1_STSr_fields, 13854 #else 13855 0, 13856 #endif 13857 #endif 13858 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13859 PHYMOD_SYMBOL_FLAG_REGISTER, 13860 "DSC_DFE_1_STSr", 13861 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13862 "DSC_D_DFE_1_STS", 13863 NULL, 13864 #endif 13865 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13866 0x0, /* 0 */ 13867 0, 13868 #endif 13869 }, 13870 { 13871 BCMI_TSCE_XGXS_DSC_DFE_2_STSr, 13872 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13873 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 13874 BCMI_TSCE_XGXS_DSC_DFE_2_STSr_fields, 13875 #else 13876 0, 13877 #endif 13878 #endif 13879 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13880 PHYMOD_SYMBOL_FLAG_REGISTER, 13881 "DSC_DFE_2_STSr", 13882 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13883 "DSC_D_DFE_2_STS", 13884 NULL, 13885 #endif 13886 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13887 0x0, /* 0 */ 13888 0, 13889 #endif 13890 }, 13891 { 13892 BCMI_TSCE_XGXS_DSC_DFE_3_4_5_STSr, 13893 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13894 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 13895 BCMI_TSCE_XGXS_DSC_DFE_3_4_5_STSr_fields, 13896 #else 13897 0, 13898 #endif 13899 #endif 13900 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13901 PHYMOD_SYMBOL_FLAG_REGISTER, 13902 "DSC_DFE_3_4_5_STSr", 13903 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13904 "DSC_D_DFE_3_4_5_STS", 13905 NULL, 13906 #endif 13907 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13908 0x0, /* 0 */ 13909 0, 13910 #endif 13911 }, 13912 { 13913 BCMI_TSCE_XGXS_DSC_VGA_TAP_BINr, 13914 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13915 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 13916 BCMI_TSCE_XGXS_DSC_VGA_TAP_BINr_fields, 13917 #else 13918 0, 13919 #endif 13920 #endif 13921 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13922 PHYMOD_SYMBOL_FLAG_REGISTER, 13923 "DSC_VGA_TAP_BINr", 13924 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13925 "DSC_D_VGA_TAP_BIN", 13926 NULL, 13927 #endif 13928 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13929 0x0, /* 0 */ 13930 0, 13931 #endif 13932 }, 13933 { 13934 BCMI_TSCE_XGXS_DSC_CTLr, 13935 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13936 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 13937 BCMI_TSCE_XGXS_DSC_CTLr_fields, 13938 #else 13939 0, 13940 #endif 13941 #endif 13942 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13943 PHYMOD_SYMBOL_FLAG_REGISTER, 13944 "DSC_CTLr", 13945 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13946 "DSC_E_CTRL", 13947 NULL, 13948 #endif 13949 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13950 0x20, /* 32 */ 13951 0, 13952 #endif 13953 }, 13954 { 13955 BCMI_TSCE_XGXS_DSC_PF_CTLr, 13956 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13957 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 13958 BCMI_TSCE_XGXS_DSC_PF_CTLr_fields, 13959 #else 13960 0, 13961 #endif 13962 #endif 13963 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13964 PHYMOD_SYMBOL_FLAG_REGISTER, 13965 "DSC_PF_CTLr", 13966 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13967 "DSC_E_PF_CTRL", 13968 NULL, 13969 #endif 13970 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13971 0x0, /* 0 */ 13972 0, 13973 #endif 13974 }, 13975 { 13976 BCMI_TSCE_XGXS_DSC_PF2_LOWP_CTLr, 13977 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13978 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 13979 BCMI_TSCE_XGXS_DSC_PF2_LOWP_CTLr_fields, 13980 #else 13981 0, 13982 #endif 13983 #endif 13984 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13985 PHYMOD_SYMBOL_FLAG_REGISTER, 13986 "DSC_PF2_LOWP_CTLr", 13987 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13988 "DSC_E_PF2_LOWP_CTRL", 13989 NULL, 13990 #endif 13991 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13992 0x0, /* 0 */ 13993 0, 13994 #endif 13995 }, 13996 { 13997 BCMI_TSCE_XGXS_DSC_OFFS_ADJ_DATA_ODDr, 13998 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13999 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 14000 BCMI_TSCE_XGXS_DSC_OFFS_ADJ_DATA_ODDr_fields, 14001 #else 14002 0, 14003 #endif 14004 #endif 14005 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14006 PHYMOD_SYMBOL_FLAG_REGISTER, 14007 "DSC_OFFS_ADJ_DATA_ODDr", 14008 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14009 "DSC_E_OFFSET_ADJ_DATA_ODD", 14010 NULL, 14011 #endif 14012 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14013 0x0, /* 0 */ 14014 0, 14015 #endif 14016 }, 14017 { 14018 BCMI_TSCE_XGXS_DSC_OFFS_ADJ_DATA_EVENr, 14019 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14020 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 14021 BCMI_TSCE_XGXS_DSC_OFFS_ADJ_DATA_EVENr_fields, 14022 #else 14023 0, 14024 #endif 14025 #endif 14026 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14027 PHYMOD_SYMBOL_FLAG_REGISTER, 14028 "DSC_OFFS_ADJ_DATA_EVENr", 14029 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14030 "DSC_E_OFFSET_ADJ_DATA_EVEN", 14031 NULL, 14032 #endif 14033 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14034 0x0, /* 0 */ 14035 0, 14036 #endif 14037 }, 14038 { 14039 BCMI_TSCE_XGXS_DSC_OFFS_ADJ_P1_ODDr, 14040 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14041 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 14042 BCMI_TSCE_XGXS_DSC_OFFS_ADJ_P1_ODDr_fields, 14043 #else 14044 0, 14045 #endif 14046 #endif 14047 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14048 PHYMOD_SYMBOL_FLAG_REGISTER, 14049 "DSC_OFFS_ADJ_P1_ODDr", 14050 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14051 "DSC_E_OFFSET_ADJ_P1_ODD", 14052 NULL, 14053 #endif 14054 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14055 0x0, /* 0 */ 14056 0, 14057 #endif 14058 }, 14059 { 14060 BCMI_TSCE_XGXS_DSC_OFFS_ADJ_P1_EVENr, 14061 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14062 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 14063 BCMI_TSCE_XGXS_DSC_OFFS_ADJ_P1_EVENr_fields, 14064 #else 14065 0, 14066 #endif 14067 #endif 14068 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14069 PHYMOD_SYMBOL_FLAG_REGISTER, 14070 "DSC_OFFS_ADJ_P1_EVENr", 14071 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14072 "DSC_E_OFFSET_ADJ_P1_EVEN", 14073 NULL, 14074 #endif 14075 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14076 0x0, /* 0 */ 14077 0, 14078 #endif 14079 }, 14080 { 14081 BCMI_TSCE_XGXS_DSC_OFFS_ADJ_M1_ODDr, 14082 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14083 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 14084 BCMI_TSCE_XGXS_DSC_OFFS_ADJ_M1_ODDr_fields, 14085 #else 14086 0, 14087 #endif 14088 #endif 14089 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14090 PHYMOD_SYMBOL_FLAG_REGISTER, 14091 "DSC_OFFS_ADJ_M1_ODDr", 14092 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14093 "DSC_E_OFFSET_ADJ_M1_ODD", 14094 NULL, 14095 #endif 14096 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14097 0x0, /* 0 */ 14098 0, 14099 #endif 14100 }, 14101 { 14102 BCMI_TSCE_XGXS_DSC_OFFS_ADJ_M1_EVENr, 14103 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14104 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 14105 BCMI_TSCE_XGXS_DSC_OFFS_ADJ_M1_EVENr_fields, 14106 #else 14107 0, 14108 #endif 14109 #endif 14110 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14111 PHYMOD_SYMBOL_FLAG_REGISTER, 14112 "DSC_OFFS_ADJ_M1_EVENr", 14113 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14114 "DSC_E_OFFSET_ADJ_M1_EVEN", 14115 NULL, 14116 #endif 14117 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14118 0x0, /* 0 */ 14119 0, 14120 #endif 14121 }, 14122 { 14123 BCMI_TSCE_XGXS_DSC_DC_OFFSr, 14124 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14125 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 14126 BCMI_TSCE_XGXS_DSC_DC_OFFSr_fields, 14127 #else 14128 0, 14129 #endif 14130 #endif 14131 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14132 PHYMOD_SYMBOL_FLAG_REGISTER, 14133 "DSC_DC_OFFSr", 14134 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14135 "DSC_E_DC_OFFSET", 14136 NULL, 14137 #endif 14138 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14139 0x0, /* 0 */ 14140 0, 14141 #endif 14142 }, 14143 { 14144 BCMI_TSCE_XGXS_CL72_RXRCVD_STSr, 14145 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14146 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 14147 BCMI_TSCE_XGXS_CL72_RXRCVD_STSr_fields, 14148 #else 14149 0, 14150 #endif 14151 #endif 14152 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14153 PHYMOD_SYMBOL_FLAG_REGISTER, 14154 "CL72_RXRCVD_STSr", 14155 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14156 "CL72_USER_RX_RCVD_STATUS_REGISTER", 14157 NULL, 14158 #endif 14159 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14160 0x0, /* 0 */ 14161 0, 14162 #endif 14163 }, 14164 { 14165 BCMI_TSCE_XGXS_CL72_RXMISC1_CTLr, 14166 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14167 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 14168 BCMI_TSCE_XGXS_CL72_RXMISC1_CTLr_fields, 14169 #else 14170 0, 14171 #endif 14172 #endif 14173 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14174 PHYMOD_SYMBOL_FLAG_REGISTER, 14175 "CL72_RXMISC1_CTLr", 14176 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14177 "CL72_USER_RX_MISC1_CONTROL", 14178 NULL, 14179 #endif 14180 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14181 0x4, /* 4 */ 14182 0, 14183 #endif 14184 }, 14185 { 14186 BCMI_TSCE_XGXS_CL72_RXDBG2r, 14187 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14188 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 14189 BCMI_TSCE_XGXS_CL72_RXDBG2r_fields, 14190 #else 14191 0, 14192 #endif 14193 #endif 14194 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14195 PHYMOD_SYMBOL_FLAG_REGISTER, 14196 "CL72_RXDBG2r", 14197 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14198 "CL72_USER_RX_DEBUG_2_REGISTER", 14199 NULL, 14200 #endif 14201 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14202 0x96, /* 150 */ 14203 0, 14204 #endif 14205 }, 14206 { 14207 BCMI_TSCE_XGXS_CL72_RXCL72_LP_CTL_PAGEr, 14208 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14209 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 14210 BCMI_TSCE_XGXS_CL72_RXCL72_LP_CTL_PAGEr_fields, 14211 #else 14212 0, 14213 #endif 14214 #endif 14215 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14216 PHYMOD_SYMBOL_FLAG_REGISTER, 14217 "CL72_RXCL72_LP_CTL_PAGEr", 14218 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14219 "CL72_USER_RX_CL72_LP_CONTROL_PAGE", 14220 NULL, 14221 #endif 14222 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14223 0x0, /* 0 */ 14224 0, 14225 #endif 14226 }, 14227 { 14228 BCMI_TSCE_XGXS_CL72_RXCL72_STS1r, 14229 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14230 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 14231 BCMI_TSCE_XGXS_CL72_RXCL72_STS1r_fields, 14232 #else 14233 0, 14234 #endif 14235 #endif 14236 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14237 PHYMOD_SYMBOL_FLAG_REGISTER, 14238 "CL72_RXCL72_STS1r", 14239 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14240 "CL72_USER_RX_CL72_STATUS1_REGISTER", 14241 NULL, 14242 #endif 14243 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14244 0x0, /* 0 */ 14245 0, 14246 #endif 14247 }, 14248 { 14249 BCMI_TSCE_XGXS_CL72_TXXMT_UPDr, 14250 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14251 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 14252 BCMI_TSCE_XGXS_CL72_TXXMT_UPDr_fields, 14253 #else 14254 0, 14255 #endif 14256 #endif 14257 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14258 PHYMOD_SYMBOL_FLAG_REGISTER, 14259 "CL72_TXXMT_UPDr", 14260 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14261 "CL72_USER_TX_XMT_UPDATE_REGISTER", 14262 NULL, 14263 #endif 14264 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14265 0x0, /* 0 */ 14266 0, 14267 #endif 14268 }, 14269 { 14270 BCMI_TSCE_XGXS_CL72_TXMISC2_CTLr, 14271 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14272 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 14273 BCMI_TSCE_XGXS_CL72_TXMISC2_CTLr_fields, 14274 #else 14275 0, 14276 #endif 14277 #endif 14278 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14279 PHYMOD_SYMBOL_FLAG_REGISTER, 14280 "CL72_TXMISC2_CTLr", 14281 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14282 "CL72_USER_TX_MISC2_CONTROL", 14283 NULL, 14284 #endif 14285 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14286 0x4, /* 4 */ 14287 0, 14288 #endif 14289 }, 14290 { 14291 BCMI_TSCE_XGXS_CL72_TXDBG3r, 14292 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14293 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 14294 BCMI_TSCE_XGXS_CL72_TXDBG3r_fields, 14295 #else 14296 0, 14297 #endif 14298 #endif 14299 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14300 PHYMOD_SYMBOL_FLAG_REGISTER, 14301 "CL72_TXDBG3r", 14302 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14303 "CL72_USER_TX_DEBUG_3_REGISTER", 14304 NULL, 14305 #endif 14306 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14307 0x2, /* 2 */ 14308 0, 14309 #endif 14310 }, 14311 { 14312 BCMI_TSCE_XGXS_CL72_TXPCS_INTERFACE_CTLr, 14313 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14314 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 14315 BCMI_TSCE_XGXS_CL72_TXPCS_INTERFACE_CTLr_fields, 14316 #else 14317 0, 14318 #endif 14319 #endif 14320 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14321 PHYMOD_SYMBOL_FLAG_REGISTER, 14322 "CL72_TXPCS_INTERFACE_CTLr", 14323 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14324 "CL72_USER_TX_PCS_INTERFACE_CONTROL_REGISTER", 14325 NULL, 14326 #endif 14327 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14328 0x0, /* 0 */ 14329 0, 14330 #endif 14331 }, 14332 { 14333 BCMI_TSCE_XGXS_CL72_TXCL72_LD_STS_PAGEr, 14334 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14335 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 14336 BCMI_TSCE_XGXS_CL72_TXCL72_LD_STS_PAGEr_fields, 14337 #else 14338 0, 14339 #endif 14340 #endif 14341 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14342 PHYMOD_SYMBOL_FLAG_REGISTER, 14343 "CL72_TXCL72_LD_STS_PAGEr", 14344 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14345 "CL72_USER_TX_CL72_LD_STATUS_PAGE", 14346 NULL, 14347 #endif 14348 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14349 0x0, /* 0 */ 14350 0, 14351 #endif 14352 }, 14353 { 14354 BCMI_TSCE_XGXS_CL72_TXCL72_READY_FOR_CMDr, 14355 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14356 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 14357 BCMI_TSCE_XGXS_CL72_TXCL72_READY_FOR_CMDr_fields, 14358 #else 14359 0, 14360 #endif 14361 #endif 14362 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14363 PHYMOD_SYMBOL_FLAG_REGISTER, 14364 "CL72_TXCL72_READY_FOR_CMDr", 14365 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14366 "CL72_USER_TX_CL72_READY_FOR_CMD_REGISTER", 14367 NULL, 14368 #endif 14369 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14370 0x1, /* 1 */ 14371 0, 14372 #endif 14373 }, 14374 { 14375 BCMI_TSCE_XGXS_CL72_TXKR_DFLT_CTL1r, 14376 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14377 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 14378 BCMI_TSCE_XGXS_CL72_TXKR_DFLT_CTL1r_fields, 14379 #else 14380 0, 14381 #endif 14382 #endif 14383 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14384 PHYMOD_SYMBOL_FLAG_REGISTER, 14385 "CL72_TXKR_DFLT_CTL1r", 14386 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14387 "CL72_USER_TX_KR_DEFAULT_CONTROL1", 14388 NULL, 14389 #endif 14390 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14391 0x588, /* 1416 */ 14392 0, 14393 #endif 14394 }, 14395 { 14396 BCMI_TSCE_XGXS_CL72_TXKR_DFLT_CTL2r, 14397 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14398 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 14399 BCMI_TSCE_XGXS_CL72_TXKR_DFLT_CTL2r_fields, 14400 #else 14401 0, 14402 #endif 14403 #endif 14404 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14405 PHYMOD_SYMBOL_FLAG_REGISTER, 14406 "CL72_TXKR_DFLT_CTL2r", 14407 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14408 "CL72_USER_TX_KR_DEFAULT_CONTROL2", 14409 NULL, 14410 #endif 14411 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14412 0x3c, /* 60 */ 14413 0, 14414 #endif 14415 }, 14416 { 14417 BCMI_TSCE_XGXS_CL72_TXMISC_COEFF_CTLr, 14418 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14419 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 14420 BCMI_TSCE_XGXS_CL72_TXMISC_COEFF_CTLr_fields, 14421 #else 14422 0, 14423 #endif 14424 #endif 14425 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14426 PHYMOD_SYMBOL_FLAG_REGISTER, 14427 "CL72_TXMISC_COEFF_CTLr", 14428 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14429 "CL72_USER_TX_MISC_COEFF_CONTROL", 14430 NULL, 14431 #endif 14432 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14433 0x83, /* 131 */ 14434 0, 14435 #endif 14436 }, 14437 { 14438 BCMI_TSCE_XGXS_CL72_TXCL72_LD_XMT_STS_PAGE_OVRRr, 14439 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14440 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 14441 BCMI_TSCE_XGXS_CL72_TXCL72_LD_XMT_STS_PAGE_OVRRr_fields, 14442 #else 14443 0, 14444 #endif 14445 #endif 14446 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14447 PHYMOD_SYMBOL_FLAG_REGISTER, 14448 "CL72_TXCL72_LD_XMT_STS_PAGE_OVRRr", 14449 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14450 "CL72_USER_TX_CL72_LD_XMT_STATUS_PAGE_OVERRIDE", 14451 NULL, 14452 #endif 14453 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14454 0x0, /* 0 */ 14455 0, 14456 #endif 14457 }, 14458 { 14459 BCMI_TSCE_XGXS_CL72_TXCL72_TX_DBG_STSr, 14460 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14461 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 14462 BCMI_TSCE_XGXS_CL72_TXCL72_TX_DBG_STSr_fields, 14463 #else 14464 0, 14465 #endif 14466 #endif 14467 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14468 PHYMOD_SYMBOL_FLAG_REGISTER, 14469 "CL72_TXCL72_TX_DBG_STSr", 14470 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14471 "CL72_USER_TX_CL72_TX_DEBUG_STATUS", 14472 NULL, 14473 #endif 14474 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14475 0x0, /* 0 */ 14476 0, 14477 #endif 14478 }, 14479 { 14480 BCMI_TSCE_XGXS_TX_PI_CTL0r, 14481 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14482 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 14483 BCMI_TSCE_XGXS_TX_PI_CTL0r_fields, 14484 #else 14485 0, 14486 #endif 14487 #endif 14488 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14489 PHYMOD_SYMBOL_FLAG_REGISTER, 14490 "TX_PI_CTL0r", 14491 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14492 "TX_PI_COM_CONTROL_0", 14493 NULL, 14494 #endif 14495 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14496 0x2000, /* 8192 */ 14497 0, 14498 #endif 14499 }, 14500 { 14501 BCMI_TSCE_XGXS_TX_PI_CTL1r, 14502 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14503 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 14504 BCMI_TSCE_XGXS_TX_PI_CTL1r_fields, 14505 #else 14506 0, 14507 #endif 14508 #endif 14509 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14510 PHYMOD_SYMBOL_FLAG_REGISTER, 14511 "TX_PI_CTL1r", 14512 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14513 "TX_PI_COM_CONTROL_1", 14514 NULL, 14515 #endif 14516 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14517 0x0, /* 0 */ 14518 0, 14519 #endif 14520 }, 14521 { 14522 BCMI_TSCE_XGXS_TX_PI_CTL2r, 14523 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14524 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 14525 BCMI_TSCE_XGXS_TX_PI_CTL2r_fields, 14526 #else 14527 0, 14528 #endif 14529 #endif 14530 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14531 PHYMOD_SYMBOL_FLAG_REGISTER, 14532 "TX_PI_CTL2r", 14533 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14534 "TX_PI_COM_CONTROL_2", 14535 NULL, 14536 #endif 14537 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14538 0x0, /* 0 */ 14539 0, 14540 #endif 14541 }, 14542 { 14543 BCMI_TSCE_XGXS_TX_PI_CTL3r, 14544 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14545 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 14546 BCMI_TSCE_XGXS_TX_PI_CTL3r_fields, 14547 #else 14548 0, 14549 #endif 14550 #endif 14551 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14552 PHYMOD_SYMBOL_FLAG_REGISTER, 14553 "TX_PI_CTL3r", 14554 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14555 "TX_PI_COM_CONTROL_3", 14556 NULL, 14557 #endif 14558 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14559 0x100, /* 256 */ 14560 0, 14561 #endif 14562 }, 14563 { 14564 BCMI_TSCE_XGXS_TX_PI_CTL4r, 14565 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14566 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 14567 BCMI_TSCE_XGXS_TX_PI_CTL4r_fields, 14568 #else 14569 0, 14570 #endif 14571 #endif 14572 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14573 PHYMOD_SYMBOL_FLAG_REGISTER, 14574 "TX_PI_CTL4r", 14575 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14576 "TX_PI_COM_CONTROL_4", 14577 NULL, 14578 #endif 14579 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14580 0x4, /* 4 */ 14581 0, 14582 #endif 14583 }, 14584 { 14585 BCMI_TSCE_XGXS_TX_PI_CTL6r, 14586 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14587 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 14588 BCMI_TSCE_XGXS_TX_PI_CTL6r_fields, 14589 #else 14590 0, 14591 #endif 14592 #endif 14593 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14594 PHYMOD_SYMBOL_FLAG_REGISTER, 14595 "TX_PI_CTL6r", 14596 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14597 "TX_PI_COM_CONTROL_6", 14598 NULL, 14599 #endif 14600 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14601 0x0, /* 0 */ 14602 0, 14603 #endif 14604 }, 14605 { 14606 BCMI_TSCE_XGXS_TX_PI_STS0r, 14607 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14608 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 14609 BCMI_TSCE_XGXS_TX_PI_STS0r_fields, 14610 #else 14611 0, 14612 #endif 14613 #endif 14614 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14615 PHYMOD_SYMBOL_FLAG_REGISTER, 14616 "TX_PI_STS0r", 14617 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14618 "TX_PI_COM_STATUS_0", 14619 NULL, 14620 #endif 14621 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14622 0x0, /* 0 */ 14623 0, 14624 #endif 14625 }, 14626 { 14627 BCMI_TSCE_XGXS_TX_PI_STS1r, 14628 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14629 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 14630 BCMI_TSCE_XGXS_TX_PI_STS1r_fields, 14631 #else 14632 0, 14633 #endif 14634 #endif 14635 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14636 PHYMOD_SYMBOL_FLAG_REGISTER, 14637 "TX_PI_STS1r", 14638 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14639 "TX_PI_COM_STATUS_1", 14640 NULL, 14641 #endif 14642 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14643 0x0, /* 0 */ 14644 0, 14645 #endif 14646 }, 14647 { 14648 BCMI_TSCE_XGXS_TX_PI_STS2r, 14649 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14650 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 14651 BCMI_TSCE_XGXS_TX_PI_STS2r_fields, 14652 #else 14653 0, 14654 #endif 14655 #endif 14656 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14657 PHYMOD_SYMBOL_FLAG_REGISTER, 14658 "TX_PI_STS2r", 14659 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14660 "TX_PI_COM_STATUS_2", 14661 NULL, 14662 #endif 14663 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14664 0x0, /* 0 */ 14665 0, 14666 #endif 14667 }, 14668 { 14669 BCMI_TSCE_XGXS_TX_PI_STS3r, 14670 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14671 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 14672 BCMI_TSCE_XGXS_TX_PI_STS3r_fields, 14673 #else 14674 0, 14675 #endif 14676 #endif 14677 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14678 PHYMOD_SYMBOL_FLAG_REGISTER, 14679 "TX_PI_STS3r", 14680 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14681 "TX_PI_COM_STATUS_3", 14682 NULL, 14683 #endif 14684 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14685 0x0, /* 0 */ 14686 0, 14687 #endif 14688 }, 14689 { 14690 BCMI_TSCE_XGXS_CKRST_OSR_MODE_CTLr, 14691 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14692 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 14693 BCMI_TSCE_XGXS_CKRST_OSR_MODE_CTLr_fields, 14694 #else 14695 0, 14696 #endif 14697 #endif 14698 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14699 PHYMOD_SYMBOL_FLAG_REGISTER, 14700 "CKRST_OSR_MODE_CTLr", 14701 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14702 "CKRST_CTRL_OSR_MODE_CONTROL", 14703 NULL, 14704 #endif 14705 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14706 0x0, /* 0 */ 14707 0, 14708 #endif 14709 }, 14710 { 14711 BCMI_TSCE_XGXS_CKRST_LN_CLK_RST_N_PWRDWN_CTLr, 14712 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14713 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 14714 BCMI_TSCE_XGXS_CKRST_LN_CLK_RST_N_PWRDWN_CTLr_fields, 14715 #else 14716 0, 14717 #endif 14718 #endif 14719 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14720 PHYMOD_SYMBOL_FLAG_REGISTER, 14721 "CKRST_LN_CLK_RST_N_PWRDWN_CTLr", 14722 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14723 "CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL", 14724 NULL, 14725 #endif 14726 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14727 0x0, /* 0 */ 14728 0, 14729 #endif 14730 }, 14731 { 14732 BCMI_TSCE_XGXS_CKRST_LN_AFE_RST_PWRDWN_CTL_CTLr, 14733 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14734 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 14735 BCMI_TSCE_XGXS_CKRST_LN_AFE_RST_PWRDWN_CTL_CTLr_fields, 14736 #else 14737 0, 14738 #endif 14739 #endif 14740 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14741 PHYMOD_SYMBOL_FLAG_REGISTER, 14742 "CKRST_LN_AFE_RST_PWRDWN_CTL_CTLr", 14743 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14744 "CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL", 14745 NULL, 14746 #endif 14747 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14748 0x0, /* 0 */ 14749 0, 14750 #endif 14751 }, 14752 { 14753 BCMI_TSCE_XGXS_CKRST_LN_RST_N_PWRDN_PIN_KILL_CTLr, 14754 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14755 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 14756 BCMI_TSCE_XGXS_CKRST_LN_RST_N_PWRDN_PIN_KILL_CTLr_fields, 14757 #else 14758 0, 14759 #endif 14760 #endif 14761 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14762 PHYMOD_SYMBOL_FLAG_REGISTER, 14763 "CKRST_LN_RST_N_PWRDN_PIN_KILL_CTLr", 14764 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14765 "CKRST_CTRL_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL", 14766 NULL, 14767 #endif 14768 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14769 0x0, /* 0 */ 14770 0, 14771 #endif 14772 }, 14773 { 14774 BCMI_TSCE_XGXS_CKRST_LN_DBG_RST_CTLr, 14775 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14776 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 14777 BCMI_TSCE_XGXS_CKRST_LN_DBG_RST_CTLr_fields, 14778 #else 14779 0, 14780 #endif 14781 #endif 14782 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14783 PHYMOD_SYMBOL_FLAG_REGISTER, 14784 "CKRST_LN_DBG_RST_CTLr", 14785 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14786 "CKRST_CTRL_LANE_DEBUG_RESET_CONTROL", 14787 NULL, 14788 #endif 14789 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14790 0x303, /* 771 */ 14791 0, 14792 #endif 14793 }, 14794 { 14795 BCMI_TSCE_XGXS_CKRST_UC_ACK_LN_CTLr, 14796 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14797 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 14798 BCMI_TSCE_XGXS_CKRST_UC_ACK_LN_CTLr_fields, 14799 #else 14800 0, 14801 #endif 14802 #endif 14803 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14804 PHYMOD_SYMBOL_FLAG_REGISTER, 14805 "CKRST_UC_ACK_LN_CTLr", 14806 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14807 "CKRST_CTRL_UC_ACK_LANE_CONTROL", 14808 NULL, 14809 #endif 14810 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14811 0x0, /* 0 */ 14812 0, 14813 #endif 14814 }, 14815 { 14816 BCMI_TSCE_XGXS_CKRST_LN_RST_OCC_CTLr, 14817 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14818 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 14819 BCMI_TSCE_XGXS_CKRST_LN_RST_OCC_CTLr_fields, 14820 #else 14821 0, 14822 #endif 14823 #endif 14824 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14825 PHYMOD_SYMBOL_FLAG_REGISTER, 14826 "CKRST_LN_RST_OCC_CTLr", 14827 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14828 "CKRST_CTRL_LANE_REG_RESET_OCCURRED_CONTROL", 14829 NULL, 14830 #endif 14831 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14832 0x1, /* 1 */ 14833 0, 14834 #endif 14835 }, 14836 { 14837 BCMI_TSCE_XGXS_CKRST_CLK_N_RST_DBG_CTLr, 14838 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14839 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 14840 BCMI_TSCE_XGXS_CKRST_CLK_N_RST_DBG_CTLr_fields, 14841 #else 14842 0, 14843 #endif 14844 #endif 14845 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14846 PHYMOD_SYMBOL_FLAG_REGISTER, 14847 "CKRST_CLK_N_RST_DBG_CTLr", 14848 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14849 "CKRST_CTRL_CLOCK_N_RESET_DEBUG_CONTROL", 14850 NULL, 14851 #endif 14852 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14853 0x0, /* 0 */ 14854 0, 14855 #endif 14856 }, 14857 { 14858 BCMI_TSCE_XGXS_CKRST_PMD_LN_MODE_STSr, 14859 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14860 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 14861 BCMI_TSCE_XGXS_CKRST_PMD_LN_MODE_STSr_fields, 14862 #else 14863 0, 14864 #endif 14865 #endif 14866 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14867 PHYMOD_SYMBOL_FLAG_REGISTER, 14868 "CKRST_PMD_LN_MODE_STSr", 14869 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14870 "CKRST_CTRL_PMD_LANE_MODE_STATUS", 14871 NULL, 14872 #endif 14873 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14874 0x0, /* 0 */ 14875 0, 14876 #endif 14877 }, 14878 { 14879 BCMI_TSCE_XGXS_CKRST_LN_DP_RST_ST_STSr, 14880 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14881 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 14882 BCMI_TSCE_XGXS_CKRST_LN_DP_RST_ST_STSr_fields, 14883 #else 14884 0, 14885 #endif 14886 #endif 14887 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14888 PHYMOD_SYMBOL_FLAG_REGISTER, 14889 "CKRST_LN_DP_RST_ST_STSr", 14890 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14891 "CKRST_CTRL_LANE_DP_RESET_STATE_STATUS", 14892 NULL, 14893 #endif 14894 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14895 0x7, /* 7 */ 14896 0, 14897 #endif 14898 }, 14899 { 14900 BCMI_TSCE_XGXS_CKRST_LN_MCST_MASK_CTLr, 14901 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14902 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 14903 BCMI_TSCE_XGXS_CKRST_LN_MCST_MASK_CTLr_fields, 14904 #else 14905 0, 14906 #endif 14907 #endif 14908 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14909 PHYMOD_SYMBOL_FLAG_REGISTER, 14910 "CKRST_LN_MCST_MASK_CTLr", 14911 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14912 "CKRST_CTRL_LANE_MULTICAST_MASK_CONTROL", 14913 NULL, 14914 #endif 14915 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14916 0x0, /* 0 */ 14917 0, 14918 #endif 14919 }, 14920 { 14921 BCMI_TSCE_XGXS_CKRST_OSR_MODE_STSr, 14922 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14923 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 14924 BCMI_TSCE_XGXS_CKRST_OSR_MODE_STSr_fields, 14925 #else 14926 0, 14927 #endif 14928 #endif 14929 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14930 PHYMOD_SYMBOL_FLAG_REGISTER, 14931 "CKRST_OSR_MODE_STSr", 14932 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14933 "CKRST_CTRL_OSR_MODE_STATUS", 14934 NULL, 14935 #endif 14936 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14937 0x0, /* 0 */ 14938 0, 14939 #endif 14940 }, 14941 { 14942 BCMI_TSCE_XGXS_CKRST_OSR_MODE_PIN_STSr, 14943 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14944 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 14945 BCMI_TSCE_XGXS_CKRST_OSR_MODE_PIN_STSr_fields, 14946 #else 14947 0, 14948 #endif 14949 #endif 14950 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14951 PHYMOD_SYMBOL_FLAG_REGISTER, 14952 "CKRST_OSR_MODE_PIN_STSr", 14953 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14954 "CKRST_CTRL_OSR_MODE_PIN_STATUS", 14955 NULL, 14956 #endif 14957 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14958 0x0, /* 0 */ 14959 0, 14960 #endif 14961 }, 14962 { 14963 BCMI_TSCE_XGXS_CKRST_LN_S_RSTB_CTLr, 14964 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14965 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 14966 BCMI_TSCE_XGXS_CKRST_LN_S_RSTB_CTLr_fields, 14967 #else 14968 0, 14969 #endif 14970 #endif 14971 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14972 PHYMOD_SYMBOL_FLAG_REGISTER, 14973 "CKRST_LN_S_RSTB_CTLr", 14974 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14975 "CKRST_CTRL_LN_S_RSTB_CONTROL", 14976 NULL, 14977 #endif 14978 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14979 0x1, /* 1 */ 14980 0, 14981 #endif 14982 }, 14983 { 14984 BCMI_TSCE_XGXS_AMS_RX_CTL0r, 14985 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14986 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 14987 BCMI_TSCE_XGXS_AMS_RX_CTL0r_fields, 14988 #else 14989 0, 14990 #endif 14991 #endif 14992 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14993 PHYMOD_SYMBOL_FLAG_REGISTER, 14994 "AMS_RX_CTL0r", 14995 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14996 "AMS_RX_CONTROL_0", 14997 NULL, 14998 #endif 14999 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15000 0x10, /* 16 */ 15001 0, 15002 #endif 15003 }, 15004 { 15005 BCMI_TSCE_XGXS_AMS_RX_CTL1r, 15006 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15007 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 15008 BCMI_TSCE_XGXS_AMS_RX_CTL1r_fields, 15009 #else 15010 0, 15011 #endif 15012 #endif 15013 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15014 PHYMOD_SYMBOL_FLAG_REGISTER, 15015 "AMS_RX_CTL1r", 15016 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15017 "AMS_RX_CONTROL_1", 15018 NULL, 15019 #endif 15020 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15021 0x0, /* 0 */ 15022 0, 15023 #endif 15024 }, 15025 { 15026 BCMI_TSCE_XGXS_AMS_RX_CTL2r, 15027 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15028 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 15029 BCMI_TSCE_XGXS_AMS_RX_CTL2r_fields, 15030 #else 15031 0, 15032 #endif 15033 #endif 15034 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15035 PHYMOD_SYMBOL_FLAG_REGISTER, 15036 "AMS_RX_CTL2r", 15037 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15038 "AMS_RX_CONTROL_2", 15039 NULL, 15040 #endif 15041 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15042 0x2800, /* 10240 */ 15043 0, 15044 #endif 15045 }, 15046 { 15047 BCMI_TSCE_XGXS_AMS_RX_CTL3r, 15048 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15049 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 15050 BCMI_TSCE_XGXS_AMS_RX_CTL3r_fields, 15051 #else 15052 0, 15053 #endif 15054 #endif 15055 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15056 PHYMOD_SYMBOL_FLAG_REGISTER, 15057 "AMS_RX_CTL3r", 15058 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15059 "AMS_RX_CONTROL_3", 15060 NULL, 15061 #endif 15062 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15063 0x0, /* 0 */ 15064 0, 15065 #endif 15066 }, 15067 { 15068 BCMI_TSCE_XGXS_AMS_RX_CTL4r, 15069 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15070 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 15071 BCMI_TSCE_XGXS_AMS_RX_CTL4r_fields, 15072 #else 15073 0, 15074 #endif 15075 #endif 15076 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15077 PHYMOD_SYMBOL_FLAG_REGISTER, 15078 "AMS_RX_CTL4r", 15079 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15080 "AMS_RX_CONTROL_4", 15081 NULL, 15082 #endif 15083 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15084 0x0, /* 0 */ 15085 0, 15086 #endif 15087 }, 15088 { 15089 BCMI_TSCE_XGXS_AMS_RX_INTCTLr, 15090 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15091 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 15092 BCMI_TSCE_XGXS_AMS_RX_INTCTLr_fields, 15093 #else 15094 0, 15095 #endif 15096 #endif 15097 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15098 PHYMOD_SYMBOL_FLAG_REGISTER, 15099 "AMS_RX_INTCTLr", 15100 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15101 "AMS_RX_INTCTRL", 15102 NULL, 15103 #endif 15104 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15105 0x0, /* 0 */ 15106 0, 15107 #endif 15108 }, 15109 { 15110 BCMI_TSCE_XGXS_AMS_RX_STSr, 15111 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15112 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 15113 BCMI_TSCE_XGXS_AMS_RX_STSr_fields, 15114 #else 15115 0, 15116 #endif 15117 #endif 15118 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15119 PHYMOD_SYMBOL_FLAG_REGISTER, 15120 "AMS_RX_STSr", 15121 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15122 "AMS_RX_STATUS", 15123 NULL, 15124 #endif 15125 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15126 0x8000, /* 32768 */ 15127 0, 15128 #endif 15129 }, 15130 { 15131 BCMI_TSCE_XGXS_AMS_TX_CTL0r, 15132 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15133 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 15134 BCMI_TSCE_XGXS_AMS_TX_CTL0r_fields, 15135 #else 15136 0, 15137 #endif 15138 #endif 15139 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15140 PHYMOD_SYMBOL_FLAG_REGISTER, 15141 "AMS_TX_CTL0r", 15142 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15143 "AMS_TX_CONTROL_0", 15144 NULL, 15145 #endif 15146 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15147 0x80, /* 128 */ 15148 0, 15149 #endif 15150 }, 15151 { 15152 BCMI_TSCE_XGXS_AMS_TX_CTL1r, 15153 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15154 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 15155 BCMI_TSCE_XGXS_AMS_TX_CTL1r_fields, 15156 #else 15157 0, 15158 #endif 15159 #endif 15160 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15161 PHYMOD_SYMBOL_FLAG_REGISTER, 15162 "AMS_TX_CTL1r", 15163 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15164 "AMS_TX_CONTROL_1", 15165 NULL, 15166 #endif 15167 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15168 0x0, /* 0 */ 15169 0, 15170 #endif 15171 }, 15172 { 15173 BCMI_TSCE_XGXS_AMS_TX_CTL2r, 15174 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15175 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 15176 BCMI_TSCE_XGXS_AMS_TX_CTL2r_fields, 15177 #else 15178 0, 15179 #endif 15180 #endif 15181 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15182 PHYMOD_SYMBOL_FLAG_REGISTER, 15183 "AMS_TX_CTL2r", 15184 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15185 "AMS_TX_CONTROL_2", 15186 NULL, 15187 #endif 15188 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15189 0xc, /* 12 */ 15190 0, 15191 #endif 15192 }, 15193 { 15194 BCMI_TSCE_XGXS_AMS_TX_INTCTLr, 15195 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15196 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 15197 BCMI_TSCE_XGXS_AMS_TX_INTCTLr_fields, 15198 #else 15199 0, 15200 #endif 15201 #endif 15202 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15203 PHYMOD_SYMBOL_FLAG_REGISTER, 15204 "AMS_TX_INTCTLr", 15205 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15206 "AMS_TX_INTCTRL", 15207 NULL, 15208 #endif 15209 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15210 0x0, /* 0 */ 15211 0, 15212 #endif 15213 }, 15214 { 15215 BCMI_TSCE_XGXS_AMS_TX_STSr, 15216 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15217 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 15218 BCMI_TSCE_XGXS_AMS_TX_STSr_fields, 15219 #else 15220 0, 15221 #endif 15222 #endif 15223 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15224 PHYMOD_SYMBOL_FLAG_REGISTER, 15225 "AMS_TX_STSr", 15226 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15227 "AMS_TX_STATUS", 15228 NULL, 15229 #endif 15230 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15231 0x0, /* 0 */ 15232 0, 15233 #endif 15234 }, 15235 { 15236 BCMI_TSCE_XGXS_AMS_CTL0r, 15237 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15238 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 15239 BCMI_TSCE_XGXS_AMS_CTL0r_fields, 15240 #else 15241 0, 15242 #endif 15243 #endif 15244 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15245 PHYMOD_SYMBOL_FLAG_REGISTER, 15246 "AMS_CTL0r", 15247 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15248 "AMS_COM_CONTROL_0", 15249 NULL, 15250 #endif 15251 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15252 0x0, /* 0 */ 15253 0, 15254 #endif 15255 }, 15256 { 15257 BCMI_TSCE_XGXS_AMS_CTL1r, 15258 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15259 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 15260 BCMI_TSCE_XGXS_AMS_CTL1r_fields, 15261 #else 15262 0, 15263 #endif 15264 #endif 15265 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15266 PHYMOD_SYMBOL_FLAG_REGISTER, 15267 "AMS_CTL1r", 15268 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15269 "AMS_COM_CONTROL_1", 15270 NULL, 15271 #endif 15272 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15273 0x8001, /* 32769 */ 15274 0, 15275 #endif 15276 }, 15277 { 15278 BCMI_TSCE_XGXS_AMS_CTL2r, 15279 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15280 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 15281 BCMI_TSCE_XGXS_AMS_CTL2r_fields, 15282 #else 15283 0, 15284 #endif 15285 #endif 15286 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15287 PHYMOD_SYMBOL_FLAG_REGISTER, 15288 "AMS_CTL2r", 15289 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15290 "AMS_COM_CONTROL_2", 15291 NULL, 15292 #endif 15293 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15294 0x16, /* 22 */ 15295 0, 15296 #endif 15297 }, 15298 { 15299 BCMI_TSCE_XGXS_AMS_CTL3r, 15300 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15301 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 15302 BCMI_TSCE_XGXS_AMS_CTL3r_fields, 15303 #else 15304 0, 15305 #endif 15306 #endif 15307 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15308 PHYMOD_SYMBOL_FLAG_REGISTER, 15309 "AMS_CTL3r", 15310 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15311 "AMS_COM_CONTROL_3", 15312 NULL, 15313 #endif 15314 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15315 0x0, /* 0 */ 15316 0, 15317 #endif 15318 }, 15319 { 15320 BCMI_TSCE_XGXS_AMS_CTL4r, 15321 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15322 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 15323 BCMI_TSCE_XGXS_AMS_CTL4r_fields, 15324 #else 15325 0, 15326 #endif 15327 #endif 15328 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15329 PHYMOD_SYMBOL_FLAG_REGISTER, 15330 "AMS_CTL4r", 15331 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15332 "AMS_COM_CONTROL_4", 15333 NULL, 15334 #endif 15335 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15336 0x77, /* 119 */ 15337 0, 15338 #endif 15339 }, 15340 { 15341 BCMI_TSCE_XGXS_AMS_CTL5r, 15342 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15343 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 15344 BCMI_TSCE_XGXS_AMS_CTL5r_fields, 15345 #else 15346 0, 15347 #endif 15348 #endif 15349 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15350 PHYMOD_SYMBOL_FLAG_REGISTER, 15351 "AMS_CTL5r", 15352 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15353 "AMS_COM_CONTROL_5", 15354 NULL, 15355 #endif 15356 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15357 0x7bc0, /* 31680 */ 15358 0, 15359 #endif 15360 }, 15361 { 15362 BCMI_TSCE_XGXS_AMS_CTL6r, 15363 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15364 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 15365 BCMI_TSCE_XGXS_AMS_CTL6r_fields, 15366 #else 15367 0, 15368 #endif 15369 #endif 15370 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15371 PHYMOD_SYMBOL_FLAG_REGISTER, 15372 "AMS_CTL6r", 15373 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15374 "AMS_COM_CONTROL_6", 15375 NULL, 15376 #endif 15377 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15378 0x45c0, /* 17856 */ 15379 0, 15380 #endif 15381 }, 15382 { 15383 BCMI_TSCE_XGXS_AMS_CTL7r, 15384 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15385 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 15386 BCMI_TSCE_XGXS_AMS_CTL7r_fields, 15387 #else 15388 0, 15389 #endif 15390 #endif 15391 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15392 PHYMOD_SYMBOL_FLAG_REGISTER, 15393 "AMS_CTL7r", 15394 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15395 "AMS_COM_CONTROL_7", 15396 NULL, 15397 #endif 15398 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15399 0x0, /* 0 */ 15400 0, 15401 #endif 15402 }, 15403 { 15404 BCMI_TSCE_XGXS_AMS_CTL8r, 15405 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15406 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 15407 BCMI_TSCE_XGXS_AMS_CTL8r_fields, 15408 #else 15409 0, 15410 #endif 15411 #endif 15412 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15413 PHYMOD_SYMBOL_FLAG_REGISTER, 15414 "AMS_CTL8r", 15415 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15416 "AMS_COM_CONTROL_8", 15417 NULL, 15418 #endif 15419 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15420 0x0, /* 0 */ 15421 0, 15422 #endif 15423 }, 15424 { 15425 BCMI_TSCE_XGXS_AMS_INTCTLr, 15426 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15427 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 15428 BCMI_TSCE_XGXS_AMS_INTCTLr_fields, 15429 #else 15430 0, 15431 #endif 15432 #endif 15433 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15434 PHYMOD_SYMBOL_FLAG_REGISTER, 15435 "AMS_INTCTLr", 15436 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15437 "AMS_COM_INTCTRL", 15438 NULL, 15439 #endif 15440 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15441 0x0, /* 0 */ 15442 0, 15443 #endif 15444 }, 15445 { 15446 BCMI_TSCE_XGXS_AMS_STSr, 15447 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15448 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 15449 BCMI_TSCE_XGXS_AMS_STSr_fields, 15450 #else 15451 0, 15452 #endif 15453 #endif 15454 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15455 PHYMOD_SYMBOL_FLAG_REGISTER, 15456 "AMS_STSr", 15457 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15458 "AMS_COM_STATUS", 15459 NULL, 15460 #endif 15461 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15462 0x300a, /* 12298 */ 15463 0, 15464 #endif 15465 }, 15466 { 15467 BCMI_TSCE_XGXS_SIGDET_CTL0r, 15468 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15469 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 15470 BCMI_TSCE_XGXS_SIGDET_CTL0r_fields, 15471 #else 15472 0, 15473 #endif 15474 #endif 15475 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15476 PHYMOD_SYMBOL_FLAG_REGISTER, 15477 "SIGDET_CTL0r", 15478 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15479 "SIGDET_CTRL_0", 15480 NULL, 15481 #endif 15482 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15483 0x1109, /* 4361 */ 15484 0, 15485 #endif 15486 }, 15487 { 15488 BCMI_TSCE_XGXS_SIGDET_CTL1r, 15489 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15490 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 15491 BCMI_TSCE_XGXS_SIGDET_CTL1r_fields, 15492 #else 15493 0, 15494 #endif 15495 #endif 15496 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15497 PHYMOD_SYMBOL_FLAG_REGISTER, 15498 "SIGDET_CTL1r", 15499 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15500 "SIGDET_CTRL_1", 15501 NULL, 15502 #endif 15503 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15504 0xa008, /* 40968 */ 15505 0, 15506 #endif 15507 }, 15508 { 15509 BCMI_TSCE_XGXS_SIGDET_CTL2r, 15510 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15511 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 15512 BCMI_TSCE_XGXS_SIGDET_CTL2r_fields, 15513 #else 15514 0, 15515 #endif 15516 #endif 15517 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15518 PHYMOD_SYMBOL_FLAG_REGISTER, 15519 "SIGDET_CTL2r", 15520 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15521 "SIGDET_CTRL_2", 15522 NULL, 15523 #endif 15524 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15525 0x3f22, /* 16162 */ 15526 0, 15527 #endif 15528 }, 15529 { 15530 BCMI_TSCE_XGXS_SIGDET_STS0r, 15531 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15532 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 15533 BCMI_TSCE_XGXS_SIGDET_STS0r_fields, 15534 #else 15535 0, 15536 #endif 15537 #endif 15538 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15539 PHYMOD_SYMBOL_FLAG_REGISTER, 15540 "SIGDET_STS0r", 15541 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15542 "SIGDET_STATUS_0", 15543 NULL, 15544 #endif 15545 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15546 0x200, /* 512 */ 15547 0, 15548 #endif 15549 }, 15550 { 15551 BCMI_TSCE_XGXS_TLB_RX_PRBS_CHK_CNT_CFGr, 15552 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15553 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 15554 BCMI_TSCE_XGXS_TLB_RX_PRBS_CHK_CNT_CFGr_fields, 15555 #else 15556 0, 15557 #endif 15558 #endif 15559 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15560 PHYMOD_SYMBOL_FLAG_REGISTER, 15561 "TLB_RX_PRBS_CHK_CNT_CFGr", 15562 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15563 "TLB_RX_PRBS_CHK_CNT_CONFIG", 15564 NULL, 15565 #endif 15566 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15567 0x602, /* 1538 */ 15568 0, 15569 #endif 15570 }, 15571 { 15572 BCMI_TSCE_XGXS_TLB_RX_PRBS_CHK_CFGr, 15573 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15574 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 15575 BCMI_TSCE_XGXS_TLB_RX_PRBS_CHK_CFGr_fields, 15576 #else 15577 0, 15578 #endif 15579 #endif 15580 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15581 PHYMOD_SYMBOL_FLAG_REGISTER, 15582 "TLB_RX_PRBS_CHK_CFGr", 15583 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15584 "TLB_RX_PRBS_CHK_CONFIG", 15585 NULL, 15586 #endif 15587 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15588 0xa, /* 10 */ 15589 0, 15590 #endif 15591 }, 15592 { 15593 BCMI_TSCE_XGXS_TLB_RX_DIG_LPBK_CFGr, 15594 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15595 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 15596 BCMI_TSCE_XGXS_TLB_RX_DIG_LPBK_CFGr_fields, 15597 #else 15598 0, 15599 #endif 15600 #endif 15601 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15602 PHYMOD_SYMBOL_FLAG_REGISTER, 15603 "TLB_RX_DIG_LPBK_CFGr", 15604 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15605 "TLB_RX_DIG_LPBK_CONFIG", 15606 NULL, 15607 #endif 15608 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15609 0x6, /* 6 */ 15610 0, 15611 #endif 15612 }, 15613 { 15614 BCMI_TSCE_XGXS_TLB_RX_TLB_RX_MISC_CFGr, 15615 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15616 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 15617 BCMI_TSCE_XGXS_TLB_RX_TLB_RX_MISC_CFGr_fields, 15618 #else 15619 0, 15620 #endif 15621 #endif 15622 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15623 PHYMOD_SYMBOL_FLAG_REGISTER, 15624 "TLB_RX_TLB_RX_MISC_CFGr", 15625 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15626 "TLB_RX_TLB_RX_MISC_CONFIG", 15627 NULL, 15628 #endif 15629 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15630 0x0, /* 0 */ 15631 0, 15632 #endif 15633 }, 15634 { 15635 BCMI_TSCE_XGXS_TLB_RX_PRBS_CHK_EN_TMR_CTLr, 15636 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15637 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 15638 BCMI_TSCE_XGXS_TLB_RX_PRBS_CHK_EN_TMR_CTLr_fields, 15639 #else 15640 0, 15641 #endif 15642 #endif 15643 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15644 PHYMOD_SYMBOL_FLAG_REGISTER, 15645 "TLB_RX_PRBS_CHK_EN_TMR_CTLr", 15646 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15647 "TLB_RX_PRBS_CHK_EN_TIMER_CONTROL", 15648 NULL, 15649 #endif 15650 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15651 0x0, /* 0 */ 15652 0, 15653 #endif 15654 }, 15655 { 15656 BCMI_TSCE_XGXS_TLB_RX_DIG_LPBK_PD_STSr, 15657 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15658 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 15659 BCMI_TSCE_XGXS_TLB_RX_DIG_LPBK_PD_STSr_fields, 15660 #else 15661 0, 15662 #endif 15663 #endif 15664 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15665 PHYMOD_SYMBOL_FLAG_REGISTER, 15666 "TLB_RX_DIG_LPBK_PD_STSr", 15667 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15668 "TLB_RX_DIG_LPBK_PD_STATUS", 15669 NULL, 15670 #endif 15671 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15672 0x2, /* 2 */ 15673 0, 15674 #endif 15675 }, 15676 { 15677 BCMI_TSCE_XGXS_TLB_RX_PRBS_CHK_LOCK_STSr, 15678 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15679 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 15680 BCMI_TSCE_XGXS_TLB_RX_PRBS_CHK_LOCK_STSr_fields, 15681 #else 15682 0, 15683 #endif 15684 #endif 15685 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15686 PHYMOD_SYMBOL_FLAG_REGISTER, 15687 "TLB_RX_PRBS_CHK_LOCK_STSr", 15688 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15689 "TLB_RX_PRBS_CHK_LOCK_STATUS", 15690 NULL, 15691 #endif 15692 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15693 0x0, /* 0 */ 15694 0, 15695 #endif 15696 }, 15697 { 15698 BCMI_TSCE_XGXS_TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr, 15699 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15700 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 15701 BCMI_TSCE_XGXS_TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr_fields, 15702 #else 15703 0, 15704 #endif 15705 #endif 15706 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15707 PHYMOD_SYMBOL_FLAG_REGISTER, 15708 "TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr", 15709 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15710 "TLB_RX_PRBS_CHK_ERR_CNT_MSB_STATUS", 15711 NULL, 15712 #endif 15713 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15714 0x8000, /* 32768 */ 15715 0, 15716 #endif 15717 }, 15718 { 15719 BCMI_TSCE_XGXS_TLB_RX_PRBS_CHK_ERR_CNT_LSB_STSr, 15720 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15721 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 15722 BCMI_TSCE_XGXS_TLB_RX_PRBS_CHK_ERR_CNT_LSB_STSr_fields, 15723 #else 15724 0, 15725 #endif 15726 #endif 15727 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15728 PHYMOD_SYMBOL_FLAG_REGISTER, 15729 "TLB_RX_PRBS_CHK_ERR_CNT_LSB_STSr", 15730 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15731 "TLB_RX_PRBS_CHK_ERR_CNT_LSB_STATUS", 15732 NULL, 15733 #endif 15734 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15735 0x0, /* 0 */ 15736 0, 15737 #endif 15738 }, 15739 { 15740 BCMI_TSCE_XGXS_TLB_RX_PMD_RX_LOCK_STSr, 15741 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15742 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 15743 BCMI_TSCE_XGXS_TLB_RX_PMD_RX_LOCK_STSr_fields, 15744 #else 15745 0, 15746 #endif 15747 #endif 15748 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15749 PHYMOD_SYMBOL_FLAG_REGISTER, 15750 "TLB_RX_PMD_RX_LOCK_STSr", 15751 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15752 "TLB_RX_PMD_RX_LOCK_STATUS", 15753 NULL, 15754 #endif 15755 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15756 0x0, /* 0 */ 15757 0, 15758 #endif 15759 }, 15760 { 15761 BCMI_TSCE_XGXS_TLB_TX_PATGEN_CFGr, 15762 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15763 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 15764 BCMI_TSCE_XGXS_TLB_TX_PATGEN_CFGr_fields, 15765 #else 15766 0, 15767 #endif 15768 #endif 15769 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15770 PHYMOD_SYMBOL_FLAG_REGISTER, 15771 "TLB_TX_PATGEN_CFGr", 15772 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15773 "TLB_TX_PATT_GEN_CONFIG", 15774 NULL, 15775 #endif 15776 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15777 0xb000, /* 45056 */ 15778 0, 15779 #endif 15780 }, 15781 { 15782 BCMI_TSCE_XGXS_TLB_TX_PRBS_GEN_CFGr, 15783 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15784 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 15785 BCMI_TSCE_XGXS_TLB_TX_PRBS_GEN_CFGr_fields, 15786 #else 15787 0, 15788 #endif 15789 #endif 15790 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15791 PHYMOD_SYMBOL_FLAG_REGISTER, 15792 "TLB_TX_PRBS_GEN_CFGr", 15793 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15794 "TLB_TX_PRBS_GEN_CONFIG", 15795 NULL, 15796 #endif 15797 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15798 0xa, /* 10 */ 15799 0, 15800 #endif 15801 }, 15802 { 15803 BCMI_TSCE_XGXS_TLB_TX_RMT_LPBK_CFGr, 15804 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15805 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 15806 BCMI_TSCE_XGXS_TLB_TX_RMT_LPBK_CFGr_fields, 15807 #else 15808 0, 15809 #endif 15810 #endif 15811 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15812 PHYMOD_SYMBOL_FLAG_REGISTER, 15813 "TLB_TX_RMT_LPBK_CFGr", 15814 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15815 "TLB_TX_RMT_LPBK_CONFIG", 15816 NULL, 15817 #endif 15818 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15819 0x2, /* 2 */ 15820 0, 15821 #endif 15822 }, 15823 { 15824 BCMI_TSCE_XGXS_TLB_TX_TLB_TX_MISC_CFGr, 15825 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15826 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 15827 BCMI_TSCE_XGXS_TLB_TX_TLB_TX_MISC_CFGr_fields, 15828 #else 15829 0, 15830 #endif 15831 #endif 15832 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15833 PHYMOD_SYMBOL_FLAG_REGISTER, 15834 "TLB_TX_TLB_TX_MISC_CFGr", 15835 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15836 "TLB_TX_TLB_TX_MISC_CONFIG", 15837 NULL, 15838 #endif 15839 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15840 0x0, /* 0 */ 15841 0, 15842 #endif 15843 }, 15844 { 15845 BCMI_TSCE_XGXS_TLB_TX_TX_PI_LOOP_TIMING_CFGr, 15846 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15847 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 15848 BCMI_TSCE_XGXS_TLB_TX_TX_PI_LOOP_TIMING_CFGr_fields, 15849 #else 15850 0, 15851 #endif 15852 #endif 15853 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15854 PHYMOD_SYMBOL_FLAG_REGISTER, 15855 "TLB_TX_TX_PI_LOOP_TIMING_CFGr", 15856 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15857 "TLB_TX_TX_PI_LOOP_TIMING_CONFIG", 15858 NULL, 15859 #endif 15860 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15861 0x0, /* 0 */ 15862 0, 15863 #endif 15864 }, 15865 { 15866 BCMI_TSCE_XGXS_TLB_TX_RMT_LPBK_PD_STSr, 15867 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15868 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 15869 BCMI_TSCE_XGXS_TLB_TX_RMT_LPBK_PD_STSr_fields, 15870 #else 15871 0, 15872 #endif 15873 #endif 15874 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15875 PHYMOD_SYMBOL_FLAG_REGISTER, 15876 "TLB_TX_RMT_LPBK_PD_STSr", 15877 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15878 "TLB_TX_RMT_LPBK_PD_STATUS", 15879 NULL, 15880 #endif 15881 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15882 0x2, /* 2 */ 15883 0, 15884 #endif 15885 }, 15886 { 15887 BCMI_TSCE_XGXS_DIG_REVID0r, 15888 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15889 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 15890 BCMI_TSCE_XGXS_DIG_REVID0r_fields, 15891 #else 15892 0, 15893 #endif 15894 #endif 15895 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15896 PHYMOD_SYMBOL_FLAG_REGISTER, 15897 "DIG_REVID0r", 15898 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15899 "DIG_COM_REVID0", 15900 NULL, 15901 #endif 15902 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15903 0x2da, /* 730 */ 15904 0, 15905 #endif 15906 }, 15907 { 15908 BCMI_TSCE_XGXS_DIG_RST_CTL_PMDr, 15909 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15910 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 15911 BCMI_TSCE_XGXS_DIG_RST_CTL_PMDr_fields, 15912 #else 15913 0, 15914 #endif 15915 #endif 15916 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15917 PHYMOD_SYMBOL_FLAG_REGISTER, 15918 "DIG_RST_CTL_PMDr", 15919 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15920 "DIG_COM_RESET_CONTROL_PMD", 15921 NULL, 15922 #endif 15923 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15924 0x1, /* 1 */ 15925 0, 15926 #endif 15927 }, 15928 { 15929 BCMI_TSCE_XGXS_DIG_RST_CTL_CORE_DPr, 15930 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15931 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 15932 BCMI_TSCE_XGXS_DIG_RST_CTL_CORE_DPr_fields, 15933 #else 15934 0, 15935 #endif 15936 #endif 15937 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15938 PHYMOD_SYMBOL_FLAG_REGISTER, 15939 "DIG_RST_CTL_CORE_DPr", 15940 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15941 "DIG_COM_RESET_CONTROL_CORE_DP", 15942 NULL, 15943 #endif 15944 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15945 0x4000, /* 16384 */ 15946 0, 15947 #endif 15948 }, 15949 { 15950 BCMI_TSCE_XGXS_DIG_CORE_MCST_MASK_CTLr, 15951 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15952 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 15953 BCMI_TSCE_XGXS_DIG_CORE_MCST_MASK_CTLr_fields, 15954 #else 15955 0, 15956 #endif 15957 #endif 15958 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15959 PHYMOD_SYMBOL_FLAG_REGISTER, 15960 "DIG_CORE_MCST_MASK_CTLr", 15961 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15962 "DIG_COM_CORE_MULTICAST_MASK_CONRTOL", 15963 NULL, 15964 #endif 15965 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15966 0x0, /* 0 */ 15967 0, 15968 #endif 15969 }, 15970 { 15971 BCMI_TSCE_XGXS_DIG_TOP_USER_CTL0r, 15972 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15973 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 15974 BCMI_TSCE_XGXS_DIG_TOP_USER_CTL0r_fields, 15975 #else 15976 0, 15977 #endif 15978 #endif 15979 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15980 PHYMOD_SYMBOL_FLAG_REGISTER, 15981 "DIG_TOP_USER_CTL0r", 15982 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15983 "DIG_COM_TOP_USER_CONTROL_0", 15984 NULL, 15985 #endif 15986 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15987 0x271, /* 625 */ 15988 0, 15989 #endif 15990 }, 15991 { 15992 BCMI_TSCE_XGXS_DIG_UC_ACK_CORE_CTLr, 15993 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15994 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 15995 BCMI_TSCE_XGXS_DIG_UC_ACK_CORE_CTLr_fields, 15996 #else 15997 0, 15998 #endif 15999 #endif 16000 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16001 PHYMOD_SYMBOL_FLAG_REGISTER, 16002 "DIG_UC_ACK_CORE_CTLr", 16003 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16004 "DIG_COM_UC_ACK_CORE_CONTROL", 16005 NULL, 16006 #endif 16007 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16008 0x0, /* 0 */ 16009 0, 16010 #endif 16011 }, 16012 { 16013 BCMI_TSCE_XGXS_DIG_CORE_RST_OCC_CTLr, 16014 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16015 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 16016 BCMI_TSCE_XGXS_DIG_CORE_RST_OCC_CTLr_fields, 16017 #else 16018 0, 16019 #endif 16020 #endif 16021 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16022 PHYMOD_SYMBOL_FLAG_REGISTER, 16023 "DIG_CORE_RST_OCC_CTLr", 16024 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16025 "DIG_COM_CORE_REG_RESET_OCCURRED_CONTROL", 16026 NULL, 16027 #endif 16028 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16029 0x1, /* 1 */ 16030 0, 16031 #endif 16032 }, 16033 { 16034 BCMI_TSCE_XGXS_DIG_RST_SEQ_TMR_CTLr, 16035 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16036 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 16037 BCMI_TSCE_XGXS_DIG_RST_SEQ_TMR_CTLr_fields, 16038 #else 16039 0, 16040 #endif 16041 #endif 16042 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16043 PHYMOD_SYMBOL_FLAG_REGISTER, 16044 "DIG_RST_SEQ_TMR_CTLr", 16045 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16046 "DIG_COM_RST_SEQ_TIMER_CONTROL", 16047 NULL, 16048 #endif 16049 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16050 0x8304, /* 33540 */ 16051 0, 16052 #endif 16053 }, 16054 { 16055 BCMI_TSCE_XGXS_DIG_CORE_DP_RST_ST_STSr, 16056 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16057 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 16058 BCMI_TSCE_XGXS_DIG_CORE_DP_RST_ST_STSr_fields, 16059 #else 16060 0, 16061 #endif 16062 #endif 16063 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16064 PHYMOD_SYMBOL_FLAG_REGISTER, 16065 "DIG_CORE_DP_RST_ST_STSr", 16066 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16067 "DIG_COM_CORE_DP_RESET_STATE_STATUS", 16068 NULL, 16069 #endif 16070 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16071 0x7, /* 7 */ 16072 0, 16073 #endif 16074 }, 16075 { 16076 BCMI_TSCE_XGXS_DIG_PMD_CORE_MODE_STSr, 16077 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16078 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 16079 BCMI_TSCE_XGXS_DIG_PMD_CORE_MODE_STSr_fields, 16080 #else 16081 0, 16082 #endif 16083 #endif 16084 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16085 PHYMOD_SYMBOL_FLAG_REGISTER, 16086 "DIG_PMD_CORE_MODE_STSr", 16087 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16088 "DIG_COM_PMD_CORE_MODE_STATUS", 16089 NULL, 16090 #endif 16091 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16092 0x0, /* 0 */ 16093 0, 16094 #endif 16095 }, 16096 { 16097 BCMI_TSCE_XGXS_DIG_REVID1r, 16098 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16099 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 16100 BCMI_TSCE_XGXS_DIG_REVID1r_fields, 16101 #else 16102 0, 16103 #endif 16104 #endif 16105 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16106 PHYMOD_SYMBOL_FLAG_REGISTER, 16107 "DIG_REVID1r", 16108 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16109 "DIG_COM_REVID1", 16110 NULL, 16111 #endif 16112 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16113 0x4038, /* 16440 */ 16114 0, 16115 #endif 16116 }, 16117 { 16118 BCMI_TSCE_XGXS_DIG_TX_LN_MAP_0_1_2r, 16119 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16120 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 16121 BCMI_TSCE_XGXS_DIG_TX_LN_MAP_0_1_2r_fields, 16122 #else 16123 0, 16124 #endif 16125 #endif 16126 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16127 PHYMOD_SYMBOL_FLAG_REGISTER, 16128 "DIG_TX_LN_MAP_0_1_2r", 16129 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16130 "DIG_COM_TX_LANE_MAP_0_1_2", 16131 NULL, 16132 #endif 16133 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16134 0x820, /* 2080 */ 16135 0, 16136 #endif 16137 }, 16138 { 16139 BCMI_TSCE_XGXS_DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r, 16140 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16141 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 16142 BCMI_TSCE_XGXS_DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r_fields, 16143 #else 16144 0, 16145 #endif 16146 #endif 16147 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16148 PHYMOD_SYMBOL_FLAG_REGISTER, 16149 "DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r", 16150 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16151 "DIG_COM_TX_LANE_MAP_3_N_LANE_ADDR_0_1", 16152 NULL, 16153 #endif 16154 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16155 0x403, /* 1027 */ 16156 0, 16157 #endif 16158 }, 16159 { 16160 BCMI_TSCE_XGXS_DIG_LN_ADDR_2_3r, 16161 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16162 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 16163 BCMI_TSCE_XGXS_DIG_LN_ADDR_2_3r_fields, 16164 #else 16165 0, 16166 #endif 16167 #endif 16168 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16169 PHYMOD_SYMBOL_FLAG_REGISTER, 16170 "DIG_LN_ADDR_2_3r", 16171 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16172 "DIG_COM_LANE_ADDR_2_3", 16173 NULL, 16174 #endif 16175 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16176 0x302, /* 770 */ 16177 0, 16178 #endif 16179 }, 16180 { 16181 BCMI_TSCE_XGXS_DIG_REVID2r, 16182 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16183 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 16184 BCMI_TSCE_XGXS_DIG_REVID2r_fields, 16185 #else 16186 0, 16187 #endif 16188 #endif 16189 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16190 PHYMOD_SYMBOL_FLAG_REGISTER, 16191 "DIG_REVID2r", 16192 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16193 "DIG_COM_REVID2", 16194 NULL, 16195 #endif 16196 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16197 0x0, /* 0 */ 16198 0, 16199 #endif 16200 }, 16201 { 16202 BCMI_TSCE_XGXS_PATGEN_SEQ0r, 16203 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16204 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 16205 BCMI_TSCE_XGXS_PATGEN_SEQ0r_fields, 16206 #else 16207 0, 16208 #endif 16209 #endif 16210 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16211 PHYMOD_SYMBOL_FLAG_REGISTER, 16212 "PATGEN_SEQ0r", 16213 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16214 "PATT_GEN_COM_SEQ_0", 16215 NULL, 16216 #endif 16217 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16218 0xff00, /* 65280 */ 16219 0, 16220 #endif 16221 }, 16222 { 16223 BCMI_TSCE_XGXS_PATGEN_SEQ1r, 16224 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16225 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 16226 BCMI_TSCE_XGXS_PATGEN_SEQ1r_fields, 16227 #else 16228 0, 16229 #endif 16230 #endif 16231 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16232 PHYMOD_SYMBOL_FLAG_REGISTER, 16233 "PATGEN_SEQ1r", 16234 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16235 "PATT_GEN_COM_SEQ_1", 16236 NULL, 16237 #endif 16238 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16239 0xff00, /* 65280 */ 16240 0, 16241 #endif 16242 }, 16243 { 16244 BCMI_TSCE_XGXS_PATGEN_SEQ2r, 16245 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16246 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 16247 BCMI_TSCE_XGXS_PATGEN_SEQ2r_fields, 16248 #else 16249 0, 16250 #endif 16251 #endif 16252 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16253 PHYMOD_SYMBOL_FLAG_REGISTER, 16254 "PATGEN_SEQ2r", 16255 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16256 "PATT_GEN_COM_SEQ_2", 16257 NULL, 16258 #endif 16259 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16260 0xff00, /* 65280 */ 16261 0, 16262 #endif 16263 }, 16264 { 16265 BCMI_TSCE_XGXS_PATGEN_SEQ3r, 16266 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16267 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 16268 BCMI_TSCE_XGXS_PATGEN_SEQ3r_fields, 16269 #else 16270 0, 16271 #endif 16272 #endif 16273 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16274 PHYMOD_SYMBOL_FLAG_REGISTER, 16275 "PATGEN_SEQ3r", 16276 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16277 "PATT_GEN_COM_SEQ_3", 16278 NULL, 16279 #endif 16280 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16281 0xff00, /* 65280 */ 16282 0, 16283 #endif 16284 }, 16285 { 16286 BCMI_TSCE_XGXS_PATGEN_SEQ4r, 16287 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16288 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 16289 BCMI_TSCE_XGXS_PATGEN_SEQ4r_fields, 16290 #else 16291 0, 16292 #endif 16293 #endif 16294 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16295 PHYMOD_SYMBOL_FLAG_REGISTER, 16296 "PATGEN_SEQ4r", 16297 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16298 "PATT_GEN_COM_SEQ_4", 16299 NULL, 16300 #endif 16301 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16302 0xff00, /* 65280 */ 16303 0, 16304 #endif 16305 }, 16306 { 16307 BCMI_TSCE_XGXS_PATGEN_SEQ5r, 16308 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16309 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 16310 BCMI_TSCE_XGXS_PATGEN_SEQ5r_fields, 16311 #else 16312 0, 16313 #endif 16314 #endif 16315 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16316 PHYMOD_SYMBOL_FLAG_REGISTER, 16317 "PATGEN_SEQ5r", 16318 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16319 "PATT_GEN_COM_SEQ_5", 16320 NULL, 16321 #endif 16322 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16323 0xff00, /* 65280 */ 16324 0, 16325 #endif 16326 }, 16327 { 16328 BCMI_TSCE_XGXS_PATGEN_SEQ6r, 16329 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16330 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 16331 BCMI_TSCE_XGXS_PATGEN_SEQ6r_fields, 16332 #else 16333 0, 16334 #endif 16335 #endif 16336 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16337 PHYMOD_SYMBOL_FLAG_REGISTER, 16338 "PATGEN_SEQ6r", 16339 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16340 "PATT_GEN_COM_SEQ_6", 16341 NULL, 16342 #endif 16343 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16344 0xff00, /* 65280 */ 16345 0, 16346 #endif 16347 }, 16348 { 16349 BCMI_TSCE_XGXS_PATGEN_SEQ7r, 16350 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16351 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 16352 BCMI_TSCE_XGXS_PATGEN_SEQ7r_fields, 16353 #else 16354 0, 16355 #endif 16356 #endif 16357 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16358 PHYMOD_SYMBOL_FLAG_REGISTER, 16359 "PATGEN_SEQ7r", 16360 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16361 "PATT_GEN_COM_SEQ_7", 16362 NULL, 16363 #endif 16364 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16365 0xff00, /* 65280 */ 16366 0, 16367 #endif 16368 }, 16369 { 16370 BCMI_TSCE_XGXS_PATGEN_SEQ8r, 16371 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16372 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 16373 BCMI_TSCE_XGXS_PATGEN_SEQ8r_fields, 16374 #else 16375 0, 16376 #endif 16377 #endif 16378 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16379 PHYMOD_SYMBOL_FLAG_REGISTER, 16380 "PATGEN_SEQ8r", 16381 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16382 "PATT_GEN_COM_SEQ_8", 16383 NULL, 16384 #endif 16385 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16386 0xff00, /* 65280 */ 16387 0, 16388 #endif 16389 }, 16390 { 16391 BCMI_TSCE_XGXS_PATGEN_SEQ9r, 16392 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16393 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 16394 BCMI_TSCE_XGXS_PATGEN_SEQ9r_fields, 16395 #else 16396 0, 16397 #endif 16398 #endif 16399 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16400 PHYMOD_SYMBOL_FLAG_REGISTER, 16401 "PATGEN_SEQ9r", 16402 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16403 "PATT_GEN_COM_SEQ_9", 16404 NULL, 16405 #endif 16406 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16407 0xff00, /* 65280 */ 16408 0, 16409 #endif 16410 }, 16411 { 16412 BCMI_TSCE_XGXS_PATGEN_SEQ_10r, 16413 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16414 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 16415 BCMI_TSCE_XGXS_PATGEN_SEQ_10r_fields, 16416 #else 16417 0, 16418 #endif 16419 #endif 16420 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16421 PHYMOD_SYMBOL_FLAG_REGISTER, 16422 "PATGEN_SEQ_10r", 16423 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16424 "PATT_GEN_COM_SEQ_10", 16425 NULL, 16426 #endif 16427 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16428 0xff00, /* 65280 */ 16429 0, 16430 #endif 16431 }, 16432 { 16433 BCMI_TSCE_XGXS_PATGEN_SEQ_11r, 16434 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16435 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 16436 BCMI_TSCE_XGXS_PATGEN_SEQ_11r_fields, 16437 #else 16438 0, 16439 #endif 16440 #endif 16441 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16442 PHYMOD_SYMBOL_FLAG_REGISTER, 16443 "PATGEN_SEQ_11r", 16444 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16445 "PATT_GEN_COM_SEQ_11", 16446 NULL, 16447 #endif 16448 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16449 0xff00, /* 65280 */ 16450 0, 16451 #endif 16452 }, 16453 { 16454 BCMI_TSCE_XGXS_PATGEN_SEQ_12r, 16455 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16456 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 16457 BCMI_TSCE_XGXS_PATGEN_SEQ_12r_fields, 16458 #else 16459 0, 16460 #endif 16461 #endif 16462 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16463 PHYMOD_SYMBOL_FLAG_REGISTER, 16464 "PATGEN_SEQ_12r", 16465 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16466 "PATT_GEN_COM_SEQ_12", 16467 NULL, 16468 #endif 16469 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16470 0xff00, /* 65280 */ 16471 0, 16472 #endif 16473 }, 16474 { 16475 BCMI_TSCE_XGXS_PATGEN_SEQ_13r, 16476 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16477 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 16478 BCMI_TSCE_XGXS_PATGEN_SEQ_13r_fields, 16479 #else 16480 0, 16481 #endif 16482 #endif 16483 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16484 PHYMOD_SYMBOL_FLAG_REGISTER, 16485 "PATGEN_SEQ_13r", 16486 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16487 "PATT_GEN_COM_SEQ_13", 16488 NULL, 16489 #endif 16490 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16491 0xff00, /* 65280 */ 16492 0, 16493 #endif 16494 }, 16495 { 16496 BCMI_TSCE_XGXS_PATGEN_SEQ_14r, 16497 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16498 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 16499 BCMI_TSCE_XGXS_PATGEN_SEQ_14r_fields, 16500 #else 16501 0, 16502 #endif 16503 #endif 16504 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16505 PHYMOD_SYMBOL_FLAG_REGISTER, 16506 "PATGEN_SEQ_14r", 16507 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16508 "PATT_GEN_COM_SEQ_14", 16509 NULL, 16510 #endif 16511 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16512 0xff00, /* 65280 */ 16513 0, 16514 #endif 16515 }, 16516 { 16517 BCMI_TSCE_XGXS_TXFIR_CTL1r, 16518 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16519 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 16520 BCMI_TSCE_XGXS_TXFIR_CTL1r_fields, 16521 #else 16522 0, 16523 #endif 16524 #endif 16525 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16526 PHYMOD_SYMBOL_FLAG_REGISTER, 16527 "TXFIR_CTL1r", 16528 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16529 "TX_FED_TXFIR_CONTROL1", 16530 NULL, 16531 #endif 16532 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16533 0x588, /* 1416 */ 16534 0, 16535 #endif 16536 }, 16537 { 16538 BCMI_TSCE_XGXS_TXFIR_CTL2r, 16539 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16540 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 16541 BCMI_TSCE_XGXS_TXFIR_CTL2r_fields, 16542 #else 16543 0, 16544 #endif 16545 #endif 16546 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16547 PHYMOD_SYMBOL_FLAG_REGISTER, 16548 "TXFIR_CTL2r", 16549 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16550 "TX_FED_TXFIR_CONTROL2", 16551 NULL, 16552 #endif 16553 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16554 0x3c, /* 60 */ 16555 0, 16556 #endif 16557 }, 16558 { 16559 BCMI_TSCE_XGXS_TXFIR_CTL3r, 16560 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16561 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 16562 BCMI_TSCE_XGXS_TXFIR_CTL3r_fields, 16563 #else 16564 0, 16565 #endif 16566 #endif 16567 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16568 PHYMOD_SYMBOL_FLAG_REGISTER, 16569 "TXFIR_CTL3r", 16570 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16571 "TX_FED_TXFIR_CONTROL3", 16572 NULL, 16573 #endif 16574 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16575 0x8888, /* 34952 */ 16576 0, 16577 #endif 16578 }, 16579 { 16580 BCMI_TSCE_XGXS_TXFIR_STS1r, 16581 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16582 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 16583 BCMI_TSCE_XGXS_TXFIR_STS1r_fields, 16584 #else 16585 0, 16586 #endif 16587 #endif 16588 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16589 PHYMOD_SYMBOL_FLAG_REGISTER, 16590 "TXFIR_STS1r", 16591 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16592 "TX_FED_TXFIR_STATUS1", 16593 NULL, 16594 #endif 16595 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16596 0x588, /* 1416 */ 16597 0, 16598 #endif 16599 }, 16600 { 16601 BCMI_TSCE_XGXS_TXFIR_STS2r, 16602 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16603 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 16604 BCMI_TSCE_XGXS_TXFIR_STS2r_fields, 16605 #else 16606 0, 16607 #endif 16608 #endif 16609 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16610 PHYMOD_SYMBOL_FLAG_REGISTER, 16611 "TXFIR_STS2r", 16612 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16613 "TX_FED_TXFIR_STATUS2", 16614 NULL, 16615 #endif 16616 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16617 0x3c, /* 60 */ 16618 0, 16619 #endif 16620 }, 16621 { 16622 BCMI_TSCE_XGXS_TXFIR_STS3r, 16623 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16624 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 16625 BCMI_TSCE_XGXS_TXFIR_STS3r_fields, 16626 #else 16627 0, 16628 #endif 16629 #endif 16630 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16631 PHYMOD_SYMBOL_FLAG_REGISTER, 16632 "TXFIR_STS3r", 16633 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16634 "TX_FED_TXFIR_STATUS3", 16635 NULL, 16636 #endif 16637 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16638 0x588, /* 1416 */ 16639 0, 16640 #endif 16641 }, 16642 { 16643 BCMI_TSCE_XGXS_TXFIR_STS4r, 16644 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16645 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 16646 BCMI_TSCE_XGXS_TXFIR_STS4r_fields, 16647 #else 16648 0, 16649 #endif 16650 #endif 16651 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16652 PHYMOD_SYMBOL_FLAG_REGISTER, 16653 "TXFIR_STS4r", 16654 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16655 "TX_FED_TXFIR_STATUS4", 16656 NULL, 16657 #endif 16658 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16659 0x3c, /* 60 */ 16660 0, 16661 #endif 16662 }, 16663 { 16664 BCMI_TSCE_XGXS_TXFIR_UC_CTLr, 16665 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16666 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 16667 BCMI_TSCE_XGXS_TXFIR_UC_CTLr_fields, 16668 #else 16669 0, 16670 #endif 16671 #endif 16672 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16673 PHYMOD_SYMBOL_FLAG_REGISTER, 16674 "TXFIR_UC_CTLr", 16675 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16676 "TX_FED_MICRO_CONTROL", 16677 NULL, 16678 #endif 16679 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16680 0x0, /* 0 */ 16681 0, 16682 #endif 16683 }, 16684 { 16685 BCMI_TSCE_XGXS_TXFIR_MISC_CTL1r, 16686 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16687 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 16688 BCMI_TSCE_XGXS_TXFIR_MISC_CTL1r_fields, 16689 #else 16690 0, 16691 #endif 16692 #endif 16693 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16694 PHYMOD_SYMBOL_FLAG_REGISTER, 16695 "TXFIR_MISC_CTL1r", 16696 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16697 "TX_FED_MISC_CONTROL1", 16698 NULL, 16699 #endif 16700 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16701 0x300, /* 768 */ 16702 0, 16703 #endif 16704 }, 16705 { 16706 BCMI_TSCE_XGXS_TXFIR_CTL4r, 16707 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16708 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 16709 BCMI_TSCE_XGXS_TXFIR_CTL4r_fields, 16710 #else 16711 0, 16712 #endif 16713 #endif 16714 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16715 PHYMOD_SYMBOL_FLAG_REGISTER, 16716 "TXFIR_CTL4r", 16717 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16718 "TX_FED_TXFIR_CONTROL4", 16719 NULL, 16720 #endif 16721 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16722 0x800, /* 2048 */ 16723 0, 16724 #endif 16725 }, 16726 { 16727 BCMI_TSCE_XGXS_PLL_CAL_CTL0r, 16728 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16729 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 16730 BCMI_TSCE_XGXS_PLL_CAL_CTL0r_fields, 16731 #else 16732 0, 16733 #endif 16734 #endif 16735 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16736 PHYMOD_SYMBOL_FLAG_REGISTER, 16737 "PLL_CAL_CTL0r", 16738 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16739 "PLL_CAL_COM_CTL_0", 16740 NULL, 16741 #endif 16742 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16743 0xc803, /* 51203 */ 16744 0, 16745 #endif 16746 }, 16747 { 16748 BCMI_TSCE_XGXS_PLL_CAL_CTL1r, 16749 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16750 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 16751 BCMI_TSCE_XGXS_PLL_CAL_CTL1r_fields, 16752 #else 16753 0, 16754 #endif 16755 #endif 16756 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16757 PHYMOD_SYMBOL_FLAG_REGISTER, 16758 "PLL_CAL_CTL1r", 16759 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16760 "PLL_CAL_COM_CTL_1", 16761 NULL, 16762 #endif 16763 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16764 0xc8ff, /* 51455 */ 16765 0, 16766 #endif 16767 }, 16768 { 16769 BCMI_TSCE_XGXS_PLL_CAL_CTL2r, 16770 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16771 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 16772 BCMI_TSCE_XGXS_PLL_CAL_CTL2r_fields, 16773 #else 16774 0, 16775 #endif 16776 #endif 16777 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16778 PHYMOD_SYMBOL_FLAG_REGISTER, 16779 "PLL_CAL_CTL2r", 16780 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16781 "PLL_CAL_COM_CTL_2", 16782 NULL, 16783 #endif 16784 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16785 0xff01, /* 65281 */ 16786 0, 16787 #endif 16788 }, 16789 { 16790 BCMI_TSCE_XGXS_PLL_CAL_CTL3r, 16791 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16792 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 16793 BCMI_TSCE_XGXS_PLL_CAL_CTL3r_fields, 16794 #else 16795 0, 16796 #endif 16797 #endif 16798 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16799 PHYMOD_SYMBOL_FLAG_REGISTER, 16800 "PLL_CAL_CTL3r", 16801 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16802 "PLL_CAL_COM_CTL_3", 16803 NULL, 16804 #endif 16805 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16806 0x0, /* 0 */ 16807 0, 16808 #endif 16809 }, 16810 { 16811 BCMI_TSCE_XGXS_PLL_CAL_CTL4r, 16812 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16813 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 16814 BCMI_TSCE_XGXS_PLL_CAL_CTL4r_fields, 16815 #else 16816 0, 16817 #endif 16818 #endif 16819 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16820 PHYMOD_SYMBOL_FLAG_REGISTER, 16821 "PLL_CAL_CTL4r", 16822 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16823 "PLL_CAL_COM_CTL_4", 16824 NULL, 16825 #endif 16826 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16827 0xa80d, /* 43021 */ 16828 0, 16829 #endif 16830 }, 16831 { 16832 BCMI_TSCE_XGXS_PLL_CAL_CTL5r, 16833 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16834 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 16835 BCMI_TSCE_XGXS_PLL_CAL_CTL5r_fields, 16836 #else 16837 0, 16838 #endif 16839 #endif 16840 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16841 PHYMOD_SYMBOL_FLAG_REGISTER, 16842 "PLL_CAL_CTL5r", 16843 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16844 "PLL_CAL_COM_CTL_5", 16845 NULL, 16846 #endif 16847 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16848 0x27, /* 39 */ 16849 0, 16850 #endif 16851 }, 16852 { 16853 BCMI_TSCE_XGXS_PLL_CAL_CTL6r, 16854 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16855 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 16856 BCMI_TSCE_XGXS_PLL_CAL_CTL6r_fields, 16857 #else 16858 0, 16859 #endif 16860 #endif 16861 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16862 PHYMOD_SYMBOL_FLAG_REGISTER, 16863 "PLL_CAL_CTL6r", 16864 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16865 "PLL_CAL_COM_CTL_6", 16866 NULL, 16867 #endif 16868 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16869 0x7, /* 7 */ 16870 0, 16871 #endif 16872 }, 16873 { 16874 BCMI_TSCE_XGXS_PLL_CAL_CTL7r, 16875 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16876 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 16877 BCMI_TSCE_XGXS_PLL_CAL_CTL7r_fields, 16878 #else 16879 0, 16880 #endif 16881 #endif 16882 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16883 PHYMOD_SYMBOL_FLAG_REGISTER, 16884 "PLL_CAL_CTL7r", 16885 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16886 "PLL_CAL_COM_CTL_7", 16887 NULL, 16888 #endif 16889 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16890 0xa, /* 10 */ 16891 0, 16892 #endif 16893 }, 16894 { 16895 BCMI_TSCE_XGXS_PLL_CAL_CTL_STS0r, 16896 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16897 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 16898 BCMI_TSCE_XGXS_PLL_CAL_CTL_STS0r_fields, 16899 #else 16900 0, 16901 #endif 16902 #endif 16903 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16904 PHYMOD_SYMBOL_FLAG_REGISTER, 16905 "PLL_CAL_CTL_STS0r", 16906 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16907 "PLL_CAL_COM_CTL_STATUS_0", 16908 NULL, 16909 #endif 16910 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16911 0x0, /* 0 */ 16912 0, 16913 #endif 16914 }, 16915 { 16916 BCMI_TSCE_XGXS_PLL_CAL_CTL_STS1r, 16917 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16918 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 16919 BCMI_TSCE_XGXS_PLL_CAL_CTL_STS1r_fields, 16920 #else 16921 0, 16922 #endif 16923 #endif 16924 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16925 PHYMOD_SYMBOL_FLAG_REGISTER, 16926 "PLL_CAL_CTL_STS1r", 16927 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16928 "PLL_CAL_COM_CTL_STATUS_1", 16929 NULL, 16930 #endif 16931 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16932 0x0, /* 0 */ 16933 0, 16934 #endif 16935 }, 16936 { 16937 BCMI_TSCE_XGXS_PLL_CAL_CTL_STS_DBGr, 16938 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16939 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 16940 BCMI_TSCE_XGXS_PLL_CAL_CTL_STS_DBGr_fields, 16941 #else 16942 0, 16943 #endif 16944 #endif 16945 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16946 PHYMOD_SYMBOL_FLAG_REGISTER, 16947 "PLL_CAL_CTL_STS_DBGr", 16948 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16949 "PLL_CAL_COM_CTL_STATUS_DBG", 16950 NULL, 16951 #endif 16952 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16953 0x1, /* 1 */ 16954 0, 16955 #endif 16956 }, 16957 { 16958 BCMI_TSCE_XGXS_CL72_TXC_TAP_LIMIT_CTL1r, 16959 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16960 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 16961 BCMI_TSCE_XGXS_CL72_TXC_TAP_LIMIT_CTL1r_fields, 16962 #else 16963 0, 16964 #endif 16965 #endif 16966 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16967 PHYMOD_SYMBOL_FLAG_REGISTER, 16968 "CL72_TXC_TAP_LIMIT_CTL1r", 16969 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16970 "TX_COM_CL72_TAP_LIMIT_CONTROL1", 16971 NULL, 16972 #endif 16973 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16974 0x7ff, /* 2047 */ 16975 0, 16976 #endif 16977 }, 16978 { 16979 BCMI_TSCE_XGXS_CL72_TXC_TAP_LIMIT_CTL2r, 16980 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16981 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 16982 BCMI_TSCE_XGXS_CL72_TXC_TAP_LIMIT_CTL2r_fields, 16983 #else 16984 0, 16985 #endif 16986 #endif 16987 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16988 PHYMOD_SYMBOL_FLAG_REGISTER, 16989 "CL72_TXC_TAP_LIMIT_CTL2r", 16990 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16991 "TX_COM_CL72_TAP_LIMIT_CONTROL2", 16992 NULL, 16993 #endif 16994 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16995 0x70, /* 112 */ 16996 0, 16997 #endif 16998 }, 16999 { 17000 BCMI_TSCE_XGXS_CL72_TXC_TAP_PRESET_CTLr, 17001 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17002 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 17003 BCMI_TSCE_XGXS_CL72_TXC_TAP_PRESET_CTLr_fields, 17004 #else 17005 0, 17006 #endif 17007 #endif 17008 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17009 PHYMOD_SYMBOL_FLAG_REGISTER, 17010 "CL72_TXC_TAP_PRESET_CTLr", 17011 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17012 "TX_COM_CL72_TAP_PRESET_CONTROL", 17013 NULL, 17014 #endif 17015 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17016 0x0, /* 0 */ 17017 0, 17018 #endif 17019 }, 17020 { 17021 BCMI_TSCE_XGXS_CL72_TXC_DBG1r, 17022 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17023 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 17024 BCMI_TSCE_XGXS_CL72_TXC_DBG1r_fields, 17025 #else 17026 0, 17027 #endif 17028 #endif 17029 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17030 PHYMOD_SYMBOL_FLAG_REGISTER, 17031 "CL72_TXC_DBG1r", 17032 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17033 "TX_COM_CL72_DEBUG_1_REGISTER", 17034 NULL, 17035 #endif 17036 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17037 0x3828, /* 14376 */ 17038 0, 17039 #endif 17040 }, 17041 { 17042 BCMI_TSCE_XGXS_CL72_TXC_MAX_WAIT_TMRr, 17043 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17044 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 17045 BCMI_TSCE_XGXS_CL72_TXC_MAX_WAIT_TMRr_fields, 17046 #else 17047 0, 17048 #endif 17049 #endif 17050 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17051 PHYMOD_SYMBOL_FLAG_REGISTER, 17052 "CL72_TXC_MAX_WAIT_TMRr", 17053 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17054 "TX_COM_CL72_MAX_WAIT_TIMER_REGISTER", 17055 NULL, 17056 #endif 17057 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17058 0x1f4, /* 500 */ 17059 0, 17060 #endif 17061 }, 17062 { 17063 BCMI_TSCE_XGXS_CL72_TXC_WAIT_TMRr, 17064 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17065 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 17066 BCMI_TSCE_XGXS_CL72_TXC_WAIT_TMRr_fields, 17067 #else 17068 0, 17069 #endif 17070 #endif 17071 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17072 PHYMOD_SYMBOL_FLAG_REGISTER, 17073 "CL72_TXC_WAIT_TMRr", 17074 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17075 "TX_COM_CL72_WAIT_TIMER_REGISTER", 17076 NULL, 17077 #endif 17078 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17079 0xc8, /* 200 */ 17080 0, 17081 #endif 17082 }, 17083 { 17084 BCMI_TSCE_XGXS_UC_RAMWORDr, 17085 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17086 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 17087 BCMI_TSCE_XGXS_UC_RAMWORDr_fields, 17088 #else 17089 0, 17090 #endif 17091 #endif 17092 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17093 PHYMOD_SYMBOL_FLAG_REGISTER, 17094 "UC_RAMWORDr", 17095 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17096 "MICRO_A_COM_RAMWORD", 17097 NULL, 17098 #endif 17099 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17100 0x0, /* 0 */ 17101 0, 17102 #endif 17103 }, 17104 { 17105 BCMI_TSCE_XGXS_UC_ADDRr, 17106 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17107 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 17108 BCMI_TSCE_XGXS_UC_ADDRr_fields, 17109 #else 17110 0, 17111 #endif 17112 #endif 17113 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17114 PHYMOD_SYMBOL_FLAG_REGISTER, 17115 "UC_ADDRr", 17116 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17117 "MICRO_A_COM_ADDRESS", 17118 NULL, 17119 #endif 17120 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17121 0x0, /* 0 */ 17122 0, 17123 #endif 17124 }, 17125 { 17126 BCMI_TSCE_XGXS_UC_COMMANDr, 17127 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17128 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 17129 BCMI_TSCE_XGXS_UC_COMMANDr_fields, 17130 #else 17131 0, 17132 #endif 17133 #endif 17134 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17135 PHYMOD_SYMBOL_FLAG_REGISTER, 17136 "UC_COMMANDr", 17137 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17138 "MICRO_A_COM_COMMAND", 17139 NULL, 17140 #endif 17141 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17142 0x0, /* 0 */ 17143 0, 17144 #endif 17145 }, 17146 { 17147 BCMI_TSCE_XGXS_UC_RAM_WRDATAr, 17148 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17149 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 17150 BCMI_TSCE_XGXS_UC_RAM_WRDATAr_fields, 17151 #else 17152 0, 17153 #endif 17154 #endif 17155 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17156 PHYMOD_SYMBOL_FLAG_REGISTER, 17157 "UC_RAM_WRDATAr", 17158 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17159 "MICRO_A_COM_RAM_WRDATA", 17160 NULL, 17161 #endif 17162 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17163 0x0, /* 0 */ 17164 0, 17165 #endif 17166 }, 17167 { 17168 BCMI_TSCE_XGXS_UC_RAM_RDDATAr, 17169 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17170 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 17171 BCMI_TSCE_XGXS_UC_RAM_RDDATAr_fields, 17172 #else 17173 0, 17174 #endif 17175 #endif 17176 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17177 PHYMOD_SYMBOL_FLAG_REGISTER, 17178 "UC_RAM_RDDATAr", 17179 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17180 "MICRO_A_COM_RAM_RDDATA", 17181 NULL, 17182 #endif 17183 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17184 0x0, /* 0 */ 17185 0, 17186 #endif 17187 }, 17188 { 17189 BCMI_TSCE_XGXS_UC_DWNLOAD_STSr, 17190 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17191 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 17192 BCMI_TSCE_XGXS_UC_DWNLOAD_STSr_fields, 17193 #else 17194 0, 17195 #endif 17196 #endif 17197 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17198 PHYMOD_SYMBOL_FLAG_REGISTER, 17199 "UC_DWNLOAD_STSr", 17200 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17201 "MICRO_A_COM_DOWNLOAD_STATUS", 17202 NULL, 17203 #endif 17204 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17205 0x0, /* 0 */ 17206 0, 17207 #endif 17208 }, 17209 { 17210 BCMI_TSCE_XGXS_UC_SFR_STSr, 17211 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17212 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 17213 BCMI_TSCE_XGXS_UC_SFR_STSr_fields, 17214 #else 17215 0, 17216 #endif 17217 #endif 17218 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17219 PHYMOD_SYMBOL_FLAG_REGISTER, 17220 "UC_SFR_STSr", 17221 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17222 "MICRO_A_COM_SFR_STATUS", 17223 NULL, 17224 #endif 17225 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17226 0x0, /* 0 */ 17227 0, 17228 #endif 17229 }, 17230 { 17231 BCMI_TSCE_XGXS_UC_MDIO_UC_MAILBOX_MSWr, 17232 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17233 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 17234 BCMI_TSCE_XGXS_UC_MDIO_UC_MAILBOX_MSWr_fields, 17235 #else 17236 0, 17237 #endif 17238 #endif 17239 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17240 PHYMOD_SYMBOL_FLAG_REGISTER, 17241 "UC_MDIO_UC_MAILBOX_MSWr", 17242 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17243 "MICRO_A_COM_MDIO_UC_MAILBOX_MSW", 17244 NULL, 17245 #endif 17246 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17247 0x0, /* 0 */ 17248 0, 17249 #endif 17250 }, 17251 { 17252 BCMI_TSCE_XGXS_UC_MDIO_UC_MAILBOX_LSWr, 17253 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17254 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 17255 BCMI_TSCE_XGXS_UC_MDIO_UC_MAILBOX_LSWr_fields, 17256 #else 17257 0, 17258 #endif 17259 #endif 17260 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17261 PHYMOD_SYMBOL_FLAG_REGISTER, 17262 "UC_MDIO_UC_MAILBOX_LSWr", 17263 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17264 "MICRO_A_COM_MDIO_UC_MAILBOX_LSW", 17265 NULL, 17266 #endif 17267 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17268 0x0, /* 0 */ 17269 0, 17270 #endif 17271 }, 17272 { 17273 BCMI_TSCE_XGXS_UC_UC_MDIO_MAILBOX_LSWr, 17274 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17275 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 17276 BCMI_TSCE_XGXS_UC_UC_MDIO_MAILBOX_LSWr_fields, 17277 #else 17278 0, 17279 #endif 17280 #endif 17281 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17282 PHYMOD_SYMBOL_FLAG_REGISTER, 17283 "UC_UC_MDIO_MAILBOX_LSWr", 17284 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17285 "MICRO_A_COM_UC_MDIO_MAILBOX_LSW", 17286 NULL, 17287 #endif 17288 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17289 0x0, /* 0 */ 17290 0, 17291 #endif 17292 }, 17293 { 17294 BCMI_TSCE_XGXS_UC_COMMAND2r, 17295 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17296 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 17297 BCMI_TSCE_XGXS_UC_COMMAND2r_fields, 17298 #else 17299 0, 17300 #endif 17301 #endif 17302 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17303 PHYMOD_SYMBOL_FLAG_REGISTER, 17304 "UC_COMMAND2r", 17305 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17306 "MICRO_A_COM_COMMAND2", 17307 NULL, 17308 #endif 17309 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17310 0x80f, /* 2063 */ 17311 0, 17312 #endif 17313 }, 17314 { 17315 BCMI_TSCE_XGXS_UC_UC_MDIO_MAILBOX_MSWr, 17316 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17317 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 17318 BCMI_TSCE_XGXS_UC_UC_MDIO_MAILBOX_MSWr_fields, 17319 #else 17320 0, 17321 #endif 17322 #endif 17323 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17324 PHYMOD_SYMBOL_FLAG_REGISTER, 17325 "UC_UC_MDIO_MAILBOX_MSWr", 17326 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17327 "MICRO_A_COM_UC_MDIO_MAILBOX_MSW", 17328 NULL, 17329 #endif 17330 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17331 0x0, /* 0 */ 17332 0, 17333 #endif 17334 }, 17335 { 17336 BCMI_TSCE_XGXS_UC_COMMAND3r, 17337 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17338 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 17339 BCMI_TSCE_XGXS_UC_COMMAND3r_fields, 17340 #else 17341 0, 17342 #endif 17343 #endif 17344 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17345 PHYMOD_SYMBOL_FLAG_REGISTER, 17346 "UC_COMMAND3r", 17347 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17348 "MICRO_A_COM_COMMAND3", 17349 NULL, 17350 #endif 17351 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17352 0x2, /* 2 */ 17353 0, 17354 #endif 17355 }, 17356 { 17357 BCMI_TSCE_XGXS_UC_COMMAND4r, 17358 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17359 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 17360 BCMI_TSCE_XGXS_UC_COMMAND4r_fields, 17361 #else 17362 0, 17363 #endif 17364 #endif 17365 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17366 PHYMOD_SYMBOL_FLAG_REGISTER, 17367 "UC_COMMAND4r", 17368 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17369 "MICRO_A_COM_COMMAND4", 17370 NULL, 17371 #endif 17372 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17373 0x0, /* 0 */ 17374 0, 17375 #endif 17376 }, 17377 { 17378 BCMI_TSCE_XGXS_UC_TEMPERATURE_STSr, 17379 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17380 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 17381 BCMI_TSCE_XGXS_UC_TEMPERATURE_STSr_fields, 17382 #else 17383 0, 17384 #endif 17385 #endif 17386 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17387 PHYMOD_SYMBOL_FLAG_REGISTER, 17388 "UC_TEMPERATURE_STSr", 17389 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17390 "MICRO_A_COM_TEMPERATURE_STATUS", 17391 NULL, 17392 #endif 17393 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17394 0x0, /* 0 */ 17395 0, 17396 #endif 17397 }, 17398 { 17399 BCMI_TSCE_XGXS_UC_PROGRAM_RAM_CTL1r, 17400 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17401 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 17402 BCMI_TSCE_XGXS_UC_PROGRAM_RAM_CTL1r_fields, 17403 #else 17404 0, 17405 #endif 17406 #endif 17407 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17408 PHYMOD_SYMBOL_FLAG_REGISTER, 17409 "UC_PROGRAM_RAM_CTL1r", 17410 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17411 "MICRO_B_COM_PROGRAM_RAM_CONTROL1", 17412 NULL, 17413 #endif 17414 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17415 0x0, /* 0 */ 17416 0, 17417 #endif 17418 }, 17419 { 17420 BCMI_TSCE_XGXS_UC_DATARAM_CTL1r, 17421 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17422 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 17423 BCMI_TSCE_XGXS_UC_DATARAM_CTL1r_fields, 17424 #else 17425 0, 17426 #endif 17427 #endif 17428 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17429 PHYMOD_SYMBOL_FLAG_REGISTER, 17430 "UC_DATARAM_CTL1r", 17431 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17432 "MICRO_B_COM_DATARAM_CONTROL1", 17433 NULL, 17434 #endif 17435 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17436 0x0, /* 0 */ 17437 0, 17438 #endif 17439 }, 17440 { 17441 BCMI_TSCE_XGXS_UC_IRAM_CTL1r, 17442 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17443 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 17444 BCMI_TSCE_XGXS_UC_IRAM_CTL1r_fields, 17445 #else 17446 0, 17447 #endif 17448 #endif 17449 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17450 PHYMOD_SYMBOL_FLAG_REGISTER, 17451 "UC_IRAM_CTL1r", 17452 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17453 "MICRO_B_COM_IRAM_CONTROL1", 17454 NULL, 17455 #endif 17456 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17457 0x0, /* 0 */ 17458 0, 17459 #endif 17460 }, 17461 { 17462 BCMI_TSCE_XGXS_MDIO_MASKDATAr, 17463 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17464 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 17465 BCMI_TSCE_XGXS_MDIO_MASKDATAr_fields, 17466 #else 17467 0, 17468 #endif 17469 #endif 17470 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17471 PHYMOD_SYMBOL_FLAG_REGISTER, 17472 "MDIO_MASKDATAr", 17473 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17474 "MDIO_MMDSEL_AER_COM_MDIO_MASKDATA", 17475 NULL, 17476 #endif 17477 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17478 0x0, /* 0 */ 17479 0, 17480 #endif 17481 }, 17482 { 17483 BCMI_TSCE_XGXS_MDIO_BCST_PORT_ADDRr, 17484 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17485 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 17486 BCMI_TSCE_XGXS_MDIO_BCST_PORT_ADDRr_fields, 17487 #else 17488 0, 17489 #endif 17490 #endif 17491 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17492 PHYMOD_SYMBOL_FLAG_REGISTER, 17493 "MDIO_BCST_PORT_ADDRr", 17494 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17495 "MDIO_MMDSEL_AER_COM_MDIO_BRCST_PORT_ADDR", 17496 NULL, 17497 #endif 17498 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17499 0x1f, /* 31 */ 17500 0, 17501 #endif 17502 }, 17503 { 17504 BCMI_TSCE_XGXS_MDIO_MMD_SELr, 17505 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17506 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 17507 BCMI_TSCE_XGXS_MDIO_MMD_SELr_fields, 17508 #else 17509 0, 17510 #endif 17511 #endif 17512 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17513 PHYMOD_SYMBOL_FLAG_REGISTER, 17514 "MDIO_MMD_SELr", 17515 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17516 "MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT", 17517 NULL, 17518 #endif 17519 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17520 0x404d, /* 16461 */ 17521 0, 17522 #endif 17523 }, 17524 { 17525 BCMI_TSCE_XGXS_MDIO_AERr, 17526 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17527 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 17528 BCMI_TSCE_XGXS_MDIO_AERr_fields, 17529 #else 17530 0, 17531 #endif 17532 #endif 17533 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17534 PHYMOD_SYMBOL_FLAG_REGISTER, 17535 "MDIO_AERr", 17536 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17537 "MDIO_MMDSEL_AER_COM_MDIO_AER", 17538 NULL, 17539 #endif 17540 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17541 0x0, /* 0 */ 17542 0, 17543 #endif 17544 }, 17545 { 17546 BCMI_TSCE_XGXS_MDIO_BLK_ADDRr, 17547 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17548 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCE_XGXS 17549 BCMI_TSCE_XGXS_MDIO_BLK_ADDRr_fields, 17550 #else 17551 0, 17552 #endif 17553 #endif 17554 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17555 PHYMOD_SYMBOL_FLAG_REGISTER, 17556 "MDIO_BLK_ADDRr", 17557 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17558 "MDIO_BLK_ADDR_COM_BLK_ADDR", 17559 NULL, 17560 #endif 17561 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17562 0x0, /* 0 */ 17563 0, 17564 #endif 17565 }, 17566 #endif 17567 }; 17568 17569 17570 phymod_symbols_t bcmi_tsce_xgxs_symbols = 17571 { 17572 bcmi_tsce_xgxs_syms, sizeof(bcmi_tsce_xgxs_syms)/sizeof(bcmi_tsce_xgxs_syms[0]), 17573 #if PHYMOD_CONFIG_INCLUDE_FIELD_NAMES == 1 17574 bcmi_tsce_xgxs_fields 17575 #else 17576 NULL 17577 #endif 17578 /* END OF SYMBOL FILE */ 17579 }; 17580 17581 #endif /* PHYMOD_CONFIG_INCLUDE_CHIP_SYMBOLS */