bcmi_qtce16_xgxs_sym.c (545536B)
1 /******************************************************************************* 2 * 3 * 4 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 5 * 6 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 7 * 8 * DO NOT EDIT THIS FILE! 9 * This file is auto-generated from the registers file. 10 * Edits to this file will be lost when it is regenerated. 11 * 12 * Symbol table file for the BCMI_QTC_XGXS. 13 * This symbol table is used by the Broadcom debug shell. 14 */ 15 16 17 #include <phymod/chip/bcmi_qtce16_xgxs_defs.h> 18 #include <phymod/phymod_symbols.h> 19 20 /* No symbols will be compiled unless this is defined. */ 21 #if PHYMOD_CONFIG_INCLUDE_CHIP_SYMBOLS == 1 22 /******************************************************************************* 23 * 24 * If PHYMOD_CONFIG_INCLUDE_FIELD_INFO is 1, then symbol information 25 * necessary to encode and decode the individual fields of a register or memory 26 * will be available. 27 * 28 * Without it, only the register and memory names will be symbolically available 29 * and their values will be displayed as raw data only. 30 * 31 * Field information can be compiled out in the interest of saving code space. 32 */ 33 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 34 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 35 36 static uint32_t BCMI_QTC_XGXS_ACC_ADDR_DATAr_fields[] = 37 { 38 /* MDIO_ADDR_DATA:0:15 */ 39 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(673, 15, 0) 40 }; 41 static uint32_t BCMI_QTC_XGXS_ACC_CTLr_fields[] = 42 { 43 /* MDIO_DEVAD:0:4 */ 44 PHYMOD_SYMBOL_FIELD_ENCODE(677, 4, 0), 45 /* MDIO_FUNCTION:14:15 */ 46 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(685, 15, 14) 47 }; 48 static uint32_t BCMI_QTC_XGXS_AMS_RX_RX_CTL0r_fields[] = 49 { 50 /* SUM_PSEUDO_DIFF:0:0 */ 51 PHYMOD_SYMBOL_FIELD_ENCODE(1111, 0, 0), 52 /* RX_CM_SEL:1:1 */ 53 PHYMOD_SYMBOL_FIELD_ENCODE(999, 1, 1), 54 /* SIGDET_PWRDN:2:2 */ 55 PHYMOD_SYMBOL_FIELD_ENCODE(1079, 2, 2), 56 /* SIGDET_BYPASS:3:3 */ 57 PHYMOD_SYMBOL_FIELD_ENCODE(1074, 3, 3), 58 /* RCM_SUM:4:4 */ 59 PHYMOD_SYMBOL_FIELD_ENCODE(931, 4, 4), 60 /* VGA_CM_SEL:5:5 */ 61 PHYMOD_SYMBOL_FIELD_ENCODE(1392, 5, 5), 62 /* AMS_SPARE_0_2:6:8 */ 63 PHYMOD_SYMBOL_FIELD_ENCODE(27, 8, 6), 64 /* EN_RXCK_TESTPORT:9:9 */ 65 PHYMOD_SYMBOL_FIELD_ENCODE(487, 9, 9), 66 /* EN_RXCK_TEST:10:11 */ 67 PHYMOD_SYMBOL_FIELD_ENCODE(486, 11, 10), 68 /* TERM_CM_ENA:12:12 */ 69 PHYMOD_SYMBOL_FIELD_ENCODE(1155, 12, 12), 70 /* TERM_CMULT_ENA:13:13 */ 71 PHYMOD_SYMBOL_FIELD_ENCODE(1153, 13, 13), 72 /* TERM_LOWZGND:14:14 */ 73 PHYMOD_SYMBOL_FIELD_ENCODE(1156, 14, 14), 74 /* TERM_LOWZVDD:15:15 */ 75 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1157, 15, 15) 76 }; 77 static uint32_t BCMI_QTC_XGXS_AMS_RX_RX_CTL1r_fields[] = 78 { 79 /* VGA_OUT_IDLE:0:0 */ 80 PHYMOD_SYMBOL_FIELD_ENCODE(1402, 0, 0), 81 /* VGA_EN_HGAIN:1:1 */ 82 PHYMOD_SYMBOL_FIELD_ENCODE(1394, 1, 1), 83 /* CURR_CTLE:2:4 */ 84 PHYMOD_SYMBOL_FIELD_ENCODE(324, 4, 2), 85 /* CURR_PI:5:7 */ 86 PHYMOD_SYMBOL_FIELD_ENCODE(329, 7, 5), 87 /* AMS_SPARE_1_0:8:10 */ 88 PHYMOD_SYMBOL_FIELD_ENCODE(28, 10, 8), 89 /* CURR_DFE_2:11:13 */ 90 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(326, 13, 11) 91 }; 92 static uint32_t BCMI_QTC_XGXS_AMS_RX_RX_CTL2r_fields[] = 93 { 94 /* CURR_DFE_1:0:2 */ 95 PHYMOD_SYMBOL_FIELD_ENCODE(325, 2, 0), 96 /* CURR_DFE_SUMMER:3:5 */ 97 PHYMOD_SYMBOL_FIELD_ENCODE(327, 5, 3), 98 /* CURR_VGA:6:8 */ 99 PHYMOD_SYMBOL_FIELD_ENCODE(333, 8, 6), 100 /* EN_DFE_TAP_FB:9:13 */ 101 PHYMOD_SYMBOL_FIELD_ENCODE(473, 13, 9), 102 /* AMS_SPARE_2_0:14:15 */ 103 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(29, 15, 14) 104 }; 105 static uint32_t BCMI_QTC_XGXS_AMS_RX_RX_CTL3r_fields[] = 106 { 107 /* EN_VCCTRL:0:0 */ 108 PHYMOD_SYMBOL_FIELD_ENCODE(492, 0, 0), 109 /* EN_CLK33:1:1 */ 110 PHYMOD_SYMBOL_FIELD_ENCODE(468, 1, 1), 111 /* EN_CLK16:2:2 */ 112 PHYMOD_SYMBOL_FIELD_ENCODE(467, 2, 2), 113 /* EN_20B_DEMUX:3:3 */ 114 PHYMOD_SYMBOL_FIELD_ENCODE(463, 3, 3), 115 /* RX_DFE_OS2X_MODE:4:4 */ 116 PHYMOD_SYMBOL_FIELD_ENCODE(1000, 4, 4), 117 /* OS2X_MODE_EVEN_ODD:5:5 */ 118 PHYMOD_SYMBOL_FIELD_ENCODE(775, 5, 5), 119 /* CURR_VDDR_AFE:6:8 */ 120 PHYMOD_SYMBOL_FIELD_ENCODE(332, 8, 6), 121 /* CURR_SIGDET:9:11 */ 122 PHYMOD_SYMBOL_FIELD_ENCODE(331, 11, 9), 123 /* I4DEADZONE:12:12 */ 124 PHYMOD_SYMBOL_FIELD_ENCODE(535, 12, 12), 125 /* SELI1P25DFE:13:13 */ 126 PHYMOD_SYMBOL_FIELD_ENCODE(1046, 13, 13), 127 /* LL_EN:14:14 */ 128 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(594, 14, 14) 129 }; 130 static uint32_t BCMI_QTC_XGXS_AMS_RX_RX_CTL4r_fields[] = 131 { 132 /* RECCLKDIV:0:4 */ 133 PHYMOD_SYMBOL_FIELD_ENCODE(932, 4, 0), 134 /* DIV3O4O5:5:6 */ 135 PHYMOD_SYMBOL_FIELD_ENCODE(423, 6, 5), 136 /* EN_RECCLKDIV:7:7 */ 137 PHYMOD_SYMBOL_FIELD_ENCODE(484, 7, 7), 138 /* AMS_SPARE_4_0:8:10 */ 139 PHYMOD_SYMBOL_FIELD_ENCODE(31, 10, 8), 140 /* OC_2X:11:11 */ 141 PHYMOD_SYMBOL_FIELD_ENCODE(773, 11, 11), 142 /* VGA_PON:12:15 */ 143 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1407, 15, 12) 144 }; 145 static uint32_t BCMI_QTC_XGXS_AMS_RX_RX_CTL5r_fields[] = 146 { 147 /* RX_PON:0:3 */ 148 PHYMOD_SYMBOL_FIELD_ENCODE(1035, 3, 0), 149 /* CURR_IN_OFFSET:4:6 */ 150 PHYMOD_SYMBOL_FIELD_ENCODE(328, 6, 4), 151 /* CTLE_GAIN_CTRL:7:10 */ 152 PHYMOD_SYMBOL_FIELD_ENCODE(323, 10, 7), 153 /* EN_DFECLK:11:11 */ 154 PHYMOD_SYMBOL_FIELD_ENCODE(472, 11, 11), 155 /* DCC1_PHASE_FLIP:12:12 */ 156 PHYMOD_SYMBOL_FIELD_ENCODE(339, 12, 12), 157 /* PI_PD:13:13 */ 158 PHYMOD_SYMBOL_FIELD_ENCODE(843, 13, 13), 159 /* SLCR_CALIB_RANGE_SEL:14:14 */ 160 PHYMOD_SYMBOL_FIELD_ENCODE(1095, 14, 14), 161 /* DCC2_PHASE_FLIP:15:15 */ 162 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(340, 15, 15) 163 }; 164 static uint32_t BCMI_QTC_XGXS_AMS_RX_RX_CTL6r_fields[] = 165 { 166 /* M1_SIGN:0:0 */ 167 PHYMOD_SYMBOL_FIELD_ENCODE(662, 0, 0), 168 /* HIZ_1:1:1 */ 169 PHYMOD_SYMBOL_FIELD_ENCODE(514, 1, 1), 170 /* EN_SIGDET_CALIB:2:2 */ 171 PHYMOD_SYMBOL_FIELD_ENCODE(489, 2, 2), 172 /* SUM_GAIN_CTRL:3:6 */ 173 PHYMOD_SYMBOL_FIELD_ENCODE(1110, 6, 3), 174 /* SIGDET_CALIBRATION_SELECT:7:7 */ 175 PHYMOD_SYMBOL_FIELD_ENCODE(1075, 7, 7), 176 /* SIGDET_OFFSET_CORRECTION_POS:8:12 */ 177 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1078, 12, 8) 178 }; 179 static uint32_t BCMI_QTC_XGXS_AMS_RX_RX_CTL7r_fields[] = 180 { 181 /* SIGDET_OFFSET_CORRECTION_NEG:0:4 */ 182 PHYMOD_SYMBOL_FIELD_ENCODE(1077, 4, 0), 183 /* SIGDET_THRESHOLD:5:9 */ 184 PHYMOD_SYMBOL_FIELD_ENCODE(1080, 9, 5), 185 /* AMS_SPARE_7_0:10:13 */ 186 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(33, 13, 10) 187 }; 188 static uint32_t BCMI_QTC_XGXS_AMS_RX_RX_INTr_fields[] = 189 { 190 /* VGAPON_SEL:0:0 */ 191 PHYMOD_SYMBOL_FIELD_ENCODE(1388, 0, 0), 192 /* RXPON_SEL:1:1 */ 193 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(992, 1, 1) 194 }; 195 static uint32_t BCMI_QTC_XGXS_AMS_RX_RX_STSr_fields[] = 196 { 197 /* RXPON_MUX:0:3 */ 198 PHYMOD_SYMBOL_FIELD_ENCODE(991, 3, 0), 199 /* VGAPON_MUX:4:7 */ 200 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1387, 7, 4) 201 }; 202 static uint32_t BCMI_QTC_XGXS_AMS_TX_TX_CTL0r_fields[] = 203 { 204 /* TX_PWRDN:0:0 */ 205 PHYMOD_SYMBOL_FIELD_ENCODE(1335, 0, 0), 206 /* TICKSEL:1:2 */ 207 PHYMOD_SYMBOL_FIELD_ENCODE(1165, 2, 1), 208 /* TX_PON:3:6 */ 209 PHYMOD_SYMBOL_FIELD_ENCODE(1333, 6, 3), 210 /* ENABLE_OS_2:7:7 */ 211 PHYMOD_SYMBOL_FIELD_ENCODE(452, 7, 7), 212 /* LL_SELPATH_TX:8:8 */ 213 PHYMOD_SYMBOL_FIELD_ENCODE(598, 8, 8), 214 /* LL_POLARITY_FLIP:9:9 */ 215 PHYMOD_SYMBOL_FIELD_ENCODE(597, 9, 9), 216 /* LL_FIFO_ZERO_OUT:10:10 */ 217 PHYMOD_SYMBOL_FIELD_ENCODE(596, 10, 10), 218 /* LL_FIFO_CTRL:11:13 */ 219 PHYMOD_SYMBOL_FIELD_ENCODE(595, 13, 11), 220 /* TX_FIFO_RESETB:14:14 */ 221 PHYMOD_SYMBOL_FIELD_ENCODE(1269, 14, 14), 222 /* LOWLATENCY_EN:15:15 */ 223 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(640, 15, 15) 224 }; 225 static uint32_t BCMI_QTC_XGXS_AMS_TX_TX_CTL1r_fields[] = 226 { 227 /* ENABLE_OS_4:0:0 */ 228 PHYMOD_SYMBOL_FIELD_ENCODE(453, 0, 0), 229 /* EN_HIGH_CURRENT:1:1 */ 230 PHYMOD_SYMBOL_FIELD_ENCODE(476, 1, 1), 231 /* RXDTCT_TH_SEL:2:3 */ 232 PHYMOD_SYMBOL_FIELD_ENCODE(988, 3, 2), 233 /* CNTRL_RXDETECT_EN:4:4 */ 234 PHYMOD_SYMBOL_FIELD_ENCODE(297, 4, 4), 235 /* TESTSEL:5:6 */ 236 PHYMOD_SYMBOL_FIELD_ENCODE(1160, 6, 5), 237 /* TESTCLK_ENA:7:7 */ 238 PHYMOD_SYMBOL_FIELD_ENCODE(1159, 7, 7), 239 /* EN_WCLK16:8:8 */ 240 PHYMOD_SYMBOL_FIELD_ENCODE(493, 8, 8), 241 /* EN_WCLK20:9:9 */ 242 PHYMOD_SYMBOL_FIELD_ENCODE(494, 9, 9), 243 /* EN_WCLK33:10:10 */ 244 PHYMOD_SYMBOL_FIELD_ENCODE(495, 10, 10), 245 /* EN_SLOW:11:14 */ 246 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(490, 14, 11) 247 }; 248 static uint32_t BCMI_QTC_XGXS_AMS_TX_TX_CTL2r_fields[] = 249 { 250 /* EN_HPF:0:3 */ 251 PHYMOD_SYMBOL_FIELD_ENCODE(477, 3, 0), 252 /* DCC_EN:4:4 */ 253 PHYMOD_SYMBOL_FIELD_ENCODE(341, 4, 4), 254 /* IBIAS_OPAMP_CNTL:5:7 */ 255 PHYMOD_SYMBOL_FIELD_ENCODE(536, 7, 5), 256 /* IBIAS_PI_CNTL:8:10 */ 257 PHYMOD_SYMBOL_FIELD_ENCODE(538, 10, 8), 258 /* IBIAS_PIBUF_CNTL:11:13 */ 259 PHYMOD_SYMBOL_FIELD_ENCODE(537, 13, 11), 260 /* FIFO_PHSDETECT_MODE:14:14 */ 261 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(504, 14, 14) 262 }; 263 static uint32_t BCMI_QTC_XGXS_AMS_TX_TX_CTL3r_fields[] = 264 { 265 /* AMS_SPARE_3_0:0:1 */ 266 PHYMOD_SYMBOL_FIELD_ENCODE(30, 1, 0), 267 /* REFCALSHUNT:2:5 */ 268 PHYMOD_SYMBOL_FIELD_ENCODE(937, 5, 2), 269 /* REFCALP:6:9 */ 270 PHYMOD_SYMBOL_FIELD_ENCODE(935, 9, 6), 271 /* REFCALM:10:13 */ 272 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(933, 13, 10) 273 }; 274 static uint32_t BCMI_QTC_XGXS_AMS_TX_TX_CTL4r_fields[] = 275 { 276 /* SHNTPRE_POST1PRE:0:5 */ 277 PHYMOD_SYMBOL_FIELD_ENCODE(1073, 5, 0), 278 /* SHNTPOST1_POST1PRE:6:11 */ 279 PHYMOD_SYMBOL_FIELD_ENCODE(1071, 11, 6), 280 /* SHNTPOST2_POST2:12:15 */ 281 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1072, 15, 12) 282 }; 283 static uint32_t BCMI_QTC_XGXS_AMS_TX_TX_CTL5r_fields[] = 284 { 285 /* SHNTMAIN_POST1PRE:0:5 */ 286 PHYMOD_SYMBOL_FIELD_ENCODE(1068, 5, 0), 287 /* SHNTMAIN_POST2:6:9 */ 288 PHYMOD_SYMBOL_FIELD_ENCODE(1069, 9, 6), 289 /* EN_POST2:10:10 */ 290 PHYMOD_SYMBOL_FIELD_ENCODE(481, 10, 10), 291 /* EN_POST1:11:11 */ 292 PHYMOD_SYMBOL_FIELD_ENCODE(480, 11, 11), 293 /* EN_PRE:12:12 */ 294 PHYMOD_SYMBOL_FIELD_ENCODE(482, 12, 12), 295 /* POST2TO1:13:13 */ 296 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(901, 13, 13) 297 }; 298 static uint32_t BCMI_QTC_XGXS_AMS_TX_TX_CTL6r_fields[] = 299 { 300 /* EN_SHUNTMODE:0:0 */ 301 PHYMOD_SYMBOL_FIELD_ENCODE(488, 0, 0), 302 /* PD_PHASEDET:1:1 */ 303 PHYMOD_SYMBOL_FIELD_ENCODE(832, 1, 1), 304 /* AMS_SPARE_6_0:2:5 */ 305 PHYMOD_SYMBOL_FIELD_ENCODE(32, 5, 2), 306 /* DIS_CAL:6:10 */ 307 PHYMOD_SYMBOL_FIELD_ENCODE(422, 10, 6), 308 /* SHNTPOST1_POST1:11:15 */ 309 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1070, 15, 11) 310 }; 311 static uint32_t BCMI_QTC_XGXS_AMS_TX_TX_CTL7r_fields[] = 312 { 313 /* SHNTMAIN_POST1:0:4 */ 314 PHYMOD_SYMBOL_FIELD_ENCODE(1067, 4, 0), 315 /* REFCALMCS:5:8 */ 316 PHYMOD_SYMBOL_FIELD_ENCODE(934, 8, 5), 317 /* REFCALPCS:9:12 */ 318 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(936, 12, 9) 319 }; 320 static uint32_t BCMI_QTC_XGXS_AMS_TX_TX_CTL8r_fields[] = 321 { 322 /* SHNTEN_MAIN:0:0 */ 323 PHYMOD_SYMBOL_FIELD_ENCODE(1066, 0, 0), 324 /* AMS_SPARE_8_0:1:8 */ 325 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(34, 8, 1) 326 }; 327 static uint32_t BCMI_QTC_XGXS_AMS_TX_TX_INTr_fields[] = 328 { 329 /* TXPON_SEL:1:1 */ 330 PHYMOD_SYMBOL_FIELD_ENCODE(1252, 1, 1), 331 /* AUTO_LL_SELPATH_TX_DIS:2:2 */ 332 PHYMOD_SYMBOL_FIELD_ENCODE(109, 2, 2), 333 /* SEL_TXMASTER:3:3 */ 334 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1048, 3, 3) 335 }; 336 static uint32_t BCMI_QTC_XGXS_AMS_TX_TX_STSr_fields[] = 337 { 338 /* TXPON_MUX:0:3 */ 339 PHYMOD_SYMBOL_FIELD_ENCODE(1251, 3, 0), 340 /* RESCAL:4:7 */ 341 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(957, 7, 4) 342 }; 343 static uint32_t BCMI_QTC_XGXS_AN_X4_ABI_SP0_CTLSr_fields[] = 344 { 345 /* AN_GOOD_TRAP:2:2 */ 346 PHYMOD_SYMBOL_FIELD_ENCODE(50, 2, 2), 347 /* AN_GOOD_CHECK_TRAP:3:3 */ 348 PHYMOD_SYMBOL_FIELD_ENCODE(49, 3, 3), 349 /* LINKFAILTIMER_DIS:4:4 */ 350 PHYMOD_SYMBOL_FIELD_ENCODE(570, 4, 4), 351 /* LINKFAILTIMERQUAL_EN:5:5 */ 352 PHYMOD_SYMBOL_FIELD_ENCODE(569, 5, 5), 353 /* AN_FAIL_COUNT_LIMIT:6:9 */ 354 PHYMOD_SYMBOL_FIELD_ENCODE(48, 9, 6), 355 /* OUI_CONTROL:10:15 */ 356 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(783, 15, 10) 357 }; 358 static uint32_t BCMI_QTC_XGXS_AN_X4_ABI_SP0_ENSr_fields[] = 359 { 360 /* CL37_AN_RESTART:0:0 */ 361 PHYMOD_SYMBOL_FIELD_ENCODE(184, 0, 0), 362 /* SGMII_TO_CL37_AUTO_ENABLE:1:1 */ 363 PHYMOD_SYMBOL_FIELD_ENCODE(1057, 1, 1), 364 /* CL37_BAM_TO_SGMII_AUTO_ENABLE:2:2 */ 365 PHYMOD_SYMBOL_FIELD_ENCODE(188, 2, 2), 366 /* CL37_ENABLE:3:3 */ 367 PHYMOD_SYMBOL_FIELD_ENCODE(189, 3, 3), 368 /* CL37_SGMII_ENABLE:4:4 */ 369 PHYMOD_SYMBOL_FIELD_ENCODE(196, 4, 4), 370 /* CL37_BAM_ENABLE:5:5 */ 371 PHYMOD_SYMBOL_FIELD_ENCODE(187, 5, 5), 372 /* DISABLE_REMOTE_FAULT_REPORTING:6:6 */ 373 PHYMOD_SYMBOL_FIELD_ENCODE(419, 6, 6), 374 /* QSGMII_EN:7:7 */ 375 PHYMOD_SYMBOL_FIELD_ENCODE(929, 7, 7), 376 /* USXGMII_EN:8:8 */ 377 PHYMOD_SYMBOL_FIELD_ENCODE(1365, 8, 8), 378 /* EEE_CLOCK_CAPABILITY_ECHO:9:9 */ 379 PHYMOD_SYMBOL_FIELD_ENCODE(441, 9, 9), 380 /* EEE_CAPABILITY_ECHO:10:10 */ 381 PHYMOD_SYMBOL_FIELD_ENCODE(439, 10, 10), 382 /* SPEED_ECHO:11:11 */ 383 PHYMOD_SYMBOL_FIELD_ENCODE(1103, 11, 11), 384 /* DUPLEX_MODE_ECHO:12:12 */ 385 PHYMOD_SYMBOL_FIELD_ENCODE(434, 12, 12), 386 /* LINK_STATUS_ECHO:13:13 */ 387 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(573, 13, 13) 388 }; 389 static uint32_t BCMI_QTC_XGXS_AN_X4_ABI_SP0_LOC_DEV_CL37_BAM_ABILr_fields[] = 390 { 391 /* OVER1G_PAGE_COUNT:0:1 */ 392 PHYMOD_SYMBOL_FIELD_ENCODE(787, 1, 0), 393 /* OVER1G_ABILITY:2:2 */ 394 PHYMOD_SYMBOL_FIELD_ENCODE(786, 2, 2), 395 /* CL37_BAM_CODE:3:11 */ 396 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(186, 11, 3) 397 }; 398 static uint32_t BCMI_QTC_XGXS_AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_fields[] = 399 { 400 /* SGMII_SPEED:0:2 */ 401 PHYMOD_SYMBOL_FIELD_ENCODE(1055, 2, 0), 402 /* SGMII_FULL_DUPLEX:3:3 */ 403 PHYMOD_SYMBOL_FIELD_ENCODE(1051, 3, 3), 404 /* CL37_FULL_DUPLEX:4:4 */ 405 PHYMOD_SYMBOL_FIELD_ENCODE(191, 4, 4), 406 /* CL37_HALF_DUPLEX:5:5 */ 407 PHYMOD_SYMBOL_FIELD_ENCODE(192, 5, 5), 408 /* CL37_PAUSE:6:7 */ 409 PHYMOD_SYMBOL_FIELD_ENCODE(194, 7, 6), 410 /* CL37_NEXT_PAGE:8:8 */ 411 PHYMOD_SYMBOL_FIELD_ENCODE(193, 8, 8), 412 /* SGMII_MASTER_MODE:9:9 */ 413 PHYMOD_SYMBOL_FIELD_ENCODE(1052, 9, 9), 414 /* LINK_STATUS:10:10 */ 415 PHYMOD_SYMBOL_FIELD_ENCODE(572, 10, 10), 416 /* CL37_AN_RESTART_RESET_DISABLE:11:11 */ 417 PHYMOD_SYMBOL_FIELD_ENCODE(185, 11, 11), 418 /* CL37_SW_RESTART_RESET_DISABLE:12:12 */ 419 PHYMOD_SYMBOL_FIELD_ENCODE(197, 12, 12), 420 /* CL37_AN_DISABLE_RESET_DISABLE:13:13 */ 421 PHYMOD_SYMBOL_FIELD_ENCODE(183, 13, 13), 422 /* EEE_CLOCK_STOP_CAPABILITY:14:14 */ 423 PHYMOD_SYMBOL_FIELD_ENCODE(442, 14, 14), 424 /* EEE_CAPABILITY:15:15 */ 425 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(438, 15, 15) 426 }; 427 static uint32_t BCMI_QTC_XGXS_AN_X4_ABI_SP0_LOC_DEV_OVER1G_ABIL0r_fields[] = 428 { 429 /* BAM_2P5GBASE_X:0:0 */ 430 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(110, 0, 0) 431 }; 432 static uint32_t BCMI_QTC_XGXS_AN_X4_ABI_SP1_CTLSr_fields[] = 433 { 434 /* AN_GOOD_TRAP:2:2 */ 435 PHYMOD_SYMBOL_FIELD_ENCODE(50, 2, 2), 436 /* AN_GOOD_CHECK_TRAP:3:3 */ 437 PHYMOD_SYMBOL_FIELD_ENCODE(49, 3, 3), 438 /* LINKFAILTIMER_DIS:4:4 */ 439 PHYMOD_SYMBOL_FIELD_ENCODE(570, 4, 4), 440 /* LINKFAILTIMERQUAL_EN:5:5 */ 441 PHYMOD_SYMBOL_FIELD_ENCODE(569, 5, 5), 442 /* AN_FAIL_COUNT_LIMIT:6:9 */ 443 PHYMOD_SYMBOL_FIELD_ENCODE(48, 9, 6), 444 /* OUI_CONTROL:10:15 */ 445 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(783, 15, 10) 446 }; 447 static uint32_t BCMI_QTC_XGXS_AN_X4_ABI_SP1_ENSr_fields[] = 448 { 449 /* CL37_AN_RESTART:0:0 */ 450 PHYMOD_SYMBOL_FIELD_ENCODE(184, 0, 0), 451 /* SGMII_TO_CL37_AUTO_ENABLE:1:1 */ 452 PHYMOD_SYMBOL_FIELD_ENCODE(1057, 1, 1), 453 /* CL37_BAM_TO_SGMII_AUTO_ENABLE:2:2 */ 454 PHYMOD_SYMBOL_FIELD_ENCODE(188, 2, 2), 455 /* CL37_ENABLE:3:3 */ 456 PHYMOD_SYMBOL_FIELD_ENCODE(189, 3, 3), 457 /* CL37_SGMII_ENABLE:4:4 */ 458 PHYMOD_SYMBOL_FIELD_ENCODE(196, 4, 4), 459 /* CL37_BAM_ENABLE:5:5 */ 460 PHYMOD_SYMBOL_FIELD_ENCODE(187, 5, 5), 461 /* DISABLE_REMOTE_FAULT_REPORTING:6:6 */ 462 PHYMOD_SYMBOL_FIELD_ENCODE(419, 6, 6), 463 /* QSGMII_EN:7:7 */ 464 PHYMOD_SYMBOL_FIELD_ENCODE(929, 7, 7), 465 /* USXGMII_EN:8:8 */ 466 PHYMOD_SYMBOL_FIELD_ENCODE(1365, 8, 8), 467 /* EEE_CLOCK_CAPABILITY_ECHO:9:9 */ 468 PHYMOD_SYMBOL_FIELD_ENCODE(441, 9, 9), 469 /* EEE_CAPABILITY_ECHO:10:10 */ 470 PHYMOD_SYMBOL_FIELD_ENCODE(439, 10, 10), 471 /* SPEED_ECHO:11:11 */ 472 PHYMOD_SYMBOL_FIELD_ENCODE(1103, 11, 11), 473 /* DUPLEX_MODE_ECHO:12:12 */ 474 PHYMOD_SYMBOL_FIELD_ENCODE(434, 12, 12), 475 /* LINK_STATUS_ECHO:13:13 */ 476 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(573, 13, 13) 477 }; 478 static uint32_t BCMI_QTC_XGXS_AN_X4_ABI_SP1_LOC_DEV_CL37_BAM_ABILr_fields[] = 479 { 480 /* OVER1G_PAGE_COUNT:0:1 */ 481 PHYMOD_SYMBOL_FIELD_ENCODE(787, 1, 0), 482 /* OVER1G_ABILITY:2:2 */ 483 PHYMOD_SYMBOL_FIELD_ENCODE(786, 2, 2), 484 /* CL37_BAM_CODE:3:11 */ 485 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(186, 11, 3) 486 }; 487 static uint32_t BCMI_QTC_XGXS_AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_fields[] = 488 { 489 /* SGMII_SPEED:0:2 */ 490 PHYMOD_SYMBOL_FIELD_ENCODE(1055, 2, 0), 491 /* SGMII_FULL_DUPLEX:3:3 */ 492 PHYMOD_SYMBOL_FIELD_ENCODE(1051, 3, 3), 493 /* CL37_FULL_DUPLEX:4:4 */ 494 PHYMOD_SYMBOL_FIELD_ENCODE(191, 4, 4), 495 /* CL37_HALF_DUPLEX:5:5 */ 496 PHYMOD_SYMBOL_FIELD_ENCODE(192, 5, 5), 497 /* CL37_PAUSE:6:7 */ 498 PHYMOD_SYMBOL_FIELD_ENCODE(194, 7, 6), 499 /* CL37_NEXT_PAGE:8:8 */ 500 PHYMOD_SYMBOL_FIELD_ENCODE(193, 8, 8), 501 /* SGMII_MASTER_MODE:9:9 */ 502 PHYMOD_SYMBOL_FIELD_ENCODE(1052, 9, 9), 503 /* LINK_STATUS:10:10 */ 504 PHYMOD_SYMBOL_FIELD_ENCODE(572, 10, 10), 505 /* CL37_AN_RESTART_RESET_DISABLE:11:11 */ 506 PHYMOD_SYMBOL_FIELD_ENCODE(185, 11, 11), 507 /* CL37_SW_RESTART_RESET_DISABLE:12:12 */ 508 PHYMOD_SYMBOL_FIELD_ENCODE(197, 12, 12), 509 /* CL37_AN_DISABLE_RESET_DISABLE:13:13 */ 510 PHYMOD_SYMBOL_FIELD_ENCODE(183, 13, 13), 511 /* EEE_CLOCK_STOP_CAPABILITY:14:14 */ 512 PHYMOD_SYMBOL_FIELD_ENCODE(442, 14, 14), 513 /* EEE_CAPABILITY:15:15 */ 514 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(438, 15, 15) 515 }; 516 static uint32_t BCMI_QTC_XGXS_AN_X4_ABI_SP1_LOC_DEV_OVER1G_ABIL0r_fields[] = 517 { 518 /* BAM_2P5GBASE_X:0:0 */ 519 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(110, 0, 0) 520 }; 521 static uint32_t BCMI_QTC_XGXS_AN_X4_ABI_SP2_CTLSr_fields[] = 522 { 523 /* AN_GOOD_TRAP:2:2 */ 524 PHYMOD_SYMBOL_FIELD_ENCODE(50, 2, 2), 525 /* AN_GOOD_CHECK_TRAP:3:3 */ 526 PHYMOD_SYMBOL_FIELD_ENCODE(49, 3, 3), 527 /* LINKFAILTIMER_DIS:4:4 */ 528 PHYMOD_SYMBOL_FIELD_ENCODE(570, 4, 4), 529 /* LINKFAILTIMERQUAL_EN:5:5 */ 530 PHYMOD_SYMBOL_FIELD_ENCODE(569, 5, 5), 531 /* AN_FAIL_COUNT_LIMIT:6:9 */ 532 PHYMOD_SYMBOL_FIELD_ENCODE(48, 9, 6), 533 /* OUI_CONTROL:10:15 */ 534 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(783, 15, 10) 535 }; 536 static uint32_t BCMI_QTC_XGXS_AN_X4_ABI_SP2_ENSr_fields[] = 537 { 538 /* CL37_AN_RESTART:0:0 */ 539 PHYMOD_SYMBOL_FIELD_ENCODE(184, 0, 0), 540 /* SGMII_TO_CL37_AUTO_ENABLE:1:1 */ 541 PHYMOD_SYMBOL_FIELD_ENCODE(1057, 1, 1), 542 /* CL37_BAM_TO_SGMII_AUTO_ENABLE:2:2 */ 543 PHYMOD_SYMBOL_FIELD_ENCODE(188, 2, 2), 544 /* CL37_ENABLE:3:3 */ 545 PHYMOD_SYMBOL_FIELD_ENCODE(189, 3, 3), 546 /* CL37_SGMII_ENABLE:4:4 */ 547 PHYMOD_SYMBOL_FIELD_ENCODE(196, 4, 4), 548 /* CL37_BAM_ENABLE:5:5 */ 549 PHYMOD_SYMBOL_FIELD_ENCODE(187, 5, 5), 550 /* DISABLE_REMOTE_FAULT_REPORTING:6:6 */ 551 PHYMOD_SYMBOL_FIELD_ENCODE(419, 6, 6), 552 /* QSGMII_EN:7:7 */ 553 PHYMOD_SYMBOL_FIELD_ENCODE(929, 7, 7), 554 /* USXGMII_EN:8:8 */ 555 PHYMOD_SYMBOL_FIELD_ENCODE(1365, 8, 8), 556 /* EEE_CLOCK_CAPABILITY_ECHO:9:9 */ 557 PHYMOD_SYMBOL_FIELD_ENCODE(441, 9, 9), 558 /* EEE_CAPABILITY_ECHO:10:10 */ 559 PHYMOD_SYMBOL_FIELD_ENCODE(439, 10, 10), 560 /* SPEED_ECHO:11:11 */ 561 PHYMOD_SYMBOL_FIELD_ENCODE(1103, 11, 11), 562 /* DUPLEX_MODE_ECHO:12:12 */ 563 PHYMOD_SYMBOL_FIELD_ENCODE(434, 12, 12), 564 /* LINK_STATUS_ECHO:13:13 */ 565 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(573, 13, 13) 566 }; 567 static uint32_t BCMI_QTC_XGXS_AN_X4_ABI_SP2_LOC_DEV_CL37_BAM_ABILr_fields[] = 568 { 569 /* OVER1G_PAGE_COUNT:0:1 */ 570 PHYMOD_SYMBOL_FIELD_ENCODE(787, 1, 0), 571 /* OVER1G_ABILITY:2:2 */ 572 PHYMOD_SYMBOL_FIELD_ENCODE(786, 2, 2), 573 /* CL37_BAM_CODE:3:11 */ 574 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(186, 11, 3) 575 }; 576 static uint32_t BCMI_QTC_XGXS_AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_fields[] = 577 { 578 /* SGMII_SPEED:0:2 */ 579 PHYMOD_SYMBOL_FIELD_ENCODE(1055, 2, 0), 580 /* SGMII_FULL_DUPLEX:3:3 */ 581 PHYMOD_SYMBOL_FIELD_ENCODE(1051, 3, 3), 582 /* CL37_FULL_DUPLEX:4:4 */ 583 PHYMOD_SYMBOL_FIELD_ENCODE(191, 4, 4), 584 /* CL37_HALF_DUPLEX:5:5 */ 585 PHYMOD_SYMBOL_FIELD_ENCODE(192, 5, 5), 586 /* CL37_PAUSE:6:7 */ 587 PHYMOD_SYMBOL_FIELD_ENCODE(194, 7, 6), 588 /* CL37_NEXT_PAGE:8:8 */ 589 PHYMOD_SYMBOL_FIELD_ENCODE(193, 8, 8), 590 /* SGMII_MASTER_MODE:9:9 */ 591 PHYMOD_SYMBOL_FIELD_ENCODE(1052, 9, 9), 592 /* LINK_STATUS:10:10 */ 593 PHYMOD_SYMBOL_FIELD_ENCODE(572, 10, 10), 594 /* CL37_AN_RESTART_RESET_DISABLE:11:11 */ 595 PHYMOD_SYMBOL_FIELD_ENCODE(185, 11, 11), 596 /* CL37_SW_RESTART_RESET_DISABLE:12:12 */ 597 PHYMOD_SYMBOL_FIELD_ENCODE(197, 12, 12), 598 /* CL37_AN_DISABLE_RESET_DISABLE:13:13 */ 599 PHYMOD_SYMBOL_FIELD_ENCODE(183, 13, 13), 600 /* EEE_CLOCK_STOP_CAPABILITY:14:14 */ 601 PHYMOD_SYMBOL_FIELD_ENCODE(442, 14, 14), 602 /* EEE_CAPABILITY:15:15 */ 603 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(438, 15, 15) 604 }; 605 static uint32_t BCMI_QTC_XGXS_AN_X4_ABI_SP2_LOC_DEV_OVER1G_ABIL0r_fields[] = 606 { 607 /* BAM_2P5GBASE_X:0:0 */ 608 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(110, 0, 0) 609 }; 610 static uint32_t BCMI_QTC_XGXS_AN_X4_ABI_SP3_CTLSr_fields[] = 611 { 612 /* AN_GOOD_TRAP:2:2 */ 613 PHYMOD_SYMBOL_FIELD_ENCODE(50, 2, 2), 614 /* AN_GOOD_CHECK_TRAP:3:3 */ 615 PHYMOD_SYMBOL_FIELD_ENCODE(49, 3, 3), 616 /* LINKFAILTIMER_DIS:4:4 */ 617 PHYMOD_SYMBOL_FIELD_ENCODE(570, 4, 4), 618 /* LINKFAILTIMERQUAL_EN:5:5 */ 619 PHYMOD_SYMBOL_FIELD_ENCODE(569, 5, 5), 620 /* AN_FAIL_COUNT_LIMIT:6:9 */ 621 PHYMOD_SYMBOL_FIELD_ENCODE(48, 9, 6), 622 /* OUI_CONTROL:10:15 */ 623 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(783, 15, 10) 624 }; 625 static uint32_t BCMI_QTC_XGXS_AN_X4_ABI_SP3_ENSr_fields[] = 626 { 627 /* CL37_AN_RESTART:0:0 */ 628 PHYMOD_SYMBOL_FIELD_ENCODE(184, 0, 0), 629 /* SGMII_TO_CL37_AUTO_ENABLE:1:1 */ 630 PHYMOD_SYMBOL_FIELD_ENCODE(1057, 1, 1), 631 /* CL37_BAM_TO_SGMII_AUTO_ENABLE:2:2 */ 632 PHYMOD_SYMBOL_FIELD_ENCODE(188, 2, 2), 633 /* CL37_ENABLE:3:3 */ 634 PHYMOD_SYMBOL_FIELD_ENCODE(189, 3, 3), 635 /* CL37_SGMII_ENABLE:4:4 */ 636 PHYMOD_SYMBOL_FIELD_ENCODE(196, 4, 4), 637 /* CL37_BAM_ENABLE:5:5 */ 638 PHYMOD_SYMBOL_FIELD_ENCODE(187, 5, 5), 639 /* DISABLE_REMOTE_FAULT_REPORTING:6:6 */ 640 PHYMOD_SYMBOL_FIELD_ENCODE(419, 6, 6), 641 /* QSGMII_EN:7:7 */ 642 PHYMOD_SYMBOL_FIELD_ENCODE(929, 7, 7), 643 /* USXGMII_EN:8:8 */ 644 PHYMOD_SYMBOL_FIELD_ENCODE(1365, 8, 8), 645 /* EEE_CLOCK_CAPABILITY_ECHO:9:9 */ 646 PHYMOD_SYMBOL_FIELD_ENCODE(441, 9, 9), 647 /* EEE_CAPABILITY_ECHO:10:10 */ 648 PHYMOD_SYMBOL_FIELD_ENCODE(439, 10, 10), 649 /* SPEED_ECHO:11:11 */ 650 PHYMOD_SYMBOL_FIELD_ENCODE(1103, 11, 11), 651 /* DUPLEX_MODE_ECHO:12:12 */ 652 PHYMOD_SYMBOL_FIELD_ENCODE(434, 12, 12), 653 /* LINK_STATUS_ECHO:13:13 */ 654 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(573, 13, 13) 655 }; 656 static uint32_t BCMI_QTC_XGXS_AN_X4_ABI_SP3_LOC_DEV_CL37_BAM_ABILr_fields[] = 657 { 658 /* OVER1G_PAGE_COUNT:0:1 */ 659 PHYMOD_SYMBOL_FIELD_ENCODE(787, 1, 0), 660 /* OVER1G_ABILITY:2:2 */ 661 PHYMOD_SYMBOL_FIELD_ENCODE(786, 2, 2), 662 /* CL37_BAM_CODE:3:11 */ 663 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(186, 11, 3) 664 }; 665 static uint32_t BCMI_QTC_XGXS_AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_fields[] = 666 { 667 /* SGMII_SPEED:0:2 */ 668 PHYMOD_SYMBOL_FIELD_ENCODE(1055, 2, 0), 669 /* SGMII_FULL_DUPLEX:3:3 */ 670 PHYMOD_SYMBOL_FIELD_ENCODE(1051, 3, 3), 671 /* CL37_FULL_DUPLEX:4:4 */ 672 PHYMOD_SYMBOL_FIELD_ENCODE(191, 4, 4), 673 /* CL37_HALF_DUPLEX:5:5 */ 674 PHYMOD_SYMBOL_FIELD_ENCODE(192, 5, 5), 675 /* CL37_PAUSE:6:7 */ 676 PHYMOD_SYMBOL_FIELD_ENCODE(194, 7, 6), 677 /* CL37_NEXT_PAGE:8:8 */ 678 PHYMOD_SYMBOL_FIELD_ENCODE(193, 8, 8), 679 /* SGMII_MASTER_MODE:9:9 */ 680 PHYMOD_SYMBOL_FIELD_ENCODE(1052, 9, 9), 681 /* LINK_STATUS:10:10 */ 682 PHYMOD_SYMBOL_FIELD_ENCODE(572, 10, 10), 683 /* CL37_AN_RESTART_RESET_DISABLE:11:11 */ 684 PHYMOD_SYMBOL_FIELD_ENCODE(185, 11, 11), 685 /* CL37_SW_RESTART_RESET_DISABLE:12:12 */ 686 PHYMOD_SYMBOL_FIELD_ENCODE(197, 12, 12), 687 /* CL37_AN_DISABLE_RESET_DISABLE:13:13 */ 688 PHYMOD_SYMBOL_FIELD_ENCODE(183, 13, 13), 689 /* EEE_CLOCK_STOP_CAPABILITY:14:14 */ 690 PHYMOD_SYMBOL_FIELD_ENCODE(442, 14, 14), 691 /* EEE_CAPABILITY:15:15 */ 692 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(438, 15, 15) 693 }; 694 static uint32_t BCMI_QTC_XGXS_AN_X4_ABI_SP3_LOC_DEV_OVER1G_ABIL0r_fields[] = 695 { 696 /* BAM_2P5GBASE_X:0:0 */ 697 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(110, 0, 0) 698 }; 699 static uint32_t BCMI_QTC_XGXS_AN_X4_LP_SP0_LP_BASE_PAGE1r_fields[] = 700 { 701 /* LP_BASE_PAGE1_PAGE_DATA:0:15 */ 702 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(645, 15, 0) 703 }; 704 static uint32_t BCMI_QTC_XGXS_AN_X4_LP_SP0_LP_BASE_PAGE2r_fields[] = 705 { 706 /* LP_BASE_PAGE2_PAGE_DATA:0:15 */ 707 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(646, 15, 0) 708 }; 709 static uint32_t BCMI_QTC_XGXS_AN_X4_LP_SP0_LP_BASE_PAGE3r_fields[] = 710 { 711 /* LP_BASE_PAGE3_PAGE_DATA:0:15 */ 712 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(647, 15, 0) 713 }; 714 static uint32_t BCMI_QTC_XGXS_AN_X4_LP_SP0_LP_MP1024_UP1r_fields[] = 715 { 716 /* LP_MP1024_UP1_PAGE_DATA:0:15 */ 717 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(648, 15, 0) 718 }; 719 static uint32_t BCMI_QTC_XGXS_AN_X4_LP_SP0_LP_MP1024_UP2r_fields[] = 720 { 721 /* LP_MP1024_UP2_PAGE_DATA:0:15 */ 722 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(649, 15, 0) 723 }; 724 static uint32_t BCMI_QTC_XGXS_AN_X4_LP_SP0_LP_MP1024_UP3r_fields[] = 725 { 726 /* LP_MP1024_UP3_PAGE_DATA:0:15 */ 727 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(650, 15, 0) 728 }; 729 static uint32_t BCMI_QTC_XGXS_AN_X4_LP_SP0_LP_MP1024_UP4r_fields[] = 730 { 731 /* LP_MP1024_UP4_PAGE_DATA:0:15 */ 732 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(651, 15, 0) 733 }; 734 static uint32_t BCMI_QTC_XGXS_AN_X4_LP_SP0_LP_MP5_UP1r_fields[] = 735 { 736 /* LP_MP5_UP1_PAGE_DATA:0:15 */ 737 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(652, 15, 0) 738 }; 739 static uint32_t BCMI_QTC_XGXS_AN_X4_LP_SP0_LP_MP5_UP2r_fields[] = 740 { 741 /* LP_MP5_UP2_PAGE_DATA:0:15 */ 742 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(653, 15, 0) 743 }; 744 static uint32_t BCMI_QTC_XGXS_AN_X4_LP_SP0_LP_MP5_UP3r_fields[] = 745 { 746 /* LP_MP5_UP3_PAGE_DATA:0:15 */ 747 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(654, 15, 0) 748 }; 749 static uint32_t BCMI_QTC_XGXS_AN_X4_LP_SP0_LP_MP5_UP4r_fields[] = 750 { 751 /* LP_MP5_UP4_PAGE_DATA:0:15 */ 752 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(655, 15, 0) 753 }; 754 static uint32_t BCMI_QTC_XGXS_AN_X4_LP_SP1_LP_BASE_PAGE1r_fields[] = 755 { 756 /* LP_BASE_PAGE1_PAGE_DATA:0:15 */ 757 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(645, 15, 0) 758 }; 759 static uint32_t BCMI_QTC_XGXS_AN_X4_LP_SP1_LP_BASE_PAGE2r_fields[] = 760 { 761 /* LP_BASE_PAGE2_PAGE_DATA:0:15 */ 762 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(646, 15, 0) 763 }; 764 static uint32_t BCMI_QTC_XGXS_AN_X4_LP_SP1_LP_BASE_PAGE3r_fields[] = 765 { 766 /* LP_BASE_PAGE3_PAGE_DATA:0:15 */ 767 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(647, 15, 0) 768 }; 769 static uint32_t BCMI_QTC_XGXS_AN_X4_LP_SP1_LP_MP1024_UP1r_fields[] = 770 { 771 /* LP_MP1024_UP1_PAGE_DATA:0:15 */ 772 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(648, 15, 0) 773 }; 774 static uint32_t BCMI_QTC_XGXS_AN_X4_LP_SP1_LP_MP1024_UP2r_fields[] = 775 { 776 /* LP_MP1024_UP2_PAGE_DATA:0:15 */ 777 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(649, 15, 0) 778 }; 779 static uint32_t BCMI_QTC_XGXS_AN_X4_LP_SP1_LP_MP1024_UP3r_fields[] = 780 { 781 /* LP_MP1024_UP3_PAGE_DATA:0:15 */ 782 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(650, 15, 0) 783 }; 784 static uint32_t BCMI_QTC_XGXS_AN_X4_LP_SP1_LP_MP1024_UP4r_fields[] = 785 { 786 /* LP_MP1024_UP4_PAGE_DATA:0:15 */ 787 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(651, 15, 0) 788 }; 789 static uint32_t BCMI_QTC_XGXS_AN_X4_LP_SP1_LP_MP5_UP1r_fields[] = 790 { 791 /* LP_MP5_UP1_PAGE_DATA:0:15 */ 792 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(652, 15, 0) 793 }; 794 static uint32_t BCMI_QTC_XGXS_AN_X4_LP_SP1_LP_MP5_UP2r_fields[] = 795 { 796 /* LP_MP5_UP2_PAGE_DATA:0:15 */ 797 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(653, 15, 0) 798 }; 799 static uint32_t BCMI_QTC_XGXS_AN_X4_LP_SP1_LP_MP5_UP3r_fields[] = 800 { 801 /* LP_MP5_UP3_PAGE_DATA:0:15 */ 802 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(654, 15, 0) 803 }; 804 static uint32_t BCMI_QTC_XGXS_AN_X4_LP_SP1_LP_MP5_UP4r_fields[] = 805 { 806 /* LP_MP5_UP4_PAGE_DATA:0:15 */ 807 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(655, 15, 0) 808 }; 809 static uint32_t BCMI_QTC_XGXS_AN_X4_LP_SP2_LP_BASE_PAGE1r_fields[] = 810 { 811 /* LP_BASE_PAGE1_PAGE_DATA:0:15 */ 812 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(645, 15, 0) 813 }; 814 static uint32_t BCMI_QTC_XGXS_AN_X4_LP_SP2_LP_BASE_PAGE2r_fields[] = 815 { 816 /* LP_BASE_PAGE2_PAGE_DATA:0:15 */ 817 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(646, 15, 0) 818 }; 819 static uint32_t BCMI_QTC_XGXS_AN_X4_LP_SP2_LP_BASE_PAGE3r_fields[] = 820 { 821 /* LP_BASE_PAGE3_PAGE_DATA:0:15 */ 822 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(647, 15, 0) 823 }; 824 static uint32_t BCMI_QTC_XGXS_AN_X4_LP_SP2_LP_MP1024_UP1r_fields[] = 825 { 826 /* LP_MP1024_UP1_PAGE_DATA:0:15 */ 827 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(648, 15, 0) 828 }; 829 static uint32_t BCMI_QTC_XGXS_AN_X4_LP_SP2_LP_MP1024_UP2r_fields[] = 830 { 831 /* LP_MP1024_UP2_PAGE_DATA:0:15 */ 832 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(649, 15, 0) 833 }; 834 static uint32_t BCMI_QTC_XGXS_AN_X4_LP_SP2_LP_MP1024_UP3r_fields[] = 835 { 836 /* LP_MP1024_UP3_PAGE_DATA:0:15 */ 837 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(650, 15, 0) 838 }; 839 static uint32_t BCMI_QTC_XGXS_AN_X4_LP_SP2_LP_MP1024_UP4r_fields[] = 840 { 841 /* LP_MP1024_UP4_PAGE_DATA:0:15 */ 842 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(651, 15, 0) 843 }; 844 static uint32_t BCMI_QTC_XGXS_AN_X4_LP_SP2_LP_MP5_UP1r_fields[] = 845 { 846 /* LP_MP5_UP1_PAGE_DATA:0:15 */ 847 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(652, 15, 0) 848 }; 849 static uint32_t BCMI_QTC_XGXS_AN_X4_LP_SP2_LP_MP5_UP2r_fields[] = 850 { 851 /* LP_MP5_UP2_PAGE_DATA:0:15 */ 852 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(653, 15, 0) 853 }; 854 static uint32_t BCMI_QTC_XGXS_AN_X4_LP_SP2_LP_MP5_UP3r_fields[] = 855 { 856 /* LP_MP5_UP3_PAGE_DATA:0:15 */ 857 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(654, 15, 0) 858 }; 859 static uint32_t BCMI_QTC_XGXS_AN_X4_LP_SP2_LP_MP5_UP4r_fields[] = 860 { 861 /* LP_MP5_UP4_PAGE_DATA:0:15 */ 862 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(655, 15, 0) 863 }; 864 static uint32_t BCMI_QTC_XGXS_AN_X4_LP_SP3_LP_BASE_PAGE1r_fields[] = 865 { 866 /* LP_BASE_PAGE1_PAGE_DATA:0:15 */ 867 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(645, 15, 0) 868 }; 869 static uint32_t BCMI_QTC_XGXS_AN_X4_LP_SP3_LP_BASE_PAGE2r_fields[] = 870 { 871 /* LP_BASE_PAGE2_PAGE_DATA:0:15 */ 872 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(646, 15, 0) 873 }; 874 static uint32_t BCMI_QTC_XGXS_AN_X4_LP_SP3_LP_BASE_PAGE3r_fields[] = 875 { 876 /* LP_BASE_PAGE3_PAGE_DATA:0:15 */ 877 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(647, 15, 0) 878 }; 879 static uint32_t BCMI_QTC_XGXS_AN_X4_LP_SP3_LP_MP1024_UP1r_fields[] = 880 { 881 /* LP_MP1024_UP1_PAGE_DATA:0:15 */ 882 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(648, 15, 0) 883 }; 884 static uint32_t BCMI_QTC_XGXS_AN_X4_LP_SP3_LP_MP1024_UP2r_fields[] = 885 { 886 /* LP_MP1024_UP2_PAGE_DATA:0:15 */ 887 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(649, 15, 0) 888 }; 889 static uint32_t BCMI_QTC_XGXS_AN_X4_LP_SP3_LP_MP1024_UP3r_fields[] = 890 { 891 /* LP_MP1024_UP3_PAGE_DATA:0:15 */ 892 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(650, 15, 0) 893 }; 894 static uint32_t BCMI_QTC_XGXS_AN_X4_LP_SP3_LP_MP1024_UP4r_fields[] = 895 { 896 /* LP_MP1024_UP4_PAGE_DATA:0:15 */ 897 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(651, 15, 0) 898 }; 899 static uint32_t BCMI_QTC_XGXS_AN_X4_LP_SP3_LP_MP5_UP1r_fields[] = 900 { 901 /* LP_MP5_UP1_PAGE_DATA:0:15 */ 902 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(652, 15, 0) 903 }; 904 static uint32_t BCMI_QTC_XGXS_AN_X4_LP_SP3_LP_MP5_UP2r_fields[] = 905 { 906 /* LP_MP5_UP2_PAGE_DATA:0:15 */ 907 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(653, 15, 0) 908 }; 909 static uint32_t BCMI_QTC_XGXS_AN_X4_LP_SP3_LP_MP5_UP3r_fields[] = 910 { 911 /* LP_MP5_UP3_PAGE_DATA:0:15 */ 912 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(654, 15, 0) 913 }; 914 static uint32_t BCMI_QTC_XGXS_AN_X4_LP_SP3_LP_MP5_UP4r_fields[] = 915 { 916 /* LP_MP5_UP4_PAGE_DATA:0:15 */ 917 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(655, 15, 0) 918 }; 919 static uint32_t BCMI_QTC_XGXS_AN_X4_SW_SP0_AN_ABIL_RESOLUTION_STSr_fields[] = 920 { 921 /* AN_HCD_SWITCH_TO_CL37:0:0 */ 922 PHYMOD_SYMBOL_FIELD_ENCODE(57, 0, 0), 923 /* AN_HCD_HIGIG2:1:1 */ 924 PHYMOD_SYMBOL_FIELD_ENCODE(54, 1, 1), 925 /* AN_HCD_CL72:2:2 */ 926 PHYMOD_SYMBOL_FIELD_ENCODE(51, 2, 2), 927 /* AN_HCD_FEC:3:3 */ 928 PHYMOD_SYMBOL_FIELD_ENCODE(53, 3, 3), 929 /* AN_HCD_SPEED:4:11 */ 930 PHYMOD_SYMBOL_FIELD_ENCODE(56, 11, 4), 931 /* AN_HCD_PAUSE:12:13 */ 932 PHYMOD_SYMBOL_FIELD_ENCODE(55, 13, 12), 933 /* AN_HCD_DUPLEX:14:14 */ 934 PHYMOD_SYMBOL_FIELD_ENCODE(52, 14, 14), 935 /* AN_ST_RESOLUTION_ERR:15:15 */ 936 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(92, 15, 15) 937 }; 938 static uint32_t BCMI_QTC_XGXS_AN_X4_SW_SP0_AN_MISC_STSr_fields[] = 939 { 940 /* PD_HCD_KX4_OR_KX:0:0 */ 941 PHYMOD_SYMBOL_FIELD_ENCODE(830, 0, 0), 942 /* PD_IN_PROGRESS:1:1 */ 943 PHYMOD_SYMBOL_FIELD_ENCODE(831, 1, 1), 944 /* AN_FAIL_COUNT:2:5 */ 945 PHYMOD_SYMBOL_FIELD_ENCODE(47, 5, 2), 946 /* AN_ACTIVE:6:6 */ 947 PHYMOD_SYMBOL_FIELD_ENCODE(44, 6, 6), 948 /* PD_COMPLETED:7:7 */ 949 PHYMOD_SYMBOL_FIELD_ENCODE(829, 7, 7), 950 /* REMOTE_FAULT_IN_BASE_PAGE:8:8 */ 951 PHYMOD_SYMBOL_FIELD_ENCODE(952, 8, 8), 952 /* AN_RETRY_COUNT:9:14 */ 953 PHYMOD_SYMBOL_FIELD_ENCODE(63, 14, 9), 954 /* AN_COMPLETE:15:15 */ 955 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(45, 15, 15) 956 }; 957 static uint32_t BCMI_QTC_XGXS_AN_X4_SW_SP0_AN_PAGE_DECR_STSr_fields[] = 958 { 959 /* AN_RX_ST_STATE:0:1 */ 960 PHYMOD_SYMBOL_FIELD_ENCODE(75, 1, 0), 961 /* AN_RX_ST_RUDI_INVALID:2:2 */ 962 PHYMOD_SYMBOL_FIELD_ENCODE(74, 2, 2), 963 /* AN_RX_ST_RUDI_CONFIG:3:3 */ 964 PHYMOD_SYMBOL_FIELD_ENCODE(72, 3, 3), 965 /* AN_RX_ST_RUDI_IDLE:4:4 */ 966 PHYMOD_SYMBOL_FIELD_ENCODE(73, 4, 4), 967 /* AN_RX_ST_PAGE:5:5 */ 968 PHYMOD_SYMBOL_FIELD_ENCODE(66, 5, 5), 969 /* AN_RX_ST_MV_PAIR:6:6 */ 970 PHYMOD_SYMBOL_FIELD_ENCODE(65, 6, 6), 971 /* AN_RX_ST_CLK_TRANS_MISS:7:7 */ 972 PHYMOD_SYMBOL_FIELD_ENCODE(64, 7, 7), 973 /* AN_RX_ST_PAGE_TOO_LONG:8:8 */ 974 PHYMOD_SYMBOL_FIELD_ENCODE(67, 8, 8), 975 /* AN_RX_ST_PAGE_TOO_SHORT:9:9 */ 976 PHYMOD_SYMBOL_FIELD_ENCODE(68, 9, 9), 977 /* AN_RX_ST_PULSE_TOO_LONG:10:10 */ 978 PHYMOD_SYMBOL_FIELD_ENCODE(69, 10, 10), 979 /* AN_RX_ST_PULSE_TOO_SHORT:11:11 */ 980 PHYMOD_SYMBOL_FIELD_ENCODE(71, 11, 11), 981 /* AN_RX_ST_PULSE_TOO_MODERATE:12:12 */ 982 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(70, 12, 12) 983 }; 984 static uint32_t BCMI_QTC_XGXS_AN_X4_SW_SP0_AN_PAGE_EXCHANGEER_STSr_fields[] = 985 { 986 /* AN_ST_CONFIG_RESTART:0:0 */ 987 PHYMOD_SYMBOL_FIELD_ENCODE(84, 0, 0), 988 /* AN_ST_IDLE_DETECT:1:1 */ 989 PHYMOD_SYMBOL_FIELD_ENCODE(89, 1, 1), 990 /* AN_ST_DISABLE_LINK:2:2 */ 991 PHYMOD_SYMBOL_FIELD_ENCODE(86, 2, 2), 992 /* AN_ST_ERROR_STATE:3:3 */ 993 PHYMOD_SYMBOL_FIELD_ENCODE(87, 3, 3), 994 /* AN_ST_AN_ENABLE:4:4 */ 995 PHYMOD_SYMBOL_FIELD_ENCODE(78, 4, 4), 996 /* AN_ST_ABILITY_DETECT:5:5 */ 997 PHYMOD_SYMBOL_FIELD_ENCODE(76, 5, 5), 998 /* AN_ST_ACK_DETECT:6:6 */ 999 PHYMOD_SYMBOL_FIELD_ENCODE(77, 6, 6), 1000 /* AN_ST_COMPLETE_ACK:7:7 */ 1001 PHYMOD_SYMBOL_FIELD_ENCODE(82, 7, 7), 1002 /* AN_ST_CONSISTENCY_MISMATCH:8:8 */ 1003 PHYMOD_SYMBOL_FIELD_ENCODE(85, 8, 8), 1004 /* AN_ST_CONFIG_NONZERO:9:9 */ 1005 PHYMOD_SYMBOL_FIELD_ENCODE(83, 9, 9), 1006 /* AN_ST_RESTART:10:10 */ 1007 PHYMOD_SYMBOL_FIELD_ENCODE(93, 10, 10), 1008 /* AN_ST_AN_GOOD_CHECK:11:11 */ 1009 PHYMOD_SYMBOL_FIELD_ENCODE(79, 11, 11), 1010 /* AN_ST_LINK_OK:12:12 */ 1011 PHYMOD_SYMBOL_FIELD_ENCODE(90, 12, 12), 1012 /* AN_ST_NEXT_PAGE_WAIT:13:13 */ 1013 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(91, 13, 13) 1014 }; 1015 static uint32_t BCMI_QTC_XGXS_AN_X4_SW_SP0_AN_PAGE_SEQUENCER_STSr_fields[] = 1016 { 1017 /* AN_ST_CL73_COMPLETE:0:0 */ 1018 PHYMOD_SYMBOL_FIELD_ENCODE(81, 0, 0), 1019 /* AN_ST_CL37_COMPLETE:1:1 */ 1020 PHYMOD_SYMBOL_FIELD_ENCODE(80, 1, 1), 1021 /* AN_ST_RX_NP_TOGGLE_ERR:2:2 */ 1022 PHYMOD_SYMBOL_FIELD_ENCODE(101, 2, 2), 1023 /* AN_ST_RX_INVALID_SEQ:3:3 */ 1024 PHYMOD_SYMBOL_FIELD_ENCODE(95, 3, 3), 1025 /* AN_ST_RX_UP_OUI_MATCH:4:4 */ 1026 PHYMOD_SYMBOL_FIELD_ENCODE(104, 4, 4), 1027 /* AN_ST_RX_UP_OUI_MISMATCH:5:5 */ 1028 PHYMOD_SYMBOL_FIELD_ENCODE(105, 5, 5), 1029 /* AN_ST_RX_UP_3:6:6 */ 1030 PHYMOD_SYMBOL_FIELD_ENCODE(103, 6, 6), 1031 /* AN_ST_RX_MP_MISMATCH:7:7 */ 1032 PHYMOD_SYMBOL_FIELD_ENCODE(96, 7, 7), 1033 /* AN_ST_RX_MP_OVER1G:8:8 */ 1034 PHYMOD_SYMBOL_FIELD_ENCODE(99, 8, 8), 1035 /* AN_ST_RX_MP_OUI:9:9 */ 1036 PHYMOD_SYMBOL_FIELD_ENCODE(98, 9, 9), 1037 /* AN_ST_RX_MP_NULL:10:10 */ 1038 PHYMOD_SYMBOL_FIELD_ENCODE(97, 10, 10), 1039 /* AN_ST_RX_NP:11:11 */ 1040 PHYMOD_SYMBOL_FIELD_ENCODE(100, 11, 11), 1041 /* AN_ST_RX_BP:12:12 */ 1042 PHYMOD_SYMBOL_FIELD_ENCODE(94, 12, 12), 1043 /* AN_ST_RX_SGMII_MISMATCH:13:13 */ 1044 PHYMOD_SYMBOL_FIELD_ENCODE(102, 13, 13), 1045 /* AN_ST_HP_MODE:14:14 */ 1046 PHYMOD_SYMBOL_FIELD_ENCODE(88, 14, 14), 1047 /* AN_ST_SGMII_MODE:15:15 */ 1048 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(106, 15, 15) 1049 }; 1050 static uint32_t BCMI_QTC_XGXS_AN_X4_SW_SP0_AN_SEQ_UNEXPECTED_PAGEr_fields[] = 1051 { 1052 /* SEQ_UNEXPECTED_PAGE:0:15 */ 1053 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1049, 15, 0) 1054 }; 1055 static uint32_t BCMI_QTC_XGXS_AN_X4_SW_SP0_LD_CTLr_fields[] = 1056 { 1057 /* SW_HCD:0:0 */ 1058 PHYMOD_SYMBOL_FIELD_ENCODE(1117, 0, 0), 1059 /* SW_AN:1:1 */ 1060 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1116, 1, 1) 1061 }; 1062 static uint32_t BCMI_QTC_XGXS_AN_X4_SW_SP0_LD_PAGE0r_fields[] = 1063 { 1064 /* LD_PAGE_0_PAGE_DATA:0:15 */ 1065 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(566, 15, 0) 1066 }; 1067 static uint32_t BCMI_QTC_XGXS_AN_X4_SW_SP0_LD_PAGE1r_fields[] = 1068 { 1069 /* LD_PAGE_1_PAGE_DATA:0:15 */ 1070 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(567, 15, 0) 1071 }; 1072 static uint32_t BCMI_QTC_XGXS_AN_X4_SW_SP0_LD_PAGE2r_fields[] = 1073 { 1074 /* LD_PAGE_2_PAGE_DATA:0:15 */ 1075 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(568, 15, 0) 1076 }; 1077 static uint32_t BCMI_QTC_XGXS_AN_X4_SW_SP0_LP_PAGE0r_fields[] = 1078 { 1079 /* LP_PAGE_0_PAGE_DATA:0:15 */ 1080 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(656, 15, 0) 1081 }; 1082 static uint32_t BCMI_QTC_XGXS_AN_X4_SW_SP0_LP_PAGE1r_fields[] = 1083 { 1084 /* LP_PAGE_1_PAGE_DATA:0:15 */ 1085 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(657, 15, 0) 1086 }; 1087 static uint32_t BCMI_QTC_XGXS_AN_X4_SW_SP0_LP_PAGE2r_fields[] = 1088 { 1089 /* LP_PAGE_2_PAGE_DATA:0:15 */ 1090 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(658, 15, 0) 1091 }; 1092 static uint32_t BCMI_QTC_XGXS_AN_X4_SW_SP0_SW_CTL_STSr_fields[] = 1093 { 1094 /* TLA_LN_SEQUENCER_FSM_STATUS1:0:7 */ 1095 PHYMOD_SYMBOL_FIELD_ENCODE(1173, 7, 0), 1096 /* PD_CL37_COMPLETED:8:8 */ 1097 PHYMOD_SYMBOL_FIELD_ENCODE(828, 8, 8), 1098 /* LP_STATUS_VALID:13:13 */ 1099 PHYMOD_SYMBOL_FIELD_ENCODE(659, 13, 13), 1100 /* LD_CONTROL_VALID:14:14 */ 1101 PHYMOD_SYMBOL_FIELD_ENCODE(565, 14, 14), 1102 /* AN_COMPLETED_SW:15:15 */ 1103 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(46, 15, 15) 1104 }; 1105 static uint32_t BCMI_QTC_XGXS_AN_X4_SW_SP0_TLA_SEQUENCER_STSr_fields[] = 1106 { 1107 /* TLA_LN_SEQUENCER_FSM_STATUS:0:15 */ 1108 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1172, 15, 0) 1109 }; 1110 static uint32_t BCMI_QTC_XGXS_AN_X4_SW_SP1_AN_ABIL_RESOLUTION_STSr_fields[] = 1111 { 1112 /* AN_HCD_SWITCH_TO_CL37:0:0 */ 1113 PHYMOD_SYMBOL_FIELD_ENCODE(57, 0, 0), 1114 /* AN_HCD_HIGIG2:1:1 */ 1115 PHYMOD_SYMBOL_FIELD_ENCODE(54, 1, 1), 1116 /* AN_HCD_CL72:2:2 */ 1117 PHYMOD_SYMBOL_FIELD_ENCODE(51, 2, 2), 1118 /* AN_HCD_FEC:3:3 */ 1119 PHYMOD_SYMBOL_FIELD_ENCODE(53, 3, 3), 1120 /* AN_HCD_SPEED:4:11 */ 1121 PHYMOD_SYMBOL_FIELD_ENCODE(56, 11, 4), 1122 /* AN_HCD_PAUSE:12:13 */ 1123 PHYMOD_SYMBOL_FIELD_ENCODE(55, 13, 12), 1124 /* AN_HCD_DUPLEX:14:14 */ 1125 PHYMOD_SYMBOL_FIELD_ENCODE(52, 14, 14), 1126 /* AN_ST_RESOLUTION_ERR:15:15 */ 1127 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(92, 15, 15) 1128 }; 1129 static uint32_t BCMI_QTC_XGXS_AN_X4_SW_SP1_AN_MISC_STSr_fields[] = 1130 { 1131 /* PD_HCD_KX4_OR_KX:0:0 */ 1132 PHYMOD_SYMBOL_FIELD_ENCODE(830, 0, 0), 1133 /* PD_IN_PROGRESS:1:1 */ 1134 PHYMOD_SYMBOL_FIELD_ENCODE(831, 1, 1), 1135 /* AN_FAIL_COUNT:2:5 */ 1136 PHYMOD_SYMBOL_FIELD_ENCODE(47, 5, 2), 1137 /* AN_ACTIVE:6:6 */ 1138 PHYMOD_SYMBOL_FIELD_ENCODE(44, 6, 6), 1139 /* PD_COMPLETED:7:7 */ 1140 PHYMOD_SYMBOL_FIELD_ENCODE(829, 7, 7), 1141 /* REMOTE_FAULT_IN_BASE_PAGE:8:8 */ 1142 PHYMOD_SYMBOL_FIELD_ENCODE(952, 8, 8), 1143 /* AN_RETRY_COUNT:9:14 */ 1144 PHYMOD_SYMBOL_FIELD_ENCODE(63, 14, 9), 1145 /* AN_COMPLETE:15:15 */ 1146 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(45, 15, 15) 1147 }; 1148 static uint32_t BCMI_QTC_XGXS_AN_X4_SW_SP1_AN_PAGE_DECR_STSr_fields[] = 1149 { 1150 /* AN_RX_ST_STATE:0:1 */ 1151 PHYMOD_SYMBOL_FIELD_ENCODE(75, 1, 0), 1152 /* AN_RX_ST_RUDI_INVALID:2:2 */ 1153 PHYMOD_SYMBOL_FIELD_ENCODE(74, 2, 2), 1154 /* AN_RX_ST_RUDI_CONFIG:3:3 */ 1155 PHYMOD_SYMBOL_FIELD_ENCODE(72, 3, 3), 1156 /* AN_RX_ST_RUDI_IDLE:4:4 */ 1157 PHYMOD_SYMBOL_FIELD_ENCODE(73, 4, 4), 1158 /* AN_RX_ST_PAGE:5:5 */ 1159 PHYMOD_SYMBOL_FIELD_ENCODE(66, 5, 5), 1160 /* AN_RX_ST_MV_PAIR:6:6 */ 1161 PHYMOD_SYMBOL_FIELD_ENCODE(65, 6, 6), 1162 /* AN_RX_ST_CLK_TRANS_MISS:7:7 */ 1163 PHYMOD_SYMBOL_FIELD_ENCODE(64, 7, 7), 1164 /* AN_RX_ST_PAGE_TOO_LONG:8:8 */ 1165 PHYMOD_SYMBOL_FIELD_ENCODE(67, 8, 8), 1166 /* AN_RX_ST_PAGE_TOO_SHORT:9:9 */ 1167 PHYMOD_SYMBOL_FIELD_ENCODE(68, 9, 9), 1168 /* AN_RX_ST_PULSE_TOO_LONG:10:10 */ 1169 PHYMOD_SYMBOL_FIELD_ENCODE(69, 10, 10), 1170 /* AN_RX_ST_PULSE_TOO_SHORT:11:11 */ 1171 PHYMOD_SYMBOL_FIELD_ENCODE(71, 11, 11), 1172 /* AN_RX_ST_PULSE_TOO_MODERATE:12:12 */ 1173 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(70, 12, 12) 1174 }; 1175 static uint32_t BCMI_QTC_XGXS_AN_X4_SW_SP1_AN_PAGE_EXCHANGEER_STSr_fields[] = 1176 { 1177 /* AN_ST_CONFIG_RESTART:0:0 */ 1178 PHYMOD_SYMBOL_FIELD_ENCODE(84, 0, 0), 1179 /* AN_ST_IDLE_DETECT:1:1 */ 1180 PHYMOD_SYMBOL_FIELD_ENCODE(89, 1, 1), 1181 /* AN_ST_DISABLE_LINK:2:2 */ 1182 PHYMOD_SYMBOL_FIELD_ENCODE(86, 2, 2), 1183 /* AN_ST_ERROR_STATE:3:3 */ 1184 PHYMOD_SYMBOL_FIELD_ENCODE(87, 3, 3), 1185 /* AN_ST_AN_ENABLE:4:4 */ 1186 PHYMOD_SYMBOL_FIELD_ENCODE(78, 4, 4), 1187 /* AN_ST_ABILITY_DETECT:5:5 */ 1188 PHYMOD_SYMBOL_FIELD_ENCODE(76, 5, 5), 1189 /* AN_ST_ACK_DETECT:6:6 */ 1190 PHYMOD_SYMBOL_FIELD_ENCODE(77, 6, 6), 1191 /* AN_ST_COMPLETE_ACK:7:7 */ 1192 PHYMOD_SYMBOL_FIELD_ENCODE(82, 7, 7), 1193 /* AN_ST_CONSISTENCY_MISMATCH:8:8 */ 1194 PHYMOD_SYMBOL_FIELD_ENCODE(85, 8, 8), 1195 /* AN_ST_CONFIG_NONZERO:9:9 */ 1196 PHYMOD_SYMBOL_FIELD_ENCODE(83, 9, 9), 1197 /* AN_ST_RESTART:10:10 */ 1198 PHYMOD_SYMBOL_FIELD_ENCODE(93, 10, 10), 1199 /* AN_ST_AN_GOOD_CHECK:11:11 */ 1200 PHYMOD_SYMBOL_FIELD_ENCODE(79, 11, 11), 1201 /* AN_ST_LINK_OK:12:12 */ 1202 PHYMOD_SYMBOL_FIELD_ENCODE(90, 12, 12), 1203 /* AN_ST_NEXT_PAGE_WAIT:13:13 */ 1204 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(91, 13, 13) 1205 }; 1206 static uint32_t BCMI_QTC_XGXS_AN_X4_SW_SP1_AN_PAGE_SEQUENCER_STSr_fields[] = 1207 { 1208 /* AN_ST_CL73_COMPLETE:0:0 */ 1209 PHYMOD_SYMBOL_FIELD_ENCODE(81, 0, 0), 1210 /* AN_ST_CL37_COMPLETE:1:1 */ 1211 PHYMOD_SYMBOL_FIELD_ENCODE(80, 1, 1), 1212 /* AN_ST_RX_NP_TOGGLE_ERR:2:2 */ 1213 PHYMOD_SYMBOL_FIELD_ENCODE(101, 2, 2), 1214 /* AN_ST_RX_INVALID_SEQ:3:3 */ 1215 PHYMOD_SYMBOL_FIELD_ENCODE(95, 3, 3), 1216 /* AN_ST_RX_UP_OUI_MATCH:4:4 */ 1217 PHYMOD_SYMBOL_FIELD_ENCODE(104, 4, 4), 1218 /* AN_ST_RX_UP_OUI_MISMATCH:5:5 */ 1219 PHYMOD_SYMBOL_FIELD_ENCODE(105, 5, 5), 1220 /* AN_ST_RX_UP_3:6:6 */ 1221 PHYMOD_SYMBOL_FIELD_ENCODE(103, 6, 6), 1222 /* AN_ST_RX_MP_MISMATCH:7:7 */ 1223 PHYMOD_SYMBOL_FIELD_ENCODE(96, 7, 7), 1224 /* AN_ST_RX_MP_OVER1G:8:8 */ 1225 PHYMOD_SYMBOL_FIELD_ENCODE(99, 8, 8), 1226 /* AN_ST_RX_MP_OUI:9:9 */ 1227 PHYMOD_SYMBOL_FIELD_ENCODE(98, 9, 9), 1228 /* AN_ST_RX_MP_NULL:10:10 */ 1229 PHYMOD_SYMBOL_FIELD_ENCODE(97, 10, 10), 1230 /* AN_ST_RX_NP:11:11 */ 1231 PHYMOD_SYMBOL_FIELD_ENCODE(100, 11, 11), 1232 /* AN_ST_RX_BP:12:12 */ 1233 PHYMOD_SYMBOL_FIELD_ENCODE(94, 12, 12), 1234 /* AN_ST_RX_SGMII_MISMATCH:13:13 */ 1235 PHYMOD_SYMBOL_FIELD_ENCODE(102, 13, 13), 1236 /* AN_ST_HP_MODE:14:14 */ 1237 PHYMOD_SYMBOL_FIELD_ENCODE(88, 14, 14), 1238 /* AN_ST_SGMII_MODE:15:15 */ 1239 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(106, 15, 15) 1240 }; 1241 static uint32_t BCMI_QTC_XGXS_AN_X4_SW_SP1_AN_SEQ_UNEXPECTED_PAGEr_fields[] = 1242 { 1243 /* SEQ_UNEXPECTED_PAGE:0:15 */ 1244 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1049, 15, 0) 1245 }; 1246 static uint32_t BCMI_QTC_XGXS_AN_X4_SW_SP1_LD_CTLr_fields[] = 1247 { 1248 /* SW_HCD:0:0 */ 1249 PHYMOD_SYMBOL_FIELD_ENCODE(1117, 0, 0), 1250 /* SW_AN:1:1 */ 1251 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1116, 1, 1) 1252 }; 1253 static uint32_t BCMI_QTC_XGXS_AN_X4_SW_SP1_LD_PAGE0r_fields[] = 1254 { 1255 /* LD_PAGE_0_PAGE_DATA:0:15 */ 1256 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(566, 15, 0) 1257 }; 1258 static uint32_t BCMI_QTC_XGXS_AN_X4_SW_SP1_LD_PAGE1r_fields[] = 1259 { 1260 /* LD_PAGE_1_PAGE_DATA:0:15 */ 1261 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(567, 15, 0) 1262 }; 1263 static uint32_t BCMI_QTC_XGXS_AN_X4_SW_SP1_LD_PAGE2r_fields[] = 1264 { 1265 /* LD_PAGE_2_PAGE_DATA:0:15 */ 1266 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(568, 15, 0) 1267 }; 1268 static uint32_t BCMI_QTC_XGXS_AN_X4_SW_SP1_LP_PAGE0r_fields[] = 1269 { 1270 /* LP_PAGE_0_PAGE_DATA:0:15 */ 1271 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(656, 15, 0) 1272 }; 1273 static uint32_t BCMI_QTC_XGXS_AN_X4_SW_SP1_LP_PAGE1r_fields[] = 1274 { 1275 /* LP_PAGE_1_PAGE_DATA:0:15 */ 1276 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(657, 15, 0) 1277 }; 1278 static uint32_t BCMI_QTC_XGXS_AN_X4_SW_SP1_LP_PAGE2r_fields[] = 1279 { 1280 /* LP_PAGE_2_PAGE_DATA:0:15 */ 1281 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(658, 15, 0) 1282 }; 1283 static uint32_t BCMI_QTC_XGXS_AN_X4_SW_SP1_SW_CTL_STSr_fields[] = 1284 { 1285 /* TLA_LN_SEQUENCER_FSM_STATUS1:0:7 */ 1286 PHYMOD_SYMBOL_FIELD_ENCODE(1173, 7, 0), 1287 /* PD_CL37_COMPLETED:8:8 */ 1288 PHYMOD_SYMBOL_FIELD_ENCODE(828, 8, 8), 1289 /* LP_STATUS_VALID:13:13 */ 1290 PHYMOD_SYMBOL_FIELD_ENCODE(659, 13, 13), 1291 /* LD_CONTROL_VALID:14:14 */ 1292 PHYMOD_SYMBOL_FIELD_ENCODE(565, 14, 14), 1293 /* AN_COMPLETED_SW:15:15 */ 1294 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(46, 15, 15) 1295 }; 1296 static uint32_t BCMI_QTC_XGXS_AN_X4_SW_SP1_TLA_SEQUENCER_STSr_fields[] = 1297 { 1298 /* TLA_LN_SEQUENCER_FSM_STATUS:0:15 */ 1299 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1172, 15, 0) 1300 }; 1301 static uint32_t BCMI_QTC_XGXS_AN_X4_SW_SP2_AN_ABIL_RESOLUTION_STSr_fields[] = 1302 { 1303 /* AN_HCD_SWITCH_TO_CL37:0:0 */ 1304 PHYMOD_SYMBOL_FIELD_ENCODE(57, 0, 0), 1305 /* AN_HCD_HIGIG2:1:1 */ 1306 PHYMOD_SYMBOL_FIELD_ENCODE(54, 1, 1), 1307 /* AN_HCD_CL72:2:2 */ 1308 PHYMOD_SYMBOL_FIELD_ENCODE(51, 2, 2), 1309 /* AN_HCD_FEC:3:3 */ 1310 PHYMOD_SYMBOL_FIELD_ENCODE(53, 3, 3), 1311 /* AN_HCD_SPEED:4:11 */ 1312 PHYMOD_SYMBOL_FIELD_ENCODE(56, 11, 4), 1313 /* AN_HCD_PAUSE:12:13 */ 1314 PHYMOD_SYMBOL_FIELD_ENCODE(55, 13, 12), 1315 /* AN_HCD_DUPLEX:14:14 */ 1316 PHYMOD_SYMBOL_FIELD_ENCODE(52, 14, 14), 1317 /* AN_ST_RESOLUTION_ERR:15:15 */ 1318 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(92, 15, 15) 1319 }; 1320 static uint32_t BCMI_QTC_XGXS_AN_X4_SW_SP2_AN_MISC_STSr_fields[] = 1321 { 1322 /* PD_HCD_KX4_OR_KX:0:0 */ 1323 PHYMOD_SYMBOL_FIELD_ENCODE(830, 0, 0), 1324 /* PD_IN_PROGRESS:1:1 */ 1325 PHYMOD_SYMBOL_FIELD_ENCODE(831, 1, 1), 1326 /* AN_FAIL_COUNT:2:5 */ 1327 PHYMOD_SYMBOL_FIELD_ENCODE(47, 5, 2), 1328 /* AN_ACTIVE:6:6 */ 1329 PHYMOD_SYMBOL_FIELD_ENCODE(44, 6, 6), 1330 /* PD_COMPLETED:7:7 */ 1331 PHYMOD_SYMBOL_FIELD_ENCODE(829, 7, 7), 1332 /* REMOTE_FAULT_IN_BASE_PAGE:8:8 */ 1333 PHYMOD_SYMBOL_FIELD_ENCODE(952, 8, 8), 1334 /* AN_RETRY_COUNT:9:14 */ 1335 PHYMOD_SYMBOL_FIELD_ENCODE(63, 14, 9), 1336 /* AN_COMPLETE:15:15 */ 1337 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(45, 15, 15) 1338 }; 1339 static uint32_t BCMI_QTC_XGXS_AN_X4_SW_SP2_AN_PAGE_DECR_STSr_fields[] = 1340 { 1341 /* AN_RX_ST_STATE:0:1 */ 1342 PHYMOD_SYMBOL_FIELD_ENCODE(75, 1, 0), 1343 /* AN_RX_ST_RUDI_INVALID:2:2 */ 1344 PHYMOD_SYMBOL_FIELD_ENCODE(74, 2, 2), 1345 /* AN_RX_ST_RUDI_CONFIG:3:3 */ 1346 PHYMOD_SYMBOL_FIELD_ENCODE(72, 3, 3), 1347 /* AN_RX_ST_RUDI_IDLE:4:4 */ 1348 PHYMOD_SYMBOL_FIELD_ENCODE(73, 4, 4), 1349 /* AN_RX_ST_PAGE:5:5 */ 1350 PHYMOD_SYMBOL_FIELD_ENCODE(66, 5, 5), 1351 /* AN_RX_ST_MV_PAIR:6:6 */ 1352 PHYMOD_SYMBOL_FIELD_ENCODE(65, 6, 6), 1353 /* AN_RX_ST_CLK_TRANS_MISS:7:7 */ 1354 PHYMOD_SYMBOL_FIELD_ENCODE(64, 7, 7), 1355 /* AN_RX_ST_PAGE_TOO_LONG:8:8 */ 1356 PHYMOD_SYMBOL_FIELD_ENCODE(67, 8, 8), 1357 /* AN_RX_ST_PAGE_TOO_SHORT:9:9 */ 1358 PHYMOD_SYMBOL_FIELD_ENCODE(68, 9, 9), 1359 /* AN_RX_ST_PULSE_TOO_LONG:10:10 */ 1360 PHYMOD_SYMBOL_FIELD_ENCODE(69, 10, 10), 1361 /* AN_RX_ST_PULSE_TOO_SHORT:11:11 */ 1362 PHYMOD_SYMBOL_FIELD_ENCODE(71, 11, 11), 1363 /* AN_RX_ST_PULSE_TOO_MODERATE:12:12 */ 1364 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(70, 12, 12) 1365 }; 1366 static uint32_t BCMI_QTC_XGXS_AN_X4_SW_SP2_AN_PAGE_EXCHANGEER_STSr_fields[] = 1367 { 1368 /* AN_ST_CONFIG_RESTART:0:0 */ 1369 PHYMOD_SYMBOL_FIELD_ENCODE(84, 0, 0), 1370 /* AN_ST_IDLE_DETECT:1:1 */ 1371 PHYMOD_SYMBOL_FIELD_ENCODE(89, 1, 1), 1372 /* AN_ST_DISABLE_LINK:2:2 */ 1373 PHYMOD_SYMBOL_FIELD_ENCODE(86, 2, 2), 1374 /* AN_ST_ERROR_STATE:3:3 */ 1375 PHYMOD_SYMBOL_FIELD_ENCODE(87, 3, 3), 1376 /* AN_ST_AN_ENABLE:4:4 */ 1377 PHYMOD_SYMBOL_FIELD_ENCODE(78, 4, 4), 1378 /* AN_ST_ABILITY_DETECT:5:5 */ 1379 PHYMOD_SYMBOL_FIELD_ENCODE(76, 5, 5), 1380 /* AN_ST_ACK_DETECT:6:6 */ 1381 PHYMOD_SYMBOL_FIELD_ENCODE(77, 6, 6), 1382 /* AN_ST_COMPLETE_ACK:7:7 */ 1383 PHYMOD_SYMBOL_FIELD_ENCODE(82, 7, 7), 1384 /* AN_ST_CONSISTENCY_MISMATCH:8:8 */ 1385 PHYMOD_SYMBOL_FIELD_ENCODE(85, 8, 8), 1386 /* AN_ST_CONFIG_NONZERO:9:9 */ 1387 PHYMOD_SYMBOL_FIELD_ENCODE(83, 9, 9), 1388 /* AN_ST_RESTART:10:10 */ 1389 PHYMOD_SYMBOL_FIELD_ENCODE(93, 10, 10), 1390 /* AN_ST_AN_GOOD_CHECK:11:11 */ 1391 PHYMOD_SYMBOL_FIELD_ENCODE(79, 11, 11), 1392 /* AN_ST_LINK_OK:12:12 */ 1393 PHYMOD_SYMBOL_FIELD_ENCODE(90, 12, 12), 1394 /* AN_ST_NEXT_PAGE_WAIT:13:13 */ 1395 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(91, 13, 13) 1396 }; 1397 static uint32_t BCMI_QTC_XGXS_AN_X4_SW_SP2_AN_PAGE_SEQUENCER_STSr_fields[] = 1398 { 1399 /* AN_ST_CL73_COMPLETE:0:0 */ 1400 PHYMOD_SYMBOL_FIELD_ENCODE(81, 0, 0), 1401 /* AN_ST_CL37_COMPLETE:1:1 */ 1402 PHYMOD_SYMBOL_FIELD_ENCODE(80, 1, 1), 1403 /* AN_ST_RX_NP_TOGGLE_ERR:2:2 */ 1404 PHYMOD_SYMBOL_FIELD_ENCODE(101, 2, 2), 1405 /* AN_ST_RX_INVALID_SEQ:3:3 */ 1406 PHYMOD_SYMBOL_FIELD_ENCODE(95, 3, 3), 1407 /* AN_ST_RX_UP_OUI_MATCH:4:4 */ 1408 PHYMOD_SYMBOL_FIELD_ENCODE(104, 4, 4), 1409 /* AN_ST_RX_UP_OUI_MISMATCH:5:5 */ 1410 PHYMOD_SYMBOL_FIELD_ENCODE(105, 5, 5), 1411 /* AN_ST_RX_UP_3:6:6 */ 1412 PHYMOD_SYMBOL_FIELD_ENCODE(103, 6, 6), 1413 /* AN_ST_RX_MP_MISMATCH:7:7 */ 1414 PHYMOD_SYMBOL_FIELD_ENCODE(96, 7, 7), 1415 /* AN_ST_RX_MP_OVER1G:8:8 */ 1416 PHYMOD_SYMBOL_FIELD_ENCODE(99, 8, 8), 1417 /* AN_ST_RX_MP_OUI:9:9 */ 1418 PHYMOD_SYMBOL_FIELD_ENCODE(98, 9, 9), 1419 /* AN_ST_RX_MP_NULL:10:10 */ 1420 PHYMOD_SYMBOL_FIELD_ENCODE(97, 10, 10), 1421 /* AN_ST_RX_NP:11:11 */ 1422 PHYMOD_SYMBOL_FIELD_ENCODE(100, 11, 11), 1423 /* AN_ST_RX_BP:12:12 */ 1424 PHYMOD_SYMBOL_FIELD_ENCODE(94, 12, 12), 1425 /* AN_ST_RX_SGMII_MISMATCH:13:13 */ 1426 PHYMOD_SYMBOL_FIELD_ENCODE(102, 13, 13), 1427 /* AN_ST_HP_MODE:14:14 */ 1428 PHYMOD_SYMBOL_FIELD_ENCODE(88, 14, 14), 1429 /* AN_ST_SGMII_MODE:15:15 */ 1430 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(106, 15, 15) 1431 }; 1432 static uint32_t BCMI_QTC_XGXS_AN_X4_SW_SP2_AN_SEQ_UNEXPECTED_PAGEr_fields[] = 1433 { 1434 /* SEQ_UNEXPECTED_PAGE:0:15 */ 1435 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1049, 15, 0) 1436 }; 1437 static uint32_t BCMI_QTC_XGXS_AN_X4_SW_SP2_LD_CTLr_fields[] = 1438 { 1439 /* SW_HCD:0:0 */ 1440 PHYMOD_SYMBOL_FIELD_ENCODE(1117, 0, 0), 1441 /* SW_AN:1:1 */ 1442 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1116, 1, 1) 1443 }; 1444 static uint32_t BCMI_QTC_XGXS_AN_X4_SW_SP2_LD_PAGE0r_fields[] = 1445 { 1446 /* LD_PAGE_0_PAGE_DATA:0:15 */ 1447 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(566, 15, 0) 1448 }; 1449 static uint32_t BCMI_QTC_XGXS_AN_X4_SW_SP2_LD_PAGE1r_fields[] = 1450 { 1451 /* LD_PAGE_1_PAGE_DATA:0:15 */ 1452 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(567, 15, 0) 1453 }; 1454 static uint32_t BCMI_QTC_XGXS_AN_X4_SW_SP2_LD_PAGE2r_fields[] = 1455 { 1456 /* LD_PAGE_2_PAGE_DATA:0:15 */ 1457 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(568, 15, 0) 1458 }; 1459 static uint32_t BCMI_QTC_XGXS_AN_X4_SW_SP2_LP_PAGE0r_fields[] = 1460 { 1461 /* LP_PAGE_0_PAGE_DATA:0:15 */ 1462 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(656, 15, 0) 1463 }; 1464 static uint32_t BCMI_QTC_XGXS_AN_X4_SW_SP2_LP_PAGE1r_fields[] = 1465 { 1466 /* LP_PAGE_1_PAGE_DATA:0:15 */ 1467 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(657, 15, 0) 1468 }; 1469 static uint32_t BCMI_QTC_XGXS_AN_X4_SW_SP2_LP_PAGE2r_fields[] = 1470 { 1471 /* LP_PAGE_2_PAGE_DATA:0:15 */ 1472 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(658, 15, 0) 1473 }; 1474 static uint32_t BCMI_QTC_XGXS_AN_X4_SW_SP2_SW_CTL_STSr_fields[] = 1475 { 1476 /* TLA_LN_SEQUENCER_FSM_STATUS1:0:7 */ 1477 PHYMOD_SYMBOL_FIELD_ENCODE(1173, 7, 0), 1478 /* PD_CL37_COMPLETED:8:8 */ 1479 PHYMOD_SYMBOL_FIELD_ENCODE(828, 8, 8), 1480 /* LP_STATUS_VALID:13:13 */ 1481 PHYMOD_SYMBOL_FIELD_ENCODE(659, 13, 13), 1482 /* LD_CONTROL_VALID:14:14 */ 1483 PHYMOD_SYMBOL_FIELD_ENCODE(565, 14, 14), 1484 /* AN_COMPLETED_SW:15:15 */ 1485 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(46, 15, 15) 1486 }; 1487 static uint32_t BCMI_QTC_XGXS_AN_X4_SW_SP2_TLA_SEQUENCER_STSr_fields[] = 1488 { 1489 /* TLA_LN_SEQUENCER_FSM_STATUS:0:15 */ 1490 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1172, 15, 0) 1491 }; 1492 static uint32_t BCMI_QTC_XGXS_AN_X4_SW_SP3_AN_ABIL_RESOLUTION_STSr_fields[] = 1493 { 1494 /* AN_HCD_SWITCH_TO_CL37:0:0 */ 1495 PHYMOD_SYMBOL_FIELD_ENCODE(57, 0, 0), 1496 /* AN_HCD_HIGIG2:1:1 */ 1497 PHYMOD_SYMBOL_FIELD_ENCODE(54, 1, 1), 1498 /* AN_HCD_CL72:2:2 */ 1499 PHYMOD_SYMBOL_FIELD_ENCODE(51, 2, 2), 1500 /* AN_HCD_FEC:3:3 */ 1501 PHYMOD_SYMBOL_FIELD_ENCODE(53, 3, 3), 1502 /* AN_HCD_SPEED:4:11 */ 1503 PHYMOD_SYMBOL_FIELD_ENCODE(56, 11, 4), 1504 /* AN_HCD_PAUSE:12:13 */ 1505 PHYMOD_SYMBOL_FIELD_ENCODE(55, 13, 12), 1506 /* AN_HCD_DUPLEX:14:14 */ 1507 PHYMOD_SYMBOL_FIELD_ENCODE(52, 14, 14), 1508 /* AN_ST_RESOLUTION_ERR:15:15 */ 1509 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(92, 15, 15) 1510 }; 1511 static uint32_t BCMI_QTC_XGXS_AN_X4_SW_SP3_AN_MISC_STSr_fields[] = 1512 { 1513 /* PD_HCD_KX4_OR_KX:0:0 */ 1514 PHYMOD_SYMBOL_FIELD_ENCODE(830, 0, 0), 1515 /* PD_IN_PROGRESS:1:1 */ 1516 PHYMOD_SYMBOL_FIELD_ENCODE(831, 1, 1), 1517 /* AN_FAIL_COUNT:2:5 */ 1518 PHYMOD_SYMBOL_FIELD_ENCODE(47, 5, 2), 1519 /* AN_ACTIVE:6:6 */ 1520 PHYMOD_SYMBOL_FIELD_ENCODE(44, 6, 6), 1521 /* PD_COMPLETED:7:7 */ 1522 PHYMOD_SYMBOL_FIELD_ENCODE(829, 7, 7), 1523 /* REMOTE_FAULT_IN_BASE_PAGE:8:8 */ 1524 PHYMOD_SYMBOL_FIELD_ENCODE(952, 8, 8), 1525 /* AN_RETRY_COUNT:9:14 */ 1526 PHYMOD_SYMBOL_FIELD_ENCODE(63, 14, 9), 1527 /* AN_COMPLETE:15:15 */ 1528 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(45, 15, 15) 1529 }; 1530 static uint32_t BCMI_QTC_XGXS_AN_X4_SW_SP3_AN_PAGE_DECR_STSr_fields[] = 1531 { 1532 /* AN_RX_ST_STATE:0:1 */ 1533 PHYMOD_SYMBOL_FIELD_ENCODE(75, 1, 0), 1534 /* AN_RX_ST_RUDI_INVALID:2:2 */ 1535 PHYMOD_SYMBOL_FIELD_ENCODE(74, 2, 2), 1536 /* AN_RX_ST_RUDI_CONFIG:3:3 */ 1537 PHYMOD_SYMBOL_FIELD_ENCODE(72, 3, 3), 1538 /* AN_RX_ST_RUDI_IDLE:4:4 */ 1539 PHYMOD_SYMBOL_FIELD_ENCODE(73, 4, 4), 1540 /* AN_RX_ST_PAGE:5:5 */ 1541 PHYMOD_SYMBOL_FIELD_ENCODE(66, 5, 5), 1542 /* AN_RX_ST_MV_PAIR:6:6 */ 1543 PHYMOD_SYMBOL_FIELD_ENCODE(65, 6, 6), 1544 /* AN_RX_ST_CLK_TRANS_MISS:7:7 */ 1545 PHYMOD_SYMBOL_FIELD_ENCODE(64, 7, 7), 1546 /* AN_RX_ST_PAGE_TOO_LONG:8:8 */ 1547 PHYMOD_SYMBOL_FIELD_ENCODE(67, 8, 8), 1548 /* AN_RX_ST_PAGE_TOO_SHORT:9:9 */ 1549 PHYMOD_SYMBOL_FIELD_ENCODE(68, 9, 9), 1550 /* AN_RX_ST_PULSE_TOO_LONG:10:10 */ 1551 PHYMOD_SYMBOL_FIELD_ENCODE(69, 10, 10), 1552 /* AN_RX_ST_PULSE_TOO_SHORT:11:11 */ 1553 PHYMOD_SYMBOL_FIELD_ENCODE(71, 11, 11), 1554 /* AN_RX_ST_PULSE_TOO_MODERATE:12:12 */ 1555 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(70, 12, 12) 1556 }; 1557 static uint32_t BCMI_QTC_XGXS_AN_X4_SW_SP3_AN_PAGE_EXCHANGEER_STSr_fields[] = 1558 { 1559 /* AN_ST_CONFIG_RESTART:0:0 */ 1560 PHYMOD_SYMBOL_FIELD_ENCODE(84, 0, 0), 1561 /* AN_ST_IDLE_DETECT:1:1 */ 1562 PHYMOD_SYMBOL_FIELD_ENCODE(89, 1, 1), 1563 /* AN_ST_DISABLE_LINK:2:2 */ 1564 PHYMOD_SYMBOL_FIELD_ENCODE(86, 2, 2), 1565 /* AN_ST_ERROR_STATE:3:3 */ 1566 PHYMOD_SYMBOL_FIELD_ENCODE(87, 3, 3), 1567 /* AN_ST_AN_ENABLE:4:4 */ 1568 PHYMOD_SYMBOL_FIELD_ENCODE(78, 4, 4), 1569 /* AN_ST_ABILITY_DETECT:5:5 */ 1570 PHYMOD_SYMBOL_FIELD_ENCODE(76, 5, 5), 1571 /* AN_ST_ACK_DETECT:6:6 */ 1572 PHYMOD_SYMBOL_FIELD_ENCODE(77, 6, 6), 1573 /* AN_ST_COMPLETE_ACK:7:7 */ 1574 PHYMOD_SYMBOL_FIELD_ENCODE(82, 7, 7), 1575 /* AN_ST_CONSISTENCY_MISMATCH:8:8 */ 1576 PHYMOD_SYMBOL_FIELD_ENCODE(85, 8, 8), 1577 /* AN_ST_CONFIG_NONZERO:9:9 */ 1578 PHYMOD_SYMBOL_FIELD_ENCODE(83, 9, 9), 1579 /* AN_ST_RESTART:10:10 */ 1580 PHYMOD_SYMBOL_FIELD_ENCODE(93, 10, 10), 1581 /* AN_ST_AN_GOOD_CHECK:11:11 */ 1582 PHYMOD_SYMBOL_FIELD_ENCODE(79, 11, 11), 1583 /* AN_ST_LINK_OK:12:12 */ 1584 PHYMOD_SYMBOL_FIELD_ENCODE(90, 12, 12), 1585 /* AN_ST_NEXT_PAGE_WAIT:13:13 */ 1586 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(91, 13, 13) 1587 }; 1588 static uint32_t BCMI_QTC_XGXS_AN_X4_SW_SP3_AN_PAGE_SEQUENCER_STSr_fields[] = 1589 { 1590 /* AN_ST_CL73_COMPLETE:0:0 */ 1591 PHYMOD_SYMBOL_FIELD_ENCODE(81, 0, 0), 1592 /* AN_ST_CL37_COMPLETE:1:1 */ 1593 PHYMOD_SYMBOL_FIELD_ENCODE(80, 1, 1), 1594 /* AN_ST_RX_NP_TOGGLE_ERR:2:2 */ 1595 PHYMOD_SYMBOL_FIELD_ENCODE(101, 2, 2), 1596 /* AN_ST_RX_INVALID_SEQ:3:3 */ 1597 PHYMOD_SYMBOL_FIELD_ENCODE(95, 3, 3), 1598 /* AN_ST_RX_UP_OUI_MATCH:4:4 */ 1599 PHYMOD_SYMBOL_FIELD_ENCODE(104, 4, 4), 1600 /* AN_ST_RX_UP_OUI_MISMATCH:5:5 */ 1601 PHYMOD_SYMBOL_FIELD_ENCODE(105, 5, 5), 1602 /* AN_ST_RX_UP_3:6:6 */ 1603 PHYMOD_SYMBOL_FIELD_ENCODE(103, 6, 6), 1604 /* AN_ST_RX_MP_MISMATCH:7:7 */ 1605 PHYMOD_SYMBOL_FIELD_ENCODE(96, 7, 7), 1606 /* AN_ST_RX_MP_OVER1G:8:8 */ 1607 PHYMOD_SYMBOL_FIELD_ENCODE(99, 8, 8), 1608 /* AN_ST_RX_MP_OUI:9:9 */ 1609 PHYMOD_SYMBOL_FIELD_ENCODE(98, 9, 9), 1610 /* AN_ST_RX_MP_NULL:10:10 */ 1611 PHYMOD_SYMBOL_FIELD_ENCODE(97, 10, 10), 1612 /* AN_ST_RX_NP:11:11 */ 1613 PHYMOD_SYMBOL_FIELD_ENCODE(100, 11, 11), 1614 /* AN_ST_RX_BP:12:12 */ 1615 PHYMOD_SYMBOL_FIELD_ENCODE(94, 12, 12), 1616 /* AN_ST_RX_SGMII_MISMATCH:13:13 */ 1617 PHYMOD_SYMBOL_FIELD_ENCODE(102, 13, 13), 1618 /* AN_ST_HP_MODE:14:14 */ 1619 PHYMOD_SYMBOL_FIELD_ENCODE(88, 14, 14), 1620 /* AN_ST_SGMII_MODE:15:15 */ 1621 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(106, 15, 15) 1622 }; 1623 static uint32_t BCMI_QTC_XGXS_AN_X4_SW_SP3_AN_SEQ_UNEXPECTED_PAGEr_fields[] = 1624 { 1625 /* SEQ_UNEXPECTED_PAGE:0:15 */ 1626 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1049, 15, 0) 1627 }; 1628 static uint32_t BCMI_QTC_XGXS_AN_X4_SW_SP3_LD_CTLr_fields[] = 1629 { 1630 /* SW_HCD:0:0 */ 1631 PHYMOD_SYMBOL_FIELD_ENCODE(1117, 0, 0), 1632 /* SW_AN:1:1 */ 1633 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1116, 1, 1) 1634 }; 1635 static uint32_t BCMI_QTC_XGXS_AN_X4_SW_SP3_LD_PAGE0r_fields[] = 1636 { 1637 /* LD_PAGE_0_PAGE_DATA:0:15 */ 1638 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(566, 15, 0) 1639 }; 1640 static uint32_t BCMI_QTC_XGXS_AN_X4_SW_SP3_LD_PAGE1r_fields[] = 1641 { 1642 /* LD_PAGE_1_PAGE_DATA:0:15 */ 1643 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(567, 15, 0) 1644 }; 1645 static uint32_t BCMI_QTC_XGXS_AN_X4_SW_SP3_LD_PAGE2r_fields[] = 1646 { 1647 /* LD_PAGE_2_PAGE_DATA:0:15 */ 1648 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(568, 15, 0) 1649 }; 1650 static uint32_t BCMI_QTC_XGXS_AN_X4_SW_SP3_LP_PAGE0r_fields[] = 1651 { 1652 /* LP_PAGE_0_PAGE_DATA:0:15 */ 1653 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(656, 15, 0) 1654 }; 1655 static uint32_t BCMI_QTC_XGXS_AN_X4_SW_SP3_LP_PAGE1r_fields[] = 1656 { 1657 /* LP_PAGE_1_PAGE_DATA:0:15 */ 1658 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(657, 15, 0) 1659 }; 1660 static uint32_t BCMI_QTC_XGXS_AN_X4_SW_SP3_LP_PAGE2r_fields[] = 1661 { 1662 /* LP_PAGE_2_PAGE_DATA:0:15 */ 1663 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(658, 15, 0) 1664 }; 1665 static uint32_t BCMI_QTC_XGXS_AN_X4_SW_SP3_SW_CTL_STSr_fields[] = 1666 { 1667 /* TLA_LN_SEQUENCER_FSM_STATUS1:0:7 */ 1668 PHYMOD_SYMBOL_FIELD_ENCODE(1173, 7, 0), 1669 /* PD_CL37_COMPLETED:8:8 */ 1670 PHYMOD_SYMBOL_FIELD_ENCODE(828, 8, 8), 1671 /* LP_STATUS_VALID:13:13 */ 1672 PHYMOD_SYMBOL_FIELD_ENCODE(659, 13, 13), 1673 /* LD_CONTROL_VALID:14:14 */ 1674 PHYMOD_SYMBOL_FIELD_ENCODE(565, 14, 14), 1675 /* AN_COMPLETED_SW:15:15 */ 1676 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(46, 15, 15) 1677 }; 1678 static uint32_t BCMI_QTC_XGXS_AN_X4_SW_SP3_TLA_SEQUENCER_STSr_fields[] = 1679 { 1680 /* TLA_LN_SEQUENCER_FSM_STATUS:0:15 */ 1681 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1172, 15, 0) 1682 }; 1683 static uint32_t BCMI_QTC_XGXS_BAM_SPD_PRI_5_0r_fields[] = 1684 { 1685 /* AN_PRIORITY_1000M:0:1 */ 1686 PHYMOD_SYMBOL_FIELD_ENCODE(58, 1, 0), 1687 /* AN_PRIORITY_100M:2:3 */ 1688 PHYMOD_SYMBOL_FIELD_ENCODE(59, 3, 2), 1689 /* AN_PRIORITY_10M:4:5 */ 1690 PHYMOD_SYMBOL_FIELD_ENCODE(60, 5, 4), 1691 /* AN_PRIORITY_2P5GX1:8:9 */ 1692 PHYMOD_SYMBOL_FIELD_ENCODE(62, 9, 8), 1693 /* AN_PRIORITY_1GKX:10:11 */ 1694 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(61, 11, 10) 1695 }; 1696 static uint32_t BCMI_QTC_XGXS_BARREL_SHIFTER_STr_fields[] = 1697 { 1698 /* SHIFT_AMMOUNT:0:7 */ 1699 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1058, 7, 0) 1700 }; 1701 static uint32_t BCMI_QTC_XGXS_BERCNT0r_fields[] = 1702 { 1703 /* BER_COUNT_SP0:0:7 */ 1704 PHYMOD_SYMBOL_FIELD_ENCODE(117, 7, 0), 1705 /* BER_COUNT_SP1:8:15 */ 1706 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(118, 15, 8) 1707 }; 1708 static uint32_t BCMI_QTC_XGXS_BERCNT1r_fields[] = 1709 { 1710 /* BER_COUNT_SP2:0:7 */ 1711 PHYMOD_SYMBOL_FIELD_ENCODE(119, 7, 0), 1712 /* BER_COUNT_SP3:8:15 */ 1713 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(120, 15, 8) 1714 }; 1715 static uint32_t BCMI_QTC_XGXS_BLK_ADDRr_fields[] = 1716 { 1717 /* MDIO_BLK_ADDR:4:14 */ 1718 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(675, 14, 4) 1719 }; 1720 static uint32_t BCMI_QTC_XGXS_CL36TX_CTLr_fields[] = 1721 { 1722 /* CL36TX_LPI_EN:1:1 */ 1723 PHYMOD_SYMBOL_FIELD_ENCODE(171, 1, 1), 1724 /* CL36TX_CATCH_ALL_8B10B_DIS:2:2 */ 1725 PHYMOD_SYMBOL_FIELD_ENCODE(170, 2, 2), 1726 /* QSGMII_EN:3:3 */ 1727 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(929, 3, 3) 1728 }; 1729 static uint32_t BCMI_QTC_XGXS_CL36_FSM_STSr_fields[] = 1730 { 1731 /* CL36_TXSM_STATE:0:3 */ 1732 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(180, 3, 0) 1733 }; 1734 static uint32_t BCMI_QTC_XGXS_CL36_RXr_fields[] = 1735 { 1736 /* QSGMII_EN:0:0 */ 1737 PHYMOD_SYMBOL_FIELD_ENCODE(929, 0, 0), 1738 /* DISABLE_CARRIER_EXTEND:1:1 */ 1739 PHYMOD_SYMBOL_FIELD_ENCODE(417, 1, 1), 1740 /* CL36_FORCE_COMMA_ALIGN_ENABLE:2:2 */ 1741 PHYMOD_SYMBOL_FIELD_ENCODE(173, 2, 2), 1742 /* CL36_BER_EN:3:3 */ 1743 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(172, 3, 3) 1744 }; 1745 static uint32_t BCMI_QTC_XGXS_CL36_RXSM_BINARY_STSr_fields[] = 1746 { 1747 /* CL36_RXSM_STATE_SPN:0:4 */ 1748 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(177, 4, 0) 1749 }; 1750 static uint32_t BCMI_QTC_XGXS_CL36_RXSM_ONEHOT_STS0r_fields[] = 1751 { 1752 /* CL36_RXSM_ONEHOT_LATCHED_LO_STATUS:0:15 */ 1753 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(176, 15, 0) 1754 }; 1755 static uint32_t BCMI_QTC_XGXS_CL36_RXSM_ONEHOT_STS1r_fields[] = 1756 { 1757 /* CL36_RXSM_ONEHOT_LATCHED_HI_STATUS:0:3 */ 1758 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(175, 3, 0) 1759 }; 1760 static uint32_t BCMI_QTC_XGXS_CL37_ACKr_fields[] = 1761 { 1762 /* CL37_ACK_TIMER_PERIOD:0:15 */ 1763 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(182, 15, 0) 1764 }; 1765 static uint32_t BCMI_QTC_XGXS_CL37_ERRr_fields[] = 1766 { 1767 /* CL37_ERROR_TIMER_PERIOD:0:15 */ 1768 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(190, 15, 0) 1769 }; 1770 static uint32_t BCMI_QTC_XGXS_CL37_RESTARTr_fields[] = 1771 { 1772 /* CL37_RESTART_TIMER_PERIOD:0:15 */ 1773 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(195, 15, 0) 1774 }; 1775 static uint32_t BCMI_QTC_XGXS_CL37_SYNC_STS_FILTER_TMRr_fields[] = 1776 { 1777 /* CL37_SYNC_STATUS_FILTER_TIMER_PERIOD:0:15 */ 1778 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(198, 15, 0) 1779 }; 1780 static uint32_t BCMI_QTC_XGXS_CL72_RXCL72IR_BASE_R_LP_COEFF_UPDr_fields[] = 1781 { 1782 /* CL72_IEEE_LP_COEFF_UPDATE:0:15 */ 1783 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(248, 15, 0) 1784 }; 1785 static uint32_t BCMI_QTC_XGXS_CL72_RXCL72IR_BASE_R_LP_STS_REPr_fields[] = 1786 { 1787 /* CL72_IEEE_LP_STATUS_REPORT:0:15 */ 1788 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(249, 15, 0) 1789 }; 1790 static uint32_t BCMI_QTC_XGXS_CL72_RXCL72UR_CTL0r_fields[] = 1791 { 1792 /* CL72_RX_TRAINING_EN:0:0 */ 1793 PHYMOD_SYMBOL_FIELD_ENCODE(274, 0, 0), 1794 /* CL72_TR_COARSE_LOCK:1:1 */ 1795 PHYMOD_SYMBOL_FIELD_ENCODE(282, 1, 1), 1796 /* CL72_RX_SIGNAL_OK:2:2 */ 1797 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(273, 2, 2) 1798 }; 1799 static uint32_t BCMI_QTC_XGXS_CL72_RXCL72UR_CTL1r_fields[] = 1800 { 1801 /* CL72_GOOD_MARKER_CNT:0:1 */ 1802 PHYMOD_SYMBOL_FIELD_ENCODE(244, 1, 0), 1803 /* CL72_BAD_MARKER_CNT:4:6 */ 1804 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(236, 6, 4) 1805 }; 1806 static uint32_t BCMI_QTC_XGXS_CL72_RXCL72UR_CTL2r_fields[] = 1807 { 1808 /* CL72_CTRL_FRAME_DLY:0:3 */ 1809 PHYMOD_SYMBOL_FIELD_ENCODE(239, 3, 0), 1810 /* CL72_DME_CELL_BOUNDARY_CHK:4:4 */ 1811 PHYMOD_SYMBOL_FIELD_ENCODE(241, 4, 4), 1812 /* CL72_STRICT_DME_CHK:5:5 */ 1813 PHYMOD_SYMBOL_FIELD_ENCODE(275, 5, 5), 1814 /* CL72_STRICT_MARKER_CHK:6:6 */ 1815 PHYMOD_SYMBOL_FIELD_ENCODE(276, 6, 6), 1816 /* CL72_PPM_OFFSET_EN:7:7 */ 1817 PHYMOD_SYMBOL_FIELD_ENCODE(267, 7, 7), 1818 /* CL72_RX_DP_LN_CLK_EN:8:8 */ 1819 PHYMOD_SYMBOL_FIELD_ENCODE(272, 8, 8), 1820 /* CL72_FRAME_CONSISTENCY_CHK_EN:9:9 */ 1821 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(242, 9, 9) 1822 }; 1823 static uint32_t BCMI_QTC_XGXS_CL72_RXCL72UR_STS0r_fields[] = 1824 { 1825 /* CL72_FRAME_LOCK:0:0 */ 1826 PHYMOD_SYMBOL_FIELD_ENCODE(243, 0, 0), 1827 /* CL72_REMOTE_RX_READY:1:1 */ 1828 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(271, 1, 1) 1829 }; 1830 static uint32_t BCMI_QTC_XGXS_CL72_RXCL72UR_UC_INTR_CTL0r_fields[] = 1831 { 1832 /* CL72_MICRO_UPDATE_CHG_INT_EN:0:0 */ 1833 PHYMOD_SYMBOL_FIELD_ENCODE(263, 0, 0), 1834 /* CL72_MICRO_STATUS_CHG_INT_EN:1:1 */ 1835 PHYMOD_SYMBOL_FIELD_ENCODE(259, 1, 1), 1836 /* CL72_MICRO_FRAME_LOCK_INT_EN:2:2 */ 1837 PHYMOD_SYMBOL_FIELD_ENCODE(257, 2, 2), 1838 /* CL72_MICRO_UPDATE_REQ_INT_FRC:8:8 */ 1839 PHYMOD_SYMBOL_FIELD_ENCODE(265, 8, 8), 1840 /* CL72_MICRO_UPDATE_REQ_INT_FRC_VAL:9:9 */ 1841 PHYMOD_SYMBOL_FIELD_ENCODE(266, 9, 9), 1842 /* CL72_MICRO_STATUS_RESP_INT_FRC:10:10 */ 1843 PHYMOD_SYMBOL_FIELD_ENCODE(261, 10, 10), 1844 /* CL72_MICRO_STATUS_RESP_INT_FRC_VAL:11:11 */ 1845 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(262, 11, 11) 1846 }; 1847 static uint32_t BCMI_QTC_XGXS_CL72_RXCL72UR_UC_STS0r_fields[] = 1848 { 1849 /* CL72_MICRO_UPDATE_CHG_LSTATUS:0:0 */ 1850 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(264, 0, 0) 1851 }; 1852 static uint32_t BCMI_QTC_XGXS_CL72_RXCL72UR_UC_STS1r_fields[] = 1853 { 1854 /* CL72_MICRO_STATUS_CHG_LSTATUS:0:0 */ 1855 PHYMOD_SYMBOL_FIELD_ENCODE(260, 0, 0), 1856 /* CL72_MICRO_FRAME_LOCK_LSTATUS:1:1 */ 1857 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(258, 1, 1) 1858 }; 1859 static uint32_t BCMI_QTC_XGXS_CL72_TXCL72IT_BASE_R_LD_COEFF_UPDr_fields[] = 1860 { 1861 /* CL72_IEEE_LD_COEFF_UPDATE:0:15 */ 1862 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(246, 15, 0) 1863 }; 1864 static uint32_t BCMI_QTC_XGXS_CL72_TXCL72IT_BASE_R_LD_STS_REPr_fields[] = 1865 { 1866 /* CL72_IEEE_LD_STATUS_REPORT:0:15 */ 1867 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(247, 15, 0) 1868 }; 1869 static uint32_t BCMI_QTC_XGXS_CL72_TXCL72IT_BASE_R_PMD_CTLr_fields[] = 1870 { 1871 /* CL72_IEEE_RESTART_TRAINING:0:0 */ 1872 PHYMOD_SYMBOL_FIELD_ENCODE(251, 0, 0), 1873 /* CL72_IEEE_TRAINING_ENABLE:1:1 */ 1874 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(252, 1, 1) 1875 }; 1876 static uint32_t BCMI_QTC_XGXS_CL72_TXCL72IT_BASE_R_PMD_STSr_fields[] = 1877 { 1878 /* CL72_IEEE_RECEIVER_STATUS:0:0 */ 1879 PHYMOD_SYMBOL_FIELD_ENCODE(250, 0, 0), 1880 /* CL72_IEEE_FRAME_LOCK:1:1 */ 1881 PHYMOD_SYMBOL_FIELD_ENCODE(245, 1, 1), 1882 /* CL72_IEEE_TRAINING_STATUS:2:2 */ 1883 PHYMOD_SYMBOL_FIELD_ENCODE(254, 2, 2), 1884 /* CL72_IEEE_TRAINING_FAILURE:3:3 */ 1885 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(253, 3, 3) 1886 }; 1887 static uint32_t BCMI_QTC_XGXS_CL72_TXCL72UT_CTL0r_fields[] = 1888 { 1889 /* CL72_SW_RX_TRAINED:0:0 */ 1890 PHYMOD_SYMBOL_FIELD_ENCODE(279, 0, 0), 1891 /* CL72_SW_FRAME_LOCK:1:1 */ 1892 PHYMOD_SYMBOL_FIELD_ENCODE(277, 1, 1), 1893 /* CL72_SW_REMOTE_RX_READY:2:2 */ 1894 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(278, 2, 2) 1895 }; 1896 static uint32_t BCMI_QTC_XGXS_CL72_TXCL72UT_CTL1r_fields[] = 1897 { 1898 /* CL72_BRK_RING_OSC:0:0 */ 1899 PHYMOD_SYMBOL_FIELD_ENCODE(237, 0, 0), 1900 /* CL72_DIS_MAX_WAIT_TIMER:1:1 */ 1901 PHYMOD_SYMBOL_FIELD_ENCODE(240, 1, 1), 1902 /* CL72_TX_DP_LN_CLK_EN:2:2 */ 1903 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(286, 2, 2) 1904 }; 1905 static uint32_t BCMI_QTC_XGXS_CL72_TXCL72UT_CTL2r_fields[] = 1906 { 1907 /* CL72_TXFIR_PRE:0:3 */ 1908 PHYMOD_SYMBOL_FIELD_ENCODE(285, 3, 0), 1909 /* CL72_TXFIR_POST:8:12 */ 1910 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(284, 12, 8) 1911 }; 1912 static uint32_t BCMI_QTC_XGXS_CL72_TXCL72UT_CTL3r_fields[] = 1913 { 1914 /* CL72_TXFIR_MAIN:0:5 */ 1915 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(283, 5, 0) 1916 }; 1917 static uint32_t BCMI_QTC_XGXS_CL72_TXCL72UT_CTL4r_fields[] = 1918 { 1919 /* CL72_PRBS_SEED_VAL:0:10 */ 1920 PHYMOD_SYMBOL_FIELD_ENCODE(270, 10, 0), 1921 /* CL72_CL93PRBS_POLY_SEL:11:12 */ 1922 PHYMOD_SYMBOL_FIELD_ENCODE(238, 12, 11), 1923 /* CL72_PRBS_MODE_SEL:13:13 */ 1924 PHYMOD_SYMBOL_FIELD_ENCODE(268, 13, 13), 1925 /* CL72_PRBS_SEED_SEL:14:15 */ 1926 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(269, 15, 14) 1927 }; 1928 static uint32_t BCMI_QTC_XGXS_CL72_TXCL72UT_LD_XMT_STS_PAGEr_fields[] = 1929 { 1930 /* CL72_LD_XMT_STATUS_PAGE:0:15 */ 1931 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(255, 15, 0) 1932 }; 1933 static uint32_t BCMI_QTC_XGXS_CL72_TXCL72UT_STS0r_fields[] = 1934 { 1935 /* CL72_LOCAL_RX_READY:0:0 */ 1936 PHYMOD_SYMBOL_FIELD_ENCODE(256, 0, 0), 1937 /* CL72_TRAINING_FSM_SIGNAL_DETECT:1:1 */ 1938 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(281, 1, 1) 1939 }; 1940 static uint32_t BCMI_QTC_XGXS_CL72_TXCL72UT_XMT_UPD_PAGEr_fields[] = 1941 { 1942 /* CL72_XMT_UPDATE_PAGE:0:15 */ 1943 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(287, 15, 0) 1944 }; 1945 static uint32_t BCMI_QTC_XGXS_CORE_DP_RST_ST_STSr_fields[] = 1946 { 1947 /* CORE_DP_RESET_STATE:0:2 */ 1948 PHYMOD_SYMBOL_FIELD_ENCODE(311, 2, 0), 1949 /* TX_LANE_RESET_RELEASED_INDEX:3:7 */ 1950 PHYMOD_SYMBOL_FIELD_ENCODE(1279, 7, 3), 1951 /* LANE_RESET_RELEASED_INDEX:8:12 */ 1952 PHYMOD_SYMBOL_FIELD_ENCODE(562, 12, 8), 1953 /* LANE_RESET_RELEASED:14:14 */ 1954 PHYMOD_SYMBOL_FIELD_ENCODE(561, 14, 14), 1955 /* TX_LANE_RESET_RELEASED:15:15 */ 1956 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1278, 15, 15) 1957 }; 1958 static uint32_t BCMI_QTC_XGXS_CORE_RST_OCC_CTLr_fields[] = 1959 { 1960 /* CORE_REG_RESET_OCCURRED:0:0 */ 1961 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(315, 0, 0) 1962 }; 1963 static uint32_t BCMI_QTC_XGXS_CRCERRCNTr_fields[] = 1964 { 1965 /* CRCERRCNT:0:15 */ 1966 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(320, 15, 0) 1967 }; 1968 static uint32_t BCMI_QTC_XGXS_DSC_CDR_CTL0r_fields[] = 1969 { 1970 /* CDR_PHASE_SAT_CTRL:0:0 */ 1971 PHYMOD_SYMBOL_FIELD_ENCODE(164, 0, 0), 1972 /* BR_PD_EN:1:1 */ 1973 PHYMOD_SYMBOL_FIELD_ENCODE(130, 1, 1), 1974 /* CDR_FREQ_EN:2:2 */ 1975 PHYMOD_SYMBOL_FIELD_ENCODE(152, 2, 2), 1976 /* CDR_INTEG_REG_CLR:4:4 */ 1977 PHYMOD_SYMBOL_FIELD_ENCODE(158, 4, 4), 1978 /* CDR_PHASE_ERR_FRZ:5:5 */ 1979 PHYMOD_SYMBOL_FIELD_ENCODE(163, 5, 5), 1980 /* CDR_INTEG_SAT_SEL:6:6 */ 1981 PHYMOD_SYMBOL_FIELD_ENCODE(159, 6, 6), 1982 /* CDR_FREQ_OVERRIDE_EN:7:7 */ 1983 PHYMOD_SYMBOL_FIELD_ENCODE(153, 7, 7), 1984 /* CDR_LM_THR_SEL:8:10 */ 1985 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(161, 10, 8) 1986 }; 1987 static uint32_t BCMI_QTC_XGXS_DSC_CDR_CTL1r_fields[] = 1988 { 1989 /* DFE_VGA_UNFREEZE:0:0 */ 1990 PHYMOD_SYMBOL_FIELD_ENCODE(409, 0, 0), 1991 /* CDR_FREQ_OVERRIDE_VAL:1:15 */ 1992 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(154, 15, 1) 1993 }; 1994 static uint32_t BCMI_QTC_XGXS_DSC_CDR_CTL2r_fields[] = 1995 { 1996 /* CDR_ZERO_POLARITY:0:0 */ 1997 PHYMOD_SYMBOL_FIELD_ENCODE(167, 0, 0), 1998 /* PHASE_ERR_OFFSET_MULT_2:1:1 */ 1999 PHYMOD_SYMBOL_FIELD_ENCODE(840, 1, 1), 2000 /* PATTERN_SEL:4:7 */ 2001 PHYMOD_SYMBOL_FIELD_ENCODE(800, 7, 4), 2002 /* OSX2P_PHERR_GAIN:8:9 */ 2003 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(780, 9, 8) 2004 }; 2005 static uint32_t BCMI_QTC_XGXS_DSC_CDR_STS_INTEGr_fields[] = 2006 { 2007 /* CDR_INTEG_REG:0:15 */ 2008 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(157, 15, 0) 2009 }; 2010 static uint32_t BCMI_QTC_XGXS_DSC_CDR_STS_PHASE_ERRr_fields[] = 2011 { 2012 /* CDR_PHASE_ERR:0:4 */ 2013 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(162, 4, 0) 2014 }; 2015 static uint32_t BCMI_QTC_XGXS_DSC_DC_SLCR_OFFS_CTLr_fields[] = 2016 { 2017 /* DC_OFFSET_EN:0:0 */ 2018 PHYMOD_SYMBOL_FIELD_ENCODE(344, 0, 0), 2019 /* HW_DC_OFFSET_HYS_EN:1:1 */ 2020 PHYMOD_SYMBOL_FIELD_ENCODE(525, 1, 1), 2021 /* HW_DC_OFFSET_ERR_GAIN:2:3 */ 2022 PHYMOD_SYMBOL_FIELD_ENCODE(523, 3, 2), 2023 /* DC_OFFSET_INV:4:4 */ 2024 PHYMOD_SYMBOL_FIELD_ENCODE(345, 4, 4), 2025 /* DC_OFFSET_PATTERN_INV_EN:5:5 */ 2026 PHYMOD_SYMBOL_FIELD_ENCODE(348, 5, 5), 2027 /* HW_DC_OFFSET_GRAD_INV:6:6 */ 2028 PHYMOD_SYMBOL_FIELD_ENCODE(524, 6, 6), 2029 /* DC_OFFSET_PATTERN:8:11 */ 2030 PHYMOD_SYMBOL_FIELD_ENCODE(346, 11, 8), 2031 /* DC_OFFSET_PATTERN_BIT_EN:12:15 */ 2032 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(347, 15, 12) 2033 }; 2034 static uint32_t BCMI_QTC_XGXS_DSC_DFE_1_CTLr_fields[] = 2035 { 2036 /* DFE_1_ACC_CLR:0:0 */ 2037 PHYMOD_SYMBOL_FIELD_ENCODE(351, 0, 0), 2038 /* DFE_1_CMN_ONLY:1:1 */ 2039 PHYMOD_SYMBOL_FIELD_ENCODE(353, 1, 1), 2040 /* DFE_1_INV_P1:8:8 */ 2041 PHYMOD_SYMBOL_FIELD_ENCODE(360, 8, 8), 2042 /* DFE_1_INV_M1:9:9 */ 2043 PHYMOD_SYMBOL_FIELD_ENCODE(359, 9, 9), 2044 /* DFE_1_ERR_GAIN:10:11 */ 2045 PHYMOD_SYMBOL_FIELD_ENCODE(356, 11, 10), 2046 /* DFE_1_GRADIENT_INVERT:12:12 */ 2047 PHYMOD_SYMBOL_FIELD_ENCODE(358, 12, 12), 2048 /* DFE_1_ERR_SEL:13:14 */ 2049 PHYMOD_SYMBOL_FIELD_ENCODE(357, 14, 13), 2050 /* DFE_1_EN:15:15 */ 2051 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(355, 15, 15) 2052 }; 2053 static uint32_t BCMI_QTC_XGXS_DSC_DFE_1_STSr_fields[] = 2054 { 2055 /* DFE_1_CMN:0:5 */ 2056 PHYMOD_SYMBOL_FIELD_ENCODE(352, 5, 0), 2057 /* DFE_1_O:8:10 */ 2058 PHYMOD_SYMBOL_FIELD_ENCODE(361, 10, 8), 2059 /* DFE_1_E:11:13 */ 2060 PHYMOD_SYMBOL_FIELD_ENCODE(354, 13, 11), 2061 /* DFE_1_WANTS_NEGATIVE:15:15 */ 2062 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(362, 15, 15) 2063 }; 2064 static uint32_t BCMI_QTC_XGXS_DSC_DFE_2_CTLr_fields[] = 2065 { 2066 /* DFE_2_ACC_CLR:0:0 */ 2067 PHYMOD_SYMBOL_FIELD_ENCODE(363, 0, 0), 2068 /* DFE_2_CMN_ONLY:1:1 */ 2069 PHYMOD_SYMBOL_FIELD_ENCODE(365, 1, 1), 2070 /* DFE_2_INV_P1:8:8 */ 2071 PHYMOD_SYMBOL_FIELD_ENCODE(372, 8, 8), 2072 /* DFE_2_INV_M1:9:9 */ 2073 PHYMOD_SYMBOL_FIELD_ENCODE(371, 9, 9), 2074 /* DFE_2_ERR_GAIN:10:11 */ 2075 PHYMOD_SYMBOL_FIELD_ENCODE(368, 11, 10), 2076 /* DFE_2_GRADIENT_INVERT:12:12 */ 2077 PHYMOD_SYMBOL_FIELD_ENCODE(370, 12, 12), 2078 /* DFE_2_ERR_SEL:13:14 */ 2079 PHYMOD_SYMBOL_FIELD_ENCODE(369, 14, 13), 2080 /* DFE_2_EN:15:15 */ 2081 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(367, 15, 15) 2082 }; 2083 static uint32_t BCMI_QTC_XGXS_DSC_DFE_2_STSr_fields[] = 2084 { 2085 /* DFE_2_CMN:0:4 */ 2086 PHYMOD_SYMBOL_FIELD_ENCODE(364, 4, 0), 2087 /* DFE_2_SO:5:5 */ 2088 PHYMOD_SYMBOL_FIELD_ENCODE(375, 5, 5), 2089 /* DFE_2_SE:6:6 */ 2090 PHYMOD_SYMBOL_FIELD_ENCODE(374, 6, 6), 2091 /* DFE_2_O:8:10 */ 2092 PHYMOD_SYMBOL_FIELD_ENCODE(373, 10, 8), 2093 /* DFE_2_E:11:13 */ 2094 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(366, 13, 11) 2095 }; 2096 static uint32_t BCMI_QTC_XGXS_DSC_DFE_3_4_5_STSr_fields[] = 2097 { 2098 /* DFE_3_CMN:0:5 */ 2099 PHYMOD_SYMBOL_FIELD_ENCODE(377, 5, 0), 2100 /* DFE_4_CMN:6:10 */ 2101 PHYMOD_SYMBOL_FIELD_ENCODE(385, 10, 6), 2102 /* DFE_5_CMN:11:15 */ 2103 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(393, 15, 11) 2104 }; 2105 static uint32_t BCMI_QTC_XGXS_DSC_DFE_3_CTLr_fields[] = 2106 { 2107 /* DFE_3_ACC_CLR:0:0 */ 2108 PHYMOD_SYMBOL_FIELD_ENCODE(376, 0, 0), 2109 /* DFE_3_INV_P1:8:8 */ 2110 PHYMOD_SYMBOL_FIELD_ENCODE(383, 8, 8), 2111 /* DFE_3_INV_M1:9:9 */ 2112 PHYMOD_SYMBOL_FIELD_ENCODE(382, 9, 9), 2113 /* DFE_3_ERR_GAIN:10:11 */ 2114 PHYMOD_SYMBOL_FIELD_ENCODE(379, 11, 10), 2115 /* DFE_3_GRADIENT_INVERT:12:12 */ 2116 PHYMOD_SYMBOL_FIELD_ENCODE(381, 12, 12), 2117 /* DFE_3_ERR_SEL:13:14 */ 2118 PHYMOD_SYMBOL_FIELD_ENCODE(380, 14, 13), 2119 /* DFE_3_EN:15:15 */ 2120 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(378, 15, 15) 2121 }; 2122 static uint32_t BCMI_QTC_XGXS_DSC_DFE_4_CTLr_fields[] = 2123 { 2124 /* DFE_4_ACC_CLR:0:0 */ 2125 PHYMOD_SYMBOL_FIELD_ENCODE(384, 0, 0), 2126 /* DFE_4_INV_P1:8:8 */ 2127 PHYMOD_SYMBOL_FIELD_ENCODE(391, 8, 8), 2128 /* DFE_4_INV_M1:9:9 */ 2129 PHYMOD_SYMBOL_FIELD_ENCODE(390, 9, 9), 2130 /* DFE_4_ERR_GAIN:10:11 */ 2131 PHYMOD_SYMBOL_FIELD_ENCODE(387, 11, 10), 2132 /* DFE_4_GRADIENT_INVERT:12:12 */ 2133 PHYMOD_SYMBOL_FIELD_ENCODE(389, 12, 12), 2134 /* DFE_4_ERR_SEL:13:14 */ 2135 PHYMOD_SYMBOL_FIELD_ENCODE(388, 14, 13), 2136 /* DFE_4_EN:15:15 */ 2137 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(386, 15, 15) 2138 }; 2139 static uint32_t BCMI_QTC_XGXS_DSC_DFE_5_CTLr_fields[] = 2140 { 2141 /* DFE_5_ACC_CLR:0:0 */ 2142 PHYMOD_SYMBOL_FIELD_ENCODE(392, 0, 0), 2143 /* DFE_5_INV_P1:8:8 */ 2144 PHYMOD_SYMBOL_FIELD_ENCODE(399, 8, 8), 2145 /* DFE_5_INV_M1:9:9 */ 2146 PHYMOD_SYMBOL_FIELD_ENCODE(398, 9, 9), 2147 /* DFE_5_ERR_GAIN:10:11 */ 2148 PHYMOD_SYMBOL_FIELD_ENCODE(395, 11, 10), 2149 /* DFE_5_GRADIENT_INVERT:12:12 */ 2150 PHYMOD_SYMBOL_FIELD_ENCODE(397, 12, 12), 2151 /* DFE_5_ERR_SEL:13:14 */ 2152 PHYMOD_SYMBOL_FIELD_ENCODE(396, 14, 13), 2153 /* DFE_5_EN:15:15 */ 2154 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(394, 15, 15) 2155 }; 2156 static uint32_t BCMI_QTC_XGXS_DSC_DFE_COMMON_CTLr_fields[] = 2157 { 2158 /* DFE_LEAKY_LMS_EN:0:0 */ 2159 PHYMOD_SYMBOL_FIELD_ENCODE(404, 0, 0), 2160 /* DFE_LEAKY_LMS_UPD_DUR:1:4 */ 2161 PHYMOD_SYMBOL_FIELD_ENCODE(405, 4, 1), 2162 /* DFE_HW_EYE_CLOSURE_EN:5:5 */ 2163 PHYMOD_SYMBOL_FIELD_ENCODE(403, 5, 5), 2164 /* DFE_EYE_CLOSURE_ERR_SEL:6:7 */ 2165 PHYMOD_SYMBOL_FIELD_ENCODE(402, 7, 6), 2166 /* DFE_UPDATE_GAIN:13:13 */ 2167 PHYMOD_SYMBOL_FIELD_ENCODE(408, 13, 13), 2168 /* DFE_ALLOW_SIMULT:14:14 */ 2169 PHYMOD_SYMBOL_FIELD_ENCODE(401, 14, 14), 2170 /* DFE_ACC_HYS_EN:15:15 */ 2171 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(400, 15, 15) 2172 }; 2173 static uint32_t BCMI_QTC_XGXS_DSC_DFE_PAT_CTLr_fields[] = 2174 { 2175 /* DFE_PATTERN:0:5 */ 2176 PHYMOD_SYMBOL_FIELD_ENCODE(406, 5, 0), 2177 /* DFE_PATTERN_BIT_EN:8:13 */ 2178 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(407, 13, 8) 2179 }; 2180 static uint32_t BCMI_QTC_XGXS_DSC_E_CTLr_fields[] = 2181 { 2182 /* PD_CH_P1:0:0 */ 2183 PHYMOD_SYMBOL_FIELD_ENCODE(827, 0, 0), 2184 /* OFFSET_PD:1:1 */ 2185 PHYMOD_SYMBOL_FIELD_ENCODE(774, 1, 1), 2186 /* EN_HGAIN:2:2 */ 2187 PHYMOD_SYMBOL_FIELD_ENCODE(475, 2, 2), 2188 /* P1_THRESH_SEL:3:3 */ 2189 PHYMOD_SYMBOL_FIELD_ENCODE(797, 3, 3), 2190 /* M1_THRESH_ZERO:4:4 */ 2191 PHYMOD_SYMBOL_FIELD_ENCODE(664, 4, 4), 2192 /* M1_THRESH_SEL:5:6 */ 2193 PHYMOD_SYMBOL_FIELD_ENCODE(663, 6, 5), 2194 /* PF_HIZ:7:7 */ 2195 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(837, 7, 7) 2196 }; 2197 static uint32_t BCMI_QTC_XGXS_DSC_E_PF2_LOWP_CTLr_fields[] = 2198 { 2199 /* PF2_LOWP_CTRL:0:2 */ 2200 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(833, 2, 0) 2201 }; 2202 static uint32_t BCMI_QTC_XGXS_DSC_E_PF_CTLr_fields[] = 2203 { 2204 /* PF_CTRL:0:3 */ 2205 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(836, 3, 0) 2206 }; 2207 static uint32_t BCMI_QTC_XGXS_DSC_F_DATA_EVEN_OFFSr_fields[] = 2208 { 2209 /* DATA_OFFSET_EVN_BIN:0:5 */ 2210 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(334, 5, 0) 2211 }; 2212 static uint32_t BCMI_QTC_XGXS_DSC_F_DATA_ODD_OFFSr_fields[] = 2213 { 2214 /* DATA_OFFSET_ODD_BIN:0:5 */ 2215 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(335, 5, 0) 2216 }; 2217 static uint32_t BCMI_QTC_XGXS_DSC_F_DC_OFFSr_fields[] = 2218 { 2219 /* DC_OFFSET_BIN:0:6 */ 2220 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(343, 6, 0) 2221 }; 2222 static uint32_t BCMI_QTC_XGXS_DSC_F_M1_EVEN_OFFSr_fields[] = 2223 { 2224 /* M1_OFFSET_EVN_BIN:0:5 */ 2225 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(660, 5, 0) 2226 }; 2227 static uint32_t BCMI_QTC_XGXS_DSC_F_M1_ODD_OFFSr_fields[] = 2228 { 2229 /* M1_OFFSET_ODD_BIN:0:5 */ 2230 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(661, 5, 0) 2231 }; 2232 static uint32_t BCMI_QTC_XGXS_DSC_F_P1_EVEN_OFFSr_fields[] = 2233 { 2234 /* P1_OFFSET_EVN_BIN:0:5 */ 2235 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(794, 5, 0) 2236 }; 2237 static uint32_t BCMI_QTC_XGXS_DSC_F_P1_ODD_OFFSr_fields[] = 2238 { 2239 /* P1_OFFSET_ODD_BIN:0:5 */ 2240 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(795, 5, 0) 2241 }; 2242 static uint32_t BCMI_QTC_XGXS_DSC_HWTUNE_OVR_OVRRr_fields[] = 2243 { 2244 /* HWTUNE_OVR_WRITE_VAL:0:8 */ 2245 PHYMOD_SYMBOL_FIELD_ENCODE(522, 8, 0), 2246 /* HWTUNE_OVR_WRITE_SEL:9:13 */ 2247 PHYMOD_SYMBOL_FIELD_ENCODE(521, 13, 9), 2248 /* HWTUNE_OVR_WRITE_EN:15:15 */ 2249 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(520, 15, 15) 2250 }; 2251 static uint32_t BCMI_QTC_XGXS_DSC_P1_FRAC_OFFS_CTLr_fields[] = 2252 { 2253 /* P1_OFFSET:0:6 */ 2254 PHYMOD_SYMBOL_FIELD_ENCODE(792, 6, 0), 2255 /* P1_OFFSET_EN:7:7 */ 2256 PHYMOD_SYMBOL_FIELD_ENCODE(793, 7, 7), 2257 /* P1_OFF_3LEVELQ_EN:8:8 */ 2258 PHYMOD_SYMBOL_FIELD_ENCODE(796, 8, 8), 2259 /* P1_HWTUNE_MAX:10:15 */ 2260 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(790, 15, 10) 2261 }; 2262 static uint32_t BCMI_QTC_XGXS_DSC_RX_PI_CNT_BIN_Dr_fields[] = 2263 { 2264 /* CNT_BIN_D_DREG:0:6 */ 2265 PHYMOD_SYMBOL_FIELD_ENCODE(298, 6, 0), 2266 /* CNT_BIN_P1_DREG:8:14 */ 2267 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(302, 14, 8) 2268 }; 2269 static uint32_t BCMI_QTC_XGXS_DSC_RX_PI_CNT_BIN_Mr_fields[] = 2270 { 2271 /* CNT_BIN_M1_MREG:0:6 */ 2272 PHYMOD_SYMBOL_FIELD_ENCODE(300, 6, 0), 2273 /* CNT_BIN_D_MREG:8:14 */ 2274 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(299, 14, 8) 2275 }; 2276 static uint32_t BCMI_QTC_XGXS_DSC_RX_PI_CNT_BIN_Pr_fields[] = 2277 { 2278 /* CNT_BIN_P1_PREG:0:6 */ 2279 PHYMOD_SYMBOL_FIELD_ENCODE(303, 6, 0), 2280 /* CNT_BIN_M1_PREG:8:14 */ 2281 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(301, 14, 8) 2282 }; 2283 static uint32_t BCMI_QTC_XGXS_DSC_RX_PI_CTLr_fields[] = 2284 { 2285 /* RX_PI_PHASE_STEP_CNT:0:6 */ 2286 PHYMOD_SYMBOL_FIELD_ENCODE(1030, 6, 0), 2287 /* RX_PI_MANUAL_STROBE:9:9 */ 2288 PHYMOD_SYMBOL_FIELD_ENCODE(1029, 9, 9), 2289 /* RX_PI_PHASE_STEP_DIR:10:10 */ 2290 PHYMOD_SYMBOL_FIELD_ENCODE(1031, 10, 10), 2291 /* RX_PI_MANUAL_MODE:11:11 */ 2292 PHYMOD_SYMBOL_FIELD_ENCODE(1027, 11, 11), 2293 /* RX_PI_SLICERS_EN:12:14 */ 2294 PHYMOD_SYMBOL_FIELD_ENCODE(1032, 14, 12), 2295 /* RX_PI_MANUAL_RESET:15:15 */ 2296 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1028, 15, 15) 2297 }; 2298 static uint32_t BCMI_QTC_XGXS_DSC_RX_PI_DIFF_BINr_fields[] = 2299 { 2300 /* CNT_D_MINUS_M1:0:7 */ 2301 PHYMOD_SYMBOL_FIELD_ENCODE(304, 7, 0), 2302 /* CNT_D_MINUS_P1:8:15 */ 2303 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(305, 15, 8) 2304 }; 2305 static uint32_t BCMI_QTC_XGXS_DSC_SCRATCHr_fields[] = 2306 { 2307 /* UC_DSC_SCRATCH:0:15 */ 2308 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1355, 15, 0) 2309 }; 2310 static uint32_t BCMI_QTC_XGXS_DSC_SLCR_OFFS_CTLr_fields[] = 2311 { 2312 /* HW_SLICER_OFFSET_EN:0:0 */ 2313 PHYMOD_SYMBOL_FIELD_ENCODE(526, 0, 0), 2314 /* HW_SLICER_OFFSET_HYS_EN:1:1 */ 2315 PHYMOD_SYMBOL_FIELD_ENCODE(529, 1, 1), 2316 /* HW_SLICER_OFFSET_ERR_GAIN:2:3 */ 2317 PHYMOD_SYMBOL_FIELD_ENCODE(527, 3, 2), 2318 /* HW_SLICER_OFFSET_INV_DATA:4:4 */ 2319 PHYMOD_SYMBOL_FIELD_ENCODE(530, 4, 4), 2320 /* HW_SLICER_OFFSET_INV_M1:5:5 */ 2321 PHYMOD_SYMBOL_FIELD_ENCODE(531, 5, 5), 2322 /* HW_SLICER_OFFSET_INV_P1:6:6 */ 2323 PHYMOD_SYMBOL_FIELD_ENCODE(532, 6, 6), 2324 /* HW_SLICER_OFFSET_GRAD_INV:7:7 */ 2325 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(528, 7, 7) 2326 }; 2327 static uint32_t BCMI_QTC_XGXS_DSC_SM_CTL0r_fields[] = 2328 { 2329 /* EEE_MODE_EN:1:1 */ 2330 PHYMOD_SYMBOL_FIELD_ENCODE(447, 1, 1), 2331 /* EEE_QUIET_RX_AFE_PWRDWN_VAL:2:2 */ 2332 PHYMOD_SYMBOL_FIELD_ENCODE(451, 2, 2), 2333 /* IGNORE_RX_MODE:3:3 */ 2334 PHYMOD_SYMBOL_FIELD_ENCODE(541, 3, 3), 2335 /* CL72_TIMER_EN:4:4 */ 2336 PHYMOD_SYMBOL_FIELD_ENCODE(280, 4, 4), 2337 /* UC_TUNE_EN:5:5 */ 2338 PHYMOD_SYMBOL_FIELD_ENCODE(1364, 5, 5), 2339 /* HW_TUNE_EN:6:6 */ 2340 PHYMOD_SYMBOL_FIELD_ENCODE(533, 6, 6), 2341 /* UC_TRNSUM_EN:7:7 */ 2342 PHYMOD_SYMBOL_FIELD_ENCODE(1363, 7, 7), 2343 /* EEE_MEASURE_EN:8:8 */ 2344 PHYMOD_SYMBOL_FIELD_ENCODE(446, 8, 8), 2345 /* SLICER_CAL_DONE_CLEAR:9:9 */ 2346 PHYMOD_SYMBOL_FIELD_ENCODE(1098, 9, 9), 2347 /* SLICER_CAL_BYPASS:10:10 */ 2348 PHYMOD_SYMBOL_FIELD_ENCODE(1096, 10, 10), 2349 /* UC_ACK_DSC_EEE_DONE:11:11 */ 2350 PHYMOD_SYMBOL_FIELD_ENCODE(1345, 11, 11), 2351 /* UC_ACK_DSC_RESTART:13:13 */ 2352 PHYMOD_SYMBOL_FIELD_ENCODE(1346, 13, 13), 2353 /* UC_ACK_DSC_CONFIG:14:14 */ 2354 PHYMOD_SYMBOL_FIELD_ENCODE(1344, 14, 14), 2355 /* SET_MEAS_INCOMPLETE:15:15 */ 2356 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1050, 15, 15) 2357 }; 2358 static uint32_t BCMI_QTC_XGXS_DSC_SM_CTL1r_fields[] = 2359 { 2360 /* RX_DSC_LOCK_FRC:0:0 */ 2361 PHYMOD_SYMBOL_FIELD_ENCODE(1004, 0, 0), 2362 /* RX_DSC_LOCK_FRC_VAL:1:1 */ 2363 PHYMOD_SYMBOL_FIELD_ENCODE(1005, 1, 1), 2364 /* DSC_CLR_FRC:2:2 */ 2365 PHYMOD_SYMBOL_FIELD_ENCODE(425, 2, 2), 2366 /* DSC_CLR_FRC_VAL:3:3 */ 2367 PHYMOD_SYMBOL_FIELD_ENCODE(426, 3, 3), 2368 /* TRNSUM_FRZ_FRC:4:4 */ 2369 PHYMOD_SYMBOL_FIELD_ENCODE(1187, 4, 4), 2370 /* TRNSUM_FRZ_FRC_VAL:5:5 */ 2371 PHYMOD_SYMBOL_FIELD_ENCODE(1188, 5, 5), 2372 /* TIMER_DONE_FRC:6:6 */ 2373 PHYMOD_SYMBOL_FIELD_ENCODE(1170, 6, 6), 2374 /* TIMER_DONE_FRC_VAL:7:7 */ 2375 PHYMOD_SYMBOL_FIELD_ENCODE(1171, 7, 7), 2376 /* FREQ_UPD_EN_FRC:8:8 */ 2377 PHYMOD_SYMBOL_FIELD_ENCODE(508, 8, 8), 2378 /* FREQ_UPD_EN_FRC_VAL:9:9 */ 2379 PHYMOD_SYMBOL_FIELD_ENCODE(509, 9, 9), 2380 /* CDR_FRZ_FRC:10:10 */ 2381 PHYMOD_SYMBOL_FIELD_ENCODE(155, 10, 10), 2382 /* CDR_FRZ_FRC_VAL:11:11 */ 2383 PHYMOD_SYMBOL_FIELD_ENCODE(156, 11, 11), 2384 /* TRNSUM_CLR_FRC:12:12 */ 2385 PHYMOD_SYMBOL_FIELD_ENCODE(1174, 12, 12), 2386 /* TRNSUM_CLR_FRC_VAL:13:13 */ 2387 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1175, 13, 13) 2388 }; 2389 static uint32_t BCMI_QTC_XGXS_DSC_SM_CTL2r_fields[] = 2390 { 2391 /* EEE_LFSR_CNT:0:12 */ 2392 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(444, 12, 0) 2393 }; 2394 static uint32_t BCMI_QTC_XGXS_DSC_SM_CTL3r_fields[] = 2395 { 2396 /* MEASURE_LFSR_CNT:0:12 */ 2397 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(688, 12, 0) 2398 }; 2399 static uint32_t BCMI_QTC_XGXS_DSC_SM_CTL4r_fields[] = 2400 { 2401 /* ACQ_CDR_TIMEOUT:0:4 */ 2402 PHYMOD_SYMBOL_FIELD_ENCODE(1, 4, 0), 2403 /* CDR_SETTLE_TIMEOUT:5:9 */ 2404 PHYMOD_SYMBOL_FIELD_ENCODE(166, 9, 5), 2405 /* HW_TUNE_TIMEOUT:10:14 */ 2406 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(534, 14, 10) 2407 }; 2408 static uint32_t BCMI_QTC_XGXS_DSC_SM_CTL5r_fields[] = 2409 { 2410 /* MEASURE_TIMEOUT:0:4 */ 2411 PHYMOD_SYMBOL_FIELD_ENCODE(689, 4, 0), 2412 /* EEE_ACQ_CDR_TIMEOUT:5:9 */ 2413 PHYMOD_SYMBOL_FIELD_ENCODE(436, 9, 5), 2414 /* EEE_CDR_SETTLE_TIMEOUT:10:14 */ 2415 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(440, 14, 10) 2416 }; 2417 static uint32_t BCMI_QTC_XGXS_DSC_SM_CTL6r_fields[] = 2418 { 2419 /* EEE_HW_TUNE_TIMEOUT:0:4 */ 2420 PHYMOD_SYMBOL_FIELD_ENCODE(443, 4, 0), 2421 /* SLICER_CAL_TIMEOUT:5:9 */ 2422 PHYMOD_SYMBOL_FIELD_ENCODE(1099, 9, 5), 2423 /* EEE_ANA_PWR_TIMEOUT:10:14 */ 2424 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(437, 14, 10) 2425 }; 2426 static uint32_t BCMI_QTC_XGXS_DSC_SM_CTL7r_fields[] = 2427 { 2428 /* CDR_BWSEL_INTEG_ACQCDR:0:3 */ 2429 PHYMOD_SYMBOL_FIELD_ENCODE(146, 3, 0), 2430 /* CDR_BWSEL_INTEG_EEE_ACQCDR:4:7 */ 2431 PHYMOD_SYMBOL_FIELD_ENCODE(147, 7, 4), 2432 /* CDR_BWSEL_INTEG_NORM:8:11 */ 2433 PHYMOD_SYMBOL_FIELD_ENCODE(148, 11, 8), 2434 /* CDR_BWSEL_PROP_ACQCDR:12:13 */ 2435 PHYMOD_SYMBOL_FIELD_ENCODE(149, 13, 12), 2436 /* CDR_BWSEL_PROP_NORM:14:15 */ 2437 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(151, 15, 14) 2438 }; 2439 static uint32_t BCMI_QTC_XGXS_DSC_SM_CTL8r_fields[] = 2440 { 2441 /* PHASE_ERR_OFFSET:0:3 */ 2442 PHYMOD_SYMBOL_FIELD_ENCODE(838, 3, 0), 2443 /* EEE_PHASE_ERR_OFFSET:4:7 */ 2444 PHYMOD_SYMBOL_FIELD_ENCODE(448, 7, 4), 2445 /* PHASE_ERR_OFFSET_EN:8:9 */ 2446 PHYMOD_SYMBOL_FIELD_ENCODE(839, 9, 8), 2447 /* EEE_PHASE_ERR_OFFSET_EN:10:11 */ 2448 PHYMOD_SYMBOL_FIELD_ENCODE(449, 11, 10), 2449 /* CDR_BWSEL_PROP_EEE_ACQCDR:14:15 */ 2450 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(150, 15, 14) 2451 }; 2452 static uint32_t BCMI_QTC_XGXS_DSC_SM_CTL9r_fields[] = 2453 { 2454 /* RX_RESTART_PMD:0:0 */ 2455 PHYMOD_SYMBOL_FIELD_ENCODE(1037, 0, 0), 2456 /* RX_RESTART_PMD_HOLD:1:1 */ 2457 PHYMOD_SYMBOL_FIELD_ENCODE(1038, 1, 1), 2458 /* DCOFF_CAL_TIMEOUT:10:14 */ 2459 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(342, 14, 10) 2460 }; 2461 static uint32_t BCMI_QTC_XGXS_DSC_SM_STS_DSC_LOCKr_fields[] = 2462 { 2463 /* RX_DSC_LOCK:0:0 */ 2464 PHYMOD_SYMBOL_FIELD_ENCODE(1003, 0, 0), 2465 /* MEAS_INCOMPLETE:1:1 */ 2466 PHYMOD_SYMBOL_FIELD_ENCODE(690, 1, 1), 2467 /* SLICER_CAL_DONE:2:2 */ 2468 PHYMOD_SYMBOL_FIELD_ENCODE(1097, 2, 2), 2469 /* EEE_MEASURE_CNT:7:15 */ 2470 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(445, 15, 7) 2471 }; 2472 static uint32_t BCMI_QTC_XGXS_DSC_SM_STS_DSC_STr_fields[] = 2473 { 2474 /* DSC_SM_GP_UC_REQ:0:5 */ 2475 PHYMOD_SYMBOL_FIELD_ENCODE(427, 5, 0), 2476 /* CDR_LM_OUTOFLOCK:6:6 */ 2477 PHYMOD_SYMBOL_FIELD_ENCODE(160, 6, 6), 2478 /* DSC_SM_READY_FOR_CMD:7:7 */ 2479 PHYMOD_SYMBOL_FIELD_ENCODE(428, 7, 7), 2480 /* DSC_SM_SCRATCH:8:10 */ 2481 PHYMOD_SYMBOL_FIELD_ENCODE(429, 10, 8), 2482 /* DSC_STATE:11:15 */ 2483 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(430, 15, 11) 2484 }; 2485 static uint32_t BCMI_QTC_XGXS_DSC_SM_STS_DSC_ST_EEE_ONE_HOTr_fields[] = 2486 { 2487 /* DSC_STATE_EEE_ONE_HOT:0:6 */ 2488 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(431, 6, 0) 2489 }; 2490 static uint32_t BCMI_QTC_XGXS_DSC_SM_STS_DSC_ST_ONE_HOTr_fields[] = 2491 { 2492 /* DSC_STATE_ONE_HOT:0:11 */ 2493 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(432, 11, 0) 2494 }; 2495 static uint32_t BCMI_QTC_XGXS_DSC_SM_STS_RESTARTr_fields[] = 2496 { 2497 /* RESTART_PI_EXT_MODE:0:0 */ 2498 PHYMOD_SYMBOL_FIELD_ENCODE(959, 0, 0), 2499 /* RESTART_SIGDET:1:1 */ 2500 PHYMOD_SYMBOL_FIELD_ENCODE(961, 1, 1), 2501 /* RESTART_PMD_RESTART:2:2 */ 2502 PHYMOD_SYMBOL_FIELD_ENCODE(960, 2, 2), 2503 /* EEE_QUIET_FROM_EEE_STATES:3:3 */ 2504 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(450, 3, 3) 2505 }; 2506 static uint32_t BCMI_QTC_XGXS_DSC_TRNSUM_CTL1r_fields[] = 2507 { 2508 /* TRNSUM_TAP_RANGE_SEL:2:3 */ 2509 PHYMOD_SYMBOL_FIELD_ENCODE(1202, 3, 2), 2510 /* CDR_QPHASE_MULT_EN:4:4 */ 2511 PHYMOD_SYMBOL_FIELD_ENCODE(165, 4, 4), 2512 /* TRNSUM_EYE_CLOSURE_EN:5:5 */ 2513 PHYMOD_SYMBOL_FIELD_ENCODE(1183, 5, 5), 2514 /* TRNSUM_GAIN:6:7 */ 2515 PHYMOD_SYMBOL_FIELD_ENCODE(1189, 7, 6), 2516 /* TRNSUM_EDGE_PATTERN_EN:8:8 */ 2517 PHYMOD_SYMBOL_FIELD_ENCODE(1178, 8, 8), 2518 /* TRNSUM_PATTERN_FULL_CHECK_OFF:9:9 */ 2519 PHYMOD_SYMBOL_FIELD_ENCODE(1197, 9, 9), 2520 /* TRNSUM_INV_PATTERN_EN:10:10 */ 2521 PHYMOD_SYMBOL_FIELD_ENCODE(1191, 10, 10), 2522 /* TRNSUM_RANDOM_TAPSEL_DISABLE:11:11 */ 2523 PHYMOD_SYMBOL_FIELD_ENCODE(1200, 11, 11), 2524 /* TRNSUM_ERR_SEL:12:14 */ 2525 PHYMOD_SYMBOL_FIELD_ENCODE(1181, 14, 12), 2526 /* TRNSUM_EN:15:15 */ 2527 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1179, 15, 15) 2528 }; 2529 static uint32_t BCMI_QTC_XGXS_DSC_TRNSUM_CTL2r_fields[] = 2530 { 2531 /* TRNSUM_PATTERN_BIT_EN:0:7 */ 2532 PHYMOD_SYMBOL_FIELD_ENCODE(1196, 7, 0), 2533 /* TRNSUM_PATTERN:8:15 */ 2534 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1195, 15, 8) 2535 }; 2536 static uint32_t BCMI_QTC_XGXS_DSC_TRNSUM_CTL3r_fields[] = 2537 { 2538 /* TRNSUM_TAP_SIGN:0:7 */ 2539 PHYMOD_SYMBOL_FIELD_ENCODE(1203, 7, 0), 2540 /* TRNSUM_TAP_EN:8:15 */ 2541 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1201, 15, 8) 2542 }; 2543 static uint32_t BCMI_QTC_XGXS_DSC_TRNSUM_CTL4r_fields[] = 2544 { 2545 /* TRNSUM_UNSIGNED_CORR:0:0 */ 2546 PHYMOD_SYMBOL_FIELD_ENCODE(1204, 0, 0), 2547 /* TRNSUM_UNSIGNED_FLIP:1:1 */ 2548 PHYMOD_SYMBOL_FIELD_ENCODE(1205, 1, 1), 2549 /* TDR_BIT_SEL:2:6 */ 2550 PHYMOD_SYMBOL_FIELD_ENCODE(1148, 6, 2), 2551 /* TDR_TRNSUM_EN:7:7 */ 2552 PHYMOD_SYMBOL_FIELD_ENCODE(1151, 7, 7), 2553 /* TDR_CYCLE_SEL:8:11 */ 2554 PHYMOD_SYMBOL_FIELD_ENCODE(1150, 11, 8), 2555 /* TDR_CYCLE_BIN:12:15 */ 2556 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1149, 15, 12) 2557 }; 2558 static uint32_t BCMI_QTC_XGXS_DSC_TRNSUM_CTL5r_fields[] = 2559 { 2560 /* TRNSUM_CLR_SC:0:0 */ 2561 PHYMOD_SYMBOL_FIELD_ENCODE(1176, 0, 0), 2562 /* TRNSUM_DISABLE_SM_CLEAR:1:1 */ 2563 PHYMOD_SYMBOL_FIELD_ENCODE(1177, 1, 1), 2564 /* TRNSUM_PATTERN_MATCH_SEL:2:3 */ 2565 PHYMOD_SYMBOL_FIELD_ENCODE(1198, 3, 2), 2566 /* TRNSUM_EYE_CLOSE_PREV_EN:4:4 */ 2567 PHYMOD_SYMBOL_FIELD_ENCODE(1182, 4, 4), 2568 /* TRNSUM_PRBS_SEL:5:6 */ 2569 PHYMOD_SYMBOL_FIELD_ENCODE(1199, 6, 5), 2570 /* SWAP_LMS_M1:10:10 */ 2571 PHYMOD_SYMBOL_FIELD_ENCODE(1115, 10, 10), 2572 /* SWAP_LMS_DATA:11:11 */ 2573 PHYMOD_SYMBOL_FIELD_ENCODE(1114, 11, 11), 2574 /* TRNSUM_EYE_CLOSURE_ERR_SEL:12:13 */ 2575 PHYMOD_SYMBOL_FIELD_ENCODE(1184, 13, 12), 2576 /* EDGE_COUNT_REFLESS_EN:15:15 */ 2577 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(435, 15, 15) 2578 }; 2579 static uint32_t BCMI_QTC_XGXS_DSC_TRNSUM_STS1r_fields[] = 2580 { 2581 /* TRNSUM_E_HIGH:0:15 */ 2582 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1185, 15, 0) 2583 }; 2584 static uint32_t BCMI_QTC_XGXS_DSC_TRNSUM_STS2r_fields[] = 2585 { 2586 /* TRNSUM_E_LOW:0:7 */ 2587 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1186, 7, 0) 2588 }; 2589 static uint32_t BCMI_QTC_XGXS_DSC_TRNSUM_STS3r_fields[] = 2590 { 2591 /* TRNSUM_O_HIGH:0:15 */ 2592 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1193, 15, 0) 2593 }; 2594 static uint32_t BCMI_QTC_XGXS_DSC_TRNSUM_STS4r_fields[] = 2595 { 2596 /* TRNSUM_O_LOW:0:7 */ 2597 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1194, 7, 0) 2598 }; 2599 static uint32_t BCMI_QTC_XGXS_DSC_TRNSUM_STS5r_fields[] = 2600 { 2601 /* TRNSUM_HIGH:0:15 */ 2602 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1190, 15, 0) 2603 }; 2604 static uint32_t BCMI_QTC_XGXS_DSC_TRNSUM_STS6r_fields[] = 2605 { 2606 /* TRNSUM_LOW:0:9 */ 2607 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1192, 9, 0) 2608 }; 2609 static uint32_t BCMI_QTC_XGXS_DSC_UC_CTLr_fields[] = 2610 { 2611 /* UC_DSC_GP_UC_REQ:0:5 */ 2612 PHYMOD_SYMBOL_FIELD_ENCODE(1353, 5, 0), 2613 /* UC_DSC_ERROR_FOUND:6:6 */ 2614 PHYMOD_SYMBOL_FIELD_ENCODE(1352, 6, 6), 2615 /* UC_DSC_READY_FOR_CMD:7:7 */ 2616 PHYMOD_SYMBOL_FIELD_ENCODE(1354, 7, 7), 2617 /* UC_DSC_SUPP_INFO:8:15 */ 2618 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1356, 15, 8) 2619 }; 2620 static uint32_t BCMI_QTC_XGXS_DSC_VGA_CTLr_fields[] = 2621 { 2622 /* VGA_P1_ACC_CLR:0:0 */ 2623 PHYMOD_SYMBOL_FIELD_ENCODE(1403, 0, 0), 2624 /* VGA_ACC_HYS_EN:1:1 */ 2625 PHYMOD_SYMBOL_FIELD_ENCODE(1389, 1, 1), 2626 /* VGA_UPDATE_STYLE:2:3 */ 2627 PHYMOD_SYMBOL_FIELD_ENCODE(1409, 3, 2), 2628 /* VGA_AFFECTED_BY_DFE1:4:4 */ 2629 PHYMOD_SYMBOL_FIELD_ENCODE(1390, 4, 4), 2630 /* VGA_UPDATE_GAIN:6:7 */ 2631 PHYMOD_SYMBOL_FIELD_ENCODE(1408, 7, 6), 2632 /* VGA_INV_P1:8:8 */ 2633 PHYMOD_SYMBOL_FIELD_ENCODE(1399, 8, 8), 2634 /* VGA_INV_M1:9:9 */ 2635 PHYMOD_SYMBOL_FIELD_ENCODE(1398, 9, 9), 2636 /* VGA_ERR_GAIN:10:11 */ 2637 PHYMOD_SYMBOL_FIELD_ENCODE(1395, 11, 10), 2638 /* VGA_P1_GRADIENT_INVERT:12:12 */ 2639 PHYMOD_SYMBOL_FIELD_ENCODE(1404, 12, 12), 2640 /* VGA_ERR_SEL:13:14 */ 2641 PHYMOD_SYMBOL_FIELD_ENCODE(1396, 14, 13), 2642 /* VGA_EN:15:15 */ 2643 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1393, 15, 15) 2644 }; 2645 static uint32_t BCMI_QTC_XGXS_DSC_VGA_P1EYEDIAG_STSr_fields[] = 2646 { 2647 /* VGA_BIN:0:5 */ 2648 PHYMOD_SYMBOL_FIELD_ENCODE(1391, 5, 0), 2649 /* VGA_WANTS_TO_GO_LOW:6:6 */ 2650 PHYMOD_SYMBOL_FIELD_ENCODE(1410, 6, 6), 2651 /* P1_EYEDIAG_BIN:8:13 */ 2652 PHYMOD_SYMBOL_FIELD_ENCODE(788, 13, 8), 2653 /* P1_WANTS_TO_GO_LOW:14:14 */ 2654 PHYMOD_SYMBOL_FIELD_ENCODE(799, 14, 14), 2655 /* P1_WANTS_TO_GO_HIGH:15:15 */ 2656 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(798, 15, 15) 2657 }; 2658 static uint32_t BCMI_QTC_XGXS_DSC_VGA_P1_MISC_CTLr_fields[] = 2659 { 2660 /* VGA_HWTUNE_MIN:0:5 */ 2661 PHYMOD_SYMBOL_FIELD_ENCODE(1397, 5, 0), 2662 /* VGA_OP_SHORT_OFFCAL:6:6 */ 2663 PHYMOD_SYMBOL_FIELD_ENCODE(1401, 6, 6), 2664 /* VGA_OP_SHORT_NORM:7:7 */ 2665 PHYMOD_SYMBOL_FIELD_ENCODE(1400, 7, 7), 2666 /* P1_HWTUNE_MIN:10:15 */ 2667 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(791, 15, 10) 2668 }; 2669 static uint32_t BCMI_QTC_XGXS_DSC_VGA_PAT_EYEDIAG_CTLr_fields[] = 2670 { 2671 /* VGA_PATTERN:0:3 */ 2672 PHYMOD_SYMBOL_FIELD_ENCODE(1405, 3, 0), 2673 /* VGA_PATTERN_BIT_EN:4:7 */ 2674 PHYMOD_SYMBOL_FIELD_ENCODE(1406, 7, 4), 2675 /* P1_EYEDIAG_EN:15:15 */ 2676 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(789, 15, 15) 2677 }; 2678 static uint32_t BCMI_QTC_XGXS_DSC_VGA_TAP_BINr_fields[] = 2679 { 2680 /* VGA1_CTRL_BIN:0:3 */ 2681 PHYMOD_SYMBOL_FIELD_ENCODE(1384, 3, 0), 2682 /* VGA2_CTRL_BIN:4:7 */ 2683 PHYMOD_SYMBOL_FIELD_ENCODE(1385, 7, 4), 2684 /* VGA3_CTRL_BIN:8:11 */ 2685 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1386, 11, 8) 2686 }; 2687 static uint32_t BCMI_QTC_XGXS_ERRMASKr_fields[] = 2688 { 2689 /* ERROR_MASK:0:7 */ 2690 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(497, 7, 0) 2691 }; 2692 static uint32_t BCMI_QTC_XGXS_ERR_GENr_fields[] = 2693 { 2694 /* ERRGEN_EN:0:3 */ 2695 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(496, 3, 0) 2696 }; 2697 static uint32_t BCMI_QTC_XGXS_GBOX_STSr_fields[] = 2698 { 2699 /* GBOX_UNDERRUN_ERR:0:0 */ 2700 PHYMOD_SYMBOL_FIELD_ENCODE(511, 0, 0), 2701 /* GBOX_OVERFLOW_ERR:1:1 */ 2702 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(510, 1, 1) 2703 }; 2704 static uint32_t BCMI_QTC_XGXS_IGNORE_LNK_TMR_TYPEr_fields[] = 2705 { 2706 /* IGNORE_LINK_TIMER_PERIOD:0:15 */ 2707 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(539, 15, 0) 2708 }; 2709 static uint32_t BCMI_QTC_XGXS_LNK_FAIL_INHBT_TMR_NOT_CL72_TYPEr_fields[] = 2710 { 2711 /* LINK_FAIL_INHIBIT_TIMER_NCL72_PERIOD:0:15 */ 2712 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(571, 15, 0) 2713 }; 2714 static uint32_t BCMI_QTC_XGXS_LNK_UP_TYPEr_fields[] = 2715 { 2716 /* LINK_UP_TIMER_PERIOD:0:15 */ 2717 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(586, 15, 0) 2718 }; 2719 static uint32_t BCMI_QTC_XGXS_LN_ADDR0r_fields[] = 2720 { 2721 /* RX_LANE_ADDR_0:0:4 */ 2722 PHYMOD_SYMBOL_FIELD_ENCODE(1007, 4, 0), 2723 /* TX_LANE_ADDR_0:8:12 */ 2724 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1271, 12, 8) 2725 }; 2726 static uint32_t BCMI_QTC_XGXS_LN_ADDR1r_fields[] = 2727 { 2728 /* RX_LANE_ADDR_1:0:4 */ 2729 PHYMOD_SYMBOL_FIELD_ENCODE(1008, 4, 0), 2730 /* TX_LANE_ADDR_1:8:12 */ 2731 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1272, 12, 8) 2732 }; 2733 static uint32_t BCMI_QTC_XGXS_LN_ADDR2r_fields[] = 2734 { 2735 /* RX_LANE_ADDR_2:0:4 */ 2736 PHYMOD_SYMBOL_FIELD_ENCODE(1009, 4, 0), 2737 /* TX_LANE_ADDR_2:8:12 */ 2738 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1273, 12, 8) 2739 }; 2740 static uint32_t BCMI_QTC_XGXS_LN_ADDR3r_fields[] = 2741 { 2742 /* RX_LANE_ADDR_3:0:4 */ 2743 PHYMOD_SYMBOL_FIELD_ENCODE(1010, 4, 0), 2744 /* TX_LANE_ADDR_3:8:12 */ 2745 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1274, 12, 8) 2746 }; 2747 static uint32_t BCMI_QTC_XGXS_MAIN_DEVINPKG5r_fields[] = 2748 { 2749 /* CLAUSE22:0:0 */ 2750 PHYMOD_SYMBOL_FIELD_ENCODE(288, 0, 0), 2751 /* PMA_PMD:1:1 */ 2752 PHYMOD_SYMBOL_FIELD_ENCODE(875, 1, 1), 2753 /* WIS:2:2 */ 2754 PHYMOD_SYMBOL_FIELD_ENCODE(1411, 2, 2), 2755 /* PCS_XS:3:3 */ 2756 PHYMOD_SYMBOL_FIELD_ENCODE(826, 3, 3), 2757 /* PHY_XS:4:4 */ 2758 PHYMOD_SYMBOL_FIELD_ENCODE(841, 4, 4), 2759 /* DTE_XS:5:5 */ 2760 PHYMOD_SYMBOL_FIELD_ENCODE(433, 5, 5), 2761 /* TC:6:6 */ 2762 PHYMOD_SYMBOL_FIELD_ENCODE(1147, 6, 6), 2763 /* AN:7:7 */ 2764 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(43, 7, 7) 2765 }; 2766 static uint32_t BCMI_QTC_XGXS_MAIN_LN_SWPr_fields[] = 2767 { 2768 /* LOG0_TO_PHY_TX_LNSWAP_SEL:0:1 */ 2769 PHYMOD_SYMBOL_FIELD_ENCODE(627, 1, 0), 2770 /* LOG1_TO_PHY_TX_LNSWAP_SEL:2:3 */ 2771 PHYMOD_SYMBOL_FIELD_ENCODE(629, 3, 2), 2772 /* LOG2_TO_PHY_TX_LNSWAP_SEL:4:5 */ 2773 PHYMOD_SYMBOL_FIELD_ENCODE(631, 5, 4), 2774 /* LOG3_TO_PHY_TX_LNSWAP_SEL:6:7 */ 2775 PHYMOD_SYMBOL_FIELD_ENCODE(633, 7, 6), 2776 /* LOG0_TO_PHY_RX_LNSWAP_SEL:8:9 */ 2777 PHYMOD_SYMBOL_FIELD_ENCODE(626, 9, 8), 2778 /* LOG1_TO_PHY_RX_LNSWAP_SEL:10:11 */ 2779 PHYMOD_SYMBOL_FIELD_ENCODE(628, 11, 10), 2780 /* LOG2_TO_PHY_RX_LNSWAP_SEL:12:13 */ 2781 PHYMOD_SYMBOL_FIELD_ENCODE(630, 13, 12), 2782 /* LOG3_TO_PHY_RX_LNSWAP_SEL:14:15 */ 2783 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(632, 15, 14) 2784 }; 2785 static uint32_t BCMI_QTC_XGXS_MAIN_LPBK_CTLr_fields[] = 2786 { 2787 /* LOCAL_PCS_LOOPBACK_ENABLE:0:3 */ 2788 PHYMOD_SYMBOL_FIELD_ENCODE(623, 3, 0), 2789 /* REMOTE_PCS_LOOPBACK_ENABLE:8:11 */ 2790 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(954, 11, 8) 2791 }; 2792 static uint32_t BCMI_QTC_XGXS_MAIN_MDIO_BCSTr_fields[] = 2793 { 2794 /* MULTIPRTS_EN:7:10 */ 2795 PHYMOD_SYMBOL_FIELD_ENCODE(771, 10, 7), 2796 /* PRTAD_BCST:11:15 */ 2797 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(926, 15, 11) 2798 }; 2799 static uint32_t BCMI_QTC_XGXS_MAIN_SERDESIDr_fields[] = 2800 { 2801 /* MODEL_NUMBER:0:5 */ 2802 PHYMOD_SYMBOL_FIELD_ENCODE(768, 5, 0), 2803 /* TECH_PROC:6:8 */ 2804 PHYMOD_SYMBOL_FIELD_ENCODE(1152, 8, 6), 2805 /* BONDING:9:10 */ 2806 PHYMOD_SYMBOL_FIELD_ENCODE(129, 10, 9), 2807 /* REV_NUMBER:11:13 */ 2808 PHYMOD_SYMBOL_FIELD_ENCODE(976, 13, 11), 2809 /* REV_LETTER:14:15 */ 2810 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(975, 15, 14) 2811 }; 2812 static uint32_t BCMI_QTC_XGXS_MAIN_SETUPr_fields[] = 2813 { 2814 /* MASTER_PORT_NUM:0:1 */ 2815 PHYMOD_SYMBOL_FIELD_ENCODE(672, 1, 0), 2816 /* PLL_RESET_EN:2:2 */ 2817 PHYMOD_SYMBOL_FIELD_ENCODE(869, 2, 2), 2818 /* SINGLE_PORT_MODE:3:3 */ 2819 PHYMOD_SYMBOL_FIELD_ENCODE(1094, 3, 3), 2820 /* MAC_TO_PCS_LANE_MAP_SEL_SGMII:4:4 */ 2821 PHYMOD_SYMBOL_FIELD_ENCODE(667, 4, 4), 2822 /* PRESERVE_PREAMBLE:5:5 */ 2823 PHYMOD_SYMBOL_FIELD_ENCODE(925, 5, 5), 2824 /* MAP_LF_TO_LINK_STATUS:6:6 */ 2825 PHYMOD_SYMBOL_FIELD_ENCODE(668, 6, 6), 2826 /* MAP_RF_TO_LINK_STATUS:7:7 */ 2827 PHYMOD_SYMBOL_FIELD_ENCODE(669, 7, 7), 2828 /* CL37_10G_VCO:8:8 */ 2829 PHYMOD_SYMBOL_FIELD_ENCODE(181, 8, 8), 2830 /* DISABLE_XGMII_TO_GMII_ERR_HANDLING:9:9 */ 2831 PHYMOD_SYMBOL_FIELD_ENCODE(420, 9, 9), 2832 /* REFCLK_SEL:13:15 */ 2833 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(942, 15, 13) 2834 }; 2835 static uint32_t BCMI_QTC_XGXS_MAIN_SHIM_FF_THRr_fields[] = 2836 { 2837 /* SHIM_FF_THRESHOLD_10M:0:3 */ 2838 PHYMOD_SYMBOL_FIELD_ENCODE(1061, 3, 0), 2839 /* SHIM_FF_THRESHOLD_100M:4:7 */ 2840 PHYMOD_SYMBOL_FIELD_ENCODE(1060, 7, 4), 2841 /* SHIM_FF_THRESHOLD_1G:8:11 */ 2842 PHYMOD_SYMBOL_FIELD_ENCODE(1062, 11, 8), 2843 /* SHIM_FF_THRESHOLD_2P5G:12:15 */ 2844 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1063, 15, 12) 2845 }; 2846 static uint32_t BCMI_QTC_XGXS_MAIN_SYNCE_CTLr_fields[] = 2847 { 2848 /* SYNCE_MODE0_PHY_LN0:0:1 */ 2849 PHYMOD_SYMBOL_FIELD_ENCODE(1126, 1, 0), 2850 /* SYNCE_MODE1_PHY_LN0:2:3 */ 2851 PHYMOD_SYMBOL_FIELD_ENCODE(1130, 3, 2), 2852 /* SYNCE_MODE0_PHY_LN1:4:5 */ 2853 PHYMOD_SYMBOL_FIELD_ENCODE(1127, 5, 4), 2854 /* SYNCE_MODE1_PHY_LN1:6:7 */ 2855 PHYMOD_SYMBOL_FIELD_ENCODE(1131, 7, 6), 2856 /* SYNCE_MODE0_PHY_LN2:8:9 */ 2857 PHYMOD_SYMBOL_FIELD_ENCODE(1128, 9, 8), 2858 /* SYNCE_MODE1_PHY_LN2:10:11 */ 2859 PHYMOD_SYMBOL_FIELD_ENCODE(1132, 11, 10), 2860 /* SYNCE_MODE0_PHY_LN3:12:13 */ 2861 PHYMOD_SYMBOL_FIELD_ENCODE(1129, 13, 12), 2862 /* SYNCE_MODE1_PHY_LN3:14:15 */ 2863 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1133, 15, 14) 2864 }; 2865 static uint32_t BCMI_QTC_XGXS_MAIN_SYNCE_DIVISOR0_PHY_LN0r_fields[] = 2866 { 2867 /* SYNCE_DIVISOR0:0:15 */ 2868 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1122, 15, 0) 2869 }; 2870 static uint32_t BCMI_QTC_XGXS_MAIN_SYNCE_DIVISOR1_PHY_LN1r_fields[] = 2871 { 2872 /* SYNCE_DIVISOR1:0:15 */ 2873 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1123, 15, 0) 2874 }; 2875 static uint32_t BCMI_QTC_XGXS_MAIN_SYNCE_DIVISOR2_PHY_LN2r_fields[] = 2876 { 2877 /* SYNCE_DIVISOR2:0:15 */ 2878 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1124, 15, 0) 2879 }; 2880 static uint32_t BCMI_QTC_XGXS_MAIN_SYNCE_DIVISOR3_PHY_LN3r_fields[] = 2881 { 2882 /* SYNCE_DIVISOR3:0:15 */ 2883 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1125, 15, 0) 2884 }; 2885 static uint32_t BCMI_QTC_XGXS_MAIN_TICK_CTL0r_fields[] = 2886 { 2887 /* TICK_DENOMINATOR:2:11 */ 2888 PHYMOD_SYMBOL_FIELD_ENCODE(1166, 11, 2), 2889 /* TICK_NUMERATOR_LOWER:12:15 */ 2890 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1167, 15, 12) 2891 }; 2892 static uint32_t BCMI_QTC_XGXS_MAIN_TICK_CTL1r_fields[] = 2893 { 2894 /* TICK_NUMERATOR_UPPER:0:14 */ 2895 PHYMOD_SYMBOL_FIELD_ENCODE(1168, 14, 0), 2896 /* TICK_OVERRIDE:15:15 */ 2897 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1169, 15, 15) 2898 }; 2899 static uint32_t BCMI_QTC_XGXS_MAIN_UNIMAC_SHIM_CLKr_fields[] = 2900 { 2901 /* SHIM_TX_CLK_GATE_DISABLE:0:3 */ 2902 PHYMOD_SYMBOL_FIELD_ENCODE(1065, 3, 0), 2903 /* SHIM_RX_CLK_GATE_DISABLE:4:7 */ 2904 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1064, 7, 4) 2905 }; 2906 static uint32_t BCMI_QTC_XGXS_MASKDATAr_fields[] = 2907 { 2908 /* MASKDATA:0:15 */ 2909 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(670, 15, 0) 2910 }; 2911 static uint32_t BCMI_QTC_XGXS_MDIO_AERr_fields[] = 2912 { 2913 /* MDIO_AER:0:15 */ 2914 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(674, 15, 0) 2915 }; 2916 static uint32_t BCMI_QTC_XGXS_MDIO_BCST_PORT_ADDRr_fields[] = 2917 { 2918 /* MDIO_BRCST_PORT_ADDR:0:4 */ 2919 PHYMOD_SYMBOL_FIELD_ENCODE(676, 4, 0), 2920 /* MDIO_DRV_COMCLK:15:15 */ 2921 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(684, 15, 15) 2922 }; 2923 static uint32_t BCMI_QTC_XGXS_MDIO_MMD_SELr_fields[] = 2924 { 2925 /* MDIO_DEV_CL22_EN:0:0 */ 2926 PHYMOD_SYMBOL_FIELD_ENCODE(679, 0, 0), 2927 /* MDIO_DEV_PMD_EN:2:2 */ 2928 PHYMOD_SYMBOL_FIELD_ENCODE(683, 2, 2), 2929 /* MDIO_DEV_AN_EN:3:3 */ 2930 PHYMOD_SYMBOL_FIELD_ENCODE(678, 3, 3), 2931 /* MDIO_DEV_PHY_EN:4:4 */ 2932 PHYMOD_SYMBOL_FIELD_ENCODE(682, 4, 4), 2933 /* MDIO_DEV_DTE_EN:5:5 */ 2934 PHYMOD_SYMBOL_FIELD_ENCODE(680, 5, 5), 2935 /* MDIO_DEV_PCS_EN:6:6 */ 2936 PHYMOD_SYMBOL_FIELD_ENCODE(681, 6, 6), 2937 /* MDIO_MULTI_MMDS_EN:14:14 */ 2938 PHYMOD_SYMBOL_FIELD_ENCODE(686, 14, 14), 2939 /* MDIO_MULTI_PRTS_EN:15:15 */ 2940 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(687, 15, 15) 2941 }; 2942 static uint32_t BCMI_QTC_XGXS_MISCr_fields[] = 2943 { 2944 /* ENABLE_TX_LANE:0:0 */ 2945 PHYMOD_SYMBOL_FIELD_ENCODE(454, 0, 0), 2946 /* RSTB_TX_LANE:1:1 */ 2947 PHYMOD_SYMBOL_FIELD_ENCODE(984, 1, 1), 2948 /* TX_FIFO_WATERMARK:2:7 */ 2949 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1270, 7, 2) 2950 }; 2951 static uint32_t BCMI_QTC_XGXS_OUI_LWRr_fields[] = 2952 { 2953 /* OUI_LOWER_DATA:0:15 */ 2954 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(784, 15, 0) 2955 }; 2956 static uint32_t BCMI_QTC_XGXS_OUI_UPRr_fields[] = 2957 { 2958 /* OUI_UPPER_DATA:0:7 */ 2959 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(785, 7, 0) 2960 }; 2961 static uint32_t BCMI_QTC_XGXS_PATGEN_SEQ0r_fields[] = 2962 { 2963 /* PATT_GEN_SEQ_0:0:15 */ 2964 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(802, 15, 0) 2965 }; 2966 static uint32_t BCMI_QTC_XGXS_PATGEN_SEQ1r_fields[] = 2967 { 2968 /* PATT_GEN_SEQ_1:0:15 */ 2969 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(803, 15, 0) 2970 }; 2971 static uint32_t BCMI_QTC_XGXS_PATGEN_SEQ2r_fields[] = 2972 { 2973 /* PATT_GEN_SEQ_2:0:15 */ 2974 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(809, 15, 0) 2975 }; 2976 static uint32_t BCMI_QTC_XGXS_PATGEN_SEQ3r_fields[] = 2977 { 2978 /* PATT_GEN_SEQ_3:0:15 */ 2979 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(810, 15, 0) 2980 }; 2981 static uint32_t BCMI_QTC_XGXS_PATGEN_SEQ4r_fields[] = 2982 { 2983 /* PATT_GEN_SEQ_4:0:15 */ 2984 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(811, 15, 0) 2985 }; 2986 static uint32_t BCMI_QTC_XGXS_PATGEN_SEQ5r_fields[] = 2987 { 2988 /* PATT_GEN_SEQ_5:0:15 */ 2989 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(812, 15, 0) 2990 }; 2991 static uint32_t BCMI_QTC_XGXS_PATGEN_SEQ6r_fields[] = 2992 { 2993 /* PATT_GEN_SEQ_6:0:15 */ 2994 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(813, 15, 0) 2995 }; 2996 static uint32_t BCMI_QTC_XGXS_PATGEN_SEQ7r_fields[] = 2997 { 2998 /* PATT_GEN_SEQ_7:0:15 */ 2999 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(814, 15, 0) 3000 }; 3001 static uint32_t BCMI_QTC_XGXS_PATGEN_SEQ8r_fields[] = 3002 { 3003 /* PATT_GEN_SEQ_8:0:15 */ 3004 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(815, 15, 0) 3005 }; 3006 static uint32_t BCMI_QTC_XGXS_PATGEN_SEQ9r_fields[] = 3007 { 3008 /* PATT_GEN_SEQ_9:0:15 */ 3009 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(816, 15, 0) 3010 }; 3011 static uint32_t BCMI_QTC_XGXS_PATGEN_SEQ_10r_fields[] = 3012 { 3013 /* PATT_GEN_SEQ_10:0:15 */ 3014 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(804, 15, 0) 3015 }; 3016 static uint32_t BCMI_QTC_XGXS_PATGEN_SEQ_11r_fields[] = 3017 { 3018 /* PATT_GEN_SEQ_11:0:15 */ 3019 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(805, 15, 0) 3020 }; 3021 static uint32_t BCMI_QTC_XGXS_PATGEN_SEQ_12r_fields[] = 3022 { 3023 /* PATT_GEN_SEQ_12:0:15 */ 3024 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(806, 15, 0) 3025 }; 3026 static uint32_t BCMI_QTC_XGXS_PATGEN_SEQ_13r_fields[] = 3027 { 3028 /* PATT_GEN_SEQ_13:0:15 */ 3029 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(807, 15, 0) 3030 }; 3031 static uint32_t BCMI_QTC_XGXS_PATGEN_SEQ_14r_fields[] = 3032 { 3033 /* PATT_GEN_SEQ_14:0:15 */ 3034 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(808, 15, 0) 3035 }; 3036 static uint32_t BCMI_QTC_XGXS_PAYLOADBYTESr_fields[] = 3037 { 3038 /* BYTE0:0:7 */ 3039 PHYMOD_SYMBOL_FIELD_ENCODE(131, 7, 0), 3040 /* BYTE1:8:15 */ 3041 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(132, 15, 8) 3042 }; 3043 static uint32_t BCMI_QTC_XGXS_PCS_CTLr_fields[] = 3044 { 3045 /* DISPARITY_ERR_NOT_CAUSE_LOSS_SYNC:0:0 */ 3046 PHYMOD_SYMBOL_FIELD_ENCODE(421, 0, 0), 3047 /* RUNNING_DISPARITY_ERR_MSK:1:1 */ 3048 PHYMOD_SYMBOL_FIELD_ENCODE(987, 1, 1), 3049 /* LPI_ENABLE:2:2 */ 3050 PHYMOD_SYMBOL_FIELD_ENCODE(642, 2, 2), 3051 /* CL36BYTEDELETEMODE:3:4 */ 3052 PHYMOD_SYMBOL_FIELD_ENCODE(168, 4, 3), 3053 /* CL36_RXSM_DEBUG_SP_SEL:5:6 */ 3054 PHYMOD_SYMBOL_FIELD_ENCODE(174, 6, 5), 3055 /* SYNC_ACQ_STATUS_DEBUG_SP_SEL:7:8 */ 3056 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1134, 8, 7) 3057 }; 3058 static uint32_t BCMI_QTC_XGXS_PCS_LATCH_STSr_fields[] = 3059 { 3060 /* SYNC_STATUS_LL_SP0:0:0 */ 3061 PHYMOD_SYMBOL_FIELD_ENCODE(1139, 0, 0), 3062 /* SYNC_STATUS_LH_SP0:1:1 */ 3063 PHYMOD_SYMBOL_FIELD_ENCODE(1135, 1, 1), 3064 /* LINK_STATUS_LL_SP0:2:2 */ 3065 PHYMOD_SYMBOL_FIELD_ENCODE(578, 2, 2), 3066 /* LINK_STATUS_LH_SP0:3:3 */ 3067 PHYMOD_SYMBOL_FIELD_ENCODE(574, 3, 3), 3068 /* SYNC_STATUS_LL_SP1:4:4 */ 3069 PHYMOD_SYMBOL_FIELD_ENCODE(1140, 4, 4), 3070 /* SYNC_STATUS_LH_SP1:5:5 */ 3071 PHYMOD_SYMBOL_FIELD_ENCODE(1136, 5, 5), 3072 /* LINK_STATUS_LL_SP1:6:6 */ 3073 PHYMOD_SYMBOL_FIELD_ENCODE(579, 6, 6), 3074 /* LINK_STATUS_LH_SP1:7:7 */ 3075 PHYMOD_SYMBOL_FIELD_ENCODE(575, 7, 7), 3076 /* SYNC_STATUS_LL_SP2:8:8 */ 3077 PHYMOD_SYMBOL_FIELD_ENCODE(1141, 8, 8), 3078 /* SYNC_STATUS_LH_SP2:9:9 */ 3079 PHYMOD_SYMBOL_FIELD_ENCODE(1137, 9, 9), 3080 /* LINK_STATUS_LL_SP2:10:10 */ 3081 PHYMOD_SYMBOL_FIELD_ENCODE(580, 10, 10), 3082 /* LINK_STATUS_LH_SP2:11:11 */ 3083 PHYMOD_SYMBOL_FIELD_ENCODE(576, 11, 11), 3084 /* SYNC_STATUS_LL_SP3:12:12 */ 3085 PHYMOD_SYMBOL_FIELD_ENCODE(1142, 12, 12), 3086 /* SYNC_STATUS_LH_SP3:13:13 */ 3087 PHYMOD_SYMBOL_FIELD_ENCODE(1138, 13, 13), 3088 /* LINK_STATUS_LL_SP3:14:14 */ 3089 PHYMOD_SYMBOL_FIELD_ENCODE(581, 14, 14), 3090 /* LINK_STATUS_LH_SP3:15:15 */ 3091 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(577, 15, 15) 3092 }; 3093 static uint32_t BCMI_QTC_XGXS_PCS_LIVE_STSr_fields[] = 3094 { 3095 /* SYNC_STATUS_SP0:0:0 */ 3096 PHYMOD_SYMBOL_FIELD_ENCODE(1143, 0, 0), 3097 /* LINK_STATUS_SP0:1:1 */ 3098 PHYMOD_SYMBOL_FIELD_ENCODE(582, 1, 1), 3099 /* SYNC_STATUS_SP1:2:2 */ 3100 PHYMOD_SYMBOL_FIELD_ENCODE(1144, 2, 2), 3101 /* LINK_STATUS_SP1:3:3 */ 3102 PHYMOD_SYMBOL_FIELD_ENCODE(583, 3, 3), 3103 /* SYNC_STATUS_SP2:4:4 */ 3104 PHYMOD_SYMBOL_FIELD_ENCODE(1145, 4, 4), 3105 /* LINK_STATUS_SP2:5:5 */ 3106 PHYMOD_SYMBOL_FIELD_ENCODE(584, 5, 5), 3107 /* SYNC_STATUS_SP3:6:6 */ 3108 PHYMOD_SYMBOL_FIELD_ENCODE(1146, 6, 6), 3109 /* LINK_STATUS_SP3:7:7 */ 3110 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(585, 7, 7) 3111 }; 3112 static uint32_t BCMI_QTC_XGXS_PHYID2r_fields[] = 3113 { 3114 /* REGID1:0:15 */ 3115 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(949, 15, 0) 3116 }; 3117 static uint32_t BCMI_QTC_XGXS_PHYID3r_fields[] = 3118 { 3119 /* REGID2:0:15 */ 3120 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(950, 15, 0) 3121 }; 3122 static uint32_t BCMI_QTC_XGXS_PKTGENCTL1r_fields[] = 3123 { 3124 /* TX_PORT_SEL:0:3 */ 3125 PHYMOD_SYMBOL_FIELD_ENCODE(1334, 3, 0), 3126 /* RX_PORT_SEL:4:7 */ 3127 PHYMOD_SYMBOL_FIELD_ENCODE(1036, 7, 4), 3128 /* LPI_EN:8:8 */ 3129 PHYMOD_SYMBOL_FIELD_ENCODE(641, 8, 8), 3130 /* CLR_CRCCNT:9:9 */ 3131 PHYMOD_SYMBOL_FIELD_ENCODE(293, 9, 9), 3132 /* RX_BUS_TYPE:10:10 */ 3133 PHYMOD_SYMBOL_FIELD_ENCODE(994, 10, 10), 3134 /* RX_PKT_CHECK_EN:11:11 */ 3135 PHYMOD_SYMBOL_FIELD_ENCODE(1033, 11, 11), 3136 /* NUMBER_PKT:12:15 */ 3137 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(772, 15, 12) 3138 }; 3139 static uint32_t BCMI_QTC_XGXS_PKTGENCTL2r_fields[] = 3140 { 3141 /* IPG_SIZE:0:4 */ 3142 PHYMOD_SYMBOL_FIELD_ENCODE(542, 4, 0), 3143 /* PKT_SIZE:5:10 */ 3144 PHYMOD_SYMBOL_FIELD_ENCODE(845, 10, 5), 3145 /* PAYLOAD_TYPE:11:13 */ 3146 PHYMOD_SYMBOL_FIELD_ENCODE(819, 13, 11), 3147 /* TX_BUS_TYPE:14:14 */ 3148 PHYMOD_SYMBOL_FIELD_ENCODE(1253, 14, 14), 3149 /* PKTGEN_EN:15:15 */ 3150 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(844, 15, 15) 3151 }; 3152 static uint32_t BCMI_QTC_XGXS_PKT_CTRS_X4_SP0_RXPKTCNT_Lr_fields[] = 3153 { 3154 /* RXPKTCNT_L:0:15 */ 3155 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(989, 15, 0) 3156 }; 3157 static uint32_t BCMI_QTC_XGXS_PKT_CTRS_X4_SP0_RXPKTCNT_Ur_fields[] = 3158 { 3159 /* RXPKTCNT_U:0:15 */ 3160 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(990, 15, 0) 3161 }; 3162 static uint32_t BCMI_QTC_XGXS_PKT_CTRS_X4_SP0_TXPKTCNT_Lr_fields[] = 3163 { 3164 /* TXPKTCNT_L:0:15 */ 3165 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1249, 15, 0) 3166 }; 3167 static uint32_t BCMI_QTC_XGXS_PKT_CTRS_X4_SP0_TXPKTCNT_Ur_fields[] = 3168 { 3169 /* TXPKTCNT_U:0:15 */ 3170 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1250, 15, 0) 3171 }; 3172 static uint32_t BCMI_QTC_XGXS_PKT_CTRS_X4_SP1_RXPKTCNT_Lr_fields[] = 3173 { 3174 /* RXPKTCNT_L:0:15 */ 3175 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(989, 15, 0) 3176 }; 3177 static uint32_t BCMI_QTC_XGXS_PKT_CTRS_X4_SP1_RXPKTCNT_Ur_fields[] = 3178 { 3179 /* RXPKTCNT_U:0:15 */ 3180 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(990, 15, 0) 3181 }; 3182 static uint32_t BCMI_QTC_XGXS_PKT_CTRS_X4_SP1_TXPKTCNT_Lr_fields[] = 3183 { 3184 /* TXPKTCNT_L:0:15 */ 3185 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1249, 15, 0) 3186 }; 3187 static uint32_t BCMI_QTC_XGXS_PKT_CTRS_X4_SP1_TXPKTCNT_Ur_fields[] = 3188 { 3189 /* TXPKTCNT_U:0:15 */ 3190 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1250, 15, 0) 3191 }; 3192 static uint32_t BCMI_QTC_XGXS_PKT_CTRS_X4_SP2_RXPKTCNT_Lr_fields[] = 3193 { 3194 /* RXPKTCNT_L:0:15 */ 3195 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(989, 15, 0) 3196 }; 3197 static uint32_t BCMI_QTC_XGXS_PKT_CTRS_X4_SP2_RXPKTCNT_Ur_fields[] = 3198 { 3199 /* RXPKTCNT_U:0:15 */ 3200 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(990, 15, 0) 3201 }; 3202 static uint32_t BCMI_QTC_XGXS_PKT_CTRS_X4_SP2_TXPKTCNT_Lr_fields[] = 3203 { 3204 /* TXPKTCNT_L:0:15 */ 3205 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1249, 15, 0) 3206 }; 3207 static uint32_t BCMI_QTC_XGXS_PKT_CTRS_X4_SP2_TXPKTCNT_Ur_fields[] = 3208 { 3209 /* TXPKTCNT_U:0:15 */ 3210 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1250, 15, 0) 3211 }; 3212 static uint32_t BCMI_QTC_XGXS_PKT_CTRS_X4_SP3_RXPKTCNT_Lr_fields[] = 3213 { 3214 /* RXPKTCNT_L:0:15 */ 3215 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(989, 15, 0) 3216 }; 3217 static uint32_t BCMI_QTC_XGXS_PKT_CTRS_X4_SP3_RXPKTCNT_Ur_fields[] = 3218 { 3219 /* RXPKTCNT_U:0:15 */ 3220 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(990, 15, 0) 3221 }; 3222 static uint32_t BCMI_QTC_XGXS_PKT_CTRS_X4_SP3_TXPKTCNT_Lr_fields[] = 3223 { 3224 /* TXPKTCNT_L:0:15 */ 3225 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1249, 15, 0) 3226 }; 3227 static uint32_t BCMI_QTC_XGXS_PKT_CTRS_X4_SP3_TXPKTCNT_Ur_fields[] = 3228 { 3229 /* TXPKTCNT_U:0:15 */ 3230 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1250, 15, 0) 3231 }; 3232 static uint32_t BCMI_QTC_XGXS_PLL_CALCTL0r_fields[] = 3233 { 3234 /* CALIB_STEP_TIME:0:12 */ 3235 PHYMOD_SYMBOL_FIELD_ENCODE(136, 12, 0), 3236 /* CAL_TH:14:15 */ 3237 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(143, 15, 14) 3238 }; 3239 static uint32_t BCMI_QTC_XGXS_PLL_CALCTL1r_fields[] = 3240 { 3241 /* FREQDET_TIME:0:15 */ 3242 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(505, 15, 0) 3243 }; 3244 static uint32_t BCMI_QTC_XGXS_PLL_CALCTL2r_fields[] = 3245 { 3246 /* CALIB_CAP_CHARGE_TIME:0:11 */ 3247 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(134, 11, 0) 3248 }; 3249 static uint32_t BCMI_QTC_XGXS_PLL_CALCTL3r_fields[] = 3250 { 3251 /* FREQDET_WIN:0:7 */ 3252 PHYMOD_SYMBOL_FIELD_ENCODE(507, 7, 0), 3253 /* FREQDET_TIME_MSB:9:9 */ 3254 PHYMOD_SYMBOL_FIELD_ENCODE(506, 9, 9), 3255 /* DEBUG_CLR:10:10 */ 3256 PHYMOD_SYMBOL_FIELD_ENCODE(349, 10, 10), 3257 /* ACCEL_EN:11:11 */ 3258 PHYMOD_SYMBOL_FIELD_ENCODE(0, 11, 11), 3259 /* EXT_STATE:12:15 */ 3260 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(503, 15, 12) 3261 }; 3262 static uint32_t BCMI_QTC_XGXS_PLL_CALCTL4r_fields[] = 3263 { 3264 /* EXT_RANGE:0:6 */ 3265 PHYMOD_SYMBOL_FIELD_ENCODE(500, 6, 0), 3266 /* EN_CALIB_N:8:8 */ 3267 PHYMOD_SYMBOL_FIELD_ENCODE(466, 8, 8), 3268 /* CALIB_START:9:9 */ 3269 PHYMOD_SYMBOL_FIELD_ENCODE(135, 9, 9), 3270 /* CAP_DELAY:10:10 */ 3271 PHYMOD_SYMBOL_FIELD_ENCODE(145, 10, 10), 3272 /* CAL_PAUSE_REL:11:11 */ 3273 PHYMOD_SYMBOL_FIELD_ENCODE(141, 11, 11), 3274 /* CAL_PAUSE_EN:12:12 */ 3275 PHYMOD_SYMBOL_FIELD_ENCODE(140, 12, 12), 3276 /* PLL_FORCE_CAP_PASS:13:13 */ 3277 PHYMOD_SYMBOL_FIELD_ENCODE(853, 13, 13), 3278 /* PLL_FORCE_CAP_PASS_EN:14:14 */ 3279 PHYMOD_SYMBOL_FIELD_ENCODE(854, 14, 14), 3280 /* HALFSTEP_EN:15:15 */ 3281 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(512, 15, 15) 3282 }; 3283 static uint32_t BCMI_QTC_XGXS_PLL_CALCTL5r_fields[] = 3284 { 3285 /* PLLFORCE_FDONE_EN:0:0 */ 3286 PHYMOD_SYMBOL_FIELD_ENCODE(848, 0, 0), 3287 /* PLLFORCE_FDONE:1:1 */ 3288 PHYMOD_SYMBOL_FIELD_ENCODE(847, 1, 1), 3289 /* PLL_LOCK_FRC:2:2 */ 3290 PHYMOD_SYMBOL_FIELD_ENCODE(857, 2, 2), 3291 /* PLL_LOCK_FRC_VAL:3:3 */ 3292 PHYMOD_SYMBOL_FIELD_ENCODE(858, 3, 3), 3293 /* LKDT_BYP:4:4 */ 3294 PHYMOD_SYMBOL_FIELD_ENCODE(591, 4, 4), 3295 /* AUTOCAL_CNT:5:7 */ 3296 PHYMOD_SYMBOL_FIELD_ENCODE(107, 7, 5), 3297 /* AUTOCAL_EN:8:8 */ 3298 PHYMOD_SYMBOL_FIELD_ENCODE(108, 8, 8), 3299 /* VCO_RST_EN:12:12 */ 3300 PHYMOD_SYMBOL_FIELD_ENCODE(1381, 12, 12), 3301 /* LKDT_PAUSE_REL:13:13 */ 3302 PHYMOD_SYMBOL_FIELD_ENCODE(593, 13, 13), 3303 /* LKDT_PAUSE_EN:14:14 */ 3304 PHYMOD_SYMBOL_FIELD_ENCODE(592, 14, 14), 3305 /* PLL_SEQ_START:15:15 */ 3306 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(870, 15, 15) 3307 }; 3308 static uint32_t BCMI_QTC_XGXS_PLL_CALCTL6r_fields[] = 3309 { 3310 /* PLLPON_SEL:1:1 */ 3311 PHYMOD_SYMBOL_FIELD_ENCODE(850, 1, 1), 3312 /* VCOPON_SEL:3:3 */ 3313 PHYMOD_SYMBOL_FIELD_ENCODE(1373, 3, 3), 3314 /* VCOBUFPON_SEL:5:5 */ 3315 PHYMOD_SYMBOL_FIELD_ENCODE(1367, 5, 5), 3316 /* VCORANGE_SEL:6:6 */ 3317 PHYMOD_SYMBOL_FIELD_ENCODE(1374, 6, 6), 3318 /* BAND_IQBUF_SEL:7:7 */ 3319 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(113, 7, 7) 3320 }; 3321 static uint32_t BCMI_QTC_XGXS_PLL_CALSTS0r_fields[] = 3322 { 3323 /* PLL_RANGE:0:6 */ 3324 PHYMOD_SYMBOL_FIELD_ENCODE(868, 6, 0), 3325 /* PLL_LOCK_BAR_STKY:8:8 */ 3326 PHYMOD_SYMBOL_FIELD_ENCODE(856, 8, 8), 3327 /* PLL_LOCK:9:9 */ 3328 PHYMOD_SYMBOL_FIELD_ENCODE(855, 9, 9), 3329 /* CAL_VALID:10:10 */ 3330 PHYMOD_SYMBOL_FIELD_ENCODE(144, 10, 10), 3331 /* CAL_STATE:11:14 */ 3332 PHYMOD_SYMBOL_FIELD_ENCODE(142, 14, 11), 3333 /* PLL_FAIL_STKY:15:15 */ 3334 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(852, 15, 15) 3335 }; 3336 static uint32_t BCMI_QTC_XGXS_PLL_CALSTS1r_fields[] = 3337 { 3338 /* CALREF_COUNTER:0:12 */ 3339 PHYMOD_SYMBOL_FIELD_ENCODE(137, 12, 0), 3340 /* LKDTVCO_COUNTER_MSB:14:14 */ 3341 PHYMOD_SYMBOL_FIELD_ENCODE(590, 14, 14), 3342 /* LKDTREF_COUNTER_MSB:15:15 */ 3343 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(588, 15, 15) 3344 }; 3345 static uint32_t BCMI_QTC_XGXS_PLL_CALSTS2r_fields[] = 3346 { 3347 /* CALVCO_COUNTER:0:12 */ 3348 PHYMOD_SYMBOL_FIELD_ENCODE(139, 12, 0), 3349 /* BAND_IQBUF_MUX:13:15 */ 3350 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(112, 15, 13) 3351 }; 3352 static uint32_t BCMI_QTC_XGXS_PLL_CALSTS3r_fields[] = 3353 { 3354 /* LKDTREF_COUNTER:0:15 */ 3355 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(587, 15, 0) 3356 }; 3357 static uint32_t BCMI_QTC_XGXS_PLL_CALSTS4r_fields[] = 3358 { 3359 /* LKDTVCO_COUNTER:0:15 */ 3360 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(589, 15, 0) 3361 }; 3362 static uint32_t BCMI_QTC_XGXS_PLL_CALSTS5r_fields[] = 3363 { 3364 /* CALSTATE_ONEHOT:0:9 */ 3365 PHYMOD_SYMBOL_FIELD_ENCODE(138, 9, 0), 3366 /* VCOBUFPON_MUX:10:13 */ 3367 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1366, 13, 10) 3368 }; 3369 static uint32_t BCMI_QTC_XGXS_PLL_CALSTS6r_fields[] = 3370 { 3371 /* PLLPON_MUX:0:3 */ 3372 PHYMOD_SYMBOL_FIELD_ENCODE(849, 3, 0), 3373 /* VCOPON_MUX:4:7 */ 3374 PHYMOD_SYMBOL_FIELD_ENCODE(1372, 7, 4), 3375 /* VCO_RANGE_MUX:8:14 */ 3376 PHYMOD_SYMBOL_FIELD_ENCODE(1380, 14, 8), 3377 /* PLL_PWRDN_OR:15:15 */ 3378 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(867, 15, 15) 3379 }; 3380 static uint32_t BCMI_QTC_XGXS_PLL_CTL0r_fields[] = 3381 { 3382 /* PLL_SPARE_0_0:0:6 */ 3383 PHYMOD_SYMBOL_FIELD_ENCODE(872, 6, 0), 3384 /* LC_REFCLK_ADJ_1_0:7:8 */ 3385 PHYMOD_SYMBOL_FIELD_ENCODE(563, 8, 7), 3386 /* RPAR:9:11 */ 3387 PHYMOD_SYMBOL_FIELD_ENCODE(982, 11, 9), 3388 /* PLL_SPARE_0_1:12:12 */ 3389 PHYMOD_SYMBOL_FIELD_ENCODE(873, 12, 12), 3390 /* TERM_CM_EN:13:13 */ 3391 PHYMOD_SYMBOL_FIELD_ENCODE(1154, 13, 13), 3392 /* CPAR:14:15 */ 3393 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(317, 15, 14) 3394 }; 3395 static uint32_t BCMI_QTC_XGXS_PLL_CTL1r_fields[] = 3396 { 3397 /* CURR_SEL:0:3 */ 3398 PHYMOD_SYMBOL_FIELD_ENCODE(330, 3, 0), 3399 /* PLL_SPARE_1_0:4:4 */ 3400 PHYMOD_SYMBOL_FIELD_ENCODE(874, 4, 4), 3401 /* EN_8P5G_VCO:5:5 */ 3402 PHYMOD_SYMBOL_FIELD_ENCODE(465, 5, 5), 3403 /* VCO_RANGE:6:12 */ 3404 PHYMOD_SYMBOL_FIELD_ENCODE(1379, 12, 6), 3405 /* ENB_8T:13:13 */ 3406 PHYMOD_SYMBOL_FIELD_ENCODE(457, 13, 13), 3407 /* ENB_10T:14:14 */ 3408 PHYMOD_SYMBOL_FIELD_ENCODE(455, 14, 14), 3409 /* EN_HCUR_VCO:15:15 */ 3410 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(474, 15, 15) 3411 }; 3412 static uint32_t BCMI_QTC_XGXS_PLL_CTL2r_fields[] = 3413 { 3414 /* VCO_PON:0:3 */ 3415 PHYMOD_SYMBOL_FIELD_ENCODE(1378, 3, 0), 3416 /* EN_8P5G:4:4 */ 3417 PHYMOD_SYMBOL_FIELD_ENCODE(464, 4, 4), 3418 /* CALIB_ADJ:5:7 */ 3419 PHYMOD_SYMBOL_FIELD_ENCODE(133, 7, 5), 3420 /* EN_CMOS_REFCLK_CH_HIZ:8:8 */ 3421 PHYMOD_SYMBOL_FIELD_ENCODE(470, 8, 8), 3422 /* PLL_CLKVCO_CAL_INVERT:9:9 */ 3423 PHYMOD_SYMBOL_FIELD_ENCODE(851, 9, 9), 3424 /* VCOBUF_PON:10:13 */ 3425 PHYMOD_SYMBOL_FIELD_ENCODE(1368, 13, 10), 3426 /* EN_I4IQBUF:14:15 */ 3427 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(478, 15, 14) 3428 }; 3429 static uint32_t BCMI_QTC_XGXS_PLL_CTL3r_fields[] = 3430 { 3431 /* BAND_IQBUF_CTR:0:2 */ 3432 PHYMOD_SYMBOL_FIELD_ENCODE(111, 2, 0), 3433 /* ENB_16T:3:3 */ 3434 PHYMOD_SYMBOL_FIELD_ENCODE(456, 3, 3), 3435 /* EN_TEST_FRAC_CLK:4:4 */ 3436 PHYMOD_SYMBOL_FIELD_ENCODE(491, 4, 4), 3437 /* EN_CML_REFOUT_OVERWR:5:5 */ 3438 PHYMOD_SYMBOL_FIELD_ENCODE(469, 5, 5), 3439 /* EN_CMOS_REFOUT_OVERWR:6:6 */ 3440 PHYMOD_SYMBOL_FIELD_ENCODE(471, 6, 6), 3441 /* EN_RCLK_REFOUT:7:7 */ 3442 PHYMOD_SYMBOL_FIELD_ENCODE(483, 7, 7), 3443 /* PLLCLKSEL:8:8 */ 3444 PHYMOD_SYMBOL_FIELD_ENCODE(846, 8, 8), 3445 /* REF_CML_PD:9:9 */ 3446 PHYMOD_SYMBOL_FIELD_ENCODE(947, 9, 9), 3447 /* REF_CMOS_HZ:10:10 */ 3448 PHYMOD_SYMBOL_FIELD_ENCODE(948, 10, 10), 3449 /* REF_CML_CURX2:11:11 */ 3450 PHYMOD_SYMBOL_FIELD_ENCODE(946, 11, 11), 3451 /* CP_BIAS:12:14 */ 3452 PHYMOD_SYMBOL_FIELD_ENCODE(318, 14, 12), 3453 /* EN_MMD_HALFRATE:15:15 */ 3454 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(479, 15, 15) 3455 }; 3456 static uint32_t BCMI_QTC_XGXS_PLL_CTL4r_fields[] = 3457 { 3458 /* LC_REFCLK_ADJ_3_2:0:1 */ 3459 PHYMOD_SYMBOL_FIELD_ENCODE(564, 1, 0), 3460 /* CP_OPAMP_BIAS:2:3 */ 3461 PHYMOD_SYMBOL_FIELD_ENCODE(319, 3, 2), 3462 /* CMOS_TPORT_EN:4:4 */ 3463 PHYMOD_SYMBOL_FIELD_ENCODE(296, 4, 4), 3464 /* BIAS_VDD_SEL:5:6 */ 3465 PHYMOD_SYMBOL_FIELD_ENCODE(125, 6, 5), 3466 /* VCO_HKVCO:7:7 */ 3467 PHYMOD_SYMBOL_FIELD_ENCODE(1376, 7, 7), 3468 /* BIAS_EN:8:8 */ 3469 PHYMOD_SYMBOL_FIELD_ENCODE(123, 8, 8), 3470 /* VCO_TEST_CLK_EN:9:9 */ 3471 PHYMOD_SYMBOL_FIELD_ENCODE(1383, 9, 9), 3472 /* TEST_AMP:10:11 */ 3473 PHYMOD_SYMBOL_FIELD_ENCODE(1161, 11, 10), 3474 /* TEST_SEL:12:14 */ 3475 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1162, 14, 12) 3476 }; 3477 static uint32_t BCMI_QTC_XGXS_PLL_CTL5r_fields[] = 3478 { 3479 /* REFOUT_DIV_SEL:0:2 */ 3480 PHYMOD_SYMBOL_FIELD_ENCODE(945, 2, 0), 3481 /* TEST_VC:3:3 */ 3482 PHYMOD_SYMBOL_FIELD_ENCODE(1164, 3, 3), 3483 /* TEST_SEL_OVERWRITE:4:4 */ 3484 PHYMOD_SYMBOL_FIELD_ENCODE(1163, 4, 4), 3485 /* TERM_SEL:5:6 */ 3486 PHYMOD_SYMBOL_FIELD_ENCODE(1158, 6, 5), 3487 /* PLL_PWRDN:7:7 */ 3488 PHYMOD_SYMBOL_FIELD_ENCODE(866, 7, 7), 3489 /* EN_REFOUT_DIV:8:8 */ 3490 PHYMOD_SYMBOL_FIELD_ENCODE(485, 8, 8), 3491 /* PWDB_EXTR_D2C:9:9 */ 3492 PHYMOD_SYMBOL_FIELD_ENCODE(927, 9, 9), 3493 /* REFDIV_TEST_SEL:10:12 */ 3494 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(944, 12, 10) 3495 }; 3496 static uint32_t BCMI_QTC_XGXS_PLL_CTL6r_fields[] = 3497 { 3498 /* PLL_PON:0:3 */ 3499 PHYMOD_SYMBOL_FIELD_ENCODE(865, 3, 0), 3500 /* VCO_GM_BOOST:4:5 */ 3501 PHYMOD_SYMBOL_FIELD_ENCODE(1375, 5, 4), 3502 /* VCO_I_BOOST:6:7 */ 3503 PHYMOD_SYMBOL_FIELD_ENCODE(1377, 7, 6), 3504 /* PFD_OFFSET_ENLARGE:8:8 */ 3505 PHYMOD_SYMBOL_FIELD_ENCODE(835, 8, 8), 3506 /* PLL_SPARE6_1:9:9 */ 3507 PHYMOD_SYMBOL_FIELD_ENCODE(871, 9, 9), 3508 /* PFD_OFFSET:10:11 */ 3509 PHYMOD_SYMBOL_FIELD_ENCODE(834, 11, 10), 3510 /* I_NDIV_FRAC_L:12:15 */ 3511 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(545, 15, 12) 3512 }; 3513 static uint32_t BCMI_QTC_XGXS_PLL_CTL7r_fields[] = 3514 { 3515 /* I_NDIV_FRAC_H:0:13 */ 3516 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(544, 13, 0) 3517 }; 3518 static uint32_t BCMI_QTC_XGXS_PLL_CTL8r_fields[] = 3519 { 3520 /* I_NDIV_INT:0:9 */ 3521 PHYMOD_SYMBOL_FIELD_ENCODE(546, 9, 0), 3522 /* CML_REFCLK_BIAS:10:11 */ 3523 PHYMOD_SYMBOL_FIELD_ENCODE(295, 11, 10), 3524 /* VCOFB_DIV:12:13 */ 3525 PHYMOD_SYMBOL_FIELD_ENCODE(1371, 13, 12), 3526 /* I_PLL_SDM_PWRDNB:14:14 */ 3527 PHYMOD_SYMBOL_FIELD_ENCODE(548, 14, 14), 3528 /* I_NDIV_DITHER_EN:15:15 */ 3529 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(543, 15, 15) 3530 }; 3531 static uint32_t BCMI_QTC_XGXS_PLL_CTL9r_fields[] = 3532 { 3533 /* MMD_RESETB:0:0 */ 3534 PHYMOD_SYMBOL_FIELD_ENCODE(767, 0, 0), 3535 /* I_PLL_FRAC_MODE:1:2 */ 3536 PHYMOD_SYMBOL_FIELD_ENCODE(547, 2, 1), 3537 /* SEL_FP3CAP:3:6 */ 3538 PHYMOD_SYMBOL_FIELD_ENCODE(1047, 6, 3), 3539 /* VCO_SUPPLY_ADJ:7:7 */ 3540 PHYMOD_SYMBOL_FIELD_ENCODE(1382, 7, 7), 3541 /* BIAS_DIV_CTRL:8:10 */ 3542 PHYMOD_SYMBOL_FIELD_ENCODE(122, 10, 8), 3543 /* BIAS_IQ_CTRL:11:13 */ 3544 PHYMOD_SYMBOL_FIELD_ENCODE(124, 13, 11), 3545 /* CML_REFCLK_ADJ:14:15 */ 3546 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(294, 15, 14) 3547 }; 3548 static uint32_t BCMI_QTC_XGXS_PLL_CTL_10r_fields[] = 3549 { 3550 /* REFCLK_IN_BIAS:0:5 */ 3551 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(941, 5, 0) 3552 }; 3553 static uint32_t BCMI_QTC_XGXS_PLL_INTr_fields[] = 3554 { 3555 /* REFCLK_DIV4_FRC_VAL:0:0 */ 3556 PHYMOD_SYMBOL_FIELD_ENCODE(939, 0, 0), 3557 /* REFCLK_DIV2_FRC_VAL:1:1 */ 3558 PHYMOD_SYMBOL_FIELD_ENCODE(938, 1, 1), 3559 /* REFCLK_DIV_FRC:2:2 */ 3560 PHYMOD_SYMBOL_FIELD_ENCODE(940, 2, 2), 3561 /* REFCLK_TERM_FRC:3:3 */ 3562 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(943, 3, 3) 3563 }; 3564 static uint32_t BCMI_QTC_XGXS_PLL_STSr_fields[] = 3565 { 3566 /* AFE_REV_ID:0:3 */ 3567 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(2, 3, 0) 3568 }; 3569 static uint32_t BCMI_QTC_XGXS_PMA_CTLr_fields[] = 3570 { 3571 /* RSTB_LANE:0:0 */ 3572 PHYMOD_SYMBOL_FIELD_ENCODE(983, 0, 0), 3573 /* RX_GBOX_AFRST_EN:1:1 */ 3574 PHYMOD_SYMBOL_FIELD_ENCODE(1006, 1, 1), 3575 /* OS_MODE:3:6 */ 3576 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(781, 6, 3) 3577 }; 3578 static uint32_t BCMI_QTC_XGXS_PMD_CORE_MODE_STSr_fields[] = 3579 { 3580 /* PMD_CORE_MODE:0:15 */ 3581 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(877, 15, 0) 3582 }; 3583 static uint32_t BCMI_QTC_XGXS_PMD_X1_CTLr_fields[] = 3584 { 3585 /* CORE_DP_H_RSTB:0:0 */ 3586 PHYMOD_SYMBOL_FIELD_ENCODE(309, 0, 0), 3587 /* POR_H_RSTB:1:1 */ 3588 PHYMOD_SYMBOL_FIELD_ENCODE(900, 1, 1), 3589 /* PRAM_ABILITY:8:8 */ 3590 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(902, 8, 8) 3591 }; 3592 static uint32_t BCMI_QTC_XGXS_PMD_X1_LATCH_STSr_fields[] = 3593 { 3594 /* PLL_LOCK_LL:0:0 */ 3595 PHYMOD_SYMBOL_FIELD_ENCODE(860, 0, 0), 3596 /* PLL_LOCK_LH:1:1 */ 3597 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(859, 1, 1) 3598 }; 3599 static uint32_t BCMI_QTC_XGXS_PMD_X1_MODEr_fields[] = 3600 { 3601 /* CORE_MODE:0:15 */ 3602 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(313, 15, 0) 3603 }; 3604 static uint32_t BCMI_QTC_XGXS_PMD_X1_OVRRr_fields[] = 3605 { 3606 /* PLL_LOCK_OVRD:0:0 */ 3607 PHYMOD_SYMBOL_FIELD_ENCODE(861, 0, 0), 3608 /* CORE_MODE_OEN:1:1 */ 3609 PHYMOD_SYMBOL_FIELD_ENCODE(314, 1, 1), 3610 /* CORE_DP_H_RSTB_OEN:2:2 */ 3611 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(310, 2, 2) 3612 }; 3613 static uint32_t BCMI_QTC_XGXS_PMD_X1_STSr_fields[] = 3614 { 3615 /* PLL_LOCK_STS:0:0 */ 3616 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(862, 0, 0) 3617 }; 3618 static uint32_t BCMI_QTC_XGXS_PMD_X4_CTLr_fields[] = 3619 { 3620 /* LN_RX_DP_H_RSTB:0:0 */ 3621 PHYMOD_SYMBOL_FIELD_ENCODE(600, 0, 0), 3622 /* LN_RX_H_RSTB:1:1 */ 3623 PHYMOD_SYMBOL_FIELD_ENCODE(604, 1, 1), 3624 /* LN_TX_H_PWRDN:2:2 */ 3625 PHYMOD_SYMBOL_FIELD_ENCODE(614, 2, 2), 3626 /* LN_RX_H_PWRDN:3:3 */ 3627 PHYMOD_SYMBOL_FIELD_ENCODE(603, 3, 3), 3628 /* TX_OSR_MODE:4:7 */ 3629 PHYMOD_SYMBOL_FIELD_ENCODE(1291, 7, 4), 3630 /* TX_DISABLE:8:8 */ 3631 PHYMOD_SYMBOL_FIELD_ENCODE(1258, 8, 8), 3632 /* RX_OSR_MODE:9:12 */ 3633 PHYMOD_SYMBOL_FIELD_ENCODE(1022, 12, 9), 3634 /* RX_DME_EN:13:13 */ 3635 PHYMOD_SYMBOL_FIELD_ENCODE(1001, 13, 13), 3636 /* LN_TX_DP_H_RSTB:14:14 */ 3637 PHYMOD_SYMBOL_FIELD_ENCODE(611, 14, 14), 3638 /* LN_TX_H_RSTB:15:15 */ 3639 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(615, 15, 15) 3640 }; 3641 static uint32_t BCMI_QTC_XGXS_PMD_X4_EEE_CTLr_fields[] = 3642 { 3643 /* TX_MODE:0:1 */ 3644 PHYMOD_SYMBOL_FIELD_ENCODE(1287, 1, 0), 3645 /* RX_MODE:2:2 */ 3646 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1019, 2, 2) 3647 }; 3648 static uint32_t BCMI_QTC_XGXS_PMD_X4_EEE_STSr_fields[] = 3649 { 3650 /* ENERGY_DETECT:0:0 */ 3651 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(458, 0, 0) 3652 }; 3653 static uint32_t BCMI_QTC_XGXS_PMD_X4_LATCH_STSr_fields[] = 3654 { 3655 /* RX_LOCK_LL:0:0 */ 3656 PHYMOD_SYMBOL_FIELD_ENCODE(1016, 0, 0), 3657 /* RX_LOCK_LH:1:1 */ 3658 PHYMOD_SYMBOL_FIELD_ENCODE(1015, 1, 1), 3659 /* SIGNAL_DETECT_LL:2:2 */ 3660 PHYMOD_SYMBOL_FIELD_ENCODE(1088, 2, 2), 3661 /* SIGNAL_DETECT_LH:3:3 */ 3662 PHYMOD_SYMBOL_FIELD_ENCODE(1087, 3, 3), 3663 /* RX_CLK_VLD_LL:4:4 */ 3664 PHYMOD_SYMBOL_FIELD_ENCODE(996, 4, 4), 3665 /* RX_CLK_VLD_LH:5:5 */ 3666 PHYMOD_SYMBOL_FIELD_ENCODE(995, 5, 5), 3667 /* TX_CLK_VLD_LL:6:6 */ 3668 PHYMOD_SYMBOL_FIELD_ENCODE(1255, 6, 6), 3669 /* TX_CLK_VLD_LH:7:7 */ 3670 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1254, 7, 7) 3671 }; 3672 static uint32_t BCMI_QTC_XGXS_PMD_X4_MODEr_fields[] = 3673 { 3674 /* LANE_MODE:0:15 */ 3675 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(558, 15, 0) 3676 }; 3677 static uint32_t BCMI_QTC_XGXS_PMD_X4_OVRRr_fields[] = 3678 { 3679 /* RX_LOCK_OVRD:0:0 */ 3680 PHYMOD_SYMBOL_FIELD_ENCODE(1017, 0, 0), 3681 /* SIGNAL_DETECT_OVRD:1:1 */ 3682 PHYMOD_SYMBOL_FIELD_ENCODE(1089, 1, 1), 3683 /* RX_CLK_VLD_OVRD:2:2 */ 3684 PHYMOD_SYMBOL_FIELD_ENCODE(997, 2, 2), 3685 /* LANE_MODE_OEN:3:3 */ 3686 PHYMOD_SYMBOL_FIELD_ENCODE(559, 3, 3), 3687 /* RX_OSR_MODE_OEN:4:4 */ 3688 PHYMOD_SYMBOL_FIELD_ENCODE(1025, 4, 4), 3689 /* RX_DME_EN_OEN:5:5 */ 3690 PHYMOD_SYMBOL_FIELD_ENCODE(1002, 5, 5), 3691 /* TX_DISABLE_OEN:6:6 */ 3692 PHYMOD_SYMBOL_FIELD_ENCODE(1259, 6, 6), 3693 /* LN_RX_DP_H_RSTB_OEN:7:7 */ 3694 PHYMOD_SYMBOL_FIELD_ENCODE(601, 7, 7), 3695 /* TX_CLK_VLD_OVRD:8:8 */ 3696 PHYMOD_SYMBOL_FIELD_ENCODE(1256, 8, 8), 3697 /* TX_OSR_MODE_OEN:9:9 */ 3698 PHYMOD_SYMBOL_FIELD_ENCODE(1294, 9, 9), 3699 /* LN_TX_DP_H_RSTB_OEN:10:10 */ 3700 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(612, 10, 10) 3701 }; 3702 static uint32_t BCMI_QTC_XGXS_PMD_X4_STSr_fields[] = 3703 { 3704 /* RX_LOCK_STS:0:0 */ 3705 PHYMOD_SYMBOL_FIELD_ENCODE(1018, 0, 0), 3706 /* SIGNAL_DETECT_STS:1:1 */ 3707 PHYMOD_SYMBOL_FIELD_ENCODE(1092, 1, 1), 3708 /* RX_CLK_VLD_STS:2:2 */ 3709 PHYMOD_SYMBOL_FIELD_ENCODE(998, 2, 2), 3710 /* TX_CLK_VLD_STS:3:3 */ 3711 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1257, 3, 3) 3712 }; 3713 static uint32_t BCMI_QTC_XGXS_REVID0r_fields[] = 3714 { 3715 /* REVID_MODEL:0:5 */ 3716 PHYMOD_SYMBOL_FIELD_ENCODE(969, 5, 0), 3717 /* REVID_PROCESS:6:8 */ 3718 PHYMOD_SYMBOL_FIELD_ENCODE(972, 8, 6), 3719 /* REVID_BONDING:9:10 */ 3720 PHYMOD_SYMBOL_FIELD_ENCODE(963, 10, 9), 3721 /* REVID_REV_NUMBER:11:13 */ 3722 PHYMOD_SYMBOL_FIELD_ENCODE(974, 13, 11), 3723 /* REVID_REV_LETTER:14:15 */ 3724 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(973, 15, 14) 3725 }; 3726 static uint32_t BCMI_QTC_XGXS_REVID1r_fields[] = 3727 { 3728 /* REVID_EEE:0:0 */ 3729 PHYMOD_SYMBOL_FIELD_ENCODE(965, 0, 0), 3730 /* REVID_LLP:1:1 */ 3731 PHYMOD_SYMBOL_FIELD_ENCODE(966, 1, 1), 3732 /* REVID_PIR:2:2 */ 3733 PHYMOD_SYMBOL_FIELD_ENCODE(971, 2, 2), 3734 /* REVID_CL72:3:3 */ 3735 PHYMOD_SYMBOL_FIELD_ENCODE(964, 3, 3), 3736 /* REVID_MICRO:4:4 */ 3737 PHYMOD_SYMBOL_FIELD_ENCODE(968, 4, 4), 3738 /* REVID_MDIO:5:5 */ 3739 PHYMOD_SYMBOL_FIELD_ENCODE(967, 5, 5), 3740 /* REVID_MULTIPLICITY:12:15 */ 3741 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(970, 15, 12) 3742 }; 3743 static uint32_t BCMI_QTC_XGXS_REVID2r_fields[] = 3744 { 3745 /* REVID2:0:3 */ 3746 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(962, 3, 0) 3747 }; 3748 static uint32_t BCMI_QTC_XGXS_RST_CTL_CORE_DPr_fields[] = 3749 { 3750 /* PMD_CORE_DP_H_RSTB_PKILL:1:1 */ 3751 PHYMOD_SYMBOL_FIELD_ENCODE(876, 1, 1), 3752 /* SUP_RST_SEQ_FRC_VAL:3:3 */ 3753 PHYMOD_SYMBOL_FIELD_ENCODE(1113, 3, 3), 3754 /* SUP_RST_SEQ_FRC:4:4 */ 3755 PHYMOD_SYMBOL_FIELD_ENCODE(1112, 4, 4), 3756 /* PMD_MDIO_TRANS_PKILL:5:5 */ 3757 PHYMOD_SYMBOL_FIELD_ENCODE(889, 5, 5), 3758 /* VCOCLK16_S_COMCLK_SEL:7:7 */ 3759 PHYMOD_SYMBOL_FIELD_ENCODE(1370, 7, 7), 3760 /* VCOCLK16_S_COMCLK_FRC_ON:8:8 */ 3761 PHYMOD_SYMBOL_FIELD_ENCODE(1369, 8, 8), 3762 /* PMD_VCOCLK16_VLD_FRC:9:9 */ 3763 PHYMOD_SYMBOL_FIELD_ENCODE(898, 9, 9), 3764 /* PMD_VCOCLK16_VLD_FRC_VAL:10:10 */ 3765 PHYMOD_SYMBOL_FIELD_ENCODE(899, 10, 10), 3766 /* DISABLE_ACK_TIMEOUT:15:15 */ 3767 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(416, 15, 15) 3768 }; 3769 static uint32_t BCMI_QTC_XGXS_RST_CTL_PMDr_fields[] = 3770 { 3771 /* CORE_S_RSTB:0:0 */ 3772 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(316, 0, 0) 3773 }; 3774 static uint32_t BCMI_QTC_XGXS_RST_SEQ_TMR_CTLr_fields[] = 3775 { 3776 /* RST_SEQ_TIMER:0:2 */ 3777 PHYMOD_SYMBOL_FIELD_ENCODE(986, 2, 0), 3778 /* PWRDN_SEQ_TIMER:9:11 */ 3779 PHYMOD_SYMBOL_FIELD_ENCODE(928, 11, 9), 3780 /* RST_SEQ_DIS_FLT_MODE:14:15 */ 3781 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(985, 15, 14) 3782 }; 3783 static uint32_t BCMI_QTC_XGXS_RXCOM_AFE_RST_PWRDN_OSR_MODE_PIN_STSr_fields[] = 3784 { 3785 /* RX_OSR_MODE_PIN:0:3 */ 3786 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1026, 3, 0) 3787 }; 3788 static uint32_t BCMI_QTC_XGXS_RXCOM_LN_CLK_RST_N_PWRDWN_CTLr_fields[] = 3789 { 3790 /* RX_LN_DP_S_RSTB:0:0 */ 3791 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1013, 0, 0) 3792 }; 3793 static uint32_t BCMI_QTC_XGXS_RXCOM_LN_DP_RST_ST_STSr_fields[] = 3794 { 3795 /* RX_LANE_DP_RESET_STATE:0:2 */ 3796 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1011, 2, 0) 3797 }; 3798 static uint32_t BCMI_QTC_XGXS_RXCOM_LN_RST_N_PWRDN_PIN_KILL_CTLr_fields[] = 3799 { 3800 /* PMD_LN_RX_H_RSTB_PKILL:0:0 */ 3801 PHYMOD_SYMBOL_FIELD_ENCODE(883, 0, 0), 3802 /* PMD_LN_RX_DP_H_RSTB_PKILL:1:1 */ 3803 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(881, 1, 1) 3804 }; 3805 static uint32_t BCMI_QTC_XGXS_RXCOM_LN_RST_OCC_CTLr_fields[] = 3806 { 3807 /* RX_LANE_REG_RESET_OCCURRED:0:0 */ 3808 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1012, 0, 0) 3809 }; 3810 static uint32_t BCMI_QTC_XGXS_RXCOM_LN_S_RSTB_CTLr_fields[] = 3811 { 3812 /* RX_LN_S_RSTB:0:0 */ 3813 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1014, 0, 0) 3814 }; 3815 static uint32_t BCMI_QTC_XGXS_RXCOM_MCST_MASK_CTLr_fields[] = 3816 { 3817 /* RX_MULTICAST_MASK_CONTROL:0:0 */ 3818 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1020, 0, 0) 3819 }; 3820 static uint32_t BCMI_QTC_XGXS_RXCOM_OSR_MODE_CTLr_fields[] = 3821 { 3822 /* RX_OSR_MODE_FRC_VAL:0:3 */ 3823 PHYMOD_SYMBOL_FIELD_ENCODE(1024, 3, 0), 3824 /* RX_OSR_MODE_FRC:15:15 */ 3825 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1023, 15, 15) 3826 }; 3827 static uint32_t BCMI_QTC_XGXS_RXCOM_OSR_MODE_STS_MC_MASKr_fields[] = 3828 { 3829 /* RX_OSR_MODE:0:3 */ 3830 PHYMOD_SYMBOL_FIELD_ENCODE(1022, 3, 0), 3831 /* RX_MULTICAST_MASK_CONTROL_STATUS:4:4 */ 3832 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1021, 4, 4) 3833 }; 3834 static uint32_t BCMI_QTC_XGXS_RXCOM_UC_ACK_LN_CTLr_fields[] = 3835 { 3836 /* RX_UC_ACK_LANE_CFG_DONE:0:0 */ 3837 PHYMOD_SYMBOL_FIELD_ENCODE(1039, 0, 0), 3838 /* RX_UC_ACK_LANE_DP_RESET:1:1 */ 3839 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1040, 1, 1) 3840 }; 3841 static uint32_t BCMI_QTC_XGXS_RXTXCOM_AFE_RST_PWRDN_OSR_MODE_PIN_STSr_fields[] = 3842 { 3843 /* OSR_MODE_PIN:0:3 */ 3844 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(779, 3, 0) 3845 }; 3846 static uint32_t BCMI_QTC_XGXS_RXTXCOM_LN_CLK_RST_N_PWRDWN_CTLr_fields[] = 3847 { 3848 /* LN_DP_S_RSTB:0:0 */ 3849 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(599, 0, 0) 3850 }; 3851 static uint32_t BCMI_QTC_XGXS_RXTXCOM_LN_DP_RST_ST_STSr_fields[] = 3852 { 3853 /* LANE_DP_RESET_STATE:0:2 */ 3854 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(557, 2, 0) 3855 }; 3856 static uint32_t BCMI_QTC_XGXS_RXTXCOM_LN_RST_N_PWRDN_PIN_KILL_CTLr_fields[] = 3857 { 3858 /* PMD_LN_H_RSTB_PKILL:0:0 */ 3859 PHYMOD_SYMBOL_FIELD_ENCODE(880, 0, 0), 3860 /* PMD_LN_DP_H_RSTB_PKILL:1:1 */ 3861 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(879, 1, 1) 3862 }; 3863 static uint32_t BCMI_QTC_XGXS_RXTXCOM_LN_RST_OCC_CTLr_fields[] = 3864 { 3865 /* LANE_REG_RESET_OCCURRED:0:0 */ 3866 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(560, 0, 0) 3867 }; 3868 static uint32_t BCMI_QTC_XGXS_RXTXCOM_LN_S_RSTB_CTLr_fields[] = 3869 { 3870 /* LN_S_RSTB:0:0 */ 3871 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(610, 0, 0) 3872 }; 3873 static uint32_t BCMI_QTC_XGXS_RXTXCOM_MCST_MASK_CTLr_fields[] = 3874 { 3875 /* MULTICAST_MASK_CONTROL:0:0 */ 3876 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(769, 0, 0) 3877 }; 3878 static uint32_t BCMI_QTC_XGXS_RXTXCOM_OSR_MODE_CTLr_fields[] = 3879 { 3880 /* OSR_MODE_FRC_VAL:0:3 */ 3881 PHYMOD_SYMBOL_FIELD_ENCODE(778, 3, 0), 3882 /* OSR_MODE_FRC:15:15 */ 3883 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(777, 15, 15) 3884 }; 3885 static uint32_t BCMI_QTC_XGXS_RXTXCOM_OSR_MODE_STS_MC_MASKr_fields[] = 3886 { 3887 /* OSR_MODE:0:3 */ 3888 PHYMOD_SYMBOL_FIELD_ENCODE(776, 3, 0), 3889 /* MULTICAST_MASK_CONTROL_STATUS:4:4 */ 3890 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(770, 4, 4) 3891 }; 3892 static uint32_t BCMI_QTC_XGXS_RXTXCOM_UC_ACK_LN_CTLr_fields[] = 3893 { 3894 /* UC_ACK_LANE_CFG_DONE:0:0 */ 3895 PHYMOD_SYMBOL_FIELD_ENCODE(1347, 0, 0), 3896 /* UC_ACK_LANE_DP_RESET:1:1 */ 3897 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1348, 1, 1) 3898 }; 3899 static uint32_t BCMI_QTC_XGXS_RX_AFE_RST_PWRDN_OSR_MODE_PIN_STSr_fields[] = 3900 { 3901 /* AFE_RX_PWRDN:0:0 */ 3902 PHYMOD_SYMBOL_FIELD_ENCODE(3, 0, 0), 3903 /* AFE_RX_RESET:1:1 */ 3904 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(6, 1, 1) 3905 }; 3906 static uint32_t BCMI_QTC_XGXS_RX_CLK_N_RST_DBG_CTLr_fields[] = 3907 { 3908 /* LN_RX_S_CLKGATE_FRC_ON:0:0 */ 3909 PHYMOD_SYMBOL_FIELD_ENCODE(605, 0, 0), 3910 /* LN_RX_S_COMCLK_SEL:1:1 */ 3911 PHYMOD_SYMBOL_FIELD_ENCODE(607, 1, 1), 3912 /* LN_RX_S_COMCLK_FRC_ON:2:2 */ 3913 PHYMOD_SYMBOL_FIELD_ENCODE(606, 2, 2), 3914 /* PMD_RX_CLK_VLD_FRC:3:3 */ 3915 PHYMOD_SYMBOL_FIELD_ENCODE(890, 3, 3), 3916 /* PMD_RX_CLK_VLD_FRC_VAL:4:4 */ 3917 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(891, 4, 4) 3918 }; 3919 static uint32_t BCMI_QTC_XGXS_RX_LN_AFE_RST_PWRDWN_CTL_CTLr_fields[] = 3920 { 3921 /* AFE_RX_PWRDN_FRC:0:0 */ 3922 PHYMOD_SYMBOL_FIELD_ENCODE(4, 0, 0), 3923 /* AFE_RX_PWRDN_FRC_VAL:1:1 */ 3924 PHYMOD_SYMBOL_FIELD_ENCODE(5, 1, 1), 3925 /* AFE_RX_RESET_FRC:2:2 */ 3926 PHYMOD_SYMBOL_FIELD_ENCODE(7, 2, 2), 3927 /* AFE_RX_RESET_FRC_VAL:3:3 */ 3928 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(8, 3, 3) 3929 }; 3930 static uint32_t BCMI_QTC_XGXS_RX_LN_CLK_RST_N_PWRDWN_CTLr_fields[] = 3931 { 3932 /* LN_RX_S_PWRDN:0:0 */ 3933 PHYMOD_SYMBOL_FIELD_ENCODE(608, 0, 0), 3934 /* AFE_SIGDET_PWRDN:1:1 */ 3935 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(11, 1, 1) 3936 }; 3937 static uint32_t BCMI_QTC_XGXS_RX_LN_DBG_RST_CTLr_fields[] = 3938 { 3939 /* LN_RX_S_RSTB:0:0 */ 3940 PHYMOD_SYMBOL_FIELD_ENCODE(609, 0, 0), 3941 /* LN_RX_DP_S_RSTB:1:1 */ 3942 PHYMOD_SYMBOL_FIELD_ENCODE(602, 1, 1), 3943 /* SIGDET_DP_RSTB_EN:2:2 */ 3944 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1076, 2, 2) 3945 }; 3946 static uint32_t BCMI_QTC_XGXS_RX_LN_RST_N_PWRDN_PIN_KILL_CTLr_fields[] = 3947 { 3948 /* PMD_LN_RX_H_PWRDN_PKILL:0:0 */ 3949 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(882, 0, 0) 3950 }; 3951 static uint32_t BCMI_QTC_XGXS_RX_PMD_LN_MODE_STSr_fields[] = 3952 { 3953 /* PMD_LANE_MODE:0:15 */ 3954 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(878, 15, 0) 3955 }; 3956 static uint32_t BCMI_QTC_XGXS_RX_X4_CL49_CTL0_DEC_CTL0r_fields[] = 3957 { 3958 /* CL49_RX_RF_ENABLE:0:0 */ 3959 PHYMOD_SYMBOL_FIELD_ENCODE(217, 0, 0), 3960 /* CL49_RX_LF_ENABLE:1:1 */ 3961 PHYMOD_SYMBOL_FIELD_ENCODE(216, 1, 1), 3962 /* LPI_ENABLE:2:2 */ 3963 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(642, 2, 2) 3964 }; 3965 static uint32_t BCMI_QTC_XGXS_RX_X4_CL49_CTL0_PCS_CTL0r_fields[] = 3966 { 3967 /* DISABLE_CL49_BERMON:0:0 */ 3968 PHYMOD_SYMBOL_FIELD_ENCODE(418, 0, 0), 3969 /* BER_WINDOW_512:1:1 */ 3970 PHYMOD_SYMBOL_FIELD_ENCODE(121, 1, 1), 3971 /* CL49_BER_LIMIT:2:7 */ 3972 PHYMOD_SYMBOL_FIELD_ENCODE(203, 7, 2), 3973 /* DESCRAMBLERMODE:15:15 */ 3974 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(350, 15, 15) 3975 }; 3976 static uint32_t BCMI_QTC_XGXS_RX_X4_CL49_STS0_AM_LOCK_STSr_fields[] = 3977 { 3978 /* AM_LOCK_CURRENT_STATE:0:3 */ 3979 PHYMOD_SYMBOL_FIELD_ENCODE(37, 3, 0), 3980 /* AM_LOCK_HISTORY_STATE:4:13 */ 3981 PHYMOD_SYMBOL_FIELD_ENCODE(38, 13, 4), 3982 /* AM_SEQUENCE_ERR:14:14 */ 3983 PHYMOD_SYMBOL_FIELD_ENCODE(41, 14, 14), 3984 /* AM_SPACING_ERR:15:15 */ 3985 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(42, 15, 15) 3986 }; 3987 static uint32_t BCMI_QTC_XGXS_RX_X4_CL49_STS0_BARREL_SHIFTER_STr_fields[] = 3988 { 3989 /* SHIFT_AMOUNT:0:7 */ 3990 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1059, 7, 0) 3991 }; 3992 static uint32_t BCMI_QTC_XGXS_RX_X4_CL49_STS0_BERCNTr_fields[] = 3993 { 3994 /* BER_COUNT:0:5 */ 3995 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(116, 5, 0) 3996 }; 3997 static uint32_t BCMI_QTC_XGXS_RX_X4_CL49_STS0_BERMON_STSr_fields[] = 3998 { 3999 /* BERMON_CURRENT_STATE:0:4 */ 4000 PHYMOD_SYMBOL_FIELD_ENCODE(114, 4, 0), 4001 /* BERMON_HISTORY_STATE:5:9 */ 4002 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(115, 9, 5) 4003 }; 4004 static uint32_t BCMI_QTC_XGXS_RX_X4_CL49_STS0_DEC_ERRED_BLKS_SP01r_fields[] = 4005 { 4006 /* CL49IEEE_ERRORED_BLOCKS_SP0:0:7 */ 4007 PHYMOD_SYMBOL_FIELD_ENCODE(199, 7, 0), 4008 /* CL49IEEE_ERRORED_BLOCKS_SP1:8:15 */ 4009 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(200, 15, 8) 4010 }; 4011 static uint32_t BCMI_QTC_XGXS_RX_X4_CL49_STS0_DEC_ERRED_BLKS_SP23r_fields[] = 4012 { 4013 /* CL49IEEE_ERRORED_BLOCKS_SP2:0:7 */ 4014 PHYMOD_SYMBOL_FIELD_ENCODE(201, 7, 0), 4015 /* CL49IEEE_ERRORED_BLOCKS_SP3:8:15 */ 4016 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(202, 15, 8) 4017 }; 4018 static uint32_t BCMI_QTC_XGXS_RX_X4_CL49_STS0_DEC_STS_SP0r_fields[] = 4019 { 4020 /* CL49_RXSM_CURRENT_STATE_SP0:0:2 */ 4021 PHYMOD_SYMBOL_FIELD_ENCODE(208, 2, 0), 4022 /* CL49_RXSM_HISTORY_STATE_SP0:3:10 */ 4023 PHYMOD_SYMBOL_FIELD_ENCODE(212, 10, 3), 4024 /* CL49_R_TYPE_CODED_SP0:12:15 */ 4025 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(218, 15, 12) 4026 }; 4027 static uint32_t BCMI_QTC_XGXS_RX_X4_CL49_STS0_DEC_STS_SP1r_fields[] = 4028 { 4029 /* CL49_RXSM_CURRENT_STATE_SP1:0:2 */ 4030 PHYMOD_SYMBOL_FIELD_ENCODE(209, 2, 0), 4031 /* CL49_RXSM_HISTORY_STATE_SP1:3:10 */ 4032 PHYMOD_SYMBOL_FIELD_ENCODE(213, 10, 3), 4033 /* CL49_R_TYPE_CODED_SP1:12:15 */ 4034 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(219, 15, 12) 4035 }; 4036 static uint32_t BCMI_QTC_XGXS_RX_X4_CL49_STS0_DEC_STS_SP2r_fields[] = 4037 { 4038 /* CL49_RXSM_CURRENT_STATE_SP2:0:2 */ 4039 PHYMOD_SYMBOL_FIELD_ENCODE(210, 2, 0), 4040 /* CL49_RXSM_HISTORY_STATE_SP2:3:10 */ 4041 PHYMOD_SYMBOL_FIELD_ENCODE(214, 10, 3), 4042 /* CL49_R_TYPE_CODED_SP2:12:15 */ 4043 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(220, 15, 12) 4044 }; 4045 static uint32_t BCMI_QTC_XGXS_RX_X4_CL49_STS0_DEC_STS_SP3r_fields[] = 4046 { 4047 /* CL49_RXSM_CURRENT_STATE_SP3:0:2 */ 4048 PHYMOD_SYMBOL_FIELD_ENCODE(211, 2, 0), 4049 /* CL49_RXSM_HISTORY_STATE_SP3:3:10 */ 4050 PHYMOD_SYMBOL_FIELD_ENCODE(215, 10, 3), 4051 /* CL49_R_TYPE_CODED_SP3:12:15 */ 4052 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(221, 15, 12) 4053 }; 4054 static uint32_t BCMI_QTC_XGXS_RX_X4_CL49_STS0_PCS_LATCH_STS0r_fields[] = 4055 { 4056 /* HI_BER_LL:0:0 */ 4057 PHYMOD_SYMBOL_FIELD_ENCODE(517, 0, 0), 4058 /* HI_BER_LH:1:1 */ 4059 PHYMOD_SYMBOL_FIELD_ENCODE(516, 1, 1), 4060 /* AM_LOCK_LL:2:2 */ 4061 PHYMOD_SYMBOL_FIELD_ENCODE(40, 2, 2), 4062 /* AM_LOCK_LH:3:3 */ 4063 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(39, 3, 3) 4064 }; 4065 static uint32_t BCMI_QTC_XGXS_RX_X4_CL49_STS0_PCS_LATCH_STS1r_fields[] = 4066 { 4067 /* RESERVED_ORDERED_SET_LH:0:3 */ 4068 PHYMOD_SYMBOL_FIELD_ENCODE(958, 3, 0), 4069 /* LPI_RECEIVED_LH:4:7 */ 4070 PHYMOD_SYMBOL_FIELD_ENCODE(644, 7, 4), 4071 /* REMOTE_FAULT_LH:8:11 */ 4072 PHYMOD_SYMBOL_FIELD_ENCODE(953, 11, 8), 4073 /* LOCAL_FAULT_LH:12:15 */ 4074 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(622, 15, 12) 4075 }; 4076 static uint32_t BCMI_QTC_XGXS_RX_X4_CL49_STS0_PCS_LIVE_STSr_fields[] = 4077 { 4078 /* HI_BER:0:0 */ 4079 PHYMOD_SYMBOL_FIELD_ENCODE(515, 0, 0), 4080 /* AM_LOCK:1:1 */ 4081 PHYMOD_SYMBOL_FIELD_ENCODE(36, 1, 1), 4082 /* LPI_RECEIVED:4:7 */ 4083 PHYMOD_SYMBOL_FIELD_ENCODE(643, 7, 4), 4084 /* REMOTE_FAULT:8:11 */ 4085 PHYMOD_SYMBOL_FIELD_ENCODE(951, 11, 8), 4086 /* LOCAL_FAULT:12:15 */ 4087 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(621, 15, 12) 4088 }; 4089 static uint32_t BCMI_QTC_XGXS_RX_X4_CL49_STS0_SYNC_FSM_STSr_fields[] = 4090 { 4091 /* LOCK_CURRENT_STATE:0:1 */ 4092 PHYMOD_SYMBOL_FIELD_ENCODE(624, 1, 0), 4093 /* LOCK_HISTORY_STATE:2:4 */ 4094 PHYMOD_SYMBOL_FIELD_ENCODE(625, 4, 2), 4095 /* BLOCK_LOCK:13:13 */ 4096 PHYMOD_SYMBOL_FIELD_ENCODE(126, 13, 13), 4097 /* BLOCK_LOCK_LL:14:14 */ 4098 PHYMOD_SYMBOL_FIELD_ENCODE(128, 14, 14), 4099 /* BLOCK_LOCK_LH:15:15 */ 4100 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(127, 15, 15) 4101 }; 4102 static uint32_t BCMI_QTC_XGXS_SC_X1_PIPE_RST_CNTr_fields[] = 4103 { 4104 /* PIPELINE_RESET_COUNT:0:15 */ 4105 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(842, 15, 0) 4106 }; 4107 static uint32_t BCMI_QTC_XGXS_SC_X1_PLL_LOCK_TMRr_fields[] = 4108 { 4109 /* PLL_LOCK_TIMER_PERIOD:0:15 */ 4110 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(864, 15, 0) 4111 }; 4112 static uint32_t BCMI_QTC_XGXS_SC_X1_PMD_LOCK_TMRr_fields[] = 4113 { 4114 /* PMD_LOCK_TIMER_PERIOD:0:15 */ 4115 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(888, 15, 0) 4116 }; 4117 static uint32_t BCMI_QTC_XGXS_SC_X1_SPD_OVRR0_0r_fields[] = 4118 { 4119 /* OS_MODE:0:3 */ 4120 PHYMOD_SYMBOL_FIELD_ENCODE(781, 3, 0), 4121 /* CL36BYTEDELETEMODE:4:5 */ 4122 PHYMOD_SYMBOL_FIELD_ENCODE(168, 5, 4), 4123 /* QSGMII_EN:6:6 */ 4124 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(929, 6, 6) 4125 }; 4126 static uint32_t BCMI_QTC_XGXS_SC_X1_SPD_OVRR0_1r_fields[] = 4127 { 4128 /* CLOCKCNT0:0:13 */ 4129 PHYMOD_SYMBOL_FIELD_ENCODE(289, 13, 0), 4130 /* SGMII_SPD_SWITCH:15:15 */ 4131 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1053, 15, 15) 4132 }; 4133 static uint32_t BCMI_QTC_XGXS_SC_X1_SPD_OVRR0_2r_fields[] = 4134 { 4135 /* CLOCKCNT1:0:7 */ 4136 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(291, 7, 0) 4137 }; 4138 static uint32_t BCMI_QTC_XGXS_SC_X1_SPD_OVRR0_3r_fields[] = 4139 { 4140 /* LOOPCNT1:0:5 */ 4141 PHYMOD_SYMBOL_FIELD_ENCODE(636, 5, 0), 4142 /* LOOPCNT0:6:13 */ 4143 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(634, 13, 6) 4144 }; 4145 static uint32_t BCMI_QTC_XGXS_SC_X1_SPD_OVRR0_4r_fields[] = 4146 { 4147 /* MAC_CREDITGENCNT:0:12 */ 4148 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(665, 12, 0) 4149 }; 4150 static uint32_t BCMI_QTC_XGXS_SC_X1_SPD_OVRR0_5r_fields[] = 4151 { 4152 /* PCS_CLOCKCNT0:0:13 */ 4153 PHYMOD_SYMBOL_FIELD_ENCODE(820, 13, 0), 4154 /* PCS_CREDITENABLE:14:14 */ 4155 PHYMOD_SYMBOL_FIELD_ENCODE(822, 14, 14), 4156 /* REPLICATION_CNT:15:15 */ 4157 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(955, 15, 15) 4158 }; 4159 static uint32_t BCMI_QTC_XGXS_SC_X1_SPD_OVRR0_6r_fields[] = 4160 { 4161 /* PCS_CREDITGENCNT:0:12 */ 4162 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(824, 12, 0) 4163 }; 4164 static uint32_t BCMI_QTC_XGXS_SC_X1_SPD_OVRR0_SPDr_fields[] = 4165 { 4166 /* SPEED:0:7 */ 4167 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1102, 7, 0) 4168 }; 4169 static uint32_t BCMI_QTC_XGXS_SC_X1_SPD_OVRR1_0r_fields[] = 4170 { 4171 /* OS_MODE:0:3 */ 4172 PHYMOD_SYMBOL_FIELD_ENCODE(781, 3, 0), 4173 /* CL36BYTEDELETEMODE:4:5 */ 4174 PHYMOD_SYMBOL_FIELD_ENCODE(168, 5, 4), 4175 /* QSGMII_EN:6:6 */ 4176 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(929, 6, 6) 4177 }; 4178 static uint32_t BCMI_QTC_XGXS_SC_X1_SPD_OVRR1_1r_fields[] = 4179 { 4180 /* CLOCKCNT0:0:13 */ 4181 PHYMOD_SYMBOL_FIELD_ENCODE(289, 13, 0), 4182 /* SGMII_SPD_SWITCH:15:15 */ 4183 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1053, 15, 15) 4184 }; 4185 static uint32_t BCMI_QTC_XGXS_SC_X1_SPD_OVRR1_2r_fields[] = 4186 { 4187 /* CLOCKCNT1:0:7 */ 4188 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(291, 7, 0) 4189 }; 4190 static uint32_t BCMI_QTC_XGXS_SC_X1_SPD_OVRR1_3r_fields[] = 4191 { 4192 /* LOOPCNT1:0:5 */ 4193 PHYMOD_SYMBOL_FIELD_ENCODE(636, 5, 0), 4194 /* LOOPCNT0:6:13 */ 4195 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(634, 13, 6) 4196 }; 4197 static uint32_t BCMI_QTC_XGXS_SC_X1_SPD_OVRR1_4r_fields[] = 4198 { 4199 /* MAC_CREDITGENCNT:0:12 */ 4200 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(665, 12, 0) 4201 }; 4202 static uint32_t BCMI_QTC_XGXS_SC_X1_SPD_OVRR1_5r_fields[] = 4203 { 4204 /* PCS_CLOCKCNT0:0:13 */ 4205 PHYMOD_SYMBOL_FIELD_ENCODE(820, 13, 0), 4206 /* PCS_CREDITENABLE:14:14 */ 4207 PHYMOD_SYMBOL_FIELD_ENCODE(822, 14, 14), 4208 /* REPLICATION_CNT:15:15 */ 4209 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(955, 15, 15) 4210 }; 4211 static uint32_t BCMI_QTC_XGXS_SC_X1_SPD_OVRR1_6r_fields[] = 4212 { 4213 /* PCS_CREDITGENCNT:0:12 */ 4214 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(824, 12, 0) 4215 }; 4216 static uint32_t BCMI_QTC_XGXS_SC_X1_SPD_OVRR1_SPDr_fields[] = 4217 { 4218 /* SPEED:0:7 */ 4219 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1102, 7, 0) 4220 }; 4221 static uint32_t BCMI_QTC_XGXS_SC_X1_SPD_OVRR2_0r_fields[] = 4222 { 4223 /* OS_MODE:0:3 */ 4224 PHYMOD_SYMBOL_FIELD_ENCODE(781, 3, 0), 4225 /* CL36BYTEDELETEMODE:4:5 */ 4226 PHYMOD_SYMBOL_FIELD_ENCODE(168, 5, 4), 4227 /* QSGMII_EN:6:6 */ 4228 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(929, 6, 6) 4229 }; 4230 static uint32_t BCMI_QTC_XGXS_SC_X1_SPD_OVRR2_1r_fields[] = 4231 { 4232 /* CLOCKCNT0:0:13 */ 4233 PHYMOD_SYMBOL_FIELD_ENCODE(289, 13, 0), 4234 /* SGMII_SPD_SWITCH:15:15 */ 4235 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1053, 15, 15) 4236 }; 4237 static uint32_t BCMI_QTC_XGXS_SC_X1_SPD_OVRR2_2r_fields[] = 4238 { 4239 /* CLOCKCNT1:0:7 */ 4240 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(291, 7, 0) 4241 }; 4242 static uint32_t BCMI_QTC_XGXS_SC_X1_SPD_OVRR2_3r_fields[] = 4243 { 4244 /* LOOPCNT1:0:5 */ 4245 PHYMOD_SYMBOL_FIELD_ENCODE(636, 5, 0), 4246 /* LOOPCNT0:6:13 */ 4247 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(634, 13, 6) 4248 }; 4249 static uint32_t BCMI_QTC_XGXS_SC_X1_SPD_OVRR2_4r_fields[] = 4250 { 4251 /* MAC_CREDITGENCNT:0:12 */ 4252 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(665, 12, 0) 4253 }; 4254 static uint32_t BCMI_QTC_XGXS_SC_X1_SPD_OVRR2_5r_fields[] = 4255 { 4256 /* PCS_CLOCKCNT0:0:13 */ 4257 PHYMOD_SYMBOL_FIELD_ENCODE(820, 13, 0), 4258 /* PCS_CREDITENABLE:14:14 */ 4259 PHYMOD_SYMBOL_FIELD_ENCODE(822, 14, 14), 4260 /* REPLICATION_CNT:15:15 */ 4261 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(955, 15, 15) 4262 }; 4263 static uint32_t BCMI_QTC_XGXS_SC_X1_SPD_OVRR2_6r_fields[] = 4264 { 4265 /* PCS_CREDITGENCNT:0:12 */ 4266 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(824, 12, 0) 4267 }; 4268 static uint32_t BCMI_QTC_XGXS_SC_X1_SPD_OVRR2_SPDr_fields[] = 4269 { 4270 /* SPEED:0:7 */ 4271 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1102, 7, 0) 4272 }; 4273 static uint32_t BCMI_QTC_XGXS_SC_X1_SPD_OVRR3_0r_fields[] = 4274 { 4275 /* OS_MODE:0:3 */ 4276 PHYMOD_SYMBOL_FIELD_ENCODE(781, 3, 0), 4277 /* CL36BYTEDELETEMODE:4:5 */ 4278 PHYMOD_SYMBOL_FIELD_ENCODE(168, 5, 4), 4279 /* QSGMII_EN:6:6 */ 4280 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(929, 6, 6) 4281 }; 4282 static uint32_t BCMI_QTC_XGXS_SC_X1_SPD_OVRR3_1r_fields[] = 4283 { 4284 /* CLOCKCNT0:0:13 */ 4285 PHYMOD_SYMBOL_FIELD_ENCODE(289, 13, 0), 4286 /* SGMII_SPD_SWITCH:15:15 */ 4287 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1053, 15, 15) 4288 }; 4289 static uint32_t BCMI_QTC_XGXS_SC_X1_SPD_OVRR3_2r_fields[] = 4290 { 4291 /* CLOCKCNT1:0:7 */ 4292 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(291, 7, 0) 4293 }; 4294 static uint32_t BCMI_QTC_XGXS_SC_X1_SPD_OVRR3_3r_fields[] = 4295 { 4296 /* LOOPCNT1:0:5 */ 4297 PHYMOD_SYMBOL_FIELD_ENCODE(636, 5, 0), 4298 /* LOOPCNT0:6:13 */ 4299 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(634, 13, 6) 4300 }; 4301 static uint32_t BCMI_QTC_XGXS_SC_X1_SPD_OVRR3_4r_fields[] = 4302 { 4303 /* MAC_CREDITGENCNT:0:12 */ 4304 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(665, 12, 0) 4305 }; 4306 static uint32_t BCMI_QTC_XGXS_SC_X1_SPD_OVRR3_5r_fields[] = 4307 { 4308 /* PCS_CLOCKCNT0:0:13 */ 4309 PHYMOD_SYMBOL_FIELD_ENCODE(820, 13, 0), 4310 /* PCS_CREDITENABLE:14:14 */ 4311 PHYMOD_SYMBOL_FIELD_ENCODE(822, 14, 14), 4312 /* REPLICATION_CNT:15:15 */ 4313 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(955, 15, 15) 4314 }; 4315 static uint32_t BCMI_QTC_XGXS_SC_X1_SPD_OVRR3_6r_fields[] = 4316 { 4317 /* PCS_CREDITGENCNT:0:12 */ 4318 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(824, 12, 0) 4319 }; 4320 static uint32_t BCMI_QTC_XGXS_SC_X1_SPD_OVRR3_SPDr_fields[] = 4321 { 4322 /* SPEED:0:7 */ 4323 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1102, 7, 0) 4324 }; 4325 static uint32_t BCMI_QTC_XGXS_SC_X1_TX_RST_CNTr_fields[] = 4326 { 4327 /* TX_RESET_COUNT:0:15 */ 4328 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1339, 15, 0) 4329 }; 4330 static uint32_t BCMI_QTC_XGXS_SC_X4_BYPASSr_fields[] = 4331 { 4332 /* SC_BYPASS:0:0 */ 4333 PHYMOD_SYMBOL_FIELD_ENCODE(1042, 0, 0), 4334 /* SC_IGNORE_TX_DATA_VLD:1:1 */ 4335 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1044, 1, 1) 4336 }; 4337 static uint32_t BCMI_QTC_XGXS_SC_X4_CTLr_fields[] = 4338 { 4339 /* SW_SPEED:0:7 */ 4340 PHYMOD_SYMBOL_FIELD_ENCODE(1118, 7, 0), 4341 /* SW_SPEED_CHANGE:8:8 */ 4342 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1119, 8, 8) 4343 }; 4344 static uint32_t BCMI_QTC_XGXS_SC_X4_DBGr_fields[] = 4345 { 4346 /* SC_FSM_STATUS:0:15 */ 4347 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1043, 15, 0) 4348 }; 4349 static uint32_t BCMI_QTC_XGXS_SC_X4_ERRr_fields[] = 4350 { 4351 /* PLL_LOCK_TIMED_OUT:0:0 */ 4352 PHYMOD_SYMBOL_FIELD_ENCODE(863, 0, 0), 4353 /* PMD_LOCK_TIMED_OUT:1:1 */ 4354 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(887, 1, 1) 4355 }; 4356 static uint32_t BCMI_QTC_XGXS_SC_X4_FI_SP0_RSLVD0r_fields[] = 4357 { 4358 /* OS_MODE:0:3 */ 4359 PHYMOD_SYMBOL_FIELD_ENCODE(781, 3, 0), 4360 /* CL36BYTEDELETEMODE:4:5 */ 4361 PHYMOD_SYMBOL_FIELD_ENCODE(168, 5, 4), 4362 /* QSGMII_EN:6:6 */ 4363 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(929, 6, 6) 4364 }; 4365 static uint32_t BCMI_QTC_XGXS_SC_X4_FI_SP0_RSLVD1r_fields[] = 4366 { 4367 /* CLOCKCNT0:0:13 */ 4368 PHYMOD_SYMBOL_FIELD_ENCODE(289, 13, 0), 4369 /* SGMII_SPD_SWITCH:15:15 */ 4370 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1053, 15, 15) 4371 }; 4372 static uint32_t BCMI_QTC_XGXS_SC_X4_FI_SP0_RSLVD2r_fields[] = 4373 { 4374 /* CLOCKCNT1:0:7 */ 4375 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(291, 7, 0) 4376 }; 4377 static uint32_t BCMI_QTC_XGXS_SC_X4_FI_SP0_RSLVD3r_fields[] = 4378 { 4379 /* LOOPCNT1:0:5 */ 4380 PHYMOD_SYMBOL_FIELD_ENCODE(636, 5, 0), 4381 /* LOOPCNT0:6:13 */ 4382 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(634, 13, 6) 4383 }; 4384 static uint32_t BCMI_QTC_XGXS_SC_X4_FI_SP0_RSLVD4r_fields[] = 4385 { 4386 /* MAC_CREDITGENCNT:0:12 */ 4387 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(665, 12, 0) 4388 }; 4389 static uint32_t BCMI_QTC_XGXS_SC_X4_FI_SP0_RSLVD5r_fields[] = 4390 { 4391 /* PCS_CLOCKCNT0:0:13 */ 4392 PHYMOD_SYMBOL_FIELD_ENCODE(820, 13, 0), 4393 /* PCS_CREDITENABLE:14:14 */ 4394 PHYMOD_SYMBOL_FIELD_ENCODE(822, 14, 14), 4395 /* REPLICATION_CNT:15:15 */ 4396 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(955, 15, 15) 4397 }; 4398 static uint32_t BCMI_QTC_XGXS_SC_X4_FI_SP0_RSLVD6r_fields[] = 4399 { 4400 /* PCS_CREDITGENCNT:0:12 */ 4401 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(824, 12, 0) 4402 }; 4403 static uint32_t BCMI_QTC_XGXS_SC_X4_FI_SP0_RSLVD_SPDr_fields[] = 4404 { 4405 /* SPEED:0:7 */ 4406 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1102, 7, 0) 4407 }; 4408 static uint32_t BCMI_QTC_XGXS_SC_X4_FI_SP1_RSLVD0r_fields[] = 4409 { 4410 /* OS_MODE:0:3 */ 4411 PHYMOD_SYMBOL_FIELD_ENCODE(781, 3, 0), 4412 /* CL36BYTEDELETEMODE:4:5 */ 4413 PHYMOD_SYMBOL_FIELD_ENCODE(168, 5, 4), 4414 /* QSGMII_EN:6:6 */ 4415 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(929, 6, 6) 4416 }; 4417 static uint32_t BCMI_QTC_XGXS_SC_X4_FI_SP1_RSLVD1r_fields[] = 4418 { 4419 /* CLOCKCNT0:0:13 */ 4420 PHYMOD_SYMBOL_FIELD_ENCODE(289, 13, 0), 4421 /* SGMII_SPD_SWITCH:15:15 */ 4422 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1053, 15, 15) 4423 }; 4424 static uint32_t BCMI_QTC_XGXS_SC_X4_FI_SP1_RSLVD2r_fields[] = 4425 { 4426 /* CLOCKCNT1:0:7 */ 4427 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(291, 7, 0) 4428 }; 4429 static uint32_t BCMI_QTC_XGXS_SC_X4_FI_SP1_RSLVD3r_fields[] = 4430 { 4431 /* LOOPCNT1:0:5 */ 4432 PHYMOD_SYMBOL_FIELD_ENCODE(636, 5, 0), 4433 /* LOOPCNT0:6:13 */ 4434 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(634, 13, 6) 4435 }; 4436 static uint32_t BCMI_QTC_XGXS_SC_X4_FI_SP1_RSLVD4r_fields[] = 4437 { 4438 /* MAC_CREDITGENCNT:0:12 */ 4439 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(665, 12, 0) 4440 }; 4441 static uint32_t BCMI_QTC_XGXS_SC_X4_FI_SP1_RSLVD5r_fields[] = 4442 { 4443 /* PCS_CLOCKCNT0:0:13 */ 4444 PHYMOD_SYMBOL_FIELD_ENCODE(820, 13, 0), 4445 /* PCS_CREDITENABLE:14:14 */ 4446 PHYMOD_SYMBOL_FIELD_ENCODE(822, 14, 14), 4447 /* REPLICATION_CNT:15:15 */ 4448 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(955, 15, 15) 4449 }; 4450 static uint32_t BCMI_QTC_XGXS_SC_X4_FI_SP1_RSLVD6r_fields[] = 4451 { 4452 /* PCS_CREDITGENCNT:0:12 */ 4453 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(824, 12, 0) 4454 }; 4455 static uint32_t BCMI_QTC_XGXS_SC_X4_FI_SP1_RSLVD_SPDr_fields[] = 4456 { 4457 /* SPEED:0:7 */ 4458 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1102, 7, 0) 4459 }; 4460 static uint32_t BCMI_QTC_XGXS_SC_X4_FI_SP2_RSLVD0r_fields[] = 4461 { 4462 /* OS_MODE:0:3 */ 4463 PHYMOD_SYMBOL_FIELD_ENCODE(781, 3, 0), 4464 /* CL36BYTEDELETEMODE:4:5 */ 4465 PHYMOD_SYMBOL_FIELD_ENCODE(168, 5, 4), 4466 /* QSGMII_EN:6:6 */ 4467 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(929, 6, 6) 4468 }; 4469 static uint32_t BCMI_QTC_XGXS_SC_X4_FI_SP2_RSLVD1r_fields[] = 4470 { 4471 /* CLOCKCNT0:0:13 */ 4472 PHYMOD_SYMBOL_FIELD_ENCODE(289, 13, 0), 4473 /* SGMII_SPD_SWITCH:15:15 */ 4474 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1053, 15, 15) 4475 }; 4476 static uint32_t BCMI_QTC_XGXS_SC_X4_FI_SP2_RSLVD2r_fields[] = 4477 { 4478 /* CLOCKCNT1:0:7 */ 4479 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(291, 7, 0) 4480 }; 4481 static uint32_t BCMI_QTC_XGXS_SC_X4_FI_SP2_RSLVD3r_fields[] = 4482 { 4483 /* LOOPCNT1:0:5 */ 4484 PHYMOD_SYMBOL_FIELD_ENCODE(636, 5, 0), 4485 /* LOOPCNT0:6:13 */ 4486 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(634, 13, 6) 4487 }; 4488 static uint32_t BCMI_QTC_XGXS_SC_X4_FI_SP2_RSLVD4r_fields[] = 4489 { 4490 /* MAC_CREDITGENCNT:0:12 */ 4491 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(665, 12, 0) 4492 }; 4493 static uint32_t BCMI_QTC_XGXS_SC_X4_FI_SP2_RSLVD5r_fields[] = 4494 { 4495 /* PCS_CLOCKCNT0:0:13 */ 4496 PHYMOD_SYMBOL_FIELD_ENCODE(820, 13, 0), 4497 /* PCS_CREDITENABLE:14:14 */ 4498 PHYMOD_SYMBOL_FIELD_ENCODE(822, 14, 14), 4499 /* REPLICATION_CNT:15:15 */ 4500 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(955, 15, 15) 4501 }; 4502 static uint32_t BCMI_QTC_XGXS_SC_X4_FI_SP2_RSLVD6r_fields[] = 4503 { 4504 /* PCS_CREDITGENCNT:0:12 */ 4505 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(824, 12, 0) 4506 }; 4507 static uint32_t BCMI_QTC_XGXS_SC_X4_FI_SP2_RSLVD_SPDr_fields[] = 4508 { 4509 /* SPEED:0:7 */ 4510 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1102, 7, 0) 4511 }; 4512 static uint32_t BCMI_QTC_XGXS_SC_X4_FI_SP3_RSLVD0r_fields[] = 4513 { 4514 /* OS_MODE:0:3 */ 4515 PHYMOD_SYMBOL_FIELD_ENCODE(781, 3, 0), 4516 /* CL36BYTEDELETEMODE:4:5 */ 4517 PHYMOD_SYMBOL_FIELD_ENCODE(168, 5, 4), 4518 /* QSGMII_EN:6:6 */ 4519 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(929, 6, 6) 4520 }; 4521 static uint32_t BCMI_QTC_XGXS_SC_X4_FI_SP3_RSLVD1r_fields[] = 4522 { 4523 /* CLOCKCNT0:0:13 */ 4524 PHYMOD_SYMBOL_FIELD_ENCODE(289, 13, 0), 4525 /* SGMII_SPD_SWITCH:15:15 */ 4526 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1053, 15, 15) 4527 }; 4528 static uint32_t BCMI_QTC_XGXS_SC_X4_FI_SP3_RSLVD2r_fields[] = 4529 { 4530 /* CLOCKCNT1:0:7 */ 4531 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(291, 7, 0) 4532 }; 4533 static uint32_t BCMI_QTC_XGXS_SC_X4_FI_SP3_RSLVD3r_fields[] = 4534 { 4535 /* LOOPCNT1:0:5 */ 4536 PHYMOD_SYMBOL_FIELD_ENCODE(636, 5, 0), 4537 /* LOOPCNT0:6:13 */ 4538 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(634, 13, 6) 4539 }; 4540 static uint32_t BCMI_QTC_XGXS_SC_X4_FI_SP3_RSLVD4r_fields[] = 4541 { 4542 /* MAC_CREDITGENCNT:0:12 */ 4543 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(665, 12, 0) 4544 }; 4545 static uint32_t BCMI_QTC_XGXS_SC_X4_FI_SP3_RSLVD5r_fields[] = 4546 { 4547 /* PCS_CLOCKCNT0:0:13 */ 4548 PHYMOD_SYMBOL_FIELD_ENCODE(820, 13, 0), 4549 /* PCS_CREDITENABLE:14:14 */ 4550 PHYMOD_SYMBOL_FIELD_ENCODE(822, 14, 14), 4551 /* REPLICATION_CNT:15:15 */ 4552 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(955, 15, 15) 4553 }; 4554 static uint32_t BCMI_QTC_XGXS_SC_X4_FI_SP3_RSLVD6r_fields[] = 4555 { 4556 /* PCS_CREDITGENCNT:0:12 */ 4557 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(824, 12, 0) 4558 }; 4559 static uint32_t BCMI_QTC_XGXS_SC_X4_FI_SP3_RSLVD_SPDr_fields[] = 4560 { 4561 /* SPEED:0:7 */ 4562 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1102, 7, 0) 4563 }; 4564 static uint32_t BCMI_QTC_XGXS_SC_X4_FLD_OVRR_EN0_TYPEr_fields[] = 4565 { 4566 /* PCS_CREDITGENCNT_OEN:0:0 */ 4567 PHYMOD_SYMBOL_FIELD_ENCODE(825, 0, 0), 4568 /* PCS_CLOCKCNT0_OEN:1:1 */ 4569 PHYMOD_SYMBOL_FIELD_ENCODE(821, 1, 1), 4570 /* PCS_CREDITENABLE_OEN:2:2 */ 4571 PHYMOD_SYMBOL_FIELD_ENCODE(823, 2, 2), 4572 /* REPLICATION_CNT_OEN:3:3 */ 4573 PHYMOD_SYMBOL_FIELD_ENCODE(956, 3, 3), 4574 /* MAC_CREDITGENCNT_OEN:4:4 */ 4575 PHYMOD_SYMBOL_FIELD_ENCODE(666, 4, 4), 4576 /* LOOPCNT1_OEN:5:5 */ 4577 PHYMOD_SYMBOL_FIELD_ENCODE(637, 5, 5), 4578 /* LOOPCNT0_OEN:6:6 */ 4579 PHYMOD_SYMBOL_FIELD_ENCODE(635, 6, 6), 4580 /* CLOCKCNT1_OEN:7:7 */ 4581 PHYMOD_SYMBOL_FIELD_ENCODE(292, 7, 7), 4582 /* CLOCKCNT0_OEN:8:8 */ 4583 PHYMOD_SYMBOL_FIELD_ENCODE(290, 8, 8), 4584 /* CREDITENABLE_OEN:9:9 */ 4585 PHYMOD_SYMBOL_FIELD_ENCODE(322, 9, 9), 4586 /* SGMII_SPD_SWITCH_OEN:10:10 */ 4587 PHYMOD_SYMBOL_FIELD_ENCODE(1054, 10, 10), 4588 /* OS_MODE_OEN:11:11 */ 4589 PHYMOD_SYMBOL_FIELD_ENCODE(782, 11, 11), 4590 /* CL36BYTEDELETEMODE_OEN:12:12 */ 4591 PHYMOD_SYMBOL_FIELD_ENCODE(169, 12, 12), 4592 /* QSGMII_EN_OEN:13:13 */ 4593 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(930, 13, 13) 4594 }; 4595 static uint32_t BCMI_QTC_XGXS_SC_X4_QSGMII_SPDr_fields[] = 4596 { 4597 /* SPEED_SP0:0:1 */ 4598 PHYMOD_SYMBOL_FIELD_ENCODE(1104, 1, 0), 4599 /* SPEED_SP1:2:3 */ 4600 PHYMOD_SYMBOL_FIELD_ENCODE(1105, 3, 2), 4601 /* SPEED_SP2:4:5 */ 4602 PHYMOD_SYMBOL_FIELD_ENCODE(1106, 5, 4), 4603 /* SPEED_SP3:6:7 */ 4604 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1107, 7, 6) 4605 }; 4606 static uint32_t BCMI_QTC_XGXS_SC_X4_SC_AN_SUBP_CTLr_fields[] = 4607 { 4608 /* SUBP_TO_SEE_SC:0:1 */ 4609 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1109, 1, 0) 4610 }; 4611 static uint32_t BCMI_QTC_XGXS_SC_X4_STSr_fields[] = 4612 { 4613 /* SW_SPEED_CHANGE_DONE:0:0 */ 4614 PHYMOD_SYMBOL_FIELD_ENCODE(1120, 0, 0), 4615 /* SW_SPEED_CONFIG_VLD:1:1 */ 4616 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1121, 1, 1) 4617 }; 4618 static uint32_t BCMI_QTC_XGXS_SGMII_CL37_TMR_TYPEr_fields[] = 4619 { 4620 /* SGMII_TIMER:0:15 */ 4621 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1056, 15, 0) 4622 }; 4623 static uint32_t BCMI_QTC_XGXS_SIGDET_CTL0r_fields[] = 4624 { 4625 /* SIGNAL_DETECT_FILTER_COUNT:0:4 */ 4626 PHYMOD_SYMBOL_FIELD_ENCODE(1084, 4, 0), 4627 /* LOS_FILTER_COUNT:5:9 */ 4628 PHYMOD_SYMBOL_FIELD_ENCODE(638, 9, 5), 4629 /* ENERGY_DETECT_MASK_COUNT:10:14 */ 4630 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(462, 14, 10) 4631 }; 4632 static uint32_t BCMI_QTC_XGXS_SIGDET_CTL1r_fields[] = 4633 { 4634 /* AFE_SIGNAL_DETECT_DIS:0:0 */ 4635 PHYMOD_SYMBOL_FIELD_ENCODE(13, 0, 0), 4636 /* EXT_LOS_EN:1:1 */ 4637 PHYMOD_SYMBOL_FIELD_ENCODE(498, 1, 1), 4638 /* EXT_LOS_INV:2:2 */ 4639 PHYMOD_SYMBOL_FIELD_ENCODE(499, 2, 2), 4640 /* IGNORE_LP_MODE:3:3 */ 4641 PHYMOD_SYMBOL_FIELD_ENCODE(540, 3, 3), 4642 /* SIGNAL_DETECT_FILTER_1US:4:4 */ 4643 PHYMOD_SYMBOL_FIELD_ENCODE(1083, 4, 4), 4644 /* ENERGY_DETECT_FRC:5:5 */ 4645 PHYMOD_SYMBOL_FIELD_ENCODE(460, 5, 5), 4646 /* ENERGY_DETECT_FRC_VAL:6:6 */ 4647 PHYMOD_SYMBOL_FIELD_ENCODE(461, 6, 6), 4648 /* SIGNAL_DETECT_FRC:7:7 */ 4649 PHYMOD_SYMBOL_FIELD_ENCODE(1085, 7, 7), 4650 /* SIGNAL_DETECT_FRC_VAL:8:8 */ 4651 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1086, 8, 8) 4652 }; 4653 static uint32_t BCMI_QTC_XGXS_SIGDET_CTL2r_fields[] = 4654 { 4655 /* LOS_THRESH:0:4 */ 4656 PHYMOD_SYMBOL_FIELD_ENCODE(639, 4, 0), 4657 /* SIGNAL_DETECT_THRESH:5:9 */ 4658 PHYMOD_SYMBOL_FIELD_ENCODE(1093, 9, 5), 4659 /* HOLD_LOS_COUNT:10:12 */ 4660 PHYMOD_SYMBOL_FIELD_ENCODE(518, 12, 10), 4661 /* HOLD_SD_COUNT:13:15 */ 4662 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(519, 15, 13) 4663 }; 4664 static uint32_t BCMI_QTC_XGXS_SIGDET_STS0r_fields[] = 4665 { 4666 /* SIGNAL_DETECT:0:0 */ 4667 PHYMOD_SYMBOL_FIELD_ENCODE(1081, 0, 0), 4668 /* SIGNAL_DETECT_CHANGE:1:1 */ 4669 PHYMOD_SYMBOL_FIELD_ENCODE(1082, 1, 1), 4670 /* SIGNAL_DETECT_RAW:4:4 */ 4671 PHYMOD_SYMBOL_FIELD_ENCODE(1090, 4, 4), 4672 /* SIGNAL_DETECT_RAW_CHANGE:5:5 */ 4673 PHYMOD_SYMBOL_FIELD_ENCODE(1091, 5, 5), 4674 /* EXT_SIGDET:6:6 */ 4675 PHYMOD_SYMBOL_FIELD_ENCODE(501, 6, 6), 4676 /* EXT_SIGDET_CHANGE:7:7 */ 4677 PHYMOD_SYMBOL_FIELD_ENCODE(502, 7, 7), 4678 /* AFE_SIGDET:8:8 */ 4679 PHYMOD_SYMBOL_FIELD_ENCODE(9, 8, 8), 4680 /* AFE_SIGDET_CHANGE:9:9 */ 4681 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(10, 9, 9) 4682 }; 4683 static uint32_t BCMI_QTC_XGXS_SIGDET_STS1r_fields[] = 4684 { 4685 /* UC_SIGNAL_DETECT:0:0 */ 4686 PHYMOD_SYMBOL_FIELD_ENCODE(1361, 0, 0), 4687 /* UC_SIGNAL_DETECT_CHANGE:1:1 */ 4688 PHYMOD_SYMBOL_FIELD_ENCODE(1362, 1, 1), 4689 /* UC_EXT_SIGDET:6:6 */ 4690 PHYMOD_SYMBOL_FIELD_ENCODE(1357, 6, 6), 4691 /* UC_EXT_SIGDET_CHANGE:7:7 */ 4692 PHYMOD_SYMBOL_FIELD_ENCODE(1358, 7, 7), 4693 /* UC_AFE_SIGDET:8:8 */ 4694 PHYMOD_SYMBOL_FIELD_ENCODE(1350, 8, 8), 4695 /* UC_AFE_SIGDET_CHANGE:9:9 */ 4696 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1351, 9, 9) 4697 }; 4698 static uint32_t BCMI_QTC_XGXS_SIGDET_STS2r_fields[] = 4699 { 4700 /* ENERGY_DETECT:0:0 */ 4701 PHYMOD_SYMBOL_FIELD_ENCODE(458, 0, 0), 4702 /* ENERGY_DETECT_CHANGE:1:1 */ 4703 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(459, 1, 1) 4704 }; 4705 static uint32_t BCMI_QTC_XGXS_SIGDET_STS3r_fields[] = 4706 { 4707 /* PMD_SIGNAL_DETECT:0:0 */ 4708 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(894, 0, 0) 4709 }; 4710 static uint32_t BCMI_QTC_XGXS_SIGDET_STS4r_fields[] = 4711 { 4712 /* AFE_SIGDET_THRESH:0:4 */ 4713 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(12, 4, 0) 4714 }; 4715 static uint32_t BCMI_QTC_XGXS_SPARE0r_fields[] = 4716 { 4717 /* SPARE0:0:7 */ 4718 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1100, 7, 0) 4719 }; 4720 static uint32_t BCMI_QTC_XGXS_SPARE1r_fields[] = 4721 { 4722 /* SPARE1:0:7 */ 4723 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1101, 7, 0) 4724 }; 4725 static uint32_t BCMI_QTC_XGXS_SYNCACQ_STS_0_SP0r_fields[] = 4726 { 4727 /* CL36_SYNCACQ_STATE_CODED_PER_LN:0:3 */ 4728 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(179, 3, 0) 4729 }; 4730 static uint32_t BCMI_QTC_XGXS_SYNCACQ_STS_1_SP0r_fields[] = 4731 { 4732 /* CL36_SYNCACQ_HIS_STATE_PER_LN:0:12 */ 4733 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(178, 12, 0) 4734 }; 4735 static uint32_t BCMI_QTC_XGXS_TLB_RX_DBG_PMD_RX_LOCK_STSr_fields[] = 4736 { 4737 /* DBG_PMD_RX_LOCK:0:0 */ 4738 PHYMOD_SYMBOL_FIELD_ENCODE(337, 0, 0), 4739 /* DBG_PMD_RX_LOCK_CHANGE:1:1 */ 4740 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(338, 1, 1) 4741 }; 4742 static uint32_t BCMI_QTC_XGXS_TLB_RX_DIG_LPBK_CFGr_fields[] = 4743 { 4744 /* DIG_LPBK_EN:0:0 */ 4745 PHYMOD_SYMBOL_FIELD_ENCODE(410, 0, 0), 4746 /* DIG_LPBK_PD_MODE:1:1 */ 4747 PHYMOD_SYMBOL_FIELD_ENCODE(415, 1, 1), 4748 /* DIG_LPBK_PD_FLT_BYPASS:2:2 */ 4749 PHYMOD_SYMBOL_FIELD_ENCODE(413, 2, 2), 4750 /* DIG_LPBK_PD_BIAS_EN:3:3 */ 4751 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(411, 3, 3) 4752 }; 4753 static uint32_t BCMI_QTC_XGXS_TLB_RX_DIG_LPBK_PD_STSr_fields[] = 4754 { 4755 /* DIG_LPBK_PD_LATE_IND:0:0 */ 4756 PHYMOD_SYMBOL_FIELD_ENCODE(414, 0, 0), 4757 /* DIG_LPBK_PD_EARLY_IND:1:1 */ 4758 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(412, 1, 1) 4759 }; 4760 static uint32_t BCMI_QTC_XGXS_TLB_RX_PMD_RX_LOCK_STSr_fields[] = 4761 { 4762 /* PMD_RX_LOCK:0:0 */ 4763 PHYMOD_SYMBOL_FIELD_ENCODE(892, 0, 0), 4764 /* PMD_RX_LOCK_CHANGE:1:1 */ 4765 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(893, 1, 1) 4766 }; 4767 static uint32_t BCMI_QTC_XGXS_TLB_RX_PRBS_CHK_BURST_ERR_CNT_STSr_fields[] = 4768 { 4769 /* PRBS_CHK_BURST_ERR_CNT:0:9 */ 4770 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(903, 9, 0) 4771 }; 4772 static uint32_t BCMI_QTC_XGXS_TLB_RX_PRBS_CHK_CFGr_fields[] = 4773 { 4774 /* PRBS_CHK_EN:0:0 */ 4775 PHYMOD_SYMBOL_FIELD_ENCODE(906, 0, 0), 4776 /* PRBS_CHK_MODE_SEL:1:3 */ 4777 PHYMOD_SYMBOL_FIELD_ENCODE(919, 3, 1), 4778 /* PRBS_CHK_INV:4:4 */ 4779 PHYMOD_SYMBOL_FIELD_ENCODE(914, 4, 4), 4780 /* PRBS_CHK_MODE:5:6 */ 4781 PHYMOD_SYMBOL_FIELD_ENCODE(918, 6, 5), 4782 /* PRBS_CHK_EN_AUTO_MODE:7:7 */ 4783 PHYMOD_SYMBOL_FIELD_ENCODE(907, 7, 7), 4784 /* PRBS_CHK_ERR_CNT_BURST_MODE:9:9 */ 4785 PHYMOD_SYMBOL_FIELD_ENCODE(910, 9, 9), 4786 /* TRNSUM_ERROR_COUNT_EN:10:10 */ 4787 PHYMOD_SYMBOL_FIELD_ENCODE(1180, 10, 10), 4788 /* PRBS_CHK_CLK_EN_FRC_ON:11:11 */ 4789 PHYMOD_SYMBOL_FIELD_ENCODE(905, 11, 11), 4790 /* PRBS_CHK_BURST_ERR_CNT_EN:15:15 */ 4791 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(904, 15, 15) 4792 }; 4793 static uint32_t BCMI_QTC_XGXS_TLB_RX_PRBS_CHK_CNT_CFGr_fields[] = 4794 { 4795 /* PRBS_CHK_LOCK_CNT:0:4 */ 4796 PHYMOD_SYMBOL_FIELD_ENCODE(916, 4, 0), 4797 /* PRBS_CHK_OOL_CNT:8:12 */ 4798 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(920, 12, 8) 4799 }; 4800 static uint32_t BCMI_QTC_XGXS_TLB_RX_PRBS_CHK_EN_TMR_CTLr_fields[] = 4801 { 4802 /* PRBS_CHK_EN_TIMER_MODE:0:1 */ 4803 PHYMOD_SYMBOL_FIELD_ENCODE(909, 1, 0), 4804 /* PRBS_CHK_EN_TIMEOUT:8:12 */ 4805 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(908, 12, 8) 4806 }; 4807 static uint32_t BCMI_QTC_XGXS_TLB_RX_PRBS_CHK_ERR_CNT_LSB_STSr_fields[] = 4808 { 4809 /* PRBS_CHK_ERR_CNT_LSB:0:15 */ 4810 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(911, 15, 0) 4811 }; 4812 static uint32_t BCMI_QTC_XGXS_TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr_fields[] = 4813 { 4814 /* PRBS_CHK_ERR_CNT_MSB:0:14 */ 4815 PHYMOD_SYMBOL_FIELD_ENCODE(912, 14, 0), 4816 /* PRBS_CHK_LOCK_LOST_LH:15:15 */ 4817 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(917, 15, 15) 4818 }; 4819 static uint32_t BCMI_QTC_XGXS_TLB_RX_PRBS_CHK_LOCK_STSr_fields[] = 4820 { 4821 /* PRBS_CHK_LOCK:0:0 */ 4822 PHYMOD_SYMBOL_FIELD_ENCODE(915, 0, 0), 4823 /* PRBS_CHK_ERR_CNT_NO_CLR:1:15 */ 4824 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(913, 15, 1) 4825 }; 4826 static uint32_t BCMI_QTC_XGXS_TLB_RX_TLB_RX_MISC_CFGr_fields[] = 4827 { 4828 /* RX_PMD_DP_INVERT:0:0 */ 4829 PHYMOD_SYMBOL_FIELD_ENCODE(1034, 0, 0), 4830 /* RX_AGGREGATOR_BYPASS_EN:1:1 */ 4831 PHYMOD_SYMBOL_FIELD_ENCODE(993, 1, 1), 4832 /* DBG_MASK_DIG_LPBK_EN:2:2 */ 4833 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(336, 2, 2) 4834 }; 4835 static uint32_t BCMI_QTC_XGXS_TLB_RX_UC_PMD_RX_LOCK_STSr_fields[] = 4836 { 4837 /* UC_PMD_RX_LOCK:0:0 */ 4838 PHYMOD_SYMBOL_FIELD_ENCODE(1359, 0, 0), 4839 /* UC_PMD_RX_LOCK_CHANGE:1:1 */ 4840 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1360, 1, 1) 4841 }; 4842 static uint32_t BCMI_QTC_XGXS_TLB_TX_PATGEN_CFGr_fields[] = 4843 { 4844 /* PATT_GEN_EN:0:0 */ 4845 PHYMOD_SYMBOL_FIELD_ENCODE(801, 0, 0), 4846 /* PATT_GEN_STOP_POS:8:11 */ 4847 PHYMOD_SYMBOL_FIELD_ENCODE(818, 11, 8), 4848 /* PATT_GEN_START_POS:12:15 */ 4849 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(817, 15, 12) 4850 }; 4851 static uint32_t BCMI_QTC_XGXS_TLB_TX_PRBS_GEN_CFGr_fields[] = 4852 { 4853 /* PRBS_GEN_EN:0:0 */ 4854 PHYMOD_SYMBOL_FIELD_ENCODE(921, 0, 0), 4855 /* PRBS_GEN_MODE_SEL:1:3 */ 4856 PHYMOD_SYMBOL_FIELD_ENCODE(924, 3, 1), 4857 /* PRBS_GEN_INV:4:4 */ 4858 PHYMOD_SYMBOL_FIELD_ENCODE(923, 4, 4), 4859 /* PRBS_GEN_ERR_INS:5:5 */ 4860 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(922, 5, 5) 4861 }; 4862 static uint32_t BCMI_QTC_XGXS_TLB_TX_RMT_LPBK_CFGr_fields[] = 4863 { 4864 /* RMT_LPBK_EN:0:0 */ 4865 PHYMOD_SYMBOL_FIELD_ENCODE(977, 0, 0), 4866 /* RMT_LPBK_PD_MODE:1:1 */ 4867 PHYMOD_SYMBOL_FIELD_ENCODE(981, 1, 1), 4868 /* RMT_LPBK_PD_FRC_ON:2:2 */ 4869 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(979, 2, 2) 4870 }; 4871 static uint32_t BCMI_QTC_XGXS_TLB_TX_RMT_LPBK_PD_STSr_fields[] = 4872 { 4873 /* RMT_LPBK_PD_LATE_IND:0:0 */ 4874 PHYMOD_SYMBOL_FIELD_ENCODE(980, 0, 0), 4875 /* RMT_LPBK_PD_EARLY_IND:1:1 */ 4876 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(978, 1, 1) 4877 }; 4878 static uint32_t BCMI_QTC_XGXS_TLB_TX_TLB_TX_MISC_CFGr_fields[] = 4879 { 4880 /* TX_PMD_DP_INVERT:0:0 */ 4881 PHYMOD_SYMBOL_FIELD_ENCODE(1332, 0, 0), 4882 /* TX_PCS_NATIVE_ANA_FRMT_EN:1:1 */ 4883 PHYMOD_SYMBOL_FIELD_ENCODE(1296, 1, 1), 4884 /* TX_MUX_SEL_ORDER:2:2 */ 4885 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1290, 2, 2) 4886 }; 4887 static uint32_t BCMI_QTC_XGXS_TOP_USER_CTL0r_fields[] = 4888 { 4889 /* HEARTBEAT_COUNT_1US:0:9 */ 4890 PHYMOD_SYMBOL_FIELD_ENCODE(513, 9, 0), 4891 /* MASKDATA_BUS_ASSIGN:10:11 */ 4892 PHYMOD_SYMBOL_FIELD_ENCODE(671, 11, 10), 4893 /* CORE_DP_S_RSTB:13:13 */ 4894 PHYMOD_SYMBOL_FIELD_ENCODE(312, 13, 13), 4895 /* AFE_S_PLL_PWRDN:14:14 */ 4896 PHYMOD_SYMBOL_FIELD_ENCODE(14, 14, 14), 4897 /* UC_ACTIVE:15:15 */ 4898 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1349, 15, 15) 4899 }; 4900 static uint32_t BCMI_QTC_XGXS_TXCOM_AFE_RST_PWRDN_OSR_MODE_PIN_STSr_fields[] = 4901 { 4902 /* TX_OSR_MODE_PIN:0:3 */ 4903 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1295, 3, 0) 4904 }; 4905 static uint32_t BCMI_QTC_XGXS_TXCOM_CTL0r_fields[] = 4906 { 4907 /* TXCOM_CL72_MAX_WAIT_TIMER_PERIOD:0:15 */ 4908 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1206, 15, 0) 4909 }; 4910 static uint32_t BCMI_QTC_XGXS_TXCOM_CTL1r_fields[] = 4911 { 4912 /* TXCOM_CL72_WAIT_CNTR_LIMIT:0:8 */ 4913 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1207, 8, 0) 4914 }; 4915 static uint32_t BCMI_QTC_XGXS_TXCOM_LN_CLK_RST_N_PWRDWN_CTLr_fields[] = 4916 { 4917 /* TX_LN_DP_S_RSTB:0:0 */ 4918 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1280, 0, 0) 4919 }; 4920 static uint32_t BCMI_QTC_XGXS_TXCOM_LN_DP_RST_ST_STSr_fields[] = 4921 { 4922 /* TX_LANE_DP_RESET_STATE:0:2 */ 4923 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1275, 2, 0) 4924 }; 4925 static uint32_t BCMI_QTC_XGXS_TXCOM_LN_RST_N_PWRDN_PIN_KILL_CTLr_fields[] = 4926 { 4927 /* PMD_LN_TX_H_RSTB_PKILL:0:0 */ 4928 PHYMOD_SYMBOL_FIELD_ENCODE(886, 0, 0), 4929 /* PMD_LN_TX_DP_H_RSTB_PKILL:1:1 */ 4930 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(884, 1, 1) 4931 }; 4932 static uint32_t BCMI_QTC_XGXS_TXCOM_LN_RST_OCC_CTLr_fields[] = 4933 { 4934 /* TX_LANE_REG_RESET_OCCURRED:0:0 */ 4935 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1277, 0, 0) 4936 }; 4937 static uint32_t BCMI_QTC_XGXS_TXCOM_LN_S_RSTB_CTLr_fields[] = 4938 { 4939 /* TX_LN_S_RSTB:0:0 */ 4940 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1281, 0, 0) 4941 }; 4942 static uint32_t BCMI_QTC_XGXS_TXCOM_MCST_MASK_CTLr_fields[] = 4943 { 4944 /* TX_MULTICAST_MASK_CONTROL:0:0 */ 4945 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1288, 0, 0) 4946 }; 4947 static uint32_t BCMI_QTC_XGXS_TXCOM_OSR_MODE_CTLr_fields[] = 4948 { 4949 /* TX_OSR_MODE_FRC_VAL:0:3 */ 4950 PHYMOD_SYMBOL_FIELD_ENCODE(1293, 3, 0), 4951 /* TX_OSR_MODE_FRC:15:15 */ 4952 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1292, 15, 15) 4953 }; 4954 static uint32_t BCMI_QTC_XGXS_TXCOM_OSR_MODE_STS_MC_MASKr_fields[] = 4955 { 4956 /* TX_OSR_MODE:0:3 */ 4957 PHYMOD_SYMBOL_FIELD_ENCODE(1291, 3, 0), 4958 /* TX_MULTICAST_MASK_CONTROL_STATUS:4:4 */ 4959 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1289, 4, 4) 4960 }; 4961 static uint32_t BCMI_QTC_XGXS_TXCOM_UC_ACK_LN_CTLr_fields[] = 4962 { 4963 /* TX_UC_ACK_LANE_CFG_DONE:0:0 */ 4964 PHYMOD_SYMBOL_FIELD_ENCODE(1340, 0, 0), 4965 /* TX_UC_ACK_LANE_DP_RESET:1:1 */ 4966 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1341, 1, 1) 4967 }; 4968 static uint32_t BCMI_QTC_XGXS_TXFIR_DC_LEVEL_AFE_CTL0r_fields[] = 4969 { 4970 /* TXFIR_DC_LEVEL_0P5X:0:0 */ 4971 PHYMOD_SYMBOL_FIELD_ENCODE(1208, 0, 0), 4972 /* TXFIR_DC_LEVEL_1X:1:1 */ 4973 PHYMOD_SYMBOL_FIELD_ENCODE(1209, 1, 1), 4974 /* TXFIR_DC_LEVEL_2X_0:2:2 */ 4975 PHYMOD_SYMBOL_FIELD_ENCODE(1210, 2, 2), 4976 /* TXFIR_DC_LEVEL_2X_1:3:3 */ 4977 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1211, 3, 3) 4978 }; 4979 static uint32_t BCMI_QTC_XGXS_TXFIR_MISC_CTL0r_fields[] = 4980 { 4981 /* SDK_TX_DISABLE:0:0 */ 4982 PHYMOD_SYMBOL_FIELD_ENCODE(1045, 0, 0), 4983 /* TX_DISABLE_OUTPUT_SEL:2:3 */ 4984 PHYMOD_SYMBOL_FIELD_ENCODE(1260, 3, 2), 4985 /* CONVERT_TAPS_TO_AFE:4:4 */ 4986 PHYMOD_SYMBOL_FIELD_ENCODE(306, 4, 4), 4987 /* CONVERT_TAPS_TO_AFE_INT_EN:5:5 */ 4988 PHYMOD_SYMBOL_FIELD_ENCODE(308, 5, 5), 4989 /* CONVERT_TAPS_TO_AFE_ERROR:6:6 */ 4990 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(307, 6, 6) 4991 }; 4992 static uint32_t BCMI_QTC_XGXS_TXFIR_MISC_STS0r_fields[] = 4993 { 4994 /* TX_DISABLE_STATUS:0:0 */ 4995 PHYMOD_SYMBOL_FIELD_ENCODE(1261, 0, 0), 4996 /* TX_ELEC_IDLE_STATUS:1:1 */ 4997 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1266, 1, 1) 4998 }; 4999 static uint32_t BCMI_QTC_XGXS_TXFIR_POST1PRE_AFE_CTL0r_fields[] = 5000 { 5001 /* TXFIR_PRE_POST1PRE_1X_1:0:0 */ 5002 PHYMOD_SYMBOL_FIELD_ENCODE(1244, 0, 0), 5003 /* TXFIR_POST1_POST1PRE_1X_1:1:1 */ 5004 PHYMOD_SYMBOL_FIELD_ENCODE(1228, 1, 1), 5005 /* TXFIR_DC_LEVEL_POST1PRE_1X_1:2:2 */ 5006 PHYMOD_SYMBOL_FIELD_ENCODE(1213, 2, 2), 5007 /* TXFIR_PRE_POST1PRE_2X_0:3:3 */ 5008 PHYMOD_SYMBOL_FIELD_ENCODE(1245, 3, 3), 5009 /* TXFIR_POST1_POST1PRE_2X_0:4:4 */ 5010 PHYMOD_SYMBOL_FIELD_ENCODE(1229, 4, 4), 5011 /* TXFIR_DC_LEVEL_POST1PRE_2X_0:5:5 */ 5012 PHYMOD_SYMBOL_FIELD_ENCODE(1214, 5, 5), 5013 /* TXFIR_PRE_POST1PRE_2X_1:6:6 */ 5014 PHYMOD_SYMBOL_FIELD_ENCODE(1246, 6, 6), 5015 /* TXFIR_POST1_POST1PRE_2X_1:7:7 */ 5016 PHYMOD_SYMBOL_FIELD_ENCODE(1230, 7, 7), 5017 /* TXFIR_DC_LEVEL_POST1PRE_2X_1:8:8 */ 5018 PHYMOD_SYMBOL_FIELD_ENCODE(1215, 8, 8), 5019 /* TXFIR_PRE_POST1PRE_2X_2:9:9 */ 5020 PHYMOD_SYMBOL_FIELD_ENCODE(1247, 9, 9), 5021 /* TXFIR_POST1_POST1PRE_2X_2:10:10 */ 5022 PHYMOD_SYMBOL_FIELD_ENCODE(1231, 10, 10), 5023 /* TXFIR_DC_LEVEL_POST1PRE_2X_2:11:11 */ 5024 PHYMOD_SYMBOL_FIELD_ENCODE(1216, 11, 11), 5025 /* TXFIR_PRE_POST1PRE_2X_3:12:12 */ 5026 PHYMOD_SYMBOL_FIELD_ENCODE(1248, 12, 12), 5027 /* TXFIR_POST1_POST1PRE_2X_3:13:13 */ 5028 PHYMOD_SYMBOL_FIELD_ENCODE(1232, 13, 13), 5029 /* TXFIR_DC_LEVEL_POST1PRE_2X_3:14:14 */ 5030 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1217, 14, 14) 5031 }; 5032 static uint32_t BCMI_QTC_XGXS_TXFIR_POST1_AFE_CTL0r_fields[] = 5033 { 5034 /* TXFIR_POST1_POST1_1X_0:0:0 */ 5035 PHYMOD_SYMBOL_FIELD_ENCODE(1233, 0, 0), 5036 /* TXFIR_DC_LEVEL_POST1_1X_0:1:1 */ 5037 PHYMOD_SYMBOL_FIELD_ENCODE(1218, 1, 1), 5038 /* TXFIR_POST1_POST1_1X_1:2:2 */ 5039 PHYMOD_SYMBOL_FIELD_ENCODE(1234, 2, 2), 5040 /* TXFIR_DC_LEVEL_POST1_1X_1:3:3 */ 5041 PHYMOD_SYMBOL_FIELD_ENCODE(1219, 3, 3), 5042 /* TXFIR_POST1_POST1_2X_0:4:4 */ 5043 PHYMOD_SYMBOL_FIELD_ENCODE(1235, 4, 4), 5044 /* TXFIR_DC_LEVEL_POST1_2X_0:5:5 */ 5045 PHYMOD_SYMBOL_FIELD_ENCODE(1220, 5, 5), 5046 /* TXFIR_POST1_POST1_2X_1:6:6 */ 5047 PHYMOD_SYMBOL_FIELD_ENCODE(1236, 6, 6), 5048 /* TXFIR_DC_LEVEL_POST1_2X_1:7:7 */ 5049 PHYMOD_SYMBOL_FIELD_ENCODE(1221, 7, 7), 5050 /* TXFIR_POST1_POST1_2X_2:8:8 */ 5051 PHYMOD_SYMBOL_FIELD_ENCODE(1237, 8, 8), 5052 /* TXFIR_DC_LEVEL_POST1_2X_2:9:9 */ 5053 PHYMOD_SYMBOL_FIELD_ENCODE(1222, 9, 9), 5054 /* TXFIR_PRE_POST1PRE_1X_0:12:12 */ 5055 PHYMOD_SYMBOL_FIELD_ENCODE(1243, 12, 12), 5056 /* TXFIR_POST1_POST1PRE_1X_0:13:13 */ 5057 PHYMOD_SYMBOL_FIELD_ENCODE(1227, 13, 13), 5058 /* TXFIR_DC_LEVEL_POST1PRE_1X_0:14:14 */ 5059 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1212, 14, 14) 5060 }; 5061 static uint32_t BCMI_QTC_XGXS_TXFIR_POST2_AFE_CTL0r_fields[] = 5062 { 5063 /* TXFIR_POST2_POST2_1X_0:0:0 */ 5064 PHYMOD_SYMBOL_FIELD_ENCODE(1239, 0, 0), 5065 /* TXFIR_DC_LEVEL_POST2_1X_0:1:1 */ 5066 PHYMOD_SYMBOL_FIELD_ENCODE(1223, 1, 1), 5067 /* TXFIR_POST2_POST2_1X_1:2:2 */ 5068 PHYMOD_SYMBOL_FIELD_ENCODE(1240, 2, 2), 5069 /* TXFIR_DC_LEVEL_POST2_1X_1:3:3 */ 5070 PHYMOD_SYMBOL_FIELD_ENCODE(1224, 3, 3), 5071 /* TXFIR_POST2_POST2_2X_0:4:4 */ 5072 PHYMOD_SYMBOL_FIELD_ENCODE(1241, 4, 4), 5073 /* TXFIR_DC_LEVEL_POST2_2X_0:5:5 */ 5074 PHYMOD_SYMBOL_FIELD_ENCODE(1225, 5, 5), 5075 /* TXFIR_POST2_POST2_2X_1:6:6 */ 5076 PHYMOD_SYMBOL_FIELD_ENCODE(1242, 6, 6), 5077 /* TXFIR_DC_LEVEL_POST2_2X_1:7:7 */ 5078 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1226, 7, 7) 5079 }; 5080 static uint32_t BCMI_QTC_XGXS_TXFIR_TAP_CTL0r_fields[] = 5081 { 5082 /* TXFIR_POST2:0:3 */ 5083 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1238, 3, 0) 5084 }; 5085 static uint32_t BCMI_QTC_XGXS_TXFIR_UC_CTL0r_fields[] = 5086 { 5087 /* MICRO_TX_DISABLE:0:0 */ 5088 PHYMOD_SYMBOL_FIELD_ENCODE(766, 0, 0), 5089 /* TX_DISABLE_TRIGGER:1:1 */ 5090 PHYMOD_SYMBOL_FIELD_ENCODE(1263, 1, 1), 5091 /* DP_RESET_TX_DISABLE_DIS:2:2 */ 5092 PHYMOD_SYMBOL_FIELD_ENCODE(424, 2, 2), 5093 /* PMD_TX_DISABLE_PKILL:3:3 */ 5094 PHYMOD_SYMBOL_FIELD_ENCODE(897, 3, 3), 5095 /* TX_DISABLE_TIMER_CTRL:4:9 */ 5096 PHYMOD_SYMBOL_FIELD_ENCODE(1262, 9, 4), 5097 /* TX_EEE_QUIET_EN:14:14 */ 5098 PHYMOD_SYMBOL_FIELD_ENCODE(1265, 14, 14), 5099 /* TX_EEE_ALERT_EN:15:15 */ 5100 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1264, 15, 15) 5101 }; 5102 static uint32_t BCMI_QTC_XGXS_TX_AFE_RST_PWRDN_OSR_MODE_PIN_STSr_fields[] = 5103 { 5104 /* AFE_TX_PWRDN:0:0 */ 5105 PHYMOD_SYMBOL_FIELD_ENCODE(20, 0, 0), 5106 /* AFE_TX_RESET:1:1 */ 5107 PHYMOD_SYMBOL_FIELD_ENCODE(23, 1, 1), 5108 /* AFE_TXCLK_RESET:2:2 */ 5109 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(15, 2, 2) 5110 }; 5111 static uint32_t BCMI_QTC_XGXS_TX_CLK_N_RST_DBG_CTLr_fields[] = 5112 { 5113 /* LN_TX_S_CLKGATE_FRC_ON:0:0 */ 5114 PHYMOD_SYMBOL_FIELD_ENCODE(616, 0, 0), 5115 /* LN_TX_S_COMCLK_SEL:1:1 */ 5116 PHYMOD_SYMBOL_FIELD_ENCODE(618, 1, 1), 5117 /* LN_TX_S_COMCLK_FRC_ON:2:2 */ 5118 PHYMOD_SYMBOL_FIELD_ENCODE(617, 2, 2), 5119 /* PMD_TX_CLK_VLD_FRC:3:3 */ 5120 PHYMOD_SYMBOL_FIELD_ENCODE(895, 3, 3), 5121 /* PMD_TX_CLK_VLD_FRC_VAL:4:4 */ 5122 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(896, 4, 4) 5123 }; 5124 static uint32_t BCMI_QTC_XGXS_TX_CLK_N_RST_MISC_CTLr_fields[] = 5125 { 5126 /* TX_PI_LOOP_FILTER_STABLE:0:0 */ 5127 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1316, 0, 0) 5128 }; 5129 static uint32_t BCMI_QTC_XGXS_TX_LN_AFE_RST_PWRDWN_CTL_CTLr_fields[] = 5130 { 5131 /* AFE_TX_PWRDN_FRC:0:0 */ 5132 PHYMOD_SYMBOL_FIELD_ENCODE(21, 0, 0), 5133 /* AFE_TX_PWRDN_FRC_VAL:1:1 */ 5134 PHYMOD_SYMBOL_FIELD_ENCODE(22, 1, 1), 5135 /* AFE_TX_RESET_FRC:2:2 */ 5136 PHYMOD_SYMBOL_FIELD_ENCODE(25, 2, 2), 5137 /* AFE_TX_RESET_FRC_VAL:3:3 */ 5138 PHYMOD_SYMBOL_FIELD_ENCODE(26, 3, 3), 5139 /* AFE_TXCLK_RESET_FRC:4:4 */ 5140 PHYMOD_SYMBOL_FIELD_ENCODE(16, 4, 4), 5141 /* AFE_TXCLK_RESET_FRC_VAL:5:5 */ 5142 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(17, 5, 5) 5143 }; 5144 static uint32_t BCMI_QTC_XGXS_TX_LN_CLK_RST_N_PWRDWN_CTLr_fields[] = 5145 { 5146 /* LN_TX_S_PWRDN:0:0 */ 5147 PHYMOD_SYMBOL_FIELD_ENCODE(619, 0, 0), 5148 /* AFE_TX_RESET_DEASSERT:15:15 */ 5149 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(24, 15, 15) 5150 }; 5151 static uint32_t BCMI_QTC_XGXS_TX_LN_DBG_RST_CTLr_fields[] = 5152 { 5153 /* LN_TX_S_RSTB:0:0 */ 5154 PHYMOD_SYMBOL_FIELD_ENCODE(620, 0, 0), 5155 /* LN_TX_DP_S_RSTB:1:1 */ 5156 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(613, 1, 1) 5157 }; 5158 static uint32_t BCMI_QTC_XGXS_TX_LN_RST_N_PWRDN_PIN_KILL_CTLr_fields[] = 5159 { 5160 /* PMD_LN_TX_H_PWRDN_PKILL:0:0 */ 5161 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(885, 0, 0) 5162 }; 5163 static uint32_t BCMI_QTC_XGXS_TX_PI_CTL0r_fields[] = 5164 { 5165 /* TX_PI_EN:0:0 */ 5166 PHYMOD_SYMBOL_FIELD_ENCODE(1297, 0, 0), 5167 /* TX_PI_JITTER_FILTER_EN:1:1 */ 5168 PHYMOD_SYMBOL_FIELD_ENCODE(1312, 1, 1), 5169 /* TX_PI_EXT_CTRL_EN:2:2 */ 5170 PHYMOD_SYMBOL_FIELD_ENCODE(1298, 2, 2), 5171 /* TX_PI_FREQ_OVERRIDE_EN:3:3 */ 5172 PHYMOD_SYMBOL_FIELD_ENCODE(1303, 3, 3), 5173 /* TX_PI_SJ_GEN_EN:4:4 */ 5174 PHYMOD_SYMBOL_FIELD_ENCODE(1330, 4, 4), 5175 /* TX_PI_SSC_GEN_EN:5:5 */ 5176 PHYMOD_SYMBOL_FIELD_ENCODE(1331, 5, 5), 5177 /* TX_PI_JIT_SSC_FREQ_MODE:6:6 */ 5178 PHYMOD_SYMBOL_FIELD_ENCODE(1315, 6, 6), 5179 /* TX_PI_RESET_CODE_DBG:7:7 */ 5180 PHYMOD_SYMBOL_FIELD_ENCODE(1327, 7, 7), 5181 /* TX_PI_SECOND_ORDER_LOOP_EN:8:8 */ 5182 PHYMOD_SYMBOL_FIELD_ENCODE(1329, 8, 8), 5183 /* TX_PI_FIRST_ORDER_BWSEL_INTEG:10:11 */ 5184 PHYMOD_SYMBOL_FIELD_ENCODE(1301, 11, 10), 5185 /* TX_PI_SECOND_ORDER_BWSEL_INTEG:12:13 */ 5186 PHYMOD_SYMBOL_FIELD_ENCODE(1328, 13, 12), 5187 /* TX_PI_FRC_PHASE_STEP_MUX_SEL:15:15 */ 5188 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1302, 15, 15) 5189 }; 5190 static uint32_t BCMI_QTC_XGXS_TX_PI_CTL1r_fields[] = 5191 { 5192 /* TX_PI_FREQ_OVERRIDE_VAL:0:14 */ 5193 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1304, 14, 0) 5194 }; 5195 static uint32_t BCMI_QTC_XGXS_TX_PI_CTL2r_fields[] = 5196 { 5197 /* TX_PI_JIT_FREQ_IDX:0:5 */ 5198 PHYMOD_SYMBOL_FIELD_ENCODE(1314, 5, 0), 5199 /* TX_PI_JIT_AMP:8:13 */ 5200 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1313, 13, 8) 5201 }; 5202 static uint32_t BCMI_QTC_XGXS_TX_PI_CTL3r_fields[] = 5203 { 5204 /* TX_PI_PHASE_OVERRIDE:0:0 */ 5205 PHYMOD_SYMBOL_FIELD_ENCODE(1322, 0, 0), 5206 /* TX_PI_PHASE_STROBE:1:1 */ 5207 PHYMOD_SYMBOL_FIELD_ENCODE(1325, 1, 1), 5208 /* TX_PI_PHASE_STEP_DIR:2:2 */ 5209 PHYMOD_SYMBOL_FIELD_ENCODE(1323, 2, 2), 5210 /* TX_PI_PHASE_INVERT:4:4 */ 5211 PHYMOD_SYMBOL_FIELD_ENCODE(1321, 4, 4), 5212 /* TX_PI_PHASE_STEP_NUM:8:11 */ 5213 PHYMOD_SYMBOL_FIELD_ENCODE(1324, 11, 8), 5214 /* TX_PI_EXT_PHASE_BWSEL_INTEG:12:14 */ 5215 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1300, 14, 12) 5216 }; 5217 static uint32_t BCMI_QTC_XGXS_TX_PI_CTL4r_fields[] = 5218 { 5219 /* TX_PI_FRZ_FRC:0:0 */ 5220 PHYMOD_SYMBOL_FIELD_ENCODE(1305, 0, 0), 5221 /* TX_PI_FRZ_FRC_VAL:1:1 */ 5222 PHYMOD_SYMBOL_FIELD_ENCODE(1306, 1, 1), 5223 /* TX_PI_FRZ_MODE:2:2 */ 5224 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1307, 2, 2) 5225 }; 5226 static uint32_t BCMI_QTC_XGXS_TX_PI_CTL5r_fields[] = 5227 { 5228 /* TX_PI_HS_FIFO_PHSERR_INVERT:1:1 */ 5229 PHYMOD_SYMBOL_FIELD_ENCODE(1309, 1, 1), 5230 /* TX_PI_REPEATER_MODE_EN:2:2 */ 5231 PHYMOD_SYMBOL_FIELD_ENCODE(1326, 2, 2), 5232 /* TX_PI_EXT_PD_SEL:3:3 */ 5233 PHYMOD_SYMBOL_FIELD_ENCODE(1299, 3, 3), 5234 /* AFE_TX_FIFO_RESETB:8:8 */ 5235 PHYMOD_SYMBOL_FIELD_ENCODE(18, 8, 8), 5236 /* AFE_TX_FIFO_RESETB_FRC_ON:9:9 */ 5237 PHYMOD_SYMBOL_FIELD_ENCODE(19, 9, 9), 5238 /* TX_PI_PD_BYPASS_FLT:10:10 */ 5239 PHYMOD_SYMBOL_FIELD_ENCODE(1317, 10, 10), 5240 /* TX_PI_PD_BYPASS_VCO:11:11 */ 5241 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1318, 11, 11) 5242 }; 5243 static uint32_t BCMI_QTC_XGXS_TX_PI_STS0r_fields[] = 5244 { 5245 /* TX_PI_PHASE_CNTR:0:6 */ 5246 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1319, 6, 0) 5247 }; 5248 static uint32_t BCMI_QTC_XGXS_TX_PI_STS1r_fields[] = 5249 { 5250 /* TX_PI_INTEG1_REG:0:13 */ 5251 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1310, 13, 0) 5252 }; 5253 static uint32_t BCMI_QTC_XGXS_TX_PI_STS2r_fields[] = 5254 { 5255 /* TX_PI_INTEG2_REG:0:14 */ 5256 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1311, 14, 0) 5257 }; 5258 static uint32_t BCMI_QTC_XGXS_TX_PI_STS3r_fields[] = 5259 { 5260 /* TX_PI_PHASE_ERR:0:5 */ 5261 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1320, 5, 0) 5262 }; 5263 static uint32_t BCMI_QTC_XGXS_TX_PI_STS4r_fields[] = 5264 { 5265 /* TX_PI_HS_FIFO_PHSERR:0:0 */ 5266 PHYMOD_SYMBOL_FIELD_ENCODE(1308, 0, 0), 5267 /* ST_AFE_TX_FIFO_RESETB:1:1 */ 5268 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1108, 1, 1) 5269 }; 5270 static uint32_t BCMI_QTC_XGXS_TX_PI_TX_FIFO_OVFB_STSr_fields[] = 5271 { 5272 /* TX_FIFO_OVFB:0:0 */ 5273 PHYMOD_SYMBOL_FIELD_ENCODE(1267, 0, 0), 5274 /* TX_FIFO_OVFB_FALL_EDGE_LH:1:1 */ 5275 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1268, 1, 1) 5276 }; 5277 static uint32_t BCMI_QTC_XGXS_TX_RATE_MISMATCHr_fields[] = 5278 { 5279 /* TX_LANE_RATE_MISMATCH:0:0 */ 5280 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1276, 0, 0) 5281 }; 5282 static uint32_t BCMI_QTC_XGXS_TX_X4_CL49_CTL0_TX_ENC_CTL0r_fields[] = 5283 { 5284 /* CL49_TX_RF_ENABLE:0:0 */ 5285 PHYMOD_SYMBOL_FIELD_ENCODE(231, 0, 0), 5286 /* CL49_TX_LF_ENABLE:1:1 */ 5287 PHYMOD_SYMBOL_FIELD_ENCODE(230, 1, 1), 5288 /* TX_LPI_ENABLE:2:2 */ 5289 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1284, 2, 2) 5290 }; 5291 static uint32_t BCMI_QTC_XGXS_TX_X4_CL49_CTL0_TX_PCS_CTL0r_fields[] = 5292 { 5293 /* SCRAMBLERMODE:15:15 */ 5294 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1041, 15, 15) 5295 }; 5296 static uint32_t BCMI_QTC_XGXS_TX_X4_CL49_STS0_ENC_STS_SP0r_fields[] = 5297 { 5298 /* CL49_TXSM_STATE_SP0:0:2 */ 5299 PHYMOD_SYMBOL_FIELD_ENCODE(222, 2, 0), 5300 /* CL49_LTXSM_STATE_SP0:3:10 */ 5301 PHYMOD_SYMBOL_FIELD_ENCODE(204, 10, 3), 5302 /* CL49_TX_FAULT_DET_SP0:11:11 */ 5303 PHYMOD_SYMBOL_FIELD_ENCODE(226, 11, 11), 5304 /* CL49_T_TYPE_CODED_SP0:12:15 */ 5305 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(232, 15, 12) 5306 }; 5307 static uint32_t BCMI_QTC_XGXS_TX_X4_CL49_STS0_ENC_STS_SP1r_fields[] = 5308 { 5309 /* CL49_TXSM_STATE_SP1:0:2 */ 5310 PHYMOD_SYMBOL_FIELD_ENCODE(223, 2, 0), 5311 /* CL49_LTXSM_STATE_SP1:3:10 */ 5312 PHYMOD_SYMBOL_FIELD_ENCODE(205, 10, 3), 5313 /* CL49_TX_FAULT_DET_SP1:11:11 */ 5314 PHYMOD_SYMBOL_FIELD_ENCODE(227, 11, 11), 5315 /* CL49_T_TYPE_CODED_SP1:12:15 */ 5316 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(233, 15, 12) 5317 }; 5318 static uint32_t BCMI_QTC_XGXS_TX_X4_CL49_STS0_ENC_STS_SP2r_fields[] = 5319 { 5320 /* CL49_TXSM_STATE_SP2:0:2 */ 5321 PHYMOD_SYMBOL_FIELD_ENCODE(224, 2, 0), 5322 /* CL49_LTXSM_STATE_SP2:3:10 */ 5323 PHYMOD_SYMBOL_FIELD_ENCODE(206, 10, 3), 5324 /* CL49_TX_FAULT_DET_SP2:11:11 */ 5325 PHYMOD_SYMBOL_FIELD_ENCODE(228, 11, 11), 5326 /* CL49_T_TYPE_CODED_SP2:12:15 */ 5327 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(234, 15, 12) 5328 }; 5329 static uint32_t BCMI_QTC_XGXS_TX_X4_CL49_STS0_ENC_STS_SP3r_fields[] = 5330 { 5331 /* CL49_TXSM_STATE_SP3:0:2 */ 5332 PHYMOD_SYMBOL_FIELD_ENCODE(225, 2, 0), 5333 /* CL49_LTXSM_STATE_SP3:3:10 */ 5334 PHYMOD_SYMBOL_FIELD_ENCODE(207, 10, 3), 5335 /* CL49_TX_FAULT_DET_SP3:11:11 */ 5336 PHYMOD_SYMBOL_FIELD_ENCODE(229, 11, 11), 5337 /* CL49_T_TYPE_CODED_SP3:12:15 */ 5338 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(235, 15, 12) 5339 }; 5340 static uint32_t BCMI_QTC_XGXS_TX_X4_CL49_STS0_TX_PCS_LATCH_STSr_fields[] = 5341 { 5342 /* TX_RESERVED_ORDERED_SET_LH:0:3 */ 5343 PHYMOD_SYMBOL_FIELD_ENCODE(1338, 3, 0), 5344 /* TX_LPI_RECEIVED_LH:4:7 */ 5345 PHYMOD_SYMBOL_FIELD_ENCODE(1286, 7, 4), 5346 /* TX_REMOTE_FAULT_LH:8:11 */ 5347 PHYMOD_SYMBOL_FIELD_ENCODE(1337, 11, 8), 5348 /* TX_LOCAL_FAULT_LH:12:15 */ 5349 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1283, 15, 12) 5350 }; 5351 static uint32_t BCMI_QTC_XGXS_TX_X4_CL49_STS0_TX_PCS_LIVE_STSr_fields[] = 5352 { 5353 /* TX_LPI_RECEIVED:4:7 */ 5354 PHYMOD_SYMBOL_FIELD_ENCODE(1285, 7, 4), 5355 /* TX_REMOTE_FAULT:8:11 */ 5356 PHYMOD_SYMBOL_FIELD_ENCODE(1336, 11, 8), 5357 /* TX_LOCAL_FAULT:12:15 */ 5358 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1282, 15, 12) 5359 }; 5360 static uint32_t BCMI_QTC_XGXS_TX_X4_SP0_CRED0r_fields[] = 5361 { 5362 /* CLOCKCNT0:0:13 */ 5363 PHYMOD_SYMBOL_FIELD_ENCODE(289, 13, 0), 5364 /* CREDITENABLE:14:14 */ 5365 PHYMOD_SYMBOL_FIELD_ENCODE(321, 14, 14), 5366 /* SGMII_SPD_SWITCH:15:15 */ 5367 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1053, 15, 15) 5368 }; 5369 static uint32_t BCMI_QTC_XGXS_TX_X4_SP0_CRED1r_fields[] = 5370 { 5371 /* CLOCKCNT1:0:7 */ 5372 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(291, 7, 0) 5373 }; 5374 static uint32_t BCMI_QTC_XGXS_TX_X4_SP0_LOOPCNTr_fields[] = 5375 { 5376 /* LOOPCNT1:0:5 */ 5377 PHYMOD_SYMBOL_FIELD_ENCODE(636, 5, 0), 5378 /* LOOPCNT0:6:13 */ 5379 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(634, 13, 6) 5380 }; 5381 static uint32_t BCMI_QTC_XGXS_TX_X4_SP0_MAC_CREDGENCNTr_fields[] = 5382 { 5383 /* MAC_CREDITGENCNT:0:12 */ 5384 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(665, 12, 0) 5385 }; 5386 static uint32_t BCMI_QTC_XGXS_TX_X4_SP0_PCS_CLKCNT0r_fields[] = 5387 { 5388 /* PCS_CLOCKCNT0:0:13 */ 5389 PHYMOD_SYMBOL_FIELD_ENCODE(820, 13, 0), 5390 /* PCS_CREDITENABLE:14:14 */ 5391 PHYMOD_SYMBOL_FIELD_ENCODE(822, 14, 14), 5392 /* REPLICATION_CNT:15:15 */ 5393 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(955, 15, 15) 5394 }; 5395 static uint32_t BCMI_QTC_XGXS_TX_X4_SP0_PCS_CREDGENCNTr_fields[] = 5396 { 5397 /* PCS_CREDITGENCNT:0:12 */ 5398 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(824, 12, 0) 5399 }; 5400 static uint32_t BCMI_QTC_XGXS_TX_X4_SP1_CRED0r_fields[] = 5401 { 5402 /* CLOCKCNT0:0:13 */ 5403 PHYMOD_SYMBOL_FIELD_ENCODE(289, 13, 0), 5404 /* CREDITENABLE:14:14 */ 5405 PHYMOD_SYMBOL_FIELD_ENCODE(321, 14, 14), 5406 /* SGMII_SPD_SWITCH:15:15 */ 5407 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1053, 15, 15) 5408 }; 5409 static uint32_t BCMI_QTC_XGXS_TX_X4_SP1_CRED1r_fields[] = 5410 { 5411 /* CLOCKCNT1:0:7 */ 5412 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(291, 7, 0) 5413 }; 5414 static uint32_t BCMI_QTC_XGXS_TX_X4_SP1_LOOPCNTr_fields[] = 5415 { 5416 /* LOOPCNT1:0:5 */ 5417 PHYMOD_SYMBOL_FIELD_ENCODE(636, 5, 0), 5418 /* LOOPCNT0:6:13 */ 5419 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(634, 13, 6) 5420 }; 5421 static uint32_t BCMI_QTC_XGXS_TX_X4_SP1_MAC_CREDGENCNTr_fields[] = 5422 { 5423 /* MAC_CREDITGENCNT:0:12 */ 5424 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(665, 12, 0) 5425 }; 5426 static uint32_t BCMI_QTC_XGXS_TX_X4_SP1_PCS_CLKCNT0r_fields[] = 5427 { 5428 /* PCS_CLOCKCNT0:0:13 */ 5429 PHYMOD_SYMBOL_FIELD_ENCODE(820, 13, 0), 5430 /* PCS_CREDITENABLE:14:14 */ 5431 PHYMOD_SYMBOL_FIELD_ENCODE(822, 14, 14), 5432 /* REPLICATION_CNT:15:15 */ 5433 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(955, 15, 15) 5434 }; 5435 static uint32_t BCMI_QTC_XGXS_TX_X4_SP1_PCS_CREDGENCNTr_fields[] = 5436 { 5437 /* PCS_CREDITGENCNT:0:12 */ 5438 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(824, 12, 0) 5439 }; 5440 static uint32_t BCMI_QTC_XGXS_TX_X4_SP2_CRED0r_fields[] = 5441 { 5442 /* CLOCKCNT0:0:13 */ 5443 PHYMOD_SYMBOL_FIELD_ENCODE(289, 13, 0), 5444 /* CREDITENABLE:14:14 */ 5445 PHYMOD_SYMBOL_FIELD_ENCODE(321, 14, 14), 5446 /* SGMII_SPD_SWITCH:15:15 */ 5447 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1053, 15, 15) 5448 }; 5449 static uint32_t BCMI_QTC_XGXS_TX_X4_SP2_CRED1r_fields[] = 5450 { 5451 /* CLOCKCNT1:0:7 */ 5452 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(291, 7, 0) 5453 }; 5454 static uint32_t BCMI_QTC_XGXS_TX_X4_SP2_LOOPCNTr_fields[] = 5455 { 5456 /* LOOPCNT1:0:5 */ 5457 PHYMOD_SYMBOL_FIELD_ENCODE(636, 5, 0), 5458 /* LOOPCNT0:6:13 */ 5459 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(634, 13, 6) 5460 }; 5461 static uint32_t BCMI_QTC_XGXS_TX_X4_SP2_MAC_CREDGENCNTr_fields[] = 5462 { 5463 /* MAC_CREDITGENCNT:0:12 */ 5464 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(665, 12, 0) 5465 }; 5466 static uint32_t BCMI_QTC_XGXS_TX_X4_SP2_PCS_CLKCNT0r_fields[] = 5467 { 5468 /* PCS_CLOCKCNT0:0:13 */ 5469 PHYMOD_SYMBOL_FIELD_ENCODE(820, 13, 0), 5470 /* PCS_CREDITENABLE:14:14 */ 5471 PHYMOD_SYMBOL_FIELD_ENCODE(822, 14, 14), 5472 /* REPLICATION_CNT:15:15 */ 5473 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(955, 15, 15) 5474 }; 5475 static uint32_t BCMI_QTC_XGXS_TX_X4_SP2_PCS_CREDGENCNTr_fields[] = 5476 { 5477 /* PCS_CREDITGENCNT:0:12 */ 5478 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(824, 12, 0) 5479 }; 5480 static uint32_t BCMI_QTC_XGXS_TX_X4_SP3_CRED0r_fields[] = 5481 { 5482 /* CLOCKCNT0:0:13 */ 5483 PHYMOD_SYMBOL_FIELD_ENCODE(289, 13, 0), 5484 /* CREDITENABLE:14:14 */ 5485 PHYMOD_SYMBOL_FIELD_ENCODE(321, 14, 14), 5486 /* SGMII_SPD_SWITCH:15:15 */ 5487 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1053, 15, 15) 5488 }; 5489 static uint32_t BCMI_QTC_XGXS_TX_X4_SP3_CRED1r_fields[] = 5490 { 5491 /* CLOCKCNT1:0:7 */ 5492 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(291, 7, 0) 5493 }; 5494 static uint32_t BCMI_QTC_XGXS_TX_X4_SP3_LOOPCNTr_fields[] = 5495 { 5496 /* LOOPCNT1:0:5 */ 5497 PHYMOD_SYMBOL_FIELD_ENCODE(636, 5, 0), 5498 /* LOOPCNT0:6:13 */ 5499 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(634, 13, 6) 5500 }; 5501 static uint32_t BCMI_QTC_XGXS_TX_X4_SP3_MAC_CREDGENCNTr_fields[] = 5502 { 5503 /* MAC_CREDITGENCNT:0:12 */ 5504 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(665, 12, 0) 5505 }; 5506 static uint32_t BCMI_QTC_XGXS_TX_X4_SP3_PCS_CLKCNT0r_fields[] = 5507 { 5508 /* PCS_CLOCKCNT0:0:13 */ 5509 PHYMOD_SYMBOL_FIELD_ENCODE(820, 13, 0), 5510 /* PCS_CREDITENABLE:14:14 */ 5511 PHYMOD_SYMBOL_FIELD_ENCODE(822, 14, 14), 5512 /* REPLICATION_CNT:15:15 */ 5513 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(955, 15, 15) 5514 }; 5515 static uint32_t BCMI_QTC_XGXS_TX_X4_SP3_PCS_CREDGENCNTr_fields[] = 5516 { 5517 /* PCS_CREDITGENCNT:0:12 */ 5518 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(824, 12, 0) 5519 }; 5520 static uint32_t BCMI_QTC_XGXS_UC_ACK_CORE_CTLr_fields[] = 5521 { 5522 /* UC_ACK_CORE_CFG_DONE:0:0 */ 5523 PHYMOD_SYMBOL_FIELD_ENCODE(1342, 0, 0), 5524 /* UC_ACK_CORE_DP_RESET:1:1 */ 5525 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1343, 1, 1) 5526 }; 5527 static uint32_t BCMI_QTC_XGXS_UC_AHB_CTL0r_fields[] = 5528 { 5529 /* MICRO_RA_WRDATASIZE:0:1 */ 5530 PHYMOD_SYMBOL_FIELD_ENCODE(741, 1, 0), 5531 /* MICRO_RA_RDDATASIZE:4:5 */ 5532 PHYMOD_SYMBOL_FIELD_ENCODE(736, 5, 4), 5533 /* MICRO_RA_INIT:8:9 */ 5534 PHYMOD_SYMBOL_FIELD_ENCODE(732, 9, 8), 5535 /* MICRO_AUTOINC_WRADDR_EN:12:12 */ 5536 PHYMOD_SYMBOL_FIELD_ENCODE(692, 12, 12), 5537 /* MICRO_AUTOINC_RDADDR_EN:13:13 */ 5538 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(691, 13, 13) 5539 }; 5540 static uint32_t BCMI_QTC_XGXS_UC_AHB_RDADDR_LSWr_fields[] = 5541 { 5542 /* MICRO_RA_RDADDR_LSW:0:15 */ 5543 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(734, 15, 0) 5544 }; 5545 static uint32_t BCMI_QTC_XGXS_UC_AHB_RDADDR_MSWr_fields[] = 5546 { 5547 /* MICRO_RA_RDADDR_MSW:0:15 */ 5548 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(735, 15, 0) 5549 }; 5550 static uint32_t BCMI_QTC_XGXS_UC_AHB_RDDATA_LSWr_fields[] = 5551 { 5552 /* MICRO_RA_RDDATA_LSW:0:15 */ 5553 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(737, 15, 0) 5554 }; 5555 static uint32_t BCMI_QTC_XGXS_UC_AHB_RDDATA_MSWr_fields[] = 5556 { 5557 /* MICRO_RA_RDDATA_MSW:0:15 */ 5558 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(738, 15, 0) 5559 }; 5560 static uint32_t BCMI_QTC_XGXS_UC_AHB_STS0r_fields[] = 5561 { 5562 /* MICRO_RA_INITDONE:0:0 */ 5563 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(733, 0, 0) 5564 }; 5565 static uint32_t BCMI_QTC_XGXS_UC_AHB_WRADDR_LSWr_fields[] = 5566 { 5567 /* MICRO_RA_WRADDR_LSW:0:15 */ 5568 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(739, 15, 0) 5569 }; 5570 static uint32_t BCMI_QTC_XGXS_UC_AHB_WRADDR_MSWr_fields[] = 5571 { 5572 /* MICRO_RA_WRADDR_MSW:0:15 */ 5573 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(740, 15, 0) 5574 }; 5575 static uint32_t BCMI_QTC_XGXS_UC_AHB_WRDATA_LSWr_fields[] = 5576 { 5577 /* MICRO_RA_WRDATA_LSW:0:15 */ 5578 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(742, 15, 0) 5579 }; 5580 static uint32_t BCMI_QTC_XGXS_UC_AHB_WRDATA_MSWr_fields[] = 5581 { 5582 /* MICRO_RA_WRDATA_MSW:0:15 */ 5583 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(743, 15, 0) 5584 }; 5585 static uint32_t BCMI_QTC_XGXS_UC_CLK_CTL0r_fields[] = 5586 { 5587 /* MICRO_MASTER_CLK_EN:0:0 */ 5588 PHYMOD_SYMBOL_FIELD_ENCODE(707, 0, 0), 5589 /* MICRO_CORE_CLK_EN:1:1 */ 5590 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(695, 1, 1) 5591 }; 5592 static uint32_t BCMI_QTC_XGXS_UC_CODE_RAM_ECCCONTRO1r_fields[] = 5593 { 5594 /* MICRO_RA_ECC_WRDATA:0:6 */ 5595 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(731, 6, 0) 5596 }; 5597 static uint32_t BCMI_QTC_XGXS_UC_CODE_RAM_ECCCTL0r_fields[] = 5598 { 5599 /* MICRO_ECCG_MODE:0:0 */ 5600 PHYMOD_SYMBOL_FIELD_ENCODE(699, 0, 0), 5601 /* MICRO_ECC_FRC_DISABLE:1:1 */ 5602 PHYMOD_SYMBOL_FIELD_ENCODE(701, 1, 1), 5603 /* MICRO_ECC_CORRUPT:4:5 */ 5604 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(700, 5, 4) 5605 }; 5606 static uint32_t BCMI_QTC_XGXS_UC_CODE_RAM_ECCSTS0r_fields[] = 5607 { 5608 /* MICRO_CODE_RAM_ECC_ADDRESS:0:14 */ 5609 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(693, 14, 0) 5610 }; 5611 static uint32_t BCMI_QTC_XGXS_UC_CODE_RAM_ECCSTS1r_fields[] = 5612 { 5613 /* MICRO_RA_ECC_RDDATA:0:6 */ 5614 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(730, 6, 0) 5615 }; 5616 static uint32_t BCMI_QTC_XGXS_UC_CODE_RAM_TESTIFCTL0r_fields[] = 5617 { 5618 /* MICRO_CODE_RAM_TM:0:6 */ 5619 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(694, 6, 0) 5620 }; 5621 static uint32_t BCMI_QTC_XGXS_UC_PRAMIF_AHB_WRADDR_LSWr_fields[] = 5622 { 5623 /* MICRO_PRAMIF_AHB_WRADDR_LSW:2:15 */ 5624 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(717, 15, 2) 5625 }; 5626 static uint32_t BCMI_QTC_XGXS_UC_PRAMIF_AHB_WRADDR_MSWr_fields[] = 5627 { 5628 /* MICRO_PRAMIF_AHB_WRADDR_MSW:0:15 */ 5629 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(718, 15, 0) 5630 }; 5631 static uint32_t BCMI_QTC_XGXS_UC_PRAMIF_CTL0r_fields[] = 5632 { 5633 /* MICRO_PRAMIF_EN:0:0 */ 5634 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(719, 0, 0) 5635 }; 5636 static uint32_t BCMI_QTC_XGXS_UC_PVT_STS0r_fields[] = 5637 { 5638 /* MICRO_PVT_TEMPDATA_RMI:0:9 */ 5639 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(726, 9, 0) 5640 }; 5641 static uint32_t BCMI_QTC_XGXS_UC_RAM_CTL0r_fields[] = 5642 { 5643 /* MICRO_DR_LOOKTAB_EN:0:0 */ 5644 PHYMOD_SYMBOL_FIELD_ENCODE(697, 0, 0), 5645 /* MICRO_PROTECT_FWCODE:1:1 */ 5646 PHYMOD_SYMBOL_FIELD_ENCODE(721, 1, 1), 5647 /* MICRO_DR_SIZE:8:13 */ 5648 PHYMOD_SYMBOL_FIELD_ENCODE(698, 13, 8), 5649 /* MICRO_RAMCLK_NONINV:14:14 */ 5650 PHYMOD_SYMBOL_FIELD_ENCODE(727, 14, 14), 5651 /* MICRO_IGNORE_M0_CODE_WRITES:15:15 */ 5652 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(704, 15, 15) 5653 }; 5654 static uint32_t BCMI_QTC_XGXS_UC_RMI_AHB_CTL1r_fields[] = 5655 { 5656 /* MICRO_M0_HRESP_EN:0:0 */ 5657 PHYMOD_SYMBOL_FIELD_ENCODE(706, 0, 0), 5658 /* MICRO_SW_PMI_HP_RSTB:1:1 */ 5659 PHYMOD_SYMBOL_FIELD_ENCODE(763, 1, 1), 5660 /* MICRO_SW_PMI_HP_EXT_RSTB:2:2 */ 5661 PHYMOD_SYMBOL_FIELD_ENCODE(762, 2, 2), 5662 /* MICRO_PMI_HP_ACK_TIMEOUT_DIS:3:3 */ 5663 PHYMOD_SYMBOL_FIELD_ENCODE(709, 3, 3), 5664 /* MICRO_PMI_HP_EXT_ACK_TIMEOUT_DIS:4:4 */ 5665 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(710, 4, 4) 5666 }; 5667 static uint32_t BCMI_QTC_XGXS_UC_RMI_AHB_STS1r_fields[] = 5668 { 5669 /* MICRO_M0_DEFAULT_SLAVE_ERROR:0:0 */ 5670 PHYMOD_SYMBOL_FIELD_ENCODE(705, 0, 0), 5671 /* MICRO_RMI_DEFAULT_SLAVE_ERROR:1:1 */ 5672 PHYMOD_SYMBOL_FIELD_ENCODE(744, 1, 1), 5673 /* MICRO_PR_DEFAULT_SLAVE_ERROR:2:2 */ 5674 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(723, 2, 2) 5675 }; 5676 static uint32_t BCMI_QTC_XGXS_UC_RMI_EXT_INTR_CTL0r_fields[] = 5677 { 5678 /* MICRO_RMI_MBOX_MSGOUT_INTR_EN:0:0 */ 5679 PHYMOD_SYMBOL_FIELD_ENCODE(755, 0, 0), 5680 /* MICRO_RMI_ECC_CORR_ERR_INTR_EN:4:4 */ 5681 PHYMOD_SYMBOL_FIELD_ENCODE(745, 4, 4), 5682 /* MICRO_RMI_ECC_UNCORR_ERR_INTR_EN:5:5 */ 5683 PHYMOD_SYMBOL_FIELD_ENCODE(749, 5, 5), 5684 /* MICRO_RMI_ECC_MULTIROW_ERR_INTR_EN:6:6 */ 5685 PHYMOD_SYMBOL_FIELD_ENCODE(747, 6, 6), 5686 /* MICRO_RMI_M0_LOCKUP_INTR_EN:8:8 */ 5687 PHYMOD_SYMBOL_FIELD_ENCODE(751, 8, 8), 5688 /* MICRO_RMI_M0_SYSTEMRESETREQ_INTR_EN:9:9 */ 5689 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(753, 9, 9) 5690 }; 5691 static uint32_t BCMI_QTC_XGXS_UC_RMI_EXT_INTR_STS0r_fields[] = 5692 { 5693 /* MICRO_RMI_MBOX_MSGOUT_STATUS:0:0 */ 5694 PHYMOD_SYMBOL_FIELD_ENCODE(756, 0, 0), 5695 /* MICRO_RMI_ECC_CORR_ERR_STATUS:4:4 */ 5696 PHYMOD_SYMBOL_FIELD_ENCODE(746, 4, 4), 5697 /* MICRO_RMI_ECC_UNCORR_ERR_STATUS:5:5 */ 5698 PHYMOD_SYMBOL_FIELD_ENCODE(750, 5, 5), 5699 /* MICRO_RMI_ECC_MULTIROW_ERR_STATUS:6:6 */ 5700 PHYMOD_SYMBOL_FIELD_ENCODE(748, 6, 6), 5701 /* MICRO_RMI_M0_LOCKUP_STATUS:8:8 */ 5702 PHYMOD_SYMBOL_FIELD_ENCODE(752, 8, 8), 5703 /* MICRO_RMI_M0_SYSTEMRESETREQ_STATUS:9:9 */ 5704 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(754, 9, 9) 5705 }; 5706 static uint32_t BCMI_QTC_XGXS_UC_RMI_MBOX_CTL0r_fields[] = 5707 { 5708 /* MICRO_RMI_MBOX_SEND_MSGIN:0:0 */ 5709 PHYMOD_SYMBOL_FIELD_ENCODE(757, 0, 0), 5710 /* MICRO_GEN_INTR_RMI_MBOX0WR:1:1 */ 5711 PHYMOD_SYMBOL_FIELD_ENCODE(702, 1, 1), 5712 /* MICRO_GEN_INTR_RMI_MBOX1WR:2:2 */ 5713 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(703, 2, 2) 5714 }; 5715 static uint32_t BCMI_QTC_XGXS_UC_RMI_PMI_IF_CTL0r_fields[] = 5716 { 5717 /* MICRO_PMI_HP_FAST_READ_EN:0:0 */ 5718 PHYMOD_SYMBOL_FIELD_ENCODE(716, 0, 0), 5719 /* MICRO_PMI_HP_FAST_DUAL_META_FF_EN:1:1 */ 5720 PHYMOD_SYMBOL_FIELD_ENCODE(715, 1, 1), 5721 /* MICRO_PMI_HP_FAST_BKTOBK_EN:2:2 */ 5722 PHYMOD_SYMBOL_FIELD_ENCODE(714, 2, 2), 5723 /* MICRO_PMI_HP_EXT_FAST_READ_EN:8:8 */ 5724 PHYMOD_SYMBOL_FIELD_ENCODE(713, 8, 8), 5725 /* MICRO_PMI_HP_EXT_FAST_DUAL_META_FF_EN:9:9 */ 5726 PHYMOD_SYMBOL_FIELD_ENCODE(712, 9, 9), 5727 /* MICRO_PMI_HP_EXT_FAST_BKTOBK_EN:10:10 */ 5728 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(711, 10, 10) 5729 }; 5730 static uint32_t BCMI_QTC_XGXS_UC_RMI_PR_AINC_NXT_WRADDR_LSWr_fields[] = 5731 { 5732 /* MICRO_PR_AUTOINC_NXT_WRADDR_LSW:0:15 */ 5733 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(722, 15, 0) 5734 }; 5735 static uint32_t BCMI_QTC_XGXS_UC_RMI_PVT_CTL0r_fields[] = 5736 { 5737 /* MICRO_PVT_TEMPDATA_FRCVAL:0:9 */ 5738 PHYMOD_SYMBOL_FIELD_ENCODE(725, 9, 0), 5739 /* MICRO_PVT_TEMPDATA_FRC:12:12 */ 5740 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(724, 12, 12) 5741 }; 5742 static uint32_t BCMI_QTC_XGXS_UC_RMI_RA_AINC_NXT_RDADDR_LSWr_fields[] = 5743 { 5744 /* MICRO_RA_AUTOINC_NXT_RDADDR_LSW:0:15 */ 5745 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(728, 15, 0) 5746 }; 5747 static uint32_t BCMI_QTC_XGXS_UC_RMI_RA_AINC_NXT_WRADDR_LSWr_fields[] = 5748 { 5749 /* MICRO_RA_AUTOINC_NXT_WRADDR_LSW:0:15 */ 5750 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(729, 15, 0) 5751 }; 5752 static uint32_t BCMI_QTC_XGXS_UC_RMI_SILICON_DBG_CTL0r_fields[] = 5753 { 5754 /* MICRO_SILICON_DEBUG_STATUS_MUX_SEL:0:1 */ 5755 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(761, 1, 0) 5756 }; 5757 static uint32_t BCMI_QTC_XGXS_UC_RMI_SILICON_DBG_STS0r_fields[] = 5758 { 5759 /* MICRO_SILICON_DEBUG_STATUS_MUXED_DATA:0:15 */ 5760 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(760, 15, 0) 5761 }; 5762 static uint32_t BCMI_QTC_XGXS_UC_RMI_TO_UC_MBOX0r_fields[] = 5763 { 5764 /* MICRO_RMI_TO_MICRO_MBOX0:0:15 */ 5765 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(758, 15, 0) 5766 }; 5767 static uint32_t BCMI_QTC_XGXS_UC_RMI_TO_UC_MBOX1r_fields[] = 5768 { 5769 /* MICRO_RMI_TO_MICRO_MBOX1:0:15 */ 5770 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(759, 15, 0) 5771 }; 5772 static uint32_t BCMI_QTC_XGXS_UC_RST_CTL0r_fields[] = 5773 { 5774 /* MICRO_MASTER_RSTB:0:0 */ 5775 PHYMOD_SYMBOL_FIELD_ENCODE(708, 0, 0), 5776 /* MICRO_CORE_RSTB:1:1 */ 5777 PHYMOD_SYMBOL_FIELD_ENCODE(696, 1, 1), 5778 /* MICRO_PRAM_IF_RSTB:3:3 */ 5779 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(720, 3, 3) 5780 }; 5781 static uint32_t BCMI_QTC_XGXS_UC_UC_TO_RMI_MBOX0r_fields[] = 5782 { 5783 /* MICRO_TO_RMI_MBOX0:0:15 */ 5784 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(764, 15, 0) 5785 }; 5786 static uint32_t BCMI_QTC_XGXS_UC_UC_TO_RMI_MBOX1r_fields[] = 5787 { 5788 /* MICRO_TO_RMI_MBOX1:0:15 */ 5789 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(765, 15, 0) 5790 }; 5791 static uint32_t BCMI_QTC_XGXS_USXGMII_AM_INSERTION_INTERVALr_fields[] = 5792 { 5793 /* AM_INSERTION_INTERVAL:0:15 */ 5794 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(35, 15, 0) 5795 }; 5796 static uint32_t BCMI_QTC_XGXS_USXGMII_LN_0_AM_BYTE2r_fields[] = 5797 { 5798 /* LANE_0_AM_2:0:7 */ 5799 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(550, 7, 0) 5800 }; 5801 static uint32_t BCMI_QTC_XGXS_USXGMII_LN_0_AM_BYTES_1_0r_fields[] = 5802 { 5803 /* LANE_0_AM_1_0:0:15 */ 5804 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(549, 15, 0) 5805 }; 5806 static uint32_t BCMI_QTC_XGXS_USXGMII_LN_1_AM_BYTE2r_fields[] = 5807 { 5808 /* LANE_1_AM_2:0:7 */ 5809 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(552, 7, 0) 5810 }; 5811 static uint32_t BCMI_QTC_XGXS_USXGMII_LN_1_AM_BYTES_1_0r_fields[] = 5812 { 5813 /* LANE_1_AM_1_0:0:15 */ 5814 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(551, 15, 0) 5815 }; 5816 static uint32_t BCMI_QTC_XGXS_USXGMII_LN_2_AM_BYTE2r_fields[] = 5817 { 5818 /* LANE_2_AM_2:0:7 */ 5819 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(554, 7, 0) 5820 }; 5821 static uint32_t BCMI_QTC_XGXS_USXGMII_LN_2_AM_BYTES_1_0r_fields[] = 5822 { 5823 /* LANE_2_AM_1_0:0:15 */ 5824 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(553, 15, 0) 5825 }; 5826 static uint32_t BCMI_QTC_XGXS_USXGMII_LN_3_AM_BYTE2r_fields[] = 5827 { 5828 /* LANE_3_AM_2:0:7 */ 5829 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(556, 7, 0) 5830 }; 5831 static uint32_t BCMI_QTC_XGXS_USXGMII_LN_3_AM_BYTES_1_0r_fields[] = 5832 { 5833 /* LANE_3_AM_1_0:0:15 */ 5834 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(555, 15, 0) 5835 }; 5836 5837 5838 5839 /******************************************************************************* 5840 * 5841 * The following is the field name table. 5842 */ 5843 #if PHYMOD_CONFIG_INCLUDE_FIELD_NAMES == 1 5844 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_NAMES_BCMI_QTC_XGXS 5845 const char* bcmi_qtc_xgxs_fields[] = 5846 { 5847 "ACCEL_EN", 5848 "ACQ_CDR_TIMEOUT", 5849 "AFE_REV_ID", 5850 "AFE_RX_PWRDN", 5851 "AFE_RX_PWRDN_FRC", 5852 "AFE_RX_PWRDN_FRC_VAL", 5853 "AFE_RX_RESET", 5854 "AFE_RX_RESET_FRC", 5855 "AFE_RX_RESET_FRC_VAL", 5856 "AFE_SIGDET", 5857 "AFE_SIGDET_CHANGE", 5858 "AFE_SIGDET_PWRDN", 5859 "AFE_SIGDET_THRESH", 5860 "AFE_SIGNAL_DETECT_DIS", 5861 "AFE_S_PLL_PWRDN", 5862 "AFE_TXCLK_RESET", 5863 "AFE_TXCLK_RESET_FRC", 5864 "AFE_TXCLK_RESET_FRC_VAL", 5865 "AFE_TX_FIFO_RESETB", 5866 "AFE_TX_FIFO_RESETB_FRC_ON", 5867 "AFE_TX_PWRDN", 5868 "AFE_TX_PWRDN_FRC", 5869 "AFE_TX_PWRDN_FRC_VAL", 5870 "AFE_TX_RESET", 5871 "AFE_TX_RESET_DEASSERT", 5872 "AFE_TX_RESET_FRC", 5873 "AFE_TX_RESET_FRC_VAL", 5874 "AMS_SPARE_0_2", 5875 "AMS_SPARE_1_0", 5876 "AMS_SPARE_2_0", 5877 "AMS_SPARE_3_0", 5878 "AMS_SPARE_4_0", 5879 "AMS_SPARE_6_0", 5880 "AMS_SPARE_7_0", 5881 "AMS_SPARE_8_0", 5882 "AM_INSERTION_INTERVAL", 5883 "AM_LOCK", 5884 "AM_LOCK_CURRENT_STATE", 5885 "AM_LOCK_HISTORY_STATE", 5886 "AM_LOCK_LH", 5887 "AM_LOCK_LL", 5888 "AM_SEQUENCE_ERR", 5889 "AM_SPACING_ERR", 5890 "AN", 5891 "AN_ACTIVE", 5892 "AN_COMPLETE", 5893 "AN_COMPLETED_SW", 5894 "AN_FAIL_COUNT", 5895 "AN_FAIL_COUNT_LIMIT", 5896 "AN_GOOD_CHECK_TRAP", 5897 "AN_GOOD_TRAP", 5898 "AN_HCD_CL72", 5899 "AN_HCD_DUPLEX", 5900 "AN_HCD_FEC", 5901 "AN_HCD_HIGIG2", 5902 "AN_HCD_PAUSE", 5903 "AN_HCD_SPEED", 5904 "AN_HCD_SWITCH_TO_CL37", 5905 "AN_PRIORITY_1000M", 5906 "AN_PRIORITY_100M", 5907 "AN_PRIORITY_10M", 5908 "AN_PRIORITY_1GKX", 5909 "AN_PRIORITY_2P5GX1", 5910 "AN_RETRY_COUNT", 5911 "AN_RX_ST_CLK_TRANS_MISS", 5912 "AN_RX_ST_MV_PAIR", 5913 "AN_RX_ST_PAGE", 5914 "AN_RX_ST_PAGE_TOO_LONG", 5915 "AN_RX_ST_PAGE_TOO_SHORT", 5916 "AN_RX_ST_PULSE_TOO_LONG", 5917 "AN_RX_ST_PULSE_TOO_MODERATE", 5918 "AN_RX_ST_PULSE_TOO_SHORT", 5919 "AN_RX_ST_RUDI_CONFIG", 5920 "AN_RX_ST_RUDI_IDLE", 5921 "AN_RX_ST_RUDI_INVALID", 5922 "AN_RX_ST_STATE", 5923 "AN_ST_ABILITY_DETECT", 5924 "AN_ST_ACK_DETECT", 5925 "AN_ST_AN_ENABLE", 5926 "AN_ST_AN_GOOD_CHECK", 5927 "AN_ST_CL37_COMPLETE", 5928 "AN_ST_CL73_COMPLETE", 5929 "AN_ST_COMPLETE_ACK", 5930 "AN_ST_CONFIG_NONZERO", 5931 "AN_ST_CONFIG_RESTART", 5932 "AN_ST_CONSISTENCY_MISMATCH", 5933 "AN_ST_DISABLE_LINK", 5934 "AN_ST_ERROR_STATE", 5935 "AN_ST_HP_MODE", 5936 "AN_ST_IDLE_DETECT", 5937 "AN_ST_LINK_OK", 5938 "AN_ST_NEXT_PAGE_WAIT", 5939 "AN_ST_RESOLUTION_ERR", 5940 "AN_ST_RESTART", 5941 "AN_ST_RX_BP", 5942 "AN_ST_RX_INVALID_SEQ", 5943 "AN_ST_RX_MP_MISMATCH", 5944 "AN_ST_RX_MP_NULL", 5945 "AN_ST_RX_MP_OUI", 5946 "AN_ST_RX_MP_OVER1G", 5947 "AN_ST_RX_NP", 5948 "AN_ST_RX_NP_TOGGLE_ERR", 5949 "AN_ST_RX_SGMII_MISMATCH", 5950 "AN_ST_RX_UP_3", 5951 "AN_ST_RX_UP_OUI_MATCH", 5952 "AN_ST_RX_UP_OUI_MISMATCH", 5953 "AN_ST_SGMII_MODE", 5954 "AUTOCAL_CNT", 5955 "AUTOCAL_EN", 5956 "AUTO_LL_SELPATH_TX_DIS", 5957 "BAM_2P5GBASE_X", 5958 "BAND_IQBUF_CTR", 5959 "BAND_IQBUF_MUX", 5960 "BAND_IQBUF_SEL", 5961 "BERMON_CURRENT_STATE", 5962 "BERMON_HISTORY_STATE", 5963 "BER_COUNT", 5964 "BER_COUNT_SP0", 5965 "BER_COUNT_SP1", 5966 "BER_COUNT_SP2", 5967 "BER_COUNT_SP3", 5968 "BER_WINDOW_512", 5969 "BIAS_DIV_CTRL", 5970 "BIAS_EN", 5971 "BIAS_IQ_CTRL", 5972 "BIAS_VDD_SEL", 5973 "BLOCK_LOCK", 5974 "BLOCK_LOCK_LH", 5975 "BLOCK_LOCK_LL", 5976 "BONDING", 5977 "BR_PD_EN", 5978 "BYTE0", 5979 "BYTE1", 5980 "CALIB_ADJ", 5981 "CALIB_CAP_CHARGE_TIME", 5982 "CALIB_START", 5983 "CALIB_STEP_TIME", 5984 "CALREF_COUNTER", 5985 "CALSTATE_ONEHOT", 5986 "CALVCO_COUNTER", 5987 "CAL_PAUSE_EN", 5988 "CAL_PAUSE_REL", 5989 "CAL_STATE", 5990 "CAL_TH", 5991 "CAL_VALID", 5992 "CAP_DELAY", 5993 "CDR_BWSEL_INTEG_ACQCDR", 5994 "CDR_BWSEL_INTEG_EEE_ACQCDR", 5995 "CDR_BWSEL_INTEG_NORM", 5996 "CDR_BWSEL_PROP_ACQCDR", 5997 "CDR_BWSEL_PROP_EEE_ACQCDR", 5998 "CDR_BWSEL_PROP_NORM", 5999 "CDR_FREQ_EN", 6000 "CDR_FREQ_OVERRIDE_EN", 6001 "CDR_FREQ_OVERRIDE_VAL", 6002 "CDR_FRZ_FRC", 6003 "CDR_FRZ_FRC_VAL", 6004 "CDR_INTEG_REG", 6005 "CDR_INTEG_REG_CLR", 6006 "CDR_INTEG_SAT_SEL", 6007 "CDR_LM_OUTOFLOCK", 6008 "CDR_LM_THR_SEL", 6009 "CDR_PHASE_ERR", 6010 "CDR_PHASE_ERR_FRZ", 6011 "CDR_PHASE_SAT_CTRL", 6012 "CDR_QPHASE_MULT_EN", 6013 "CDR_SETTLE_TIMEOUT", 6014 "CDR_ZERO_POLARITY", 6015 "CL36BYTEDELETEMODE", 6016 "CL36BYTEDELETEMODE_OEN", 6017 "CL36TX_CATCH_ALL_8B10B_DIS", 6018 "CL36TX_LPI_EN", 6019 "CL36_BER_EN", 6020 "CL36_FORCE_COMMA_ALIGN_ENABLE", 6021 "CL36_RXSM_DEBUG_SP_SEL", 6022 "CL36_RXSM_ONEHOT_LATCHED_HI_STATUS", 6023 "CL36_RXSM_ONEHOT_LATCHED_LO_STATUS", 6024 "CL36_RXSM_STATE_SPN", 6025 "CL36_SYNCACQ_HIS_STATE_PER_LN", 6026 "CL36_SYNCACQ_STATE_CODED_PER_LN", 6027 "CL36_TXSM_STATE", 6028 "CL37_10G_VCO", 6029 "CL37_ACK_TIMER_PERIOD", 6030 "CL37_AN_DISABLE_RESET_DISABLE", 6031 "CL37_AN_RESTART", 6032 "CL37_AN_RESTART_RESET_DISABLE", 6033 "CL37_BAM_CODE", 6034 "CL37_BAM_ENABLE", 6035 "CL37_BAM_TO_SGMII_AUTO_ENABLE", 6036 "CL37_ENABLE", 6037 "CL37_ERROR_TIMER_PERIOD", 6038 "CL37_FULL_DUPLEX", 6039 "CL37_HALF_DUPLEX", 6040 "CL37_NEXT_PAGE", 6041 "CL37_PAUSE", 6042 "CL37_RESTART_TIMER_PERIOD", 6043 "CL37_SGMII_ENABLE", 6044 "CL37_SW_RESTART_RESET_DISABLE", 6045 "CL37_SYNC_STATUS_FILTER_TIMER_PERIOD", 6046 "CL49IEEE_ERRORED_BLOCKS_SP0", 6047 "CL49IEEE_ERRORED_BLOCKS_SP1", 6048 "CL49IEEE_ERRORED_BLOCKS_SP2", 6049 "CL49IEEE_ERRORED_BLOCKS_SP3", 6050 "CL49_BER_LIMIT", 6051 "CL49_LTXSM_STATE_SP0", 6052 "CL49_LTXSM_STATE_SP1", 6053 "CL49_LTXSM_STATE_SP2", 6054 "CL49_LTXSM_STATE_SP3", 6055 "CL49_RXSM_CURRENT_STATE_SP0", 6056 "CL49_RXSM_CURRENT_STATE_SP1", 6057 "CL49_RXSM_CURRENT_STATE_SP2", 6058 "CL49_RXSM_CURRENT_STATE_SP3", 6059 "CL49_RXSM_HISTORY_STATE_SP0", 6060 "CL49_RXSM_HISTORY_STATE_SP1", 6061 "CL49_RXSM_HISTORY_STATE_SP2", 6062 "CL49_RXSM_HISTORY_STATE_SP3", 6063 "CL49_RX_LF_ENABLE", 6064 "CL49_RX_RF_ENABLE", 6065 "CL49_R_TYPE_CODED_SP0", 6066 "CL49_R_TYPE_CODED_SP1", 6067 "CL49_R_TYPE_CODED_SP2", 6068 "CL49_R_TYPE_CODED_SP3", 6069 "CL49_TXSM_STATE_SP0", 6070 "CL49_TXSM_STATE_SP1", 6071 "CL49_TXSM_STATE_SP2", 6072 "CL49_TXSM_STATE_SP3", 6073 "CL49_TX_FAULT_DET_SP0", 6074 "CL49_TX_FAULT_DET_SP1", 6075 "CL49_TX_FAULT_DET_SP2", 6076 "CL49_TX_FAULT_DET_SP3", 6077 "CL49_TX_LF_ENABLE", 6078 "CL49_TX_RF_ENABLE", 6079 "CL49_T_TYPE_CODED_SP0", 6080 "CL49_T_TYPE_CODED_SP1", 6081 "CL49_T_TYPE_CODED_SP2", 6082 "CL49_T_TYPE_CODED_SP3", 6083 "CL72_BAD_MARKER_CNT", 6084 "CL72_BRK_RING_OSC", 6085 "CL72_CL93PRBS_POLY_SEL", 6086 "CL72_CTRL_FRAME_DLY", 6087 "CL72_DIS_MAX_WAIT_TIMER", 6088 "CL72_DME_CELL_BOUNDARY_CHK", 6089 "CL72_FRAME_CONSISTENCY_CHK_EN", 6090 "CL72_FRAME_LOCK", 6091 "CL72_GOOD_MARKER_CNT", 6092 "CL72_IEEE_FRAME_LOCK", 6093 "CL72_IEEE_LD_COEFF_UPDATE", 6094 "CL72_IEEE_LD_STATUS_REPORT", 6095 "CL72_IEEE_LP_COEFF_UPDATE", 6096 "CL72_IEEE_LP_STATUS_REPORT", 6097 "CL72_IEEE_RECEIVER_STATUS", 6098 "CL72_IEEE_RESTART_TRAINING", 6099 "CL72_IEEE_TRAINING_ENABLE", 6100 "CL72_IEEE_TRAINING_FAILURE", 6101 "CL72_IEEE_TRAINING_STATUS", 6102 "CL72_LD_XMT_STATUS_PAGE", 6103 "CL72_LOCAL_RX_READY", 6104 "CL72_MICRO_FRAME_LOCK_INT_EN", 6105 "CL72_MICRO_FRAME_LOCK_LSTATUS", 6106 "CL72_MICRO_STATUS_CHG_INT_EN", 6107 "CL72_MICRO_STATUS_CHG_LSTATUS", 6108 "CL72_MICRO_STATUS_RESP_INT_FRC", 6109 "CL72_MICRO_STATUS_RESP_INT_FRC_VAL", 6110 "CL72_MICRO_UPDATE_CHG_INT_EN", 6111 "CL72_MICRO_UPDATE_CHG_LSTATUS", 6112 "CL72_MICRO_UPDATE_REQ_INT_FRC", 6113 "CL72_MICRO_UPDATE_REQ_INT_FRC_VAL", 6114 "CL72_PPM_OFFSET_EN", 6115 "CL72_PRBS_MODE_SEL", 6116 "CL72_PRBS_SEED_SEL", 6117 "CL72_PRBS_SEED_VAL", 6118 "CL72_REMOTE_RX_READY", 6119 "CL72_RX_DP_LN_CLK_EN", 6120 "CL72_RX_SIGNAL_OK", 6121 "CL72_RX_TRAINING_EN", 6122 "CL72_STRICT_DME_CHK", 6123 "CL72_STRICT_MARKER_CHK", 6124 "CL72_SW_FRAME_LOCK", 6125 "CL72_SW_REMOTE_RX_READY", 6126 "CL72_SW_RX_TRAINED", 6127 "CL72_TIMER_EN", 6128 "CL72_TRAINING_FSM_SIGNAL_DETECT", 6129 "CL72_TR_COARSE_LOCK", 6130 "CL72_TXFIR_MAIN", 6131 "CL72_TXFIR_POST", 6132 "CL72_TXFIR_PRE", 6133 "CL72_TX_DP_LN_CLK_EN", 6134 "CL72_XMT_UPDATE_PAGE", 6135 "CLAUSE22", 6136 "CLOCKCNT0", 6137 "CLOCKCNT0_OEN", 6138 "CLOCKCNT1", 6139 "CLOCKCNT1_OEN", 6140 "CLR_CRCCNT", 6141 "CML_REFCLK_ADJ", 6142 "CML_REFCLK_BIAS", 6143 "CMOS_TPORT_EN", 6144 "CNTRL_RXDETECT_EN", 6145 "CNT_BIN_D_DREG", 6146 "CNT_BIN_D_MREG", 6147 "CNT_BIN_M1_MREG", 6148 "CNT_BIN_M1_PREG", 6149 "CNT_BIN_P1_DREG", 6150 "CNT_BIN_P1_PREG", 6151 "CNT_D_MINUS_M1", 6152 "CNT_D_MINUS_P1", 6153 "CONVERT_TAPS_TO_AFE", 6154 "CONVERT_TAPS_TO_AFE_ERROR", 6155 "CONVERT_TAPS_TO_AFE_INT_EN", 6156 "CORE_DP_H_RSTB", 6157 "CORE_DP_H_RSTB_OEN", 6158 "CORE_DP_RESET_STATE", 6159 "CORE_DP_S_RSTB", 6160 "CORE_MODE", 6161 "CORE_MODE_OEN", 6162 "CORE_REG_RESET_OCCURRED", 6163 "CORE_S_RSTB", 6164 "CPAR", 6165 "CP_BIAS", 6166 "CP_OPAMP_BIAS", 6167 "CRCERRCNT", 6168 "CREDITENABLE", 6169 "CREDITENABLE_OEN", 6170 "CTLE_GAIN_CTRL", 6171 "CURR_CTLE", 6172 "CURR_DFE_1", 6173 "CURR_DFE_2", 6174 "CURR_DFE_SUMMER", 6175 "CURR_IN_OFFSET", 6176 "CURR_PI", 6177 "CURR_SEL", 6178 "CURR_SIGDET", 6179 "CURR_VDDR_AFE", 6180 "CURR_VGA", 6181 "DATA_OFFSET_EVN_BIN", 6182 "DATA_OFFSET_ODD_BIN", 6183 "DBG_MASK_DIG_LPBK_EN", 6184 "DBG_PMD_RX_LOCK", 6185 "DBG_PMD_RX_LOCK_CHANGE", 6186 "DCC1_PHASE_FLIP", 6187 "DCC2_PHASE_FLIP", 6188 "DCC_EN", 6189 "DCOFF_CAL_TIMEOUT", 6190 "DC_OFFSET_BIN", 6191 "DC_OFFSET_EN", 6192 "DC_OFFSET_INV", 6193 "DC_OFFSET_PATTERN", 6194 "DC_OFFSET_PATTERN_BIT_EN", 6195 "DC_OFFSET_PATTERN_INV_EN", 6196 "DEBUG_CLR", 6197 "DESCRAMBLERMODE", 6198 "DFE_1_ACC_CLR", 6199 "DFE_1_CMN", 6200 "DFE_1_CMN_ONLY", 6201 "DFE_1_E", 6202 "DFE_1_EN", 6203 "DFE_1_ERR_GAIN", 6204 "DFE_1_ERR_SEL", 6205 "DFE_1_GRADIENT_INVERT", 6206 "DFE_1_INV_M1", 6207 "DFE_1_INV_P1", 6208 "DFE_1_O", 6209 "DFE_1_WANTS_NEGATIVE", 6210 "DFE_2_ACC_CLR", 6211 "DFE_2_CMN", 6212 "DFE_2_CMN_ONLY", 6213 "DFE_2_E", 6214 "DFE_2_EN", 6215 "DFE_2_ERR_GAIN", 6216 "DFE_2_ERR_SEL", 6217 "DFE_2_GRADIENT_INVERT", 6218 "DFE_2_INV_M1", 6219 "DFE_2_INV_P1", 6220 "DFE_2_O", 6221 "DFE_2_SE", 6222 "DFE_2_SO", 6223 "DFE_3_ACC_CLR", 6224 "DFE_3_CMN", 6225 "DFE_3_EN", 6226 "DFE_3_ERR_GAIN", 6227 "DFE_3_ERR_SEL", 6228 "DFE_3_GRADIENT_INVERT", 6229 "DFE_3_INV_M1", 6230 "DFE_3_INV_P1", 6231 "DFE_4_ACC_CLR", 6232 "DFE_4_CMN", 6233 "DFE_4_EN", 6234 "DFE_4_ERR_GAIN", 6235 "DFE_4_ERR_SEL", 6236 "DFE_4_GRADIENT_INVERT", 6237 "DFE_4_INV_M1", 6238 "DFE_4_INV_P1", 6239 "DFE_5_ACC_CLR", 6240 "DFE_5_CMN", 6241 "DFE_5_EN", 6242 "DFE_5_ERR_GAIN", 6243 "DFE_5_ERR_SEL", 6244 "DFE_5_GRADIENT_INVERT", 6245 "DFE_5_INV_M1", 6246 "DFE_5_INV_P1", 6247 "DFE_ACC_HYS_EN", 6248 "DFE_ALLOW_SIMULT", 6249 "DFE_EYE_CLOSURE_ERR_SEL", 6250 "DFE_HW_EYE_CLOSURE_EN", 6251 "DFE_LEAKY_LMS_EN", 6252 "DFE_LEAKY_LMS_UPD_DUR", 6253 "DFE_PATTERN", 6254 "DFE_PATTERN_BIT_EN", 6255 "DFE_UPDATE_GAIN", 6256 "DFE_VGA_UNFREEZE", 6257 "DIG_LPBK_EN", 6258 "DIG_LPBK_PD_BIAS_EN", 6259 "DIG_LPBK_PD_EARLY_IND", 6260 "DIG_LPBK_PD_FLT_BYPASS", 6261 "DIG_LPBK_PD_LATE_IND", 6262 "DIG_LPBK_PD_MODE", 6263 "DISABLE_ACK_TIMEOUT", 6264 "DISABLE_CARRIER_EXTEND", 6265 "DISABLE_CL49_BERMON", 6266 "DISABLE_REMOTE_FAULT_REPORTING", 6267 "DISABLE_XGMII_TO_GMII_ERR_HANDLING", 6268 "DISPARITY_ERR_NOT_CAUSE_LOSS_SYNC", 6269 "DIS_CAL", 6270 "DIV3O4O5", 6271 "DP_RESET_TX_DISABLE_DIS", 6272 "DSC_CLR_FRC", 6273 "DSC_CLR_FRC_VAL", 6274 "DSC_SM_GP_UC_REQ", 6275 "DSC_SM_READY_FOR_CMD", 6276 "DSC_SM_SCRATCH", 6277 "DSC_STATE", 6278 "DSC_STATE_EEE_ONE_HOT", 6279 "DSC_STATE_ONE_HOT", 6280 "DTE_XS", 6281 "DUPLEX_MODE_ECHO", 6282 "EDGE_COUNT_REFLESS_EN", 6283 "EEE_ACQ_CDR_TIMEOUT", 6284 "EEE_ANA_PWR_TIMEOUT", 6285 "EEE_CAPABILITY", 6286 "EEE_CAPABILITY_ECHO", 6287 "EEE_CDR_SETTLE_TIMEOUT", 6288 "EEE_CLOCK_CAPABILITY_ECHO", 6289 "EEE_CLOCK_STOP_CAPABILITY", 6290 "EEE_HW_TUNE_TIMEOUT", 6291 "EEE_LFSR_CNT", 6292 "EEE_MEASURE_CNT", 6293 "EEE_MEASURE_EN", 6294 "EEE_MODE_EN", 6295 "EEE_PHASE_ERR_OFFSET", 6296 "EEE_PHASE_ERR_OFFSET_EN", 6297 "EEE_QUIET_FROM_EEE_STATES", 6298 "EEE_QUIET_RX_AFE_PWRDWN_VAL", 6299 "ENABLE_OS_2", 6300 "ENABLE_OS_4", 6301 "ENABLE_TX_LANE", 6302 "ENB_10T", 6303 "ENB_16T", 6304 "ENB_8T", 6305 "ENERGY_DETECT", 6306 "ENERGY_DETECT_CHANGE", 6307 "ENERGY_DETECT_FRC", 6308 "ENERGY_DETECT_FRC_VAL", 6309 "ENERGY_DETECT_MASK_COUNT", 6310 "EN_20B_DEMUX", 6311 "EN_8P5G", 6312 "EN_8P5G_VCO", 6313 "EN_CALIB_N", 6314 "EN_CLK16", 6315 "EN_CLK33", 6316 "EN_CML_REFOUT_OVERWR", 6317 "EN_CMOS_REFCLK_CH_HIZ", 6318 "EN_CMOS_REFOUT_OVERWR", 6319 "EN_DFECLK", 6320 "EN_DFE_TAP_FB", 6321 "EN_HCUR_VCO", 6322 "EN_HGAIN", 6323 "EN_HIGH_CURRENT", 6324 "EN_HPF", 6325 "EN_I4IQBUF", 6326 "EN_MMD_HALFRATE", 6327 "EN_POST1", 6328 "EN_POST2", 6329 "EN_PRE", 6330 "EN_RCLK_REFOUT", 6331 "EN_RECCLKDIV", 6332 "EN_REFOUT_DIV", 6333 "EN_RXCK_TEST", 6334 "EN_RXCK_TESTPORT", 6335 "EN_SHUNTMODE", 6336 "EN_SIGDET_CALIB", 6337 "EN_SLOW", 6338 "EN_TEST_FRAC_CLK", 6339 "EN_VCCTRL", 6340 "EN_WCLK16", 6341 "EN_WCLK20", 6342 "EN_WCLK33", 6343 "ERRGEN_EN", 6344 "ERROR_MASK", 6345 "EXT_LOS_EN", 6346 "EXT_LOS_INV", 6347 "EXT_RANGE", 6348 "EXT_SIGDET", 6349 "EXT_SIGDET_CHANGE", 6350 "EXT_STATE", 6351 "FIFO_PHSDETECT_MODE", 6352 "FREQDET_TIME", 6353 "FREQDET_TIME_MSB", 6354 "FREQDET_WIN", 6355 "FREQ_UPD_EN_FRC", 6356 "FREQ_UPD_EN_FRC_VAL", 6357 "GBOX_OVERFLOW_ERR", 6358 "GBOX_UNDERRUN_ERR", 6359 "HALFSTEP_EN", 6360 "HEARTBEAT_COUNT_1US", 6361 "HIZ_1", 6362 "HI_BER", 6363 "HI_BER_LH", 6364 "HI_BER_LL", 6365 "HOLD_LOS_COUNT", 6366 "HOLD_SD_COUNT", 6367 "HWTUNE_OVR_WRITE_EN", 6368 "HWTUNE_OVR_WRITE_SEL", 6369 "HWTUNE_OVR_WRITE_VAL", 6370 "HW_DC_OFFSET_ERR_GAIN", 6371 "HW_DC_OFFSET_GRAD_INV", 6372 "HW_DC_OFFSET_HYS_EN", 6373 "HW_SLICER_OFFSET_EN", 6374 "HW_SLICER_OFFSET_ERR_GAIN", 6375 "HW_SLICER_OFFSET_GRAD_INV", 6376 "HW_SLICER_OFFSET_HYS_EN", 6377 "HW_SLICER_OFFSET_INV_DATA", 6378 "HW_SLICER_OFFSET_INV_M1", 6379 "HW_SLICER_OFFSET_INV_P1", 6380 "HW_TUNE_EN", 6381 "HW_TUNE_TIMEOUT", 6382 "I4DEADZONE", 6383 "IBIAS_OPAMP_CNTL", 6384 "IBIAS_PIBUF_CNTL", 6385 "IBIAS_PI_CNTL", 6386 "IGNORE_LINK_TIMER_PERIOD", 6387 "IGNORE_LP_MODE", 6388 "IGNORE_RX_MODE", 6389 "IPG_SIZE", 6390 "I_NDIV_DITHER_EN", 6391 "I_NDIV_FRAC_H", 6392 "I_NDIV_FRAC_L", 6393 "I_NDIV_INT", 6394 "I_PLL_FRAC_MODE", 6395 "I_PLL_SDM_PWRDNB", 6396 "LANE_0_AM_1_0", 6397 "LANE_0_AM_2", 6398 "LANE_1_AM_1_0", 6399 "LANE_1_AM_2", 6400 "LANE_2_AM_1_0", 6401 "LANE_2_AM_2", 6402 "LANE_3_AM_1_0", 6403 "LANE_3_AM_2", 6404 "LANE_DP_RESET_STATE", 6405 "LANE_MODE", 6406 "LANE_MODE_OEN", 6407 "LANE_REG_RESET_OCCURRED", 6408 "LANE_RESET_RELEASED", 6409 "LANE_RESET_RELEASED_INDEX", 6410 "LC_REFCLK_ADJ_1_0", 6411 "LC_REFCLK_ADJ_3_2", 6412 "LD_CONTROL_VALID", 6413 "LD_PAGE_0_PAGE_DATA", 6414 "LD_PAGE_1_PAGE_DATA", 6415 "LD_PAGE_2_PAGE_DATA", 6416 "LINKFAILTIMERQUAL_EN", 6417 "LINKFAILTIMER_DIS", 6418 "LINK_FAIL_INHIBIT_TIMER_NCL72_PERIOD", 6419 "LINK_STATUS", 6420 "LINK_STATUS_ECHO", 6421 "LINK_STATUS_LH_SP0", 6422 "LINK_STATUS_LH_SP1", 6423 "LINK_STATUS_LH_SP2", 6424 "LINK_STATUS_LH_SP3", 6425 "LINK_STATUS_LL_SP0", 6426 "LINK_STATUS_LL_SP1", 6427 "LINK_STATUS_LL_SP2", 6428 "LINK_STATUS_LL_SP3", 6429 "LINK_STATUS_SP0", 6430 "LINK_STATUS_SP1", 6431 "LINK_STATUS_SP2", 6432 "LINK_STATUS_SP3", 6433 "LINK_UP_TIMER_PERIOD", 6434 "LKDTREF_COUNTER", 6435 "LKDTREF_COUNTER_MSB", 6436 "LKDTVCO_COUNTER", 6437 "LKDTVCO_COUNTER_MSB", 6438 "LKDT_BYP", 6439 "LKDT_PAUSE_EN", 6440 "LKDT_PAUSE_REL", 6441 "LL_EN", 6442 "LL_FIFO_CTRL", 6443 "LL_FIFO_ZERO_OUT", 6444 "LL_POLARITY_FLIP", 6445 "LL_SELPATH_TX", 6446 "LN_DP_S_RSTB", 6447 "LN_RX_DP_H_RSTB", 6448 "LN_RX_DP_H_RSTB_OEN", 6449 "LN_RX_DP_S_RSTB", 6450 "LN_RX_H_PWRDN", 6451 "LN_RX_H_RSTB", 6452 "LN_RX_S_CLKGATE_FRC_ON", 6453 "LN_RX_S_COMCLK_FRC_ON", 6454 "LN_RX_S_COMCLK_SEL", 6455 "LN_RX_S_PWRDN", 6456 "LN_RX_S_RSTB", 6457 "LN_S_RSTB", 6458 "LN_TX_DP_H_RSTB", 6459 "LN_TX_DP_H_RSTB_OEN", 6460 "LN_TX_DP_S_RSTB", 6461 "LN_TX_H_PWRDN", 6462 "LN_TX_H_RSTB", 6463 "LN_TX_S_CLKGATE_FRC_ON", 6464 "LN_TX_S_COMCLK_FRC_ON", 6465 "LN_TX_S_COMCLK_SEL", 6466 "LN_TX_S_PWRDN", 6467 "LN_TX_S_RSTB", 6468 "LOCAL_FAULT", 6469 "LOCAL_FAULT_LH", 6470 "LOCAL_PCS_LOOPBACK_ENABLE", 6471 "LOCK_CURRENT_STATE", 6472 "LOCK_HISTORY_STATE", 6473 "LOG0_TO_PHY_RX_LNSWAP_SEL", 6474 "LOG0_TO_PHY_TX_LNSWAP_SEL", 6475 "LOG1_TO_PHY_RX_LNSWAP_SEL", 6476 "LOG1_TO_PHY_TX_LNSWAP_SEL", 6477 "LOG2_TO_PHY_RX_LNSWAP_SEL", 6478 "LOG2_TO_PHY_TX_LNSWAP_SEL", 6479 "LOG3_TO_PHY_RX_LNSWAP_SEL", 6480 "LOG3_TO_PHY_TX_LNSWAP_SEL", 6481 "LOOPCNT0", 6482 "LOOPCNT0_OEN", 6483 "LOOPCNT1", 6484 "LOOPCNT1_OEN", 6485 "LOS_FILTER_COUNT", 6486 "LOS_THRESH", 6487 "LOWLATENCY_EN", 6488 "LPI_EN", 6489 "LPI_ENABLE", 6490 "LPI_RECEIVED", 6491 "LPI_RECEIVED_LH", 6492 "LP_BASE_PAGE1_PAGE_DATA", 6493 "LP_BASE_PAGE2_PAGE_DATA", 6494 "LP_BASE_PAGE3_PAGE_DATA", 6495 "LP_MP1024_UP1_PAGE_DATA", 6496 "LP_MP1024_UP2_PAGE_DATA", 6497 "LP_MP1024_UP3_PAGE_DATA", 6498 "LP_MP1024_UP4_PAGE_DATA", 6499 "LP_MP5_UP1_PAGE_DATA", 6500 "LP_MP5_UP2_PAGE_DATA", 6501 "LP_MP5_UP3_PAGE_DATA", 6502 "LP_MP5_UP4_PAGE_DATA", 6503 "LP_PAGE_0_PAGE_DATA", 6504 "LP_PAGE_1_PAGE_DATA", 6505 "LP_PAGE_2_PAGE_DATA", 6506 "LP_STATUS_VALID", 6507 "M1_OFFSET_EVN_BIN", 6508 "M1_OFFSET_ODD_BIN", 6509 "M1_SIGN", 6510 "M1_THRESH_SEL", 6511 "M1_THRESH_ZERO", 6512 "MAC_CREDITGENCNT", 6513 "MAC_CREDITGENCNT_OEN", 6514 "MAC_TO_PCS_LANE_MAP_SEL_SGMII", 6515 "MAP_LF_TO_LINK_STATUS", 6516 "MAP_RF_TO_LINK_STATUS", 6517 "MASKDATA", 6518 "MASKDATA_BUS_ASSIGN", 6519 "MASTER_PORT_NUM", 6520 "MDIO_ADDR_DATA", 6521 "MDIO_AER", 6522 "MDIO_BLK_ADDR", 6523 "MDIO_BRCST_PORT_ADDR", 6524 "MDIO_DEVAD", 6525 "MDIO_DEV_AN_EN", 6526 "MDIO_DEV_CL22_EN", 6527 "MDIO_DEV_DTE_EN", 6528 "MDIO_DEV_PCS_EN", 6529 "MDIO_DEV_PHY_EN", 6530 "MDIO_DEV_PMD_EN", 6531 "MDIO_DRV_COMCLK", 6532 "MDIO_FUNCTION", 6533 "MDIO_MULTI_MMDS_EN", 6534 "MDIO_MULTI_PRTS_EN", 6535 "MEASURE_LFSR_CNT", 6536 "MEASURE_TIMEOUT", 6537 "MEAS_INCOMPLETE", 6538 "MICRO_AUTOINC_RDADDR_EN", 6539 "MICRO_AUTOINC_WRADDR_EN", 6540 "MICRO_CODE_RAM_ECC_ADDRESS", 6541 "MICRO_CODE_RAM_TM", 6542 "MICRO_CORE_CLK_EN", 6543 "MICRO_CORE_RSTB", 6544 "MICRO_DR_LOOKTAB_EN", 6545 "MICRO_DR_SIZE", 6546 "MICRO_ECCG_MODE", 6547 "MICRO_ECC_CORRUPT", 6548 "MICRO_ECC_FRC_DISABLE", 6549 "MICRO_GEN_INTR_RMI_MBOX0WR", 6550 "MICRO_GEN_INTR_RMI_MBOX1WR", 6551 "MICRO_IGNORE_M0_CODE_WRITES", 6552 "MICRO_M0_DEFAULT_SLAVE_ERROR", 6553 "MICRO_M0_HRESP_EN", 6554 "MICRO_MASTER_CLK_EN", 6555 "MICRO_MASTER_RSTB", 6556 "MICRO_PMI_HP_ACK_TIMEOUT_DIS", 6557 "MICRO_PMI_HP_EXT_ACK_TIMEOUT_DIS", 6558 "MICRO_PMI_HP_EXT_FAST_BKTOBK_EN", 6559 "MICRO_PMI_HP_EXT_FAST_DUAL_META_FF_EN", 6560 "MICRO_PMI_HP_EXT_FAST_READ_EN", 6561 "MICRO_PMI_HP_FAST_BKTOBK_EN", 6562 "MICRO_PMI_HP_FAST_DUAL_META_FF_EN", 6563 "MICRO_PMI_HP_FAST_READ_EN", 6564 "MICRO_PRAMIF_AHB_WRADDR_LSW", 6565 "MICRO_PRAMIF_AHB_WRADDR_MSW", 6566 "MICRO_PRAMIF_EN", 6567 "MICRO_PRAM_IF_RSTB", 6568 "MICRO_PROTECT_FWCODE", 6569 "MICRO_PR_AUTOINC_NXT_WRADDR_LSW", 6570 "MICRO_PR_DEFAULT_SLAVE_ERROR", 6571 "MICRO_PVT_TEMPDATA_FRC", 6572 "MICRO_PVT_TEMPDATA_FRCVAL", 6573 "MICRO_PVT_TEMPDATA_RMI", 6574 "MICRO_RAMCLK_NONINV", 6575 "MICRO_RA_AUTOINC_NXT_RDADDR_LSW", 6576 "MICRO_RA_AUTOINC_NXT_WRADDR_LSW", 6577 "MICRO_RA_ECC_RDDATA", 6578 "MICRO_RA_ECC_WRDATA", 6579 "MICRO_RA_INIT", 6580 "MICRO_RA_INITDONE", 6581 "MICRO_RA_RDADDR_LSW", 6582 "MICRO_RA_RDADDR_MSW", 6583 "MICRO_RA_RDDATASIZE", 6584 "MICRO_RA_RDDATA_LSW", 6585 "MICRO_RA_RDDATA_MSW", 6586 "MICRO_RA_WRADDR_LSW", 6587 "MICRO_RA_WRADDR_MSW", 6588 "MICRO_RA_WRDATASIZE", 6589 "MICRO_RA_WRDATA_LSW", 6590 "MICRO_RA_WRDATA_MSW", 6591 "MICRO_RMI_DEFAULT_SLAVE_ERROR", 6592 "MICRO_RMI_ECC_CORR_ERR_INTR_EN", 6593 "MICRO_RMI_ECC_CORR_ERR_STATUS", 6594 "MICRO_RMI_ECC_MULTIROW_ERR_INTR_EN", 6595 "MICRO_RMI_ECC_MULTIROW_ERR_STATUS", 6596 "MICRO_RMI_ECC_UNCORR_ERR_INTR_EN", 6597 "MICRO_RMI_ECC_UNCORR_ERR_STATUS", 6598 "MICRO_RMI_M0_LOCKUP_INTR_EN", 6599 "MICRO_RMI_M0_LOCKUP_STATUS", 6600 "MICRO_RMI_M0_SYSTEMRESETREQ_INTR_EN", 6601 "MICRO_RMI_M0_SYSTEMRESETREQ_STATUS", 6602 "MICRO_RMI_MBOX_MSGOUT_INTR_EN", 6603 "MICRO_RMI_MBOX_MSGOUT_STATUS", 6604 "MICRO_RMI_MBOX_SEND_MSGIN", 6605 "MICRO_RMI_TO_MICRO_MBOX0", 6606 "MICRO_RMI_TO_MICRO_MBOX1", 6607 "MICRO_SILICON_DEBUG_STATUS_MUXED_DATA", 6608 "MICRO_SILICON_DEBUG_STATUS_MUX_SEL", 6609 "MICRO_SW_PMI_HP_EXT_RSTB", 6610 "MICRO_SW_PMI_HP_RSTB", 6611 "MICRO_TO_RMI_MBOX0", 6612 "MICRO_TO_RMI_MBOX1", 6613 "MICRO_TX_DISABLE", 6614 "MMD_RESETB", 6615 "MODEL_NUMBER", 6616 "MULTICAST_MASK_CONTROL", 6617 "MULTICAST_MASK_CONTROL_STATUS", 6618 "MULTIPRTS_EN", 6619 "NUMBER_PKT", 6620 "OC_2X", 6621 "OFFSET_PD", 6622 "OS2X_MODE_EVEN_ODD", 6623 "OSR_MODE", 6624 "OSR_MODE_FRC", 6625 "OSR_MODE_FRC_VAL", 6626 "OSR_MODE_PIN", 6627 "OSX2P_PHERR_GAIN", 6628 "OS_MODE", 6629 "OS_MODE_OEN", 6630 "OUI_CONTROL", 6631 "OUI_LOWER_DATA", 6632 "OUI_UPPER_DATA", 6633 "OVER1G_ABILITY", 6634 "OVER1G_PAGE_COUNT", 6635 "P1_EYEDIAG_BIN", 6636 "P1_EYEDIAG_EN", 6637 "P1_HWTUNE_MAX", 6638 "P1_HWTUNE_MIN", 6639 "P1_OFFSET", 6640 "P1_OFFSET_EN", 6641 "P1_OFFSET_EVN_BIN", 6642 "P1_OFFSET_ODD_BIN", 6643 "P1_OFF_3LEVELQ_EN", 6644 "P1_THRESH_SEL", 6645 "P1_WANTS_TO_GO_HIGH", 6646 "P1_WANTS_TO_GO_LOW", 6647 "PATTERN_SEL", 6648 "PATT_GEN_EN", 6649 "PATT_GEN_SEQ_0", 6650 "PATT_GEN_SEQ_1", 6651 "PATT_GEN_SEQ_10", 6652 "PATT_GEN_SEQ_11", 6653 "PATT_GEN_SEQ_12", 6654 "PATT_GEN_SEQ_13", 6655 "PATT_GEN_SEQ_14", 6656 "PATT_GEN_SEQ_2", 6657 "PATT_GEN_SEQ_3", 6658 "PATT_GEN_SEQ_4", 6659 "PATT_GEN_SEQ_5", 6660 "PATT_GEN_SEQ_6", 6661 "PATT_GEN_SEQ_7", 6662 "PATT_GEN_SEQ_8", 6663 "PATT_GEN_SEQ_9", 6664 "PATT_GEN_START_POS", 6665 "PATT_GEN_STOP_POS", 6666 "PAYLOAD_TYPE", 6667 "PCS_CLOCKCNT0", 6668 "PCS_CLOCKCNT0_OEN", 6669 "PCS_CREDITENABLE", 6670 "PCS_CREDITENABLE_OEN", 6671 "PCS_CREDITGENCNT", 6672 "PCS_CREDITGENCNT_OEN", 6673 "PCS_XS", 6674 "PD_CH_P1", 6675 "PD_CL37_COMPLETED", 6676 "PD_COMPLETED", 6677 "PD_HCD_KX4_OR_KX", 6678 "PD_IN_PROGRESS", 6679 "PD_PHASEDET", 6680 "PF2_LOWP_CTRL", 6681 "PFD_OFFSET", 6682 "PFD_OFFSET_ENLARGE", 6683 "PF_CTRL", 6684 "PF_HIZ", 6685 "PHASE_ERR_OFFSET", 6686 "PHASE_ERR_OFFSET_EN", 6687 "PHASE_ERR_OFFSET_MULT_2", 6688 "PHY_XS", 6689 "PIPELINE_RESET_COUNT", 6690 "PI_PD", 6691 "PKTGEN_EN", 6692 "PKT_SIZE", 6693 "PLLCLKSEL", 6694 "PLLFORCE_FDONE", 6695 "PLLFORCE_FDONE_EN", 6696 "PLLPON_MUX", 6697 "PLLPON_SEL", 6698 "PLL_CLKVCO_CAL_INVERT", 6699 "PLL_FAIL_STKY", 6700 "PLL_FORCE_CAP_PASS", 6701 "PLL_FORCE_CAP_PASS_EN", 6702 "PLL_LOCK", 6703 "PLL_LOCK_BAR_STKY", 6704 "PLL_LOCK_FRC", 6705 "PLL_LOCK_FRC_VAL", 6706 "PLL_LOCK_LH", 6707 "PLL_LOCK_LL", 6708 "PLL_LOCK_OVRD", 6709 "PLL_LOCK_STS", 6710 "PLL_LOCK_TIMED_OUT", 6711 "PLL_LOCK_TIMER_PERIOD", 6712 "PLL_PON", 6713 "PLL_PWRDN", 6714 "PLL_PWRDN_OR", 6715 "PLL_RANGE", 6716 "PLL_RESET_EN", 6717 "PLL_SEQ_START", 6718 "PLL_SPARE6_1", 6719 "PLL_SPARE_0_0", 6720 "PLL_SPARE_0_1", 6721 "PLL_SPARE_1_0", 6722 "PMA_PMD", 6723 "PMD_CORE_DP_H_RSTB_PKILL", 6724 "PMD_CORE_MODE", 6725 "PMD_LANE_MODE", 6726 "PMD_LN_DP_H_RSTB_PKILL", 6727 "PMD_LN_H_RSTB_PKILL", 6728 "PMD_LN_RX_DP_H_RSTB_PKILL", 6729 "PMD_LN_RX_H_PWRDN_PKILL", 6730 "PMD_LN_RX_H_RSTB_PKILL", 6731 "PMD_LN_TX_DP_H_RSTB_PKILL", 6732 "PMD_LN_TX_H_PWRDN_PKILL", 6733 "PMD_LN_TX_H_RSTB_PKILL", 6734 "PMD_LOCK_TIMED_OUT", 6735 "PMD_LOCK_TIMER_PERIOD", 6736 "PMD_MDIO_TRANS_PKILL", 6737 "PMD_RX_CLK_VLD_FRC", 6738 "PMD_RX_CLK_VLD_FRC_VAL", 6739 "PMD_RX_LOCK", 6740 "PMD_RX_LOCK_CHANGE", 6741 "PMD_SIGNAL_DETECT", 6742 "PMD_TX_CLK_VLD_FRC", 6743 "PMD_TX_CLK_VLD_FRC_VAL", 6744 "PMD_TX_DISABLE_PKILL", 6745 "PMD_VCOCLK16_VLD_FRC", 6746 "PMD_VCOCLK16_VLD_FRC_VAL", 6747 "POR_H_RSTB", 6748 "POST2TO1", 6749 "PRAM_ABILITY", 6750 "PRBS_CHK_BURST_ERR_CNT", 6751 "PRBS_CHK_BURST_ERR_CNT_EN", 6752 "PRBS_CHK_CLK_EN_FRC_ON", 6753 "PRBS_CHK_EN", 6754 "PRBS_CHK_EN_AUTO_MODE", 6755 "PRBS_CHK_EN_TIMEOUT", 6756 "PRBS_CHK_EN_TIMER_MODE", 6757 "PRBS_CHK_ERR_CNT_BURST_MODE", 6758 "PRBS_CHK_ERR_CNT_LSB", 6759 "PRBS_CHK_ERR_CNT_MSB", 6760 "PRBS_CHK_ERR_CNT_NO_CLR", 6761 "PRBS_CHK_INV", 6762 "PRBS_CHK_LOCK", 6763 "PRBS_CHK_LOCK_CNT", 6764 "PRBS_CHK_LOCK_LOST_LH", 6765 "PRBS_CHK_MODE", 6766 "PRBS_CHK_MODE_SEL", 6767 "PRBS_CHK_OOL_CNT", 6768 "PRBS_GEN_EN", 6769 "PRBS_GEN_ERR_INS", 6770 "PRBS_GEN_INV", 6771 "PRBS_GEN_MODE_SEL", 6772 "PRESERVE_PREAMBLE", 6773 "PRTAD_BCST", 6774 "PWDB_EXTR_D2C", 6775 "PWRDN_SEQ_TIMER", 6776 "QSGMII_EN", 6777 "QSGMII_EN_OEN", 6778 "RCM_SUM", 6779 "RECCLKDIV", 6780 "REFCALM", 6781 "REFCALMCS", 6782 "REFCALP", 6783 "REFCALPCS", 6784 "REFCALSHUNT", 6785 "REFCLK_DIV2_FRC_VAL", 6786 "REFCLK_DIV4_FRC_VAL", 6787 "REFCLK_DIV_FRC", 6788 "REFCLK_IN_BIAS", 6789 "REFCLK_SEL", 6790 "REFCLK_TERM_FRC", 6791 "REFDIV_TEST_SEL", 6792 "REFOUT_DIV_SEL", 6793 "REF_CML_CURX2", 6794 "REF_CML_PD", 6795 "REF_CMOS_HZ", 6796 "REGID1", 6797 "REGID2", 6798 "REMOTE_FAULT", 6799 "REMOTE_FAULT_IN_BASE_PAGE", 6800 "REMOTE_FAULT_LH", 6801 "REMOTE_PCS_LOOPBACK_ENABLE", 6802 "REPLICATION_CNT", 6803 "REPLICATION_CNT_OEN", 6804 "RESCAL", 6805 "RESERVED_ORDERED_SET_LH", 6806 "RESTART_PI_EXT_MODE", 6807 "RESTART_PMD_RESTART", 6808 "RESTART_SIGDET", 6809 "REVID2", 6810 "REVID_BONDING", 6811 "REVID_CL72", 6812 "REVID_EEE", 6813 "REVID_LLP", 6814 "REVID_MDIO", 6815 "REVID_MICRO", 6816 "REVID_MODEL", 6817 "REVID_MULTIPLICITY", 6818 "REVID_PIR", 6819 "REVID_PROCESS", 6820 "REVID_REV_LETTER", 6821 "REVID_REV_NUMBER", 6822 "REV_LETTER", 6823 "REV_NUMBER", 6824 "RMT_LPBK_EN", 6825 "RMT_LPBK_PD_EARLY_IND", 6826 "RMT_LPBK_PD_FRC_ON", 6827 "RMT_LPBK_PD_LATE_IND", 6828 "RMT_LPBK_PD_MODE", 6829 "RPAR", 6830 "RSTB_LANE", 6831 "RSTB_TX_LANE", 6832 "RST_SEQ_DIS_FLT_MODE", 6833 "RST_SEQ_TIMER", 6834 "RUNNING_DISPARITY_ERR_MSK", 6835 "RXDTCT_TH_SEL", 6836 "RXPKTCNT_L", 6837 "RXPKTCNT_U", 6838 "RXPON_MUX", 6839 "RXPON_SEL", 6840 "RX_AGGREGATOR_BYPASS_EN", 6841 "RX_BUS_TYPE", 6842 "RX_CLK_VLD_LH", 6843 "RX_CLK_VLD_LL", 6844 "RX_CLK_VLD_OVRD", 6845 "RX_CLK_VLD_STS", 6846 "RX_CM_SEL", 6847 "RX_DFE_OS2X_MODE", 6848 "RX_DME_EN", 6849 "RX_DME_EN_OEN", 6850 "RX_DSC_LOCK", 6851 "RX_DSC_LOCK_FRC", 6852 "RX_DSC_LOCK_FRC_VAL", 6853 "RX_GBOX_AFRST_EN", 6854 "RX_LANE_ADDR_0", 6855 "RX_LANE_ADDR_1", 6856 "RX_LANE_ADDR_2", 6857 "RX_LANE_ADDR_3", 6858 "RX_LANE_DP_RESET_STATE", 6859 "RX_LANE_REG_RESET_OCCURRED", 6860 "RX_LN_DP_S_RSTB", 6861 "RX_LN_S_RSTB", 6862 "RX_LOCK_LH", 6863 "RX_LOCK_LL", 6864 "RX_LOCK_OVRD", 6865 "RX_LOCK_STS", 6866 "RX_MODE", 6867 "RX_MULTICAST_MASK_CONTROL", 6868 "RX_MULTICAST_MASK_CONTROL_STATUS", 6869 "RX_OSR_MODE", 6870 "RX_OSR_MODE_FRC", 6871 "RX_OSR_MODE_FRC_VAL", 6872 "RX_OSR_MODE_OEN", 6873 "RX_OSR_MODE_PIN", 6874 "RX_PI_MANUAL_MODE", 6875 "RX_PI_MANUAL_RESET", 6876 "RX_PI_MANUAL_STROBE", 6877 "RX_PI_PHASE_STEP_CNT", 6878 "RX_PI_PHASE_STEP_DIR", 6879 "RX_PI_SLICERS_EN", 6880 "RX_PKT_CHECK_EN", 6881 "RX_PMD_DP_INVERT", 6882 "RX_PON", 6883 "RX_PORT_SEL", 6884 "RX_RESTART_PMD", 6885 "RX_RESTART_PMD_HOLD", 6886 "RX_UC_ACK_LANE_CFG_DONE", 6887 "RX_UC_ACK_LANE_DP_RESET", 6888 "SCRAMBLERMODE", 6889 "SC_BYPASS", 6890 "SC_FSM_STATUS", 6891 "SC_IGNORE_TX_DATA_VLD", 6892 "SDK_TX_DISABLE", 6893 "SELI1P25DFE", 6894 "SEL_FP3CAP", 6895 "SEL_TXMASTER", 6896 "SEQ_UNEXPECTED_PAGE", 6897 "SET_MEAS_INCOMPLETE", 6898 "SGMII_FULL_DUPLEX", 6899 "SGMII_MASTER_MODE", 6900 "SGMII_SPD_SWITCH", 6901 "SGMII_SPD_SWITCH_OEN", 6902 "SGMII_SPEED", 6903 "SGMII_TIMER", 6904 "SGMII_TO_CL37_AUTO_ENABLE", 6905 "SHIFT_AMMOUNT", 6906 "SHIFT_AMOUNT", 6907 "SHIM_FF_THRESHOLD_100M", 6908 "SHIM_FF_THRESHOLD_10M", 6909 "SHIM_FF_THRESHOLD_1G", 6910 "SHIM_FF_THRESHOLD_2P5G", 6911 "SHIM_RX_CLK_GATE_DISABLE", 6912 "SHIM_TX_CLK_GATE_DISABLE", 6913 "SHNTEN_MAIN", 6914 "SHNTMAIN_POST1", 6915 "SHNTMAIN_POST1PRE", 6916 "SHNTMAIN_POST2", 6917 "SHNTPOST1_POST1", 6918 "SHNTPOST1_POST1PRE", 6919 "SHNTPOST2_POST2", 6920 "SHNTPRE_POST1PRE", 6921 "SIGDET_BYPASS", 6922 "SIGDET_CALIBRATION_SELECT", 6923 "SIGDET_DP_RSTB_EN", 6924 "SIGDET_OFFSET_CORRECTION_NEG", 6925 "SIGDET_OFFSET_CORRECTION_POS", 6926 "SIGDET_PWRDN", 6927 "SIGDET_THRESHOLD", 6928 "SIGNAL_DETECT", 6929 "SIGNAL_DETECT_CHANGE", 6930 "SIGNAL_DETECT_FILTER_1US", 6931 "SIGNAL_DETECT_FILTER_COUNT", 6932 "SIGNAL_DETECT_FRC", 6933 "SIGNAL_DETECT_FRC_VAL", 6934 "SIGNAL_DETECT_LH", 6935 "SIGNAL_DETECT_LL", 6936 "SIGNAL_DETECT_OVRD", 6937 "SIGNAL_DETECT_RAW", 6938 "SIGNAL_DETECT_RAW_CHANGE", 6939 "SIGNAL_DETECT_STS", 6940 "SIGNAL_DETECT_THRESH", 6941 "SINGLE_PORT_MODE", 6942 "SLCR_CALIB_RANGE_SEL", 6943 "SLICER_CAL_BYPASS", 6944 "SLICER_CAL_DONE", 6945 "SLICER_CAL_DONE_CLEAR", 6946 "SLICER_CAL_TIMEOUT", 6947 "SPARE0", 6948 "SPARE1", 6949 "SPEED", 6950 "SPEED_ECHO", 6951 "SPEED_SP0", 6952 "SPEED_SP1", 6953 "SPEED_SP2", 6954 "SPEED_SP3", 6955 "ST_AFE_TX_FIFO_RESETB", 6956 "SUBP_TO_SEE_SC", 6957 "SUM_GAIN_CTRL", 6958 "SUM_PSEUDO_DIFF", 6959 "SUP_RST_SEQ_FRC", 6960 "SUP_RST_SEQ_FRC_VAL", 6961 "SWAP_LMS_DATA", 6962 "SWAP_LMS_M1", 6963 "SW_AN", 6964 "SW_HCD", 6965 "SW_SPEED", 6966 "SW_SPEED_CHANGE", 6967 "SW_SPEED_CHANGE_DONE", 6968 "SW_SPEED_CONFIG_VLD", 6969 "SYNCE_DIVISOR0", 6970 "SYNCE_DIVISOR1", 6971 "SYNCE_DIVISOR2", 6972 "SYNCE_DIVISOR3", 6973 "SYNCE_MODE0_PHY_LN0", 6974 "SYNCE_MODE0_PHY_LN1", 6975 "SYNCE_MODE0_PHY_LN2", 6976 "SYNCE_MODE0_PHY_LN3", 6977 "SYNCE_MODE1_PHY_LN0", 6978 "SYNCE_MODE1_PHY_LN1", 6979 "SYNCE_MODE1_PHY_LN2", 6980 "SYNCE_MODE1_PHY_LN3", 6981 "SYNC_ACQ_STATUS_DEBUG_SP_SEL", 6982 "SYNC_STATUS_LH_SP0", 6983 "SYNC_STATUS_LH_SP1", 6984 "SYNC_STATUS_LH_SP2", 6985 "SYNC_STATUS_LH_SP3", 6986 "SYNC_STATUS_LL_SP0", 6987 "SYNC_STATUS_LL_SP1", 6988 "SYNC_STATUS_LL_SP2", 6989 "SYNC_STATUS_LL_SP3", 6990 "SYNC_STATUS_SP0", 6991 "SYNC_STATUS_SP1", 6992 "SYNC_STATUS_SP2", 6993 "SYNC_STATUS_SP3", 6994 "TC", 6995 "TDR_BIT_SEL", 6996 "TDR_CYCLE_BIN", 6997 "TDR_CYCLE_SEL", 6998 "TDR_TRNSUM_EN", 6999 "TECH_PROC", 7000 "TERM_CMULT_ENA", 7001 "TERM_CM_EN", 7002 "TERM_CM_ENA", 7003 "TERM_LOWZGND", 7004 "TERM_LOWZVDD", 7005 "TERM_SEL", 7006 "TESTCLK_ENA", 7007 "TESTSEL", 7008 "TEST_AMP", 7009 "TEST_SEL", 7010 "TEST_SEL_OVERWRITE", 7011 "TEST_VC", 7012 "TICKSEL", 7013 "TICK_DENOMINATOR", 7014 "TICK_NUMERATOR_LOWER", 7015 "TICK_NUMERATOR_UPPER", 7016 "TICK_OVERRIDE", 7017 "TIMER_DONE_FRC", 7018 "TIMER_DONE_FRC_VAL", 7019 "TLA_LN_SEQUENCER_FSM_STATUS", 7020 "TLA_LN_SEQUENCER_FSM_STATUS1", 7021 "TRNSUM_CLR_FRC", 7022 "TRNSUM_CLR_FRC_VAL", 7023 "TRNSUM_CLR_SC", 7024 "TRNSUM_DISABLE_SM_CLEAR", 7025 "TRNSUM_EDGE_PATTERN_EN", 7026 "TRNSUM_EN", 7027 "TRNSUM_ERROR_COUNT_EN", 7028 "TRNSUM_ERR_SEL", 7029 "TRNSUM_EYE_CLOSE_PREV_EN", 7030 "TRNSUM_EYE_CLOSURE_EN", 7031 "TRNSUM_EYE_CLOSURE_ERR_SEL", 7032 "TRNSUM_E_HIGH", 7033 "TRNSUM_E_LOW", 7034 "TRNSUM_FRZ_FRC", 7035 "TRNSUM_FRZ_FRC_VAL", 7036 "TRNSUM_GAIN", 7037 "TRNSUM_HIGH", 7038 "TRNSUM_INV_PATTERN_EN", 7039 "TRNSUM_LOW", 7040 "TRNSUM_O_HIGH", 7041 "TRNSUM_O_LOW", 7042 "TRNSUM_PATTERN", 7043 "TRNSUM_PATTERN_BIT_EN", 7044 "TRNSUM_PATTERN_FULL_CHECK_OFF", 7045 "TRNSUM_PATTERN_MATCH_SEL", 7046 "TRNSUM_PRBS_SEL", 7047 "TRNSUM_RANDOM_TAPSEL_DISABLE", 7048 "TRNSUM_TAP_EN", 7049 "TRNSUM_TAP_RANGE_SEL", 7050 "TRNSUM_TAP_SIGN", 7051 "TRNSUM_UNSIGNED_CORR", 7052 "TRNSUM_UNSIGNED_FLIP", 7053 "TXCOM_CL72_MAX_WAIT_TIMER_PERIOD", 7054 "TXCOM_CL72_WAIT_CNTR_LIMIT", 7055 "TXFIR_DC_LEVEL_0P5X", 7056 "TXFIR_DC_LEVEL_1X", 7057 "TXFIR_DC_LEVEL_2X_0", 7058 "TXFIR_DC_LEVEL_2X_1", 7059 "TXFIR_DC_LEVEL_POST1PRE_1X_0", 7060 "TXFIR_DC_LEVEL_POST1PRE_1X_1", 7061 "TXFIR_DC_LEVEL_POST1PRE_2X_0", 7062 "TXFIR_DC_LEVEL_POST1PRE_2X_1", 7063 "TXFIR_DC_LEVEL_POST1PRE_2X_2", 7064 "TXFIR_DC_LEVEL_POST1PRE_2X_3", 7065 "TXFIR_DC_LEVEL_POST1_1X_0", 7066 "TXFIR_DC_LEVEL_POST1_1X_1", 7067 "TXFIR_DC_LEVEL_POST1_2X_0", 7068 "TXFIR_DC_LEVEL_POST1_2X_1", 7069 "TXFIR_DC_LEVEL_POST1_2X_2", 7070 "TXFIR_DC_LEVEL_POST2_1X_0", 7071 "TXFIR_DC_LEVEL_POST2_1X_1", 7072 "TXFIR_DC_LEVEL_POST2_2X_0", 7073 "TXFIR_DC_LEVEL_POST2_2X_1", 7074 "TXFIR_POST1_POST1PRE_1X_0", 7075 "TXFIR_POST1_POST1PRE_1X_1", 7076 "TXFIR_POST1_POST1PRE_2X_0", 7077 "TXFIR_POST1_POST1PRE_2X_1", 7078 "TXFIR_POST1_POST1PRE_2X_2", 7079 "TXFIR_POST1_POST1PRE_2X_3", 7080 "TXFIR_POST1_POST1_1X_0", 7081 "TXFIR_POST1_POST1_1X_1", 7082 "TXFIR_POST1_POST1_2X_0", 7083 "TXFIR_POST1_POST1_2X_1", 7084 "TXFIR_POST1_POST1_2X_2", 7085 "TXFIR_POST2", 7086 "TXFIR_POST2_POST2_1X_0", 7087 "TXFIR_POST2_POST2_1X_1", 7088 "TXFIR_POST2_POST2_2X_0", 7089 "TXFIR_POST2_POST2_2X_1", 7090 "TXFIR_PRE_POST1PRE_1X_0", 7091 "TXFIR_PRE_POST1PRE_1X_1", 7092 "TXFIR_PRE_POST1PRE_2X_0", 7093 "TXFIR_PRE_POST1PRE_2X_1", 7094 "TXFIR_PRE_POST1PRE_2X_2", 7095 "TXFIR_PRE_POST1PRE_2X_3", 7096 "TXPKTCNT_L", 7097 "TXPKTCNT_U", 7098 "TXPON_MUX", 7099 "TXPON_SEL", 7100 "TX_BUS_TYPE", 7101 "TX_CLK_VLD_LH", 7102 "TX_CLK_VLD_LL", 7103 "TX_CLK_VLD_OVRD", 7104 "TX_CLK_VLD_STS", 7105 "TX_DISABLE", 7106 "TX_DISABLE_OEN", 7107 "TX_DISABLE_OUTPUT_SEL", 7108 "TX_DISABLE_STATUS", 7109 "TX_DISABLE_TIMER_CTRL", 7110 "TX_DISABLE_TRIGGER", 7111 "TX_EEE_ALERT_EN", 7112 "TX_EEE_QUIET_EN", 7113 "TX_ELEC_IDLE_STATUS", 7114 "TX_FIFO_OVFB", 7115 "TX_FIFO_OVFB_FALL_EDGE_LH", 7116 "TX_FIFO_RESETB", 7117 "TX_FIFO_WATERMARK", 7118 "TX_LANE_ADDR_0", 7119 "TX_LANE_ADDR_1", 7120 "TX_LANE_ADDR_2", 7121 "TX_LANE_ADDR_3", 7122 "TX_LANE_DP_RESET_STATE", 7123 "TX_LANE_RATE_MISMATCH", 7124 "TX_LANE_REG_RESET_OCCURRED", 7125 "TX_LANE_RESET_RELEASED", 7126 "TX_LANE_RESET_RELEASED_INDEX", 7127 "TX_LN_DP_S_RSTB", 7128 "TX_LN_S_RSTB", 7129 "TX_LOCAL_FAULT", 7130 "TX_LOCAL_FAULT_LH", 7131 "TX_LPI_ENABLE", 7132 "TX_LPI_RECEIVED", 7133 "TX_LPI_RECEIVED_LH", 7134 "TX_MODE", 7135 "TX_MULTICAST_MASK_CONTROL", 7136 "TX_MULTICAST_MASK_CONTROL_STATUS", 7137 "TX_MUX_SEL_ORDER", 7138 "TX_OSR_MODE", 7139 "TX_OSR_MODE_FRC", 7140 "TX_OSR_MODE_FRC_VAL", 7141 "TX_OSR_MODE_OEN", 7142 "TX_OSR_MODE_PIN", 7143 "TX_PCS_NATIVE_ANA_FRMT_EN", 7144 "TX_PI_EN", 7145 "TX_PI_EXT_CTRL_EN", 7146 "TX_PI_EXT_PD_SEL", 7147 "TX_PI_EXT_PHASE_BWSEL_INTEG", 7148 "TX_PI_FIRST_ORDER_BWSEL_INTEG", 7149 "TX_PI_FRC_PHASE_STEP_MUX_SEL", 7150 "TX_PI_FREQ_OVERRIDE_EN", 7151 "TX_PI_FREQ_OVERRIDE_VAL", 7152 "TX_PI_FRZ_FRC", 7153 "TX_PI_FRZ_FRC_VAL", 7154 "TX_PI_FRZ_MODE", 7155 "TX_PI_HS_FIFO_PHSERR", 7156 "TX_PI_HS_FIFO_PHSERR_INVERT", 7157 "TX_PI_INTEG1_REG", 7158 "TX_PI_INTEG2_REG", 7159 "TX_PI_JITTER_FILTER_EN", 7160 "TX_PI_JIT_AMP", 7161 "TX_PI_JIT_FREQ_IDX", 7162 "TX_PI_JIT_SSC_FREQ_MODE", 7163 "TX_PI_LOOP_FILTER_STABLE", 7164 "TX_PI_PD_BYPASS_FLT", 7165 "TX_PI_PD_BYPASS_VCO", 7166 "TX_PI_PHASE_CNTR", 7167 "TX_PI_PHASE_ERR", 7168 "TX_PI_PHASE_INVERT", 7169 "TX_PI_PHASE_OVERRIDE", 7170 "TX_PI_PHASE_STEP_DIR", 7171 "TX_PI_PHASE_STEP_NUM", 7172 "TX_PI_PHASE_STROBE", 7173 "TX_PI_REPEATER_MODE_EN", 7174 "TX_PI_RESET_CODE_DBG", 7175 "TX_PI_SECOND_ORDER_BWSEL_INTEG", 7176 "TX_PI_SECOND_ORDER_LOOP_EN", 7177 "TX_PI_SJ_GEN_EN", 7178 "TX_PI_SSC_GEN_EN", 7179 "TX_PMD_DP_INVERT", 7180 "TX_PON", 7181 "TX_PORT_SEL", 7182 "TX_PWRDN", 7183 "TX_REMOTE_FAULT", 7184 "TX_REMOTE_FAULT_LH", 7185 "TX_RESERVED_ORDERED_SET_LH", 7186 "TX_RESET_COUNT", 7187 "TX_UC_ACK_LANE_CFG_DONE", 7188 "TX_UC_ACK_LANE_DP_RESET", 7189 "UC_ACK_CORE_CFG_DONE", 7190 "UC_ACK_CORE_DP_RESET", 7191 "UC_ACK_DSC_CONFIG", 7192 "UC_ACK_DSC_EEE_DONE", 7193 "UC_ACK_DSC_RESTART", 7194 "UC_ACK_LANE_CFG_DONE", 7195 "UC_ACK_LANE_DP_RESET", 7196 "UC_ACTIVE", 7197 "UC_AFE_SIGDET", 7198 "UC_AFE_SIGDET_CHANGE", 7199 "UC_DSC_ERROR_FOUND", 7200 "UC_DSC_GP_UC_REQ", 7201 "UC_DSC_READY_FOR_CMD", 7202 "UC_DSC_SCRATCH", 7203 "UC_DSC_SUPP_INFO", 7204 "UC_EXT_SIGDET", 7205 "UC_EXT_SIGDET_CHANGE", 7206 "UC_PMD_RX_LOCK", 7207 "UC_PMD_RX_LOCK_CHANGE", 7208 "UC_SIGNAL_DETECT", 7209 "UC_SIGNAL_DETECT_CHANGE", 7210 "UC_TRNSUM_EN", 7211 "UC_TUNE_EN", 7212 "USXGMII_EN", 7213 "VCOBUFPON_MUX", 7214 "VCOBUFPON_SEL", 7215 "VCOBUF_PON", 7216 "VCOCLK16_S_COMCLK_FRC_ON", 7217 "VCOCLK16_S_COMCLK_SEL", 7218 "VCOFB_DIV", 7219 "VCOPON_MUX", 7220 "VCOPON_SEL", 7221 "VCORANGE_SEL", 7222 "VCO_GM_BOOST", 7223 "VCO_HKVCO", 7224 "VCO_I_BOOST", 7225 "VCO_PON", 7226 "VCO_RANGE", 7227 "VCO_RANGE_MUX", 7228 "VCO_RST_EN", 7229 "VCO_SUPPLY_ADJ", 7230 "VCO_TEST_CLK_EN", 7231 "VGA1_CTRL_BIN", 7232 "VGA2_CTRL_BIN", 7233 "VGA3_CTRL_BIN", 7234 "VGAPON_MUX", 7235 "VGAPON_SEL", 7236 "VGA_ACC_HYS_EN", 7237 "VGA_AFFECTED_BY_DFE1", 7238 "VGA_BIN", 7239 "VGA_CM_SEL", 7240 "VGA_EN", 7241 "VGA_EN_HGAIN", 7242 "VGA_ERR_GAIN", 7243 "VGA_ERR_SEL", 7244 "VGA_HWTUNE_MIN", 7245 "VGA_INV_M1", 7246 "VGA_INV_P1", 7247 "VGA_OP_SHORT_NORM", 7248 "VGA_OP_SHORT_OFFCAL", 7249 "VGA_OUT_IDLE", 7250 "VGA_P1_ACC_CLR", 7251 "VGA_P1_GRADIENT_INVERT", 7252 "VGA_PATTERN", 7253 "VGA_PATTERN_BIT_EN", 7254 "VGA_PON", 7255 "VGA_UPDATE_GAIN", 7256 "VGA_UPDATE_STYLE", 7257 "VGA_WANTS_TO_GO_LOW", 7258 "WIS", 7259 }; 7260 7261 #endif 7262 #endif 7263 #endif 7264 #endif /* PHYMOD_CONFIG_INCLUDE_FIELD_INFO */ 7265 7266 7267 7268 /******************************************************************************* 7269 * 7270 * The following is the symbol table itself. 7271 * It defines the entries for all registers and memories. 7272 * It also incorporates the field information for each register and memory if 7273 * applicable. 7274 */ 7275 static const phymod_symbol_t bcmi_qtc_xgxs_syms[] = { 7276 #ifndef PHYMOD_CONFIG_EXCLUDE_CHIP_SYMBOLS_BCMI_QTC_XGXS 7277 { 7278 BCMI_QTC_XGXS_PHYID2r, 7279 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7280 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 7281 BCMI_QTC_XGXS_PHYID2r_fields, 7282 #else 7283 0, 7284 #endif 7285 #endif 7286 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7287 PHYMOD_SYMBOL_FLAG_REGISTER, 7288 "PHYID2r", 7289 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7290 "CL22_B0_PHYID2", 7291 NULL, 7292 #endif 7293 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7294 0x600d, /* 24589 */ 7295 0, 7296 #endif 7297 }, 7298 { 7299 BCMI_QTC_XGXS_PHYID3r, 7300 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7301 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 7302 BCMI_QTC_XGXS_PHYID3r_fields, 7303 #else 7304 0, 7305 #endif 7306 #endif 7307 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7308 PHYMOD_SYMBOL_FLAG_REGISTER, 7309 "PHYID3r", 7310 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7311 "CL22_B0_PHYID3", 7312 NULL, 7313 #endif 7314 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7315 0x8770, /* 34672 */ 7316 0, 7317 #endif 7318 }, 7319 { 7320 BCMI_QTC_XGXS_MAIN_SETUPr, 7321 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7322 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 7323 BCMI_QTC_XGXS_MAIN_SETUPr_fields, 7324 #else 7325 0, 7326 #endif 7327 #endif 7328 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7329 PHYMOD_SYMBOL_FLAG_REGISTER, 7330 "MAIN_SETUPr", 7331 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7332 NULL, 7333 NULL, 7334 #endif 7335 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7336 0xd0, /* 208 */ 7337 0, 7338 #endif 7339 }, 7340 { 7341 BCMI_QTC_XGXS_MAIN_LN_SWPr, 7342 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7343 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 7344 BCMI_QTC_XGXS_MAIN_LN_SWPr_fields, 7345 #else 7346 0, 7347 #endif 7348 #endif 7349 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7350 PHYMOD_SYMBOL_FLAG_REGISTER, 7351 "MAIN_LN_SWPr", 7352 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7353 "MAIN_LANE_SWAP", 7354 NULL, 7355 #endif 7356 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7357 0xe4e4, /* 58596 */ 7358 0, 7359 #endif 7360 }, 7361 { 7362 BCMI_QTC_XGXS_MAIN_DEVINPKG5r, 7363 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7364 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 7365 BCMI_QTC_XGXS_MAIN_DEVINPKG5r_fields, 7366 #else 7367 0, 7368 #endif 7369 #endif 7370 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7371 PHYMOD_SYMBOL_FLAG_REGISTER, 7372 "MAIN_DEVINPKG5r", 7373 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7374 "MAIN_DEVICEINPKG5", 7375 NULL, 7376 #endif 7377 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7378 0x83, /* 131 */ 7379 0, 7380 #endif 7381 }, 7382 { 7383 BCMI_QTC_XGXS_MAIN_TICK_CTL1r, 7384 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7385 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 7386 BCMI_QTC_XGXS_MAIN_TICK_CTL1r_fields, 7387 #else 7388 0, 7389 #endif 7390 #endif 7391 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7392 PHYMOD_SYMBOL_FLAG_REGISTER, 7393 "MAIN_TICK_CTL1r", 7394 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7395 "MAIN_TICK_CONTROL_1", 7396 NULL, 7397 #endif 7398 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7399 0x0, /* 0 */ 7400 0, 7401 #endif 7402 }, 7403 { 7404 BCMI_QTC_XGXS_MAIN_TICK_CTL0r, 7405 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7406 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 7407 BCMI_QTC_XGXS_MAIN_TICK_CTL0r_fields, 7408 #else 7409 0, 7410 #endif 7411 #endif 7412 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7413 PHYMOD_SYMBOL_FLAG_REGISTER, 7414 "MAIN_TICK_CTL0r", 7415 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7416 "MAIN_TICK_CONTROL_0", 7417 NULL, 7418 #endif 7419 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7420 0x0, /* 0 */ 7421 0, 7422 #endif 7423 }, 7424 { 7425 BCMI_QTC_XGXS_MAIN_LPBK_CTLr, 7426 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7427 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 7428 BCMI_QTC_XGXS_MAIN_LPBK_CTLr_fields, 7429 #else 7430 0, 7431 #endif 7432 #endif 7433 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7434 PHYMOD_SYMBOL_FLAG_REGISTER, 7435 "MAIN_LPBK_CTLr", 7436 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7437 "MAIN_LOOPBACK_CONTROL", 7438 NULL, 7439 #endif 7440 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7441 0x0, /* 0 */ 7442 0, 7443 #endif 7444 }, 7445 { 7446 BCMI_QTC_XGXS_MAIN_MDIO_BCSTr, 7447 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7448 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 7449 BCMI_QTC_XGXS_MAIN_MDIO_BCSTr_fields, 7450 #else 7451 0, 7452 #endif 7453 #endif 7454 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7455 PHYMOD_SYMBOL_FLAG_REGISTER, 7456 "MAIN_MDIO_BCSTr", 7457 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7458 "MAIN_MDIO_BROADCAST", 7459 NULL, 7460 #endif 7461 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7462 0xf800, /* 63488 */ 7463 0, 7464 #endif 7465 }, 7466 { 7467 BCMI_QTC_XGXS_MAIN_SERDESIDr, 7468 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7469 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 7470 BCMI_QTC_XGXS_MAIN_SERDESIDr_fields, 7471 #else 7472 0, 7473 #endif 7474 #endif 7475 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7476 PHYMOD_SYMBOL_FLAG_REGISTER, 7477 "MAIN_SERDESIDr", 7478 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7479 NULL, 7480 NULL, 7481 #endif 7482 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7483 0x316, /* 790 */ 7484 0, 7485 #endif 7486 }, 7487 { 7488 BCMI_QTC_XGXS_MAIN_SYNCE_CTLr, 7489 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7490 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 7491 BCMI_QTC_XGXS_MAIN_SYNCE_CTLr_fields, 7492 #else 7493 0, 7494 #endif 7495 #endif 7496 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7497 PHYMOD_SYMBOL_FLAG_REGISTER, 7498 "MAIN_SYNCE_CTLr", 7499 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7500 "MAIN_SYNCE_CONTROL", 7501 NULL, 7502 #endif 7503 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7504 0x8888, /* 34952 */ 7505 0, 7506 #endif 7507 }, 7508 { 7509 BCMI_QTC_XGXS_MAIN_SYNCE_DIVISOR0_PHY_LN0r, 7510 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7511 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 7512 BCMI_QTC_XGXS_MAIN_SYNCE_DIVISOR0_PHY_LN0r_fields, 7513 #else 7514 0, 7515 #endif 7516 #endif 7517 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7518 PHYMOD_SYMBOL_FLAG_REGISTER, 7519 "MAIN_SYNCE_DIVISOR0_PHY_LN0r", 7520 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7521 NULL, 7522 NULL, 7523 #endif 7524 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7525 0x14a0, /* 5280 */ 7526 0, 7527 #endif 7528 }, 7529 { 7530 BCMI_QTC_XGXS_MAIN_SYNCE_DIVISOR1_PHY_LN1r, 7531 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7532 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 7533 BCMI_QTC_XGXS_MAIN_SYNCE_DIVISOR1_PHY_LN1r_fields, 7534 #else 7535 0, 7536 #endif 7537 #endif 7538 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7539 PHYMOD_SYMBOL_FLAG_REGISTER, 7540 "MAIN_SYNCE_DIVISOR1_PHY_LN1r", 7541 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7542 NULL, 7543 NULL, 7544 #endif 7545 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7546 0x14a0, /* 5280 */ 7547 0, 7548 #endif 7549 }, 7550 { 7551 BCMI_QTC_XGXS_MAIN_SYNCE_DIVISOR2_PHY_LN2r, 7552 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7553 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 7554 BCMI_QTC_XGXS_MAIN_SYNCE_DIVISOR2_PHY_LN2r_fields, 7555 #else 7556 0, 7557 #endif 7558 #endif 7559 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7560 PHYMOD_SYMBOL_FLAG_REGISTER, 7561 "MAIN_SYNCE_DIVISOR2_PHY_LN2r", 7562 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7563 NULL, 7564 NULL, 7565 #endif 7566 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7567 0x14a0, /* 5280 */ 7568 0, 7569 #endif 7570 }, 7571 { 7572 BCMI_QTC_XGXS_MAIN_SYNCE_DIVISOR3_PHY_LN3r, 7573 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7574 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 7575 BCMI_QTC_XGXS_MAIN_SYNCE_DIVISOR3_PHY_LN3r_fields, 7576 #else 7577 0, 7578 #endif 7579 #endif 7580 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7581 PHYMOD_SYMBOL_FLAG_REGISTER, 7582 "MAIN_SYNCE_DIVISOR3_PHY_LN3r", 7583 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7584 NULL, 7585 NULL, 7586 #endif 7587 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7588 0x14a0, /* 5280 */ 7589 0, 7590 #endif 7591 }, 7592 { 7593 BCMI_QTC_XGXS_MAIN_UNIMAC_SHIM_CLKr, 7594 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7595 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 7596 BCMI_QTC_XGXS_MAIN_UNIMAC_SHIM_CLKr_fields, 7597 #else 7598 0, 7599 #endif 7600 #endif 7601 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7602 PHYMOD_SYMBOL_FLAG_REGISTER, 7603 "MAIN_UNIMAC_SHIM_CLKr", 7604 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7605 NULL, 7606 NULL, 7607 #endif 7608 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7609 0x0, /* 0 */ 7610 0, 7611 #endif 7612 }, 7613 { 7614 BCMI_QTC_XGXS_MAIN_SHIM_FF_THRr, 7615 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7616 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 7617 BCMI_QTC_XGXS_MAIN_SHIM_FF_THRr_fields, 7618 #else 7619 0, 7620 #endif 7621 #endif 7622 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7623 PHYMOD_SYMBOL_FLAG_REGISTER, 7624 "MAIN_SHIM_FF_THRr", 7625 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7626 "MAIN_SHIM_FF_THRESHOLD", 7627 NULL, 7628 #endif 7629 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7630 0x111, /* 273 */ 7631 0, 7632 #endif 7633 }, 7634 { 7635 BCMI_QTC_XGXS_PMD_X1_CTLr, 7636 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7637 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 7638 BCMI_QTC_XGXS_PMD_X1_CTLr_fields, 7639 #else 7640 0, 7641 #endif 7642 #endif 7643 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7644 PHYMOD_SYMBOL_FLAG_REGISTER, 7645 "PMD_X1_CTLr", 7646 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7647 "PMD_X1_CONTROL", 7648 NULL, 7649 #endif 7650 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7651 0x0, /* 0 */ 7652 0, 7653 #endif 7654 }, 7655 { 7656 BCMI_QTC_XGXS_PMD_X1_MODEr, 7657 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7658 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 7659 BCMI_QTC_XGXS_PMD_X1_MODEr_fields, 7660 #else 7661 0, 7662 #endif 7663 #endif 7664 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7665 PHYMOD_SYMBOL_FLAG_REGISTER, 7666 "PMD_X1_MODEr", 7667 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7668 NULL, 7669 NULL, 7670 #endif 7671 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7672 0x0, /* 0 */ 7673 0, 7674 #endif 7675 }, 7676 { 7677 BCMI_QTC_XGXS_PMD_X1_STSr, 7678 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7679 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 7680 BCMI_QTC_XGXS_PMD_X1_STSr_fields, 7681 #else 7682 0, 7683 #endif 7684 #endif 7685 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7686 PHYMOD_SYMBOL_FLAG_REGISTER, 7687 "PMD_X1_STSr", 7688 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7689 "PMD_X1_STATUS", 7690 NULL, 7691 #endif 7692 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7693 0x0, /* 0 */ 7694 0, 7695 #endif 7696 }, 7697 { 7698 BCMI_QTC_XGXS_PMD_X1_LATCH_STSr, 7699 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7700 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 7701 BCMI_QTC_XGXS_PMD_X1_LATCH_STSr_fields, 7702 #else 7703 0, 7704 #endif 7705 #endif 7706 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7707 PHYMOD_SYMBOL_FLAG_REGISTER, 7708 "PMD_X1_LATCH_STSr", 7709 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7710 "PMD_X1_LATCH_STATUS", 7711 NULL, 7712 #endif 7713 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7714 0x0, /* 0 */ 7715 0, 7716 #endif 7717 }, 7718 { 7719 BCMI_QTC_XGXS_PMD_X1_OVRRr, 7720 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7721 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 7722 BCMI_QTC_XGXS_PMD_X1_OVRRr_fields, 7723 #else 7724 0, 7725 #endif 7726 #endif 7727 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7728 PHYMOD_SYMBOL_FLAG_REGISTER, 7729 "PMD_X1_OVRRr", 7730 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7731 "PMD_X1_OVERRIDE", 7732 NULL, 7733 #endif 7734 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7735 0x0, /* 0 */ 7736 0, 7737 #endif 7738 }, 7739 { 7740 BCMI_QTC_XGXS_USXGMII_AM_INSERTION_INTERVALr, 7741 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7742 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 7743 BCMI_QTC_XGXS_USXGMII_AM_INSERTION_INTERVALr_fields, 7744 #else 7745 0, 7746 #endif 7747 #endif 7748 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7749 PHYMOD_SYMBOL_FLAG_REGISTER, 7750 "USXGMII_AM_INSERTION_INTERVALr", 7751 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7752 "USXGMII_X1_CONTROL_USXGMII_AM_INSERTION_INTERVAL", 7753 NULL, 7754 #endif 7755 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7756 0x4010, /* 16400 */ 7757 0, 7758 #endif 7759 }, 7760 { 7761 BCMI_QTC_XGXS_USXGMII_LN_0_AM_BYTES_1_0r, 7762 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7763 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 7764 BCMI_QTC_XGXS_USXGMII_LN_0_AM_BYTES_1_0r_fields, 7765 #else 7766 0, 7767 #endif 7768 #endif 7769 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7770 PHYMOD_SYMBOL_FLAG_REGISTER, 7771 "USXGMII_LN_0_AM_BYTES_1_0r", 7772 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7773 "USXGMII_X1_CONTROL_USXGMII_LANE_0_AM_BYTES_1_0", 7774 NULL, 7775 #endif 7776 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7777 0x68c1, /* 26817 */ 7778 0, 7779 #endif 7780 }, 7781 { 7782 BCMI_QTC_XGXS_USXGMII_LN_0_AM_BYTE2r, 7783 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7784 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 7785 BCMI_QTC_XGXS_USXGMII_LN_0_AM_BYTE2r_fields, 7786 #else 7787 0, 7788 #endif 7789 #endif 7790 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7791 PHYMOD_SYMBOL_FLAG_REGISTER, 7792 "USXGMII_LN_0_AM_BYTE2r", 7793 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7794 "USXGMII_X1_CONTROL_USXGMII_LANE_0_AM_BYTE_2", 7795 NULL, 7796 #endif 7797 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7798 0x21, /* 33 */ 7799 0, 7800 #endif 7801 }, 7802 { 7803 BCMI_QTC_XGXS_USXGMII_LN_1_AM_BYTES_1_0r, 7804 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7805 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 7806 BCMI_QTC_XGXS_USXGMII_LN_1_AM_BYTES_1_0r_fields, 7807 #else 7808 0, 7809 #endif 7810 #endif 7811 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7812 PHYMOD_SYMBOL_FLAG_REGISTER, 7813 "USXGMII_LN_1_AM_BYTES_1_0r", 7814 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7815 "USXGMII_X1_CONTROL_USXGMII_LANE_1_AM_BYTES_1_0", 7816 NULL, 7817 #endif 7818 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7819 0xc4f0, /* 50416 */ 7820 0, 7821 #endif 7822 }, 7823 { 7824 BCMI_QTC_XGXS_USXGMII_LN_1_AM_BYTE2r, 7825 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7826 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 7827 BCMI_QTC_XGXS_USXGMII_LN_1_AM_BYTE2r_fields, 7828 #else 7829 0, 7830 #endif 7831 #endif 7832 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7833 PHYMOD_SYMBOL_FLAG_REGISTER, 7834 "USXGMII_LN_1_AM_BYTE2r", 7835 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7836 "USXGMII_X1_CONTROL_USXGMII_LANE_1_AM_BYTE_2", 7837 NULL, 7838 #endif 7839 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7840 0xe6, /* 230 */ 7841 0, 7842 #endif 7843 }, 7844 { 7845 BCMI_QTC_XGXS_USXGMII_LN_2_AM_BYTES_1_0r, 7846 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7847 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 7848 BCMI_QTC_XGXS_USXGMII_LN_2_AM_BYTES_1_0r_fields, 7849 #else 7850 0, 7851 #endif 7852 #endif 7853 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7854 PHYMOD_SYMBOL_FLAG_REGISTER, 7855 "USXGMII_LN_2_AM_BYTES_1_0r", 7856 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7857 "USXGMII_X1_CONTROL_USXGMII_LANE_2_AM_BYTES_1_0", 7858 NULL, 7859 #endif 7860 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7861 0x65c5, /* 26053 */ 7862 0, 7863 #endif 7864 }, 7865 { 7866 BCMI_QTC_XGXS_USXGMII_LN_2_AM_BYTE2r, 7867 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7868 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 7869 BCMI_QTC_XGXS_USXGMII_LN_2_AM_BYTE2r_fields, 7870 #else 7871 0, 7872 #endif 7873 #endif 7874 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7875 PHYMOD_SYMBOL_FLAG_REGISTER, 7876 "USXGMII_LN_2_AM_BYTE2r", 7877 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7878 "USXGMII_X1_CONTROL_USXGMII_LANE_2_AM_BYTE_2", 7879 NULL, 7880 #endif 7881 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7882 0x9b, /* 155 */ 7883 0, 7884 #endif 7885 }, 7886 { 7887 BCMI_QTC_XGXS_USXGMII_LN_3_AM_BYTES_1_0r, 7888 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7889 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 7890 BCMI_QTC_XGXS_USXGMII_LN_3_AM_BYTES_1_0r_fields, 7891 #else 7892 0, 7893 #endif 7894 #endif 7895 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7896 PHYMOD_SYMBOL_FLAG_REGISTER, 7897 "USXGMII_LN_3_AM_BYTES_1_0r", 7898 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7899 "USXGMII_X1_CONTROL_USXGMII_LANE_3_AM_BYTES_1_0", 7900 NULL, 7901 #endif 7902 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7903 0x79a2, /* 31138 */ 7904 0, 7905 #endif 7906 }, 7907 { 7908 BCMI_QTC_XGXS_USXGMII_LN_3_AM_BYTE2r, 7909 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7910 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 7911 BCMI_QTC_XGXS_USXGMII_LN_3_AM_BYTE2r_fields, 7912 #else 7913 0, 7914 #endif 7915 #endif 7916 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7917 PHYMOD_SYMBOL_FLAG_REGISTER, 7918 "USXGMII_LN_3_AM_BYTE2r", 7919 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7920 "USXGMII_X1_CONTROL_USXGMII_LANE_3_AM_BYTE_2", 7921 NULL, 7922 #endif 7923 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7924 0x3d, /* 61 */ 7925 0, 7926 #endif 7927 }, 7928 { 7929 BCMI_QTC_XGXS_PKTGENCTL1r, 7930 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7931 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 7932 BCMI_QTC_XGXS_PKTGENCTL1r_fields, 7933 #else 7934 0, 7935 #endif 7936 #endif 7937 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7938 PHYMOD_SYMBOL_FLAG_REGISTER, 7939 "PKTGENCTL1r", 7940 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7941 "PACKET_GEN_PKTGENCTRL1", 7942 NULL, 7943 #endif 7944 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7945 0x0, /* 0 */ 7946 0, 7947 #endif 7948 }, 7949 { 7950 BCMI_QTC_XGXS_PKTGENCTL2r, 7951 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7952 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 7953 BCMI_QTC_XGXS_PKTGENCTL2r_fields, 7954 #else 7955 0, 7956 #endif 7957 #endif 7958 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7959 PHYMOD_SYMBOL_FLAG_REGISTER, 7960 "PKTGENCTL2r", 7961 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7962 "PACKET_GEN_PKTGENCTRL2", 7963 NULL, 7964 #endif 7965 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7966 0x2c, /* 44 */ 7967 0, 7968 #endif 7969 }, 7970 { 7971 BCMI_QTC_XGXS_PAYLOADBYTESr, 7972 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7973 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 7974 BCMI_QTC_XGXS_PAYLOADBYTESr_fields, 7975 #else 7976 0, 7977 #endif 7978 #endif 7979 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7980 PHYMOD_SYMBOL_FLAG_REGISTER, 7981 "PAYLOADBYTESr", 7982 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7983 "PACKET_GEN_PAYLOADBYTES", 7984 NULL, 7985 #endif 7986 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7987 0x0, /* 0 */ 7988 0, 7989 #endif 7990 }, 7991 { 7992 BCMI_QTC_XGXS_ERR_GENr, 7993 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7994 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 7995 BCMI_QTC_XGXS_ERR_GENr_fields, 7996 #else 7997 0, 7998 #endif 7999 #endif 8000 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8001 PHYMOD_SYMBOL_FLAG_REGISTER, 8002 "ERR_GENr", 8003 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8004 "PACKET_GEN_ERROR_GEN", 8005 NULL, 8006 #endif 8007 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8008 0x0, /* 0 */ 8009 0, 8010 #endif 8011 }, 8012 { 8013 BCMI_QTC_XGXS_ERRMASKr, 8014 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8015 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 8016 BCMI_QTC_XGXS_ERRMASKr_fields, 8017 #else 8018 0, 8019 #endif 8020 #endif 8021 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8022 PHYMOD_SYMBOL_FLAG_REGISTER, 8023 "ERRMASKr", 8024 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8025 "PACKET_GEN_ERRORMASK", 8026 NULL, 8027 #endif 8028 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8029 0x0, /* 0 */ 8030 0, 8031 #endif 8032 }, 8033 { 8034 BCMI_QTC_XGXS_CRCERRCNTr, 8035 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8036 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 8037 BCMI_QTC_XGXS_CRCERRCNTr_fields, 8038 #else 8039 0, 8040 #endif 8041 #endif 8042 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8043 PHYMOD_SYMBOL_FLAG_REGISTER, 8044 "CRCERRCNTr", 8045 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8046 "PACKET_GEN_CRCERRORCOUNT", 8047 NULL, 8048 #endif 8049 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8050 0x0, /* 0 */ 8051 0, 8052 #endif 8053 }, 8054 { 8055 BCMI_QTC_XGXS_OUI_UPRr, 8056 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8057 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 8058 BCMI_QTC_XGXS_OUI_UPRr_fields, 8059 #else 8060 0, 8061 #endif 8062 #endif 8063 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8064 PHYMOD_SYMBOL_FLAG_REGISTER, 8065 "OUI_UPRr", 8066 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8067 "AN_X1_CONTROL_OUI_UPPER", 8068 NULL, 8069 #endif 8070 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8071 0x0, /* 0 */ 8072 0, 8073 #endif 8074 }, 8075 { 8076 BCMI_QTC_XGXS_OUI_LWRr, 8077 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8078 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 8079 BCMI_QTC_XGXS_OUI_LWRr_fields, 8080 #else 8081 0, 8082 #endif 8083 #endif 8084 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8085 PHYMOD_SYMBOL_FLAG_REGISTER, 8086 "OUI_LWRr", 8087 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8088 "AN_X1_CONTROL_OUI_LOWER", 8089 NULL, 8090 #endif 8091 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8092 0x0, /* 0 */ 8093 0, 8094 #endif 8095 }, 8096 { 8097 BCMI_QTC_XGXS_BAM_SPD_PRI_5_0r, 8098 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8099 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 8100 BCMI_QTC_XGXS_BAM_SPD_PRI_5_0r_fields, 8101 #else 8102 0, 8103 #endif 8104 #endif 8105 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8106 PHYMOD_SYMBOL_FLAG_REGISTER, 8107 "BAM_SPD_PRI_5_0r", 8108 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8109 "AN_X1_CONTROL_BAM_SPEED_PRI_5_0", 8110 NULL, 8111 #endif 8112 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8113 0x0, /* 0 */ 8114 0, 8115 #endif 8116 }, 8117 { 8118 BCMI_QTC_XGXS_CL37_RESTARTr, 8119 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8120 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 8121 BCMI_QTC_XGXS_CL37_RESTARTr_fields, 8122 #else 8123 0, 8124 #endif 8125 #endif 8126 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8127 PHYMOD_SYMBOL_FLAG_REGISTER, 8128 "CL37_RESTARTr", 8129 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8130 "AN_X1_TIMERS_CL37_RESTART", 8131 NULL, 8132 #endif 8133 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8134 0x0, /* 0 */ 8135 0, 8136 #endif 8137 }, 8138 { 8139 BCMI_QTC_XGXS_CL37_ACKr, 8140 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8141 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 8142 BCMI_QTC_XGXS_CL37_ACKr_fields, 8143 #else 8144 0, 8145 #endif 8146 #endif 8147 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8148 PHYMOD_SYMBOL_FLAG_REGISTER, 8149 "CL37_ACKr", 8150 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8151 "AN_X1_TIMERS_CL37_ACK", 8152 NULL, 8153 #endif 8154 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8155 0x0, /* 0 */ 8156 0, 8157 #endif 8158 }, 8159 { 8160 BCMI_QTC_XGXS_CL37_ERRr, 8161 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8162 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 8163 BCMI_QTC_XGXS_CL37_ERRr_fields, 8164 #else 8165 0, 8166 #endif 8167 #endif 8168 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8169 PHYMOD_SYMBOL_FLAG_REGISTER, 8170 "CL37_ERRr", 8171 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8172 "AN_X1_TIMERS_CL37_ERROR", 8173 NULL, 8174 #endif 8175 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8176 0x0, /* 0 */ 8177 0, 8178 #endif 8179 }, 8180 { 8181 BCMI_QTC_XGXS_CL37_SYNC_STS_FILTER_TMRr, 8182 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8183 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 8184 BCMI_QTC_XGXS_CL37_SYNC_STS_FILTER_TMRr_fields, 8185 #else 8186 0, 8187 #endif 8188 #endif 8189 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8190 PHYMOD_SYMBOL_FLAG_REGISTER, 8191 "CL37_SYNC_STS_FILTER_TMRr", 8192 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8193 "AN_X1_TIMERS_CL37_SYNC_STATUS_FILTER_TIMER", 8194 NULL, 8195 #endif 8196 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8197 0x2, /* 2 */ 8198 0, 8199 #endif 8200 }, 8201 { 8202 BCMI_QTC_XGXS_SGMII_CL37_TMR_TYPEr, 8203 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8204 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 8205 BCMI_QTC_XGXS_SGMII_CL37_TMR_TYPEr_fields, 8206 #else 8207 0, 8208 #endif 8209 #endif 8210 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8211 PHYMOD_SYMBOL_FLAG_REGISTER, 8212 "SGMII_CL37_TMR_TYPEr", 8213 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8214 "AN_X1_TIMERS_SGMII_CL37_TIMER_TYPE", 8215 NULL, 8216 #endif 8217 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8218 0x6b, /* 107 */ 8219 0, 8220 #endif 8221 }, 8222 { 8223 BCMI_QTC_XGXS_LNK_UP_TYPEr, 8224 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8225 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 8226 BCMI_QTC_XGXS_LNK_UP_TYPEr_fields, 8227 #else 8228 0, 8229 #endif 8230 #endif 8231 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8232 PHYMOD_SYMBOL_FLAG_REGISTER, 8233 "LNK_UP_TYPEr", 8234 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8235 "AN_X1_TIMERS_LINK_UP_TYPE", 8236 NULL, 8237 #endif 8238 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8239 0x6b, /* 107 */ 8240 0, 8241 #endif 8242 }, 8243 { 8244 BCMI_QTC_XGXS_IGNORE_LNK_TMR_TYPEr, 8245 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8246 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 8247 BCMI_QTC_XGXS_IGNORE_LNK_TMR_TYPEr_fields, 8248 #else 8249 0, 8250 #endif 8251 #endif 8252 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8253 PHYMOD_SYMBOL_FLAG_REGISTER, 8254 "IGNORE_LNK_TMR_TYPEr", 8255 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8256 "AN_X1_TIMERS_IGNORE_LINK_TIMER_TYPE", 8257 NULL, 8258 #endif 8259 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8260 0x1, /* 1 */ 8261 0, 8262 #endif 8263 }, 8264 { 8265 BCMI_QTC_XGXS_LNK_FAIL_INHBT_TMR_NOT_CL72_TYPEr, 8266 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8267 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 8268 BCMI_QTC_XGXS_LNK_FAIL_INHBT_TMR_NOT_CL72_TYPEr_fields, 8269 #else 8270 0, 8271 #endif 8272 #endif 8273 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8274 PHYMOD_SYMBOL_FLAG_REGISTER, 8275 "LNK_FAIL_INHBT_TMR_NOT_CL72_TYPEr", 8276 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8277 "AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_NOT_CL72_TYPE", 8278 NULL, 8279 #endif 8280 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8281 0xffff, /* 65535 */ 8282 0, 8283 #endif 8284 }, 8285 { 8286 BCMI_QTC_XGXS_SC_X1_PLL_LOCK_TMRr, 8287 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8288 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 8289 BCMI_QTC_XGXS_SC_X1_PLL_LOCK_TMRr_fields, 8290 #else 8291 0, 8292 #endif 8293 #endif 8294 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8295 PHYMOD_SYMBOL_FLAG_REGISTER, 8296 "SC_X1_PLL_LOCK_TMRr", 8297 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8298 "SC_X1_CONTROL_PLL_LOCK_TIMER", 8299 NULL, 8300 #endif 8301 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8302 0x0, /* 0 */ 8303 0, 8304 #endif 8305 }, 8306 { 8307 BCMI_QTC_XGXS_SC_X1_PMD_LOCK_TMRr, 8308 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8309 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 8310 BCMI_QTC_XGXS_SC_X1_PMD_LOCK_TMRr_fields, 8311 #else 8312 0, 8313 #endif 8314 #endif 8315 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8316 PHYMOD_SYMBOL_FLAG_REGISTER, 8317 "SC_X1_PMD_LOCK_TMRr", 8318 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8319 "SC_X1_CONTROL_PMD_LOCK_TIMER", 8320 NULL, 8321 #endif 8322 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8323 0x0, /* 0 */ 8324 0, 8325 #endif 8326 }, 8327 { 8328 BCMI_QTC_XGXS_SC_X1_PIPE_RST_CNTr, 8329 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8330 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 8331 BCMI_QTC_XGXS_SC_X1_PIPE_RST_CNTr_fields, 8332 #else 8333 0, 8334 #endif 8335 #endif 8336 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8337 PHYMOD_SYMBOL_FLAG_REGISTER, 8338 "SC_X1_PIPE_RST_CNTr", 8339 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8340 "SC_X1_CONTROL_PIPELINE_RESET_COUNT", 8341 NULL, 8342 #endif 8343 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8344 0xff, /* 255 */ 8345 0, 8346 #endif 8347 }, 8348 { 8349 BCMI_QTC_XGXS_SC_X1_TX_RST_CNTr, 8350 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8351 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 8352 BCMI_QTC_XGXS_SC_X1_TX_RST_CNTr_fields, 8353 #else 8354 0, 8355 #endif 8356 #endif 8357 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8358 PHYMOD_SYMBOL_FLAG_REGISTER, 8359 "SC_X1_TX_RST_CNTr", 8360 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8361 "SC_X1_CONTROL_TX_RESET_COUNT", 8362 NULL, 8363 #endif 8364 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8365 0x2, /* 2 */ 8366 0, 8367 #endif 8368 }, 8369 { 8370 BCMI_QTC_XGXS_SC_X1_SPD_OVRR0_SPDr, 8371 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8372 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 8373 BCMI_QTC_XGXS_SC_X1_SPD_OVRR0_SPDr_fields, 8374 #else 8375 0, 8376 #endif 8377 #endif 8378 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8379 PHYMOD_SYMBOL_FLAG_REGISTER, 8380 "SC_X1_SPD_OVRR0_SPDr", 8381 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8382 "SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED", 8383 NULL, 8384 #endif 8385 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8386 0xff, /* 255 */ 8387 0, 8388 #endif 8389 }, 8390 { 8391 BCMI_QTC_XGXS_SC_X1_SPD_OVRR0_0r, 8392 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8393 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 8394 BCMI_QTC_XGXS_SC_X1_SPD_OVRR0_0r_fields, 8395 #else 8396 0, 8397 #endif 8398 #endif 8399 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8400 PHYMOD_SYMBOL_FLAG_REGISTER, 8401 "SC_X1_SPD_OVRR0_0r", 8402 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8403 "SC_X1_SPEED_OVERRIDE0_OVERRIDE_0", 8404 NULL, 8405 #endif 8406 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8407 0x0, /* 0 */ 8408 0, 8409 #endif 8410 }, 8411 { 8412 BCMI_QTC_XGXS_SC_X1_SPD_OVRR0_1r, 8413 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8414 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 8415 BCMI_QTC_XGXS_SC_X1_SPD_OVRR0_1r_fields, 8416 #else 8417 0, 8418 #endif 8419 #endif 8420 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8421 PHYMOD_SYMBOL_FLAG_REGISTER, 8422 "SC_X1_SPD_OVRR0_1r", 8423 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8424 "SC_X1_SPEED_OVERRIDE0_OVERRIDE_1", 8425 NULL, 8426 #endif 8427 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8428 0x0, /* 0 */ 8429 0, 8430 #endif 8431 }, 8432 { 8433 BCMI_QTC_XGXS_SC_X1_SPD_OVRR0_2r, 8434 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8435 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 8436 BCMI_QTC_XGXS_SC_X1_SPD_OVRR0_2r_fields, 8437 #else 8438 0, 8439 #endif 8440 #endif 8441 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8442 PHYMOD_SYMBOL_FLAG_REGISTER, 8443 "SC_X1_SPD_OVRR0_2r", 8444 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8445 "SC_X1_SPEED_OVERRIDE0_OVERRIDE_2", 8446 NULL, 8447 #endif 8448 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8449 0x0, /* 0 */ 8450 0, 8451 #endif 8452 }, 8453 { 8454 BCMI_QTC_XGXS_SC_X1_SPD_OVRR0_3r, 8455 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8456 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 8457 BCMI_QTC_XGXS_SC_X1_SPD_OVRR0_3r_fields, 8458 #else 8459 0, 8460 #endif 8461 #endif 8462 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8463 PHYMOD_SYMBOL_FLAG_REGISTER, 8464 "SC_X1_SPD_OVRR0_3r", 8465 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8466 "SC_X1_SPEED_OVERRIDE0_OVERRIDE_3", 8467 NULL, 8468 #endif 8469 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8470 0x0, /* 0 */ 8471 0, 8472 #endif 8473 }, 8474 { 8475 BCMI_QTC_XGXS_SC_X1_SPD_OVRR0_4r, 8476 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8477 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 8478 BCMI_QTC_XGXS_SC_X1_SPD_OVRR0_4r_fields, 8479 #else 8480 0, 8481 #endif 8482 #endif 8483 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8484 PHYMOD_SYMBOL_FLAG_REGISTER, 8485 "SC_X1_SPD_OVRR0_4r", 8486 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8487 "SC_X1_SPEED_OVERRIDE0_OVERRIDE_4", 8488 NULL, 8489 #endif 8490 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8491 0x0, /* 0 */ 8492 0, 8493 #endif 8494 }, 8495 { 8496 BCMI_QTC_XGXS_SC_X1_SPD_OVRR0_5r, 8497 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8498 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 8499 BCMI_QTC_XGXS_SC_X1_SPD_OVRR0_5r_fields, 8500 #else 8501 0, 8502 #endif 8503 #endif 8504 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8505 PHYMOD_SYMBOL_FLAG_REGISTER, 8506 "SC_X1_SPD_OVRR0_5r", 8507 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8508 "SC_X1_SPEED_OVERRIDE0_OVERRIDE_5", 8509 NULL, 8510 #endif 8511 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8512 0x0, /* 0 */ 8513 0, 8514 #endif 8515 }, 8516 { 8517 BCMI_QTC_XGXS_SC_X1_SPD_OVRR0_6r, 8518 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8519 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 8520 BCMI_QTC_XGXS_SC_X1_SPD_OVRR0_6r_fields, 8521 #else 8522 0, 8523 #endif 8524 #endif 8525 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8526 PHYMOD_SYMBOL_FLAG_REGISTER, 8527 "SC_X1_SPD_OVRR0_6r", 8528 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8529 "SC_X1_SPEED_OVERRIDE0_OVERRIDE_6", 8530 NULL, 8531 #endif 8532 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8533 0x0, /* 0 */ 8534 0, 8535 #endif 8536 }, 8537 { 8538 BCMI_QTC_XGXS_SC_X1_SPD_OVRR1_SPDr, 8539 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8540 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 8541 BCMI_QTC_XGXS_SC_X1_SPD_OVRR1_SPDr_fields, 8542 #else 8543 0, 8544 #endif 8545 #endif 8546 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8547 PHYMOD_SYMBOL_FLAG_REGISTER, 8548 "SC_X1_SPD_OVRR1_SPDr", 8549 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8550 "SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED", 8551 NULL, 8552 #endif 8553 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8554 0xff, /* 255 */ 8555 0, 8556 #endif 8557 }, 8558 { 8559 BCMI_QTC_XGXS_SC_X1_SPD_OVRR1_0r, 8560 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8561 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 8562 BCMI_QTC_XGXS_SC_X1_SPD_OVRR1_0r_fields, 8563 #else 8564 0, 8565 #endif 8566 #endif 8567 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8568 PHYMOD_SYMBOL_FLAG_REGISTER, 8569 "SC_X1_SPD_OVRR1_0r", 8570 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8571 "SC_X1_SPEED_OVERRIDE1_OVERRIDE_0", 8572 NULL, 8573 #endif 8574 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8575 0x0, /* 0 */ 8576 0, 8577 #endif 8578 }, 8579 { 8580 BCMI_QTC_XGXS_SC_X1_SPD_OVRR1_1r, 8581 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8582 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 8583 BCMI_QTC_XGXS_SC_X1_SPD_OVRR1_1r_fields, 8584 #else 8585 0, 8586 #endif 8587 #endif 8588 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8589 PHYMOD_SYMBOL_FLAG_REGISTER, 8590 "SC_X1_SPD_OVRR1_1r", 8591 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8592 "SC_X1_SPEED_OVERRIDE1_OVERRIDE_1", 8593 NULL, 8594 #endif 8595 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8596 0x0, /* 0 */ 8597 0, 8598 #endif 8599 }, 8600 { 8601 BCMI_QTC_XGXS_SC_X1_SPD_OVRR1_2r, 8602 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8603 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 8604 BCMI_QTC_XGXS_SC_X1_SPD_OVRR1_2r_fields, 8605 #else 8606 0, 8607 #endif 8608 #endif 8609 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8610 PHYMOD_SYMBOL_FLAG_REGISTER, 8611 "SC_X1_SPD_OVRR1_2r", 8612 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8613 "SC_X1_SPEED_OVERRIDE1_OVERRIDE_2", 8614 NULL, 8615 #endif 8616 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8617 0x0, /* 0 */ 8618 0, 8619 #endif 8620 }, 8621 { 8622 BCMI_QTC_XGXS_SC_X1_SPD_OVRR1_3r, 8623 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8624 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 8625 BCMI_QTC_XGXS_SC_X1_SPD_OVRR1_3r_fields, 8626 #else 8627 0, 8628 #endif 8629 #endif 8630 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8631 PHYMOD_SYMBOL_FLAG_REGISTER, 8632 "SC_X1_SPD_OVRR1_3r", 8633 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8634 "SC_X1_SPEED_OVERRIDE1_OVERRIDE_3", 8635 NULL, 8636 #endif 8637 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8638 0x0, /* 0 */ 8639 0, 8640 #endif 8641 }, 8642 { 8643 BCMI_QTC_XGXS_SC_X1_SPD_OVRR1_4r, 8644 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8645 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 8646 BCMI_QTC_XGXS_SC_X1_SPD_OVRR1_4r_fields, 8647 #else 8648 0, 8649 #endif 8650 #endif 8651 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8652 PHYMOD_SYMBOL_FLAG_REGISTER, 8653 "SC_X1_SPD_OVRR1_4r", 8654 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8655 "SC_X1_SPEED_OVERRIDE1_OVERRIDE_4", 8656 NULL, 8657 #endif 8658 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8659 0x0, /* 0 */ 8660 0, 8661 #endif 8662 }, 8663 { 8664 BCMI_QTC_XGXS_SC_X1_SPD_OVRR1_5r, 8665 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8666 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 8667 BCMI_QTC_XGXS_SC_X1_SPD_OVRR1_5r_fields, 8668 #else 8669 0, 8670 #endif 8671 #endif 8672 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8673 PHYMOD_SYMBOL_FLAG_REGISTER, 8674 "SC_X1_SPD_OVRR1_5r", 8675 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8676 "SC_X1_SPEED_OVERRIDE1_OVERRIDE_5", 8677 NULL, 8678 #endif 8679 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8680 0x0, /* 0 */ 8681 0, 8682 #endif 8683 }, 8684 { 8685 BCMI_QTC_XGXS_SC_X1_SPD_OVRR1_6r, 8686 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8687 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 8688 BCMI_QTC_XGXS_SC_X1_SPD_OVRR1_6r_fields, 8689 #else 8690 0, 8691 #endif 8692 #endif 8693 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8694 PHYMOD_SYMBOL_FLAG_REGISTER, 8695 "SC_X1_SPD_OVRR1_6r", 8696 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8697 "SC_X1_SPEED_OVERRIDE1_OVERRIDE_6", 8698 NULL, 8699 #endif 8700 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8701 0x0, /* 0 */ 8702 0, 8703 #endif 8704 }, 8705 { 8706 BCMI_QTC_XGXS_SC_X1_SPD_OVRR2_SPDr, 8707 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8708 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 8709 BCMI_QTC_XGXS_SC_X1_SPD_OVRR2_SPDr_fields, 8710 #else 8711 0, 8712 #endif 8713 #endif 8714 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8715 PHYMOD_SYMBOL_FLAG_REGISTER, 8716 "SC_X1_SPD_OVRR2_SPDr", 8717 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8718 "SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED", 8719 NULL, 8720 #endif 8721 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8722 0xff, /* 255 */ 8723 0, 8724 #endif 8725 }, 8726 { 8727 BCMI_QTC_XGXS_SC_X1_SPD_OVRR2_0r, 8728 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8729 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 8730 BCMI_QTC_XGXS_SC_X1_SPD_OVRR2_0r_fields, 8731 #else 8732 0, 8733 #endif 8734 #endif 8735 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8736 PHYMOD_SYMBOL_FLAG_REGISTER, 8737 "SC_X1_SPD_OVRR2_0r", 8738 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8739 "SC_X1_SPEED_OVERRIDE2_OVERRIDE_0", 8740 NULL, 8741 #endif 8742 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8743 0x0, /* 0 */ 8744 0, 8745 #endif 8746 }, 8747 { 8748 BCMI_QTC_XGXS_SC_X1_SPD_OVRR2_1r, 8749 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8750 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 8751 BCMI_QTC_XGXS_SC_X1_SPD_OVRR2_1r_fields, 8752 #else 8753 0, 8754 #endif 8755 #endif 8756 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8757 PHYMOD_SYMBOL_FLAG_REGISTER, 8758 "SC_X1_SPD_OVRR2_1r", 8759 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8760 "SC_X1_SPEED_OVERRIDE2_OVERRIDE_1", 8761 NULL, 8762 #endif 8763 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8764 0x0, /* 0 */ 8765 0, 8766 #endif 8767 }, 8768 { 8769 BCMI_QTC_XGXS_SC_X1_SPD_OVRR2_2r, 8770 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8771 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 8772 BCMI_QTC_XGXS_SC_X1_SPD_OVRR2_2r_fields, 8773 #else 8774 0, 8775 #endif 8776 #endif 8777 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8778 PHYMOD_SYMBOL_FLAG_REGISTER, 8779 "SC_X1_SPD_OVRR2_2r", 8780 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8781 "SC_X1_SPEED_OVERRIDE2_OVERRIDE_2", 8782 NULL, 8783 #endif 8784 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8785 0x0, /* 0 */ 8786 0, 8787 #endif 8788 }, 8789 { 8790 BCMI_QTC_XGXS_SC_X1_SPD_OVRR2_3r, 8791 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8792 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 8793 BCMI_QTC_XGXS_SC_X1_SPD_OVRR2_3r_fields, 8794 #else 8795 0, 8796 #endif 8797 #endif 8798 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8799 PHYMOD_SYMBOL_FLAG_REGISTER, 8800 "SC_X1_SPD_OVRR2_3r", 8801 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8802 "SC_X1_SPEED_OVERRIDE2_OVERRIDE_3", 8803 NULL, 8804 #endif 8805 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8806 0x0, /* 0 */ 8807 0, 8808 #endif 8809 }, 8810 { 8811 BCMI_QTC_XGXS_SC_X1_SPD_OVRR2_4r, 8812 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8813 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 8814 BCMI_QTC_XGXS_SC_X1_SPD_OVRR2_4r_fields, 8815 #else 8816 0, 8817 #endif 8818 #endif 8819 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8820 PHYMOD_SYMBOL_FLAG_REGISTER, 8821 "SC_X1_SPD_OVRR2_4r", 8822 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8823 "SC_X1_SPEED_OVERRIDE2_OVERRIDE_4", 8824 NULL, 8825 #endif 8826 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8827 0x0, /* 0 */ 8828 0, 8829 #endif 8830 }, 8831 { 8832 BCMI_QTC_XGXS_SC_X1_SPD_OVRR2_5r, 8833 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8834 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 8835 BCMI_QTC_XGXS_SC_X1_SPD_OVRR2_5r_fields, 8836 #else 8837 0, 8838 #endif 8839 #endif 8840 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8841 PHYMOD_SYMBOL_FLAG_REGISTER, 8842 "SC_X1_SPD_OVRR2_5r", 8843 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8844 "SC_X1_SPEED_OVERRIDE2_OVERRIDE_5", 8845 NULL, 8846 #endif 8847 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8848 0x0, /* 0 */ 8849 0, 8850 #endif 8851 }, 8852 { 8853 BCMI_QTC_XGXS_SC_X1_SPD_OVRR2_6r, 8854 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8855 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 8856 BCMI_QTC_XGXS_SC_X1_SPD_OVRR2_6r_fields, 8857 #else 8858 0, 8859 #endif 8860 #endif 8861 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8862 PHYMOD_SYMBOL_FLAG_REGISTER, 8863 "SC_X1_SPD_OVRR2_6r", 8864 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8865 "SC_X1_SPEED_OVERRIDE2_OVERRIDE_6", 8866 NULL, 8867 #endif 8868 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8869 0x0, /* 0 */ 8870 0, 8871 #endif 8872 }, 8873 { 8874 BCMI_QTC_XGXS_SC_X1_SPD_OVRR3_SPDr, 8875 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8876 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 8877 BCMI_QTC_XGXS_SC_X1_SPD_OVRR3_SPDr_fields, 8878 #else 8879 0, 8880 #endif 8881 #endif 8882 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8883 PHYMOD_SYMBOL_FLAG_REGISTER, 8884 "SC_X1_SPD_OVRR3_SPDr", 8885 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8886 "SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED", 8887 NULL, 8888 #endif 8889 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8890 0xff, /* 255 */ 8891 0, 8892 #endif 8893 }, 8894 { 8895 BCMI_QTC_XGXS_SC_X1_SPD_OVRR3_0r, 8896 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8897 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 8898 BCMI_QTC_XGXS_SC_X1_SPD_OVRR3_0r_fields, 8899 #else 8900 0, 8901 #endif 8902 #endif 8903 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8904 PHYMOD_SYMBOL_FLAG_REGISTER, 8905 "SC_X1_SPD_OVRR3_0r", 8906 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8907 "SC_X1_SPEED_OVERRIDE3_OVERRIDE_0", 8908 NULL, 8909 #endif 8910 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8911 0x0, /* 0 */ 8912 0, 8913 #endif 8914 }, 8915 { 8916 BCMI_QTC_XGXS_SC_X1_SPD_OVRR3_1r, 8917 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8918 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 8919 BCMI_QTC_XGXS_SC_X1_SPD_OVRR3_1r_fields, 8920 #else 8921 0, 8922 #endif 8923 #endif 8924 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8925 PHYMOD_SYMBOL_FLAG_REGISTER, 8926 "SC_X1_SPD_OVRR3_1r", 8927 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8928 "SC_X1_SPEED_OVERRIDE3_OVERRIDE_1", 8929 NULL, 8930 #endif 8931 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8932 0x0, /* 0 */ 8933 0, 8934 #endif 8935 }, 8936 { 8937 BCMI_QTC_XGXS_SC_X1_SPD_OVRR3_2r, 8938 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8939 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 8940 BCMI_QTC_XGXS_SC_X1_SPD_OVRR3_2r_fields, 8941 #else 8942 0, 8943 #endif 8944 #endif 8945 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8946 PHYMOD_SYMBOL_FLAG_REGISTER, 8947 "SC_X1_SPD_OVRR3_2r", 8948 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8949 "SC_X1_SPEED_OVERRIDE3_OVERRIDE_2", 8950 NULL, 8951 #endif 8952 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8953 0x0, /* 0 */ 8954 0, 8955 #endif 8956 }, 8957 { 8958 BCMI_QTC_XGXS_SC_X1_SPD_OVRR3_3r, 8959 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8960 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 8961 BCMI_QTC_XGXS_SC_X1_SPD_OVRR3_3r_fields, 8962 #else 8963 0, 8964 #endif 8965 #endif 8966 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8967 PHYMOD_SYMBOL_FLAG_REGISTER, 8968 "SC_X1_SPD_OVRR3_3r", 8969 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8970 "SC_X1_SPEED_OVERRIDE3_OVERRIDE_3", 8971 NULL, 8972 #endif 8973 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8974 0x0, /* 0 */ 8975 0, 8976 #endif 8977 }, 8978 { 8979 BCMI_QTC_XGXS_SC_X1_SPD_OVRR3_4r, 8980 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8981 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 8982 BCMI_QTC_XGXS_SC_X1_SPD_OVRR3_4r_fields, 8983 #else 8984 0, 8985 #endif 8986 #endif 8987 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8988 PHYMOD_SYMBOL_FLAG_REGISTER, 8989 "SC_X1_SPD_OVRR3_4r", 8990 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8991 "SC_X1_SPEED_OVERRIDE3_OVERRIDE_4", 8992 NULL, 8993 #endif 8994 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8995 0x0, /* 0 */ 8996 0, 8997 #endif 8998 }, 8999 { 9000 BCMI_QTC_XGXS_SC_X1_SPD_OVRR3_5r, 9001 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9002 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 9003 BCMI_QTC_XGXS_SC_X1_SPD_OVRR3_5r_fields, 9004 #else 9005 0, 9006 #endif 9007 #endif 9008 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9009 PHYMOD_SYMBOL_FLAG_REGISTER, 9010 "SC_X1_SPD_OVRR3_5r", 9011 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9012 "SC_X1_SPEED_OVERRIDE3_OVERRIDE_5", 9013 NULL, 9014 #endif 9015 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9016 0x0, /* 0 */ 9017 0, 9018 #endif 9019 }, 9020 { 9021 BCMI_QTC_XGXS_SC_X1_SPD_OVRR3_6r, 9022 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9023 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 9024 BCMI_QTC_XGXS_SC_X1_SPD_OVRR3_6r_fields, 9025 #else 9026 0, 9027 #endif 9028 #endif 9029 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9030 PHYMOD_SYMBOL_FLAG_REGISTER, 9031 "SC_X1_SPD_OVRR3_6r", 9032 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9033 "SC_X1_SPEED_OVERRIDE3_OVERRIDE_6", 9034 NULL, 9035 #endif 9036 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9037 0x0, /* 0 */ 9038 0, 9039 #endif 9040 }, 9041 { 9042 BCMI_QTC_XGXS_PMD_X4_CTLr, 9043 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9044 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 9045 BCMI_QTC_XGXS_PMD_X4_CTLr_fields, 9046 #else 9047 0, 9048 #endif 9049 #endif 9050 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9051 PHYMOD_SYMBOL_FLAG_REGISTER, 9052 "PMD_X4_CTLr", 9053 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9054 "PMD_X4_CONTROL", 9055 NULL, 9056 #endif 9057 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9058 0x0, /* 0 */ 9059 0, 9060 #endif 9061 }, 9062 { 9063 BCMI_QTC_XGXS_PMD_X4_MODEr, 9064 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9065 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 9066 BCMI_QTC_XGXS_PMD_X4_MODEr_fields, 9067 #else 9068 0, 9069 #endif 9070 #endif 9071 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9072 PHYMOD_SYMBOL_FLAG_REGISTER, 9073 "PMD_X4_MODEr", 9074 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9075 NULL, 9076 NULL, 9077 #endif 9078 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9079 0x0, /* 0 */ 9080 0, 9081 #endif 9082 }, 9083 { 9084 BCMI_QTC_XGXS_PMD_X4_STSr, 9085 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9086 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 9087 BCMI_QTC_XGXS_PMD_X4_STSr_fields, 9088 #else 9089 0, 9090 #endif 9091 #endif 9092 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9093 PHYMOD_SYMBOL_FLAG_REGISTER, 9094 "PMD_X4_STSr", 9095 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9096 "PMD_X4_STATUS", 9097 NULL, 9098 #endif 9099 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9100 0x0, /* 0 */ 9101 0, 9102 #endif 9103 }, 9104 { 9105 BCMI_QTC_XGXS_PMD_X4_LATCH_STSr, 9106 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9107 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 9108 BCMI_QTC_XGXS_PMD_X4_LATCH_STSr_fields, 9109 #else 9110 0, 9111 #endif 9112 #endif 9113 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9114 PHYMOD_SYMBOL_FLAG_REGISTER, 9115 "PMD_X4_LATCH_STSr", 9116 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9117 "PMD_X4_LATCH_STATUS", 9118 NULL, 9119 #endif 9120 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9121 0x0, /* 0 */ 9122 0, 9123 #endif 9124 }, 9125 { 9126 BCMI_QTC_XGXS_PMD_X4_OVRRr, 9127 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9128 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 9129 BCMI_QTC_XGXS_PMD_X4_OVRRr_fields, 9130 #else 9131 0, 9132 #endif 9133 #endif 9134 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9135 PHYMOD_SYMBOL_FLAG_REGISTER, 9136 "PMD_X4_OVRRr", 9137 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9138 "PMD_X4_OVERRIDE", 9139 NULL, 9140 #endif 9141 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9142 0x0, /* 0 */ 9143 0, 9144 #endif 9145 }, 9146 { 9147 BCMI_QTC_XGXS_PMD_X4_EEE_CTLr, 9148 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9149 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 9150 BCMI_QTC_XGXS_PMD_X4_EEE_CTLr_fields, 9151 #else 9152 0, 9153 #endif 9154 #endif 9155 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9156 PHYMOD_SYMBOL_FLAG_REGISTER, 9157 "PMD_X4_EEE_CTLr", 9158 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9159 "PMD_X4_EEE_CONTROL", 9160 NULL, 9161 #endif 9162 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9163 0x0, /* 0 */ 9164 0, 9165 #endif 9166 }, 9167 { 9168 BCMI_QTC_XGXS_PMD_X4_EEE_STSr, 9169 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9170 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 9171 BCMI_QTC_XGXS_PMD_X4_EEE_STSr_fields, 9172 #else 9173 0, 9174 #endif 9175 #endif 9176 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9177 PHYMOD_SYMBOL_FLAG_REGISTER, 9178 "PMD_X4_EEE_STSr", 9179 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9180 "PMD_X4_EEE_STATUS", 9181 NULL, 9182 #endif 9183 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9184 0x0, /* 0 */ 9185 0, 9186 #endif 9187 }, 9188 { 9189 BCMI_QTC_XGXS_SC_X4_CTLr, 9190 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9191 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 9192 BCMI_QTC_XGXS_SC_X4_CTLr_fields, 9193 #else 9194 0, 9195 #endif 9196 #endif 9197 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9198 PHYMOD_SYMBOL_FLAG_REGISTER, 9199 "SC_X4_CTLr", 9200 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9201 "SC_X4_CONTROL_CONTROL", 9202 NULL, 9203 #endif 9204 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9205 0xff, /* 255 */ 9206 0, 9207 #endif 9208 }, 9209 { 9210 BCMI_QTC_XGXS_SC_X4_QSGMII_SPDr, 9211 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9212 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 9213 BCMI_QTC_XGXS_SC_X4_QSGMII_SPDr_fields, 9214 #else 9215 0, 9216 #endif 9217 #endif 9218 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9219 PHYMOD_SYMBOL_FLAG_REGISTER, 9220 "SC_X4_QSGMII_SPDr", 9221 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9222 "SC_X4_CONTROL_QSGMII_SPEED", 9223 NULL, 9224 #endif 9225 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9226 0x0, /* 0 */ 9227 0, 9228 #endif 9229 }, 9230 { 9231 BCMI_QTC_XGXS_SC_X4_STSr, 9232 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9233 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 9234 BCMI_QTC_XGXS_SC_X4_STSr_fields, 9235 #else 9236 0, 9237 #endif 9238 #endif 9239 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9240 PHYMOD_SYMBOL_FLAG_REGISTER, 9241 "SC_X4_STSr", 9242 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9243 "SC_X4_CONTROL_STATUS", 9244 NULL, 9245 #endif 9246 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9247 0x0, /* 0 */ 9248 0, 9249 #endif 9250 }, 9251 { 9252 BCMI_QTC_XGXS_SC_X4_ERRr, 9253 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9254 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 9255 BCMI_QTC_XGXS_SC_X4_ERRr_fields, 9256 #else 9257 0, 9258 #endif 9259 #endif 9260 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9261 PHYMOD_SYMBOL_FLAG_REGISTER, 9262 "SC_X4_ERRr", 9263 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9264 "SC_X4_CONTROL_ERROR", 9265 NULL, 9266 #endif 9267 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9268 0x0, /* 0 */ 9269 0, 9270 #endif 9271 }, 9272 { 9273 BCMI_QTC_XGXS_SC_X4_DBGr, 9274 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9275 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 9276 BCMI_QTC_XGXS_SC_X4_DBGr_fields, 9277 #else 9278 0, 9279 #endif 9280 #endif 9281 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9282 PHYMOD_SYMBOL_FLAG_REGISTER, 9283 "SC_X4_DBGr", 9284 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9285 "SC_X4_CONTROL_DEBUG", 9286 NULL, 9287 #endif 9288 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9289 0x8000, /* 32768 */ 9290 0, 9291 #endif 9292 }, 9293 { 9294 BCMI_QTC_XGXS_SC_X4_BYPASSr, 9295 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9296 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 9297 BCMI_QTC_XGXS_SC_X4_BYPASSr_fields, 9298 #else 9299 0, 9300 #endif 9301 #endif 9302 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9303 PHYMOD_SYMBOL_FLAG_REGISTER, 9304 "SC_X4_BYPASSr", 9305 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9306 "SC_X4_CONTROL_BYPASS", 9307 NULL, 9308 #endif 9309 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9310 0x0, /* 0 */ 9311 0, 9312 #endif 9313 }, 9314 { 9315 BCMI_QTC_XGXS_SC_X4_SC_AN_SUBP_CTLr, 9316 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9317 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 9318 BCMI_QTC_XGXS_SC_X4_SC_AN_SUBP_CTLr_fields, 9319 #else 9320 0, 9321 #endif 9322 #endif 9323 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9324 PHYMOD_SYMBOL_FLAG_REGISTER, 9325 "SC_X4_SC_AN_SUBP_CTLr", 9326 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9327 "SC_X4_CONTROL_SC_AN_SUBP_CONTROL", 9328 NULL, 9329 #endif 9330 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9331 0x0, /* 0 */ 9332 0, 9333 #endif 9334 }, 9335 { 9336 BCMI_QTC_XGXS_SC_X4_FLD_OVRR_EN0_TYPEr, 9337 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9338 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 9339 BCMI_QTC_XGXS_SC_X4_FLD_OVRR_EN0_TYPEr_fields, 9340 #else 9341 0, 9342 #endif 9343 #endif 9344 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9345 PHYMOD_SYMBOL_FLAG_REGISTER, 9346 "SC_X4_FLD_OVRR_EN0_TYPEr", 9347 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9348 "SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE", 9349 NULL, 9350 #endif 9351 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9352 0x0, /* 0 */ 9353 0, 9354 #endif 9355 }, 9356 { 9357 BCMI_QTC_XGXS_SC_X4_FI_SP0_RSLVD_SPDr, 9358 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9359 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 9360 BCMI_QTC_XGXS_SC_X4_FI_SP0_RSLVD_SPDr_fields, 9361 #else 9362 0, 9363 #endif 9364 #endif 9365 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9366 PHYMOD_SYMBOL_FLAG_REGISTER, 9367 "SC_X4_FI_SP0_RSLVD_SPDr", 9368 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9369 "SC_X4_FINAL_CONFIG_STATUS_SP0_RESOLVED_SPEED", 9370 NULL, 9371 #endif 9372 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9373 0x0, /* 0 */ 9374 0, 9375 #endif 9376 }, 9377 { 9378 BCMI_QTC_XGXS_SC_X4_FI_SP0_RSLVD0r, 9379 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9380 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 9381 BCMI_QTC_XGXS_SC_X4_FI_SP0_RSLVD0r_fields, 9382 #else 9383 0, 9384 #endif 9385 #endif 9386 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9387 PHYMOD_SYMBOL_FLAG_REGISTER, 9388 "SC_X4_FI_SP0_RSLVD0r", 9389 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9390 "SC_X4_FINAL_CONFIG_STATUS_SP0_RESOLVED_0", 9391 NULL, 9392 #endif 9393 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9394 0x0, /* 0 */ 9395 0, 9396 #endif 9397 }, 9398 { 9399 BCMI_QTC_XGXS_SC_X4_FI_SP0_RSLVD1r, 9400 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9401 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 9402 BCMI_QTC_XGXS_SC_X4_FI_SP0_RSLVD1r_fields, 9403 #else 9404 0, 9405 #endif 9406 #endif 9407 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9408 PHYMOD_SYMBOL_FLAG_REGISTER, 9409 "SC_X4_FI_SP0_RSLVD1r", 9410 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9411 "SC_X4_FINAL_CONFIG_STATUS_SP0_RESOLVED_1", 9412 NULL, 9413 #endif 9414 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9415 0x0, /* 0 */ 9416 0, 9417 #endif 9418 }, 9419 { 9420 BCMI_QTC_XGXS_SC_X4_FI_SP0_RSLVD2r, 9421 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9422 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 9423 BCMI_QTC_XGXS_SC_X4_FI_SP0_RSLVD2r_fields, 9424 #else 9425 0, 9426 #endif 9427 #endif 9428 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9429 PHYMOD_SYMBOL_FLAG_REGISTER, 9430 "SC_X4_FI_SP0_RSLVD2r", 9431 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9432 "SC_X4_FINAL_CONFIG_STATUS_SP0_RESOLVED_2", 9433 NULL, 9434 #endif 9435 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9436 0x0, /* 0 */ 9437 0, 9438 #endif 9439 }, 9440 { 9441 BCMI_QTC_XGXS_SC_X4_FI_SP0_RSLVD3r, 9442 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9443 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 9444 BCMI_QTC_XGXS_SC_X4_FI_SP0_RSLVD3r_fields, 9445 #else 9446 0, 9447 #endif 9448 #endif 9449 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9450 PHYMOD_SYMBOL_FLAG_REGISTER, 9451 "SC_X4_FI_SP0_RSLVD3r", 9452 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9453 "SC_X4_FINAL_CONFIG_STATUS_SP0_RESOLVED_3", 9454 NULL, 9455 #endif 9456 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9457 0x0, /* 0 */ 9458 0, 9459 #endif 9460 }, 9461 { 9462 BCMI_QTC_XGXS_SC_X4_FI_SP0_RSLVD4r, 9463 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9464 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 9465 BCMI_QTC_XGXS_SC_X4_FI_SP0_RSLVD4r_fields, 9466 #else 9467 0, 9468 #endif 9469 #endif 9470 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9471 PHYMOD_SYMBOL_FLAG_REGISTER, 9472 "SC_X4_FI_SP0_RSLVD4r", 9473 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9474 "SC_X4_FINAL_CONFIG_STATUS_SP0_RESOLVED_4", 9475 NULL, 9476 #endif 9477 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9478 0x0, /* 0 */ 9479 0, 9480 #endif 9481 }, 9482 { 9483 BCMI_QTC_XGXS_SC_X4_FI_SP0_RSLVD5r, 9484 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9485 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 9486 BCMI_QTC_XGXS_SC_X4_FI_SP0_RSLVD5r_fields, 9487 #else 9488 0, 9489 #endif 9490 #endif 9491 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9492 PHYMOD_SYMBOL_FLAG_REGISTER, 9493 "SC_X4_FI_SP0_RSLVD5r", 9494 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9495 "SC_X4_FINAL_CONFIG_STATUS_SP0_RESOLVED_5", 9496 NULL, 9497 #endif 9498 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9499 0x0, /* 0 */ 9500 0, 9501 #endif 9502 }, 9503 { 9504 BCMI_QTC_XGXS_SC_X4_FI_SP0_RSLVD6r, 9505 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9506 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 9507 BCMI_QTC_XGXS_SC_X4_FI_SP0_RSLVD6r_fields, 9508 #else 9509 0, 9510 #endif 9511 #endif 9512 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9513 PHYMOD_SYMBOL_FLAG_REGISTER, 9514 "SC_X4_FI_SP0_RSLVD6r", 9515 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9516 "SC_X4_FINAL_CONFIG_STATUS_SP0_RESOLVED_6", 9517 NULL, 9518 #endif 9519 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9520 0x0, /* 0 */ 9521 0, 9522 #endif 9523 }, 9524 { 9525 BCMI_QTC_XGXS_SC_X4_FI_SP1_RSLVD_SPDr, 9526 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9527 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 9528 BCMI_QTC_XGXS_SC_X4_FI_SP1_RSLVD_SPDr_fields, 9529 #else 9530 0, 9531 #endif 9532 #endif 9533 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9534 PHYMOD_SYMBOL_FLAG_REGISTER, 9535 "SC_X4_FI_SP1_RSLVD_SPDr", 9536 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9537 "SC_X4_FINAL_CONFIG_STATUS_SP1_RESOLVED_SPEED", 9538 NULL, 9539 #endif 9540 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9541 0x0, /* 0 */ 9542 0, 9543 #endif 9544 }, 9545 { 9546 BCMI_QTC_XGXS_SC_X4_FI_SP1_RSLVD0r, 9547 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9548 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 9549 BCMI_QTC_XGXS_SC_X4_FI_SP1_RSLVD0r_fields, 9550 #else 9551 0, 9552 #endif 9553 #endif 9554 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9555 PHYMOD_SYMBOL_FLAG_REGISTER, 9556 "SC_X4_FI_SP1_RSLVD0r", 9557 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9558 "SC_X4_FINAL_CONFIG_STATUS_SP1_RESOLVED_0", 9559 NULL, 9560 #endif 9561 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9562 0x0, /* 0 */ 9563 0, 9564 #endif 9565 }, 9566 { 9567 BCMI_QTC_XGXS_SC_X4_FI_SP1_RSLVD1r, 9568 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9569 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 9570 BCMI_QTC_XGXS_SC_X4_FI_SP1_RSLVD1r_fields, 9571 #else 9572 0, 9573 #endif 9574 #endif 9575 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9576 PHYMOD_SYMBOL_FLAG_REGISTER, 9577 "SC_X4_FI_SP1_RSLVD1r", 9578 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9579 "SC_X4_FINAL_CONFIG_STATUS_SP1_RESOLVED_1", 9580 NULL, 9581 #endif 9582 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9583 0x0, /* 0 */ 9584 0, 9585 #endif 9586 }, 9587 { 9588 BCMI_QTC_XGXS_SC_X4_FI_SP1_RSLVD2r, 9589 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9590 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 9591 BCMI_QTC_XGXS_SC_X4_FI_SP1_RSLVD2r_fields, 9592 #else 9593 0, 9594 #endif 9595 #endif 9596 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9597 PHYMOD_SYMBOL_FLAG_REGISTER, 9598 "SC_X4_FI_SP1_RSLVD2r", 9599 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9600 "SC_X4_FINAL_CONFIG_STATUS_SP1_RESOLVED_2", 9601 NULL, 9602 #endif 9603 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9604 0x0, /* 0 */ 9605 0, 9606 #endif 9607 }, 9608 { 9609 BCMI_QTC_XGXS_SC_X4_FI_SP1_RSLVD3r, 9610 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9611 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 9612 BCMI_QTC_XGXS_SC_X4_FI_SP1_RSLVD3r_fields, 9613 #else 9614 0, 9615 #endif 9616 #endif 9617 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9618 PHYMOD_SYMBOL_FLAG_REGISTER, 9619 "SC_X4_FI_SP1_RSLVD3r", 9620 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9621 "SC_X4_FINAL_CONFIG_STATUS_SP1_RESOLVED_3", 9622 NULL, 9623 #endif 9624 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9625 0x0, /* 0 */ 9626 0, 9627 #endif 9628 }, 9629 { 9630 BCMI_QTC_XGXS_SC_X4_FI_SP1_RSLVD4r, 9631 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9632 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 9633 BCMI_QTC_XGXS_SC_X4_FI_SP1_RSLVD4r_fields, 9634 #else 9635 0, 9636 #endif 9637 #endif 9638 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9639 PHYMOD_SYMBOL_FLAG_REGISTER, 9640 "SC_X4_FI_SP1_RSLVD4r", 9641 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9642 "SC_X4_FINAL_CONFIG_STATUS_SP1_RESOLVED_4", 9643 NULL, 9644 #endif 9645 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9646 0x0, /* 0 */ 9647 0, 9648 #endif 9649 }, 9650 { 9651 BCMI_QTC_XGXS_SC_X4_FI_SP1_RSLVD5r, 9652 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9653 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 9654 BCMI_QTC_XGXS_SC_X4_FI_SP1_RSLVD5r_fields, 9655 #else 9656 0, 9657 #endif 9658 #endif 9659 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9660 PHYMOD_SYMBOL_FLAG_REGISTER, 9661 "SC_X4_FI_SP1_RSLVD5r", 9662 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9663 "SC_X4_FINAL_CONFIG_STATUS_SP1_RESOLVED_5", 9664 NULL, 9665 #endif 9666 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9667 0x0, /* 0 */ 9668 0, 9669 #endif 9670 }, 9671 { 9672 BCMI_QTC_XGXS_SC_X4_FI_SP1_RSLVD6r, 9673 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9674 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 9675 BCMI_QTC_XGXS_SC_X4_FI_SP1_RSLVD6r_fields, 9676 #else 9677 0, 9678 #endif 9679 #endif 9680 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9681 PHYMOD_SYMBOL_FLAG_REGISTER, 9682 "SC_X4_FI_SP1_RSLVD6r", 9683 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9684 "SC_X4_FINAL_CONFIG_STATUS_SP1_RESOLVED_6", 9685 NULL, 9686 #endif 9687 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9688 0x0, /* 0 */ 9689 0, 9690 #endif 9691 }, 9692 { 9693 BCMI_QTC_XGXS_SC_X4_FI_SP2_RSLVD_SPDr, 9694 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9695 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 9696 BCMI_QTC_XGXS_SC_X4_FI_SP2_RSLVD_SPDr_fields, 9697 #else 9698 0, 9699 #endif 9700 #endif 9701 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9702 PHYMOD_SYMBOL_FLAG_REGISTER, 9703 "SC_X4_FI_SP2_RSLVD_SPDr", 9704 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9705 "SC_X4_FINAL_CONFIG_STATUS_SP2_RESOLVED_SPEED", 9706 NULL, 9707 #endif 9708 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9709 0x0, /* 0 */ 9710 0, 9711 #endif 9712 }, 9713 { 9714 BCMI_QTC_XGXS_SC_X4_FI_SP2_RSLVD0r, 9715 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9716 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 9717 BCMI_QTC_XGXS_SC_X4_FI_SP2_RSLVD0r_fields, 9718 #else 9719 0, 9720 #endif 9721 #endif 9722 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9723 PHYMOD_SYMBOL_FLAG_REGISTER, 9724 "SC_X4_FI_SP2_RSLVD0r", 9725 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9726 "SC_X4_FINAL_CONFIG_STATUS_SP2_RESOLVED_0", 9727 NULL, 9728 #endif 9729 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9730 0x0, /* 0 */ 9731 0, 9732 #endif 9733 }, 9734 { 9735 BCMI_QTC_XGXS_SC_X4_FI_SP2_RSLVD1r, 9736 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9737 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 9738 BCMI_QTC_XGXS_SC_X4_FI_SP2_RSLVD1r_fields, 9739 #else 9740 0, 9741 #endif 9742 #endif 9743 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9744 PHYMOD_SYMBOL_FLAG_REGISTER, 9745 "SC_X4_FI_SP2_RSLVD1r", 9746 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9747 "SC_X4_FINAL_CONFIG_STATUS_SP2_RESOLVED_1", 9748 NULL, 9749 #endif 9750 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9751 0x0, /* 0 */ 9752 0, 9753 #endif 9754 }, 9755 { 9756 BCMI_QTC_XGXS_SC_X4_FI_SP2_RSLVD2r, 9757 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9758 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 9759 BCMI_QTC_XGXS_SC_X4_FI_SP2_RSLVD2r_fields, 9760 #else 9761 0, 9762 #endif 9763 #endif 9764 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9765 PHYMOD_SYMBOL_FLAG_REGISTER, 9766 "SC_X4_FI_SP2_RSLVD2r", 9767 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9768 "SC_X4_FINAL_CONFIG_STATUS_SP2_RESOLVED_2", 9769 NULL, 9770 #endif 9771 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9772 0x0, /* 0 */ 9773 0, 9774 #endif 9775 }, 9776 { 9777 BCMI_QTC_XGXS_SC_X4_FI_SP2_RSLVD3r, 9778 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9779 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 9780 BCMI_QTC_XGXS_SC_X4_FI_SP2_RSLVD3r_fields, 9781 #else 9782 0, 9783 #endif 9784 #endif 9785 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9786 PHYMOD_SYMBOL_FLAG_REGISTER, 9787 "SC_X4_FI_SP2_RSLVD3r", 9788 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9789 "SC_X4_FINAL_CONFIG_STATUS_SP2_RESOLVED_3", 9790 NULL, 9791 #endif 9792 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9793 0x0, /* 0 */ 9794 0, 9795 #endif 9796 }, 9797 { 9798 BCMI_QTC_XGXS_SC_X4_FI_SP2_RSLVD4r, 9799 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9800 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 9801 BCMI_QTC_XGXS_SC_X4_FI_SP2_RSLVD4r_fields, 9802 #else 9803 0, 9804 #endif 9805 #endif 9806 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9807 PHYMOD_SYMBOL_FLAG_REGISTER, 9808 "SC_X4_FI_SP2_RSLVD4r", 9809 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9810 "SC_X4_FINAL_CONFIG_STATUS_SP2_RESOLVED_4", 9811 NULL, 9812 #endif 9813 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9814 0x0, /* 0 */ 9815 0, 9816 #endif 9817 }, 9818 { 9819 BCMI_QTC_XGXS_SC_X4_FI_SP2_RSLVD5r, 9820 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9821 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 9822 BCMI_QTC_XGXS_SC_X4_FI_SP2_RSLVD5r_fields, 9823 #else 9824 0, 9825 #endif 9826 #endif 9827 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9828 PHYMOD_SYMBOL_FLAG_REGISTER, 9829 "SC_X4_FI_SP2_RSLVD5r", 9830 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9831 "SC_X4_FINAL_CONFIG_STATUS_SP2_RESOLVED_5", 9832 NULL, 9833 #endif 9834 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9835 0x0, /* 0 */ 9836 0, 9837 #endif 9838 }, 9839 { 9840 BCMI_QTC_XGXS_SC_X4_FI_SP2_RSLVD6r, 9841 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9842 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 9843 BCMI_QTC_XGXS_SC_X4_FI_SP2_RSLVD6r_fields, 9844 #else 9845 0, 9846 #endif 9847 #endif 9848 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9849 PHYMOD_SYMBOL_FLAG_REGISTER, 9850 "SC_X4_FI_SP2_RSLVD6r", 9851 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9852 "SC_X4_FINAL_CONFIG_STATUS_SP2_RESOLVED_6", 9853 NULL, 9854 #endif 9855 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9856 0x0, /* 0 */ 9857 0, 9858 #endif 9859 }, 9860 { 9861 BCMI_QTC_XGXS_SC_X4_FI_SP3_RSLVD_SPDr, 9862 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9863 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 9864 BCMI_QTC_XGXS_SC_X4_FI_SP3_RSLVD_SPDr_fields, 9865 #else 9866 0, 9867 #endif 9868 #endif 9869 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9870 PHYMOD_SYMBOL_FLAG_REGISTER, 9871 "SC_X4_FI_SP3_RSLVD_SPDr", 9872 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9873 "SC_X4_FINAL_CONFIG_STATUS_SP3_RESOLVED_SPEED", 9874 NULL, 9875 #endif 9876 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9877 0x0, /* 0 */ 9878 0, 9879 #endif 9880 }, 9881 { 9882 BCMI_QTC_XGXS_SC_X4_FI_SP3_RSLVD0r, 9883 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9884 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 9885 BCMI_QTC_XGXS_SC_X4_FI_SP3_RSLVD0r_fields, 9886 #else 9887 0, 9888 #endif 9889 #endif 9890 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9891 PHYMOD_SYMBOL_FLAG_REGISTER, 9892 "SC_X4_FI_SP3_RSLVD0r", 9893 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9894 "SC_X4_FINAL_CONFIG_STATUS_SP3_RESOLVED_0", 9895 NULL, 9896 #endif 9897 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9898 0x0, /* 0 */ 9899 0, 9900 #endif 9901 }, 9902 { 9903 BCMI_QTC_XGXS_SC_X4_FI_SP3_RSLVD1r, 9904 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9905 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 9906 BCMI_QTC_XGXS_SC_X4_FI_SP3_RSLVD1r_fields, 9907 #else 9908 0, 9909 #endif 9910 #endif 9911 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9912 PHYMOD_SYMBOL_FLAG_REGISTER, 9913 "SC_X4_FI_SP3_RSLVD1r", 9914 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9915 "SC_X4_FINAL_CONFIG_STATUS_SP3_RESOLVED_1", 9916 NULL, 9917 #endif 9918 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9919 0x0, /* 0 */ 9920 0, 9921 #endif 9922 }, 9923 { 9924 BCMI_QTC_XGXS_SC_X4_FI_SP3_RSLVD2r, 9925 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9926 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 9927 BCMI_QTC_XGXS_SC_X4_FI_SP3_RSLVD2r_fields, 9928 #else 9929 0, 9930 #endif 9931 #endif 9932 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9933 PHYMOD_SYMBOL_FLAG_REGISTER, 9934 "SC_X4_FI_SP3_RSLVD2r", 9935 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9936 "SC_X4_FINAL_CONFIG_STATUS_SP3_RESOLVED_2", 9937 NULL, 9938 #endif 9939 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9940 0x0, /* 0 */ 9941 0, 9942 #endif 9943 }, 9944 { 9945 BCMI_QTC_XGXS_SC_X4_FI_SP3_RSLVD3r, 9946 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9947 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 9948 BCMI_QTC_XGXS_SC_X4_FI_SP3_RSLVD3r_fields, 9949 #else 9950 0, 9951 #endif 9952 #endif 9953 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9954 PHYMOD_SYMBOL_FLAG_REGISTER, 9955 "SC_X4_FI_SP3_RSLVD3r", 9956 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9957 "SC_X4_FINAL_CONFIG_STATUS_SP3_RESOLVED_3", 9958 NULL, 9959 #endif 9960 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9961 0x0, /* 0 */ 9962 0, 9963 #endif 9964 }, 9965 { 9966 BCMI_QTC_XGXS_SC_X4_FI_SP3_RSLVD4r, 9967 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9968 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 9969 BCMI_QTC_XGXS_SC_X4_FI_SP3_RSLVD4r_fields, 9970 #else 9971 0, 9972 #endif 9973 #endif 9974 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9975 PHYMOD_SYMBOL_FLAG_REGISTER, 9976 "SC_X4_FI_SP3_RSLVD4r", 9977 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9978 "SC_X4_FINAL_CONFIG_STATUS_SP3_RESOLVED_4", 9979 NULL, 9980 #endif 9981 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9982 0x0, /* 0 */ 9983 0, 9984 #endif 9985 }, 9986 { 9987 BCMI_QTC_XGXS_SC_X4_FI_SP3_RSLVD5r, 9988 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9989 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 9990 BCMI_QTC_XGXS_SC_X4_FI_SP3_RSLVD5r_fields, 9991 #else 9992 0, 9993 #endif 9994 #endif 9995 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9996 PHYMOD_SYMBOL_FLAG_REGISTER, 9997 "SC_X4_FI_SP3_RSLVD5r", 9998 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9999 "SC_X4_FINAL_CONFIG_STATUS_SP3_RESOLVED_5", 10000 NULL, 10001 #endif 10002 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10003 0x0, /* 0 */ 10004 0, 10005 #endif 10006 }, 10007 { 10008 BCMI_QTC_XGXS_SC_X4_FI_SP3_RSLVD6r, 10009 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10010 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 10011 BCMI_QTC_XGXS_SC_X4_FI_SP3_RSLVD6r_fields, 10012 #else 10013 0, 10014 #endif 10015 #endif 10016 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10017 PHYMOD_SYMBOL_FLAG_REGISTER, 10018 "SC_X4_FI_SP3_RSLVD6r", 10019 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10020 "SC_X4_FINAL_CONFIG_STATUS_SP3_RESOLVED_6", 10021 NULL, 10022 #endif 10023 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10024 0x0, /* 0 */ 10025 0, 10026 #endif 10027 }, 10028 { 10029 BCMI_QTC_XGXS_TX_X4_SP0_CRED0r, 10030 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10031 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 10032 BCMI_QTC_XGXS_TX_X4_SP0_CRED0r_fields, 10033 #else 10034 0, 10035 #endif 10036 #endif 10037 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10038 PHYMOD_SYMBOL_FLAG_REGISTER, 10039 "TX_X4_SP0_CRED0r", 10040 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10041 "TX_X4_CREDIT_SP0_CREDIT0", 10042 NULL, 10043 #endif 10044 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10045 0x0, /* 0 */ 10046 0, 10047 #endif 10048 }, 10049 { 10050 BCMI_QTC_XGXS_TX_X4_SP0_CRED1r, 10051 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10052 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 10053 BCMI_QTC_XGXS_TX_X4_SP0_CRED1r_fields, 10054 #else 10055 0, 10056 #endif 10057 #endif 10058 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10059 PHYMOD_SYMBOL_FLAG_REGISTER, 10060 "TX_X4_SP0_CRED1r", 10061 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10062 "TX_X4_CREDIT_SP0_CREDIT1", 10063 NULL, 10064 #endif 10065 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10066 0x0, /* 0 */ 10067 0, 10068 #endif 10069 }, 10070 { 10071 BCMI_QTC_XGXS_TX_X4_SP0_LOOPCNTr, 10072 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10073 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 10074 BCMI_QTC_XGXS_TX_X4_SP0_LOOPCNTr_fields, 10075 #else 10076 0, 10077 #endif 10078 #endif 10079 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10080 PHYMOD_SYMBOL_FLAG_REGISTER, 10081 "TX_X4_SP0_LOOPCNTr", 10082 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10083 "TX_X4_CREDIT_SP0_LOOPCNT", 10084 NULL, 10085 #endif 10086 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10087 0x0, /* 0 */ 10088 0, 10089 #endif 10090 }, 10091 { 10092 BCMI_QTC_XGXS_TX_X4_SP0_MAC_CREDGENCNTr, 10093 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10094 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 10095 BCMI_QTC_XGXS_TX_X4_SP0_MAC_CREDGENCNTr_fields, 10096 #else 10097 0, 10098 #endif 10099 #endif 10100 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10101 PHYMOD_SYMBOL_FLAG_REGISTER, 10102 "TX_X4_SP0_MAC_CREDGENCNTr", 10103 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10104 "TX_X4_CREDIT_SP0_MAC_CREDITGENCNT", 10105 NULL, 10106 #endif 10107 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10108 0x0, /* 0 */ 10109 0, 10110 #endif 10111 }, 10112 { 10113 BCMI_QTC_XGXS_TX_X4_SP0_PCS_CLKCNT0r, 10114 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10115 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 10116 BCMI_QTC_XGXS_TX_X4_SP0_PCS_CLKCNT0r_fields, 10117 #else 10118 0, 10119 #endif 10120 #endif 10121 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10122 PHYMOD_SYMBOL_FLAG_REGISTER, 10123 "TX_X4_SP0_PCS_CLKCNT0r", 10124 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10125 "TX_X4_CREDIT_SP0_PCS_CLOCKCNT0", 10126 NULL, 10127 #endif 10128 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10129 0x0, /* 0 */ 10130 0, 10131 #endif 10132 }, 10133 { 10134 BCMI_QTC_XGXS_TX_X4_SP0_PCS_CREDGENCNTr, 10135 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10136 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 10137 BCMI_QTC_XGXS_TX_X4_SP0_PCS_CREDGENCNTr_fields, 10138 #else 10139 0, 10140 #endif 10141 #endif 10142 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10143 PHYMOD_SYMBOL_FLAG_REGISTER, 10144 "TX_X4_SP0_PCS_CREDGENCNTr", 10145 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10146 "TX_X4_CREDIT_SP0_PCS_CREDITGENCNT", 10147 NULL, 10148 #endif 10149 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10150 0x0, /* 0 */ 10151 0, 10152 #endif 10153 }, 10154 { 10155 BCMI_QTC_XGXS_TX_X4_SP1_CRED0r, 10156 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10157 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 10158 BCMI_QTC_XGXS_TX_X4_SP1_CRED0r_fields, 10159 #else 10160 0, 10161 #endif 10162 #endif 10163 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10164 PHYMOD_SYMBOL_FLAG_REGISTER, 10165 "TX_X4_SP1_CRED0r", 10166 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10167 "TX_X4_CREDIT_SP1_CREDIT0", 10168 NULL, 10169 #endif 10170 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10171 0x0, /* 0 */ 10172 0, 10173 #endif 10174 }, 10175 { 10176 BCMI_QTC_XGXS_TX_X4_SP1_CRED1r, 10177 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10178 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 10179 BCMI_QTC_XGXS_TX_X4_SP1_CRED1r_fields, 10180 #else 10181 0, 10182 #endif 10183 #endif 10184 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10185 PHYMOD_SYMBOL_FLAG_REGISTER, 10186 "TX_X4_SP1_CRED1r", 10187 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10188 "TX_X4_CREDIT_SP1_CREDIT1", 10189 NULL, 10190 #endif 10191 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10192 0x0, /* 0 */ 10193 0, 10194 #endif 10195 }, 10196 { 10197 BCMI_QTC_XGXS_TX_X4_SP1_LOOPCNTr, 10198 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10199 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 10200 BCMI_QTC_XGXS_TX_X4_SP1_LOOPCNTr_fields, 10201 #else 10202 0, 10203 #endif 10204 #endif 10205 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10206 PHYMOD_SYMBOL_FLAG_REGISTER, 10207 "TX_X4_SP1_LOOPCNTr", 10208 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10209 "TX_X4_CREDIT_SP1_LOOPCNT", 10210 NULL, 10211 #endif 10212 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10213 0x0, /* 0 */ 10214 0, 10215 #endif 10216 }, 10217 { 10218 BCMI_QTC_XGXS_TX_X4_SP1_MAC_CREDGENCNTr, 10219 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10220 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 10221 BCMI_QTC_XGXS_TX_X4_SP1_MAC_CREDGENCNTr_fields, 10222 #else 10223 0, 10224 #endif 10225 #endif 10226 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10227 PHYMOD_SYMBOL_FLAG_REGISTER, 10228 "TX_X4_SP1_MAC_CREDGENCNTr", 10229 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10230 "TX_X4_CREDIT_SP1_MAC_CREDITGENCNT", 10231 NULL, 10232 #endif 10233 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10234 0x0, /* 0 */ 10235 0, 10236 #endif 10237 }, 10238 { 10239 BCMI_QTC_XGXS_TX_X4_SP1_PCS_CLKCNT0r, 10240 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10241 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 10242 BCMI_QTC_XGXS_TX_X4_SP1_PCS_CLKCNT0r_fields, 10243 #else 10244 0, 10245 #endif 10246 #endif 10247 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10248 PHYMOD_SYMBOL_FLAG_REGISTER, 10249 "TX_X4_SP1_PCS_CLKCNT0r", 10250 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10251 "TX_X4_CREDIT_SP1_PCS_CLOCKCNT0", 10252 NULL, 10253 #endif 10254 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10255 0x0, /* 0 */ 10256 0, 10257 #endif 10258 }, 10259 { 10260 BCMI_QTC_XGXS_TX_X4_SP1_PCS_CREDGENCNTr, 10261 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10262 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 10263 BCMI_QTC_XGXS_TX_X4_SP1_PCS_CREDGENCNTr_fields, 10264 #else 10265 0, 10266 #endif 10267 #endif 10268 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10269 PHYMOD_SYMBOL_FLAG_REGISTER, 10270 "TX_X4_SP1_PCS_CREDGENCNTr", 10271 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10272 "TX_X4_CREDIT_SP1_PCS_CREDITGENCNT", 10273 NULL, 10274 #endif 10275 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10276 0x0, /* 0 */ 10277 0, 10278 #endif 10279 }, 10280 { 10281 BCMI_QTC_XGXS_TX_X4_SP2_CRED0r, 10282 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10283 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 10284 BCMI_QTC_XGXS_TX_X4_SP2_CRED0r_fields, 10285 #else 10286 0, 10287 #endif 10288 #endif 10289 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10290 PHYMOD_SYMBOL_FLAG_REGISTER, 10291 "TX_X4_SP2_CRED0r", 10292 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10293 "TX_X4_CREDIT_SP2_CREDIT0", 10294 NULL, 10295 #endif 10296 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10297 0x0, /* 0 */ 10298 0, 10299 #endif 10300 }, 10301 { 10302 BCMI_QTC_XGXS_TX_X4_SP2_CRED1r, 10303 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10304 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 10305 BCMI_QTC_XGXS_TX_X4_SP2_CRED1r_fields, 10306 #else 10307 0, 10308 #endif 10309 #endif 10310 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10311 PHYMOD_SYMBOL_FLAG_REGISTER, 10312 "TX_X4_SP2_CRED1r", 10313 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10314 "TX_X4_CREDIT_SP2_CREDIT1", 10315 NULL, 10316 #endif 10317 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10318 0x0, /* 0 */ 10319 0, 10320 #endif 10321 }, 10322 { 10323 BCMI_QTC_XGXS_TX_X4_SP2_LOOPCNTr, 10324 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10325 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 10326 BCMI_QTC_XGXS_TX_X4_SP2_LOOPCNTr_fields, 10327 #else 10328 0, 10329 #endif 10330 #endif 10331 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10332 PHYMOD_SYMBOL_FLAG_REGISTER, 10333 "TX_X4_SP2_LOOPCNTr", 10334 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10335 "TX_X4_CREDIT_SP2_LOOPCNT", 10336 NULL, 10337 #endif 10338 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10339 0x0, /* 0 */ 10340 0, 10341 #endif 10342 }, 10343 { 10344 BCMI_QTC_XGXS_TX_X4_SP2_MAC_CREDGENCNTr, 10345 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10346 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 10347 BCMI_QTC_XGXS_TX_X4_SP2_MAC_CREDGENCNTr_fields, 10348 #else 10349 0, 10350 #endif 10351 #endif 10352 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10353 PHYMOD_SYMBOL_FLAG_REGISTER, 10354 "TX_X4_SP2_MAC_CREDGENCNTr", 10355 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10356 "TX_X4_CREDIT_SP2_MAC_CREDITGENCNT", 10357 NULL, 10358 #endif 10359 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10360 0x0, /* 0 */ 10361 0, 10362 #endif 10363 }, 10364 { 10365 BCMI_QTC_XGXS_TX_X4_SP2_PCS_CLKCNT0r, 10366 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10367 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 10368 BCMI_QTC_XGXS_TX_X4_SP2_PCS_CLKCNT0r_fields, 10369 #else 10370 0, 10371 #endif 10372 #endif 10373 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10374 PHYMOD_SYMBOL_FLAG_REGISTER, 10375 "TX_X4_SP2_PCS_CLKCNT0r", 10376 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10377 "TX_X4_CREDIT_SP2_PCS_CLOCKCNT0", 10378 NULL, 10379 #endif 10380 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10381 0x0, /* 0 */ 10382 0, 10383 #endif 10384 }, 10385 { 10386 BCMI_QTC_XGXS_TX_X4_SP2_PCS_CREDGENCNTr, 10387 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10388 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 10389 BCMI_QTC_XGXS_TX_X4_SP2_PCS_CREDGENCNTr_fields, 10390 #else 10391 0, 10392 #endif 10393 #endif 10394 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10395 PHYMOD_SYMBOL_FLAG_REGISTER, 10396 "TX_X4_SP2_PCS_CREDGENCNTr", 10397 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10398 "TX_X4_CREDIT_SP2_PCS_CREDITGENCNT", 10399 NULL, 10400 #endif 10401 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10402 0x0, /* 0 */ 10403 0, 10404 #endif 10405 }, 10406 { 10407 BCMI_QTC_XGXS_TX_X4_SP3_CRED0r, 10408 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10409 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 10410 BCMI_QTC_XGXS_TX_X4_SP3_CRED0r_fields, 10411 #else 10412 0, 10413 #endif 10414 #endif 10415 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10416 PHYMOD_SYMBOL_FLAG_REGISTER, 10417 "TX_X4_SP3_CRED0r", 10418 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10419 "TX_X4_CREDIT_SP3_CREDIT0", 10420 NULL, 10421 #endif 10422 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10423 0x0, /* 0 */ 10424 0, 10425 #endif 10426 }, 10427 { 10428 BCMI_QTC_XGXS_TX_X4_SP3_CRED1r, 10429 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10430 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 10431 BCMI_QTC_XGXS_TX_X4_SP3_CRED1r_fields, 10432 #else 10433 0, 10434 #endif 10435 #endif 10436 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10437 PHYMOD_SYMBOL_FLAG_REGISTER, 10438 "TX_X4_SP3_CRED1r", 10439 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10440 "TX_X4_CREDIT_SP3_CREDIT1", 10441 NULL, 10442 #endif 10443 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10444 0x0, /* 0 */ 10445 0, 10446 #endif 10447 }, 10448 { 10449 BCMI_QTC_XGXS_TX_X4_SP3_LOOPCNTr, 10450 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10451 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 10452 BCMI_QTC_XGXS_TX_X4_SP3_LOOPCNTr_fields, 10453 #else 10454 0, 10455 #endif 10456 #endif 10457 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10458 PHYMOD_SYMBOL_FLAG_REGISTER, 10459 "TX_X4_SP3_LOOPCNTr", 10460 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10461 "TX_X4_CREDIT_SP3_LOOPCNT", 10462 NULL, 10463 #endif 10464 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10465 0x0, /* 0 */ 10466 0, 10467 #endif 10468 }, 10469 { 10470 BCMI_QTC_XGXS_TX_X4_SP3_MAC_CREDGENCNTr, 10471 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10472 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 10473 BCMI_QTC_XGXS_TX_X4_SP3_MAC_CREDGENCNTr_fields, 10474 #else 10475 0, 10476 #endif 10477 #endif 10478 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10479 PHYMOD_SYMBOL_FLAG_REGISTER, 10480 "TX_X4_SP3_MAC_CREDGENCNTr", 10481 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10482 "TX_X4_CREDIT_SP3_MAC_CREDITGENCNT", 10483 NULL, 10484 #endif 10485 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10486 0x0, /* 0 */ 10487 0, 10488 #endif 10489 }, 10490 { 10491 BCMI_QTC_XGXS_TX_X4_SP3_PCS_CLKCNT0r, 10492 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10493 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 10494 BCMI_QTC_XGXS_TX_X4_SP3_PCS_CLKCNT0r_fields, 10495 #else 10496 0, 10497 #endif 10498 #endif 10499 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10500 PHYMOD_SYMBOL_FLAG_REGISTER, 10501 "TX_X4_SP3_PCS_CLKCNT0r", 10502 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10503 "TX_X4_CREDIT_SP3_PCS_CLOCKCNT0", 10504 NULL, 10505 #endif 10506 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10507 0x0, /* 0 */ 10508 0, 10509 #endif 10510 }, 10511 { 10512 BCMI_QTC_XGXS_TX_X4_SP3_PCS_CREDGENCNTr, 10513 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10514 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 10515 BCMI_QTC_XGXS_TX_X4_SP3_PCS_CREDGENCNTr_fields, 10516 #else 10517 0, 10518 #endif 10519 #endif 10520 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10521 PHYMOD_SYMBOL_FLAG_REGISTER, 10522 "TX_X4_SP3_PCS_CREDGENCNTr", 10523 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10524 "TX_X4_CREDIT_SP3_PCS_CREDITGENCNT", 10525 NULL, 10526 #endif 10527 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10528 0x0, /* 0 */ 10529 0, 10530 #endif 10531 }, 10532 { 10533 BCMI_QTC_XGXS_MISCr, 10534 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10535 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 10536 BCMI_QTC_XGXS_MISCr_fields, 10537 #else 10538 0, 10539 #endif 10540 #endif 10541 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10542 PHYMOD_SYMBOL_FLAG_REGISTER, 10543 "MISCr", 10544 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10545 "TX_X4_CONTROL0_MISC", 10546 NULL, 10547 #endif 10548 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10549 0x3c, /* 60 */ 10550 0, 10551 #endif 10552 }, 10553 { 10554 BCMI_QTC_XGXS_CL36TX_CTLr, 10555 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10556 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 10557 BCMI_QTC_XGXS_CL36TX_CTLr_fields, 10558 #else 10559 0, 10560 #endif 10561 #endif 10562 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10563 PHYMOD_SYMBOL_FLAG_REGISTER, 10564 "CL36TX_CTLr", 10565 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10566 "TX_X4_CONTROL0_CL36TX_CONTROL", 10567 NULL, 10568 #endif 10569 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10570 0x0, /* 0 */ 10571 0, 10572 #endif 10573 }, 10574 { 10575 BCMI_QTC_XGXS_CL36_FSM_STSr, 10576 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10577 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 10578 BCMI_QTC_XGXS_CL36_FSM_STSr_fields, 10579 #else 10580 0, 10581 #endif 10582 #endif 10583 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10584 PHYMOD_SYMBOL_FLAG_REGISTER, 10585 "CL36_FSM_STSr", 10586 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10587 "TX_X4_STATUS0_CL36_FSM_STATUS", 10588 NULL, 10589 #endif 10590 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10591 0x0, /* 0 */ 10592 0, 10593 #endif 10594 }, 10595 { 10596 BCMI_QTC_XGXS_TX_RATE_MISMATCHr, 10597 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10598 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 10599 BCMI_QTC_XGXS_TX_RATE_MISMATCHr_fields, 10600 #else 10601 0, 10602 #endif 10603 #endif 10604 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10605 PHYMOD_SYMBOL_FLAG_REGISTER, 10606 "TX_RATE_MISMATCHr", 10607 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10608 "TX_X4_STATUS0_TX_RATE_MISMATCH", 10609 NULL, 10610 #endif 10611 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10612 0x0, /* 0 */ 10613 0, 10614 #endif 10615 }, 10616 { 10617 BCMI_QTC_XGXS_PCS_CTLr, 10618 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10619 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 10620 BCMI_QTC_XGXS_PCS_CTLr_fields, 10621 #else 10622 0, 10623 #endif 10624 #endif 10625 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10626 PHYMOD_SYMBOL_FLAG_REGISTER, 10627 "PCS_CTLr", 10628 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10629 "RX_X4_CONTROL0_PCS_CONTROL", 10630 NULL, 10631 #endif 10632 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10633 0x0, /* 0 */ 10634 0, 10635 #endif 10636 }, 10637 { 10638 BCMI_QTC_XGXS_CL36_RXr, 10639 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10640 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 10641 BCMI_QTC_XGXS_CL36_RXr_fields, 10642 #else 10643 0, 10644 #endif 10645 #endif 10646 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10647 PHYMOD_SYMBOL_FLAG_REGISTER, 10648 "CL36_RXr", 10649 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10650 "RX_X4_CONTROL0_CL36_RX", 10651 NULL, 10652 #endif 10653 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10654 0x0, /* 0 */ 10655 0, 10656 #endif 10657 }, 10658 { 10659 BCMI_QTC_XGXS_PMA_CTLr, 10660 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10661 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 10662 BCMI_QTC_XGXS_PMA_CTLr_fields, 10663 #else 10664 0, 10665 #endif 10666 #endif 10667 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10668 PHYMOD_SYMBOL_FLAG_REGISTER, 10669 "PMA_CTLr", 10670 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10671 "RX_X4_CONTROL0_PMA_CONTROL", 10672 NULL, 10673 #endif 10674 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10675 0x0, /* 0 */ 10676 0, 10677 #endif 10678 }, 10679 { 10680 BCMI_QTC_XGXS_BARREL_SHIFTER_STr, 10681 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10682 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 10683 BCMI_QTC_XGXS_BARREL_SHIFTER_STr_fields, 10684 #else 10685 0, 10686 #endif 10687 #endif 10688 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10689 PHYMOD_SYMBOL_FLAG_REGISTER, 10690 "BARREL_SHIFTER_STr", 10691 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10692 "RX_X4_STATUS0_BARREL_SHIFTER_STATE", 10693 NULL, 10694 #endif 10695 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10696 0x0, /* 0 */ 10697 0, 10698 #endif 10699 }, 10700 { 10701 BCMI_QTC_XGXS_SYNCACQ_STS_0_SP0r, 10702 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10703 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 10704 BCMI_QTC_XGXS_SYNCACQ_STS_0_SP0r_fields, 10705 #else 10706 0, 10707 #endif 10708 #endif 10709 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10710 PHYMOD_SYMBOL_FLAG_REGISTER, 10711 "SYNCACQ_STS_0_SP0r", 10712 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10713 "RX_X4_STATUS0_SYNCACQ_STATUS_0_SP0", 10714 NULL, 10715 #endif 10716 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10717 0x0, /* 0 */ 10718 0, 10719 #endif 10720 }, 10721 { 10722 BCMI_QTC_XGXS_SYNCACQ_STS_1_SP0r, 10723 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10724 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 10725 BCMI_QTC_XGXS_SYNCACQ_STS_1_SP0r_fields, 10726 #else 10727 0, 10728 #endif 10729 #endif 10730 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10731 PHYMOD_SYMBOL_FLAG_REGISTER, 10732 "SYNCACQ_STS_1_SP0r", 10733 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10734 "RX_X4_STATUS0_SYNCACQ_STATUS_1_SP0", 10735 NULL, 10736 #endif 10737 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10738 0x0, /* 0 */ 10739 0, 10740 #endif 10741 }, 10742 { 10743 BCMI_QTC_XGXS_CL36_RXSM_BINARY_STSr, 10744 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10745 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 10746 BCMI_QTC_XGXS_CL36_RXSM_BINARY_STSr_fields, 10747 #else 10748 0, 10749 #endif 10750 #endif 10751 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10752 PHYMOD_SYMBOL_FLAG_REGISTER, 10753 "CL36_RXSM_BINARY_STSr", 10754 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10755 "RX_X4_STATUS0_CL36_RXSM_BINARY_STATUS", 10756 NULL, 10757 #endif 10758 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10759 0x0, /* 0 */ 10760 0, 10761 #endif 10762 }, 10763 { 10764 BCMI_QTC_XGXS_CL36_RXSM_ONEHOT_STS0r, 10765 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10766 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 10767 BCMI_QTC_XGXS_CL36_RXSM_ONEHOT_STS0r_fields, 10768 #else 10769 0, 10770 #endif 10771 #endif 10772 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10773 PHYMOD_SYMBOL_FLAG_REGISTER, 10774 "CL36_RXSM_ONEHOT_STS0r", 10775 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10776 "RX_X4_STATUS0_CL36_RXSM_ONEHOT_STATUS_0", 10777 NULL, 10778 #endif 10779 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10780 0x0, /* 0 */ 10781 0, 10782 #endif 10783 }, 10784 { 10785 BCMI_QTC_XGXS_CL36_RXSM_ONEHOT_STS1r, 10786 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10787 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 10788 BCMI_QTC_XGXS_CL36_RXSM_ONEHOT_STS1r_fields, 10789 #else 10790 0, 10791 #endif 10792 #endif 10793 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10794 PHYMOD_SYMBOL_FLAG_REGISTER, 10795 "CL36_RXSM_ONEHOT_STS1r", 10796 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10797 "RX_X4_STATUS0_CL36_RXSM_ONEHOT_STATUS_1", 10798 NULL, 10799 #endif 10800 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10801 0x0, /* 0 */ 10802 0, 10803 #endif 10804 }, 10805 { 10806 BCMI_QTC_XGXS_BERCNT0r, 10807 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10808 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 10809 BCMI_QTC_XGXS_BERCNT0r_fields, 10810 #else 10811 0, 10812 #endif 10813 #endif 10814 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10815 PHYMOD_SYMBOL_FLAG_REGISTER, 10816 "BERCNT0r", 10817 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10818 "RX_X4_STATUS0_BERCOUNT0", 10819 NULL, 10820 #endif 10821 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10822 0x0, /* 0 */ 10823 0, 10824 #endif 10825 }, 10826 { 10827 BCMI_QTC_XGXS_BERCNT1r, 10828 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10829 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 10830 BCMI_QTC_XGXS_BERCNT1r_fields, 10831 #else 10832 0, 10833 #endif 10834 #endif 10835 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10836 PHYMOD_SYMBOL_FLAG_REGISTER, 10837 "BERCNT1r", 10838 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10839 "RX_X4_STATUS0_BERCOUNT1", 10840 NULL, 10841 #endif 10842 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10843 0x0, /* 0 */ 10844 0, 10845 #endif 10846 }, 10847 { 10848 BCMI_QTC_XGXS_PCS_LATCH_STSr, 10849 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10850 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 10851 BCMI_QTC_XGXS_PCS_LATCH_STSr_fields, 10852 #else 10853 0, 10854 #endif 10855 #endif 10856 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10857 PHYMOD_SYMBOL_FLAG_REGISTER, 10858 "PCS_LATCH_STSr", 10859 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10860 "RX_X4_STATUS0_PCS_LATCHED_STATUS", 10861 NULL, 10862 #endif 10863 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10864 0x0, /* 0 */ 10865 0, 10866 #endif 10867 }, 10868 { 10869 BCMI_QTC_XGXS_PCS_LIVE_STSr, 10870 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10871 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 10872 BCMI_QTC_XGXS_PCS_LIVE_STSr_fields, 10873 #else 10874 0, 10875 #endif 10876 #endif 10877 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10878 PHYMOD_SYMBOL_FLAG_REGISTER, 10879 "PCS_LIVE_STSr", 10880 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10881 "RX_X4_STATUS0_PCS_LIVE_STATUS", 10882 NULL, 10883 #endif 10884 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10885 0x0, /* 0 */ 10886 0, 10887 #endif 10888 }, 10889 { 10890 BCMI_QTC_XGXS_GBOX_STSr, 10891 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10892 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 10893 BCMI_QTC_XGXS_GBOX_STSr_fields, 10894 #else 10895 0, 10896 #endif 10897 #endif 10898 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10899 PHYMOD_SYMBOL_FLAG_REGISTER, 10900 "GBOX_STSr", 10901 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10902 "RX_X4_STATUS0_GBOX_STATUS", 10903 NULL, 10904 #endif 10905 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10906 0x0, /* 0 */ 10907 0, 10908 #endif 10909 }, 10910 { 10911 BCMI_QTC_XGXS_RX_X4_CL49_CTL0_PCS_CTL0r, 10912 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10913 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 10914 BCMI_QTC_XGXS_RX_X4_CL49_CTL0_PCS_CTL0r_fields, 10915 #else 10916 0, 10917 #endif 10918 #endif 10919 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10920 PHYMOD_SYMBOL_FLAG_REGISTER, 10921 "RX_X4_CL49_CTL0_PCS_CTL0r", 10922 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10923 "RX_X4_CL49_CONTROL0_PCS_CONTROL_0", 10924 NULL, 10925 #endif 10926 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10927 0x8040, /* 32832 */ 10928 0, 10929 #endif 10930 }, 10931 { 10932 BCMI_QTC_XGXS_RX_X4_CL49_CTL0_DEC_CTL0r, 10933 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10934 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 10935 BCMI_QTC_XGXS_RX_X4_CL49_CTL0_DEC_CTL0r_fields, 10936 #else 10937 0, 10938 #endif 10939 #endif 10940 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10941 PHYMOD_SYMBOL_FLAG_REGISTER, 10942 "RX_X4_CL49_CTL0_DEC_CTL0r", 10943 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10944 "RX_X4_CL49_CONTROL0_DECODE_CONTROL_0", 10945 NULL, 10946 #endif 10947 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10948 0x7, /* 7 */ 10949 0, 10950 #endif 10951 }, 10952 { 10953 BCMI_QTC_XGXS_RX_X4_CL49_STS0_BARREL_SHIFTER_STr, 10954 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10955 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 10956 BCMI_QTC_XGXS_RX_X4_CL49_STS0_BARREL_SHIFTER_STr_fields, 10957 #else 10958 0, 10959 #endif 10960 #endif 10961 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10962 PHYMOD_SYMBOL_FLAG_REGISTER, 10963 "RX_X4_CL49_STS0_BARREL_SHIFTER_STr", 10964 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10965 "RX_X4_CL49_STATUS0_BARREL_SHIFTER_STATE", 10966 NULL, 10967 #endif 10968 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10969 0x0, /* 0 */ 10970 0, 10971 #endif 10972 }, 10973 { 10974 BCMI_QTC_XGXS_RX_X4_CL49_STS0_SYNC_FSM_STSr, 10975 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10976 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 10977 BCMI_QTC_XGXS_RX_X4_CL49_STS0_SYNC_FSM_STSr_fields, 10978 #else 10979 0, 10980 #endif 10981 #endif 10982 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 10983 PHYMOD_SYMBOL_FLAG_REGISTER, 10984 "RX_X4_CL49_STS0_SYNC_FSM_STSr", 10985 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 10986 "RX_X4_CL49_STATUS0_SYNC_FSM_STATUS", 10987 NULL, 10988 #endif 10989 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 10990 0x0, /* 0 */ 10991 0, 10992 #endif 10993 }, 10994 { 10995 BCMI_QTC_XGXS_RX_X4_CL49_STS0_AM_LOCK_STSr, 10996 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 10997 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 10998 BCMI_QTC_XGXS_RX_X4_CL49_STS0_AM_LOCK_STSr_fields, 10999 #else 11000 0, 11001 #endif 11002 #endif 11003 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11004 PHYMOD_SYMBOL_FLAG_REGISTER, 11005 "RX_X4_CL49_STS0_AM_LOCK_STSr", 11006 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11007 "RX_X4_CL49_STATUS0_AM_LOCK_STATUS", 11008 NULL, 11009 #endif 11010 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11011 0x0, /* 0 */ 11012 0, 11013 #endif 11014 }, 11015 { 11016 BCMI_QTC_XGXS_RX_X4_CL49_STS0_DEC_STS_SP0r, 11017 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11018 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 11019 BCMI_QTC_XGXS_RX_X4_CL49_STS0_DEC_STS_SP0r_fields, 11020 #else 11021 0, 11022 #endif 11023 #endif 11024 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11025 PHYMOD_SYMBOL_FLAG_REGISTER, 11026 "RX_X4_CL49_STS0_DEC_STS_SP0r", 11027 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11028 "RX_X4_CL49_STATUS0_DECODE_STATUS_SP0", 11029 NULL, 11030 #endif 11031 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11032 0x0, /* 0 */ 11033 0, 11034 #endif 11035 }, 11036 { 11037 BCMI_QTC_XGXS_RX_X4_CL49_STS0_DEC_STS_SP1r, 11038 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11039 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 11040 BCMI_QTC_XGXS_RX_X4_CL49_STS0_DEC_STS_SP1r_fields, 11041 #else 11042 0, 11043 #endif 11044 #endif 11045 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11046 PHYMOD_SYMBOL_FLAG_REGISTER, 11047 "RX_X4_CL49_STS0_DEC_STS_SP1r", 11048 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11049 "RX_X4_CL49_STATUS0_DECODE_STATUS_SP1", 11050 NULL, 11051 #endif 11052 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11053 0x0, /* 0 */ 11054 0, 11055 #endif 11056 }, 11057 { 11058 BCMI_QTC_XGXS_RX_X4_CL49_STS0_DEC_STS_SP2r, 11059 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11060 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 11061 BCMI_QTC_XGXS_RX_X4_CL49_STS0_DEC_STS_SP2r_fields, 11062 #else 11063 0, 11064 #endif 11065 #endif 11066 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11067 PHYMOD_SYMBOL_FLAG_REGISTER, 11068 "RX_X4_CL49_STS0_DEC_STS_SP2r", 11069 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11070 "RX_X4_CL49_STATUS0_DECODE_STATUS_SP2", 11071 NULL, 11072 #endif 11073 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11074 0x0, /* 0 */ 11075 0, 11076 #endif 11077 }, 11078 { 11079 BCMI_QTC_XGXS_RX_X4_CL49_STS0_DEC_STS_SP3r, 11080 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11081 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 11082 BCMI_QTC_XGXS_RX_X4_CL49_STS0_DEC_STS_SP3r_fields, 11083 #else 11084 0, 11085 #endif 11086 #endif 11087 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11088 PHYMOD_SYMBOL_FLAG_REGISTER, 11089 "RX_X4_CL49_STS0_DEC_STS_SP3r", 11090 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11091 "RX_X4_CL49_STATUS0_DECODE_STATUS_SP3", 11092 NULL, 11093 #endif 11094 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11095 0x0, /* 0 */ 11096 0, 11097 #endif 11098 }, 11099 { 11100 BCMI_QTC_XGXS_RX_X4_CL49_STS0_BERMON_STSr, 11101 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11102 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 11103 BCMI_QTC_XGXS_RX_X4_CL49_STS0_BERMON_STSr_fields, 11104 #else 11105 0, 11106 #endif 11107 #endif 11108 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11109 PHYMOD_SYMBOL_FLAG_REGISTER, 11110 "RX_X4_CL49_STS0_BERMON_STSr", 11111 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11112 "RX_X4_CL49_STATUS0_BERMON_STATUS", 11113 NULL, 11114 #endif 11115 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11116 0x0, /* 0 */ 11117 0, 11118 #endif 11119 }, 11120 { 11121 BCMI_QTC_XGXS_RX_X4_CL49_STS0_DEC_ERRED_BLKS_SP01r, 11122 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11123 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 11124 BCMI_QTC_XGXS_RX_X4_CL49_STS0_DEC_ERRED_BLKS_SP01r_fields, 11125 #else 11126 0, 11127 #endif 11128 #endif 11129 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11130 PHYMOD_SYMBOL_FLAG_REGISTER, 11131 "RX_X4_CL49_STS0_DEC_ERRED_BLKS_SP01r", 11132 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11133 "RX_X4_CL49_STATUS0_DECODE_ERRORED_BLOCKS_SP01", 11134 NULL, 11135 #endif 11136 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11137 0x0, /* 0 */ 11138 0, 11139 #endif 11140 }, 11141 { 11142 BCMI_QTC_XGXS_RX_X4_CL49_STS0_DEC_ERRED_BLKS_SP23r, 11143 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11144 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 11145 BCMI_QTC_XGXS_RX_X4_CL49_STS0_DEC_ERRED_BLKS_SP23r_fields, 11146 #else 11147 0, 11148 #endif 11149 #endif 11150 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11151 PHYMOD_SYMBOL_FLAG_REGISTER, 11152 "RX_X4_CL49_STS0_DEC_ERRED_BLKS_SP23r", 11153 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11154 "RX_X4_CL49_STATUS0_DECODE_ERRORED_BLOCKS_SP23", 11155 NULL, 11156 #endif 11157 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11158 0x0, /* 0 */ 11159 0, 11160 #endif 11161 }, 11162 { 11163 BCMI_QTC_XGXS_RX_X4_CL49_STS0_BERCNTr, 11164 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11165 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 11166 BCMI_QTC_XGXS_RX_X4_CL49_STS0_BERCNTr_fields, 11167 #else 11168 0, 11169 #endif 11170 #endif 11171 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11172 PHYMOD_SYMBOL_FLAG_REGISTER, 11173 "RX_X4_CL49_STS0_BERCNTr", 11174 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11175 "RX_X4_CL49_STATUS0_BERCOUNT", 11176 NULL, 11177 #endif 11178 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11179 0x0, /* 0 */ 11180 0, 11181 #endif 11182 }, 11183 { 11184 BCMI_QTC_XGXS_RX_X4_CL49_STS0_PCS_LATCH_STS0r, 11185 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11186 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 11187 BCMI_QTC_XGXS_RX_X4_CL49_STS0_PCS_LATCH_STS0r_fields, 11188 #else 11189 0, 11190 #endif 11191 #endif 11192 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11193 PHYMOD_SYMBOL_FLAG_REGISTER, 11194 "RX_X4_CL49_STS0_PCS_LATCH_STS0r", 11195 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11196 "RX_X4_CL49_STATUS0_PCS_LATCHED_STATUS_0", 11197 NULL, 11198 #endif 11199 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11200 0x0, /* 0 */ 11201 0, 11202 #endif 11203 }, 11204 { 11205 BCMI_QTC_XGXS_RX_X4_CL49_STS0_PCS_LATCH_STS1r, 11206 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11207 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 11208 BCMI_QTC_XGXS_RX_X4_CL49_STS0_PCS_LATCH_STS1r_fields, 11209 #else 11210 0, 11211 #endif 11212 #endif 11213 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11214 PHYMOD_SYMBOL_FLAG_REGISTER, 11215 "RX_X4_CL49_STS0_PCS_LATCH_STS1r", 11216 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11217 "RX_X4_CL49_STATUS0_PCS_LATCHED_STATUS_1", 11218 NULL, 11219 #endif 11220 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11221 0x0, /* 0 */ 11222 0, 11223 #endif 11224 }, 11225 { 11226 BCMI_QTC_XGXS_RX_X4_CL49_STS0_PCS_LIVE_STSr, 11227 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11228 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 11229 BCMI_QTC_XGXS_RX_X4_CL49_STS0_PCS_LIVE_STSr_fields, 11230 #else 11231 0, 11232 #endif 11233 #endif 11234 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11235 PHYMOD_SYMBOL_FLAG_REGISTER, 11236 "RX_X4_CL49_STS0_PCS_LIVE_STSr", 11237 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11238 "RX_X4_CL49_STATUS0_PCS_LIVE_STATUS", 11239 NULL, 11240 #endif 11241 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11242 0xf000, /* 61440 */ 11243 0, 11244 #endif 11245 }, 11246 { 11247 BCMI_QTC_XGXS_TX_X4_CL49_CTL0_TX_PCS_CTL0r, 11248 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11249 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 11250 BCMI_QTC_XGXS_TX_X4_CL49_CTL0_TX_PCS_CTL0r_fields, 11251 #else 11252 0, 11253 #endif 11254 #endif 11255 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11256 PHYMOD_SYMBOL_FLAG_REGISTER, 11257 "TX_X4_CL49_CTL0_TX_PCS_CTL0r", 11258 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11259 "TX_X4_CL49_CONTROL0_TX_PCS_CONTROL_0", 11260 NULL, 11261 #endif 11262 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11263 0x8000, /* 32768 */ 11264 0, 11265 #endif 11266 }, 11267 { 11268 BCMI_QTC_XGXS_TX_X4_CL49_CTL0_TX_ENC_CTL0r, 11269 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11270 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 11271 BCMI_QTC_XGXS_TX_X4_CL49_CTL0_TX_ENC_CTL0r_fields, 11272 #else 11273 0, 11274 #endif 11275 #endif 11276 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11277 PHYMOD_SYMBOL_FLAG_REGISTER, 11278 "TX_X4_CL49_CTL0_TX_ENC_CTL0r", 11279 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11280 "TX_X4_CL49_CONTROL0_TX_ENCODE_CONTROL_0", 11281 NULL, 11282 #endif 11283 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11284 0x7, /* 7 */ 11285 0, 11286 #endif 11287 }, 11288 { 11289 BCMI_QTC_XGXS_TX_X4_CL49_STS0_ENC_STS_SP0r, 11290 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11291 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 11292 BCMI_QTC_XGXS_TX_X4_CL49_STS0_ENC_STS_SP0r_fields, 11293 #else 11294 0, 11295 #endif 11296 #endif 11297 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11298 PHYMOD_SYMBOL_FLAG_REGISTER, 11299 "TX_X4_CL49_STS0_ENC_STS_SP0r", 11300 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11301 "TX_X4_CL49_STATUS0_ENCODE_STATUS_SP0", 11302 NULL, 11303 #endif 11304 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11305 0x0, /* 0 */ 11306 0, 11307 #endif 11308 }, 11309 { 11310 BCMI_QTC_XGXS_TX_X4_CL49_STS0_ENC_STS_SP1r, 11311 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11312 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 11313 BCMI_QTC_XGXS_TX_X4_CL49_STS0_ENC_STS_SP1r_fields, 11314 #else 11315 0, 11316 #endif 11317 #endif 11318 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11319 PHYMOD_SYMBOL_FLAG_REGISTER, 11320 "TX_X4_CL49_STS0_ENC_STS_SP1r", 11321 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11322 "TX_X4_CL49_STATUS0_ENCODE_STATUS_SP1", 11323 NULL, 11324 #endif 11325 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11326 0x0, /* 0 */ 11327 0, 11328 #endif 11329 }, 11330 { 11331 BCMI_QTC_XGXS_TX_X4_CL49_STS0_ENC_STS_SP2r, 11332 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11333 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 11334 BCMI_QTC_XGXS_TX_X4_CL49_STS0_ENC_STS_SP2r_fields, 11335 #else 11336 0, 11337 #endif 11338 #endif 11339 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11340 PHYMOD_SYMBOL_FLAG_REGISTER, 11341 "TX_X4_CL49_STS0_ENC_STS_SP2r", 11342 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11343 "TX_X4_CL49_STATUS0_ENCODE_STATUS_SP2", 11344 NULL, 11345 #endif 11346 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11347 0x0, /* 0 */ 11348 0, 11349 #endif 11350 }, 11351 { 11352 BCMI_QTC_XGXS_TX_X4_CL49_STS0_ENC_STS_SP3r, 11353 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11354 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 11355 BCMI_QTC_XGXS_TX_X4_CL49_STS0_ENC_STS_SP3r_fields, 11356 #else 11357 0, 11358 #endif 11359 #endif 11360 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11361 PHYMOD_SYMBOL_FLAG_REGISTER, 11362 "TX_X4_CL49_STS0_ENC_STS_SP3r", 11363 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11364 "TX_X4_CL49_STATUS0_ENCODE_STATUS_SP3", 11365 NULL, 11366 #endif 11367 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11368 0x0, /* 0 */ 11369 0, 11370 #endif 11371 }, 11372 { 11373 BCMI_QTC_XGXS_TX_X4_CL49_STS0_TX_PCS_LIVE_STSr, 11374 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11375 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 11376 BCMI_QTC_XGXS_TX_X4_CL49_STS0_TX_PCS_LIVE_STSr_fields, 11377 #else 11378 0, 11379 #endif 11380 #endif 11381 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11382 PHYMOD_SYMBOL_FLAG_REGISTER, 11383 "TX_X4_CL49_STS0_TX_PCS_LIVE_STSr", 11384 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11385 "TX_X4_CL49_STATUS0_TX_PCS_LIVE_STATUS", 11386 NULL, 11387 #endif 11388 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11389 0x0, /* 0 */ 11390 0, 11391 #endif 11392 }, 11393 { 11394 BCMI_QTC_XGXS_TX_X4_CL49_STS0_TX_PCS_LATCH_STSr, 11395 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11396 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 11397 BCMI_QTC_XGXS_TX_X4_CL49_STS0_TX_PCS_LATCH_STSr_fields, 11398 #else 11399 0, 11400 #endif 11401 #endif 11402 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11403 PHYMOD_SYMBOL_FLAG_REGISTER, 11404 "TX_X4_CL49_STS0_TX_PCS_LATCH_STSr", 11405 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11406 "TX_X4_CL49_STATUS0_TX_PCS_LATCHED_STATUS", 11407 NULL, 11408 #endif 11409 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11410 0x0, /* 0 */ 11411 0, 11412 #endif 11413 }, 11414 { 11415 BCMI_QTC_XGXS_AN_X4_ABI_SP0_ENSr, 11416 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11417 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 11418 BCMI_QTC_XGXS_AN_X4_ABI_SP0_ENSr_fields, 11419 #else 11420 0, 11421 #endif 11422 #endif 11423 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11424 PHYMOD_SYMBOL_FLAG_REGISTER, 11425 "AN_X4_ABI_SP0_ENSr", 11426 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11427 "AN_X4_ABILITIES_SP0_ENABLES", 11428 NULL, 11429 #endif 11430 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11431 0x0, /* 0 */ 11432 0, 11433 #endif 11434 }, 11435 { 11436 BCMI_QTC_XGXS_AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr, 11437 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11438 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 11439 BCMI_QTC_XGXS_AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_fields, 11440 #else 11441 0, 11442 #endif 11443 #endif 11444 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11445 PHYMOD_SYMBOL_FLAG_REGISTER, 11446 "AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr", 11447 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11448 "AN_X4_ABILITIES_SP0_LOCAL_DEVICE_CL37_BASE_ABILITIES", 11449 NULL, 11450 #endif 11451 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11452 0x2, /* 2 */ 11453 0, 11454 #endif 11455 }, 11456 { 11457 BCMI_QTC_XGXS_AN_X4_ABI_SP0_LOC_DEV_CL37_BAM_ABILr, 11458 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11459 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 11460 BCMI_QTC_XGXS_AN_X4_ABI_SP0_LOC_DEV_CL37_BAM_ABILr_fields, 11461 #else 11462 0, 11463 #endif 11464 #endif 11465 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11466 PHYMOD_SYMBOL_FLAG_REGISTER, 11467 "AN_X4_ABI_SP0_LOC_DEV_CL37_BAM_ABILr", 11468 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11469 "AN_X4_ABILITIES_SP0_LOCAL_DEVICE_CL37_BAM_ABILITIES", 11470 NULL, 11471 #endif 11472 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11473 0x0, /* 0 */ 11474 0, 11475 #endif 11476 }, 11477 { 11478 BCMI_QTC_XGXS_AN_X4_ABI_SP0_LOC_DEV_OVER1G_ABIL0r, 11479 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11480 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 11481 BCMI_QTC_XGXS_AN_X4_ABI_SP0_LOC_DEV_OVER1G_ABIL0r_fields, 11482 #else 11483 0, 11484 #endif 11485 #endif 11486 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11487 PHYMOD_SYMBOL_FLAG_REGISTER, 11488 "AN_X4_ABI_SP0_LOC_DEV_OVER1G_ABIL0r", 11489 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11490 "AN_X4_ABILITIES_SP0_LOCAL_DEVICE_OVER1G_ABILITIES_0", 11491 NULL, 11492 #endif 11493 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11494 0x0, /* 0 */ 11495 0, 11496 #endif 11497 }, 11498 { 11499 BCMI_QTC_XGXS_AN_X4_ABI_SP0_CTLSr, 11500 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11501 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 11502 BCMI_QTC_XGXS_AN_X4_ABI_SP0_CTLSr_fields, 11503 #else 11504 0, 11505 #endif 11506 #endif 11507 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11508 PHYMOD_SYMBOL_FLAG_REGISTER, 11509 "AN_X4_ABI_SP0_CTLSr", 11510 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11511 "AN_X4_ABILITIES_SP0_CONTROLS", 11512 NULL, 11513 #endif 11514 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11515 0x0, /* 0 */ 11516 0, 11517 #endif 11518 }, 11519 { 11520 BCMI_QTC_XGXS_AN_X4_ABI_SP1_ENSr, 11521 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11522 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 11523 BCMI_QTC_XGXS_AN_X4_ABI_SP1_ENSr_fields, 11524 #else 11525 0, 11526 #endif 11527 #endif 11528 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11529 PHYMOD_SYMBOL_FLAG_REGISTER, 11530 "AN_X4_ABI_SP1_ENSr", 11531 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11532 "AN_X4_ABILITIES_SP1_ENABLES", 11533 NULL, 11534 #endif 11535 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11536 0x0, /* 0 */ 11537 0, 11538 #endif 11539 }, 11540 { 11541 BCMI_QTC_XGXS_AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr, 11542 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11543 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 11544 BCMI_QTC_XGXS_AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_fields, 11545 #else 11546 0, 11547 #endif 11548 #endif 11549 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11550 PHYMOD_SYMBOL_FLAG_REGISTER, 11551 "AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr", 11552 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11553 "AN_X4_ABILITIES_SP1_LOCAL_DEVICE_CL37_BASE_ABILITIES", 11554 NULL, 11555 #endif 11556 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11557 0x2, /* 2 */ 11558 0, 11559 #endif 11560 }, 11561 { 11562 BCMI_QTC_XGXS_AN_X4_ABI_SP1_LOC_DEV_CL37_BAM_ABILr, 11563 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11564 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 11565 BCMI_QTC_XGXS_AN_X4_ABI_SP1_LOC_DEV_CL37_BAM_ABILr_fields, 11566 #else 11567 0, 11568 #endif 11569 #endif 11570 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11571 PHYMOD_SYMBOL_FLAG_REGISTER, 11572 "AN_X4_ABI_SP1_LOC_DEV_CL37_BAM_ABILr", 11573 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11574 "AN_X4_ABILITIES_SP1_LOCAL_DEVICE_CL37_BAM_ABILITIES", 11575 NULL, 11576 #endif 11577 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11578 0x0, /* 0 */ 11579 0, 11580 #endif 11581 }, 11582 { 11583 BCMI_QTC_XGXS_AN_X4_ABI_SP1_LOC_DEV_OVER1G_ABIL0r, 11584 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11585 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 11586 BCMI_QTC_XGXS_AN_X4_ABI_SP1_LOC_DEV_OVER1G_ABIL0r_fields, 11587 #else 11588 0, 11589 #endif 11590 #endif 11591 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11592 PHYMOD_SYMBOL_FLAG_REGISTER, 11593 "AN_X4_ABI_SP1_LOC_DEV_OVER1G_ABIL0r", 11594 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11595 "AN_X4_ABILITIES_SP1_LOCAL_DEVICE_OVER1G_ABILITIES_0", 11596 NULL, 11597 #endif 11598 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11599 0x0, /* 0 */ 11600 0, 11601 #endif 11602 }, 11603 { 11604 BCMI_QTC_XGXS_AN_X4_ABI_SP1_CTLSr, 11605 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11606 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 11607 BCMI_QTC_XGXS_AN_X4_ABI_SP1_CTLSr_fields, 11608 #else 11609 0, 11610 #endif 11611 #endif 11612 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11613 PHYMOD_SYMBOL_FLAG_REGISTER, 11614 "AN_X4_ABI_SP1_CTLSr", 11615 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11616 "AN_X4_ABILITIES_SP1_CONTROLS", 11617 NULL, 11618 #endif 11619 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11620 0x0, /* 0 */ 11621 0, 11622 #endif 11623 }, 11624 { 11625 BCMI_QTC_XGXS_AN_X4_ABI_SP2_ENSr, 11626 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11627 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 11628 BCMI_QTC_XGXS_AN_X4_ABI_SP2_ENSr_fields, 11629 #else 11630 0, 11631 #endif 11632 #endif 11633 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11634 PHYMOD_SYMBOL_FLAG_REGISTER, 11635 "AN_X4_ABI_SP2_ENSr", 11636 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11637 "AN_X4_ABILITIES_SP2_ENABLES", 11638 NULL, 11639 #endif 11640 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11641 0x0, /* 0 */ 11642 0, 11643 #endif 11644 }, 11645 { 11646 BCMI_QTC_XGXS_AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr, 11647 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11648 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 11649 BCMI_QTC_XGXS_AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_fields, 11650 #else 11651 0, 11652 #endif 11653 #endif 11654 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11655 PHYMOD_SYMBOL_FLAG_REGISTER, 11656 "AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr", 11657 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11658 "AN_X4_ABILITIES_SP2_LOCAL_DEVICE_CL37_BASE_ABILITIES", 11659 NULL, 11660 #endif 11661 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11662 0x2, /* 2 */ 11663 0, 11664 #endif 11665 }, 11666 { 11667 BCMI_QTC_XGXS_AN_X4_ABI_SP2_LOC_DEV_CL37_BAM_ABILr, 11668 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11669 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 11670 BCMI_QTC_XGXS_AN_X4_ABI_SP2_LOC_DEV_CL37_BAM_ABILr_fields, 11671 #else 11672 0, 11673 #endif 11674 #endif 11675 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11676 PHYMOD_SYMBOL_FLAG_REGISTER, 11677 "AN_X4_ABI_SP2_LOC_DEV_CL37_BAM_ABILr", 11678 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11679 "AN_X4_ABILITIES_SP2_LOCAL_DEVICE_CL37_BAM_ABILITIES", 11680 NULL, 11681 #endif 11682 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11683 0x0, /* 0 */ 11684 0, 11685 #endif 11686 }, 11687 { 11688 BCMI_QTC_XGXS_AN_X4_ABI_SP2_LOC_DEV_OVER1G_ABIL0r, 11689 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11690 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 11691 BCMI_QTC_XGXS_AN_X4_ABI_SP2_LOC_DEV_OVER1G_ABIL0r_fields, 11692 #else 11693 0, 11694 #endif 11695 #endif 11696 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11697 PHYMOD_SYMBOL_FLAG_REGISTER, 11698 "AN_X4_ABI_SP2_LOC_DEV_OVER1G_ABIL0r", 11699 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11700 "AN_X4_ABILITIES_SP2_LOCAL_DEVICE_OVER1G_ABILITIES_0", 11701 NULL, 11702 #endif 11703 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11704 0x0, /* 0 */ 11705 0, 11706 #endif 11707 }, 11708 { 11709 BCMI_QTC_XGXS_AN_X4_ABI_SP2_CTLSr, 11710 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11711 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 11712 BCMI_QTC_XGXS_AN_X4_ABI_SP2_CTLSr_fields, 11713 #else 11714 0, 11715 #endif 11716 #endif 11717 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11718 PHYMOD_SYMBOL_FLAG_REGISTER, 11719 "AN_X4_ABI_SP2_CTLSr", 11720 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11721 "AN_X4_ABILITIES_SP2_CONTROLS", 11722 NULL, 11723 #endif 11724 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11725 0x0, /* 0 */ 11726 0, 11727 #endif 11728 }, 11729 { 11730 BCMI_QTC_XGXS_AN_X4_ABI_SP3_ENSr, 11731 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11732 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 11733 BCMI_QTC_XGXS_AN_X4_ABI_SP3_ENSr_fields, 11734 #else 11735 0, 11736 #endif 11737 #endif 11738 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11739 PHYMOD_SYMBOL_FLAG_REGISTER, 11740 "AN_X4_ABI_SP3_ENSr", 11741 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11742 "AN_X4_ABILITIES_SP3_ENABLES", 11743 NULL, 11744 #endif 11745 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11746 0x0, /* 0 */ 11747 0, 11748 #endif 11749 }, 11750 { 11751 BCMI_QTC_XGXS_AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr, 11752 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11753 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 11754 BCMI_QTC_XGXS_AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_fields, 11755 #else 11756 0, 11757 #endif 11758 #endif 11759 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11760 PHYMOD_SYMBOL_FLAG_REGISTER, 11761 "AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr", 11762 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11763 "AN_X4_ABILITIES_SP3_LOCAL_DEVICE_CL37_BASE_ABILITIES", 11764 NULL, 11765 #endif 11766 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11767 0x2, /* 2 */ 11768 0, 11769 #endif 11770 }, 11771 { 11772 BCMI_QTC_XGXS_AN_X4_ABI_SP3_LOC_DEV_CL37_BAM_ABILr, 11773 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11774 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 11775 BCMI_QTC_XGXS_AN_X4_ABI_SP3_LOC_DEV_CL37_BAM_ABILr_fields, 11776 #else 11777 0, 11778 #endif 11779 #endif 11780 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11781 PHYMOD_SYMBOL_FLAG_REGISTER, 11782 "AN_X4_ABI_SP3_LOC_DEV_CL37_BAM_ABILr", 11783 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11784 "AN_X4_ABILITIES_SP3_LOCAL_DEVICE_CL37_BAM_ABILITIES", 11785 NULL, 11786 #endif 11787 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11788 0x0, /* 0 */ 11789 0, 11790 #endif 11791 }, 11792 { 11793 BCMI_QTC_XGXS_AN_X4_ABI_SP3_LOC_DEV_OVER1G_ABIL0r, 11794 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11795 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 11796 BCMI_QTC_XGXS_AN_X4_ABI_SP3_LOC_DEV_OVER1G_ABIL0r_fields, 11797 #else 11798 0, 11799 #endif 11800 #endif 11801 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11802 PHYMOD_SYMBOL_FLAG_REGISTER, 11803 "AN_X4_ABI_SP3_LOC_DEV_OVER1G_ABIL0r", 11804 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11805 "AN_X4_ABILITIES_SP3_LOCAL_DEVICE_OVER1G_ABILITIES_0", 11806 NULL, 11807 #endif 11808 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11809 0x0, /* 0 */ 11810 0, 11811 #endif 11812 }, 11813 { 11814 BCMI_QTC_XGXS_AN_X4_ABI_SP3_CTLSr, 11815 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11816 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 11817 BCMI_QTC_XGXS_AN_X4_ABI_SP3_CTLSr_fields, 11818 #else 11819 0, 11820 #endif 11821 #endif 11822 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11823 PHYMOD_SYMBOL_FLAG_REGISTER, 11824 "AN_X4_ABI_SP3_CTLSr", 11825 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11826 "AN_X4_ABILITIES_SP3_CONTROLS", 11827 NULL, 11828 #endif 11829 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11830 0x0, /* 0 */ 11831 0, 11832 #endif 11833 }, 11834 { 11835 BCMI_QTC_XGXS_AN_X4_LP_SP0_LP_MP5_UP1r, 11836 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11837 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 11838 BCMI_QTC_XGXS_AN_X4_LP_SP0_LP_MP5_UP1r_fields, 11839 #else 11840 0, 11841 #endif 11842 #endif 11843 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11844 PHYMOD_SYMBOL_FLAG_REGISTER, 11845 "AN_X4_LP_SP0_LP_MP5_UP1r", 11846 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11847 "AN_X4_LP_PAGES_SP0_LP_MP5_UP1", 11848 NULL, 11849 #endif 11850 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11851 0x0, /* 0 */ 11852 0, 11853 #endif 11854 }, 11855 { 11856 BCMI_QTC_XGXS_AN_X4_LP_SP0_LP_MP5_UP2r, 11857 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11858 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 11859 BCMI_QTC_XGXS_AN_X4_LP_SP0_LP_MP5_UP2r_fields, 11860 #else 11861 0, 11862 #endif 11863 #endif 11864 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11865 PHYMOD_SYMBOL_FLAG_REGISTER, 11866 "AN_X4_LP_SP0_LP_MP5_UP2r", 11867 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11868 "AN_X4_LP_PAGES_SP0_LP_MP5_UP2", 11869 NULL, 11870 #endif 11871 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11872 0x0, /* 0 */ 11873 0, 11874 #endif 11875 }, 11876 { 11877 BCMI_QTC_XGXS_AN_X4_LP_SP0_LP_MP5_UP3r, 11878 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11879 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 11880 BCMI_QTC_XGXS_AN_X4_LP_SP0_LP_MP5_UP3r_fields, 11881 #else 11882 0, 11883 #endif 11884 #endif 11885 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11886 PHYMOD_SYMBOL_FLAG_REGISTER, 11887 "AN_X4_LP_SP0_LP_MP5_UP3r", 11888 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11889 "AN_X4_LP_PAGES_SP0_LP_MP5_UP3", 11890 NULL, 11891 #endif 11892 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11893 0x0, /* 0 */ 11894 0, 11895 #endif 11896 }, 11897 { 11898 BCMI_QTC_XGXS_AN_X4_LP_SP0_LP_MP5_UP4r, 11899 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11900 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 11901 BCMI_QTC_XGXS_AN_X4_LP_SP0_LP_MP5_UP4r_fields, 11902 #else 11903 0, 11904 #endif 11905 #endif 11906 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11907 PHYMOD_SYMBOL_FLAG_REGISTER, 11908 "AN_X4_LP_SP0_LP_MP5_UP4r", 11909 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11910 "AN_X4_LP_PAGES_SP0_LP_MP5_UP4", 11911 NULL, 11912 #endif 11913 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11914 0x0, /* 0 */ 11915 0, 11916 #endif 11917 }, 11918 { 11919 BCMI_QTC_XGXS_AN_X4_LP_SP0_LP_MP1024_UP1r, 11920 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11921 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 11922 BCMI_QTC_XGXS_AN_X4_LP_SP0_LP_MP1024_UP1r_fields, 11923 #else 11924 0, 11925 #endif 11926 #endif 11927 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11928 PHYMOD_SYMBOL_FLAG_REGISTER, 11929 "AN_X4_LP_SP0_LP_MP1024_UP1r", 11930 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11931 "AN_X4_LP_PAGES_SP0_LP_MP1024_UP1", 11932 NULL, 11933 #endif 11934 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11935 0x0, /* 0 */ 11936 0, 11937 #endif 11938 }, 11939 { 11940 BCMI_QTC_XGXS_AN_X4_LP_SP0_LP_MP1024_UP2r, 11941 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11942 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 11943 BCMI_QTC_XGXS_AN_X4_LP_SP0_LP_MP1024_UP2r_fields, 11944 #else 11945 0, 11946 #endif 11947 #endif 11948 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11949 PHYMOD_SYMBOL_FLAG_REGISTER, 11950 "AN_X4_LP_SP0_LP_MP1024_UP2r", 11951 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11952 "AN_X4_LP_PAGES_SP0_LP_MP1024_UP2", 11953 NULL, 11954 #endif 11955 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11956 0x0, /* 0 */ 11957 0, 11958 #endif 11959 }, 11960 { 11961 BCMI_QTC_XGXS_AN_X4_LP_SP0_LP_MP1024_UP3r, 11962 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11963 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 11964 BCMI_QTC_XGXS_AN_X4_LP_SP0_LP_MP1024_UP3r_fields, 11965 #else 11966 0, 11967 #endif 11968 #endif 11969 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11970 PHYMOD_SYMBOL_FLAG_REGISTER, 11971 "AN_X4_LP_SP0_LP_MP1024_UP3r", 11972 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11973 "AN_X4_LP_PAGES_SP0_LP_MP1024_UP3", 11974 NULL, 11975 #endif 11976 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11977 0x0, /* 0 */ 11978 0, 11979 #endif 11980 }, 11981 { 11982 BCMI_QTC_XGXS_AN_X4_LP_SP0_LP_MP1024_UP4r, 11983 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 11984 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 11985 BCMI_QTC_XGXS_AN_X4_LP_SP0_LP_MP1024_UP4r_fields, 11986 #else 11987 0, 11988 #endif 11989 #endif 11990 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 11991 PHYMOD_SYMBOL_FLAG_REGISTER, 11992 "AN_X4_LP_SP0_LP_MP1024_UP4r", 11993 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 11994 "AN_X4_LP_PAGES_SP0_LP_MP1024_UP4", 11995 NULL, 11996 #endif 11997 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 11998 0x0, /* 0 */ 11999 0, 12000 #endif 12001 }, 12002 { 12003 BCMI_QTC_XGXS_AN_X4_LP_SP0_LP_BASE_PAGE1r, 12004 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12005 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 12006 BCMI_QTC_XGXS_AN_X4_LP_SP0_LP_BASE_PAGE1r_fields, 12007 #else 12008 0, 12009 #endif 12010 #endif 12011 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12012 PHYMOD_SYMBOL_FLAG_REGISTER, 12013 "AN_X4_LP_SP0_LP_BASE_PAGE1r", 12014 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12015 "AN_X4_LP_PAGES_SP0_LP_BASE_PAGE1", 12016 NULL, 12017 #endif 12018 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12019 0x0, /* 0 */ 12020 0, 12021 #endif 12022 }, 12023 { 12024 BCMI_QTC_XGXS_AN_X4_LP_SP0_LP_BASE_PAGE2r, 12025 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12026 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 12027 BCMI_QTC_XGXS_AN_X4_LP_SP0_LP_BASE_PAGE2r_fields, 12028 #else 12029 0, 12030 #endif 12031 #endif 12032 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12033 PHYMOD_SYMBOL_FLAG_REGISTER, 12034 "AN_X4_LP_SP0_LP_BASE_PAGE2r", 12035 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12036 "AN_X4_LP_PAGES_SP0_LP_BASE_PAGE2", 12037 NULL, 12038 #endif 12039 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12040 0x0, /* 0 */ 12041 0, 12042 #endif 12043 }, 12044 { 12045 BCMI_QTC_XGXS_AN_X4_LP_SP0_LP_BASE_PAGE3r, 12046 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12047 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 12048 BCMI_QTC_XGXS_AN_X4_LP_SP0_LP_BASE_PAGE3r_fields, 12049 #else 12050 0, 12051 #endif 12052 #endif 12053 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12054 PHYMOD_SYMBOL_FLAG_REGISTER, 12055 "AN_X4_LP_SP0_LP_BASE_PAGE3r", 12056 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12057 "AN_X4_LP_PAGES_SP0_LP_BASE_PAGE3", 12058 NULL, 12059 #endif 12060 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12061 0x0, /* 0 */ 12062 0, 12063 #endif 12064 }, 12065 { 12066 BCMI_QTC_XGXS_AN_X4_LP_SP1_LP_MP5_UP1r, 12067 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12068 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 12069 BCMI_QTC_XGXS_AN_X4_LP_SP1_LP_MP5_UP1r_fields, 12070 #else 12071 0, 12072 #endif 12073 #endif 12074 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12075 PHYMOD_SYMBOL_FLAG_REGISTER, 12076 "AN_X4_LP_SP1_LP_MP5_UP1r", 12077 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12078 "AN_X4_LP_PAGES_SP1_LP_MP5_UP1", 12079 NULL, 12080 #endif 12081 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12082 0x0, /* 0 */ 12083 0, 12084 #endif 12085 }, 12086 { 12087 BCMI_QTC_XGXS_AN_X4_LP_SP1_LP_MP5_UP2r, 12088 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12089 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 12090 BCMI_QTC_XGXS_AN_X4_LP_SP1_LP_MP5_UP2r_fields, 12091 #else 12092 0, 12093 #endif 12094 #endif 12095 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12096 PHYMOD_SYMBOL_FLAG_REGISTER, 12097 "AN_X4_LP_SP1_LP_MP5_UP2r", 12098 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12099 "AN_X4_LP_PAGES_SP1_LP_MP5_UP2", 12100 NULL, 12101 #endif 12102 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12103 0x0, /* 0 */ 12104 0, 12105 #endif 12106 }, 12107 { 12108 BCMI_QTC_XGXS_AN_X4_LP_SP1_LP_MP5_UP3r, 12109 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12110 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 12111 BCMI_QTC_XGXS_AN_X4_LP_SP1_LP_MP5_UP3r_fields, 12112 #else 12113 0, 12114 #endif 12115 #endif 12116 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12117 PHYMOD_SYMBOL_FLAG_REGISTER, 12118 "AN_X4_LP_SP1_LP_MP5_UP3r", 12119 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12120 "AN_X4_LP_PAGES_SP1_LP_MP5_UP3", 12121 NULL, 12122 #endif 12123 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12124 0x0, /* 0 */ 12125 0, 12126 #endif 12127 }, 12128 { 12129 BCMI_QTC_XGXS_AN_X4_LP_SP1_LP_MP5_UP4r, 12130 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12131 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 12132 BCMI_QTC_XGXS_AN_X4_LP_SP1_LP_MP5_UP4r_fields, 12133 #else 12134 0, 12135 #endif 12136 #endif 12137 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12138 PHYMOD_SYMBOL_FLAG_REGISTER, 12139 "AN_X4_LP_SP1_LP_MP5_UP4r", 12140 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12141 "AN_X4_LP_PAGES_SP1_LP_MP5_UP4", 12142 NULL, 12143 #endif 12144 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12145 0x0, /* 0 */ 12146 0, 12147 #endif 12148 }, 12149 { 12150 BCMI_QTC_XGXS_AN_X4_LP_SP1_LP_MP1024_UP1r, 12151 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12152 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 12153 BCMI_QTC_XGXS_AN_X4_LP_SP1_LP_MP1024_UP1r_fields, 12154 #else 12155 0, 12156 #endif 12157 #endif 12158 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12159 PHYMOD_SYMBOL_FLAG_REGISTER, 12160 "AN_X4_LP_SP1_LP_MP1024_UP1r", 12161 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12162 "AN_X4_LP_PAGES_SP1_LP_MP1024_UP1", 12163 NULL, 12164 #endif 12165 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12166 0x0, /* 0 */ 12167 0, 12168 #endif 12169 }, 12170 { 12171 BCMI_QTC_XGXS_AN_X4_LP_SP1_LP_MP1024_UP2r, 12172 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12173 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 12174 BCMI_QTC_XGXS_AN_X4_LP_SP1_LP_MP1024_UP2r_fields, 12175 #else 12176 0, 12177 #endif 12178 #endif 12179 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12180 PHYMOD_SYMBOL_FLAG_REGISTER, 12181 "AN_X4_LP_SP1_LP_MP1024_UP2r", 12182 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12183 "AN_X4_LP_PAGES_SP1_LP_MP1024_UP2", 12184 NULL, 12185 #endif 12186 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12187 0x0, /* 0 */ 12188 0, 12189 #endif 12190 }, 12191 { 12192 BCMI_QTC_XGXS_AN_X4_LP_SP1_LP_MP1024_UP3r, 12193 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12194 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 12195 BCMI_QTC_XGXS_AN_X4_LP_SP1_LP_MP1024_UP3r_fields, 12196 #else 12197 0, 12198 #endif 12199 #endif 12200 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12201 PHYMOD_SYMBOL_FLAG_REGISTER, 12202 "AN_X4_LP_SP1_LP_MP1024_UP3r", 12203 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12204 "AN_X4_LP_PAGES_SP1_LP_MP1024_UP3", 12205 NULL, 12206 #endif 12207 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12208 0x0, /* 0 */ 12209 0, 12210 #endif 12211 }, 12212 { 12213 BCMI_QTC_XGXS_AN_X4_LP_SP1_LP_MP1024_UP4r, 12214 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12215 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 12216 BCMI_QTC_XGXS_AN_X4_LP_SP1_LP_MP1024_UP4r_fields, 12217 #else 12218 0, 12219 #endif 12220 #endif 12221 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12222 PHYMOD_SYMBOL_FLAG_REGISTER, 12223 "AN_X4_LP_SP1_LP_MP1024_UP4r", 12224 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12225 "AN_X4_LP_PAGES_SP1_LP_MP1024_UP4", 12226 NULL, 12227 #endif 12228 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12229 0x0, /* 0 */ 12230 0, 12231 #endif 12232 }, 12233 { 12234 BCMI_QTC_XGXS_AN_X4_LP_SP1_LP_BASE_PAGE1r, 12235 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12236 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 12237 BCMI_QTC_XGXS_AN_X4_LP_SP1_LP_BASE_PAGE1r_fields, 12238 #else 12239 0, 12240 #endif 12241 #endif 12242 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12243 PHYMOD_SYMBOL_FLAG_REGISTER, 12244 "AN_X4_LP_SP1_LP_BASE_PAGE1r", 12245 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12246 "AN_X4_LP_PAGES_SP1_LP_BASE_PAGE1", 12247 NULL, 12248 #endif 12249 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12250 0x0, /* 0 */ 12251 0, 12252 #endif 12253 }, 12254 { 12255 BCMI_QTC_XGXS_AN_X4_LP_SP1_LP_BASE_PAGE2r, 12256 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12257 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 12258 BCMI_QTC_XGXS_AN_X4_LP_SP1_LP_BASE_PAGE2r_fields, 12259 #else 12260 0, 12261 #endif 12262 #endif 12263 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12264 PHYMOD_SYMBOL_FLAG_REGISTER, 12265 "AN_X4_LP_SP1_LP_BASE_PAGE2r", 12266 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12267 "AN_X4_LP_PAGES_SP1_LP_BASE_PAGE2", 12268 NULL, 12269 #endif 12270 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12271 0x0, /* 0 */ 12272 0, 12273 #endif 12274 }, 12275 { 12276 BCMI_QTC_XGXS_AN_X4_LP_SP1_LP_BASE_PAGE3r, 12277 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12278 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 12279 BCMI_QTC_XGXS_AN_X4_LP_SP1_LP_BASE_PAGE3r_fields, 12280 #else 12281 0, 12282 #endif 12283 #endif 12284 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12285 PHYMOD_SYMBOL_FLAG_REGISTER, 12286 "AN_X4_LP_SP1_LP_BASE_PAGE3r", 12287 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12288 "AN_X4_LP_PAGES_SP1_LP_BASE_PAGE3", 12289 NULL, 12290 #endif 12291 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12292 0x0, /* 0 */ 12293 0, 12294 #endif 12295 }, 12296 { 12297 BCMI_QTC_XGXS_AN_X4_LP_SP2_LP_MP5_UP1r, 12298 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12299 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 12300 BCMI_QTC_XGXS_AN_X4_LP_SP2_LP_MP5_UP1r_fields, 12301 #else 12302 0, 12303 #endif 12304 #endif 12305 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12306 PHYMOD_SYMBOL_FLAG_REGISTER, 12307 "AN_X4_LP_SP2_LP_MP5_UP1r", 12308 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12309 "AN_X4_LP_PAGES_SP2_LP_MP5_UP1", 12310 NULL, 12311 #endif 12312 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12313 0x0, /* 0 */ 12314 0, 12315 #endif 12316 }, 12317 { 12318 BCMI_QTC_XGXS_AN_X4_LP_SP2_LP_MP5_UP2r, 12319 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12320 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 12321 BCMI_QTC_XGXS_AN_X4_LP_SP2_LP_MP5_UP2r_fields, 12322 #else 12323 0, 12324 #endif 12325 #endif 12326 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12327 PHYMOD_SYMBOL_FLAG_REGISTER, 12328 "AN_X4_LP_SP2_LP_MP5_UP2r", 12329 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12330 "AN_X4_LP_PAGES_SP2_LP_MP5_UP2", 12331 NULL, 12332 #endif 12333 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12334 0x0, /* 0 */ 12335 0, 12336 #endif 12337 }, 12338 { 12339 BCMI_QTC_XGXS_AN_X4_LP_SP2_LP_MP5_UP3r, 12340 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12341 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 12342 BCMI_QTC_XGXS_AN_X4_LP_SP2_LP_MP5_UP3r_fields, 12343 #else 12344 0, 12345 #endif 12346 #endif 12347 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12348 PHYMOD_SYMBOL_FLAG_REGISTER, 12349 "AN_X4_LP_SP2_LP_MP5_UP3r", 12350 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12351 "AN_X4_LP_PAGES_SP2_LP_MP5_UP3", 12352 NULL, 12353 #endif 12354 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12355 0x0, /* 0 */ 12356 0, 12357 #endif 12358 }, 12359 { 12360 BCMI_QTC_XGXS_AN_X4_LP_SP2_LP_MP5_UP4r, 12361 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12362 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 12363 BCMI_QTC_XGXS_AN_X4_LP_SP2_LP_MP5_UP4r_fields, 12364 #else 12365 0, 12366 #endif 12367 #endif 12368 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12369 PHYMOD_SYMBOL_FLAG_REGISTER, 12370 "AN_X4_LP_SP2_LP_MP5_UP4r", 12371 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12372 "AN_X4_LP_PAGES_SP2_LP_MP5_UP4", 12373 NULL, 12374 #endif 12375 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12376 0x0, /* 0 */ 12377 0, 12378 #endif 12379 }, 12380 { 12381 BCMI_QTC_XGXS_AN_X4_LP_SP2_LP_MP1024_UP1r, 12382 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12383 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 12384 BCMI_QTC_XGXS_AN_X4_LP_SP2_LP_MP1024_UP1r_fields, 12385 #else 12386 0, 12387 #endif 12388 #endif 12389 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12390 PHYMOD_SYMBOL_FLAG_REGISTER, 12391 "AN_X4_LP_SP2_LP_MP1024_UP1r", 12392 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12393 "AN_X4_LP_PAGES_SP2_LP_MP1024_UP1", 12394 NULL, 12395 #endif 12396 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12397 0x0, /* 0 */ 12398 0, 12399 #endif 12400 }, 12401 { 12402 BCMI_QTC_XGXS_AN_X4_LP_SP2_LP_MP1024_UP2r, 12403 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12404 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 12405 BCMI_QTC_XGXS_AN_X4_LP_SP2_LP_MP1024_UP2r_fields, 12406 #else 12407 0, 12408 #endif 12409 #endif 12410 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12411 PHYMOD_SYMBOL_FLAG_REGISTER, 12412 "AN_X4_LP_SP2_LP_MP1024_UP2r", 12413 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12414 "AN_X4_LP_PAGES_SP2_LP_MP1024_UP2", 12415 NULL, 12416 #endif 12417 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12418 0x0, /* 0 */ 12419 0, 12420 #endif 12421 }, 12422 { 12423 BCMI_QTC_XGXS_AN_X4_LP_SP2_LP_MP1024_UP3r, 12424 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12425 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 12426 BCMI_QTC_XGXS_AN_X4_LP_SP2_LP_MP1024_UP3r_fields, 12427 #else 12428 0, 12429 #endif 12430 #endif 12431 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12432 PHYMOD_SYMBOL_FLAG_REGISTER, 12433 "AN_X4_LP_SP2_LP_MP1024_UP3r", 12434 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12435 "AN_X4_LP_PAGES_SP2_LP_MP1024_UP3", 12436 NULL, 12437 #endif 12438 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12439 0x0, /* 0 */ 12440 0, 12441 #endif 12442 }, 12443 { 12444 BCMI_QTC_XGXS_AN_X4_LP_SP2_LP_MP1024_UP4r, 12445 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12446 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 12447 BCMI_QTC_XGXS_AN_X4_LP_SP2_LP_MP1024_UP4r_fields, 12448 #else 12449 0, 12450 #endif 12451 #endif 12452 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12453 PHYMOD_SYMBOL_FLAG_REGISTER, 12454 "AN_X4_LP_SP2_LP_MP1024_UP4r", 12455 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12456 "AN_X4_LP_PAGES_SP2_LP_MP1024_UP4", 12457 NULL, 12458 #endif 12459 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12460 0x0, /* 0 */ 12461 0, 12462 #endif 12463 }, 12464 { 12465 BCMI_QTC_XGXS_AN_X4_LP_SP2_LP_BASE_PAGE1r, 12466 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12467 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 12468 BCMI_QTC_XGXS_AN_X4_LP_SP2_LP_BASE_PAGE1r_fields, 12469 #else 12470 0, 12471 #endif 12472 #endif 12473 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12474 PHYMOD_SYMBOL_FLAG_REGISTER, 12475 "AN_X4_LP_SP2_LP_BASE_PAGE1r", 12476 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12477 "AN_X4_LP_PAGES_SP2_LP_BASE_PAGE1", 12478 NULL, 12479 #endif 12480 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12481 0x0, /* 0 */ 12482 0, 12483 #endif 12484 }, 12485 { 12486 BCMI_QTC_XGXS_AN_X4_LP_SP2_LP_BASE_PAGE2r, 12487 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12488 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 12489 BCMI_QTC_XGXS_AN_X4_LP_SP2_LP_BASE_PAGE2r_fields, 12490 #else 12491 0, 12492 #endif 12493 #endif 12494 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12495 PHYMOD_SYMBOL_FLAG_REGISTER, 12496 "AN_X4_LP_SP2_LP_BASE_PAGE2r", 12497 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12498 "AN_X4_LP_PAGES_SP2_LP_BASE_PAGE2", 12499 NULL, 12500 #endif 12501 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12502 0x0, /* 0 */ 12503 0, 12504 #endif 12505 }, 12506 { 12507 BCMI_QTC_XGXS_AN_X4_LP_SP2_LP_BASE_PAGE3r, 12508 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12509 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 12510 BCMI_QTC_XGXS_AN_X4_LP_SP2_LP_BASE_PAGE3r_fields, 12511 #else 12512 0, 12513 #endif 12514 #endif 12515 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12516 PHYMOD_SYMBOL_FLAG_REGISTER, 12517 "AN_X4_LP_SP2_LP_BASE_PAGE3r", 12518 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12519 "AN_X4_LP_PAGES_SP2_LP_BASE_PAGE3", 12520 NULL, 12521 #endif 12522 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12523 0x0, /* 0 */ 12524 0, 12525 #endif 12526 }, 12527 { 12528 BCMI_QTC_XGXS_AN_X4_LP_SP3_LP_MP5_UP1r, 12529 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12530 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 12531 BCMI_QTC_XGXS_AN_X4_LP_SP3_LP_MP5_UP1r_fields, 12532 #else 12533 0, 12534 #endif 12535 #endif 12536 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12537 PHYMOD_SYMBOL_FLAG_REGISTER, 12538 "AN_X4_LP_SP3_LP_MP5_UP1r", 12539 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12540 "AN_X4_LP_PAGES_SP3_LP_MP5_UP1", 12541 NULL, 12542 #endif 12543 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12544 0x0, /* 0 */ 12545 0, 12546 #endif 12547 }, 12548 { 12549 BCMI_QTC_XGXS_AN_X4_LP_SP3_LP_MP5_UP2r, 12550 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12551 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 12552 BCMI_QTC_XGXS_AN_X4_LP_SP3_LP_MP5_UP2r_fields, 12553 #else 12554 0, 12555 #endif 12556 #endif 12557 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12558 PHYMOD_SYMBOL_FLAG_REGISTER, 12559 "AN_X4_LP_SP3_LP_MP5_UP2r", 12560 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12561 "AN_X4_LP_PAGES_SP3_LP_MP5_UP2", 12562 NULL, 12563 #endif 12564 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12565 0x0, /* 0 */ 12566 0, 12567 #endif 12568 }, 12569 { 12570 BCMI_QTC_XGXS_AN_X4_LP_SP3_LP_MP5_UP3r, 12571 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12572 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 12573 BCMI_QTC_XGXS_AN_X4_LP_SP3_LP_MP5_UP3r_fields, 12574 #else 12575 0, 12576 #endif 12577 #endif 12578 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12579 PHYMOD_SYMBOL_FLAG_REGISTER, 12580 "AN_X4_LP_SP3_LP_MP5_UP3r", 12581 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12582 "AN_X4_LP_PAGES_SP3_LP_MP5_UP3", 12583 NULL, 12584 #endif 12585 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12586 0x0, /* 0 */ 12587 0, 12588 #endif 12589 }, 12590 { 12591 BCMI_QTC_XGXS_AN_X4_LP_SP3_LP_MP5_UP4r, 12592 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12593 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 12594 BCMI_QTC_XGXS_AN_X4_LP_SP3_LP_MP5_UP4r_fields, 12595 #else 12596 0, 12597 #endif 12598 #endif 12599 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12600 PHYMOD_SYMBOL_FLAG_REGISTER, 12601 "AN_X4_LP_SP3_LP_MP5_UP4r", 12602 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12603 "AN_X4_LP_PAGES_SP3_LP_MP5_UP4", 12604 NULL, 12605 #endif 12606 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12607 0x0, /* 0 */ 12608 0, 12609 #endif 12610 }, 12611 { 12612 BCMI_QTC_XGXS_AN_X4_LP_SP3_LP_MP1024_UP1r, 12613 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12614 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 12615 BCMI_QTC_XGXS_AN_X4_LP_SP3_LP_MP1024_UP1r_fields, 12616 #else 12617 0, 12618 #endif 12619 #endif 12620 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12621 PHYMOD_SYMBOL_FLAG_REGISTER, 12622 "AN_X4_LP_SP3_LP_MP1024_UP1r", 12623 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12624 "AN_X4_LP_PAGES_SP3_LP_MP1024_UP1", 12625 NULL, 12626 #endif 12627 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12628 0x0, /* 0 */ 12629 0, 12630 #endif 12631 }, 12632 { 12633 BCMI_QTC_XGXS_AN_X4_LP_SP3_LP_MP1024_UP2r, 12634 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12635 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 12636 BCMI_QTC_XGXS_AN_X4_LP_SP3_LP_MP1024_UP2r_fields, 12637 #else 12638 0, 12639 #endif 12640 #endif 12641 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12642 PHYMOD_SYMBOL_FLAG_REGISTER, 12643 "AN_X4_LP_SP3_LP_MP1024_UP2r", 12644 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12645 "AN_X4_LP_PAGES_SP3_LP_MP1024_UP2", 12646 NULL, 12647 #endif 12648 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12649 0x0, /* 0 */ 12650 0, 12651 #endif 12652 }, 12653 { 12654 BCMI_QTC_XGXS_AN_X4_LP_SP3_LP_MP1024_UP3r, 12655 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12656 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 12657 BCMI_QTC_XGXS_AN_X4_LP_SP3_LP_MP1024_UP3r_fields, 12658 #else 12659 0, 12660 #endif 12661 #endif 12662 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12663 PHYMOD_SYMBOL_FLAG_REGISTER, 12664 "AN_X4_LP_SP3_LP_MP1024_UP3r", 12665 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12666 "AN_X4_LP_PAGES_SP3_LP_MP1024_UP3", 12667 NULL, 12668 #endif 12669 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12670 0x0, /* 0 */ 12671 0, 12672 #endif 12673 }, 12674 { 12675 BCMI_QTC_XGXS_AN_X4_LP_SP3_LP_MP1024_UP4r, 12676 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12677 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 12678 BCMI_QTC_XGXS_AN_X4_LP_SP3_LP_MP1024_UP4r_fields, 12679 #else 12680 0, 12681 #endif 12682 #endif 12683 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12684 PHYMOD_SYMBOL_FLAG_REGISTER, 12685 "AN_X4_LP_SP3_LP_MP1024_UP4r", 12686 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12687 "AN_X4_LP_PAGES_SP3_LP_MP1024_UP4", 12688 NULL, 12689 #endif 12690 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12691 0x0, /* 0 */ 12692 0, 12693 #endif 12694 }, 12695 { 12696 BCMI_QTC_XGXS_AN_X4_LP_SP3_LP_BASE_PAGE1r, 12697 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12698 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 12699 BCMI_QTC_XGXS_AN_X4_LP_SP3_LP_BASE_PAGE1r_fields, 12700 #else 12701 0, 12702 #endif 12703 #endif 12704 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12705 PHYMOD_SYMBOL_FLAG_REGISTER, 12706 "AN_X4_LP_SP3_LP_BASE_PAGE1r", 12707 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12708 "AN_X4_LP_PAGES_SP3_LP_BASE_PAGE1", 12709 NULL, 12710 #endif 12711 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12712 0x0, /* 0 */ 12713 0, 12714 #endif 12715 }, 12716 { 12717 BCMI_QTC_XGXS_AN_X4_LP_SP3_LP_BASE_PAGE2r, 12718 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12719 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 12720 BCMI_QTC_XGXS_AN_X4_LP_SP3_LP_BASE_PAGE2r_fields, 12721 #else 12722 0, 12723 #endif 12724 #endif 12725 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12726 PHYMOD_SYMBOL_FLAG_REGISTER, 12727 "AN_X4_LP_SP3_LP_BASE_PAGE2r", 12728 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12729 "AN_X4_LP_PAGES_SP3_LP_BASE_PAGE2", 12730 NULL, 12731 #endif 12732 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12733 0x0, /* 0 */ 12734 0, 12735 #endif 12736 }, 12737 { 12738 BCMI_QTC_XGXS_AN_X4_LP_SP3_LP_BASE_PAGE3r, 12739 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12740 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 12741 BCMI_QTC_XGXS_AN_X4_LP_SP3_LP_BASE_PAGE3r_fields, 12742 #else 12743 0, 12744 #endif 12745 #endif 12746 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12747 PHYMOD_SYMBOL_FLAG_REGISTER, 12748 "AN_X4_LP_SP3_LP_BASE_PAGE3r", 12749 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12750 "AN_X4_LP_PAGES_SP3_LP_BASE_PAGE3", 12751 NULL, 12752 #endif 12753 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12754 0x0, /* 0 */ 12755 0, 12756 #endif 12757 }, 12758 { 12759 BCMI_QTC_XGXS_AN_X4_SW_SP0_LD_PAGE2r, 12760 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12761 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 12762 BCMI_QTC_XGXS_AN_X4_SW_SP0_LD_PAGE2r_fields, 12763 #else 12764 0, 12765 #endif 12766 #endif 12767 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12768 PHYMOD_SYMBOL_FLAG_REGISTER, 12769 "AN_X4_SW_SP0_LD_PAGE2r", 12770 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12771 "AN_X4_SW_MANAGEMENT_SP0_LD_PAGE_2", 12772 NULL, 12773 #endif 12774 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12775 0x0, /* 0 */ 12776 0, 12777 #endif 12778 }, 12779 { 12780 BCMI_QTC_XGXS_AN_X4_SW_SP0_LD_PAGE1r, 12781 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12782 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 12783 BCMI_QTC_XGXS_AN_X4_SW_SP0_LD_PAGE1r_fields, 12784 #else 12785 0, 12786 #endif 12787 #endif 12788 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12789 PHYMOD_SYMBOL_FLAG_REGISTER, 12790 "AN_X4_SW_SP0_LD_PAGE1r", 12791 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12792 "AN_X4_SW_MANAGEMENT_SP0_LD_PAGE_1", 12793 NULL, 12794 #endif 12795 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12796 0x0, /* 0 */ 12797 0, 12798 #endif 12799 }, 12800 { 12801 BCMI_QTC_XGXS_AN_X4_SW_SP0_LD_PAGE0r, 12802 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12803 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 12804 BCMI_QTC_XGXS_AN_X4_SW_SP0_LD_PAGE0r_fields, 12805 #else 12806 0, 12807 #endif 12808 #endif 12809 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12810 PHYMOD_SYMBOL_FLAG_REGISTER, 12811 "AN_X4_SW_SP0_LD_PAGE0r", 12812 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12813 "AN_X4_SW_MANAGEMENT_SP0_LD_PAGE_0", 12814 NULL, 12815 #endif 12816 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12817 0x0, /* 0 */ 12818 0, 12819 #endif 12820 }, 12821 { 12822 BCMI_QTC_XGXS_AN_X4_SW_SP0_LP_PAGE2r, 12823 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12824 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 12825 BCMI_QTC_XGXS_AN_X4_SW_SP0_LP_PAGE2r_fields, 12826 #else 12827 0, 12828 #endif 12829 #endif 12830 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12831 PHYMOD_SYMBOL_FLAG_REGISTER, 12832 "AN_X4_SW_SP0_LP_PAGE2r", 12833 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12834 "AN_X4_SW_MANAGEMENT_SP0_LP_PAGE_2", 12835 NULL, 12836 #endif 12837 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12838 0x0, /* 0 */ 12839 0, 12840 #endif 12841 }, 12842 { 12843 BCMI_QTC_XGXS_AN_X4_SW_SP0_LP_PAGE1r, 12844 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12845 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 12846 BCMI_QTC_XGXS_AN_X4_SW_SP0_LP_PAGE1r_fields, 12847 #else 12848 0, 12849 #endif 12850 #endif 12851 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12852 PHYMOD_SYMBOL_FLAG_REGISTER, 12853 "AN_X4_SW_SP0_LP_PAGE1r", 12854 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12855 "AN_X4_SW_MANAGEMENT_SP0_LP_PAGE_1", 12856 NULL, 12857 #endif 12858 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12859 0x0, /* 0 */ 12860 0, 12861 #endif 12862 }, 12863 { 12864 BCMI_QTC_XGXS_AN_X4_SW_SP0_LP_PAGE0r, 12865 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12866 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 12867 BCMI_QTC_XGXS_AN_X4_SW_SP0_LP_PAGE0r_fields, 12868 #else 12869 0, 12870 #endif 12871 #endif 12872 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12873 PHYMOD_SYMBOL_FLAG_REGISTER, 12874 "AN_X4_SW_SP0_LP_PAGE0r", 12875 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12876 "AN_X4_SW_MANAGEMENT_SP0_LP_PAGE_0", 12877 NULL, 12878 #endif 12879 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12880 0x0, /* 0 */ 12881 0, 12882 #endif 12883 }, 12884 { 12885 BCMI_QTC_XGXS_AN_X4_SW_SP0_SW_CTL_STSr, 12886 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12887 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 12888 BCMI_QTC_XGXS_AN_X4_SW_SP0_SW_CTL_STSr_fields, 12889 #else 12890 0, 12891 #endif 12892 #endif 12893 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12894 PHYMOD_SYMBOL_FLAG_REGISTER, 12895 "AN_X4_SW_SP0_SW_CTL_STSr", 12896 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12897 "AN_X4_SW_MANAGEMENT_SP0_SW_CONTROL_STATUS", 12898 NULL, 12899 #endif 12900 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12901 0x0, /* 0 */ 12902 0, 12903 #endif 12904 }, 12905 { 12906 BCMI_QTC_XGXS_AN_X4_SW_SP0_LD_CTLr, 12907 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12908 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 12909 BCMI_QTC_XGXS_AN_X4_SW_SP0_LD_CTLr_fields, 12910 #else 12911 0, 12912 #endif 12913 #endif 12914 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12915 PHYMOD_SYMBOL_FLAG_REGISTER, 12916 "AN_X4_SW_SP0_LD_CTLr", 12917 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12918 "AN_X4_SW_MANAGEMENT_SP0_LD_CONTROL", 12919 NULL, 12920 #endif 12921 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12922 0x0, /* 0 */ 12923 0, 12924 #endif 12925 }, 12926 { 12927 BCMI_QTC_XGXS_AN_X4_SW_SP0_AN_PAGE_SEQUENCER_STSr, 12928 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12929 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 12930 BCMI_QTC_XGXS_AN_X4_SW_SP0_AN_PAGE_SEQUENCER_STSr_fields, 12931 #else 12932 0, 12933 #endif 12934 #endif 12935 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12936 PHYMOD_SYMBOL_FLAG_REGISTER, 12937 "AN_X4_SW_SP0_AN_PAGE_SEQUENCER_STSr", 12938 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12939 "AN_X4_SW_MANAGEMENT_SP0_AN_PAGE_SEQUENCER_STATUS", 12940 NULL, 12941 #endif 12942 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12943 0x0, /* 0 */ 12944 0, 12945 #endif 12946 }, 12947 { 12948 BCMI_QTC_XGXS_AN_X4_SW_SP0_AN_PAGE_EXCHANGEER_STSr, 12949 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12950 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 12951 BCMI_QTC_XGXS_AN_X4_SW_SP0_AN_PAGE_EXCHANGEER_STSr_fields, 12952 #else 12953 0, 12954 #endif 12955 #endif 12956 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12957 PHYMOD_SYMBOL_FLAG_REGISTER, 12958 "AN_X4_SW_SP0_AN_PAGE_EXCHANGEER_STSr", 12959 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12960 "AN_X4_SW_MANAGEMENT_SP0_AN_PAGE_EXCHANGEER_STATUS", 12961 NULL, 12962 #endif 12963 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12964 0x0, /* 0 */ 12965 0, 12966 #endif 12967 }, 12968 { 12969 BCMI_QTC_XGXS_AN_X4_SW_SP0_AN_PAGE_DECR_STSr, 12970 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12971 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 12972 BCMI_QTC_XGXS_AN_X4_SW_SP0_AN_PAGE_DECR_STSr_fields, 12973 #else 12974 0, 12975 #endif 12976 #endif 12977 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12978 PHYMOD_SYMBOL_FLAG_REGISTER, 12979 "AN_X4_SW_SP0_AN_PAGE_DECR_STSr", 12980 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 12981 "AN_X4_SW_MANAGEMENT_SP0_AN_PAGE_DECODER_STATUS", 12982 NULL, 12983 #endif 12984 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 12985 0x0, /* 0 */ 12986 0, 12987 #endif 12988 }, 12989 { 12990 BCMI_QTC_XGXS_AN_X4_SW_SP0_AN_ABIL_RESOLUTION_STSr, 12991 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 12992 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 12993 BCMI_QTC_XGXS_AN_X4_SW_SP0_AN_ABIL_RESOLUTION_STSr_fields, 12994 #else 12995 0, 12996 #endif 12997 #endif 12998 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 12999 PHYMOD_SYMBOL_FLAG_REGISTER, 13000 "AN_X4_SW_SP0_AN_ABIL_RESOLUTION_STSr", 13001 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13002 "AN_X4_SW_MANAGEMENT_SP0_AN_ABILITY_RESOLUTION_STATUS", 13003 NULL, 13004 #endif 13005 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13006 0x30, /* 48 */ 13007 0, 13008 #endif 13009 }, 13010 { 13011 BCMI_QTC_XGXS_AN_X4_SW_SP0_AN_MISC_STSr, 13012 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13013 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 13014 BCMI_QTC_XGXS_AN_X4_SW_SP0_AN_MISC_STSr_fields, 13015 #else 13016 0, 13017 #endif 13018 #endif 13019 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13020 PHYMOD_SYMBOL_FLAG_REGISTER, 13021 "AN_X4_SW_SP0_AN_MISC_STSr", 13022 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13023 "AN_X4_SW_MANAGEMENT_SP0_AN_MISC_STATUS", 13024 NULL, 13025 #endif 13026 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13027 0x0, /* 0 */ 13028 0, 13029 #endif 13030 }, 13031 { 13032 BCMI_QTC_XGXS_AN_X4_SW_SP0_TLA_SEQUENCER_STSr, 13033 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13034 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 13035 BCMI_QTC_XGXS_AN_X4_SW_SP0_TLA_SEQUENCER_STSr_fields, 13036 #else 13037 0, 13038 #endif 13039 #endif 13040 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13041 PHYMOD_SYMBOL_FLAG_REGISTER, 13042 "AN_X4_SW_SP0_TLA_SEQUENCER_STSr", 13043 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13044 "AN_X4_SW_MANAGEMENT_SP0_TLA_SEQUENCER_STATUS", 13045 NULL, 13046 #endif 13047 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13048 0x1, /* 1 */ 13049 0, 13050 #endif 13051 }, 13052 { 13053 BCMI_QTC_XGXS_AN_X4_SW_SP0_AN_SEQ_UNEXPECTED_PAGEr, 13054 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13055 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 13056 BCMI_QTC_XGXS_AN_X4_SW_SP0_AN_SEQ_UNEXPECTED_PAGEr_fields, 13057 #else 13058 0, 13059 #endif 13060 #endif 13061 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13062 PHYMOD_SYMBOL_FLAG_REGISTER, 13063 "AN_X4_SW_SP0_AN_SEQ_UNEXPECTED_PAGEr", 13064 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13065 "AN_X4_SW_MANAGEMENT_SP0_AN_SEQ_UNEXPECTED_PAGE", 13066 NULL, 13067 #endif 13068 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13069 0x0, /* 0 */ 13070 0, 13071 #endif 13072 }, 13073 { 13074 BCMI_QTC_XGXS_AN_X4_SW_SP1_LD_PAGE2r, 13075 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13076 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 13077 BCMI_QTC_XGXS_AN_X4_SW_SP1_LD_PAGE2r_fields, 13078 #else 13079 0, 13080 #endif 13081 #endif 13082 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13083 PHYMOD_SYMBOL_FLAG_REGISTER, 13084 "AN_X4_SW_SP1_LD_PAGE2r", 13085 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13086 "AN_X4_SW_MANAGEMENT_SP1_LD_PAGE_2", 13087 NULL, 13088 #endif 13089 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13090 0x0, /* 0 */ 13091 0, 13092 #endif 13093 }, 13094 { 13095 BCMI_QTC_XGXS_AN_X4_SW_SP1_LD_PAGE1r, 13096 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13097 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 13098 BCMI_QTC_XGXS_AN_X4_SW_SP1_LD_PAGE1r_fields, 13099 #else 13100 0, 13101 #endif 13102 #endif 13103 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13104 PHYMOD_SYMBOL_FLAG_REGISTER, 13105 "AN_X4_SW_SP1_LD_PAGE1r", 13106 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13107 "AN_X4_SW_MANAGEMENT_SP1_LD_PAGE_1", 13108 NULL, 13109 #endif 13110 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13111 0x0, /* 0 */ 13112 0, 13113 #endif 13114 }, 13115 { 13116 BCMI_QTC_XGXS_AN_X4_SW_SP1_LD_PAGE0r, 13117 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13118 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 13119 BCMI_QTC_XGXS_AN_X4_SW_SP1_LD_PAGE0r_fields, 13120 #else 13121 0, 13122 #endif 13123 #endif 13124 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13125 PHYMOD_SYMBOL_FLAG_REGISTER, 13126 "AN_X4_SW_SP1_LD_PAGE0r", 13127 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13128 "AN_X4_SW_MANAGEMENT_SP1_LD_PAGE_0", 13129 NULL, 13130 #endif 13131 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13132 0x0, /* 0 */ 13133 0, 13134 #endif 13135 }, 13136 { 13137 BCMI_QTC_XGXS_AN_X4_SW_SP1_LP_PAGE2r, 13138 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13139 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 13140 BCMI_QTC_XGXS_AN_X4_SW_SP1_LP_PAGE2r_fields, 13141 #else 13142 0, 13143 #endif 13144 #endif 13145 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13146 PHYMOD_SYMBOL_FLAG_REGISTER, 13147 "AN_X4_SW_SP1_LP_PAGE2r", 13148 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13149 "AN_X4_SW_MANAGEMENT_SP1_LP_PAGE_2", 13150 NULL, 13151 #endif 13152 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13153 0x0, /* 0 */ 13154 0, 13155 #endif 13156 }, 13157 { 13158 BCMI_QTC_XGXS_AN_X4_SW_SP1_LP_PAGE1r, 13159 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13160 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 13161 BCMI_QTC_XGXS_AN_X4_SW_SP1_LP_PAGE1r_fields, 13162 #else 13163 0, 13164 #endif 13165 #endif 13166 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13167 PHYMOD_SYMBOL_FLAG_REGISTER, 13168 "AN_X4_SW_SP1_LP_PAGE1r", 13169 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13170 "AN_X4_SW_MANAGEMENT_SP1_LP_PAGE_1", 13171 NULL, 13172 #endif 13173 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13174 0x0, /* 0 */ 13175 0, 13176 #endif 13177 }, 13178 { 13179 BCMI_QTC_XGXS_AN_X4_SW_SP1_LP_PAGE0r, 13180 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13181 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 13182 BCMI_QTC_XGXS_AN_X4_SW_SP1_LP_PAGE0r_fields, 13183 #else 13184 0, 13185 #endif 13186 #endif 13187 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13188 PHYMOD_SYMBOL_FLAG_REGISTER, 13189 "AN_X4_SW_SP1_LP_PAGE0r", 13190 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13191 "AN_X4_SW_MANAGEMENT_SP1_LP_PAGE_0", 13192 NULL, 13193 #endif 13194 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13195 0x0, /* 0 */ 13196 0, 13197 #endif 13198 }, 13199 { 13200 BCMI_QTC_XGXS_AN_X4_SW_SP1_SW_CTL_STSr, 13201 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13202 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 13203 BCMI_QTC_XGXS_AN_X4_SW_SP1_SW_CTL_STSr_fields, 13204 #else 13205 0, 13206 #endif 13207 #endif 13208 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13209 PHYMOD_SYMBOL_FLAG_REGISTER, 13210 "AN_X4_SW_SP1_SW_CTL_STSr", 13211 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13212 "AN_X4_SW_MANAGEMENT_SP1_SW_CONTROL_STATUS", 13213 NULL, 13214 #endif 13215 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13216 0x0, /* 0 */ 13217 0, 13218 #endif 13219 }, 13220 { 13221 BCMI_QTC_XGXS_AN_X4_SW_SP1_LD_CTLr, 13222 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13223 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 13224 BCMI_QTC_XGXS_AN_X4_SW_SP1_LD_CTLr_fields, 13225 #else 13226 0, 13227 #endif 13228 #endif 13229 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13230 PHYMOD_SYMBOL_FLAG_REGISTER, 13231 "AN_X4_SW_SP1_LD_CTLr", 13232 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13233 "AN_X4_SW_MANAGEMENT_SP1_LD_CONTROL", 13234 NULL, 13235 #endif 13236 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13237 0x0, /* 0 */ 13238 0, 13239 #endif 13240 }, 13241 { 13242 BCMI_QTC_XGXS_AN_X4_SW_SP1_AN_PAGE_SEQUENCER_STSr, 13243 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13244 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 13245 BCMI_QTC_XGXS_AN_X4_SW_SP1_AN_PAGE_SEQUENCER_STSr_fields, 13246 #else 13247 0, 13248 #endif 13249 #endif 13250 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13251 PHYMOD_SYMBOL_FLAG_REGISTER, 13252 "AN_X4_SW_SP1_AN_PAGE_SEQUENCER_STSr", 13253 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13254 "AN_X4_SW_MANAGEMENT_SP1_AN_PAGE_SEQUENCER_STATUS", 13255 NULL, 13256 #endif 13257 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13258 0x0, /* 0 */ 13259 0, 13260 #endif 13261 }, 13262 { 13263 BCMI_QTC_XGXS_AN_X4_SW_SP1_AN_PAGE_EXCHANGEER_STSr, 13264 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13265 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 13266 BCMI_QTC_XGXS_AN_X4_SW_SP1_AN_PAGE_EXCHANGEER_STSr_fields, 13267 #else 13268 0, 13269 #endif 13270 #endif 13271 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13272 PHYMOD_SYMBOL_FLAG_REGISTER, 13273 "AN_X4_SW_SP1_AN_PAGE_EXCHANGEER_STSr", 13274 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13275 "AN_X4_SW_MANAGEMENT_SP1_AN_PAGE_EXCHANGEER_STATUS", 13276 NULL, 13277 #endif 13278 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13279 0x0, /* 0 */ 13280 0, 13281 #endif 13282 }, 13283 { 13284 BCMI_QTC_XGXS_AN_X4_SW_SP1_AN_PAGE_DECR_STSr, 13285 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13286 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 13287 BCMI_QTC_XGXS_AN_X4_SW_SP1_AN_PAGE_DECR_STSr_fields, 13288 #else 13289 0, 13290 #endif 13291 #endif 13292 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13293 PHYMOD_SYMBOL_FLAG_REGISTER, 13294 "AN_X4_SW_SP1_AN_PAGE_DECR_STSr", 13295 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13296 "AN_X4_SW_MANAGEMENT_SP1_AN_PAGE_DECODER_STATUS", 13297 NULL, 13298 #endif 13299 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13300 0x0, /* 0 */ 13301 0, 13302 #endif 13303 }, 13304 { 13305 BCMI_QTC_XGXS_AN_X4_SW_SP1_AN_ABIL_RESOLUTION_STSr, 13306 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13307 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 13308 BCMI_QTC_XGXS_AN_X4_SW_SP1_AN_ABIL_RESOLUTION_STSr_fields, 13309 #else 13310 0, 13311 #endif 13312 #endif 13313 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13314 PHYMOD_SYMBOL_FLAG_REGISTER, 13315 "AN_X4_SW_SP1_AN_ABIL_RESOLUTION_STSr", 13316 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13317 "AN_X4_SW_MANAGEMENT_SP1_AN_ABILITY_RESOLUTION_STATUS", 13318 NULL, 13319 #endif 13320 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13321 0x30, /* 48 */ 13322 0, 13323 #endif 13324 }, 13325 { 13326 BCMI_QTC_XGXS_AN_X4_SW_SP1_AN_MISC_STSr, 13327 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13328 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 13329 BCMI_QTC_XGXS_AN_X4_SW_SP1_AN_MISC_STSr_fields, 13330 #else 13331 0, 13332 #endif 13333 #endif 13334 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13335 PHYMOD_SYMBOL_FLAG_REGISTER, 13336 "AN_X4_SW_SP1_AN_MISC_STSr", 13337 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13338 "AN_X4_SW_MANAGEMENT_SP1_AN_MISC_STATUS", 13339 NULL, 13340 #endif 13341 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13342 0x0, /* 0 */ 13343 0, 13344 #endif 13345 }, 13346 { 13347 BCMI_QTC_XGXS_AN_X4_SW_SP1_TLA_SEQUENCER_STSr, 13348 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13349 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 13350 BCMI_QTC_XGXS_AN_X4_SW_SP1_TLA_SEQUENCER_STSr_fields, 13351 #else 13352 0, 13353 #endif 13354 #endif 13355 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13356 PHYMOD_SYMBOL_FLAG_REGISTER, 13357 "AN_X4_SW_SP1_TLA_SEQUENCER_STSr", 13358 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13359 "AN_X4_SW_MANAGEMENT_SP1_TLA_SEQUENCER_STATUS", 13360 NULL, 13361 #endif 13362 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13363 0x1, /* 1 */ 13364 0, 13365 #endif 13366 }, 13367 { 13368 BCMI_QTC_XGXS_AN_X4_SW_SP1_AN_SEQ_UNEXPECTED_PAGEr, 13369 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13370 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 13371 BCMI_QTC_XGXS_AN_X4_SW_SP1_AN_SEQ_UNEXPECTED_PAGEr_fields, 13372 #else 13373 0, 13374 #endif 13375 #endif 13376 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13377 PHYMOD_SYMBOL_FLAG_REGISTER, 13378 "AN_X4_SW_SP1_AN_SEQ_UNEXPECTED_PAGEr", 13379 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13380 "AN_X4_SW_MANAGEMENT_SP1_AN_SEQ_UNEXPECTED_PAGE", 13381 NULL, 13382 #endif 13383 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13384 0x0, /* 0 */ 13385 0, 13386 #endif 13387 }, 13388 { 13389 BCMI_QTC_XGXS_AN_X4_SW_SP2_LD_PAGE2r, 13390 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13391 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 13392 BCMI_QTC_XGXS_AN_X4_SW_SP2_LD_PAGE2r_fields, 13393 #else 13394 0, 13395 #endif 13396 #endif 13397 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13398 PHYMOD_SYMBOL_FLAG_REGISTER, 13399 "AN_X4_SW_SP2_LD_PAGE2r", 13400 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13401 "AN_X4_SW_MANAGEMENT_SP2_LD_PAGE_2", 13402 NULL, 13403 #endif 13404 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13405 0x0, /* 0 */ 13406 0, 13407 #endif 13408 }, 13409 { 13410 BCMI_QTC_XGXS_AN_X4_SW_SP2_LD_PAGE1r, 13411 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13412 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 13413 BCMI_QTC_XGXS_AN_X4_SW_SP2_LD_PAGE1r_fields, 13414 #else 13415 0, 13416 #endif 13417 #endif 13418 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13419 PHYMOD_SYMBOL_FLAG_REGISTER, 13420 "AN_X4_SW_SP2_LD_PAGE1r", 13421 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13422 "AN_X4_SW_MANAGEMENT_SP2_LD_PAGE_1", 13423 NULL, 13424 #endif 13425 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13426 0x0, /* 0 */ 13427 0, 13428 #endif 13429 }, 13430 { 13431 BCMI_QTC_XGXS_AN_X4_SW_SP2_LD_PAGE0r, 13432 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13433 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 13434 BCMI_QTC_XGXS_AN_X4_SW_SP2_LD_PAGE0r_fields, 13435 #else 13436 0, 13437 #endif 13438 #endif 13439 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13440 PHYMOD_SYMBOL_FLAG_REGISTER, 13441 "AN_X4_SW_SP2_LD_PAGE0r", 13442 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13443 "AN_X4_SW_MANAGEMENT_SP2_LD_PAGE_0", 13444 NULL, 13445 #endif 13446 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13447 0x0, /* 0 */ 13448 0, 13449 #endif 13450 }, 13451 { 13452 BCMI_QTC_XGXS_AN_X4_SW_SP2_LP_PAGE2r, 13453 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13454 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 13455 BCMI_QTC_XGXS_AN_X4_SW_SP2_LP_PAGE2r_fields, 13456 #else 13457 0, 13458 #endif 13459 #endif 13460 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13461 PHYMOD_SYMBOL_FLAG_REGISTER, 13462 "AN_X4_SW_SP2_LP_PAGE2r", 13463 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13464 "AN_X4_SW_MANAGEMENT_SP2_LP_PAGE_2", 13465 NULL, 13466 #endif 13467 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13468 0x0, /* 0 */ 13469 0, 13470 #endif 13471 }, 13472 { 13473 BCMI_QTC_XGXS_AN_X4_SW_SP2_LP_PAGE1r, 13474 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13475 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 13476 BCMI_QTC_XGXS_AN_X4_SW_SP2_LP_PAGE1r_fields, 13477 #else 13478 0, 13479 #endif 13480 #endif 13481 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13482 PHYMOD_SYMBOL_FLAG_REGISTER, 13483 "AN_X4_SW_SP2_LP_PAGE1r", 13484 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13485 "AN_X4_SW_MANAGEMENT_SP2_LP_PAGE_1", 13486 NULL, 13487 #endif 13488 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13489 0x0, /* 0 */ 13490 0, 13491 #endif 13492 }, 13493 { 13494 BCMI_QTC_XGXS_AN_X4_SW_SP2_LP_PAGE0r, 13495 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13496 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 13497 BCMI_QTC_XGXS_AN_X4_SW_SP2_LP_PAGE0r_fields, 13498 #else 13499 0, 13500 #endif 13501 #endif 13502 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13503 PHYMOD_SYMBOL_FLAG_REGISTER, 13504 "AN_X4_SW_SP2_LP_PAGE0r", 13505 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13506 "AN_X4_SW_MANAGEMENT_SP2_LP_PAGE_0", 13507 NULL, 13508 #endif 13509 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13510 0x0, /* 0 */ 13511 0, 13512 #endif 13513 }, 13514 { 13515 BCMI_QTC_XGXS_AN_X4_SW_SP2_SW_CTL_STSr, 13516 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13517 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 13518 BCMI_QTC_XGXS_AN_X4_SW_SP2_SW_CTL_STSr_fields, 13519 #else 13520 0, 13521 #endif 13522 #endif 13523 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13524 PHYMOD_SYMBOL_FLAG_REGISTER, 13525 "AN_X4_SW_SP2_SW_CTL_STSr", 13526 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13527 "AN_X4_SW_MANAGEMENT_SP2_SW_CONTROL_STATUS", 13528 NULL, 13529 #endif 13530 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13531 0x0, /* 0 */ 13532 0, 13533 #endif 13534 }, 13535 { 13536 BCMI_QTC_XGXS_AN_X4_SW_SP2_LD_CTLr, 13537 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13538 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 13539 BCMI_QTC_XGXS_AN_X4_SW_SP2_LD_CTLr_fields, 13540 #else 13541 0, 13542 #endif 13543 #endif 13544 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13545 PHYMOD_SYMBOL_FLAG_REGISTER, 13546 "AN_X4_SW_SP2_LD_CTLr", 13547 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13548 "AN_X4_SW_MANAGEMENT_SP2_LD_CONTROL", 13549 NULL, 13550 #endif 13551 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13552 0x0, /* 0 */ 13553 0, 13554 #endif 13555 }, 13556 { 13557 BCMI_QTC_XGXS_AN_X4_SW_SP2_AN_PAGE_SEQUENCER_STSr, 13558 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13559 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 13560 BCMI_QTC_XGXS_AN_X4_SW_SP2_AN_PAGE_SEQUENCER_STSr_fields, 13561 #else 13562 0, 13563 #endif 13564 #endif 13565 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13566 PHYMOD_SYMBOL_FLAG_REGISTER, 13567 "AN_X4_SW_SP2_AN_PAGE_SEQUENCER_STSr", 13568 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13569 "AN_X4_SW_MANAGEMENT_SP2_AN_PAGE_SEQUENCER_STATUS", 13570 NULL, 13571 #endif 13572 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13573 0x0, /* 0 */ 13574 0, 13575 #endif 13576 }, 13577 { 13578 BCMI_QTC_XGXS_AN_X4_SW_SP2_AN_PAGE_EXCHANGEER_STSr, 13579 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13580 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 13581 BCMI_QTC_XGXS_AN_X4_SW_SP2_AN_PAGE_EXCHANGEER_STSr_fields, 13582 #else 13583 0, 13584 #endif 13585 #endif 13586 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13587 PHYMOD_SYMBOL_FLAG_REGISTER, 13588 "AN_X4_SW_SP2_AN_PAGE_EXCHANGEER_STSr", 13589 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13590 "AN_X4_SW_MANAGEMENT_SP2_AN_PAGE_EXCHANGEER_STATUS", 13591 NULL, 13592 #endif 13593 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13594 0x0, /* 0 */ 13595 0, 13596 #endif 13597 }, 13598 { 13599 BCMI_QTC_XGXS_AN_X4_SW_SP2_AN_PAGE_DECR_STSr, 13600 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13601 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 13602 BCMI_QTC_XGXS_AN_X4_SW_SP2_AN_PAGE_DECR_STSr_fields, 13603 #else 13604 0, 13605 #endif 13606 #endif 13607 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13608 PHYMOD_SYMBOL_FLAG_REGISTER, 13609 "AN_X4_SW_SP2_AN_PAGE_DECR_STSr", 13610 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13611 "AN_X4_SW_MANAGEMENT_SP2_AN_PAGE_DECODER_STATUS", 13612 NULL, 13613 #endif 13614 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13615 0x0, /* 0 */ 13616 0, 13617 #endif 13618 }, 13619 { 13620 BCMI_QTC_XGXS_AN_X4_SW_SP2_AN_ABIL_RESOLUTION_STSr, 13621 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13622 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 13623 BCMI_QTC_XGXS_AN_X4_SW_SP2_AN_ABIL_RESOLUTION_STSr_fields, 13624 #else 13625 0, 13626 #endif 13627 #endif 13628 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13629 PHYMOD_SYMBOL_FLAG_REGISTER, 13630 "AN_X4_SW_SP2_AN_ABIL_RESOLUTION_STSr", 13631 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13632 "AN_X4_SW_MANAGEMENT_SP2_AN_ABILITY_RESOLUTION_STATUS", 13633 NULL, 13634 #endif 13635 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13636 0x30, /* 48 */ 13637 0, 13638 #endif 13639 }, 13640 { 13641 BCMI_QTC_XGXS_AN_X4_SW_SP2_AN_MISC_STSr, 13642 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13643 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 13644 BCMI_QTC_XGXS_AN_X4_SW_SP2_AN_MISC_STSr_fields, 13645 #else 13646 0, 13647 #endif 13648 #endif 13649 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13650 PHYMOD_SYMBOL_FLAG_REGISTER, 13651 "AN_X4_SW_SP2_AN_MISC_STSr", 13652 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13653 "AN_X4_SW_MANAGEMENT_SP2_AN_MISC_STATUS", 13654 NULL, 13655 #endif 13656 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13657 0x0, /* 0 */ 13658 0, 13659 #endif 13660 }, 13661 { 13662 BCMI_QTC_XGXS_AN_X4_SW_SP2_TLA_SEQUENCER_STSr, 13663 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13664 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 13665 BCMI_QTC_XGXS_AN_X4_SW_SP2_TLA_SEQUENCER_STSr_fields, 13666 #else 13667 0, 13668 #endif 13669 #endif 13670 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13671 PHYMOD_SYMBOL_FLAG_REGISTER, 13672 "AN_X4_SW_SP2_TLA_SEQUENCER_STSr", 13673 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13674 "AN_X4_SW_MANAGEMENT_SP2_TLA_SEQUENCER_STATUS", 13675 NULL, 13676 #endif 13677 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13678 0x1, /* 1 */ 13679 0, 13680 #endif 13681 }, 13682 { 13683 BCMI_QTC_XGXS_AN_X4_SW_SP2_AN_SEQ_UNEXPECTED_PAGEr, 13684 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13685 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 13686 BCMI_QTC_XGXS_AN_X4_SW_SP2_AN_SEQ_UNEXPECTED_PAGEr_fields, 13687 #else 13688 0, 13689 #endif 13690 #endif 13691 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13692 PHYMOD_SYMBOL_FLAG_REGISTER, 13693 "AN_X4_SW_SP2_AN_SEQ_UNEXPECTED_PAGEr", 13694 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13695 "AN_X4_SW_MANAGEMENT_SP2_AN_SEQ_UNEXPECTED_PAGE", 13696 NULL, 13697 #endif 13698 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13699 0x0, /* 0 */ 13700 0, 13701 #endif 13702 }, 13703 { 13704 BCMI_QTC_XGXS_AN_X4_SW_SP3_LD_PAGE2r, 13705 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13706 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 13707 BCMI_QTC_XGXS_AN_X4_SW_SP3_LD_PAGE2r_fields, 13708 #else 13709 0, 13710 #endif 13711 #endif 13712 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13713 PHYMOD_SYMBOL_FLAG_REGISTER, 13714 "AN_X4_SW_SP3_LD_PAGE2r", 13715 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13716 "AN_X4_SW_MANAGEMENT_SP3_LD_PAGE_2", 13717 NULL, 13718 #endif 13719 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13720 0x0, /* 0 */ 13721 0, 13722 #endif 13723 }, 13724 { 13725 BCMI_QTC_XGXS_AN_X4_SW_SP3_LD_PAGE1r, 13726 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13727 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 13728 BCMI_QTC_XGXS_AN_X4_SW_SP3_LD_PAGE1r_fields, 13729 #else 13730 0, 13731 #endif 13732 #endif 13733 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13734 PHYMOD_SYMBOL_FLAG_REGISTER, 13735 "AN_X4_SW_SP3_LD_PAGE1r", 13736 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13737 "AN_X4_SW_MANAGEMENT_SP3_LD_PAGE_1", 13738 NULL, 13739 #endif 13740 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13741 0x0, /* 0 */ 13742 0, 13743 #endif 13744 }, 13745 { 13746 BCMI_QTC_XGXS_AN_X4_SW_SP3_LD_PAGE0r, 13747 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13748 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 13749 BCMI_QTC_XGXS_AN_X4_SW_SP3_LD_PAGE0r_fields, 13750 #else 13751 0, 13752 #endif 13753 #endif 13754 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13755 PHYMOD_SYMBOL_FLAG_REGISTER, 13756 "AN_X4_SW_SP3_LD_PAGE0r", 13757 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13758 "AN_X4_SW_MANAGEMENT_SP3_LD_PAGE_0", 13759 NULL, 13760 #endif 13761 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13762 0x0, /* 0 */ 13763 0, 13764 #endif 13765 }, 13766 { 13767 BCMI_QTC_XGXS_AN_X4_SW_SP3_LP_PAGE2r, 13768 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13769 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 13770 BCMI_QTC_XGXS_AN_X4_SW_SP3_LP_PAGE2r_fields, 13771 #else 13772 0, 13773 #endif 13774 #endif 13775 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13776 PHYMOD_SYMBOL_FLAG_REGISTER, 13777 "AN_X4_SW_SP3_LP_PAGE2r", 13778 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13779 "AN_X4_SW_MANAGEMENT_SP3_LP_PAGE_2", 13780 NULL, 13781 #endif 13782 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13783 0x0, /* 0 */ 13784 0, 13785 #endif 13786 }, 13787 { 13788 BCMI_QTC_XGXS_AN_X4_SW_SP3_LP_PAGE1r, 13789 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13790 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 13791 BCMI_QTC_XGXS_AN_X4_SW_SP3_LP_PAGE1r_fields, 13792 #else 13793 0, 13794 #endif 13795 #endif 13796 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13797 PHYMOD_SYMBOL_FLAG_REGISTER, 13798 "AN_X4_SW_SP3_LP_PAGE1r", 13799 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13800 "AN_X4_SW_MANAGEMENT_SP3_LP_PAGE_1", 13801 NULL, 13802 #endif 13803 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13804 0x0, /* 0 */ 13805 0, 13806 #endif 13807 }, 13808 { 13809 BCMI_QTC_XGXS_AN_X4_SW_SP3_LP_PAGE0r, 13810 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13811 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 13812 BCMI_QTC_XGXS_AN_X4_SW_SP3_LP_PAGE0r_fields, 13813 #else 13814 0, 13815 #endif 13816 #endif 13817 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13818 PHYMOD_SYMBOL_FLAG_REGISTER, 13819 "AN_X4_SW_SP3_LP_PAGE0r", 13820 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13821 "AN_X4_SW_MANAGEMENT_SP3_LP_PAGE_0", 13822 NULL, 13823 #endif 13824 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13825 0x0, /* 0 */ 13826 0, 13827 #endif 13828 }, 13829 { 13830 BCMI_QTC_XGXS_AN_X4_SW_SP3_SW_CTL_STSr, 13831 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13832 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 13833 BCMI_QTC_XGXS_AN_X4_SW_SP3_SW_CTL_STSr_fields, 13834 #else 13835 0, 13836 #endif 13837 #endif 13838 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13839 PHYMOD_SYMBOL_FLAG_REGISTER, 13840 "AN_X4_SW_SP3_SW_CTL_STSr", 13841 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13842 "AN_X4_SW_MANAGEMENT_SP3_SW_CONTROL_STATUS", 13843 NULL, 13844 #endif 13845 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13846 0x0, /* 0 */ 13847 0, 13848 #endif 13849 }, 13850 { 13851 BCMI_QTC_XGXS_AN_X4_SW_SP3_LD_CTLr, 13852 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13853 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 13854 BCMI_QTC_XGXS_AN_X4_SW_SP3_LD_CTLr_fields, 13855 #else 13856 0, 13857 #endif 13858 #endif 13859 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13860 PHYMOD_SYMBOL_FLAG_REGISTER, 13861 "AN_X4_SW_SP3_LD_CTLr", 13862 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13863 "AN_X4_SW_MANAGEMENT_SP3_LD_CONTROL", 13864 NULL, 13865 #endif 13866 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13867 0x0, /* 0 */ 13868 0, 13869 #endif 13870 }, 13871 { 13872 BCMI_QTC_XGXS_AN_X4_SW_SP3_AN_PAGE_SEQUENCER_STSr, 13873 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13874 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 13875 BCMI_QTC_XGXS_AN_X4_SW_SP3_AN_PAGE_SEQUENCER_STSr_fields, 13876 #else 13877 0, 13878 #endif 13879 #endif 13880 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13881 PHYMOD_SYMBOL_FLAG_REGISTER, 13882 "AN_X4_SW_SP3_AN_PAGE_SEQUENCER_STSr", 13883 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13884 "AN_X4_SW_MANAGEMENT_SP3_AN_PAGE_SEQUENCER_STATUS", 13885 NULL, 13886 #endif 13887 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13888 0x0, /* 0 */ 13889 0, 13890 #endif 13891 }, 13892 { 13893 BCMI_QTC_XGXS_AN_X4_SW_SP3_AN_PAGE_EXCHANGEER_STSr, 13894 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13895 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 13896 BCMI_QTC_XGXS_AN_X4_SW_SP3_AN_PAGE_EXCHANGEER_STSr_fields, 13897 #else 13898 0, 13899 #endif 13900 #endif 13901 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13902 PHYMOD_SYMBOL_FLAG_REGISTER, 13903 "AN_X4_SW_SP3_AN_PAGE_EXCHANGEER_STSr", 13904 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13905 "AN_X4_SW_MANAGEMENT_SP3_AN_PAGE_EXCHANGEER_STATUS", 13906 NULL, 13907 #endif 13908 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13909 0x0, /* 0 */ 13910 0, 13911 #endif 13912 }, 13913 { 13914 BCMI_QTC_XGXS_AN_X4_SW_SP3_AN_PAGE_DECR_STSr, 13915 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13916 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 13917 BCMI_QTC_XGXS_AN_X4_SW_SP3_AN_PAGE_DECR_STSr_fields, 13918 #else 13919 0, 13920 #endif 13921 #endif 13922 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13923 PHYMOD_SYMBOL_FLAG_REGISTER, 13924 "AN_X4_SW_SP3_AN_PAGE_DECR_STSr", 13925 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13926 "AN_X4_SW_MANAGEMENT_SP3_AN_PAGE_DECODER_STATUS", 13927 NULL, 13928 #endif 13929 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13930 0x0, /* 0 */ 13931 0, 13932 #endif 13933 }, 13934 { 13935 BCMI_QTC_XGXS_AN_X4_SW_SP3_AN_ABIL_RESOLUTION_STSr, 13936 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13937 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 13938 BCMI_QTC_XGXS_AN_X4_SW_SP3_AN_ABIL_RESOLUTION_STSr_fields, 13939 #else 13940 0, 13941 #endif 13942 #endif 13943 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13944 PHYMOD_SYMBOL_FLAG_REGISTER, 13945 "AN_X4_SW_SP3_AN_ABIL_RESOLUTION_STSr", 13946 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13947 "AN_X4_SW_MANAGEMENT_SP3_AN_ABILITY_RESOLUTION_STATUS", 13948 NULL, 13949 #endif 13950 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13951 0x30, /* 48 */ 13952 0, 13953 #endif 13954 }, 13955 { 13956 BCMI_QTC_XGXS_AN_X4_SW_SP3_AN_MISC_STSr, 13957 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13958 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 13959 BCMI_QTC_XGXS_AN_X4_SW_SP3_AN_MISC_STSr_fields, 13960 #else 13961 0, 13962 #endif 13963 #endif 13964 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13965 PHYMOD_SYMBOL_FLAG_REGISTER, 13966 "AN_X4_SW_SP3_AN_MISC_STSr", 13967 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13968 "AN_X4_SW_MANAGEMENT_SP3_AN_MISC_STATUS", 13969 NULL, 13970 #endif 13971 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13972 0x0, /* 0 */ 13973 0, 13974 #endif 13975 }, 13976 { 13977 BCMI_QTC_XGXS_AN_X4_SW_SP3_TLA_SEQUENCER_STSr, 13978 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 13979 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 13980 BCMI_QTC_XGXS_AN_X4_SW_SP3_TLA_SEQUENCER_STSr_fields, 13981 #else 13982 0, 13983 #endif 13984 #endif 13985 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 13986 PHYMOD_SYMBOL_FLAG_REGISTER, 13987 "AN_X4_SW_SP3_TLA_SEQUENCER_STSr", 13988 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 13989 "AN_X4_SW_MANAGEMENT_SP3_TLA_SEQUENCER_STATUS", 13990 NULL, 13991 #endif 13992 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 13993 0x1, /* 1 */ 13994 0, 13995 #endif 13996 }, 13997 { 13998 BCMI_QTC_XGXS_AN_X4_SW_SP3_AN_SEQ_UNEXPECTED_PAGEr, 13999 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14000 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 14001 BCMI_QTC_XGXS_AN_X4_SW_SP3_AN_SEQ_UNEXPECTED_PAGEr_fields, 14002 #else 14003 0, 14004 #endif 14005 #endif 14006 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14007 PHYMOD_SYMBOL_FLAG_REGISTER, 14008 "AN_X4_SW_SP3_AN_SEQ_UNEXPECTED_PAGEr", 14009 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14010 "AN_X4_SW_MANAGEMENT_SP3_AN_SEQ_UNEXPECTED_PAGE", 14011 NULL, 14012 #endif 14013 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14014 0x0, /* 0 */ 14015 0, 14016 #endif 14017 }, 14018 { 14019 BCMI_QTC_XGXS_PKT_CTRS_X4_SP0_TXPKTCNT_Ur, 14020 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14021 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 14022 BCMI_QTC_XGXS_PKT_CTRS_X4_SP0_TXPKTCNT_Ur_fields, 14023 #else 14024 0, 14025 #endif 14026 #endif 14027 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14028 PHYMOD_SYMBOL_FLAG_REGISTER, 14029 "PKT_CTRS_X4_SP0_TXPKTCNT_Ur", 14030 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14031 "PACKET_COUNTERS_X4_SP0_TXPKTCNT_U", 14032 NULL, 14033 #endif 14034 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14035 0x0, /* 0 */ 14036 0, 14037 #endif 14038 }, 14039 { 14040 BCMI_QTC_XGXS_PKT_CTRS_X4_SP0_TXPKTCNT_Lr, 14041 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14042 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 14043 BCMI_QTC_XGXS_PKT_CTRS_X4_SP0_TXPKTCNT_Lr_fields, 14044 #else 14045 0, 14046 #endif 14047 #endif 14048 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14049 PHYMOD_SYMBOL_FLAG_REGISTER, 14050 "PKT_CTRS_X4_SP0_TXPKTCNT_Lr", 14051 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14052 "PACKET_COUNTERS_X4_SP0_TXPKTCNT_L", 14053 NULL, 14054 #endif 14055 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14056 0x0, /* 0 */ 14057 0, 14058 #endif 14059 }, 14060 { 14061 BCMI_QTC_XGXS_PKT_CTRS_X4_SP0_RXPKTCNT_Ur, 14062 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14063 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 14064 BCMI_QTC_XGXS_PKT_CTRS_X4_SP0_RXPKTCNT_Ur_fields, 14065 #else 14066 0, 14067 #endif 14068 #endif 14069 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14070 PHYMOD_SYMBOL_FLAG_REGISTER, 14071 "PKT_CTRS_X4_SP0_RXPKTCNT_Ur", 14072 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14073 "PACKET_COUNTERS_X4_SP0_RXPKTCNT_U", 14074 NULL, 14075 #endif 14076 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14077 0x0, /* 0 */ 14078 0, 14079 #endif 14080 }, 14081 { 14082 BCMI_QTC_XGXS_PKT_CTRS_X4_SP0_RXPKTCNT_Lr, 14083 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14084 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 14085 BCMI_QTC_XGXS_PKT_CTRS_X4_SP0_RXPKTCNT_Lr_fields, 14086 #else 14087 0, 14088 #endif 14089 #endif 14090 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14091 PHYMOD_SYMBOL_FLAG_REGISTER, 14092 "PKT_CTRS_X4_SP0_RXPKTCNT_Lr", 14093 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14094 "PACKET_COUNTERS_X4_SP0_RXPKTCNT_L", 14095 NULL, 14096 #endif 14097 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14098 0x0, /* 0 */ 14099 0, 14100 #endif 14101 }, 14102 { 14103 BCMI_QTC_XGXS_PKT_CTRS_X4_SP1_TXPKTCNT_Ur, 14104 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14105 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 14106 BCMI_QTC_XGXS_PKT_CTRS_X4_SP1_TXPKTCNT_Ur_fields, 14107 #else 14108 0, 14109 #endif 14110 #endif 14111 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14112 PHYMOD_SYMBOL_FLAG_REGISTER, 14113 "PKT_CTRS_X4_SP1_TXPKTCNT_Ur", 14114 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14115 "PACKET_COUNTERS_X4_SP1_TXPKTCNT_U", 14116 NULL, 14117 #endif 14118 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14119 0x0, /* 0 */ 14120 0, 14121 #endif 14122 }, 14123 { 14124 BCMI_QTC_XGXS_PKT_CTRS_X4_SP1_TXPKTCNT_Lr, 14125 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14126 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 14127 BCMI_QTC_XGXS_PKT_CTRS_X4_SP1_TXPKTCNT_Lr_fields, 14128 #else 14129 0, 14130 #endif 14131 #endif 14132 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14133 PHYMOD_SYMBOL_FLAG_REGISTER, 14134 "PKT_CTRS_X4_SP1_TXPKTCNT_Lr", 14135 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14136 "PACKET_COUNTERS_X4_SP1_TXPKTCNT_L", 14137 NULL, 14138 #endif 14139 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14140 0x0, /* 0 */ 14141 0, 14142 #endif 14143 }, 14144 { 14145 BCMI_QTC_XGXS_PKT_CTRS_X4_SP1_RXPKTCNT_Ur, 14146 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14147 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 14148 BCMI_QTC_XGXS_PKT_CTRS_X4_SP1_RXPKTCNT_Ur_fields, 14149 #else 14150 0, 14151 #endif 14152 #endif 14153 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14154 PHYMOD_SYMBOL_FLAG_REGISTER, 14155 "PKT_CTRS_X4_SP1_RXPKTCNT_Ur", 14156 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14157 "PACKET_COUNTERS_X4_SP1_RXPKTCNT_U", 14158 NULL, 14159 #endif 14160 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14161 0x0, /* 0 */ 14162 0, 14163 #endif 14164 }, 14165 { 14166 BCMI_QTC_XGXS_PKT_CTRS_X4_SP1_RXPKTCNT_Lr, 14167 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14168 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 14169 BCMI_QTC_XGXS_PKT_CTRS_X4_SP1_RXPKTCNT_Lr_fields, 14170 #else 14171 0, 14172 #endif 14173 #endif 14174 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14175 PHYMOD_SYMBOL_FLAG_REGISTER, 14176 "PKT_CTRS_X4_SP1_RXPKTCNT_Lr", 14177 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14178 "PACKET_COUNTERS_X4_SP1_RXPKTCNT_L", 14179 NULL, 14180 #endif 14181 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14182 0x0, /* 0 */ 14183 0, 14184 #endif 14185 }, 14186 { 14187 BCMI_QTC_XGXS_PKT_CTRS_X4_SP2_TXPKTCNT_Ur, 14188 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14189 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 14190 BCMI_QTC_XGXS_PKT_CTRS_X4_SP2_TXPKTCNT_Ur_fields, 14191 #else 14192 0, 14193 #endif 14194 #endif 14195 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14196 PHYMOD_SYMBOL_FLAG_REGISTER, 14197 "PKT_CTRS_X4_SP2_TXPKTCNT_Ur", 14198 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14199 "PACKET_COUNTERS_X4_SP2_TXPKTCNT_U", 14200 NULL, 14201 #endif 14202 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14203 0x0, /* 0 */ 14204 0, 14205 #endif 14206 }, 14207 { 14208 BCMI_QTC_XGXS_PKT_CTRS_X4_SP2_TXPKTCNT_Lr, 14209 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14210 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 14211 BCMI_QTC_XGXS_PKT_CTRS_X4_SP2_TXPKTCNT_Lr_fields, 14212 #else 14213 0, 14214 #endif 14215 #endif 14216 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14217 PHYMOD_SYMBOL_FLAG_REGISTER, 14218 "PKT_CTRS_X4_SP2_TXPKTCNT_Lr", 14219 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14220 "PACKET_COUNTERS_X4_SP2_TXPKTCNT_L", 14221 NULL, 14222 #endif 14223 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14224 0x0, /* 0 */ 14225 0, 14226 #endif 14227 }, 14228 { 14229 BCMI_QTC_XGXS_PKT_CTRS_X4_SP2_RXPKTCNT_Ur, 14230 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14231 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 14232 BCMI_QTC_XGXS_PKT_CTRS_X4_SP2_RXPKTCNT_Ur_fields, 14233 #else 14234 0, 14235 #endif 14236 #endif 14237 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14238 PHYMOD_SYMBOL_FLAG_REGISTER, 14239 "PKT_CTRS_X4_SP2_RXPKTCNT_Ur", 14240 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14241 "PACKET_COUNTERS_X4_SP2_RXPKTCNT_U", 14242 NULL, 14243 #endif 14244 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14245 0x0, /* 0 */ 14246 0, 14247 #endif 14248 }, 14249 { 14250 BCMI_QTC_XGXS_PKT_CTRS_X4_SP2_RXPKTCNT_Lr, 14251 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14252 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 14253 BCMI_QTC_XGXS_PKT_CTRS_X4_SP2_RXPKTCNT_Lr_fields, 14254 #else 14255 0, 14256 #endif 14257 #endif 14258 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14259 PHYMOD_SYMBOL_FLAG_REGISTER, 14260 "PKT_CTRS_X4_SP2_RXPKTCNT_Lr", 14261 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14262 "PACKET_COUNTERS_X4_SP2_RXPKTCNT_L", 14263 NULL, 14264 #endif 14265 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14266 0x0, /* 0 */ 14267 0, 14268 #endif 14269 }, 14270 { 14271 BCMI_QTC_XGXS_PKT_CTRS_X4_SP3_TXPKTCNT_Ur, 14272 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14273 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 14274 BCMI_QTC_XGXS_PKT_CTRS_X4_SP3_TXPKTCNT_Ur_fields, 14275 #else 14276 0, 14277 #endif 14278 #endif 14279 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14280 PHYMOD_SYMBOL_FLAG_REGISTER, 14281 "PKT_CTRS_X4_SP3_TXPKTCNT_Ur", 14282 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14283 "PACKET_COUNTERS_X4_SP3_TXPKTCNT_U", 14284 NULL, 14285 #endif 14286 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14287 0x0, /* 0 */ 14288 0, 14289 #endif 14290 }, 14291 { 14292 BCMI_QTC_XGXS_PKT_CTRS_X4_SP3_TXPKTCNT_Lr, 14293 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14294 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 14295 BCMI_QTC_XGXS_PKT_CTRS_X4_SP3_TXPKTCNT_Lr_fields, 14296 #else 14297 0, 14298 #endif 14299 #endif 14300 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14301 PHYMOD_SYMBOL_FLAG_REGISTER, 14302 "PKT_CTRS_X4_SP3_TXPKTCNT_Lr", 14303 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14304 "PACKET_COUNTERS_X4_SP3_TXPKTCNT_L", 14305 NULL, 14306 #endif 14307 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14308 0x0, /* 0 */ 14309 0, 14310 #endif 14311 }, 14312 { 14313 BCMI_QTC_XGXS_PKT_CTRS_X4_SP3_RXPKTCNT_Ur, 14314 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14315 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 14316 BCMI_QTC_XGXS_PKT_CTRS_X4_SP3_RXPKTCNT_Ur_fields, 14317 #else 14318 0, 14319 #endif 14320 #endif 14321 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14322 PHYMOD_SYMBOL_FLAG_REGISTER, 14323 "PKT_CTRS_X4_SP3_RXPKTCNT_Ur", 14324 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14325 "PACKET_COUNTERS_X4_SP3_RXPKTCNT_U", 14326 NULL, 14327 #endif 14328 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14329 0x0, /* 0 */ 14330 0, 14331 #endif 14332 }, 14333 { 14334 BCMI_QTC_XGXS_PKT_CTRS_X4_SP3_RXPKTCNT_Lr, 14335 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14336 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 14337 BCMI_QTC_XGXS_PKT_CTRS_X4_SP3_RXPKTCNT_Lr_fields, 14338 #else 14339 0, 14340 #endif 14341 #endif 14342 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14343 PHYMOD_SYMBOL_FLAG_REGISTER, 14344 "PKT_CTRS_X4_SP3_RXPKTCNT_Lr", 14345 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14346 "PACKET_COUNTERS_X4_SP3_RXPKTCNT_L", 14347 NULL, 14348 #endif 14349 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14350 0x0, /* 0 */ 14351 0, 14352 #endif 14353 }, 14354 { 14355 BCMI_QTC_XGXS_SPARE0r, 14356 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14357 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 14358 BCMI_QTC_XGXS_SPARE0r_fields, 14359 #else 14360 0, 14361 #endif 14362 #endif 14363 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14364 PHYMOD_SYMBOL_FLAG_REGISTER, 14365 "SPARE0r", 14366 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14367 "SPARE_SPARE0", 14368 NULL, 14369 #endif 14370 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14371 0x0, /* 0 */ 14372 0, 14373 #endif 14374 }, 14375 { 14376 BCMI_QTC_XGXS_SPARE1r, 14377 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14378 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 14379 BCMI_QTC_XGXS_SPARE1r_fields, 14380 #else 14381 0, 14382 #endif 14383 #endif 14384 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14385 PHYMOD_SYMBOL_FLAG_REGISTER, 14386 "SPARE1r", 14387 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14388 "SPARE_SPARE1", 14389 NULL, 14390 #endif 14391 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14392 0x0, /* 0 */ 14393 0, 14394 #endif 14395 }, 14396 { 14397 BCMI_QTC_XGXS_ACC_CTLr, 14398 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14399 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 14400 BCMI_QTC_XGXS_ACC_CTLr_fields, 14401 #else 14402 0, 14403 #endif 14404 #endif 14405 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14406 PHYMOD_SYMBOL_FLAG_REGISTER, 14407 "ACC_CTLr", 14408 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14409 "MDIO_CL22_IEEE_ACC_CTRL", 14410 NULL, 14411 #endif 14412 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14413 0x0, /* 0 */ 14414 0, 14415 #endif 14416 }, 14417 { 14418 BCMI_QTC_XGXS_ACC_ADDR_DATAr, 14419 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14420 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 14421 BCMI_QTC_XGXS_ACC_ADDR_DATAr_fields, 14422 #else 14423 0, 14424 #endif 14425 #endif 14426 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14427 PHYMOD_SYMBOL_FLAG_REGISTER, 14428 "ACC_ADDR_DATAr", 14429 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14430 "MDIO_CL22_IEEE_ACC_ADDR_DATA", 14431 NULL, 14432 #endif 14433 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14434 0x0, /* 0 */ 14435 0, 14436 #endif 14437 }, 14438 { 14439 BCMI_QTC_XGXS_CL72_TXCL72IT_BASE_R_PMD_CTLr, 14440 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14441 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 14442 BCMI_QTC_XGXS_CL72_TXCL72IT_BASE_R_PMD_CTLr_fields, 14443 #else 14444 0, 14445 #endif 14446 #endif 14447 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14448 PHYMOD_SYMBOL_FLAG_REGISTER, 14449 "CL72_TXCL72IT_BASE_R_PMD_CTLr", 14450 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14451 "CL72_IEEE_TX_CL72IT_BASE_R_PMD_CONTROL_REGISTER_150", 14452 NULL, 14453 #endif 14454 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14455 0x0, /* 0 */ 14456 0, 14457 #endif 14458 }, 14459 { 14460 BCMI_QTC_XGXS_CL72_TXCL72IT_BASE_R_PMD_STSr, 14461 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14462 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 14463 BCMI_QTC_XGXS_CL72_TXCL72IT_BASE_R_PMD_STSr_fields, 14464 #else 14465 0, 14466 #endif 14467 #endif 14468 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14469 PHYMOD_SYMBOL_FLAG_REGISTER, 14470 "CL72_TXCL72IT_BASE_R_PMD_STSr", 14471 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14472 "CL72_IEEE_TX_CL72IT_BASE_R_PMD_STATUS_REGISTER_151", 14473 NULL, 14474 #endif 14475 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14476 0x0, /* 0 */ 14477 0, 14478 #endif 14479 }, 14480 { 14481 BCMI_QTC_XGXS_CL72_RXCL72IR_BASE_R_LP_COEFF_UPDr, 14482 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14483 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 14484 BCMI_QTC_XGXS_CL72_RXCL72IR_BASE_R_LP_COEFF_UPDr_fields, 14485 #else 14486 0, 14487 #endif 14488 #endif 14489 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14490 PHYMOD_SYMBOL_FLAG_REGISTER, 14491 "CL72_RXCL72IR_BASE_R_LP_COEFF_UPDr", 14492 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14493 "CL72_IEEE_RX_CL72IR_BASE_R_LP_COEFF_UPDATE_REGISTER_152", 14494 NULL, 14495 #endif 14496 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14497 0x0, /* 0 */ 14498 0, 14499 #endif 14500 }, 14501 { 14502 BCMI_QTC_XGXS_CL72_RXCL72IR_BASE_R_LP_STS_REPr, 14503 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14504 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 14505 BCMI_QTC_XGXS_CL72_RXCL72IR_BASE_R_LP_STS_REPr_fields, 14506 #else 14507 0, 14508 #endif 14509 #endif 14510 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14511 PHYMOD_SYMBOL_FLAG_REGISTER, 14512 "CL72_RXCL72IR_BASE_R_LP_STS_REPr", 14513 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14514 "CL72_IEEE_RX_CL72IR_BASE_R_LP_STATUS_REPORT_REGISTER_153", 14515 NULL, 14516 #endif 14517 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14518 0x0, /* 0 */ 14519 0, 14520 #endif 14521 }, 14522 { 14523 BCMI_QTC_XGXS_CL72_TXCL72IT_BASE_R_LD_COEFF_UPDr, 14524 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14525 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 14526 BCMI_QTC_XGXS_CL72_TXCL72IT_BASE_R_LD_COEFF_UPDr_fields, 14527 #else 14528 0, 14529 #endif 14530 #endif 14531 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14532 PHYMOD_SYMBOL_FLAG_REGISTER, 14533 "CL72_TXCL72IT_BASE_R_LD_COEFF_UPDr", 14534 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14535 "CL72_IEEE_TX_CL72IT_BASE_R_LD_COEFF_UPDATE_REGISTER_154", 14536 NULL, 14537 #endif 14538 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14539 0x0, /* 0 */ 14540 0, 14541 #endif 14542 }, 14543 { 14544 BCMI_QTC_XGXS_CL72_TXCL72IT_BASE_R_LD_STS_REPr, 14545 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14546 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 14547 BCMI_QTC_XGXS_CL72_TXCL72IT_BASE_R_LD_STS_REPr_fields, 14548 #else 14549 0, 14550 #endif 14551 #endif 14552 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14553 PHYMOD_SYMBOL_FLAG_REGISTER, 14554 "CL72_TXCL72IT_BASE_R_LD_STS_REPr", 14555 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14556 "CL72_IEEE_TX_CL72IT_BASE_R_LD_STATUS_REPORT_REGISTER_155", 14557 NULL, 14558 #endif 14559 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14560 0x0, /* 0 */ 14561 0, 14562 #endif 14563 }, 14564 { 14565 BCMI_QTC_XGXS_DSC_CDR_CTL0r, 14566 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14567 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 14568 BCMI_QTC_XGXS_DSC_CDR_CTL0r_fields, 14569 #else 14570 0, 14571 #endif 14572 #endif 14573 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14574 PHYMOD_SYMBOL_FLAG_REGISTER, 14575 "DSC_CDR_CTL0r", 14576 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14577 "DSC_A_CDR_CONTROL_0", 14578 NULL, 14579 #endif 14580 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14581 0x4, /* 4 */ 14582 0, 14583 #endif 14584 }, 14585 { 14586 BCMI_QTC_XGXS_DSC_CDR_CTL1r, 14587 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14588 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 14589 BCMI_QTC_XGXS_DSC_CDR_CTL1r_fields, 14590 #else 14591 0, 14592 #endif 14593 #endif 14594 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14595 PHYMOD_SYMBOL_FLAG_REGISTER, 14596 "DSC_CDR_CTL1r", 14597 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14598 "DSC_A_CDR_CONTROL_1", 14599 NULL, 14600 #endif 14601 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14602 0x690, /* 1680 */ 14603 0, 14604 #endif 14605 }, 14606 { 14607 BCMI_QTC_XGXS_DSC_CDR_CTL2r, 14608 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14609 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 14610 BCMI_QTC_XGXS_DSC_CDR_CTL2r_fields, 14611 #else 14612 0, 14613 #endif 14614 #endif 14615 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14616 PHYMOD_SYMBOL_FLAG_REGISTER, 14617 "DSC_CDR_CTL2r", 14618 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14619 "DSC_A_CDR_CONTROL_2", 14620 NULL, 14621 #endif 14622 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14623 0xf0, /* 240 */ 14624 0, 14625 #endif 14626 }, 14627 { 14628 BCMI_QTC_XGXS_DSC_RX_PI_CTLr, 14629 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14630 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 14631 BCMI_QTC_XGXS_DSC_RX_PI_CTLr_fields, 14632 #else 14633 0, 14634 #endif 14635 #endif 14636 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14637 PHYMOD_SYMBOL_FLAG_REGISTER, 14638 "DSC_RX_PI_CTLr", 14639 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14640 "DSC_A_RX_PI_CONTROL", 14641 NULL, 14642 #endif 14643 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14644 0x0, /* 0 */ 14645 0, 14646 #endif 14647 }, 14648 { 14649 BCMI_QTC_XGXS_DSC_CDR_STS_INTEGr, 14650 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14651 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 14652 BCMI_QTC_XGXS_DSC_CDR_STS_INTEGr_fields, 14653 #else 14654 0, 14655 #endif 14656 #endif 14657 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14658 PHYMOD_SYMBOL_FLAG_REGISTER, 14659 "DSC_CDR_STS_INTEGr", 14660 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14661 "DSC_A_CDR_STATUS_INTEG_REG", 14662 NULL, 14663 #endif 14664 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14665 0x0, /* 0 */ 14666 0, 14667 #endif 14668 }, 14669 { 14670 BCMI_QTC_XGXS_DSC_CDR_STS_PHASE_ERRr, 14671 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14672 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 14673 BCMI_QTC_XGXS_DSC_CDR_STS_PHASE_ERRr_fields, 14674 #else 14675 0, 14676 #endif 14677 #endif 14678 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14679 PHYMOD_SYMBOL_FLAG_REGISTER, 14680 "DSC_CDR_STS_PHASE_ERRr", 14681 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14682 "DSC_A_CDR_STATUS_PHASE_ERROR", 14683 NULL, 14684 #endif 14685 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14686 0x0, /* 0 */ 14687 0, 14688 #endif 14689 }, 14690 { 14691 BCMI_QTC_XGXS_DSC_RX_PI_CNT_BIN_Dr, 14692 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14693 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 14694 BCMI_QTC_XGXS_DSC_RX_PI_CNT_BIN_Dr_fields, 14695 #else 14696 0, 14697 #endif 14698 #endif 14699 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14700 PHYMOD_SYMBOL_FLAG_REGISTER, 14701 "DSC_RX_PI_CNT_BIN_Dr", 14702 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14703 "DSC_A_RX_PI_CNT_BIN_D", 14704 NULL, 14705 #endif 14706 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14707 0x0, /* 0 */ 14708 0, 14709 #endif 14710 }, 14711 { 14712 BCMI_QTC_XGXS_DSC_RX_PI_CNT_BIN_Pr, 14713 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14714 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 14715 BCMI_QTC_XGXS_DSC_RX_PI_CNT_BIN_Pr_fields, 14716 #else 14717 0, 14718 #endif 14719 #endif 14720 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14721 PHYMOD_SYMBOL_FLAG_REGISTER, 14722 "DSC_RX_PI_CNT_BIN_Pr", 14723 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14724 "DSC_A_RX_PI_CNT_BIN_P", 14725 NULL, 14726 #endif 14727 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14728 0x2000, /* 8192 */ 14729 0, 14730 #endif 14731 }, 14732 { 14733 BCMI_QTC_XGXS_DSC_RX_PI_CNT_BIN_Mr, 14734 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14735 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 14736 BCMI_QTC_XGXS_DSC_RX_PI_CNT_BIN_Mr_fields, 14737 #else 14738 0, 14739 #endif 14740 #endif 14741 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14742 PHYMOD_SYMBOL_FLAG_REGISTER, 14743 "DSC_RX_PI_CNT_BIN_Mr", 14744 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14745 "DSC_A_RX_PI_CNT_BIN_M", 14746 NULL, 14747 #endif 14748 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14749 0x20, /* 32 */ 14750 0, 14751 #endif 14752 }, 14753 { 14754 BCMI_QTC_XGXS_DSC_RX_PI_DIFF_BINr, 14755 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14756 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 14757 BCMI_QTC_XGXS_DSC_RX_PI_DIFF_BINr_fields, 14758 #else 14759 0, 14760 #endif 14761 #endif 14762 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14763 PHYMOD_SYMBOL_FLAG_REGISTER, 14764 "DSC_RX_PI_DIFF_BINr", 14765 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14766 "DSC_A_RX_PI_DIFF_BIN", 14767 NULL, 14768 #endif 14769 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14770 0x0, /* 0 */ 14771 0, 14772 #endif 14773 }, 14774 { 14775 BCMI_QTC_XGXS_DSC_TRNSUM_CTL5r, 14776 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14777 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 14778 BCMI_QTC_XGXS_DSC_TRNSUM_CTL5r_fields, 14779 #else 14780 0, 14781 #endif 14782 #endif 14783 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14784 PHYMOD_SYMBOL_FLAG_REGISTER, 14785 "DSC_TRNSUM_CTL5r", 14786 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14787 "DSC_A_TRNSUM_CNTL_5", 14788 NULL, 14789 #endif 14790 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14791 0x60, /* 96 */ 14792 0, 14793 #endif 14794 }, 14795 { 14796 BCMI_QTC_XGXS_DSC_UC_CTLr, 14797 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14798 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 14799 BCMI_QTC_XGXS_DSC_UC_CTLr_fields, 14800 #else 14801 0, 14802 #endif 14803 #endif 14804 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14805 PHYMOD_SYMBOL_FLAG_REGISTER, 14806 "DSC_UC_CTLr", 14807 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14808 "DSC_A_DSC_UC_CTRL", 14809 NULL, 14810 #endif 14811 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14812 0x0, /* 0 */ 14813 0, 14814 #endif 14815 }, 14816 { 14817 BCMI_QTC_XGXS_DSC_SCRATCHr, 14818 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14819 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 14820 BCMI_QTC_XGXS_DSC_SCRATCHr_fields, 14821 #else 14822 0, 14823 #endif 14824 #endif 14825 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14826 PHYMOD_SYMBOL_FLAG_REGISTER, 14827 "DSC_SCRATCHr", 14828 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14829 "DSC_A_DSC_SCRATCH", 14830 NULL, 14831 #endif 14832 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14833 0x0, /* 0 */ 14834 0, 14835 #endif 14836 }, 14837 { 14838 BCMI_QTC_XGXS_DSC_SM_CTL0r, 14839 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14840 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 14841 BCMI_QTC_XGXS_DSC_SM_CTL0r_fields, 14842 #else 14843 0, 14844 #endif 14845 #endif 14846 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14847 PHYMOD_SYMBOL_FLAG_REGISTER, 14848 "DSC_SM_CTL0r", 14849 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14850 "DSC_B_DSC_SM_CTRL_0", 14851 NULL, 14852 #endif 14853 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14854 0x8, /* 8 */ 14855 0, 14856 #endif 14857 }, 14858 { 14859 BCMI_QTC_XGXS_DSC_SM_CTL1r, 14860 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14861 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 14862 BCMI_QTC_XGXS_DSC_SM_CTL1r_fields, 14863 #else 14864 0, 14865 #endif 14866 #endif 14867 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14868 PHYMOD_SYMBOL_FLAG_REGISTER, 14869 "DSC_SM_CTL1r", 14870 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14871 "DSC_B_DSC_SM_CTRL_1", 14872 NULL, 14873 #endif 14874 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14875 0x200, /* 512 */ 14876 0, 14877 #endif 14878 }, 14879 { 14880 BCMI_QTC_XGXS_DSC_SM_CTL2r, 14881 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14882 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 14883 BCMI_QTC_XGXS_DSC_SM_CTL2r_fields, 14884 #else 14885 0, 14886 #endif 14887 #endif 14888 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14889 PHYMOD_SYMBOL_FLAG_REGISTER, 14890 "DSC_SM_CTL2r", 14891 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14892 "DSC_B_DSC_SM_CTRL_2", 14893 NULL, 14894 #endif 14895 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14896 0x87, /* 135 */ 14897 0, 14898 #endif 14899 }, 14900 { 14901 BCMI_QTC_XGXS_DSC_SM_CTL3r, 14902 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14903 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 14904 BCMI_QTC_XGXS_DSC_SM_CTL3r_fields, 14905 #else 14906 0, 14907 #endif 14908 #endif 14909 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14910 PHYMOD_SYMBOL_FLAG_REGISTER, 14911 "DSC_SM_CTL3r", 14912 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14913 "DSC_B_DSC_SM_CTRL_3", 14914 NULL, 14915 #endif 14916 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14917 0x1c1e, /* 7198 */ 14918 0, 14919 #endif 14920 }, 14921 { 14922 BCMI_QTC_XGXS_DSC_SM_CTL4r, 14923 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14924 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 14925 BCMI_QTC_XGXS_DSC_SM_CTL4r_fields, 14926 #else 14927 0, 14928 #endif 14929 #endif 14930 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14931 PHYMOD_SYMBOL_FLAG_REGISTER, 14932 "DSC_SM_CTL4r", 14933 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14934 "DSC_B_DSC_SM_CTRL_4", 14935 NULL, 14936 #endif 14937 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14938 0x35ad, /* 13741 */ 14939 0, 14940 #endif 14941 }, 14942 { 14943 BCMI_QTC_XGXS_DSC_SM_CTL5r, 14944 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14945 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 14946 BCMI_QTC_XGXS_DSC_SM_CTL5r_fields, 14947 #else 14948 0, 14949 #endif 14950 #endif 14951 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14952 PHYMOD_SYMBOL_FLAG_REGISTER, 14953 "DSC_SM_CTL5r", 14954 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14955 "DSC_B_DSC_SM_CTRL_5", 14956 NULL, 14957 #endif 14958 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14959 0x35ad, /* 13741 */ 14960 0, 14961 #endif 14962 }, 14963 { 14964 BCMI_QTC_XGXS_DSC_SM_CTL6r, 14965 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14966 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 14967 BCMI_QTC_XGXS_DSC_SM_CTL6r_fields, 14968 #else 14969 0, 14970 #endif 14971 #endif 14972 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14973 PHYMOD_SYMBOL_FLAG_REGISTER, 14974 "DSC_SM_CTL6r", 14975 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14976 "DSC_B_DSC_SM_CTRL_6", 14977 NULL, 14978 #endif 14979 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 14980 0x340d, /* 13325 */ 14981 0, 14982 #endif 14983 }, 14984 { 14985 BCMI_QTC_XGXS_DSC_SM_CTL7r, 14986 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 14987 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 14988 BCMI_QTC_XGXS_DSC_SM_CTL7r_fields, 14989 #else 14990 0, 14991 #endif 14992 #endif 14993 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 14994 PHYMOD_SYMBOL_FLAG_REGISTER, 14995 "DSC_SM_CTL7r", 14996 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 14997 "DSC_B_DSC_SM_CTRL_7", 14998 NULL, 14999 #endif 15000 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15001 0x0, /* 0 */ 15002 0, 15003 #endif 15004 }, 15005 { 15006 BCMI_QTC_XGXS_DSC_SM_CTL8r, 15007 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15008 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 15009 BCMI_QTC_XGXS_DSC_SM_CTL8r_fields, 15010 #else 15011 0, 15012 #endif 15013 #endif 15014 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15015 PHYMOD_SYMBOL_FLAG_REGISTER, 15016 "DSC_SM_CTL8r", 15017 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15018 "DSC_B_DSC_SM_CTRL_8", 15019 NULL, 15020 #endif 15021 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15022 0x11, /* 17 */ 15023 0, 15024 #endif 15025 }, 15026 { 15027 BCMI_QTC_XGXS_DSC_SM_CTL9r, 15028 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15029 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 15030 BCMI_QTC_XGXS_DSC_SM_CTL9r_fields, 15031 #else 15032 0, 15033 #endif 15034 #endif 15035 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15036 PHYMOD_SYMBOL_FLAG_REGISTER, 15037 "DSC_SM_CTL9r", 15038 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15039 "DSC_B_DSC_SM_CTRL_9", 15040 NULL, 15041 #endif 15042 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15043 0x0, /* 0 */ 15044 0, 15045 #endif 15046 }, 15047 { 15048 BCMI_QTC_XGXS_DSC_SM_STS_DSC_LOCKr, 15049 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15050 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 15051 BCMI_QTC_XGXS_DSC_SM_STS_DSC_LOCKr_fields, 15052 #else 15053 0, 15054 #endif 15055 #endif 15056 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15057 PHYMOD_SYMBOL_FLAG_REGISTER, 15058 "DSC_SM_STS_DSC_LOCKr", 15059 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15060 "DSC_B_DSC_SM_STATUS_DSC_LOCK", 15061 NULL, 15062 #endif 15063 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15064 0x0, /* 0 */ 15065 0, 15066 #endif 15067 }, 15068 { 15069 BCMI_QTC_XGXS_DSC_SM_STS_DSC_ST_ONE_HOTr, 15070 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15071 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 15072 BCMI_QTC_XGXS_DSC_SM_STS_DSC_ST_ONE_HOTr_fields, 15073 #else 15074 0, 15075 #endif 15076 #endif 15077 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15078 PHYMOD_SYMBOL_FLAG_REGISTER, 15079 "DSC_SM_STS_DSC_ST_ONE_HOTr", 15080 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15081 "DSC_B_DSC_SM_STATUS_DSC_STATE_ONE_HOT", 15082 NULL, 15083 #endif 15084 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15085 0x0, /* 0 */ 15086 0, 15087 #endif 15088 }, 15089 { 15090 BCMI_QTC_XGXS_DSC_SM_STS_DSC_ST_EEE_ONE_HOTr, 15091 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15092 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 15093 BCMI_QTC_XGXS_DSC_SM_STS_DSC_ST_EEE_ONE_HOTr_fields, 15094 #else 15095 0, 15096 #endif 15097 #endif 15098 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15099 PHYMOD_SYMBOL_FLAG_REGISTER, 15100 "DSC_SM_STS_DSC_ST_EEE_ONE_HOTr", 15101 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15102 "DSC_B_DSC_SM_STATUS_DSC_STATE_EEE_ONE_HOT", 15103 NULL, 15104 #endif 15105 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15106 0x0, /* 0 */ 15107 0, 15108 #endif 15109 }, 15110 { 15111 BCMI_QTC_XGXS_DSC_SM_STS_RESTARTr, 15112 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15113 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 15114 BCMI_QTC_XGXS_DSC_SM_STS_RESTARTr_fields, 15115 #else 15116 0, 15117 #endif 15118 #endif 15119 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15120 PHYMOD_SYMBOL_FLAG_REGISTER, 15121 "DSC_SM_STS_RESTARTr", 15122 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15123 "DSC_B_DSC_SM_STATUS_RESTART", 15124 NULL, 15125 #endif 15126 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15127 0x0, /* 0 */ 15128 0, 15129 #endif 15130 }, 15131 { 15132 BCMI_QTC_XGXS_DSC_SM_STS_DSC_STr, 15133 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15134 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 15135 BCMI_QTC_XGXS_DSC_SM_STS_DSC_STr_fields, 15136 #else 15137 0, 15138 #endif 15139 #endif 15140 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15141 PHYMOD_SYMBOL_FLAG_REGISTER, 15142 "DSC_SM_STS_DSC_STr", 15143 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15144 "DSC_B_DSC_SM_STATUS_DSC_STATE", 15145 NULL, 15146 #endif 15147 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15148 0x40, /* 64 */ 15149 0, 15150 #endif 15151 }, 15152 { 15153 BCMI_QTC_XGXS_DSC_DFE_COMMON_CTLr, 15154 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15155 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 15156 BCMI_QTC_XGXS_DSC_DFE_COMMON_CTLr_fields, 15157 #else 15158 0, 15159 #endif 15160 #endif 15161 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15162 PHYMOD_SYMBOL_FLAG_REGISTER, 15163 "DSC_DFE_COMMON_CTLr", 15164 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15165 "DSC_C_DFE_COMMON_CTL", 15166 NULL, 15167 #endif 15168 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15169 0x0, /* 0 */ 15170 0, 15171 #endif 15172 }, 15173 { 15174 BCMI_QTC_XGXS_DSC_DFE_1_CTLr, 15175 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15176 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 15177 BCMI_QTC_XGXS_DSC_DFE_1_CTLr_fields, 15178 #else 15179 0, 15180 #endif 15181 #endif 15182 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15183 PHYMOD_SYMBOL_FLAG_REGISTER, 15184 "DSC_DFE_1_CTLr", 15185 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15186 "DSC_C_DFE_1_CTL", 15187 NULL, 15188 #endif 15189 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15190 0x0, /* 0 */ 15191 0, 15192 #endif 15193 }, 15194 { 15195 BCMI_QTC_XGXS_DSC_DFE_2_CTLr, 15196 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15197 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 15198 BCMI_QTC_XGXS_DSC_DFE_2_CTLr_fields, 15199 #else 15200 0, 15201 #endif 15202 #endif 15203 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15204 PHYMOD_SYMBOL_FLAG_REGISTER, 15205 "DSC_DFE_2_CTLr", 15206 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15207 "DSC_C_DFE_2_CTL", 15208 NULL, 15209 #endif 15210 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15211 0x0, /* 0 */ 15212 0, 15213 #endif 15214 }, 15215 { 15216 BCMI_QTC_XGXS_DSC_DFE_3_CTLr, 15217 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15218 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 15219 BCMI_QTC_XGXS_DSC_DFE_3_CTLr_fields, 15220 #else 15221 0, 15222 #endif 15223 #endif 15224 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15225 PHYMOD_SYMBOL_FLAG_REGISTER, 15226 "DSC_DFE_3_CTLr", 15227 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15228 "DSC_C_DFE_3_CTL", 15229 NULL, 15230 #endif 15231 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15232 0x0, /* 0 */ 15233 0, 15234 #endif 15235 }, 15236 { 15237 BCMI_QTC_XGXS_DSC_DFE_4_CTLr, 15238 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15239 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 15240 BCMI_QTC_XGXS_DSC_DFE_4_CTLr_fields, 15241 #else 15242 0, 15243 #endif 15244 #endif 15245 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15246 PHYMOD_SYMBOL_FLAG_REGISTER, 15247 "DSC_DFE_4_CTLr", 15248 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15249 "DSC_C_DFE_4_CTL", 15250 NULL, 15251 #endif 15252 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15253 0x0, /* 0 */ 15254 0, 15255 #endif 15256 }, 15257 { 15258 BCMI_QTC_XGXS_DSC_DFE_5_CTLr, 15259 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15260 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 15261 BCMI_QTC_XGXS_DSC_DFE_5_CTLr_fields, 15262 #else 15263 0, 15264 #endif 15265 #endif 15266 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15267 PHYMOD_SYMBOL_FLAG_REGISTER, 15268 "DSC_DFE_5_CTLr", 15269 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15270 "DSC_C_DFE_5_CTL", 15271 NULL, 15272 #endif 15273 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15274 0x0, /* 0 */ 15275 0, 15276 #endif 15277 }, 15278 { 15279 BCMI_QTC_XGXS_DSC_DFE_PAT_CTLr, 15280 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15281 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 15282 BCMI_QTC_XGXS_DSC_DFE_PAT_CTLr_fields, 15283 #else 15284 0, 15285 #endif 15286 #endif 15287 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15288 PHYMOD_SYMBOL_FLAG_REGISTER, 15289 "DSC_DFE_PAT_CTLr", 15290 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15291 "DSC_C_DFE_PAT_CTL", 15292 NULL, 15293 #endif 15294 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15295 0x0, /* 0 */ 15296 0, 15297 #endif 15298 }, 15299 { 15300 BCMI_QTC_XGXS_DSC_VGA_P1_MISC_CTLr, 15301 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15302 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 15303 BCMI_QTC_XGXS_DSC_VGA_P1_MISC_CTLr_fields, 15304 #else 15305 0, 15306 #endif 15307 #endif 15308 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15309 PHYMOD_SYMBOL_FLAG_REGISTER, 15310 "DSC_VGA_P1_MISC_CTLr", 15311 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15312 "DSC_C_VGA_P1_MISC_CONTROL", 15313 NULL, 15314 #endif 15315 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15316 0x8440, /* 33856 */ 15317 0, 15318 #endif 15319 }, 15320 { 15321 BCMI_QTC_XGXS_DSC_DC_SLCR_OFFS_CTLr, 15322 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15323 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 15324 BCMI_QTC_XGXS_DSC_DC_SLCR_OFFS_CTLr_fields, 15325 #else 15326 0, 15327 #endif 15328 #endif 15329 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15330 PHYMOD_SYMBOL_FLAG_REGISTER, 15331 "DSC_DC_SLCR_OFFS_CTLr", 15332 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15333 "DSC_C_DC_SLICER_OFFSET_CTL", 15334 NULL, 15335 #endif 15336 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15337 0x0, /* 0 */ 15338 0, 15339 #endif 15340 }, 15341 { 15342 BCMI_QTC_XGXS_DSC_SLCR_OFFS_CTLr, 15343 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15344 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 15345 BCMI_QTC_XGXS_DSC_SLCR_OFFS_CTLr_fields, 15346 #else 15347 0, 15348 #endif 15349 #endif 15350 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15351 PHYMOD_SYMBOL_FLAG_REGISTER, 15352 "DSC_SLCR_OFFS_CTLr", 15353 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15354 "DSC_C_SLICER_OFFSET_CONTROL", 15355 NULL, 15356 #endif 15357 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15358 0x0, /* 0 */ 15359 0, 15360 #endif 15361 }, 15362 { 15363 BCMI_QTC_XGXS_DSC_HWTUNE_OVR_OVRRr, 15364 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15365 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 15366 BCMI_QTC_XGXS_DSC_HWTUNE_OVR_OVRRr_fields, 15367 #else 15368 0, 15369 #endif 15370 #endif 15371 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15372 PHYMOD_SYMBOL_FLAG_REGISTER, 15373 "DSC_HWTUNE_OVR_OVRRr", 15374 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15375 "DSC_C_HWTUNE_OVR_OVERRIDE", 15376 NULL, 15377 #endif 15378 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15379 0x0, /* 0 */ 15380 0, 15381 #endif 15382 }, 15383 { 15384 BCMI_QTC_XGXS_DSC_VGA_CTLr, 15385 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15386 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 15387 BCMI_QTC_XGXS_DSC_VGA_CTLr_fields, 15388 #else 15389 0, 15390 #endif 15391 #endif 15392 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15393 PHYMOD_SYMBOL_FLAG_REGISTER, 15394 "DSC_VGA_CTLr", 15395 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15396 "DSC_C_VGA_CTL", 15397 NULL, 15398 #endif 15399 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15400 0x0, /* 0 */ 15401 0, 15402 #endif 15403 }, 15404 { 15405 BCMI_QTC_XGXS_DSC_VGA_PAT_EYEDIAG_CTLr, 15406 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15407 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 15408 BCMI_QTC_XGXS_DSC_VGA_PAT_EYEDIAG_CTLr_fields, 15409 #else 15410 0, 15411 #endif 15412 #endif 15413 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15414 PHYMOD_SYMBOL_FLAG_REGISTER, 15415 "DSC_VGA_PAT_EYEDIAG_CTLr", 15416 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15417 "DSC_C_VGA_PAT_EYEDIAG_CTL", 15418 NULL, 15419 #endif 15420 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15421 0x0, /* 0 */ 15422 0, 15423 #endif 15424 }, 15425 { 15426 BCMI_QTC_XGXS_DSC_P1_FRAC_OFFS_CTLr, 15427 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15428 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 15429 BCMI_QTC_XGXS_DSC_P1_FRAC_OFFS_CTLr_fields, 15430 #else 15431 0, 15432 #endif 15433 #endif 15434 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15435 PHYMOD_SYMBOL_FLAG_REGISTER, 15436 "DSC_P1_FRAC_OFFS_CTLr", 15437 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15438 "DSC_C_P1_FRAC_OFFS_CTL", 15439 NULL, 15440 #endif 15441 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15442 0xc400, /* 50176 */ 15443 0, 15444 #endif 15445 }, 15446 { 15447 BCMI_QTC_XGXS_DSC_TRNSUM_CTL1r, 15448 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15449 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 15450 BCMI_QTC_XGXS_DSC_TRNSUM_CTL1r_fields, 15451 #else 15452 0, 15453 #endif 15454 #endif 15455 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15456 PHYMOD_SYMBOL_FLAG_REGISTER, 15457 "DSC_TRNSUM_CTL1r", 15458 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15459 "DSC_D_TRNSUM_CTL_1", 15460 NULL, 15461 #endif 15462 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15463 0x0, /* 0 */ 15464 0, 15465 #endif 15466 }, 15467 { 15468 BCMI_QTC_XGXS_DSC_TRNSUM_CTL2r, 15469 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15470 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 15471 BCMI_QTC_XGXS_DSC_TRNSUM_CTL2r_fields, 15472 #else 15473 0, 15474 #endif 15475 #endif 15476 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15477 PHYMOD_SYMBOL_FLAG_REGISTER, 15478 "DSC_TRNSUM_CTL2r", 15479 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15480 "DSC_D_TRNSUM_CTL_2", 15481 NULL, 15482 #endif 15483 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15484 0x0, /* 0 */ 15485 0, 15486 #endif 15487 }, 15488 { 15489 BCMI_QTC_XGXS_DSC_TRNSUM_CTL3r, 15490 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15491 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 15492 BCMI_QTC_XGXS_DSC_TRNSUM_CTL3r_fields, 15493 #else 15494 0, 15495 #endif 15496 #endif 15497 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15498 PHYMOD_SYMBOL_FLAG_REGISTER, 15499 "DSC_TRNSUM_CTL3r", 15500 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15501 "DSC_D_TRNSUM_CTL_3", 15502 NULL, 15503 #endif 15504 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15505 0x0, /* 0 */ 15506 0, 15507 #endif 15508 }, 15509 { 15510 BCMI_QTC_XGXS_DSC_TRNSUM_CTL4r, 15511 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15512 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 15513 BCMI_QTC_XGXS_DSC_TRNSUM_CTL4r_fields, 15514 #else 15515 0, 15516 #endif 15517 #endif 15518 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15519 PHYMOD_SYMBOL_FLAG_REGISTER, 15520 "DSC_TRNSUM_CTL4r", 15521 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15522 "DSC_D_TRNSUM_CTL_4", 15523 NULL, 15524 #endif 15525 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15526 0x0, /* 0 */ 15527 0, 15528 #endif 15529 }, 15530 { 15531 BCMI_QTC_XGXS_DSC_TRNSUM_STS1r, 15532 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15533 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 15534 BCMI_QTC_XGXS_DSC_TRNSUM_STS1r_fields, 15535 #else 15536 0, 15537 #endif 15538 #endif 15539 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15540 PHYMOD_SYMBOL_FLAG_REGISTER, 15541 "DSC_TRNSUM_STS1r", 15542 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15543 "DSC_D_TRNSUM_STS_1", 15544 NULL, 15545 #endif 15546 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15547 0x0, /* 0 */ 15548 0, 15549 #endif 15550 }, 15551 { 15552 BCMI_QTC_XGXS_DSC_TRNSUM_STS2r, 15553 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15554 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 15555 BCMI_QTC_XGXS_DSC_TRNSUM_STS2r_fields, 15556 #else 15557 0, 15558 #endif 15559 #endif 15560 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15561 PHYMOD_SYMBOL_FLAG_REGISTER, 15562 "DSC_TRNSUM_STS2r", 15563 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15564 "DSC_D_TRNSUM_STS_2", 15565 NULL, 15566 #endif 15567 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15568 0x0, /* 0 */ 15569 0, 15570 #endif 15571 }, 15572 { 15573 BCMI_QTC_XGXS_DSC_TRNSUM_STS3r, 15574 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15575 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 15576 BCMI_QTC_XGXS_DSC_TRNSUM_STS3r_fields, 15577 #else 15578 0, 15579 #endif 15580 #endif 15581 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15582 PHYMOD_SYMBOL_FLAG_REGISTER, 15583 "DSC_TRNSUM_STS3r", 15584 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15585 "DSC_D_TRNSUM_STS_3", 15586 NULL, 15587 #endif 15588 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15589 0x0, /* 0 */ 15590 0, 15591 #endif 15592 }, 15593 { 15594 BCMI_QTC_XGXS_DSC_TRNSUM_STS4r, 15595 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15596 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 15597 BCMI_QTC_XGXS_DSC_TRNSUM_STS4r_fields, 15598 #else 15599 0, 15600 #endif 15601 #endif 15602 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15603 PHYMOD_SYMBOL_FLAG_REGISTER, 15604 "DSC_TRNSUM_STS4r", 15605 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15606 "DSC_D_TRNSUM_STS_4", 15607 NULL, 15608 #endif 15609 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15610 0x0, /* 0 */ 15611 0, 15612 #endif 15613 }, 15614 { 15615 BCMI_QTC_XGXS_DSC_TRNSUM_STS5r, 15616 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15617 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 15618 BCMI_QTC_XGXS_DSC_TRNSUM_STS5r_fields, 15619 #else 15620 0, 15621 #endif 15622 #endif 15623 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15624 PHYMOD_SYMBOL_FLAG_REGISTER, 15625 "DSC_TRNSUM_STS5r", 15626 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15627 "DSC_D_TRNSUM_STS_5", 15628 NULL, 15629 #endif 15630 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15631 0x0, /* 0 */ 15632 0, 15633 #endif 15634 }, 15635 { 15636 BCMI_QTC_XGXS_DSC_TRNSUM_STS6r, 15637 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15638 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 15639 BCMI_QTC_XGXS_DSC_TRNSUM_STS6r_fields, 15640 #else 15641 0, 15642 #endif 15643 #endif 15644 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15645 PHYMOD_SYMBOL_FLAG_REGISTER, 15646 "DSC_TRNSUM_STS6r", 15647 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15648 "DSC_D_TRNSUM_STS_6", 15649 NULL, 15650 #endif 15651 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15652 0x0, /* 0 */ 15653 0, 15654 #endif 15655 }, 15656 { 15657 BCMI_QTC_XGXS_DSC_VGA_P1EYEDIAG_STSr, 15658 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15659 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 15660 BCMI_QTC_XGXS_DSC_VGA_P1EYEDIAG_STSr_fields, 15661 #else 15662 0, 15663 #endif 15664 #endif 15665 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15666 PHYMOD_SYMBOL_FLAG_REGISTER, 15667 "DSC_VGA_P1EYEDIAG_STSr", 15668 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15669 "DSC_D_VGA_P1EYEDIAG_STS", 15670 NULL, 15671 #endif 15672 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15673 0x0, /* 0 */ 15674 0, 15675 #endif 15676 }, 15677 { 15678 BCMI_QTC_XGXS_DSC_DFE_1_STSr, 15679 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15680 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 15681 BCMI_QTC_XGXS_DSC_DFE_1_STSr_fields, 15682 #else 15683 0, 15684 #endif 15685 #endif 15686 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15687 PHYMOD_SYMBOL_FLAG_REGISTER, 15688 "DSC_DFE_1_STSr", 15689 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15690 "DSC_D_DFE_1_STS", 15691 NULL, 15692 #endif 15693 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15694 0x0, /* 0 */ 15695 0, 15696 #endif 15697 }, 15698 { 15699 BCMI_QTC_XGXS_DSC_DFE_2_STSr, 15700 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15701 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 15702 BCMI_QTC_XGXS_DSC_DFE_2_STSr_fields, 15703 #else 15704 0, 15705 #endif 15706 #endif 15707 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15708 PHYMOD_SYMBOL_FLAG_REGISTER, 15709 "DSC_DFE_2_STSr", 15710 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15711 "DSC_D_DFE_2_STS", 15712 NULL, 15713 #endif 15714 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15715 0x0, /* 0 */ 15716 0, 15717 #endif 15718 }, 15719 { 15720 BCMI_QTC_XGXS_DSC_DFE_3_4_5_STSr, 15721 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15722 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 15723 BCMI_QTC_XGXS_DSC_DFE_3_4_5_STSr_fields, 15724 #else 15725 0, 15726 #endif 15727 #endif 15728 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15729 PHYMOD_SYMBOL_FLAG_REGISTER, 15730 "DSC_DFE_3_4_5_STSr", 15731 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15732 "DSC_D_DFE_3_4_5_STS", 15733 NULL, 15734 #endif 15735 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15736 0x0, /* 0 */ 15737 0, 15738 #endif 15739 }, 15740 { 15741 BCMI_QTC_XGXS_DSC_VGA_TAP_BINr, 15742 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15743 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 15744 BCMI_QTC_XGXS_DSC_VGA_TAP_BINr_fields, 15745 #else 15746 0, 15747 #endif 15748 #endif 15749 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15750 PHYMOD_SYMBOL_FLAG_REGISTER, 15751 "DSC_VGA_TAP_BINr", 15752 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15753 "DSC_D_VGA_TAP_BIN", 15754 NULL, 15755 #endif 15756 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15757 0x0, /* 0 */ 15758 0, 15759 #endif 15760 }, 15761 { 15762 BCMI_QTC_XGXS_DSC_E_CTLr, 15763 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15764 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 15765 BCMI_QTC_XGXS_DSC_E_CTLr_fields, 15766 #else 15767 0, 15768 #endif 15769 #endif 15770 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15771 PHYMOD_SYMBOL_FLAG_REGISTER, 15772 "DSC_E_CTLr", 15773 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15774 "DSC_E_DSC_E_CTRL", 15775 NULL, 15776 #endif 15777 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15778 0x30, /* 48 */ 15779 0, 15780 #endif 15781 }, 15782 { 15783 BCMI_QTC_XGXS_DSC_E_PF_CTLr, 15784 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15785 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 15786 BCMI_QTC_XGXS_DSC_E_PF_CTLr_fields, 15787 #else 15788 0, 15789 #endif 15790 #endif 15791 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15792 PHYMOD_SYMBOL_FLAG_REGISTER, 15793 "DSC_E_PF_CTLr", 15794 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15795 "DSC_E_DSC_E_PF_CTRL", 15796 NULL, 15797 #endif 15798 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15799 0x0, /* 0 */ 15800 0, 15801 #endif 15802 }, 15803 { 15804 BCMI_QTC_XGXS_DSC_E_PF2_LOWP_CTLr, 15805 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15806 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 15807 BCMI_QTC_XGXS_DSC_E_PF2_LOWP_CTLr_fields, 15808 #else 15809 0, 15810 #endif 15811 #endif 15812 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15813 PHYMOD_SYMBOL_FLAG_REGISTER, 15814 "DSC_E_PF2_LOWP_CTLr", 15815 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15816 "DSC_E_DSC_E_PF2_LOWP_CTRL", 15817 NULL, 15818 #endif 15819 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15820 0x0, /* 0 */ 15821 0, 15822 #endif 15823 }, 15824 { 15825 BCMI_QTC_XGXS_CL72_RXCL72UR_CTL0r, 15826 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15827 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 15828 BCMI_QTC_XGXS_CL72_RXCL72UR_CTL0r_fields, 15829 #else 15830 0, 15831 #endif 15832 #endif 15833 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15834 PHYMOD_SYMBOL_FLAG_REGISTER, 15835 "CL72_RXCL72UR_CTL0r", 15836 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15837 "CL72_USER_RX_CL72UR_CONTROL0_REGISTER", 15838 NULL, 15839 #endif 15840 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15841 0x4, /* 4 */ 15842 0, 15843 #endif 15844 }, 15845 { 15846 BCMI_QTC_XGXS_CL72_RXCL72UR_CTL1r, 15847 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15848 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 15849 BCMI_QTC_XGXS_CL72_RXCL72UR_CTL1r_fields, 15850 #else 15851 0, 15852 #endif 15853 #endif 15854 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15855 PHYMOD_SYMBOL_FLAG_REGISTER, 15856 "CL72_RXCL72UR_CTL1r", 15857 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15858 "CL72_USER_RX_CL72UR_CONTROL1_REGISTER", 15859 NULL, 15860 #endif 15861 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15862 0x52, /* 82 */ 15863 0, 15864 #endif 15865 }, 15866 { 15867 BCMI_QTC_XGXS_CL72_RXCL72UR_CTL2r, 15868 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15869 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 15870 BCMI_QTC_XGXS_CL72_RXCL72UR_CTL2r_fields, 15871 #else 15872 0, 15873 #endif 15874 #endif 15875 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15876 PHYMOD_SYMBOL_FLAG_REGISTER, 15877 "CL72_RXCL72UR_CTL2r", 15878 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15879 "CL72_USER_RX_CL72UR_CONTROL2_REGISTER", 15880 NULL, 15881 #endif 15882 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15883 0x310, /* 784 */ 15884 0, 15885 #endif 15886 }, 15887 { 15888 BCMI_QTC_XGXS_CL72_RXCL72UR_STS0r, 15889 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15890 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 15891 BCMI_QTC_XGXS_CL72_RXCL72UR_STS0r_fields, 15892 #else 15893 0, 15894 #endif 15895 #endif 15896 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15897 PHYMOD_SYMBOL_FLAG_REGISTER, 15898 "CL72_RXCL72UR_STS0r", 15899 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15900 "CL72_USER_RX_CL72UR_STATUS0_REGISTER", 15901 NULL, 15902 #endif 15903 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15904 0x0, /* 0 */ 15905 0, 15906 #endif 15907 }, 15908 { 15909 BCMI_QTC_XGXS_CL72_RXCL72UR_UC_INTR_CTL0r, 15910 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15911 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 15912 BCMI_QTC_XGXS_CL72_RXCL72UR_UC_INTR_CTL0r_fields, 15913 #else 15914 0, 15915 #endif 15916 #endif 15917 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15918 PHYMOD_SYMBOL_FLAG_REGISTER, 15919 "CL72_RXCL72UR_UC_INTR_CTL0r", 15920 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15921 "CL72_USER_RX_CL72UR_MICRO_INTERRUPT_CONTROL0_REGISTER", 15922 NULL, 15923 #endif 15924 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15925 0x0, /* 0 */ 15926 0, 15927 #endif 15928 }, 15929 { 15930 BCMI_QTC_XGXS_CL72_RXCL72UR_UC_STS0r, 15931 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15932 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 15933 BCMI_QTC_XGXS_CL72_RXCL72UR_UC_STS0r_fields, 15934 #else 15935 0, 15936 #endif 15937 #endif 15938 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15939 PHYMOD_SYMBOL_FLAG_REGISTER, 15940 "CL72_RXCL72UR_UC_STS0r", 15941 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15942 "CL72_USER_RX_CL72UR_MICRO_STATUS0_REGISTER", 15943 NULL, 15944 #endif 15945 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15946 0x0, /* 0 */ 15947 0, 15948 #endif 15949 }, 15950 { 15951 BCMI_QTC_XGXS_CL72_RXCL72UR_UC_STS1r, 15952 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15953 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 15954 BCMI_QTC_XGXS_CL72_RXCL72UR_UC_STS1r_fields, 15955 #else 15956 0, 15957 #endif 15958 #endif 15959 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15960 PHYMOD_SYMBOL_FLAG_REGISTER, 15961 "CL72_RXCL72UR_UC_STS1r", 15962 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15963 "CL72_USER_RX_CL72UR_MICRO_STATUS1_REGISTER", 15964 NULL, 15965 #endif 15966 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15967 0x0, /* 0 */ 15968 0, 15969 #endif 15970 }, 15971 { 15972 BCMI_QTC_XGXS_CL72_TXCL72UT_XMT_UPD_PAGEr, 15973 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15974 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 15975 BCMI_QTC_XGXS_CL72_TXCL72UT_XMT_UPD_PAGEr_fields, 15976 #else 15977 0, 15978 #endif 15979 #endif 15980 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 15981 PHYMOD_SYMBOL_FLAG_REGISTER, 15982 "CL72_TXCL72UT_XMT_UPD_PAGEr", 15983 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 15984 "CL72_USER_TX_CL72UT_XMT_UPDATE_PAGE_REGISTER", 15985 NULL, 15986 #endif 15987 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 15988 0x0, /* 0 */ 15989 0, 15990 #endif 15991 }, 15992 { 15993 BCMI_QTC_XGXS_CL72_TXCL72UT_LD_XMT_STS_PAGEr, 15994 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 15995 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 15996 BCMI_QTC_XGXS_CL72_TXCL72UT_LD_XMT_STS_PAGEr_fields, 15997 #else 15998 0, 15999 #endif 16000 #endif 16001 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16002 PHYMOD_SYMBOL_FLAG_REGISTER, 16003 "CL72_TXCL72UT_LD_XMT_STS_PAGEr", 16004 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16005 "CL72_USER_TX_CL72UT_LD_XMT_STATUS_PAGE", 16006 NULL, 16007 #endif 16008 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16009 0x0, /* 0 */ 16010 0, 16011 #endif 16012 }, 16013 { 16014 BCMI_QTC_XGXS_CL72_TXCL72UT_CTL0r, 16015 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16016 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 16017 BCMI_QTC_XGXS_CL72_TXCL72UT_CTL0r_fields, 16018 #else 16019 0, 16020 #endif 16021 #endif 16022 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16023 PHYMOD_SYMBOL_FLAG_REGISTER, 16024 "CL72_TXCL72UT_CTL0r", 16025 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16026 "CL72_USER_TX_CL72UT_CONTROL0_REGISTER", 16027 NULL, 16028 #endif 16029 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16030 0x0, /* 0 */ 16031 0, 16032 #endif 16033 }, 16034 { 16035 BCMI_QTC_XGXS_CL72_TXCL72UT_CTL1r, 16036 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16037 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 16038 BCMI_QTC_XGXS_CL72_TXCL72UT_CTL1r_fields, 16039 #else 16040 0, 16041 #endif 16042 #endif 16043 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16044 PHYMOD_SYMBOL_FLAG_REGISTER, 16045 "CL72_TXCL72UT_CTL1r", 16046 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16047 "CL72_USER_TX_CL72UT_CONTROL1_REGISTER", 16048 NULL, 16049 #endif 16050 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16051 0x4, /* 4 */ 16052 0, 16053 #endif 16054 }, 16055 { 16056 BCMI_QTC_XGXS_CL72_TXCL72UT_CTL2r, 16057 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16058 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 16059 BCMI_QTC_XGXS_CL72_TXCL72UT_CTL2r_fields, 16060 #else 16061 0, 16062 #endif 16063 #endif 16064 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16065 PHYMOD_SYMBOL_FLAG_REGISTER, 16066 "CL72_TXCL72UT_CTL2r", 16067 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16068 "CL72_USER_TX_CL72UT_CONTROL2_REGISTER", 16069 NULL, 16070 #endif 16071 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16072 0x0, /* 0 */ 16073 0, 16074 #endif 16075 }, 16076 { 16077 BCMI_QTC_XGXS_CL72_TXCL72UT_CTL3r, 16078 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16079 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 16080 BCMI_QTC_XGXS_CL72_TXCL72UT_CTL3r_fields, 16081 #else 16082 0, 16083 #endif 16084 #endif 16085 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16086 PHYMOD_SYMBOL_FLAG_REGISTER, 16087 "CL72_TXCL72UT_CTL3r", 16088 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16089 "CL72_USER_TX_CL72UT_CONTROL3_REGISTER", 16090 NULL, 16091 #endif 16092 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16093 0x24, /* 36 */ 16094 0, 16095 #endif 16096 }, 16097 { 16098 BCMI_QTC_XGXS_CL72_TXCL72UT_STS0r, 16099 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16100 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 16101 BCMI_QTC_XGXS_CL72_TXCL72UT_STS0r_fields, 16102 #else 16103 0, 16104 #endif 16105 #endif 16106 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16107 PHYMOD_SYMBOL_FLAG_REGISTER, 16108 "CL72_TXCL72UT_STS0r", 16109 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16110 "CL72_USER_TX_CL72UT_STATUS0_REGISTER", 16111 NULL, 16112 #endif 16113 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16114 0x2, /* 2 */ 16115 0, 16116 #endif 16117 }, 16118 { 16119 BCMI_QTC_XGXS_CL72_TXCL72UT_CTL4r, 16120 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16121 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 16122 BCMI_QTC_XGXS_CL72_TXCL72UT_CTL4r_fields, 16123 #else 16124 0, 16125 #endif 16126 #endif 16127 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16128 PHYMOD_SYMBOL_FLAG_REGISTER, 16129 "CL72_TXCL72UT_CTL4r", 16130 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16131 "CL72_USER_TX_CL72UT_CONTROL4_REGISTER", 16132 NULL, 16133 #endif 16134 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16135 0x3f5, /* 1013 */ 16136 0, 16137 #endif 16138 }, 16139 { 16140 BCMI_QTC_XGXS_TX_PI_CTL0r, 16141 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16142 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 16143 BCMI_QTC_XGXS_TX_PI_CTL0r_fields, 16144 #else 16145 0, 16146 #endif 16147 #endif 16148 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16149 PHYMOD_SYMBOL_FLAG_REGISTER, 16150 "TX_PI_CTL0r", 16151 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16152 "TX_PI_TX_PI_CONTROL_0", 16153 NULL, 16154 #endif 16155 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16156 0x0, /* 0 */ 16157 0, 16158 #endif 16159 }, 16160 { 16161 BCMI_QTC_XGXS_TX_PI_CTL1r, 16162 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16163 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 16164 BCMI_QTC_XGXS_TX_PI_CTL1r_fields, 16165 #else 16166 0, 16167 #endif 16168 #endif 16169 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16170 PHYMOD_SYMBOL_FLAG_REGISTER, 16171 "TX_PI_CTL1r", 16172 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16173 "TX_PI_TX_PI_CONTROL_1", 16174 NULL, 16175 #endif 16176 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16177 0x0, /* 0 */ 16178 0, 16179 #endif 16180 }, 16181 { 16182 BCMI_QTC_XGXS_TX_PI_CTL2r, 16183 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16184 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 16185 BCMI_QTC_XGXS_TX_PI_CTL2r_fields, 16186 #else 16187 0, 16188 #endif 16189 #endif 16190 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16191 PHYMOD_SYMBOL_FLAG_REGISTER, 16192 "TX_PI_CTL2r", 16193 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16194 "TX_PI_TX_PI_CONTROL_2", 16195 NULL, 16196 #endif 16197 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16198 0x0, /* 0 */ 16199 0, 16200 #endif 16201 }, 16202 { 16203 BCMI_QTC_XGXS_TX_PI_CTL3r, 16204 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16205 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 16206 BCMI_QTC_XGXS_TX_PI_CTL3r_fields, 16207 #else 16208 0, 16209 #endif 16210 #endif 16211 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16212 PHYMOD_SYMBOL_FLAG_REGISTER, 16213 "TX_PI_CTL3r", 16214 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16215 "TX_PI_TX_PI_CONTROL_3", 16216 NULL, 16217 #endif 16218 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16219 0x3100, /* 12544 */ 16220 0, 16221 #endif 16222 }, 16223 { 16224 BCMI_QTC_XGXS_TX_PI_CTL4r, 16225 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16226 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 16227 BCMI_QTC_XGXS_TX_PI_CTL4r_fields, 16228 #else 16229 0, 16230 #endif 16231 #endif 16232 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16233 PHYMOD_SYMBOL_FLAG_REGISTER, 16234 "TX_PI_CTL4r", 16235 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16236 "TX_PI_TX_PI_CONTROL_4", 16237 NULL, 16238 #endif 16239 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16240 0x4, /* 4 */ 16241 0, 16242 #endif 16243 }, 16244 { 16245 BCMI_QTC_XGXS_TX_PI_CTL5r, 16246 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16247 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 16248 BCMI_QTC_XGXS_TX_PI_CTL5r_fields, 16249 #else 16250 0, 16251 #endif 16252 #endif 16253 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16254 PHYMOD_SYMBOL_FLAG_REGISTER, 16255 "TX_PI_CTL5r", 16256 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16257 "TX_PI_TX_PI_CONTROL_5", 16258 NULL, 16259 #endif 16260 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16261 0x4, /* 4 */ 16262 0, 16263 #endif 16264 }, 16265 { 16266 BCMI_QTC_XGXS_TX_PI_STS0r, 16267 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16268 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 16269 BCMI_QTC_XGXS_TX_PI_STS0r_fields, 16270 #else 16271 0, 16272 #endif 16273 #endif 16274 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16275 PHYMOD_SYMBOL_FLAG_REGISTER, 16276 "TX_PI_STS0r", 16277 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16278 "TX_PI_TX_PI_STATUS_0", 16279 NULL, 16280 #endif 16281 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16282 0x0, /* 0 */ 16283 0, 16284 #endif 16285 }, 16286 { 16287 BCMI_QTC_XGXS_TX_PI_STS1r, 16288 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16289 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 16290 BCMI_QTC_XGXS_TX_PI_STS1r_fields, 16291 #else 16292 0, 16293 #endif 16294 #endif 16295 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16296 PHYMOD_SYMBOL_FLAG_REGISTER, 16297 "TX_PI_STS1r", 16298 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16299 "TX_PI_TX_PI_STATUS_1", 16300 NULL, 16301 #endif 16302 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16303 0x0, /* 0 */ 16304 0, 16305 #endif 16306 }, 16307 { 16308 BCMI_QTC_XGXS_TX_PI_STS2r, 16309 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16310 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 16311 BCMI_QTC_XGXS_TX_PI_STS2r_fields, 16312 #else 16313 0, 16314 #endif 16315 #endif 16316 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16317 PHYMOD_SYMBOL_FLAG_REGISTER, 16318 "TX_PI_STS2r", 16319 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16320 "TX_PI_TX_PI_STATUS_2", 16321 NULL, 16322 #endif 16323 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16324 0x0, /* 0 */ 16325 0, 16326 #endif 16327 }, 16328 { 16329 BCMI_QTC_XGXS_TX_PI_STS3r, 16330 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16331 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 16332 BCMI_QTC_XGXS_TX_PI_STS3r_fields, 16333 #else 16334 0, 16335 #endif 16336 #endif 16337 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16338 PHYMOD_SYMBOL_FLAG_REGISTER, 16339 "TX_PI_STS3r", 16340 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16341 "TX_PI_TX_PI_STATUS_3", 16342 NULL, 16343 #endif 16344 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16345 0x0, /* 0 */ 16346 0, 16347 #endif 16348 }, 16349 { 16350 BCMI_QTC_XGXS_TX_PI_STS4r, 16351 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16352 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 16353 BCMI_QTC_XGXS_TX_PI_STS4r_fields, 16354 #else 16355 0, 16356 #endif 16357 #endif 16358 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16359 PHYMOD_SYMBOL_FLAG_REGISTER, 16360 "TX_PI_STS4r", 16361 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16362 "TX_PI_TX_PI_STATUS_4", 16363 NULL, 16364 #endif 16365 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16366 0x0, /* 0 */ 16367 0, 16368 #endif 16369 }, 16370 { 16371 BCMI_QTC_XGXS_TX_PI_TX_FIFO_OVFB_STSr, 16372 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16373 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 16374 BCMI_QTC_XGXS_TX_PI_TX_FIFO_OVFB_STSr_fields, 16375 #else 16376 0, 16377 #endif 16378 #endif 16379 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16380 PHYMOD_SYMBOL_FLAG_REGISTER, 16381 "TX_PI_TX_FIFO_OVFB_STSr", 16382 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16383 "TX_PI_TX_PI_TX_FIFO_OVFB_STATUS", 16384 NULL, 16385 #endif 16386 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16387 0x0, /* 0 */ 16388 0, 16389 #endif 16390 }, 16391 { 16392 BCMI_QTC_XGXS_RXTXCOM_OSR_MODE_CTLr, 16393 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16394 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 16395 BCMI_QTC_XGXS_RXTXCOM_OSR_MODE_CTLr_fields, 16396 #else 16397 0, 16398 #endif 16399 #endif 16400 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16401 PHYMOD_SYMBOL_FLAG_REGISTER, 16402 "RXTXCOM_OSR_MODE_CTLr", 16403 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16404 "RXTXCOM_CKRST_CTRL_OSR_MODE_CONTROL", 16405 NULL, 16406 #endif 16407 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16408 0x0, /* 0 */ 16409 0, 16410 #endif 16411 }, 16412 { 16413 BCMI_QTC_XGXS_RXTXCOM_LN_CLK_RST_N_PWRDWN_CTLr, 16414 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16415 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 16416 BCMI_QTC_XGXS_RXTXCOM_LN_CLK_RST_N_PWRDWN_CTLr_fields, 16417 #else 16418 0, 16419 #endif 16420 #endif 16421 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16422 PHYMOD_SYMBOL_FLAG_REGISTER, 16423 "RXTXCOM_LN_CLK_RST_N_PWRDWN_CTLr", 16424 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16425 "RXTXCOM_CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL", 16426 NULL, 16427 #endif 16428 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16429 0x0, /* 0 */ 16430 0, 16431 #endif 16432 }, 16433 { 16434 BCMI_QTC_XGXS_RXTXCOM_LN_RST_N_PWRDN_PIN_KILL_CTLr, 16435 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16436 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 16437 BCMI_QTC_XGXS_RXTXCOM_LN_RST_N_PWRDN_PIN_KILL_CTLr_fields, 16438 #else 16439 0, 16440 #endif 16441 #endif 16442 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16443 PHYMOD_SYMBOL_FLAG_REGISTER, 16444 "RXTXCOM_LN_RST_N_PWRDN_PIN_KILL_CTLr", 16445 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16446 "RXTXCOM_CKRST_CTRL_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL", 16447 NULL, 16448 #endif 16449 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16450 0x0, /* 0 */ 16451 0, 16452 #endif 16453 }, 16454 { 16455 BCMI_QTC_XGXS_RXTXCOM_UC_ACK_LN_CTLr, 16456 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16457 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 16458 BCMI_QTC_XGXS_RXTXCOM_UC_ACK_LN_CTLr_fields, 16459 #else 16460 0, 16461 #endif 16462 #endif 16463 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16464 PHYMOD_SYMBOL_FLAG_REGISTER, 16465 "RXTXCOM_UC_ACK_LN_CTLr", 16466 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16467 "RXTXCOM_CKRST_CTRL_UC_ACK_LANE_CONTROL", 16468 NULL, 16469 #endif 16470 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16471 0x0, /* 0 */ 16472 0, 16473 #endif 16474 }, 16475 { 16476 BCMI_QTC_XGXS_RXTXCOM_LN_RST_OCC_CTLr, 16477 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16478 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 16479 BCMI_QTC_XGXS_RXTXCOM_LN_RST_OCC_CTLr_fields, 16480 #else 16481 0, 16482 #endif 16483 #endif 16484 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16485 PHYMOD_SYMBOL_FLAG_REGISTER, 16486 "RXTXCOM_LN_RST_OCC_CTLr", 16487 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16488 "RXTXCOM_CKRST_CTRL_LANE_REG_RESET_OCCURRED_CONTROL", 16489 NULL, 16490 #endif 16491 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16492 0x1, /* 1 */ 16493 0, 16494 #endif 16495 }, 16496 { 16497 BCMI_QTC_XGXS_RXTXCOM_LN_DP_RST_ST_STSr, 16498 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16499 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 16500 BCMI_QTC_XGXS_RXTXCOM_LN_DP_RST_ST_STSr_fields, 16501 #else 16502 0, 16503 #endif 16504 #endif 16505 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16506 PHYMOD_SYMBOL_FLAG_REGISTER, 16507 "RXTXCOM_LN_DP_RST_ST_STSr", 16508 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16509 "RXTXCOM_CKRST_CTRL_LANE_DP_RESET_STATE_STATUS", 16510 NULL, 16511 #endif 16512 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16513 0x7, /* 7 */ 16514 0, 16515 #endif 16516 }, 16517 { 16518 BCMI_QTC_XGXS_RXTXCOM_MCST_MASK_CTLr, 16519 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16520 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 16521 BCMI_QTC_XGXS_RXTXCOM_MCST_MASK_CTLr_fields, 16522 #else 16523 0, 16524 #endif 16525 #endif 16526 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16527 PHYMOD_SYMBOL_FLAG_REGISTER, 16528 "RXTXCOM_MCST_MASK_CTLr", 16529 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16530 "RXTXCOM_CKRST_CTRL_MULTICAST_MASK_CONTROL", 16531 NULL, 16532 #endif 16533 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16534 0x0, /* 0 */ 16535 0, 16536 #endif 16537 }, 16538 { 16539 BCMI_QTC_XGXS_RXTXCOM_OSR_MODE_STS_MC_MASKr, 16540 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16541 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 16542 BCMI_QTC_XGXS_RXTXCOM_OSR_MODE_STS_MC_MASKr_fields, 16543 #else 16544 0, 16545 #endif 16546 #endif 16547 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16548 PHYMOD_SYMBOL_FLAG_REGISTER, 16549 "RXTXCOM_OSR_MODE_STS_MC_MASKr", 16550 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16551 "RXTXCOM_CKRST_CTRL_OSR_MODE_STATUS_MC_MASK", 16552 NULL, 16553 #endif 16554 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16555 0x0, /* 0 */ 16556 0, 16557 #endif 16558 }, 16559 { 16560 BCMI_QTC_XGXS_RXTXCOM_AFE_RST_PWRDN_OSR_MODE_PIN_STSr, 16561 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16562 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 16563 BCMI_QTC_XGXS_RXTXCOM_AFE_RST_PWRDN_OSR_MODE_PIN_STSr_fields, 16564 #else 16565 0, 16566 #endif 16567 #endif 16568 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16569 PHYMOD_SYMBOL_FLAG_REGISTER, 16570 "RXTXCOM_AFE_RST_PWRDN_OSR_MODE_PIN_STSr", 16571 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16572 "RXTXCOM_CKRST_CTRL_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS", 16573 NULL, 16574 #endif 16575 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16576 0x0, /* 0 */ 16577 0, 16578 #endif 16579 }, 16580 { 16581 BCMI_QTC_XGXS_RXTXCOM_LN_S_RSTB_CTLr, 16582 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16583 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 16584 BCMI_QTC_XGXS_RXTXCOM_LN_S_RSTB_CTLr_fields, 16585 #else 16586 0, 16587 #endif 16588 #endif 16589 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16590 PHYMOD_SYMBOL_FLAG_REGISTER, 16591 "RXTXCOM_LN_S_RSTB_CTLr", 16592 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16593 "RXTXCOM_CKRST_CTRL_LN_S_RSTB_CONTROL", 16594 NULL, 16595 #endif 16596 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16597 0x1, /* 1 */ 16598 0, 16599 #endif 16600 }, 16601 { 16602 BCMI_QTC_XGXS_AMS_RX_RX_CTL0r, 16603 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16604 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 16605 BCMI_QTC_XGXS_AMS_RX_RX_CTL0r_fields, 16606 #else 16607 0, 16608 #endif 16609 #endif 16610 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16611 PHYMOD_SYMBOL_FLAG_REGISTER, 16612 "AMS_RX_RX_CTL0r", 16613 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16614 "AMS_RX_RX_CTRL_0", 16615 NULL, 16616 #endif 16617 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16618 0x1c00, /* 7168 */ 16619 0, 16620 #endif 16621 }, 16622 { 16623 BCMI_QTC_XGXS_AMS_RX_RX_CTL1r, 16624 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16625 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 16626 BCMI_QTC_XGXS_AMS_RX_RX_CTL1r_fields, 16627 #else 16628 0, 16629 #endif 16630 #endif 16631 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16632 PHYMOD_SYMBOL_FLAG_REGISTER, 16633 "AMS_RX_RX_CTL1r", 16634 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16635 "AMS_RX_RX_CTRL_1", 16636 NULL, 16637 #endif 16638 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16639 0x1048, /* 4168 */ 16640 0, 16641 #endif 16642 }, 16643 { 16644 BCMI_QTC_XGXS_AMS_RX_RX_CTL2r, 16645 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16646 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 16647 BCMI_QTC_XGXS_AMS_RX_RX_CTL2r_fields, 16648 #else 16649 0, 16650 #endif 16651 #endif 16652 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16653 PHYMOD_SYMBOL_FLAG_REGISTER, 16654 "AMS_RX_RX_CTL2r", 16655 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16656 "AMS_RX_RX_CTRL_2", 16657 NULL, 16658 #endif 16659 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16660 0x7e92, /* 32402 */ 16661 0, 16662 #endif 16663 }, 16664 { 16665 BCMI_QTC_XGXS_AMS_RX_RX_CTL3r, 16666 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16667 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 16668 BCMI_QTC_XGXS_AMS_RX_RX_CTL3r_fields, 16669 #else 16670 0, 16671 #endif 16672 #endif 16673 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16674 PHYMOD_SYMBOL_FLAG_REGISTER, 16675 "AMS_RX_RX_CTL3r", 16676 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16677 "AMS_RX_RX_CTRL_3", 16678 NULL, 16679 #endif 16680 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16681 0x288f, /* 10383 */ 16682 0, 16683 #endif 16684 }, 16685 { 16686 BCMI_QTC_XGXS_AMS_RX_RX_CTL4r, 16687 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16688 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 16689 BCMI_QTC_XGXS_AMS_RX_RX_CTL4r_fields, 16690 #else 16691 0, 16692 #endif 16693 #endif 16694 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16695 PHYMOD_SYMBOL_FLAG_REGISTER, 16696 "AMS_RX_RX_CTL4r", 16697 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16698 "AMS_RX_RX_CTRL_4", 16699 NULL, 16700 #endif 16701 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16702 0x20, /* 32 */ 16703 0, 16704 #endif 16705 }, 16706 { 16707 BCMI_QTC_XGXS_AMS_RX_RX_CTL5r, 16708 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16709 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 16710 BCMI_QTC_XGXS_AMS_RX_RX_CTL5r_fields, 16711 #else 16712 0, 16713 #endif 16714 #endif 16715 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16716 PHYMOD_SYMBOL_FLAG_REGISTER, 16717 "AMS_RX_RX_CTL5r", 16718 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16719 "AMS_RX_RX_CTRL_5", 16720 NULL, 16721 #endif 16722 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16723 0xfa0, /* 4000 */ 16724 0, 16725 #endif 16726 }, 16727 { 16728 BCMI_QTC_XGXS_AMS_RX_RX_CTL6r, 16729 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16730 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 16731 BCMI_QTC_XGXS_AMS_RX_RX_CTL6r_fields, 16732 #else 16733 0, 16734 #endif 16735 #endif 16736 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16737 PHYMOD_SYMBOL_FLAG_REGISTER, 16738 "AMS_RX_RX_CTL6r", 16739 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16740 "AMS_RX_RX_CTRL_6", 16741 NULL, 16742 #endif 16743 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16744 0x1078, /* 4216 */ 16745 0, 16746 #endif 16747 }, 16748 { 16749 BCMI_QTC_XGXS_AMS_RX_RX_CTL7r, 16750 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16751 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 16752 BCMI_QTC_XGXS_AMS_RX_RX_CTL7r_fields, 16753 #else 16754 0, 16755 #endif 16756 #endif 16757 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16758 PHYMOD_SYMBOL_FLAG_REGISTER, 16759 "AMS_RX_RX_CTL7r", 16760 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16761 "AMS_RX_RX_CTRL_7", 16762 NULL, 16763 #endif 16764 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16765 0x130, /* 304 */ 16766 0, 16767 #endif 16768 }, 16769 { 16770 BCMI_QTC_XGXS_AMS_RX_RX_INTr, 16771 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16772 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 16773 BCMI_QTC_XGXS_AMS_RX_RX_INTr_fields, 16774 #else 16775 0, 16776 #endif 16777 #endif 16778 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16779 PHYMOD_SYMBOL_FLAG_REGISTER, 16780 "AMS_RX_RX_INTr", 16781 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16782 NULL, 16783 NULL, 16784 #endif 16785 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16786 0x0, /* 0 */ 16787 0, 16788 #endif 16789 }, 16790 { 16791 BCMI_QTC_XGXS_AMS_RX_RX_STSr, 16792 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16793 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 16794 BCMI_QTC_XGXS_AMS_RX_RX_STSr_fields, 16795 #else 16796 0, 16797 #endif 16798 #endif 16799 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16800 PHYMOD_SYMBOL_FLAG_REGISTER, 16801 "AMS_RX_RX_STSr", 16802 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16803 NULL, 16804 NULL, 16805 #endif 16806 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16807 0x0, /* 0 */ 16808 0, 16809 #endif 16810 }, 16811 { 16812 BCMI_QTC_XGXS_AMS_TX_TX_CTL0r, 16813 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16814 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 16815 BCMI_QTC_XGXS_AMS_TX_TX_CTL0r_fields, 16816 #else 16817 0, 16818 #endif 16819 #endif 16820 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16821 PHYMOD_SYMBOL_FLAG_REGISTER, 16822 "AMS_TX_TX_CTL0r", 16823 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16824 "AMS_TX_TX_CTRL_0", 16825 NULL, 16826 #endif 16827 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16828 0x2800, /* 10240 */ 16829 0, 16830 #endif 16831 }, 16832 { 16833 BCMI_QTC_XGXS_AMS_TX_TX_CTL1r, 16834 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16835 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 16836 BCMI_QTC_XGXS_AMS_TX_TX_CTL1r_fields, 16837 #else 16838 0, 16839 #endif 16840 #endif 16841 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16842 PHYMOD_SYMBOL_FLAG_REGISTER, 16843 "AMS_TX_TX_CTL1r", 16844 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16845 "AMS_TX_TX_CTRL_1", 16846 NULL, 16847 #endif 16848 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16849 0x744, /* 1860 */ 16850 0, 16851 #endif 16852 }, 16853 { 16854 BCMI_QTC_XGXS_AMS_TX_TX_CTL2r, 16855 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16856 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 16857 BCMI_QTC_XGXS_AMS_TX_TX_CTL2r_fields, 16858 #else 16859 0, 16860 #endif 16861 #endif 16862 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16863 PHYMOD_SYMBOL_FLAG_REGISTER, 16864 "AMS_TX_TX_CTL2r", 16865 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16866 "AMS_TX_TX_CTRL_2", 16867 NULL, 16868 #endif 16869 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16870 0x5250, /* 21072 */ 16871 0, 16872 #endif 16873 }, 16874 { 16875 BCMI_QTC_XGXS_AMS_TX_TX_CTL3r, 16876 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16877 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 16878 BCMI_QTC_XGXS_AMS_TX_TX_CTL3r_fields, 16879 #else 16880 0, 16881 #endif 16882 #endif 16883 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16884 PHYMOD_SYMBOL_FLAG_REGISTER, 16885 "AMS_TX_TX_CTL3r", 16886 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16887 "AMS_TX_TX_CTRL_3", 16888 NULL, 16889 #endif 16890 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16891 0x1556, /* 5462 */ 16892 0, 16893 #endif 16894 }, 16895 { 16896 BCMI_QTC_XGXS_AMS_TX_TX_CTL4r, 16897 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16898 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 16899 BCMI_QTC_XGXS_AMS_TX_TX_CTL4r_fields, 16900 #else 16901 0, 16902 #endif 16903 #endif 16904 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16905 PHYMOD_SYMBOL_FLAG_REGISTER, 16906 "AMS_TX_TX_CTL4r", 16907 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16908 "AMS_TX_TX_CTRL_4", 16909 NULL, 16910 #endif 16911 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16912 0x0, /* 0 */ 16913 0, 16914 #endif 16915 }, 16916 { 16917 BCMI_QTC_XGXS_AMS_TX_TX_CTL5r, 16918 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16919 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 16920 BCMI_QTC_XGXS_AMS_TX_TX_CTL5r_fields, 16921 #else 16922 0, 16923 #endif 16924 #endif 16925 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16926 PHYMOD_SYMBOL_FLAG_REGISTER, 16927 "AMS_TX_TX_CTL5r", 16928 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16929 "AMS_TX_TX_CTRL_5", 16930 NULL, 16931 #endif 16932 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16933 0x0, /* 0 */ 16934 0, 16935 #endif 16936 }, 16937 { 16938 BCMI_QTC_XGXS_AMS_TX_TX_CTL6r, 16939 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16940 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 16941 BCMI_QTC_XGXS_AMS_TX_TX_CTL6r_fields, 16942 #else 16943 0, 16944 #endif 16945 #endif 16946 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16947 PHYMOD_SYMBOL_FLAG_REGISTER, 16948 "AMS_TX_TX_CTL6r", 16949 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16950 "AMS_TX_TX_CTRL_6", 16951 NULL, 16952 #endif 16953 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16954 0x1, /* 1 */ 16955 0, 16956 #endif 16957 }, 16958 { 16959 BCMI_QTC_XGXS_AMS_TX_TX_CTL7r, 16960 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16961 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 16962 BCMI_QTC_XGXS_AMS_TX_TX_CTL7r_fields, 16963 #else 16964 0, 16965 #endif 16966 #endif 16967 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16968 PHYMOD_SYMBOL_FLAG_REGISTER, 16969 "AMS_TX_TX_CTL7r", 16970 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16971 "AMS_TX_TX_CTRL_7", 16972 NULL, 16973 #endif 16974 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16975 0xaa0, /* 2720 */ 16976 0, 16977 #endif 16978 }, 16979 { 16980 BCMI_QTC_XGXS_AMS_TX_TX_CTL8r, 16981 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 16982 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 16983 BCMI_QTC_XGXS_AMS_TX_TX_CTL8r_fields, 16984 #else 16985 0, 16986 #endif 16987 #endif 16988 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 16989 PHYMOD_SYMBOL_FLAG_REGISTER, 16990 "AMS_TX_TX_CTL8r", 16991 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 16992 "AMS_TX_TX_CTRL_8", 16993 NULL, 16994 #endif 16995 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 16996 0x0, /* 0 */ 16997 0, 16998 #endif 16999 }, 17000 { 17001 BCMI_QTC_XGXS_AMS_TX_TX_INTr, 17002 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17003 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 17004 BCMI_QTC_XGXS_AMS_TX_TX_INTr_fields, 17005 #else 17006 0, 17007 #endif 17008 #endif 17009 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17010 PHYMOD_SYMBOL_FLAG_REGISTER, 17011 "AMS_TX_TX_INTr", 17012 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17013 NULL, 17014 NULL, 17015 #endif 17016 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17017 0x0, /* 0 */ 17018 0, 17019 #endif 17020 }, 17021 { 17022 BCMI_QTC_XGXS_AMS_TX_TX_STSr, 17023 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17024 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 17025 BCMI_QTC_XGXS_AMS_TX_TX_STSr_fields, 17026 #else 17027 0, 17028 #endif 17029 #endif 17030 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17031 PHYMOD_SYMBOL_FLAG_REGISTER, 17032 "AMS_TX_TX_STSr", 17033 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17034 NULL, 17035 NULL, 17036 #endif 17037 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17038 0x0, /* 0 */ 17039 0, 17040 #endif 17041 }, 17042 { 17043 BCMI_QTC_XGXS_PLL_CTL0r, 17044 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17045 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 17046 BCMI_QTC_XGXS_PLL_CTL0r_fields, 17047 #else 17048 0, 17049 #endif 17050 #endif 17051 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17052 PHYMOD_SYMBOL_FLAG_REGISTER, 17053 "PLL_CTL0r", 17054 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17055 "AMSCOM_PLL_CTRL_0", 17056 NULL, 17057 #endif 17058 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17059 0x2480, /* 9344 */ 17060 0, 17061 #endif 17062 }, 17063 { 17064 BCMI_QTC_XGXS_PLL_CTL1r, 17065 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17066 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 17067 BCMI_QTC_XGXS_PLL_CTL1r_fields, 17068 #else 17069 0, 17070 #endif 17071 #endif 17072 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17073 PHYMOD_SYMBOL_FLAG_REGISTER, 17074 "PLL_CTL1r", 17075 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17076 "AMSCOM_PLL_CTRL_1", 17077 NULL, 17078 #endif 17079 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17080 0x7, /* 7 */ 17081 0, 17082 #endif 17083 }, 17084 { 17085 BCMI_QTC_XGXS_PLL_CTL2r, 17086 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17087 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 17088 BCMI_QTC_XGXS_PLL_CTL2r_fields, 17089 #else 17090 0, 17091 #endif 17092 #endif 17093 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17094 PHYMOD_SYMBOL_FLAG_REGISTER, 17095 "PLL_CTL2r", 17096 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17097 "AMSCOM_PLL_CTRL_2", 17098 NULL, 17099 #endif 17100 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17101 0x80, /* 128 */ 17102 0, 17103 #endif 17104 }, 17105 { 17106 BCMI_QTC_XGXS_PLL_CTL3r, 17107 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17108 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 17109 BCMI_QTC_XGXS_PLL_CTL3r_fields, 17110 #else 17111 0, 17112 #endif 17113 #endif 17114 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17115 PHYMOD_SYMBOL_FLAG_REGISTER, 17116 "PLL_CTL3r", 17117 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17118 "AMSCOM_PLL_CTRL_3", 17119 NULL, 17120 #endif 17121 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17122 0x460e, /* 17934 */ 17123 0, 17124 #endif 17125 }, 17126 { 17127 BCMI_QTC_XGXS_PLL_CTL4r, 17128 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17129 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 17130 BCMI_QTC_XGXS_PLL_CTL4r_fields, 17131 #else 17132 0, 17133 #endif 17134 #endif 17135 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17136 PHYMOD_SYMBOL_FLAG_REGISTER, 17137 "PLL_CTL4r", 17138 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17139 "AMSCOM_PLL_CTRL_4", 17140 NULL, 17141 #endif 17142 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17143 0x501, /* 1281 */ 17144 0, 17145 #endif 17146 }, 17147 { 17148 BCMI_QTC_XGXS_PLL_CTL5r, 17149 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17150 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 17151 BCMI_QTC_XGXS_PLL_CTL5r_fields, 17152 #else 17153 0, 17154 #endif 17155 #endif 17156 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17157 PHYMOD_SYMBOL_FLAG_REGISTER, 17158 "PLL_CTL5r", 17159 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17160 "AMSCOM_PLL_CTRL_5", 17161 NULL, 17162 #endif 17163 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17164 0x1405, /* 5125 */ 17165 0, 17166 #endif 17167 }, 17168 { 17169 BCMI_QTC_XGXS_PLL_CTL6r, 17170 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17171 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 17172 BCMI_QTC_XGXS_PLL_CTL6r_fields, 17173 #else 17174 0, 17175 #endif 17176 #endif 17177 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17178 PHYMOD_SYMBOL_FLAG_REGISTER, 17179 "PLL_CTL6r", 17180 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17181 "AMSCOM_PLL_CTRL_6", 17182 NULL, 17183 #endif 17184 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17185 0x0, /* 0 */ 17186 0, 17187 #endif 17188 }, 17189 { 17190 BCMI_QTC_XGXS_PLL_CTL7r, 17191 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17192 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 17193 BCMI_QTC_XGXS_PLL_CTL7r_fields, 17194 #else 17195 0, 17196 #endif 17197 #endif 17198 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17199 PHYMOD_SYMBOL_FLAG_REGISTER, 17200 "PLL_CTL7r", 17201 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17202 "AMSCOM_PLL_CTRL_7", 17203 NULL, 17204 #endif 17205 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17206 0x0, /* 0 */ 17207 0, 17208 #endif 17209 }, 17210 { 17211 BCMI_QTC_XGXS_PLL_CTL8r, 17212 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17213 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 17214 BCMI_QTC_XGXS_PLL_CTL8r_fields, 17215 #else 17216 0, 17217 #endif 17218 #endif 17219 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17220 PHYMOD_SYMBOL_FLAG_REGISTER, 17221 "PLL_CTL8r", 17222 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17223 "AMSCOM_PLL_CTRL_8", 17224 NULL, 17225 #endif 17226 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17227 0x4442, /* 17474 */ 17228 0, 17229 #endif 17230 }, 17231 { 17232 BCMI_QTC_XGXS_PLL_CTL9r, 17233 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17234 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 17235 BCMI_QTC_XGXS_PLL_CTL9r_fields, 17236 #else 17237 0, 17238 #endif 17239 #endif 17240 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17241 PHYMOD_SYMBOL_FLAG_REGISTER, 17242 "PLL_CTL9r", 17243 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17244 "AMSCOM_PLL_CTRL_9", 17245 NULL, 17246 #endif 17247 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17248 0x5285, /* 21125 */ 17249 0, 17250 #endif 17251 }, 17252 { 17253 BCMI_QTC_XGXS_PLL_CTL_10r, 17254 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17255 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 17256 BCMI_QTC_XGXS_PLL_CTL_10r_fields, 17257 #else 17258 0, 17259 #endif 17260 #endif 17261 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17262 PHYMOD_SYMBOL_FLAG_REGISTER, 17263 "PLL_CTL_10r", 17264 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17265 "AMSCOM_PLL_CTRL_10", 17266 NULL, 17267 #endif 17268 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17269 0x15, /* 21 */ 17270 0, 17271 #endif 17272 }, 17273 { 17274 BCMI_QTC_XGXS_PLL_INTr, 17275 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17276 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 17277 BCMI_QTC_XGXS_PLL_INTr_fields, 17278 #else 17279 0, 17280 #endif 17281 #endif 17282 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17283 PHYMOD_SYMBOL_FLAG_REGISTER, 17284 "PLL_INTr", 17285 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17286 "AMSCOM_PLL_INT", 17287 NULL, 17288 #endif 17289 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17290 0x0, /* 0 */ 17291 0, 17292 #endif 17293 }, 17294 { 17295 BCMI_QTC_XGXS_PLL_STSr, 17296 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17297 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 17298 BCMI_QTC_XGXS_PLL_STSr_fields, 17299 #else 17300 0, 17301 #endif 17302 #endif 17303 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17304 PHYMOD_SYMBOL_FLAG_REGISTER, 17305 "PLL_STSr", 17306 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17307 "AMSCOM_PLL_STS", 17308 NULL, 17309 #endif 17310 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17311 0x0, /* 0 */ 17312 0, 17313 #endif 17314 }, 17315 { 17316 BCMI_QTC_XGXS_SIGDET_CTL0r, 17317 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17318 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 17319 BCMI_QTC_XGXS_SIGDET_CTL0r_fields, 17320 #else 17321 0, 17322 #endif 17323 #endif 17324 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17325 PHYMOD_SYMBOL_FLAG_REGISTER, 17326 "SIGDET_CTL0r", 17327 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17328 "SIGDET_SIGDET_CTRL_0", 17329 NULL, 17330 #endif 17331 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17332 0x5229, /* 21033 */ 17333 0, 17334 #endif 17335 }, 17336 { 17337 BCMI_QTC_XGXS_SIGDET_CTL1r, 17338 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17339 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 17340 BCMI_QTC_XGXS_SIGDET_CTL1r_fields, 17341 #else 17342 0, 17343 #endif 17344 #endif 17345 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17346 PHYMOD_SYMBOL_FLAG_REGISTER, 17347 "SIGDET_CTL1r", 17348 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17349 "SIGDET_SIGDET_CTRL_1", 17350 NULL, 17351 #endif 17352 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17353 0x8, /* 8 */ 17354 0, 17355 #endif 17356 }, 17357 { 17358 BCMI_QTC_XGXS_SIGDET_CTL2r, 17359 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17360 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 17361 BCMI_QTC_XGXS_SIGDET_CTL2r_fields, 17362 #else 17363 0, 17364 #endif 17365 #endif 17366 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17367 PHYMOD_SYMBOL_FLAG_REGISTER, 17368 "SIGDET_CTL2r", 17369 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17370 "SIGDET_SIGDET_CTRL_2", 17371 NULL, 17372 #endif 17373 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17374 0xfd29, /* 64809 */ 17375 0, 17376 #endif 17377 }, 17378 { 17379 BCMI_QTC_XGXS_SIGDET_STS0r, 17380 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17381 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 17382 BCMI_QTC_XGXS_SIGDET_STS0r_fields, 17383 #else 17384 0, 17385 #endif 17386 #endif 17387 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17388 PHYMOD_SYMBOL_FLAG_REGISTER, 17389 "SIGDET_STS0r", 17390 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17391 "SIGDET_SIGDET_STATUS_0", 17392 NULL, 17393 #endif 17394 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17395 0x0, /* 0 */ 17396 0, 17397 #endif 17398 }, 17399 { 17400 BCMI_QTC_XGXS_SIGDET_STS1r, 17401 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17402 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 17403 BCMI_QTC_XGXS_SIGDET_STS1r_fields, 17404 #else 17405 0, 17406 #endif 17407 #endif 17408 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17409 PHYMOD_SYMBOL_FLAG_REGISTER, 17410 "SIGDET_STS1r", 17411 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17412 "SIGDET_SIGDET_STATUS_1", 17413 NULL, 17414 #endif 17415 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17416 0x0, /* 0 */ 17417 0, 17418 #endif 17419 }, 17420 { 17421 BCMI_QTC_XGXS_SIGDET_STS2r, 17422 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17423 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 17424 BCMI_QTC_XGXS_SIGDET_STS2r_fields, 17425 #else 17426 0, 17427 #endif 17428 #endif 17429 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17430 PHYMOD_SYMBOL_FLAG_REGISTER, 17431 "SIGDET_STS2r", 17432 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17433 "SIGDET_SIGDET_STATUS_2", 17434 NULL, 17435 #endif 17436 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17437 0x0, /* 0 */ 17438 0, 17439 #endif 17440 }, 17441 { 17442 BCMI_QTC_XGXS_SIGDET_STS3r, 17443 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17444 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 17445 BCMI_QTC_XGXS_SIGDET_STS3r_fields, 17446 #else 17447 0, 17448 #endif 17449 #endif 17450 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17451 PHYMOD_SYMBOL_FLAG_REGISTER, 17452 "SIGDET_STS3r", 17453 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17454 "SIGDET_SIGDET_STATUS_3", 17455 NULL, 17456 #endif 17457 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17458 0x0, /* 0 */ 17459 0, 17460 #endif 17461 }, 17462 { 17463 BCMI_QTC_XGXS_SIGDET_STS4r, 17464 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17465 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 17466 BCMI_QTC_XGXS_SIGDET_STS4r_fields, 17467 #else 17468 0, 17469 #endif 17470 #endif 17471 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17472 PHYMOD_SYMBOL_FLAG_REGISTER, 17473 "SIGDET_STS4r", 17474 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17475 "SIGDET_SIGDET_STATUS_4", 17476 NULL, 17477 #endif 17478 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17479 0x9, /* 9 */ 17480 0, 17481 #endif 17482 }, 17483 { 17484 BCMI_QTC_XGXS_TLB_RX_PRBS_CHK_CNT_CFGr, 17485 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17486 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 17487 BCMI_QTC_XGXS_TLB_RX_PRBS_CHK_CNT_CFGr_fields, 17488 #else 17489 0, 17490 #endif 17491 #endif 17492 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17493 PHYMOD_SYMBOL_FLAG_REGISTER, 17494 "TLB_RX_PRBS_CHK_CNT_CFGr", 17495 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17496 "TLB_RX_PRBS_CHK_CNT_CONFIG", 17497 NULL, 17498 #endif 17499 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17500 0x602, /* 1538 */ 17501 0, 17502 #endif 17503 }, 17504 { 17505 BCMI_QTC_XGXS_TLB_RX_PRBS_CHK_CFGr, 17506 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17507 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 17508 BCMI_QTC_XGXS_TLB_RX_PRBS_CHK_CFGr_fields, 17509 #else 17510 0, 17511 #endif 17512 #endif 17513 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17514 PHYMOD_SYMBOL_FLAG_REGISTER, 17515 "TLB_RX_PRBS_CHK_CFGr", 17516 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17517 "TLB_RX_PRBS_CHK_CONFIG", 17518 NULL, 17519 #endif 17520 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17521 0x2a, /* 42 */ 17522 0, 17523 #endif 17524 }, 17525 { 17526 BCMI_QTC_XGXS_TLB_RX_DIG_LPBK_CFGr, 17527 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17528 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 17529 BCMI_QTC_XGXS_TLB_RX_DIG_LPBK_CFGr_fields, 17530 #else 17531 0, 17532 #endif 17533 #endif 17534 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17535 PHYMOD_SYMBOL_FLAG_REGISTER, 17536 "TLB_RX_DIG_LPBK_CFGr", 17537 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17538 "TLB_RX_DIG_LPBK_CONFIG", 17539 NULL, 17540 #endif 17541 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17542 0xe, /* 14 */ 17543 0, 17544 #endif 17545 }, 17546 { 17547 BCMI_QTC_XGXS_TLB_RX_TLB_RX_MISC_CFGr, 17548 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17549 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 17550 BCMI_QTC_XGXS_TLB_RX_TLB_RX_MISC_CFGr_fields, 17551 #else 17552 0, 17553 #endif 17554 #endif 17555 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17556 PHYMOD_SYMBOL_FLAG_REGISTER, 17557 "TLB_RX_TLB_RX_MISC_CFGr", 17558 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17559 "TLB_RX_TLB_RX_MISC_CONFIG", 17560 NULL, 17561 #endif 17562 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17563 0x0, /* 0 */ 17564 0, 17565 #endif 17566 }, 17567 { 17568 BCMI_QTC_XGXS_TLB_RX_PRBS_CHK_EN_TMR_CTLr, 17569 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17570 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 17571 BCMI_QTC_XGXS_TLB_RX_PRBS_CHK_EN_TMR_CTLr_fields, 17572 #else 17573 0, 17574 #endif 17575 #endif 17576 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17577 PHYMOD_SYMBOL_FLAG_REGISTER, 17578 "TLB_RX_PRBS_CHK_EN_TMR_CTLr", 17579 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17580 "TLB_RX_PRBS_CHK_EN_TIMER_CONTROL", 17581 NULL, 17582 #endif 17583 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17584 0x0, /* 0 */ 17585 0, 17586 #endif 17587 }, 17588 { 17589 BCMI_QTC_XGXS_TLB_RX_PRBS_CHK_BURST_ERR_CNT_STSr, 17590 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17591 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 17592 BCMI_QTC_XGXS_TLB_RX_PRBS_CHK_BURST_ERR_CNT_STSr_fields, 17593 #else 17594 0, 17595 #endif 17596 #endif 17597 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17598 PHYMOD_SYMBOL_FLAG_REGISTER, 17599 "TLB_RX_PRBS_CHK_BURST_ERR_CNT_STSr", 17600 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17601 "TLB_RX_PRBS_CHK_BURST_ERR_CNT_STATUS", 17602 NULL, 17603 #endif 17604 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17605 0x0, /* 0 */ 17606 0, 17607 #endif 17608 }, 17609 { 17610 BCMI_QTC_XGXS_TLB_RX_DBG_PMD_RX_LOCK_STSr, 17611 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17612 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 17613 BCMI_QTC_XGXS_TLB_RX_DBG_PMD_RX_LOCK_STSr_fields, 17614 #else 17615 0, 17616 #endif 17617 #endif 17618 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17619 PHYMOD_SYMBOL_FLAG_REGISTER, 17620 "TLB_RX_DBG_PMD_RX_LOCK_STSr", 17621 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17622 "TLB_RX_DBG_PMD_RX_LOCK_STATUS", 17623 NULL, 17624 #endif 17625 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17626 0x0, /* 0 */ 17627 0, 17628 #endif 17629 }, 17630 { 17631 BCMI_QTC_XGXS_TLB_RX_UC_PMD_RX_LOCK_STSr, 17632 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17633 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 17634 BCMI_QTC_XGXS_TLB_RX_UC_PMD_RX_LOCK_STSr_fields, 17635 #else 17636 0, 17637 #endif 17638 #endif 17639 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17640 PHYMOD_SYMBOL_FLAG_REGISTER, 17641 "TLB_RX_UC_PMD_RX_LOCK_STSr", 17642 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17643 "TLB_RX_UC_PMD_RX_LOCK_STATUS", 17644 NULL, 17645 #endif 17646 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17647 0x0, /* 0 */ 17648 0, 17649 #endif 17650 }, 17651 { 17652 BCMI_QTC_XGXS_TLB_RX_DIG_LPBK_PD_STSr, 17653 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17654 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 17655 BCMI_QTC_XGXS_TLB_RX_DIG_LPBK_PD_STSr_fields, 17656 #else 17657 0, 17658 #endif 17659 #endif 17660 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17661 PHYMOD_SYMBOL_FLAG_REGISTER, 17662 "TLB_RX_DIG_LPBK_PD_STSr", 17663 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17664 "TLB_RX_DIG_LPBK_PD_STATUS", 17665 NULL, 17666 #endif 17667 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17668 0x2, /* 2 */ 17669 0, 17670 #endif 17671 }, 17672 { 17673 BCMI_QTC_XGXS_TLB_RX_PRBS_CHK_LOCK_STSr, 17674 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17675 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 17676 BCMI_QTC_XGXS_TLB_RX_PRBS_CHK_LOCK_STSr_fields, 17677 #else 17678 0, 17679 #endif 17680 #endif 17681 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17682 PHYMOD_SYMBOL_FLAG_REGISTER, 17683 "TLB_RX_PRBS_CHK_LOCK_STSr", 17684 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17685 "TLB_RX_PRBS_CHK_LOCK_STATUS", 17686 NULL, 17687 #endif 17688 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17689 0x0, /* 0 */ 17690 0, 17691 #endif 17692 }, 17693 { 17694 BCMI_QTC_XGXS_TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr, 17695 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17696 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 17697 BCMI_QTC_XGXS_TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr_fields, 17698 #else 17699 0, 17700 #endif 17701 #endif 17702 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17703 PHYMOD_SYMBOL_FLAG_REGISTER, 17704 "TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr", 17705 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17706 "TLB_RX_PRBS_CHK_ERR_CNT_MSB_STATUS", 17707 NULL, 17708 #endif 17709 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17710 0x8000, /* 32768 */ 17711 0, 17712 #endif 17713 }, 17714 { 17715 BCMI_QTC_XGXS_TLB_RX_PRBS_CHK_ERR_CNT_LSB_STSr, 17716 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17717 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 17718 BCMI_QTC_XGXS_TLB_RX_PRBS_CHK_ERR_CNT_LSB_STSr_fields, 17719 #else 17720 0, 17721 #endif 17722 #endif 17723 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17724 PHYMOD_SYMBOL_FLAG_REGISTER, 17725 "TLB_RX_PRBS_CHK_ERR_CNT_LSB_STSr", 17726 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17727 "TLB_RX_PRBS_CHK_ERR_CNT_LSB_STATUS", 17728 NULL, 17729 #endif 17730 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17731 0x0, /* 0 */ 17732 0, 17733 #endif 17734 }, 17735 { 17736 BCMI_QTC_XGXS_TLB_RX_PMD_RX_LOCK_STSr, 17737 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17738 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 17739 BCMI_QTC_XGXS_TLB_RX_PMD_RX_LOCK_STSr_fields, 17740 #else 17741 0, 17742 #endif 17743 #endif 17744 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17745 PHYMOD_SYMBOL_FLAG_REGISTER, 17746 "TLB_RX_PMD_RX_LOCK_STSr", 17747 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17748 "TLB_RX_PMD_RX_LOCK_STATUS", 17749 NULL, 17750 #endif 17751 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17752 0x0, /* 0 */ 17753 0, 17754 #endif 17755 }, 17756 { 17757 BCMI_QTC_XGXS_TLB_TX_PATGEN_CFGr, 17758 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17759 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 17760 BCMI_QTC_XGXS_TLB_TX_PATGEN_CFGr_fields, 17761 #else 17762 0, 17763 #endif 17764 #endif 17765 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17766 PHYMOD_SYMBOL_FLAG_REGISTER, 17767 "TLB_TX_PATGEN_CFGr", 17768 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17769 "TLB_TX_PATT_GEN_CONFIG", 17770 NULL, 17771 #endif 17772 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17773 0xb000, /* 45056 */ 17774 0, 17775 #endif 17776 }, 17777 { 17778 BCMI_QTC_XGXS_TLB_TX_PRBS_GEN_CFGr, 17779 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17780 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 17781 BCMI_QTC_XGXS_TLB_TX_PRBS_GEN_CFGr_fields, 17782 #else 17783 0, 17784 #endif 17785 #endif 17786 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17787 PHYMOD_SYMBOL_FLAG_REGISTER, 17788 "TLB_TX_PRBS_GEN_CFGr", 17789 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17790 "TLB_TX_PRBS_GEN_CONFIG", 17791 NULL, 17792 #endif 17793 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17794 0xa, /* 10 */ 17795 0, 17796 #endif 17797 }, 17798 { 17799 BCMI_QTC_XGXS_TLB_TX_RMT_LPBK_CFGr, 17800 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17801 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 17802 BCMI_QTC_XGXS_TLB_TX_RMT_LPBK_CFGr_fields, 17803 #else 17804 0, 17805 #endif 17806 #endif 17807 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17808 PHYMOD_SYMBOL_FLAG_REGISTER, 17809 "TLB_TX_RMT_LPBK_CFGr", 17810 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17811 "TLB_TX_RMT_LPBK_CONFIG", 17812 NULL, 17813 #endif 17814 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17815 0x2, /* 2 */ 17816 0, 17817 #endif 17818 }, 17819 { 17820 BCMI_QTC_XGXS_TLB_TX_TLB_TX_MISC_CFGr, 17821 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17822 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 17823 BCMI_QTC_XGXS_TLB_TX_TLB_TX_MISC_CFGr_fields, 17824 #else 17825 0, 17826 #endif 17827 #endif 17828 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17829 PHYMOD_SYMBOL_FLAG_REGISTER, 17830 "TLB_TX_TLB_TX_MISC_CFGr", 17831 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17832 "TLB_TX_TLB_TX_MISC_CONFIG", 17833 NULL, 17834 #endif 17835 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17836 0x0, /* 0 */ 17837 0, 17838 #endif 17839 }, 17840 { 17841 BCMI_QTC_XGXS_TLB_TX_RMT_LPBK_PD_STSr, 17842 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17843 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 17844 BCMI_QTC_XGXS_TLB_TX_RMT_LPBK_PD_STSr_fields, 17845 #else 17846 0, 17847 #endif 17848 #endif 17849 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17850 PHYMOD_SYMBOL_FLAG_REGISTER, 17851 "TLB_TX_RMT_LPBK_PD_STSr", 17852 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17853 "TLB_TX_RMT_LPBK_PD_STATUS", 17854 NULL, 17855 #endif 17856 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17857 0x2, /* 2 */ 17858 0, 17859 #endif 17860 }, 17861 { 17862 BCMI_QTC_XGXS_REVID0r, 17863 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17864 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 17865 BCMI_QTC_XGXS_REVID0r_fields, 17866 #else 17867 0, 17868 #endif 17869 #endif 17870 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17871 PHYMOD_SYMBOL_FLAG_REGISTER, 17872 "REVID0r", 17873 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17874 "DIGCOM_REVID0", 17875 NULL, 17876 #endif 17877 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17878 0x363, /* 867 */ 17879 0, 17880 #endif 17881 }, 17882 { 17883 BCMI_QTC_XGXS_RST_CTL_PMDr, 17884 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17885 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 17886 BCMI_QTC_XGXS_RST_CTL_PMDr_fields, 17887 #else 17888 0, 17889 #endif 17890 #endif 17891 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17892 PHYMOD_SYMBOL_FLAG_REGISTER, 17893 "RST_CTL_PMDr", 17894 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17895 "DIGCOM_RESET_CONTROL_PMD", 17896 NULL, 17897 #endif 17898 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17899 0x1, /* 1 */ 17900 0, 17901 #endif 17902 }, 17903 { 17904 BCMI_QTC_XGXS_RST_CTL_CORE_DPr, 17905 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17906 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 17907 BCMI_QTC_XGXS_RST_CTL_CORE_DPr_fields, 17908 #else 17909 0, 17910 #endif 17911 #endif 17912 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17913 PHYMOD_SYMBOL_FLAG_REGISTER, 17914 "RST_CTL_CORE_DPr", 17915 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17916 "DIGCOM_RESET_CONTROL_CORE_DP", 17917 NULL, 17918 #endif 17919 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17920 0x0, /* 0 */ 17921 0, 17922 #endif 17923 }, 17924 { 17925 BCMI_QTC_XGXS_MASKDATAr, 17926 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17927 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 17928 BCMI_QTC_XGXS_MASKDATAr_fields, 17929 #else 17930 0, 17931 #endif 17932 #endif 17933 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17934 PHYMOD_SYMBOL_FLAG_REGISTER, 17935 "MASKDATAr", 17936 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17937 "DIGCOM_MASKDATA_REG", 17938 NULL, 17939 #endif 17940 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17941 0x0, /* 0 */ 17942 0, 17943 #endif 17944 }, 17945 { 17946 BCMI_QTC_XGXS_TOP_USER_CTL0r, 17947 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17948 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 17949 BCMI_QTC_XGXS_TOP_USER_CTL0r_fields, 17950 #else 17951 0, 17952 #endif 17953 #endif 17954 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17955 PHYMOD_SYMBOL_FLAG_REGISTER, 17956 "TOP_USER_CTL0r", 17957 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17958 "DIGCOM_TOP_USER_CONTROL_0", 17959 NULL, 17960 #endif 17961 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17962 0x271, /* 625 */ 17963 0, 17964 #endif 17965 }, 17966 { 17967 BCMI_QTC_XGXS_UC_ACK_CORE_CTLr, 17968 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17969 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 17970 BCMI_QTC_XGXS_UC_ACK_CORE_CTLr_fields, 17971 #else 17972 0, 17973 #endif 17974 #endif 17975 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17976 PHYMOD_SYMBOL_FLAG_REGISTER, 17977 "UC_ACK_CORE_CTLr", 17978 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 17979 "DIGCOM_UC_ACK_CORE_CONTROL", 17980 NULL, 17981 #endif 17982 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 17983 0x0, /* 0 */ 17984 0, 17985 #endif 17986 }, 17987 { 17988 BCMI_QTC_XGXS_CORE_RST_OCC_CTLr, 17989 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 17990 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 17991 BCMI_QTC_XGXS_CORE_RST_OCC_CTLr_fields, 17992 #else 17993 0, 17994 #endif 17995 #endif 17996 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 17997 PHYMOD_SYMBOL_FLAG_REGISTER, 17998 "CORE_RST_OCC_CTLr", 17999 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18000 "DIGCOM_CORE_REG_RESET_OCCURRED_CONTROL", 18001 NULL, 18002 #endif 18003 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18004 0x1, /* 1 */ 18005 0, 18006 #endif 18007 }, 18008 { 18009 BCMI_QTC_XGXS_RST_SEQ_TMR_CTLr, 18010 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18011 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 18012 BCMI_QTC_XGXS_RST_SEQ_TMR_CTLr_fields, 18013 #else 18014 0, 18015 #endif 18016 #endif 18017 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18018 PHYMOD_SYMBOL_FLAG_REGISTER, 18019 "RST_SEQ_TMR_CTLr", 18020 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18021 "DIGCOM_RST_SEQ_TIMER_CONTROL", 18022 NULL, 18023 #endif 18024 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18025 0x8604, /* 34308 */ 18026 0, 18027 #endif 18028 }, 18029 { 18030 BCMI_QTC_XGXS_CORE_DP_RST_ST_STSr, 18031 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18032 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 18033 BCMI_QTC_XGXS_CORE_DP_RST_ST_STSr_fields, 18034 #else 18035 0, 18036 #endif 18037 #endif 18038 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18039 PHYMOD_SYMBOL_FLAG_REGISTER, 18040 "CORE_DP_RST_ST_STSr", 18041 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18042 "DIGCOM_CORE_DP_RESET_STATE_STATUS", 18043 NULL, 18044 #endif 18045 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18046 0x7, /* 7 */ 18047 0, 18048 #endif 18049 }, 18050 { 18051 BCMI_QTC_XGXS_PMD_CORE_MODE_STSr, 18052 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18053 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 18054 BCMI_QTC_XGXS_PMD_CORE_MODE_STSr_fields, 18055 #else 18056 0, 18057 #endif 18058 #endif 18059 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18060 PHYMOD_SYMBOL_FLAG_REGISTER, 18061 "PMD_CORE_MODE_STSr", 18062 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18063 "DIGCOM_PMD_CORE_MODE_STATUS", 18064 NULL, 18065 #endif 18066 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18067 0x0, /* 0 */ 18068 0, 18069 #endif 18070 }, 18071 { 18072 BCMI_QTC_XGXS_REVID1r, 18073 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18074 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 18075 BCMI_QTC_XGXS_REVID1r_fields, 18076 #else 18077 0, 18078 #endif 18079 #endif 18080 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18081 PHYMOD_SYMBOL_FLAG_REGISTER, 18082 "REVID1r", 18083 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18084 "DIGCOM_REVID1", 18085 NULL, 18086 #endif 18087 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18088 0x403c, /* 16444 */ 18089 0, 18090 #endif 18091 }, 18092 { 18093 BCMI_QTC_XGXS_REVID2r, 18094 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18095 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 18096 BCMI_QTC_XGXS_REVID2r_fields, 18097 #else 18098 0, 18099 #endif 18100 #endif 18101 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18102 PHYMOD_SYMBOL_FLAG_REGISTER, 18103 "REVID2r", 18104 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18105 "DIGCOM_REVID2", 18106 NULL, 18107 #endif 18108 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18109 0x0, /* 0 */ 18110 0, 18111 #endif 18112 }, 18113 { 18114 BCMI_QTC_XGXS_PATGEN_SEQ0r, 18115 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18116 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 18117 BCMI_QTC_XGXS_PATGEN_SEQ0r_fields, 18118 #else 18119 0, 18120 #endif 18121 #endif 18122 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18123 PHYMOD_SYMBOL_FLAG_REGISTER, 18124 "PATGEN_SEQ0r", 18125 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18126 "PATT_GEN_PATT_GEN_SEQ_0", 18127 NULL, 18128 #endif 18129 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18130 0xff00, /* 65280 */ 18131 0, 18132 #endif 18133 }, 18134 { 18135 BCMI_QTC_XGXS_PATGEN_SEQ1r, 18136 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18137 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 18138 BCMI_QTC_XGXS_PATGEN_SEQ1r_fields, 18139 #else 18140 0, 18141 #endif 18142 #endif 18143 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18144 PHYMOD_SYMBOL_FLAG_REGISTER, 18145 "PATGEN_SEQ1r", 18146 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18147 "PATT_GEN_PATT_GEN_SEQ_1", 18148 NULL, 18149 #endif 18150 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18151 0xff00, /* 65280 */ 18152 0, 18153 #endif 18154 }, 18155 { 18156 BCMI_QTC_XGXS_PATGEN_SEQ2r, 18157 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18158 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 18159 BCMI_QTC_XGXS_PATGEN_SEQ2r_fields, 18160 #else 18161 0, 18162 #endif 18163 #endif 18164 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18165 PHYMOD_SYMBOL_FLAG_REGISTER, 18166 "PATGEN_SEQ2r", 18167 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18168 "PATT_GEN_PATT_GEN_SEQ_2", 18169 NULL, 18170 #endif 18171 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18172 0xff00, /* 65280 */ 18173 0, 18174 #endif 18175 }, 18176 { 18177 BCMI_QTC_XGXS_PATGEN_SEQ3r, 18178 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18179 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 18180 BCMI_QTC_XGXS_PATGEN_SEQ3r_fields, 18181 #else 18182 0, 18183 #endif 18184 #endif 18185 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18186 PHYMOD_SYMBOL_FLAG_REGISTER, 18187 "PATGEN_SEQ3r", 18188 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18189 "PATT_GEN_PATT_GEN_SEQ_3", 18190 NULL, 18191 #endif 18192 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18193 0xff00, /* 65280 */ 18194 0, 18195 #endif 18196 }, 18197 { 18198 BCMI_QTC_XGXS_PATGEN_SEQ4r, 18199 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18200 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 18201 BCMI_QTC_XGXS_PATGEN_SEQ4r_fields, 18202 #else 18203 0, 18204 #endif 18205 #endif 18206 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18207 PHYMOD_SYMBOL_FLAG_REGISTER, 18208 "PATGEN_SEQ4r", 18209 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18210 "PATT_GEN_PATT_GEN_SEQ_4", 18211 NULL, 18212 #endif 18213 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18214 0xff00, /* 65280 */ 18215 0, 18216 #endif 18217 }, 18218 { 18219 BCMI_QTC_XGXS_PATGEN_SEQ5r, 18220 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18221 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 18222 BCMI_QTC_XGXS_PATGEN_SEQ5r_fields, 18223 #else 18224 0, 18225 #endif 18226 #endif 18227 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18228 PHYMOD_SYMBOL_FLAG_REGISTER, 18229 "PATGEN_SEQ5r", 18230 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18231 "PATT_GEN_PATT_GEN_SEQ_5", 18232 NULL, 18233 #endif 18234 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18235 0xff00, /* 65280 */ 18236 0, 18237 #endif 18238 }, 18239 { 18240 BCMI_QTC_XGXS_PATGEN_SEQ6r, 18241 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18242 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 18243 BCMI_QTC_XGXS_PATGEN_SEQ6r_fields, 18244 #else 18245 0, 18246 #endif 18247 #endif 18248 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18249 PHYMOD_SYMBOL_FLAG_REGISTER, 18250 "PATGEN_SEQ6r", 18251 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18252 "PATT_GEN_PATT_GEN_SEQ_6", 18253 NULL, 18254 #endif 18255 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18256 0xff00, /* 65280 */ 18257 0, 18258 #endif 18259 }, 18260 { 18261 BCMI_QTC_XGXS_PATGEN_SEQ7r, 18262 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18263 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 18264 BCMI_QTC_XGXS_PATGEN_SEQ7r_fields, 18265 #else 18266 0, 18267 #endif 18268 #endif 18269 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18270 PHYMOD_SYMBOL_FLAG_REGISTER, 18271 "PATGEN_SEQ7r", 18272 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18273 "PATT_GEN_PATT_GEN_SEQ_7", 18274 NULL, 18275 #endif 18276 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18277 0xff00, /* 65280 */ 18278 0, 18279 #endif 18280 }, 18281 { 18282 BCMI_QTC_XGXS_PATGEN_SEQ8r, 18283 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18284 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 18285 BCMI_QTC_XGXS_PATGEN_SEQ8r_fields, 18286 #else 18287 0, 18288 #endif 18289 #endif 18290 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18291 PHYMOD_SYMBOL_FLAG_REGISTER, 18292 "PATGEN_SEQ8r", 18293 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18294 "PATT_GEN_PATT_GEN_SEQ_8", 18295 NULL, 18296 #endif 18297 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18298 0xff00, /* 65280 */ 18299 0, 18300 #endif 18301 }, 18302 { 18303 BCMI_QTC_XGXS_PATGEN_SEQ9r, 18304 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18305 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 18306 BCMI_QTC_XGXS_PATGEN_SEQ9r_fields, 18307 #else 18308 0, 18309 #endif 18310 #endif 18311 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18312 PHYMOD_SYMBOL_FLAG_REGISTER, 18313 "PATGEN_SEQ9r", 18314 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18315 "PATT_GEN_PATT_GEN_SEQ_9", 18316 NULL, 18317 #endif 18318 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18319 0xff00, /* 65280 */ 18320 0, 18321 #endif 18322 }, 18323 { 18324 BCMI_QTC_XGXS_PATGEN_SEQ_10r, 18325 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18326 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 18327 BCMI_QTC_XGXS_PATGEN_SEQ_10r_fields, 18328 #else 18329 0, 18330 #endif 18331 #endif 18332 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18333 PHYMOD_SYMBOL_FLAG_REGISTER, 18334 "PATGEN_SEQ_10r", 18335 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18336 "PATT_GEN_PATT_GEN_SEQ_10", 18337 NULL, 18338 #endif 18339 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18340 0xff00, /* 65280 */ 18341 0, 18342 #endif 18343 }, 18344 { 18345 BCMI_QTC_XGXS_PATGEN_SEQ_11r, 18346 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18347 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 18348 BCMI_QTC_XGXS_PATGEN_SEQ_11r_fields, 18349 #else 18350 0, 18351 #endif 18352 #endif 18353 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18354 PHYMOD_SYMBOL_FLAG_REGISTER, 18355 "PATGEN_SEQ_11r", 18356 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18357 "PATT_GEN_PATT_GEN_SEQ_11", 18358 NULL, 18359 #endif 18360 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18361 0xff00, /* 65280 */ 18362 0, 18363 #endif 18364 }, 18365 { 18366 BCMI_QTC_XGXS_PATGEN_SEQ_12r, 18367 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18368 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 18369 BCMI_QTC_XGXS_PATGEN_SEQ_12r_fields, 18370 #else 18371 0, 18372 #endif 18373 #endif 18374 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18375 PHYMOD_SYMBOL_FLAG_REGISTER, 18376 "PATGEN_SEQ_12r", 18377 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18378 "PATT_GEN_PATT_GEN_SEQ_12", 18379 NULL, 18380 #endif 18381 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18382 0xff00, /* 65280 */ 18383 0, 18384 #endif 18385 }, 18386 { 18387 BCMI_QTC_XGXS_PATGEN_SEQ_13r, 18388 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18389 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 18390 BCMI_QTC_XGXS_PATGEN_SEQ_13r_fields, 18391 #else 18392 0, 18393 #endif 18394 #endif 18395 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18396 PHYMOD_SYMBOL_FLAG_REGISTER, 18397 "PATGEN_SEQ_13r", 18398 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18399 "PATT_GEN_PATT_GEN_SEQ_13", 18400 NULL, 18401 #endif 18402 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18403 0xff00, /* 65280 */ 18404 0, 18405 #endif 18406 }, 18407 { 18408 BCMI_QTC_XGXS_PATGEN_SEQ_14r, 18409 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18410 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 18411 BCMI_QTC_XGXS_PATGEN_SEQ_14r_fields, 18412 #else 18413 0, 18414 #endif 18415 #endif 18416 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18417 PHYMOD_SYMBOL_FLAG_REGISTER, 18418 "PATGEN_SEQ_14r", 18419 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18420 "PATT_GEN_PATT_GEN_SEQ_14", 18421 NULL, 18422 #endif 18423 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18424 0xff00, /* 65280 */ 18425 0, 18426 #endif 18427 }, 18428 { 18429 BCMI_QTC_XGXS_TXFIR_TAP_CTL0r, 18430 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18431 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 18432 BCMI_QTC_XGXS_TXFIR_TAP_CTL0r_fields, 18433 #else 18434 0, 18435 #endif 18436 #endif 18437 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18438 PHYMOD_SYMBOL_FLAG_REGISTER, 18439 "TXFIR_TAP_CTL0r", 18440 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18441 "TX_FED_TXFIR_TAP_CONTROL0", 18442 NULL, 18443 #endif 18444 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18445 0x0, /* 0 */ 18446 0, 18447 #endif 18448 }, 18449 { 18450 BCMI_QTC_XGXS_TXFIR_MISC_CTL0r, 18451 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18452 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 18453 BCMI_QTC_XGXS_TXFIR_MISC_CTL0r_fields, 18454 #else 18455 0, 18456 #endif 18457 #endif 18458 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18459 PHYMOD_SYMBOL_FLAG_REGISTER, 18460 "TXFIR_MISC_CTL0r", 18461 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18462 "TX_FED_MISC_CONTROL0", 18463 NULL, 18464 #endif 18465 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18466 0x20, /* 32 */ 18467 0, 18468 #endif 18469 }, 18470 { 18471 BCMI_QTC_XGXS_TXFIR_MISC_STS0r, 18472 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18473 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 18474 BCMI_QTC_XGXS_TXFIR_MISC_STS0r_fields, 18475 #else 18476 0, 18477 #endif 18478 #endif 18479 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18480 PHYMOD_SYMBOL_FLAG_REGISTER, 18481 "TXFIR_MISC_STS0r", 18482 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18483 "TX_FED_MISC_STATUS0", 18484 NULL, 18485 #endif 18486 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18487 0x3, /* 3 */ 18488 0, 18489 #endif 18490 }, 18491 { 18492 BCMI_QTC_XGXS_TXFIR_UC_CTL0r, 18493 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18494 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 18495 BCMI_QTC_XGXS_TXFIR_UC_CTL0r_fields, 18496 #else 18497 0, 18498 #endif 18499 #endif 18500 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18501 PHYMOD_SYMBOL_FLAG_REGISTER, 18502 "TXFIR_UC_CTL0r", 18503 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18504 "TX_FED_MICRO_CONTROL0", 18505 NULL, 18506 #endif 18507 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18508 0xc160, /* 49504 */ 18509 0, 18510 #endif 18511 }, 18512 { 18513 BCMI_QTC_XGXS_TXFIR_POST2_AFE_CTL0r, 18514 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18515 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 18516 BCMI_QTC_XGXS_TXFIR_POST2_AFE_CTL0r_fields, 18517 #else 18518 0, 18519 #endif 18520 #endif 18521 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18522 PHYMOD_SYMBOL_FLAG_REGISTER, 18523 "TXFIR_POST2_AFE_CTL0r", 18524 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18525 "TX_FED_POST2_AFE_CONTROL0", 18526 NULL, 18527 #endif 18528 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18529 0xa0, /* 160 */ 18530 0, 18531 #endif 18532 }, 18533 { 18534 BCMI_QTC_XGXS_TXFIR_POST1_AFE_CTL0r, 18535 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18536 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 18537 BCMI_QTC_XGXS_TXFIR_POST1_AFE_CTL0r_fields, 18538 #else 18539 0, 18540 #endif 18541 #endif 18542 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18543 PHYMOD_SYMBOL_FLAG_REGISTER, 18544 "TXFIR_POST1_AFE_CTL0r", 18545 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18546 "TX_FED_POST1_AFE_CONTROL0", 18547 NULL, 18548 #endif 18549 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18550 0x2a0, /* 672 */ 18551 0, 18552 #endif 18553 }, 18554 { 18555 BCMI_QTC_XGXS_TXFIR_POST1PRE_AFE_CTL0r, 18556 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18557 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 18558 BCMI_QTC_XGXS_TXFIR_POST1PRE_AFE_CTL0r_fields, 18559 #else 18560 0, 18561 #endif 18562 #endif 18563 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18564 PHYMOD_SYMBOL_FLAG_REGISTER, 18565 "TXFIR_POST1PRE_AFE_CTL0r", 18566 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18567 "TX_FED_POST1PRE_AFE_CONTROL0", 18568 NULL, 18569 #endif 18570 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18571 0x4000, /* 16384 */ 18572 0, 18573 #endif 18574 }, 18575 { 18576 BCMI_QTC_XGXS_TXFIR_DC_LEVEL_AFE_CTL0r, 18577 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18578 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 18579 BCMI_QTC_XGXS_TXFIR_DC_LEVEL_AFE_CTL0r_fields, 18580 #else 18581 0, 18582 #endif 18583 #endif 18584 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18585 PHYMOD_SYMBOL_FLAG_REGISTER, 18586 "TXFIR_DC_LEVEL_AFE_CTL0r", 18587 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18588 "TX_FED_DC_LEVEL_AFE_CONTROL0", 18589 NULL, 18590 #endif 18591 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18592 0xf, /* 15 */ 18593 0, 18594 #endif 18595 }, 18596 { 18597 BCMI_QTC_XGXS_PLL_CALCTL0r, 18598 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18599 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 18600 BCMI_QTC_XGXS_PLL_CALCTL0r_fields, 18601 #else 18602 0, 18603 #endif 18604 #endif 18605 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18606 PHYMOD_SYMBOL_FLAG_REGISTER, 18607 "PLL_CALCTL0r", 18608 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18609 "PLL_CAL_PLL_CALCTL_0", 18610 NULL, 18611 #endif 18612 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18613 0x1ffa, /* 8186 */ 18614 0, 18615 #endif 18616 }, 18617 { 18618 BCMI_QTC_XGXS_PLL_CALCTL1r, 18619 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18620 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 18621 BCMI_QTC_XGXS_PLL_CALCTL1r_fields, 18622 #else 18623 0, 18624 #endif 18625 #endif 18626 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18627 PHYMOD_SYMBOL_FLAG_REGISTER, 18628 "PLL_CALCTL1r", 18629 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18630 "PLL_CAL_PLL_CALCTL_1", 18631 NULL, 18632 #endif 18633 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18634 0xfff0, /* 65520 */ 18635 0, 18636 #endif 18637 }, 18638 { 18639 BCMI_QTC_XGXS_PLL_CALCTL2r, 18640 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18641 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 18642 BCMI_QTC_XGXS_PLL_CALCTL2r_fields, 18643 #else 18644 0, 18645 #endif 18646 #endif 18647 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18648 PHYMOD_SYMBOL_FLAG_REGISTER, 18649 "PLL_CALCTL2r", 18650 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18651 "PLL_CAL_PLL_CALCTL_2", 18652 NULL, 18653 #endif 18654 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18655 0xfff, /* 4095 */ 18656 0, 18657 #endif 18658 }, 18659 { 18660 BCMI_QTC_XGXS_PLL_CALCTL3r, 18661 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18662 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 18663 BCMI_QTC_XGXS_PLL_CALCTL3r_fields, 18664 #else 18665 0, 18666 #endif 18667 #endif 18668 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18669 PHYMOD_SYMBOL_FLAG_REGISTER, 18670 "PLL_CALCTL3r", 18671 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18672 "PLL_CAL_PLL_CALCTL_3", 18673 NULL, 18674 #endif 18675 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18676 0x1007, /* 4103 */ 18677 0, 18678 #endif 18679 }, 18680 { 18681 BCMI_QTC_XGXS_PLL_CALCTL4r, 18682 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18683 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 18684 BCMI_QTC_XGXS_PLL_CALCTL4r_fields, 18685 #else 18686 0, 18687 #endif 18688 #endif 18689 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18690 PHYMOD_SYMBOL_FLAG_REGISTER, 18691 "PLL_CALCTL4r", 18692 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18693 "PLL_CAL_PLL_CALCTL_4", 18694 NULL, 18695 #endif 18696 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18697 0x8240, /* 33344 */ 18698 0, 18699 #endif 18700 }, 18701 { 18702 BCMI_QTC_XGXS_PLL_CALCTL5r, 18703 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18704 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 18705 BCMI_QTC_XGXS_PLL_CALCTL5r_fields, 18706 #else 18707 0, 18708 #endif 18709 #endif 18710 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18711 PHYMOD_SYMBOL_FLAG_REGISTER, 18712 "PLL_CALCTL5r", 18713 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18714 "PLL_CAL_PLL_CALCTL_5", 18715 NULL, 18716 #endif 18717 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18718 0x8160, /* 33120 */ 18719 0, 18720 #endif 18721 }, 18722 { 18723 BCMI_QTC_XGXS_PLL_CALCTL6r, 18724 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18725 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 18726 BCMI_QTC_XGXS_PLL_CALCTL6r_fields, 18727 #else 18728 0, 18729 #endif 18730 #endif 18731 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18732 PHYMOD_SYMBOL_FLAG_REGISTER, 18733 "PLL_CALCTL6r", 18734 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18735 "PLL_CAL_PLL_CALCTL_6", 18736 NULL, 18737 #endif 18738 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18739 0x0, /* 0 */ 18740 0, 18741 #endif 18742 }, 18743 { 18744 BCMI_QTC_XGXS_PLL_CALSTS0r, 18745 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18746 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 18747 BCMI_QTC_XGXS_PLL_CALSTS0r_fields, 18748 #else 18749 0, 18750 #endif 18751 #endif 18752 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18753 PHYMOD_SYMBOL_FLAG_REGISTER, 18754 "PLL_CALSTS0r", 18755 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18756 "PLL_CAL_PLL_CALSTS_0", 18757 NULL, 18758 #endif 18759 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18760 0x13f, /* 319 */ 18761 0, 18762 #endif 18763 }, 18764 { 18765 BCMI_QTC_XGXS_PLL_CALSTS1r, 18766 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18767 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 18768 BCMI_QTC_XGXS_PLL_CALSTS1r_fields, 18769 #else 18770 0, 18771 #endif 18772 #endif 18773 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18774 PHYMOD_SYMBOL_FLAG_REGISTER, 18775 "PLL_CALSTS1r", 18776 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18777 "PLL_CAL_PLL_CALSTS_1", 18778 NULL, 18779 #endif 18780 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18781 0x0, /* 0 */ 18782 0, 18783 #endif 18784 }, 18785 { 18786 BCMI_QTC_XGXS_PLL_CALSTS2r, 18787 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18788 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 18789 BCMI_QTC_XGXS_PLL_CALSTS2r_fields, 18790 #else 18791 0, 18792 #endif 18793 #endif 18794 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18795 PHYMOD_SYMBOL_FLAG_REGISTER, 18796 "PLL_CALSTS2r", 18797 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18798 "PLL_CAL_PLL_CALSTS_2", 18799 NULL, 18800 #endif 18801 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18802 0x6000, /* 24576 */ 18803 0, 18804 #endif 18805 }, 18806 { 18807 BCMI_QTC_XGXS_PLL_CALSTS3r, 18808 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18809 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 18810 BCMI_QTC_XGXS_PLL_CALSTS3r_fields, 18811 #else 18812 0, 18813 #endif 18814 #endif 18815 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18816 PHYMOD_SYMBOL_FLAG_REGISTER, 18817 "PLL_CALSTS3r", 18818 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18819 "PLL_CAL_PLL_CALSTS_3", 18820 NULL, 18821 #endif 18822 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18823 0x0, /* 0 */ 18824 0, 18825 #endif 18826 }, 18827 { 18828 BCMI_QTC_XGXS_PLL_CALSTS4r, 18829 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18830 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 18831 BCMI_QTC_XGXS_PLL_CALSTS4r_fields, 18832 #else 18833 0, 18834 #endif 18835 #endif 18836 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18837 PHYMOD_SYMBOL_FLAG_REGISTER, 18838 "PLL_CALSTS4r", 18839 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18840 "PLL_CAL_PLL_CALSTS_4", 18841 NULL, 18842 #endif 18843 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18844 0x0, /* 0 */ 18845 0, 18846 #endif 18847 }, 18848 { 18849 BCMI_QTC_XGXS_PLL_CALSTS5r, 18850 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18851 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 18852 BCMI_QTC_XGXS_PLL_CALSTS5r_fields, 18853 #else 18854 0, 18855 #endif 18856 #endif 18857 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18858 PHYMOD_SYMBOL_FLAG_REGISTER, 18859 "PLL_CALSTS5r", 18860 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18861 "PLL_CAL_PLL_CALSTS_5", 18862 NULL, 18863 #endif 18864 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18865 0x0, /* 0 */ 18866 0, 18867 #endif 18868 }, 18869 { 18870 BCMI_QTC_XGXS_PLL_CALSTS6r, 18871 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18872 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 18873 BCMI_QTC_XGXS_PLL_CALSTS6r_fields, 18874 #else 18875 0, 18876 #endif 18877 #endif 18878 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18879 PHYMOD_SYMBOL_FLAG_REGISTER, 18880 "PLL_CALSTS6r", 18881 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18882 "PLL_CAL_PLL_CALSTS_6", 18883 NULL, 18884 #endif 18885 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18886 0x3f00, /* 16128 */ 18887 0, 18888 #endif 18889 }, 18890 { 18891 BCMI_QTC_XGXS_TXCOM_CTL0r, 18892 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18893 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 18894 BCMI_QTC_XGXS_TXCOM_CTL0r_fields, 18895 #else 18896 0, 18897 #endif 18898 #endif 18899 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18900 PHYMOD_SYMBOL_FLAG_REGISTER, 18901 "TXCOM_CTL0r", 18902 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18903 "TXCOM_TXCOM_CONTROL0_REGISTER", 18904 NULL, 18905 #endif 18906 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18907 0x1f4, /* 500 */ 18908 0, 18909 #endif 18910 }, 18911 { 18912 BCMI_QTC_XGXS_TXCOM_CTL1r, 18913 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18914 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 18915 BCMI_QTC_XGXS_TXCOM_CTL1r_fields, 18916 #else 18917 0, 18918 #endif 18919 #endif 18920 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18921 PHYMOD_SYMBOL_FLAG_REGISTER, 18922 "TXCOM_CTL1r", 18923 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18924 "TXCOM_TXCOM_CONTROL1_REGISTER", 18925 NULL, 18926 #endif 18927 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18928 0xc8, /* 200 */ 18929 0, 18930 #endif 18931 }, 18932 { 18933 BCMI_QTC_XGXS_DSC_F_DATA_ODD_OFFSr, 18934 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18935 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 18936 BCMI_QTC_XGXS_DSC_F_DATA_ODD_OFFSr_fields, 18937 #else 18938 0, 18939 #endif 18940 #endif 18941 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18942 PHYMOD_SYMBOL_FLAG_REGISTER, 18943 "DSC_F_DATA_ODD_OFFSr", 18944 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18945 "DSC_F_DSC_F_DATA_ODD_OFFSET", 18946 NULL, 18947 #endif 18948 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18949 0x0, /* 0 */ 18950 0, 18951 #endif 18952 }, 18953 { 18954 BCMI_QTC_XGXS_DSC_F_DATA_EVEN_OFFSr, 18955 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18956 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 18957 BCMI_QTC_XGXS_DSC_F_DATA_EVEN_OFFSr_fields, 18958 #else 18959 0, 18960 #endif 18961 #endif 18962 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18963 PHYMOD_SYMBOL_FLAG_REGISTER, 18964 "DSC_F_DATA_EVEN_OFFSr", 18965 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18966 "DSC_F_DSC_F_DATA_EVEN_OFFSET", 18967 NULL, 18968 #endif 18969 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18970 0x0, /* 0 */ 18971 0, 18972 #endif 18973 }, 18974 { 18975 BCMI_QTC_XGXS_DSC_F_P1_ODD_OFFSr, 18976 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18977 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 18978 BCMI_QTC_XGXS_DSC_F_P1_ODD_OFFSr_fields, 18979 #else 18980 0, 18981 #endif 18982 #endif 18983 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 18984 PHYMOD_SYMBOL_FLAG_REGISTER, 18985 "DSC_F_P1_ODD_OFFSr", 18986 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 18987 "DSC_F_DSC_F_P1_ODD_OFFSET", 18988 NULL, 18989 #endif 18990 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 18991 0x0, /* 0 */ 18992 0, 18993 #endif 18994 }, 18995 { 18996 BCMI_QTC_XGXS_DSC_F_P1_EVEN_OFFSr, 18997 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 18998 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 18999 BCMI_QTC_XGXS_DSC_F_P1_EVEN_OFFSr_fields, 19000 #else 19001 0, 19002 #endif 19003 #endif 19004 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 19005 PHYMOD_SYMBOL_FLAG_REGISTER, 19006 "DSC_F_P1_EVEN_OFFSr", 19007 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 19008 "DSC_F_DSC_F_P1_EVEN_OFFSET", 19009 NULL, 19010 #endif 19011 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 19012 0x0, /* 0 */ 19013 0, 19014 #endif 19015 }, 19016 { 19017 BCMI_QTC_XGXS_DSC_F_M1_ODD_OFFSr, 19018 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 19019 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 19020 BCMI_QTC_XGXS_DSC_F_M1_ODD_OFFSr_fields, 19021 #else 19022 0, 19023 #endif 19024 #endif 19025 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 19026 PHYMOD_SYMBOL_FLAG_REGISTER, 19027 "DSC_F_M1_ODD_OFFSr", 19028 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 19029 "DSC_F_DSC_F_M1_ODD_OFFSET", 19030 NULL, 19031 #endif 19032 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 19033 0x0, /* 0 */ 19034 0, 19035 #endif 19036 }, 19037 { 19038 BCMI_QTC_XGXS_DSC_F_M1_EVEN_OFFSr, 19039 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 19040 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 19041 BCMI_QTC_XGXS_DSC_F_M1_EVEN_OFFSr_fields, 19042 #else 19043 0, 19044 #endif 19045 #endif 19046 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 19047 PHYMOD_SYMBOL_FLAG_REGISTER, 19048 "DSC_F_M1_EVEN_OFFSr", 19049 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 19050 "DSC_F_DSC_F_M1_EVEN_OFFSET", 19051 NULL, 19052 #endif 19053 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 19054 0x0, /* 0 */ 19055 0, 19056 #endif 19057 }, 19058 { 19059 BCMI_QTC_XGXS_DSC_F_DC_OFFSr, 19060 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 19061 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 19062 BCMI_QTC_XGXS_DSC_F_DC_OFFSr_fields, 19063 #else 19064 0, 19065 #endif 19066 #endif 19067 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 19068 PHYMOD_SYMBOL_FLAG_REGISTER, 19069 "DSC_F_DC_OFFSr", 19070 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 19071 "DSC_F_DSC_F_DC_OFFSET", 19072 NULL, 19073 #endif 19074 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 19075 0x0, /* 0 */ 19076 0, 19077 #endif 19078 }, 19079 { 19080 BCMI_QTC_XGXS_LN_ADDR0r, 19081 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 19082 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 19083 BCMI_QTC_XGXS_LN_ADDR0r_fields, 19084 #else 19085 0, 19086 #endif 19087 #endif 19088 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 19089 PHYMOD_SYMBOL_FLAG_REGISTER, 19090 "LN_ADDR0r", 19091 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 19092 "DIGCOM_B_LANE_ADDR_0", 19093 NULL, 19094 #endif 19095 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 19096 0x0, /* 0 */ 19097 0, 19098 #endif 19099 }, 19100 { 19101 BCMI_QTC_XGXS_LN_ADDR1r, 19102 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 19103 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 19104 BCMI_QTC_XGXS_LN_ADDR1r_fields, 19105 #else 19106 0, 19107 #endif 19108 #endif 19109 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 19110 PHYMOD_SYMBOL_FLAG_REGISTER, 19111 "LN_ADDR1r", 19112 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 19113 "DIGCOM_B_LANE_ADDR_1", 19114 NULL, 19115 #endif 19116 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 19117 0x101, /* 257 */ 19118 0, 19119 #endif 19120 }, 19121 { 19122 BCMI_QTC_XGXS_LN_ADDR2r, 19123 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 19124 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 19125 BCMI_QTC_XGXS_LN_ADDR2r_fields, 19126 #else 19127 0, 19128 #endif 19129 #endif 19130 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 19131 PHYMOD_SYMBOL_FLAG_REGISTER, 19132 "LN_ADDR2r", 19133 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 19134 "DIGCOM_B_LANE_ADDR_2", 19135 NULL, 19136 #endif 19137 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 19138 0x202, /* 514 */ 19139 0, 19140 #endif 19141 }, 19142 { 19143 BCMI_QTC_XGXS_LN_ADDR3r, 19144 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 19145 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 19146 BCMI_QTC_XGXS_LN_ADDR3r_fields, 19147 #else 19148 0, 19149 #endif 19150 #endif 19151 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 19152 PHYMOD_SYMBOL_FLAG_REGISTER, 19153 "LN_ADDR3r", 19154 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 19155 "DIGCOM_B_LANE_ADDR_3", 19156 NULL, 19157 #endif 19158 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 19159 0x303, /* 771 */ 19160 0, 19161 #endif 19162 }, 19163 { 19164 BCMI_QTC_XGXS_RX_LN_CLK_RST_N_PWRDWN_CTLr, 19165 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 19166 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 19167 BCMI_QTC_XGXS_RX_LN_CLK_RST_N_PWRDWN_CTLr_fields, 19168 #else 19169 0, 19170 #endif 19171 #endif 19172 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 19173 PHYMOD_SYMBOL_FLAG_REGISTER, 19174 "RX_LN_CLK_RST_N_PWRDWN_CTLr", 19175 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 19176 "RX_CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL", 19177 NULL, 19178 #endif 19179 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 19180 0x0, /* 0 */ 19181 0, 19182 #endif 19183 }, 19184 { 19185 BCMI_QTC_XGXS_RX_LN_AFE_RST_PWRDWN_CTL_CTLr, 19186 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 19187 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 19188 BCMI_QTC_XGXS_RX_LN_AFE_RST_PWRDWN_CTL_CTLr_fields, 19189 #else 19190 0, 19191 #endif 19192 #endif 19193 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 19194 PHYMOD_SYMBOL_FLAG_REGISTER, 19195 "RX_LN_AFE_RST_PWRDWN_CTL_CTLr", 19196 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 19197 "RX_CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL", 19198 NULL, 19199 #endif 19200 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 19201 0x0, /* 0 */ 19202 0, 19203 #endif 19204 }, 19205 { 19206 BCMI_QTC_XGXS_RX_LN_RST_N_PWRDN_PIN_KILL_CTLr, 19207 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 19208 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 19209 BCMI_QTC_XGXS_RX_LN_RST_N_PWRDN_PIN_KILL_CTLr_fields, 19210 #else 19211 0, 19212 #endif 19213 #endif 19214 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 19215 PHYMOD_SYMBOL_FLAG_REGISTER, 19216 "RX_LN_RST_N_PWRDN_PIN_KILL_CTLr", 19217 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 19218 "RX_CKRST_CTRL_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL", 19219 NULL, 19220 #endif 19221 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 19222 0x0, /* 0 */ 19223 0, 19224 #endif 19225 }, 19226 { 19227 BCMI_QTC_XGXS_RX_LN_DBG_RST_CTLr, 19228 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 19229 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 19230 BCMI_QTC_XGXS_RX_LN_DBG_RST_CTLr_fields, 19231 #else 19232 0, 19233 #endif 19234 #endif 19235 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 19236 PHYMOD_SYMBOL_FLAG_REGISTER, 19237 "RX_LN_DBG_RST_CTLr", 19238 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 19239 "RX_CKRST_CTRL_LANE_DEBUG_RESET_CONTROL", 19240 NULL, 19241 #endif 19242 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 19243 0x3, /* 3 */ 19244 0, 19245 #endif 19246 }, 19247 { 19248 BCMI_QTC_XGXS_RX_CLK_N_RST_DBG_CTLr, 19249 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 19250 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 19251 BCMI_QTC_XGXS_RX_CLK_N_RST_DBG_CTLr_fields, 19252 #else 19253 0, 19254 #endif 19255 #endif 19256 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 19257 PHYMOD_SYMBOL_FLAG_REGISTER, 19258 "RX_CLK_N_RST_DBG_CTLr", 19259 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 19260 "RX_CKRST_CTRL_CLOCK_N_RESET_DEBUG_CONTROL", 19261 NULL, 19262 #endif 19263 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 19264 0x0, /* 0 */ 19265 0, 19266 #endif 19267 }, 19268 { 19269 BCMI_QTC_XGXS_RX_PMD_LN_MODE_STSr, 19270 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 19271 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 19272 BCMI_QTC_XGXS_RX_PMD_LN_MODE_STSr_fields, 19273 #else 19274 0, 19275 #endif 19276 #endif 19277 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 19278 PHYMOD_SYMBOL_FLAG_REGISTER, 19279 "RX_PMD_LN_MODE_STSr", 19280 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 19281 "RX_CKRST_CTRL_PMD_LANE_MODE_STATUS", 19282 NULL, 19283 #endif 19284 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 19285 0x0, /* 0 */ 19286 0, 19287 #endif 19288 }, 19289 { 19290 BCMI_QTC_XGXS_RX_AFE_RST_PWRDN_OSR_MODE_PIN_STSr, 19291 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 19292 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 19293 BCMI_QTC_XGXS_RX_AFE_RST_PWRDN_OSR_MODE_PIN_STSr_fields, 19294 #else 19295 0, 19296 #endif 19297 #endif 19298 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 19299 PHYMOD_SYMBOL_FLAG_REGISTER, 19300 "RX_AFE_RST_PWRDN_OSR_MODE_PIN_STSr", 19301 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 19302 "RX_CKRST_CTRL_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS", 19303 NULL, 19304 #endif 19305 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 19306 0x2, /* 2 */ 19307 0, 19308 #endif 19309 }, 19310 { 19311 BCMI_QTC_XGXS_TX_LN_CLK_RST_N_PWRDWN_CTLr, 19312 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 19313 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 19314 BCMI_QTC_XGXS_TX_LN_CLK_RST_N_PWRDWN_CTLr_fields, 19315 #else 19316 0, 19317 #endif 19318 #endif 19319 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 19320 PHYMOD_SYMBOL_FLAG_REGISTER, 19321 "TX_LN_CLK_RST_N_PWRDWN_CTLr", 19322 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 19323 "TX_CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL", 19324 NULL, 19325 #endif 19326 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 19327 0x0, /* 0 */ 19328 0, 19329 #endif 19330 }, 19331 { 19332 BCMI_QTC_XGXS_TX_LN_AFE_RST_PWRDWN_CTL_CTLr, 19333 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 19334 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 19335 BCMI_QTC_XGXS_TX_LN_AFE_RST_PWRDWN_CTL_CTLr_fields, 19336 #else 19337 0, 19338 #endif 19339 #endif 19340 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 19341 PHYMOD_SYMBOL_FLAG_REGISTER, 19342 "TX_LN_AFE_RST_PWRDWN_CTL_CTLr", 19343 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 19344 "TX_CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL", 19345 NULL, 19346 #endif 19347 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 19348 0x0, /* 0 */ 19349 0, 19350 #endif 19351 }, 19352 { 19353 BCMI_QTC_XGXS_TX_LN_RST_N_PWRDN_PIN_KILL_CTLr, 19354 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 19355 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 19356 BCMI_QTC_XGXS_TX_LN_RST_N_PWRDN_PIN_KILL_CTLr_fields, 19357 #else 19358 0, 19359 #endif 19360 #endif 19361 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 19362 PHYMOD_SYMBOL_FLAG_REGISTER, 19363 "TX_LN_RST_N_PWRDN_PIN_KILL_CTLr", 19364 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 19365 "TX_CKRST_CTRL_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL", 19366 NULL, 19367 #endif 19368 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 19369 0x0, /* 0 */ 19370 0, 19371 #endif 19372 }, 19373 { 19374 BCMI_QTC_XGXS_TX_LN_DBG_RST_CTLr, 19375 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 19376 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 19377 BCMI_QTC_XGXS_TX_LN_DBG_RST_CTLr_fields, 19378 #else 19379 0, 19380 #endif 19381 #endif 19382 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 19383 PHYMOD_SYMBOL_FLAG_REGISTER, 19384 "TX_LN_DBG_RST_CTLr", 19385 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 19386 "TX_CKRST_CTRL_LANE_DEBUG_RESET_CONTROL", 19387 NULL, 19388 #endif 19389 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 19390 0x3, /* 3 */ 19391 0, 19392 #endif 19393 }, 19394 { 19395 BCMI_QTC_XGXS_TX_CLK_N_RST_DBG_CTLr, 19396 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 19397 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 19398 BCMI_QTC_XGXS_TX_CLK_N_RST_DBG_CTLr_fields, 19399 #else 19400 0, 19401 #endif 19402 #endif 19403 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 19404 PHYMOD_SYMBOL_FLAG_REGISTER, 19405 "TX_CLK_N_RST_DBG_CTLr", 19406 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 19407 "TX_CKRST_CTRL_CLOCK_N_RESET_DEBUG_CONTROL", 19408 NULL, 19409 #endif 19410 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 19411 0x0, /* 0 */ 19412 0, 19413 #endif 19414 }, 19415 { 19416 BCMI_QTC_XGXS_TX_AFE_RST_PWRDN_OSR_MODE_PIN_STSr, 19417 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 19418 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 19419 BCMI_QTC_XGXS_TX_AFE_RST_PWRDN_OSR_MODE_PIN_STSr_fields, 19420 #else 19421 0, 19422 #endif 19423 #endif 19424 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 19425 PHYMOD_SYMBOL_FLAG_REGISTER, 19426 "TX_AFE_RST_PWRDN_OSR_MODE_PIN_STSr", 19427 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 19428 "TX_CKRST_CTRL_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS", 19429 NULL, 19430 #endif 19431 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 19432 0x6, /* 6 */ 19433 0, 19434 #endif 19435 }, 19436 { 19437 BCMI_QTC_XGXS_TX_CLK_N_RST_MISC_CTLr, 19438 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 19439 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 19440 BCMI_QTC_XGXS_TX_CLK_N_RST_MISC_CTLr_fields, 19441 #else 19442 0, 19443 #endif 19444 #endif 19445 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 19446 PHYMOD_SYMBOL_FLAG_REGISTER, 19447 "TX_CLK_N_RST_MISC_CTLr", 19448 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 19449 "TX_CKRST_CTRL_CLOCK_N_RESET_MISC_CONTROL", 19450 NULL, 19451 #endif 19452 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 19453 0x1, /* 1 */ 19454 0, 19455 #endif 19456 }, 19457 { 19458 BCMI_QTC_XGXS_RXCOM_OSR_MODE_CTLr, 19459 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 19460 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 19461 BCMI_QTC_XGXS_RXCOM_OSR_MODE_CTLr_fields, 19462 #else 19463 0, 19464 #endif 19465 #endif 19466 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 19467 PHYMOD_SYMBOL_FLAG_REGISTER, 19468 "RXCOM_OSR_MODE_CTLr", 19469 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 19470 "RXCOM_CKRST_CTRL_OSR_MODE_CONTROL", 19471 NULL, 19472 #endif 19473 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 19474 0x0, /* 0 */ 19475 0, 19476 #endif 19477 }, 19478 { 19479 BCMI_QTC_XGXS_RXCOM_LN_CLK_RST_N_PWRDWN_CTLr, 19480 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 19481 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 19482 BCMI_QTC_XGXS_RXCOM_LN_CLK_RST_N_PWRDWN_CTLr_fields, 19483 #else 19484 0, 19485 #endif 19486 #endif 19487 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 19488 PHYMOD_SYMBOL_FLAG_REGISTER, 19489 "RXCOM_LN_CLK_RST_N_PWRDWN_CTLr", 19490 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 19491 "RXCOM_CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL", 19492 NULL, 19493 #endif 19494 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 19495 0x0, /* 0 */ 19496 0, 19497 #endif 19498 }, 19499 { 19500 BCMI_QTC_XGXS_RXCOM_LN_RST_N_PWRDN_PIN_KILL_CTLr, 19501 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 19502 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 19503 BCMI_QTC_XGXS_RXCOM_LN_RST_N_PWRDN_PIN_KILL_CTLr_fields, 19504 #else 19505 0, 19506 #endif 19507 #endif 19508 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 19509 PHYMOD_SYMBOL_FLAG_REGISTER, 19510 "RXCOM_LN_RST_N_PWRDN_PIN_KILL_CTLr", 19511 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 19512 "RXCOM_CKRST_CTRL_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL", 19513 NULL, 19514 #endif 19515 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 19516 0x0, /* 0 */ 19517 0, 19518 #endif 19519 }, 19520 { 19521 BCMI_QTC_XGXS_RXCOM_UC_ACK_LN_CTLr, 19522 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 19523 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 19524 BCMI_QTC_XGXS_RXCOM_UC_ACK_LN_CTLr_fields, 19525 #else 19526 0, 19527 #endif 19528 #endif 19529 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 19530 PHYMOD_SYMBOL_FLAG_REGISTER, 19531 "RXCOM_UC_ACK_LN_CTLr", 19532 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 19533 "RXCOM_CKRST_CTRL_UC_ACK_LANE_CONTROL", 19534 NULL, 19535 #endif 19536 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 19537 0x0, /* 0 */ 19538 0, 19539 #endif 19540 }, 19541 { 19542 BCMI_QTC_XGXS_RXCOM_LN_RST_OCC_CTLr, 19543 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 19544 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 19545 BCMI_QTC_XGXS_RXCOM_LN_RST_OCC_CTLr_fields, 19546 #else 19547 0, 19548 #endif 19549 #endif 19550 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 19551 PHYMOD_SYMBOL_FLAG_REGISTER, 19552 "RXCOM_LN_RST_OCC_CTLr", 19553 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 19554 "RXCOM_CKRST_CTRL_LANE_REG_RESET_OCCURRED_CONTROL", 19555 NULL, 19556 #endif 19557 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 19558 0x1, /* 1 */ 19559 0, 19560 #endif 19561 }, 19562 { 19563 BCMI_QTC_XGXS_RXCOM_LN_DP_RST_ST_STSr, 19564 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 19565 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 19566 BCMI_QTC_XGXS_RXCOM_LN_DP_RST_ST_STSr_fields, 19567 #else 19568 0, 19569 #endif 19570 #endif 19571 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 19572 PHYMOD_SYMBOL_FLAG_REGISTER, 19573 "RXCOM_LN_DP_RST_ST_STSr", 19574 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 19575 "RXCOM_CKRST_CTRL_LANE_DP_RESET_STATE_STATUS", 19576 NULL, 19577 #endif 19578 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 19579 0x7, /* 7 */ 19580 0, 19581 #endif 19582 }, 19583 { 19584 BCMI_QTC_XGXS_RXCOM_MCST_MASK_CTLr, 19585 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 19586 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 19587 BCMI_QTC_XGXS_RXCOM_MCST_MASK_CTLr_fields, 19588 #else 19589 0, 19590 #endif 19591 #endif 19592 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 19593 PHYMOD_SYMBOL_FLAG_REGISTER, 19594 "RXCOM_MCST_MASK_CTLr", 19595 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 19596 "RXCOM_CKRST_CTRL_MULTICAST_MASK_CONTROL", 19597 NULL, 19598 #endif 19599 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 19600 0x0, /* 0 */ 19601 0, 19602 #endif 19603 }, 19604 { 19605 BCMI_QTC_XGXS_RXCOM_OSR_MODE_STS_MC_MASKr, 19606 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 19607 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 19608 BCMI_QTC_XGXS_RXCOM_OSR_MODE_STS_MC_MASKr_fields, 19609 #else 19610 0, 19611 #endif 19612 #endif 19613 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 19614 PHYMOD_SYMBOL_FLAG_REGISTER, 19615 "RXCOM_OSR_MODE_STS_MC_MASKr", 19616 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 19617 "RXCOM_CKRST_CTRL_OSR_MODE_STATUS_MC_MASK", 19618 NULL, 19619 #endif 19620 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 19621 0x0, /* 0 */ 19622 0, 19623 #endif 19624 }, 19625 { 19626 BCMI_QTC_XGXS_RXCOM_AFE_RST_PWRDN_OSR_MODE_PIN_STSr, 19627 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 19628 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 19629 BCMI_QTC_XGXS_RXCOM_AFE_RST_PWRDN_OSR_MODE_PIN_STSr_fields, 19630 #else 19631 0, 19632 #endif 19633 #endif 19634 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 19635 PHYMOD_SYMBOL_FLAG_REGISTER, 19636 "RXCOM_AFE_RST_PWRDN_OSR_MODE_PIN_STSr", 19637 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 19638 "RXCOM_CKRST_CTRL_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS", 19639 NULL, 19640 #endif 19641 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 19642 0x0, /* 0 */ 19643 0, 19644 #endif 19645 }, 19646 { 19647 BCMI_QTC_XGXS_RXCOM_LN_S_RSTB_CTLr, 19648 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 19649 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 19650 BCMI_QTC_XGXS_RXCOM_LN_S_RSTB_CTLr_fields, 19651 #else 19652 0, 19653 #endif 19654 #endif 19655 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 19656 PHYMOD_SYMBOL_FLAG_REGISTER, 19657 "RXCOM_LN_S_RSTB_CTLr", 19658 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 19659 "RXCOM_CKRST_CTRL_LN_S_RSTB_CONTROL", 19660 NULL, 19661 #endif 19662 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 19663 0x1, /* 1 */ 19664 0, 19665 #endif 19666 }, 19667 { 19668 BCMI_QTC_XGXS_TXCOM_OSR_MODE_CTLr, 19669 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 19670 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 19671 BCMI_QTC_XGXS_TXCOM_OSR_MODE_CTLr_fields, 19672 #else 19673 0, 19674 #endif 19675 #endif 19676 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 19677 PHYMOD_SYMBOL_FLAG_REGISTER, 19678 "TXCOM_OSR_MODE_CTLr", 19679 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 19680 "TXCOM_CKRST_CTRL_OSR_MODE_CONTROL", 19681 NULL, 19682 #endif 19683 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 19684 0x0, /* 0 */ 19685 0, 19686 #endif 19687 }, 19688 { 19689 BCMI_QTC_XGXS_TXCOM_LN_CLK_RST_N_PWRDWN_CTLr, 19690 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 19691 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 19692 BCMI_QTC_XGXS_TXCOM_LN_CLK_RST_N_PWRDWN_CTLr_fields, 19693 #else 19694 0, 19695 #endif 19696 #endif 19697 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 19698 PHYMOD_SYMBOL_FLAG_REGISTER, 19699 "TXCOM_LN_CLK_RST_N_PWRDWN_CTLr", 19700 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 19701 "TXCOM_CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL", 19702 NULL, 19703 #endif 19704 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 19705 0x0, /* 0 */ 19706 0, 19707 #endif 19708 }, 19709 { 19710 BCMI_QTC_XGXS_TXCOM_LN_RST_N_PWRDN_PIN_KILL_CTLr, 19711 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 19712 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 19713 BCMI_QTC_XGXS_TXCOM_LN_RST_N_PWRDN_PIN_KILL_CTLr_fields, 19714 #else 19715 0, 19716 #endif 19717 #endif 19718 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 19719 PHYMOD_SYMBOL_FLAG_REGISTER, 19720 "TXCOM_LN_RST_N_PWRDN_PIN_KILL_CTLr", 19721 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 19722 "TXCOM_CKRST_CTRL_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL", 19723 NULL, 19724 #endif 19725 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 19726 0x0, /* 0 */ 19727 0, 19728 #endif 19729 }, 19730 { 19731 BCMI_QTC_XGXS_TXCOM_UC_ACK_LN_CTLr, 19732 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 19733 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 19734 BCMI_QTC_XGXS_TXCOM_UC_ACK_LN_CTLr_fields, 19735 #else 19736 0, 19737 #endif 19738 #endif 19739 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 19740 PHYMOD_SYMBOL_FLAG_REGISTER, 19741 "TXCOM_UC_ACK_LN_CTLr", 19742 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 19743 "TXCOM_CKRST_CTRL_UC_ACK_LANE_CONTROL", 19744 NULL, 19745 #endif 19746 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 19747 0x0, /* 0 */ 19748 0, 19749 #endif 19750 }, 19751 { 19752 BCMI_QTC_XGXS_TXCOM_LN_RST_OCC_CTLr, 19753 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 19754 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 19755 BCMI_QTC_XGXS_TXCOM_LN_RST_OCC_CTLr_fields, 19756 #else 19757 0, 19758 #endif 19759 #endif 19760 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 19761 PHYMOD_SYMBOL_FLAG_REGISTER, 19762 "TXCOM_LN_RST_OCC_CTLr", 19763 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 19764 "TXCOM_CKRST_CTRL_LANE_REG_RESET_OCCURRED_CONTROL", 19765 NULL, 19766 #endif 19767 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 19768 0x1, /* 1 */ 19769 0, 19770 #endif 19771 }, 19772 { 19773 BCMI_QTC_XGXS_TXCOM_LN_DP_RST_ST_STSr, 19774 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 19775 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 19776 BCMI_QTC_XGXS_TXCOM_LN_DP_RST_ST_STSr_fields, 19777 #else 19778 0, 19779 #endif 19780 #endif 19781 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 19782 PHYMOD_SYMBOL_FLAG_REGISTER, 19783 "TXCOM_LN_DP_RST_ST_STSr", 19784 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 19785 "TXCOM_CKRST_CTRL_LANE_DP_RESET_STATE_STATUS", 19786 NULL, 19787 #endif 19788 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 19789 0x7, /* 7 */ 19790 0, 19791 #endif 19792 }, 19793 { 19794 BCMI_QTC_XGXS_TXCOM_MCST_MASK_CTLr, 19795 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 19796 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 19797 BCMI_QTC_XGXS_TXCOM_MCST_MASK_CTLr_fields, 19798 #else 19799 0, 19800 #endif 19801 #endif 19802 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 19803 PHYMOD_SYMBOL_FLAG_REGISTER, 19804 "TXCOM_MCST_MASK_CTLr", 19805 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 19806 "TXCOM_CKRST_CTRL_MULTICAST_MASK_CONTROL", 19807 NULL, 19808 #endif 19809 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 19810 0x0, /* 0 */ 19811 0, 19812 #endif 19813 }, 19814 { 19815 BCMI_QTC_XGXS_TXCOM_OSR_MODE_STS_MC_MASKr, 19816 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 19817 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 19818 BCMI_QTC_XGXS_TXCOM_OSR_MODE_STS_MC_MASKr_fields, 19819 #else 19820 0, 19821 #endif 19822 #endif 19823 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 19824 PHYMOD_SYMBOL_FLAG_REGISTER, 19825 "TXCOM_OSR_MODE_STS_MC_MASKr", 19826 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 19827 "TXCOM_CKRST_CTRL_OSR_MODE_STATUS_MC_MASK", 19828 NULL, 19829 #endif 19830 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 19831 0x0, /* 0 */ 19832 0, 19833 #endif 19834 }, 19835 { 19836 BCMI_QTC_XGXS_TXCOM_AFE_RST_PWRDN_OSR_MODE_PIN_STSr, 19837 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 19838 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 19839 BCMI_QTC_XGXS_TXCOM_AFE_RST_PWRDN_OSR_MODE_PIN_STSr_fields, 19840 #else 19841 0, 19842 #endif 19843 #endif 19844 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 19845 PHYMOD_SYMBOL_FLAG_REGISTER, 19846 "TXCOM_AFE_RST_PWRDN_OSR_MODE_PIN_STSr", 19847 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 19848 "TXCOM_CKRST_CTRL_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS", 19849 NULL, 19850 #endif 19851 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 19852 0x0, /* 0 */ 19853 0, 19854 #endif 19855 }, 19856 { 19857 BCMI_QTC_XGXS_TXCOM_LN_S_RSTB_CTLr, 19858 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 19859 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 19860 BCMI_QTC_XGXS_TXCOM_LN_S_RSTB_CTLr_fields, 19861 #else 19862 0, 19863 #endif 19864 #endif 19865 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 19866 PHYMOD_SYMBOL_FLAG_REGISTER, 19867 "TXCOM_LN_S_RSTB_CTLr", 19868 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 19869 "TXCOM_CKRST_CTRL_LN_S_RSTB_CONTROL", 19870 NULL, 19871 #endif 19872 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 19873 0x1, /* 1 */ 19874 0, 19875 #endif 19876 }, 19877 { 19878 BCMI_QTC_XGXS_UC_CLK_CTL0r, 19879 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 19880 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 19881 BCMI_QTC_XGXS_UC_CLK_CTL0r_fields, 19882 #else 19883 0, 19884 #endif 19885 #endif 19886 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 19887 PHYMOD_SYMBOL_FLAG_REGISTER, 19888 "UC_CLK_CTL0r", 19889 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 19890 "MICRO_A_CLOCK_CONTROL0", 19891 NULL, 19892 #endif 19893 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 19894 0x0, /* 0 */ 19895 0, 19896 #endif 19897 }, 19898 { 19899 BCMI_QTC_XGXS_UC_RST_CTL0r, 19900 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 19901 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 19902 BCMI_QTC_XGXS_UC_RST_CTL0r_fields, 19903 #else 19904 0, 19905 #endif 19906 #endif 19907 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 19908 PHYMOD_SYMBOL_FLAG_REGISTER, 19909 "UC_RST_CTL0r", 19910 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 19911 "MICRO_A_RESET_CONTROL0", 19912 NULL, 19913 #endif 19914 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 19915 0x0, /* 0 */ 19916 0, 19917 #endif 19918 }, 19919 { 19920 BCMI_QTC_XGXS_UC_AHB_CTL0r, 19921 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 19922 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 19923 BCMI_QTC_XGXS_UC_AHB_CTL0r_fields, 19924 #else 19925 0, 19926 #endif 19927 #endif 19928 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 19929 PHYMOD_SYMBOL_FLAG_REGISTER, 19930 "UC_AHB_CTL0r", 19931 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 19932 "MICRO_A_AHB_CONTROL0", 19933 NULL, 19934 #endif 19935 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 19936 0x0, /* 0 */ 19937 0, 19938 #endif 19939 }, 19940 { 19941 BCMI_QTC_XGXS_UC_AHB_STS0r, 19942 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 19943 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 19944 BCMI_QTC_XGXS_UC_AHB_STS0r_fields, 19945 #else 19946 0, 19947 #endif 19948 #endif 19949 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 19950 PHYMOD_SYMBOL_FLAG_REGISTER, 19951 "UC_AHB_STS0r", 19952 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 19953 "MICRO_A_AHB_STATUS0", 19954 NULL, 19955 #endif 19956 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 19957 0x0, /* 0 */ 19958 0, 19959 #endif 19960 }, 19961 { 19962 BCMI_QTC_XGXS_UC_AHB_WRADDR_LSWr, 19963 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 19964 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 19965 BCMI_QTC_XGXS_UC_AHB_WRADDR_LSWr_fields, 19966 #else 19967 0, 19968 #endif 19969 #endif 19970 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 19971 PHYMOD_SYMBOL_FLAG_REGISTER, 19972 "UC_AHB_WRADDR_LSWr", 19973 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 19974 "MICRO_A_AHB_WRADDR_LSW", 19975 NULL, 19976 #endif 19977 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 19978 0x0, /* 0 */ 19979 0, 19980 #endif 19981 }, 19982 { 19983 BCMI_QTC_XGXS_UC_AHB_WRADDR_MSWr, 19984 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 19985 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 19986 BCMI_QTC_XGXS_UC_AHB_WRADDR_MSWr_fields, 19987 #else 19988 0, 19989 #endif 19990 #endif 19991 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 19992 PHYMOD_SYMBOL_FLAG_REGISTER, 19993 "UC_AHB_WRADDR_MSWr", 19994 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 19995 "MICRO_A_AHB_WRADDR_MSW", 19996 NULL, 19997 #endif 19998 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 19999 0x0, /* 0 */ 20000 0, 20001 #endif 20002 }, 20003 { 20004 BCMI_QTC_XGXS_UC_AHB_WRDATA_LSWr, 20005 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 20006 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 20007 BCMI_QTC_XGXS_UC_AHB_WRDATA_LSWr_fields, 20008 #else 20009 0, 20010 #endif 20011 #endif 20012 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 20013 PHYMOD_SYMBOL_FLAG_REGISTER, 20014 "UC_AHB_WRDATA_LSWr", 20015 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 20016 "MICRO_A_AHB_WRDATA_LSW", 20017 NULL, 20018 #endif 20019 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 20020 0x0, /* 0 */ 20021 0, 20022 #endif 20023 }, 20024 { 20025 BCMI_QTC_XGXS_UC_AHB_WRDATA_MSWr, 20026 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 20027 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 20028 BCMI_QTC_XGXS_UC_AHB_WRDATA_MSWr_fields, 20029 #else 20030 0, 20031 #endif 20032 #endif 20033 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 20034 PHYMOD_SYMBOL_FLAG_REGISTER, 20035 "UC_AHB_WRDATA_MSWr", 20036 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 20037 "MICRO_A_AHB_WRDATA_MSW", 20038 NULL, 20039 #endif 20040 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 20041 0x0, /* 0 */ 20042 0, 20043 #endif 20044 }, 20045 { 20046 BCMI_QTC_XGXS_UC_AHB_RDADDR_LSWr, 20047 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 20048 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 20049 BCMI_QTC_XGXS_UC_AHB_RDADDR_LSWr_fields, 20050 #else 20051 0, 20052 #endif 20053 #endif 20054 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 20055 PHYMOD_SYMBOL_FLAG_REGISTER, 20056 "UC_AHB_RDADDR_LSWr", 20057 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 20058 "MICRO_A_AHB_RDADDR_LSW", 20059 NULL, 20060 #endif 20061 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 20062 0x0, /* 0 */ 20063 0, 20064 #endif 20065 }, 20066 { 20067 BCMI_QTC_XGXS_UC_AHB_RDADDR_MSWr, 20068 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 20069 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 20070 BCMI_QTC_XGXS_UC_AHB_RDADDR_MSWr_fields, 20071 #else 20072 0, 20073 #endif 20074 #endif 20075 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 20076 PHYMOD_SYMBOL_FLAG_REGISTER, 20077 "UC_AHB_RDADDR_MSWr", 20078 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 20079 "MICRO_A_AHB_RDADDR_MSW", 20080 NULL, 20081 #endif 20082 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 20083 0x0, /* 0 */ 20084 0, 20085 #endif 20086 }, 20087 { 20088 BCMI_QTC_XGXS_UC_AHB_RDDATA_LSWr, 20089 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 20090 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 20091 BCMI_QTC_XGXS_UC_AHB_RDDATA_LSWr_fields, 20092 #else 20093 0, 20094 #endif 20095 #endif 20096 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 20097 PHYMOD_SYMBOL_FLAG_REGISTER, 20098 "UC_AHB_RDDATA_LSWr", 20099 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 20100 "MICRO_A_AHB_RDDATA_LSW", 20101 NULL, 20102 #endif 20103 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 20104 0x0, /* 0 */ 20105 0, 20106 #endif 20107 }, 20108 { 20109 BCMI_QTC_XGXS_UC_AHB_RDDATA_MSWr, 20110 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 20111 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 20112 BCMI_QTC_XGXS_UC_AHB_RDDATA_MSWr_fields, 20113 #else 20114 0, 20115 #endif 20116 #endif 20117 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 20118 PHYMOD_SYMBOL_FLAG_REGISTER, 20119 "UC_AHB_RDDATA_MSWr", 20120 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 20121 "MICRO_A_AHB_RDDATA_MSW", 20122 NULL, 20123 #endif 20124 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 20125 0x0, /* 0 */ 20126 0, 20127 #endif 20128 }, 20129 { 20130 BCMI_QTC_XGXS_UC_PRAMIF_CTL0r, 20131 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 20132 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 20133 BCMI_QTC_XGXS_UC_PRAMIF_CTL0r_fields, 20134 #else 20135 0, 20136 #endif 20137 #endif 20138 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 20139 PHYMOD_SYMBOL_FLAG_REGISTER, 20140 "UC_PRAMIF_CTL0r", 20141 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 20142 "MICRO_A_PRAMIF_CONTROL0", 20143 NULL, 20144 #endif 20145 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 20146 0x0, /* 0 */ 20147 0, 20148 #endif 20149 }, 20150 { 20151 BCMI_QTC_XGXS_UC_PRAMIF_AHB_WRADDR_LSWr, 20152 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 20153 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 20154 BCMI_QTC_XGXS_UC_PRAMIF_AHB_WRADDR_LSWr_fields, 20155 #else 20156 0, 20157 #endif 20158 #endif 20159 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 20160 PHYMOD_SYMBOL_FLAG_REGISTER, 20161 "UC_PRAMIF_AHB_WRADDR_LSWr", 20162 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 20163 "MICRO_A_PRAMIF_AHB_WRADDR_LSW", 20164 NULL, 20165 #endif 20166 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 20167 0x0, /* 0 */ 20168 0, 20169 #endif 20170 }, 20171 { 20172 BCMI_QTC_XGXS_UC_PRAMIF_AHB_WRADDR_MSWr, 20173 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 20174 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 20175 BCMI_QTC_XGXS_UC_PRAMIF_AHB_WRADDR_MSWr_fields, 20176 #else 20177 0, 20178 #endif 20179 #endif 20180 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 20181 PHYMOD_SYMBOL_FLAG_REGISTER, 20182 "UC_PRAMIF_AHB_WRADDR_MSWr", 20183 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 20184 "MICRO_A_PRAMIF_AHB_WRADDR_MSW", 20185 NULL, 20186 #endif 20187 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 20188 0x0, /* 0 */ 20189 0, 20190 #endif 20191 }, 20192 { 20193 BCMI_QTC_XGXS_UC_PVT_STS0r, 20194 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 20195 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 20196 BCMI_QTC_XGXS_UC_PVT_STS0r_fields, 20197 #else 20198 0, 20199 #endif 20200 #endif 20201 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 20202 PHYMOD_SYMBOL_FLAG_REGISTER, 20203 "UC_PVT_STS0r", 20204 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 20205 "MICRO_B_PVT_STATUS0", 20206 NULL, 20207 #endif 20208 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 20209 0x0, /* 0 */ 20210 0, 20211 #endif 20212 }, 20213 { 20214 BCMI_QTC_XGXS_UC_RMI_TO_UC_MBOX0r, 20215 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 20216 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 20217 BCMI_QTC_XGXS_UC_RMI_TO_UC_MBOX0r_fields, 20218 #else 20219 0, 20220 #endif 20221 #endif 20222 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 20223 PHYMOD_SYMBOL_FLAG_REGISTER, 20224 "UC_RMI_TO_UC_MBOX0r", 20225 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 20226 "MICRO_B_RMI_TO_MICRO_MBOX0", 20227 NULL, 20228 #endif 20229 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 20230 0x0, /* 0 */ 20231 0, 20232 #endif 20233 }, 20234 { 20235 BCMI_QTC_XGXS_UC_RMI_TO_UC_MBOX1r, 20236 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 20237 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 20238 BCMI_QTC_XGXS_UC_RMI_TO_UC_MBOX1r_fields, 20239 #else 20240 0, 20241 #endif 20242 #endif 20243 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 20244 PHYMOD_SYMBOL_FLAG_REGISTER, 20245 "UC_RMI_TO_UC_MBOX1r", 20246 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 20247 "MICRO_B_RMI_TO_MICRO_MBOX1", 20248 NULL, 20249 #endif 20250 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 20251 0x0, /* 0 */ 20252 0, 20253 #endif 20254 }, 20255 { 20256 BCMI_QTC_XGXS_UC_UC_TO_RMI_MBOX0r, 20257 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 20258 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 20259 BCMI_QTC_XGXS_UC_UC_TO_RMI_MBOX0r_fields, 20260 #else 20261 0, 20262 #endif 20263 #endif 20264 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 20265 PHYMOD_SYMBOL_FLAG_REGISTER, 20266 "UC_UC_TO_RMI_MBOX0r", 20267 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 20268 "MICRO_B_MICRO_TO_RMI_MBOX0", 20269 NULL, 20270 #endif 20271 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 20272 0x0, /* 0 */ 20273 0, 20274 #endif 20275 }, 20276 { 20277 BCMI_QTC_XGXS_UC_UC_TO_RMI_MBOX1r, 20278 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 20279 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 20280 BCMI_QTC_XGXS_UC_UC_TO_RMI_MBOX1r_fields, 20281 #else 20282 0, 20283 #endif 20284 #endif 20285 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 20286 PHYMOD_SYMBOL_FLAG_REGISTER, 20287 "UC_UC_TO_RMI_MBOX1r", 20288 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 20289 "MICRO_B_MICRO_TO_RMI_MBOX1", 20290 NULL, 20291 #endif 20292 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 20293 0x0, /* 0 */ 20294 0, 20295 #endif 20296 }, 20297 { 20298 BCMI_QTC_XGXS_UC_RMI_MBOX_CTL0r, 20299 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 20300 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 20301 BCMI_QTC_XGXS_UC_RMI_MBOX_CTL0r_fields, 20302 #else 20303 0, 20304 #endif 20305 #endif 20306 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 20307 PHYMOD_SYMBOL_FLAG_REGISTER, 20308 "UC_RMI_MBOX_CTL0r", 20309 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 20310 "MICRO_B_RMI_MBOX_CONTROL0", 20311 NULL, 20312 #endif 20313 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 20314 0x0, /* 0 */ 20315 0, 20316 #endif 20317 }, 20318 { 20319 BCMI_QTC_XGXS_UC_RMI_AHB_CTL1r, 20320 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 20321 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 20322 BCMI_QTC_XGXS_UC_RMI_AHB_CTL1r_fields, 20323 #else 20324 0, 20325 #endif 20326 #endif 20327 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 20328 PHYMOD_SYMBOL_FLAG_REGISTER, 20329 "UC_RMI_AHB_CTL1r", 20330 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 20331 "MICRO_B_RMI_AHB_CONTROL1", 20332 NULL, 20333 #endif 20334 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 20335 0x7, /* 7 */ 20336 0, 20337 #endif 20338 }, 20339 { 20340 BCMI_QTC_XGXS_UC_RMI_AHB_STS1r, 20341 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 20342 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 20343 BCMI_QTC_XGXS_UC_RMI_AHB_STS1r_fields, 20344 #else 20345 0, 20346 #endif 20347 #endif 20348 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 20349 PHYMOD_SYMBOL_FLAG_REGISTER, 20350 "UC_RMI_AHB_STS1r", 20351 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 20352 "MICRO_B_RMI_AHB_STATUS1", 20353 NULL, 20354 #endif 20355 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 20356 0x0, /* 0 */ 20357 0, 20358 #endif 20359 }, 20360 { 20361 BCMI_QTC_XGXS_UC_RMI_RA_AINC_NXT_WRADDR_LSWr, 20362 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 20363 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 20364 BCMI_QTC_XGXS_UC_RMI_RA_AINC_NXT_WRADDR_LSWr_fields, 20365 #else 20366 0, 20367 #endif 20368 #endif 20369 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 20370 PHYMOD_SYMBOL_FLAG_REGISTER, 20371 "UC_RMI_RA_AINC_NXT_WRADDR_LSWr", 20372 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 20373 "MICRO_B_RMI_RA_AUTOINC_NXT_WRADDR_LSW", 20374 NULL, 20375 #endif 20376 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 20377 0x0, /* 0 */ 20378 0, 20379 #endif 20380 }, 20381 { 20382 BCMI_QTC_XGXS_UC_RMI_RA_AINC_NXT_RDADDR_LSWr, 20383 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 20384 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 20385 BCMI_QTC_XGXS_UC_RMI_RA_AINC_NXT_RDADDR_LSWr_fields, 20386 #else 20387 0, 20388 #endif 20389 #endif 20390 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 20391 PHYMOD_SYMBOL_FLAG_REGISTER, 20392 "UC_RMI_RA_AINC_NXT_RDADDR_LSWr", 20393 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 20394 "MICRO_B_RMI_RA_AUTOINC_NXT_RDADDR_LSW", 20395 NULL, 20396 #endif 20397 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 20398 0x0, /* 0 */ 20399 0, 20400 #endif 20401 }, 20402 { 20403 BCMI_QTC_XGXS_UC_RMI_PR_AINC_NXT_WRADDR_LSWr, 20404 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 20405 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 20406 BCMI_QTC_XGXS_UC_RMI_PR_AINC_NXT_WRADDR_LSWr_fields, 20407 #else 20408 0, 20409 #endif 20410 #endif 20411 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 20412 PHYMOD_SYMBOL_FLAG_REGISTER, 20413 "UC_RMI_PR_AINC_NXT_WRADDR_LSWr", 20414 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 20415 "MICRO_B_RMI_PR_AUTOINC_NXT_WRADDR_LSW", 20416 NULL, 20417 #endif 20418 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 20419 0x0, /* 0 */ 20420 0, 20421 #endif 20422 }, 20423 { 20424 BCMI_QTC_XGXS_UC_RMI_PVT_CTL0r, 20425 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 20426 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 20427 BCMI_QTC_XGXS_UC_RMI_PVT_CTL0r_fields, 20428 #else 20429 0, 20430 #endif 20431 #endif 20432 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 20433 PHYMOD_SYMBOL_FLAG_REGISTER, 20434 "UC_RMI_PVT_CTL0r", 20435 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 20436 "MICRO_B_RMI_PVT_CONTROL0", 20437 NULL, 20438 #endif 20439 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 20440 0x0, /* 0 */ 20441 0, 20442 #endif 20443 }, 20444 { 20445 BCMI_QTC_XGXS_UC_CODE_RAM_ECCCTL0r, 20446 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 20447 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 20448 BCMI_QTC_XGXS_UC_CODE_RAM_ECCCTL0r_fields, 20449 #else 20450 0, 20451 #endif 20452 #endif 20453 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 20454 PHYMOD_SYMBOL_FLAG_REGISTER, 20455 "UC_CODE_RAM_ECCCTL0r", 20456 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 20457 "MICRO_C_CODE_RAM_ECCCONTROL0", 20458 NULL, 20459 #endif 20460 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 20461 0x0, /* 0 */ 20462 0, 20463 #endif 20464 }, 20465 { 20466 BCMI_QTC_XGXS_UC_CODE_RAM_ECCCONTRO1r, 20467 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 20468 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 20469 BCMI_QTC_XGXS_UC_CODE_RAM_ECCCONTRO1r_fields, 20470 #else 20471 0, 20472 #endif 20473 #endif 20474 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 20475 PHYMOD_SYMBOL_FLAG_REGISTER, 20476 "UC_CODE_RAM_ECCCONTRO1r", 20477 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 20478 "MICRO_C_CODE_RAM_ECCCONTRO1", 20479 NULL, 20480 #endif 20481 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 20482 0x0, /* 0 */ 20483 0, 20484 #endif 20485 }, 20486 { 20487 BCMI_QTC_XGXS_UC_CODE_RAM_ECCSTS0r, 20488 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 20489 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 20490 BCMI_QTC_XGXS_UC_CODE_RAM_ECCSTS0r_fields, 20491 #else 20492 0, 20493 #endif 20494 #endif 20495 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 20496 PHYMOD_SYMBOL_FLAG_REGISTER, 20497 "UC_CODE_RAM_ECCSTS0r", 20498 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 20499 "MICRO_C_CODE_RAM_ECCSTATUS0", 20500 NULL, 20501 #endif 20502 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 20503 0x0, /* 0 */ 20504 0, 20505 #endif 20506 }, 20507 { 20508 BCMI_QTC_XGXS_UC_CODE_RAM_ECCSTS1r, 20509 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 20510 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 20511 BCMI_QTC_XGXS_UC_CODE_RAM_ECCSTS1r_fields, 20512 #else 20513 0, 20514 #endif 20515 #endif 20516 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 20517 PHYMOD_SYMBOL_FLAG_REGISTER, 20518 "UC_CODE_RAM_ECCSTS1r", 20519 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 20520 "MICRO_C_CODE_RAM_ECCSTATUS1", 20521 NULL, 20522 #endif 20523 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 20524 0x0, /* 0 */ 20525 0, 20526 #endif 20527 }, 20528 { 20529 BCMI_QTC_XGXS_UC_CODE_RAM_TESTIFCTL0r, 20530 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 20531 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 20532 BCMI_QTC_XGXS_UC_CODE_RAM_TESTIFCTL0r_fields, 20533 #else 20534 0, 20535 #endif 20536 #endif 20537 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 20538 PHYMOD_SYMBOL_FLAG_REGISTER, 20539 "UC_CODE_RAM_TESTIFCTL0r", 20540 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 20541 "MICRO_C_CODE_RAM_TESTIFCONTROL0", 20542 NULL, 20543 #endif 20544 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 20545 0x0, /* 0 */ 20546 0, 20547 #endif 20548 }, 20549 { 20550 BCMI_QTC_XGXS_UC_RAM_CTL0r, 20551 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 20552 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 20553 BCMI_QTC_XGXS_UC_RAM_CTL0r_fields, 20554 #else 20555 0, 20556 #endif 20557 #endif 20558 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 20559 PHYMOD_SYMBOL_FLAG_REGISTER, 20560 "UC_RAM_CTL0r", 20561 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 20562 "MICRO_C_RAM_CONTROL0", 20563 NULL, 20564 #endif 20565 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 20566 0x8401, /* 33793 */ 20567 0, 20568 #endif 20569 }, 20570 { 20571 BCMI_QTC_XGXS_UC_RMI_EXT_INTR_CTL0r, 20572 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 20573 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 20574 BCMI_QTC_XGXS_UC_RMI_EXT_INTR_CTL0r_fields, 20575 #else 20576 0, 20577 #endif 20578 #endif 20579 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 20580 PHYMOD_SYMBOL_FLAG_REGISTER, 20581 "UC_RMI_EXT_INTR_CTL0r", 20582 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 20583 "MICRO_C_RMI_EXT_INTR_CONTROL0", 20584 NULL, 20585 #endif 20586 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 20587 0x0, /* 0 */ 20588 0, 20589 #endif 20590 }, 20591 { 20592 BCMI_QTC_XGXS_UC_RMI_EXT_INTR_STS0r, 20593 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 20594 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 20595 BCMI_QTC_XGXS_UC_RMI_EXT_INTR_STS0r_fields, 20596 #else 20597 0, 20598 #endif 20599 #endif 20600 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 20601 PHYMOD_SYMBOL_FLAG_REGISTER, 20602 "UC_RMI_EXT_INTR_STS0r", 20603 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 20604 "MICRO_C_RMI_EXT_INTR_STATUS0", 20605 NULL, 20606 #endif 20607 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 20608 0x0, /* 0 */ 20609 0, 20610 #endif 20611 }, 20612 { 20613 BCMI_QTC_XGXS_UC_RMI_PMI_IF_CTL0r, 20614 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 20615 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 20616 BCMI_QTC_XGXS_UC_RMI_PMI_IF_CTL0r_fields, 20617 #else 20618 0, 20619 #endif 20620 #endif 20621 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 20622 PHYMOD_SYMBOL_FLAG_REGISTER, 20623 "UC_RMI_PMI_IF_CTL0r", 20624 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 20625 "MICRO_C_RMI_PMI_IF_CONTROL0", 20626 NULL, 20627 #endif 20628 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 20629 0x101, /* 257 */ 20630 0, 20631 #endif 20632 }, 20633 { 20634 BCMI_QTC_XGXS_UC_RMI_SILICON_DBG_CTL0r, 20635 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 20636 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 20637 BCMI_QTC_XGXS_UC_RMI_SILICON_DBG_CTL0r_fields, 20638 #else 20639 0, 20640 #endif 20641 #endif 20642 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 20643 PHYMOD_SYMBOL_FLAG_REGISTER, 20644 "UC_RMI_SILICON_DBG_CTL0r", 20645 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 20646 "MICRO_C_RMI_SILICON_DEBUG_CONTROL0", 20647 NULL, 20648 #endif 20649 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 20650 0x0, /* 0 */ 20651 0, 20652 #endif 20653 }, 20654 { 20655 BCMI_QTC_XGXS_UC_RMI_SILICON_DBG_STS0r, 20656 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 20657 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 20658 BCMI_QTC_XGXS_UC_RMI_SILICON_DBG_STS0r_fields, 20659 #else 20660 0, 20661 #endif 20662 #endif 20663 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 20664 PHYMOD_SYMBOL_FLAG_REGISTER, 20665 "UC_RMI_SILICON_DBG_STS0r", 20666 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 20667 "MICRO_C_RMI_SILICON_DEBUG_STATUS0", 20668 NULL, 20669 #endif 20670 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 20671 0x0, /* 0 */ 20672 0, 20673 #endif 20674 }, 20675 { 20676 BCMI_QTC_XGXS_MDIO_BCST_PORT_ADDRr, 20677 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 20678 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 20679 BCMI_QTC_XGXS_MDIO_BCST_PORT_ADDRr_fields, 20680 #else 20681 0, 20682 #endif 20683 #endif 20684 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 20685 PHYMOD_SYMBOL_FLAG_REGISTER, 20686 "MDIO_BCST_PORT_ADDRr", 20687 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 20688 "MDIO_MMDSEL_AER_MDIO_BRCST_PORT_ADDR", 20689 NULL, 20690 #endif 20691 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 20692 0x1f, /* 31 */ 20693 0, 20694 #endif 20695 }, 20696 { 20697 BCMI_QTC_XGXS_MDIO_MMD_SELr, 20698 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 20699 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 20700 BCMI_QTC_XGXS_MDIO_MMD_SELr_fields, 20701 #else 20702 0, 20703 #endif 20704 #endif 20705 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 20706 PHYMOD_SYMBOL_FLAG_REGISTER, 20707 "MDIO_MMD_SELr", 20708 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 20709 "MDIO_MMDSEL_AER_MDIO_MMD_SELECT", 20710 NULL, 20711 #endif 20712 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 20713 0x404d, /* 16461 */ 20714 0, 20715 #endif 20716 }, 20717 { 20718 BCMI_QTC_XGXS_MDIO_AERr, 20719 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 20720 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 20721 BCMI_QTC_XGXS_MDIO_AERr_fields, 20722 #else 20723 0, 20724 #endif 20725 #endif 20726 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 20727 PHYMOD_SYMBOL_FLAG_REGISTER, 20728 "MDIO_AERr", 20729 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 20730 "MDIO_MMDSEL_AER_MDIO_AER", 20731 NULL, 20732 #endif 20733 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 20734 0x0, /* 0 */ 20735 0, 20736 #endif 20737 }, 20738 { 20739 BCMI_QTC_XGXS_BLK_ADDRr, 20740 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 20741 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_QTC_XGXS 20742 BCMI_QTC_XGXS_BLK_ADDRr_fields, 20743 #else 20744 0, 20745 #endif 20746 #endif 20747 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 20748 PHYMOD_SYMBOL_FLAG_REGISTER, 20749 "BLK_ADDRr", 20750 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 20751 "MDIO_BLK_ADDR_BLK_ADDR", 20752 NULL, 20753 #endif 20754 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 20755 0x0, /* 0 */ 20756 0, 20757 #endif 20758 }, 20759 #endif 20760 }; 20761 20762 20763 phymod_symbols_t bcmi_qtce16_xgxs_symbols = 20764 { 20765 bcmi_qtc_xgxs_syms, sizeof(bcmi_qtc_xgxs_syms)/sizeof(bcmi_qtc_xgxs_syms[0]), 20766 #if PHYMOD_CONFIG_INCLUDE_FIELD_NAMES == 1 20767 bcmi_qtc_xgxs_fields 20768 #else 20769 NULL 20770 #endif 20771 /* END OF SYMBOL FILE */ 20772 }; 20773 20774 #endif /* PHYMOD_CONFIG_INCLUDE_CHIP_SYMBOLS */