bcmi_falcon_xgxs_sym.c (241380B)
1 /******************************************************************************* 2 * 3 * 4 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 5 * 6 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 7 * 8 * DO NOT EDIT THIS FILE! 9 * This file is auto-generated from the registers file. 10 * Edits to this file will be lost when it is regenerated. 11 * 12 * Symbol table file for the BCMI_FALCON_XGXS. 13 * This symbol table is used by the Broadcom debug shell. 14 */ 15 16 17 #include <phymod/chip/bcmi_falcon_xgxs_defs.h> 18 #include <phymod/phymod_symbols.h> 19 20 /* No symbols will be compiled unless this is defined. */ 21 #if PHYMOD_CONFIG_INCLUDE_CHIP_SYMBOLS == 1 22 /******************************************************************************* 23 * 24 * If PHYMOD_CONFIG_INCLUDE_FIELD_INFO is 1, then symbol information 25 * necessary to encode and decode the individual fields of a register or memory 26 * will be available. 27 * 28 * Without it, only the register and memory names will be symbolically available 29 * and their values will be displayed as raw data only. 30 * 31 * Field information can be compiled out in the interest of saving code space. 32 */ 33 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 34 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 35 36 static uint32_t BCMI_FALCON_XGXS_ACC_ADDR_DATAr_fields[] = 37 { 38 /* MDIO_ADDR_DATA:0:15 */ 39 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(361, 15, 0) 40 }; 41 static uint32_t BCMI_FALCON_XGXS_ACC_CTLr_fields[] = 42 { 43 /* MDIO_DEVAD:0:4 */ 44 PHYMOD_SYMBOL_FIELD_ENCODE(365, 4, 0), 45 /* MDIO_FUNCTION:14:15 */ 46 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(372, 15, 14) 47 }; 48 static uint32_t BCMI_FALCON_XGXS_AMS_PLL_CTL0r_fields[] = 49 { 50 /* AMS_PLL_SET_CLK4TSC:0:1 */ 51 PHYMOD_SYMBOL_FIELD_ENCODE(75, 1, 0), 52 /* AMS_PLL_IMIN_ICLKINT:2:2 */ 53 PHYMOD_SYMBOL_FIELD_ENCODE(44, 2, 2), 54 /* AMS_PLL_IMAX_ICLKINT:3:3 */ 55 PHYMOD_SYMBOL_FIELD_ENCODE(33, 3, 3), 56 /* AMS_PLL_IMODE_ICLKINT:4:4 */ 57 PHYMOD_SYMBOL_FIELD_ENCODE(55, 4, 4), 58 /* AMS_PLL_IMIN_ICLKODRV1:5:5 */ 59 PHYMOD_SYMBOL_FIELD_ENCODE(45, 5, 5), 60 /* AMS_PLL_IMAX_ICLKODRV1:6:6 */ 61 PHYMOD_SYMBOL_FIELD_ENCODE(34, 6, 6), 62 /* AMS_PLL_IMODE_ICLKODRV1:7:7 */ 63 PHYMOD_SYMBOL_FIELD_ENCODE(56, 7, 7), 64 /* AMS_PLL_IMIN_ICLKIDRV1:8:8 */ 65 PHYMOD_SYMBOL_FIELD_ENCODE(43, 8, 8), 66 /* AMS_PLL_IMAX_ICLKIDRV1:9:9 */ 67 PHYMOD_SYMBOL_FIELD_ENCODE(32, 9, 9), 68 /* AMS_PLL_IMODE_ICLKIDRV1:10:10 */ 69 PHYMOD_SYMBOL_FIELD_ENCODE(54, 10, 10), 70 /* AMS_PLL_CAL_OFF:11:11 */ 71 PHYMOD_SYMBOL_FIELD_ENCODE(22, 11, 11), 72 /* AMS_PLL_CAL_AUX:12:15 */ 73 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(21, 15, 12) 74 }; 75 static uint32_t BCMI_FALCON_XGXS_AMS_PLL_CTL1r_fields[] = 76 { 77 /* AMS_PLL_IMIN_ICKGEN:0:0 */ 78 PHYMOD_SYMBOL_FIELD_ENCODE(42, 0, 0), 79 /* AMS_PLL_IMAX_ICKGEN:1:1 */ 80 PHYMOD_SYMBOL_FIELD_ENCODE(31, 1, 1), 81 /* AMS_PLL_IMODE_ICKGEN:2:2 */ 82 PHYMOD_SYMBOL_FIELD_ENCODE(53, 2, 2), 83 /* AMS_PLL_DRV_HV_DISABLE:3:3 */ 84 PHYMOD_SYMBOL_FIELD_ENCODE(24, 3, 3), 85 /* AMS_PLL_TEST_BG_OPAMP_BIAS:4:5 */ 86 PHYMOD_SYMBOL_FIELD_ENCODE(80, 5, 4), 87 /* AMS_PLL_SPARE_23_22:6:7 */ 88 PHYMOD_SYMBOL_FIELD_ENCODE(78, 7, 6), 89 /* AMS_PLL_VCOICTRL:8:9 */ 90 PHYMOD_SYMBOL_FIELD_ENCODE(88, 9, 8), 91 /* AMS_PLL_VCO_INDICATOR:10:10 */ 92 PHYMOD_SYMBOL_FIELD_ENCODE(89, 10, 10), 93 /* AMS_PLL_IVCO:11:13 */ 94 PHYMOD_SYMBOL_FIELD_ENCODE(63, 13, 11), 95 /* AMS_PLL_RESET:14:14 */ 96 PHYMOD_SYMBOL_FIELD_ENCODE(74, 14, 14), 97 /* AMS_PLL_ENABLE_FTUNE:15:15 */ 98 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(25, 15, 15) 99 }; 100 static uint32_t BCMI_FALCON_XGXS_AMS_PLL_CTL2r_fields[] = 101 { 102 /* AMS_PLL_EN_HRZ:0:0 */ 103 PHYMOD_SYMBOL_FIELD_ENCODE(26, 0, 0), 104 /* AMS_PLL_IQP:1:4 */ 105 PHYMOD_SYMBOL_FIELD_ENCODE(62, 4, 1), 106 /* AMS_PLL_REFL_PLL:5:5 */ 107 PHYMOD_SYMBOL_FIELD_ENCODE(73, 5, 5), 108 /* AMS_PLL_REFH_PLL:6:6 */ 109 PHYMOD_SYMBOL_FIELD_ENCODE(72, 6, 6), 110 /* AMS_PLL_IMIN_IBIAS:7:7 */ 111 PHYMOD_SYMBOL_FIELD_ENCODE(40, 7, 7), 112 /* AMS_PLL_IMODE_IBIAS:8:8 */ 113 PHYMOD_SYMBOL_FIELD_ENCODE(51, 8, 8), 114 /* AMS_PLL_IMAX_IBIAS:9:9 */ 115 PHYMOD_SYMBOL_FIELD_ENCODE(29, 9, 9), 116 /* AMS_PLL_IMIN_ICP:10:10 */ 117 PHYMOD_SYMBOL_FIELD_ENCODE(48, 10, 10), 118 /* AMS_PLL_IMODE_ICP:11:11 */ 119 PHYMOD_SYMBOL_FIELD_ENCODE(59, 11, 11), 120 /* AMS_PLL_IMAX_ICP:12:12 */ 121 PHYMOD_SYMBOL_FIELD_ENCODE(37, 12, 12), 122 /* AMS_PLL_IMIN_ICK:13:13 */ 123 PHYMOD_SYMBOL_FIELD_ENCODE(41, 13, 13), 124 /* AMS_PLL_IMODE_ICK:14:14 */ 125 PHYMOD_SYMBOL_FIELD_ENCODE(52, 14, 14), 126 /* AMS_PLL_IMAX_ICK:15:15 */ 127 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(30, 15, 15) 128 }; 129 static uint32_t BCMI_FALCON_XGXS_AMS_PLL_CTL3r_fields[] = 130 { 131 /* AMS_PLL_IMIN_IRXCLKBUF:0:0 */ 132 PHYMOD_SYMBOL_FIELD_ENCODE(50, 0, 0), 133 /* AMS_PLL_IMODE_IRXCLKBUF:1:1 */ 134 PHYMOD_SYMBOL_FIELD_ENCODE(61, 1, 1), 135 /* AMS_PLL_IMAX_IRXCLKBUF:2:2 */ 136 PHYMOD_SYMBOL_FIELD_ENCODE(39, 2, 2), 137 /* AMS_PLL_IMIN_ICMLDIV:3:3 */ 138 PHYMOD_SYMBOL_FIELD_ENCODE(46, 3, 3), 139 /* AMS_PLL_IMODE_ICMLDIV:4:4 */ 140 PHYMOD_SYMBOL_FIELD_ENCODE(57, 4, 4), 141 /* AMS_PLL_IMAX_ICMLDIV:5:5 */ 142 PHYMOD_SYMBOL_FIELD_ENCODE(35, 5, 5), 143 /* AMS_PLL_IMIN_ICOMP:6:6 */ 144 PHYMOD_SYMBOL_FIELD_ENCODE(47, 6, 6), 145 /* AMS_PLL_IMODE_ICOMP:7:7 */ 146 PHYMOD_SYMBOL_FIELD_ENCODE(58, 7, 7), 147 /* AMS_PLL_IMAX_ICOMP:8:8 */ 148 PHYMOD_SYMBOL_FIELD_ENCODE(36, 8, 8), 149 /* AMS_PLL_IMIN_IOP:9:9 */ 150 PHYMOD_SYMBOL_FIELD_ENCODE(49, 9, 9), 151 /* AMS_PLL_IMODE_IOP:10:10 */ 152 PHYMOD_SYMBOL_FIELD_ENCODE(60, 10, 10), 153 /* AMS_PLL_IMAX_IOP:11:11 */ 154 PHYMOD_SYMBOL_FIELD_ENCODE(38, 11, 11), 155 /* AMS_PLL_TEST_VREF:12:12 */ 156 PHYMOD_SYMBOL_FIELD_ENCODE(86, 12, 12), 157 /* AMS_PLL_TEST_VC:13:13 */ 158 PHYMOD_SYMBOL_FIELD_ENCODE(85, 13, 13), 159 /* AMS_PLL_TEST_PLL:14:14 */ 160 PHYMOD_SYMBOL_FIELD_ENCODE(81, 14, 14), 161 /* AMS_PLL_TEST_RX:15:15 */ 162 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(84, 15, 15) 163 }; 164 static uint32_t BCMI_FALCON_XGXS_AMS_PLL_CTL4r_fields[] = 165 { 166 /* AMS_PLL_BGR_PTATADJ:0:3 */ 167 PHYMOD_SYMBOL_FIELD_ENCODE(20, 3, 0), 168 /* AMS_PLL_BGR_CTATADJ:4:7 */ 169 PHYMOD_SYMBOL_FIELD_ENCODE(19, 7, 4), 170 /* AMS_PLL_PLL2RX_CLKBW:8:9 */ 171 PHYMOD_SYMBOL_FIELD_ENCODE(71, 9, 8), 172 /* AMS_PLL_COMP_VTH:10:10 */ 173 PHYMOD_SYMBOL_FIELD_ENCODE(23, 10, 10), 174 /* AMS_PLL_VDDR_BGB:11:11 */ 175 PHYMOD_SYMBOL_FIELD_ENCODE(90, 11, 11), 176 /* AMS_PLL_KVH_FORCE:12:13 */ 177 PHYMOD_SYMBOL_FIELD_ENCODE(64, 13, 12), 178 /* AMS_PLL_FORCE_KVH_BW:14:14 */ 179 PHYMOD_SYMBOL_FIELD_ENCODE(27, 14, 14), 180 /* AMS_PLL_FORCE_RESCAL:15:15 */ 181 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(28, 15, 15) 182 }; 183 static uint32_t BCMI_FALCON_XGXS_AMS_PLL_CTL5r_fields[] = 184 { 185 /* AMS_PLL_TEST_PORT_MAX_AMPLITUDE:0:0 */ 186 PHYMOD_SYMBOL_FIELD_ENCODE(83, 0, 0), 187 /* AMS_PLL_BGIP:1:1 */ 188 PHYMOD_SYMBOL_FIELD_ENCODE(18, 1, 1), 189 /* AMS_PLL_BGINT:2:2 */ 190 PHYMOD_SYMBOL_FIELD_ENCODE(17, 2, 2), 191 /* AMS_PLL_VBYPASS:3:3 */ 192 PHYMOD_SYMBOL_FIELD_ENCODE(87, 3, 3), 193 /* AMS_PLL_TEST_PNP:4:5 */ 194 PHYMOD_SYMBOL_FIELD_ENCODE(82, 5, 4), 195 /* AMS_PLL_MIX3P1C_CALR_CTATADJ:6:10 */ 196 PHYMOD_SYMBOL_FIELD_ENCODE(69, 10, 6), 197 /* AMS_PLL_MIX3P1C_CALR_PTATADJ:11:15 */ 198 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(70, 15, 11) 199 }; 200 static uint32_t BCMI_FALCON_XGXS_AMS_PLL_CTL6r_fields[] = 201 { 202 /* AMS_PLL_SPARE_101_96:0:5 */ 203 PHYMOD_SYMBOL_FIELD_ENCODE(76, 5, 0), 204 /* AMS_PLL_MIX1P2CR_CTATADJ:6:10 */ 205 PHYMOD_SYMBOL_FIELD_ENCODE(65, 10, 6), 206 /* AMS_PLL_MIX1P2CR_PTATADJ:11:15 */ 207 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(66, 15, 11) 208 }; 209 static uint32_t BCMI_FALCON_XGXS_AMS_PLL_CTL7r_fields[] = 210 { 211 /* AMS_PLL_SPARE_117_112:0:5 */ 212 PHYMOD_SYMBOL_FIELD_ENCODE(77, 5, 0), 213 /* AMS_PLL_MIX3P1CR_CTATADJ:6:10 */ 214 PHYMOD_SYMBOL_FIELD_ENCODE(67, 10, 6), 215 /* AMS_PLL_MIX3P1CR_PTATADJ:11:15 */ 216 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(68, 15, 11) 217 }; 218 static uint32_t BCMI_FALCON_XGXS_AMS_PLL_STSr_fields[] = 219 { 220 /* AMS_PLL_STS:0:15 */ 221 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(79, 15, 0) 222 }; 223 static uint32_t BCMI_FALCON_XGXS_AMS_RX_CTL0r_fields[] = 224 { 225 /* AMS_RX_MASTER_DIODES_IBIAS:0:2 */ 226 PHYMOD_SYMBOL_FIELD_ENCODE(109, 2, 0), 227 /* AMS_RX_SIGDET_THRESHOLD:3:5 */ 228 PHYMOD_SYMBOL_FIELD_ENCODE(127, 5, 3), 229 /* AMS_RX_SIGDET_PWRDN:6:6 */ 230 PHYMOD_SYMBOL_FIELD_ENCODE(126, 6, 6), 231 /* AMS_RX_SIGDET_BYPASS:7:7 */ 232 PHYMOD_SYMBOL_FIELD_ENCODE(123, 7, 7), 233 /* AMS_RX_TPORT_EN:8:8 */ 234 PHYMOD_SYMBOL_FIELD_ENCODE(140, 8, 8), 235 /* AMS_RX_VGA_10G_BW:9:9 */ 236 PHYMOD_SYMBOL_FIELD_ENCODE(149, 9, 9), 237 /* AMS_RX_EQ_LZ_EN:10:10 */ 238 PHYMOD_SYMBOL_FIELD_ENCODE(107, 10, 10), 239 /* AMS_RX_DFE_HGAIN_EN:11:11 */ 240 PHYMOD_SYMBOL_FIELD_ENCODE(100, 11, 11), 241 /* AMS_RX_DC_COUPLE:12:12 */ 242 PHYMOD_SYMBOL_FIELD_ENCODE(97, 12, 12), 243 /* AMS_RX_PEAKING_FILTER_IBIAS:13:15 */ 244 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(114, 15, 13) 245 }; 246 static uint32_t BCMI_FALCON_XGXS_AMS_RX_CTL1r_fields[] = 247 { 248 /* AMS_RX_SPARE_16:0:0 */ 249 PHYMOD_SYMBOL_FIELD_ENCODE(134, 0, 0), 250 /* AMS_RX_VGA0_IBIAS:1:3 */ 251 PHYMOD_SYMBOL_FIELD_ENCODE(141, 3, 1), 252 /* AMS_RX_VGA1_IBIAS:4:6 */ 253 PHYMOD_SYMBOL_FIELD_ENCODE(143, 6, 4), 254 /* AMS_RX_VGA2_IBIAS:7:9 */ 255 PHYMOD_SYMBOL_FIELD_ENCODE(145, 9, 7), 256 /* AMS_RX_VGA3_IBIAS:10:12 */ 257 PHYMOD_SYMBOL_FIELD_ENCODE(147, 12, 10), 258 /* AMS_RX_CM_VOLTAGE_IBIAS:13:15 */ 259 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(92, 15, 13) 260 }; 261 static uint32_t BCMI_FALCON_XGXS_AMS_RX_CTL2r_fields[] = 262 { 263 /* AMS_RX_SIGDET_IBIAS:0:2 */ 264 PHYMOD_SYMBOL_FIELD_ENCODE(124, 2, 0), 265 /* AMS_RX_PHASE_INTERPOLATORS_IBIAS:3:5 */ 266 PHYMOD_SYMBOL_FIELD_ENCODE(116, 5, 3), 267 /* AMS_RX_DFE_TAP_WEIGHT_IBIAS:6:8 */ 268 PHYMOD_SYMBOL_FIELD_ENCODE(104, 8, 6), 269 /* AMS_RX_SEL_UGBW:9:10 */ 270 PHYMOD_SYMBOL_FIELD_ENCODE(121, 10, 9), 271 /* AMS_RX_SEL_TH4DFE:11:12 */ 272 PHYMOD_SYMBOL_FIELD_ENCODE(120, 12, 11), 273 /* AMS_RX_PD_CH_P1:13:13 */ 274 PHYMOD_SYMBOL_FIELD_ENCODE(113, 13, 13), 275 /* AMS_RX_SIGDET_POWER_SAVE:14:14 */ 276 PHYMOD_SYMBOL_FIELD_ENCODE(125, 14, 14), 277 /* AMS_RX_PWRDN_FTAP:15:15 */ 278 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(117, 15, 15) 279 }; 280 static uint32_t BCMI_FALCON_XGXS_AMS_RX_CTL3r_fields[] = 281 { 282 /* AMS_RX_MET_R_IBIAS:0:2 */ 283 PHYMOD_SYMBOL_FIELD_ENCODE(110, 2, 0), 284 /* AMS_RX_DLL_IBIAS:3:5 */ 285 PHYMOD_SYMBOL_FIELD_ENCODE(105, 5, 3), 286 /* AMS_RX_OFFSET_CORRECTION_IBIAS:6:8 */ 287 PHYMOD_SYMBOL_FIELD_ENCODE(111, 8, 6), 288 /* AMS_RX_DFE_SUM_BUF_IBIAS:9:11 */ 289 PHYMOD_SYMBOL_FIELD_ENCODE(103, 11, 9), 290 /* AMS_RX_DFE_SLICER_IBIAS:12:14 */ 291 PHYMOD_SYMBOL_FIELD_ENCODE(102, 14, 12), 292 /* AMS_RX_SPARE_63:15:15 */ 293 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(135, 15, 15) 294 }; 295 static uint32_t BCMI_FALCON_XGXS_AMS_RX_CTL4r_fields[] = 296 { 297 /* AMS_RX_DFE_SLICER_CAL_IBIAS:0:2 */ 298 PHYMOD_SYMBOL_FIELD_ENCODE(101, 2, 0), 299 /* AMS_RX_TBD_IBIAS:3:5 */ 300 PHYMOD_SYMBOL_FIELD_ENCODE(138, 5, 3), 301 /* AMS_RX_VGA0_RESCAL_MUX:6:10 */ 302 PHYMOD_SYMBOL_FIELD_ENCODE(142, 10, 6), 303 /* AMS_RX_VGA1_RESCAL_MUX:11:15 */ 304 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(144, 15, 11) 305 }; 306 static uint32_t BCMI_FALCON_XGXS_AMS_RX_CTL5r_fields[] = 307 { 308 /* AMS_RX_VGA2_RESCAL_MUX:0:4 */ 309 PHYMOD_SYMBOL_FIELD_ENCODE(146, 4, 0), 310 /* AMS_RX_VGA3_RESCAL_MUX:5:9 */ 311 PHYMOD_SYMBOL_FIELD_ENCODE(148, 9, 5), 312 /* AMS_RX_TERMINATION_RESISTOR_RESCAL_MUX:10:14 */ 313 PHYMOD_SYMBOL_FIELD_ENCODE(139, 14, 10), 314 /* AMS_RX_SPARE_95:15:15 */ 315 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(136, 15, 15) 316 }; 317 static uint32_t BCMI_FALCON_XGXS_AMS_RX_CTL6r_fields[] = 318 { 319 /* AMS_RX_PEAKING_FILTER_RESCAL_MUX:0:3 */ 320 PHYMOD_SYMBOL_FIELD_ENCODE(115, 3, 0), 321 /* AMS_RX_OFFSET_CORRECTION_RESCAL_MUX:4:7 */ 322 PHYMOD_SYMBOL_FIELD_ENCODE(112, 7, 4), 323 /* AMS_RX_SPARE_111_104:8:15 */ 324 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(128, 15, 8) 325 }; 326 static uint32_t BCMI_FALCON_XGXS_AMS_RX_CTL7r_fields[] = 327 { 328 /* AMS_RX_DC_OFFSET:0:6 */ 329 PHYMOD_SYMBOL_FIELD_ENCODE(98, 6, 0), 330 /* AMS_RX_FORCE_DC_OFFSET:7:7 */ 331 PHYMOD_SYMBOL_FIELD_ENCODE(108, 7, 7), 332 /* AMS_RX_DC_OFFSET_RANGE:8:8 */ 333 PHYMOD_SYMBOL_FIELD_ENCODE(99, 8, 8), 334 /* AMS_RX_RX_OFFSET_PD:9:9 */ 335 PHYMOD_SYMBOL_FIELD_ENCODE(118, 9, 9), 336 /* AMS_RX_SHORT_VGA_OUTPUT:10:10 */ 337 PHYMOD_SYMBOL_FIELD_ENCODE(122, 10, 10), 338 /* AMS_RX_SPARE_123:11:11 */ 339 PHYMOD_SYMBOL_FIELD_ENCODE(129, 11, 11), 340 /* AMS_RX_VGA_LOW_GAIN:12:13 */ 341 PHYMOD_SYMBOL_FIELD_ENCODE(150, 13, 12), 342 /* AMS_RX_VGA_STEP_MODE:14:15 */ 343 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(151, 15, 14) 344 }; 345 static uint32_t BCMI_FALCON_XGXS_AMS_RX_CTL8r_fields[] = 346 { 347 /* AMS_RX_DAC4CK_LMS:0:5 */ 348 PHYMOD_SYMBOL_FIELD_ENCODE(95, 5, 0), 349 /* AMS_RX_SPARE_135_134:6:7 */ 350 PHYMOD_SYMBOL_FIELD_ENCODE(130, 7, 6), 351 /* AMS_RX_DAC4CK_PHS:8:13 */ 352 PHYMOD_SYMBOL_FIELD_ENCODE(96, 13, 8), 353 /* AMS_RX_SPARE_143_142:14:15 */ 354 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(131, 15, 14) 355 }; 356 static uint32_t BCMI_FALCON_XGXS_AMS_RX_CTL9r_fields[] = 357 { 358 /* AMS_RX_DAC4CK_DAT:0:5 */ 359 PHYMOD_SYMBOL_FIELD_ENCODE(94, 5, 0), 360 /* AMS_RX_SPARE_151_150:6:7 */ 361 PHYMOD_SYMBOL_FIELD_ENCODE(132, 7, 6), 362 /* AMS_RX_CLK_BW_CTRL:8:9 */ 363 PHYMOD_SYMBOL_FIELD_ENCODE(91, 9, 8), 364 /* AMS_RX_EN_TAP9DELAY:10:10 */ 365 PHYMOD_SYMBOL_FIELD_ENCODE(106, 10, 10), 366 /* AMS_RX_SEL_D2CLP:11:11 */ 367 PHYMOD_SYMBOL_FIELD_ENCODE(119, 11, 11), 368 /* AMS_RX_D2C_CLKBUF_IBIAS:12:14 */ 369 PHYMOD_SYMBOL_FIELD_ENCODE(93, 14, 12), 370 /* AMS_RX_SPARE_159:15:15 */ 371 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(133, 15, 15) 372 }; 373 static uint32_t BCMI_FALCON_XGXS_AMS_RX_STSr_fields[] = 374 { 375 /* AMS_RX_STS:0:15 */ 376 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(137, 15, 0) 377 }; 378 static uint32_t BCMI_FALCON_XGXS_AMS_TX_CTL0r_fields[] = 379 { 380 /* AMS_TX_SPARE_0:0:0 */ 381 PHYMOD_SYMBOL_FIELD_ENCODE(168, 0, 0), 382 /* AMS_TX_SPARE_3_1:1:3 */ 383 PHYMOD_SYMBOL_FIELD_ENCODE(171, 3, 1), 384 /* AMS_TX_TEST_DATA:4:5 */ 385 PHYMOD_SYMBOL_FIELD_ENCODE(174, 5, 4), 386 /* AMS_TX_TICKSEL:6:7 */ 387 PHYMOD_SYMBOL_FIELD_ENCODE(175, 7, 6), 388 /* AMS_TX_VDDR_BGB:8:8 */ 389 PHYMOD_SYMBOL_FIELD_ENCODE(176, 8, 8), 390 /* AMS_TX_DCC_SEL:9:9 */ 391 PHYMOD_SYMBOL_FIELD_ENCODE(156, 9, 9), 392 /* AMS_TX_DCC_DIS:10:10 */ 393 PHYMOD_SYMBOL_FIELD_ENCODE(155, 10, 10), 394 /* AMS_TX_CAL_OFF:11:11 */ 395 PHYMOD_SYMBOL_FIELD_ENCODE(154, 11, 11), 396 /* AMS_TX_CAL_AUX:12:15 */ 397 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(153, 15, 12) 398 }; 399 static uint32_t BCMI_FALCON_XGXS_AMS_TX_CTL1r_fields[] = 400 { 401 /* AMS_TX_IBIAS:0:2 */ 402 PHYMOD_SYMBOL_FIELD_ENCODE(159, 2, 0), 403 /* AMS_TX_SPARE_21_19:3:5 */ 404 PHYMOD_SYMBOL_FIELD_ENCODE(169, 5, 3), 405 /* AMS_TX_ICML:6:8 */ 406 PHYMOD_SYMBOL_FIELD_ENCODE(160, 8, 6), 407 /* AMS_TX_ILDO:9:11 */ 408 PHYMOD_SYMBOL_FIELD_ENCODE(161, 11, 9), 409 /* AMS_TX_LDO_VREF:12:13 */ 410 PHYMOD_SYMBOL_FIELD_ENCODE(162, 13, 12), 411 /* AMS_TX_SEL_EMPH_MODE:14:14 */ 412 PHYMOD_SYMBOL_FIELD_ENCODE(165, 14, 14), 413 /* AMS_TX_SPARE_31:15:15 */ 414 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(170, 15, 15) 415 }; 416 static uint32_t BCMI_FALCON_XGXS_AMS_TX_CTL2r_fields[] = 417 { 418 /* AMS_TX_AMP_CTL:0:3 */ 419 PHYMOD_SYMBOL_FIELD_ENCODE(152, 3, 0), 420 /* AMS_TX_POST3_COEF:4:6 */ 421 PHYMOD_SYMBOL_FIELD_ENCODE(164, 6, 4), 422 /* AMS_TX_SIGN_POST3:7:7 */ 423 PHYMOD_SYMBOL_FIELD_ENCODE(167, 7, 7), 424 /* AMS_TX_POST2_COEF:8:11 */ 425 PHYMOD_SYMBOL_FIELD_ENCODE(163, 11, 8), 426 /* AMS_TX_SIGN_POST2:12:12 */ 427 PHYMOD_SYMBOL_FIELD_ENCODE(166, 12, 12), 428 /* AMS_TX_DRIVERMODE:13:14 */ 429 PHYMOD_SYMBOL_FIELD_ENCODE(157, 14, 13), 430 /* AMS_TX_ELEC_IDLE_AUX:15:15 */ 431 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(158, 15, 15) 432 }; 433 static uint32_t BCMI_FALCON_XGXS_AMS_TX_CTL3r_fields[] = 434 { 435 /* AMS_TX_SPARE_63_48:0:15 */ 436 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(172, 15, 0) 437 }; 438 static uint32_t BCMI_FALCON_XGXS_AMS_TX_STSr_fields[] = 439 { 440 /* AMS_TX_STS:0:15 */ 441 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(173, 15, 0) 442 }; 443 static uint32_t BCMI_FALCON_XGXS_CKRST_CLK_N_RST_DBG_CTLr_fields[] = 444 { 445 /* LN_RX_S_CLKGATE_FRC_ON:0:0 */ 446 PHYMOD_SYMBOL_FIELD_ENCODE(348, 0, 0), 447 /* LN_RX_S_COMCLK_SEL:1:1 */ 448 PHYMOD_SYMBOL_FIELD_ENCODE(350, 1, 1), 449 /* LN_RX_S_COMCLK_FRC_ON:2:2 */ 450 PHYMOD_SYMBOL_FIELD_ENCODE(349, 2, 2), 451 /* PMD_RX_CLK_VLD_FRC:3:3 */ 452 PHYMOD_SYMBOL_FIELD_ENCODE(494, 3, 3), 453 /* PMD_RX_CLK_VLD_FRC_VAL:4:4 */ 454 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(495, 4, 4) 455 }; 456 static uint32_t BCMI_FALCON_XGXS_CKRST_LN_AFE_RST_PWRDWN_CTLr_fields[] = 457 { 458 /* AFE_RX_PWRDN_FRC:0:0 */ 459 PHYMOD_SYMBOL_FIELD_ENCODE(1, 0, 0), 460 /* AFE_RX_PWRDN_FRC_VAL:1:1 */ 461 PHYMOD_SYMBOL_FIELD_ENCODE(2, 1, 1), 462 /* AFE_RX_RESET_FRC:2:2 */ 463 PHYMOD_SYMBOL_FIELD_ENCODE(5, 2, 2), 464 /* AFE_RX_RESET_FRC_VAL:3:3 */ 465 PHYMOD_SYMBOL_FIELD_ENCODE(6, 3, 3), 466 /* AFE_TX_PWRDN_FRC:4:4 */ 467 PHYMOD_SYMBOL_FIELD_ENCODE(13, 4, 4), 468 /* AFE_TX_PWRDN_FRC_VAL:5:5 */ 469 PHYMOD_SYMBOL_FIELD_ENCODE(14, 5, 5), 470 /* AFE_TX_RESET_FRC:6:6 */ 471 PHYMOD_SYMBOL_FIELD_ENCODE(15, 6, 6), 472 /* AFE_TX_RESET_FRC_VAL:7:7 */ 473 PHYMOD_SYMBOL_FIELD_ENCODE(16, 7, 7), 474 /* AFE_RX_RCLK20_PWRDN_FRC:8:8 */ 475 PHYMOD_SYMBOL_FIELD_ENCODE(3, 8, 8), 476 /* AFE_RX_RCLK20_PWRDN_FRC_VAL:9:9 */ 477 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(4, 9, 9) 478 }; 479 static uint32_t BCMI_FALCON_XGXS_CKRST_LN_CLK_RST_N_PWRDWN_CTLr_fields[] = 480 { 481 /* LN_DP_S_RSTB:1:1 */ 482 PHYMOD_SYMBOL_FIELD_ENCODE(346, 1, 1), 483 /* LN_RX_S_PWRDN:2:2 */ 484 PHYMOD_SYMBOL_FIELD_ENCODE(351, 2, 2), 485 /* LN_TX_S_PWRDN:3:3 */ 486 PHYMOD_SYMBOL_FIELD_ENCODE(355, 3, 3), 487 /* AFE_SIGDET_PWRDN:4:4 */ 488 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(7, 4, 4) 489 }; 490 static uint32_t BCMI_FALCON_XGXS_CKRST_LN_DBG_RST_CTLr_fields[] = 491 { 492 /* LN_RX_S_RSTB:0:0 */ 493 PHYMOD_SYMBOL_FIELD_ENCODE(352, 0, 0), 494 /* LN_RX_DP_S_RSTB:1:1 */ 495 PHYMOD_SYMBOL_FIELD_ENCODE(347, 1, 1), 496 /* SIGDET_DP_RSTB_EN:2:2 */ 497 PHYMOD_SYMBOL_FIELD_ENCODE(694, 2, 2), 498 /* LN_TX_S_RSTB:8:8 */ 499 PHYMOD_SYMBOL_FIELD_ENCODE(356, 8, 8), 500 /* LN_TX_DP_S_RSTB:9:9 */ 501 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(354, 9, 9) 502 }; 503 static uint32_t BCMI_FALCON_XGXS_CKRST_LN_DP_RST_ST_STSr_fields[] = 504 { 505 /* LANE_DP_RESET_STATE:0:2 */ 506 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(341, 2, 0) 507 }; 508 static uint32_t BCMI_FALCON_XGXS_CKRST_LN_MASKr_fields[] = 509 { 510 /* LANE_MULTICAST_MASK_CONTROL:0:0 */ 511 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(342, 0, 0) 512 }; 513 static uint32_t BCMI_FALCON_XGXS_CKRST_LN_RST_N_PWRDN_PIN_KILL_CTLr_fields[] = 514 { 515 /* PMD_LN_H_RSTB_PKILL:0:0 */ 516 PHYMOD_SYMBOL_FIELD_ENCODE(490, 0, 0), 517 /* PMD_LN_DP_H_RSTB_PKILL:1:1 */ 518 PHYMOD_SYMBOL_FIELD_ENCODE(489, 1, 1), 519 /* PMD_LN_RX_H_PWRDN_PKILL:2:2 */ 520 PHYMOD_SYMBOL_FIELD_ENCODE(491, 2, 2), 521 /* PMD_LN_TX_H_PWRDN_PKILL:3:3 */ 522 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(492, 3, 3) 523 }; 524 static uint32_t BCMI_FALCON_XGXS_CKRST_LN_RST_OCC_CTLr_fields[] = 525 { 526 /* LANE_REG_RESET_OCCURRED:0:0 */ 527 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(343, 0, 0) 528 }; 529 static uint32_t BCMI_FALCON_XGXS_CKRST_LN_S_RSTB_CTLr_fields[] = 530 { 531 /* LN_S_RSTB:0:0 */ 532 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(353, 0, 0) 533 }; 534 static uint32_t BCMI_FALCON_XGXS_CKRST_OSR_MODE_CTLr_fields[] = 535 { 536 /* OSR_MODE_FRC_VAL:0:3 */ 537 PHYMOD_SYMBOL_FIELD_ENCODE(444, 3, 0), 538 /* OSR_MODE_FRC:15:15 */ 539 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(443, 15, 15) 540 }; 541 static uint32_t BCMI_FALCON_XGXS_CKRST_OSR_MODE_PIN_STSr_fields[] = 542 { 543 /* OSR_MODE_PIN:0:3 */ 544 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(445, 3, 0) 545 }; 546 static uint32_t BCMI_FALCON_XGXS_CKRST_OSR_MODE_STSr_fields[] = 547 { 548 /* OSR_MODE:0:3 */ 549 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(442, 3, 0) 550 }; 551 static uint32_t BCMI_FALCON_XGXS_CKRST_PMD_LN_MODE_STSr_fields[] = 552 { 553 /* PMD_LANE_MODE:0:15 */ 554 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(488, 15, 0) 555 }; 556 static uint32_t BCMI_FALCON_XGXS_CKRST_UC_ACK_LN_CTLr_fields[] = 557 { 558 /* UC_ACK_LANE_CFG_DONE:0:0 */ 559 PHYMOD_SYMBOL_FIELD_ENCODE(818, 0, 0), 560 /* UC_ACK_LANE_DP_RESET:1:1 */ 561 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(819, 1, 1) 562 }; 563 static uint32_t BCMI_FALCON_XGXS_CL93N72_IR_BASE_R_LP_COEFF_UPDr_fields[] = 564 { 565 /* CL93N72_IEEE_LP_COEFF_UPDATE:0:15 */ 566 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(232, 15, 0) 567 }; 568 static uint32_t BCMI_FALCON_XGXS_CL93N72_IR_BASE_R_LP_STS_REPr_fields[] = 569 { 570 /* CL93N72_IEEE_LP_STATUS_REPORT:0:15 */ 571 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(233, 15, 0) 572 }; 573 static uint32_t BCMI_FALCON_XGXS_CL93N72_IT_BASE_R_LD_COEFF_UPDr_fields[] = 574 { 575 /* CL93N72_IEEE_LD_COEFF_UPDATE:0:15 */ 576 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(230, 15, 0) 577 }; 578 static uint32_t BCMI_FALCON_XGXS_CL93N72_IT_BASE_R_LD_STS_REPr_fields[] = 579 { 580 /* CL93N72_IEEE_LD_STATUS_REPORT:0:15 */ 581 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(231, 15, 0) 582 }; 583 static uint32_t BCMI_FALCON_XGXS_CL93N72_IT_BASE_R_PMD_CTLr_fields[] = 584 { 585 /* CL93N72_IEEE_RESTART_TRAINING:0:0 */ 586 PHYMOD_SYMBOL_FIELD_ENCODE(235, 0, 0), 587 /* CL93N72_IEEE_TRAINING_ENABLE:1:1 */ 588 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(236, 1, 1) 589 }; 590 static uint32_t BCMI_FALCON_XGXS_CL93N72_IT_BASE_R_PMD_STSr_fields[] = 591 { 592 /* CL93N72_IEEE_RECEIVER_STATUS:0:0 */ 593 PHYMOD_SYMBOL_FIELD_ENCODE(234, 0, 0), 594 /* CL93N72_IEEE_FRAME_LOCK:1:1 */ 595 PHYMOD_SYMBOL_FIELD_ENCODE(229, 1, 1), 596 /* CL93N72_IEEE_TRAINING_STATUS:2:2 */ 597 PHYMOD_SYMBOL_FIELD_ENCODE(238, 2, 2), 598 /* CL93N72_IEEE_TRAINING_FAILURE:3:3 */ 599 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(237, 3, 3) 600 }; 601 static uint32_t BCMI_FALCON_XGXS_CL93N72_UR_CTL0r_fields[] = 602 { 603 /* CL93N72_RX_TRAINING_EN:0:0 */ 604 PHYMOD_SYMBOL_FIELD_ENCODE(251, 0, 0), 605 /* CL93N72_TR_COARSE_LOCK:1:1 */ 606 PHYMOD_SYMBOL_FIELD_ENCODE(258, 1, 1), 607 /* CL93N72_RX_SIGNAL_OK:2:2 */ 608 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(250, 2, 2) 609 }; 610 static uint32_t BCMI_FALCON_XGXS_CL93N72_UR_CTL1r_fields[] = 611 { 612 /* CL93N72_GOOD_MARKER_CNT:0:1 */ 613 PHYMOD_SYMBOL_FIELD_ENCODE(228, 1, 0), 614 /* CL93N72_BAD_MARKER_CNT:4:6 */ 615 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(219, 6, 4) 616 }; 617 static uint32_t BCMI_FALCON_XGXS_CL93N72_UR_CTL2r_fields[] = 618 { 619 /* CL93N72_CTRL_FRAME_DLY:0:3 */ 620 PHYMOD_SYMBOL_FIELD_ENCODE(223, 3, 0), 621 /* CL93N72_DME_CELL_BOUNDARY_CHK:4:4 */ 622 PHYMOD_SYMBOL_FIELD_ENCODE(225, 4, 4), 623 /* CL93N72_STRICT_DME_CHK:5:5 */ 624 PHYMOD_SYMBOL_FIELD_ENCODE(252, 5, 5), 625 /* CL93N72_STRICT_MARKER_CHK:6:6 */ 626 PHYMOD_SYMBOL_FIELD_ENCODE(253, 6, 6), 627 /* CL93N72_PPM_OFFSET_EN:7:7 */ 628 PHYMOD_SYMBOL_FIELD_ENCODE(247, 7, 7), 629 /* CL93N72_RX_DP_LN_CLK_EN:8:8 */ 630 PHYMOD_SYMBOL_FIELD_ENCODE(249, 8, 8), 631 /* CL93N72_FRAME_CONSISTENCY_CHK_EN:9:9 */ 632 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(226, 9, 9) 633 }; 634 static uint32_t BCMI_FALCON_XGXS_CL93N72_UR_STS0r_fields[] = 635 { 636 /* CL93N72_FRAME_LOCK:0:0 */ 637 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(227, 0, 0) 638 }; 639 static uint32_t BCMI_FALCON_XGXS_CL93N72_UR_UC_INTR_CTL0r_fields[] = 640 { 641 /* CL93N72_MICRO_UPDATE_CHG_INT_EN:0:0 */ 642 PHYMOD_SYMBOL_FIELD_ENCODE(245, 0, 0), 643 /* CL93N72_MICRO_STATUS_CHG_INT_EN:1:1 */ 644 PHYMOD_SYMBOL_FIELD_ENCODE(243, 1, 1), 645 /* CL93N72_MICRO_FRAME_LOCK_INT_EN:2:2 */ 646 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(241, 2, 2) 647 }; 648 static uint32_t BCMI_FALCON_XGXS_CL93N72_UR_UC_STS0r_fields[] = 649 { 650 /* CL93N72_MICRO_UPDATE_CHG_LSTATUS:0:0 */ 651 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(246, 0, 0) 652 }; 653 static uint32_t BCMI_FALCON_XGXS_CL93N72_UR_UC_STS1r_fields[] = 654 { 655 /* CL93N72_MICRO_STATUS_CHG_LSTATUS:0:0 */ 656 PHYMOD_SYMBOL_FIELD_ENCODE(244, 0, 0), 657 /* CL93N72_MICRO_FRAME_LOCK_LSTATUS:1:1 */ 658 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(242, 1, 1) 659 }; 660 static uint32_t BCMI_FALCON_XGXS_CL93N72_UT_CTL0r_fields[] = 661 { 662 /* CL93N72_SW_RX_TRAINED:0:0 */ 663 PHYMOD_SYMBOL_FIELD_ENCODE(256, 0, 0), 664 /* CL93N72_SW_FRAME_LOCK:1:1 */ 665 PHYMOD_SYMBOL_FIELD_ENCODE(254, 1, 1), 666 /* CL93N72_SW_REMOTE_RX_READY:2:2 */ 667 PHYMOD_SYMBOL_FIELD_ENCODE(255, 2, 2), 668 /* CL93N72_PRBS_SEL:4:6 */ 669 PHYMOD_SYMBOL_FIELD_ENCODE(248, 6, 4), 670 /* CL93N72_CL93PRBSSEED_ORDER:7:7 */ 671 PHYMOD_SYMBOL_FIELD_ENCODE(221, 7, 7), 672 /* CL93N72_CL93PRBSSEED_RANDOM:8:8 */ 673 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(222, 8, 8) 674 }; 675 static uint32_t BCMI_FALCON_XGXS_CL93N72_UT_CTL1r_fields[] = 676 { 677 /* CL93N72_BRK_RING_OSC:0:0 */ 678 PHYMOD_SYMBOL_FIELD_ENCODE(220, 0, 0), 679 /* CL93N72_DIS_MAX_WAIT_TIMER:1:1 */ 680 PHYMOD_SYMBOL_FIELD_ENCODE(224, 1, 1), 681 /* CL93N72_TX_DP_LN_CLK_EN:2:2 */ 682 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(262, 2, 2) 683 }; 684 static uint32_t BCMI_FALCON_XGXS_CL93N72_UT_CTL2r_fields[] = 685 { 686 /* CL93N72_TXFIR_PRE:0:4 */ 687 PHYMOD_SYMBOL_FIELD_ENCODE(261, 4, 0), 688 /* CL93N72_TXFIR_POST:8:13 */ 689 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(260, 13, 8) 690 }; 691 static uint32_t BCMI_FALCON_XGXS_CL93N72_UT_CTL3r_fields[] = 692 { 693 /* CL93N72_TXFIR_MAIN:0:6 */ 694 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(259, 6, 0) 695 }; 696 static uint32_t BCMI_FALCON_XGXS_CL93N72_UT_LD_XMT_STS_PAGEr_fields[] = 697 { 698 /* CL93N72_LD_XMT_STATUS_PAGE:0:15 */ 699 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(239, 15, 0) 700 }; 701 static uint32_t BCMI_FALCON_XGXS_CL93N72_UT_STS0r_fields[] = 702 { 703 /* CL93N72_LOCAL_RX_READY:0:0 */ 704 PHYMOD_SYMBOL_FIELD_ENCODE(240, 0, 0), 705 /* CL93N72_TRAINING_FSM_SIGNAL_DETECT:1:1 */ 706 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(257, 1, 1) 707 }; 708 static uint32_t BCMI_FALCON_XGXS_CL93N72_UT_XMT_UPD_PAGEr_fields[] = 709 { 710 /* CL93N72_XMT_UPDATE_PAGE:0:15 */ 711 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(263, 15, 0) 712 }; 713 static uint32_t BCMI_FALCON_XGXS_DIG_CORE_DP_RST_ST_STSr_fields[] = 714 { 715 /* CORE_DP_RESET_STATE:0:2 */ 716 PHYMOD_SYMBOL_FIELD_ENCODE(264, 2, 0), 717 /* LANE_RESET_RELEASED_INDEX:8:12 */ 718 PHYMOD_SYMBOL_FIELD_ENCODE(345, 12, 8), 719 /* LANE_RESET_RELEASED:14:14 */ 720 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(344, 14, 14) 721 }; 722 static uint32_t BCMI_FALCON_XGXS_DIG_CORE_RST_OCC_CTLr_fields[] = 723 { 724 /* CORE_REG_RESET_OCCURRED:0:0 */ 725 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(267, 0, 0) 726 }; 727 static uint32_t BCMI_FALCON_XGXS_DIG_LN_ADDR_2_3r_fields[] = 728 { 729 /* LANE_ADDR_2:0:4 */ 730 PHYMOD_SYMBOL_FIELD_ENCODE(339, 4, 0), 731 /* LANE_ADDR_3:8:12 */ 732 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(340, 12, 8) 733 }; 734 static uint32_t BCMI_FALCON_XGXS_DIG_LN_MASKr_fields[] = 735 { 736 /* CORE_MULTICAST_MASK_CONTROL:0:3 */ 737 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(266, 3, 0) 738 }; 739 static uint32_t BCMI_FALCON_XGXS_DIG_PMD_CORE_MODE_STSr_fields[] = 740 { 741 /* PMD_CORE_MODE:0:15 */ 742 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(487, 15, 0) 743 }; 744 static uint32_t BCMI_FALCON_XGXS_DIG_REVID0r_fields[] = 745 { 746 /* REVID_MODEL:0:5 */ 747 PHYMOD_SYMBOL_FIELD_ENCODE(545, 5, 0), 748 /* REVID_PROCESS:6:8 */ 749 PHYMOD_SYMBOL_FIELD_ENCODE(548, 8, 6), 750 /* REVID_BONDING:9:10 */ 751 PHYMOD_SYMBOL_FIELD_ENCODE(539, 10, 9), 752 /* REVID_REV_NUMBER:11:13 */ 753 PHYMOD_SYMBOL_FIELD_ENCODE(550, 13, 11), 754 /* REVID_REV_LETTER:14:15 */ 755 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(549, 15, 14) 756 }; 757 static uint32_t BCMI_FALCON_XGXS_DIG_REVID1r_fields[] = 758 { 759 /* REVID_EEE:0:0 */ 760 PHYMOD_SYMBOL_FIELD_ENCODE(541, 0, 0), 761 /* REVID_LLP:1:1 */ 762 PHYMOD_SYMBOL_FIELD_ENCODE(542, 1, 1), 763 /* REVID_PIR:2:2 */ 764 PHYMOD_SYMBOL_FIELD_ENCODE(547, 2, 2), 765 /* REVID_CL72:3:3 */ 766 PHYMOD_SYMBOL_FIELD_ENCODE(540, 3, 3), 767 /* REVID_MICRO:4:4 */ 768 PHYMOD_SYMBOL_FIELD_ENCODE(544, 4, 4), 769 /* REVID_MDIO:5:5 */ 770 PHYMOD_SYMBOL_FIELD_ENCODE(543, 5, 5), 771 /* REVID_MULTIPLICITY:12:15 */ 772 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(546, 15, 12) 773 }; 774 static uint32_t BCMI_FALCON_XGXS_DIG_REVID2r_fields[] = 775 { 776 /* REVID2:0:3 */ 777 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(538, 3, 0) 778 }; 779 static uint32_t BCMI_FALCON_XGXS_DIG_RST_CTL_CORE_DPr_fields[] = 780 { 781 /* PMD_CORE_DP_H_RSTB_PKILL:1:1 */ 782 PHYMOD_SYMBOL_FIELD_ENCODE(486, 1, 1), 783 /* SUP_RST_SEQ_FRC_VAL:3:3 */ 784 PHYMOD_SYMBOL_FIELD_ENCODE(706, 3, 3), 785 /* SUP_RST_SEQ_FRC:4:4 */ 786 PHYMOD_SYMBOL_FIELD_ENCODE(705, 4, 4), 787 /* PMD_MDIO_TRANS_PKILL:5:5 */ 788 PHYMOD_SYMBOL_FIELD_ENCODE(493, 5, 5), 789 /* PMD_TX_CLK_VLD_FRC:7:7 */ 790 PHYMOD_SYMBOL_FIELD_ENCODE(498, 7, 7), 791 /* PMD_TX_CLK_VLD_FRC_VAL:8:8 */ 792 PHYMOD_SYMBOL_FIELD_ENCODE(499, 8, 8), 793 /* TX_S_COMCLK_SEL:9:9 */ 794 PHYMOD_SYMBOL_FIELD_ENCODE(812, 9, 9), 795 /* TX_S_COMCLK_FRC_ON:10:10 */ 796 PHYMOD_SYMBOL_FIELD_ENCODE(811, 10, 10), 797 /* TX_S_CLKGATE_FRC_ON:11:11 */ 798 PHYMOD_SYMBOL_FIELD_ENCODE(810, 11, 11), 799 /* AFE_S_PLL_RESET_FRC_VAL:12:12 */ 800 PHYMOD_SYMBOL_FIELD_ENCODE(12, 12, 12), 801 /* AFE_S_PLL_RESET_FRC:13:13 */ 802 PHYMOD_SYMBOL_FIELD_ENCODE(11, 13, 13), 803 /* TX_PI_LOOP_FILTER_STABLE:14:14 */ 804 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(794, 14, 14) 805 }; 806 static uint32_t BCMI_FALCON_XGXS_DIG_RST_CTL_PMDr_fields[] = 807 { 808 /* CORE_S_RSTB:0:0 */ 809 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(268, 0, 0) 810 }; 811 static uint32_t BCMI_FALCON_XGXS_DIG_RST_SEQ_TMR_CTLr_fields[] = 812 { 813 /* RST_SEQ_TIMER:0:2 */ 814 PHYMOD_SYMBOL_FIELD_ENCODE(557, 2, 0), 815 /* PWRDN_SEQ_TIMER:8:10 */ 816 PHYMOD_SYMBOL_FIELD_ENCODE(527, 10, 8), 817 /* RST_SEQ_DIS_FLT_MODE:14:15 */ 818 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(556, 15, 14) 819 }; 820 static uint32_t BCMI_FALCON_XGXS_DIG_TOP_USER_CTL0r_fields[] = 821 { 822 /* HEARTBEAT_COUNT_1US:0:9 */ 823 PHYMOD_SYMBOL_FIELD_ENCODE(330, 9, 0), 824 /* CORE_DP_S_RSTB:13:13 */ 825 PHYMOD_SYMBOL_FIELD_ENCODE(265, 13, 13), 826 /* AFE_S_PLL_PWRDN:14:14 */ 827 PHYMOD_SYMBOL_FIELD_ENCODE(10, 14, 14), 828 /* UC_ACTIVE:15:15 */ 829 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(820, 15, 15) 830 }; 831 static uint32_t BCMI_FALCON_XGXS_DIG_TX_LN_MAP_0_1_2r_fields[] = 832 { 833 /* TX_LANE_MAP_0:0:4 */ 834 PHYMOD_SYMBOL_FIELD_ENCODE(773, 4, 0), 835 /* TX_LANE_MAP_1:5:9 */ 836 PHYMOD_SYMBOL_FIELD_ENCODE(774, 9, 5), 837 /* TX_LANE_MAP_2:10:14 */ 838 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(775, 14, 10) 839 }; 840 static uint32_t BCMI_FALCON_XGXS_DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r_fields[] = 841 { 842 /* TX_LANE_MAP_3:0:4 */ 843 PHYMOD_SYMBOL_FIELD_ENCODE(776, 4, 0), 844 /* LANE_ADDR_0:5:9 */ 845 PHYMOD_SYMBOL_FIELD_ENCODE(337, 9, 5), 846 /* LANE_ADDR_1:10:14 */ 847 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(338, 14, 10) 848 }; 849 static uint32_t BCMI_FALCON_XGXS_DIG_UC_ACK_CORE_CTLr_fields[] = 850 { 851 /* UC_ACK_CORE_CFG_DONE:0:0 */ 852 PHYMOD_SYMBOL_FIELD_ENCODE(813, 0, 0), 853 /* UC_ACK_CORE_DP_RESET:1:1 */ 854 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(814, 1, 1) 855 }; 856 static uint32_t BCMI_FALCON_XGXS_DSC_CDR_1G_STSr_fields[] = 857 { 858 /* CDR_1G_PHASE_POINTER:0:7 */ 859 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(194, 7, 0) 860 }; 861 static uint32_t BCMI_FALCON_XGXS_DSC_CDR_CTL0r_fields[] = 862 { 863 /* OS_ALL_EDGES:0:0 */ 864 PHYMOD_SYMBOL_FIELD_ENCODE(446, 0, 0), 865 /* BR_PD_EN:1:1 */ 866 PHYMOD_SYMBOL_FIELD_ENCODE(177, 1, 1), 867 /* OS_PATTERN_ENHANCED:2:2 */ 868 PHYMOD_SYMBOL_FIELD_ENCODE(447, 2, 2), 869 /* CDR_FREQ_EN:3:3 */ 870 PHYMOD_SYMBOL_FIELD_ENCODE(203, 3, 3), 871 /* CDR_INTEG_REG_CLR:5:5 */ 872 PHYMOD_SYMBOL_FIELD_ENCODE(209, 5, 5), 873 /* CDR_PHASE_ERR_FRZ:6:6 */ 874 PHYMOD_SYMBOL_FIELD_ENCODE(214, 6, 6), 875 /* CDR_INTEG_SAT_SEL:7:7 */ 876 PHYMOD_SYMBOL_FIELD_ENCODE(210, 7, 7), 877 /* CDR_FREQ_OVERRIDE_EN:8:8 */ 878 PHYMOD_SYMBOL_FIELD_ENCODE(204, 8, 8), 879 /* CDR_ZERO_POLARITY:9:9 */ 880 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(217, 9, 9) 881 }; 882 static uint32_t BCMI_FALCON_XGXS_DSC_CDR_CTL1r_fields[] = 883 { 884 /* CDR_FREQ_OVERRIDE_VAL:5:15 */ 885 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(205, 15, 5) 886 }; 887 static uint32_t BCMI_FALCON_XGXS_DSC_CDR_CTL2r_fields[] = 888 { 889 /* CDR_LM_THR_SEL:0:3 */ 890 PHYMOD_SYMBOL_FIELD_ENCODE(212, 3, 0), 891 /* CDR_1G_SWAP_PZ:4:4 */ 892 PHYMOD_SYMBOL_FIELD_ENCODE(195, 4, 4), 893 /* CDR_1G_FORCE_EN:5:5 */ 894 PHYMOD_SYMBOL_FIELD_ENCODE(191, 5, 5), 895 /* TX_PI_LOOP_TIMING_SRC_SEL:6:6 */ 896 PHYMOD_SYMBOL_FIELD_ENCODE(795, 6, 6), 897 /* PHS_SUM_IGNORE_DSC_LOCK:7:7 */ 898 PHYMOD_SYMBOL_FIELD_ENCODE(468, 7, 7), 899 /* CDR_1G_MANUAL_MODE:8:8 */ 900 PHYMOD_SYMBOL_FIELD_ENCODE(192, 8, 8), 901 /* CDR_1G_MANUAL_STROBE:9:9 */ 902 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(193, 9, 9) 903 }; 904 static uint32_t BCMI_FALCON_XGXS_DSC_CDR_STS_INTEGr_fields[] = 905 { 906 /* CDR_INTEG_REG:0:15 */ 907 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(208, 15, 0) 908 }; 909 static uint32_t BCMI_FALCON_XGXS_DSC_CDR_STS_MISCr_fields[] = 910 { 911 /* CDR_LM_OUTOFLOCK:0:0 */ 912 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(211, 0, 0) 913 }; 914 static uint32_t BCMI_FALCON_XGXS_DSC_CDR_STS_PHASE_ERRr_fields[] = 915 { 916 /* CDR_PHASE_ERROR:0:5 */ 917 PHYMOD_SYMBOL_FIELD_ENCODE(213, 5, 0), 918 /* CDR_VCO_REG:12:15 */ 919 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(216, 15, 12) 920 }; 921 static uint32_t BCMI_FALCON_XGXS_DSC_DATA_SLCR_THR_CTLr_fields[] = 922 { 923 /* THRESH_TIMER_T1:0:1 */ 924 PHYMOD_SYMBOL_FIELD_ENCODE(714, 1, 0), 925 /* THRESH_STEP_SIZE:4:5 */ 926 PHYMOD_SYMBOL_FIELD_ENCODE(713, 5, 4), 927 /* DATA_THRESH_SEL_VAL:8:14 */ 928 PHYMOD_SYMBOL_FIELD_ENCODE(269, 14, 8), 929 /* DATA_THRESH_WRITE:15:15 */ 930 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(270, 15, 15) 931 }; 932 static uint32_t BCMI_FALCON_XGXS_DSC_DC_OFFS_CTLr_fields[] = 933 { 934 /* DC_OFFS_EN:0:0 */ 935 PHYMOD_SYMBOL_FIELD_ENCODE(279, 0, 0), 936 /* DC_OFFS_HYS_EN:2:2 */ 937 PHYMOD_SYMBOL_FIELD_ENCODE(282, 2, 2), 938 /* DC_OFFS_HYS_MAG:3:3 */ 939 PHYMOD_SYMBOL_FIELD_ENCODE(283, 3, 3), 940 /* DC_OFFS_GRADIENT_INVERT:4:4 */ 941 PHYMOD_SYMBOL_FIELD_ENCODE(281, 4, 4), 942 /* DC_OFFS_GAIN:5:6 */ 943 PHYMOD_SYMBOL_FIELD_ENCODE(280, 6, 5), 944 /* DC_OFFS_ACC_CLR:7:7 */ 945 PHYMOD_SYMBOL_FIELD_ENCODE(278, 7, 7), 946 /* DC_OFFS_WRITE_VAL:8:14 */ 947 PHYMOD_SYMBOL_FIELD_ENCODE(286, 14, 8), 948 /* DC_OFFS_WRITE_FRC_EN:15:15 */ 949 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(285, 15, 15) 950 }; 951 static uint32_t BCMI_FALCON_XGXS_DSC_DC_OFFS_STSr_fields[] = 952 { 953 /* DC_OFFSET_BIN:0:6 */ 954 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(277, 6, 0) 955 }; 956 static uint32_t BCMI_FALCON_XGXS_DSC_LOAD_PRESETSr_fields[] = 957 { 958 /* PRESET_DSC_AFE_BANK:0:0 */ 959 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(522, 0, 0) 960 }; 961 static uint32_t BCMI_FALCON_XGXS_DSC_PRESETr_fields[] = 962 { 963 /* PRESET_DSC_C_BANK:0:0 */ 964 PHYMOD_SYMBOL_FIELD_ENCODE(524, 0, 0), 965 /* PRESET_DSC_D_BANK:1:1 */ 966 PHYMOD_SYMBOL_FIELD_ENCODE(525, 1, 1), 967 /* PRESET_DSC_A_BANK:2:2 */ 968 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(523, 2, 2) 969 }; 970 static uint32_t BCMI_FALCON_XGXS_DSC_RXAB_SLCR_OFFS_ADJ_LMSr_fields[] = 971 { 972 /* RXB_SLICER_OFFSET_ADJ_LMS:0:5 */ 973 PHYMOD_SYMBOL_FIELD_ENCODE(607, 5, 0), 974 /* RXA_SLICER_OFFSET_ADJ_LMS:8:13 */ 975 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(581, 13, 8) 976 }; 977 static uint32_t BCMI_FALCON_XGXS_DSC_RXA_SLCR_OFFS_ADJ_DN_DPr_fields[] = 978 { 979 /* RXA_SLICER_OFFSET_ADJ_DP:0:5 */ 980 PHYMOD_SYMBOL_FIELD_ENCODE(580, 5, 0), 981 /* RXA_SLICER_OFFSET_ADJ_DN:8:13 */ 982 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(579, 13, 8) 983 }; 984 static uint32_t BCMI_FALCON_XGXS_DSC_RXA_SLCR_OFFS_ADJ_ZN_ZPr_fields[] = 985 { 986 /* RXA_SLICER_OFFSET_ADJ_ZP:0:5 */ 987 PHYMOD_SYMBOL_FIELD_ENCODE(583, 5, 0), 988 /* RXA_SLICER_OFFSET_ADJ_ZN:8:13 */ 989 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(582, 13, 8) 990 }; 991 static uint32_t BCMI_FALCON_XGXS_DSC_RXB_SLCR_OFFS_ADJ_DN_DPr_fields[] = 992 { 993 /* RXB_SLICER_OFFSET_ADJ_DP:0:5 */ 994 PHYMOD_SYMBOL_FIELD_ENCODE(606, 5, 0), 995 /* RXB_SLICER_OFFSET_ADJ_DN:8:13 */ 996 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(605, 13, 8) 997 }; 998 static uint32_t BCMI_FALCON_XGXS_DSC_RXB_SLCR_OFFS_ADJ_ZN_ZPr_fields[] = 999 { 1000 /* RXB_SLICER_OFFSET_ADJ_ZP:0:5 */ 1001 PHYMOD_SYMBOL_FIELD_ENCODE(609, 5, 0), 1002 /* RXB_SLICER_OFFSET_ADJ_ZN:8:13 */ 1003 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(608, 13, 8) 1004 }; 1005 static uint32_t BCMI_FALCON_XGXS_DSC_RXCD_SLCR_OFFS_ADJ_LMSr_fields[] = 1006 { 1007 /* RXD_SLICER_OFFSET_ADJ_LMS:0:5 */ 1008 PHYMOD_SYMBOL_FIELD_ENCODE(659, 5, 0), 1009 /* RXC_SLICER_OFFSET_ADJ_LMS:8:13 */ 1010 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(633, 13, 8) 1011 }; 1012 static uint32_t BCMI_FALCON_XGXS_DSC_RXC_SLCR_OFFS_ADJ_DN_DPr_fields[] = 1013 { 1014 /* RXC_SLICER_OFFSET_ADJ_DP:0:5 */ 1015 PHYMOD_SYMBOL_FIELD_ENCODE(632, 5, 0), 1016 /* RXC_SLICER_OFFSET_ADJ_DN:8:13 */ 1017 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(631, 13, 8) 1018 }; 1019 static uint32_t BCMI_FALCON_XGXS_DSC_RXC_SLCR_OFFS_ADJ_ZN_ZPr_fields[] = 1020 { 1021 /* RXC_SLICER_OFFSET_ADJ_ZP:0:5 */ 1022 PHYMOD_SYMBOL_FIELD_ENCODE(635, 5, 0), 1023 /* RXC_SLICER_OFFSET_ADJ_ZN:8:13 */ 1024 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(634, 13, 8) 1025 }; 1026 static uint32_t BCMI_FALCON_XGXS_DSC_RXD_SLCR_OFFS_ADJ_DN_DPr_fields[] = 1027 { 1028 /* RXD_SLICER_OFFSET_ADJ_DP:0:5 */ 1029 PHYMOD_SYMBOL_FIELD_ENCODE(658, 5, 0), 1030 /* RXD_SLICER_OFFSET_ADJ_DN:8:13 */ 1031 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(657, 13, 8) 1032 }; 1033 static uint32_t BCMI_FALCON_XGXS_DSC_RXD_SLCR_OFFS_ADJ_ZN_ZPr_fields[] = 1034 { 1035 /* RXD_SLICER_OFFSET_ADJ_ZP:0:5 */ 1036 PHYMOD_SYMBOL_FIELD_ENCODE(661, 5, 0), 1037 /* RXD_SLICER_OFFSET_ADJ_ZN:8:13 */ 1038 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(660, 13, 8) 1039 }; 1040 static uint32_t BCMI_FALCON_XGXS_DSC_RX_DATA_15_TO0r_fields[] = 1041 { 1042 /* RX_DATA_15_TO_0:0:15 */ 1043 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(662, 15, 0) 1044 }; 1045 static uint32_t BCMI_FALCON_XGXS_DSC_RX_DATA_35_TO_20r_fields[] = 1046 { 1047 /* RX_DATA_35_TO_20:0:15 */ 1048 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(663, 15, 0) 1049 }; 1050 static uint32_t BCMI_FALCON_XGXS_DSC_RX_DFE_TAP10_ABCDr_fields[] = 1051 { 1052 /* RXD_DFE_TAP10:0:3 */ 1053 PHYMOD_SYMBOL_FIELD_ENCODE(636, 3, 0), 1054 /* RXC_DFE_TAP10:4:7 */ 1055 PHYMOD_SYMBOL_FIELD_ENCODE(610, 7, 4), 1056 /* RXB_DFE_TAP10:8:11 */ 1057 PHYMOD_SYMBOL_FIELD_ENCODE(584, 11, 8), 1058 /* RXA_DFE_TAP10:12:15 */ 1059 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(558, 15, 12) 1060 }; 1061 static uint32_t BCMI_FALCON_XGXS_DSC_RX_DFE_TAP11_12_MUX_ABCDr_fields[] = 1062 { 1063 /* RXD_DFE_TAP12_MUX:0:1 */ 1064 PHYMOD_SYMBOL_FIELD_ENCODE(641, 1, 0), 1065 /* RXD_DFE_TAP11_MUX:2:3 */ 1066 PHYMOD_SYMBOL_FIELD_ENCODE(639, 3, 2), 1067 /* RXC_DFE_TAP12_MUX:4:5 */ 1068 PHYMOD_SYMBOL_FIELD_ENCODE(615, 5, 4), 1069 /* RXC_DFE_TAP11_MUX:6:7 */ 1070 PHYMOD_SYMBOL_FIELD_ENCODE(613, 7, 6), 1071 /* RXB_DFE_TAP12_MUX:8:9 */ 1072 PHYMOD_SYMBOL_FIELD_ENCODE(589, 9, 8), 1073 /* RXB_DFE_TAP11_MUX:10:11 */ 1074 PHYMOD_SYMBOL_FIELD_ENCODE(587, 11, 10), 1075 /* RXA_DFE_TAP12_MUX:12:13 */ 1076 PHYMOD_SYMBOL_FIELD_ENCODE(563, 13, 12), 1077 /* RXA_DFE_TAP11_MUX:14:15 */ 1078 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(561, 15, 14) 1079 }; 1080 static uint32_t BCMI_FALCON_XGXS_DSC_RX_DFE_TAP11_ABCDr_fields[] = 1081 { 1082 /* RXD_DFE_TAP11:0:3 */ 1083 PHYMOD_SYMBOL_FIELD_ENCODE(638, 3, 0), 1084 /* RXC_DFE_TAP11:4:7 */ 1085 PHYMOD_SYMBOL_FIELD_ENCODE(612, 7, 4), 1086 /* RXB_DFE_TAP11:8:11 */ 1087 PHYMOD_SYMBOL_FIELD_ENCODE(586, 11, 8), 1088 /* RXA_DFE_TAP11:12:15 */ 1089 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(560, 15, 12) 1090 }; 1091 static uint32_t BCMI_FALCON_XGXS_DSC_RX_DFE_TAP12_ABCDr_fields[] = 1092 { 1093 /* RXD_DFE_TAP12:0:3 */ 1094 PHYMOD_SYMBOL_FIELD_ENCODE(640, 3, 0), 1095 /* RXC_DFE_TAP12:4:7 */ 1096 PHYMOD_SYMBOL_FIELD_ENCODE(614, 7, 4), 1097 /* RXB_DFE_TAP12:8:11 */ 1098 PHYMOD_SYMBOL_FIELD_ENCODE(588, 11, 8), 1099 /* RXA_DFE_TAP12:12:15 */ 1100 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(562, 15, 12) 1101 }; 1102 static uint32_t BCMI_FALCON_XGXS_DSC_RX_DFE_TAP13_14_MUX_ABCDr_fields[] = 1103 { 1104 /* RXD_DFE_TAP14_MUX:0:1 */ 1105 PHYMOD_SYMBOL_FIELD_ENCODE(645, 1, 0), 1106 /* RXD_DFE_TAP13_MUX:2:3 */ 1107 PHYMOD_SYMBOL_FIELD_ENCODE(643, 3, 2), 1108 /* RXC_DFE_TAP14_MUX:4:5 */ 1109 PHYMOD_SYMBOL_FIELD_ENCODE(619, 5, 4), 1110 /* RXC_DFE_TAP13_MUX:6:7 */ 1111 PHYMOD_SYMBOL_FIELD_ENCODE(617, 7, 6), 1112 /* RXB_DFE_TAP14_MUX:8:9 */ 1113 PHYMOD_SYMBOL_FIELD_ENCODE(593, 9, 8), 1114 /* RXB_DFE_TAP13_MUX:10:11 */ 1115 PHYMOD_SYMBOL_FIELD_ENCODE(591, 11, 10), 1116 /* RXA_DFE_TAP14_MUX:12:13 */ 1117 PHYMOD_SYMBOL_FIELD_ENCODE(567, 13, 12), 1118 /* RXA_DFE_TAP13_MUX:14:15 */ 1119 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(565, 15, 14) 1120 }; 1121 static uint32_t BCMI_FALCON_XGXS_DSC_RX_DFE_TAP13_ABCDr_fields[] = 1122 { 1123 /* RXD_DFE_TAP13:0:3 */ 1124 PHYMOD_SYMBOL_FIELD_ENCODE(642, 3, 0), 1125 /* RXC_DFE_TAP13:4:7 */ 1126 PHYMOD_SYMBOL_FIELD_ENCODE(616, 7, 4), 1127 /* RXB_DFE_TAP13:8:11 */ 1128 PHYMOD_SYMBOL_FIELD_ENCODE(590, 11, 8), 1129 /* RXA_DFE_TAP13:12:15 */ 1130 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(564, 15, 12) 1131 }; 1132 static uint32_t BCMI_FALCON_XGXS_DSC_RX_DFE_TAP14_ABCDr_fields[] = 1133 { 1134 /* RXD_DFE_TAP14:0:3 */ 1135 PHYMOD_SYMBOL_FIELD_ENCODE(644, 3, 0), 1136 /* RXC_DFE_TAP14:4:7 */ 1137 PHYMOD_SYMBOL_FIELD_ENCODE(618, 7, 4), 1138 /* RXB_DFE_TAP14:8:11 */ 1139 PHYMOD_SYMBOL_FIELD_ENCODE(592, 11, 8), 1140 /* RXA_DFE_TAP14:12:15 */ 1141 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(566, 15, 12) 1142 }; 1143 static uint32_t BCMI_FALCON_XGXS_DSC_RX_DFE_TAP2_ABr_fields[] = 1144 { 1145 /* RXB_DFE_TAP2:0:4 */ 1146 PHYMOD_SYMBOL_FIELD_ENCODE(594, 4, 0), 1147 /* RXA_DFE_TAP2:8:12 */ 1148 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(568, 12, 8) 1149 }; 1150 static uint32_t BCMI_FALCON_XGXS_DSC_RX_DFE_TAP2_CDr_fields[] = 1151 { 1152 /* RXD_DFE_TAP2:0:4 */ 1153 PHYMOD_SYMBOL_FIELD_ENCODE(646, 4, 0), 1154 /* RXC_DFE_TAP2:8:12 */ 1155 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(620, 12, 8) 1156 }; 1157 static uint32_t BCMI_FALCON_XGXS_DSC_RX_DFE_TAP3_ABr_fields[] = 1158 { 1159 /* RXB_DFE_TAP3:0:4 */ 1160 PHYMOD_SYMBOL_FIELD_ENCODE(595, 4, 0), 1161 /* RXA_DFE_TAP3:8:12 */ 1162 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(569, 12, 8) 1163 }; 1164 static uint32_t BCMI_FALCON_XGXS_DSC_RX_DFE_TAP3_CDr_fields[] = 1165 { 1166 /* RXD_DFE_TAP3:0:4 */ 1167 PHYMOD_SYMBOL_FIELD_ENCODE(647, 4, 0), 1168 /* RXC_DFE_TAP3:8:12 */ 1169 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(621, 12, 8) 1170 }; 1171 static uint32_t BCMI_FALCON_XGXS_DSC_RX_DFE_TAP4_ABCDr_fields[] = 1172 { 1173 /* RXD_DFE_TAP4:0:3 */ 1174 PHYMOD_SYMBOL_FIELD_ENCODE(648, 3, 0), 1175 /* RXC_DFE_TAP4:4:7 */ 1176 PHYMOD_SYMBOL_FIELD_ENCODE(622, 7, 4), 1177 /* RXB_DFE_TAP4:8:11 */ 1178 PHYMOD_SYMBOL_FIELD_ENCODE(596, 11, 8), 1179 /* RXA_DFE_TAP4:12:15 */ 1180 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(570, 15, 12) 1181 }; 1182 static uint32_t BCMI_FALCON_XGXS_DSC_RX_DFE_TAP5_ABCDr_fields[] = 1183 { 1184 /* RXD_DFE_TAP5:0:3 */ 1185 PHYMOD_SYMBOL_FIELD_ENCODE(649, 3, 0), 1186 /* RXC_DFE_TAP5:4:7 */ 1187 PHYMOD_SYMBOL_FIELD_ENCODE(623, 7, 4), 1188 /* RXB_DFE_TAP5:8:11 */ 1189 PHYMOD_SYMBOL_FIELD_ENCODE(597, 11, 8), 1190 /* RXA_DFE_TAP5:12:15 */ 1191 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(571, 15, 12) 1192 }; 1193 static uint32_t BCMI_FALCON_XGXS_DSC_RX_DFE_TAP6_ABCDr_fields[] = 1194 { 1195 /* RXD_DFE_TAP6:0:3 */ 1196 PHYMOD_SYMBOL_FIELD_ENCODE(650, 3, 0), 1197 /* RXC_DFE_TAP6:4:7 */ 1198 PHYMOD_SYMBOL_FIELD_ENCODE(624, 7, 4), 1199 /* RXB_DFE_TAP6:8:11 */ 1200 PHYMOD_SYMBOL_FIELD_ENCODE(598, 11, 8), 1201 /* RXA_DFE_TAP6:12:15 */ 1202 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(572, 15, 12) 1203 }; 1204 static uint32_t BCMI_FALCON_XGXS_DSC_RX_DFE_TAP7_8_MUX_ABCDr_fields[] = 1205 { 1206 /* RXD_DFE_TAP8_MUX:0:1 */ 1207 PHYMOD_SYMBOL_FIELD_ENCODE(654, 1, 0), 1208 /* RXD_DFE_TAP7_MUX:2:3 */ 1209 PHYMOD_SYMBOL_FIELD_ENCODE(652, 3, 2), 1210 /* RXC_DFE_TAP8_MUX:4:5 */ 1211 PHYMOD_SYMBOL_FIELD_ENCODE(628, 5, 4), 1212 /* RXC_DFE_TAP7_MUX:6:7 */ 1213 PHYMOD_SYMBOL_FIELD_ENCODE(626, 7, 6), 1214 /* RXB_DFE_TAP8_MUX:8:9 */ 1215 PHYMOD_SYMBOL_FIELD_ENCODE(602, 9, 8), 1216 /* RXB_DFE_TAP7_MUX:10:11 */ 1217 PHYMOD_SYMBOL_FIELD_ENCODE(600, 11, 10), 1218 /* RXA_DFE_TAP8_MUX:12:13 */ 1219 PHYMOD_SYMBOL_FIELD_ENCODE(576, 13, 12), 1220 /* RXA_DFE_TAP7_MUX:14:15 */ 1221 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(574, 15, 14) 1222 }; 1223 static uint32_t BCMI_FALCON_XGXS_DSC_RX_DFE_TAP7_ABCDr_fields[] = 1224 { 1225 /* RXD_DFE_TAP7:0:3 */ 1226 PHYMOD_SYMBOL_FIELD_ENCODE(651, 3, 0), 1227 /* RXC_DFE_TAP7:4:7 */ 1228 PHYMOD_SYMBOL_FIELD_ENCODE(625, 7, 4), 1229 /* RXB_DFE_TAP7:8:11 */ 1230 PHYMOD_SYMBOL_FIELD_ENCODE(599, 11, 8), 1231 /* RXA_DFE_TAP7:12:15 */ 1232 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(573, 15, 12) 1233 }; 1234 static uint32_t BCMI_FALCON_XGXS_DSC_RX_DFE_TAP8_ABCDr_fields[] = 1235 { 1236 /* RXD_DFE_TAP8:0:3 */ 1237 PHYMOD_SYMBOL_FIELD_ENCODE(653, 3, 0), 1238 /* RXC_DFE_TAP8:4:7 */ 1239 PHYMOD_SYMBOL_FIELD_ENCODE(627, 7, 4), 1240 /* RXB_DFE_TAP8:8:11 */ 1241 PHYMOD_SYMBOL_FIELD_ENCODE(601, 11, 8), 1242 /* RXA_DFE_TAP8:12:15 */ 1243 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(575, 15, 12) 1244 }; 1245 static uint32_t BCMI_FALCON_XGXS_DSC_RX_DFE_TAP9_10_MUX_ABCDr_fields[] = 1246 { 1247 /* RXD_DFE_TAP10_MUX:0:1 */ 1248 PHYMOD_SYMBOL_FIELD_ENCODE(637, 1, 0), 1249 /* RXD_DFE_TAP9_MUX:2:3 */ 1250 PHYMOD_SYMBOL_FIELD_ENCODE(656, 3, 2), 1251 /* RXC_DFE_TAP10_MUX:4:5 */ 1252 PHYMOD_SYMBOL_FIELD_ENCODE(611, 5, 4), 1253 /* RXC_DFE_TAP9_MUX:6:7 */ 1254 PHYMOD_SYMBOL_FIELD_ENCODE(630, 7, 6), 1255 /* RXB_DFE_TAP10_MUX:8:9 */ 1256 PHYMOD_SYMBOL_FIELD_ENCODE(585, 9, 8), 1257 /* RXB_DFE_TAP9_MUX:10:11 */ 1258 PHYMOD_SYMBOL_FIELD_ENCODE(604, 11, 10), 1259 /* RXA_DFE_TAP10_MUX:12:13 */ 1260 PHYMOD_SYMBOL_FIELD_ENCODE(559, 13, 12), 1261 /* RXA_DFE_TAP9_MUX:14:15 */ 1262 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(578, 15, 14) 1263 }; 1264 static uint32_t BCMI_FALCON_XGXS_DSC_RX_DFE_TAP9_ABCDr_fields[] = 1265 { 1266 /* RXD_DFE_TAP9:0:3 */ 1267 PHYMOD_SYMBOL_FIELD_ENCODE(655, 3, 0), 1268 /* RXC_DFE_TAP9:4:7 */ 1269 PHYMOD_SYMBOL_FIELD_ENCODE(629, 7, 4), 1270 /* RXB_DFE_TAP9:8:11 */ 1271 PHYMOD_SYMBOL_FIELD_ENCODE(603, 11, 8), 1272 /* RXA_DFE_TAP9:12:15 */ 1273 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(577, 15, 12) 1274 }; 1275 static uint32_t BCMI_FALCON_XGXS_DSC_RX_PF_CTL_DC_OFFSr_fields[] = 1276 { 1277 /* RX_PF2_CTRL:8:10 */ 1278 PHYMOD_SYMBOL_FIELD_ENCODE(669, 10, 8), 1279 /* RX_PF_CTRL:11:14 */ 1280 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(670, 14, 11) 1281 }; 1282 static uint32_t BCMI_FALCON_XGXS_DSC_RX_PHASE_LMS_THR_SELr_fields[] = 1283 { 1284 /* RX_LMS_THRESH_SEL:0:7 */ 1285 PHYMOD_SYMBOL_FIELD_ENCODE(668, 7, 0), 1286 /* RX_PHASE_THRESH_SEL:8:14 */ 1287 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(671, 14, 8) 1288 }; 1289 static uint32_t BCMI_FALCON_XGXS_DSC_RX_PI_CNT_BIN_Dr_fields[] = 1290 { 1291 /* RX_PI_CNT_BIN_D:0:7 */ 1292 PHYMOD_SYMBOL_FIELD_ENCODE(672, 7, 0), 1293 /* RX_PI_CNT_BIN_DQ:8:15 */ 1294 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(673, 15, 8) 1295 }; 1296 static uint32_t BCMI_FALCON_XGXS_DSC_RX_PI_CNT_BIN_Lr_fields[] = 1297 { 1298 /* RX_PI_CNT_BIN_L:0:7 */ 1299 PHYMOD_SYMBOL_FIELD_ENCODE(676, 7, 0), 1300 /* RX_PI_CNT_BIN_LQ:8:15 */ 1301 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(677, 15, 8) 1302 }; 1303 static uint32_t BCMI_FALCON_XGXS_DSC_RX_PI_CNT_BIN_LDr_fields[] = 1304 { 1305 /* RX_PI_CNT_BIN_L_LD:0:7 */ 1306 PHYMOD_SYMBOL_FIELD_ENCODE(678, 7, 0), 1307 /* RX_PI_CNT_BIN_D_LD:8:15 */ 1308 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(674, 15, 8) 1309 }; 1310 static uint32_t BCMI_FALCON_XGXS_DSC_RX_PI_CNT_BIN_Pr_fields[] = 1311 { 1312 /* RX_PI_CNT_BIN_P:0:7 */ 1313 PHYMOD_SYMBOL_FIELD_ENCODE(679, 7, 0), 1314 /* RX_PI_CNT_BIN_PQ:8:15 */ 1315 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(680, 15, 8) 1316 }; 1317 static uint32_t BCMI_FALCON_XGXS_DSC_RX_PI_CNT_BIN_PDr_fields[] = 1318 { 1319 /* RX_PI_CNT_BIN_P_PD:0:7 */ 1320 PHYMOD_SYMBOL_FIELD_ENCODE(681, 7, 0), 1321 /* RX_PI_CNT_BIN_D_PD:8:15 */ 1322 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(675, 15, 8) 1323 }; 1324 static uint32_t BCMI_FALCON_XGXS_DSC_RX_PI_CTLr_fields[] = 1325 { 1326 /* RX_PI_SLICERS_EN:0:5 */ 1327 PHYMOD_SYMBOL_FIELD_ENCODE(686, 5, 0), 1328 /* RX_PI_PHASE_STEP_CNT:6:8 */ 1329 PHYMOD_SYMBOL_FIELD_ENCODE(684, 8, 6), 1330 /* RX_PI_PHASE_STEP_DIR:9:9 */ 1331 PHYMOD_SYMBOL_FIELD_ENCODE(685, 9, 9), 1332 /* RX_PI_MANUAL_MODE:10:10 */ 1333 PHYMOD_SYMBOL_FIELD_ENCODE(682, 10, 10), 1334 /* RX_PI_MANUAL_STROBE:11:11 */ 1335 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(683, 11, 11) 1336 }; 1337 static uint32_t BCMI_FALCON_XGXS_DSC_SCRATCHr_fields[] = 1338 { 1339 /* UC_DSC_SCRATCH:0:15 */ 1340 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(824, 15, 0) 1341 }; 1342 static uint32_t BCMI_FALCON_XGXS_DSC_SM_CTL0r_fields[] = 1343 { 1344 /* EEE_MODE_EN:1:1 */ 1345 PHYMOD_SYMBOL_FIELD_ENCODE(308, 1, 1), 1346 /* EEE_QUIET_RX_AFE_PWRDWN_VAL:2:2 */ 1347 PHYMOD_SYMBOL_FIELD_ENCODE(312, 2, 2), 1348 /* IGNORE_RX_MODE:3:3 */ 1349 PHYMOD_SYMBOL_FIELD_ENCODE(336, 3, 3), 1350 /* CL72_TIMER_EN:4:4 */ 1351 PHYMOD_SYMBOL_FIELD_ENCODE(218, 4, 4), 1352 /* UC_TUNE_EN:5:5 */ 1353 PHYMOD_SYMBOL_FIELD_ENCODE(827, 5, 5), 1354 /* HW_TUNE_EN:6:6 */ 1355 PHYMOD_SYMBOL_FIELD_ENCODE(333, 6, 6), 1356 /* EEE_MEASURE_EN:8:8 */ 1357 PHYMOD_SYMBOL_FIELD_ENCODE(307, 8, 8), 1358 /* UC_ACK_DSC_EEE_DONE:11:11 */ 1359 PHYMOD_SYMBOL_FIELD_ENCODE(816, 11, 11), 1360 /* UC_ACK_DSC_RESTART:13:13 */ 1361 PHYMOD_SYMBOL_FIELD_ENCODE(817, 13, 13), 1362 /* UC_ACK_DSC_CONFIG:14:14 */ 1363 PHYMOD_SYMBOL_FIELD_ENCODE(815, 14, 14), 1364 /* SET_MEAS_INCOMPLETE:15:15 */ 1365 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(693, 15, 15) 1366 }; 1367 static uint32_t BCMI_FALCON_XGXS_DSC_SM_CTL1r_fields[] = 1368 { 1369 /* RX_DSC_LOCK_FRC:0:0 */ 1370 PHYMOD_SYMBOL_FIELD_ENCODE(666, 0, 0), 1371 /* RX_DSC_LOCK_FRC_VAL:1:1 */ 1372 PHYMOD_SYMBOL_FIELD_ENCODE(667, 1, 1), 1373 /* DSC_CLR_FRC:2:2 */ 1374 PHYMOD_SYMBOL_FIELD_ENCODE(293, 2, 2), 1375 /* DSC_CLR_FRC_VAL:3:3 */ 1376 PHYMOD_SYMBOL_FIELD_ENCODE(294, 3, 3), 1377 /* TRNSUM_FRZ_FRC:4:4 */ 1378 PHYMOD_SYMBOL_FIELD_ENCODE(735, 4, 4), 1379 /* TRNSUM_FRZ_FRC_VAL:5:5 */ 1380 PHYMOD_SYMBOL_FIELD_ENCODE(736, 5, 5), 1381 /* TIMER_DONE_FRC:6:6 */ 1382 PHYMOD_SYMBOL_FIELD_ENCODE(715, 6, 6), 1383 /* TIMER_DONE_FRC_VAL:7:7 */ 1384 PHYMOD_SYMBOL_FIELD_ENCODE(716, 7, 7), 1385 /* FREQ_UPD_EN_FRC:8:8 */ 1386 PHYMOD_SYMBOL_FIELD_ENCODE(328, 8, 8), 1387 /* FREQ_UPD_EN_FRC_VAL:9:9 */ 1388 PHYMOD_SYMBOL_FIELD_ENCODE(329, 9, 9), 1389 /* CDR_FRZ_FRC:10:10 */ 1390 PHYMOD_SYMBOL_FIELD_ENCODE(206, 10, 10), 1391 /* CDR_FRZ_FRC_VAL:11:11 */ 1392 PHYMOD_SYMBOL_FIELD_ENCODE(207, 11, 11), 1393 /* TRNSUM_CLR_FRC:12:12 */ 1394 PHYMOD_SYMBOL_FIELD_ENCODE(725, 12, 12), 1395 /* TRNSUM_CLR_FRC_VAL:13:13 */ 1396 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(726, 13, 13) 1397 }; 1398 static uint32_t BCMI_FALCON_XGXS_DSC_SM_CTL2r_fields[] = 1399 { 1400 /* EEE_LFSR_CNT:0:12 */ 1401 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(305, 12, 0) 1402 }; 1403 static uint32_t BCMI_FALCON_XGXS_DSC_SM_CTL3r_fields[] = 1404 { 1405 /* MEASURE_LFSR_CNT:0:12 */ 1406 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(376, 12, 0) 1407 }; 1408 static uint32_t BCMI_FALCON_XGXS_DSC_SM_CTL4r_fields[] = 1409 { 1410 /* ACQ_CDR_TIMEOUT:0:4 */ 1411 PHYMOD_SYMBOL_FIELD_ENCODE(0, 4, 0), 1412 /* CDR_SETTLE_TIMEOUT:5:9 */ 1413 PHYMOD_SYMBOL_FIELD_ENCODE(215, 9, 5), 1414 /* HW_TUNE_TIMEOUT:10:14 */ 1415 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(334, 14, 10) 1416 }; 1417 static uint32_t BCMI_FALCON_XGXS_DSC_SM_CTL5r_fields[] = 1418 { 1419 /* MEASURE_TIMEOUT:0:4 */ 1420 PHYMOD_SYMBOL_FIELD_ENCODE(377, 4, 0), 1421 /* EEE_ACQ_CDR_TIMEOUT:5:9 */ 1422 PHYMOD_SYMBOL_FIELD_ENCODE(301, 9, 5), 1423 /* EEE_CDR_SETTLE_TIMEOUT:10:14 */ 1424 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(303, 14, 10) 1425 }; 1426 static uint32_t BCMI_FALCON_XGXS_DSC_SM_CTL6r_fields[] = 1427 { 1428 /* EEE_HW_TUNE_TIMEOUT:0:4 */ 1429 PHYMOD_SYMBOL_FIELD_ENCODE(304, 4, 0), 1430 /* EEE_ANA_PWR_TIMEOUT:10:14 */ 1431 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(302, 14, 10) 1432 }; 1433 static uint32_t BCMI_FALCON_XGXS_DSC_SM_CTL7r_fields[] = 1434 { 1435 /* CDR_BWSEL_INTEG_ACQCDR:0:3 */ 1436 PHYMOD_SYMBOL_FIELD_ENCODE(197, 3, 0), 1437 /* CDR_BWSEL_INTEG_EEE_ACQCDR:4:7 */ 1438 PHYMOD_SYMBOL_FIELD_ENCODE(198, 7, 4), 1439 /* CDR_BWSEL_INTEG_NORM:8:11 */ 1440 PHYMOD_SYMBOL_FIELD_ENCODE(199, 11, 8), 1441 /* CDR_BWSEL_PROP_ACQCDR:12:12 */ 1442 PHYMOD_SYMBOL_FIELD_ENCODE(200, 12, 12), 1443 /* CDR_BWSEL_PROP_NORM:14:14 */ 1444 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(202, 14, 14) 1445 }; 1446 static uint32_t BCMI_FALCON_XGXS_DSC_SM_CTL8r_fields[] = 1447 { 1448 /* PHASE_ERR_OFFSET:0:3 */ 1449 PHYMOD_SYMBOL_FIELD_ENCODE(466, 3, 0), 1450 /* EEE_PHASE_ERR_OFFSET:4:7 */ 1451 PHYMOD_SYMBOL_FIELD_ENCODE(309, 7, 4), 1452 /* PHASE_ERR_OFFSET_EN:8:9 */ 1453 PHYMOD_SYMBOL_FIELD_ENCODE(467, 9, 8), 1454 /* EEE_PHASE_ERR_OFFSET_EN:10:11 */ 1455 PHYMOD_SYMBOL_FIELD_ENCODE(310, 11, 10), 1456 /* CDR_BWSEL_PROP_EEE_ACQCDR:14:14 */ 1457 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(201, 14, 14) 1458 }; 1459 static uint32_t BCMI_FALCON_XGXS_DSC_SM_CTL9r_fields[] = 1460 { 1461 /* RX_RESTART_PMD:0:0 */ 1462 PHYMOD_SYMBOL_FIELD_ENCODE(688, 0, 0), 1463 /* RX_RESTART_PMD_HOLD:1:1 */ 1464 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(689, 1, 1) 1465 }; 1466 static uint32_t BCMI_FALCON_XGXS_DSC_SM_STS_DSC_LOCKr_fields[] = 1467 { 1468 /* RX_DSC_LOCK:0:0 */ 1469 PHYMOD_SYMBOL_FIELD_ENCODE(665, 0, 0), 1470 /* MEAS_INCOMPLETE:1:1 */ 1471 PHYMOD_SYMBOL_FIELD_ENCODE(378, 1, 1), 1472 /* EEE_MEASURE_CNT:7:15 */ 1473 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(306, 15, 7) 1474 }; 1475 static uint32_t BCMI_FALCON_XGXS_DSC_SM_STS_DSC_STr_fields[] = 1476 { 1477 /* DSC_SM_SCRATCH:0:3 */ 1478 PHYMOD_SYMBOL_FIELD_ENCODE(297, 3, 0), 1479 /* DSC_SM_READY_FOR_CMD:4:4 */ 1480 PHYMOD_SYMBOL_FIELD_ENCODE(296, 4, 4), 1481 /* DSC_SM_GP_UC_REQ:5:10 */ 1482 PHYMOD_SYMBOL_FIELD_ENCODE(295, 10, 5), 1483 /* DSC_STATE:11:15 */ 1484 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(298, 15, 11) 1485 }; 1486 static uint32_t BCMI_FALCON_XGXS_DSC_SM_STS_DSC_ST_EEE_ONE_HOTr_fields[] = 1487 { 1488 /* DSC_STATE_EEE_ONE_HOT:0:6 */ 1489 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(299, 6, 0) 1490 }; 1491 static uint32_t BCMI_FALCON_XGXS_DSC_SM_STS_DSC_ST_ONE_HOTr_fields[] = 1492 { 1493 /* DSC_STATE_ONE_HOT:0:9 */ 1494 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(300, 9, 0) 1495 }; 1496 static uint32_t BCMI_FALCON_XGXS_DSC_SM_STS_RESTARTr_fields[] = 1497 { 1498 /* RESTART_PI_EXT_MODE:0:0 */ 1499 PHYMOD_SYMBOL_FIELD_ENCODE(533, 0, 0), 1500 /* RESTART_SIGDET:1:1 */ 1501 PHYMOD_SYMBOL_FIELD_ENCODE(535, 1, 1), 1502 /* RESTART_PMD_RESTART:2:2 */ 1503 PHYMOD_SYMBOL_FIELD_ENCODE(534, 2, 2), 1504 /* EEE_QUIET_FROM_EEE_STATES:3:3 */ 1505 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(311, 3, 3) 1506 }; 1507 static uint32_t BCMI_FALCON_XGXS_DSC_TRNSUMr_fields[] = 1508 { 1509 /* TRNSUM:0:15 */ 1510 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(719, 15, 0) 1511 }; 1512 static uint32_t BCMI_FALCON_XGXS_DSC_TRNSUM_Ar_fields[] = 1513 { 1514 /* TRNSUM_A:0:15 */ 1515 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(720, 15, 0) 1516 }; 1517 static uint32_t BCMI_FALCON_XGXS_DSC_TRNSUM_A_LOr_fields[] = 1518 { 1519 /* TRNSUM_A_LOW:8:15 */ 1520 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(721, 15, 8) 1521 }; 1522 static uint32_t BCMI_FALCON_XGXS_DSC_TRNSUM_Br_fields[] = 1523 { 1524 /* TRNSUM_B:0:15 */ 1525 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(722, 15, 0) 1526 }; 1527 static uint32_t BCMI_FALCON_XGXS_DSC_TRNSUM_B_LOr_fields[] = 1528 { 1529 /* TRNSUM_B_LOW:8:15 */ 1530 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(723, 15, 8) 1531 }; 1532 static uint32_t BCMI_FALCON_XGXS_DSC_TRNSUM_Cr_fields[] = 1533 { 1534 /* TRNSUM_C:0:15 */ 1535 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(724, 15, 0) 1536 }; 1537 static uint32_t BCMI_FALCON_XGXS_DSC_TRNSUM_CTLr_fields[] = 1538 { 1539 /* TRNSUM_GAIN:0:1 */ 1540 PHYMOD_SYMBOL_FIELD_ENCODE(737, 1, 0), 1541 /* TRNSUM_SEL_EMUX:2:2 */ 1542 PHYMOD_SYMBOL_FIELD_ENCODE(745, 2, 2), 1543 /* TRNSUM_TAP_RANGE_SEL:4:6 */ 1544 PHYMOD_SYMBOL_FIELD_ENCODE(747, 6, 4), 1545 /* TRNSUM_COR_SEL:8:9 */ 1546 PHYMOD_SYMBOL_FIELD_ENCODE(727, 9, 8), 1547 /* TRNSUM_QPHASE_MULT_EN:12:12 */ 1548 PHYMOD_SYMBOL_FIELD_ENCODE(743, 12, 12), 1549 /* TRNSUM_RANDOM_TAPSEL_DISABLE:13:13 */ 1550 PHYMOD_SYMBOL_FIELD_ENCODE(744, 13, 13), 1551 /* TRNSUM_EYE_CLOSURE_EN:14:14 */ 1552 PHYMOD_SYMBOL_FIELD_ENCODE(734, 14, 14), 1553 /* TRNSUM_EN:15:15 */ 1554 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(732, 15, 15) 1555 }; 1556 static uint32_t BCMI_FALCON_XGXS_DSC_TRNSUM_C_LOr_fields[] = 1557 { 1558 /* TRNSUM_C_LOW:8:15 */ 1559 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(728, 15, 8) 1560 }; 1561 static uint32_t BCMI_FALCON_XGXS_DSC_TRNSUM_Dr_fields[] = 1562 { 1563 /* TRNSUM_D:0:15 */ 1564 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(729, 15, 0) 1565 }; 1566 static uint32_t BCMI_FALCON_XGXS_DSC_TRNSUM_D_LOr_fields[] = 1567 { 1568 /* TRNSUM_D_LOW:8:15 */ 1569 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(730, 15, 8) 1570 }; 1571 static uint32_t BCMI_FALCON_XGXS_DSC_TRNSUM_LOr_fields[] = 1572 { 1573 /* TRNSUM_LOW:6:15 */ 1574 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(739, 15, 6) 1575 }; 1576 static uint32_t BCMI_FALCON_XGXS_DSC_TRNSUM_MISCr_fields[] = 1577 { 1578 /* TDT_PRBS_SLIP:0:0 */ 1579 PHYMOD_SYMBOL_FIELD_ENCODE(711, 0, 0), 1580 /* CDR_1G_TRNSUM_EN:1:1 */ 1581 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(196, 1, 1) 1582 }; 1583 static uint32_t BCMI_FALCON_XGXS_DSC_TRNSUM_PAT_CTL1r_fields[] = 1584 { 1585 /* TRNSUM_PATTERN:0:9 */ 1586 PHYMOD_SYMBOL_FIELD_ENCODE(740, 9, 0), 1587 /* TRNSUM_PATTERN_FULL_CHECK_OFF:12:12 */ 1588 PHYMOD_SYMBOL_FIELD_ENCODE(742, 12, 12), 1589 /* TRNSUM_EDGE_PATTERN_EN:14:14 */ 1590 PHYMOD_SYMBOL_FIELD_ENCODE(731, 14, 14), 1591 /* TRNSUM_INV_PATTERN_EN:15:15 */ 1592 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(738, 15, 15) 1593 }; 1594 static uint32_t BCMI_FALCON_XGXS_DSC_TRNSUM_PAT_CTL2r_fields[] = 1595 { 1596 /* TRNSUM_PATTERN_BIT_EN:0:9 */ 1597 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(741, 9, 0) 1598 }; 1599 static uint32_t BCMI_FALCON_XGXS_DSC_TRNSUM_TAP_CTLr_fields[] = 1600 { 1601 /* TRNSUM_TAP_EN:0:7 */ 1602 PHYMOD_SYMBOL_FIELD_ENCODE(746, 7, 0), 1603 /* TRNSUM_TAP_SIGN:8:15 */ 1604 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(748, 15, 8) 1605 }; 1606 static uint32_t BCMI_FALCON_XGXS_DSC_TRNSUM_TDT_CTLr_fields[] = 1607 { 1608 /* TDT_BIT_SEL:0:5 */ 1609 PHYMOD_SYMBOL_FIELD_ENCODE(707, 5, 0), 1610 /* TDT_PRBS_MODE:6:6 */ 1611 PHYMOD_SYMBOL_FIELD_ENCODE(710, 6, 6), 1612 /* TDT_TRNSUM_EN:7:7 */ 1613 PHYMOD_SYMBOL_FIELD_ENCODE(712, 7, 7), 1614 /* TDT_CYCLE_SEL:8:11 */ 1615 PHYMOD_SYMBOL_FIELD_ENCODE(709, 11, 8), 1616 /* TDT_CYCLE_BIN:12:15 */ 1617 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(708, 15, 12) 1618 }; 1619 static uint32_t BCMI_FALCON_XGXS_DSC_UC_CTLr_fields[] = 1620 { 1621 /* UC_DSC_GP_UC_REQ:0:5 */ 1622 PHYMOD_SYMBOL_FIELD_ENCODE(822, 5, 0), 1623 /* UC_DSC_ERROR_FOUND:6:6 */ 1624 PHYMOD_SYMBOL_FIELD_ENCODE(821, 6, 6), 1625 /* UC_DSC_READY_FOR_CMD:7:7 */ 1626 PHYMOD_SYMBOL_FIELD_ENCODE(823, 7, 7), 1627 /* UC_DSC_SUPP_INFO:8:15 */ 1628 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(825, 15, 8) 1629 }; 1630 static uint32_t BCMI_FALCON_XGXS_DSC_VGA_CTL1r_fields[] = 1631 { 1632 /* VGA_TIMER_T2:0:2 */ 1633 PHYMOD_SYMBOL_FIELD_ENCODE(835, 2, 0), 1634 /* UC_TRNSUM_EN:3:3 */ 1635 PHYMOD_SYMBOL_FIELD_ENCODE(826, 3, 3), 1636 /* DC_OFFS_WRITE_EN:4:4 */ 1637 PHYMOD_SYMBOL_FIELD_ENCODE(284, 4, 4), 1638 /* VGA_DEC:5:5 */ 1639 PHYMOD_SYMBOL_FIELD_ENCODE(833, 5, 5), 1640 /* VGA_INC:7:7 */ 1641 PHYMOD_SYMBOL_FIELD_ENCODE(834, 7, 7), 1642 /* RX_VGA_CTRL_VAL:8:14 */ 1643 PHYMOD_SYMBOL_FIELD_ENCODE(691, 14, 8), 1644 /* VGA_WRITE:15:15 */ 1645 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(836, 15, 15) 1646 }; 1647 static uint32_t BCMI_FALCON_XGXS_DSC_VGA_D_THR_STSr_fields[] = 1648 { 1649 /* RX_DATA_THRESH_SEL:0:6 */ 1650 PHYMOD_SYMBOL_FIELD_ENCODE(664, 6, 0), 1651 /* RX_VGA_CTRL:8:14 */ 1652 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(690, 14, 8) 1653 }; 1654 static uint32_t BCMI_FALCON_XGXS_MDIO_AERr_fields[] = 1655 { 1656 /* MDIO_AER:0:15 */ 1657 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(362, 15, 0) 1658 }; 1659 static uint32_t BCMI_FALCON_XGXS_MDIO_BCST_PORT_ADDRr_fields[] = 1660 { 1661 /* MDIO_BRCST_PORT_ADDR:0:4 */ 1662 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(364, 4, 0) 1663 }; 1664 static uint32_t BCMI_FALCON_XGXS_MDIO_BLK_ADDRr_fields[] = 1665 { 1666 /* MDIO_BLK_ADDR:4:14 */ 1667 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(363, 14, 4) 1668 }; 1669 static uint32_t BCMI_FALCON_XGXS_MDIO_MASKDATAr_fields[] = 1670 { 1671 /* MDIO_MASKDATA:0:15 */ 1672 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(373, 15, 0) 1673 }; 1674 static uint32_t BCMI_FALCON_XGXS_MDIO_MMD_SELr_fields[] = 1675 { 1676 /* MDIO_DEV_CL22_EN:0:0 */ 1677 PHYMOD_SYMBOL_FIELD_ENCODE(367, 0, 0), 1678 /* MDIO_DEV_PMD_EN:2:2 */ 1679 PHYMOD_SYMBOL_FIELD_ENCODE(371, 2, 2), 1680 /* MDIO_DEV_AN_EN:3:3 */ 1681 PHYMOD_SYMBOL_FIELD_ENCODE(366, 3, 3), 1682 /* MDIO_DEV_PHY_EN:4:4 */ 1683 PHYMOD_SYMBOL_FIELD_ENCODE(370, 4, 4), 1684 /* MDIO_DEV_DTE_EN:5:5 */ 1685 PHYMOD_SYMBOL_FIELD_ENCODE(368, 5, 5), 1686 /* MDIO_DEV_PCS_EN:6:6 */ 1687 PHYMOD_SYMBOL_FIELD_ENCODE(369, 6, 6), 1688 /* MDIO_MULTI_MMDS_EN:14:14 */ 1689 PHYMOD_SYMBOL_FIELD_ENCODE(374, 14, 14), 1690 /* MDIO_MULTI_PRTS_EN:15:15 */ 1691 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(375, 15, 15) 1692 }; 1693 static uint32_t BCMI_FALCON_XGXS_PATT_GEN_SEQ0r_fields[] = 1694 { 1695 /* PATT_GEN_SEQ_0:0:15 */ 1696 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(449, 15, 0) 1697 }; 1698 static uint32_t BCMI_FALCON_XGXS_PATT_GEN_SEQ1r_fields[] = 1699 { 1700 /* PATT_GEN_SEQ_1:0:15 */ 1701 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(450, 15, 0) 1702 }; 1703 static uint32_t BCMI_FALCON_XGXS_PATT_GEN_SEQ2r_fields[] = 1704 { 1705 /* PATT_GEN_SEQ_2:0:15 */ 1706 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(456, 15, 0) 1707 }; 1708 static uint32_t BCMI_FALCON_XGXS_PATT_GEN_SEQ3r_fields[] = 1709 { 1710 /* PATT_GEN_SEQ_3:0:15 */ 1711 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(457, 15, 0) 1712 }; 1713 static uint32_t BCMI_FALCON_XGXS_PATT_GEN_SEQ4r_fields[] = 1714 { 1715 /* PATT_GEN_SEQ_4:0:15 */ 1716 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(458, 15, 0) 1717 }; 1718 static uint32_t BCMI_FALCON_XGXS_PATT_GEN_SEQ5r_fields[] = 1719 { 1720 /* PATT_GEN_SEQ_5:0:15 */ 1721 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(459, 15, 0) 1722 }; 1723 static uint32_t BCMI_FALCON_XGXS_PATT_GEN_SEQ6r_fields[] = 1724 { 1725 /* PATT_GEN_SEQ_6:0:15 */ 1726 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(460, 15, 0) 1727 }; 1728 static uint32_t BCMI_FALCON_XGXS_PATT_GEN_SEQ7r_fields[] = 1729 { 1730 /* PATT_GEN_SEQ_7:0:15 */ 1731 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(461, 15, 0) 1732 }; 1733 static uint32_t BCMI_FALCON_XGXS_PATT_GEN_SEQ8r_fields[] = 1734 { 1735 /* PATT_GEN_SEQ_8:0:15 */ 1736 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(462, 15, 0) 1737 }; 1738 static uint32_t BCMI_FALCON_XGXS_PATT_GEN_SEQ9r_fields[] = 1739 { 1740 /* PATT_GEN_SEQ_9:0:15 */ 1741 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(463, 15, 0) 1742 }; 1743 static uint32_t BCMI_FALCON_XGXS_PATT_GEN_SEQ_10r_fields[] = 1744 { 1745 /* PATT_GEN_SEQ_10:0:15 */ 1746 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(451, 15, 0) 1747 }; 1748 static uint32_t BCMI_FALCON_XGXS_PATT_GEN_SEQ_11r_fields[] = 1749 { 1750 /* PATT_GEN_SEQ_11:0:15 */ 1751 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(452, 15, 0) 1752 }; 1753 static uint32_t BCMI_FALCON_XGXS_PATT_GEN_SEQ_12r_fields[] = 1754 { 1755 /* PATT_GEN_SEQ_12:0:15 */ 1756 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(453, 15, 0) 1757 }; 1758 static uint32_t BCMI_FALCON_XGXS_PATT_GEN_SEQ_13r_fields[] = 1759 { 1760 /* PATT_GEN_SEQ_13:0:15 */ 1761 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(454, 15, 0) 1762 }; 1763 static uint32_t BCMI_FALCON_XGXS_PATT_GEN_SEQ_14r_fields[] = 1764 { 1765 /* PATT_GEN_SEQ_14:0:15 */ 1766 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(455, 15, 0) 1767 }; 1768 static uint32_t BCMI_FALCON_XGXS_PLL_CAL_CTL0r_fields[] = 1769 { 1770 /* VCO_STEP_TIME:0:7 */ 1771 PHYMOD_SYMBOL_FIELD_ENCODE(832, 7, 0), 1772 /* VCO_START_TIME:8:15 */ 1773 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(831, 15, 8) 1774 }; 1775 static uint32_t BCMI_FALCON_XGXS_PLL_CAL_CTL1r_fields[] = 1776 { 1777 /* RETRY_TIME:0:7 */ 1778 PHYMOD_SYMBOL_FIELD_ENCODE(537, 7, 0), 1779 /* PRE_FREQ_DET_TIME:8:15 */ 1780 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(526, 15, 8) 1781 }; 1782 static uint32_t BCMI_FALCON_XGXS_PLL_CAL_CTL2r_fields[] = 1783 { 1784 /* WIN_CAL_CNTR:0:7 */ 1785 PHYMOD_SYMBOL_FIELD_ENCODE(837, 7, 0), 1786 /* RES_CAL_CNTR:8:15 */ 1787 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(536, 15, 8) 1788 }; 1789 static uint32_t BCMI_FALCON_XGXS_PLL_CAL_CTL3r_fields[] = 1790 { 1791 /* FAST_SEARCH_MODE:0:0 */ 1792 PHYMOD_SYMBOL_FIELD_ENCODE(320, 0, 0), 1793 /* CAP_CNT_MASK_EN:1:1 */ 1794 PHYMOD_SYMBOL_FIELD_ENCODE(178, 1, 1), 1795 /* CAP_SEQ_CYA:2:2 */ 1796 PHYMOD_SYMBOL_FIELD_ENCODE(190, 2, 2), 1797 /* CAP_RESTART:3:3 */ 1798 PHYMOD_SYMBOL_FIELD_ENCODE(185, 3, 3), 1799 /* CAP_RETRY_EN:4:4 */ 1800 PHYMOD_SYMBOL_FIELD_ENCODE(186, 4, 4), 1801 /* CAP_FORCE_SLOWDOWN:5:5 */ 1802 PHYMOD_SYMBOL_FIELD_ENCODE(181, 5, 5), 1803 /* CAP_FORCE_SLOWDOWN_EN:6:6 */ 1804 PHYMOD_SYMBOL_FIELD_ENCODE(182, 6, 6), 1805 /* CAP_SELECT_M_EN:7:7 */ 1806 PHYMOD_SYMBOL_FIELD_ENCODE(189, 7, 7), 1807 /* CAP_SELECT_M:8:15 */ 1808 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(188, 15, 8) 1809 }; 1810 static uint32_t BCMI_FALCON_XGXS_PLL_CAL_CTL4r_fields[] = 1811 { 1812 /* PLL_LOCK_FRC_VAL:0:0 */ 1813 PHYMOD_SYMBOL_FIELD_ENCODE(478, 0, 0), 1814 /* PLL_LOCK_FRC:1:1 */ 1815 PHYMOD_SYMBOL_FIELD_ENCODE(477, 1, 1), 1816 /* PLL_FORCE_CAP_PASS:2:2 */ 1817 PHYMOD_SYMBOL_FIELD_ENCODE(471, 2, 2), 1818 /* PLL_FORCE_CAP_PASS_EN:3:3 */ 1819 PHYMOD_SYMBOL_FIELD_ENCODE(472, 3, 3), 1820 /* PLL_FORCE_CAP_DONE:4:4 */ 1821 PHYMOD_SYMBOL_FIELD_ENCODE(469, 4, 4), 1822 /* PLL_FORCE_CAP_DONE_EN:5:5 */ 1823 PHYMOD_SYMBOL_FIELD_ENCODE(470, 5, 5), 1824 /* PLL_FORCE_FPASS:6:6 */ 1825 PHYMOD_SYMBOL_FIELD_ENCODE(475, 6, 6), 1826 /* PLL_FORCE_FDONE:7:7 */ 1827 PHYMOD_SYMBOL_FIELD_ENCODE(473, 7, 7), 1828 /* PLL_FORCE_FDONE_EN:8:8 */ 1829 PHYMOD_SYMBOL_FIELD_ENCODE(474, 8, 8), 1830 /* VCO_RST_EN:9:9 */ 1831 PHYMOD_SYMBOL_FIELD_ENCODE(830, 9, 9), 1832 /* SLOWDN_XOR:10:10 */ 1833 PHYMOD_SYMBOL_FIELD_ENCODE(704, 10, 10), 1834 /* FREQ_MONITOR_EN:11:11 */ 1835 PHYMOD_SYMBOL_FIELD_ENCODE(325, 11, 11), 1836 /* FREQ_DET_RESTART_EN:12:12 */ 1837 PHYMOD_SYMBOL_FIELD_ENCODE(321, 12, 12), 1838 /* FREQ_DET_RETRY_EN:13:13 */ 1839 PHYMOD_SYMBOL_FIELD_ENCODE(322, 13, 13), 1840 /* VCO_DONE_EN:14:14 */ 1841 PHYMOD_SYMBOL_FIELD_ENCODE(828, 14, 14), 1842 /* PLL_SEQ_START:15:15 */ 1843 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(485, 15, 15) 1844 }; 1845 static uint32_t BCMI_FALCON_XGXS_PLL_CAL_CTL5r_fields[] = 1846 { 1847 /* REFCLK_DIVCNT:0:13 */ 1848 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(528, 13, 0) 1849 }; 1850 static uint32_t BCMI_FALCON_XGXS_PLL_CAL_CTL6r_fields[] = 1851 { 1852 /* REFCLK_DIVCNT_SEL:0:2 */ 1853 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(529, 2, 0) 1854 }; 1855 static uint32_t BCMI_FALCON_XGXS_PLL_CAL_CTL7r_fields[] = 1856 { 1857 /* PLL_MODE:0:3 */ 1858 PHYMOD_SYMBOL_FIELD_ENCODE(480, 3, 0), 1859 /* RESCAL_FRC_VAL:4:7 */ 1860 PHYMOD_SYMBOL_FIELD_ENCODE(531, 7, 4), 1861 /* RESCAL_FRC:8:8 */ 1862 PHYMOD_SYMBOL_FIELD_ENCODE(530, 8, 8), 1863 /* VCO_RANGE_ADJUST:9:13 */ 1864 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(829, 13, 9) 1865 }; 1866 static uint32_t BCMI_FALCON_XGXS_PLL_CAL_CTL_STS0r_fields[] = 1867 { 1868 /* PLL_LOCK_LH_LL:0:0 */ 1869 PHYMOD_SYMBOL_FIELD_ENCODE(479, 0, 0), 1870 /* PLL_SEQ_PASS_LH_LL:1:1 */ 1871 PHYMOD_SYMBOL_FIELD_ENCODE(484, 1, 1), 1872 /* PLL_SEQ_DONE_LH_LL:2:2 */ 1873 PHYMOD_SYMBOL_FIELD_ENCODE(482, 2, 2), 1874 /* FREQ_PASS_SM_LH_LL:3:3 */ 1875 PHYMOD_SYMBOL_FIELD_ENCODE(327, 3, 3), 1876 /* FREQ_DONE_SM_LH_LL:4:4 */ 1877 PHYMOD_SYMBOL_FIELD_ENCODE(324, 4, 4), 1878 /* CAP_PASS_LH_LL:5:5 */ 1879 PHYMOD_SYMBOL_FIELD_ENCODE(184, 5, 5), 1880 /* CAP_DONE_LH_LL:6:6 */ 1881 PHYMOD_SYMBOL_FIELD_ENCODE(180, 6, 6), 1882 /* PLL_LOCK:8:8 */ 1883 PHYMOD_SYMBOL_FIELD_ENCODE(476, 8, 8), 1884 /* PLL_SEQ_PASS:9:9 */ 1885 PHYMOD_SYMBOL_FIELD_ENCODE(483, 9, 9), 1886 /* PLL_SEQ_DONE:10:10 */ 1887 PHYMOD_SYMBOL_FIELD_ENCODE(481, 10, 10), 1888 /* FREQ_PASS_SM:11:11 */ 1889 PHYMOD_SYMBOL_FIELD_ENCODE(326, 11, 11), 1890 /* FREQ_DONE_SM:12:12 */ 1891 PHYMOD_SYMBOL_FIELD_ENCODE(323, 12, 12), 1892 /* CAP_PASS:13:13 */ 1893 PHYMOD_SYMBOL_FIELD_ENCODE(183, 13, 13), 1894 /* CAP_DONE:14:14 */ 1895 PHYMOD_SYMBOL_FIELD_ENCODE(179, 14, 14), 1896 /* LOST_PLL_LOCK_SM:15:15 */ 1897 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(357, 15, 15) 1898 }; 1899 static uint32_t BCMI_FALCON_XGXS_PLL_CAL_CTL_STS1r_fields[] = 1900 { 1901 /* CAP_SELECT:0:7 */ 1902 PHYMOD_SYMBOL_FIELD_ENCODE(187, 7, 0), 1903 /* RESCAL_IN:8:11 */ 1904 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(532, 11, 8) 1905 }; 1906 static uint32_t BCMI_FALCON_XGXS_PLL_CAL_CTL_STS_DBGr_fields[] = 1907 { 1908 /* DBG_SLOWDN:0:0 */ 1909 PHYMOD_SYMBOL_FIELD_ENCODE(275, 0, 0), 1910 /* DBG_SLOWDN_CHANGE:1:1 */ 1911 PHYMOD_SYMBOL_FIELD_ENCODE(276, 1, 1), 1912 /* DBG_FDBCK:2:2 */ 1913 PHYMOD_SYMBOL_FIELD_ENCODE(272, 2, 2), 1914 /* DBG_CAP_STATE_ONE_HOT:3:7 */ 1915 PHYMOD_SYMBOL_FIELD_ENCODE(271, 7, 3), 1916 /* DBG_PLL_STATE_ONE_HOT:8:15 */ 1917 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(274, 15, 8) 1918 }; 1919 static uint32_t BCMI_FALCON_XGXS_SIGDET_CTL0r_fields[] = 1920 { 1921 /* SIGNAL_DETECT_FILTER_COUNT:0:4 */ 1922 PHYMOD_SYMBOL_FIELD_ENCODE(698, 4, 0), 1923 /* LOS_FILTER_COUNT:8:12 */ 1924 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(358, 12, 8) 1925 }; 1926 static uint32_t BCMI_FALCON_XGXS_SIGDET_CTL1r_fields[] = 1927 { 1928 /* AFE_SIGNAL_DETECT_DIS:0:0 */ 1929 PHYMOD_SYMBOL_FIELD_ENCODE(9, 0, 0), 1930 /* EXT_LOS_EN:1:1 */ 1931 PHYMOD_SYMBOL_FIELD_ENCODE(318, 1, 1), 1932 /* EXT_LOS_INV:2:2 */ 1933 PHYMOD_SYMBOL_FIELD_ENCODE(319, 2, 2), 1934 /* IGNORE_LP_MODE:3:3 */ 1935 PHYMOD_SYMBOL_FIELD_ENCODE(335, 3, 3), 1936 /* SIGNAL_DETECT_FILTER_1US:4:4 */ 1937 PHYMOD_SYMBOL_FIELD_ENCODE(697, 4, 4), 1938 /* ENERGY_DETECT_FRC:5:5 */ 1939 PHYMOD_SYMBOL_FIELD_ENCODE(315, 5, 5), 1940 /* ENERGY_DETECT_FRC_VAL:6:6 */ 1941 PHYMOD_SYMBOL_FIELD_ENCODE(316, 6, 6), 1942 /* SIGNAL_DETECT_FRC:7:7 */ 1943 PHYMOD_SYMBOL_FIELD_ENCODE(699, 7, 7), 1944 /* SIGNAL_DETECT_FRC_VAL:8:8 */ 1945 PHYMOD_SYMBOL_FIELD_ENCODE(700, 8, 8), 1946 /* ENERGY_DETECT_MASK_COUNT:11:15 */ 1947 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(317, 15, 11) 1948 }; 1949 static uint32_t BCMI_FALCON_XGXS_SIGDET_CTL2r_fields[] = 1950 { 1951 /* LOS_THRESH:0:2 */ 1952 PHYMOD_SYMBOL_FIELD_ENCODE(359, 2, 0), 1953 /* SIGNAL_DETECT_THRESH:4:6 */ 1954 PHYMOD_SYMBOL_FIELD_ENCODE(703, 6, 4), 1955 /* HOLD_LOS_COUNT:8:10 */ 1956 PHYMOD_SYMBOL_FIELD_ENCODE(331, 10, 8), 1957 /* HOLD_SD_COUNT:11:13 */ 1958 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(332, 13, 11) 1959 }; 1960 static uint32_t BCMI_FALCON_XGXS_SIGDET_STS0r_fields[] = 1961 { 1962 /* SIGNAL_DETECT:0:0 */ 1963 PHYMOD_SYMBOL_FIELD_ENCODE(695, 0, 0), 1964 /* SIGNAL_DETECT_CHANGE:1:1 */ 1965 PHYMOD_SYMBOL_FIELD_ENCODE(696, 1, 1), 1966 /* ENERGY_DETECT:2:2 */ 1967 PHYMOD_SYMBOL_FIELD_ENCODE(313, 2, 2), 1968 /* ENERGY_DETECT_CHANGE:3:3 */ 1969 PHYMOD_SYMBOL_FIELD_ENCODE(314, 3, 3), 1970 /* SIGNAL_DETECT_RAW:4:4 */ 1971 PHYMOD_SYMBOL_FIELD_ENCODE(701, 4, 4), 1972 /* SIGNAL_DETECT_RAW_CHANGE:5:5 */ 1973 PHYMOD_SYMBOL_FIELD_ENCODE(702, 5, 5), 1974 /* AFE_SIGDET_THRESH:8:10 */ 1975 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(8, 10, 8) 1976 }; 1977 static uint32_t BCMI_FALCON_XGXS_TLB_RX_DIG_LPBK_CFGr_fields[] = 1978 { 1979 /* DIG_LPBK_EN:0:0 */ 1980 PHYMOD_SYMBOL_FIELD_ENCODE(287, 0, 0), 1981 /* DIG_LPBK_PD_MODE:1:1 */ 1982 PHYMOD_SYMBOL_FIELD_ENCODE(291, 1, 1), 1983 /* DIG_LPBK_PD_BIAS_EN:3:3 */ 1984 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(288, 3, 3) 1985 }; 1986 static uint32_t BCMI_FALCON_XGXS_TLB_RX_DIG_LPBK_PD_STSr_fields[] = 1987 { 1988 /* DIG_LPBK_PD_LATE_IND:0:0 */ 1989 PHYMOD_SYMBOL_FIELD_ENCODE(290, 0, 0), 1990 /* DIG_LPBK_PD_EARLY_IND:1:1 */ 1991 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(289, 1, 1) 1992 }; 1993 static uint32_t BCMI_FALCON_XGXS_TLB_RX_MAX_PRBS_BURST_ERR_LEN_STSr_fields[] = 1994 { 1995 /* MAX_PRBS_BURST_ERR_LENGTH_STATUS:0:5 */ 1996 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(360, 5, 0) 1997 }; 1998 static uint32_t BCMI_FALCON_XGXS_TLB_RX_MISC_CFGr_fields[] = 1999 { 2000 /* RX_PMD_DP_INVERT:0:0 */ 2001 PHYMOD_SYMBOL_FIELD_ENCODE(687, 0, 0), 2002 /* DBG_MASK_DIG_LPBK_EN:2:2 */ 2003 PHYMOD_SYMBOL_FIELD_ENCODE(273, 2, 2), 2004 /* TLB_RX_DIFF_DEC_EN:3:3 */ 2005 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(717, 3, 3) 2006 }; 2007 static uint32_t BCMI_FALCON_XGXS_TLB_RX_PMD_RX_LOCK_STSr_fields[] = 2008 { 2009 /* PMD_RX_LOCK:0:0 */ 2010 PHYMOD_SYMBOL_FIELD_ENCODE(496, 0, 0), 2011 /* PMD_RX_LOCK_CHANGE:1:1 */ 2012 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(497, 1, 1) 2013 }; 2014 static uint32_t BCMI_FALCON_XGXS_TLB_RX_PRBS_BURST_ERR_LEN_STSr_fields[] = 2015 { 2016 /* PRBS_BURST_ERR_LENGTH_STATUS:0:5 */ 2017 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(501, 5, 0) 2018 }; 2019 static uint32_t BCMI_FALCON_XGXS_TLB_RX_PRBS_CHK_CFGr_fields[] = 2020 { 2021 /* PRBS_CHK_EN:0:0 */ 2022 PHYMOD_SYMBOL_FIELD_ENCODE(504, 0, 0), 2023 /* PRBS_CHK_MODE_SEL:1:3 */ 2024 PHYMOD_SYMBOL_FIELD_ENCODE(516, 3, 1), 2025 /* PRBS_CHK_INV:4:4 */ 2026 PHYMOD_SYMBOL_FIELD_ENCODE(511, 4, 4), 2027 /* PRBS_CHK_MODE:5:6 */ 2028 PHYMOD_SYMBOL_FIELD_ENCODE(515, 6, 5), 2029 /* PRBS_CHK_EN_AUTO_MODE:7:7 */ 2030 PHYMOD_SYMBOL_FIELD_ENCODE(505, 7, 7), 2031 /* PRBS_BURST_LEN_CHK_EN:8:8 */ 2032 PHYMOD_SYMBOL_FIELD_ENCODE(502, 8, 8), 2033 /* PRBS_CHK_ERR_CNT_BURST_MODE:9:9 */ 2034 PHYMOD_SYMBOL_FIELD_ENCODE(508, 9, 9), 2035 /* TRNSUM_ERROR_COUNT_EN:10:10 */ 2036 PHYMOD_SYMBOL_FIELD_ENCODE(733, 10, 10), 2037 /* PRBS_CHK_CLK_EN_FRC_ON:11:11 */ 2038 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(503, 11, 11) 2039 }; 2040 static uint32_t BCMI_FALCON_XGXS_TLB_RX_PRBS_CHK_CNT_CFGr_fields[] = 2041 { 2042 /* PRBS_CHK_LOCK_CNT:0:4 */ 2043 PHYMOD_SYMBOL_FIELD_ENCODE(513, 4, 0), 2044 /* PRBS_CHK_OOL_CNT:8:12 */ 2045 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(517, 12, 8) 2046 }; 2047 static uint32_t BCMI_FALCON_XGXS_TLB_RX_PRBS_CHK_EN_TMR_CTLr_fields[] = 2048 { 2049 /* PRBS_CHK_EN_TIMER_MODE:0:1 */ 2050 PHYMOD_SYMBOL_FIELD_ENCODE(507, 1, 0), 2051 /* PRBS_CHK_EN_TIMEOUT:8:12 */ 2052 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(506, 12, 8) 2053 }; 2054 static uint32_t BCMI_FALCON_XGXS_TLB_RX_PRBS_CHK_ERR_CNT_LSB_STSr_fields[] = 2055 { 2056 /* PRBS_CHK_ERR_CNT_LSB:0:15 */ 2057 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(509, 15, 0) 2058 }; 2059 static uint32_t BCMI_FALCON_XGXS_TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr_fields[] = 2060 { 2061 /* PRBS_CHK_ERR_CNT_MSB:0:14 */ 2062 PHYMOD_SYMBOL_FIELD_ENCODE(510, 14, 0), 2063 /* PRBS_CHK_LOCK_LOST_LH:15:15 */ 2064 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(514, 15, 15) 2065 }; 2066 static uint32_t BCMI_FALCON_XGXS_TLB_RX_PRBS_CHK_LOCK_STSr_fields[] = 2067 { 2068 /* PRBS_CHK_LOCK:0:0 */ 2069 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(512, 0, 0) 2070 }; 2071 static uint32_t BCMI_FALCON_XGXS_TLB_TX_MISC_CFGr_fields[] = 2072 { 2073 /* TX_PMD_DP_INVERT:0:0 */ 2074 PHYMOD_SYMBOL_FIELD_ENCODE(809, 0, 0), 2075 /* TX_PCS_NATIVE_ANA_FRMT_EN:1:1 */ 2076 PHYMOD_SYMBOL_FIELD_ENCODE(778, 1, 1), 2077 /* TX_MUX_SEL_ORDER:2:2 */ 2078 PHYMOD_SYMBOL_FIELD_ENCODE(777, 2, 2), 2079 /* TLB_TX_DIFF_ENC_EN:3:3 */ 2080 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(718, 3, 3) 2081 }; 2082 static uint32_t BCMI_FALCON_XGXS_TLB_TX_PATT_GEN_CFGr_fields[] = 2083 { 2084 /* PATT_GEN_EN:0:0 */ 2085 PHYMOD_SYMBOL_FIELD_ENCODE(448, 0, 0), 2086 /* PATT_GEN_STOP_POS:8:11 */ 2087 PHYMOD_SYMBOL_FIELD_ENCODE(465, 11, 8), 2088 /* PATT_GEN_START_POS:12:15 */ 2089 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(464, 15, 12) 2090 }; 2091 static uint32_t BCMI_FALCON_XGXS_TLB_TX_PRBS_GEN_CFGr_fields[] = 2092 { 2093 /* PRBS_GEN_EN:0:0 */ 2094 PHYMOD_SYMBOL_FIELD_ENCODE(518, 0, 0), 2095 /* PRBS_GEN_MODE_SEL:1:3 */ 2096 PHYMOD_SYMBOL_FIELD_ENCODE(521, 3, 1), 2097 /* PRBS_GEN_INV:4:4 */ 2098 PHYMOD_SYMBOL_FIELD_ENCODE(520, 4, 4), 2099 /* PRBS_GEN_ERR_INS:5:5 */ 2100 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(519, 5, 5) 2101 }; 2102 static uint32_t BCMI_FALCON_XGXS_TLB_TX_RMT_LPBK_CFGr_fields[] = 2103 { 2104 /* RMT_LPBK_EN:0:0 */ 2105 PHYMOD_SYMBOL_FIELD_ENCODE(551, 0, 0), 2106 /* RMT_LPBK_PD_MODE:1:1 */ 2107 PHYMOD_SYMBOL_FIELD_ENCODE(555, 1, 1), 2108 /* RMT_LPBK_PD_FRC_ON:2:2 */ 2109 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(553, 2, 2) 2110 }; 2111 static uint32_t BCMI_FALCON_XGXS_TLB_TX_RMT_LPBK_PD_STSr_fields[] = 2112 { 2113 /* RMT_LPBK_PD_LATE_IND:0:0 */ 2114 PHYMOD_SYMBOL_FIELD_ENCODE(554, 0, 0), 2115 /* RMT_LPBK_PD_EARLY_IND:1:1 */ 2116 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(552, 1, 1) 2117 }; 2118 static uint32_t BCMI_FALCON_XGXS_TXFIR_CTL0r_fields[] = 2119 { 2120 /* TXFIR_PRE_OFFSET:0:3 */ 2121 PHYMOD_SYMBOL_FIELD_ENCODE(768, 3, 0), 2122 /* TXFIR_MAIN_OFFSET:4:7 */ 2123 PHYMOD_SYMBOL_FIELD_ENCODE(756, 7, 4), 2124 /* TXFIR_POST_OFFSET:8:11 */ 2125 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(765, 11, 8) 2126 }; 2127 static uint32_t BCMI_FALCON_XGXS_TXFIR_CTL1r_fields[] = 2128 { 2129 /* TXFIR_POST2:0:4 */ 2130 PHYMOD_SYMBOL_FIELD_ENCODE(757, 4, 0), 2131 /* TXFIR_POST2_OFFSET:8:11 */ 2132 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(759, 11, 8) 2133 }; 2134 static uint32_t BCMI_FALCON_XGXS_TXFIR_CTL2r_fields[] = 2135 { 2136 /* TXFIR_POST3:0:3 */ 2137 PHYMOD_SYMBOL_FIELD_ENCODE(760, 3, 0), 2138 /* TXFIR_POST3_OFFSET:8:11 */ 2139 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(762, 11, 8) 2140 }; 2141 static uint32_t BCMI_FALCON_XGXS_TXFIR_MISC_CTL1r_fields[] = 2142 { 2143 /* SDK_TX_DISABLE:0:0 */ 2144 PHYMOD_SYMBOL_FIELD_ENCODE(692, 0, 0), 2145 /* PMD_TX_DISABLE_PIN_DIS:1:1 */ 2146 PHYMOD_SYMBOL_FIELD_ENCODE(500, 1, 1), 2147 /* TX_DISABLE_TIMER_CTRL:2:7 */ 2148 PHYMOD_SYMBOL_FIELD_ENCODE(770, 7, 2), 2149 /* TX_EEE_QUIET_EN:8:8 */ 2150 PHYMOD_SYMBOL_FIELD_ENCODE(772, 8, 8), 2151 /* TX_EEE_ALERT_EN:9:9 */ 2152 PHYMOD_SYMBOL_FIELD_ENCODE(771, 9, 9), 2153 /* TX_DISABLE_OUTPUT_SEL:10:11 */ 2154 PHYMOD_SYMBOL_FIELD_ENCODE(769, 11, 10), 2155 /* DP_RESET_TX_DISABLE_DIS:12:12 */ 2156 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(292, 12, 12) 2157 }; 2158 static uint32_t BCMI_FALCON_XGXS_TXFIR_STS0r_fields[] = 2159 { 2160 /* TXFIR_PRE_AFTER_OVR:0:4 */ 2161 PHYMOD_SYMBOL_FIELD_ENCODE(767, 4, 0), 2162 /* TXFIR_POST_AFTER_OVR:8:13 */ 2163 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(764, 13, 8) 2164 }; 2165 static uint32_t BCMI_FALCON_XGXS_TXFIR_STS1r_fields[] = 2166 { 2167 /* TXFIR_MAIN_AFTER_OVR:0:6 */ 2168 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(755, 6, 0) 2169 }; 2170 static uint32_t BCMI_FALCON_XGXS_TXFIR_STS2r_fields[] = 2171 { 2172 /* TXFIR_PRE_ADJUSTED:0:4 */ 2173 PHYMOD_SYMBOL_FIELD_ENCODE(766, 4, 0), 2174 /* TXFIR_POST_ADJUSTED:8:13 */ 2175 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(763, 13, 8) 2176 }; 2177 static uint32_t BCMI_FALCON_XGXS_TXFIR_STS3r_fields[] = 2178 { 2179 /* TXFIR_MAIN_ADJUSTED:0:6 */ 2180 PHYMOD_SYMBOL_FIELD_ENCODE(754, 6, 0), 2181 /* TXFIR_POST2_ADJUSTED:8:12 */ 2182 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(758, 12, 8) 2183 }; 2184 static uint32_t BCMI_FALCON_XGXS_TXFIR_STS4r_fields[] = 2185 { 2186 /* TXFIR_POST3_ADJUSTED:0:3 */ 2187 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(761, 3, 0) 2188 }; 2189 static uint32_t BCMI_FALCON_XGXS_TXFIR_UC_CTL0r_fields[] = 2190 { 2191 /* MICRO_TX_DISABLE:0:0 */ 2192 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(441, 0, 0) 2193 }; 2194 static uint32_t BCMI_FALCON_XGXS_TX_CTL0r_fields[] = 2195 { 2196 /* TXCOM_POST_TAP_ALERT_VAL:0:5 */ 2197 PHYMOD_SYMBOL_FIELD_ENCODE(752, 5, 0), 2198 /* TXCOM_PRE_TAP_ALERT_VAL:8:12 */ 2199 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(753, 12, 8) 2200 }; 2201 static uint32_t BCMI_FALCON_XGXS_TX_CTL1r_fields[] = 2202 { 2203 /* TXCOM_MAIN_TAP_ALERT_VAL:0:6 */ 2204 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(751, 6, 0) 2205 }; 2206 static uint32_t BCMI_FALCON_XGXS_TX_CTL2r_fields[] = 2207 { 2208 /* TXCOM_CL93N72_MAX_WAIT_TIMER_PERIOD:0:15 */ 2209 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(749, 15, 0) 2210 }; 2211 static uint32_t BCMI_FALCON_XGXS_TX_CTL3r_fields[] = 2212 { 2213 /* TXCOM_CL93N72_WAIT_CNTR_LIMIT:0:8 */ 2214 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(750, 8, 0) 2215 }; 2216 static uint32_t BCMI_FALCON_XGXS_TX_PI_PMD_CTL0r_fields[] = 2217 { 2218 /* TX_PI_EN:0:0 */ 2219 PHYMOD_SYMBOL_FIELD_ENCODE(779, 0, 0), 2220 /* TX_PI_JITTER_FILTER_EN:1:1 */ 2221 PHYMOD_SYMBOL_FIELD_ENCODE(790, 1, 1), 2222 /* TX_PI_EXT_CTRL_EN:2:2 */ 2223 PHYMOD_SYMBOL_FIELD_ENCODE(780, 2, 2), 2224 /* TX_PI_FREQ_OVERRIDE_EN:3:3 */ 2225 PHYMOD_SYMBOL_FIELD_ENCODE(783, 3, 3), 2226 /* TX_PI_SJ_GEN_EN:4:4 */ 2227 PHYMOD_SYMBOL_FIELD_ENCODE(807, 4, 4), 2228 /* TX_PI_SSC_GEN_EN:5:5 */ 2229 PHYMOD_SYMBOL_FIELD_ENCODE(808, 5, 5), 2230 /* TX_PI_JIT_SSC_FREQ_MODE:6:6 */ 2231 PHYMOD_SYMBOL_FIELD_ENCODE(793, 6, 6), 2232 /* TX_PI_SECOND_ORDER_LOOP_EN:7:7 */ 2233 PHYMOD_SYMBOL_FIELD_ENCODE(806, 7, 7), 2234 /* TX_PI_FIRST_ORDER_BWSEL_INTEG:8:9 */ 2235 PHYMOD_SYMBOL_FIELD_ENCODE(782, 9, 8), 2236 /* TX_PI_SECOND_ORDER_BWSEL_INTEG:10:11 */ 2237 PHYMOD_SYMBOL_FIELD_ENCODE(805, 11, 10), 2238 /* TX_PI_EXT_PHASE_BWSEL_INTEG:12:14 */ 2239 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(781, 14, 12) 2240 }; 2241 static uint32_t BCMI_FALCON_XGXS_TX_PI_PMD_CTL1r_fields[] = 2242 { 2243 /* TX_PI_FREQ_OVERRIDE_VAL:0:14 */ 2244 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(784, 14, 0) 2245 }; 2246 static uint32_t BCMI_FALCON_XGXS_TX_PI_PMD_CTL2r_fields[] = 2247 { 2248 /* TX_PI_JIT_FREQ_IDX:0:5 */ 2249 PHYMOD_SYMBOL_FIELD_ENCODE(792, 5, 0), 2250 /* TX_PI_JIT_AMP:8:13 */ 2251 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(791, 13, 8) 2252 }; 2253 static uint32_t BCMI_FALCON_XGXS_TX_PI_PMD_CTL3r_fields[] = 2254 { 2255 /* TX_PI_PHASE_OVERRIDE:0:0 */ 2256 PHYMOD_SYMBOL_FIELD_ENCODE(799, 0, 0), 2257 /* TX_PI_PHASE_STROBE:1:1 */ 2258 PHYMOD_SYMBOL_FIELD_ENCODE(802, 1, 1), 2259 /* TX_PI_PHASE_STEP_DIR:2:2 */ 2260 PHYMOD_SYMBOL_FIELD_ENCODE(800, 2, 2), 2261 /* TX_PI_PHASE_INVERT:4:4 */ 2262 PHYMOD_SYMBOL_FIELD_ENCODE(798, 4, 4), 2263 /* TX_PI_PHASE_STEP_NUM:8:11 */ 2264 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(801, 11, 8) 2265 }; 2266 static uint32_t BCMI_FALCON_XGXS_TX_PI_PMD_CTL4r_fields[] = 2267 { 2268 /* TX_PI_FRZ_FRC:0:0 */ 2269 PHYMOD_SYMBOL_FIELD_ENCODE(785, 0, 0), 2270 /* TX_PI_FRZ_FRC_VAL:1:1 */ 2271 PHYMOD_SYMBOL_FIELD_ENCODE(786, 1, 1), 2272 /* TX_PI_FRZ_MODE:2:2 */ 2273 PHYMOD_SYMBOL_FIELD_ENCODE(787, 2, 2), 2274 /* TX_PI_RESET_CODE_DBG:3:3 */ 2275 PHYMOD_SYMBOL_FIELD_ENCODE(803, 3, 3), 2276 /* TX_PI_RMT_LPBK_BYPASS_FLT:4:4 */ 2277 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(804, 4, 4) 2278 }; 2279 static uint32_t BCMI_FALCON_XGXS_TX_PI_PMD_STS0r_fields[] = 2280 { 2281 /* TX_PI_PHASE_CNTR:0:6 */ 2282 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(796, 6, 0) 2283 }; 2284 static uint32_t BCMI_FALCON_XGXS_TX_PI_PMD_STS1r_fields[] = 2285 { 2286 /* TX_PI_INTEG1_REG:0:13 */ 2287 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(788, 13, 0) 2288 }; 2289 static uint32_t BCMI_FALCON_XGXS_TX_PI_PMD_STS2r_fields[] = 2290 { 2291 /* TX_PI_INTEG2_REG:0:14 */ 2292 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(789, 14, 0) 2293 }; 2294 static uint32_t BCMI_FALCON_XGXS_TX_PI_PMD_STS3r_fields[] = 2295 { 2296 /* TX_PI_PHASE_ERR:0:5 */ 2297 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(797, 5, 0) 2298 }; 2299 static uint32_t BCMI_FALCON_XGXS_UC_AHB_CTL0r_fields[] = 2300 { 2301 /* MICRO_RA_WRDATASIZE:0:1 */ 2302 PHYMOD_SYMBOL_FIELD_ENCODE(418, 1, 0), 2303 /* MICRO_RA_RDDATASIZE:4:5 */ 2304 PHYMOD_SYMBOL_FIELD_ENCODE(413, 5, 4), 2305 /* MICRO_RA_INIT:8:9 */ 2306 PHYMOD_SYMBOL_FIELD_ENCODE(409, 9, 8), 2307 /* MICRO_AUTOINC_WRADDR_EN:12:12 */ 2308 PHYMOD_SYMBOL_FIELD_ENCODE(380, 12, 12), 2309 /* MICRO_AUTOINC_RDADDR_EN:13:13 */ 2310 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(379, 13, 13) 2311 }; 2312 static uint32_t BCMI_FALCON_XGXS_UC_AHB_RDADDR_LSWr_fields[] = 2313 { 2314 /* MICRO_RA_RDADDR_LSW:0:15 */ 2315 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(411, 15, 0) 2316 }; 2317 static uint32_t BCMI_FALCON_XGXS_UC_AHB_RDADDR_MSWr_fields[] = 2318 { 2319 /* MICRO_RA_RDADDR_MSW:0:15 */ 2320 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(412, 15, 0) 2321 }; 2322 static uint32_t BCMI_FALCON_XGXS_UC_AHB_RDDATA_LSWr_fields[] = 2323 { 2324 /* MICRO_RA_RDDATA_LSW:0:15 */ 2325 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(414, 15, 0) 2326 }; 2327 static uint32_t BCMI_FALCON_XGXS_UC_AHB_RDDATA_MSWr_fields[] = 2328 { 2329 /* MICRO_RA_RDDATA_MSW:0:15 */ 2330 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(415, 15, 0) 2331 }; 2332 static uint32_t BCMI_FALCON_XGXS_UC_AHB_STS0r_fields[] = 2333 { 2334 /* MICRO_RA_INITDONE:0:0 */ 2335 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(410, 0, 0) 2336 }; 2337 static uint32_t BCMI_FALCON_XGXS_UC_AHB_WRADDR_LSWr_fields[] = 2338 { 2339 /* MICRO_RA_WRADDR_LSW:0:15 */ 2340 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(416, 15, 0) 2341 }; 2342 static uint32_t BCMI_FALCON_XGXS_UC_AHB_WRADDR_MSWr_fields[] = 2343 { 2344 /* MICRO_RA_WRADDR_MSW:0:15 */ 2345 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(417, 15, 0) 2346 }; 2347 static uint32_t BCMI_FALCON_XGXS_UC_AHB_WRDATA_LSWr_fields[] = 2348 { 2349 /* MICRO_RA_WRDATA_LSW:0:15 */ 2350 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(419, 15, 0) 2351 }; 2352 static uint32_t BCMI_FALCON_XGXS_UC_AHB_WRDATA_MSWr_fields[] = 2353 { 2354 /* MICRO_RA_WRDATA_MSW:0:15 */ 2355 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(420, 15, 0) 2356 }; 2357 static uint32_t BCMI_FALCON_XGXS_UC_CLK_CTL0r_fields[] = 2358 { 2359 /* MICRO_MASTER_CLK_EN:0:0 */ 2360 PHYMOD_SYMBOL_FIELD_ENCODE(394, 0, 0), 2361 /* MICRO_CORE_CLK_EN:1:1 */ 2362 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(383, 1, 1) 2363 }; 2364 static uint32_t BCMI_FALCON_XGXS_UC_CODE_RAM_ECCCONTRO1r_fields[] = 2365 { 2366 /* MICRO_RA_ECC_WRDATA:0:6 */ 2367 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(408, 6, 0) 2368 }; 2369 static uint32_t BCMI_FALCON_XGXS_UC_CODE_RAM_ECCCTL0r_fields[] = 2370 { 2371 /* MICRO_ECCG_MODE:0:0 */ 2372 PHYMOD_SYMBOL_FIELD_ENCODE(387, 0, 0), 2373 /* MICRO_ECC_FRC_DISABLE:1:1 */ 2374 PHYMOD_SYMBOL_FIELD_ENCODE(389, 1, 1), 2375 /* MICRO_ECC_CORRUPT:4:5 */ 2376 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(388, 5, 4) 2377 }; 2378 static uint32_t BCMI_FALCON_XGXS_UC_CODE_RAM_ECCSTS0r_fields[] = 2379 { 2380 /* MICRO_CODE_RAM_ECC_ADDRESS:0:14 */ 2381 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(381, 14, 0) 2382 }; 2383 static uint32_t BCMI_FALCON_XGXS_UC_CODE_RAM_ECCSTS1r_fields[] = 2384 { 2385 /* MICRO_RA_ECC_RDDATA:0:6 */ 2386 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(407, 6, 0) 2387 }; 2388 static uint32_t BCMI_FALCON_XGXS_UC_CODE_RAM_TESTIFCTL0r_fields[] = 2389 { 2390 /* MICRO_CODE_RAM_TM:0:13 */ 2391 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(382, 13, 0) 2392 }; 2393 static uint32_t BCMI_FALCON_XGXS_UC_PRAMIF_AHB_WRADDR_LSWr_fields[] = 2394 { 2395 /* MICRO_PRAMIF_AHB_WRADDR_LSW:2:15 */ 2396 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(396, 15, 2) 2397 }; 2398 static uint32_t BCMI_FALCON_XGXS_UC_PRAMIF_AHB_WRADDR_MSWr_fields[] = 2399 { 2400 /* MICRO_PRAMIF_AHB_WRADDR_MSW:0:15 */ 2401 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(397, 15, 0) 2402 }; 2403 static uint32_t BCMI_FALCON_XGXS_UC_PRAMIF_CTL0r_fields[] = 2404 { 2405 /* MICRO_PRAMIF_EN:0:0 */ 2406 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(398, 0, 0) 2407 }; 2408 static uint32_t BCMI_FALCON_XGXS_UC_PVT_STS0r_fields[] = 2409 { 2410 /* MICRO_PVT_TEMPDATA_RMI:0:9 */ 2411 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(404, 9, 0) 2412 }; 2413 static uint32_t BCMI_FALCON_XGXS_UC_RAM_CTL0r_fields[] = 2414 { 2415 /* MICRO_DR_LOOKTAB_EN:0:0 */ 2416 PHYMOD_SYMBOL_FIELD_ENCODE(385, 0, 0), 2417 /* MICRO_DR_SIZE:8:13 */ 2418 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(386, 13, 8) 2419 }; 2420 static uint32_t BCMI_FALCON_XGXS_UC_RMI_AHB_CTL1r_fields[] = 2421 { 2422 /* MICRO_M0_HRESP_EN:0:0 */ 2423 PHYMOD_SYMBOL_FIELD_ENCODE(393, 0, 0), 2424 /* MICRO_SW_PMI_HP_RSTB:1:1 */ 2425 PHYMOD_SYMBOL_FIELD_ENCODE(438, 1, 1), 2426 /* MICRO_SW_PMI_HP_EXT_RSTB:2:2 */ 2427 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(437, 2, 2) 2428 }; 2429 static uint32_t BCMI_FALCON_XGXS_UC_RMI_AHB_STS1r_fields[] = 2430 { 2431 /* MICRO_M0_DEFAULT_SLAVE_ERROR:0:0 */ 2432 PHYMOD_SYMBOL_FIELD_ENCODE(392, 0, 0), 2433 /* MICRO_RMI_DEFAULT_SLAVE_ERROR:1:1 */ 2434 PHYMOD_SYMBOL_FIELD_ENCODE(421, 1, 1), 2435 /* MICRO_PR_DEFAULT_SLAVE_ERROR:2:2 */ 2436 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(401, 2, 2) 2437 }; 2438 static uint32_t BCMI_FALCON_XGXS_UC_RMI_EXT_INTR_CTL0r_fields[] = 2439 { 2440 /* MICRO_RMI_MBOX_MSGOUT_INTR_EN:0:0 */ 2441 PHYMOD_SYMBOL_FIELD_ENCODE(432, 0, 0), 2442 /* MICRO_RMI_ECC_CORR_ERR_INTR_EN:4:4 */ 2443 PHYMOD_SYMBOL_FIELD_ENCODE(422, 4, 4), 2444 /* MICRO_RMI_ECC_UNCORR_ERR_INTR_EN:5:5 */ 2445 PHYMOD_SYMBOL_FIELD_ENCODE(426, 5, 5), 2446 /* MICRO_RMI_ECC_MULTIROW_ERR_INTR_EN:6:6 */ 2447 PHYMOD_SYMBOL_FIELD_ENCODE(424, 6, 6), 2448 /* MICRO_RMI_M0_LOCKUP_INTR_EN:8:8 */ 2449 PHYMOD_SYMBOL_FIELD_ENCODE(428, 8, 8), 2450 /* MICRO_RMI_M0_SYSTEMRESETREQ_INTR_EN:9:9 */ 2451 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(430, 9, 9) 2452 }; 2453 static uint32_t BCMI_FALCON_XGXS_UC_RMI_EXT_INTR_STS0r_fields[] = 2454 { 2455 /* MICRO_RMI_MBOX_MSGOUT_STATUS:0:0 */ 2456 PHYMOD_SYMBOL_FIELD_ENCODE(433, 0, 0), 2457 /* MICRO_RMI_ECC_CORR_ERR_STATUS:4:4 */ 2458 PHYMOD_SYMBOL_FIELD_ENCODE(423, 4, 4), 2459 /* MICRO_RMI_ECC_UNCORR_ERR_STATUS:5:5 */ 2460 PHYMOD_SYMBOL_FIELD_ENCODE(427, 5, 5), 2461 /* MICRO_RMI_ECC_MULTIROW_ERR_STATUS:6:6 */ 2462 PHYMOD_SYMBOL_FIELD_ENCODE(425, 6, 6), 2463 /* MICRO_RMI_M0_LOCKUP_STATUS:8:8 */ 2464 PHYMOD_SYMBOL_FIELD_ENCODE(429, 8, 8), 2465 /* MICRO_RMI_M0_SYSTEMRESETREQ_STATUS:9:9 */ 2466 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(431, 9, 9) 2467 }; 2468 static uint32_t BCMI_FALCON_XGXS_UC_RMI_MBOX_CTL0r_fields[] = 2469 { 2470 /* MICRO_RMI_MBOX_SEND_MSGIN:0:0 */ 2471 PHYMOD_SYMBOL_FIELD_ENCODE(434, 0, 0), 2472 /* MICRO_GEN_INTR_RMI_MBOX0WR:1:1 */ 2473 PHYMOD_SYMBOL_FIELD_ENCODE(390, 1, 1), 2474 /* MICRO_GEN_INTR_RMI_MBOX1WR:2:2 */ 2475 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(391, 2, 2) 2476 }; 2477 static uint32_t BCMI_FALCON_XGXS_UC_RMI_PR_AINC_NXT_WRADDR_LSWr_fields[] = 2478 { 2479 /* MICRO_PR_AUTOINC_NXT_WRADDR_LSW:0:15 */ 2480 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(400, 15, 0) 2481 }; 2482 static uint32_t BCMI_FALCON_XGXS_UC_RMI_PVT_CTL0r_fields[] = 2483 { 2484 /* MICRO_PVT_TEMPDATA_FRCVAL:0:9 */ 2485 PHYMOD_SYMBOL_FIELD_ENCODE(403, 9, 0), 2486 /* MICRO_PVT_TEMPDATA_FRC:12:12 */ 2487 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(402, 12, 12) 2488 }; 2489 static uint32_t BCMI_FALCON_XGXS_UC_RMI_RA_AINC_NXT_RDADDR_LSWr_fields[] = 2490 { 2491 /* MICRO_RA_AUTOINC_NXT_RDADDR_LSW:0:15 */ 2492 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(405, 15, 0) 2493 }; 2494 static uint32_t BCMI_FALCON_XGXS_UC_RMI_RA_AINC_NXT_WRADDR_LSWr_fields[] = 2495 { 2496 /* MICRO_RA_AUTOINC_NXT_WRADDR_LSW:0:15 */ 2497 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(406, 15, 0) 2498 }; 2499 static uint32_t BCMI_FALCON_XGXS_UC_RMI_TO_UC_MBOX0r_fields[] = 2500 { 2501 /* MICRO_RMI_TO_MICRO_MBOX0:0:15 */ 2502 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(435, 15, 0) 2503 }; 2504 static uint32_t BCMI_FALCON_XGXS_UC_RMI_TO_UC_MBOX1r_fields[] = 2505 { 2506 /* MICRO_RMI_TO_MICRO_MBOX1:0:15 */ 2507 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(436, 15, 0) 2508 }; 2509 static uint32_t BCMI_FALCON_XGXS_UC_RST_CTL0r_fields[] = 2510 { 2511 /* MICRO_MASTER_RSTB:0:0 */ 2512 PHYMOD_SYMBOL_FIELD_ENCODE(395, 0, 0), 2513 /* MICRO_CORE_RSTB:1:1 */ 2514 PHYMOD_SYMBOL_FIELD_ENCODE(384, 1, 1), 2515 /* MICRO_PRAM_IF_RSTB:3:3 */ 2516 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(399, 3, 3) 2517 }; 2518 static uint32_t BCMI_FALCON_XGXS_UC_UC_TO_RMI_MBOX0r_fields[] = 2519 { 2520 /* MICRO_TO_RMI_MBOX0:0:15 */ 2521 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(439, 15, 0) 2522 }; 2523 static uint32_t BCMI_FALCON_XGXS_UC_UC_TO_RMI_MBOX1r_fields[] = 2524 { 2525 /* MICRO_TO_RMI_MBOX1:0:15 */ 2526 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(440, 15, 0) 2527 }; 2528 2529 2530 2531 /******************************************************************************* 2532 * 2533 * The following is the field name table. 2534 */ 2535 #if PHYMOD_CONFIG_INCLUDE_FIELD_NAMES == 1 2536 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_NAMES_BCMI_FALCON_XGXS 2537 const char* bcmi_falcon_xgxs_fields[] = 2538 { 2539 "ACQ_CDR_TIMEOUT", 2540 "AFE_RX_PWRDN_FRC", 2541 "AFE_RX_PWRDN_FRC_VAL", 2542 "AFE_RX_RCLK20_PWRDN_FRC", 2543 "AFE_RX_RCLK20_PWRDN_FRC_VAL", 2544 "AFE_RX_RESET_FRC", 2545 "AFE_RX_RESET_FRC_VAL", 2546 "AFE_SIGDET_PWRDN", 2547 "AFE_SIGDET_THRESH", 2548 "AFE_SIGNAL_DETECT_DIS", 2549 "AFE_S_PLL_PWRDN", 2550 "AFE_S_PLL_RESET_FRC", 2551 "AFE_S_PLL_RESET_FRC_VAL", 2552 "AFE_TX_PWRDN_FRC", 2553 "AFE_TX_PWRDN_FRC_VAL", 2554 "AFE_TX_RESET_FRC", 2555 "AFE_TX_RESET_FRC_VAL", 2556 "AMS_PLL_BGINT", 2557 "AMS_PLL_BGIP", 2558 "AMS_PLL_BGR_CTATADJ", 2559 "AMS_PLL_BGR_PTATADJ", 2560 "AMS_PLL_CAL_AUX", 2561 "AMS_PLL_CAL_OFF", 2562 "AMS_PLL_COMP_VTH", 2563 "AMS_PLL_DRV_HV_DISABLE", 2564 "AMS_PLL_ENABLE_FTUNE", 2565 "AMS_PLL_EN_HRZ", 2566 "AMS_PLL_FORCE_KVH_BW", 2567 "AMS_PLL_FORCE_RESCAL", 2568 "AMS_PLL_IMAX_IBIAS", 2569 "AMS_PLL_IMAX_ICK", 2570 "AMS_PLL_IMAX_ICKGEN", 2571 "AMS_PLL_IMAX_ICLKIDRV1", 2572 "AMS_PLL_IMAX_ICLKINT", 2573 "AMS_PLL_IMAX_ICLKODRV1", 2574 "AMS_PLL_IMAX_ICMLDIV", 2575 "AMS_PLL_IMAX_ICOMP", 2576 "AMS_PLL_IMAX_ICP", 2577 "AMS_PLL_IMAX_IOP", 2578 "AMS_PLL_IMAX_IRXCLKBUF", 2579 "AMS_PLL_IMIN_IBIAS", 2580 "AMS_PLL_IMIN_ICK", 2581 "AMS_PLL_IMIN_ICKGEN", 2582 "AMS_PLL_IMIN_ICLKIDRV1", 2583 "AMS_PLL_IMIN_ICLKINT", 2584 "AMS_PLL_IMIN_ICLKODRV1", 2585 "AMS_PLL_IMIN_ICMLDIV", 2586 "AMS_PLL_IMIN_ICOMP", 2587 "AMS_PLL_IMIN_ICP", 2588 "AMS_PLL_IMIN_IOP", 2589 "AMS_PLL_IMIN_IRXCLKBUF", 2590 "AMS_PLL_IMODE_IBIAS", 2591 "AMS_PLL_IMODE_ICK", 2592 "AMS_PLL_IMODE_ICKGEN", 2593 "AMS_PLL_IMODE_ICLKIDRV1", 2594 "AMS_PLL_IMODE_ICLKINT", 2595 "AMS_PLL_IMODE_ICLKODRV1", 2596 "AMS_PLL_IMODE_ICMLDIV", 2597 "AMS_PLL_IMODE_ICOMP", 2598 "AMS_PLL_IMODE_ICP", 2599 "AMS_PLL_IMODE_IOP", 2600 "AMS_PLL_IMODE_IRXCLKBUF", 2601 "AMS_PLL_IQP", 2602 "AMS_PLL_IVCO", 2603 "AMS_PLL_KVH_FORCE", 2604 "AMS_PLL_MIX1P2CR_CTATADJ", 2605 "AMS_PLL_MIX1P2CR_PTATADJ", 2606 "AMS_PLL_MIX3P1CR_CTATADJ", 2607 "AMS_PLL_MIX3P1CR_PTATADJ", 2608 "AMS_PLL_MIX3P1C_CALR_CTATADJ", 2609 "AMS_PLL_MIX3P1C_CALR_PTATADJ", 2610 "AMS_PLL_PLL2RX_CLKBW", 2611 "AMS_PLL_REFH_PLL", 2612 "AMS_PLL_REFL_PLL", 2613 "AMS_PLL_RESET", 2614 "AMS_PLL_SET_CLK4TSC", 2615 "AMS_PLL_SPARE_101_96", 2616 "AMS_PLL_SPARE_117_112", 2617 "AMS_PLL_SPARE_23_22", 2618 "AMS_PLL_STS", 2619 "AMS_PLL_TEST_BG_OPAMP_BIAS", 2620 "AMS_PLL_TEST_PLL", 2621 "AMS_PLL_TEST_PNP", 2622 "AMS_PLL_TEST_PORT_MAX_AMPLITUDE", 2623 "AMS_PLL_TEST_RX", 2624 "AMS_PLL_TEST_VC", 2625 "AMS_PLL_TEST_VREF", 2626 "AMS_PLL_VBYPASS", 2627 "AMS_PLL_VCOICTRL", 2628 "AMS_PLL_VCO_INDICATOR", 2629 "AMS_PLL_VDDR_BGB", 2630 "AMS_RX_CLK_BW_CTRL", 2631 "AMS_RX_CM_VOLTAGE_IBIAS", 2632 "AMS_RX_D2C_CLKBUF_IBIAS", 2633 "AMS_RX_DAC4CK_DAT", 2634 "AMS_RX_DAC4CK_LMS", 2635 "AMS_RX_DAC4CK_PHS", 2636 "AMS_RX_DC_COUPLE", 2637 "AMS_RX_DC_OFFSET", 2638 "AMS_RX_DC_OFFSET_RANGE", 2639 "AMS_RX_DFE_HGAIN_EN", 2640 "AMS_RX_DFE_SLICER_CAL_IBIAS", 2641 "AMS_RX_DFE_SLICER_IBIAS", 2642 "AMS_RX_DFE_SUM_BUF_IBIAS", 2643 "AMS_RX_DFE_TAP_WEIGHT_IBIAS", 2644 "AMS_RX_DLL_IBIAS", 2645 "AMS_RX_EN_TAP9DELAY", 2646 "AMS_RX_EQ_LZ_EN", 2647 "AMS_RX_FORCE_DC_OFFSET", 2648 "AMS_RX_MASTER_DIODES_IBIAS", 2649 "AMS_RX_MET_R_IBIAS", 2650 "AMS_RX_OFFSET_CORRECTION_IBIAS", 2651 "AMS_RX_OFFSET_CORRECTION_RESCAL_MUX", 2652 "AMS_RX_PD_CH_P1", 2653 "AMS_RX_PEAKING_FILTER_IBIAS", 2654 "AMS_RX_PEAKING_FILTER_RESCAL_MUX", 2655 "AMS_RX_PHASE_INTERPOLATORS_IBIAS", 2656 "AMS_RX_PWRDN_FTAP", 2657 "AMS_RX_RX_OFFSET_PD", 2658 "AMS_RX_SEL_D2CLP", 2659 "AMS_RX_SEL_TH4DFE", 2660 "AMS_RX_SEL_UGBW", 2661 "AMS_RX_SHORT_VGA_OUTPUT", 2662 "AMS_RX_SIGDET_BYPASS", 2663 "AMS_RX_SIGDET_IBIAS", 2664 "AMS_RX_SIGDET_POWER_SAVE", 2665 "AMS_RX_SIGDET_PWRDN", 2666 "AMS_RX_SIGDET_THRESHOLD", 2667 "AMS_RX_SPARE_111_104", 2668 "AMS_RX_SPARE_123", 2669 "AMS_RX_SPARE_135_134", 2670 "AMS_RX_SPARE_143_142", 2671 "AMS_RX_SPARE_151_150", 2672 "AMS_RX_SPARE_159", 2673 "AMS_RX_SPARE_16", 2674 "AMS_RX_SPARE_63", 2675 "AMS_RX_SPARE_95", 2676 "AMS_RX_STS", 2677 "AMS_RX_TBD_IBIAS", 2678 "AMS_RX_TERMINATION_RESISTOR_RESCAL_MUX", 2679 "AMS_RX_TPORT_EN", 2680 "AMS_RX_VGA0_IBIAS", 2681 "AMS_RX_VGA0_RESCAL_MUX", 2682 "AMS_RX_VGA1_IBIAS", 2683 "AMS_RX_VGA1_RESCAL_MUX", 2684 "AMS_RX_VGA2_IBIAS", 2685 "AMS_RX_VGA2_RESCAL_MUX", 2686 "AMS_RX_VGA3_IBIAS", 2687 "AMS_RX_VGA3_RESCAL_MUX", 2688 "AMS_RX_VGA_10G_BW", 2689 "AMS_RX_VGA_LOW_GAIN", 2690 "AMS_RX_VGA_STEP_MODE", 2691 "AMS_TX_AMP_CTL", 2692 "AMS_TX_CAL_AUX", 2693 "AMS_TX_CAL_OFF", 2694 "AMS_TX_DCC_DIS", 2695 "AMS_TX_DCC_SEL", 2696 "AMS_TX_DRIVERMODE", 2697 "AMS_TX_ELEC_IDLE_AUX", 2698 "AMS_TX_IBIAS", 2699 "AMS_TX_ICML", 2700 "AMS_TX_ILDO", 2701 "AMS_TX_LDO_VREF", 2702 "AMS_TX_POST2_COEF", 2703 "AMS_TX_POST3_COEF", 2704 "AMS_TX_SEL_EMPH_MODE", 2705 "AMS_TX_SIGN_POST2", 2706 "AMS_TX_SIGN_POST3", 2707 "AMS_TX_SPARE_0", 2708 "AMS_TX_SPARE_21_19", 2709 "AMS_TX_SPARE_31", 2710 "AMS_TX_SPARE_3_1", 2711 "AMS_TX_SPARE_63_48", 2712 "AMS_TX_STS", 2713 "AMS_TX_TEST_DATA", 2714 "AMS_TX_TICKSEL", 2715 "AMS_TX_VDDR_BGB", 2716 "BR_PD_EN", 2717 "CAP_CNT_MASK_EN", 2718 "CAP_DONE", 2719 "CAP_DONE_LH_LL", 2720 "CAP_FORCE_SLOWDOWN", 2721 "CAP_FORCE_SLOWDOWN_EN", 2722 "CAP_PASS", 2723 "CAP_PASS_LH_LL", 2724 "CAP_RESTART", 2725 "CAP_RETRY_EN", 2726 "CAP_SELECT", 2727 "CAP_SELECT_M", 2728 "CAP_SELECT_M_EN", 2729 "CAP_SEQ_CYA", 2730 "CDR_1G_FORCE_EN", 2731 "CDR_1G_MANUAL_MODE", 2732 "CDR_1G_MANUAL_STROBE", 2733 "CDR_1G_PHASE_POINTER", 2734 "CDR_1G_SWAP_PZ", 2735 "CDR_1G_TRNSUM_EN", 2736 "CDR_BWSEL_INTEG_ACQCDR", 2737 "CDR_BWSEL_INTEG_EEE_ACQCDR", 2738 "CDR_BWSEL_INTEG_NORM", 2739 "CDR_BWSEL_PROP_ACQCDR", 2740 "CDR_BWSEL_PROP_EEE_ACQCDR", 2741 "CDR_BWSEL_PROP_NORM", 2742 "CDR_FREQ_EN", 2743 "CDR_FREQ_OVERRIDE_EN", 2744 "CDR_FREQ_OVERRIDE_VAL", 2745 "CDR_FRZ_FRC", 2746 "CDR_FRZ_FRC_VAL", 2747 "CDR_INTEG_REG", 2748 "CDR_INTEG_REG_CLR", 2749 "CDR_INTEG_SAT_SEL", 2750 "CDR_LM_OUTOFLOCK", 2751 "CDR_LM_THR_SEL", 2752 "CDR_PHASE_ERROR", 2753 "CDR_PHASE_ERR_FRZ", 2754 "CDR_SETTLE_TIMEOUT", 2755 "CDR_VCO_REG", 2756 "CDR_ZERO_POLARITY", 2757 "CL72_TIMER_EN", 2758 "CL93N72_BAD_MARKER_CNT", 2759 "CL93N72_BRK_RING_OSC", 2760 "CL93N72_CL93PRBSSEED_ORDER", 2761 "CL93N72_CL93PRBSSEED_RANDOM", 2762 "CL93N72_CTRL_FRAME_DLY", 2763 "CL93N72_DIS_MAX_WAIT_TIMER", 2764 "CL93N72_DME_CELL_BOUNDARY_CHK", 2765 "CL93N72_FRAME_CONSISTENCY_CHK_EN", 2766 "CL93N72_FRAME_LOCK", 2767 "CL93N72_GOOD_MARKER_CNT", 2768 "CL93N72_IEEE_FRAME_LOCK", 2769 "CL93N72_IEEE_LD_COEFF_UPDATE", 2770 "CL93N72_IEEE_LD_STATUS_REPORT", 2771 "CL93N72_IEEE_LP_COEFF_UPDATE", 2772 "CL93N72_IEEE_LP_STATUS_REPORT", 2773 "CL93N72_IEEE_RECEIVER_STATUS", 2774 "CL93N72_IEEE_RESTART_TRAINING", 2775 "CL93N72_IEEE_TRAINING_ENABLE", 2776 "CL93N72_IEEE_TRAINING_FAILURE", 2777 "CL93N72_IEEE_TRAINING_STATUS", 2778 "CL93N72_LD_XMT_STATUS_PAGE", 2779 "CL93N72_LOCAL_RX_READY", 2780 "CL93N72_MICRO_FRAME_LOCK_INT_EN", 2781 "CL93N72_MICRO_FRAME_LOCK_LSTATUS", 2782 "CL93N72_MICRO_STATUS_CHG_INT_EN", 2783 "CL93N72_MICRO_STATUS_CHG_LSTATUS", 2784 "CL93N72_MICRO_UPDATE_CHG_INT_EN", 2785 "CL93N72_MICRO_UPDATE_CHG_LSTATUS", 2786 "CL93N72_PPM_OFFSET_EN", 2787 "CL93N72_PRBS_SEL", 2788 "CL93N72_RX_DP_LN_CLK_EN", 2789 "CL93N72_RX_SIGNAL_OK", 2790 "CL93N72_RX_TRAINING_EN", 2791 "CL93N72_STRICT_DME_CHK", 2792 "CL93N72_STRICT_MARKER_CHK", 2793 "CL93N72_SW_FRAME_LOCK", 2794 "CL93N72_SW_REMOTE_RX_READY", 2795 "CL93N72_SW_RX_TRAINED", 2796 "CL93N72_TRAINING_FSM_SIGNAL_DETECT", 2797 "CL93N72_TR_COARSE_LOCK", 2798 "CL93N72_TXFIR_MAIN", 2799 "CL93N72_TXFIR_POST", 2800 "CL93N72_TXFIR_PRE", 2801 "CL93N72_TX_DP_LN_CLK_EN", 2802 "CL93N72_XMT_UPDATE_PAGE", 2803 "CORE_DP_RESET_STATE", 2804 "CORE_DP_S_RSTB", 2805 "CORE_MULTICAST_MASK_CONTROL", 2806 "CORE_REG_RESET_OCCURRED", 2807 "CORE_S_RSTB", 2808 "DATA_THRESH_SEL_VAL", 2809 "DATA_THRESH_WRITE", 2810 "DBG_CAP_STATE_ONE_HOT", 2811 "DBG_FDBCK", 2812 "DBG_MASK_DIG_LPBK_EN", 2813 "DBG_PLL_STATE_ONE_HOT", 2814 "DBG_SLOWDN", 2815 "DBG_SLOWDN_CHANGE", 2816 "DC_OFFSET_BIN", 2817 "DC_OFFS_ACC_CLR", 2818 "DC_OFFS_EN", 2819 "DC_OFFS_GAIN", 2820 "DC_OFFS_GRADIENT_INVERT", 2821 "DC_OFFS_HYS_EN", 2822 "DC_OFFS_HYS_MAG", 2823 "DC_OFFS_WRITE_EN", 2824 "DC_OFFS_WRITE_FRC_EN", 2825 "DC_OFFS_WRITE_VAL", 2826 "DIG_LPBK_EN", 2827 "DIG_LPBK_PD_BIAS_EN", 2828 "DIG_LPBK_PD_EARLY_IND", 2829 "DIG_LPBK_PD_LATE_IND", 2830 "DIG_LPBK_PD_MODE", 2831 "DP_RESET_TX_DISABLE_DIS", 2832 "DSC_CLR_FRC", 2833 "DSC_CLR_FRC_VAL", 2834 "DSC_SM_GP_UC_REQ", 2835 "DSC_SM_READY_FOR_CMD", 2836 "DSC_SM_SCRATCH", 2837 "DSC_STATE", 2838 "DSC_STATE_EEE_ONE_HOT", 2839 "DSC_STATE_ONE_HOT", 2840 "EEE_ACQ_CDR_TIMEOUT", 2841 "EEE_ANA_PWR_TIMEOUT", 2842 "EEE_CDR_SETTLE_TIMEOUT", 2843 "EEE_HW_TUNE_TIMEOUT", 2844 "EEE_LFSR_CNT", 2845 "EEE_MEASURE_CNT", 2846 "EEE_MEASURE_EN", 2847 "EEE_MODE_EN", 2848 "EEE_PHASE_ERR_OFFSET", 2849 "EEE_PHASE_ERR_OFFSET_EN", 2850 "EEE_QUIET_FROM_EEE_STATES", 2851 "EEE_QUIET_RX_AFE_PWRDWN_VAL", 2852 "ENERGY_DETECT", 2853 "ENERGY_DETECT_CHANGE", 2854 "ENERGY_DETECT_FRC", 2855 "ENERGY_DETECT_FRC_VAL", 2856 "ENERGY_DETECT_MASK_COUNT", 2857 "EXT_LOS_EN", 2858 "EXT_LOS_INV", 2859 "FAST_SEARCH_MODE", 2860 "FREQ_DET_RESTART_EN", 2861 "FREQ_DET_RETRY_EN", 2862 "FREQ_DONE_SM", 2863 "FREQ_DONE_SM_LH_LL", 2864 "FREQ_MONITOR_EN", 2865 "FREQ_PASS_SM", 2866 "FREQ_PASS_SM_LH_LL", 2867 "FREQ_UPD_EN_FRC", 2868 "FREQ_UPD_EN_FRC_VAL", 2869 "HEARTBEAT_COUNT_1US", 2870 "HOLD_LOS_COUNT", 2871 "HOLD_SD_COUNT", 2872 "HW_TUNE_EN", 2873 "HW_TUNE_TIMEOUT", 2874 "IGNORE_LP_MODE", 2875 "IGNORE_RX_MODE", 2876 "LANE_ADDR_0", 2877 "LANE_ADDR_1", 2878 "LANE_ADDR_2", 2879 "LANE_ADDR_3", 2880 "LANE_DP_RESET_STATE", 2881 "LANE_MULTICAST_MASK_CONTROL", 2882 "LANE_REG_RESET_OCCURRED", 2883 "LANE_RESET_RELEASED", 2884 "LANE_RESET_RELEASED_INDEX", 2885 "LN_DP_S_RSTB", 2886 "LN_RX_DP_S_RSTB", 2887 "LN_RX_S_CLKGATE_FRC_ON", 2888 "LN_RX_S_COMCLK_FRC_ON", 2889 "LN_RX_S_COMCLK_SEL", 2890 "LN_RX_S_PWRDN", 2891 "LN_RX_S_RSTB", 2892 "LN_S_RSTB", 2893 "LN_TX_DP_S_RSTB", 2894 "LN_TX_S_PWRDN", 2895 "LN_TX_S_RSTB", 2896 "LOST_PLL_LOCK_SM", 2897 "LOS_FILTER_COUNT", 2898 "LOS_THRESH", 2899 "MAX_PRBS_BURST_ERR_LENGTH_STATUS", 2900 "MDIO_ADDR_DATA", 2901 "MDIO_AER", 2902 "MDIO_BLK_ADDR", 2903 "MDIO_BRCST_PORT_ADDR", 2904 "MDIO_DEVAD", 2905 "MDIO_DEV_AN_EN", 2906 "MDIO_DEV_CL22_EN", 2907 "MDIO_DEV_DTE_EN", 2908 "MDIO_DEV_PCS_EN", 2909 "MDIO_DEV_PHY_EN", 2910 "MDIO_DEV_PMD_EN", 2911 "MDIO_FUNCTION", 2912 "MDIO_MASKDATA", 2913 "MDIO_MULTI_MMDS_EN", 2914 "MDIO_MULTI_PRTS_EN", 2915 "MEASURE_LFSR_CNT", 2916 "MEASURE_TIMEOUT", 2917 "MEAS_INCOMPLETE", 2918 "MICRO_AUTOINC_RDADDR_EN", 2919 "MICRO_AUTOINC_WRADDR_EN", 2920 "MICRO_CODE_RAM_ECC_ADDRESS", 2921 "MICRO_CODE_RAM_TM", 2922 "MICRO_CORE_CLK_EN", 2923 "MICRO_CORE_RSTB", 2924 "MICRO_DR_LOOKTAB_EN", 2925 "MICRO_DR_SIZE", 2926 "MICRO_ECCG_MODE", 2927 "MICRO_ECC_CORRUPT", 2928 "MICRO_ECC_FRC_DISABLE", 2929 "MICRO_GEN_INTR_RMI_MBOX0WR", 2930 "MICRO_GEN_INTR_RMI_MBOX1WR", 2931 "MICRO_M0_DEFAULT_SLAVE_ERROR", 2932 "MICRO_M0_HRESP_EN", 2933 "MICRO_MASTER_CLK_EN", 2934 "MICRO_MASTER_RSTB", 2935 "MICRO_PRAMIF_AHB_WRADDR_LSW", 2936 "MICRO_PRAMIF_AHB_WRADDR_MSW", 2937 "MICRO_PRAMIF_EN", 2938 "MICRO_PRAM_IF_RSTB", 2939 "MICRO_PR_AUTOINC_NXT_WRADDR_LSW", 2940 "MICRO_PR_DEFAULT_SLAVE_ERROR", 2941 "MICRO_PVT_TEMPDATA_FRC", 2942 "MICRO_PVT_TEMPDATA_FRCVAL", 2943 "MICRO_PVT_TEMPDATA_RMI", 2944 "MICRO_RA_AUTOINC_NXT_RDADDR_LSW", 2945 "MICRO_RA_AUTOINC_NXT_WRADDR_LSW", 2946 "MICRO_RA_ECC_RDDATA", 2947 "MICRO_RA_ECC_WRDATA", 2948 "MICRO_RA_INIT", 2949 "MICRO_RA_INITDONE", 2950 "MICRO_RA_RDADDR_LSW", 2951 "MICRO_RA_RDADDR_MSW", 2952 "MICRO_RA_RDDATASIZE", 2953 "MICRO_RA_RDDATA_LSW", 2954 "MICRO_RA_RDDATA_MSW", 2955 "MICRO_RA_WRADDR_LSW", 2956 "MICRO_RA_WRADDR_MSW", 2957 "MICRO_RA_WRDATASIZE", 2958 "MICRO_RA_WRDATA_LSW", 2959 "MICRO_RA_WRDATA_MSW", 2960 "MICRO_RMI_DEFAULT_SLAVE_ERROR", 2961 "MICRO_RMI_ECC_CORR_ERR_INTR_EN", 2962 "MICRO_RMI_ECC_CORR_ERR_STATUS", 2963 "MICRO_RMI_ECC_MULTIROW_ERR_INTR_EN", 2964 "MICRO_RMI_ECC_MULTIROW_ERR_STATUS", 2965 "MICRO_RMI_ECC_UNCORR_ERR_INTR_EN", 2966 "MICRO_RMI_ECC_UNCORR_ERR_STATUS", 2967 "MICRO_RMI_M0_LOCKUP_INTR_EN", 2968 "MICRO_RMI_M0_LOCKUP_STATUS", 2969 "MICRO_RMI_M0_SYSTEMRESETREQ_INTR_EN", 2970 "MICRO_RMI_M0_SYSTEMRESETREQ_STATUS", 2971 "MICRO_RMI_MBOX_MSGOUT_INTR_EN", 2972 "MICRO_RMI_MBOX_MSGOUT_STATUS", 2973 "MICRO_RMI_MBOX_SEND_MSGIN", 2974 "MICRO_RMI_TO_MICRO_MBOX0", 2975 "MICRO_RMI_TO_MICRO_MBOX1", 2976 "MICRO_SW_PMI_HP_EXT_RSTB", 2977 "MICRO_SW_PMI_HP_RSTB", 2978 "MICRO_TO_RMI_MBOX0", 2979 "MICRO_TO_RMI_MBOX1", 2980 "MICRO_TX_DISABLE", 2981 "OSR_MODE", 2982 "OSR_MODE_FRC", 2983 "OSR_MODE_FRC_VAL", 2984 "OSR_MODE_PIN", 2985 "OS_ALL_EDGES", 2986 "OS_PATTERN_ENHANCED", 2987 "PATT_GEN_EN", 2988 "PATT_GEN_SEQ_0", 2989 "PATT_GEN_SEQ_1", 2990 "PATT_GEN_SEQ_10", 2991 "PATT_GEN_SEQ_11", 2992 "PATT_GEN_SEQ_12", 2993 "PATT_GEN_SEQ_13", 2994 "PATT_GEN_SEQ_14", 2995 "PATT_GEN_SEQ_2", 2996 "PATT_GEN_SEQ_3", 2997 "PATT_GEN_SEQ_4", 2998 "PATT_GEN_SEQ_5", 2999 "PATT_GEN_SEQ_6", 3000 "PATT_GEN_SEQ_7", 3001 "PATT_GEN_SEQ_8", 3002 "PATT_GEN_SEQ_9", 3003 "PATT_GEN_START_POS", 3004 "PATT_GEN_STOP_POS", 3005 "PHASE_ERR_OFFSET", 3006 "PHASE_ERR_OFFSET_EN", 3007 "PHS_SUM_IGNORE_DSC_LOCK", 3008 "PLL_FORCE_CAP_DONE", 3009 "PLL_FORCE_CAP_DONE_EN", 3010 "PLL_FORCE_CAP_PASS", 3011 "PLL_FORCE_CAP_PASS_EN", 3012 "PLL_FORCE_FDONE", 3013 "PLL_FORCE_FDONE_EN", 3014 "PLL_FORCE_FPASS", 3015 "PLL_LOCK", 3016 "PLL_LOCK_FRC", 3017 "PLL_LOCK_FRC_VAL", 3018 "PLL_LOCK_LH_LL", 3019 "PLL_MODE", 3020 "PLL_SEQ_DONE", 3021 "PLL_SEQ_DONE_LH_LL", 3022 "PLL_SEQ_PASS", 3023 "PLL_SEQ_PASS_LH_LL", 3024 "PLL_SEQ_START", 3025 "PMD_CORE_DP_H_RSTB_PKILL", 3026 "PMD_CORE_MODE", 3027 "PMD_LANE_MODE", 3028 "PMD_LN_DP_H_RSTB_PKILL", 3029 "PMD_LN_H_RSTB_PKILL", 3030 "PMD_LN_RX_H_PWRDN_PKILL", 3031 "PMD_LN_TX_H_PWRDN_PKILL", 3032 "PMD_MDIO_TRANS_PKILL", 3033 "PMD_RX_CLK_VLD_FRC", 3034 "PMD_RX_CLK_VLD_FRC_VAL", 3035 "PMD_RX_LOCK", 3036 "PMD_RX_LOCK_CHANGE", 3037 "PMD_TX_CLK_VLD_FRC", 3038 "PMD_TX_CLK_VLD_FRC_VAL", 3039 "PMD_TX_DISABLE_PIN_DIS", 3040 "PRBS_BURST_ERR_LENGTH_STATUS", 3041 "PRBS_BURST_LEN_CHK_EN", 3042 "PRBS_CHK_CLK_EN_FRC_ON", 3043 "PRBS_CHK_EN", 3044 "PRBS_CHK_EN_AUTO_MODE", 3045 "PRBS_CHK_EN_TIMEOUT", 3046 "PRBS_CHK_EN_TIMER_MODE", 3047 "PRBS_CHK_ERR_CNT_BURST_MODE", 3048 "PRBS_CHK_ERR_CNT_LSB", 3049 "PRBS_CHK_ERR_CNT_MSB", 3050 "PRBS_CHK_INV", 3051 "PRBS_CHK_LOCK", 3052 "PRBS_CHK_LOCK_CNT", 3053 "PRBS_CHK_LOCK_LOST_LH", 3054 "PRBS_CHK_MODE", 3055 "PRBS_CHK_MODE_SEL", 3056 "PRBS_CHK_OOL_CNT", 3057 "PRBS_GEN_EN", 3058 "PRBS_GEN_ERR_INS", 3059 "PRBS_GEN_INV", 3060 "PRBS_GEN_MODE_SEL", 3061 "PRESET_DSC_AFE_BANK", 3062 "PRESET_DSC_A_BANK", 3063 "PRESET_DSC_C_BANK", 3064 "PRESET_DSC_D_BANK", 3065 "PRE_FREQ_DET_TIME", 3066 "PWRDN_SEQ_TIMER", 3067 "REFCLK_DIVCNT", 3068 "REFCLK_DIVCNT_SEL", 3069 "RESCAL_FRC", 3070 "RESCAL_FRC_VAL", 3071 "RESCAL_IN", 3072 "RESTART_PI_EXT_MODE", 3073 "RESTART_PMD_RESTART", 3074 "RESTART_SIGDET", 3075 "RES_CAL_CNTR", 3076 "RETRY_TIME", 3077 "REVID2", 3078 "REVID_BONDING", 3079 "REVID_CL72", 3080 "REVID_EEE", 3081 "REVID_LLP", 3082 "REVID_MDIO", 3083 "REVID_MICRO", 3084 "REVID_MODEL", 3085 "REVID_MULTIPLICITY", 3086 "REVID_PIR", 3087 "REVID_PROCESS", 3088 "REVID_REV_LETTER", 3089 "REVID_REV_NUMBER", 3090 "RMT_LPBK_EN", 3091 "RMT_LPBK_PD_EARLY_IND", 3092 "RMT_LPBK_PD_FRC_ON", 3093 "RMT_LPBK_PD_LATE_IND", 3094 "RMT_LPBK_PD_MODE", 3095 "RST_SEQ_DIS_FLT_MODE", 3096 "RST_SEQ_TIMER", 3097 "RXA_DFE_TAP10", 3098 "RXA_DFE_TAP10_MUX", 3099 "RXA_DFE_TAP11", 3100 "RXA_DFE_TAP11_MUX", 3101 "RXA_DFE_TAP12", 3102 "RXA_DFE_TAP12_MUX", 3103 "RXA_DFE_TAP13", 3104 "RXA_DFE_TAP13_MUX", 3105 "RXA_DFE_TAP14", 3106 "RXA_DFE_TAP14_MUX", 3107 "RXA_DFE_TAP2", 3108 "RXA_DFE_TAP3", 3109 "RXA_DFE_TAP4", 3110 "RXA_DFE_TAP5", 3111 "RXA_DFE_TAP6", 3112 "RXA_DFE_TAP7", 3113 "RXA_DFE_TAP7_MUX", 3114 "RXA_DFE_TAP8", 3115 "RXA_DFE_TAP8_MUX", 3116 "RXA_DFE_TAP9", 3117 "RXA_DFE_TAP9_MUX", 3118 "RXA_SLICER_OFFSET_ADJ_DN", 3119 "RXA_SLICER_OFFSET_ADJ_DP", 3120 "RXA_SLICER_OFFSET_ADJ_LMS", 3121 "RXA_SLICER_OFFSET_ADJ_ZN", 3122 "RXA_SLICER_OFFSET_ADJ_ZP", 3123 "RXB_DFE_TAP10", 3124 "RXB_DFE_TAP10_MUX", 3125 "RXB_DFE_TAP11", 3126 "RXB_DFE_TAP11_MUX", 3127 "RXB_DFE_TAP12", 3128 "RXB_DFE_TAP12_MUX", 3129 "RXB_DFE_TAP13", 3130 "RXB_DFE_TAP13_MUX", 3131 "RXB_DFE_TAP14", 3132 "RXB_DFE_TAP14_MUX", 3133 "RXB_DFE_TAP2", 3134 "RXB_DFE_TAP3", 3135 "RXB_DFE_TAP4", 3136 "RXB_DFE_TAP5", 3137 "RXB_DFE_TAP6", 3138 "RXB_DFE_TAP7", 3139 "RXB_DFE_TAP7_MUX", 3140 "RXB_DFE_TAP8", 3141 "RXB_DFE_TAP8_MUX", 3142 "RXB_DFE_TAP9", 3143 "RXB_DFE_TAP9_MUX", 3144 "RXB_SLICER_OFFSET_ADJ_DN", 3145 "RXB_SLICER_OFFSET_ADJ_DP", 3146 "RXB_SLICER_OFFSET_ADJ_LMS", 3147 "RXB_SLICER_OFFSET_ADJ_ZN", 3148 "RXB_SLICER_OFFSET_ADJ_ZP", 3149 "RXC_DFE_TAP10", 3150 "RXC_DFE_TAP10_MUX", 3151 "RXC_DFE_TAP11", 3152 "RXC_DFE_TAP11_MUX", 3153 "RXC_DFE_TAP12", 3154 "RXC_DFE_TAP12_MUX", 3155 "RXC_DFE_TAP13", 3156 "RXC_DFE_TAP13_MUX", 3157 "RXC_DFE_TAP14", 3158 "RXC_DFE_TAP14_MUX", 3159 "RXC_DFE_TAP2", 3160 "RXC_DFE_TAP3", 3161 "RXC_DFE_TAP4", 3162 "RXC_DFE_TAP5", 3163 "RXC_DFE_TAP6", 3164 "RXC_DFE_TAP7", 3165 "RXC_DFE_TAP7_MUX", 3166 "RXC_DFE_TAP8", 3167 "RXC_DFE_TAP8_MUX", 3168 "RXC_DFE_TAP9", 3169 "RXC_DFE_TAP9_MUX", 3170 "RXC_SLICER_OFFSET_ADJ_DN", 3171 "RXC_SLICER_OFFSET_ADJ_DP", 3172 "RXC_SLICER_OFFSET_ADJ_LMS", 3173 "RXC_SLICER_OFFSET_ADJ_ZN", 3174 "RXC_SLICER_OFFSET_ADJ_ZP", 3175 "RXD_DFE_TAP10", 3176 "RXD_DFE_TAP10_MUX", 3177 "RXD_DFE_TAP11", 3178 "RXD_DFE_TAP11_MUX", 3179 "RXD_DFE_TAP12", 3180 "RXD_DFE_TAP12_MUX", 3181 "RXD_DFE_TAP13", 3182 "RXD_DFE_TAP13_MUX", 3183 "RXD_DFE_TAP14", 3184 "RXD_DFE_TAP14_MUX", 3185 "RXD_DFE_TAP2", 3186 "RXD_DFE_TAP3", 3187 "RXD_DFE_TAP4", 3188 "RXD_DFE_TAP5", 3189 "RXD_DFE_TAP6", 3190 "RXD_DFE_TAP7", 3191 "RXD_DFE_TAP7_MUX", 3192 "RXD_DFE_TAP8", 3193 "RXD_DFE_TAP8_MUX", 3194 "RXD_DFE_TAP9", 3195 "RXD_DFE_TAP9_MUX", 3196 "RXD_SLICER_OFFSET_ADJ_DN", 3197 "RXD_SLICER_OFFSET_ADJ_DP", 3198 "RXD_SLICER_OFFSET_ADJ_LMS", 3199 "RXD_SLICER_OFFSET_ADJ_ZN", 3200 "RXD_SLICER_OFFSET_ADJ_ZP", 3201 "RX_DATA_15_TO_0", 3202 "RX_DATA_35_TO_20", 3203 "RX_DATA_THRESH_SEL", 3204 "RX_DSC_LOCK", 3205 "RX_DSC_LOCK_FRC", 3206 "RX_DSC_LOCK_FRC_VAL", 3207 "RX_LMS_THRESH_SEL", 3208 "RX_PF2_CTRL", 3209 "RX_PF_CTRL", 3210 "RX_PHASE_THRESH_SEL", 3211 "RX_PI_CNT_BIN_D", 3212 "RX_PI_CNT_BIN_DQ", 3213 "RX_PI_CNT_BIN_D_LD", 3214 "RX_PI_CNT_BIN_D_PD", 3215 "RX_PI_CNT_BIN_L", 3216 "RX_PI_CNT_BIN_LQ", 3217 "RX_PI_CNT_BIN_L_LD", 3218 "RX_PI_CNT_BIN_P", 3219 "RX_PI_CNT_BIN_PQ", 3220 "RX_PI_CNT_BIN_P_PD", 3221 "RX_PI_MANUAL_MODE", 3222 "RX_PI_MANUAL_STROBE", 3223 "RX_PI_PHASE_STEP_CNT", 3224 "RX_PI_PHASE_STEP_DIR", 3225 "RX_PI_SLICERS_EN", 3226 "RX_PMD_DP_INVERT", 3227 "RX_RESTART_PMD", 3228 "RX_RESTART_PMD_HOLD", 3229 "RX_VGA_CTRL", 3230 "RX_VGA_CTRL_VAL", 3231 "SDK_TX_DISABLE", 3232 "SET_MEAS_INCOMPLETE", 3233 "SIGDET_DP_RSTB_EN", 3234 "SIGNAL_DETECT", 3235 "SIGNAL_DETECT_CHANGE", 3236 "SIGNAL_DETECT_FILTER_1US", 3237 "SIGNAL_DETECT_FILTER_COUNT", 3238 "SIGNAL_DETECT_FRC", 3239 "SIGNAL_DETECT_FRC_VAL", 3240 "SIGNAL_DETECT_RAW", 3241 "SIGNAL_DETECT_RAW_CHANGE", 3242 "SIGNAL_DETECT_THRESH", 3243 "SLOWDN_XOR", 3244 "SUP_RST_SEQ_FRC", 3245 "SUP_RST_SEQ_FRC_VAL", 3246 "TDT_BIT_SEL", 3247 "TDT_CYCLE_BIN", 3248 "TDT_CYCLE_SEL", 3249 "TDT_PRBS_MODE", 3250 "TDT_PRBS_SLIP", 3251 "TDT_TRNSUM_EN", 3252 "THRESH_STEP_SIZE", 3253 "THRESH_TIMER_T1", 3254 "TIMER_DONE_FRC", 3255 "TIMER_DONE_FRC_VAL", 3256 "TLB_RX_DIFF_DEC_EN", 3257 "TLB_TX_DIFF_ENC_EN", 3258 "TRNSUM", 3259 "TRNSUM_A", 3260 "TRNSUM_A_LOW", 3261 "TRNSUM_B", 3262 "TRNSUM_B_LOW", 3263 "TRNSUM_C", 3264 "TRNSUM_CLR_FRC", 3265 "TRNSUM_CLR_FRC_VAL", 3266 "TRNSUM_COR_SEL", 3267 "TRNSUM_C_LOW", 3268 "TRNSUM_D", 3269 "TRNSUM_D_LOW", 3270 "TRNSUM_EDGE_PATTERN_EN", 3271 "TRNSUM_EN", 3272 "TRNSUM_ERROR_COUNT_EN", 3273 "TRNSUM_EYE_CLOSURE_EN", 3274 "TRNSUM_FRZ_FRC", 3275 "TRNSUM_FRZ_FRC_VAL", 3276 "TRNSUM_GAIN", 3277 "TRNSUM_INV_PATTERN_EN", 3278 "TRNSUM_LOW", 3279 "TRNSUM_PATTERN", 3280 "TRNSUM_PATTERN_BIT_EN", 3281 "TRNSUM_PATTERN_FULL_CHECK_OFF", 3282 "TRNSUM_QPHASE_MULT_EN", 3283 "TRNSUM_RANDOM_TAPSEL_DISABLE", 3284 "TRNSUM_SEL_EMUX", 3285 "TRNSUM_TAP_EN", 3286 "TRNSUM_TAP_RANGE_SEL", 3287 "TRNSUM_TAP_SIGN", 3288 "TXCOM_CL93N72_MAX_WAIT_TIMER_PERIOD", 3289 "TXCOM_CL93N72_WAIT_CNTR_LIMIT", 3290 "TXCOM_MAIN_TAP_ALERT_VAL", 3291 "TXCOM_POST_TAP_ALERT_VAL", 3292 "TXCOM_PRE_TAP_ALERT_VAL", 3293 "TXFIR_MAIN_ADJUSTED", 3294 "TXFIR_MAIN_AFTER_OVR", 3295 "TXFIR_MAIN_OFFSET", 3296 "TXFIR_POST2", 3297 "TXFIR_POST2_ADJUSTED", 3298 "TXFIR_POST2_OFFSET", 3299 "TXFIR_POST3", 3300 "TXFIR_POST3_ADJUSTED", 3301 "TXFIR_POST3_OFFSET", 3302 "TXFIR_POST_ADJUSTED", 3303 "TXFIR_POST_AFTER_OVR", 3304 "TXFIR_POST_OFFSET", 3305 "TXFIR_PRE_ADJUSTED", 3306 "TXFIR_PRE_AFTER_OVR", 3307 "TXFIR_PRE_OFFSET", 3308 "TX_DISABLE_OUTPUT_SEL", 3309 "TX_DISABLE_TIMER_CTRL", 3310 "TX_EEE_ALERT_EN", 3311 "TX_EEE_QUIET_EN", 3312 "TX_LANE_MAP_0", 3313 "TX_LANE_MAP_1", 3314 "TX_LANE_MAP_2", 3315 "TX_LANE_MAP_3", 3316 "TX_MUX_SEL_ORDER", 3317 "TX_PCS_NATIVE_ANA_FRMT_EN", 3318 "TX_PI_EN", 3319 "TX_PI_EXT_CTRL_EN", 3320 "TX_PI_EXT_PHASE_BWSEL_INTEG", 3321 "TX_PI_FIRST_ORDER_BWSEL_INTEG", 3322 "TX_PI_FREQ_OVERRIDE_EN", 3323 "TX_PI_FREQ_OVERRIDE_VAL", 3324 "TX_PI_FRZ_FRC", 3325 "TX_PI_FRZ_FRC_VAL", 3326 "TX_PI_FRZ_MODE", 3327 "TX_PI_INTEG1_REG", 3328 "TX_PI_INTEG2_REG", 3329 "TX_PI_JITTER_FILTER_EN", 3330 "TX_PI_JIT_AMP", 3331 "TX_PI_JIT_FREQ_IDX", 3332 "TX_PI_JIT_SSC_FREQ_MODE", 3333 "TX_PI_LOOP_FILTER_STABLE", 3334 "TX_PI_LOOP_TIMING_SRC_SEL", 3335 "TX_PI_PHASE_CNTR", 3336 "TX_PI_PHASE_ERR", 3337 "TX_PI_PHASE_INVERT", 3338 "TX_PI_PHASE_OVERRIDE", 3339 "TX_PI_PHASE_STEP_DIR", 3340 "TX_PI_PHASE_STEP_NUM", 3341 "TX_PI_PHASE_STROBE", 3342 "TX_PI_RESET_CODE_DBG", 3343 "TX_PI_RMT_LPBK_BYPASS_FLT", 3344 "TX_PI_SECOND_ORDER_BWSEL_INTEG", 3345 "TX_PI_SECOND_ORDER_LOOP_EN", 3346 "TX_PI_SJ_GEN_EN", 3347 "TX_PI_SSC_GEN_EN", 3348 "TX_PMD_DP_INVERT", 3349 "TX_S_CLKGATE_FRC_ON", 3350 "TX_S_COMCLK_FRC_ON", 3351 "TX_S_COMCLK_SEL", 3352 "UC_ACK_CORE_CFG_DONE", 3353 "UC_ACK_CORE_DP_RESET", 3354 "UC_ACK_DSC_CONFIG", 3355 "UC_ACK_DSC_EEE_DONE", 3356 "UC_ACK_DSC_RESTART", 3357 "UC_ACK_LANE_CFG_DONE", 3358 "UC_ACK_LANE_DP_RESET", 3359 "UC_ACTIVE", 3360 "UC_DSC_ERROR_FOUND", 3361 "UC_DSC_GP_UC_REQ", 3362 "UC_DSC_READY_FOR_CMD", 3363 "UC_DSC_SCRATCH", 3364 "UC_DSC_SUPP_INFO", 3365 "UC_TRNSUM_EN", 3366 "UC_TUNE_EN", 3367 "VCO_DONE_EN", 3368 "VCO_RANGE_ADJUST", 3369 "VCO_RST_EN", 3370 "VCO_START_TIME", 3371 "VCO_STEP_TIME", 3372 "VGA_DEC", 3373 "VGA_INC", 3374 "VGA_TIMER_T2", 3375 "VGA_WRITE", 3376 "WIN_CAL_CNTR", 3377 }; 3378 3379 #endif 3380 #endif 3381 #endif 3382 #endif /* PHYMOD_CONFIG_INCLUDE_FIELD_INFO */ 3383 3384 3385 3386 /******************************************************************************* 3387 * 3388 * The following is the symbol table itself. 3389 * It defines the entries for all registers and memories. 3390 * It also incorporates the field information for each register and memory if 3391 * applicable. 3392 */ 3393 static const phymod_symbol_t bcmi_falcon_xgxs_syms[] = { 3394 #ifndef PHYMOD_CONFIG_EXCLUDE_CHIP_SYMBOLS_BCMI_FALCON_XGXS 3395 { 3396 BCMI_FALCON_XGXS_ACC_CTLr, 3397 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3398 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 3399 BCMI_FALCON_XGXS_ACC_CTLr_fields, 3400 #else 3401 0, 3402 #endif 3403 #endif 3404 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3405 PHYMOD_SYMBOL_FLAG_REGISTER, 3406 "ACC_CTLr", 3407 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3408 "MDIO_CL22_IEEE_COM_ACC_CTRL", 3409 NULL, 3410 #endif 3411 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3412 0x0, /* 0 */ 3413 0, 3414 #endif 3415 }, 3416 { 3417 BCMI_FALCON_XGXS_ACC_ADDR_DATAr, 3418 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3419 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 3420 BCMI_FALCON_XGXS_ACC_ADDR_DATAr_fields, 3421 #else 3422 0, 3423 #endif 3424 #endif 3425 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3426 PHYMOD_SYMBOL_FLAG_REGISTER, 3427 "ACC_ADDR_DATAr", 3428 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3429 "MDIO_CL22_IEEE_COM_ACC_ADDR_DATA", 3430 NULL, 3431 #endif 3432 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3433 0x0, /* 0 */ 3434 0, 3435 #endif 3436 }, 3437 { 3438 BCMI_FALCON_XGXS_CL93N72_IT_BASE_R_PMD_CTLr, 3439 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3440 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 3441 BCMI_FALCON_XGXS_CL93N72_IT_BASE_R_PMD_CTLr_fields, 3442 #else 3443 0, 3444 #endif 3445 #endif 3446 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3447 PHYMOD_SYMBOL_FLAG_REGISTER, 3448 "CL93N72_IT_BASE_R_PMD_CTLr", 3449 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3450 "CL93N72_IEEE_TX_CL93N72IT_BASE_R_PMD_CONTROL_REGISTER_150", 3451 NULL, 3452 #endif 3453 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3454 0x0, /* 0 */ 3455 0, 3456 #endif 3457 }, 3458 { 3459 BCMI_FALCON_XGXS_CL93N72_IT_BASE_R_PMD_STSr, 3460 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3461 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 3462 BCMI_FALCON_XGXS_CL93N72_IT_BASE_R_PMD_STSr_fields, 3463 #else 3464 0, 3465 #endif 3466 #endif 3467 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3468 PHYMOD_SYMBOL_FLAG_REGISTER, 3469 "CL93N72_IT_BASE_R_PMD_STSr", 3470 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3471 "CL93N72_IEEE_TX_CL93N72IT_BASE_R_PMD_STATUS_REGISTER_151", 3472 NULL, 3473 #endif 3474 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3475 0x0, /* 0 */ 3476 0, 3477 #endif 3478 }, 3479 { 3480 BCMI_FALCON_XGXS_CL93N72_IR_BASE_R_LP_COEFF_UPDr, 3481 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3482 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 3483 BCMI_FALCON_XGXS_CL93N72_IR_BASE_R_LP_COEFF_UPDr_fields, 3484 #else 3485 0, 3486 #endif 3487 #endif 3488 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3489 PHYMOD_SYMBOL_FLAG_REGISTER, 3490 "CL93N72_IR_BASE_R_LP_COEFF_UPDr", 3491 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3492 "CL93N72_IEEE_RX_CL93N72IR_BASE_R_LP_COEFF_UPDATE_REGISTER_152", 3493 NULL, 3494 #endif 3495 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3496 0x0, /* 0 */ 3497 0, 3498 #endif 3499 }, 3500 { 3501 BCMI_FALCON_XGXS_CL93N72_IR_BASE_R_LP_STS_REPr, 3502 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3503 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 3504 BCMI_FALCON_XGXS_CL93N72_IR_BASE_R_LP_STS_REPr_fields, 3505 #else 3506 0, 3507 #endif 3508 #endif 3509 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3510 PHYMOD_SYMBOL_FLAG_REGISTER, 3511 "CL93N72_IR_BASE_R_LP_STS_REPr", 3512 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3513 "CL93N72_IEEE_RX_CL93N72IR_BASE_R_LP_STATUS_REPORT_REGISTER_153", 3514 NULL, 3515 #endif 3516 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3517 0x0, /* 0 */ 3518 0, 3519 #endif 3520 }, 3521 { 3522 BCMI_FALCON_XGXS_CL93N72_IT_BASE_R_LD_COEFF_UPDr, 3523 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3524 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 3525 BCMI_FALCON_XGXS_CL93N72_IT_BASE_R_LD_COEFF_UPDr_fields, 3526 #else 3527 0, 3528 #endif 3529 #endif 3530 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3531 PHYMOD_SYMBOL_FLAG_REGISTER, 3532 "CL93N72_IT_BASE_R_LD_COEFF_UPDr", 3533 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3534 "CL93N72_IEEE_TX_CL93N72IT_BASE_R_LD_COEFF_UPDATE_REGISTER_154", 3535 NULL, 3536 #endif 3537 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3538 0x0, /* 0 */ 3539 0, 3540 #endif 3541 }, 3542 { 3543 BCMI_FALCON_XGXS_CL93N72_IT_BASE_R_LD_STS_REPr, 3544 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3545 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 3546 BCMI_FALCON_XGXS_CL93N72_IT_BASE_R_LD_STS_REPr_fields, 3547 #else 3548 0, 3549 #endif 3550 #endif 3551 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3552 PHYMOD_SYMBOL_FLAG_REGISTER, 3553 "CL93N72_IT_BASE_R_LD_STS_REPr", 3554 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3555 "CL93N72_IEEE_TX_CL93N72IT_BASE_R_LD_STATUS_REPORT_REGISTER_155", 3556 NULL, 3557 #endif 3558 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3559 0x0, /* 0 */ 3560 0, 3561 #endif 3562 }, 3563 { 3564 BCMI_FALCON_XGXS_DSC_RX_PF_CTL_DC_OFFSr, 3565 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3566 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 3567 BCMI_FALCON_XGXS_DSC_RX_PF_CTL_DC_OFFSr_fields, 3568 #else 3569 0, 3570 #endif 3571 #endif 3572 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3573 PHYMOD_SYMBOL_FLAG_REGISTER, 3574 "DSC_RX_PF_CTL_DC_OFFSr", 3575 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3576 "DSC_AFE1_RX_PF_CTRL_DC_OFFSET", 3577 NULL, 3578 #endif 3579 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3580 0x0, /* 0 */ 3581 0, 3582 #endif 3583 }, 3584 { 3585 BCMI_FALCON_XGXS_DSC_RXA_SLCR_OFFS_ADJ_DN_DPr, 3586 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3587 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 3588 BCMI_FALCON_XGXS_DSC_RXA_SLCR_OFFS_ADJ_DN_DPr_fields, 3589 #else 3590 0, 3591 #endif 3592 #endif 3593 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3594 PHYMOD_SYMBOL_FLAG_REGISTER, 3595 "DSC_RXA_SLCR_OFFS_ADJ_DN_DPr", 3596 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3597 "DSC_AFE1_RXA_SLICER_OFFSET_ADJ_DN_DP", 3598 NULL, 3599 #endif 3600 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3601 0x0, /* 0 */ 3602 0, 3603 #endif 3604 }, 3605 { 3606 BCMI_FALCON_XGXS_DSC_RXA_SLCR_OFFS_ADJ_ZN_ZPr, 3607 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3608 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 3609 BCMI_FALCON_XGXS_DSC_RXA_SLCR_OFFS_ADJ_ZN_ZPr_fields, 3610 #else 3611 0, 3612 #endif 3613 #endif 3614 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3615 PHYMOD_SYMBOL_FLAG_REGISTER, 3616 "DSC_RXA_SLCR_OFFS_ADJ_ZN_ZPr", 3617 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3618 "DSC_AFE1_RXA_SLICER_OFFSET_ADJ_ZN_ZP", 3619 NULL, 3620 #endif 3621 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3622 0x0, /* 0 */ 3623 0, 3624 #endif 3625 }, 3626 { 3627 BCMI_FALCON_XGXS_DSC_RXAB_SLCR_OFFS_ADJ_LMSr, 3628 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3629 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 3630 BCMI_FALCON_XGXS_DSC_RXAB_SLCR_OFFS_ADJ_LMSr_fields, 3631 #else 3632 0, 3633 #endif 3634 #endif 3635 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3636 PHYMOD_SYMBOL_FLAG_REGISTER, 3637 "DSC_RXAB_SLCR_OFFS_ADJ_LMSr", 3638 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3639 "DSC_AFE1_RXAB_SLICER_OFFSET_ADJ_LMS", 3640 NULL, 3641 #endif 3642 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3643 0x0, /* 0 */ 3644 0, 3645 #endif 3646 }, 3647 { 3648 BCMI_FALCON_XGXS_DSC_RXB_SLCR_OFFS_ADJ_DN_DPr, 3649 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3650 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 3651 BCMI_FALCON_XGXS_DSC_RXB_SLCR_OFFS_ADJ_DN_DPr_fields, 3652 #else 3653 0, 3654 #endif 3655 #endif 3656 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3657 PHYMOD_SYMBOL_FLAG_REGISTER, 3658 "DSC_RXB_SLCR_OFFS_ADJ_DN_DPr", 3659 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3660 "DSC_AFE1_RXB_SLICER_OFFSET_ADJ_DN_DP", 3661 NULL, 3662 #endif 3663 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3664 0x0, /* 0 */ 3665 0, 3666 #endif 3667 }, 3668 { 3669 BCMI_FALCON_XGXS_DSC_RXB_SLCR_OFFS_ADJ_ZN_ZPr, 3670 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3671 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 3672 BCMI_FALCON_XGXS_DSC_RXB_SLCR_OFFS_ADJ_ZN_ZPr_fields, 3673 #else 3674 0, 3675 #endif 3676 #endif 3677 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3678 PHYMOD_SYMBOL_FLAG_REGISTER, 3679 "DSC_RXB_SLCR_OFFS_ADJ_ZN_ZPr", 3680 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3681 "DSC_AFE1_RXB_SLICER_OFFSET_ADJ_ZN_ZP", 3682 NULL, 3683 #endif 3684 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3685 0x0, /* 0 */ 3686 0, 3687 #endif 3688 }, 3689 { 3690 BCMI_FALCON_XGXS_DSC_RXC_SLCR_OFFS_ADJ_DN_DPr, 3691 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3692 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 3693 BCMI_FALCON_XGXS_DSC_RXC_SLCR_OFFS_ADJ_DN_DPr_fields, 3694 #else 3695 0, 3696 #endif 3697 #endif 3698 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3699 PHYMOD_SYMBOL_FLAG_REGISTER, 3700 "DSC_RXC_SLCR_OFFS_ADJ_DN_DPr", 3701 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3702 "DSC_AFE1_RXC_SLICER_OFFSET_ADJ_DN_DP", 3703 NULL, 3704 #endif 3705 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3706 0x0, /* 0 */ 3707 0, 3708 #endif 3709 }, 3710 { 3711 BCMI_FALCON_XGXS_DSC_RXC_SLCR_OFFS_ADJ_ZN_ZPr, 3712 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3713 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 3714 BCMI_FALCON_XGXS_DSC_RXC_SLCR_OFFS_ADJ_ZN_ZPr_fields, 3715 #else 3716 0, 3717 #endif 3718 #endif 3719 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3720 PHYMOD_SYMBOL_FLAG_REGISTER, 3721 "DSC_RXC_SLCR_OFFS_ADJ_ZN_ZPr", 3722 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3723 "DSC_AFE1_RXC_SLICER_OFFSET_ADJ_ZN_ZP", 3724 NULL, 3725 #endif 3726 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3727 0x0, /* 0 */ 3728 0, 3729 #endif 3730 }, 3731 { 3732 BCMI_FALCON_XGXS_DSC_RXCD_SLCR_OFFS_ADJ_LMSr, 3733 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3734 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 3735 BCMI_FALCON_XGXS_DSC_RXCD_SLCR_OFFS_ADJ_LMSr_fields, 3736 #else 3737 0, 3738 #endif 3739 #endif 3740 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3741 PHYMOD_SYMBOL_FLAG_REGISTER, 3742 "DSC_RXCD_SLCR_OFFS_ADJ_LMSr", 3743 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3744 "DSC_AFE1_RXCD_SLICER_OFFSET_ADJ_LMS", 3745 NULL, 3746 #endif 3747 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3748 0x0, /* 0 */ 3749 0, 3750 #endif 3751 }, 3752 { 3753 BCMI_FALCON_XGXS_DSC_RXD_SLCR_OFFS_ADJ_DN_DPr, 3754 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3755 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 3756 BCMI_FALCON_XGXS_DSC_RXD_SLCR_OFFS_ADJ_DN_DPr_fields, 3757 #else 3758 0, 3759 #endif 3760 #endif 3761 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3762 PHYMOD_SYMBOL_FLAG_REGISTER, 3763 "DSC_RXD_SLCR_OFFS_ADJ_DN_DPr", 3764 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3765 "DSC_AFE1_RXD_SLICER_OFFSET_ADJ_DN_DP", 3766 NULL, 3767 #endif 3768 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3769 0x0, /* 0 */ 3770 0, 3771 #endif 3772 }, 3773 { 3774 BCMI_FALCON_XGXS_DSC_RXD_SLCR_OFFS_ADJ_ZN_ZPr, 3775 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3776 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 3777 BCMI_FALCON_XGXS_DSC_RXD_SLCR_OFFS_ADJ_ZN_ZPr_fields, 3778 #else 3779 0, 3780 #endif 3781 #endif 3782 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3783 PHYMOD_SYMBOL_FLAG_REGISTER, 3784 "DSC_RXD_SLCR_OFFS_ADJ_ZN_ZPr", 3785 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3786 "DSC_AFE1_RXD_SLICER_OFFSET_ADJ_ZN_ZP", 3787 NULL, 3788 #endif 3789 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3790 0x0, /* 0 */ 3791 0, 3792 #endif 3793 }, 3794 { 3795 BCMI_FALCON_XGXS_DSC_RX_PHASE_LMS_THR_SELr, 3796 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3797 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 3798 BCMI_FALCON_XGXS_DSC_RX_PHASE_LMS_THR_SELr_fields, 3799 #else 3800 0, 3801 #endif 3802 #endif 3803 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3804 PHYMOD_SYMBOL_FLAG_REGISTER, 3805 "DSC_RX_PHASE_LMS_THR_SELr", 3806 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3807 "DSC_AFE1_RX_PHASE_LMS_THRESH_SEL", 3808 NULL, 3809 #endif 3810 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3811 0x0, /* 0 */ 3812 0, 3813 #endif 3814 }, 3815 { 3816 BCMI_FALCON_XGXS_DSC_RX_DFE_TAP2_ABr, 3817 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3818 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 3819 BCMI_FALCON_XGXS_DSC_RX_DFE_TAP2_ABr_fields, 3820 #else 3821 0, 3822 #endif 3823 #endif 3824 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3825 PHYMOD_SYMBOL_FLAG_REGISTER, 3826 "DSC_RX_DFE_TAP2_ABr", 3827 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3828 "DSC_AFE2_RX_DFE_TAP2_AB", 3829 NULL, 3830 #endif 3831 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3832 0x0, /* 0 */ 3833 0, 3834 #endif 3835 }, 3836 { 3837 BCMI_FALCON_XGXS_DSC_RX_DFE_TAP2_CDr, 3838 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3839 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 3840 BCMI_FALCON_XGXS_DSC_RX_DFE_TAP2_CDr_fields, 3841 #else 3842 0, 3843 #endif 3844 #endif 3845 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3846 PHYMOD_SYMBOL_FLAG_REGISTER, 3847 "DSC_RX_DFE_TAP2_CDr", 3848 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3849 "DSC_AFE2_RX_DFE_TAP2_CD", 3850 NULL, 3851 #endif 3852 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3853 0x0, /* 0 */ 3854 0, 3855 #endif 3856 }, 3857 { 3858 BCMI_FALCON_XGXS_DSC_RX_DFE_TAP3_ABr, 3859 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3860 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 3861 BCMI_FALCON_XGXS_DSC_RX_DFE_TAP3_ABr_fields, 3862 #else 3863 0, 3864 #endif 3865 #endif 3866 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3867 PHYMOD_SYMBOL_FLAG_REGISTER, 3868 "DSC_RX_DFE_TAP3_ABr", 3869 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3870 "DSC_AFE2_RX_DFE_TAP3_AB", 3871 NULL, 3872 #endif 3873 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3874 0x0, /* 0 */ 3875 0, 3876 #endif 3877 }, 3878 { 3879 BCMI_FALCON_XGXS_DSC_RX_DFE_TAP3_CDr, 3880 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3881 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 3882 BCMI_FALCON_XGXS_DSC_RX_DFE_TAP3_CDr_fields, 3883 #else 3884 0, 3885 #endif 3886 #endif 3887 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3888 PHYMOD_SYMBOL_FLAG_REGISTER, 3889 "DSC_RX_DFE_TAP3_CDr", 3890 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3891 "DSC_AFE2_RX_DFE_TAP3_CD", 3892 NULL, 3893 #endif 3894 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3895 0x0, /* 0 */ 3896 0, 3897 #endif 3898 }, 3899 { 3900 BCMI_FALCON_XGXS_DSC_RX_DFE_TAP4_ABCDr, 3901 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3902 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 3903 BCMI_FALCON_XGXS_DSC_RX_DFE_TAP4_ABCDr_fields, 3904 #else 3905 0, 3906 #endif 3907 #endif 3908 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3909 PHYMOD_SYMBOL_FLAG_REGISTER, 3910 "DSC_RX_DFE_TAP4_ABCDr", 3911 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3912 "DSC_AFE2_RX_DFE_TAP4_ABCD", 3913 NULL, 3914 #endif 3915 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3916 0x0, /* 0 */ 3917 0, 3918 #endif 3919 }, 3920 { 3921 BCMI_FALCON_XGXS_DSC_RX_DFE_TAP5_ABCDr, 3922 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3923 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 3924 BCMI_FALCON_XGXS_DSC_RX_DFE_TAP5_ABCDr_fields, 3925 #else 3926 0, 3927 #endif 3928 #endif 3929 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3930 PHYMOD_SYMBOL_FLAG_REGISTER, 3931 "DSC_RX_DFE_TAP5_ABCDr", 3932 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3933 "DSC_AFE2_RX_DFE_TAP5_ABCD", 3934 NULL, 3935 #endif 3936 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3937 0x0, /* 0 */ 3938 0, 3939 #endif 3940 }, 3941 { 3942 BCMI_FALCON_XGXS_DSC_RX_DFE_TAP6_ABCDr, 3943 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3944 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 3945 BCMI_FALCON_XGXS_DSC_RX_DFE_TAP6_ABCDr_fields, 3946 #else 3947 0, 3948 #endif 3949 #endif 3950 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3951 PHYMOD_SYMBOL_FLAG_REGISTER, 3952 "DSC_RX_DFE_TAP6_ABCDr", 3953 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3954 "DSC_AFE2_RX_DFE_TAP6_ABCD", 3955 NULL, 3956 #endif 3957 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3958 0x0, /* 0 */ 3959 0, 3960 #endif 3961 }, 3962 { 3963 BCMI_FALCON_XGXS_DSC_RX_DFE_TAP7_ABCDr, 3964 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3965 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 3966 BCMI_FALCON_XGXS_DSC_RX_DFE_TAP7_ABCDr_fields, 3967 #else 3968 0, 3969 #endif 3970 #endif 3971 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3972 PHYMOD_SYMBOL_FLAG_REGISTER, 3973 "DSC_RX_DFE_TAP7_ABCDr", 3974 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3975 "DSC_AFE2_RX_DFE_TAP7_ABCD", 3976 NULL, 3977 #endif 3978 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3979 0x0, /* 0 */ 3980 0, 3981 #endif 3982 }, 3983 { 3984 BCMI_FALCON_XGXS_DSC_RX_DFE_TAP8_ABCDr, 3985 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3986 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 3987 BCMI_FALCON_XGXS_DSC_RX_DFE_TAP8_ABCDr_fields, 3988 #else 3989 0, 3990 #endif 3991 #endif 3992 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3993 PHYMOD_SYMBOL_FLAG_REGISTER, 3994 "DSC_RX_DFE_TAP8_ABCDr", 3995 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3996 "DSC_AFE2_RX_DFE_TAP8_ABCD", 3997 NULL, 3998 #endif 3999 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4000 0x0, /* 0 */ 4001 0, 4002 #endif 4003 }, 4004 { 4005 BCMI_FALCON_XGXS_DSC_RX_DFE_TAP9_ABCDr, 4006 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4007 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 4008 BCMI_FALCON_XGXS_DSC_RX_DFE_TAP9_ABCDr_fields, 4009 #else 4010 0, 4011 #endif 4012 #endif 4013 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4014 PHYMOD_SYMBOL_FLAG_REGISTER, 4015 "DSC_RX_DFE_TAP9_ABCDr", 4016 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4017 "DSC_AFE2_RX_DFE_TAP9_ABCD", 4018 NULL, 4019 #endif 4020 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4021 0x0, /* 0 */ 4022 0, 4023 #endif 4024 }, 4025 { 4026 BCMI_FALCON_XGXS_DSC_RX_DFE_TAP10_ABCDr, 4027 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4028 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 4029 BCMI_FALCON_XGXS_DSC_RX_DFE_TAP10_ABCDr_fields, 4030 #else 4031 0, 4032 #endif 4033 #endif 4034 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4035 PHYMOD_SYMBOL_FLAG_REGISTER, 4036 "DSC_RX_DFE_TAP10_ABCDr", 4037 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4038 "DSC_AFE3_RX_DFE_TAP10_ABCD", 4039 NULL, 4040 #endif 4041 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4042 0x0, /* 0 */ 4043 0, 4044 #endif 4045 }, 4046 { 4047 BCMI_FALCON_XGXS_DSC_RX_DFE_TAP11_ABCDr, 4048 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4049 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 4050 BCMI_FALCON_XGXS_DSC_RX_DFE_TAP11_ABCDr_fields, 4051 #else 4052 0, 4053 #endif 4054 #endif 4055 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4056 PHYMOD_SYMBOL_FLAG_REGISTER, 4057 "DSC_RX_DFE_TAP11_ABCDr", 4058 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4059 "DSC_AFE3_RX_DFE_TAP11_ABCD", 4060 NULL, 4061 #endif 4062 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4063 0x0, /* 0 */ 4064 0, 4065 #endif 4066 }, 4067 { 4068 BCMI_FALCON_XGXS_DSC_RX_DFE_TAP12_ABCDr, 4069 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4070 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 4071 BCMI_FALCON_XGXS_DSC_RX_DFE_TAP12_ABCDr_fields, 4072 #else 4073 0, 4074 #endif 4075 #endif 4076 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4077 PHYMOD_SYMBOL_FLAG_REGISTER, 4078 "DSC_RX_DFE_TAP12_ABCDr", 4079 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4080 "DSC_AFE3_RX_DFE_TAP12_ABCD", 4081 NULL, 4082 #endif 4083 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4084 0x0, /* 0 */ 4085 0, 4086 #endif 4087 }, 4088 { 4089 BCMI_FALCON_XGXS_DSC_RX_DFE_TAP13_ABCDr, 4090 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4091 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 4092 BCMI_FALCON_XGXS_DSC_RX_DFE_TAP13_ABCDr_fields, 4093 #else 4094 0, 4095 #endif 4096 #endif 4097 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4098 PHYMOD_SYMBOL_FLAG_REGISTER, 4099 "DSC_RX_DFE_TAP13_ABCDr", 4100 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4101 "DSC_AFE3_RX_DFE_TAP13_ABCD", 4102 NULL, 4103 #endif 4104 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4105 0x0, /* 0 */ 4106 0, 4107 #endif 4108 }, 4109 { 4110 BCMI_FALCON_XGXS_DSC_RX_DFE_TAP14_ABCDr, 4111 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4112 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 4113 BCMI_FALCON_XGXS_DSC_RX_DFE_TAP14_ABCDr_fields, 4114 #else 4115 0, 4116 #endif 4117 #endif 4118 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4119 PHYMOD_SYMBOL_FLAG_REGISTER, 4120 "DSC_RX_DFE_TAP14_ABCDr", 4121 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4122 "DSC_AFE3_RX_DFE_TAP14_ABCD", 4123 NULL, 4124 #endif 4125 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4126 0x0, /* 0 */ 4127 0, 4128 #endif 4129 }, 4130 { 4131 BCMI_FALCON_XGXS_DSC_RX_DFE_TAP7_8_MUX_ABCDr, 4132 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4133 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 4134 BCMI_FALCON_XGXS_DSC_RX_DFE_TAP7_8_MUX_ABCDr_fields, 4135 #else 4136 0, 4137 #endif 4138 #endif 4139 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4140 PHYMOD_SYMBOL_FLAG_REGISTER, 4141 "DSC_RX_DFE_TAP7_8_MUX_ABCDr", 4142 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4143 "DSC_AFE3_RX_DFE_TAP7_8_MUX_ABCD", 4144 NULL, 4145 #endif 4146 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4147 0x0, /* 0 */ 4148 0, 4149 #endif 4150 }, 4151 { 4152 BCMI_FALCON_XGXS_DSC_RX_DFE_TAP9_10_MUX_ABCDr, 4153 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4154 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 4155 BCMI_FALCON_XGXS_DSC_RX_DFE_TAP9_10_MUX_ABCDr_fields, 4156 #else 4157 0, 4158 #endif 4159 #endif 4160 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4161 PHYMOD_SYMBOL_FLAG_REGISTER, 4162 "DSC_RX_DFE_TAP9_10_MUX_ABCDr", 4163 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4164 "DSC_AFE3_RX_DFE_TAP9_10_MUX_ABCD", 4165 NULL, 4166 #endif 4167 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4168 0x0, /* 0 */ 4169 0, 4170 #endif 4171 }, 4172 { 4173 BCMI_FALCON_XGXS_DSC_RX_DFE_TAP11_12_MUX_ABCDr, 4174 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4175 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 4176 BCMI_FALCON_XGXS_DSC_RX_DFE_TAP11_12_MUX_ABCDr_fields, 4177 #else 4178 0, 4179 #endif 4180 #endif 4181 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4182 PHYMOD_SYMBOL_FLAG_REGISTER, 4183 "DSC_RX_DFE_TAP11_12_MUX_ABCDr", 4184 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4185 "DSC_AFE3_RX_DFE_TAP11_12_MUX_ABCD", 4186 NULL, 4187 #endif 4188 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4189 0x0, /* 0 */ 4190 0, 4191 #endif 4192 }, 4193 { 4194 BCMI_FALCON_XGXS_DSC_RX_DFE_TAP13_14_MUX_ABCDr, 4195 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4196 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 4197 BCMI_FALCON_XGXS_DSC_RX_DFE_TAP13_14_MUX_ABCDr_fields, 4198 #else 4199 0, 4200 #endif 4201 #endif 4202 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4203 PHYMOD_SYMBOL_FLAG_REGISTER, 4204 "DSC_RX_DFE_TAP13_14_MUX_ABCDr", 4205 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4206 "DSC_AFE3_RX_DFE_TAP13_14_MUX_ABCD", 4207 NULL, 4208 #endif 4209 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4210 0x0, /* 0 */ 4211 0, 4212 #endif 4213 }, 4214 { 4215 BCMI_FALCON_XGXS_DSC_LOAD_PRESETSr, 4216 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4217 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 4218 BCMI_FALCON_XGXS_DSC_LOAD_PRESETSr_fields, 4219 #else 4220 0, 4221 #endif 4222 #endif 4223 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4224 PHYMOD_SYMBOL_FLAG_REGISTER, 4225 "DSC_LOAD_PRESETSr", 4226 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4227 "DSC_AFE3_LOAD_PRESETS", 4228 NULL, 4229 #endif 4230 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4231 0x0, /* 0 */ 4232 0, 4233 #endif 4234 }, 4235 { 4236 BCMI_FALCON_XGXS_DSC_UC_CTLr, 4237 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4238 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 4239 BCMI_FALCON_XGXS_DSC_UC_CTLr_fields, 4240 #else 4241 0, 4242 #endif 4243 #endif 4244 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4245 PHYMOD_SYMBOL_FLAG_REGISTER, 4246 "DSC_UC_CTLr", 4247 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4248 "DSC_A_DSC_UC_CTRL", 4249 NULL, 4250 #endif 4251 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4252 0x0, /* 0 */ 4253 0, 4254 #endif 4255 }, 4256 { 4257 BCMI_FALCON_XGXS_DSC_SCRATCHr, 4258 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4259 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 4260 BCMI_FALCON_XGXS_DSC_SCRATCHr_fields, 4261 #else 4262 0, 4263 #endif 4264 #endif 4265 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4266 PHYMOD_SYMBOL_FLAG_REGISTER, 4267 "DSC_SCRATCHr", 4268 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4269 "DSC_A_DSC_SCRATCH", 4270 NULL, 4271 #endif 4272 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4273 0x0, /* 0 */ 4274 0, 4275 #endif 4276 }, 4277 { 4278 BCMI_FALCON_XGXS_DSC_TRNSUM_A_LOr, 4279 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4280 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 4281 BCMI_FALCON_XGXS_DSC_TRNSUM_A_LOr_fields, 4282 #else 4283 0, 4284 #endif 4285 #endif 4286 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4287 PHYMOD_SYMBOL_FLAG_REGISTER, 4288 "DSC_TRNSUM_A_LOr", 4289 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4290 "DSC_B_TRNSUM_A_LOW", 4291 NULL, 4292 #endif 4293 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4294 0x0, /* 0 */ 4295 0, 4296 #endif 4297 }, 4298 { 4299 BCMI_FALCON_XGXS_DSC_TRNSUM_Ar, 4300 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4301 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 4302 BCMI_FALCON_XGXS_DSC_TRNSUM_Ar_fields, 4303 #else 4304 0, 4305 #endif 4306 #endif 4307 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4308 PHYMOD_SYMBOL_FLAG_REGISTER, 4309 "DSC_TRNSUM_Ar", 4310 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4311 "DSC_B_TRNSUM_A", 4312 NULL, 4313 #endif 4314 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4315 0x0, /* 0 */ 4316 0, 4317 #endif 4318 }, 4319 { 4320 BCMI_FALCON_XGXS_DSC_TRNSUM_B_LOr, 4321 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4322 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 4323 BCMI_FALCON_XGXS_DSC_TRNSUM_B_LOr_fields, 4324 #else 4325 0, 4326 #endif 4327 #endif 4328 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4329 PHYMOD_SYMBOL_FLAG_REGISTER, 4330 "DSC_TRNSUM_B_LOr", 4331 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4332 "DSC_B_TRNSUM_B_LOW", 4333 NULL, 4334 #endif 4335 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4336 0x0, /* 0 */ 4337 0, 4338 #endif 4339 }, 4340 { 4341 BCMI_FALCON_XGXS_DSC_TRNSUM_Br, 4342 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4343 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 4344 BCMI_FALCON_XGXS_DSC_TRNSUM_Br_fields, 4345 #else 4346 0, 4347 #endif 4348 #endif 4349 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4350 PHYMOD_SYMBOL_FLAG_REGISTER, 4351 "DSC_TRNSUM_Br", 4352 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4353 "DSC_B_TRNSUM_B", 4354 NULL, 4355 #endif 4356 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4357 0x0, /* 0 */ 4358 0, 4359 #endif 4360 }, 4361 { 4362 BCMI_FALCON_XGXS_DSC_TRNSUM_C_LOr, 4363 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4364 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 4365 BCMI_FALCON_XGXS_DSC_TRNSUM_C_LOr_fields, 4366 #else 4367 0, 4368 #endif 4369 #endif 4370 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4371 PHYMOD_SYMBOL_FLAG_REGISTER, 4372 "DSC_TRNSUM_C_LOr", 4373 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4374 "DSC_B_TRNSUM_C_LOW", 4375 NULL, 4376 #endif 4377 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4378 0x0, /* 0 */ 4379 0, 4380 #endif 4381 }, 4382 { 4383 BCMI_FALCON_XGXS_DSC_TRNSUM_Cr, 4384 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4385 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 4386 BCMI_FALCON_XGXS_DSC_TRNSUM_Cr_fields, 4387 #else 4388 0, 4389 #endif 4390 #endif 4391 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4392 PHYMOD_SYMBOL_FLAG_REGISTER, 4393 "DSC_TRNSUM_Cr", 4394 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4395 "DSC_B_TRNSUM_C", 4396 NULL, 4397 #endif 4398 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4399 0x0, /* 0 */ 4400 0, 4401 #endif 4402 }, 4403 { 4404 BCMI_FALCON_XGXS_DSC_TRNSUM_D_LOr, 4405 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4406 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 4407 BCMI_FALCON_XGXS_DSC_TRNSUM_D_LOr_fields, 4408 #else 4409 0, 4410 #endif 4411 #endif 4412 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4413 PHYMOD_SYMBOL_FLAG_REGISTER, 4414 "DSC_TRNSUM_D_LOr", 4415 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4416 "DSC_B_TRNSUM_D_LOW", 4417 NULL, 4418 #endif 4419 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4420 0x0, /* 0 */ 4421 0, 4422 #endif 4423 }, 4424 { 4425 BCMI_FALCON_XGXS_DSC_TRNSUM_Dr, 4426 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4427 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 4428 BCMI_FALCON_XGXS_DSC_TRNSUM_Dr_fields, 4429 #else 4430 0, 4431 #endif 4432 #endif 4433 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4434 PHYMOD_SYMBOL_FLAG_REGISTER, 4435 "DSC_TRNSUM_Dr", 4436 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4437 "DSC_B_TRNSUM_D", 4438 NULL, 4439 #endif 4440 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4441 0x0, /* 0 */ 4442 0, 4443 #endif 4444 }, 4445 { 4446 BCMI_FALCON_XGXS_DSC_TRNSUM_LOr, 4447 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4448 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 4449 BCMI_FALCON_XGXS_DSC_TRNSUM_LOr_fields, 4450 #else 4451 0, 4452 #endif 4453 #endif 4454 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4455 PHYMOD_SYMBOL_FLAG_REGISTER, 4456 "DSC_TRNSUM_LOr", 4457 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4458 "DSC_B_TRNSUM_LOW", 4459 NULL, 4460 #endif 4461 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4462 0x0, /* 0 */ 4463 0, 4464 #endif 4465 }, 4466 { 4467 BCMI_FALCON_XGXS_DSC_TRNSUMr, 4468 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4469 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 4470 BCMI_FALCON_XGXS_DSC_TRNSUMr_fields, 4471 #else 4472 0, 4473 #endif 4474 #endif 4475 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4476 PHYMOD_SYMBOL_FLAG_REGISTER, 4477 "DSC_TRNSUMr", 4478 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4479 "DSC_B_TRNSUM", 4480 NULL, 4481 #endif 4482 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4483 0x0, /* 0 */ 4484 0, 4485 #endif 4486 }, 4487 { 4488 BCMI_FALCON_XGXS_DSC_DC_OFFS_STSr, 4489 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4490 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 4491 BCMI_FALCON_XGXS_DSC_DC_OFFS_STSr_fields, 4492 #else 4493 0, 4494 #endif 4495 #endif 4496 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4497 PHYMOD_SYMBOL_FLAG_REGISTER, 4498 "DSC_DC_OFFS_STSr", 4499 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4500 "DSC_B_DC_OFFSET_STATUS", 4501 NULL, 4502 #endif 4503 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4504 0x0, /* 0 */ 4505 0, 4506 #endif 4507 }, 4508 { 4509 BCMI_FALCON_XGXS_DSC_VGA_D_THR_STSr, 4510 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4511 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 4512 BCMI_FALCON_XGXS_DSC_VGA_D_THR_STSr_fields, 4513 #else 4514 0, 4515 #endif 4516 #endif 4517 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4518 PHYMOD_SYMBOL_FLAG_REGISTER, 4519 "DSC_VGA_D_THR_STSr", 4520 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4521 "DSC_B_VGA_D_THRESH_STATUS", 4522 NULL, 4523 #endif 4524 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4525 0x2700, /* 9984 */ 4526 0, 4527 #endif 4528 }, 4529 { 4530 BCMI_FALCON_XGXS_DSC_CDR_CTL0r, 4531 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4532 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 4533 BCMI_FALCON_XGXS_DSC_CDR_CTL0r_fields, 4534 #else 4535 0, 4536 #endif 4537 #endif 4538 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4539 PHYMOD_SYMBOL_FLAG_REGISTER, 4540 "DSC_CDR_CTL0r", 4541 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4542 "DSC_C_CDR_CONTROL_0", 4543 NULL, 4544 #endif 4545 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4546 0x9, /* 9 */ 4547 0, 4548 #endif 4549 }, 4550 { 4551 BCMI_FALCON_XGXS_DSC_CDR_CTL1r, 4552 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4553 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 4554 BCMI_FALCON_XGXS_DSC_CDR_CTL1r_fields, 4555 #else 4556 0, 4557 #endif 4558 #endif 4559 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4560 PHYMOD_SYMBOL_FLAG_REGISTER, 4561 "DSC_CDR_CTL1r", 4562 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4563 "DSC_C_CDR_CONTROL_1", 4564 NULL, 4565 #endif 4566 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4567 0x0, /* 0 */ 4568 0, 4569 #endif 4570 }, 4571 { 4572 BCMI_FALCON_XGXS_DSC_CDR_CTL2r, 4573 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4574 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 4575 BCMI_FALCON_XGXS_DSC_CDR_CTL2r_fields, 4576 #else 4577 0, 4578 #endif 4579 #endif 4580 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4581 PHYMOD_SYMBOL_FLAG_REGISTER, 4582 "DSC_CDR_CTL2r", 4583 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4584 "DSC_C_CDR_CONTROL_2", 4585 NULL, 4586 #endif 4587 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4588 0x80, /* 128 */ 4589 0, 4590 #endif 4591 }, 4592 { 4593 BCMI_FALCON_XGXS_DSC_RX_PI_CTLr, 4594 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4595 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 4596 BCMI_FALCON_XGXS_DSC_RX_PI_CTLr_fields, 4597 #else 4598 0, 4599 #endif 4600 #endif 4601 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4602 PHYMOD_SYMBOL_FLAG_REGISTER, 4603 "DSC_RX_PI_CTLr", 4604 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4605 "DSC_C_RX_PI_CONTROL", 4606 NULL, 4607 #endif 4608 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4609 0x0, /* 0 */ 4610 0, 4611 #endif 4612 }, 4613 { 4614 BCMI_FALCON_XGXS_DSC_TRNSUM_CTLr, 4615 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4616 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 4617 BCMI_FALCON_XGXS_DSC_TRNSUM_CTLr_fields, 4618 #else 4619 0, 4620 #endif 4621 #endif 4622 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4623 PHYMOD_SYMBOL_FLAG_REGISTER, 4624 "DSC_TRNSUM_CTLr", 4625 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4626 "DSC_C_TRNSUM_CONTROL", 4627 NULL, 4628 #endif 4629 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4630 0x0, /* 0 */ 4631 0, 4632 #endif 4633 }, 4634 { 4635 BCMI_FALCON_XGXS_DSC_TRNSUM_PAT_CTL1r, 4636 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4637 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 4638 BCMI_FALCON_XGXS_DSC_TRNSUM_PAT_CTL1r_fields, 4639 #else 4640 0, 4641 #endif 4642 #endif 4643 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4644 PHYMOD_SYMBOL_FLAG_REGISTER, 4645 "DSC_TRNSUM_PAT_CTL1r", 4646 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4647 "DSC_C_TRNSUM_PAT_CTRL_1", 4648 NULL, 4649 #endif 4650 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4651 0x0, /* 0 */ 4652 0, 4653 #endif 4654 }, 4655 { 4656 BCMI_FALCON_XGXS_DSC_TRNSUM_PAT_CTL2r, 4657 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4658 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 4659 BCMI_FALCON_XGXS_DSC_TRNSUM_PAT_CTL2r_fields, 4660 #else 4661 0, 4662 #endif 4663 #endif 4664 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4665 PHYMOD_SYMBOL_FLAG_REGISTER, 4666 "DSC_TRNSUM_PAT_CTL2r", 4667 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4668 "DSC_C_TRNSUM_PAT_CTRL_2", 4669 NULL, 4670 #endif 4671 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4672 0x0, /* 0 */ 4673 0, 4674 #endif 4675 }, 4676 { 4677 BCMI_FALCON_XGXS_DSC_TRNSUM_TAP_CTLr, 4678 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4679 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 4680 BCMI_FALCON_XGXS_DSC_TRNSUM_TAP_CTLr_fields, 4681 #else 4682 0, 4683 #endif 4684 #endif 4685 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4686 PHYMOD_SYMBOL_FLAG_REGISTER, 4687 "DSC_TRNSUM_TAP_CTLr", 4688 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4689 "DSC_C_TRNSUM_TAP_CTRL", 4690 NULL, 4691 #endif 4692 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4693 0x0, /* 0 */ 4694 0, 4695 #endif 4696 }, 4697 { 4698 BCMI_FALCON_XGXS_DSC_TRNSUM_TDT_CTLr, 4699 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4700 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 4701 BCMI_FALCON_XGXS_DSC_TRNSUM_TDT_CTLr_fields, 4702 #else 4703 0, 4704 #endif 4705 #endif 4706 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4707 PHYMOD_SYMBOL_FLAG_REGISTER, 4708 "DSC_TRNSUM_TDT_CTLr", 4709 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4710 "DSC_C_TRNSUM_TDT_CTL", 4711 NULL, 4712 #endif 4713 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4714 0x0, /* 0 */ 4715 0, 4716 #endif 4717 }, 4718 { 4719 BCMI_FALCON_XGXS_DSC_TRNSUM_MISCr, 4720 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4721 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 4722 BCMI_FALCON_XGXS_DSC_TRNSUM_MISCr_fields, 4723 #else 4724 0, 4725 #endif 4726 #endif 4727 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4728 PHYMOD_SYMBOL_FLAG_REGISTER, 4729 "DSC_TRNSUM_MISCr", 4730 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4731 "DSC_C_TRNSUM_MISC", 4732 NULL, 4733 #endif 4734 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4735 0x0, /* 0 */ 4736 0, 4737 #endif 4738 }, 4739 { 4740 BCMI_FALCON_XGXS_DSC_VGA_CTL1r, 4741 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4742 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 4743 BCMI_FALCON_XGXS_DSC_VGA_CTL1r_fields, 4744 #else 4745 0, 4746 #endif 4747 #endif 4748 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4749 PHYMOD_SYMBOL_FLAG_REGISTER, 4750 "DSC_VGA_CTL1r", 4751 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4752 "DSC_C_VGA_CTRL_1", 4753 NULL, 4754 #endif 4755 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4756 0x0, /* 0 */ 4757 0, 4758 #endif 4759 }, 4760 { 4761 BCMI_FALCON_XGXS_DSC_DATA_SLCR_THR_CTLr, 4762 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4763 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 4764 BCMI_FALCON_XGXS_DSC_DATA_SLCR_THR_CTLr_fields, 4765 #else 4766 0, 4767 #endif 4768 #endif 4769 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4770 PHYMOD_SYMBOL_FLAG_REGISTER, 4771 "DSC_DATA_SLCR_THR_CTLr", 4772 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4773 "DSC_C_DATA_SLICER_THRESH_CTRL", 4774 NULL, 4775 #endif 4776 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4777 0x0, /* 0 */ 4778 0, 4779 #endif 4780 }, 4781 { 4782 BCMI_FALCON_XGXS_DSC_DC_OFFS_CTLr, 4783 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4784 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 4785 BCMI_FALCON_XGXS_DSC_DC_OFFS_CTLr_fields, 4786 #else 4787 0, 4788 #endif 4789 #endif 4790 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4791 PHYMOD_SYMBOL_FLAG_REGISTER, 4792 "DSC_DC_OFFS_CTLr", 4793 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4794 "DSC_C_DC_OFFSET_CONTROL", 4795 NULL, 4796 #endif 4797 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4798 0x0, /* 0 */ 4799 0, 4800 #endif 4801 }, 4802 { 4803 BCMI_FALCON_XGXS_DSC_SM_CTL0r, 4804 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4805 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 4806 BCMI_FALCON_XGXS_DSC_SM_CTL0r_fields, 4807 #else 4808 0, 4809 #endif 4810 #endif 4811 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4812 PHYMOD_SYMBOL_FLAG_REGISTER, 4813 "DSC_SM_CTL0r", 4814 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4815 "DSC_D_DSC_SM_CTRL_0", 4816 NULL, 4817 #endif 4818 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4819 0x8, /* 8 */ 4820 0, 4821 #endif 4822 }, 4823 { 4824 BCMI_FALCON_XGXS_DSC_SM_CTL1r, 4825 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4826 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 4827 BCMI_FALCON_XGXS_DSC_SM_CTL1r_fields, 4828 #else 4829 0, 4830 #endif 4831 #endif 4832 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4833 PHYMOD_SYMBOL_FLAG_REGISTER, 4834 "DSC_SM_CTL1r", 4835 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4836 "DSC_D_DSC_SM_CTRL_1", 4837 NULL, 4838 #endif 4839 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4840 0x200, /* 512 */ 4841 0, 4842 #endif 4843 }, 4844 { 4845 BCMI_FALCON_XGXS_DSC_SM_CTL2r, 4846 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4847 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 4848 BCMI_FALCON_XGXS_DSC_SM_CTL2r_fields, 4849 #else 4850 0, 4851 #endif 4852 #endif 4853 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4854 PHYMOD_SYMBOL_FLAG_REGISTER, 4855 "DSC_SM_CTL2r", 4856 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4857 "DSC_D_DSC_SM_CTRL_2", 4858 NULL, 4859 #endif 4860 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4861 0x87, /* 135 */ 4862 0, 4863 #endif 4864 }, 4865 { 4866 BCMI_FALCON_XGXS_DSC_SM_CTL3r, 4867 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4868 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 4869 BCMI_FALCON_XGXS_DSC_SM_CTL3r_fields, 4870 #else 4871 0, 4872 #endif 4873 #endif 4874 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4875 PHYMOD_SYMBOL_FLAG_REGISTER, 4876 "DSC_SM_CTL3r", 4877 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4878 "DSC_D_DSC_SM_CTRL_3", 4879 NULL, 4880 #endif 4881 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4882 0x1c1e, /* 7198 */ 4883 0, 4884 #endif 4885 }, 4886 { 4887 BCMI_FALCON_XGXS_DSC_SM_CTL4r, 4888 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4889 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 4890 BCMI_FALCON_XGXS_DSC_SM_CTL4r_fields, 4891 #else 4892 0, 4893 #endif 4894 #endif 4895 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4896 PHYMOD_SYMBOL_FLAG_REGISTER, 4897 "DSC_SM_CTL4r", 4898 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4899 "DSC_D_DSC_SM_CTRL_4", 4900 NULL, 4901 #endif 4902 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4903 0x0, /* 0 */ 4904 0, 4905 #endif 4906 }, 4907 { 4908 BCMI_FALCON_XGXS_DSC_SM_CTL5r, 4909 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4910 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 4911 BCMI_FALCON_XGXS_DSC_SM_CTL5r_fields, 4912 #else 4913 0, 4914 #endif 4915 #endif 4916 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4917 PHYMOD_SYMBOL_FLAG_REGISTER, 4918 "DSC_SM_CTL5r", 4919 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4920 "DSC_D_DSC_SM_CTRL_5", 4921 NULL, 4922 #endif 4923 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4924 0x35ad, /* 13741 */ 4925 0, 4926 #endif 4927 }, 4928 { 4929 BCMI_FALCON_XGXS_DSC_SM_CTL6r, 4930 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4931 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 4932 BCMI_FALCON_XGXS_DSC_SM_CTL6r_fields, 4933 #else 4934 0, 4935 #endif 4936 #endif 4937 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4938 PHYMOD_SYMBOL_FLAG_REGISTER, 4939 "DSC_SM_CTL6r", 4940 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4941 "DSC_D_DSC_SM_CTRL_6", 4942 NULL, 4943 #endif 4944 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4945 0x340d, /* 13325 */ 4946 0, 4947 #endif 4948 }, 4949 { 4950 BCMI_FALCON_XGXS_DSC_SM_CTL7r, 4951 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4952 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 4953 BCMI_FALCON_XGXS_DSC_SM_CTL7r_fields, 4954 #else 4955 0, 4956 #endif 4957 #endif 4958 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4959 PHYMOD_SYMBOL_FLAG_REGISTER, 4960 "DSC_SM_CTL7r", 4961 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4962 "DSC_D_DSC_SM_CTRL_7", 4963 NULL, 4964 #endif 4965 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4966 0x0, /* 0 */ 4967 0, 4968 #endif 4969 }, 4970 { 4971 BCMI_FALCON_XGXS_DSC_SM_CTL8r, 4972 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4973 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 4974 BCMI_FALCON_XGXS_DSC_SM_CTL8r_fields, 4975 #else 4976 0, 4977 #endif 4978 #endif 4979 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4980 PHYMOD_SYMBOL_FLAG_REGISTER, 4981 "DSC_SM_CTL8r", 4982 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4983 "DSC_D_DSC_SM_CTRL_8", 4984 NULL, 4985 #endif 4986 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4987 0x11, /* 17 */ 4988 0, 4989 #endif 4990 }, 4991 { 4992 BCMI_FALCON_XGXS_DSC_SM_CTL9r, 4993 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4994 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 4995 BCMI_FALCON_XGXS_DSC_SM_CTL9r_fields, 4996 #else 4997 0, 4998 #endif 4999 #endif 5000 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5001 PHYMOD_SYMBOL_FLAG_REGISTER, 5002 "DSC_SM_CTL9r", 5003 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5004 "DSC_D_DSC_SM_CTRL_9", 5005 NULL, 5006 #endif 5007 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5008 0x0, /* 0 */ 5009 0, 5010 #endif 5011 }, 5012 { 5013 BCMI_FALCON_XGXS_DSC_SM_STS_DSC_LOCKr, 5014 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5015 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 5016 BCMI_FALCON_XGXS_DSC_SM_STS_DSC_LOCKr_fields, 5017 #else 5018 0, 5019 #endif 5020 #endif 5021 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5022 PHYMOD_SYMBOL_FLAG_REGISTER, 5023 "DSC_SM_STS_DSC_LOCKr", 5024 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5025 "DSC_D_DSC_SM_STATUS_DSC_LOCK", 5026 NULL, 5027 #endif 5028 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5029 0x0, /* 0 */ 5030 0, 5031 #endif 5032 }, 5033 { 5034 BCMI_FALCON_XGXS_DSC_SM_STS_DSC_ST_ONE_HOTr, 5035 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5036 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 5037 BCMI_FALCON_XGXS_DSC_SM_STS_DSC_ST_ONE_HOTr_fields, 5038 #else 5039 0, 5040 #endif 5041 #endif 5042 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5043 PHYMOD_SYMBOL_FLAG_REGISTER, 5044 "DSC_SM_STS_DSC_ST_ONE_HOTr", 5045 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5046 "DSC_D_DSC_SM_STATUS_DSC_STATE_ONE_HOT", 5047 NULL, 5048 #endif 5049 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5050 0x0, /* 0 */ 5051 0, 5052 #endif 5053 }, 5054 { 5055 BCMI_FALCON_XGXS_DSC_SM_STS_DSC_ST_EEE_ONE_HOTr, 5056 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5057 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 5058 BCMI_FALCON_XGXS_DSC_SM_STS_DSC_ST_EEE_ONE_HOTr_fields, 5059 #else 5060 0, 5061 #endif 5062 #endif 5063 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5064 PHYMOD_SYMBOL_FLAG_REGISTER, 5065 "DSC_SM_STS_DSC_ST_EEE_ONE_HOTr", 5066 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5067 "DSC_D_DSC_SM_STATUS_DSC_STATE_EEE_ONE_HOT", 5068 NULL, 5069 #endif 5070 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5071 0x0, /* 0 */ 5072 0, 5073 #endif 5074 }, 5075 { 5076 BCMI_FALCON_XGXS_DSC_SM_STS_RESTARTr, 5077 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5078 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 5079 BCMI_FALCON_XGXS_DSC_SM_STS_RESTARTr_fields, 5080 #else 5081 0, 5082 #endif 5083 #endif 5084 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5085 PHYMOD_SYMBOL_FLAG_REGISTER, 5086 "DSC_SM_STS_RESTARTr", 5087 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5088 "DSC_D_DSC_SM_STATUS_RESTART", 5089 NULL, 5090 #endif 5091 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5092 0x0, /* 0 */ 5093 0, 5094 #endif 5095 }, 5096 { 5097 BCMI_FALCON_XGXS_DSC_SM_STS_DSC_STr, 5098 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5099 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 5100 BCMI_FALCON_XGXS_DSC_SM_STS_DSC_STr_fields, 5101 #else 5102 0, 5103 #endif 5104 #endif 5105 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5106 PHYMOD_SYMBOL_FLAG_REGISTER, 5107 "DSC_SM_STS_DSC_STr", 5108 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5109 "DSC_D_DSC_SM_STATUS_DSC_STATE", 5110 NULL, 5111 #endif 5112 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5113 0x0, /* 0 */ 5114 0, 5115 #endif 5116 }, 5117 { 5118 BCMI_FALCON_XGXS_DSC_RX_PI_CNT_BIN_PDr, 5119 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5120 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 5121 BCMI_FALCON_XGXS_DSC_RX_PI_CNT_BIN_PDr_fields, 5122 #else 5123 0, 5124 #endif 5125 #endif 5126 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5127 PHYMOD_SYMBOL_FLAG_REGISTER, 5128 "DSC_RX_PI_CNT_BIN_PDr", 5129 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5130 "DSC_E_RX_PI_CNT_BIN_PD", 5131 NULL, 5132 #endif 5133 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5134 0x0, /* 0 */ 5135 0, 5136 #endif 5137 }, 5138 { 5139 BCMI_FALCON_XGXS_DSC_RX_PI_CNT_BIN_LDr, 5140 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5141 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 5142 BCMI_FALCON_XGXS_DSC_RX_PI_CNT_BIN_LDr_fields, 5143 #else 5144 0, 5145 #endif 5146 #endif 5147 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5148 PHYMOD_SYMBOL_FLAG_REGISTER, 5149 "DSC_RX_PI_CNT_BIN_LDr", 5150 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5151 "DSC_E_RX_PI_CNT_BIN_LD", 5152 NULL, 5153 #endif 5154 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5155 0x0, /* 0 */ 5156 0, 5157 #endif 5158 }, 5159 { 5160 BCMI_FALCON_XGXS_DSC_RX_DATA_15_TO0r, 5161 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5162 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 5163 BCMI_FALCON_XGXS_DSC_RX_DATA_15_TO0r_fields, 5164 #else 5165 0, 5166 #endif 5167 #endif 5168 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5169 PHYMOD_SYMBOL_FLAG_REGISTER, 5170 "DSC_RX_DATA_15_TO0r", 5171 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5172 "DSC_E_RX_DATA_15_TO_0", 5173 NULL, 5174 #endif 5175 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5176 0x0, /* 0 */ 5177 0, 5178 #endif 5179 }, 5180 { 5181 BCMI_FALCON_XGXS_DSC_RX_DATA_35_TO_20r, 5182 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5183 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 5184 BCMI_FALCON_XGXS_DSC_RX_DATA_35_TO_20r_fields, 5185 #else 5186 0, 5187 #endif 5188 #endif 5189 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5190 PHYMOD_SYMBOL_FLAG_REGISTER, 5191 "DSC_RX_DATA_35_TO_20r", 5192 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5193 "DSC_E_RX_DATA_35_TO_20", 5194 NULL, 5195 #endif 5196 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5197 0x0, /* 0 */ 5198 0, 5199 #endif 5200 }, 5201 { 5202 BCMI_FALCON_XGXS_DSC_CDR_STS_PHASE_ERRr, 5203 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5204 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 5205 BCMI_FALCON_XGXS_DSC_CDR_STS_PHASE_ERRr_fields, 5206 #else 5207 0, 5208 #endif 5209 #endif 5210 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5211 PHYMOD_SYMBOL_FLAG_REGISTER, 5212 "DSC_CDR_STS_PHASE_ERRr", 5213 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5214 "DSC_E_CDR_STATUS_PHASE_ERROR", 5215 NULL, 5216 #endif 5217 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5218 0x0, /* 0 */ 5219 0, 5220 #endif 5221 }, 5222 { 5223 BCMI_FALCON_XGXS_DSC_RX_PI_CNT_BIN_Dr, 5224 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5225 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 5226 BCMI_FALCON_XGXS_DSC_RX_PI_CNT_BIN_Dr_fields, 5227 #else 5228 0, 5229 #endif 5230 #endif 5231 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5232 PHYMOD_SYMBOL_FLAG_REGISTER, 5233 "DSC_RX_PI_CNT_BIN_Dr", 5234 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5235 "DSC_E_RX_PI_CNT_BIN_D", 5236 NULL, 5237 #endif 5238 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5239 0x0, /* 0 */ 5240 0, 5241 #endif 5242 }, 5243 { 5244 BCMI_FALCON_XGXS_DSC_RX_PI_CNT_BIN_Pr, 5245 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5246 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 5247 BCMI_FALCON_XGXS_DSC_RX_PI_CNT_BIN_Pr_fields, 5248 #else 5249 0, 5250 #endif 5251 #endif 5252 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5253 PHYMOD_SYMBOL_FLAG_REGISTER, 5254 "DSC_RX_PI_CNT_BIN_Pr", 5255 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5256 "DSC_E_RX_PI_CNT_BIN_P", 5257 NULL, 5258 #endif 5259 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5260 0x0, /* 0 */ 5261 0, 5262 #endif 5263 }, 5264 { 5265 BCMI_FALCON_XGXS_DSC_RX_PI_CNT_BIN_Lr, 5266 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5267 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 5268 BCMI_FALCON_XGXS_DSC_RX_PI_CNT_BIN_Lr_fields, 5269 #else 5270 0, 5271 #endif 5272 #endif 5273 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5274 PHYMOD_SYMBOL_FLAG_REGISTER, 5275 "DSC_RX_PI_CNT_BIN_Lr", 5276 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5277 "DSC_E_RX_PI_CNT_BIN_L", 5278 NULL, 5279 #endif 5280 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5281 0x0, /* 0 */ 5282 0, 5283 #endif 5284 }, 5285 { 5286 BCMI_FALCON_XGXS_DSC_CDR_STS_INTEGr, 5287 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5288 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 5289 BCMI_FALCON_XGXS_DSC_CDR_STS_INTEGr_fields, 5290 #else 5291 0, 5292 #endif 5293 #endif 5294 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5295 PHYMOD_SYMBOL_FLAG_REGISTER, 5296 "DSC_CDR_STS_INTEGr", 5297 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5298 "DSC_E_CDR_STATUS_INTEG_REG", 5299 NULL, 5300 #endif 5301 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5302 0x0, /* 0 */ 5303 0, 5304 #endif 5305 }, 5306 { 5307 BCMI_FALCON_XGXS_DSC_CDR_STS_MISCr, 5308 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5309 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 5310 BCMI_FALCON_XGXS_DSC_CDR_STS_MISCr_fields, 5311 #else 5312 0, 5313 #endif 5314 #endif 5315 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5316 PHYMOD_SYMBOL_FLAG_REGISTER, 5317 "DSC_CDR_STS_MISCr", 5318 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5319 "DSC_E_CDR_STATUS_MISC", 5320 NULL, 5321 #endif 5322 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5323 0x1, /* 1 */ 5324 0, 5325 #endif 5326 }, 5327 { 5328 BCMI_FALCON_XGXS_DSC_CDR_1G_STSr, 5329 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5330 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 5331 BCMI_FALCON_XGXS_DSC_CDR_1G_STSr_fields, 5332 #else 5333 0, 5334 #endif 5335 #endif 5336 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5337 PHYMOD_SYMBOL_FLAG_REGISTER, 5338 "DSC_CDR_1G_STSr", 5339 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5340 "DSC_E_CDR_1G_STATUS", 5341 NULL, 5342 #endif 5343 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5344 0x0, /* 0 */ 5345 0, 5346 #endif 5347 }, 5348 { 5349 BCMI_FALCON_XGXS_DSC_PRESETr, 5350 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5351 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 5352 BCMI_FALCON_XGXS_DSC_PRESETr_fields, 5353 #else 5354 0, 5355 #endif 5356 #endif 5357 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5358 PHYMOD_SYMBOL_FLAG_REGISTER, 5359 "DSC_PRESETr", 5360 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5361 "DSC_E_PRESET_REG", 5362 NULL, 5363 #endif 5364 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5365 0x0, /* 0 */ 5366 0, 5367 #endif 5368 }, 5369 { 5370 BCMI_FALCON_XGXS_CL93N72_UR_CTL0r, 5371 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5372 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 5373 BCMI_FALCON_XGXS_CL93N72_UR_CTL0r_fields, 5374 #else 5375 0, 5376 #endif 5377 #endif 5378 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5379 PHYMOD_SYMBOL_FLAG_REGISTER, 5380 "CL93N72_UR_CTL0r", 5381 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5382 "CL93N72_USER_RX_CL93N72UR_CONTROL0_REGISTER", 5383 NULL, 5384 #endif 5385 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5386 0x4, /* 4 */ 5387 0, 5388 #endif 5389 }, 5390 { 5391 BCMI_FALCON_XGXS_CL93N72_UR_CTL1r, 5392 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5393 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 5394 BCMI_FALCON_XGXS_CL93N72_UR_CTL1r_fields, 5395 #else 5396 0, 5397 #endif 5398 #endif 5399 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5400 PHYMOD_SYMBOL_FLAG_REGISTER, 5401 "CL93N72_UR_CTL1r", 5402 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5403 "CL93N72_USER_RX_CL93N72UR_CONTROL1_REGISTER", 5404 NULL, 5405 #endif 5406 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5407 0x52, /* 82 */ 5408 0, 5409 #endif 5410 }, 5411 { 5412 BCMI_FALCON_XGXS_CL93N72_UR_CTL2r, 5413 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5414 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 5415 BCMI_FALCON_XGXS_CL93N72_UR_CTL2r_fields, 5416 #else 5417 0, 5418 #endif 5419 #endif 5420 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5421 PHYMOD_SYMBOL_FLAG_REGISTER, 5422 "CL93N72_UR_CTL2r", 5423 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5424 "CL93N72_USER_RX_CL93N72UR_CONTROL2_REGISTER", 5425 NULL, 5426 #endif 5427 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5428 0x310, /* 784 */ 5429 0, 5430 #endif 5431 }, 5432 { 5433 BCMI_FALCON_XGXS_CL93N72_UR_STS0r, 5434 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5435 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 5436 BCMI_FALCON_XGXS_CL93N72_UR_STS0r_fields, 5437 #else 5438 0, 5439 #endif 5440 #endif 5441 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5442 PHYMOD_SYMBOL_FLAG_REGISTER, 5443 "CL93N72_UR_STS0r", 5444 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5445 "CL93N72_USER_RX_CL93N72UR_STATUS0_REGISTER", 5446 NULL, 5447 #endif 5448 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5449 0x0, /* 0 */ 5450 0, 5451 #endif 5452 }, 5453 { 5454 BCMI_FALCON_XGXS_CL93N72_UR_UC_INTR_CTL0r, 5455 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5456 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 5457 BCMI_FALCON_XGXS_CL93N72_UR_UC_INTR_CTL0r_fields, 5458 #else 5459 0, 5460 #endif 5461 #endif 5462 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5463 PHYMOD_SYMBOL_FLAG_REGISTER, 5464 "CL93N72_UR_UC_INTR_CTL0r", 5465 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5466 "CL93N72_USER_RX_CL93N72UR_MICRO_INTERRUPT_CONTROL0_REGISTER", 5467 NULL, 5468 #endif 5469 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5470 0x0, /* 0 */ 5471 0, 5472 #endif 5473 }, 5474 { 5475 BCMI_FALCON_XGXS_CL93N72_UR_UC_STS0r, 5476 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5477 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 5478 BCMI_FALCON_XGXS_CL93N72_UR_UC_STS0r_fields, 5479 #else 5480 0, 5481 #endif 5482 #endif 5483 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5484 PHYMOD_SYMBOL_FLAG_REGISTER, 5485 "CL93N72_UR_UC_STS0r", 5486 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5487 "CL93N72_USER_RX_CL93N72UR_MICRO_STATUS0_REGISTER", 5488 NULL, 5489 #endif 5490 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5491 0x0, /* 0 */ 5492 0, 5493 #endif 5494 }, 5495 { 5496 BCMI_FALCON_XGXS_CL93N72_UR_UC_STS1r, 5497 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5498 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 5499 BCMI_FALCON_XGXS_CL93N72_UR_UC_STS1r_fields, 5500 #else 5501 0, 5502 #endif 5503 #endif 5504 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5505 PHYMOD_SYMBOL_FLAG_REGISTER, 5506 "CL93N72_UR_UC_STS1r", 5507 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5508 "CL93N72_USER_RX_CL93N72UR_MICRO_STATUS1_REGISTER", 5509 NULL, 5510 #endif 5511 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5512 0x0, /* 0 */ 5513 0, 5514 #endif 5515 }, 5516 { 5517 BCMI_FALCON_XGXS_CL93N72_UT_XMT_UPD_PAGEr, 5518 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5519 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 5520 BCMI_FALCON_XGXS_CL93N72_UT_XMT_UPD_PAGEr_fields, 5521 #else 5522 0, 5523 #endif 5524 #endif 5525 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5526 PHYMOD_SYMBOL_FLAG_REGISTER, 5527 "CL93N72_UT_XMT_UPD_PAGEr", 5528 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5529 "CL93N72_USER_TX_CL93N72UT_XMT_UPDATE_PAGE_REGISTER", 5530 NULL, 5531 #endif 5532 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5533 0x0, /* 0 */ 5534 0, 5535 #endif 5536 }, 5537 { 5538 BCMI_FALCON_XGXS_CL93N72_UT_LD_XMT_STS_PAGEr, 5539 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5540 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 5541 BCMI_FALCON_XGXS_CL93N72_UT_LD_XMT_STS_PAGEr_fields, 5542 #else 5543 0, 5544 #endif 5545 #endif 5546 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5547 PHYMOD_SYMBOL_FLAG_REGISTER, 5548 "CL93N72_UT_LD_XMT_STS_PAGEr", 5549 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5550 "CL93N72_USER_TX_CL93N72UT_LD_XMT_STATUS_PAGE", 5551 NULL, 5552 #endif 5553 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5554 0x0, /* 0 */ 5555 0, 5556 #endif 5557 }, 5558 { 5559 BCMI_FALCON_XGXS_CL93N72_UT_CTL0r, 5560 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5561 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 5562 BCMI_FALCON_XGXS_CL93N72_UT_CTL0r_fields, 5563 #else 5564 0, 5565 #endif 5566 #endif 5567 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5568 PHYMOD_SYMBOL_FLAG_REGISTER, 5569 "CL93N72_UT_CTL0r", 5570 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5571 "CL93N72_USER_TX_CL93N72UT_CONTROL0_REGISTER", 5572 NULL, 5573 #endif 5574 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5575 0x0, /* 0 */ 5576 0, 5577 #endif 5578 }, 5579 { 5580 BCMI_FALCON_XGXS_CL93N72_UT_CTL1r, 5581 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5582 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 5583 BCMI_FALCON_XGXS_CL93N72_UT_CTL1r_fields, 5584 #else 5585 0, 5586 #endif 5587 #endif 5588 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5589 PHYMOD_SYMBOL_FLAG_REGISTER, 5590 "CL93N72_UT_CTL1r", 5591 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5592 "CL93N72_USER_TX_CL93N72UT_CONTROL1_REGISTER", 5593 NULL, 5594 #endif 5595 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5596 0x4, /* 4 */ 5597 0, 5598 #endif 5599 }, 5600 { 5601 BCMI_FALCON_XGXS_CL93N72_UT_CTL2r, 5602 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5603 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 5604 BCMI_FALCON_XGXS_CL93N72_UT_CTL2r_fields, 5605 #else 5606 0, 5607 #endif 5608 #endif 5609 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5610 PHYMOD_SYMBOL_FLAG_REGISTER, 5611 "CL93N72_UT_CTL2r", 5612 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5613 "CL93N72_USER_TX_CL93N72UT_CONTROL2_REGISTER", 5614 NULL, 5615 #endif 5616 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5617 0x2c08, /* 11272 */ 5618 0, 5619 #endif 5620 }, 5621 { 5622 BCMI_FALCON_XGXS_CL93N72_UT_CTL3r, 5623 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5624 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 5625 BCMI_FALCON_XGXS_CL93N72_UT_CTL3r_fields, 5626 #else 5627 0, 5628 #endif 5629 #endif 5630 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5631 PHYMOD_SYMBOL_FLAG_REGISTER, 5632 "CL93N72_UT_CTL3r", 5633 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5634 "CL93N72_USER_TX_CL93N72UT_CONTROL3_REGISTER", 5635 NULL, 5636 #endif 5637 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5638 0x3c, /* 60 */ 5639 0, 5640 #endif 5641 }, 5642 { 5643 BCMI_FALCON_XGXS_CL93N72_UT_STS0r, 5644 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5645 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 5646 BCMI_FALCON_XGXS_CL93N72_UT_STS0r_fields, 5647 #else 5648 0, 5649 #endif 5650 #endif 5651 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5652 PHYMOD_SYMBOL_FLAG_REGISTER, 5653 "CL93N72_UT_STS0r", 5654 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5655 "CL93N72_USER_TX_CL93N72UT_STATUS0_REGISTER", 5656 NULL, 5657 #endif 5658 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5659 0x0, /* 0 */ 5660 0, 5661 #endif 5662 }, 5663 { 5664 BCMI_FALCON_XGXS_TX_PI_PMD_CTL0r, 5665 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5666 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 5667 BCMI_FALCON_XGXS_TX_PI_PMD_CTL0r_fields, 5668 #else 5669 0, 5670 #endif 5671 #endif 5672 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5673 PHYMOD_SYMBOL_FLAG_REGISTER, 5674 "TX_PI_PMD_CTL0r", 5675 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5676 "TX_PI_PMD_COM_CONTROL_0", 5677 NULL, 5678 #endif 5679 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5680 0x7000, /* 28672 */ 5681 0, 5682 #endif 5683 }, 5684 { 5685 BCMI_FALCON_XGXS_TX_PI_PMD_CTL1r, 5686 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5687 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 5688 BCMI_FALCON_XGXS_TX_PI_PMD_CTL1r_fields, 5689 #else 5690 0, 5691 #endif 5692 #endif 5693 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5694 PHYMOD_SYMBOL_FLAG_REGISTER, 5695 "TX_PI_PMD_CTL1r", 5696 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5697 "TX_PI_PMD_COM_CONTROL_1", 5698 NULL, 5699 #endif 5700 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5701 0x0, /* 0 */ 5702 0, 5703 #endif 5704 }, 5705 { 5706 BCMI_FALCON_XGXS_TX_PI_PMD_CTL2r, 5707 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5708 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 5709 BCMI_FALCON_XGXS_TX_PI_PMD_CTL2r_fields, 5710 #else 5711 0, 5712 #endif 5713 #endif 5714 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5715 PHYMOD_SYMBOL_FLAG_REGISTER, 5716 "TX_PI_PMD_CTL2r", 5717 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5718 "TX_PI_PMD_COM_CONTROL_2", 5719 NULL, 5720 #endif 5721 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5722 0x0, /* 0 */ 5723 0, 5724 #endif 5725 }, 5726 { 5727 BCMI_FALCON_XGXS_TX_PI_PMD_CTL3r, 5728 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5729 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 5730 BCMI_FALCON_XGXS_TX_PI_PMD_CTL3r_fields, 5731 #else 5732 0, 5733 #endif 5734 #endif 5735 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5736 PHYMOD_SYMBOL_FLAG_REGISTER, 5737 "TX_PI_PMD_CTL3r", 5738 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5739 "TX_PI_PMD_COM_CONTROL_3", 5740 NULL, 5741 #endif 5742 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5743 0x100, /* 256 */ 5744 0, 5745 #endif 5746 }, 5747 { 5748 BCMI_FALCON_XGXS_TX_PI_PMD_CTL4r, 5749 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5750 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 5751 BCMI_FALCON_XGXS_TX_PI_PMD_CTL4r_fields, 5752 #else 5753 0, 5754 #endif 5755 #endif 5756 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5757 PHYMOD_SYMBOL_FLAG_REGISTER, 5758 "TX_PI_PMD_CTL4r", 5759 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5760 "TX_PI_PMD_COM_CONTROL_4", 5761 NULL, 5762 #endif 5763 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5764 0x4, /* 4 */ 5765 0, 5766 #endif 5767 }, 5768 { 5769 BCMI_FALCON_XGXS_TX_PI_PMD_STS0r, 5770 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5771 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 5772 BCMI_FALCON_XGXS_TX_PI_PMD_STS0r_fields, 5773 #else 5774 0, 5775 #endif 5776 #endif 5777 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5778 PHYMOD_SYMBOL_FLAG_REGISTER, 5779 "TX_PI_PMD_STS0r", 5780 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5781 "TX_PI_PMD_COM_STATUS_0", 5782 NULL, 5783 #endif 5784 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5785 0x0, /* 0 */ 5786 0, 5787 #endif 5788 }, 5789 { 5790 BCMI_FALCON_XGXS_TX_PI_PMD_STS1r, 5791 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5792 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 5793 BCMI_FALCON_XGXS_TX_PI_PMD_STS1r_fields, 5794 #else 5795 0, 5796 #endif 5797 #endif 5798 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5799 PHYMOD_SYMBOL_FLAG_REGISTER, 5800 "TX_PI_PMD_STS1r", 5801 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5802 "TX_PI_PMD_COM_STATUS_1", 5803 NULL, 5804 #endif 5805 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5806 0x0, /* 0 */ 5807 0, 5808 #endif 5809 }, 5810 { 5811 BCMI_FALCON_XGXS_TX_PI_PMD_STS2r, 5812 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5813 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 5814 BCMI_FALCON_XGXS_TX_PI_PMD_STS2r_fields, 5815 #else 5816 0, 5817 #endif 5818 #endif 5819 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5820 PHYMOD_SYMBOL_FLAG_REGISTER, 5821 "TX_PI_PMD_STS2r", 5822 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5823 "TX_PI_PMD_COM_STATUS_2", 5824 NULL, 5825 #endif 5826 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5827 0x0, /* 0 */ 5828 0, 5829 #endif 5830 }, 5831 { 5832 BCMI_FALCON_XGXS_TX_PI_PMD_STS3r, 5833 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5834 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 5835 BCMI_FALCON_XGXS_TX_PI_PMD_STS3r_fields, 5836 #else 5837 0, 5838 #endif 5839 #endif 5840 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5841 PHYMOD_SYMBOL_FLAG_REGISTER, 5842 "TX_PI_PMD_STS3r", 5843 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5844 "TX_PI_PMD_COM_STATUS_3", 5845 NULL, 5846 #endif 5847 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5848 0x0, /* 0 */ 5849 0, 5850 #endif 5851 }, 5852 { 5853 BCMI_FALCON_XGXS_CKRST_OSR_MODE_CTLr, 5854 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5855 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 5856 BCMI_FALCON_XGXS_CKRST_OSR_MODE_CTLr_fields, 5857 #else 5858 0, 5859 #endif 5860 #endif 5861 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5862 PHYMOD_SYMBOL_FLAG_REGISTER, 5863 "CKRST_OSR_MODE_CTLr", 5864 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5865 "CKRST_CTRL_PMD_OSR_MODE_CONTROL", 5866 NULL, 5867 #endif 5868 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5869 0x0, /* 0 */ 5870 0, 5871 #endif 5872 }, 5873 { 5874 BCMI_FALCON_XGXS_CKRST_LN_CLK_RST_N_PWRDWN_CTLr, 5875 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5876 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 5877 BCMI_FALCON_XGXS_CKRST_LN_CLK_RST_N_PWRDWN_CTLr_fields, 5878 #else 5879 0, 5880 #endif 5881 #endif 5882 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5883 PHYMOD_SYMBOL_FLAG_REGISTER, 5884 "CKRST_LN_CLK_RST_N_PWRDWN_CTLr", 5885 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5886 "CKRST_CTRL_PMD_LANE_CLK_RESET_N_POWERDOWN_CONTROL", 5887 NULL, 5888 #endif 5889 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5890 0x0, /* 0 */ 5891 0, 5892 #endif 5893 }, 5894 { 5895 BCMI_FALCON_XGXS_CKRST_LN_AFE_RST_PWRDWN_CTLr, 5896 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5897 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 5898 BCMI_FALCON_XGXS_CKRST_LN_AFE_RST_PWRDWN_CTLr_fields, 5899 #else 5900 0, 5901 #endif 5902 #endif 5903 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5904 PHYMOD_SYMBOL_FLAG_REGISTER, 5905 "CKRST_LN_AFE_RST_PWRDWN_CTLr", 5906 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5907 "CKRST_CTRL_PMD_LANE_AFE_RESET_PWRDWN_CONTROL", 5908 NULL, 5909 #endif 5910 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5911 0x0, /* 0 */ 5912 0, 5913 #endif 5914 }, 5915 { 5916 BCMI_FALCON_XGXS_CKRST_LN_RST_N_PWRDN_PIN_KILL_CTLr, 5917 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5918 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 5919 BCMI_FALCON_XGXS_CKRST_LN_RST_N_PWRDN_PIN_KILL_CTLr_fields, 5920 #else 5921 0, 5922 #endif 5923 #endif 5924 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5925 PHYMOD_SYMBOL_FLAG_REGISTER, 5926 "CKRST_LN_RST_N_PWRDN_PIN_KILL_CTLr", 5927 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5928 "CKRST_CTRL_PMD_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL", 5929 NULL, 5930 #endif 5931 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5932 0x0, /* 0 */ 5933 0, 5934 #endif 5935 }, 5936 { 5937 BCMI_FALCON_XGXS_CKRST_LN_DBG_RST_CTLr, 5938 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5939 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 5940 BCMI_FALCON_XGXS_CKRST_LN_DBG_RST_CTLr_fields, 5941 #else 5942 0, 5943 #endif 5944 #endif 5945 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5946 PHYMOD_SYMBOL_FLAG_REGISTER, 5947 "CKRST_LN_DBG_RST_CTLr", 5948 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5949 "CKRST_CTRL_PMD_LANE_DEBUG_RESET_CONTROL", 5950 NULL, 5951 #endif 5952 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5953 0x303, /* 771 */ 5954 0, 5955 #endif 5956 }, 5957 { 5958 BCMI_FALCON_XGXS_CKRST_UC_ACK_LN_CTLr, 5959 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5960 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 5961 BCMI_FALCON_XGXS_CKRST_UC_ACK_LN_CTLr_fields, 5962 #else 5963 0, 5964 #endif 5965 #endif 5966 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5967 PHYMOD_SYMBOL_FLAG_REGISTER, 5968 "CKRST_UC_ACK_LN_CTLr", 5969 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5970 "CKRST_CTRL_PMD_UC_ACK_LANE_CONTROL", 5971 NULL, 5972 #endif 5973 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5974 0x0, /* 0 */ 5975 0, 5976 #endif 5977 }, 5978 { 5979 BCMI_FALCON_XGXS_CKRST_LN_RST_OCC_CTLr, 5980 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5981 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 5982 BCMI_FALCON_XGXS_CKRST_LN_RST_OCC_CTLr_fields, 5983 #else 5984 0, 5985 #endif 5986 #endif 5987 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5988 PHYMOD_SYMBOL_FLAG_REGISTER, 5989 "CKRST_LN_RST_OCC_CTLr", 5990 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5991 "CKRST_CTRL_PMD_LANE_REG_RESET_OCCURRED_CONTROL", 5992 NULL, 5993 #endif 5994 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5995 0x1, /* 1 */ 5996 0, 5997 #endif 5998 }, 5999 { 6000 BCMI_FALCON_XGXS_CKRST_CLK_N_RST_DBG_CTLr, 6001 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6002 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 6003 BCMI_FALCON_XGXS_CKRST_CLK_N_RST_DBG_CTLr_fields, 6004 #else 6005 0, 6006 #endif 6007 #endif 6008 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6009 PHYMOD_SYMBOL_FLAG_REGISTER, 6010 "CKRST_CLK_N_RST_DBG_CTLr", 6011 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6012 "CKRST_CTRL_PMD_CLOCK_N_RESET_DEBUG_CONTROL", 6013 NULL, 6014 #endif 6015 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6016 0x0, /* 0 */ 6017 0, 6018 #endif 6019 }, 6020 { 6021 BCMI_FALCON_XGXS_CKRST_PMD_LN_MODE_STSr, 6022 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6023 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 6024 BCMI_FALCON_XGXS_CKRST_PMD_LN_MODE_STSr_fields, 6025 #else 6026 0, 6027 #endif 6028 #endif 6029 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6030 PHYMOD_SYMBOL_FLAG_REGISTER, 6031 "CKRST_PMD_LN_MODE_STSr", 6032 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6033 "CKRST_CTRL_PMD_PMD_LANE_MODE_STATUS", 6034 NULL, 6035 #endif 6036 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6037 0x0, /* 0 */ 6038 0, 6039 #endif 6040 }, 6041 { 6042 BCMI_FALCON_XGXS_CKRST_LN_DP_RST_ST_STSr, 6043 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6044 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 6045 BCMI_FALCON_XGXS_CKRST_LN_DP_RST_ST_STSr_fields, 6046 #else 6047 0, 6048 #endif 6049 #endif 6050 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6051 PHYMOD_SYMBOL_FLAG_REGISTER, 6052 "CKRST_LN_DP_RST_ST_STSr", 6053 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6054 "CKRST_CTRL_PMD_LANE_DP_RESET_STATE_STATUS", 6055 NULL, 6056 #endif 6057 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6058 0x7, /* 7 */ 6059 0, 6060 #endif 6061 }, 6062 { 6063 BCMI_FALCON_XGXS_CKRST_LN_MASKr, 6064 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6065 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 6066 BCMI_FALCON_XGXS_CKRST_LN_MASKr_fields, 6067 #else 6068 0, 6069 #endif 6070 #endif 6071 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6072 PHYMOD_SYMBOL_FLAG_REGISTER, 6073 "CKRST_LN_MASKr", 6074 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6075 "CKRST_CTRL_PMD_LN_MASK", 6076 NULL, 6077 #endif 6078 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6079 0x0, /* 0 */ 6080 0, 6081 #endif 6082 }, 6083 { 6084 BCMI_FALCON_XGXS_CKRST_OSR_MODE_STSr, 6085 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6086 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 6087 BCMI_FALCON_XGXS_CKRST_OSR_MODE_STSr_fields, 6088 #else 6089 0, 6090 #endif 6091 #endif 6092 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6093 PHYMOD_SYMBOL_FLAG_REGISTER, 6094 "CKRST_OSR_MODE_STSr", 6095 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6096 "CKRST_CTRL_PMD_OSR_MODE_STATUS", 6097 NULL, 6098 #endif 6099 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6100 0x0, /* 0 */ 6101 0, 6102 #endif 6103 }, 6104 { 6105 BCMI_FALCON_XGXS_CKRST_OSR_MODE_PIN_STSr, 6106 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6107 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 6108 BCMI_FALCON_XGXS_CKRST_OSR_MODE_PIN_STSr_fields, 6109 #else 6110 0, 6111 #endif 6112 #endif 6113 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6114 PHYMOD_SYMBOL_FLAG_REGISTER, 6115 "CKRST_OSR_MODE_PIN_STSr", 6116 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6117 "CKRST_CTRL_PMD_OSR_MODE_PIN_STATUS", 6118 NULL, 6119 #endif 6120 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6121 0x0, /* 0 */ 6122 0, 6123 #endif 6124 }, 6125 { 6126 BCMI_FALCON_XGXS_CKRST_LN_S_RSTB_CTLr, 6127 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6128 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 6129 BCMI_FALCON_XGXS_CKRST_LN_S_RSTB_CTLr_fields, 6130 #else 6131 0, 6132 #endif 6133 #endif 6134 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6135 PHYMOD_SYMBOL_FLAG_REGISTER, 6136 "CKRST_LN_S_RSTB_CTLr", 6137 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6138 "CKRST_CTRL_PMD_LN_S_RSTB_CONTROL", 6139 NULL, 6140 #endif 6141 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6142 0x1, /* 1 */ 6143 0, 6144 #endif 6145 }, 6146 { 6147 BCMI_FALCON_XGXS_AMS_RX_CTL0r, 6148 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6149 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 6150 BCMI_FALCON_XGXS_AMS_RX_CTL0r_fields, 6151 #else 6152 0, 6153 #endif 6154 #endif 6155 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6156 PHYMOD_SYMBOL_FLAG_REGISTER, 6157 "AMS_RX_CTL0r", 6158 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6159 "AMS_RX_CONTROL_0", 6160 NULL, 6161 #endif 6162 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6163 0x10, /* 16 */ 6164 0, 6165 #endif 6166 }, 6167 { 6168 BCMI_FALCON_XGXS_AMS_RX_CTL1r, 6169 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6170 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 6171 BCMI_FALCON_XGXS_AMS_RX_CTL1r_fields, 6172 #else 6173 0, 6174 #endif 6175 #endif 6176 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6177 PHYMOD_SYMBOL_FLAG_REGISTER, 6178 "AMS_RX_CTL1r", 6179 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6180 "AMS_RX_CONTROL_1", 6181 NULL, 6182 #endif 6183 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6184 0x0, /* 0 */ 6185 0, 6186 #endif 6187 }, 6188 { 6189 BCMI_FALCON_XGXS_AMS_RX_CTL2r, 6190 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6191 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 6192 BCMI_FALCON_XGXS_AMS_RX_CTL2r_fields, 6193 #else 6194 0, 6195 #endif 6196 #endif 6197 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6198 PHYMOD_SYMBOL_FLAG_REGISTER, 6199 "AMS_RX_CTL2r", 6200 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6201 "AMS_RX_CONTROL_2", 6202 NULL, 6203 #endif 6204 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6205 0xe00, /* 3584 */ 6206 0, 6207 #endif 6208 }, 6209 { 6210 BCMI_FALCON_XGXS_AMS_RX_CTL3r, 6211 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6212 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 6213 BCMI_FALCON_XGXS_AMS_RX_CTL3r_fields, 6214 #else 6215 0, 6216 #endif 6217 #endif 6218 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6219 PHYMOD_SYMBOL_FLAG_REGISTER, 6220 "AMS_RX_CTL3r", 6221 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6222 "AMS_RX_CONTROL_3", 6223 NULL, 6224 #endif 6225 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6226 0x0, /* 0 */ 6227 0, 6228 #endif 6229 }, 6230 { 6231 BCMI_FALCON_XGXS_AMS_RX_CTL4r, 6232 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6233 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 6234 BCMI_FALCON_XGXS_AMS_RX_CTL4r_fields, 6235 #else 6236 0, 6237 #endif 6238 #endif 6239 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6240 PHYMOD_SYMBOL_FLAG_REGISTER, 6241 "AMS_RX_CTL4r", 6242 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6243 "AMS_RX_CONTROL_4", 6244 NULL, 6245 #endif 6246 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6247 0x0, /* 0 */ 6248 0, 6249 #endif 6250 }, 6251 { 6252 BCMI_FALCON_XGXS_AMS_RX_CTL5r, 6253 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6254 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 6255 BCMI_FALCON_XGXS_AMS_RX_CTL5r_fields, 6256 #else 6257 0, 6258 #endif 6259 #endif 6260 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6261 PHYMOD_SYMBOL_FLAG_REGISTER, 6262 "AMS_RX_CTL5r", 6263 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6264 "AMS_RX_CONTROL_5", 6265 NULL, 6266 #endif 6267 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6268 0x0, /* 0 */ 6269 0, 6270 #endif 6271 }, 6272 { 6273 BCMI_FALCON_XGXS_AMS_RX_CTL6r, 6274 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6275 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 6276 BCMI_FALCON_XGXS_AMS_RX_CTL6r_fields, 6277 #else 6278 0, 6279 #endif 6280 #endif 6281 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6282 PHYMOD_SYMBOL_FLAG_REGISTER, 6283 "AMS_RX_CTL6r", 6284 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6285 "AMS_RX_CONTROL_6", 6286 NULL, 6287 #endif 6288 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6289 0x0, /* 0 */ 6290 0, 6291 #endif 6292 }, 6293 { 6294 BCMI_FALCON_XGXS_AMS_RX_CTL7r, 6295 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6296 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 6297 BCMI_FALCON_XGXS_AMS_RX_CTL7r_fields, 6298 #else 6299 0, 6300 #endif 6301 #endif 6302 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6303 PHYMOD_SYMBOL_FLAG_REGISTER, 6304 "AMS_RX_CTL7r", 6305 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6306 "AMS_RX_CONTROL_7", 6307 NULL, 6308 #endif 6309 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6310 0x0, /* 0 */ 6311 0, 6312 #endif 6313 }, 6314 { 6315 BCMI_FALCON_XGXS_AMS_RX_CTL8r, 6316 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6317 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 6318 BCMI_FALCON_XGXS_AMS_RX_CTL8r_fields, 6319 #else 6320 0, 6321 #endif 6322 #endif 6323 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6324 PHYMOD_SYMBOL_FLAG_REGISTER, 6325 "AMS_RX_CTL8r", 6326 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6327 "AMS_RX_CONTROL_8", 6328 NULL, 6329 #endif 6330 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6331 0x0, /* 0 */ 6332 0, 6333 #endif 6334 }, 6335 { 6336 BCMI_FALCON_XGXS_AMS_RX_CTL9r, 6337 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6338 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 6339 BCMI_FALCON_XGXS_AMS_RX_CTL9r_fields, 6340 #else 6341 0, 6342 #endif 6343 #endif 6344 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6345 PHYMOD_SYMBOL_FLAG_REGISTER, 6346 "AMS_RX_CTL9r", 6347 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6348 "AMS_RX_CONTROL_9", 6349 NULL, 6350 #endif 6351 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6352 0x300, /* 768 */ 6353 0, 6354 #endif 6355 }, 6356 { 6357 BCMI_FALCON_XGXS_AMS_RX_STSr, 6358 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6359 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 6360 BCMI_FALCON_XGXS_AMS_RX_STSr_fields, 6361 #else 6362 0, 6363 #endif 6364 #endif 6365 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6366 PHYMOD_SYMBOL_FLAG_REGISTER, 6367 "AMS_RX_STSr", 6368 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6369 "AMS_RX_STATUS", 6370 NULL, 6371 #endif 6372 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6373 0x8000, /* 32768 */ 6374 0, 6375 #endif 6376 }, 6377 { 6378 BCMI_FALCON_XGXS_AMS_TX_CTL0r, 6379 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6380 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 6381 BCMI_FALCON_XGXS_AMS_TX_CTL0r_fields, 6382 #else 6383 0, 6384 #endif 6385 #endif 6386 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6387 PHYMOD_SYMBOL_FLAG_REGISTER, 6388 "AMS_TX_CTL0r", 6389 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6390 "AMS_TX_CONTROL_0", 6391 NULL, 6392 #endif 6393 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6394 0xc0, /* 192 */ 6395 0, 6396 #endif 6397 }, 6398 { 6399 BCMI_FALCON_XGXS_AMS_TX_CTL1r, 6400 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6401 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 6402 BCMI_FALCON_XGXS_AMS_TX_CTL1r_fields, 6403 #else 6404 0, 6405 #endif 6406 #endif 6407 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6408 PHYMOD_SYMBOL_FLAG_REGISTER, 6409 "AMS_TX_CTL1r", 6410 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6411 "AMS_TX_CONTROL_1", 6412 NULL, 6413 #endif 6414 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6415 0x2000, /* 8192 */ 6416 0, 6417 #endif 6418 }, 6419 { 6420 BCMI_FALCON_XGXS_AMS_TX_CTL2r, 6421 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6422 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 6423 BCMI_FALCON_XGXS_AMS_TX_CTL2r_fields, 6424 #else 6425 0, 6426 #endif 6427 #endif 6428 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6429 PHYMOD_SYMBOL_FLAG_REGISTER, 6430 "AMS_TX_CTL2r", 6431 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6432 "AMS_TX_CONTROL_2", 6433 NULL, 6434 #endif 6435 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6436 0xf, /* 15 */ 6437 0, 6438 #endif 6439 }, 6440 { 6441 BCMI_FALCON_XGXS_AMS_TX_CTL3r, 6442 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6443 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 6444 BCMI_FALCON_XGXS_AMS_TX_CTL3r_fields, 6445 #else 6446 0, 6447 #endif 6448 #endif 6449 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6450 PHYMOD_SYMBOL_FLAG_REGISTER, 6451 "AMS_TX_CTL3r", 6452 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6453 "AMS_TX_CONTROL_3", 6454 NULL, 6455 #endif 6456 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6457 0x0, /* 0 */ 6458 0, 6459 #endif 6460 }, 6461 { 6462 BCMI_FALCON_XGXS_AMS_TX_STSr, 6463 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6464 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 6465 BCMI_FALCON_XGXS_AMS_TX_STSr_fields, 6466 #else 6467 0, 6468 #endif 6469 #endif 6470 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6471 PHYMOD_SYMBOL_FLAG_REGISTER, 6472 "AMS_TX_STSr", 6473 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6474 "AMS_TX_STATUS", 6475 NULL, 6476 #endif 6477 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6478 0xa0, /* 160 */ 6479 0, 6480 #endif 6481 }, 6482 { 6483 BCMI_FALCON_XGXS_SIGDET_CTL0r, 6484 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6485 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 6486 BCMI_FALCON_XGXS_SIGDET_CTL0r_fields, 6487 #else 6488 0, 6489 #endif 6490 #endif 6491 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6492 PHYMOD_SYMBOL_FLAG_REGISTER, 6493 "SIGDET_CTL0r", 6494 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6495 "SIGDET_CTRL_0", 6496 NULL, 6497 #endif 6498 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6499 0x1109, /* 4361 */ 6500 0, 6501 #endif 6502 }, 6503 { 6504 BCMI_FALCON_XGXS_SIGDET_CTL1r, 6505 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6506 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 6507 BCMI_FALCON_XGXS_SIGDET_CTL1r_fields, 6508 #else 6509 0, 6510 #endif 6511 #endif 6512 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6513 PHYMOD_SYMBOL_FLAG_REGISTER, 6514 "SIGDET_CTL1r", 6515 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6516 "SIGDET_CTRL_1", 6517 NULL, 6518 #endif 6519 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6520 0xa008, /* 40968 */ 6521 0, 6522 #endif 6523 }, 6524 { 6525 BCMI_FALCON_XGXS_SIGDET_CTL2r, 6526 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6527 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 6528 BCMI_FALCON_XGXS_SIGDET_CTL2r_fields, 6529 #else 6530 0, 6531 #endif 6532 #endif 6533 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6534 PHYMOD_SYMBOL_FLAG_REGISTER, 6535 "SIGDET_CTL2r", 6536 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6537 "SIGDET_CTRL_2", 6538 NULL, 6539 #endif 6540 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6541 0x3f22, /* 16162 */ 6542 0, 6543 #endif 6544 }, 6545 { 6546 BCMI_FALCON_XGXS_SIGDET_STS0r, 6547 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6548 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 6549 BCMI_FALCON_XGXS_SIGDET_STS0r_fields, 6550 #else 6551 0, 6552 #endif 6553 #endif 6554 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6555 PHYMOD_SYMBOL_FLAG_REGISTER, 6556 "SIGDET_STS0r", 6557 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6558 "SIGDET_STATUS_0", 6559 NULL, 6560 #endif 6561 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6562 0x200, /* 512 */ 6563 0, 6564 #endif 6565 }, 6566 { 6567 BCMI_FALCON_XGXS_DIG_REVID0r, 6568 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6569 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 6570 BCMI_FALCON_XGXS_DIG_REVID0r_fields, 6571 #else 6572 0, 6573 #endif 6574 #endif 6575 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6576 PHYMOD_SYMBOL_FLAG_REGISTER, 6577 "DIG_REVID0r", 6578 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6579 "DIG_COM_REVID0", 6580 NULL, 6581 #endif 6582 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6583 0x2db, /* 731 */ 6584 0, 6585 #endif 6586 }, 6587 { 6588 BCMI_FALCON_XGXS_DIG_RST_CTL_PMDr, 6589 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6590 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 6591 BCMI_FALCON_XGXS_DIG_RST_CTL_PMDr_fields, 6592 #else 6593 0, 6594 #endif 6595 #endif 6596 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6597 PHYMOD_SYMBOL_FLAG_REGISTER, 6598 "DIG_RST_CTL_PMDr", 6599 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6600 "DIG_COM_RESET_CONTROL_PMD", 6601 NULL, 6602 #endif 6603 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6604 0x1, /* 1 */ 6605 0, 6606 #endif 6607 }, 6608 { 6609 BCMI_FALCON_XGXS_DIG_RST_CTL_CORE_DPr, 6610 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6611 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 6612 BCMI_FALCON_XGXS_DIG_RST_CTL_CORE_DPr_fields, 6613 #else 6614 0, 6615 #endif 6616 #endif 6617 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6618 PHYMOD_SYMBOL_FLAG_REGISTER, 6619 "DIG_RST_CTL_CORE_DPr", 6620 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6621 "DIG_COM_RESET_CONTROL_CORE_DP", 6622 NULL, 6623 #endif 6624 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6625 0x4000, /* 16384 */ 6626 0, 6627 #endif 6628 }, 6629 { 6630 BCMI_FALCON_XGXS_DIG_LN_MASKr, 6631 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6632 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 6633 BCMI_FALCON_XGXS_DIG_LN_MASKr_fields, 6634 #else 6635 0, 6636 #endif 6637 #endif 6638 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6639 PHYMOD_SYMBOL_FLAG_REGISTER, 6640 "DIG_LN_MASKr", 6641 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6642 "DIG_COM_LANE_MASK", 6643 NULL, 6644 #endif 6645 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6646 0x0, /* 0 */ 6647 0, 6648 #endif 6649 }, 6650 { 6651 BCMI_FALCON_XGXS_DIG_TOP_USER_CTL0r, 6652 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6653 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 6654 BCMI_FALCON_XGXS_DIG_TOP_USER_CTL0r_fields, 6655 #else 6656 0, 6657 #endif 6658 #endif 6659 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6660 PHYMOD_SYMBOL_FLAG_REGISTER, 6661 "DIG_TOP_USER_CTL0r", 6662 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6663 "DIG_COM_TOP_USER_CONTROL_0", 6664 NULL, 6665 #endif 6666 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6667 0x271, /* 625 */ 6668 0, 6669 #endif 6670 }, 6671 { 6672 BCMI_FALCON_XGXS_DIG_UC_ACK_CORE_CTLr, 6673 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6674 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 6675 BCMI_FALCON_XGXS_DIG_UC_ACK_CORE_CTLr_fields, 6676 #else 6677 0, 6678 #endif 6679 #endif 6680 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6681 PHYMOD_SYMBOL_FLAG_REGISTER, 6682 "DIG_UC_ACK_CORE_CTLr", 6683 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6684 "DIG_COM_UC_ACK_CORE_CONTROL", 6685 NULL, 6686 #endif 6687 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6688 0x0, /* 0 */ 6689 0, 6690 #endif 6691 }, 6692 { 6693 BCMI_FALCON_XGXS_DIG_CORE_RST_OCC_CTLr, 6694 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6695 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 6696 BCMI_FALCON_XGXS_DIG_CORE_RST_OCC_CTLr_fields, 6697 #else 6698 0, 6699 #endif 6700 #endif 6701 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6702 PHYMOD_SYMBOL_FLAG_REGISTER, 6703 "DIG_CORE_RST_OCC_CTLr", 6704 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6705 "DIG_COM_CORE_REG_RESET_OCCURRED_CONTROL", 6706 NULL, 6707 #endif 6708 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6709 0x1, /* 1 */ 6710 0, 6711 #endif 6712 }, 6713 { 6714 BCMI_FALCON_XGXS_DIG_RST_SEQ_TMR_CTLr, 6715 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6716 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 6717 BCMI_FALCON_XGXS_DIG_RST_SEQ_TMR_CTLr_fields, 6718 #else 6719 0, 6720 #endif 6721 #endif 6722 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6723 PHYMOD_SYMBOL_FLAG_REGISTER, 6724 "DIG_RST_SEQ_TMR_CTLr", 6725 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6726 "DIG_COM_RST_SEQ_TIMER_CONTROL", 6727 NULL, 6728 #endif 6729 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6730 0x8304, /* 33540 */ 6731 0, 6732 #endif 6733 }, 6734 { 6735 BCMI_FALCON_XGXS_DIG_CORE_DP_RST_ST_STSr, 6736 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6737 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 6738 BCMI_FALCON_XGXS_DIG_CORE_DP_RST_ST_STSr_fields, 6739 #else 6740 0, 6741 #endif 6742 #endif 6743 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6744 PHYMOD_SYMBOL_FLAG_REGISTER, 6745 "DIG_CORE_DP_RST_ST_STSr", 6746 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6747 "DIG_COM_CORE_DP_RESET_STATE_STATUS", 6748 NULL, 6749 #endif 6750 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6751 0x7, /* 7 */ 6752 0, 6753 #endif 6754 }, 6755 { 6756 BCMI_FALCON_XGXS_DIG_PMD_CORE_MODE_STSr, 6757 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6758 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 6759 BCMI_FALCON_XGXS_DIG_PMD_CORE_MODE_STSr_fields, 6760 #else 6761 0, 6762 #endif 6763 #endif 6764 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6765 PHYMOD_SYMBOL_FLAG_REGISTER, 6766 "DIG_PMD_CORE_MODE_STSr", 6767 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6768 "DIG_COM_PMD_CORE_MODE_STATUS", 6769 NULL, 6770 #endif 6771 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6772 0x0, /* 0 */ 6773 0, 6774 #endif 6775 }, 6776 { 6777 BCMI_FALCON_XGXS_DIG_REVID1r, 6778 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6779 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 6780 BCMI_FALCON_XGXS_DIG_REVID1r_fields, 6781 #else 6782 0, 6783 #endif 6784 #endif 6785 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6786 PHYMOD_SYMBOL_FLAG_REGISTER, 6787 "DIG_REVID1r", 6788 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6789 "DIG_COM_REVID1", 6790 NULL, 6791 #endif 6792 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6793 0x403c, /* 16444 */ 6794 0, 6795 #endif 6796 }, 6797 { 6798 BCMI_FALCON_XGXS_DIG_TX_LN_MAP_0_1_2r, 6799 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6800 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 6801 BCMI_FALCON_XGXS_DIG_TX_LN_MAP_0_1_2r_fields, 6802 #else 6803 0, 6804 #endif 6805 #endif 6806 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6807 PHYMOD_SYMBOL_FLAG_REGISTER, 6808 "DIG_TX_LN_MAP_0_1_2r", 6809 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6810 "DIG_COM_TX_LANE_MAP_0_1_2", 6811 NULL, 6812 #endif 6813 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6814 0x820, /* 2080 */ 6815 0, 6816 #endif 6817 }, 6818 { 6819 BCMI_FALCON_XGXS_DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r, 6820 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6821 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 6822 BCMI_FALCON_XGXS_DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r_fields, 6823 #else 6824 0, 6825 #endif 6826 #endif 6827 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6828 PHYMOD_SYMBOL_FLAG_REGISTER, 6829 "DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r", 6830 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6831 "DIG_COM_TX_LANE_MAP_3_N_LANE_ADDR_0_1", 6832 NULL, 6833 #endif 6834 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6835 0x403, /* 1027 */ 6836 0, 6837 #endif 6838 }, 6839 { 6840 BCMI_FALCON_XGXS_DIG_LN_ADDR_2_3r, 6841 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6842 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 6843 BCMI_FALCON_XGXS_DIG_LN_ADDR_2_3r_fields, 6844 #else 6845 0, 6846 #endif 6847 #endif 6848 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6849 PHYMOD_SYMBOL_FLAG_REGISTER, 6850 "DIG_LN_ADDR_2_3r", 6851 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6852 "DIG_COM_LANE_ADDR_2_3", 6853 NULL, 6854 #endif 6855 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6856 0x302, /* 770 */ 6857 0, 6858 #endif 6859 }, 6860 { 6861 BCMI_FALCON_XGXS_DIG_REVID2r, 6862 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6863 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 6864 BCMI_FALCON_XGXS_DIG_REVID2r_fields, 6865 #else 6866 0, 6867 #endif 6868 #endif 6869 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6870 PHYMOD_SYMBOL_FLAG_REGISTER, 6871 "DIG_REVID2r", 6872 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6873 "DIG_COM_REVID2", 6874 NULL, 6875 #endif 6876 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6877 0x0, /* 0 */ 6878 0, 6879 #endif 6880 }, 6881 { 6882 BCMI_FALCON_XGXS_AMS_PLL_CTL0r, 6883 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6884 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 6885 BCMI_FALCON_XGXS_AMS_PLL_CTL0r_fields, 6886 #else 6887 0, 6888 #endif 6889 #endif 6890 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6891 PHYMOD_SYMBOL_FLAG_REGISTER, 6892 "AMS_PLL_CTL0r", 6893 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6894 "AMS_COM_PLL_CONTROL_0", 6895 NULL, 6896 #endif 6897 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6898 0x0, /* 0 */ 6899 0, 6900 #endif 6901 }, 6902 { 6903 BCMI_FALCON_XGXS_AMS_PLL_CTL1r, 6904 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6905 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 6906 BCMI_FALCON_XGXS_AMS_PLL_CTL1r_fields, 6907 #else 6908 0, 6909 #endif 6910 #endif 6911 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6912 PHYMOD_SYMBOL_FLAG_REGISTER, 6913 "AMS_PLL_CTL1r", 6914 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6915 "AMS_COM_PLL_CONTROL_1", 6916 NULL, 6917 #endif 6918 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6919 0x8000, /* 32768 */ 6920 0, 6921 #endif 6922 }, 6923 { 6924 BCMI_FALCON_XGXS_AMS_PLL_CTL2r, 6925 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6926 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 6927 BCMI_FALCON_XGXS_AMS_PLL_CTL2r_fields, 6928 #else 6929 0, 6930 #endif 6931 #endif 6932 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6933 PHYMOD_SYMBOL_FLAG_REGISTER, 6934 "AMS_PLL_CTL2r", 6935 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6936 "AMS_COM_PLL_CONTROL_2", 6937 NULL, 6938 #endif 6939 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6940 0x1e, /* 30 */ 6941 0, 6942 #endif 6943 }, 6944 { 6945 BCMI_FALCON_XGXS_AMS_PLL_CTL3r, 6946 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6947 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 6948 BCMI_FALCON_XGXS_AMS_PLL_CTL3r_fields, 6949 #else 6950 0, 6951 #endif 6952 #endif 6953 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6954 PHYMOD_SYMBOL_FLAG_REGISTER, 6955 "AMS_PLL_CTL3r", 6956 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6957 "AMS_COM_PLL_CONTROL_3", 6958 NULL, 6959 #endif 6960 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6961 0x0, /* 0 */ 6962 0, 6963 #endif 6964 }, 6965 { 6966 BCMI_FALCON_XGXS_AMS_PLL_CTL4r, 6967 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6968 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 6969 BCMI_FALCON_XGXS_AMS_PLL_CTL4r_fields, 6970 #else 6971 0, 6972 #endif 6973 #endif 6974 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6975 PHYMOD_SYMBOL_FLAG_REGISTER, 6976 "AMS_PLL_CTL4r", 6977 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6978 "AMS_COM_PLL_CONTROL_4", 6979 NULL, 6980 #endif 6981 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6982 0x77, /* 119 */ 6983 0, 6984 #endif 6985 }, 6986 { 6987 BCMI_FALCON_XGXS_AMS_PLL_CTL5r, 6988 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6989 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 6990 BCMI_FALCON_XGXS_AMS_PLL_CTL5r_fields, 6991 #else 6992 0, 6993 #endif 6994 #endif 6995 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6996 PHYMOD_SYMBOL_FLAG_REGISTER, 6997 "AMS_PLL_CTL5r", 6998 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6999 "AMS_COM_PLL_CONTROL_5", 7000 NULL, 7001 #endif 7002 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7003 0x1f00, /* 7936 */ 7004 0, 7005 #endif 7006 }, 7007 { 7008 BCMI_FALCON_XGXS_AMS_PLL_CTL6r, 7009 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7010 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 7011 BCMI_FALCON_XGXS_AMS_PLL_CTL6r_fields, 7012 #else 7013 0, 7014 #endif 7015 #endif 7016 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7017 PHYMOD_SYMBOL_FLAG_REGISTER, 7018 "AMS_PLL_CTL6r", 7019 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7020 "AMS_COM_PLL_CONTROL_6", 7021 NULL, 7022 #endif 7023 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7024 0xc1c0, /* 49600 */ 7025 0, 7026 #endif 7027 }, 7028 { 7029 BCMI_FALCON_XGXS_AMS_PLL_CTL7r, 7030 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7031 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 7032 BCMI_FALCON_XGXS_AMS_PLL_CTL7r_fields, 7033 #else 7034 0, 7035 #endif 7036 #endif 7037 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7038 PHYMOD_SYMBOL_FLAG_REGISTER, 7039 "AMS_PLL_CTL7r", 7040 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7041 "AMS_COM_PLL_CONTROL_7", 7042 NULL, 7043 #endif 7044 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7045 0x1f00, /* 7936 */ 7046 0, 7047 #endif 7048 }, 7049 { 7050 BCMI_FALCON_XGXS_AMS_PLL_STSr, 7051 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7052 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 7053 BCMI_FALCON_XGXS_AMS_PLL_STSr_fields, 7054 #else 7055 0, 7056 #endif 7057 #endif 7058 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7059 PHYMOD_SYMBOL_FLAG_REGISTER, 7060 "AMS_PLL_STSr", 7061 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7062 "AMS_COM_PLL_STATUS", 7063 NULL, 7064 #endif 7065 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7066 0xc007, /* 49159 */ 7067 0, 7068 #endif 7069 }, 7070 { 7071 BCMI_FALCON_XGXS_PATT_GEN_SEQ0r, 7072 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7073 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 7074 BCMI_FALCON_XGXS_PATT_GEN_SEQ0r_fields, 7075 #else 7076 0, 7077 #endif 7078 #endif 7079 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7080 PHYMOD_SYMBOL_FLAG_REGISTER, 7081 "PATT_GEN_SEQ0r", 7082 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7083 "PATT_GEN_COM_SEQ_0", 7084 NULL, 7085 #endif 7086 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7087 0xff00, /* 65280 */ 7088 0, 7089 #endif 7090 }, 7091 { 7092 BCMI_FALCON_XGXS_PATT_GEN_SEQ1r, 7093 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7094 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 7095 BCMI_FALCON_XGXS_PATT_GEN_SEQ1r_fields, 7096 #else 7097 0, 7098 #endif 7099 #endif 7100 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7101 PHYMOD_SYMBOL_FLAG_REGISTER, 7102 "PATT_GEN_SEQ1r", 7103 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7104 "PATT_GEN_COM_SEQ_1", 7105 NULL, 7106 #endif 7107 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7108 0xff00, /* 65280 */ 7109 0, 7110 #endif 7111 }, 7112 { 7113 BCMI_FALCON_XGXS_PATT_GEN_SEQ2r, 7114 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7115 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 7116 BCMI_FALCON_XGXS_PATT_GEN_SEQ2r_fields, 7117 #else 7118 0, 7119 #endif 7120 #endif 7121 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7122 PHYMOD_SYMBOL_FLAG_REGISTER, 7123 "PATT_GEN_SEQ2r", 7124 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7125 "PATT_GEN_COM_SEQ_2", 7126 NULL, 7127 #endif 7128 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7129 0xff00, /* 65280 */ 7130 0, 7131 #endif 7132 }, 7133 { 7134 BCMI_FALCON_XGXS_PATT_GEN_SEQ3r, 7135 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7136 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 7137 BCMI_FALCON_XGXS_PATT_GEN_SEQ3r_fields, 7138 #else 7139 0, 7140 #endif 7141 #endif 7142 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7143 PHYMOD_SYMBOL_FLAG_REGISTER, 7144 "PATT_GEN_SEQ3r", 7145 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7146 "PATT_GEN_COM_SEQ_3", 7147 NULL, 7148 #endif 7149 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7150 0xff00, /* 65280 */ 7151 0, 7152 #endif 7153 }, 7154 { 7155 BCMI_FALCON_XGXS_PATT_GEN_SEQ4r, 7156 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7157 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 7158 BCMI_FALCON_XGXS_PATT_GEN_SEQ4r_fields, 7159 #else 7160 0, 7161 #endif 7162 #endif 7163 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7164 PHYMOD_SYMBOL_FLAG_REGISTER, 7165 "PATT_GEN_SEQ4r", 7166 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7167 "PATT_GEN_COM_SEQ_4", 7168 NULL, 7169 #endif 7170 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7171 0xff00, /* 65280 */ 7172 0, 7173 #endif 7174 }, 7175 { 7176 BCMI_FALCON_XGXS_PATT_GEN_SEQ5r, 7177 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7178 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 7179 BCMI_FALCON_XGXS_PATT_GEN_SEQ5r_fields, 7180 #else 7181 0, 7182 #endif 7183 #endif 7184 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7185 PHYMOD_SYMBOL_FLAG_REGISTER, 7186 "PATT_GEN_SEQ5r", 7187 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7188 "PATT_GEN_COM_SEQ_5", 7189 NULL, 7190 #endif 7191 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7192 0xff00, /* 65280 */ 7193 0, 7194 #endif 7195 }, 7196 { 7197 BCMI_FALCON_XGXS_PATT_GEN_SEQ6r, 7198 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7199 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 7200 BCMI_FALCON_XGXS_PATT_GEN_SEQ6r_fields, 7201 #else 7202 0, 7203 #endif 7204 #endif 7205 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7206 PHYMOD_SYMBOL_FLAG_REGISTER, 7207 "PATT_GEN_SEQ6r", 7208 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7209 "PATT_GEN_COM_SEQ_6", 7210 NULL, 7211 #endif 7212 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7213 0xff00, /* 65280 */ 7214 0, 7215 #endif 7216 }, 7217 { 7218 BCMI_FALCON_XGXS_PATT_GEN_SEQ7r, 7219 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7220 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 7221 BCMI_FALCON_XGXS_PATT_GEN_SEQ7r_fields, 7222 #else 7223 0, 7224 #endif 7225 #endif 7226 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7227 PHYMOD_SYMBOL_FLAG_REGISTER, 7228 "PATT_GEN_SEQ7r", 7229 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7230 "PATT_GEN_COM_SEQ_7", 7231 NULL, 7232 #endif 7233 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7234 0xff00, /* 65280 */ 7235 0, 7236 #endif 7237 }, 7238 { 7239 BCMI_FALCON_XGXS_PATT_GEN_SEQ8r, 7240 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7241 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 7242 BCMI_FALCON_XGXS_PATT_GEN_SEQ8r_fields, 7243 #else 7244 0, 7245 #endif 7246 #endif 7247 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7248 PHYMOD_SYMBOL_FLAG_REGISTER, 7249 "PATT_GEN_SEQ8r", 7250 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7251 "PATT_GEN_COM_SEQ_8", 7252 NULL, 7253 #endif 7254 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7255 0xff00, /* 65280 */ 7256 0, 7257 #endif 7258 }, 7259 { 7260 BCMI_FALCON_XGXS_PATT_GEN_SEQ9r, 7261 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7262 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 7263 BCMI_FALCON_XGXS_PATT_GEN_SEQ9r_fields, 7264 #else 7265 0, 7266 #endif 7267 #endif 7268 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7269 PHYMOD_SYMBOL_FLAG_REGISTER, 7270 "PATT_GEN_SEQ9r", 7271 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7272 "PATT_GEN_COM_SEQ_9", 7273 NULL, 7274 #endif 7275 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7276 0xff00, /* 65280 */ 7277 0, 7278 #endif 7279 }, 7280 { 7281 BCMI_FALCON_XGXS_PATT_GEN_SEQ_10r, 7282 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7283 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 7284 BCMI_FALCON_XGXS_PATT_GEN_SEQ_10r_fields, 7285 #else 7286 0, 7287 #endif 7288 #endif 7289 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7290 PHYMOD_SYMBOL_FLAG_REGISTER, 7291 "PATT_GEN_SEQ_10r", 7292 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7293 "PATT_GEN_COM_SEQ_10", 7294 NULL, 7295 #endif 7296 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7297 0xff00, /* 65280 */ 7298 0, 7299 #endif 7300 }, 7301 { 7302 BCMI_FALCON_XGXS_PATT_GEN_SEQ_11r, 7303 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7304 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 7305 BCMI_FALCON_XGXS_PATT_GEN_SEQ_11r_fields, 7306 #else 7307 0, 7308 #endif 7309 #endif 7310 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7311 PHYMOD_SYMBOL_FLAG_REGISTER, 7312 "PATT_GEN_SEQ_11r", 7313 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7314 "PATT_GEN_COM_SEQ_11", 7315 NULL, 7316 #endif 7317 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7318 0xff00, /* 65280 */ 7319 0, 7320 #endif 7321 }, 7322 { 7323 BCMI_FALCON_XGXS_PATT_GEN_SEQ_12r, 7324 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7325 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 7326 BCMI_FALCON_XGXS_PATT_GEN_SEQ_12r_fields, 7327 #else 7328 0, 7329 #endif 7330 #endif 7331 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7332 PHYMOD_SYMBOL_FLAG_REGISTER, 7333 "PATT_GEN_SEQ_12r", 7334 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7335 "PATT_GEN_COM_SEQ_12", 7336 NULL, 7337 #endif 7338 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7339 0xff00, /* 65280 */ 7340 0, 7341 #endif 7342 }, 7343 { 7344 BCMI_FALCON_XGXS_PATT_GEN_SEQ_13r, 7345 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7346 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 7347 BCMI_FALCON_XGXS_PATT_GEN_SEQ_13r_fields, 7348 #else 7349 0, 7350 #endif 7351 #endif 7352 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7353 PHYMOD_SYMBOL_FLAG_REGISTER, 7354 "PATT_GEN_SEQ_13r", 7355 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7356 "PATT_GEN_COM_SEQ_13", 7357 NULL, 7358 #endif 7359 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7360 0xff00, /* 65280 */ 7361 0, 7362 #endif 7363 }, 7364 { 7365 BCMI_FALCON_XGXS_PATT_GEN_SEQ_14r, 7366 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7367 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 7368 BCMI_FALCON_XGXS_PATT_GEN_SEQ_14r_fields, 7369 #else 7370 0, 7371 #endif 7372 #endif 7373 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7374 PHYMOD_SYMBOL_FLAG_REGISTER, 7375 "PATT_GEN_SEQ_14r", 7376 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7377 "PATT_GEN_COM_SEQ_14", 7378 NULL, 7379 #endif 7380 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7381 0xff00, /* 65280 */ 7382 0, 7383 #endif 7384 }, 7385 { 7386 BCMI_FALCON_XGXS_TXFIR_CTL0r, 7387 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7388 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 7389 BCMI_FALCON_XGXS_TXFIR_CTL0r_fields, 7390 #else 7391 0, 7392 #endif 7393 #endif 7394 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7395 PHYMOD_SYMBOL_FLAG_REGISTER, 7396 "TXFIR_CTL0r", 7397 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7398 "TX_FED_TXFIR_CONTROL0", 7399 NULL, 7400 #endif 7401 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7402 0x0, /* 0 */ 7403 0, 7404 #endif 7405 }, 7406 { 7407 BCMI_FALCON_XGXS_TXFIR_CTL1r, 7408 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7409 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 7410 BCMI_FALCON_XGXS_TXFIR_CTL1r_fields, 7411 #else 7412 0, 7413 #endif 7414 #endif 7415 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7416 PHYMOD_SYMBOL_FLAG_REGISTER, 7417 "TXFIR_CTL1r", 7418 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7419 "TX_FED_TXFIR_CONTROL1", 7420 NULL, 7421 #endif 7422 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7423 0x0, /* 0 */ 7424 0, 7425 #endif 7426 }, 7427 { 7428 BCMI_FALCON_XGXS_TXFIR_CTL2r, 7429 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7430 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 7431 BCMI_FALCON_XGXS_TXFIR_CTL2r_fields, 7432 #else 7433 0, 7434 #endif 7435 #endif 7436 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7437 PHYMOD_SYMBOL_FLAG_REGISTER, 7438 "TXFIR_CTL2r", 7439 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7440 "TX_FED_TXFIR_CONTROL2", 7441 NULL, 7442 #endif 7443 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7444 0x800, /* 2048 */ 7445 0, 7446 #endif 7447 }, 7448 { 7449 BCMI_FALCON_XGXS_TXFIR_STS0r, 7450 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7451 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 7452 BCMI_FALCON_XGXS_TXFIR_STS0r_fields, 7453 #else 7454 0, 7455 #endif 7456 #endif 7457 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7458 PHYMOD_SYMBOL_FLAG_REGISTER, 7459 "TXFIR_STS0r", 7460 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7461 "TX_FED_TXFIR_STATUS0", 7462 NULL, 7463 #endif 7464 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7465 0x2c08, /* 11272 */ 7466 0, 7467 #endif 7468 }, 7469 { 7470 BCMI_FALCON_XGXS_TXFIR_STS1r, 7471 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7472 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 7473 BCMI_FALCON_XGXS_TXFIR_STS1r_fields, 7474 #else 7475 0, 7476 #endif 7477 #endif 7478 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7479 PHYMOD_SYMBOL_FLAG_REGISTER, 7480 "TXFIR_STS1r", 7481 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7482 "TX_FED_TXFIR_STATUS1", 7483 NULL, 7484 #endif 7485 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7486 0x3c, /* 60 */ 7487 0, 7488 #endif 7489 }, 7490 { 7491 BCMI_FALCON_XGXS_TXFIR_STS2r, 7492 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7493 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 7494 BCMI_FALCON_XGXS_TXFIR_STS2r_fields, 7495 #else 7496 0, 7497 #endif 7498 #endif 7499 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7500 PHYMOD_SYMBOL_FLAG_REGISTER, 7501 "TXFIR_STS2r", 7502 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7503 "TX_FED_TXFIR_STATUS2", 7504 NULL, 7505 #endif 7506 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7507 0x2c08, /* 11272 */ 7508 0, 7509 #endif 7510 }, 7511 { 7512 BCMI_FALCON_XGXS_TXFIR_STS3r, 7513 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7514 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 7515 BCMI_FALCON_XGXS_TXFIR_STS3r_fields, 7516 #else 7517 0, 7518 #endif 7519 #endif 7520 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7521 PHYMOD_SYMBOL_FLAG_REGISTER, 7522 "TXFIR_STS3r", 7523 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7524 "TX_FED_TXFIR_STATUS3", 7525 NULL, 7526 #endif 7527 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7528 0x3c, /* 60 */ 7529 0, 7530 #endif 7531 }, 7532 { 7533 BCMI_FALCON_XGXS_TXFIR_STS4r, 7534 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7535 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 7536 BCMI_FALCON_XGXS_TXFIR_STS4r_fields, 7537 #else 7538 0, 7539 #endif 7540 #endif 7541 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7542 PHYMOD_SYMBOL_FLAG_REGISTER, 7543 "TXFIR_STS4r", 7544 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7545 "TX_FED_TXFIR_STATUS4", 7546 NULL, 7547 #endif 7548 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7549 0x8, /* 8 */ 7550 0, 7551 #endif 7552 }, 7553 { 7554 BCMI_FALCON_XGXS_TXFIR_UC_CTL0r, 7555 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7556 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 7557 BCMI_FALCON_XGXS_TXFIR_UC_CTL0r_fields, 7558 #else 7559 0, 7560 #endif 7561 #endif 7562 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7563 PHYMOD_SYMBOL_FLAG_REGISTER, 7564 "TXFIR_UC_CTL0r", 7565 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7566 "TX_FED_TXFIR_MICRO_CONTROL0", 7567 NULL, 7568 #endif 7569 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7570 0x0, /* 0 */ 7571 0, 7572 #endif 7573 }, 7574 { 7575 BCMI_FALCON_XGXS_TXFIR_MISC_CTL1r, 7576 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7577 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 7578 BCMI_FALCON_XGXS_TXFIR_MISC_CTL1r_fields, 7579 #else 7580 0, 7581 #endif 7582 #endif 7583 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7584 PHYMOD_SYMBOL_FLAG_REGISTER, 7585 "TXFIR_MISC_CTL1r", 7586 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7587 "TX_FED_TXFIR_MISC_CONTROL1", 7588 NULL, 7589 #endif 7590 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7591 0x300, /* 768 */ 7592 0, 7593 #endif 7594 }, 7595 { 7596 BCMI_FALCON_XGXS_PLL_CAL_CTL0r, 7597 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7598 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 7599 BCMI_FALCON_XGXS_PLL_CAL_CTL0r_fields, 7600 #else 7601 0, 7602 #endif 7603 #endif 7604 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7605 PHYMOD_SYMBOL_FLAG_REGISTER, 7606 "PLL_CAL_CTL0r", 7607 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7608 "PLL_CAL_COM_CTL_0", 7609 NULL, 7610 #endif 7611 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7612 0xc803, /* 51203 */ 7613 0, 7614 #endif 7615 }, 7616 { 7617 BCMI_FALCON_XGXS_PLL_CAL_CTL1r, 7618 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7619 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 7620 BCMI_FALCON_XGXS_PLL_CAL_CTL1r_fields, 7621 #else 7622 0, 7623 #endif 7624 #endif 7625 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7626 PHYMOD_SYMBOL_FLAG_REGISTER, 7627 "PLL_CAL_CTL1r", 7628 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7629 "PLL_CAL_COM_CTL_1", 7630 NULL, 7631 #endif 7632 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7633 0xc8ff, /* 51455 */ 7634 0, 7635 #endif 7636 }, 7637 { 7638 BCMI_FALCON_XGXS_PLL_CAL_CTL2r, 7639 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7640 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 7641 BCMI_FALCON_XGXS_PLL_CAL_CTL2r_fields, 7642 #else 7643 0, 7644 #endif 7645 #endif 7646 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7647 PHYMOD_SYMBOL_FLAG_REGISTER, 7648 "PLL_CAL_CTL2r", 7649 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7650 "PLL_CAL_COM_CTL_2", 7651 NULL, 7652 #endif 7653 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7654 0xff01, /* 65281 */ 7655 0, 7656 #endif 7657 }, 7658 { 7659 BCMI_FALCON_XGXS_PLL_CAL_CTL3r, 7660 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7661 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 7662 BCMI_FALCON_XGXS_PLL_CAL_CTL3r_fields, 7663 #else 7664 0, 7665 #endif 7666 #endif 7667 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7668 PHYMOD_SYMBOL_FLAG_REGISTER, 7669 "PLL_CAL_CTL3r", 7670 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7671 "PLL_CAL_COM_CTL_3", 7672 NULL, 7673 #endif 7674 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7675 0x0, /* 0 */ 7676 0, 7677 #endif 7678 }, 7679 { 7680 BCMI_FALCON_XGXS_PLL_CAL_CTL4r, 7681 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7682 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 7683 BCMI_FALCON_XGXS_PLL_CAL_CTL4r_fields, 7684 #else 7685 0, 7686 #endif 7687 #endif 7688 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7689 PHYMOD_SYMBOL_FLAG_REGISTER, 7690 "PLL_CAL_CTL4r", 7691 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7692 "PLL_CAL_COM_CTL_4", 7693 NULL, 7694 #endif 7695 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7696 0xa80d, /* 43021 */ 7697 0, 7698 #endif 7699 }, 7700 { 7701 BCMI_FALCON_XGXS_PLL_CAL_CTL5r, 7702 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7703 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 7704 BCMI_FALCON_XGXS_PLL_CAL_CTL5r_fields, 7705 #else 7706 0, 7707 #endif 7708 #endif 7709 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7710 PHYMOD_SYMBOL_FLAG_REGISTER, 7711 "PLL_CAL_CTL5r", 7712 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7713 "PLL_CAL_COM_CTL_5", 7714 NULL, 7715 #endif 7716 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7717 0x27, /* 39 */ 7718 0, 7719 #endif 7720 }, 7721 { 7722 BCMI_FALCON_XGXS_PLL_CAL_CTL6r, 7723 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7724 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 7725 BCMI_FALCON_XGXS_PLL_CAL_CTL6r_fields, 7726 #else 7727 0, 7728 #endif 7729 #endif 7730 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7731 PHYMOD_SYMBOL_FLAG_REGISTER, 7732 "PLL_CAL_CTL6r", 7733 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7734 "PLL_CAL_COM_CTL_6", 7735 NULL, 7736 #endif 7737 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7738 0x7, /* 7 */ 7739 0, 7740 #endif 7741 }, 7742 { 7743 BCMI_FALCON_XGXS_PLL_CAL_CTL7r, 7744 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7745 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 7746 BCMI_FALCON_XGXS_PLL_CAL_CTL7r_fields, 7747 #else 7748 0, 7749 #endif 7750 #endif 7751 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7752 PHYMOD_SYMBOL_FLAG_REGISTER, 7753 "PLL_CAL_CTL7r", 7754 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7755 "PLL_CAL_COM_CTL_7", 7756 NULL, 7757 #endif 7758 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7759 0x7, /* 7 */ 7760 0, 7761 #endif 7762 }, 7763 { 7764 BCMI_FALCON_XGXS_PLL_CAL_CTL_STS0r, 7765 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7766 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 7767 BCMI_FALCON_XGXS_PLL_CAL_CTL_STS0r_fields, 7768 #else 7769 0, 7770 #endif 7771 #endif 7772 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7773 PHYMOD_SYMBOL_FLAG_REGISTER, 7774 "PLL_CAL_CTL_STS0r", 7775 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7776 "PLL_CAL_COM_CTL_STATUS_0", 7777 NULL, 7778 #endif 7779 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7780 0x0, /* 0 */ 7781 0, 7782 #endif 7783 }, 7784 { 7785 BCMI_FALCON_XGXS_PLL_CAL_CTL_STS1r, 7786 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7787 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 7788 BCMI_FALCON_XGXS_PLL_CAL_CTL_STS1r_fields, 7789 #else 7790 0, 7791 #endif 7792 #endif 7793 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7794 PHYMOD_SYMBOL_FLAG_REGISTER, 7795 "PLL_CAL_CTL_STS1r", 7796 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7797 "PLL_CAL_COM_CTL_STATUS_1", 7798 NULL, 7799 #endif 7800 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7801 0x0, /* 0 */ 7802 0, 7803 #endif 7804 }, 7805 { 7806 BCMI_FALCON_XGXS_PLL_CAL_CTL_STS_DBGr, 7807 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7808 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 7809 BCMI_FALCON_XGXS_PLL_CAL_CTL_STS_DBGr_fields, 7810 #else 7811 0, 7812 #endif 7813 #endif 7814 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7815 PHYMOD_SYMBOL_FLAG_REGISTER, 7816 "PLL_CAL_CTL_STS_DBGr", 7817 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7818 "PLL_CAL_COM_CTL_STATUS_DBG", 7819 NULL, 7820 #endif 7821 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7822 0x1, /* 1 */ 7823 0, 7824 #endif 7825 }, 7826 { 7827 BCMI_FALCON_XGXS_TX_CTL0r, 7828 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7829 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 7830 BCMI_FALCON_XGXS_TX_CTL0r_fields, 7831 #else 7832 0, 7833 #endif 7834 #endif 7835 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7836 PHYMOD_SYMBOL_FLAG_REGISTER, 7837 "TX_CTL0r", 7838 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7839 "TX_COM_CONTROL0_REGISTER", 7840 NULL, 7841 #endif 7842 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7843 0x0, /* 0 */ 7844 0, 7845 #endif 7846 }, 7847 { 7848 BCMI_FALCON_XGXS_TX_CTL1r, 7849 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7850 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 7851 BCMI_FALCON_XGXS_TX_CTL1r_fields, 7852 #else 7853 0, 7854 #endif 7855 #endif 7856 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7857 PHYMOD_SYMBOL_FLAG_REGISTER, 7858 "TX_CTL1r", 7859 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7860 "TX_COM_CONTROL1_REGISTER", 7861 NULL, 7862 #endif 7863 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7864 0x70, /* 112 */ 7865 0, 7866 #endif 7867 }, 7868 { 7869 BCMI_FALCON_XGXS_TX_CTL2r, 7870 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7871 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 7872 BCMI_FALCON_XGXS_TX_CTL2r_fields, 7873 #else 7874 0, 7875 #endif 7876 #endif 7877 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7878 PHYMOD_SYMBOL_FLAG_REGISTER, 7879 "TX_CTL2r", 7880 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7881 "TX_COM_CONTROL2_REGISTER", 7882 NULL, 7883 #endif 7884 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7885 0x1f4, /* 500 */ 7886 0, 7887 #endif 7888 }, 7889 { 7890 BCMI_FALCON_XGXS_TX_CTL3r, 7891 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7892 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 7893 BCMI_FALCON_XGXS_TX_CTL3r_fields, 7894 #else 7895 0, 7896 #endif 7897 #endif 7898 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7899 PHYMOD_SYMBOL_FLAG_REGISTER, 7900 "TX_CTL3r", 7901 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7902 "TX_COM_CONTROL3_REGISTER", 7903 NULL, 7904 #endif 7905 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7906 0xc8, /* 200 */ 7907 0, 7908 #endif 7909 }, 7910 { 7911 BCMI_FALCON_XGXS_TLB_RX_PRBS_CHK_CNT_CFGr, 7912 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7913 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 7914 BCMI_FALCON_XGXS_TLB_RX_PRBS_CHK_CNT_CFGr_fields, 7915 #else 7916 0, 7917 #endif 7918 #endif 7919 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7920 PHYMOD_SYMBOL_FLAG_REGISTER, 7921 "TLB_RX_PRBS_CHK_CNT_CFGr", 7922 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7923 "TLB_RX_PRBS_CHK_CNT_CONFIG", 7924 NULL, 7925 #endif 7926 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7927 0x602, /* 1538 */ 7928 0, 7929 #endif 7930 }, 7931 { 7932 BCMI_FALCON_XGXS_TLB_RX_PRBS_CHK_CFGr, 7933 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7934 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 7935 BCMI_FALCON_XGXS_TLB_RX_PRBS_CHK_CFGr_fields, 7936 #else 7937 0, 7938 #endif 7939 #endif 7940 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7941 PHYMOD_SYMBOL_FLAG_REGISTER, 7942 "TLB_RX_PRBS_CHK_CFGr", 7943 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7944 "TLB_RX_PRBS_CHK_CONFIG", 7945 NULL, 7946 #endif 7947 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7948 0x10a, /* 266 */ 7949 0, 7950 #endif 7951 }, 7952 { 7953 BCMI_FALCON_XGXS_TLB_RX_DIG_LPBK_CFGr, 7954 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7955 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 7956 BCMI_FALCON_XGXS_TLB_RX_DIG_LPBK_CFGr_fields, 7957 #else 7958 0, 7959 #endif 7960 #endif 7961 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7962 PHYMOD_SYMBOL_FLAG_REGISTER, 7963 "TLB_RX_DIG_LPBK_CFGr", 7964 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7965 "TLB_RX_DIG_LPBK_CONFIG", 7966 NULL, 7967 #endif 7968 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7969 0xa, /* 10 */ 7970 0, 7971 #endif 7972 }, 7973 { 7974 BCMI_FALCON_XGXS_TLB_RX_MISC_CFGr, 7975 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7976 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 7977 BCMI_FALCON_XGXS_TLB_RX_MISC_CFGr_fields, 7978 #else 7979 0, 7980 #endif 7981 #endif 7982 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7983 PHYMOD_SYMBOL_FLAG_REGISTER, 7984 "TLB_RX_MISC_CFGr", 7985 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7986 "TLB_RX_MISC_CONFIG", 7987 NULL, 7988 #endif 7989 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7990 0x0, /* 0 */ 7991 0, 7992 #endif 7993 }, 7994 { 7995 BCMI_FALCON_XGXS_TLB_RX_PRBS_CHK_EN_TMR_CTLr, 7996 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7997 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 7998 BCMI_FALCON_XGXS_TLB_RX_PRBS_CHK_EN_TMR_CTLr_fields, 7999 #else 8000 0, 8001 #endif 8002 #endif 8003 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8004 PHYMOD_SYMBOL_FLAG_REGISTER, 8005 "TLB_RX_PRBS_CHK_EN_TMR_CTLr", 8006 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8007 "TLB_RX_PRBS_CHK_EN_TIMER_CONTROL", 8008 NULL, 8009 #endif 8010 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8011 0x0, /* 0 */ 8012 0, 8013 #endif 8014 }, 8015 { 8016 BCMI_FALCON_XGXS_TLB_RX_DIG_LPBK_PD_STSr, 8017 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8018 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 8019 BCMI_FALCON_XGXS_TLB_RX_DIG_LPBK_PD_STSr_fields, 8020 #else 8021 0, 8022 #endif 8023 #endif 8024 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8025 PHYMOD_SYMBOL_FLAG_REGISTER, 8026 "TLB_RX_DIG_LPBK_PD_STSr", 8027 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8028 "TLB_RX_DIG_LPBK_PD_STATUS", 8029 NULL, 8030 #endif 8031 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8032 0x2, /* 2 */ 8033 0, 8034 #endif 8035 }, 8036 { 8037 BCMI_FALCON_XGXS_TLB_RX_PRBS_CHK_LOCK_STSr, 8038 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8039 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 8040 BCMI_FALCON_XGXS_TLB_RX_PRBS_CHK_LOCK_STSr_fields, 8041 #else 8042 0, 8043 #endif 8044 #endif 8045 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8046 PHYMOD_SYMBOL_FLAG_REGISTER, 8047 "TLB_RX_PRBS_CHK_LOCK_STSr", 8048 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8049 "TLB_RX_PRBS_CHK_LOCK_STATUS", 8050 NULL, 8051 #endif 8052 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8053 0x0, /* 0 */ 8054 0, 8055 #endif 8056 }, 8057 { 8058 BCMI_FALCON_XGXS_TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr, 8059 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8060 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 8061 BCMI_FALCON_XGXS_TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr_fields, 8062 #else 8063 0, 8064 #endif 8065 #endif 8066 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8067 PHYMOD_SYMBOL_FLAG_REGISTER, 8068 "TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr", 8069 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8070 "TLB_RX_PRBS_CHK_ERR_CNT_MSB_STATUS", 8071 NULL, 8072 #endif 8073 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8074 0x8000, /* 32768 */ 8075 0, 8076 #endif 8077 }, 8078 { 8079 BCMI_FALCON_XGXS_TLB_RX_PRBS_CHK_ERR_CNT_LSB_STSr, 8080 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8081 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 8082 BCMI_FALCON_XGXS_TLB_RX_PRBS_CHK_ERR_CNT_LSB_STSr_fields, 8083 #else 8084 0, 8085 #endif 8086 #endif 8087 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8088 PHYMOD_SYMBOL_FLAG_REGISTER, 8089 "TLB_RX_PRBS_CHK_ERR_CNT_LSB_STSr", 8090 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8091 "TLB_RX_PRBS_CHK_ERR_CNT_LSB_STATUS", 8092 NULL, 8093 #endif 8094 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8095 0x0, /* 0 */ 8096 0, 8097 #endif 8098 }, 8099 { 8100 BCMI_FALCON_XGXS_TLB_RX_PMD_RX_LOCK_STSr, 8101 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8102 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 8103 BCMI_FALCON_XGXS_TLB_RX_PMD_RX_LOCK_STSr_fields, 8104 #else 8105 0, 8106 #endif 8107 #endif 8108 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8109 PHYMOD_SYMBOL_FLAG_REGISTER, 8110 "TLB_RX_PMD_RX_LOCK_STSr", 8111 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8112 "TLB_RX_PMD_RX_LOCK_STATUS", 8113 NULL, 8114 #endif 8115 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8116 0x0, /* 0 */ 8117 0, 8118 #endif 8119 }, 8120 { 8121 BCMI_FALCON_XGXS_TLB_RX_PRBS_BURST_ERR_LEN_STSr, 8122 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8123 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 8124 BCMI_FALCON_XGXS_TLB_RX_PRBS_BURST_ERR_LEN_STSr_fields, 8125 #else 8126 0, 8127 #endif 8128 #endif 8129 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8130 PHYMOD_SYMBOL_FLAG_REGISTER, 8131 "TLB_RX_PRBS_BURST_ERR_LEN_STSr", 8132 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8133 "TLB_RX_PRBS_BURST_ERR_LENGTH_STATUS", 8134 NULL, 8135 #endif 8136 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8137 0x0, /* 0 */ 8138 0, 8139 #endif 8140 }, 8141 { 8142 BCMI_FALCON_XGXS_TLB_RX_MAX_PRBS_BURST_ERR_LEN_STSr, 8143 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8144 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 8145 BCMI_FALCON_XGXS_TLB_RX_MAX_PRBS_BURST_ERR_LEN_STSr_fields, 8146 #else 8147 0, 8148 #endif 8149 #endif 8150 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8151 PHYMOD_SYMBOL_FLAG_REGISTER, 8152 "TLB_RX_MAX_PRBS_BURST_ERR_LEN_STSr", 8153 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8154 "TLB_RX_MAX_PRBS_BURST_ERR_LENGTH_STATUS", 8155 NULL, 8156 #endif 8157 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8158 0x0, /* 0 */ 8159 0, 8160 #endif 8161 }, 8162 { 8163 BCMI_FALCON_XGXS_TLB_TX_PATT_GEN_CFGr, 8164 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8165 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 8166 BCMI_FALCON_XGXS_TLB_TX_PATT_GEN_CFGr_fields, 8167 #else 8168 0, 8169 #endif 8170 #endif 8171 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8172 PHYMOD_SYMBOL_FLAG_REGISTER, 8173 "TLB_TX_PATT_GEN_CFGr", 8174 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8175 "TLB_TX_PATT_GEN_CONFIG", 8176 NULL, 8177 #endif 8178 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8179 0xb000, /* 45056 */ 8180 0, 8181 #endif 8182 }, 8183 { 8184 BCMI_FALCON_XGXS_TLB_TX_PRBS_GEN_CFGr, 8185 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8186 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 8187 BCMI_FALCON_XGXS_TLB_TX_PRBS_GEN_CFGr_fields, 8188 #else 8189 0, 8190 #endif 8191 #endif 8192 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8193 PHYMOD_SYMBOL_FLAG_REGISTER, 8194 "TLB_TX_PRBS_GEN_CFGr", 8195 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8196 "TLB_TX_PRBS_GEN_CONFIG", 8197 NULL, 8198 #endif 8199 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8200 0xa, /* 10 */ 8201 0, 8202 #endif 8203 }, 8204 { 8205 BCMI_FALCON_XGXS_TLB_TX_RMT_LPBK_CFGr, 8206 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8207 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 8208 BCMI_FALCON_XGXS_TLB_TX_RMT_LPBK_CFGr_fields, 8209 #else 8210 0, 8211 #endif 8212 #endif 8213 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8214 PHYMOD_SYMBOL_FLAG_REGISTER, 8215 "TLB_TX_RMT_LPBK_CFGr", 8216 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8217 "TLB_TX_RMT_LPBK_CONFIG", 8218 NULL, 8219 #endif 8220 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8221 0x2, /* 2 */ 8222 0, 8223 #endif 8224 }, 8225 { 8226 BCMI_FALCON_XGXS_TLB_TX_MISC_CFGr, 8227 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8228 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 8229 BCMI_FALCON_XGXS_TLB_TX_MISC_CFGr_fields, 8230 #else 8231 0, 8232 #endif 8233 #endif 8234 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8235 PHYMOD_SYMBOL_FLAG_REGISTER, 8236 "TLB_TX_MISC_CFGr", 8237 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8238 "TLB_TX_MISC_CONFIG", 8239 NULL, 8240 #endif 8241 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8242 0x0, /* 0 */ 8243 0, 8244 #endif 8245 }, 8246 { 8247 BCMI_FALCON_XGXS_TLB_TX_RMT_LPBK_PD_STSr, 8248 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8249 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 8250 BCMI_FALCON_XGXS_TLB_TX_RMT_LPBK_PD_STSr_fields, 8251 #else 8252 0, 8253 #endif 8254 #endif 8255 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8256 PHYMOD_SYMBOL_FLAG_REGISTER, 8257 "TLB_TX_RMT_LPBK_PD_STSr", 8258 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8259 "TLB_TX_RMT_LPBK_PD_STATUS", 8260 NULL, 8261 #endif 8262 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8263 0x2, /* 2 */ 8264 0, 8265 #endif 8266 }, 8267 { 8268 BCMI_FALCON_XGXS_UC_CLK_CTL0r, 8269 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8270 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 8271 BCMI_FALCON_XGXS_UC_CLK_CTL0r_fields, 8272 #else 8273 0, 8274 #endif 8275 #endif 8276 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8277 PHYMOD_SYMBOL_FLAG_REGISTER, 8278 "UC_CLK_CTL0r", 8279 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8280 "MICRO_A_COM_CLOCK_CONTROL0", 8281 NULL, 8282 #endif 8283 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8284 0x0, /* 0 */ 8285 0, 8286 #endif 8287 }, 8288 { 8289 BCMI_FALCON_XGXS_UC_RST_CTL0r, 8290 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8291 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 8292 BCMI_FALCON_XGXS_UC_RST_CTL0r_fields, 8293 #else 8294 0, 8295 #endif 8296 #endif 8297 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8298 PHYMOD_SYMBOL_FLAG_REGISTER, 8299 "UC_RST_CTL0r", 8300 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8301 "MICRO_A_COM_RESET_CONTROL0", 8302 NULL, 8303 #endif 8304 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8305 0x0, /* 0 */ 8306 0, 8307 #endif 8308 }, 8309 { 8310 BCMI_FALCON_XGXS_UC_AHB_CTL0r, 8311 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8312 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 8313 BCMI_FALCON_XGXS_UC_AHB_CTL0r_fields, 8314 #else 8315 0, 8316 #endif 8317 #endif 8318 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8319 PHYMOD_SYMBOL_FLAG_REGISTER, 8320 "UC_AHB_CTL0r", 8321 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8322 "MICRO_A_COM_AHB_CONTROL0", 8323 NULL, 8324 #endif 8325 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8326 0x0, /* 0 */ 8327 0, 8328 #endif 8329 }, 8330 { 8331 BCMI_FALCON_XGXS_UC_AHB_STS0r, 8332 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8333 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 8334 BCMI_FALCON_XGXS_UC_AHB_STS0r_fields, 8335 #else 8336 0, 8337 #endif 8338 #endif 8339 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8340 PHYMOD_SYMBOL_FLAG_REGISTER, 8341 "UC_AHB_STS0r", 8342 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8343 "MICRO_A_COM_AHB_STATUS0", 8344 NULL, 8345 #endif 8346 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8347 0x0, /* 0 */ 8348 0, 8349 #endif 8350 }, 8351 { 8352 BCMI_FALCON_XGXS_UC_AHB_WRADDR_LSWr, 8353 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8354 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 8355 BCMI_FALCON_XGXS_UC_AHB_WRADDR_LSWr_fields, 8356 #else 8357 0, 8358 #endif 8359 #endif 8360 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8361 PHYMOD_SYMBOL_FLAG_REGISTER, 8362 "UC_AHB_WRADDR_LSWr", 8363 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8364 "MICRO_A_COM_AHB_WRADDR_LSW", 8365 NULL, 8366 #endif 8367 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8368 0x0, /* 0 */ 8369 0, 8370 #endif 8371 }, 8372 { 8373 BCMI_FALCON_XGXS_UC_AHB_WRADDR_MSWr, 8374 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8375 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 8376 BCMI_FALCON_XGXS_UC_AHB_WRADDR_MSWr_fields, 8377 #else 8378 0, 8379 #endif 8380 #endif 8381 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8382 PHYMOD_SYMBOL_FLAG_REGISTER, 8383 "UC_AHB_WRADDR_MSWr", 8384 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8385 "MICRO_A_COM_AHB_WRADDR_MSW", 8386 NULL, 8387 #endif 8388 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8389 0x0, /* 0 */ 8390 0, 8391 #endif 8392 }, 8393 { 8394 BCMI_FALCON_XGXS_UC_AHB_WRDATA_LSWr, 8395 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8396 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 8397 BCMI_FALCON_XGXS_UC_AHB_WRDATA_LSWr_fields, 8398 #else 8399 0, 8400 #endif 8401 #endif 8402 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8403 PHYMOD_SYMBOL_FLAG_REGISTER, 8404 "UC_AHB_WRDATA_LSWr", 8405 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8406 "MICRO_A_COM_AHB_WRDATA_LSW", 8407 NULL, 8408 #endif 8409 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8410 0x0, /* 0 */ 8411 0, 8412 #endif 8413 }, 8414 { 8415 BCMI_FALCON_XGXS_UC_AHB_WRDATA_MSWr, 8416 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8417 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 8418 BCMI_FALCON_XGXS_UC_AHB_WRDATA_MSWr_fields, 8419 #else 8420 0, 8421 #endif 8422 #endif 8423 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8424 PHYMOD_SYMBOL_FLAG_REGISTER, 8425 "UC_AHB_WRDATA_MSWr", 8426 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8427 "MICRO_A_COM_AHB_WRDATA_MSW", 8428 NULL, 8429 #endif 8430 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8431 0x0, /* 0 */ 8432 0, 8433 #endif 8434 }, 8435 { 8436 BCMI_FALCON_XGXS_UC_AHB_RDADDR_LSWr, 8437 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8438 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 8439 BCMI_FALCON_XGXS_UC_AHB_RDADDR_LSWr_fields, 8440 #else 8441 0, 8442 #endif 8443 #endif 8444 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8445 PHYMOD_SYMBOL_FLAG_REGISTER, 8446 "UC_AHB_RDADDR_LSWr", 8447 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8448 "MICRO_A_COM_AHB_RDADDR_LSW", 8449 NULL, 8450 #endif 8451 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8452 0x0, /* 0 */ 8453 0, 8454 #endif 8455 }, 8456 { 8457 BCMI_FALCON_XGXS_UC_AHB_RDADDR_MSWr, 8458 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8459 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 8460 BCMI_FALCON_XGXS_UC_AHB_RDADDR_MSWr_fields, 8461 #else 8462 0, 8463 #endif 8464 #endif 8465 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8466 PHYMOD_SYMBOL_FLAG_REGISTER, 8467 "UC_AHB_RDADDR_MSWr", 8468 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8469 "MICRO_A_COM_AHB_RDADDR_MSW", 8470 NULL, 8471 #endif 8472 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8473 0x0, /* 0 */ 8474 0, 8475 #endif 8476 }, 8477 { 8478 BCMI_FALCON_XGXS_UC_AHB_RDDATA_LSWr, 8479 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8480 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 8481 BCMI_FALCON_XGXS_UC_AHB_RDDATA_LSWr_fields, 8482 #else 8483 0, 8484 #endif 8485 #endif 8486 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8487 PHYMOD_SYMBOL_FLAG_REGISTER, 8488 "UC_AHB_RDDATA_LSWr", 8489 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8490 "MICRO_A_COM_AHB_RDDATA_LSW", 8491 NULL, 8492 #endif 8493 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8494 0x0, /* 0 */ 8495 0, 8496 #endif 8497 }, 8498 { 8499 BCMI_FALCON_XGXS_UC_AHB_RDDATA_MSWr, 8500 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8501 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 8502 BCMI_FALCON_XGXS_UC_AHB_RDDATA_MSWr_fields, 8503 #else 8504 0, 8505 #endif 8506 #endif 8507 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8508 PHYMOD_SYMBOL_FLAG_REGISTER, 8509 "UC_AHB_RDDATA_MSWr", 8510 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8511 "MICRO_A_COM_AHB_RDDATA_MSW", 8512 NULL, 8513 #endif 8514 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8515 0x0, /* 0 */ 8516 0, 8517 #endif 8518 }, 8519 { 8520 BCMI_FALCON_XGXS_UC_PRAMIF_CTL0r, 8521 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8522 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 8523 BCMI_FALCON_XGXS_UC_PRAMIF_CTL0r_fields, 8524 #else 8525 0, 8526 #endif 8527 #endif 8528 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8529 PHYMOD_SYMBOL_FLAG_REGISTER, 8530 "UC_PRAMIF_CTL0r", 8531 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8532 "MICRO_A_COM_PRAMIF_CONTROL0", 8533 NULL, 8534 #endif 8535 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8536 0x0, /* 0 */ 8537 0, 8538 #endif 8539 }, 8540 { 8541 BCMI_FALCON_XGXS_UC_PRAMIF_AHB_WRADDR_LSWr, 8542 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8543 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 8544 BCMI_FALCON_XGXS_UC_PRAMIF_AHB_WRADDR_LSWr_fields, 8545 #else 8546 0, 8547 #endif 8548 #endif 8549 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8550 PHYMOD_SYMBOL_FLAG_REGISTER, 8551 "UC_PRAMIF_AHB_WRADDR_LSWr", 8552 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8553 "MICRO_A_COM_PRAMIF_AHB_WRADDR_LSW", 8554 NULL, 8555 #endif 8556 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8557 0x0, /* 0 */ 8558 0, 8559 #endif 8560 }, 8561 { 8562 BCMI_FALCON_XGXS_UC_PRAMIF_AHB_WRADDR_MSWr, 8563 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8564 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 8565 BCMI_FALCON_XGXS_UC_PRAMIF_AHB_WRADDR_MSWr_fields, 8566 #else 8567 0, 8568 #endif 8569 #endif 8570 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8571 PHYMOD_SYMBOL_FLAG_REGISTER, 8572 "UC_PRAMIF_AHB_WRADDR_MSWr", 8573 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8574 "MICRO_A_COM_PRAMIF_AHB_WRADDR_MSW", 8575 NULL, 8576 #endif 8577 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8578 0x0, /* 0 */ 8579 0, 8580 #endif 8581 }, 8582 { 8583 BCMI_FALCON_XGXS_UC_PVT_STS0r, 8584 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8585 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 8586 BCMI_FALCON_XGXS_UC_PVT_STS0r_fields, 8587 #else 8588 0, 8589 #endif 8590 #endif 8591 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8592 PHYMOD_SYMBOL_FLAG_REGISTER, 8593 "UC_PVT_STS0r", 8594 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8595 "MICRO_B_COM_PVT_STATUS0", 8596 NULL, 8597 #endif 8598 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8599 0x0, /* 0 */ 8600 0, 8601 #endif 8602 }, 8603 { 8604 BCMI_FALCON_XGXS_UC_RMI_TO_UC_MBOX0r, 8605 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8606 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 8607 BCMI_FALCON_XGXS_UC_RMI_TO_UC_MBOX0r_fields, 8608 #else 8609 0, 8610 #endif 8611 #endif 8612 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8613 PHYMOD_SYMBOL_FLAG_REGISTER, 8614 "UC_RMI_TO_UC_MBOX0r", 8615 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8616 "MICRO_B_COM_RMI_TO_MICRO_MBOX0", 8617 NULL, 8618 #endif 8619 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8620 0x0, /* 0 */ 8621 0, 8622 #endif 8623 }, 8624 { 8625 BCMI_FALCON_XGXS_UC_RMI_TO_UC_MBOX1r, 8626 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8627 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 8628 BCMI_FALCON_XGXS_UC_RMI_TO_UC_MBOX1r_fields, 8629 #else 8630 0, 8631 #endif 8632 #endif 8633 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8634 PHYMOD_SYMBOL_FLAG_REGISTER, 8635 "UC_RMI_TO_UC_MBOX1r", 8636 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8637 "MICRO_B_COM_RMI_TO_MICRO_MBOX1", 8638 NULL, 8639 #endif 8640 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8641 0x0, /* 0 */ 8642 0, 8643 #endif 8644 }, 8645 { 8646 BCMI_FALCON_XGXS_UC_UC_TO_RMI_MBOX0r, 8647 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8648 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 8649 BCMI_FALCON_XGXS_UC_UC_TO_RMI_MBOX0r_fields, 8650 #else 8651 0, 8652 #endif 8653 #endif 8654 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8655 PHYMOD_SYMBOL_FLAG_REGISTER, 8656 "UC_UC_TO_RMI_MBOX0r", 8657 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8658 "MICRO_B_COM_MICRO_TO_RMI_MBOX0", 8659 NULL, 8660 #endif 8661 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8662 0x0, /* 0 */ 8663 0, 8664 #endif 8665 }, 8666 { 8667 BCMI_FALCON_XGXS_UC_UC_TO_RMI_MBOX1r, 8668 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8669 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 8670 BCMI_FALCON_XGXS_UC_UC_TO_RMI_MBOX1r_fields, 8671 #else 8672 0, 8673 #endif 8674 #endif 8675 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8676 PHYMOD_SYMBOL_FLAG_REGISTER, 8677 "UC_UC_TO_RMI_MBOX1r", 8678 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8679 "MICRO_B_COM_MICRO_TO_RMI_MBOX1", 8680 NULL, 8681 #endif 8682 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8683 0x0, /* 0 */ 8684 0, 8685 #endif 8686 }, 8687 { 8688 BCMI_FALCON_XGXS_UC_RMI_MBOX_CTL0r, 8689 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8690 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 8691 BCMI_FALCON_XGXS_UC_RMI_MBOX_CTL0r_fields, 8692 #else 8693 0, 8694 #endif 8695 #endif 8696 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8697 PHYMOD_SYMBOL_FLAG_REGISTER, 8698 "UC_RMI_MBOX_CTL0r", 8699 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8700 "MICRO_B_COM_RMI_MBOX_CONTROL0", 8701 NULL, 8702 #endif 8703 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8704 0x0, /* 0 */ 8705 0, 8706 #endif 8707 }, 8708 { 8709 BCMI_FALCON_XGXS_UC_RMI_AHB_CTL1r, 8710 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8711 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 8712 BCMI_FALCON_XGXS_UC_RMI_AHB_CTL1r_fields, 8713 #else 8714 0, 8715 #endif 8716 #endif 8717 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8718 PHYMOD_SYMBOL_FLAG_REGISTER, 8719 "UC_RMI_AHB_CTL1r", 8720 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8721 "MICRO_B_COM_RMI_AHB_CONTROL1", 8722 NULL, 8723 #endif 8724 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8725 0x7, /* 7 */ 8726 0, 8727 #endif 8728 }, 8729 { 8730 BCMI_FALCON_XGXS_UC_RMI_AHB_STS1r, 8731 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8732 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 8733 BCMI_FALCON_XGXS_UC_RMI_AHB_STS1r_fields, 8734 #else 8735 0, 8736 #endif 8737 #endif 8738 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8739 PHYMOD_SYMBOL_FLAG_REGISTER, 8740 "UC_RMI_AHB_STS1r", 8741 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8742 "MICRO_B_COM_RMI_AHB_STATUS1", 8743 NULL, 8744 #endif 8745 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8746 0x0, /* 0 */ 8747 0, 8748 #endif 8749 }, 8750 { 8751 BCMI_FALCON_XGXS_UC_RMI_RA_AINC_NXT_WRADDR_LSWr, 8752 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8753 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 8754 BCMI_FALCON_XGXS_UC_RMI_RA_AINC_NXT_WRADDR_LSWr_fields, 8755 #else 8756 0, 8757 #endif 8758 #endif 8759 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8760 PHYMOD_SYMBOL_FLAG_REGISTER, 8761 "UC_RMI_RA_AINC_NXT_WRADDR_LSWr", 8762 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8763 "MICRO_B_COM_RMI_RA_AUTOINC_NXT_WRADDR_LSW", 8764 NULL, 8765 #endif 8766 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8767 0x0, /* 0 */ 8768 0, 8769 #endif 8770 }, 8771 { 8772 BCMI_FALCON_XGXS_UC_RMI_RA_AINC_NXT_RDADDR_LSWr, 8773 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8774 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 8775 BCMI_FALCON_XGXS_UC_RMI_RA_AINC_NXT_RDADDR_LSWr_fields, 8776 #else 8777 0, 8778 #endif 8779 #endif 8780 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8781 PHYMOD_SYMBOL_FLAG_REGISTER, 8782 "UC_RMI_RA_AINC_NXT_RDADDR_LSWr", 8783 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8784 "MICRO_B_COM_RMI_RA_AUTOINC_NXT_RDADDR_LSW", 8785 NULL, 8786 #endif 8787 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8788 0x0, /* 0 */ 8789 0, 8790 #endif 8791 }, 8792 { 8793 BCMI_FALCON_XGXS_UC_RMI_PR_AINC_NXT_WRADDR_LSWr, 8794 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8795 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 8796 BCMI_FALCON_XGXS_UC_RMI_PR_AINC_NXT_WRADDR_LSWr_fields, 8797 #else 8798 0, 8799 #endif 8800 #endif 8801 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8802 PHYMOD_SYMBOL_FLAG_REGISTER, 8803 "UC_RMI_PR_AINC_NXT_WRADDR_LSWr", 8804 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8805 "MICRO_B_COM_RMI_PR_AUTOINC_NXT_WRADDR_LSW", 8806 NULL, 8807 #endif 8808 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8809 0x0, /* 0 */ 8810 0, 8811 #endif 8812 }, 8813 { 8814 BCMI_FALCON_XGXS_UC_RMI_PVT_CTL0r, 8815 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8816 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 8817 BCMI_FALCON_XGXS_UC_RMI_PVT_CTL0r_fields, 8818 #else 8819 0, 8820 #endif 8821 #endif 8822 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8823 PHYMOD_SYMBOL_FLAG_REGISTER, 8824 "UC_RMI_PVT_CTL0r", 8825 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8826 "MICRO_B_COM_RMI_PVT_CONTROL0", 8827 NULL, 8828 #endif 8829 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8830 0x0, /* 0 */ 8831 0, 8832 #endif 8833 }, 8834 { 8835 BCMI_FALCON_XGXS_UC_CODE_RAM_ECCCTL0r, 8836 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8837 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 8838 BCMI_FALCON_XGXS_UC_CODE_RAM_ECCCTL0r_fields, 8839 #else 8840 0, 8841 #endif 8842 #endif 8843 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8844 PHYMOD_SYMBOL_FLAG_REGISTER, 8845 "UC_CODE_RAM_ECCCTL0r", 8846 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8847 "MICRO_C_COM_CODE_RAM_ECCCONTROL0", 8848 NULL, 8849 #endif 8850 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8851 0x0, /* 0 */ 8852 0, 8853 #endif 8854 }, 8855 { 8856 BCMI_FALCON_XGXS_UC_CODE_RAM_ECCCONTRO1r, 8857 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8858 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 8859 BCMI_FALCON_XGXS_UC_CODE_RAM_ECCCONTRO1r_fields, 8860 #else 8861 0, 8862 #endif 8863 #endif 8864 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8865 PHYMOD_SYMBOL_FLAG_REGISTER, 8866 "UC_CODE_RAM_ECCCONTRO1r", 8867 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8868 "MICRO_C_COM_CODE_RAM_ECCCONTRO1", 8869 NULL, 8870 #endif 8871 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8872 0x0, /* 0 */ 8873 0, 8874 #endif 8875 }, 8876 { 8877 BCMI_FALCON_XGXS_UC_CODE_RAM_ECCSTS0r, 8878 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8879 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 8880 BCMI_FALCON_XGXS_UC_CODE_RAM_ECCSTS0r_fields, 8881 #else 8882 0, 8883 #endif 8884 #endif 8885 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8886 PHYMOD_SYMBOL_FLAG_REGISTER, 8887 "UC_CODE_RAM_ECCSTS0r", 8888 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8889 "MICRO_C_COM_CODE_RAM_ECCSTATUS0", 8890 NULL, 8891 #endif 8892 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8893 0x0, /* 0 */ 8894 0, 8895 #endif 8896 }, 8897 { 8898 BCMI_FALCON_XGXS_UC_CODE_RAM_ECCSTS1r, 8899 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8900 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 8901 BCMI_FALCON_XGXS_UC_CODE_RAM_ECCSTS1r_fields, 8902 #else 8903 0, 8904 #endif 8905 #endif 8906 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8907 PHYMOD_SYMBOL_FLAG_REGISTER, 8908 "UC_CODE_RAM_ECCSTS1r", 8909 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8910 "MICRO_C_COM_CODE_RAM_ECCSTATUS1", 8911 NULL, 8912 #endif 8913 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8914 0x0, /* 0 */ 8915 0, 8916 #endif 8917 }, 8918 { 8919 BCMI_FALCON_XGXS_UC_CODE_RAM_TESTIFCTL0r, 8920 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8921 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 8922 BCMI_FALCON_XGXS_UC_CODE_RAM_TESTIFCTL0r_fields, 8923 #else 8924 0, 8925 #endif 8926 #endif 8927 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8928 PHYMOD_SYMBOL_FLAG_REGISTER, 8929 "UC_CODE_RAM_TESTIFCTL0r", 8930 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8931 "MICRO_C_COM_CODE_RAM_TESTIFCONTROL0", 8932 NULL, 8933 #endif 8934 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8935 0x0, /* 0 */ 8936 0, 8937 #endif 8938 }, 8939 { 8940 BCMI_FALCON_XGXS_UC_RAM_CTL0r, 8941 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8942 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 8943 BCMI_FALCON_XGXS_UC_RAM_CTL0r_fields, 8944 #else 8945 0, 8946 #endif 8947 #endif 8948 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8949 PHYMOD_SYMBOL_FLAG_REGISTER, 8950 "UC_RAM_CTL0r", 8951 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8952 "MICRO_C_COM_RAM_CONTROL0", 8953 NULL, 8954 #endif 8955 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8956 0x401, /* 1025 */ 8957 0, 8958 #endif 8959 }, 8960 { 8961 BCMI_FALCON_XGXS_UC_RMI_EXT_INTR_CTL0r, 8962 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8963 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 8964 BCMI_FALCON_XGXS_UC_RMI_EXT_INTR_CTL0r_fields, 8965 #else 8966 0, 8967 #endif 8968 #endif 8969 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8970 PHYMOD_SYMBOL_FLAG_REGISTER, 8971 "UC_RMI_EXT_INTR_CTL0r", 8972 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8973 "MICRO_C_COM_RMI_EXT_INTR_CONTROL0", 8974 NULL, 8975 #endif 8976 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8977 0x0, /* 0 */ 8978 0, 8979 #endif 8980 }, 8981 { 8982 BCMI_FALCON_XGXS_UC_RMI_EXT_INTR_STS0r, 8983 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8984 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 8985 BCMI_FALCON_XGXS_UC_RMI_EXT_INTR_STS0r_fields, 8986 #else 8987 0, 8988 #endif 8989 #endif 8990 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8991 PHYMOD_SYMBOL_FLAG_REGISTER, 8992 "UC_RMI_EXT_INTR_STS0r", 8993 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8994 "MICRO_C_COM_RMI_EXT_INTR_STATUS0", 8995 NULL, 8996 #endif 8997 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8998 0x0, /* 0 */ 8999 0, 9000 #endif 9001 }, 9002 { 9003 BCMI_FALCON_XGXS_MDIO_MASKDATAr, 9004 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9005 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 9006 BCMI_FALCON_XGXS_MDIO_MASKDATAr_fields, 9007 #else 9008 0, 9009 #endif 9010 #endif 9011 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9012 PHYMOD_SYMBOL_FLAG_REGISTER, 9013 "MDIO_MASKDATAr", 9014 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9015 "MDIO_MMDSEL_AER_COM_MDIO_MASKDATA", 9016 NULL, 9017 #endif 9018 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9019 0x0, /* 0 */ 9020 0, 9021 #endif 9022 }, 9023 { 9024 BCMI_FALCON_XGXS_MDIO_BCST_PORT_ADDRr, 9025 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9026 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 9027 BCMI_FALCON_XGXS_MDIO_BCST_PORT_ADDRr_fields, 9028 #else 9029 0, 9030 #endif 9031 #endif 9032 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9033 PHYMOD_SYMBOL_FLAG_REGISTER, 9034 "MDIO_BCST_PORT_ADDRr", 9035 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9036 "MDIO_MMDSEL_AER_COM_MDIO_BRCST_PORT_ADDR", 9037 NULL, 9038 #endif 9039 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9040 0x1f, /* 31 */ 9041 0, 9042 #endif 9043 }, 9044 { 9045 BCMI_FALCON_XGXS_MDIO_MMD_SELr, 9046 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9047 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 9048 BCMI_FALCON_XGXS_MDIO_MMD_SELr_fields, 9049 #else 9050 0, 9051 #endif 9052 #endif 9053 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9054 PHYMOD_SYMBOL_FLAG_REGISTER, 9055 "MDIO_MMD_SELr", 9056 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9057 "MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT", 9058 NULL, 9059 #endif 9060 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9061 0x404d, /* 16461 */ 9062 0, 9063 #endif 9064 }, 9065 { 9066 BCMI_FALCON_XGXS_MDIO_AERr, 9067 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9068 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 9069 BCMI_FALCON_XGXS_MDIO_AERr_fields, 9070 #else 9071 0, 9072 #endif 9073 #endif 9074 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9075 PHYMOD_SYMBOL_FLAG_REGISTER, 9076 "MDIO_AERr", 9077 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9078 "MDIO_MMDSEL_AER_COM_MDIO_AER", 9079 NULL, 9080 #endif 9081 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9082 0x0, /* 0 */ 9083 0, 9084 #endif 9085 }, 9086 { 9087 BCMI_FALCON_XGXS_MDIO_BLK_ADDRr, 9088 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 9089 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS 9090 BCMI_FALCON_XGXS_MDIO_BLK_ADDRr_fields, 9091 #else 9092 0, 9093 #endif 9094 #endif 9095 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 9096 PHYMOD_SYMBOL_FLAG_REGISTER, 9097 "MDIO_BLK_ADDRr", 9098 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 9099 "MDIO_BLK_ADDR_COM_BLK_ADDR", 9100 NULL, 9101 #endif 9102 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 9103 0x0, /* 0 */ 9104 0, 9105 #endif 9106 }, 9107 #endif 9108 }; 9109 9110 9111 phymod_symbols_t bcmi_falcon_xgxs_symbols = 9112 { 9113 bcmi_falcon_xgxs_syms, sizeof(bcmi_falcon_xgxs_syms)/sizeof(bcmi_falcon_xgxs_syms[0]), 9114 #if PHYMOD_CONFIG_INCLUDE_FIELD_NAMES == 1 9115 bcmi_falcon_xgxs_fields 9116 #else 9117 NULL 9118 #endif 9119 /* END OF SYMBOL FILE */ 9120 }; 9121 9122 #endif /* PHYMOD_CONFIG_INCLUDE_CHIP_SYMBOLS */