bcmi_eagle_xgxs_sym.c (214921B)
1 /******************************************************************************* 2 * 3 * 4 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 5 * 6 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 7 * 8 * DO NOT EDIT THIS FILE! 9 * This file is auto-generated from the registers file. 10 * Edits to this file will be lost when it is regenerated. 11 * 12 * Symbol table file for the BCMI_EAGLE_XGXS. 13 * This symbol table is used by the Broadcom debug shell. 14 */ 15 16 17 #include <phymod/chip/bcmi_eagle_xgxs_defs.h> 18 #include <phymod/phymod_symbols.h> 19 20 /* No symbols will be compiled unless this is defined. */ 21 #if PHYMOD_CONFIG_INCLUDE_CHIP_SYMBOLS == 1 22 /******************************************************************************* 23 * 24 * If PHYMOD_CONFIG_INCLUDE_FIELD_INFO is 1, then symbol information 25 * necessary to encode and decode the individual fields of a register or memory 26 * will be available. 27 * 28 * Without it, only the register and memory names will be symbolically available 29 * and their values will be displayed as raw data only. 30 * 31 * Field information can be compiled out in the interest of saving code space. 32 */ 33 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 34 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 35 36 static uint32_t BCMI_EAGLE_XGXS_ACC_ADDR_DATAr_fields[] = 37 { 38 /* MDIO_ADDR_DATA:0:15 */ 39 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(443, 15, 0) 40 }; 41 static uint32_t BCMI_EAGLE_XGXS_ACC_CTLr_fields[] = 42 { 43 /* MDIO_DEVAD:0:4 */ 44 PHYMOD_SYMBOL_FIELD_ENCODE(447, 4, 0), 45 /* MDIO_FUNCTION:14:15 */ 46 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(454, 15, 14) 47 }; 48 static uint32_t BCMI_EAGLE_XGXS_AMS_CTL0r_fields[] = 49 { 50 /* AMS_PLL_LOWPWR_6G:0:0 */ 51 PHYMOD_SYMBOL_FIELD_ENCODE(72, 0, 0), 52 /* AMS_PLL_TXCG_VDDR_BGB:1:1 */ 53 PHYMOD_SYMBOL_FIELD_ENCODE(92, 1, 1), 54 /* AMS_PLL_IMIN_ICLKINT:2:2 */ 55 PHYMOD_SYMBOL_FIELD_ENCODE(54, 2, 2), 56 /* AMS_PLL_IMAX_ICLKINT:3:3 */ 57 PHYMOD_SYMBOL_FIELD_ENCODE(44, 3, 3), 58 /* AMS_PLL_IMODE_ICLKINT:4:4 */ 59 PHYMOD_SYMBOL_FIELD_ENCODE(64, 4, 4), 60 /* AMS_PLL_IMIN_ICKGEN:5:5 */ 61 PHYMOD_SYMBOL_FIELD_ENCODE(52, 5, 5), 62 /* AMS_PLL_IMAX_ICKGEN:6:6 */ 63 PHYMOD_SYMBOL_FIELD_ENCODE(42, 6, 6), 64 /* AMS_PLL_IMODE_ICKGEN:7:7 */ 65 PHYMOD_SYMBOL_FIELD_ENCODE(62, 7, 7), 66 /* AMS_PLL_IMIN_ICLKIDRV1:8:8 */ 67 PHYMOD_SYMBOL_FIELD_ENCODE(53, 8, 8), 68 /* AMS_PLL_IMAX_ICLKIDRV1:9:9 */ 69 PHYMOD_SYMBOL_FIELD_ENCODE(43, 9, 9), 70 /* AMS_PLL_IMODE_ICLKIDRV1:10:10 */ 71 PHYMOD_SYMBOL_FIELD_ENCODE(63, 10, 10), 72 /* AMS_PLL_CAL_OFF:11:11 */ 73 PHYMOD_SYMBOL_FIELD_ENCODE(23, 11, 11), 74 /* AMS_PLL_CAL_AUX:12:15 */ 75 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(22, 15, 12) 76 }; 77 static uint32_t BCMI_EAGLE_XGXS_AMS_CTL1r_fields[] = 78 { 79 /* AMS_PLL_DBLR_CTRL:0:1 */ 80 PHYMOD_SYMBOL_FIELD_ENCODE(25, 1, 0), 81 /* AMS_PLL_SPARE_18:2:2 */ 82 PHYMOD_SYMBOL_FIELD_ENCODE(84, 2, 2), 83 /* AMS_PLL_FP3_RH:3:3 */ 84 PHYMOD_SYMBOL_FIELD_ENCODE(32, 3, 3), 85 /* AMS_PLL_FP3_CTRL:4:5 */ 86 PHYMOD_SYMBOL_FIELD_ENCODE(31, 5, 4), 87 /* AMS_PLL_VCO_DIV2:6:6 */ 88 PHYMOD_SYMBOL_FIELD_ENCODE(96, 6, 6), 89 /* AMS_PLL_VCO_DIV4:7:7 */ 90 PHYMOD_SYMBOL_FIELD_ENCODE(97, 7, 7), 91 /* AMS_PLL_VCOICTRL:8:9 */ 92 PHYMOD_SYMBOL_FIELD_ENCODE(95, 9, 8), 93 /* AMS_PLL_VCO_IMAX:10:10 */ 94 PHYMOD_SYMBOL_FIELD_ENCODE(98, 10, 10), 95 /* AMS_PLL_IVCO:11:13 */ 96 PHYMOD_SYMBOL_FIELD_ENCODE(70, 13, 11), 97 /* AMS_PLL_RESET:14:14 */ 98 PHYMOD_SYMBOL_FIELD_ENCODE(82, 14, 14), 99 /* AMS_PLL_ENABLE_FTUNE:15:15 */ 100 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(27, 15, 15) 101 }; 102 static uint32_t BCMI_EAGLE_XGXS_AMS_CTL2r_fields[] = 103 { 104 /* AMS_PLL_EN_HRZ:0:0 */ 105 PHYMOD_SYMBOL_FIELD_ENCODE(28, 0, 0), 106 /* AMS_PLL_IQP:1:4 */ 107 PHYMOD_SYMBOL_FIELD_ENCODE(69, 4, 1), 108 /* AMS_PLL_REFL_PLL:5:5 */ 109 PHYMOD_SYMBOL_FIELD_ENCODE(81, 5, 5), 110 /* AMS_PLL_REFH_PLL:6:6 */ 111 PHYMOD_SYMBOL_FIELD_ENCODE(80, 6, 6), 112 /* AMS_PLL_IMIN_IBIAS:7:7 */ 113 PHYMOD_SYMBOL_FIELD_ENCODE(50, 7, 7), 114 /* AMS_PLL_IMODE_IBIAS:8:8 */ 115 PHYMOD_SYMBOL_FIELD_ENCODE(60, 8, 8), 116 /* AMS_PLL_IMAX_IBIAS:9:9 */ 117 PHYMOD_SYMBOL_FIELD_ENCODE(40, 9, 9), 118 /* AMS_PLL_IMIN_ICP:10:10 */ 119 PHYMOD_SYMBOL_FIELD_ENCODE(57, 10, 10), 120 /* AMS_PLL_IMODE_ICP:11:11 */ 121 PHYMOD_SYMBOL_FIELD_ENCODE(67, 11, 11), 122 /* AMS_PLL_IMAX_ICP:12:12 */ 123 PHYMOD_SYMBOL_FIELD_ENCODE(47, 12, 12), 124 /* AMS_PLL_IMIN_ICK:13:13 */ 125 PHYMOD_SYMBOL_FIELD_ENCODE(51, 13, 13), 126 /* AMS_PLL_IMODE_ICK:14:14 */ 127 PHYMOD_SYMBOL_FIELD_ENCODE(61, 14, 14), 128 /* AMS_PLL_IMAX_ICK:15:15 */ 129 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(41, 15, 15) 130 }; 131 static uint32_t BCMI_EAGLE_XGXS_AMS_CTL3r_fields[] = 132 { 133 /* AMS_PLL_IMIN_I10GBUF:0:0 */ 134 PHYMOD_SYMBOL_FIELD_ENCODE(49, 0, 0), 135 /* AMS_PLL_IMODE_I10GBUF:1:1 */ 136 PHYMOD_SYMBOL_FIELD_ENCODE(59, 1, 1), 137 /* AMS_PLL_IMAX_I10GBUF:2:2 */ 138 PHYMOD_SYMBOL_FIELD_ENCODE(39, 2, 2), 139 /* AMS_PLL_IMIN_ICML:3:3 */ 140 PHYMOD_SYMBOL_FIELD_ENCODE(55, 3, 3), 141 /* AMS_PLL_IMODE_ICML:4:4 */ 142 PHYMOD_SYMBOL_FIELD_ENCODE(65, 4, 4), 143 /* AMS_PLL_IMAX_ICML:5:5 */ 144 PHYMOD_SYMBOL_FIELD_ENCODE(45, 5, 5), 145 /* AMS_PLL_IMIN_ICOMP:6:6 */ 146 PHYMOD_SYMBOL_FIELD_ENCODE(56, 6, 6), 147 /* AMS_PLL_IMODE_ICOMP:7:7 */ 148 PHYMOD_SYMBOL_FIELD_ENCODE(66, 7, 7), 149 /* AMS_PLL_IMAX_ICOMP:8:8 */ 150 PHYMOD_SYMBOL_FIELD_ENCODE(46, 8, 8), 151 /* AMS_PLL_IMIN_IOP:9:9 */ 152 PHYMOD_SYMBOL_FIELD_ENCODE(58, 9, 9), 153 /* AMS_PLL_IMODE_IOP:10:10 */ 154 PHYMOD_SYMBOL_FIELD_ENCODE(68, 10, 10), 155 /* AMS_PLL_IMAX_IOP:11:11 */ 156 PHYMOD_SYMBOL_FIELD_ENCODE(48, 11, 11), 157 /* AMS_PLL_TEST_VREF:12:12 */ 158 PHYMOD_SYMBOL_FIELD_ENCODE(91, 12, 12), 159 /* AMS_PLL_TEST_VC:13:13 */ 160 PHYMOD_SYMBOL_FIELD_ENCODE(90, 13, 13), 161 /* AMS_PLL_TEST_PLL:14:14 */ 162 PHYMOD_SYMBOL_FIELD_ENCODE(87, 14, 14), 163 /* AMS_PLL_TEST_RX:15:15 */ 164 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(89, 15, 15) 165 }; 166 static uint32_t BCMI_EAGLE_XGXS_AMS_CTL4r_fields[] = 167 { 168 /* AMS_PLL_BGR_PTATADJ:0:3 */ 169 PHYMOD_SYMBOL_FIELD_ENCODE(21, 3, 0), 170 /* AMS_PLL_BGR_CTATADJ:4:7 */ 171 PHYMOD_SYMBOL_FIELD_ENCODE(20, 7, 4), 172 /* AMS_PLL_2RX_CLKBW:8:9 */ 173 PHYMOD_SYMBOL_FIELD_ENCODE(15, 9, 8), 174 /* AMS_PLL_COMP_VTH:10:10 */ 175 PHYMOD_SYMBOL_FIELD_ENCODE(24, 10, 10), 176 /* AMS_PLL_VDDR_BGB:11:11 */ 177 PHYMOD_SYMBOL_FIELD_ENCODE(99, 11, 11), 178 /* AMS_PLL_KVH_FORCE:12:13 */ 179 PHYMOD_SYMBOL_FIELD_ENCODE(71, 13, 12), 180 /* AMS_PLL_FORCE_KVH_BW:14:14 */ 181 PHYMOD_SYMBOL_FIELD_ENCODE(29, 14, 14), 182 /* AMS_PLL_FORCE_RESCAL:15:15 */ 183 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(30, 15, 15) 184 }; 185 static uint32_t BCMI_EAGLE_XGXS_AMS_CTL5r_fields[] = 186 { 187 /* AMS_PLL_MAX_TEST_PORT_AMPL:0:0 */ 188 PHYMOD_SYMBOL_FIELD_ENCODE(73, 0, 0), 189 /* AMS_PLL_BGIP:1:1 */ 190 PHYMOD_SYMBOL_FIELD_ENCODE(19, 1, 1), 191 /* AMS_PLL_BGINT:2:2 */ 192 PHYMOD_SYMBOL_FIELD_ENCODE(18, 2, 2), 193 /* AMS_PLL_VBYPASS:3:3 */ 194 PHYMOD_SYMBOL_FIELD_ENCODE(94, 3, 3), 195 /* AMS_PLL_TEST_PNP:4:5 */ 196 PHYMOD_SYMBOL_FIELD_ENCODE(88, 5, 4), 197 /* AMS_PLL_BGCALR_CTATADJ:6:10 */ 198 PHYMOD_SYMBOL_FIELD_ENCODE(16, 10, 6), 199 /* AMS_PLL_BGCALR_PTATADJ:11:15 */ 200 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(17, 15, 11) 201 }; 202 static uint32_t BCMI_EAGLE_XGXS_AMS_CTL6r_fields[] = 203 { 204 /* AMS_PLL_TEST_FRACN_EN:0:0 */ 205 PHYMOD_SYMBOL_FIELD_ENCODE(86, 0, 0), 206 /* AMS_PLL_PDF_SKEW_ENLARGE:1:1 */ 207 PHYMOD_SYMBOL_FIELD_ENCODE(78, 1, 1), 208 /* AMS_PLL_PDF_FD_SKEW:2:2 */ 209 PHYMOD_SYMBOL_FIELD_ENCODE(76, 2, 2), 210 /* AMS_PLL_PDF_REF_SKEW:3:3 */ 211 PHYMOD_SYMBOL_FIELD_ENCODE(77, 3, 3), 212 /* AMS_PLL_SPARE_100:4:4 */ 213 PHYMOD_SYMBOL_FIELD_ENCODE(83, 4, 4), 214 /* AMS_PLL_REFCLK_DOUBLER:5:5 */ 215 PHYMOD_SYMBOL_FIELD_ENCODE(79, 5, 5), 216 /* AMS_PLL_MIX2P1CR_CTATADJ:6:10 */ 217 PHYMOD_SYMBOL_FIELD_ENCODE(74, 10, 6), 218 /* AMS_PLL_MIX2P1CR_PTATADJ:11:15 */ 219 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(75, 15, 11) 220 }; 221 static uint32_t BCMI_EAGLE_XGXS_AMS_CTL7r_fields[] = 222 { 223 /* AMS_PLL_FRACN_DIV_L:0:15 */ 224 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(36, 15, 0) 225 }; 226 static uint32_t BCMI_EAGLE_XGXS_AMS_CTL8r_fields[] = 227 { 228 /* AMS_PLL_FRACN_DIV_H:0:1 */ 229 PHYMOD_SYMBOL_FIELD_ENCODE(35, 1, 0), 230 /* AMS_PLL_FRACN_DIVRANGE:2:2 */ 231 PHYMOD_SYMBOL_FIELD_ENCODE(34, 2, 2), 232 /* AMS_PLL_FRACN_BYPASS:3:3 */ 233 PHYMOD_SYMBOL_FIELD_ENCODE(33, 3, 3), 234 /* AMS_PLL_FRACN_NDIV_INT:4:13 */ 235 PHYMOD_SYMBOL_FIELD_ENCODE(37, 13, 4), 236 /* AMS_PLL_DITHEREN:14:14 */ 237 PHYMOD_SYMBOL_FIELD_ENCODE(26, 14, 14), 238 /* AMS_PLL_FRACN_SEL:15:15 */ 239 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(38, 15, 15) 240 }; 241 static uint32_t BCMI_EAGLE_XGXS_AMS_INTCTLr_fields[] = 242 { 243 /* AMS_PLL_TX_LOWPWR_6G:0:0 */ 244 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(93, 0, 0) 245 }; 246 static uint32_t BCMI_EAGLE_XGXS_AMS_RX_CTL0r_fields[] = 247 { 248 /* AMS_RX_SEL_DFECKDELAY:0:1 */ 249 PHYMOD_SYMBOL_FIELD_ENCODE(147, 1, 0), 250 /* AMS_RX_PHASE_INT_AMPL_CTRL:2:2 */ 251 PHYMOD_SYMBOL_FIELD_ENCODE(145, 2, 2), 252 /* AMS_RX_SIGDET_THRESHOLD:3:5 */ 253 PHYMOD_SYMBOL_FIELD_ENCODE(152, 5, 3), 254 /* AMS_RX_SIG_PWRDN:6:6 */ 255 PHYMOD_SYMBOL_FIELD_ENCODE(153, 6, 6), 256 /* AMS_RX_VGA_OUTPUT_IDLE:7:7 */ 257 PHYMOD_SYMBOL_FIELD_ENCODE(164, 7, 7), 258 /* AMS_RX_TPORT_EN:8:8 */ 259 PHYMOD_SYMBOL_FIELD_ENCODE(162, 8, 8), 260 /* AMS_RX_SIGDET_BYPASS:9:9 */ 261 PHYMOD_SYMBOL_FIELD_ENCODE(150, 9, 9), 262 /* AMS_RX_SIGDET_LOW_POWER:10:10 */ 263 PHYMOD_SYMBOL_FIELD_ENCODE(151, 10, 10), 264 /* AMS_RX_VGA_BW_EXTENSION:11:11 */ 265 PHYMOD_SYMBOL_FIELD_ENCODE(163, 11, 11), 266 /* AMS_RX_DC_COUPLE:12:12 */ 267 PHYMOD_SYMBOL_FIELD_ENCODE(100, 12, 12), 268 /* AMS_RX_EN_10GMODE:13:13 */ 269 PHYMOD_SYMBOL_FIELD_ENCODE(104, 13, 13), 270 /* AMS_RX_IMIN_COMMONMODE:14:14 */ 271 PHYMOD_SYMBOL_FIELD_ENCODE(121, 14, 14), 272 /* AMS_RX_IMOD_COMMONMODE:15:15 */ 273 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(144, 15, 15) 274 }; 275 static uint32_t BCMI_EAGLE_XGXS_AMS_RX_CTL1r_fields[] = 276 { 277 /* AMS_RX_IMAX_COMMONMODE:0:0 */ 278 PHYMOD_SYMBOL_FIELD_ENCODE(109, 0, 0), 279 /* AMS_RX_IMIN_PHASE_INT:1:1 */ 280 PHYMOD_SYMBOL_FIELD_ENCODE(128, 1, 1), 281 /* AMS_RX_IMODE_PHASE_INT:2:2 */ 282 PHYMOD_SYMBOL_FIELD_ENCODE(139, 2, 2), 283 /* AMS_RX_IMAX_PHASE_INT:3:3 */ 284 PHYMOD_SYMBOL_FIELD_ENCODE(116, 3, 3), 285 /* AMS_RX_IMIN_VGA:4:4 */ 286 PHYMOD_SYMBOL_FIELD_ENCODE(132, 4, 4), 287 /* AMS_RX_IMODE_VGA:5:5 */ 288 PHYMOD_SYMBOL_FIELD_ENCODE(143, 5, 5), 289 /* AMS_RX_IMAX_VGA:6:6 */ 290 PHYMOD_SYMBOL_FIELD_ENCODE(120, 6, 6), 291 /* AMS_RX_IMIN_DFE_SUMMER:7:7 */ 292 PHYMOD_SYMBOL_FIELD_ENCODE(124, 7, 7), 293 /* AMS_RX_IMODE_DFE_SUMMER:8:8 */ 294 PHYMOD_SYMBOL_FIELD_ENCODE(135, 8, 8), 295 /* AMS_RX_IMAX_DFE_SUMMER:9:9 */ 296 PHYMOD_SYMBOL_FIELD_ENCODE(112, 9, 9), 297 /* AMS_RX_IMIN_PF:10:10 */ 298 PHYMOD_SYMBOL_FIELD_ENCODE(127, 10, 10), 299 /* AMS_RX_IMODE_PF:11:11 */ 300 PHYMOD_SYMBOL_FIELD_ENCODE(138, 11, 11), 301 /* AMS_RX_IMAX_PF:12:12 */ 302 PHYMOD_SYMBOL_FIELD_ENCODE(115, 12, 12), 303 /* AMS_RX_IMIN_CTAT:13:13 */ 304 PHYMOD_SYMBOL_FIELD_ENCODE(122, 13, 13), 305 /* AMS_RX_IMODE_CTAT:14:14 */ 306 PHYMOD_SYMBOL_FIELD_ENCODE(133, 14, 14), 307 /* AMS_RX_IMAX_CTAT:15:15 */ 308 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(110, 15, 15) 309 }; 310 static uint32_t BCMI_EAGLE_XGXS_AMS_RX_CTL2r_fields[] = 311 { 312 /* AMS_RX_SPARE_32:0:0 */ 313 PHYMOD_SYMBOL_FIELD_ENCODE(154, 0, 0), 314 /* AMS_RX_SPARE_33:1:1 */ 315 PHYMOD_SYMBOL_FIELD_ENCODE(155, 1, 1), 316 /* AMS_RX_SPARE_34:2:2 */ 317 PHYMOD_SYMBOL_FIELD_ENCODE(156, 2, 2), 318 /* AMS_RX_IMIN_SLICER:3:3 */ 319 PHYMOD_SYMBOL_FIELD_ENCODE(131, 3, 3), 320 /* AMS_RX_IMODE_SLICER:4:4 */ 321 PHYMOD_SYMBOL_FIELD_ENCODE(142, 4, 4), 322 /* AMS_RX_IMAX_SLICER:5:5 */ 323 PHYMOD_SYMBOL_FIELD_ENCODE(119, 5, 5), 324 /* AMS_RX_IMIN_DFE_TAP_WEIGHT:6:6 */ 325 PHYMOD_SYMBOL_FIELD_ENCODE(125, 6, 6), 326 /* AMS_RX_IMODE_DFE_TAP_WEIGHT:7:7 */ 327 PHYMOD_SYMBOL_FIELD_ENCODE(136, 7, 7), 328 /* AMS_RX_IMAX_DFE_TAP_WEIGHT:8:8 */ 329 PHYMOD_SYMBOL_FIELD_ENCODE(113, 8, 8), 330 /* AMS_RX_SEL_UGBW:9:10 */ 331 PHYMOD_SYMBOL_FIELD_ENCODE(149, 10, 9), 332 /* AMS_RX_SEL_TH4DFE:11:12 */ 333 PHYMOD_SYMBOL_FIELD_ENCODE(148, 12, 11), 334 /* AMS_RX_EN_VCCTRL:13:13 */ 335 PHYMOD_SYMBOL_FIELD_ENCODE(105, 13, 13), 336 /* AMS_RX_SPARE_46:14:14 */ 337 PHYMOD_SYMBOL_FIELD_ENCODE(157, 14, 14), 338 /* AMS_RX_SPARE_47:15:15 */ 339 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(158, 15, 15) 340 }; 341 static uint32_t BCMI_EAGLE_XGXS_AMS_RX_CTL3r_fields[] = 342 { 343 /* AMS_RX_IMIN_DC_OFFSET_DAC:0:0 */ 344 PHYMOD_SYMBOL_FIELD_ENCODE(123, 0, 0), 345 /* AMS_RX_IMODE_DC_OFFSET_DAC:1:1 */ 346 PHYMOD_SYMBOL_FIELD_ENCODE(134, 1, 1), 347 /* AMS_RX_IMAX_DC_OFFSET_DAC:2:2 */ 348 PHYMOD_SYMBOL_FIELD_ENCODE(111, 2, 2), 349 /* AMS_RX_IMIN_PHASE_INT_P1:3:3 */ 350 PHYMOD_SYMBOL_FIELD_ENCODE(129, 3, 3), 351 /* AMS_RX_IMODE_PHASE_INT_P1:4:4 */ 352 PHYMOD_SYMBOL_FIELD_ENCODE(140, 4, 4), 353 /* AMS_RX_IMAX_PHASE_INT_P1:5:5 */ 354 PHYMOD_SYMBOL_FIELD_ENCODE(117, 5, 5), 355 /* AMS_RX_IMIN_METRES_EYEDIAG:6:6 */ 356 PHYMOD_SYMBOL_FIELD_ENCODE(126, 6, 6), 357 /* AMS_RX_IMODE_METRES_EYEDIAG:7:7 */ 358 PHYMOD_SYMBOL_FIELD_ENCODE(137, 7, 7), 359 /* AMS_RX_IMAX_METRES_EYEDIAG:8:8 */ 360 PHYMOD_SYMBOL_FIELD_ENCODE(114, 8, 8), 361 /* AMS_RX_IMIN_SIGNAL_DETECT:9:9 */ 362 PHYMOD_SYMBOL_FIELD_ENCODE(130, 9, 9), 363 /* AMS_RX_IMODE_SIGNAL_DETECT:10:10 */ 364 PHYMOD_SYMBOL_FIELD_ENCODE(141, 10, 10), 365 /* AMS_RX_IMAX_SIGNAL_DETECT:11:11 */ 366 PHYMOD_SYMBOL_FIELD_ENCODE(118, 11, 11), 367 /* AMS_RX_I4DEADZONE:12:12 */ 368 PHYMOD_SYMBOL_FIELD_ENCODE(108, 12, 12), 369 /* AMS_RX_I1P25DFE:13:13 */ 370 PHYMOD_SYMBOL_FIELD_ENCODE(107, 13, 13), 371 /* AMS_RX_SPARE_62:14:14 */ 372 PHYMOD_SYMBOL_FIELD_ENCODE(159, 14, 14), 373 /* AMS_RX_SPARE_63:15:15 */ 374 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(160, 15, 15) 375 }; 376 static uint32_t BCMI_EAGLE_XGXS_AMS_RX_CTL4r_fields[] = 377 { 378 /* AMS_RX_DC_OFFSET:0:6 */ 379 PHYMOD_SYMBOL_FIELD_ENCODE(101, 6, 0), 380 /* AMS_RX_FORCE_DC_OFFSET:7:7 */ 381 PHYMOD_SYMBOL_FIELD_ENCODE(106, 7, 7), 382 /* AMS_RX_DC_OFFSET_RANGE:8:8 */ 383 PHYMOD_SYMBOL_FIELD_ENCODE(102, 8, 8), 384 /* AMS_RX_VGA_RESCAL_MUX:9:11 */ 385 PHYMOD_SYMBOL_FIELD_ENCODE(165, 11, 9), 386 /* AMS_RX_PHS_INTERP_RESCAL_MUX:12:15 */ 387 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(146, 15, 12) 388 }; 389 static uint32_t BCMI_EAGLE_XGXS_AMS_RX_INTCTLr_fields[] = 390 { 391 /* AMS_RX_DFE_OS2X_MODE:0:0 */ 392 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(103, 0, 0) 393 }; 394 static uint32_t BCMI_EAGLE_XGXS_AMS_RX_STSr_fields[] = 395 { 396 /* AMS_RX_STS:0:15 */ 397 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(161, 15, 0) 398 }; 399 static uint32_t BCMI_EAGLE_XGXS_AMS_STSr_fields[] = 400 { 401 /* AMS_PLL_STS:0:15 */ 402 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(85, 15, 0) 403 }; 404 static uint32_t BCMI_EAGLE_XGXS_AMS_TX_CTL0r_fields[] = 405 { 406 /* AMS_TX_OSR4:0:0 */ 407 PHYMOD_SYMBOL_FIELD_ENCODE(178, 0, 0), 408 /* AMS_TX_SPARE_1:1:1 */ 409 PHYMOD_SYMBOL_FIELD_ENCODE(184, 1, 1), 410 /* AMS_TX_SPARE_2:2:2 */ 411 PHYMOD_SYMBOL_FIELD_ENCODE(185, 2, 2), 412 /* AMS_TX_SPARE_3:3:3 */ 413 PHYMOD_SYMBOL_FIELD_ENCODE(186, 3, 3), 414 /* AMS_TX_TEST_DATA:4:5 */ 415 PHYMOD_SYMBOL_FIELD_ENCODE(189, 5, 4), 416 /* AMS_TX_TICKSEL:6:7 */ 417 PHYMOD_SYMBOL_FIELD_ENCODE(190, 7, 6), 418 /* AMS_TX_KR_TEST_MODE:8:8 */ 419 PHYMOD_SYMBOL_FIELD_ENCODE(176, 8, 8), 420 /* AMS_TX_DCC_SEL:9:9 */ 421 PHYMOD_SYMBOL_FIELD_ENCODE(170, 9, 9), 422 /* AMS_TX_DCC_DIS:10:10 */ 423 PHYMOD_SYMBOL_FIELD_ENCODE(169, 10, 10), 424 /* AMS_TX_CAL_OFF:11:11 */ 425 PHYMOD_SYMBOL_FIELD_ENCODE(168, 11, 11), 426 /* AMS_TX_CAL_AUX:12:15 */ 427 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(167, 15, 12) 428 }; 429 static uint32_t BCMI_EAGLE_XGXS_AMS_TX_CTL1r_fields[] = 430 { 431 /* AMS_TX_IBIAS:0:2 */ 432 PHYMOD_SYMBOL_FIELD_ENCODE(173, 2, 0), 433 /* AMS_TX_IDCC:3:5 */ 434 PHYMOD_SYMBOL_FIELD_ENCODE(175, 5, 3), 435 /* AMS_TX_ICML:6:8 */ 436 PHYMOD_SYMBOL_FIELD_ENCODE(174, 8, 6), 437 /* AMS_TX_SPARE_30_25:9:14 */ 438 PHYMOD_SYMBOL_FIELD_ENCODE(187, 14, 9), 439 /* AMS_TX_LP_OVRD:15:15 */ 440 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(177, 15, 15) 441 }; 442 static uint32_t BCMI_EAGLE_XGXS_AMS_TX_CTL2r_fields[] = 443 { 444 /* AMS_TX_AMP_CTL:0:3 */ 445 PHYMOD_SYMBOL_FIELD_ENCODE(166, 3, 0), 446 /* AMS_TX_POST3_COEF:4:6 */ 447 PHYMOD_SYMBOL_FIELD_ENCODE(180, 6, 4), 448 /* AMS_TX_SIGN_POST3:7:7 */ 449 PHYMOD_SYMBOL_FIELD_ENCODE(183, 7, 7), 450 /* AMS_TX_POST2_COEF:8:11 */ 451 PHYMOD_SYMBOL_FIELD_ENCODE(179, 11, 8), 452 /* AMS_TX_SIGN_POST2:12:12 */ 453 PHYMOD_SYMBOL_FIELD_ENCODE(182, 12, 12), 454 /* AMS_TX_DRIVERMODE:13:14 */ 455 PHYMOD_SYMBOL_FIELD_ENCODE(171, 14, 13), 456 /* AMS_TX_ELEC_IDLE_AUX:15:15 */ 457 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(172, 15, 15) 458 }; 459 static uint32_t BCMI_EAGLE_XGXS_AMS_TX_INTCTLr_fields[] = 460 { 461 /* AMS_TX_SEL_HALFRATE:0:0 */ 462 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(181, 0, 0) 463 }; 464 static uint32_t BCMI_EAGLE_XGXS_AMS_TX_STSr_fields[] = 465 { 466 /* AMS_TX_STS:0:15 */ 467 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(188, 15, 0) 468 }; 469 static uint32_t BCMI_EAGLE_XGXS_CKRST_CLK_N_RST_DBG_CTLr_fields[] = 470 { 471 /* LN_RX_S_CLKGATE_FRC_ON:0:0 */ 472 PHYMOD_SYMBOL_FIELD_ENCODE(426, 0, 0), 473 /* LN_RX_S_COMCLK_SEL:1:1 */ 474 PHYMOD_SYMBOL_FIELD_ENCODE(428, 1, 1), 475 /* LN_RX_S_COMCLK_FRC_ON:2:2 */ 476 PHYMOD_SYMBOL_FIELD_ENCODE(427, 2, 2), 477 /* PMD_RX_CLK_VLD_FRC:3:3 */ 478 PHYMOD_SYMBOL_FIELD_ENCODE(573, 3, 3), 479 /* PMD_RX_CLK_VLD_FRC_VAL:4:4 */ 480 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(574, 4, 4) 481 }; 482 static uint32_t BCMI_EAGLE_XGXS_CKRST_LN_AFE_RST_PWRDWN_CTL_CTLr_fields[] = 483 { 484 /* AFE_RX_PWRDN_FRC:0:0 */ 485 PHYMOD_SYMBOL_FIELD_ENCODE(1, 0, 0), 486 /* AFE_RX_PWRDN_FRC_VAL:1:1 */ 487 PHYMOD_SYMBOL_FIELD_ENCODE(2, 1, 1), 488 /* AFE_RX_RESET_FRC:2:2 */ 489 PHYMOD_SYMBOL_FIELD_ENCODE(3, 2, 2), 490 /* AFE_RX_RESET_FRC_VAL:3:3 */ 491 PHYMOD_SYMBOL_FIELD_ENCODE(4, 3, 3), 492 /* AFE_TX_PWRDN_FRC:4:4 */ 493 PHYMOD_SYMBOL_FIELD_ENCODE(11, 4, 4), 494 /* AFE_TX_PWRDN_FRC_VAL:5:5 */ 495 PHYMOD_SYMBOL_FIELD_ENCODE(12, 5, 5), 496 /* AFE_TX_RESET_FRC:6:6 */ 497 PHYMOD_SYMBOL_FIELD_ENCODE(13, 6, 6), 498 /* AFE_TX_RESET_FRC_VAL:7:7 */ 499 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(14, 7, 7) 500 }; 501 static uint32_t BCMI_EAGLE_XGXS_CKRST_LN_CLK_RST_N_PWRDWN_CTLr_fields[] = 502 { 503 /* LN_DP_S_RSTB:1:1 */ 504 PHYMOD_SYMBOL_FIELD_ENCODE(424, 1, 1), 505 /* LN_RX_S_PWRDN:2:2 */ 506 PHYMOD_SYMBOL_FIELD_ENCODE(429, 2, 2), 507 /* LN_TX_S_PWRDN:3:3 */ 508 PHYMOD_SYMBOL_FIELD_ENCODE(433, 3, 3), 509 /* AFE_SIGDET_PWRDN:4:4 */ 510 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(5, 4, 4) 511 }; 512 static uint32_t BCMI_EAGLE_XGXS_CKRST_LN_DBG_RST_CTLr_fields[] = 513 { 514 /* LN_RX_S_RSTB:0:0 */ 515 PHYMOD_SYMBOL_FIELD_ENCODE(430, 0, 0), 516 /* LN_RX_DP_S_RSTB:1:1 */ 517 PHYMOD_SYMBOL_FIELD_ENCODE(425, 1, 1), 518 /* SIGDET_DP_RSTB_EN:2:2 */ 519 PHYMOD_SYMBOL_FIELD_ENCODE(651, 2, 2), 520 /* LN_TX_S_RSTB:8:8 */ 521 PHYMOD_SYMBOL_FIELD_ENCODE(434, 8, 8), 522 /* LN_TX_DP_S_RSTB:9:9 */ 523 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(432, 9, 9) 524 }; 525 static uint32_t BCMI_EAGLE_XGXS_CKRST_LN_DP_RST_ST_STSr_fields[] = 526 { 527 /* LANE_DP_RESET_STATE:0:2 */ 528 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(419, 2, 0) 529 }; 530 static uint32_t BCMI_EAGLE_XGXS_CKRST_LN_MCST_MASK_CTLr_fields[] = 531 { 532 /* LANE_MULTICAST_MASK_CONTROL:0:0 */ 533 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(420, 0, 0) 534 }; 535 static uint32_t BCMI_EAGLE_XGXS_CKRST_LN_RST_N_PWRDN_PIN_KILL_CTLr_fields[] = 536 { 537 /* PMD_LN_H_RSTB_PKILL:0:0 */ 538 PHYMOD_SYMBOL_FIELD_ENCODE(569, 0, 0), 539 /* PMD_LN_DP_H_RSTB_PKILL:1:1 */ 540 PHYMOD_SYMBOL_FIELD_ENCODE(568, 1, 1), 541 /* PMD_LN_RX_H_PWRDN_PKILL:2:2 */ 542 PHYMOD_SYMBOL_FIELD_ENCODE(570, 2, 2), 543 /* PMD_LN_TX_H_PWRDN_PKILL:3:3 */ 544 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(571, 3, 3) 545 }; 546 static uint32_t BCMI_EAGLE_XGXS_CKRST_LN_RST_OCC_CTLr_fields[] = 547 { 548 /* LANE_REG_RESET_OCCURRED:0:0 */ 549 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(421, 0, 0) 550 }; 551 static uint32_t BCMI_EAGLE_XGXS_CKRST_LN_S_RSTB_CTLr_fields[] = 552 { 553 /* LN_S_RSTB:0:0 */ 554 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(431, 0, 0) 555 }; 556 static uint32_t BCMI_EAGLE_XGXS_CKRST_OSR_MODE_CTLr_fields[] = 557 { 558 /* OSR_MODE_FRC_VAL:0:3 */ 559 PHYMOD_SYMBOL_FIELD_ENCODE(513, 3, 0), 560 /* OSR_MODE_FRC:15:15 */ 561 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(512, 15, 15) 562 }; 563 static uint32_t BCMI_EAGLE_XGXS_CKRST_OSR_MODE_PIN_STSr_fields[] = 564 { 565 /* OSR_MODE_PIN:0:3 */ 566 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(514, 3, 0) 567 }; 568 static uint32_t BCMI_EAGLE_XGXS_CKRST_OSR_MODE_STSr_fields[] = 569 { 570 /* OSR_MODE:0:3 */ 571 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(511, 3, 0) 572 }; 573 static uint32_t BCMI_EAGLE_XGXS_CKRST_PMD_LN_MODE_STSr_fields[] = 574 { 575 /* PMD_LANE_MODE:0:15 */ 576 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(567, 15, 0) 577 }; 578 static uint32_t BCMI_EAGLE_XGXS_CKRST_UC_ACK_LN_CTLr_fields[] = 579 { 580 /* UC_ACK_LANE_CFG_DONE:0:0 */ 581 PHYMOD_SYMBOL_FIELD_ENCODE(768, 0, 0), 582 /* UC_ACK_LANE_DP_RESET:1:1 */ 583 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(769, 1, 1) 584 }; 585 static uint32_t BCMI_EAGLE_XGXS_CL72_RXBASE_R_LD_STS_REPr_fields[] = 586 { 587 /* CL72_IEEE_LP_STATUS_REPORT:0:15 */ 588 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(241, 15, 0) 589 }; 590 static uint32_t BCMI_EAGLE_XGXS_CL72_RXCL72_LP_CTL_PAGEr_fields[] = 591 { 592 /* CL72_LP_CONTROL_PAGE:0:15 */ 593 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(252, 15, 0) 594 }; 595 static uint32_t BCMI_EAGLE_XGXS_CL72_RXCL72_STS1r_fields[] = 596 { 597 /* CL72_SIGNAL_DETECT:0:0 */ 598 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(259, 0, 0) 599 }; 600 static uint32_t BCMI_EAGLE_XGXS_CL72_RXDBG2r_fields[] = 601 { 602 /* CL72_GOOD_MARKER_CNT:0:1 */ 603 PHYMOD_SYMBOL_FIELD_ENCODE(236, 1, 0), 604 /* CL72_BAD_MARKER_CNT:2:4 */ 605 PHYMOD_SYMBOL_FIELD_ENCODE(227, 4, 2), 606 /* CL72_DME_CELL_BOUNDARY_CHK:7:7 */ 607 PHYMOD_SYMBOL_FIELD_ENCODE(232, 7, 7), 608 /* CL72_CTRL_FRAME_DLY:8:11 */ 609 PHYMOD_SYMBOL_FIELD_ENCODE(229, 11, 8), 610 /* CL72_STRICT_DME_CHK:12:12 */ 611 PHYMOD_SYMBOL_FIELD_ENCODE(261, 12, 12), 612 /* CL72_STRICT_MARKER_CHK:13:13 */ 613 PHYMOD_SYMBOL_FIELD_ENCODE(262, 13, 13), 614 /* CL72_PPM_OFFSET_EN:14:14 */ 615 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(254, 14, 14) 616 }; 617 static uint32_t BCMI_EAGLE_XGXS_CL72_RXMISC1_CTLr_fields[] = 618 { 619 /* CL72_TR_COARSE_LOCK:1:1 */ 620 PHYMOD_SYMBOL_FIELD_ENCODE(265, 1, 1), 621 /* CL72_RX_DP_LN_CLK_EN:2:2 */ 622 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(257, 2, 2) 623 }; 624 static uint32_t BCMI_EAGLE_XGXS_CL72_RXRCVD_STSr_fields[] = 625 { 626 /* CL72_RCVD_STATUS_PAGE:0:15 */ 627 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(255, 15, 0) 628 }; 629 static uint32_t BCMI_EAGLE_XGXS_CL72_TXBASE_R_LD_COEFF_UPDr_fields[] = 630 { 631 /* CL72_IEEE_LD_COEFF_UPDATE:0:15 */ 632 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(238, 15, 0) 633 }; 634 static uint32_t BCMI_EAGLE_XGXS_CL72_TXBASE_R_LD_STS_REPr_fields[] = 635 { 636 /* CL72_IEEE_LD_STATUS_REPORT:0:15 */ 637 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(239, 15, 0) 638 }; 639 static uint32_t BCMI_EAGLE_XGXS_CL72_TXBASE_R_LP_COEFF_UPDr_fields[] = 640 { 641 /* CL72_IEEE_LP_COEFF_UPDATE:0:15 */ 642 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(240, 15, 0) 643 }; 644 static uint32_t BCMI_EAGLE_XGXS_CL72_TXBASE_R_PMD_CTLr_fields[] = 645 { 646 /* CL72_IEEE_RESTART_TRAINING:0:0 */ 647 PHYMOD_SYMBOL_FIELD_ENCODE(243, 0, 0), 648 /* CL72_IEEE_TRAINING_ENABLE:1:1 */ 649 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(244, 1, 1) 650 }; 651 static uint32_t BCMI_EAGLE_XGXS_CL72_TXBASE_R_PMD_STSr_fields[] = 652 { 653 /* CL72_IEEE_RECEIVER_STATUS:0:0 */ 654 PHYMOD_SYMBOL_FIELD_ENCODE(242, 0, 0), 655 /* CL72_IEEE_FRAME_LOCK:1:1 */ 656 PHYMOD_SYMBOL_FIELD_ENCODE(237, 1, 1), 657 /* CL72_IEEE_TRAINING_STATUS:2:2 */ 658 PHYMOD_SYMBOL_FIELD_ENCODE(246, 2, 2), 659 /* CL72_IEEE_TRAINING_FAILURE:3:3 */ 660 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(245, 3, 3) 661 }; 662 static uint32_t BCMI_EAGLE_XGXS_CL72_TXCL72_LD_STS_PAGEr_fields[] = 663 { 664 /* CL72_LD_STATUS_PAGE:0:15 */ 665 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(249, 15, 0) 666 }; 667 static uint32_t BCMI_EAGLE_XGXS_CL72_TXCL72_LD_XMT_STS_PAGE_OVRRr_fields[] = 668 { 669 /* CL72_OVERRIDE_LD_STATUS_PAGE:0:15 */ 670 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(253, 15, 0) 671 }; 672 static uint32_t BCMI_EAGLE_XGXS_CL72_TXCL72_READY_FOR_CMDr_fields[] = 673 { 674 /* CL72_READY_FOR_CMD:0:0 */ 675 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(256, 0, 0) 676 }; 677 static uint32_t BCMI_EAGLE_XGXS_CL72_TXCL72_TX_DBG_STSr_fields[] = 678 { 679 /* CL72_LD_COEFF_CMD_HIST:0:10 */ 680 PHYMOD_SYMBOL_FIELD_ENCODE(248, 10, 0), 681 /* CL72_FRAME_LOCK_LH:11:11 */ 682 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(234, 11, 11) 683 }; 684 static uint32_t BCMI_EAGLE_XGXS_CL72_TXC_DBG1r_fields[] = 685 { 686 /* MAIN_TAP_MIN_VAL:0:6 */ 687 PHYMOD_SYMBOL_FIELD_ENCODE(441, 6, 0), 688 /* TAP_SUM_MAX_VAL:7:14 */ 689 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(664, 14, 7) 690 }; 691 static uint32_t BCMI_EAGLE_XGXS_CL72_TXC_MAX_WAIT_TMRr_fields[] = 692 { 693 /* MAX_WAIT_TIMER_PERIOD:0:15 */ 694 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(442, 15, 0) 695 }; 696 static uint32_t BCMI_EAGLE_XGXS_CL72_TXC_TAP_LIMIT_CTL1r_fields[] = 697 { 698 /* PRE_TAP_LIMIT:0:4 */ 699 PHYMOD_SYMBOL_FIELD_ENCODE(602, 4, 0), 700 /* POST_TAP_LIMIT:5:10 */ 701 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(580, 10, 5) 702 }; 703 static uint32_t BCMI_EAGLE_XGXS_CL72_TXC_TAP_LIMIT_CTL2r_fields[] = 704 { 705 /* MAIN_TAP_LIMIT:0:6 */ 706 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(440, 6, 0) 707 }; 708 static uint32_t BCMI_EAGLE_XGXS_CL72_TXC_TAP_PRESET_CTLr_fields[] = 709 { 710 /* POST_TAP_PRESET_VAL:0:5 */ 711 PHYMOD_SYMBOL_FIELD_ENCODE(581, 5, 0), 712 /* PRE_TAP_PRESET_VAL:6:10 */ 713 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(603, 10, 6) 714 }; 715 static uint32_t BCMI_EAGLE_XGXS_CL72_TXC_WAIT_TMRr_fields[] = 716 { 717 /* WAIT_CNTR_LIMIT:0:8 */ 718 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(797, 8, 0) 719 }; 720 static uint32_t BCMI_EAGLE_XGXS_CL72_TXDBG3r_fields[] = 721 { 722 /* CL72_BRK_RING_OSC:0:0 */ 723 PHYMOD_SYMBOL_FIELD_ENCODE(228, 0, 0), 724 /* CL72_FRAME_LOCK_RDY_FOR_CMD_EN:1:1 */ 725 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(235, 1, 1) 726 }; 727 static uint32_t BCMI_EAGLE_XGXS_CL72_TXKR_DFLT_CTL1r_fields[] = 728 { 729 /* CL72_TX_FIR_TAP_PRE_KR_INIT_VAL:0:4 */ 730 PHYMOD_SYMBOL_FIELD_ENCODE(269, 4, 0), 731 /* CL72_TX_FIR_TAP_POST_KR_INIT_VAL:5:10 */ 732 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(268, 10, 5) 733 }; 734 static uint32_t BCMI_EAGLE_XGXS_CL72_TXKR_DFLT_CTL2r_fields[] = 735 { 736 /* CL72_TX_FIR_TAP_MAIN_KR_INIT_VAL:0:6 */ 737 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(267, 6, 0) 738 }; 739 static uint32_t BCMI_EAGLE_XGXS_CL72_TXMISC2_CTLr_fields[] = 740 { 741 /* CL72_RX_TRAINED:0:0 */ 742 PHYMOD_SYMBOL_FIELD_ENCODE(258, 0, 0), 743 /* CL72_SIGNAL_DET_FRC:1:1 */ 744 PHYMOD_SYMBOL_FIELD_ENCODE(260, 1, 1), 745 /* CL72_TX_DP_LN_CLK_EN:2:2 */ 746 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(266, 2, 2) 747 }; 748 static uint32_t BCMI_EAGLE_XGXS_CL72_TXMISC_COEFF_CTLr_fields[] = 749 { 750 /* CL72_INC_DEC_VAL_SEL:0:1 */ 751 PHYMOD_SYMBOL_FIELD_ENCODE(247, 1, 0), 752 /* CL72_TAP_V2_VAL:2:7 */ 753 PHYMOD_SYMBOL_FIELD_ENCODE(263, 7, 2), 754 /* CL72_V2_CONSTRAINT_DIS:8:8 */ 755 PHYMOD_SYMBOL_FIELD_ENCODE(270, 8, 8), 756 /* CL72_LD_XMT_STATUS_LOAD:9:9 */ 757 PHYMOD_SYMBOL_FIELD_ENCODE(250, 9, 9), 758 /* CL72_LD_XMT_STATUS_OVERRIDE:10:10 */ 759 PHYMOD_SYMBOL_FIELD_ENCODE(251, 10, 10), 760 /* CL72_DIS_LP_COEFF_UPDATES_TO_LD:11:11 */ 761 PHYMOD_SYMBOL_FIELD_ENCODE(230, 11, 11), 762 /* CL72_DOUBLE_CMD_EN:12:12 */ 763 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(233, 12, 12) 764 }; 765 static uint32_t BCMI_EAGLE_XGXS_CL72_TXPCS_INTERFACE_CTLr_fields[] = 766 { 767 /* CL72_DIS_MAX_WAIT_TIMER:0:0 */ 768 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(231, 0, 0) 769 }; 770 static uint32_t BCMI_EAGLE_XGXS_CL72_TXXMT_UPDr_fields[] = 771 { 772 /* CL72_XMT_UPDATE_PAGE:0:15 */ 773 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(271, 15, 0) 774 }; 775 static uint32_t BCMI_EAGLE_XGXS_DIG_CORE_DP_RST_ST_STSr_fields[] = 776 { 777 /* CORE_DP_RESET_STATE:0:2 */ 778 PHYMOD_SYMBOL_FIELD_ENCODE(280, 2, 0), 779 /* LANE_RESET_RELEASED_INDEX:8:12 */ 780 PHYMOD_SYMBOL_FIELD_ENCODE(423, 12, 8), 781 /* LANE_RESET_RELEASED:14:14 */ 782 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(422, 14, 14) 783 }; 784 static uint32_t BCMI_EAGLE_XGXS_DIG_CORE_MCST_MASK_CTLr_fields[] = 785 { 786 /* CORE_MULTICAST_MASK_CONTROL:0:3 */ 787 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(282, 3, 0) 788 }; 789 static uint32_t BCMI_EAGLE_XGXS_DIG_CORE_RST_OCC_CTLr_fields[] = 790 { 791 /* CORE_REG_RESET_OCCURRED:0:0 */ 792 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(283, 0, 0) 793 }; 794 static uint32_t BCMI_EAGLE_XGXS_DIG_LN_ADDR_2_3r_fields[] = 795 { 796 /* LANE_ADDR_2:0:4 */ 797 PHYMOD_SYMBOL_FIELD_ENCODE(417, 4, 0), 798 /* LANE_ADDR_3:8:12 */ 799 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(418, 12, 8) 800 }; 801 static uint32_t BCMI_EAGLE_XGXS_DIG_PMD_CORE_MODE_STSr_fields[] = 802 { 803 /* PMD_CORE_MODE:0:15 */ 804 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(566, 15, 0) 805 }; 806 static uint32_t BCMI_EAGLE_XGXS_DIG_REVID0r_fields[] = 807 { 808 /* REVID_MODEL:0:5 */ 809 PHYMOD_SYMBOL_FIELD_ENCODE(622, 5, 0), 810 /* REVID_PROCESS:6:8 */ 811 PHYMOD_SYMBOL_FIELD_ENCODE(625, 8, 6), 812 /* REVID_BONDING:9:10 */ 813 PHYMOD_SYMBOL_FIELD_ENCODE(616, 10, 9), 814 /* REVID_REV_NUMBER:11:13 */ 815 PHYMOD_SYMBOL_FIELD_ENCODE(627, 13, 11), 816 /* REVID_REV_LETTER:14:15 */ 817 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(626, 15, 14) 818 }; 819 static uint32_t BCMI_EAGLE_XGXS_DIG_REVID1r_fields[] = 820 { 821 /* REVID_EEE:0:0 */ 822 PHYMOD_SYMBOL_FIELD_ENCODE(618, 0, 0), 823 /* REVID_LLP:1:1 */ 824 PHYMOD_SYMBOL_FIELD_ENCODE(619, 1, 1), 825 /* REVID_PIR:2:2 */ 826 PHYMOD_SYMBOL_FIELD_ENCODE(624, 2, 2), 827 /* REVID_CL72:3:3 */ 828 PHYMOD_SYMBOL_FIELD_ENCODE(617, 3, 3), 829 /* REVID_MICRO:4:4 */ 830 PHYMOD_SYMBOL_FIELD_ENCODE(621, 4, 4), 831 /* REVID_MDIO:5:5 */ 832 PHYMOD_SYMBOL_FIELD_ENCODE(620, 5, 5), 833 /* REVID_MULTIPLICITY:12:15 */ 834 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(623, 15, 12) 835 }; 836 static uint32_t BCMI_EAGLE_XGXS_DIG_REVID2r_fields[] = 837 { 838 /* REVID2:0:3 */ 839 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(615, 3, 0) 840 }; 841 static uint32_t BCMI_EAGLE_XGXS_DIG_RST_CTL_CORE_DPr_fields[] = 842 { 843 /* PMD_CORE_DP_H_RSTB_PKILL:1:1 */ 844 PHYMOD_SYMBOL_FIELD_ENCODE(565, 1, 1), 845 /* SUP_RST_SEQ_FRC_VAL:3:3 */ 846 PHYMOD_SYMBOL_FIELD_ENCODE(663, 3, 3), 847 /* SUP_RST_SEQ_FRC:4:4 */ 848 PHYMOD_SYMBOL_FIELD_ENCODE(662, 4, 4), 849 /* PMD_MDIO_TRANS_PKILL:5:5 */ 850 PHYMOD_SYMBOL_FIELD_ENCODE(572, 5, 5), 851 /* PMD_TX_CLK_VLD_FRC:7:7 */ 852 PHYMOD_SYMBOL_FIELD_ENCODE(577, 7, 7), 853 /* PMD_TX_CLK_VLD_FRC_VAL:8:8 */ 854 PHYMOD_SYMBOL_FIELD_ENCODE(578, 8, 8), 855 /* TX_S_COMCLK_SEL:9:9 */ 856 PHYMOD_SYMBOL_FIELD_ENCODE(761, 9, 9), 857 /* TX_S_COMCLK_FRC_ON:10:10 */ 858 PHYMOD_SYMBOL_FIELD_ENCODE(760, 10, 10), 859 /* TX_S_CLKGATE_FRC_ON:11:11 */ 860 PHYMOD_SYMBOL_FIELD_ENCODE(759, 11, 11), 861 /* AFE_S_PLL_RESET_FRC_VAL:12:12 */ 862 PHYMOD_SYMBOL_FIELD_ENCODE(10, 12, 12), 863 /* AFE_S_PLL_RESET_FRC:13:13 */ 864 PHYMOD_SYMBOL_FIELD_ENCODE(9, 13, 13), 865 /* TX_PI_LOOP_FILTER_STABLE:14:14 */ 866 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(743, 14, 14) 867 }; 868 static uint32_t BCMI_EAGLE_XGXS_DIG_RST_CTL_PMDr_fields[] = 869 { 870 /* CORE_S_RSTB:0:0 */ 871 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(284, 0, 0) 872 }; 873 static uint32_t BCMI_EAGLE_XGXS_DIG_RST_SEQ_TMR_CTLr_fields[] = 874 { 875 /* RST_SEQ_TIMER:0:2 */ 876 PHYMOD_SYMBOL_FIELD_ENCODE(634, 2, 0), 877 /* PWRDN_SEQ_TIMER:8:10 */ 878 PHYMOD_SYMBOL_FIELD_ENCODE(604, 10, 8), 879 /* RST_SEQ_DIS_FLT_MODE:14:15 */ 880 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(633, 15, 14) 881 }; 882 static uint32_t BCMI_EAGLE_XGXS_DIG_TOP_USER_CTL0r_fields[] = 883 { 884 /* HEARTBEAT_COUNT_1US:0:9 */ 885 PHYMOD_SYMBOL_FIELD_ENCODE(408, 9, 0), 886 /* CORE_DP_S_RSTB:13:13 */ 887 PHYMOD_SYMBOL_FIELD_ENCODE(281, 13, 13), 888 /* AFE_S_PLL_PWRDN:14:14 */ 889 PHYMOD_SYMBOL_FIELD_ENCODE(8, 14, 14), 890 /* UC_ACTIVE:15:15 */ 891 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(770, 15, 15) 892 }; 893 static uint32_t BCMI_EAGLE_XGXS_DIG_TX_LN_MAP_0_1_2r_fields[] = 894 { 895 /* TX_LANE_MAP_0:0:4 */ 896 PHYMOD_SYMBOL_FIELD_ENCODE(719, 4, 0), 897 /* TX_LANE_MAP_1:5:9 */ 898 PHYMOD_SYMBOL_FIELD_ENCODE(720, 9, 5), 899 /* TX_LANE_MAP_2:10:14 */ 900 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(721, 14, 10) 901 }; 902 static uint32_t BCMI_EAGLE_XGXS_DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r_fields[] = 903 { 904 /* TX_LANE_MAP_3:0:4 */ 905 PHYMOD_SYMBOL_FIELD_ENCODE(722, 4, 0), 906 /* LANE_ADDR_0:5:9 */ 907 PHYMOD_SYMBOL_FIELD_ENCODE(415, 9, 5), 908 /* LANE_ADDR_1:10:14 */ 909 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(416, 14, 10) 910 }; 911 static uint32_t BCMI_EAGLE_XGXS_DIG_UC_ACK_CORE_CTLr_fields[] = 912 { 913 /* UC_ACK_CORE_CFG_DONE:0:0 */ 914 PHYMOD_SYMBOL_FIELD_ENCODE(762, 0, 0), 915 /* UC_ACK_CORE_DP_RESET:1:1 */ 916 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(763, 1, 1) 917 }; 918 static uint32_t BCMI_EAGLE_XGXS_DSC_CDR_CTL0r_fields[] = 919 { 920 /* CDR_PHASE_SAT_CTRL:0:0 */ 921 PHYMOD_SYMBOL_FIELD_ENCODE(223, 0, 0), 922 /* BR_PD_EN:1:1 */ 923 PHYMOD_SYMBOL_FIELD_ENCODE(191, 1, 1), 924 /* CDR_FREQ_EN:2:2 */ 925 PHYMOD_SYMBOL_FIELD_ENCODE(211, 2, 2), 926 /* CDR_INTEG_REG_CLR:4:4 */ 927 PHYMOD_SYMBOL_FIELD_ENCODE(217, 4, 4), 928 /* CDR_PHASE_ERR_FRZ:5:5 */ 929 PHYMOD_SYMBOL_FIELD_ENCODE(222, 5, 5), 930 /* CDR_INTEG_SAT_SEL:6:6 */ 931 PHYMOD_SYMBOL_FIELD_ENCODE(218, 6, 6), 932 /* CDR_FREQ_OVERRIDE_EN:7:7 */ 933 PHYMOD_SYMBOL_FIELD_ENCODE(212, 7, 7), 934 /* CDR_LM_THR_SEL:8:10 */ 935 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(220, 10, 8) 936 }; 937 static uint32_t BCMI_EAGLE_XGXS_DSC_CDR_CTL1r_fields[] = 938 { 939 /* CDR_FREQ_OVERRIDE_VAL:0:15 */ 940 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(213, 15, 0) 941 }; 942 static uint32_t BCMI_EAGLE_XGXS_DSC_CDR_CTL2r_fields[] = 943 { 944 /* CDR_ZERO_POLARITY:0:0 */ 945 PHYMOD_SYMBOL_FIELD_ENCODE(226, 0, 0), 946 /* PHASE_ERR_OFFSET_MULT_2:1:1 */ 947 PHYMOD_SYMBOL_FIELD_ENCODE(547, 1, 1), 948 /* PATTERN_SEL:4:7 */ 949 PHYMOD_SYMBOL_FIELD_ENCODE(522, 7, 4), 950 /* OSX2P_PHERR_GAIN:8:9 */ 951 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(515, 9, 8) 952 }; 953 static uint32_t BCMI_EAGLE_XGXS_DSC_CDR_STS_INTEGr_fields[] = 954 { 955 /* CDR_INTEG_REG:0:15 */ 956 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(216, 15, 0) 957 }; 958 static uint32_t BCMI_EAGLE_XGXS_DSC_CDR_STS_PHASE_ERRr_fields[] = 959 { 960 /* CDR_PHASE_ERR:0:4 */ 961 PHYMOD_SYMBOL_FIELD_ENCODE(221, 4, 0), 962 /* CDR_LM_OUTOFLOCK:8:8 */ 963 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(219, 8, 8) 964 }; 965 static uint32_t BCMI_EAGLE_XGXS_DSC_CTLr_fields[] = 966 { 967 /* PD_CH_P1:0:0 */ 968 PHYMOD_SYMBOL_FIELD_ENCODE(541, 0, 0), 969 /* OFFSET_PD:1:1 */ 970 PHYMOD_SYMBOL_FIELD_ENCODE(510, 1, 1), 971 /* EN_HGAIN:2:2 */ 972 PHYMOD_SYMBOL_FIELD_ENCODE(395, 2, 2), 973 /* P1_THRESH_SEL:3:3 */ 974 PHYMOD_SYMBOL_FIELD_ENCODE(521, 3, 3), 975 /* M1_THRESH_ZERO:4:4 */ 976 PHYMOD_SYMBOL_FIELD_ENCODE(439, 4, 4), 977 /* M1_THRESH_SEL:5:6 */ 978 PHYMOD_SYMBOL_FIELD_ENCODE(438, 6, 5), 979 /* PF_HIZ:7:7 */ 980 PHYMOD_SYMBOL_FIELD_ENCODE(544, 7, 7), 981 /* EN_DFE_CLK:8:8 */ 982 PHYMOD_SYMBOL_FIELD_ENCODE(394, 8, 8), 983 /* OFFSET_FASTACQ:9:9 */ 984 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(509, 9, 9) 985 }; 986 static uint32_t BCMI_EAGLE_XGXS_DSC_DC_OFFSr_fields[] = 987 { 988 /* DC_OFFSET:0:6 */ 989 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(291, 6, 0) 990 }; 991 static uint32_t BCMI_EAGLE_XGXS_DSC_DFE_1_CTLr_fields[] = 992 { 993 /* DFE_1_ACC_CLR:0:0 */ 994 PHYMOD_SYMBOL_FIELD_ENCODE(292, 0, 0), 995 /* DFE_1_CMN_ONLY:1:1 */ 996 PHYMOD_SYMBOL_FIELD_ENCODE(294, 1, 1), 997 /* DFE_1_INV_P1:8:8 */ 998 PHYMOD_SYMBOL_FIELD_ENCODE(301, 8, 8), 999 /* DFE_1_INV_M1:9:9 */ 1000 PHYMOD_SYMBOL_FIELD_ENCODE(300, 9, 9), 1001 /* DFE_1_ERR_GAIN:10:11 */ 1002 PHYMOD_SYMBOL_FIELD_ENCODE(297, 11, 10), 1003 /* DFE_1_GRADIENT_INVERT:12:12 */ 1004 PHYMOD_SYMBOL_FIELD_ENCODE(299, 12, 12), 1005 /* DFE_1_ERR_SEL:13:14 */ 1006 PHYMOD_SYMBOL_FIELD_ENCODE(298, 14, 13), 1007 /* DFE_1_EN:15:15 */ 1008 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(296, 15, 15) 1009 }; 1010 static uint32_t BCMI_EAGLE_XGXS_DSC_DFE_1_PAT_CTLr_fields[] = 1011 { 1012 /* DFE_1_PATTERN:0:5 */ 1013 PHYMOD_SYMBOL_FIELD_ENCODE(303, 5, 0), 1014 /* DFE_1_PATTERN_BIT_EN:8:13 */ 1015 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(304, 13, 8) 1016 }; 1017 static uint32_t BCMI_EAGLE_XGXS_DSC_DFE_1_STSr_fields[] = 1018 { 1019 /* DFE_1_CMN:0:5 */ 1020 PHYMOD_SYMBOL_FIELD_ENCODE(293, 5, 0), 1021 /* DFE_1_O:8:10 */ 1022 PHYMOD_SYMBOL_FIELD_ENCODE(302, 10, 8), 1023 /* DFE_1_E:11:13 */ 1024 PHYMOD_SYMBOL_FIELD_ENCODE(295, 13, 11), 1025 /* DFE_1_WANTS_NEGATIVE:15:15 */ 1026 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(305, 15, 15) 1027 }; 1028 static uint32_t BCMI_EAGLE_XGXS_DSC_DFE_2_CTLr_fields[] = 1029 { 1030 /* DFE_2_ACC_CLR:0:0 */ 1031 PHYMOD_SYMBOL_FIELD_ENCODE(306, 0, 0), 1032 /* DFE_2_CMN_ONLY:1:1 */ 1033 PHYMOD_SYMBOL_FIELD_ENCODE(308, 1, 1), 1034 /* DFE_2_INV_P1:8:8 */ 1035 PHYMOD_SYMBOL_FIELD_ENCODE(315, 8, 8), 1036 /* DFE_2_INV_M1:9:9 */ 1037 PHYMOD_SYMBOL_FIELD_ENCODE(314, 9, 9), 1038 /* DFE_2_ERR_GAIN:10:11 */ 1039 PHYMOD_SYMBOL_FIELD_ENCODE(311, 11, 10), 1040 /* DFE_2_GRADIENT_INVERT:12:12 */ 1041 PHYMOD_SYMBOL_FIELD_ENCODE(313, 12, 12), 1042 /* DFE_2_ERR_SEL:13:14 */ 1043 PHYMOD_SYMBOL_FIELD_ENCODE(312, 14, 13), 1044 /* DFE_2_EN:15:15 */ 1045 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(310, 15, 15) 1046 }; 1047 static uint32_t BCMI_EAGLE_XGXS_DSC_DFE_2_PAT_CTLr_fields[] = 1048 { 1049 /* DFE_2_PATTERN:0:5 */ 1050 PHYMOD_SYMBOL_FIELD_ENCODE(317, 5, 0), 1051 /* DFE_2_PATTERN_BIT_EN:8:13 */ 1052 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(318, 13, 8) 1053 }; 1054 static uint32_t BCMI_EAGLE_XGXS_DSC_DFE_2_STSr_fields[] = 1055 { 1056 /* DFE_2_CMN:0:4 */ 1057 PHYMOD_SYMBOL_FIELD_ENCODE(307, 4, 0), 1058 /* DFE_2_SO:5:5 */ 1059 PHYMOD_SYMBOL_FIELD_ENCODE(320, 5, 5), 1060 /* DFE_2_SE:6:6 */ 1061 PHYMOD_SYMBOL_FIELD_ENCODE(319, 6, 6), 1062 /* DFE_2_O:8:10 */ 1063 PHYMOD_SYMBOL_FIELD_ENCODE(316, 10, 8), 1064 /* DFE_2_E:11:13 */ 1065 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(309, 13, 11) 1066 }; 1067 static uint32_t BCMI_EAGLE_XGXS_DSC_DFE_3_4_5_STSr_fields[] = 1068 { 1069 /* DFE_3_CMN:0:5 */ 1070 PHYMOD_SYMBOL_FIELD_ENCODE(322, 5, 0), 1071 /* DFE_4_CMN:6:10 */ 1072 PHYMOD_SYMBOL_FIELD_ENCODE(332, 10, 6), 1073 /* DFE_5_CMN:11:15 */ 1074 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(342, 15, 11) 1075 }; 1076 static uint32_t BCMI_EAGLE_XGXS_DSC_DFE_3_CTLr_fields[] = 1077 { 1078 /* DFE_3_ACC_CLR:0:0 */ 1079 PHYMOD_SYMBOL_FIELD_ENCODE(321, 0, 0), 1080 /* DFE_3_INV_P1:8:8 */ 1081 PHYMOD_SYMBOL_FIELD_ENCODE(328, 8, 8), 1082 /* DFE_3_INV_M1:9:9 */ 1083 PHYMOD_SYMBOL_FIELD_ENCODE(327, 9, 9), 1084 /* DFE_3_ERR_GAIN:10:11 */ 1085 PHYMOD_SYMBOL_FIELD_ENCODE(324, 11, 10), 1086 /* DFE_3_GRADIENT_INVERT:12:12 */ 1087 PHYMOD_SYMBOL_FIELD_ENCODE(326, 12, 12), 1088 /* DFE_3_ERR_SEL:13:14 */ 1089 PHYMOD_SYMBOL_FIELD_ENCODE(325, 14, 13), 1090 /* DFE_3_EN:15:15 */ 1091 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(323, 15, 15) 1092 }; 1093 static uint32_t BCMI_EAGLE_XGXS_DSC_DFE_3_PAT_CTLr_fields[] = 1094 { 1095 /* DFE_3_PATTERN:0:5 */ 1096 PHYMOD_SYMBOL_FIELD_ENCODE(329, 5, 0), 1097 /* DFE_3_PATTERN_BIT_EN:8:13 */ 1098 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(330, 13, 8) 1099 }; 1100 static uint32_t BCMI_EAGLE_XGXS_DSC_DFE_4_CTLr_fields[] = 1101 { 1102 /* DFE_4_ACC_CLR:0:0 */ 1103 PHYMOD_SYMBOL_FIELD_ENCODE(331, 0, 0), 1104 /* DFE_4_INV_P1:8:8 */ 1105 PHYMOD_SYMBOL_FIELD_ENCODE(338, 8, 8), 1106 /* DFE_4_INV_M1:9:9 */ 1107 PHYMOD_SYMBOL_FIELD_ENCODE(337, 9, 9), 1108 /* DFE_4_ERR_GAIN:10:11 */ 1109 PHYMOD_SYMBOL_FIELD_ENCODE(334, 11, 10), 1110 /* DFE_4_GRADIENT_INVERT:12:12 */ 1111 PHYMOD_SYMBOL_FIELD_ENCODE(336, 12, 12), 1112 /* DFE_4_ERR_SEL:13:14 */ 1113 PHYMOD_SYMBOL_FIELD_ENCODE(335, 14, 13), 1114 /* DFE_4_EN:15:15 */ 1115 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(333, 15, 15) 1116 }; 1117 static uint32_t BCMI_EAGLE_XGXS_DSC_DFE_4_PAT_CTLr_fields[] = 1118 { 1119 /* DFE_4_PATTERN:0:5 */ 1120 PHYMOD_SYMBOL_FIELD_ENCODE(339, 5, 0), 1121 /* DFE_4_PATTERN_BIT_EN:8:13 */ 1122 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(340, 13, 8) 1123 }; 1124 static uint32_t BCMI_EAGLE_XGXS_DSC_DFE_5_CTLr_fields[] = 1125 { 1126 /* DFE_5_ACC_CLR:0:0 */ 1127 PHYMOD_SYMBOL_FIELD_ENCODE(341, 0, 0), 1128 /* DFE_5_INV_P1:8:8 */ 1129 PHYMOD_SYMBOL_FIELD_ENCODE(348, 8, 8), 1130 /* DFE_5_INV_M1:9:9 */ 1131 PHYMOD_SYMBOL_FIELD_ENCODE(347, 9, 9), 1132 /* DFE_5_ERR_GAIN:10:11 */ 1133 PHYMOD_SYMBOL_FIELD_ENCODE(344, 11, 10), 1134 /* DFE_5_GRADIENT_INVERT:12:12 */ 1135 PHYMOD_SYMBOL_FIELD_ENCODE(346, 12, 12), 1136 /* DFE_5_ERR_SEL:13:14 */ 1137 PHYMOD_SYMBOL_FIELD_ENCODE(345, 14, 13), 1138 /* DFE_5_EN:15:15 */ 1139 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(343, 15, 15) 1140 }; 1141 static uint32_t BCMI_EAGLE_XGXS_DSC_DFE_5_PAT_CTLr_fields[] = 1142 { 1143 /* DFE_5_PATTERN:0:5 */ 1144 PHYMOD_SYMBOL_FIELD_ENCODE(349, 5, 0), 1145 /* DFE_5_PATTERN_BIT_EN:8:13 */ 1146 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(350, 13, 8) 1147 }; 1148 static uint32_t BCMI_EAGLE_XGXS_DSC_DFE_COMMON_CTLr_fields[] = 1149 { 1150 /* DFE_UPDATE_GAIN:13:13 */ 1151 PHYMOD_SYMBOL_FIELD_ENCODE(359, 13, 13), 1152 /* DFE_ALLOW_SIMULT:14:14 */ 1153 PHYMOD_SYMBOL_FIELD_ENCODE(352, 14, 14), 1154 /* DFE_ACC_HYS_EN:15:15 */ 1155 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(351, 15, 15) 1156 }; 1157 static uint32_t BCMI_EAGLE_XGXS_DSC_DFE_VGA_OVRRr_fields[] = 1158 { 1159 /* DFE_VGA_WRITE_VAL:0:8 */ 1160 PHYMOD_SYMBOL_FIELD_ENCODE(362, 8, 0), 1161 /* DFE_VGA_WRITE_TAPSEL:9:13 */ 1162 PHYMOD_SYMBOL_FIELD_ENCODE(361, 13, 9), 1163 /* DFE_VGA_WRITE_EN:15:15 */ 1164 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(360, 15, 15) 1165 }; 1166 static uint32_t BCMI_EAGLE_XGXS_DSC_OFFS_ADJ_DATA_EVENr_fields[] = 1167 { 1168 /* DFE_OFFSET_ADJ_DATA_EVEN:0:5 */ 1169 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(353, 5, 0) 1170 }; 1171 static uint32_t BCMI_EAGLE_XGXS_DSC_OFFS_ADJ_DATA_ODDr_fields[] = 1172 { 1173 /* DFE_OFFSET_ADJ_DATA_ODD:0:5 */ 1174 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(354, 5, 0) 1175 }; 1176 static uint32_t BCMI_EAGLE_XGXS_DSC_OFFS_ADJ_M1_EVENr_fields[] = 1177 { 1178 /* DFE_OFFSET_ADJ_M1_EVEN:0:5 */ 1179 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(355, 5, 0) 1180 }; 1181 static uint32_t BCMI_EAGLE_XGXS_DSC_OFFS_ADJ_M1_ODDr_fields[] = 1182 { 1183 /* DFE_OFFSET_ADJ_M1_ODD:0:5 */ 1184 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(356, 5, 0) 1185 }; 1186 static uint32_t BCMI_EAGLE_XGXS_DSC_OFFS_ADJ_P1_EVENr_fields[] = 1187 { 1188 /* DFE_OFFSET_ADJ_P1_EVEN:0:5 */ 1189 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(357, 5, 0) 1190 }; 1191 static uint32_t BCMI_EAGLE_XGXS_DSC_OFFS_ADJ_P1_ODDr_fields[] = 1192 { 1193 /* DFE_OFFSET_ADJ_P1_ODD:0:5 */ 1194 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(358, 5, 0) 1195 }; 1196 static uint32_t BCMI_EAGLE_XGXS_DSC_P1_FRAC_OFFS_CTLr_fields[] = 1197 { 1198 /* P1_OFFSET:0:6 */ 1199 PHYMOD_SYMBOL_FIELD_ENCODE(518, 6, 0), 1200 /* P1_OFFSET_EN:7:7 */ 1201 PHYMOD_SYMBOL_FIELD_ENCODE(519, 7, 7), 1202 /* P1_OFF_3LEVELQ_EN:8:8 */ 1203 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(520, 8, 8) 1204 }; 1205 static uint32_t BCMI_EAGLE_XGXS_DSC_PF2_LOWP_CTLr_fields[] = 1206 { 1207 /* PF2_LOWP_CTRL:0:2 */ 1208 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(542, 2, 0) 1209 }; 1210 static uint32_t BCMI_EAGLE_XGXS_DSC_PF_CTLr_fields[] = 1211 { 1212 /* PF_CTRL:0:3 */ 1213 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(543, 3, 0) 1214 }; 1215 static uint32_t BCMI_EAGLE_XGXS_DSC_RX_PI_CNT_BIN_Dr_fields[] = 1216 { 1217 /* CNT_BIN_D_DREG:0:6 */ 1218 PHYMOD_SYMBOL_FIELD_ENCODE(272, 6, 0), 1219 /* CNT_BIN_P1_DREG:8:14 */ 1220 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(276, 14, 8) 1221 }; 1222 static uint32_t BCMI_EAGLE_XGXS_DSC_RX_PI_CNT_BIN_Mr_fields[] = 1223 { 1224 /* CNT_BIN_M1_MREG:0:6 */ 1225 PHYMOD_SYMBOL_FIELD_ENCODE(274, 6, 0), 1226 /* CNT_BIN_D_MREG:8:14 */ 1227 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(273, 14, 8) 1228 }; 1229 static uint32_t BCMI_EAGLE_XGXS_DSC_RX_PI_CNT_BIN_Pr_fields[] = 1230 { 1231 /* CNT_BIN_P1_PREG:0:6 */ 1232 PHYMOD_SYMBOL_FIELD_ENCODE(277, 6, 0), 1233 /* CNT_BIN_M1_PREG:8:14 */ 1234 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(275, 14, 8) 1235 }; 1236 static uint32_t BCMI_EAGLE_XGXS_DSC_RX_PI_CTLr_fields[] = 1237 { 1238 /* RX_PI_PHASE_STEP_CNT:0:6 */ 1239 PHYMOD_SYMBOL_FIELD_ENCODE(642, 6, 0), 1240 /* RX_PI_MANUAL_STROBE:9:9 */ 1241 PHYMOD_SYMBOL_FIELD_ENCODE(641, 9, 9), 1242 /* RX_PI_PHASE_STEP_DIR:10:10 */ 1243 PHYMOD_SYMBOL_FIELD_ENCODE(643, 10, 10), 1244 /* RX_PI_MANUAL_MODE:11:11 */ 1245 PHYMOD_SYMBOL_FIELD_ENCODE(639, 11, 11), 1246 /* RX_PI_SLICERS_EN:12:14 */ 1247 PHYMOD_SYMBOL_FIELD_ENCODE(644, 14, 12), 1248 /* RX_PI_MANUAL_RESET:15:15 */ 1249 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(640, 15, 15) 1250 }; 1251 static uint32_t BCMI_EAGLE_XGXS_DSC_RX_PI_DIFF_BINr_fields[] = 1252 { 1253 /* CNT_D_MINUS_M1:0:7 */ 1254 PHYMOD_SYMBOL_FIELD_ENCODE(278, 7, 0), 1255 /* CNT_D_MINUS_P1:8:15 */ 1256 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(279, 15, 8) 1257 }; 1258 static uint32_t BCMI_EAGLE_XGXS_DSC_SCRATCHr_fields[] = 1259 { 1260 /* UC_DSC_SCRATCH:0:15 */ 1261 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(774, 15, 0) 1262 }; 1263 static uint32_t BCMI_EAGLE_XGXS_DSC_SM_CTL0r_fields[] = 1264 { 1265 /* EEE_MODE_EN:1:1 */ 1266 PHYMOD_SYMBOL_FIELD_ENCODE(384, 1, 1), 1267 /* EEE_QUIET_RX_AFE_PWRDWN_VAL:2:2 */ 1268 PHYMOD_SYMBOL_FIELD_ENCODE(388, 2, 2), 1269 /* IGNORE_RX_MODE:3:3 */ 1270 PHYMOD_SYMBOL_FIELD_ENCODE(414, 3, 3), 1271 /* CL72_TIMER_EN:4:4 */ 1272 PHYMOD_SYMBOL_FIELD_ENCODE(264, 4, 4), 1273 /* UC_TUNE_EN:5:5 */ 1274 PHYMOD_SYMBOL_FIELD_ENCODE(777, 5, 5), 1275 /* HW_TUNE_EN:6:6 */ 1276 PHYMOD_SYMBOL_FIELD_ENCODE(411, 6, 6), 1277 /* UC_TRNSUM_EN:7:7 */ 1278 PHYMOD_SYMBOL_FIELD_ENCODE(776, 7, 7), 1279 /* EEE_MEASURE_EN:8:8 */ 1280 PHYMOD_SYMBOL_FIELD_ENCODE(383, 8, 8), 1281 /* UC_ACK_DSC_EEE_DONE:11:11 */ 1282 PHYMOD_SYMBOL_FIELD_ENCODE(765, 11, 11), 1283 /* UC_ACK_DSC_RESET:12:12 */ 1284 PHYMOD_SYMBOL_FIELD_ENCODE(766, 12, 12), 1285 /* UC_ACK_DSC_RESTART:13:13 */ 1286 PHYMOD_SYMBOL_FIELD_ENCODE(767, 13, 13), 1287 /* UC_ACK_DSC_CONFIG:14:14 */ 1288 PHYMOD_SYMBOL_FIELD_ENCODE(764, 14, 14), 1289 /* SET_MEAS_INCOMPLETE:15:15 */ 1290 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(650, 15, 15) 1291 }; 1292 static uint32_t BCMI_EAGLE_XGXS_DSC_SM_CTL1r_fields[] = 1293 { 1294 /* RX_DSC_LOCK_FRC:0:0 */ 1295 PHYMOD_SYMBOL_FIELD_ENCODE(637, 0, 0), 1296 /* RX_DSC_LOCK_FRC_VAL:1:1 */ 1297 PHYMOD_SYMBOL_FIELD_ENCODE(638, 1, 1), 1298 /* DSC_CLR_FRC:2:2 */ 1299 PHYMOD_SYMBOL_FIELD_ENCODE(369, 2, 2), 1300 /* DSC_CLR_FRC_VAL:3:3 */ 1301 PHYMOD_SYMBOL_FIELD_ENCODE(370, 3, 3), 1302 /* TRNSUM_FRZ_FRC:4:4 */ 1303 PHYMOD_SYMBOL_FIELD_ENCODE(679, 4, 4), 1304 /* TRNSUM_FRZ_FRC_VAL:5:5 */ 1305 PHYMOD_SYMBOL_FIELD_ENCODE(680, 5, 5), 1306 /* TIMER_DONE_FRC:6:6 */ 1307 PHYMOD_SYMBOL_FIELD_ENCODE(669, 6, 6), 1308 /* TIMER_DONE_FRC_VAL:7:7 */ 1309 PHYMOD_SYMBOL_FIELD_ENCODE(670, 7, 7), 1310 /* FREQ_UPD_EN_FRC:8:8 */ 1311 PHYMOD_SYMBOL_FIELD_ENCODE(406, 8, 8), 1312 /* FREQ_UPD_EN_FRC_VAL:9:9 */ 1313 PHYMOD_SYMBOL_FIELD_ENCODE(407, 9, 9), 1314 /* CDR_FRZ_FRC:10:10 */ 1315 PHYMOD_SYMBOL_FIELD_ENCODE(214, 10, 10), 1316 /* CDR_FRZ_FRC_VAL:11:11 */ 1317 PHYMOD_SYMBOL_FIELD_ENCODE(215, 11, 11), 1318 /* TRNSUM_CLR_FRC:12:12 */ 1319 PHYMOD_SYMBOL_FIELD_ENCODE(671, 12, 12), 1320 /* TRNSUM_CLR_FRC_VAL:13:13 */ 1321 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(672, 13, 13) 1322 }; 1323 static uint32_t BCMI_EAGLE_XGXS_DSC_SM_CTL2r_fields[] = 1324 { 1325 /* EEE_LFSR_CNT:0:12 */ 1326 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(381, 12, 0) 1327 }; 1328 static uint32_t BCMI_EAGLE_XGXS_DSC_SM_CTL3r_fields[] = 1329 { 1330 /* MEASURE_LFSR_CNT:0:12 */ 1331 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(458, 12, 0) 1332 }; 1333 static uint32_t BCMI_EAGLE_XGXS_DSC_SM_CTL4r_fields[] = 1334 { 1335 /* ACQ_CDR_TIMEOUT:0:4 */ 1336 PHYMOD_SYMBOL_FIELD_ENCODE(0, 4, 0), 1337 /* CDR_SETTLE_TIMEOUT:5:9 */ 1338 PHYMOD_SYMBOL_FIELD_ENCODE(225, 9, 5), 1339 /* HW_TUNE_TIMEOUT:10:14 */ 1340 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(412, 14, 10) 1341 }; 1342 static uint32_t BCMI_EAGLE_XGXS_DSC_SM_CTL5r_fields[] = 1343 { 1344 /* MEASURE_TIMEOUT:0:4 */ 1345 PHYMOD_SYMBOL_FIELD_ENCODE(459, 4, 0), 1346 /* EEE_ACQ_CDR_TIMEOUT:5:9 */ 1347 PHYMOD_SYMBOL_FIELD_ENCODE(377, 9, 5), 1348 /* EEE_CDR_SETTLE_TIMEOUT:10:14 */ 1349 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(379, 14, 10) 1350 }; 1351 static uint32_t BCMI_EAGLE_XGXS_DSC_SM_CTL6r_fields[] = 1352 { 1353 /* EEE_HW_TUNE_TIMEOUT:0:4 */ 1354 PHYMOD_SYMBOL_FIELD_ENCODE(380, 4, 0), 1355 /* EEE_ANA_PWR_TIMEOUT:10:14 */ 1356 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(378, 14, 10) 1357 }; 1358 static uint32_t BCMI_EAGLE_XGXS_DSC_SM_CTL7r_fields[] = 1359 { 1360 /* CDR_BWSEL_INTEG_ACQCDR:0:3 */ 1361 PHYMOD_SYMBOL_FIELD_ENCODE(205, 3, 0), 1362 /* CDR_BWSEL_INTEG_EEE_ACQCDR:4:7 */ 1363 PHYMOD_SYMBOL_FIELD_ENCODE(206, 7, 4), 1364 /* CDR_BWSEL_INTEG_NORM:8:11 */ 1365 PHYMOD_SYMBOL_FIELD_ENCODE(207, 11, 8), 1366 /* CDR_BWSEL_PROP_ACQCDR:12:13 */ 1367 PHYMOD_SYMBOL_FIELD_ENCODE(208, 13, 12), 1368 /* CDR_BWSEL_PROP_NORM:14:15 */ 1369 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(210, 15, 14) 1370 }; 1371 static uint32_t BCMI_EAGLE_XGXS_DSC_SM_CTL8r_fields[] = 1372 { 1373 /* PHASE_ERR_OFFSET:0:3 */ 1374 PHYMOD_SYMBOL_FIELD_ENCODE(545, 3, 0), 1375 /* EEE_PHASE_ERR_OFFSET:4:7 */ 1376 PHYMOD_SYMBOL_FIELD_ENCODE(385, 7, 4), 1377 /* PHASE_ERR_OFFSET_EN:8:9 */ 1378 PHYMOD_SYMBOL_FIELD_ENCODE(546, 9, 8), 1379 /* EEE_PHASE_ERR_OFFSET_EN:10:11 */ 1380 PHYMOD_SYMBOL_FIELD_ENCODE(386, 11, 10), 1381 /* CDR_BWSEL_PROP_EEE_ACQCDR:14:15 */ 1382 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(209, 15, 14) 1383 }; 1384 static uint32_t BCMI_EAGLE_XGXS_DSC_SM_CTL9r_fields[] = 1385 { 1386 /* RX_RESTART_PMD:0:0 */ 1387 PHYMOD_SYMBOL_FIELD_ENCODE(646, 0, 0), 1388 /* RX_RESTART_PMD_HOLD:1:1 */ 1389 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(647, 1, 1) 1390 }; 1391 static uint32_t BCMI_EAGLE_XGXS_DSC_SM_STS_DSC_LOCKr_fields[] = 1392 { 1393 /* RX_DSC_LOCK:0:0 */ 1394 PHYMOD_SYMBOL_FIELD_ENCODE(636, 0, 0), 1395 /* MEAS_INCOMPLETE:1:1 */ 1396 PHYMOD_SYMBOL_FIELD_ENCODE(460, 1, 1), 1397 /* EEE_MEASURE_CNT:7:15 */ 1398 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(382, 15, 7) 1399 }; 1400 static uint32_t BCMI_EAGLE_XGXS_DSC_SM_STS_DSC_STr_fields[] = 1401 { 1402 /* DSC_SM_SCRATCH:0:3 */ 1403 PHYMOD_SYMBOL_FIELD_ENCODE(373, 3, 0), 1404 /* DSC_SM_READY_FOR_CMD:4:4 */ 1405 PHYMOD_SYMBOL_FIELD_ENCODE(372, 4, 4), 1406 /* DSC_SM_GP_UC_REQ:5:10 */ 1407 PHYMOD_SYMBOL_FIELD_ENCODE(371, 10, 5), 1408 /* DSC_STATE:11:15 */ 1409 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(374, 15, 11) 1410 }; 1411 static uint32_t BCMI_EAGLE_XGXS_DSC_SM_STS_DSC_ST_EEE_ONE_HOTr_fields[] = 1412 { 1413 /* DSC_STATE_EEE_ONE_HOT:0:6 */ 1414 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(375, 6, 0) 1415 }; 1416 static uint32_t BCMI_EAGLE_XGXS_DSC_SM_STS_DSC_ST_ONE_HOTr_fields[] = 1417 { 1418 /* DSC_STATE_ONE_HOT:0:9 */ 1419 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(376, 9, 0) 1420 }; 1421 static uint32_t BCMI_EAGLE_XGXS_DSC_SM_STS_RESTARTr_fields[] = 1422 { 1423 /* RESTART_PI_EXT_MODE:0:0 */ 1424 PHYMOD_SYMBOL_FIELD_ENCODE(610, 0, 0), 1425 /* RESTART_SIGDET:1:1 */ 1426 PHYMOD_SYMBOL_FIELD_ENCODE(612, 1, 1), 1427 /* RESTART_PMD_RESTART:2:2 */ 1428 PHYMOD_SYMBOL_FIELD_ENCODE(611, 2, 2), 1429 /* EEE_QUIET_FROM_EEE_STATES:3:3 */ 1430 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(387, 3, 3) 1431 }; 1432 static uint32_t BCMI_EAGLE_XGXS_DSC_TRNSUM_CTL1r_fields[] = 1433 { 1434 /* TRNSUM_TAP_RANGE_SEL:2:3 */ 1435 PHYMOD_SYMBOL_FIELD_ENCODE(692, 3, 2), 1436 /* CDR_QPHASE_MULT_EN:4:4 */ 1437 PHYMOD_SYMBOL_FIELD_ENCODE(224, 4, 4), 1438 /* TRNSUM_EYE_CLOSURE_EN:5:5 */ 1439 PHYMOD_SYMBOL_FIELD_ENCODE(676, 5, 5), 1440 /* TRNSUM_GAIN:6:7 */ 1441 PHYMOD_SYMBOL_FIELD_ENCODE(681, 7, 6), 1442 /* TRNSUM_PATTERN_FULL_CHECK_OFF:9:9 */ 1443 PHYMOD_SYMBOL_FIELD_ENCODE(689, 9, 9), 1444 /* TRNSUM_INV_PATTERN_EN:10:10 */ 1445 PHYMOD_SYMBOL_FIELD_ENCODE(683, 10, 10), 1446 /* TRNSUM_RANDOM_TAPSEL_DISABLE:11:11 */ 1447 PHYMOD_SYMBOL_FIELD_ENCODE(690, 11, 11), 1448 /* TRNSUM_ERR_SEL:12:14 */ 1449 PHYMOD_SYMBOL_FIELD_ENCODE(675, 14, 12), 1450 /* TRNSUM_EN:15:15 */ 1451 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(673, 15, 15) 1452 }; 1453 static uint32_t BCMI_EAGLE_XGXS_DSC_TRNSUM_CTL2r_fields[] = 1454 { 1455 /* TRNSUM_PATTERN_BIT_EN:0:7 */ 1456 PHYMOD_SYMBOL_FIELD_ENCODE(688, 7, 0), 1457 /* TRNSUM_PATTERN:8:15 */ 1458 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(687, 15, 8) 1459 }; 1460 static uint32_t BCMI_EAGLE_XGXS_DSC_TRNSUM_CTL3r_fields[] = 1461 { 1462 /* TRNSUM_TAP_SIGN:0:7 */ 1463 PHYMOD_SYMBOL_FIELD_ENCODE(693, 7, 0), 1464 /* TRNSUM_TAP_EN:8:15 */ 1465 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(691, 15, 8) 1466 }; 1467 static uint32_t BCMI_EAGLE_XGXS_DSC_TRNSUM_CTL4r_fields[] = 1468 { 1469 /* TRNSUM_UNSIGNED_CORR:0:0 */ 1470 PHYMOD_SYMBOL_FIELD_ENCODE(694, 0, 0), 1471 /* TRNSUM_UNSIGNED_FLIP:1:1 */ 1472 PHYMOD_SYMBOL_FIELD_ENCODE(695, 1, 1), 1473 /* TDR_BIT_SEL:2:6 */ 1474 PHYMOD_SYMBOL_FIELD_ENCODE(665, 6, 2), 1475 /* TDR_TRNSUM_EN:7:7 */ 1476 PHYMOD_SYMBOL_FIELD_ENCODE(668, 7, 7), 1477 /* TDR_CYCLE_SEL:8:11 */ 1478 PHYMOD_SYMBOL_FIELD_ENCODE(667, 11, 8), 1479 /* TDR_CYCLE_BIN:12:15 */ 1480 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(666, 15, 12) 1481 }; 1482 static uint32_t BCMI_EAGLE_XGXS_DSC_TRNSUM_CTL5r_fields[] = 1483 { 1484 /* SEND_LMS_TO_PCS:14:14 */ 1485 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(649, 14, 14) 1486 }; 1487 static uint32_t BCMI_EAGLE_XGXS_DSC_TRNSUM_STS1r_fields[] = 1488 { 1489 /* TRNSUM_E_HIGH:0:15 */ 1490 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(677, 15, 0) 1491 }; 1492 static uint32_t BCMI_EAGLE_XGXS_DSC_TRNSUM_STS2r_fields[] = 1493 { 1494 /* TRNSUM_E_LOW:0:7 */ 1495 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(678, 7, 0) 1496 }; 1497 static uint32_t BCMI_EAGLE_XGXS_DSC_TRNSUM_STS3r_fields[] = 1498 { 1499 /* TRNSUM_O_HIGH:0:15 */ 1500 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(685, 15, 0) 1501 }; 1502 static uint32_t BCMI_EAGLE_XGXS_DSC_TRNSUM_STS4r_fields[] = 1503 { 1504 /* TRNSUM_O_LOW:0:7 */ 1505 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(686, 7, 0) 1506 }; 1507 static uint32_t BCMI_EAGLE_XGXS_DSC_TRNSUM_STS5r_fields[] = 1508 { 1509 /* TRNSUM_HIGH:0:15 */ 1510 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(682, 15, 0) 1511 }; 1512 static uint32_t BCMI_EAGLE_XGXS_DSC_TRNSUM_STS6r_fields[] = 1513 { 1514 /* TRNSUM_LOW:0:9 */ 1515 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(684, 9, 0) 1516 }; 1517 static uint32_t BCMI_EAGLE_XGXS_DSC_UC_CTLr_fields[] = 1518 { 1519 /* UC_DSC_GP_UC_REQ:0:5 */ 1520 PHYMOD_SYMBOL_FIELD_ENCODE(772, 5, 0), 1521 /* UC_DSC_ERROR_FOUND:6:6 */ 1522 PHYMOD_SYMBOL_FIELD_ENCODE(771, 6, 6), 1523 /* UC_DSC_READY_FOR_CMD:7:7 */ 1524 PHYMOD_SYMBOL_FIELD_ENCODE(773, 7, 7), 1525 /* UC_DSC_SUPP_INFO:8:15 */ 1526 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(775, 15, 8) 1527 }; 1528 static uint32_t BCMI_EAGLE_XGXS_DSC_VGA_CTLr_fields[] = 1529 { 1530 /* VGA_P1_ACC_CLR:0:0 */ 1531 PHYMOD_SYMBOL_FIELD_ENCODE(791, 0, 0), 1532 /* VGA_ACC_HYS_EN:1:1 */ 1533 PHYMOD_SYMBOL_FIELD_ENCODE(783, 1, 1), 1534 /* VGA_TABLEMAP_DISABLE:2:2 */ 1535 PHYMOD_SYMBOL_FIELD_ENCODE(795, 2, 2), 1536 /* VGA_UPDATE_GAIN:6:7 */ 1537 PHYMOD_SYMBOL_FIELD_ENCODE(796, 7, 6), 1538 /* VGA_INV_P1:8:8 */ 1539 PHYMOD_SYMBOL_FIELD_ENCODE(790, 8, 8), 1540 /* VGA_INV_M1:9:9 */ 1541 PHYMOD_SYMBOL_FIELD_ENCODE(789, 9, 9), 1542 /* VGA_ERR_GAIN:10:11 */ 1543 PHYMOD_SYMBOL_FIELD_ENCODE(787, 11, 10), 1544 /* VGA_P1_GRADIENT_INVERT:12:12 */ 1545 PHYMOD_SYMBOL_FIELD_ENCODE(792, 12, 12), 1546 /* VGA_ERR_SEL:13:14 */ 1547 PHYMOD_SYMBOL_FIELD_ENCODE(788, 14, 13), 1548 /* VGA_EN:15:15 */ 1549 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(786, 15, 15) 1550 }; 1551 static uint32_t BCMI_EAGLE_XGXS_DSC_VGA_P1EYEDIAG_STSr_fields[] = 1552 { 1553 /* VGA_BIN:0:5 */ 1554 PHYMOD_SYMBOL_FIELD_ENCODE(784, 5, 0), 1555 /* P1_EYEDIAG_BIN:8:13 */ 1556 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(516, 13, 8) 1557 }; 1558 static uint32_t BCMI_EAGLE_XGXS_DSC_VGA_PAT_EYEDIAG_CTLr_fields[] = 1559 { 1560 /* VGA_PATTERN:0:3 */ 1561 PHYMOD_SYMBOL_FIELD_ENCODE(793, 3, 0), 1562 /* VGA_PATTERN_BIT_EN:4:7 */ 1563 PHYMOD_SYMBOL_FIELD_ENCODE(794, 7, 4), 1564 /* P1_EYEDIAG_EN:15:15 */ 1565 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(517, 15, 15) 1566 }; 1567 static uint32_t BCMI_EAGLE_XGXS_DSC_VGA_TAP_BINr_fields[] = 1568 { 1569 /* VGA_CTRL_BIN:0:4 */ 1570 PHYMOD_SYMBOL_FIELD_ENCODE(785, 4, 0), 1571 /* VGA3_CTRL_BIN:8:11 */ 1572 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(782, 11, 8) 1573 }; 1574 static uint32_t BCMI_EAGLE_XGXS_MDIO_AERr_fields[] = 1575 { 1576 /* MDIO_AER:0:15 */ 1577 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(444, 15, 0) 1578 }; 1579 static uint32_t BCMI_EAGLE_XGXS_MDIO_BCST_PORT_ADDRr_fields[] = 1580 { 1581 /* MDIO_BRCST_PORT_ADDR:0:4 */ 1582 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(446, 4, 0) 1583 }; 1584 static uint32_t BCMI_EAGLE_XGXS_MDIO_BLK_ADDRr_fields[] = 1585 { 1586 /* MDIO_BLK_ADDR:4:14 */ 1587 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(445, 14, 4) 1588 }; 1589 static uint32_t BCMI_EAGLE_XGXS_MDIO_MASKDATAr_fields[] = 1590 { 1591 /* MDIO_MASKDATA:0:15 */ 1592 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(455, 15, 0) 1593 }; 1594 static uint32_t BCMI_EAGLE_XGXS_MDIO_MMD_SELr_fields[] = 1595 { 1596 /* MDIO_DEV_CL22_EN:0:0 */ 1597 PHYMOD_SYMBOL_FIELD_ENCODE(449, 0, 0), 1598 /* MDIO_DEV_PMD_EN:2:2 */ 1599 PHYMOD_SYMBOL_FIELD_ENCODE(453, 2, 2), 1600 /* MDIO_DEV_AN_EN:3:3 */ 1601 PHYMOD_SYMBOL_FIELD_ENCODE(448, 3, 3), 1602 /* MDIO_DEV_PHY_EN:4:4 */ 1603 PHYMOD_SYMBOL_FIELD_ENCODE(452, 4, 4), 1604 /* MDIO_DEV_DTE_EN:5:5 */ 1605 PHYMOD_SYMBOL_FIELD_ENCODE(450, 5, 5), 1606 /* MDIO_DEV_PCS_EN:6:6 */ 1607 PHYMOD_SYMBOL_FIELD_ENCODE(451, 6, 6), 1608 /* MDIO_MULTI_MMDS_EN:14:14 */ 1609 PHYMOD_SYMBOL_FIELD_ENCODE(456, 14, 14), 1610 /* MDIO_MULTI_PRTS_EN:15:15 */ 1611 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(457, 15, 15) 1612 }; 1613 static uint32_t BCMI_EAGLE_XGXS_PATGEN_SEQ0r_fields[] = 1614 { 1615 /* PATT_GEN_SEQ_0:0:15 */ 1616 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(524, 15, 0) 1617 }; 1618 static uint32_t BCMI_EAGLE_XGXS_PATGEN_SEQ1r_fields[] = 1619 { 1620 /* PATT_GEN_SEQ_1:0:15 */ 1621 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(525, 15, 0) 1622 }; 1623 static uint32_t BCMI_EAGLE_XGXS_PATGEN_SEQ2r_fields[] = 1624 { 1625 /* PATT_GEN_SEQ_2:0:15 */ 1626 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(531, 15, 0) 1627 }; 1628 static uint32_t BCMI_EAGLE_XGXS_PATGEN_SEQ3r_fields[] = 1629 { 1630 /* PATT_GEN_SEQ_3:0:15 */ 1631 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(532, 15, 0) 1632 }; 1633 static uint32_t BCMI_EAGLE_XGXS_PATGEN_SEQ4r_fields[] = 1634 { 1635 /* PATT_GEN_SEQ_4:0:15 */ 1636 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(533, 15, 0) 1637 }; 1638 static uint32_t BCMI_EAGLE_XGXS_PATGEN_SEQ5r_fields[] = 1639 { 1640 /* PATT_GEN_SEQ_5:0:15 */ 1641 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(534, 15, 0) 1642 }; 1643 static uint32_t BCMI_EAGLE_XGXS_PATGEN_SEQ6r_fields[] = 1644 { 1645 /* PATT_GEN_SEQ_6:0:15 */ 1646 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(535, 15, 0) 1647 }; 1648 static uint32_t BCMI_EAGLE_XGXS_PATGEN_SEQ7r_fields[] = 1649 { 1650 /* PATT_GEN_SEQ_7:0:15 */ 1651 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(536, 15, 0) 1652 }; 1653 static uint32_t BCMI_EAGLE_XGXS_PATGEN_SEQ8r_fields[] = 1654 { 1655 /* PATT_GEN_SEQ_8:0:15 */ 1656 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(537, 15, 0) 1657 }; 1658 static uint32_t BCMI_EAGLE_XGXS_PATGEN_SEQ9r_fields[] = 1659 { 1660 /* PATT_GEN_SEQ_9:0:15 */ 1661 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(538, 15, 0) 1662 }; 1663 static uint32_t BCMI_EAGLE_XGXS_PATGEN_SEQ_10r_fields[] = 1664 { 1665 /* PATT_GEN_SEQ_10:0:15 */ 1666 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(526, 15, 0) 1667 }; 1668 static uint32_t BCMI_EAGLE_XGXS_PATGEN_SEQ_11r_fields[] = 1669 { 1670 /* PATT_GEN_SEQ_11:0:15 */ 1671 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(527, 15, 0) 1672 }; 1673 static uint32_t BCMI_EAGLE_XGXS_PATGEN_SEQ_12r_fields[] = 1674 { 1675 /* PATT_GEN_SEQ_12:0:15 */ 1676 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(528, 15, 0) 1677 }; 1678 static uint32_t BCMI_EAGLE_XGXS_PATGEN_SEQ_13r_fields[] = 1679 { 1680 /* PATT_GEN_SEQ_13:0:15 */ 1681 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(529, 15, 0) 1682 }; 1683 static uint32_t BCMI_EAGLE_XGXS_PATGEN_SEQ_14r_fields[] = 1684 { 1685 /* PATT_GEN_SEQ_14:0:15 */ 1686 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(530, 15, 0) 1687 }; 1688 static uint32_t BCMI_EAGLE_XGXS_PLL_CAL_CTL0r_fields[] = 1689 { 1690 /* VCO_STEP_TIME:0:7 */ 1691 PHYMOD_SYMBOL_FIELD_ENCODE(781, 7, 0), 1692 /* VCO_START_TIME:8:15 */ 1693 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(780, 15, 8) 1694 }; 1695 static uint32_t BCMI_EAGLE_XGXS_PLL_CAL_CTL1r_fields[] = 1696 { 1697 /* RETRY_TIME:0:7 */ 1698 PHYMOD_SYMBOL_FIELD_ENCODE(614, 7, 0), 1699 /* PRE_FREQ_DET_TIME:8:15 */ 1700 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(601, 15, 8) 1701 }; 1702 static uint32_t BCMI_EAGLE_XGXS_PLL_CAL_CTL2r_fields[] = 1703 { 1704 /* WIN_CAL_CNTR:0:7 */ 1705 PHYMOD_SYMBOL_FIELD_ENCODE(798, 7, 0), 1706 /* RES_CAL_CNTR:8:15 */ 1707 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(613, 15, 8) 1708 }; 1709 static uint32_t BCMI_EAGLE_XGXS_PLL_CAL_CTL3r_fields[] = 1710 { 1711 /* FAST_SEARCH_MODE:0:0 */ 1712 PHYMOD_SYMBOL_FIELD_ENCODE(398, 0, 0), 1713 /* CAP_CNT_MASK_EN:1:1 */ 1714 PHYMOD_SYMBOL_FIELD_ENCODE(192, 1, 1), 1715 /* CAP_SEQ_CYA:2:2 */ 1716 PHYMOD_SYMBOL_FIELD_ENCODE(204, 2, 2), 1717 /* CAP_RESTART:3:3 */ 1718 PHYMOD_SYMBOL_FIELD_ENCODE(199, 3, 3), 1719 /* CAP_RETRY_EN:4:4 */ 1720 PHYMOD_SYMBOL_FIELD_ENCODE(200, 4, 4), 1721 /* CAP_FORCE_SLOWDOWN:5:5 */ 1722 PHYMOD_SYMBOL_FIELD_ENCODE(195, 5, 5), 1723 /* CAP_FORCE_SLOWDOWN_EN:6:6 */ 1724 PHYMOD_SYMBOL_FIELD_ENCODE(196, 6, 6), 1725 /* CAP_SELECT_M_EN:7:7 */ 1726 PHYMOD_SYMBOL_FIELD_ENCODE(203, 7, 7), 1727 /* CAP_SELECT_M:8:15 */ 1728 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(202, 15, 8) 1729 }; 1730 static uint32_t BCMI_EAGLE_XGXS_PLL_CAL_CTL4r_fields[] = 1731 { 1732 /* PLL_LOCK_FRC_VAL:0:0 */ 1733 PHYMOD_SYMBOL_FIELD_ENCODE(557, 0, 0), 1734 /* PLL_LOCK_FRC:1:1 */ 1735 PHYMOD_SYMBOL_FIELD_ENCODE(556, 1, 1), 1736 /* PLL_FORCE_CAP_PASS:2:2 */ 1737 PHYMOD_SYMBOL_FIELD_ENCODE(550, 2, 2), 1738 /* PLL_FORCE_CAP_PASS_EN:3:3 */ 1739 PHYMOD_SYMBOL_FIELD_ENCODE(551, 3, 3), 1740 /* PLL_FORCE_CAP_DONE:4:4 */ 1741 PHYMOD_SYMBOL_FIELD_ENCODE(548, 4, 4), 1742 /* PLL_FORCE_CAP_DONE_EN:5:5 */ 1743 PHYMOD_SYMBOL_FIELD_ENCODE(549, 5, 5), 1744 /* PLL_FORCE_FPASS:6:6 */ 1745 PHYMOD_SYMBOL_FIELD_ENCODE(554, 6, 6), 1746 /* PLL_FORCE_FDONE:7:7 */ 1747 PHYMOD_SYMBOL_FIELD_ENCODE(552, 7, 7), 1748 /* PLL_FORCE_FDONE_EN:8:8 */ 1749 PHYMOD_SYMBOL_FIELD_ENCODE(553, 8, 8), 1750 /* VCO_RST_EN:9:9 */ 1751 PHYMOD_SYMBOL_FIELD_ENCODE(779, 9, 9), 1752 /* SLOWDN_XOR:10:10 */ 1753 PHYMOD_SYMBOL_FIELD_ENCODE(661, 10, 10), 1754 /* FREQ_MONITOR_EN:11:11 */ 1755 PHYMOD_SYMBOL_FIELD_ENCODE(403, 11, 11), 1756 /* FREQ_DET_RESTART_EN:12:12 */ 1757 PHYMOD_SYMBOL_FIELD_ENCODE(399, 12, 12), 1758 /* FREQ_DET_RETRY_EN:13:13 */ 1759 PHYMOD_SYMBOL_FIELD_ENCODE(400, 13, 13), 1760 /* VCO_DONE_EN:14:14 */ 1761 PHYMOD_SYMBOL_FIELD_ENCODE(778, 14, 14), 1762 /* PLL_SEQ_START:15:15 */ 1763 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(564, 15, 15) 1764 }; 1765 static uint32_t BCMI_EAGLE_XGXS_PLL_CAL_CTL5r_fields[] = 1766 { 1767 /* REFCLK_DIVCNT:0:13 */ 1768 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(605, 13, 0) 1769 }; 1770 static uint32_t BCMI_EAGLE_XGXS_PLL_CAL_CTL6r_fields[] = 1771 { 1772 /* REFCLK_DIVCNT_SEL:0:2 */ 1773 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(606, 2, 0) 1774 }; 1775 static uint32_t BCMI_EAGLE_XGXS_PLL_CAL_CTL7r_fields[] = 1776 { 1777 /* PLL_MODE:0:3 */ 1778 PHYMOD_SYMBOL_FIELD_ENCODE(559, 3, 0), 1779 /* RESCAL_FRC_VAL:4:7 */ 1780 PHYMOD_SYMBOL_FIELD_ENCODE(608, 7, 4), 1781 /* RESCAL_FRC:8:8 */ 1782 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(607, 8, 8) 1783 }; 1784 static uint32_t BCMI_EAGLE_XGXS_PLL_CAL_CTL_STS0r_fields[] = 1785 { 1786 /* PLL_LOCK_LH_LL:0:0 */ 1787 PHYMOD_SYMBOL_FIELD_ENCODE(558, 0, 0), 1788 /* PLL_SEQ_PASS_LH_LL:1:1 */ 1789 PHYMOD_SYMBOL_FIELD_ENCODE(563, 1, 1), 1790 /* PLL_SEQ_DONE_LH_LL:2:2 */ 1791 PHYMOD_SYMBOL_FIELD_ENCODE(561, 2, 2), 1792 /* FREQ_PASS_SM_LH_LL:3:3 */ 1793 PHYMOD_SYMBOL_FIELD_ENCODE(405, 3, 3), 1794 /* FREQ_DONE_SM_LH_LL:4:4 */ 1795 PHYMOD_SYMBOL_FIELD_ENCODE(402, 4, 4), 1796 /* CAP_PASS_LH_LL:5:5 */ 1797 PHYMOD_SYMBOL_FIELD_ENCODE(198, 5, 5), 1798 /* CAP_DONE_LH_LL:6:6 */ 1799 PHYMOD_SYMBOL_FIELD_ENCODE(194, 6, 6), 1800 /* PLL_LOCK:8:8 */ 1801 PHYMOD_SYMBOL_FIELD_ENCODE(555, 8, 8), 1802 /* PLL_SEQ_PASS:9:9 */ 1803 PHYMOD_SYMBOL_FIELD_ENCODE(562, 9, 9), 1804 /* PLL_SEQ_DONE:10:10 */ 1805 PHYMOD_SYMBOL_FIELD_ENCODE(560, 10, 10), 1806 /* FREQ_PASS_SM:11:11 */ 1807 PHYMOD_SYMBOL_FIELD_ENCODE(404, 11, 11), 1808 /* FREQ_DONE_SM:12:12 */ 1809 PHYMOD_SYMBOL_FIELD_ENCODE(401, 12, 12), 1810 /* CAP_PASS:13:13 */ 1811 PHYMOD_SYMBOL_FIELD_ENCODE(197, 13, 13), 1812 /* CAP_DONE:14:14 */ 1813 PHYMOD_SYMBOL_FIELD_ENCODE(193, 14, 14), 1814 /* LOST_PLL_LOCK_SM:15:15 */ 1815 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(435, 15, 15) 1816 }; 1817 static uint32_t BCMI_EAGLE_XGXS_PLL_CAL_CTL_STS1r_fields[] = 1818 { 1819 /* CAP_SELECT:0:7 */ 1820 PHYMOD_SYMBOL_FIELD_ENCODE(201, 7, 0), 1821 /* RESCAL_IN:8:11 */ 1822 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(609, 11, 8) 1823 }; 1824 static uint32_t BCMI_EAGLE_XGXS_PLL_CAL_CTL_STS_DBGr_fields[] = 1825 { 1826 /* DBG_SLOWDN:0:0 */ 1827 PHYMOD_SYMBOL_FIELD_ENCODE(289, 0, 0), 1828 /* DBG_SLOWDN_CHANGE:1:1 */ 1829 PHYMOD_SYMBOL_FIELD_ENCODE(290, 1, 1), 1830 /* DBG_FDBCK:2:2 */ 1831 PHYMOD_SYMBOL_FIELD_ENCODE(286, 2, 2), 1832 /* DBG_CAP_STATE_ONE_HOT:3:7 */ 1833 PHYMOD_SYMBOL_FIELD_ENCODE(285, 7, 3), 1834 /* DBG_PLL_STATE_ONE_HOT:8:15 */ 1835 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(288, 15, 8) 1836 }; 1837 static uint32_t BCMI_EAGLE_XGXS_SIGDET_CTL0r_fields[] = 1838 { 1839 /* SIGNAL_DETECT_FILTER_COUNT:0:4 */ 1840 PHYMOD_SYMBOL_FIELD_ENCODE(655, 4, 0), 1841 /* LOS_FILTER_COUNT:8:12 */ 1842 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(436, 12, 8) 1843 }; 1844 static uint32_t BCMI_EAGLE_XGXS_SIGDET_CTL1r_fields[] = 1845 { 1846 /* AFE_SIGNAL_DETECT_DIS:0:0 */ 1847 PHYMOD_SYMBOL_FIELD_ENCODE(7, 0, 0), 1848 /* EXT_LOS_EN:1:1 */ 1849 PHYMOD_SYMBOL_FIELD_ENCODE(396, 1, 1), 1850 /* EXT_LOS_INV:2:2 */ 1851 PHYMOD_SYMBOL_FIELD_ENCODE(397, 2, 2), 1852 /* IGNORE_LP_MODE:3:3 */ 1853 PHYMOD_SYMBOL_FIELD_ENCODE(413, 3, 3), 1854 /* SIGNAL_DETECT_FILTER_1US:4:4 */ 1855 PHYMOD_SYMBOL_FIELD_ENCODE(654, 4, 4), 1856 /* ENERGY_DETECT_FRC:5:5 */ 1857 PHYMOD_SYMBOL_FIELD_ENCODE(391, 5, 5), 1858 /* ENERGY_DETECT_FRC_VAL:6:6 */ 1859 PHYMOD_SYMBOL_FIELD_ENCODE(392, 6, 6), 1860 /* SIGNAL_DETECT_FRC:7:7 */ 1861 PHYMOD_SYMBOL_FIELD_ENCODE(656, 7, 7), 1862 /* SIGNAL_DETECT_FRC_VAL:8:8 */ 1863 PHYMOD_SYMBOL_FIELD_ENCODE(657, 8, 8), 1864 /* ENERGY_DETECT_MASK_COUNT:11:15 */ 1865 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(393, 15, 11) 1866 }; 1867 static uint32_t BCMI_EAGLE_XGXS_SIGDET_CTL2r_fields[] = 1868 { 1869 /* LOS_THRESH:0:2 */ 1870 PHYMOD_SYMBOL_FIELD_ENCODE(437, 2, 0), 1871 /* SIGNAL_DETECT_THRESH:4:6 */ 1872 PHYMOD_SYMBOL_FIELD_ENCODE(660, 6, 4), 1873 /* HOLD_LOS_COUNT:8:10 */ 1874 PHYMOD_SYMBOL_FIELD_ENCODE(409, 10, 8), 1875 /* HOLD_SD_COUNT:11:13 */ 1876 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(410, 13, 11) 1877 }; 1878 static uint32_t BCMI_EAGLE_XGXS_SIGDET_STS0r_fields[] = 1879 { 1880 /* SIGNAL_DETECT:0:0 */ 1881 PHYMOD_SYMBOL_FIELD_ENCODE(652, 0, 0), 1882 /* SIGNAL_DETECT_CHANGE:1:1 */ 1883 PHYMOD_SYMBOL_FIELD_ENCODE(653, 1, 1), 1884 /* ENERGY_DETECT:2:2 */ 1885 PHYMOD_SYMBOL_FIELD_ENCODE(389, 2, 2), 1886 /* ENERGY_DETECT_CHANGE:3:3 */ 1887 PHYMOD_SYMBOL_FIELD_ENCODE(390, 3, 3), 1888 /* SIGNAL_DETECT_RAW:4:4 */ 1889 PHYMOD_SYMBOL_FIELD_ENCODE(658, 4, 4), 1890 /* SIGNAL_DETECT_RAW_CHANGE:5:5 */ 1891 PHYMOD_SYMBOL_FIELD_ENCODE(659, 5, 5), 1892 /* AFE_SIGDET_THRESH:8:10 */ 1893 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(6, 10, 8) 1894 }; 1895 static uint32_t BCMI_EAGLE_XGXS_TLB_RX_DIG_LPBK_CFGr_fields[] = 1896 { 1897 /* DIG_LPBK_EN:0:0 */ 1898 PHYMOD_SYMBOL_FIELD_ENCODE(363, 0, 0), 1899 /* DIG_LPBK_PD_MODE:1:1 */ 1900 PHYMOD_SYMBOL_FIELD_ENCODE(367, 1, 1), 1901 /* DIG_LPBK_PD_FLT_BYPASS:2:2 */ 1902 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(365, 2, 2) 1903 }; 1904 static uint32_t BCMI_EAGLE_XGXS_TLB_RX_DIG_LPBK_PD_STSr_fields[] = 1905 { 1906 /* DIG_LPBK_PD_LATE_IND:0:0 */ 1907 PHYMOD_SYMBOL_FIELD_ENCODE(366, 0, 0), 1908 /* DIG_LPBK_PD_EARLY_IND:1:1 */ 1909 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(364, 1, 1) 1910 }; 1911 static uint32_t BCMI_EAGLE_XGXS_TLB_RX_PMD_RX_LOCK_STSr_fields[] = 1912 { 1913 /* PMD_RX_LOCK:0:0 */ 1914 PHYMOD_SYMBOL_FIELD_ENCODE(575, 0, 0), 1915 /* PMD_RX_LOCK_CHANGE:1:1 */ 1916 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(576, 1, 1) 1917 }; 1918 static uint32_t BCMI_EAGLE_XGXS_TLB_RX_PRBS_CHK_CFGr_fields[] = 1919 { 1920 /* PRBS_CHK_EN:0:0 */ 1921 PHYMOD_SYMBOL_FIELD_ENCODE(583, 0, 0), 1922 /* PRBS_CHK_MODE_SEL:1:3 */ 1923 PHYMOD_SYMBOL_FIELD_ENCODE(595, 3, 1), 1924 /* PRBS_CHK_INV:4:4 */ 1925 PHYMOD_SYMBOL_FIELD_ENCODE(590, 4, 4), 1926 /* PRBS_CHK_MODE:5:6 */ 1927 PHYMOD_SYMBOL_FIELD_ENCODE(594, 6, 5), 1928 /* PRBS_CHK_EN_AUTO_MODE:7:7 */ 1929 PHYMOD_SYMBOL_FIELD_ENCODE(584, 7, 7), 1930 /* PRBS_CHK_ERR_CNT_BURST_MODE:9:9 */ 1931 PHYMOD_SYMBOL_FIELD_ENCODE(587, 9, 9), 1932 /* TRNSUM_ERROR_COUNT_EN:10:10 */ 1933 PHYMOD_SYMBOL_FIELD_ENCODE(674, 10, 10), 1934 /* PRBS_CHK_CLK_EN_FRC_ON:11:11 */ 1935 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(582, 11, 11) 1936 }; 1937 static uint32_t BCMI_EAGLE_XGXS_TLB_RX_PRBS_CHK_CNT_CFGr_fields[] = 1938 { 1939 /* PRBS_CHK_LOCK_CNT:0:4 */ 1940 PHYMOD_SYMBOL_FIELD_ENCODE(592, 4, 0), 1941 /* PRBS_CHK_OOL_CNT:8:12 */ 1942 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(596, 12, 8) 1943 }; 1944 static uint32_t BCMI_EAGLE_XGXS_TLB_RX_PRBS_CHK_EN_TMR_CTLr_fields[] = 1945 { 1946 /* PRBS_CHK_EN_TIMER_MODE:0:1 */ 1947 PHYMOD_SYMBOL_FIELD_ENCODE(586, 1, 0), 1948 /* PRBS_CHK_EN_TIMEOUT:8:12 */ 1949 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(585, 12, 8) 1950 }; 1951 static uint32_t BCMI_EAGLE_XGXS_TLB_RX_PRBS_CHK_ERR_CNT_LSB_STSr_fields[] = 1952 { 1953 /* PRBS_CHK_ERR_CNT_LSB:0:15 */ 1954 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(588, 15, 0) 1955 }; 1956 static uint32_t BCMI_EAGLE_XGXS_TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr_fields[] = 1957 { 1958 /* PRBS_CHK_ERR_CNT_MSB:0:14 */ 1959 PHYMOD_SYMBOL_FIELD_ENCODE(589, 14, 0), 1960 /* PRBS_CHK_LOCK_LOST_LH:15:15 */ 1961 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(593, 15, 15) 1962 }; 1963 static uint32_t BCMI_EAGLE_XGXS_TLB_RX_PRBS_CHK_LOCK_STSr_fields[] = 1964 { 1965 /* PRBS_CHK_LOCK:0:0 */ 1966 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(591, 0, 0) 1967 }; 1968 static uint32_t BCMI_EAGLE_XGXS_TLB_RX_TLB_RX_MISC_CFGr_fields[] = 1969 { 1970 /* RX_PMD_DP_INVERT:0:0 */ 1971 PHYMOD_SYMBOL_FIELD_ENCODE(645, 0, 0), 1972 /* RX_AGGREGATOR_BYPASS_EN:1:1 */ 1973 PHYMOD_SYMBOL_FIELD_ENCODE(635, 1, 1), 1974 /* DBG_MASK_DIG_LPBK_EN:2:2 */ 1975 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(287, 2, 2) 1976 }; 1977 static uint32_t BCMI_EAGLE_XGXS_TLB_TX_PATGEN_CFGr_fields[] = 1978 { 1979 /* PATT_GEN_EN:0:0 */ 1980 PHYMOD_SYMBOL_FIELD_ENCODE(523, 0, 0), 1981 /* PATT_GEN_STOP_POS:8:11 */ 1982 PHYMOD_SYMBOL_FIELD_ENCODE(540, 11, 8), 1983 /* PATT_GEN_START_POS:12:15 */ 1984 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(539, 15, 12) 1985 }; 1986 static uint32_t BCMI_EAGLE_XGXS_TLB_TX_PRBS_GEN_CFGr_fields[] = 1987 { 1988 /* PRBS_GEN_EN:0:0 */ 1989 PHYMOD_SYMBOL_FIELD_ENCODE(597, 0, 0), 1990 /* PRBS_GEN_MODE_SEL:1:3 */ 1991 PHYMOD_SYMBOL_FIELD_ENCODE(600, 3, 1), 1992 /* PRBS_GEN_INV:4:4 */ 1993 PHYMOD_SYMBOL_FIELD_ENCODE(599, 4, 4), 1994 /* PRBS_GEN_ERR_INS:5:5 */ 1995 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(598, 5, 5) 1996 }; 1997 static uint32_t BCMI_EAGLE_XGXS_TLB_TX_RMT_LPBK_CFGr_fields[] = 1998 { 1999 /* RMT_LPBK_EN:0:0 */ 2000 PHYMOD_SYMBOL_FIELD_ENCODE(628, 0, 0), 2001 /* RMT_LPBK_PD_MODE:1:1 */ 2002 PHYMOD_SYMBOL_FIELD_ENCODE(632, 1, 1), 2003 /* RMT_LPBK_PD_FRC_ON:2:2 */ 2004 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(630, 2, 2) 2005 }; 2006 static uint32_t BCMI_EAGLE_XGXS_TLB_TX_RMT_LPBK_PD_STSr_fields[] = 2007 { 2008 /* RMT_LPBK_PD_LATE_IND:0:0 */ 2009 PHYMOD_SYMBOL_FIELD_ENCODE(631, 0, 0), 2010 /* RMT_LPBK_PD_EARLY_IND:1:1 */ 2011 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(629, 1, 1) 2012 }; 2013 static uint32_t BCMI_EAGLE_XGXS_TLB_TX_TLB_TX_MISC_CFGr_fields[] = 2014 { 2015 /* TX_PMD_DP_INVERT:0:0 */ 2016 PHYMOD_SYMBOL_FIELD_ENCODE(758, 0, 0), 2017 /* TX_PCS_NATIVE_ANA_FRMT_EN:1:1 */ 2018 PHYMOD_SYMBOL_FIELD_ENCODE(724, 1, 1), 2019 /* TX_MUX_SEL_ORDER:2:2 */ 2020 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(723, 2, 2) 2021 }; 2022 static uint32_t BCMI_EAGLE_XGXS_TLB_TX_TX_PI_LOOP_TIMING_CFGr_fields[] = 2023 { 2024 /* TX_PI_LOOP_TIMING_SRC_SEL:0:0 */ 2025 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(744, 0, 0) 2026 }; 2027 static uint32_t BCMI_EAGLE_XGXS_TXFIR_CTL1r_fields[] = 2028 { 2029 /* TXFIR_PRE_OVERRIDE:0:4 */ 2030 PHYMOD_SYMBOL_FIELD_ENCODE(714, 4, 0), 2031 /* TXFIR_POST_OVERRIDE:5:10 */ 2032 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(710, 10, 5) 2033 }; 2034 static uint32_t BCMI_EAGLE_XGXS_TXFIR_CTL2r_fields[] = 2035 { 2036 /* TXFIR_MAIN_OVERRIDE:0:6 */ 2037 PHYMOD_SYMBOL_FIELD_ENCODE(699, 6, 0), 2038 /* TXFIR_POST2:7:11 */ 2039 PHYMOD_SYMBOL_FIELD_ENCODE(701, 11, 7), 2040 /* TXFIR_OVERRIDE_EN:15:15 */ 2041 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(700, 15, 15) 2042 }; 2043 static uint32_t BCMI_EAGLE_XGXS_TXFIR_CTL3r_fields[] = 2044 { 2045 /* TXFIR_PRE_OFFSET:0:3 */ 2046 PHYMOD_SYMBOL_FIELD_ENCODE(713, 3, 0), 2047 /* TXFIR_MAIN_OFFSET:4:7 */ 2048 PHYMOD_SYMBOL_FIELD_ENCODE(698, 7, 4), 2049 /* TXFIR_POST_OFFSET:8:11 */ 2050 PHYMOD_SYMBOL_FIELD_ENCODE(709, 11, 8), 2051 /* TXFIR_POST2_OFFSET:12:15 */ 2052 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(703, 15, 12) 2053 }; 2054 static uint32_t BCMI_EAGLE_XGXS_TXFIR_CTL4r_fields[] = 2055 { 2056 /* TXFIR_POST3:0:3 */ 2057 PHYMOD_SYMBOL_FIELD_ENCODE(704, 3, 0), 2058 /* TXFIR_POST3_OFFSET:8:11 */ 2059 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(706, 11, 8) 2060 }; 2061 static uint32_t BCMI_EAGLE_XGXS_TXFIR_MISC_CTL1r_fields[] = 2062 { 2063 /* SDK_TX_DISABLE:0:0 */ 2064 PHYMOD_SYMBOL_FIELD_ENCODE(648, 0, 0), 2065 /* PMD_TX_DISABLE_PIN_DIS:1:1 */ 2066 PHYMOD_SYMBOL_FIELD_ENCODE(579, 1, 1), 2067 /* TX_DISABLE_TIMER_CTRL:2:7 */ 2068 PHYMOD_SYMBOL_FIELD_ENCODE(716, 7, 2), 2069 /* TX_EEE_QUIET_EN:8:8 */ 2070 PHYMOD_SYMBOL_FIELD_ENCODE(718, 8, 8), 2071 /* TX_EEE_ALERT_EN:9:9 */ 2072 PHYMOD_SYMBOL_FIELD_ENCODE(717, 9, 9), 2073 /* TX_DISABLE_OUTPUT_SEL:10:11 */ 2074 PHYMOD_SYMBOL_FIELD_ENCODE(715, 11, 10), 2075 /* DP_RESET_TX_DISABLE_DIS:12:12 */ 2076 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(368, 12, 12) 2077 }; 2078 static uint32_t BCMI_EAGLE_XGXS_TXFIR_STS1r_fields[] = 2079 { 2080 /* TXFIR_PRE_AFTER_OVR:0:4 */ 2081 PHYMOD_SYMBOL_FIELD_ENCODE(712, 4, 0), 2082 /* TXFIR_POST_AFTER_OVR:5:10 */ 2083 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(708, 10, 5) 2084 }; 2085 static uint32_t BCMI_EAGLE_XGXS_TXFIR_STS2r_fields[] = 2086 { 2087 /* TXFIR_MAIN_AFTER_OVR:0:6 */ 2088 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(697, 6, 0) 2089 }; 2090 static uint32_t BCMI_EAGLE_XGXS_TXFIR_STS3r_fields[] = 2091 { 2092 /* TXFIR_PRE_ADJUSTED:0:4 */ 2093 PHYMOD_SYMBOL_FIELD_ENCODE(711, 4, 0), 2094 /* TXFIR_POST_ADJUSTED:5:10 */ 2095 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(707, 10, 5) 2096 }; 2097 static uint32_t BCMI_EAGLE_XGXS_TXFIR_STS4r_fields[] = 2098 { 2099 /* TXFIR_MAIN_ADJUSTED:0:6 */ 2100 PHYMOD_SYMBOL_FIELD_ENCODE(696, 6, 0), 2101 /* TXFIR_POST2_ADJUSTED:7:11 */ 2102 PHYMOD_SYMBOL_FIELD_ENCODE(702, 11, 7), 2103 /* TXFIR_POST3_ADJUSTED:12:15 */ 2104 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(705, 15, 12) 2105 }; 2106 static uint32_t BCMI_EAGLE_XGXS_TXFIR_UC_CTLr_fields[] = 2107 { 2108 /* MICRO_TX_DISABLE:0:0 */ 2109 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(504, 0, 0) 2110 }; 2111 static uint32_t BCMI_EAGLE_XGXS_TX_PI_CTL0r_fields[] = 2112 { 2113 /* TX_PI_EN:0:0 */ 2114 PHYMOD_SYMBOL_FIELD_ENCODE(725, 0, 0), 2115 /* TX_PI_JITTER_FILTER_EN:1:1 */ 2116 PHYMOD_SYMBOL_FIELD_ENCODE(737, 1, 1), 2117 /* TX_PI_EXT_CTRL_EN:2:2 */ 2118 PHYMOD_SYMBOL_FIELD_ENCODE(726, 2, 2), 2119 /* TX_PI_FREQ_OVERRIDE_EN:3:3 */ 2120 PHYMOD_SYMBOL_FIELD_ENCODE(730, 3, 3), 2121 /* TX_PI_SJ_GEN_EN:4:4 */ 2122 PHYMOD_SYMBOL_FIELD_ENCODE(756, 4, 4), 2123 /* TX_PI_SSC_GEN_EN:5:5 */ 2124 PHYMOD_SYMBOL_FIELD_ENCODE(757, 5, 5), 2125 /* TX_PI_JIT_SSC_FREQ_MODE:6:6 */ 2126 PHYMOD_SYMBOL_FIELD_ENCODE(740, 6, 6), 2127 /* TX_PI_SECOND_ORDER_LOOP_EN:7:7 */ 2128 PHYMOD_SYMBOL_FIELD_ENCODE(755, 7, 7), 2129 /* TX_PI_FIRST_ORDER_BWSEL_INTEG:8:9 */ 2130 PHYMOD_SYMBOL_FIELD_ENCODE(728, 9, 8), 2131 /* TX_PI_SECOND_ORDER_BWSEL_INTEG:10:11 */ 2132 PHYMOD_SYMBOL_FIELD_ENCODE(754, 11, 10), 2133 /* TX_PI_EXT_PHASE_BWSEL_INTEG:12:14 */ 2134 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(727, 14, 12) 2135 }; 2136 static uint32_t BCMI_EAGLE_XGXS_TX_PI_CTL1r_fields[] = 2137 { 2138 /* TX_PI_FREQ_OVERRIDE_VAL:0:14 */ 2139 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(731, 14, 0) 2140 }; 2141 static uint32_t BCMI_EAGLE_XGXS_TX_PI_CTL2r_fields[] = 2142 { 2143 /* TX_PI_JIT_FREQ_IDX:0:5 */ 2144 PHYMOD_SYMBOL_FIELD_ENCODE(739, 5, 0), 2145 /* TX_PI_JIT_AMP:8:13 */ 2146 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(738, 13, 8) 2147 }; 2148 static uint32_t BCMI_EAGLE_XGXS_TX_PI_CTL3r_fields[] = 2149 { 2150 /* TX_PI_PHASE_OVERRIDE:0:0 */ 2151 PHYMOD_SYMBOL_FIELD_ENCODE(748, 0, 0), 2152 /* TX_PI_PHASE_STROBE:1:1 */ 2153 PHYMOD_SYMBOL_FIELD_ENCODE(751, 1, 1), 2154 /* TX_PI_PHASE_STEP_DIR:2:2 */ 2155 PHYMOD_SYMBOL_FIELD_ENCODE(749, 2, 2), 2156 /* TX_PI_PHASE_INVERT:4:4 */ 2157 PHYMOD_SYMBOL_FIELD_ENCODE(747, 4, 4), 2158 /* TX_PI_PHASE_STEP_NUM:8:11 */ 2159 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(750, 11, 8) 2160 }; 2161 static uint32_t BCMI_EAGLE_XGXS_TX_PI_CTL4r_fields[] = 2162 { 2163 /* TX_PI_FRZ_FRC:0:0 */ 2164 PHYMOD_SYMBOL_FIELD_ENCODE(732, 0, 0), 2165 /* TX_PI_FRZ_FRC_VAL:1:1 */ 2166 PHYMOD_SYMBOL_FIELD_ENCODE(733, 1, 1), 2167 /* TX_PI_FRZ_MODE:2:2 */ 2168 PHYMOD_SYMBOL_FIELD_ENCODE(734, 2, 2), 2169 /* TX_PI_RESET_CODE_DBG:3:3 */ 2170 PHYMOD_SYMBOL_FIELD_ENCODE(752, 3, 3), 2171 /* TX_PI_RMT_LPBK_BYPASS_FLT:4:4 */ 2172 PHYMOD_SYMBOL_FIELD_ENCODE(753, 4, 4), 2173 /* TX_PI_FRC_PHASE_STEP_MUX_SEL:5:5 */ 2174 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(729, 5, 5) 2175 }; 2176 static uint32_t BCMI_EAGLE_XGXS_TX_PI_CTL6r_fields[] = 2177 { 2178 /* TX_PI_LANE_SEL_FRC_VAL:0:4 */ 2179 PHYMOD_SYMBOL_FIELD_ENCODE(742, 4, 0), 2180 /* TX_PI_LANE_SEL_FRC:8:8 */ 2181 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(741, 8, 8) 2182 }; 2183 static uint32_t BCMI_EAGLE_XGXS_TX_PI_STS0r_fields[] = 2184 { 2185 /* TX_PI_PHASE_CNTR:0:6 */ 2186 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(745, 6, 0) 2187 }; 2188 static uint32_t BCMI_EAGLE_XGXS_TX_PI_STS1r_fields[] = 2189 { 2190 /* TX_PI_INTEG1_REG:0:13 */ 2191 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(735, 13, 0) 2192 }; 2193 static uint32_t BCMI_EAGLE_XGXS_TX_PI_STS2r_fields[] = 2194 { 2195 /* TX_PI_INTEG2_REG:0:14 */ 2196 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(736, 14, 0) 2197 }; 2198 static uint32_t BCMI_EAGLE_XGXS_TX_PI_STS3r_fields[] = 2199 { 2200 /* TX_PI_PHASE_ERR:0:5 */ 2201 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(746, 5, 0) 2202 }; 2203 static uint32_t BCMI_EAGLE_XGXS_UC_ADDRr_fields[] = 2204 { 2205 /* MICRO_RAM_ADDRESS:0:15 */ 2206 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(488, 15, 0) 2207 }; 2208 static uint32_t BCMI_EAGLE_XGXS_UC_COMMANDr_fields[] = 2209 { 2210 /* MICRO_RUN:0:0 */ 2211 PHYMOD_SYMBOL_FIELD_ENCODE(494, 0, 0), 2212 /* MICRO_STOP:1:1 */ 2213 PHYMOD_SYMBOL_FIELD_ENCODE(500, 1, 1), 2214 /* MICRO_READ:2:2 */ 2215 PHYMOD_SYMBOL_FIELD_ENCODE(493, 2, 2), 2216 /* MICRO_WRITE:3:3 */ 2217 PHYMOD_SYMBOL_FIELD_ENCODE(507, 3, 3), 2218 /* MICRO_MDIO_DW8051_RESET_N:4:4 */ 2219 PHYMOD_SYMBOL_FIELD_ENCODE(474, 4, 4), 2220 /* MICRO_MDIO_RAM_READ_AUTOINC_EN:6:6 */ 2221 PHYMOD_SYMBOL_FIELD_ENCODE(478, 6, 6), 2222 /* MICRO_MDIO_RAM_ACCESS_MODE:7:8 */ 2223 PHYMOD_SYMBOL_FIELD_ENCODE(477, 8, 7), 2224 /* MICRO_BYTE_MODE:9:9 */ 2225 PHYMOD_SYMBOL_FIELD_ENCODE(461, 9, 9), 2226 /* MICRO_MDIO_AUTOWAKEUP:10:10 */ 2227 PHYMOD_SYMBOL_FIELD_ENCODE(473, 10, 10), 2228 /* MICRO_MDIO_PROG_RAM_CS_FRC:11:11 */ 2229 PHYMOD_SYMBOL_FIELD_ENCODE(475, 11, 11), 2230 /* MICRO_MDIO_PROG_RAM_CS_FRC_VAL:12:12 */ 2231 PHYMOD_SYMBOL_FIELD_ENCODE(476, 12, 12), 2232 /* MICRO_PMI_HP_ACK_FRC:13:13 */ 2233 PHYMOD_SYMBOL_FIELD_ENCODE(482, 13, 13), 2234 /* MICRO_PMI_HP_ACK_FRC_VAL:14:14 */ 2235 PHYMOD_SYMBOL_FIELD_ENCODE(483, 14, 14), 2236 /* MICRO_INIT_CMD:15:15 */ 2237 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(468, 15, 15) 2238 }; 2239 static uint32_t BCMI_EAGLE_XGXS_UC_COMMAND2r_fields[] = 2240 { 2241 /* MICRO_PMI_ACK_TIMEOUT_VAL:0:3 */ 2242 PHYMOD_SYMBOL_FIELD_ENCODE(481, 3, 0), 2243 /* MICRO_SRST_MDIO_DATARAM_ACCESS:10:10 */ 2244 PHYMOD_SYMBOL_FIELD_ENCODE(496, 10, 10), 2245 /* MICRO_RAM_CLK_INVERT:11:11 */ 2246 PHYMOD_SYMBOL_FIELD_ENCODE(489, 11, 11), 2247 /* MICRO_ZERO_ROM_DATAOUT:12:12 */ 2248 PHYMOD_SYMBOL_FIELD_ENCODE(508, 12, 12), 2249 /* MICRO_SRST_MDIO_LOAD_PROGRAM_RAM:13:13 */ 2250 PHYMOD_SYMBOL_FIELD_ENCODE(497, 13, 13), 2251 /* MICRO_SRST_MDIO_PROGRAM_ACCESS:14:14 */ 2252 PHYMOD_SYMBOL_FIELD_ENCODE(498, 14, 14), 2253 /* MICRO_SRST_DW8051_TO_PMI:15:15 */ 2254 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(495, 15, 15) 2255 }; 2256 static uint32_t BCMI_EAGLE_XGXS_UC_COMMAND3r_fields[] = 2257 { 2258 /* MICRO_PRAM_IF_EN:0:0 */ 2259 PHYMOD_SYMBOL_FIELD_ENCODE(484, 0, 0), 2260 /* MICRO_PRAM_IF_FLOP_BYPASS:1:1 */ 2261 PHYMOD_SYMBOL_FIELD_ENCODE(485, 1, 1), 2262 /* MICRO_PRAM_IF_RSTB:2:2 */ 2263 PHYMOD_SYMBOL_FIELD_ENCODE(486, 2, 2), 2264 /* MICRO_INRUSH_CURRENT_FRC:10:10 */ 2265 PHYMOD_SYMBOL_FIELD_ENCODE(470, 10, 10), 2266 /* MICRO_INRUSH_CURRENT_FRC_VAL:11:11 */ 2267 PHYMOD_SYMBOL_FIELD_ENCODE(471, 11, 11), 2268 /* MICRO_DISABLE_ECC:12:12 */ 2269 PHYMOD_SYMBOL_FIELD_ENCODE(463, 12, 12), 2270 /* MICRO_GEN_STATUS_SEL:13:15 */ 2271 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(467, 15, 13) 2272 }; 2273 static uint32_t BCMI_EAGLE_XGXS_UC_COMMAND4r_fields[] = 2274 { 2275 /* MICRO_SYSTEM_CLK_EN:0:0 */ 2276 PHYMOD_SYMBOL_FIELD_ENCODE(501, 0, 0), 2277 /* MICRO_SYSTEM_RESET_N:1:1 */ 2278 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(502, 1, 1) 2279 }; 2280 static uint32_t BCMI_EAGLE_XGXS_UC_DATARAM_CTL1r_fields[] = 2281 { 2282 /* MICRO_DATARAM_TM:0:9 */ 2283 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(462, 9, 0) 2284 }; 2285 static uint32_t BCMI_EAGLE_XGXS_UC_DWNLOAD_STSr_fields[] = 2286 { 2287 /* MICRO_ERR0:0:0 */ 2288 PHYMOD_SYMBOL_FIELD_ENCODE(464, 0, 0), 2289 /* MICRO_ERR1:1:1 */ 2290 PHYMOD_SYMBOL_FIELD_ENCODE(465, 1, 1), 2291 /* MICRO_FSM:2:5 */ 2292 PHYMOD_SYMBOL_FIELD_ENCODE(466, 5, 2), 2293 /* MICRO_INIT_DONE:15:15 */ 2294 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(469, 15, 15) 2295 }; 2296 static uint32_t BCMI_EAGLE_XGXS_UC_IRAM_CTL1r_fields[] = 2297 { 2298 /* MICRO_IRAM_TM:0:9 */ 2299 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(472, 9, 0) 2300 }; 2301 static uint32_t BCMI_EAGLE_XGXS_UC_MDIO_UC_MAILBOX_LSWr_fields[] = 2302 { 2303 /* MICRO_MDIO_UC_MAILBOX_LSW:0:15 */ 2304 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(479, 15, 0) 2305 }; 2306 static uint32_t BCMI_EAGLE_XGXS_UC_MDIO_UC_MAILBOX_MSWr_fields[] = 2307 { 2308 /* MICRO_MDIO_UC_MAILBOX_MSW:0:15 */ 2309 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(480, 15, 0) 2310 }; 2311 static uint32_t BCMI_EAGLE_XGXS_UC_PROGRAM_RAM_CTL1r_fields[] = 2312 { 2313 /* MICRO_PROGRAM_RAM_TM:0:13 */ 2314 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(487, 13, 0) 2315 }; 2316 static uint32_t BCMI_EAGLE_XGXS_UC_RAMWORDr_fields[] = 2317 { 2318 /* MICRO_RAM_COUNT:0:15 */ 2319 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(490, 15, 0) 2320 }; 2321 static uint32_t BCMI_EAGLE_XGXS_UC_RAM_RDDATAr_fields[] = 2322 { 2323 /* MICRO_RAM_RDDATA:0:15 */ 2324 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(491, 15, 0) 2325 }; 2326 static uint32_t BCMI_EAGLE_XGXS_UC_RAM_WRDATAr_fields[] = 2327 { 2328 /* MICRO_RAM_WRDATA:0:15 */ 2329 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(492, 15, 0) 2330 }; 2331 static uint32_t BCMI_EAGLE_XGXS_UC_SFR_STSr_fields[] = 2332 { 2333 /* MICRO_STATUS_MUXED:0:15 */ 2334 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(499, 15, 0) 2335 }; 2336 static uint32_t BCMI_EAGLE_XGXS_UC_TEMPERATURE_STSr_fields[] = 2337 { 2338 /* MICRO_TEMPATURE_DATA:0:15 */ 2339 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(503, 15, 0) 2340 }; 2341 static uint32_t BCMI_EAGLE_XGXS_UC_UC_MDIO_MAILBOX_LSWr_fields[] = 2342 { 2343 /* MICRO_UC_MDIO_MAILBOX_LSW:0:15 */ 2344 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(505, 15, 0) 2345 }; 2346 static uint32_t BCMI_EAGLE_XGXS_UC_UC_MDIO_MAILBOX_MSWr_fields[] = 2347 { 2348 /* MICRO_UC_MDIO_MAILBOX_MSW:0:15 */ 2349 PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(506, 15, 0) 2350 }; 2351 2352 2353 2354 /******************************************************************************* 2355 * 2356 * The following is the field name table. 2357 */ 2358 #if PHYMOD_CONFIG_INCLUDE_FIELD_NAMES == 1 2359 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_NAMES_BCMI_EAGLE_XGXS 2360 const char* bcmi_eagle_xgxs_fields[] = 2361 { 2362 "ACQ_CDR_TIMEOUT", 2363 "AFE_RX_PWRDN_FRC", 2364 "AFE_RX_PWRDN_FRC_VAL", 2365 "AFE_RX_RESET_FRC", 2366 "AFE_RX_RESET_FRC_VAL", 2367 "AFE_SIGDET_PWRDN", 2368 "AFE_SIGDET_THRESH", 2369 "AFE_SIGNAL_DETECT_DIS", 2370 "AFE_S_PLL_PWRDN", 2371 "AFE_S_PLL_RESET_FRC", 2372 "AFE_S_PLL_RESET_FRC_VAL", 2373 "AFE_TX_PWRDN_FRC", 2374 "AFE_TX_PWRDN_FRC_VAL", 2375 "AFE_TX_RESET_FRC", 2376 "AFE_TX_RESET_FRC_VAL", 2377 "AMS_PLL_2RX_CLKBW", 2378 "AMS_PLL_BGCALR_CTATADJ", 2379 "AMS_PLL_BGCALR_PTATADJ", 2380 "AMS_PLL_BGINT", 2381 "AMS_PLL_BGIP", 2382 "AMS_PLL_BGR_CTATADJ", 2383 "AMS_PLL_BGR_PTATADJ", 2384 "AMS_PLL_CAL_AUX", 2385 "AMS_PLL_CAL_OFF", 2386 "AMS_PLL_COMP_VTH", 2387 "AMS_PLL_DBLR_CTRL", 2388 "AMS_PLL_DITHEREN", 2389 "AMS_PLL_ENABLE_FTUNE", 2390 "AMS_PLL_EN_HRZ", 2391 "AMS_PLL_FORCE_KVH_BW", 2392 "AMS_PLL_FORCE_RESCAL", 2393 "AMS_PLL_FP3_CTRL", 2394 "AMS_PLL_FP3_RH", 2395 "AMS_PLL_FRACN_BYPASS", 2396 "AMS_PLL_FRACN_DIVRANGE", 2397 "AMS_PLL_FRACN_DIV_H", 2398 "AMS_PLL_FRACN_DIV_L", 2399 "AMS_PLL_FRACN_NDIV_INT", 2400 "AMS_PLL_FRACN_SEL", 2401 "AMS_PLL_IMAX_I10GBUF", 2402 "AMS_PLL_IMAX_IBIAS", 2403 "AMS_PLL_IMAX_ICK", 2404 "AMS_PLL_IMAX_ICKGEN", 2405 "AMS_PLL_IMAX_ICLKIDRV1", 2406 "AMS_PLL_IMAX_ICLKINT", 2407 "AMS_PLL_IMAX_ICML", 2408 "AMS_PLL_IMAX_ICOMP", 2409 "AMS_PLL_IMAX_ICP", 2410 "AMS_PLL_IMAX_IOP", 2411 "AMS_PLL_IMIN_I10GBUF", 2412 "AMS_PLL_IMIN_IBIAS", 2413 "AMS_PLL_IMIN_ICK", 2414 "AMS_PLL_IMIN_ICKGEN", 2415 "AMS_PLL_IMIN_ICLKIDRV1", 2416 "AMS_PLL_IMIN_ICLKINT", 2417 "AMS_PLL_IMIN_ICML", 2418 "AMS_PLL_IMIN_ICOMP", 2419 "AMS_PLL_IMIN_ICP", 2420 "AMS_PLL_IMIN_IOP", 2421 "AMS_PLL_IMODE_I10GBUF", 2422 "AMS_PLL_IMODE_IBIAS", 2423 "AMS_PLL_IMODE_ICK", 2424 "AMS_PLL_IMODE_ICKGEN", 2425 "AMS_PLL_IMODE_ICLKIDRV1", 2426 "AMS_PLL_IMODE_ICLKINT", 2427 "AMS_PLL_IMODE_ICML", 2428 "AMS_PLL_IMODE_ICOMP", 2429 "AMS_PLL_IMODE_ICP", 2430 "AMS_PLL_IMODE_IOP", 2431 "AMS_PLL_IQP", 2432 "AMS_PLL_IVCO", 2433 "AMS_PLL_KVH_FORCE", 2434 "AMS_PLL_LOWPWR_6G", 2435 "AMS_PLL_MAX_TEST_PORT_AMPL", 2436 "AMS_PLL_MIX2P1CR_CTATADJ", 2437 "AMS_PLL_MIX2P1CR_PTATADJ", 2438 "AMS_PLL_PDF_FD_SKEW", 2439 "AMS_PLL_PDF_REF_SKEW", 2440 "AMS_PLL_PDF_SKEW_ENLARGE", 2441 "AMS_PLL_REFCLK_DOUBLER", 2442 "AMS_PLL_REFH_PLL", 2443 "AMS_PLL_REFL_PLL", 2444 "AMS_PLL_RESET", 2445 "AMS_PLL_SPARE_100", 2446 "AMS_PLL_SPARE_18", 2447 "AMS_PLL_STS", 2448 "AMS_PLL_TEST_FRACN_EN", 2449 "AMS_PLL_TEST_PLL", 2450 "AMS_PLL_TEST_PNP", 2451 "AMS_PLL_TEST_RX", 2452 "AMS_PLL_TEST_VC", 2453 "AMS_PLL_TEST_VREF", 2454 "AMS_PLL_TXCG_VDDR_BGB", 2455 "AMS_PLL_TX_LOWPWR_6G", 2456 "AMS_PLL_VBYPASS", 2457 "AMS_PLL_VCOICTRL", 2458 "AMS_PLL_VCO_DIV2", 2459 "AMS_PLL_VCO_DIV4", 2460 "AMS_PLL_VCO_IMAX", 2461 "AMS_PLL_VDDR_BGB", 2462 "AMS_RX_DC_COUPLE", 2463 "AMS_RX_DC_OFFSET", 2464 "AMS_RX_DC_OFFSET_RANGE", 2465 "AMS_RX_DFE_OS2X_MODE", 2466 "AMS_RX_EN_10GMODE", 2467 "AMS_RX_EN_VCCTRL", 2468 "AMS_RX_FORCE_DC_OFFSET", 2469 "AMS_RX_I1P25DFE", 2470 "AMS_RX_I4DEADZONE", 2471 "AMS_RX_IMAX_COMMONMODE", 2472 "AMS_RX_IMAX_CTAT", 2473 "AMS_RX_IMAX_DC_OFFSET_DAC", 2474 "AMS_RX_IMAX_DFE_SUMMER", 2475 "AMS_RX_IMAX_DFE_TAP_WEIGHT", 2476 "AMS_RX_IMAX_METRES_EYEDIAG", 2477 "AMS_RX_IMAX_PF", 2478 "AMS_RX_IMAX_PHASE_INT", 2479 "AMS_RX_IMAX_PHASE_INT_P1", 2480 "AMS_RX_IMAX_SIGNAL_DETECT", 2481 "AMS_RX_IMAX_SLICER", 2482 "AMS_RX_IMAX_VGA", 2483 "AMS_RX_IMIN_COMMONMODE", 2484 "AMS_RX_IMIN_CTAT", 2485 "AMS_RX_IMIN_DC_OFFSET_DAC", 2486 "AMS_RX_IMIN_DFE_SUMMER", 2487 "AMS_RX_IMIN_DFE_TAP_WEIGHT", 2488 "AMS_RX_IMIN_METRES_EYEDIAG", 2489 "AMS_RX_IMIN_PF", 2490 "AMS_RX_IMIN_PHASE_INT", 2491 "AMS_RX_IMIN_PHASE_INT_P1", 2492 "AMS_RX_IMIN_SIGNAL_DETECT", 2493 "AMS_RX_IMIN_SLICER", 2494 "AMS_RX_IMIN_VGA", 2495 "AMS_RX_IMODE_CTAT", 2496 "AMS_RX_IMODE_DC_OFFSET_DAC", 2497 "AMS_RX_IMODE_DFE_SUMMER", 2498 "AMS_RX_IMODE_DFE_TAP_WEIGHT", 2499 "AMS_RX_IMODE_METRES_EYEDIAG", 2500 "AMS_RX_IMODE_PF", 2501 "AMS_RX_IMODE_PHASE_INT", 2502 "AMS_RX_IMODE_PHASE_INT_P1", 2503 "AMS_RX_IMODE_SIGNAL_DETECT", 2504 "AMS_RX_IMODE_SLICER", 2505 "AMS_RX_IMODE_VGA", 2506 "AMS_RX_IMOD_COMMONMODE", 2507 "AMS_RX_PHASE_INT_AMPL_CTRL", 2508 "AMS_RX_PHS_INTERP_RESCAL_MUX", 2509 "AMS_RX_SEL_DFECKDELAY", 2510 "AMS_RX_SEL_TH4DFE", 2511 "AMS_RX_SEL_UGBW", 2512 "AMS_RX_SIGDET_BYPASS", 2513 "AMS_RX_SIGDET_LOW_POWER", 2514 "AMS_RX_SIGDET_THRESHOLD", 2515 "AMS_RX_SIG_PWRDN", 2516 "AMS_RX_SPARE_32", 2517 "AMS_RX_SPARE_33", 2518 "AMS_RX_SPARE_34", 2519 "AMS_RX_SPARE_46", 2520 "AMS_RX_SPARE_47", 2521 "AMS_RX_SPARE_62", 2522 "AMS_RX_SPARE_63", 2523 "AMS_RX_STS", 2524 "AMS_RX_TPORT_EN", 2525 "AMS_RX_VGA_BW_EXTENSION", 2526 "AMS_RX_VGA_OUTPUT_IDLE", 2527 "AMS_RX_VGA_RESCAL_MUX", 2528 "AMS_TX_AMP_CTL", 2529 "AMS_TX_CAL_AUX", 2530 "AMS_TX_CAL_OFF", 2531 "AMS_TX_DCC_DIS", 2532 "AMS_TX_DCC_SEL", 2533 "AMS_TX_DRIVERMODE", 2534 "AMS_TX_ELEC_IDLE_AUX", 2535 "AMS_TX_IBIAS", 2536 "AMS_TX_ICML", 2537 "AMS_TX_IDCC", 2538 "AMS_TX_KR_TEST_MODE", 2539 "AMS_TX_LP_OVRD", 2540 "AMS_TX_OSR4", 2541 "AMS_TX_POST2_COEF", 2542 "AMS_TX_POST3_COEF", 2543 "AMS_TX_SEL_HALFRATE", 2544 "AMS_TX_SIGN_POST2", 2545 "AMS_TX_SIGN_POST3", 2546 "AMS_TX_SPARE_1", 2547 "AMS_TX_SPARE_2", 2548 "AMS_TX_SPARE_3", 2549 "AMS_TX_SPARE_30_25", 2550 "AMS_TX_STS", 2551 "AMS_TX_TEST_DATA", 2552 "AMS_TX_TICKSEL", 2553 "BR_PD_EN", 2554 "CAP_CNT_MASK_EN", 2555 "CAP_DONE", 2556 "CAP_DONE_LH_LL", 2557 "CAP_FORCE_SLOWDOWN", 2558 "CAP_FORCE_SLOWDOWN_EN", 2559 "CAP_PASS", 2560 "CAP_PASS_LH_LL", 2561 "CAP_RESTART", 2562 "CAP_RETRY_EN", 2563 "CAP_SELECT", 2564 "CAP_SELECT_M", 2565 "CAP_SELECT_M_EN", 2566 "CAP_SEQ_CYA", 2567 "CDR_BWSEL_INTEG_ACQCDR", 2568 "CDR_BWSEL_INTEG_EEE_ACQCDR", 2569 "CDR_BWSEL_INTEG_NORM", 2570 "CDR_BWSEL_PROP_ACQCDR", 2571 "CDR_BWSEL_PROP_EEE_ACQCDR", 2572 "CDR_BWSEL_PROP_NORM", 2573 "CDR_FREQ_EN", 2574 "CDR_FREQ_OVERRIDE_EN", 2575 "CDR_FREQ_OVERRIDE_VAL", 2576 "CDR_FRZ_FRC", 2577 "CDR_FRZ_FRC_VAL", 2578 "CDR_INTEG_REG", 2579 "CDR_INTEG_REG_CLR", 2580 "CDR_INTEG_SAT_SEL", 2581 "CDR_LM_OUTOFLOCK", 2582 "CDR_LM_THR_SEL", 2583 "CDR_PHASE_ERR", 2584 "CDR_PHASE_ERR_FRZ", 2585 "CDR_PHASE_SAT_CTRL", 2586 "CDR_QPHASE_MULT_EN", 2587 "CDR_SETTLE_TIMEOUT", 2588 "CDR_ZERO_POLARITY", 2589 "CL72_BAD_MARKER_CNT", 2590 "CL72_BRK_RING_OSC", 2591 "CL72_CTRL_FRAME_DLY", 2592 "CL72_DIS_LP_COEFF_UPDATES_TO_LD", 2593 "CL72_DIS_MAX_WAIT_TIMER", 2594 "CL72_DME_CELL_BOUNDARY_CHK", 2595 "CL72_DOUBLE_CMD_EN", 2596 "CL72_FRAME_LOCK_LH", 2597 "CL72_FRAME_LOCK_RDY_FOR_CMD_EN", 2598 "CL72_GOOD_MARKER_CNT", 2599 "CL72_IEEE_FRAME_LOCK", 2600 "CL72_IEEE_LD_COEFF_UPDATE", 2601 "CL72_IEEE_LD_STATUS_REPORT", 2602 "CL72_IEEE_LP_COEFF_UPDATE", 2603 "CL72_IEEE_LP_STATUS_REPORT", 2604 "CL72_IEEE_RECEIVER_STATUS", 2605 "CL72_IEEE_RESTART_TRAINING", 2606 "CL72_IEEE_TRAINING_ENABLE", 2607 "CL72_IEEE_TRAINING_FAILURE", 2608 "CL72_IEEE_TRAINING_STATUS", 2609 "CL72_INC_DEC_VAL_SEL", 2610 "CL72_LD_COEFF_CMD_HIST", 2611 "CL72_LD_STATUS_PAGE", 2612 "CL72_LD_XMT_STATUS_LOAD", 2613 "CL72_LD_XMT_STATUS_OVERRIDE", 2614 "CL72_LP_CONTROL_PAGE", 2615 "CL72_OVERRIDE_LD_STATUS_PAGE", 2616 "CL72_PPM_OFFSET_EN", 2617 "CL72_RCVD_STATUS_PAGE", 2618 "CL72_READY_FOR_CMD", 2619 "CL72_RX_DP_LN_CLK_EN", 2620 "CL72_RX_TRAINED", 2621 "CL72_SIGNAL_DETECT", 2622 "CL72_SIGNAL_DET_FRC", 2623 "CL72_STRICT_DME_CHK", 2624 "CL72_STRICT_MARKER_CHK", 2625 "CL72_TAP_V2_VAL", 2626 "CL72_TIMER_EN", 2627 "CL72_TR_COARSE_LOCK", 2628 "CL72_TX_DP_LN_CLK_EN", 2629 "CL72_TX_FIR_TAP_MAIN_KR_INIT_VAL", 2630 "CL72_TX_FIR_TAP_POST_KR_INIT_VAL", 2631 "CL72_TX_FIR_TAP_PRE_KR_INIT_VAL", 2632 "CL72_V2_CONSTRAINT_DIS", 2633 "CL72_XMT_UPDATE_PAGE", 2634 "CNT_BIN_D_DREG", 2635 "CNT_BIN_D_MREG", 2636 "CNT_BIN_M1_MREG", 2637 "CNT_BIN_M1_PREG", 2638 "CNT_BIN_P1_DREG", 2639 "CNT_BIN_P1_PREG", 2640 "CNT_D_MINUS_M1", 2641 "CNT_D_MINUS_P1", 2642 "CORE_DP_RESET_STATE", 2643 "CORE_DP_S_RSTB", 2644 "CORE_MULTICAST_MASK_CONTROL", 2645 "CORE_REG_RESET_OCCURRED", 2646 "CORE_S_RSTB", 2647 "DBG_CAP_STATE_ONE_HOT", 2648 "DBG_FDBCK", 2649 "DBG_MASK_DIG_LPBK_EN", 2650 "DBG_PLL_STATE_ONE_HOT", 2651 "DBG_SLOWDN", 2652 "DBG_SLOWDN_CHANGE", 2653 "DC_OFFSET", 2654 "DFE_1_ACC_CLR", 2655 "DFE_1_CMN", 2656 "DFE_1_CMN_ONLY", 2657 "DFE_1_E", 2658 "DFE_1_EN", 2659 "DFE_1_ERR_GAIN", 2660 "DFE_1_ERR_SEL", 2661 "DFE_1_GRADIENT_INVERT", 2662 "DFE_1_INV_M1", 2663 "DFE_1_INV_P1", 2664 "DFE_1_O", 2665 "DFE_1_PATTERN", 2666 "DFE_1_PATTERN_BIT_EN", 2667 "DFE_1_WANTS_NEGATIVE", 2668 "DFE_2_ACC_CLR", 2669 "DFE_2_CMN", 2670 "DFE_2_CMN_ONLY", 2671 "DFE_2_E", 2672 "DFE_2_EN", 2673 "DFE_2_ERR_GAIN", 2674 "DFE_2_ERR_SEL", 2675 "DFE_2_GRADIENT_INVERT", 2676 "DFE_2_INV_M1", 2677 "DFE_2_INV_P1", 2678 "DFE_2_O", 2679 "DFE_2_PATTERN", 2680 "DFE_2_PATTERN_BIT_EN", 2681 "DFE_2_SE", 2682 "DFE_2_SO", 2683 "DFE_3_ACC_CLR", 2684 "DFE_3_CMN", 2685 "DFE_3_EN", 2686 "DFE_3_ERR_GAIN", 2687 "DFE_3_ERR_SEL", 2688 "DFE_3_GRADIENT_INVERT", 2689 "DFE_3_INV_M1", 2690 "DFE_3_INV_P1", 2691 "DFE_3_PATTERN", 2692 "DFE_3_PATTERN_BIT_EN", 2693 "DFE_4_ACC_CLR", 2694 "DFE_4_CMN", 2695 "DFE_4_EN", 2696 "DFE_4_ERR_GAIN", 2697 "DFE_4_ERR_SEL", 2698 "DFE_4_GRADIENT_INVERT", 2699 "DFE_4_INV_M1", 2700 "DFE_4_INV_P1", 2701 "DFE_4_PATTERN", 2702 "DFE_4_PATTERN_BIT_EN", 2703 "DFE_5_ACC_CLR", 2704 "DFE_5_CMN", 2705 "DFE_5_EN", 2706 "DFE_5_ERR_GAIN", 2707 "DFE_5_ERR_SEL", 2708 "DFE_5_GRADIENT_INVERT", 2709 "DFE_5_INV_M1", 2710 "DFE_5_INV_P1", 2711 "DFE_5_PATTERN", 2712 "DFE_5_PATTERN_BIT_EN", 2713 "DFE_ACC_HYS_EN", 2714 "DFE_ALLOW_SIMULT", 2715 "DFE_OFFSET_ADJ_DATA_EVEN", 2716 "DFE_OFFSET_ADJ_DATA_ODD", 2717 "DFE_OFFSET_ADJ_M1_EVEN", 2718 "DFE_OFFSET_ADJ_M1_ODD", 2719 "DFE_OFFSET_ADJ_P1_EVEN", 2720 "DFE_OFFSET_ADJ_P1_ODD", 2721 "DFE_UPDATE_GAIN", 2722 "DFE_VGA_WRITE_EN", 2723 "DFE_VGA_WRITE_TAPSEL", 2724 "DFE_VGA_WRITE_VAL", 2725 "DIG_LPBK_EN", 2726 "DIG_LPBK_PD_EARLY_IND", 2727 "DIG_LPBK_PD_FLT_BYPASS", 2728 "DIG_LPBK_PD_LATE_IND", 2729 "DIG_LPBK_PD_MODE", 2730 "DP_RESET_TX_DISABLE_DIS", 2731 "DSC_CLR_FRC", 2732 "DSC_CLR_FRC_VAL", 2733 "DSC_SM_GP_UC_REQ", 2734 "DSC_SM_READY_FOR_CMD", 2735 "DSC_SM_SCRATCH", 2736 "DSC_STATE", 2737 "DSC_STATE_EEE_ONE_HOT", 2738 "DSC_STATE_ONE_HOT", 2739 "EEE_ACQ_CDR_TIMEOUT", 2740 "EEE_ANA_PWR_TIMEOUT", 2741 "EEE_CDR_SETTLE_TIMEOUT", 2742 "EEE_HW_TUNE_TIMEOUT", 2743 "EEE_LFSR_CNT", 2744 "EEE_MEASURE_CNT", 2745 "EEE_MEASURE_EN", 2746 "EEE_MODE_EN", 2747 "EEE_PHASE_ERR_OFFSET", 2748 "EEE_PHASE_ERR_OFFSET_EN", 2749 "EEE_QUIET_FROM_EEE_STATES", 2750 "EEE_QUIET_RX_AFE_PWRDWN_VAL", 2751 "ENERGY_DETECT", 2752 "ENERGY_DETECT_CHANGE", 2753 "ENERGY_DETECT_FRC", 2754 "ENERGY_DETECT_FRC_VAL", 2755 "ENERGY_DETECT_MASK_COUNT", 2756 "EN_DFE_CLK", 2757 "EN_HGAIN", 2758 "EXT_LOS_EN", 2759 "EXT_LOS_INV", 2760 "FAST_SEARCH_MODE", 2761 "FREQ_DET_RESTART_EN", 2762 "FREQ_DET_RETRY_EN", 2763 "FREQ_DONE_SM", 2764 "FREQ_DONE_SM_LH_LL", 2765 "FREQ_MONITOR_EN", 2766 "FREQ_PASS_SM", 2767 "FREQ_PASS_SM_LH_LL", 2768 "FREQ_UPD_EN_FRC", 2769 "FREQ_UPD_EN_FRC_VAL", 2770 "HEARTBEAT_COUNT_1US", 2771 "HOLD_LOS_COUNT", 2772 "HOLD_SD_COUNT", 2773 "HW_TUNE_EN", 2774 "HW_TUNE_TIMEOUT", 2775 "IGNORE_LP_MODE", 2776 "IGNORE_RX_MODE", 2777 "LANE_ADDR_0", 2778 "LANE_ADDR_1", 2779 "LANE_ADDR_2", 2780 "LANE_ADDR_3", 2781 "LANE_DP_RESET_STATE", 2782 "LANE_MULTICAST_MASK_CONTROL", 2783 "LANE_REG_RESET_OCCURRED", 2784 "LANE_RESET_RELEASED", 2785 "LANE_RESET_RELEASED_INDEX", 2786 "LN_DP_S_RSTB", 2787 "LN_RX_DP_S_RSTB", 2788 "LN_RX_S_CLKGATE_FRC_ON", 2789 "LN_RX_S_COMCLK_FRC_ON", 2790 "LN_RX_S_COMCLK_SEL", 2791 "LN_RX_S_PWRDN", 2792 "LN_RX_S_RSTB", 2793 "LN_S_RSTB", 2794 "LN_TX_DP_S_RSTB", 2795 "LN_TX_S_PWRDN", 2796 "LN_TX_S_RSTB", 2797 "LOST_PLL_LOCK_SM", 2798 "LOS_FILTER_COUNT", 2799 "LOS_THRESH", 2800 "M1_THRESH_SEL", 2801 "M1_THRESH_ZERO", 2802 "MAIN_TAP_LIMIT", 2803 "MAIN_TAP_MIN_VAL", 2804 "MAX_WAIT_TIMER_PERIOD", 2805 "MDIO_ADDR_DATA", 2806 "MDIO_AER", 2807 "MDIO_BLK_ADDR", 2808 "MDIO_BRCST_PORT_ADDR", 2809 "MDIO_DEVAD", 2810 "MDIO_DEV_AN_EN", 2811 "MDIO_DEV_CL22_EN", 2812 "MDIO_DEV_DTE_EN", 2813 "MDIO_DEV_PCS_EN", 2814 "MDIO_DEV_PHY_EN", 2815 "MDIO_DEV_PMD_EN", 2816 "MDIO_FUNCTION", 2817 "MDIO_MASKDATA", 2818 "MDIO_MULTI_MMDS_EN", 2819 "MDIO_MULTI_PRTS_EN", 2820 "MEASURE_LFSR_CNT", 2821 "MEASURE_TIMEOUT", 2822 "MEAS_INCOMPLETE", 2823 "MICRO_BYTE_MODE", 2824 "MICRO_DATARAM_TM", 2825 "MICRO_DISABLE_ECC", 2826 "MICRO_ERR0", 2827 "MICRO_ERR1", 2828 "MICRO_FSM", 2829 "MICRO_GEN_STATUS_SEL", 2830 "MICRO_INIT_CMD", 2831 "MICRO_INIT_DONE", 2832 "MICRO_INRUSH_CURRENT_FRC", 2833 "MICRO_INRUSH_CURRENT_FRC_VAL", 2834 "MICRO_IRAM_TM", 2835 "MICRO_MDIO_AUTOWAKEUP", 2836 "MICRO_MDIO_DW8051_RESET_N", 2837 "MICRO_MDIO_PROG_RAM_CS_FRC", 2838 "MICRO_MDIO_PROG_RAM_CS_FRC_VAL", 2839 "MICRO_MDIO_RAM_ACCESS_MODE", 2840 "MICRO_MDIO_RAM_READ_AUTOINC_EN", 2841 "MICRO_MDIO_UC_MAILBOX_LSW", 2842 "MICRO_MDIO_UC_MAILBOX_MSW", 2843 "MICRO_PMI_ACK_TIMEOUT_VAL", 2844 "MICRO_PMI_HP_ACK_FRC", 2845 "MICRO_PMI_HP_ACK_FRC_VAL", 2846 "MICRO_PRAM_IF_EN", 2847 "MICRO_PRAM_IF_FLOP_BYPASS", 2848 "MICRO_PRAM_IF_RSTB", 2849 "MICRO_PROGRAM_RAM_TM", 2850 "MICRO_RAM_ADDRESS", 2851 "MICRO_RAM_CLK_INVERT", 2852 "MICRO_RAM_COUNT", 2853 "MICRO_RAM_RDDATA", 2854 "MICRO_RAM_WRDATA", 2855 "MICRO_READ", 2856 "MICRO_RUN", 2857 "MICRO_SRST_DW8051_TO_PMI", 2858 "MICRO_SRST_MDIO_DATARAM_ACCESS", 2859 "MICRO_SRST_MDIO_LOAD_PROGRAM_RAM", 2860 "MICRO_SRST_MDIO_PROGRAM_ACCESS", 2861 "MICRO_STATUS_MUXED", 2862 "MICRO_STOP", 2863 "MICRO_SYSTEM_CLK_EN", 2864 "MICRO_SYSTEM_RESET_N", 2865 "MICRO_TEMPATURE_DATA", 2866 "MICRO_TX_DISABLE", 2867 "MICRO_UC_MDIO_MAILBOX_LSW", 2868 "MICRO_UC_MDIO_MAILBOX_MSW", 2869 "MICRO_WRITE", 2870 "MICRO_ZERO_ROM_DATAOUT", 2871 "OFFSET_FASTACQ", 2872 "OFFSET_PD", 2873 "OSR_MODE", 2874 "OSR_MODE_FRC", 2875 "OSR_MODE_FRC_VAL", 2876 "OSR_MODE_PIN", 2877 "OSX2P_PHERR_GAIN", 2878 "P1_EYEDIAG_BIN", 2879 "P1_EYEDIAG_EN", 2880 "P1_OFFSET", 2881 "P1_OFFSET_EN", 2882 "P1_OFF_3LEVELQ_EN", 2883 "P1_THRESH_SEL", 2884 "PATTERN_SEL", 2885 "PATT_GEN_EN", 2886 "PATT_GEN_SEQ_0", 2887 "PATT_GEN_SEQ_1", 2888 "PATT_GEN_SEQ_10", 2889 "PATT_GEN_SEQ_11", 2890 "PATT_GEN_SEQ_12", 2891 "PATT_GEN_SEQ_13", 2892 "PATT_GEN_SEQ_14", 2893 "PATT_GEN_SEQ_2", 2894 "PATT_GEN_SEQ_3", 2895 "PATT_GEN_SEQ_4", 2896 "PATT_GEN_SEQ_5", 2897 "PATT_GEN_SEQ_6", 2898 "PATT_GEN_SEQ_7", 2899 "PATT_GEN_SEQ_8", 2900 "PATT_GEN_SEQ_9", 2901 "PATT_GEN_START_POS", 2902 "PATT_GEN_STOP_POS", 2903 "PD_CH_P1", 2904 "PF2_LOWP_CTRL", 2905 "PF_CTRL", 2906 "PF_HIZ", 2907 "PHASE_ERR_OFFSET", 2908 "PHASE_ERR_OFFSET_EN", 2909 "PHASE_ERR_OFFSET_MULT_2", 2910 "PLL_FORCE_CAP_DONE", 2911 "PLL_FORCE_CAP_DONE_EN", 2912 "PLL_FORCE_CAP_PASS", 2913 "PLL_FORCE_CAP_PASS_EN", 2914 "PLL_FORCE_FDONE", 2915 "PLL_FORCE_FDONE_EN", 2916 "PLL_FORCE_FPASS", 2917 "PLL_LOCK", 2918 "PLL_LOCK_FRC", 2919 "PLL_LOCK_FRC_VAL", 2920 "PLL_LOCK_LH_LL", 2921 "PLL_MODE", 2922 "PLL_SEQ_DONE", 2923 "PLL_SEQ_DONE_LH_LL", 2924 "PLL_SEQ_PASS", 2925 "PLL_SEQ_PASS_LH_LL", 2926 "PLL_SEQ_START", 2927 "PMD_CORE_DP_H_RSTB_PKILL", 2928 "PMD_CORE_MODE", 2929 "PMD_LANE_MODE", 2930 "PMD_LN_DP_H_RSTB_PKILL", 2931 "PMD_LN_H_RSTB_PKILL", 2932 "PMD_LN_RX_H_PWRDN_PKILL", 2933 "PMD_LN_TX_H_PWRDN_PKILL", 2934 "PMD_MDIO_TRANS_PKILL", 2935 "PMD_RX_CLK_VLD_FRC", 2936 "PMD_RX_CLK_VLD_FRC_VAL", 2937 "PMD_RX_LOCK", 2938 "PMD_RX_LOCK_CHANGE", 2939 "PMD_TX_CLK_VLD_FRC", 2940 "PMD_TX_CLK_VLD_FRC_VAL", 2941 "PMD_TX_DISABLE_PIN_DIS", 2942 "POST_TAP_LIMIT", 2943 "POST_TAP_PRESET_VAL", 2944 "PRBS_CHK_CLK_EN_FRC_ON", 2945 "PRBS_CHK_EN", 2946 "PRBS_CHK_EN_AUTO_MODE", 2947 "PRBS_CHK_EN_TIMEOUT", 2948 "PRBS_CHK_EN_TIMER_MODE", 2949 "PRBS_CHK_ERR_CNT_BURST_MODE", 2950 "PRBS_CHK_ERR_CNT_LSB", 2951 "PRBS_CHK_ERR_CNT_MSB", 2952 "PRBS_CHK_INV", 2953 "PRBS_CHK_LOCK", 2954 "PRBS_CHK_LOCK_CNT", 2955 "PRBS_CHK_LOCK_LOST_LH", 2956 "PRBS_CHK_MODE", 2957 "PRBS_CHK_MODE_SEL", 2958 "PRBS_CHK_OOL_CNT", 2959 "PRBS_GEN_EN", 2960 "PRBS_GEN_ERR_INS", 2961 "PRBS_GEN_INV", 2962 "PRBS_GEN_MODE_SEL", 2963 "PRE_FREQ_DET_TIME", 2964 "PRE_TAP_LIMIT", 2965 "PRE_TAP_PRESET_VAL", 2966 "PWRDN_SEQ_TIMER", 2967 "REFCLK_DIVCNT", 2968 "REFCLK_DIVCNT_SEL", 2969 "RESCAL_FRC", 2970 "RESCAL_FRC_VAL", 2971 "RESCAL_IN", 2972 "RESTART_PI_EXT_MODE", 2973 "RESTART_PMD_RESTART", 2974 "RESTART_SIGDET", 2975 "RES_CAL_CNTR", 2976 "RETRY_TIME", 2977 "REVID2", 2978 "REVID_BONDING", 2979 "REVID_CL72", 2980 "REVID_EEE", 2981 "REVID_LLP", 2982 "REVID_MDIO", 2983 "REVID_MICRO", 2984 "REVID_MODEL", 2985 "REVID_MULTIPLICITY", 2986 "REVID_PIR", 2987 "REVID_PROCESS", 2988 "REVID_REV_LETTER", 2989 "REVID_REV_NUMBER", 2990 "RMT_LPBK_EN", 2991 "RMT_LPBK_PD_EARLY_IND", 2992 "RMT_LPBK_PD_FRC_ON", 2993 "RMT_LPBK_PD_LATE_IND", 2994 "RMT_LPBK_PD_MODE", 2995 "RST_SEQ_DIS_FLT_MODE", 2996 "RST_SEQ_TIMER", 2997 "RX_AGGREGATOR_BYPASS_EN", 2998 "RX_DSC_LOCK", 2999 "RX_DSC_LOCK_FRC", 3000 "RX_DSC_LOCK_FRC_VAL", 3001 "RX_PI_MANUAL_MODE", 3002 "RX_PI_MANUAL_RESET", 3003 "RX_PI_MANUAL_STROBE", 3004 "RX_PI_PHASE_STEP_CNT", 3005 "RX_PI_PHASE_STEP_DIR", 3006 "RX_PI_SLICERS_EN", 3007 "RX_PMD_DP_INVERT", 3008 "RX_RESTART_PMD", 3009 "RX_RESTART_PMD_HOLD", 3010 "SDK_TX_DISABLE", 3011 "SEND_LMS_TO_PCS", 3012 "SET_MEAS_INCOMPLETE", 3013 "SIGDET_DP_RSTB_EN", 3014 "SIGNAL_DETECT", 3015 "SIGNAL_DETECT_CHANGE", 3016 "SIGNAL_DETECT_FILTER_1US", 3017 "SIGNAL_DETECT_FILTER_COUNT", 3018 "SIGNAL_DETECT_FRC", 3019 "SIGNAL_DETECT_FRC_VAL", 3020 "SIGNAL_DETECT_RAW", 3021 "SIGNAL_DETECT_RAW_CHANGE", 3022 "SIGNAL_DETECT_THRESH", 3023 "SLOWDN_XOR", 3024 "SUP_RST_SEQ_FRC", 3025 "SUP_RST_SEQ_FRC_VAL", 3026 "TAP_SUM_MAX_VAL", 3027 "TDR_BIT_SEL", 3028 "TDR_CYCLE_BIN", 3029 "TDR_CYCLE_SEL", 3030 "TDR_TRNSUM_EN", 3031 "TIMER_DONE_FRC", 3032 "TIMER_DONE_FRC_VAL", 3033 "TRNSUM_CLR_FRC", 3034 "TRNSUM_CLR_FRC_VAL", 3035 "TRNSUM_EN", 3036 "TRNSUM_ERROR_COUNT_EN", 3037 "TRNSUM_ERR_SEL", 3038 "TRNSUM_EYE_CLOSURE_EN", 3039 "TRNSUM_E_HIGH", 3040 "TRNSUM_E_LOW", 3041 "TRNSUM_FRZ_FRC", 3042 "TRNSUM_FRZ_FRC_VAL", 3043 "TRNSUM_GAIN", 3044 "TRNSUM_HIGH", 3045 "TRNSUM_INV_PATTERN_EN", 3046 "TRNSUM_LOW", 3047 "TRNSUM_O_HIGH", 3048 "TRNSUM_O_LOW", 3049 "TRNSUM_PATTERN", 3050 "TRNSUM_PATTERN_BIT_EN", 3051 "TRNSUM_PATTERN_FULL_CHECK_OFF", 3052 "TRNSUM_RANDOM_TAPSEL_DISABLE", 3053 "TRNSUM_TAP_EN", 3054 "TRNSUM_TAP_RANGE_SEL", 3055 "TRNSUM_TAP_SIGN", 3056 "TRNSUM_UNSIGNED_CORR", 3057 "TRNSUM_UNSIGNED_FLIP", 3058 "TXFIR_MAIN_ADJUSTED", 3059 "TXFIR_MAIN_AFTER_OVR", 3060 "TXFIR_MAIN_OFFSET", 3061 "TXFIR_MAIN_OVERRIDE", 3062 "TXFIR_OVERRIDE_EN", 3063 "TXFIR_POST2", 3064 "TXFIR_POST2_ADJUSTED", 3065 "TXFIR_POST2_OFFSET", 3066 "TXFIR_POST3", 3067 "TXFIR_POST3_ADJUSTED", 3068 "TXFIR_POST3_OFFSET", 3069 "TXFIR_POST_ADJUSTED", 3070 "TXFIR_POST_AFTER_OVR", 3071 "TXFIR_POST_OFFSET", 3072 "TXFIR_POST_OVERRIDE", 3073 "TXFIR_PRE_ADJUSTED", 3074 "TXFIR_PRE_AFTER_OVR", 3075 "TXFIR_PRE_OFFSET", 3076 "TXFIR_PRE_OVERRIDE", 3077 "TX_DISABLE_OUTPUT_SEL", 3078 "TX_DISABLE_TIMER_CTRL", 3079 "TX_EEE_ALERT_EN", 3080 "TX_EEE_QUIET_EN", 3081 "TX_LANE_MAP_0", 3082 "TX_LANE_MAP_1", 3083 "TX_LANE_MAP_2", 3084 "TX_LANE_MAP_3", 3085 "TX_MUX_SEL_ORDER", 3086 "TX_PCS_NATIVE_ANA_FRMT_EN", 3087 "TX_PI_EN", 3088 "TX_PI_EXT_CTRL_EN", 3089 "TX_PI_EXT_PHASE_BWSEL_INTEG", 3090 "TX_PI_FIRST_ORDER_BWSEL_INTEG", 3091 "TX_PI_FRC_PHASE_STEP_MUX_SEL", 3092 "TX_PI_FREQ_OVERRIDE_EN", 3093 "TX_PI_FREQ_OVERRIDE_VAL", 3094 "TX_PI_FRZ_FRC", 3095 "TX_PI_FRZ_FRC_VAL", 3096 "TX_PI_FRZ_MODE", 3097 "TX_PI_INTEG1_REG", 3098 "TX_PI_INTEG2_REG", 3099 "TX_PI_JITTER_FILTER_EN", 3100 "TX_PI_JIT_AMP", 3101 "TX_PI_JIT_FREQ_IDX", 3102 "TX_PI_JIT_SSC_FREQ_MODE", 3103 "TX_PI_LANE_SEL_FRC", 3104 "TX_PI_LANE_SEL_FRC_VAL", 3105 "TX_PI_LOOP_FILTER_STABLE", 3106 "TX_PI_LOOP_TIMING_SRC_SEL", 3107 "TX_PI_PHASE_CNTR", 3108 "TX_PI_PHASE_ERR", 3109 "TX_PI_PHASE_INVERT", 3110 "TX_PI_PHASE_OVERRIDE", 3111 "TX_PI_PHASE_STEP_DIR", 3112 "TX_PI_PHASE_STEP_NUM", 3113 "TX_PI_PHASE_STROBE", 3114 "TX_PI_RESET_CODE_DBG", 3115 "TX_PI_RMT_LPBK_BYPASS_FLT", 3116 "TX_PI_SECOND_ORDER_BWSEL_INTEG", 3117 "TX_PI_SECOND_ORDER_LOOP_EN", 3118 "TX_PI_SJ_GEN_EN", 3119 "TX_PI_SSC_GEN_EN", 3120 "TX_PMD_DP_INVERT", 3121 "TX_S_CLKGATE_FRC_ON", 3122 "TX_S_COMCLK_FRC_ON", 3123 "TX_S_COMCLK_SEL", 3124 "UC_ACK_CORE_CFG_DONE", 3125 "UC_ACK_CORE_DP_RESET", 3126 "UC_ACK_DSC_CONFIG", 3127 "UC_ACK_DSC_EEE_DONE", 3128 "UC_ACK_DSC_RESET", 3129 "UC_ACK_DSC_RESTART", 3130 "UC_ACK_LANE_CFG_DONE", 3131 "UC_ACK_LANE_DP_RESET", 3132 "UC_ACTIVE", 3133 "UC_DSC_ERROR_FOUND", 3134 "UC_DSC_GP_UC_REQ", 3135 "UC_DSC_READY_FOR_CMD", 3136 "UC_DSC_SCRATCH", 3137 "UC_DSC_SUPP_INFO", 3138 "UC_TRNSUM_EN", 3139 "UC_TUNE_EN", 3140 "VCO_DONE_EN", 3141 "VCO_RST_EN", 3142 "VCO_START_TIME", 3143 "VCO_STEP_TIME", 3144 "VGA3_CTRL_BIN", 3145 "VGA_ACC_HYS_EN", 3146 "VGA_BIN", 3147 "VGA_CTRL_BIN", 3148 "VGA_EN", 3149 "VGA_ERR_GAIN", 3150 "VGA_ERR_SEL", 3151 "VGA_INV_M1", 3152 "VGA_INV_P1", 3153 "VGA_P1_ACC_CLR", 3154 "VGA_P1_GRADIENT_INVERT", 3155 "VGA_PATTERN", 3156 "VGA_PATTERN_BIT_EN", 3157 "VGA_TABLEMAP_DISABLE", 3158 "VGA_UPDATE_GAIN", 3159 "WAIT_CNTR_LIMIT", 3160 "WIN_CAL_CNTR", 3161 }; 3162 3163 #endif 3164 #endif 3165 #endif 3166 #endif /* PHYMOD_CONFIG_INCLUDE_FIELD_INFO */ 3167 3168 3169 3170 /******************************************************************************* 3171 * 3172 * The following is the symbol table itself. 3173 * It defines the entries for all registers and memories. 3174 * It also incorporates the field information for each register and memory if 3175 * applicable. 3176 */ 3177 static const phymod_symbol_t bcmi_eagle_xgxs_syms[] = { 3178 #ifndef PHYMOD_CONFIG_EXCLUDE_CHIP_SYMBOLS_BCMI_EAGLE_XGXS 3179 { 3180 BCMI_EAGLE_XGXS_ACC_CTLr, 3181 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3182 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 3183 BCMI_EAGLE_XGXS_ACC_CTLr_fields, 3184 #else 3185 0, 3186 #endif 3187 #endif 3188 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3189 PHYMOD_SYMBOL_FLAG_REGISTER, 3190 "ACC_CTLr", 3191 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3192 "MDIO_CL22_IEEE_COM_ACC_CTRL", 3193 NULL, 3194 #endif 3195 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3196 0x0, /* 0 */ 3197 0, 3198 #endif 3199 }, 3200 { 3201 BCMI_EAGLE_XGXS_ACC_ADDR_DATAr, 3202 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3203 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 3204 BCMI_EAGLE_XGXS_ACC_ADDR_DATAr_fields, 3205 #else 3206 0, 3207 #endif 3208 #endif 3209 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3210 PHYMOD_SYMBOL_FLAG_REGISTER, 3211 "ACC_ADDR_DATAr", 3212 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3213 "MDIO_CL22_IEEE_COM_ACC_ADDR_DATA", 3214 NULL, 3215 #endif 3216 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3217 0x0, /* 0 */ 3218 0, 3219 #endif 3220 }, 3221 { 3222 BCMI_EAGLE_XGXS_CL72_TXBASE_R_PMD_CTLr, 3223 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3224 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 3225 BCMI_EAGLE_XGXS_CL72_TXBASE_R_PMD_CTLr_fields, 3226 #else 3227 0, 3228 #endif 3229 #endif 3230 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3231 PHYMOD_SYMBOL_FLAG_REGISTER, 3232 "CL72_TXBASE_R_PMD_CTLr", 3233 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3234 "CL72_IEEE_TX_BASE_R_PMD_CONTROL_REGISTER_150", 3235 NULL, 3236 #endif 3237 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3238 0x0, /* 0 */ 3239 0, 3240 #endif 3241 }, 3242 { 3243 BCMI_EAGLE_XGXS_CL72_TXBASE_R_PMD_STSr, 3244 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3245 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 3246 BCMI_EAGLE_XGXS_CL72_TXBASE_R_PMD_STSr_fields, 3247 #else 3248 0, 3249 #endif 3250 #endif 3251 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3252 PHYMOD_SYMBOL_FLAG_REGISTER, 3253 "CL72_TXBASE_R_PMD_STSr", 3254 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3255 "CL72_IEEE_TX_BASE_R_PMD_STATUS_REGISTER_151", 3256 NULL, 3257 #endif 3258 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3259 0x0, /* 0 */ 3260 0, 3261 #endif 3262 }, 3263 { 3264 BCMI_EAGLE_XGXS_CL72_TXBASE_R_LP_COEFF_UPDr, 3265 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3266 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 3267 BCMI_EAGLE_XGXS_CL72_TXBASE_R_LP_COEFF_UPDr_fields, 3268 #else 3269 0, 3270 #endif 3271 #endif 3272 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3273 PHYMOD_SYMBOL_FLAG_REGISTER, 3274 "CL72_TXBASE_R_LP_COEFF_UPDr", 3275 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3276 "CL72_IEEE_TX_BASE_R_LP_COEFF_UPDATE_REGISTER_152", 3277 NULL, 3278 #endif 3279 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3280 0x0, /* 0 */ 3281 0, 3282 #endif 3283 }, 3284 { 3285 BCMI_EAGLE_XGXS_CL72_RXBASE_R_LD_STS_REPr, 3286 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3287 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 3288 BCMI_EAGLE_XGXS_CL72_RXBASE_R_LD_STS_REPr_fields, 3289 #else 3290 0, 3291 #endif 3292 #endif 3293 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3294 PHYMOD_SYMBOL_FLAG_REGISTER, 3295 "CL72_RXBASE_R_LD_STS_REPr", 3296 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3297 "CL72_IEEE_RX_BASE_R_LD_STATUS_REPORT_REGISTER_153", 3298 NULL, 3299 #endif 3300 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3301 0x0, /* 0 */ 3302 0, 3303 #endif 3304 }, 3305 { 3306 BCMI_EAGLE_XGXS_CL72_TXBASE_R_LD_COEFF_UPDr, 3307 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3308 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 3309 BCMI_EAGLE_XGXS_CL72_TXBASE_R_LD_COEFF_UPDr_fields, 3310 #else 3311 0, 3312 #endif 3313 #endif 3314 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3315 PHYMOD_SYMBOL_FLAG_REGISTER, 3316 "CL72_TXBASE_R_LD_COEFF_UPDr", 3317 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3318 "CL72_IEEE_TX_BASE_R_LD_COEFF_UPDATE_REGISTER_154", 3319 NULL, 3320 #endif 3321 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3322 0x0, /* 0 */ 3323 0, 3324 #endif 3325 }, 3326 { 3327 BCMI_EAGLE_XGXS_CL72_TXBASE_R_LD_STS_REPr, 3328 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3329 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 3330 BCMI_EAGLE_XGXS_CL72_TXBASE_R_LD_STS_REPr_fields, 3331 #else 3332 0, 3333 #endif 3334 #endif 3335 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3336 PHYMOD_SYMBOL_FLAG_REGISTER, 3337 "CL72_TXBASE_R_LD_STS_REPr", 3338 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3339 "CL72_IEEE_TX_BASE_R_LD_STATUS_REPORT_REGISTER_155", 3340 NULL, 3341 #endif 3342 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3343 0x0, /* 0 */ 3344 0, 3345 #endif 3346 }, 3347 { 3348 BCMI_EAGLE_XGXS_DSC_CDR_CTL0r, 3349 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3350 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 3351 BCMI_EAGLE_XGXS_DSC_CDR_CTL0r_fields, 3352 #else 3353 0, 3354 #endif 3355 #endif 3356 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3357 PHYMOD_SYMBOL_FLAG_REGISTER, 3358 "DSC_CDR_CTL0r", 3359 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3360 "DSC_A_CDR_CONTROL_0", 3361 NULL, 3362 #endif 3363 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3364 0x4, /* 4 */ 3365 0, 3366 #endif 3367 }, 3368 { 3369 BCMI_EAGLE_XGXS_DSC_CDR_CTL1r, 3370 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3371 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 3372 BCMI_EAGLE_XGXS_DSC_CDR_CTL1r_fields, 3373 #else 3374 0, 3375 #endif 3376 #endif 3377 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3378 PHYMOD_SYMBOL_FLAG_REGISTER, 3379 "DSC_CDR_CTL1r", 3380 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3381 "DSC_A_CDR_CONTROL_1", 3382 NULL, 3383 #endif 3384 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3385 0x690, /* 1680 */ 3386 0, 3387 #endif 3388 }, 3389 { 3390 BCMI_EAGLE_XGXS_DSC_CDR_CTL2r, 3391 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3392 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 3393 BCMI_EAGLE_XGXS_DSC_CDR_CTL2r_fields, 3394 #else 3395 0, 3396 #endif 3397 #endif 3398 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3399 PHYMOD_SYMBOL_FLAG_REGISTER, 3400 "DSC_CDR_CTL2r", 3401 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3402 "DSC_A_CDR_CONTROL_2", 3403 NULL, 3404 #endif 3405 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3406 0xf0, /* 240 */ 3407 0, 3408 #endif 3409 }, 3410 { 3411 BCMI_EAGLE_XGXS_DSC_RX_PI_CTLr, 3412 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3413 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 3414 BCMI_EAGLE_XGXS_DSC_RX_PI_CTLr_fields, 3415 #else 3416 0, 3417 #endif 3418 #endif 3419 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3420 PHYMOD_SYMBOL_FLAG_REGISTER, 3421 "DSC_RX_PI_CTLr", 3422 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3423 "DSC_A_RX_PI_CONTROL", 3424 NULL, 3425 #endif 3426 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3427 0x0, /* 0 */ 3428 0, 3429 #endif 3430 }, 3431 { 3432 BCMI_EAGLE_XGXS_DSC_CDR_STS_INTEGr, 3433 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3434 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 3435 BCMI_EAGLE_XGXS_DSC_CDR_STS_INTEGr_fields, 3436 #else 3437 0, 3438 #endif 3439 #endif 3440 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3441 PHYMOD_SYMBOL_FLAG_REGISTER, 3442 "DSC_CDR_STS_INTEGr", 3443 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3444 "DSC_A_CDR_STATUS_INTEG_REG", 3445 NULL, 3446 #endif 3447 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3448 0x0, /* 0 */ 3449 0, 3450 #endif 3451 }, 3452 { 3453 BCMI_EAGLE_XGXS_DSC_CDR_STS_PHASE_ERRr, 3454 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3455 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 3456 BCMI_EAGLE_XGXS_DSC_CDR_STS_PHASE_ERRr_fields, 3457 #else 3458 0, 3459 #endif 3460 #endif 3461 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3462 PHYMOD_SYMBOL_FLAG_REGISTER, 3463 "DSC_CDR_STS_PHASE_ERRr", 3464 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3465 "DSC_A_CDR_STATUS_PHASE_ERROR", 3466 NULL, 3467 #endif 3468 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3469 0x100, /* 256 */ 3470 0, 3471 #endif 3472 }, 3473 { 3474 BCMI_EAGLE_XGXS_DSC_RX_PI_CNT_BIN_Dr, 3475 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3476 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 3477 BCMI_EAGLE_XGXS_DSC_RX_PI_CNT_BIN_Dr_fields, 3478 #else 3479 0, 3480 #endif 3481 #endif 3482 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3483 PHYMOD_SYMBOL_FLAG_REGISTER, 3484 "DSC_RX_PI_CNT_BIN_Dr", 3485 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3486 "DSC_A_RX_PI_CNT_BIN_D", 3487 NULL, 3488 #endif 3489 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3490 0x0, /* 0 */ 3491 0, 3492 #endif 3493 }, 3494 { 3495 BCMI_EAGLE_XGXS_DSC_RX_PI_CNT_BIN_Pr, 3496 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3497 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 3498 BCMI_EAGLE_XGXS_DSC_RX_PI_CNT_BIN_Pr_fields, 3499 #else 3500 0, 3501 #endif 3502 #endif 3503 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3504 PHYMOD_SYMBOL_FLAG_REGISTER, 3505 "DSC_RX_PI_CNT_BIN_Pr", 3506 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3507 "DSC_A_RX_PI_CNT_BIN_P", 3508 NULL, 3509 #endif 3510 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3511 0x2000, /* 8192 */ 3512 0, 3513 #endif 3514 }, 3515 { 3516 BCMI_EAGLE_XGXS_DSC_RX_PI_CNT_BIN_Mr, 3517 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3518 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 3519 BCMI_EAGLE_XGXS_DSC_RX_PI_CNT_BIN_Mr_fields, 3520 #else 3521 0, 3522 #endif 3523 #endif 3524 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3525 PHYMOD_SYMBOL_FLAG_REGISTER, 3526 "DSC_RX_PI_CNT_BIN_Mr", 3527 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3528 "DSC_A_RX_PI_CNT_BIN_M", 3529 NULL, 3530 #endif 3531 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3532 0x20, /* 32 */ 3533 0, 3534 #endif 3535 }, 3536 { 3537 BCMI_EAGLE_XGXS_DSC_RX_PI_DIFF_BINr, 3538 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3539 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 3540 BCMI_EAGLE_XGXS_DSC_RX_PI_DIFF_BINr_fields, 3541 #else 3542 0, 3543 #endif 3544 #endif 3545 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3546 PHYMOD_SYMBOL_FLAG_REGISTER, 3547 "DSC_RX_PI_DIFF_BINr", 3548 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3549 "DSC_A_RX_PI_DIFF_BIN", 3550 NULL, 3551 #endif 3552 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3553 0x0, /* 0 */ 3554 0, 3555 #endif 3556 }, 3557 { 3558 BCMI_EAGLE_XGXS_DSC_TRNSUM_CTL5r, 3559 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3560 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 3561 BCMI_EAGLE_XGXS_DSC_TRNSUM_CTL5r_fields, 3562 #else 3563 0, 3564 #endif 3565 #endif 3566 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3567 PHYMOD_SYMBOL_FLAG_REGISTER, 3568 "DSC_TRNSUM_CTL5r", 3569 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3570 "DSC_A_TRNSUM_CNTL_5", 3571 NULL, 3572 #endif 3573 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3574 0x0, /* 0 */ 3575 0, 3576 #endif 3577 }, 3578 { 3579 BCMI_EAGLE_XGXS_DSC_UC_CTLr, 3580 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3581 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 3582 BCMI_EAGLE_XGXS_DSC_UC_CTLr_fields, 3583 #else 3584 0, 3585 #endif 3586 #endif 3587 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3588 PHYMOD_SYMBOL_FLAG_REGISTER, 3589 "DSC_UC_CTLr", 3590 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3591 "DSC_A_DSC_UC_CTRL", 3592 NULL, 3593 #endif 3594 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3595 0x0, /* 0 */ 3596 0, 3597 #endif 3598 }, 3599 { 3600 BCMI_EAGLE_XGXS_DSC_SCRATCHr, 3601 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3602 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 3603 BCMI_EAGLE_XGXS_DSC_SCRATCHr_fields, 3604 #else 3605 0, 3606 #endif 3607 #endif 3608 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3609 PHYMOD_SYMBOL_FLAG_REGISTER, 3610 "DSC_SCRATCHr", 3611 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3612 "DSC_A_DSC_SCRATCH", 3613 NULL, 3614 #endif 3615 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3616 0x0, /* 0 */ 3617 0, 3618 #endif 3619 }, 3620 { 3621 BCMI_EAGLE_XGXS_DSC_SM_CTL0r, 3622 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3623 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 3624 BCMI_EAGLE_XGXS_DSC_SM_CTL0r_fields, 3625 #else 3626 0, 3627 #endif 3628 #endif 3629 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3630 PHYMOD_SYMBOL_FLAG_REGISTER, 3631 "DSC_SM_CTL0r", 3632 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3633 "DSC_B_DSC_SM_CTRL_0", 3634 NULL, 3635 #endif 3636 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3637 0x8, /* 8 */ 3638 0, 3639 #endif 3640 }, 3641 { 3642 BCMI_EAGLE_XGXS_DSC_SM_CTL1r, 3643 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3644 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 3645 BCMI_EAGLE_XGXS_DSC_SM_CTL1r_fields, 3646 #else 3647 0, 3648 #endif 3649 #endif 3650 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3651 PHYMOD_SYMBOL_FLAG_REGISTER, 3652 "DSC_SM_CTL1r", 3653 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3654 "DSC_B_DSC_SM_CTRL_1", 3655 NULL, 3656 #endif 3657 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3658 0x200, /* 512 */ 3659 0, 3660 #endif 3661 }, 3662 { 3663 BCMI_EAGLE_XGXS_DSC_SM_CTL2r, 3664 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3665 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 3666 BCMI_EAGLE_XGXS_DSC_SM_CTL2r_fields, 3667 #else 3668 0, 3669 #endif 3670 #endif 3671 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3672 PHYMOD_SYMBOL_FLAG_REGISTER, 3673 "DSC_SM_CTL2r", 3674 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3675 "DSC_B_DSC_SM_CTRL_2", 3676 NULL, 3677 #endif 3678 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3679 0x87, /* 135 */ 3680 0, 3681 #endif 3682 }, 3683 { 3684 BCMI_EAGLE_XGXS_DSC_SM_CTL3r, 3685 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3686 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 3687 BCMI_EAGLE_XGXS_DSC_SM_CTL3r_fields, 3688 #else 3689 0, 3690 #endif 3691 #endif 3692 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3693 PHYMOD_SYMBOL_FLAG_REGISTER, 3694 "DSC_SM_CTL3r", 3695 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3696 "DSC_B_DSC_SM_CTRL_3", 3697 NULL, 3698 #endif 3699 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3700 0x1c1e, /* 7198 */ 3701 0, 3702 #endif 3703 }, 3704 { 3705 BCMI_EAGLE_XGXS_DSC_SM_CTL4r, 3706 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3707 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 3708 BCMI_EAGLE_XGXS_DSC_SM_CTL4r_fields, 3709 #else 3710 0, 3711 #endif 3712 #endif 3713 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3714 PHYMOD_SYMBOL_FLAG_REGISTER, 3715 "DSC_SM_CTL4r", 3716 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3717 "DSC_B_DSC_SM_CTRL_4", 3718 NULL, 3719 #endif 3720 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3721 0x35ad, /* 13741 */ 3722 0, 3723 #endif 3724 }, 3725 { 3726 BCMI_EAGLE_XGXS_DSC_SM_CTL5r, 3727 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3728 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 3729 BCMI_EAGLE_XGXS_DSC_SM_CTL5r_fields, 3730 #else 3731 0, 3732 #endif 3733 #endif 3734 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3735 PHYMOD_SYMBOL_FLAG_REGISTER, 3736 "DSC_SM_CTL5r", 3737 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3738 "DSC_B_DSC_SM_CTRL_5", 3739 NULL, 3740 #endif 3741 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3742 0x35ad, /* 13741 */ 3743 0, 3744 #endif 3745 }, 3746 { 3747 BCMI_EAGLE_XGXS_DSC_SM_CTL6r, 3748 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3749 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 3750 BCMI_EAGLE_XGXS_DSC_SM_CTL6r_fields, 3751 #else 3752 0, 3753 #endif 3754 #endif 3755 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3756 PHYMOD_SYMBOL_FLAG_REGISTER, 3757 "DSC_SM_CTL6r", 3758 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3759 "DSC_B_DSC_SM_CTRL_6", 3760 NULL, 3761 #endif 3762 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3763 0x340d, /* 13325 */ 3764 0, 3765 #endif 3766 }, 3767 { 3768 BCMI_EAGLE_XGXS_DSC_SM_CTL7r, 3769 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3770 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 3771 BCMI_EAGLE_XGXS_DSC_SM_CTL7r_fields, 3772 #else 3773 0, 3774 #endif 3775 #endif 3776 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3777 PHYMOD_SYMBOL_FLAG_REGISTER, 3778 "DSC_SM_CTL7r", 3779 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3780 "DSC_B_DSC_SM_CTRL_7", 3781 NULL, 3782 #endif 3783 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3784 0x0, /* 0 */ 3785 0, 3786 #endif 3787 }, 3788 { 3789 BCMI_EAGLE_XGXS_DSC_SM_CTL8r, 3790 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3791 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 3792 BCMI_EAGLE_XGXS_DSC_SM_CTL8r_fields, 3793 #else 3794 0, 3795 #endif 3796 #endif 3797 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3798 PHYMOD_SYMBOL_FLAG_REGISTER, 3799 "DSC_SM_CTL8r", 3800 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3801 "DSC_B_DSC_SM_CTRL_8", 3802 NULL, 3803 #endif 3804 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3805 0x11, /* 17 */ 3806 0, 3807 #endif 3808 }, 3809 { 3810 BCMI_EAGLE_XGXS_DSC_SM_CTL9r, 3811 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3812 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 3813 BCMI_EAGLE_XGXS_DSC_SM_CTL9r_fields, 3814 #else 3815 0, 3816 #endif 3817 #endif 3818 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3819 PHYMOD_SYMBOL_FLAG_REGISTER, 3820 "DSC_SM_CTL9r", 3821 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3822 "DSC_B_DSC_SM_CTRL_9", 3823 NULL, 3824 #endif 3825 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3826 0x0, /* 0 */ 3827 0, 3828 #endif 3829 }, 3830 { 3831 BCMI_EAGLE_XGXS_DSC_SM_STS_DSC_LOCKr, 3832 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3833 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 3834 BCMI_EAGLE_XGXS_DSC_SM_STS_DSC_LOCKr_fields, 3835 #else 3836 0, 3837 #endif 3838 #endif 3839 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3840 PHYMOD_SYMBOL_FLAG_REGISTER, 3841 "DSC_SM_STS_DSC_LOCKr", 3842 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3843 "DSC_B_DSC_SM_STATUS_DSC_LOCK", 3844 NULL, 3845 #endif 3846 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3847 0x0, /* 0 */ 3848 0, 3849 #endif 3850 }, 3851 { 3852 BCMI_EAGLE_XGXS_DSC_SM_STS_DSC_ST_ONE_HOTr, 3853 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3854 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 3855 BCMI_EAGLE_XGXS_DSC_SM_STS_DSC_ST_ONE_HOTr_fields, 3856 #else 3857 0, 3858 #endif 3859 #endif 3860 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3861 PHYMOD_SYMBOL_FLAG_REGISTER, 3862 "DSC_SM_STS_DSC_ST_ONE_HOTr", 3863 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3864 "DSC_B_DSC_SM_STATUS_DSC_STATE_ONE_HOT", 3865 NULL, 3866 #endif 3867 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3868 0x0, /* 0 */ 3869 0, 3870 #endif 3871 }, 3872 { 3873 BCMI_EAGLE_XGXS_DSC_SM_STS_DSC_ST_EEE_ONE_HOTr, 3874 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3875 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 3876 BCMI_EAGLE_XGXS_DSC_SM_STS_DSC_ST_EEE_ONE_HOTr_fields, 3877 #else 3878 0, 3879 #endif 3880 #endif 3881 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3882 PHYMOD_SYMBOL_FLAG_REGISTER, 3883 "DSC_SM_STS_DSC_ST_EEE_ONE_HOTr", 3884 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3885 "DSC_B_DSC_SM_STATUS_DSC_STATE_EEE_ONE_HOT", 3886 NULL, 3887 #endif 3888 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3889 0x0, /* 0 */ 3890 0, 3891 #endif 3892 }, 3893 { 3894 BCMI_EAGLE_XGXS_DSC_SM_STS_RESTARTr, 3895 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3896 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 3897 BCMI_EAGLE_XGXS_DSC_SM_STS_RESTARTr_fields, 3898 #else 3899 0, 3900 #endif 3901 #endif 3902 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3903 PHYMOD_SYMBOL_FLAG_REGISTER, 3904 "DSC_SM_STS_RESTARTr", 3905 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3906 "DSC_B_DSC_SM_STATUS_RESTART", 3907 NULL, 3908 #endif 3909 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3910 0x0, /* 0 */ 3911 0, 3912 #endif 3913 }, 3914 { 3915 BCMI_EAGLE_XGXS_DSC_SM_STS_DSC_STr, 3916 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3917 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 3918 BCMI_EAGLE_XGXS_DSC_SM_STS_DSC_STr_fields, 3919 #else 3920 0, 3921 #endif 3922 #endif 3923 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3924 PHYMOD_SYMBOL_FLAG_REGISTER, 3925 "DSC_SM_STS_DSC_STr", 3926 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3927 "DSC_B_DSC_SM_STATUS_DSC_STATE", 3928 NULL, 3929 #endif 3930 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3931 0x0, /* 0 */ 3932 0, 3933 #endif 3934 }, 3935 { 3936 BCMI_EAGLE_XGXS_DSC_DFE_COMMON_CTLr, 3937 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3938 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 3939 BCMI_EAGLE_XGXS_DSC_DFE_COMMON_CTLr_fields, 3940 #else 3941 0, 3942 #endif 3943 #endif 3944 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3945 PHYMOD_SYMBOL_FLAG_REGISTER, 3946 "DSC_DFE_COMMON_CTLr", 3947 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3948 "DSC_C_DFE_COMMON_CTL", 3949 NULL, 3950 #endif 3951 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3952 0x0, /* 0 */ 3953 0, 3954 #endif 3955 }, 3956 { 3957 BCMI_EAGLE_XGXS_DSC_DFE_1_CTLr, 3958 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3959 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 3960 BCMI_EAGLE_XGXS_DSC_DFE_1_CTLr_fields, 3961 #else 3962 0, 3963 #endif 3964 #endif 3965 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3966 PHYMOD_SYMBOL_FLAG_REGISTER, 3967 "DSC_DFE_1_CTLr", 3968 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3969 "DSC_C_DFE_1_CTL", 3970 NULL, 3971 #endif 3972 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3973 0x0, /* 0 */ 3974 0, 3975 #endif 3976 }, 3977 { 3978 BCMI_EAGLE_XGXS_DSC_DFE_1_PAT_CTLr, 3979 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 3980 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 3981 BCMI_EAGLE_XGXS_DSC_DFE_1_PAT_CTLr_fields, 3982 #else 3983 0, 3984 #endif 3985 #endif 3986 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 3987 PHYMOD_SYMBOL_FLAG_REGISTER, 3988 "DSC_DFE_1_PAT_CTLr", 3989 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 3990 "DSC_C_DFE_1_PAT_CTL", 3991 NULL, 3992 #endif 3993 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 3994 0x0, /* 0 */ 3995 0, 3996 #endif 3997 }, 3998 { 3999 BCMI_EAGLE_XGXS_DSC_DFE_2_CTLr, 4000 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4001 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 4002 BCMI_EAGLE_XGXS_DSC_DFE_2_CTLr_fields, 4003 #else 4004 0, 4005 #endif 4006 #endif 4007 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4008 PHYMOD_SYMBOL_FLAG_REGISTER, 4009 "DSC_DFE_2_CTLr", 4010 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4011 "DSC_C_DFE_2_CTL", 4012 NULL, 4013 #endif 4014 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4015 0x0, /* 0 */ 4016 0, 4017 #endif 4018 }, 4019 { 4020 BCMI_EAGLE_XGXS_DSC_DFE_2_PAT_CTLr, 4021 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4022 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 4023 BCMI_EAGLE_XGXS_DSC_DFE_2_PAT_CTLr_fields, 4024 #else 4025 0, 4026 #endif 4027 #endif 4028 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4029 PHYMOD_SYMBOL_FLAG_REGISTER, 4030 "DSC_DFE_2_PAT_CTLr", 4031 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4032 "DSC_C_DFE_2_PAT_CTL", 4033 NULL, 4034 #endif 4035 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4036 0x0, /* 0 */ 4037 0, 4038 #endif 4039 }, 4040 { 4041 BCMI_EAGLE_XGXS_DSC_DFE_3_CTLr, 4042 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4043 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 4044 BCMI_EAGLE_XGXS_DSC_DFE_3_CTLr_fields, 4045 #else 4046 0, 4047 #endif 4048 #endif 4049 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4050 PHYMOD_SYMBOL_FLAG_REGISTER, 4051 "DSC_DFE_3_CTLr", 4052 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4053 "DSC_C_DFE_3_CTL", 4054 NULL, 4055 #endif 4056 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4057 0x0, /* 0 */ 4058 0, 4059 #endif 4060 }, 4061 { 4062 BCMI_EAGLE_XGXS_DSC_DFE_3_PAT_CTLr, 4063 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4064 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 4065 BCMI_EAGLE_XGXS_DSC_DFE_3_PAT_CTLr_fields, 4066 #else 4067 0, 4068 #endif 4069 #endif 4070 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4071 PHYMOD_SYMBOL_FLAG_REGISTER, 4072 "DSC_DFE_3_PAT_CTLr", 4073 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4074 "DSC_C_DFE_3_PAT_CTL", 4075 NULL, 4076 #endif 4077 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4078 0x0, /* 0 */ 4079 0, 4080 #endif 4081 }, 4082 { 4083 BCMI_EAGLE_XGXS_DSC_DFE_4_CTLr, 4084 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4085 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 4086 BCMI_EAGLE_XGXS_DSC_DFE_4_CTLr_fields, 4087 #else 4088 0, 4089 #endif 4090 #endif 4091 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4092 PHYMOD_SYMBOL_FLAG_REGISTER, 4093 "DSC_DFE_4_CTLr", 4094 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4095 "DSC_C_DFE_4_CTL", 4096 NULL, 4097 #endif 4098 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4099 0x0, /* 0 */ 4100 0, 4101 #endif 4102 }, 4103 { 4104 BCMI_EAGLE_XGXS_DSC_DFE_4_PAT_CTLr, 4105 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4106 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 4107 BCMI_EAGLE_XGXS_DSC_DFE_4_PAT_CTLr_fields, 4108 #else 4109 0, 4110 #endif 4111 #endif 4112 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4113 PHYMOD_SYMBOL_FLAG_REGISTER, 4114 "DSC_DFE_4_PAT_CTLr", 4115 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4116 "DSC_C_DFE_4_PAT_CTL", 4117 NULL, 4118 #endif 4119 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4120 0x0, /* 0 */ 4121 0, 4122 #endif 4123 }, 4124 { 4125 BCMI_EAGLE_XGXS_DSC_DFE_5_CTLr, 4126 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4127 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 4128 BCMI_EAGLE_XGXS_DSC_DFE_5_CTLr_fields, 4129 #else 4130 0, 4131 #endif 4132 #endif 4133 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4134 PHYMOD_SYMBOL_FLAG_REGISTER, 4135 "DSC_DFE_5_CTLr", 4136 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4137 "DSC_C_DFE_5_CTL", 4138 NULL, 4139 #endif 4140 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4141 0x0, /* 0 */ 4142 0, 4143 #endif 4144 }, 4145 { 4146 BCMI_EAGLE_XGXS_DSC_DFE_5_PAT_CTLr, 4147 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4148 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 4149 BCMI_EAGLE_XGXS_DSC_DFE_5_PAT_CTLr_fields, 4150 #else 4151 0, 4152 #endif 4153 #endif 4154 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4155 PHYMOD_SYMBOL_FLAG_REGISTER, 4156 "DSC_DFE_5_PAT_CTLr", 4157 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4158 "DSC_C_DFE_5_PAT_CTL", 4159 NULL, 4160 #endif 4161 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4162 0x0, /* 0 */ 4163 0, 4164 #endif 4165 }, 4166 { 4167 BCMI_EAGLE_XGXS_DSC_DFE_VGA_OVRRr, 4168 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4169 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 4170 BCMI_EAGLE_XGXS_DSC_DFE_VGA_OVRRr_fields, 4171 #else 4172 0, 4173 #endif 4174 #endif 4175 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4176 PHYMOD_SYMBOL_FLAG_REGISTER, 4177 "DSC_DFE_VGA_OVRRr", 4178 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4179 "DSC_C_DFE_VGA_OVERRIDE", 4180 NULL, 4181 #endif 4182 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4183 0x0, /* 0 */ 4184 0, 4185 #endif 4186 }, 4187 { 4188 BCMI_EAGLE_XGXS_DSC_VGA_CTLr, 4189 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4190 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 4191 BCMI_EAGLE_XGXS_DSC_VGA_CTLr_fields, 4192 #else 4193 0, 4194 #endif 4195 #endif 4196 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4197 PHYMOD_SYMBOL_FLAG_REGISTER, 4198 "DSC_VGA_CTLr", 4199 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4200 "DSC_C_VGA_CTL", 4201 NULL, 4202 #endif 4203 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4204 0x0, /* 0 */ 4205 0, 4206 #endif 4207 }, 4208 { 4209 BCMI_EAGLE_XGXS_DSC_VGA_PAT_EYEDIAG_CTLr, 4210 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4211 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 4212 BCMI_EAGLE_XGXS_DSC_VGA_PAT_EYEDIAG_CTLr_fields, 4213 #else 4214 0, 4215 #endif 4216 #endif 4217 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4218 PHYMOD_SYMBOL_FLAG_REGISTER, 4219 "DSC_VGA_PAT_EYEDIAG_CTLr", 4220 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4221 "DSC_C_VGA_PAT_EYEDIAG_CTL", 4222 NULL, 4223 #endif 4224 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4225 0x0, /* 0 */ 4226 0, 4227 #endif 4228 }, 4229 { 4230 BCMI_EAGLE_XGXS_DSC_P1_FRAC_OFFS_CTLr, 4231 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4232 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 4233 BCMI_EAGLE_XGXS_DSC_P1_FRAC_OFFS_CTLr_fields, 4234 #else 4235 0, 4236 #endif 4237 #endif 4238 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4239 PHYMOD_SYMBOL_FLAG_REGISTER, 4240 "DSC_P1_FRAC_OFFS_CTLr", 4241 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4242 "DSC_C_P1_FRAC_OFFS_CTL", 4243 NULL, 4244 #endif 4245 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4246 0x0, /* 0 */ 4247 0, 4248 #endif 4249 }, 4250 { 4251 BCMI_EAGLE_XGXS_DSC_TRNSUM_CTL1r, 4252 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4253 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 4254 BCMI_EAGLE_XGXS_DSC_TRNSUM_CTL1r_fields, 4255 #else 4256 0, 4257 #endif 4258 #endif 4259 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4260 PHYMOD_SYMBOL_FLAG_REGISTER, 4261 "DSC_TRNSUM_CTL1r", 4262 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4263 "DSC_D_TRNSUM_CTL_1", 4264 NULL, 4265 #endif 4266 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4267 0x0, /* 0 */ 4268 0, 4269 #endif 4270 }, 4271 { 4272 BCMI_EAGLE_XGXS_DSC_TRNSUM_CTL2r, 4273 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4274 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 4275 BCMI_EAGLE_XGXS_DSC_TRNSUM_CTL2r_fields, 4276 #else 4277 0, 4278 #endif 4279 #endif 4280 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4281 PHYMOD_SYMBOL_FLAG_REGISTER, 4282 "DSC_TRNSUM_CTL2r", 4283 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4284 "DSC_D_TRNSUM_CTL_2", 4285 NULL, 4286 #endif 4287 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4288 0x0, /* 0 */ 4289 0, 4290 #endif 4291 }, 4292 { 4293 BCMI_EAGLE_XGXS_DSC_TRNSUM_CTL3r, 4294 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4295 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 4296 BCMI_EAGLE_XGXS_DSC_TRNSUM_CTL3r_fields, 4297 #else 4298 0, 4299 #endif 4300 #endif 4301 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4302 PHYMOD_SYMBOL_FLAG_REGISTER, 4303 "DSC_TRNSUM_CTL3r", 4304 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4305 "DSC_D_TRNSUM_CTL_3", 4306 NULL, 4307 #endif 4308 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4309 0x0, /* 0 */ 4310 0, 4311 #endif 4312 }, 4313 { 4314 BCMI_EAGLE_XGXS_DSC_TRNSUM_CTL4r, 4315 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4316 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 4317 BCMI_EAGLE_XGXS_DSC_TRNSUM_CTL4r_fields, 4318 #else 4319 0, 4320 #endif 4321 #endif 4322 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4323 PHYMOD_SYMBOL_FLAG_REGISTER, 4324 "DSC_TRNSUM_CTL4r", 4325 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4326 "DSC_D_TRNSUM_CTL_4", 4327 NULL, 4328 #endif 4329 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4330 0x0, /* 0 */ 4331 0, 4332 #endif 4333 }, 4334 { 4335 BCMI_EAGLE_XGXS_DSC_TRNSUM_STS1r, 4336 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4337 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 4338 BCMI_EAGLE_XGXS_DSC_TRNSUM_STS1r_fields, 4339 #else 4340 0, 4341 #endif 4342 #endif 4343 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4344 PHYMOD_SYMBOL_FLAG_REGISTER, 4345 "DSC_TRNSUM_STS1r", 4346 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4347 "DSC_D_TRNSUM_STS_1", 4348 NULL, 4349 #endif 4350 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4351 0x0, /* 0 */ 4352 0, 4353 #endif 4354 }, 4355 { 4356 BCMI_EAGLE_XGXS_DSC_TRNSUM_STS2r, 4357 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4358 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 4359 BCMI_EAGLE_XGXS_DSC_TRNSUM_STS2r_fields, 4360 #else 4361 0, 4362 #endif 4363 #endif 4364 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4365 PHYMOD_SYMBOL_FLAG_REGISTER, 4366 "DSC_TRNSUM_STS2r", 4367 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4368 "DSC_D_TRNSUM_STS_2", 4369 NULL, 4370 #endif 4371 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4372 0x0, /* 0 */ 4373 0, 4374 #endif 4375 }, 4376 { 4377 BCMI_EAGLE_XGXS_DSC_TRNSUM_STS3r, 4378 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4379 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 4380 BCMI_EAGLE_XGXS_DSC_TRNSUM_STS3r_fields, 4381 #else 4382 0, 4383 #endif 4384 #endif 4385 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4386 PHYMOD_SYMBOL_FLAG_REGISTER, 4387 "DSC_TRNSUM_STS3r", 4388 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4389 "DSC_D_TRNSUM_STS_3", 4390 NULL, 4391 #endif 4392 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4393 0x0, /* 0 */ 4394 0, 4395 #endif 4396 }, 4397 { 4398 BCMI_EAGLE_XGXS_DSC_TRNSUM_STS4r, 4399 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4400 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 4401 BCMI_EAGLE_XGXS_DSC_TRNSUM_STS4r_fields, 4402 #else 4403 0, 4404 #endif 4405 #endif 4406 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4407 PHYMOD_SYMBOL_FLAG_REGISTER, 4408 "DSC_TRNSUM_STS4r", 4409 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4410 "DSC_D_TRNSUM_STS_4", 4411 NULL, 4412 #endif 4413 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4414 0x0, /* 0 */ 4415 0, 4416 #endif 4417 }, 4418 { 4419 BCMI_EAGLE_XGXS_DSC_TRNSUM_STS5r, 4420 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4421 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 4422 BCMI_EAGLE_XGXS_DSC_TRNSUM_STS5r_fields, 4423 #else 4424 0, 4425 #endif 4426 #endif 4427 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4428 PHYMOD_SYMBOL_FLAG_REGISTER, 4429 "DSC_TRNSUM_STS5r", 4430 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4431 "DSC_D_TRNSUM_STS_5", 4432 NULL, 4433 #endif 4434 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4435 0x0, /* 0 */ 4436 0, 4437 #endif 4438 }, 4439 { 4440 BCMI_EAGLE_XGXS_DSC_TRNSUM_STS6r, 4441 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4442 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 4443 BCMI_EAGLE_XGXS_DSC_TRNSUM_STS6r_fields, 4444 #else 4445 0, 4446 #endif 4447 #endif 4448 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4449 PHYMOD_SYMBOL_FLAG_REGISTER, 4450 "DSC_TRNSUM_STS6r", 4451 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4452 "DSC_D_TRNSUM_STS_6", 4453 NULL, 4454 #endif 4455 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4456 0x0, /* 0 */ 4457 0, 4458 #endif 4459 }, 4460 { 4461 BCMI_EAGLE_XGXS_DSC_VGA_P1EYEDIAG_STSr, 4462 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4463 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 4464 BCMI_EAGLE_XGXS_DSC_VGA_P1EYEDIAG_STSr_fields, 4465 #else 4466 0, 4467 #endif 4468 #endif 4469 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4470 PHYMOD_SYMBOL_FLAG_REGISTER, 4471 "DSC_VGA_P1EYEDIAG_STSr", 4472 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4473 "DSC_D_VGA_P1EYEDIAG_STS", 4474 NULL, 4475 #endif 4476 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4477 0x0, /* 0 */ 4478 0, 4479 #endif 4480 }, 4481 { 4482 BCMI_EAGLE_XGXS_DSC_DFE_1_STSr, 4483 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4484 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 4485 BCMI_EAGLE_XGXS_DSC_DFE_1_STSr_fields, 4486 #else 4487 0, 4488 #endif 4489 #endif 4490 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4491 PHYMOD_SYMBOL_FLAG_REGISTER, 4492 "DSC_DFE_1_STSr", 4493 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4494 "DSC_D_DFE_1_STS", 4495 NULL, 4496 #endif 4497 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4498 0x0, /* 0 */ 4499 0, 4500 #endif 4501 }, 4502 { 4503 BCMI_EAGLE_XGXS_DSC_DFE_2_STSr, 4504 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4505 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 4506 BCMI_EAGLE_XGXS_DSC_DFE_2_STSr_fields, 4507 #else 4508 0, 4509 #endif 4510 #endif 4511 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4512 PHYMOD_SYMBOL_FLAG_REGISTER, 4513 "DSC_DFE_2_STSr", 4514 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4515 "DSC_D_DFE_2_STS", 4516 NULL, 4517 #endif 4518 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4519 0x0, /* 0 */ 4520 0, 4521 #endif 4522 }, 4523 { 4524 BCMI_EAGLE_XGXS_DSC_DFE_3_4_5_STSr, 4525 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4526 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 4527 BCMI_EAGLE_XGXS_DSC_DFE_3_4_5_STSr_fields, 4528 #else 4529 0, 4530 #endif 4531 #endif 4532 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4533 PHYMOD_SYMBOL_FLAG_REGISTER, 4534 "DSC_DFE_3_4_5_STSr", 4535 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4536 "DSC_D_DFE_3_4_5_STS", 4537 NULL, 4538 #endif 4539 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4540 0x0, /* 0 */ 4541 0, 4542 #endif 4543 }, 4544 { 4545 BCMI_EAGLE_XGXS_DSC_VGA_TAP_BINr, 4546 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4547 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 4548 BCMI_EAGLE_XGXS_DSC_VGA_TAP_BINr_fields, 4549 #else 4550 0, 4551 #endif 4552 #endif 4553 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4554 PHYMOD_SYMBOL_FLAG_REGISTER, 4555 "DSC_VGA_TAP_BINr", 4556 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4557 "DSC_D_VGA_TAP_BIN", 4558 NULL, 4559 #endif 4560 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4561 0x0, /* 0 */ 4562 0, 4563 #endif 4564 }, 4565 { 4566 BCMI_EAGLE_XGXS_DSC_CTLr, 4567 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4568 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 4569 BCMI_EAGLE_XGXS_DSC_CTLr_fields, 4570 #else 4571 0, 4572 #endif 4573 #endif 4574 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4575 PHYMOD_SYMBOL_FLAG_REGISTER, 4576 "DSC_CTLr", 4577 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4578 "DSC_E_CTRL", 4579 NULL, 4580 #endif 4581 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4582 0x20, /* 32 */ 4583 0, 4584 #endif 4585 }, 4586 { 4587 BCMI_EAGLE_XGXS_DSC_PF_CTLr, 4588 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4589 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 4590 BCMI_EAGLE_XGXS_DSC_PF_CTLr_fields, 4591 #else 4592 0, 4593 #endif 4594 #endif 4595 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4596 PHYMOD_SYMBOL_FLAG_REGISTER, 4597 "DSC_PF_CTLr", 4598 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4599 "DSC_E_PF_CTRL", 4600 NULL, 4601 #endif 4602 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4603 0x0, /* 0 */ 4604 0, 4605 #endif 4606 }, 4607 { 4608 BCMI_EAGLE_XGXS_DSC_PF2_LOWP_CTLr, 4609 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4610 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 4611 BCMI_EAGLE_XGXS_DSC_PF2_LOWP_CTLr_fields, 4612 #else 4613 0, 4614 #endif 4615 #endif 4616 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4617 PHYMOD_SYMBOL_FLAG_REGISTER, 4618 "DSC_PF2_LOWP_CTLr", 4619 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4620 "DSC_E_PF2_LOWP_CTRL", 4621 NULL, 4622 #endif 4623 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4624 0x0, /* 0 */ 4625 0, 4626 #endif 4627 }, 4628 { 4629 BCMI_EAGLE_XGXS_DSC_OFFS_ADJ_DATA_ODDr, 4630 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4631 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 4632 BCMI_EAGLE_XGXS_DSC_OFFS_ADJ_DATA_ODDr_fields, 4633 #else 4634 0, 4635 #endif 4636 #endif 4637 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4638 PHYMOD_SYMBOL_FLAG_REGISTER, 4639 "DSC_OFFS_ADJ_DATA_ODDr", 4640 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4641 "DSC_E_OFFSET_ADJ_DATA_ODD", 4642 NULL, 4643 #endif 4644 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4645 0x0, /* 0 */ 4646 0, 4647 #endif 4648 }, 4649 { 4650 BCMI_EAGLE_XGXS_DSC_OFFS_ADJ_DATA_EVENr, 4651 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4652 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 4653 BCMI_EAGLE_XGXS_DSC_OFFS_ADJ_DATA_EVENr_fields, 4654 #else 4655 0, 4656 #endif 4657 #endif 4658 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4659 PHYMOD_SYMBOL_FLAG_REGISTER, 4660 "DSC_OFFS_ADJ_DATA_EVENr", 4661 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4662 "DSC_E_OFFSET_ADJ_DATA_EVEN", 4663 NULL, 4664 #endif 4665 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4666 0x0, /* 0 */ 4667 0, 4668 #endif 4669 }, 4670 { 4671 BCMI_EAGLE_XGXS_DSC_OFFS_ADJ_P1_ODDr, 4672 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4673 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 4674 BCMI_EAGLE_XGXS_DSC_OFFS_ADJ_P1_ODDr_fields, 4675 #else 4676 0, 4677 #endif 4678 #endif 4679 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4680 PHYMOD_SYMBOL_FLAG_REGISTER, 4681 "DSC_OFFS_ADJ_P1_ODDr", 4682 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4683 "DSC_E_OFFSET_ADJ_P1_ODD", 4684 NULL, 4685 #endif 4686 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4687 0x0, /* 0 */ 4688 0, 4689 #endif 4690 }, 4691 { 4692 BCMI_EAGLE_XGXS_DSC_OFFS_ADJ_P1_EVENr, 4693 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4694 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 4695 BCMI_EAGLE_XGXS_DSC_OFFS_ADJ_P1_EVENr_fields, 4696 #else 4697 0, 4698 #endif 4699 #endif 4700 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4701 PHYMOD_SYMBOL_FLAG_REGISTER, 4702 "DSC_OFFS_ADJ_P1_EVENr", 4703 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4704 "DSC_E_OFFSET_ADJ_P1_EVEN", 4705 NULL, 4706 #endif 4707 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4708 0x0, /* 0 */ 4709 0, 4710 #endif 4711 }, 4712 { 4713 BCMI_EAGLE_XGXS_DSC_OFFS_ADJ_M1_ODDr, 4714 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4715 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 4716 BCMI_EAGLE_XGXS_DSC_OFFS_ADJ_M1_ODDr_fields, 4717 #else 4718 0, 4719 #endif 4720 #endif 4721 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4722 PHYMOD_SYMBOL_FLAG_REGISTER, 4723 "DSC_OFFS_ADJ_M1_ODDr", 4724 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4725 "DSC_E_OFFSET_ADJ_M1_ODD", 4726 NULL, 4727 #endif 4728 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4729 0x0, /* 0 */ 4730 0, 4731 #endif 4732 }, 4733 { 4734 BCMI_EAGLE_XGXS_DSC_OFFS_ADJ_M1_EVENr, 4735 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4736 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 4737 BCMI_EAGLE_XGXS_DSC_OFFS_ADJ_M1_EVENr_fields, 4738 #else 4739 0, 4740 #endif 4741 #endif 4742 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4743 PHYMOD_SYMBOL_FLAG_REGISTER, 4744 "DSC_OFFS_ADJ_M1_EVENr", 4745 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4746 "DSC_E_OFFSET_ADJ_M1_EVEN", 4747 NULL, 4748 #endif 4749 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4750 0x0, /* 0 */ 4751 0, 4752 #endif 4753 }, 4754 { 4755 BCMI_EAGLE_XGXS_DSC_DC_OFFSr, 4756 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4757 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 4758 BCMI_EAGLE_XGXS_DSC_DC_OFFSr_fields, 4759 #else 4760 0, 4761 #endif 4762 #endif 4763 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4764 PHYMOD_SYMBOL_FLAG_REGISTER, 4765 "DSC_DC_OFFSr", 4766 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4767 "DSC_E_DC_OFFSET", 4768 NULL, 4769 #endif 4770 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4771 0x0, /* 0 */ 4772 0, 4773 #endif 4774 }, 4775 { 4776 BCMI_EAGLE_XGXS_CL72_RXRCVD_STSr, 4777 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4778 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 4779 BCMI_EAGLE_XGXS_CL72_RXRCVD_STSr_fields, 4780 #else 4781 0, 4782 #endif 4783 #endif 4784 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4785 PHYMOD_SYMBOL_FLAG_REGISTER, 4786 "CL72_RXRCVD_STSr", 4787 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4788 "CL72_USER_RX_RCVD_STATUS_REGISTER", 4789 NULL, 4790 #endif 4791 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4792 0x0, /* 0 */ 4793 0, 4794 #endif 4795 }, 4796 { 4797 BCMI_EAGLE_XGXS_CL72_RXMISC1_CTLr, 4798 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4799 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 4800 BCMI_EAGLE_XGXS_CL72_RXMISC1_CTLr_fields, 4801 #else 4802 0, 4803 #endif 4804 #endif 4805 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4806 PHYMOD_SYMBOL_FLAG_REGISTER, 4807 "CL72_RXMISC1_CTLr", 4808 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4809 "CL72_USER_RX_MISC1_CONTROL", 4810 NULL, 4811 #endif 4812 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4813 0x4, /* 4 */ 4814 0, 4815 #endif 4816 }, 4817 { 4818 BCMI_EAGLE_XGXS_CL72_RXDBG2r, 4819 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4820 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 4821 BCMI_EAGLE_XGXS_CL72_RXDBG2r_fields, 4822 #else 4823 0, 4824 #endif 4825 #endif 4826 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4827 PHYMOD_SYMBOL_FLAG_REGISTER, 4828 "CL72_RXDBG2r", 4829 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4830 "CL72_USER_RX_DEBUG_2_REGISTER", 4831 NULL, 4832 #endif 4833 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4834 0x96, /* 150 */ 4835 0, 4836 #endif 4837 }, 4838 { 4839 BCMI_EAGLE_XGXS_CL72_RXCL72_LP_CTL_PAGEr, 4840 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4841 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 4842 BCMI_EAGLE_XGXS_CL72_RXCL72_LP_CTL_PAGEr_fields, 4843 #else 4844 0, 4845 #endif 4846 #endif 4847 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4848 PHYMOD_SYMBOL_FLAG_REGISTER, 4849 "CL72_RXCL72_LP_CTL_PAGEr", 4850 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4851 "CL72_USER_RX_CL72_LP_CONTROL_PAGE", 4852 NULL, 4853 #endif 4854 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4855 0x0, /* 0 */ 4856 0, 4857 #endif 4858 }, 4859 { 4860 BCMI_EAGLE_XGXS_CL72_RXCL72_STS1r, 4861 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4862 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 4863 BCMI_EAGLE_XGXS_CL72_RXCL72_STS1r_fields, 4864 #else 4865 0, 4866 #endif 4867 #endif 4868 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4869 PHYMOD_SYMBOL_FLAG_REGISTER, 4870 "CL72_RXCL72_STS1r", 4871 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4872 "CL72_USER_RX_CL72_STATUS1_REGISTER", 4873 NULL, 4874 #endif 4875 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4876 0x0, /* 0 */ 4877 0, 4878 #endif 4879 }, 4880 { 4881 BCMI_EAGLE_XGXS_CL72_TXXMT_UPDr, 4882 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4883 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 4884 BCMI_EAGLE_XGXS_CL72_TXXMT_UPDr_fields, 4885 #else 4886 0, 4887 #endif 4888 #endif 4889 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4890 PHYMOD_SYMBOL_FLAG_REGISTER, 4891 "CL72_TXXMT_UPDr", 4892 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4893 "CL72_USER_TX_XMT_UPDATE_REGISTER", 4894 NULL, 4895 #endif 4896 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4897 0x0, /* 0 */ 4898 0, 4899 #endif 4900 }, 4901 { 4902 BCMI_EAGLE_XGXS_CL72_TXMISC2_CTLr, 4903 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4904 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 4905 BCMI_EAGLE_XGXS_CL72_TXMISC2_CTLr_fields, 4906 #else 4907 0, 4908 #endif 4909 #endif 4910 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4911 PHYMOD_SYMBOL_FLAG_REGISTER, 4912 "CL72_TXMISC2_CTLr", 4913 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4914 "CL72_USER_TX_MISC2_CONTROL", 4915 NULL, 4916 #endif 4917 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4918 0x4, /* 4 */ 4919 0, 4920 #endif 4921 }, 4922 { 4923 BCMI_EAGLE_XGXS_CL72_TXDBG3r, 4924 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4925 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 4926 BCMI_EAGLE_XGXS_CL72_TXDBG3r_fields, 4927 #else 4928 0, 4929 #endif 4930 #endif 4931 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4932 PHYMOD_SYMBOL_FLAG_REGISTER, 4933 "CL72_TXDBG3r", 4934 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4935 "CL72_USER_TX_DEBUG_3_REGISTER", 4936 NULL, 4937 #endif 4938 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4939 0x2, /* 2 */ 4940 0, 4941 #endif 4942 }, 4943 { 4944 BCMI_EAGLE_XGXS_CL72_TXPCS_INTERFACE_CTLr, 4945 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4946 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 4947 BCMI_EAGLE_XGXS_CL72_TXPCS_INTERFACE_CTLr_fields, 4948 #else 4949 0, 4950 #endif 4951 #endif 4952 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4953 PHYMOD_SYMBOL_FLAG_REGISTER, 4954 "CL72_TXPCS_INTERFACE_CTLr", 4955 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4956 "CL72_USER_TX_PCS_INTERFACE_CONTROL_REGISTER", 4957 NULL, 4958 #endif 4959 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4960 0x0, /* 0 */ 4961 0, 4962 #endif 4963 }, 4964 { 4965 BCMI_EAGLE_XGXS_CL72_TXCL72_LD_STS_PAGEr, 4966 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4967 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 4968 BCMI_EAGLE_XGXS_CL72_TXCL72_LD_STS_PAGEr_fields, 4969 #else 4970 0, 4971 #endif 4972 #endif 4973 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4974 PHYMOD_SYMBOL_FLAG_REGISTER, 4975 "CL72_TXCL72_LD_STS_PAGEr", 4976 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4977 "CL72_USER_TX_CL72_LD_STATUS_PAGE", 4978 NULL, 4979 #endif 4980 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 4981 0x0, /* 0 */ 4982 0, 4983 #endif 4984 }, 4985 { 4986 BCMI_EAGLE_XGXS_CL72_TXCL72_READY_FOR_CMDr, 4987 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 4988 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 4989 BCMI_EAGLE_XGXS_CL72_TXCL72_READY_FOR_CMDr_fields, 4990 #else 4991 0, 4992 #endif 4993 #endif 4994 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 4995 PHYMOD_SYMBOL_FLAG_REGISTER, 4996 "CL72_TXCL72_READY_FOR_CMDr", 4997 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 4998 "CL72_USER_TX_CL72_READY_FOR_CMD_REGISTER", 4999 NULL, 5000 #endif 5001 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5002 0x1, /* 1 */ 5003 0, 5004 #endif 5005 }, 5006 { 5007 BCMI_EAGLE_XGXS_CL72_TXKR_DFLT_CTL1r, 5008 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5009 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 5010 BCMI_EAGLE_XGXS_CL72_TXKR_DFLT_CTL1r_fields, 5011 #else 5012 0, 5013 #endif 5014 #endif 5015 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5016 PHYMOD_SYMBOL_FLAG_REGISTER, 5017 "CL72_TXKR_DFLT_CTL1r", 5018 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5019 "CL72_USER_TX_KR_DEFAULT_CONTROL1", 5020 NULL, 5021 #endif 5022 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5023 0x588, /* 1416 */ 5024 0, 5025 #endif 5026 }, 5027 { 5028 BCMI_EAGLE_XGXS_CL72_TXKR_DFLT_CTL2r, 5029 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5030 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 5031 BCMI_EAGLE_XGXS_CL72_TXKR_DFLT_CTL2r_fields, 5032 #else 5033 0, 5034 #endif 5035 #endif 5036 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5037 PHYMOD_SYMBOL_FLAG_REGISTER, 5038 "CL72_TXKR_DFLT_CTL2r", 5039 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5040 "CL72_USER_TX_KR_DEFAULT_CONTROL2", 5041 NULL, 5042 #endif 5043 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5044 0x3c, /* 60 */ 5045 0, 5046 #endif 5047 }, 5048 { 5049 BCMI_EAGLE_XGXS_CL72_TXMISC_COEFF_CTLr, 5050 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5051 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 5052 BCMI_EAGLE_XGXS_CL72_TXMISC_COEFF_CTLr_fields, 5053 #else 5054 0, 5055 #endif 5056 #endif 5057 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5058 PHYMOD_SYMBOL_FLAG_REGISTER, 5059 "CL72_TXMISC_COEFF_CTLr", 5060 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5061 "CL72_USER_TX_MISC_COEFF_CONTROL", 5062 NULL, 5063 #endif 5064 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5065 0x83, /* 131 */ 5066 0, 5067 #endif 5068 }, 5069 { 5070 BCMI_EAGLE_XGXS_CL72_TXCL72_LD_XMT_STS_PAGE_OVRRr, 5071 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5072 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 5073 BCMI_EAGLE_XGXS_CL72_TXCL72_LD_XMT_STS_PAGE_OVRRr_fields, 5074 #else 5075 0, 5076 #endif 5077 #endif 5078 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5079 PHYMOD_SYMBOL_FLAG_REGISTER, 5080 "CL72_TXCL72_LD_XMT_STS_PAGE_OVRRr", 5081 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5082 "CL72_USER_TX_CL72_LD_XMT_STATUS_PAGE_OVERRIDE", 5083 NULL, 5084 #endif 5085 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5086 0x0, /* 0 */ 5087 0, 5088 #endif 5089 }, 5090 { 5091 BCMI_EAGLE_XGXS_CL72_TXCL72_TX_DBG_STSr, 5092 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5093 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 5094 BCMI_EAGLE_XGXS_CL72_TXCL72_TX_DBG_STSr_fields, 5095 #else 5096 0, 5097 #endif 5098 #endif 5099 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5100 PHYMOD_SYMBOL_FLAG_REGISTER, 5101 "CL72_TXCL72_TX_DBG_STSr", 5102 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5103 "CL72_USER_TX_CL72_TX_DEBUG_STATUS", 5104 NULL, 5105 #endif 5106 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5107 0x0, /* 0 */ 5108 0, 5109 #endif 5110 }, 5111 { 5112 BCMI_EAGLE_XGXS_TX_PI_CTL0r, 5113 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5114 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 5115 BCMI_EAGLE_XGXS_TX_PI_CTL0r_fields, 5116 #else 5117 0, 5118 #endif 5119 #endif 5120 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5121 PHYMOD_SYMBOL_FLAG_REGISTER, 5122 "TX_PI_CTL0r", 5123 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5124 "TX_PI_COM_CONTROL_0", 5125 NULL, 5126 #endif 5127 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5128 0x2000, /* 8192 */ 5129 0, 5130 #endif 5131 }, 5132 { 5133 BCMI_EAGLE_XGXS_TX_PI_CTL1r, 5134 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5135 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 5136 BCMI_EAGLE_XGXS_TX_PI_CTL1r_fields, 5137 #else 5138 0, 5139 #endif 5140 #endif 5141 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5142 PHYMOD_SYMBOL_FLAG_REGISTER, 5143 "TX_PI_CTL1r", 5144 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5145 "TX_PI_COM_CONTROL_1", 5146 NULL, 5147 #endif 5148 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5149 0x0, /* 0 */ 5150 0, 5151 #endif 5152 }, 5153 { 5154 BCMI_EAGLE_XGXS_TX_PI_CTL2r, 5155 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5156 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 5157 BCMI_EAGLE_XGXS_TX_PI_CTL2r_fields, 5158 #else 5159 0, 5160 #endif 5161 #endif 5162 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5163 PHYMOD_SYMBOL_FLAG_REGISTER, 5164 "TX_PI_CTL2r", 5165 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5166 "TX_PI_COM_CONTROL_2", 5167 NULL, 5168 #endif 5169 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5170 0x0, /* 0 */ 5171 0, 5172 #endif 5173 }, 5174 { 5175 BCMI_EAGLE_XGXS_TX_PI_CTL3r, 5176 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5177 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 5178 BCMI_EAGLE_XGXS_TX_PI_CTL3r_fields, 5179 #else 5180 0, 5181 #endif 5182 #endif 5183 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5184 PHYMOD_SYMBOL_FLAG_REGISTER, 5185 "TX_PI_CTL3r", 5186 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5187 "TX_PI_COM_CONTROL_3", 5188 NULL, 5189 #endif 5190 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5191 0x100, /* 256 */ 5192 0, 5193 #endif 5194 }, 5195 { 5196 BCMI_EAGLE_XGXS_TX_PI_CTL4r, 5197 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5198 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 5199 BCMI_EAGLE_XGXS_TX_PI_CTL4r_fields, 5200 #else 5201 0, 5202 #endif 5203 #endif 5204 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5205 PHYMOD_SYMBOL_FLAG_REGISTER, 5206 "TX_PI_CTL4r", 5207 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5208 "TX_PI_COM_CONTROL_4", 5209 NULL, 5210 #endif 5211 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5212 0x4, /* 4 */ 5213 0, 5214 #endif 5215 }, 5216 { 5217 BCMI_EAGLE_XGXS_TX_PI_CTL6r, 5218 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5219 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 5220 BCMI_EAGLE_XGXS_TX_PI_CTL6r_fields, 5221 #else 5222 0, 5223 #endif 5224 #endif 5225 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5226 PHYMOD_SYMBOL_FLAG_REGISTER, 5227 "TX_PI_CTL6r", 5228 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5229 "TX_PI_COM_CONTROL_6", 5230 NULL, 5231 #endif 5232 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5233 0x0, /* 0 */ 5234 0, 5235 #endif 5236 }, 5237 { 5238 BCMI_EAGLE_XGXS_TX_PI_STS0r, 5239 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5240 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 5241 BCMI_EAGLE_XGXS_TX_PI_STS0r_fields, 5242 #else 5243 0, 5244 #endif 5245 #endif 5246 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5247 PHYMOD_SYMBOL_FLAG_REGISTER, 5248 "TX_PI_STS0r", 5249 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5250 "TX_PI_COM_STATUS_0", 5251 NULL, 5252 #endif 5253 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5254 0x0, /* 0 */ 5255 0, 5256 #endif 5257 }, 5258 { 5259 BCMI_EAGLE_XGXS_TX_PI_STS1r, 5260 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5261 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 5262 BCMI_EAGLE_XGXS_TX_PI_STS1r_fields, 5263 #else 5264 0, 5265 #endif 5266 #endif 5267 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5268 PHYMOD_SYMBOL_FLAG_REGISTER, 5269 "TX_PI_STS1r", 5270 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5271 "TX_PI_COM_STATUS_1", 5272 NULL, 5273 #endif 5274 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5275 0x0, /* 0 */ 5276 0, 5277 #endif 5278 }, 5279 { 5280 BCMI_EAGLE_XGXS_TX_PI_STS2r, 5281 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5282 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 5283 BCMI_EAGLE_XGXS_TX_PI_STS2r_fields, 5284 #else 5285 0, 5286 #endif 5287 #endif 5288 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5289 PHYMOD_SYMBOL_FLAG_REGISTER, 5290 "TX_PI_STS2r", 5291 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5292 "TX_PI_COM_STATUS_2", 5293 NULL, 5294 #endif 5295 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5296 0x0, /* 0 */ 5297 0, 5298 #endif 5299 }, 5300 { 5301 BCMI_EAGLE_XGXS_TX_PI_STS3r, 5302 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5303 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 5304 BCMI_EAGLE_XGXS_TX_PI_STS3r_fields, 5305 #else 5306 0, 5307 #endif 5308 #endif 5309 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5310 PHYMOD_SYMBOL_FLAG_REGISTER, 5311 "TX_PI_STS3r", 5312 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5313 "TX_PI_COM_STATUS_3", 5314 NULL, 5315 #endif 5316 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5317 0x0, /* 0 */ 5318 0, 5319 #endif 5320 }, 5321 { 5322 BCMI_EAGLE_XGXS_CKRST_OSR_MODE_CTLr, 5323 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5324 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 5325 BCMI_EAGLE_XGXS_CKRST_OSR_MODE_CTLr_fields, 5326 #else 5327 0, 5328 #endif 5329 #endif 5330 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5331 PHYMOD_SYMBOL_FLAG_REGISTER, 5332 "CKRST_OSR_MODE_CTLr", 5333 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5334 "CKRST_CTRL_OSR_MODE_CONTROL", 5335 NULL, 5336 #endif 5337 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5338 0x0, /* 0 */ 5339 0, 5340 #endif 5341 }, 5342 { 5343 BCMI_EAGLE_XGXS_CKRST_LN_CLK_RST_N_PWRDWN_CTLr, 5344 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5345 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 5346 BCMI_EAGLE_XGXS_CKRST_LN_CLK_RST_N_PWRDWN_CTLr_fields, 5347 #else 5348 0, 5349 #endif 5350 #endif 5351 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5352 PHYMOD_SYMBOL_FLAG_REGISTER, 5353 "CKRST_LN_CLK_RST_N_PWRDWN_CTLr", 5354 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5355 "CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL", 5356 NULL, 5357 #endif 5358 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5359 0x0, /* 0 */ 5360 0, 5361 #endif 5362 }, 5363 { 5364 BCMI_EAGLE_XGXS_CKRST_LN_AFE_RST_PWRDWN_CTL_CTLr, 5365 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5366 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 5367 BCMI_EAGLE_XGXS_CKRST_LN_AFE_RST_PWRDWN_CTL_CTLr_fields, 5368 #else 5369 0, 5370 #endif 5371 #endif 5372 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5373 PHYMOD_SYMBOL_FLAG_REGISTER, 5374 "CKRST_LN_AFE_RST_PWRDWN_CTL_CTLr", 5375 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5376 "CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL", 5377 NULL, 5378 #endif 5379 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5380 0x0, /* 0 */ 5381 0, 5382 #endif 5383 }, 5384 { 5385 BCMI_EAGLE_XGXS_CKRST_LN_RST_N_PWRDN_PIN_KILL_CTLr, 5386 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5387 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 5388 BCMI_EAGLE_XGXS_CKRST_LN_RST_N_PWRDN_PIN_KILL_CTLr_fields, 5389 #else 5390 0, 5391 #endif 5392 #endif 5393 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5394 PHYMOD_SYMBOL_FLAG_REGISTER, 5395 "CKRST_LN_RST_N_PWRDN_PIN_KILL_CTLr", 5396 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5397 "CKRST_CTRL_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL", 5398 NULL, 5399 #endif 5400 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5401 0x0, /* 0 */ 5402 0, 5403 #endif 5404 }, 5405 { 5406 BCMI_EAGLE_XGXS_CKRST_LN_DBG_RST_CTLr, 5407 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5408 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 5409 BCMI_EAGLE_XGXS_CKRST_LN_DBG_RST_CTLr_fields, 5410 #else 5411 0, 5412 #endif 5413 #endif 5414 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5415 PHYMOD_SYMBOL_FLAG_REGISTER, 5416 "CKRST_LN_DBG_RST_CTLr", 5417 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5418 "CKRST_CTRL_LANE_DEBUG_RESET_CONTROL", 5419 NULL, 5420 #endif 5421 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5422 0x303, /* 771 */ 5423 0, 5424 #endif 5425 }, 5426 { 5427 BCMI_EAGLE_XGXS_CKRST_UC_ACK_LN_CTLr, 5428 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5429 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 5430 BCMI_EAGLE_XGXS_CKRST_UC_ACK_LN_CTLr_fields, 5431 #else 5432 0, 5433 #endif 5434 #endif 5435 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5436 PHYMOD_SYMBOL_FLAG_REGISTER, 5437 "CKRST_UC_ACK_LN_CTLr", 5438 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5439 "CKRST_CTRL_UC_ACK_LANE_CONTROL", 5440 NULL, 5441 #endif 5442 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5443 0x0, /* 0 */ 5444 0, 5445 #endif 5446 }, 5447 { 5448 BCMI_EAGLE_XGXS_CKRST_LN_RST_OCC_CTLr, 5449 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5450 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 5451 BCMI_EAGLE_XGXS_CKRST_LN_RST_OCC_CTLr_fields, 5452 #else 5453 0, 5454 #endif 5455 #endif 5456 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5457 PHYMOD_SYMBOL_FLAG_REGISTER, 5458 "CKRST_LN_RST_OCC_CTLr", 5459 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5460 "CKRST_CTRL_LANE_REG_RESET_OCCURRED_CONTROL", 5461 NULL, 5462 #endif 5463 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5464 0x1, /* 1 */ 5465 0, 5466 #endif 5467 }, 5468 { 5469 BCMI_EAGLE_XGXS_CKRST_CLK_N_RST_DBG_CTLr, 5470 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5471 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 5472 BCMI_EAGLE_XGXS_CKRST_CLK_N_RST_DBG_CTLr_fields, 5473 #else 5474 0, 5475 #endif 5476 #endif 5477 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5478 PHYMOD_SYMBOL_FLAG_REGISTER, 5479 "CKRST_CLK_N_RST_DBG_CTLr", 5480 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5481 "CKRST_CTRL_CLOCK_N_RESET_DEBUG_CONTROL", 5482 NULL, 5483 #endif 5484 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5485 0x0, /* 0 */ 5486 0, 5487 #endif 5488 }, 5489 { 5490 BCMI_EAGLE_XGXS_CKRST_PMD_LN_MODE_STSr, 5491 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5492 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 5493 BCMI_EAGLE_XGXS_CKRST_PMD_LN_MODE_STSr_fields, 5494 #else 5495 0, 5496 #endif 5497 #endif 5498 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5499 PHYMOD_SYMBOL_FLAG_REGISTER, 5500 "CKRST_PMD_LN_MODE_STSr", 5501 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5502 "CKRST_CTRL_PMD_LANE_MODE_STATUS", 5503 NULL, 5504 #endif 5505 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5506 0x0, /* 0 */ 5507 0, 5508 #endif 5509 }, 5510 { 5511 BCMI_EAGLE_XGXS_CKRST_LN_DP_RST_ST_STSr, 5512 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5513 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 5514 BCMI_EAGLE_XGXS_CKRST_LN_DP_RST_ST_STSr_fields, 5515 #else 5516 0, 5517 #endif 5518 #endif 5519 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5520 PHYMOD_SYMBOL_FLAG_REGISTER, 5521 "CKRST_LN_DP_RST_ST_STSr", 5522 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5523 "CKRST_CTRL_LANE_DP_RESET_STATE_STATUS", 5524 NULL, 5525 #endif 5526 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5527 0x7, /* 7 */ 5528 0, 5529 #endif 5530 }, 5531 { 5532 BCMI_EAGLE_XGXS_CKRST_LN_MCST_MASK_CTLr, 5533 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5534 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 5535 BCMI_EAGLE_XGXS_CKRST_LN_MCST_MASK_CTLr_fields, 5536 #else 5537 0, 5538 #endif 5539 #endif 5540 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5541 PHYMOD_SYMBOL_FLAG_REGISTER, 5542 "CKRST_LN_MCST_MASK_CTLr", 5543 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5544 "CKRST_CTRL_LANE_MULTICAST_MASK_CONTROL", 5545 NULL, 5546 #endif 5547 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5548 0x0, /* 0 */ 5549 0, 5550 #endif 5551 }, 5552 { 5553 BCMI_EAGLE_XGXS_CKRST_OSR_MODE_STSr, 5554 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5555 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 5556 BCMI_EAGLE_XGXS_CKRST_OSR_MODE_STSr_fields, 5557 #else 5558 0, 5559 #endif 5560 #endif 5561 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5562 PHYMOD_SYMBOL_FLAG_REGISTER, 5563 "CKRST_OSR_MODE_STSr", 5564 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5565 "CKRST_CTRL_OSR_MODE_STATUS", 5566 NULL, 5567 #endif 5568 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5569 0x0, /* 0 */ 5570 0, 5571 #endif 5572 }, 5573 { 5574 BCMI_EAGLE_XGXS_CKRST_OSR_MODE_PIN_STSr, 5575 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5576 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 5577 BCMI_EAGLE_XGXS_CKRST_OSR_MODE_PIN_STSr_fields, 5578 #else 5579 0, 5580 #endif 5581 #endif 5582 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5583 PHYMOD_SYMBOL_FLAG_REGISTER, 5584 "CKRST_OSR_MODE_PIN_STSr", 5585 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5586 "CKRST_CTRL_OSR_MODE_PIN_STATUS", 5587 NULL, 5588 #endif 5589 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5590 0x0, /* 0 */ 5591 0, 5592 #endif 5593 }, 5594 { 5595 BCMI_EAGLE_XGXS_CKRST_LN_S_RSTB_CTLr, 5596 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5597 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 5598 BCMI_EAGLE_XGXS_CKRST_LN_S_RSTB_CTLr_fields, 5599 #else 5600 0, 5601 #endif 5602 #endif 5603 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5604 PHYMOD_SYMBOL_FLAG_REGISTER, 5605 "CKRST_LN_S_RSTB_CTLr", 5606 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5607 "CKRST_CTRL_LN_S_RSTB_CONTROL", 5608 NULL, 5609 #endif 5610 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5611 0x1, /* 1 */ 5612 0, 5613 #endif 5614 }, 5615 { 5616 BCMI_EAGLE_XGXS_AMS_RX_CTL0r, 5617 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5618 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 5619 BCMI_EAGLE_XGXS_AMS_RX_CTL0r_fields, 5620 #else 5621 0, 5622 #endif 5623 #endif 5624 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5625 PHYMOD_SYMBOL_FLAG_REGISTER, 5626 "AMS_RX_CTL0r", 5627 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5628 "AMS_RX_CONTROL_0", 5629 NULL, 5630 #endif 5631 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5632 0x10, /* 16 */ 5633 0, 5634 #endif 5635 }, 5636 { 5637 BCMI_EAGLE_XGXS_AMS_RX_CTL1r, 5638 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5639 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 5640 BCMI_EAGLE_XGXS_AMS_RX_CTL1r_fields, 5641 #else 5642 0, 5643 #endif 5644 #endif 5645 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5646 PHYMOD_SYMBOL_FLAG_REGISTER, 5647 "AMS_RX_CTL1r", 5648 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5649 "AMS_RX_CONTROL_1", 5650 NULL, 5651 #endif 5652 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5653 0x0, /* 0 */ 5654 0, 5655 #endif 5656 }, 5657 { 5658 BCMI_EAGLE_XGXS_AMS_RX_CTL2r, 5659 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5660 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 5661 BCMI_EAGLE_XGXS_AMS_RX_CTL2r_fields, 5662 #else 5663 0, 5664 #endif 5665 #endif 5666 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5667 PHYMOD_SYMBOL_FLAG_REGISTER, 5668 "AMS_RX_CTL2r", 5669 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5670 "AMS_RX_CONTROL_2", 5671 NULL, 5672 #endif 5673 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5674 0x2800, /* 10240 */ 5675 0, 5676 #endif 5677 }, 5678 { 5679 BCMI_EAGLE_XGXS_AMS_RX_CTL3r, 5680 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5681 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 5682 BCMI_EAGLE_XGXS_AMS_RX_CTL3r_fields, 5683 #else 5684 0, 5685 #endif 5686 #endif 5687 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5688 PHYMOD_SYMBOL_FLAG_REGISTER, 5689 "AMS_RX_CTL3r", 5690 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5691 "AMS_RX_CONTROL_3", 5692 NULL, 5693 #endif 5694 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5695 0x0, /* 0 */ 5696 0, 5697 #endif 5698 }, 5699 { 5700 BCMI_EAGLE_XGXS_AMS_RX_CTL4r, 5701 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5702 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 5703 BCMI_EAGLE_XGXS_AMS_RX_CTL4r_fields, 5704 #else 5705 0, 5706 #endif 5707 #endif 5708 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5709 PHYMOD_SYMBOL_FLAG_REGISTER, 5710 "AMS_RX_CTL4r", 5711 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5712 "AMS_RX_CONTROL_4", 5713 NULL, 5714 #endif 5715 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5716 0x0, /* 0 */ 5717 0, 5718 #endif 5719 }, 5720 { 5721 BCMI_EAGLE_XGXS_AMS_RX_INTCTLr, 5722 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5723 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 5724 BCMI_EAGLE_XGXS_AMS_RX_INTCTLr_fields, 5725 #else 5726 0, 5727 #endif 5728 #endif 5729 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5730 PHYMOD_SYMBOL_FLAG_REGISTER, 5731 "AMS_RX_INTCTLr", 5732 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5733 "AMS_RX_INTCTRL", 5734 NULL, 5735 #endif 5736 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5737 0x0, /* 0 */ 5738 0, 5739 #endif 5740 }, 5741 { 5742 BCMI_EAGLE_XGXS_AMS_RX_STSr, 5743 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5744 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 5745 BCMI_EAGLE_XGXS_AMS_RX_STSr_fields, 5746 #else 5747 0, 5748 #endif 5749 #endif 5750 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5751 PHYMOD_SYMBOL_FLAG_REGISTER, 5752 "AMS_RX_STSr", 5753 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5754 "AMS_RX_STATUS", 5755 NULL, 5756 #endif 5757 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5758 0x8000, /* 32768 */ 5759 0, 5760 #endif 5761 }, 5762 { 5763 BCMI_EAGLE_XGXS_AMS_TX_CTL0r, 5764 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5765 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 5766 BCMI_EAGLE_XGXS_AMS_TX_CTL0r_fields, 5767 #else 5768 0, 5769 #endif 5770 #endif 5771 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5772 PHYMOD_SYMBOL_FLAG_REGISTER, 5773 "AMS_TX_CTL0r", 5774 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5775 "AMS_TX_CONTROL_0", 5776 NULL, 5777 #endif 5778 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5779 0x80, /* 128 */ 5780 0, 5781 #endif 5782 }, 5783 { 5784 BCMI_EAGLE_XGXS_AMS_TX_CTL1r, 5785 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5786 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 5787 BCMI_EAGLE_XGXS_AMS_TX_CTL1r_fields, 5788 #else 5789 0, 5790 #endif 5791 #endif 5792 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5793 PHYMOD_SYMBOL_FLAG_REGISTER, 5794 "AMS_TX_CTL1r", 5795 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5796 "AMS_TX_CONTROL_1", 5797 NULL, 5798 #endif 5799 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5800 0x0, /* 0 */ 5801 0, 5802 #endif 5803 }, 5804 { 5805 BCMI_EAGLE_XGXS_AMS_TX_CTL2r, 5806 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5807 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 5808 BCMI_EAGLE_XGXS_AMS_TX_CTL2r_fields, 5809 #else 5810 0, 5811 #endif 5812 #endif 5813 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5814 PHYMOD_SYMBOL_FLAG_REGISTER, 5815 "AMS_TX_CTL2r", 5816 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5817 "AMS_TX_CONTROL_2", 5818 NULL, 5819 #endif 5820 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5821 0xc, /* 12 */ 5822 0, 5823 #endif 5824 }, 5825 { 5826 BCMI_EAGLE_XGXS_AMS_TX_INTCTLr, 5827 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5828 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 5829 BCMI_EAGLE_XGXS_AMS_TX_INTCTLr_fields, 5830 #else 5831 0, 5832 #endif 5833 #endif 5834 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5835 PHYMOD_SYMBOL_FLAG_REGISTER, 5836 "AMS_TX_INTCTLr", 5837 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5838 "AMS_TX_INTCTRL", 5839 NULL, 5840 #endif 5841 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5842 0x0, /* 0 */ 5843 0, 5844 #endif 5845 }, 5846 { 5847 BCMI_EAGLE_XGXS_AMS_TX_STSr, 5848 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5849 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 5850 BCMI_EAGLE_XGXS_AMS_TX_STSr_fields, 5851 #else 5852 0, 5853 #endif 5854 #endif 5855 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5856 PHYMOD_SYMBOL_FLAG_REGISTER, 5857 "AMS_TX_STSr", 5858 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5859 "AMS_TX_STATUS", 5860 NULL, 5861 #endif 5862 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5863 0x0, /* 0 */ 5864 0, 5865 #endif 5866 }, 5867 { 5868 BCMI_EAGLE_XGXS_AMS_CTL0r, 5869 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5870 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 5871 BCMI_EAGLE_XGXS_AMS_CTL0r_fields, 5872 #else 5873 0, 5874 #endif 5875 #endif 5876 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5877 PHYMOD_SYMBOL_FLAG_REGISTER, 5878 "AMS_CTL0r", 5879 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5880 "AMS_COM_CONTROL_0", 5881 NULL, 5882 #endif 5883 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5884 0x0, /* 0 */ 5885 0, 5886 #endif 5887 }, 5888 { 5889 BCMI_EAGLE_XGXS_AMS_CTL1r, 5890 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5891 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 5892 BCMI_EAGLE_XGXS_AMS_CTL1r_fields, 5893 #else 5894 0, 5895 #endif 5896 #endif 5897 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5898 PHYMOD_SYMBOL_FLAG_REGISTER, 5899 "AMS_CTL1r", 5900 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5901 "AMS_COM_CONTROL_1", 5902 NULL, 5903 #endif 5904 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5905 0x8001, /* 32769 */ 5906 0, 5907 #endif 5908 }, 5909 { 5910 BCMI_EAGLE_XGXS_AMS_CTL2r, 5911 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5912 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 5913 BCMI_EAGLE_XGXS_AMS_CTL2r_fields, 5914 #else 5915 0, 5916 #endif 5917 #endif 5918 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5919 PHYMOD_SYMBOL_FLAG_REGISTER, 5920 "AMS_CTL2r", 5921 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5922 "AMS_COM_CONTROL_2", 5923 NULL, 5924 #endif 5925 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5926 0x16, /* 22 */ 5927 0, 5928 #endif 5929 }, 5930 { 5931 BCMI_EAGLE_XGXS_AMS_CTL3r, 5932 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5933 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 5934 BCMI_EAGLE_XGXS_AMS_CTL3r_fields, 5935 #else 5936 0, 5937 #endif 5938 #endif 5939 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5940 PHYMOD_SYMBOL_FLAG_REGISTER, 5941 "AMS_CTL3r", 5942 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5943 "AMS_COM_CONTROL_3", 5944 NULL, 5945 #endif 5946 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5947 0x0, /* 0 */ 5948 0, 5949 #endif 5950 }, 5951 { 5952 BCMI_EAGLE_XGXS_AMS_CTL4r, 5953 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5954 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 5955 BCMI_EAGLE_XGXS_AMS_CTL4r_fields, 5956 #else 5957 0, 5958 #endif 5959 #endif 5960 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5961 PHYMOD_SYMBOL_FLAG_REGISTER, 5962 "AMS_CTL4r", 5963 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5964 "AMS_COM_CONTROL_4", 5965 NULL, 5966 #endif 5967 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5968 0x77, /* 119 */ 5969 0, 5970 #endif 5971 }, 5972 { 5973 BCMI_EAGLE_XGXS_AMS_CTL5r, 5974 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5975 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 5976 BCMI_EAGLE_XGXS_AMS_CTL5r_fields, 5977 #else 5978 0, 5979 #endif 5980 #endif 5981 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 5982 PHYMOD_SYMBOL_FLAG_REGISTER, 5983 "AMS_CTL5r", 5984 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 5985 "AMS_COM_CONTROL_5", 5986 NULL, 5987 #endif 5988 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 5989 0x7bc0, /* 31680 */ 5990 0, 5991 #endif 5992 }, 5993 { 5994 BCMI_EAGLE_XGXS_AMS_CTL6r, 5995 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 5996 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 5997 BCMI_EAGLE_XGXS_AMS_CTL6r_fields, 5998 #else 5999 0, 6000 #endif 6001 #endif 6002 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6003 PHYMOD_SYMBOL_FLAG_REGISTER, 6004 "AMS_CTL6r", 6005 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6006 "AMS_COM_CONTROL_6", 6007 NULL, 6008 #endif 6009 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6010 0x45c0, /* 17856 */ 6011 0, 6012 #endif 6013 }, 6014 { 6015 BCMI_EAGLE_XGXS_AMS_CTL7r, 6016 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6017 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 6018 BCMI_EAGLE_XGXS_AMS_CTL7r_fields, 6019 #else 6020 0, 6021 #endif 6022 #endif 6023 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6024 PHYMOD_SYMBOL_FLAG_REGISTER, 6025 "AMS_CTL7r", 6026 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6027 "AMS_COM_CONTROL_7", 6028 NULL, 6029 #endif 6030 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6031 0x0, /* 0 */ 6032 0, 6033 #endif 6034 }, 6035 { 6036 BCMI_EAGLE_XGXS_AMS_CTL8r, 6037 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6038 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 6039 BCMI_EAGLE_XGXS_AMS_CTL8r_fields, 6040 #else 6041 0, 6042 #endif 6043 #endif 6044 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6045 PHYMOD_SYMBOL_FLAG_REGISTER, 6046 "AMS_CTL8r", 6047 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6048 "AMS_COM_CONTROL_8", 6049 NULL, 6050 #endif 6051 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6052 0x0, /* 0 */ 6053 0, 6054 #endif 6055 }, 6056 { 6057 BCMI_EAGLE_XGXS_AMS_INTCTLr, 6058 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6059 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 6060 BCMI_EAGLE_XGXS_AMS_INTCTLr_fields, 6061 #else 6062 0, 6063 #endif 6064 #endif 6065 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6066 PHYMOD_SYMBOL_FLAG_REGISTER, 6067 "AMS_INTCTLr", 6068 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6069 "AMS_COM_INTCTRL", 6070 NULL, 6071 #endif 6072 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6073 0x0, /* 0 */ 6074 0, 6075 #endif 6076 }, 6077 { 6078 BCMI_EAGLE_XGXS_AMS_STSr, 6079 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6080 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 6081 BCMI_EAGLE_XGXS_AMS_STSr_fields, 6082 #else 6083 0, 6084 #endif 6085 #endif 6086 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6087 PHYMOD_SYMBOL_FLAG_REGISTER, 6088 "AMS_STSr", 6089 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6090 "AMS_COM_STATUS", 6091 NULL, 6092 #endif 6093 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6094 0x300a, /* 12298 */ 6095 0, 6096 #endif 6097 }, 6098 { 6099 BCMI_EAGLE_XGXS_SIGDET_CTL0r, 6100 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6101 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 6102 BCMI_EAGLE_XGXS_SIGDET_CTL0r_fields, 6103 #else 6104 0, 6105 #endif 6106 #endif 6107 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6108 PHYMOD_SYMBOL_FLAG_REGISTER, 6109 "SIGDET_CTL0r", 6110 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6111 "SIGDET_CTRL_0", 6112 NULL, 6113 #endif 6114 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6115 0x1109, /* 4361 */ 6116 0, 6117 #endif 6118 }, 6119 { 6120 BCMI_EAGLE_XGXS_SIGDET_CTL1r, 6121 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6122 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 6123 BCMI_EAGLE_XGXS_SIGDET_CTL1r_fields, 6124 #else 6125 0, 6126 #endif 6127 #endif 6128 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6129 PHYMOD_SYMBOL_FLAG_REGISTER, 6130 "SIGDET_CTL1r", 6131 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6132 "SIGDET_CTRL_1", 6133 NULL, 6134 #endif 6135 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6136 0xa008, /* 40968 */ 6137 0, 6138 #endif 6139 }, 6140 { 6141 BCMI_EAGLE_XGXS_SIGDET_CTL2r, 6142 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6143 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 6144 BCMI_EAGLE_XGXS_SIGDET_CTL2r_fields, 6145 #else 6146 0, 6147 #endif 6148 #endif 6149 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6150 PHYMOD_SYMBOL_FLAG_REGISTER, 6151 "SIGDET_CTL2r", 6152 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6153 "SIGDET_CTRL_2", 6154 NULL, 6155 #endif 6156 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6157 0x3f22, /* 16162 */ 6158 0, 6159 #endif 6160 }, 6161 { 6162 BCMI_EAGLE_XGXS_SIGDET_STS0r, 6163 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6164 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 6165 BCMI_EAGLE_XGXS_SIGDET_STS0r_fields, 6166 #else 6167 0, 6168 #endif 6169 #endif 6170 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6171 PHYMOD_SYMBOL_FLAG_REGISTER, 6172 "SIGDET_STS0r", 6173 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6174 "SIGDET_STATUS_0", 6175 NULL, 6176 #endif 6177 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6178 0x200, /* 512 */ 6179 0, 6180 #endif 6181 }, 6182 { 6183 BCMI_EAGLE_XGXS_TLB_RX_PRBS_CHK_CNT_CFGr, 6184 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6185 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 6186 BCMI_EAGLE_XGXS_TLB_RX_PRBS_CHK_CNT_CFGr_fields, 6187 #else 6188 0, 6189 #endif 6190 #endif 6191 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6192 PHYMOD_SYMBOL_FLAG_REGISTER, 6193 "TLB_RX_PRBS_CHK_CNT_CFGr", 6194 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6195 "TLB_RX_PRBS_CHK_CNT_CONFIG", 6196 NULL, 6197 #endif 6198 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6199 0x602, /* 1538 */ 6200 0, 6201 #endif 6202 }, 6203 { 6204 BCMI_EAGLE_XGXS_TLB_RX_PRBS_CHK_CFGr, 6205 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6206 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 6207 BCMI_EAGLE_XGXS_TLB_RX_PRBS_CHK_CFGr_fields, 6208 #else 6209 0, 6210 #endif 6211 #endif 6212 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6213 PHYMOD_SYMBOL_FLAG_REGISTER, 6214 "TLB_RX_PRBS_CHK_CFGr", 6215 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6216 "TLB_RX_PRBS_CHK_CONFIG", 6217 NULL, 6218 #endif 6219 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6220 0xa, /* 10 */ 6221 0, 6222 #endif 6223 }, 6224 { 6225 BCMI_EAGLE_XGXS_TLB_RX_DIG_LPBK_CFGr, 6226 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6227 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 6228 BCMI_EAGLE_XGXS_TLB_RX_DIG_LPBK_CFGr_fields, 6229 #else 6230 0, 6231 #endif 6232 #endif 6233 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6234 PHYMOD_SYMBOL_FLAG_REGISTER, 6235 "TLB_RX_DIG_LPBK_CFGr", 6236 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6237 "TLB_RX_DIG_LPBK_CONFIG", 6238 NULL, 6239 #endif 6240 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6241 0x6, /* 6 */ 6242 0, 6243 #endif 6244 }, 6245 { 6246 BCMI_EAGLE_XGXS_TLB_RX_TLB_RX_MISC_CFGr, 6247 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6248 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 6249 BCMI_EAGLE_XGXS_TLB_RX_TLB_RX_MISC_CFGr_fields, 6250 #else 6251 0, 6252 #endif 6253 #endif 6254 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6255 PHYMOD_SYMBOL_FLAG_REGISTER, 6256 "TLB_RX_TLB_RX_MISC_CFGr", 6257 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6258 "TLB_RX_TLB_RX_MISC_CONFIG", 6259 NULL, 6260 #endif 6261 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6262 0x0, /* 0 */ 6263 0, 6264 #endif 6265 }, 6266 { 6267 BCMI_EAGLE_XGXS_TLB_RX_PRBS_CHK_EN_TMR_CTLr, 6268 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6269 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 6270 BCMI_EAGLE_XGXS_TLB_RX_PRBS_CHK_EN_TMR_CTLr_fields, 6271 #else 6272 0, 6273 #endif 6274 #endif 6275 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6276 PHYMOD_SYMBOL_FLAG_REGISTER, 6277 "TLB_RX_PRBS_CHK_EN_TMR_CTLr", 6278 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6279 "TLB_RX_PRBS_CHK_EN_TIMER_CONTROL", 6280 NULL, 6281 #endif 6282 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6283 0x0, /* 0 */ 6284 0, 6285 #endif 6286 }, 6287 { 6288 BCMI_EAGLE_XGXS_TLB_RX_DIG_LPBK_PD_STSr, 6289 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6290 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 6291 BCMI_EAGLE_XGXS_TLB_RX_DIG_LPBK_PD_STSr_fields, 6292 #else 6293 0, 6294 #endif 6295 #endif 6296 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6297 PHYMOD_SYMBOL_FLAG_REGISTER, 6298 "TLB_RX_DIG_LPBK_PD_STSr", 6299 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6300 "TLB_RX_DIG_LPBK_PD_STATUS", 6301 NULL, 6302 #endif 6303 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6304 0x2, /* 2 */ 6305 0, 6306 #endif 6307 }, 6308 { 6309 BCMI_EAGLE_XGXS_TLB_RX_PRBS_CHK_LOCK_STSr, 6310 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6311 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 6312 BCMI_EAGLE_XGXS_TLB_RX_PRBS_CHK_LOCK_STSr_fields, 6313 #else 6314 0, 6315 #endif 6316 #endif 6317 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6318 PHYMOD_SYMBOL_FLAG_REGISTER, 6319 "TLB_RX_PRBS_CHK_LOCK_STSr", 6320 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6321 "TLB_RX_PRBS_CHK_LOCK_STATUS", 6322 NULL, 6323 #endif 6324 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6325 0x0, /* 0 */ 6326 0, 6327 #endif 6328 }, 6329 { 6330 BCMI_EAGLE_XGXS_TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr, 6331 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6332 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 6333 BCMI_EAGLE_XGXS_TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr_fields, 6334 #else 6335 0, 6336 #endif 6337 #endif 6338 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6339 PHYMOD_SYMBOL_FLAG_REGISTER, 6340 "TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr", 6341 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6342 "TLB_RX_PRBS_CHK_ERR_CNT_MSB_STATUS", 6343 NULL, 6344 #endif 6345 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6346 0x8000, /* 32768 */ 6347 0, 6348 #endif 6349 }, 6350 { 6351 BCMI_EAGLE_XGXS_TLB_RX_PRBS_CHK_ERR_CNT_LSB_STSr, 6352 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6353 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 6354 BCMI_EAGLE_XGXS_TLB_RX_PRBS_CHK_ERR_CNT_LSB_STSr_fields, 6355 #else 6356 0, 6357 #endif 6358 #endif 6359 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6360 PHYMOD_SYMBOL_FLAG_REGISTER, 6361 "TLB_RX_PRBS_CHK_ERR_CNT_LSB_STSr", 6362 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6363 "TLB_RX_PRBS_CHK_ERR_CNT_LSB_STATUS", 6364 NULL, 6365 #endif 6366 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6367 0x0, /* 0 */ 6368 0, 6369 #endif 6370 }, 6371 { 6372 BCMI_EAGLE_XGXS_TLB_RX_PMD_RX_LOCK_STSr, 6373 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6374 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 6375 BCMI_EAGLE_XGXS_TLB_RX_PMD_RX_LOCK_STSr_fields, 6376 #else 6377 0, 6378 #endif 6379 #endif 6380 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6381 PHYMOD_SYMBOL_FLAG_REGISTER, 6382 "TLB_RX_PMD_RX_LOCK_STSr", 6383 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6384 "TLB_RX_PMD_RX_LOCK_STATUS", 6385 NULL, 6386 #endif 6387 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6388 0x0, /* 0 */ 6389 0, 6390 #endif 6391 }, 6392 { 6393 BCMI_EAGLE_XGXS_TLB_TX_PATGEN_CFGr, 6394 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6395 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 6396 BCMI_EAGLE_XGXS_TLB_TX_PATGEN_CFGr_fields, 6397 #else 6398 0, 6399 #endif 6400 #endif 6401 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6402 PHYMOD_SYMBOL_FLAG_REGISTER, 6403 "TLB_TX_PATGEN_CFGr", 6404 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6405 "TLB_TX_PATT_GEN_CONFIG", 6406 NULL, 6407 #endif 6408 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6409 0xb000, /* 45056 */ 6410 0, 6411 #endif 6412 }, 6413 { 6414 BCMI_EAGLE_XGXS_TLB_TX_PRBS_GEN_CFGr, 6415 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6416 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 6417 BCMI_EAGLE_XGXS_TLB_TX_PRBS_GEN_CFGr_fields, 6418 #else 6419 0, 6420 #endif 6421 #endif 6422 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6423 PHYMOD_SYMBOL_FLAG_REGISTER, 6424 "TLB_TX_PRBS_GEN_CFGr", 6425 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6426 "TLB_TX_PRBS_GEN_CONFIG", 6427 NULL, 6428 #endif 6429 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6430 0xa, /* 10 */ 6431 0, 6432 #endif 6433 }, 6434 { 6435 BCMI_EAGLE_XGXS_TLB_TX_RMT_LPBK_CFGr, 6436 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6437 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 6438 BCMI_EAGLE_XGXS_TLB_TX_RMT_LPBK_CFGr_fields, 6439 #else 6440 0, 6441 #endif 6442 #endif 6443 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6444 PHYMOD_SYMBOL_FLAG_REGISTER, 6445 "TLB_TX_RMT_LPBK_CFGr", 6446 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6447 "TLB_TX_RMT_LPBK_CONFIG", 6448 NULL, 6449 #endif 6450 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6451 0x2, /* 2 */ 6452 0, 6453 #endif 6454 }, 6455 { 6456 BCMI_EAGLE_XGXS_TLB_TX_TLB_TX_MISC_CFGr, 6457 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6458 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 6459 BCMI_EAGLE_XGXS_TLB_TX_TLB_TX_MISC_CFGr_fields, 6460 #else 6461 0, 6462 #endif 6463 #endif 6464 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6465 PHYMOD_SYMBOL_FLAG_REGISTER, 6466 "TLB_TX_TLB_TX_MISC_CFGr", 6467 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6468 "TLB_TX_TLB_TX_MISC_CONFIG", 6469 NULL, 6470 #endif 6471 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6472 0x0, /* 0 */ 6473 0, 6474 #endif 6475 }, 6476 { 6477 BCMI_EAGLE_XGXS_TLB_TX_TX_PI_LOOP_TIMING_CFGr, 6478 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6479 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 6480 BCMI_EAGLE_XGXS_TLB_TX_TX_PI_LOOP_TIMING_CFGr_fields, 6481 #else 6482 0, 6483 #endif 6484 #endif 6485 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6486 PHYMOD_SYMBOL_FLAG_REGISTER, 6487 "TLB_TX_TX_PI_LOOP_TIMING_CFGr", 6488 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6489 "TLB_TX_TX_PI_LOOP_TIMING_CONFIG", 6490 NULL, 6491 #endif 6492 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6493 0x0, /* 0 */ 6494 0, 6495 #endif 6496 }, 6497 { 6498 BCMI_EAGLE_XGXS_TLB_TX_RMT_LPBK_PD_STSr, 6499 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6500 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 6501 BCMI_EAGLE_XGXS_TLB_TX_RMT_LPBK_PD_STSr_fields, 6502 #else 6503 0, 6504 #endif 6505 #endif 6506 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6507 PHYMOD_SYMBOL_FLAG_REGISTER, 6508 "TLB_TX_RMT_LPBK_PD_STSr", 6509 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6510 "TLB_TX_RMT_LPBK_PD_STATUS", 6511 NULL, 6512 #endif 6513 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6514 0x2, /* 2 */ 6515 0, 6516 #endif 6517 }, 6518 { 6519 BCMI_EAGLE_XGXS_DIG_REVID0r, 6520 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6521 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 6522 BCMI_EAGLE_XGXS_DIG_REVID0r_fields, 6523 #else 6524 0, 6525 #endif 6526 #endif 6527 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6528 PHYMOD_SYMBOL_FLAG_REGISTER, 6529 "DIG_REVID0r", 6530 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6531 "DIG_COM_REVID0", 6532 NULL, 6533 #endif 6534 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6535 0x2da, /* 730 */ 6536 0, 6537 #endif 6538 }, 6539 { 6540 BCMI_EAGLE_XGXS_DIG_RST_CTL_PMDr, 6541 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6542 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 6543 BCMI_EAGLE_XGXS_DIG_RST_CTL_PMDr_fields, 6544 #else 6545 0, 6546 #endif 6547 #endif 6548 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6549 PHYMOD_SYMBOL_FLAG_REGISTER, 6550 "DIG_RST_CTL_PMDr", 6551 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6552 "DIG_COM_RESET_CONTROL_PMD", 6553 NULL, 6554 #endif 6555 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6556 0x1, /* 1 */ 6557 0, 6558 #endif 6559 }, 6560 { 6561 BCMI_EAGLE_XGXS_DIG_RST_CTL_CORE_DPr, 6562 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6563 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 6564 BCMI_EAGLE_XGXS_DIG_RST_CTL_CORE_DPr_fields, 6565 #else 6566 0, 6567 #endif 6568 #endif 6569 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6570 PHYMOD_SYMBOL_FLAG_REGISTER, 6571 "DIG_RST_CTL_CORE_DPr", 6572 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6573 "DIG_COM_RESET_CONTROL_CORE_DP", 6574 NULL, 6575 #endif 6576 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6577 0x4000, /* 16384 */ 6578 0, 6579 #endif 6580 }, 6581 { 6582 BCMI_EAGLE_XGXS_DIG_CORE_MCST_MASK_CTLr, 6583 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6584 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 6585 BCMI_EAGLE_XGXS_DIG_CORE_MCST_MASK_CTLr_fields, 6586 #else 6587 0, 6588 #endif 6589 #endif 6590 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6591 PHYMOD_SYMBOL_FLAG_REGISTER, 6592 "DIG_CORE_MCST_MASK_CTLr", 6593 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6594 "DIG_COM_CORE_MULTICAST_MASK_CONRTOL", 6595 NULL, 6596 #endif 6597 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6598 0x0, /* 0 */ 6599 0, 6600 #endif 6601 }, 6602 { 6603 BCMI_EAGLE_XGXS_DIG_TOP_USER_CTL0r, 6604 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6605 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 6606 BCMI_EAGLE_XGXS_DIG_TOP_USER_CTL0r_fields, 6607 #else 6608 0, 6609 #endif 6610 #endif 6611 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6612 PHYMOD_SYMBOL_FLAG_REGISTER, 6613 "DIG_TOP_USER_CTL0r", 6614 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6615 "DIG_COM_TOP_USER_CONTROL_0", 6616 NULL, 6617 #endif 6618 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6619 0x271, /* 625 */ 6620 0, 6621 #endif 6622 }, 6623 { 6624 BCMI_EAGLE_XGXS_DIG_UC_ACK_CORE_CTLr, 6625 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6626 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 6627 BCMI_EAGLE_XGXS_DIG_UC_ACK_CORE_CTLr_fields, 6628 #else 6629 0, 6630 #endif 6631 #endif 6632 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6633 PHYMOD_SYMBOL_FLAG_REGISTER, 6634 "DIG_UC_ACK_CORE_CTLr", 6635 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6636 "DIG_COM_UC_ACK_CORE_CONTROL", 6637 NULL, 6638 #endif 6639 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6640 0x0, /* 0 */ 6641 0, 6642 #endif 6643 }, 6644 { 6645 BCMI_EAGLE_XGXS_DIG_CORE_RST_OCC_CTLr, 6646 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6647 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 6648 BCMI_EAGLE_XGXS_DIG_CORE_RST_OCC_CTLr_fields, 6649 #else 6650 0, 6651 #endif 6652 #endif 6653 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6654 PHYMOD_SYMBOL_FLAG_REGISTER, 6655 "DIG_CORE_RST_OCC_CTLr", 6656 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6657 "DIG_COM_CORE_REG_RESET_OCCURRED_CONTROL", 6658 NULL, 6659 #endif 6660 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6661 0x1, /* 1 */ 6662 0, 6663 #endif 6664 }, 6665 { 6666 BCMI_EAGLE_XGXS_DIG_RST_SEQ_TMR_CTLr, 6667 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6668 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 6669 BCMI_EAGLE_XGXS_DIG_RST_SEQ_TMR_CTLr_fields, 6670 #else 6671 0, 6672 #endif 6673 #endif 6674 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6675 PHYMOD_SYMBOL_FLAG_REGISTER, 6676 "DIG_RST_SEQ_TMR_CTLr", 6677 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6678 "DIG_COM_RST_SEQ_TIMER_CONTROL", 6679 NULL, 6680 #endif 6681 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6682 0x8304, /* 33540 */ 6683 0, 6684 #endif 6685 }, 6686 { 6687 BCMI_EAGLE_XGXS_DIG_CORE_DP_RST_ST_STSr, 6688 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6689 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 6690 BCMI_EAGLE_XGXS_DIG_CORE_DP_RST_ST_STSr_fields, 6691 #else 6692 0, 6693 #endif 6694 #endif 6695 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6696 PHYMOD_SYMBOL_FLAG_REGISTER, 6697 "DIG_CORE_DP_RST_ST_STSr", 6698 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6699 "DIG_COM_CORE_DP_RESET_STATE_STATUS", 6700 NULL, 6701 #endif 6702 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6703 0x7, /* 7 */ 6704 0, 6705 #endif 6706 }, 6707 { 6708 BCMI_EAGLE_XGXS_DIG_PMD_CORE_MODE_STSr, 6709 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6710 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 6711 BCMI_EAGLE_XGXS_DIG_PMD_CORE_MODE_STSr_fields, 6712 #else 6713 0, 6714 #endif 6715 #endif 6716 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6717 PHYMOD_SYMBOL_FLAG_REGISTER, 6718 "DIG_PMD_CORE_MODE_STSr", 6719 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6720 "DIG_COM_PMD_CORE_MODE_STATUS", 6721 NULL, 6722 #endif 6723 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6724 0x0, /* 0 */ 6725 0, 6726 #endif 6727 }, 6728 { 6729 BCMI_EAGLE_XGXS_DIG_REVID1r, 6730 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6731 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 6732 BCMI_EAGLE_XGXS_DIG_REVID1r_fields, 6733 #else 6734 0, 6735 #endif 6736 #endif 6737 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6738 PHYMOD_SYMBOL_FLAG_REGISTER, 6739 "DIG_REVID1r", 6740 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6741 "DIG_COM_REVID1", 6742 NULL, 6743 #endif 6744 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6745 0x4038, /* 16440 */ 6746 0, 6747 #endif 6748 }, 6749 { 6750 BCMI_EAGLE_XGXS_DIG_TX_LN_MAP_0_1_2r, 6751 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6752 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 6753 BCMI_EAGLE_XGXS_DIG_TX_LN_MAP_0_1_2r_fields, 6754 #else 6755 0, 6756 #endif 6757 #endif 6758 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6759 PHYMOD_SYMBOL_FLAG_REGISTER, 6760 "DIG_TX_LN_MAP_0_1_2r", 6761 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6762 "DIG_COM_TX_LANE_MAP_0_1_2", 6763 NULL, 6764 #endif 6765 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6766 0x820, /* 2080 */ 6767 0, 6768 #endif 6769 }, 6770 { 6771 BCMI_EAGLE_XGXS_DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r, 6772 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6773 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 6774 BCMI_EAGLE_XGXS_DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r_fields, 6775 #else 6776 0, 6777 #endif 6778 #endif 6779 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6780 PHYMOD_SYMBOL_FLAG_REGISTER, 6781 "DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r", 6782 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6783 "DIG_COM_TX_LANE_MAP_3_N_LANE_ADDR_0_1", 6784 NULL, 6785 #endif 6786 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6787 0x403, /* 1027 */ 6788 0, 6789 #endif 6790 }, 6791 { 6792 BCMI_EAGLE_XGXS_DIG_LN_ADDR_2_3r, 6793 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6794 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 6795 BCMI_EAGLE_XGXS_DIG_LN_ADDR_2_3r_fields, 6796 #else 6797 0, 6798 #endif 6799 #endif 6800 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6801 PHYMOD_SYMBOL_FLAG_REGISTER, 6802 "DIG_LN_ADDR_2_3r", 6803 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6804 "DIG_COM_LANE_ADDR_2_3", 6805 NULL, 6806 #endif 6807 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6808 0x302, /* 770 */ 6809 0, 6810 #endif 6811 }, 6812 { 6813 BCMI_EAGLE_XGXS_DIG_REVID2r, 6814 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6815 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 6816 BCMI_EAGLE_XGXS_DIG_REVID2r_fields, 6817 #else 6818 0, 6819 #endif 6820 #endif 6821 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6822 PHYMOD_SYMBOL_FLAG_REGISTER, 6823 "DIG_REVID2r", 6824 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6825 "DIG_COM_REVID2", 6826 NULL, 6827 #endif 6828 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6829 0x0, /* 0 */ 6830 0, 6831 #endif 6832 }, 6833 { 6834 BCMI_EAGLE_XGXS_PATGEN_SEQ0r, 6835 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6836 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 6837 BCMI_EAGLE_XGXS_PATGEN_SEQ0r_fields, 6838 #else 6839 0, 6840 #endif 6841 #endif 6842 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6843 PHYMOD_SYMBOL_FLAG_REGISTER, 6844 "PATGEN_SEQ0r", 6845 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6846 "PATT_GEN_COM_SEQ_0", 6847 NULL, 6848 #endif 6849 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6850 0xff00, /* 65280 */ 6851 0, 6852 #endif 6853 }, 6854 { 6855 BCMI_EAGLE_XGXS_PATGEN_SEQ1r, 6856 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6857 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 6858 BCMI_EAGLE_XGXS_PATGEN_SEQ1r_fields, 6859 #else 6860 0, 6861 #endif 6862 #endif 6863 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6864 PHYMOD_SYMBOL_FLAG_REGISTER, 6865 "PATGEN_SEQ1r", 6866 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6867 "PATT_GEN_COM_SEQ_1", 6868 NULL, 6869 #endif 6870 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6871 0xff00, /* 65280 */ 6872 0, 6873 #endif 6874 }, 6875 { 6876 BCMI_EAGLE_XGXS_PATGEN_SEQ2r, 6877 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6878 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 6879 BCMI_EAGLE_XGXS_PATGEN_SEQ2r_fields, 6880 #else 6881 0, 6882 #endif 6883 #endif 6884 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6885 PHYMOD_SYMBOL_FLAG_REGISTER, 6886 "PATGEN_SEQ2r", 6887 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6888 "PATT_GEN_COM_SEQ_2", 6889 NULL, 6890 #endif 6891 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6892 0xff00, /* 65280 */ 6893 0, 6894 #endif 6895 }, 6896 { 6897 BCMI_EAGLE_XGXS_PATGEN_SEQ3r, 6898 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6899 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 6900 BCMI_EAGLE_XGXS_PATGEN_SEQ3r_fields, 6901 #else 6902 0, 6903 #endif 6904 #endif 6905 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6906 PHYMOD_SYMBOL_FLAG_REGISTER, 6907 "PATGEN_SEQ3r", 6908 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6909 "PATT_GEN_COM_SEQ_3", 6910 NULL, 6911 #endif 6912 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6913 0xff00, /* 65280 */ 6914 0, 6915 #endif 6916 }, 6917 { 6918 BCMI_EAGLE_XGXS_PATGEN_SEQ4r, 6919 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6920 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 6921 BCMI_EAGLE_XGXS_PATGEN_SEQ4r_fields, 6922 #else 6923 0, 6924 #endif 6925 #endif 6926 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6927 PHYMOD_SYMBOL_FLAG_REGISTER, 6928 "PATGEN_SEQ4r", 6929 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6930 "PATT_GEN_COM_SEQ_4", 6931 NULL, 6932 #endif 6933 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6934 0xff00, /* 65280 */ 6935 0, 6936 #endif 6937 }, 6938 { 6939 BCMI_EAGLE_XGXS_PATGEN_SEQ5r, 6940 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6941 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 6942 BCMI_EAGLE_XGXS_PATGEN_SEQ5r_fields, 6943 #else 6944 0, 6945 #endif 6946 #endif 6947 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6948 PHYMOD_SYMBOL_FLAG_REGISTER, 6949 "PATGEN_SEQ5r", 6950 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6951 "PATT_GEN_COM_SEQ_5", 6952 NULL, 6953 #endif 6954 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6955 0xff00, /* 65280 */ 6956 0, 6957 #endif 6958 }, 6959 { 6960 BCMI_EAGLE_XGXS_PATGEN_SEQ6r, 6961 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6962 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 6963 BCMI_EAGLE_XGXS_PATGEN_SEQ6r_fields, 6964 #else 6965 0, 6966 #endif 6967 #endif 6968 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6969 PHYMOD_SYMBOL_FLAG_REGISTER, 6970 "PATGEN_SEQ6r", 6971 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6972 "PATT_GEN_COM_SEQ_6", 6973 NULL, 6974 #endif 6975 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6976 0xff00, /* 65280 */ 6977 0, 6978 #endif 6979 }, 6980 { 6981 BCMI_EAGLE_XGXS_PATGEN_SEQ7r, 6982 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 6983 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 6984 BCMI_EAGLE_XGXS_PATGEN_SEQ7r_fields, 6985 #else 6986 0, 6987 #endif 6988 #endif 6989 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 6990 PHYMOD_SYMBOL_FLAG_REGISTER, 6991 "PATGEN_SEQ7r", 6992 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 6993 "PATT_GEN_COM_SEQ_7", 6994 NULL, 6995 #endif 6996 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 6997 0xff00, /* 65280 */ 6998 0, 6999 #endif 7000 }, 7001 { 7002 BCMI_EAGLE_XGXS_PATGEN_SEQ8r, 7003 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7004 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 7005 BCMI_EAGLE_XGXS_PATGEN_SEQ8r_fields, 7006 #else 7007 0, 7008 #endif 7009 #endif 7010 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7011 PHYMOD_SYMBOL_FLAG_REGISTER, 7012 "PATGEN_SEQ8r", 7013 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7014 "PATT_GEN_COM_SEQ_8", 7015 NULL, 7016 #endif 7017 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7018 0xff00, /* 65280 */ 7019 0, 7020 #endif 7021 }, 7022 { 7023 BCMI_EAGLE_XGXS_PATGEN_SEQ9r, 7024 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7025 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 7026 BCMI_EAGLE_XGXS_PATGEN_SEQ9r_fields, 7027 #else 7028 0, 7029 #endif 7030 #endif 7031 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7032 PHYMOD_SYMBOL_FLAG_REGISTER, 7033 "PATGEN_SEQ9r", 7034 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7035 "PATT_GEN_COM_SEQ_9", 7036 NULL, 7037 #endif 7038 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7039 0xff00, /* 65280 */ 7040 0, 7041 #endif 7042 }, 7043 { 7044 BCMI_EAGLE_XGXS_PATGEN_SEQ_10r, 7045 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7046 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 7047 BCMI_EAGLE_XGXS_PATGEN_SEQ_10r_fields, 7048 #else 7049 0, 7050 #endif 7051 #endif 7052 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7053 PHYMOD_SYMBOL_FLAG_REGISTER, 7054 "PATGEN_SEQ_10r", 7055 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7056 "PATT_GEN_COM_SEQ_10", 7057 NULL, 7058 #endif 7059 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7060 0xff00, /* 65280 */ 7061 0, 7062 #endif 7063 }, 7064 { 7065 BCMI_EAGLE_XGXS_PATGEN_SEQ_11r, 7066 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7067 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 7068 BCMI_EAGLE_XGXS_PATGEN_SEQ_11r_fields, 7069 #else 7070 0, 7071 #endif 7072 #endif 7073 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7074 PHYMOD_SYMBOL_FLAG_REGISTER, 7075 "PATGEN_SEQ_11r", 7076 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7077 "PATT_GEN_COM_SEQ_11", 7078 NULL, 7079 #endif 7080 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7081 0xff00, /* 65280 */ 7082 0, 7083 #endif 7084 }, 7085 { 7086 BCMI_EAGLE_XGXS_PATGEN_SEQ_12r, 7087 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7088 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 7089 BCMI_EAGLE_XGXS_PATGEN_SEQ_12r_fields, 7090 #else 7091 0, 7092 #endif 7093 #endif 7094 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7095 PHYMOD_SYMBOL_FLAG_REGISTER, 7096 "PATGEN_SEQ_12r", 7097 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7098 "PATT_GEN_COM_SEQ_12", 7099 NULL, 7100 #endif 7101 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7102 0xff00, /* 65280 */ 7103 0, 7104 #endif 7105 }, 7106 { 7107 BCMI_EAGLE_XGXS_PATGEN_SEQ_13r, 7108 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7109 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 7110 BCMI_EAGLE_XGXS_PATGEN_SEQ_13r_fields, 7111 #else 7112 0, 7113 #endif 7114 #endif 7115 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7116 PHYMOD_SYMBOL_FLAG_REGISTER, 7117 "PATGEN_SEQ_13r", 7118 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7119 "PATT_GEN_COM_SEQ_13", 7120 NULL, 7121 #endif 7122 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7123 0xff00, /* 65280 */ 7124 0, 7125 #endif 7126 }, 7127 { 7128 BCMI_EAGLE_XGXS_PATGEN_SEQ_14r, 7129 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7130 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 7131 BCMI_EAGLE_XGXS_PATGEN_SEQ_14r_fields, 7132 #else 7133 0, 7134 #endif 7135 #endif 7136 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7137 PHYMOD_SYMBOL_FLAG_REGISTER, 7138 "PATGEN_SEQ_14r", 7139 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7140 "PATT_GEN_COM_SEQ_14", 7141 NULL, 7142 #endif 7143 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7144 0xff00, /* 65280 */ 7145 0, 7146 #endif 7147 }, 7148 { 7149 BCMI_EAGLE_XGXS_TXFIR_CTL1r, 7150 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7151 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 7152 BCMI_EAGLE_XGXS_TXFIR_CTL1r_fields, 7153 #else 7154 0, 7155 #endif 7156 #endif 7157 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7158 PHYMOD_SYMBOL_FLAG_REGISTER, 7159 "TXFIR_CTL1r", 7160 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7161 "TX_FED_TXFIR_CONTROL1", 7162 NULL, 7163 #endif 7164 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7165 0x588, /* 1416 */ 7166 0, 7167 #endif 7168 }, 7169 { 7170 BCMI_EAGLE_XGXS_TXFIR_CTL2r, 7171 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7172 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 7173 BCMI_EAGLE_XGXS_TXFIR_CTL2r_fields, 7174 #else 7175 0, 7176 #endif 7177 #endif 7178 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7179 PHYMOD_SYMBOL_FLAG_REGISTER, 7180 "TXFIR_CTL2r", 7181 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7182 "TX_FED_TXFIR_CONTROL2", 7183 NULL, 7184 #endif 7185 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7186 0x3c, /* 60 */ 7187 0, 7188 #endif 7189 }, 7190 { 7191 BCMI_EAGLE_XGXS_TXFIR_CTL3r, 7192 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7193 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 7194 BCMI_EAGLE_XGXS_TXFIR_CTL3r_fields, 7195 #else 7196 0, 7197 #endif 7198 #endif 7199 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7200 PHYMOD_SYMBOL_FLAG_REGISTER, 7201 "TXFIR_CTL3r", 7202 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7203 "TX_FED_TXFIR_CONTROL3", 7204 NULL, 7205 #endif 7206 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7207 0x8888, /* 34952 */ 7208 0, 7209 #endif 7210 }, 7211 { 7212 BCMI_EAGLE_XGXS_TXFIR_STS1r, 7213 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7214 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 7215 BCMI_EAGLE_XGXS_TXFIR_STS1r_fields, 7216 #else 7217 0, 7218 #endif 7219 #endif 7220 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7221 PHYMOD_SYMBOL_FLAG_REGISTER, 7222 "TXFIR_STS1r", 7223 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7224 "TX_FED_TXFIR_STATUS1", 7225 NULL, 7226 #endif 7227 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7228 0x588, /* 1416 */ 7229 0, 7230 #endif 7231 }, 7232 { 7233 BCMI_EAGLE_XGXS_TXFIR_STS2r, 7234 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7235 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 7236 BCMI_EAGLE_XGXS_TXFIR_STS2r_fields, 7237 #else 7238 0, 7239 #endif 7240 #endif 7241 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7242 PHYMOD_SYMBOL_FLAG_REGISTER, 7243 "TXFIR_STS2r", 7244 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7245 "TX_FED_TXFIR_STATUS2", 7246 NULL, 7247 #endif 7248 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7249 0x3c, /* 60 */ 7250 0, 7251 #endif 7252 }, 7253 { 7254 BCMI_EAGLE_XGXS_TXFIR_STS3r, 7255 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7256 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 7257 BCMI_EAGLE_XGXS_TXFIR_STS3r_fields, 7258 #else 7259 0, 7260 #endif 7261 #endif 7262 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7263 PHYMOD_SYMBOL_FLAG_REGISTER, 7264 "TXFIR_STS3r", 7265 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7266 "TX_FED_TXFIR_STATUS3", 7267 NULL, 7268 #endif 7269 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7270 0x588, /* 1416 */ 7271 0, 7272 #endif 7273 }, 7274 { 7275 BCMI_EAGLE_XGXS_TXFIR_STS4r, 7276 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7277 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 7278 BCMI_EAGLE_XGXS_TXFIR_STS4r_fields, 7279 #else 7280 0, 7281 #endif 7282 #endif 7283 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7284 PHYMOD_SYMBOL_FLAG_REGISTER, 7285 "TXFIR_STS4r", 7286 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7287 "TX_FED_TXFIR_STATUS4", 7288 NULL, 7289 #endif 7290 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7291 0x3c, /* 60 */ 7292 0, 7293 #endif 7294 }, 7295 { 7296 BCMI_EAGLE_XGXS_TXFIR_UC_CTLr, 7297 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7298 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 7299 BCMI_EAGLE_XGXS_TXFIR_UC_CTLr_fields, 7300 #else 7301 0, 7302 #endif 7303 #endif 7304 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7305 PHYMOD_SYMBOL_FLAG_REGISTER, 7306 "TXFIR_UC_CTLr", 7307 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7308 "TX_FED_MICRO_CONTROL", 7309 NULL, 7310 #endif 7311 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7312 0x0, /* 0 */ 7313 0, 7314 #endif 7315 }, 7316 { 7317 BCMI_EAGLE_XGXS_TXFIR_MISC_CTL1r, 7318 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7319 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 7320 BCMI_EAGLE_XGXS_TXFIR_MISC_CTL1r_fields, 7321 #else 7322 0, 7323 #endif 7324 #endif 7325 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7326 PHYMOD_SYMBOL_FLAG_REGISTER, 7327 "TXFIR_MISC_CTL1r", 7328 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7329 "TX_FED_MISC_CONTROL1", 7330 NULL, 7331 #endif 7332 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7333 0x300, /* 768 */ 7334 0, 7335 #endif 7336 }, 7337 { 7338 BCMI_EAGLE_XGXS_TXFIR_CTL4r, 7339 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7340 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 7341 BCMI_EAGLE_XGXS_TXFIR_CTL4r_fields, 7342 #else 7343 0, 7344 #endif 7345 #endif 7346 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7347 PHYMOD_SYMBOL_FLAG_REGISTER, 7348 "TXFIR_CTL4r", 7349 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7350 "TX_FED_TXFIR_CONTROL4", 7351 NULL, 7352 #endif 7353 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7354 0x800, /* 2048 */ 7355 0, 7356 #endif 7357 }, 7358 { 7359 BCMI_EAGLE_XGXS_PLL_CAL_CTL0r, 7360 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7361 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 7362 BCMI_EAGLE_XGXS_PLL_CAL_CTL0r_fields, 7363 #else 7364 0, 7365 #endif 7366 #endif 7367 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7368 PHYMOD_SYMBOL_FLAG_REGISTER, 7369 "PLL_CAL_CTL0r", 7370 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7371 "PLL_CAL_COM_CTL_0", 7372 NULL, 7373 #endif 7374 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7375 0xc803, /* 51203 */ 7376 0, 7377 #endif 7378 }, 7379 { 7380 BCMI_EAGLE_XGXS_PLL_CAL_CTL1r, 7381 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7382 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 7383 BCMI_EAGLE_XGXS_PLL_CAL_CTL1r_fields, 7384 #else 7385 0, 7386 #endif 7387 #endif 7388 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7389 PHYMOD_SYMBOL_FLAG_REGISTER, 7390 "PLL_CAL_CTL1r", 7391 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7392 "PLL_CAL_COM_CTL_1", 7393 NULL, 7394 #endif 7395 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7396 0xc8ff, /* 51455 */ 7397 0, 7398 #endif 7399 }, 7400 { 7401 BCMI_EAGLE_XGXS_PLL_CAL_CTL2r, 7402 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7403 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 7404 BCMI_EAGLE_XGXS_PLL_CAL_CTL2r_fields, 7405 #else 7406 0, 7407 #endif 7408 #endif 7409 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7410 PHYMOD_SYMBOL_FLAG_REGISTER, 7411 "PLL_CAL_CTL2r", 7412 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7413 "PLL_CAL_COM_CTL_2", 7414 NULL, 7415 #endif 7416 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7417 0xff01, /* 65281 */ 7418 0, 7419 #endif 7420 }, 7421 { 7422 BCMI_EAGLE_XGXS_PLL_CAL_CTL3r, 7423 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7424 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 7425 BCMI_EAGLE_XGXS_PLL_CAL_CTL3r_fields, 7426 #else 7427 0, 7428 #endif 7429 #endif 7430 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7431 PHYMOD_SYMBOL_FLAG_REGISTER, 7432 "PLL_CAL_CTL3r", 7433 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7434 "PLL_CAL_COM_CTL_3", 7435 NULL, 7436 #endif 7437 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7438 0x0, /* 0 */ 7439 0, 7440 #endif 7441 }, 7442 { 7443 BCMI_EAGLE_XGXS_PLL_CAL_CTL4r, 7444 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7445 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 7446 BCMI_EAGLE_XGXS_PLL_CAL_CTL4r_fields, 7447 #else 7448 0, 7449 #endif 7450 #endif 7451 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7452 PHYMOD_SYMBOL_FLAG_REGISTER, 7453 "PLL_CAL_CTL4r", 7454 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7455 "PLL_CAL_COM_CTL_4", 7456 NULL, 7457 #endif 7458 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7459 0xa80d, /* 43021 */ 7460 0, 7461 #endif 7462 }, 7463 { 7464 BCMI_EAGLE_XGXS_PLL_CAL_CTL5r, 7465 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7466 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 7467 BCMI_EAGLE_XGXS_PLL_CAL_CTL5r_fields, 7468 #else 7469 0, 7470 #endif 7471 #endif 7472 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7473 PHYMOD_SYMBOL_FLAG_REGISTER, 7474 "PLL_CAL_CTL5r", 7475 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7476 "PLL_CAL_COM_CTL_5", 7477 NULL, 7478 #endif 7479 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7480 0x27, /* 39 */ 7481 0, 7482 #endif 7483 }, 7484 { 7485 BCMI_EAGLE_XGXS_PLL_CAL_CTL6r, 7486 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7487 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 7488 BCMI_EAGLE_XGXS_PLL_CAL_CTL6r_fields, 7489 #else 7490 0, 7491 #endif 7492 #endif 7493 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7494 PHYMOD_SYMBOL_FLAG_REGISTER, 7495 "PLL_CAL_CTL6r", 7496 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7497 "PLL_CAL_COM_CTL_6", 7498 NULL, 7499 #endif 7500 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7501 0x7, /* 7 */ 7502 0, 7503 #endif 7504 }, 7505 { 7506 BCMI_EAGLE_XGXS_PLL_CAL_CTL7r, 7507 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7508 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 7509 BCMI_EAGLE_XGXS_PLL_CAL_CTL7r_fields, 7510 #else 7511 0, 7512 #endif 7513 #endif 7514 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7515 PHYMOD_SYMBOL_FLAG_REGISTER, 7516 "PLL_CAL_CTL7r", 7517 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7518 "PLL_CAL_COM_CTL_7", 7519 NULL, 7520 #endif 7521 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7522 0xa, /* 10 */ 7523 0, 7524 #endif 7525 }, 7526 { 7527 BCMI_EAGLE_XGXS_PLL_CAL_CTL_STS0r, 7528 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7529 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 7530 BCMI_EAGLE_XGXS_PLL_CAL_CTL_STS0r_fields, 7531 #else 7532 0, 7533 #endif 7534 #endif 7535 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7536 PHYMOD_SYMBOL_FLAG_REGISTER, 7537 "PLL_CAL_CTL_STS0r", 7538 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7539 "PLL_CAL_COM_CTL_STATUS_0", 7540 NULL, 7541 #endif 7542 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7543 0x0, /* 0 */ 7544 0, 7545 #endif 7546 }, 7547 { 7548 BCMI_EAGLE_XGXS_PLL_CAL_CTL_STS1r, 7549 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7550 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 7551 BCMI_EAGLE_XGXS_PLL_CAL_CTL_STS1r_fields, 7552 #else 7553 0, 7554 #endif 7555 #endif 7556 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7557 PHYMOD_SYMBOL_FLAG_REGISTER, 7558 "PLL_CAL_CTL_STS1r", 7559 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7560 "PLL_CAL_COM_CTL_STATUS_1", 7561 NULL, 7562 #endif 7563 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7564 0x0, /* 0 */ 7565 0, 7566 #endif 7567 }, 7568 { 7569 BCMI_EAGLE_XGXS_PLL_CAL_CTL_STS_DBGr, 7570 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7571 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 7572 BCMI_EAGLE_XGXS_PLL_CAL_CTL_STS_DBGr_fields, 7573 #else 7574 0, 7575 #endif 7576 #endif 7577 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7578 PHYMOD_SYMBOL_FLAG_REGISTER, 7579 "PLL_CAL_CTL_STS_DBGr", 7580 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7581 "PLL_CAL_COM_CTL_STATUS_DBG", 7582 NULL, 7583 #endif 7584 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7585 0x1, /* 1 */ 7586 0, 7587 #endif 7588 }, 7589 { 7590 BCMI_EAGLE_XGXS_CL72_TXC_TAP_LIMIT_CTL1r, 7591 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7592 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 7593 BCMI_EAGLE_XGXS_CL72_TXC_TAP_LIMIT_CTL1r_fields, 7594 #else 7595 0, 7596 #endif 7597 #endif 7598 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7599 PHYMOD_SYMBOL_FLAG_REGISTER, 7600 "CL72_TXC_TAP_LIMIT_CTL1r", 7601 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7602 "TX_COM_CL72_TAP_LIMIT_CONTROL1", 7603 NULL, 7604 #endif 7605 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7606 0x7ff, /* 2047 */ 7607 0, 7608 #endif 7609 }, 7610 { 7611 BCMI_EAGLE_XGXS_CL72_TXC_TAP_LIMIT_CTL2r, 7612 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7613 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 7614 BCMI_EAGLE_XGXS_CL72_TXC_TAP_LIMIT_CTL2r_fields, 7615 #else 7616 0, 7617 #endif 7618 #endif 7619 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7620 PHYMOD_SYMBOL_FLAG_REGISTER, 7621 "CL72_TXC_TAP_LIMIT_CTL2r", 7622 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7623 "TX_COM_CL72_TAP_LIMIT_CONTROL2", 7624 NULL, 7625 #endif 7626 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7627 0x70, /* 112 */ 7628 0, 7629 #endif 7630 }, 7631 { 7632 BCMI_EAGLE_XGXS_CL72_TXC_TAP_PRESET_CTLr, 7633 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7634 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 7635 BCMI_EAGLE_XGXS_CL72_TXC_TAP_PRESET_CTLr_fields, 7636 #else 7637 0, 7638 #endif 7639 #endif 7640 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7641 PHYMOD_SYMBOL_FLAG_REGISTER, 7642 "CL72_TXC_TAP_PRESET_CTLr", 7643 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7644 "TX_COM_CL72_TAP_PRESET_CONTROL", 7645 NULL, 7646 #endif 7647 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7648 0x0, /* 0 */ 7649 0, 7650 #endif 7651 }, 7652 { 7653 BCMI_EAGLE_XGXS_CL72_TXC_DBG1r, 7654 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7655 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 7656 BCMI_EAGLE_XGXS_CL72_TXC_DBG1r_fields, 7657 #else 7658 0, 7659 #endif 7660 #endif 7661 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7662 PHYMOD_SYMBOL_FLAG_REGISTER, 7663 "CL72_TXC_DBG1r", 7664 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7665 "TX_COM_CL72_DEBUG_1_REGISTER", 7666 NULL, 7667 #endif 7668 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7669 0x3828, /* 14376 */ 7670 0, 7671 #endif 7672 }, 7673 { 7674 BCMI_EAGLE_XGXS_CL72_TXC_MAX_WAIT_TMRr, 7675 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7676 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 7677 BCMI_EAGLE_XGXS_CL72_TXC_MAX_WAIT_TMRr_fields, 7678 #else 7679 0, 7680 #endif 7681 #endif 7682 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7683 PHYMOD_SYMBOL_FLAG_REGISTER, 7684 "CL72_TXC_MAX_WAIT_TMRr", 7685 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7686 "TX_COM_CL72_MAX_WAIT_TIMER_REGISTER", 7687 NULL, 7688 #endif 7689 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7690 0x1f4, /* 500 */ 7691 0, 7692 #endif 7693 }, 7694 { 7695 BCMI_EAGLE_XGXS_CL72_TXC_WAIT_TMRr, 7696 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7697 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 7698 BCMI_EAGLE_XGXS_CL72_TXC_WAIT_TMRr_fields, 7699 #else 7700 0, 7701 #endif 7702 #endif 7703 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7704 PHYMOD_SYMBOL_FLAG_REGISTER, 7705 "CL72_TXC_WAIT_TMRr", 7706 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7707 "TX_COM_CL72_WAIT_TIMER_REGISTER", 7708 NULL, 7709 #endif 7710 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7711 0xc8, /* 200 */ 7712 0, 7713 #endif 7714 }, 7715 { 7716 BCMI_EAGLE_XGXS_UC_RAMWORDr, 7717 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7718 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 7719 BCMI_EAGLE_XGXS_UC_RAMWORDr_fields, 7720 #else 7721 0, 7722 #endif 7723 #endif 7724 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7725 PHYMOD_SYMBOL_FLAG_REGISTER, 7726 "UC_RAMWORDr", 7727 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7728 "MICRO_A_COM_RAMWORD", 7729 NULL, 7730 #endif 7731 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7732 0x0, /* 0 */ 7733 0, 7734 #endif 7735 }, 7736 { 7737 BCMI_EAGLE_XGXS_UC_ADDRr, 7738 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7739 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 7740 BCMI_EAGLE_XGXS_UC_ADDRr_fields, 7741 #else 7742 0, 7743 #endif 7744 #endif 7745 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7746 PHYMOD_SYMBOL_FLAG_REGISTER, 7747 "UC_ADDRr", 7748 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7749 "MICRO_A_COM_ADDRESS", 7750 NULL, 7751 #endif 7752 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7753 0x0, /* 0 */ 7754 0, 7755 #endif 7756 }, 7757 { 7758 BCMI_EAGLE_XGXS_UC_COMMANDr, 7759 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7760 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 7761 BCMI_EAGLE_XGXS_UC_COMMANDr_fields, 7762 #else 7763 0, 7764 #endif 7765 #endif 7766 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7767 PHYMOD_SYMBOL_FLAG_REGISTER, 7768 "UC_COMMANDr", 7769 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7770 "MICRO_A_COM_COMMAND", 7771 NULL, 7772 #endif 7773 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7774 0x0, /* 0 */ 7775 0, 7776 #endif 7777 }, 7778 { 7779 BCMI_EAGLE_XGXS_UC_RAM_WRDATAr, 7780 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7781 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 7782 BCMI_EAGLE_XGXS_UC_RAM_WRDATAr_fields, 7783 #else 7784 0, 7785 #endif 7786 #endif 7787 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7788 PHYMOD_SYMBOL_FLAG_REGISTER, 7789 "UC_RAM_WRDATAr", 7790 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7791 "MICRO_A_COM_RAM_WRDATA", 7792 NULL, 7793 #endif 7794 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7795 0x0, /* 0 */ 7796 0, 7797 #endif 7798 }, 7799 { 7800 BCMI_EAGLE_XGXS_UC_RAM_RDDATAr, 7801 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7802 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 7803 BCMI_EAGLE_XGXS_UC_RAM_RDDATAr_fields, 7804 #else 7805 0, 7806 #endif 7807 #endif 7808 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7809 PHYMOD_SYMBOL_FLAG_REGISTER, 7810 "UC_RAM_RDDATAr", 7811 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7812 "MICRO_A_COM_RAM_RDDATA", 7813 NULL, 7814 #endif 7815 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7816 0x0, /* 0 */ 7817 0, 7818 #endif 7819 }, 7820 { 7821 BCMI_EAGLE_XGXS_UC_DWNLOAD_STSr, 7822 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7823 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 7824 BCMI_EAGLE_XGXS_UC_DWNLOAD_STSr_fields, 7825 #else 7826 0, 7827 #endif 7828 #endif 7829 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7830 PHYMOD_SYMBOL_FLAG_REGISTER, 7831 "UC_DWNLOAD_STSr", 7832 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7833 "MICRO_A_COM_DOWNLOAD_STATUS", 7834 NULL, 7835 #endif 7836 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7837 0x0, /* 0 */ 7838 0, 7839 #endif 7840 }, 7841 { 7842 BCMI_EAGLE_XGXS_UC_SFR_STSr, 7843 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7844 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 7845 BCMI_EAGLE_XGXS_UC_SFR_STSr_fields, 7846 #else 7847 0, 7848 #endif 7849 #endif 7850 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7851 PHYMOD_SYMBOL_FLAG_REGISTER, 7852 "UC_SFR_STSr", 7853 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7854 "MICRO_A_COM_SFR_STATUS", 7855 NULL, 7856 #endif 7857 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7858 0x0, /* 0 */ 7859 0, 7860 #endif 7861 }, 7862 { 7863 BCMI_EAGLE_XGXS_UC_MDIO_UC_MAILBOX_MSWr, 7864 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7865 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 7866 BCMI_EAGLE_XGXS_UC_MDIO_UC_MAILBOX_MSWr_fields, 7867 #else 7868 0, 7869 #endif 7870 #endif 7871 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7872 PHYMOD_SYMBOL_FLAG_REGISTER, 7873 "UC_MDIO_UC_MAILBOX_MSWr", 7874 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7875 "MICRO_A_COM_MDIO_UC_MAILBOX_MSW", 7876 NULL, 7877 #endif 7878 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7879 0x0, /* 0 */ 7880 0, 7881 #endif 7882 }, 7883 { 7884 BCMI_EAGLE_XGXS_UC_MDIO_UC_MAILBOX_LSWr, 7885 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7886 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 7887 BCMI_EAGLE_XGXS_UC_MDIO_UC_MAILBOX_LSWr_fields, 7888 #else 7889 0, 7890 #endif 7891 #endif 7892 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7893 PHYMOD_SYMBOL_FLAG_REGISTER, 7894 "UC_MDIO_UC_MAILBOX_LSWr", 7895 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7896 "MICRO_A_COM_MDIO_UC_MAILBOX_LSW", 7897 NULL, 7898 #endif 7899 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7900 0x0, /* 0 */ 7901 0, 7902 #endif 7903 }, 7904 { 7905 BCMI_EAGLE_XGXS_UC_UC_MDIO_MAILBOX_LSWr, 7906 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7907 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 7908 BCMI_EAGLE_XGXS_UC_UC_MDIO_MAILBOX_LSWr_fields, 7909 #else 7910 0, 7911 #endif 7912 #endif 7913 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7914 PHYMOD_SYMBOL_FLAG_REGISTER, 7915 "UC_UC_MDIO_MAILBOX_LSWr", 7916 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7917 "MICRO_A_COM_UC_MDIO_MAILBOX_LSW", 7918 NULL, 7919 #endif 7920 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7921 0x0, /* 0 */ 7922 0, 7923 #endif 7924 }, 7925 { 7926 BCMI_EAGLE_XGXS_UC_COMMAND2r, 7927 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7928 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 7929 BCMI_EAGLE_XGXS_UC_COMMAND2r_fields, 7930 #else 7931 0, 7932 #endif 7933 #endif 7934 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7935 PHYMOD_SYMBOL_FLAG_REGISTER, 7936 "UC_COMMAND2r", 7937 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7938 "MICRO_A_COM_COMMAND2", 7939 NULL, 7940 #endif 7941 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7942 0x80f, /* 2063 */ 7943 0, 7944 #endif 7945 }, 7946 { 7947 BCMI_EAGLE_XGXS_UC_UC_MDIO_MAILBOX_MSWr, 7948 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7949 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 7950 BCMI_EAGLE_XGXS_UC_UC_MDIO_MAILBOX_MSWr_fields, 7951 #else 7952 0, 7953 #endif 7954 #endif 7955 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7956 PHYMOD_SYMBOL_FLAG_REGISTER, 7957 "UC_UC_MDIO_MAILBOX_MSWr", 7958 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7959 "MICRO_A_COM_UC_MDIO_MAILBOX_MSW", 7960 NULL, 7961 #endif 7962 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7963 0x0, /* 0 */ 7964 0, 7965 #endif 7966 }, 7967 { 7968 BCMI_EAGLE_XGXS_UC_COMMAND3r, 7969 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7970 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 7971 BCMI_EAGLE_XGXS_UC_COMMAND3r_fields, 7972 #else 7973 0, 7974 #endif 7975 #endif 7976 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7977 PHYMOD_SYMBOL_FLAG_REGISTER, 7978 "UC_COMMAND3r", 7979 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 7980 "MICRO_A_COM_COMMAND3", 7981 NULL, 7982 #endif 7983 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 7984 0x2, /* 2 */ 7985 0, 7986 #endif 7987 }, 7988 { 7989 BCMI_EAGLE_XGXS_UC_COMMAND4r, 7990 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 7991 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 7992 BCMI_EAGLE_XGXS_UC_COMMAND4r_fields, 7993 #else 7994 0, 7995 #endif 7996 #endif 7997 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 7998 PHYMOD_SYMBOL_FLAG_REGISTER, 7999 "UC_COMMAND4r", 8000 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8001 "MICRO_A_COM_COMMAND4", 8002 NULL, 8003 #endif 8004 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8005 0x0, /* 0 */ 8006 0, 8007 #endif 8008 }, 8009 { 8010 BCMI_EAGLE_XGXS_UC_TEMPERATURE_STSr, 8011 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8012 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 8013 BCMI_EAGLE_XGXS_UC_TEMPERATURE_STSr_fields, 8014 #else 8015 0, 8016 #endif 8017 #endif 8018 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8019 PHYMOD_SYMBOL_FLAG_REGISTER, 8020 "UC_TEMPERATURE_STSr", 8021 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8022 "MICRO_A_COM_TEMPERATURE_STATUS", 8023 NULL, 8024 #endif 8025 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8026 0x0, /* 0 */ 8027 0, 8028 #endif 8029 }, 8030 { 8031 BCMI_EAGLE_XGXS_UC_PROGRAM_RAM_CTL1r, 8032 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8033 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 8034 BCMI_EAGLE_XGXS_UC_PROGRAM_RAM_CTL1r_fields, 8035 #else 8036 0, 8037 #endif 8038 #endif 8039 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8040 PHYMOD_SYMBOL_FLAG_REGISTER, 8041 "UC_PROGRAM_RAM_CTL1r", 8042 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8043 "MICRO_B_COM_PROGRAM_RAM_CONTROL1", 8044 NULL, 8045 #endif 8046 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8047 0x0, /* 0 */ 8048 0, 8049 #endif 8050 }, 8051 { 8052 BCMI_EAGLE_XGXS_UC_DATARAM_CTL1r, 8053 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8054 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 8055 BCMI_EAGLE_XGXS_UC_DATARAM_CTL1r_fields, 8056 #else 8057 0, 8058 #endif 8059 #endif 8060 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8061 PHYMOD_SYMBOL_FLAG_REGISTER, 8062 "UC_DATARAM_CTL1r", 8063 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8064 "MICRO_B_COM_DATARAM_CONTROL1", 8065 NULL, 8066 #endif 8067 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8068 0x0, /* 0 */ 8069 0, 8070 #endif 8071 }, 8072 { 8073 BCMI_EAGLE_XGXS_UC_IRAM_CTL1r, 8074 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8075 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 8076 BCMI_EAGLE_XGXS_UC_IRAM_CTL1r_fields, 8077 #else 8078 0, 8079 #endif 8080 #endif 8081 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8082 PHYMOD_SYMBOL_FLAG_REGISTER, 8083 "UC_IRAM_CTL1r", 8084 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8085 "MICRO_B_COM_IRAM_CONTROL1", 8086 NULL, 8087 #endif 8088 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8089 0x0, /* 0 */ 8090 0, 8091 #endif 8092 }, 8093 { 8094 BCMI_EAGLE_XGXS_MDIO_MASKDATAr, 8095 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8096 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 8097 BCMI_EAGLE_XGXS_MDIO_MASKDATAr_fields, 8098 #else 8099 0, 8100 #endif 8101 #endif 8102 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8103 PHYMOD_SYMBOL_FLAG_REGISTER, 8104 "MDIO_MASKDATAr", 8105 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8106 "MDIO_MMDSEL_AER_COM_MDIO_MASKDATA", 8107 NULL, 8108 #endif 8109 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8110 0x0, /* 0 */ 8111 0, 8112 #endif 8113 }, 8114 { 8115 BCMI_EAGLE_XGXS_MDIO_BCST_PORT_ADDRr, 8116 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8117 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 8118 BCMI_EAGLE_XGXS_MDIO_BCST_PORT_ADDRr_fields, 8119 #else 8120 0, 8121 #endif 8122 #endif 8123 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8124 PHYMOD_SYMBOL_FLAG_REGISTER, 8125 "MDIO_BCST_PORT_ADDRr", 8126 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8127 "MDIO_MMDSEL_AER_COM_MDIO_BRCST_PORT_ADDR", 8128 NULL, 8129 #endif 8130 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8131 0x1f, /* 31 */ 8132 0, 8133 #endif 8134 }, 8135 { 8136 BCMI_EAGLE_XGXS_MDIO_MMD_SELr, 8137 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8138 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 8139 BCMI_EAGLE_XGXS_MDIO_MMD_SELr_fields, 8140 #else 8141 0, 8142 #endif 8143 #endif 8144 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8145 PHYMOD_SYMBOL_FLAG_REGISTER, 8146 "MDIO_MMD_SELr", 8147 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8148 "MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT", 8149 NULL, 8150 #endif 8151 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8152 0x404d, /* 16461 */ 8153 0, 8154 #endif 8155 }, 8156 { 8157 BCMI_EAGLE_XGXS_MDIO_AERr, 8158 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8159 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 8160 BCMI_EAGLE_XGXS_MDIO_AERr_fields, 8161 #else 8162 0, 8163 #endif 8164 #endif 8165 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8166 PHYMOD_SYMBOL_FLAG_REGISTER, 8167 "MDIO_AERr", 8168 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8169 "MDIO_MMDSEL_AER_COM_MDIO_AER", 8170 NULL, 8171 #endif 8172 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8173 0x0, /* 0 */ 8174 0, 8175 #endif 8176 }, 8177 { 8178 BCMI_EAGLE_XGXS_MDIO_BLK_ADDRr, 8179 #if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1 8180 #ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_EAGLE_XGXS 8181 BCMI_EAGLE_XGXS_MDIO_BLK_ADDRr_fields, 8182 #else 8183 0, 8184 #endif 8185 #endif 8186 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1), 8187 PHYMOD_SYMBOL_FLAG_REGISTER, 8188 "MDIO_BLK_ADDRr", 8189 #if PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1 8190 "MDIO_BLK_ADDR_COM_BLK_ADDR", 8191 NULL, 8192 #endif 8193 #if PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1 8194 0x0, /* 0 */ 8195 0, 8196 #endif 8197 }, 8198 #endif 8199 }; 8200 8201 8202 phymod_symbols_t bcmi_eagle_xgxs_symbols = 8203 { 8204 bcmi_eagle_xgxs_syms, sizeof(bcmi_eagle_xgxs_syms)/sizeof(bcmi_eagle_xgxs_syms[0]), 8205 #if PHYMOD_CONFIG_INCLUDE_FIELD_NAMES == 1 8206 bcmi_eagle_xgxs_fields 8207 #else 8208 NULL 8209 #endif 8210 /* END OF SYMBOL FILE */ 8211 }; 8212 8213 #endif /* PHYMOD_CONFIG_INCLUDE_CHIP_SYMBOLS */