phymod_reg.h (6007B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 */ 7 8 #ifndef __PHYMOD_REG_H__ 9 #define __PHYMOD_REG_H__ 10 11 #include <phymod/phymod_types.h> 12 13 /* 14 * Generic 32-bit PHY register layout: 15 * 16 * [31:28] - Access method 17 * [27:24] - Flags for access method 18 * [23:0] - Register address 19 * 20 * 21 * Access method 0 (Raw) 22 * 23 * For clause 22 access, register address is in bits [4:0]. For 24 * clause 45 access, register address is in bits [15:0] and 25 * DEVAD is in bits [20:16]. 26 * 27 * 28 * Access method 1 (Broadcom Gigabit/Fast Ethernet shadow) 29 * 30 * If register is shadowed (register 18h, 1Ch, etc.) then shadow 31 * number is in bits [15:8] and base register is in bits [4:0]. 32 * If register is an expansion register (registers 15h/17h), then 33 * register address is in bits [23:8] and bits [4:0] is 15h. 34 * If register is a clause 45 register (registers 0Dh/0Eh), then 35 * clause 45 device type is in bits [27:24], clause 45 register 36 * address is in bits [23:8] and bits [4:0] is 0Eh. 37 * 38 * 39 * Access method 2 (Broadcom Gigabit/1000BASE-X registers) 40 * 41 * Base address is in bits [4:0]. The 1000BASE-X registers will 42 * be mapped into the IEEE space before register is accessed. 43 * 44 * 45 * Access method 3 (Internal SerDes PHY block-based) 46 * 47 * Block address is in bits [23:8] (will be written to register. 48 * 1Fh). Base address is in bits [4:0]. For clause 45 devices 49 * the DEVAD is stored in the flags field (bits [26:24]). 50 * 51 * 52 * Access method 4 (Internal XAUI/SerDes PHY with IEEE-map) 53 * 54 * Identical to access method 3, but supports the following 55 * access flag instead of clause 45 DEVAD: 56 * 57 * Bit 3 - If set, map SerDes registers before reading IEEE 58 * register. otherwise map XAUI registers before 59 * reading IEEE register. 60 * 61 * 62 * Access method 5 (Internal SerDes PHY clause 45 with AER) 63 * 64 * Clause 45 address is in bits [15:0] and DEVAD in bits [19:16]. 65 * If a register is not duplicated for each XAUI lane, the actual 66 * number of copies (1 or 2) will be stored in bits [22:20]. 67 * If clause 45 access is not supported the access will be done 68 * using clause 22 block-mapped access. 69 * 70 * This method supports the following flags: 71 * 72 * Bit 3 - If set, force write to lane specified in flag 73 * bits [2:0]. 74 * 75 * Bit 2 - If set, broadcast writes to all lanes if not in 76 * independent lane mode (aka. serdes mode). 77 * Ignored if flag bit 3 is set (force lane). 78 * 79 * In addition to the standard flags, bit 23 is used as a 80 * write-only flag. 81 * 82 * 83 * Access method 6 (Broadcom 10-Gigabit registers) 84 * 85 * Standard clause 45 access with additional support for Gigabit 86 * shadow and extension register. Also supports multiple PHYs 87 * (each with multiple clause 45 device types) for a single PHY 88 * address. 89 * If register is a standard clause 45 register, then clause 45 90 * device type is in bits [20:16] and register address is in 91 * bits [15:0]. 92 * If register is shadowed (register 18h, 1Ch, etc.) then shadow 93 * number is in bits [15:8] and base register is in bits [4:0]. 94 * If register is an expansion register (registers 15h/17h), then 95 * register address is in bits [23:8] and bits [4:0] is 15h. 96 * 97 * This method supports the following flags: 98 * 99 * Bit 3 - Use shadow/extension register access. 100 * 101 * Flag bits [2:0] may be used to select an alternative PHY device. 102 */ 103 104 /* Register layout */ 105 #define PHYMOD_REG_ACCESS_METHOD_SHIFT 28 106 #define PHYMOD_REG_ACCESS_FLAGS_SHIFT 24 107 #define PHYMOD_INTERFACE_SIDE_SHIFT 31 108 /* Access methods */ 109 #define PHYMOD_REG_ACC_RAW LSHIFT32(0, PHYMOD_REG_ACCESS_METHOD_SHIFT) 110 #define PHYMOD_REG_ACC_BRCM_SHADOW LSHIFT32(1, PHYMOD_REG_ACCESS_METHOD_SHIFT) 111 #define PHYMOD_REG_ACC_BRCM_1000X LSHIFT32(2, PHYMOD_REG_ACCESS_METHOD_SHIFT) 112 #define PHYMOD_REG_ACC_XGS_IBLK LSHIFT32(3, PHYMOD_REG_ACCESS_METHOD_SHIFT) 113 #define PHYMOD_REG_ACC_XAUI_IBLK LSHIFT32(4, PHYMOD_REG_ACCESS_METHOD_SHIFT) 114 #define PHYMOD_REG_ACC_AER_IBLK LSHIFT32(5, PHYMOD_REG_ACCESS_METHOD_SHIFT) 115 #define PHYMOD_REG_ACC_BRCM_XE LSHIFT32(6, PHYMOD_REG_ACCESS_METHOD_SHIFT) 116 #define PHYMOD_REG_ACC_TSC_IBLK LSHIFT32(7, PHYMOD_REG_ACCESS_METHOD_SHIFT) 117 #define PHYMOD_REG_ACC_BRCM_RDB LSHIFT32(8, PHYMOD_REG_ACCESS_METHOD_SHIFT) 118 119 #define PHYMOD_REG_ACCESS_METHOD(_r) ((_r) & LSHIFT32(0xf, PHYMOD_REG_ACCESS_METHOD_SHIFT)) 120 121 #define PHYMOD_REG_IBLK_DEVAD(_r) (((_r) >> PHYMOD_REG_ACCESS_FLAGS_SHIFT) & 0x7) 122 123 /* Spacing between elements in register arrays */ 124 #define PHYMOD_REG_ACC_XGS_IBLK_STEP 0x1000 125 #define PHYMOD_REG_ACC_XAUI_IBLK_STEP 0x1000 126 #define PHYMOD_REG_ACC_AER_IBLK_STEP 0x10 127 128 /* Flags for PHYMOD_REG_ACC_XAUI_IBLK method */ 129 #define PHYMOD_REG_ACC_XAUI_IBLK_CL22 LSHIFT32(0x8, PHYMOD_REG_ACCESS_FLAGS_SHIFT) 130 131 /* Flags for PHYMOD_REG_ACC_AER_IBLK method */ 132 #define PHYMOD_REG_ACC_AER_IBLK_FORCE_LANE LSHIFT32(0x8, PHYMOD_REG_ACCESS_FLAGS_SHIFT) 133 #define PHYMOD_REG_ACC_AER_IBLK_FORCE_MASK LSHIFT32(0x7, PHYMOD_REG_ACCESS_FLAGS_SHIFT) 134 #define PHYMOD_REG_ACC_AER_IBLK_WR_ONLY LSHIFT32(1, 23) 135 136 /* Flags for PHYMOD_REG_ACC_BRCM_XE method */ 137 #define PHYMOD_REG_ACC_BRCM_XE_SHADOW LSHIFT32(0x8, PHYMOD_REG_ACCESS_FLAGS_SHIFT) 138 139 /* Flags for PHYMOD_REG_ACC_TSC_IBLK method */ 140 #define PHYMOD_REG_ACC_TSC_IBLK_FORCE_LANE LSHIFT32(0x8, PHYMOD_REG_ACCESS_FLAGS_SHIFT) 141 #define PHYMOD_REG_ACC_TSC_IBLK_BCAST LSHIFT32(0x4, PHYMOD_REG_ACCESS_FLAGS_SHIFT) 142 #define PHYMOD_REG_ACC_TSC_IBLK_WR_ONLY LSHIFT32(1, 23) 143 144 extern int 145 phymod_reg_read(phymod_access_t *pa, uint32_t addr, uint32_t *data); 146 147 extern int 148 phymod_reg_write(phymod_access_t *pa, uint32_t addr, uint32_t data); 149 150 #endif /* __PHYMOD_REG_H__ */