xfi_10gosrm2.soc (3235B)
1 #/*---------------------------------------------------------------------- 2 # * 3 # * 4 # * 5 # * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 6 # * 7 # * Copyright 2007-2019 Broadcom Inc. All rights reserved. 8 # * 9 # * Broadcom Corporation 10 # * Proprietary and Confidential information 11 # * All rights reserved 12 # * This source file is the property of Broadcom Corporation, and 13 # * may not be copied or distributed in any isomorphic form without the 14 # * prior written consent of Broadcom Corporation. 15 # *--------------------------------------------------------------------- 16 # * File : xfi_10gosrm2.soc 17 # * Description: xfi_10g Oversampling rate of 2 18 # *---------------------------------------------------------------------*/ 19 20 # reg_name=Reg_tsc_pmd_x1_control, dev_adr=0, reg_adr=0x1089010, reg_width=0x10, reg_data=0x3 21 #core/dp and core power release 22 local port $1 23 local lane $2 24 phy raw sbus $port 0.$lane 0x9010 0x0000 25 26 sleep 1 27 phy raw sbus $port 0.$lane 0x9010 0x0003 28 phy raw sbus $port 0.$lane 0x9010 29 30 # reg_name=Reg_tsc_pmd_x4_control, dev_adr=0, reg_adr=0x108c010, reg_width=0x10, reg_data=0x0 31 #x4 reset release 32 33 phy raw sbus $port 0.$lane 0xc010 0x0000 34 phy raw sbus $port 0.$lane 0xc010 0x0003 35 phy raw sbus $port 0.$lane 0xc010 36 37 # ln_dp_s_rstb release, reg_adr=0x908d081 reg_data=0x2 38 phy raw sbus $port 1.$lane 0xd081 0x0002 39 phy raw sbus $port 1.$lane 0xd081 40 41 # core_dp_s_rstb = 1, heartbeat_count_1us = 0x271, reg_adr=0x908d0f4 reg_data=0x2000 42 phy raw sbus $port 1.$lane 0xd0f4 0x2271 43 phy raw sbus $port 1.$lane 0xd0f4 44 45 46 # 0xr_mode_frc = 1, reg_adr=0x908d080 reg_data=0x8000 47 phy raw sbus $port 1.$lane 0xd080 0x8001 48 phy raw sbus $port 1.$lane 0xd080 49 50 51 # pll_mode = a, reg_adr=0x908d127 reg_data=0xa 52 phy raw sbus $port 1.$lane 0xd127 0x000a 53 phy raw sbus $port 1.$lane 0xd127 54 55 56 # reg_name=Reg_tsc_main0_setup, dev_adr=0, reg_adr=0x1089000, reg_width=0x10, reg_data=0x6400 57 phy raw sbus $port 0.$lane 0x9000 0x6400 58 phy raw sbus $port 0.$lane 0x9000 59 60 61 # release RXP reset ??, reg_name=Reg_tsc_rx_x4_control0_pma_control_0, dev_adr=0, reg_adr=0x108c137, reg_width=0x10, reg_data=0x1 62 63 phy raw sbus $port 0.$lane 0xc137 0x0001 64 phy raw sbus $port 0.$lane 0xc137 65 66 67 # release TXP reset, reg_name=Reg_tsc_tx_x4_control0_misc, dev_adr=0, reg_adr=0x108c113, reg_width=0x10, reg_data=0x2 68 69 phy raw sbus $port 0.$lane 0xc113 0x01ca 70 phy raw sbus $port 0.$lane 0xc113 71 72 73 # reg_name=Reg_tsc_tx_x4_control0_misc, dev_adr=0, reg_adr=0x108c113, reg_width=0x10, reg_data=0x1 74 75 phy raw sbus $port 0.$lane 0xc113 0x01cb 76 phy raw sbus $port 0.$lane 0xc113 77 78 79 # Reg_tsc_sc_x4_control_control, dev_adr=0, reg_adr=0x108c050, reg_width=0x10, reg_data=0x1c 80 81 phy raw sbus $port 0.$lane 0xc050 0x001c 82 phy raw sbus $port 0.$lane 0xc050 83 84 phy raw sbus $port 0.$lane 0xc050 0x011c 85 phy raw sbus $port 0.$lane 0xc050 86 87 sleep 1; 88 phy raw sbus $port 0.$lane 0xc154 89 90 # PMD LOOPBACK 91 #phy raw sbus $port 1.$lane 0xd0d2 92 phy raw sbus $port 1.$lane 0xd0d2 0x1 # PMD Digital loopback control 93 # PCS LOOPBACK 94 phy raw sbus $port 0.$lane 0x9009 0xf0 # Main0 loopback control 95 phy raw sbus $port 1.$lane 0xd080 # OSR control 96 phy raw sbus $port 0.$lane 0xc154 # pcs live link status 97 98