an_1g.soc (1683B)
1 #/*---------------------------------------------------------------------- 2 #* 3 #* This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 #* 5 #* Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 #* 7 #* Broadcom Corporation 8 #* Proprietary and Confidential information 9 #* All rights reserved 10 #* This source file is the property of Broadcom Corporation, and 11 #* may not be copied or distributed in any isomorphic form without the 12 #* prior written consent of Broadcom Corporation. 13 #*--------------------------------------------------------------------- 14 #* File : an_1g.soc 15 #* Description: an_1g cl73 16 #*---------------------------------------------------------------------*/ 17 18 link off 19 /* Disable the ports */ 20 phy xe0 0x2c050 0x001c 21 phy xe1 0x2c050 0x001c 22 23 /* This basically is used to write the data ram with pcs_lane_config */ 24 port xe0,xe1 adv=1000full an=t 25 26 /* Clear An enable */ 27 phy xe0 0x2c180 0x0000 28 phy xe1 0x2c180 0x0000 29 30 /* Set the adv. speed to 1G */ 31 phy xe0 0x2c186 0x20 32 phy xe1 0x2c186 0x20 33 34 /* Set the Nonce match OVerride, so the nonce match is ignored */ 35 phy xe0 0x2c185 0xa01 36 phy xe1 0x2c185 0xa01 37 38 /* cl73 link inhibit fail timer ncl72 */ 39 phy xe 0x9258 0x1200 40 41 42 #phy xe0 0x802d080 0x8008 43 #phy xe1 0x802d080 0x8008 44 45 #phy xe0 0x9000 0x6600 46 #phy xe1 0x9000 0x6600 47 48 /* Trying on lane #2, so set the master portnum to 0x6208 */ 49 phy xe0 0x9000 0x6208 50 phy xe1 0x9000 0x6208 51 52 phy xe0 0x2c180 0x0000 53 phy xe1 0x2c180 0x0000 54 55 /* Enable AN CL73 */ 56 phy xe0 0x2c180 0x0100 57 phy xe1 0x2c180 0x0100 58 59 /* Debug state registers */ 60 #phy xe0 0x2c054 61 #phy xe0 0x2c1ad 62 #phy xe1 0x2c054 63 #phy xe1 0x2c1ad 64 65 66 67