openbcm

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phymod_acc.c (2113B)

      1 /*
      2  * 
      3  * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file.
      4  * 
      5  * Copyright 2007-2019 Broadcom Inc. All rights reserved.
      6  */
      7 
      8 #include <phymod/phymod_acc.h>
      9 
     10 int
     11 phymod_acc_check(const phymod_access_t *pa)
     12 {
     13     if (pa == 0 ||
     14         PHYMOD_ACC_BUS(pa) == 0 ||
     15         PHYMOD_ACC_BUS(pa)->read == 0 ||
     16         PHYMOD_ACC_BUS(pa)->write == 0 ||
     17         PHYMOD_ACC_BUS(pa)->mem_read == 0 ||
     18         PHYMOD_ACC_BUS(pa)->mem_write == 0) {
     19         return -1;
     20     }
     21     return 0;
     22 }
     23 
     24 int
     25 phymod_bus_read(const phymod_access_t *pa, uint32_t reg, uint32_t *data)
     26 {
     27     /* Read raw PHY data */
     28     return PHYMOD_ACC_BUS(pa)->read(PHYMOD_ACC_USER_ACC(pa),
     29                                     PHYMOD_ACC_BUS_ADDR(pa),
     30                                     reg, data);
     31 }
     32 
     33 int
     34 phymod_mem_read(const phymod_access_t *pa, phymod_mem_type_t mem_type, uint32_t mem_index, uint32_t* val)
     35 {
     36     /* Read raw PHY data */
     37     return PHYMOD_ACC_BUS(pa)->mem_read(PHYMOD_ACC_USER_ACC(pa),
     38                                     mem_type,
     39                                     mem_index,
     40                                     val);
     41 }
     42 
     43 
     44 int
     45 phymod_bus_write(const phymod_access_t *pa, uint32_t reg, uint32_t data)
     46 {
     47     /* Write raw PHY data */
     48     return PHYMOD_ACC_BUS(pa)->write(PHYMOD_ACC_USER_ACC(pa),
     49                                      PHYMOD_ACC_BUS_ADDR(pa),
     50                                      reg, data);
     51 }
     52 
     53 int
     54 phymod_mem_write(const phymod_access_t *pa, phymod_mem_type_t mem_type, uint32_t mem_index, uint32_t* data)
     55 {
     56     /* Read raw PHY data */
     57     return PHYMOD_ACC_BUS(pa)->mem_write(PHYMOD_ACC_USER_ACC(pa),
     58                                     mem_type,
     59                                     mem_index,
     60                                     data);
     61 }
     62 
     63 
     64 int
     65 phymod_is_write_disabled(const phymod_access_t *pa, uint32_t *data)
     66 {
     67     if((PHYMOD_ACC_BUS(pa)->is_write_disabled) == NULL) { *data = 0; } else {
     68         return PHYMOD_ACC_BUS(pa)->is_write_disabled(PHYMOD_ACC_USER_ACC(pa),
     69                                      data);
     70     }
     71     return 0;
     72 }