tefmod_gen3.h (27885B)
1 /*---------------------------------------------------------------------- 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * $Copyright: (c) 2014 Broadcom Corporation All Rights Reserved.$ 8 * Broadcom Corporation 9 * Proprietary and Confidential information 10 * All rights reserved 11 * This source file is the property of Broadcom Corporation, and 12 * may not be copied or distributed in any isomorphic form without the 13 * prior written consent of Broadcom Corporation. 14 *---------------------------------------------------------------------- 15 * Description: define enumerators 16 *----------------------------------------------------------------------*/ 17 /* 18 * 19 * $Copyright: 20 * All Rights Reserved.$ 21 */ 22 23 #ifndef _tefmod_gen3_H_ 24 #define _tefmod_gen3_H_ 25 26 #define _SDK_TEFMOD_GEN3_ 1 27 28 29 #ifdef _SDK_TEFMOD_GEN3_ 30 #include <phymod/phymod.h> 31 #include <phymod/phymod_debug.h> 32 #include "tefmod_gen3_enum_defines.h" 33 #endif 34 35 #ifdef _SDK_TEFMOD_GEN3_ 36 #define PHYMOD_ST const phymod_access_t 37 #else 38 #define PHYMOD_ST tefmod_st 39 #endif 40 41 #define TEFMOD_FEC_NOT_SUPRTD 0 42 #define TEFMOD_FEC_SUPRTD_NOT_REQSTD 1 43 #define TEFMOD_FEC_CL74_SUPRTD_REQSTD 4 44 #define TEFMOD_FEC_CL91_SUPRTD_REQSTD 8 45 46 /* matching SOC_PHY_CONTROL_FEC_OFF 47 * SOC_PHY_CONTROL_FEC_ON 48 * SOC_PHY_CONTROL_FEC_AUTO 49 */ 50 #define TEFMOD_PHY_CONTROL_FEC_OFF 0 51 #define TEFMOD_PHY_CONTROL_FEC_ON 1 52 #define TEFMOD_PHY_CONTROL_FEC_AUTO 2 53 #define TEFMOD_PHY_CONTROL_FEC_MASK 3 54 55 56 /* So far 4 bits debug mask are used by TEFMOD */ 57 #define TEFMOD_GEN3_DBG_FUNCVAR (1L << 5) /* Local variables in Tier1 */ 58 #define TEFMOD_GEN3_DBG_MEM (1L << 4) /* allocation/object */ 59 #define TEFMOD_GEN3_DBG_REGACC (1L << 3) /* Print all register accesses */ 60 #define TEFMOD_GEN3_DBG_FUNCVALOUT (1L << 2) /* All values returned by Tier1*/ 61 #define TEFMOD_GEN3_DBG_FUNCVALIN (1L << 1) /* All values pumped into Tier1*/ 62 #define TEFMOD_GEN3_DBG_FUNC (1L << 0) /* Every time we enter a Tier1*/ 63 64 typedef enum { 65 TEFMOD_AN_MODE_CL73 = 0, 66 TEFMOD_AN_MODE_CL73BAM, 67 TEFMOD_AN_MODE_HPAM, 68 TEFMOD_AN_MODE_NONE, 69 TEFMOD_AN_MODE_CL73_MSA, 70 TEFMOD_AN_MODE_MSA, 71 TEFMOD_AN_MODE_TYPE_COUNT 72 }tefmod_gen3_an_mode_type_t; 73 74 75 76 typedef enum { 77 TEFMOD_AN_SET_RF_DISABLE = 0, 78 TEFMOD_AN_SET_SGMII_SPEED, 79 TEFMOD_AN_SET_SGMII_MASTER, 80 TEFMOD_AN_SET_HG_MODE, 81 TEFMOD_AN_SET_FEC_MODE, 82 TEFMOD_AN_SET_CL72_MODE, 83 TEFMOD_AN_SET_CL37_ATTR, 84 TEFMOD_AN_SET_CL48_SYNC, 85 TEFMOD_AN_SET_LK_FAIL_INHIBIT_TIMER_NO_CL72, 86 TEFMOD_AN_SET_CL73_FEC_OFF, 87 TEFMOD_AN_SET_CL73_FEC_ON, 88 TEFMOD_AN_SET_SPEED_PAUSE, 89 TEFMOD_AN_SET_TYPE_COUNT 90 }tefmod_gen3_an_set_type_t; 91 92 typedef union { 93 int tefmod_an_set_rf_disable; 94 int tefmod_an_set_sgmii_speed; 95 int tefmod_an_set_sgmii_master; 96 tefmod_gen3_an_set_type_t tefmod_gen3_an_set_cl37_attr; 97 }tefmod_gen3_an_set_value_t; 98 99 typedef enum { 100 TEFMOD_CL73_10GBASE_KR1 = 0, 101 TEFMOD_CL73_40GBASE_KR4, 102 TEFMOD_CL73_40GBASE_CR4, 103 TEFMOD_CL73_100GBASE_KR4, 104 TEFMOD_CL73_100GBASE_CR4, 105 TEFMOD_CL73_1GBASE_KX, 106 TEFMOD_CL73_25GBASE_KR1, 107 TEFMOD_CL73_25GBASE_CR1, 108 TEFMOD_CL73_25GBASE_KRS1, 109 TEFMOD_CL73_25GBASE_CRS1, 110 TEFMOD_CL73_2P5GBASE_KX1, 111 TEFMOD_CL73_5GBASE_KR1, 112 TEFMOD_CL73_SPEED_COUNT 113 }tefmod_gen3_cl73_speed_t; 114 115 typedef enum { 116 TEFMOD_CL73_BAM_20GBASE_KR2 = 0, 117 TEFMOD_CL73_BAM_20GBASE_CR2, 118 TEFMOD_CL73_BAM_40GBASE_KR2, 119 TEFMOD_CL73_BAM_40GBASE_CR2, 120 TEFMOD_CL73_BAM_RESERVED_1, 121 TEFMOD_CL73_BAM_RESERVED_2, 122 TEFMOD_CL73_BAM_50GBASE_KR2, 123 TEFMOD_CL73_BAM_50GBASE_CR2, 124 TEFMOD_CL73_BAM_50GBASE_KR4, 125 TEFMOD_CL73_BAM_50GBASE_CR4, 126 TEFMOD_CL73_BAM_SPEED_COUNT 127 }tefmod_gen3_cl73_bam_speed_t; 128 129 typedef enum { 130 TEFMOD_CL73_BAM_20GBASE_KR1 = 1, 131 TEFMOD_CL73_BAM_20GBASE_CR1, 132 TEFMOD_CL73_BAM_25GBASE_KR1, 133 TEFMOD_CL73_BAM_25GBASE_CR1, 134 TEFMOD_CL73_BAM_SPEED1_COUNT 135 }tefmod_gen3_cl73_bam_speed1_t; 136 137 typedef enum { 138 TEFMOD_NO_PAUSE = 0, 139 TEFMOD_SYMM_PAUSE, 140 TEFMOD_ASYM_PAUSE, 141 TEFMOD_ASYM_SYMM_PAUSE, 142 TEFMOD_AN_PAUSE_COUNT 143 }tefmod_gen3_an_pause_t; 144 145 typedef enum { 146 OVERRIDE_CLEAR = 0x0000, 147 OVERRIDE_NUM_LANES = 0x0001, 148 OVERRIDE_OS_MODE = 0x0002, 149 OVERRIDE_T_FIFO_MODE = 0x0004, 150 OVERRIDE_T_ENC_MODE = 0x0008, 151 OVERRIDE_T_HG2_ENABLE = 0x0010, 152 OVERRIDE_T_PMA_BTMX_MODE_OEN = 0x0020, 153 OVERRIDE_SCR_MODE = 0x0040, 154 OVERRIDE_DESCR_MODE_OEN = 0x0100, 155 OVERRIDE_DEC_TL_MODE = 0x0200, 156 OVERRIDE_DESKEW_MODE = 0x0400, 157 OVERRIDE_DEC_FSM_MODE = 0x0800, 158 OVERRIDE_R_HG2_ENABLE = 0x8001, 159 OVERRIDE_BS_SM_SYNC_MODE_OEN = 0x8002, 160 OVERRIDE_BS_SYNC_EN_OEN = 0x8004, 161 OVERRIDE_BS_DIST_MODE_OEN = 0x8008, 162 OVERRIDE_BS_BTMX_MODE_OEN = 0x8010, 163 OVERRIDE_CL72_EN = 0x8020, 164 OVERRIDE_CLOCKCNT0 = 0xf040, 165 OVERRIDE_CLOCKCNT1 = 0x8080, 166 OVERRIDE_LOOPCNT0 = 0x8100, 167 OVERRIDE_LOOPCNT1 = 0x8200, 168 OVERRIDE_MAC_CREDITGENCNT = 0x8400, 169 OVERRIDE_NUM_LANES_DIS = 0xff01, 170 OVERRIDE_OS_MODE_DIS = 0xff02, 171 OVERRIDE_T_FIFO_MODE_DIS = 0xff03, 172 OVERRIDE_T_ENC_MODE_DIS = 0xff04, 173 OVERRIDE_T_HG2_ENABLE_DIS = 0xff05, 174 OVERRIDE_T_PMA_BTMX_MODE_OEN_DIS= 0xff06, 175 OVERRIDE_SCR_MODE_DIS = 0xff07, 176 OVERRIDE_DESCR_MODE_OEN_DIS = 0xff08, 177 OVERRIDE_DEC_TL_MODE_DIS = 0xff09, 178 OVERRIDE_DESKEW_MODE_DIS = 0xff0a, 179 OVERRIDE_DEC_FSM_MODE_DIS = 0xff0b, 180 OVERRIDE_R_HG2_ENABLE_DIS = 0xff0c, 181 OVERRIDE_BS_SM_SYNC_MODE_OEN_DIS= 0xff0d, 182 OVERRIDE_BS_SYNC_EN_OEN_DIS = 0xff0e, 183 OVERRIDE_BS_DIST_MODE_OEN_DIS = 0xff0f, 184 OVERRIDE_BS_BTMX_MODE_OEN_DIS = 0xff10, 185 OVERRIDE_CL72_EN_DIS = 0xff11, 186 OVERRIDE_CLOCKCNT0_DIS = 0xff12, 187 OVERRIDE_CLOCKCNT1_DIS = 0xff13, 188 OVERRIDE_LOOPCNT0_DIS = 0xff14, 189 OVERRIDE_LOOPCNT1_DIS = 0xff15, 190 OVERRIDE_MAC_CREDITGENCNT_DIS = 0xff16 191 } override_type_t; 192 193 typedef enum { 194 TEFMOD_HG2_CODEC_OFF = 0, 195 TEFMOD_HG2_CODEC_ON_8BYTE_IPG, 196 TEFMOD_HG2_CODEC_ON_9BYTE_IPG, 197 TEFMOD_HG2_CODEC_COUNT 198 }tefmod_gen3_hg2_codec_t; 199 200 /** 201 \struct tefmod_gen3_an_adv_ability_s 202 TBD 203 */ 204 205 typedef struct tefmod_gen3_an_adv_ability_s{ 206 tefmod_gen3_cl73_speed_t an_base_speed; 207 tefmod_gen3_cl73_bam_speed_t an_bam_speed; 208 tefmod_gen3_cl73_bam_speed1_t an_bam_speed1; 209 uint16_t an_nxt_page; 210 tefmod_gen3_an_pause_t an_pause; 211 uint16_t an_fec; 212 uint16_t an_cl72; 213 uint16_t an_hg2; 214 }tefmod_gen3_an_adv_ability_t; 215 216 typedef struct tefmod_gen3_an_ability_s{ 217 tefmod_gen3_an_adv_ability_t cl73_adv; /*includes cl73 and cl73-bam related */ 218 }tefmod_gen3_an_ability_t; 219 220 /** 221 \struct tefmod_gen3_an_oui_s 222 oui : New oui 223 override_bam73_adv : Adv new OUI for BAM73 224 override_bam73_det : Detect new OUI for BAM73 225 override_hpam_adv : Adv new OUI for HPAM 226 override_hpam_det : Detect new OUI for HPAM 227 */ 228 typedef struct tefmod_gen3_an_oui_s { 229 uint32_t oui; 230 uint16_t oui_override_bam73_adv; 231 uint16_t oui_override_bam73_det; 232 uint16_t oui_override_hpam_adv; 233 uint16_t oui_override_hpam_det; 234 } tefmod_gen3_an_oui_t; 235 236 typedef struct tefmod_gen3_an_control_s { 237 tefmod_gen3_an_mode_type_t an_type; 238 uint16_t num_lane_adv; 239 uint16_t enable; 240 uint16_t pd_kx_en; 241 uint16_t pd_2P5G_kx_en; 242 an_property_enable an_property_type; 243 uint16_t cl72_config_allowed; 244 } tefmod_gen3_an_control_t; 245 246 /** 247 \struct tefmod_gen3_an_init_s 248 249 This embodies all parameters required to program autonegotiation features in the 250 PHY for both CL37 and CL73 type autonegotiation and the BAM variants. 251 For details of individual fields, please refer to microarchitectural doc. 252 */ 253 typedef struct tefmod_gen3_an_init_s{ 254 uint16_t an_fail_cnt; 255 uint16_t linkfailtimer_dis; 256 uint16_t linkfailtimerqua_en; 257 uint16_t an_good_check_trap; 258 uint16_t an_good_trap; 259 uint16_t bam73_adv_oui; 260 uint16_t bam73_det_oui; 261 uint16_t hpam_adv_oui; 262 uint16_t hpam_det_oui; 263 uint16_t disable_rf_report; 264 uint16_t cl73_remote_fault; 265 uint16_t cl73_nonce_match_over; 266 uint16_t cl73_nonce_match_val; 267 uint16_t cl73_transmit_nonce; 268 uint16_t base_selector; 269 } tefmod_gen3_an_init_t; 270 271 typedef struct tefmod_gen3_ts_tx_info_s { 272 uint16_t ts_val_lo; 273 uint16_t ts_val_hi; 274 uint16_t ts_seq_id; 275 uint16_t ts_sub_nanosec; 276 } tefmod_gen3_ts_tx_info_t; 277 278 /** 279 \struct tefmod_gen3_an_timers_s 280 TBD 281 */ 282 typedef struct tefmod_gen3_an_timers_s{ 283 uint16_t value; 284 } tefmod_gen3_an_timers_t; 285 286 /* definitions for SW AN PAGE */ 287 #define BRCM_OUI 0xAF7 288 #define BRCM_BAM_CODE 0x3 289 #define HP_OUI 0x643150 290 #define HP_USR_DEF_FIELD 0xABE20 291 #define MSA_OUI 0x6A737D /* OUI defined for consortium 25G */ 292 #define MSA_OUI_13to23 0x353 293 #define MSA_OUT_2to12 0x4DF 294 #define MSA_OUI_0to1 0x1 295 #define EXT_TECH_ABILITY_CODE 0x3 296 #define MSA_MSG_CODE 0x5 297 298 #define OS_MODE_1 0 299 #define OS_MODE_2 1 300 #define OS_MODE_4 2 301 #define OS_MODE_8p25 4 302 #define OS_MODE_16p5 8 303 #define OS_MODE_20p625 12 304 305 /* Below macros are defined based on IEEE and MSA 25G spec 306 * for detailed information Please refer to the 307 * IEEE 802.3by section 73.6 Link codeword encoding 308 * MSA Spec section 3.2.5 Auto-negotiation Figure 10 309 */ 310 311 #define AN_BASE0_PAGE_IEEE_SEL_MASK 0x1F 312 #define AN_BASE0_PAGE_IEEE_SEL_OFFSET 0x0 313 314 #define AN_BASE0_PAGE_CL73_NOUNCE_MASK 0x1F 315 #define AN_BASE0_PAGE_CL73_NOUNCE_OFFSET 0x5 316 317 /* pause capability not related to PHY */ 318 #define AN_BASE0_PAGE_CAP_MASK 0x3 319 #define AN_BASE0_PAGE_CAP_OFFSET 0xA 320 321 #define AN_BASE0_PAGE_REMOTE_FAULT_MASK 0x1 322 #define AN_BASE0_PAGE_REMOTE_FAULT_OFFSET 0xD 323 324 /* acknowledgement bit postion */ 325 #define AN_BASE0_PAGE_ACK_MASK 0x1 326 #define AN_BASE0_PAGE_ACK_OFFSET 0xE 327 328 /* Next Page bit postion */ 329 #define AN_BASE0_PAGE_NP_MASK 0x1 330 #define AN_BASE0_PAGE_NP_OFFSET 0xF 331 332 333 #define AN_BASE1_PAGE_TX_NOUNCE_MASK 0x1F 334 #define AN_BASE1_PAGE_TX_NOUNCE_OFFSET 0x0 335 336 #define AN_BASE1_PAGE_ABILITY_MASK 0x7FF 337 #define AN_BASE1_PAGE_ABILITY_OFFSET 0x5 338 339 #define AN_BASE_TECH_ABILITY_1000KX_MASK 0x1 340 #define AN_BASE_TECH_ABILITY_1000KX_OFFSET 0x5 341 342 #define AN_BASE_TECH_ABILITY_10GKX4_MASK 0x1 343 #define AN_BASE_TECH_ABILITY_10GKX4_OFFSET 0x6 344 345 #define AN_BASE_TECH_ABILITY_10GKR_MASK 0x1 346 #define AN_BASE_TECH_ABILITY_10GKR_OFFSET 0x7 347 348 #define AN_BASE_TECH_ABILITY_40GKR4_MASK 0x1 349 #define AN_BASE_TECH_ABILITY_40GKR4_OFFSET 0x8 350 351 #define AN_BASE_TECH_ABILITY_40GCR4_MASK 0x1 352 #define AN_BASE_TECH_ABILITY_40GCR4_OFFSET 0x9 353 354 #define AN_BASE_TECH_ABILITY_100GCR10_MASK 0x1 355 #define AN_BASE_TECH_ABILITY_100GCR10_OFFSET 0xA 356 357 #define AN_BASE_TECH_ABILITY_100GKP4_MASK 0x1 358 #define AN_BASE_TECH_ABILITY_100GKP4_OFFSET 0xB 359 360 #define AN_BASE_TECH_ABILITY_100GKR4_MASK 0x1 361 #define AN_BASE_TECH_ABILITY_100GKR4_OFFSET 0xC 362 363 #define AN_BASE_TECH_ABILITY_100GCR4_MASK 0x1 364 #define AN_BASE_TECH_ABILITY_100GCR4_OFFSET 0xD 365 366 #define AN_BASE_TECH_ABILITY_25GKRS_MASK 0x1 367 #define AN_BASE_TECH_ABILITY_25GKRS_OFFSET 0xE 368 369 #define AN_BASE_TECH_ABILITY_25GKR_MASK 0x1 370 #define AN_BASE_TECH_ABILITY_25GKR_OFFSET 0xF 371 372 #define AN_BASE2_PAGE_ABILITY_RSVD_MASK 0xFF7 373 #define AN_BASE2_PAGE_ABILITY_RSVD_OFFSET 0x0 374 375 #define AN_BASE2_PAGE_FEC_ABILITY_MASK 0xF 376 #define AN_BASE2_PAGE_FEC_ABILITY_OFFSET 0xC 377 378 #define AN_BASE_CL74_ABILITY_SUP_MASK 0x1 379 #define AN_BASE_CL74_ABILITY_SUP_OFFSET 0xE 380 381 #define AN_BASE_CL74_ABILITY_REQ_MASK 0x1 382 #define AN_BASE_CL74_ABILITY_REQ_OFFSET 0xF 383 384 #define AN_BASE_CL91_ABILITY_REQ_MASK 0x1 385 #define AN_BASE_CL91_ABILITY_REQ_OFFSET 0xC 386 387 #define AN_BASE_CL74_25GKRS_REQ_MASK 0x1 388 #define AN_BASE_CL74_25GKRS_REQ_OFFSET 0xD 389 390 /* Message Page definitions */ 391 392 #define AN_MSG_PAGE0_MSG_CODE_MASK 0x3FF 393 #define AN_MSG_PAGE0_MSG_CODE_OFFSET 0x0 394 395 #define AN_MSG_PAGE0_TOGGLE_MASK 0x1 396 #define AN_MSG_PAGE0_TOGGLE_OFFSET 0xB 397 398 #define AN_MSG_PAGE0_ACK2_MASK 0x1 399 #define AN_MSG_PAGE0_ACK2_OFFSET 0xC 400 401 #define AN_MSG_PAGE0_MSG_PAGE_MASK 0x1 402 #define AN_MSG_PAGE0_MSG_PAGE_OFFSET 0xD 403 404 #define AN_MSG_PAGE0_ACK_MASK 0x1 405 #define AN_MSG_PAGE0_ACK_OFFSET 0xE 406 407 #define AN_MSG_PAGE0_NP_MASK 0x1 408 #define AN_MSG_PAGE0_NP_OFFSET 0xF 409 410 #define AN_MSG_PAGE1_OUI_13to23_MASK 0x7FF 411 #define AN_MSG_PAGE1_OUI_13to23_OFFSET 0x0 412 413 #define AN_MSG_PAGE2_OUI_2to12_MASK 0x7FF 414 #define AN_MSG_PAGE2_OUI_2to12_OFFSET 0x0 415 416 /* Unformatted Page for MSA */ 417 418 #define AN_UF_PAGE0_EXT_TECH_ABILITY_MASK 0xFF 419 #define AN_UF_PAGE0_EXT_TECH_ABILITY_OFFSET 0x0 420 421 #define AN_UF_PAGE0_OUI_MASK 0x3 422 #define AN_UF_PAGE0_OUI_OFFSET 0x9 423 424 #define AN_UF_PAGE0_TOGGLE_MASK 0x1 425 #define AN_UF_PAGE0_TOGGLE_OFFSET 0xB 426 427 #define AN_UF_PAGE0_ACK_MASK 0x1 428 #define AN_UF_PAGE0_ACK_OFFSET 0xE 429 430 #define AN_UF_PAGE0_NP_MASK 0x1 431 #define AN_UF_PAGE0_NP_OFFSET 0xF 432 433 #define AN_UF_PAGE1_25G_KR1_ABILITY_MASK 0x1 434 #define AN_UF_PAGE1_25G_KR1_ABILITY_OFFSET 0x4 435 436 #define AN_UF_PAGE1_25G_CR1_ABILITY_MASK 0x1 437 #define AN_UF_PAGE1_25G_CR1_ABILITY_OFFSET 0x5 438 439 #define AN_UF_PAGE1_50G_KR2_ABILITY_MASK 0x1 440 #define AN_UF_PAGE1_50G_KR2_ABILITY_OFFSET 0x8 441 442 #define AN_UF_PAGE1_50G_CR2_ABILITY_MASK 0x1 443 #define AN_UF_PAGE1_50G_CR2_ABILITY_OFFSET 0x9 444 445 #define AN_UF_PAGE2_CL91_SUPPORT_MASK 0x1 446 #define AN_UF_PAGE2_CL91_SUPPORT_OFFSET 0x8 447 448 #define AN_UF_PAGE2_CL74_SUPPORT_MASK 0x1 449 #define AN_UF_PAGE2_CL74_SUPPORT_OFFSET 0x9 450 451 #define AN_UF_PAGE2_CL91_REQ_MASK 0x1 452 #define AN_UF_PAGE2_CL91_REQ_OFFSET 0xA 453 454 #define AN_UF_PAGE2_CL74_REQ_MASK 0x1 455 #define AN_UF_PAGE2_CL74_REQ_OFFSET 0xB 456 457 #define TEFMOD_GEN3_25G_KR_SPD_IF 0x11 458 #define TEFMOD_GEN3_25G_CR_SPD_IF 0x10 459 460 #define TEFMOD_GEN3_50G_KR2_SPD_IF 0x31 461 #define TEFMOD_GEN3_50G_CR2_SPD_IF 0x30 462 463 #define TEFMOD_GEN3_100G_KR4_SPD_IF 0x41 464 #define TEFMOD_GEN3_100G_CR4_SPD_IF 0x40 465 466 #define HCD_SPEED_ID_UNDEFINED 0xFF 467 468 typedef enum ieee_sel_e { 469 IEEE_SEL_RSVD = 0, 470 IEEE_SEL_802P3, 471 IEEE_SEL_802P9, 472 IEEE_SEL_802P5, 473 IEEE_SEL_1394 474 } ieee_sel_t; 475 476 typedef enum an_page_id_e { 477 TEFMOD_AN_PAGE_ID_NONE = 0, 478 TEFMOD_AN_PAGE_ID_BASE_PAGE, 479 TEFMOD_AN_PAGE_ID_MSG_PAGE, 480 TEFMOD_AN_PAGE_ID_UP_PAGE, 481 TEFMOD_AN_PAGE_ID_NULL_PAGE, 482 TEFMOD_AN_PAGE_ID_MAX 483 } an_page_id_t; 484 485 typedef enum { 486 TEFMOD_GEN3_NO_CL91_FEC = 0, 487 TEFMOD_GEN3_CL91_SINGLE_LANE_FC, 488 TEFMOD_GEN3_CL91_SINGLE_LANE_BRCM_PROP, 489 TEFMOD_GEN3_CL91_DUAL_LANE_BRCM_PROP, 490 TEFMOD_GEN3_CL91_QUAD_LANE, 491 TEFMOD_GEN3_IEEE_25G_CL91_SINGLE_LANE, 492 TEFMOD_GEN3_CL91_COUNT 493 }tefmod_gen3_cl91_fec_mode_t; 494 495 #ifdef CHECKIFNEEDED 496 497 extern int get_mapped_speed(tefmod_gen3_spd_intfc_type spd_intf, int *speed); 498 extern int get_actual_speed(int speed_id, int *speed); 499 500 #endif 501 extern int phymod_debug_check(uint32_t flags, PHYMOD_ST *pc); 502 503 extern int configure_st_entry(int st_entry_num, int st_entry_speed, PHYMOD_ST *pc); 504 505 extern int tefmod_gen3_pmd_os_mode_set(PHYMOD_ST *pc, tefmod_gen3_spd_intfc_type_t spd_intf, phymod_ref_clk_t refclk, int os_mode); 506 extern int tefmod_gen3_pmd_x4_reset(PHYMOD_ST *pc); 507 extern int tefmod_gen3_tx_loopback_get(PHYMOD_ST *pc, uint32_t *enable); 508 extern int tefmod_gen3_firmware_set(PHYMOD_ST *pc); 509 extern int tefmod_gen3_tx_lane_disable (PHYMOD_ST *pc, int tx); 510 extern int tefmod_gen3_init_pcs_ilkn(PHYMOD_ST *pc); 511 extern int tefmod_gen3_pcs_ilkn_chk(PHYMOD_ST *pc, int *ilkn_set); 512 extern int tefmod_gen3_pmd_reset_bypass (PHYMOD_ST *pc, int pmd_reset_control); 513 extern int tefmod_gen3_afe_speed_up_dsc_vga(PHYMOD_ST *pc); 514 extern int tefmod_gen3_get_pll_div(PHYMOD_ST *pc, uint32_t *plldiv_r_val); 515 extern int tefmod_gen3_update_port_mode_select(PHYMOD_ST *pc, tefmod_gen3_port_type_t port_type, int master_port, int tsc_clk_freq_pll_by_48, int pll_reset_en); 516 extern int tefmod_gen3_set_port_mode(PHYMOD_ST *pc, int refclk, int plldiv, tefmod_gen3_port_type_t port_type, int master_port, int tsc_clk_freq_pll_by_48, int pll_reset_en); 517 extern int tefmod_gen3_tx_loopback_control(PHYMOD_ST *pc, int pcs_gloop_en, int starting_lane, int num_lanes); 518 extern int tefmod_gen3_tx_pmd_loopback_control(PHYMOD_ST* pc, int pmd_gloop_en); 519 extern int tefmod_gen3_rx_loopback_control(PHYMOD_ST *pc, int pcs_rloop_en); 520 extern int tefmod_gen3_rx_pmd_loopback_control(PHYMOD_ST *pc, int pcs_rloop_en, int pmd_rloop_en, int lane); 521 extern int tefmod_gen3_credit_set(PHYMOD_ST *pc); 522 extern int tefmod_gen3_encode_set(PHYMOD_ST *pc, int per_lane_control, tefmod_gen3_spd_intfc_type_t spd_intf, int tx_am_timer_init_val); 523 extern int tefmod_gen3_lf_rf_control(PHYMOD_ST *pc); 524 extern int tefmod_gen3_decode_set(PHYMOD_ST *pc); 525 extern int tefmod_gen3_trigger_speed_change(PHYMOD_ST *pc); 526 extern int tefmod_gen3_set_override_0(PHYMOD_ST *pc, int per_field_override_en); 527 extern int tefmod_gen3_set_override_1(PHYMOD_ST *pc, int per_lane_control, uint32_t per_field_override_en); 528 extern int tefmod_gen3_credit_control(PHYMOD_ST *pc, int per_lane_control); 529 extern int tefmod_gen3_tx_lane_control_set(PHYMOD_ST *pc, tefmod_gen3_tx_disable_enum_t dis); 530 extern int tefmod_gen3_tx_lane_control_get(PHYMOD_ST *pc, int *reset, int *enable); 531 extern int tefmod_gen3_rx_lane_control(PHYMOD_ST *pc, int accData, int per_lane_control); 532 extern int tefmod_gen3_bypass_sc(PHYMOD_ST *pc); 533 extern int tefmod_gen3_revid_read(PHYMOD_ST *pc, uint32_t *revIdV); 534 extern int tefmod_gen3_clause72_control(PHYMOD_ST* pc, int per_lane_control); 535 extern int tefmod_gen3_prbs_check(PHYMOD_ST *pc, int accData); 536 extern int tefmod_gen3_prbs_mode(PHYMOD_ST *pc, int per_lane_control); 537 extern int tefmod_gen3_prbs_control(PHYMOD_ST *pc, int per_lane_control); 538 extern int tefmod_gen3_cjpat_crpat_control(PHYMOD_ST *pc); 539 extern int tefmod_gen3_cjpat_crpat_check(PHYMOD_ST *pc); 540 extern int tefmod_gen3_tx_bert_control(PHYMOD_ST *pc); 541 extern int tefmod_gen3_FEC_control(PHYMOD_ST *pc, tefmod_gen3_fec_type_t fec_type, int enable, int cl74or91); 542 extern int tefmod_gen3_FEC_get(PHYMOD_ST *pc, tefmod_gen3_fec_type_t fec_type, int *fec_en); 543 extern int tefmod_gen3_power_control(PHYMOD_ST *pc, int tx, int rx); 544 extern int tefmod_gen3_duplex_control(PHYMOD_ST *pc); 545 extern int tefmod_gen3_disable_pcs_falcon(PHYMOD_ST *pc); 546 extern int tefmod_gen3_pmd_lane_swap(PHYMOD_ST *pc, int tx_lane_swap, int rx_lane_swap); 547 extern int tefmod_gen3_pcs_tx_lane_swap(PHYMOD_ST *pc, int tx_lane_swap); 548 extern int tefmod_gen3_pcs_rx_lane_swap(PHYMOD_ST *pc, int rx_lane_swap); 549 extern int tefmod_gen3_pmd_reset_remove(PHYMOD_ST *pc, int pmd_touched); 550 extern int tefmod_gen3_init_pcs_falcon(PHYMOD_ST *pc); 551 extern int tefmod_gen3_init_pmd_falcon(PHYMOD_ST *pc); 552 extern int tefmod_gen3_set_sc_speed(PHYMOD_ST* pc); 553 extern int tefmod_gen3_poll_for_sc_done(PHYMOD_ST *pc, int mapped_speed); 554 extern int tefmod_gen3_check_status(PHYMOD_ST *pc); 555 extern int tefmod_gen3_set_port_mode_sel(PHYMOD_ST *pc, int tsc_touched, tefmod_gen3_port_type_t port_type); 556 extern int tefmod_gen3_init_pcs_fs(PHYMOD_ST *pc); 557 extern int tefmod_gen3_init_pcs_an(PHYMOD_ST *pc); 558 extern int tefmod_gen3_set_an_override(PHYMOD_ST *pc); 559 extern int tefmod_gen3_tx_squelch_get(PHYMOD_ST *pc, int *val); 560 extern int tefmod_gen3_refclk_get(PHYMOD_ST *pc, phymod_ref_clk_t *ref_clk); 561 extern int tefmod_gen3_refclk_set(PHYMOD_ST *pc, phymod_ref_clk_t ref_clock); 562 563 extern int tefmod_gen3_get_mapped_speed(tefmod_gen3_spd_intfc_type_t spd_intf, int *speed); 564 extern int tefmod_gen3_toggle_sw_speed_change(PHYMOD_ST* pc); 565 566 extern int tefmod_gen3_autoneg_get(PHYMOD_ST* pc); 567 568 extern int tefmod_gen3_get_mapped_speed(tefmod_gen3_spd_intfc_type_t spd_intf, int *speed); 569 extern int tefmod_gen3_am_bits_get(int speed, uint32_t *am_bits); 570 extern int tefmod_gen3_txrx_fixed_latency_get(int speed, uint16_t *tx_fixed_int, uint16_t *tx_fixed_frac, uint16_t *rx_fixed_int, uint16_t *rx_fixed_frac); 571 extern int tefmod_gen3_ui_values_get(int speed, uint16_t *ui_msb, uint16_t *ui_lsb); 572 extern int tefmod_gen3_get_vl_bml(int speed, uint16_t *vl, uint16_t *bml); 573 574 int tefmod_gen3_set_an_port_mode(PHYMOD_ST* pc, int num_of_lanes, int starting_lane); 575 extern int tefmod_gen3_set_an_single_port_mode(PHYMOD_ST* pc, int an_enable); 576 extern int tefmod_gen3_set_spd_intf(PHYMOD_ST *pc, tefmod_gen3_spd_intfc_type_t spd_intf); 577 extern int tefmod_gen3_autoneg_set_init(PHYMOD_ST* pc, tefmod_gen3_an_init_t *an_init_st); 578 extern int tefmod_gen3_autoneg_timer_init(PHYMOD_ST* pc); 579 extern int tefmod_gen3_autoneg_control(PHYMOD_ST* pc, tefmod_gen3_an_control_t *an_control); 580 extern int tefmod_gen3_autoneg_ability_set(PHYMOD_ST* pc, tefmod_gen3_an_adv_ability_t *an_ability_st); 581 extern int tefmod_gen3_diag(PHYMOD_ST *ws, tefmod_gen3_diag_type_t diag_type); 582 extern int tefmod_gen3_diag_disp(PHYMOD_ST *ws, const char *arg); 583 extern int tefmod_gen3_autoneg_control_get(PHYMOD_ST *pc, tefmod_gen3_an_control_t *an_control, int *an_complete); 584 extern int tefmod_gen3_autoneg_ability_get(PHYMOD_ST *pc, tefmod_gen3_an_adv_ability_t *an_ability_st); 585 extern int tefmod_gen3_autoneg_remote_ability_get(PHYMOD_ST *pc, tefmod_gen3_an_adv_ability_t *an_ability_st); 586 extern int tefmod_gen3_st_control_field_set (PHYMOD_ST *pc, uint16_t st_entry_no, override_type_t st_control_field, uint16_t st_field_value); 587 extern int tefmod_gen3_port_enable_set(PHYMOD_ST *pc, int enable); 588 extern int tefmod_gen3_tx_squelch_set(PHYMOD_ST *pc, int enable); 589 extern int tefmod_gen3_rx_squelch_set(PHYMOD_ST *pc, int enable); 590 extern int tefmod_gen3_rx_squelch_get(PHYMOD_ST *pc, int *enable); 591 extern int tefmod_gen3_default_init(PHYMOD_ST* pc); 592 extern int tefmod_gen3_pmd_x4_reset_get(PHYMOD_ST *pc, int *is_in_reset); 593 594 extern int tefmod_gen3_port_enable_get(PHYMOD_ST *pc, int *tx_enable, int *rx_enable); 595 extern int tefmod_gen3_pll_lock_get(PHYMOD_ST *pc, int* lockStatus); 596 extern int tefmod_gen3_pmd_lock_get(PHYMOD_ST *pc, uint32_t* lockStatus); 597 extern int tefmod_gen3_set_pll_mode(PHYMOD_ST *pc, int pmd_touched, tefmod_gen3_spd_intfc_type_t spd_intf, int pll_mode); 598 extern int tefmod_gen3_speed_id_get(PHYMOD_ST *pc, int *speed_id); 599 extern int tefmod_gen3_pmd_reset_seq(PHYMOD_ST *pc, int pmd_touched); 600 extern int tefmod_gen3_master_port_num_set( PHYMOD_ST *pc, int port_num); 601 extern int tefmod_gen3_port_mode_select( PHYMOD_ST *pc); 602 extern int tefmod_gen3_pll_reset_enable_set (PHYMOD_ST *pc , int enable); 603 extern int tefmod_gen3_get_pcs_link_status(PHYMOD_ST* pc, uint32_t *link); 604 extern int tefmod_gen3_get_pcs_latched_link_status(PHYMOD_ST* pc, uint32_t *link); 605 extern int tefmod_gen3_disable_get(PHYMOD_ST* pc, uint32_t* enable); 606 extern int tefmod_gen3_disable_set(PHYMOD_ST* pc); 607 extern int tefmod_gen3_enable_set(PHYMOD_ST* pc); 608 extern int tefmod_gen3_pll_div_lkup_get(PHYMOD_ST* pc, tefmod_gen3_spd_intfc_type_t spd_intf, phymod_ref_clk_t refclk, uint32_t* plldiv); 609 extern int tefmod_gen3_pll_div_get(PHYMOD_ST* pc, uint32_t* pll0_div, uint32_t* pll1_div); 610 extern int tefmod_gen3_osmode_lkup_get(PHYMOD_ST *pc, tefmod_gen3_spd_intfc_type_t spd_intf, phymod_ref_clk_t refclk, uint32_t *osmode); 611 extern int tefmod_gen3_pmd_lane_swap_tx_rx_get ( PHYMOD_ST* pc, uint32_t *tx_lane_map, uint32_t *rx_lane_map); 612 extern int tefmod_gen3_rx_lane_control_set(PHYMOD_ST *pc, int enable); 613 extern int tefmod_gen3_rx_lane_control_get(PHYMOD_ST *pc, int* enable); 614 extern int tefmod_gen3_tx_rx_polarity_get ( PHYMOD_ST *pc, uint32_t *tx_polarity, uint32_t *rx_polarity); 615 extern int tefmod_gen3_tx_rx_polarity_set ( PHYMOD_ST *pc, uint32_t tx_polarity, uint32_t rx_polarity); 616 617 int tefmod_gen3_eee_control_set(PHYMOD_ST *pc, uint32_t enable); 618 int tefmod_gen3_eee_control_get(PHYMOD_ST *pc, uint32_t *enable); 619 int tefmod_gen3_cl74_chng_default (PHYMOD_ST *pc); 620 int tefmod_gen3_cl91_ecc_clear(PHYMOD_ST *pc); 621 622 extern int tefmod_gen3_an_msa_mode_set(PHYMOD_ST *pc, uint32_t val); 623 extern int tefmod_gen3_an_msa_mode_get(PHYMOD_ST *pc, uint32_t *val); 624 extern int tefmod_gen3_an_oui_set(PHYMOD_ST *pc, tefmod_gen3_an_oui_t oui); 625 extern int tefmod_gen3_an_oui_get(PHYMOD_ST *pc, tefmod_gen3_an_oui_t *oui); 626 extern int tefmod_gen3_autoneg_status_get(PHYMOD_ST *pc, int *an_en, int *an_done); 627 extern int tefmod_gen3_autoneg_lp_status_get(PHYMOD_ST *pc, uint16_t *baseP0, uint16_t *baseP1, uint16_t *baseP2, uint16_t *nextP3, uint16_t *nextP4); 628 extern int tefmod_gen3_hg2_codec_set(PHYMOD_ST *pc, tefmod_gen3_hg2_codec_t hg2_codec); 629 extern int tefmod_gen3_hg2_codec_get(PHYMOD_ST *pc, tefmod_gen3_hg2_codec_t *hg2_codec); 630 631 extern int tefmod_gen3_fec_correctable_counter_get(PHYMOD_ST *pc, uint32_t *count); 632 extern int tefmod_gen3_fec_uncorrectable_counter_get(PHYMOD_ST *pc, uint32_t *count); 633 extern int tefmod_gen3_fec_cl91_correctable_counter_get(PHYMOD_ST *pc, uint32_t *count); 634 extern int tefmod_gen3_fec_cl91_uncorrectable_counter_get(PHYMOD_ST *pc, uint32_t *count); 635 extern int tefmod_gen3_pcs_ilkn_mode_set(PHYMOD_ST *pc); /* INIT_PCS_ILKN */ 636 extern int tefmod_gen3_pmd_ln_h_rstb_pkill_override(PHYMOD_ST *pc, int value); 637 extern int tefmod_gen3_pmd_ams_pll_idq_set(PHYMOD_ST *pc, const phymod_afe_pll_t *afe_pll); 638 extern int tefmod_gen3_pmd_core_dp_reset(PHYMOD_ST *pc, int enable); 639 extern int tefmod_gen3_pll_mode_set(PHYMOD_ST *pc, int pll_mode); 640 extern int tefmod_gen3_pll_mode_get(PHYMOD_ST *pc, int *pll_mode); 641 extern int tefmod_gen3_uc_active_get(PHYMOD_ST *pc, uint32_t *enable); 642 extern int tefmod_gen3_configure_pll(phymod_access_t *pc, phymod_tscf_pll_multiplier_t pll_mode, phymod_ref_clk_t ref_clk); 643 extern int tefmod_gen3_pll_to_vco_rate(PHYMOD_ST *pc, phymod_tscf_pll_multiplier_t pll_mode, phymod_ref_clk_t ref_clk, uint32_t *vco_rate); 644 extern int tefmod_gen3_pmd_reset_seq_dp(PHYMOD_ST *pc, int pmd_touched); 645 extern int tefmod_gen3_pll_multiplier_get(uint32_t pll_div, uint32_t *pll_multiplier); 646 extern int tefmod_gen3_pcs_tx_lane_swap_get(PHYMOD_ST *pc, uint32_t *tx_swap); 647 extern int tefmod_gen3_pcs_rx_lane_swap_get(PHYMOD_ST *pc, uint32_t *rx_swap); 648 extern int tefmod_gen3_pll_idx_set(phymod_access_t *pa, int pll_idx); 649 extern int tefmod_gen3_pll_select_set(PHYMOD_ST *pc, int pll_select); 650 extern int tefmod_gen3_pll_select_get(PHYMOD_ST *pc, int *pll_select); 651 extern int tefmod_gen3_25g_rsfec_am_init(PHYMOD_ST *pc); 652 extern int tefmod_gen3_1588_rx_deskew_set(PHYMOD_ST* pc, phymod_timesync_compensation_mode_t timesync_am_norm_mode); 653 extern int tefmod_gen3_1588_txrx_fixed_latency_set(PHYMOD_ST* pc); 654 extern int tefmod_gen3_1588_ui_values_set(PHYMOD_ST* pc); 655 extern int tefmod_gen3_1588_fclk_set(PHYMOD_ST* pc); 656 extern int tefmod_gen3_1588_pcs_control_set(PHYMOD_ST* pc); 657 extern int tefmod_gen3_1588_ts_offset_set(PHYMOD_ST *pc, uint32_t offset); 658 extern int tefmod_gen3_1588_ts_enable_get(PHYMOD_ST *pc, uint32_t *enable); 659 extern int tefmod_gen3_1588_ts_enable_set(PHYMOD_ST *pc, uint32_t enable); 660 661 extern int tefmod_gen3_encode_mode_get(PHYMOD_ST* pc, tefmod_gen3_encode_mode *mode); 662 extern int tefmod_gen3_bip_error_counter_get(PHYMOD_ST* pc, uint32_t* count); 663 extern int tefmod_gen3_cl49_ber_counter_get(PHYMOD_ST* pc, uint32_t* count); 664 extern int tefmod_gen3_cl82_ber_counter_get(PHYMOD_ST* pc, uint32_t* count); 665 666 extern int tefmod_gen3_lane_soft_reset(PHYMOD_ST* pc, int enable); 667 668 extern int tefmod_gen3_1588_tx_info_get(PHYMOD_ST* pc, tefmod_gen3_ts_tx_info_t* ts_tx_info); 669 670 extern int tefmod_gen3_synce_stg0_mode_set(PHYMOD_ST *pc, int mode); 671 extern int tefmod_gen3_synce_stg0_mode_get(PHYMOD_ST *pc, int *mode); 672 extern int tefmod_gen3_synce_stg1_mode_set(PHYMOD_ST *pc, int mode); 673 extern int tefmod_gen3_synce_stg1_mode_get(PHYMOD_ST *pc, int *mode); 674 extern int tefmod_gen3_synce_clk_ctrl_set(PHYMOD_ST *pc, uint32_t val); 675 extern int tefmod_gen3_synce_clk_ctrl_get(PHYMOD_ST *pc, uint32_t *val); 676 #endif /* _tefmod_gen3_H_ */ 677