tf16PCSRegEnums.h (1737708B)
1 /*************************************************************************** 2 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 3 * 4 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 5 * 6 * 7 * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE 8 * AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR 9 * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT. 10 * 11 * $brcm_Workfile: $ 12 * $brcm_Revision: $ 13 * $brcm_Date: $ 14 * 15 * Module Description: 16 * DO NOT EDIT THIS FILE DIRECTLY 17 * 18 * This module was generated magically with RDB from a source description 19 * file. You must edit the source file for changes to be made to this file. 20 * 21 * 22 * Date: Generated on Mon Jun 8 16:48:39 2015 23 * MD5 Checksum aa6f8a52532334e5d986d273d2283ed2 24 * 25 * Compiled with: RDB Utility 5.0 26 * RDB Parser 3.0 27 * rdb2macro.pm 4.0 28 * Perl Interpreter 5.014001 29 * Operating System linux 30 * 31 * Spec Versions: an_x1_control 1 32 * an_x1_sw_mgmt 1 33 * an_x1_timers 1 34 * an_x4_abilities 1 35 * an_x4_status 1 36 * an_x4_sw_mgmt 1 37 * cl82 1 38 * cl82_am 1 39 * cl82_shared 1 40 * ieee0_cl22 1 41 * ilkn_x4_control0 1 42 * ilkn_x4_status0 1 43 * main0 1 44 * pmd_x1 1 45 * pmd_x4 1 46 * rx_x1_control0 1 47 * rx_x1_ecc 1 48 * rx_x1_status0 1 49 * rx_x2_control0 1 50 * rx_x4_cl91_status0 1 51 * rx_x4_cl91_status1 1 52 * rx_x4_control0 1 53 * rx_x4_ecc 1 54 * rx_x4_fec_control 1 55 * rx_x4_status0 1 56 * rx_x4_status1 1 57 * rx_x4_status2 1 58 * rx_x4_status3 1 59 * rx_x4_status4 1 60 * rx_x4_status5 1 61 * sc_x1_control 1 62 * sc_x1_speed_override01 63 * sc_x1_speed_override11 64 * sc_x1_speed_override21 65 * sc_x1_speed_override31 66 * sc_x4_control 1 67 * sc_x4_field_override_enable1 68 * sc_x4_final_config_status1 69 * test1 1 70 * testshared0 1 71 * testshared1 1 72 * tx_x1_control0 1 73 * tx_x2_control0 1 74 * tx_x2_status0 1 75 * tx_x4_control0 1 76 * tx_x4_credit_gen0 1 77 * tx_x4_status0 1 78 * 79 * RDB Files: /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/WC4_TSC_ALL.rdb 80 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/ieee0_cl22_regs.rdb 81 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/testshared0_regs.rdb 82 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/enum_inc.rdb 83 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/testshared1_regs.rdb 84 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/cl82_shared_regs.rdb 85 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/cl82_am_regs.rdb 86 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/test1_regs.rdb 87 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/main0_regs.rdb 88 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/enum_inc.rdb 89 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/rx_x1_control0_regs.rdb 90 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/rx_x1_ecc_regs.rdb 91 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/rx_x1_status0_regs.rdb 92 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/enum_inc.rdb 93 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/pmd_x1_regs.rdb 94 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/pmd_x4_regs.rdb 95 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/an_x1_control_regs.rdb 96 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/an_x4_abilities_regs.rdb 97 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/enum_inc.rdb 98 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/an_x1_timers_regs.rdb 99 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/an_x4_status_regs.rdb 100 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/an_x4_sw_mgmt_regs.rdb 101 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/an_x1_sw_mgmt_regs.rdb 102 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/cl82_user_regs.rdb 103 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/enum_inc.rdb 104 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/tx_x2_control0_regs.rdb 105 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/enum_inc.rdb 106 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/tx_x2_status0_regs.rdb 107 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/enum_inc.rdb 108 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/rx_x2_control0_regs.rdb 109 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/tx_x4_credit_gen0_regs.rdb 110 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/enum_inc.rdb 111 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/tx_x4_control0_regs.rdb 112 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/enum_inc.rdb 113 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/tx_x4_status0_regs.rdb 114 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/enum_inc.rdb 115 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/rx_x4_control0_regs.rdb 116 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/enum_inc.rdb 117 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/rx_x4_fec_control_regs.rdb 118 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/enum_inc.rdb 119 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/rx_x4_status0_regs.rdb 120 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/rx_x4_status1_regs.rdb 121 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/enum_inc.rdb 122 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/rx_x4_status2_regs.rdb 123 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/enum_inc.rdb 124 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/rx_x4_status3_regs.rdb 125 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/enum_inc.rdb 126 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/rx_x4_status4_regs.rdb 127 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/enum_inc.rdb 128 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/rx_x4_status5_regs.rdb 129 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/enum_inc.rdb 130 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/rx_x4_cl91_status0_regs.rdb 131 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/enum_inc.rdb 132 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/rx_x4_cl91_status1_regs.rdb 133 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/enum_inc.rdb 134 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/tx_x1_control0_regs.rdb 135 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/ilkn_x4_control0_regs.rdb 136 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/ilkn_x4_status0_regs.rdb 137 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/rx_x4_ecc_regs.rdb 138 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/sc_x4_control_regs.rdb 139 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/enum_inc.rdb 140 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/sc_x1_control_regs.rdb 141 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/sc_x1_speed_override0_regs.rdb 142 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/sc_x1_speed_override_common.rdb 143 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/enum_inc.rdb 144 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/sc_x1_speed_override1_regs.rdb 145 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/sc_x1_speed_override_common.rdb 146 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/enum_inc.rdb 147 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/sc_x1_speed_override2_regs.rdb 148 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/sc_x1_speed_override_common.rdb 149 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/enum_inc.rdb 150 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/sc_x1_speed_override3_regs.rdb 151 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/sc_x1_speed_override_common.rdb 152 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/enum_inc.rdb 153 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/sc_x4_final_config_status_regs.rdb 154 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/sc_x1_speed_override_common.rdb 155 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/enum_inc.rdb 156 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/sc_x4_field_override_enable_regs.rdb 157 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/WC4_ieeeBlockCL22.rdb 158 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/WC4_userBlocks1.rdb 159 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/WC4_userBlocks2.rdb 160 * /projects/TSC_ext6/alaleedh/tscf_16nm/tscf_16nm/rtl/rdb/WC4_userBlocks4.rdb 161 * 162 * Revision History: 163 * 164 * $brcm_Log: $ 165 */ 166 167 #ifndef TEF_TMP__ 168 #define TEF_TMP__ 169 170 /** 171 * m = memory, c = core, r = register, f = field, d = data. 172 */ 173 #if !defined(GET_FIELD) && !defined(SET_FIELD) 174 #define BRCM_ALIGN(c,r,f) c##_##r##_##f##_ALIGN 175 #define BRCM_BITS(c,r,f) c##_##r##_##f##_BITS 176 #define BRCM_MASK(c,r,f) c##_##r##_##f##_MASK 177 #define BRCM_SHIFT(c,r,f) c##_##r##_##f##_SHIFT 178 179 #define GET_FIELD(m,c,r,f) \ 180 ((((m) & BRCM_MASK(c,r,f)) >> BRCM_SHIFT(c,r,f)) << BRCM_ALIGN(c,r,f)) 181 182 #define SET_FIELD(m,c,r,f,d) \ 183 ((m) = (((m) & ~BRCM_MASK(c,r,f)) | ((((d) >> BRCM_ALIGN(c,r,f)) << \ 184 BRCM_SHIFT(c,r,f)) & BRCM_MASK(c,r,f))) \ 185 ) 186 187 #define SET_TYPE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##d) 188 #define SET_NAME_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##r##_##f##_##d) 189 #define SET_VALUE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,d) 190 191 #endif /* GET & SET */ 192 193 /**************************************************************************** 194 * Core Enums. 195 */ 196 /**************************************************************************** 197 * Enums: an_x4_abilities_cl36TxEEEStates_l 198 */ 199 #define an_x4_abilities_cl36TxEEEStates_l_TX_REFRESH 8 200 #define an_x4_abilities_cl36TxEEEStates_l_TX_QUIET 4 201 #define an_x4_abilities_cl36TxEEEStates_l_TX_SLEEP 2 202 #define an_x4_abilities_cl36TxEEEStates_l_TX_ACTIVE 1 203 204 /**************************************************************************** 205 * Enums: an_x4_abilities_cl36TxEEEStates_c 206 */ 207 #define an_x4_abilities_cl36TxEEEStates_c_TX_REFRESH 3 208 #define an_x4_abilities_cl36TxEEEStates_c_TX_QUIET 2 209 #define an_x4_abilities_cl36TxEEEStates_c_TX_SLEEP 1 210 #define an_x4_abilities_cl36TxEEEStates_c_TX_ACTIVE 0 211 212 /**************************************************************************** 213 * Enums: an_x4_abilities_cl49TxEEEStates_l 214 */ 215 #define an_x4_abilities_cl49TxEEEStates_l_SCR_RESET_2 64 216 #define an_x4_abilities_cl49TxEEEStates_l_SCR_RESET_1 32 217 #define an_x4_abilities_cl49TxEEEStates_l_TX_WAKE 16 218 #define an_x4_abilities_cl49TxEEEStates_l_TX_REFRESH 8 219 #define an_x4_abilities_cl49TxEEEStates_l_TX_QUIET 4 220 #define an_x4_abilities_cl49TxEEEStates_l_TX_SLEEP 2 221 #define an_x4_abilities_cl49TxEEEStates_l_TX_ACTIVE 1 222 223 /**************************************************************************** 224 * Enums: an_x4_abilities_fec_req_enum 225 */ 226 #define an_x4_abilities_fec_req_enum_FEC_not_supported 0 227 #define an_x4_abilities_fec_req_enum_FEC_supported_but_not_requested 1 228 #define an_x4_abilities_fec_req_enum_invalid_setting 2 229 #define an_x4_abilities_fec_req_enum_FEC_supported_and_requested 3 230 231 /**************************************************************************** 232 * Enums: an_x4_abilities_cl73_pause_enum 233 */ 234 #define an_x4_abilities_cl73_pause_enum_No_PAUSE_ability 0 235 #define an_x4_abilities_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 236 #define an_x4_abilities_cl73_pause_enum_Symmetric_PAUSE_ability 1 237 #define an_x4_abilities_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 238 239 /**************************************************************************** 240 * Enums: an_x4_abilities_cl49TxEEEStates_c 241 */ 242 #define an_x4_abilities_cl49TxEEEStates_c_SCR_RESET_2 6 243 #define an_x4_abilities_cl49TxEEEStates_c_SCR_RESET_1 5 244 #define an_x4_abilities_cl49TxEEEStates_c_TX_WAKE 4 245 #define an_x4_abilities_cl49TxEEEStates_c_TX_REFRESH 3 246 #define an_x4_abilities_cl49TxEEEStates_c_TX_QUIET 2 247 #define an_x4_abilities_cl49TxEEEStates_c_TX_SLEEP 1 248 #define an_x4_abilities_cl49TxEEEStates_c_TX_ACTIVE 0 249 250 /**************************************************************************** 251 * Enums: an_x4_abilities_cl36RxEEEStates_l 252 */ 253 #define an_x4_abilities_cl36RxEEEStates_l_RX_LINK_FAIL 32 254 #define an_x4_abilities_cl36RxEEEStates_l_RX_WTF 16 255 #define an_x4_abilities_cl36RxEEEStates_l_RX_WAKE 8 256 #define an_x4_abilities_cl36RxEEEStates_l_RX_QUIET 4 257 #define an_x4_abilities_cl36RxEEEStates_l_RX_SLEEP 2 258 #define an_x4_abilities_cl36RxEEEStates_l_RX_ACTIVE 1 259 260 /**************************************************************************** 261 * Enums: an_x4_abilities_cl36RxEEEStates_c 262 */ 263 #define an_x4_abilities_cl36RxEEEStates_c_RX_LINK_FAIL 5 264 #define an_x4_abilities_cl36RxEEEStates_c_RX_WTF 4 265 #define an_x4_abilities_cl36RxEEEStates_c_RX_WAKE 3 266 #define an_x4_abilities_cl36RxEEEStates_c_RX_QUIET 2 267 #define an_x4_abilities_cl36RxEEEStates_c_RX_SLEEP 1 268 #define an_x4_abilities_cl36RxEEEStates_c_RX_ACTIVE 0 269 270 /**************************************************************************** 271 * Enums: an_x4_abilities_cl49RxEEEStates_l 272 */ 273 #define an_x4_abilities_cl49RxEEEStates_l_RX_LINK_FAIL 32 274 #define an_x4_abilities_cl49RxEEEStates_l_RX_WTF 16 275 #define an_x4_abilities_cl49RxEEEStates_l_RX_WAKE 8 276 #define an_x4_abilities_cl49RxEEEStates_l_RX_QUIET 4 277 #define an_x4_abilities_cl49RxEEEStates_l_RX_SLEEP 2 278 #define an_x4_abilities_cl49RxEEEStates_l_RX_ACTIVE 1 279 280 /**************************************************************************** 281 * Enums: an_x4_abilities_cl49RxEEEStates_c 282 */ 283 #define an_x4_abilities_cl49RxEEEStates_c_RX_LINK_FAIL 5 284 #define an_x4_abilities_cl49RxEEEStates_c_RX_WTF 4 285 #define an_x4_abilities_cl49RxEEEStates_c_RX_WAKE 3 286 #define an_x4_abilities_cl49RxEEEStates_c_RX_QUIET 2 287 #define an_x4_abilities_cl49RxEEEStates_c_RX_SLEEP 1 288 #define an_x4_abilities_cl49RxEEEStates_c_RX_ACTIVE 0 289 290 /**************************************************************************** 291 * Enums: an_x4_abilities_cl48TxEEEStates_l 292 */ 293 #define an_x4_abilities_cl48TxEEEStates_l_TX_REFRESH 8 294 #define an_x4_abilities_cl48TxEEEStates_l_TX_QUIET 4 295 #define an_x4_abilities_cl48TxEEEStates_l_TX_SLEEP 2 296 #define an_x4_abilities_cl48TxEEEStates_l_TX_ACTIVE 1 297 298 /**************************************************************************** 299 * Enums: an_x4_abilities_cl48TxEEEStates_c 300 */ 301 #define an_x4_abilities_cl48TxEEEStates_c_TX_REFRESH 3 302 #define an_x4_abilities_cl48TxEEEStates_c_TX_QUIET 2 303 #define an_x4_abilities_cl48TxEEEStates_c_TX_SLEEP 1 304 #define an_x4_abilities_cl48TxEEEStates_c_TX_ACTIVE 0 305 306 /**************************************************************************** 307 * Enums: an_x4_abilities_cl48RxEEEStates_l 308 */ 309 #define an_x4_abilities_cl48RxEEEStates_l_RX_LINK_FAIL 32 310 #define an_x4_abilities_cl48RxEEEStates_l_RX_WAKE 16 311 #define an_x4_abilities_cl48RxEEEStates_l_RX_QUIET 8 312 #define an_x4_abilities_cl48RxEEEStates_l_RX_DEACT 4 313 #define an_x4_abilities_cl48RxEEEStates_l_RX_SLEEP 2 314 #define an_x4_abilities_cl48RxEEEStates_l_RX_ACTIVE 1 315 316 /**************************************************************************** 317 * Enums: an_x4_abilities_cl48RxEEEStates_c 318 */ 319 #define an_x4_abilities_cl48RxEEEStates_c_RX_LINK_FAIL 5 320 #define an_x4_abilities_cl48RxEEEStates_c_RX_WAKE 4 321 #define an_x4_abilities_cl48RxEEEStates_c_RX_QUIET 3 322 #define an_x4_abilities_cl48RxEEEStates_c_RX_DEACT 2 323 #define an_x4_abilities_cl48RxEEEStates_c_RX_SLEEP 1 324 #define an_x4_abilities_cl48RxEEEStates_c_RX_ACTIVE 0 325 326 /**************************************************************************** 327 * Enums: an_x4_abilities_IQP_Options 328 */ 329 #define an_x4_abilities_IQP_Options_i50uA 0 330 #define an_x4_abilities_IQP_Options_i100uA 1 331 #define an_x4_abilities_IQP_Options_i150uA 2 332 #define an_x4_abilities_IQP_Options_i200uA 3 333 #define an_x4_abilities_IQP_Options_i250uA 4 334 #define an_x4_abilities_IQP_Options_i300uA 5 335 #define an_x4_abilities_IQP_Options_i350uA 6 336 #define an_x4_abilities_IQP_Options_i400uA 7 337 #define an_x4_abilities_IQP_Options_i450uA 8 338 #define an_x4_abilities_IQP_Options_i500uA 9 339 #define an_x4_abilities_IQP_Options_i550uA 10 340 #define an_x4_abilities_IQP_Options_i600uA 11 341 #define an_x4_abilities_IQP_Options_i650uA 12 342 #define an_x4_abilities_IQP_Options_i700uA 13 343 #define an_x4_abilities_IQP_Options_i750uA 14 344 #define an_x4_abilities_IQP_Options_i800uA 15 345 346 /**************************************************************************** 347 * Enums: an_x4_abilities_IDriver_Options 348 */ 349 #define an_x4_abilities_IDriver_Options_v680mV 0 350 #define an_x4_abilities_IDriver_Options_v730mV 1 351 #define an_x4_abilities_IDriver_Options_v780mV 2 352 #define an_x4_abilities_IDriver_Options_v830mV 3 353 #define an_x4_abilities_IDriver_Options_v880mV 4 354 #define an_x4_abilities_IDriver_Options_v930mV 5 355 #define an_x4_abilities_IDriver_Options_v980mV 6 356 #define an_x4_abilities_IDriver_Options_v1010mV 7 357 #define an_x4_abilities_IDriver_Options_v1040mV 8 358 #define an_x4_abilities_IDriver_Options_v1060mV 9 359 #define an_x4_abilities_IDriver_Options_v1070mV 10 360 #define an_x4_abilities_IDriver_Options_v1080mV 11 361 #define an_x4_abilities_IDriver_Options_v1085mV 12 362 #define an_x4_abilities_IDriver_Options_v1090mV 13 363 #define an_x4_abilities_IDriver_Options_v1095mV 14 364 #define an_x4_abilities_IDriver_Options_v1100mV 15 365 366 /**************************************************************************** 367 * Enums: an_x4_abilities_operationModes 368 */ 369 #define an_x4_abilities_operationModes_XGXS 0 370 #define an_x4_abilities_operationModes_XGXG_nCC 1 371 #define an_x4_abilities_operationModes_Indlane_OS8 4 372 #define an_x4_abilities_operationModes_IndLane_OS5 5 373 #define an_x4_abilities_operationModes_PCI 7 374 #define an_x4_abilities_operationModes_XGXS_nLQ 8 375 #define an_x4_abilities_operationModes_XGXS_nLQnCC 9 376 #define an_x4_abilities_operationModes_PBypass 10 377 #define an_x4_abilities_operationModes_PBypass_nDSK 11 378 #define an_x4_abilities_operationModes_ComboCoreMode 12 379 #define an_x4_abilities_operationModes_Clocks_off 15 380 381 /**************************************************************************** 382 * Enums: an_x4_abilities_actualSpeeds 383 */ 384 #define an_x4_abilities_actualSpeeds_dr_10M 0 385 #define an_x4_abilities_actualSpeeds_dr_100M 1 386 #define an_x4_abilities_actualSpeeds_dr_1G 2 387 #define an_x4_abilities_actualSpeeds_dr_2p5G 3 388 #define an_x4_abilities_actualSpeeds_dr_5G_X4 4 389 #define an_x4_abilities_actualSpeeds_dr_6G_X4 5 390 #define an_x4_abilities_actualSpeeds_dr_10G_HiG 6 391 #define an_x4_abilities_actualSpeeds_dr_10G_CX4 7 392 #define an_x4_abilities_actualSpeeds_dr_12G_HiG 8 393 #define an_x4_abilities_actualSpeeds_dr_12p5G_X4 9 394 #define an_x4_abilities_actualSpeeds_dr_13G_X4 10 395 #define an_x4_abilities_actualSpeeds_dr_15G_X4 11 396 #define an_x4_abilities_actualSpeeds_dr_16G_X4 12 397 #define an_x4_abilities_actualSpeeds_dr_1G_KX 13 398 #define an_x4_abilities_actualSpeeds_dr_10G_KX4 14 399 #define an_x4_abilities_actualSpeeds_dr_10G_KR 15 400 #define an_x4_abilities_actualSpeeds_dr_5G 16 401 #define an_x4_abilities_actualSpeeds_dr_6p4G 17 402 #define an_x4_abilities_actualSpeeds_dr_20G_X4 18 403 #define an_x4_abilities_actualSpeeds_dr_21G_X4 19 404 #define an_x4_abilities_actualSpeeds_dr_25G_X4 20 405 #define an_x4_abilities_actualSpeeds_dr_10G_HiG_DXGXS 21 406 #define an_x4_abilities_actualSpeeds_dr_10G_DXGXS 22 407 #define an_x4_abilities_actualSpeeds_dr_10p5G_HiG_DXGXS 23 408 #define an_x4_abilities_actualSpeeds_dr_10p5G_DXGXS 24 409 #define an_x4_abilities_actualSpeeds_dr_12p773G_HiG_DXGXS 25 410 #define an_x4_abilities_actualSpeeds_dr_12p773G_DXGXS 26 411 #define an_x4_abilities_actualSpeeds_dr_10G_XFI 27 412 #define an_x4_abilities_actualSpeeds_dr_40G 28 413 #define an_x4_abilities_actualSpeeds_dr_20G_HiG_DXGXS 29 414 #define an_x4_abilities_actualSpeeds_dr_20G_DXGXS 30 415 #define an_x4_abilities_actualSpeeds_dr_10G_SFI 31 416 #define an_x4_abilities_actualSpeeds_dr_31p5G 32 417 #define an_x4_abilities_actualSpeeds_dr_32p7G 33 418 #define an_x4_abilities_actualSpeeds_dr_20G_SCR 34 419 #define an_x4_abilities_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 420 #define an_x4_abilities_actualSpeeds_dr_10G_DXGXS_SCR 36 421 #define an_x4_abilities_actualSpeeds_dr_12G_R2 37 422 #define an_x4_abilities_actualSpeeds_dr_10G_X2 38 423 #define an_x4_abilities_actualSpeeds_dr_40G_KR4 39 424 #define an_x4_abilities_actualSpeeds_dr_40G_CR4 40 425 #define an_x4_abilities_actualSpeeds_dr_100G_CR10 41 426 #define an_x4_abilities_actualSpeeds_dr_15p75G_DXGXS 44 427 #define an_x4_abilities_actualSpeeds_dr_20G_KR2 57 428 #define an_x4_abilities_actualSpeeds_dr_20G_CR2 58 429 430 /**************************************************************************** 431 * Enums: an_x4_abilities_actualSpeedsMisc1 432 */ 433 #define an_x4_abilities_actualSpeedsMisc1_dr_2500BRCM_X1 16 434 #define an_x4_abilities_actualSpeedsMisc1_dr_5000BRCM_X4 17 435 #define an_x4_abilities_actualSpeedsMisc1_dr_6000BRCM_X4 18 436 #define an_x4_abilities_actualSpeedsMisc1_dr_10GHiGig_X4 19 437 #define an_x4_abilities_actualSpeedsMisc1_dr_10GBASE_CX4 20 438 #define an_x4_abilities_actualSpeedsMisc1_dr_12GHiGig_X4 21 439 #define an_x4_abilities_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 440 #define an_x4_abilities_actualSpeedsMisc1_dr_13GHiGig_X4 23 441 #define an_x4_abilities_actualSpeedsMisc1_dr_15GHiGig_X4 24 442 #define an_x4_abilities_actualSpeedsMisc1_dr_16GHiGig_X4 25 443 #define an_x4_abilities_actualSpeedsMisc1_dr_5000BRCM_X1 26 444 #define an_x4_abilities_actualSpeedsMisc1_dr_6363BRCM_X1 27 445 #define an_x4_abilities_actualSpeedsMisc1_dr_20GHiGig_X4 28 446 #define an_x4_abilities_actualSpeedsMisc1_dr_21GHiGig_X4 29 447 #define an_x4_abilities_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 448 #define an_x4_abilities_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 449 450 /**************************************************************************** 451 * Enums: an_x4_abilities_IndLaneModes 452 */ 453 #define an_x4_abilities_IndLaneModes_SWSDR_div2 0 454 #define an_x4_abilities_IndLaneModes_SWSDR_div1 1 455 #define an_x4_abilities_IndLaneModes_DWSDR_div2 2 456 #define an_x4_abilities_IndLaneModes_DWSDR_div1 3 457 458 /**************************************************************************** 459 * Enums: an_x4_abilities_prbsSelect 460 */ 461 #define an_x4_abilities_prbsSelect_prbs7 0 462 #define an_x4_abilities_prbsSelect_prbs15 1 463 #define an_x4_abilities_prbsSelect_prbs23 2 464 #define an_x4_abilities_prbsSelect_prbs31 3 465 466 /**************************************************************************** 467 * Enums: an_x4_abilities_vcoDivider 468 */ 469 #define an_x4_abilities_vcoDivider_div32 0 470 #define an_x4_abilities_vcoDivider_div36 1 471 #define an_x4_abilities_vcoDivider_div40 2 472 #define an_x4_abilities_vcoDivider_div42 3 473 #define an_x4_abilities_vcoDivider_div48 4 474 #define an_x4_abilities_vcoDivider_div50 5 475 #define an_x4_abilities_vcoDivider_div52 6 476 #define an_x4_abilities_vcoDivider_div54 7 477 #define an_x4_abilities_vcoDivider_div60 8 478 #define an_x4_abilities_vcoDivider_div64 9 479 #define an_x4_abilities_vcoDivider_div66 10 480 #define an_x4_abilities_vcoDivider_div68 11 481 #define an_x4_abilities_vcoDivider_div70 12 482 #define an_x4_abilities_vcoDivider_div80 13 483 #define an_x4_abilities_vcoDivider_div92 14 484 #define an_x4_abilities_vcoDivider_div100 15 485 486 /**************************************************************************** 487 * Enums: an_x4_abilities_refClkSelect 488 */ 489 #define an_x4_abilities_refClkSelect_clk_25MHz 0 490 #define an_x4_abilities_refClkSelect_clk_100MHz 1 491 #define an_x4_abilities_refClkSelect_clk_125MHz 2 492 #define an_x4_abilities_refClkSelect_clk_156p25MHz 3 493 #define an_x4_abilities_refClkSelect_clk_187p5MHz 4 494 #define an_x4_abilities_refClkSelect_clk_161p25Mhz 5 495 #define an_x4_abilities_refClkSelect_clk_50Mhz 6 496 #define an_x4_abilities_refClkSelect_clk_106p25Mhz 7 497 498 /**************************************************************************** 499 * Enums: an_x4_abilities_aerMMDdevTypeSelect 500 */ 501 #define an_x4_abilities_aerMMDdevTypeSelect_combo_core 0 502 #define an_x4_abilities_aerMMDdevTypeSelect_PMA_PMD 1 503 #define an_x4_abilities_aerMMDdevTypeSelect_PCS 3 504 #define an_x4_abilities_aerMMDdevTypeSelect_PHY 4 505 #define an_x4_abilities_aerMMDdevTypeSelect_DTE 5 506 #define an_x4_abilities_aerMMDdevTypeSelect_CL73_AN 7 507 508 /**************************************************************************** 509 * Enums: an_x4_abilities_aerMMDportSelect 510 */ 511 #define an_x4_abilities_aerMMDportSelect_ln0 0 512 #define an_x4_abilities_aerMMDportSelect_ln1 1 513 #define an_x4_abilities_aerMMDportSelect_ln2 2 514 #define an_x4_abilities_aerMMDportSelect_ln3 3 515 #define an_x4_abilities_aerMMDportSelect_BCST_ln0_1_2_3 511 516 #define an_x4_abilities_aerMMDportSelect_BCST_ln0_1 512 517 #define an_x4_abilities_aerMMDportSelect_BCST_ln2_3 513 518 519 /**************************************************************************** 520 * Enums: an_x4_abilities_firmwareModeSelect 521 */ 522 #define an_x4_abilities_firmwareModeSelect_DEFAULT 0 523 #define an_x4_abilities_firmwareModeSelect_SFP_OPT_LR 1 524 #define an_x4_abilities_firmwareModeSelect_SFP_DAC 2 525 #define an_x4_abilities_firmwareModeSelect_XLAUI 3 526 #define an_x4_abilities_firmwareModeSelect_LONG_CH_6G 4 527 528 /**************************************************************************** 529 * Enums: an_x4_abilities_tempIdxSelect 530 */ 531 #define an_x4_abilities_tempIdxSelect_LTE__22p9C 15 532 #define an_x4_abilities_tempIdxSelect_LTE__12p6C 14 533 #define an_x4_abilities_tempIdxSelect_LTE__3p0C 13 534 #define an_x4_abilities_tempIdxSelect_LTE_6p7C 12 535 #define an_x4_abilities_tempIdxSelect_LTE_16p4C 11 536 #define an_x4_abilities_tempIdxSelect_LTE_26p6C 10 537 #define an_x4_abilities_tempIdxSelect_LTE_36p3C 9 538 #define an_x4_abilities_tempIdxSelect_LTE_46p0C 8 539 #define an_x4_abilities_tempIdxSelect_LTE_56p2C 7 540 #define an_x4_abilities_tempIdxSelect_LTE_65p9C 6 541 #define an_x4_abilities_tempIdxSelect_LTE_75p6C 5 542 #define an_x4_abilities_tempIdxSelect_LTE_85p3C 4 543 #define an_x4_abilities_tempIdxSelect_LTE_95p5C 3 544 #define an_x4_abilities_tempIdxSelect_LTE_105p2C 2 545 #define an_x4_abilities_tempIdxSelect_LTE_114p9C 1 546 #define an_x4_abilities_tempIdxSelect_LTE_125p1C 0 547 548 /**************************************************************************** 549 * Enums: an_x4_abilities_port_mode 550 */ 551 #define an_x4_abilities_port_mode_QUAD_PORT 0 552 #define an_x4_abilities_port_mode_TRI_1_PORT 1 553 #define an_x4_abilities_port_mode_TRI_2_PORT 2 554 #define an_x4_abilities_port_mode_DUAL_PORT 3 555 #define an_x4_abilities_port_mode_SINGLE_PORT 4 556 557 /**************************************************************************** 558 * Enums: an_x4_abilities_rev_letter_enum 559 */ 560 #define an_x4_abilities_rev_letter_enum_REV_A 0 561 #define an_x4_abilities_rev_letter_enum_REV_B 1 562 #define an_x4_abilities_rev_letter_enum_REV_C 2 563 #define an_x4_abilities_rev_letter_enum_REV_D 3 564 565 /**************************************************************************** 566 * Enums: an_x4_abilities_rev_number_enum 567 */ 568 #define an_x4_abilities_rev_number_enum_REV_0 0 569 #define an_x4_abilities_rev_number_enum_REV_1 1 570 #define an_x4_abilities_rev_number_enum_REV_2 2 571 #define an_x4_abilities_rev_number_enum_REV_3 3 572 #define an_x4_abilities_rev_number_enum_REV_4 4 573 #define an_x4_abilities_rev_number_enum_REV_5 5 574 #define an_x4_abilities_rev_number_enum_REV_6 6 575 #define an_x4_abilities_rev_number_enum_REV_7 7 576 577 /**************************************************************************** 578 * Enums: an_x4_abilities_bonding_enum 579 */ 580 #define an_x4_abilities_bonding_enum_WIRE_BOND 0 581 #define an_x4_abilities_bonding_enum_FLIP_CHIP 1 582 583 /**************************************************************************** 584 * Enums: an_x4_abilities_tech_process 585 */ 586 #define an_x4_abilities_tech_process_PROCESS_90NM 0 587 #define an_x4_abilities_tech_process_PROCESS_65NM 1 588 #define an_x4_abilities_tech_process_PROCESS_40NM 2 589 #define an_x4_abilities_tech_process_PROCESS_28NM 3 590 #define an_x4_abilities_tech_process_PROCESS_16NM 4 591 592 /**************************************************************************** 593 * Enums: an_x4_abilities_model_num 594 */ 595 #define an_x4_abilities_model_num_SERDES_CL73 0 596 #define an_x4_abilities_model_num_XGXS_16G 1 597 #define an_x4_abilities_model_num_HYPERCORE 2 598 #define an_x4_abilities_model_num_HYPERLITE 3 599 #define an_x4_abilities_model_num_PCIE_G2_PIPE 4 600 #define an_x4_abilities_model_num_SERDES_1p25GBd 5 601 #define an_x4_abilities_model_num_SATA2 6 602 #define an_x4_abilities_model_num_QSGMII 7 603 #define an_x4_abilities_model_num_XGXS10G 8 604 #define an_x4_abilities_model_num_WARPCORE 9 605 #define an_x4_abilities_model_num_XFICORE 10 606 #define an_x4_abilities_model_num_RXFI 11 607 #define an_x4_abilities_model_num_WARPLITE 12 608 #define an_x4_abilities_model_num_PENTACORE 13 609 #define an_x4_abilities_model_num_ESM 14 610 #define an_x4_abilities_model_num_QUAD_SGMII 15 611 #define an_x4_abilities_model_num_WARPCORE_3 16 612 #define an_x4_abilities_model_num_TSC 17 613 #define an_x4_abilities_model_num_TSC4E 18 614 #define an_x4_abilities_model_num_TSC12E 19 615 #define an_x4_abilities_model_num_TSC4F 20 616 #define an_x4_abilities_model_num_TSC4F_GEN2 21 617 #define an_x4_abilities_model_num_XGXS_CL73_90NM 29 618 #define an_x4_abilities_model_num_SERDES_CL73_90NM 30 619 #define an_x4_abilities_model_num_WARPCORE3 32 620 #define an_x4_abilities_model_num_WARPCORE4_TSC 33 621 #define an_x4_abilities_model_num_RXAUI 34 622 623 /**************************************************************************** 624 * Enums: an_x4_abilities_payload 625 */ 626 #define an_x4_abilities_payload_REPEAT_2_BYTES 0 627 #define an_x4_abilities_payload_RAMPING 1 628 #define an_x4_abilities_payload_CL48_CRPAT 2 629 #define an_x4_abilities_payload_CL48_CJPAT 3 630 #define an_x4_abilities_payload_CL36_LONG_CRPAT 4 631 #define an_x4_abilities_payload_CL36_SHORT_CRPAT 5 632 633 /**************************************************************************** 634 * Enums: an_x4_abilities_sc 635 */ 636 #define an_x4_abilities_sc_S_10G_CR1 0 637 #define an_x4_abilities_sc_S_10G_KR1 1 638 #define an_x4_abilities_sc_S_10G_X1 2 639 #define an_x4_abilities_sc_S_10G_HG2_CR1 4 640 #define an_x4_abilities_sc_S_10G_HG2_KR1 5 641 #define an_x4_abilities_sc_S_10G_HG2_X1 6 642 #define an_x4_abilities_sc_S_20G_CR1 8 643 #define an_x4_abilities_sc_S_20G_KR1 9 644 #define an_x4_abilities_sc_S_20G_X1 10 645 #define an_x4_abilities_sc_S_20G_HG2_CR1 12 646 #define an_x4_abilities_sc_S_20G_HG2_KR1 13 647 #define an_x4_abilities_sc_S_20G_HG2_X1 14 648 #define an_x4_abilities_sc_S_25G_CR1 16 649 #define an_x4_abilities_sc_S_25G_KR1 17 650 #define an_x4_abilities_sc_S_25G_X1 18 651 #define an_x4_abilities_sc_S_25G_HG2_CR1 20 652 #define an_x4_abilities_sc_S_25G_HG2_KR1 21 653 #define an_x4_abilities_sc_S_25G_HG2_X1 22 654 #define an_x4_abilities_sc_S_20G_CR2 24 655 #define an_x4_abilities_sc_S_20G_KR2 25 656 #define an_x4_abilities_sc_S_20G_X2 26 657 #define an_x4_abilities_sc_S_20G_HG2_CR2 28 658 #define an_x4_abilities_sc_S_20G_HG2_KR2 29 659 #define an_x4_abilities_sc_S_20G_HG2_X2 30 660 #define an_x4_abilities_sc_S_40G_CR2 32 661 #define an_x4_abilities_sc_S_40G_KR2 33 662 #define an_x4_abilities_sc_S_40G_X2 34 663 #define an_x4_abilities_sc_S_40G_HG2_CR2 36 664 #define an_x4_abilities_sc_S_40G_HG2_KR2 37 665 #define an_x4_abilities_sc_S_40G_HG2_X2 38 666 #define an_x4_abilities_sc_S_40G_CR4 40 667 #define an_x4_abilities_sc_S_40G_KR4 41 668 #define an_x4_abilities_sc_S_40G_X4 42 669 #define an_x4_abilities_sc_S_40G_HG2_CR4 44 670 #define an_x4_abilities_sc_S_40G_HG2_KR4 45 671 #define an_x4_abilities_sc_S_40G_HG2_X4 46 672 #define an_x4_abilities_sc_S_50G_CR2 48 673 #define an_x4_abilities_sc_S_50G_KR2 49 674 #define an_x4_abilities_sc_S_50G_X2 50 675 #define an_x4_abilities_sc_S_50G_HG2_CR2 52 676 #define an_x4_abilities_sc_S_50G_HG2_KR2 53 677 #define an_x4_abilities_sc_S_50G_HG2_X2 54 678 #define an_x4_abilities_sc_S_50G_CR4 56 679 #define an_x4_abilities_sc_S_50G_KR4 57 680 #define an_x4_abilities_sc_S_50G_X4 58 681 #define an_x4_abilities_sc_S_50G_HG2_CR4 60 682 #define an_x4_abilities_sc_S_50G_HG2_KR4 61 683 #define an_x4_abilities_sc_S_50G_HG2_X4 62 684 #define an_x4_abilities_sc_S_100G_CR4 64 685 #define an_x4_abilities_sc_S_100G_KR4 65 686 #define an_x4_abilities_sc_S_100G_X4 66 687 #define an_x4_abilities_sc_S_100G_HG2_CR4 68 688 #define an_x4_abilities_sc_S_100G_HG2_KR4 69 689 #define an_x4_abilities_sc_S_100G_HG2_X4 70 690 #define an_x4_abilities_sc_S_CL73_20GVCO 72 691 #define an_x4_abilities_sc_S_CL73_25GVCO 80 692 #define an_x4_abilities_sc_S_CL36_20GVCO 88 693 #define an_x4_abilities_sc_S_CL36_25GVCO 96 694 #define an_x4_abilities_sc_S_25G_CR_IEEE 112 695 #define an_x4_abilities_sc_S_25G_CRS_IEEE 113 696 #define an_x4_abilities_sc_S_25G_KR_IEEE 114 697 #define an_x4_abilities_sc_S_25G_KRS_IEEE 115 698 699 /**************************************************************************** 700 * Enums: an_x4_abilities_t_fifo_modes 701 */ 702 #define an_x4_abilities_t_fifo_modes_T_FIFO_INSERT_NO_AM 0 703 #define an_x4_abilities_t_fifo_modes_T_FIFO_INSERT_4_AM 1 704 #define an_x4_abilities_t_fifo_modes_T_FIFO_INSERT_20_AM 2 705 #define an_x4_abilities_t_fifo_modes_T_FIFO_INSERT_2_AM 3 706 707 /**************************************************************************** 708 * Enums: an_x4_abilities_t_enc_modes 709 */ 710 #define an_x4_abilities_t_enc_modes_T_ENC_MODE_BYPASS 0 711 #define an_x4_abilities_t_enc_modes_T_ENC_MODE_CL49 1 712 #define an_x4_abilities_t_enc_modes_T_ENC_MODE_CL82 2 713 714 /**************************************************************************** 715 * Enums: an_x4_abilities_btmx_mode 716 */ 717 #define an_x4_abilities_btmx_mode_BS_BTMX_MODE_1to1 0 718 #define an_x4_abilities_btmx_mode_BS_BTMX_MODE_2to1 1 719 #define an_x4_abilities_btmx_mode_BS_BTMX_MODE_5to1 2 720 721 /**************************************************************************** 722 * Enums: an_x4_abilities_t_type_cl82 723 */ 724 #define an_x4_abilities_t_type_cl82_T_TYPE_B1 5 725 #define an_x4_abilities_t_type_cl82_T_TYPE_C 4 726 #define an_x4_abilities_t_type_cl82_T_TYPE_S 3 727 #define an_x4_abilities_t_type_cl82_T_TYPE_T 2 728 #define an_x4_abilities_t_type_cl82_T_TYPE_D 1 729 #define an_x4_abilities_t_type_cl82_T_TYPE_E 0 730 731 /**************************************************************************** 732 * Enums: an_x4_abilities_txsm_state_cl82 733 */ 734 #define an_x4_abilities_txsm_state_cl82_TX_HIG_END 6 735 #define an_x4_abilities_txsm_state_cl82_TX_HIG_START 5 736 #define an_x4_abilities_txsm_state_cl82_TX_E 4 737 #define an_x4_abilities_txsm_state_cl82_TX_T 3 738 #define an_x4_abilities_txsm_state_cl82_TX_D 2 739 #define an_x4_abilities_txsm_state_cl82_TX_C 1 740 #define an_x4_abilities_txsm_state_cl82_TX_INIT 0 741 742 /**************************************************************************** 743 * Enums: an_x4_abilities_ltxsm_state_cl82 744 */ 745 #define an_x4_abilities_ltxsm_state_cl82_TX_HIG_END 64 746 #define an_x4_abilities_ltxsm_state_cl82_TX_HIG_START 32 747 #define an_x4_abilities_ltxsm_state_cl82_TX_E 16 748 #define an_x4_abilities_ltxsm_state_cl82_TX_T 8 749 #define an_x4_abilities_ltxsm_state_cl82_TX_D 4 750 #define an_x4_abilities_ltxsm_state_cl82_TX_C 2 751 #define an_x4_abilities_ltxsm_state_cl82_TX_INIT 1 752 753 /**************************************************************************** 754 * Enums: an_x4_abilities_r_type_coded_cl82 755 */ 756 #define an_x4_abilities_r_type_coded_cl82_R_TYPE_B1 32 757 #define an_x4_abilities_r_type_coded_cl82_R_TYPE_C 16 758 #define an_x4_abilities_r_type_coded_cl82_R_TYPE_S 8 759 #define an_x4_abilities_r_type_coded_cl82_R_TYPE_T 4 760 #define an_x4_abilities_r_type_coded_cl82_R_TYPE_D 2 761 #define an_x4_abilities_r_type_coded_cl82_R_TYPE_E 1 762 763 /**************************************************************************** 764 * Enums: an_x4_abilities_rxsm_state_cl82 765 */ 766 #define an_x4_abilities_rxsm_state_cl82_RX_HIG_END 64 767 #define an_x4_abilities_rxsm_state_cl82_RX_HIG_START 32 768 #define an_x4_abilities_rxsm_state_cl82_RX_E 16 769 #define an_x4_abilities_rxsm_state_cl82_RX_T 8 770 #define an_x4_abilities_rxsm_state_cl82_RX_D 4 771 #define an_x4_abilities_rxsm_state_cl82_RX_C 2 772 #define an_x4_abilities_rxsm_state_cl82_RX_INIT 1 773 774 /**************************************************************************** 775 * Enums: an_x4_abilities_deskew_state 776 */ 777 #define an_x4_abilities_deskew_state_ALIGN_ACQUIRED 2 778 #define an_x4_abilities_deskew_state_LOSS_OF_ALIGNMENT 1 779 780 /**************************************************************************** 781 * Enums: an_x4_abilities_os_mode_enum 782 */ 783 #define an_x4_abilities_os_mode_enum_OS_MODE_1 0 784 #define an_x4_abilities_os_mode_enum_OS_MODE_2 1 785 #define an_x4_abilities_os_mode_enum_OS_MODE_4 2 786 #define an_x4_abilities_os_mode_enum_OS_MODE_16p5 8 787 #define an_x4_abilities_os_mode_enum_OS_MODE_20p625 12 788 789 /**************************************************************************** 790 * Enums: an_x4_abilities_scr_modes 791 */ 792 #define an_x4_abilities_scr_modes_T_SCR_MODE_BYPASS 0 793 #define an_x4_abilities_scr_modes_T_SCR_MODE_CL49 1 794 #define an_x4_abilities_scr_modes_T_SCR_MODE_40G_2_LANE 2 795 #define an_x4_abilities_scr_modes_T_SCR_MODE_100G 3 796 #define an_x4_abilities_scr_modes_T_SCR_MODE_20G 4 797 #define an_x4_abilities_scr_modes_T_SCR_MODE_40G_4_LANE 5 798 799 /**************************************************************************** 800 * Enums: an_x4_abilities_descr_modes 801 */ 802 #define an_x4_abilities_descr_modes_R_DESCR_MODE_BYPASS 0 803 #define an_x4_abilities_descr_modes_R_DESCR_MODE_CL49 1 804 #define an_x4_abilities_descr_modes_R_DESCR_MODE_CL82 2 805 806 /**************************************************************************** 807 * Enums: an_x4_abilities_r_dec_tl_mode 808 */ 809 #define an_x4_abilities_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 810 #define an_x4_abilities_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 811 #define an_x4_abilities_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 812 813 /**************************************************************************** 814 * Enums: an_x4_abilities_r_dec_fsm_mode 815 */ 816 #define an_x4_abilities_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 817 #define an_x4_abilities_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 818 #define an_x4_abilities_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 819 820 /**************************************************************************** 821 * Enums: an_x4_abilities_r_deskew_mode 822 */ 823 #define an_x4_abilities_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 824 #define an_x4_abilities_r_deskew_mode_R_DESKEW_MODE_20G 1 825 #define an_x4_abilities_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 826 #define an_x4_abilities_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 827 #define an_x4_abilities_r_deskew_mode_R_DESKEW_MODE_100G 4 828 #define an_x4_abilities_r_deskew_mode_R_DESKEW_MODE_CL49 5 829 #define an_x4_abilities_r_deskew_mode_R_DESKEW_MODE_CL91_QUAD 6 830 #define an_x4_abilities_r_deskew_mode_R_DESKEW_MODE_CL91_SINGLE_BRCM 7 831 #define an_x4_abilities_r_deskew_mode_R_DESKEW_MODE_CL91_DUAL_BRCM 8 832 #define an_x4_abilities_r_deskew_mode_R_DESKEW_MODE_CL91_FC 9 833 834 /**************************************************************************** 835 * Enums: an_x4_abilities_bs_dist_modes 836 */ 837 #define an_x4_abilities_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 838 #define an_x4_abilities_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 839 #define an_x4_abilities_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 840 #define an_x4_abilities_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 841 842 /**************************************************************************** 843 * Enums: an_x4_abilities_cl49_t_type 844 */ 845 #define an_x4_abilities_cl49_t_type_BAD_T_TYPE 15 846 #define an_x4_abilities_cl49_t_type_T_TYPE_B0 11 847 #define an_x4_abilities_cl49_t_type_T_TYPE_OB 10 848 #define an_x4_abilities_cl49_t_type_T_TYPE_B1 9 849 #define an_x4_abilities_cl49_t_type_T_TYPE_DB 8 850 #define an_x4_abilities_cl49_t_type_T_TYPE_FC 7 851 #define an_x4_abilities_cl49_t_type_T_TYPE_TB 6 852 #define an_x4_abilities_cl49_t_type_T_TYPE_LI 5 853 #define an_x4_abilities_cl49_t_type_T_TYPE_C 4 854 #define an_x4_abilities_cl49_t_type_T_TYPE_S 3 855 #define an_x4_abilities_cl49_t_type_T_TYPE_T 2 856 #define an_x4_abilities_cl49_t_type_T_TYPE_D 1 857 #define an_x4_abilities_cl49_t_type_T_TYPE_E 0 858 859 /**************************************************************************** 860 * Enums: an_x4_abilities_cl49_txsm_states 861 */ 862 #define an_x4_abilities_cl49_txsm_states_TX_HIG_END 7 863 #define an_x4_abilities_cl49_txsm_states_TX_HIG_START 6 864 #define an_x4_abilities_cl49_txsm_states_TX_LI 5 865 #define an_x4_abilities_cl49_txsm_states_TX_E 4 866 #define an_x4_abilities_cl49_txsm_states_TX_T 3 867 #define an_x4_abilities_cl49_txsm_states_TX_D 2 868 #define an_x4_abilities_cl49_txsm_states_TX_C 1 869 #define an_x4_abilities_cl49_txsm_states_TX_INIT 0 870 871 /**************************************************************************** 872 * Enums: an_x4_abilities_cl49_ltxsm_states 873 */ 874 #define an_x4_abilities_cl49_ltxsm_states_TX_HIG_END 128 875 #define an_x4_abilities_cl49_ltxsm_states_TX_HIG_START 64 876 #define an_x4_abilities_cl49_ltxsm_states_TX_LI 32 877 #define an_x4_abilities_cl49_ltxsm_states_TX_E 16 878 #define an_x4_abilities_cl49_ltxsm_states_TX_T 8 879 #define an_x4_abilities_cl49_ltxsm_states_TX_D 4 880 #define an_x4_abilities_cl49_ltxsm_states_TX_C 2 881 #define an_x4_abilities_cl49_ltxsm_states_TX_INIT 1 882 883 /**************************************************************************** 884 * Enums: an_x4_abilities_burst_error_mode 885 */ 886 #define an_x4_abilities_burst_error_mode_BURST_ERROR_11_BITS 0 887 #define an_x4_abilities_burst_error_mode_BURST_ERROR_16_BITS 1 888 #define an_x4_abilities_burst_error_mode_BURST_ERROR_17_BITS 2 889 #define an_x4_abilities_burst_error_mode_BURST_ERROR_18_BITS 3 890 #define an_x4_abilities_burst_error_mode_BURST_ERROR_19_BITS 4 891 #define an_x4_abilities_burst_error_mode_BURST_ERROR_20_BITS 5 892 #define an_x4_abilities_burst_error_mode_BURST_ERROR_21_BITS 6 893 #define an_x4_abilities_burst_error_mode_BURST_ERROR_22_BITS 7 894 #define an_x4_abilities_burst_error_mode_BURST_ERROR_23_BITS 8 895 #define an_x4_abilities_burst_error_mode_BURST_ERROR_24_BITS 9 896 #define an_x4_abilities_burst_error_mode_BURST_ERROR_25_BITS 10 897 #define an_x4_abilities_burst_error_mode_BURST_ERROR_26_BITS 11 898 #define an_x4_abilities_burst_error_mode_BURST_ERROR_27_BITS 12 899 #define an_x4_abilities_burst_error_mode_BURST_ERROR_28_BITS 13 900 #define an_x4_abilities_burst_error_mode_BURST_ERROR_29_BITS 14 901 #define an_x4_abilities_burst_error_mode_BURST_ERROR_30_BITS 15 902 #define an_x4_abilities_burst_error_mode_BURST_ERROR_31_BITS 16 903 #define an_x4_abilities_burst_error_mode_BURST_ERROR_32_BITS 17 904 #define an_x4_abilities_burst_error_mode_BURST_ERROR_33_BITS 18 905 #define an_x4_abilities_burst_error_mode_BURST_ERROR_34_BITS 19 906 #define an_x4_abilities_burst_error_mode_BURST_ERROR_35_BITS 20 907 #define an_x4_abilities_burst_error_mode_BURST_ERROR_36_BITS 21 908 #define an_x4_abilities_burst_error_mode_BURST_ERROR_37_BITS 22 909 #define an_x4_abilities_burst_error_mode_BURST_ERROR_38_BITS 23 910 #define an_x4_abilities_burst_error_mode_BURST_ERROR_39_BITS 24 911 #define an_x4_abilities_burst_error_mode_BURST_ERROR_40_BITS 25 912 #define an_x4_abilities_burst_error_mode_BURST_ERROR_41_BITS 26 913 914 /**************************************************************************** 915 * Enums: an_x4_abilities_bermon_state 916 */ 917 #define an_x4_abilities_bermon_state_HI_BER 4 918 #define an_x4_abilities_bermon_state_GOOD_BER 3 919 #define an_x4_abilities_bermon_state_BER_TEST_SH 2 920 #define an_x4_abilities_bermon_state_START_TIMER 1 921 #define an_x4_abilities_bermon_state_BER_MT_INIT 0 922 923 /**************************************************************************** 924 * Enums: an_x4_abilities_rxsm_state_cl49 925 */ 926 #define an_x4_abilities_rxsm_state_cl49_RX_HIG_END 128 927 #define an_x4_abilities_rxsm_state_cl49_RX_HIG_START 64 928 #define an_x4_abilities_rxsm_state_cl49_RX_LI 32 929 #define an_x4_abilities_rxsm_state_cl49_RX_E 16 930 #define an_x4_abilities_rxsm_state_cl49_RX_T 8 931 #define an_x4_abilities_rxsm_state_cl49_RX_D 4 932 #define an_x4_abilities_rxsm_state_cl49_RX_C 2 933 #define an_x4_abilities_rxsm_state_cl49_RX_INIT 1 934 935 /**************************************************************************** 936 * Enums: an_x4_abilities_r_type 937 */ 938 #define an_x4_abilities_r_type_BAD_R_TYPE 15 939 #define an_x4_abilities_r_type_R_TYPE_B0 11 940 #define an_x4_abilities_r_type_R_TYPE_OB 10 941 #define an_x4_abilities_r_type_R_TYPE_B1 9 942 #define an_x4_abilities_r_type_R_TYPE_DB 8 943 #define an_x4_abilities_r_type_R_TYPE_FC 7 944 #define an_x4_abilities_r_type_R_TYPE_TB 6 945 #define an_x4_abilities_r_type_R_TYPE_LI 5 946 #define an_x4_abilities_r_type_R_TYPE_C 4 947 #define an_x4_abilities_r_type_R_TYPE_S 3 948 #define an_x4_abilities_r_type_R_TYPE_T 2 949 #define an_x4_abilities_r_type_R_TYPE_D 1 950 #define an_x4_abilities_r_type_R_TYPE_E 0 951 952 /**************************************************************************** 953 * Enums: an_x4_abilities_am_lock_state 954 */ 955 #define an_x4_abilities_am_lock_state_INVALID_AM 512 956 #define an_x4_abilities_am_lock_state_GOOD_AM 256 957 #define an_x4_abilities_am_lock_state_COMP_AM 128 958 #define an_x4_abilities_am_lock_state_TIMER_2 64 959 #define an_x4_abilities_am_lock_state_AM_2_GOOD 32 960 #define an_x4_abilities_am_lock_state_COMP_2ND 16 961 #define an_x4_abilities_am_lock_state_TIMER_1 8 962 #define an_x4_abilities_am_lock_state_FIND_1ST 4 963 #define an_x4_abilities_am_lock_state_AM_RESET_CNT 2 964 #define an_x4_abilities_am_lock_state_AM_LOCK_INIT 1 965 966 /**************************************************************************** 967 * Enums: an_x4_abilities_msg_selector 968 */ 969 #define an_x4_abilities_msg_selector_RESERVED 0 970 #define an_x4_abilities_msg_selector_VALUE_802p3 1 971 #define an_x4_abilities_msg_selector_VALUE_802p9 2 972 #define an_x4_abilities_msg_selector_VALUE_802p5 3 973 #define an_x4_abilities_msg_selector_VALUE_1394 4 974 975 /**************************************************************************** 976 * Enums: an_x4_abilities_synce_enum 977 */ 978 #define an_x4_abilities_synce_enum_SYNCE_NO_DIV 0 979 #define an_x4_abilities_synce_enum_SYNCE_DIV_7 1 980 #define an_x4_abilities_synce_enum_SYNCE_DIV_11 2 981 982 /**************************************************************************** 983 * Enums: an_x4_abilities_synce_enum_stage0 984 */ 985 #define an_x4_abilities_synce_enum_stage0_SYNCE_NO_DIV 0 986 #define an_x4_abilities_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 987 #define an_x4_abilities_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 988 989 /**************************************************************************** 990 * Enums: an_x4_abilities_cl91_sync_state 991 */ 992 #define an_x4_abilities_cl91_sync_state_FIND_1ST 0 993 #define an_x4_abilities_cl91_sync_state_COUNT_NEXT 1 994 #define an_x4_abilities_cl91_sync_state_COMP_2ND 2 995 #define an_x4_abilities_cl91_sync_state_TWO_GOOD 3 996 997 /**************************************************************************** 998 * Enums: an_x4_abilities_cl91_algn_state 999 */ 1000 #define an_x4_abilities_cl91_algn_state_LOSS_OF_ALIGNMENT 0 1001 #define an_x4_abilities_cl91_algn_state_DESKEW 1 1002 #define an_x4_abilities_cl91_algn_state_DESKEW_FAIL 2 1003 #define an_x4_abilities_cl91_algn_state_ALIGN_ACQUIRED 3 1004 #define an_x4_abilities_cl91_algn_state_CW_GOOD 4 1005 #define an_x4_abilities_cl91_algn_state_CW_BAD 5 1006 #define an_x4_abilities_cl91_algn_state_THREE_BAD 6 1007 1008 /**************************************************************************** 1009 * Enums: an_x4_abilities_fec_sel_override 1010 */ 1011 #define an_x4_abilities_fec_sel_override_NO_OVERRIDE 0 1012 #define an_x4_abilities_fec_sel_override_NO_FEC 1 1013 #define an_x4_abilities_fec_sel_override_FEC_CL74 2 1014 #define an_x4_abilities_fec_sel_override_FEC_CL91 3 1015 1016 /**************************************************************************** 1017 * Enums: an_x4_abilities_cl91_blksync_mode 1018 */ 1019 #define an_x4_abilities_cl91_blksync_mode_R_BLKSYNC_NO_CL91_FEC 0 1020 #define an_x4_abilities_cl91_blksync_mode_R_BLKSYNC_CL91_QUAD_LANE_FEC 1 1021 #define an_x4_abilities_cl91_blksync_mode_R_BLKSYNC_CL91_DUAL_LANE_FEC 2 1022 #define an_x4_abilities_cl91_blksync_mode_R_BLKSYNC_CL91_SINGLE_LANE_FEC 3 1023 #define an_x4_abilities_cl91_blksync_mode_R_BLKSYNC_CL91_FC_FEC 4 1024 1025 /**************************************************************************** 1026 * Enums: an_x4_abilities_r_merge_mode 1027 */ 1028 #define an_x4_abilities_r_merge_mode_R_MERGE_MODE_BYPASS 0 1029 #define an_x4_abilities_r_merge_mode_R_MERGE_MODE_CL91_FC 1 1030 #define an_x4_abilities_r_merge_mode_R_MERGE_MODE_CL91_SINGLE_LANE 2 1031 #define an_x4_abilities_r_merge_mode_R_MERGE_MODE_CL91_DUAL_LANE 3 1032 #define an_x4_abilities_r_merge_mode_R_MERGE_MODE_CL91_QUAD_LANE 4 1033 1034 /**************************************************************************** 1035 * Enums: an_x4_abilities_r_tc_mode 1036 */ 1037 #define an_x4_abilities_r_tc_mode_R_TC_MODE_SINGLE 0 1038 #define an_x4_abilities_r_tc_mode_R_TC_MODE_DUAL 1 1039 #define an_x4_abilities_r_tc_mode_R_TC_MODE_QUAD 2 1040 1041 /**************************************************************************** 1042 * Enums: an_x4_abilities_r_tc_out_mode 1043 */ 1044 #define an_x4_abilities_r_tc_out_mode_R_TC_OUT_MODE_SINGLE 0 1045 #define an_x4_abilities_r_tc_out_mode_R_TC_OUT_MODE_DUAL 1 1046 #define an_x4_abilities_r_tc_out_mode_R_TC_OUT_MODE_QUAD 2 1047 1048 /**************************************************************************** 1049 * Enums: an_x4_abilities_cl91_fec_mode 1050 */ 1051 #define an_x4_abilities_cl91_fec_mode_NO_CL91_FEC 0 1052 #define an_x4_abilities_cl91_fec_mode_CL91_SINGLE_LANE_FC 1 1053 #define an_x4_abilities_cl91_fec_mode_CL91_SINGLE_LANE_BRCM_PROP 2 1054 #define an_x4_abilities_cl91_fec_mode_CL91_DUAL_LANE_BRCM_PROP 3 1055 #define an_x4_abilities_cl91_fec_mode_CL91_QUAD_LANE 4 1056 #define an_x4_abilities_cl91_fec_mode_IEEE_25G_CL91_SINGLE_LANE 5 1057 1058 /**************************************************************************** 1059 * Enums: an_x4_abilities_am_spacing_mul 1060 */ 1061 #define an_x4_abilities_am_spacing_mul_AM_SPACING_MUL_2 0 1062 #define an_x4_abilities_am_spacing_mul_AM_SPACING_MUL_4 1 1063 #define an_x4_abilities_am_spacing_mul_AM_SPACING_MUL_5 2 1064 #define an_x4_abilities_am_spacing_mul_AM_SPACING_MUL_20 3 1065 1066 /**************************************************************************** 1067 * Enums: an_x4_sw_mgmt_tla_ln_seq_status 1068 */ 1069 #define an_x4_sw_mgmt_tla_ln_seq_status_INIT 1 1070 #define an_x4_sw_mgmt_tla_ln_seq_status_SET_AN_SPEED 2 1071 #define an_x4_sw_mgmt_tla_ln_seq_status_WAIT_AN_SPEED 4 1072 #define an_x4_sw_mgmt_tla_ln_seq_status_WAIT_AN_DONE 8 1073 #define an_x4_sw_mgmt_tla_ln_seq_status_SET_RS_SPEED 16 1074 #define an_x4_sw_mgmt_tla_ln_seq_status_WAIT_RS_CL72EN 32 1075 #define an_x4_sw_mgmt_tla_ln_seq_status_WAIT_RS_SPEED 64 1076 #define an_x4_sw_mgmt_tla_ln_seq_status_AN_IGNORE_LINK 128 1077 #define an_x4_sw_mgmt_tla_ln_seq_status_AN_GOOD_CHECK 256 1078 #define an_x4_sw_mgmt_tla_ln_seq_status_AN_GOOD 512 1079 #define an_x4_sw_mgmt_tla_ln_seq_status_AN_FAIL 1024 1080 #define an_x4_sw_mgmt_tla_ln_seq_status_AN_DEAD 2048 1081 #define an_x4_sw_mgmt_tla_ln_seq_status_WAIT_PD_SPEED 4096 1082 #define an_x4_sw_mgmt_tla_ln_seq_status_PD_IGNORE_LINK 8192 1083 #define an_x4_sw_mgmt_tla_ln_seq_status_PD_GOOD_CHECK 16384 1084 #define an_x4_sw_mgmt_tla_ln_seq_status_SW_SPEED_CHANGE 32768 1085 1086 /**************************************************************************** 1087 * Enums: cl82_cl36TxEEEStates_l 1088 */ 1089 #define cl82_cl36TxEEEStates_l_TX_REFRESH 8 1090 #define cl82_cl36TxEEEStates_l_TX_QUIET 4 1091 #define cl82_cl36TxEEEStates_l_TX_SLEEP 2 1092 #define cl82_cl36TxEEEStates_l_TX_ACTIVE 1 1093 1094 /**************************************************************************** 1095 * Enums: cl82_cl36TxEEEStates_c 1096 */ 1097 #define cl82_cl36TxEEEStates_c_TX_REFRESH 3 1098 #define cl82_cl36TxEEEStates_c_TX_QUIET 2 1099 #define cl82_cl36TxEEEStates_c_TX_SLEEP 1 1100 #define cl82_cl36TxEEEStates_c_TX_ACTIVE 0 1101 1102 /**************************************************************************** 1103 * Enums: cl82_cl49TxEEEStates_l 1104 */ 1105 #define cl82_cl49TxEEEStates_l_SCR_RESET_2 64 1106 #define cl82_cl49TxEEEStates_l_SCR_RESET_1 32 1107 #define cl82_cl49TxEEEStates_l_TX_WAKE 16 1108 #define cl82_cl49TxEEEStates_l_TX_REFRESH 8 1109 #define cl82_cl49TxEEEStates_l_TX_QUIET 4 1110 #define cl82_cl49TxEEEStates_l_TX_SLEEP 2 1111 #define cl82_cl49TxEEEStates_l_TX_ACTIVE 1 1112 1113 /**************************************************************************** 1114 * Enums: cl82_fec_req_enum 1115 */ 1116 #define cl82_fec_req_enum_FEC_not_supported 0 1117 #define cl82_fec_req_enum_FEC_supported_but_not_requested 1 1118 #define cl82_fec_req_enum_invalid_setting 2 1119 #define cl82_fec_req_enum_FEC_supported_and_requested 3 1120 1121 /**************************************************************************** 1122 * Enums: cl82_cl73_pause_enum 1123 */ 1124 #define cl82_cl73_pause_enum_No_PAUSE_ability 0 1125 #define cl82_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 1126 #define cl82_cl73_pause_enum_Symmetric_PAUSE_ability 1 1127 #define cl82_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 1128 1129 /**************************************************************************** 1130 * Enums: cl82_cl49TxEEEStates_c 1131 */ 1132 #define cl82_cl49TxEEEStates_c_SCR_RESET_2 6 1133 #define cl82_cl49TxEEEStates_c_SCR_RESET_1 5 1134 #define cl82_cl49TxEEEStates_c_TX_WAKE 4 1135 #define cl82_cl49TxEEEStates_c_TX_REFRESH 3 1136 #define cl82_cl49TxEEEStates_c_TX_QUIET 2 1137 #define cl82_cl49TxEEEStates_c_TX_SLEEP 1 1138 #define cl82_cl49TxEEEStates_c_TX_ACTIVE 0 1139 1140 /**************************************************************************** 1141 * Enums: cl82_cl36RxEEEStates_l 1142 */ 1143 #define cl82_cl36RxEEEStates_l_RX_LINK_FAIL 32 1144 #define cl82_cl36RxEEEStates_l_RX_WTF 16 1145 #define cl82_cl36RxEEEStates_l_RX_WAKE 8 1146 #define cl82_cl36RxEEEStates_l_RX_QUIET 4 1147 #define cl82_cl36RxEEEStates_l_RX_SLEEP 2 1148 #define cl82_cl36RxEEEStates_l_RX_ACTIVE 1 1149 1150 /**************************************************************************** 1151 * Enums: cl82_cl36RxEEEStates_c 1152 */ 1153 #define cl82_cl36RxEEEStates_c_RX_LINK_FAIL 5 1154 #define cl82_cl36RxEEEStates_c_RX_WTF 4 1155 #define cl82_cl36RxEEEStates_c_RX_WAKE 3 1156 #define cl82_cl36RxEEEStates_c_RX_QUIET 2 1157 #define cl82_cl36RxEEEStates_c_RX_SLEEP 1 1158 #define cl82_cl36RxEEEStates_c_RX_ACTIVE 0 1159 1160 /**************************************************************************** 1161 * Enums: cl82_cl49RxEEEStates_l 1162 */ 1163 #define cl82_cl49RxEEEStates_l_RX_LINK_FAIL 32 1164 #define cl82_cl49RxEEEStates_l_RX_WTF 16 1165 #define cl82_cl49RxEEEStates_l_RX_WAKE 8 1166 #define cl82_cl49RxEEEStates_l_RX_QUIET 4 1167 #define cl82_cl49RxEEEStates_l_RX_SLEEP 2 1168 #define cl82_cl49RxEEEStates_l_RX_ACTIVE 1 1169 1170 /**************************************************************************** 1171 * Enums: cl82_cl49RxEEEStates_c 1172 */ 1173 #define cl82_cl49RxEEEStates_c_RX_LINK_FAIL 5 1174 #define cl82_cl49RxEEEStates_c_RX_WTF 4 1175 #define cl82_cl49RxEEEStates_c_RX_WAKE 3 1176 #define cl82_cl49RxEEEStates_c_RX_QUIET 2 1177 #define cl82_cl49RxEEEStates_c_RX_SLEEP 1 1178 #define cl82_cl49RxEEEStates_c_RX_ACTIVE 0 1179 1180 /**************************************************************************** 1181 * Enums: cl82_cl48TxEEEStates_l 1182 */ 1183 #define cl82_cl48TxEEEStates_l_TX_REFRESH 8 1184 #define cl82_cl48TxEEEStates_l_TX_QUIET 4 1185 #define cl82_cl48TxEEEStates_l_TX_SLEEP 2 1186 #define cl82_cl48TxEEEStates_l_TX_ACTIVE 1 1187 1188 /**************************************************************************** 1189 * Enums: cl82_cl48TxEEEStates_c 1190 */ 1191 #define cl82_cl48TxEEEStates_c_TX_REFRESH 3 1192 #define cl82_cl48TxEEEStates_c_TX_QUIET 2 1193 #define cl82_cl48TxEEEStates_c_TX_SLEEP 1 1194 #define cl82_cl48TxEEEStates_c_TX_ACTIVE 0 1195 1196 /**************************************************************************** 1197 * Enums: cl82_cl48RxEEEStates_l 1198 */ 1199 #define cl82_cl48RxEEEStates_l_RX_LINK_FAIL 32 1200 #define cl82_cl48RxEEEStates_l_RX_WAKE 16 1201 #define cl82_cl48RxEEEStates_l_RX_QUIET 8 1202 #define cl82_cl48RxEEEStates_l_RX_DEACT 4 1203 #define cl82_cl48RxEEEStates_l_RX_SLEEP 2 1204 #define cl82_cl48RxEEEStates_l_RX_ACTIVE 1 1205 1206 /**************************************************************************** 1207 * Enums: cl82_cl48RxEEEStates_c 1208 */ 1209 #define cl82_cl48RxEEEStates_c_RX_LINK_FAIL 5 1210 #define cl82_cl48RxEEEStates_c_RX_WAKE 4 1211 #define cl82_cl48RxEEEStates_c_RX_QUIET 3 1212 #define cl82_cl48RxEEEStates_c_RX_DEACT 2 1213 #define cl82_cl48RxEEEStates_c_RX_SLEEP 1 1214 #define cl82_cl48RxEEEStates_c_RX_ACTIVE 0 1215 1216 /**************************************************************************** 1217 * Enums: cl82_IQP_Options 1218 */ 1219 #define cl82_IQP_Options_i50uA 0 1220 #define cl82_IQP_Options_i100uA 1 1221 #define cl82_IQP_Options_i150uA 2 1222 #define cl82_IQP_Options_i200uA 3 1223 #define cl82_IQP_Options_i250uA 4 1224 #define cl82_IQP_Options_i300uA 5 1225 #define cl82_IQP_Options_i350uA 6 1226 #define cl82_IQP_Options_i400uA 7 1227 #define cl82_IQP_Options_i450uA 8 1228 #define cl82_IQP_Options_i500uA 9 1229 #define cl82_IQP_Options_i550uA 10 1230 #define cl82_IQP_Options_i600uA 11 1231 #define cl82_IQP_Options_i650uA 12 1232 #define cl82_IQP_Options_i700uA 13 1233 #define cl82_IQP_Options_i750uA 14 1234 #define cl82_IQP_Options_i800uA 15 1235 1236 /**************************************************************************** 1237 * Enums: cl82_IDriver_Options 1238 */ 1239 #define cl82_IDriver_Options_v680mV 0 1240 #define cl82_IDriver_Options_v730mV 1 1241 #define cl82_IDriver_Options_v780mV 2 1242 #define cl82_IDriver_Options_v830mV 3 1243 #define cl82_IDriver_Options_v880mV 4 1244 #define cl82_IDriver_Options_v930mV 5 1245 #define cl82_IDriver_Options_v980mV 6 1246 #define cl82_IDriver_Options_v1010mV 7 1247 #define cl82_IDriver_Options_v1040mV 8 1248 #define cl82_IDriver_Options_v1060mV 9 1249 #define cl82_IDriver_Options_v1070mV 10 1250 #define cl82_IDriver_Options_v1080mV 11 1251 #define cl82_IDriver_Options_v1085mV 12 1252 #define cl82_IDriver_Options_v1090mV 13 1253 #define cl82_IDriver_Options_v1095mV 14 1254 #define cl82_IDriver_Options_v1100mV 15 1255 1256 /**************************************************************************** 1257 * Enums: cl82_operationModes 1258 */ 1259 #define cl82_operationModes_XGXS 0 1260 #define cl82_operationModes_XGXG_nCC 1 1261 #define cl82_operationModes_Indlane_OS8 4 1262 #define cl82_operationModes_IndLane_OS5 5 1263 #define cl82_operationModes_PCI 7 1264 #define cl82_operationModes_XGXS_nLQ 8 1265 #define cl82_operationModes_XGXS_nLQnCC 9 1266 #define cl82_operationModes_PBypass 10 1267 #define cl82_operationModes_PBypass_nDSK 11 1268 #define cl82_operationModes_ComboCoreMode 12 1269 #define cl82_operationModes_Clocks_off 15 1270 1271 /**************************************************************************** 1272 * Enums: cl82_actualSpeeds 1273 */ 1274 #define cl82_actualSpeeds_dr_10M 0 1275 #define cl82_actualSpeeds_dr_100M 1 1276 #define cl82_actualSpeeds_dr_1G 2 1277 #define cl82_actualSpeeds_dr_2p5G 3 1278 #define cl82_actualSpeeds_dr_5G_X4 4 1279 #define cl82_actualSpeeds_dr_6G_X4 5 1280 #define cl82_actualSpeeds_dr_10G_HiG 6 1281 #define cl82_actualSpeeds_dr_10G_CX4 7 1282 #define cl82_actualSpeeds_dr_12G_HiG 8 1283 #define cl82_actualSpeeds_dr_12p5G_X4 9 1284 #define cl82_actualSpeeds_dr_13G_X4 10 1285 #define cl82_actualSpeeds_dr_15G_X4 11 1286 #define cl82_actualSpeeds_dr_16G_X4 12 1287 #define cl82_actualSpeeds_dr_1G_KX 13 1288 #define cl82_actualSpeeds_dr_10G_KX4 14 1289 #define cl82_actualSpeeds_dr_10G_KR 15 1290 #define cl82_actualSpeeds_dr_5G 16 1291 #define cl82_actualSpeeds_dr_6p4G 17 1292 #define cl82_actualSpeeds_dr_20G_X4 18 1293 #define cl82_actualSpeeds_dr_21G_X4 19 1294 #define cl82_actualSpeeds_dr_25G_X4 20 1295 #define cl82_actualSpeeds_dr_10G_HiG_DXGXS 21 1296 #define cl82_actualSpeeds_dr_10G_DXGXS 22 1297 #define cl82_actualSpeeds_dr_10p5G_HiG_DXGXS 23 1298 #define cl82_actualSpeeds_dr_10p5G_DXGXS 24 1299 #define cl82_actualSpeeds_dr_12p773G_HiG_DXGXS 25 1300 #define cl82_actualSpeeds_dr_12p773G_DXGXS 26 1301 #define cl82_actualSpeeds_dr_10G_XFI 27 1302 #define cl82_actualSpeeds_dr_40G 28 1303 #define cl82_actualSpeeds_dr_20G_HiG_DXGXS 29 1304 #define cl82_actualSpeeds_dr_20G_DXGXS 30 1305 #define cl82_actualSpeeds_dr_10G_SFI 31 1306 #define cl82_actualSpeeds_dr_31p5G 32 1307 #define cl82_actualSpeeds_dr_32p7G 33 1308 #define cl82_actualSpeeds_dr_20G_SCR 34 1309 #define cl82_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 1310 #define cl82_actualSpeeds_dr_10G_DXGXS_SCR 36 1311 #define cl82_actualSpeeds_dr_12G_R2 37 1312 #define cl82_actualSpeeds_dr_10G_X2 38 1313 #define cl82_actualSpeeds_dr_40G_KR4 39 1314 #define cl82_actualSpeeds_dr_40G_CR4 40 1315 #define cl82_actualSpeeds_dr_100G_CR10 41 1316 #define cl82_actualSpeeds_dr_15p75G_DXGXS 44 1317 #define cl82_actualSpeeds_dr_20G_KR2 57 1318 #define cl82_actualSpeeds_dr_20G_CR2 58 1319 1320 /**************************************************************************** 1321 * Enums: cl82_actualSpeedsMisc1 1322 */ 1323 #define cl82_actualSpeedsMisc1_dr_2500BRCM_X1 16 1324 #define cl82_actualSpeedsMisc1_dr_5000BRCM_X4 17 1325 #define cl82_actualSpeedsMisc1_dr_6000BRCM_X4 18 1326 #define cl82_actualSpeedsMisc1_dr_10GHiGig_X4 19 1327 #define cl82_actualSpeedsMisc1_dr_10GBASE_CX4 20 1328 #define cl82_actualSpeedsMisc1_dr_12GHiGig_X4 21 1329 #define cl82_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 1330 #define cl82_actualSpeedsMisc1_dr_13GHiGig_X4 23 1331 #define cl82_actualSpeedsMisc1_dr_15GHiGig_X4 24 1332 #define cl82_actualSpeedsMisc1_dr_16GHiGig_X4 25 1333 #define cl82_actualSpeedsMisc1_dr_5000BRCM_X1 26 1334 #define cl82_actualSpeedsMisc1_dr_6363BRCM_X1 27 1335 #define cl82_actualSpeedsMisc1_dr_20GHiGig_X4 28 1336 #define cl82_actualSpeedsMisc1_dr_21GHiGig_X4 29 1337 #define cl82_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 1338 #define cl82_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 1339 1340 /**************************************************************************** 1341 * Enums: cl82_IndLaneModes 1342 */ 1343 #define cl82_IndLaneModes_SWSDR_div2 0 1344 #define cl82_IndLaneModes_SWSDR_div1 1 1345 #define cl82_IndLaneModes_DWSDR_div2 2 1346 #define cl82_IndLaneModes_DWSDR_div1 3 1347 1348 /**************************************************************************** 1349 * Enums: cl82_prbsSelect 1350 */ 1351 #define cl82_prbsSelect_prbs7 0 1352 #define cl82_prbsSelect_prbs15 1 1353 #define cl82_prbsSelect_prbs23 2 1354 #define cl82_prbsSelect_prbs31 3 1355 1356 /**************************************************************************** 1357 * Enums: cl82_vcoDivider 1358 */ 1359 #define cl82_vcoDivider_div32 0 1360 #define cl82_vcoDivider_div36 1 1361 #define cl82_vcoDivider_div40 2 1362 #define cl82_vcoDivider_div42 3 1363 #define cl82_vcoDivider_div48 4 1364 #define cl82_vcoDivider_div50 5 1365 #define cl82_vcoDivider_div52 6 1366 #define cl82_vcoDivider_div54 7 1367 #define cl82_vcoDivider_div60 8 1368 #define cl82_vcoDivider_div64 9 1369 #define cl82_vcoDivider_div66 10 1370 #define cl82_vcoDivider_div68 11 1371 #define cl82_vcoDivider_div70 12 1372 #define cl82_vcoDivider_div80 13 1373 #define cl82_vcoDivider_div92 14 1374 #define cl82_vcoDivider_div100 15 1375 1376 /**************************************************************************** 1377 * Enums: cl82_refClkSelect 1378 */ 1379 #define cl82_refClkSelect_clk_25MHz 0 1380 #define cl82_refClkSelect_clk_100MHz 1 1381 #define cl82_refClkSelect_clk_125MHz 2 1382 #define cl82_refClkSelect_clk_156p25MHz 3 1383 #define cl82_refClkSelect_clk_187p5MHz 4 1384 #define cl82_refClkSelect_clk_161p25Mhz 5 1385 #define cl82_refClkSelect_clk_50Mhz 6 1386 #define cl82_refClkSelect_clk_106p25Mhz 7 1387 1388 /**************************************************************************** 1389 * Enums: cl82_aerMMDdevTypeSelect 1390 */ 1391 #define cl82_aerMMDdevTypeSelect_combo_core 0 1392 #define cl82_aerMMDdevTypeSelect_PMA_PMD 1 1393 #define cl82_aerMMDdevTypeSelect_PCS 3 1394 #define cl82_aerMMDdevTypeSelect_PHY 4 1395 #define cl82_aerMMDdevTypeSelect_DTE 5 1396 #define cl82_aerMMDdevTypeSelect_CL73_AN 7 1397 1398 /**************************************************************************** 1399 * Enums: cl82_aerMMDportSelect 1400 */ 1401 #define cl82_aerMMDportSelect_ln0 0 1402 #define cl82_aerMMDportSelect_ln1 1 1403 #define cl82_aerMMDportSelect_ln2 2 1404 #define cl82_aerMMDportSelect_ln3 3 1405 #define cl82_aerMMDportSelect_BCST_ln0_1_2_3 511 1406 #define cl82_aerMMDportSelect_BCST_ln0_1 512 1407 #define cl82_aerMMDportSelect_BCST_ln2_3 513 1408 1409 /**************************************************************************** 1410 * Enums: cl82_firmwareModeSelect 1411 */ 1412 #define cl82_firmwareModeSelect_DEFAULT 0 1413 #define cl82_firmwareModeSelect_SFP_OPT_LR 1 1414 #define cl82_firmwareModeSelect_SFP_DAC 2 1415 #define cl82_firmwareModeSelect_XLAUI 3 1416 #define cl82_firmwareModeSelect_LONG_CH_6G 4 1417 1418 /**************************************************************************** 1419 * Enums: cl82_tempIdxSelect 1420 */ 1421 #define cl82_tempIdxSelect_LTE__22p9C 15 1422 #define cl82_tempIdxSelect_LTE__12p6C 14 1423 #define cl82_tempIdxSelect_LTE__3p0C 13 1424 #define cl82_tempIdxSelect_LTE_6p7C 12 1425 #define cl82_tempIdxSelect_LTE_16p4C 11 1426 #define cl82_tempIdxSelect_LTE_26p6C 10 1427 #define cl82_tempIdxSelect_LTE_36p3C 9 1428 #define cl82_tempIdxSelect_LTE_46p0C 8 1429 #define cl82_tempIdxSelect_LTE_56p2C 7 1430 #define cl82_tempIdxSelect_LTE_65p9C 6 1431 #define cl82_tempIdxSelect_LTE_75p6C 5 1432 #define cl82_tempIdxSelect_LTE_85p3C 4 1433 #define cl82_tempIdxSelect_LTE_95p5C 3 1434 #define cl82_tempIdxSelect_LTE_105p2C 2 1435 #define cl82_tempIdxSelect_LTE_114p9C 1 1436 #define cl82_tempIdxSelect_LTE_125p1C 0 1437 1438 /**************************************************************************** 1439 * Enums: cl82_port_mode 1440 */ 1441 #define cl82_port_mode_QUAD_PORT 0 1442 #define cl82_port_mode_TRI_1_PORT 1 1443 #define cl82_port_mode_TRI_2_PORT 2 1444 #define cl82_port_mode_DUAL_PORT 3 1445 #define cl82_port_mode_SINGLE_PORT 4 1446 1447 /**************************************************************************** 1448 * Enums: cl82_rev_letter_enum 1449 */ 1450 #define cl82_rev_letter_enum_REV_A 0 1451 #define cl82_rev_letter_enum_REV_B 1 1452 #define cl82_rev_letter_enum_REV_C 2 1453 #define cl82_rev_letter_enum_REV_D 3 1454 1455 /**************************************************************************** 1456 * Enums: cl82_rev_number_enum 1457 */ 1458 #define cl82_rev_number_enum_REV_0 0 1459 #define cl82_rev_number_enum_REV_1 1 1460 #define cl82_rev_number_enum_REV_2 2 1461 #define cl82_rev_number_enum_REV_3 3 1462 #define cl82_rev_number_enum_REV_4 4 1463 #define cl82_rev_number_enum_REV_5 5 1464 #define cl82_rev_number_enum_REV_6 6 1465 #define cl82_rev_number_enum_REV_7 7 1466 1467 /**************************************************************************** 1468 * Enums: cl82_bonding_enum 1469 */ 1470 #define cl82_bonding_enum_WIRE_BOND 0 1471 #define cl82_bonding_enum_FLIP_CHIP 1 1472 1473 /**************************************************************************** 1474 * Enums: cl82_tech_process 1475 */ 1476 #define cl82_tech_process_PROCESS_90NM 0 1477 #define cl82_tech_process_PROCESS_65NM 1 1478 #define cl82_tech_process_PROCESS_40NM 2 1479 #define cl82_tech_process_PROCESS_28NM 3 1480 #define cl82_tech_process_PROCESS_16NM 4 1481 1482 /**************************************************************************** 1483 * Enums: cl82_model_num 1484 */ 1485 #define cl82_model_num_SERDES_CL73 0 1486 #define cl82_model_num_XGXS_16G 1 1487 #define cl82_model_num_HYPERCORE 2 1488 #define cl82_model_num_HYPERLITE 3 1489 #define cl82_model_num_PCIE_G2_PIPE 4 1490 #define cl82_model_num_SERDES_1p25GBd 5 1491 #define cl82_model_num_SATA2 6 1492 #define cl82_model_num_QSGMII 7 1493 #define cl82_model_num_XGXS10G 8 1494 #define cl82_model_num_WARPCORE 9 1495 #define cl82_model_num_XFICORE 10 1496 #define cl82_model_num_RXFI 11 1497 #define cl82_model_num_WARPLITE 12 1498 #define cl82_model_num_PENTACORE 13 1499 #define cl82_model_num_ESM 14 1500 #define cl82_model_num_QUAD_SGMII 15 1501 #define cl82_model_num_WARPCORE_3 16 1502 #define cl82_model_num_TSC 17 1503 #define cl82_model_num_TSC4E 18 1504 #define cl82_model_num_TSC12E 19 1505 #define cl82_model_num_TSC4F 20 1506 #define cl82_model_num_TSC4F_GEN2 21 1507 #define cl82_model_num_XGXS_CL73_90NM 29 1508 #define cl82_model_num_SERDES_CL73_90NM 30 1509 #define cl82_model_num_WARPCORE3 32 1510 #define cl82_model_num_WARPCORE4_TSC 33 1511 #define cl82_model_num_RXAUI 34 1512 1513 /**************************************************************************** 1514 * Enums: cl82_payload 1515 */ 1516 #define cl82_payload_REPEAT_2_BYTES 0 1517 #define cl82_payload_RAMPING 1 1518 #define cl82_payload_CL48_CRPAT 2 1519 #define cl82_payload_CL48_CJPAT 3 1520 #define cl82_payload_CL36_LONG_CRPAT 4 1521 #define cl82_payload_CL36_SHORT_CRPAT 5 1522 1523 /**************************************************************************** 1524 * Enums: cl82_sc 1525 */ 1526 #define cl82_sc_S_10G_CR1 0 1527 #define cl82_sc_S_10G_KR1 1 1528 #define cl82_sc_S_10G_X1 2 1529 #define cl82_sc_S_10G_HG2_CR1 4 1530 #define cl82_sc_S_10G_HG2_KR1 5 1531 #define cl82_sc_S_10G_HG2_X1 6 1532 #define cl82_sc_S_20G_CR1 8 1533 #define cl82_sc_S_20G_KR1 9 1534 #define cl82_sc_S_20G_X1 10 1535 #define cl82_sc_S_20G_HG2_CR1 12 1536 #define cl82_sc_S_20G_HG2_KR1 13 1537 #define cl82_sc_S_20G_HG2_X1 14 1538 #define cl82_sc_S_25G_CR1 16 1539 #define cl82_sc_S_25G_KR1 17 1540 #define cl82_sc_S_25G_X1 18 1541 #define cl82_sc_S_25G_HG2_CR1 20 1542 #define cl82_sc_S_25G_HG2_KR1 21 1543 #define cl82_sc_S_25G_HG2_X1 22 1544 #define cl82_sc_S_20G_CR2 24 1545 #define cl82_sc_S_20G_KR2 25 1546 #define cl82_sc_S_20G_X2 26 1547 #define cl82_sc_S_20G_HG2_CR2 28 1548 #define cl82_sc_S_20G_HG2_KR2 29 1549 #define cl82_sc_S_20G_HG2_X2 30 1550 #define cl82_sc_S_40G_CR2 32 1551 #define cl82_sc_S_40G_KR2 33 1552 #define cl82_sc_S_40G_X2 34 1553 #define cl82_sc_S_40G_HG2_CR2 36 1554 #define cl82_sc_S_40G_HG2_KR2 37 1555 #define cl82_sc_S_40G_HG2_X2 38 1556 #define cl82_sc_S_40G_CR4 40 1557 #define cl82_sc_S_40G_KR4 41 1558 #define cl82_sc_S_40G_X4 42 1559 #define cl82_sc_S_40G_HG2_CR4 44 1560 #define cl82_sc_S_40G_HG2_KR4 45 1561 #define cl82_sc_S_40G_HG2_X4 46 1562 #define cl82_sc_S_50G_CR2 48 1563 #define cl82_sc_S_50G_KR2 49 1564 #define cl82_sc_S_50G_X2 50 1565 #define cl82_sc_S_50G_HG2_CR2 52 1566 #define cl82_sc_S_50G_HG2_KR2 53 1567 #define cl82_sc_S_50G_HG2_X2 54 1568 #define cl82_sc_S_50G_CR4 56 1569 #define cl82_sc_S_50G_KR4 57 1570 #define cl82_sc_S_50G_X4 58 1571 #define cl82_sc_S_50G_HG2_CR4 60 1572 #define cl82_sc_S_50G_HG2_KR4 61 1573 #define cl82_sc_S_50G_HG2_X4 62 1574 #define cl82_sc_S_100G_CR4 64 1575 #define cl82_sc_S_100G_KR4 65 1576 #define cl82_sc_S_100G_X4 66 1577 #define cl82_sc_S_100G_HG2_CR4 68 1578 #define cl82_sc_S_100G_HG2_KR4 69 1579 #define cl82_sc_S_100G_HG2_X4 70 1580 #define cl82_sc_S_CL73_20GVCO 72 1581 #define cl82_sc_S_CL73_25GVCO 80 1582 #define cl82_sc_S_CL36_20GVCO 88 1583 #define cl82_sc_S_CL36_25GVCO 96 1584 #define cl82_sc_S_25G_CR_IEEE 112 1585 #define cl82_sc_S_25G_CRS_IEEE 113 1586 #define cl82_sc_S_25G_KR_IEEE 114 1587 #define cl82_sc_S_25G_KRS_IEEE 115 1588 1589 /**************************************************************************** 1590 * Enums: cl82_t_fifo_modes 1591 */ 1592 #define cl82_t_fifo_modes_T_FIFO_INSERT_NO_AM 0 1593 #define cl82_t_fifo_modes_T_FIFO_INSERT_4_AM 1 1594 #define cl82_t_fifo_modes_T_FIFO_INSERT_20_AM 2 1595 #define cl82_t_fifo_modes_T_FIFO_INSERT_2_AM 3 1596 1597 /**************************************************************************** 1598 * Enums: cl82_t_enc_modes 1599 */ 1600 #define cl82_t_enc_modes_T_ENC_MODE_BYPASS 0 1601 #define cl82_t_enc_modes_T_ENC_MODE_CL49 1 1602 #define cl82_t_enc_modes_T_ENC_MODE_CL82 2 1603 1604 /**************************************************************************** 1605 * Enums: cl82_btmx_mode 1606 */ 1607 #define cl82_btmx_mode_BS_BTMX_MODE_1to1 0 1608 #define cl82_btmx_mode_BS_BTMX_MODE_2to1 1 1609 #define cl82_btmx_mode_BS_BTMX_MODE_5to1 2 1610 1611 /**************************************************************************** 1612 * Enums: cl82_t_type_cl82 1613 */ 1614 #define cl82_t_type_cl82_T_TYPE_B1 5 1615 #define cl82_t_type_cl82_T_TYPE_C 4 1616 #define cl82_t_type_cl82_T_TYPE_S 3 1617 #define cl82_t_type_cl82_T_TYPE_T 2 1618 #define cl82_t_type_cl82_T_TYPE_D 1 1619 #define cl82_t_type_cl82_T_TYPE_E 0 1620 1621 /**************************************************************************** 1622 * Enums: cl82_txsm_state_cl82 1623 */ 1624 #define cl82_txsm_state_cl82_TX_HIG_END 6 1625 #define cl82_txsm_state_cl82_TX_HIG_START 5 1626 #define cl82_txsm_state_cl82_TX_E 4 1627 #define cl82_txsm_state_cl82_TX_T 3 1628 #define cl82_txsm_state_cl82_TX_D 2 1629 #define cl82_txsm_state_cl82_TX_C 1 1630 #define cl82_txsm_state_cl82_TX_INIT 0 1631 1632 /**************************************************************************** 1633 * Enums: cl82_ltxsm_state_cl82 1634 */ 1635 #define cl82_ltxsm_state_cl82_TX_HIG_END 64 1636 #define cl82_ltxsm_state_cl82_TX_HIG_START 32 1637 #define cl82_ltxsm_state_cl82_TX_E 16 1638 #define cl82_ltxsm_state_cl82_TX_T 8 1639 #define cl82_ltxsm_state_cl82_TX_D 4 1640 #define cl82_ltxsm_state_cl82_TX_C 2 1641 #define cl82_ltxsm_state_cl82_TX_INIT 1 1642 1643 /**************************************************************************** 1644 * Enums: cl82_r_type_coded_cl82 1645 */ 1646 #define cl82_r_type_coded_cl82_R_TYPE_B1 32 1647 #define cl82_r_type_coded_cl82_R_TYPE_C 16 1648 #define cl82_r_type_coded_cl82_R_TYPE_S 8 1649 #define cl82_r_type_coded_cl82_R_TYPE_T 4 1650 #define cl82_r_type_coded_cl82_R_TYPE_D 2 1651 #define cl82_r_type_coded_cl82_R_TYPE_E 1 1652 1653 /**************************************************************************** 1654 * Enums: cl82_rxsm_state_cl82 1655 */ 1656 #define cl82_rxsm_state_cl82_RX_HIG_END 64 1657 #define cl82_rxsm_state_cl82_RX_HIG_START 32 1658 #define cl82_rxsm_state_cl82_RX_E 16 1659 #define cl82_rxsm_state_cl82_RX_T 8 1660 #define cl82_rxsm_state_cl82_RX_D 4 1661 #define cl82_rxsm_state_cl82_RX_C 2 1662 #define cl82_rxsm_state_cl82_RX_INIT 1 1663 1664 /**************************************************************************** 1665 * Enums: cl82_deskew_state 1666 */ 1667 #define cl82_deskew_state_ALIGN_ACQUIRED 2 1668 #define cl82_deskew_state_LOSS_OF_ALIGNMENT 1 1669 1670 /**************************************************************************** 1671 * Enums: cl82_os_mode_enum 1672 */ 1673 #define cl82_os_mode_enum_OS_MODE_1 0 1674 #define cl82_os_mode_enum_OS_MODE_2 1 1675 #define cl82_os_mode_enum_OS_MODE_4 2 1676 #define cl82_os_mode_enum_OS_MODE_16p5 8 1677 #define cl82_os_mode_enum_OS_MODE_20p625 12 1678 1679 /**************************************************************************** 1680 * Enums: cl82_scr_modes 1681 */ 1682 #define cl82_scr_modes_T_SCR_MODE_BYPASS 0 1683 #define cl82_scr_modes_T_SCR_MODE_CL49 1 1684 #define cl82_scr_modes_T_SCR_MODE_40G_2_LANE 2 1685 #define cl82_scr_modes_T_SCR_MODE_100G 3 1686 #define cl82_scr_modes_T_SCR_MODE_20G 4 1687 #define cl82_scr_modes_T_SCR_MODE_40G_4_LANE 5 1688 1689 /**************************************************************************** 1690 * Enums: cl82_descr_modes 1691 */ 1692 #define cl82_descr_modes_R_DESCR_MODE_BYPASS 0 1693 #define cl82_descr_modes_R_DESCR_MODE_CL49 1 1694 #define cl82_descr_modes_R_DESCR_MODE_CL82 2 1695 1696 /**************************************************************************** 1697 * Enums: cl82_r_dec_tl_mode 1698 */ 1699 #define cl82_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 1700 #define cl82_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 1701 #define cl82_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 1702 1703 /**************************************************************************** 1704 * Enums: cl82_r_dec_fsm_mode 1705 */ 1706 #define cl82_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 1707 #define cl82_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 1708 #define cl82_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 1709 1710 /**************************************************************************** 1711 * Enums: cl82_r_deskew_mode 1712 */ 1713 #define cl82_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 1714 #define cl82_r_deskew_mode_R_DESKEW_MODE_20G 1 1715 #define cl82_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 1716 #define cl82_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 1717 #define cl82_r_deskew_mode_R_DESKEW_MODE_100G 4 1718 #define cl82_r_deskew_mode_R_DESKEW_MODE_CL49 5 1719 #define cl82_r_deskew_mode_R_DESKEW_MODE_CL91_QUAD 6 1720 #define cl82_r_deskew_mode_R_DESKEW_MODE_CL91_SINGLE_BRCM 7 1721 #define cl82_r_deskew_mode_R_DESKEW_MODE_CL91_DUAL_BRCM 8 1722 #define cl82_r_deskew_mode_R_DESKEW_MODE_CL91_FC 9 1723 1724 /**************************************************************************** 1725 * Enums: cl82_bs_dist_modes 1726 */ 1727 #define cl82_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 1728 #define cl82_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 1729 #define cl82_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 1730 #define cl82_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 1731 1732 /**************************************************************************** 1733 * Enums: cl82_cl49_t_type 1734 */ 1735 #define cl82_cl49_t_type_BAD_T_TYPE 15 1736 #define cl82_cl49_t_type_T_TYPE_B0 11 1737 #define cl82_cl49_t_type_T_TYPE_OB 10 1738 #define cl82_cl49_t_type_T_TYPE_B1 9 1739 #define cl82_cl49_t_type_T_TYPE_DB 8 1740 #define cl82_cl49_t_type_T_TYPE_FC 7 1741 #define cl82_cl49_t_type_T_TYPE_TB 6 1742 #define cl82_cl49_t_type_T_TYPE_LI 5 1743 #define cl82_cl49_t_type_T_TYPE_C 4 1744 #define cl82_cl49_t_type_T_TYPE_S 3 1745 #define cl82_cl49_t_type_T_TYPE_T 2 1746 #define cl82_cl49_t_type_T_TYPE_D 1 1747 #define cl82_cl49_t_type_T_TYPE_E 0 1748 1749 /**************************************************************************** 1750 * Enums: cl82_cl49_txsm_states 1751 */ 1752 #define cl82_cl49_txsm_states_TX_HIG_END 7 1753 #define cl82_cl49_txsm_states_TX_HIG_START 6 1754 #define cl82_cl49_txsm_states_TX_LI 5 1755 #define cl82_cl49_txsm_states_TX_E 4 1756 #define cl82_cl49_txsm_states_TX_T 3 1757 #define cl82_cl49_txsm_states_TX_D 2 1758 #define cl82_cl49_txsm_states_TX_C 1 1759 #define cl82_cl49_txsm_states_TX_INIT 0 1760 1761 /**************************************************************************** 1762 * Enums: cl82_cl49_ltxsm_states 1763 */ 1764 #define cl82_cl49_ltxsm_states_TX_HIG_END 128 1765 #define cl82_cl49_ltxsm_states_TX_HIG_START 64 1766 #define cl82_cl49_ltxsm_states_TX_LI 32 1767 #define cl82_cl49_ltxsm_states_TX_E 16 1768 #define cl82_cl49_ltxsm_states_TX_T 8 1769 #define cl82_cl49_ltxsm_states_TX_D 4 1770 #define cl82_cl49_ltxsm_states_TX_C 2 1771 #define cl82_cl49_ltxsm_states_TX_INIT 1 1772 1773 /**************************************************************************** 1774 * Enums: cl82_burst_error_mode 1775 */ 1776 #define cl82_burst_error_mode_BURST_ERROR_11_BITS 0 1777 #define cl82_burst_error_mode_BURST_ERROR_16_BITS 1 1778 #define cl82_burst_error_mode_BURST_ERROR_17_BITS 2 1779 #define cl82_burst_error_mode_BURST_ERROR_18_BITS 3 1780 #define cl82_burst_error_mode_BURST_ERROR_19_BITS 4 1781 #define cl82_burst_error_mode_BURST_ERROR_20_BITS 5 1782 #define cl82_burst_error_mode_BURST_ERROR_21_BITS 6 1783 #define cl82_burst_error_mode_BURST_ERROR_22_BITS 7 1784 #define cl82_burst_error_mode_BURST_ERROR_23_BITS 8 1785 #define cl82_burst_error_mode_BURST_ERROR_24_BITS 9 1786 #define cl82_burst_error_mode_BURST_ERROR_25_BITS 10 1787 #define cl82_burst_error_mode_BURST_ERROR_26_BITS 11 1788 #define cl82_burst_error_mode_BURST_ERROR_27_BITS 12 1789 #define cl82_burst_error_mode_BURST_ERROR_28_BITS 13 1790 #define cl82_burst_error_mode_BURST_ERROR_29_BITS 14 1791 #define cl82_burst_error_mode_BURST_ERROR_30_BITS 15 1792 #define cl82_burst_error_mode_BURST_ERROR_31_BITS 16 1793 #define cl82_burst_error_mode_BURST_ERROR_32_BITS 17 1794 #define cl82_burst_error_mode_BURST_ERROR_33_BITS 18 1795 #define cl82_burst_error_mode_BURST_ERROR_34_BITS 19 1796 #define cl82_burst_error_mode_BURST_ERROR_35_BITS 20 1797 #define cl82_burst_error_mode_BURST_ERROR_36_BITS 21 1798 #define cl82_burst_error_mode_BURST_ERROR_37_BITS 22 1799 #define cl82_burst_error_mode_BURST_ERROR_38_BITS 23 1800 #define cl82_burst_error_mode_BURST_ERROR_39_BITS 24 1801 #define cl82_burst_error_mode_BURST_ERROR_40_BITS 25 1802 #define cl82_burst_error_mode_BURST_ERROR_41_BITS 26 1803 1804 /**************************************************************************** 1805 * Enums: cl82_bermon_state 1806 */ 1807 #define cl82_bermon_state_HI_BER 4 1808 #define cl82_bermon_state_GOOD_BER 3 1809 #define cl82_bermon_state_BER_TEST_SH 2 1810 #define cl82_bermon_state_START_TIMER 1 1811 #define cl82_bermon_state_BER_MT_INIT 0 1812 1813 /**************************************************************************** 1814 * Enums: cl82_rxsm_state_cl49 1815 */ 1816 #define cl82_rxsm_state_cl49_RX_HIG_END 128 1817 #define cl82_rxsm_state_cl49_RX_HIG_START 64 1818 #define cl82_rxsm_state_cl49_RX_LI 32 1819 #define cl82_rxsm_state_cl49_RX_E 16 1820 #define cl82_rxsm_state_cl49_RX_T 8 1821 #define cl82_rxsm_state_cl49_RX_D 4 1822 #define cl82_rxsm_state_cl49_RX_C 2 1823 #define cl82_rxsm_state_cl49_RX_INIT 1 1824 1825 /**************************************************************************** 1826 * Enums: cl82_r_type 1827 */ 1828 #define cl82_r_type_BAD_R_TYPE 15 1829 #define cl82_r_type_R_TYPE_B0 11 1830 #define cl82_r_type_R_TYPE_OB 10 1831 #define cl82_r_type_R_TYPE_B1 9 1832 #define cl82_r_type_R_TYPE_DB 8 1833 #define cl82_r_type_R_TYPE_FC 7 1834 #define cl82_r_type_R_TYPE_TB 6 1835 #define cl82_r_type_R_TYPE_LI 5 1836 #define cl82_r_type_R_TYPE_C 4 1837 #define cl82_r_type_R_TYPE_S 3 1838 #define cl82_r_type_R_TYPE_T 2 1839 #define cl82_r_type_R_TYPE_D 1 1840 #define cl82_r_type_R_TYPE_E 0 1841 1842 /**************************************************************************** 1843 * Enums: cl82_am_lock_state 1844 */ 1845 #define cl82_am_lock_state_INVALID_AM 512 1846 #define cl82_am_lock_state_GOOD_AM 256 1847 #define cl82_am_lock_state_COMP_AM 128 1848 #define cl82_am_lock_state_TIMER_2 64 1849 #define cl82_am_lock_state_AM_2_GOOD 32 1850 #define cl82_am_lock_state_COMP_2ND 16 1851 #define cl82_am_lock_state_TIMER_1 8 1852 #define cl82_am_lock_state_FIND_1ST 4 1853 #define cl82_am_lock_state_AM_RESET_CNT 2 1854 #define cl82_am_lock_state_AM_LOCK_INIT 1 1855 1856 /**************************************************************************** 1857 * Enums: cl82_msg_selector 1858 */ 1859 #define cl82_msg_selector_RESERVED 0 1860 #define cl82_msg_selector_VALUE_802p3 1 1861 #define cl82_msg_selector_VALUE_802p9 2 1862 #define cl82_msg_selector_VALUE_802p5 3 1863 #define cl82_msg_selector_VALUE_1394 4 1864 1865 /**************************************************************************** 1866 * Enums: cl82_synce_enum 1867 */ 1868 #define cl82_synce_enum_SYNCE_NO_DIV 0 1869 #define cl82_synce_enum_SYNCE_DIV_7 1 1870 #define cl82_synce_enum_SYNCE_DIV_11 2 1871 1872 /**************************************************************************** 1873 * Enums: cl82_synce_enum_stage0 1874 */ 1875 #define cl82_synce_enum_stage0_SYNCE_NO_DIV 0 1876 #define cl82_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 1877 #define cl82_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 1878 1879 /**************************************************************************** 1880 * Enums: cl82_cl91_sync_state 1881 */ 1882 #define cl82_cl91_sync_state_FIND_1ST 0 1883 #define cl82_cl91_sync_state_COUNT_NEXT 1 1884 #define cl82_cl91_sync_state_COMP_2ND 2 1885 #define cl82_cl91_sync_state_TWO_GOOD 3 1886 1887 /**************************************************************************** 1888 * Enums: cl82_cl91_algn_state 1889 */ 1890 #define cl82_cl91_algn_state_LOSS_OF_ALIGNMENT 0 1891 #define cl82_cl91_algn_state_DESKEW 1 1892 #define cl82_cl91_algn_state_DESKEW_FAIL 2 1893 #define cl82_cl91_algn_state_ALIGN_ACQUIRED 3 1894 #define cl82_cl91_algn_state_CW_GOOD 4 1895 #define cl82_cl91_algn_state_CW_BAD 5 1896 #define cl82_cl91_algn_state_THREE_BAD 6 1897 1898 /**************************************************************************** 1899 * Enums: cl82_fec_sel_override 1900 */ 1901 #define cl82_fec_sel_override_NO_OVERRIDE 0 1902 #define cl82_fec_sel_override_NO_FEC 1 1903 #define cl82_fec_sel_override_FEC_CL74 2 1904 #define cl82_fec_sel_override_FEC_CL91 3 1905 1906 /**************************************************************************** 1907 * Enums: cl82_cl91_blksync_mode 1908 */ 1909 #define cl82_cl91_blksync_mode_R_BLKSYNC_NO_CL91_FEC 0 1910 #define cl82_cl91_blksync_mode_R_BLKSYNC_CL91_QUAD_LANE_FEC 1 1911 #define cl82_cl91_blksync_mode_R_BLKSYNC_CL91_DUAL_LANE_FEC 2 1912 #define cl82_cl91_blksync_mode_R_BLKSYNC_CL91_SINGLE_LANE_FEC 3 1913 #define cl82_cl91_blksync_mode_R_BLKSYNC_CL91_FC_FEC 4 1914 1915 /**************************************************************************** 1916 * Enums: cl82_r_merge_mode 1917 */ 1918 #define cl82_r_merge_mode_R_MERGE_MODE_BYPASS 0 1919 #define cl82_r_merge_mode_R_MERGE_MODE_CL91_FC 1 1920 #define cl82_r_merge_mode_R_MERGE_MODE_CL91_SINGLE_LANE 2 1921 #define cl82_r_merge_mode_R_MERGE_MODE_CL91_DUAL_LANE 3 1922 #define cl82_r_merge_mode_R_MERGE_MODE_CL91_QUAD_LANE 4 1923 1924 /**************************************************************************** 1925 * Enums: cl82_r_tc_mode 1926 */ 1927 #define cl82_r_tc_mode_R_TC_MODE_SINGLE 0 1928 #define cl82_r_tc_mode_R_TC_MODE_DUAL 1 1929 #define cl82_r_tc_mode_R_TC_MODE_QUAD 2 1930 1931 /**************************************************************************** 1932 * Enums: cl82_r_tc_out_mode 1933 */ 1934 #define cl82_r_tc_out_mode_R_TC_OUT_MODE_SINGLE 0 1935 #define cl82_r_tc_out_mode_R_TC_OUT_MODE_DUAL 1 1936 #define cl82_r_tc_out_mode_R_TC_OUT_MODE_QUAD 2 1937 1938 /**************************************************************************** 1939 * Enums: cl82_cl91_fec_mode 1940 */ 1941 #define cl82_cl91_fec_mode_NO_CL91_FEC 0 1942 #define cl82_cl91_fec_mode_CL91_SINGLE_LANE_FC 1 1943 #define cl82_cl91_fec_mode_CL91_SINGLE_LANE_BRCM_PROP 2 1944 #define cl82_cl91_fec_mode_CL91_DUAL_LANE_BRCM_PROP 3 1945 #define cl82_cl91_fec_mode_CL91_QUAD_LANE 4 1946 #define cl82_cl91_fec_mode_IEEE_25G_CL91_SINGLE_LANE 5 1947 1948 /**************************************************************************** 1949 * Enums: cl82_am_spacing_mul 1950 */ 1951 #define cl82_am_spacing_mul_AM_SPACING_MUL_2 0 1952 #define cl82_am_spacing_mul_AM_SPACING_MUL_4 1 1953 #define cl82_am_spacing_mul_AM_SPACING_MUL_5 2 1954 #define cl82_am_spacing_mul_AM_SPACING_MUL_20 3 1955 1956 /**************************************************************************** 1957 * Enums: main0_cl36TxEEEStates_l 1958 */ 1959 #define main0_cl36TxEEEStates_l_TX_REFRESH 8 1960 #define main0_cl36TxEEEStates_l_TX_QUIET 4 1961 #define main0_cl36TxEEEStates_l_TX_SLEEP 2 1962 #define main0_cl36TxEEEStates_l_TX_ACTIVE 1 1963 1964 /**************************************************************************** 1965 * Enums: main0_cl36TxEEEStates_c 1966 */ 1967 #define main0_cl36TxEEEStates_c_TX_REFRESH 3 1968 #define main0_cl36TxEEEStates_c_TX_QUIET 2 1969 #define main0_cl36TxEEEStates_c_TX_SLEEP 1 1970 #define main0_cl36TxEEEStates_c_TX_ACTIVE 0 1971 1972 /**************************************************************************** 1973 * Enums: main0_cl49TxEEEStates_l 1974 */ 1975 #define main0_cl49TxEEEStates_l_SCR_RESET_2 64 1976 #define main0_cl49TxEEEStates_l_SCR_RESET_1 32 1977 #define main0_cl49TxEEEStates_l_TX_WAKE 16 1978 #define main0_cl49TxEEEStates_l_TX_REFRESH 8 1979 #define main0_cl49TxEEEStates_l_TX_QUIET 4 1980 #define main0_cl49TxEEEStates_l_TX_SLEEP 2 1981 #define main0_cl49TxEEEStates_l_TX_ACTIVE 1 1982 1983 /**************************************************************************** 1984 * Enums: main0_fec_req_enum 1985 */ 1986 #define main0_fec_req_enum_FEC_not_supported 0 1987 #define main0_fec_req_enum_FEC_supported_but_not_requested 1 1988 #define main0_fec_req_enum_invalid_setting 2 1989 #define main0_fec_req_enum_FEC_supported_and_requested 3 1990 1991 /**************************************************************************** 1992 * Enums: main0_cl73_pause_enum 1993 */ 1994 #define main0_cl73_pause_enum_No_PAUSE_ability 0 1995 #define main0_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 1996 #define main0_cl73_pause_enum_Symmetric_PAUSE_ability 1 1997 #define main0_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 1998 1999 /**************************************************************************** 2000 * Enums: main0_cl49TxEEEStates_c 2001 */ 2002 #define main0_cl49TxEEEStates_c_SCR_RESET_2 6 2003 #define main0_cl49TxEEEStates_c_SCR_RESET_1 5 2004 #define main0_cl49TxEEEStates_c_TX_WAKE 4 2005 #define main0_cl49TxEEEStates_c_TX_REFRESH 3 2006 #define main0_cl49TxEEEStates_c_TX_QUIET 2 2007 #define main0_cl49TxEEEStates_c_TX_SLEEP 1 2008 #define main0_cl49TxEEEStates_c_TX_ACTIVE 0 2009 2010 /**************************************************************************** 2011 * Enums: main0_cl36RxEEEStates_l 2012 */ 2013 #define main0_cl36RxEEEStates_l_RX_LINK_FAIL 32 2014 #define main0_cl36RxEEEStates_l_RX_WTF 16 2015 #define main0_cl36RxEEEStates_l_RX_WAKE 8 2016 #define main0_cl36RxEEEStates_l_RX_QUIET 4 2017 #define main0_cl36RxEEEStates_l_RX_SLEEP 2 2018 #define main0_cl36RxEEEStates_l_RX_ACTIVE 1 2019 2020 /**************************************************************************** 2021 * Enums: main0_cl36RxEEEStates_c 2022 */ 2023 #define main0_cl36RxEEEStates_c_RX_LINK_FAIL 5 2024 #define main0_cl36RxEEEStates_c_RX_WTF 4 2025 #define main0_cl36RxEEEStates_c_RX_WAKE 3 2026 #define main0_cl36RxEEEStates_c_RX_QUIET 2 2027 #define main0_cl36RxEEEStates_c_RX_SLEEP 1 2028 #define main0_cl36RxEEEStates_c_RX_ACTIVE 0 2029 2030 /**************************************************************************** 2031 * Enums: main0_cl49RxEEEStates_l 2032 */ 2033 #define main0_cl49RxEEEStates_l_RX_LINK_FAIL 32 2034 #define main0_cl49RxEEEStates_l_RX_WTF 16 2035 #define main0_cl49RxEEEStates_l_RX_WAKE 8 2036 #define main0_cl49RxEEEStates_l_RX_QUIET 4 2037 #define main0_cl49RxEEEStates_l_RX_SLEEP 2 2038 #define main0_cl49RxEEEStates_l_RX_ACTIVE 1 2039 2040 /**************************************************************************** 2041 * Enums: main0_cl49RxEEEStates_c 2042 */ 2043 #define main0_cl49RxEEEStates_c_RX_LINK_FAIL 5 2044 #define main0_cl49RxEEEStates_c_RX_WTF 4 2045 #define main0_cl49RxEEEStates_c_RX_WAKE 3 2046 #define main0_cl49RxEEEStates_c_RX_QUIET 2 2047 #define main0_cl49RxEEEStates_c_RX_SLEEP 1 2048 #define main0_cl49RxEEEStates_c_RX_ACTIVE 0 2049 2050 /**************************************************************************** 2051 * Enums: main0_cl48TxEEEStates_l 2052 */ 2053 #define main0_cl48TxEEEStates_l_TX_REFRESH 8 2054 #define main0_cl48TxEEEStates_l_TX_QUIET 4 2055 #define main0_cl48TxEEEStates_l_TX_SLEEP 2 2056 #define main0_cl48TxEEEStates_l_TX_ACTIVE 1 2057 2058 /**************************************************************************** 2059 * Enums: main0_cl48TxEEEStates_c 2060 */ 2061 #define main0_cl48TxEEEStates_c_TX_REFRESH 3 2062 #define main0_cl48TxEEEStates_c_TX_QUIET 2 2063 #define main0_cl48TxEEEStates_c_TX_SLEEP 1 2064 #define main0_cl48TxEEEStates_c_TX_ACTIVE 0 2065 2066 /**************************************************************************** 2067 * Enums: main0_cl48RxEEEStates_l 2068 */ 2069 #define main0_cl48RxEEEStates_l_RX_LINK_FAIL 32 2070 #define main0_cl48RxEEEStates_l_RX_WAKE 16 2071 #define main0_cl48RxEEEStates_l_RX_QUIET 8 2072 #define main0_cl48RxEEEStates_l_RX_DEACT 4 2073 #define main0_cl48RxEEEStates_l_RX_SLEEP 2 2074 #define main0_cl48RxEEEStates_l_RX_ACTIVE 1 2075 2076 /**************************************************************************** 2077 * Enums: main0_cl48RxEEEStates_c 2078 */ 2079 #define main0_cl48RxEEEStates_c_RX_LINK_FAIL 5 2080 #define main0_cl48RxEEEStates_c_RX_WAKE 4 2081 #define main0_cl48RxEEEStates_c_RX_QUIET 3 2082 #define main0_cl48RxEEEStates_c_RX_DEACT 2 2083 #define main0_cl48RxEEEStates_c_RX_SLEEP 1 2084 #define main0_cl48RxEEEStates_c_RX_ACTIVE 0 2085 2086 /**************************************************************************** 2087 * Enums: main0_IQP_Options 2088 */ 2089 #define main0_IQP_Options_i50uA 0 2090 #define main0_IQP_Options_i100uA 1 2091 #define main0_IQP_Options_i150uA 2 2092 #define main0_IQP_Options_i200uA 3 2093 #define main0_IQP_Options_i250uA 4 2094 #define main0_IQP_Options_i300uA 5 2095 #define main0_IQP_Options_i350uA 6 2096 #define main0_IQP_Options_i400uA 7 2097 #define main0_IQP_Options_i450uA 8 2098 #define main0_IQP_Options_i500uA 9 2099 #define main0_IQP_Options_i550uA 10 2100 #define main0_IQP_Options_i600uA 11 2101 #define main0_IQP_Options_i650uA 12 2102 #define main0_IQP_Options_i700uA 13 2103 #define main0_IQP_Options_i750uA 14 2104 #define main0_IQP_Options_i800uA 15 2105 2106 /**************************************************************************** 2107 * Enums: main0_IDriver_Options 2108 */ 2109 #define main0_IDriver_Options_v680mV 0 2110 #define main0_IDriver_Options_v730mV 1 2111 #define main0_IDriver_Options_v780mV 2 2112 #define main0_IDriver_Options_v830mV 3 2113 #define main0_IDriver_Options_v880mV 4 2114 #define main0_IDriver_Options_v930mV 5 2115 #define main0_IDriver_Options_v980mV 6 2116 #define main0_IDriver_Options_v1010mV 7 2117 #define main0_IDriver_Options_v1040mV 8 2118 #define main0_IDriver_Options_v1060mV 9 2119 #define main0_IDriver_Options_v1070mV 10 2120 #define main0_IDriver_Options_v1080mV 11 2121 #define main0_IDriver_Options_v1085mV 12 2122 #define main0_IDriver_Options_v1090mV 13 2123 #define main0_IDriver_Options_v1095mV 14 2124 #define main0_IDriver_Options_v1100mV 15 2125 2126 /**************************************************************************** 2127 * Enums: main0_operationModes 2128 */ 2129 #define main0_operationModes_XGXS 0 2130 #define main0_operationModes_XGXG_nCC 1 2131 #define main0_operationModes_Indlane_OS8 4 2132 #define main0_operationModes_IndLane_OS5 5 2133 #define main0_operationModes_PCI 7 2134 #define main0_operationModes_XGXS_nLQ 8 2135 #define main0_operationModes_XGXS_nLQnCC 9 2136 #define main0_operationModes_PBypass 10 2137 #define main0_operationModes_PBypass_nDSK 11 2138 #define main0_operationModes_ComboCoreMode 12 2139 #define main0_operationModes_Clocks_off 15 2140 2141 /**************************************************************************** 2142 * Enums: main0_actualSpeeds 2143 */ 2144 #define main0_actualSpeeds_dr_10M 0 2145 #define main0_actualSpeeds_dr_100M 1 2146 #define main0_actualSpeeds_dr_1G 2 2147 #define main0_actualSpeeds_dr_2p5G 3 2148 #define main0_actualSpeeds_dr_5G_X4 4 2149 #define main0_actualSpeeds_dr_6G_X4 5 2150 #define main0_actualSpeeds_dr_10G_HiG 6 2151 #define main0_actualSpeeds_dr_10G_CX4 7 2152 #define main0_actualSpeeds_dr_12G_HiG 8 2153 #define main0_actualSpeeds_dr_12p5G_X4 9 2154 #define main0_actualSpeeds_dr_13G_X4 10 2155 #define main0_actualSpeeds_dr_15G_X4 11 2156 #define main0_actualSpeeds_dr_16G_X4 12 2157 #define main0_actualSpeeds_dr_1G_KX 13 2158 #define main0_actualSpeeds_dr_10G_KX4 14 2159 #define main0_actualSpeeds_dr_10G_KR 15 2160 #define main0_actualSpeeds_dr_5G 16 2161 #define main0_actualSpeeds_dr_6p4G 17 2162 #define main0_actualSpeeds_dr_20G_X4 18 2163 #define main0_actualSpeeds_dr_21G_X4 19 2164 #define main0_actualSpeeds_dr_25G_X4 20 2165 #define main0_actualSpeeds_dr_10G_HiG_DXGXS 21 2166 #define main0_actualSpeeds_dr_10G_DXGXS 22 2167 #define main0_actualSpeeds_dr_10p5G_HiG_DXGXS 23 2168 #define main0_actualSpeeds_dr_10p5G_DXGXS 24 2169 #define main0_actualSpeeds_dr_12p773G_HiG_DXGXS 25 2170 #define main0_actualSpeeds_dr_12p773G_DXGXS 26 2171 #define main0_actualSpeeds_dr_10G_XFI 27 2172 #define main0_actualSpeeds_dr_40G 28 2173 #define main0_actualSpeeds_dr_20G_HiG_DXGXS 29 2174 #define main0_actualSpeeds_dr_20G_DXGXS 30 2175 #define main0_actualSpeeds_dr_10G_SFI 31 2176 #define main0_actualSpeeds_dr_31p5G 32 2177 #define main0_actualSpeeds_dr_32p7G 33 2178 #define main0_actualSpeeds_dr_20G_SCR 34 2179 #define main0_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 2180 #define main0_actualSpeeds_dr_10G_DXGXS_SCR 36 2181 #define main0_actualSpeeds_dr_12G_R2 37 2182 #define main0_actualSpeeds_dr_10G_X2 38 2183 #define main0_actualSpeeds_dr_40G_KR4 39 2184 #define main0_actualSpeeds_dr_40G_CR4 40 2185 #define main0_actualSpeeds_dr_100G_CR10 41 2186 #define main0_actualSpeeds_dr_15p75G_DXGXS 44 2187 #define main0_actualSpeeds_dr_20G_KR2 57 2188 #define main0_actualSpeeds_dr_20G_CR2 58 2189 2190 /**************************************************************************** 2191 * Enums: main0_actualSpeedsMisc1 2192 */ 2193 #define main0_actualSpeedsMisc1_dr_2500BRCM_X1 16 2194 #define main0_actualSpeedsMisc1_dr_5000BRCM_X4 17 2195 #define main0_actualSpeedsMisc1_dr_6000BRCM_X4 18 2196 #define main0_actualSpeedsMisc1_dr_10GHiGig_X4 19 2197 #define main0_actualSpeedsMisc1_dr_10GBASE_CX4 20 2198 #define main0_actualSpeedsMisc1_dr_12GHiGig_X4 21 2199 #define main0_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 2200 #define main0_actualSpeedsMisc1_dr_13GHiGig_X4 23 2201 #define main0_actualSpeedsMisc1_dr_15GHiGig_X4 24 2202 #define main0_actualSpeedsMisc1_dr_16GHiGig_X4 25 2203 #define main0_actualSpeedsMisc1_dr_5000BRCM_X1 26 2204 #define main0_actualSpeedsMisc1_dr_6363BRCM_X1 27 2205 #define main0_actualSpeedsMisc1_dr_20GHiGig_X4 28 2206 #define main0_actualSpeedsMisc1_dr_21GHiGig_X4 29 2207 #define main0_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 2208 #define main0_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 2209 2210 /**************************************************************************** 2211 * Enums: main0_IndLaneModes 2212 */ 2213 #define main0_IndLaneModes_SWSDR_div2 0 2214 #define main0_IndLaneModes_SWSDR_div1 1 2215 #define main0_IndLaneModes_DWSDR_div2 2 2216 #define main0_IndLaneModes_DWSDR_div1 3 2217 2218 /**************************************************************************** 2219 * Enums: main0_prbsSelect 2220 */ 2221 #define main0_prbsSelect_prbs7 0 2222 #define main0_prbsSelect_prbs15 1 2223 #define main0_prbsSelect_prbs23 2 2224 #define main0_prbsSelect_prbs31 3 2225 2226 /**************************************************************************** 2227 * Enums: main0_vcoDivider 2228 */ 2229 #define main0_vcoDivider_div32 0 2230 #define main0_vcoDivider_div36 1 2231 #define main0_vcoDivider_div40 2 2232 #define main0_vcoDivider_div42 3 2233 #define main0_vcoDivider_div48 4 2234 #define main0_vcoDivider_div50 5 2235 #define main0_vcoDivider_div52 6 2236 #define main0_vcoDivider_div54 7 2237 #define main0_vcoDivider_div60 8 2238 #define main0_vcoDivider_div64 9 2239 #define main0_vcoDivider_div66 10 2240 #define main0_vcoDivider_div68 11 2241 #define main0_vcoDivider_div70 12 2242 #define main0_vcoDivider_div80 13 2243 #define main0_vcoDivider_div92 14 2244 #define main0_vcoDivider_div100 15 2245 2246 /**************************************************************************** 2247 * Enums: main0_refClkSelect 2248 */ 2249 #define main0_refClkSelect_clk_25MHz 0 2250 #define main0_refClkSelect_clk_100MHz 1 2251 #define main0_refClkSelect_clk_125MHz 2 2252 #define main0_refClkSelect_clk_156p25MHz 3 2253 #define main0_refClkSelect_clk_187p5MHz 4 2254 #define main0_refClkSelect_clk_161p25Mhz 5 2255 #define main0_refClkSelect_clk_50Mhz 6 2256 #define main0_refClkSelect_clk_106p25Mhz 7 2257 2258 /**************************************************************************** 2259 * Enums: main0_aerMMDdevTypeSelect 2260 */ 2261 #define main0_aerMMDdevTypeSelect_combo_core 0 2262 #define main0_aerMMDdevTypeSelect_PMA_PMD 1 2263 #define main0_aerMMDdevTypeSelect_PCS 3 2264 #define main0_aerMMDdevTypeSelect_PHY 4 2265 #define main0_aerMMDdevTypeSelect_DTE 5 2266 #define main0_aerMMDdevTypeSelect_CL73_AN 7 2267 2268 /**************************************************************************** 2269 * Enums: main0_aerMMDportSelect 2270 */ 2271 #define main0_aerMMDportSelect_ln0 0 2272 #define main0_aerMMDportSelect_ln1 1 2273 #define main0_aerMMDportSelect_ln2 2 2274 #define main0_aerMMDportSelect_ln3 3 2275 #define main0_aerMMDportSelect_BCST_ln0_1_2_3 511 2276 #define main0_aerMMDportSelect_BCST_ln0_1 512 2277 #define main0_aerMMDportSelect_BCST_ln2_3 513 2278 2279 /**************************************************************************** 2280 * Enums: main0_firmwareModeSelect 2281 */ 2282 #define main0_firmwareModeSelect_DEFAULT 0 2283 #define main0_firmwareModeSelect_SFP_OPT_LR 1 2284 #define main0_firmwareModeSelect_SFP_DAC 2 2285 #define main0_firmwareModeSelect_XLAUI 3 2286 #define main0_firmwareModeSelect_LONG_CH_6G 4 2287 2288 /**************************************************************************** 2289 * Enums: main0_tempIdxSelect 2290 */ 2291 #define main0_tempIdxSelect_LTE__22p9C 15 2292 #define main0_tempIdxSelect_LTE__12p6C 14 2293 #define main0_tempIdxSelect_LTE__3p0C 13 2294 #define main0_tempIdxSelect_LTE_6p7C 12 2295 #define main0_tempIdxSelect_LTE_16p4C 11 2296 #define main0_tempIdxSelect_LTE_26p6C 10 2297 #define main0_tempIdxSelect_LTE_36p3C 9 2298 #define main0_tempIdxSelect_LTE_46p0C 8 2299 #define main0_tempIdxSelect_LTE_56p2C 7 2300 #define main0_tempIdxSelect_LTE_65p9C 6 2301 #define main0_tempIdxSelect_LTE_75p6C 5 2302 #define main0_tempIdxSelect_LTE_85p3C 4 2303 #define main0_tempIdxSelect_LTE_95p5C 3 2304 #define main0_tempIdxSelect_LTE_105p2C 2 2305 #define main0_tempIdxSelect_LTE_114p9C 1 2306 #define main0_tempIdxSelect_LTE_125p1C 0 2307 2308 /**************************************************************************** 2309 * Enums: main0_port_mode 2310 */ 2311 #define main0_port_mode_QUAD_PORT 0 2312 #define main0_port_mode_TRI_1_PORT 1 2313 #define main0_port_mode_TRI_2_PORT 2 2314 #define main0_port_mode_DUAL_PORT 3 2315 #define main0_port_mode_SINGLE_PORT 4 2316 2317 /**************************************************************************** 2318 * Enums: main0_rev_letter_enum 2319 */ 2320 #define main0_rev_letter_enum_REV_A 0 2321 #define main0_rev_letter_enum_REV_B 1 2322 #define main0_rev_letter_enum_REV_C 2 2323 #define main0_rev_letter_enum_REV_D 3 2324 2325 /**************************************************************************** 2326 * Enums: main0_rev_number_enum 2327 */ 2328 #define main0_rev_number_enum_REV_0 0 2329 #define main0_rev_number_enum_REV_1 1 2330 #define main0_rev_number_enum_REV_2 2 2331 #define main0_rev_number_enum_REV_3 3 2332 #define main0_rev_number_enum_REV_4 4 2333 #define main0_rev_number_enum_REV_5 5 2334 #define main0_rev_number_enum_REV_6 6 2335 #define main0_rev_number_enum_REV_7 7 2336 2337 /**************************************************************************** 2338 * Enums: main0_bonding_enum 2339 */ 2340 #define main0_bonding_enum_WIRE_BOND 0 2341 #define main0_bonding_enum_FLIP_CHIP 1 2342 2343 /**************************************************************************** 2344 * Enums: main0_tech_process 2345 */ 2346 #define main0_tech_process_PROCESS_90NM 0 2347 #define main0_tech_process_PROCESS_65NM 1 2348 #define main0_tech_process_PROCESS_40NM 2 2349 #define main0_tech_process_PROCESS_28NM 3 2350 #define main0_tech_process_PROCESS_16NM 4 2351 2352 /**************************************************************************** 2353 * Enums: main0_model_num 2354 */ 2355 #define main0_model_num_SERDES_CL73 0 2356 #define main0_model_num_XGXS_16G 1 2357 #define main0_model_num_HYPERCORE 2 2358 #define main0_model_num_HYPERLITE 3 2359 #define main0_model_num_PCIE_G2_PIPE 4 2360 #define main0_model_num_SERDES_1p25GBd 5 2361 #define main0_model_num_SATA2 6 2362 #define main0_model_num_QSGMII 7 2363 #define main0_model_num_XGXS10G 8 2364 #define main0_model_num_WARPCORE 9 2365 #define main0_model_num_XFICORE 10 2366 #define main0_model_num_RXFI 11 2367 #define main0_model_num_WARPLITE 12 2368 #define main0_model_num_PENTACORE 13 2369 #define main0_model_num_ESM 14 2370 #define main0_model_num_QUAD_SGMII 15 2371 #define main0_model_num_WARPCORE_3 16 2372 #define main0_model_num_TSC 17 2373 #define main0_model_num_TSC4E 18 2374 #define main0_model_num_TSC12E 19 2375 #define main0_model_num_TSC4F 20 2376 #define main0_model_num_TSC4F_GEN2 21 2377 #define main0_model_num_XGXS_CL73_90NM 29 2378 #define main0_model_num_SERDES_CL73_90NM 30 2379 #define main0_model_num_WARPCORE3 32 2380 #define main0_model_num_WARPCORE4_TSC 33 2381 #define main0_model_num_RXAUI 34 2382 2383 /**************************************************************************** 2384 * Enums: main0_payload 2385 */ 2386 #define main0_payload_REPEAT_2_BYTES 0 2387 #define main0_payload_RAMPING 1 2388 #define main0_payload_CL48_CRPAT 2 2389 #define main0_payload_CL48_CJPAT 3 2390 #define main0_payload_CL36_LONG_CRPAT 4 2391 #define main0_payload_CL36_SHORT_CRPAT 5 2392 2393 /**************************************************************************** 2394 * Enums: main0_sc 2395 */ 2396 #define main0_sc_S_10G_CR1 0 2397 #define main0_sc_S_10G_KR1 1 2398 #define main0_sc_S_10G_X1 2 2399 #define main0_sc_S_10G_HG2_CR1 4 2400 #define main0_sc_S_10G_HG2_KR1 5 2401 #define main0_sc_S_10G_HG2_X1 6 2402 #define main0_sc_S_20G_CR1 8 2403 #define main0_sc_S_20G_KR1 9 2404 #define main0_sc_S_20G_X1 10 2405 #define main0_sc_S_20G_HG2_CR1 12 2406 #define main0_sc_S_20G_HG2_KR1 13 2407 #define main0_sc_S_20G_HG2_X1 14 2408 #define main0_sc_S_25G_CR1 16 2409 #define main0_sc_S_25G_KR1 17 2410 #define main0_sc_S_25G_X1 18 2411 #define main0_sc_S_25G_HG2_CR1 20 2412 #define main0_sc_S_25G_HG2_KR1 21 2413 #define main0_sc_S_25G_HG2_X1 22 2414 #define main0_sc_S_20G_CR2 24 2415 #define main0_sc_S_20G_KR2 25 2416 #define main0_sc_S_20G_X2 26 2417 #define main0_sc_S_20G_HG2_CR2 28 2418 #define main0_sc_S_20G_HG2_KR2 29 2419 #define main0_sc_S_20G_HG2_X2 30 2420 #define main0_sc_S_40G_CR2 32 2421 #define main0_sc_S_40G_KR2 33 2422 #define main0_sc_S_40G_X2 34 2423 #define main0_sc_S_40G_HG2_CR2 36 2424 #define main0_sc_S_40G_HG2_KR2 37 2425 #define main0_sc_S_40G_HG2_X2 38 2426 #define main0_sc_S_40G_CR4 40 2427 #define main0_sc_S_40G_KR4 41 2428 #define main0_sc_S_40G_X4 42 2429 #define main0_sc_S_40G_HG2_CR4 44 2430 #define main0_sc_S_40G_HG2_KR4 45 2431 #define main0_sc_S_40G_HG2_X4 46 2432 #define main0_sc_S_50G_CR2 48 2433 #define main0_sc_S_50G_KR2 49 2434 #define main0_sc_S_50G_X2 50 2435 #define main0_sc_S_50G_HG2_CR2 52 2436 #define main0_sc_S_50G_HG2_KR2 53 2437 #define main0_sc_S_50G_HG2_X2 54 2438 #define main0_sc_S_50G_CR4 56 2439 #define main0_sc_S_50G_KR4 57 2440 #define main0_sc_S_50G_X4 58 2441 #define main0_sc_S_50G_HG2_CR4 60 2442 #define main0_sc_S_50G_HG2_KR4 61 2443 #define main0_sc_S_50G_HG2_X4 62 2444 #define main0_sc_S_100G_CR4 64 2445 #define main0_sc_S_100G_KR4 65 2446 #define main0_sc_S_100G_X4 66 2447 #define main0_sc_S_100G_HG2_CR4 68 2448 #define main0_sc_S_100G_HG2_KR4 69 2449 #define main0_sc_S_100G_HG2_X4 70 2450 #define main0_sc_S_CL73_20GVCO 72 2451 #define main0_sc_S_CL73_25GVCO 80 2452 #define main0_sc_S_CL36_20GVCO 88 2453 #define main0_sc_S_CL36_25GVCO 96 2454 #define main0_sc_S_25G_CR_IEEE 112 2455 #define main0_sc_S_25G_CRS_IEEE 113 2456 #define main0_sc_S_25G_KR_IEEE 114 2457 #define main0_sc_S_25G_KRS_IEEE 115 2458 2459 /**************************************************************************** 2460 * Enums: main0_t_fifo_modes 2461 */ 2462 #define main0_t_fifo_modes_T_FIFO_INSERT_NO_AM 0 2463 #define main0_t_fifo_modes_T_FIFO_INSERT_4_AM 1 2464 #define main0_t_fifo_modes_T_FIFO_INSERT_20_AM 2 2465 #define main0_t_fifo_modes_T_FIFO_INSERT_2_AM 3 2466 2467 /**************************************************************************** 2468 * Enums: main0_t_enc_modes 2469 */ 2470 #define main0_t_enc_modes_T_ENC_MODE_BYPASS 0 2471 #define main0_t_enc_modes_T_ENC_MODE_CL49 1 2472 #define main0_t_enc_modes_T_ENC_MODE_CL82 2 2473 2474 /**************************************************************************** 2475 * Enums: main0_btmx_mode 2476 */ 2477 #define main0_btmx_mode_BS_BTMX_MODE_1to1 0 2478 #define main0_btmx_mode_BS_BTMX_MODE_2to1 1 2479 #define main0_btmx_mode_BS_BTMX_MODE_5to1 2 2480 2481 /**************************************************************************** 2482 * Enums: main0_t_type_cl82 2483 */ 2484 #define main0_t_type_cl82_T_TYPE_B1 5 2485 #define main0_t_type_cl82_T_TYPE_C 4 2486 #define main0_t_type_cl82_T_TYPE_S 3 2487 #define main0_t_type_cl82_T_TYPE_T 2 2488 #define main0_t_type_cl82_T_TYPE_D 1 2489 #define main0_t_type_cl82_T_TYPE_E 0 2490 2491 /**************************************************************************** 2492 * Enums: main0_txsm_state_cl82 2493 */ 2494 #define main0_txsm_state_cl82_TX_HIG_END 6 2495 #define main0_txsm_state_cl82_TX_HIG_START 5 2496 #define main0_txsm_state_cl82_TX_E 4 2497 #define main0_txsm_state_cl82_TX_T 3 2498 #define main0_txsm_state_cl82_TX_D 2 2499 #define main0_txsm_state_cl82_TX_C 1 2500 #define main0_txsm_state_cl82_TX_INIT 0 2501 2502 /**************************************************************************** 2503 * Enums: main0_ltxsm_state_cl82 2504 */ 2505 #define main0_ltxsm_state_cl82_TX_HIG_END 64 2506 #define main0_ltxsm_state_cl82_TX_HIG_START 32 2507 #define main0_ltxsm_state_cl82_TX_E 16 2508 #define main0_ltxsm_state_cl82_TX_T 8 2509 #define main0_ltxsm_state_cl82_TX_D 4 2510 #define main0_ltxsm_state_cl82_TX_C 2 2511 #define main0_ltxsm_state_cl82_TX_INIT 1 2512 2513 /**************************************************************************** 2514 * Enums: main0_r_type_coded_cl82 2515 */ 2516 #define main0_r_type_coded_cl82_R_TYPE_B1 32 2517 #define main0_r_type_coded_cl82_R_TYPE_C 16 2518 #define main0_r_type_coded_cl82_R_TYPE_S 8 2519 #define main0_r_type_coded_cl82_R_TYPE_T 4 2520 #define main0_r_type_coded_cl82_R_TYPE_D 2 2521 #define main0_r_type_coded_cl82_R_TYPE_E 1 2522 2523 /**************************************************************************** 2524 * Enums: main0_rxsm_state_cl82 2525 */ 2526 #define main0_rxsm_state_cl82_RX_HIG_END 64 2527 #define main0_rxsm_state_cl82_RX_HIG_START 32 2528 #define main0_rxsm_state_cl82_RX_E 16 2529 #define main0_rxsm_state_cl82_RX_T 8 2530 #define main0_rxsm_state_cl82_RX_D 4 2531 #define main0_rxsm_state_cl82_RX_C 2 2532 #define main0_rxsm_state_cl82_RX_INIT 1 2533 2534 /**************************************************************************** 2535 * Enums: main0_deskew_state 2536 */ 2537 #define main0_deskew_state_ALIGN_ACQUIRED 2 2538 #define main0_deskew_state_LOSS_OF_ALIGNMENT 1 2539 2540 /**************************************************************************** 2541 * Enums: main0_os_mode_enum 2542 */ 2543 #define main0_os_mode_enum_OS_MODE_1 0 2544 #define main0_os_mode_enum_OS_MODE_2 1 2545 #define main0_os_mode_enum_OS_MODE_4 2 2546 #define main0_os_mode_enum_OS_MODE_16p5 8 2547 #define main0_os_mode_enum_OS_MODE_20p625 12 2548 2549 /**************************************************************************** 2550 * Enums: main0_scr_modes 2551 */ 2552 #define main0_scr_modes_T_SCR_MODE_BYPASS 0 2553 #define main0_scr_modes_T_SCR_MODE_CL49 1 2554 #define main0_scr_modes_T_SCR_MODE_40G_2_LANE 2 2555 #define main0_scr_modes_T_SCR_MODE_100G 3 2556 #define main0_scr_modes_T_SCR_MODE_20G 4 2557 #define main0_scr_modes_T_SCR_MODE_40G_4_LANE 5 2558 2559 /**************************************************************************** 2560 * Enums: main0_descr_modes 2561 */ 2562 #define main0_descr_modes_R_DESCR_MODE_BYPASS 0 2563 #define main0_descr_modes_R_DESCR_MODE_CL49 1 2564 #define main0_descr_modes_R_DESCR_MODE_CL82 2 2565 2566 /**************************************************************************** 2567 * Enums: main0_r_dec_tl_mode 2568 */ 2569 #define main0_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 2570 #define main0_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 2571 #define main0_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 2572 2573 /**************************************************************************** 2574 * Enums: main0_r_dec_fsm_mode 2575 */ 2576 #define main0_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 2577 #define main0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 2578 #define main0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 2579 2580 /**************************************************************************** 2581 * Enums: main0_r_deskew_mode 2582 */ 2583 #define main0_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 2584 #define main0_r_deskew_mode_R_DESKEW_MODE_20G 1 2585 #define main0_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 2586 #define main0_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 2587 #define main0_r_deskew_mode_R_DESKEW_MODE_100G 4 2588 #define main0_r_deskew_mode_R_DESKEW_MODE_CL49 5 2589 #define main0_r_deskew_mode_R_DESKEW_MODE_CL91_QUAD 6 2590 #define main0_r_deskew_mode_R_DESKEW_MODE_CL91_SINGLE_BRCM 7 2591 #define main0_r_deskew_mode_R_DESKEW_MODE_CL91_DUAL_BRCM 8 2592 #define main0_r_deskew_mode_R_DESKEW_MODE_CL91_FC 9 2593 2594 /**************************************************************************** 2595 * Enums: main0_bs_dist_modes 2596 */ 2597 #define main0_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 2598 #define main0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 2599 #define main0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 2600 #define main0_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 2601 2602 /**************************************************************************** 2603 * Enums: main0_cl49_t_type 2604 */ 2605 #define main0_cl49_t_type_BAD_T_TYPE 15 2606 #define main0_cl49_t_type_T_TYPE_B0 11 2607 #define main0_cl49_t_type_T_TYPE_OB 10 2608 #define main0_cl49_t_type_T_TYPE_B1 9 2609 #define main0_cl49_t_type_T_TYPE_DB 8 2610 #define main0_cl49_t_type_T_TYPE_FC 7 2611 #define main0_cl49_t_type_T_TYPE_TB 6 2612 #define main0_cl49_t_type_T_TYPE_LI 5 2613 #define main0_cl49_t_type_T_TYPE_C 4 2614 #define main0_cl49_t_type_T_TYPE_S 3 2615 #define main0_cl49_t_type_T_TYPE_T 2 2616 #define main0_cl49_t_type_T_TYPE_D 1 2617 #define main0_cl49_t_type_T_TYPE_E 0 2618 2619 /**************************************************************************** 2620 * Enums: main0_cl49_txsm_states 2621 */ 2622 #define main0_cl49_txsm_states_TX_HIG_END 7 2623 #define main0_cl49_txsm_states_TX_HIG_START 6 2624 #define main0_cl49_txsm_states_TX_LI 5 2625 #define main0_cl49_txsm_states_TX_E 4 2626 #define main0_cl49_txsm_states_TX_T 3 2627 #define main0_cl49_txsm_states_TX_D 2 2628 #define main0_cl49_txsm_states_TX_C 1 2629 #define main0_cl49_txsm_states_TX_INIT 0 2630 2631 /**************************************************************************** 2632 * Enums: main0_cl49_ltxsm_states 2633 */ 2634 #define main0_cl49_ltxsm_states_TX_HIG_END 128 2635 #define main0_cl49_ltxsm_states_TX_HIG_START 64 2636 #define main0_cl49_ltxsm_states_TX_LI 32 2637 #define main0_cl49_ltxsm_states_TX_E 16 2638 #define main0_cl49_ltxsm_states_TX_T 8 2639 #define main0_cl49_ltxsm_states_TX_D 4 2640 #define main0_cl49_ltxsm_states_TX_C 2 2641 #define main0_cl49_ltxsm_states_TX_INIT 1 2642 2643 /**************************************************************************** 2644 * Enums: main0_burst_error_mode 2645 */ 2646 #define main0_burst_error_mode_BURST_ERROR_11_BITS 0 2647 #define main0_burst_error_mode_BURST_ERROR_16_BITS 1 2648 #define main0_burst_error_mode_BURST_ERROR_17_BITS 2 2649 #define main0_burst_error_mode_BURST_ERROR_18_BITS 3 2650 #define main0_burst_error_mode_BURST_ERROR_19_BITS 4 2651 #define main0_burst_error_mode_BURST_ERROR_20_BITS 5 2652 #define main0_burst_error_mode_BURST_ERROR_21_BITS 6 2653 #define main0_burst_error_mode_BURST_ERROR_22_BITS 7 2654 #define main0_burst_error_mode_BURST_ERROR_23_BITS 8 2655 #define main0_burst_error_mode_BURST_ERROR_24_BITS 9 2656 #define main0_burst_error_mode_BURST_ERROR_25_BITS 10 2657 #define main0_burst_error_mode_BURST_ERROR_26_BITS 11 2658 #define main0_burst_error_mode_BURST_ERROR_27_BITS 12 2659 #define main0_burst_error_mode_BURST_ERROR_28_BITS 13 2660 #define main0_burst_error_mode_BURST_ERROR_29_BITS 14 2661 #define main0_burst_error_mode_BURST_ERROR_30_BITS 15 2662 #define main0_burst_error_mode_BURST_ERROR_31_BITS 16 2663 #define main0_burst_error_mode_BURST_ERROR_32_BITS 17 2664 #define main0_burst_error_mode_BURST_ERROR_33_BITS 18 2665 #define main0_burst_error_mode_BURST_ERROR_34_BITS 19 2666 #define main0_burst_error_mode_BURST_ERROR_35_BITS 20 2667 #define main0_burst_error_mode_BURST_ERROR_36_BITS 21 2668 #define main0_burst_error_mode_BURST_ERROR_37_BITS 22 2669 #define main0_burst_error_mode_BURST_ERROR_38_BITS 23 2670 #define main0_burst_error_mode_BURST_ERROR_39_BITS 24 2671 #define main0_burst_error_mode_BURST_ERROR_40_BITS 25 2672 #define main0_burst_error_mode_BURST_ERROR_41_BITS 26 2673 2674 /**************************************************************************** 2675 * Enums: main0_bermon_state 2676 */ 2677 #define main0_bermon_state_HI_BER 4 2678 #define main0_bermon_state_GOOD_BER 3 2679 #define main0_bermon_state_BER_TEST_SH 2 2680 #define main0_bermon_state_START_TIMER 1 2681 #define main0_bermon_state_BER_MT_INIT 0 2682 2683 /**************************************************************************** 2684 * Enums: main0_rxsm_state_cl49 2685 */ 2686 #define main0_rxsm_state_cl49_RX_HIG_END 128 2687 #define main0_rxsm_state_cl49_RX_HIG_START 64 2688 #define main0_rxsm_state_cl49_RX_LI 32 2689 #define main0_rxsm_state_cl49_RX_E 16 2690 #define main0_rxsm_state_cl49_RX_T 8 2691 #define main0_rxsm_state_cl49_RX_D 4 2692 #define main0_rxsm_state_cl49_RX_C 2 2693 #define main0_rxsm_state_cl49_RX_INIT 1 2694 2695 /**************************************************************************** 2696 * Enums: main0_r_type 2697 */ 2698 #define main0_r_type_BAD_R_TYPE 15 2699 #define main0_r_type_R_TYPE_B0 11 2700 #define main0_r_type_R_TYPE_OB 10 2701 #define main0_r_type_R_TYPE_B1 9 2702 #define main0_r_type_R_TYPE_DB 8 2703 #define main0_r_type_R_TYPE_FC 7 2704 #define main0_r_type_R_TYPE_TB 6 2705 #define main0_r_type_R_TYPE_LI 5 2706 #define main0_r_type_R_TYPE_C 4 2707 #define main0_r_type_R_TYPE_S 3 2708 #define main0_r_type_R_TYPE_T 2 2709 #define main0_r_type_R_TYPE_D 1 2710 #define main0_r_type_R_TYPE_E 0 2711 2712 /**************************************************************************** 2713 * Enums: main0_am_lock_state 2714 */ 2715 #define main0_am_lock_state_INVALID_AM 512 2716 #define main0_am_lock_state_GOOD_AM 256 2717 #define main0_am_lock_state_COMP_AM 128 2718 #define main0_am_lock_state_TIMER_2 64 2719 #define main0_am_lock_state_AM_2_GOOD 32 2720 #define main0_am_lock_state_COMP_2ND 16 2721 #define main0_am_lock_state_TIMER_1 8 2722 #define main0_am_lock_state_FIND_1ST 4 2723 #define main0_am_lock_state_AM_RESET_CNT 2 2724 #define main0_am_lock_state_AM_LOCK_INIT 1 2725 2726 /**************************************************************************** 2727 * Enums: main0_msg_selector 2728 */ 2729 #define main0_msg_selector_RESERVED 0 2730 #define main0_msg_selector_VALUE_802p3 1 2731 #define main0_msg_selector_VALUE_802p9 2 2732 #define main0_msg_selector_VALUE_802p5 3 2733 #define main0_msg_selector_VALUE_1394 4 2734 2735 /**************************************************************************** 2736 * Enums: main0_synce_enum 2737 */ 2738 #define main0_synce_enum_SYNCE_NO_DIV 0 2739 #define main0_synce_enum_SYNCE_DIV_7 1 2740 #define main0_synce_enum_SYNCE_DIV_11 2 2741 2742 /**************************************************************************** 2743 * Enums: main0_synce_enum_stage0 2744 */ 2745 #define main0_synce_enum_stage0_SYNCE_NO_DIV 0 2746 #define main0_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 2747 #define main0_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 2748 2749 /**************************************************************************** 2750 * Enums: main0_cl91_sync_state 2751 */ 2752 #define main0_cl91_sync_state_FIND_1ST 0 2753 #define main0_cl91_sync_state_COUNT_NEXT 1 2754 #define main0_cl91_sync_state_COMP_2ND 2 2755 #define main0_cl91_sync_state_TWO_GOOD 3 2756 2757 /**************************************************************************** 2758 * Enums: main0_cl91_algn_state 2759 */ 2760 #define main0_cl91_algn_state_LOSS_OF_ALIGNMENT 0 2761 #define main0_cl91_algn_state_DESKEW 1 2762 #define main0_cl91_algn_state_DESKEW_FAIL 2 2763 #define main0_cl91_algn_state_ALIGN_ACQUIRED 3 2764 #define main0_cl91_algn_state_CW_GOOD 4 2765 #define main0_cl91_algn_state_CW_BAD 5 2766 #define main0_cl91_algn_state_THREE_BAD 6 2767 2768 /**************************************************************************** 2769 * Enums: main0_fec_sel_override 2770 */ 2771 #define main0_fec_sel_override_NO_OVERRIDE 0 2772 #define main0_fec_sel_override_NO_FEC 1 2773 #define main0_fec_sel_override_FEC_CL74 2 2774 #define main0_fec_sel_override_FEC_CL91 3 2775 2776 /**************************************************************************** 2777 * Enums: main0_cl91_blksync_mode 2778 */ 2779 #define main0_cl91_blksync_mode_R_BLKSYNC_NO_CL91_FEC 0 2780 #define main0_cl91_blksync_mode_R_BLKSYNC_CL91_QUAD_LANE_FEC 1 2781 #define main0_cl91_blksync_mode_R_BLKSYNC_CL91_DUAL_LANE_FEC 2 2782 #define main0_cl91_blksync_mode_R_BLKSYNC_CL91_SINGLE_LANE_FEC 3 2783 #define main0_cl91_blksync_mode_R_BLKSYNC_CL91_FC_FEC 4 2784 2785 /**************************************************************************** 2786 * Enums: main0_r_merge_mode 2787 */ 2788 #define main0_r_merge_mode_R_MERGE_MODE_BYPASS 0 2789 #define main0_r_merge_mode_R_MERGE_MODE_CL91_FC 1 2790 #define main0_r_merge_mode_R_MERGE_MODE_CL91_SINGLE_LANE 2 2791 #define main0_r_merge_mode_R_MERGE_MODE_CL91_DUAL_LANE 3 2792 #define main0_r_merge_mode_R_MERGE_MODE_CL91_QUAD_LANE 4 2793 2794 /**************************************************************************** 2795 * Enums: main0_r_tc_mode 2796 */ 2797 #define main0_r_tc_mode_R_TC_MODE_SINGLE 0 2798 #define main0_r_tc_mode_R_TC_MODE_DUAL 1 2799 #define main0_r_tc_mode_R_TC_MODE_QUAD 2 2800 2801 /**************************************************************************** 2802 * Enums: main0_r_tc_out_mode 2803 */ 2804 #define main0_r_tc_out_mode_R_TC_OUT_MODE_SINGLE 0 2805 #define main0_r_tc_out_mode_R_TC_OUT_MODE_DUAL 1 2806 #define main0_r_tc_out_mode_R_TC_OUT_MODE_QUAD 2 2807 2808 /**************************************************************************** 2809 * Enums: main0_cl91_fec_mode 2810 */ 2811 #define main0_cl91_fec_mode_NO_CL91_FEC 0 2812 #define main0_cl91_fec_mode_CL91_SINGLE_LANE_FC 1 2813 #define main0_cl91_fec_mode_CL91_SINGLE_LANE_BRCM_PROP 2 2814 #define main0_cl91_fec_mode_CL91_DUAL_LANE_BRCM_PROP 3 2815 #define main0_cl91_fec_mode_CL91_QUAD_LANE 4 2816 #define main0_cl91_fec_mode_IEEE_25G_CL91_SINGLE_LANE 5 2817 2818 /**************************************************************************** 2819 * Enums: main0_am_spacing_mul 2820 */ 2821 #define main0_am_spacing_mul_AM_SPACING_MUL_2 0 2822 #define main0_am_spacing_mul_AM_SPACING_MUL_4 1 2823 #define main0_am_spacing_mul_AM_SPACING_MUL_5 2 2824 #define main0_am_spacing_mul_AM_SPACING_MUL_20 3 2825 2826 /**************************************************************************** 2827 * Enums: rx_x1_status0_cl36TxEEEStates_l 2828 */ 2829 #define rx_x1_status0_cl36TxEEEStates_l_TX_REFRESH 8 2830 #define rx_x1_status0_cl36TxEEEStates_l_TX_QUIET 4 2831 #define rx_x1_status0_cl36TxEEEStates_l_TX_SLEEP 2 2832 #define rx_x1_status0_cl36TxEEEStates_l_TX_ACTIVE 1 2833 2834 /**************************************************************************** 2835 * Enums: rx_x1_status0_cl36TxEEEStates_c 2836 */ 2837 #define rx_x1_status0_cl36TxEEEStates_c_TX_REFRESH 3 2838 #define rx_x1_status0_cl36TxEEEStates_c_TX_QUIET 2 2839 #define rx_x1_status0_cl36TxEEEStates_c_TX_SLEEP 1 2840 #define rx_x1_status0_cl36TxEEEStates_c_TX_ACTIVE 0 2841 2842 /**************************************************************************** 2843 * Enums: rx_x1_status0_cl49TxEEEStates_l 2844 */ 2845 #define rx_x1_status0_cl49TxEEEStates_l_SCR_RESET_2 64 2846 #define rx_x1_status0_cl49TxEEEStates_l_SCR_RESET_1 32 2847 #define rx_x1_status0_cl49TxEEEStates_l_TX_WAKE 16 2848 #define rx_x1_status0_cl49TxEEEStates_l_TX_REFRESH 8 2849 #define rx_x1_status0_cl49TxEEEStates_l_TX_QUIET 4 2850 #define rx_x1_status0_cl49TxEEEStates_l_TX_SLEEP 2 2851 #define rx_x1_status0_cl49TxEEEStates_l_TX_ACTIVE 1 2852 2853 /**************************************************************************** 2854 * Enums: rx_x1_status0_fec_req_enum 2855 */ 2856 #define rx_x1_status0_fec_req_enum_FEC_not_supported 0 2857 #define rx_x1_status0_fec_req_enum_FEC_supported_but_not_requested 1 2858 #define rx_x1_status0_fec_req_enum_invalid_setting 2 2859 #define rx_x1_status0_fec_req_enum_FEC_supported_and_requested 3 2860 2861 /**************************************************************************** 2862 * Enums: rx_x1_status0_cl73_pause_enum 2863 */ 2864 #define rx_x1_status0_cl73_pause_enum_No_PAUSE_ability 0 2865 #define rx_x1_status0_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 2866 #define rx_x1_status0_cl73_pause_enum_Symmetric_PAUSE_ability 1 2867 #define rx_x1_status0_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 2868 2869 /**************************************************************************** 2870 * Enums: rx_x1_status0_cl49TxEEEStates_c 2871 */ 2872 #define rx_x1_status0_cl49TxEEEStates_c_SCR_RESET_2 6 2873 #define rx_x1_status0_cl49TxEEEStates_c_SCR_RESET_1 5 2874 #define rx_x1_status0_cl49TxEEEStates_c_TX_WAKE 4 2875 #define rx_x1_status0_cl49TxEEEStates_c_TX_REFRESH 3 2876 #define rx_x1_status0_cl49TxEEEStates_c_TX_QUIET 2 2877 #define rx_x1_status0_cl49TxEEEStates_c_TX_SLEEP 1 2878 #define rx_x1_status0_cl49TxEEEStates_c_TX_ACTIVE 0 2879 2880 /**************************************************************************** 2881 * Enums: rx_x1_status0_cl36RxEEEStates_l 2882 */ 2883 #define rx_x1_status0_cl36RxEEEStates_l_RX_LINK_FAIL 32 2884 #define rx_x1_status0_cl36RxEEEStates_l_RX_WTF 16 2885 #define rx_x1_status0_cl36RxEEEStates_l_RX_WAKE 8 2886 #define rx_x1_status0_cl36RxEEEStates_l_RX_QUIET 4 2887 #define rx_x1_status0_cl36RxEEEStates_l_RX_SLEEP 2 2888 #define rx_x1_status0_cl36RxEEEStates_l_RX_ACTIVE 1 2889 2890 /**************************************************************************** 2891 * Enums: rx_x1_status0_cl36RxEEEStates_c 2892 */ 2893 #define rx_x1_status0_cl36RxEEEStates_c_RX_LINK_FAIL 5 2894 #define rx_x1_status0_cl36RxEEEStates_c_RX_WTF 4 2895 #define rx_x1_status0_cl36RxEEEStates_c_RX_WAKE 3 2896 #define rx_x1_status0_cl36RxEEEStates_c_RX_QUIET 2 2897 #define rx_x1_status0_cl36RxEEEStates_c_RX_SLEEP 1 2898 #define rx_x1_status0_cl36RxEEEStates_c_RX_ACTIVE 0 2899 2900 /**************************************************************************** 2901 * Enums: rx_x1_status0_cl49RxEEEStates_l 2902 */ 2903 #define rx_x1_status0_cl49RxEEEStates_l_RX_LINK_FAIL 32 2904 #define rx_x1_status0_cl49RxEEEStates_l_RX_WTF 16 2905 #define rx_x1_status0_cl49RxEEEStates_l_RX_WAKE 8 2906 #define rx_x1_status0_cl49RxEEEStates_l_RX_QUIET 4 2907 #define rx_x1_status0_cl49RxEEEStates_l_RX_SLEEP 2 2908 #define rx_x1_status0_cl49RxEEEStates_l_RX_ACTIVE 1 2909 2910 /**************************************************************************** 2911 * Enums: rx_x1_status0_cl49RxEEEStates_c 2912 */ 2913 #define rx_x1_status0_cl49RxEEEStates_c_RX_LINK_FAIL 5 2914 #define rx_x1_status0_cl49RxEEEStates_c_RX_WTF 4 2915 #define rx_x1_status0_cl49RxEEEStates_c_RX_WAKE 3 2916 #define rx_x1_status0_cl49RxEEEStates_c_RX_QUIET 2 2917 #define rx_x1_status0_cl49RxEEEStates_c_RX_SLEEP 1 2918 #define rx_x1_status0_cl49RxEEEStates_c_RX_ACTIVE 0 2919 2920 /**************************************************************************** 2921 * Enums: rx_x1_status0_cl48TxEEEStates_l 2922 */ 2923 #define rx_x1_status0_cl48TxEEEStates_l_TX_REFRESH 8 2924 #define rx_x1_status0_cl48TxEEEStates_l_TX_QUIET 4 2925 #define rx_x1_status0_cl48TxEEEStates_l_TX_SLEEP 2 2926 #define rx_x1_status0_cl48TxEEEStates_l_TX_ACTIVE 1 2927 2928 /**************************************************************************** 2929 * Enums: rx_x1_status0_cl48TxEEEStates_c 2930 */ 2931 #define rx_x1_status0_cl48TxEEEStates_c_TX_REFRESH 3 2932 #define rx_x1_status0_cl48TxEEEStates_c_TX_QUIET 2 2933 #define rx_x1_status0_cl48TxEEEStates_c_TX_SLEEP 1 2934 #define rx_x1_status0_cl48TxEEEStates_c_TX_ACTIVE 0 2935 2936 /**************************************************************************** 2937 * Enums: rx_x1_status0_cl48RxEEEStates_l 2938 */ 2939 #define rx_x1_status0_cl48RxEEEStates_l_RX_LINK_FAIL 32 2940 #define rx_x1_status0_cl48RxEEEStates_l_RX_WAKE 16 2941 #define rx_x1_status0_cl48RxEEEStates_l_RX_QUIET 8 2942 #define rx_x1_status0_cl48RxEEEStates_l_RX_DEACT 4 2943 #define rx_x1_status0_cl48RxEEEStates_l_RX_SLEEP 2 2944 #define rx_x1_status0_cl48RxEEEStates_l_RX_ACTIVE 1 2945 2946 /**************************************************************************** 2947 * Enums: rx_x1_status0_cl48RxEEEStates_c 2948 */ 2949 #define rx_x1_status0_cl48RxEEEStates_c_RX_LINK_FAIL 5 2950 #define rx_x1_status0_cl48RxEEEStates_c_RX_WAKE 4 2951 #define rx_x1_status0_cl48RxEEEStates_c_RX_QUIET 3 2952 #define rx_x1_status0_cl48RxEEEStates_c_RX_DEACT 2 2953 #define rx_x1_status0_cl48RxEEEStates_c_RX_SLEEP 1 2954 #define rx_x1_status0_cl48RxEEEStates_c_RX_ACTIVE 0 2955 2956 /**************************************************************************** 2957 * Enums: rx_x1_status0_IQP_Options 2958 */ 2959 #define rx_x1_status0_IQP_Options_i50uA 0 2960 #define rx_x1_status0_IQP_Options_i100uA 1 2961 #define rx_x1_status0_IQP_Options_i150uA 2 2962 #define rx_x1_status0_IQP_Options_i200uA 3 2963 #define rx_x1_status0_IQP_Options_i250uA 4 2964 #define rx_x1_status0_IQP_Options_i300uA 5 2965 #define rx_x1_status0_IQP_Options_i350uA 6 2966 #define rx_x1_status0_IQP_Options_i400uA 7 2967 #define rx_x1_status0_IQP_Options_i450uA 8 2968 #define rx_x1_status0_IQP_Options_i500uA 9 2969 #define rx_x1_status0_IQP_Options_i550uA 10 2970 #define rx_x1_status0_IQP_Options_i600uA 11 2971 #define rx_x1_status0_IQP_Options_i650uA 12 2972 #define rx_x1_status0_IQP_Options_i700uA 13 2973 #define rx_x1_status0_IQP_Options_i750uA 14 2974 #define rx_x1_status0_IQP_Options_i800uA 15 2975 2976 /**************************************************************************** 2977 * Enums: rx_x1_status0_IDriver_Options 2978 */ 2979 #define rx_x1_status0_IDriver_Options_v680mV 0 2980 #define rx_x1_status0_IDriver_Options_v730mV 1 2981 #define rx_x1_status0_IDriver_Options_v780mV 2 2982 #define rx_x1_status0_IDriver_Options_v830mV 3 2983 #define rx_x1_status0_IDriver_Options_v880mV 4 2984 #define rx_x1_status0_IDriver_Options_v930mV 5 2985 #define rx_x1_status0_IDriver_Options_v980mV 6 2986 #define rx_x1_status0_IDriver_Options_v1010mV 7 2987 #define rx_x1_status0_IDriver_Options_v1040mV 8 2988 #define rx_x1_status0_IDriver_Options_v1060mV 9 2989 #define rx_x1_status0_IDriver_Options_v1070mV 10 2990 #define rx_x1_status0_IDriver_Options_v1080mV 11 2991 #define rx_x1_status0_IDriver_Options_v1085mV 12 2992 #define rx_x1_status0_IDriver_Options_v1090mV 13 2993 #define rx_x1_status0_IDriver_Options_v1095mV 14 2994 #define rx_x1_status0_IDriver_Options_v1100mV 15 2995 2996 /**************************************************************************** 2997 * Enums: rx_x1_status0_operationModes 2998 */ 2999 #define rx_x1_status0_operationModes_XGXS 0 3000 #define rx_x1_status0_operationModes_XGXG_nCC 1 3001 #define rx_x1_status0_operationModes_Indlane_OS8 4 3002 #define rx_x1_status0_operationModes_IndLane_OS5 5 3003 #define rx_x1_status0_operationModes_PCI 7 3004 #define rx_x1_status0_operationModes_XGXS_nLQ 8 3005 #define rx_x1_status0_operationModes_XGXS_nLQnCC 9 3006 #define rx_x1_status0_operationModes_PBypass 10 3007 #define rx_x1_status0_operationModes_PBypass_nDSK 11 3008 #define rx_x1_status0_operationModes_ComboCoreMode 12 3009 #define rx_x1_status0_operationModes_Clocks_off 15 3010 3011 /**************************************************************************** 3012 * Enums: rx_x1_status0_actualSpeeds 3013 */ 3014 #define rx_x1_status0_actualSpeeds_dr_10M 0 3015 #define rx_x1_status0_actualSpeeds_dr_100M 1 3016 #define rx_x1_status0_actualSpeeds_dr_1G 2 3017 #define rx_x1_status0_actualSpeeds_dr_2p5G 3 3018 #define rx_x1_status0_actualSpeeds_dr_5G_X4 4 3019 #define rx_x1_status0_actualSpeeds_dr_6G_X4 5 3020 #define rx_x1_status0_actualSpeeds_dr_10G_HiG 6 3021 #define rx_x1_status0_actualSpeeds_dr_10G_CX4 7 3022 #define rx_x1_status0_actualSpeeds_dr_12G_HiG 8 3023 #define rx_x1_status0_actualSpeeds_dr_12p5G_X4 9 3024 #define rx_x1_status0_actualSpeeds_dr_13G_X4 10 3025 #define rx_x1_status0_actualSpeeds_dr_15G_X4 11 3026 #define rx_x1_status0_actualSpeeds_dr_16G_X4 12 3027 #define rx_x1_status0_actualSpeeds_dr_1G_KX 13 3028 #define rx_x1_status0_actualSpeeds_dr_10G_KX4 14 3029 #define rx_x1_status0_actualSpeeds_dr_10G_KR 15 3030 #define rx_x1_status0_actualSpeeds_dr_5G 16 3031 #define rx_x1_status0_actualSpeeds_dr_6p4G 17 3032 #define rx_x1_status0_actualSpeeds_dr_20G_X4 18 3033 #define rx_x1_status0_actualSpeeds_dr_21G_X4 19 3034 #define rx_x1_status0_actualSpeeds_dr_25G_X4 20 3035 #define rx_x1_status0_actualSpeeds_dr_10G_HiG_DXGXS 21 3036 #define rx_x1_status0_actualSpeeds_dr_10G_DXGXS 22 3037 #define rx_x1_status0_actualSpeeds_dr_10p5G_HiG_DXGXS 23 3038 #define rx_x1_status0_actualSpeeds_dr_10p5G_DXGXS 24 3039 #define rx_x1_status0_actualSpeeds_dr_12p773G_HiG_DXGXS 25 3040 #define rx_x1_status0_actualSpeeds_dr_12p773G_DXGXS 26 3041 #define rx_x1_status0_actualSpeeds_dr_10G_XFI 27 3042 #define rx_x1_status0_actualSpeeds_dr_40G 28 3043 #define rx_x1_status0_actualSpeeds_dr_20G_HiG_DXGXS 29 3044 #define rx_x1_status0_actualSpeeds_dr_20G_DXGXS 30 3045 #define rx_x1_status0_actualSpeeds_dr_10G_SFI 31 3046 #define rx_x1_status0_actualSpeeds_dr_31p5G 32 3047 #define rx_x1_status0_actualSpeeds_dr_32p7G 33 3048 #define rx_x1_status0_actualSpeeds_dr_20G_SCR 34 3049 #define rx_x1_status0_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 3050 #define rx_x1_status0_actualSpeeds_dr_10G_DXGXS_SCR 36 3051 #define rx_x1_status0_actualSpeeds_dr_12G_R2 37 3052 #define rx_x1_status0_actualSpeeds_dr_10G_X2 38 3053 #define rx_x1_status0_actualSpeeds_dr_40G_KR4 39 3054 #define rx_x1_status0_actualSpeeds_dr_40G_CR4 40 3055 #define rx_x1_status0_actualSpeeds_dr_100G_CR10 41 3056 #define rx_x1_status0_actualSpeeds_dr_15p75G_DXGXS 44 3057 #define rx_x1_status0_actualSpeeds_dr_20G_KR2 57 3058 #define rx_x1_status0_actualSpeeds_dr_20G_CR2 58 3059 3060 /**************************************************************************** 3061 * Enums: rx_x1_status0_actualSpeedsMisc1 3062 */ 3063 #define rx_x1_status0_actualSpeedsMisc1_dr_2500BRCM_X1 16 3064 #define rx_x1_status0_actualSpeedsMisc1_dr_5000BRCM_X4 17 3065 #define rx_x1_status0_actualSpeedsMisc1_dr_6000BRCM_X4 18 3066 #define rx_x1_status0_actualSpeedsMisc1_dr_10GHiGig_X4 19 3067 #define rx_x1_status0_actualSpeedsMisc1_dr_10GBASE_CX4 20 3068 #define rx_x1_status0_actualSpeedsMisc1_dr_12GHiGig_X4 21 3069 #define rx_x1_status0_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 3070 #define rx_x1_status0_actualSpeedsMisc1_dr_13GHiGig_X4 23 3071 #define rx_x1_status0_actualSpeedsMisc1_dr_15GHiGig_X4 24 3072 #define rx_x1_status0_actualSpeedsMisc1_dr_16GHiGig_X4 25 3073 #define rx_x1_status0_actualSpeedsMisc1_dr_5000BRCM_X1 26 3074 #define rx_x1_status0_actualSpeedsMisc1_dr_6363BRCM_X1 27 3075 #define rx_x1_status0_actualSpeedsMisc1_dr_20GHiGig_X4 28 3076 #define rx_x1_status0_actualSpeedsMisc1_dr_21GHiGig_X4 29 3077 #define rx_x1_status0_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 3078 #define rx_x1_status0_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 3079 3080 /**************************************************************************** 3081 * Enums: rx_x1_status0_IndLaneModes 3082 */ 3083 #define rx_x1_status0_IndLaneModes_SWSDR_div2 0 3084 #define rx_x1_status0_IndLaneModes_SWSDR_div1 1 3085 #define rx_x1_status0_IndLaneModes_DWSDR_div2 2 3086 #define rx_x1_status0_IndLaneModes_DWSDR_div1 3 3087 3088 /**************************************************************************** 3089 * Enums: rx_x1_status0_prbsSelect 3090 */ 3091 #define rx_x1_status0_prbsSelect_prbs7 0 3092 #define rx_x1_status0_prbsSelect_prbs15 1 3093 #define rx_x1_status0_prbsSelect_prbs23 2 3094 #define rx_x1_status0_prbsSelect_prbs31 3 3095 3096 /**************************************************************************** 3097 * Enums: rx_x1_status0_vcoDivider 3098 */ 3099 #define rx_x1_status0_vcoDivider_div32 0 3100 #define rx_x1_status0_vcoDivider_div36 1 3101 #define rx_x1_status0_vcoDivider_div40 2 3102 #define rx_x1_status0_vcoDivider_div42 3 3103 #define rx_x1_status0_vcoDivider_div48 4 3104 #define rx_x1_status0_vcoDivider_div50 5 3105 #define rx_x1_status0_vcoDivider_div52 6 3106 #define rx_x1_status0_vcoDivider_div54 7 3107 #define rx_x1_status0_vcoDivider_div60 8 3108 #define rx_x1_status0_vcoDivider_div64 9 3109 #define rx_x1_status0_vcoDivider_div66 10 3110 #define rx_x1_status0_vcoDivider_div68 11 3111 #define rx_x1_status0_vcoDivider_div70 12 3112 #define rx_x1_status0_vcoDivider_div80 13 3113 #define rx_x1_status0_vcoDivider_div92 14 3114 #define rx_x1_status0_vcoDivider_div100 15 3115 3116 /**************************************************************************** 3117 * Enums: rx_x1_status0_refClkSelect 3118 */ 3119 #define rx_x1_status0_refClkSelect_clk_25MHz 0 3120 #define rx_x1_status0_refClkSelect_clk_100MHz 1 3121 #define rx_x1_status0_refClkSelect_clk_125MHz 2 3122 #define rx_x1_status0_refClkSelect_clk_156p25MHz 3 3123 #define rx_x1_status0_refClkSelect_clk_187p5MHz 4 3124 #define rx_x1_status0_refClkSelect_clk_161p25Mhz 5 3125 #define rx_x1_status0_refClkSelect_clk_50Mhz 6 3126 #define rx_x1_status0_refClkSelect_clk_106p25Mhz 7 3127 3128 /**************************************************************************** 3129 * Enums: rx_x1_status0_aerMMDdevTypeSelect 3130 */ 3131 #define rx_x1_status0_aerMMDdevTypeSelect_combo_core 0 3132 #define rx_x1_status0_aerMMDdevTypeSelect_PMA_PMD 1 3133 #define rx_x1_status0_aerMMDdevTypeSelect_PCS 3 3134 #define rx_x1_status0_aerMMDdevTypeSelect_PHY 4 3135 #define rx_x1_status0_aerMMDdevTypeSelect_DTE 5 3136 #define rx_x1_status0_aerMMDdevTypeSelect_CL73_AN 7 3137 3138 /**************************************************************************** 3139 * Enums: rx_x1_status0_aerMMDportSelect 3140 */ 3141 #define rx_x1_status0_aerMMDportSelect_ln0 0 3142 #define rx_x1_status0_aerMMDportSelect_ln1 1 3143 #define rx_x1_status0_aerMMDportSelect_ln2 2 3144 #define rx_x1_status0_aerMMDportSelect_ln3 3 3145 #define rx_x1_status0_aerMMDportSelect_BCST_ln0_1_2_3 511 3146 #define rx_x1_status0_aerMMDportSelect_BCST_ln0_1 512 3147 #define rx_x1_status0_aerMMDportSelect_BCST_ln2_3 513 3148 3149 /**************************************************************************** 3150 * Enums: rx_x1_status0_firmwareModeSelect 3151 */ 3152 #define rx_x1_status0_firmwareModeSelect_DEFAULT 0 3153 #define rx_x1_status0_firmwareModeSelect_SFP_OPT_LR 1 3154 #define rx_x1_status0_firmwareModeSelect_SFP_DAC 2 3155 #define rx_x1_status0_firmwareModeSelect_XLAUI 3 3156 #define rx_x1_status0_firmwareModeSelect_LONG_CH_6G 4 3157 3158 /**************************************************************************** 3159 * Enums: rx_x1_status0_tempIdxSelect 3160 */ 3161 #define rx_x1_status0_tempIdxSelect_LTE__22p9C 15 3162 #define rx_x1_status0_tempIdxSelect_LTE__12p6C 14 3163 #define rx_x1_status0_tempIdxSelect_LTE__3p0C 13 3164 #define rx_x1_status0_tempIdxSelect_LTE_6p7C 12 3165 #define rx_x1_status0_tempIdxSelect_LTE_16p4C 11 3166 #define rx_x1_status0_tempIdxSelect_LTE_26p6C 10 3167 #define rx_x1_status0_tempIdxSelect_LTE_36p3C 9 3168 #define rx_x1_status0_tempIdxSelect_LTE_46p0C 8 3169 #define rx_x1_status0_tempIdxSelect_LTE_56p2C 7 3170 #define rx_x1_status0_tempIdxSelect_LTE_65p9C 6 3171 #define rx_x1_status0_tempIdxSelect_LTE_75p6C 5 3172 #define rx_x1_status0_tempIdxSelect_LTE_85p3C 4 3173 #define rx_x1_status0_tempIdxSelect_LTE_95p5C 3 3174 #define rx_x1_status0_tempIdxSelect_LTE_105p2C 2 3175 #define rx_x1_status0_tempIdxSelect_LTE_114p9C 1 3176 #define rx_x1_status0_tempIdxSelect_LTE_125p1C 0 3177 3178 /**************************************************************************** 3179 * Enums: rx_x1_status0_port_mode 3180 */ 3181 #define rx_x1_status0_port_mode_QUAD_PORT 0 3182 #define rx_x1_status0_port_mode_TRI_1_PORT 1 3183 #define rx_x1_status0_port_mode_TRI_2_PORT 2 3184 #define rx_x1_status0_port_mode_DUAL_PORT 3 3185 #define rx_x1_status0_port_mode_SINGLE_PORT 4 3186 3187 /**************************************************************************** 3188 * Enums: rx_x1_status0_rev_letter_enum 3189 */ 3190 #define rx_x1_status0_rev_letter_enum_REV_A 0 3191 #define rx_x1_status0_rev_letter_enum_REV_B 1 3192 #define rx_x1_status0_rev_letter_enum_REV_C 2 3193 #define rx_x1_status0_rev_letter_enum_REV_D 3 3194 3195 /**************************************************************************** 3196 * Enums: rx_x1_status0_rev_number_enum 3197 */ 3198 #define rx_x1_status0_rev_number_enum_REV_0 0 3199 #define rx_x1_status0_rev_number_enum_REV_1 1 3200 #define rx_x1_status0_rev_number_enum_REV_2 2 3201 #define rx_x1_status0_rev_number_enum_REV_3 3 3202 #define rx_x1_status0_rev_number_enum_REV_4 4 3203 #define rx_x1_status0_rev_number_enum_REV_5 5 3204 #define rx_x1_status0_rev_number_enum_REV_6 6 3205 #define rx_x1_status0_rev_number_enum_REV_7 7 3206 3207 /**************************************************************************** 3208 * Enums: rx_x1_status0_bonding_enum 3209 */ 3210 #define rx_x1_status0_bonding_enum_WIRE_BOND 0 3211 #define rx_x1_status0_bonding_enum_FLIP_CHIP 1 3212 3213 /**************************************************************************** 3214 * Enums: rx_x1_status0_tech_process 3215 */ 3216 #define rx_x1_status0_tech_process_PROCESS_90NM 0 3217 #define rx_x1_status0_tech_process_PROCESS_65NM 1 3218 #define rx_x1_status0_tech_process_PROCESS_40NM 2 3219 #define rx_x1_status0_tech_process_PROCESS_28NM 3 3220 #define rx_x1_status0_tech_process_PROCESS_16NM 4 3221 3222 /**************************************************************************** 3223 * Enums: rx_x1_status0_model_num 3224 */ 3225 #define rx_x1_status0_model_num_SERDES_CL73 0 3226 #define rx_x1_status0_model_num_XGXS_16G 1 3227 #define rx_x1_status0_model_num_HYPERCORE 2 3228 #define rx_x1_status0_model_num_HYPERLITE 3 3229 #define rx_x1_status0_model_num_PCIE_G2_PIPE 4 3230 #define rx_x1_status0_model_num_SERDES_1p25GBd 5 3231 #define rx_x1_status0_model_num_SATA2 6 3232 #define rx_x1_status0_model_num_QSGMII 7 3233 #define rx_x1_status0_model_num_XGXS10G 8 3234 #define rx_x1_status0_model_num_WARPCORE 9 3235 #define rx_x1_status0_model_num_XFICORE 10 3236 #define rx_x1_status0_model_num_RXFI 11 3237 #define rx_x1_status0_model_num_WARPLITE 12 3238 #define rx_x1_status0_model_num_PENTACORE 13 3239 #define rx_x1_status0_model_num_ESM 14 3240 #define rx_x1_status0_model_num_QUAD_SGMII 15 3241 #define rx_x1_status0_model_num_WARPCORE_3 16 3242 #define rx_x1_status0_model_num_TSC 17 3243 #define rx_x1_status0_model_num_TSC4E 18 3244 #define rx_x1_status0_model_num_TSC12E 19 3245 #define rx_x1_status0_model_num_TSC4F 20 3246 #define rx_x1_status0_model_num_TSC4F_GEN2 21 3247 #define rx_x1_status0_model_num_XGXS_CL73_90NM 29 3248 #define rx_x1_status0_model_num_SERDES_CL73_90NM 30 3249 #define rx_x1_status0_model_num_WARPCORE3 32 3250 #define rx_x1_status0_model_num_WARPCORE4_TSC 33 3251 #define rx_x1_status0_model_num_RXAUI 34 3252 3253 /**************************************************************************** 3254 * Enums: rx_x1_status0_payload 3255 */ 3256 #define rx_x1_status0_payload_REPEAT_2_BYTES 0 3257 #define rx_x1_status0_payload_RAMPING 1 3258 #define rx_x1_status0_payload_CL48_CRPAT 2 3259 #define rx_x1_status0_payload_CL48_CJPAT 3 3260 #define rx_x1_status0_payload_CL36_LONG_CRPAT 4 3261 #define rx_x1_status0_payload_CL36_SHORT_CRPAT 5 3262 3263 /**************************************************************************** 3264 * Enums: rx_x1_status0_sc 3265 */ 3266 #define rx_x1_status0_sc_S_10G_CR1 0 3267 #define rx_x1_status0_sc_S_10G_KR1 1 3268 #define rx_x1_status0_sc_S_10G_X1 2 3269 #define rx_x1_status0_sc_S_10G_HG2_CR1 4 3270 #define rx_x1_status0_sc_S_10G_HG2_KR1 5 3271 #define rx_x1_status0_sc_S_10G_HG2_X1 6 3272 #define rx_x1_status0_sc_S_20G_CR1 8 3273 #define rx_x1_status0_sc_S_20G_KR1 9 3274 #define rx_x1_status0_sc_S_20G_X1 10 3275 #define rx_x1_status0_sc_S_20G_HG2_CR1 12 3276 #define rx_x1_status0_sc_S_20G_HG2_KR1 13 3277 #define rx_x1_status0_sc_S_20G_HG2_X1 14 3278 #define rx_x1_status0_sc_S_25G_CR1 16 3279 #define rx_x1_status0_sc_S_25G_KR1 17 3280 #define rx_x1_status0_sc_S_25G_X1 18 3281 #define rx_x1_status0_sc_S_25G_HG2_CR1 20 3282 #define rx_x1_status0_sc_S_25G_HG2_KR1 21 3283 #define rx_x1_status0_sc_S_25G_HG2_X1 22 3284 #define rx_x1_status0_sc_S_20G_CR2 24 3285 #define rx_x1_status0_sc_S_20G_KR2 25 3286 #define rx_x1_status0_sc_S_20G_X2 26 3287 #define rx_x1_status0_sc_S_20G_HG2_CR2 28 3288 #define rx_x1_status0_sc_S_20G_HG2_KR2 29 3289 #define rx_x1_status0_sc_S_20G_HG2_X2 30 3290 #define rx_x1_status0_sc_S_40G_CR2 32 3291 #define rx_x1_status0_sc_S_40G_KR2 33 3292 #define rx_x1_status0_sc_S_40G_X2 34 3293 #define rx_x1_status0_sc_S_40G_HG2_CR2 36 3294 #define rx_x1_status0_sc_S_40G_HG2_KR2 37 3295 #define rx_x1_status0_sc_S_40G_HG2_X2 38 3296 #define rx_x1_status0_sc_S_40G_CR4 40 3297 #define rx_x1_status0_sc_S_40G_KR4 41 3298 #define rx_x1_status0_sc_S_40G_X4 42 3299 #define rx_x1_status0_sc_S_40G_HG2_CR4 44 3300 #define rx_x1_status0_sc_S_40G_HG2_KR4 45 3301 #define rx_x1_status0_sc_S_40G_HG2_X4 46 3302 #define rx_x1_status0_sc_S_50G_CR2 48 3303 #define rx_x1_status0_sc_S_50G_KR2 49 3304 #define rx_x1_status0_sc_S_50G_X2 50 3305 #define rx_x1_status0_sc_S_50G_HG2_CR2 52 3306 #define rx_x1_status0_sc_S_50G_HG2_KR2 53 3307 #define rx_x1_status0_sc_S_50G_HG2_X2 54 3308 #define rx_x1_status0_sc_S_50G_CR4 56 3309 #define rx_x1_status0_sc_S_50G_KR4 57 3310 #define rx_x1_status0_sc_S_50G_X4 58 3311 #define rx_x1_status0_sc_S_50G_HG2_CR4 60 3312 #define rx_x1_status0_sc_S_50G_HG2_KR4 61 3313 #define rx_x1_status0_sc_S_50G_HG2_X4 62 3314 #define rx_x1_status0_sc_S_100G_CR4 64 3315 #define rx_x1_status0_sc_S_100G_KR4 65 3316 #define rx_x1_status0_sc_S_100G_X4 66 3317 #define rx_x1_status0_sc_S_100G_HG2_CR4 68 3318 #define rx_x1_status0_sc_S_100G_HG2_KR4 69 3319 #define rx_x1_status0_sc_S_100G_HG2_X4 70 3320 #define rx_x1_status0_sc_S_CL73_20GVCO 72 3321 #define rx_x1_status0_sc_S_CL73_25GVCO 80 3322 #define rx_x1_status0_sc_S_CL36_20GVCO 88 3323 #define rx_x1_status0_sc_S_CL36_25GVCO 96 3324 #define rx_x1_status0_sc_S_25G_CR_IEEE 112 3325 #define rx_x1_status0_sc_S_25G_CRS_IEEE 113 3326 #define rx_x1_status0_sc_S_25G_KR_IEEE 114 3327 #define rx_x1_status0_sc_S_25G_KRS_IEEE 115 3328 3329 /**************************************************************************** 3330 * Enums: rx_x1_status0_t_fifo_modes 3331 */ 3332 #define rx_x1_status0_t_fifo_modes_T_FIFO_INSERT_NO_AM 0 3333 #define rx_x1_status0_t_fifo_modes_T_FIFO_INSERT_4_AM 1 3334 #define rx_x1_status0_t_fifo_modes_T_FIFO_INSERT_20_AM 2 3335 #define rx_x1_status0_t_fifo_modes_T_FIFO_INSERT_2_AM 3 3336 3337 /**************************************************************************** 3338 * Enums: rx_x1_status0_t_enc_modes 3339 */ 3340 #define rx_x1_status0_t_enc_modes_T_ENC_MODE_BYPASS 0 3341 #define rx_x1_status0_t_enc_modes_T_ENC_MODE_CL49 1 3342 #define rx_x1_status0_t_enc_modes_T_ENC_MODE_CL82 2 3343 3344 /**************************************************************************** 3345 * Enums: rx_x1_status0_btmx_mode 3346 */ 3347 #define rx_x1_status0_btmx_mode_BS_BTMX_MODE_1to1 0 3348 #define rx_x1_status0_btmx_mode_BS_BTMX_MODE_2to1 1 3349 #define rx_x1_status0_btmx_mode_BS_BTMX_MODE_5to1 2 3350 3351 /**************************************************************************** 3352 * Enums: rx_x1_status0_t_type_cl82 3353 */ 3354 #define rx_x1_status0_t_type_cl82_T_TYPE_B1 5 3355 #define rx_x1_status0_t_type_cl82_T_TYPE_C 4 3356 #define rx_x1_status0_t_type_cl82_T_TYPE_S 3 3357 #define rx_x1_status0_t_type_cl82_T_TYPE_T 2 3358 #define rx_x1_status0_t_type_cl82_T_TYPE_D 1 3359 #define rx_x1_status0_t_type_cl82_T_TYPE_E 0 3360 3361 /**************************************************************************** 3362 * Enums: rx_x1_status0_txsm_state_cl82 3363 */ 3364 #define rx_x1_status0_txsm_state_cl82_TX_HIG_END 6 3365 #define rx_x1_status0_txsm_state_cl82_TX_HIG_START 5 3366 #define rx_x1_status0_txsm_state_cl82_TX_E 4 3367 #define rx_x1_status0_txsm_state_cl82_TX_T 3 3368 #define rx_x1_status0_txsm_state_cl82_TX_D 2 3369 #define rx_x1_status0_txsm_state_cl82_TX_C 1 3370 #define rx_x1_status0_txsm_state_cl82_TX_INIT 0 3371 3372 /**************************************************************************** 3373 * Enums: rx_x1_status0_ltxsm_state_cl82 3374 */ 3375 #define rx_x1_status0_ltxsm_state_cl82_TX_HIG_END 64 3376 #define rx_x1_status0_ltxsm_state_cl82_TX_HIG_START 32 3377 #define rx_x1_status0_ltxsm_state_cl82_TX_E 16 3378 #define rx_x1_status0_ltxsm_state_cl82_TX_T 8 3379 #define rx_x1_status0_ltxsm_state_cl82_TX_D 4 3380 #define rx_x1_status0_ltxsm_state_cl82_TX_C 2 3381 #define rx_x1_status0_ltxsm_state_cl82_TX_INIT 1 3382 3383 /**************************************************************************** 3384 * Enums: rx_x1_status0_r_type_coded_cl82 3385 */ 3386 #define rx_x1_status0_r_type_coded_cl82_R_TYPE_B1 32 3387 #define rx_x1_status0_r_type_coded_cl82_R_TYPE_C 16 3388 #define rx_x1_status0_r_type_coded_cl82_R_TYPE_S 8 3389 #define rx_x1_status0_r_type_coded_cl82_R_TYPE_T 4 3390 #define rx_x1_status0_r_type_coded_cl82_R_TYPE_D 2 3391 #define rx_x1_status0_r_type_coded_cl82_R_TYPE_E 1 3392 3393 /**************************************************************************** 3394 * Enums: rx_x1_status0_rxsm_state_cl82 3395 */ 3396 #define rx_x1_status0_rxsm_state_cl82_RX_HIG_END 64 3397 #define rx_x1_status0_rxsm_state_cl82_RX_HIG_START 32 3398 #define rx_x1_status0_rxsm_state_cl82_RX_E 16 3399 #define rx_x1_status0_rxsm_state_cl82_RX_T 8 3400 #define rx_x1_status0_rxsm_state_cl82_RX_D 4 3401 #define rx_x1_status0_rxsm_state_cl82_RX_C 2 3402 #define rx_x1_status0_rxsm_state_cl82_RX_INIT 1 3403 3404 /**************************************************************************** 3405 * Enums: rx_x1_status0_deskew_state 3406 */ 3407 #define rx_x1_status0_deskew_state_ALIGN_ACQUIRED 2 3408 #define rx_x1_status0_deskew_state_LOSS_OF_ALIGNMENT 1 3409 3410 /**************************************************************************** 3411 * Enums: rx_x1_status0_os_mode_enum 3412 */ 3413 #define rx_x1_status0_os_mode_enum_OS_MODE_1 0 3414 #define rx_x1_status0_os_mode_enum_OS_MODE_2 1 3415 #define rx_x1_status0_os_mode_enum_OS_MODE_4 2 3416 #define rx_x1_status0_os_mode_enum_OS_MODE_16p5 8 3417 #define rx_x1_status0_os_mode_enum_OS_MODE_20p625 12 3418 3419 /**************************************************************************** 3420 * Enums: rx_x1_status0_scr_modes 3421 */ 3422 #define rx_x1_status0_scr_modes_T_SCR_MODE_BYPASS 0 3423 #define rx_x1_status0_scr_modes_T_SCR_MODE_CL49 1 3424 #define rx_x1_status0_scr_modes_T_SCR_MODE_40G_2_LANE 2 3425 #define rx_x1_status0_scr_modes_T_SCR_MODE_100G 3 3426 #define rx_x1_status0_scr_modes_T_SCR_MODE_20G 4 3427 #define rx_x1_status0_scr_modes_T_SCR_MODE_40G_4_LANE 5 3428 3429 /**************************************************************************** 3430 * Enums: rx_x1_status0_descr_modes 3431 */ 3432 #define rx_x1_status0_descr_modes_R_DESCR_MODE_BYPASS 0 3433 #define rx_x1_status0_descr_modes_R_DESCR_MODE_CL49 1 3434 #define rx_x1_status0_descr_modes_R_DESCR_MODE_CL82 2 3435 3436 /**************************************************************************** 3437 * Enums: rx_x1_status0_r_dec_tl_mode 3438 */ 3439 #define rx_x1_status0_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 3440 #define rx_x1_status0_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 3441 #define rx_x1_status0_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 3442 3443 /**************************************************************************** 3444 * Enums: rx_x1_status0_r_dec_fsm_mode 3445 */ 3446 #define rx_x1_status0_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 3447 #define rx_x1_status0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 3448 #define rx_x1_status0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 3449 3450 /**************************************************************************** 3451 * Enums: rx_x1_status0_r_deskew_mode 3452 */ 3453 #define rx_x1_status0_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 3454 #define rx_x1_status0_r_deskew_mode_R_DESKEW_MODE_20G 1 3455 #define rx_x1_status0_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 3456 #define rx_x1_status0_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 3457 #define rx_x1_status0_r_deskew_mode_R_DESKEW_MODE_100G 4 3458 #define rx_x1_status0_r_deskew_mode_R_DESKEW_MODE_CL49 5 3459 #define rx_x1_status0_r_deskew_mode_R_DESKEW_MODE_CL91_QUAD 6 3460 #define rx_x1_status0_r_deskew_mode_R_DESKEW_MODE_CL91_SINGLE_BRCM 7 3461 #define rx_x1_status0_r_deskew_mode_R_DESKEW_MODE_CL91_DUAL_BRCM 8 3462 #define rx_x1_status0_r_deskew_mode_R_DESKEW_MODE_CL91_FC 9 3463 3464 /**************************************************************************** 3465 * Enums: rx_x1_status0_bs_dist_modes 3466 */ 3467 #define rx_x1_status0_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 3468 #define rx_x1_status0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 3469 #define rx_x1_status0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 3470 #define rx_x1_status0_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 3471 3472 /**************************************************************************** 3473 * Enums: rx_x1_status0_cl49_t_type 3474 */ 3475 #define rx_x1_status0_cl49_t_type_BAD_T_TYPE 15 3476 #define rx_x1_status0_cl49_t_type_T_TYPE_B0 11 3477 #define rx_x1_status0_cl49_t_type_T_TYPE_OB 10 3478 #define rx_x1_status0_cl49_t_type_T_TYPE_B1 9 3479 #define rx_x1_status0_cl49_t_type_T_TYPE_DB 8 3480 #define rx_x1_status0_cl49_t_type_T_TYPE_FC 7 3481 #define rx_x1_status0_cl49_t_type_T_TYPE_TB 6 3482 #define rx_x1_status0_cl49_t_type_T_TYPE_LI 5 3483 #define rx_x1_status0_cl49_t_type_T_TYPE_C 4 3484 #define rx_x1_status0_cl49_t_type_T_TYPE_S 3 3485 #define rx_x1_status0_cl49_t_type_T_TYPE_T 2 3486 #define rx_x1_status0_cl49_t_type_T_TYPE_D 1 3487 #define rx_x1_status0_cl49_t_type_T_TYPE_E 0 3488 3489 /**************************************************************************** 3490 * Enums: rx_x1_status0_cl49_txsm_states 3491 */ 3492 #define rx_x1_status0_cl49_txsm_states_TX_HIG_END 7 3493 #define rx_x1_status0_cl49_txsm_states_TX_HIG_START 6 3494 #define rx_x1_status0_cl49_txsm_states_TX_LI 5 3495 #define rx_x1_status0_cl49_txsm_states_TX_E 4 3496 #define rx_x1_status0_cl49_txsm_states_TX_T 3 3497 #define rx_x1_status0_cl49_txsm_states_TX_D 2 3498 #define rx_x1_status0_cl49_txsm_states_TX_C 1 3499 #define rx_x1_status0_cl49_txsm_states_TX_INIT 0 3500 3501 /**************************************************************************** 3502 * Enums: rx_x1_status0_cl49_ltxsm_states 3503 */ 3504 #define rx_x1_status0_cl49_ltxsm_states_TX_HIG_END 128 3505 #define rx_x1_status0_cl49_ltxsm_states_TX_HIG_START 64 3506 #define rx_x1_status0_cl49_ltxsm_states_TX_LI 32 3507 #define rx_x1_status0_cl49_ltxsm_states_TX_E 16 3508 #define rx_x1_status0_cl49_ltxsm_states_TX_T 8 3509 #define rx_x1_status0_cl49_ltxsm_states_TX_D 4 3510 #define rx_x1_status0_cl49_ltxsm_states_TX_C 2 3511 #define rx_x1_status0_cl49_ltxsm_states_TX_INIT 1 3512 3513 /**************************************************************************** 3514 * Enums: rx_x1_status0_burst_error_mode 3515 */ 3516 #define rx_x1_status0_burst_error_mode_BURST_ERROR_11_BITS 0 3517 #define rx_x1_status0_burst_error_mode_BURST_ERROR_16_BITS 1 3518 #define rx_x1_status0_burst_error_mode_BURST_ERROR_17_BITS 2 3519 #define rx_x1_status0_burst_error_mode_BURST_ERROR_18_BITS 3 3520 #define rx_x1_status0_burst_error_mode_BURST_ERROR_19_BITS 4 3521 #define rx_x1_status0_burst_error_mode_BURST_ERROR_20_BITS 5 3522 #define rx_x1_status0_burst_error_mode_BURST_ERROR_21_BITS 6 3523 #define rx_x1_status0_burst_error_mode_BURST_ERROR_22_BITS 7 3524 #define rx_x1_status0_burst_error_mode_BURST_ERROR_23_BITS 8 3525 #define rx_x1_status0_burst_error_mode_BURST_ERROR_24_BITS 9 3526 #define rx_x1_status0_burst_error_mode_BURST_ERROR_25_BITS 10 3527 #define rx_x1_status0_burst_error_mode_BURST_ERROR_26_BITS 11 3528 #define rx_x1_status0_burst_error_mode_BURST_ERROR_27_BITS 12 3529 #define rx_x1_status0_burst_error_mode_BURST_ERROR_28_BITS 13 3530 #define rx_x1_status0_burst_error_mode_BURST_ERROR_29_BITS 14 3531 #define rx_x1_status0_burst_error_mode_BURST_ERROR_30_BITS 15 3532 #define rx_x1_status0_burst_error_mode_BURST_ERROR_31_BITS 16 3533 #define rx_x1_status0_burst_error_mode_BURST_ERROR_32_BITS 17 3534 #define rx_x1_status0_burst_error_mode_BURST_ERROR_33_BITS 18 3535 #define rx_x1_status0_burst_error_mode_BURST_ERROR_34_BITS 19 3536 #define rx_x1_status0_burst_error_mode_BURST_ERROR_35_BITS 20 3537 #define rx_x1_status0_burst_error_mode_BURST_ERROR_36_BITS 21 3538 #define rx_x1_status0_burst_error_mode_BURST_ERROR_37_BITS 22 3539 #define rx_x1_status0_burst_error_mode_BURST_ERROR_38_BITS 23 3540 #define rx_x1_status0_burst_error_mode_BURST_ERROR_39_BITS 24 3541 #define rx_x1_status0_burst_error_mode_BURST_ERROR_40_BITS 25 3542 #define rx_x1_status0_burst_error_mode_BURST_ERROR_41_BITS 26 3543 3544 /**************************************************************************** 3545 * Enums: rx_x1_status0_bermon_state 3546 */ 3547 #define rx_x1_status0_bermon_state_HI_BER 4 3548 #define rx_x1_status0_bermon_state_GOOD_BER 3 3549 #define rx_x1_status0_bermon_state_BER_TEST_SH 2 3550 #define rx_x1_status0_bermon_state_START_TIMER 1 3551 #define rx_x1_status0_bermon_state_BER_MT_INIT 0 3552 3553 /**************************************************************************** 3554 * Enums: rx_x1_status0_rxsm_state_cl49 3555 */ 3556 #define rx_x1_status0_rxsm_state_cl49_RX_HIG_END 128 3557 #define rx_x1_status0_rxsm_state_cl49_RX_HIG_START 64 3558 #define rx_x1_status0_rxsm_state_cl49_RX_LI 32 3559 #define rx_x1_status0_rxsm_state_cl49_RX_E 16 3560 #define rx_x1_status0_rxsm_state_cl49_RX_T 8 3561 #define rx_x1_status0_rxsm_state_cl49_RX_D 4 3562 #define rx_x1_status0_rxsm_state_cl49_RX_C 2 3563 #define rx_x1_status0_rxsm_state_cl49_RX_INIT 1 3564 3565 /**************************************************************************** 3566 * Enums: rx_x1_status0_r_type 3567 */ 3568 #define rx_x1_status0_r_type_BAD_R_TYPE 15 3569 #define rx_x1_status0_r_type_R_TYPE_B0 11 3570 #define rx_x1_status0_r_type_R_TYPE_OB 10 3571 #define rx_x1_status0_r_type_R_TYPE_B1 9 3572 #define rx_x1_status0_r_type_R_TYPE_DB 8 3573 #define rx_x1_status0_r_type_R_TYPE_FC 7 3574 #define rx_x1_status0_r_type_R_TYPE_TB 6 3575 #define rx_x1_status0_r_type_R_TYPE_LI 5 3576 #define rx_x1_status0_r_type_R_TYPE_C 4 3577 #define rx_x1_status0_r_type_R_TYPE_S 3 3578 #define rx_x1_status0_r_type_R_TYPE_T 2 3579 #define rx_x1_status0_r_type_R_TYPE_D 1 3580 #define rx_x1_status0_r_type_R_TYPE_E 0 3581 3582 /**************************************************************************** 3583 * Enums: rx_x1_status0_am_lock_state 3584 */ 3585 #define rx_x1_status0_am_lock_state_INVALID_AM 512 3586 #define rx_x1_status0_am_lock_state_GOOD_AM 256 3587 #define rx_x1_status0_am_lock_state_COMP_AM 128 3588 #define rx_x1_status0_am_lock_state_TIMER_2 64 3589 #define rx_x1_status0_am_lock_state_AM_2_GOOD 32 3590 #define rx_x1_status0_am_lock_state_COMP_2ND 16 3591 #define rx_x1_status0_am_lock_state_TIMER_1 8 3592 #define rx_x1_status0_am_lock_state_FIND_1ST 4 3593 #define rx_x1_status0_am_lock_state_AM_RESET_CNT 2 3594 #define rx_x1_status0_am_lock_state_AM_LOCK_INIT 1 3595 3596 /**************************************************************************** 3597 * Enums: rx_x1_status0_msg_selector 3598 */ 3599 #define rx_x1_status0_msg_selector_RESERVED 0 3600 #define rx_x1_status0_msg_selector_VALUE_802p3 1 3601 #define rx_x1_status0_msg_selector_VALUE_802p9 2 3602 #define rx_x1_status0_msg_selector_VALUE_802p5 3 3603 #define rx_x1_status0_msg_selector_VALUE_1394 4 3604 3605 /**************************************************************************** 3606 * Enums: rx_x1_status0_synce_enum 3607 */ 3608 #define rx_x1_status0_synce_enum_SYNCE_NO_DIV 0 3609 #define rx_x1_status0_synce_enum_SYNCE_DIV_7 1 3610 #define rx_x1_status0_synce_enum_SYNCE_DIV_11 2 3611 3612 /**************************************************************************** 3613 * Enums: rx_x1_status0_synce_enum_stage0 3614 */ 3615 #define rx_x1_status0_synce_enum_stage0_SYNCE_NO_DIV 0 3616 #define rx_x1_status0_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 3617 #define rx_x1_status0_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 3618 3619 /**************************************************************************** 3620 * Enums: rx_x1_status0_cl91_sync_state 3621 */ 3622 #define rx_x1_status0_cl91_sync_state_FIND_1ST 0 3623 #define rx_x1_status0_cl91_sync_state_COUNT_NEXT 1 3624 #define rx_x1_status0_cl91_sync_state_COMP_2ND 2 3625 #define rx_x1_status0_cl91_sync_state_TWO_GOOD 3 3626 3627 /**************************************************************************** 3628 * Enums: rx_x1_status0_cl91_algn_state 3629 */ 3630 #define rx_x1_status0_cl91_algn_state_LOSS_OF_ALIGNMENT 0 3631 #define rx_x1_status0_cl91_algn_state_DESKEW 1 3632 #define rx_x1_status0_cl91_algn_state_DESKEW_FAIL 2 3633 #define rx_x1_status0_cl91_algn_state_ALIGN_ACQUIRED 3 3634 #define rx_x1_status0_cl91_algn_state_CW_GOOD 4 3635 #define rx_x1_status0_cl91_algn_state_CW_BAD 5 3636 #define rx_x1_status0_cl91_algn_state_THREE_BAD 6 3637 3638 /**************************************************************************** 3639 * Enums: rx_x1_status0_fec_sel_override 3640 */ 3641 #define rx_x1_status0_fec_sel_override_NO_OVERRIDE 0 3642 #define rx_x1_status0_fec_sel_override_NO_FEC 1 3643 #define rx_x1_status0_fec_sel_override_FEC_CL74 2 3644 #define rx_x1_status0_fec_sel_override_FEC_CL91 3 3645 3646 /**************************************************************************** 3647 * Enums: rx_x1_status0_cl91_blksync_mode 3648 */ 3649 #define rx_x1_status0_cl91_blksync_mode_R_BLKSYNC_NO_CL91_FEC 0 3650 #define rx_x1_status0_cl91_blksync_mode_R_BLKSYNC_CL91_QUAD_LANE_FEC 1 3651 #define rx_x1_status0_cl91_blksync_mode_R_BLKSYNC_CL91_DUAL_LANE_FEC 2 3652 #define rx_x1_status0_cl91_blksync_mode_R_BLKSYNC_CL91_SINGLE_LANE_FEC 3 3653 #define rx_x1_status0_cl91_blksync_mode_R_BLKSYNC_CL91_FC_FEC 4 3654 3655 /**************************************************************************** 3656 * Enums: rx_x1_status0_r_merge_mode 3657 */ 3658 #define rx_x1_status0_r_merge_mode_R_MERGE_MODE_BYPASS 0 3659 #define rx_x1_status0_r_merge_mode_R_MERGE_MODE_CL91_FC 1 3660 #define rx_x1_status0_r_merge_mode_R_MERGE_MODE_CL91_SINGLE_LANE 2 3661 #define rx_x1_status0_r_merge_mode_R_MERGE_MODE_CL91_DUAL_LANE 3 3662 #define rx_x1_status0_r_merge_mode_R_MERGE_MODE_CL91_QUAD_LANE 4 3663 3664 /**************************************************************************** 3665 * Enums: rx_x1_status0_r_tc_mode 3666 */ 3667 #define rx_x1_status0_r_tc_mode_R_TC_MODE_SINGLE 0 3668 #define rx_x1_status0_r_tc_mode_R_TC_MODE_DUAL 1 3669 #define rx_x1_status0_r_tc_mode_R_TC_MODE_QUAD 2 3670 3671 /**************************************************************************** 3672 * Enums: rx_x1_status0_r_tc_out_mode 3673 */ 3674 #define rx_x1_status0_r_tc_out_mode_R_TC_OUT_MODE_SINGLE 0 3675 #define rx_x1_status0_r_tc_out_mode_R_TC_OUT_MODE_DUAL 1 3676 #define rx_x1_status0_r_tc_out_mode_R_TC_OUT_MODE_QUAD 2 3677 3678 /**************************************************************************** 3679 * Enums: rx_x1_status0_cl91_fec_mode 3680 */ 3681 #define rx_x1_status0_cl91_fec_mode_NO_CL91_FEC 0 3682 #define rx_x1_status0_cl91_fec_mode_CL91_SINGLE_LANE_FC 1 3683 #define rx_x1_status0_cl91_fec_mode_CL91_SINGLE_LANE_BRCM_PROP 2 3684 #define rx_x1_status0_cl91_fec_mode_CL91_DUAL_LANE_BRCM_PROP 3 3685 #define rx_x1_status0_cl91_fec_mode_CL91_QUAD_LANE 4 3686 #define rx_x1_status0_cl91_fec_mode_IEEE_25G_CL91_SINGLE_LANE 5 3687 3688 /**************************************************************************** 3689 * Enums: rx_x1_status0_am_spacing_mul 3690 */ 3691 #define rx_x1_status0_am_spacing_mul_AM_SPACING_MUL_2 0 3692 #define rx_x1_status0_am_spacing_mul_AM_SPACING_MUL_4 1 3693 #define rx_x1_status0_am_spacing_mul_AM_SPACING_MUL_5 2 3694 #define rx_x1_status0_am_spacing_mul_AM_SPACING_MUL_20 3 3695 3696 /**************************************************************************** 3697 * Enums: rx_x4_cl91_status0_cl36TxEEEStates_l 3698 */ 3699 #define rx_x4_cl91_status0_cl36TxEEEStates_l_TX_REFRESH 8 3700 #define rx_x4_cl91_status0_cl36TxEEEStates_l_TX_QUIET 4 3701 #define rx_x4_cl91_status0_cl36TxEEEStates_l_TX_SLEEP 2 3702 #define rx_x4_cl91_status0_cl36TxEEEStates_l_TX_ACTIVE 1 3703 3704 /**************************************************************************** 3705 * Enums: rx_x4_cl91_status0_cl36TxEEEStates_c 3706 */ 3707 #define rx_x4_cl91_status0_cl36TxEEEStates_c_TX_REFRESH 3 3708 #define rx_x4_cl91_status0_cl36TxEEEStates_c_TX_QUIET 2 3709 #define rx_x4_cl91_status0_cl36TxEEEStates_c_TX_SLEEP 1 3710 #define rx_x4_cl91_status0_cl36TxEEEStates_c_TX_ACTIVE 0 3711 3712 /**************************************************************************** 3713 * Enums: rx_x4_cl91_status0_cl49TxEEEStates_l 3714 */ 3715 #define rx_x4_cl91_status0_cl49TxEEEStates_l_SCR_RESET_2 64 3716 #define rx_x4_cl91_status0_cl49TxEEEStates_l_SCR_RESET_1 32 3717 #define rx_x4_cl91_status0_cl49TxEEEStates_l_TX_WAKE 16 3718 #define rx_x4_cl91_status0_cl49TxEEEStates_l_TX_REFRESH 8 3719 #define rx_x4_cl91_status0_cl49TxEEEStates_l_TX_QUIET 4 3720 #define rx_x4_cl91_status0_cl49TxEEEStates_l_TX_SLEEP 2 3721 #define rx_x4_cl91_status0_cl49TxEEEStates_l_TX_ACTIVE 1 3722 3723 /**************************************************************************** 3724 * Enums: rx_x4_cl91_status0_fec_req_enum 3725 */ 3726 #define rx_x4_cl91_status0_fec_req_enum_FEC_not_supported 0 3727 #define rx_x4_cl91_status0_fec_req_enum_FEC_supported_but_not_requested 1 3728 #define rx_x4_cl91_status0_fec_req_enum_invalid_setting 2 3729 #define rx_x4_cl91_status0_fec_req_enum_FEC_supported_and_requested 3 3730 3731 /**************************************************************************** 3732 * Enums: rx_x4_cl91_status0_cl73_pause_enum 3733 */ 3734 #define rx_x4_cl91_status0_cl73_pause_enum_No_PAUSE_ability 0 3735 #define rx_x4_cl91_status0_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 3736 #define rx_x4_cl91_status0_cl73_pause_enum_Symmetric_PAUSE_ability 1 3737 #define rx_x4_cl91_status0_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 3738 3739 /**************************************************************************** 3740 * Enums: rx_x4_cl91_status0_cl49TxEEEStates_c 3741 */ 3742 #define rx_x4_cl91_status0_cl49TxEEEStates_c_SCR_RESET_2 6 3743 #define rx_x4_cl91_status0_cl49TxEEEStates_c_SCR_RESET_1 5 3744 #define rx_x4_cl91_status0_cl49TxEEEStates_c_TX_WAKE 4 3745 #define rx_x4_cl91_status0_cl49TxEEEStates_c_TX_REFRESH 3 3746 #define rx_x4_cl91_status0_cl49TxEEEStates_c_TX_QUIET 2 3747 #define rx_x4_cl91_status0_cl49TxEEEStates_c_TX_SLEEP 1 3748 #define rx_x4_cl91_status0_cl49TxEEEStates_c_TX_ACTIVE 0 3749 3750 /**************************************************************************** 3751 * Enums: rx_x4_cl91_status0_cl36RxEEEStates_l 3752 */ 3753 #define rx_x4_cl91_status0_cl36RxEEEStates_l_RX_LINK_FAIL 32 3754 #define rx_x4_cl91_status0_cl36RxEEEStates_l_RX_WTF 16 3755 #define rx_x4_cl91_status0_cl36RxEEEStates_l_RX_WAKE 8 3756 #define rx_x4_cl91_status0_cl36RxEEEStates_l_RX_QUIET 4 3757 #define rx_x4_cl91_status0_cl36RxEEEStates_l_RX_SLEEP 2 3758 #define rx_x4_cl91_status0_cl36RxEEEStates_l_RX_ACTIVE 1 3759 3760 /**************************************************************************** 3761 * Enums: rx_x4_cl91_status0_cl36RxEEEStates_c 3762 */ 3763 #define rx_x4_cl91_status0_cl36RxEEEStates_c_RX_LINK_FAIL 5 3764 #define rx_x4_cl91_status0_cl36RxEEEStates_c_RX_WTF 4 3765 #define rx_x4_cl91_status0_cl36RxEEEStates_c_RX_WAKE 3 3766 #define rx_x4_cl91_status0_cl36RxEEEStates_c_RX_QUIET 2 3767 #define rx_x4_cl91_status0_cl36RxEEEStates_c_RX_SLEEP 1 3768 #define rx_x4_cl91_status0_cl36RxEEEStates_c_RX_ACTIVE 0 3769 3770 /**************************************************************************** 3771 * Enums: rx_x4_cl91_status0_cl49RxEEEStates_l 3772 */ 3773 #define rx_x4_cl91_status0_cl49RxEEEStates_l_RX_LINK_FAIL 32 3774 #define rx_x4_cl91_status0_cl49RxEEEStates_l_RX_WTF 16 3775 #define rx_x4_cl91_status0_cl49RxEEEStates_l_RX_WAKE 8 3776 #define rx_x4_cl91_status0_cl49RxEEEStates_l_RX_QUIET 4 3777 #define rx_x4_cl91_status0_cl49RxEEEStates_l_RX_SLEEP 2 3778 #define rx_x4_cl91_status0_cl49RxEEEStates_l_RX_ACTIVE 1 3779 3780 /**************************************************************************** 3781 * Enums: rx_x4_cl91_status0_cl49RxEEEStates_c 3782 */ 3783 #define rx_x4_cl91_status0_cl49RxEEEStates_c_RX_LINK_FAIL 5 3784 #define rx_x4_cl91_status0_cl49RxEEEStates_c_RX_WTF 4 3785 #define rx_x4_cl91_status0_cl49RxEEEStates_c_RX_WAKE 3 3786 #define rx_x4_cl91_status0_cl49RxEEEStates_c_RX_QUIET 2 3787 #define rx_x4_cl91_status0_cl49RxEEEStates_c_RX_SLEEP 1 3788 #define rx_x4_cl91_status0_cl49RxEEEStates_c_RX_ACTIVE 0 3789 3790 /**************************************************************************** 3791 * Enums: rx_x4_cl91_status0_cl48TxEEEStates_l 3792 */ 3793 #define rx_x4_cl91_status0_cl48TxEEEStates_l_TX_REFRESH 8 3794 #define rx_x4_cl91_status0_cl48TxEEEStates_l_TX_QUIET 4 3795 #define rx_x4_cl91_status0_cl48TxEEEStates_l_TX_SLEEP 2 3796 #define rx_x4_cl91_status0_cl48TxEEEStates_l_TX_ACTIVE 1 3797 3798 /**************************************************************************** 3799 * Enums: rx_x4_cl91_status0_cl48TxEEEStates_c 3800 */ 3801 #define rx_x4_cl91_status0_cl48TxEEEStates_c_TX_REFRESH 3 3802 #define rx_x4_cl91_status0_cl48TxEEEStates_c_TX_QUIET 2 3803 #define rx_x4_cl91_status0_cl48TxEEEStates_c_TX_SLEEP 1 3804 #define rx_x4_cl91_status0_cl48TxEEEStates_c_TX_ACTIVE 0 3805 3806 /**************************************************************************** 3807 * Enums: rx_x4_cl91_status0_cl48RxEEEStates_l 3808 */ 3809 #define rx_x4_cl91_status0_cl48RxEEEStates_l_RX_LINK_FAIL 32 3810 #define rx_x4_cl91_status0_cl48RxEEEStates_l_RX_WAKE 16 3811 #define rx_x4_cl91_status0_cl48RxEEEStates_l_RX_QUIET 8 3812 #define rx_x4_cl91_status0_cl48RxEEEStates_l_RX_DEACT 4 3813 #define rx_x4_cl91_status0_cl48RxEEEStates_l_RX_SLEEP 2 3814 #define rx_x4_cl91_status0_cl48RxEEEStates_l_RX_ACTIVE 1 3815 3816 /**************************************************************************** 3817 * Enums: rx_x4_cl91_status0_cl48RxEEEStates_c 3818 */ 3819 #define rx_x4_cl91_status0_cl48RxEEEStates_c_RX_LINK_FAIL 5 3820 #define rx_x4_cl91_status0_cl48RxEEEStates_c_RX_WAKE 4 3821 #define rx_x4_cl91_status0_cl48RxEEEStates_c_RX_QUIET 3 3822 #define rx_x4_cl91_status0_cl48RxEEEStates_c_RX_DEACT 2 3823 #define rx_x4_cl91_status0_cl48RxEEEStates_c_RX_SLEEP 1 3824 #define rx_x4_cl91_status0_cl48RxEEEStates_c_RX_ACTIVE 0 3825 3826 /**************************************************************************** 3827 * Enums: rx_x4_cl91_status0_IQP_Options 3828 */ 3829 #define rx_x4_cl91_status0_IQP_Options_i50uA 0 3830 #define rx_x4_cl91_status0_IQP_Options_i100uA 1 3831 #define rx_x4_cl91_status0_IQP_Options_i150uA 2 3832 #define rx_x4_cl91_status0_IQP_Options_i200uA 3 3833 #define rx_x4_cl91_status0_IQP_Options_i250uA 4 3834 #define rx_x4_cl91_status0_IQP_Options_i300uA 5 3835 #define rx_x4_cl91_status0_IQP_Options_i350uA 6 3836 #define rx_x4_cl91_status0_IQP_Options_i400uA 7 3837 #define rx_x4_cl91_status0_IQP_Options_i450uA 8 3838 #define rx_x4_cl91_status0_IQP_Options_i500uA 9 3839 #define rx_x4_cl91_status0_IQP_Options_i550uA 10 3840 #define rx_x4_cl91_status0_IQP_Options_i600uA 11 3841 #define rx_x4_cl91_status0_IQP_Options_i650uA 12 3842 #define rx_x4_cl91_status0_IQP_Options_i700uA 13 3843 #define rx_x4_cl91_status0_IQP_Options_i750uA 14 3844 #define rx_x4_cl91_status0_IQP_Options_i800uA 15 3845 3846 /**************************************************************************** 3847 * Enums: rx_x4_cl91_status0_IDriver_Options 3848 */ 3849 #define rx_x4_cl91_status0_IDriver_Options_v680mV 0 3850 #define rx_x4_cl91_status0_IDriver_Options_v730mV 1 3851 #define rx_x4_cl91_status0_IDriver_Options_v780mV 2 3852 #define rx_x4_cl91_status0_IDriver_Options_v830mV 3 3853 #define rx_x4_cl91_status0_IDriver_Options_v880mV 4 3854 #define rx_x4_cl91_status0_IDriver_Options_v930mV 5 3855 #define rx_x4_cl91_status0_IDriver_Options_v980mV 6 3856 #define rx_x4_cl91_status0_IDriver_Options_v1010mV 7 3857 #define rx_x4_cl91_status0_IDriver_Options_v1040mV 8 3858 #define rx_x4_cl91_status0_IDriver_Options_v1060mV 9 3859 #define rx_x4_cl91_status0_IDriver_Options_v1070mV 10 3860 #define rx_x4_cl91_status0_IDriver_Options_v1080mV 11 3861 #define rx_x4_cl91_status0_IDriver_Options_v1085mV 12 3862 #define rx_x4_cl91_status0_IDriver_Options_v1090mV 13 3863 #define rx_x4_cl91_status0_IDriver_Options_v1095mV 14 3864 #define rx_x4_cl91_status0_IDriver_Options_v1100mV 15 3865 3866 /**************************************************************************** 3867 * Enums: rx_x4_cl91_status0_operationModes 3868 */ 3869 #define rx_x4_cl91_status0_operationModes_XGXS 0 3870 #define rx_x4_cl91_status0_operationModes_XGXG_nCC 1 3871 #define rx_x4_cl91_status0_operationModes_Indlane_OS8 4 3872 #define rx_x4_cl91_status0_operationModes_IndLane_OS5 5 3873 #define rx_x4_cl91_status0_operationModes_PCI 7 3874 #define rx_x4_cl91_status0_operationModes_XGXS_nLQ 8 3875 #define rx_x4_cl91_status0_operationModes_XGXS_nLQnCC 9 3876 #define rx_x4_cl91_status0_operationModes_PBypass 10 3877 #define rx_x4_cl91_status0_operationModes_PBypass_nDSK 11 3878 #define rx_x4_cl91_status0_operationModes_ComboCoreMode 12 3879 #define rx_x4_cl91_status0_operationModes_Clocks_off 15 3880 3881 /**************************************************************************** 3882 * Enums: rx_x4_cl91_status0_actualSpeeds 3883 */ 3884 #define rx_x4_cl91_status0_actualSpeeds_dr_10M 0 3885 #define rx_x4_cl91_status0_actualSpeeds_dr_100M 1 3886 #define rx_x4_cl91_status0_actualSpeeds_dr_1G 2 3887 #define rx_x4_cl91_status0_actualSpeeds_dr_2p5G 3 3888 #define rx_x4_cl91_status0_actualSpeeds_dr_5G_X4 4 3889 #define rx_x4_cl91_status0_actualSpeeds_dr_6G_X4 5 3890 #define rx_x4_cl91_status0_actualSpeeds_dr_10G_HiG 6 3891 #define rx_x4_cl91_status0_actualSpeeds_dr_10G_CX4 7 3892 #define rx_x4_cl91_status0_actualSpeeds_dr_12G_HiG 8 3893 #define rx_x4_cl91_status0_actualSpeeds_dr_12p5G_X4 9 3894 #define rx_x4_cl91_status0_actualSpeeds_dr_13G_X4 10 3895 #define rx_x4_cl91_status0_actualSpeeds_dr_15G_X4 11 3896 #define rx_x4_cl91_status0_actualSpeeds_dr_16G_X4 12 3897 #define rx_x4_cl91_status0_actualSpeeds_dr_1G_KX 13 3898 #define rx_x4_cl91_status0_actualSpeeds_dr_10G_KX4 14 3899 #define rx_x4_cl91_status0_actualSpeeds_dr_10G_KR 15 3900 #define rx_x4_cl91_status0_actualSpeeds_dr_5G 16 3901 #define rx_x4_cl91_status0_actualSpeeds_dr_6p4G 17 3902 #define rx_x4_cl91_status0_actualSpeeds_dr_20G_X4 18 3903 #define rx_x4_cl91_status0_actualSpeeds_dr_21G_X4 19 3904 #define rx_x4_cl91_status0_actualSpeeds_dr_25G_X4 20 3905 #define rx_x4_cl91_status0_actualSpeeds_dr_10G_HiG_DXGXS 21 3906 #define rx_x4_cl91_status0_actualSpeeds_dr_10G_DXGXS 22 3907 #define rx_x4_cl91_status0_actualSpeeds_dr_10p5G_HiG_DXGXS 23 3908 #define rx_x4_cl91_status0_actualSpeeds_dr_10p5G_DXGXS 24 3909 #define rx_x4_cl91_status0_actualSpeeds_dr_12p773G_HiG_DXGXS 25 3910 #define rx_x4_cl91_status0_actualSpeeds_dr_12p773G_DXGXS 26 3911 #define rx_x4_cl91_status0_actualSpeeds_dr_10G_XFI 27 3912 #define rx_x4_cl91_status0_actualSpeeds_dr_40G 28 3913 #define rx_x4_cl91_status0_actualSpeeds_dr_20G_HiG_DXGXS 29 3914 #define rx_x4_cl91_status0_actualSpeeds_dr_20G_DXGXS 30 3915 #define rx_x4_cl91_status0_actualSpeeds_dr_10G_SFI 31 3916 #define rx_x4_cl91_status0_actualSpeeds_dr_31p5G 32 3917 #define rx_x4_cl91_status0_actualSpeeds_dr_32p7G 33 3918 #define rx_x4_cl91_status0_actualSpeeds_dr_20G_SCR 34 3919 #define rx_x4_cl91_status0_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 3920 #define rx_x4_cl91_status0_actualSpeeds_dr_10G_DXGXS_SCR 36 3921 #define rx_x4_cl91_status0_actualSpeeds_dr_12G_R2 37 3922 #define rx_x4_cl91_status0_actualSpeeds_dr_10G_X2 38 3923 #define rx_x4_cl91_status0_actualSpeeds_dr_40G_KR4 39 3924 #define rx_x4_cl91_status0_actualSpeeds_dr_40G_CR4 40 3925 #define rx_x4_cl91_status0_actualSpeeds_dr_100G_CR10 41 3926 #define rx_x4_cl91_status0_actualSpeeds_dr_15p75G_DXGXS 44 3927 #define rx_x4_cl91_status0_actualSpeeds_dr_20G_KR2 57 3928 #define rx_x4_cl91_status0_actualSpeeds_dr_20G_CR2 58 3929 3930 /**************************************************************************** 3931 * Enums: rx_x4_cl91_status0_actualSpeedsMisc1 3932 */ 3933 #define rx_x4_cl91_status0_actualSpeedsMisc1_dr_2500BRCM_X1 16 3934 #define rx_x4_cl91_status0_actualSpeedsMisc1_dr_5000BRCM_X4 17 3935 #define rx_x4_cl91_status0_actualSpeedsMisc1_dr_6000BRCM_X4 18 3936 #define rx_x4_cl91_status0_actualSpeedsMisc1_dr_10GHiGig_X4 19 3937 #define rx_x4_cl91_status0_actualSpeedsMisc1_dr_10GBASE_CX4 20 3938 #define rx_x4_cl91_status0_actualSpeedsMisc1_dr_12GHiGig_X4 21 3939 #define rx_x4_cl91_status0_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 3940 #define rx_x4_cl91_status0_actualSpeedsMisc1_dr_13GHiGig_X4 23 3941 #define rx_x4_cl91_status0_actualSpeedsMisc1_dr_15GHiGig_X4 24 3942 #define rx_x4_cl91_status0_actualSpeedsMisc1_dr_16GHiGig_X4 25 3943 #define rx_x4_cl91_status0_actualSpeedsMisc1_dr_5000BRCM_X1 26 3944 #define rx_x4_cl91_status0_actualSpeedsMisc1_dr_6363BRCM_X1 27 3945 #define rx_x4_cl91_status0_actualSpeedsMisc1_dr_20GHiGig_X4 28 3946 #define rx_x4_cl91_status0_actualSpeedsMisc1_dr_21GHiGig_X4 29 3947 #define rx_x4_cl91_status0_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 3948 #define rx_x4_cl91_status0_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 3949 3950 /**************************************************************************** 3951 * Enums: rx_x4_cl91_status0_IndLaneModes 3952 */ 3953 #define rx_x4_cl91_status0_IndLaneModes_SWSDR_div2 0 3954 #define rx_x4_cl91_status0_IndLaneModes_SWSDR_div1 1 3955 #define rx_x4_cl91_status0_IndLaneModes_DWSDR_div2 2 3956 #define rx_x4_cl91_status0_IndLaneModes_DWSDR_div1 3 3957 3958 /**************************************************************************** 3959 * Enums: rx_x4_cl91_status0_prbsSelect 3960 */ 3961 #define rx_x4_cl91_status0_prbsSelect_prbs7 0 3962 #define rx_x4_cl91_status0_prbsSelect_prbs15 1 3963 #define rx_x4_cl91_status0_prbsSelect_prbs23 2 3964 #define rx_x4_cl91_status0_prbsSelect_prbs31 3 3965 3966 /**************************************************************************** 3967 * Enums: rx_x4_cl91_status0_vcoDivider 3968 */ 3969 #define rx_x4_cl91_status0_vcoDivider_div32 0 3970 #define rx_x4_cl91_status0_vcoDivider_div36 1 3971 #define rx_x4_cl91_status0_vcoDivider_div40 2 3972 #define rx_x4_cl91_status0_vcoDivider_div42 3 3973 #define rx_x4_cl91_status0_vcoDivider_div48 4 3974 #define rx_x4_cl91_status0_vcoDivider_div50 5 3975 #define rx_x4_cl91_status0_vcoDivider_div52 6 3976 #define rx_x4_cl91_status0_vcoDivider_div54 7 3977 #define rx_x4_cl91_status0_vcoDivider_div60 8 3978 #define rx_x4_cl91_status0_vcoDivider_div64 9 3979 #define rx_x4_cl91_status0_vcoDivider_div66 10 3980 #define rx_x4_cl91_status0_vcoDivider_div68 11 3981 #define rx_x4_cl91_status0_vcoDivider_div70 12 3982 #define rx_x4_cl91_status0_vcoDivider_div80 13 3983 #define rx_x4_cl91_status0_vcoDivider_div92 14 3984 #define rx_x4_cl91_status0_vcoDivider_div100 15 3985 3986 /**************************************************************************** 3987 * Enums: rx_x4_cl91_status0_refClkSelect 3988 */ 3989 #define rx_x4_cl91_status0_refClkSelect_clk_25MHz 0 3990 #define rx_x4_cl91_status0_refClkSelect_clk_100MHz 1 3991 #define rx_x4_cl91_status0_refClkSelect_clk_125MHz 2 3992 #define rx_x4_cl91_status0_refClkSelect_clk_156p25MHz 3 3993 #define rx_x4_cl91_status0_refClkSelect_clk_187p5MHz 4 3994 #define rx_x4_cl91_status0_refClkSelect_clk_161p25Mhz 5 3995 #define rx_x4_cl91_status0_refClkSelect_clk_50Mhz 6 3996 #define rx_x4_cl91_status0_refClkSelect_clk_106p25Mhz 7 3997 3998 /**************************************************************************** 3999 * Enums: rx_x4_cl91_status0_aerMMDdevTypeSelect 4000 */ 4001 #define rx_x4_cl91_status0_aerMMDdevTypeSelect_combo_core 0 4002 #define rx_x4_cl91_status0_aerMMDdevTypeSelect_PMA_PMD 1 4003 #define rx_x4_cl91_status0_aerMMDdevTypeSelect_PCS 3 4004 #define rx_x4_cl91_status0_aerMMDdevTypeSelect_PHY 4 4005 #define rx_x4_cl91_status0_aerMMDdevTypeSelect_DTE 5 4006 #define rx_x4_cl91_status0_aerMMDdevTypeSelect_CL73_AN 7 4007 4008 /**************************************************************************** 4009 * Enums: rx_x4_cl91_status0_aerMMDportSelect 4010 */ 4011 #define rx_x4_cl91_status0_aerMMDportSelect_ln0 0 4012 #define rx_x4_cl91_status0_aerMMDportSelect_ln1 1 4013 #define rx_x4_cl91_status0_aerMMDportSelect_ln2 2 4014 #define rx_x4_cl91_status0_aerMMDportSelect_ln3 3 4015 #define rx_x4_cl91_status0_aerMMDportSelect_BCST_ln0_1_2_3 511 4016 #define rx_x4_cl91_status0_aerMMDportSelect_BCST_ln0_1 512 4017 #define rx_x4_cl91_status0_aerMMDportSelect_BCST_ln2_3 513 4018 4019 /**************************************************************************** 4020 * Enums: rx_x4_cl91_status0_firmwareModeSelect 4021 */ 4022 #define rx_x4_cl91_status0_firmwareModeSelect_DEFAULT 0 4023 #define rx_x4_cl91_status0_firmwareModeSelect_SFP_OPT_LR 1 4024 #define rx_x4_cl91_status0_firmwareModeSelect_SFP_DAC 2 4025 #define rx_x4_cl91_status0_firmwareModeSelect_XLAUI 3 4026 #define rx_x4_cl91_status0_firmwareModeSelect_LONG_CH_6G 4 4027 4028 /**************************************************************************** 4029 * Enums: rx_x4_cl91_status0_tempIdxSelect 4030 */ 4031 #define rx_x4_cl91_status0_tempIdxSelect_LTE__22p9C 15 4032 #define rx_x4_cl91_status0_tempIdxSelect_LTE__12p6C 14 4033 #define rx_x4_cl91_status0_tempIdxSelect_LTE__3p0C 13 4034 #define rx_x4_cl91_status0_tempIdxSelect_LTE_6p7C 12 4035 #define rx_x4_cl91_status0_tempIdxSelect_LTE_16p4C 11 4036 #define rx_x4_cl91_status0_tempIdxSelect_LTE_26p6C 10 4037 #define rx_x4_cl91_status0_tempIdxSelect_LTE_36p3C 9 4038 #define rx_x4_cl91_status0_tempIdxSelect_LTE_46p0C 8 4039 #define rx_x4_cl91_status0_tempIdxSelect_LTE_56p2C 7 4040 #define rx_x4_cl91_status0_tempIdxSelect_LTE_65p9C 6 4041 #define rx_x4_cl91_status0_tempIdxSelect_LTE_75p6C 5 4042 #define rx_x4_cl91_status0_tempIdxSelect_LTE_85p3C 4 4043 #define rx_x4_cl91_status0_tempIdxSelect_LTE_95p5C 3 4044 #define rx_x4_cl91_status0_tempIdxSelect_LTE_105p2C 2 4045 #define rx_x4_cl91_status0_tempIdxSelect_LTE_114p9C 1 4046 #define rx_x4_cl91_status0_tempIdxSelect_LTE_125p1C 0 4047 4048 /**************************************************************************** 4049 * Enums: rx_x4_cl91_status0_port_mode 4050 */ 4051 #define rx_x4_cl91_status0_port_mode_QUAD_PORT 0 4052 #define rx_x4_cl91_status0_port_mode_TRI_1_PORT 1 4053 #define rx_x4_cl91_status0_port_mode_TRI_2_PORT 2 4054 #define rx_x4_cl91_status0_port_mode_DUAL_PORT 3 4055 #define rx_x4_cl91_status0_port_mode_SINGLE_PORT 4 4056 4057 /**************************************************************************** 4058 * Enums: rx_x4_cl91_status0_rev_letter_enum 4059 */ 4060 #define rx_x4_cl91_status0_rev_letter_enum_REV_A 0 4061 #define rx_x4_cl91_status0_rev_letter_enum_REV_B 1 4062 #define rx_x4_cl91_status0_rev_letter_enum_REV_C 2 4063 #define rx_x4_cl91_status0_rev_letter_enum_REV_D 3 4064 4065 /**************************************************************************** 4066 * Enums: rx_x4_cl91_status0_rev_number_enum 4067 */ 4068 #define rx_x4_cl91_status0_rev_number_enum_REV_0 0 4069 #define rx_x4_cl91_status0_rev_number_enum_REV_1 1 4070 #define rx_x4_cl91_status0_rev_number_enum_REV_2 2 4071 #define rx_x4_cl91_status0_rev_number_enum_REV_3 3 4072 #define rx_x4_cl91_status0_rev_number_enum_REV_4 4 4073 #define rx_x4_cl91_status0_rev_number_enum_REV_5 5 4074 #define rx_x4_cl91_status0_rev_number_enum_REV_6 6 4075 #define rx_x4_cl91_status0_rev_number_enum_REV_7 7 4076 4077 /**************************************************************************** 4078 * Enums: rx_x4_cl91_status0_bonding_enum 4079 */ 4080 #define rx_x4_cl91_status0_bonding_enum_WIRE_BOND 0 4081 #define rx_x4_cl91_status0_bonding_enum_FLIP_CHIP 1 4082 4083 /**************************************************************************** 4084 * Enums: rx_x4_cl91_status0_tech_process 4085 */ 4086 #define rx_x4_cl91_status0_tech_process_PROCESS_90NM 0 4087 #define rx_x4_cl91_status0_tech_process_PROCESS_65NM 1 4088 #define rx_x4_cl91_status0_tech_process_PROCESS_40NM 2 4089 #define rx_x4_cl91_status0_tech_process_PROCESS_28NM 3 4090 #define rx_x4_cl91_status0_tech_process_PROCESS_16NM 4 4091 4092 /**************************************************************************** 4093 * Enums: rx_x4_cl91_status0_model_num 4094 */ 4095 #define rx_x4_cl91_status0_model_num_SERDES_CL73 0 4096 #define rx_x4_cl91_status0_model_num_XGXS_16G 1 4097 #define rx_x4_cl91_status0_model_num_HYPERCORE 2 4098 #define rx_x4_cl91_status0_model_num_HYPERLITE 3 4099 #define rx_x4_cl91_status0_model_num_PCIE_G2_PIPE 4 4100 #define rx_x4_cl91_status0_model_num_SERDES_1p25GBd 5 4101 #define rx_x4_cl91_status0_model_num_SATA2 6 4102 #define rx_x4_cl91_status0_model_num_QSGMII 7 4103 #define rx_x4_cl91_status0_model_num_XGXS10G 8 4104 #define rx_x4_cl91_status0_model_num_WARPCORE 9 4105 #define rx_x4_cl91_status0_model_num_XFICORE 10 4106 #define rx_x4_cl91_status0_model_num_RXFI 11 4107 #define rx_x4_cl91_status0_model_num_WARPLITE 12 4108 #define rx_x4_cl91_status0_model_num_PENTACORE 13 4109 #define rx_x4_cl91_status0_model_num_ESM 14 4110 #define rx_x4_cl91_status0_model_num_QUAD_SGMII 15 4111 #define rx_x4_cl91_status0_model_num_WARPCORE_3 16 4112 #define rx_x4_cl91_status0_model_num_TSC 17 4113 #define rx_x4_cl91_status0_model_num_TSC4E 18 4114 #define rx_x4_cl91_status0_model_num_TSC12E 19 4115 #define rx_x4_cl91_status0_model_num_TSC4F 20 4116 #define rx_x4_cl91_status0_model_num_TSC4F_GEN2 21 4117 #define rx_x4_cl91_status0_model_num_XGXS_CL73_90NM 29 4118 #define rx_x4_cl91_status0_model_num_SERDES_CL73_90NM 30 4119 #define rx_x4_cl91_status0_model_num_WARPCORE3 32 4120 #define rx_x4_cl91_status0_model_num_WARPCORE4_TSC 33 4121 #define rx_x4_cl91_status0_model_num_RXAUI 34 4122 4123 /**************************************************************************** 4124 * Enums: rx_x4_cl91_status0_payload 4125 */ 4126 #define rx_x4_cl91_status0_payload_REPEAT_2_BYTES 0 4127 #define rx_x4_cl91_status0_payload_RAMPING 1 4128 #define rx_x4_cl91_status0_payload_CL48_CRPAT 2 4129 #define rx_x4_cl91_status0_payload_CL48_CJPAT 3 4130 #define rx_x4_cl91_status0_payload_CL36_LONG_CRPAT 4 4131 #define rx_x4_cl91_status0_payload_CL36_SHORT_CRPAT 5 4132 4133 /**************************************************************************** 4134 * Enums: rx_x4_cl91_status0_sc 4135 */ 4136 #define rx_x4_cl91_status0_sc_S_10G_CR1 0 4137 #define rx_x4_cl91_status0_sc_S_10G_KR1 1 4138 #define rx_x4_cl91_status0_sc_S_10G_X1 2 4139 #define rx_x4_cl91_status0_sc_S_10G_HG2_CR1 4 4140 #define rx_x4_cl91_status0_sc_S_10G_HG2_KR1 5 4141 #define rx_x4_cl91_status0_sc_S_10G_HG2_X1 6 4142 #define rx_x4_cl91_status0_sc_S_20G_CR1 8 4143 #define rx_x4_cl91_status0_sc_S_20G_KR1 9 4144 #define rx_x4_cl91_status0_sc_S_20G_X1 10 4145 #define rx_x4_cl91_status0_sc_S_20G_HG2_CR1 12 4146 #define rx_x4_cl91_status0_sc_S_20G_HG2_KR1 13 4147 #define rx_x4_cl91_status0_sc_S_20G_HG2_X1 14 4148 #define rx_x4_cl91_status0_sc_S_25G_CR1 16 4149 #define rx_x4_cl91_status0_sc_S_25G_KR1 17 4150 #define rx_x4_cl91_status0_sc_S_25G_X1 18 4151 #define rx_x4_cl91_status0_sc_S_25G_HG2_CR1 20 4152 #define rx_x4_cl91_status0_sc_S_25G_HG2_KR1 21 4153 #define rx_x4_cl91_status0_sc_S_25G_HG2_X1 22 4154 #define rx_x4_cl91_status0_sc_S_20G_CR2 24 4155 #define rx_x4_cl91_status0_sc_S_20G_KR2 25 4156 #define rx_x4_cl91_status0_sc_S_20G_X2 26 4157 #define rx_x4_cl91_status0_sc_S_20G_HG2_CR2 28 4158 #define rx_x4_cl91_status0_sc_S_20G_HG2_KR2 29 4159 #define rx_x4_cl91_status0_sc_S_20G_HG2_X2 30 4160 #define rx_x4_cl91_status0_sc_S_40G_CR2 32 4161 #define rx_x4_cl91_status0_sc_S_40G_KR2 33 4162 #define rx_x4_cl91_status0_sc_S_40G_X2 34 4163 #define rx_x4_cl91_status0_sc_S_40G_HG2_CR2 36 4164 #define rx_x4_cl91_status0_sc_S_40G_HG2_KR2 37 4165 #define rx_x4_cl91_status0_sc_S_40G_HG2_X2 38 4166 #define rx_x4_cl91_status0_sc_S_40G_CR4 40 4167 #define rx_x4_cl91_status0_sc_S_40G_KR4 41 4168 #define rx_x4_cl91_status0_sc_S_40G_X4 42 4169 #define rx_x4_cl91_status0_sc_S_40G_HG2_CR4 44 4170 #define rx_x4_cl91_status0_sc_S_40G_HG2_KR4 45 4171 #define rx_x4_cl91_status0_sc_S_40G_HG2_X4 46 4172 #define rx_x4_cl91_status0_sc_S_50G_CR2 48 4173 #define rx_x4_cl91_status0_sc_S_50G_KR2 49 4174 #define rx_x4_cl91_status0_sc_S_50G_X2 50 4175 #define rx_x4_cl91_status0_sc_S_50G_HG2_CR2 52 4176 #define rx_x4_cl91_status0_sc_S_50G_HG2_KR2 53 4177 #define rx_x4_cl91_status0_sc_S_50G_HG2_X2 54 4178 #define rx_x4_cl91_status0_sc_S_50G_CR4 56 4179 #define rx_x4_cl91_status0_sc_S_50G_KR4 57 4180 #define rx_x4_cl91_status0_sc_S_50G_X4 58 4181 #define rx_x4_cl91_status0_sc_S_50G_HG2_CR4 60 4182 #define rx_x4_cl91_status0_sc_S_50G_HG2_KR4 61 4183 #define rx_x4_cl91_status0_sc_S_50G_HG2_X4 62 4184 #define rx_x4_cl91_status0_sc_S_100G_CR4 64 4185 #define rx_x4_cl91_status0_sc_S_100G_KR4 65 4186 #define rx_x4_cl91_status0_sc_S_100G_X4 66 4187 #define rx_x4_cl91_status0_sc_S_100G_HG2_CR4 68 4188 #define rx_x4_cl91_status0_sc_S_100G_HG2_KR4 69 4189 #define rx_x4_cl91_status0_sc_S_100G_HG2_X4 70 4190 #define rx_x4_cl91_status0_sc_S_CL73_20GVCO 72 4191 #define rx_x4_cl91_status0_sc_S_CL73_25GVCO 80 4192 #define rx_x4_cl91_status0_sc_S_CL36_20GVCO 88 4193 #define rx_x4_cl91_status0_sc_S_CL36_25GVCO 96 4194 #define rx_x4_cl91_status0_sc_S_25G_CR_IEEE 112 4195 #define rx_x4_cl91_status0_sc_S_25G_CRS_IEEE 113 4196 #define rx_x4_cl91_status0_sc_S_25G_KR_IEEE 114 4197 #define rx_x4_cl91_status0_sc_S_25G_KRS_IEEE 115 4198 4199 /**************************************************************************** 4200 * Enums: rx_x4_cl91_status0_t_fifo_modes 4201 */ 4202 #define rx_x4_cl91_status0_t_fifo_modes_T_FIFO_INSERT_NO_AM 0 4203 #define rx_x4_cl91_status0_t_fifo_modes_T_FIFO_INSERT_4_AM 1 4204 #define rx_x4_cl91_status0_t_fifo_modes_T_FIFO_INSERT_20_AM 2 4205 #define rx_x4_cl91_status0_t_fifo_modes_T_FIFO_INSERT_2_AM 3 4206 4207 /**************************************************************************** 4208 * Enums: rx_x4_cl91_status0_t_enc_modes 4209 */ 4210 #define rx_x4_cl91_status0_t_enc_modes_T_ENC_MODE_BYPASS 0 4211 #define rx_x4_cl91_status0_t_enc_modes_T_ENC_MODE_CL49 1 4212 #define rx_x4_cl91_status0_t_enc_modes_T_ENC_MODE_CL82 2 4213 4214 /**************************************************************************** 4215 * Enums: rx_x4_cl91_status0_btmx_mode 4216 */ 4217 #define rx_x4_cl91_status0_btmx_mode_BS_BTMX_MODE_1to1 0 4218 #define rx_x4_cl91_status0_btmx_mode_BS_BTMX_MODE_2to1 1 4219 #define rx_x4_cl91_status0_btmx_mode_BS_BTMX_MODE_5to1 2 4220 4221 /**************************************************************************** 4222 * Enums: rx_x4_cl91_status0_t_type_cl82 4223 */ 4224 #define rx_x4_cl91_status0_t_type_cl82_T_TYPE_B1 5 4225 #define rx_x4_cl91_status0_t_type_cl82_T_TYPE_C 4 4226 #define rx_x4_cl91_status0_t_type_cl82_T_TYPE_S 3 4227 #define rx_x4_cl91_status0_t_type_cl82_T_TYPE_T 2 4228 #define rx_x4_cl91_status0_t_type_cl82_T_TYPE_D 1 4229 #define rx_x4_cl91_status0_t_type_cl82_T_TYPE_E 0 4230 4231 /**************************************************************************** 4232 * Enums: rx_x4_cl91_status0_txsm_state_cl82 4233 */ 4234 #define rx_x4_cl91_status0_txsm_state_cl82_TX_HIG_END 6 4235 #define rx_x4_cl91_status0_txsm_state_cl82_TX_HIG_START 5 4236 #define rx_x4_cl91_status0_txsm_state_cl82_TX_E 4 4237 #define rx_x4_cl91_status0_txsm_state_cl82_TX_T 3 4238 #define rx_x4_cl91_status0_txsm_state_cl82_TX_D 2 4239 #define rx_x4_cl91_status0_txsm_state_cl82_TX_C 1 4240 #define rx_x4_cl91_status0_txsm_state_cl82_TX_INIT 0 4241 4242 /**************************************************************************** 4243 * Enums: rx_x4_cl91_status0_ltxsm_state_cl82 4244 */ 4245 #define rx_x4_cl91_status0_ltxsm_state_cl82_TX_HIG_END 64 4246 #define rx_x4_cl91_status0_ltxsm_state_cl82_TX_HIG_START 32 4247 #define rx_x4_cl91_status0_ltxsm_state_cl82_TX_E 16 4248 #define rx_x4_cl91_status0_ltxsm_state_cl82_TX_T 8 4249 #define rx_x4_cl91_status0_ltxsm_state_cl82_TX_D 4 4250 #define rx_x4_cl91_status0_ltxsm_state_cl82_TX_C 2 4251 #define rx_x4_cl91_status0_ltxsm_state_cl82_TX_INIT 1 4252 4253 /**************************************************************************** 4254 * Enums: rx_x4_cl91_status0_r_type_coded_cl82 4255 */ 4256 #define rx_x4_cl91_status0_r_type_coded_cl82_R_TYPE_B1 32 4257 #define rx_x4_cl91_status0_r_type_coded_cl82_R_TYPE_C 16 4258 #define rx_x4_cl91_status0_r_type_coded_cl82_R_TYPE_S 8 4259 #define rx_x4_cl91_status0_r_type_coded_cl82_R_TYPE_T 4 4260 #define rx_x4_cl91_status0_r_type_coded_cl82_R_TYPE_D 2 4261 #define rx_x4_cl91_status0_r_type_coded_cl82_R_TYPE_E 1 4262 4263 /**************************************************************************** 4264 * Enums: rx_x4_cl91_status0_rxsm_state_cl82 4265 */ 4266 #define rx_x4_cl91_status0_rxsm_state_cl82_RX_HIG_END 64 4267 #define rx_x4_cl91_status0_rxsm_state_cl82_RX_HIG_START 32 4268 #define rx_x4_cl91_status0_rxsm_state_cl82_RX_E 16 4269 #define rx_x4_cl91_status0_rxsm_state_cl82_RX_T 8 4270 #define rx_x4_cl91_status0_rxsm_state_cl82_RX_D 4 4271 #define rx_x4_cl91_status0_rxsm_state_cl82_RX_C 2 4272 #define rx_x4_cl91_status0_rxsm_state_cl82_RX_INIT 1 4273 4274 /**************************************************************************** 4275 * Enums: rx_x4_cl91_status0_deskew_state 4276 */ 4277 #define rx_x4_cl91_status0_deskew_state_ALIGN_ACQUIRED 2 4278 #define rx_x4_cl91_status0_deskew_state_LOSS_OF_ALIGNMENT 1 4279 4280 /**************************************************************************** 4281 * Enums: rx_x4_cl91_status0_os_mode_enum 4282 */ 4283 #define rx_x4_cl91_status0_os_mode_enum_OS_MODE_1 0 4284 #define rx_x4_cl91_status0_os_mode_enum_OS_MODE_2 1 4285 #define rx_x4_cl91_status0_os_mode_enum_OS_MODE_4 2 4286 #define rx_x4_cl91_status0_os_mode_enum_OS_MODE_16p5 8 4287 #define rx_x4_cl91_status0_os_mode_enum_OS_MODE_20p625 12 4288 4289 /**************************************************************************** 4290 * Enums: rx_x4_cl91_status0_scr_modes 4291 */ 4292 #define rx_x4_cl91_status0_scr_modes_T_SCR_MODE_BYPASS 0 4293 #define rx_x4_cl91_status0_scr_modes_T_SCR_MODE_CL49 1 4294 #define rx_x4_cl91_status0_scr_modes_T_SCR_MODE_40G_2_LANE 2 4295 #define rx_x4_cl91_status0_scr_modes_T_SCR_MODE_100G 3 4296 #define rx_x4_cl91_status0_scr_modes_T_SCR_MODE_20G 4 4297 #define rx_x4_cl91_status0_scr_modes_T_SCR_MODE_40G_4_LANE 5 4298 4299 /**************************************************************************** 4300 * Enums: rx_x4_cl91_status0_descr_modes 4301 */ 4302 #define rx_x4_cl91_status0_descr_modes_R_DESCR_MODE_BYPASS 0 4303 #define rx_x4_cl91_status0_descr_modes_R_DESCR_MODE_CL49 1 4304 #define rx_x4_cl91_status0_descr_modes_R_DESCR_MODE_CL82 2 4305 4306 /**************************************************************************** 4307 * Enums: rx_x4_cl91_status0_r_dec_tl_mode 4308 */ 4309 #define rx_x4_cl91_status0_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 4310 #define rx_x4_cl91_status0_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 4311 #define rx_x4_cl91_status0_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 4312 4313 /**************************************************************************** 4314 * Enums: rx_x4_cl91_status0_r_dec_fsm_mode 4315 */ 4316 #define rx_x4_cl91_status0_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 4317 #define rx_x4_cl91_status0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 4318 #define rx_x4_cl91_status0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 4319 4320 /**************************************************************************** 4321 * Enums: rx_x4_cl91_status0_r_deskew_mode 4322 */ 4323 #define rx_x4_cl91_status0_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 4324 #define rx_x4_cl91_status0_r_deskew_mode_R_DESKEW_MODE_20G 1 4325 #define rx_x4_cl91_status0_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 4326 #define rx_x4_cl91_status0_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 4327 #define rx_x4_cl91_status0_r_deskew_mode_R_DESKEW_MODE_100G 4 4328 #define rx_x4_cl91_status0_r_deskew_mode_R_DESKEW_MODE_CL49 5 4329 #define rx_x4_cl91_status0_r_deskew_mode_R_DESKEW_MODE_CL91_QUAD 6 4330 #define rx_x4_cl91_status0_r_deskew_mode_R_DESKEW_MODE_CL91_SINGLE_BRCM 7 4331 #define rx_x4_cl91_status0_r_deskew_mode_R_DESKEW_MODE_CL91_DUAL_BRCM 8 4332 #define rx_x4_cl91_status0_r_deskew_mode_R_DESKEW_MODE_CL91_FC 9 4333 4334 /**************************************************************************** 4335 * Enums: rx_x4_cl91_status0_bs_dist_modes 4336 */ 4337 #define rx_x4_cl91_status0_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 4338 #define rx_x4_cl91_status0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 4339 #define rx_x4_cl91_status0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 4340 #define rx_x4_cl91_status0_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 4341 4342 /**************************************************************************** 4343 * Enums: rx_x4_cl91_status0_cl49_t_type 4344 */ 4345 #define rx_x4_cl91_status0_cl49_t_type_BAD_T_TYPE 15 4346 #define rx_x4_cl91_status0_cl49_t_type_T_TYPE_B0 11 4347 #define rx_x4_cl91_status0_cl49_t_type_T_TYPE_OB 10 4348 #define rx_x4_cl91_status0_cl49_t_type_T_TYPE_B1 9 4349 #define rx_x4_cl91_status0_cl49_t_type_T_TYPE_DB 8 4350 #define rx_x4_cl91_status0_cl49_t_type_T_TYPE_FC 7 4351 #define rx_x4_cl91_status0_cl49_t_type_T_TYPE_TB 6 4352 #define rx_x4_cl91_status0_cl49_t_type_T_TYPE_LI 5 4353 #define rx_x4_cl91_status0_cl49_t_type_T_TYPE_C 4 4354 #define rx_x4_cl91_status0_cl49_t_type_T_TYPE_S 3 4355 #define rx_x4_cl91_status0_cl49_t_type_T_TYPE_T 2 4356 #define rx_x4_cl91_status0_cl49_t_type_T_TYPE_D 1 4357 #define rx_x4_cl91_status0_cl49_t_type_T_TYPE_E 0 4358 4359 /**************************************************************************** 4360 * Enums: rx_x4_cl91_status0_cl49_txsm_states 4361 */ 4362 #define rx_x4_cl91_status0_cl49_txsm_states_TX_HIG_END 7 4363 #define rx_x4_cl91_status0_cl49_txsm_states_TX_HIG_START 6 4364 #define rx_x4_cl91_status0_cl49_txsm_states_TX_LI 5 4365 #define rx_x4_cl91_status0_cl49_txsm_states_TX_E 4 4366 #define rx_x4_cl91_status0_cl49_txsm_states_TX_T 3 4367 #define rx_x4_cl91_status0_cl49_txsm_states_TX_D 2 4368 #define rx_x4_cl91_status0_cl49_txsm_states_TX_C 1 4369 #define rx_x4_cl91_status0_cl49_txsm_states_TX_INIT 0 4370 4371 /**************************************************************************** 4372 * Enums: rx_x4_cl91_status0_cl49_ltxsm_states 4373 */ 4374 #define rx_x4_cl91_status0_cl49_ltxsm_states_TX_HIG_END 128 4375 #define rx_x4_cl91_status0_cl49_ltxsm_states_TX_HIG_START 64 4376 #define rx_x4_cl91_status0_cl49_ltxsm_states_TX_LI 32 4377 #define rx_x4_cl91_status0_cl49_ltxsm_states_TX_E 16 4378 #define rx_x4_cl91_status0_cl49_ltxsm_states_TX_T 8 4379 #define rx_x4_cl91_status0_cl49_ltxsm_states_TX_D 4 4380 #define rx_x4_cl91_status0_cl49_ltxsm_states_TX_C 2 4381 #define rx_x4_cl91_status0_cl49_ltxsm_states_TX_INIT 1 4382 4383 /**************************************************************************** 4384 * Enums: rx_x4_cl91_status0_burst_error_mode 4385 */ 4386 #define rx_x4_cl91_status0_burst_error_mode_BURST_ERROR_11_BITS 0 4387 #define rx_x4_cl91_status0_burst_error_mode_BURST_ERROR_16_BITS 1 4388 #define rx_x4_cl91_status0_burst_error_mode_BURST_ERROR_17_BITS 2 4389 #define rx_x4_cl91_status0_burst_error_mode_BURST_ERROR_18_BITS 3 4390 #define rx_x4_cl91_status0_burst_error_mode_BURST_ERROR_19_BITS 4 4391 #define rx_x4_cl91_status0_burst_error_mode_BURST_ERROR_20_BITS 5 4392 #define rx_x4_cl91_status0_burst_error_mode_BURST_ERROR_21_BITS 6 4393 #define rx_x4_cl91_status0_burst_error_mode_BURST_ERROR_22_BITS 7 4394 #define rx_x4_cl91_status0_burst_error_mode_BURST_ERROR_23_BITS 8 4395 #define rx_x4_cl91_status0_burst_error_mode_BURST_ERROR_24_BITS 9 4396 #define rx_x4_cl91_status0_burst_error_mode_BURST_ERROR_25_BITS 10 4397 #define rx_x4_cl91_status0_burst_error_mode_BURST_ERROR_26_BITS 11 4398 #define rx_x4_cl91_status0_burst_error_mode_BURST_ERROR_27_BITS 12 4399 #define rx_x4_cl91_status0_burst_error_mode_BURST_ERROR_28_BITS 13 4400 #define rx_x4_cl91_status0_burst_error_mode_BURST_ERROR_29_BITS 14 4401 #define rx_x4_cl91_status0_burst_error_mode_BURST_ERROR_30_BITS 15 4402 #define rx_x4_cl91_status0_burst_error_mode_BURST_ERROR_31_BITS 16 4403 #define rx_x4_cl91_status0_burst_error_mode_BURST_ERROR_32_BITS 17 4404 #define rx_x4_cl91_status0_burst_error_mode_BURST_ERROR_33_BITS 18 4405 #define rx_x4_cl91_status0_burst_error_mode_BURST_ERROR_34_BITS 19 4406 #define rx_x4_cl91_status0_burst_error_mode_BURST_ERROR_35_BITS 20 4407 #define rx_x4_cl91_status0_burst_error_mode_BURST_ERROR_36_BITS 21 4408 #define rx_x4_cl91_status0_burst_error_mode_BURST_ERROR_37_BITS 22 4409 #define rx_x4_cl91_status0_burst_error_mode_BURST_ERROR_38_BITS 23 4410 #define rx_x4_cl91_status0_burst_error_mode_BURST_ERROR_39_BITS 24 4411 #define rx_x4_cl91_status0_burst_error_mode_BURST_ERROR_40_BITS 25 4412 #define rx_x4_cl91_status0_burst_error_mode_BURST_ERROR_41_BITS 26 4413 4414 /**************************************************************************** 4415 * Enums: rx_x4_cl91_status0_bermon_state 4416 */ 4417 #define rx_x4_cl91_status0_bermon_state_HI_BER 4 4418 #define rx_x4_cl91_status0_bermon_state_GOOD_BER 3 4419 #define rx_x4_cl91_status0_bermon_state_BER_TEST_SH 2 4420 #define rx_x4_cl91_status0_bermon_state_START_TIMER 1 4421 #define rx_x4_cl91_status0_bermon_state_BER_MT_INIT 0 4422 4423 /**************************************************************************** 4424 * Enums: rx_x4_cl91_status0_rxsm_state_cl49 4425 */ 4426 #define rx_x4_cl91_status0_rxsm_state_cl49_RX_HIG_END 128 4427 #define rx_x4_cl91_status0_rxsm_state_cl49_RX_HIG_START 64 4428 #define rx_x4_cl91_status0_rxsm_state_cl49_RX_LI 32 4429 #define rx_x4_cl91_status0_rxsm_state_cl49_RX_E 16 4430 #define rx_x4_cl91_status0_rxsm_state_cl49_RX_T 8 4431 #define rx_x4_cl91_status0_rxsm_state_cl49_RX_D 4 4432 #define rx_x4_cl91_status0_rxsm_state_cl49_RX_C 2 4433 #define rx_x4_cl91_status0_rxsm_state_cl49_RX_INIT 1 4434 4435 /**************************************************************************** 4436 * Enums: rx_x4_cl91_status0_r_type 4437 */ 4438 #define rx_x4_cl91_status0_r_type_BAD_R_TYPE 15 4439 #define rx_x4_cl91_status0_r_type_R_TYPE_B0 11 4440 #define rx_x4_cl91_status0_r_type_R_TYPE_OB 10 4441 #define rx_x4_cl91_status0_r_type_R_TYPE_B1 9 4442 #define rx_x4_cl91_status0_r_type_R_TYPE_DB 8 4443 #define rx_x4_cl91_status0_r_type_R_TYPE_FC 7 4444 #define rx_x4_cl91_status0_r_type_R_TYPE_TB 6 4445 #define rx_x4_cl91_status0_r_type_R_TYPE_LI 5 4446 #define rx_x4_cl91_status0_r_type_R_TYPE_C 4 4447 #define rx_x4_cl91_status0_r_type_R_TYPE_S 3 4448 #define rx_x4_cl91_status0_r_type_R_TYPE_T 2 4449 #define rx_x4_cl91_status0_r_type_R_TYPE_D 1 4450 #define rx_x4_cl91_status0_r_type_R_TYPE_E 0 4451 4452 /**************************************************************************** 4453 * Enums: rx_x4_cl91_status0_am_lock_state 4454 */ 4455 #define rx_x4_cl91_status0_am_lock_state_INVALID_AM 512 4456 #define rx_x4_cl91_status0_am_lock_state_GOOD_AM 256 4457 #define rx_x4_cl91_status0_am_lock_state_COMP_AM 128 4458 #define rx_x4_cl91_status0_am_lock_state_TIMER_2 64 4459 #define rx_x4_cl91_status0_am_lock_state_AM_2_GOOD 32 4460 #define rx_x4_cl91_status0_am_lock_state_COMP_2ND 16 4461 #define rx_x4_cl91_status0_am_lock_state_TIMER_1 8 4462 #define rx_x4_cl91_status0_am_lock_state_FIND_1ST 4 4463 #define rx_x4_cl91_status0_am_lock_state_AM_RESET_CNT 2 4464 #define rx_x4_cl91_status0_am_lock_state_AM_LOCK_INIT 1 4465 4466 /**************************************************************************** 4467 * Enums: rx_x4_cl91_status0_msg_selector 4468 */ 4469 #define rx_x4_cl91_status0_msg_selector_RESERVED 0 4470 #define rx_x4_cl91_status0_msg_selector_VALUE_802p3 1 4471 #define rx_x4_cl91_status0_msg_selector_VALUE_802p9 2 4472 #define rx_x4_cl91_status0_msg_selector_VALUE_802p5 3 4473 #define rx_x4_cl91_status0_msg_selector_VALUE_1394 4 4474 4475 /**************************************************************************** 4476 * Enums: rx_x4_cl91_status0_synce_enum 4477 */ 4478 #define rx_x4_cl91_status0_synce_enum_SYNCE_NO_DIV 0 4479 #define rx_x4_cl91_status0_synce_enum_SYNCE_DIV_7 1 4480 #define rx_x4_cl91_status0_synce_enum_SYNCE_DIV_11 2 4481 4482 /**************************************************************************** 4483 * Enums: rx_x4_cl91_status0_synce_enum_stage0 4484 */ 4485 #define rx_x4_cl91_status0_synce_enum_stage0_SYNCE_NO_DIV 0 4486 #define rx_x4_cl91_status0_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 4487 #define rx_x4_cl91_status0_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 4488 4489 /**************************************************************************** 4490 * Enums: rx_x4_cl91_status0_cl91_sync_state 4491 */ 4492 #define rx_x4_cl91_status0_cl91_sync_state_FIND_1ST 0 4493 #define rx_x4_cl91_status0_cl91_sync_state_COUNT_NEXT 1 4494 #define rx_x4_cl91_status0_cl91_sync_state_COMP_2ND 2 4495 #define rx_x4_cl91_status0_cl91_sync_state_TWO_GOOD 3 4496 4497 /**************************************************************************** 4498 * Enums: rx_x4_cl91_status0_cl91_algn_state 4499 */ 4500 #define rx_x4_cl91_status0_cl91_algn_state_LOSS_OF_ALIGNMENT 0 4501 #define rx_x4_cl91_status0_cl91_algn_state_DESKEW 1 4502 #define rx_x4_cl91_status0_cl91_algn_state_DESKEW_FAIL 2 4503 #define rx_x4_cl91_status0_cl91_algn_state_ALIGN_ACQUIRED 3 4504 #define rx_x4_cl91_status0_cl91_algn_state_CW_GOOD 4 4505 #define rx_x4_cl91_status0_cl91_algn_state_CW_BAD 5 4506 #define rx_x4_cl91_status0_cl91_algn_state_THREE_BAD 6 4507 4508 /**************************************************************************** 4509 * Enums: rx_x4_cl91_status0_fec_sel_override 4510 */ 4511 #define rx_x4_cl91_status0_fec_sel_override_NO_OVERRIDE 0 4512 #define rx_x4_cl91_status0_fec_sel_override_NO_FEC 1 4513 #define rx_x4_cl91_status0_fec_sel_override_FEC_CL74 2 4514 #define rx_x4_cl91_status0_fec_sel_override_FEC_CL91 3 4515 4516 /**************************************************************************** 4517 * Enums: rx_x4_cl91_status0_cl91_blksync_mode 4518 */ 4519 #define rx_x4_cl91_status0_cl91_blksync_mode_R_BLKSYNC_NO_CL91_FEC 0 4520 #define rx_x4_cl91_status0_cl91_blksync_mode_R_BLKSYNC_CL91_QUAD_LANE_FEC 1 4521 #define rx_x4_cl91_status0_cl91_blksync_mode_R_BLKSYNC_CL91_DUAL_LANE_FEC 2 4522 #define rx_x4_cl91_status0_cl91_blksync_mode_R_BLKSYNC_CL91_SINGLE_LANE_FEC 3 4523 #define rx_x4_cl91_status0_cl91_blksync_mode_R_BLKSYNC_CL91_FC_FEC 4 4524 4525 /**************************************************************************** 4526 * Enums: rx_x4_cl91_status0_r_merge_mode 4527 */ 4528 #define rx_x4_cl91_status0_r_merge_mode_R_MERGE_MODE_BYPASS 0 4529 #define rx_x4_cl91_status0_r_merge_mode_R_MERGE_MODE_CL91_FC 1 4530 #define rx_x4_cl91_status0_r_merge_mode_R_MERGE_MODE_CL91_SINGLE_LANE 2 4531 #define rx_x4_cl91_status0_r_merge_mode_R_MERGE_MODE_CL91_DUAL_LANE 3 4532 #define rx_x4_cl91_status0_r_merge_mode_R_MERGE_MODE_CL91_QUAD_LANE 4 4533 4534 /**************************************************************************** 4535 * Enums: rx_x4_cl91_status0_r_tc_mode 4536 */ 4537 #define rx_x4_cl91_status0_r_tc_mode_R_TC_MODE_SINGLE 0 4538 #define rx_x4_cl91_status0_r_tc_mode_R_TC_MODE_DUAL 1 4539 #define rx_x4_cl91_status0_r_tc_mode_R_TC_MODE_QUAD 2 4540 4541 /**************************************************************************** 4542 * Enums: rx_x4_cl91_status0_r_tc_out_mode 4543 */ 4544 #define rx_x4_cl91_status0_r_tc_out_mode_R_TC_OUT_MODE_SINGLE 0 4545 #define rx_x4_cl91_status0_r_tc_out_mode_R_TC_OUT_MODE_DUAL 1 4546 #define rx_x4_cl91_status0_r_tc_out_mode_R_TC_OUT_MODE_QUAD 2 4547 4548 /**************************************************************************** 4549 * Enums: rx_x4_cl91_status0_cl91_fec_mode 4550 */ 4551 #define rx_x4_cl91_status0_cl91_fec_mode_NO_CL91_FEC 0 4552 #define rx_x4_cl91_status0_cl91_fec_mode_CL91_SINGLE_LANE_FC 1 4553 #define rx_x4_cl91_status0_cl91_fec_mode_CL91_SINGLE_LANE_BRCM_PROP 2 4554 #define rx_x4_cl91_status0_cl91_fec_mode_CL91_DUAL_LANE_BRCM_PROP 3 4555 #define rx_x4_cl91_status0_cl91_fec_mode_CL91_QUAD_LANE 4 4556 #define rx_x4_cl91_status0_cl91_fec_mode_IEEE_25G_CL91_SINGLE_LANE 5 4557 4558 /**************************************************************************** 4559 * Enums: rx_x4_cl91_status0_am_spacing_mul 4560 */ 4561 #define rx_x4_cl91_status0_am_spacing_mul_AM_SPACING_MUL_2 0 4562 #define rx_x4_cl91_status0_am_spacing_mul_AM_SPACING_MUL_4 1 4563 #define rx_x4_cl91_status0_am_spacing_mul_AM_SPACING_MUL_5 2 4564 #define rx_x4_cl91_status0_am_spacing_mul_AM_SPACING_MUL_20 3 4565 4566 /**************************************************************************** 4567 * Enums: rx_x4_cl91_status1_cl36TxEEEStates_l 4568 */ 4569 #define rx_x4_cl91_status1_cl36TxEEEStates_l_TX_REFRESH 8 4570 #define rx_x4_cl91_status1_cl36TxEEEStates_l_TX_QUIET 4 4571 #define rx_x4_cl91_status1_cl36TxEEEStates_l_TX_SLEEP 2 4572 #define rx_x4_cl91_status1_cl36TxEEEStates_l_TX_ACTIVE 1 4573 4574 /**************************************************************************** 4575 * Enums: rx_x4_cl91_status1_cl36TxEEEStates_c 4576 */ 4577 #define rx_x4_cl91_status1_cl36TxEEEStates_c_TX_REFRESH 3 4578 #define rx_x4_cl91_status1_cl36TxEEEStates_c_TX_QUIET 2 4579 #define rx_x4_cl91_status1_cl36TxEEEStates_c_TX_SLEEP 1 4580 #define rx_x4_cl91_status1_cl36TxEEEStates_c_TX_ACTIVE 0 4581 4582 /**************************************************************************** 4583 * Enums: rx_x4_cl91_status1_cl49TxEEEStates_l 4584 */ 4585 #define rx_x4_cl91_status1_cl49TxEEEStates_l_SCR_RESET_2 64 4586 #define rx_x4_cl91_status1_cl49TxEEEStates_l_SCR_RESET_1 32 4587 #define rx_x4_cl91_status1_cl49TxEEEStates_l_TX_WAKE 16 4588 #define rx_x4_cl91_status1_cl49TxEEEStates_l_TX_REFRESH 8 4589 #define rx_x4_cl91_status1_cl49TxEEEStates_l_TX_QUIET 4 4590 #define rx_x4_cl91_status1_cl49TxEEEStates_l_TX_SLEEP 2 4591 #define rx_x4_cl91_status1_cl49TxEEEStates_l_TX_ACTIVE 1 4592 4593 /**************************************************************************** 4594 * Enums: rx_x4_cl91_status1_fec_req_enum 4595 */ 4596 #define rx_x4_cl91_status1_fec_req_enum_FEC_not_supported 0 4597 #define rx_x4_cl91_status1_fec_req_enum_FEC_supported_but_not_requested 1 4598 #define rx_x4_cl91_status1_fec_req_enum_invalid_setting 2 4599 #define rx_x4_cl91_status1_fec_req_enum_FEC_supported_and_requested 3 4600 4601 /**************************************************************************** 4602 * Enums: rx_x4_cl91_status1_cl73_pause_enum 4603 */ 4604 #define rx_x4_cl91_status1_cl73_pause_enum_No_PAUSE_ability 0 4605 #define rx_x4_cl91_status1_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 4606 #define rx_x4_cl91_status1_cl73_pause_enum_Symmetric_PAUSE_ability 1 4607 #define rx_x4_cl91_status1_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 4608 4609 /**************************************************************************** 4610 * Enums: rx_x4_cl91_status1_cl49TxEEEStates_c 4611 */ 4612 #define rx_x4_cl91_status1_cl49TxEEEStates_c_SCR_RESET_2 6 4613 #define rx_x4_cl91_status1_cl49TxEEEStates_c_SCR_RESET_1 5 4614 #define rx_x4_cl91_status1_cl49TxEEEStates_c_TX_WAKE 4 4615 #define rx_x4_cl91_status1_cl49TxEEEStates_c_TX_REFRESH 3 4616 #define rx_x4_cl91_status1_cl49TxEEEStates_c_TX_QUIET 2 4617 #define rx_x4_cl91_status1_cl49TxEEEStates_c_TX_SLEEP 1 4618 #define rx_x4_cl91_status1_cl49TxEEEStates_c_TX_ACTIVE 0 4619 4620 /**************************************************************************** 4621 * Enums: rx_x4_cl91_status1_cl36RxEEEStates_l 4622 */ 4623 #define rx_x4_cl91_status1_cl36RxEEEStates_l_RX_LINK_FAIL 32 4624 #define rx_x4_cl91_status1_cl36RxEEEStates_l_RX_WTF 16 4625 #define rx_x4_cl91_status1_cl36RxEEEStates_l_RX_WAKE 8 4626 #define rx_x4_cl91_status1_cl36RxEEEStates_l_RX_QUIET 4 4627 #define rx_x4_cl91_status1_cl36RxEEEStates_l_RX_SLEEP 2 4628 #define rx_x4_cl91_status1_cl36RxEEEStates_l_RX_ACTIVE 1 4629 4630 /**************************************************************************** 4631 * Enums: rx_x4_cl91_status1_cl36RxEEEStates_c 4632 */ 4633 #define rx_x4_cl91_status1_cl36RxEEEStates_c_RX_LINK_FAIL 5 4634 #define rx_x4_cl91_status1_cl36RxEEEStates_c_RX_WTF 4 4635 #define rx_x4_cl91_status1_cl36RxEEEStates_c_RX_WAKE 3 4636 #define rx_x4_cl91_status1_cl36RxEEEStates_c_RX_QUIET 2 4637 #define rx_x4_cl91_status1_cl36RxEEEStates_c_RX_SLEEP 1 4638 #define rx_x4_cl91_status1_cl36RxEEEStates_c_RX_ACTIVE 0 4639 4640 /**************************************************************************** 4641 * Enums: rx_x4_cl91_status1_cl49RxEEEStates_l 4642 */ 4643 #define rx_x4_cl91_status1_cl49RxEEEStates_l_RX_LINK_FAIL 32 4644 #define rx_x4_cl91_status1_cl49RxEEEStates_l_RX_WTF 16 4645 #define rx_x4_cl91_status1_cl49RxEEEStates_l_RX_WAKE 8 4646 #define rx_x4_cl91_status1_cl49RxEEEStates_l_RX_QUIET 4 4647 #define rx_x4_cl91_status1_cl49RxEEEStates_l_RX_SLEEP 2 4648 #define rx_x4_cl91_status1_cl49RxEEEStates_l_RX_ACTIVE 1 4649 4650 /**************************************************************************** 4651 * Enums: rx_x4_cl91_status1_cl49RxEEEStates_c 4652 */ 4653 #define rx_x4_cl91_status1_cl49RxEEEStates_c_RX_LINK_FAIL 5 4654 #define rx_x4_cl91_status1_cl49RxEEEStates_c_RX_WTF 4 4655 #define rx_x4_cl91_status1_cl49RxEEEStates_c_RX_WAKE 3 4656 #define rx_x4_cl91_status1_cl49RxEEEStates_c_RX_QUIET 2 4657 #define rx_x4_cl91_status1_cl49RxEEEStates_c_RX_SLEEP 1 4658 #define rx_x4_cl91_status1_cl49RxEEEStates_c_RX_ACTIVE 0 4659 4660 /**************************************************************************** 4661 * Enums: rx_x4_cl91_status1_cl48TxEEEStates_l 4662 */ 4663 #define rx_x4_cl91_status1_cl48TxEEEStates_l_TX_REFRESH 8 4664 #define rx_x4_cl91_status1_cl48TxEEEStates_l_TX_QUIET 4 4665 #define rx_x4_cl91_status1_cl48TxEEEStates_l_TX_SLEEP 2 4666 #define rx_x4_cl91_status1_cl48TxEEEStates_l_TX_ACTIVE 1 4667 4668 /**************************************************************************** 4669 * Enums: rx_x4_cl91_status1_cl48TxEEEStates_c 4670 */ 4671 #define rx_x4_cl91_status1_cl48TxEEEStates_c_TX_REFRESH 3 4672 #define rx_x4_cl91_status1_cl48TxEEEStates_c_TX_QUIET 2 4673 #define rx_x4_cl91_status1_cl48TxEEEStates_c_TX_SLEEP 1 4674 #define rx_x4_cl91_status1_cl48TxEEEStates_c_TX_ACTIVE 0 4675 4676 /**************************************************************************** 4677 * Enums: rx_x4_cl91_status1_cl48RxEEEStates_l 4678 */ 4679 #define rx_x4_cl91_status1_cl48RxEEEStates_l_RX_LINK_FAIL 32 4680 #define rx_x4_cl91_status1_cl48RxEEEStates_l_RX_WAKE 16 4681 #define rx_x4_cl91_status1_cl48RxEEEStates_l_RX_QUIET 8 4682 #define rx_x4_cl91_status1_cl48RxEEEStates_l_RX_DEACT 4 4683 #define rx_x4_cl91_status1_cl48RxEEEStates_l_RX_SLEEP 2 4684 #define rx_x4_cl91_status1_cl48RxEEEStates_l_RX_ACTIVE 1 4685 4686 /**************************************************************************** 4687 * Enums: rx_x4_cl91_status1_cl48RxEEEStates_c 4688 */ 4689 #define rx_x4_cl91_status1_cl48RxEEEStates_c_RX_LINK_FAIL 5 4690 #define rx_x4_cl91_status1_cl48RxEEEStates_c_RX_WAKE 4 4691 #define rx_x4_cl91_status1_cl48RxEEEStates_c_RX_QUIET 3 4692 #define rx_x4_cl91_status1_cl48RxEEEStates_c_RX_DEACT 2 4693 #define rx_x4_cl91_status1_cl48RxEEEStates_c_RX_SLEEP 1 4694 #define rx_x4_cl91_status1_cl48RxEEEStates_c_RX_ACTIVE 0 4695 4696 /**************************************************************************** 4697 * Enums: rx_x4_cl91_status1_IQP_Options 4698 */ 4699 #define rx_x4_cl91_status1_IQP_Options_i50uA 0 4700 #define rx_x4_cl91_status1_IQP_Options_i100uA 1 4701 #define rx_x4_cl91_status1_IQP_Options_i150uA 2 4702 #define rx_x4_cl91_status1_IQP_Options_i200uA 3 4703 #define rx_x4_cl91_status1_IQP_Options_i250uA 4 4704 #define rx_x4_cl91_status1_IQP_Options_i300uA 5 4705 #define rx_x4_cl91_status1_IQP_Options_i350uA 6 4706 #define rx_x4_cl91_status1_IQP_Options_i400uA 7 4707 #define rx_x4_cl91_status1_IQP_Options_i450uA 8 4708 #define rx_x4_cl91_status1_IQP_Options_i500uA 9 4709 #define rx_x4_cl91_status1_IQP_Options_i550uA 10 4710 #define rx_x4_cl91_status1_IQP_Options_i600uA 11 4711 #define rx_x4_cl91_status1_IQP_Options_i650uA 12 4712 #define rx_x4_cl91_status1_IQP_Options_i700uA 13 4713 #define rx_x4_cl91_status1_IQP_Options_i750uA 14 4714 #define rx_x4_cl91_status1_IQP_Options_i800uA 15 4715 4716 /**************************************************************************** 4717 * Enums: rx_x4_cl91_status1_IDriver_Options 4718 */ 4719 #define rx_x4_cl91_status1_IDriver_Options_v680mV 0 4720 #define rx_x4_cl91_status1_IDriver_Options_v730mV 1 4721 #define rx_x4_cl91_status1_IDriver_Options_v780mV 2 4722 #define rx_x4_cl91_status1_IDriver_Options_v830mV 3 4723 #define rx_x4_cl91_status1_IDriver_Options_v880mV 4 4724 #define rx_x4_cl91_status1_IDriver_Options_v930mV 5 4725 #define rx_x4_cl91_status1_IDriver_Options_v980mV 6 4726 #define rx_x4_cl91_status1_IDriver_Options_v1010mV 7 4727 #define rx_x4_cl91_status1_IDriver_Options_v1040mV 8 4728 #define rx_x4_cl91_status1_IDriver_Options_v1060mV 9 4729 #define rx_x4_cl91_status1_IDriver_Options_v1070mV 10 4730 #define rx_x4_cl91_status1_IDriver_Options_v1080mV 11 4731 #define rx_x4_cl91_status1_IDriver_Options_v1085mV 12 4732 #define rx_x4_cl91_status1_IDriver_Options_v1090mV 13 4733 #define rx_x4_cl91_status1_IDriver_Options_v1095mV 14 4734 #define rx_x4_cl91_status1_IDriver_Options_v1100mV 15 4735 4736 /**************************************************************************** 4737 * Enums: rx_x4_cl91_status1_operationModes 4738 */ 4739 #define rx_x4_cl91_status1_operationModes_XGXS 0 4740 #define rx_x4_cl91_status1_operationModes_XGXG_nCC 1 4741 #define rx_x4_cl91_status1_operationModes_Indlane_OS8 4 4742 #define rx_x4_cl91_status1_operationModes_IndLane_OS5 5 4743 #define rx_x4_cl91_status1_operationModes_PCI 7 4744 #define rx_x4_cl91_status1_operationModes_XGXS_nLQ 8 4745 #define rx_x4_cl91_status1_operationModes_XGXS_nLQnCC 9 4746 #define rx_x4_cl91_status1_operationModes_PBypass 10 4747 #define rx_x4_cl91_status1_operationModes_PBypass_nDSK 11 4748 #define rx_x4_cl91_status1_operationModes_ComboCoreMode 12 4749 #define rx_x4_cl91_status1_operationModes_Clocks_off 15 4750 4751 /**************************************************************************** 4752 * Enums: rx_x4_cl91_status1_actualSpeeds 4753 */ 4754 #define rx_x4_cl91_status1_actualSpeeds_dr_10M 0 4755 #define rx_x4_cl91_status1_actualSpeeds_dr_100M 1 4756 #define rx_x4_cl91_status1_actualSpeeds_dr_1G 2 4757 #define rx_x4_cl91_status1_actualSpeeds_dr_2p5G 3 4758 #define rx_x4_cl91_status1_actualSpeeds_dr_5G_X4 4 4759 #define rx_x4_cl91_status1_actualSpeeds_dr_6G_X4 5 4760 #define rx_x4_cl91_status1_actualSpeeds_dr_10G_HiG 6 4761 #define rx_x4_cl91_status1_actualSpeeds_dr_10G_CX4 7 4762 #define rx_x4_cl91_status1_actualSpeeds_dr_12G_HiG 8 4763 #define rx_x4_cl91_status1_actualSpeeds_dr_12p5G_X4 9 4764 #define rx_x4_cl91_status1_actualSpeeds_dr_13G_X4 10 4765 #define rx_x4_cl91_status1_actualSpeeds_dr_15G_X4 11 4766 #define rx_x4_cl91_status1_actualSpeeds_dr_16G_X4 12 4767 #define rx_x4_cl91_status1_actualSpeeds_dr_1G_KX 13 4768 #define rx_x4_cl91_status1_actualSpeeds_dr_10G_KX4 14 4769 #define rx_x4_cl91_status1_actualSpeeds_dr_10G_KR 15 4770 #define rx_x4_cl91_status1_actualSpeeds_dr_5G 16 4771 #define rx_x4_cl91_status1_actualSpeeds_dr_6p4G 17 4772 #define rx_x4_cl91_status1_actualSpeeds_dr_20G_X4 18 4773 #define rx_x4_cl91_status1_actualSpeeds_dr_21G_X4 19 4774 #define rx_x4_cl91_status1_actualSpeeds_dr_25G_X4 20 4775 #define rx_x4_cl91_status1_actualSpeeds_dr_10G_HiG_DXGXS 21 4776 #define rx_x4_cl91_status1_actualSpeeds_dr_10G_DXGXS 22 4777 #define rx_x4_cl91_status1_actualSpeeds_dr_10p5G_HiG_DXGXS 23 4778 #define rx_x4_cl91_status1_actualSpeeds_dr_10p5G_DXGXS 24 4779 #define rx_x4_cl91_status1_actualSpeeds_dr_12p773G_HiG_DXGXS 25 4780 #define rx_x4_cl91_status1_actualSpeeds_dr_12p773G_DXGXS 26 4781 #define rx_x4_cl91_status1_actualSpeeds_dr_10G_XFI 27 4782 #define rx_x4_cl91_status1_actualSpeeds_dr_40G 28 4783 #define rx_x4_cl91_status1_actualSpeeds_dr_20G_HiG_DXGXS 29 4784 #define rx_x4_cl91_status1_actualSpeeds_dr_20G_DXGXS 30 4785 #define rx_x4_cl91_status1_actualSpeeds_dr_10G_SFI 31 4786 #define rx_x4_cl91_status1_actualSpeeds_dr_31p5G 32 4787 #define rx_x4_cl91_status1_actualSpeeds_dr_32p7G 33 4788 #define rx_x4_cl91_status1_actualSpeeds_dr_20G_SCR 34 4789 #define rx_x4_cl91_status1_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 4790 #define rx_x4_cl91_status1_actualSpeeds_dr_10G_DXGXS_SCR 36 4791 #define rx_x4_cl91_status1_actualSpeeds_dr_12G_R2 37 4792 #define rx_x4_cl91_status1_actualSpeeds_dr_10G_X2 38 4793 #define rx_x4_cl91_status1_actualSpeeds_dr_40G_KR4 39 4794 #define rx_x4_cl91_status1_actualSpeeds_dr_40G_CR4 40 4795 #define rx_x4_cl91_status1_actualSpeeds_dr_100G_CR10 41 4796 #define rx_x4_cl91_status1_actualSpeeds_dr_15p75G_DXGXS 44 4797 #define rx_x4_cl91_status1_actualSpeeds_dr_20G_KR2 57 4798 #define rx_x4_cl91_status1_actualSpeeds_dr_20G_CR2 58 4799 4800 /**************************************************************************** 4801 * Enums: rx_x4_cl91_status1_actualSpeedsMisc1 4802 */ 4803 #define rx_x4_cl91_status1_actualSpeedsMisc1_dr_2500BRCM_X1 16 4804 #define rx_x4_cl91_status1_actualSpeedsMisc1_dr_5000BRCM_X4 17 4805 #define rx_x4_cl91_status1_actualSpeedsMisc1_dr_6000BRCM_X4 18 4806 #define rx_x4_cl91_status1_actualSpeedsMisc1_dr_10GHiGig_X4 19 4807 #define rx_x4_cl91_status1_actualSpeedsMisc1_dr_10GBASE_CX4 20 4808 #define rx_x4_cl91_status1_actualSpeedsMisc1_dr_12GHiGig_X4 21 4809 #define rx_x4_cl91_status1_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 4810 #define rx_x4_cl91_status1_actualSpeedsMisc1_dr_13GHiGig_X4 23 4811 #define rx_x4_cl91_status1_actualSpeedsMisc1_dr_15GHiGig_X4 24 4812 #define rx_x4_cl91_status1_actualSpeedsMisc1_dr_16GHiGig_X4 25 4813 #define rx_x4_cl91_status1_actualSpeedsMisc1_dr_5000BRCM_X1 26 4814 #define rx_x4_cl91_status1_actualSpeedsMisc1_dr_6363BRCM_X1 27 4815 #define rx_x4_cl91_status1_actualSpeedsMisc1_dr_20GHiGig_X4 28 4816 #define rx_x4_cl91_status1_actualSpeedsMisc1_dr_21GHiGig_X4 29 4817 #define rx_x4_cl91_status1_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 4818 #define rx_x4_cl91_status1_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 4819 4820 /**************************************************************************** 4821 * Enums: rx_x4_cl91_status1_IndLaneModes 4822 */ 4823 #define rx_x4_cl91_status1_IndLaneModes_SWSDR_div2 0 4824 #define rx_x4_cl91_status1_IndLaneModes_SWSDR_div1 1 4825 #define rx_x4_cl91_status1_IndLaneModes_DWSDR_div2 2 4826 #define rx_x4_cl91_status1_IndLaneModes_DWSDR_div1 3 4827 4828 /**************************************************************************** 4829 * Enums: rx_x4_cl91_status1_prbsSelect 4830 */ 4831 #define rx_x4_cl91_status1_prbsSelect_prbs7 0 4832 #define rx_x4_cl91_status1_prbsSelect_prbs15 1 4833 #define rx_x4_cl91_status1_prbsSelect_prbs23 2 4834 #define rx_x4_cl91_status1_prbsSelect_prbs31 3 4835 4836 /**************************************************************************** 4837 * Enums: rx_x4_cl91_status1_vcoDivider 4838 */ 4839 #define rx_x4_cl91_status1_vcoDivider_div32 0 4840 #define rx_x4_cl91_status1_vcoDivider_div36 1 4841 #define rx_x4_cl91_status1_vcoDivider_div40 2 4842 #define rx_x4_cl91_status1_vcoDivider_div42 3 4843 #define rx_x4_cl91_status1_vcoDivider_div48 4 4844 #define rx_x4_cl91_status1_vcoDivider_div50 5 4845 #define rx_x4_cl91_status1_vcoDivider_div52 6 4846 #define rx_x4_cl91_status1_vcoDivider_div54 7 4847 #define rx_x4_cl91_status1_vcoDivider_div60 8 4848 #define rx_x4_cl91_status1_vcoDivider_div64 9 4849 #define rx_x4_cl91_status1_vcoDivider_div66 10 4850 #define rx_x4_cl91_status1_vcoDivider_div68 11 4851 #define rx_x4_cl91_status1_vcoDivider_div70 12 4852 #define rx_x4_cl91_status1_vcoDivider_div80 13 4853 #define rx_x4_cl91_status1_vcoDivider_div92 14 4854 #define rx_x4_cl91_status1_vcoDivider_div100 15 4855 4856 /**************************************************************************** 4857 * Enums: rx_x4_cl91_status1_refClkSelect 4858 */ 4859 #define rx_x4_cl91_status1_refClkSelect_clk_25MHz 0 4860 #define rx_x4_cl91_status1_refClkSelect_clk_100MHz 1 4861 #define rx_x4_cl91_status1_refClkSelect_clk_125MHz 2 4862 #define rx_x4_cl91_status1_refClkSelect_clk_156p25MHz 3 4863 #define rx_x4_cl91_status1_refClkSelect_clk_187p5MHz 4 4864 #define rx_x4_cl91_status1_refClkSelect_clk_161p25Mhz 5 4865 #define rx_x4_cl91_status1_refClkSelect_clk_50Mhz 6 4866 #define rx_x4_cl91_status1_refClkSelect_clk_106p25Mhz 7 4867 4868 /**************************************************************************** 4869 * Enums: rx_x4_cl91_status1_aerMMDdevTypeSelect 4870 */ 4871 #define rx_x4_cl91_status1_aerMMDdevTypeSelect_combo_core 0 4872 #define rx_x4_cl91_status1_aerMMDdevTypeSelect_PMA_PMD 1 4873 #define rx_x4_cl91_status1_aerMMDdevTypeSelect_PCS 3 4874 #define rx_x4_cl91_status1_aerMMDdevTypeSelect_PHY 4 4875 #define rx_x4_cl91_status1_aerMMDdevTypeSelect_DTE 5 4876 #define rx_x4_cl91_status1_aerMMDdevTypeSelect_CL73_AN 7 4877 4878 /**************************************************************************** 4879 * Enums: rx_x4_cl91_status1_aerMMDportSelect 4880 */ 4881 #define rx_x4_cl91_status1_aerMMDportSelect_ln0 0 4882 #define rx_x4_cl91_status1_aerMMDportSelect_ln1 1 4883 #define rx_x4_cl91_status1_aerMMDportSelect_ln2 2 4884 #define rx_x4_cl91_status1_aerMMDportSelect_ln3 3 4885 #define rx_x4_cl91_status1_aerMMDportSelect_BCST_ln0_1_2_3 511 4886 #define rx_x4_cl91_status1_aerMMDportSelect_BCST_ln0_1 512 4887 #define rx_x4_cl91_status1_aerMMDportSelect_BCST_ln2_3 513 4888 4889 /**************************************************************************** 4890 * Enums: rx_x4_cl91_status1_firmwareModeSelect 4891 */ 4892 #define rx_x4_cl91_status1_firmwareModeSelect_DEFAULT 0 4893 #define rx_x4_cl91_status1_firmwareModeSelect_SFP_OPT_LR 1 4894 #define rx_x4_cl91_status1_firmwareModeSelect_SFP_DAC 2 4895 #define rx_x4_cl91_status1_firmwareModeSelect_XLAUI 3 4896 #define rx_x4_cl91_status1_firmwareModeSelect_LONG_CH_6G 4 4897 4898 /**************************************************************************** 4899 * Enums: rx_x4_cl91_status1_tempIdxSelect 4900 */ 4901 #define rx_x4_cl91_status1_tempIdxSelect_LTE__22p9C 15 4902 #define rx_x4_cl91_status1_tempIdxSelect_LTE__12p6C 14 4903 #define rx_x4_cl91_status1_tempIdxSelect_LTE__3p0C 13 4904 #define rx_x4_cl91_status1_tempIdxSelect_LTE_6p7C 12 4905 #define rx_x4_cl91_status1_tempIdxSelect_LTE_16p4C 11 4906 #define rx_x4_cl91_status1_tempIdxSelect_LTE_26p6C 10 4907 #define rx_x4_cl91_status1_tempIdxSelect_LTE_36p3C 9 4908 #define rx_x4_cl91_status1_tempIdxSelect_LTE_46p0C 8 4909 #define rx_x4_cl91_status1_tempIdxSelect_LTE_56p2C 7 4910 #define rx_x4_cl91_status1_tempIdxSelect_LTE_65p9C 6 4911 #define rx_x4_cl91_status1_tempIdxSelect_LTE_75p6C 5 4912 #define rx_x4_cl91_status1_tempIdxSelect_LTE_85p3C 4 4913 #define rx_x4_cl91_status1_tempIdxSelect_LTE_95p5C 3 4914 #define rx_x4_cl91_status1_tempIdxSelect_LTE_105p2C 2 4915 #define rx_x4_cl91_status1_tempIdxSelect_LTE_114p9C 1 4916 #define rx_x4_cl91_status1_tempIdxSelect_LTE_125p1C 0 4917 4918 /**************************************************************************** 4919 * Enums: rx_x4_cl91_status1_port_mode 4920 */ 4921 #define rx_x4_cl91_status1_port_mode_QUAD_PORT 0 4922 #define rx_x4_cl91_status1_port_mode_TRI_1_PORT 1 4923 #define rx_x4_cl91_status1_port_mode_TRI_2_PORT 2 4924 #define rx_x4_cl91_status1_port_mode_DUAL_PORT 3 4925 #define rx_x4_cl91_status1_port_mode_SINGLE_PORT 4 4926 4927 /**************************************************************************** 4928 * Enums: rx_x4_cl91_status1_rev_letter_enum 4929 */ 4930 #define rx_x4_cl91_status1_rev_letter_enum_REV_A 0 4931 #define rx_x4_cl91_status1_rev_letter_enum_REV_B 1 4932 #define rx_x4_cl91_status1_rev_letter_enum_REV_C 2 4933 #define rx_x4_cl91_status1_rev_letter_enum_REV_D 3 4934 4935 /**************************************************************************** 4936 * Enums: rx_x4_cl91_status1_rev_number_enum 4937 */ 4938 #define rx_x4_cl91_status1_rev_number_enum_REV_0 0 4939 #define rx_x4_cl91_status1_rev_number_enum_REV_1 1 4940 #define rx_x4_cl91_status1_rev_number_enum_REV_2 2 4941 #define rx_x4_cl91_status1_rev_number_enum_REV_3 3 4942 #define rx_x4_cl91_status1_rev_number_enum_REV_4 4 4943 #define rx_x4_cl91_status1_rev_number_enum_REV_5 5 4944 #define rx_x4_cl91_status1_rev_number_enum_REV_6 6 4945 #define rx_x4_cl91_status1_rev_number_enum_REV_7 7 4946 4947 /**************************************************************************** 4948 * Enums: rx_x4_cl91_status1_bonding_enum 4949 */ 4950 #define rx_x4_cl91_status1_bonding_enum_WIRE_BOND 0 4951 #define rx_x4_cl91_status1_bonding_enum_FLIP_CHIP 1 4952 4953 /**************************************************************************** 4954 * Enums: rx_x4_cl91_status1_tech_process 4955 */ 4956 #define rx_x4_cl91_status1_tech_process_PROCESS_90NM 0 4957 #define rx_x4_cl91_status1_tech_process_PROCESS_65NM 1 4958 #define rx_x4_cl91_status1_tech_process_PROCESS_40NM 2 4959 #define rx_x4_cl91_status1_tech_process_PROCESS_28NM 3 4960 #define rx_x4_cl91_status1_tech_process_PROCESS_16NM 4 4961 4962 /**************************************************************************** 4963 * Enums: rx_x4_cl91_status1_model_num 4964 */ 4965 #define rx_x4_cl91_status1_model_num_SERDES_CL73 0 4966 #define rx_x4_cl91_status1_model_num_XGXS_16G 1 4967 #define rx_x4_cl91_status1_model_num_HYPERCORE 2 4968 #define rx_x4_cl91_status1_model_num_HYPERLITE 3 4969 #define rx_x4_cl91_status1_model_num_PCIE_G2_PIPE 4 4970 #define rx_x4_cl91_status1_model_num_SERDES_1p25GBd 5 4971 #define rx_x4_cl91_status1_model_num_SATA2 6 4972 #define rx_x4_cl91_status1_model_num_QSGMII 7 4973 #define rx_x4_cl91_status1_model_num_XGXS10G 8 4974 #define rx_x4_cl91_status1_model_num_WARPCORE 9 4975 #define rx_x4_cl91_status1_model_num_XFICORE 10 4976 #define rx_x4_cl91_status1_model_num_RXFI 11 4977 #define rx_x4_cl91_status1_model_num_WARPLITE 12 4978 #define rx_x4_cl91_status1_model_num_PENTACORE 13 4979 #define rx_x4_cl91_status1_model_num_ESM 14 4980 #define rx_x4_cl91_status1_model_num_QUAD_SGMII 15 4981 #define rx_x4_cl91_status1_model_num_WARPCORE_3 16 4982 #define rx_x4_cl91_status1_model_num_TSC 17 4983 #define rx_x4_cl91_status1_model_num_TSC4E 18 4984 #define rx_x4_cl91_status1_model_num_TSC12E 19 4985 #define rx_x4_cl91_status1_model_num_TSC4F 20 4986 #define rx_x4_cl91_status1_model_num_TSC4F_GEN2 21 4987 #define rx_x4_cl91_status1_model_num_XGXS_CL73_90NM 29 4988 #define rx_x4_cl91_status1_model_num_SERDES_CL73_90NM 30 4989 #define rx_x4_cl91_status1_model_num_WARPCORE3 32 4990 #define rx_x4_cl91_status1_model_num_WARPCORE4_TSC 33 4991 #define rx_x4_cl91_status1_model_num_RXAUI 34 4992 4993 /**************************************************************************** 4994 * Enums: rx_x4_cl91_status1_payload 4995 */ 4996 #define rx_x4_cl91_status1_payload_REPEAT_2_BYTES 0 4997 #define rx_x4_cl91_status1_payload_RAMPING 1 4998 #define rx_x4_cl91_status1_payload_CL48_CRPAT 2 4999 #define rx_x4_cl91_status1_payload_CL48_CJPAT 3 5000 #define rx_x4_cl91_status1_payload_CL36_LONG_CRPAT 4 5001 #define rx_x4_cl91_status1_payload_CL36_SHORT_CRPAT 5 5002 5003 /**************************************************************************** 5004 * Enums: rx_x4_cl91_status1_sc 5005 */ 5006 #define rx_x4_cl91_status1_sc_S_10G_CR1 0 5007 #define rx_x4_cl91_status1_sc_S_10G_KR1 1 5008 #define rx_x4_cl91_status1_sc_S_10G_X1 2 5009 #define rx_x4_cl91_status1_sc_S_10G_HG2_CR1 4 5010 #define rx_x4_cl91_status1_sc_S_10G_HG2_KR1 5 5011 #define rx_x4_cl91_status1_sc_S_10G_HG2_X1 6 5012 #define rx_x4_cl91_status1_sc_S_20G_CR1 8 5013 #define rx_x4_cl91_status1_sc_S_20G_KR1 9 5014 #define rx_x4_cl91_status1_sc_S_20G_X1 10 5015 #define rx_x4_cl91_status1_sc_S_20G_HG2_CR1 12 5016 #define rx_x4_cl91_status1_sc_S_20G_HG2_KR1 13 5017 #define rx_x4_cl91_status1_sc_S_20G_HG2_X1 14 5018 #define rx_x4_cl91_status1_sc_S_25G_CR1 16 5019 #define rx_x4_cl91_status1_sc_S_25G_KR1 17 5020 #define rx_x4_cl91_status1_sc_S_25G_X1 18 5021 #define rx_x4_cl91_status1_sc_S_25G_HG2_CR1 20 5022 #define rx_x4_cl91_status1_sc_S_25G_HG2_KR1 21 5023 #define rx_x4_cl91_status1_sc_S_25G_HG2_X1 22 5024 #define rx_x4_cl91_status1_sc_S_20G_CR2 24 5025 #define rx_x4_cl91_status1_sc_S_20G_KR2 25 5026 #define rx_x4_cl91_status1_sc_S_20G_X2 26 5027 #define rx_x4_cl91_status1_sc_S_20G_HG2_CR2 28 5028 #define rx_x4_cl91_status1_sc_S_20G_HG2_KR2 29 5029 #define rx_x4_cl91_status1_sc_S_20G_HG2_X2 30 5030 #define rx_x4_cl91_status1_sc_S_40G_CR2 32 5031 #define rx_x4_cl91_status1_sc_S_40G_KR2 33 5032 #define rx_x4_cl91_status1_sc_S_40G_X2 34 5033 #define rx_x4_cl91_status1_sc_S_40G_HG2_CR2 36 5034 #define rx_x4_cl91_status1_sc_S_40G_HG2_KR2 37 5035 #define rx_x4_cl91_status1_sc_S_40G_HG2_X2 38 5036 #define rx_x4_cl91_status1_sc_S_40G_CR4 40 5037 #define rx_x4_cl91_status1_sc_S_40G_KR4 41 5038 #define rx_x4_cl91_status1_sc_S_40G_X4 42 5039 #define rx_x4_cl91_status1_sc_S_40G_HG2_CR4 44 5040 #define rx_x4_cl91_status1_sc_S_40G_HG2_KR4 45 5041 #define rx_x4_cl91_status1_sc_S_40G_HG2_X4 46 5042 #define rx_x4_cl91_status1_sc_S_50G_CR2 48 5043 #define rx_x4_cl91_status1_sc_S_50G_KR2 49 5044 #define rx_x4_cl91_status1_sc_S_50G_X2 50 5045 #define rx_x4_cl91_status1_sc_S_50G_HG2_CR2 52 5046 #define rx_x4_cl91_status1_sc_S_50G_HG2_KR2 53 5047 #define rx_x4_cl91_status1_sc_S_50G_HG2_X2 54 5048 #define rx_x4_cl91_status1_sc_S_50G_CR4 56 5049 #define rx_x4_cl91_status1_sc_S_50G_KR4 57 5050 #define rx_x4_cl91_status1_sc_S_50G_X4 58 5051 #define rx_x4_cl91_status1_sc_S_50G_HG2_CR4 60 5052 #define rx_x4_cl91_status1_sc_S_50G_HG2_KR4 61 5053 #define rx_x4_cl91_status1_sc_S_50G_HG2_X4 62 5054 #define rx_x4_cl91_status1_sc_S_100G_CR4 64 5055 #define rx_x4_cl91_status1_sc_S_100G_KR4 65 5056 #define rx_x4_cl91_status1_sc_S_100G_X4 66 5057 #define rx_x4_cl91_status1_sc_S_100G_HG2_CR4 68 5058 #define rx_x4_cl91_status1_sc_S_100G_HG2_KR4 69 5059 #define rx_x4_cl91_status1_sc_S_100G_HG2_X4 70 5060 #define rx_x4_cl91_status1_sc_S_CL73_20GVCO 72 5061 #define rx_x4_cl91_status1_sc_S_CL73_25GVCO 80 5062 #define rx_x4_cl91_status1_sc_S_CL36_20GVCO 88 5063 #define rx_x4_cl91_status1_sc_S_CL36_25GVCO 96 5064 #define rx_x4_cl91_status1_sc_S_25G_CR_IEEE 112 5065 #define rx_x4_cl91_status1_sc_S_25G_CRS_IEEE 113 5066 #define rx_x4_cl91_status1_sc_S_25G_KR_IEEE 114 5067 #define rx_x4_cl91_status1_sc_S_25G_KRS_IEEE 115 5068 5069 /**************************************************************************** 5070 * Enums: rx_x4_cl91_status1_t_fifo_modes 5071 */ 5072 #define rx_x4_cl91_status1_t_fifo_modes_T_FIFO_INSERT_NO_AM 0 5073 #define rx_x4_cl91_status1_t_fifo_modes_T_FIFO_INSERT_4_AM 1 5074 #define rx_x4_cl91_status1_t_fifo_modes_T_FIFO_INSERT_20_AM 2 5075 #define rx_x4_cl91_status1_t_fifo_modes_T_FIFO_INSERT_2_AM 3 5076 5077 /**************************************************************************** 5078 * Enums: rx_x4_cl91_status1_t_enc_modes 5079 */ 5080 #define rx_x4_cl91_status1_t_enc_modes_T_ENC_MODE_BYPASS 0 5081 #define rx_x4_cl91_status1_t_enc_modes_T_ENC_MODE_CL49 1 5082 #define rx_x4_cl91_status1_t_enc_modes_T_ENC_MODE_CL82 2 5083 5084 /**************************************************************************** 5085 * Enums: rx_x4_cl91_status1_btmx_mode 5086 */ 5087 #define rx_x4_cl91_status1_btmx_mode_BS_BTMX_MODE_1to1 0 5088 #define rx_x4_cl91_status1_btmx_mode_BS_BTMX_MODE_2to1 1 5089 #define rx_x4_cl91_status1_btmx_mode_BS_BTMX_MODE_5to1 2 5090 5091 /**************************************************************************** 5092 * Enums: rx_x4_cl91_status1_t_type_cl82 5093 */ 5094 #define rx_x4_cl91_status1_t_type_cl82_T_TYPE_B1 5 5095 #define rx_x4_cl91_status1_t_type_cl82_T_TYPE_C 4 5096 #define rx_x4_cl91_status1_t_type_cl82_T_TYPE_S 3 5097 #define rx_x4_cl91_status1_t_type_cl82_T_TYPE_T 2 5098 #define rx_x4_cl91_status1_t_type_cl82_T_TYPE_D 1 5099 #define rx_x4_cl91_status1_t_type_cl82_T_TYPE_E 0 5100 5101 /**************************************************************************** 5102 * Enums: rx_x4_cl91_status1_txsm_state_cl82 5103 */ 5104 #define rx_x4_cl91_status1_txsm_state_cl82_TX_HIG_END 6 5105 #define rx_x4_cl91_status1_txsm_state_cl82_TX_HIG_START 5 5106 #define rx_x4_cl91_status1_txsm_state_cl82_TX_E 4 5107 #define rx_x4_cl91_status1_txsm_state_cl82_TX_T 3 5108 #define rx_x4_cl91_status1_txsm_state_cl82_TX_D 2 5109 #define rx_x4_cl91_status1_txsm_state_cl82_TX_C 1 5110 #define rx_x4_cl91_status1_txsm_state_cl82_TX_INIT 0 5111 5112 /**************************************************************************** 5113 * Enums: rx_x4_cl91_status1_ltxsm_state_cl82 5114 */ 5115 #define rx_x4_cl91_status1_ltxsm_state_cl82_TX_HIG_END 64 5116 #define rx_x4_cl91_status1_ltxsm_state_cl82_TX_HIG_START 32 5117 #define rx_x4_cl91_status1_ltxsm_state_cl82_TX_E 16 5118 #define rx_x4_cl91_status1_ltxsm_state_cl82_TX_T 8 5119 #define rx_x4_cl91_status1_ltxsm_state_cl82_TX_D 4 5120 #define rx_x4_cl91_status1_ltxsm_state_cl82_TX_C 2 5121 #define rx_x4_cl91_status1_ltxsm_state_cl82_TX_INIT 1 5122 5123 /**************************************************************************** 5124 * Enums: rx_x4_cl91_status1_r_type_coded_cl82 5125 */ 5126 #define rx_x4_cl91_status1_r_type_coded_cl82_R_TYPE_B1 32 5127 #define rx_x4_cl91_status1_r_type_coded_cl82_R_TYPE_C 16 5128 #define rx_x4_cl91_status1_r_type_coded_cl82_R_TYPE_S 8 5129 #define rx_x4_cl91_status1_r_type_coded_cl82_R_TYPE_T 4 5130 #define rx_x4_cl91_status1_r_type_coded_cl82_R_TYPE_D 2 5131 #define rx_x4_cl91_status1_r_type_coded_cl82_R_TYPE_E 1 5132 5133 /**************************************************************************** 5134 * Enums: rx_x4_cl91_status1_rxsm_state_cl82 5135 */ 5136 #define rx_x4_cl91_status1_rxsm_state_cl82_RX_HIG_END 64 5137 #define rx_x4_cl91_status1_rxsm_state_cl82_RX_HIG_START 32 5138 #define rx_x4_cl91_status1_rxsm_state_cl82_RX_E 16 5139 #define rx_x4_cl91_status1_rxsm_state_cl82_RX_T 8 5140 #define rx_x4_cl91_status1_rxsm_state_cl82_RX_D 4 5141 #define rx_x4_cl91_status1_rxsm_state_cl82_RX_C 2 5142 #define rx_x4_cl91_status1_rxsm_state_cl82_RX_INIT 1 5143 5144 /**************************************************************************** 5145 * Enums: rx_x4_cl91_status1_deskew_state 5146 */ 5147 #define rx_x4_cl91_status1_deskew_state_ALIGN_ACQUIRED 2 5148 #define rx_x4_cl91_status1_deskew_state_LOSS_OF_ALIGNMENT 1 5149 5150 /**************************************************************************** 5151 * Enums: rx_x4_cl91_status1_os_mode_enum 5152 */ 5153 #define rx_x4_cl91_status1_os_mode_enum_OS_MODE_1 0 5154 #define rx_x4_cl91_status1_os_mode_enum_OS_MODE_2 1 5155 #define rx_x4_cl91_status1_os_mode_enum_OS_MODE_4 2 5156 #define rx_x4_cl91_status1_os_mode_enum_OS_MODE_16p5 8 5157 #define rx_x4_cl91_status1_os_mode_enum_OS_MODE_20p625 12 5158 5159 /**************************************************************************** 5160 * Enums: rx_x4_cl91_status1_scr_modes 5161 */ 5162 #define rx_x4_cl91_status1_scr_modes_T_SCR_MODE_BYPASS 0 5163 #define rx_x4_cl91_status1_scr_modes_T_SCR_MODE_CL49 1 5164 #define rx_x4_cl91_status1_scr_modes_T_SCR_MODE_40G_2_LANE 2 5165 #define rx_x4_cl91_status1_scr_modes_T_SCR_MODE_100G 3 5166 #define rx_x4_cl91_status1_scr_modes_T_SCR_MODE_20G 4 5167 #define rx_x4_cl91_status1_scr_modes_T_SCR_MODE_40G_4_LANE 5 5168 5169 /**************************************************************************** 5170 * Enums: rx_x4_cl91_status1_descr_modes 5171 */ 5172 #define rx_x4_cl91_status1_descr_modes_R_DESCR_MODE_BYPASS 0 5173 #define rx_x4_cl91_status1_descr_modes_R_DESCR_MODE_CL49 1 5174 #define rx_x4_cl91_status1_descr_modes_R_DESCR_MODE_CL82 2 5175 5176 /**************************************************************************** 5177 * Enums: rx_x4_cl91_status1_r_dec_tl_mode 5178 */ 5179 #define rx_x4_cl91_status1_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 5180 #define rx_x4_cl91_status1_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 5181 #define rx_x4_cl91_status1_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 5182 5183 /**************************************************************************** 5184 * Enums: rx_x4_cl91_status1_r_dec_fsm_mode 5185 */ 5186 #define rx_x4_cl91_status1_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 5187 #define rx_x4_cl91_status1_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 5188 #define rx_x4_cl91_status1_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 5189 5190 /**************************************************************************** 5191 * Enums: rx_x4_cl91_status1_r_deskew_mode 5192 */ 5193 #define rx_x4_cl91_status1_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 5194 #define rx_x4_cl91_status1_r_deskew_mode_R_DESKEW_MODE_20G 1 5195 #define rx_x4_cl91_status1_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 5196 #define rx_x4_cl91_status1_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 5197 #define rx_x4_cl91_status1_r_deskew_mode_R_DESKEW_MODE_100G 4 5198 #define rx_x4_cl91_status1_r_deskew_mode_R_DESKEW_MODE_CL49 5 5199 #define rx_x4_cl91_status1_r_deskew_mode_R_DESKEW_MODE_CL91_QUAD 6 5200 #define rx_x4_cl91_status1_r_deskew_mode_R_DESKEW_MODE_CL91_SINGLE_BRCM 7 5201 #define rx_x4_cl91_status1_r_deskew_mode_R_DESKEW_MODE_CL91_DUAL_BRCM 8 5202 #define rx_x4_cl91_status1_r_deskew_mode_R_DESKEW_MODE_CL91_FC 9 5203 5204 /**************************************************************************** 5205 * Enums: rx_x4_cl91_status1_bs_dist_modes 5206 */ 5207 #define rx_x4_cl91_status1_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 5208 #define rx_x4_cl91_status1_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 5209 #define rx_x4_cl91_status1_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 5210 #define rx_x4_cl91_status1_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 5211 5212 /**************************************************************************** 5213 * Enums: rx_x4_cl91_status1_cl49_t_type 5214 */ 5215 #define rx_x4_cl91_status1_cl49_t_type_BAD_T_TYPE 15 5216 #define rx_x4_cl91_status1_cl49_t_type_T_TYPE_B0 11 5217 #define rx_x4_cl91_status1_cl49_t_type_T_TYPE_OB 10 5218 #define rx_x4_cl91_status1_cl49_t_type_T_TYPE_B1 9 5219 #define rx_x4_cl91_status1_cl49_t_type_T_TYPE_DB 8 5220 #define rx_x4_cl91_status1_cl49_t_type_T_TYPE_FC 7 5221 #define rx_x4_cl91_status1_cl49_t_type_T_TYPE_TB 6 5222 #define rx_x4_cl91_status1_cl49_t_type_T_TYPE_LI 5 5223 #define rx_x4_cl91_status1_cl49_t_type_T_TYPE_C 4 5224 #define rx_x4_cl91_status1_cl49_t_type_T_TYPE_S 3 5225 #define rx_x4_cl91_status1_cl49_t_type_T_TYPE_T 2 5226 #define rx_x4_cl91_status1_cl49_t_type_T_TYPE_D 1 5227 #define rx_x4_cl91_status1_cl49_t_type_T_TYPE_E 0 5228 5229 /**************************************************************************** 5230 * Enums: rx_x4_cl91_status1_cl49_txsm_states 5231 */ 5232 #define rx_x4_cl91_status1_cl49_txsm_states_TX_HIG_END 7 5233 #define rx_x4_cl91_status1_cl49_txsm_states_TX_HIG_START 6 5234 #define rx_x4_cl91_status1_cl49_txsm_states_TX_LI 5 5235 #define rx_x4_cl91_status1_cl49_txsm_states_TX_E 4 5236 #define rx_x4_cl91_status1_cl49_txsm_states_TX_T 3 5237 #define rx_x4_cl91_status1_cl49_txsm_states_TX_D 2 5238 #define rx_x4_cl91_status1_cl49_txsm_states_TX_C 1 5239 #define rx_x4_cl91_status1_cl49_txsm_states_TX_INIT 0 5240 5241 /**************************************************************************** 5242 * Enums: rx_x4_cl91_status1_cl49_ltxsm_states 5243 */ 5244 #define rx_x4_cl91_status1_cl49_ltxsm_states_TX_HIG_END 128 5245 #define rx_x4_cl91_status1_cl49_ltxsm_states_TX_HIG_START 64 5246 #define rx_x4_cl91_status1_cl49_ltxsm_states_TX_LI 32 5247 #define rx_x4_cl91_status1_cl49_ltxsm_states_TX_E 16 5248 #define rx_x4_cl91_status1_cl49_ltxsm_states_TX_T 8 5249 #define rx_x4_cl91_status1_cl49_ltxsm_states_TX_D 4 5250 #define rx_x4_cl91_status1_cl49_ltxsm_states_TX_C 2 5251 #define rx_x4_cl91_status1_cl49_ltxsm_states_TX_INIT 1 5252 5253 /**************************************************************************** 5254 * Enums: rx_x4_cl91_status1_burst_error_mode 5255 */ 5256 #define rx_x4_cl91_status1_burst_error_mode_BURST_ERROR_11_BITS 0 5257 #define rx_x4_cl91_status1_burst_error_mode_BURST_ERROR_16_BITS 1 5258 #define rx_x4_cl91_status1_burst_error_mode_BURST_ERROR_17_BITS 2 5259 #define rx_x4_cl91_status1_burst_error_mode_BURST_ERROR_18_BITS 3 5260 #define rx_x4_cl91_status1_burst_error_mode_BURST_ERROR_19_BITS 4 5261 #define rx_x4_cl91_status1_burst_error_mode_BURST_ERROR_20_BITS 5 5262 #define rx_x4_cl91_status1_burst_error_mode_BURST_ERROR_21_BITS 6 5263 #define rx_x4_cl91_status1_burst_error_mode_BURST_ERROR_22_BITS 7 5264 #define rx_x4_cl91_status1_burst_error_mode_BURST_ERROR_23_BITS 8 5265 #define rx_x4_cl91_status1_burst_error_mode_BURST_ERROR_24_BITS 9 5266 #define rx_x4_cl91_status1_burst_error_mode_BURST_ERROR_25_BITS 10 5267 #define rx_x4_cl91_status1_burst_error_mode_BURST_ERROR_26_BITS 11 5268 #define rx_x4_cl91_status1_burst_error_mode_BURST_ERROR_27_BITS 12 5269 #define rx_x4_cl91_status1_burst_error_mode_BURST_ERROR_28_BITS 13 5270 #define rx_x4_cl91_status1_burst_error_mode_BURST_ERROR_29_BITS 14 5271 #define rx_x4_cl91_status1_burst_error_mode_BURST_ERROR_30_BITS 15 5272 #define rx_x4_cl91_status1_burst_error_mode_BURST_ERROR_31_BITS 16 5273 #define rx_x4_cl91_status1_burst_error_mode_BURST_ERROR_32_BITS 17 5274 #define rx_x4_cl91_status1_burst_error_mode_BURST_ERROR_33_BITS 18 5275 #define rx_x4_cl91_status1_burst_error_mode_BURST_ERROR_34_BITS 19 5276 #define rx_x4_cl91_status1_burst_error_mode_BURST_ERROR_35_BITS 20 5277 #define rx_x4_cl91_status1_burst_error_mode_BURST_ERROR_36_BITS 21 5278 #define rx_x4_cl91_status1_burst_error_mode_BURST_ERROR_37_BITS 22 5279 #define rx_x4_cl91_status1_burst_error_mode_BURST_ERROR_38_BITS 23 5280 #define rx_x4_cl91_status1_burst_error_mode_BURST_ERROR_39_BITS 24 5281 #define rx_x4_cl91_status1_burst_error_mode_BURST_ERROR_40_BITS 25 5282 #define rx_x4_cl91_status1_burst_error_mode_BURST_ERROR_41_BITS 26 5283 5284 /**************************************************************************** 5285 * Enums: rx_x4_cl91_status1_bermon_state 5286 */ 5287 #define rx_x4_cl91_status1_bermon_state_HI_BER 4 5288 #define rx_x4_cl91_status1_bermon_state_GOOD_BER 3 5289 #define rx_x4_cl91_status1_bermon_state_BER_TEST_SH 2 5290 #define rx_x4_cl91_status1_bermon_state_START_TIMER 1 5291 #define rx_x4_cl91_status1_bermon_state_BER_MT_INIT 0 5292 5293 /**************************************************************************** 5294 * Enums: rx_x4_cl91_status1_rxsm_state_cl49 5295 */ 5296 #define rx_x4_cl91_status1_rxsm_state_cl49_RX_HIG_END 128 5297 #define rx_x4_cl91_status1_rxsm_state_cl49_RX_HIG_START 64 5298 #define rx_x4_cl91_status1_rxsm_state_cl49_RX_LI 32 5299 #define rx_x4_cl91_status1_rxsm_state_cl49_RX_E 16 5300 #define rx_x4_cl91_status1_rxsm_state_cl49_RX_T 8 5301 #define rx_x4_cl91_status1_rxsm_state_cl49_RX_D 4 5302 #define rx_x4_cl91_status1_rxsm_state_cl49_RX_C 2 5303 #define rx_x4_cl91_status1_rxsm_state_cl49_RX_INIT 1 5304 5305 /**************************************************************************** 5306 * Enums: rx_x4_cl91_status1_r_type 5307 */ 5308 #define rx_x4_cl91_status1_r_type_BAD_R_TYPE 15 5309 #define rx_x4_cl91_status1_r_type_R_TYPE_B0 11 5310 #define rx_x4_cl91_status1_r_type_R_TYPE_OB 10 5311 #define rx_x4_cl91_status1_r_type_R_TYPE_B1 9 5312 #define rx_x4_cl91_status1_r_type_R_TYPE_DB 8 5313 #define rx_x4_cl91_status1_r_type_R_TYPE_FC 7 5314 #define rx_x4_cl91_status1_r_type_R_TYPE_TB 6 5315 #define rx_x4_cl91_status1_r_type_R_TYPE_LI 5 5316 #define rx_x4_cl91_status1_r_type_R_TYPE_C 4 5317 #define rx_x4_cl91_status1_r_type_R_TYPE_S 3 5318 #define rx_x4_cl91_status1_r_type_R_TYPE_T 2 5319 #define rx_x4_cl91_status1_r_type_R_TYPE_D 1 5320 #define rx_x4_cl91_status1_r_type_R_TYPE_E 0 5321 5322 /**************************************************************************** 5323 * Enums: rx_x4_cl91_status1_am_lock_state 5324 */ 5325 #define rx_x4_cl91_status1_am_lock_state_INVALID_AM 512 5326 #define rx_x4_cl91_status1_am_lock_state_GOOD_AM 256 5327 #define rx_x4_cl91_status1_am_lock_state_COMP_AM 128 5328 #define rx_x4_cl91_status1_am_lock_state_TIMER_2 64 5329 #define rx_x4_cl91_status1_am_lock_state_AM_2_GOOD 32 5330 #define rx_x4_cl91_status1_am_lock_state_COMP_2ND 16 5331 #define rx_x4_cl91_status1_am_lock_state_TIMER_1 8 5332 #define rx_x4_cl91_status1_am_lock_state_FIND_1ST 4 5333 #define rx_x4_cl91_status1_am_lock_state_AM_RESET_CNT 2 5334 #define rx_x4_cl91_status1_am_lock_state_AM_LOCK_INIT 1 5335 5336 /**************************************************************************** 5337 * Enums: rx_x4_cl91_status1_msg_selector 5338 */ 5339 #define rx_x4_cl91_status1_msg_selector_RESERVED 0 5340 #define rx_x4_cl91_status1_msg_selector_VALUE_802p3 1 5341 #define rx_x4_cl91_status1_msg_selector_VALUE_802p9 2 5342 #define rx_x4_cl91_status1_msg_selector_VALUE_802p5 3 5343 #define rx_x4_cl91_status1_msg_selector_VALUE_1394 4 5344 5345 /**************************************************************************** 5346 * Enums: rx_x4_cl91_status1_synce_enum 5347 */ 5348 #define rx_x4_cl91_status1_synce_enum_SYNCE_NO_DIV 0 5349 #define rx_x4_cl91_status1_synce_enum_SYNCE_DIV_7 1 5350 #define rx_x4_cl91_status1_synce_enum_SYNCE_DIV_11 2 5351 5352 /**************************************************************************** 5353 * Enums: rx_x4_cl91_status1_synce_enum_stage0 5354 */ 5355 #define rx_x4_cl91_status1_synce_enum_stage0_SYNCE_NO_DIV 0 5356 #define rx_x4_cl91_status1_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 5357 #define rx_x4_cl91_status1_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 5358 5359 /**************************************************************************** 5360 * Enums: rx_x4_cl91_status1_cl91_sync_state 5361 */ 5362 #define rx_x4_cl91_status1_cl91_sync_state_FIND_1ST 0 5363 #define rx_x4_cl91_status1_cl91_sync_state_COUNT_NEXT 1 5364 #define rx_x4_cl91_status1_cl91_sync_state_COMP_2ND 2 5365 #define rx_x4_cl91_status1_cl91_sync_state_TWO_GOOD 3 5366 5367 /**************************************************************************** 5368 * Enums: rx_x4_cl91_status1_cl91_algn_state 5369 */ 5370 #define rx_x4_cl91_status1_cl91_algn_state_LOSS_OF_ALIGNMENT 0 5371 #define rx_x4_cl91_status1_cl91_algn_state_DESKEW 1 5372 #define rx_x4_cl91_status1_cl91_algn_state_DESKEW_FAIL 2 5373 #define rx_x4_cl91_status1_cl91_algn_state_ALIGN_ACQUIRED 3 5374 #define rx_x4_cl91_status1_cl91_algn_state_CW_GOOD 4 5375 #define rx_x4_cl91_status1_cl91_algn_state_CW_BAD 5 5376 #define rx_x4_cl91_status1_cl91_algn_state_THREE_BAD 6 5377 5378 /**************************************************************************** 5379 * Enums: rx_x4_cl91_status1_fec_sel_override 5380 */ 5381 #define rx_x4_cl91_status1_fec_sel_override_NO_OVERRIDE 0 5382 #define rx_x4_cl91_status1_fec_sel_override_NO_FEC 1 5383 #define rx_x4_cl91_status1_fec_sel_override_FEC_CL74 2 5384 #define rx_x4_cl91_status1_fec_sel_override_FEC_CL91 3 5385 5386 /**************************************************************************** 5387 * Enums: rx_x4_cl91_status1_cl91_blksync_mode 5388 */ 5389 #define rx_x4_cl91_status1_cl91_blksync_mode_R_BLKSYNC_NO_CL91_FEC 0 5390 #define rx_x4_cl91_status1_cl91_blksync_mode_R_BLKSYNC_CL91_QUAD_LANE_FEC 1 5391 #define rx_x4_cl91_status1_cl91_blksync_mode_R_BLKSYNC_CL91_DUAL_LANE_FEC 2 5392 #define rx_x4_cl91_status1_cl91_blksync_mode_R_BLKSYNC_CL91_SINGLE_LANE_FEC 3 5393 #define rx_x4_cl91_status1_cl91_blksync_mode_R_BLKSYNC_CL91_FC_FEC 4 5394 5395 /**************************************************************************** 5396 * Enums: rx_x4_cl91_status1_r_merge_mode 5397 */ 5398 #define rx_x4_cl91_status1_r_merge_mode_R_MERGE_MODE_BYPASS 0 5399 #define rx_x4_cl91_status1_r_merge_mode_R_MERGE_MODE_CL91_FC 1 5400 #define rx_x4_cl91_status1_r_merge_mode_R_MERGE_MODE_CL91_SINGLE_LANE 2 5401 #define rx_x4_cl91_status1_r_merge_mode_R_MERGE_MODE_CL91_DUAL_LANE 3 5402 #define rx_x4_cl91_status1_r_merge_mode_R_MERGE_MODE_CL91_QUAD_LANE 4 5403 5404 /**************************************************************************** 5405 * Enums: rx_x4_cl91_status1_r_tc_mode 5406 */ 5407 #define rx_x4_cl91_status1_r_tc_mode_R_TC_MODE_SINGLE 0 5408 #define rx_x4_cl91_status1_r_tc_mode_R_TC_MODE_DUAL 1 5409 #define rx_x4_cl91_status1_r_tc_mode_R_TC_MODE_QUAD 2 5410 5411 /**************************************************************************** 5412 * Enums: rx_x4_cl91_status1_r_tc_out_mode 5413 */ 5414 #define rx_x4_cl91_status1_r_tc_out_mode_R_TC_OUT_MODE_SINGLE 0 5415 #define rx_x4_cl91_status1_r_tc_out_mode_R_TC_OUT_MODE_DUAL 1 5416 #define rx_x4_cl91_status1_r_tc_out_mode_R_TC_OUT_MODE_QUAD 2 5417 5418 /**************************************************************************** 5419 * Enums: rx_x4_cl91_status1_cl91_fec_mode 5420 */ 5421 #define rx_x4_cl91_status1_cl91_fec_mode_NO_CL91_FEC 0 5422 #define rx_x4_cl91_status1_cl91_fec_mode_CL91_SINGLE_LANE_FC 1 5423 #define rx_x4_cl91_status1_cl91_fec_mode_CL91_SINGLE_LANE_BRCM_PROP 2 5424 #define rx_x4_cl91_status1_cl91_fec_mode_CL91_DUAL_LANE_BRCM_PROP 3 5425 #define rx_x4_cl91_status1_cl91_fec_mode_CL91_QUAD_LANE 4 5426 #define rx_x4_cl91_status1_cl91_fec_mode_IEEE_25G_CL91_SINGLE_LANE 5 5427 5428 /**************************************************************************** 5429 * Enums: rx_x4_cl91_status1_am_spacing_mul 5430 */ 5431 #define rx_x4_cl91_status1_am_spacing_mul_AM_SPACING_MUL_2 0 5432 #define rx_x4_cl91_status1_am_spacing_mul_AM_SPACING_MUL_4 1 5433 #define rx_x4_cl91_status1_am_spacing_mul_AM_SPACING_MUL_5 2 5434 #define rx_x4_cl91_status1_am_spacing_mul_AM_SPACING_MUL_20 3 5435 5436 /**************************************************************************** 5437 * Enums: rx_x4_control0_cl36TxEEEStates_l 5438 */ 5439 #define rx_x4_control0_cl36TxEEEStates_l_TX_REFRESH 8 5440 #define rx_x4_control0_cl36TxEEEStates_l_TX_QUIET 4 5441 #define rx_x4_control0_cl36TxEEEStates_l_TX_SLEEP 2 5442 #define rx_x4_control0_cl36TxEEEStates_l_TX_ACTIVE 1 5443 5444 /**************************************************************************** 5445 * Enums: rx_x4_control0_cl36TxEEEStates_c 5446 */ 5447 #define rx_x4_control0_cl36TxEEEStates_c_TX_REFRESH 3 5448 #define rx_x4_control0_cl36TxEEEStates_c_TX_QUIET 2 5449 #define rx_x4_control0_cl36TxEEEStates_c_TX_SLEEP 1 5450 #define rx_x4_control0_cl36TxEEEStates_c_TX_ACTIVE 0 5451 5452 /**************************************************************************** 5453 * Enums: rx_x4_control0_cl49TxEEEStates_l 5454 */ 5455 #define rx_x4_control0_cl49TxEEEStates_l_SCR_RESET_2 64 5456 #define rx_x4_control0_cl49TxEEEStates_l_SCR_RESET_1 32 5457 #define rx_x4_control0_cl49TxEEEStates_l_TX_WAKE 16 5458 #define rx_x4_control0_cl49TxEEEStates_l_TX_REFRESH 8 5459 #define rx_x4_control0_cl49TxEEEStates_l_TX_QUIET 4 5460 #define rx_x4_control0_cl49TxEEEStates_l_TX_SLEEP 2 5461 #define rx_x4_control0_cl49TxEEEStates_l_TX_ACTIVE 1 5462 5463 /**************************************************************************** 5464 * Enums: rx_x4_control0_fec_req_enum 5465 */ 5466 #define rx_x4_control0_fec_req_enum_FEC_not_supported 0 5467 #define rx_x4_control0_fec_req_enum_FEC_supported_but_not_requested 1 5468 #define rx_x4_control0_fec_req_enum_invalid_setting 2 5469 #define rx_x4_control0_fec_req_enum_FEC_supported_and_requested 3 5470 5471 /**************************************************************************** 5472 * Enums: rx_x4_control0_cl73_pause_enum 5473 */ 5474 #define rx_x4_control0_cl73_pause_enum_No_PAUSE_ability 0 5475 #define rx_x4_control0_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 5476 #define rx_x4_control0_cl73_pause_enum_Symmetric_PAUSE_ability 1 5477 #define rx_x4_control0_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 5478 5479 /**************************************************************************** 5480 * Enums: rx_x4_control0_cl49TxEEEStates_c 5481 */ 5482 #define rx_x4_control0_cl49TxEEEStates_c_SCR_RESET_2 6 5483 #define rx_x4_control0_cl49TxEEEStates_c_SCR_RESET_1 5 5484 #define rx_x4_control0_cl49TxEEEStates_c_TX_WAKE 4 5485 #define rx_x4_control0_cl49TxEEEStates_c_TX_REFRESH 3 5486 #define rx_x4_control0_cl49TxEEEStates_c_TX_QUIET 2 5487 #define rx_x4_control0_cl49TxEEEStates_c_TX_SLEEP 1 5488 #define rx_x4_control0_cl49TxEEEStates_c_TX_ACTIVE 0 5489 5490 /**************************************************************************** 5491 * Enums: rx_x4_control0_cl36RxEEEStates_l 5492 */ 5493 #define rx_x4_control0_cl36RxEEEStates_l_RX_LINK_FAIL 32 5494 #define rx_x4_control0_cl36RxEEEStates_l_RX_WTF 16 5495 #define rx_x4_control0_cl36RxEEEStates_l_RX_WAKE 8 5496 #define rx_x4_control0_cl36RxEEEStates_l_RX_QUIET 4 5497 #define rx_x4_control0_cl36RxEEEStates_l_RX_SLEEP 2 5498 #define rx_x4_control0_cl36RxEEEStates_l_RX_ACTIVE 1 5499 5500 /**************************************************************************** 5501 * Enums: rx_x4_control0_cl36RxEEEStates_c 5502 */ 5503 #define rx_x4_control0_cl36RxEEEStates_c_RX_LINK_FAIL 5 5504 #define rx_x4_control0_cl36RxEEEStates_c_RX_WTF 4 5505 #define rx_x4_control0_cl36RxEEEStates_c_RX_WAKE 3 5506 #define rx_x4_control0_cl36RxEEEStates_c_RX_QUIET 2 5507 #define rx_x4_control0_cl36RxEEEStates_c_RX_SLEEP 1 5508 #define rx_x4_control0_cl36RxEEEStates_c_RX_ACTIVE 0 5509 5510 /**************************************************************************** 5511 * Enums: rx_x4_control0_cl49RxEEEStates_l 5512 */ 5513 #define rx_x4_control0_cl49RxEEEStates_l_RX_LINK_FAIL 32 5514 #define rx_x4_control0_cl49RxEEEStates_l_RX_WTF 16 5515 #define rx_x4_control0_cl49RxEEEStates_l_RX_WAKE 8 5516 #define rx_x4_control0_cl49RxEEEStates_l_RX_QUIET 4 5517 #define rx_x4_control0_cl49RxEEEStates_l_RX_SLEEP 2 5518 #define rx_x4_control0_cl49RxEEEStates_l_RX_ACTIVE 1 5519 5520 /**************************************************************************** 5521 * Enums: rx_x4_control0_cl49RxEEEStates_c 5522 */ 5523 #define rx_x4_control0_cl49RxEEEStates_c_RX_LINK_FAIL 5 5524 #define rx_x4_control0_cl49RxEEEStates_c_RX_WTF 4 5525 #define rx_x4_control0_cl49RxEEEStates_c_RX_WAKE 3 5526 #define rx_x4_control0_cl49RxEEEStates_c_RX_QUIET 2 5527 #define rx_x4_control0_cl49RxEEEStates_c_RX_SLEEP 1 5528 #define rx_x4_control0_cl49RxEEEStates_c_RX_ACTIVE 0 5529 5530 /**************************************************************************** 5531 * Enums: rx_x4_control0_cl48TxEEEStates_l 5532 */ 5533 #define rx_x4_control0_cl48TxEEEStates_l_TX_REFRESH 8 5534 #define rx_x4_control0_cl48TxEEEStates_l_TX_QUIET 4 5535 #define rx_x4_control0_cl48TxEEEStates_l_TX_SLEEP 2 5536 #define rx_x4_control0_cl48TxEEEStates_l_TX_ACTIVE 1 5537 5538 /**************************************************************************** 5539 * Enums: rx_x4_control0_cl48TxEEEStates_c 5540 */ 5541 #define rx_x4_control0_cl48TxEEEStates_c_TX_REFRESH 3 5542 #define rx_x4_control0_cl48TxEEEStates_c_TX_QUIET 2 5543 #define rx_x4_control0_cl48TxEEEStates_c_TX_SLEEP 1 5544 #define rx_x4_control0_cl48TxEEEStates_c_TX_ACTIVE 0 5545 5546 /**************************************************************************** 5547 * Enums: rx_x4_control0_cl48RxEEEStates_l 5548 */ 5549 #define rx_x4_control0_cl48RxEEEStates_l_RX_LINK_FAIL 32 5550 #define rx_x4_control0_cl48RxEEEStates_l_RX_WAKE 16 5551 #define rx_x4_control0_cl48RxEEEStates_l_RX_QUIET 8 5552 #define rx_x4_control0_cl48RxEEEStates_l_RX_DEACT 4 5553 #define rx_x4_control0_cl48RxEEEStates_l_RX_SLEEP 2 5554 #define rx_x4_control0_cl48RxEEEStates_l_RX_ACTIVE 1 5555 5556 /**************************************************************************** 5557 * Enums: rx_x4_control0_cl48RxEEEStates_c 5558 */ 5559 #define rx_x4_control0_cl48RxEEEStates_c_RX_LINK_FAIL 5 5560 #define rx_x4_control0_cl48RxEEEStates_c_RX_WAKE 4 5561 #define rx_x4_control0_cl48RxEEEStates_c_RX_QUIET 3 5562 #define rx_x4_control0_cl48RxEEEStates_c_RX_DEACT 2 5563 #define rx_x4_control0_cl48RxEEEStates_c_RX_SLEEP 1 5564 #define rx_x4_control0_cl48RxEEEStates_c_RX_ACTIVE 0 5565 5566 /**************************************************************************** 5567 * Enums: rx_x4_control0_IQP_Options 5568 */ 5569 #define rx_x4_control0_IQP_Options_i50uA 0 5570 #define rx_x4_control0_IQP_Options_i100uA 1 5571 #define rx_x4_control0_IQP_Options_i150uA 2 5572 #define rx_x4_control0_IQP_Options_i200uA 3 5573 #define rx_x4_control0_IQP_Options_i250uA 4 5574 #define rx_x4_control0_IQP_Options_i300uA 5 5575 #define rx_x4_control0_IQP_Options_i350uA 6 5576 #define rx_x4_control0_IQP_Options_i400uA 7 5577 #define rx_x4_control0_IQP_Options_i450uA 8 5578 #define rx_x4_control0_IQP_Options_i500uA 9 5579 #define rx_x4_control0_IQP_Options_i550uA 10 5580 #define rx_x4_control0_IQP_Options_i600uA 11 5581 #define rx_x4_control0_IQP_Options_i650uA 12 5582 #define rx_x4_control0_IQP_Options_i700uA 13 5583 #define rx_x4_control0_IQP_Options_i750uA 14 5584 #define rx_x4_control0_IQP_Options_i800uA 15 5585 5586 /**************************************************************************** 5587 * Enums: rx_x4_control0_IDriver_Options 5588 */ 5589 #define rx_x4_control0_IDriver_Options_v680mV 0 5590 #define rx_x4_control0_IDriver_Options_v730mV 1 5591 #define rx_x4_control0_IDriver_Options_v780mV 2 5592 #define rx_x4_control0_IDriver_Options_v830mV 3 5593 #define rx_x4_control0_IDriver_Options_v880mV 4 5594 #define rx_x4_control0_IDriver_Options_v930mV 5 5595 #define rx_x4_control0_IDriver_Options_v980mV 6 5596 #define rx_x4_control0_IDriver_Options_v1010mV 7 5597 #define rx_x4_control0_IDriver_Options_v1040mV 8 5598 #define rx_x4_control0_IDriver_Options_v1060mV 9 5599 #define rx_x4_control0_IDriver_Options_v1070mV 10 5600 #define rx_x4_control0_IDriver_Options_v1080mV 11 5601 #define rx_x4_control0_IDriver_Options_v1085mV 12 5602 #define rx_x4_control0_IDriver_Options_v1090mV 13 5603 #define rx_x4_control0_IDriver_Options_v1095mV 14 5604 #define rx_x4_control0_IDriver_Options_v1100mV 15 5605 5606 /**************************************************************************** 5607 * Enums: rx_x4_control0_operationModes 5608 */ 5609 #define rx_x4_control0_operationModes_XGXS 0 5610 #define rx_x4_control0_operationModes_XGXG_nCC 1 5611 #define rx_x4_control0_operationModes_Indlane_OS8 4 5612 #define rx_x4_control0_operationModes_IndLane_OS5 5 5613 #define rx_x4_control0_operationModes_PCI 7 5614 #define rx_x4_control0_operationModes_XGXS_nLQ 8 5615 #define rx_x4_control0_operationModes_XGXS_nLQnCC 9 5616 #define rx_x4_control0_operationModes_PBypass 10 5617 #define rx_x4_control0_operationModes_PBypass_nDSK 11 5618 #define rx_x4_control0_operationModes_ComboCoreMode 12 5619 #define rx_x4_control0_operationModes_Clocks_off 15 5620 5621 /**************************************************************************** 5622 * Enums: rx_x4_control0_actualSpeeds 5623 */ 5624 #define rx_x4_control0_actualSpeeds_dr_10M 0 5625 #define rx_x4_control0_actualSpeeds_dr_100M 1 5626 #define rx_x4_control0_actualSpeeds_dr_1G 2 5627 #define rx_x4_control0_actualSpeeds_dr_2p5G 3 5628 #define rx_x4_control0_actualSpeeds_dr_5G_X4 4 5629 #define rx_x4_control0_actualSpeeds_dr_6G_X4 5 5630 #define rx_x4_control0_actualSpeeds_dr_10G_HiG 6 5631 #define rx_x4_control0_actualSpeeds_dr_10G_CX4 7 5632 #define rx_x4_control0_actualSpeeds_dr_12G_HiG 8 5633 #define rx_x4_control0_actualSpeeds_dr_12p5G_X4 9 5634 #define rx_x4_control0_actualSpeeds_dr_13G_X4 10 5635 #define rx_x4_control0_actualSpeeds_dr_15G_X4 11 5636 #define rx_x4_control0_actualSpeeds_dr_16G_X4 12 5637 #define rx_x4_control0_actualSpeeds_dr_1G_KX 13 5638 #define rx_x4_control0_actualSpeeds_dr_10G_KX4 14 5639 #define rx_x4_control0_actualSpeeds_dr_10G_KR 15 5640 #define rx_x4_control0_actualSpeeds_dr_5G 16 5641 #define rx_x4_control0_actualSpeeds_dr_6p4G 17 5642 #define rx_x4_control0_actualSpeeds_dr_20G_X4 18 5643 #define rx_x4_control0_actualSpeeds_dr_21G_X4 19 5644 #define rx_x4_control0_actualSpeeds_dr_25G_X4 20 5645 #define rx_x4_control0_actualSpeeds_dr_10G_HiG_DXGXS 21 5646 #define rx_x4_control0_actualSpeeds_dr_10G_DXGXS 22 5647 #define rx_x4_control0_actualSpeeds_dr_10p5G_HiG_DXGXS 23 5648 #define rx_x4_control0_actualSpeeds_dr_10p5G_DXGXS 24 5649 #define rx_x4_control0_actualSpeeds_dr_12p773G_HiG_DXGXS 25 5650 #define rx_x4_control0_actualSpeeds_dr_12p773G_DXGXS 26 5651 #define rx_x4_control0_actualSpeeds_dr_10G_XFI 27 5652 #define rx_x4_control0_actualSpeeds_dr_40G 28 5653 #define rx_x4_control0_actualSpeeds_dr_20G_HiG_DXGXS 29 5654 #define rx_x4_control0_actualSpeeds_dr_20G_DXGXS 30 5655 #define rx_x4_control0_actualSpeeds_dr_10G_SFI 31 5656 #define rx_x4_control0_actualSpeeds_dr_31p5G 32 5657 #define rx_x4_control0_actualSpeeds_dr_32p7G 33 5658 #define rx_x4_control0_actualSpeeds_dr_20G_SCR 34 5659 #define rx_x4_control0_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 5660 #define rx_x4_control0_actualSpeeds_dr_10G_DXGXS_SCR 36 5661 #define rx_x4_control0_actualSpeeds_dr_12G_R2 37 5662 #define rx_x4_control0_actualSpeeds_dr_10G_X2 38 5663 #define rx_x4_control0_actualSpeeds_dr_40G_KR4 39 5664 #define rx_x4_control0_actualSpeeds_dr_40G_CR4 40 5665 #define rx_x4_control0_actualSpeeds_dr_100G_CR10 41 5666 #define rx_x4_control0_actualSpeeds_dr_15p75G_DXGXS 44 5667 #define rx_x4_control0_actualSpeeds_dr_20G_KR2 57 5668 #define rx_x4_control0_actualSpeeds_dr_20G_CR2 58 5669 5670 /**************************************************************************** 5671 * Enums: rx_x4_control0_actualSpeedsMisc1 5672 */ 5673 #define rx_x4_control0_actualSpeedsMisc1_dr_2500BRCM_X1 16 5674 #define rx_x4_control0_actualSpeedsMisc1_dr_5000BRCM_X4 17 5675 #define rx_x4_control0_actualSpeedsMisc1_dr_6000BRCM_X4 18 5676 #define rx_x4_control0_actualSpeedsMisc1_dr_10GHiGig_X4 19 5677 #define rx_x4_control0_actualSpeedsMisc1_dr_10GBASE_CX4 20 5678 #define rx_x4_control0_actualSpeedsMisc1_dr_12GHiGig_X4 21 5679 #define rx_x4_control0_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 5680 #define rx_x4_control0_actualSpeedsMisc1_dr_13GHiGig_X4 23 5681 #define rx_x4_control0_actualSpeedsMisc1_dr_15GHiGig_X4 24 5682 #define rx_x4_control0_actualSpeedsMisc1_dr_16GHiGig_X4 25 5683 #define rx_x4_control0_actualSpeedsMisc1_dr_5000BRCM_X1 26 5684 #define rx_x4_control0_actualSpeedsMisc1_dr_6363BRCM_X1 27 5685 #define rx_x4_control0_actualSpeedsMisc1_dr_20GHiGig_X4 28 5686 #define rx_x4_control0_actualSpeedsMisc1_dr_21GHiGig_X4 29 5687 #define rx_x4_control0_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 5688 #define rx_x4_control0_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 5689 5690 /**************************************************************************** 5691 * Enums: rx_x4_control0_IndLaneModes 5692 */ 5693 #define rx_x4_control0_IndLaneModes_SWSDR_div2 0 5694 #define rx_x4_control0_IndLaneModes_SWSDR_div1 1 5695 #define rx_x4_control0_IndLaneModes_DWSDR_div2 2 5696 #define rx_x4_control0_IndLaneModes_DWSDR_div1 3 5697 5698 /**************************************************************************** 5699 * Enums: rx_x4_control0_prbsSelect 5700 */ 5701 #define rx_x4_control0_prbsSelect_prbs7 0 5702 #define rx_x4_control0_prbsSelect_prbs15 1 5703 #define rx_x4_control0_prbsSelect_prbs23 2 5704 #define rx_x4_control0_prbsSelect_prbs31 3 5705 5706 /**************************************************************************** 5707 * Enums: rx_x4_control0_vcoDivider 5708 */ 5709 #define rx_x4_control0_vcoDivider_div32 0 5710 #define rx_x4_control0_vcoDivider_div36 1 5711 #define rx_x4_control0_vcoDivider_div40 2 5712 #define rx_x4_control0_vcoDivider_div42 3 5713 #define rx_x4_control0_vcoDivider_div48 4 5714 #define rx_x4_control0_vcoDivider_div50 5 5715 #define rx_x4_control0_vcoDivider_div52 6 5716 #define rx_x4_control0_vcoDivider_div54 7 5717 #define rx_x4_control0_vcoDivider_div60 8 5718 #define rx_x4_control0_vcoDivider_div64 9 5719 #define rx_x4_control0_vcoDivider_div66 10 5720 #define rx_x4_control0_vcoDivider_div68 11 5721 #define rx_x4_control0_vcoDivider_div70 12 5722 #define rx_x4_control0_vcoDivider_div80 13 5723 #define rx_x4_control0_vcoDivider_div92 14 5724 #define rx_x4_control0_vcoDivider_div100 15 5725 5726 /**************************************************************************** 5727 * Enums: rx_x4_control0_refClkSelect 5728 */ 5729 #define rx_x4_control0_refClkSelect_clk_25MHz 0 5730 #define rx_x4_control0_refClkSelect_clk_100MHz 1 5731 #define rx_x4_control0_refClkSelect_clk_125MHz 2 5732 #define rx_x4_control0_refClkSelect_clk_156p25MHz 3 5733 #define rx_x4_control0_refClkSelect_clk_187p5MHz 4 5734 #define rx_x4_control0_refClkSelect_clk_161p25Mhz 5 5735 #define rx_x4_control0_refClkSelect_clk_50Mhz 6 5736 #define rx_x4_control0_refClkSelect_clk_106p25Mhz 7 5737 5738 /**************************************************************************** 5739 * Enums: rx_x4_control0_aerMMDdevTypeSelect 5740 */ 5741 #define rx_x4_control0_aerMMDdevTypeSelect_combo_core 0 5742 #define rx_x4_control0_aerMMDdevTypeSelect_PMA_PMD 1 5743 #define rx_x4_control0_aerMMDdevTypeSelect_PCS 3 5744 #define rx_x4_control0_aerMMDdevTypeSelect_PHY 4 5745 #define rx_x4_control0_aerMMDdevTypeSelect_DTE 5 5746 #define rx_x4_control0_aerMMDdevTypeSelect_CL73_AN 7 5747 5748 /**************************************************************************** 5749 * Enums: rx_x4_control0_aerMMDportSelect 5750 */ 5751 #define rx_x4_control0_aerMMDportSelect_ln0 0 5752 #define rx_x4_control0_aerMMDportSelect_ln1 1 5753 #define rx_x4_control0_aerMMDportSelect_ln2 2 5754 #define rx_x4_control0_aerMMDportSelect_ln3 3 5755 #define rx_x4_control0_aerMMDportSelect_BCST_ln0_1_2_3 511 5756 #define rx_x4_control0_aerMMDportSelect_BCST_ln0_1 512 5757 #define rx_x4_control0_aerMMDportSelect_BCST_ln2_3 513 5758 5759 /**************************************************************************** 5760 * Enums: rx_x4_control0_firmwareModeSelect 5761 */ 5762 #define rx_x4_control0_firmwareModeSelect_DEFAULT 0 5763 #define rx_x4_control0_firmwareModeSelect_SFP_OPT_LR 1 5764 #define rx_x4_control0_firmwareModeSelect_SFP_DAC 2 5765 #define rx_x4_control0_firmwareModeSelect_XLAUI 3 5766 #define rx_x4_control0_firmwareModeSelect_LONG_CH_6G 4 5767 5768 /**************************************************************************** 5769 * Enums: rx_x4_control0_tempIdxSelect 5770 */ 5771 #define rx_x4_control0_tempIdxSelect_LTE__22p9C 15 5772 #define rx_x4_control0_tempIdxSelect_LTE__12p6C 14 5773 #define rx_x4_control0_tempIdxSelect_LTE__3p0C 13 5774 #define rx_x4_control0_tempIdxSelect_LTE_6p7C 12 5775 #define rx_x4_control0_tempIdxSelect_LTE_16p4C 11 5776 #define rx_x4_control0_tempIdxSelect_LTE_26p6C 10 5777 #define rx_x4_control0_tempIdxSelect_LTE_36p3C 9 5778 #define rx_x4_control0_tempIdxSelect_LTE_46p0C 8 5779 #define rx_x4_control0_tempIdxSelect_LTE_56p2C 7 5780 #define rx_x4_control0_tempIdxSelect_LTE_65p9C 6 5781 #define rx_x4_control0_tempIdxSelect_LTE_75p6C 5 5782 #define rx_x4_control0_tempIdxSelect_LTE_85p3C 4 5783 #define rx_x4_control0_tempIdxSelect_LTE_95p5C 3 5784 #define rx_x4_control0_tempIdxSelect_LTE_105p2C 2 5785 #define rx_x4_control0_tempIdxSelect_LTE_114p9C 1 5786 #define rx_x4_control0_tempIdxSelect_LTE_125p1C 0 5787 5788 /**************************************************************************** 5789 * Enums: rx_x4_control0_port_mode 5790 */ 5791 #define rx_x4_control0_port_mode_QUAD_PORT 0 5792 #define rx_x4_control0_port_mode_TRI_1_PORT 1 5793 #define rx_x4_control0_port_mode_TRI_2_PORT 2 5794 #define rx_x4_control0_port_mode_DUAL_PORT 3 5795 #define rx_x4_control0_port_mode_SINGLE_PORT 4 5796 5797 /**************************************************************************** 5798 * Enums: rx_x4_control0_rev_letter_enum 5799 */ 5800 #define rx_x4_control0_rev_letter_enum_REV_A 0 5801 #define rx_x4_control0_rev_letter_enum_REV_B 1 5802 #define rx_x4_control0_rev_letter_enum_REV_C 2 5803 #define rx_x4_control0_rev_letter_enum_REV_D 3 5804 5805 /**************************************************************************** 5806 * Enums: rx_x4_control0_rev_number_enum 5807 */ 5808 #define rx_x4_control0_rev_number_enum_REV_0 0 5809 #define rx_x4_control0_rev_number_enum_REV_1 1 5810 #define rx_x4_control0_rev_number_enum_REV_2 2 5811 #define rx_x4_control0_rev_number_enum_REV_3 3 5812 #define rx_x4_control0_rev_number_enum_REV_4 4 5813 #define rx_x4_control0_rev_number_enum_REV_5 5 5814 #define rx_x4_control0_rev_number_enum_REV_6 6 5815 #define rx_x4_control0_rev_number_enum_REV_7 7 5816 5817 /**************************************************************************** 5818 * Enums: rx_x4_control0_bonding_enum 5819 */ 5820 #define rx_x4_control0_bonding_enum_WIRE_BOND 0 5821 #define rx_x4_control0_bonding_enum_FLIP_CHIP 1 5822 5823 /**************************************************************************** 5824 * Enums: rx_x4_control0_tech_process 5825 */ 5826 #define rx_x4_control0_tech_process_PROCESS_90NM 0 5827 #define rx_x4_control0_tech_process_PROCESS_65NM 1 5828 #define rx_x4_control0_tech_process_PROCESS_40NM 2 5829 #define rx_x4_control0_tech_process_PROCESS_28NM 3 5830 #define rx_x4_control0_tech_process_PROCESS_16NM 4 5831 5832 /**************************************************************************** 5833 * Enums: rx_x4_control0_model_num 5834 */ 5835 #define rx_x4_control0_model_num_SERDES_CL73 0 5836 #define rx_x4_control0_model_num_XGXS_16G 1 5837 #define rx_x4_control0_model_num_HYPERCORE 2 5838 #define rx_x4_control0_model_num_HYPERLITE 3 5839 #define rx_x4_control0_model_num_PCIE_G2_PIPE 4 5840 #define rx_x4_control0_model_num_SERDES_1p25GBd 5 5841 #define rx_x4_control0_model_num_SATA2 6 5842 #define rx_x4_control0_model_num_QSGMII 7 5843 #define rx_x4_control0_model_num_XGXS10G 8 5844 #define rx_x4_control0_model_num_WARPCORE 9 5845 #define rx_x4_control0_model_num_XFICORE 10 5846 #define rx_x4_control0_model_num_RXFI 11 5847 #define rx_x4_control0_model_num_WARPLITE 12 5848 #define rx_x4_control0_model_num_PENTACORE 13 5849 #define rx_x4_control0_model_num_ESM 14 5850 #define rx_x4_control0_model_num_QUAD_SGMII 15 5851 #define rx_x4_control0_model_num_WARPCORE_3 16 5852 #define rx_x4_control0_model_num_TSC 17 5853 #define rx_x4_control0_model_num_TSC4E 18 5854 #define rx_x4_control0_model_num_TSC12E 19 5855 #define rx_x4_control0_model_num_TSC4F 20 5856 #define rx_x4_control0_model_num_TSC4F_GEN2 21 5857 #define rx_x4_control0_model_num_XGXS_CL73_90NM 29 5858 #define rx_x4_control0_model_num_SERDES_CL73_90NM 30 5859 #define rx_x4_control0_model_num_WARPCORE3 32 5860 #define rx_x4_control0_model_num_WARPCORE4_TSC 33 5861 #define rx_x4_control0_model_num_RXAUI 34 5862 5863 /**************************************************************************** 5864 * Enums: rx_x4_control0_payload 5865 */ 5866 #define rx_x4_control0_payload_REPEAT_2_BYTES 0 5867 #define rx_x4_control0_payload_RAMPING 1 5868 #define rx_x4_control0_payload_CL48_CRPAT 2 5869 #define rx_x4_control0_payload_CL48_CJPAT 3 5870 #define rx_x4_control0_payload_CL36_LONG_CRPAT 4 5871 #define rx_x4_control0_payload_CL36_SHORT_CRPAT 5 5872 5873 /**************************************************************************** 5874 * Enums: rx_x4_control0_sc 5875 */ 5876 #define rx_x4_control0_sc_S_10G_CR1 0 5877 #define rx_x4_control0_sc_S_10G_KR1 1 5878 #define rx_x4_control0_sc_S_10G_X1 2 5879 #define rx_x4_control0_sc_S_10G_HG2_CR1 4 5880 #define rx_x4_control0_sc_S_10G_HG2_KR1 5 5881 #define rx_x4_control0_sc_S_10G_HG2_X1 6 5882 #define rx_x4_control0_sc_S_20G_CR1 8 5883 #define rx_x4_control0_sc_S_20G_KR1 9 5884 #define rx_x4_control0_sc_S_20G_X1 10 5885 #define rx_x4_control0_sc_S_20G_HG2_CR1 12 5886 #define rx_x4_control0_sc_S_20G_HG2_KR1 13 5887 #define rx_x4_control0_sc_S_20G_HG2_X1 14 5888 #define rx_x4_control0_sc_S_25G_CR1 16 5889 #define rx_x4_control0_sc_S_25G_KR1 17 5890 #define rx_x4_control0_sc_S_25G_X1 18 5891 #define rx_x4_control0_sc_S_25G_HG2_CR1 20 5892 #define rx_x4_control0_sc_S_25G_HG2_KR1 21 5893 #define rx_x4_control0_sc_S_25G_HG2_X1 22 5894 #define rx_x4_control0_sc_S_20G_CR2 24 5895 #define rx_x4_control0_sc_S_20G_KR2 25 5896 #define rx_x4_control0_sc_S_20G_X2 26 5897 #define rx_x4_control0_sc_S_20G_HG2_CR2 28 5898 #define rx_x4_control0_sc_S_20G_HG2_KR2 29 5899 #define rx_x4_control0_sc_S_20G_HG2_X2 30 5900 #define rx_x4_control0_sc_S_40G_CR2 32 5901 #define rx_x4_control0_sc_S_40G_KR2 33 5902 #define rx_x4_control0_sc_S_40G_X2 34 5903 #define rx_x4_control0_sc_S_40G_HG2_CR2 36 5904 #define rx_x4_control0_sc_S_40G_HG2_KR2 37 5905 #define rx_x4_control0_sc_S_40G_HG2_X2 38 5906 #define rx_x4_control0_sc_S_40G_CR4 40 5907 #define rx_x4_control0_sc_S_40G_KR4 41 5908 #define rx_x4_control0_sc_S_40G_X4 42 5909 #define rx_x4_control0_sc_S_40G_HG2_CR4 44 5910 #define rx_x4_control0_sc_S_40G_HG2_KR4 45 5911 #define rx_x4_control0_sc_S_40G_HG2_X4 46 5912 #define rx_x4_control0_sc_S_50G_CR2 48 5913 #define rx_x4_control0_sc_S_50G_KR2 49 5914 #define rx_x4_control0_sc_S_50G_X2 50 5915 #define rx_x4_control0_sc_S_50G_HG2_CR2 52 5916 #define rx_x4_control0_sc_S_50G_HG2_KR2 53 5917 #define rx_x4_control0_sc_S_50G_HG2_X2 54 5918 #define rx_x4_control0_sc_S_50G_CR4 56 5919 #define rx_x4_control0_sc_S_50G_KR4 57 5920 #define rx_x4_control0_sc_S_50G_X4 58 5921 #define rx_x4_control0_sc_S_50G_HG2_CR4 60 5922 #define rx_x4_control0_sc_S_50G_HG2_KR4 61 5923 #define rx_x4_control0_sc_S_50G_HG2_X4 62 5924 #define rx_x4_control0_sc_S_100G_CR4 64 5925 #define rx_x4_control0_sc_S_100G_KR4 65 5926 #define rx_x4_control0_sc_S_100G_X4 66 5927 #define rx_x4_control0_sc_S_100G_HG2_CR4 68 5928 #define rx_x4_control0_sc_S_100G_HG2_KR4 69 5929 #define rx_x4_control0_sc_S_100G_HG2_X4 70 5930 #define rx_x4_control0_sc_S_CL73_20GVCO 72 5931 #define rx_x4_control0_sc_S_CL73_25GVCO 80 5932 #define rx_x4_control0_sc_S_CL36_20GVCO 88 5933 #define rx_x4_control0_sc_S_CL36_25GVCO 96 5934 #define rx_x4_control0_sc_S_25G_CR_IEEE 112 5935 #define rx_x4_control0_sc_S_25G_CRS_IEEE 113 5936 #define rx_x4_control0_sc_S_25G_KR_IEEE 114 5937 #define rx_x4_control0_sc_S_25G_KRS_IEEE 115 5938 5939 /**************************************************************************** 5940 * Enums: rx_x4_control0_t_fifo_modes 5941 */ 5942 #define rx_x4_control0_t_fifo_modes_T_FIFO_INSERT_NO_AM 0 5943 #define rx_x4_control0_t_fifo_modes_T_FIFO_INSERT_4_AM 1 5944 #define rx_x4_control0_t_fifo_modes_T_FIFO_INSERT_20_AM 2 5945 #define rx_x4_control0_t_fifo_modes_T_FIFO_INSERT_2_AM 3 5946 5947 /**************************************************************************** 5948 * Enums: rx_x4_control0_t_enc_modes 5949 */ 5950 #define rx_x4_control0_t_enc_modes_T_ENC_MODE_BYPASS 0 5951 #define rx_x4_control0_t_enc_modes_T_ENC_MODE_CL49 1 5952 #define rx_x4_control0_t_enc_modes_T_ENC_MODE_CL82 2 5953 5954 /**************************************************************************** 5955 * Enums: rx_x4_control0_btmx_mode 5956 */ 5957 #define rx_x4_control0_btmx_mode_BS_BTMX_MODE_1to1 0 5958 #define rx_x4_control0_btmx_mode_BS_BTMX_MODE_2to1 1 5959 #define rx_x4_control0_btmx_mode_BS_BTMX_MODE_5to1 2 5960 5961 /**************************************************************************** 5962 * Enums: rx_x4_control0_t_type_cl82 5963 */ 5964 #define rx_x4_control0_t_type_cl82_T_TYPE_B1 5 5965 #define rx_x4_control0_t_type_cl82_T_TYPE_C 4 5966 #define rx_x4_control0_t_type_cl82_T_TYPE_S 3 5967 #define rx_x4_control0_t_type_cl82_T_TYPE_T 2 5968 #define rx_x4_control0_t_type_cl82_T_TYPE_D 1 5969 #define rx_x4_control0_t_type_cl82_T_TYPE_E 0 5970 5971 /**************************************************************************** 5972 * Enums: rx_x4_control0_txsm_state_cl82 5973 */ 5974 #define rx_x4_control0_txsm_state_cl82_TX_HIG_END 6 5975 #define rx_x4_control0_txsm_state_cl82_TX_HIG_START 5 5976 #define rx_x4_control0_txsm_state_cl82_TX_E 4 5977 #define rx_x4_control0_txsm_state_cl82_TX_T 3 5978 #define rx_x4_control0_txsm_state_cl82_TX_D 2 5979 #define rx_x4_control0_txsm_state_cl82_TX_C 1 5980 #define rx_x4_control0_txsm_state_cl82_TX_INIT 0 5981 5982 /**************************************************************************** 5983 * Enums: rx_x4_control0_ltxsm_state_cl82 5984 */ 5985 #define rx_x4_control0_ltxsm_state_cl82_TX_HIG_END 64 5986 #define rx_x4_control0_ltxsm_state_cl82_TX_HIG_START 32 5987 #define rx_x4_control0_ltxsm_state_cl82_TX_E 16 5988 #define rx_x4_control0_ltxsm_state_cl82_TX_T 8 5989 #define rx_x4_control0_ltxsm_state_cl82_TX_D 4 5990 #define rx_x4_control0_ltxsm_state_cl82_TX_C 2 5991 #define rx_x4_control0_ltxsm_state_cl82_TX_INIT 1 5992 5993 /**************************************************************************** 5994 * Enums: rx_x4_control0_r_type_coded_cl82 5995 */ 5996 #define rx_x4_control0_r_type_coded_cl82_R_TYPE_B1 32 5997 #define rx_x4_control0_r_type_coded_cl82_R_TYPE_C 16 5998 #define rx_x4_control0_r_type_coded_cl82_R_TYPE_S 8 5999 #define rx_x4_control0_r_type_coded_cl82_R_TYPE_T 4 6000 #define rx_x4_control0_r_type_coded_cl82_R_TYPE_D 2 6001 #define rx_x4_control0_r_type_coded_cl82_R_TYPE_E 1 6002 6003 /**************************************************************************** 6004 * Enums: rx_x4_control0_rxsm_state_cl82 6005 */ 6006 #define rx_x4_control0_rxsm_state_cl82_RX_HIG_END 64 6007 #define rx_x4_control0_rxsm_state_cl82_RX_HIG_START 32 6008 #define rx_x4_control0_rxsm_state_cl82_RX_E 16 6009 #define rx_x4_control0_rxsm_state_cl82_RX_T 8 6010 #define rx_x4_control0_rxsm_state_cl82_RX_D 4 6011 #define rx_x4_control0_rxsm_state_cl82_RX_C 2 6012 #define rx_x4_control0_rxsm_state_cl82_RX_INIT 1 6013 6014 /**************************************************************************** 6015 * Enums: rx_x4_control0_deskew_state 6016 */ 6017 #define rx_x4_control0_deskew_state_ALIGN_ACQUIRED 2 6018 #define rx_x4_control0_deskew_state_LOSS_OF_ALIGNMENT 1 6019 6020 /**************************************************************************** 6021 * Enums: rx_x4_control0_os_mode_enum 6022 */ 6023 #define rx_x4_control0_os_mode_enum_OS_MODE_1 0 6024 #define rx_x4_control0_os_mode_enum_OS_MODE_2 1 6025 #define rx_x4_control0_os_mode_enum_OS_MODE_4 2 6026 #define rx_x4_control0_os_mode_enum_OS_MODE_16p5 8 6027 #define rx_x4_control0_os_mode_enum_OS_MODE_20p625 12 6028 6029 /**************************************************************************** 6030 * Enums: rx_x4_control0_scr_modes 6031 */ 6032 #define rx_x4_control0_scr_modes_T_SCR_MODE_BYPASS 0 6033 #define rx_x4_control0_scr_modes_T_SCR_MODE_CL49 1 6034 #define rx_x4_control0_scr_modes_T_SCR_MODE_40G_2_LANE 2 6035 #define rx_x4_control0_scr_modes_T_SCR_MODE_100G 3 6036 #define rx_x4_control0_scr_modes_T_SCR_MODE_20G 4 6037 #define rx_x4_control0_scr_modes_T_SCR_MODE_40G_4_LANE 5 6038 6039 /**************************************************************************** 6040 * Enums: rx_x4_control0_descr_modes 6041 */ 6042 #define rx_x4_control0_descr_modes_R_DESCR_MODE_BYPASS 0 6043 #define rx_x4_control0_descr_modes_R_DESCR_MODE_CL49 1 6044 #define rx_x4_control0_descr_modes_R_DESCR_MODE_CL82 2 6045 6046 /**************************************************************************** 6047 * Enums: rx_x4_control0_r_dec_tl_mode 6048 */ 6049 #define rx_x4_control0_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 6050 #define rx_x4_control0_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 6051 #define rx_x4_control0_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 6052 6053 /**************************************************************************** 6054 * Enums: rx_x4_control0_r_dec_fsm_mode 6055 */ 6056 #define rx_x4_control0_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 6057 #define rx_x4_control0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 6058 #define rx_x4_control0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 6059 6060 /**************************************************************************** 6061 * Enums: rx_x4_control0_r_deskew_mode 6062 */ 6063 #define rx_x4_control0_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 6064 #define rx_x4_control0_r_deskew_mode_R_DESKEW_MODE_20G 1 6065 #define rx_x4_control0_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 6066 #define rx_x4_control0_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 6067 #define rx_x4_control0_r_deskew_mode_R_DESKEW_MODE_100G 4 6068 #define rx_x4_control0_r_deskew_mode_R_DESKEW_MODE_CL49 5 6069 #define rx_x4_control0_r_deskew_mode_R_DESKEW_MODE_CL91_QUAD 6 6070 #define rx_x4_control0_r_deskew_mode_R_DESKEW_MODE_CL91_SINGLE_BRCM 7 6071 #define rx_x4_control0_r_deskew_mode_R_DESKEW_MODE_CL91_DUAL_BRCM 8 6072 #define rx_x4_control0_r_deskew_mode_R_DESKEW_MODE_CL91_FC 9 6073 6074 /**************************************************************************** 6075 * Enums: rx_x4_control0_bs_dist_modes 6076 */ 6077 #define rx_x4_control0_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 6078 #define rx_x4_control0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 6079 #define rx_x4_control0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 6080 #define rx_x4_control0_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 6081 6082 /**************************************************************************** 6083 * Enums: rx_x4_control0_cl49_t_type 6084 */ 6085 #define rx_x4_control0_cl49_t_type_BAD_T_TYPE 15 6086 #define rx_x4_control0_cl49_t_type_T_TYPE_B0 11 6087 #define rx_x4_control0_cl49_t_type_T_TYPE_OB 10 6088 #define rx_x4_control0_cl49_t_type_T_TYPE_B1 9 6089 #define rx_x4_control0_cl49_t_type_T_TYPE_DB 8 6090 #define rx_x4_control0_cl49_t_type_T_TYPE_FC 7 6091 #define rx_x4_control0_cl49_t_type_T_TYPE_TB 6 6092 #define rx_x4_control0_cl49_t_type_T_TYPE_LI 5 6093 #define rx_x4_control0_cl49_t_type_T_TYPE_C 4 6094 #define rx_x4_control0_cl49_t_type_T_TYPE_S 3 6095 #define rx_x4_control0_cl49_t_type_T_TYPE_T 2 6096 #define rx_x4_control0_cl49_t_type_T_TYPE_D 1 6097 #define rx_x4_control0_cl49_t_type_T_TYPE_E 0 6098 6099 /**************************************************************************** 6100 * Enums: rx_x4_control0_cl49_txsm_states 6101 */ 6102 #define rx_x4_control0_cl49_txsm_states_TX_HIG_END 7 6103 #define rx_x4_control0_cl49_txsm_states_TX_HIG_START 6 6104 #define rx_x4_control0_cl49_txsm_states_TX_LI 5 6105 #define rx_x4_control0_cl49_txsm_states_TX_E 4 6106 #define rx_x4_control0_cl49_txsm_states_TX_T 3 6107 #define rx_x4_control0_cl49_txsm_states_TX_D 2 6108 #define rx_x4_control0_cl49_txsm_states_TX_C 1 6109 #define rx_x4_control0_cl49_txsm_states_TX_INIT 0 6110 6111 /**************************************************************************** 6112 * Enums: rx_x4_control0_cl49_ltxsm_states 6113 */ 6114 #define rx_x4_control0_cl49_ltxsm_states_TX_HIG_END 128 6115 #define rx_x4_control0_cl49_ltxsm_states_TX_HIG_START 64 6116 #define rx_x4_control0_cl49_ltxsm_states_TX_LI 32 6117 #define rx_x4_control0_cl49_ltxsm_states_TX_E 16 6118 #define rx_x4_control0_cl49_ltxsm_states_TX_T 8 6119 #define rx_x4_control0_cl49_ltxsm_states_TX_D 4 6120 #define rx_x4_control0_cl49_ltxsm_states_TX_C 2 6121 #define rx_x4_control0_cl49_ltxsm_states_TX_INIT 1 6122 6123 /**************************************************************************** 6124 * Enums: rx_x4_control0_burst_error_mode 6125 */ 6126 #define rx_x4_control0_burst_error_mode_BURST_ERROR_11_BITS 0 6127 #define rx_x4_control0_burst_error_mode_BURST_ERROR_16_BITS 1 6128 #define rx_x4_control0_burst_error_mode_BURST_ERROR_17_BITS 2 6129 #define rx_x4_control0_burst_error_mode_BURST_ERROR_18_BITS 3 6130 #define rx_x4_control0_burst_error_mode_BURST_ERROR_19_BITS 4 6131 #define rx_x4_control0_burst_error_mode_BURST_ERROR_20_BITS 5 6132 #define rx_x4_control0_burst_error_mode_BURST_ERROR_21_BITS 6 6133 #define rx_x4_control0_burst_error_mode_BURST_ERROR_22_BITS 7 6134 #define rx_x4_control0_burst_error_mode_BURST_ERROR_23_BITS 8 6135 #define rx_x4_control0_burst_error_mode_BURST_ERROR_24_BITS 9 6136 #define rx_x4_control0_burst_error_mode_BURST_ERROR_25_BITS 10 6137 #define rx_x4_control0_burst_error_mode_BURST_ERROR_26_BITS 11 6138 #define rx_x4_control0_burst_error_mode_BURST_ERROR_27_BITS 12 6139 #define rx_x4_control0_burst_error_mode_BURST_ERROR_28_BITS 13 6140 #define rx_x4_control0_burst_error_mode_BURST_ERROR_29_BITS 14 6141 #define rx_x4_control0_burst_error_mode_BURST_ERROR_30_BITS 15 6142 #define rx_x4_control0_burst_error_mode_BURST_ERROR_31_BITS 16 6143 #define rx_x4_control0_burst_error_mode_BURST_ERROR_32_BITS 17 6144 #define rx_x4_control0_burst_error_mode_BURST_ERROR_33_BITS 18 6145 #define rx_x4_control0_burst_error_mode_BURST_ERROR_34_BITS 19 6146 #define rx_x4_control0_burst_error_mode_BURST_ERROR_35_BITS 20 6147 #define rx_x4_control0_burst_error_mode_BURST_ERROR_36_BITS 21 6148 #define rx_x4_control0_burst_error_mode_BURST_ERROR_37_BITS 22 6149 #define rx_x4_control0_burst_error_mode_BURST_ERROR_38_BITS 23 6150 #define rx_x4_control0_burst_error_mode_BURST_ERROR_39_BITS 24 6151 #define rx_x4_control0_burst_error_mode_BURST_ERROR_40_BITS 25 6152 #define rx_x4_control0_burst_error_mode_BURST_ERROR_41_BITS 26 6153 6154 /**************************************************************************** 6155 * Enums: rx_x4_control0_bermon_state 6156 */ 6157 #define rx_x4_control0_bermon_state_HI_BER 4 6158 #define rx_x4_control0_bermon_state_GOOD_BER 3 6159 #define rx_x4_control0_bermon_state_BER_TEST_SH 2 6160 #define rx_x4_control0_bermon_state_START_TIMER 1 6161 #define rx_x4_control0_bermon_state_BER_MT_INIT 0 6162 6163 /**************************************************************************** 6164 * Enums: rx_x4_control0_rxsm_state_cl49 6165 */ 6166 #define rx_x4_control0_rxsm_state_cl49_RX_HIG_END 128 6167 #define rx_x4_control0_rxsm_state_cl49_RX_HIG_START 64 6168 #define rx_x4_control0_rxsm_state_cl49_RX_LI 32 6169 #define rx_x4_control0_rxsm_state_cl49_RX_E 16 6170 #define rx_x4_control0_rxsm_state_cl49_RX_T 8 6171 #define rx_x4_control0_rxsm_state_cl49_RX_D 4 6172 #define rx_x4_control0_rxsm_state_cl49_RX_C 2 6173 #define rx_x4_control0_rxsm_state_cl49_RX_INIT 1 6174 6175 /**************************************************************************** 6176 * Enums: rx_x4_control0_r_type 6177 */ 6178 #define rx_x4_control0_r_type_BAD_R_TYPE 15 6179 #define rx_x4_control0_r_type_R_TYPE_B0 11 6180 #define rx_x4_control0_r_type_R_TYPE_OB 10 6181 #define rx_x4_control0_r_type_R_TYPE_B1 9 6182 #define rx_x4_control0_r_type_R_TYPE_DB 8 6183 #define rx_x4_control0_r_type_R_TYPE_FC 7 6184 #define rx_x4_control0_r_type_R_TYPE_TB 6 6185 #define rx_x4_control0_r_type_R_TYPE_LI 5 6186 #define rx_x4_control0_r_type_R_TYPE_C 4 6187 #define rx_x4_control0_r_type_R_TYPE_S 3 6188 #define rx_x4_control0_r_type_R_TYPE_T 2 6189 #define rx_x4_control0_r_type_R_TYPE_D 1 6190 #define rx_x4_control0_r_type_R_TYPE_E 0 6191 6192 /**************************************************************************** 6193 * Enums: rx_x4_control0_am_lock_state 6194 */ 6195 #define rx_x4_control0_am_lock_state_INVALID_AM 512 6196 #define rx_x4_control0_am_lock_state_GOOD_AM 256 6197 #define rx_x4_control0_am_lock_state_COMP_AM 128 6198 #define rx_x4_control0_am_lock_state_TIMER_2 64 6199 #define rx_x4_control0_am_lock_state_AM_2_GOOD 32 6200 #define rx_x4_control0_am_lock_state_COMP_2ND 16 6201 #define rx_x4_control0_am_lock_state_TIMER_1 8 6202 #define rx_x4_control0_am_lock_state_FIND_1ST 4 6203 #define rx_x4_control0_am_lock_state_AM_RESET_CNT 2 6204 #define rx_x4_control0_am_lock_state_AM_LOCK_INIT 1 6205 6206 /**************************************************************************** 6207 * Enums: rx_x4_control0_msg_selector 6208 */ 6209 #define rx_x4_control0_msg_selector_RESERVED 0 6210 #define rx_x4_control0_msg_selector_VALUE_802p3 1 6211 #define rx_x4_control0_msg_selector_VALUE_802p9 2 6212 #define rx_x4_control0_msg_selector_VALUE_802p5 3 6213 #define rx_x4_control0_msg_selector_VALUE_1394 4 6214 6215 /**************************************************************************** 6216 * Enums: rx_x4_control0_synce_enum 6217 */ 6218 #define rx_x4_control0_synce_enum_SYNCE_NO_DIV 0 6219 #define rx_x4_control0_synce_enum_SYNCE_DIV_7 1 6220 #define rx_x4_control0_synce_enum_SYNCE_DIV_11 2 6221 6222 /**************************************************************************** 6223 * Enums: rx_x4_control0_synce_enum_stage0 6224 */ 6225 #define rx_x4_control0_synce_enum_stage0_SYNCE_NO_DIV 0 6226 #define rx_x4_control0_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 6227 #define rx_x4_control0_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 6228 6229 /**************************************************************************** 6230 * Enums: rx_x4_control0_cl91_sync_state 6231 */ 6232 #define rx_x4_control0_cl91_sync_state_FIND_1ST 0 6233 #define rx_x4_control0_cl91_sync_state_COUNT_NEXT 1 6234 #define rx_x4_control0_cl91_sync_state_COMP_2ND 2 6235 #define rx_x4_control0_cl91_sync_state_TWO_GOOD 3 6236 6237 /**************************************************************************** 6238 * Enums: rx_x4_control0_cl91_algn_state 6239 */ 6240 #define rx_x4_control0_cl91_algn_state_LOSS_OF_ALIGNMENT 0 6241 #define rx_x4_control0_cl91_algn_state_DESKEW 1 6242 #define rx_x4_control0_cl91_algn_state_DESKEW_FAIL 2 6243 #define rx_x4_control0_cl91_algn_state_ALIGN_ACQUIRED 3 6244 #define rx_x4_control0_cl91_algn_state_CW_GOOD 4 6245 #define rx_x4_control0_cl91_algn_state_CW_BAD 5 6246 #define rx_x4_control0_cl91_algn_state_THREE_BAD 6 6247 6248 /**************************************************************************** 6249 * Enums: rx_x4_control0_fec_sel_override 6250 */ 6251 #define rx_x4_control0_fec_sel_override_NO_OVERRIDE 0 6252 #define rx_x4_control0_fec_sel_override_NO_FEC 1 6253 #define rx_x4_control0_fec_sel_override_FEC_CL74 2 6254 #define rx_x4_control0_fec_sel_override_FEC_CL91 3 6255 6256 /**************************************************************************** 6257 * Enums: rx_x4_control0_cl91_blksync_mode 6258 */ 6259 #define rx_x4_control0_cl91_blksync_mode_R_BLKSYNC_NO_CL91_FEC 0 6260 #define rx_x4_control0_cl91_blksync_mode_R_BLKSYNC_CL91_QUAD_LANE_FEC 1 6261 #define rx_x4_control0_cl91_blksync_mode_R_BLKSYNC_CL91_DUAL_LANE_FEC 2 6262 #define rx_x4_control0_cl91_blksync_mode_R_BLKSYNC_CL91_SINGLE_LANE_FEC 3 6263 #define rx_x4_control0_cl91_blksync_mode_R_BLKSYNC_CL91_FC_FEC 4 6264 6265 /**************************************************************************** 6266 * Enums: rx_x4_control0_r_merge_mode 6267 */ 6268 #define rx_x4_control0_r_merge_mode_R_MERGE_MODE_BYPASS 0 6269 #define rx_x4_control0_r_merge_mode_R_MERGE_MODE_CL91_FC 1 6270 #define rx_x4_control0_r_merge_mode_R_MERGE_MODE_CL91_SINGLE_LANE 2 6271 #define rx_x4_control0_r_merge_mode_R_MERGE_MODE_CL91_DUAL_LANE 3 6272 #define rx_x4_control0_r_merge_mode_R_MERGE_MODE_CL91_QUAD_LANE 4 6273 6274 /**************************************************************************** 6275 * Enums: rx_x4_control0_r_tc_mode 6276 */ 6277 #define rx_x4_control0_r_tc_mode_R_TC_MODE_SINGLE 0 6278 #define rx_x4_control0_r_tc_mode_R_TC_MODE_DUAL 1 6279 #define rx_x4_control0_r_tc_mode_R_TC_MODE_QUAD 2 6280 6281 /**************************************************************************** 6282 * Enums: rx_x4_control0_r_tc_out_mode 6283 */ 6284 #define rx_x4_control0_r_tc_out_mode_R_TC_OUT_MODE_SINGLE 0 6285 #define rx_x4_control0_r_tc_out_mode_R_TC_OUT_MODE_DUAL 1 6286 #define rx_x4_control0_r_tc_out_mode_R_TC_OUT_MODE_QUAD 2 6287 6288 /**************************************************************************** 6289 * Enums: rx_x4_control0_cl91_fec_mode 6290 */ 6291 #define rx_x4_control0_cl91_fec_mode_NO_CL91_FEC 0 6292 #define rx_x4_control0_cl91_fec_mode_CL91_SINGLE_LANE_FC 1 6293 #define rx_x4_control0_cl91_fec_mode_CL91_SINGLE_LANE_BRCM_PROP 2 6294 #define rx_x4_control0_cl91_fec_mode_CL91_DUAL_LANE_BRCM_PROP 3 6295 #define rx_x4_control0_cl91_fec_mode_CL91_QUAD_LANE 4 6296 #define rx_x4_control0_cl91_fec_mode_IEEE_25G_CL91_SINGLE_LANE 5 6297 6298 /**************************************************************************** 6299 * Enums: rx_x4_control0_am_spacing_mul 6300 */ 6301 #define rx_x4_control0_am_spacing_mul_AM_SPACING_MUL_2 0 6302 #define rx_x4_control0_am_spacing_mul_AM_SPACING_MUL_4 1 6303 #define rx_x4_control0_am_spacing_mul_AM_SPACING_MUL_5 2 6304 #define rx_x4_control0_am_spacing_mul_AM_SPACING_MUL_20 3 6305 6306 /**************************************************************************** 6307 * Enums: rx_x4_fec_control_cl36TxEEEStates_l 6308 */ 6309 #define rx_x4_fec_control_cl36TxEEEStates_l_TX_REFRESH 8 6310 #define rx_x4_fec_control_cl36TxEEEStates_l_TX_QUIET 4 6311 #define rx_x4_fec_control_cl36TxEEEStates_l_TX_SLEEP 2 6312 #define rx_x4_fec_control_cl36TxEEEStates_l_TX_ACTIVE 1 6313 6314 /**************************************************************************** 6315 * Enums: rx_x4_fec_control_cl36TxEEEStates_c 6316 */ 6317 #define rx_x4_fec_control_cl36TxEEEStates_c_TX_REFRESH 3 6318 #define rx_x4_fec_control_cl36TxEEEStates_c_TX_QUIET 2 6319 #define rx_x4_fec_control_cl36TxEEEStates_c_TX_SLEEP 1 6320 #define rx_x4_fec_control_cl36TxEEEStates_c_TX_ACTIVE 0 6321 6322 /**************************************************************************** 6323 * Enums: rx_x4_fec_control_cl49TxEEEStates_l 6324 */ 6325 #define rx_x4_fec_control_cl49TxEEEStates_l_SCR_RESET_2 64 6326 #define rx_x4_fec_control_cl49TxEEEStates_l_SCR_RESET_1 32 6327 #define rx_x4_fec_control_cl49TxEEEStates_l_TX_WAKE 16 6328 #define rx_x4_fec_control_cl49TxEEEStates_l_TX_REFRESH 8 6329 #define rx_x4_fec_control_cl49TxEEEStates_l_TX_QUIET 4 6330 #define rx_x4_fec_control_cl49TxEEEStates_l_TX_SLEEP 2 6331 #define rx_x4_fec_control_cl49TxEEEStates_l_TX_ACTIVE 1 6332 6333 /**************************************************************************** 6334 * Enums: rx_x4_fec_control_fec_req_enum 6335 */ 6336 #define rx_x4_fec_control_fec_req_enum_FEC_not_supported 0 6337 #define rx_x4_fec_control_fec_req_enum_FEC_supported_but_not_requested 1 6338 #define rx_x4_fec_control_fec_req_enum_invalid_setting 2 6339 #define rx_x4_fec_control_fec_req_enum_FEC_supported_and_requested 3 6340 6341 /**************************************************************************** 6342 * Enums: rx_x4_fec_control_cl73_pause_enum 6343 */ 6344 #define rx_x4_fec_control_cl73_pause_enum_No_PAUSE_ability 0 6345 #define rx_x4_fec_control_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 6346 #define rx_x4_fec_control_cl73_pause_enum_Symmetric_PAUSE_ability 1 6347 #define rx_x4_fec_control_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 6348 6349 /**************************************************************************** 6350 * Enums: rx_x4_fec_control_cl49TxEEEStates_c 6351 */ 6352 #define rx_x4_fec_control_cl49TxEEEStates_c_SCR_RESET_2 6 6353 #define rx_x4_fec_control_cl49TxEEEStates_c_SCR_RESET_1 5 6354 #define rx_x4_fec_control_cl49TxEEEStates_c_TX_WAKE 4 6355 #define rx_x4_fec_control_cl49TxEEEStates_c_TX_REFRESH 3 6356 #define rx_x4_fec_control_cl49TxEEEStates_c_TX_QUIET 2 6357 #define rx_x4_fec_control_cl49TxEEEStates_c_TX_SLEEP 1 6358 #define rx_x4_fec_control_cl49TxEEEStates_c_TX_ACTIVE 0 6359 6360 /**************************************************************************** 6361 * Enums: rx_x4_fec_control_cl36RxEEEStates_l 6362 */ 6363 #define rx_x4_fec_control_cl36RxEEEStates_l_RX_LINK_FAIL 32 6364 #define rx_x4_fec_control_cl36RxEEEStates_l_RX_WTF 16 6365 #define rx_x4_fec_control_cl36RxEEEStates_l_RX_WAKE 8 6366 #define rx_x4_fec_control_cl36RxEEEStates_l_RX_QUIET 4 6367 #define rx_x4_fec_control_cl36RxEEEStates_l_RX_SLEEP 2 6368 #define rx_x4_fec_control_cl36RxEEEStates_l_RX_ACTIVE 1 6369 6370 /**************************************************************************** 6371 * Enums: rx_x4_fec_control_cl36RxEEEStates_c 6372 */ 6373 #define rx_x4_fec_control_cl36RxEEEStates_c_RX_LINK_FAIL 5 6374 #define rx_x4_fec_control_cl36RxEEEStates_c_RX_WTF 4 6375 #define rx_x4_fec_control_cl36RxEEEStates_c_RX_WAKE 3 6376 #define rx_x4_fec_control_cl36RxEEEStates_c_RX_QUIET 2 6377 #define rx_x4_fec_control_cl36RxEEEStates_c_RX_SLEEP 1 6378 #define rx_x4_fec_control_cl36RxEEEStates_c_RX_ACTIVE 0 6379 6380 /**************************************************************************** 6381 * Enums: rx_x4_fec_control_cl49RxEEEStates_l 6382 */ 6383 #define rx_x4_fec_control_cl49RxEEEStates_l_RX_LINK_FAIL 32 6384 #define rx_x4_fec_control_cl49RxEEEStates_l_RX_WTF 16 6385 #define rx_x4_fec_control_cl49RxEEEStates_l_RX_WAKE 8 6386 #define rx_x4_fec_control_cl49RxEEEStates_l_RX_QUIET 4 6387 #define rx_x4_fec_control_cl49RxEEEStates_l_RX_SLEEP 2 6388 #define rx_x4_fec_control_cl49RxEEEStates_l_RX_ACTIVE 1 6389 6390 /**************************************************************************** 6391 * Enums: rx_x4_fec_control_cl49RxEEEStates_c 6392 */ 6393 #define rx_x4_fec_control_cl49RxEEEStates_c_RX_LINK_FAIL 5 6394 #define rx_x4_fec_control_cl49RxEEEStates_c_RX_WTF 4 6395 #define rx_x4_fec_control_cl49RxEEEStates_c_RX_WAKE 3 6396 #define rx_x4_fec_control_cl49RxEEEStates_c_RX_QUIET 2 6397 #define rx_x4_fec_control_cl49RxEEEStates_c_RX_SLEEP 1 6398 #define rx_x4_fec_control_cl49RxEEEStates_c_RX_ACTIVE 0 6399 6400 /**************************************************************************** 6401 * Enums: rx_x4_fec_control_cl48TxEEEStates_l 6402 */ 6403 #define rx_x4_fec_control_cl48TxEEEStates_l_TX_REFRESH 8 6404 #define rx_x4_fec_control_cl48TxEEEStates_l_TX_QUIET 4 6405 #define rx_x4_fec_control_cl48TxEEEStates_l_TX_SLEEP 2 6406 #define rx_x4_fec_control_cl48TxEEEStates_l_TX_ACTIVE 1 6407 6408 /**************************************************************************** 6409 * Enums: rx_x4_fec_control_cl48TxEEEStates_c 6410 */ 6411 #define rx_x4_fec_control_cl48TxEEEStates_c_TX_REFRESH 3 6412 #define rx_x4_fec_control_cl48TxEEEStates_c_TX_QUIET 2 6413 #define rx_x4_fec_control_cl48TxEEEStates_c_TX_SLEEP 1 6414 #define rx_x4_fec_control_cl48TxEEEStates_c_TX_ACTIVE 0 6415 6416 /**************************************************************************** 6417 * Enums: rx_x4_fec_control_cl48RxEEEStates_l 6418 */ 6419 #define rx_x4_fec_control_cl48RxEEEStates_l_RX_LINK_FAIL 32 6420 #define rx_x4_fec_control_cl48RxEEEStates_l_RX_WAKE 16 6421 #define rx_x4_fec_control_cl48RxEEEStates_l_RX_QUIET 8 6422 #define rx_x4_fec_control_cl48RxEEEStates_l_RX_DEACT 4 6423 #define rx_x4_fec_control_cl48RxEEEStates_l_RX_SLEEP 2 6424 #define rx_x4_fec_control_cl48RxEEEStates_l_RX_ACTIVE 1 6425 6426 /**************************************************************************** 6427 * Enums: rx_x4_fec_control_cl48RxEEEStates_c 6428 */ 6429 #define rx_x4_fec_control_cl48RxEEEStates_c_RX_LINK_FAIL 5 6430 #define rx_x4_fec_control_cl48RxEEEStates_c_RX_WAKE 4 6431 #define rx_x4_fec_control_cl48RxEEEStates_c_RX_QUIET 3 6432 #define rx_x4_fec_control_cl48RxEEEStates_c_RX_DEACT 2 6433 #define rx_x4_fec_control_cl48RxEEEStates_c_RX_SLEEP 1 6434 #define rx_x4_fec_control_cl48RxEEEStates_c_RX_ACTIVE 0 6435 6436 /**************************************************************************** 6437 * Enums: rx_x4_fec_control_IQP_Options 6438 */ 6439 #define rx_x4_fec_control_IQP_Options_i50uA 0 6440 #define rx_x4_fec_control_IQP_Options_i100uA 1 6441 #define rx_x4_fec_control_IQP_Options_i150uA 2 6442 #define rx_x4_fec_control_IQP_Options_i200uA 3 6443 #define rx_x4_fec_control_IQP_Options_i250uA 4 6444 #define rx_x4_fec_control_IQP_Options_i300uA 5 6445 #define rx_x4_fec_control_IQP_Options_i350uA 6 6446 #define rx_x4_fec_control_IQP_Options_i400uA 7 6447 #define rx_x4_fec_control_IQP_Options_i450uA 8 6448 #define rx_x4_fec_control_IQP_Options_i500uA 9 6449 #define rx_x4_fec_control_IQP_Options_i550uA 10 6450 #define rx_x4_fec_control_IQP_Options_i600uA 11 6451 #define rx_x4_fec_control_IQP_Options_i650uA 12 6452 #define rx_x4_fec_control_IQP_Options_i700uA 13 6453 #define rx_x4_fec_control_IQP_Options_i750uA 14 6454 #define rx_x4_fec_control_IQP_Options_i800uA 15 6455 6456 /**************************************************************************** 6457 * Enums: rx_x4_fec_control_IDriver_Options 6458 */ 6459 #define rx_x4_fec_control_IDriver_Options_v680mV 0 6460 #define rx_x4_fec_control_IDriver_Options_v730mV 1 6461 #define rx_x4_fec_control_IDriver_Options_v780mV 2 6462 #define rx_x4_fec_control_IDriver_Options_v830mV 3 6463 #define rx_x4_fec_control_IDriver_Options_v880mV 4 6464 #define rx_x4_fec_control_IDriver_Options_v930mV 5 6465 #define rx_x4_fec_control_IDriver_Options_v980mV 6 6466 #define rx_x4_fec_control_IDriver_Options_v1010mV 7 6467 #define rx_x4_fec_control_IDriver_Options_v1040mV 8 6468 #define rx_x4_fec_control_IDriver_Options_v1060mV 9 6469 #define rx_x4_fec_control_IDriver_Options_v1070mV 10 6470 #define rx_x4_fec_control_IDriver_Options_v1080mV 11 6471 #define rx_x4_fec_control_IDriver_Options_v1085mV 12 6472 #define rx_x4_fec_control_IDriver_Options_v1090mV 13 6473 #define rx_x4_fec_control_IDriver_Options_v1095mV 14 6474 #define rx_x4_fec_control_IDriver_Options_v1100mV 15 6475 6476 /**************************************************************************** 6477 * Enums: rx_x4_fec_control_operationModes 6478 */ 6479 #define rx_x4_fec_control_operationModes_XGXS 0 6480 #define rx_x4_fec_control_operationModes_XGXG_nCC 1 6481 #define rx_x4_fec_control_operationModes_Indlane_OS8 4 6482 #define rx_x4_fec_control_operationModes_IndLane_OS5 5 6483 #define rx_x4_fec_control_operationModes_PCI 7 6484 #define rx_x4_fec_control_operationModes_XGXS_nLQ 8 6485 #define rx_x4_fec_control_operationModes_XGXS_nLQnCC 9 6486 #define rx_x4_fec_control_operationModes_PBypass 10 6487 #define rx_x4_fec_control_operationModes_PBypass_nDSK 11 6488 #define rx_x4_fec_control_operationModes_ComboCoreMode 12 6489 #define rx_x4_fec_control_operationModes_Clocks_off 15 6490 6491 /**************************************************************************** 6492 * Enums: rx_x4_fec_control_actualSpeeds 6493 */ 6494 #define rx_x4_fec_control_actualSpeeds_dr_10M 0 6495 #define rx_x4_fec_control_actualSpeeds_dr_100M 1 6496 #define rx_x4_fec_control_actualSpeeds_dr_1G 2 6497 #define rx_x4_fec_control_actualSpeeds_dr_2p5G 3 6498 #define rx_x4_fec_control_actualSpeeds_dr_5G_X4 4 6499 #define rx_x4_fec_control_actualSpeeds_dr_6G_X4 5 6500 #define rx_x4_fec_control_actualSpeeds_dr_10G_HiG 6 6501 #define rx_x4_fec_control_actualSpeeds_dr_10G_CX4 7 6502 #define rx_x4_fec_control_actualSpeeds_dr_12G_HiG 8 6503 #define rx_x4_fec_control_actualSpeeds_dr_12p5G_X4 9 6504 #define rx_x4_fec_control_actualSpeeds_dr_13G_X4 10 6505 #define rx_x4_fec_control_actualSpeeds_dr_15G_X4 11 6506 #define rx_x4_fec_control_actualSpeeds_dr_16G_X4 12 6507 #define rx_x4_fec_control_actualSpeeds_dr_1G_KX 13 6508 #define rx_x4_fec_control_actualSpeeds_dr_10G_KX4 14 6509 #define rx_x4_fec_control_actualSpeeds_dr_10G_KR 15 6510 #define rx_x4_fec_control_actualSpeeds_dr_5G 16 6511 #define rx_x4_fec_control_actualSpeeds_dr_6p4G 17 6512 #define rx_x4_fec_control_actualSpeeds_dr_20G_X4 18 6513 #define rx_x4_fec_control_actualSpeeds_dr_21G_X4 19 6514 #define rx_x4_fec_control_actualSpeeds_dr_25G_X4 20 6515 #define rx_x4_fec_control_actualSpeeds_dr_10G_HiG_DXGXS 21 6516 #define rx_x4_fec_control_actualSpeeds_dr_10G_DXGXS 22 6517 #define rx_x4_fec_control_actualSpeeds_dr_10p5G_HiG_DXGXS 23 6518 #define rx_x4_fec_control_actualSpeeds_dr_10p5G_DXGXS 24 6519 #define rx_x4_fec_control_actualSpeeds_dr_12p773G_HiG_DXGXS 25 6520 #define rx_x4_fec_control_actualSpeeds_dr_12p773G_DXGXS 26 6521 #define rx_x4_fec_control_actualSpeeds_dr_10G_XFI 27 6522 #define rx_x4_fec_control_actualSpeeds_dr_40G 28 6523 #define rx_x4_fec_control_actualSpeeds_dr_20G_HiG_DXGXS 29 6524 #define rx_x4_fec_control_actualSpeeds_dr_20G_DXGXS 30 6525 #define rx_x4_fec_control_actualSpeeds_dr_10G_SFI 31 6526 #define rx_x4_fec_control_actualSpeeds_dr_31p5G 32 6527 #define rx_x4_fec_control_actualSpeeds_dr_32p7G 33 6528 #define rx_x4_fec_control_actualSpeeds_dr_20G_SCR 34 6529 #define rx_x4_fec_control_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 6530 #define rx_x4_fec_control_actualSpeeds_dr_10G_DXGXS_SCR 36 6531 #define rx_x4_fec_control_actualSpeeds_dr_12G_R2 37 6532 #define rx_x4_fec_control_actualSpeeds_dr_10G_X2 38 6533 #define rx_x4_fec_control_actualSpeeds_dr_40G_KR4 39 6534 #define rx_x4_fec_control_actualSpeeds_dr_40G_CR4 40 6535 #define rx_x4_fec_control_actualSpeeds_dr_100G_CR10 41 6536 #define rx_x4_fec_control_actualSpeeds_dr_15p75G_DXGXS 44 6537 #define rx_x4_fec_control_actualSpeeds_dr_20G_KR2 57 6538 #define rx_x4_fec_control_actualSpeeds_dr_20G_CR2 58 6539 6540 /**************************************************************************** 6541 * Enums: rx_x4_fec_control_actualSpeedsMisc1 6542 */ 6543 #define rx_x4_fec_control_actualSpeedsMisc1_dr_2500BRCM_X1 16 6544 #define rx_x4_fec_control_actualSpeedsMisc1_dr_5000BRCM_X4 17 6545 #define rx_x4_fec_control_actualSpeedsMisc1_dr_6000BRCM_X4 18 6546 #define rx_x4_fec_control_actualSpeedsMisc1_dr_10GHiGig_X4 19 6547 #define rx_x4_fec_control_actualSpeedsMisc1_dr_10GBASE_CX4 20 6548 #define rx_x4_fec_control_actualSpeedsMisc1_dr_12GHiGig_X4 21 6549 #define rx_x4_fec_control_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 6550 #define rx_x4_fec_control_actualSpeedsMisc1_dr_13GHiGig_X4 23 6551 #define rx_x4_fec_control_actualSpeedsMisc1_dr_15GHiGig_X4 24 6552 #define rx_x4_fec_control_actualSpeedsMisc1_dr_16GHiGig_X4 25 6553 #define rx_x4_fec_control_actualSpeedsMisc1_dr_5000BRCM_X1 26 6554 #define rx_x4_fec_control_actualSpeedsMisc1_dr_6363BRCM_X1 27 6555 #define rx_x4_fec_control_actualSpeedsMisc1_dr_20GHiGig_X4 28 6556 #define rx_x4_fec_control_actualSpeedsMisc1_dr_21GHiGig_X4 29 6557 #define rx_x4_fec_control_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 6558 #define rx_x4_fec_control_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 6559 6560 /**************************************************************************** 6561 * Enums: rx_x4_fec_control_IndLaneModes 6562 */ 6563 #define rx_x4_fec_control_IndLaneModes_SWSDR_div2 0 6564 #define rx_x4_fec_control_IndLaneModes_SWSDR_div1 1 6565 #define rx_x4_fec_control_IndLaneModes_DWSDR_div2 2 6566 #define rx_x4_fec_control_IndLaneModes_DWSDR_div1 3 6567 6568 /**************************************************************************** 6569 * Enums: rx_x4_fec_control_prbsSelect 6570 */ 6571 #define rx_x4_fec_control_prbsSelect_prbs7 0 6572 #define rx_x4_fec_control_prbsSelect_prbs15 1 6573 #define rx_x4_fec_control_prbsSelect_prbs23 2 6574 #define rx_x4_fec_control_prbsSelect_prbs31 3 6575 6576 /**************************************************************************** 6577 * Enums: rx_x4_fec_control_vcoDivider 6578 */ 6579 #define rx_x4_fec_control_vcoDivider_div32 0 6580 #define rx_x4_fec_control_vcoDivider_div36 1 6581 #define rx_x4_fec_control_vcoDivider_div40 2 6582 #define rx_x4_fec_control_vcoDivider_div42 3 6583 #define rx_x4_fec_control_vcoDivider_div48 4 6584 #define rx_x4_fec_control_vcoDivider_div50 5 6585 #define rx_x4_fec_control_vcoDivider_div52 6 6586 #define rx_x4_fec_control_vcoDivider_div54 7 6587 #define rx_x4_fec_control_vcoDivider_div60 8 6588 #define rx_x4_fec_control_vcoDivider_div64 9 6589 #define rx_x4_fec_control_vcoDivider_div66 10 6590 #define rx_x4_fec_control_vcoDivider_div68 11 6591 #define rx_x4_fec_control_vcoDivider_div70 12 6592 #define rx_x4_fec_control_vcoDivider_div80 13 6593 #define rx_x4_fec_control_vcoDivider_div92 14 6594 #define rx_x4_fec_control_vcoDivider_div100 15 6595 6596 /**************************************************************************** 6597 * Enums: rx_x4_fec_control_refClkSelect 6598 */ 6599 #define rx_x4_fec_control_refClkSelect_clk_25MHz 0 6600 #define rx_x4_fec_control_refClkSelect_clk_100MHz 1 6601 #define rx_x4_fec_control_refClkSelect_clk_125MHz 2 6602 #define rx_x4_fec_control_refClkSelect_clk_156p25MHz 3 6603 #define rx_x4_fec_control_refClkSelect_clk_187p5MHz 4 6604 #define rx_x4_fec_control_refClkSelect_clk_161p25Mhz 5 6605 #define rx_x4_fec_control_refClkSelect_clk_50Mhz 6 6606 #define rx_x4_fec_control_refClkSelect_clk_106p25Mhz 7 6607 6608 /**************************************************************************** 6609 * Enums: rx_x4_fec_control_aerMMDdevTypeSelect 6610 */ 6611 #define rx_x4_fec_control_aerMMDdevTypeSelect_combo_core 0 6612 #define rx_x4_fec_control_aerMMDdevTypeSelect_PMA_PMD 1 6613 #define rx_x4_fec_control_aerMMDdevTypeSelect_PCS 3 6614 #define rx_x4_fec_control_aerMMDdevTypeSelect_PHY 4 6615 #define rx_x4_fec_control_aerMMDdevTypeSelect_DTE 5 6616 #define rx_x4_fec_control_aerMMDdevTypeSelect_CL73_AN 7 6617 6618 /**************************************************************************** 6619 * Enums: rx_x4_fec_control_aerMMDportSelect 6620 */ 6621 #define rx_x4_fec_control_aerMMDportSelect_ln0 0 6622 #define rx_x4_fec_control_aerMMDportSelect_ln1 1 6623 #define rx_x4_fec_control_aerMMDportSelect_ln2 2 6624 #define rx_x4_fec_control_aerMMDportSelect_ln3 3 6625 #define rx_x4_fec_control_aerMMDportSelect_BCST_ln0_1_2_3 511 6626 #define rx_x4_fec_control_aerMMDportSelect_BCST_ln0_1 512 6627 #define rx_x4_fec_control_aerMMDportSelect_BCST_ln2_3 513 6628 6629 /**************************************************************************** 6630 * Enums: rx_x4_fec_control_firmwareModeSelect 6631 */ 6632 #define rx_x4_fec_control_firmwareModeSelect_DEFAULT 0 6633 #define rx_x4_fec_control_firmwareModeSelect_SFP_OPT_LR 1 6634 #define rx_x4_fec_control_firmwareModeSelect_SFP_DAC 2 6635 #define rx_x4_fec_control_firmwareModeSelect_XLAUI 3 6636 #define rx_x4_fec_control_firmwareModeSelect_LONG_CH_6G 4 6637 6638 /**************************************************************************** 6639 * Enums: rx_x4_fec_control_tempIdxSelect 6640 */ 6641 #define rx_x4_fec_control_tempIdxSelect_LTE__22p9C 15 6642 #define rx_x4_fec_control_tempIdxSelect_LTE__12p6C 14 6643 #define rx_x4_fec_control_tempIdxSelect_LTE__3p0C 13 6644 #define rx_x4_fec_control_tempIdxSelect_LTE_6p7C 12 6645 #define rx_x4_fec_control_tempIdxSelect_LTE_16p4C 11 6646 #define rx_x4_fec_control_tempIdxSelect_LTE_26p6C 10 6647 #define rx_x4_fec_control_tempIdxSelect_LTE_36p3C 9 6648 #define rx_x4_fec_control_tempIdxSelect_LTE_46p0C 8 6649 #define rx_x4_fec_control_tempIdxSelect_LTE_56p2C 7 6650 #define rx_x4_fec_control_tempIdxSelect_LTE_65p9C 6 6651 #define rx_x4_fec_control_tempIdxSelect_LTE_75p6C 5 6652 #define rx_x4_fec_control_tempIdxSelect_LTE_85p3C 4 6653 #define rx_x4_fec_control_tempIdxSelect_LTE_95p5C 3 6654 #define rx_x4_fec_control_tempIdxSelect_LTE_105p2C 2 6655 #define rx_x4_fec_control_tempIdxSelect_LTE_114p9C 1 6656 #define rx_x4_fec_control_tempIdxSelect_LTE_125p1C 0 6657 6658 /**************************************************************************** 6659 * Enums: rx_x4_fec_control_port_mode 6660 */ 6661 #define rx_x4_fec_control_port_mode_QUAD_PORT 0 6662 #define rx_x4_fec_control_port_mode_TRI_1_PORT 1 6663 #define rx_x4_fec_control_port_mode_TRI_2_PORT 2 6664 #define rx_x4_fec_control_port_mode_DUAL_PORT 3 6665 #define rx_x4_fec_control_port_mode_SINGLE_PORT 4 6666 6667 /**************************************************************************** 6668 * Enums: rx_x4_fec_control_rev_letter_enum 6669 */ 6670 #define rx_x4_fec_control_rev_letter_enum_REV_A 0 6671 #define rx_x4_fec_control_rev_letter_enum_REV_B 1 6672 #define rx_x4_fec_control_rev_letter_enum_REV_C 2 6673 #define rx_x4_fec_control_rev_letter_enum_REV_D 3 6674 6675 /**************************************************************************** 6676 * Enums: rx_x4_fec_control_rev_number_enum 6677 */ 6678 #define rx_x4_fec_control_rev_number_enum_REV_0 0 6679 #define rx_x4_fec_control_rev_number_enum_REV_1 1 6680 #define rx_x4_fec_control_rev_number_enum_REV_2 2 6681 #define rx_x4_fec_control_rev_number_enum_REV_3 3 6682 #define rx_x4_fec_control_rev_number_enum_REV_4 4 6683 #define rx_x4_fec_control_rev_number_enum_REV_5 5 6684 #define rx_x4_fec_control_rev_number_enum_REV_6 6 6685 #define rx_x4_fec_control_rev_number_enum_REV_7 7 6686 6687 /**************************************************************************** 6688 * Enums: rx_x4_fec_control_bonding_enum 6689 */ 6690 #define rx_x4_fec_control_bonding_enum_WIRE_BOND 0 6691 #define rx_x4_fec_control_bonding_enum_FLIP_CHIP 1 6692 6693 /**************************************************************************** 6694 * Enums: rx_x4_fec_control_tech_process 6695 */ 6696 #define rx_x4_fec_control_tech_process_PROCESS_90NM 0 6697 #define rx_x4_fec_control_tech_process_PROCESS_65NM 1 6698 #define rx_x4_fec_control_tech_process_PROCESS_40NM 2 6699 #define rx_x4_fec_control_tech_process_PROCESS_28NM 3 6700 #define rx_x4_fec_control_tech_process_PROCESS_16NM 4 6701 6702 /**************************************************************************** 6703 * Enums: rx_x4_fec_control_model_num 6704 */ 6705 #define rx_x4_fec_control_model_num_SERDES_CL73 0 6706 #define rx_x4_fec_control_model_num_XGXS_16G 1 6707 #define rx_x4_fec_control_model_num_HYPERCORE 2 6708 #define rx_x4_fec_control_model_num_HYPERLITE 3 6709 #define rx_x4_fec_control_model_num_PCIE_G2_PIPE 4 6710 #define rx_x4_fec_control_model_num_SERDES_1p25GBd 5 6711 #define rx_x4_fec_control_model_num_SATA2 6 6712 #define rx_x4_fec_control_model_num_QSGMII 7 6713 #define rx_x4_fec_control_model_num_XGXS10G 8 6714 #define rx_x4_fec_control_model_num_WARPCORE 9 6715 #define rx_x4_fec_control_model_num_XFICORE 10 6716 #define rx_x4_fec_control_model_num_RXFI 11 6717 #define rx_x4_fec_control_model_num_WARPLITE 12 6718 #define rx_x4_fec_control_model_num_PENTACORE 13 6719 #define rx_x4_fec_control_model_num_ESM 14 6720 #define rx_x4_fec_control_model_num_QUAD_SGMII 15 6721 #define rx_x4_fec_control_model_num_WARPCORE_3 16 6722 #define rx_x4_fec_control_model_num_TSC 17 6723 #define rx_x4_fec_control_model_num_TSC4E 18 6724 #define rx_x4_fec_control_model_num_TSC12E 19 6725 #define rx_x4_fec_control_model_num_TSC4F 20 6726 #define rx_x4_fec_control_model_num_TSC4F_GEN2 21 6727 #define rx_x4_fec_control_model_num_XGXS_CL73_90NM 29 6728 #define rx_x4_fec_control_model_num_SERDES_CL73_90NM 30 6729 #define rx_x4_fec_control_model_num_WARPCORE3 32 6730 #define rx_x4_fec_control_model_num_WARPCORE4_TSC 33 6731 #define rx_x4_fec_control_model_num_RXAUI 34 6732 6733 /**************************************************************************** 6734 * Enums: rx_x4_fec_control_payload 6735 */ 6736 #define rx_x4_fec_control_payload_REPEAT_2_BYTES 0 6737 #define rx_x4_fec_control_payload_RAMPING 1 6738 #define rx_x4_fec_control_payload_CL48_CRPAT 2 6739 #define rx_x4_fec_control_payload_CL48_CJPAT 3 6740 #define rx_x4_fec_control_payload_CL36_LONG_CRPAT 4 6741 #define rx_x4_fec_control_payload_CL36_SHORT_CRPAT 5 6742 6743 /**************************************************************************** 6744 * Enums: rx_x4_fec_control_sc 6745 */ 6746 #define rx_x4_fec_control_sc_S_10G_CR1 0 6747 #define rx_x4_fec_control_sc_S_10G_KR1 1 6748 #define rx_x4_fec_control_sc_S_10G_X1 2 6749 #define rx_x4_fec_control_sc_S_10G_HG2_CR1 4 6750 #define rx_x4_fec_control_sc_S_10G_HG2_KR1 5 6751 #define rx_x4_fec_control_sc_S_10G_HG2_X1 6 6752 #define rx_x4_fec_control_sc_S_20G_CR1 8 6753 #define rx_x4_fec_control_sc_S_20G_KR1 9 6754 #define rx_x4_fec_control_sc_S_20G_X1 10 6755 #define rx_x4_fec_control_sc_S_20G_HG2_CR1 12 6756 #define rx_x4_fec_control_sc_S_20G_HG2_KR1 13 6757 #define rx_x4_fec_control_sc_S_20G_HG2_X1 14 6758 #define rx_x4_fec_control_sc_S_25G_CR1 16 6759 #define rx_x4_fec_control_sc_S_25G_KR1 17 6760 #define rx_x4_fec_control_sc_S_25G_X1 18 6761 #define rx_x4_fec_control_sc_S_25G_HG2_CR1 20 6762 #define rx_x4_fec_control_sc_S_25G_HG2_KR1 21 6763 #define rx_x4_fec_control_sc_S_25G_HG2_X1 22 6764 #define rx_x4_fec_control_sc_S_20G_CR2 24 6765 #define rx_x4_fec_control_sc_S_20G_KR2 25 6766 #define rx_x4_fec_control_sc_S_20G_X2 26 6767 #define rx_x4_fec_control_sc_S_20G_HG2_CR2 28 6768 #define rx_x4_fec_control_sc_S_20G_HG2_KR2 29 6769 #define rx_x4_fec_control_sc_S_20G_HG2_X2 30 6770 #define rx_x4_fec_control_sc_S_40G_CR2 32 6771 #define rx_x4_fec_control_sc_S_40G_KR2 33 6772 #define rx_x4_fec_control_sc_S_40G_X2 34 6773 #define rx_x4_fec_control_sc_S_40G_HG2_CR2 36 6774 #define rx_x4_fec_control_sc_S_40G_HG2_KR2 37 6775 #define rx_x4_fec_control_sc_S_40G_HG2_X2 38 6776 #define rx_x4_fec_control_sc_S_40G_CR4 40 6777 #define rx_x4_fec_control_sc_S_40G_KR4 41 6778 #define rx_x4_fec_control_sc_S_40G_X4 42 6779 #define rx_x4_fec_control_sc_S_40G_HG2_CR4 44 6780 #define rx_x4_fec_control_sc_S_40G_HG2_KR4 45 6781 #define rx_x4_fec_control_sc_S_40G_HG2_X4 46 6782 #define rx_x4_fec_control_sc_S_50G_CR2 48 6783 #define rx_x4_fec_control_sc_S_50G_KR2 49 6784 #define rx_x4_fec_control_sc_S_50G_X2 50 6785 #define rx_x4_fec_control_sc_S_50G_HG2_CR2 52 6786 #define rx_x4_fec_control_sc_S_50G_HG2_KR2 53 6787 #define rx_x4_fec_control_sc_S_50G_HG2_X2 54 6788 #define rx_x4_fec_control_sc_S_50G_CR4 56 6789 #define rx_x4_fec_control_sc_S_50G_KR4 57 6790 #define rx_x4_fec_control_sc_S_50G_X4 58 6791 #define rx_x4_fec_control_sc_S_50G_HG2_CR4 60 6792 #define rx_x4_fec_control_sc_S_50G_HG2_KR4 61 6793 #define rx_x4_fec_control_sc_S_50G_HG2_X4 62 6794 #define rx_x4_fec_control_sc_S_100G_CR4 64 6795 #define rx_x4_fec_control_sc_S_100G_KR4 65 6796 #define rx_x4_fec_control_sc_S_100G_X4 66 6797 #define rx_x4_fec_control_sc_S_100G_HG2_CR4 68 6798 #define rx_x4_fec_control_sc_S_100G_HG2_KR4 69 6799 #define rx_x4_fec_control_sc_S_100G_HG2_X4 70 6800 #define rx_x4_fec_control_sc_S_CL73_20GVCO 72 6801 #define rx_x4_fec_control_sc_S_CL73_25GVCO 80 6802 #define rx_x4_fec_control_sc_S_CL36_20GVCO 88 6803 #define rx_x4_fec_control_sc_S_CL36_25GVCO 96 6804 #define rx_x4_fec_control_sc_S_25G_CR_IEEE 112 6805 #define rx_x4_fec_control_sc_S_25G_CRS_IEEE 113 6806 #define rx_x4_fec_control_sc_S_25G_KR_IEEE 114 6807 #define rx_x4_fec_control_sc_S_25G_KRS_IEEE 115 6808 6809 /**************************************************************************** 6810 * Enums: rx_x4_fec_control_t_fifo_modes 6811 */ 6812 #define rx_x4_fec_control_t_fifo_modes_T_FIFO_INSERT_NO_AM 0 6813 #define rx_x4_fec_control_t_fifo_modes_T_FIFO_INSERT_4_AM 1 6814 #define rx_x4_fec_control_t_fifo_modes_T_FIFO_INSERT_20_AM 2 6815 #define rx_x4_fec_control_t_fifo_modes_T_FIFO_INSERT_2_AM 3 6816 6817 /**************************************************************************** 6818 * Enums: rx_x4_fec_control_t_enc_modes 6819 */ 6820 #define rx_x4_fec_control_t_enc_modes_T_ENC_MODE_BYPASS 0 6821 #define rx_x4_fec_control_t_enc_modes_T_ENC_MODE_CL49 1 6822 #define rx_x4_fec_control_t_enc_modes_T_ENC_MODE_CL82 2 6823 6824 /**************************************************************************** 6825 * Enums: rx_x4_fec_control_btmx_mode 6826 */ 6827 #define rx_x4_fec_control_btmx_mode_BS_BTMX_MODE_1to1 0 6828 #define rx_x4_fec_control_btmx_mode_BS_BTMX_MODE_2to1 1 6829 #define rx_x4_fec_control_btmx_mode_BS_BTMX_MODE_5to1 2 6830 6831 /**************************************************************************** 6832 * Enums: rx_x4_fec_control_t_type_cl82 6833 */ 6834 #define rx_x4_fec_control_t_type_cl82_T_TYPE_B1 5 6835 #define rx_x4_fec_control_t_type_cl82_T_TYPE_C 4 6836 #define rx_x4_fec_control_t_type_cl82_T_TYPE_S 3 6837 #define rx_x4_fec_control_t_type_cl82_T_TYPE_T 2 6838 #define rx_x4_fec_control_t_type_cl82_T_TYPE_D 1 6839 #define rx_x4_fec_control_t_type_cl82_T_TYPE_E 0 6840 6841 /**************************************************************************** 6842 * Enums: rx_x4_fec_control_txsm_state_cl82 6843 */ 6844 #define rx_x4_fec_control_txsm_state_cl82_TX_HIG_END 6 6845 #define rx_x4_fec_control_txsm_state_cl82_TX_HIG_START 5 6846 #define rx_x4_fec_control_txsm_state_cl82_TX_E 4 6847 #define rx_x4_fec_control_txsm_state_cl82_TX_T 3 6848 #define rx_x4_fec_control_txsm_state_cl82_TX_D 2 6849 #define rx_x4_fec_control_txsm_state_cl82_TX_C 1 6850 #define rx_x4_fec_control_txsm_state_cl82_TX_INIT 0 6851 6852 /**************************************************************************** 6853 * Enums: rx_x4_fec_control_ltxsm_state_cl82 6854 */ 6855 #define rx_x4_fec_control_ltxsm_state_cl82_TX_HIG_END 64 6856 #define rx_x4_fec_control_ltxsm_state_cl82_TX_HIG_START 32 6857 #define rx_x4_fec_control_ltxsm_state_cl82_TX_E 16 6858 #define rx_x4_fec_control_ltxsm_state_cl82_TX_T 8 6859 #define rx_x4_fec_control_ltxsm_state_cl82_TX_D 4 6860 #define rx_x4_fec_control_ltxsm_state_cl82_TX_C 2 6861 #define rx_x4_fec_control_ltxsm_state_cl82_TX_INIT 1 6862 6863 /**************************************************************************** 6864 * Enums: rx_x4_fec_control_r_type_coded_cl82 6865 */ 6866 #define rx_x4_fec_control_r_type_coded_cl82_R_TYPE_B1 32 6867 #define rx_x4_fec_control_r_type_coded_cl82_R_TYPE_C 16 6868 #define rx_x4_fec_control_r_type_coded_cl82_R_TYPE_S 8 6869 #define rx_x4_fec_control_r_type_coded_cl82_R_TYPE_T 4 6870 #define rx_x4_fec_control_r_type_coded_cl82_R_TYPE_D 2 6871 #define rx_x4_fec_control_r_type_coded_cl82_R_TYPE_E 1 6872 6873 /**************************************************************************** 6874 * Enums: rx_x4_fec_control_rxsm_state_cl82 6875 */ 6876 #define rx_x4_fec_control_rxsm_state_cl82_RX_HIG_END 64 6877 #define rx_x4_fec_control_rxsm_state_cl82_RX_HIG_START 32 6878 #define rx_x4_fec_control_rxsm_state_cl82_RX_E 16 6879 #define rx_x4_fec_control_rxsm_state_cl82_RX_T 8 6880 #define rx_x4_fec_control_rxsm_state_cl82_RX_D 4 6881 #define rx_x4_fec_control_rxsm_state_cl82_RX_C 2 6882 #define rx_x4_fec_control_rxsm_state_cl82_RX_INIT 1 6883 6884 /**************************************************************************** 6885 * Enums: rx_x4_fec_control_deskew_state 6886 */ 6887 #define rx_x4_fec_control_deskew_state_ALIGN_ACQUIRED 2 6888 #define rx_x4_fec_control_deskew_state_LOSS_OF_ALIGNMENT 1 6889 6890 /**************************************************************************** 6891 * Enums: rx_x4_fec_control_os_mode_enum 6892 */ 6893 #define rx_x4_fec_control_os_mode_enum_OS_MODE_1 0 6894 #define rx_x4_fec_control_os_mode_enum_OS_MODE_2 1 6895 #define rx_x4_fec_control_os_mode_enum_OS_MODE_4 2 6896 #define rx_x4_fec_control_os_mode_enum_OS_MODE_16p5 8 6897 #define rx_x4_fec_control_os_mode_enum_OS_MODE_20p625 12 6898 6899 /**************************************************************************** 6900 * Enums: rx_x4_fec_control_scr_modes 6901 */ 6902 #define rx_x4_fec_control_scr_modes_T_SCR_MODE_BYPASS 0 6903 #define rx_x4_fec_control_scr_modes_T_SCR_MODE_CL49 1 6904 #define rx_x4_fec_control_scr_modes_T_SCR_MODE_40G_2_LANE 2 6905 #define rx_x4_fec_control_scr_modes_T_SCR_MODE_100G 3 6906 #define rx_x4_fec_control_scr_modes_T_SCR_MODE_20G 4 6907 #define rx_x4_fec_control_scr_modes_T_SCR_MODE_40G_4_LANE 5 6908 6909 /**************************************************************************** 6910 * Enums: rx_x4_fec_control_descr_modes 6911 */ 6912 #define rx_x4_fec_control_descr_modes_R_DESCR_MODE_BYPASS 0 6913 #define rx_x4_fec_control_descr_modes_R_DESCR_MODE_CL49 1 6914 #define rx_x4_fec_control_descr_modes_R_DESCR_MODE_CL82 2 6915 6916 /**************************************************************************** 6917 * Enums: rx_x4_fec_control_r_dec_tl_mode 6918 */ 6919 #define rx_x4_fec_control_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 6920 #define rx_x4_fec_control_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 6921 #define rx_x4_fec_control_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 6922 6923 /**************************************************************************** 6924 * Enums: rx_x4_fec_control_r_dec_fsm_mode 6925 */ 6926 #define rx_x4_fec_control_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 6927 #define rx_x4_fec_control_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 6928 #define rx_x4_fec_control_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 6929 6930 /**************************************************************************** 6931 * Enums: rx_x4_fec_control_r_deskew_mode 6932 */ 6933 #define rx_x4_fec_control_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 6934 #define rx_x4_fec_control_r_deskew_mode_R_DESKEW_MODE_20G 1 6935 #define rx_x4_fec_control_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 6936 #define rx_x4_fec_control_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 6937 #define rx_x4_fec_control_r_deskew_mode_R_DESKEW_MODE_100G 4 6938 #define rx_x4_fec_control_r_deskew_mode_R_DESKEW_MODE_CL49 5 6939 #define rx_x4_fec_control_r_deskew_mode_R_DESKEW_MODE_CL91_QUAD 6 6940 #define rx_x4_fec_control_r_deskew_mode_R_DESKEW_MODE_CL91_SINGLE_BRCM 7 6941 #define rx_x4_fec_control_r_deskew_mode_R_DESKEW_MODE_CL91_DUAL_BRCM 8 6942 #define rx_x4_fec_control_r_deskew_mode_R_DESKEW_MODE_CL91_FC 9 6943 6944 /**************************************************************************** 6945 * Enums: rx_x4_fec_control_bs_dist_modes 6946 */ 6947 #define rx_x4_fec_control_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 6948 #define rx_x4_fec_control_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 6949 #define rx_x4_fec_control_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 6950 #define rx_x4_fec_control_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 6951 6952 /**************************************************************************** 6953 * Enums: rx_x4_fec_control_cl49_t_type 6954 */ 6955 #define rx_x4_fec_control_cl49_t_type_BAD_T_TYPE 15 6956 #define rx_x4_fec_control_cl49_t_type_T_TYPE_B0 11 6957 #define rx_x4_fec_control_cl49_t_type_T_TYPE_OB 10 6958 #define rx_x4_fec_control_cl49_t_type_T_TYPE_B1 9 6959 #define rx_x4_fec_control_cl49_t_type_T_TYPE_DB 8 6960 #define rx_x4_fec_control_cl49_t_type_T_TYPE_FC 7 6961 #define rx_x4_fec_control_cl49_t_type_T_TYPE_TB 6 6962 #define rx_x4_fec_control_cl49_t_type_T_TYPE_LI 5 6963 #define rx_x4_fec_control_cl49_t_type_T_TYPE_C 4 6964 #define rx_x4_fec_control_cl49_t_type_T_TYPE_S 3 6965 #define rx_x4_fec_control_cl49_t_type_T_TYPE_T 2 6966 #define rx_x4_fec_control_cl49_t_type_T_TYPE_D 1 6967 #define rx_x4_fec_control_cl49_t_type_T_TYPE_E 0 6968 6969 /**************************************************************************** 6970 * Enums: rx_x4_fec_control_cl49_txsm_states 6971 */ 6972 #define rx_x4_fec_control_cl49_txsm_states_TX_HIG_END 7 6973 #define rx_x4_fec_control_cl49_txsm_states_TX_HIG_START 6 6974 #define rx_x4_fec_control_cl49_txsm_states_TX_LI 5 6975 #define rx_x4_fec_control_cl49_txsm_states_TX_E 4 6976 #define rx_x4_fec_control_cl49_txsm_states_TX_T 3 6977 #define rx_x4_fec_control_cl49_txsm_states_TX_D 2 6978 #define rx_x4_fec_control_cl49_txsm_states_TX_C 1 6979 #define rx_x4_fec_control_cl49_txsm_states_TX_INIT 0 6980 6981 /**************************************************************************** 6982 * Enums: rx_x4_fec_control_cl49_ltxsm_states 6983 */ 6984 #define rx_x4_fec_control_cl49_ltxsm_states_TX_HIG_END 128 6985 #define rx_x4_fec_control_cl49_ltxsm_states_TX_HIG_START 64 6986 #define rx_x4_fec_control_cl49_ltxsm_states_TX_LI 32 6987 #define rx_x4_fec_control_cl49_ltxsm_states_TX_E 16 6988 #define rx_x4_fec_control_cl49_ltxsm_states_TX_T 8 6989 #define rx_x4_fec_control_cl49_ltxsm_states_TX_D 4 6990 #define rx_x4_fec_control_cl49_ltxsm_states_TX_C 2 6991 #define rx_x4_fec_control_cl49_ltxsm_states_TX_INIT 1 6992 6993 /**************************************************************************** 6994 * Enums: rx_x4_fec_control_burst_error_mode 6995 */ 6996 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_11_BITS 0 6997 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_16_BITS 1 6998 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_17_BITS 2 6999 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_18_BITS 3 7000 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_19_BITS 4 7001 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_20_BITS 5 7002 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_21_BITS 6 7003 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_22_BITS 7 7004 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_23_BITS 8 7005 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_24_BITS 9 7006 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_25_BITS 10 7007 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_26_BITS 11 7008 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_27_BITS 12 7009 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_28_BITS 13 7010 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_29_BITS 14 7011 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_30_BITS 15 7012 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_31_BITS 16 7013 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_32_BITS 17 7014 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_33_BITS 18 7015 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_34_BITS 19 7016 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_35_BITS 20 7017 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_36_BITS 21 7018 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_37_BITS 22 7019 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_38_BITS 23 7020 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_39_BITS 24 7021 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_40_BITS 25 7022 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_41_BITS 26 7023 7024 /**************************************************************************** 7025 * Enums: rx_x4_fec_control_bermon_state 7026 */ 7027 #define rx_x4_fec_control_bermon_state_HI_BER 4 7028 #define rx_x4_fec_control_bermon_state_GOOD_BER 3 7029 #define rx_x4_fec_control_bermon_state_BER_TEST_SH 2 7030 #define rx_x4_fec_control_bermon_state_START_TIMER 1 7031 #define rx_x4_fec_control_bermon_state_BER_MT_INIT 0 7032 7033 /**************************************************************************** 7034 * Enums: rx_x4_fec_control_rxsm_state_cl49 7035 */ 7036 #define rx_x4_fec_control_rxsm_state_cl49_RX_HIG_END 128 7037 #define rx_x4_fec_control_rxsm_state_cl49_RX_HIG_START 64 7038 #define rx_x4_fec_control_rxsm_state_cl49_RX_LI 32 7039 #define rx_x4_fec_control_rxsm_state_cl49_RX_E 16 7040 #define rx_x4_fec_control_rxsm_state_cl49_RX_T 8 7041 #define rx_x4_fec_control_rxsm_state_cl49_RX_D 4 7042 #define rx_x4_fec_control_rxsm_state_cl49_RX_C 2 7043 #define rx_x4_fec_control_rxsm_state_cl49_RX_INIT 1 7044 7045 /**************************************************************************** 7046 * Enums: rx_x4_fec_control_r_type 7047 */ 7048 #define rx_x4_fec_control_r_type_BAD_R_TYPE 15 7049 #define rx_x4_fec_control_r_type_R_TYPE_B0 11 7050 #define rx_x4_fec_control_r_type_R_TYPE_OB 10 7051 #define rx_x4_fec_control_r_type_R_TYPE_B1 9 7052 #define rx_x4_fec_control_r_type_R_TYPE_DB 8 7053 #define rx_x4_fec_control_r_type_R_TYPE_FC 7 7054 #define rx_x4_fec_control_r_type_R_TYPE_TB 6 7055 #define rx_x4_fec_control_r_type_R_TYPE_LI 5 7056 #define rx_x4_fec_control_r_type_R_TYPE_C 4 7057 #define rx_x4_fec_control_r_type_R_TYPE_S 3 7058 #define rx_x4_fec_control_r_type_R_TYPE_T 2 7059 #define rx_x4_fec_control_r_type_R_TYPE_D 1 7060 #define rx_x4_fec_control_r_type_R_TYPE_E 0 7061 7062 /**************************************************************************** 7063 * Enums: rx_x4_fec_control_am_lock_state 7064 */ 7065 #define rx_x4_fec_control_am_lock_state_INVALID_AM 512 7066 #define rx_x4_fec_control_am_lock_state_GOOD_AM 256 7067 #define rx_x4_fec_control_am_lock_state_COMP_AM 128 7068 #define rx_x4_fec_control_am_lock_state_TIMER_2 64 7069 #define rx_x4_fec_control_am_lock_state_AM_2_GOOD 32 7070 #define rx_x4_fec_control_am_lock_state_COMP_2ND 16 7071 #define rx_x4_fec_control_am_lock_state_TIMER_1 8 7072 #define rx_x4_fec_control_am_lock_state_FIND_1ST 4 7073 #define rx_x4_fec_control_am_lock_state_AM_RESET_CNT 2 7074 #define rx_x4_fec_control_am_lock_state_AM_LOCK_INIT 1 7075 7076 /**************************************************************************** 7077 * Enums: rx_x4_fec_control_msg_selector 7078 */ 7079 #define rx_x4_fec_control_msg_selector_RESERVED 0 7080 #define rx_x4_fec_control_msg_selector_VALUE_802p3 1 7081 #define rx_x4_fec_control_msg_selector_VALUE_802p9 2 7082 #define rx_x4_fec_control_msg_selector_VALUE_802p5 3 7083 #define rx_x4_fec_control_msg_selector_VALUE_1394 4 7084 7085 /**************************************************************************** 7086 * Enums: rx_x4_fec_control_synce_enum 7087 */ 7088 #define rx_x4_fec_control_synce_enum_SYNCE_NO_DIV 0 7089 #define rx_x4_fec_control_synce_enum_SYNCE_DIV_7 1 7090 #define rx_x4_fec_control_synce_enum_SYNCE_DIV_11 2 7091 7092 /**************************************************************************** 7093 * Enums: rx_x4_fec_control_synce_enum_stage0 7094 */ 7095 #define rx_x4_fec_control_synce_enum_stage0_SYNCE_NO_DIV 0 7096 #define rx_x4_fec_control_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 7097 #define rx_x4_fec_control_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 7098 7099 /**************************************************************************** 7100 * Enums: rx_x4_fec_control_cl91_sync_state 7101 */ 7102 #define rx_x4_fec_control_cl91_sync_state_FIND_1ST 0 7103 #define rx_x4_fec_control_cl91_sync_state_COUNT_NEXT 1 7104 #define rx_x4_fec_control_cl91_sync_state_COMP_2ND 2 7105 #define rx_x4_fec_control_cl91_sync_state_TWO_GOOD 3 7106 7107 /**************************************************************************** 7108 * Enums: rx_x4_fec_control_cl91_algn_state 7109 */ 7110 #define rx_x4_fec_control_cl91_algn_state_LOSS_OF_ALIGNMENT 0 7111 #define rx_x4_fec_control_cl91_algn_state_DESKEW 1 7112 #define rx_x4_fec_control_cl91_algn_state_DESKEW_FAIL 2 7113 #define rx_x4_fec_control_cl91_algn_state_ALIGN_ACQUIRED 3 7114 #define rx_x4_fec_control_cl91_algn_state_CW_GOOD 4 7115 #define rx_x4_fec_control_cl91_algn_state_CW_BAD 5 7116 #define rx_x4_fec_control_cl91_algn_state_THREE_BAD 6 7117 7118 /**************************************************************************** 7119 * Enums: rx_x4_fec_control_fec_sel_override 7120 */ 7121 #define rx_x4_fec_control_fec_sel_override_NO_OVERRIDE 0 7122 #define rx_x4_fec_control_fec_sel_override_NO_FEC 1 7123 #define rx_x4_fec_control_fec_sel_override_FEC_CL74 2 7124 #define rx_x4_fec_control_fec_sel_override_FEC_CL91 3 7125 7126 /**************************************************************************** 7127 * Enums: rx_x4_fec_control_cl91_blksync_mode 7128 */ 7129 #define rx_x4_fec_control_cl91_blksync_mode_R_BLKSYNC_NO_CL91_FEC 0 7130 #define rx_x4_fec_control_cl91_blksync_mode_R_BLKSYNC_CL91_QUAD_LANE_FEC 1 7131 #define rx_x4_fec_control_cl91_blksync_mode_R_BLKSYNC_CL91_DUAL_LANE_FEC 2 7132 #define rx_x4_fec_control_cl91_blksync_mode_R_BLKSYNC_CL91_SINGLE_LANE_FEC 3 7133 #define rx_x4_fec_control_cl91_blksync_mode_R_BLKSYNC_CL91_FC_FEC 4 7134 7135 /**************************************************************************** 7136 * Enums: rx_x4_fec_control_r_merge_mode 7137 */ 7138 #define rx_x4_fec_control_r_merge_mode_R_MERGE_MODE_BYPASS 0 7139 #define rx_x4_fec_control_r_merge_mode_R_MERGE_MODE_CL91_FC 1 7140 #define rx_x4_fec_control_r_merge_mode_R_MERGE_MODE_CL91_SINGLE_LANE 2 7141 #define rx_x4_fec_control_r_merge_mode_R_MERGE_MODE_CL91_DUAL_LANE 3 7142 #define rx_x4_fec_control_r_merge_mode_R_MERGE_MODE_CL91_QUAD_LANE 4 7143 7144 /**************************************************************************** 7145 * Enums: rx_x4_fec_control_r_tc_mode 7146 */ 7147 #define rx_x4_fec_control_r_tc_mode_R_TC_MODE_SINGLE 0 7148 #define rx_x4_fec_control_r_tc_mode_R_TC_MODE_DUAL 1 7149 #define rx_x4_fec_control_r_tc_mode_R_TC_MODE_QUAD 2 7150 7151 /**************************************************************************** 7152 * Enums: rx_x4_fec_control_r_tc_out_mode 7153 */ 7154 #define rx_x4_fec_control_r_tc_out_mode_R_TC_OUT_MODE_SINGLE 0 7155 #define rx_x4_fec_control_r_tc_out_mode_R_TC_OUT_MODE_DUAL 1 7156 #define rx_x4_fec_control_r_tc_out_mode_R_TC_OUT_MODE_QUAD 2 7157 7158 /**************************************************************************** 7159 * Enums: rx_x4_fec_control_cl91_fec_mode 7160 */ 7161 #define rx_x4_fec_control_cl91_fec_mode_NO_CL91_FEC 0 7162 #define rx_x4_fec_control_cl91_fec_mode_CL91_SINGLE_LANE_FC 1 7163 #define rx_x4_fec_control_cl91_fec_mode_CL91_SINGLE_LANE_BRCM_PROP 2 7164 #define rx_x4_fec_control_cl91_fec_mode_CL91_DUAL_LANE_BRCM_PROP 3 7165 #define rx_x4_fec_control_cl91_fec_mode_CL91_QUAD_LANE 4 7166 #define rx_x4_fec_control_cl91_fec_mode_IEEE_25G_CL91_SINGLE_LANE 5 7167 7168 /**************************************************************************** 7169 * Enums: rx_x4_fec_control_am_spacing_mul 7170 */ 7171 #define rx_x4_fec_control_am_spacing_mul_AM_SPACING_MUL_2 0 7172 #define rx_x4_fec_control_am_spacing_mul_AM_SPACING_MUL_4 1 7173 #define rx_x4_fec_control_am_spacing_mul_AM_SPACING_MUL_5 2 7174 #define rx_x4_fec_control_am_spacing_mul_AM_SPACING_MUL_20 3 7175 7176 /**************************************************************************** 7177 * Enums: rx_x4_status1_cl36TxEEEStates_l 7178 */ 7179 #define rx_x4_status1_cl36TxEEEStates_l_TX_REFRESH 8 7180 #define rx_x4_status1_cl36TxEEEStates_l_TX_QUIET 4 7181 #define rx_x4_status1_cl36TxEEEStates_l_TX_SLEEP 2 7182 #define rx_x4_status1_cl36TxEEEStates_l_TX_ACTIVE 1 7183 7184 /**************************************************************************** 7185 * Enums: rx_x4_status1_cl36TxEEEStates_c 7186 */ 7187 #define rx_x4_status1_cl36TxEEEStates_c_TX_REFRESH 3 7188 #define rx_x4_status1_cl36TxEEEStates_c_TX_QUIET 2 7189 #define rx_x4_status1_cl36TxEEEStates_c_TX_SLEEP 1 7190 #define rx_x4_status1_cl36TxEEEStates_c_TX_ACTIVE 0 7191 7192 /**************************************************************************** 7193 * Enums: rx_x4_status1_cl49TxEEEStates_l 7194 */ 7195 #define rx_x4_status1_cl49TxEEEStates_l_SCR_RESET_2 64 7196 #define rx_x4_status1_cl49TxEEEStates_l_SCR_RESET_1 32 7197 #define rx_x4_status1_cl49TxEEEStates_l_TX_WAKE 16 7198 #define rx_x4_status1_cl49TxEEEStates_l_TX_REFRESH 8 7199 #define rx_x4_status1_cl49TxEEEStates_l_TX_QUIET 4 7200 #define rx_x4_status1_cl49TxEEEStates_l_TX_SLEEP 2 7201 #define rx_x4_status1_cl49TxEEEStates_l_TX_ACTIVE 1 7202 7203 /**************************************************************************** 7204 * Enums: rx_x4_status1_fec_req_enum 7205 */ 7206 #define rx_x4_status1_fec_req_enum_FEC_not_supported 0 7207 #define rx_x4_status1_fec_req_enum_FEC_supported_but_not_requested 1 7208 #define rx_x4_status1_fec_req_enum_invalid_setting 2 7209 #define rx_x4_status1_fec_req_enum_FEC_supported_and_requested 3 7210 7211 /**************************************************************************** 7212 * Enums: rx_x4_status1_cl73_pause_enum 7213 */ 7214 #define rx_x4_status1_cl73_pause_enum_No_PAUSE_ability 0 7215 #define rx_x4_status1_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 7216 #define rx_x4_status1_cl73_pause_enum_Symmetric_PAUSE_ability 1 7217 #define rx_x4_status1_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 7218 7219 /**************************************************************************** 7220 * Enums: rx_x4_status1_cl49TxEEEStates_c 7221 */ 7222 #define rx_x4_status1_cl49TxEEEStates_c_SCR_RESET_2 6 7223 #define rx_x4_status1_cl49TxEEEStates_c_SCR_RESET_1 5 7224 #define rx_x4_status1_cl49TxEEEStates_c_TX_WAKE 4 7225 #define rx_x4_status1_cl49TxEEEStates_c_TX_REFRESH 3 7226 #define rx_x4_status1_cl49TxEEEStates_c_TX_QUIET 2 7227 #define rx_x4_status1_cl49TxEEEStates_c_TX_SLEEP 1 7228 #define rx_x4_status1_cl49TxEEEStates_c_TX_ACTIVE 0 7229 7230 /**************************************************************************** 7231 * Enums: rx_x4_status1_cl36RxEEEStates_l 7232 */ 7233 #define rx_x4_status1_cl36RxEEEStates_l_RX_LINK_FAIL 32 7234 #define rx_x4_status1_cl36RxEEEStates_l_RX_WTF 16 7235 #define rx_x4_status1_cl36RxEEEStates_l_RX_WAKE 8 7236 #define rx_x4_status1_cl36RxEEEStates_l_RX_QUIET 4 7237 #define rx_x4_status1_cl36RxEEEStates_l_RX_SLEEP 2 7238 #define rx_x4_status1_cl36RxEEEStates_l_RX_ACTIVE 1 7239 7240 /**************************************************************************** 7241 * Enums: rx_x4_status1_cl36RxEEEStates_c 7242 */ 7243 #define rx_x4_status1_cl36RxEEEStates_c_RX_LINK_FAIL 5 7244 #define rx_x4_status1_cl36RxEEEStates_c_RX_WTF 4 7245 #define rx_x4_status1_cl36RxEEEStates_c_RX_WAKE 3 7246 #define rx_x4_status1_cl36RxEEEStates_c_RX_QUIET 2 7247 #define rx_x4_status1_cl36RxEEEStates_c_RX_SLEEP 1 7248 #define rx_x4_status1_cl36RxEEEStates_c_RX_ACTIVE 0 7249 7250 /**************************************************************************** 7251 * Enums: rx_x4_status1_cl49RxEEEStates_l 7252 */ 7253 #define rx_x4_status1_cl49RxEEEStates_l_RX_LINK_FAIL 32 7254 #define rx_x4_status1_cl49RxEEEStates_l_RX_WTF 16 7255 #define rx_x4_status1_cl49RxEEEStates_l_RX_WAKE 8 7256 #define rx_x4_status1_cl49RxEEEStates_l_RX_QUIET 4 7257 #define rx_x4_status1_cl49RxEEEStates_l_RX_SLEEP 2 7258 #define rx_x4_status1_cl49RxEEEStates_l_RX_ACTIVE 1 7259 7260 /**************************************************************************** 7261 * Enums: rx_x4_status1_cl49RxEEEStates_c 7262 */ 7263 #define rx_x4_status1_cl49RxEEEStates_c_RX_LINK_FAIL 5 7264 #define rx_x4_status1_cl49RxEEEStates_c_RX_WTF 4 7265 #define rx_x4_status1_cl49RxEEEStates_c_RX_WAKE 3 7266 #define rx_x4_status1_cl49RxEEEStates_c_RX_QUIET 2 7267 #define rx_x4_status1_cl49RxEEEStates_c_RX_SLEEP 1 7268 #define rx_x4_status1_cl49RxEEEStates_c_RX_ACTIVE 0 7269 7270 /**************************************************************************** 7271 * Enums: rx_x4_status1_cl48TxEEEStates_l 7272 */ 7273 #define rx_x4_status1_cl48TxEEEStates_l_TX_REFRESH 8 7274 #define rx_x4_status1_cl48TxEEEStates_l_TX_QUIET 4 7275 #define rx_x4_status1_cl48TxEEEStates_l_TX_SLEEP 2 7276 #define rx_x4_status1_cl48TxEEEStates_l_TX_ACTIVE 1 7277 7278 /**************************************************************************** 7279 * Enums: rx_x4_status1_cl48TxEEEStates_c 7280 */ 7281 #define rx_x4_status1_cl48TxEEEStates_c_TX_REFRESH 3 7282 #define rx_x4_status1_cl48TxEEEStates_c_TX_QUIET 2 7283 #define rx_x4_status1_cl48TxEEEStates_c_TX_SLEEP 1 7284 #define rx_x4_status1_cl48TxEEEStates_c_TX_ACTIVE 0 7285 7286 /**************************************************************************** 7287 * Enums: rx_x4_status1_cl48RxEEEStates_l 7288 */ 7289 #define rx_x4_status1_cl48RxEEEStates_l_RX_LINK_FAIL 32 7290 #define rx_x4_status1_cl48RxEEEStates_l_RX_WAKE 16 7291 #define rx_x4_status1_cl48RxEEEStates_l_RX_QUIET 8 7292 #define rx_x4_status1_cl48RxEEEStates_l_RX_DEACT 4 7293 #define rx_x4_status1_cl48RxEEEStates_l_RX_SLEEP 2 7294 #define rx_x4_status1_cl48RxEEEStates_l_RX_ACTIVE 1 7295 7296 /**************************************************************************** 7297 * Enums: rx_x4_status1_cl48RxEEEStates_c 7298 */ 7299 #define rx_x4_status1_cl48RxEEEStates_c_RX_LINK_FAIL 5 7300 #define rx_x4_status1_cl48RxEEEStates_c_RX_WAKE 4 7301 #define rx_x4_status1_cl48RxEEEStates_c_RX_QUIET 3 7302 #define rx_x4_status1_cl48RxEEEStates_c_RX_DEACT 2 7303 #define rx_x4_status1_cl48RxEEEStates_c_RX_SLEEP 1 7304 #define rx_x4_status1_cl48RxEEEStates_c_RX_ACTIVE 0 7305 7306 /**************************************************************************** 7307 * Enums: rx_x4_status1_IQP_Options 7308 */ 7309 #define rx_x4_status1_IQP_Options_i50uA 0 7310 #define rx_x4_status1_IQP_Options_i100uA 1 7311 #define rx_x4_status1_IQP_Options_i150uA 2 7312 #define rx_x4_status1_IQP_Options_i200uA 3 7313 #define rx_x4_status1_IQP_Options_i250uA 4 7314 #define rx_x4_status1_IQP_Options_i300uA 5 7315 #define rx_x4_status1_IQP_Options_i350uA 6 7316 #define rx_x4_status1_IQP_Options_i400uA 7 7317 #define rx_x4_status1_IQP_Options_i450uA 8 7318 #define rx_x4_status1_IQP_Options_i500uA 9 7319 #define rx_x4_status1_IQP_Options_i550uA 10 7320 #define rx_x4_status1_IQP_Options_i600uA 11 7321 #define rx_x4_status1_IQP_Options_i650uA 12 7322 #define rx_x4_status1_IQP_Options_i700uA 13 7323 #define rx_x4_status1_IQP_Options_i750uA 14 7324 #define rx_x4_status1_IQP_Options_i800uA 15 7325 7326 /**************************************************************************** 7327 * Enums: rx_x4_status1_IDriver_Options 7328 */ 7329 #define rx_x4_status1_IDriver_Options_v680mV 0 7330 #define rx_x4_status1_IDriver_Options_v730mV 1 7331 #define rx_x4_status1_IDriver_Options_v780mV 2 7332 #define rx_x4_status1_IDriver_Options_v830mV 3 7333 #define rx_x4_status1_IDriver_Options_v880mV 4 7334 #define rx_x4_status1_IDriver_Options_v930mV 5 7335 #define rx_x4_status1_IDriver_Options_v980mV 6 7336 #define rx_x4_status1_IDriver_Options_v1010mV 7 7337 #define rx_x4_status1_IDriver_Options_v1040mV 8 7338 #define rx_x4_status1_IDriver_Options_v1060mV 9 7339 #define rx_x4_status1_IDriver_Options_v1070mV 10 7340 #define rx_x4_status1_IDriver_Options_v1080mV 11 7341 #define rx_x4_status1_IDriver_Options_v1085mV 12 7342 #define rx_x4_status1_IDriver_Options_v1090mV 13 7343 #define rx_x4_status1_IDriver_Options_v1095mV 14 7344 #define rx_x4_status1_IDriver_Options_v1100mV 15 7345 7346 /**************************************************************************** 7347 * Enums: rx_x4_status1_operationModes 7348 */ 7349 #define rx_x4_status1_operationModes_XGXS 0 7350 #define rx_x4_status1_operationModes_XGXG_nCC 1 7351 #define rx_x4_status1_operationModes_Indlane_OS8 4 7352 #define rx_x4_status1_operationModes_IndLane_OS5 5 7353 #define rx_x4_status1_operationModes_PCI 7 7354 #define rx_x4_status1_operationModes_XGXS_nLQ 8 7355 #define rx_x4_status1_operationModes_XGXS_nLQnCC 9 7356 #define rx_x4_status1_operationModes_PBypass 10 7357 #define rx_x4_status1_operationModes_PBypass_nDSK 11 7358 #define rx_x4_status1_operationModes_ComboCoreMode 12 7359 #define rx_x4_status1_operationModes_Clocks_off 15 7360 7361 /**************************************************************************** 7362 * Enums: rx_x4_status1_actualSpeeds 7363 */ 7364 #define rx_x4_status1_actualSpeeds_dr_10M 0 7365 #define rx_x4_status1_actualSpeeds_dr_100M 1 7366 #define rx_x4_status1_actualSpeeds_dr_1G 2 7367 #define rx_x4_status1_actualSpeeds_dr_2p5G 3 7368 #define rx_x4_status1_actualSpeeds_dr_5G_X4 4 7369 #define rx_x4_status1_actualSpeeds_dr_6G_X4 5 7370 #define rx_x4_status1_actualSpeeds_dr_10G_HiG 6 7371 #define rx_x4_status1_actualSpeeds_dr_10G_CX4 7 7372 #define rx_x4_status1_actualSpeeds_dr_12G_HiG 8 7373 #define rx_x4_status1_actualSpeeds_dr_12p5G_X4 9 7374 #define rx_x4_status1_actualSpeeds_dr_13G_X4 10 7375 #define rx_x4_status1_actualSpeeds_dr_15G_X4 11 7376 #define rx_x4_status1_actualSpeeds_dr_16G_X4 12 7377 #define rx_x4_status1_actualSpeeds_dr_1G_KX 13 7378 #define rx_x4_status1_actualSpeeds_dr_10G_KX4 14 7379 #define rx_x4_status1_actualSpeeds_dr_10G_KR 15 7380 #define rx_x4_status1_actualSpeeds_dr_5G 16 7381 #define rx_x4_status1_actualSpeeds_dr_6p4G 17 7382 #define rx_x4_status1_actualSpeeds_dr_20G_X4 18 7383 #define rx_x4_status1_actualSpeeds_dr_21G_X4 19 7384 #define rx_x4_status1_actualSpeeds_dr_25G_X4 20 7385 #define rx_x4_status1_actualSpeeds_dr_10G_HiG_DXGXS 21 7386 #define rx_x4_status1_actualSpeeds_dr_10G_DXGXS 22 7387 #define rx_x4_status1_actualSpeeds_dr_10p5G_HiG_DXGXS 23 7388 #define rx_x4_status1_actualSpeeds_dr_10p5G_DXGXS 24 7389 #define rx_x4_status1_actualSpeeds_dr_12p773G_HiG_DXGXS 25 7390 #define rx_x4_status1_actualSpeeds_dr_12p773G_DXGXS 26 7391 #define rx_x4_status1_actualSpeeds_dr_10G_XFI 27 7392 #define rx_x4_status1_actualSpeeds_dr_40G 28 7393 #define rx_x4_status1_actualSpeeds_dr_20G_HiG_DXGXS 29 7394 #define rx_x4_status1_actualSpeeds_dr_20G_DXGXS 30 7395 #define rx_x4_status1_actualSpeeds_dr_10G_SFI 31 7396 #define rx_x4_status1_actualSpeeds_dr_31p5G 32 7397 #define rx_x4_status1_actualSpeeds_dr_32p7G 33 7398 #define rx_x4_status1_actualSpeeds_dr_20G_SCR 34 7399 #define rx_x4_status1_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 7400 #define rx_x4_status1_actualSpeeds_dr_10G_DXGXS_SCR 36 7401 #define rx_x4_status1_actualSpeeds_dr_12G_R2 37 7402 #define rx_x4_status1_actualSpeeds_dr_10G_X2 38 7403 #define rx_x4_status1_actualSpeeds_dr_40G_KR4 39 7404 #define rx_x4_status1_actualSpeeds_dr_40G_CR4 40 7405 #define rx_x4_status1_actualSpeeds_dr_100G_CR10 41 7406 #define rx_x4_status1_actualSpeeds_dr_15p75G_DXGXS 44 7407 #define rx_x4_status1_actualSpeeds_dr_20G_KR2 57 7408 #define rx_x4_status1_actualSpeeds_dr_20G_CR2 58 7409 7410 /**************************************************************************** 7411 * Enums: rx_x4_status1_actualSpeedsMisc1 7412 */ 7413 #define rx_x4_status1_actualSpeedsMisc1_dr_2500BRCM_X1 16 7414 #define rx_x4_status1_actualSpeedsMisc1_dr_5000BRCM_X4 17 7415 #define rx_x4_status1_actualSpeedsMisc1_dr_6000BRCM_X4 18 7416 #define rx_x4_status1_actualSpeedsMisc1_dr_10GHiGig_X4 19 7417 #define rx_x4_status1_actualSpeedsMisc1_dr_10GBASE_CX4 20 7418 #define rx_x4_status1_actualSpeedsMisc1_dr_12GHiGig_X4 21 7419 #define rx_x4_status1_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 7420 #define rx_x4_status1_actualSpeedsMisc1_dr_13GHiGig_X4 23 7421 #define rx_x4_status1_actualSpeedsMisc1_dr_15GHiGig_X4 24 7422 #define rx_x4_status1_actualSpeedsMisc1_dr_16GHiGig_X4 25 7423 #define rx_x4_status1_actualSpeedsMisc1_dr_5000BRCM_X1 26 7424 #define rx_x4_status1_actualSpeedsMisc1_dr_6363BRCM_X1 27 7425 #define rx_x4_status1_actualSpeedsMisc1_dr_20GHiGig_X4 28 7426 #define rx_x4_status1_actualSpeedsMisc1_dr_21GHiGig_X4 29 7427 #define rx_x4_status1_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 7428 #define rx_x4_status1_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 7429 7430 /**************************************************************************** 7431 * Enums: rx_x4_status1_IndLaneModes 7432 */ 7433 #define rx_x4_status1_IndLaneModes_SWSDR_div2 0 7434 #define rx_x4_status1_IndLaneModes_SWSDR_div1 1 7435 #define rx_x4_status1_IndLaneModes_DWSDR_div2 2 7436 #define rx_x4_status1_IndLaneModes_DWSDR_div1 3 7437 7438 /**************************************************************************** 7439 * Enums: rx_x4_status1_prbsSelect 7440 */ 7441 #define rx_x4_status1_prbsSelect_prbs7 0 7442 #define rx_x4_status1_prbsSelect_prbs15 1 7443 #define rx_x4_status1_prbsSelect_prbs23 2 7444 #define rx_x4_status1_prbsSelect_prbs31 3 7445 7446 /**************************************************************************** 7447 * Enums: rx_x4_status1_vcoDivider 7448 */ 7449 #define rx_x4_status1_vcoDivider_div32 0 7450 #define rx_x4_status1_vcoDivider_div36 1 7451 #define rx_x4_status1_vcoDivider_div40 2 7452 #define rx_x4_status1_vcoDivider_div42 3 7453 #define rx_x4_status1_vcoDivider_div48 4 7454 #define rx_x4_status1_vcoDivider_div50 5 7455 #define rx_x4_status1_vcoDivider_div52 6 7456 #define rx_x4_status1_vcoDivider_div54 7 7457 #define rx_x4_status1_vcoDivider_div60 8 7458 #define rx_x4_status1_vcoDivider_div64 9 7459 #define rx_x4_status1_vcoDivider_div66 10 7460 #define rx_x4_status1_vcoDivider_div68 11 7461 #define rx_x4_status1_vcoDivider_div70 12 7462 #define rx_x4_status1_vcoDivider_div80 13 7463 #define rx_x4_status1_vcoDivider_div92 14 7464 #define rx_x4_status1_vcoDivider_div100 15 7465 7466 /**************************************************************************** 7467 * Enums: rx_x4_status1_refClkSelect 7468 */ 7469 #define rx_x4_status1_refClkSelect_clk_25MHz 0 7470 #define rx_x4_status1_refClkSelect_clk_100MHz 1 7471 #define rx_x4_status1_refClkSelect_clk_125MHz 2 7472 #define rx_x4_status1_refClkSelect_clk_156p25MHz 3 7473 #define rx_x4_status1_refClkSelect_clk_187p5MHz 4 7474 #define rx_x4_status1_refClkSelect_clk_161p25Mhz 5 7475 #define rx_x4_status1_refClkSelect_clk_50Mhz 6 7476 #define rx_x4_status1_refClkSelect_clk_106p25Mhz 7 7477 7478 /**************************************************************************** 7479 * Enums: rx_x4_status1_aerMMDdevTypeSelect 7480 */ 7481 #define rx_x4_status1_aerMMDdevTypeSelect_combo_core 0 7482 #define rx_x4_status1_aerMMDdevTypeSelect_PMA_PMD 1 7483 #define rx_x4_status1_aerMMDdevTypeSelect_PCS 3 7484 #define rx_x4_status1_aerMMDdevTypeSelect_PHY 4 7485 #define rx_x4_status1_aerMMDdevTypeSelect_DTE 5 7486 #define rx_x4_status1_aerMMDdevTypeSelect_CL73_AN 7 7487 7488 /**************************************************************************** 7489 * Enums: rx_x4_status1_aerMMDportSelect 7490 */ 7491 #define rx_x4_status1_aerMMDportSelect_ln0 0 7492 #define rx_x4_status1_aerMMDportSelect_ln1 1 7493 #define rx_x4_status1_aerMMDportSelect_ln2 2 7494 #define rx_x4_status1_aerMMDportSelect_ln3 3 7495 #define rx_x4_status1_aerMMDportSelect_BCST_ln0_1_2_3 511 7496 #define rx_x4_status1_aerMMDportSelect_BCST_ln0_1 512 7497 #define rx_x4_status1_aerMMDportSelect_BCST_ln2_3 513 7498 7499 /**************************************************************************** 7500 * Enums: rx_x4_status1_firmwareModeSelect 7501 */ 7502 #define rx_x4_status1_firmwareModeSelect_DEFAULT 0 7503 #define rx_x4_status1_firmwareModeSelect_SFP_OPT_LR 1 7504 #define rx_x4_status1_firmwareModeSelect_SFP_DAC 2 7505 #define rx_x4_status1_firmwareModeSelect_XLAUI 3 7506 #define rx_x4_status1_firmwareModeSelect_LONG_CH_6G 4 7507 7508 /**************************************************************************** 7509 * Enums: rx_x4_status1_tempIdxSelect 7510 */ 7511 #define rx_x4_status1_tempIdxSelect_LTE__22p9C 15 7512 #define rx_x4_status1_tempIdxSelect_LTE__12p6C 14 7513 #define rx_x4_status1_tempIdxSelect_LTE__3p0C 13 7514 #define rx_x4_status1_tempIdxSelect_LTE_6p7C 12 7515 #define rx_x4_status1_tempIdxSelect_LTE_16p4C 11 7516 #define rx_x4_status1_tempIdxSelect_LTE_26p6C 10 7517 #define rx_x4_status1_tempIdxSelect_LTE_36p3C 9 7518 #define rx_x4_status1_tempIdxSelect_LTE_46p0C 8 7519 #define rx_x4_status1_tempIdxSelect_LTE_56p2C 7 7520 #define rx_x4_status1_tempIdxSelect_LTE_65p9C 6 7521 #define rx_x4_status1_tempIdxSelect_LTE_75p6C 5 7522 #define rx_x4_status1_tempIdxSelect_LTE_85p3C 4 7523 #define rx_x4_status1_tempIdxSelect_LTE_95p5C 3 7524 #define rx_x4_status1_tempIdxSelect_LTE_105p2C 2 7525 #define rx_x4_status1_tempIdxSelect_LTE_114p9C 1 7526 #define rx_x4_status1_tempIdxSelect_LTE_125p1C 0 7527 7528 /**************************************************************************** 7529 * Enums: rx_x4_status1_port_mode 7530 */ 7531 #define rx_x4_status1_port_mode_QUAD_PORT 0 7532 #define rx_x4_status1_port_mode_TRI_1_PORT 1 7533 #define rx_x4_status1_port_mode_TRI_2_PORT 2 7534 #define rx_x4_status1_port_mode_DUAL_PORT 3 7535 #define rx_x4_status1_port_mode_SINGLE_PORT 4 7536 7537 /**************************************************************************** 7538 * Enums: rx_x4_status1_rev_letter_enum 7539 */ 7540 #define rx_x4_status1_rev_letter_enum_REV_A 0 7541 #define rx_x4_status1_rev_letter_enum_REV_B 1 7542 #define rx_x4_status1_rev_letter_enum_REV_C 2 7543 #define rx_x4_status1_rev_letter_enum_REV_D 3 7544 7545 /**************************************************************************** 7546 * Enums: rx_x4_status1_rev_number_enum 7547 */ 7548 #define rx_x4_status1_rev_number_enum_REV_0 0 7549 #define rx_x4_status1_rev_number_enum_REV_1 1 7550 #define rx_x4_status1_rev_number_enum_REV_2 2 7551 #define rx_x4_status1_rev_number_enum_REV_3 3 7552 #define rx_x4_status1_rev_number_enum_REV_4 4 7553 #define rx_x4_status1_rev_number_enum_REV_5 5 7554 #define rx_x4_status1_rev_number_enum_REV_6 6 7555 #define rx_x4_status1_rev_number_enum_REV_7 7 7556 7557 /**************************************************************************** 7558 * Enums: rx_x4_status1_bonding_enum 7559 */ 7560 #define rx_x4_status1_bonding_enum_WIRE_BOND 0 7561 #define rx_x4_status1_bonding_enum_FLIP_CHIP 1 7562 7563 /**************************************************************************** 7564 * Enums: rx_x4_status1_tech_process 7565 */ 7566 #define rx_x4_status1_tech_process_PROCESS_90NM 0 7567 #define rx_x4_status1_tech_process_PROCESS_65NM 1 7568 #define rx_x4_status1_tech_process_PROCESS_40NM 2 7569 #define rx_x4_status1_tech_process_PROCESS_28NM 3 7570 #define rx_x4_status1_tech_process_PROCESS_16NM 4 7571 7572 /**************************************************************************** 7573 * Enums: rx_x4_status1_model_num 7574 */ 7575 #define rx_x4_status1_model_num_SERDES_CL73 0 7576 #define rx_x4_status1_model_num_XGXS_16G 1 7577 #define rx_x4_status1_model_num_HYPERCORE 2 7578 #define rx_x4_status1_model_num_HYPERLITE 3 7579 #define rx_x4_status1_model_num_PCIE_G2_PIPE 4 7580 #define rx_x4_status1_model_num_SERDES_1p25GBd 5 7581 #define rx_x4_status1_model_num_SATA2 6 7582 #define rx_x4_status1_model_num_QSGMII 7 7583 #define rx_x4_status1_model_num_XGXS10G 8 7584 #define rx_x4_status1_model_num_WARPCORE 9 7585 #define rx_x4_status1_model_num_XFICORE 10 7586 #define rx_x4_status1_model_num_RXFI 11 7587 #define rx_x4_status1_model_num_WARPLITE 12 7588 #define rx_x4_status1_model_num_PENTACORE 13 7589 #define rx_x4_status1_model_num_ESM 14 7590 #define rx_x4_status1_model_num_QUAD_SGMII 15 7591 #define rx_x4_status1_model_num_WARPCORE_3 16 7592 #define rx_x4_status1_model_num_TSC 17 7593 #define rx_x4_status1_model_num_TSC4E 18 7594 #define rx_x4_status1_model_num_TSC12E 19 7595 #define rx_x4_status1_model_num_TSC4F 20 7596 #define rx_x4_status1_model_num_TSC4F_GEN2 21 7597 #define rx_x4_status1_model_num_XGXS_CL73_90NM 29 7598 #define rx_x4_status1_model_num_SERDES_CL73_90NM 30 7599 #define rx_x4_status1_model_num_WARPCORE3 32 7600 #define rx_x4_status1_model_num_WARPCORE4_TSC 33 7601 #define rx_x4_status1_model_num_RXAUI 34 7602 7603 /**************************************************************************** 7604 * Enums: rx_x4_status1_payload 7605 */ 7606 #define rx_x4_status1_payload_REPEAT_2_BYTES 0 7607 #define rx_x4_status1_payload_RAMPING 1 7608 #define rx_x4_status1_payload_CL48_CRPAT 2 7609 #define rx_x4_status1_payload_CL48_CJPAT 3 7610 #define rx_x4_status1_payload_CL36_LONG_CRPAT 4 7611 #define rx_x4_status1_payload_CL36_SHORT_CRPAT 5 7612 7613 /**************************************************************************** 7614 * Enums: rx_x4_status1_sc 7615 */ 7616 #define rx_x4_status1_sc_S_10G_CR1 0 7617 #define rx_x4_status1_sc_S_10G_KR1 1 7618 #define rx_x4_status1_sc_S_10G_X1 2 7619 #define rx_x4_status1_sc_S_10G_HG2_CR1 4 7620 #define rx_x4_status1_sc_S_10G_HG2_KR1 5 7621 #define rx_x4_status1_sc_S_10G_HG2_X1 6 7622 #define rx_x4_status1_sc_S_20G_CR1 8 7623 #define rx_x4_status1_sc_S_20G_KR1 9 7624 #define rx_x4_status1_sc_S_20G_X1 10 7625 #define rx_x4_status1_sc_S_20G_HG2_CR1 12 7626 #define rx_x4_status1_sc_S_20G_HG2_KR1 13 7627 #define rx_x4_status1_sc_S_20G_HG2_X1 14 7628 #define rx_x4_status1_sc_S_25G_CR1 16 7629 #define rx_x4_status1_sc_S_25G_KR1 17 7630 #define rx_x4_status1_sc_S_25G_X1 18 7631 #define rx_x4_status1_sc_S_25G_HG2_CR1 20 7632 #define rx_x4_status1_sc_S_25G_HG2_KR1 21 7633 #define rx_x4_status1_sc_S_25G_HG2_X1 22 7634 #define rx_x4_status1_sc_S_20G_CR2 24 7635 #define rx_x4_status1_sc_S_20G_KR2 25 7636 #define rx_x4_status1_sc_S_20G_X2 26 7637 #define rx_x4_status1_sc_S_20G_HG2_CR2 28 7638 #define rx_x4_status1_sc_S_20G_HG2_KR2 29 7639 #define rx_x4_status1_sc_S_20G_HG2_X2 30 7640 #define rx_x4_status1_sc_S_40G_CR2 32 7641 #define rx_x4_status1_sc_S_40G_KR2 33 7642 #define rx_x4_status1_sc_S_40G_X2 34 7643 #define rx_x4_status1_sc_S_40G_HG2_CR2 36 7644 #define rx_x4_status1_sc_S_40G_HG2_KR2 37 7645 #define rx_x4_status1_sc_S_40G_HG2_X2 38 7646 #define rx_x4_status1_sc_S_40G_CR4 40 7647 #define rx_x4_status1_sc_S_40G_KR4 41 7648 #define rx_x4_status1_sc_S_40G_X4 42 7649 #define rx_x4_status1_sc_S_40G_HG2_CR4 44 7650 #define rx_x4_status1_sc_S_40G_HG2_KR4 45 7651 #define rx_x4_status1_sc_S_40G_HG2_X4 46 7652 #define rx_x4_status1_sc_S_50G_CR2 48 7653 #define rx_x4_status1_sc_S_50G_KR2 49 7654 #define rx_x4_status1_sc_S_50G_X2 50 7655 #define rx_x4_status1_sc_S_50G_HG2_CR2 52 7656 #define rx_x4_status1_sc_S_50G_HG2_KR2 53 7657 #define rx_x4_status1_sc_S_50G_HG2_X2 54 7658 #define rx_x4_status1_sc_S_50G_CR4 56 7659 #define rx_x4_status1_sc_S_50G_KR4 57 7660 #define rx_x4_status1_sc_S_50G_X4 58 7661 #define rx_x4_status1_sc_S_50G_HG2_CR4 60 7662 #define rx_x4_status1_sc_S_50G_HG2_KR4 61 7663 #define rx_x4_status1_sc_S_50G_HG2_X4 62 7664 #define rx_x4_status1_sc_S_100G_CR4 64 7665 #define rx_x4_status1_sc_S_100G_KR4 65 7666 #define rx_x4_status1_sc_S_100G_X4 66 7667 #define rx_x4_status1_sc_S_100G_HG2_CR4 68 7668 #define rx_x4_status1_sc_S_100G_HG2_KR4 69 7669 #define rx_x4_status1_sc_S_100G_HG2_X4 70 7670 #define rx_x4_status1_sc_S_CL73_20GVCO 72 7671 #define rx_x4_status1_sc_S_CL73_25GVCO 80 7672 #define rx_x4_status1_sc_S_CL36_20GVCO 88 7673 #define rx_x4_status1_sc_S_CL36_25GVCO 96 7674 #define rx_x4_status1_sc_S_25G_CR_IEEE 112 7675 #define rx_x4_status1_sc_S_25G_CRS_IEEE 113 7676 #define rx_x4_status1_sc_S_25G_KR_IEEE 114 7677 #define rx_x4_status1_sc_S_25G_KRS_IEEE 115 7678 7679 /**************************************************************************** 7680 * Enums: rx_x4_status1_t_fifo_modes 7681 */ 7682 #define rx_x4_status1_t_fifo_modes_T_FIFO_INSERT_NO_AM 0 7683 #define rx_x4_status1_t_fifo_modes_T_FIFO_INSERT_4_AM 1 7684 #define rx_x4_status1_t_fifo_modes_T_FIFO_INSERT_20_AM 2 7685 #define rx_x4_status1_t_fifo_modes_T_FIFO_INSERT_2_AM 3 7686 7687 /**************************************************************************** 7688 * Enums: rx_x4_status1_t_enc_modes 7689 */ 7690 #define rx_x4_status1_t_enc_modes_T_ENC_MODE_BYPASS 0 7691 #define rx_x4_status1_t_enc_modes_T_ENC_MODE_CL49 1 7692 #define rx_x4_status1_t_enc_modes_T_ENC_MODE_CL82 2 7693 7694 /**************************************************************************** 7695 * Enums: rx_x4_status1_btmx_mode 7696 */ 7697 #define rx_x4_status1_btmx_mode_BS_BTMX_MODE_1to1 0 7698 #define rx_x4_status1_btmx_mode_BS_BTMX_MODE_2to1 1 7699 #define rx_x4_status1_btmx_mode_BS_BTMX_MODE_5to1 2 7700 7701 /**************************************************************************** 7702 * Enums: rx_x4_status1_t_type_cl82 7703 */ 7704 #define rx_x4_status1_t_type_cl82_T_TYPE_B1 5 7705 #define rx_x4_status1_t_type_cl82_T_TYPE_C 4 7706 #define rx_x4_status1_t_type_cl82_T_TYPE_S 3 7707 #define rx_x4_status1_t_type_cl82_T_TYPE_T 2 7708 #define rx_x4_status1_t_type_cl82_T_TYPE_D 1 7709 #define rx_x4_status1_t_type_cl82_T_TYPE_E 0 7710 7711 /**************************************************************************** 7712 * Enums: rx_x4_status1_txsm_state_cl82 7713 */ 7714 #define rx_x4_status1_txsm_state_cl82_TX_HIG_END 6 7715 #define rx_x4_status1_txsm_state_cl82_TX_HIG_START 5 7716 #define rx_x4_status1_txsm_state_cl82_TX_E 4 7717 #define rx_x4_status1_txsm_state_cl82_TX_T 3 7718 #define rx_x4_status1_txsm_state_cl82_TX_D 2 7719 #define rx_x4_status1_txsm_state_cl82_TX_C 1 7720 #define rx_x4_status1_txsm_state_cl82_TX_INIT 0 7721 7722 /**************************************************************************** 7723 * Enums: rx_x4_status1_ltxsm_state_cl82 7724 */ 7725 #define rx_x4_status1_ltxsm_state_cl82_TX_HIG_END 64 7726 #define rx_x4_status1_ltxsm_state_cl82_TX_HIG_START 32 7727 #define rx_x4_status1_ltxsm_state_cl82_TX_E 16 7728 #define rx_x4_status1_ltxsm_state_cl82_TX_T 8 7729 #define rx_x4_status1_ltxsm_state_cl82_TX_D 4 7730 #define rx_x4_status1_ltxsm_state_cl82_TX_C 2 7731 #define rx_x4_status1_ltxsm_state_cl82_TX_INIT 1 7732 7733 /**************************************************************************** 7734 * Enums: rx_x4_status1_r_type_coded_cl82 7735 */ 7736 #define rx_x4_status1_r_type_coded_cl82_R_TYPE_B1 32 7737 #define rx_x4_status1_r_type_coded_cl82_R_TYPE_C 16 7738 #define rx_x4_status1_r_type_coded_cl82_R_TYPE_S 8 7739 #define rx_x4_status1_r_type_coded_cl82_R_TYPE_T 4 7740 #define rx_x4_status1_r_type_coded_cl82_R_TYPE_D 2 7741 #define rx_x4_status1_r_type_coded_cl82_R_TYPE_E 1 7742 7743 /**************************************************************************** 7744 * Enums: rx_x4_status1_rxsm_state_cl82 7745 */ 7746 #define rx_x4_status1_rxsm_state_cl82_RX_HIG_END 64 7747 #define rx_x4_status1_rxsm_state_cl82_RX_HIG_START 32 7748 #define rx_x4_status1_rxsm_state_cl82_RX_E 16 7749 #define rx_x4_status1_rxsm_state_cl82_RX_T 8 7750 #define rx_x4_status1_rxsm_state_cl82_RX_D 4 7751 #define rx_x4_status1_rxsm_state_cl82_RX_C 2 7752 #define rx_x4_status1_rxsm_state_cl82_RX_INIT 1 7753 7754 /**************************************************************************** 7755 * Enums: rx_x4_status1_deskew_state 7756 */ 7757 #define rx_x4_status1_deskew_state_ALIGN_ACQUIRED 2 7758 #define rx_x4_status1_deskew_state_LOSS_OF_ALIGNMENT 1 7759 7760 /**************************************************************************** 7761 * Enums: rx_x4_status1_os_mode_enum 7762 */ 7763 #define rx_x4_status1_os_mode_enum_OS_MODE_1 0 7764 #define rx_x4_status1_os_mode_enum_OS_MODE_2 1 7765 #define rx_x4_status1_os_mode_enum_OS_MODE_4 2 7766 #define rx_x4_status1_os_mode_enum_OS_MODE_16p5 8 7767 #define rx_x4_status1_os_mode_enum_OS_MODE_20p625 12 7768 7769 /**************************************************************************** 7770 * Enums: rx_x4_status1_scr_modes 7771 */ 7772 #define rx_x4_status1_scr_modes_T_SCR_MODE_BYPASS 0 7773 #define rx_x4_status1_scr_modes_T_SCR_MODE_CL49 1 7774 #define rx_x4_status1_scr_modes_T_SCR_MODE_40G_2_LANE 2 7775 #define rx_x4_status1_scr_modes_T_SCR_MODE_100G 3 7776 #define rx_x4_status1_scr_modes_T_SCR_MODE_20G 4 7777 #define rx_x4_status1_scr_modes_T_SCR_MODE_40G_4_LANE 5 7778 7779 /**************************************************************************** 7780 * Enums: rx_x4_status1_descr_modes 7781 */ 7782 #define rx_x4_status1_descr_modes_R_DESCR_MODE_BYPASS 0 7783 #define rx_x4_status1_descr_modes_R_DESCR_MODE_CL49 1 7784 #define rx_x4_status1_descr_modes_R_DESCR_MODE_CL82 2 7785 7786 /**************************************************************************** 7787 * Enums: rx_x4_status1_r_dec_tl_mode 7788 */ 7789 #define rx_x4_status1_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 7790 #define rx_x4_status1_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 7791 #define rx_x4_status1_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 7792 7793 /**************************************************************************** 7794 * Enums: rx_x4_status1_r_dec_fsm_mode 7795 */ 7796 #define rx_x4_status1_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 7797 #define rx_x4_status1_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 7798 #define rx_x4_status1_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 7799 7800 /**************************************************************************** 7801 * Enums: rx_x4_status1_r_deskew_mode 7802 */ 7803 #define rx_x4_status1_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 7804 #define rx_x4_status1_r_deskew_mode_R_DESKEW_MODE_20G 1 7805 #define rx_x4_status1_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 7806 #define rx_x4_status1_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 7807 #define rx_x4_status1_r_deskew_mode_R_DESKEW_MODE_100G 4 7808 #define rx_x4_status1_r_deskew_mode_R_DESKEW_MODE_CL49 5 7809 #define rx_x4_status1_r_deskew_mode_R_DESKEW_MODE_CL91_QUAD 6 7810 #define rx_x4_status1_r_deskew_mode_R_DESKEW_MODE_CL91_SINGLE_BRCM 7 7811 #define rx_x4_status1_r_deskew_mode_R_DESKEW_MODE_CL91_DUAL_BRCM 8 7812 #define rx_x4_status1_r_deskew_mode_R_DESKEW_MODE_CL91_FC 9 7813 7814 /**************************************************************************** 7815 * Enums: rx_x4_status1_bs_dist_modes 7816 */ 7817 #define rx_x4_status1_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 7818 #define rx_x4_status1_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 7819 #define rx_x4_status1_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 7820 #define rx_x4_status1_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 7821 7822 /**************************************************************************** 7823 * Enums: rx_x4_status1_cl49_t_type 7824 */ 7825 #define rx_x4_status1_cl49_t_type_BAD_T_TYPE 15 7826 #define rx_x4_status1_cl49_t_type_T_TYPE_B0 11 7827 #define rx_x4_status1_cl49_t_type_T_TYPE_OB 10 7828 #define rx_x4_status1_cl49_t_type_T_TYPE_B1 9 7829 #define rx_x4_status1_cl49_t_type_T_TYPE_DB 8 7830 #define rx_x4_status1_cl49_t_type_T_TYPE_FC 7 7831 #define rx_x4_status1_cl49_t_type_T_TYPE_TB 6 7832 #define rx_x4_status1_cl49_t_type_T_TYPE_LI 5 7833 #define rx_x4_status1_cl49_t_type_T_TYPE_C 4 7834 #define rx_x4_status1_cl49_t_type_T_TYPE_S 3 7835 #define rx_x4_status1_cl49_t_type_T_TYPE_T 2 7836 #define rx_x4_status1_cl49_t_type_T_TYPE_D 1 7837 #define rx_x4_status1_cl49_t_type_T_TYPE_E 0 7838 7839 /**************************************************************************** 7840 * Enums: rx_x4_status1_cl49_txsm_states 7841 */ 7842 #define rx_x4_status1_cl49_txsm_states_TX_HIG_END 7 7843 #define rx_x4_status1_cl49_txsm_states_TX_HIG_START 6 7844 #define rx_x4_status1_cl49_txsm_states_TX_LI 5 7845 #define rx_x4_status1_cl49_txsm_states_TX_E 4 7846 #define rx_x4_status1_cl49_txsm_states_TX_T 3 7847 #define rx_x4_status1_cl49_txsm_states_TX_D 2 7848 #define rx_x4_status1_cl49_txsm_states_TX_C 1 7849 #define rx_x4_status1_cl49_txsm_states_TX_INIT 0 7850 7851 /**************************************************************************** 7852 * Enums: rx_x4_status1_cl49_ltxsm_states 7853 */ 7854 #define rx_x4_status1_cl49_ltxsm_states_TX_HIG_END 128 7855 #define rx_x4_status1_cl49_ltxsm_states_TX_HIG_START 64 7856 #define rx_x4_status1_cl49_ltxsm_states_TX_LI 32 7857 #define rx_x4_status1_cl49_ltxsm_states_TX_E 16 7858 #define rx_x4_status1_cl49_ltxsm_states_TX_T 8 7859 #define rx_x4_status1_cl49_ltxsm_states_TX_D 4 7860 #define rx_x4_status1_cl49_ltxsm_states_TX_C 2 7861 #define rx_x4_status1_cl49_ltxsm_states_TX_INIT 1 7862 7863 /**************************************************************************** 7864 * Enums: rx_x4_status1_burst_error_mode 7865 */ 7866 #define rx_x4_status1_burst_error_mode_BURST_ERROR_11_BITS 0 7867 #define rx_x4_status1_burst_error_mode_BURST_ERROR_16_BITS 1 7868 #define rx_x4_status1_burst_error_mode_BURST_ERROR_17_BITS 2 7869 #define rx_x4_status1_burst_error_mode_BURST_ERROR_18_BITS 3 7870 #define rx_x4_status1_burst_error_mode_BURST_ERROR_19_BITS 4 7871 #define rx_x4_status1_burst_error_mode_BURST_ERROR_20_BITS 5 7872 #define rx_x4_status1_burst_error_mode_BURST_ERROR_21_BITS 6 7873 #define rx_x4_status1_burst_error_mode_BURST_ERROR_22_BITS 7 7874 #define rx_x4_status1_burst_error_mode_BURST_ERROR_23_BITS 8 7875 #define rx_x4_status1_burst_error_mode_BURST_ERROR_24_BITS 9 7876 #define rx_x4_status1_burst_error_mode_BURST_ERROR_25_BITS 10 7877 #define rx_x4_status1_burst_error_mode_BURST_ERROR_26_BITS 11 7878 #define rx_x4_status1_burst_error_mode_BURST_ERROR_27_BITS 12 7879 #define rx_x4_status1_burst_error_mode_BURST_ERROR_28_BITS 13 7880 #define rx_x4_status1_burst_error_mode_BURST_ERROR_29_BITS 14 7881 #define rx_x4_status1_burst_error_mode_BURST_ERROR_30_BITS 15 7882 #define rx_x4_status1_burst_error_mode_BURST_ERROR_31_BITS 16 7883 #define rx_x4_status1_burst_error_mode_BURST_ERROR_32_BITS 17 7884 #define rx_x4_status1_burst_error_mode_BURST_ERROR_33_BITS 18 7885 #define rx_x4_status1_burst_error_mode_BURST_ERROR_34_BITS 19 7886 #define rx_x4_status1_burst_error_mode_BURST_ERROR_35_BITS 20 7887 #define rx_x4_status1_burst_error_mode_BURST_ERROR_36_BITS 21 7888 #define rx_x4_status1_burst_error_mode_BURST_ERROR_37_BITS 22 7889 #define rx_x4_status1_burst_error_mode_BURST_ERROR_38_BITS 23 7890 #define rx_x4_status1_burst_error_mode_BURST_ERROR_39_BITS 24 7891 #define rx_x4_status1_burst_error_mode_BURST_ERROR_40_BITS 25 7892 #define rx_x4_status1_burst_error_mode_BURST_ERROR_41_BITS 26 7893 7894 /**************************************************************************** 7895 * Enums: rx_x4_status1_bermon_state 7896 */ 7897 #define rx_x4_status1_bermon_state_HI_BER 4 7898 #define rx_x4_status1_bermon_state_GOOD_BER 3 7899 #define rx_x4_status1_bermon_state_BER_TEST_SH 2 7900 #define rx_x4_status1_bermon_state_START_TIMER 1 7901 #define rx_x4_status1_bermon_state_BER_MT_INIT 0 7902 7903 /**************************************************************************** 7904 * Enums: rx_x4_status1_rxsm_state_cl49 7905 */ 7906 #define rx_x4_status1_rxsm_state_cl49_RX_HIG_END 128 7907 #define rx_x4_status1_rxsm_state_cl49_RX_HIG_START 64 7908 #define rx_x4_status1_rxsm_state_cl49_RX_LI 32 7909 #define rx_x4_status1_rxsm_state_cl49_RX_E 16 7910 #define rx_x4_status1_rxsm_state_cl49_RX_T 8 7911 #define rx_x4_status1_rxsm_state_cl49_RX_D 4 7912 #define rx_x4_status1_rxsm_state_cl49_RX_C 2 7913 #define rx_x4_status1_rxsm_state_cl49_RX_INIT 1 7914 7915 /**************************************************************************** 7916 * Enums: rx_x4_status1_r_type 7917 */ 7918 #define rx_x4_status1_r_type_BAD_R_TYPE 15 7919 #define rx_x4_status1_r_type_R_TYPE_B0 11 7920 #define rx_x4_status1_r_type_R_TYPE_OB 10 7921 #define rx_x4_status1_r_type_R_TYPE_B1 9 7922 #define rx_x4_status1_r_type_R_TYPE_DB 8 7923 #define rx_x4_status1_r_type_R_TYPE_FC 7 7924 #define rx_x4_status1_r_type_R_TYPE_TB 6 7925 #define rx_x4_status1_r_type_R_TYPE_LI 5 7926 #define rx_x4_status1_r_type_R_TYPE_C 4 7927 #define rx_x4_status1_r_type_R_TYPE_S 3 7928 #define rx_x4_status1_r_type_R_TYPE_T 2 7929 #define rx_x4_status1_r_type_R_TYPE_D 1 7930 #define rx_x4_status1_r_type_R_TYPE_E 0 7931 7932 /**************************************************************************** 7933 * Enums: rx_x4_status1_am_lock_state 7934 */ 7935 #define rx_x4_status1_am_lock_state_INVALID_AM 512 7936 #define rx_x4_status1_am_lock_state_GOOD_AM 256 7937 #define rx_x4_status1_am_lock_state_COMP_AM 128 7938 #define rx_x4_status1_am_lock_state_TIMER_2 64 7939 #define rx_x4_status1_am_lock_state_AM_2_GOOD 32 7940 #define rx_x4_status1_am_lock_state_COMP_2ND 16 7941 #define rx_x4_status1_am_lock_state_TIMER_1 8 7942 #define rx_x4_status1_am_lock_state_FIND_1ST 4 7943 #define rx_x4_status1_am_lock_state_AM_RESET_CNT 2 7944 #define rx_x4_status1_am_lock_state_AM_LOCK_INIT 1 7945 7946 /**************************************************************************** 7947 * Enums: rx_x4_status1_msg_selector 7948 */ 7949 #define rx_x4_status1_msg_selector_RESERVED 0 7950 #define rx_x4_status1_msg_selector_VALUE_802p3 1 7951 #define rx_x4_status1_msg_selector_VALUE_802p9 2 7952 #define rx_x4_status1_msg_selector_VALUE_802p5 3 7953 #define rx_x4_status1_msg_selector_VALUE_1394 4 7954 7955 /**************************************************************************** 7956 * Enums: rx_x4_status1_synce_enum 7957 */ 7958 #define rx_x4_status1_synce_enum_SYNCE_NO_DIV 0 7959 #define rx_x4_status1_synce_enum_SYNCE_DIV_7 1 7960 #define rx_x4_status1_synce_enum_SYNCE_DIV_11 2 7961 7962 /**************************************************************************** 7963 * Enums: rx_x4_status1_synce_enum_stage0 7964 */ 7965 #define rx_x4_status1_synce_enum_stage0_SYNCE_NO_DIV 0 7966 #define rx_x4_status1_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 7967 #define rx_x4_status1_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 7968 7969 /**************************************************************************** 7970 * Enums: rx_x4_status1_cl91_sync_state 7971 */ 7972 #define rx_x4_status1_cl91_sync_state_FIND_1ST 0 7973 #define rx_x4_status1_cl91_sync_state_COUNT_NEXT 1 7974 #define rx_x4_status1_cl91_sync_state_COMP_2ND 2 7975 #define rx_x4_status1_cl91_sync_state_TWO_GOOD 3 7976 7977 /**************************************************************************** 7978 * Enums: rx_x4_status1_cl91_algn_state 7979 */ 7980 #define rx_x4_status1_cl91_algn_state_LOSS_OF_ALIGNMENT 0 7981 #define rx_x4_status1_cl91_algn_state_DESKEW 1 7982 #define rx_x4_status1_cl91_algn_state_DESKEW_FAIL 2 7983 #define rx_x4_status1_cl91_algn_state_ALIGN_ACQUIRED 3 7984 #define rx_x4_status1_cl91_algn_state_CW_GOOD 4 7985 #define rx_x4_status1_cl91_algn_state_CW_BAD 5 7986 #define rx_x4_status1_cl91_algn_state_THREE_BAD 6 7987 7988 /**************************************************************************** 7989 * Enums: rx_x4_status1_fec_sel_override 7990 */ 7991 #define rx_x4_status1_fec_sel_override_NO_OVERRIDE 0 7992 #define rx_x4_status1_fec_sel_override_NO_FEC 1 7993 #define rx_x4_status1_fec_sel_override_FEC_CL74 2 7994 #define rx_x4_status1_fec_sel_override_FEC_CL91 3 7995 7996 /**************************************************************************** 7997 * Enums: rx_x4_status1_cl91_blksync_mode 7998 */ 7999 #define rx_x4_status1_cl91_blksync_mode_R_BLKSYNC_NO_CL91_FEC 0 8000 #define rx_x4_status1_cl91_blksync_mode_R_BLKSYNC_CL91_QUAD_LANE_FEC 1 8001 #define rx_x4_status1_cl91_blksync_mode_R_BLKSYNC_CL91_DUAL_LANE_FEC 2 8002 #define rx_x4_status1_cl91_blksync_mode_R_BLKSYNC_CL91_SINGLE_LANE_FEC 3 8003 #define rx_x4_status1_cl91_blksync_mode_R_BLKSYNC_CL91_FC_FEC 4 8004 8005 /**************************************************************************** 8006 * Enums: rx_x4_status1_r_merge_mode 8007 */ 8008 #define rx_x4_status1_r_merge_mode_R_MERGE_MODE_BYPASS 0 8009 #define rx_x4_status1_r_merge_mode_R_MERGE_MODE_CL91_FC 1 8010 #define rx_x4_status1_r_merge_mode_R_MERGE_MODE_CL91_SINGLE_LANE 2 8011 #define rx_x4_status1_r_merge_mode_R_MERGE_MODE_CL91_DUAL_LANE 3 8012 #define rx_x4_status1_r_merge_mode_R_MERGE_MODE_CL91_QUAD_LANE 4 8013 8014 /**************************************************************************** 8015 * Enums: rx_x4_status1_r_tc_mode 8016 */ 8017 #define rx_x4_status1_r_tc_mode_R_TC_MODE_SINGLE 0 8018 #define rx_x4_status1_r_tc_mode_R_TC_MODE_DUAL 1 8019 #define rx_x4_status1_r_tc_mode_R_TC_MODE_QUAD 2 8020 8021 /**************************************************************************** 8022 * Enums: rx_x4_status1_r_tc_out_mode 8023 */ 8024 #define rx_x4_status1_r_tc_out_mode_R_TC_OUT_MODE_SINGLE 0 8025 #define rx_x4_status1_r_tc_out_mode_R_TC_OUT_MODE_DUAL 1 8026 #define rx_x4_status1_r_tc_out_mode_R_TC_OUT_MODE_QUAD 2 8027 8028 /**************************************************************************** 8029 * Enums: rx_x4_status1_cl91_fec_mode 8030 */ 8031 #define rx_x4_status1_cl91_fec_mode_NO_CL91_FEC 0 8032 #define rx_x4_status1_cl91_fec_mode_CL91_SINGLE_LANE_FC 1 8033 #define rx_x4_status1_cl91_fec_mode_CL91_SINGLE_LANE_BRCM_PROP 2 8034 #define rx_x4_status1_cl91_fec_mode_CL91_DUAL_LANE_BRCM_PROP 3 8035 #define rx_x4_status1_cl91_fec_mode_CL91_QUAD_LANE 4 8036 #define rx_x4_status1_cl91_fec_mode_IEEE_25G_CL91_SINGLE_LANE 5 8037 8038 /**************************************************************************** 8039 * Enums: rx_x4_status1_am_spacing_mul 8040 */ 8041 #define rx_x4_status1_am_spacing_mul_AM_SPACING_MUL_2 0 8042 #define rx_x4_status1_am_spacing_mul_AM_SPACING_MUL_4 1 8043 #define rx_x4_status1_am_spacing_mul_AM_SPACING_MUL_5 2 8044 #define rx_x4_status1_am_spacing_mul_AM_SPACING_MUL_20 3 8045 8046 /**************************************************************************** 8047 * Enums: rx_x4_status2_cl36TxEEEStates_l 8048 */ 8049 #define rx_x4_status2_cl36TxEEEStates_l_TX_REFRESH 8 8050 #define rx_x4_status2_cl36TxEEEStates_l_TX_QUIET 4 8051 #define rx_x4_status2_cl36TxEEEStates_l_TX_SLEEP 2 8052 #define rx_x4_status2_cl36TxEEEStates_l_TX_ACTIVE 1 8053 8054 /**************************************************************************** 8055 * Enums: rx_x4_status2_cl36TxEEEStates_c 8056 */ 8057 #define rx_x4_status2_cl36TxEEEStates_c_TX_REFRESH 3 8058 #define rx_x4_status2_cl36TxEEEStates_c_TX_QUIET 2 8059 #define rx_x4_status2_cl36TxEEEStates_c_TX_SLEEP 1 8060 #define rx_x4_status2_cl36TxEEEStates_c_TX_ACTIVE 0 8061 8062 /**************************************************************************** 8063 * Enums: rx_x4_status2_cl49TxEEEStates_l 8064 */ 8065 #define rx_x4_status2_cl49TxEEEStates_l_SCR_RESET_2 64 8066 #define rx_x4_status2_cl49TxEEEStates_l_SCR_RESET_1 32 8067 #define rx_x4_status2_cl49TxEEEStates_l_TX_WAKE 16 8068 #define rx_x4_status2_cl49TxEEEStates_l_TX_REFRESH 8 8069 #define rx_x4_status2_cl49TxEEEStates_l_TX_QUIET 4 8070 #define rx_x4_status2_cl49TxEEEStates_l_TX_SLEEP 2 8071 #define rx_x4_status2_cl49TxEEEStates_l_TX_ACTIVE 1 8072 8073 /**************************************************************************** 8074 * Enums: rx_x4_status2_fec_req_enum 8075 */ 8076 #define rx_x4_status2_fec_req_enum_FEC_not_supported 0 8077 #define rx_x4_status2_fec_req_enum_FEC_supported_but_not_requested 1 8078 #define rx_x4_status2_fec_req_enum_invalid_setting 2 8079 #define rx_x4_status2_fec_req_enum_FEC_supported_and_requested 3 8080 8081 /**************************************************************************** 8082 * Enums: rx_x4_status2_cl73_pause_enum 8083 */ 8084 #define rx_x4_status2_cl73_pause_enum_No_PAUSE_ability 0 8085 #define rx_x4_status2_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 8086 #define rx_x4_status2_cl73_pause_enum_Symmetric_PAUSE_ability 1 8087 #define rx_x4_status2_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 8088 8089 /**************************************************************************** 8090 * Enums: rx_x4_status2_cl49TxEEEStates_c 8091 */ 8092 #define rx_x4_status2_cl49TxEEEStates_c_SCR_RESET_2 6 8093 #define rx_x4_status2_cl49TxEEEStates_c_SCR_RESET_1 5 8094 #define rx_x4_status2_cl49TxEEEStates_c_TX_WAKE 4 8095 #define rx_x4_status2_cl49TxEEEStates_c_TX_REFRESH 3 8096 #define rx_x4_status2_cl49TxEEEStates_c_TX_QUIET 2 8097 #define rx_x4_status2_cl49TxEEEStates_c_TX_SLEEP 1 8098 #define rx_x4_status2_cl49TxEEEStates_c_TX_ACTIVE 0 8099 8100 /**************************************************************************** 8101 * Enums: rx_x4_status2_cl36RxEEEStates_l 8102 */ 8103 #define rx_x4_status2_cl36RxEEEStates_l_RX_LINK_FAIL 32 8104 #define rx_x4_status2_cl36RxEEEStates_l_RX_WTF 16 8105 #define rx_x4_status2_cl36RxEEEStates_l_RX_WAKE 8 8106 #define rx_x4_status2_cl36RxEEEStates_l_RX_QUIET 4 8107 #define rx_x4_status2_cl36RxEEEStates_l_RX_SLEEP 2 8108 #define rx_x4_status2_cl36RxEEEStates_l_RX_ACTIVE 1 8109 8110 /**************************************************************************** 8111 * Enums: rx_x4_status2_cl36RxEEEStates_c 8112 */ 8113 #define rx_x4_status2_cl36RxEEEStates_c_RX_LINK_FAIL 5 8114 #define rx_x4_status2_cl36RxEEEStates_c_RX_WTF 4 8115 #define rx_x4_status2_cl36RxEEEStates_c_RX_WAKE 3 8116 #define rx_x4_status2_cl36RxEEEStates_c_RX_QUIET 2 8117 #define rx_x4_status2_cl36RxEEEStates_c_RX_SLEEP 1 8118 #define rx_x4_status2_cl36RxEEEStates_c_RX_ACTIVE 0 8119 8120 /**************************************************************************** 8121 * Enums: rx_x4_status2_cl49RxEEEStates_l 8122 */ 8123 #define rx_x4_status2_cl49RxEEEStates_l_RX_LINK_FAIL 32 8124 #define rx_x4_status2_cl49RxEEEStates_l_RX_WTF 16 8125 #define rx_x4_status2_cl49RxEEEStates_l_RX_WAKE 8 8126 #define rx_x4_status2_cl49RxEEEStates_l_RX_QUIET 4 8127 #define rx_x4_status2_cl49RxEEEStates_l_RX_SLEEP 2 8128 #define rx_x4_status2_cl49RxEEEStates_l_RX_ACTIVE 1 8129 8130 /**************************************************************************** 8131 * Enums: rx_x4_status2_cl49RxEEEStates_c 8132 */ 8133 #define rx_x4_status2_cl49RxEEEStates_c_RX_LINK_FAIL 5 8134 #define rx_x4_status2_cl49RxEEEStates_c_RX_WTF 4 8135 #define rx_x4_status2_cl49RxEEEStates_c_RX_WAKE 3 8136 #define rx_x4_status2_cl49RxEEEStates_c_RX_QUIET 2 8137 #define rx_x4_status2_cl49RxEEEStates_c_RX_SLEEP 1 8138 #define rx_x4_status2_cl49RxEEEStates_c_RX_ACTIVE 0 8139 8140 /**************************************************************************** 8141 * Enums: rx_x4_status2_cl48TxEEEStates_l 8142 */ 8143 #define rx_x4_status2_cl48TxEEEStates_l_TX_REFRESH 8 8144 #define rx_x4_status2_cl48TxEEEStates_l_TX_QUIET 4 8145 #define rx_x4_status2_cl48TxEEEStates_l_TX_SLEEP 2 8146 #define rx_x4_status2_cl48TxEEEStates_l_TX_ACTIVE 1 8147 8148 /**************************************************************************** 8149 * Enums: rx_x4_status2_cl48TxEEEStates_c 8150 */ 8151 #define rx_x4_status2_cl48TxEEEStates_c_TX_REFRESH 3 8152 #define rx_x4_status2_cl48TxEEEStates_c_TX_QUIET 2 8153 #define rx_x4_status2_cl48TxEEEStates_c_TX_SLEEP 1 8154 #define rx_x4_status2_cl48TxEEEStates_c_TX_ACTIVE 0 8155 8156 /**************************************************************************** 8157 * Enums: rx_x4_status2_cl48RxEEEStates_l 8158 */ 8159 #define rx_x4_status2_cl48RxEEEStates_l_RX_LINK_FAIL 32 8160 #define rx_x4_status2_cl48RxEEEStates_l_RX_WAKE 16 8161 #define rx_x4_status2_cl48RxEEEStates_l_RX_QUIET 8 8162 #define rx_x4_status2_cl48RxEEEStates_l_RX_DEACT 4 8163 #define rx_x4_status2_cl48RxEEEStates_l_RX_SLEEP 2 8164 #define rx_x4_status2_cl48RxEEEStates_l_RX_ACTIVE 1 8165 8166 /**************************************************************************** 8167 * Enums: rx_x4_status2_cl48RxEEEStates_c 8168 */ 8169 #define rx_x4_status2_cl48RxEEEStates_c_RX_LINK_FAIL 5 8170 #define rx_x4_status2_cl48RxEEEStates_c_RX_WAKE 4 8171 #define rx_x4_status2_cl48RxEEEStates_c_RX_QUIET 3 8172 #define rx_x4_status2_cl48RxEEEStates_c_RX_DEACT 2 8173 #define rx_x4_status2_cl48RxEEEStates_c_RX_SLEEP 1 8174 #define rx_x4_status2_cl48RxEEEStates_c_RX_ACTIVE 0 8175 8176 /**************************************************************************** 8177 * Enums: rx_x4_status2_IQP_Options 8178 */ 8179 #define rx_x4_status2_IQP_Options_i50uA 0 8180 #define rx_x4_status2_IQP_Options_i100uA 1 8181 #define rx_x4_status2_IQP_Options_i150uA 2 8182 #define rx_x4_status2_IQP_Options_i200uA 3 8183 #define rx_x4_status2_IQP_Options_i250uA 4 8184 #define rx_x4_status2_IQP_Options_i300uA 5 8185 #define rx_x4_status2_IQP_Options_i350uA 6 8186 #define rx_x4_status2_IQP_Options_i400uA 7 8187 #define rx_x4_status2_IQP_Options_i450uA 8 8188 #define rx_x4_status2_IQP_Options_i500uA 9 8189 #define rx_x4_status2_IQP_Options_i550uA 10 8190 #define rx_x4_status2_IQP_Options_i600uA 11 8191 #define rx_x4_status2_IQP_Options_i650uA 12 8192 #define rx_x4_status2_IQP_Options_i700uA 13 8193 #define rx_x4_status2_IQP_Options_i750uA 14 8194 #define rx_x4_status2_IQP_Options_i800uA 15 8195 8196 /**************************************************************************** 8197 * Enums: rx_x4_status2_IDriver_Options 8198 */ 8199 #define rx_x4_status2_IDriver_Options_v680mV 0 8200 #define rx_x4_status2_IDriver_Options_v730mV 1 8201 #define rx_x4_status2_IDriver_Options_v780mV 2 8202 #define rx_x4_status2_IDriver_Options_v830mV 3 8203 #define rx_x4_status2_IDriver_Options_v880mV 4 8204 #define rx_x4_status2_IDriver_Options_v930mV 5 8205 #define rx_x4_status2_IDriver_Options_v980mV 6 8206 #define rx_x4_status2_IDriver_Options_v1010mV 7 8207 #define rx_x4_status2_IDriver_Options_v1040mV 8 8208 #define rx_x4_status2_IDriver_Options_v1060mV 9 8209 #define rx_x4_status2_IDriver_Options_v1070mV 10 8210 #define rx_x4_status2_IDriver_Options_v1080mV 11 8211 #define rx_x4_status2_IDriver_Options_v1085mV 12 8212 #define rx_x4_status2_IDriver_Options_v1090mV 13 8213 #define rx_x4_status2_IDriver_Options_v1095mV 14 8214 #define rx_x4_status2_IDriver_Options_v1100mV 15 8215 8216 /**************************************************************************** 8217 * Enums: rx_x4_status2_operationModes 8218 */ 8219 #define rx_x4_status2_operationModes_XGXS 0 8220 #define rx_x4_status2_operationModes_XGXG_nCC 1 8221 #define rx_x4_status2_operationModes_Indlane_OS8 4 8222 #define rx_x4_status2_operationModes_IndLane_OS5 5 8223 #define rx_x4_status2_operationModes_PCI 7 8224 #define rx_x4_status2_operationModes_XGXS_nLQ 8 8225 #define rx_x4_status2_operationModes_XGXS_nLQnCC 9 8226 #define rx_x4_status2_operationModes_PBypass 10 8227 #define rx_x4_status2_operationModes_PBypass_nDSK 11 8228 #define rx_x4_status2_operationModes_ComboCoreMode 12 8229 #define rx_x4_status2_operationModes_Clocks_off 15 8230 8231 /**************************************************************************** 8232 * Enums: rx_x4_status2_actualSpeeds 8233 */ 8234 #define rx_x4_status2_actualSpeeds_dr_10M 0 8235 #define rx_x4_status2_actualSpeeds_dr_100M 1 8236 #define rx_x4_status2_actualSpeeds_dr_1G 2 8237 #define rx_x4_status2_actualSpeeds_dr_2p5G 3 8238 #define rx_x4_status2_actualSpeeds_dr_5G_X4 4 8239 #define rx_x4_status2_actualSpeeds_dr_6G_X4 5 8240 #define rx_x4_status2_actualSpeeds_dr_10G_HiG 6 8241 #define rx_x4_status2_actualSpeeds_dr_10G_CX4 7 8242 #define rx_x4_status2_actualSpeeds_dr_12G_HiG 8 8243 #define rx_x4_status2_actualSpeeds_dr_12p5G_X4 9 8244 #define rx_x4_status2_actualSpeeds_dr_13G_X4 10 8245 #define rx_x4_status2_actualSpeeds_dr_15G_X4 11 8246 #define rx_x4_status2_actualSpeeds_dr_16G_X4 12 8247 #define rx_x4_status2_actualSpeeds_dr_1G_KX 13 8248 #define rx_x4_status2_actualSpeeds_dr_10G_KX4 14 8249 #define rx_x4_status2_actualSpeeds_dr_10G_KR 15 8250 #define rx_x4_status2_actualSpeeds_dr_5G 16 8251 #define rx_x4_status2_actualSpeeds_dr_6p4G 17 8252 #define rx_x4_status2_actualSpeeds_dr_20G_X4 18 8253 #define rx_x4_status2_actualSpeeds_dr_21G_X4 19 8254 #define rx_x4_status2_actualSpeeds_dr_25G_X4 20 8255 #define rx_x4_status2_actualSpeeds_dr_10G_HiG_DXGXS 21 8256 #define rx_x4_status2_actualSpeeds_dr_10G_DXGXS 22 8257 #define rx_x4_status2_actualSpeeds_dr_10p5G_HiG_DXGXS 23 8258 #define rx_x4_status2_actualSpeeds_dr_10p5G_DXGXS 24 8259 #define rx_x4_status2_actualSpeeds_dr_12p773G_HiG_DXGXS 25 8260 #define rx_x4_status2_actualSpeeds_dr_12p773G_DXGXS 26 8261 #define rx_x4_status2_actualSpeeds_dr_10G_XFI 27 8262 #define rx_x4_status2_actualSpeeds_dr_40G 28 8263 #define rx_x4_status2_actualSpeeds_dr_20G_HiG_DXGXS 29 8264 #define rx_x4_status2_actualSpeeds_dr_20G_DXGXS 30 8265 #define rx_x4_status2_actualSpeeds_dr_10G_SFI 31 8266 #define rx_x4_status2_actualSpeeds_dr_31p5G 32 8267 #define rx_x4_status2_actualSpeeds_dr_32p7G 33 8268 #define rx_x4_status2_actualSpeeds_dr_20G_SCR 34 8269 #define rx_x4_status2_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 8270 #define rx_x4_status2_actualSpeeds_dr_10G_DXGXS_SCR 36 8271 #define rx_x4_status2_actualSpeeds_dr_12G_R2 37 8272 #define rx_x4_status2_actualSpeeds_dr_10G_X2 38 8273 #define rx_x4_status2_actualSpeeds_dr_40G_KR4 39 8274 #define rx_x4_status2_actualSpeeds_dr_40G_CR4 40 8275 #define rx_x4_status2_actualSpeeds_dr_100G_CR10 41 8276 #define rx_x4_status2_actualSpeeds_dr_15p75G_DXGXS 44 8277 #define rx_x4_status2_actualSpeeds_dr_20G_KR2 57 8278 #define rx_x4_status2_actualSpeeds_dr_20G_CR2 58 8279 8280 /**************************************************************************** 8281 * Enums: rx_x4_status2_actualSpeedsMisc1 8282 */ 8283 #define rx_x4_status2_actualSpeedsMisc1_dr_2500BRCM_X1 16 8284 #define rx_x4_status2_actualSpeedsMisc1_dr_5000BRCM_X4 17 8285 #define rx_x4_status2_actualSpeedsMisc1_dr_6000BRCM_X4 18 8286 #define rx_x4_status2_actualSpeedsMisc1_dr_10GHiGig_X4 19 8287 #define rx_x4_status2_actualSpeedsMisc1_dr_10GBASE_CX4 20 8288 #define rx_x4_status2_actualSpeedsMisc1_dr_12GHiGig_X4 21 8289 #define rx_x4_status2_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 8290 #define rx_x4_status2_actualSpeedsMisc1_dr_13GHiGig_X4 23 8291 #define rx_x4_status2_actualSpeedsMisc1_dr_15GHiGig_X4 24 8292 #define rx_x4_status2_actualSpeedsMisc1_dr_16GHiGig_X4 25 8293 #define rx_x4_status2_actualSpeedsMisc1_dr_5000BRCM_X1 26 8294 #define rx_x4_status2_actualSpeedsMisc1_dr_6363BRCM_X1 27 8295 #define rx_x4_status2_actualSpeedsMisc1_dr_20GHiGig_X4 28 8296 #define rx_x4_status2_actualSpeedsMisc1_dr_21GHiGig_X4 29 8297 #define rx_x4_status2_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 8298 #define rx_x4_status2_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 8299 8300 /**************************************************************************** 8301 * Enums: rx_x4_status2_IndLaneModes 8302 */ 8303 #define rx_x4_status2_IndLaneModes_SWSDR_div2 0 8304 #define rx_x4_status2_IndLaneModes_SWSDR_div1 1 8305 #define rx_x4_status2_IndLaneModes_DWSDR_div2 2 8306 #define rx_x4_status2_IndLaneModes_DWSDR_div1 3 8307 8308 /**************************************************************************** 8309 * Enums: rx_x4_status2_prbsSelect 8310 */ 8311 #define rx_x4_status2_prbsSelect_prbs7 0 8312 #define rx_x4_status2_prbsSelect_prbs15 1 8313 #define rx_x4_status2_prbsSelect_prbs23 2 8314 #define rx_x4_status2_prbsSelect_prbs31 3 8315 8316 /**************************************************************************** 8317 * Enums: rx_x4_status2_vcoDivider 8318 */ 8319 #define rx_x4_status2_vcoDivider_div32 0 8320 #define rx_x4_status2_vcoDivider_div36 1 8321 #define rx_x4_status2_vcoDivider_div40 2 8322 #define rx_x4_status2_vcoDivider_div42 3 8323 #define rx_x4_status2_vcoDivider_div48 4 8324 #define rx_x4_status2_vcoDivider_div50 5 8325 #define rx_x4_status2_vcoDivider_div52 6 8326 #define rx_x4_status2_vcoDivider_div54 7 8327 #define rx_x4_status2_vcoDivider_div60 8 8328 #define rx_x4_status2_vcoDivider_div64 9 8329 #define rx_x4_status2_vcoDivider_div66 10 8330 #define rx_x4_status2_vcoDivider_div68 11 8331 #define rx_x4_status2_vcoDivider_div70 12 8332 #define rx_x4_status2_vcoDivider_div80 13 8333 #define rx_x4_status2_vcoDivider_div92 14 8334 #define rx_x4_status2_vcoDivider_div100 15 8335 8336 /**************************************************************************** 8337 * Enums: rx_x4_status2_refClkSelect 8338 */ 8339 #define rx_x4_status2_refClkSelect_clk_25MHz 0 8340 #define rx_x4_status2_refClkSelect_clk_100MHz 1 8341 #define rx_x4_status2_refClkSelect_clk_125MHz 2 8342 #define rx_x4_status2_refClkSelect_clk_156p25MHz 3 8343 #define rx_x4_status2_refClkSelect_clk_187p5MHz 4 8344 #define rx_x4_status2_refClkSelect_clk_161p25Mhz 5 8345 #define rx_x4_status2_refClkSelect_clk_50Mhz 6 8346 #define rx_x4_status2_refClkSelect_clk_106p25Mhz 7 8347 8348 /**************************************************************************** 8349 * Enums: rx_x4_status2_aerMMDdevTypeSelect 8350 */ 8351 #define rx_x4_status2_aerMMDdevTypeSelect_combo_core 0 8352 #define rx_x4_status2_aerMMDdevTypeSelect_PMA_PMD 1 8353 #define rx_x4_status2_aerMMDdevTypeSelect_PCS 3 8354 #define rx_x4_status2_aerMMDdevTypeSelect_PHY 4 8355 #define rx_x4_status2_aerMMDdevTypeSelect_DTE 5 8356 #define rx_x4_status2_aerMMDdevTypeSelect_CL73_AN 7 8357 8358 /**************************************************************************** 8359 * Enums: rx_x4_status2_aerMMDportSelect 8360 */ 8361 #define rx_x4_status2_aerMMDportSelect_ln0 0 8362 #define rx_x4_status2_aerMMDportSelect_ln1 1 8363 #define rx_x4_status2_aerMMDportSelect_ln2 2 8364 #define rx_x4_status2_aerMMDportSelect_ln3 3 8365 #define rx_x4_status2_aerMMDportSelect_BCST_ln0_1_2_3 511 8366 #define rx_x4_status2_aerMMDportSelect_BCST_ln0_1 512 8367 #define rx_x4_status2_aerMMDportSelect_BCST_ln2_3 513 8368 8369 /**************************************************************************** 8370 * Enums: rx_x4_status2_firmwareModeSelect 8371 */ 8372 #define rx_x4_status2_firmwareModeSelect_DEFAULT 0 8373 #define rx_x4_status2_firmwareModeSelect_SFP_OPT_LR 1 8374 #define rx_x4_status2_firmwareModeSelect_SFP_DAC 2 8375 #define rx_x4_status2_firmwareModeSelect_XLAUI 3 8376 #define rx_x4_status2_firmwareModeSelect_LONG_CH_6G 4 8377 8378 /**************************************************************************** 8379 * Enums: rx_x4_status2_tempIdxSelect 8380 */ 8381 #define rx_x4_status2_tempIdxSelect_LTE__22p9C 15 8382 #define rx_x4_status2_tempIdxSelect_LTE__12p6C 14 8383 #define rx_x4_status2_tempIdxSelect_LTE__3p0C 13 8384 #define rx_x4_status2_tempIdxSelect_LTE_6p7C 12 8385 #define rx_x4_status2_tempIdxSelect_LTE_16p4C 11 8386 #define rx_x4_status2_tempIdxSelect_LTE_26p6C 10 8387 #define rx_x4_status2_tempIdxSelect_LTE_36p3C 9 8388 #define rx_x4_status2_tempIdxSelect_LTE_46p0C 8 8389 #define rx_x4_status2_tempIdxSelect_LTE_56p2C 7 8390 #define rx_x4_status2_tempIdxSelect_LTE_65p9C 6 8391 #define rx_x4_status2_tempIdxSelect_LTE_75p6C 5 8392 #define rx_x4_status2_tempIdxSelect_LTE_85p3C 4 8393 #define rx_x4_status2_tempIdxSelect_LTE_95p5C 3 8394 #define rx_x4_status2_tempIdxSelect_LTE_105p2C 2 8395 #define rx_x4_status2_tempIdxSelect_LTE_114p9C 1 8396 #define rx_x4_status2_tempIdxSelect_LTE_125p1C 0 8397 8398 /**************************************************************************** 8399 * Enums: rx_x4_status2_port_mode 8400 */ 8401 #define rx_x4_status2_port_mode_QUAD_PORT 0 8402 #define rx_x4_status2_port_mode_TRI_1_PORT 1 8403 #define rx_x4_status2_port_mode_TRI_2_PORT 2 8404 #define rx_x4_status2_port_mode_DUAL_PORT 3 8405 #define rx_x4_status2_port_mode_SINGLE_PORT 4 8406 8407 /**************************************************************************** 8408 * Enums: rx_x4_status2_rev_letter_enum 8409 */ 8410 #define rx_x4_status2_rev_letter_enum_REV_A 0 8411 #define rx_x4_status2_rev_letter_enum_REV_B 1 8412 #define rx_x4_status2_rev_letter_enum_REV_C 2 8413 #define rx_x4_status2_rev_letter_enum_REV_D 3 8414 8415 /**************************************************************************** 8416 * Enums: rx_x4_status2_rev_number_enum 8417 */ 8418 #define rx_x4_status2_rev_number_enum_REV_0 0 8419 #define rx_x4_status2_rev_number_enum_REV_1 1 8420 #define rx_x4_status2_rev_number_enum_REV_2 2 8421 #define rx_x4_status2_rev_number_enum_REV_3 3 8422 #define rx_x4_status2_rev_number_enum_REV_4 4 8423 #define rx_x4_status2_rev_number_enum_REV_5 5 8424 #define rx_x4_status2_rev_number_enum_REV_6 6 8425 #define rx_x4_status2_rev_number_enum_REV_7 7 8426 8427 /**************************************************************************** 8428 * Enums: rx_x4_status2_bonding_enum 8429 */ 8430 #define rx_x4_status2_bonding_enum_WIRE_BOND 0 8431 #define rx_x4_status2_bonding_enum_FLIP_CHIP 1 8432 8433 /**************************************************************************** 8434 * Enums: rx_x4_status2_tech_process 8435 */ 8436 #define rx_x4_status2_tech_process_PROCESS_90NM 0 8437 #define rx_x4_status2_tech_process_PROCESS_65NM 1 8438 #define rx_x4_status2_tech_process_PROCESS_40NM 2 8439 #define rx_x4_status2_tech_process_PROCESS_28NM 3 8440 #define rx_x4_status2_tech_process_PROCESS_16NM 4 8441 8442 /**************************************************************************** 8443 * Enums: rx_x4_status2_model_num 8444 */ 8445 #define rx_x4_status2_model_num_SERDES_CL73 0 8446 #define rx_x4_status2_model_num_XGXS_16G 1 8447 #define rx_x4_status2_model_num_HYPERCORE 2 8448 #define rx_x4_status2_model_num_HYPERLITE 3 8449 #define rx_x4_status2_model_num_PCIE_G2_PIPE 4 8450 #define rx_x4_status2_model_num_SERDES_1p25GBd 5 8451 #define rx_x4_status2_model_num_SATA2 6 8452 #define rx_x4_status2_model_num_QSGMII 7 8453 #define rx_x4_status2_model_num_XGXS10G 8 8454 #define rx_x4_status2_model_num_WARPCORE 9 8455 #define rx_x4_status2_model_num_XFICORE 10 8456 #define rx_x4_status2_model_num_RXFI 11 8457 #define rx_x4_status2_model_num_WARPLITE 12 8458 #define rx_x4_status2_model_num_PENTACORE 13 8459 #define rx_x4_status2_model_num_ESM 14 8460 #define rx_x4_status2_model_num_QUAD_SGMII 15 8461 #define rx_x4_status2_model_num_WARPCORE_3 16 8462 #define rx_x4_status2_model_num_TSC 17 8463 #define rx_x4_status2_model_num_TSC4E 18 8464 #define rx_x4_status2_model_num_TSC12E 19 8465 #define rx_x4_status2_model_num_TSC4F 20 8466 #define rx_x4_status2_model_num_TSC4F_GEN2 21 8467 #define rx_x4_status2_model_num_XGXS_CL73_90NM 29 8468 #define rx_x4_status2_model_num_SERDES_CL73_90NM 30 8469 #define rx_x4_status2_model_num_WARPCORE3 32 8470 #define rx_x4_status2_model_num_WARPCORE4_TSC 33 8471 #define rx_x4_status2_model_num_RXAUI 34 8472 8473 /**************************************************************************** 8474 * Enums: rx_x4_status2_payload 8475 */ 8476 #define rx_x4_status2_payload_REPEAT_2_BYTES 0 8477 #define rx_x4_status2_payload_RAMPING 1 8478 #define rx_x4_status2_payload_CL48_CRPAT 2 8479 #define rx_x4_status2_payload_CL48_CJPAT 3 8480 #define rx_x4_status2_payload_CL36_LONG_CRPAT 4 8481 #define rx_x4_status2_payload_CL36_SHORT_CRPAT 5 8482 8483 /**************************************************************************** 8484 * Enums: rx_x4_status2_sc 8485 */ 8486 #define rx_x4_status2_sc_S_10G_CR1 0 8487 #define rx_x4_status2_sc_S_10G_KR1 1 8488 #define rx_x4_status2_sc_S_10G_X1 2 8489 #define rx_x4_status2_sc_S_10G_HG2_CR1 4 8490 #define rx_x4_status2_sc_S_10G_HG2_KR1 5 8491 #define rx_x4_status2_sc_S_10G_HG2_X1 6 8492 #define rx_x4_status2_sc_S_20G_CR1 8 8493 #define rx_x4_status2_sc_S_20G_KR1 9 8494 #define rx_x4_status2_sc_S_20G_X1 10 8495 #define rx_x4_status2_sc_S_20G_HG2_CR1 12 8496 #define rx_x4_status2_sc_S_20G_HG2_KR1 13 8497 #define rx_x4_status2_sc_S_20G_HG2_X1 14 8498 #define rx_x4_status2_sc_S_25G_CR1 16 8499 #define rx_x4_status2_sc_S_25G_KR1 17 8500 #define rx_x4_status2_sc_S_25G_X1 18 8501 #define rx_x4_status2_sc_S_25G_HG2_CR1 20 8502 #define rx_x4_status2_sc_S_25G_HG2_KR1 21 8503 #define rx_x4_status2_sc_S_25G_HG2_X1 22 8504 #define rx_x4_status2_sc_S_20G_CR2 24 8505 #define rx_x4_status2_sc_S_20G_KR2 25 8506 #define rx_x4_status2_sc_S_20G_X2 26 8507 #define rx_x4_status2_sc_S_20G_HG2_CR2 28 8508 #define rx_x4_status2_sc_S_20G_HG2_KR2 29 8509 #define rx_x4_status2_sc_S_20G_HG2_X2 30 8510 #define rx_x4_status2_sc_S_40G_CR2 32 8511 #define rx_x4_status2_sc_S_40G_KR2 33 8512 #define rx_x4_status2_sc_S_40G_X2 34 8513 #define rx_x4_status2_sc_S_40G_HG2_CR2 36 8514 #define rx_x4_status2_sc_S_40G_HG2_KR2 37 8515 #define rx_x4_status2_sc_S_40G_HG2_X2 38 8516 #define rx_x4_status2_sc_S_40G_CR4 40 8517 #define rx_x4_status2_sc_S_40G_KR4 41 8518 #define rx_x4_status2_sc_S_40G_X4 42 8519 #define rx_x4_status2_sc_S_40G_HG2_CR4 44 8520 #define rx_x4_status2_sc_S_40G_HG2_KR4 45 8521 #define rx_x4_status2_sc_S_40G_HG2_X4 46 8522 #define rx_x4_status2_sc_S_50G_CR2 48 8523 #define rx_x4_status2_sc_S_50G_KR2 49 8524 #define rx_x4_status2_sc_S_50G_X2 50 8525 #define rx_x4_status2_sc_S_50G_HG2_CR2 52 8526 #define rx_x4_status2_sc_S_50G_HG2_KR2 53 8527 #define rx_x4_status2_sc_S_50G_HG2_X2 54 8528 #define rx_x4_status2_sc_S_50G_CR4 56 8529 #define rx_x4_status2_sc_S_50G_KR4 57 8530 #define rx_x4_status2_sc_S_50G_X4 58 8531 #define rx_x4_status2_sc_S_50G_HG2_CR4 60 8532 #define rx_x4_status2_sc_S_50G_HG2_KR4 61 8533 #define rx_x4_status2_sc_S_50G_HG2_X4 62 8534 #define rx_x4_status2_sc_S_100G_CR4 64 8535 #define rx_x4_status2_sc_S_100G_KR4 65 8536 #define rx_x4_status2_sc_S_100G_X4 66 8537 #define rx_x4_status2_sc_S_100G_HG2_CR4 68 8538 #define rx_x4_status2_sc_S_100G_HG2_KR4 69 8539 #define rx_x4_status2_sc_S_100G_HG2_X4 70 8540 #define rx_x4_status2_sc_S_CL73_20GVCO 72 8541 #define rx_x4_status2_sc_S_CL73_25GVCO 80 8542 #define rx_x4_status2_sc_S_CL36_20GVCO 88 8543 #define rx_x4_status2_sc_S_CL36_25GVCO 96 8544 #define rx_x4_status2_sc_S_25G_CR_IEEE 112 8545 #define rx_x4_status2_sc_S_25G_CRS_IEEE 113 8546 #define rx_x4_status2_sc_S_25G_KR_IEEE 114 8547 #define rx_x4_status2_sc_S_25G_KRS_IEEE 115 8548 8549 /**************************************************************************** 8550 * Enums: rx_x4_status2_t_fifo_modes 8551 */ 8552 #define rx_x4_status2_t_fifo_modes_T_FIFO_INSERT_NO_AM 0 8553 #define rx_x4_status2_t_fifo_modes_T_FIFO_INSERT_4_AM 1 8554 #define rx_x4_status2_t_fifo_modes_T_FIFO_INSERT_20_AM 2 8555 #define rx_x4_status2_t_fifo_modes_T_FIFO_INSERT_2_AM 3 8556 8557 /**************************************************************************** 8558 * Enums: rx_x4_status2_t_enc_modes 8559 */ 8560 #define rx_x4_status2_t_enc_modes_T_ENC_MODE_BYPASS 0 8561 #define rx_x4_status2_t_enc_modes_T_ENC_MODE_CL49 1 8562 #define rx_x4_status2_t_enc_modes_T_ENC_MODE_CL82 2 8563 8564 /**************************************************************************** 8565 * Enums: rx_x4_status2_btmx_mode 8566 */ 8567 #define rx_x4_status2_btmx_mode_BS_BTMX_MODE_1to1 0 8568 #define rx_x4_status2_btmx_mode_BS_BTMX_MODE_2to1 1 8569 #define rx_x4_status2_btmx_mode_BS_BTMX_MODE_5to1 2 8570 8571 /**************************************************************************** 8572 * Enums: rx_x4_status2_t_type_cl82 8573 */ 8574 #define rx_x4_status2_t_type_cl82_T_TYPE_B1 5 8575 #define rx_x4_status2_t_type_cl82_T_TYPE_C 4 8576 #define rx_x4_status2_t_type_cl82_T_TYPE_S 3 8577 #define rx_x4_status2_t_type_cl82_T_TYPE_T 2 8578 #define rx_x4_status2_t_type_cl82_T_TYPE_D 1 8579 #define rx_x4_status2_t_type_cl82_T_TYPE_E 0 8580 8581 /**************************************************************************** 8582 * Enums: rx_x4_status2_txsm_state_cl82 8583 */ 8584 #define rx_x4_status2_txsm_state_cl82_TX_HIG_END 6 8585 #define rx_x4_status2_txsm_state_cl82_TX_HIG_START 5 8586 #define rx_x4_status2_txsm_state_cl82_TX_E 4 8587 #define rx_x4_status2_txsm_state_cl82_TX_T 3 8588 #define rx_x4_status2_txsm_state_cl82_TX_D 2 8589 #define rx_x4_status2_txsm_state_cl82_TX_C 1 8590 #define rx_x4_status2_txsm_state_cl82_TX_INIT 0 8591 8592 /**************************************************************************** 8593 * Enums: rx_x4_status2_ltxsm_state_cl82 8594 */ 8595 #define rx_x4_status2_ltxsm_state_cl82_TX_HIG_END 64 8596 #define rx_x4_status2_ltxsm_state_cl82_TX_HIG_START 32 8597 #define rx_x4_status2_ltxsm_state_cl82_TX_E 16 8598 #define rx_x4_status2_ltxsm_state_cl82_TX_T 8 8599 #define rx_x4_status2_ltxsm_state_cl82_TX_D 4 8600 #define rx_x4_status2_ltxsm_state_cl82_TX_C 2 8601 #define rx_x4_status2_ltxsm_state_cl82_TX_INIT 1 8602 8603 /**************************************************************************** 8604 * Enums: rx_x4_status2_r_type_coded_cl82 8605 */ 8606 #define rx_x4_status2_r_type_coded_cl82_R_TYPE_B1 32 8607 #define rx_x4_status2_r_type_coded_cl82_R_TYPE_C 16 8608 #define rx_x4_status2_r_type_coded_cl82_R_TYPE_S 8 8609 #define rx_x4_status2_r_type_coded_cl82_R_TYPE_T 4 8610 #define rx_x4_status2_r_type_coded_cl82_R_TYPE_D 2 8611 #define rx_x4_status2_r_type_coded_cl82_R_TYPE_E 1 8612 8613 /**************************************************************************** 8614 * Enums: rx_x4_status2_rxsm_state_cl82 8615 */ 8616 #define rx_x4_status2_rxsm_state_cl82_RX_HIG_END 64 8617 #define rx_x4_status2_rxsm_state_cl82_RX_HIG_START 32 8618 #define rx_x4_status2_rxsm_state_cl82_RX_E 16 8619 #define rx_x4_status2_rxsm_state_cl82_RX_T 8 8620 #define rx_x4_status2_rxsm_state_cl82_RX_D 4 8621 #define rx_x4_status2_rxsm_state_cl82_RX_C 2 8622 #define rx_x4_status2_rxsm_state_cl82_RX_INIT 1 8623 8624 /**************************************************************************** 8625 * Enums: rx_x4_status2_deskew_state 8626 */ 8627 #define rx_x4_status2_deskew_state_ALIGN_ACQUIRED 2 8628 #define rx_x4_status2_deskew_state_LOSS_OF_ALIGNMENT 1 8629 8630 /**************************************************************************** 8631 * Enums: rx_x4_status2_os_mode_enum 8632 */ 8633 #define rx_x4_status2_os_mode_enum_OS_MODE_1 0 8634 #define rx_x4_status2_os_mode_enum_OS_MODE_2 1 8635 #define rx_x4_status2_os_mode_enum_OS_MODE_4 2 8636 #define rx_x4_status2_os_mode_enum_OS_MODE_16p5 8 8637 #define rx_x4_status2_os_mode_enum_OS_MODE_20p625 12 8638 8639 /**************************************************************************** 8640 * Enums: rx_x4_status2_scr_modes 8641 */ 8642 #define rx_x4_status2_scr_modes_T_SCR_MODE_BYPASS 0 8643 #define rx_x4_status2_scr_modes_T_SCR_MODE_CL49 1 8644 #define rx_x4_status2_scr_modes_T_SCR_MODE_40G_2_LANE 2 8645 #define rx_x4_status2_scr_modes_T_SCR_MODE_100G 3 8646 #define rx_x4_status2_scr_modes_T_SCR_MODE_20G 4 8647 #define rx_x4_status2_scr_modes_T_SCR_MODE_40G_4_LANE 5 8648 8649 /**************************************************************************** 8650 * Enums: rx_x4_status2_descr_modes 8651 */ 8652 #define rx_x4_status2_descr_modes_R_DESCR_MODE_BYPASS 0 8653 #define rx_x4_status2_descr_modes_R_DESCR_MODE_CL49 1 8654 #define rx_x4_status2_descr_modes_R_DESCR_MODE_CL82 2 8655 8656 /**************************************************************************** 8657 * Enums: rx_x4_status2_r_dec_tl_mode 8658 */ 8659 #define rx_x4_status2_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 8660 #define rx_x4_status2_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 8661 #define rx_x4_status2_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 8662 8663 /**************************************************************************** 8664 * Enums: rx_x4_status2_r_dec_fsm_mode 8665 */ 8666 #define rx_x4_status2_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 8667 #define rx_x4_status2_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 8668 #define rx_x4_status2_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 8669 8670 /**************************************************************************** 8671 * Enums: rx_x4_status2_r_deskew_mode 8672 */ 8673 #define rx_x4_status2_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 8674 #define rx_x4_status2_r_deskew_mode_R_DESKEW_MODE_20G 1 8675 #define rx_x4_status2_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 8676 #define rx_x4_status2_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 8677 #define rx_x4_status2_r_deskew_mode_R_DESKEW_MODE_100G 4 8678 #define rx_x4_status2_r_deskew_mode_R_DESKEW_MODE_CL49 5 8679 #define rx_x4_status2_r_deskew_mode_R_DESKEW_MODE_CL91_QUAD 6 8680 #define rx_x4_status2_r_deskew_mode_R_DESKEW_MODE_CL91_SINGLE_BRCM 7 8681 #define rx_x4_status2_r_deskew_mode_R_DESKEW_MODE_CL91_DUAL_BRCM 8 8682 #define rx_x4_status2_r_deskew_mode_R_DESKEW_MODE_CL91_FC 9 8683 8684 /**************************************************************************** 8685 * Enums: rx_x4_status2_bs_dist_modes 8686 */ 8687 #define rx_x4_status2_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 8688 #define rx_x4_status2_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 8689 #define rx_x4_status2_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 8690 #define rx_x4_status2_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 8691 8692 /**************************************************************************** 8693 * Enums: rx_x4_status2_cl49_t_type 8694 */ 8695 #define rx_x4_status2_cl49_t_type_BAD_T_TYPE 15 8696 #define rx_x4_status2_cl49_t_type_T_TYPE_B0 11 8697 #define rx_x4_status2_cl49_t_type_T_TYPE_OB 10 8698 #define rx_x4_status2_cl49_t_type_T_TYPE_B1 9 8699 #define rx_x4_status2_cl49_t_type_T_TYPE_DB 8 8700 #define rx_x4_status2_cl49_t_type_T_TYPE_FC 7 8701 #define rx_x4_status2_cl49_t_type_T_TYPE_TB 6 8702 #define rx_x4_status2_cl49_t_type_T_TYPE_LI 5 8703 #define rx_x4_status2_cl49_t_type_T_TYPE_C 4 8704 #define rx_x4_status2_cl49_t_type_T_TYPE_S 3 8705 #define rx_x4_status2_cl49_t_type_T_TYPE_T 2 8706 #define rx_x4_status2_cl49_t_type_T_TYPE_D 1 8707 #define rx_x4_status2_cl49_t_type_T_TYPE_E 0 8708 8709 /**************************************************************************** 8710 * Enums: rx_x4_status2_cl49_txsm_states 8711 */ 8712 #define rx_x4_status2_cl49_txsm_states_TX_HIG_END 7 8713 #define rx_x4_status2_cl49_txsm_states_TX_HIG_START 6 8714 #define rx_x4_status2_cl49_txsm_states_TX_LI 5 8715 #define rx_x4_status2_cl49_txsm_states_TX_E 4 8716 #define rx_x4_status2_cl49_txsm_states_TX_T 3 8717 #define rx_x4_status2_cl49_txsm_states_TX_D 2 8718 #define rx_x4_status2_cl49_txsm_states_TX_C 1 8719 #define rx_x4_status2_cl49_txsm_states_TX_INIT 0 8720 8721 /**************************************************************************** 8722 * Enums: rx_x4_status2_cl49_ltxsm_states 8723 */ 8724 #define rx_x4_status2_cl49_ltxsm_states_TX_HIG_END 128 8725 #define rx_x4_status2_cl49_ltxsm_states_TX_HIG_START 64 8726 #define rx_x4_status2_cl49_ltxsm_states_TX_LI 32 8727 #define rx_x4_status2_cl49_ltxsm_states_TX_E 16 8728 #define rx_x4_status2_cl49_ltxsm_states_TX_T 8 8729 #define rx_x4_status2_cl49_ltxsm_states_TX_D 4 8730 #define rx_x4_status2_cl49_ltxsm_states_TX_C 2 8731 #define rx_x4_status2_cl49_ltxsm_states_TX_INIT 1 8732 8733 /**************************************************************************** 8734 * Enums: rx_x4_status2_burst_error_mode 8735 */ 8736 #define rx_x4_status2_burst_error_mode_BURST_ERROR_11_BITS 0 8737 #define rx_x4_status2_burst_error_mode_BURST_ERROR_16_BITS 1 8738 #define rx_x4_status2_burst_error_mode_BURST_ERROR_17_BITS 2 8739 #define rx_x4_status2_burst_error_mode_BURST_ERROR_18_BITS 3 8740 #define rx_x4_status2_burst_error_mode_BURST_ERROR_19_BITS 4 8741 #define rx_x4_status2_burst_error_mode_BURST_ERROR_20_BITS 5 8742 #define rx_x4_status2_burst_error_mode_BURST_ERROR_21_BITS 6 8743 #define rx_x4_status2_burst_error_mode_BURST_ERROR_22_BITS 7 8744 #define rx_x4_status2_burst_error_mode_BURST_ERROR_23_BITS 8 8745 #define rx_x4_status2_burst_error_mode_BURST_ERROR_24_BITS 9 8746 #define rx_x4_status2_burst_error_mode_BURST_ERROR_25_BITS 10 8747 #define rx_x4_status2_burst_error_mode_BURST_ERROR_26_BITS 11 8748 #define rx_x4_status2_burst_error_mode_BURST_ERROR_27_BITS 12 8749 #define rx_x4_status2_burst_error_mode_BURST_ERROR_28_BITS 13 8750 #define rx_x4_status2_burst_error_mode_BURST_ERROR_29_BITS 14 8751 #define rx_x4_status2_burst_error_mode_BURST_ERROR_30_BITS 15 8752 #define rx_x4_status2_burst_error_mode_BURST_ERROR_31_BITS 16 8753 #define rx_x4_status2_burst_error_mode_BURST_ERROR_32_BITS 17 8754 #define rx_x4_status2_burst_error_mode_BURST_ERROR_33_BITS 18 8755 #define rx_x4_status2_burst_error_mode_BURST_ERROR_34_BITS 19 8756 #define rx_x4_status2_burst_error_mode_BURST_ERROR_35_BITS 20 8757 #define rx_x4_status2_burst_error_mode_BURST_ERROR_36_BITS 21 8758 #define rx_x4_status2_burst_error_mode_BURST_ERROR_37_BITS 22 8759 #define rx_x4_status2_burst_error_mode_BURST_ERROR_38_BITS 23 8760 #define rx_x4_status2_burst_error_mode_BURST_ERROR_39_BITS 24 8761 #define rx_x4_status2_burst_error_mode_BURST_ERROR_40_BITS 25 8762 #define rx_x4_status2_burst_error_mode_BURST_ERROR_41_BITS 26 8763 8764 /**************************************************************************** 8765 * Enums: rx_x4_status2_bermon_state 8766 */ 8767 #define rx_x4_status2_bermon_state_HI_BER 4 8768 #define rx_x4_status2_bermon_state_GOOD_BER 3 8769 #define rx_x4_status2_bermon_state_BER_TEST_SH 2 8770 #define rx_x4_status2_bermon_state_START_TIMER 1 8771 #define rx_x4_status2_bermon_state_BER_MT_INIT 0 8772 8773 /**************************************************************************** 8774 * Enums: rx_x4_status2_rxsm_state_cl49 8775 */ 8776 #define rx_x4_status2_rxsm_state_cl49_RX_HIG_END 128 8777 #define rx_x4_status2_rxsm_state_cl49_RX_HIG_START 64 8778 #define rx_x4_status2_rxsm_state_cl49_RX_LI 32 8779 #define rx_x4_status2_rxsm_state_cl49_RX_E 16 8780 #define rx_x4_status2_rxsm_state_cl49_RX_T 8 8781 #define rx_x4_status2_rxsm_state_cl49_RX_D 4 8782 #define rx_x4_status2_rxsm_state_cl49_RX_C 2 8783 #define rx_x4_status2_rxsm_state_cl49_RX_INIT 1 8784 8785 /**************************************************************************** 8786 * Enums: rx_x4_status2_r_type 8787 */ 8788 #define rx_x4_status2_r_type_BAD_R_TYPE 15 8789 #define rx_x4_status2_r_type_R_TYPE_B0 11 8790 #define rx_x4_status2_r_type_R_TYPE_OB 10 8791 #define rx_x4_status2_r_type_R_TYPE_B1 9 8792 #define rx_x4_status2_r_type_R_TYPE_DB 8 8793 #define rx_x4_status2_r_type_R_TYPE_FC 7 8794 #define rx_x4_status2_r_type_R_TYPE_TB 6 8795 #define rx_x4_status2_r_type_R_TYPE_LI 5 8796 #define rx_x4_status2_r_type_R_TYPE_C 4 8797 #define rx_x4_status2_r_type_R_TYPE_S 3 8798 #define rx_x4_status2_r_type_R_TYPE_T 2 8799 #define rx_x4_status2_r_type_R_TYPE_D 1 8800 #define rx_x4_status2_r_type_R_TYPE_E 0 8801 8802 /**************************************************************************** 8803 * Enums: rx_x4_status2_am_lock_state 8804 */ 8805 #define rx_x4_status2_am_lock_state_INVALID_AM 512 8806 #define rx_x4_status2_am_lock_state_GOOD_AM 256 8807 #define rx_x4_status2_am_lock_state_COMP_AM 128 8808 #define rx_x4_status2_am_lock_state_TIMER_2 64 8809 #define rx_x4_status2_am_lock_state_AM_2_GOOD 32 8810 #define rx_x4_status2_am_lock_state_COMP_2ND 16 8811 #define rx_x4_status2_am_lock_state_TIMER_1 8 8812 #define rx_x4_status2_am_lock_state_FIND_1ST 4 8813 #define rx_x4_status2_am_lock_state_AM_RESET_CNT 2 8814 #define rx_x4_status2_am_lock_state_AM_LOCK_INIT 1 8815 8816 /**************************************************************************** 8817 * Enums: rx_x4_status2_msg_selector 8818 */ 8819 #define rx_x4_status2_msg_selector_RESERVED 0 8820 #define rx_x4_status2_msg_selector_VALUE_802p3 1 8821 #define rx_x4_status2_msg_selector_VALUE_802p9 2 8822 #define rx_x4_status2_msg_selector_VALUE_802p5 3 8823 #define rx_x4_status2_msg_selector_VALUE_1394 4 8824 8825 /**************************************************************************** 8826 * Enums: rx_x4_status2_synce_enum 8827 */ 8828 #define rx_x4_status2_synce_enum_SYNCE_NO_DIV 0 8829 #define rx_x4_status2_synce_enum_SYNCE_DIV_7 1 8830 #define rx_x4_status2_synce_enum_SYNCE_DIV_11 2 8831 8832 /**************************************************************************** 8833 * Enums: rx_x4_status2_synce_enum_stage0 8834 */ 8835 #define rx_x4_status2_synce_enum_stage0_SYNCE_NO_DIV 0 8836 #define rx_x4_status2_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 8837 #define rx_x4_status2_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 8838 8839 /**************************************************************************** 8840 * Enums: rx_x4_status2_cl91_sync_state 8841 */ 8842 #define rx_x4_status2_cl91_sync_state_FIND_1ST 0 8843 #define rx_x4_status2_cl91_sync_state_COUNT_NEXT 1 8844 #define rx_x4_status2_cl91_sync_state_COMP_2ND 2 8845 #define rx_x4_status2_cl91_sync_state_TWO_GOOD 3 8846 8847 /**************************************************************************** 8848 * Enums: rx_x4_status2_cl91_algn_state 8849 */ 8850 #define rx_x4_status2_cl91_algn_state_LOSS_OF_ALIGNMENT 0 8851 #define rx_x4_status2_cl91_algn_state_DESKEW 1 8852 #define rx_x4_status2_cl91_algn_state_DESKEW_FAIL 2 8853 #define rx_x4_status2_cl91_algn_state_ALIGN_ACQUIRED 3 8854 #define rx_x4_status2_cl91_algn_state_CW_GOOD 4 8855 #define rx_x4_status2_cl91_algn_state_CW_BAD 5 8856 #define rx_x4_status2_cl91_algn_state_THREE_BAD 6 8857 8858 /**************************************************************************** 8859 * Enums: rx_x4_status2_fec_sel_override 8860 */ 8861 #define rx_x4_status2_fec_sel_override_NO_OVERRIDE 0 8862 #define rx_x4_status2_fec_sel_override_NO_FEC 1 8863 #define rx_x4_status2_fec_sel_override_FEC_CL74 2 8864 #define rx_x4_status2_fec_sel_override_FEC_CL91 3 8865 8866 /**************************************************************************** 8867 * Enums: rx_x4_status2_cl91_blksync_mode 8868 */ 8869 #define rx_x4_status2_cl91_blksync_mode_R_BLKSYNC_NO_CL91_FEC 0 8870 #define rx_x4_status2_cl91_blksync_mode_R_BLKSYNC_CL91_QUAD_LANE_FEC 1 8871 #define rx_x4_status2_cl91_blksync_mode_R_BLKSYNC_CL91_DUAL_LANE_FEC 2 8872 #define rx_x4_status2_cl91_blksync_mode_R_BLKSYNC_CL91_SINGLE_LANE_FEC 3 8873 #define rx_x4_status2_cl91_blksync_mode_R_BLKSYNC_CL91_FC_FEC 4 8874 8875 /**************************************************************************** 8876 * Enums: rx_x4_status2_r_merge_mode 8877 */ 8878 #define rx_x4_status2_r_merge_mode_R_MERGE_MODE_BYPASS 0 8879 #define rx_x4_status2_r_merge_mode_R_MERGE_MODE_CL91_FC 1 8880 #define rx_x4_status2_r_merge_mode_R_MERGE_MODE_CL91_SINGLE_LANE 2 8881 #define rx_x4_status2_r_merge_mode_R_MERGE_MODE_CL91_DUAL_LANE 3 8882 #define rx_x4_status2_r_merge_mode_R_MERGE_MODE_CL91_QUAD_LANE 4 8883 8884 /**************************************************************************** 8885 * Enums: rx_x4_status2_r_tc_mode 8886 */ 8887 #define rx_x4_status2_r_tc_mode_R_TC_MODE_SINGLE 0 8888 #define rx_x4_status2_r_tc_mode_R_TC_MODE_DUAL 1 8889 #define rx_x4_status2_r_tc_mode_R_TC_MODE_QUAD 2 8890 8891 /**************************************************************************** 8892 * Enums: rx_x4_status2_r_tc_out_mode 8893 */ 8894 #define rx_x4_status2_r_tc_out_mode_R_TC_OUT_MODE_SINGLE 0 8895 #define rx_x4_status2_r_tc_out_mode_R_TC_OUT_MODE_DUAL 1 8896 #define rx_x4_status2_r_tc_out_mode_R_TC_OUT_MODE_QUAD 2 8897 8898 /**************************************************************************** 8899 * Enums: rx_x4_status2_cl91_fec_mode 8900 */ 8901 #define rx_x4_status2_cl91_fec_mode_NO_CL91_FEC 0 8902 #define rx_x4_status2_cl91_fec_mode_CL91_SINGLE_LANE_FC 1 8903 #define rx_x4_status2_cl91_fec_mode_CL91_SINGLE_LANE_BRCM_PROP 2 8904 #define rx_x4_status2_cl91_fec_mode_CL91_DUAL_LANE_BRCM_PROP 3 8905 #define rx_x4_status2_cl91_fec_mode_CL91_QUAD_LANE 4 8906 #define rx_x4_status2_cl91_fec_mode_IEEE_25G_CL91_SINGLE_LANE 5 8907 8908 /**************************************************************************** 8909 * Enums: rx_x4_status2_am_spacing_mul 8910 */ 8911 #define rx_x4_status2_am_spacing_mul_AM_SPACING_MUL_2 0 8912 #define rx_x4_status2_am_spacing_mul_AM_SPACING_MUL_4 1 8913 #define rx_x4_status2_am_spacing_mul_AM_SPACING_MUL_5 2 8914 #define rx_x4_status2_am_spacing_mul_AM_SPACING_MUL_20 3 8915 8916 /**************************************************************************** 8917 * Enums: rx_x4_status3_cl36TxEEEStates_l 8918 */ 8919 #define rx_x4_status3_cl36TxEEEStates_l_TX_REFRESH 8 8920 #define rx_x4_status3_cl36TxEEEStates_l_TX_QUIET 4 8921 #define rx_x4_status3_cl36TxEEEStates_l_TX_SLEEP 2 8922 #define rx_x4_status3_cl36TxEEEStates_l_TX_ACTIVE 1 8923 8924 /**************************************************************************** 8925 * Enums: rx_x4_status3_cl36TxEEEStates_c 8926 */ 8927 #define rx_x4_status3_cl36TxEEEStates_c_TX_REFRESH 3 8928 #define rx_x4_status3_cl36TxEEEStates_c_TX_QUIET 2 8929 #define rx_x4_status3_cl36TxEEEStates_c_TX_SLEEP 1 8930 #define rx_x4_status3_cl36TxEEEStates_c_TX_ACTIVE 0 8931 8932 /**************************************************************************** 8933 * Enums: rx_x4_status3_cl49TxEEEStates_l 8934 */ 8935 #define rx_x4_status3_cl49TxEEEStates_l_SCR_RESET_2 64 8936 #define rx_x4_status3_cl49TxEEEStates_l_SCR_RESET_1 32 8937 #define rx_x4_status3_cl49TxEEEStates_l_TX_WAKE 16 8938 #define rx_x4_status3_cl49TxEEEStates_l_TX_REFRESH 8 8939 #define rx_x4_status3_cl49TxEEEStates_l_TX_QUIET 4 8940 #define rx_x4_status3_cl49TxEEEStates_l_TX_SLEEP 2 8941 #define rx_x4_status3_cl49TxEEEStates_l_TX_ACTIVE 1 8942 8943 /**************************************************************************** 8944 * Enums: rx_x4_status3_fec_req_enum 8945 */ 8946 #define rx_x4_status3_fec_req_enum_FEC_not_supported 0 8947 #define rx_x4_status3_fec_req_enum_FEC_supported_but_not_requested 1 8948 #define rx_x4_status3_fec_req_enum_invalid_setting 2 8949 #define rx_x4_status3_fec_req_enum_FEC_supported_and_requested 3 8950 8951 /**************************************************************************** 8952 * Enums: rx_x4_status3_cl73_pause_enum 8953 */ 8954 #define rx_x4_status3_cl73_pause_enum_No_PAUSE_ability 0 8955 #define rx_x4_status3_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 8956 #define rx_x4_status3_cl73_pause_enum_Symmetric_PAUSE_ability 1 8957 #define rx_x4_status3_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 8958 8959 /**************************************************************************** 8960 * Enums: rx_x4_status3_cl49TxEEEStates_c 8961 */ 8962 #define rx_x4_status3_cl49TxEEEStates_c_SCR_RESET_2 6 8963 #define rx_x4_status3_cl49TxEEEStates_c_SCR_RESET_1 5 8964 #define rx_x4_status3_cl49TxEEEStates_c_TX_WAKE 4 8965 #define rx_x4_status3_cl49TxEEEStates_c_TX_REFRESH 3 8966 #define rx_x4_status3_cl49TxEEEStates_c_TX_QUIET 2 8967 #define rx_x4_status3_cl49TxEEEStates_c_TX_SLEEP 1 8968 #define rx_x4_status3_cl49TxEEEStates_c_TX_ACTIVE 0 8969 8970 /**************************************************************************** 8971 * Enums: rx_x4_status3_cl36RxEEEStates_l 8972 */ 8973 #define rx_x4_status3_cl36RxEEEStates_l_RX_LINK_FAIL 32 8974 #define rx_x4_status3_cl36RxEEEStates_l_RX_WTF 16 8975 #define rx_x4_status3_cl36RxEEEStates_l_RX_WAKE 8 8976 #define rx_x4_status3_cl36RxEEEStates_l_RX_QUIET 4 8977 #define rx_x4_status3_cl36RxEEEStates_l_RX_SLEEP 2 8978 #define rx_x4_status3_cl36RxEEEStates_l_RX_ACTIVE 1 8979 8980 /**************************************************************************** 8981 * Enums: rx_x4_status3_cl36RxEEEStates_c 8982 */ 8983 #define rx_x4_status3_cl36RxEEEStates_c_RX_LINK_FAIL 5 8984 #define rx_x4_status3_cl36RxEEEStates_c_RX_WTF 4 8985 #define rx_x4_status3_cl36RxEEEStates_c_RX_WAKE 3 8986 #define rx_x4_status3_cl36RxEEEStates_c_RX_QUIET 2 8987 #define rx_x4_status3_cl36RxEEEStates_c_RX_SLEEP 1 8988 #define rx_x4_status3_cl36RxEEEStates_c_RX_ACTIVE 0 8989 8990 /**************************************************************************** 8991 * Enums: rx_x4_status3_cl49RxEEEStates_l 8992 */ 8993 #define rx_x4_status3_cl49RxEEEStates_l_RX_LINK_FAIL 32 8994 #define rx_x4_status3_cl49RxEEEStates_l_RX_WTF 16 8995 #define rx_x4_status3_cl49RxEEEStates_l_RX_WAKE 8 8996 #define rx_x4_status3_cl49RxEEEStates_l_RX_QUIET 4 8997 #define rx_x4_status3_cl49RxEEEStates_l_RX_SLEEP 2 8998 #define rx_x4_status3_cl49RxEEEStates_l_RX_ACTIVE 1 8999 9000 /**************************************************************************** 9001 * Enums: rx_x4_status3_cl49RxEEEStates_c 9002 */ 9003 #define rx_x4_status3_cl49RxEEEStates_c_RX_LINK_FAIL 5 9004 #define rx_x4_status3_cl49RxEEEStates_c_RX_WTF 4 9005 #define rx_x4_status3_cl49RxEEEStates_c_RX_WAKE 3 9006 #define rx_x4_status3_cl49RxEEEStates_c_RX_QUIET 2 9007 #define rx_x4_status3_cl49RxEEEStates_c_RX_SLEEP 1 9008 #define rx_x4_status3_cl49RxEEEStates_c_RX_ACTIVE 0 9009 9010 /**************************************************************************** 9011 * Enums: rx_x4_status3_cl48TxEEEStates_l 9012 */ 9013 #define rx_x4_status3_cl48TxEEEStates_l_TX_REFRESH 8 9014 #define rx_x4_status3_cl48TxEEEStates_l_TX_QUIET 4 9015 #define rx_x4_status3_cl48TxEEEStates_l_TX_SLEEP 2 9016 #define rx_x4_status3_cl48TxEEEStates_l_TX_ACTIVE 1 9017 9018 /**************************************************************************** 9019 * Enums: rx_x4_status3_cl48TxEEEStates_c 9020 */ 9021 #define rx_x4_status3_cl48TxEEEStates_c_TX_REFRESH 3 9022 #define rx_x4_status3_cl48TxEEEStates_c_TX_QUIET 2 9023 #define rx_x4_status3_cl48TxEEEStates_c_TX_SLEEP 1 9024 #define rx_x4_status3_cl48TxEEEStates_c_TX_ACTIVE 0 9025 9026 /**************************************************************************** 9027 * Enums: rx_x4_status3_cl48RxEEEStates_l 9028 */ 9029 #define rx_x4_status3_cl48RxEEEStates_l_RX_LINK_FAIL 32 9030 #define rx_x4_status3_cl48RxEEEStates_l_RX_WAKE 16 9031 #define rx_x4_status3_cl48RxEEEStates_l_RX_QUIET 8 9032 #define rx_x4_status3_cl48RxEEEStates_l_RX_DEACT 4 9033 #define rx_x4_status3_cl48RxEEEStates_l_RX_SLEEP 2 9034 #define rx_x4_status3_cl48RxEEEStates_l_RX_ACTIVE 1 9035 9036 /**************************************************************************** 9037 * Enums: rx_x4_status3_cl48RxEEEStates_c 9038 */ 9039 #define rx_x4_status3_cl48RxEEEStates_c_RX_LINK_FAIL 5 9040 #define rx_x4_status3_cl48RxEEEStates_c_RX_WAKE 4 9041 #define rx_x4_status3_cl48RxEEEStates_c_RX_QUIET 3 9042 #define rx_x4_status3_cl48RxEEEStates_c_RX_DEACT 2 9043 #define rx_x4_status3_cl48RxEEEStates_c_RX_SLEEP 1 9044 #define rx_x4_status3_cl48RxEEEStates_c_RX_ACTIVE 0 9045 9046 /**************************************************************************** 9047 * Enums: rx_x4_status3_IQP_Options 9048 */ 9049 #define rx_x4_status3_IQP_Options_i50uA 0 9050 #define rx_x4_status3_IQP_Options_i100uA 1 9051 #define rx_x4_status3_IQP_Options_i150uA 2 9052 #define rx_x4_status3_IQP_Options_i200uA 3 9053 #define rx_x4_status3_IQP_Options_i250uA 4 9054 #define rx_x4_status3_IQP_Options_i300uA 5 9055 #define rx_x4_status3_IQP_Options_i350uA 6 9056 #define rx_x4_status3_IQP_Options_i400uA 7 9057 #define rx_x4_status3_IQP_Options_i450uA 8 9058 #define rx_x4_status3_IQP_Options_i500uA 9 9059 #define rx_x4_status3_IQP_Options_i550uA 10 9060 #define rx_x4_status3_IQP_Options_i600uA 11 9061 #define rx_x4_status3_IQP_Options_i650uA 12 9062 #define rx_x4_status3_IQP_Options_i700uA 13 9063 #define rx_x4_status3_IQP_Options_i750uA 14 9064 #define rx_x4_status3_IQP_Options_i800uA 15 9065 9066 /**************************************************************************** 9067 * Enums: rx_x4_status3_IDriver_Options 9068 */ 9069 #define rx_x4_status3_IDriver_Options_v680mV 0 9070 #define rx_x4_status3_IDriver_Options_v730mV 1 9071 #define rx_x4_status3_IDriver_Options_v780mV 2 9072 #define rx_x4_status3_IDriver_Options_v830mV 3 9073 #define rx_x4_status3_IDriver_Options_v880mV 4 9074 #define rx_x4_status3_IDriver_Options_v930mV 5 9075 #define rx_x4_status3_IDriver_Options_v980mV 6 9076 #define rx_x4_status3_IDriver_Options_v1010mV 7 9077 #define rx_x4_status3_IDriver_Options_v1040mV 8 9078 #define rx_x4_status3_IDriver_Options_v1060mV 9 9079 #define rx_x4_status3_IDriver_Options_v1070mV 10 9080 #define rx_x4_status3_IDriver_Options_v1080mV 11 9081 #define rx_x4_status3_IDriver_Options_v1085mV 12 9082 #define rx_x4_status3_IDriver_Options_v1090mV 13 9083 #define rx_x4_status3_IDriver_Options_v1095mV 14 9084 #define rx_x4_status3_IDriver_Options_v1100mV 15 9085 9086 /**************************************************************************** 9087 * Enums: rx_x4_status3_operationModes 9088 */ 9089 #define rx_x4_status3_operationModes_XGXS 0 9090 #define rx_x4_status3_operationModes_XGXG_nCC 1 9091 #define rx_x4_status3_operationModes_Indlane_OS8 4 9092 #define rx_x4_status3_operationModes_IndLane_OS5 5 9093 #define rx_x4_status3_operationModes_PCI 7 9094 #define rx_x4_status3_operationModes_XGXS_nLQ 8 9095 #define rx_x4_status3_operationModes_XGXS_nLQnCC 9 9096 #define rx_x4_status3_operationModes_PBypass 10 9097 #define rx_x4_status3_operationModes_PBypass_nDSK 11 9098 #define rx_x4_status3_operationModes_ComboCoreMode 12 9099 #define rx_x4_status3_operationModes_Clocks_off 15 9100 9101 /**************************************************************************** 9102 * Enums: rx_x4_status3_actualSpeeds 9103 */ 9104 #define rx_x4_status3_actualSpeeds_dr_10M 0 9105 #define rx_x4_status3_actualSpeeds_dr_100M 1 9106 #define rx_x4_status3_actualSpeeds_dr_1G 2 9107 #define rx_x4_status3_actualSpeeds_dr_2p5G 3 9108 #define rx_x4_status3_actualSpeeds_dr_5G_X4 4 9109 #define rx_x4_status3_actualSpeeds_dr_6G_X4 5 9110 #define rx_x4_status3_actualSpeeds_dr_10G_HiG 6 9111 #define rx_x4_status3_actualSpeeds_dr_10G_CX4 7 9112 #define rx_x4_status3_actualSpeeds_dr_12G_HiG 8 9113 #define rx_x4_status3_actualSpeeds_dr_12p5G_X4 9 9114 #define rx_x4_status3_actualSpeeds_dr_13G_X4 10 9115 #define rx_x4_status3_actualSpeeds_dr_15G_X4 11 9116 #define rx_x4_status3_actualSpeeds_dr_16G_X4 12 9117 #define rx_x4_status3_actualSpeeds_dr_1G_KX 13 9118 #define rx_x4_status3_actualSpeeds_dr_10G_KX4 14 9119 #define rx_x4_status3_actualSpeeds_dr_10G_KR 15 9120 #define rx_x4_status3_actualSpeeds_dr_5G 16 9121 #define rx_x4_status3_actualSpeeds_dr_6p4G 17 9122 #define rx_x4_status3_actualSpeeds_dr_20G_X4 18 9123 #define rx_x4_status3_actualSpeeds_dr_21G_X4 19 9124 #define rx_x4_status3_actualSpeeds_dr_25G_X4 20 9125 #define rx_x4_status3_actualSpeeds_dr_10G_HiG_DXGXS 21 9126 #define rx_x4_status3_actualSpeeds_dr_10G_DXGXS 22 9127 #define rx_x4_status3_actualSpeeds_dr_10p5G_HiG_DXGXS 23 9128 #define rx_x4_status3_actualSpeeds_dr_10p5G_DXGXS 24 9129 #define rx_x4_status3_actualSpeeds_dr_12p773G_HiG_DXGXS 25 9130 #define rx_x4_status3_actualSpeeds_dr_12p773G_DXGXS 26 9131 #define rx_x4_status3_actualSpeeds_dr_10G_XFI 27 9132 #define rx_x4_status3_actualSpeeds_dr_40G 28 9133 #define rx_x4_status3_actualSpeeds_dr_20G_HiG_DXGXS 29 9134 #define rx_x4_status3_actualSpeeds_dr_20G_DXGXS 30 9135 #define rx_x4_status3_actualSpeeds_dr_10G_SFI 31 9136 #define rx_x4_status3_actualSpeeds_dr_31p5G 32 9137 #define rx_x4_status3_actualSpeeds_dr_32p7G 33 9138 #define rx_x4_status3_actualSpeeds_dr_20G_SCR 34 9139 #define rx_x4_status3_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 9140 #define rx_x4_status3_actualSpeeds_dr_10G_DXGXS_SCR 36 9141 #define rx_x4_status3_actualSpeeds_dr_12G_R2 37 9142 #define rx_x4_status3_actualSpeeds_dr_10G_X2 38 9143 #define rx_x4_status3_actualSpeeds_dr_40G_KR4 39 9144 #define rx_x4_status3_actualSpeeds_dr_40G_CR4 40 9145 #define rx_x4_status3_actualSpeeds_dr_100G_CR10 41 9146 #define rx_x4_status3_actualSpeeds_dr_15p75G_DXGXS 44 9147 #define rx_x4_status3_actualSpeeds_dr_20G_KR2 57 9148 #define rx_x4_status3_actualSpeeds_dr_20G_CR2 58 9149 9150 /**************************************************************************** 9151 * Enums: rx_x4_status3_actualSpeedsMisc1 9152 */ 9153 #define rx_x4_status3_actualSpeedsMisc1_dr_2500BRCM_X1 16 9154 #define rx_x4_status3_actualSpeedsMisc1_dr_5000BRCM_X4 17 9155 #define rx_x4_status3_actualSpeedsMisc1_dr_6000BRCM_X4 18 9156 #define rx_x4_status3_actualSpeedsMisc1_dr_10GHiGig_X4 19 9157 #define rx_x4_status3_actualSpeedsMisc1_dr_10GBASE_CX4 20 9158 #define rx_x4_status3_actualSpeedsMisc1_dr_12GHiGig_X4 21 9159 #define rx_x4_status3_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 9160 #define rx_x4_status3_actualSpeedsMisc1_dr_13GHiGig_X4 23 9161 #define rx_x4_status3_actualSpeedsMisc1_dr_15GHiGig_X4 24 9162 #define rx_x4_status3_actualSpeedsMisc1_dr_16GHiGig_X4 25 9163 #define rx_x4_status3_actualSpeedsMisc1_dr_5000BRCM_X1 26 9164 #define rx_x4_status3_actualSpeedsMisc1_dr_6363BRCM_X1 27 9165 #define rx_x4_status3_actualSpeedsMisc1_dr_20GHiGig_X4 28 9166 #define rx_x4_status3_actualSpeedsMisc1_dr_21GHiGig_X4 29 9167 #define rx_x4_status3_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 9168 #define rx_x4_status3_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 9169 9170 /**************************************************************************** 9171 * Enums: rx_x4_status3_IndLaneModes 9172 */ 9173 #define rx_x4_status3_IndLaneModes_SWSDR_div2 0 9174 #define rx_x4_status3_IndLaneModes_SWSDR_div1 1 9175 #define rx_x4_status3_IndLaneModes_DWSDR_div2 2 9176 #define rx_x4_status3_IndLaneModes_DWSDR_div1 3 9177 9178 /**************************************************************************** 9179 * Enums: rx_x4_status3_prbsSelect 9180 */ 9181 #define rx_x4_status3_prbsSelect_prbs7 0 9182 #define rx_x4_status3_prbsSelect_prbs15 1 9183 #define rx_x4_status3_prbsSelect_prbs23 2 9184 #define rx_x4_status3_prbsSelect_prbs31 3 9185 9186 /**************************************************************************** 9187 * Enums: rx_x4_status3_vcoDivider 9188 */ 9189 #define rx_x4_status3_vcoDivider_div32 0 9190 #define rx_x4_status3_vcoDivider_div36 1 9191 #define rx_x4_status3_vcoDivider_div40 2 9192 #define rx_x4_status3_vcoDivider_div42 3 9193 #define rx_x4_status3_vcoDivider_div48 4 9194 #define rx_x4_status3_vcoDivider_div50 5 9195 #define rx_x4_status3_vcoDivider_div52 6 9196 #define rx_x4_status3_vcoDivider_div54 7 9197 #define rx_x4_status3_vcoDivider_div60 8 9198 #define rx_x4_status3_vcoDivider_div64 9 9199 #define rx_x4_status3_vcoDivider_div66 10 9200 #define rx_x4_status3_vcoDivider_div68 11 9201 #define rx_x4_status3_vcoDivider_div70 12 9202 #define rx_x4_status3_vcoDivider_div80 13 9203 #define rx_x4_status3_vcoDivider_div92 14 9204 #define rx_x4_status3_vcoDivider_div100 15 9205 9206 /**************************************************************************** 9207 * Enums: rx_x4_status3_refClkSelect 9208 */ 9209 #define rx_x4_status3_refClkSelect_clk_25MHz 0 9210 #define rx_x4_status3_refClkSelect_clk_100MHz 1 9211 #define rx_x4_status3_refClkSelect_clk_125MHz 2 9212 #define rx_x4_status3_refClkSelect_clk_156p25MHz 3 9213 #define rx_x4_status3_refClkSelect_clk_187p5MHz 4 9214 #define rx_x4_status3_refClkSelect_clk_161p25Mhz 5 9215 #define rx_x4_status3_refClkSelect_clk_50Mhz 6 9216 #define rx_x4_status3_refClkSelect_clk_106p25Mhz 7 9217 9218 /**************************************************************************** 9219 * Enums: rx_x4_status3_aerMMDdevTypeSelect 9220 */ 9221 #define rx_x4_status3_aerMMDdevTypeSelect_combo_core 0 9222 #define rx_x4_status3_aerMMDdevTypeSelect_PMA_PMD 1 9223 #define rx_x4_status3_aerMMDdevTypeSelect_PCS 3 9224 #define rx_x4_status3_aerMMDdevTypeSelect_PHY 4 9225 #define rx_x4_status3_aerMMDdevTypeSelect_DTE 5 9226 #define rx_x4_status3_aerMMDdevTypeSelect_CL73_AN 7 9227 9228 /**************************************************************************** 9229 * Enums: rx_x4_status3_aerMMDportSelect 9230 */ 9231 #define rx_x4_status3_aerMMDportSelect_ln0 0 9232 #define rx_x4_status3_aerMMDportSelect_ln1 1 9233 #define rx_x4_status3_aerMMDportSelect_ln2 2 9234 #define rx_x4_status3_aerMMDportSelect_ln3 3 9235 #define rx_x4_status3_aerMMDportSelect_BCST_ln0_1_2_3 511 9236 #define rx_x4_status3_aerMMDportSelect_BCST_ln0_1 512 9237 #define rx_x4_status3_aerMMDportSelect_BCST_ln2_3 513 9238 9239 /**************************************************************************** 9240 * Enums: rx_x4_status3_firmwareModeSelect 9241 */ 9242 #define rx_x4_status3_firmwareModeSelect_DEFAULT 0 9243 #define rx_x4_status3_firmwareModeSelect_SFP_OPT_LR 1 9244 #define rx_x4_status3_firmwareModeSelect_SFP_DAC 2 9245 #define rx_x4_status3_firmwareModeSelect_XLAUI 3 9246 #define rx_x4_status3_firmwareModeSelect_LONG_CH_6G 4 9247 9248 /**************************************************************************** 9249 * Enums: rx_x4_status3_tempIdxSelect 9250 */ 9251 #define rx_x4_status3_tempIdxSelect_LTE__22p9C 15 9252 #define rx_x4_status3_tempIdxSelect_LTE__12p6C 14 9253 #define rx_x4_status3_tempIdxSelect_LTE__3p0C 13 9254 #define rx_x4_status3_tempIdxSelect_LTE_6p7C 12 9255 #define rx_x4_status3_tempIdxSelect_LTE_16p4C 11 9256 #define rx_x4_status3_tempIdxSelect_LTE_26p6C 10 9257 #define rx_x4_status3_tempIdxSelect_LTE_36p3C 9 9258 #define rx_x4_status3_tempIdxSelect_LTE_46p0C 8 9259 #define rx_x4_status3_tempIdxSelect_LTE_56p2C 7 9260 #define rx_x4_status3_tempIdxSelect_LTE_65p9C 6 9261 #define rx_x4_status3_tempIdxSelect_LTE_75p6C 5 9262 #define rx_x4_status3_tempIdxSelect_LTE_85p3C 4 9263 #define rx_x4_status3_tempIdxSelect_LTE_95p5C 3 9264 #define rx_x4_status3_tempIdxSelect_LTE_105p2C 2 9265 #define rx_x4_status3_tempIdxSelect_LTE_114p9C 1 9266 #define rx_x4_status3_tempIdxSelect_LTE_125p1C 0 9267 9268 /**************************************************************************** 9269 * Enums: rx_x4_status3_port_mode 9270 */ 9271 #define rx_x4_status3_port_mode_QUAD_PORT 0 9272 #define rx_x4_status3_port_mode_TRI_1_PORT 1 9273 #define rx_x4_status3_port_mode_TRI_2_PORT 2 9274 #define rx_x4_status3_port_mode_DUAL_PORT 3 9275 #define rx_x4_status3_port_mode_SINGLE_PORT 4 9276 9277 /**************************************************************************** 9278 * Enums: rx_x4_status3_rev_letter_enum 9279 */ 9280 #define rx_x4_status3_rev_letter_enum_REV_A 0 9281 #define rx_x4_status3_rev_letter_enum_REV_B 1 9282 #define rx_x4_status3_rev_letter_enum_REV_C 2 9283 #define rx_x4_status3_rev_letter_enum_REV_D 3 9284 9285 /**************************************************************************** 9286 * Enums: rx_x4_status3_rev_number_enum 9287 */ 9288 #define rx_x4_status3_rev_number_enum_REV_0 0 9289 #define rx_x4_status3_rev_number_enum_REV_1 1 9290 #define rx_x4_status3_rev_number_enum_REV_2 2 9291 #define rx_x4_status3_rev_number_enum_REV_3 3 9292 #define rx_x4_status3_rev_number_enum_REV_4 4 9293 #define rx_x4_status3_rev_number_enum_REV_5 5 9294 #define rx_x4_status3_rev_number_enum_REV_6 6 9295 #define rx_x4_status3_rev_number_enum_REV_7 7 9296 9297 /**************************************************************************** 9298 * Enums: rx_x4_status3_bonding_enum 9299 */ 9300 #define rx_x4_status3_bonding_enum_WIRE_BOND 0 9301 #define rx_x4_status3_bonding_enum_FLIP_CHIP 1 9302 9303 /**************************************************************************** 9304 * Enums: rx_x4_status3_tech_process 9305 */ 9306 #define rx_x4_status3_tech_process_PROCESS_90NM 0 9307 #define rx_x4_status3_tech_process_PROCESS_65NM 1 9308 #define rx_x4_status3_tech_process_PROCESS_40NM 2 9309 #define rx_x4_status3_tech_process_PROCESS_28NM 3 9310 #define rx_x4_status3_tech_process_PROCESS_16NM 4 9311 9312 /**************************************************************************** 9313 * Enums: rx_x4_status3_model_num 9314 */ 9315 #define rx_x4_status3_model_num_SERDES_CL73 0 9316 #define rx_x4_status3_model_num_XGXS_16G 1 9317 #define rx_x4_status3_model_num_HYPERCORE 2 9318 #define rx_x4_status3_model_num_HYPERLITE 3 9319 #define rx_x4_status3_model_num_PCIE_G2_PIPE 4 9320 #define rx_x4_status3_model_num_SERDES_1p25GBd 5 9321 #define rx_x4_status3_model_num_SATA2 6 9322 #define rx_x4_status3_model_num_QSGMII 7 9323 #define rx_x4_status3_model_num_XGXS10G 8 9324 #define rx_x4_status3_model_num_WARPCORE 9 9325 #define rx_x4_status3_model_num_XFICORE 10 9326 #define rx_x4_status3_model_num_RXFI 11 9327 #define rx_x4_status3_model_num_WARPLITE 12 9328 #define rx_x4_status3_model_num_PENTACORE 13 9329 #define rx_x4_status3_model_num_ESM 14 9330 #define rx_x4_status3_model_num_QUAD_SGMII 15 9331 #define rx_x4_status3_model_num_WARPCORE_3 16 9332 #define rx_x4_status3_model_num_TSC 17 9333 #define rx_x4_status3_model_num_TSC4E 18 9334 #define rx_x4_status3_model_num_TSC12E 19 9335 #define rx_x4_status3_model_num_TSC4F 20 9336 #define rx_x4_status3_model_num_TSC4F_GEN2 21 9337 #define rx_x4_status3_model_num_XGXS_CL73_90NM 29 9338 #define rx_x4_status3_model_num_SERDES_CL73_90NM 30 9339 #define rx_x4_status3_model_num_WARPCORE3 32 9340 #define rx_x4_status3_model_num_WARPCORE4_TSC 33 9341 #define rx_x4_status3_model_num_RXAUI 34 9342 9343 /**************************************************************************** 9344 * Enums: rx_x4_status3_payload 9345 */ 9346 #define rx_x4_status3_payload_REPEAT_2_BYTES 0 9347 #define rx_x4_status3_payload_RAMPING 1 9348 #define rx_x4_status3_payload_CL48_CRPAT 2 9349 #define rx_x4_status3_payload_CL48_CJPAT 3 9350 #define rx_x4_status3_payload_CL36_LONG_CRPAT 4 9351 #define rx_x4_status3_payload_CL36_SHORT_CRPAT 5 9352 9353 /**************************************************************************** 9354 * Enums: rx_x4_status3_sc 9355 */ 9356 #define rx_x4_status3_sc_S_10G_CR1 0 9357 #define rx_x4_status3_sc_S_10G_KR1 1 9358 #define rx_x4_status3_sc_S_10G_X1 2 9359 #define rx_x4_status3_sc_S_10G_HG2_CR1 4 9360 #define rx_x4_status3_sc_S_10G_HG2_KR1 5 9361 #define rx_x4_status3_sc_S_10G_HG2_X1 6 9362 #define rx_x4_status3_sc_S_20G_CR1 8 9363 #define rx_x4_status3_sc_S_20G_KR1 9 9364 #define rx_x4_status3_sc_S_20G_X1 10 9365 #define rx_x4_status3_sc_S_20G_HG2_CR1 12 9366 #define rx_x4_status3_sc_S_20G_HG2_KR1 13 9367 #define rx_x4_status3_sc_S_20G_HG2_X1 14 9368 #define rx_x4_status3_sc_S_25G_CR1 16 9369 #define rx_x4_status3_sc_S_25G_KR1 17 9370 #define rx_x4_status3_sc_S_25G_X1 18 9371 #define rx_x4_status3_sc_S_25G_HG2_CR1 20 9372 #define rx_x4_status3_sc_S_25G_HG2_KR1 21 9373 #define rx_x4_status3_sc_S_25G_HG2_X1 22 9374 #define rx_x4_status3_sc_S_20G_CR2 24 9375 #define rx_x4_status3_sc_S_20G_KR2 25 9376 #define rx_x4_status3_sc_S_20G_X2 26 9377 #define rx_x4_status3_sc_S_20G_HG2_CR2 28 9378 #define rx_x4_status3_sc_S_20G_HG2_KR2 29 9379 #define rx_x4_status3_sc_S_20G_HG2_X2 30 9380 #define rx_x4_status3_sc_S_40G_CR2 32 9381 #define rx_x4_status3_sc_S_40G_KR2 33 9382 #define rx_x4_status3_sc_S_40G_X2 34 9383 #define rx_x4_status3_sc_S_40G_HG2_CR2 36 9384 #define rx_x4_status3_sc_S_40G_HG2_KR2 37 9385 #define rx_x4_status3_sc_S_40G_HG2_X2 38 9386 #define rx_x4_status3_sc_S_40G_CR4 40 9387 #define rx_x4_status3_sc_S_40G_KR4 41 9388 #define rx_x4_status3_sc_S_40G_X4 42 9389 #define rx_x4_status3_sc_S_40G_HG2_CR4 44 9390 #define rx_x4_status3_sc_S_40G_HG2_KR4 45 9391 #define rx_x4_status3_sc_S_40G_HG2_X4 46 9392 #define rx_x4_status3_sc_S_50G_CR2 48 9393 #define rx_x4_status3_sc_S_50G_KR2 49 9394 #define rx_x4_status3_sc_S_50G_X2 50 9395 #define rx_x4_status3_sc_S_50G_HG2_CR2 52 9396 #define rx_x4_status3_sc_S_50G_HG2_KR2 53 9397 #define rx_x4_status3_sc_S_50G_HG2_X2 54 9398 #define rx_x4_status3_sc_S_50G_CR4 56 9399 #define rx_x4_status3_sc_S_50G_KR4 57 9400 #define rx_x4_status3_sc_S_50G_X4 58 9401 #define rx_x4_status3_sc_S_50G_HG2_CR4 60 9402 #define rx_x4_status3_sc_S_50G_HG2_KR4 61 9403 #define rx_x4_status3_sc_S_50G_HG2_X4 62 9404 #define rx_x4_status3_sc_S_100G_CR4 64 9405 #define rx_x4_status3_sc_S_100G_KR4 65 9406 #define rx_x4_status3_sc_S_100G_X4 66 9407 #define rx_x4_status3_sc_S_100G_HG2_CR4 68 9408 #define rx_x4_status3_sc_S_100G_HG2_KR4 69 9409 #define rx_x4_status3_sc_S_100G_HG2_X4 70 9410 #define rx_x4_status3_sc_S_CL73_20GVCO 72 9411 #define rx_x4_status3_sc_S_CL73_25GVCO 80 9412 #define rx_x4_status3_sc_S_CL36_20GVCO 88 9413 #define rx_x4_status3_sc_S_CL36_25GVCO 96 9414 #define rx_x4_status3_sc_S_25G_CR_IEEE 112 9415 #define rx_x4_status3_sc_S_25G_CRS_IEEE 113 9416 #define rx_x4_status3_sc_S_25G_KR_IEEE 114 9417 #define rx_x4_status3_sc_S_25G_KRS_IEEE 115 9418 9419 /**************************************************************************** 9420 * Enums: rx_x4_status3_t_fifo_modes 9421 */ 9422 #define rx_x4_status3_t_fifo_modes_T_FIFO_INSERT_NO_AM 0 9423 #define rx_x4_status3_t_fifo_modes_T_FIFO_INSERT_4_AM 1 9424 #define rx_x4_status3_t_fifo_modes_T_FIFO_INSERT_20_AM 2 9425 #define rx_x4_status3_t_fifo_modes_T_FIFO_INSERT_2_AM 3 9426 9427 /**************************************************************************** 9428 * Enums: rx_x4_status3_t_enc_modes 9429 */ 9430 #define rx_x4_status3_t_enc_modes_T_ENC_MODE_BYPASS 0 9431 #define rx_x4_status3_t_enc_modes_T_ENC_MODE_CL49 1 9432 #define rx_x4_status3_t_enc_modes_T_ENC_MODE_CL82 2 9433 9434 /**************************************************************************** 9435 * Enums: rx_x4_status3_btmx_mode 9436 */ 9437 #define rx_x4_status3_btmx_mode_BS_BTMX_MODE_1to1 0 9438 #define rx_x4_status3_btmx_mode_BS_BTMX_MODE_2to1 1 9439 #define rx_x4_status3_btmx_mode_BS_BTMX_MODE_5to1 2 9440 9441 /**************************************************************************** 9442 * Enums: rx_x4_status3_t_type_cl82 9443 */ 9444 #define rx_x4_status3_t_type_cl82_T_TYPE_B1 5 9445 #define rx_x4_status3_t_type_cl82_T_TYPE_C 4 9446 #define rx_x4_status3_t_type_cl82_T_TYPE_S 3 9447 #define rx_x4_status3_t_type_cl82_T_TYPE_T 2 9448 #define rx_x4_status3_t_type_cl82_T_TYPE_D 1 9449 #define rx_x4_status3_t_type_cl82_T_TYPE_E 0 9450 9451 /**************************************************************************** 9452 * Enums: rx_x4_status3_txsm_state_cl82 9453 */ 9454 #define rx_x4_status3_txsm_state_cl82_TX_HIG_END 6 9455 #define rx_x4_status3_txsm_state_cl82_TX_HIG_START 5 9456 #define rx_x4_status3_txsm_state_cl82_TX_E 4 9457 #define rx_x4_status3_txsm_state_cl82_TX_T 3 9458 #define rx_x4_status3_txsm_state_cl82_TX_D 2 9459 #define rx_x4_status3_txsm_state_cl82_TX_C 1 9460 #define rx_x4_status3_txsm_state_cl82_TX_INIT 0 9461 9462 /**************************************************************************** 9463 * Enums: rx_x4_status3_ltxsm_state_cl82 9464 */ 9465 #define rx_x4_status3_ltxsm_state_cl82_TX_HIG_END 64 9466 #define rx_x4_status3_ltxsm_state_cl82_TX_HIG_START 32 9467 #define rx_x4_status3_ltxsm_state_cl82_TX_E 16 9468 #define rx_x4_status3_ltxsm_state_cl82_TX_T 8 9469 #define rx_x4_status3_ltxsm_state_cl82_TX_D 4 9470 #define rx_x4_status3_ltxsm_state_cl82_TX_C 2 9471 #define rx_x4_status3_ltxsm_state_cl82_TX_INIT 1 9472 9473 /**************************************************************************** 9474 * Enums: rx_x4_status3_r_type_coded_cl82 9475 */ 9476 #define rx_x4_status3_r_type_coded_cl82_R_TYPE_B1 32 9477 #define rx_x4_status3_r_type_coded_cl82_R_TYPE_C 16 9478 #define rx_x4_status3_r_type_coded_cl82_R_TYPE_S 8 9479 #define rx_x4_status3_r_type_coded_cl82_R_TYPE_T 4 9480 #define rx_x4_status3_r_type_coded_cl82_R_TYPE_D 2 9481 #define rx_x4_status3_r_type_coded_cl82_R_TYPE_E 1 9482 9483 /**************************************************************************** 9484 * Enums: rx_x4_status3_rxsm_state_cl82 9485 */ 9486 #define rx_x4_status3_rxsm_state_cl82_RX_HIG_END 64 9487 #define rx_x4_status3_rxsm_state_cl82_RX_HIG_START 32 9488 #define rx_x4_status3_rxsm_state_cl82_RX_E 16 9489 #define rx_x4_status3_rxsm_state_cl82_RX_T 8 9490 #define rx_x4_status3_rxsm_state_cl82_RX_D 4 9491 #define rx_x4_status3_rxsm_state_cl82_RX_C 2 9492 #define rx_x4_status3_rxsm_state_cl82_RX_INIT 1 9493 9494 /**************************************************************************** 9495 * Enums: rx_x4_status3_deskew_state 9496 */ 9497 #define rx_x4_status3_deskew_state_ALIGN_ACQUIRED 2 9498 #define rx_x4_status3_deskew_state_LOSS_OF_ALIGNMENT 1 9499 9500 /**************************************************************************** 9501 * Enums: rx_x4_status3_os_mode_enum 9502 */ 9503 #define rx_x4_status3_os_mode_enum_OS_MODE_1 0 9504 #define rx_x4_status3_os_mode_enum_OS_MODE_2 1 9505 #define rx_x4_status3_os_mode_enum_OS_MODE_4 2 9506 #define rx_x4_status3_os_mode_enum_OS_MODE_16p5 8 9507 #define rx_x4_status3_os_mode_enum_OS_MODE_20p625 12 9508 9509 /**************************************************************************** 9510 * Enums: rx_x4_status3_scr_modes 9511 */ 9512 #define rx_x4_status3_scr_modes_T_SCR_MODE_BYPASS 0 9513 #define rx_x4_status3_scr_modes_T_SCR_MODE_CL49 1 9514 #define rx_x4_status3_scr_modes_T_SCR_MODE_40G_2_LANE 2 9515 #define rx_x4_status3_scr_modes_T_SCR_MODE_100G 3 9516 #define rx_x4_status3_scr_modes_T_SCR_MODE_20G 4 9517 #define rx_x4_status3_scr_modes_T_SCR_MODE_40G_4_LANE 5 9518 9519 /**************************************************************************** 9520 * Enums: rx_x4_status3_descr_modes 9521 */ 9522 #define rx_x4_status3_descr_modes_R_DESCR_MODE_BYPASS 0 9523 #define rx_x4_status3_descr_modes_R_DESCR_MODE_CL49 1 9524 #define rx_x4_status3_descr_modes_R_DESCR_MODE_CL82 2 9525 9526 /**************************************************************************** 9527 * Enums: rx_x4_status3_r_dec_tl_mode 9528 */ 9529 #define rx_x4_status3_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 9530 #define rx_x4_status3_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 9531 #define rx_x4_status3_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 9532 9533 /**************************************************************************** 9534 * Enums: rx_x4_status3_r_dec_fsm_mode 9535 */ 9536 #define rx_x4_status3_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 9537 #define rx_x4_status3_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 9538 #define rx_x4_status3_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 9539 9540 /**************************************************************************** 9541 * Enums: rx_x4_status3_r_deskew_mode 9542 */ 9543 #define rx_x4_status3_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 9544 #define rx_x4_status3_r_deskew_mode_R_DESKEW_MODE_20G 1 9545 #define rx_x4_status3_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 9546 #define rx_x4_status3_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 9547 #define rx_x4_status3_r_deskew_mode_R_DESKEW_MODE_100G 4 9548 #define rx_x4_status3_r_deskew_mode_R_DESKEW_MODE_CL49 5 9549 #define rx_x4_status3_r_deskew_mode_R_DESKEW_MODE_CL91_QUAD 6 9550 #define rx_x4_status3_r_deskew_mode_R_DESKEW_MODE_CL91_SINGLE_BRCM 7 9551 #define rx_x4_status3_r_deskew_mode_R_DESKEW_MODE_CL91_DUAL_BRCM 8 9552 #define rx_x4_status3_r_deskew_mode_R_DESKEW_MODE_CL91_FC 9 9553 9554 /**************************************************************************** 9555 * Enums: rx_x4_status3_bs_dist_modes 9556 */ 9557 #define rx_x4_status3_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 9558 #define rx_x4_status3_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 9559 #define rx_x4_status3_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 9560 #define rx_x4_status3_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 9561 9562 /**************************************************************************** 9563 * Enums: rx_x4_status3_cl49_t_type 9564 */ 9565 #define rx_x4_status3_cl49_t_type_BAD_T_TYPE 15 9566 #define rx_x4_status3_cl49_t_type_T_TYPE_B0 11 9567 #define rx_x4_status3_cl49_t_type_T_TYPE_OB 10 9568 #define rx_x4_status3_cl49_t_type_T_TYPE_B1 9 9569 #define rx_x4_status3_cl49_t_type_T_TYPE_DB 8 9570 #define rx_x4_status3_cl49_t_type_T_TYPE_FC 7 9571 #define rx_x4_status3_cl49_t_type_T_TYPE_TB 6 9572 #define rx_x4_status3_cl49_t_type_T_TYPE_LI 5 9573 #define rx_x4_status3_cl49_t_type_T_TYPE_C 4 9574 #define rx_x4_status3_cl49_t_type_T_TYPE_S 3 9575 #define rx_x4_status3_cl49_t_type_T_TYPE_T 2 9576 #define rx_x4_status3_cl49_t_type_T_TYPE_D 1 9577 #define rx_x4_status3_cl49_t_type_T_TYPE_E 0 9578 9579 /**************************************************************************** 9580 * Enums: rx_x4_status3_cl49_txsm_states 9581 */ 9582 #define rx_x4_status3_cl49_txsm_states_TX_HIG_END 7 9583 #define rx_x4_status3_cl49_txsm_states_TX_HIG_START 6 9584 #define rx_x4_status3_cl49_txsm_states_TX_LI 5 9585 #define rx_x4_status3_cl49_txsm_states_TX_E 4 9586 #define rx_x4_status3_cl49_txsm_states_TX_T 3 9587 #define rx_x4_status3_cl49_txsm_states_TX_D 2 9588 #define rx_x4_status3_cl49_txsm_states_TX_C 1 9589 #define rx_x4_status3_cl49_txsm_states_TX_INIT 0 9590 9591 /**************************************************************************** 9592 * Enums: rx_x4_status3_cl49_ltxsm_states 9593 */ 9594 #define rx_x4_status3_cl49_ltxsm_states_TX_HIG_END 128 9595 #define rx_x4_status3_cl49_ltxsm_states_TX_HIG_START 64 9596 #define rx_x4_status3_cl49_ltxsm_states_TX_LI 32 9597 #define rx_x4_status3_cl49_ltxsm_states_TX_E 16 9598 #define rx_x4_status3_cl49_ltxsm_states_TX_T 8 9599 #define rx_x4_status3_cl49_ltxsm_states_TX_D 4 9600 #define rx_x4_status3_cl49_ltxsm_states_TX_C 2 9601 #define rx_x4_status3_cl49_ltxsm_states_TX_INIT 1 9602 9603 /**************************************************************************** 9604 * Enums: rx_x4_status3_burst_error_mode 9605 */ 9606 #define rx_x4_status3_burst_error_mode_BURST_ERROR_11_BITS 0 9607 #define rx_x4_status3_burst_error_mode_BURST_ERROR_16_BITS 1 9608 #define rx_x4_status3_burst_error_mode_BURST_ERROR_17_BITS 2 9609 #define rx_x4_status3_burst_error_mode_BURST_ERROR_18_BITS 3 9610 #define rx_x4_status3_burst_error_mode_BURST_ERROR_19_BITS 4 9611 #define rx_x4_status3_burst_error_mode_BURST_ERROR_20_BITS 5 9612 #define rx_x4_status3_burst_error_mode_BURST_ERROR_21_BITS 6 9613 #define rx_x4_status3_burst_error_mode_BURST_ERROR_22_BITS 7 9614 #define rx_x4_status3_burst_error_mode_BURST_ERROR_23_BITS 8 9615 #define rx_x4_status3_burst_error_mode_BURST_ERROR_24_BITS 9 9616 #define rx_x4_status3_burst_error_mode_BURST_ERROR_25_BITS 10 9617 #define rx_x4_status3_burst_error_mode_BURST_ERROR_26_BITS 11 9618 #define rx_x4_status3_burst_error_mode_BURST_ERROR_27_BITS 12 9619 #define rx_x4_status3_burst_error_mode_BURST_ERROR_28_BITS 13 9620 #define rx_x4_status3_burst_error_mode_BURST_ERROR_29_BITS 14 9621 #define rx_x4_status3_burst_error_mode_BURST_ERROR_30_BITS 15 9622 #define rx_x4_status3_burst_error_mode_BURST_ERROR_31_BITS 16 9623 #define rx_x4_status3_burst_error_mode_BURST_ERROR_32_BITS 17 9624 #define rx_x4_status3_burst_error_mode_BURST_ERROR_33_BITS 18 9625 #define rx_x4_status3_burst_error_mode_BURST_ERROR_34_BITS 19 9626 #define rx_x4_status3_burst_error_mode_BURST_ERROR_35_BITS 20 9627 #define rx_x4_status3_burst_error_mode_BURST_ERROR_36_BITS 21 9628 #define rx_x4_status3_burst_error_mode_BURST_ERROR_37_BITS 22 9629 #define rx_x4_status3_burst_error_mode_BURST_ERROR_38_BITS 23 9630 #define rx_x4_status3_burst_error_mode_BURST_ERROR_39_BITS 24 9631 #define rx_x4_status3_burst_error_mode_BURST_ERROR_40_BITS 25 9632 #define rx_x4_status3_burst_error_mode_BURST_ERROR_41_BITS 26 9633 9634 /**************************************************************************** 9635 * Enums: rx_x4_status3_bermon_state 9636 */ 9637 #define rx_x4_status3_bermon_state_HI_BER 4 9638 #define rx_x4_status3_bermon_state_GOOD_BER 3 9639 #define rx_x4_status3_bermon_state_BER_TEST_SH 2 9640 #define rx_x4_status3_bermon_state_START_TIMER 1 9641 #define rx_x4_status3_bermon_state_BER_MT_INIT 0 9642 9643 /**************************************************************************** 9644 * Enums: rx_x4_status3_rxsm_state_cl49 9645 */ 9646 #define rx_x4_status3_rxsm_state_cl49_RX_HIG_END 128 9647 #define rx_x4_status3_rxsm_state_cl49_RX_HIG_START 64 9648 #define rx_x4_status3_rxsm_state_cl49_RX_LI 32 9649 #define rx_x4_status3_rxsm_state_cl49_RX_E 16 9650 #define rx_x4_status3_rxsm_state_cl49_RX_T 8 9651 #define rx_x4_status3_rxsm_state_cl49_RX_D 4 9652 #define rx_x4_status3_rxsm_state_cl49_RX_C 2 9653 #define rx_x4_status3_rxsm_state_cl49_RX_INIT 1 9654 9655 /**************************************************************************** 9656 * Enums: rx_x4_status3_r_type 9657 */ 9658 #define rx_x4_status3_r_type_BAD_R_TYPE 15 9659 #define rx_x4_status3_r_type_R_TYPE_B0 11 9660 #define rx_x4_status3_r_type_R_TYPE_OB 10 9661 #define rx_x4_status3_r_type_R_TYPE_B1 9 9662 #define rx_x4_status3_r_type_R_TYPE_DB 8 9663 #define rx_x4_status3_r_type_R_TYPE_FC 7 9664 #define rx_x4_status3_r_type_R_TYPE_TB 6 9665 #define rx_x4_status3_r_type_R_TYPE_LI 5 9666 #define rx_x4_status3_r_type_R_TYPE_C 4 9667 #define rx_x4_status3_r_type_R_TYPE_S 3 9668 #define rx_x4_status3_r_type_R_TYPE_T 2 9669 #define rx_x4_status3_r_type_R_TYPE_D 1 9670 #define rx_x4_status3_r_type_R_TYPE_E 0 9671 9672 /**************************************************************************** 9673 * Enums: rx_x4_status3_am_lock_state 9674 */ 9675 #define rx_x4_status3_am_lock_state_INVALID_AM 512 9676 #define rx_x4_status3_am_lock_state_GOOD_AM 256 9677 #define rx_x4_status3_am_lock_state_COMP_AM 128 9678 #define rx_x4_status3_am_lock_state_TIMER_2 64 9679 #define rx_x4_status3_am_lock_state_AM_2_GOOD 32 9680 #define rx_x4_status3_am_lock_state_COMP_2ND 16 9681 #define rx_x4_status3_am_lock_state_TIMER_1 8 9682 #define rx_x4_status3_am_lock_state_FIND_1ST 4 9683 #define rx_x4_status3_am_lock_state_AM_RESET_CNT 2 9684 #define rx_x4_status3_am_lock_state_AM_LOCK_INIT 1 9685 9686 /**************************************************************************** 9687 * Enums: rx_x4_status3_msg_selector 9688 */ 9689 #define rx_x4_status3_msg_selector_RESERVED 0 9690 #define rx_x4_status3_msg_selector_VALUE_802p3 1 9691 #define rx_x4_status3_msg_selector_VALUE_802p9 2 9692 #define rx_x4_status3_msg_selector_VALUE_802p5 3 9693 #define rx_x4_status3_msg_selector_VALUE_1394 4 9694 9695 /**************************************************************************** 9696 * Enums: rx_x4_status3_synce_enum 9697 */ 9698 #define rx_x4_status3_synce_enum_SYNCE_NO_DIV 0 9699 #define rx_x4_status3_synce_enum_SYNCE_DIV_7 1 9700 #define rx_x4_status3_synce_enum_SYNCE_DIV_11 2 9701 9702 /**************************************************************************** 9703 * Enums: rx_x4_status3_synce_enum_stage0 9704 */ 9705 #define rx_x4_status3_synce_enum_stage0_SYNCE_NO_DIV 0 9706 #define rx_x4_status3_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 9707 #define rx_x4_status3_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 9708 9709 /**************************************************************************** 9710 * Enums: rx_x4_status3_cl91_sync_state 9711 */ 9712 #define rx_x4_status3_cl91_sync_state_FIND_1ST 0 9713 #define rx_x4_status3_cl91_sync_state_COUNT_NEXT 1 9714 #define rx_x4_status3_cl91_sync_state_COMP_2ND 2 9715 #define rx_x4_status3_cl91_sync_state_TWO_GOOD 3 9716 9717 /**************************************************************************** 9718 * Enums: rx_x4_status3_cl91_algn_state 9719 */ 9720 #define rx_x4_status3_cl91_algn_state_LOSS_OF_ALIGNMENT 0 9721 #define rx_x4_status3_cl91_algn_state_DESKEW 1 9722 #define rx_x4_status3_cl91_algn_state_DESKEW_FAIL 2 9723 #define rx_x4_status3_cl91_algn_state_ALIGN_ACQUIRED 3 9724 #define rx_x4_status3_cl91_algn_state_CW_GOOD 4 9725 #define rx_x4_status3_cl91_algn_state_CW_BAD 5 9726 #define rx_x4_status3_cl91_algn_state_THREE_BAD 6 9727 9728 /**************************************************************************** 9729 * Enums: rx_x4_status3_fec_sel_override 9730 */ 9731 #define rx_x4_status3_fec_sel_override_NO_OVERRIDE 0 9732 #define rx_x4_status3_fec_sel_override_NO_FEC 1 9733 #define rx_x4_status3_fec_sel_override_FEC_CL74 2 9734 #define rx_x4_status3_fec_sel_override_FEC_CL91 3 9735 9736 /**************************************************************************** 9737 * Enums: rx_x4_status3_cl91_blksync_mode 9738 */ 9739 #define rx_x4_status3_cl91_blksync_mode_R_BLKSYNC_NO_CL91_FEC 0 9740 #define rx_x4_status3_cl91_blksync_mode_R_BLKSYNC_CL91_QUAD_LANE_FEC 1 9741 #define rx_x4_status3_cl91_blksync_mode_R_BLKSYNC_CL91_DUAL_LANE_FEC 2 9742 #define rx_x4_status3_cl91_blksync_mode_R_BLKSYNC_CL91_SINGLE_LANE_FEC 3 9743 #define rx_x4_status3_cl91_blksync_mode_R_BLKSYNC_CL91_FC_FEC 4 9744 9745 /**************************************************************************** 9746 * Enums: rx_x4_status3_r_merge_mode 9747 */ 9748 #define rx_x4_status3_r_merge_mode_R_MERGE_MODE_BYPASS 0 9749 #define rx_x4_status3_r_merge_mode_R_MERGE_MODE_CL91_FC 1 9750 #define rx_x4_status3_r_merge_mode_R_MERGE_MODE_CL91_SINGLE_LANE 2 9751 #define rx_x4_status3_r_merge_mode_R_MERGE_MODE_CL91_DUAL_LANE 3 9752 #define rx_x4_status3_r_merge_mode_R_MERGE_MODE_CL91_QUAD_LANE 4 9753 9754 /**************************************************************************** 9755 * Enums: rx_x4_status3_r_tc_mode 9756 */ 9757 #define rx_x4_status3_r_tc_mode_R_TC_MODE_SINGLE 0 9758 #define rx_x4_status3_r_tc_mode_R_TC_MODE_DUAL 1 9759 #define rx_x4_status3_r_tc_mode_R_TC_MODE_QUAD 2 9760 9761 /**************************************************************************** 9762 * Enums: rx_x4_status3_r_tc_out_mode 9763 */ 9764 #define rx_x4_status3_r_tc_out_mode_R_TC_OUT_MODE_SINGLE 0 9765 #define rx_x4_status3_r_tc_out_mode_R_TC_OUT_MODE_DUAL 1 9766 #define rx_x4_status3_r_tc_out_mode_R_TC_OUT_MODE_QUAD 2 9767 9768 /**************************************************************************** 9769 * Enums: rx_x4_status3_cl91_fec_mode 9770 */ 9771 #define rx_x4_status3_cl91_fec_mode_NO_CL91_FEC 0 9772 #define rx_x4_status3_cl91_fec_mode_CL91_SINGLE_LANE_FC 1 9773 #define rx_x4_status3_cl91_fec_mode_CL91_SINGLE_LANE_BRCM_PROP 2 9774 #define rx_x4_status3_cl91_fec_mode_CL91_DUAL_LANE_BRCM_PROP 3 9775 #define rx_x4_status3_cl91_fec_mode_CL91_QUAD_LANE 4 9776 #define rx_x4_status3_cl91_fec_mode_IEEE_25G_CL91_SINGLE_LANE 5 9777 9778 /**************************************************************************** 9779 * Enums: rx_x4_status3_am_spacing_mul 9780 */ 9781 #define rx_x4_status3_am_spacing_mul_AM_SPACING_MUL_2 0 9782 #define rx_x4_status3_am_spacing_mul_AM_SPACING_MUL_4 1 9783 #define rx_x4_status3_am_spacing_mul_AM_SPACING_MUL_5 2 9784 #define rx_x4_status3_am_spacing_mul_AM_SPACING_MUL_20 3 9785 9786 /**************************************************************************** 9787 * Enums: rx_x4_status4_cl36TxEEEStates_l 9788 */ 9789 #define rx_x4_status4_cl36TxEEEStates_l_TX_REFRESH 8 9790 #define rx_x4_status4_cl36TxEEEStates_l_TX_QUIET 4 9791 #define rx_x4_status4_cl36TxEEEStates_l_TX_SLEEP 2 9792 #define rx_x4_status4_cl36TxEEEStates_l_TX_ACTIVE 1 9793 9794 /**************************************************************************** 9795 * Enums: rx_x4_status4_cl36TxEEEStates_c 9796 */ 9797 #define rx_x4_status4_cl36TxEEEStates_c_TX_REFRESH 3 9798 #define rx_x4_status4_cl36TxEEEStates_c_TX_QUIET 2 9799 #define rx_x4_status4_cl36TxEEEStates_c_TX_SLEEP 1 9800 #define rx_x4_status4_cl36TxEEEStates_c_TX_ACTIVE 0 9801 9802 /**************************************************************************** 9803 * Enums: rx_x4_status4_cl49TxEEEStates_l 9804 */ 9805 #define rx_x4_status4_cl49TxEEEStates_l_SCR_RESET_2 64 9806 #define rx_x4_status4_cl49TxEEEStates_l_SCR_RESET_1 32 9807 #define rx_x4_status4_cl49TxEEEStates_l_TX_WAKE 16 9808 #define rx_x4_status4_cl49TxEEEStates_l_TX_REFRESH 8 9809 #define rx_x4_status4_cl49TxEEEStates_l_TX_QUIET 4 9810 #define rx_x4_status4_cl49TxEEEStates_l_TX_SLEEP 2 9811 #define rx_x4_status4_cl49TxEEEStates_l_TX_ACTIVE 1 9812 9813 /**************************************************************************** 9814 * Enums: rx_x4_status4_fec_req_enum 9815 */ 9816 #define rx_x4_status4_fec_req_enum_FEC_not_supported 0 9817 #define rx_x4_status4_fec_req_enum_FEC_supported_but_not_requested 1 9818 #define rx_x4_status4_fec_req_enum_invalid_setting 2 9819 #define rx_x4_status4_fec_req_enum_FEC_supported_and_requested 3 9820 9821 /**************************************************************************** 9822 * Enums: rx_x4_status4_cl73_pause_enum 9823 */ 9824 #define rx_x4_status4_cl73_pause_enum_No_PAUSE_ability 0 9825 #define rx_x4_status4_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 9826 #define rx_x4_status4_cl73_pause_enum_Symmetric_PAUSE_ability 1 9827 #define rx_x4_status4_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 9828 9829 /**************************************************************************** 9830 * Enums: rx_x4_status4_cl49TxEEEStates_c 9831 */ 9832 #define rx_x4_status4_cl49TxEEEStates_c_SCR_RESET_2 6 9833 #define rx_x4_status4_cl49TxEEEStates_c_SCR_RESET_1 5 9834 #define rx_x4_status4_cl49TxEEEStates_c_TX_WAKE 4 9835 #define rx_x4_status4_cl49TxEEEStates_c_TX_REFRESH 3 9836 #define rx_x4_status4_cl49TxEEEStates_c_TX_QUIET 2 9837 #define rx_x4_status4_cl49TxEEEStates_c_TX_SLEEP 1 9838 #define rx_x4_status4_cl49TxEEEStates_c_TX_ACTIVE 0 9839 9840 /**************************************************************************** 9841 * Enums: rx_x4_status4_cl36RxEEEStates_l 9842 */ 9843 #define rx_x4_status4_cl36RxEEEStates_l_RX_LINK_FAIL 32 9844 #define rx_x4_status4_cl36RxEEEStates_l_RX_WTF 16 9845 #define rx_x4_status4_cl36RxEEEStates_l_RX_WAKE 8 9846 #define rx_x4_status4_cl36RxEEEStates_l_RX_QUIET 4 9847 #define rx_x4_status4_cl36RxEEEStates_l_RX_SLEEP 2 9848 #define rx_x4_status4_cl36RxEEEStates_l_RX_ACTIVE 1 9849 9850 /**************************************************************************** 9851 * Enums: rx_x4_status4_cl36RxEEEStates_c 9852 */ 9853 #define rx_x4_status4_cl36RxEEEStates_c_RX_LINK_FAIL 5 9854 #define rx_x4_status4_cl36RxEEEStates_c_RX_WTF 4 9855 #define rx_x4_status4_cl36RxEEEStates_c_RX_WAKE 3 9856 #define rx_x4_status4_cl36RxEEEStates_c_RX_QUIET 2 9857 #define rx_x4_status4_cl36RxEEEStates_c_RX_SLEEP 1 9858 #define rx_x4_status4_cl36RxEEEStates_c_RX_ACTIVE 0 9859 9860 /**************************************************************************** 9861 * Enums: rx_x4_status4_cl49RxEEEStates_l 9862 */ 9863 #define rx_x4_status4_cl49RxEEEStates_l_RX_LINK_FAIL 32 9864 #define rx_x4_status4_cl49RxEEEStates_l_RX_WTF 16 9865 #define rx_x4_status4_cl49RxEEEStates_l_RX_WAKE 8 9866 #define rx_x4_status4_cl49RxEEEStates_l_RX_QUIET 4 9867 #define rx_x4_status4_cl49RxEEEStates_l_RX_SLEEP 2 9868 #define rx_x4_status4_cl49RxEEEStates_l_RX_ACTIVE 1 9869 9870 /**************************************************************************** 9871 * Enums: rx_x4_status4_cl49RxEEEStates_c 9872 */ 9873 #define rx_x4_status4_cl49RxEEEStates_c_RX_LINK_FAIL 5 9874 #define rx_x4_status4_cl49RxEEEStates_c_RX_WTF 4 9875 #define rx_x4_status4_cl49RxEEEStates_c_RX_WAKE 3 9876 #define rx_x4_status4_cl49RxEEEStates_c_RX_QUIET 2 9877 #define rx_x4_status4_cl49RxEEEStates_c_RX_SLEEP 1 9878 #define rx_x4_status4_cl49RxEEEStates_c_RX_ACTIVE 0 9879 9880 /**************************************************************************** 9881 * Enums: rx_x4_status4_cl48TxEEEStates_l 9882 */ 9883 #define rx_x4_status4_cl48TxEEEStates_l_TX_REFRESH 8 9884 #define rx_x4_status4_cl48TxEEEStates_l_TX_QUIET 4 9885 #define rx_x4_status4_cl48TxEEEStates_l_TX_SLEEP 2 9886 #define rx_x4_status4_cl48TxEEEStates_l_TX_ACTIVE 1 9887 9888 /**************************************************************************** 9889 * Enums: rx_x4_status4_cl48TxEEEStates_c 9890 */ 9891 #define rx_x4_status4_cl48TxEEEStates_c_TX_REFRESH 3 9892 #define rx_x4_status4_cl48TxEEEStates_c_TX_QUIET 2 9893 #define rx_x4_status4_cl48TxEEEStates_c_TX_SLEEP 1 9894 #define rx_x4_status4_cl48TxEEEStates_c_TX_ACTIVE 0 9895 9896 /**************************************************************************** 9897 * Enums: rx_x4_status4_cl48RxEEEStates_l 9898 */ 9899 #define rx_x4_status4_cl48RxEEEStates_l_RX_LINK_FAIL 32 9900 #define rx_x4_status4_cl48RxEEEStates_l_RX_WAKE 16 9901 #define rx_x4_status4_cl48RxEEEStates_l_RX_QUIET 8 9902 #define rx_x4_status4_cl48RxEEEStates_l_RX_DEACT 4 9903 #define rx_x4_status4_cl48RxEEEStates_l_RX_SLEEP 2 9904 #define rx_x4_status4_cl48RxEEEStates_l_RX_ACTIVE 1 9905 9906 /**************************************************************************** 9907 * Enums: rx_x4_status4_cl48RxEEEStates_c 9908 */ 9909 #define rx_x4_status4_cl48RxEEEStates_c_RX_LINK_FAIL 5 9910 #define rx_x4_status4_cl48RxEEEStates_c_RX_WAKE 4 9911 #define rx_x4_status4_cl48RxEEEStates_c_RX_QUIET 3 9912 #define rx_x4_status4_cl48RxEEEStates_c_RX_DEACT 2 9913 #define rx_x4_status4_cl48RxEEEStates_c_RX_SLEEP 1 9914 #define rx_x4_status4_cl48RxEEEStates_c_RX_ACTIVE 0 9915 9916 /**************************************************************************** 9917 * Enums: rx_x4_status4_IQP_Options 9918 */ 9919 #define rx_x4_status4_IQP_Options_i50uA 0 9920 #define rx_x4_status4_IQP_Options_i100uA 1 9921 #define rx_x4_status4_IQP_Options_i150uA 2 9922 #define rx_x4_status4_IQP_Options_i200uA 3 9923 #define rx_x4_status4_IQP_Options_i250uA 4 9924 #define rx_x4_status4_IQP_Options_i300uA 5 9925 #define rx_x4_status4_IQP_Options_i350uA 6 9926 #define rx_x4_status4_IQP_Options_i400uA 7 9927 #define rx_x4_status4_IQP_Options_i450uA 8 9928 #define rx_x4_status4_IQP_Options_i500uA 9 9929 #define rx_x4_status4_IQP_Options_i550uA 10 9930 #define rx_x4_status4_IQP_Options_i600uA 11 9931 #define rx_x4_status4_IQP_Options_i650uA 12 9932 #define rx_x4_status4_IQP_Options_i700uA 13 9933 #define rx_x4_status4_IQP_Options_i750uA 14 9934 #define rx_x4_status4_IQP_Options_i800uA 15 9935 9936 /**************************************************************************** 9937 * Enums: rx_x4_status4_IDriver_Options 9938 */ 9939 #define rx_x4_status4_IDriver_Options_v680mV 0 9940 #define rx_x4_status4_IDriver_Options_v730mV 1 9941 #define rx_x4_status4_IDriver_Options_v780mV 2 9942 #define rx_x4_status4_IDriver_Options_v830mV 3 9943 #define rx_x4_status4_IDriver_Options_v880mV 4 9944 #define rx_x4_status4_IDriver_Options_v930mV 5 9945 #define rx_x4_status4_IDriver_Options_v980mV 6 9946 #define rx_x4_status4_IDriver_Options_v1010mV 7 9947 #define rx_x4_status4_IDriver_Options_v1040mV 8 9948 #define rx_x4_status4_IDriver_Options_v1060mV 9 9949 #define rx_x4_status4_IDriver_Options_v1070mV 10 9950 #define rx_x4_status4_IDriver_Options_v1080mV 11 9951 #define rx_x4_status4_IDriver_Options_v1085mV 12 9952 #define rx_x4_status4_IDriver_Options_v1090mV 13 9953 #define rx_x4_status4_IDriver_Options_v1095mV 14 9954 #define rx_x4_status4_IDriver_Options_v1100mV 15 9955 9956 /**************************************************************************** 9957 * Enums: rx_x4_status4_operationModes 9958 */ 9959 #define rx_x4_status4_operationModes_XGXS 0 9960 #define rx_x4_status4_operationModes_XGXG_nCC 1 9961 #define rx_x4_status4_operationModes_Indlane_OS8 4 9962 #define rx_x4_status4_operationModes_IndLane_OS5 5 9963 #define rx_x4_status4_operationModes_PCI 7 9964 #define rx_x4_status4_operationModes_XGXS_nLQ 8 9965 #define rx_x4_status4_operationModes_XGXS_nLQnCC 9 9966 #define rx_x4_status4_operationModes_PBypass 10 9967 #define rx_x4_status4_operationModes_PBypass_nDSK 11 9968 #define rx_x4_status4_operationModes_ComboCoreMode 12 9969 #define rx_x4_status4_operationModes_Clocks_off 15 9970 9971 /**************************************************************************** 9972 * Enums: rx_x4_status4_actualSpeeds 9973 */ 9974 #define rx_x4_status4_actualSpeeds_dr_10M 0 9975 #define rx_x4_status4_actualSpeeds_dr_100M 1 9976 #define rx_x4_status4_actualSpeeds_dr_1G 2 9977 #define rx_x4_status4_actualSpeeds_dr_2p5G 3 9978 #define rx_x4_status4_actualSpeeds_dr_5G_X4 4 9979 #define rx_x4_status4_actualSpeeds_dr_6G_X4 5 9980 #define rx_x4_status4_actualSpeeds_dr_10G_HiG 6 9981 #define rx_x4_status4_actualSpeeds_dr_10G_CX4 7 9982 #define rx_x4_status4_actualSpeeds_dr_12G_HiG 8 9983 #define rx_x4_status4_actualSpeeds_dr_12p5G_X4 9 9984 #define rx_x4_status4_actualSpeeds_dr_13G_X4 10 9985 #define rx_x4_status4_actualSpeeds_dr_15G_X4 11 9986 #define rx_x4_status4_actualSpeeds_dr_16G_X4 12 9987 #define rx_x4_status4_actualSpeeds_dr_1G_KX 13 9988 #define rx_x4_status4_actualSpeeds_dr_10G_KX4 14 9989 #define rx_x4_status4_actualSpeeds_dr_10G_KR 15 9990 #define rx_x4_status4_actualSpeeds_dr_5G 16 9991 #define rx_x4_status4_actualSpeeds_dr_6p4G 17 9992 #define rx_x4_status4_actualSpeeds_dr_20G_X4 18 9993 #define rx_x4_status4_actualSpeeds_dr_21G_X4 19 9994 #define rx_x4_status4_actualSpeeds_dr_25G_X4 20 9995 #define rx_x4_status4_actualSpeeds_dr_10G_HiG_DXGXS 21 9996 #define rx_x4_status4_actualSpeeds_dr_10G_DXGXS 22 9997 #define rx_x4_status4_actualSpeeds_dr_10p5G_HiG_DXGXS 23 9998 #define rx_x4_status4_actualSpeeds_dr_10p5G_DXGXS 24 9999 #define rx_x4_status4_actualSpeeds_dr_12p773G_HiG_DXGXS 25 10000 #define rx_x4_status4_actualSpeeds_dr_12p773G_DXGXS 26 10001 #define rx_x4_status4_actualSpeeds_dr_10G_XFI 27 10002 #define rx_x4_status4_actualSpeeds_dr_40G 28 10003 #define rx_x4_status4_actualSpeeds_dr_20G_HiG_DXGXS 29 10004 #define rx_x4_status4_actualSpeeds_dr_20G_DXGXS 30 10005 #define rx_x4_status4_actualSpeeds_dr_10G_SFI 31 10006 #define rx_x4_status4_actualSpeeds_dr_31p5G 32 10007 #define rx_x4_status4_actualSpeeds_dr_32p7G 33 10008 #define rx_x4_status4_actualSpeeds_dr_20G_SCR 34 10009 #define rx_x4_status4_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 10010 #define rx_x4_status4_actualSpeeds_dr_10G_DXGXS_SCR 36 10011 #define rx_x4_status4_actualSpeeds_dr_12G_R2 37 10012 #define rx_x4_status4_actualSpeeds_dr_10G_X2 38 10013 #define rx_x4_status4_actualSpeeds_dr_40G_KR4 39 10014 #define rx_x4_status4_actualSpeeds_dr_40G_CR4 40 10015 #define rx_x4_status4_actualSpeeds_dr_100G_CR10 41 10016 #define rx_x4_status4_actualSpeeds_dr_15p75G_DXGXS 44 10017 #define rx_x4_status4_actualSpeeds_dr_20G_KR2 57 10018 #define rx_x4_status4_actualSpeeds_dr_20G_CR2 58 10019 10020 /**************************************************************************** 10021 * Enums: rx_x4_status4_actualSpeedsMisc1 10022 */ 10023 #define rx_x4_status4_actualSpeedsMisc1_dr_2500BRCM_X1 16 10024 #define rx_x4_status4_actualSpeedsMisc1_dr_5000BRCM_X4 17 10025 #define rx_x4_status4_actualSpeedsMisc1_dr_6000BRCM_X4 18 10026 #define rx_x4_status4_actualSpeedsMisc1_dr_10GHiGig_X4 19 10027 #define rx_x4_status4_actualSpeedsMisc1_dr_10GBASE_CX4 20 10028 #define rx_x4_status4_actualSpeedsMisc1_dr_12GHiGig_X4 21 10029 #define rx_x4_status4_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 10030 #define rx_x4_status4_actualSpeedsMisc1_dr_13GHiGig_X4 23 10031 #define rx_x4_status4_actualSpeedsMisc1_dr_15GHiGig_X4 24 10032 #define rx_x4_status4_actualSpeedsMisc1_dr_16GHiGig_X4 25 10033 #define rx_x4_status4_actualSpeedsMisc1_dr_5000BRCM_X1 26 10034 #define rx_x4_status4_actualSpeedsMisc1_dr_6363BRCM_X1 27 10035 #define rx_x4_status4_actualSpeedsMisc1_dr_20GHiGig_X4 28 10036 #define rx_x4_status4_actualSpeedsMisc1_dr_21GHiGig_X4 29 10037 #define rx_x4_status4_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 10038 #define rx_x4_status4_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 10039 10040 /**************************************************************************** 10041 * Enums: rx_x4_status4_IndLaneModes 10042 */ 10043 #define rx_x4_status4_IndLaneModes_SWSDR_div2 0 10044 #define rx_x4_status4_IndLaneModes_SWSDR_div1 1 10045 #define rx_x4_status4_IndLaneModes_DWSDR_div2 2 10046 #define rx_x4_status4_IndLaneModes_DWSDR_div1 3 10047 10048 /**************************************************************************** 10049 * Enums: rx_x4_status4_prbsSelect 10050 */ 10051 #define rx_x4_status4_prbsSelect_prbs7 0 10052 #define rx_x4_status4_prbsSelect_prbs15 1 10053 #define rx_x4_status4_prbsSelect_prbs23 2 10054 #define rx_x4_status4_prbsSelect_prbs31 3 10055 10056 /**************************************************************************** 10057 * Enums: rx_x4_status4_vcoDivider 10058 */ 10059 #define rx_x4_status4_vcoDivider_div32 0 10060 #define rx_x4_status4_vcoDivider_div36 1 10061 #define rx_x4_status4_vcoDivider_div40 2 10062 #define rx_x4_status4_vcoDivider_div42 3 10063 #define rx_x4_status4_vcoDivider_div48 4 10064 #define rx_x4_status4_vcoDivider_div50 5 10065 #define rx_x4_status4_vcoDivider_div52 6 10066 #define rx_x4_status4_vcoDivider_div54 7 10067 #define rx_x4_status4_vcoDivider_div60 8 10068 #define rx_x4_status4_vcoDivider_div64 9 10069 #define rx_x4_status4_vcoDivider_div66 10 10070 #define rx_x4_status4_vcoDivider_div68 11 10071 #define rx_x4_status4_vcoDivider_div70 12 10072 #define rx_x4_status4_vcoDivider_div80 13 10073 #define rx_x4_status4_vcoDivider_div92 14 10074 #define rx_x4_status4_vcoDivider_div100 15 10075 10076 /**************************************************************************** 10077 * Enums: rx_x4_status4_refClkSelect 10078 */ 10079 #define rx_x4_status4_refClkSelect_clk_25MHz 0 10080 #define rx_x4_status4_refClkSelect_clk_100MHz 1 10081 #define rx_x4_status4_refClkSelect_clk_125MHz 2 10082 #define rx_x4_status4_refClkSelect_clk_156p25MHz 3 10083 #define rx_x4_status4_refClkSelect_clk_187p5MHz 4 10084 #define rx_x4_status4_refClkSelect_clk_161p25Mhz 5 10085 #define rx_x4_status4_refClkSelect_clk_50Mhz 6 10086 #define rx_x4_status4_refClkSelect_clk_106p25Mhz 7 10087 10088 /**************************************************************************** 10089 * Enums: rx_x4_status4_aerMMDdevTypeSelect 10090 */ 10091 #define rx_x4_status4_aerMMDdevTypeSelect_combo_core 0 10092 #define rx_x4_status4_aerMMDdevTypeSelect_PMA_PMD 1 10093 #define rx_x4_status4_aerMMDdevTypeSelect_PCS 3 10094 #define rx_x4_status4_aerMMDdevTypeSelect_PHY 4 10095 #define rx_x4_status4_aerMMDdevTypeSelect_DTE 5 10096 #define rx_x4_status4_aerMMDdevTypeSelect_CL73_AN 7 10097 10098 /**************************************************************************** 10099 * Enums: rx_x4_status4_aerMMDportSelect 10100 */ 10101 #define rx_x4_status4_aerMMDportSelect_ln0 0 10102 #define rx_x4_status4_aerMMDportSelect_ln1 1 10103 #define rx_x4_status4_aerMMDportSelect_ln2 2 10104 #define rx_x4_status4_aerMMDportSelect_ln3 3 10105 #define rx_x4_status4_aerMMDportSelect_BCST_ln0_1_2_3 511 10106 #define rx_x4_status4_aerMMDportSelect_BCST_ln0_1 512 10107 #define rx_x4_status4_aerMMDportSelect_BCST_ln2_3 513 10108 10109 /**************************************************************************** 10110 * Enums: rx_x4_status4_firmwareModeSelect 10111 */ 10112 #define rx_x4_status4_firmwareModeSelect_DEFAULT 0 10113 #define rx_x4_status4_firmwareModeSelect_SFP_OPT_LR 1 10114 #define rx_x4_status4_firmwareModeSelect_SFP_DAC 2 10115 #define rx_x4_status4_firmwareModeSelect_XLAUI 3 10116 #define rx_x4_status4_firmwareModeSelect_LONG_CH_6G 4 10117 10118 /**************************************************************************** 10119 * Enums: rx_x4_status4_tempIdxSelect 10120 */ 10121 #define rx_x4_status4_tempIdxSelect_LTE__22p9C 15 10122 #define rx_x4_status4_tempIdxSelect_LTE__12p6C 14 10123 #define rx_x4_status4_tempIdxSelect_LTE__3p0C 13 10124 #define rx_x4_status4_tempIdxSelect_LTE_6p7C 12 10125 #define rx_x4_status4_tempIdxSelect_LTE_16p4C 11 10126 #define rx_x4_status4_tempIdxSelect_LTE_26p6C 10 10127 #define rx_x4_status4_tempIdxSelect_LTE_36p3C 9 10128 #define rx_x4_status4_tempIdxSelect_LTE_46p0C 8 10129 #define rx_x4_status4_tempIdxSelect_LTE_56p2C 7 10130 #define rx_x4_status4_tempIdxSelect_LTE_65p9C 6 10131 #define rx_x4_status4_tempIdxSelect_LTE_75p6C 5 10132 #define rx_x4_status4_tempIdxSelect_LTE_85p3C 4 10133 #define rx_x4_status4_tempIdxSelect_LTE_95p5C 3 10134 #define rx_x4_status4_tempIdxSelect_LTE_105p2C 2 10135 #define rx_x4_status4_tempIdxSelect_LTE_114p9C 1 10136 #define rx_x4_status4_tempIdxSelect_LTE_125p1C 0 10137 10138 /**************************************************************************** 10139 * Enums: rx_x4_status4_port_mode 10140 */ 10141 #define rx_x4_status4_port_mode_QUAD_PORT 0 10142 #define rx_x4_status4_port_mode_TRI_1_PORT 1 10143 #define rx_x4_status4_port_mode_TRI_2_PORT 2 10144 #define rx_x4_status4_port_mode_DUAL_PORT 3 10145 #define rx_x4_status4_port_mode_SINGLE_PORT 4 10146 10147 /**************************************************************************** 10148 * Enums: rx_x4_status4_rev_letter_enum 10149 */ 10150 #define rx_x4_status4_rev_letter_enum_REV_A 0 10151 #define rx_x4_status4_rev_letter_enum_REV_B 1 10152 #define rx_x4_status4_rev_letter_enum_REV_C 2 10153 #define rx_x4_status4_rev_letter_enum_REV_D 3 10154 10155 /**************************************************************************** 10156 * Enums: rx_x4_status4_rev_number_enum 10157 */ 10158 #define rx_x4_status4_rev_number_enum_REV_0 0 10159 #define rx_x4_status4_rev_number_enum_REV_1 1 10160 #define rx_x4_status4_rev_number_enum_REV_2 2 10161 #define rx_x4_status4_rev_number_enum_REV_3 3 10162 #define rx_x4_status4_rev_number_enum_REV_4 4 10163 #define rx_x4_status4_rev_number_enum_REV_5 5 10164 #define rx_x4_status4_rev_number_enum_REV_6 6 10165 #define rx_x4_status4_rev_number_enum_REV_7 7 10166 10167 /**************************************************************************** 10168 * Enums: rx_x4_status4_bonding_enum 10169 */ 10170 #define rx_x4_status4_bonding_enum_WIRE_BOND 0 10171 #define rx_x4_status4_bonding_enum_FLIP_CHIP 1 10172 10173 /**************************************************************************** 10174 * Enums: rx_x4_status4_tech_process 10175 */ 10176 #define rx_x4_status4_tech_process_PROCESS_90NM 0 10177 #define rx_x4_status4_tech_process_PROCESS_65NM 1 10178 #define rx_x4_status4_tech_process_PROCESS_40NM 2 10179 #define rx_x4_status4_tech_process_PROCESS_28NM 3 10180 #define rx_x4_status4_tech_process_PROCESS_16NM 4 10181 10182 /**************************************************************************** 10183 * Enums: rx_x4_status4_model_num 10184 */ 10185 #define rx_x4_status4_model_num_SERDES_CL73 0 10186 #define rx_x4_status4_model_num_XGXS_16G 1 10187 #define rx_x4_status4_model_num_HYPERCORE 2 10188 #define rx_x4_status4_model_num_HYPERLITE 3 10189 #define rx_x4_status4_model_num_PCIE_G2_PIPE 4 10190 #define rx_x4_status4_model_num_SERDES_1p25GBd 5 10191 #define rx_x4_status4_model_num_SATA2 6 10192 #define rx_x4_status4_model_num_QSGMII 7 10193 #define rx_x4_status4_model_num_XGXS10G 8 10194 #define rx_x4_status4_model_num_WARPCORE 9 10195 #define rx_x4_status4_model_num_XFICORE 10 10196 #define rx_x4_status4_model_num_RXFI 11 10197 #define rx_x4_status4_model_num_WARPLITE 12 10198 #define rx_x4_status4_model_num_PENTACORE 13 10199 #define rx_x4_status4_model_num_ESM 14 10200 #define rx_x4_status4_model_num_QUAD_SGMII 15 10201 #define rx_x4_status4_model_num_WARPCORE_3 16 10202 #define rx_x4_status4_model_num_TSC 17 10203 #define rx_x4_status4_model_num_TSC4E 18 10204 #define rx_x4_status4_model_num_TSC12E 19 10205 #define rx_x4_status4_model_num_TSC4F 20 10206 #define rx_x4_status4_model_num_TSC4F_GEN2 21 10207 #define rx_x4_status4_model_num_XGXS_CL73_90NM 29 10208 #define rx_x4_status4_model_num_SERDES_CL73_90NM 30 10209 #define rx_x4_status4_model_num_WARPCORE3 32 10210 #define rx_x4_status4_model_num_WARPCORE4_TSC 33 10211 #define rx_x4_status4_model_num_RXAUI 34 10212 10213 /**************************************************************************** 10214 * Enums: rx_x4_status4_payload 10215 */ 10216 #define rx_x4_status4_payload_REPEAT_2_BYTES 0 10217 #define rx_x4_status4_payload_RAMPING 1 10218 #define rx_x4_status4_payload_CL48_CRPAT 2 10219 #define rx_x4_status4_payload_CL48_CJPAT 3 10220 #define rx_x4_status4_payload_CL36_LONG_CRPAT 4 10221 #define rx_x4_status4_payload_CL36_SHORT_CRPAT 5 10222 10223 /**************************************************************************** 10224 * Enums: rx_x4_status4_sc 10225 */ 10226 #define rx_x4_status4_sc_S_10G_CR1 0 10227 #define rx_x4_status4_sc_S_10G_KR1 1 10228 #define rx_x4_status4_sc_S_10G_X1 2 10229 #define rx_x4_status4_sc_S_10G_HG2_CR1 4 10230 #define rx_x4_status4_sc_S_10G_HG2_KR1 5 10231 #define rx_x4_status4_sc_S_10G_HG2_X1 6 10232 #define rx_x4_status4_sc_S_20G_CR1 8 10233 #define rx_x4_status4_sc_S_20G_KR1 9 10234 #define rx_x4_status4_sc_S_20G_X1 10 10235 #define rx_x4_status4_sc_S_20G_HG2_CR1 12 10236 #define rx_x4_status4_sc_S_20G_HG2_KR1 13 10237 #define rx_x4_status4_sc_S_20G_HG2_X1 14 10238 #define rx_x4_status4_sc_S_25G_CR1 16 10239 #define rx_x4_status4_sc_S_25G_KR1 17 10240 #define rx_x4_status4_sc_S_25G_X1 18 10241 #define rx_x4_status4_sc_S_25G_HG2_CR1 20 10242 #define rx_x4_status4_sc_S_25G_HG2_KR1 21 10243 #define rx_x4_status4_sc_S_25G_HG2_X1 22 10244 #define rx_x4_status4_sc_S_20G_CR2 24 10245 #define rx_x4_status4_sc_S_20G_KR2 25 10246 #define rx_x4_status4_sc_S_20G_X2 26 10247 #define rx_x4_status4_sc_S_20G_HG2_CR2 28 10248 #define rx_x4_status4_sc_S_20G_HG2_KR2 29 10249 #define rx_x4_status4_sc_S_20G_HG2_X2 30 10250 #define rx_x4_status4_sc_S_40G_CR2 32 10251 #define rx_x4_status4_sc_S_40G_KR2 33 10252 #define rx_x4_status4_sc_S_40G_X2 34 10253 #define rx_x4_status4_sc_S_40G_HG2_CR2 36 10254 #define rx_x4_status4_sc_S_40G_HG2_KR2 37 10255 #define rx_x4_status4_sc_S_40G_HG2_X2 38 10256 #define rx_x4_status4_sc_S_40G_CR4 40 10257 #define rx_x4_status4_sc_S_40G_KR4 41 10258 #define rx_x4_status4_sc_S_40G_X4 42 10259 #define rx_x4_status4_sc_S_40G_HG2_CR4 44 10260 #define rx_x4_status4_sc_S_40G_HG2_KR4 45 10261 #define rx_x4_status4_sc_S_40G_HG2_X4 46 10262 #define rx_x4_status4_sc_S_50G_CR2 48 10263 #define rx_x4_status4_sc_S_50G_KR2 49 10264 #define rx_x4_status4_sc_S_50G_X2 50 10265 #define rx_x4_status4_sc_S_50G_HG2_CR2 52 10266 #define rx_x4_status4_sc_S_50G_HG2_KR2 53 10267 #define rx_x4_status4_sc_S_50G_HG2_X2 54 10268 #define rx_x4_status4_sc_S_50G_CR4 56 10269 #define rx_x4_status4_sc_S_50G_KR4 57 10270 #define rx_x4_status4_sc_S_50G_X4 58 10271 #define rx_x4_status4_sc_S_50G_HG2_CR4 60 10272 #define rx_x4_status4_sc_S_50G_HG2_KR4 61 10273 #define rx_x4_status4_sc_S_50G_HG2_X4 62 10274 #define rx_x4_status4_sc_S_100G_CR4 64 10275 #define rx_x4_status4_sc_S_100G_KR4 65 10276 #define rx_x4_status4_sc_S_100G_X4 66 10277 #define rx_x4_status4_sc_S_100G_HG2_CR4 68 10278 #define rx_x4_status4_sc_S_100G_HG2_KR4 69 10279 #define rx_x4_status4_sc_S_100G_HG2_X4 70 10280 #define rx_x4_status4_sc_S_CL73_20GVCO 72 10281 #define rx_x4_status4_sc_S_CL73_25GVCO 80 10282 #define rx_x4_status4_sc_S_CL36_20GVCO 88 10283 #define rx_x4_status4_sc_S_CL36_25GVCO 96 10284 #define rx_x4_status4_sc_S_25G_CR_IEEE 112 10285 #define rx_x4_status4_sc_S_25G_CRS_IEEE 113 10286 #define rx_x4_status4_sc_S_25G_KR_IEEE 114 10287 #define rx_x4_status4_sc_S_25G_KRS_IEEE 115 10288 10289 /**************************************************************************** 10290 * Enums: rx_x4_status4_t_fifo_modes 10291 */ 10292 #define rx_x4_status4_t_fifo_modes_T_FIFO_INSERT_NO_AM 0 10293 #define rx_x4_status4_t_fifo_modes_T_FIFO_INSERT_4_AM 1 10294 #define rx_x4_status4_t_fifo_modes_T_FIFO_INSERT_20_AM 2 10295 #define rx_x4_status4_t_fifo_modes_T_FIFO_INSERT_2_AM 3 10296 10297 /**************************************************************************** 10298 * Enums: rx_x4_status4_t_enc_modes 10299 */ 10300 #define rx_x4_status4_t_enc_modes_T_ENC_MODE_BYPASS 0 10301 #define rx_x4_status4_t_enc_modes_T_ENC_MODE_CL49 1 10302 #define rx_x4_status4_t_enc_modes_T_ENC_MODE_CL82 2 10303 10304 /**************************************************************************** 10305 * Enums: rx_x4_status4_btmx_mode 10306 */ 10307 #define rx_x4_status4_btmx_mode_BS_BTMX_MODE_1to1 0 10308 #define rx_x4_status4_btmx_mode_BS_BTMX_MODE_2to1 1 10309 #define rx_x4_status4_btmx_mode_BS_BTMX_MODE_5to1 2 10310 10311 /**************************************************************************** 10312 * Enums: rx_x4_status4_t_type_cl82 10313 */ 10314 #define rx_x4_status4_t_type_cl82_T_TYPE_B1 5 10315 #define rx_x4_status4_t_type_cl82_T_TYPE_C 4 10316 #define rx_x4_status4_t_type_cl82_T_TYPE_S 3 10317 #define rx_x4_status4_t_type_cl82_T_TYPE_T 2 10318 #define rx_x4_status4_t_type_cl82_T_TYPE_D 1 10319 #define rx_x4_status4_t_type_cl82_T_TYPE_E 0 10320 10321 /**************************************************************************** 10322 * Enums: rx_x4_status4_txsm_state_cl82 10323 */ 10324 #define rx_x4_status4_txsm_state_cl82_TX_HIG_END 6 10325 #define rx_x4_status4_txsm_state_cl82_TX_HIG_START 5 10326 #define rx_x4_status4_txsm_state_cl82_TX_E 4 10327 #define rx_x4_status4_txsm_state_cl82_TX_T 3 10328 #define rx_x4_status4_txsm_state_cl82_TX_D 2 10329 #define rx_x4_status4_txsm_state_cl82_TX_C 1 10330 #define rx_x4_status4_txsm_state_cl82_TX_INIT 0 10331 10332 /**************************************************************************** 10333 * Enums: rx_x4_status4_ltxsm_state_cl82 10334 */ 10335 #define rx_x4_status4_ltxsm_state_cl82_TX_HIG_END 64 10336 #define rx_x4_status4_ltxsm_state_cl82_TX_HIG_START 32 10337 #define rx_x4_status4_ltxsm_state_cl82_TX_E 16 10338 #define rx_x4_status4_ltxsm_state_cl82_TX_T 8 10339 #define rx_x4_status4_ltxsm_state_cl82_TX_D 4 10340 #define rx_x4_status4_ltxsm_state_cl82_TX_C 2 10341 #define rx_x4_status4_ltxsm_state_cl82_TX_INIT 1 10342 10343 /**************************************************************************** 10344 * Enums: rx_x4_status4_r_type_coded_cl82 10345 */ 10346 #define rx_x4_status4_r_type_coded_cl82_R_TYPE_B1 32 10347 #define rx_x4_status4_r_type_coded_cl82_R_TYPE_C 16 10348 #define rx_x4_status4_r_type_coded_cl82_R_TYPE_S 8 10349 #define rx_x4_status4_r_type_coded_cl82_R_TYPE_T 4 10350 #define rx_x4_status4_r_type_coded_cl82_R_TYPE_D 2 10351 #define rx_x4_status4_r_type_coded_cl82_R_TYPE_E 1 10352 10353 /**************************************************************************** 10354 * Enums: rx_x4_status4_rxsm_state_cl82 10355 */ 10356 #define rx_x4_status4_rxsm_state_cl82_RX_HIG_END 64 10357 #define rx_x4_status4_rxsm_state_cl82_RX_HIG_START 32 10358 #define rx_x4_status4_rxsm_state_cl82_RX_E 16 10359 #define rx_x4_status4_rxsm_state_cl82_RX_T 8 10360 #define rx_x4_status4_rxsm_state_cl82_RX_D 4 10361 #define rx_x4_status4_rxsm_state_cl82_RX_C 2 10362 #define rx_x4_status4_rxsm_state_cl82_RX_INIT 1 10363 10364 /**************************************************************************** 10365 * Enums: rx_x4_status4_deskew_state 10366 */ 10367 #define rx_x4_status4_deskew_state_ALIGN_ACQUIRED 2 10368 #define rx_x4_status4_deskew_state_LOSS_OF_ALIGNMENT 1 10369 10370 /**************************************************************************** 10371 * Enums: rx_x4_status4_os_mode_enum 10372 */ 10373 #define rx_x4_status4_os_mode_enum_OS_MODE_1 0 10374 #define rx_x4_status4_os_mode_enum_OS_MODE_2 1 10375 #define rx_x4_status4_os_mode_enum_OS_MODE_4 2 10376 #define rx_x4_status4_os_mode_enum_OS_MODE_16p5 8 10377 #define rx_x4_status4_os_mode_enum_OS_MODE_20p625 12 10378 10379 /**************************************************************************** 10380 * Enums: rx_x4_status4_scr_modes 10381 */ 10382 #define rx_x4_status4_scr_modes_T_SCR_MODE_BYPASS 0 10383 #define rx_x4_status4_scr_modes_T_SCR_MODE_CL49 1 10384 #define rx_x4_status4_scr_modes_T_SCR_MODE_40G_2_LANE 2 10385 #define rx_x4_status4_scr_modes_T_SCR_MODE_100G 3 10386 #define rx_x4_status4_scr_modes_T_SCR_MODE_20G 4 10387 #define rx_x4_status4_scr_modes_T_SCR_MODE_40G_4_LANE 5 10388 10389 /**************************************************************************** 10390 * Enums: rx_x4_status4_descr_modes 10391 */ 10392 #define rx_x4_status4_descr_modes_R_DESCR_MODE_BYPASS 0 10393 #define rx_x4_status4_descr_modes_R_DESCR_MODE_CL49 1 10394 #define rx_x4_status4_descr_modes_R_DESCR_MODE_CL82 2 10395 10396 /**************************************************************************** 10397 * Enums: rx_x4_status4_r_dec_tl_mode 10398 */ 10399 #define rx_x4_status4_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 10400 #define rx_x4_status4_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 10401 #define rx_x4_status4_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 10402 10403 /**************************************************************************** 10404 * Enums: rx_x4_status4_r_dec_fsm_mode 10405 */ 10406 #define rx_x4_status4_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 10407 #define rx_x4_status4_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 10408 #define rx_x4_status4_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 10409 10410 /**************************************************************************** 10411 * Enums: rx_x4_status4_r_deskew_mode 10412 */ 10413 #define rx_x4_status4_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 10414 #define rx_x4_status4_r_deskew_mode_R_DESKEW_MODE_20G 1 10415 #define rx_x4_status4_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 10416 #define rx_x4_status4_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 10417 #define rx_x4_status4_r_deskew_mode_R_DESKEW_MODE_100G 4 10418 #define rx_x4_status4_r_deskew_mode_R_DESKEW_MODE_CL49 5 10419 #define rx_x4_status4_r_deskew_mode_R_DESKEW_MODE_CL91_QUAD 6 10420 #define rx_x4_status4_r_deskew_mode_R_DESKEW_MODE_CL91_SINGLE_BRCM 7 10421 #define rx_x4_status4_r_deskew_mode_R_DESKEW_MODE_CL91_DUAL_BRCM 8 10422 #define rx_x4_status4_r_deskew_mode_R_DESKEW_MODE_CL91_FC 9 10423 10424 /**************************************************************************** 10425 * Enums: rx_x4_status4_bs_dist_modes 10426 */ 10427 #define rx_x4_status4_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 10428 #define rx_x4_status4_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 10429 #define rx_x4_status4_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 10430 #define rx_x4_status4_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 10431 10432 /**************************************************************************** 10433 * Enums: rx_x4_status4_cl49_t_type 10434 */ 10435 #define rx_x4_status4_cl49_t_type_BAD_T_TYPE 15 10436 #define rx_x4_status4_cl49_t_type_T_TYPE_B0 11 10437 #define rx_x4_status4_cl49_t_type_T_TYPE_OB 10 10438 #define rx_x4_status4_cl49_t_type_T_TYPE_B1 9 10439 #define rx_x4_status4_cl49_t_type_T_TYPE_DB 8 10440 #define rx_x4_status4_cl49_t_type_T_TYPE_FC 7 10441 #define rx_x4_status4_cl49_t_type_T_TYPE_TB 6 10442 #define rx_x4_status4_cl49_t_type_T_TYPE_LI 5 10443 #define rx_x4_status4_cl49_t_type_T_TYPE_C 4 10444 #define rx_x4_status4_cl49_t_type_T_TYPE_S 3 10445 #define rx_x4_status4_cl49_t_type_T_TYPE_T 2 10446 #define rx_x4_status4_cl49_t_type_T_TYPE_D 1 10447 #define rx_x4_status4_cl49_t_type_T_TYPE_E 0 10448 10449 /**************************************************************************** 10450 * Enums: rx_x4_status4_cl49_txsm_states 10451 */ 10452 #define rx_x4_status4_cl49_txsm_states_TX_HIG_END 7 10453 #define rx_x4_status4_cl49_txsm_states_TX_HIG_START 6 10454 #define rx_x4_status4_cl49_txsm_states_TX_LI 5 10455 #define rx_x4_status4_cl49_txsm_states_TX_E 4 10456 #define rx_x4_status4_cl49_txsm_states_TX_T 3 10457 #define rx_x4_status4_cl49_txsm_states_TX_D 2 10458 #define rx_x4_status4_cl49_txsm_states_TX_C 1 10459 #define rx_x4_status4_cl49_txsm_states_TX_INIT 0 10460 10461 /**************************************************************************** 10462 * Enums: rx_x4_status4_cl49_ltxsm_states 10463 */ 10464 #define rx_x4_status4_cl49_ltxsm_states_TX_HIG_END 128 10465 #define rx_x4_status4_cl49_ltxsm_states_TX_HIG_START 64 10466 #define rx_x4_status4_cl49_ltxsm_states_TX_LI 32 10467 #define rx_x4_status4_cl49_ltxsm_states_TX_E 16 10468 #define rx_x4_status4_cl49_ltxsm_states_TX_T 8 10469 #define rx_x4_status4_cl49_ltxsm_states_TX_D 4 10470 #define rx_x4_status4_cl49_ltxsm_states_TX_C 2 10471 #define rx_x4_status4_cl49_ltxsm_states_TX_INIT 1 10472 10473 /**************************************************************************** 10474 * Enums: rx_x4_status4_burst_error_mode 10475 */ 10476 #define rx_x4_status4_burst_error_mode_BURST_ERROR_11_BITS 0 10477 #define rx_x4_status4_burst_error_mode_BURST_ERROR_16_BITS 1 10478 #define rx_x4_status4_burst_error_mode_BURST_ERROR_17_BITS 2 10479 #define rx_x4_status4_burst_error_mode_BURST_ERROR_18_BITS 3 10480 #define rx_x4_status4_burst_error_mode_BURST_ERROR_19_BITS 4 10481 #define rx_x4_status4_burst_error_mode_BURST_ERROR_20_BITS 5 10482 #define rx_x4_status4_burst_error_mode_BURST_ERROR_21_BITS 6 10483 #define rx_x4_status4_burst_error_mode_BURST_ERROR_22_BITS 7 10484 #define rx_x4_status4_burst_error_mode_BURST_ERROR_23_BITS 8 10485 #define rx_x4_status4_burst_error_mode_BURST_ERROR_24_BITS 9 10486 #define rx_x4_status4_burst_error_mode_BURST_ERROR_25_BITS 10 10487 #define rx_x4_status4_burst_error_mode_BURST_ERROR_26_BITS 11 10488 #define rx_x4_status4_burst_error_mode_BURST_ERROR_27_BITS 12 10489 #define rx_x4_status4_burst_error_mode_BURST_ERROR_28_BITS 13 10490 #define rx_x4_status4_burst_error_mode_BURST_ERROR_29_BITS 14 10491 #define rx_x4_status4_burst_error_mode_BURST_ERROR_30_BITS 15 10492 #define rx_x4_status4_burst_error_mode_BURST_ERROR_31_BITS 16 10493 #define rx_x4_status4_burst_error_mode_BURST_ERROR_32_BITS 17 10494 #define rx_x4_status4_burst_error_mode_BURST_ERROR_33_BITS 18 10495 #define rx_x4_status4_burst_error_mode_BURST_ERROR_34_BITS 19 10496 #define rx_x4_status4_burst_error_mode_BURST_ERROR_35_BITS 20 10497 #define rx_x4_status4_burst_error_mode_BURST_ERROR_36_BITS 21 10498 #define rx_x4_status4_burst_error_mode_BURST_ERROR_37_BITS 22 10499 #define rx_x4_status4_burst_error_mode_BURST_ERROR_38_BITS 23 10500 #define rx_x4_status4_burst_error_mode_BURST_ERROR_39_BITS 24 10501 #define rx_x4_status4_burst_error_mode_BURST_ERROR_40_BITS 25 10502 #define rx_x4_status4_burst_error_mode_BURST_ERROR_41_BITS 26 10503 10504 /**************************************************************************** 10505 * Enums: rx_x4_status4_bermon_state 10506 */ 10507 #define rx_x4_status4_bermon_state_HI_BER 4 10508 #define rx_x4_status4_bermon_state_GOOD_BER 3 10509 #define rx_x4_status4_bermon_state_BER_TEST_SH 2 10510 #define rx_x4_status4_bermon_state_START_TIMER 1 10511 #define rx_x4_status4_bermon_state_BER_MT_INIT 0 10512 10513 /**************************************************************************** 10514 * Enums: rx_x4_status4_rxsm_state_cl49 10515 */ 10516 #define rx_x4_status4_rxsm_state_cl49_RX_HIG_END 128 10517 #define rx_x4_status4_rxsm_state_cl49_RX_HIG_START 64 10518 #define rx_x4_status4_rxsm_state_cl49_RX_LI 32 10519 #define rx_x4_status4_rxsm_state_cl49_RX_E 16 10520 #define rx_x4_status4_rxsm_state_cl49_RX_T 8 10521 #define rx_x4_status4_rxsm_state_cl49_RX_D 4 10522 #define rx_x4_status4_rxsm_state_cl49_RX_C 2 10523 #define rx_x4_status4_rxsm_state_cl49_RX_INIT 1 10524 10525 /**************************************************************************** 10526 * Enums: rx_x4_status4_r_type 10527 */ 10528 #define rx_x4_status4_r_type_BAD_R_TYPE 15 10529 #define rx_x4_status4_r_type_R_TYPE_B0 11 10530 #define rx_x4_status4_r_type_R_TYPE_OB 10 10531 #define rx_x4_status4_r_type_R_TYPE_B1 9 10532 #define rx_x4_status4_r_type_R_TYPE_DB 8 10533 #define rx_x4_status4_r_type_R_TYPE_FC 7 10534 #define rx_x4_status4_r_type_R_TYPE_TB 6 10535 #define rx_x4_status4_r_type_R_TYPE_LI 5 10536 #define rx_x4_status4_r_type_R_TYPE_C 4 10537 #define rx_x4_status4_r_type_R_TYPE_S 3 10538 #define rx_x4_status4_r_type_R_TYPE_T 2 10539 #define rx_x4_status4_r_type_R_TYPE_D 1 10540 #define rx_x4_status4_r_type_R_TYPE_E 0 10541 10542 /**************************************************************************** 10543 * Enums: rx_x4_status4_am_lock_state 10544 */ 10545 #define rx_x4_status4_am_lock_state_INVALID_AM 512 10546 #define rx_x4_status4_am_lock_state_GOOD_AM 256 10547 #define rx_x4_status4_am_lock_state_COMP_AM 128 10548 #define rx_x4_status4_am_lock_state_TIMER_2 64 10549 #define rx_x4_status4_am_lock_state_AM_2_GOOD 32 10550 #define rx_x4_status4_am_lock_state_COMP_2ND 16 10551 #define rx_x4_status4_am_lock_state_TIMER_1 8 10552 #define rx_x4_status4_am_lock_state_FIND_1ST 4 10553 #define rx_x4_status4_am_lock_state_AM_RESET_CNT 2 10554 #define rx_x4_status4_am_lock_state_AM_LOCK_INIT 1 10555 10556 /**************************************************************************** 10557 * Enums: rx_x4_status4_msg_selector 10558 */ 10559 #define rx_x4_status4_msg_selector_RESERVED 0 10560 #define rx_x4_status4_msg_selector_VALUE_802p3 1 10561 #define rx_x4_status4_msg_selector_VALUE_802p9 2 10562 #define rx_x4_status4_msg_selector_VALUE_802p5 3 10563 #define rx_x4_status4_msg_selector_VALUE_1394 4 10564 10565 /**************************************************************************** 10566 * Enums: rx_x4_status4_synce_enum 10567 */ 10568 #define rx_x4_status4_synce_enum_SYNCE_NO_DIV 0 10569 #define rx_x4_status4_synce_enum_SYNCE_DIV_7 1 10570 #define rx_x4_status4_synce_enum_SYNCE_DIV_11 2 10571 10572 /**************************************************************************** 10573 * Enums: rx_x4_status4_synce_enum_stage0 10574 */ 10575 #define rx_x4_status4_synce_enum_stage0_SYNCE_NO_DIV 0 10576 #define rx_x4_status4_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 10577 #define rx_x4_status4_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 10578 10579 /**************************************************************************** 10580 * Enums: rx_x4_status4_cl91_sync_state 10581 */ 10582 #define rx_x4_status4_cl91_sync_state_FIND_1ST 0 10583 #define rx_x4_status4_cl91_sync_state_COUNT_NEXT 1 10584 #define rx_x4_status4_cl91_sync_state_COMP_2ND 2 10585 #define rx_x4_status4_cl91_sync_state_TWO_GOOD 3 10586 10587 /**************************************************************************** 10588 * Enums: rx_x4_status4_cl91_algn_state 10589 */ 10590 #define rx_x4_status4_cl91_algn_state_LOSS_OF_ALIGNMENT 0 10591 #define rx_x4_status4_cl91_algn_state_DESKEW 1 10592 #define rx_x4_status4_cl91_algn_state_DESKEW_FAIL 2 10593 #define rx_x4_status4_cl91_algn_state_ALIGN_ACQUIRED 3 10594 #define rx_x4_status4_cl91_algn_state_CW_GOOD 4 10595 #define rx_x4_status4_cl91_algn_state_CW_BAD 5 10596 #define rx_x4_status4_cl91_algn_state_THREE_BAD 6 10597 10598 /**************************************************************************** 10599 * Enums: rx_x4_status4_fec_sel_override 10600 */ 10601 #define rx_x4_status4_fec_sel_override_NO_OVERRIDE 0 10602 #define rx_x4_status4_fec_sel_override_NO_FEC 1 10603 #define rx_x4_status4_fec_sel_override_FEC_CL74 2 10604 #define rx_x4_status4_fec_sel_override_FEC_CL91 3 10605 10606 /**************************************************************************** 10607 * Enums: rx_x4_status4_cl91_blksync_mode 10608 */ 10609 #define rx_x4_status4_cl91_blksync_mode_R_BLKSYNC_NO_CL91_FEC 0 10610 #define rx_x4_status4_cl91_blksync_mode_R_BLKSYNC_CL91_QUAD_LANE_FEC 1 10611 #define rx_x4_status4_cl91_blksync_mode_R_BLKSYNC_CL91_DUAL_LANE_FEC 2 10612 #define rx_x4_status4_cl91_blksync_mode_R_BLKSYNC_CL91_SINGLE_LANE_FEC 3 10613 #define rx_x4_status4_cl91_blksync_mode_R_BLKSYNC_CL91_FC_FEC 4 10614 10615 /**************************************************************************** 10616 * Enums: rx_x4_status4_r_merge_mode 10617 */ 10618 #define rx_x4_status4_r_merge_mode_R_MERGE_MODE_BYPASS 0 10619 #define rx_x4_status4_r_merge_mode_R_MERGE_MODE_CL91_FC 1 10620 #define rx_x4_status4_r_merge_mode_R_MERGE_MODE_CL91_SINGLE_LANE 2 10621 #define rx_x4_status4_r_merge_mode_R_MERGE_MODE_CL91_DUAL_LANE 3 10622 #define rx_x4_status4_r_merge_mode_R_MERGE_MODE_CL91_QUAD_LANE 4 10623 10624 /**************************************************************************** 10625 * Enums: rx_x4_status4_r_tc_mode 10626 */ 10627 #define rx_x4_status4_r_tc_mode_R_TC_MODE_SINGLE 0 10628 #define rx_x4_status4_r_tc_mode_R_TC_MODE_DUAL 1 10629 #define rx_x4_status4_r_tc_mode_R_TC_MODE_QUAD 2 10630 10631 /**************************************************************************** 10632 * Enums: rx_x4_status4_r_tc_out_mode 10633 */ 10634 #define rx_x4_status4_r_tc_out_mode_R_TC_OUT_MODE_SINGLE 0 10635 #define rx_x4_status4_r_tc_out_mode_R_TC_OUT_MODE_DUAL 1 10636 #define rx_x4_status4_r_tc_out_mode_R_TC_OUT_MODE_QUAD 2 10637 10638 /**************************************************************************** 10639 * Enums: rx_x4_status4_cl91_fec_mode 10640 */ 10641 #define rx_x4_status4_cl91_fec_mode_NO_CL91_FEC 0 10642 #define rx_x4_status4_cl91_fec_mode_CL91_SINGLE_LANE_FC 1 10643 #define rx_x4_status4_cl91_fec_mode_CL91_SINGLE_LANE_BRCM_PROP 2 10644 #define rx_x4_status4_cl91_fec_mode_CL91_DUAL_LANE_BRCM_PROP 3 10645 #define rx_x4_status4_cl91_fec_mode_CL91_QUAD_LANE 4 10646 #define rx_x4_status4_cl91_fec_mode_IEEE_25G_CL91_SINGLE_LANE 5 10647 10648 /**************************************************************************** 10649 * Enums: rx_x4_status4_am_spacing_mul 10650 */ 10651 #define rx_x4_status4_am_spacing_mul_AM_SPACING_MUL_2 0 10652 #define rx_x4_status4_am_spacing_mul_AM_SPACING_MUL_4 1 10653 #define rx_x4_status4_am_spacing_mul_AM_SPACING_MUL_5 2 10654 #define rx_x4_status4_am_spacing_mul_AM_SPACING_MUL_20 3 10655 10656 /**************************************************************************** 10657 * Enums: rx_x4_status5_cl36TxEEEStates_l 10658 */ 10659 #define rx_x4_status5_cl36TxEEEStates_l_TX_REFRESH 8 10660 #define rx_x4_status5_cl36TxEEEStates_l_TX_QUIET 4 10661 #define rx_x4_status5_cl36TxEEEStates_l_TX_SLEEP 2 10662 #define rx_x4_status5_cl36TxEEEStates_l_TX_ACTIVE 1 10663 10664 /**************************************************************************** 10665 * Enums: rx_x4_status5_cl36TxEEEStates_c 10666 */ 10667 #define rx_x4_status5_cl36TxEEEStates_c_TX_REFRESH 3 10668 #define rx_x4_status5_cl36TxEEEStates_c_TX_QUIET 2 10669 #define rx_x4_status5_cl36TxEEEStates_c_TX_SLEEP 1 10670 #define rx_x4_status5_cl36TxEEEStates_c_TX_ACTIVE 0 10671 10672 /**************************************************************************** 10673 * Enums: rx_x4_status5_cl49TxEEEStates_l 10674 */ 10675 #define rx_x4_status5_cl49TxEEEStates_l_SCR_RESET_2 64 10676 #define rx_x4_status5_cl49TxEEEStates_l_SCR_RESET_1 32 10677 #define rx_x4_status5_cl49TxEEEStates_l_TX_WAKE 16 10678 #define rx_x4_status5_cl49TxEEEStates_l_TX_REFRESH 8 10679 #define rx_x4_status5_cl49TxEEEStates_l_TX_QUIET 4 10680 #define rx_x4_status5_cl49TxEEEStates_l_TX_SLEEP 2 10681 #define rx_x4_status5_cl49TxEEEStates_l_TX_ACTIVE 1 10682 10683 /**************************************************************************** 10684 * Enums: rx_x4_status5_fec_req_enum 10685 */ 10686 #define rx_x4_status5_fec_req_enum_FEC_not_supported 0 10687 #define rx_x4_status5_fec_req_enum_FEC_supported_but_not_requested 1 10688 #define rx_x4_status5_fec_req_enum_invalid_setting 2 10689 #define rx_x4_status5_fec_req_enum_FEC_supported_and_requested 3 10690 10691 /**************************************************************************** 10692 * Enums: rx_x4_status5_cl73_pause_enum 10693 */ 10694 #define rx_x4_status5_cl73_pause_enum_No_PAUSE_ability 0 10695 #define rx_x4_status5_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 10696 #define rx_x4_status5_cl73_pause_enum_Symmetric_PAUSE_ability 1 10697 #define rx_x4_status5_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 10698 10699 /**************************************************************************** 10700 * Enums: rx_x4_status5_cl49TxEEEStates_c 10701 */ 10702 #define rx_x4_status5_cl49TxEEEStates_c_SCR_RESET_2 6 10703 #define rx_x4_status5_cl49TxEEEStates_c_SCR_RESET_1 5 10704 #define rx_x4_status5_cl49TxEEEStates_c_TX_WAKE 4 10705 #define rx_x4_status5_cl49TxEEEStates_c_TX_REFRESH 3 10706 #define rx_x4_status5_cl49TxEEEStates_c_TX_QUIET 2 10707 #define rx_x4_status5_cl49TxEEEStates_c_TX_SLEEP 1 10708 #define rx_x4_status5_cl49TxEEEStates_c_TX_ACTIVE 0 10709 10710 /**************************************************************************** 10711 * Enums: rx_x4_status5_cl36RxEEEStates_l 10712 */ 10713 #define rx_x4_status5_cl36RxEEEStates_l_RX_LINK_FAIL 32 10714 #define rx_x4_status5_cl36RxEEEStates_l_RX_WTF 16 10715 #define rx_x4_status5_cl36RxEEEStates_l_RX_WAKE 8 10716 #define rx_x4_status5_cl36RxEEEStates_l_RX_QUIET 4 10717 #define rx_x4_status5_cl36RxEEEStates_l_RX_SLEEP 2 10718 #define rx_x4_status5_cl36RxEEEStates_l_RX_ACTIVE 1 10719 10720 /**************************************************************************** 10721 * Enums: rx_x4_status5_cl36RxEEEStates_c 10722 */ 10723 #define rx_x4_status5_cl36RxEEEStates_c_RX_LINK_FAIL 5 10724 #define rx_x4_status5_cl36RxEEEStates_c_RX_WTF 4 10725 #define rx_x4_status5_cl36RxEEEStates_c_RX_WAKE 3 10726 #define rx_x4_status5_cl36RxEEEStates_c_RX_QUIET 2 10727 #define rx_x4_status5_cl36RxEEEStates_c_RX_SLEEP 1 10728 #define rx_x4_status5_cl36RxEEEStates_c_RX_ACTIVE 0 10729 10730 /**************************************************************************** 10731 * Enums: rx_x4_status5_cl49RxEEEStates_l 10732 */ 10733 #define rx_x4_status5_cl49RxEEEStates_l_RX_LINK_FAIL 32 10734 #define rx_x4_status5_cl49RxEEEStates_l_RX_WTF 16 10735 #define rx_x4_status5_cl49RxEEEStates_l_RX_WAKE 8 10736 #define rx_x4_status5_cl49RxEEEStates_l_RX_QUIET 4 10737 #define rx_x4_status5_cl49RxEEEStates_l_RX_SLEEP 2 10738 #define rx_x4_status5_cl49RxEEEStates_l_RX_ACTIVE 1 10739 10740 /**************************************************************************** 10741 * Enums: rx_x4_status5_cl49RxEEEStates_c 10742 */ 10743 #define rx_x4_status5_cl49RxEEEStates_c_RX_LINK_FAIL 5 10744 #define rx_x4_status5_cl49RxEEEStates_c_RX_WTF 4 10745 #define rx_x4_status5_cl49RxEEEStates_c_RX_WAKE 3 10746 #define rx_x4_status5_cl49RxEEEStates_c_RX_QUIET 2 10747 #define rx_x4_status5_cl49RxEEEStates_c_RX_SLEEP 1 10748 #define rx_x4_status5_cl49RxEEEStates_c_RX_ACTIVE 0 10749 10750 /**************************************************************************** 10751 * Enums: rx_x4_status5_cl48TxEEEStates_l 10752 */ 10753 #define rx_x4_status5_cl48TxEEEStates_l_TX_REFRESH 8 10754 #define rx_x4_status5_cl48TxEEEStates_l_TX_QUIET 4 10755 #define rx_x4_status5_cl48TxEEEStates_l_TX_SLEEP 2 10756 #define rx_x4_status5_cl48TxEEEStates_l_TX_ACTIVE 1 10757 10758 /**************************************************************************** 10759 * Enums: rx_x4_status5_cl48TxEEEStates_c 10760 */ 10761 #define rx_x4_status5_cl48TxEEEStates_c_TX_REFRESH 3 10762 #define rx_x4_status5_cl48TxEEEStates_c_TX_QUIET 2 10763 #define rx_x4_status5_cl48TxEEEStates_c_TX_SLEEP 1 10764 #define rx_x4_status5_cl48TxEEEStates_c_TX_ACTIVE 0 10765 10766 /**************************************************************************** 10767 * Enums: rx_x4_status5_cl48RxEEEStates_l 10768 */ 10769 #define rx_x4_status5_cl48RxEEEStates_l_RX_LINK_FAIL 32 10770 #define rx_x4_status5_cl48RxEEEStates_l_RX_WAKE 16 10771 #define rx_x4_status5_cl48RxEEEStates_l_RX_QUIET 8 10772 #define rx_x4_status5_cl48RxEEEStates_l_RX_DEACT 4 10773 #define rx_x4_status5_cl48RxEEEStates_l_RX_SLEEP 2 10774 #define rx_x4_status5_cl48RxEEEStates_l_RX_ACTIVE 1 10775 10776 /**************************************************************************** 10777 * Enums: rx_x4_status5_cl48RxEEEStates_c 10778 */ 10779 #define rx_x4_status5_cl48RxEEEStates_c_RX_LINK_FAIL 5 10780 #define rx_x4_status5_cl48RxEEEStates_c_RX_WAKE 4 10781 #define rx_x4_status5_cl48RxEEEStates_c_RX_QUIET 3 10782 #define rx_x4_status5_cl48RxEEEStates_c_RX_DEACT 2 10783 #define rx_x4_status5_cl48RxEEEStates_c_RX_SLEEP 1 10784 #define rx_x4_status5_cl48RxEEEStates_c_RX_ACTIVE 0 10785 10786 /**************************************************************************** 10787 * Enums: rx_x4_status5_IQP_Options 10788 */ 10789 #define rx_x4_status5_IQP_Options_i50uA 0 10790 #define rx_x4_status5_IQP_Options_i100uA 1 10791 #define rx_x4_status5_IQP_Options_i150uA 2 10792 #define rx_x4_status5_IQP_Options_i200uA 3 10793 #define rx_x4_status5_IQP_Options_i250uA 4 10794 #define rx_x4_status5_IQP_Options_i300uA 5 10795 #define rx_x4_status5_IQP_Options_i350uA 6 10796 #define rx_x4_status5_IQP_Options_i400uA 7 10797 #define rx_x4_status5_IQP_Options_i450uA 8 10798 #define rx_x4_status5_IQP_Options_i500uA 9 10799 #define rx_x4_status5_IQP_Options_i550uA 10 10800 #define rx_x4_status5_IQP_Options_i600uA 11 10801 #define rx_x4_status5_IQP_Options_i650uA 12 10802 #define rx_x4_status5_IQP_Options_i700uA 13 10803 #define rx_x4_status5_IQP_Options_i750uA 14 10804 #define rx_x4_status5_IQP_Options_i800uA 15 10805 10806 /**************************************************************************** 10807 * Enums: rx_x4_status5_IDriver_Options 10808 */ 10809 #define rx_x4_status5_IDriver_Options_v680mV 0 10810 #define rx_x4_status5_IDriver_Options_v730mV 1 10811 #define rx_x4_status5_IDriver_Options_v780mV 2 10812 #define rx_x4_status5_IDriver_Options_v830mV 3 10813 #define rx_x4_status5_IDriver_Options_v880mV 4 10814 #define rx_x4_status5_IDriver_Options_v930mV 5 10815 #define rx_x4_status5_IDriver_Options_v980mV 6 10816 #define rx_x4_status5_IDriver_Options_v1010mV 7 10817 #define rx_x4_status5_IDriver_Options_v1040mV 8 10818 #define rx_x4_status5_IDriver_Options_v1060mV 9 10819 #define rx_x4_status5_IDriver_Options_v1070mV 10 10820 #define rx_x4_status5_IDriver_Options_v1080mV 11 10821 #define rx_x4_status5_IDriver_Options_v1085mV 12 10822 #define rx_x4_status5_IDriver_Options_v1090mV 13 10823 #define rx_x4_status5_IDriver_Options_v1095mV 14 10824 #define rx_x4_status5_IDriver_Options_v1100mV 15 10825 10826 /**************************************************************************** 10827 * Enums: rx_x4_status5_operationModes 10828 */ 10829 #define rx_x4_status5_operationModes_XGXS 0 10830 #define rx_x4_status5_operationModes_XGXG_nCC 1 10831 #define rx_x4_status5_operationModes_Indlane_OS8 4 10832 #define rx_x4_status5_operationModes_IndLane_OS5 5 10833 #define rx_x4_status5_operationModes_PCI 7 10834 #define rx_x4_status5_operationModes_XGXS_nLQ 8 10835 #define rx_x4_status5_operationModes_XGXS_nLQnCC 9 10836 #define rx_x4_status5_operationModes_PBypass 10 10837 #define rx_x4_status5_operationModes_PBypass_nDSK 11 10838 #define rx_x4_status5_operationModes_ComboCoreMode 12 10839 #define rx_x4_status5_operationModes_Clocks_off 15 10840 10841 /**************************************************************************** 10842 * Enums: rx_x4_status5_actualSpeeds 10843 */ 10844 #define rx_x4_status5_actualSpeeds_dr_10M 0 10845 #define rx_x4_status5_actualSpeeds_dr_100M 1 10846 #define rx_x4_status5_actualSpeeds_dr_1G 2 10847 #define rx_x4_status5_actualSpeeds_dr_2p5G 3 10848 #define rx_x4_status5_actualSpeeds_dr_5G_X4 4 10849 #define rx_x4_status5_actualSpeeds_dr_6G_X4 5 10850 #define rx_x4_status5_actualSpeeds_dr_10G_HiG 6 10851 #define rx_x4_status5_actualSpeeds_dr_10G_CX4 7 10852 #define rx_x4_status5_actualSpeeds_dr_12G_HiG 8 10853 #define rx_x4_status5_actualSpeeds_dr_12p5G_X4 9 10854 #define rx_x4_status5_actualSpeeds_dr_13G_X4 10 10855 #define rx_x4_status5_actualSpeeds_dr_15G_X4 11 10856 #define rx_x4_status5_actualSpeeds_dr_16G_X4 12 10857 #define rx_x4_status5_actualSpeeds_dr_1G_KX 13 10858 #define rx_x4_status5_actualSpeeds_dr_10G_KX4 14 10859 #define rx_x4_status5_actualSpeeds_dr_10G_KR 15 10860 #define rx_x4_status5_actualSpeeds_dr_5G 16 10861 #define rx_x4_status5_actualSpeeds_dr_6p4G 17 10862 #define rx_x4_status5_actualSpeeds_dr_20G_X4 18 10863 #define rx_x4_status5_actualSpeeds_dr_21G_X4 19 10864 #define rx_x4_status5_actualSpeeds_dr_25G_X4 20 10865 #define rx_x4_status5_actualSpeeds_dr_10G_HiG_DXGXS 21 10866 #define rx_x4_status5_actualSpeeds_dr_10G_DXGXS 22 10867 #define rx_x4_status5_actualSpeeds_dr_10p5G_HiG_DXGXS 23 10868 #define rx_x4_status5_actualSpeeds_dr_10p5G_DXGXS 24 10869 #define rx_x4_status5_actualSpeeds_dr_12p773G_HiG_DXGXS 25 10870 #define rx_x4_status5_actualSpeeds_dr_12p773G_DXGXS 26 10871 #define rx_x4_status5_actualSpeeds_dr_10G_XFI 27 10872 #define rx_x4_status5_actualSpeeds_dr_40G 28 10873 #define rx_x4_status5_actualSpeeds_dr_20G_HiG_DXGXS 29 10874 #define rx_x4_status5_actualSpeeds_dr_20G_DXGXS 30 10875 #define rx_x4_status5_actualSpeeds_dr_10G_SFI 31 10876 #define rx_x4_status5_actualSpeeds_dr_31p5G 32 10877 #define rx_x4_status5_actualSpeeds_dr_32p7G 33 10878 #define rx_x4_status5_actualSpeeds_dr_20G_SCR 34 10879 #define rx_x4_status5_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 10880 #define rx_x4_status5_actualSpeeds_dr_10G_DXGXS_SCR 36 10881 #define rx_x4_status5_actualSpeeds_dr_12G_R2 37 10882 #define rx_x4_status5_actualSpeeds_dr_10G_X2 38 10883 #define rx_x4_status5_actualSpeeds_dr_40G_KR4 39 10884 #define rx_x4_status5_actualSpeeds_dr_40G_CR4 40 10885 #define rx_x4_status5_actualSpeeds_dr_100G_CR10 41 10886 #define rx_x4_status5_actualSpeeds_dr_15p75G_DXGXS 44 10887 #define rx_x4_status5_actualSpeeds_dr_20G_KR2 57 10888 #define rx_x4_status5_actualSpeeds_dr_20G_CR2 58 10889 10890 /**************************************************************************** 10891 * Enums: rx_x4_status5_actualSpeedsMisc1 10892 */ 10893 #define rx_x4_status5_actualSpeedsMisc1_dr_2500BRCM_X1 16 10894 #define rx_x4_status5_actualSpeedsMisc1_dr_5000BRCM_X4 17 10895 #define rx_x4_status5_actualSpeedsMisc1_dr_6000BRCM_X4 18 10896 #define rx_x4_status5_actualSpeedsMisc1_dr_10GHiGig_X4 19 10897 #define rx_x4_status5_actualSpeedsMisc1_dr_10GBASE_CX4 20 10898 #define rx_x4_status5_actualSpeedsMisc1_dr_12GHiGig_X4 21 10899 #define rx_x4_status5_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 10900 #define rx_x4_status5_actualSpeedsMisc1_dr_13GHiGig_X4 23 10901 #define rx_x4_status5_actualSpeedsMisc1_dr_15GHiGig_X4 24 10902 #define rx_x4_status5_actualSpeedsMisc1_dr_16GHiGig_X4 25 10903 #define rx_x4_status5_actualSpeedsMisc1_dr_5000BRCM_X1 26 10904 #define rx_x4_status5_actualSpeedsMisc1_dr_6363BRCM_X1 27 10905 #define rx_x4_status5_actualSpeedsMisc1_dr_20GHiGig_X4 28 10906 #define rx_x4_status5_actualSpeedsMisc1_dr_21GHiGig_X4 29 10907 #define rx_x4_status5_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 10908 #define rx_x4_status5_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 10909 10910 /**************************************************************************** 10911 * Enums: rx_x4_status5_IndLaneModes 10912 */ 10913 #define rx_x4_status5_IndLaneModes_SWSDR_div2 0 10914 #define rx_x4_status5_IndLaneModes_SWSDR_div1 1 10915 #define rx_x4_status5_IndLaneModes_DWSDR_div2 2 10916 #define rx_x4_status5_IndLaneModes_DWSDR_div1 3 10917 10918 /**************************************************************************** 10919 * Enums: rx_x4_status5_prbsSelect 10920 */ 10921 #define rx_x4_status5_prbsSelect_prbs7 0 10922 #define rx_x4_status5_prbsSelect_prbs15 1 10923 #define rx_x4_status5_prbsSelect_prbs23 2 10924 #define rx_x4_status5_prbsSelect_prbs31 3 10925 10926 /**************************************************************************** 10927 * Enums: rx_x4_status5_vcoDivider 10928 */ 10929 #define rx_x4_status5_vcoDivider_div32 0 10930 #define rx_x4_status5_vcoDivider_div36 1 10931 #define rx_x4_status5_vcoDivider_div40 2 10932 #define rx_x4_status5_vcoDivider_div42 3 10933 #define rx_x4_status5_vcoDivider_div48 4 10934 #define rx_x4_status5_vcoDivider_div50 5 10935 #define rx_x4_status5_vcoDivider_div52 6 10936 #define rx_x4_status5_vcoDivider_div54 7 10937 #define rx_x4_status5_vcoDivider_div60 8 10938 #define rx_x4_status5_vcoDivider_div64 9 10939 #define rx_x4_status5_vcoDivider_div66 10 10940 #define rx_x4_status5_vcoDivider_div68 11 10941 #define rx_x4_status5_vcoDivider_div70 12 10942 #define rx_x4_status5_vcoDivider_div80 13 10943 #define rx_x4_status5_vcoDivider_div92 14 10944 #define rx_x4_status5_vcoDivider_div100 15 10945 10946 /**************************************************************************** 10947 * Enums: rx_x4_status5_refClkSelect 10948 */ 10949 #define rx_x4_status5_refClkSelect_clk_25MHz 0 10950 #define rx_x4_status5_refClkSelect_clk_100MHz 1 10951 #define rx_x4_status5_refClkSelect_clk_125MHz 2 10952 #define rx_x4_status5_refClkSelect_clk_156p25MHz 3 10953 #define rx_x4_status5_refClkSelect_clk_187p5MHz 4 10954 #define rx_x4_status5_refClkSelect_clk_161p25Mhz 5 10955 #define rx_x4_status5_refClkSelect_clk_50Mhz 6 10956 #define rx_x4_status5_refClkSelect_clk_106p25Mhz 7 10957 10958 /**************************************************************************** 10959 * Enums: rx_x4_status5_aerMMDdevTypeSelect 10960 */ 10961 #define rx_x4_status5_aerMMDdevTypeSelect_combo_core 0 10962 #define rx_x4_status5_aerMMDdevTypeSelect_PMA_PMD 1 10963 #define rx_x4_status5_aerMMDdevTypeSelect_PCS 3 10964 #define rx_x4_status5_aerMMDdevTypeSelect_PHY 4 10965 #define rx_x4_status5_aerMMDdevTypeSelect_DTE 5 10966 #define rx_x4_status5_aerMMDdevTypeSelect_CL73_AN 7 10967 10968 /**************************************************************************** 10969 * Enums: rx_x4_status5_aerMMDportSelect 10970 */ 10971 #define rx_x4_status5_aerMMDportSelect_ln0 0 10972 #define rx_x4_status5_aerMMDportSelect_ln1 1 10973 #define rx_x4_status5_aerMMDportSelect_ln2 2 10974 #define rx_x4_status5_aerMMDportSelect_ln3 3 10975 #define rx_x4_status5_aerMMDportSelect_BCST_ln0_1_2_3 511 10976 #define rx_x4_status5_aerMMDportSelect_BCST_ln0_1 512 10977 #define rx_x4_status5_aerMMDportSelect_BCST_ln2_3 513 10978 10979 /**************************************************************************** 10980 * Enums: rx_x4_status5_firmwareModeSelect 10981 */ 10982 #define rx_x4_status5_firmwareModeSelect_DEFAULT 0 10983 #define rx_x4_status5_firmwareModeSelect_SFP_OPT_LR 1 10984 #define rx_x4_status5_firmwareModeSelect_SFP_DAC 2 10985 #define rx_x4_status5_firmwareModeSelect_XLAUI 3 10986 #define rx_x4_status5_firmwareModeSelect_LONG_CH_6G 4 10987 10988 /**************************************************************************** 10989 * Enums: rx_x4_status5_tempIdxSelect 10990 */ 10991 #define rx_x4_status5_tempIdxSelect_LTE__22p9C 15 10992 #define rx_x4_status5_tempIdxSelect_LTE__12p6C 14 10993 #define rx_x4_status5_tempIdxSelect_LTE__3p0C 13 10994 #define rx_x4_status5_tempIdxSelect_LTE_6p7C 12 10995 #define rx_x4_status5_tempIdxSelect_LTE_16p4C 11 10996 #define rx_x4_status5_tempIdxSelect_LTE_26p6C 10 10997 #define rx_x4_status5_tempIdxSelect_LTE_36p3C 9 10998 #define rx_x4_status5_tempIdxSelect_LTE_46p0C 8 10999 #define rx_x4_status5_tempIdxSelect_LTE_56p2C 7 11000 #define rx_x4_status5_tempIdxSelect_LTE_65p9C 6 11001 #define rx_x4_status5_tempIdxSelect_LTE_75p6C 5 11002 #define rx_x4_status5_tempIdxSelect_LTE_85p3C 4 11003 #define rx_x4_status5_tempIdxSelect_LTE_95p5C 3 11004 #define rx_x4_status5_tempIdxSelect_LTE_105p2C 2 11005 #define rx_x4_status5_tempIdxSelect_LTE_114p9C 1 11006 #define rx_x4_status5_tempIdxSelect_LTE_125p1C 0 11007 11008 /**************************************************************************** 11009 * Enums: rx_x4_status5_port_mode 11010 */ 11011 #define rx_x4_status5_port_mode_QUAD_PORT 0 11012 #define rx_x4_status5_port_mode_TRI_1_PORT 1 11013 #define rx_x4_status5_port_mode_TRI_2_PORT 2 11014 #define rx_x4_status5_port_mode_DUAL_PORT 3 11015 #define rx_x4_status5_port_mode_SINGLE_PORT 4 11016 11017 /**************************************************************************** 11018 * Enums: rx_x4_status5_rev_letter_enum 11019 */ 11020 #define rx_x4_status5_rev_letter_enum_REV_A 0 11021 #define rx_x4_status5_rev_letter_enum_REV_B 1 11022 #define rx_x4_status5_rev_letter_enum_REV_C 2 11023 #define rx_x4_status5_rev_letter_enum_REV_D 3 11024 11025 /**************************************************************************** 11026 * Enums: rx_x4_status5_rev_number_enum 11027 */ 11028 #define rx_x4_status5_rev_number_enum_REV_0 0 11029 #define rx_x4_status5_rev_number_enum_REV_1 1 11030 #define rx_x4_status5_rev_number_enum_REV_2 2 11031 #define rx_x4_status5_rev_number_enum_REV_3 3 11032 #define rx_x4_status5_rev_number_enum_REV_4 4 11033 #define rx_x4_status5_rev_number_enum_REV_5 5 11034 #define rx_x4_status5_rev_number_enum_REV_6 6 11035 #define rx_x4_status5_rev_number_enum_REV_7 7 11036 11037 /**************************************************************************** 11038 * Enums: rx_x4_status5_bonding_enum 11039 */ 11040 #define rx_x4_status5_bonding_enum_WIRE_BOND 0 11041 #define rx_x4_status5_bonding_enum_FLIP_CHIP 1 11042 11043 /**************************************************************************** 11044 * Enums: rx_x4_status5_tech_process 11045 */ 11046 #define rx_x4_status5_tech_process_PROCESS_90NM 0 11047 #define rx_x4_status5_tech_process_PROCESS_65NM 1 11048 #define rx_x4_status5_tech_process_PROCESS_40NM 2 11049 #define rx_x4_status5_tech_process_PROCESS_28NM 3 11050 #define rx_x4_status5_tech_process_PROCESS_16NM 4 11051 11052 /**************************************************************************** 11053 * Enums: rx_x4_status5_model_num 11054 */ 11055 #define rx_x4_status5_model_num_SERDES_CL73 0 11056 #define rx_x4_status5_model_num_XGXS_16G 1 11057 #define rx_x4_status5_model_num_HYPERCORE 2 11058 #define rx_x4_status5_model_num_HYPERLITE 3 11059 #define rx_x4_status5_model_num_PCIE_G2_PIPE 4 11060 #define rx_x4_status5_model_num_SERDES_1p25GBd 5 11061 #define rx_x4_status5_model_num_SATA2 6 11062 #define rx_x4_status5_model_num_QSGMII 7 11063 #define rx_x4_status5_model_num_XGXS10G 8 11064 #define rx_x4_status5_model_num_WARPCORE 9 11065 #define rx_x4_status5_model_num_XFICORE 10 11066 #define rx_x4_status5_model_num_RXFI 11 11067 #define rx_x4_status5_model_num_WARPLITE 12 11068 #define rx_x4_status5_model_num_PENTACORE 13 11069 #define rx_x4_status5_model_num_ESM 14 11070 #define rx_x4_status5_model_num_QUAD_SGMII 15 11071 #define rx_x4_status5_model_num_WARPCORE_3 16 11072 #define rx_x4_status5_model_num_TSC 17 11073 #define rx_x4_status5_model_num_TSC4E 18 11074 #define rx_x4_status5_model_num_TSC12E 19 11075 #define rx_x4_status5_model_num_TSC4F 20 11076 #define rx_x4_status5_model_num_TSC4F_GEN2 21 11077 #define rx_x4_status5_model_num_XGXS_CL73_90NM 29 11078 #define rx_x4_status5_model_num_SERDES_CL73_90NM 30 11079 #define rx_x4_status5_model_num_WARPCORE3 32 11080 #define rx_x4_status5_model_num_WARPCORE4_TSC 33 11081 #define rx_x4_status5_model_num_RXAUI 34 11082 11083 /**************************************************************************** 11084 * Enums: rx_x4_status5_payload 11085 */ 11086 #define rx_x4_status5_payload_REPEAT_2_BYTES 0 11087 #define rx_x4_status5_payload_RAMPING 1 11088 #define rx_x4_status5_payload_CL48_CRPAT 2 11089 #define rx_x4_status5_payload_CL48_CJPAT 3 11090 #define rx_x4_status5_payload_CL36_LONG_CRPAT 4 11091 #define rx_x4_status5_payload_CL36_SHORT_CRPAT 5 11092 11093 /**************************************************************************** 11094 * Enums: rx_x4_status5_sc 11095 */ 11096 #define rx_x4_status5_sc_S_10G_CR1 0 11097 #define rx_x4_status5_sc_S_10G_KR1 1 11098 #define rx_x4_status5_sc_S_10G_X1 2 11099 #define rx_x4_status5_sc_S_10G_HG2_CR1 4 11100 #define rx_x4_status5_sc_S_10G_HG2_KR1 5 11101 #define rx_x4_status5_sc_S_10G_HG2_X1 6 11102 #define rx_x4_status5_sc_S_20G_CR1 8 11103 #define rx_x4_status5_sc_S_20G_KR1 9 11104 #define rx_x4_status5_sc_S_20G_X1 10 11105 #define rx_x4_status5_sc_S_20G_HG2_CR1 12 11106 #define rx_x4_status5_sc_S_20G_HG2_KR1 13 11107 #define rx_x4_status5_sc_S_20G_HG2_X1 14 11108 #define rx_x4_status5_sc_S_25G_CR1 16 11109 #define rx_x4_status5_sc_S_25G_KR1 17 11110 #define rx_x4_status5_sc_S_25G_X1 18 11111 #define rx_x4_status5_sc_S_25G_HG2_CR1 20 11112 #define rx_x4_status5_sc_S_25G_HG2_KR1 21 11113 #define rx_x4_status5_sc_S_25G_HG2_X1 22 11114 #define rx_x4_status5_sc_S_20G_CR2 24 11115 #define rx_x4_status5_sc_S_20G_KR2 25 11116 #define rx_x4_status5_sc_S_20G_X2 26 11117 #define rx_x4_status5_sc_S_20G_HG2_CR2 28 11118 #define rx_x4_status5_sc_S_20G_HG2_KR2 29 11119 #define rx_x4_status5_sc_S_20G_HG2_X2 30 11120 #define rx_x4_status5_sc_S_40G_CR2 32 11121 #define rx_x4_status5_sc_S_40G_KR2 33 11122 #define rx_x4_status5_sc_S_40G_X2 34 11123 #define rx_x4_status5_sc_S_40G_HG2_CR2 36 11124 #define rx_x4_status5_sc_S_40G_HG2_KR2 37 11125 #define rx_x4_status5_sc_S_40G_HG2_X2 38 11126 #define rx_x4_status5_sc_S_40G_CR4 40 11127 #define rx_x4_status5_sc_S_40G_KR4 41 11128 #define rx_x4_status5_sc_S_40G_X4 42 11129 #define rx_x4_status5_sc_S_40G_HG2_CR4 44 11130 #define rx_x4_status5_sc_S_40G_HG2_KR4 45 11131 #define rx_x4_status5_sc_S_40G_HG2_X4 46 11132 #define rx_x4_status5_sc_S_50G_CR2 48 11133 #define rx_x4_status5_sc_S_50G_KR2 49 11134 #define rx_x4_status5_sc_S_50G_X2 50 11135 #define rx_x4_status5_sc_S_50G_HG2_CR2 52 11136 #define rx_x4_status5_sc_S_50G_HG2_KR2 53 11137 #define rx_x4_status5_sc_S_50G_HG2_X2 54 11138 #define rx_x4_status5_sc_S_50G_CR4 56 11139 #define rx_x4_status5_sc_S_50G_KR4 57 11140 #define rx_x4_status5_sc_S_50G_X4 58 11141 #define rx_x4_status5_sc_S_50G_HG2_CR4 60 11142 #define rx_x4_status5_sc_S_50G_HG2_KR4 61 11143 #define rx_x4_status5_sc_S_50G_HG2_X4 62 11144 #define rx_x4_status5_sc_S_100G_CR4 64 11145 #define rx_x4_status5_sc_S_100G_KR4 65 11146 #define rx_x4_status5_sc_S_100G_X4 66 11147 #define rx_x4_status5_sc_S_100G_HG2_CR4 68 11148 #define rx_x4_status5_sc_S_100G_HG2_KR4 69 11149 #define rx_x4_status5_sc_S_100G_HG2_X4 70 11150 #define rx_x4_status5_sc_S_CL73_20GVCO 72 11151 #define rx_x4_status5_sc_S_CL73_25GVCO 80 11152 #define rx_x4_status5_sc_S_CL36_20GVCO 88 11153 #define rx_x4_status5_sc_S_CL36_25GVCO 96 11154 #define rx_x4_status5_sc_S_25G_CR_IEEE 112 11155 #define rx_x4_status5_sc_S_25G_CRS_IEEE 113 11156 #define rx_x4_status5_sc_S_25G_KR_IEEE 114 11157 #define rx_x4_status5_sc_S_25G_KRS_IEEE 115 11158 11159 /**************************************************************************** 11160 * Enums: rx_x4_status5_t_fifo_modes 11161 */ 11162 #define rx_x4_status5_t_fifo_modes_T_FIFO_INSERT_NO_AM 0 11163 #define rx_x4_status5_t_fifo_modes_T_FIFO_INSERT_4_AM 1 11164 #define rx_x4_status5_t_fifo_modes_T_FIFO_INSERT_20_AM 2 11165 #define rx_x4_status5_t_fifo_modes_T_FIFO_INSERT_2_AM 3 11166 11167 /**************************************************************************** 11168 * Enums: rx_x4_status5_t_enc_modes 11169 */ 11170 #define rx_x4_status5_t_enc_modes_T_ENC_MODE_BYPASS 0 11171 #define rx_x4_status5_t_enc_modes_T_ENC_MODE_CL49 1 11172 #define rx_x4_status5_t_enc_modes_T_ENC_MODE_CL82 2 11173 11174 /**************************************************************************** 11175 * Enums: rx_x4_status5_btmx_mode 11176 */ 11177 #define rx_x4_status5_btmx_mode_BS_BTMX_MODE_1to1 0 11178 #define rx_x4_status5_btmx_mode_BS_BTMX_MODE_2to1 1 11179 #define rx_x4_status5_btmx_mode_BS_BTMX_MODE_5to1 2 11180 11181 /**************************************************************************** 11182 * Enums: rx_x4_status5_t_type_cl82 11183 */ 11184 #define rx_x4_status5_t_type_cl82_T_TYPE_B1 5 11185 #define rx_x4_status5_t_type_cl82_T_TYPE_C 4 11186 #define rx_x4_status5_t_type_cl82_T_TYPE_S 3 11187 #define rx_x4_status5_t_type_cl82_T_TYPE_T 2 11188 #define rx_x4_status5_t_type_cl82_T_TYPE_D 1 11189 #define rx_x4_status5_t_type_cl82_T_TYPE_E 0 11190 11191 /**************************************************************************** 11192 * Enums: rx_x4_status5_txsm_state_cl82 11193 */ 11194 #define rx_x4_status5_txsm_state_cl82_TX_HIG_END 6 11195 #define rx_x4_status5_txsm_state_cl82_TX_HIG_START 5 11196 #define rx_x4_status5_txsm_state_cl82_TX_E 4 11197 #define rx_x4_status5_txsm_state_cl82_TX_T 3 11198 #define rx_x4_status5_txsm_state_cl82_TX_D 2 11199 #define rx_x4_status5_txsm_state_cl82_TX_C 1 11200 #define rx_x4_status5_txsm_state_cl82_TX_INIT 0 11201 11202 /**************************************************************************** 11203 * Enums: rx_x4_status5_ltxsm_state_cl82 11204 */ 11205 #define rx_x4_status5_ltxsm_state_cl82_TX_HIG_END 64 11206 #define rx_x4_status5_ltxsm_state_cl82_TX_HIG_START 32 11207 #define rx_x4_status5_ltxsm_state_cl82_TX_E 16 11208 #define rx_x4_status5_ltxsm_state_cl82_TX_T 8 11209 #define rx_x4_status5_ltxsm_state_cl82_TX_D 4 11210 #define rx_x4_status5_ltxsm_state_cl82_TX_C 2 11211 #define rx_x4_status5_ltxsm_state_cl82_TX_INIT 1 11212 11213 /**************************************************************************** 11214 * Enums: rx_x4_status5_r_type_coded_cl82 11215 */ 11216 #define rx_x4_status5_r_type_coded_cl82_R_TYPE_B1 32 11217 #define rx_x4_status5_r_type_coded_cl82_R_TYPE_C 16 11218 #define rx_x4_status5_r_type_coded_cl82_R_TYPE_S 8 11219 #define rx_x4_status5_r_type_coded_cl82_R_TYPE_T 4 11220 #define rx_x4_status5_r_type_coded_cl82_R_TYPE_D 2 11221 #define rx_x4_status5_r_type_coded_cl82_R_TYPE_E 1 11222 11223 /**************************************************************************** 11224 * Enums: rx_x4_status5_rxsm_state_cl82 11225 */ 11226 #define rx_x4_status5_rxsm_state_cl82_RX_HIG_END 64 11227 #define rx_x4_status5_rxsm_state_cl82_RX_HIG_START 32 11228 #define rx_x4_status5_rxsm_state_cl82_RX_E 16 11229 #define rx_x4_status5_rxsm_state_cl82_RX_T 8 11230 #define rx_x4_status5_rxsm_state_cl82_RX_D 4 11231 #define rx_x4_status5_rxsm_state_cl82_RX_C 2 11232 #define rx_x4_status5_rxsm_state_cl82_RX_INIT 1 11233 11234 /**************************************************************************** 11235 * Enums: rx_x4_status5_deskew_state 11236 */ 11237 #define rx_x4_status5_deskew_state_ALIGN_ACQUIRED 2 11238 #define rx_x4_status5_deskew_state_LOSS_OF_ALIGNMENT 1 11239 11240 /**************************************************************************** 11241 * Enums: rx_x4_status5_os_mode_enum 11242 */ 11243 #define rx_x4_status5_os_mode_enum_OS_MODE_1 0 11244 #define rx_x4_status5_os_mode_enum_OS_MODE_2 1 11245 #define rx_x4_status5_os_mode_enum_OS_MODE_4 2 11246 #define rx_x4_status5_os_mode_enum_OS_MODE_16p5 8 11247 #define rx_x4_status5_os_mode_enum_OS_MODE_20p625 12 11248 11249 /**************************************************************************** 11250 * Enums: rx_x4_status5_scr_modes 11251 */ 11252 #define rx_x4_status5_scr_modes_T_SCR_MODE_BYPASS 0 11253 #define rx_x4_status5_scr_modes_T_SCR_MODE_CL49 1 11254 #define rx_x4_status5_scr_modes_T_SCR_MODE_40G_2_LANE 2 11255 #define rx_x4_status5_scr_modes_T_SCR_MODE_100G 3 11256 #define rx_x4_status5_scr_modes_T_SCR_MODE_20G 4 11257 #define rx_x4_status5_scr_modes_T_SCR_MODE_40G_4_LANE 5 11258 11259 /**************************************************************************** 11260 * Enums: rx_x4_status5_descr_modes 11261 */ 11262 #define rx_x4_status5_descr_modes_R_DESCR_MODE_BYPASS 0 11263 #define rx_x4_status5_descr_modes_R_DESCR_MODE_CL49 1 11264 #define rx_x4_status5_descr_modes_R_DESCR_MODE_CL82 2 11265 11266 /**************************************************************************** 11267 * Enums: rx_x4_status5_r_dec_tl_mode 11268 */ 11269 #define rx_x4_status5_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 11270 #define rx_x4_status5_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 11271 #define rx_x4_status5_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 11272 11273 /**************************************************************************** 11274 * Enums: rx_x4_status5_r_dec_fsm_mode 11275 */ 11276 #define rx_x4_status5_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 11277 #define rx_x4_status5_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 11278 #define rx_x4_status5_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 11279 11280 /**************************************************************************** 11281 * Enums: rx_x4_status5_r_deskew_mode 11282 */ 11283 #define rx_x4_status5_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 11284 #define rx_x4_status5_r_deskew_mode_R_DESKEW_MODE_20G 1 11285 #define rx_x4_status5_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 11286 #define rx_x4_status5_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 11287 #define rx_x4_status5_r_deskew_mode_R_DESKEW_MODE_100G 4 11288 #define rx_x4_status5_r_deskew_mode_R_DESKEW_MODE_CL49 5 11289 #define rx_x4_status5_r_deskew_mode_R_DESKEW_MODE_CL91_QUAD 6 11290 #define rx_x4_status5_r_deskew_mode_R_DESKEW_MODE_CL91_SINGLE_BRCM 7 11291 #define rx_x4_status5_r_deskew_mode_R_DESKEW_MODE_CL91_DUAL_BRCM 8 11292 #define rx_x4_status5_r_deskew_mode_R_DESKEW_MODE_CL91_FC 9 11293 11294 /**************************************************************************** 11295 * Enums: rx_x4_status5_bs_dist_modes 11296 */ 11297 #define rx_x4_status5_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 11298 #define rx_x4_status5_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 11299 #define rx_x4_status5_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 11300 #define rx_x4_status5_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 11301 11302 /**************************************************************************** 11303 * Enums: rx_x4_status5_cl49_t_type 11304 */ 11305 #define rx_x4_status5_cl49_t_type_BAD_T_TYPE 15 11306 #define rx_x4_status5_cl49_t_type_T_TYPE_B0 11 11307 #define rx_x4_status5_cl49_t_type_T_TYPE_OB 10 11308 #define rx_x4_status5_cl49_t_type_T_TYPE_B1 9 11309 #define rx_x4_status5_cl49_t_type_T_TYPE_DB 8 11310 #define rx_x4_status5_cl49_t_type_T_TYPE_FC 7 11311 #define rx_x4_status5_cl49_t_type_T_TYPE_TB 6 11312 #define rx_x4_status5_cl49_t_type_T_TYPE_LI 5 11313 #define rx_x4_status5_cl49_t_type_T_TYPE_C 4 11314 #define rx_x4_status5_cl49_t_type_T_TYPE_S 3 11315 #define rx_x4_status5_cl49_t_type_T_TYPE_T 2 11316 #define rx_x4_status5_cl49_t_type_T_TYPE_D 1 11317 #define rx_x4_status5_cl49_t_type_T_TYPE_E 0 11318 11319 /**************************************************************************** 11320 * Enums: rx_x4_status5_cl49_txsm_states 11321 */ 11322 #define rx_x4_status5_cl49_txsm_states_TX_HIG_END 7 11323 #define rx_x4_status5_cl49_txsm_states_TX_HIG_START 6 11324 #define rx_x4_status5_cl49_txsm_states_TX_LI 5 11325 #define rx_x4_status5_cl49_txsm_states_TX_E 4 11326 #define rx_x4_status5_cl49_txsm_states_TX_T 3 11327 #define rx_x4_status5_cl49_txsm_states_TX_D 2 11328 #define rx_x4_status5_cl49_txsm_states_TX_C 1 11329 #define rx_x4_status5_cl49_txsm_states_TX_INIT 0 11330 11331 /**************************************************************************** 11332 * Enums: rx_x4_status5_cl49_ltxsm_states 11333 */ 11334 #define rx_x4_status5_cl49_ltxsm_states_TX_HIG_END 128 11335 #define rx_x4_status5_cl49_ltxsm_states_TX_HIG_START 64 11336 #define rx_x4_status5_cl49_ltxsm_states_TX_LI 32 11337 #define rx_x4_status5_cl49_ltxsm_states_TX_E 16 11338 #define rx_x4_status5_cl49_ltxsm_states_TX_T 8 11339 #define rx_x4_status5_cl49_ltxsm_states_TX_D 4 11340 #define rx_x4_status5_cl49_ltxsm_states_TX_C 2 11341 #define rx_x4_status5_cl49_ltxsm_states_TX_INIT 1 11342 11343 /**************************************************************************** 11344 * Enums: rx_x4_status5_burst_error_mode 11345 */ 11346 #define rx_x4_status5_burst_error_mode_BURST_ERROR_11_BITS 0 11347 #define rx_x4_status5_burst_error_mode_BURST_ERROR_16_BITS 1 11348 #define rx_x4_status5_burst_error_mode_BURST_ERROR_17_BITS 2 11349 #define rx_x4_status5_burst_error_mode_BURST_ERROR_18_BITS 3 11350 #define rx_x4_status5_burst_error_mode_BURST_ERROR_19_BITS 4 11351 #define rx_x4_status5_burst_error_mode_BURST_ERROR_20_BITS 5 11352 #define rx_x4_status5_burst_error_mode_BURST_ERROR_21_BITS 6 11353 #define rx_x4_status5_burst_error_mode_BURST_ERROR_22_BITS 7 11354 #define rx_x4_status5_burst_error_mode_BURST_ERROR_23_BITS 8 11355 #define rx_x4_status5_burst_error_mode_BURST_ERROR_24_BITS 9 11356 #define rx_x4_status5_burst_error_mode_BURST_ERROR_25_BITS 10 11357 #define rx_x4_status5_burst_error_mode_BURST_ERROR_26_BITS 11 11358 #define rx_x4_status5_burst_error_mode_BURST_ERROR_27_BITS 12 11359 #define rx_x4_status5_burst_error_mode_BURST_ERROR_28_BITS 13 11360 #define rx_x4_status5_burst_error_mode_BURST_ERROR_29_BITS 14 11361 #define rx_x4_status5_burst_error_mode_BURST_ERROR_30_BITS 15 11362 #define rx_x4_status5_burst_error_mode_BURST_ERROR_31_BITS 16 11363 #define rx_x4_status5_burst_error_mode_BURST_ERROR_32_BITS 17 11364 #define rx_x4_status5_burst_error_mode_BURST_ERROR_33_BITS 18 11365 #define rx_x4_status5_burst_error_mode_BURST_ERROR_34_BITS 19 11366 #define rx_x4_status5_burst_error_mode_BURST_ERROR_35_BITS 20 11367 #define rx_x4_status5_burst_error_mode_BURST_ERROR_36_BITS 21 11368 #define rx_x4_status5_burst_error_mode_BURST_ERROR_37_BITS 22 11369 #define rx_x4_status5_burst_error_mode_BURST_ERROR_38_BITS 23 11370 #define rx_x4_status5_burst_error_mode_BURST_ERROR_39_BITS 24 11371 #define rx_x4_status5_burst_error_mode_BURST_ERROR_40_BITS 25 11372 #define rx_x4_status5_burst_error_mode_BURST_ERROR_41_BITS 26 11373 11374 /**************************************************************************** 11375 * Enums: rx_x4_status5_bermon_state 11376 */ 11377 #define rx_x4_status5_bermon_state_HI_BER 4 11378 #define rx_x4_status5_bermon_state_GOOD_BER 3 11379 #define rx_x4_status5_bermon_state_BER_TEST_SH 2 11380 #define rx_x4_status5_bermon_state_START_TIMER 1 11381 #define rx_x4_status5_bermon_state_BER_MT_INIT 0 11382 11383 /**************************************************************************** 11384 * Enums: rx_x4_status5_rxsm_state_cl49 11385 */ 11386 #define rx_x4_status5_rxsm_state_cl49_RX_HIG_END 128 11387 #define rx_x4_status5_rxsm_state_cl49_RX_HIG_START 64 11388 #define rx_x4_status5_rxsm_state_cl49_RX_LI 32 11389 #define rx_x4_status5_rxsm_state_cl49_RX_E 16 11390 #define rx_x4_status5_rxsm_state_cl49_RX_T 8 11391 #define rx_x4_status5_rxsm_state_cl49_RX_D 4 11392 #define rx_x4_status5_rxsm_state_cl49_RX_C 2 11393 #define rx_x4_status5_rxsm_state_cl49_RX_INIT 1 11394 11395 /**************************************************************************** 11396 * Enums: rx_x4_status5_r_type 11397 */ 11398 #define rx_x4_status5_r_type_BAD_R_TYPE 15 11399 #define rx_x4_status5_r_type_R_TYPE_B0 11 11400 #define rx_x4_status5_r_type_R_TYPE_OB 10 11401 #define rx_x4_status5_r_type_R_TYPE_B1 9 11402 #define rx_x4_status5_r_type_R_TYPE_DB 8 11403 #define rx_x4_status5_r_type_R_TYPE_FC 7 11404 #define rx_x4_status5_r_type_R_TYPE_TB 6 11405 #define rx_x4_status5_r_type_R_TYPE_LI 5 11406 #define rx_x4_status5_r_type_R_TYPE_C 4 11407 #define rx_x4_status5_r_type_R_TYPE_S 3 11408 #define rx_x4_status5_r_type_R_TYPE_T 2 11409 #define rx_x4_status5_r_type_R_TYPE_D 1 11410 #define rx_x4_status5_r_type_R_TYPE_E 0 11411 11412 /**************************************************************************** 11413 * Enums: rx_x4_status5_am_lock_state 11414 */ 11415 #define rx_x4_status5_am_lock_state_INVALID_AM 512 11416 #define rx_x4_status5_am_lock_state_GOOD_AM 256 11417 #define rx_x4_status5_am_lock_state_COMP_AM 128 11418 #define rx_x4_status5_am_lock_state_TIMER_2 64 11419 #define rx_x4_status5_am_lock_state_AM_2_GOOD 32 11420 #define rx_x4_status5_am_lock_state_COMP_2ND 16 11421 #define rx_x4_status5_am_lock_state_TIMER_1 8 11422 #define rx_x4_status5_am_lock_state_FIND_1ST 4 11423 #define rx_x4_status5_am_lock_state_AM_RESET_CNT 2 11424 #define rx_x4_status5_am_lock_state_AM_LOCK_INIT 1 11425 11426 /**************************************************************************** 11427 * Enums: rx_x4_status5_msg_selector 11428 */ 11429 #define rx_x4_status5_msg_selector_RESERVED 0 11430 #define rx_x4_status5_msg_selector_VALUE_802p3 1 11431 #define rx_x4_status5_msg_selector_VALUE_802p9 2 11432 #define rx_x4_status5_msg_selector_VALUE_802p5 3 11433 #define rx_x4_status5_msg_selector_VALUE_1394 4 11434 11435 /**************************************************************************** 11436 * Enums: rx_x4_status5_synce_enum 11437 */ 11438 #define rx_x4_status5_synce_enum_SYNCE_NO_DIV 0 11439 #define rx_x4_status5_synce_enum_SYNCE_DIV_7 1 11440 #define rx_x4_status5_synce_enum_SYNCE_DIV_11 2 11441 11442 /**************************************************************************** 11443 * Enums: rx_x4_status5_synce_enum_stage0 11444 */ 11445 #define rx_x4_status5_synce_enum_stage0_SYNCE_NO_DIV 0 11446 #define rx_x4_status5_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 11447 #define rx_x4_status5_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 11448 11449 /**************************************************************************** 11450 * Enums: rx_x4_status5_cl91_sync_state 11451 */ 11452 #define rx_x4_status5_cl91_sync_state_FIND_1ST 0 11453 #define rx_x4_status5_cl91_sync_state_COUNT_NEXT 1 11454 #define rx_x4_status5_cl91_sync_state_COMP_2ND 2 11455 #define rx_x4_status5_cl91_sync_state_TWO_GOOD 3 11456 11457 /**************************************************************************** 11458 * Enums: rx_x4_status5_cl91_algn_state 11459 */ 11460 #define rx_x4_status5_cl91_algn_state_LOSS_OF_ALIGNMENT 0 11461 #define rx_x4_status5_cl91_algn_state_DESKEW 1 11462 #define rx_x4_status5_cl91_algn_state_DESKEW_FAIL 2 11463 #define rx_x4_status5_cl91_algn_state_ALIGN_ACQUIRED 3 11464 #define rx_x4_status5_cl91_algn_state_CW_GOOD 4 11465 #define rx_x4_status5_cl91_algn_state_CW_BAD 5 11466 #define rx_x4_status5_cl91_algn_state_THREE_BAD 6 11467 11468 /**************************************************************************** 11469 * Enums: rx_x4_status5_fec_sel_override 11470 */ 11471 #define rx_x4_status5_fec_sel_override_NO_OVERRIDE 0 11472 #define rx_x4_status5_fec_sel_override_NO_FEC 1 11473 #define rx_x4_status5_fec_sel_override_FEC_CL74 2 11474 #define rx_x4_status5_fec_sel_override_FEC_CL91 3 11475 11476 /**************************************************************************** 11477 * Enums: rx_x4_status5_cl91_blksync_mode 11478 */ 11479 #define rx_x4_status5_cl91_blksync_mode_R_BLKSYNC_NO_CL91_FEC 0 11480 #define rx_x4_status5_cl91_blksync_mode_R_BLKSYNC_CL91_QUAD_LANE_FEC 1 11481 #define rx_x4_status5_cl91_blksync_mode_R_BLKSYNC_CL91_DUAL_LANE_FEC 2 11482 #define rx_x4_status5_cl91_blksync_mode_R_BLKSYNC_CL91_SINGLE_LANE_FEC 3 11483 #define rx_x4_status5_cl91_blksync_mode_R_BLKSYNC_CL91_FC_FEC 4 11484 11485 /**************************************************************************** 11486 * Enums: rx_x4_status5_r_merge_mode 11487 */ 11488 #define rx_x4_status5_r_merge_mode_R_MERGE_MODE_BYPASS 0 11489 #define rx_x4_status5_r_merge_mode_R_MERGE_MODE_CL91_FC 1 11490 #define rx_x4_status5_r_merge_mode_R_MERGE_MODE_CL91_SINGLE_LANE 2 11491 #define rx_x4_status5_r_merge_mode_R_MERGE_MODE_CL91_DUAL_LANE 3 11492 #define rx_x4_status5_r_merge_mode_R_MERGE_MODE_CL91_QUAD_LANE 4 11493 11494 /**************************************************************************** 11495 * Enums: rx_x4_status5_r_tc_mode 11496 */ 11497 #define rx_x4_status5_r_tc_mode_R_TC_MODE_SINGLE 0 11498 #define rx_x4_status5_r_tc_mode_R_TC_MODE_DUAL 1 11499 #define rx_x4_status5_r_tc_mode_R_TC_MODE_QUAD 2 11500 11501 /**************************************************************************** 11502 * Enums: rx_x4_status5_r_tc_out_mode 11503 */ 11504 #define rx_x4_status5_r_tc_out_mode_R_TC_OUT_MODE_SINGLE 0 11505 #define rx_x4_status5_r_tc_out_mode_R_TC_OUT_MODE_DUAL 1 11506 #define rx_x4_status5_r_tc_out_mode_R_TC_OUT_MODE_QUAD 2 11507 11508 /**************************************************************************** 11509 * Enums: rx_x4_status5_cl91_fec_mode 11510 */ 11511 #define rx_x4_status5_cl91_fec_mode_NO_CL91_FEC 0 11512 #define rx_x4_status5_cl91_fec_mode_CL91_SINGLE_LANE_FC 1 11513 #define rx_x4_status5_cl91_fec_mode_CL91_SINGLE_LANE_BRCM_PROP 2 11514 #define rx_x4_status5_cl91_fec_mode_CL91_DUAL_LANE_BRCM_PROP 3 11515 #define rx_x4_status5_cl91_fec_mode_CL91_QUAD_LANE 4 11516 #define rx_x4_status5_cl91_fec_mode_IEEE_25G_CL91_SINGLE_LANE 5 11517 11518 /**************************************************************************** 11519 * Enums: rx_x4_status5_am_spacing_mul 11520 */ 11521 #define rx_x4_status5_am_spacing_mul_AM_SPACING_MUL_2 0 11522 #define rx_x4_status5_am_spacing_mul_AM_SPACING_MUL_4 1 11523 #define rx_x4_status5_am_spacing_mul_AM_SPACING_MUL_5 2 11524 #define rx_x4_status5_am_spacing_mul_AM_SPACING_MUL_20 3 11525 11526 /**************************************************************************** 11527 * Enums: sc_x1_speed_override0_cl36TxEEEStates_l 11528 */ 11529 #define sc_x1_speed_override0_cl36TxEEEStates_l_TX_REFRESH 8 11530 #define sc_x1_speed_override0_cl36TxEEEStates_l_TX_QUIET 4 11531 #define sc_x1_speed_override0_cl36TxEEEStates_l_TX_SLEEP 2 11532 #define sc_x1_speed_override0_cl36TxEEEStates_l_TX_ACTIVE 1 11533 11534 /**************************************************************************** 11535 * Enums: sc_x1_speed_override0_cl36TxEEEStates_c 11536 */ 11537 #define sc_x1_speed_override0_cl36TxEEEStates_c_TX_REFRESH 3 11538 #define sc_x1_speed_override0_cl36TxEEEStates_c_TX_QUIET 2 11539 #define sc_x1_speed_override0_cl36TxEEEStates_c_TX_SLEEP 1 11540 #define sc_x1_speed_override0_cl36TxEEEStates_c_TX_ACTIVE 0 11541 11542 /**************************************************************************** 11543 * Enums: sc_x1_speed_override0_cl49TxEEEStates_l 11544 */ 11545 #define sc_x1_speed_override0_cl49TxEEEStates_l_SCR_RESET_2 64 11546 #define sc_x1_speed_override0_cl49TxEEEStates_l_SCR_RESET_1 32 11547 #define sc_x1_speed_override0_cl49TxEEEStates_l_TX_WAKE 16 11548 #define sc_x1_speed_override0_cl49TxEEEStates_l_TX_REFRESH 8 11549 #define sc_x1_speed_override0_cl49TxEEEStates_l_TX_QUIET 4 11550 #define sc_x1_speed_override0_cl49TxEEEStates_l_TX_SLEEP 2 11551 #define sc_x1_speed_override0_cl49TxEEEStates_l_TX_ACTIVE 1 11552 11553 /**************************************************************************** 11554 * Enums: sc_x1_speed_override0_fec_req_enum 11555 */ 11556 #define sc_x1_speed_override0_fec_req_enum_FEC_not_supported 0 11557 #define sc_x1_speed_override0_fec_req_enum_FEC_supported_but_not_requested 1 11558 #define sc_x1_speed_override0_fec_req_enum_invalid_setting 2 11559 #define sc_x1_speed_override0_fec_req_enum_FEC_supported_and_requested 3 11560 11561 /**************************************************************************** 11562 * Enums: sc_x1_speed_override0_cl73_pause_enum 11563 */ 11564 #define sc_x1_speed_override0_cl73_pause_enum_No_PAUSE_ability 0 11565 #define sc_x1_speed_override0_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 11566 #define sc_x1_speed_override0_cl73_pause_enum_Symmetric_PAUSE_ability 1 11567 #define sc_x1_speed_override0_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 11568 11569 /**************************************************************************** 11570 * Enums: sc_x1_speed_override0_cl49TxEEEStates_c 11571 */ 11572 #define sc_x1_speed_override0_cl49TxEEEStates_c_SCR_RESET_2 6 11573 #define sc_x1_speed_override0_cl49TxEEEStates_c_SCR_RESET_1 5 11574 #define sc_x1_speed_override0_cl49TxEEEStates_c_TX_WAKE 4 11575 #define sc_x1_speed_override0_cl49TxEEEStates_c_TX_REFRESH 3 11576 #define sc_x1_speed_override0_cl49TxEEEStates_c_TX_QUIET 2 11577 #define sc_x1_speed_override0_cl49TxEEEStates_c_TX_SLEEP 1 11578 #define sc_x1_speed_override0_cl49TxEEEStates_c_TX_ACTIVE 0 11579 11580 /**************************************************************************** 11581 * Enums: sc_x1_speed_override0_cl36RxEEEStates_l 11582 */ 11583 #define sc_x1_speed_override0_cl36RxEEEStates_l_RX_LINK_FAIL 32 11584 #define sc_x1_speed_override0_cl36RxEEEStates_l_RX_WTF 16 11585 #define sc_x1_speed_override0_cl36RxEEEStates_l_RX_WAKE 8 11586 #define sc_x1_speed_override0_cl36RxEEEStates_l_RX_QUIET 4 11587 #define sc_x1_speed_override0_cl36RxEEEStates_l_RX_SLEEP 2 11588 #define sc_x1_speed_override0_cl36RxEEEStates_l_RX_ACTIVE 1 11589 11590 /**************************************************************************** 11591 * Enums: sc_x1_speed_override0_cl36RxEEEStates_c 11592 */ 11593 #define sc_x1_speed_override0_cl36RxEEEStates_c_RX_LINK_FAIL 5 11594 #define sc_x1_speed_override0_cl36RxEEEStates_c_RX_WTF 4 11595 #define sc_x1_speed_override0_cl36RxEEEStates_c_RX_WAKE 3 11596 #define sc_x1_speed_override0_cl36RxEEEStates_c_RX_QUIET 2 11597 #define sc_x1_speed_override0_cl36RxEEEStates_c_RX_SLEEP 1 11598 #define sc_x1_speed_override0_cl36RxEEEStates_c_RX_ACTIVE 0 11599 11600 /**************************************************************************** 11601 * Enums: sc_x1_speed_override0_cl49RxEEEStates_l 11602 */ 11603 #define sc_x1_speed_override0_cl49RxEEEStates_l_RX_LINK_FAIL 32 11604 #define sc_x1_speed_override0_cl49RxEEEStates_l_RX_WTF 16 11605 #define sc_x1_speed_override0_cl49RxEEEStates_l_RX_WAKE 8 11606 #define sc_x1_speed_override0_cl49RxEEEStates_l_RX_QUIET 4 11607 #define sc_x1_speed_override0_cl49RxEEEStates_l_RX_SLEEP 2 11608 #define sc_x1_speed_override0_cl49RxEEEStates_l_RX_ACTIVE 1 11609 11610 /**************************************************************************** 11611 * Enums: sc_x1_speed_override0_cl49RxEEEStates_c 11612 */ 11613 #define sc_x1_speed_override0_cl49RxEEEStates_c_RX_LINK_FAIL 5 11614 #define sc_x1_speed_override0_cl49RxEEEStates_c_RX_WTF 4 11615 #define sc_x1_speed_override0_cl49RxEEEStates_c_RX_WAKE 3 11616 #define sc_x1_speed_override0_cl49RxEEEStates_c_RX_QUIET 2 11617 #define sc_x1_speed_override0_cl49RxEEEStates_c_RX_SLEEP 1 11618 #define sc_x1_speed_override0_cl49RxEEEStates_c_RX_ACTIVE 0 11619 11620 /**************************************************************************** 11621 * Enums: sc_x1_speed_override0_cl48TxEEEStates_l 11622 */ 11623 #define sc_x1_speed_override0_cl48TxEEEStates_l_TX_REFRESH 8 11624 #define sc_x1_speed_override0_cl48TxEEEStates_l_TX_QUIET 4 11625 #define sc_x1_speed_override0_cl48TxEEEStates_l_TX_SLEEP 2 11626 #define sc_x1_speed_override0_cl48TxEEEStates_l_TX_ACTIVE 1 11627 11628 /**************************************************************************** 11629 * Enums: sc_x1_speed_override0_cl48TxEEEStates_c 11630 */ 11631 #define sc_x1_speed_override0_cl48TxEEEStates_c_TX_REFRESH 3 11632 #define sc_x1_speed_override0_cl48TxEEEStates_c_TX_QUIET 2 11633 #define sc_x1_speed_override0_cl48TxEEEStates_c_TX_SLEEP 1 11634 #define sc_x1_speed_override0_cl48TxEEEStates_c_TX_ACTIVE 0 11635 11636 /**************************************************************************** 11637 * Enums: sc_x1_speed_override0_cl48RxEEEStates_l 11638 */ 11639 #define sc_x1_speed_override0_cl48RxEEEStates_l_RX_LINK_FAIL 32 11640 #define sc_x1_speed_override0_cl48RxEEEStates_l_RX_WAKE 16 11641 #define sc_x1_speed_override0_cl48RxEEEStates_l_RX_QUIET 8 11642 #define sc_x1_speed_override0_cl48RxEEEStates_l_RX_DEACT 4 11643 #define sc_x1_speed_override0_cl48RxEEEStates_l_RX_SLEEP 2 11644 #define sc_x1_speed_override0_cl48RxEEEStates_l_RX_ACTIVE 1 11645 11646 /**************************************************************************** 11647 * Enums: sc_x1_speed_override0_cl48RxEEEStates_c 11648 */ 11649 #define sc_x1_speed_override0_cl48RxEEEStates_c_RX_LINK_FAIL 5 11650 #define sc_x1_speed_override0_cl48RxEEEStates_c_RX_WAKE 4 11651 #define sc_x1_speed_override0_cl48RxEEEStates_c_RX_QUIET 3 11652 #define sc_x1_speed_override0_cl48RxEEEStates_c_RX_DEACT 2 11653 #define sc_x1_speed_override0_cl48RxEEEStates_c_RX_SLEEP 1 11654 #define sc_x1_speed_override0_cl48RxEEEStates_c_RX_ACTIVE 0 11655 11656 /**************************************************************************** 11657 * Enums: sc_x1_speed_override0_IQP_Options 11658 */ 11659 #define sc_x1_speed_override0_IQP_Options_i50uA 0 11660 #define sc_x1_speed_override0_IQP_Options_i100uA 1 11661 #define sc_x1_speed_override0_IQP_Options_i150uA 2 11662 #define sc_x1_speed_override0_IQP_Options_i200uA 3 11663 #define sc_x1_speed_override0_IQP_Options_i250uA 4 11664 #define sc_x1_speed_override0_IQP_Options_i300uA 5 11665 #define sc_x1_speed_override0_IQP_Options_i350uA 6 11666 #define sc_x1_speed_override0_IQP_Options_i400uA 7 11667 #define sc_x1_speed_override0_IQP_Options_i450uA 8 11668 #define sc_x1_speed_override0_IQP_Options_i500uA 9 11669 #define sc_x1_speed_override0_IQP_Options_i550uA 10 11670 #define sc_x1_speed_override0_IQP_Options_i600uA 11 11671 #define sc_x1_speed_override0_IQP_Options_i650uA 12 11672 #define sc_x1_speed_override0_IQP_Options_i700uA 13 11673 #define sc_x1_speed_override0_IQP_Options_i750uA 14 11674 #define sc_x1_speed_override0_IQP_Options_i800uA 15 11675 11676 /**************************************************************************** 11677 * Enums: sc_x1_speed_override0_IDriver_Options 11678 */ 11679 #define sc_x1_speed_override0_IDriver_Options_v680mV 0 11680 #define sc_x1_speed_override0_IDriver_Options_v730mV 1 11681 #define sc_x1_speed_override0_IDriver_Options_v780mV 2 11682 #define sc_x1_speed_override0_IDriver_Options_v830mV 3 11683 #define sc_x1_speed_override0_IDriver_Options_v880mV 4 11684 #define sc_x1_speed_override0_IDriver_Options_v930mV 5 11685 #define sc_x1_speed_override0_IDriver_Options_v980mV 6 11686 #define sc_x1_speed_override0_IDriver_Options_v1010mV 7 11687 #define sc_x1_speed_override0_IDriver_Options_v1040mV 8 11688 #define sc_x1_speed_override0_IDriver_Options_v1060mV 9 11689 #define sc_x1_speed_override0_IDriver_Options_v1070mV 10 11690 #define sc_x1_speed_override0_IDriver_Options_v1080mV 11 11691 #define sc_x1_speed_override0_IDriver_Options_v1085mV 12 11692 #define sc_x1_speed_override0_IDriver_Options_v1090mV 13 11693 #define sc_x1_speed_override0_IDriver_Options_v1095mV 14 11694 #define sc_x1_speed_override0_IDriver_Options_v1100mV 15 11695 11696 /**************************************************************************** 11697 * Enums: sc_x1_speed_override0_operationModes 11698 */ 11699 #define sc_x1_speed_override0_operationModes_XGXS 0 11700 #define sc_x1_speed_override0_operationModes_XGXG_nCC 1 11701 #define sc_x1_speed_override0_operationModes_Indlane_OS8 4 11702 #define sc_x1_speed_override0_operationModes_IndLane_OS5 5 11703 #define sc_x1_speed_override0_operationModes_PCI 7 11704 #define sc_x1_speed_override0_operationModes_XGXS_nLQ 8 11705 #define sc_x1_speed_override0_operationModes_XGXS_nLQnCC 9 11706 #define sc_x1_speed_override0_operationModes_PBypass 10 11707 #define sc_x1_speed_override0_operationModes_PBypass_nDSK 11 11708 #define sc_x1_speed_override0_operationModes_ComboCoreMode 12 11709 #define sc_x1_speed_override0_operationModes_Clocks_off 15 11710 11711 /**************************************************************************** 11712 * Enums: sc_x1_speed_override0_actualSpeeds 11713 */ 11714 #define sc_x1_speed_override0_actualSpeeds_dr_10M 0 11715 #define sc_x1_speed_override0_actualSpeeds_dr_100M 1 11716 #define sc_x1_speed_override0_actualSpeeds_dr_1G 2 11717 #define sc_x1_speed_override0_actualSpeeds_dr_2p5G 3 11718 #define sc_x1_speed_override0_actualSpeeds_dr_5G_X4 4 11719 #define sc_x1_speed_override0_actualSpeeds_dr_6G_X4 5 11720 #define sc_x1_speed_override0_actualSpeeds_dr_10G_HiG 6 11721 #define sc_x1_speed_override0_actualSpeeds_dr_10G_CX4 7 11722 #define sc_x1_speed_override0_actualSpeeds_dr_12G_HiG 8 11723 #define sc_x1_speed_override0_actualSpeeds_dr_12p5G_X4 9 11724 #define sc_x1_speed_override0_actualSpeeds_dr_13G_X4 10 11725 #define sc_x1_speed_override0_actualSpeeds_dr_15G_X4 11 11726 #define sc_x1_speed_override0_actualSpeeds_dr_16G_X4 12 11727 #define sc_x1_speed_override0_actualSpeeds_dr_1G_KX 13 11728 #define sc_x1_speed_override0_actualSpeeds_dr_10G_KX4 14 11729 #define sc_x1_speed_override0_actualSpeeds_dr_10G_KR 15 11730 #define sc_x1_speed_override0_actualSpeeds_dr_5G 16 11731 #define sc_x1_speed_override0_actualSpeeds_dr_6p4G 17 11732 #define sc_x1_speed_override0_actualSpeeds_dr_20G_X4 18 11733 #define sc_x1_speed_override0_actualSpeeds_dr_21G_X4 19 11734 #define sc_x1_speed_override0_actualSpeeds_dr_25G_X4 20 11735 #define sc_x1_speed_override0_actualSpeeds_dr_10G_HiG_DXGXS 21 11736 #define sc_x1_speed_override0_actualSpeeds_dr_10G_DXGXS 22 11737 #define sc_x1_speed_override0_actualSpeeds_dr_10p5G_HiG_DXGXS 23 11738 #define sc_x1_speed_override0_actualSpeeds_dr_10p5G_DXGXS 24 11739 #define sc_x1_speed_override0_actualSpeeds_dr_12p773G_HiG_DXGXS 25 11740 #define sc_x1_speed_override0_actualSpeeds_dr_12p773G_DXGXS 26 11741 #define sc_x1_speed_override0_actualSpeeds_dr_10G_XFI 27 11742 #define sc_x1_speed_override0_actualSpeeds_dr_40G 28 11743 #define sc_x1_speed_override0_actualSpeeds_dr_20G_HiG_DXGXS 29 11744 #define sc_x1_speed_override0_actualSpeeds_dr_20G_DXGXS 30 11745 #define sc_x1_speed_override0_actualSpeeds_dr_10G_SFI 31 11746 #define sc_x1_speed_override0_actualSpeeds_dr_31p5G 32 11747 #define sc_x1_speed_override0_actualSpeeds_dr_32p7G 33 11748 #define sc_x1_speed_override0_actualSpeeds_dr_20G_SCR 34 11749 #define sc_x1_speed_override0_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 11750 #define sc_x1_speed_override0_actualSpeeds_dr_10G_DXGXS_SCR 36 11751 #define sc_x1_speed_override0_actualSpeeds_dr_12G_R2 37 11752 #define sc_x1_speed_override0_actualSpeeds_dr_10G_X2 38 11753 #define sc_x1_speed_override0_actualSpeeds_dr_40G_KR4 39 11754 #define sc_x1_speed_override0_actualSpeeds_dr_40G_CR4 40 11755 #define sc_x1_speed_override0_actualSpeeds_dr_100G_CR10 41 11756 #define sc_x1_speed_override0_actualSpeeds_dr_15p75G_DXGXS 44 11757 #define sc_x1_speed_override0_actualSpeeds_dr_20G_KR2 57 11758 #define sc_x1_speed_override0_actualSpeeds_dr_20G_CR2 58 11759 11760 /**************************************************************************** 11761 * Enums: sc_x1_speed_override0_actualSpeedsMisc1 11762 */ 11763 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_2500BRCM_X1 16 11764 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_5000BRCM_X4 17 11765 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_6000BRCM_X4 18 11766 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_10GHiGig_X4 19 11767 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_10GBASE_CX4 20 11768 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_12GHiGig_X4 21 11769 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 11770 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_13GHiGig_X4 23 11771 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_15GHiGig_X4 24 11772 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_16GHiGig_X4 25 11773 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_5000BRCM_X1 26 11774 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_6363BRCM_X1 27 11775 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_20GHiGig_X4 28 11776 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_21GHiGig_X4 29 11777 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 11778 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 11779 11780 /**************************************************************************** 11781 * Enums: sc_x1_speed_override0_IndLaneModes 11782 */ 11783 #define sc_x1_speed_override0_IndLaneModes_SWSDR_div2 0 11784 #define sc_x1_speed_override0_IndLaneModes_SWSDR_div1 1 11785 #define sc_x1_speed_override0_IndLaneModes_DWSDR_div2 2 11786 #define sc_x1_speed_override0_IndLaneModes_DWSDR_div1 3 11787 11788 /**************************************************************************** 11789 * Enums: sc_x1_speed_override0_prbsSelect 11790 */ 11791 #define sc_x1_speed_override0_prbsSelect_prbs7 0 11792 #define sc_x1_speed_override0_prbsSelect_prbs15 1 11793 #define sc_x1_speed_override0_prbsSelect_prbs23 2 11794 #define sc_x1_speed_override0_prbsSelect_prbs31 3 11795 11796 /**************************************************************************** 11797 * Enums: sc_x1_speed_override0_vcoDivider 11798 */ 11799 #define sc_x1_speed_override0_vcoDivider_div32 0 11800 #define sc_x1_speed_override0_vcoDivider_div36 1 11801 #define sc_x1_speed_override0_vcoDivider_div40 2 11802 #define sc_x1_speed_override0_vcoDivider_div42 3 11803 #define sc_x1_speed_override0_vcoDivider_div48 4 11804 #define sc_x1_speed_override0_vcoDivider_div50 5 11805 #define sc_x1_speed_override0_vcoDivider_div52 6 11806 #define sc_x1_speed_override0_vcoDivider_div54 7 11807 #define sc_x1_speed_override0_vcoDivider_div60 8 11808 #define sc_x1_speed_override0_vcoDivider_div64 9 11809 #define sc_x1_speed_override0_vcoDivider_div66 10 11810 #define sc_x1_speed_override0_vcoDivider_div68 11 11811 #define sc_x1_speed_override0_vcoDivider_div70 12 11812 #define sc_x1_speed_override0_vcoDivider_div80 13 11813 #define sc_x1_speed_override0_vcoDivider_div92 14 11814 #define sc_x1_speed_override0_vcoDivider_div100 15 11815 11816 /**************************************************************************** 11817 * Enums: sc_x1_speed_override0_refClkSelect 11818 */ 11819 #define sc_x1_speed_override0_refClkSelect_clk_25MHz 0 11820 #define sc_x1_speed_override0_refClkSelect_clk_100MHz 1 11821 #define sc_x1_speed_override0_refClkSelect_clk_125MHz 2 11822 #define sc_x1_speed_override0_refClkSelect_clk_156p25MHz 3 11823 #define sc_x1_speed_override0_refClkSelect_clk_187p5MHz 4 11824 #define sc_x1_speed_override0_refClkSelect_clk_161p25Mhz 5 11825 #define sc_x1_speed_override0_refClkSelect_clk_50Mhz 6 11826 #define sc_x1_speed_override0_refClkSelect_clk_106p25Mhz 7 11827 11828 /**************************************************************************** 11829 * Enums: sc_x1_speed_override0_aerMMDdevTypeSelect 11830 */ 11831 #define sc_x1_speed_override0_aerMMDdevTypeSelect_combo_core 0 11832 #define sc_x1_speed_override0_aerMMDdevTypeSelect_PMA_PMD 1 11833 #define sc_x1_speed_override0_aerMMDdevTypeSelect_PCS 3 11834 #define sc_x1_speed_override0_aerMMDdevTypeSelect_PHY 4 11835 #define sc_x1_speed_override0_aerMMDdevTypeSelect_DTE 5 11836 #define sc_x1_speed_override0_aerMMDdevTypeSelect_CL73_AN 7 11837 11838 /**************************************************************************** 11839 * Enums: sc_x1_speed_override0_aerMMDportSelect 11840 */ 11841 #define sc_x1_speed_override0_aerMMDportSelect_ln0 0 11842 #define sc_x1_speed_override0_aerMMDportSelect_ln1 1 11843 #define sc_x1_speed_override0_aerMMDportSelect_ln2 2 11844 #define sc_x1_speed_override0_aerMMDportSelect_ln3 3 11845 #define sc_x1_speed_override0_aerMMDportSelect_BCST_ln0_1_2_3 511 11846 #define sc_x1_speed_override0_aerMMDportSelect_BCST_ln0_1 512 11847 #define sc_x1_speed_override0_aerMMDportSelect_BCST_ln2_3 513 11848 11849 /**************************************************************************** 11850 * Enums: sc_x1_speed_override0_firmwareModeSelect 11851 */ 11852 #define sc_x1_speed_override0_firmwareModeSelect_DEFAULT 0 11853 #define sc_x1_speed_override0_firmwareModeSelect_SFP_OPT_LR 1 11854 #define sc_x1_speed_override0_firmwareModeSelect_SFP_DAC 2 11855 #define sc_x1_speed_override0_firmwareModeSelect_XLAUI 3 11856 #define sc_x1_speed_override0_firmwareModeSelect_LONG_CH_6G 4 11857 11858 /**************************************************************************** 11859 * Enums: sc_x1_speed_override0_tempIdxSelect 11860 */ 11861 #define sc_x1_speed_override0_tempIdxSelect_LTE__22p9C 15 11862 #define sc_x1_speed_override0_tempIdxSelect_LTE__12p6C 14 11863 #define sc_x1_speed_override0_tempIdxSelect_LTE__3p0C 13 11864 #define sc_x1_speed_override0_tempIdxSelect_LTE_6p7C 12 11865 #define sc_x1_speed_override0_tempIdxSelect_LTE_16p4C 11 11866 #define sc_x1_speed_override0_tempIdxSelect_LTE_26p6C 10 11867 #define sc_x1_speed_override0_tempIdxSelect_LTE_36p3C 9 11868 #define sc_x1_speed_override0_tempIdxSelect_LTE_46p0C 8 11869 #define sc_x1_speed_override0_tempIdxSelect_LTE_56p2C 7 11870 #define sc_x1_speed_override0_tempIdxSelect_LTE_65p9C 6 11871 #define sc_x1_speed_override0_tempIdxSelect_LTE_75p6C 5 11872 #define sc_x1_speed_override0_tempIdxSelect_LTE_85p3C 4 11873 #define sc_x1_speed_override0_tempIdxSelect_LTE_95p5C 3 11874 #define sc_x1_speed_override0_tempIdxSelect_LTE_105p2C 2 11875 #define sc_x1_speed_override0_tempIdxSelect_LTE_114p9C 1 11876 #define sc_x1_speed_override0_tempIdxSelect_LTE_125p1C 0 11877 11878 /**************************************************************************** 11879 * Enums: sc_x1_speed_override0_port_mode 11880 */ 11881 #define sc_x1_speed_override0_port_mode_QUAD_PORT 0 11882 #define sc_x1_speed_override0_port_mode_TRI_1_PORT 1 11883 #define sc_x1_speed_override0_port_mode_TRI_2_PORT 2 11884 #define sc_x1_speed_override0_port_mode_DUAL_PORT 3 11885 #define sc_x1_speed_override0_port_mode_SINGLE_PORT 4 11886 11887 /**************************************************************************** 11888 * Enums: sc_x1_speed_override0_rev_letter_enum 11889 */ 11890 #define sc_x1_speed_override0_rev_letter_enum_REV_A 0 11891 #define sc_x1_speed_override0_rev_letter_enum_REV_B 1 11892 #define sc_x1_speed_override0_rev_letter_enum_REV_C 2 11893 #define sc_x1_speed_override0_rev_letter_enum_REV_D 3 11894 11895 /**************************************************************************** 11896 * Enums: sc_x1_speed_override0_rev_number_enum 11897 */ 11898 #define sc_x1_speed_override0_rev_number_enum_REV_0 0 11899 #define sc_x1_speed_override0_rev_number_enum_REV_1 1 11900 #define sc_x1_speed_override0_rev_number_enum_REV_2 2 11901 #define sc_x1_speed_override0_rev_number_enum_REV_3 3 11902 #define sc_x1_speed_override0_rev_number_enum_REV_4 4 11903 #define sc_x1_speed_override0_rev_number_enum_REV_5 5 11904 #define sc_x1_speed_override0_rev_number_enum_REV_6 6 11905 #define sc_x1_speed_override0_rev_number_enum_REV_7 7 11906 11907 /**************************************************************************** 11908 * Enums: sc_x1_speed_override0_bonding_enum 11909 */ 11910 #define sc_x1_speed_override0_bonding_enum_WIRE_BOND 0 11911 #define sc_x1_speed_override0_bonding_enum_FLIP_CHIP 1 11912 11913 /**************************************************************************** 11914 * Enums: sc_x1_speed_override0_tech_process 11915 */ 11916 #define sc_x1_speed_override0_tech_process_PROCESS_90NM 0 11917 #define sc_x1_speed_override0_tech_process_PROCESS_65NM 1 11918 #define sc_x1_speed_override0_tech_process_PROCESS_40NM 2 11919 #define sc_x1_speed_override0_tech_process_PROCESS_28NM 3 11920 #define sc_x1_speed_override0_tech_process_PROCESS_16NM 4 11921 11922 /**************************************************************************** 11923 * Enums: sc_x1_speed_override0_model_num 11924 */ 11925 #define sc_x1_speed_override0_model_num_SERDES_CL73 0 11926 #define sc_x1_speed_override0_model_num_XGXS_16G 1 11927 #define sc_x1_speed_override0_model_num_HYPERCORE 2 11928 #define sc_x1_speed_override0_model_num_HYPERLITE 3 11929 #define sc_x1_speed_override0_model_num_PCIE_G2_PIPE 4 11930 #define sc_x1_speed_override0_model_num_SERDES_1p25GBd 5 11931 #define sc_x1_speed_override0_model_num_SATA2 6 11932 #define sc_x1_speed_override0_model_num_QSGMII 7 11933 #define sc_x1_speed_override0_model_num_XGXS10G 8 11934 #define sc_x1_speed_override0_model_num_WARPCORE 9 11935 #define sc_x1_speed_override0_model_num_XFICORE 10 11936 #define sc_x1_speed_override0_model_num_RXFI 11 11937 #define sc_x1_speed_override0_model_num_WARPLITE 12 11938 #define sc_x1_speed_override0_model_num_PENTACORE 13 11939 #define sc_x1_speed_override0_model_num_ESM 14 11940 #define sc_x1_speed_override0_model_num_QUAD_SGMII 15 11941 #define sc_x1_speed_override0_model_num_WARPCORE_3 16 11942 #define sc_x1_speed_override0_model_num_TSC 17 11943 #define sc_x1_speed_override0_model_num_TSC4E 18 11944 #define sc_x1_speed_override0_model_num_TSC12E 19 11945 #define sc_x1_speed_override0_model_num_TSC4F 20 11946 #define sc_x1_speed_override0_model_num_TSC4F_GEN2 21 11947 #define sc_x1_speed_override0_model_num_XGXS_CL73_90NM 29 11948 #define sc_x1_speed_override0_model_num_SERDES_CL73_90NM 30 11949 #define sc_x1_speed_override0_model_num_WARPCORE3 32 11950 #define sc_x1_speed_override0_model_num_WARPCORE4_TSC 33 11951 #define sc_x1_speed_override0_model_num_RXAUI 34 11952 11953 /**************************************************************************** 11954 * Enums: sc_x1_speed_override0_payload 11955 */ 11956 #define sc_x1_speed_override0_payload_REPEAT_2_BYTES 0 11957 #define sc_x1_speed_override0_payload_RAMPING 1 11958 #define sc_x1_speed_override0_payload_CL48_CRPAT 2 11959 #define sc_x1_speed_override0_payload_CL48_CJPAT 3 11960 #define sc_x1_speed_override0_payload_CL36_LONG_CRPAT 4 11961 #define sc_x1_speed_override0_payload_CL36_SHORT_CRPAT 5 11962 11963 /**************************************************************************** 11964 * Enums: sc_x1_speed_override0_sc 11965 */ 11966 #define sc_x1_speed_override0_sc_S_10G_CR1 0 11967 #define sc_x1_speed_override0_sc_S_10G_KR1 1 11968 #define sc_x1_speed_override0_sc_S_10G_X1 2 11969 #define sc_x1_speed_override0_sc_S_10G_HG2_CR1 4 11970 #define sc_x1_speed_override0_sc_S_10G_HG2_KR1 5 11971 #define sc_x1_speed_override0_sc_S_10G_HG2_X1 6 11972 #define sc_x1_speed_override0_sc_S_20G_CR1 8 11973 #define sc_x1_speed_override0_sc_S_20G_KR1 9 11974 #define sc_x1_speed_override0_sc_S_20G_X1 10 11975 #define sc_x1_speed_override0_sc_S_20G_HG2_CR1 12 11976 #define sc_x1_speed_override0_sc_S_20G_HG2_KR1 13 11977 #define sc_x1_speed_override0_sc_S_20G_HG2_X1 14 11978 #define sc_x1_speed_override0_sc_S_25G_CR1 16 11979 #define sc_x1_speed_override0_sc_S_25G_KR1 17 11980 #define sc_x1_speed_override0_sc_S_25G_X1 18 11981 #define sc_x1_speed_override0_sc_S_25G_HG2_CR1 20 11982 #define sc_x1_speed_override0_sc_S_25G_HG2_KR1 21 11983 #define sc_x1_speed_override0_sc_S_25G_HG2_X1 22 11984 #define sc_x1_speed_override0_sc_S_20G_CR2 24 11985 #define sc_x1_speed_override0_sc_S_20G_KR2 25 11986 #define sc_x1_speed_override0_sc_S_20G_X2 26 11987 #define sc_x1_speed_override0_sc_S_20G_HG2_CR2 28 11988 #define sc_x1_speed_override0_sc_S_20G_HG2_KR2 29 11989 #define sc_x1_speed_override0_sc_S_20G_HG2_X2 30 11990 #define sc_x1_speed_override0_sc_S_40G_CR2 32 11991 #define sc_x1_speed_override0_sc_S_40G_KR2 33 11992 #define sc_x1_speed_override0_sc_S_40G_X2 34 11993 #define sc_x1_speed_override0_sc_S_40G_HG2_CR2 36 11994 #define sc_x1_speed_override0_sc_S_40G_HG2_KR2 37 11995 #define sc_x1_speed_override0_sc_S_40G_HG2_X2 38 11996 #define sc_x1_speed_override0_sc_S_40G_CR4 40 11997 #define sc_x1_speed_override0_sc_S_40G_KR4 41 11998 #define sc_x1_speed_override0_sc_S_40G_X4 42 11999 #define sc_x1_speed_override0_sc_S_40G_HG2_CR4 44 12000 #define sc_x1_speed_override0_sc_S_40G_HG2_KR4 45 12001 #define sc_x1_speed_override0_sc_S_40G_HG2_X4 46 12002 #define sc_x1_speed_override0_sc_S_50G_CR2 48 12003 #define sc_x1_speed_override0_sc_S_50G_KR2 49 12004 #define sc_x1_speed_override0_sc_S_50G_X2 50 12005 #define sc_x1_speed_override0_sc_S_50G_HG2_CR2 52 12006 #define sc_x1_speed_override0_sc_S_50G_HG2_KR2 53 12007 #define sc_x1_speed_override0_sc_S_50G_HG2_X2 54 12008 #define sc_x1_speed_override0_sc_S_50G_CR4 56 12009 #define sc_x1_speed_override0_sc_S_50G_KR4 57 12010 #define sc_x1_speed_override0_sc_S_50G_X4 58 12011 #define sc_x1_speed_override0_sc_S_50G_HG2_CR4 60 12012 #define sc_x1_speed_override0_sc_S_50G_HG2_KR4 61 12013 #define sc_x1_speed_override0_sc_S_50G_HG2_X4 62 12014 #define sc_x1_speed_override0_sc_S_100G_CR4 64 12015 #define sc_x1_speed_override0_sc_S_100G_KR4 65 12016 #define sc_x1_speed_override0_sc_S_100G_X4 66 12017 #define sc_x1_speed_override0_sc_S_100G_HG2_CR4 68 12018 #define sc_x1_speed_override0_sc_S_100G_HG2_KR4 69 12019 #define sc_x1_speed_override0_sc_S_100G_HG2_X4 70 12020 #define sc_x1_speed_override0_sc_S_CL73_20GVCO 72 12021 #define sc_x1_speed_override0_sc_S_CL73_25GVCO 80 12022 #define sc_x1_speed_override0_sc_S_CL36_20GVCO 88 12023 #define sc_x1_speed_override0_sc_S_CL36_25GVCO 96 12024 #define sc_x1_speed_override0_sc_S_25G_CR_IEEE 112 12025 #define sc_x1_speed_override0_sc_S_25G_CRS_IEEE 113 12026 #define sc_x1_speed_override0_sc_S_25G_KR_IEEE 114 12027 #define sc_x1_speed_override0_sc_S_25G_KRS_IEEE 115 12028 12029 /**************************************************************************** 12030 * Enums: sc_x1_speed_override0_t_fifo_modes 12031 */ 12032 #define sc_x1_speed_override0_t_fifo_modes_T_FIFO_INSERT_NO_AM 0 12033 #define sc_x1_speed_override0_t_fifo_modes_T_FIFO_INSERT_4_AM 1 12034 #define sc_x1_speed_override0_t_fifo_modes_T_FIFO_INSERT_20_AM 2 12035 #define sc_x1_speed_override0_t_fifo_modes_T_FIFO_INSERT_2_AM 3 12036 12037 /**************************************************************************** 12038 * Enums: sc_x1_speed_override0_t_enc_modes 12039 */ 12040 #define sc_x1_speed_override0_t_enc_modes_T_ENC_MODE_BYPASS 0 12041 #define sc_x1_speed_override0_t_enc_modes_T_ENC_MODE_CL49 1 12042 #define sc_x1_speed_override0_t_enc_modes_T_ENC_MODE_CL82 2 12043 12044 /**************************************************************************** 12045 * Enums: sc_x1_speed_override0_btmx_mode 12046 */ 12047 #define sc_x1_speed_override0_btmx_mode_BS_BTMX_MODE_1to1 0 12048 #define sc_x1_speed_override0_btmx_mode_BS_BTMX_MODE_2to1 1 12049 #define sc_x1_speed_override0_btmx_mode_BS_BTMX_MODE_5to1 2 12050 12051 /**************************************************************************** 12052 * Enums: sc_x1_speed_override0_t_type_cl82 12053 */ 12054 #define sc_x1_speed_override0_t_type_cl82_T_TYPE_B1 5 12055 #define sc_x1_speed_override0_t_type_cl82_T_TYPE_C 4 12056 #define sc_x1_speed_override0_t_type_cl82_T_TYPE_S 3 12057 #define sc_x1_speed_override0_t_type_cl82_T_TYPE_T 2 12058 #define sc_x1_speed_override0_t_type_cl82_T_TYPE_D 1 12059 #define sc_x1_speed_override0_t_type_cl82_T_TYPE_E 0 12060 12061 /**************************************************************************** 12062 * Enums: sc_x1_speed_override0_txsm_state_cl82 12063 */ 12064 #define sc_x1_speed_override0_txsm_state_cl82_TX_HIG_END 6 12065 #define sc_x1_speed_override0_txsm_state_cl82_TX_HIG_START 5 12066 #define sc_x1_speed_override0_txsm_state_cl82_TX_E 4 12067 #define sc_x1_speed_override0_txsm_state_cl82_TX_T 3 12068 #define sc_x1_speed_override0_txsm_state_cl82_TX_D 2 12069 #define sc_x1_speed_override0_txsm_state_cl82_TX_C 1 12070 #define sc_x1_speed_override0_txsm_state_cl82_TX_INIT 0 12071 12072 /**************************************************************************** 12073 * Enums: sc_x1_speed_override0_ltxsm_state_cl82 12074 */ 12075 #define sc_x1_speed_override0_ltxsm_state_cl82_TX_HIG_END 64 12076 #define sc_x1_speed_override0_ltxsm_state_cl82_TX_HIG_START 32 12077 #define sc_x1_speed_override0_ltxsm_state_cl82_TX_E 16 12078 #define sc_x1_speed_override0_ltxsm_state_cl82_TX_T 8 12079 #define sc_x1_speed_override0_ltxsm_state_cl82_TX_D 4 12080 #define sc_x1_speed_override0_ltxsm_state_cl82_TX_C 2 12081 #define sc_x1_speed_override0_ltxsm_state_cl82_TX_INIT 1 12082 12083 /**************************************************************************** 12084 * Enums: sc_x1_speed_override0_r_type_coded_cl82 12085 */ 12086 #define sc_x1_speed_override0_r_type_coded_cl82_R_TYPE_B1 32 12087 #define sc_x1_speed_override0_r_type_coded_cl82_R_TYPE_C 16 12088 #define sc_x1_speed_override0_r_type_coded_cl82_R_TYPE_S 8 12089 #define sc_x1_speed_override0_r_type_coded_cl82_R_TYPE_T 4 12090 #define sc_x1_speed_override0_r_type_coded_cl82_R_TYPE_D 2 12091 #define sc_x1_speed_override0_r_type_coded_cl82_R_TYPE_E 1 12092 12093 /**************************************************************************** 12094 * Enums: sc_x1_speed_override0_rxsm_state_cl82 12095 */ 12096 #define sc_x1_speed_override0_rxsm_state_cl82_RX_HIG_END 64 12097 #define sc_x1_speed_override0_rxsm_state_cl82_RX_HIG_START 32 12098 #define sc_x1_speed_override0_rxsm_state_cl82_RX_E 16 12099 #define sc_x1_speed_override0_rxsm_state_cl82_RX_T 8 12100 #define sc_x1_speed_override0_rxsm_state_cl82_RX_D 4 12101 #define sc_x1_speed_override0_rxsm_state_cl82_RX_C 2 12102 #define sc_x1_speed_override0_rxsm_state_cl82_RX_INIT 1 12103 12104 /**************************************************************************** 12105 * Enums: sc_x1_speed_override0_deskew_state 12106 */ 12107 #define sc_x1_speed_override0_deskew_state_ALIGN_ACQUIRED 2 12108 #define sc_x1_speed_override0_deskew_state_LOSS_OF_ALIGNMENT 1 12109 12110 /**************************************************************************** 12111 * Enums: sc_x1_speed_override0_os_mode_enum 12112 */ 12113 #define sc_x1_speed_override0_os_mode_enum_OS_MODE_1 0 12114 #define sc_x1_speed_override0_os_mode_enum_OS_MODE_2 1 12115 #define sc_x1_speed_override0_os_mode_enum_OS_MODE_4 2 12116 #define sc_x1_speed_override0_os_mode_enum_OS_MODE_16p5 8 12117 #define sc_x1_speed_override0_os_mode_enum_OS_MODE_20p625 12 12118 12119 /**************************************************************************** 12120 * Enums: sc_x1_speed_override0_scr_modes 12121 */ 12122 #define sc_x1_speed_override0_scr_modes_T_SCR_MODE_BYPASS 0 12123 #define sc_x1_speed_override0_scr_modes_T_SCR_MODE_CL49 1 12124 #define sc_x1_speed_override0_scr_modes_T_SCR_MODE_40G_2_LANE 2 12125 #define sc_x1_speed_override0_scr_modes_T_SCR_MODE_100G 3 12126 #define sc_x1_speed_override0_scr_modes_T_SCR_MODE_20G 4 12127 #define sc_x1_speed_override0_scr_modes_T_SCR_MODE_40G_4_LANE 5 12128 12129 /**************************************************************************** 12130 * Enums: sc_x1_speed_override0_descr_modes 12131 */ 12132 #define sc_x1_speed_override0_descr_modes_R_DESCR_MODE_BYPASS 0 12133 #define sc_x1_speed_override0_descr_modes_R_DESCR_MODE_CL49 1 12134 #define sc_x1_speed_override0_descr_modes_R_DESCR_MODE_CL82 2 12135 12136 /**************************************************************************** 12137 * Enums: sc_x1_speed_override0_r_dec_tl_mode 12138 */ 12139 #define sc_x1_speed_override0_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 12140 #define sc_x1_speed_override0_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 12141 #define sc_x1_speed_override0_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 12142 12143 /**************************************************************************** 12144 * Enums: sc_x1_speed_override0_r_dec_fsm_mode 12145 */ 12146 #define sc_x1_speed_override0_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 12147 #define sc_x1_speed_override0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 12148 #define sc_x1_speed_override0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 12149 12150 /**************************************************************************** 12151 * Enums: sc_x1_speed_override0_r_deskew_mode 12152 */ 12153 #define sc_x1_speed_override0_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 12154 #define sc_x1_speed_override0_r_deskew_mode_R_DESKEW_MODE_20G 1 12155 #define sc_x1_speed_override0_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 12156 #define sc_x1_speed_override0_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 12157 #define sc_x1_speed_override0_r_deskew_mode_R_DESKEW_MODE_100G 4 12158 #define sc_x1_speed_override0_r_deskew_mode_R_DESKEW_MODE_CL49 5 12159 #define sc_x1_speed_override0_r_deskew_mode_R_DESKEW_MODE_CL91_QUAD 6 12160 #define sc_x1_speed_override0_r_deskew_mode_R_DESKEW_MODE_CL91_SINGLE_BRCM 7 12161 #define sc_x1_speed_override0_r_deskew_mode_R_DESKEW_MODE_CL91_DUAL_BRCM 8 12162 #define sc_x1_speed_override0_r_deskew_mode_R_DESKEW_MODE_CL91_FC 9 12163 12164 /**************************************************************************** 12165 * Enums: sc_x1_speed_override0_bs_dist_modes 12166 */ 12167 #define sc_x1_speed_override0_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 12168 #define sc_x1_speed_override0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 12169 #define sc_x1_speed_override0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 12170 #define sc_x1_speed_override0_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 12171 12172 /**************************************************************************** 12173 * Enums: sc_x1_speed_override0_cl49_t_type 12174 */ 12175 #define sc_x1_speed_override0_cl49_t_type_BAD_T_TYPE 15 12176 #define sc_x1_speed_override0_cl49_t_type_T_TYPE_B0 11 12177 #define sc_x1_speed_override0_cl49_t_type_T_TYPE_OB 10 12178 #define sc_x1_speed_override0_cl49_t_type_T_TYPE_B1 9 12179 #define sc_x1_speed_override0_cl49_t_type_T_TYPE_DB 8 12180 #define sc_x1_speed_override0_cl49_t_type_T_TYPE_FC 7 12181 #define sc_x1_speed_override0_cl49_t_type_T_TYPE_TB 6 12182 #define sc_x1_speed_override0_cl49_t_type_T_TYPE_LI 5 12183 #define sc_x1_speed_override0_cl49_t_type_T_TYPE_C 4 12184 #define sc_x1_speed_override0_cl49_t_type_T_TYPE_S 3 12185 #define sc_x1_speed_override0_cl49_t_type_T_TYPE_T 2 12186 #define sc_x1_speed_override0_cl49_t_type_T_TYPE_D 1 12187 #define sc_x1_speed_override0_cl49_t_type_T_TYPE_E 0 12188 12189 /**************************************************************************** 12190 * Enums: sc_x1_speed_override0_cl49_txsm_states 12191 */ 12192 #define sc_x1_speed_override0_cl49_txsm_states_TX_HIG_END 7 12193 #define sc_x1_speed_override0_cl49_txsm_states_TX_HIG_START 6 12194 #define sc_x1_speed_override0_cl49_txsm_states_TX_LI 5 12195 #define sc_x1_speed_override0_cl49_txsm_states_TX_E 4 12196 #define sc_x1_speed_override0_cl49_txsm_states_TX_T 3 12197 #define sc_x1_speed_override0_cl49_txsm_states_TX_D 2 12198 #define sc_x1_speed_override0_cl49_txsm_states_TX_C 1 12199 #define sc_x1_speed_override0_cl49_txsm_states_TX_INIT 0 12200 12201 /**************************************************************************** 12202 * Enums: sc_x1_speed_override0_cl49_ltxsm_states 12203 */ 12204 #define sc_x1_speed_override0_cl49_ltxsm_states_TX_HIG_END 128 12205 #define sc_x1_speed_override0_cl49_ltxsm_states_TX_HIG_START 64 12206 #define sc_x1_speed_override0_cl49_ltxsm_states_TX_LI 32 12207 #define sc_x1_speed_override0_cl49_ltxsm_states_TX_E 16 12208 #define sc_x1_speed_override0_cl49_ltxsm_states_TX_T 8 12209 #define sc_x1_speed_override0_cl49_ltxsm_states_TX_D 4 12210 #define sc_x1_speed_override0_cl49_ltxsm_states_TX_C 2 12211 #define sc_x1_speed_override0_cl49_ltxsm_states_TX_INIT 1 12212 12213 /**************************************************************************** 12214 * Enums: sc_x1_speed_override0_burst_error_mode 12215 */ 12216 #define sc_x1_speed_override0_burst_error_mode_BURST_ERROR_11_BITS 0 12217 #define sc_x1_speed_override0_burst_error_mode_BURST_ERROR_16_BITS 1 12218 #define sc_x1_speed_override0_burst_error_mode_BURST_ERROR_17_BITS 2 12219 #define sc_x1_speed_override0_burst_error_mode_BURST_ERROR_18_BITS 3 12220 #define sc_x1_speed_override0_burst_error_mode_BURST_ERROR_19_BITS 4 12221 #define sc_x1_speed_override0_burst_error_mode_BURST_ERROR_20_BITS 5 12222 #define sc_x1_speed_override0_burst_error_mode_BURST_ERROR_21_BITS 6 12223 #define sc_x1_speed_override0_burst_error_mode_BURST_ERROR_22_BITS 7 12224 #define sc_x1_speed_override0_burst_error_mode_BURST_ERROR_23_BITS 8 12225 #define sc_x1_speed_override0_burst_error_mode_BURST_ERROR_24_BITS 9 12226 #define sc_x1_speed_override0_burst_error_mode_BURST_ERROR_25_BITS 10 12227 #define sc_x1_speed_override0_burst_error_mode_BURST_ERROR_26_BITS 11 12228 #define sc_x1_speed_override0_burst_error_mode_BURST_ERROR_27_BITS 12 12229 #define sc_x1_speed_override0_burst_error_mode_BURST_ERROR_28_BITS 13 12230 #define sc_x1_speed_override0_burst_error_mode_BURST_ERROR_29_BITS 14 12231 #define sc_x1_speed_override0_burst_error_mode_BURST_ERROR_30_BITS 15 12232 #define sc_x1_speed_override0_burst_error_mode_BURST_ERROR_31_BITS 16 12233 #define sc_x1_speed_override0_burst_error_mode_BURST_ERROR_32_BITS 17 12234 #define sc_x1_speed_override0_burst_error_mode_BURST_ERROR_33_BITS 18 12235 #define sc_x1_speed_override0_burst_error_mode_BURST_ERROR_34_BITS 19 12236 #define sc_x1_speed_override0_burst_error_mode_BURST_ERROR_35_BITS 20 12237 #define sc_x1_speed_override0_burst_error_mode_BURST_ERROR_36_BITS 21 12238 #define sc_x1_speed_override0_burst_error_mode_BURST_ERROR_37_BITS 22 12239 #define sc_x1_speed_override0_burst_error_mode_BURST_ERROR_38_BITS 23 12240 #define sc_x1_speed_override0_burst_error_mode_BURST_ERROR_39_BITS 24 12241 #define sc_x1_speed_override0_burst_error_mode_BURST_ERROR_40_BITS 25 12242 #define sc_x1_speed_override0_burst_error_mode_BURST_ERROR_41_BITS 26 12243 12244 /**************************************************************************** 12245 * Enums: sc_x1_speed_override0_bermon_state 12246 */ 12247 #define sc_x1_speed_override0_bermon_state_HI_BER 4 12248 #define sc_x1_speed_override0_bermon_state_GOOD_BER 3 12249 #define sc_x1_speed_override0_bermon_state_BER_TEST_SH 2 12250 #define sc_x1_speed_override0_bermon_state_START_TIMER 1 12251 #define sc_x1_speed_override0_bermon_state_BER_MT_INIT 0 12252 12253 /**************************************************************************** 12254 * Enums: sc_x1_speed_override0_rxsm_state_cl49 12255 */ 12256 #define sc_x1_speed_override0_rxsm_state_cl49_RX_HIG_END 128 12257 #define sc_x1_speed_override0_rxsm_state_cl49_RX_HIG_START 64 12258 #define sc_x1_speed_override0_rxsm_state_cl49_RX_LI 32 12259 #define sc_x1_speed_override0_rxsm_state_cl49_RX_E 16 12260 #define sc_x1_speed_override0_rxsm_state_cl49_RX_T 8 12261 #define sc_x1_speed_override0_rxsm_state_cl49_RX_D 4 12262 #define sc_x1_speed_override0_rxsm_state_cl49_RX_C 2 12263 #define sc_x1_speed_override0_rxsm_state_cl49_RX_INIT 1 12264 12265 /**************************************************************************** 12266 * Enums: sc_x1_speed_override0_r_type 12267 */ 12268 #define sc_x1_speed_override0_r_type_BAD_R_TYPE 15 12269 #define sc_x1_speed_override0_r_type_R_TYPE_B0 11 12270 #define sc_x1_speed_override0_r_type_R_TYPE_OB 10 12271 #define sc_x1_speed_override0_r_type_R_TYPE_B1 9 12272 #define sc_x1_speed_override0_r_type_R_TYPE_DB 8 12273 #define sc_x1_speed_override0_r_type_R_TYPE_FC 7 12274 #define sc_x1_speed_override0_r_type_R_TYPE_TB 6 12275 #define sc_x1_speed_override0_r_type_R_TYPE_LI 5 12276 #define sc_x1_speed_override0_r_type_R_TYPE_C 4 12277 #define sc_x1_speed_override0_r_type_R_TYPE_S 3 12278 #define sc_x1_speed_override0_r_type_R_TYPE_T 2 12279 #define sc_x1_speed_override0_r_type_R_TYPE_D 1 12280 #define sc_x1_speed_override0_r_type_R_TYPE_E 0 12281 12282 /**************************************************************************** 12283 * Enums: sc_x1_speed_override0_am_lock_state 12284 */ 12285 #define sc_x1_speed_override0_am_lock_state_INVALID_AM 512 12286 #define sc_x1_speed_override0_am_lock_state_GOOD_AM 256 12287 #define sc_x1_speed_override0_am_lock_state_COMP_AM 128 12288 #define sc_x1_speed_override0_am_lock_state_TIMER_2 64 12289 #define sc_x1_speed_override0_am_lock_state_AM_2_GOOD 32 12290 #define sc_x1_speed_override0_am_lock_state_COMP_2ND 16 12291 #define sc_x1_speed_override0_am_lock_state_TIMER_1 8 12292 #define sc_x1_speed_override0_am_lock_state_FIND_1ST 4 12293 #define sc_x1_speed_override0_am_lock_state_AM_RESET_CNT 2 12294 #define sc_x1_speed_override0_am_lock_state_AM_LOCK_INIT 1 12295 12296 /**************************************************************************** 12297 * Enums: sc_x1_speed_override0_msg_selector 12298 */ 12299 #define sc_x1_speed_override0_msg_selector_RESERVED 0 12300 #define sc_x1_speed_override0_msg_selector_VALUE_802p3 1 12301 #define sc_x1_speed_override0_msg_selector_VALUE_802p9 2 12302 #define sc_x1_speed_override0_msg_selector_VALUE_802p5 3 12303 #define sc_x1_speed_override0_msg_selector_VALUE_1394 4 12304 12305 /**************************************************************************** 12306 * Enums: sc_x1_speed_override0_synce_enum 12307 */ 12308 #define sc_x1_speed_override0_synce_enum_SYNCE_NO_DIV 0 12309 #define sc_x1_speed_override0_synce_enum_SYNCE_DIV_7 1 12310 #define sc_x1_speed_override0_synce_enum_SYNCE_DIV_11 2 12311 12312 /**************************************************************************** 12313 * Enums: sc_x1_speed_override0_synce_enum_stage0 12314 */ 12315 #define sc_x1_speed_override0_synce_enum_stage0_SYNCE_NO_DIV 0 12316 #define sc_x1_speed_override0_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 12317 #define sc_x1_speed_override0_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 12318 12319 /**************************************************************************** 12320 * Enums: sc_x1_speed_override0_cl91_sync_state 12321 */ 12322 #define sc_x1_speed_override0_cl91_sync_state_FIND_1ST 0 12323 #define sc_x1_speed_override0_cl91_sync_state_COUNT_NEXT 1 12324 #define sc_x1_speed_override0_cl91_sync_state_COMP_2ND 2 12325 #define sc_x1_speed_override0_cl91_sync_state_TWO_GOOD 3 12326 12327 /**************************************************************************** 12328 * Enums: sc_x1_speed_override0_cl91_algn_state 12329 */ 12330 #define sc_x1_speed_override0_cl91_algn_state_LOSS_OF_ALIGNMENT 0 12331 #define sc_x1_speed_override0_cl91_algn_state_DESKEW 1 12332 #define sc_x1_speed_override0_cl91_algn_state_DESKEW_FAIL 2 12333 #define sc_x1_speed_override0_cl91_algn_state_ALIGN_ACQUIRED 3 12334 #define sc_x1_speed_override0_cl91_algn_state_CW_GOOD 4 12335 #define sc_x1_speed_override0_cl91_algn_state_CW_BAD 5 12336 #define sc_x1_speed_override0_cl91_algn_state_THREE_BAD 6 12337 12338 /**************************************************************************** 12339 * Enums: sc_x1_speed_override0_fec_sel_override 12340 */ 12341 #define sc_x1_speed_override0_fec_sel_override_NO_OVERRIDE 0 12342 #define sc_x1_speed_override0_fec_sel_override_NO_FEC 1 12343 #define sc_x1_speed_override0_fec_sel_override_FEC_CL74 2 12344 #define sc_x1_speed_override0_fec_sel_override_FEC_CL91 3 12345 12346 /**************************************************************************** 12347 * Enums: sc_x1_speed_override0_cl91_blksync_mode 12348 */ 12349 #define sc_x1_speed_override0_cl91_blksync_mode_R_BLKSYNC_NO_CL91_FEC 0 12350 #define sc_x1_speed_override0_cl91_blksync_mode_R_BLKSYNC_CL91_QUAD_LANE_FEC 1 12351 #define sc_x1_speed_override0_cl91_blksync_mode_R_BLKSYNC_CL91_DUAL_LANE_FEC 2 12352 #define sc_x1_speed_override0_cl91_blksync_mode_R_BLKSYNC_CL91_SINGLE_LANE_FEC 3 12353 #define sc_x1_speed_override0_cl91_blksync_mode_R_BLKSYNC_CL91_FC_FEC 4 12354 12355 /**************************************************************************** 12356 * Enums: sc_x1_speed_override0_r_merge_mode 12357 */ 12358 #define sc_x1_speed_override0_r_merge_mode_R_MERGE_MODE_BYPASS 0 12359 #define sc_x1_speed_override0_r_merge_mode_R_MERGE_MODE_CL91_FC 1 12360 #define sc_x1_speed_override0_r_merge_mode_R_MERGE_MODE_CL91_SINGLE_LANE 2 12361 #define sc_x1_speed_override0_r_merge_mode_R_MERGE_MODE_CL91_DUAL_LANE 3 12362 #define sc_x1_speed_override0_r_merge_mode_R_MERGE_MODE_CL91_QUAD_LANE 4 12363 12364 /**************************************************************************** 12365 * Enums: sc_x1_speed_override0_r_tc_mode 12366 */ 12367 #define sc_x1_speed_override0_r_tc_mode_R_TC_MODE_SINGLE 0 12368 #define sc_x1_speed_override0_r_tc_mode_R_TC_MODE_DUAL 1 12369 #define sc_x1_speed_override0_r_tc_mode_R_TC_MODE_QUAD 2 12370 12371 /**************************************************************************** 12372 * Enums: sc_x1_speed_override0_r_tc_out_mode 12373 */ 12374 #define sc_x1_speed_override0_r_tc_out_mode_R_TC_OUT_MODE_SINGLE 0 12375 #define sc_x1_speed_override0_r_tc_out_mode_R_TC_OUT_MODE_DUAL 1 12376 #define sc_x1_speed_override0_r_tc_out_mode_R_TC_OUT_MODE_QUAD 2 12377 12378 /**************************************************************************** 12379 * Enums: sc_x1_speed_override0_cl91_fec_mode 12380 */ 12381 #define sc_x1_speed_override0_cl91_fec_mode_NO_CL91_FEC 0 12382 #define sc_x1_speed_override0_cl91_fec_mode_CL91_SINGLE_LANE_FC 1 12383 #define sc_x1_speed_override0_cl91_fec_mode_CL91_SINGLE_LANE_BRCM_PROP 2 12384 #define sc_x1_speed_override0_cl91_fec_mode_CL91_DUAL_LANE_BRCM_PROP 3 12385 #define sc_x1_speed_override0_cl91_fec_mode_CL91_QUAD_LANE 4 12386 #define sc_x1_speed_override0_cl91_fec_mode_IEEE_25G_CL91_SINGLE_LANE 5 12387 12388 /**************************************************************************** 12389 * Enums: sc_x1_speed_override0_am_spacing_mul 12390 */ 12391 #define sc_x1_speed_override0_am_spacing_mul_AM_SPACING_MUL_2 0 12392 #define sc_x1_speed_override0_am_spacing_mul_AM_SPACING_MUL_4 1 12393 #define sc_x1_speed_override0_am_spacing_mul_AM_SPACING_MUL_5 2 12394 #define sc_x1_speed_override0_am_spacing_mul_AM_SPACING_MUL_20 3 12395 12396 /**************************************************************************** 12397 * Enums: sc_x1_speed_override1_cl36TxEEEStates_l 12398 */ 12399 #define sc_x1_speed_override1_cl36TxEEEStates_l_TX_REFRESH 8 12400 #define sc_x1_speed_override1_cl36TxEEEStates_l_TX_QUIET 4 12401 #define sc_x1_speed_override1_cl36TxEEEStates_l_TX_SLEEP 2 12402 #define sc_x1_speed_override1_cl36TxEEEStates_l_TX_ACTIVE 1 12403 12404 /**************************************************************************** 12405 * Enums: sc_x1_speed_override1_cl36TxEEEStates_c 12406 */ 12407 #define sc_x1_speed_override1_cl36TxEEEStates_c_TX_REFRESH 3 12408 #define sc_x1_speed_override1_cl36TxEEEStates_c_TX_QUIET 2 12409 #define sc_x1_speed_override1_cl36TxEEEStates_c_TX_SLEEP 1 12410 #define sc_x1_speed_override1_cl36TxEEEStates_c_TX_ACTIVE 0 12411 12412 /**************************************************************************** 12413 * Enums: sc_x1_speed_override1_cl49TxEEEStates_l 12414 */ 12415 #define sc_x1_speed_override1_cl49TxEEEStates_l_SCR_RESET_2 64 12416 #define sc_x1_speed_override1_cl49TxEEEStates_l_SCR_RESET_1 32 12417 #define sc_x1_speed_override1_cl49TxEEEStates_l_TX_WAKE 16 12418 #define sc_x1_speed_override1_cl49TxEEEStates_l_TX_REFRESH 8 12419 #define sc_x1_speed_override1_cl49TxEEEStates_l_TX_QUIET 4 12420 #define sc_x1_speed_override1_cl49TxEEEStates_l_TX_SLEEP 2 12421 #define sc_x1_speed_override1_cl49TxEEEStates_l_TX_ACTIVE 1 12422 12423 /**************************************************************************** 12424 * Enums: sc_x1_speed_override1_fec_req_enum 12425 */ 12426 #define sc_x1_speed_override1_fec_req_enum_FEC_not_supported 0 12427 #define sc_x1_speed_override1_fec_req_enum_FEC_supported_but_not_requested 1 12428 #define sc_x1_speed_override1_fec_req_enum_invalid_setting 2 12429 #define sc_x1_speed_override1_fec_req_enum_FEC_supported_and_requested 3 12430 12431 /**************************************************************************** 12432 * Enums: sc_x1_speed_override1_cl73_pause_enum 12433 */ 12434 #define sc_x1_speed_override1_cl73_pause_enum_No_PAUSE_ability 0 12435 #define sc_x1_speed_override1_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 12436 #define sc_x1_speed_override1_cl73_pause_enum_Symmetric_PAUSE_ability 1 12437 #define sc_x1_speed_override1_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 12438 12439 /**************************************************************************** 12440 * Enums: sc_x1_speed_override1_cl49TxEEEStates_c 12441 */ 12442 #define sc_x1_speed_override1_cl49TxEEEStates_c_SCR_RESET_2 6 12443 #define sc_x1_speed_override1_cl49TxEEEStates_c_SCR_RESET_1 5 12444 #define sc_x1_speed_override1_cl49TxEEEStates_c_TX_WAKE 4 12445 #define sc_x1_speed_override1_cl49TxEEEStates_c_TX_REFRESH 3 12446 #define sc_x1_speed_override1_cl49TxEEEStates_c_TX_QUIET 2 12447 #define sc_x1_speed_override1_cl49TxEEEStates_c_TX_SLEEP 1 12448 #define sc_x1_speed_override1_cl49TxEEEStates_c_TX_ACTIVE 0 12449 12450 /**************************************************************************** 12451 * Enums: sc_x1_speed_override1_cl36RxEEEStates_l 12452 */ 12453 #define sc_x1_speed_override1_cl36RxEEEStates_l_RX_LINK_FAIL 32 12454 #define sc_x1_speed_override1_cl36RxEEEStates_l_RX_WTF 16 12455 #define sc_x1_speed_override1_cl36RxEEEStates_l_RX_WAKE 8 12456 #define sc_x1_speed_override1_cl36RxEEEStates_l_RX_QUIET 4 12457 #define sc_x1_speed_override1_cl36RxEEEStates_l_RX_SLEEP 2 12458 #define sc_x1_speed_override1_cl36RxEEEStates_l_RX_ACTIVE 1 12459 12460 /**************************************************************************** 12461 * Enums: sc_x1_speed_override1_cl36RxEEEStates_c 12462 */ 12463 #define sc_x1_speed_override1_cl36RxEEEStates_c_RX_LINK_FAIL 5 12464 #define sc_x1_speed_override1_cl36RxEEEStates_c_RX_WTF 4 12465 #define sc_x1_speed_override1_cl36RxEEEStates_c_RX_WAKE 3 12466 #define sc_x1_speed_override1_cl36RxEEEStates_c_RX_QUIET 2 12467 #define sc_x1_speed_override1_cl36RxEEEStates_c_RX_SLEEP 1 12468 #define sc_x1_speed_override1_cl36RxEEEStates_c_RX_ACTIVE 0 12469 12470 /**************************************************************************** 12471 * Enums: sc_x1_speed_override1_cl49RxEEEStates_l 12472 */ 12473 #define sc_x1_speed_override1_cl49RxEEEStates_l_RX_LINK_FAIL 32 12474 #define sc_x1_speed_override1_cl49RxEEEStates_l_RX_WTF 16 12475 #define sc_x1_speed_override1_cl49RxEEEStates_l_RX_WAKE 8 12476 #define sc_x1_speed_override1_cl49RxEEEStates_l_RX_QUIET 4 12477 #define sc_x1_speed_override1_cl49RxEEEStates_l_RX_SLEEP 2 12478 #define sc_x1_speed_override1_cl49RxEEEStates_l_RX_ACTIVE 1 12479 12480 /**************************************************************************** 12481 * Enums: sc_x1_speed_override1_cl49RxEEEStates_c 12482 */ 12483 #define sc_x1_speed_override1_cl49RxEEEStates_c_RX_LINK_FAIL 5 12484 #define sc_x1_speed_override1_cl49RxEEEStates_c_RX_WTF 4 12485 #define sc_x1_speed_override1_cl49RxEEEStates_c_RX_WAKE 3 12486 #define sc_x1_speed_override1_cl49RxEEEStates_c_RX_QUIET 2 12487 #define sc_x1_speed_override1_cl49RxEEEStates_c_RX_SLEEP 1 12488 #define sc_x1_speed_override1_cl49RxEEEStates_c_RX_ACTIVE 0 12489 12490 /**************************************************************************** 12491 * Enums: sc_x1_speed_override1_cl48TxEEEStates_l 12492 */ 12493 #define sc_x1_speed_override1_cl48TxEEEStates_l_TX_REFRESH 8 12494 #define sc_x1_speed_override1_cl48TxEEEStates_l_TX_QUIET 4 12495 #define sc_x1_speed_override1_cl48TxEEEStates_l_TX_SLEEP 2 12496 #define sc_x1_speed_override1_cl48TxEEEStates_l_TX_ACTIVE 1 12497 12498 /**************************************************************************** 12499 * Enums: sc_x1_speed_override1_cl48TxEEEStates_c 12500 */ 12501 #define sc_x1_speed_override1_cl48TxEEEStates_c_TX_REFRESH 3 12502 #define sc_x1_speed_override1_cl48TxEEEStates_c_TX_QUIET 2 12503 #define sc_x1_speed_override1_cl48TxEEEStates_c_TX_SLEEP 1 12504 #define sc_x1_speed_override1_cl48TxEEEStates_c_TX_ACTIVE 0 12505 12506 /**************************************************************************** 12507 * Enums: sc_x1_speed_override1_cl48RxEEEStates_l 12508 */ 12509 #define sc_x1_speed_override1_cl48RxEEEStates_l_RX_LINK_FAIL 32 12510 #define sc_x1_speed_override1_cl48RxEEEStates_l_RX_WAKE 16 12511 #define sc_x1_speed_override1_cl48RxEEEStates_l_RX_QUIET 8 12512 #define sc_x1_speed_override1_cl48RxEEEStates_l_RX_DEACT 4 12513 #define sc_x1_speed_override1_cl48RxEEEStates_l_RX_SLEEP 2 12514 #define sc_x1_speed_override1_cl48RxEEEStates_l_RX_ACTIVE 1 12515 12516 /**************************************************************************** 12517 * Enums: sc_x1_speed_override1_cl48RxEEEStates_c 12518 */ 12519 #define sc_x1_speed_override1_cl48RxEEEStates_c_RX_LINK_FAIL 5 12520 #define sc_x1_speed_override1_cl48RxEEEStates_c_RX_WAKE 4 12521 #define sc_x1_speed_override1_cl48RxEEEStates_c_RX_QUIET 3 12522 #define sc_x1_speed_override1_cl48RxEEEStates_c_RX_DEACT 2 12523 #define sc_x1_speed_override1_cl48RxEEEStates_c_RX_SLEEP 1 12524 #define sc_x1_speed_override1_cl48RxEEEStates_c_RX_ACTIVE 0 12525 12526 /**************************************************************************** 12527 * Enums: sc_x1_speed_override1_IQP_Options 12528 */ 12529 #define sc_x1_speed_override1_IQP_Options_i50uA 0 12530 #define sc_x1_speed_override1_IQP_Options_i100uA 1 12531 #define sc_x1_speed_override1_IQP_Options_i150uA 2 12532 #define sc_x1_speed_override1_IQP_Options_i200uA 3 12533 #define sc_x1_speed_override1_IQP_Options_i250uA 4 12534 #define sc_x1_speed_override1_IQP_Options_i300uA 5 12535 #define sc_x1_speed_override1_IQP_Options_i350uA 6 12536 #define sc_x1_speed_override1_IQP_Options_i400uA 7 12537 #define sc_x1_speed_override1_IQP_Options_i450uA 8 12538 #define sc_x1_speed_override1_IQP_Options_i500uA 9 12539 #define sc_x1_speed_override1_IQP_Options_i550uA 10 12540 #define sc_x1_speed_override1_IQP_Options_i600uA 11 12541 #define sc_x1_speed_override1_IQP_Options_i650uA 12 12542 #define sc_x1_speed_override1_IQP_Options_i700uA 13 12543 #define sc_x1_speed_override1_IQP_Options_i750uA 14 12544 #define sc_x1_speed_override1_IQP_Options_i800uA 15 12545 12546 /**************************************************************************** 12547 * Enums: sc_x1_speed_override1_IDriver_Options 12548 */ 12549 #define sc_x1_speed_override1_IDriver_Options_v680mV 0 12550 #define sc_x1_speed_override1_IDriver_Options_v730mV 1 12551 #define sc_x1_speed_override1_IDriver_Options_v780mV 2 12552 #define sc_x1_speed_override1_IDriver_Options_v830mV 3 12553 #define sc_x1_speed_override1_IDriver_Options_v880mV 4 12554 #define sc_x1_speed_override1_IDriver_Options_v930mV 5 12555 #define sc_x1_speed_override1_IDriver_Options_v980mV 6 12556 #define sc_x1_speed_override1_IDriver_Options_v1010mV 7 12557 #define sc_x1_speed_override1_IDriver_Options_v1040mV 8 12558 #define sc_x1_speed_override1_IDriver_Options_v1060mV 9 12559 #define sc_x1_speed_override1_IDriver_Options_v1070mV 10 12560 #define sc_x1_speed_override1_IDriver_Options_v1080mV 11 12561 #define sc_x1_speed_override1_IDriver_Options_v1085mV 12 12562 #define sc_x1_speed_override1_IDriver_Options_v1090mV 13 12563 #define sc_x1_speed_override1_IDriver_Options_v1095mV 14 12564 #define sc_x1_speed_override1_IDriver_Options_v1100mV 15 12565 12566 /**************************************************************************** 12567 * Enums: sc_x1_speed_override1_operationModes 12568 */ 12569 #define sc_x1_speed_override1_operationModes_XGXS 0 12570 #define sc_x1_speed_override1_operationModes_XGXG_nCC 1 12571 #define sc_x1_speed_override1_operationModes_Indlane_OS8 4 12572 #define sc_x1_speed_override1_operationModes_IndLane_OS5 5 12573 #define sc_x1_speed_override1_operationModes_PCI 7 12574 #define sc_x1_speed_override1_operationModes_XGXS_nLQ 8 12575 #define sc_x1_speed_override1_operationModes_XGXS_nLQnCC 9 12576 #define sc_x1_speed_override1_operationModes_PBypass 10 12577 #define sc_x1_speed_override1_operationModes_PBypass_nDSK 11 12578 #define sc_x1_speed_override1_operationModes_ComboCoreMode 12 12579 #define sc_x1_speed_override1_operationModes_Clocks_off 15 12580 12581 /**************************************************************************** 12582 * Enums: sc_x1_speed_override1_actualSpeeds 12583 */ 12584 #define sc_x1_speed_override1_actualSpeeds_dr_10M 0 12585 #define sc_x1_speed_override1_actualSpeeds_dr_100M 1 12586 #define sc_x1_speed_override1_actualSpeeds_dr_1G 2 12587 #define sc_x1_speed_override1_actualSpeeds_dr_2p5G 3 12588 #define sc_x1_speed_override1_actualSpeeds_dr_5G_X4 4 12589 #define sc_x1_speed_override1_actualSpeeds_dr_6G_X4 5 12590 #define sc_x1_speed_override1_actualSpeeds_dr_10G_HiG 6 12591 #define sc_x1_speed_override1_actualSpeeds_dr_10G_CX4 7 12592 #define sc_x1_speed_override1_actualSpeeds_dr_12G_HiG 8 12593 #define sc_x1_speed_override1_actualSpeeds_dr_12p5G_X4 9 12594 #define sc_x1_speed_override1_actualSpeeds_dr_13G_X4 10 12595 #define sc_x1_speed_override1_actualSpeeds_dr_15G_X4 11 12596 #define sc_x1_speed_override1_actualSpeeds_dr_16G_X4 12 12597 #define sc_x1_speed_override1_actualSpeeds_dr_1G_KX 13 12598 #define sc_x1_speed_override1_actualSpeeds_dr_10G_KX4 14 12599 #define sc_x1_speed_override1_actualSpeeds_dr_10G_KR 15 12600 #define sc_x1_speed_override1_actualSpeeds_dr_5G 16 12601 #define sc_x1_speed_override1_actualSpeeds_dr_6p4G 17 12602 #define sc_x1_speed_override1_actualSpeeds_dr_20G_X4 18 12603 #define sc_x1_speed_override1_actualSpeeds_dr_21G_X4 19 12604 #define sc_x1_speed_override1_actualSpeeds_dr_25G_X4 20 12605 #define sc_x1_speed_override1_actualSpeeds_dr_10G_HiG_DXGXS 21 12606 #define sc_x1_speed_override1_actualSpeeds_dr_10G_DXGXS 22 12607 #define sc_x1_speed_override1_actualSpeeds_dr_10p5G_HiG_DXGXS 23 12608 #define sc_x1_speed_override1_actualSpeeds_dr_10p5G_DXGXS 24 12609 #define sc_x1_speed_override1_actualSpeeds_dr_12p773G_HiG_DXGXS 25 12610 #define sc_x1_speed_override1_actualSpeeds_dr_12p773G_DXGXS 26 12611 #define sc_x1_speed_override1_actualSpeeds_dr_10G_XFI 27 12612 #define sc_x1_speed_override1_actualSpeeds_dr_40G 28 12613 #define sc_x1_speed_override1_actualSpeeds_dr_20G_HiG_DXGXS 29 12614 #define sc_x1_speed_override1_actualSpeeds_dr_20G_DXGXS 30 12615 #define sc_x1_speed_override1_actualSpeeds_dr_10G_SFI 31 12616 #define sc_x1_speed_override1_actualSpeeds_dr_31p5G 32 12617 #define sc_x1_speed_override1_actualSpeeds_dr_32p7G 33 12618 #define sc_x1_speed_override1_actualSpeeds_dr_20G_SCR 34 12619 #define sc_x1_speed_override1_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 12620 #define sc_x1_speed_override1_actualSpeeds_dr_10G_DXGXS_SCR 36 12621 #define sc_x1_speed_override1_actualSpeeds_dr_12G_R2 37 12622 #define sc_x1_speed_override1_actualSpeeds_dr_10G_X2 38 12623 #define sc_x1_speed_override1_actualSpeeds_dr_40G_KR4 39 12624 #define sc_x1_speed_override1_actualSpeeds_dr_40G_CR4 40 12625 #define sc_x1_speed_override1_actualSpeeds_dr_100G_CR10 41 12626 #define sc_x1_speed_override1_actualSpeeds_dr_15p75G_DXGXS 44 12627 #define sc_x1_speed_override1_actualSpeeds_dr_20G_KR2 57 12628 #define sc_x1_speed_override1_actualSpeeds_dr_20G_CR2 58 12629 12630 /**************************************************************************** 12631 * Enums: sc_x1_speed_override1_actualSpeedsMisc1 12632 */ 12633 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_2500BRCM_X1 16 12634 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_5000BRCM_X4 17 12635 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_6000BRCM_X4 18 12636 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_10GHiGig_X4 19 12637 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_10GBASE_CX4 20 12638 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_12GHiGig_X4 21 12639 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 12640 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_13GHiGig_X4 23 12641 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_15GHiGig_X4 24 12642 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_16GHiGig_X4 25 12643 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_5000BRCM_X1 26 12644 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_6363BRCM_X1 27 12645 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_20GHiGig_X4 28 12646 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_21GHiGig_X4 29 12647 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 12648 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 12649 12650 /**************************************************************************** 12651 * Enums: sc_x1_speed_override1_IndLaneModes 12652 */ 12653 #define sc_x1_speed_override1_IndLaneModes_SWSDR_div2 0 12654 #define sc_x1_speed_override1_IndLaneModes_SWSDR_div1 1 12655 #define sc_x1_speed_override1_IndLaneModes_DWSDR_div2 2 12656 #define sc_x1_speed_override1_IndLaneModes_DWSDR_div1 3 12657 12658 /**************************************************************************** 12659 * Enums: sc_x1_speed_override1_prbsSelect 12660 */ 12661 #define sc_x1_speed_override1_prbsSelect_prbs7 0 12662 #define sc_x1_speed_override1_prbsSelect_prbs15 1 12663 #define sc_x1_speed_override1_prbsSelect_prbs23 2 12664 #define sc_x1_speed_override1_prbsSelect_prbs31 3 12665 12666 /**************************************************************************** 12667 * Enums: sc_x1_speed_override1_vcoDivider 12668 */ 12669 #define sc_x1_speed_override1_vcoDivider_div32 0 12670 #define sc_x1_speed_override1_vcoDivider_div36 1 12671 #define sc_x1_speed_override1_vcoDivider_div40 2 12672 #define sc_x1_speed_override1_vcoDivider_div42 3 12673 #define sc_x1_speed_override1_vcoDivider_div48 4 12674 #define sc_x1_speed_override1_vcoDivider_div50 5 12675 #define sc_x1_speed_override1_vcoDivider_div52 6 12676 #define sc_x1_speed_override1_vcoDivider_div54 7 12677 #define sc_x1_speed_override1_vcoDivider_div60 8 12678 #define sc_x1_speed_override1_vcoDivider_div64 9 12679 #define sc_x1_speed_override1_vcoDivider_div66 10 12680 #define sc_x1_speed_override1_vcoDivider_div68 11 12681 #define sc_x1_speed_override1_vcoDivider_div70 12 12682 #define sc_x1_speed_override1_vcoDivider_div80 13 12683 #define sc_x1_speed_override1_vcoDivider_div92 14 12684 #define sc_x1_speed_override1_vcoDivider_div100 15 12685 12686 /**************************************************************************** 12687 * Enums: sc_x1_speed_override1_refClkSelect 12688 */ 12689 #define sc_x1_speed_override1_refClkSelect_clk_25MHz 0 12690 #define sc_x1_speed_override1_refClkSelect_clk_100MHz 1 12691 #define sc_x1_speed_override1_refClkSelect_clk_125MHz 2 12692 #define sc_x1_speed_override1_refClkSelect_clk_156p25MHz 3 12693 #define sc_x1_speed_override1_refClkSelect_clk_187p5MHz 4 12694 #define sc_x1_speed_override1_refClkSelect_clk_161p25Mhz 5 12695 #define sc_x1_speed_override1_refClkSelect_clk_50Mhz 6 12696 #define sc_x1_speed_override1_refClkSelect_clk_106p25Mhz 7 12697 12698 /**************************************************************************** 12699 * Enums: sc_x1_speed_override1_aerMMDdevTypeSelect 12700 */ 12701 #define sc_x1_speed_override1_aerMMDdevTypeSelect_combo_core 0 12702 #define sc_x1_speed_override1_aerMMDdevTypeSelect_PMA_PMD 1 12703 #define sc_x1_speed_override1_aerMMDdevTypeSelect_PCS 3 12704 #define sc_x1_speed_override1_aerMMDdevTypeSelect_PHY 4 12705 #define sc_x1_speed_override1_aerMMDdevTypeSelect_DTE 5 12706 #define sc_x1_speed_override1_aerMMDdevTypeSelect_CL73_AN 7 12707 12708 /**************************************************************************** 12709 * Enums: sc_x1_speed_override1_aerMMDportSelect 12710 */ 12711 #define sc_x1_speed_override1_aerMMDportSelect_ln0 0 12712 #define sc_x1_speed_override1_aerMMDportSelect_ln1 1 12713 #define sc_x1_speed_override1_aerMMDportSelect_ln2 2 12714 #define sc_x1_speed_override1_aerMMDportSelect_ln3 3 12715 #define sc_x1_speed_override1_aerMMDportSelect_BCST_ln0_1_2_3 511 12716 #define sc_x1_speed_override1_aerMMDportSelect_BCST_ln0_1 512 12717 #define sc_x1_speed_override1_aerMMDportSelect_BCST_ln2_3 513 12718 12719 /**************************************************************************** 12720 * Enums: sc_x1_speed_override1_firmwareModeSelect 12721 */ 12722 #define sc_x1_speed_override1_firmwareModeSelect_DEFAULT 0 12723 #define sc_x1_speed_override1_firmwareModeSelect_SFP_OPT_LR 1 12724 #define sc_x1_speed_override1_firmwareModeSelect_SFP_DAC 2 12725 #define sc_x1_speed_override1_firmwareModeSelect_XLAUI 3 12726 #define sc_x1_speed_override1_firmwareModeSelect_LONG_CH_6G 4 12727 12728 /**************************************************************************** 12729 * Enums: sc_x1_speed_override1_tempIdxSelect 12730 */ 12731 #define sc_x1_speed_override1_tempIdxSelect_LTE__22p9C 15 12732 #define sc_x1_speed_override1_tempIdxSelect_LTE__12p6C 14 12733 #define sc_x1_speed_override1_tempIdxSelect_LTE__3p0C 13 12734 #define sc_x1_speed_override1_tempIdxSelect_LTE_6p7C 12 12735 #define sc_x1_speed_override1_tempIdxSelect_LTE_16p4C 11 12736 #define sc_x1_speed_override1_tempIdxSelect_LTE_26p6C 10 12737 #define sc_x1_speed_override1_tempIdxSelect_LTE_36p3C 9 12738 #define sc_x1_speed_override1_tempIdxSelect_LTE_46p0C 8 12739 #define sc_x1_speed_override1_tempIdxSelect_LTE_56p2C 7 12740 #define sc_x1_speed_override1_tempIdxSelect_LTE_65p9C 6 12741 #define sc_x1_speed_override1_tempIdxSelect_LTE_75p6C 5 12742 #define sc_x1_speed_override1_tempIdxSelect_LTE_85p3C 4 12743 #define sc_x1_speed_override1_tempIdxSelect_LTE_95p5C 3 12744 #define sc_x1_speed_override1_tempIdxSelect_LTE_105p2C 2 12745 #define sc_x1_speed_override1_tempIdxSelect_LTE_114p9C 1 12746 #define sc_x1_speed_override1_tempIdxSelect_LTE_125p1C 0 12747 12748 /**************************************************************************** 12749 * Enums: sc_x1_speed_override1_port_mode 12750 */ 12751 #define sc_x1_speed_override1_port_mode_QUAD_PORT 0 12752 #define sc_x1_speed_override1_port_mode_TRI_1_PORT 1 12753 #define sc_x1_speed_override1_port_mode_TRI_2_PORT 2 12754 #define sc_x1_speed_override1_port_mode_DUAL_PORT 3 12755 #define sc_x1_speed_override1_port_mode_SINGLE_PORT 4 12756 12757 /**************************************************************************** 12758 * Enums: sc_x1_speed_override1_rev_letter_enum 12759 */ 12760 #define sc_x1_speed_override1_rev_letter_enum_REV_A 0 12761 #define sc_x1_speed_override1_rev_letter_enum_REV_B 1 12762 #define sc_x1_speed_override1_rev_letter_enum_REV_C 2 12763 #define sc_x1_speed_override1_rev_letter_enum_REV_D 3 12764 12765 /**************************************************************************** 12766 * Enums: sc_x1_speed_override1_rev_number_enum 12767 */ 12768 #define sc_x1_speed_override1_rev_number_enum_REV_0 0 12769 #define sc_x1_speed_override1_rev_number_enum_REV_1 1 12770 #define sc_x1_speed_override1_rev_number_enum_REV_2 2 12771 #define sc_x1_speed_override1_rev_number_enum_REV_3 3 12772 #define sc_x1_speed_override1_rev_number_enum_REV_4 4 12773 #define sc_x1_speed_override1_rev_number_enum_REV_5 5 12774 #define sc_x1_speed_override1_rev_number_enum_REV_6 6 12775 #define sc_x1_speed_override1_rev_number_enum_REV_7 7 12776 12777 /**************************************************************************** 12778 * Enums: sc_x1_speed_override1_bonding_enum 12779 */ 12780 #define sc_x1_speed_override1_bonding_enum_WIRE_BOND 0 12781 #define sc_x1_speed_override1_bonding_enum_FLIP_CHIP 1 12782 12783 /**************************************************************************** 12784 * Enums: sc_x1_speed_override1_tech_process 12785 */ 12786 #define sc_x1_speed_override1_tech_process_PROCESS_90NM 0 12787 #define sc_x1_speed_override1_tech_process_PROCESS_65NM 1 12788 #define sc_x1_speed_override1_tech_process_PROCESS_40NM 2 12789 #define sc_x1_speed_override1_tech_process_PROCESS_28NM 3 12790 #define sc_x1_speed_override1_tech_process_PROCESS_16NM 4 12791 12792 /**************************************************************************** 12793 * Enums: sc_x1_speed_override1_model_num 12794 */ 12795 #define sc_x1_speed_override1_model_num_SERDES_CL73 0 12796 #define sc_x1_speed_override1_model_num_XGXS_16G 1 12797 #define sc_x1_speed_override1_model_num_HYPERCORE 2 12798 #define sc_x1_speed_override1_model_num_HYPERLITE 3 12799 #define sc_x1_speed_override1_model_num_PCIE_G2_PIPE 4 12800 #define sc_x1_speed_override1_model_num_SERDES_1p25GBd 5 12801 #define sc_x1_speed_override1_model_num_SATA2 6 12802 #define sc_x1_speed_override1_model_num_QSGMII 7 12803 #define sc_x1_speed_override1_model_num_XGXS10G 8 12804 #define sc_x1_speed_override1_model_num_WARPCORE 9 12805 #define sc_x1_speed_override1_model_num_XFICORE 10 12806 #define sc_x1_speed_override1_model_num_RXFI 11 12807 #define sc_x1_speed_override1_model_num_WARPLITE 12 12808 #define sc_x1_speed_override1_model_num_PENTACORE 13 12809 #define sc_x1_speed_override1_model_num_ESM 14 12810 #define sc_x1_speed_override1_model_num_QUAD_SGMII 15 12811 #define sc_x1_speed_override1_model_num_WARPCORE_3 16 12812 #define sc_x1_speed_override1_model_num_TSC 17 12813 #define sc_x1_speed_override1_model_num_TSC4E 18 12814 #define sc_x1_speed_override1_model_num_TSC12E 19 12815 #define sc_x1_speed_override1_model_num_TSC4F 20 12816 #define sc_x1_speed_override1_model_num_TSC4F_GEN2 21 12817 #define sc_x1_speed_override1_model_num_XGXS_CL73_90NM 29 12818 #define sc_x1_speed_override1_model_num_SERDES_CL73_90NM 30 12819 #define sc_x1_speed_override1_model_num_WARPCORE3 32 12820 #define sc_x1_speed_override1_model_num_WARPCORE4_TSC 33 12821 #define sc_x1_speed_override1_model_num_RXAUI 34 12822 12823 /**************************************************************************** 12824 * Enums: sc_x1_speed_override1_payload 12825 */ 12826 #define sc_x1_speed_override1_payload_REPEAT_2_BYTES 0 12827 #define sc_x1_speed_override1_payload_RAMPING 1 12828 #define sc_x1_speed_override1_payload_CL48_CRPAT 2 12829 #define sc_x1_speed_override1_payload_CL48_CJPAT 3 12830 #define sc_x1_speed_override1_payload_CL36_LONG_CRPAT 4 12831 #define sc_x1_speed_override1_payload_CL36_SHORT_CRPAT 5 12832 12833 /**************************************************************************** 12834 * Enums: sc_x1_speed_override1_sc 12835 */ 12836 #define sc_x1_speed_override1_sc_S_10G_CR1 0 12837 #define sc_x1_speed_override1_sc_S_10G_KR1 1 12838 #define sc_x1_speed_override1_sc_S_10G_X1 2 12839 #define sc_x1_speed_override1_sc_S_10G_HG2_CR1 4 12840 #define sc_x1_speed_override1_sc_S_10G_HG2_KR1 5 12841 #define sc_x1_speed_override1_sc_S_10G_HG2_X1 6 12842 #define sc_x1_speed_override1_sc_S_20G_CR1 8 12843 #define sc_x1_speed_override1_sc_S_20G_KR1 9 12844 #define sc_x1_speed_override1_sc_S_20G_X1 10 12845 #define sc_x1_speed_override1_sc_S_20G_HG2_CR1 12 12846 #define sc_x1_speed_override1_sc_S_20G_HG2_KR1 13 12847 #define sc_x1_speed_override1_sc_S_20G_HG2_X1 14 12848 #define sc_x1_speed_override1_sc_S_25G_CR1 16 12849 #define sc_x1_speed_override1_sc_S_25G_KR1 17 12850 #define sc_x1_speed_override1_sc_S_25G_X1 18 12851 #define sc_x1_speed_override1_sc_S_25G_HG2_CR1 20 12852 #define sc_x1_speed_override1_sc_S_25G_HG2_KR1 21 12853 #define sc_x1_speed_override1_sc_S_25G_HG2_X1 22 12854 #define sc_x1_speed_override1_sc_S_20G_CR2 24 12855 #define sc_x1_speed_override1_sc_S_20G_KR2 25 12856 #define sc_x1_speed_override1_sc_S_20G_X2 26 12857 #define sc_x1_speed_override1_sc_S_20G_HG2_CR2 28 12858 #define sc_x1_speed_override1_sc_S_20G_HG2_KR2 29 12859 #define sc_x1_speed_override1_sc_S_20G_HG2_X2 30 12860 #define sc_x1_speed_override1_sc_S_40G_CR2 32 12861 #define sc_x1_speed_override1_sc_S_40G_KR2 33 12862 #define sc_x1_speed_override1_sc_S_40G_X2 34 12863 #define sc_x1_speed_override1_sc_S_40G_HG2_CR2 36 12864 #define sc_x1_speed_override1_sc_S_40G_HG2_KR2 37 12865 #define sc_x1_speed_override1_sc_S_40G_HG2_X2 38 12866 #define sc_x1_speed_override1_sc_S_40G_CR4 40 12867 #define sc_x1_speed_override1_sc_S_40G_KR4 41 12868 #define sc_x1_speed_override1_sc_S_40G_X4 42 12869 #define sc_x1_speed_override1_sc_S_40G_HG2_CR4 44 12870 #define sc_x1_speed_override1_sc_S_40G_HG2_KR4 45 12871 #define sc_x1_speed_override1_sc_S_40G_HG2_X4 46 12872 #define sc_x1_speed_override1_sc_S_50G_CR2 48 12873 #define sc_x1_speed_override1_sc_S_50G_KR2 49 12874 #define sc_x1_speed_override1_sc_S_50G_X2 50 12875 #define sc_x1_speed_override1_sc_S_50G_HG2_CR2 52 12876 #define sc_x1_speed_override1_sc_S_50G_HG2_KR2 53 12877 #define sc_x1_speed_override1_sc_S_50G_HG2_X2 54 12878 #define sc_x1_speed_override1_sc_S_50G_CR4 56 12879 #define sc_x1_speed_override1_sc_S_50G_KR4 57 12880 #define sc_x1_speed_override1_sc_S_50G_X4 58 12881 #define sc_x1_speed_override1_sc_S_50G_HG2_CR4 60 12882 #define sc_x1_speed_override1_sc_S_50G_HG2_KR4 61 12883 #define sc_x1_speed_override1_sc_S_50G_HG2_X4 62 12884 #define sc_x1_speed_override1_sc_S_100G_CR4 64 12885 #define sc_x1_speed_override1_sc_S_100G_KR4 65 12886 #define sc_x1_speed_override1_sc_S_100G_X4 66 12887 #define sc_x1_speed_override1_sc_S_100G_HG2_CR4 68 12888 #define sc_x1_speed_override1_sc_S_100G_HG2_KR4 69 12889 #define sc_x1_speed_override1_sc_S_100G_HG2_X4 70 12890 #define sc_x1_speed_override1_sc_S_CL73_20GVCO 72 12891 #define sc_x1_speed_override1_sc_S_CL73_25GVCO 80 12892 #define sc_x1_speed_override1_sc_S_CL36_20GVCO 88 12893 #define sc_x1_speed_override1_sc_S_CL36_25GVCO 96 12894 #define sc_x1_speed_override1_sc_S_25G_CR_IEEE 112 12895 #define sc_x1_speed_override1_sc_S_25G_CRS_IEEE 113 12896 #define sc_x1_speed_override1_sc_S_25G_KR_IEEE 114 12897 #define sc_x1_speed_override1_sc_S_25G_KRS_IEEE 115 12898 12899 /**************************************************************************** 12900 * Enums: sc_x1_speed_override1_t_fifo_modes 12901 */ 12902 #define sc_x1_speed_override1_t_fifo_modes_T_FIFO_INSERT_NO_AM 0 12903 #define sc_x1_speed_override1_t_fifo_modes_T_FIFO_INSERT_4_AM 1 12904 #define sc_x1_speed_override1_t_fifo_modes_T_FIFO_INSERT_20_AM 2 12905 #define sc_x1_speed_override1_t_fifo_modes_T_FIFO_INSERT_2_AM 3 12906 12907 /**************************************************************************** 12908 * Enums: sc_x1_speed_override1_t_enc_modes 12909 */ 12910 #define sc_x1_speed_override1_t_enc_modes_T_ENC_MODE_BYPASS 0 12911 #define sc_x1_speed_override1_t_enc_modes_T_ENC_MODE_CL49 1 12912 #define sc_x1_speed_override1_t_enc_modes_T_ENC_MODE_CL82 2 12913 12914 /**************************************************************************** 12915 * Enums: sc_x1_speed_override1_btmx_mode 12916 */ 12917 #define sc_x1_speed_override1_btmx_mode_BS_BTMX_MODE_1to1 0 12918 #define sc_x1_speed_override1_btmx_mode_BS_BTMX_MODE_2to1 1 12919 #define sc_x1_speed_override1_btmx_mode_BS_BTMX_MODE_5to1 2 12920 12921 /**************************************************************************** 12922 * Enums: sc_x1_speed_override1_t_type_cl82 12923 */ 12924 #define sc_x1_speed_override1_t_type_cl82_T_TYPE_B1 5 12925 #define sc_x1_speed_override1_t_type_cl82_T_TYPE_C 4 12926 #define sc_x1_speed_override1_t_type_cl82_T_TYPE_S 3 12927 #define sc_x1_speed_override1_t_type_cl82_T_TYPE_T 2 12928 #define sc_x1_speed_override1_t_type_cl82_T_TYPE_D 1 12929 #define sc_x1_speed_override1_t_type_cl82_T_TYPE_E 0 12930 12931 /**************************************************************************** 12932 * Enums: sc_x1_speed_override1_txsm_state_cl82 12933 */ 12934 #define sc_x1_speed_override1_txsm_state_cl82_TX_HIG_END 6 12935 #define sc_x1_speed_override1_txsm_state_cl82_TX_HIG_START 5 12936 #define sc_x1_speed_override1_txsm_state_cl82_TX_E 4 12937 #define sc_x1_speed_override1_txsm_state_cl82_TX_T 3 12938 #define sc_x1_speed_override1_txsm_state_cl82_TX_D 2 12939 #define sc_x1_speed_override1_txsm_state_cl82_TX_C 1 12940 #define sc_x1_speed_override1_txsm_state_cl82_TX_INIT 0 12941 12942 /**************************************************************************** 12943 * Enums: sc_x1_speed_override1_ltxsm_state_cl82 12944 */ 12945 #define sc_x1_speed_override1_ltxsm_state_cl82_TX_HIG_END 64 12946 #define sc_x1_speed_override1_ltxsm_state_cl82_TX_HIG_START 32 12947 #define sc_x1_speed_override1_ltxsm_state_cl82_TX_E 16 12948 #define sc_x1_speed_override1_ltxsm_state_cl82_TX_T 8 12949 #define sc_x1_speed_override1_ltxsm_state_cl82_TX_D 4 12950 #define sc_x1_speed_override1_ltxsm_state_cl82_TX_C 2 12951 #define sc_x1_speed_override1_ltxsm_state_cl82_TX_INIT 1 12952 12953 /**************************************************************************** 12954 * Enums: sc_x1_speed_override1_r_type_coded_cl82 12955 */ 12956 #define sc_x1_speed_override1_r_type_coded_cl82_R_TYPE_B1 32 12957 #define sc_x1_speed_override1_r_type_coded_cl82_R_TYPE_C 16 12958 #define sc_x1_speed_override1_r_type_coded_cl82_R_TYPE_S 8 12959 #define sc_x1_speed_override1_r_type_coded_cl82_R_TYPE_T 4 12960 #define sc_x1_speed_override1_r_type_coded_cl82_R_TYPE_D 2 12961 #define sc_x1_speed_override1_r_type_coded_cl82_R_TYPE_E 1 12962 12963 /**************************************************************************** 12964 * Enums: sc_x1_speed_override1_rxsm_state_cl82 12965 */ 12966 #define sc_x1_speed_override1_rxsm_state_cl82_RX_HIG_END 64 12967 #define sc_x1_speed_override1_rxsm_state_cl82_RX_HIG_START 32 12968 #define sc_x1_speed_override1_rxsm_state_cl82_RX_E 16 12969 #define sc_x1_speed_override1_rxsm_state_cl82_RX_T 8 12970 #define sc_x1_speed_override1_rxsm_state_cl82_RX_D 4 12971 #define sc_x1_speed_override1_rxsm_state_cl82_RX_C 2 12972 #define sc_x1_speed_override1_rxsm_state_cl82_RX_INIT 1 12973 12974 /**************************************************************************** 12975 * Enums: sc_x1_speed_override1_deskew_state 12976 */ 12977 #define sc_x1_speed_override1_deskew_state_ALIGN_ACQUIRED 2 12978 #define sc_x1_speed_override1_deskew_state_LOSS_OF_ALIGNMENT 1 12979 12980 /**************************************************************************** 12981 * Enums: sc_x1_speed_override1_os_mode_enum 12982 */ 12983 #define sc_x1_speed_override1_os_mode_enum_OS_MODE_1 0 12984 #define sc_x1_speed_override1_os_mode_enum_OS_MODE_2 1 12985 #define sc_x1_speed_override1_os_mode_enum_OS_MODE_4 2 12986 #define sc_x1_speed_override1_os_mode_enum_OS_MODE_16p5 8 12987 #define sc_x1_speed_override1_os_mode_enum_OS_MODE_20p625 12 12988 12989 /**************************************************************************** 12990 * Enums: sc_x1_speed_override1_scr_modes 12991 */ 12992 #define sc_x1_speed_override1_scr_modes_T_SCR_MODE_BYPASS 0 12993 #define sc_x1_speed_override1_scr_modes_T_SCR_MODE_CL49 1 12994 #define sc_x1_speed_override1_scr_modes_T_SCR_MODE_40G_2_LANE 2 12995 #define sc_x1_speed_override1_scr_modes_T_SCR_MODE_100G 3 12996 #define sc_x1_speed_override1_scr_modes_T_SCR_MODE_20G 4 12997 #define sc_x1_speed_override1_scr_modes_T_SCR_MODE_40G_4_LANE 5 12998 12999 /**************************************************************************** 13000 * Enums: sc_x1_speed_override1_descr_modes 13001 */ 13002 #define sc_x1_speed_override1_descr_modes_R_DESCR_MODE_BYPASS 0 13003 #define sc_x1_speed_override1_descr_modes_R_DESCR_MODE_CL49 1 13004 #define sc_x1_speed_override1_descr_modes_R_DESCR_MODE_CL82 2 13005 13006 /**************************************************************************** 13007 * Enums: sc_x1_speed_override1_r_dec_tl_mode 13008 */ 13009 #define sc_x1_speed_override1_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 13010 #define sc_x1_speed_override1_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 13011 #define sc_x1_speed_override1_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 13012 13013 /**************************************************************************** 13014 * Enums: sc_x1_speed_override1_r_dec_fsm_mode 13015 */ 13016 #define sc_x1_speed_override1_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 13017 #define sc_x1_speed_override1_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 13018 #define sc_x1_speed_override1_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 13019 13020 /**************************************************************************** 13021 * Enums: sc_x1_speed_override1_r_deskew_mode 13022 */ 13023 #define sc_x1_speed_override1_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 13024 #define sc_x1_speed_override1_r_deskew_mode_R_DESKEW_MODE_20G 1 13025 #define sc_x1_speed_override1_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 13026 #define sc_x1_speed_override1_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 13027 #define sc_x1_speed_override1_r_deskew_mode_R_DESKEW_MODE_100G 4 13028 #define sc_x1_speed_override1_r_deskew_mode_R_DESKEW_MODE_CL49 5 13029 #define sc_x1_speed_override1_r_deskew_mode_R_DESKEW_MODE_CL91_QUAD 6 13030 #define sc_x1_speed_override1_r_deskew_mode_R_DESKEW_MODE_CL91_SINGLE_BRCM 7 13031 #define sc_x1_speed_override1_r_deskew_mode_R_DESKEW_MODE_CL91_DUAL_BRCM 8 13032 #define sc_x1_speed_override1_r_deskew_mode_R_DESKEW_MODE_CL91_FC 9 13033 13034 /**************************************************************************** 13035 * Enums: sc_x1_speed_override1_bs_dist_modes 13036 */ 13037 #define sc_x1_speed_override1_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 13038 #define sc_x1_speed_override1_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 13039 #define sc_x1_speed_override1_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 13040 #define sc_x1_speed_override1_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 13041 13042 /**************************************************************************** 13043 * Enums: sc_x1_speed_override1_cl49_t_type 13044 */ 13045 #define sc_x1_speed_override1_cl49_t_type_BAD_T_TYPE 15 13046 #define sc_x1_speed_override1_cl49_t_type_T_TYPE_B0 11 13047 #define sc_x1_speed_override1_cl49_t_type_T_TYPE_OB 10 13048 #define sc_x1_speed_override1_cl49_t_type_T_TYPE_B1 9 13049 #define sc_x1_speed_override1_cl49_t_type_T_TYPE_DB 8 13050 #define sc_x1_speed_override1_cl49_t_type_T_TYPE_FC 7 13051 #define sc_x1_speed_override1_cl49_t_type_T_TYPE_TB 6 13052 #define sc_x1_speed_override1_cl49_t_type_T_TYPE_LI 5 13053 #define sc_x1_speed_override1_cl49_t_type_T_TYPE_C 4 13054 #define sc_x1_speed_override1_cl49_t_type_T_TYPE_S 3 13055 #define sc_x1_speed_override1_cl49_t_type_T_TYPE_T 2 13056 #define sc_x1_speed_override1_cl49_t_type_T_TYPE_D 1 13057 #define sc_x1_speed_override1_cl49_t_type_T_TYPE_E 0 13058 13059 /**************************************************************************** 13060 * Enums: sc_x1_speed_override1_cl49_txsm_states 13061 */ 13062 #define sc_x1_speed_override1_cl49_txsm_states_TX_HIG_END 7 13063 #define sc_x1_speed_override1_cl49_txsm_states_TX_HIG_START 6 13064 #define sc_x1_speed_override1_cl49_txsm_states_TX_LI 5 13065 #define sc_x1_speed_override1_cl49_txsm_states_TX_E 4 13066 #define sc_x1_speed_override1_cl49_txsm_states_TX_T 3 13067 #define sc_x1_speed_override1_cl49_txsm_states_TX_D 2 13068 #define sc_x1_speed_override1_cl49_txsm_states_TX_C 1 13069 #define sc_x1_speed_override1_cl49_txsm_states_TX_INIT 0 13070 13071 /**************************************************************************** 13072 * Enums: sc_x1_speed_override1_cl49_ltxsm_states 13073 */ 13074 #define sc_x1_speed_override1_cl49_ltxsm_states_TX_HIG_END 128 13075 #define sc_x1_speed_override1_cl49_ltxsm_states_TX_HIG_START 64 13076 #define sc_x1_speed_override1_cl49_ltxsm_states_TX_LI 32 13077 #define sc_x1_speed_override1_cl49_ltxsm_states_TX_E 16 13078 #define sc_x1_speed_override1_cl49_ltxsm_states_TX_T 8 13079 #define sc_x1_speed_override1_cl49_ltxsm_states_TX_D 4 13080 #define sc_x1_speed_override1_cl49_ltxsm_states_TX_C 2 13081 #define sc_x1_speed_override1_cl49_ltxsm_states_TX_INIT 1 13082 13083 /**************************************************************************** 13084 * Enums: sc_x1_speed_override1_burst_error_mode 13085 */ 13086 #define sc_x1_speed_override1_burst_error_mode_BURST_ERROR_11_BITS 0 13087 #define sc_x1_speed_override1_burst_error_mode_BURST_ERROR_16_BITS 1 13088 #define sc_x1_speed_override1_burst_error_mode_BURST_ERROR_17_BITS 2 13089 #define sc_x1_speed_override1_burst_error_mode_BURST_ERROR_18_BITS 3 13090 #define sc_x1_speed_override1_burst_error_mode_BURST_ERROR_19_BITS 4 13091 #define sc_x1_speed_override1_burst_error_mode_BURST_ERROR_20_BITS 5 13092 #define sc_x1_speed_override1_burst_error_mode_BURST_ERROR_21_BITS 6 13093 #define sc_x1_speed_override1_burst_error_mode_BURST_ERROR_22_BITS 7 13094 #define sc_x1_speed_override1_burst_error_mode_BURST_ERROR_23_BITS 8 13095 #define sc_x1_speed_override1_burst_error_mode_BURST_ERROR_24_BITS 9 13096 #define sc_x1_speed_override1_burst_error_mode_BURST_ERROR_25_BITS 10 13097 #define sc_x1_speed_override1_burst_error_mode_BURST_ERROR_26_BITS 11 13098 #define sc_x1_speed_override1_burst_error_mode_BURST_ERROR_27_BITS 12 13099 #define sc_x1_speed_override1_burst_error_mode_BURST_ERROR_28_BITS 13 13100 #define sc_x1_speed_override1_burst_error_mode_BURST_ERROR_29_BITS 14 13101 #define sc_x1_speed_override1_burst_error_mode_BURST_ERROR_30_BITS 15 13102 #define sc_x1_speed_override1_burst_error_mode_BURST_ERROR_31_BITS 16 13103 #define sc_x1_speed_override1_burst_error_mode_BURST_ERROR_32_BITS 17 13104 #define sc_x1_speed_override1_burst_error_mode_BURST_ERROR_33_BITS 18 13105 #define sc_x1_speed_override1_burst_error_mode_BURST_ERROR_34_BITS 19 13106 #define sc_x1_speed_override1_burst_error_mode_BURST_ERROR_35_BITS 20 13107 #define sc_x1_speed_override1_burst_error_mode_BURST_ERROR_36_BITS 21 13108 #define sc_x1_speed_override1_burst_error_mode_BURST_ERROR_37_BITS 22 13109 #define sc_x1_speed_override1_burst_error_mode_BURST_ERROR_38_BITS 23 13110 #define sc_x1_speed_override1_burst_error_mode_BURST_ERROR_39_BITS 24 13111 #define sc_x1_speed_override1_burst_error_mode_BURST_ERROR_40_BITS 25 13112 #define sc_x1_speed_override1_burst_error_mode_BURST_ERROR_41_BITS 26 13113 13114 /**************************************************************************** 13115 * Enums: sc_x1_speed_override1_bermon_state 13116 */ 13117 #define sc_x1_speed_override1_bermon_state_HI_BER 4 13118 #define sc_x1_speed_override1_bermon_state_GOOD_BER 3 13119 #define sc_x1_speed_override1_bermon_state_BER_TEST_SH 2 13120 #define sc_x1_speed_override1_bermon_state_START_TIMER 1 13121 #define sc_x1_speed_override1_bermon_state_BER_MT_INIT 0 13122 13123 /**************************************************************************** 13124 * Enums: sc_x1_speed_override1_rxsm_state_cl49 13125 */ 13126 #define sc_x1_speed_override1_rxsm_state_cl49_RX_HIG_END 128 13127 #define sc_x1_speed_override1_rxsm_state_cl49_RX_HIG_START 64 13128 #define sc_x1_speed_override1_rxsm_state_cl49_RX_LI 32 13129 #define sc_x1_speed_override1_rxsm_state_cl49_RX_E 16 13130 #define sc_x1_speed_override1_rxsm_state_cl49_RX_T 8 13131 #define sc_x1_speed_override1_rxsm_state_cl49_RX_D 4 13132 #define sc_x1_speed_override1_rxsm_state_cl49_RX_C 2 13133 #define sc_x1_speed_override1_rxsm_state_cl49_RX_INIT 1 13134 13135 /**************************************************************************** 13136 * Enums: sc_x1_speed_override1_r_type 13137 */ 13138 #define sc_x1_speed_override1_r_type_BAD_R_TYPE 15 13139 #define sc_x1_speed_override1_r_type_R_TYPE_B0 11 13140 #define sc_x1_speed_override1_r_type_R_TYPE_OB 10 13141 #define sc_x1_speed_override1_r_type_R_TYPE_B1 9 13142 #define sc_x1_speed_override1_r_type_R_TYPE_DB 8 13143 #define sc_x1_speed_override1_r_type_R_TYPE_FC 7 13144 #define sc_x1_speed_override1_r_type_R_TYPE_TB 6 13145 #define sc_x1_speed_override1_r_type_R_TYPE_LI 5 13146 #define sc_x1_speed_override1_r_type_R_TYPE_C 4 13147 #define sc_x1_speed_override1_r_type_R_TYPE_S 3 13148 #define sc_x1_speed_override1_r_type_R_TYPE_T 2 13149 #define sc_x1_speed_override1_r_type_R_TYPE_D 1 13150 #define sc_x1_speed_override1_r_type_R_TYPE_E 0 13151 13152 /**************************************************************************** 13153 * Enums: sc_x1_speed_override1_am_lock_state 13154 */ 13155 #define sc_x1_speed_override1_am_lock_state_INVALID_AM 512 13156 #define sc_x1_speed_override1_am_lock_state_GOOD_AM 256 13157 #define sc_x1_speed_override1_am_lock_state_COMP_AM 128 13158 #define sc_x1_speed_override1_am_lock_state_TIMER_2 64 13159 #define sc_x1_speed_override1_am_lock_state_AM_2_GOOD 32 13160 #define sc_x1_speed_override1_am_lock_state_COMP_2ND 16 13161 #define sc_x1_speed_override1_am_lock_state_TIMER_1 8 13162 #define sc_x1_speed_override1_am_lock_state_FIND_1ST 4 13163 #define sc_x1_speed_override1_am_lock_state_AM_RESET_CNT 2 13164 #define sc_x1_speed_override1_am_lock_state_AM_LOCK_INIT 1 13165 13166 /**************************************************************************** 13167 * Enums: sc_x1_speed_override1_msg_selector 13168 */ 13169 #define sc_x1_speed_override1_msg_selector_RESERVED 0 13170 #define sc_x1_speed_override1_msg_selector_VALUE_802p3 1 13171 #define sc_x1_speed_override1_msg_selector_VALUE_802p9 2 13172 #define sc_x1_speed_override1_msg_selector_VALUE_802p5 3 13173 #define sc_x1_speed_override1_msg_selector_VALUE_1394 4 13174 13175 /**************************************************************************** 13176 * Enums: sc_x1_speed_override1_synce_enum 13177 */ 13178 #define sc_x1_speed_override1_synce_enum_SYNCE_NO_DIV 0 13179 #define sc_x1_speed_override1_synce_enum_SYNCE_DIV_7 1 13180 #define sc_x1_speed_override1_synce_enum_SYNCE_DIV_11 2 13181 13182 /**************************************************************************** 13183 * Enums: sc_x1_speed_override1_synce_enum_stage0 13184 */ 13185 #define sc_x1_speed_override1_synce_enum_stage0_SYNCE_NO_DIV 0 13186 #define sc_x1_speed_override1_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 13187 #define sc_x1_speed_override1_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 13188 13189 /**************************************************************************** 13190 * Enums: sc_x1_speed_override1_cl91_sync_state 13191 */ 13192 #define sc_x1_speed_override1_cl91_sync_state_FIND_1ST 0 13193 #define sc_x1_speed_override1_cl91_sync_state_COUNT_NEXT 1 13194 #define sc_x1_speed_override1_cl91_sync_state_COMP_2ND 2 13195 #define sc_x1_speed_override1_cl91_sync_state_TWO_GOOD 3 13196 13197 /**************************************************************************** 13198 * Enums: sc_x1_speed_override1_cl91_algn_state 13199 */ 13200 #define sc_x1_speed_override1_cl91_algn_state_LOSS_OF_ALIGNMENT 0 13201 #define sc_x1_speed_override1_cl91_algn_state_DESKEW 1 13202 #define sc_x1_speed_override1_cl91_algn_state_DESKEW_FAIL 2 13203 #define sc_x1_speed_override1_cl91_algn_state_ALIGN_ACQUIRED 3 13204 #define sc_x1_speed_override1_cl91_algn_state_CW_GOOD 4 13205 #define sc_x1_speed_override1_cl91_algn_state_CW_BAD 5 13206 #define sc_x1_speed_override1_cl91_algn_state_THREE_BAD 6 13207 13208 /**************************************************************************** 13209 * Enums: sc_x1_speed_override1_fec_sel_override 13210 */ 13211 #define sc_x1_speed_override1_fec_sel_override_NO_OVERRIDE 0 13212 #define sc_x1_speed_override1_fec_sel_override_NO_FEC 1 13213 #define sc_x1_speed_override1_fec_sel_override_FEC_CL74 2 13214 #define sc_x1_speed_override1_fec_sel_override_FEC_CL91 3 13215 13216 /**************************************************************************** 13217 * Enums: sc_x1_speed_override1_cl91_blksync_mode 13218 */ 13219 #define sc_x1_speed_override1_cl91_blksync_mode_R_BLKSYNC_NO_CL91_FEC 0 13220 #define sc_x1_speed_override1_cl91_blksync_mode_R_BLKSYNC_CL91_QUAD_LANE_FEC 1 13221 #define sc_x1_speed_override1_cl91_blksync_mode_R_BLKSYNC_CL91_DUAL_LANE_FEC 2 13222 #define sc_x1_speed_override1_cl91_blksync_mode_R_BLKSYNC_CL91_SINGLE_LANE_FEC 3 13223 #define sc_x1_speed_override1_cl91_blksync_mode_R_BLKSYNC_CL91_FC_FEC 4 13224 13225 /**************************************************************************** 13226 * Enums: sc_x1_speed_override1_r_merge_mode 13227 */ 13228 #define sc_x1_speed_override1_r_merge_mode_R_MERGE_MODE_BYPASS 0 13229 #define sc_x1_speed_override1_r_merge_mode_R_MERGE_MODE_CL91_FC 1 13230 #define sc_x1_speed_override1_r_merge_mode_R_MERGE_MODE_CL91_SINGLE_LANE 2 13231 #define sc_x1_speed_override1_r_merge_mode_R_MERGE_MODE_CL91_DUAL_LANE 3 13232 #define sc_x1_speed_override1_r_merge_mode_R_MERGE_MODE_CL91_QUAD_LANE 4 13233 13234 /**************************************************************************** 13235 * Enums: sc_x1_speed_override1_r_tc_mode 13236 */ 13237 #define sc_x1_speed_override1_r_tc_mode_R_TC_MODE_SINGLE 0 13238 #define sc_x1_speed_override1_r_tc_mode_R_TC_MODE_DUAL 1 13239 #define sc_x1_speed_override1_r_tc_mode_R_TC_MODE_QUAD 2 13240 13241 /**************************************************************************** 13242 * Enums: sc_x1_speed_override1_r_tc_out_mode 13243 */ 13244 #define sc_x1_speed_override1_r_tc_out_mode_R_TC_OUT_MODE_SINGLE 0 13245 #define sc_x1_speed_override1_r_tc_out_mode_R_TC_OUT_MODE_DUAL 1 13246 #define sc_x1_speed_override1_r_tc_out_mode_R_TC_OUT_MODE_QUAD 2 13247 13248 /**************************************************************************** 13249 * Enums: sc_x1_speed_override1_cl91_fec_mode 13250 */ 13251 #define sc_x1_speed_override1_cl91_fec_mode_NO_CL91_FEC 0 13252 #define sc_x1_speed_override1_cl91_fec_mode_CL91_SINGLE_LANE_FC 1 13253 #define sc_x1_speed_override1_cl91_fec_mode_CL91_SINGLE_LANE_BRCM_PROP 2 13254 #define sc_x1_speed_override1_cl91_fec_mode_CL91_DUAL_LANE_BRCM_PROP 3 13255 #define sc_x1_speed_override1_cl91_fec_mode_CL91_QUAD_LANE 4 13256 #define sc_x1_speed_override1_cl91_fec_mode_IEEE_25G_CL91_SINGLE_LANE 5 13257 13258 /**************************************************************************** 13259 * Enums: sc_x1_speed_override1_am_spacing_mul 13260 */ 13261 #define sc_x1_speed_override1_am_spacing_mul_AM_SPACING_MUL_2 0 13262 #define sc_x1_speed_override1_am_spacing_mul_AM_SPACING_MUL_4 1 13263 #define sc_x1_speed_override1_am_spacing_mul_AM_SPACING_MUL_5 2 13264 #define sc_x1_speed_override1_am_spacing_mul_AM_SPACING_MUL_20 3 13265 13266 /**************************************************************************** 13267 * Enums: sc_x1_speed_override2_cl36TxEEEStates_l 13268 */ 13269 #define sc_x1_speed_override2_cl36TxEEEStates_l_TX_REFRESH 8 13270 #define sc_x1_speed_override2_cl36TxEEEStates_l_TX_QUIET 4 13271 #define sc_x1_speed_override2_cl36TxEEEStates_l_TX_SLEEP 2 13272 #define sc_x1_speed_override2_cl36TxEEEStates_l_TX_ACTIVE 1 13273 13274 /**************************************************************************** 13275 * Enums: sc_x1_speed_override2_cl36TxEEEStates_c 13276 */ 13277 #define sc_x1_speed_override2_cl36TxEEEStates_c_TX_REFRESH 3 13278 #define sc_x1_speed_override2_cl36TxEEEStates_c_TX_QUIET 2 13279 #define sc_x1_speed_override2_cl36TxEEEStates_c_TX_SLEEP 1 13280 #define sc_x1_speed_override2_cl36TxEEEStates_c_TX_ACTIVE 0 13281 13282 /**************************************************************************** 13283 * Enums: sc_x1_speed_override2_cl49TxEEEStates_l 13284 */ 13285 #define sc_x1_speed_override2_cl49TxEEEStates_l_SCR_RESET_2 64 13286 #define sc_x1_speed_override2_cl49TxEEEStates_l_SCR_RESET_1 32 13287 #define sc_x1_speed_override2_cl49TxEEEStates_l_TX_WAKE 16 13288 #define sc_x1_speed_override2_cl49TxEEEStates_l_TX_REFRESH 8 13289 #define sc_x1_speed_override2_cl49TxEEEStates_l_TX_QUIET 4 13290 #define sc_x1_speed_override2_cl49TxEEEStates_l_TX_SLEEP 2 13291 #define sc_x1_speed_override2_cl49TxEEEStates_l_TX_ACTIVE 1 13292 13293 /**************************************************************************** 13294 * Enums: sc_x1_speed_override2_fec_req_enum 13295 */ 13296 #define sc_x1_speed_override2_fec_req_enum_FEC_not_supported 0 13297 #define sc_x1_speed_override2_fec_req_enum_FEC_supported_but_not_requested 1 13298 #define sc_x1_speed_override2_fec_req_enum_invalid_setting 2 13299 #define sc_x1_speed_override2_fec_req_enum_FEC_supported_and_requested 3 13300 13301 /**************************************************************************** 13302 * Enums: sc_x1_speed_override2_cl73_pause_enum 13303 */ 13304 #define sc_x1_speed_override2_cl73_pause_enum_No_PAUSE_ability 0 13305 #define sc_x1_speed_override2_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 13306 #define sc_x1_speed_override2_cl73_pause_enum_Symmetric_PAUSE_ability 1 13307 #define sc_x1_speed_override2_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 13308 13309 /**************************************************************************** 13310 * Enums: sc_x1_speed_override2_cl49TxEEEStates_c 13311 */ 13312 #define sc_x1_speed_override2_cl49TxEEEStates_c_SCR_RESET_2 6 13313 #define sc_x1_speed_override2_cl49TxEEEStates_c_SCR_RESET_1 5 13314 #define sc_x1_speed_override2_cl49TxEEEStates_c_TX_WAKE 4 13315 #define sc_x1_speed_override2_cl49TxEEEStates_c_TX_REFRESH 3 13316 #define sc_x1_speed_override2_cl49TxEEEStates_c_TX_QUIET 2 13317 #define sc_x1_speed_override2_cl49TxEEEStates_c_TX_SLEEP 1 13318 #define sc_x1_speed_override2_cl49TxEEEStates_c_TX_ACTIVE 0 13319 13320 /**************************************************************************** 13321 * Enums: sc_x1_speed_override2_cl36RxEEEStates_l 13322 */ 13323 #define sc_x1_speed_override2_cl36RxEEEStates_l_RX_LINK_FAIL 32 13324 #define sc_x1_speed_override2_cl36RxEEEStates_l_RX_WTF 16 13325 #define sc_x1_speed_override2_cl36RxEEEStates_l_RX_WAKE 8 13326 #define sc_x1_speed_override2_cl36RxEEEStates_l_RX_QUIET 4 13327 #define sc_x1_speed_override2_cl36RxEEEStates_l_RX_SLEEP 2 13328 #define sc_x1_speed_override2_cl36RxEEEStates_l_RX_ACTIVE 1 13329 13330 /**************************************************************************** 13331 * Enums: sc_x1_speed_override2_cl36RxEEEStates_c 13332 */ 13333 #define sc_x1_speed_override2_cl36RxEEEStates_c_RX_LINK_FAIL 5 13334 #define sc_x1_speed_override2_cl36RxEEEStates_c_RX_WTF 4 13335 #define sc_x1_speed_override2_cl36RxEEEStates_c_RX_WAKE 3 13336 #define sc_x1_speed_override2_cl36RxEEEStates_c_RX_QUIET 2 13337 #define sc_x1_speed_override2_cl36RxEEEStates_c_RX_SLEEP 1 13338 #define sc_x1_speed_override2_cl36RxEEEStates_c_RX_ACTIVE 0 13339 13340 /**************************************************************************** 13341 * Enums: sc_x1_speed_override2_cl49RxEEEStates_l 13342 */ 13343 #define sc_x1_speed_override2_cl49RxEEEStates_l_RX_LINK_FAIL 32 13344 #define sc_x1_speed_override2_cl49RxEEEStates_l_RX_WTF 16 13345 #define sc_x1_speed_override2_cl49RxEEEStates_l_RX_WAKE 8 13346 #define sc_x1_speed_override2_cl49RxEEEStates_l_RX_QUIET 4 13347 #define sc_x1_speed_override2_cl49RxEEEStates_l_RX_SLEEP 2 13348 #define sc_x1_speed_override2_cl49RxEEEStates_l_RX_ACTIVE 1 13349 13350 /**************************************************************************** 13351 * Enums: sc_x1_speed_override2_cl49RxEEEStates_c 13352 */ 13353 #define sc_x1_speed_override2_cl49RxEEEStates_c_RX_LINK_FAIL 5 13354 #define sc_x1_speed_override2_cl49RxEEEStates_c_RX_WTF 4 13355 #define sc_x1_speed_override2_cl49RxEEEStates_c_RX_WAKE 3 13356 #define sc_x1_speed_override2_cl49RxEEEStates_c_RX_QUIET 2 13357 #define sc_x1_speed_override2_cl49RxEEEStates_c_RX_SLEEP 1 13358 #define sc_x1_speed_override2_cl49RxEEEStates_c_RX_ACTIVE 0 13359 13360 /**************************************************************************** 13361 * Enums: sc_x1_speed_override2_cl48TxEEEStates_l 13362 */ 13363 #define sc_x1_speed_override2_cl48TxEEEStates_l_TX_REFRESH 8 13364 #define sc_x1_speed_override2_cl48TxEEEStates_l_TX_QUIET 4 13365 #define sc_x1_speed_override2_cl48TxEEEStates_l_TX_SLEEP 2 13366 #define sc_x1_speed_override2_cl48TxEEEStates_l_TX_ACTIVE 1 13367 13368 /**************************************************************************** 13369 * Enums: sc_x1_speed_override2_cl48TxEEEStates_c 13370 */ 13371 #define sc_x1_speed_override2_cl48TxEEEStates_c_TX_REFRESH 3 13372 #define sc_x1_speed_override2_cl48TxEEEStates_c_TX_QUIET 2 13373 #define sc_x1_speed_override2_cl48TxEEEStates_c_TX_SLEEP 1 13374 #define sc_x1_speed_override2_cl48TxEEEStates_c_TX_ACTIVE 0 13375 13376 /**************************************************************************** 13377 * Enums: sc_x1_speed_override2_cl48RxEEEStates_l 13378 */ 13379 #define sc_x1_speed_override2_cl48RxEEEStates_l_RX_LINK_FAIL 32 13380 #define sc_x1_speed_override2_cl48RxEEEStates_l_RX_WAKE 16 13381 #define sc_x1_speed_override2_cl48RxEEEStates_l_RX_QUIET 8 13382 #define sc_x1_speed_override2_cl48RxEEEStates_l_RX_DEACT 4 13383 #define sc_x1_speed_override2_cl48RxEEEStates_l_RX_SLEEP 2 13384 #define sc_x1_speed_override2_cl48RxEEEStates_l_RX_ACTIVE 1 13385 13386 /**************************************************************************** 13387 * Enums: sc_x1_speed_override2_cl48RxEEEStates_c 13388 */ 13389 #define sc_x1_speed_override2_cl48RxEEEStates_c_RX_LINK_FAIL 5 13390 #define sc_x1_speed_override2_cl48RxEEEStates_c_RX_WAKE 4 13391 #define sc_x1_speed_override2_cl48RxEEEStates_c_RX_QUIET 3 13392 #define sc_x1_speed_override2_cl48RxEEEStates_c_RX_DEACT 2 13393 #define sc_x1_speed_override2_cl48RxEEEStates_c_RX_SLEEP 1 13394 #define sc_x1_speed_override2_cl48RxEEEStates_c_RX_ACTIVE 0 13395 13396 /**************************************************************************** 13397 * Enums: sc_x1_speed_override2_IQP_Options 13398 */ 13399 #define sc_x1_speed_override2_IQP_Options_i50uA 0 13400 #define sc_x1_speed_override2_IQP_Options_i100uA 1 13401 #define sc_x1_speed_override2_IQP_Options_i150uA 2 13402 #define sc_x1_speed_override2_IQP_Options_i200uA 3 13403 #define sc_x1_speed_override2_IQP_Options_i250uA 4 13404 #define sc_x1_speed_override2_IQP_Options_i300uA 5 13405 #define sc_x1_speed_override2_IQP_Options_i350uA 6 13406 #define sc_x1_speed_override2_IQP_Options_i400uA 7 13407 #define sc_x1_speed_override2_IQP_Options_i450uA 8 13408 #define sc_x1_speed_override2_IQP_Options_i500uA 9 13409 #define sc_x1_speed_override2_IQP_Options_i550uA 10 13410 #define sc_x1_speed_override2_IQP_Options_i600uA 11 13411 #define sc_x1_speed_override2_IQP_Options_i650uA 12 13412 #define sc_x1_speed_override2_IQP_Options_i700uA 13 13413 #define sc_x1_speed_override2_IQP_Options_i750uA 14 13414 #define sc_x1_speed_override2_IQP_Options_i800uA 15 13415 13416 /**************************************************************************** 13417 * Enums: sc_x1_speed_override2_IDriver_Options 13418 */ 13419 #define sc_x1_speed_override2_IDriver_Options_v680mV 0 13420 #define sc_x1_speed_override2_IDriver_Options_v730mV 1 13421 #define sc_x1_speed_override2_IDriver_Options_v780mV 2 13422 #define sc_x1_speed_override2_IDriver_Options_v830mV 3 13423 #define sc_x1_speed_override2_IDriver_Options_v880mV 4 13424 #define sc_x1_speed_override2_IDriver_Options_v930mV 5 13425 #define sc_x1_speed_override2_IDriver_Options_v980mV 6 13426 #define sc_x1_speed_override2_IDriver_Options_v1010mV 7 13427 #define sc_x1_speed_override2_IDriver_Options_v1040mV 8 13428 #define sc_x1_speed_override2_IDriver_Options_v1060mV 9 13429 #define sc_x1_speed_override2_IDriver_Options_v1070mV 10 13430 #define sc_x1_speed_override2_IDriver_Options_v1080mV 11 13431 #define sc_x1_speed_override2_IDriver_Options_v1085mV 12 13432 #define sc_x1_speed_override2_IDriver_Options_v1090mV 13 13433 #define sc_x1_speed_override2_IDriver_Options_v1095mV 14 13434 #define sc_x1_speed_override2_IDriver_Options_v1100mV 15 13435 13436 /**************************************************************************** 13437 * Enums: sc_x1_speed_override2_operationModes 13438 */ 13439 #define sc_x1_speed_override2_operationModes_XGXS 0 13440 #define sc_x1_speed_override2_operationModes_XGXG_nCC 1 13441 #define sc_x1_speed_override2_operationModes_Indlane_OS8 4 13442 #define sc_x1_speed_override2_operationModes_IndLane_OS5 5 13443 #define sc_x1_speed_override2_operationModes_PCI 7 13444 #define sc_x1_speed_override2_operationModes_XGXS_nLQ 8 13445 #define sc_x1_speed_override2_operationModes_XGXS_nLQnCC 9 13446 #define sc_x1_speed_override2_operationModes_PBypass 10 13447 #define sc_x1_speed_override2_operationModes_PBypass_nDSK 11 13448 #define sc_x1_speed_override2_operationModes_ComboCoreMode 12 13449 #define sc_x1_speed_override2_operationModes_Clocks_off 15 13450 13451 /**************************************************************************** 13452 * Enums: sc_x1_speed_override2_actualSpeeds 13453 */ 13454 #define sc_x1_speed_override2_actualSpeeds_dr_10M 0 13455 #define sc_x1_speed_override2_actualSpeeds_dr_100M 1 13456 #define sc_x1_speed_override2_actualSpeeds_dr_1G 2 13457 #define sc_x1_speed_override2_actualSpeeds_dr_2p5G 3 13458 #define sc_x1_speed_override2_actualSpeeds_dr_5G_X4 4 13459 #define sc_x1_speed_override2_actualSpeeds_dr_6G_X4 5 13460 #define sc_x1_speed_override2_actualSpeeds_dr_10G_HiG 6 13461 #define sc_x1_speed_override2_actualSpeeds_dr_10G_CX4 7 13462 #define sc_x1_speed_override2_actualSpeeds_dr_12G_HiG 8 13463 #define sc_x1_speed_override2_actualSpeeds_dr_12p5G_X4 9 13464 #define sc_x1_speed_override2_actualSpeeds_dr_13G_X4 10 13465 #define sc_x1_speed_override2_actualSpeeds_dr_15G_X4 11 13466 #define sc_x1_speed_override2_actualSpeeds_dr_16G_X4 12 13467 #define sc_x1_speed_override2_actualSpeeds_dr_1G_KX 13 13468 #define sc_x1_speed_override2_actualSpeeds_dr_10G_KX4 14 13469 #define sc_x1_speed_override2_actualSpeeds_dr_10G_KR 15 13470 #define sc_x1_speed_override2_actualSpeeds_dr_5G 16 13471 #define sc_x1_speed_override2_actualSpeeds_dr_6p4G 17 13472 #define sc_x1_speed_override2_actualSpeeds_dr_20G_X4 18 13473 #define sc_x1_speed_override2_actualSpeeds_dr_21G_X4 19 13474 #define sc_x1_speed_override2_actualSpeeds_dr_25G_X4 20 13475 #define sc_x1_speed_override2_actualSpeeds_dr_10G_HiG_DXGXS 21 13476 #define sc_x1_speed_override2_actualSpeeds_dr_10G_DXGXS 22 13477 #define sc_x1_speed_override2_actualSpeeds_dr_10p5G_HiG_DXGXS 23 13478 #define sc_x1_speed_override2_actualSpeeds_dr_10p5G_DXGXS 24 13479 #define sc_x1_speed_override2_actualSpeeds_dr_12p773G_HiG_DXGXS 25 13480 #define sc_x1_speed_override2_actualSpeeds_dr_12p773G_DXGXS 26 13481 #define sc_x1_speed_override2_actualSpeeds_dr_10G_XFI 27 13482 #define sc_x1_speed_override2_actualSpeeds_dr_40G 28 13483 #define sc_x1_speed_override2_actualSpeeds_dr_20G_HiG_DXGXS 29 13484 #define sc_x1_speed_override2_actualSpeeds_dr_20G_DXGXS 30 13485 #define sc_x1_speed_override2_actualSpeeds_dr_10G_SFI 31 13486 #define sc_x1_speed_override2_actualSpeeds_dr_31p5G 32 13487 #define sc_x1_speed_override2_actualSpeeds_dr_32p7G 33 13488 #define sc_x1_speed_override2_actualSpeeds_dr_20G_SCR 34 13489 #define sc_x1_speed_override2_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 13490 #define sc_x1_speed_override2_actualSpeeds_dr_10G_DXGXS_SCR 36 13491 #define sc_x1_speed_override2_actualSpeeds_dr_12G_R2 37 13492 #define sc_x1_speed_override2_actualSpeeds_dr_10G_X2 38 13493 #define sc_x1_speed_override2_actualSpeeds_dr_40G_KR4 39 13494 #define sc_x1_speed_override2_actualSpeeds_dr_40G_CR4 40 13495 #define sc_x1_speed_override2_actualSpeeds_dr_100G_CR10 41 13496 #define sc_x1_speed_override2_actualSpeeds_dr_15p75G_DXGXS 44 13497 #define sc_x1_speed_override2_actualSpeeds_dr_20G_KR2 57 13498 #define sc_x1_speed_override2_actualSpeeds_dr_20G_CR2 58 13499 13500 /**************************************************************************** 13501 * Enums: sc_x1_speed_override2_actualSpeedsMisc1 13502 */ 13503 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_2500BRCM_X1 16 13504 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_5000BRCM_X4 17 13505 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_6000BRCM_X4 18 13506 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_10GHiGig_X4 19 13507 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_10GBASE_CX4 20 13508 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_12GHiGig_X4 21 13509 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 13510 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_13GHiGig_X4 23 13511 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_15GHiGig_X4 24 13512 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_16GHiGig_X4 25 13513 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_5000BRCM_X1 26 13514 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_6363BRCM_X1 27 13515 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_20GHiGig_X4 28 13516 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_21GHiGig_X4 29 13517 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 13518 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 13519 13520 /**************************************************************************** 13521 * Enums: sc_x1_speed_override2_IndLaneModes 13522 */ 13523 #define sc_x1_speed_override2_IndLaneModes_SWSDR_div2 0 13524 #define sc_x1_speed_override2_IndLaneModes_SWSDR_div1 1 13525 #define sc_x1_speed_override2_IndLaneModes_DWSDR_div2 2 13526 #define sc_x1_speed_override2_IndLaneModes_DWSDR_div1 3 13527 13528 /**************************************************************************** 13529 * Enums: sc_x1_speed_override2_prbsSelect 13530 */ 13531 #define sc_x1_speed_override2_prbsSelect_prbs7 0 13532 #define sc_x1_speed_override2_prbsSelect_prbs15 1 13533 #define sc_x1_speed_override2_prbsSelect_prbs23 2 13534 #define sc_x1_speed_override2_prbsSelect_prbs31 3 13535 13536 /**************************************************************************** 13537 * Enums: sc_x1_speed_override2_vcoDivider 13538 */ 13539 #define sc_x1_speed_override2_vcoDivider_div32 0 13540 #define sc_x1_speed_override2_vcoDivider_div36 1 13541 #define sc_x1_speed_override2_vcoDivider_div40 2 13542 #define sc_x1_speed_override2_vcoDivider_div42 3 13543 #define sc_x1_speed_override2_vcoDivider_div48 4 13544 #define sc_x1_speed_override2_vcoDivider_div50 5 13545 #define sc_x1_speed_override2_vcoDivider_div52 6 13546 #define sc_x1_speed_override2_vcoDivider_div54 7 13547 #define sc_x1_speed_override2_vcoDivider_div60 8 13548 #define sc_x1_speed_override2_vcoDivider_div64 9 13549 #define sc_x1_speed_override2_vcoDivider_div66 10 13550 #define sc_x1_speed_override2_vcoDivider_div68 11 13551 #define sc_x1_speed_override2_vcoDivider_div70 12 13552 #define sc_x1_speed_override2_vcoDivider_div80 13 13553 #define sc_x1_speed_override2_vcoDivider_div92 14 13554 #define sc_x1_speed_override2_vcoDivider_div100 15 13555 13556 /**************************************************************************** 13557 * Enums: sc_x1_speed_override2_refClkSelect 13558 */ 13559 #define sc_x1_speed_override2_refClkSelect_clk_25MHz 0 13560 #define sc_x1_speed_override2_refClkSelect_clk_100MHz 1 13561 #define sc_x1_speed_override2_refClkSelect_clk_125MHz 2 13562 #define sc_x1_speed_override2_refClkSelect_clk_156p25MHz 3 13563 #define sc_x1_speed_override2_refClkSelect_clk_187p5MHz 4 13564 #define sc_x1_speed_override2_refClkSelect_clk_161p25Mhz 5 13565 #define sc_x1_speed_override2_refClkSelect_clk_50Mhz 6 13566 #define sc_x1_speed_override2_refClkSelect_clk_106p25Mhz 7 13567 13568 /**************************************************************************** 13569 * Enums: sc_x1_speed_override2_aerMMDdevTypeSelect 13570 */ 13571 #define sc_x1_speed_override2_aerMMDdevTypeSelect_combo_core 0 13572 #define sc_x1_speed_override2_aerMMDdevTypeSelect_PMA_PMD 1 13573 #define sc_x1_speed_override2_aerMMDdevTypeSelect_PCS 3 13574 #define sc_x1_speed_override2_aerMMDdevTypeSelect_PHY 4 13575 #define sc_x1_speed_override2_aerMMDdevTypeSelect_DTE 5 13576 #define sc_x1_speed_override2_aerMMDdevTypeSelect_CL73_AN 7 13577 13578 /**************************************************************************** 13579 * Enums: sc_x1_speed_override2_aerMMDportSelect 13580 */ 13581 #define sc_x1_speed_override2_aerMMDportSelect_ln0 0 13582 #define sc_x1_speed_override2_aerMMDportSelect_ln1 1 13583 #define sc_x1_speed_override2_aerMMDportSelect_ln2 2 13584 #define sc_x1_speed_override2_aerMMDportSelect_ln3 3 13585 #define sc_x1_speed_override2_aerMMDportSelect_BCST_ln0_1_2_3 511 13586 #define sc_x1_speed_override2_aerMMDportSelect_BCST_ln0_1 512 13587 #define sc_x1_speed_override2_aerMMDportSelect_BCST_ln2_3 513 13588 13589 /**************************************************************************** 13590 * Enums: sc_x1_speed_override2_firmwareModeSelect 13591 */ 13592 #define sc_x1_speed_override2_firmwareModeSelect_DEFAULT 0 13593 #define sc_x1_speed_override2_firmwareModeSelect_SFP_OPT_LR 1 13594 #define sc_x1_speed_override2_firmwareModeSelect_SFP_DAC 2 13595 #define sc_x1_speed_override2_firmwareModeSelect_XLAUI 3 13596 #define sc_x1_speed_override2_firmwareModeSelect_LONG_CH_6G 4 13597 13598 /**************************************************************************** 13599 * Enums: sc_x1_speed_override2_tempIdxSelect 13600 */ 13601 #define sc_x1_speed_override2_tempIdxSelect_LTE__22p9C 15 13602 #define sc_x1_speed_override2_tempIdxSelect_LTE__12p6C 14 13603 #define sc_x1_speed_override2_tempIdxSelect_LTE__3p0C 13 13604 #define sc_x1_speed_override2_tempIdxSelect_LTE_6p7C 12 13605 #define sc_x1_speed_override2_tempIdxSelect_LTE_16p4C 11 13606 #define sc_x1_speed_override2_tempIdxSelect_LTE_26p6C 10 13607 #define sc_x1_speed_override2_tempIdxSelect_LTE_36p3C 9 13608 #define sc_x1_speed_override2_tempIdxSelect_LTE_46p0C 8 13609 #define sc_x1_speed_override2_tempIdxSelect_LTE_56p2C 7 13610 #define sc_x1_speed_override2_tempIdxSelect_LTE_65p9C 6 13611 #define sc_x1_speed_override2_tempIdxSelect_LTE_75p6C 5 13612 #define sc_x1_speed_override2_tempIdxSelect_LTE_85p3C 4 13613 #define sc_x1_speed_override2_tempIdxSelect_LTE_95p5C 3 13614 #define sc_x1_speed_override2_tempIdxSelect_LTE_105p2C 2 13615 #define sc_x1_speed_override2_tempIdxSelect_LTE_114p9C 1 13616 #define sc_x1_speed_override2_tempIdxSelect_LTE_125p1C 0 13617 13618 /**************************************************************************** 13619 * Enums: sc_x1_speed_override2_port_mode 13620 */ 13621 #define sc_x1_speed_override2_port_mode_QUAD_PORT 0 13622 #define sc_x1_speed_override2_port_mode_TRI_1_PORT 1 13623 #define sc_x1_speed_override2_port_mode_TRI_2_PORT 2 13624 #define sc_x1_speed_override2_port_mode_DUAL_PORT 3 13625 #define sc_x1_speed_override2_port_mode_SINGLE_PORT 4 13626 13627 /**************************************************************************** 13628 * Enums: sc_x1_speed_override2_rev_letter_enum 13629 */ 13630 #define sc_x1_speed_override2_rev_letter_enum_REV_A 0 13631 #define sc_x1_speed_override2_rev_letter_enum_REV_B 1 13632 #define sc_x1_speed_override2_rev_letter_enum_REV_C 2 13633 #define sc_x1_speed_override2_rev_letter_enum_REV_D 3 13634 13635 /**************************************************************************** 13636 * Enums: sc_x1_speed_override2_rev_number_enum 13637 */ 13638 #define sc_x1_speed_override2_rev_number_enum_REV_0 0 13639 #define sc_x1_speed_override2_rev_number_enum_REV_1 1 13640 #define sc_x1_speed_override2_rev_number_enum_REV_2 2 13641 #define sc_x1_speed_override2_rev_number_enum_REV_3 3 13642 #define sc_x1_speed_override2_rev_number_enum_REV_4 4 13643 #define sc_x1_speed_override2_rev_number_enum_REV_5 5 13644 #define sc_x1_speed_override2_rev_number_enum_REV_6 6 13645 #define sc_x1_speed_override2_rev_number_enum_REV_7 7 13646 13647 /**************************************************************************** 13648 * Enums: sc_x1_speed_override2_bonding_enum 13649 */ 13650 #define sc_x1_speed_override2_bonding_enum_WIRE_BOND 0 13651 #define sc_x1_speed_override2_bonding_enum_FLIP_CHIP 1 13652 13653 /**************************************************************************** 13654 * Enums: sc_x1_speed_override2_tech_process 13655 */ 13656 #define sc_x1_speed_override2_tech_process_PROCESS_90NM 0 13657 #define sc_x1_speed_override2_tech_process_PROCESS_65NM 1 13658 #define sc_x1_speed_override2_tech_process_PROCESS_40NM 2 13659 #define sc_x1_speed_override2_tech_process_PROCESS_28NM 3 13660 #define sc_x1_speed_override2_tech_process_PROCESS_16NM 4 13661 13662 /**************************************************************************** 13663 * Enums: sc_x1_speed_override2_model_num 13664 */ 13665 #define sc_x1_speed_override2_model_num_SERDES_CL73 0 13666 #define sc_x1_speed_override2_model_num_XGXS_16G 1 13667 #define sc_x1_speed_override2_model_num_HYPERCORE 2 13668 #define sc_x1_speed_override2_model_num_HYPERLITE 3 13669 #define sc_x1_speed_override2_model_num_PCIE_G2_PIPE 4 13670 #define sc_x1_speed_override2_model_num_SERDES_1p25GBd 5 13671 #define sc_x1_speed_override2_model_num_SATA2 6 13672 #define sc_x1_speed_override2_model_num_QSGMII 7 13673 #define sc_x1_speed_override2_model_num_XGXS10G 8 13674 #define sc_x1_speed_override2_model_num_WARPCORE 9 13675 #define sc_x1_speed_override2_model_num_XFICORE 10 13676 #define sc_x1_speed_override2_model_num_RXFI 11 13677 #define sc_x1_speed_override2_model_num_WARPLITE 12 13678 #define sc_x1_speed_override2_model_num_PENTACORE 13 13679 #define sc_x1_speed_override2_model_num_ESM 14 13680 #define sc_x1_speed_override2_model_num_QUAD_SGMII 15 13681 #define sc_x1_speed_override2_model_num_WARPCORE_3 16 13682 #define sc_x1_speed_override2_model_num_TSC 17 13683 #define sc_x1_speed_override2_model_num_TSC4E 18 13684 #define sc_x1_speed_override2_model_num_TSC12E 19 13685 #define sc_x1_speed_override2_model_num_TSC4F 20 13686 #define sc_x1_speed_override2_model_num_TSC4F_GEN2 21 13687 #define sc_x1_speed_override2_model_num_XGXS_CL73_90NM 29 13688 #define sc_x1_speed_override2_model_num_SERDES_CL73_90NM 30 13689 #define sc_x1_speed_override2_model_num_WARPCORE3 32 13690 #define sc_x1_speed_override2_model_num_WARPCORE4_TSC 33 13691 #define sc_x1_speed_override2_model_num_RXAUI 34 13692 13693 /**************************************************************************** 13694 * Enums: sc_x1_speed_override2_payload 13695 */ 13696 #define sc_x1_speed_override2_payload_REPEAT_2_BYTES 0 13697 #define sc_x1_speed_override2_payload_RAMPING 1 13698 #define sc_x1_speed_override2_payload_CL48_CRPAT 2 13699 #define sc_x1_speed_override2_payload_CL48_CJPAT 3 13700 #define sc_x1_speed_override2_payload_CL36_LONG_CRPAT 4 13701 #define sc_x1_speed_override2_payload_CL36_SHORT_CRPAT 5 13702 13703 /**************************************************************************** 13704 * Enums: sc_x1_speed_override2_sc 13705 */ 13706 #define sc_x1_speed_override2_sc_S_10G_CR1 0 13707 #define sc_x1_speed_override2_sc_S_10G_KR1 1 13708 #define sc_x1_speed_override2_sc_S_10G_X1 2 13709 #define sc_x1_speed_override2_sc_S_10G_HG2_CR1 4 13710 #define sc_x1_speed_override2_sc_S_10G_HG2_KR1 5 13711 #define sc_x1_speed_override2_sc_S_10G_HG2_X1 6 13712 #define sc_x1_speed_override2_sc_S_20G_CR1 8 13713 #define sc_x1_speed_override2_sc_S_20G_KR1 9 13714 #define sc_x1_speed_override2_sc_S_20G_X1 10 13715 #define sc_x1_speed_override2_sc_S_20G_HG2_CR1 12 13716 #define sc_x1_speed_override2_sc_S_20G_HG2_KR1 13 13717 #define sc_x1_speed_override2_sc_S_20G_HG2_X1 14 13718 #define sc_x1_speed_override2_sc_S_25G_CR1 16 13719 #define sc_x1_speed_override2_sc_S_25G_KR1 17 13720 #define sc_x1_speed_override2_sc_S_25G_X1 18 13721 #define sc_x1_speed_override2_sc_S_25G_HG2_CR1 20 13722 #define sc_x1_speed_override2_sc_S_25G_HG2_KR1 21 13723 #define sc_x1_speed_override2_sc_S_25G_HG2_X1 22 13724 #define sc_x1_speed_override2_sc_S_20G_CR2 24 13725 #define sc_x1_speed_override2_sc_S_20G_KR2 25 13726 #define sc_x1_speed_override2_sc_S_20G_X2 26 13727 #define sc_x1_speed_override2_sc_S_20G_HG2_CR2 28 13728 #define sc_x1_speed_override2_sc_S_20G_HG2_KR2 29 13729 #define sc_x1_speed_override2_sc_S_20G_HG2_X2 30 13730 #define sc_x1_speed_override2_sc_S_40G_CR2 32 13731 #define sc_x1_speed_override2_sc_S_40G_KR2 33 13732 #define sc_x1_speed_override2_sc_S_40G_X2 34 13733 #define sc_x1_speed_override2_sc_S_40G_HG2_CR2 36 13734 #define sc_x1_speed_override2_sc_S_40G_HG2_KR2 37 13735 #define sc_x1_speed_override2_sc_S_40G_HG2_X2 38 13736 #define sc_x1_speed_override2_sc_S_40G_CR4 40 13737 #define sc_x1_speed_override2_sc_S_40G_KR4 41 13738 #define sc_x1_speed_override2_sc_S_40G_X4 42 13739 #define sc_x1_speed_override2_sc_S_40G_HG2_CR4 44 13740 #define sc_x1_speed_override2_sc_S_40G_HG2_KR4 45 13741 #define sc_x1_speed_override2_sc_S_40G_HG2_X4 46 13742 #define sc_x1_speed_override2_sc_S_50G_CR2 48 13743 #define sc_x1_speed_override2_sc_S_50G_KR2 49 13744 #define sc_x1_speed_override2_sc_S_50G_X2 50 13745 #define sc_x1_speed_override2_sc_S_50G_HG2_CR2 52 13746 #define sc_x1_speed_override2_sc_S_50G_HG2_KR2 53 13747 #define sc_x1_speed_override2_sc_S_50G_HG2_X2 54 13748 #define sc_x1_speed_override2_sc_S_50G_CR4 56 13749 #define sc_x1_speed_override2_sc_S_50G_KR4 57 13750 #define sc_x1_speed_override2_sc_S_50G_X4 58 13751 #define sc_x1_speed_override2_sc_S_50G_HG2_CR4 60 13752 #define sc_x1_speed_override2_sc_S_50G_HG2_KR4 61 13753 #define sc_x1_speed_override2_sc_S_50G_HG2_X4 62 13754 #define sc_x1_speed_override2_sc_S_100G_CR4 64 13755 #define sc_x1_speed_override2_sc_S_100G_KR4 65 13756 #define sc_x1_speed_override2_sc_S_100G_X4 66 13757 #define sc_x1_speed_override2_sc_S_100G_HG2_CR4 68 13758 #define sc_x1_speed_override2_sc_S_100G_HG2_KR4 69 13759 #define sc_x1_speed_override2_sc_S_100G_HG2_X4 70 13760 #define sc_x1_speed_override2_sc_S_CL73_20GVCO 72 13761 #define sc_x1_speed_override2_sc_S_CL73_25GVCO 80 13762 #define sc_x1_speed_override2_sc_S_CL36_20GVCO 88 13763 #define sc_x1_speed_override2_sc_S_CL36_25GVCO 96 13764 #define sc_x1_speed_override2_sc_S_25G_CR_IEEE 112 13765 #define sc_x1_speed_override2_sc_S_25G_CRS_IEEE 113 13766 #define sc_x1_speed_override2_sc_S_25G_KR_IEEE 114 13767 #define sc_x1_speed_override2_sc_S_25G_KRS_IEEE 115 13768 13769 /**************************************************************************** 13770 * Enums: sc_x1_speed_override2_t_fifo_modes 13771 */ 13772 #define sc_x1_speed_override2_t_fifo_modes_T_FIFO_INSERT_NO_AM 0 13773 #define sc_x1_speed_override2_t_fifo_modes_T_FIFO_INSERT_4_AM 1 13774 #define sc_x1_speed_override2_t_fifo_modes_T_FIFO_INSERT_20_AM 2 13775 #define sc_x1_speed_override2_t_fifo_modes_T_FIFO_INSERT_2_AM 3 13776 13777 /**************************************************************************** 13778 * Enums: sc_x1_speed_override2_t_enc_modes 13779 */ 13780 #define sc_x1_speed_override2_t_enc_modes_T_ENC_MODE_BYPASS 0 13781 #define sc_x1_speed_override2_t_enc_modes_T_ENC_MODE_CL49 1 13782 #define sc_x1_speed_override2_t_enc_modes_T_ENC_MODE_CL82 2 13783 13784 /**************************************************************************** 13785 * Enums: sc_x1_speed_override2_btmx_mode 13786 */ 13787 #define sc_x1_speed_override2_btmx_mode_BS_BTMX_MODE_1to1 0 13788 #define sc_x1_speed_override2_btmx_mode_BS_BTMX_MODE_2to1 1 13789 #define sc_x1_speed_override2_btmx_mode_BS_BTMX_MODE_5to1 2 13790 13791 /**************************************************************************** 13792 * Enums: sc_x1_speed_override2_t_type_cl82 13793 */ 13794 #define sc_x1_speed_override2_t_type_cl82_T_TYPE_B1 5 13795 #define sc_x1_speed_override2_t_type_cl82_T_TYPE_C 4 13796 #define sc_x1_speed_override2_t_type_cl82_T_TYPE_S 3 13797 #define sc_x1_speed_override2_t_type_cl82_T_TYPE_T 2 13798 #define sc_x1_speed_override2_t_type_cl82_T_TYPE_D 1 13799 #define sc_x1_speed_override2_t_type_cl82_T_TYPE_E 0 13800 13801 /**************************************************************************** 13802 * Enums: sc_x1_speed_override2_txsm_state_cl82 13803 */ 13804 #define sc_x1_speed_override2_txsm_state_cl82_TX_HIG_END 6 13805 #define sc_x1_speed_override2_txsm_state_cl82_TX_HIG_START 5 13806 #define sc_x1_speed_override2_txsm_state_cl82_TX_E 4 13807 #define sc_x1_speed_override2_txsm_state_cl82_TX_T 3 13808 #define sc_x1_speed_override2_txsm_state_cl82_TX_D 2 13809 #define sc_x1_speed_override2_txsm_state_cl82_TX_C 1 13810 #define sc_x1_speed_override2_txsm_state_cl82_TX_INIT 0 13811 13812 /**************************************************************************** 13813 * Enums: sc_x1_speed_override2_ltxsm_state_cl82 13814 */ 13815 #define sc_x1_speed_override2_ltxsm_state_cl82_TX_HIG_END 64 13816 #define sc_x1_speed_override2_ltxsm_state_cl82_TX_HIG_START 32 13817 #define sc_x1_speed_override2_ltxsm_state_cl82_TX_E 16 13818 #define sc_x1_speed_override2_ltxsm_state_cl82_TX_T 8 13819 #define sc_x1_speed_override2_ltxsm_state_cl82_TX_D 4 13820 #define sc_x1_speed_override2_ltxsm_state_cl82_TX_C 2 13821 #define sc_x1_speed_override2_ltxsm_state_cl82_TX_INIT 1 13822 13823 /**************************************************************************** 13824 * Enums: sc_x1_speed_override2_r_type_coded_cl82 13825 */ 13826 #define sc_x1_speed_override2_r_type_coded_cl82_R_TYPE_B1 32 13827 #define sc_x1_speed_override2_r_type_coded_cl82_R_TYPE_C 16 13828 #define sc_x1_speed_override2_r_type_coded_cl82_R_TYPE_S 8 13829 #define sc_x1_speed_override2_r_type_coded_cl82_R_TYPE_T 4 13830 #define sc_x1_speed_override2_r_type_coded_cl82_R_TYPE_D 2 13831 #define sc_x1_speed_override2_r_type_coded_cl82_R_TYPE_E 1 13832 13833 /**************************************************************************** 13834 * Enums: sc_x1_speed_override2_rxsm_state_cl82 13835 */ 13836 #define sc_x1_speed_override2_rxsm_state_cl82_RX_HIG_END 64 13837 #define sc_x1_speed_override2_rxsm_state_cl82_RX_HIG_START 32 13838 #define sc_x1_speed_override2_rxsm_state_cl82_RX_E 16 13839 #define sc_x1_speed_override2_rxsm_state_cl82_RX_T 8 13840 #define sc_x1_speed_override2_rxsm_state_cl82_RX_D 4 13841 #define sc_x1_speed_override2_rxsm_state_cl82_RX_C 2 13842 #define sc_x1_speed_override2_rxsm_state_cl82_RX_INIT 1 13843 13844 /**************************************************************************** 13845 * Enums: sc_x1_speed_override2_deskew_state 13846 */ 13847 #define sc_x1_speed_override2_deskew_state_ALIGN_ACQUIRED 2 13848 #define sc_x1_speed_override2_deskew_state_LOSS_OF_ALIGNMENT 1 13849 13850 /**************************************************************************** 13851 * Enums: sc_x1_speed_override2_os_mode_enum 13852 */ 13853 #define sc_x1_speed_override2_os_mode_enum_OS_MODE_1 0 13854 #define sc_x1_speed_override2_os_mode_enum_OS_MODE_2 1 13855 #define sc_x1_speed_override2_os_mode_enum_OS_MODE_4 2 13856 #define sc_x1_speed_override2_os_mode_enum_OS_MODE_16p5 8 13857 #define sc_x1_speed_override2_os_mode_enum_OS_MODE_20p625 12 13858 13859 /**************************************************************************** 13860 * Enums: sc_x1_speed_override2_scr_modes 13861 */ 13862 #define sc_x1_speed_override2_scr_modes_T_SCR_MODE_BYPASS 0 13863 #define sc_x1_speed_override2_scr_modes_T_SCR_MODE_CL49 1 13864 #define sc_x1_speed_override2_scr_modes_T_SCR_MODE_40G_2_LANE 2 13865 #define sc_x1_speed_override2_scr_modes_T_SCR_MODE_100G 3 13866 #define sc_x1_speed_override2_scr_modes_T_SCR_MODE_20G 4 13867 #define sc_x1_speed_override2_scr_modes_T_SCR_MODE_40G_4_LANE 5 13868 13869 /**************************************************************************** 13870 * Enums: sc_x1_speed_override2_descr_modes 13871 */ 13872 #define sc_x1_speed_override2_descr_modes_R_DESCR_MODE_BYPASS 0 13873 #define sc_x1_speed_override2_descr_modes_R_DESCR_MODE_CL49 1 13874 #define sc_x1_speed_override2_descr_modes_R_DESCR_MODE_CL82 2 13875 13876 /**************************************************************************** 13877 * Enums: sc_x1_speed_override2_r_dec_tl_mode 13878 */ 13879 #define sc_x1_speed_override2_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 13880 #define sc_x1_speed_override2_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 13881 #define sc_x1_speed_override2_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 13882 13883 /**************************************************************************** 13884 * Enums: sc_x1_speed_override2_r_dec_fsm_mode 13885 */ 13886 #define sc_x1_speed_override2_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 13887 #define sc_x1_speed_override2_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 13888 #define sc_x1_speed_override2_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 13889 13890 /**************************************************************************** 13891 * Enums: sc_x1_speed_override2_r_deskew_mode 13892 */ 13893 #define sc_x1_speed_override2_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 13894 #define sc_x1_speed_override2_r_deskew_mode_R_DESKEW_MODE_20G 1 13895 #define sc_x1_speed_override2_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 13896 #define sc_x1_speed_override2_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 13897 #define sc_x1_speed_override2_r_deskew_mode_R_DESKEW_MODE_100G 4 13898 #define sc_x1_speed_override2_r_deskew_mode_R_DESKEW_MODE_CL49 5 13899 #define sc_x1_speed_override2_r_deskew_mode_R_DESKEW_MODE_CL91_QUAD 6 13900 #define sc_x1_speed_override2_r_deskew_mode_R_DESKEW_MODE_CL91_SINGLE_BRCM 7 13901 #define sc_x1_speed_override2_r_deskew_mode_R_DESKEW_MODE_CL91_DUAL_BRCM 8 13902 #define sc_x1_speed_override2_r_deskew_mode_R_DESKEW_MODE_CL91_FC 9 13903 13904 /**************************************************************************** 13905 * Enums: sc_x1_speed_override2_bs_dist_modes 13906 */ 13907 #define sc_x1_speed_override2_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 13908 #define sc_x1_speed_override2_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 13909 #define sc_x1_speed_override2_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 13910 #define sc_x1_speed_override2_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 13911 13912 /**************************************************************************** 13913 * Enums: sc_x1_speed_override2_cl49_t_type 13914 */ 13915 #define sc_x1_speed_override2_cl49_t_type_BAD_T_TYPE 15 13916 #define sc_x1_speed_override2_cl49_t_type_T_TYPE_B0 11 13917 #define sc_x1_speed_override2_cl49_t_type_T_TYPE_OB 10 13918 #define sc_x1_speed_override2_cl49_t_type_T_TYPE_B1 9 13919 #define sc_x1_speed_override2_cl49_t_type_T_TYPE_DB 8 13920 #define sc_x1_speed_override2_cl49_t_type_T_TYPE_FC 7 13921 #define sc_x1_speed_override2_cl49_t_type_T_TYPE_TB 6 13922 #define sc_x1_speed_override2_cl49_t_type_T_TYPE_LI 5 13923 #define sc_x1_speed_override2_cl49_t_type_T_TYPE_C 4 13924 #define sc_x1_speed_override2_cl49_t_type_T_TYPE_S 3 13925 #define sc_x1_speed_override2_cl49_t_type_T_TYPE_T 2 13926 #define sc_x1_speed_override2_cl49_t_type_T_TYPE_D 1 13927 #define sc_x1_speed_override2_cl49_t_type_T_TYPE_E 0 13928 13929 /**************************************************************************** 13930 * Enums: sc_x1_speed_override2_cl49_txsm_states 13931 */ 13932 #define sc_x1_speed_override2_cl49_txsm_states_TX_HIG_END 7 13933 #define sc_x1_speed_override2_cl49_txsm_states_TX_HIG_START 6 13934 #define sc_x1_speed_override2_cl49_txsm_states_TX_LI 5 13935 #define sc_x1_speed_override2_cl49_txsm_states_TX_E 4 13936 #define sc_x1_speed_override2_cl49_txsm_states_TX_T 3 13937 #define sc_x1_speed_override2_cl49_txsm_states_TX_D 2 13938 #define sc_x1_speed_override2_cl49_txsm_states_TX_C 1 13939 #define sc_x1_speed_override2_cl49_txsm_states_TX_INIT 0 13940 13941 /**************************************************************************** 13942 * Enums: sc_x1_speed_override2_cl49_ltxsm_states 13943 */ 13944 #define sc_x1_speed_override2_cl49_ltxsm_states_TX_HIG_END 128 13945 #define sc_x1_speed_override2_cl49_ltxsm_states_TX_HIG_START 64 13946 #define sc_x1_speed_override2_cl49_ltxsm_states_TX_LI 32 13947 #define sc_x1_speed_override2_cl49_ltxsm_states_TX_E 16 13948 #define sc_x1_speed_override2_cl49_ltxsm_states_TX_T 8 13949 #define sc_x1_speed_override2_cl49_ltxsm_states_TX_D 4 13950 #define sc_x1_speed_override2_cl49_ltxsm_states_TX_C 2 13951 #define sc_x1_speed_override2_cl49_ltxsm_states_TX_INIT 1 13952 13953 /**************************************************************************** 13954 * Enums: sc_x1_speed_override2_burst_error_mode 13955 */ 13956 #define sc_x1_speed_override2_burst_error_mode_BURST_ERROR_11_BITS 0 13957 #define sc_x1_speed_override2_burst_error_mode_BURST_ERROR_16_BITS 1 13958 #define sc_x1_speed_override2_burst_error_mode_BURST_ERROR_17_BITS 2 13959 #define sc_x1_speed_override2_burst_error_mode_BURST_ERROR_18_BITS 3 13960 #define sc_x1_speed_override2_burst_error_mode_BURST_ERROR_19_BITS 4 13961 #define sc_x1_speed_override2_burst_error_mode_BURST_ERROR_20_BITS 5 13962 #define sc_x1_speed_override2_burst_error_mode_BURST_ERROR_21_BITS 6 13963 #define sc_x1_speed_override2_burst_error_mode_BURST_ERROR_22_BITS 7 13964 #define sc_x1_speed_override2_burst_error_mode_BURST_ERROR_23_BITS 8 13965 #define sc_x1_speed_override2_burst_error_mode_BURST_ERROR_24_BITS 9 13966 #define sc_x1_speed_override2_burst_error_mode_BURST_ERROR_25_BITS 10 13967 #define sc_x1_speed_override2_burst_error_mode_BURST_ERROR_26_BITS 11 13968 #define sc_x1_speed_override2_burst_error_mode_BURST_ERROR_27_BITS 12 13969 #define sc_x1_speed_override2_burst_error_mode_BURST_ERROR_28_BITS 13 13970 #define sc_x1_speed_override2_burst_error_mode_BURST_ERROR_29_BITS 14 13971 #define sc_x1_speed_override2_burst_error_mode_BURST_ERROR_30_BITS 15 13972 #define sc_x1_speed_override2_burst_error_mode_BURST_ERROR_31_BITS 16 13973 #define sc_x1_speed_override2_burst_error_mode_BURST_ERROR_32_BITS 17 13974 #define sc_x1_speed_override2_burst_error_mode_BURST_ERROR_33_BITS 18 13975 #define sc_x1_speed_override2_burst_error_mode_BURST_ERROR_34_BITS 19 13976 #define sc_x1_speed_override2_burst_error_mode_BURST_ERROR_35_BITS 20 13977 #define sc_x1_speed_override2_burst_error_mode_BURST_ERROR_36_BITS 21 13978 #define sc_x1_speed_override2_burst_error_mode_BURST_ERROR_37_BITS 22 13979 #define sc_x1_speed_override2_burst_error_mode_BURST_ERROR_38_BITS 23 13980 #define sc_x1_speed_override2_burst_error_mode_BURST_ERROR_39_BITS 24 13981 #define sc_x1_speed_override2_burst_error_mode_BURST_ERROR_40_BITS 25 13982 #define sc_x1_speed_override2_burst_error_mode_BURST_ERROR_41_BITS 26 13983 13984 /**************************************************************************** 13985 * Enums: sc_x1_speed_override2_bermon_state 13986 */ 13987 #define sc_x1_speed_override2_bermon_state_HI_BER 4 13988 #define sc_x1_speed_override2_bermon_state_GOOD_BER 3 13989 #define sc_x1_speed_override2_bermon_state_BER_TEST_SH 2 13990 #define sc_x1_speed_override2_bermon_state_START_TIMER 1 13991 #define sc_x1_speed_override2_bermon_state_BER_MT_INIT 0 13992 13993 /**************************************************************************** 13994 * Enums: sc_x1_speed_override2_rxsm_state_cl49 13995 */ 13996 #define sc_x1_speed_override2_rxsm_state_cl49_RX_HIG_END 128 13997 #define sc_x1_speed_override2_rxsm_state_cl49_RX_HIG_START 64 13998 #define sc_x1_speed_override2_rxsm_state_cl49_RX_LI 32 13999 #define sc_x1_speed_override2_rxsm_state_cl49_RX_E 16 14000 #define sc_x1_speed_override2_rxsm_state_cl49_RX_T 8 14001 #define sc_x1_speed_override2_rxsm_state_cl49_RX_D 4 14002 #define sc_x1_speed_override2_rxsm_state_cl49_RX_C 2 14003 #define sc_x1_speed_override2_rxsm_state_cl49_RX_INIT 1 14004 14005 /**************************************************************************** 14006 * Enums: sc_x1_speed_override2_r_type 14007 */ 14008 #define sc_x1_speed_override2_r_type_BAD_R_TYPE 15 14009 #define sc_x1_speed_override2_r_type_R_TYPE_B0 11 14010 #define sc_x1_speed_override2_r_type_R_TYPE_OB 10 14011 #define sc_x1_speed_override2_r_type_R_TYPE_B1 9 14012 #define sc_x1_speed_override2_r_type_R_TYPE_DB 8 14013 #define sc_x1_speed_override2_r_type_R_TYPE_FC 7 14014 #define sc_x1_speed_override2_r_type_R_TYPE_TB 6 14015 #define sc_x1_speed_override2_r_type_R_TYPE_LI 5 14016 #define sc_x1_speed_override2_r_type_R_TYPE_C 4 14017 #define sc_x1_speed_override2_r_type_R_TYPE_S 3 14018 #define sc_x1_speed_override2_r_type_R_TYPE_T 2 14019 #define sc_x1_speed_override2_r_type_R_TYPE_D 1 14020 #define sc_x1_speed_override2_r_type_R_TYPE_E 0 14021 14022 /**************************************************************************** 14023 * Enums: sc_x1_speed_override2_am_lock_state 14024 */ 14025 #define sc_x1_speed_override2_am_lock_state_INVALID_AM 512 14026 #define sc_x1_speed_override2_am_lock_state_GOOD_AM 256 14027 #define sc_x1_speed_override2_am_lock_state_COMP_AM 128 14028 #define sc_x1_speed_override2_am_lock_state_TIMER_2 64 14029 #define sc_x1_speed_override2_am_lock_state_AM_2_GOOD 32 14030 #define sc_x1_speed_override2_am_lock_state_COMP_2ND 16 14031 #define sc_x1_speed_override2_am_lock_state_TIMER_1 8 14032 #define sc_x1_speed_override2_am_lock_state_FIND_1ST 4 14033 #define sc_x1_speed_override2_am_lock_state_AM_RESET_CNT 2 14034 #define sc_x1_speed_override2_am_lock_state_AM_LOCK_INIT 1 14035 14036 /**************************************************************************** 14037 * Enums: sc_x1_speed_override2_msg_selector 14038 */ 14039 #define sc_x1_speed_override2_msg_selector_RESERVED 0 14040 #define sc_x1_speed_override2_msg_selector_VALUE_802p3 1 14041 #define sc_x1_speed_override2_msg_selector_VALUE_802p9 2 14042 #define sc_x1_speed_override2_msg_selector_VALUE_802p5 3 14043 #define sc_x1_speed_override2_msg_selector_VALUE_1394 4 14044 14045 /**************************************************************************** 14046 * Enums: sc_x1_speed_override2_synce_enum 14047 */ 14048 #define sc_x1_speed_override2_synce_enum_SYNCE_NO_DIV 0 14049 #define sc_x1_speed_override2_synce_enum_SYNCE_DIV_7 1 14050 #define sc_x1_speed_override2_synce_enum_SYNCE_DIV_11 2 14051 14052 /**************************************************************************** 14053 * Enums: sc_x1_speed_override2_synce_enum_stage0 14054 */ 14055 #define sc_x1_speed_override2_synce_enum_stage0_SYNCE_NO_DIV 0 14056 #define sc_x1_speed_override2_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 14057 #define sc_x1_speed_override2_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 14058 14059 /**************************************************************************** 14060 * Enums: sc_x1_speed_override2_cl91_sync_state 14061 */ 14062 #define sc_x1_speed_override2_cl91_sync_state_FIND_1ST 0 14063 #define sc_x1_speed_override2_cl91_sync_state_COUNT_NEXT 1 14064 #define sc_x1_speed_override2_cl91_sync_state_COMP_2ND 2 14065 #define sc_x1_speed_override2_cl91_sync_state_TWO_GOOD 3 14066 14067 /**************************************************************************** 14068 * Enums: sc_x1_speed_override2_cl91_algn_state 14069 */ 14070 #define sc_x1_speed_override2_cl91_algn_state_LOSS_OF_ALIGNMENT 0 14071 #define sc_x1_speed_override2_cl91_algn_state_DESKEW 1 14072 #define sc_x1_speed_override2_cl91_algn_state_DESKEW_FAIL 2 14073 #define sc_x1_speed_override2_cl91_algn_state_ALIGN_ACQUIRED 3 14074 #define sc_x1_speed_override2_cl91_algn_state_CW_GOOD 4 14075 #define sc_x1_speed_override2_cl91_algn_state_CW_BAD 5 14076 #define sc_x1_speed_override2_cl91_algn_state_THREE_BAD 6 14077 14078 /**************************************************************************** 14079 * Enums: sc_x1_speed_override2_fec_sel_override 14080 */ 14081 #define sc_x1_speed_override2_fec_sel_override_NO_OVERRIDE 0 14082 #define sc_x1_speed_override2_fec_sel_override_NO_FEC 1 14083 #define sc_x1_speed_override2_fec_sel_override_FEC_CL74 2 14084 #define sc_x1_speed_override2_fec_sel_override_FEC_CL91 3 14085 14086 /**************************************************************************** 14087 * Enums: sc_x1_speed_override2_cl91_blksync_mode 14088 */ 14089 #define sc_x1_speed_override2_cl91_blksync_mode_R_BLKSYNC_NO_CL91_FEC 0 14090 #define sc_x1_speed_override2_cl91_blksync_mode_R_BLKSYNC_CL91_QUAD_LANE_FEC 1 14091 #define sc_x1_speed_override2_cl91_blksync_mode_R_BLKSYNC_CL91_DUAL_LANE_FEC 2 14092 #define sc_x1_speed_override2_cl91_blksync_mode_R_BLKSYNC_CL91_SINGLE_LANE_FEC 3 14093 #define sc_x1_speed_override2_cl91_blksync_mode_R_BLKSYNC_CL91_FC_FEC 4 14094 14095 /**************************************************************************** 14096 * Enums: sc_x1_speed_override2_r_merge_mode 14097 */ 14098 #define sc_x1_speed_override2_r_merge_mode_R_MERGE_MODE_BYPASS 0 14099 #define sc_x1_speed_override2_r_merge_mode_R_MERGE_MODE_CL91_FC 1 14100 #define sc_x1_speed_override2_r_merge_mode_R_MERGE_MODE_CL91_SINGLE_LANE 2 14101 #define sc_x1_speed_override2_r_merge_mode_R_MERGE_MODE_CL91_DUAL_LANE 3 14102 #define sc_x1_speed_override2_r_merge_mode_R_MERGE_MODE_CL91_QUAD_LANE 4 14103 14104 /**************************************************************************** 14105 * Enums: sc_x1_speed_override2_r_tc_mode 14106 */ 14107 #define sc_x1_speed_override2_r_tc_mode_R_TC_MODE_SINGLE 0 14108 #define sc_x1_speed_override2_r_tc_mode_R_TC_MODE_DUAL 1 14109 #define sc_x1_speed_override2_r_tc_mode_R_TC_MODE_QUAD 2 14110 14111 /**************************************************************************** 14112 * Enums: sc_x1_speed_override2_r_tc_out_mode 14113 */ 14114 #define sc_x1_speed_override2_r_tc_out_mode_R_TC_OUT_MODE_SINGLE 0 14115 #define sc_x1_speed_override2_r_tc_out_mode_R_TC_OUT_MODE_DUAL 1 14116 #define sc_x1_speed_override2_r_tc_out_mode_R_TC_OUT_MODE_QUAD 2 14117 14118 /**************************************************************************** 14119 * Enums: sc_x1_speed_override2_cl91_fec_mode 14120 */ 14121 #define sc_x1_speed_override2_cl91_fec_mode_NO_CL91_FEC 0 14122 #define sc_x1_speed_override2_cl91_fec_mode_CL91_SINGLE_LANE_FC 1 14123 #define sc_x1_speed_override2_cl91_fec_mode_CL91_SINGLE_LANE_BRCM_PROP 2 14124 #define sc_x1_speed_override2_cl91_fec_mode_CL91_DUAL_LANE_BRCM_PROP 3 14125 #define sc_x1_speed_override2_cl91_fec_mode_CL91_QUAD_LANE 4 14126 #define sc_x1_speed_override2_cl91_fec_mode_IEEE_25G_CL91_SINGLE_LANE 5 14127 14128 /**************************************************************************** 14129 * Enums: sc_x1_speed_override2_am_spacing_mul 14130 */ 14131 #define sc_x1_speed_override2_am_spacing_mul_AM_SPACING_MUL_2 0 14132 #define sc_x1_speed_override2_am_spacing_mul_AM_SPACING_MUL_4 1 14133 #define sc_x1_speed_override2_am_spacing_mul_AM_SPACING_MUL_5 2 14134 #define sc_x1_speed_override2_am_spacing_mul_AM_SPACING_MUL_20 3 14135 14136 /**************************************************************************** 14137 * Enums: sc_x1_speed_override3_cl36TxEEEStates_l 14138 */ 14139 #define sc_x1_speed_override3_cl36TxEEEStates_l_TX_REFRESH 8 14140 #define sc_x1_speed_override3_cl36TxEEEStates_l_TX_QUIET 4 14141 #define sc_x1_speed_override3_cl36TxEEEStates_l_TX_SLEEP 2 14142 #define sc_x1_speed_override3_cl36TxEEEStates_l_TX_ACTIVE 1 14143 14144 /**************************************************************************** 14145 * Enums: sc_x1_speed_override3_cl36TxEEEStates_c 14146 */ 14147 #define sc_x1_speed_override3_cl36TxEEEStates_c_TX_REFRESH 3 14148 #define sc_x1_speed_override3_cl36TxEEEStates_c_TX_QUIET 2 14149 #define sc_x1_speed_override3_cl36TxEEEStates_c_TX_SLEEP 1 14150 #define sc_x1_speed_override3_cl36TxEEEStates_c_TX_ACTIVE 0 14151 14152 /**************************************************************************** 14153 * Enums: sc_x1_speed_override3_cl49TxEEEStates_l 14154 */ 14155 #define sc_x1_speed_override3_cl49TxEEEStates_l_SCR_RESET_2 64 14156 #define sc_x1_speed_override3_cl49TxEEEStates_l_SCR_RESET_1 32 14157 #define sc_x1_speed_override3_cl49TxEEEStates_l_TX_WAKE 16 14158 #define sc_x1_speed_override3_cl49TxEEEStates_l_TX_REFRESH 8 14159 #define sc_x1_speed_override3_cl49TxEEEStates_l_TX_QUIET 4 14160 #define sc_x1_speed_override3_cl49TxEEEStates_l_TX_SLEEP 2 14161 #define sc_x1_speed_override3_cl49TxEEEStates_l_TX_ACTIVE 1 14162 14163 /**************************************************************************** 14164 * Enums: sc_x1_speed_override3_fec_req_enum 14165 */ 14166 #define sc_x1_speed_override3_fec_req_enum_FEC_not_supported 0 14167 #define sc_x1_speed_override3_fec_req_enum_FEC_supported_but_not_requested 1 14168 #define sc_x1_speed_override3_fec_req_enum_invalid_setting 2 14169 #define sc_x1_speed_override3_fec_req_enum_FEC_supported_and_requested 3 14170 14171 /**************************************************************************** 14172 * Enums: sc_x1_speed_override3_cl73_pause_enum 14173 */ 14174 #define sc_x1_speed_override3_cl73_pause_enum_No_PAUSE_ability 0 14175 #define sc_x1_speed_override3_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 14176 #define sc_x1_speed_override3_cl73_pause_enum_Symmetric_PAUSE_ability 1 14177 #define sc_x1_speed_override3_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 14178 14179 /**************************************************************************** 14180 * Enums: sc_x1_speed_override3_cl49TxEEEStates_c 14181 */ 14182 #define sc_x1_speed_override3_cl49TxEEEStates_c_SCR_RESET_2 6 14183 #define sc_x1_speed_override3_cl49TxEEEStates_c_SCR_RESET_1 5 14184 #define sc_x1_speed_override3_cl49TxEEEStates_c_TX_WAKE 4 14185 #define sc_x1_speed_override3_cl49TxEEEStates_c_TX_REFRESH 3 14186 #define sc_x1_speed_override3_cl49TxEEEStates_c_TX_QUIET 2 14187 #define sc_x1_speed_override3_cl49TxEEEStates_c_TX_SLEEP 1 14188 #define sc_x1_speed_override3_cl49TxEEEStates_c_TX_ACTIVE 0 14189 14190 /**************************************************************************** 14191 * Enums: sc_x1_speed_override3_cl36RxEEEStates_l 14192 */ 14193 #define sc_x1_speed_override3_cl36RxEEEStates_l_RX_LINK_FAIL 32 14194 #define sc_x1_speed_override3_cl36RxEEEStates_l_RX_WTF 16 14195 #define sc_x1_speed_override3_cl36RxEEEStates_l_RX_WAKE 8 14196 #define sc_x1_speed_override3_cl36RxEEEStates_l_RX_QUIET 4 14197 #define sc_x1_speed_override3_cl36RxEEEStates_l_RX_SLEEP 2 14198 #define sc_x1_speed_override3_cl36RxEEEStates_l_RX_ACTIVE 1 14199 14200 /**************************************************************************** 14201 * Enums: sc_x1_speed_override3_cl36RxEEEStates_c 14202 */ 14203 #define sc_x1_speed_override3_cl36RxEEEStates_c_RX_LINK_FAIL 5 14204 #define sc_x1_speed_override3_cl36RxEEEStates_c_RX_WTF 4 14205 #define sc_x1_speed_override3_cl36RxEEEStates_c_RX_WAKE 3 14206 #define sc_x1_speed_override3_cl36RxEEEStates_c_RX_QUIET 2 14207 #define sc_x1_speed_override3_cl36RxEEEStates_c_RX_SLEEP 1 14208 #define sc_x1_speed_override3_cl36RxEEEStates_c_RX_ACTIVE 0 14209 14210 /**************************************************************************** 14211 * Enums: sc_x1_speed_override3_cl49RxEEEStates_l 14212 */ 14213 #define sc_x1_speed_override3_cl49RxEEEStates_l_RX_LINK_FAIL 32 14214 #define sc_x1_speed_override3_cl49RxEEEStates_l_RX_WTF 16 14215 #define sc_x1_speed_override3_cl49RxEEEStates_l_RX_WAKE 8 14216 #define sc_x1_speed_override3_cl49RxEEEStates_l_RX_QUIET 4 14217 #define sc_x1_speed_override3_cl49RxEEEStates_l_RX_SLEEP 2 14218 #define sc_x1_speed_override3_cl49RxEEEStates_l_RX_ACTIVE 1 14219 14220 /**************************************************************************** 14221 * Enums: sc_x1_speed_override3_cl49RxEEEStates_c 14222 */ 14223 #define sc_x1_speed_override3_cl49RxEEEStates_c_RX_LINK_FAIL 5 14224 #define sc_x1_speed_override3_cl49RxEEEStates_c_RX_WTF 4 14225 #define sc_x1_speed_override3_cl49RxEEEStates_c_RX_WAKE 3 14226 #define sc_x1_speed_override3_cl49RxEEEStates_c_RX_QUIET 2 14227 #define sc_x1_speed_override3_cl49RxEEEStates_c_RX_SLEEP 1 14228 #define sc_x1_speed_override3_cl49RxEEEStates_c_RX_ACTIVE 0 14229 14230 /**************************************************************************** 14231 * Enums: sc_x1_speed_override3_cl48TxEEEStates_l 14232 */ 14233 #define sc_x1_speed_override3_cl48TxEEEStates_l_TX_REFRESH 8 14234 #define sc_x1_speed_override3_cl48TxEEEStates_l_TX_QUIET 4 14235 #define sc_x1_speed_override3_cl48TxEEEStates_l_TX_SLEEP 2 14236 #define sc_x1_speed_override3_cl48TxEEEStates_l_TX_ACTIVE 1 14237 14238 /**************************************************************************** 14239 * Enums: sc_x1_speed_override3_cl48TxEEEStates_c 14240 */ 14241 #define sc_x1_speed_override3_cl48TxEEEStates_c_TX_REFRESH 3 14242 #define sc_x1_speed_override3_cl48TxEEEStates_c_TX_QUIET 2 14243 #define sc_x1_speed_override3_cl48TxEEEStates_c_TX_SLEEP 1 14244 #define sc_x1_speed_override3_cl48TxEEEStates_c_TX_ACTIVE 0 14245 14246 /**************************************************************************** 14247 * Enums: sc_x1_speed_override3_cl48RxEEEStates_l 14248 */ 14249 #define sc_x1_speed_override3_cl48RxEEEStates_l_RX_LINK_FAIL 32 14250 #define sc_x1_speed_override3_cl48RxEEEStates_l_RX_WAKE 16 14251 #define sc_x1_speed_override3_cl48RxEEEStates_l_RX_QUIET 8 14252 #define sc_x1_speed_override3_cl48RxEEEStates_l_RX_DEACT 4 14253 #define sc_x1_speed_override3_cl48RxEEEStates_l_RX_SLEEP 2 14254 #define sc_x1_speed_override3_cl48RxEEEStates_l_RX_ACTIVE 1 14255 14256 /**************************************************************************** 14257 * Enums: sc_x1_speed_override3_cl48RxEEEStates_c 14258 */ 14259 #define sc_x1_speed_override3_cl48RxEEEStates_c_RX_LINK_FAIL 5 14260 #define sc_x1_speed_override3_cl48RxEEEStates_c_RX_WAKE 4 14261 #define sc_x1_speed_override3_cl48RxEEEStates_c_RX_QUIET 3 14262 #define sc_x1_speed_override3_cl48RxEEEStates_c_RX_DEACT 2 14263 #define sc_x1_speed_override3_cl48RxEEEStates_c_RX_SLEEP 1 14264 #define sc_x1_speed_override3_cl48RxEEEStates_c_RX_ACTIVE 0 14265 14266 /**************************************************************************** 14267 * Enums: sc_x1_speed_override3_IQP_Options 14268 */ 14269 #define sc_x1_speed_override3_IQP_Options_i50uA 0 14270 #define sc_x1_speed_override3_IQP_Options_i100uA 1 14271 #define sc_x1_speed_override3_IQP_Options_i150uA 2 14272 #define sc_x1_speed_override3_IQP_Options_i200uA 3 14273 #define sc_x1_speed_override3_IQP_Options_i250uA 4 14274 #define sc_x1_speed_override3_IQP_Options_i300uA 5 14275 #define sc_x1_speed_override3_IQP_Options_i350uA 6 14276 #define sc_x1_speed_override3_IQP_Options_i400uA 7 14277 #define sc_x1_speed_override3_IQP_Options_i450uA 8 14278 #define sc_x1_speed_override3_IQP_Options_i500uA 9 14279 #define sc_x1_speed_override3_IQP_Options_i550uA 10 14280 #define sc_x1_speed_override3_IQP_Options_i600uA 11 14281 #define sc_x1_speed_override3_IQP_Options_i650uA 12 14282 #define sc_x1_speed_override3_IQP_Options_i700uA 13 14283 #define sc_x1_speed_override3_IQP_Options_i750uA 14 14284 #define sc_x1_speed_override3_IQP_Options_i800uA 15 14285 14286 /**************************************************************************** 14287 * Enums: sc_x1_speed_override3_IDriver_Options 14288 */ 14289 #define sc_x1_speed_override3_IDriver_Options_v680mV 0 14290 #define sc_x1_speed_override3_IDriver_Options_v730mV 1 14291 #define sc_x1_speed_override3_IDriver_Options_v780mV 2 14292 #define sc_x1_speed_override3_IDriver_Options_v830mV 3 14293 #define sc_x1_speed_override3_IDriver_Options_v880mV 4 14294 #define sc_x1_speed_override3_IDriver_Options_v930mV 5 14295 #define sc_x1_speed_override3_IDriver_Options_v980mV 6 14296 #define sc_x1_speed_override3_IDriver_Options_v1010mV 7 14297 #define sc_x1_speed_override3_IDriver_Options_v1040mV 8 14298 #define sc_x1_speed_override3_IDriver_Options_v1060mV 9 14299 #define sc_x1_speed_override3_IDriver_Options_v1070mV 10 14300 #define sc_x1_speed_override3_IDriver_Options_v1080mV 11 14301 #define sc_x1_speed_override3_IDriver_Options_v1085mV 12 14302 #define sc_x1_speed_override3_IDriver_Options_v1090mV 13 14303 #define sc_x1_speed_override3_IDriver_Options_v1095mV 14 14304 #define sc_x1_speed_override3_IDriver_Options_v1100mV 15 14305 14306 /**************************************************************************** 14307 * Enums: sc_x1_speed_override3_operationModes 14308 */ 14309 #define sc_x1_speed_override3_operationModes_XGXS 0 14310 #define sc_x1_speed_override3_operationModes_XGXG_nCC 1 14311 #define sc_x1_speed_override3_operationModes_Indlane_OS8 4 14312 #define sc_x1_speed_override3_operationModes_IndLane_OS5 5 14313 #define sc_x1_speed_override3_operationModes_PCI 7 14314 #define sc_x1_speed_override3_operationModes_XGXS_nLQ 8 14315 #define sc_x1_speed_override3_operationModes_XGXS_nLQnCC 9 14316 #define sc_x1_speed_override3_operationModes_PBypass 10 14317 #define sc_x1_speed_override3_operationModes_PBypass_nDSK 11 14318 #define sc_x1_speed_override3_operationModes_ComboCoreMode 12 14319 #define sc_x1_speed_override3_operationModes_Clocks_off 15 14320 14321 /**************************************************************************** 14322 * Enums: sc_x1_speed_override3_actualSpeeds 14323 */ 14324 #define sc_x1_speed_override3_actualSpeeds_dr_10M 0 14325 #define sc_x1_speed_override3_actualSpeeds_dr_100M 1 14326 #define sc_x1_speed_override3_actualSpeeds_dr_1G 2 14327 #define sc_x1_speed_override3_actualSpeeds_dr_2p5G 3 14328 #define sc_x1_speed_override3_actualSpeeds_dr_5G_X4 4 14329 #define sc_x1_speed_override3_actualSpeeds_dr_6G_X4 5 14330 #define sc_x1_speed_override3_actualSpeeds_dr_10G_HiG 6 14331 #define sc_x1_speed_override3_actualSpeeds_dr_10G_CX4 7 14332 #define sc_x1_speed_override3_actualSpeeds_dr_12G_HiG 8 14333 #define sc_x1_speed_override3_actualSpeeds_dr_12p5G_X4 9 14334 #define sc_x1_speed_override3_actualSpeeds_dr_13G_X4 10 14335 #define sc_x1_speed_override3_actualSpeeds_dr_15G_X4 11 14336 #define sc_x1_speed_override3_actualSpeeds_dr_16G_X4 12 14337 #define sc_x1_speed_override3_actualSpeeds_dr_1G_KX 13 14338 #define sc_x1_speed_override3_actualSpeeds_dr_10G_KX4 14 14339 #define sc_x1_speed_override3_actualSpeeds_dr_10G_KR 15 14340 #define sc_x1_speed_override3_actualSpeeds_dr_5G 16 14341 #define sc_x1_speed_override3_actualSpeeds_dr_6p4G 17 14342 #define sc_x1_speed_override3_actualSpeeds_dr_20G_X4 18 14343 #define sc_x1_speed_override3_actualSpeeds_dr_21G_X4 19 14344 #define sc_x1_speed_override3_actualSpeeds_dr_25G_X4 20 14345 #define sc_x1_speed_override3_actualSpeeds_dr_10G_HiG_DXGXS 21 14346 #define sc_x1_speed_override3_actualSpeeds_dr_10G_DXGXS 22 14347 #define sc_x1_speed_override3_actualSpeeds_dr_10p5G_HiG_DXGXS 23 14348 #define sc_x1_speed_override3_actualSpeeds_dr_10p5G_DXGXS 24 14349 #define sc_x1_speed_override3_actualSpeeds_dr_12p773G_HiG_DXGXS 25 14350 #define sc_x1_speed_override3_actualSpeeds_dr_12p773G_DXGXS 26 14351 #define sc_x1_speed_override3_actualSpeeds_dr_10G_XFI 27 14352 #define sc_x1_speed_override3_actualSpeeds_dr_40G 28 14353 #define sc_x1_speed_override3_actualSpeeds_dr_20G_HiG_DXGXS 29 14354 #define sc_x1_speed_override3_actualSpeeds_dr_20G_DXGXS 30 14355 #define sc_x1_speed_override3_actualSpeeds_dr_10G_SFI 31 14356 #define sc_x1_speed_override3_actualSpeeds_dr_31p5G 32 14357 #define sc_x1_speed_override3_actualSpeeds_dr_32p7G 33 14358 #define sc_x1_speed_override3_actualSpeeds_dr_20G_SCR 34 14359 #define sc_x1_speed_override3_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 14360 #define sc_x1_speed_override3_actualSpeeds_dr_10G_DXGXS_SCR 36 14361 #define sc_x1_speed_override3_actualSpeeds_dr_12G_R2 37 14362 #define sc_x1_speed_override3_actualSpeeds_dr_10G_X2 38 14363 #define sc_x1_speed_override3_actualSpeeds_dr_40G_KR4 39 14364 #define sc_x1_speed_override3_actualSpeeds_dr_40G_CR4 40 14365 #define sc_x1_speed_override3_actualSpeeds_dr_100G_CR10 41 14366 #define sc_x1_speed_override3_actualSpeeds_dr_15p75G_DXGXS 44 14367 #define sc_x1_speed_override3_actualSpeeds_dr_20G_KR2 57 14368 #define sc_x1_speed_override3_actualSpeeds_dr_20G_CR2 58 14369 14370 /**************************************************************************** 14371 * Enums: sc_x1_speed_override3_actualSpeedsMisc1 14372 */ 14373 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_2500BRCM_X1 16 14374 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_5000BRCM_X4 17 14375 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_6000BRCM_X4 18 14376 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_10GHiGig_X4 19 14377 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_10GBASE_CX4 20 14378 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_12GHiGig_X4 21 14379 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 14380 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_13GHiGig_X4 23 14381 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_15GHiGig_X4 24 14382 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_16GHiGig_X4 25 14383 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_5000BRCM_X1 26 14384 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_6363BRCM_X1 27 14385 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_20GHiGig_X4 28 14386 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_21GHiGig_X4 29 14387 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 14388 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 14389 14390 /**************************************************************************** 14391 * Enums: sc_x1_speed_override3_IndLaneModes 14392 */ 14393 #define sc_x1_speed_override3_IndLaneModes_SWSDR_div2 0 14394 #define sc_x1_speed_override3_IndLaneModes_SWSDR_div1 1 14395 #define sc_x1_speed_override3_IndLaneModes_DWSDR_div2 2 14396 #define sc_x1_speed_override3_IndLaneModes_DWSDR_div1 3 14397 14398 /**************************************************************************** 14399 * Enums: sc_x1_speed_override3_prbsSelect 14400 */ 14401 #define sc_x1_speed_override3_prbsSelect_prbs7 0 14402 #define sc_x1_speed_override3_prbsSelect_prbs15 1 14403 #define sc_x1_speed_override3_prbsSelect_prbs23 2 14404 #define sc_x1_speed_override3_prbsSelect_prbs31 3 14405 14406 /**************************************************************************** 14407 * Enums: sc_x1_speed_override3_vcoDivider 14408 */ 14409 #define sc_x1_speed_override3_vcoDivider_div32 0 14410 #define sc_x1_speed_override3_vcoDivider_div36 1 14411 #define sc_x1_speed_override3_vcoDivider_div40 2 14412 #define sc_x1_speed_override3_vcoDivider_div42 3 14413 #define sc_x1_speed_override3_vcoDivider_div48 4 14414 #define sc_x1_speed_override3_vcoDivider_div50 5 14415 #define sc_x1_speed_override3_vcoDivider_div52 6 14416 #define sc_x1_speed_override3_vcoDivider_div54 7 14417 #define sc_x1_speed_override3_vcoDivider_div60 8 14418 #define sc_x1_speed_override3_vcoDivider_div64 9 14419 #define sc_x1_speed_override3_vcoDivider_div66 10 14420 #define sc_x1_speed_override3_vcoDivider_div68 11 14421 #define sc_x1_speed_override3_vcoDivider_div70 12 14422 #define sc_x1_speed_override3_vcoDivider_div80 13 14423 #define sc_x1_speed_override3_vcoDivider_div92 14 14424 #define sc_x1_speed_override3_vcoDivider_div100 15 14425 14426 /**************************************************************************** 14427 * Enums: sc_x1_speed_override3_refClkSelect 14428 */ 14429 #define sc_x1_speed_override3_refClkSelect_clk_25MHz 0 14430 #define sc_x1_speed_override3_refClkSelect_clk_100MHz 1 14431 #define sc_x1_speed_override3_refClkSelect_clk_125MHz 2 14432 #define sc_x1_speed_override3_refClkSelect_clk_156p25MHz 3 14433 #define sc_x1_speed_override3_refClkSelect_clk_187p5MHz 4 14434 #define sc_x1_speed_override3_refClkSelect_clk_161p25Mhz 5 14435 #define sc_x1_speed_override3_refClkSelect_clk_50Mhz 6 14436 #define sc_x1_speed_override3_refClkSelect_clk_106p25Mhz 7 14437 14438 /**************************************************************************** 14439 * Enums: sc_x1_speed_override3_aerMMDdevTypeSelect 14440 */ 14441 #define sc_x1_speed_override3_aerMMDdevTypeSelect_combo_core 0 14442 #define sc_x1_speed_override3_aerMMDdevTypeSelect_PMA_PMD 1 14443 #define sc_x1_speed_override3_aerMMDdevTypeSelect_PCS 3 14444 #define sc_x1_speed_override3_aerMMDdevTypeSelect_PHY 4 14445 #define sc_x1_speed_override3_aerMMDdevTypeSelect_DTE 5 14446 #define sc_x1_speed_override3_aerMMDdevTypeSelect_CL73_AN 7 14447 14448 /**************************************************************************** 14449 * Enums: sc_x1_speed_override3_aerMMDportSelect 14450 */ 14451 #define sc_x1_speed_override3_aerMMDportSelect_ln0 0 14452 #define sc_x1_speed_override3_aerMMDportSelect_ln1 1 14453 #define sc_x1_speed_override3_aerMMDportSelect_ln2 2 14454 #define sc_x1_speed_override3_aerMMDportSelect_ln3 3 14455 #define sc_x1_speed_override3_aerMMDportSelect_BCST_ln0_1_2_3 511 14456 #define sc_x1_speed_override3_aerMMDportSelect_BCST_ln0_1 512 14457 #define sc_x1_speed_override3_aerMMDportSelect_BCST_ln2_3 513 14458 14459 /**************************************************************************** 14460 * Enums: sc_x1_speed_override3_firmwareModeSelect 14461 */ 14462 #define sc_x1_speed_override3_firmwareModeSelect_DEFAULT 0 14463 #define sc_x1_speed_override3_firmwareModeSelect_SFP_OPT_LR 1 14464 #define sc_x1_speed_override3_firmwareModeSelect_SFP_DAC 2 14465 #define sc_x1_speed_override3_firmwareModeSelect_XLAUI 3 14466 #define sc_x1_speed_override3_firmwareModeSelect_LONG_CH_6G 4 14467 14468 /**************************************************************************** 14469 * Enums: sc_x1_speed_override3_tempIdxSelect 14470 */ 14471 #define sc_x1_speed_override3_tempIdxSelect_LTE__22p9C 15 14472 #define sc_x1_speed_override3_tempIdxSelect_LTE__12p6C 14 14473 #define sc_x1_speed_override3_tempIdxSelect_LTE__3p0C 13 14474 #define sc_x1_speed_override3_tempIdxSelect_LTE_6p7C 12 14475 #define sc_x1_speed_override3_tempIdxSelect_LTE_16p4C 11 14476 #define sc_x1_speed_override3_tempIdxSelect_LTE_26p6C 10 14477 #define sc_x1_speed_override3_tempIdxSelect_LTE_36p3C 9 14478 #define sc_x1_speed_override3_tempIdxSelect_LTE_46p0C 8 14479 #define sc_x1_speed_override3_tempIdxSelect_LTE_56p2C 7 14480 #define sc_x1_speed_override3_tempIdxSelect_LTE_65p9C 6 14481 #define sc_x1_speed_override3_tempIdxSelect_LTE_75p6C 5 14482 #define sc_x1_speed_override3_tempIdxSelect_LTE_85p3C 4 14483 #define sc_x1_speed_override3_tempIdxSelect_LTE_95p5C 3 14484 #define sc_x1_speed_override3_tempIdxSelect_LTE_105p2C 2 14485 #define sc_x1_speed_override3_tempIdxSelect_LTE_114p9C 1 14486 #define sc_x1_speed_override3_tempIdxSelect_LTE_125p1C 0 14487 14488 /**************************************************************************** 14489 * Enums: sc_x1_speed_override3_port_mode 14490 */ 14491 #define sc_x1_speed_override3_port_mode_QUAD_PORT 0 14492 #define sc_x1_speed_override3_port_mode_TRI_1_PORT 1 14493 #define sc_x1_speed_override3_port_mode_TRI_2_PORT 2 14494 #define sc_x1_speed_override3_port_mode_DUAL_PORT 3 14495 #define sc_x1_speed_override3_port_mode_SINGLE_PORT 4 14496 14497 /**************************************************************************** 14498 * Enums: sc_x1_speed_override3_rev_letter_enum 14499 */ 14500 #define sc_x1_speed_override3_rev_letter_enum_REV_A 0 14501 #define sc_x1_speed_override3_rev_letter_enum_REV_B 1 14502 #define sc_x1_speed_override3_rev_letter_enum_REV_C 2 14503 #define sc_x1_speed_override3_rev_letter_enum_REV_D 3 14504 14505 /**************************************************************************** 14506 * Enums: sc_x1_speed_override3_rev_number_enum 14507 */ 14508 #define sc_x1_speed_override3_rev_number_enum_REV_0 0 14509 #define sc_x1_speed_override3_rev_number_enum_REV_1 1 14510 #define sc_x1_speed_override3_rev_number_enum_REV_2 2 14511 #define sc_x1_speed_override3_rev_number_enum_REV_3 3 14512 #define sc_x1_speed_override3_rev_number_enum_REV_4 4 14513 #define sc_x1_speed_override3_rev_number_enum_REV_5 5 14514 #define sc_x1_speed_override3_rev_number_enum_REV_6 6 14515 #define sc_x1_speed_override3_rev_number_enum_REV_7 7 14516 14517 /**************************************************************************** 14518 * Enums: sc_x1_speed_override3_bonding_enum 14519 */ 14520 #define sc_x1_speed_override3_bonding_enum_WIRE_BOND 0 14521 #define sc_x1_speed_override3_bonding_enum_FLIP_CHIP 1 14522 14523 /**************************************************************************** 14524 * Enums: sc_x1_speed_override3_tech_process 14525 */ 14526 #define sc_x1_speed_override3_tech_process_PROCESS_90NM 0 14527 #define sc_x1_speed_override3_tech_process_PROCESS_65NM 1 14528 #define sc_x1_speed_override3_tech_process_PROCESS_40NM 2 14529 #define sc_x1_speed_override3_tech_process_PROCESS_28NM 3 14530 #define sc_x1_speed_override3_tech_process_PROCESS_16NM 4 14531 14532 /**************************************************************************** 14533 * Enums: sc_x1_speed_override3_model_num 14534 */ 14535 #define sc_x1_speed_override3_model_num_SERDES_CL73 0 14536 #define sc_x1_speed_override3_model_num_XGXS_16G 1 14537 #define sc_x1_speed_override3_model_num_HYPERCORE 2 14538 #define sc_x1_speed_override3_model_num_HYPERLITE 3 14539 #define sc_x1_speed_override3_model_num_PCIE_G2_PIPE 4 14540 #define sc_x1_speed_override3_model_num_SERDES_1p25GBd 5 14541 #define sc_x1_speed_override3_model_num_SATA2 6 14542 #define sc_x1_speed_override3_model_num_QSGMII 7 14543 #define sc_x1_speed_override3_model_num_XGXS10G 8 14544 #define sc_x1_speed_override3_model_num_WARPCORE 9 14545 #define sc_x1_speed_override3_model_num_XFICORE 10 14546 #define sc_x1_speed_override3_model_num_RXFI 11 14547 #define sc_x1_speed_override3_model_num_WARPLITE 12 14548 #define sc_x1_speed_override3_model_num_PENTACORE 13 14549 #define sc_x1_speed_override3_model_num_ESM 14 14550 #define sc_x1_speed_override3_model_num_QUAD_SGMII 15 14551 #define sc_x1_speed_override3_model_num_WARPCORE_3 16 14552 #define sc_x1_speed_override3_model_num_TSC 17 14553 #define sc_x1_speed_override3_model_num_TSC4E 18 14554 #define sc_x1_speed_override3_model_num_TSC12E 19 14555 #define sc_x1_speed_override3_model_num_TSC4F 20 14556 #define sc_x1_speed_override3_model_num_TSC4F_GEN2 21 14557 #define sc_x1_speed_override3_model_num_XGXS_CL73_90NM 29 14558 #define sc_x1_speed_override3_model_num_SERDES_CL73_90NM 30 14559 #define sc_x1_speed_override3_model_num_WARPCORE3 32 14560 #define sc_x1_speed_override3_model_num_WARPCORE4_TSC 33 14561 #define sc_x1_speed_override3_model_num_RXAUI 34 14562 14563 /**************************************************************************** 14564 * Enums: sc_x1_speed_override3_payload 14565 */ 14566 #define sc_x1_speed_override3_payload_REPEAT_2_BYTES 0 14567 #define sc_x1_speed_override3_payload_RAMPING 1 14568 #define sc_x1_speed_override3_payload_CL48_CRPAT 2 14569 #define sc_x1_speed_override3_payload_CL48_CJPAT 3 14570 #define sc_x1_speed_override3_payload_CL36_LONG_CRPAT 4 14571 #define sc_x1_speed_override3_payload_CL36_SHORT_CRPAT 5 14572 14573 /**************************************************************************** 14574 * Enums: sc_x1_speed_override3_sc 14575 */ 14576 #define sc_x1_speed_override3_sc_S_10G_CR1 0 14577 #define sc_x1_speed_override3_sc_S_10G_KR1 1 14578 #define sc_x1_speed_override3_sc_S_10G_X1 2 14579 #define sc_x1_speed_override3_sc_S_10G_HG2_CR1 4 14580 #define sc_x1_speed_override3_sc_S_10G_HG2_KR1 5 14581 #define sc_x1_speed_override3_sc_S_10G_HG2_X1 6 14582 #define sc_x1_speed_override3_sc_S_20G_CR1 8 14583 #define sc_x1_speed_override3_sc_S_20G_KR1 9 14584 #define sc_x1_speed_override3_sc_S_20G_X1 10 14585 #define sc_x1_speed_override3_sc_S_20G_HG2_CR1 12 14586 #define sc_x1_speed_override3_sc_S_20G_HG2_KR1 13 14587 #define sc_x1_speed_override3_sc_S_20G_HG2_X1 14 14588 #define sc_x1_speed_override3_sc_S_25G_CR1 16 14589 #define sc_x1_speed_override3_sc_S_25G_KR1 17 14590 #define sc_x1_speed_override3_sc_S_25G_X1 18 14591 #define sc_x1_speed_override3_sc_S_25G_HG2_CR1 20 14592 #define sc_x1_speed_override3_sc_S_25G_HG2_KR1 21 14593 #define sc_x1_speed_override3_sc_S_25G_HG2_X1 22 14594 #define sc_x1_speed_override3_sc_S_20G_CR2 24 14595 #define sc_x1_speed_override3_sc_S_20G_KR2 25 14596 #define sc_x1_speed_override3_sc_S_20G_X2 26 14597 #define sc_x1_speed_override3_sc_S_20G_HG2_CR2 28 14598 #define sc_x1_speed_override3_sc_S_20G_HG2_KR2 29 14599 #define sc_x1_speed_override3_sc_S_20G_HG2_X2 30 14600 #define sc_x1_speed_override3_sc_S_40G_CR2 32 14601 #define sc_x1_speed_override3_sc_S_40G_KR2 33 14602 #define sc_x1_speed_override3_sc_S_40G_X2 34 14603 #define sc_x1_speed_override3_sc_S_40G_HG2_CR2 36 14604 #define sc_x1_speed_override3_sc_S_40G_HG2_KR2 37 14605 #define sc_x1_speed_override3_sc_S_40G_HG2_X2 38 14606 #define sc_x1_speed_override3_sc_S_40G_CR4 40 14607 #define sc_x1_speed_override3_sc_S_40G_KR4 41 14608 #define sc_x1_speed_override3_sc_S_40G_X4 42 14609 #define sc_x1_speed_override3_sc_S_40G_HG2_CR4 44 14610 #define sc_x1_speed_override3_sc_S_40G_HG2_KR4 45 14611 #define sc_x1_speed_override3_sc_S_40G_HG2_X4 46 14612 #define sc_x1_speed_override3_sc_S_50G_CR2 48 14613 #define sc_x1_speed_override3_sc_S_50G_KR2 49 14614 #define sc_x1_speed_override3_sc_S_50G_X2 50 14615 #define sc_x1_speed_override3_sc_S_50G_HG2_CR2 52 14616 #define sc_x1_speed_override3_sc_S_50G_HG2_KR2 53 14617 #define sc_x1_speed_override3_sc_S_50G_HG2_X2 54 14618 #define sc_x1_speed_override3_sc_S_50G_CR4 56 14619 #define sc_x1_speed_override3_sc_S_50G_KR4 57 14620 #define sc_x1_speed_override3_sc_S_50G_X4 58 14621 #define sc_x1_speed_override3_sc_S_50G_HG2_CR4 60 14622 #define sc_x1_speed_override3_sc_S_50G_HG2_KR4 61 14623 #define sc_x1_speed_override3_sc_S_50G_HG2_X4 62 14624 #define sc_x1_speed_override3_sc_S_100G_CR4 64 14625 #define sc_x1_speed_override3_sc_S_100G_KR4 65 14626 #define sc_x1_speed_override3_sc_S_100G_X4 66 14627 #define sc_x1_speed_override3_sc_S_100G_HG2_CR4 68 14628 #define sc_x1_speed_override3_sc_S_100G_HG2_KR4 69 14629 #define sc_x1_speed_override3_sc_S_100G_HG2_X4 70 14630 #define sc_x1_speed_override3_sc_S_CL73_20GVCO 72 14631 #define sc_x1_speed_override3_sc_S_CL73_25GVCO 80 14632 #define sc_x1_speed_override3_sc_S_CL36_20GVCO 88 14633 #define sc_x1_speed_override3_sc_S_CL36_25GVCO 96 14634 #define sc_x1_speed_override3_sc_S_25G_CR_IEEE 112 14635 #define sc_x1_speed_override3_sc_S_25G_CRS_IEEE 113 14636 #define sc_x1_speed_override3_sc_S_25G_KR_IEEE 114 14637 #define sc_x1_speed_override3_sc_S_25G_KRS_IEEE 115 14638 14639 /**************************************************************************** 14640 * Enums: sc_x1_speed_override3_t_fifo_modes 14641 */ 14642 #define sc_x1_speed_override3_t_fifo_modes_T_FIFO_INSERT_NO_AM 0 14643 #define sc_x1_speed_override3_t_fifo_modes_T_FIFO_INSERT_4_AM 1 14644 #define sc_x1_speed_override3_t_fifo_modes_T_FIFO_INSERT_20_AM 2 14645 #define sc_x1_speed_override3_t_fifo_modes_T_FIFO_INSERT_2_AM 3 14646 14647 /**************************************************************************** 14648 * Enums: sc_x1_speed_override3_t_enc_modes 14649 */ 14650 #define sc_x1_speed_override3_t_enc_modes_T_ENC_MODE_BYPASS 0 14651 #define sc_x1_speed_override3_t_enc_modes_T_ENC_MODE_CL49 1 14652 #define sc_x1_speed_override3_t_enc_modes_T_ENC_MODE_CL82 2 14653 14654 /**************************************************************************** 14655 * Enums: sc_x1_speed_override3_btmx_mode 14656 */ 14657 #define sc_x1_speed_override3_btmx_mode_BS_BTMX_MODE_1to1 0 14658 #define sc_x1_speed_override3_btmx_mode_BS_BTMX_MODE_2to1 1 14659 #define sc_x1_speed_override3_btmx_mode_BS_BTMX_MODE_5to1 2 14660 14661 /**************************************************************************** 14662 * Enums: sc_x1_speed_override3_t_type_cl82 14663 */ 14664 #define sc_x1_speed_override3_t_type_cl82_T_TYPE_B1 5 14665 #define sc_x1_speed_override3_t_type_cl82_T_TYPE_C 4 14666 #define sc_x1_speed_override3_t_type_cl82_T_TYPE_S 3 14667 #define sc_x1_speed_override3_t_type_cl82_T_TYPE_T 2 14668 #define sc_x1_speed_override3_t_type_cl82_T_TYPE_D 1 14669 #define sc_x1_speed_override3_t_type_cl82_T_TYPE_E 0 14670 14671 /**************************************************************************** 14672 * Enums: sc_x1_speed_override3_txsm_state_cl82 14673 */ 14674 #define sc_x1_speed_override3_txsm_state_cl82_TX_HIG_END 6 14675 #define sc_x1_speed_override3_txsm_state_cl82_TX_HIG_START 5 14676 #define sc_x1_speed_override3_txsm_state_cl82_TX_E 4 14677 #define sc_x1_speed_override3_txsm_state_cl82_TX_T 3 14678 #define sc_x1_speed_override3_txsm_state_cl82_TX_D 2 14679 #define sc_x1_speed_override3_txsm_state_cl82_TX_C 1 14680 #define sc_x1_speed_override3_txsm_state_cl82_TX_INIT 0 14681 14682 /**************************************************************************** 14683 * Enums: sc_x1_speed_override3_ltxsm_state_cl82 14684 */ 14685 #define sc_x1_speed_override3_ltxsm_state_cl82_TX_HIG_END 64 14686 #define sc_x1_speed_override3_ltxsm_state_cl82_TX_HIG_START 32 14687 #define sc_x1_speed_override3_ltxsm_state_cl82_TX_E 16 14688 #define sc_x1_speed_override3_ltxsm_state_cl82_TX_T 8 14689 #define sc_x1_speed_override3_ltxsm_state_cl82_TX_D 4 14690 #define sc_x1_speed_override3_ltxsm_state_cl82_TX_C 2 14691 #define sc_x1_speed_override3_ltxsm_state_cl82_TX_INIT 1 14692 14693 /**************************************************************************** 14694 * Enums: sc_x1_speed_override3_r_type_coded_cl82 14695 */ 14696 #define sc_x1_speed_override3_r_type_coded_cl82_R_TYPE_B1 32 14697 #define sc_x1_speed_override3_r_type_coded_cl82_R_TYPE_C 16 14698 #define sc_x1_speed_override3_r_type_coded_cl82_R_TYPE_S 8 14699 #define sc_x1_speed_override3_r_type_coded_cl82_R_TYPE_T 4 14700 #define sc_x1_speed_override3_r_type_coded_cl82_R_TYPE_D 2 14701 #define sc_x1_speed_override3_r_type_coded_cl82_R_TYPE_E 1 14702 14703 /**************************************************************************** 14704 * Enums: sc_x1_speed_override3_rxsm_state_cl82 14705 */ 14706 #define sc_x1_speed_override3_rxsm_state_cl82_RX_HIG_END 64 14707 #define sc_x1_speed_override3_rxsm_state_cl82_RX_HIG_START 32 14708 #define sc_x1_speed_override3_rxsm_state_cl82_RX_E 16 14709 #define sc_x1_speed_override3_rxsm_state_cl82_RX_T 8 14710 #define sc_x1_speed_override3_rxsm_state_cl82_RX_D 4 14711 #define sc_x1_speed_override3_rxsm_state_cl82_RX_C 2 14712 #define sc_x1_speed_override3_rxsm_state_cl82_RX_INIT 1 14713 14714 /**************************************************************************** 14715 * Enums: sc_x1_speed_override3_deskew_state 14716 */ 14717 #define sc_x1_speed_override3_deskew_state_ALIGN_ACQUIRED 2 14718 #define sc_x1_speed_override3_deskew_state_LOSS_OF_ALIGNMENT 1 14719 14720 /**************************************************************************** 14721 * Enums: sc_x1_speed_override3_os_mode_enum 14722 */ 14723 #define sc_x1_speed_override3_os_mode_enum_OS_MODE_1 0 14724 #define sc_x1_speed_override3_os_mode_enum_OS_MODE_2 1 14725 #define sc_x1_speed_override3_os_mode_enum_OS_MODE_4 2 14726 #define sc_x1_speed_override3_os_mode_enum_OS_MODE_16p5 8 14727 #define sc_x1_speed_override3_os_mode_enum_OS_MODE_20p625 12 14728 14729 /**************************************************************************** 14730 * Enums: sc_x1_speed_override3_scr_modes 14731 */ 14732 #define sc_x1_speed_override3_scr_modes_T_SCR_MODE_BYPASS 0 14733 #define sc_x1_speed_override3_scr_modes_T_SCR_MODE_CL49 1 14734 #define sc_x1_speed_override3_scr_modes_T_SCR_MODE_40G_2_LANE 2 14735 #define sc_x1_speed_override3_scr_modes_T_SCR_MODE_100G 3 14736 #define sc_x1_speed_override3_scr_modes_T_SCR_MODE_20G 4 14737 #define sc_x1_speed_override3_scr_modes_T_SCR_MODE_40G_4_LANE 5 14738 14739 /**************************************************************************** 14740 * Enums: sc_x1_speed_override3_descr_modes 14741 */ 14742 #define sc_x1_speed_override3_descr_modes_R_DESCR_MODE_BYPASS 0 14743 #define sc_x1_speed_override3_descr_modes_R_DESCR_MODE_CL49 1 14744 #define sc_x1_speed_override3_descr_modes_R_DESCR_MODE_CL82 2 14745 14746 /**************************************************************************** 14747 * Enums: sc_x1_speed_override3_r_dec_tl_mode 14748 */ 14749 #define sc_x1_speed_override3_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 14750 #define sc_x1_speed_override3_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 14751 #define sc_x1_speed_override3_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 14752 14753 /**************************************************************************** 14754 * Enums: sc_x1_speed_override3_r_dec_fsm_mode 14755 */ 14756 #define sc_x1_speed_override3_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 14757 #define sc_x1_speed_override3_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 14758 #define sc_x1_speed_override3_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 14759 14760 /**************************************************************************** 14761 * Enums: sc_x1_speed_override3_r_deskew_mode 14762 */ 14763 #define sc_x1_speed_override3_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 14764 #define sc_x1_speed_override3_r_deskew_mode_R_DESKEW_MODE_20G 1 14765 #define sc_x1_speed_override3_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 14766 #define sc_x1_speed_override3_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 14767 #define sc_x1_speed_override3_r_deskew_mode_R_DESKEW_MODE_100G 4 14768 #define sc_x1_speed_override3_r_deskew_mode_R_DESKEW_MODE_CL49 5 14769 #define sc_x1_speed_override3_r_deskew_mode_R_DESKEW_MODE_CL91_QUAD 6 14770 #define sc_x1_speed_override3_r_deskew_mode_R_DESKEW_MODE_CL91_SINGLE_BRCM 7 14771 #define sc_x1_speed_override3_r_deskew_mode_R_DESKEW_MODE_CL91_DUAL_BRCM 8 14772 #define sc_x1_speed_override3_r_deskew_mode_R_DESKEW_MODE_CL91_FC 9 14773 14774 /**************************************************************************** 14775 * Enums: sc_x1_speed_override3_bs_dist_modes 14776 */ 14777 #define sc_x1_speed_override3_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 14778 #define sc_x1_speed_override3_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 14779 #define sc_x1_speed_override3_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 14780 #define sc_x1_speed_override3_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 14781 14782 /**************************************************************************** 14783 * Enums: sc_x1_speed_override3_cl49_t_type 14784 */ 14785 #define sc_x1_speed_override3_cl49_t_type_BAD_T_TYPE 15 14786 #define sc_x1_speed_override3_cl49_t_type_T_TYPE_B0 11 14787 #define sc_x1_speed_override3_cl49_t_type_T_TYPE_OB 10 14788 #define sc_x1_speed_override3_cl49_t_type_T_TYPE_B1 9 14789 #define sc_x1_speed_override3_cl49_t_type_T_TYPE_DB 8 14790 #define sc_x1_speed_override3_cl49_t_type_T_TYPE_FC 7 14791 #define sc_x1_speed_override3_cl49_t_type_T_TYPE_TB 6 14792 #define sc_x1_speed_override3_cl49_t_type_T_TYPE_LI 5 14793 #define sc_x1_speed_override3_cl49_t_type_T_TYPE_C 4 14794 #define sc_x1_speed_override3_cl49_t_type_T_TYPE_S 3 14795 #define sc_x1_speed_override3_cl49_t_type_T_TYPE_T 2 14796 #define sc_x1_speed_override3_cl49_t_type_T_TYPE_D 1 14797 #define sc_x1_speed_override3_cl49_t_type_T_TYPE_E 0 14798 14799 /**************************************************************************** 14800 * Enums: sc_x1_speed_override3_cl49_txsm_states 14801 */ 14802 #define sc_x1_speed_override3_cl49_txsm_states_TX_HIG_END 7 14803 #define sc_x1_speed_override3_cl49_txsm_states_TX_HIG_START 6 14804 #define sc_x1_speed_override3_cl49_txsm_states_TX_LI 5 14805 #define sc_x1_speed_override3_cl49_txsm_states_TX_E 4 14806 #define sc_x1_speed_override3_cl49_txsm_states_TX_T 3 14807 #define sc_x1_speed_override3_cl49_txsm_states_TX_D 2 14808 #define sc_x1_speed_override3_cl49_txsm_states_TX_C 1 14809 #define sc_x1_speed_override3_cl49_txsm_states_TX_INIT 0 14810 14811 /**************************************************************************** 14812 * Enums: sc_x1_speed_override3_cl49_ltxsm_states 14813 */ 14814 #define sc_x1_speed_override3_cl49_ltxsm_states_TX_HIG_END 128 14815 #define sc_x1_speed_override3_cl49_ltxsm_states_TX_HIG_START 64 14816 #define sc_x1_speed_override3_cl49_ltxsm_states_TX_LI 32 14817 #define sc_x1_speed_override3_cl49_ltxsm_states_TX_E 16 14818 #define sc_x1_speed_override3_cl49_ltxsm_states_TX_T 8 14819 #define sc_x1_speed_override3_cl49_ltxsm_states_TX_D 4 14820 #define sc_x1_speed_override3_cl49_ltxsm_states_TX_C 2 14821 #define sc_x1_speed_override3_cl49_ltxsm_states_TX_INIT 1 14822 14823 /**************************************************************************** 14824 * Enums: sc_x1_speed_override3_burst_error_mode 14825 */ 14826 #define sc_x1_speed_override3_burst_error_mode_BURST_ERROR_11_BITS 0 14827 #define sc_x1_speed_override3_burst_error_mode_BURST_ERROR_16_BITS 1 14828 #define sc_x1_speed_override3_burst_error_mode_BURST_ERROR_17_BITS 2 14829 #define sc_x1_speed_override3_burst_error_mode_BURST_ERROR_18_BITS 3 14830 #define sc_x1_speed_override3_burst_error_mode_BURST_ERROR_19_BITS 4 14831 #define sc_x1_speed_override3_burst_error_mode_BURST_ERROR_20_BITS 5 14832 #define sc_x1_speed_override3_burst_error_mode_BURST_ERROR_21_BITS 6 14833 #define sc_x1_speed_override3_burst_error_mode_BURST_ERROR_22_BITS 7 14834 #define sc_x1_speed_override3_burst_error_mode_BURST_ERROR_23_BITS 8 14835 #define sc_x1_speed_override3_burst_error_mode_BURST_ERROR_24_BITS 9 14836 #define sc_x1_speed_override3_burst_error_mode_BURST_ERROR_25_BITS 10 14837 #define sc_x1_speed_override3_burst_error_mode_BURST_ERROR_26_BITS 11 14838 #define sc_x1_speed_override3_burst_error_mode_BURST_ERROR_27_BITS 12 14839 #define sc_x1_speed_override3_burst_error_mode_BURST_ERROR_28_BITS 13 14840 #define sc_x1_speed_override3_burst_error_mode_BURST_ERROR_29_BITS 14 14841 #define sc_x1_speed_override3_burst_error_mode_BURST_ERROR_30_BITS 15 14842 #define sc_x1_speed_override3_burst_error_mode_BURST_ERROR_31_BITS 16 14843 #define sc_x1_speed_override3_burst_error_mode_BURST_ERROR_32_BITS 17 14844 #define sc_x1_speed_override3_burst_error_mode_BURST_ERROR_33_BITS 18 14845 #define sc_x1_speed_override3_burst_error_mode_BURST_ERROR_34_BITS 19 14846 #define sc_x1_speed_override3_burst_error_mode_BURST_ERROR_35_BITS 20 14847 #define sc_x1_speed_override3_burst_error_mode_BURST_ERROR_36_BITS 21 14848 #define sc_x1_speed_override3_burst_error_mode_BURST_ERROR_37_BITS 22 14849 #define sc_x1_speed_override3_burst_error_mode_BURST_ERROR_38_BITS 23 14850 #define sc_x1_speed_override3_burst_error_mode_BURST_ERROR_39_BITS 24 14851 #define sc_x1_speed_override3_burst_error_mode_BURST_ERROR_40_BITS 25 14852 #define sc_x1_speed_override3_burst_error_mode_BURST_ERROR_41_BITS 26 14853 14854 /**************************************************************************** 14855 * Enums: sc_x1_speed_override3_bermon_state 14856 */ 14857 #define sc_x1_speed_override3_bermon_state_HI_BER 4 14858 #define sc_x1_speed_override3_bermon_state_GOOD_BER 3 14859 #define sc_x1_speed_override3_bermon_state_BER_TEST_SH 2 14860 #define sc_x1_speed_override3_bermon_state_START_TIMER 1 14861 #define sc_x1_speed_override3_bermon_state_BER_MT_INIT 0 14862 14863 /**************************************************************************** 14864 * Enums: sc_x1_speed_override3_rxsm_state_cl49 14865 */ 14866 #define sc_x1_speed_override3_rxsm_state_cl49_RX_HIG_END 128 14867 #define sc_x1_speed_override3_rxsm_state_cl49_RX_HIG_START 64 14868 #define sc_x1_speed_override3_rxsm_state_cl49_RX_LI 32 14869 #define sc_x1_speed_override3_rxsm_state_cl49_RX_E 16 14870 #define sc_x1_speed_override3_rxsm_state_cl49_RX_T 8 14871 #define sc_x1_speed_override3_rxsm_state_cl49_RX_D 4 14872 #define sc_x1_speed_override3_rxsm_state_cl49_RX_C 2 14873 #define sc_x1_speed_override3_rxsm_state_cl49_RX_INIT 1 14874 14875 /**************************************************************************** 14876 * Enums: sc_x1_speed_override3_r_type 14877 */ 14878 #define sc_x1_speed_override3_r_type_BAD_R_TYPE 15 14879 #define sc_x1_speed_override3_r_type_R_TYPE_B0 11 14880 #define sc_x1_speed_override3_r_type_R_TYPE_OB 10 14881 #define sc_x1_speed_override3_r_type_R_TYPE_B1 9 14882 #define sc_x1_speed_override3_r_type_R_TYPE_DB 8 14883 #define sc_x1_speed_override3_r_type_R_TYPE_FC 7 14884 #define sc_x1_speed_override3_r_type_R_TYPE_TB 6 14885 #define sc_x1_speed_override3_r_type_R_TYPE_LI 5 14886 #define sc_x1_speed_override3_r_type_R_TYPE_C 4 14887 #define sc_x1_speed_override3_r_type_R_TYPE_S 3 14888 #define sc_x1_speed_override3_r_type_R_TYPE_T 2 14889 #define sc_x1_speed_override3_r_type_R_TYPE_D 1 14890 #define sc_x1_speed_override3_r_type_R_TYPE_E 0 14891 14892 /**************************************************************************** 14893 * Enums: sc_x1_speed_override3_am_lock_state 14894 */ 14895 #define sc_x1_speed_override3_am_lock_state_INVALID_AM 512 14896 #define sc_x1_speed_override3_am_lock_state_GOOD_AM 256 14897 #define sc_x1_speed_override3_am_lock_state_COMP_AM 128 14898 #define sc_x1_speed_override3_am_lock_state_TIMER_2 64 14899 #define sc_x1_speed_override3_am_lock_state_AM_2_GOOD 32 14900 #define sc_x1_speed_override3_am_lock_state_COMP_2ND 16 14901 #define sc_x1_speed_override3_am_lock_state_TIMER_1 8 14902 #define sc_x1_speed_override3_am_lock_state_FIND_1ST 4 14903 #define sc_x1_speed_override3_am_lock_state_AM_RESET_CNT 2 14904 #define sc_x1_speed_override3_am_lock_state_AM_LOCK_INIT 1 14905 14906 /**************************************************************************** 14907 * Enums: sc_x1_speed_override3_msg_selector 14908 */ 14909 #define sc_x1_speed_override3_msg_selector_RESERVED 0 14910 #define sc_x1_speed_override3_msg_selector_VALUE_802p3 1 14911 #define sc_x1_speed_override3_msg_selector_VALUE_802p9 2 14912 #define sc_x1_speed_override3_msg_selector_VALUE_802p5 3 14913 #define sc_x1_speed_override3_msg_selector_VALUE_1394 4 14914 14915 /**************************************************************************** 14916 * Enums: sc_x1_speed_override3_synce_enum 14917 */ 14918 #define sc_x1_speed_override3_synce_enum_SYNCE_NO_DIV 0 14919 #define sc_x1_speed_override3_synce_enum_SYNCE_DIV_7 1 14920 #define sc_x1_speed_override3_synce_enum_SYNCE_DIV_11 2 14921 14922 /**************************************************************************** 14923 * Enums: sc_x1_speed_override3_synce_enum_stage0 14924 */ 14925 #define sc_x1_speed_override3_synce_enum_stage0_SYNCE_NO_DIV 0 14926 #define sc_x1_speed_override3_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 14927 #define sc_x1_speed_override3_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 14928 14929 /**************************************************************************** 14930 * Enums: sc_x1_speed_override3_cl91_sync_state 14931 */ 14932 #define sc_x1_speed_override3_cl91_sync_state_FIND_1ST 0 14933 #define sc_x1_speed_override3_cl91_sync_state_COUNT_NEXT 1 14934 #define sc_x1_speed_override3_cl91_sync_state_COMP_2ND 2 14935 #define sc_x1_speed_override3_cl91_sync_state_TWO_GOOD 3 14936 14937 /**************************************************************************** 14938 * Enums: sc_x1_speed_override3_cl91_algn_state 14939 */ 14940 #define sc_x1_speed_override3_cl91_algn_state_LOSS_OF_ALIGNMENT 0 14941 #define sc_x1_speed_override3_cl91_algn_state_DESKEW 1 14942 #define sc_x1_speed_override3_cl91_algn_state_DESKEW_FAIL 2 14943 #define sc_x1_speed_override3_cl91_algn_state_ALIGN_ACQUIRED 3 14944 #define sc_x1_speed_override3_cl91_algn_state_CW_GOOD 4 14945 #define sc_x1_speed_override3_cl91_algn_state_CW_BAD 5 14946 #define sc_x1_speed_override3_cl91_algn_state_THREE_BAD 6 14947 14948 /**************************************************************************** 14949 * Enums: sc_x1_speed_override3_fec_sel_override 14950 */ 14951 #define sc_x1_speed_override3_fec_sel_override_NO_OVERRIDE 0 14952 #define sc_x1_speed_override3_fec_sel_override_NO_FEC 1 14953 #define sc_x1_speed_override3_fec_sel_override_FEC_CL74 2 14954 #define sc_x1_speed_override3_fec_sel_override_FEC_CL91 3 14955 14956 /**************************************************************************** 14957 * Enums: sc_x1_speed_override3_cl91_blksync_mode 14958 */ 14959 #define sc_x1_speed_override3_cl91_blksync_mode_R_BLKSYNC_NO_CL91_FEC 0 14960 #define sc_x1_speed_override3_cl91_blksync_mode_R_BLKSYNC_CL91_QUAD_LANE_FEC 1 14961 #define sc_x1_speed_override3_cl91_blksync_mode_R_BLKSYNC_CL91_DUAL_LANE_FEC 2 14962 #define sc_x1_speed_override3_cl91_blksync_mode_R_BLKSYNC_CL91_SINGLE_LANE_FEC 3 14963 #define sc_x1_speed_override3_cl91_blksync_mode_R_BLKSYNC_CL91_FC_FEC 4 14964 14965 /**************************************************************************** 14966 * Enums: sc_x1_speed_override3_r_merge_mode 14967 */ 14968 #define sc_x1_speed_override3_r_merge_mode_R_MERGE_MODE_BYPASS 0 14969 #define sc_x1_speed_override3_r_merge_mode_R_MERGE_MODE_CL91_FC 1 14970 #define sc_x1_speed_override3_r_merge_mode_R_MERGE_MODE_CL91_SINGLE_LANE 2 14971 #define sc_x1_speed_override3_r_merge_mode_R_MERGE_MODE_CL91_DUAL_LANE 3 14972 #define sc_x1_speed_override3_r_merge_mode_R_MERGE_MODE_CL91_QUAD_LANE 4 14973 14974 /**************************************************************************** 14975 * Enums: sc_x1_speed_override3_r_tc_mode 14976 */ 14977 #define sc_x1_speed_override3_r_tc_mode_R_TC_MODE_SINGLE 0 14978 #define sc_x1_speed_override3_r_tc_mode_R_TC_MODE_DUAL 1 14979 #define sc_x1_speed_override3_r_tc_mode_R_TC_MODE_QUAD 2 14980 14981 /**************************************************************************** 14982 * Enums: sc_x1_speed_override3_r_tc_out_mode 14983 */ 14984 #define sc_x1_speed_override3_r_tc_out_mode_R_TC_OUT_MODE_SINGLE 0 14985 #define sc_x1_speed_override3_r_tc_out_mode_R_TC_OUT_MODE_DUAL 1 14986 #define sc_x1_speed_override3_r_tc_out_mode_R_TC_OUT_MODE_QUAD 2 14987 14988 /**************************************************************************** 14989 * Enums: sc_x1_speed_override3_cl91_fec_mode 14990 */ 14991 #define sc_x1_speed_override3_cl91_fec_mode_NO_CL91_FEC 0 14992 #define sc_x1_speed_override3_cl91_fec_mode_CL91_SINGLE_LANE_FC 1 14993 #define sc_x1_speed_override3_cl91_fec_mode_CL91_SINGLE_LANE_BRCM_PROP 2 14994 #define sc_x1_speed_override3_cl91_fec_mode_CL91_DUAL_LANE_BRCM_PROP 3 14995 #define sc_x1_speed_override3_cl91_fec_mode_CL91_QUAD_LANE 4 14996 #define sc_x1_speed_override3_cl91_fec_mode_IEEE_25G_CL91_SINGLE_LANE 5 14997 14998 /**************************************************************************** 14999 * Enums: sc_x1_speed_override3_am_spacing_mul 15000 */ 15001 #define sc_x1_speed_override3_am_spacing_mul_AM_SPACING_MUL_2 0 15002 #define sc_x1_speed_override3_am_spacing_mul_AM_SPACING_MUL_4 1 15003 #define sc_x1_speed_override3_am_spacing_mul_AM_SPACING_MUL_5 2 15004 #define sc_x1_speed_override3_am_spacing_mul_AM_SPACING_MUL_20 3 15005 15006 /**************************************************************************** 15007 * Enums: sc_x4_control_cl36TxEEEStates_l 15008 */ 15009 #define sc_x4_control_cl36TxEEEStates_l_TX_REFRESH 8 15010 #define sc_x4_control_cl36TxEEEStates_l_TX_QUIET 4 15011 #define sc_x4_control_cl36TxEEEStates_l_TX_SLEEP 2 15012 #define sc_x4_control_cl36TxEEEStates_l_TX_ACTIVE 1 15013 15014 /**************************************************************************** 15015 * Enums: sc_x4_control_cl36TxEEEStates_c 15016 */ 15017 #define sc_x4_control_cl36TxEEEStates_c_TX_REFRESH 3 15018 #define sc_x4_control_cl36TxEEEStates_c_TX_QUIET 2 15019 #define sc_x4_control_cl36TxEEEStates_c_TX_SLEEP 1 15020 #define sc_x4_control_cl36TxEEEStates_c_TX_ACTIVE 0 15021 15022 /**************************************************************************** 15023 * Enums: sc_x4_control_cl49TxEEEStates_l 15024 */ 15025 #define sc_x4_control_cl49TxEEEStates_l_SCR_RESET_2 64 15026 #define sc_x4_control_cl49TxEEEStates_l_SCR_RESET_1 32 15027 #define sc_x4_control_cl49TxEEEStates_l_TX_WAKE 16 15028 #define sc_x4_control_cl49TxEEEStates_l_TX_REFRESH 8 15029 #define sc_x4_control_cl49TxEEEStates_l_TX_QUIET 4 15030 #define sc_x4_control_cl49TxEEEStates_l_TX_SLEEP 2 15031 #define sc_x4_control_cl49TxEEEStates_l_TX_ACTIVE 1 15032 15033 /**************************************************************************** 15034 * Enums: sc_x4_control_fec_req_enum 15035 */ 15036 #define sc_x4_control_fec_req_enum_FEC_not_supported 0 15037 #define sc_x4_control_fec_req_enum_FEC_supported_but_not_requested 1 15038 #define sc_x4_control_fec_req_enum_invalid_setting 2 15039 #define sc_x4_control_fec_req_enum_FEC_supported_and_requested 3 15040 15041 /**************************************************************************** 15042 * Enums: sc_x4_control_cl73_pause_enum 15043 */ 15044 #define sc_x4_control_cl73_pause_enum_No_PAUSE_ability 0 15045 #define sc_x4_control_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 15046 #define sc_x4_control_cl73_pause_enum_Symmetric_PAUSE_ability 1 15047 #define sc_x4_control_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 15048 15049 /**************************************************************************** 15050 * Enums: sc_x4_control_cl49TxEEEStates_c 15051 */ 15052 #define sc_x4_control_cl49TxEEEStates_c_SCR_RESET_2 6 15053 #define sc_x4_control_cl49TxEEEStates_c_SCR_RESET_1 5 15054 #define sc_x4_control_cl49TxEEEStates_c_TX_WAKE 4 15055 #define sc_x4_control_cl49TxEEEStates_c_TX_REFRESH 3 15056 #define sc_x4_control_cl49TxEEEStates_c_TX_QUIET 2 15057 #define sc_x4_control_cl49TxEEEStates_c_TX_SLEEP 1 15058 #define sc_x4_control_cl49TxEEEStates_c_TX_ACTIVE 0 15059 15060 /**************************************************************************** 15061 * Enums: sc_x4_control_cl36RxEEEStates_l 15062 */ 15063 #define sc_x4_control_cl36RxEEEStates_l_RX_LINK_FAIL 32 15064 #define sc_x4_control_cl36RxEEEStates_l_RX_WTF 16 15065 #define sc_x4_control_cl36RxEEEStates_l_RX_WAKE 8 15066 #define sc_x4_control_cl36RxEEEStates_l_RX_QUIET 4 15067 #define sc_x4_control_cl36RxEEEStates_l_RX_SLEEP 2 15068 #define sc_x4_control_cl36RxEEEStates_l_RX_ACTIVE 1 15069 15070 /**************************************************************************** 15071 * Enums: sc_x4_control_cl36RxEEEStates_c 15072 */ 15073 #define sc_x4_control_cl36RxEEEStates_c_RX_LINK_FAIL 5 15074 #define sc_x4_control_cl36RxEEEStates_c_RX_WTF 4 15075 #define sc_x4_control_cl36RxEEEStates_c_RX_WAKE 3 15076 #define sc_x4_control_cl36RxEEEStates_c_RX_QUIET 2 15077 #define sc_x4_control_cl36RxEEEStates_c_RX_SLEEP 1 15078 #define sc_x4_control_cl36RxEEEStates_c_RX_ACTIVE 0 15079 15080 /**************************************************************************** 15081 * Enums: sc_x4_control_cl49RxEEEStates_l 15082 */ 15083 #define sc_x4_control_cl49RxEEEStates_l_RX_LINK_FAIL 32 15084 #define sc_x4_control_cl49RxEEEStates_l_RX_WTF 16 15085 #define sc_x4_control_cl49RxEEEStates_l_RX_WAKE 8 15086 #define sc_x4_control_cl49RxEEEStates_l_RX_QUIET 4 15087 #define sc_x4_control_cl49RxEEEStates_l_RX_SLEEP 2 15088 #define sc_x4_control_cl49RxEEEStates_l_RX_ACTIVE 1 15089 15090 /**************************************************************************** 15091 * Enums: sc_x4_control_cl49RxEEEStates_c 15092 */ 15093 #define sc_x4_control_cl49RxEEEStates_c_RX_LINK_FAIL 5 15094 #define sc_x4_control_cl49RxEEEStates_c_RX_WTF 4 15095 #define sc_x4_control_cl49RxEEEStates_c_RX_WAKE 3 15096 #define sc_x4_control_cl49RxEEEStates_c_RX_QUIET 2 15097 #define sc_x4_control_cl49RxEEEStates_c_RX_SLEEP 1 15098 #define sc_x4_control_cl49RxEEEStates_c_RX_ACTIVE 0 15099 15100 /**************************************************************************** 15101 * Enums: sc_x4_control_cl48TxEEEStates_l 15102 */ 15103 #define sc_x4_control_cl48TxEEEStates_l_TX_REFRESH 8 15104 #define sc_x4_control_cl48TxEEEStates_l_TX_QUIET 4 15105 #define sc_x4_control_cl48TxEEEStates_l_TX_SLEEP 2 15106 #define sc_x4_control_cl48TxEEEStates_l_TX_ACTIVE 1 15107 15108 /**************************************************************************** 15109 * Enums: sc_x4_control_cl48TxEEEStates_c 15110 */ 15111 #define sc_x4_control_cl48TxEEEStates_c_TX_REFRESH 3 15112 #define sc_x4_control_cl48TxEEEStates_c_TX_QUIET 2 15113 #define sc_x4_control_cl48TxEEEStates_c_TX_SLEEP 1 15114 #define sc_x4_control_cl48TxEEEStates_c_TX_ACTIVE 0 15115 15116 /**************************************************************************** 15117 * Enums: sc_x4_control_cl48RxEEEStates_l 15118 */ 15119 #define sc_x4_control_cl48RxEEEStates_l_RX_LINK_FAIL 32 15120 #define sc_x4_control_cl48RxEEEStates_l_RX_WAKE 16 15121 #define sc_x4_control_cl48RxEEEStates_l_RX_QUIET 8 15122 #define sc_x4_control_cl48RxEEEStates_l_RX_DEACT 4 15123 #define sc_x4_control_cl48RxEEEStates_l_RX_SLEEP 2 15124 #define sc_x4_control_cl48RxEEEStates_l_RX_ACTIVE 1 15125 15126 /**************************************************************************** 15127 * Enums: sc_x4_control_cl48RxEEEStates_c 15128 */ 15129 #define sc_x4_control_cl48RxEEEStates_c_RX_LINK_FAIL 5 15130 #define sc_x4_control_cl48RxEEEStates_c_RX_WAKE 4 15131 #define sc_x4_control_cl48RxEEEStates_c_RX_QUIET 3 15132 #define sc_x4_control_cl48RxEEEStates_c_RX_DEACT 2 15133 #define sc_x4_control_cl48RxEEEStates_c_RX_SLEEP 1 15134 #define sc_x4_control_cl48RxEEEStates_c_RX_ACTIVE 0 15135 15136 /**************************************************************************** 15137 * Enums: sc_x4_control_IQP_Options 15138 */ 15139 #define sc_x4_control_IQP_Options_i50uA 0 15140 #define sc_x4_control_IQP_Options_i100uA 1 15141 #define sc_x4_control_IQP_Options_i150uA 2 15142 #define sc_x4_control_IQP_Options_i200uA 3 15143 #define sc_x4_control_IQP_Options_i250uA 4 15144 #define sc_x4_control_IQP_Options_i300uA 5 15145 #define sc_x4_control_IQP_Options_i350uA 6 15146 #define sc_x4_control_IQP_Options_i400uA 7 15147 #define sc_x4_control_IQP_Options_i450uA 8 15148 #define sc_x4_control_IQP_Options_i500uA 9 15149 #define sc_x4_control_IQP_Options_i550uA 10 15150 #define sc_x4_control_IQP_Options_i600uA 11 15151 #define sc_x4_control_IQP_Options_i650uA 12 15152 #define sc_x4_control_IQP_Options_i700uA 13 15153 #define sc_x4_control_IQP_Options_i750uA 14 15154 #define sc_x4_control_IQP_Options_i800uA 15 15155 15156 /**************************************************************************** 15157 * Enums: sc_x4_control_IDriver_Options 15158 */ 15159 #define sc_x4_control_IDriver_Options_v680mV 0 15160 #define sc_x4_control_IDriver_Options_v730mV 1 15161 #define sc_x4_control_IDriver_Options_v780mV 2 15162 #define sc_x4_control_IDriver_Options_v830mV 3 15163 #define sc_x4_control_IDriver_Options_v880mV 4 15164 #define sc_x4_control_IDriver_Options_v930mV 5 15165 #define sc_x4_control_IDriver_Options_v980mV 6 15166 #define sc_x4_control_IDriver_Options_v1010mV 7 15167 #define sc_x4_control_IDriver_Options_v1040mV 8 15168 #define sc_x4_control_IDriver_Options_v1060mV 9 15169 #define sc_x4_control_IDriver_Options_v1070mV 10 15170 #define sc_x4_control_IDriver_Options_v1080mV 11 15171 #define sc_x4_control_IDriver_Options_v1085mV 12 15172 #define sc_x4_control_IDriver_Options_v1090mV 13 15173 #define sc_x4_control_IDriver_Options_v1095mV 14 15174 #define sc_x4_control_IDriver_Options_v1100mV 15 15175 15176 /**************************************************************************** 15177 * Enums: sc_x4_control_operationModes 15178 */ 15179 #define sc_x4_control_operationModes_XGXS 0 15180 #define sc_x4_control_operationModes_XGXG_nCC 1 15181 #define sc_x4_control_operationModes_Indlane_OS8 4 15182 #define sc_x4_control_operationModes_IndLane_OS5 5 15183 #define sc_x4_control_operationModes_PCI 7 15184 #define sc_x4_control_operationModes_XGXS_nLQ 8 15185 #define sc_x4_control_operationModes_XGXS_nLQnCC 9 15186 #define sc_x4_control_operationModes_PBypass 10 15187 #define sc_x4_control_operationModes_PBypass_nDSK 11 15188 #define sc_x4_control_operationModes_ComboCoreMode 12 15189 #define sc_x4_control_operationModes_Clocks_off 15 15190 15191 /**************************************************************************** 15192 * Enums: sc_x4_control_actualSpeeds 15193 */ 15194 #define sc_x4_control_actualSpeeds_dr_10M 0 15195 #define sc_x4_control_actualSpeeds_dr_100M 1 15196 #define sc_x4_control_actualSpeeds_dr_1G 2 15197 #define sc_x4_control_actualSpeeds_dr_2p5G 3 15198 #define sc_x4_control_actualSpeeds_dr_5G_X4 4 15199 #define sc_x4_control_actualSpeeds_dr_6G_X4 5 15200 #define sc_x4_control_actualSpeeds_dr_10G_HiG 6 15201 #define sc_x4_control_actualSpeeds_dr_10G_CX4 7 15202 #define sc_x4_control_actualSpeeds_dr_12G_HiG 8 15203 #define sc_x4_control_actualSpeeds_dr_12p5G_X4 9 15204 #define sc_x4_control_actualSpeeds_dr_13G_X4 10 15205 #define sc_x4_control_actualSpeeds_dr_15G_X4 11 15206 #define sc_x4_control_actualSpeeds_dr_16G_X4 12 15207 #define sc_x4_control_actualSpeeds_dr_1G_KX 13 15208 #define sc_x4_control_actualSpeeds_dr_10G_KX4 14 15209 #define sc_x4_control_actualSpeeds_dr_10G_KR 15 15210 #define sc_x4_control_actualSpeeds_dr_5G 16 15211 #define sc_x4_control_actualSpeeds_dr_6p4G 17 15212 #define sc_x4_control_actualSpeeds_dr_20G_X4 18 15213 #define sc_x4_control_actualSpeeds_dr_21G_X4 19 15214 #define sc_x4_control_actualSpeeds_dr_25G_X4 20 15215 #define sc_x4_control_actualSpeeds_dr_10G_HiG_DXGXS 21 15216 #define sc_x4_control_actualSpeeds_dr_10G_DXGXS 22 15217 #define sc_x4_control_actualSpeeds_dr_10p5G_HiG_DXGXS 23 15218 #define sc_x4_control_actualSpeeds_dr_10p5G_DXGXS 24 15219 #define sc_x4_control_actualSpeeds_dr_12p773G_HiG_DXGXS 25 15220 #define sc_x4_control_actualSpeeds_dr_12p773G_DXGXS 26 15221 #define sc_x4_control_actualSpeeds_dr_10G_XFI 27 15222 #define sc_x4_control_actualSpeeds_dr_40G 28 15223 #define sc_x4_control_actualSpeeds_dr_20G_HiG_DXGXS 29 15224 #define sc_x4_control_actualSpeeds_dr_20G_DXGXS 30 15225 #define sc_x4_control_actualSpeeds_dr_10G_SFI 31 15226 #define sc_x4_control_actualSpeeds_dr_31p5G 32 15227 #define sc_x4_control_actualSpeeds_dr_32p7G 33 15228 #define sc_x4_control_actualSpeeds_dr_20G_SCR 34 15229 #define sc_x4_control_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 15230 #define sc_x4_control_actualSpeeds_dr_10G_DXGXS_SCR 36 15231 #define sc_x4_control_actualSpeeds_dr_12G_R2 37 15232 #define sc_x4_control_actualSpeeds_dr_10G_X2 38 15233 #define sc_x4_control_actualSpeeds_dr_40G_KR4 39 15234 #define sc_x4_control_actualSpeeds_dr_40G_CR4 40 15235 #define sc_x4_control_actualSpeeds_dr_100G_CR10 41 15236 #define sc_x4_control_actualSpeeds_dr_15p75G_DXGXS 44 15237 #define sc_x4_control_actualSpeeds_dr_20G_KR2 57 15238 #define sc_x4_control_actualSpeeds_dr_20G_CR2 58 15239 15240 /**************************************************************************** 15241 * Enums: sc_x4_control_actualSpeedsMisc1 15242 */ 15243 #define sc_x4_control_actualSpeedsMisc1_dr_2500BRCM_X1 16 15244 #define sc_x4_control_actualSpeedsMisc1_dr_5000BRCM_X4 17 15245 #define sc_x4_control_actualSpeedsMisc1_dr_6000BRCM_X4 18 15246 #define sc_x4_control_actualSpeedsMisc1_dr_10GHiGig_X4 19 15247 #define sc_x4_control_actualSpeedsMisc1_dr_10GBASE_CX4 20 15248 #define sc_x4_control_actualSpeedsMisc1_dr_12GHiGig_X4 21 15249 #define sc_x4_control_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 15250 #define sc_x4_control_actualSpeedsMisc1_dr_13GHiGig_X4 23 15251 #define sc_x4_control_actualSpeedsMisc1_dr_15GHiGig_X4 24 15252 #define sc_x4_control_actualSpeedsMisc1_dr_16GHiGig_X4 25 15253 #define sc_x4_control_actualSpeedsMisc1_dr_5000BRCM_X1 26 15254 #define sc_x4_control_actualSpeedsMisc1_dr_6363BRCM_X1 27 15255 #define sc_x4_control_actualSpeedsMisc1_dr_20GHiGig_X4 28 15256 #define sc_x4_control_actualSpeedsMisc1_dr_21GHiGig_X4 29 15257 #define sc_x4_control_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 15258 #define sc_x4_control_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 15259 15260 /**************************************************************************** 15261 * Enums: sc_x4_control_IndLaneModes 15262 */ 15263 #define sc_x4_control_IndLaneModes_SWSDR_div2 0 15264 #define sc_x4_control_IndLaneModes_SWSDR_div1 1 15265 #define sc_x4_control_IndLaneModes_DWSDR_div2 2 15266 #define sc_x4_control_IndLaneModes_DWSDR_div1 3 15267 15268 /**************************************************************************** 15269 * Enums: sc_x4_control_prbsSelect 15270 */ 15271 #define sc_x4_control_prbsSelect_prbs7 0 15272 #define sc_x4_control_prbsSelect_prbs15 1 15273 #define sc_x4_control_prbsSelect_prbs23 2 15274 #define sc_x4_control_prbsSelect_prbs31 3 15275 15276 /**************************************************************************** 15277 * Enums: sc_x4_control_vcoDivider 15278 */ 15279 #define sc_x4_control_vcoDivider_div32 0 15280 #define sc_x4_control_vcoDivider_div36 1 15281 #define sc_x4_control_vcoDivider_div40 2 15282 #define sc_x4_control_vcoDivider_div42 3 15283 #define sc_x4_control_vcoDivider_div48 4 15284 #define sc_x4_control_vcoDivider_div50 5 15285 #define sc_x4_control_vcoDivider_div52 6 15286 #define sc_x4_control_vcoDivider_div54 7 15287 #define sc_x4_control_vcoDivider_div60 8 15288 #define sc_x4_control_vcoDivider_div64 9 15289 #define sc_x4_control_vcoDivider_div66 10 15290 #define sc_x4_control_vcoDivider_div68 11 15291 #define sc_x4_control_vcoDivider_div70 12 15292 #define sc_x4_control_vcoDivider_div80 13 15293 #define sc_x4_control_vcoDivider_div92 14 15294 #define sc_x4_control_vcoDivider_div100 15 15295 15296 /**************************************************************************** 15297 * Enums: sc_x4_control_refClkSelect 15298 */ 15299 #define sc_x4_control_refClkSelect_clk_25MHz 0 15300 #define sc_x4_control_refClkSelect_clk_100MHz 1 15301 #define sc_x4_control_refClkSelect_clk_125MHz 2 15302 #define sc_x4_control_refClkSelect_clk_156p25MHz 3 15303 #define sc_x4_control_refClkSelect_clk_187p5MHz 4 15304 #define sc_x4_control_refClkSelect_clk_161p25Mhz 5 15305 #define sc_x4_control_refClkSelect_clk_50Mhz 6 15306 #define sc_x4_control_refClkSelect_clk_106p25Mhz 7 15307 15308 /**************************************************************************** 15309 * Enums: sc_x4_control_aerMMDdevTypeSelect 15310 */ 15311 #define sc_x4_control_aerMMDdevTypeSelect_combo_core 0 15312 #define sc_x4_control_aerMMDdevTypeSelect_PMA_PMD 1 15313 #define sc_x4_control_aerMMDdevTypeSelect_PCS 3 15314 #define sc_x4_control_aerMMDdevTypeSelect_PHY 4 15315 #define sc_x4_control_aerMMDdevTypeSelect_DTE 5 15316 #define sc_x4_control_aerMMDdevTypeSelect_CL73_AN 7 15317 15318 /**************************************************************************** 15319 * Enums: sc_x4_control_aerMMDportSelect 15320 */ 15321 #define sc_x4_control_aerMMDportSelect_ln0 0 15322 #define sc_x4_control_aerMMDportSelect_ln1 1 15323 #define sc_x4_control_aerMMDportSelect_ln2 2 15324 #define sc_x4_control_aerMMDportSelect_ln3 3 15325 #define sc_x4_control_aerMMDportSelect_BCST_ln0_1_2_3 511 15326 #define sc_x4_control_aerMMDportSelect_BCST_ln0_1 512 15327 #define sc_x4_control_aerMMDportSelect_BCST_ln2_3 513 15328 15329 /**************************************************************************** 15330 * Enums: sc_x4_control_firmwareModeSelect 15331 */ 15332 #define sc_x4_control_firmwareModeSelect_DEFAULT 0 15333 #define sc_x4_control_firmwareModeSelect_SFP_OPT_LR 1 15334 #define sc_x4_control_firmwareModeSelect_SFP_DAC 2 15335 #define sc_x4_control_firmwareModeSelect_XLAUI 3 15336 #define sc_x4_control_firmwareModeSelect_LONG_CH_6G 4 15337 15338 /**************************************************************************** 15339 * Enums: sc_x4_control_tempIdxSelect 15340 */ 15341 #define sc_x4_control_tempIdxSelect_LTE__22p9C 15 15342 #define sc_x4_control_tempIdxSelect_LTE__12p6C 14 15343 #define sc_x4_control_tempIdxSelect_LTE__3p0C 13 15344 #define sc_x4_control_tempIdxSelect_LTE_6p7C 12 15345 #define sc_x4_control_tempIdxSelect_LTE_16p4C 11 15346 #define sc_x4_control_tempIdxSelect_LTE_26p6C 10 15347 #define sc_x4_control_tempIdxSelect_LTE_36p3C 9 15348 #define sc_x4_control_tempIdxSelect_LTE_46p0C 8 15349 #define sc_x4_control_tempIdxSelect_LTE_56p2C 7 15350 #define sc_x4_control_tempIdxSelect_LTE_65p9C 6 15351 #define sc_x4_control_tempIdxSelect_LTE_75p6C 5 15352 #define sc_x4_control_tempIdxSelect_LTE_85p3C 4 15353 #define sc_x4_control_tempIdxSelect_LTE_95p5C 3 15354 #define sc_x4_control_tempIdxSelect_LTE_105p2C 2 15355 #define sc_x4_control_tempIdxSelect_LTE_114p9C 1 15356 #define sc_x4_control_tempIdxSelect_LTE_125p1C 0 15357 15358 /**************************************************************************** 15359 * Enums: sc_x4_control_port_mode 15360 */ 15361 #define sc_x4_control_port_mode_QUAD_PORT 0 15362 #define sc_x4_control_port_mode_TRI_1_PORT 1 15363 #define sc_x4_control_port_mode_TRI_2_PORT 2 15364 #define sc_x4_control_port_mode_DUAL_PORT 3 15365 #define sc_x4_control_port_mode_SINGLE_PORT 4 15366 15367 /**************************************************************************** 15368 * Enums: sc_x4_control_rev_letter_enum 15369 */ 15370 #define sc_x4_control_rev_letter_enum_REV_A 0 15371 #define sc_x4_control_rev_letter_enum_REV_B 1 15372 #define sc_x4_control_rev_letter_enum_REV_C 2 15373 #define sc_x4_control_rev_letter_enum_REV_D 3 15374 15375 /**************************************************************************** 15376 * Enums: sc_x4_control_rev_number_enum 15377 */ 15378 #define sc_x4_control_rev_number_enum_REV_0 0 15379 #define sc_x4_control_rev_number_enum_REV_1 1 15380 #define sc_x4_control_rev_number_enum_REV_2 2 15381 #define sc_x4_control_rev_number_enum_REV_3 3 15382 #define sc_x4_control_rev_number_enum_REV_4 4 15383 #define sc_x4_control_rev_number_enum_REV_5 5 15384 #define sc_x4_control_rev_number_enum_REV_6 6 15385 #define sc_x4_control_rev_number_enum_REV_7 7 15386 15387 /**************************************************************************** 15388 * Enums: sc_x4_control_bonding_enum 15389 */ 15390 #define sc_x4_control_bonding_enum_WIRE_BOND 0 15391 #define sc_x4_control_bonding_enum_FLIP_CHIP 1 15392 15393 /**************************************************************************** 15394 * Enums: sc_x4_control_tech_process 15395 */ 15396 #define sc_x4_control_tech_process_PROCESS_90NM 0 15397 #define sc_x4_control_tech_process_PROCESS_65NM 1 15398 #define sc_x4_control_tech_process_PROCESS_40NM 2 15399 #define sc_x4_control_tech_process_PROCESS_28NM 3 15400 #define sc_x4_control_tech_process_PROCESS_16NM 4 15401 15402 /**************************************************************************** 15403 * Enums: sc_x4_control_model_num 15404 */ 15405 #define sc_x4_control_model_num_SERDES_CL73 0 15406 #define sc_x4_control_model_num_XGXS_16G 1 15407 #define sc_x4_control_model_num_HYPERCORE 2 15408 #define sc_x4_control_model_num_HYPERLITE 3 15409 #define sc_x4_control_model_num_PCIE_G2_PIPE 4 15410 #define sc_x4_control_model_num_SERDES_1p25GBd 5 15411 #define sc_x4_control_model_num_SATA2 6 15412 #define sc_x4_control_model_num_QSGMII 7 15413 #define sc_x4_control_model_num_XGXS10G 8 15414 #define sc_x4_control_model_num_WARPCORE 9 15415 #define sc_x4_control_model_num_XFICORE 10 15416 #define sc_x4_control_model_num_RXFI 11 15417 #define sc_x4_control_model_num_WARPLITE 12 15418 #define sc_x4_control_model_num_PENTACORE 13 15419 #define sc_x4_control_model_num_ESM 14 15420 #define sc_x4_control_model_num_QUAD_SGMII 15 15421 #define sc_x4_control_model_num_WARPCORE_3 16 15422 #define sc_x4_control_model_num_TSC 17 15423 #define sc_x4_control_model_num_TSC4E 18 15424 #define sc_x4_control_model_num_TSC12E 19 15425 #define sc_x4_control_model_num_TSC4F 20 15426 #define sc_x4_control_model_num_TSC4F_GEN2 21 15427 #define sc_x4_control_model_num_XGXS_CL73_90NM 29 15428 #define sc_x4_control_model_num_SERDES_CL73_90NM 30 15429 #define sc_x4_control_model_num_WARPCORE3 32 15430 #define sc_x4_control_model_num_WARPCORE4_TSC 33 15431 #define sc_x4_control_model_num_RXAUI 34 15432 15433 /**************************************************************************** 15434 * Enums: sc_x4_control_payload 15435 */ 15436 #define sc_x4_control_payload_REPEAT_2_BYTES 0 15437 #define sc_x4_control_payload_RAMPING 1 15438 #define sc_x4_control_payload_CL48_CRPAT 2 15439 #define sc_x4_control_payload_CL48_CJPAT 3 15440 #define sc_x4_control_payload_CL36_LONG_CRPAT 4 15441 #define sc_x4_control_payload_CL36_SHORT_CRPAT 5 15442 15443 /**************************************************************************** 15444 * Enums: sc_x4_control_sc 15445 */ 15446 #define sc_x4_control_sc_S_10G_CR1 0 15447 #define sc_x4_control_sc_S_10G_KR1 1 15448 #define sc_x4_control_sc_S_10G_X1 2 15449 #define sc_x4_control_sc_S_10G_HG2_CR1 4 15450 #define sc_x4_control_sc_S_10G_HG2_KR1 5 15451 #define sc_x4_control_sc_S_10G_HG2_X1 6 15452 #define sc_x4_control_sc_S_20G_CR1 8 15453 #define sc_x4_control_sc_S_20G_KR1 9 15454 #define sc_x4_control_sc_S_20G_X1 10 15455 #define sc_x4_control_sc_S_20G_HG2_CR1 12 15456 #define sc_x4_control_sc_S_20G_HG2_KR1 13 15457 #define sc_x4_control_sc_S_20G_HG2_X1 14 15458 #define sc_x4_control_sc_S_25G_CR1 16 15459 #define sc_x4_control_sc_S_25G_KR1 17 15460 #define sc_x4_control_sc_S_25G_X1 18 15461 #define sc_x4_control_sc_S_25G_HG2_CR1 20 15462 #define sc_x4_control_sc_S_25G_HG2_KR1 21 15463 #define sc_x4_control_sc_S_25G_HG2_X1 22 15464 #define sc_x4_control_sc_S_20G_CR2 24 15465 #define sc_x4_control_sc_S_20G_KR2 25 15466 #define sc_x4_control_sc_S_20G_X2 26 15467 #define sc_x4_control_sc_S_20G_HG2_CR2 28 15468 #define sc_x4_control_sc_S_20G_HG2_KR2 29 15469 #define sc_x4_control_sc_S_20G_HG2_X2 30 15470 #define sc_x4_control_sc_S_40G_CR2 32 15471 #define sc_x4_control_sc_S_40G_KR2 33 15472 #define sc_x4_control_sc_S_40G_X2 34 15473 #define sc_x4_control_sc_S_40G_HG2_CR2 36 15474 #define sc_x4_control_sc_S_40G_HG2_KR2 37 15475 #define sc_x4_control_sc_S_40G_HG2_X2 38 15476 #define sc_x4_control_sc_S_40G_CR4 40 15477 #define sc_x4_control_sc_S_40G_KR4 41 15478 #define sc_x4_control_sc_S_40G_X4 42 15479 #define sc_x4_control_sc_S_40G_HG2_CR4 44 15480 #define sc_x4_control_sc_S_40G_HG2_KR4 45 15481 #define sc_x4_control_sc_S_40G_HG2_X4 46 15482 #define sc_x4_control_sc_S_50G_CR2 48 15483 #define sc_x4_control_sc_S_50G_KR2 49 15484 #define sc_x4_control_sc_S_50G_X2 50 15485 #define sc_x4_control_sc_S_50G_HG2_CR2 52 15486 #define sc_x4_control_sc_S_50G_HG2_KR2 53 15487 #define sc_x4_control_sc_S_50G_HG2_X2 54 15488 #define sc_x4_control_sc_S_50G_CR4 56 15489 #define sc_x4_control_sc_S_50G_KR4 57 15490 #define sc_x4_control_sc_S_50G_X4 58 15491 #define sc_x4_control_sc_S_50G_HG2_CR4 60 15492 #define sc_x4_control_sc_S_50G_HG2_KR4 61 15493 #define sc_x4_control_sc_S_50G_HG2_X4 62 15494 #define sc_x4_control_sc_S_100G_CR4 64 15495 #define sc_x4_control_sc_S_100G_KR4 65 15496 #define sc_x4_control_sc_S_100G_X4 66 15497 #define sc_x4_control_sc_S_100G_HG2_CR4 68 15498 #define sc_x4_control_sc_S_100G_HG2_KR4 69 15499 #define sc_x4_control_sc_S_100G_HG2_X4 70 15500 #define sc_x4_control_sc_S_CL73_20GVCO 72 15501 #define sc_x4_control_sc_S_CL73_25GVCO 80 15502 #define sc_x4_control_sc_S_CL36_20GVCO 88 15503 #define sc_x4_control_sc_S_CL36_25GVCO 96 15504 #define sc_x4_control_sc_S_10G_25GVCO 98 15505 #define sc_x4_control_sc_S_25G_CR_IEEE 112 15506 #define sc_x4_control_sc_S_25G_CRS_IEEE 113 15507 #define sc_x4_control_sc_S_25G_KR_IEEE 114 15508 #define sc_x4_control_sc_S_25G_KRS_IEEE 115 15509 15510 /**************************************************************************** 15511 * Enums: sc_x4_control_t_fifo_modes 15512 */ 15513 #define sc_x4_control_t_fifo_modes_T_FIFO_INSERT_NO_AM 0 15514 #define sc_x4_control_t_fifo_modes_T_FIFO_INSERT_4_AM 1 15515 #define sc_x4_control_t_fifo_modes_T_FIFO_INSERT_20_AM 2 15516 #define sc_x4_control_t_fifo_modes_T_FIFO_INSERT_2_AM 3 15517 15518 /**************************************************************************** 15519 * Enums: sc_x4_control_t_enc_modes 15520 */ 15521 #define sc_x4_control_t_enc_modes_T_ENC_MODE_BYPASS 0 15522 #define sc_x4_control_t_enc_modes_T_ENC_MODE_CL49 1 15523 #define sc_x4_control_t_enc_modes_T_ENC_MODE_CL82 2 15524 15525 /**************************************************************************** 15526 * Enums: sc_x4_control_btmx_mode 15527 */ 15528 #define sc_x4_control_btmx_mode_BS_BTMX_MODE_1to1 0 15529 #define sc_x4_control_btmx_mode_BS_BTMX_MODE_2to1 1 15530 #define sc_x4_control_btmx_mode_BS_BTMX_MODE_5to1 2 15531 15532 /**************************************************************************** 15533 * Enums: sc_x4_control_t_type_cl82 15534 */ 15535 #define sc_x4_control_t_type_cl82_T_TYPE_B1 5 15536 #define sc_x4_control_t_type_cl82_T_TYPE_C 4 15537 #define sc_x4_control_t_type_cl82_T_TYPE_S 3 15538 #define sc_x4_control_t_type_cl82_T_TYPE_T 2 15539 #define sc_x4_control_t_type_cl82_T_TYPE_D 1 15540 #define sc_x4_control_t_type_cl82_T_TYPE_E 0 15541 15542 /**************************************************************************** 15543 * Enums: sc_x4_control_txsm_state_cl82 15544 */ 15545 #define sc_x4_control_txsm_state_cl82_TX_HIG_END 6 15546 #define sc_x4_control_txsm_state_cl82_TX_HIG_START 5 15547 #define sc_x4_control_txsm_state_cl82_TX_E 4 15548 #define sc_x4_control_txsm_state_cl82_TX_T 3 15549 #define sc_x4_control_txsm_state_cl82_TX_D 2 15550 #define sc_x4_control_txsm_state_cl82_TX_C 1 15551 #define sc_x4_control_txsm_state_cl82_TX_INIT 0 15552 15553 /**************************************************************************** 15554 * Enums: sc_x4_control_ltxsm_state_cl82 15555 */ 15556 #define sc_x4_control_ltxsm_state_cl82_TX_HIG_END 64 15557 #define sc_x4_control_ltxsm_state_cl82_TX_HIG_START 32 15558 #define sc_x4_control_ltxsm_state_cl82_TX_E 16 15559 #define sc_x4_control_ltxsm_state_cl82_TX_T 8 15560 #define sc_x4_control_ltxsm_state_cl82_TX_D 4 15561 #define sc_x4_control_ltxsm_state_cl82_TX_C 2 15562 #define sc_x4_control_ltxsm_state_cl82_TX_INIT 1 15563 15564 /**************************************************************************** 15565 * Enums: sc_x4_control_r_type_coded_cl82 15566 */ 15567 #define sc_x4_control_r_type_coded_cl82_R_TYPE_B1 32 15568 #define sc_x4_control_r_type_coded_cl82_R_TYPE_C 16 15569 #define sc_x4_control_r_type_coded_cl82_R_TYPE_S 8 15570 #define sc_x4_control_r_type_coded_cl82_R_TYPE_T 4 15571 #define sc_x4_control_r_type_coded_cl82_R_TYPE_D 2 15572 #define sc_x4_control_r_type_coded_cl82_R_TYPE_E 1 15573 15574 /**************************************************************************** 15575 * Enums: sc_x4_control_rxsm_state_cl82 15576 */ 15577 #define sc_x4_control_rxsm_state_cl82_RX_HIG_END 64 15578 #define sc_x4_control_rxsm_state_cl82_RX_HIG_START 32 15579 #define sc_x4_control_rxsm_state_cl82_RX_E 16 15580 #define sc_x4_control_rxsm_state_cl82_RX_T 8 15581 #define sc_x4_control_rxsm_state_cl82_RX_D 4 15582 #define sc_x4_control_rxsm_state_cl82_RX_C 2 15583 #define sc_x4_control_rxsm_state_cl82_RX_INIT 1 15584 15585 /**************************************************************************** 15586 * Enums: sc_x4_control_deskew_state 15587 */ 15588 #define sc_x4_control_deskew_state_ALIGN_ACQUIRED 2 15589 #define sc_x4_control_deskew_state_LOSS_OF_ALIGNMENT 1 15590 15591 /**************************************************************************** 15592 * Enums: sc_x4_control_os_mode_enum 15593 */ 15594 #define sc_x4_control_os_mode_enum_OS_MODE_1 0 15595 #define sc_x4_control_os_mode_enum_OS_MODE_2 1 15596 #define sc_x4_control_os_mode_enum_OS_MODE_4 2 15597 #define sc_x4_control_os_mode_enum_OS_MODE_16p5 8 15598 #define sc_x4_control_os_mode_enum_OS_MODE_20p625 12 15599 15600 /**************************************************************************** 15601 * Enums: sc_x4_control_scr_modes 15602 */ 15603 #define sc_x4_control_scr_modes_T_SCR_MODE_BYPASS 0 15604 #define sc_x4_control_scr_modes_T_SCR_MODE_CL49 1 15605 #define sc_x4_control_scr_modes_T_SCR_MODE_40G_2_LANE 2 15606 #define sc_x4_control_scr_modes_T_SCR_MODE_100G 3 15607 #define sc_x4_control_scr_modes_T_SCR_MODE_20G 4 15608 #define sc_x4_control_scr_modes_T_SCR_MODE_40G_4_LANE 5 15609 15610 /**************************************************************************** 15611 * Enums: sc_x4_control_descr_modes 15612 */ 15613 #define sc_x4_control_descr_modes_R_DESCR_MODE_BYPASS 0 15614 #define sc_x4_control_descr_modes_R_DESCR_MODE_CL49 1 15615 #define sc_x4_control_descr_modes_R_DESCR_MODE_CL82 2 15616 15617 /**************************************************************************** 15618 * Enums: sc_x4_control_r_dec_tl_mode 15619 */ 15620 #define sc_x4_control_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 15621 #define sc_x4_control_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 15622 #define sc_x4_control_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 15623 15624 /**************************************************************************** 15625 * Enums: sc_x4_control_r_dec_fsm_mode 15626 */ 15627 #define sc_x4_control_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 15628 #define sc_x4_control_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 15629 #define sc_x4_control_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 15630 15631 /**************************************************************************** 15632 * Enums: sc_x4_control_r_deskew_mode 15633 */ 15634 #define sc_x4_control_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 15635 #define sc_x4_control_r_deskew_mode_R_DESKEW_MODE_20G 1 15636 #define sc_x4_control_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 15637 #define sc_x4_control_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 15638 #define sc_x4_control_r_deskew_mode_R_DESKEW_MODE_100G 4 15639 #define sc_x4_control_r_deskew_mode_R_DESKEW_MODE_CL49 5 15640 #define sc_x4_control_r_deskew_mode_R_DESKEW_MODE_CL91_QUAD 6 15641 #define sc_x4_control_r_deskew_mode_R_DESKEW_MODE_CL91_SINGLE_BRCM 7 15642 #define sc_x4_control_r_deskew_mode_R_DESKEW_MODE_CL91_DUAL_BRCM 8 15643 #define sc_x4_control_r_deskew_mode_R_DESKEW_MODE_CL91_FC 9 15644 15645 /**************************************************************************** 15646 * Enums: sc_x4_control_bs_dist_modes 15647 */ 15648 #define sc_x4_control_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 15649 #define sc_x4_control_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 15650 #define sc_x4_control_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 15651 #define sc_x4_control_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 15652 15653 /**************************************************************************** 15654 * Enums: sc_x4_control_cl49_t_type 15655 */ 15656 #define sc_x4_control_cl49_t_type_BAD_T_TYPE 15 15657 #define sc_x4_control_cl49_t_type_T_TYPE_B0 11 15658 #define sc_x4_control_cl49_t_type_T_TYPE_OB 10 15659 #define sc_x4_control_cl49_t_type_T_TYPE_B1 9 15660 #define sc_x4_control_cl49_t_type_T_TYPE_DB 8 15661 #define sc_x4_control_cl49_t_type_T_TYPE_FC 7 15662 #define sc_x4_control_cl49_t_type_T_TYPE_TB 6 15663 #define sc_x4_control_cl49_t_type_T_TYPE_LI 5 15664 #define sc_x4_control_cl49_t_type_T_TYPE_C 4 15665 #define sc_x4_control_cl49_t_type_T_TYPE_S 3 15666 #define sc_x4_control_cl49_t_type_T_TYPE_T 2 15667 #define sc_x4_control_cl49_t_type_T_TYPE_D 1 15668 #define sc_x4_control_cl49_t_type_T_TYPE_E 0 15669 15670 /**************************************************************************** 15671 * Enums: sc_x4_control_cl49_txsm_states 15672 */ 15673 #define sc_x4_control_cl49_txsm_states_TX_HIG_END 7 15674 #define sc_x4_control_cl49_txsm_states_TX_HIG_START 6 15675 #define sc_x4_control_cl49_txsm_states_TX_LI 5 15676 #define sc_x4_control_cl49_txsm_states_TX_E 4 15677 #define sc_x4_control_cl49_txsm_states_TX_T 3 15678 #define sc_x4_control_cl49_txsm_states_TX_D 2 15679 #define sc_x4_control_cl49_txsm_states_TX_C 1 15680 #define sc_x4_control_cl49_txsm_states_TX_INIT 0 15681 15682 /**************************************************************************** 15683 * Enums: sc_x4_control_cl49_ltxsm_states 15684 */ 15685 #define sc_x4_control_cl49_ltxsm_states_TX_HIG_END 128 15686 #define sc_x4_control_cl49_ltxsm_states_TX_HIG_START 64 15687 #define sc_x4_control_cl49_ltxsm_states_TX_LI 32 15688 #define sc_x4_control_cl49_ltxsm_states_TX_E 16 15689 #define sc_x4_control_cl49_ltxsm_states_TX_T 8 15690 #define sc_x4_control_cl49_ltxsm_states_TX_D 4 15691 #define sc_x4_control_cl49_ltxsm_states_TX_C 2 15692 #define sc_x4_control_cl49_ltxsm_states_TX_INIT 1 15693 15694 /**************************************************************************** 15695 * Enums: sc_x4_control_burst_error_mode 15696 */ 15697 #define sc_x4_control_burst_error_mode_BURST_ERROR_11_BITS 0 15698 #define sc_x4_control_burst_error_mode_BURST_ERROR_16_BITS 1 15699 #define sc_x4_control_burst_error_mode_BURST_ERROR_17_BITS 2 15700 #define sc_x4_control_burst_error_mode_BURST_ERROR_18_BITS 3 15701 #define sc_x4_control_burst_error_mode_BURST_ERROR_19_BITS 4 15702 #define sc_x4_control_burst_error_mode_BURST_ERROR_20_BITS 5 15703 #define sc_x4_control_burst_error_mode_BURST_ERROR_21_BITS 6 15704 #define sc_x4_control_burst_error_mode_BURST_ERROR_22_BITS 7 15705 #define sc_x4_control_burst_error_mode_BURST_ERROR_23_BITS 8 15706 #define sc_x4_control_burst_error_mode_BURST_ERROR_24_BITS 9 15707 #define sc_x4_control_burst_error_mode_BURST_ERROR_25_BITS 10 15708 #define sc_x4_control_burst_error_mode_BURST_ERROR_26_BITS 11 15709 #define sc_x4_control_burst_error_mode_BURST_ERROR_27_BITS 12 15710 #define sc_x4_control_burst_error_mode_BURST_ERROR_28_BITS 13 15711 #define sc_x4_control_burst_error_mode_BURST_ERROR_29_BITS 14 15712 #define sc_x4_control_burst_error_mode_BURST_ERROR_30_BITS 15 15713 #define sc_x4_control_burst_error_mode_BURST_ERROR_31_BITS 16 15714 #define sc_x4_control_burst_error_mode_BURST_ERROR_32_BITS 17 15715 #define sc_x4_control_burst_error_mode_BURST_ERROR_33_BITS 18 15716 #define sc_x4_control_burst_error_mode_BURST_ERROR_34_BITS 19 15717 #define sc_x4_control_burst_error_mode_BURST_ERROR_35_BITS 20 15718 #define sc_x4_control_burst_error_mode_BURST_ERROR_36_BITS 21 15719 #define sc_x4_control_burst_error_mode_BURST_ERROR_37_BITS 22 15720 #define sc_x4_control_burst_error_mode_BURST_ERROR_38_BITS 23 15721 #define sc_x4_control_burst_error_mode_BURST_ERROR_39_BITS 24 15722 #define sc_x4_control_burst_error_mode_BURST_ERROR_40_BITS 25 15723 #define sc_x4_control_burst_error_mode_BURST_ERROR_41_BITS 26 15724 15725 /**************************************************************************** 15726 * Enums: sc_x4_control_bermon_state 15727 */ 15728 #define sc_x4_control_bermon_state_HI_BER 4 15729 #define sc_x4_control_bermon_state_GOOD_BER 3 15730 #define sc_x4_control_bermon_state_BER_TEST_SH 2 15731 #define sc_x4_control_bermon_state_START_TIMER 1 15732 #define sc_x4_control_bermon_state_BER_MT_INIT 0 15733 15734 /**************************************************************************** 15735 * Enums: sc_x4_control_rxsm_state_cl49 15736 */ 15737 #define sc_x4_control_rxsm_state_cl49_RX_HIG_END 128 15738 #define sc_x4_control_rxsm_state_cl49_RX_HIG_START 64 15739 #define sc_x4_control_rxsm_state_cl49_RX_LI 32 15740 #define sc_x4_control_rxsm_state_cl49_RX_E 16 15741 #define sc_x4_control_rxsm_state_cl49_RX_T 8 15742 #define sc_x4_control_rxsm_state_cl49_RX_D 4 15743 #define sc_x4_control_rxsm_state_cl49_RX_C 2 15744 #define sc_x4_control_rxsm_state_cl49_RX_INIT 1 15745 15746 /**************************************************************************** 15747 * Enums: sc_x4_control_r_type 15748 */ 15749 #define sc_x4_control_r_type_BAD_R_TYPE 15 15750 #define sc_x4_control_r_type_R_TYPE_B0 11 15751 #define sc_x4_control_r_type_R_TYPE_OB 10 15752 #define sc_x4_control_r_type_R_TYPE_B1 9 15753 #define sc_x4_control_r_type_R_TYPE_DB 8 15754 #define sc_x4_control_r_type_R_TYPE_FC 7 15755 #define sc_x4_control_r_type_R_TYPE_TB 6 15756 #define sc_x4_control_r_type_R_TYPE_LI 5 15757 #define sc_x4_control_r_type_R_TYPE_C 4 15758 #define sc_x4_control_r_type_R_TYPE_S 3 15759 #define sc_x4_control_r_type_R_TYPE_T 2 15760 #define sc_x4_control_r_type_R_TYPE_D 1 15761 #define sc_x4_control_r_type_R_TYPE_E 0 15762 15763 /**************************************************************************** 15764 * Enums: sc_x4_control_am_lock_state 15765 */ 15766 #define sc_x4_control_am_lock_state_INVALID_AM 512 15767 #define sc_x4_control_am_lock_state_GOOD_AM 256 15768 #define sc_x4_control_am_lock_state_COMP_AM 128 15769 #define sc_x4_control_am_lock_state_TIMER_2 64 15770 #define sc_x4_control_am_lock_state_AM_2_GOOD 32 15771 #define sc_x4_control_am_lock_state_COMP_2ND 16 15772 #define sc_x4_control_am_lock_state_TIMER_1 8 15773 #define sc_x4_control_am_lock_state_FIND_1ST 4 15774 #define sc_x4_control_am_lock_state_AM_RESET_CNT 2 15775 #define sc_x4_control_am_lock_state_AM_LOCK_INIT 1 15776 15777 /**************************************************************************** 15778 * Enums: sc_x4_control_msg_selector 15779 */ 15780 #define sc_x4_control_msg_selector_RESERVED 0 15781 #define sc_x4_control_msg_selector_VALUE_802p3 1 15782 #define sc_x4_control_msg_selector_VALUE_802p9 2 15783 #define sc_x4_control_msg_selector_VALUE_802p5 3 15784 #define sc_x4_control_msg_selector_VALUE_1394 4 15785 15786 /**************************************************************************** 15787 * Enums: sc_x4_control_synce_enum 15788 */ 15789 #define sc_x4_control_synce_enum_SYNCE_NO_DIV 0 15790 #define sc_x4_control_synce_enum_SYNCE_DIV_7 1 15791 #define sc_x4_control_synce_enum_SYNCE_DIV_11 2 15792 15793 /**************************************************************************** 15794 * Enums: sc_x4_control_synce_enum_stage0 15795 */ 15796 #define sc_x4_control_synce_enum_stage0_SYNCE_NO_DIV 0 15797 #define sc_x4_control_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 15798 #define sc_x4_control_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 15799 15800 /**************************************************************************** 15801 * Enums: sc_x4_control_cl91_sync_state 15802 */ 15803 #define sc_x4_control_cl91_sync_state_FIND_1ST 0 15804 #define sc_x4_control_cl91_sync_state_COUNT_NEXT 1 15805 #define sc_x4_control_cl91_sync_state_COMP_2ND 2 15806 #define sc_x4_control_cl91_sync_state_TWO_GOOD 3 15807 15808 /**************************************************************************** 15809 * Enums: sc_x4_control_cl91_algn_state 15810 */ 15811 #define sc_x4_control_cl91_algn_state_LOSS_OF_ALIGNMENT 0 15812 #define sc_x4_control_cl91_algn_state_DESKEW 1 15813 #define sc_x4_control_cl91_algn_state_DESKEW_FAIL 2 15814 #define sc_x4_control_cl91_algn_state_ALIGN_ACQUIRED 3 15815 #define sc_x4_control_cl91_algn_state_CW_GOOD 4 15816 #define sc_x4_control_cl91_algn_state_CW_BAD 5 15817 #define sc_x4_control_cl91_algn_state_THREE_BAD 6 15818 15819 /**************************************************************************** 15820 * Enums: sc_x4_control_fec_sel_override 15821 */ 15822 #define sc_x4_control_fec_sel_override_NO_OVERRIDE 0 15823 #define sc_x4_control_fec_sel_override_NO_FEC 1 15824 #define sc_x4_control_fec_sel_override_FEC_CL74 2 15825 #define sc_x4_control_fec_sel_override_FEC_CL91 3 15826 15827 /**************************************************************************** 15828 * Enums: sc_x4_control_cl91_blksync_mode 15829 */ 15830 #define sc_x4_control_cl91_blksync_mode_R_BLKSYNC_NO_CL91_FEC 0 15831 #define sc_x4_control_cl91_blksync_mode_R_BLKSYNC_CL91_QUAD_LANE_FEC 1 15832 #define sc_x4_control_cl91_blksync_mode_R_BLKSYNC_CL91_DUAL_LANE_FEC 2 15833 #define sc_x4_control_cl91_blksync_mode_R_BLKSYNC_CL91_SINGLE_LANE_FEC 3 15834 #define sc_x4_control_cl91_blksync_mode_R_BLKSYNC_CL91_FC_FEC 4 15835 15836 /**************************************************************************** 15837 * Enums: sc_x4_control_r_merge_mode 15838 */ 15839 #define sc_x4_control_r_merge_mode_R_MERGE_MODE_BYPASS 0 15840 #define sc_x4_control_r_merge_mode_R_MERGE_MODE_CL91_FC 1 15841 #define sc_x4_control_r_merge_mode_R_MERGE_MODE_CL91_SINGLE_LANE 2 15842 #define sc_x4_control_r_merge_mode_R_MERGE_MODE_CL91_DUAL_LANE 3 15843 #define sc_x4_control_r_merge_mode_R_MERGE_MODE_CL91_QUAD_LANE 4 15844 15845 /**************************************************************************** 15846 * Enums: sc_x4_control_r_tc_mode 15847 */ 15848 #define sc_x4_control_r_tc_mode_R_TC_MODE_SINGLE 0 15849 #define sc_x4_control_r_tc_mode_R_TC_MODE_DUAL 1 15850 #define sc_x4_control_r_tc_mode_R_TC_MODE_QUAD 2 15851 15852 /**************************************************************************** 15853 * Enums: sc_x4_control_r_tc_out_mode 15854 */ 15855 #define sc_x4_control_r_tc_out_mode_R_TC_OUT_MODE_SINGLE 0 15856 #define sc_x4_control_r_tc_out_mode_R_TC_OUT_MODE_DUAL 1 15857 #define sc_x4_control_r_tc_out_mode_R_TC_OUT_MODE_QUAD 2 15858 15859 /**************************************************************************** 15860 * Enums: sc_x4_control_cl91_fec_mode 15861 */ 15862 #define sc_x4_control_cl91_fec_mode_NO_CL91_FEC 0 15863 #define sc_x4_control_cl91_fec_mode_CL91_SINGLE_LANE_FC 1 15864 #define sc_x4_control_cl91_fec_mode_CL91_SINGLE_LANE_BRCM_PROP 2 15865 #define sc_x4_control_cl91_fec_mode_CL91_DUAL_LANE_BRCM_PROP 3 15866 #define sc_x4_control_cl91_fec_mode_CL91_QUAD_LANE 4 15867 #define sc_x4_control_cl91_fec_mode_IEEE_25G_CL91_SINGLE_LANE 5 15868 15869 /**************************************************************************** 15870 * Enums: sc_x4_control_am_spacing_mul 15871 */ 15872 #define sc_x4_control_am_spacing_mul_AM_SPACING_MUL_2 0 15873 #define sc_x4_control_am_spacing_mul_AM_SPACING_MUL_4 1 15874 #define sc_x4_control_am_spacing_mul_AM_SPACING_MUL_5 2 15875 #define sc_x4_control_am_spacing_mul_AM_SPACING_MUL_20 3 15876 15877 /**************************************************************************** 15878 * Enums: sc_x4_final_config_status_cl36TxEEEStates_l 15879 */ 15880 #define sc_x4_final_config_status_cl36TxEEEStates_l_TX_REFRESH 8 15881 #define sc_x4_final_config_status_cl36TxEEEStates_l_TX_QUIET 4 15882 #define sc_x4_final_config_status_cl36TxEEEStates_l_TX_SLEEP 2 15883 #define sc_x4_final_config_status_cl36TxEEEStates_l_TX_ACTIVE 1 15884 15885 /**************************************************************************** 15886 * Enums: sc_x4_final_config_status_cl36TxEEEStates_c 15887 */ 15888 #define sc_x4_final_config_status_cl36TxEEEStates_c_TX_REFRESH 3 15889 #define sc_x4_final_config_status_cl36TxEEEStates_c_TX_QUIET 2 15890 #define sc_x4_final_config_status_cl36TxEEEStates_c_TX_SLEEP 1 15891 #define sc_x4_final_config_status_cl36TxEEEStates_c_TX_ACTIVE 0 15892 15893 /**************************************************************************** 15894 * Enums: sc_x4_final_config_status_cl49TxEEEStates_l 15895 */ 15896 #define sc_x4_final_config_status_cl49TxEEEStates_l_SCR_RESET_2 64 15897 #define sc_x4_final_config_status_cl49TxEEEStates_l_SCR_RESET_1 32 15898 #define sc_x4_final_config_status_cl49TxEEEStates_l_TX_WAKE 16 15899 #define sc_x4_final_config_status_cl49TxEEEStates_l_TX_REFRESH 8 15900 #define sc_x4_final_config_status_cl49TxEEEStates_l_TX_QUIET 4 15901 #define sc_x4_final_config_status_cl49TxEEEStates_l_TX_SLEEP 2 15902 #define sc_x4_final_config_status_cl49TxEEEStates_l_TX_ACTIVE 1 15903 15904 /**************************************************************************** 15905 * Enums: sc_x4_final_config_status_fec_req_enum 15906 */ 15907 #define sc_x4_final_config_status_fec_req_enum_FEC_not_supported 0 15908 #define sc_x4_final_config_status_fec_req_enum_FEC_supported_but_not_requested 1 15909 #define sc_x4_final_config_status_fec_req_enum_invalid_setting 2 15910 #define sc_x4_final_config_status_fec_req_enum_FEC_supported_and_requested 3 15911 15912 /**************************************************************************** 15913 * Enums: sc_x4_final_config_status_cl73_pause_enum 15914 */ 15915 #define sc_x4_final_config_status_cl73_pause_enum_No_PAUSE_ability 0 15916 #define sc_x4_final_config_status_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 15917 #define sc_x4_final_config_status_cl73_pause_enum_Symmetric_PAUSE_ability 1 15918 #define sc_x4_final_config_status_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 15919 15920 /**************************************************************************** 15921 * Enums: sc_x4_final_config_status_cl49TxEEEStates_c 15922 */ 15923 #define sc_x4_final_config_status_cl49TxEEEStates_c_SCR_RESET_2 6 15924 #define sc_x4_final_config_status_cl49TxEEEStates_c_SCR_RESET_1 5 15925 #define sc_x4_final_config_status_cl49TxEEEStates_c_TX_WAKE 4 15926 #define sc_x4_final_config_status_cl49TxEEEStates_c_TX_REFRESH 3 15927 #define sc_x4_final_config_status_cl49TxEEEStates_c_TX_QUIET 2 15928 #define sc_x4_final_config_status_cl49TxEEEStates_c_TX_SLEEP 1 15929 #define sc_x4_final_config_status_cl49TxEEEStates_c_TX_ACTIVE 0 15930 15931 /**************************************************************************** 15932 * Enums: sc_x4_final_config_status_cl36RxEEEStates_l 15933 */ 15934 #define sc_x4_final_config_status_cl36RxEEEStates_l_RX_LINK_FAIL 32 15935 #define sc_x4_final_config_status_cl36RxEEEStates_l_RX_WTF 16 15936 #define sc_x4_final_config_status_cl36RxEEEStates_l_RX_WAKE 8 15937 #define sc_x4_final_config_status_cl36RxEEEStates_l_RX_QUIET 4 15938 #define sc_x4_final_config_status_cl36RxEEEStates_l_RX_SLEEP 2 15939 #define sc_x4_final_config_status_cl36RxEEEStates_l_RX_ACTIVE 1 15940 15941 /**************************************************************************** 15942 * Enums: sc_x4_final_config_status_cl36RxEEEStates_c 15943 */ 15944 #define sc_x4_final_config_status_cl36RxEEEStates_c_RX_LINK_FAIL 5 15945 #define sc_x4_final_config_status_cl36RxEEEStates_c_RX_WTF 4 15946 #define sc_x4_final_config_status_cl36RxEEEStates_c_RX_WAKE 3 15947 #define sc_x4_final_config_status_cl36RxEEEStates_c_RX_QUIET 2 15948 #define sc_x4_final_config_status_cl36RxEEEStates_c_RX_SLEEP 1 15949 #define sc_x4_final_config_status_cl36RxEEEStates_c_RX_ACTIVE 0 15950 15951 /**************************************************************************** 15952 * Enums: sc_x4_final_config_status_cl49RxEEEStates_l 15953 */ 15954 #define sc_x4_final_config_status_cl49RxEEEStates_l_RX_LINK_FAIL 32 15955 #define sc_x4_final_config_status_cl49RxEEEStates_l_RX_WTF 16 15956 #define sc_x4_final_config_status_cl49RxEEEStates_l_RX_WAKE 8 15957 #define sc_x4_final_config_status_cl49RxEEEStates_l_RX_QUIET 4 15958 #define sc_x4_final_config_status_cl49RxEEEStates_l_RX_SLEEP 2 15959 #define sc_x4_final_config_status_cl49RxEEEStates_l_RX_ACTIVE 1 15960 15961 /**************************************************************************** 15962 * Enums: sc_x4_final_config_status_cl49RxEEEStates_c 15963 */ 15964 #define sc_x4_final_config_status_cl49RxEEEStates_c_RX_LINK_FAIL 5 15965 #define sc_x4_final_config_status_cl49RxEEEStates_c_RX_WTF 4 15966 #define sc_x4_final_config_status_cl49RxEEEStates_c_RX_WAKE 3 15967 #define sc_x4_final_config_status_cl49RxEEEStates_c_RX_QUIET 2 15968 #define sc_x4_final_config_status_cl49RxEEEStates_c_RX_SLEEP 1 15969 #define sc_x4_final_config_status_cl49RxEEEStates_c_RX_ACTIVE 0 15970 15971 /**************************************************************************** 15972 * Enums: sc_x4_final_config_status_cl48TxEEEStates_l 15973 */ 15974 #define sc_x4_final_config_status_cl48TxEEEStates_l_TX_REFRESH 8 15975 #define sc_x4_final_config_status_cl48TxEEEStates_l_TX_QUIET 4 15976 #define sc_x4_final_config_status_cl48TxEEEStates_l_TX_SLEEP 2 15977 #define sc_x4_final_config_status_cl48TxEEEStates_l_TX_ACTIVE 1 15978 15979 /**************************************************************************** 15980 * Enums: sc_x4_final_config_status_cl48TxEEEStates_c 15981 */ 15982 #define sc_x4_final_config_status_cl48TxEEEStates_c_TX_REFRESH 3 15983 #define sc_x4_final_config_status_cl48TxEEEStates_c_TX_QUIET 2 15984 #define sc_x4_final_config_status_cl48TxEEEStates_c_TX_SLEEP 1 15985 #define sc_x4_final_config_status_cl48TxEEEStates_c_TX_ACTIVE 0 15986 15987 /**************************************************************************** 15988 * Enums: sc_x4_final_config_status_cl48RxEEEStates_l 15989 */ 15990 #define sc_x4_final_config_status_cl48RxEEEStates_l_RX_LINK_FAIL 32 15991 #define sc_x4_final_config_status_cl48RxEEEStates_l_RX_WAKE 16 15992 #define sc_x4_final_config_status_cl48RxEEEStates_l_RX_QUIET 8 15993 #define sc_x4_final_config_status_cl48RxEEEStates_l_RX_DEACT 4 15994 #define sc_x4_final_config_status_cl48RxEEEStates_l_RX_SLEEP 2 15995 #define sc_x4_final_config_status_cl48RxEEEStates_l_RX_ACTIVE 1 15996 15997 /**************************************************************************** 15998 * Enums: sc_x4_final_config_status_cl48RxEEEStates_c 15999 */ 16000 #define sc_x4_final_config_status_cl48RxEEEStates_c_RX_LINK_FAIL 5 16001 #define sc_x4_final_config_status_cl48RxEEEStates_c_RX_WAKE 4 16002 #define sc_x4_final_config_status_cl48RxEEEStates_c_RX_QUIET 3 16003 #define sc_x4_final_config_status_cl48RxEEEStates_c_RX_DEACT 2 16004 #define sc_x4_final_config_status_cl48RxEEEStates_c_RX_SLEEP 1 16005 #define sc_x4_final_config_status_cl48RxEEEStates_c_RX_ACTIVE 0 16006 16007 /**************************************************************************** 16008 * Enums: sc_x4_final_config_status_IQP_Options 16009 */ 16010 #define sc_x4_final_config_status_IQP_Options_i50uA 0 16011 #define sc_x4_final_config_status_IQP_Options_i100uA 1 16012 #define sc_x4_final_config_status_IQP_Options_i150uA 2 16013 #define sc_x4_final_config_status_IQP_Options_i200uA 3 16014 #define sc_x4_final_config_status_IQP_Options_i250uA 4 16015 #define sc_x4_final_config_status_IQP_Options_i300uA 5 16016 #define sc_x4_final_config_status_IQP_Options_i350uA 6 16017 #define sc_x4_final_config_status_IQP_Options_i400uA 7 16018 #define sc_x4_final_config_status_IQP_Options_i450uA 8 16019 #define sc_x4_final_config_status_IQP_Options_i500uA 9 16020 #define sc_x4_final_config_status_IQP_Options_i550uA 10 16021 #define sc_x4_final_config_status_IQP_Options_i600uA 11 16022 #define sc_x4_final_config_status_IQP_Options_i650uA 12 16023 #define sc_x4_final_config_status_IQP_Options_i700uA 13 16024 #define sc_x4_final_config_status_IQP_Options_i750uA 14 16025 #define sc_x4_final_config_status_IQP_Options_i800uA 15 16026 16027 /**************************************************************************** 16028 * Enums: sc_x4_final_config_status_IDriver_Options 16029 */ 16030 #define sc_x4_final_config_status_IDriver_Options_v680mV 0 16031 #define sc_x4_final_config_status_IDriver_Options_v730mV 1 16032 #define sc_x4_final_config_status_IDriver_Options_v780mV 2 16033 #define sc_x4_final_config_status_IDriver_Options_v830mV 3 16034 #define sc_x4_final_config_status_IDriver_Options_v880mV 4 16035 #define sc_x4_final_config_status_IDriver_Options_v930mV 5 16036 #define sc_x4_final_config_status_IDriver_Options_v980mV 6 16037 #define sc_x4_final_config_status_IDriver_Options_v1010mV 7 16038 #define sc_x4_final_config_status_IDriver_Options_v1040mV 8 16039 #define sc_x4_final_config_status_IDriver_Options_v1060mV 9 16040 #define sc_x4_final_config_status_IDriver_Options_v1070mV 10 16041 #define sc_x4_final_config_status_IDriver_Options_v1080mV 11 16042 #define sc_x4_final_config_status_IDriver_Options_v1085mV 12 16043 #define sc_x4_final_config_status_IDriver_Options_v1090mV 13 16044 #define sc_x4_final_config_status_IDriver_Options_v1095mV 14 16045 #define sc_x4_final_config_status_IDriver_Options_v1100mV 15 16046 16047 /**************************************************************************** 16048 * Enums: sc_x4_final_config_status_operationModes 16049 */ 16050 #define sc_x4_final_config_status_operationModes_XGXS 0 16051 #define sc_x4_final_config_status_operationModes_XGXG_nCC 1 16052 #define sc_x4_final_config_status_operationModes_Indlane_OS8 4 16053 #define sc_x4_final_config_status_operationModes_IndLane_OS5 5 16054 #define sc_x4_final_config_status_operationModes_PCI 7 16055 #define sc_x4_final_config_status_operationModes_XGXS_nLQ 8 16056 #define sc_x4_final_config_status_operationModes_XGXS_nLQnCC 9 16057 #define sc_x4_final_config_status_operationModes_PBypass 10 16058 #define sc_x4_final_config_status_operationModes_PBypass_nDSK 11 16059 #define sc_x4_final_config_status_operationModes_ComboCoreMode 12 16060 #define sc_x4_final_config_status_operationModes_Clocks_off 15 16061 16062 /**************************************************************************** 16063 * Enums: sc_x4_final_config_status_actualSpeeds 16064 */ 16065 #define sc_x4_final_config_status_actualSpeeds_dr_10M 0 16066 #define sc_x4_final_config_status_actualSpeeds_dr_100M 1 16067 #define sc_x4_final_config_status_actualSpeeds_dr_1G 2 16068 #define sc_x4_final_config_status_actualSpeeds_dr_2p5G 3 16069 #define sc_x4_final_config_status_actualSpeeds_dr_5G_X4 4 16070 #define sc_x4_final_config_status_actualSpeeds_dr_6G_X4 5 16071 #define sc_x4_final_config_status_actualSpeeds_dr_10G_HiG 6 16072 #define sc_x4_final_config_status_actualSpeeds_dr_10G_CX4 7 16073 #define sc_x4_final_config_status_actualSpeeds_dr_12G_HiG 8 16074 #define sc_x4_final_config_status_actualSpeeds_dr_12p5G_X4 9 16075 #define sc_x4_final_config_status_actualSpeeds_dr_13G_X4 10 16076 #define sc_x4_final_config_status_actualSpeeds_dr_15G_X4 11 16077 #define sc_x4_final_config_status_actualSpeeds_dr_16G_X4 12 16078 #define sc_x4_final_config_status_actualSpeeds_dr_1G_KX 13 16079 #define sc_x4_final_config_status_actualSpeeds_dr_10G_KX4 14 16080 #define sc_x4_final_config_status_actualSpeeds_dr_10G_KR 15 16081 #define sc_x4_final_config_status_actualSpeeds_dr_5G 16 16082 #define sc_x4_final_config_status_actualSpeeds_dr_6p4G 17 16083 #define sc_x4_final_config_status_actualSpeeds_dr_20G_X4 18 16084 #define sc_x4_final_config_status_actualSpeeds_dr_21G_X4 19 16085 #define sc_x4_final_config_status_actualSpeeds_dr_25G_X4 20 16086 #define sc_x4_final_config_status_actualSpeeds_dr_10G_HiG_DXGXS 21 16087 #define sc_x4_final_config_status_actualSpeeds_dr_10G_DXGXS 22 16088 #define sc_x4_final_config_status_actualSpeeds_dr_10p5G_HiG_DXGXS 23 16089 #define sc_x4_final_config_status_actualSpeeds_dr_10p5G_DXGXS 24 16090 #define sc_x4_final_config_status_actualSpeeds_dr_12p773G_HiG_DXGXS 25 16091 #define sc_x4_final_config_status_actualSpeeds_dr_12p773G_DXGXS 26 16092 #define sc_x4_final_config_status_actualSpeeds_dr_10G_XFI 27 16093 #define sc_x4_final_config_status_actualSpeeds_dr_40G 28 16094 #define sc_x4_final_config_status_actualSpeeds_dr_20G_HiG_DXGXS 29 16095 #define sc_x4_final_config_status_actualSpeeds_dr_20G_DXGXS 30 16096 #define sc_x4_final_config_status_actualSpeeds_dr_10G_SFI 31 16097 #define sc_x4_final_config_status_actualSpeeds_dr_31p5G 32 16098 #define sc_x4_final_config_status_actualSpeeds_dr_32p7G 33 16099 #define sc_x4_final_config_status_actualSpeeds_dr_20G_SCR 34 16100 #define sc_x4_final_config_status_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 16101 #define sc_x4_final_config_status_actualSpeeds_dr_10G_DXGXS_SCR 36 16102 #define sc_x4_final_config_status_actualSpeeds_dr_12G_R2 37 16103 #define sc_x4_final_config_status_actualSpeeds_dr_10G_X2 38 16104 #define sc_x4_final_config_status_actualSpeeds_dr_40G_KR4 39 16105 #define sc_x4_final_config_status_actualSpeeds_dr_40G_CR4 40 16106 #define sc_x4_final_config_status_actualSpeeds_dr_100G_CR10 41 16107 #define sc_x4_final_config_status_actualSpeeds_dr_15p75G_DXGXS 44 16108 #define sc_x4_final_config_status_actualSpeeds_dr_20G_KR2 57 16109 #define sc_x4_final_config_status_actualSpeeds_dr_20G_CR2 58 16110 16111 /**************************************************************************** 16112 * Enums: sc_x4_final_config_status_actualSpeedsMisc1 16113 */ 16114 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_2500BRCM_X1 16 16115 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_5000BRCM_X4 17 16116 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_6000BRCM_X4 18 16117 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_10GHiGig_X4 19 16118 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_10GBASE_CX4 20 16119 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_12GHiGig_X4 21 16120 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 16121 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_13GHiGig_X4 23 16122 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_15GHiGig_X4 24 16123 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_16GHiGig_X4 25 16124 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_5000BRCM_X1 26 16125 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_6363BRCM_X1 27 16126 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_20GHiGig_X4 28 16127 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_21GHiGig_X4 29 16128 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 16129 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 16130 16131 /**************************************************************************** 16132 * Enums: sc_x4_final_config_status_IndLaneModes 16133 */ 16134 #define sc_x4_final_config_status_IndLaneModes_SWSDR_div2 0 16135 #define sc_x4_final_config_status_IndLaneModes_SWSDR_div1 1 16136 #define sc_x4_final_config_status_IndLaneModes_DWSDR_div2 2 16137 #define sc_x4_final_config_status_IndLaneModes_DWSDR_div1 3 16138 16139 /**************************************************************************** 16140 * Enums: sc_x4_final_config_status_prbsSelect 16141 */ 16142 #define sc_x4_final_config_status_prbsSelect_prbs7 0 16143 #define sc_x4_final_config_status_prbsSelect_prbs15 1 16144 #define sc_x4_final_config_status_prbsSelect_prbs23 2 16145 #define sc_x4_final_config_status_prbsSelect_prbs31 3 16146 16147 /**************************************************************************** 16148 * Enums: sc_x4_final_config_status_vcoDivider 16149 */ 16150 #define sc_x4_final_config_status_vcoDivider_div32 0 16151 #define sc_x4_final_config_status_vcoDivider_div36 1 16152 #define sc_x4_final_config_status_vcoDivider_div40 2 16153 #define sc_x4_final_config_status_vcoDivider_div42 3 16154 #define sc_x4_final_config_status_vcoDivider_div48 4 16155 #define sc_x4_final_config_status_vcoDivider_div50 5 16156 #define sc_x4_final_config_status_vcoDivider_div52 6 16157 #define sc_x4_final_config_status_vcoDivider_div54 7 16158 #define sc_x4_final_config_status_vcoDivider_div60 8 16159 #define sc_x4_final_config_status_vcoDivider_div64 9 16160 #define sc_x4_final_config_status_vcoDivider_div66 10 16161 #define sc_x4_final_config_status_vcoDivider_div68 11 16162 #define sc_x4_final_config_status_vcoDivider_div70 12 16163 #define sc_x4_final_config_status_vcoDivider_div80 13 16164 #define sc_x4_final_config_status_vcoDivider_div92 14 16165 #define sc_x4_final_config_status_vcoDivider_div100 15 16166 16167 /**************************************************************************** 16168 * Enums: sc_x4_final_config_status_refClkSelect 16169 */ 16170 #define sc_x4_final_config_status_refClkSelect_clk_25MHz 0 16171 #define sc_x4_final_config_status_refClkSelect_clk_100MHz 1 16172 #define sc_x4_final_config_status_refClkSelect_clk_125MHz 2 16173 #define sc_x4_final_config_status_refClkSelect_clk_156p25MHz 3 16174 #define sc_x4_final_config_status_refClkSelect_clk_187p5MHz 4 16175 #define sc_x4_final_config_status_refClkSelect_clk_161p25Mhz 5 16176 #define sc_x4_final_config_status_refClkSelect_clk_50Mhz 6 16177 #define sc_x4_final_config_status_refClkSelect_clk_106p25Mhz 7 16178 16179 /**************************************************************************** 16180 * Enums: sc_x4_final_config_status_aerMMDdevTypeSelect 16181 */ 16182 #define sc_x4_final_config_status_aerMMDdevTypeSelect_combo_core 0 16183 #define sc_x4_final_config_status_aerMMDdevTypeSelect_PMA_PMD 1 16184 #define sc_x4_final_config_status_aerMMDdevTypeSelect_PCS 3 16185 #define sc_x4_final_config_status_aerMMDdevTypeSelect_PHY 4 16186 #define sc_x4_final_config_status_aerMMDdevTypeSelect_DTE 5 16187 #define sc_x4_final_config_status_aerMMDdevTypeSelect_CL73_AN 7 16188 16189 /**************************************************************************** 16190 * Enums: sc_x4_final_config_status_aerMMDportSelect 16191 */ 16192 #define sc_x4_final_config_status_aerMMDportSelect_ln0 0 16193 #define sc_x4_final_config_status_aerMMDportSelect_ln1 1 16194 #define sc_x4_final_config_status_aerMMDportSelect_ln2 2 16195 #define sc_x4_final_config_status_aerMMDportSelect_ln3 3 16196 #define sc_x4_final_config_status_aerMMDportSelect_BCST_ln0_1_2_3 511 16197 #define sc_x4_final_config_status_aerMMDportSelect_BCST_ln0_1 512 16198 #define sc_x4_final_config_status_aerMMDportSelect_BCST_ln2_3 513 16199 16200 /**************************************************************************** 16201 * Enums: sc_x4_final_config_status_firmwareModeSelect 16202 */ 16203 #define sc_x4_final_config_status_firmwareModeSelect_DEFAULT 0 16204 #define sc_x4_final_config_status_firmwareModeSelect_SFP_OPT_LR 1 16205 #define sc_x4_final_config_status_firmwareModeSelect_SFP_DAC 2 16206 #define sc_x4_final_config_status_firmwareModeSelect_XLAUI 3 16207 #define sc_x4_final_config_status_firmwareModeSelect_LONG_CH_6G 4 16208 16209 /**************************************************************************** 16210 * Enums: sc_x4_final_config_status_tempIdxSelect 16211 */ 16212 #define sc_x4_final_config_status_tempIdxSelect_LTE__22p9C 15 16213 #define sc_x4_final_config_status_tempIdxSelect_LTE__12p6C 14 16214 #define sc_x4_final_config_status_tempIdxSelect_LTE__3p0C 13 16215 #define sc_x4_final_config_status_tempIdxSelect_LTE_6p7C 12 16216 #define sc_x4_final_config_status_tempIdxSelect_LTE_16p4C 11 16217 #define sc_x4_final_config_status_tempIdxSelect_LTE_26p6C 10 16218 #define sc_x4_final_config_status_tempIdxSelect_LTE_36p3C 9 16219 #define sc_x4_final_config_status_tempIdxSelect_LTE_46p0C 8 16220 #define sc_x4_final_config_status_tempIdxSelect_LTE_56p2C 7 16221 #define sc_x4_final_config_status_tempIdxSelect_LTE_65p9C 6 16222 #define sc_x4_final_config_status_tempIdxSelect_LTE_75p6C 5 16223 #define sc_x4_final_config_status_tempIdxSelect_LTE_85p3C 4 16224 #define sc_x4_final_config_status_tempIdxSelect_LTE_95p5C 3 16225 #define sc_x4_final_config_status_tempIdxSelect_LTE_105p2C 2 16226 #define sc_x4_final_config_status_tempIdxSelect_LTE_114p9C 1 16227 #define sc_x4_final_config_status_tempIdxSelect_LTE_125p1C 0 16228 16229 /**************************************************************************** 16230 * Enums: sc_x4_final_config_status_port_mode 16231 */ 16232 #define sc_x4_final_config_status_port_mode_QUAD_PORT 0 16233 #define sc_x4_final_config_status_port_mode_TRI_1_PORT 1 16234 #define sc_x4_final_config_status_port_mode_TRI_2_PORT 2 16235 #define sc_x4_final_config_status_port_mode_DUAL_PORT 3 16236 #define sc_x4_final_config_status_port_mode_SINGLE_PORT 4 16237 16238 /**************************************************************************** 16239 * Enums: sc_x4_final_config_status_rev_letter_enum 16240 */ 16241 #define sc_x4_final_config_status_rev_letter_enum_REV_A 0 16242 #define sc_x4_final_config_status_rev_letter_enum_REV_B 1 16243 #define sc_x4_final_config_status_rev_letter_enum_REV_C 2 16244 #define sc_x4_final_config_status_rev_letter_enum_REV_D 3 16245 16246 /**************************************************************************** 16247 * Enums: sc_x4_final_config_status_rev_number_enum 16248 */ 16249 #define sc_x4_final_config_status_rev_number_enum_REV_0 0 16250 #define sc_x4_final_config_status_rev_number_enum_REV_1 1 16251 #define sc_x4_final_config_status_rev_number_enum_REV_2 2 16252 #define sc_x4_final_config_status_rev_number_enum_REV_3 3 16253 #define sc_x4_final_config_status_rev_number_enum_REV_4 4 16254 #define sc_x4_final_config_status_rev_number_enum_REV_5 5 16255 #define sc_x4_final_config_status_rev_number_enum_REV_6 6 16256 #define sc_x4_final_config_status_rev_number_enum_REV_7 7 16257 16258 /**************************************************************************** 16259 * Enums: sc_x4_final_config_status_bonding_enum 16260 */ 16261 #define sc_x4_final_config_status_bonding_enum_WIRE_BOND 0 16262 #define sc_x4_final_config_status_bonding_enum_FLIP_CHIP 1 16263 16264 /**************************************************************************** 16265 * Enums: sc_x4_final_config_status_tech_process 16266 */ 16267 #define sc_x4_final_config_status_tech_process_PROCESS_90NM 0 16268 #define sc_x4_final_config_status_tech_process_PROCESS_65NM 1 16269 #define sc_x4_final_config_status_tech_process_PROCESS_40NM 2 16270 #define sc_x4_final_config_status_tech_process_PROCESS_28NM 3 16271 #define sc_x4_final_config_status_tech_process_PROCESS_16NM 4 16272 16273 /**************************************************************************** 16274 * Enums: sc_x4_final_config_status_model_num 16275 */ 16276 #define sc_x4_final_config_status_model_num_SERDES_CL73 0 16277 #define sc_x4_final_config_status_model_num_XGXS_16G 1 16278 #define sc_x4_final_config_status_model_num_HYPERCORE 2 16279 #define sc_x4_final_config_status_model_num_HYPERLITE 3 16280 #define sc_x4_final_config_status_model_num_PCIE_G2_PIPE 4 16281 #define sc_x4_final_config_status_model_num_SERDES_1p25GBd 5 16282 #define sc_x4_final_config_status_model_num_SATA2 6 16283 #define sc_x4_final_config_status_model_num_QSGMII 7 16284 #define sc_x4_final_config_status_model_num_XGXS10G 8 16285 #define sc_x4_final_config_status_model_num_WARPCORE 9 16286 #define sc_x4_final_config_status_model_num_XFICORE 10 16287 #define sc_x4_final_config_status_model_num_RXFI 11 16288 #define sc_x4_final_config_status_model_num_WARPLITE 12 16289 #define sc_x4_final_config_status_model_num_PENTACORE 13 16290 #define sc_x4_final_config_status_model_num_ESM 14 16291 #define sc_x4_final_config_status_model_num_QUAD_SGMII 15 16292 #define sc_x4_final_config_status_model_num_WARPCORE_3 16 16293 #define sc_x4_final_config_status_model_num_TSC 17 16294 #define sc_x4_final_config_status_model_num_TSC4E 18 16295 #define sc_x4_final_config_status_model_num_TSC12E 19 16296 #define sc_x4_final_config_status_model_num_TSC4F 20 16297 #define sc_x4_final_config_status_model_num_TSC4F_GEN2 21 16298 #define sc_x4_final_config_status_model_num_XGXS_CL73_90NM 29 16299 #define sc_x4_final_config_status_model_num_SERDES_CL73_90NM 30 16300 #define sc_x4_final_config_status_model_num_WARPCORE3 32 16301 #define sc_x4_final_config_status_model_num_WARPCORE4_TSC 33 16302 #define sc_x4_final_config_status_model_num_RXAUI 34 16303 16304 /**************************************************************************** 16305 * Enums: sc_x4_final_config_status_payload 16306 */ 16307 #define sc_x4_final_config_status_payload_REPEAT_2_BYTES 0 16308 #define sc_x4_final_config_status_payload_RAMPING 1 16309 #define sc_x4_final_config_status_payload_CL48_CRPAT 2 16310 #define sc_x4_final_config_status_payload_CL48_CJPAT 3 16311 #define sc_x4_final_config_status_payload_CL36_LONG_CRPAT 4 16312 #define sc_x4_final_config_status_payload_CL36_SHORT_CRPAT 5 16313 16314 /**************************************************************************** 16315 * Enums: sc_x4_final_config_status_sc 16316 */ 16317 #define sc_x4_final_config_status_sc_S_10G_CR1 0 16318 #define sc_x4_final_config_status_sc_S_10G_KR1 1 16319 #define sc_x4_final_config_status_sc_S_10G_X1 2 16320 #define sc_x4_final_config_status_sc_S_10G_HG2_CR1 4 16321 #define sc_x4_final_config_status_sc_S_10G_HG2_KR1 5 16322 #define sc_x4_final_config_status_sc_S_10G_HG2_X1 6 16323 #define sc_x4_final_config_status_sc_S_20G_CR1 8 16324 #define sc_x4_final_config_status_sc_S_20G_KR1 9 16325 #define sc_x4_final_config_status_sc_S_20G_X1 10 16326 #define sc_x4_final_config_status_sc_S_20G_HG2_CR1 12 16327 #define sc_x4_final_config_status_sc_S_20G_HG2_KR1 13 16328 #define sc_x4_final_config_status_sc_S_20G_HG2_X1 14 16329 #define sc_x4_final_config_status_sc_S_25G_CR1 16 16330 #define sc_x4_final_config_status_sc_S_25G_KR1 17 16331 #define sc_x4_final_config_status_sc_S_25G_X1 18 16332 #define sc_x4_final_config_status_sc_S_25G_HG2_CR1 20 16333 #define sc_x4_final_config_status_sc_S_25G_HG2_KR1 21 16334 #define sc_x4_final_config_status_sc_S_25G_HG2_X1 22 16335 #define sc_x4_final_config_status_sc_S_20G_CR2 24 16336 #define sc_x4_final_config_status_sc_S_20G_KR2 25 16337 #define sc_x4_final_config_status_sc_S_20G_X2 26 16338 #define sc_x4_final_config_status_sc_S_20G_HG2_CR2 28 16339 #define sc_x4_final_config_status_sc_S_20G_HG2_KR2 29 16340 #define sc_x4_final_config_status_sc_S_20G_HG2_X2 30 16341 #define sc_x4_final_config_status_sc_S_40G_CR2 32 16342 #define sc_x4_final_config_status_sc_S_40G_KR2 33 16343 #define sc_x4_final_config_status_sc_S_40G_X2 34 16344 #define sc_x4_final_config_status_sc_S_40G_HG2_CR2 36 16345 #define sc_x4_final_config_status_sc_S_40G_HG2_KR2 37 16346 #define sc_x4_final_config_status_sc_S_40G_HG2_X2 38 16347 #define sc_x4_final_config_status_sc_S_40G_CR4 40 16348 #define sc_x4_final_config_status_sc_S_40G_KR4 41 16349 #define sc_x4_final_config_status_sc_S_40G_X4 42 16350 #define sc_x4_final_config_status_sc_S_40G_HG2_CR4 44 16351 #define sc_x4_final_config_status_sc_S_40G_HG2_KR4 45 16352 #define sc_x4_final_config_status_sc_S_40G_HG2_X4 46 16353 #define sc_x4_final_config_status_sc_S_50G_CR2 48 16354 #define sc_x4_final_config_status_sc_S_50G_KR2 49 16355 #define sc_x4_final_config_status_sc_S_50G_X2 50 16356 #define sc_x4_final_config_status_sc_S_50G_HG2_CR2 52 16357 #define sc_x4_final_config_status_sc_S_50G_HG2_KR2 53 16358 #define sc_x4_final_config_status_sc_S_50G_HG2_X2 54 16359 #define sc_x4_final_config_status_sc_S_50G_CR4 56 16360 #define sc_x4_final_config_status_sc_S_50G_KR4 57 16361 #define sc_x4_final_config_status_sc_S_50G_X4 58 16362 #define sc_x4_final_config_status_sc_S_50G_HG2_CR4 60 16363 #define sc_x4_final_config_status_sc_S_50G_HG2_KR4 61 16364 #define sc_x4_final_config_status_sc_S_50G_HG2_X4 62 16365 #define sc_x4_final_config_status_sc_S_100G_CR4 64 16366 #define sc_x4_final_config_status_sc_S_100G_KR4 65 16367 #define sc_x4_final_config_status_sc_S_100G_X4 66 16368 #define sc_x4_final_config_status_sc_S_100G_HG2_CR4 68 16369 #define sc_x4_final_config_status_sc_S_100G_HG2_KR4 69 16370 #define sc_x4_final_config_status_sc_S_100G_HG2_X4 70 16371 #define sc_x4_final_config_status_sc_S_CL73_20GVCO 72 16372 #define sc_x4_final_config_status_sc_S_CL73_25GVCO 80 16373 #define sc_x4_final_config_status_sc_S_CL36_20GVCO 88 16374 #define sc_x4_final_config_status_sc_S_CL36_25GVCO 96 16375 #define sc_x4_final_config_status_sc_S_25G_CR_IEEE 112 16376 #define sc_x4_final_config_status_sc_S_25G_CRS_IEEE 113 16377 #define sc_x4_final_config_status_sc_S_25G_KR_IEEE 114 16378 #define sc_x4_final_config_status_sc_S_25G_KRS_IEEE 115 16379 16380 /**************************************************************************** 16381 * Enums: sc_x4_final_config_status_t_fifo_modes 16382 */ 16383 #define sc_x4_final_config_status_t_fifo_modes_T_FIFO_INSERT_NO_AM 0 16384 #define sc_x4_final_config_status_t_fifo_modes_T_FIFO_INSERT_4_AM 1 16385 #define sc_x4_final_config_status_t_fifo_modes_T_FIFO_INSERT_20_AM 2 16386 #define sc_x4_final_config_status_t_fifo_modes_T_FIFO_INSERT_2_AM 3 16387 16388 /**************************************************************************** 16389 * Enums: sc_x4_final_config_status_t_enc_modes 16390 */ 16391 #define sc_x4_final_config_status_t_enc_modes_T_ENC_MODE_BYPASS 0 16392 #define sc_x4_final_config_status_t_enc_modes_T_ENC_MODE_CL49 1 16393 #define sc_x4_final_config_status_t_enc_modes_T_ENC_MODE_CL82 2 16394 16395 /**************************************************************************** 16396 * Enums: sc_x4_final_config_status_btmx_mode 16397 */ 16398 #define sc_x4_final_config_status_btmx_mode_BS_BTMX_MODE_1to1 0 16399 #define sc_x4_final_config_status_btmx_mode_BS_BTMX_MODE_2to1 1 16400 #define sc_x4_final_config_status_btmx_mode_BS_BTMX_MODE_5to1 2 16401 16402 /**************************************************************************** 16403 * Enums: sc_x4_final_config_status_t_type_cl82 16404 */ 16405 #define sc_x4_final_config_status_t_type_cl82_T_TYPE_B1 5 16406 #define sc_x4_final_config_status_t_type_cl82_T_TYPE_C 4 16407 #define sc_x4_final_config_status_t_type_cl82_T_TYPE_S 3 16408 #define sc_x4_final_config_status_t_type_cl82_T_TYPE_T 2 16409 #define sc_x4_final_config_status_t_type_cl82_T_TYPE_D 1 16410 #define sc_x4_final_config_status_t_type_cl82_T_TYPE_E 0 16411 16412 /**************************************************************************** 16413 * Enums: sc_x4_final_config_status_txsm_state_cl82 16414 */ 16415 #define sc_x4_final_config_status_txsm_state_cl82_TX_HIG_END 6 16416 #define sc_x4_final_config_status_txsm_state_cl82_TX_HIG_START 5 16417 #define sc_x4_final_config_status_txsm_state_cl82_TX_E 4 16418 #define sc_x4_final_config_status_txsm_state_cl82_TX_T 3 16419 #define sc_x4_final_config_status_txsm_state_cl82_TX_D 2 16420 #define sc_x4_final_config_status_txsm_state_cl82_TX_C 1 16421 #define sc_x4_final_config_status_txsm_state_cl82_TX_INIT 0 16422 16423 /**************************************************************************** 16424 * Enums: sc_x4_final_config_status_ltxsm_state_cl82 16425 */ 16426 #define sc_x4_final_config_status_ltxsm_state_cl82_TX_HIG_END 64 16427 #define sc_x4_final_config_status_ltxsm_state_cl82_TX_HIG_START 32 16428 #define sc_x4_final_config_status_ltxsm_state_cl82_TX_E 16 16429 #define sc_x4_final_config_status_ltxsm_state_cl82_TX_T 8 16430 #define sc_x4_final_config_status_ltxsm_state_cl82_TX_D 4 16431 #define sc_x4_final_config_status_ltxsm_state_cl82_TX_C 2 16432 #define sc_x4_final_config_status_ltxsm_state_cl82_TX_INIT 1 16433 16434 /**************************************************************************** 16435 * Enums: sc_x4_final_config_status_r_type_coded_cl82 16436 */ 16437 #define sc_x4_final_config_status_r_type_coded_cl82_R_TYPE_B1 32 16438 #define sc_x4_final_config_status_r_type_coded_cl82_R_TYPE_C 16 16439 #define sc_x4_final_config_status_r_type_coded_cl82_R_TYPE_S 8 16440 #define sc_x4_final_config_status_r_type_coded_cl82_R_TYPE_T 4 16441 #define sc_x4_final_config_status_r_type_coded_cl82_R_TYPE_D 2 16442 #define sc_x4_final_config_status_r_type_coded_cl82_R_TYPE_E 1 16443 16444 /**************************************************************************** 16445 * Enums: sc_x4_final_config_status_rxsm_state_cl82 16446 */ 16447 #define sc_x4_final_config_status_rxsm_state_cl82_RX_HIG_END 64 16448 #define sc_x4_final_config_status_rxsm_state_cl82_RX_HIG_START 32 16449 #define sc_x4_final_config_status_rxsm_state_cl82_RX_E 16 16450 #define sc_x4_final_config_status_rxsm_state_cl82_RX_T 8 16451 #define sc_x4_final_config_status_rxsm_state_cl82_RX_D 4 16452 #define sc_x4_final_config_status_rxsm_state_cl82_RX_C 2 16453 #define sc_x4_final_config_status_rxsm_state_cl82_RX_INIT 1 16454 16455 /**************************************************************************** 16456 * Enums: sc_x4_final_config_status_deskew_state 16457 */ 16458 #define sc_x4_final_config_status_deskew_state_ALIGN_ACQUIRED 2 16459 #define sc_x4_final_config_status_deskew_state_LOSS_OF_ALIGNMENT 1 16460 16461 /**************************************************************************** 16462 * Enums: sc_x4_final_config_status_os_mode_enum 16463 */ 16464 #define sc_x4_final_config_status_os_mode_enum_OS_MODE_1 0 16465 #define sc_x4_final_config_status_os_mode_enum_OS_MODE_2 1 16466 #define sc_x4_final_config_status_os_mode_enum_OS_MODE_4 2 16467 #define sc_x4_final_config_status_os_mode_enum_OS_MODE_16p5 8 16468 #define sc_x4_final_config_status_os_mode_enum_OS_MODE_20p625 12 16469 16470 /**************************************************************************** 16471 * Enums: sc_x4_final_config_status_scr_modes 16472 */ 16473 #define sc_x4_final_config_status_scr_modes_T_SCR_MODE_BYPASS 0 16474 #define sc_x4_final_config_status_scr_modes_T_SCR_MODE_CL49 1 16475 #define sc_x4_final_config_status_scr_modes_T_SCR_MODE_40G_2_LANE 2 16476 #define sc_x4_final_config_status_scr_modes_T_SCR_MODE_100G 3 16477 #define sc_x4_final_config_status_scr_modes_T_SCR_MODE_20G 4 16478 #define sc_x4_final_config_status_scr_modes_T_SCR_MODE_40G_4_LANE 5 16479 16480 /**************************************************************************** 16481 * Enums: sc_x4_final_config_status_descr_modes 16482 */ 16483 #define sc_x4_final_config_status_descr_modes_R_DESCR_MODE_BYPASS 0 16484 #define sc_x4_final_config_status_descr_modes_R_DESCR_MODE_CL49 1 16485 #define sc_x4_final_config_status_descr_modes_R_DESCR_MODE_CL82 2 16486 16487 /**************************************************************************** 16488 * Enums: sc_x4_final_config_status_r_dec_tl_mode 16489 */ 16490 #define sc_x4_final_config_status_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 16491 #define sc_x4_final_config_status_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 16492 #define sc_x4_final_config_status_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 16493 16494 /**************************************************************************** 16495 * Enums: sc_x4_final_config_status_r_dec_fsm_mode 16496 */ 16497 #define sc_x4_final_config_status_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 16498 #define sc_x4_final_config_status_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 16499 #define sc_x4_final_config_status_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 16500 16501 /**************************************************************************** 16502 * Enums: sc_x4_final_config_status_r_deskew_mode 16503 */ 16504 #define sc_x4_final_config_status_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 16505 #define sc_x4_final_config_status_r_deskew_mode_R_DESKEW_MODE_20G 1 16506 #define sc_x4_final_config_status_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 16507 #define sc_x4_final_config_status_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 16508 #define sc_x4_final_config_status_r_deskew_mode_R_DESKEW_MODE_100G 4 16509 #define sc_x4_final_config_status_r_deskew_mode_R_DESKEW_MODE_CL49 5 16510 #define sc_x4_final_config_status_r_deskew_mode_R_DESKEW_MODE_CL91_QUAD 6 16511 #define sc_x4_final_config_status_r_deskew_mode_R_DESKEW_MODE_CL91_SINGLE_BRCM 7 16512 #define sc_x4_final_config_status_r_deskew_mode_R_DESKEW_MODE_CL91_DUAL_BRCM 8 16513 #define sc_x4_final_config_status_r_deskew_mode_R_DESKEW_MODE_CL91_FC 9 16514 16515 /**************************************************************************** 16516 * Enums: sc_x4_final_config_status_bs_dist_modes 16517 */ 16518 #define sc_x4_final_config_status_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 16519 #define sc_x4_final_config_status_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 16520 #define sc_x4_final_config_status_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 16521 #define sc_x4_final_config_status_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 16522 16523 /**************************************************************************** 16524 * Enums: sc_x4_final_config_status_cl49_t_type 16525 */ 16526 #define sc_x4_final_config_status_cl49_t_type_BAD_T_TYPE 15 16527 #define sc_x4_final_config_status_cl49_t_type_T_TYPE_B0 11 16528 #define sc_x4_final_config_status_cl49_t_type_T_TYPE_OB 10 16529 #define sc_x4_final_config_status_cl49_t_type_T_TYPE_B1 9 16530 #define sc_x4_final_config_status_cl49_t_type_T_TYPE_DB 8 16531 #define sc_x4_final_config_status_cl49_t_type_T_TYPE_FC 7 16532 #define sc_x4_final_config_status_cl49_t_type_T_TYPE_TB 6 16533 #define sc_x4_final_config_status_cl49_t_type_T_TYPE_LI 5 16534 #define sc_x4_final_config_status_cl49_t_type_T_TYPE_C 4 16535 #define sc_x4_final_config_status_cl49_t_type_T_TYPE_S 3 16536 #define sc_x4_final_config_status_cl49_t_type_T_TYPE_T 2 16537 #define sc_x4_final_config_status_cl49_t_type_T_TYPE_D 1 16538 #define sc_x4_final_config_status_cl49_t_type_T_TYPE_E 0 16539 16540 /**************************************************************************** 16541 * Enums: sc_x4_final_config_status_cl49_txsm_states 16542 */ 16543 #define sc_x4_final_config_status_cl49_txsm_states_TX_HIG_END 7 16544 #define sc_x4_final_config_status_cl49_txsm_states_TX_HIG_START 6 16545 #define sc_x4_final_config_status_cl49_txsm_states_TX_LI 5 16546 #define sc_x4_final_config_status_cl49_txsm_states_TX_E 4 16547 #define sc_x4_final_config_status_cl49_txsm_states_TX_T 3 16548 #define sc_x4_final_config_status_cl49_txsm_states_TX_D 2 16549 #define sc_x4_final_config_status_cl49_txsm_states_TX_C 1 16550 #define sc_x4_final_config_status_cl49_txsm_states_TX_INIT 0 16551 16552 /**************************************************************************** 16553 * Enums: sc_x4_final_config_status_cl49_ltxsm_states 16554 */ 16555 #define sc_x4_final_config_status_cl49_ltxsm_states_TX_HIG_END 128 16556 #define sc_x4_final_config_status_cl49_ltxsm_states_TX_HIG_START 64 16557 #define sc_x4_final_config_status_cl49_ltxsm_states_TX_LI 32 16558 #define sc_x4_final_config_status_cl49_ltxsm_states_TX_E 16 16559 #define sc_x4_final_config_status_cl49_ltxsm_states_TX_T 8 16560 #define sc_x4_final_config_status_cl49_ltxsm_states_TX_D 4 16561 #define sc_x4_final_config_status_cl49_ltxsm_states_TX_C 2 16562 #define sc_x4_final_config_status_cl49_ltxsm_states_TX_INIT 1 16563 16564 /**************************************************************************** 16565 * Enums: sc_x4_final_config_status_burst_error_mode 16566 */ 16567 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_11_BITS 0 16568 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_16_BITS 1 16569 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_17_BITS 2 16570 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_18_BITS 3 16571 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_19_BITS 4 16572 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_20_BITS 5 16573 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_21_BITS 6 16574 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_22_BITS 7 16575 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_23_BITS 8 16576 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_24_BITS 9 16577 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_25_BITS 10 16578 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_26_BITS 11 16579 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_27_BITS 12 16580 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_28_BITS 13 16581 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_29_BITS 14 16582 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_30_BITS 15 16583 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_31_BITS 16 16584 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_32_BITS 17 16585 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_33_BITS 18 16586 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_34_BITS 19 16587 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_35_BITS 20 16588 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_36_BITS 21 16589 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_37_BITS 22 16590 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_38_BITS 23 16591 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_39_BITS 24 16592 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_40_BITS 25 16593 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_41_BITS 26 16594 16595 /**************************************************************************** 16596 * Enums: sc_x4_final_config_status_bermon_state 16597 */ 16598 #define sc_x4_final_config_status_bermon_state_HI_BER 4 16599 #define sc_x4_final_config_status_bermon_state_GOOD_BER 3 16600 #define sc_x4_final_config_status_bermon_state_BER_TEST_SH 2 16601 #define sc_x4_final_config_status_bermon_state_START_TIMER 1 16602 #define sc_x4_final_config_status_bermon_state_BER_MT_INIT 0 16603 16604 /**************************************************************************** 16605 * Enums: sc_x4_final_config_status_rxsm_state_cl49 16606 */ 16607 #define sc_x4_final_config_status_rxsm_state_cl49_RX_HIG_END 128 16608 #define sc_x4_final_config_status_rxsm_state_cl49_RX_HIG_START 64 16609 #define sc_x4_final_config_status_rxsm_state_cl49_RX_LI 32 16610 #define sc_x4_final_config_status_rxsm_state_cl49_RX_E 16 16611 #define sc_x4_final_config_status_rxsm_state_cl49_RX_T 8 16612 #define sc_x4_final_config_status_rxsm_state_cl49_RX_D 4 16613 #define sc_x4_final_config_status_rxsm_state_cl49_RX_C 2 16614 #define sc_x4_final_config_status_rxsm_state_cl49_RX_INIT 1 16615 16616 /**************************************************************************** 16617 * Enums: sc_x4_final_config_status_r_type 16618 */ 16619 #define sc_x4_final_config_status_r_type_BAD_R_TYPE 15 16620 #define sc_x4_final_config_status_r_type_R_TYPE_B0 11 16621 #define sc_x4_final_config_status_r_type_R_TYPE_OB 10 16622 #define sc_x4_final_config_status_r_type_R_TYPE_B1 9 16623 #define sc_x4_final_config_status_r_type_R_TYPE_DB 8 16624 #define sc_x4_final_config_status_r_type_R_TYPE_FC 7 16625 #define sc_x4_final_config_status_r_type_R_TYPE_TB 6 16626 #define sc_x4_final_config_status_r_type_R_TYPE_LI 5 16627 #define sc_x4_final_config_status_r_type_R_TYPE_C 4 16628 #define sc_x4_final_config_status_r_type_R_TYPE_S 3 16629 #define sc_x4_final_config_status_r_type_R_TYPE_T 2 16630 #define sc_x4_final_config_status_r_type_R_TYPE_D 1 16631 #define sc_x4_final_config_status_r_type_R_TYPE_E 0 16632 16633 /**************************************************************************** 16634 * Enums: sc_x4_final_config_status_am_lock_state 16635 */ 16636 #define sc_x4_final_config_status_am_lock_state_INVALID_AM 512 16637 #define sc_x4_final_config_status_am_lock_state_GOOD_AM 256 16638 #define sc_x4_final_config_status_am_lock_state_COMP_AM 128 16639 #define sc_x4_final_config_status_am_lock_state_TIMER_2 64 16640 #define sc_x4_final_config_status_am_lock_state_AM_2_GOOD 32 16641 #define sc_x4_final_config_status_am_lock_state_COMP_2ND 16 16642 #define sc_x4_final_config_status_am_lock_state_TIMER_1 8 16643 #define sc_x4_final_config_status_am_lock_state_FIND_1ST 4 16644 #define sc_x4_final_config_status_am_lock_state_AM_RESET_CNT 2 16645 #define sc_x4_final_config_status_am_lock_state_AM_LOCK_INIT 1 16646 16647 /**************************************************************************** 16648 * Enums: sc_x4_final_config_status_msg_selector 16649 */ 16650 #define sc_x4_final_config_status_msg_selector_RESERVED 0 16651 #define sc_x4_final_config_status_msg_selector_VALUE_802p3 1 16652 #define sc_x4_final_config_status_msg_selector_VALUE_802p9 2 16653 #define sc_x4_final_config_status_msg_selector_VALUE_802p5 3 16654 #define sc_x4_final_config_status_msg_selector_VALUE_1394 4 16655 16656 /**************************************************************************** 16657 * Enums: sc_x4_final_config_status_synce_enum 16658 */ 16659 #define sc_x4_final_config_status_synce_enum_SYNCE_NO_DIV 0 16660 #define sc_x4_final_config_status_synce_enum_SYNCE_DIV_7 1 16661 #define sc_x4_final_config_status_synce_enum_SYNCE_DIV_11 2 16662 16663 /**************************************************************************** 16664 * Enums: sc_x4_final_config_status_synce_enum_stage0 16665 */ 16666 #define sc_x4_final_config_status_synce_enum_stage0_SYNCE_NO_DIV 0 16667 #define sc_x4_final_config_status_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 16668 #define sc_x4_final_config_status_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 16669 16670 /**************************************************************************** 16671 * Enums: sc_x4_final_config_status_cl91_sync_state 16672 */ 16673 #define sc_x4_final_config_status_cl91_sync_state_FIND_1ST 0 16674 #define sc_x4_final_config_status_cl91_sync_state_COUNT_NEXT 1 16675 #define sc_x4_final_config_status_cl91_sync_state_COMP_2ND 2 16676 #define sc_x4_final_config_status_cl91_sync_state_TWO_GOOD 3 16677 16678 /**************************************************************************** 16679 * Enums: sc_x4_final_config_status_cl91_algn_state 16680 */ 16681 #define sc_x4_final_config_status_cl91_algn_state_LOSS_OF_ALIGNMENT 0 16682 #define sc_x4_final_config_status_cl91_algn_state_DESKEW 1 16683 #define sc_x4_final_config_status_cl91_algn_state_DESKEW_FAIL 2 16684 #define sc_x4_final_config_status_cl91_algn_state_ALIGN_ACQUIRED 3 16685 #define sc_x4_final_config_status_cl91_algn_state_CW_GOOD 4 16686 #define sc_x4_final_config_status_cl91_algn_state_CW_BAD 5 16687 #define sc_x4_final_config_status_cl91_algn_state_THREE_BAD 6 16688 16689 /**************************************************************************** 16690 * Enums: sc_x4_final_config_status_fec_sel_override 16691 */ 16692 #define sc_x4_final_config_status_fec_sel_override_NO_OVERRIDE 0 16693 #define sc_x4_final_config_status_fec_sel_override_NO_FEC 1 16694 #define sc_x4_final_config_status_fec_sel_override_FEC_CL74 2 16695 #define sc_x4_final_config_status_fec_sel_override_FEC_CL91 3 16696 16697 /**************************************************************************** 16698 * Enums: sc_x4_final_config_status_cl91_blksync_mode 16699 */ 16700 #define sc_x4_final_config_status_cl91_blksync_mode_R_BLKSYNC_NO_CL91_FEC 0 16701 #define sc_x4_final_config_status_cl91_blksync_mode_R_BLKSYNC_CL91_QUAD_LANE_FEC 1 16702 #define sc_x4_final_config_status_cl91_blksync_mode_R_BLKSYNC_CL91_DUAL_LANE_FEC 2 16703 #define sc_x4_final_config_status_cl91_blksync_mode_R_BLKSYNC_CL91_SINGLE_LANE_FEC 3 16704 #define sc_x4_final_config_status_cl91_blksync_mode_R_BLKSYNC_CL91_FC_FEC 4 16705 16706 /**************************************************************************** 16707 * Enums: sc_x4_final_config_status_r_merge_mode 16708 */ 16709 #define sc_x4_final_config_status_r_merge_mode_R_MERGE_MODE_BYPASS 0 16710 #define sc_x4_final_config_status_r_merge_mode_R_MERGE_MODE_CL91_FC 1 16711 #define sc_x4_final_config_status_r_merge_mode_R_MERGE_MODE_CL91_SINGLE_LANE 2 16712 #define sc_x4_final_config_status_r_merge_mode_R_MERGE_MODE_CL91_DUAL_LANE 3 16713 #define sc_x4_final_config_status_r_merge_mode_R_MERGE_MODE_CL91_QUAD_LANE 4 16714 16715 /**************************************************************************** 16716 * Enums: sc_x4_final_config_status_r_tc_mode 16717 */ 16718 #define sc_x4_final_config_status_r_tc_mode_R_TC_MODE_SINGLE 0 16719 #define sc_x4_final_config_status_r_tc_mode_R_TC_MODE_DUAL 1 16720 #define sc_x4_final_config_status_r_tc_mode_R_TC_MODE_QUAD 2 16721 16722 /**************************************************************************** 16723 * Enums: sc_x4_final_config_status_r_tc_out_mode 16724 */ 16725 #define sc_x4_final_config_status_r_tc_out_mode_R_TC_OUT_MODE_SINGLE 0 16726 #define sc_x4_final_config_status_r_tc_out_mode_R_TC_OUT_MODE_DUAL 1 16727 #define sc_x4_final_config_status_r_tc_out_mode_R_TC_OUT_MODE_QUAD 2 16728 16729 /**************************************************************************** 16730 * Enums: sc_x4_final_config_status_cl91_fec_mode 16731 */ 16732 #define sc_x4_final_config_status_cl91_fec_mode_NO_CL91_FEC 0 16733 #define sc_x4_final_config_status_cl91_fec_mode_CL91_SINGLE_LANE_FC 1 16734 #define sc_x4_final_config_status_cl91_fec_mode_CL91_SINGLE_LANE_BRCM_PROP 2 16735 #define sc_x4_final_config_status_cl91_fec_mode_CL91_DUAL_LANE_BRCM_PROP 3 16736 #define sc_x4_final_config_status_cl91_fec_mode_CL91_QUAD_LANE 4 16737 #define sc_x4_final_config_status_cl91_fec_mode_IEEE_25G_CL91_SINGLE_LANE 5 16738 16739 /**************************************************************************** 16740 * Enums: sc_x4_final_config_status_am_spacing_mul 16741 */ 16742 #define sc_x4_final_config_status_am_spacing_mul_AM_SPACING_MUL_2 0 16743 #define sc_x4_final_config_status_am_spacing_mul_AM_SPACING_MUL_4 1 16744 #define sc_x4_final_config_status_am_spacing_mul_AM_SPACING_MUL_5 2 16745 #define sc_x4_final_config_status_am_spacing_mul_AM_SPACING_MUL_20 3 16746 16747 /**************************************************************************** 16748 * Enums: testshared0_cl36TxEEEStates_l 16749 */ 16750 #define testshared0_cl36TxEEEStates_l_TX_REFRESH 8 16751 #define testshared0_cl36TxEEEStates_l_TX_QUIET 4 16752 #define testshared0_cl36TxEEEStates_l_TX_SLEEP 2 16753 #define testshared0_cl36TxEEEStates_l_TX_ACTIVE 1 16754 16755 /**************************************************************************** 16756 * Enums: testshared0_cl36TxEEEStates_c 16757 */ 16758 #define testshared0_cl36TxEEEStates_c_TX_REFRESH 3 16759 #define testshared0_cl36TxEEEStates_c_TX_QUIET 2 16760 #define testshared0_cl36TxEEEStates_c_TX_SLEEP 1 16761 #define testshared0_cl36TxEEEStates_c_TX_ACTIVE 0 16762 16763 /**************************************************************************** 16764 * Enums: testshared0_cl49TxEEEStates_l 16765 */ 16766 #define testshared0_cl49TxEEEStates_l_SCR_RESET_2 64 16767 #define testshared0_cl49TxEEEStates_l_SCR_RESET_1 32 16768 #define testshared0_cl49TxEEEStates_l_TX_WAKE 16 16769 #define testshared0_cl49TxEEEStates_l_TX_REFRESH 8 16770 #define testshared0_cl49TxEEEStates_l_TX_QUIET 4 16771 #define testshared0_cl49TxEEEStates_l_TX_SLEEP 2 16772 #define testshared0_cl49TxEEEStates_l_TX_ACTIVE 1 16773 16774 /**************************************************************************** 16775 * Enums: testshared0_fec_req_enum 16776 */ 16777 #define testshared0_fec_req_enum_FEC_not_supported 0 16778 #define testshared0_fec_req_enum_FEC_supported_but_not_requested 1 16779 #define testshared0_fec_req_enum_invalid_setting 2 16780 #define testshared0_fec_req_enum_FEC_supported_and_requested 3 16781 16782 /**************************************************************************** 16783 * Enums: testshared0_cl73_pause_enum 16784 */ 16785 #define testshared0_cl73_pause_enum_No_PAUSE_ability 0 16786 #define testshared0_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 16787 #define testshared0_cl73_pause_enum_Symmetric_PAUSE_ability 1 16788 #define testshared0_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 16789 16790 /**************************************************************************** 16791 * Enums: testshared0_cl49TxEEEStates_c 16792 */ 16793 #define testshared0_cl49TxEEEStates_c_SCR_RESET_2 6 16794 #define testshared0_cl49TxEEEStates_c_SCR_RESET_1 5 16795 #define testshared0_cl49TxEEEStates_c_TX_WAKE 4 16796 #define testshared0_cl49TxEEEStates_c_TX_REFRESH 3 16797 #define testshared0_cl49TxEEEStates_c_TX_QUIET 2 16798 #define testshared0_cl49TxEEEStates_c_TX_SLEEP 1 16799 #define testshared0_cl49TxEEEStates_c_TX_ACTIVE 0 16800 16801 /**************************************************************************** 16802 * Enums: testshared0_cl36RxEEEStates_l 16803 */ 16804 #define testshared0_cl36RxEEEStates_l_RX_LINK_FAIL 32 16805 #define testshared0_cl36RxEEEStates_l_RX_WTF 16 16806 #define testshared0_cl36RxEEEStates_l_RX_WAKE 8 16807 #define testshared0_cl36RxEEEStates_l_RX_QUIET 4 16808 #define testshared0_cl36RxEEEStates_l_RX_SLEEP 2 16809 #define testshared0_cl36RxEEEStates_l_RX_ACTIVE 1 16810 16811 /**************************************************************************** 16812 * Enums: testshared0_cl36RxEEEStates_c 16813 */ 16814 #define testshared0_cl36RxEEEStates_c_RX_LINK_FAIL 5 16815 #define testshared0_cl36RxEEEStates_c_RX_WTF 4 16816 #define testshared0_cl36RxEEEStates_c_RX_WAKE 3 16817 #define testshared0_cl36RxEEEStates_c_RX_QUIET 2 16818 #define testshared0_cl36RxEEEStates_c_RX_SLEEP 1 16819 #define testshared0_cl36RxEEEStates_c_RX_ACTIVE 0 16820 16821 /**************************************************************************** 16822 * Enums: testshared0_cl49RxEEEStates_l 16823 */ 16824 #define testshared0_cl49RxEEEStates_l_RX_LINK_FAIL 32 16825 #define testshared0_cl49RxEEEStates_l_RX_WTF 16 16826 #define testshared0_cl49RxEEEStates_l_RX_WAKE 8 16827 #define testshared0_cl49RxEEEStates_l_RX_QUIET 4 16828 #define testshared0_cl49RxEEEStates_l_RX_SLEEP 2 16829 #define testshared0_cl49RxEEEStates_l_RX_ACTIVE 1 16830 16831 /**************************************************************************** 16832 * Enums: testshared0_cl49RxEEEStates_c 16833 */ 16834 #define testshared0_cl49RxEEEStates_c_RX_LINK_FAIL 5 16835 #define testshared0_cl49RxEEEStates_c_RX_WTF 4 16836 #define testshared0_cl49RxEEEStates_c_RX_WAKE 3 16837 #define testshared0_cl49RxEEEStates_c_RX_QUIET 2 16838 #define testshared0_cl49RxEEEStates_c_RX_SLEEP 1 16839 #define testshared0_cl49RxEEEStates_c_RX_ACTIVE 0 16840 16841 /**************************************************************************** 16842 * Enums: testshared0_cl48TxEEEStates_l 16843 */ 16844 #define testshared0_cl48TxEEEStates_l_TX_REFRESH 8 16845 #define testshared0_cl48TxEEEStates_l_TX_QUIET 4 16846 #define testshared0_cl48TxEEEStates_l_TX_SLEEP 2 16847 #define testshared0_cl48TxEEEStates_l_TX_ACTIVE 1 16848 16849 /**************************************************************************** 16850 * Enums: testshared0_cl48TxEEEStates_c 16851 */ 16852 #define testshared0_cl48TxEEEStates_c_TX_REFRESH 3 16853 #define testshared0_cl48TxEEEStates_c_TX_QUIET 2 16854 #define testshared0_cl48TxEEEStates_c_TX_SLEEP 1 16855 #define testshared0_cl48TxEEEStates_c_TX_ACTIVE 0 16856 16857 /**************************************************************************** 16858 * Enums: testshared0_cl48RxEEEStates_l 16859 */ 16860 #define testshared0_cl48RxEEEStates_l_RX_LINK_FAIL 32 16861 #define testshared0_cl48RxEEEStates_l_RX_WAKE 16 16862 #define testshared0_cl48RxEEEStates_l_RX_QUIET 8 16863 #define testshared0_cl48RxEEEStates_l_RX_DEACT 4 16864 #define testshared0_cl48RxEEEStates_l_RX_SLEEP 2 16865 #define testshared0_cl48RxEEEStates_l_RX_ACTIVE 1 16866 16867 /**************************************************************************** 16868 * Enums: testshared0_cl48RxEEEStates_c 16869 */ 16870 #define testshared0_cl48RxEEEStates_c_RX_LINK_FAIL 5 16871 #define testshared0_cl48RxEEEStates_c_RX_WAKE 4 16872 #define testshared0_cl48RxEEEStates_c_RX_QUIET 3 16873 #define testshared0_cl48RxEEEStates_c_RX_DEACT 2 16874 #define testshared0_cl48RxEEEStates_c_RX_SLEEP 1 16875 #define testshared0_cl48RxEEEStates_c_RX_ACTIVE 0 16876 16877 /**************************************************************************** 16878 * Enums: testshared0_IQP_Options 16879 */ 16880 #define testshared0_IQP_Options_i50uA 0 16881 #define testshared0_IQP_Options_i100uA 1 16882 #define testshared0_IQP_Options_i150uA 2 16883 #define testshared0_IQP_Options_i200uA 3 16884 #define testshared0_IQP_Options_i250uA 4 16885 #define testshared0_IQP_Options_i300uA 5 16886 #define testshared0_IQP_Options_i350uA 6 16887 #define testshared0_IQP_Options_i400uA 7 16888 #define testshared0_IQP_Options_i450uA 8 16889 #define testshared0_IQP_Options_i500uA 9 16890 #define testshared0_IQP_Options_i550uA 10 16891 #define testshared0_IQP_Options_i600uA 11 16892 #define testshared0_IQP_Options_i650uA 12 16893 #define testshared0_IQP_Options_i700uA 13 16894 #define testshared0_IQP_Options_i750uA 14 16895 #define testshared0_IQP_Options_i800uA 15 16896 16897 /**************************************************************************** 16898 * Enums: testshared0_IDriver_Options 16899 */ 16900 #define testshared0_IDriver_Options_v680mV 0 16901 #define testshared0_IDriver_Options_v730mV 1 16902 #define testshared0_IDriver_Options_v780mV 2 16903 #define testshared0_IDriver_Options_v830mV 3 16904 #define testshared0_IDriver_Options_v880mV 4 16905 #define testshared0_IDriver_Options_v930mV 5 16906 #define testshared0_IDriver_Options_v980mV 6 16907 #define testshared0_IDriver_Options_v1010mV 7 16908 #define testshared0_IDriver_Options_v1040mV 8 16909 #define testshared0_IDriver_Options_v1060mV 9 16910 #define testshared0_IDriver_Options_v1070mV 10 16911 #define testshared0_IDriver_Options_v1080mV 11 16912 #define testshared0_IDriver_Options_v1085mV 12 16913 #define testshared0_IDriver_Options_v1090mV 13 16914 #define testshared0_IDriver_Options_v1095mV 14 16915 #define testshared0_IDriver_Options_v1100mV 15 16916 16917 /**************************************************************************** 16918 * Enums: testshared0_operationModes 16919 */ 16920 #define testshared0_operationModes_XGXS 0 16921 #define testshared0_operationModes_XGXG_nCC 1 16922 #define testshared0_operationModes_Indlane_OS8 4 16923 #define testshared0_operationModes_IndLane_OS5 5 16924 #define testshared0_operationModes_PCI 7 16925 #define testshared0_operationModes_XGXS_nLQ 8 16926 #define testshared0_operationModes_XGXS_nLQnCC 9 16927 #define testshared0_operationModes_PBypass 10 16928 #define testshared0_operationModes_PBypass_nDSK 11 16929 #define testshared0_operationModes_ComboCoreMode 12 16930 #define testshared0_operationModes_Clocks_off 15 16931 16932 /**************************************************************************** 16933 * Enums: testshared0_actualSpeeds 16934 */ 16935 #define testshared0_actualSpeeds_dr_10M 0 16936 #define testshared0_actualSpeeds_dr_100M 1 16937 #define testshared0_actualSpeeds_dr_1G 2 16938 #define testshared0_actualSpeeds_dr_2p5G 3 16939 #define testshared0_actualSpeeds_dr_5G_X4 4 16940 #define testshared0_actualSpeeds_dr_6G_X4 5 16941 #define testshared0_actualSpeeds_dr_10G_HiG 6 16942 #define testshared0_actualSpeeds_dr_10G_CX4 7 16943 #define testshared0_actualSpeeds_dr_12G_HiG 8 16944 #define testshared0_actualSpeeds_dr_12p5G_X4 9 16945 #define testshared0_actualSpeeds_dr_13G_X4 10 16946 #define testshared0_actualSpeeds_dr_15G_X4 11 16947 #define testshared0_actualSpeeds_dr_16G_X4 12 16948 #define testshared0_actualSpeeds_dr_1G_KX 13 16949 #define testshared0_actualSpeeds_dr_10G_KX4 14 16950 #define testshared0_actualSpeeds_dr_10G_KR 15 16951 #define testshared0_actualSpeeds_dr_5G 16 16952 #define testshared0_actualSpeeds_dr_6p4G 17 16953 #define testshared0_actualSpeeds_dr_20G_X4 18 16954 #define testshared0_actualSpeeds_dr_21G_X4 19 16955 #define testshared0_actualSpeeds_dr_25G_X4 20 16956 #define testshared0_actualSpeeds_dr_10G_HiG_DXGXS 21 16957 #define testshared0_actualSpeeds_dr_10G_DXGXS 22 16958 #define testshared0_actualSpeeds_dr_10p5G_HiG_DXGXS 23 16959 #define testshared0_actualSpeeds_dr_10p5G_DXGXS 24 16960 #define testshared0_actualSpeeds_dr_12p773G_HiG_DXGXS 25 16961 #define testshared0_actualSpeeds_dr_12p773G_DXGXS 26 16962 #define testshared0_actualSpeeds_dr_10G_XFI 27 16963 #define testshared0_actualSpeeds_dr_40G 28 16964 #define testshared0_actualSpeeds_dr_20G_HiG_DXGXS 29 16965 #define testshared0_actualSpeeds_dr_20G_DXGXS 30 16966 #define testshared0_actualSpeeds_dr_10G_SFI 31 16967 #define testshared0_actualSpeeds_dr_31p5G 32 16968 #define testshared0_actualSpeeds_dr_32p7G 33 16969 #define testshared0_actualSpeeds_dr_20G_SCR 34 16970 #define testshared0_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 16971 #define testshared0_actualSpeeds_dr_10G_DXGXS_SCR 36 16972 #define testshared0_actualSpeeds_dr_12G_R2 37 16973 #define testshared0_actualSpeeds_dr_10G_X2 38 16974 #define testshared0_actualSpeeds_dr_40G_KR4 39 16975 #define testshared0_actualSpeeds_dr_40G_CR4 40 16976 #define testshared0_actualSpeeds_dr_100G_CR10 41 16977 #define testshared0_actualSpeeds_dr_15p75G_DXGXS 44 16978 #define testshared0_actualSpeeds_dr_20G_KR2 57 16979 #define testshared0_actualSpeeds_dr_20G_CR2 58 16980 16981 /**************************************************************************** 16982 * Enums: testshared0_actualSpeedsMisc1 16983 */ 16984 #define testshared0_actualSpeedsMisc1_dr_2500BRCM_X1 16 16985 #define testshared0_actualSpeedsMisc1_dr_5000BRCM_X4 17 16986 #define testshared0_actualSpeedsMisc1_dr_6000BRCM_X4 18 16987 #define testshared0_actualSpeedsMisc1_dr_10GHiGig_X4 19 16988 #define testshared0_actualSpeedsMisc1_dr_10GBASE_CX4 20 16989 #define testshared0_actualSpeedsMisc1_dr_12GHiGig_X4 21 16990 #define testshared0_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 16991 #define testshared0_actualSpeedsMisc1_dr_13GHiGig_X4 23 16992 #define testshared0_actualSpeedsMisc1_dr_15GHiGig_X4 24 16993 #define testshared0_actualSpeedsMisc1_dr_16GHiGig_X4 25 16994 #define testshared0_actualSpeedsMisc1_dr_5000BRCM_X1 26 16995 #define testshared0_actualSpeedsMisc1_dr_6363BRCM_X1 27 16996 #define testshared0_actualSpeedsMisc1_dr_20GHiGig_X4 28 16997 #define testshared0_actualSpeedsMisc1_dr_21GHiGig_X4 29 16998 #define testshared0_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 16999 #define testshared0_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 17000 17001 /**************************************************************************** 17002 * Enums: testshared0_IndLaneModes 17003 */ 17004 #define testshared0_IndLaneModes_SWSDR_div2 0 17005 #define testshared0_IndLaneModes_SWSDR_div1 1 17006 #define testshared0_IndLaneModes_DWSDR_div2 2 17007 #define testshared0_IndLaneModes_DWSDR_div1 3 17008 17009 /**************************************************************************** 17010 * Enums: testshared0_prbsSelect 17011 */ 17012 #define testshared0_prbsSelect_prbs7 0 17013 #define testshared0_prbsSelect_prbs15 1 17014 #define testshared0_prbsSelect_prbs23 2 17015 #define testshared0_prbsSelect_prbs31 3 17016 17017 /**************************************************************************** 17018 * Enums: testshared0_vcoDivider 17019 */ 17020 #define testshared0_vcoDivider_div32 0 17021 #define testshared0_vcoDivider_div36 1 17022 #define testshared0_vcoDivider_div40 2 17023 #define testshared0_vcoDivider_div42 3 17024 #define testshared0_vcoDivider_div48 4 17025 #define testshared0_vcoDivider_div50 5 17026 #define testshared0_vcoDivider_div52 6 17027 #define testshared0_vcoDivider_div54 7 17028 #define testshared0_vcoDivider_div60 8 17029 #define testshared0_vcoDivider_div64 9 17030 #define testshared0_vcoDivider_div66 10 17031 #define testshared0_vcoDivider_div68 11 17032 #define testshared0_vcoDivider_div70 12 17033 #define testshared0_vcoDivider_div80 13 17034 #define testshared0_vcoDivider_div92 14 17035 #define testshared0_vcoDivider_div100 15 17036 17037 /**************************************************************************** 17038 * Enums: testshared0_refClkSelect 17039 */ 17040 #define testshared0_refClkSelect_clk_25MHz 0 17041 #define testshared0_refClkSelect_clk_100MHz 1 17042 #define testshared0_refClkSelect_clk_125MHz 2 17043 #define testshared0_refClkSelect_clk_156p25MHz 3 17044 #define testshared0_refClkSelect_clk_187p5MHz 4 17045 #define testshared0_refClkSelect_clk_161p25Mhz 5 17046 #define testshared0_refClkSelect_clk_50Mhz 6 17047 #define testshared0_refClkSelect_clk_106p25Mhz 7 17048 17049 /**************************************************************************** 17050 * Enums: testshared0_aerMMDdevTypeSelect 17051 */ 17052 #define testshared0_aerMMDdevTypeSelect_combo_core 0 17053 #define testshared0_aerMMDdevTypeSelect_PMA_PMD 1 17054 #define testshared0_aerMMDdevTypeSelect_PCS 3 17055 #define testshared0_aerMMDdevTypeSelect_PHY 4 17056 #define testshared0_aerMMDdevTypeSelect_DTE 5 17057 #define testshared0_aerMMDdevTypeSelect_CL73_AN 7 17058 17059 /**************************************************************************** 17060 * Enums: testshared0_aerMMDportSelect 17061 */ 17062 #define testshared0_aerMMDportSelect_ln0 0 17063 #define testshared0_aerMMDportSelect_ln1 1 17064 #define testshared0_aerMMDportSelect_ln2 2 17065 #define testshared0_aerMMDportSelect_ln3 3 17066 #define testshared0_aerMMDportSelect_BCST_ln0_1_2_3 511 17067 #define testshared0_aerMMDportSelect_BCST_ln0_1 512 17068 #define testshared0_aerMMDportSelect_BCST_ln2_3 513 17069 17070 /**************************************************************************** 17071 * Enums: testshared0_firmwareModeSelect 17072 */ 17073 #define testshared0_firmwareModeSelect_DEFAULT 0 17074 #define testshared0_firmwareModeSelect_SFP_OPT_LR 1 17075 #define testshared0_firmwareModeSelect_SFP_DAC 2 17076 #define testshared0_firmwareModeSelect_XLAUI 3 17077 #define testshared0_firmwareModeSelect_LONG_CH_6G 4 17078 17079 /**************************************************************************** 17080 * Enums: testshared0_tempIdxSelect 17081 */ 17082 #define testshared0_tempIdxSelect_LTE__22p9C 15 17083 #define testshared0_tempIdxSelect_LTE__12p6C 14 17084 #define testshared0_tempIdxSelect_LTE__3p0C 13 17085 #define testshared0_tempIdxSelect_LTE_6p7C 12 17086 #define testshared0_tempIdxSelect_LTE_16p4C 11 17087 #define testshared0_tempIdxSelect_LTE_26p6C 10 17088 #define testshared0_tempIdxSelect_LTE_36p3C 9 17089 #define testshared0_tempIdxSelect_LTE_46p0C 8 17090 #define testshared0_tempIdxSelect_LTE_56p2C 7 17091 #define testshared0_tempIdxSelect_LTE_65p9C 6 17092 #define testshared0_tempIdxSelect_LTE_75p6C 5 17093 #define testshared0_tempIdxSelect_LTE_85p3C 4 17094 #define testshared0_tempIdxSelect_LTE_95p5C 3 17095 #define testshared0_tempIdxSelect_LTE_105p2C 2 17096 #define testshared0_tempIdxSelect_LTE_114p9C 1 17097 #define testshared0_tempIdxSelect_LTE_125p1C 0 17098 17099 /**************************************************************************** 17100 * Enums: testshared0_port_mode 17101 */ 17102 #define testshared0_port_mode_QUAD_PORT 0 17103 #define testshared0_port_mode_TRI_1_PORT 1 17104 #define testshared0_port_mode_TRI_2_PORT 2 17105 #define testshared0_port_mode_DUAL_PORT 3 17106 #define testshared0_port_mode_SINGLE_PORT 4 17107 17108 /**************************************************************************** 17109 * Enums: testshared0_rev_letter_enum 17110 */ 17111 #define testshared0_rev_letter_enum_REV_A 0 17112 #define testshared0_rev_letter_enum_REV_B 1 17113 #define testshared0_rev_letter_enum_REV_C 2 17114 #define testshared0_rev_letter_enum_REV_D 3 17115 17116 /**************************************************************************** 17117 * Enums: testshared0_rev_number_enum 17118 */ 17119 #define testshared0_rev_number_enum_REV_0 0 17120 #define testshared0_rev_number_enum_REV_1 1 17121 #define testshared0_rev_number_enum_REV_2 2 17122 #define testshared0_rev_number_enum_REV_3 3 17123 #define testshared0_rev_number_enum_REV_4 4 17124 #define testshared0_rev_number_enum_REV_5 5 17125 #define testshared0_rev_number_enum_REV_6 6 17126 #define testshared0_rev_number_enum_REV_7 7 17127 17128 /**************************************************************************** 17129 * Enums: testshared0_bonding_enum 17130 */ 17131 #define testshared0_bonding_enum_WIRE_BOND 0 17132 #define testshared0_bonding_enum_FLIP_CHIP 1 17133 17134 /**************************************************************************** 17135 * Enums: testshared0_tech_process 17136 */ 17137 #define testshared0_tech_process_PROCESS_90NM 0 17138 #define testshared0_tech_process_PROCESS_65NM 1 17139 #define testshared0_tech_process_PROCESS_40NM 2 17140 #define testshared0_tech_process_PROCESS_28NM 3 17141 #define testshared0_tech_process_PROCESS_16NM 4 17142 17143 /**************************************************************************** 17144 * Enums: testshared0_model_num 17145 */ 17146 #define testshared0_model_num_SERDES_CL73 0 17147 #define testshared0_model_num_XGXS_16G 1 17148 #define testshared0_model_num_HYPERCORE 2 17149 #define testshared0_model_num_HYPERLITE 3 17150 #define testshared0_model_num_PCIE_G2_PIPE 4 17151 #define testshared0_model_num_SERDES_1p25GBd 5 17152 #define testshared0_model_num_SATA2 6 17153 #define testshared0_model_num_QSGMII 7 17154 #define testshared0_model_num_XGXS10G 8 17155 #define testshared0_model_num_WARPCORE 9 17156 #define testshared0_model_num_XFICORE 10 17157 #define testshared0_model_num_RXFI 11 17158 #define testshared0_model_num_WARPLITE 12 17159 #define testshared0_model_num_PENTACORE 13 17160 #define testshared0_model_num_ESM 14 17161 #define testshared0_model_num_QUAD_SGMII 15 17162 #define testshared0_model_num_WARPCORE_3 16 17163 #define testshared0_model_num_TSC 17 17164 #define testshared0_model_num_TSC4E 18 17165 #define testshared0_model_num_TSC12E 19 17166 #define testshared0_model_num_TSC4F 20 17167 #define testshared0_model_num_TSC4F_GEN2 21 17168 #define testshared0_model_num_XGXS_CL73_90NM 29 17169 #define testshared0_model_num_SERDES_CL73_90NM 30 17170 #define testshared0_model_num_WARPCORE3 32 17171 #define testshared0_model_num_WARPCORE4_TSC 33 17172 #define testshared0_model_num_RXAUI 34 17173 17174 /**************************************************************************** 17175 * Enums: testshared0_payload 17176 */ 17177 #define testshared0_payload_REPEAT_2_BYTES 0 17178 #define testshared0_payload_RAMPING 1 17179 #define testshared0_payload_CL48_CRPAT 2 17180 #define testshared0_payload_CL48_CJPAT 3 17181 #define testshared0_payload_CL36_LONG_CRPAT 4 17182 #define testshared0_payload_CL36_SHORT_CRPAT 5 17183 17184 /**************************************************************************** 17185 * Enums: testshared0_sc 17186 */ 17187 #define testshared0_sc_S_10G_CR1 0 17188 #define testshared0_sc_S_10G_KR1 1 17189 #define testshared0_sc_S_10G_X1 2 17190 #define testshared0_sc_S_10G_HG2_CR1 4 17191 #define testshared0_sc_S_10G_HG2_KR1 5 17192 #define testshared0_sc_S_10G_HG2_X1 6 17193 #define testshared0_sc_S_20G_CR1 8 17194 #define testshared0_sc_S_20G_KR1 9 17195 #define testshared0_sc_S_20G_X1 10 17196 #define testshared0_sc_S_20G_HG2_CR1 12 17197 #define testshared0_sc_S_20G_HG2_KR1 13 17198 #define testshared0_sc_S_20G_HG2_X1 14 17199 #define testshared0_sc_S_25G_CR1 16 17200 #define testshared0_sc_S_25G_KR1 17 17201 #define testshared0_sc_S_25G_X1 18 17202 #define testshared0_sc_S_25G_HG2_CR1 20 17203 #define testshared0_sc_S_25G_HG2_KR1 21 17204 #define testshared0_sc_S_25G_HG2_X1 22 17205 #define testshared0_sc_S_20G_CR2 24 17206 #define testshared0_sc_S_20G_KR2 25 17207 #define testshared0_sc_S_20G_X2 26 17208 #define testshared0_sc_S_20G_HG2_CR2 28 17209 #define testshared0_sc_S_20G_HG2_KR2 29 17210 #define testshared0_sc_S_20G_HG2_X2 30 17211 #define testshared0_sc_S_40G_CR2 32 17212 #define testshared0_sc_S_40G_KR2 33 17213 #define testshared0_sc_S_40G_X2 34 17214 #define testshared0_sc_S_40G_HG2_CR2 36 17215 #define testshared0_sc_S_40G_HG2_KR2 37 17216 #define testshared0_sc_S_40G_HG2_X2 38 17217 #define testshared0_sc_S_40G_CR4 40 17218 #define testshared0_sc_S_40G_KR4 41 17219 #define testshared0_sc_S_40G_X4 42 17220 #define testshared0_sc_S_40G_HG2_CR4 44 17221 #define testshared0_sc_S_40G_HG2_KR4 45 17222 #define testshared0_sc_S_40G_HG2_X4 46 17223 #define testshared0_sc_S_50G_CR2 48 17224 #define testshared0_sc_S_50G_KR2 49 17225 #define testshared0_sc_S_50G_X2 50 17226 #define testshared0_sc_S_50G_HG2_CR2 52 17227 #define testshared0_sc_S_50G_HG2_KR2 53 17228 #define testshared0_sc_S_50G_HG2_X2 54 17229 #define testshared0_sc_S_50G_CR4 56 17230 #define testshared0_sc_S_50G_KR4 57 17231 #define testshared0_sc_S_50G_X4 58 17232 #define testshared0_sc_S_50G_HG2_CR4 60 17233 #define testshared0_sc_S_50G_HG2_KR4 61 17234 #define testshared0_sc_S_50G_HG2_X4 62 17235 #define testshared0_sc_S_100G_CR4 64 17236 #define testshared0_sc_S_100G_KR4 65 17237 #define testshared0_sc_S_100G_X4 66 17238 #define testshared0_sc_S_100G_HG2_CR4 68 17239 #define testshared0_sc_S_100G_HG2_KR4 69 17240 #define testshared0_sc_S_100G_HG2_X4 70 17241 #define testshared0_sc_S_CL73_20GVCO 72 17242 #define testshared0_sc_S_CL73_25GVCO 80 17243 #define testshared0_sc_S_CL36_20GVCO 88 17244 #define testshared0_sc_S_CL36_25GVCO 96 17245 #define testshared0_sc_S_25G_CR_IEEE 112 17246 #define testshared0_sc_S_25G_CRS_IEEE 113 17247 #define testshared0_sc_S_25G_KR_IEEE 114 17248 #define testshared0_sc_S_25G_KRS_IEEE 115 17249 17250 /**************************************************************************** 17251 * Enums: testshared0_t_fifo_modes 17252 */ 17253 #define testshared0_t_fifo_modes_T_FIFO_INSERT_NO_AM 0 17254 #define testshared0_t_fifo_modes_T_FIFO_INSERT_4_AM 1 17255 #define testshared0_t_fifo_modes_T_FIFO_INSERT_20_AM 2 17256 #define testshared0_t_fifo_modes_T_FIFO_INSERT_2_AM 3 17257 17258 /**************************************************************************** 17259 * Enums: testshared0_t_enc_modes 17260 */ 17261 #define testshared0_t_enc_modes_T_ENC_MODE_BYPASS 0 17262 #define testshared0_t_enc_modes_T_ENC_MODE_CL49 1 17263 #define testshared0_t_enc_modes_T_ENC_MODE_CL82 2 17264 17265 /**************************************************************************** 17266 * Enums: testshared0_btmx_mode 17267 */ 17268 #define testshared0_btmx_mode_BS_BTMX_MODE_1to1 0 17269 #define testshared0_btmx_mode_BS_BTMX_MODE_2to1 1 17270 #define testshared0_btmx_mode_BS_BTMX_MODE_5to1 2 17271 17272 /**************************************************************************** 17273 * Enums: testshared0_t_type_cl82 17274 */ 17275 #define testshared0_t_type_cl82_T_TYPE_B1 5 17276 #define testshared0_t_type_cl82_T_TYPE_C 4 17277 #define testshared0_t_type_cl82_T_TYPE_S 3 17278 #define testshared0_t_type_cl82_T_TYPE_T 2 17279 #define testshared0_t_type_cl82_T_TYPE_D 1 17280 #define testshared0_t_type_cl82_T_TYPE_E 0 17281 17282 /**************************************************************************** 17283 * Enums: testshared0_txsm_state_cl82 17284 */ 17285 #define testshared0_txsm_state_cl82_TX_HIG_END 6 17286 #define testshared0_txsm_state_cl82_TX_HIG_START 5 17287 #define testshared0_txsm_state_cl82_TX_E 4 17288 #define testshared0_txsm_state_cl82_TX_T 3 17289 #define testshared0_txsm_state_cl82_TX_D 2 17290 #define testshared0_txsm_state_cl82_TX_C 1 17291 #define testshared0_txsm_state_cl82_TX_INIT 0 17292 17293 /**************************************************************************** 17294 * Enums: testshared0_ltxsm_state_cl82 17295 */ 17296 #define testshared0_ltxsm_state_cl82_TX_HIG_END 64 17297 #define testshared0_ltxsm_state_cl82_TX_HIG_START 32 17298 #define testshared0_ltxsm_state_cl82_TX_E 16 17299 #define testshared0_ltxsm_state_cl82_TX_T 8 17300 #define testshared0_ltxsm_state_cl82_TX_D 4 17301 #define testshared0_ltxsm_state_cl82_TX_C 2 17302 #define testshared0_ltxsm_state_cl82_TX_INIT 1 17303 17304 /**************************************************************************** 17305 * Enums: testshared0_r_type_coded_cl82 17306 */ 17307 #define testshared0_r_type_coded_cl82_R_TYPE_B1 32 17308 #define testshared0_r_type_coded_cl82_R_TYPE_C 16 17309 #define testshared0_r_type_coded_cl82_R_TYPE_S 8 17310 #define testshared0_r_type_coded_cl82_R_TYPE_T 4 17311 #define testshared0_r_type_coded_cl82_R_TYPE_D 2 17312 #define testshared0_r_type_coded_cl82_R_TYPE_E 1 17313 17314 /**************************************************************************** 17315 * Enums: testshared0_rxsm_state_cl82 17316 */ 17317 #define testshared0_rxsm_state_cl82_RX_HIG_END 64 17318 #define testshared0_rxsm_state_cl82_RX_HIG_START 32 17319 #define testshared0_rxsm_state_cl82_RX_E 16 17320 #define testshared0_rxsm_state_cl82_RX_T 8 17321 #define testshared0_rxsm_state_cl82_RX_D 4 17322 #define testshared0_rxsm_state_cl82_RX_C 2 17323 #define testshared0_rxsm_state_cl82_RX_INIT 1 17324 17325 /**************************************************************************** 17326 * Enums: testshared0_deskew_state 17327 */ 17328 #define testshared0_deskew_state_ALIGN_ACQUIRED 2 17329 #define testshared0_deskew_state_LOSS_OF_ALIGNMENT 1 17330 17331 /**************************************************************************** 17332 * Enums: testshared0_os_mode_enum 17333 */ 17334 #define testshared0_os_mode_enum_OS_MODE_1 0 17335 #define testshared0_os_mode_enum_OS_MODE_2 1 17336 #define testshared0_os_mode_enum_OS_MODE_4 2 17337 #define testshared0_os_mode_enum_OS_MODE_16p5 8 17338 #define testshared0_os_mode_enum_OS_MODE_20p625 12 17339 17340 /**************************************************************************** 17341 * Enums: testshared0_scr_modes 17342 */ 17343 #define testshared0_scr_modes_T_SCR_MODE_BYPASS 0 17344 #define testshared0_scr_modes_T_SCR_MODE_CL49 1 17345 #define testshared0_scr_modes_T_SCR_MODE_40G_2_LANE 2 17346 #define testshared0_scr_modes_T_SCR_MODE_100G 3 17347 #define testshared0_scr_modes_T_SCR_MODE_20G 4 17348 #define testshared0_scr_modes_T_SCR_MODE_40G_4_LANE 5 17349 17350 /**************************************************************************** 17351 * Enums: testshared0_descr_modes 17352 */ 17353 #define testshared0_descr_modes_R_DESCR_MODE_BYPASS 0 17354 #define testshared0_descr_modes_R_DESCR_MODE_CL49 1 17355 #define testshared0_descr_modes_R_DESCR_MODE_CL82 2 17356 17357 /**************************************************************************** 17358 * Enums: testshared0_r_dec_tl_mode 17359 */ 17360 #define testshared0_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 17361 #define testshared0_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 17362 #define testshared0_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 17363 17364 /**************************************************************************** 17365 * Enums: testshared0_r_dec_fsm_mode 17366 */ 17367 #define testshared0_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 17368 #define testshared0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 17369 #define testshared0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 17370 17371 /**************************************************************************** 17372 * Enums: testshared0_r_deskew_mode 17373 */ 17374 #define testshared0_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 17375 #define testshared0_r_deskew_mode_R_DESKEW_MODE_20G 1 17376 #define testshared0_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 17377 #define testshared0_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 17378 #define testshared0_r_deskew_mode_R_DESKEW_MODE_100G 4 17379 #define testshared0_r_deskew_mode_R_DESKEW_MODE_CL49 5 17380 #define testshared0_r_deskew_mode_R_DESKEW_MODE_CL91_QUAD 6 17381 #define testshared0_r_deskew_mode_R_DESKEW_MODE_CL91_SINGLE_BRCM 7 17382 #define testshared0_r_deskew_mode_R_DESKEW_MODE_CL91_DUAL_BRCM 8 17383 #define testshared0_r_deskew_mode_R_DESKEW_MODE_CL91_FC 9 17384 17385 /**************************************************************************** 17386 * Enums: testshared0_bs_dist_modes 17387 */ 17388 #define testshared0_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 17389 #define testshared0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 17390 #define testshared0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 17391 #define testshared0_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 17392 17393 /**************************************************************************** 17394 * Enums: testshared0_cl49_t_type 17395 */ 17396 #define testshared0_cl49_t_type_BAD_T_TYPE 15 17397 #define testshared0_cl49_t_type_T_TYPE_B0 11 17398 #define testshared0_cl49_t_type_T_TYPE_OB 10 17399 #define testshared0_cl49_t_type_T_TYPE_B1 9 17400 #define testshared0_cl49_t_type_T_TYPE_DB 8 17401 #define testshared0_cl49_t_type_T_TYPE_FC 7 17402 #define testshared0_cl49_t_type_T_TYPE_TB 6 17403 #define testshared0_cl49_t_type_T_TYPE_LI 5 17404 #define testshared0_cl49_t_type_T_TYPE_C 4 17405 #define testshared0_cl49_t_type_T_TYPE_S 3 17406 #define testshared0_cl49_t_type_T_TYPE_T 2 17407 #define testshared0_cl49_t_type_T_TYPE_D 1 17408 #define testshared0_cl49_t_type_T_TYPE_E 0 17409 17410 /**************************************************************************** 17411 * Enums: testshared0_cl49_txsm_states 17412 */ 17413 #define testshared0_cl49_txsm_states_TX_HIG_END 7 17414 #define testshared0_cl49_txsm_states_TX_HIG_START 6 17415 #define testshared0_cl49_txsm_states_TX_LI 5 17416 #define testshared0_cl49_txsm_states_TX_E 4 17417 #define testshared0_cl49_txsm_states_TX_T 3 17418 #define testshared0_cl49_txsm_states_TX_D 2 17419 #define testshared0_cl49_txsm_states_TX_C 1 17420 #define testshared0_cl49_txsm_states_TX_INIT 0 17421 17422 /**************************************************************************** 17423 * Enums: testshared0_cl49_ltxsm_states 17424 */ 17425 #define testshared0_cl49_ltxsm_states_TX_HIG_END 128 17426 #define testshared0_cl49_ltxsm_states_TX_HIG_START 64 17427 #define testshared0_cl49_ltxsm_states_TX_LI 32 17428 #define testshared0_cl49_ltxsm_states_TX_E 16 17429 #define testshared0_cl49_ltxsm_states_TX_T 8 17430 #define testshared0_cl49_ltxsm_states_TX_D 4 17431 #define testshared0_cl49_ltxsm_states_TX_C 2 17432 #define testshared0_cl49_ltxsm_states_TX_INIT 1 17433 17434 /**************************************************************************** 17435 * Enums: testshared0_burst_error_mode 17436 */ 17437 #define testshared0_burst_error_mode_BURST_ERROR_11_BITS 0 17438 #define testshared0_burst_error_mode_BURST_ERROR_16_BITS 1 17439 #define testshared0_burst_error_mode_BURST_ERROR_17_BITS 2 17440 #define testshared0_burst_error_mode_BURST_ERROR_18_BITS 3 17441 #define testshared0_burst_error_mode_BURST_ERROR_19_BITS 4 17442 #define testshared0_burst_error_mode_BURST_ERROR_20_BITS 5 17443 #define testshared0_burst_error_mode_BURST_ERROR_21_BITS 6 17444 #define testshared0_burst_error_mode_BURST_ERROR_22_BITS 7 17445 #define testshared0_burst_error_mode_BURST_ERROR_23_BITS 8 17446 #define testshared0_burst_error_mode_BURST_ERROR_24_BITS 9 17447 #define testshared0_burst_error_mode_BURST_ERROR_25_BITS 10 17448 #define testshared0_burst_error_mode_BURST_ERROR_26_BITS 11 17449 #define testshared0_burst_error_mode_BURST_ERROR_27_BITS 12 17450 #define testshared0_burst_error_mode_BURST_ERROR_28_BITS 13 17451 #define testshared0_burst_error_mode_BURST_ERROR_29_BITS 14 17452 #define testshared0_burst_error_mode_BURST_ERROR_30_BITS 15 17453 #define testshared0_burst_error_mode_BURST_ERROR_31_BITS 16 17454 #define testshared0_burst_error_mode_BURST_ERROR_32_BITS 17 17455 #define testshared0_burst_error_mode_BURST_ERROR_33_BITS 18 17456 #define testshared0_burst_error_mode_BURST_ERROR_34_BITS 19 17457 #define testshared0_burst_error_mode_BURST_ERROR_35_BITS 20 17458 #define testshared0_burst_error_mode_BURST_ERROR_36_BITS 21 17459 #define testshared0_burst_error_mode_BURST_ERROR_37_BITS 22 17460 #define testshared0_burst_error_mode_BURST_ERROR_38_BITS 23 17461 #define testshared0_burst_error_mode_BURST_ERROR_39_BITS 24 17462 #define testshared0_burst_error_mode_BURST_ERROR_40_BITS 25 17463 #define testshared0_burst_error_mode_BURST_ERROR_41_BITS 26 17464 17465 /**************************************************************************** 17466 * Enums: testshared0_bermon_state 17467 */ 17468 #define testshared0_bermon_state_HI_BER 4 17469 #define testshared0_bermon_state_GOOD_BER 3 17470 #define testshared0_bermon_state_BER_TEST_SH 2 17471 #define testshared0_bermon_state_START_TIMER 1 17472 #define testshared0_bermon_state_BER_MT_INIT 0 17473 17474 /**************************************************************************** 17475 * Enums: testshared0_rxsm_state_cl49 17476 */ 17477 #define testshared0_rxsm_state_cl49_RX_HIG_END 128 17478 #define testshared0_rxsm_state_cl49_RX_HIG_START 64 17479 #define testshared0_rxsm_state_cl49_RX_LI 32 17480 #define testshared0_rxsm_state_cl49_RX_E 16 17481 #define testshared0_rxsm_state_cl49_RX_T 8 17482 #define testshared0_rxsm_state_cl49_RX_D 4 17483 #define testshared0_rxsm_state_cl49_RX_C 2 17484 #define testshared0_rxsm_state_cl49_RX_INIT 1 17485 17486 /**************************************************************************** 17487 * Enums: testshared0_r_type 17488 */ 17489 #define testshared0_r_type_BAD_R_TYPE 15 17490 #define testshared0_r_type_R_TYPE_B0 11 17491 #define testshared0_r_type_R_TYPE_OB 10 17492 #define testshared0_r_type_R_TYPE_B1 9 17493 #define testshared0_r_type_R_TYPE_DB 8 17494 #define testshared0_r_type_R_TYPE_FC 7 17495 #define testshared0_r_type_R_TYPE_TB 6 17496 #define testshared0_r_type_R_TYPE_LI 5 17497 #define testshared0_r_type_R_TYPE_C 4 17498 #define testshared0_r_type_R_TYPE_S 3 17499 #define testshared0_r_type_R_TYPE_T 2 17500 #define testshared0_r_type_R_TYPE_D 1 17501 #define testshared0_r_type_R_TYPE_E 0 17502 17503 /**************************************************************************** 17504 * Enums: testshared0_am_lock_state 17505 */ 17506 #define testshared0_am_lock_state_INVALID_AM 512 17507 #define testshared0_am_lock_state_GOOD_AM 256 17508 #define testshared0_am_lock_state_COMP_AM 128 17509 #define testshared0_am_lock_state_TIMER_2 64 17510 #define testshared0_am_lock_state_AM_2_GOOD 32 17511 #define testshared0_am_lock_state_COMP_2ND 16 17512 #define testshared0_am_lock_state_TIMER_1 8 17513 #define testshared0_am_lock_state_FIND_1ST 4 17514 #define testshared0_am_lock_state_AM_RESET_CNT 2 17515 #define testshared0_am_lock_state_AM_LOCK_INIT 1 17516 17517 /**************************************************************************** 17518 * Enums: testshared0_msg_selector 17519 */ 17520 #define testshared0_msg_selector_RESERVED 0 17521 #define testshared0_msg_selector_VALUE_802p3 1 17522 #define testshared0_msg_selector_VALUE_802p9 2 17523 #define testshared0_msg_selector_VALUE_802p5 3 17524 #define testshared0_msg_selector_VALUE_1394 4 17525 17526 /**************************************************************************** 17527 * Enums: testshared0_synce_enum 17528 */ 17529 #define testshared0_synce_enum_SYNCE_NO_DIV 0 17530 #define testshared0_synce_enum_SYNCE_DIV_7 1 17531 #define testshared0_synce_enum_SYNCE_DIV_11 2 17532 17533 /**************************************************************************** 17534 * Enums: testshared0_synce_enum_stage0 17535 */ 17536 #define testshared0_synce_enum_stage0_SYNCE_NO_DIV 0 17537 #define testshared0_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 17538 #define testshared0_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 17539 17540 /**************************************************************************** 17541 * Enums: testshared0_cl91_sync_state 17542 */ 17543 #define testshared0_cl91_sync_state_FIND_1ST 0 17544 #define testshared0_cl91_sync_state_COUNT_NEXT 1 17545 #define testshared0_cl91_sync_state_COMP_2ND 2 17546 #define testshared0_cl91_sync_state_TWO_GOOD 3 17547 17548 /**************************************************************************** 17549 * Enums: testshared0_cl91_algn_state 17550 */ 17551 #define testshared0_cl91_algn_state_LOSS_OF_ALIGNMENT 0 17552 #define testshared0_cl91_algn_state_DESKEW 1 17553 #define testshared0_cl91_algn_state_DESKEW_FAIL 2 17554 #define testshared0_cl91_algn_state_ALIGN_ACQUIRED 3 17555 #define testshared0_cl91_algn_state_CW_GOOD 4 17556 #define testshared0_cl91_algn_state_CW_BAD 5 17557 #define testshared0_cl91_algn_state_THREE_BAD 6 17558 17559 /**************************************************************************** 17560 * Enums: testshared0_fec_sel_override 17561 */ 17562 #define testshared0_fec_sel_override_NO_OVERRIDE 0 17563 #define testshared0_fec_sel_override_NO_FEC 1 17564 #define testshared0_fec_sel_override_FEC_CL74 2 17565 #define testshared0_fec_sel_override_FEC_CL91 3 17566 17567 /**************************************************************************** 17568 * Enums: testshared0_cl91_blksync_mode 17569 */ 17570 #define testshared0_cl91_blksync_mode_R_BLKSYNC_NO_CL91_FEC 0 17571 #define testshared0_cl91_blksync_mode_R_BLKSYNC_CL91_QUAD_LANE_FEC 1 17572 #define testshared0_cl91_blksync_mode_R_BLKSYNC_CL91_DUAL_LANE_FEC 2 17573 #define testshared0_cl91_blksync_mode_R_BLKSYNC_CL91_SINGLE_LANE_FEC 3 17574 #define testshared0_cl91_blksync_mode_R_BLKSYNC_CL91_FC_FEC 4 17575 17576 /**************************************************************************** 17577 * Enums: testshared0_r_merge_mode 17578 */ 17579 #define testshared0_r_merge_mode_R_MERGE_MODE_BYPASS 0 17580 #define testshared0_r_merge_mode_R_MERGE_MODE_CL91_FC 1 17581 #define testshared0_r_merge_mode_R_MERGE_MODE_CL91_SINGLE_LANE 2 17582 #define testshared0_r_merge_mode_R_MERGE_MODE_CL91_DUAL_LANE 3 17583 #define testshared0_r_merge_mode_R_MERGE_MODE_CL91_QUAD_LANE 4 17584 17585 /**************************************************************************** 17586 * Enums: testshared0_r_tc_mode 17587 */ 17588 #define testshared0_r_tc_mode_R_TC_MODE_SINGLE 0 17589 #define testshared0_r_tc_mode_R_TC_MODE_DUAL 1 17590 #define testshared0_r_tc_mode_R_TC_MODE_QUAD 2 17591 17592 /**************************************************************************** 17593 * Enums: testshared0_r_tc_out_mode 17594 */ 17595 #define testshared0_r_tc_out_mode_R_TC_OUT_MODE_SINGLE 0 17596 #define testshared0_r_tc_out_mode_R_TC_OUT_MODE_DUAL 1 17597 #define testshared0_r_tc_out_mode_R_TC_OUT_MODE_QUAD 2 17598 17599 /**************************************************************************** 17600 * Enums: testshared0_cl91_fec_mode 17601 */ 17602 #define testshared0_cl91_fec_mode_NO_CL91_FEC 0 17603 #define testshared0_cl91_fec_mode_CL91_SINGLE_LANE_FC 1 17604 #define testshared0_cl91_fec_mode_CL91_SINGLE_LANE_BRCM_PROP 2 17605 #define testshared0_cl91_fec_mode_CL91_DUAL_LANE_BRCM_PROP 3 17606 #define testshared0_cl91_fec_mode_CL91_QUAD_LANE 4 17607 #define testshared0_cl91_fec_mode_IEEE_25G_CL91_SINGLE_LANE 5 17608 17609 /**************************************************************************** 17610 * Enums: testshared0_am_spacing_mul 17611 */ 17612 #define testshared0_am_spacing_mul_AM_SPACING_MUL_2 0 17613 #define testshared0_am_spacing_mul_AM_SPACING_MUL_4 1 17614 #define testshared0_am_spacing_mul_AM_SPACING_MUL_5 2 17615 #define testshared0_am_spacing_mul_AM_SPACING_MUL_20 3 17616 17617 /**************************************************************************** 17618 * Enums: tx_x2_control0_cl36TxEEEStates_l 17619 */ 17620 #define tx_x2_control0_cl36TxEEEStates_l_TX_REFRESH 8 17621 #define tx_x2_control0_cl36TxEEEStates_l_TX_QUIET 4 17622 #define tx_x2_control0_cl36TxEEEStates_l_TX_SLEEP 2 17623 #define tx_x2_control0_cl36TxEEEStates_l_TX_ACTIVE 1 17624 17625 /**************************************************************************** 17626 * Enums: tx_x2_control0_cl36TxEEEStates_c 17627 */ 17628 #define tx_x2_control0_cl36TxEEEStates_c_TX_REFRESH 3 17629 #define tx_x2_control0_cl36TxEEEStates_c_TX_QUIET 2 17630 #define tx_x2_control0_cl36TxEEEStates_c_TX_SLEEP 1 17631 #define tx_x2_control0_cl36TxEEEStates_c_TX_ACTIVE 0 17632 17633 /**************************************************************************** 17634 * Enums: tx_x2_control0_cl49TxEEEStates_l 17635 */ 17636 #define tx_x2_control0_cl49TxEEEStates_l_SCR_RESET_2 64 17637 #define tx_x2_control0_cl49TxEEEStates_l_SCR_RESET_1 32 17638 #define tx_x2_control0_cl49TxEEEStates_l_TX_WAKE 16 17639 #define tx_x2_control0_cl49TxEEEStates_l_TX_REFRESH 8 17640 #define tx_x2_control0_cl49TxEEEStates_l_TX_QUIET 4 17641 #define tx_x2_control0_cl49TxEEEStates_l_TX_SLEEP 2 17642 #define tx_x2_control0_cl49TxEEEStates_l_TX_ACTIVE 1 17643 17644 /**************************************************************************** 17645 * Enums: tx_x2_control0_fec_req_enum 17646 */ 17647 #define tx_x2_control0_fec_req_enum_FEC_not_supported 0 17648 #define tx_x2_control0_fec_req_enum_FEC_supported_but_not_requested 1 17649 #define tx_x2_control0_fec_req_enum_invalid_setting 2 17650 #define tx_x2_control0_fec_req_enum_FEC_supported_and_requested 3 17651 17652 /**************************************************************************** 17653 * Enums: tx_x2_control0_cl73_pause_enum 17654 */ 17655 #define tx_x2_control0_cl73_pause_enum_No_PAUSE_ability 0 17656 #define tx_x2_control0_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 17657 #define tx_x2_control0_cl73_pause_enum_Symmetric_PAUSE_ability 1 17658 #define tx_x2_control0_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 17659 17660 /**************************************************************************** 17661 * Enums: tx_x2_control0_cl49TxEEEStates_c 17662 */ 17663 #define tx_x2_control0_cl49TxEEEStates_c_SCR_RESET_2 6 17664 #define tx_x2_control0_cl49TxEEEStates_c_SCR_RESET_1 5 17665 #define tx_x2_control0_cl49TxEEEStates_c_TX_WAKE 4 17666 #define tx_x2_control0_cl49TxEEEStates_c_TX_REFRESH 3 17667 #define tx_x2_control0_cl49TxEEEStates_c_TX_QUIET 2 17668 #define tx_x2_control0_cl49TxEEEStates_c_TX_SLEEP 1 17669 #define tx_x2_control0_cl49TxEEEStates_c_TX_ACTIVE 0 17670 17671 /**************************************************************************** 17672 * Enums: tx_x2_control0_cl36RxEEEStates_l 17673 */ 17674 #define tx_x2_control0_cl36RxEEEStates_l_RX_LINK_FAIL 32 17675 #define tx_x2_control0_cl36RxEEEStates_l_RX_WTF 16 17676 #define tx_x2_control0_cl36RxEEEStates_l_RX_WAKE 8 17677 #define tx_x2_control0_cl36RxEEEStates_l_RX_QUIET 4 17678 #define tx_x2_control0_cl36RxEEEStates_l_RX_SLEEP 2 17679 #define tx_x2_control0_cl36RxEEEStates_l_RX_ACTIVE 1 17680 17681 /**************************************************************************** 17682 * Enums: tx_x2_control0_cl36RxEEEStates_c 17683 */ 17684 #define tx_x2_control0_cl36RxEEEStates_c_RX_LINK_FAIL 5 17685 #define tx_x2_control0_cl36RxEEEStates_c_RX_WTF 4 17686 #define tx_x2_control0_cl36RxEEEStates_c_RX_WAKE 3 17687 #define tx_x2_control0_cl36RxEEEStates_c_RX_QUIET 2 17688 #define tx_x2_control0_cl36RxEEEStates_c_RX_SLEEP 1 17689 #define tx_x2_control0_cl36RxEEEStates_c_RX_ACTIVE 0 17690 17691 /**************************************************************************** 17692 * Enums: tx_x2_control0_cl49RxEEEStates_l 17693 */ 17694 #define tx_x2_control0_cl49RxEEEStates_l_RX_LINK_FAIL 32 17695 #define tx_x2_control0_cl49RxEEEStates_l_RX_WTF 16 17696 #define tx_x2_control0_cl49RxEEEStates_l_RX_WAKE 8 17697 #define tx_x2_control0_cl49RxEEEStates_l_RX_QUIET 4 17698 #define tx_x2_control0_cl49RxEEEStates_l_RX_SLEEP 2 17699 #define tx_x2_control0_cl49RxEEEStates_l_RX_ACTIVE 1 17700 17701 /**************************************************************************** 17702 * Enums: tx_x2_control0_cl49RxEEEStates_c 17703 */ 17704 #define tx_x2_control0_cl49RxEEEStates_c_RX_LINK_FAIL 5 17705 #define tx_x2_control0_cl49RxEEEStates_c_RX_WTF 4 17706 #define tx_x2_control0_cl49RxEEEStates_c_RX_WAKE 3 17707 #define tx_x2_control0_cl49RxEEEStates_c_RX_QUIET 2 17708 #define tx_x2_control0_cl49RxEEEStates_c_RX_SLEEP 1 17709 #define tx_x2_control0_cl49RxEEEStates_c_RX_ACTIVE 0 17710 17711 /**************************************************************************** 17712 * Enums: tx_x2_control0_cl48TxEEEStates_l 17713 */ 17714 #define tx_x2_control0_cl48TxEEEStates_l_TX_REFRESH 8 17715 #define tx_x2_control0_cl48TxEEEStates_l_TX_QUIET 4 17716 #define tx_x2_control0_cl48TxEEEStates_l_TX_SLEEP 2 17717 #define tx_x2_control0_cl48TxEEEStates_l_TX_ACTIVE 1 17718 17719 /**************************************************************************** 17720 * Enums: tx_x2_control0_cl48TxEEEStates_c 17721 */ 17722 #define tx_x2_control0_cl48TxEEEStates_c_TX_REFRESH 3 17723 #define tx_x2_control0_cl48TxEEEStates_c_TX_QUIET 2 17724 #define tx_x2_control0_cl48TxEEEStates_c_TX_SLEEP 1 17725 #define tx_x2_control0_cl48TxEEEStates_c_TX_ACTIVE 0 17726 17727 /**************************************************************************** 17728 * Enums: tx_x2_control0_cl48RxEEEStates_l 17729 */ 17730 #define tx_x2_control0_cl48RxEEEStates_l_RX_LINK_FAIL 32 17731 #define tx_x2_control0_cl48RxEEEStates_l_RX_WAKE 16 17732 #define tx_x2_control0_cl48RxEEEStates_l_RX_QUIET 8 17733 #define tx_x2_control0_cl48RxEEEStates_l_RX_DEACT 4 17734 #define tx_x2_control0_cl48RxEEEStates_l_RX_SLEEP 2 17735 #define tx_x2_control0_cl48RxEEEStates_l_RX_ACTIVE 1 17736 17737 /**************************************************************************** 17738 * Enums: tx_x2_control0_cl48RxEEEStates_c 17739 */ 17740 #define tx_x2_control0_cl48RxEEEStates_c_RX_LINK_FAIL 5 17741 #define tx_x2_control0_cl48RxEEEStates_c_RX_WAKE 4 17742 #define tx_x2_control0_cl48RxEEEStates_c_RX_QUIET 3 17743 #define tx_x2_control0_cl48RxEEEStates_c_RX_DEACT 2 17744 #define tx_x2_control0_cl48RxEEEStates_c_RX_SLEEP 1 17745 #define tx_x2_control0_cl48RxEEEStates_c_RX_ACTIVE 0 17746 17747 /**************************************************************************** 17748 * Enums: tx_x2_control0_IQP_Options 17749 */ 17750 #define tx_x2_control0_IQP_Options_i50uA 0 17751 #define tx_x2_control0_IQP_Options_i100uA 1 17752 #define tx_x2_control0_IQP_Options_i150uA 2 17753 #define tx_x2_control0_IQP_Options_i200uA 3 17754 #define tx_x2_control0_IQP_Options_i250uA 4 17755 #define tx_x2_control0_IQP_Options_i300uA 5 17756 #define tx_x2_control0_IQP_Options_i350uA 6 17757 #define tx_x2_control0_IQP_Options_i400uA 7 17758 #define tx_x2_control0_IQP_Options_i450uA 8 17759 #define tx_x2_control0_IQP_Options_i500uA 9 17760 #define tx_x2_control0_IQP_Options_i550uA 10 17761 #define tx_x2_control0_IQP_Options_i600uA 11 17762 #define tx_x2_control0_IQP_Options_i650uA 12 17763 #define tx_x2_control0_IQP_Options_i700uA 13 17764 #define tx_x2_control0_IQP_Options_i750uA 14 17765 #define tx_x2_control0_IQP_Options_i800uA 15 17766 17767 /**************************************************************************** 17768 * Enums: tx_x2_control0_IDriver_Options 17769 */ 17770 #define tx_x2_control0_IDriver_Options_v680mV 0 17771 #define tx_x2_control0_IDriver_Options_v730mV 1 17772 #define tx_x2_control0_IDriver_Options_v780mV 2 17773 #define tx_x2_control0_IDriver_Options_v830mV 3 17774 #define tx_x2_control0_IDriver_Options_v880mV 4 17775 #define tx_x2_control0_IDriver_Options_v930mV 5 17776 #define tx_x2_control0_IDriver_Options_v980mV 6 17777 #define tx_x2_control0_IDriver_Options_v1010mV 7 17778 #define tx_x2_control0_IDriver_Options_v1040mV 8 17779 #define tx_x2_control0_IDriver_Options_v1060mV 9 17780 #define tx_x2_control0_IDriver_Options_v1070mV 10 17781 #define tx_x2_control0_IDriver_Options_v1080mV 11 17782 #define tx_x2_control0_IDriver_Options_v1085mV 12 17783 #define tx_x2_control0_IDriver_Options_v1090mV 13 17784 #define tx_x2_control0_IDriver_Options_v1095mV 14 17785 #define tx_x2_control0_IDriver_Options_v1100mV 15 17786 17787 /**************************************************************************** 17788 * Enums: tx_x2_control0_operationModes 17789 */ 17790 #define tx_x2_control0_operationModes_XGXS 0 17791 #define tx_x2_control0_operationModes_XGXG_nCC 1 17792 #define tx_x2_control0_operationModes_Indlane_OS8 4 17793 #define tx_x2_control0_operationModes_IndLane_OS5 5 17794 #define tx_x2_control0_operationModes_PCI 7 17795 #define tx_x2_control0_operationModes_XGXS_nLQ 8 17796 #define tx_x2_control0_operationModes_XGXS_nLQnCC 9 17797 #define tx_x2_control0_operationModes_PBypass 10 17798 #define tx_x2_control0_operationModes_PBypass_nDSK 11 17799 #define tx_x2_control0_operationModes_ComboCoreMode 12 17800 #define tx_x2_control0_operationModes_Clocks_off 15 17801 17802 /**************************************************************************** 17803 * Enums: tx_x2_control0_actualSpeeds 17804 */ 17805 #define tx_x2_control0_actualSpeeds_dr_10M 0 17806 #define tx_x2_control0_actualSpeeds_dr_100M 1 17807 #define tx_x2_control0_actualSpeeds_dr_1G 2 17808 #define tx_x2_control0_actualSpeeds_dr_2p5G 3 17809 #define tx_x2_control0_actualSpeeds_dr_5G_X4 4 17810 #define tx_x2_control0_actualSpeeds_dr_6G_X4 5 17811 #define tx_x2_control0_actualSpeeds_dr_10G_HiG 6 17812 #define tx_x2_control0_actualSpeeds_dr_10G_CX4 7 17813 #define tx_x2_control0_actualSpeeds_dr_12G_HiG 8 17814 #define tx_x2_control0_actualSpeeds_dr_12p5G_X4 9 17815 #define tx_x2_control0_actualSpeeds_dr_13G_X4 10 17816 #define tx_x2_control0_actualSpeeds_dr_15G_X4 11 17817 #define tx_x2_control0_actualSpeeds_dr_16G_X4 12 17818 #define tx_x2_control0_actualSpeeds_dr_1G_KX 13 17819 #define tx_x2_control0_actualSpeeds_dr_10G_KX4 14 17820 #define tx_x2_control0_actualSpeeds_dr_10G_KR 15 17821 #define tx_x2_control0_actualSpeeds_dr_5G 16 17822 #define tx_x2_control0_actualSpeeds_dr_6p4G 17 17823 #define tx_x2_control0_actualSpeeds_dr_20G_X4 18 17824 #define tx_x2_control0_actualSpeeds_dr_21G_X4 19 17825 #define tx_x2_control0_actualSpeeds_dr_25G_X4 20 17826 #define tx_x2_control0_actualSpeeds_dr_10G_HiG_DXGXS 21 17827 #define tx_x2_control0_actualSpeeds_dr_10G_DXGXS 22 17828 #define tx_x2_control0_actualSpeeds_dr_10p5G_HiG_DXGXS 23 17829 #define tx_x2_control0_actualSpeeds_dr_10p5G_DXGXS 24 17830 #define tx_x2_control0_actualSpeeds_dr_12p773G_HiG_DXGXS 25 17831 #define tx_x2_control0_actualSpeeds_dr_12p773G_DXGXS 26 17832 #define tx_x2_control0_actualSpeeds_dr_10G_XFI 27 17833 #define tx_x2_control0_actualSpeeds_dr_40G 28 17834 #define tx_x2_control0_actualSpeeds_dr_20G_HiG_DXGXS 29 17835 #define tx_x2_control0_actualSpeeds_dr_20G_DXGXS 30 17836 #define tx_x2_control0_actualSpeeds_dr_10G_SFI 31 17837 #define tx_x2_control0_actualSpeeds_dr_31p5G 32 17838 #define tx_x2_control0_actualSpeeds_dr_32p7G 33 17839 #define tx_x2_control0_actualSpeeds_dr_20G_SCR 34 17840 #define tx_x2_control0_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 17841 #define tx_x2_control0_actualSpeeds_dr_10G_DXGXS_SCR 36 17842 #define tx_x2_control0_actualSpeeds_dr_12G_R2 37 17843 #define tx_x2_control0_actualSpeeds_dr_10G_X2 38 17844 #define tx_x2_control0_actualSpeeds_dr_40G_KR4 39 17845 #define tx_x2_control0_actualSpeeds_dr_40G_CR4 40 17846 #define tx_x2_control0_actualSpeeds_dr_100G_CR10 41 17847 #define tx_x2_control0_actualSpeeds_dr_15p75G_DXGXS 44 17848 #define tx_x2_control0_actualSpeeds_dr_20G_KR2 57 17849 #define tx_x2_control0_actualSpeeds_dr_20G_CR2 58 17850 17851 /**************************************************************************** 17852 * Enums: tx_x2_control0_actualSpeedsMisc1 17853 */ 17854 #define tx_x2_control0_actualSpeedsMisc1_dr_2500BRCM_X1 16 17855 #define tx_x2_control0_actualSpeedsMisc1_dr_5000BRCM_X4 17 17856 #define tx_x2_control0_actualSpeedsMisc1_dr_6000BRCM_X4 18 17857 #define tx_x2_control0_actualSpeedsMisc1_dr_10GHiGig_X4 19 17858 #define tx_x2_control0_actualSpeedsMisc1_dr_10GBASE_CX4 20 17859 #define tx_x2_control0_actualSpeedsMisc1_dr_12GHiGig_X4 21 17860 #define tx_x2_control0_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 17861 #define tx_x2_control0_actualSpeedsMisc1_dr_13GHiGig_X4 23 17862 #define tx_x2_control0_actualSpeedsMisc1_dr_15GHiGig_X4 24 17863 #define tx_x2_control0_actualSpeedsMisc1_dr_16GHiGig_X4 25 17864 #define tx_x2_control0_actualSpeedsMisc1_dr_5000BRCM_X1 26 17865 #define tx_x2_control0_actualSpeedsMisc1_dr_6363BRCM_X1 27 17866 #define tx_x2_control0_actualSpeedsMisc1_dr_20GHiGig_X4 28 17867 #define tx_x2_control0_actualSpeedsMisc1_dr_21GHiGig_X4 29 17868 #define tx_x2_control0_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 17869 #define tx_x2_control0_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 17870 17871 /**************************************************************************** 17872 * Enums: tx_x2_control0_IndLaneModes 17873 */ 17874 #define tx_x2_control0_IndLaneModes_SWSDR_div2 0 17875 #define tx_x2_control0_IndLaneModes_SWSDR_div1 1 17876 #define tx_x2_control0_IndLaneModes_DWSDR_div2 2 17877 #define tx_x2_control0_IndLaneModes_DWSDR_div1 3 17878 17879 /**************************************************************************** 17880 * Enums: tx_x2_control0_prbsSelect 17881 */ 17882 #define tx_x2_control0_prbsSelect_prbs7 0 17883 #define tx_x2_control0_prbsSelect_prbs15 1 17884 #define tx_x2_control0_prbsSelect_prbs23 2 17885 #define tx_x2_control0_prbsSelect_prbs31 3 17886 17887 /**************************************************************************** 17888 * Enums: tx_x2_control0_vcoDivider 17889 */ 17890 #define tx_x2_control0_vcoDivider_div32 0 17891 #define tx_x2_control0_vcoDivider_div36 1 17892 #define tx_x2_control0_vcoDivider_div40 2 17893 #define tx_x2_control0_vcoDivider_div42 3 17894 #define tx_x2_control0_vcoDivider_div48 4 17895 #define tx_x2_control0_vcoDivider_div50 5 17896 #define tx_x2_control0_vcoDivider_div52 6 17897 #define tx_x2_control0_vcoDivider_div54 7 17898 #define tx_x2_control0_vcoDivider_div60 8 17899 #define tx_x2_control0_vcoDivider_div64 9 17900 #define tx_x2_control0_vcoDivider_div66 10 17901 #define tx_x2_control0_vcoDivider_div68 11 17902 #define tx_x2_control0_vcoDivider_div70 12 17903 #define tx_x2_control0_vcoDivider_div80 13 17904 #define tx_x2_control0_vcoDivider_div92 14 17905 #define tx_x2_control0_vcoDivider_div100 15 17906 17907 /**************************************************************************** 17908 * Enums: tx_x2_control0_refClkSelect 17909 */ 17910 #define tx_x2_control0_refClkSelect_clk_25MHz 0 17911 #define tx_x2_control0_refClkSelect_clk_100MHz 1 17912 #define tx_x2_control0_refClkSelect_clk_125MHz 2 17913 #define tx_x2_control0_refClkSelect_clk_156p25MHz 3 17914 #define tx_x2_control0_refClkSelect_clk_187p5MHz 4 17915 #define tx_x2_control0_refClkSelect_clk_161p25Mhz 5 17916 #define tx_x2_control0_refClkSelect_clk_50Mhz 6 17917 #define tx_x2_control0_refClkSelect_clk_106p25Mhz 7 17918 17919 /**************************************************************************** 17920 * Enums: tx_x2_control0_aerMMDdevTypeSelect 17921 */ 17922 #define tx_x2_control0_aerMMDdevTypeSelect_combo_core 0 17923 #define tx_x2_control0_aerMMDdevTypeSelect_PMA_PMD 1 17924 #define tx_x2_control0_aerMMDdevTypeSelect_PCS 3 17925 #define tx_x2_control0_aerMMDdevTypeSelect_PHY 4 17926 #define tx_x2_control0_aerMMDdevTypeSelect_DTE 5 17927 #define tx_x2_control0_aerMMDdevTypeSelect_CL73_AN 7 17928 17929 /**************************************************************************** 17930 * Enums: tx_x2_control0_aerMMDportSelect 17931 */ 17932 #define tx_x2_control0_aerMMDportSelect_ln0 0 17933 #define tx_x2_control0_aerMMDportSelect_ln1 1 17934 #define tx_x2_control0_aerMMDportSelect_ln2 2 17935 #define tx_x2_control0_aerMMDportSelect_ln3 3 17936 #define tx_x2_control0_aerMMDportSelect_BCST_ln0_1_2_3 511 17937 #define tx_x2_control0_aerMMDportSelect_BCST_ln0_1 512 17938 #define tx_x2_control0_aerMMDportSelect_BCST_ln2_3 513 17939 17940 /**************************************************************************** 17941 * Enums: tx_x2_control0_firmwareModeSelect 17942 */ 17943 #define tx_x2_control0_firmwareModeSelect_DEFAULT 0 17944 #define tx_x2_control0_firmwareModeSelect_SFP_OPT_LR 1 17945 #define tx_x2_control0_firmwareModeSelect_SFP_DAC 2 17946 #define tx_x2_control0_firmwareModeSelect_XLAUI 3 17947 #define tx_x2_control0_firmwareModeSelect_LONG_CH_6G 4 17948 17949 /**************************************************************************** 17950 * Enums: tx_x2_control0_tempIdxSelect 17951 */ 17952 #define tx_x2_control0_tempIdxSelect_LTE__22p9C 15 17953 #define tx_x2_control0_tempIdxSelect_LTE__12p6C 14 17954 #define tx_x2_control0_tempIdxSelect_LTE__3p0C 13 17955 #define tx_x2_control0_tempIdxSelect_LTE_6p7C 12 17956 #define tx_x2_control0_tempIdxSelect_LTE_16p4C 11 17957 #define tx_x2_control0_tempIdxSelect_LTE_26p6C 10 17958 #define tx_x2_control0_tempIdxSelect_LTE_36p3C 9 17959 #define tx_x2_control0_tempIdxSelect_LTE_46p0C 8 17960 #define tx_x2_control0_tempIdxSelect_LTE_56p2C 7 17961 #define tx_x2_control0_tempIdxSelect_LTE_65p9C 6 17962 #define tx_x2_control0_tempIdxSelect_LTE_75p6C 5 17963 #define tx_x2_control0_tempIdxSelect_LTE_85p3C 4 17964 #define tx_x2_control0_tempIdxSelect_LTE_95p5C 3 17965 #define tx_x2_control0_tempIdxSelect_LTE_105p2C 2 17966 #define tx_x2_control0_tempIdxSelect_LTE_114p9C 1 17967 #define tx_x2_control0_tempIdxSelect_LTE_125p1C 0 17968 17969 /**************************************************************************** 17970 * Enums: tx_x2_control0_port_mode 17971 */ 17972 #define tx_x2_control0_port_mode_QUAD_PORT 0 17973 #define tx_x2_control0_port_mode_TRI_1_PORT 1 17974 #define tx_x2_control0_port_mode_TRI_2_PORT 2 17975 #define tx_x2_control0_port_mode_DUAL_PORT 3 17976 #define tx_x2_control0_port_mode_SINGLE_PORT 4 17977 17978 /**************************************************************************** 17979 * Enums: tx_x2_control0_rev_letter_enum 17980 */ 17981 #define tx_x2_control0_rev_letter_enum_REV_A 0 17982 #define tx_x2_control0_rev_letter_enum_REV_B 1 17983 #define tx_x2_control0_rev_letter_enum_REV_C 2 17984 #define tx_x2_control0_rev_letter_enum_REV_D 3 17985 17986 /**************************************************************************** 17987 * Enums: tx_x2_control0_rev_number_enum 17988 */ 17989 #define tx_x2_control0_rev_number_enum_REV_0 0 17990 #define tx_x2_control0_rev_number_enum_REV_1 1 17991 #define tx_x2_control0_rev_number_enum_REV_2 2 17992 #define tx_x2_control0_rev_number_enum_REV_3 3 17993 #define tx_x2_control0_rev_number_enum_REV_4 4 17994 #define tx_x2_control0_rev_number_enum_REV_5 5 17995 #define tx_x2_control0_rev_number_enum_REV_6 6 17996 #define tx_x2_control0_rev_number_enum_REV_7 7 17997 17998 /**************************************************************************** 17999 * Enums: tx_x2_control0_bonding_enum 18000 */ 18001 #define tx_x2_control0_bonding_enum_WIRE_BOND 0 18002 #define tx_x2_control0_bonding_enum_FLIP_CHIP 1 18003 18004 /**************************************************************************** 18005 * Enums: tx_x2_control0_tech_process 18006 */ 18007 #define tx_x2_control0_tech_process_PROCESS_90NM 0 18008 #define tx_x2_control0_tech_process_PROCESS_65NM 1 18009 #define tx_x2_control0_tech_process_PROCESS_40NM 2 18010 #define tx_x2_control0_tech_process_PROCESS_28NM 3 18011 #define tx_x2_control0_tech_process_PROCESS_16NM 4 18012 18013 /**************************************************************************** 18014 * Enums: tx_x2_control0_model_num 18015 */ 18016 #define tx_x2_control0_model_num_SERDES_CL73 0 18017 #define tx_x2_control0_model_num_XGXS_16G 1 18018 #define tx_x2_control0_model_num_HYPERCORE 2 18019 #define tx_x2_control0_model_num_HYPERLITE 3 18020 #define tx_x2_control0_model_num_PCIE_G2_PIPE 4 18021 #define tx_x2_control0_model_num_SERDES_1p25GBd 5 18022 #define tx_x2_control0_model_num_SATA2 6 18023 #define tx_x2_control0_model_num_QSGMII 7 18024 #define tx_x2_control0_model_num_XGXS10G 8 18025 #define tx_x2_control0_model_num_WARPCORE 9 18026 #define tx_x2_control0_model_num_XFICORE 10 18027 #define tx_x2_control0_model_num_RXFI 11 18028 #define tx_x2_control0_model_num_WARPLITE 12 18029 #define tx_x2_control0_model_num_PENTACORE 13 18030 #define tx_x2_control0_model_num_ESM 14 18031 #define tx_x2_control0_model_num_QUAD_SGMII 15 18032 #define tx_x2_control0_model_num_WARPCORE_3 16 18033 #define tx_x2_control0_model_num_TSC 17 18034 #define tx_x2_control0_model_num_TSC4E 18 18035 #define tx_x2_control0_model_num_TSC12E 19 18036 #define tx_x2_control0_model_num_TSC4F 20 18037 #define tx_x2_control0_model_num_TSC4F_GEN2 21 18038 #define tx_x2_control0_model_num_XGXS_CL73_90NM 29 18039 #define tx_x2_control0_model_num_SERDES_CL73_90NM 30 18040 #define tx_x2_control0_model_num_WARPCORE3 32 18041 #define tx_x2_control0_model_num_WARPCORE4_TSC 33 18042 #define tx_x2_control0_model_num_RXAUI 34 18043 18044 /**************************************************************************** 18045 * Enums: tx_x2_control0_payload 18046 */ 18047 #define tx_x2_control0_payload_REPEAT_2_BYTES 0 18048 #define tx_x2_control0_payload_RAMPING 1 18049 #define tx_x2_control0_payload_CL48_CRPAT 2 18050 #define tx_x2_control0_payload_CL48_CJPAT 3 18051 #define tx_x2_control0_payload_CL36_LONG_CRPAT 4 18052 #define tx_x2_control0_payload_CL36_SHORT_CRPAT 5 18053 18054 /**************************************************************************** 18055 * Enums: tx_x2_control0_sc 18056 */ 18057 #define tx_x2_control0_sc_S_10G_CR1 0 18058 #define tx_x2_control0_sc_S_10G_KR1 1 18059 #define tx_x2_control0_sc_S_10G_X1 2 18060 #define tx_x2_control0_sc_S_10G_HG2_CR1 4 18061 #define tx_x2_control0_sc_S_10G_HG2_KR1 5 18062 #define tx_x2_control0_sc_S_10G_HG2_X1 6 18063 #define tx_x2_control0_sc_S_20G_CR1 8 18064 #define tx_x2_control0_sc_S_20G_KR1 9 18065 #define tx_x2_control0_sc_S_20G_X1 10 18066 #define tx_x2_control0_sc_S_20G_HG2_CR1 12 18067 #define tx_x2_control0_sc_S_20G_HG2_KR1 13 18068 #define tx_x2_control0_sc_S_20G_HG2_X1 14 18069 #define tx_x2_control0_sc_S_25G_CR1 16 18070 #define tx_x2_control0_sc_S_25G_KR1 17 18071 #define tx_x2_control0_sc_S_25G_X1 18 18072 #define tx_x2_control0_sc_S_25G_HG2_CR1 20 18073 #define tx_x2_control0_sc_S_25G_HG2_KR1 21 18074 #define tx_x2_control0_sc_S_25G_HG2_X1 22 18075 #define tx_x2_control0_sc_S_20G_CR2 24 18076 #define tx_x2_control0_sc_S_20G_KR2 25 18077 #define tx_x2_control0_sc_S_20G_X2 26 18078 #define tx_x2_control0_sc_S_20G_HG2_CR2 28 18079 #define tx_x2_control0_sc_S_20G_HG2_KR2 29 18080 #define tx_x2_control0_sc_S_20G_HG2_X2 30 18081 #define tx_x2_control0_sc_S_40G_CR2 32 18082 #define tx_x2_control0_sc_S_40G_KR2 33 18083 #define tx_x2_control0_sc_S_40G_X2 34 18084 #define tx_x2_control0_sc_S_40G_HG2_CR2 36 18085 #define tx_x2_control0_sc_S_40G_HG2_KR2 37 18086 #define tx_x2_control0_sc_S_40G_HG2_X2 38 18087 #define tx_x2_control0_sc_S_40G_CR4 40 18088 #define tx_x2_control0_sc_S_40G_KR4 41 18089 #define tx_x2_control0_sc_S_40G_X4 42 18090 #define tx_x2_control0_sc_S_40G_HG2_CR4 44 18091 #define tx_x2_control0_sc_S_40G_HG2_KR4 45 18092 #define tx_x2_control0_sc_S_40G_HG2_X4 46 18093 #define tx_x2_control0_sc_S_50G_CR2 48 18094 #define tx_x2_control0_sc_S_50G_KR2 49 18095 #define tx_x2_control0_sc_S_50G_X2 50 18096 #define tx_x2_control0_sc_S_50G_HG2_CR2 52 18097 #define tx_x2_control0_sc_S_50G_HG2_KR2 53 18098 #define tx_x2_control0_sc_S_50G_HG2_X2 54 18099 #define tx_x2_control0_sc_S_50G_CR4 56 18100 #define tx_x2_control0_sc_S_50G_KR4 57 18101 #define tx_x2_control0_sc_S_50G_X4 58 18102 #define tx_x2_control0_sc_S_50G_HG2_CR4 60 18103 #define tx_x2_control0_sc_S_50G_HG2_KR4 61 18104 #define tx_x2_control0_sc_S_50G_HG2_X4 62 18105 #define tx_x2_control0_sc_S_100G_CR4 64 18106 #define tx_x2_control0_sc_S_100G_KR4 65 18107 #define tx_x2_control0_sc_S_100G_X4 66 18108 #define tx_x2_control0_sc_S_100G_HG2_CR4 68 18109 #define tx_x2_control0_sc_S_100G_HG2_KR4 69 18110 #define tx_x2_control0_sc_S_100G_HG2_X4 70 18111 #define tx_x2_control0_sc_S_CL73_20GVCO 72 18112 #define tx_x2_control0_sc_S_CL73_25GVCO 80 18113 #define tx_x2_control0_sc_S_CL36_20GVCO 88 18114 #define tx_x2_control0_sc_S_CL36_25GVCO 96 18115 #define tx_x2_control0_sc_S_25G_CR_IEEE 112 18116 #define tx_x2_control0_sc_S_25G_CRS_IEEE 113 18117 #define tx_x2_control0_sc_S_25G_KR_IEEE 114 18118 #define tx_x2_control0_sc_S_25G_KRS_IEEE 115 18119 18120 /**************************************************************************** 18121 * Enums: tx_x2_control0_t_fifo_modes 18122 */ 18123 #define tx_x2_control0_t_fifo_modes_T_FIFO_INSERT_NO_AM 0 18124 #define tx_x2_control0_t_fifo_modes_T_FIFO_INSERT_4_AM 1 18125 #define tx_x2_control0_t_fifo_modes_T_FIFO_INSERT_20_AM 2 18126 #define tx_x2_control0_t_fifo_modes_T_FIFO_INSERT_2_AM 3 18127 18128 /**************************************************************************** 18129 * Enums: tx_x2_control0_t_enc_modes 18130 */ 18131 #define tx_x2_control0_t_enc_modes_T_ENC_MODE_BYPASS 0 18132 #define tx_x2_control0_t_enc_modes_T_ENC_MODE_CL49 1 18133 #define tx_x2_control0_t_enc_modes_T_ENC_MODE_CL82 2 18134 18135 /**************************************************************************** 18136 * Enums: tx_x2_control0_btmx_mode 18137 */ 18138 #define tx_x2_control0_btmx_mode_BS_BTMX_MODE_1to1 0 18139 #define tx_x2_control0_btmx_mode_BS_BTMX_MODE_2to1 1 18140 #define tx_x2_control0_btmx_mode_BS_BTMX_MODE_5to1 2 18141 18142 /**************************************************************************** 18143 * Enums: tx_x2_control0_t_type_cl82 18144 */ 18145 #define tx_x2_control0_t_type_cl82_T_TYPE_B1 5 18146 #define tx_x2_control0_t_type_cl82_T_TYPE_C 4 18147 #define tx_x2_control0_t_type_cl82_T_TYPE_S 3 18148 #define tx_x2_control0_t_type_cl82_T_TYPE_T 2 18149 #define tx_x2_control0_t_type_cl82_T_TYPE_D 1 18150 #define tx_x2_control0_t_type_cl82_T_TYPE_E 0 18151 18152 /**************************************************************************** 18153 * Enums: tx_x2_control0_txsm_state_cl82 18154 */ 18155 #define tx_x2_control0_txsm_state_cl82_TX_HIG_END 6 18156 #define tx_x2_control0_txsm_state_cl82_TX_HIG_START 5 18157 #define tx_x2_control0_txsm_state_cl82_TX_E 4 18158 #define tx_x2_control0_txsm_state_cl82_TX_T 3 18159 #define tx_x2_control0_txsm_state_cl82_TX_D 2 18160 #define tx_x2_control0_txsm_state_cl82_TX_C 1 18161 #define tx_x2_control0_txsm_state_cl82_TX_INIT 0 18162 18163 /**************************************************************************** 18164 * Enums: tx_x2_control0_ltxsm_state_cl82 18165 */ 18166 #define tx_x2_control0_ltxsm_state_cl82_TX_HIG_END 64 18167 #define tx_x2_control0_ltxsm_state_cl82_TX_HIG_START 32 18168 #define tx_x2_control0_ltxsm_state_cl82_TX_E 16 18169 #define tx_x2_control0_ltxsm_state_cl82_TX_T 8 18170 #define tx_x2_control0_ltxsm_state_cl82_TX_D 4 18171 #define tx_x2_control0_ltxsm_state_cl82_TX_C 2 18172 #define tx_x2_control0_ltxsm_state_cl82_TX_INIT 1 18173 18174 /**************************************************************************** 18175 * Enums: tx_x2_control0_r_type_coded_cl82 18176 */ 18177 #define tx_x2_control0_r_type_coded_cl82_R_TYPE_B1 32 18178 #define tx_x2_control0_r_type_coded_cl82_R_TYPE_C 16 18179 #define tx_x2_control0_r_type_coded_cl82_R_TYPE_S 8 18180 #define tx_x2_control0_r_type_coded_cl82_R_TYPE_T 4 18181 #define tx_x2_control0_r_type_coded_cl82_R_TYPE_D 2 18182 #define tx_x2_control0_r_type_coded_cl82_R_TYPE_E 1 18183 18184 /**************************************************************************** 18185 * Enums: tx_x2_control0_rxsm_state_cl82 18186 */ 18187 #define tx_x2_control0_rxsm_state_cl82_RX_HIG_END 64 18188 #define tx_x2_control0_rxsm_state_cl82_RX_HIG_START 32 18189 #define tx_x2_control0_rxsm_state_cl82_RX_E 16 18190 #define tx_x2_control0_rxsm_state_cl82_RX_T 8 18191 #define tx_x2_control0_rxsm_state_cl82_RX_D 4 18192 #define tx_x2_control0_rxsm_state_cl82_RX_C 2 18193 #define tx_x2_control0_rxsm_state_cl82_RX_INIT 1 18194 18195 /**************************************************************************** 18196 * Enums: tx_x2_control0_deskew_state 18197 */ 18198 #define tx_x2_control0_deskew_state_ALIGN_ACQUIRED 2 18199 #define tx_x2_control0_deskew_state_LOSS_OF_ALIGNMENT 1 18200 18201 /**************************************************************************** 18202 * Enums: tx_x2_control0_os_mode_enum 18203 */ 18204 #define tx_x2_control0_os_mode_enum_OS_MODE_1 0 18205 #define tx_x2_control0_os_mode_enum_OS_MODE_2 1 18206 #define tx_x2_control0_os_mode_enum_OS_MODE_4 2 18207 #define tx_x2_control0_os_mode_enum_OS_MODE_16p5 8 18208 #define tx_x2_control0_os_mode_enum_OS_MODE_20p625 12 18209 18210 /**************************************************************************** 18211 * Enums: tx_x2_control0_scr_modes 18212 */ 18213 #define tx_x2_control0_scr_modes_T_SCR_MODE_BYPASS 0 18214 #define tx_x2_control0_scr_modes_T_SCR_MODE_CL49 1 18215 #define tx_x2_control0_scr_modes_T_SCR_MODE_40G_2_LANE 2 18216 #define tx_x2_control0_scr_modes_T_SCR_MODE_100G 3 18217 #define tx_x2_control0_scr_modes_T_SCR_MODE_20G 4 18218 #define tx_x2_control0_scr_modes_T_SCR_MODE_40G_4_LANE 5 18219 18220 /**************************************************************************** 18221 * Enums: tx_x2_control0_descr_modes 18222 */ 18223 #define tx_x2_control0_descr_modes_R_DESCR_MODE_BYPASS 0 18224 #define tx_x2_control0_descr_modes_R_DESCR_MODE_CL49 1 18225 #define tx_x2_control0_descr_modes_R_DESCR_MODE_CL82 2 18226 18227 /**************************************************************************** 18228 * Enums: tx_x2_control0_r_dec_tl_mode 18229 */ 18230 #define tx_x2_control0_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 18231 #define tx_x2_control0_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 18232 #define tx_x2_control0_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 18233 18234 /**************************************************************************** 18235 * Enums: tx_x2_control0_r_dec_fsm_mode 18236 */ 18237 #define tx_x2_control0_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 18238 #define tx_x2_control0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 18239 #define tx_x2_control0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 18240 18241 /**************************************************************************** 18242 * Enums: tx_x2_control0_r_deskew_mode 18243 */ 18244 #define tx_x2_control0_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 18245 #define tx_x2_control0_r_deskew_mode_R_DESKEW_MODE_20G 1 18246 #define tx_x2_control0_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 18247 #define tx_x2_control0_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 18248 #define tx_x2_control0_r_deskew_mode_R_DESKEW_MODE_100G 4 18249 #define tx_x2_control0_r_deskew_mode_R_DESKEW_MODE_CL49 5 18250 #define tx_x2_control0_r_deskew_mode_R_DESKEW_MODE_CL91_QUAD 6 18251 #define tx_x2_control0_r_deskew_mode_R_DESKEW_MODE_CL91_SINGLE_BRCM 7 18252 #define tx_x2_control0_r_deskew_mode_R_DESKEW_MODE_CL91_DUAL_BRCM 8 18253 #define tx_x2_control0_r_deskew_mode_R_DESKEW_MODE_CL91_FC 9 18254 18255 /**************************************************************************** 18256 * Enums: tx_x2_control0_bs_dist_modes 18257 */ 18258 #define tx_x2_control0_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 18259 #define tx_x2_control0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 18260 #define tx_x2_control0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 18261 #define tx_x2_control0_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 18262 18263 /**************************************************************************** 18264 * Enums: tx_x2_control0_cl49_t_type 18265 */ 18266 #define tx_x2_control0_cl49_t_type_BAD_T_TYPE 15 18267 #define tx_x2_control0_cl49_t_type_T_TYPE_B0 11 18268 #define tx_x2_control0_cl49_t_type_T_TYPE_OB 10 18269 #define tx_x2_control0_cl49_t_type_T_TYPE_B1 9 18270 #define tx_x2_control0_cl49_t_type_T_TYPE_DB 8 18271 #define tx_x2_control0_cl49_t_type_T_TYPE_FC 7 18272 #define tx_x2_control0_cl49_t_type_T_TYPE_TB 6 18273 #define tx_x2_control0_cl49_t_type_T_TYPE_LI 5 18274 #define tx_x2_control0_cl49_t_type_T_TYPE_C 4 18275 #define tx_x2_control0_cl49_t_type_T_TYPE_S 3 18276 #define tx_x2_control0_cl49_t_type_T_TYPE_T 2 18277 #define tx_x2_control0_cl49_t_type_T_TYPE_D 1 18278 #define tx_x2_control0_cl49_t_type_T_TYPE_E 0 18279 18280 /**************************************************************************** 18281 * Enums: tx_x2_control0_cl49_txsm_states 18282 */ 18283 #define tx_x2_control0_cl49_txsm_states_TX_HIG_END 7 18284 #define tx_x2_control0_cl49_txsm_states_TX_HIG_START 6 18285 #define tx_x2_control0_cl49_txsm_states_TX_LI 5 18286 #define tx_x2_control0_cl49_txsm_states_TX_E 4 18287 #define tx_x2_control0_cl49_txsm_states_TX_T 3 18288 #define tx_x2_control0_cl49_txsm_states_TX_D 2 18289 #define tx_x2_control0_cl49_txsm_states_TX_C 1 18290 #define tx_x2_control0_cl49_txsm_states_TX_INIT 0 18291 18292 /**************************************************************************** 18293 * Enums: tx_x2_control0_cl49_ltxsm_states 18294 */ 18295 #define tx_x2_control0_cl49_ltxsm_states_TX_HIG_END 128 18296 #define tx_x2_control0_cl49_ltxsm_states_TX_HIG_START 64 18297 #define tx_x2_control0_cl49_ltxsm_states_TX_LI 32 18298 #define tx_x2_control0_cl49_ltxsm_states_TX_E 16 18299 #define tx_x2_control0_cl49_ltxsm_states_TX_T 8 18300 #define tx_x2_control0_cl49_ltxsm_states_TX_D 4 18301 #define tx_x2_control0_cl49_ltxsm_states_TX_C 2 18302 #define tx_x2_control0_cl49_ltxsm_states_TX_INIT 1 18303 18304 /**************************************************************************** 18305 * Enums: tx_x2_control0_burst_error_mode 18306 */ 18307 #define tx_x2_control0_burst_error_mode_BURST_ERROR_11_BITS 0 18308 #define tx_x2_control0_burst_error_mode_BURST_ERROR_16_BITS 1 18309 #define tx_x2_control0_burst_error_mode_BURST_ERROR_17_BITS 2 18310 #define tx_x2_control0_burst_error_mode_BURST_ERROR_18_BITS 3 18311 #define tx_x2_control0_burst_error_mode_BURST_ERROR_19_BITS 4 18312 #define tx_x2_control0_burst_error_mode_BURST_ERROR_20_BITS 5 18313 #define tx_x2_control0_burst_error_mode_BURST_ERROR_21_BITS 6 18314 #define tx_x2_control0_burst_error_mode_BURST_ERROR_22_BITS 7 18315 #define tx_x2_control0_burst_error_mode_BURST_ERROR_23_BITS 8 18316 #define tx_x2_control0_burst_error_mode_BURST_ERROR_24_BITS 9 18317 #define tx_x2_control0_burst_error_mode_BURST_ERROR_25_BITS 10 18318 #define tx_x2_control0_burst_error_mode_BURST_ERROR_26_BITS 11 18319 #define tx_x2_control0_burst_error_mode_BURST_ERROR_27_BITS 12 18320 #define tx_x2_control0_burst_error_mode_BURST_ERROR_28_BITS 13 18321 #define tx_x2_control0_burst_error_mode_BURST_ERROR_29_BITS 14 18322 #define tx_x2_control0_burst_error_mode_BURST_ERROR_30_BITS 15 18323 #define tx_x2_control0_burst_error_mode_BURST_ERROR_31_BITS 16 18324 #define tx_x2_control0_burst_error_mode_BURST_ERROR_32_BITS 17 18325 #define tx_x2_control0_burst_error_mode_BURST_ERROR_33_BITS 18 18326 #define tx_x2_control0_burst_error_mode_BURST_ERROR_34_BITS 19 18327 #define tx_x2_control0_burst_error_mode_BURST_ERROR_35_BITS 20 18328 #define tx_x2_control0_burst_error_mode_BURST_ERROR_36_BITS 21 18329 #define tx_x2_control0_burst_error_mode_BURST_ERROR_37_BITS 22 18330 #define tx_x2_control0_burst_error_mode_BURST_ERROR_38_BITS 23 18331 #define tx_x2_control0_burst_error_mode_BURST_ERROR_39_BITS 24 18332 #define tx_x2_control0_burst_error_mode_BURST_ERROR_40_BITS 25 18333 #define tx_x2_control0_burst_error_mode_BURST_ERROR_41_BITS 26 18334 18335 /**************************************************************************** 18336 * Enums: tx_x2_control0_bermon_state 18337 */ 18338 #define tx_x2_control0_bermon_state_HI_BER 4 18339 #define tx_x2_control0_bermon_state_GOOD_BER 3 18340 #define tx_x2_control0_bermon_state_BER_TEST_SH 2 18341 #define tx_x2_control0_bermon_state_START_TIMER 1 18342 #define tx_x2_control0_bermon_state_BER_MT_INIT 0 18343 18344 /**************************************************************************** 18345 * Enums: tx_x2_control0_rxsm_state_cl49 18346 */ 18347 #define tx_x2_control0_rxsm_state_cl49_RX_HIG_END 128 18348 #define tx_x2_control0_rxsm_state_cl49_RX_HIG_START 64 18349 #define tx_x2_control0_rxsm_state_cl49_RX_LI 32 18350 #define tx_x2_control0_rxsm_state_cl49_RX_E 16 18351 #define tx_x2_control0_rxsm_state_cl49_RX_T 8 18352 #define tx_x2_control0_rxsm_state_cl49_RX_D 4 18353 #define tx_x2_control0_rxsm_state_cl49_RX_C 2 18354 #define tx_x2_control0_rxsm_state_cl49_RX_INIT 1 18355 18356 /**************************************************************************** 18357 * Enums: tx_x2_control0_r_type 18358 */ 18359 #define tx_x2_control0_r_type_BAD_R_TYPE 15 18360 #define tx_x2_control0_r_type_R_TYPE_B0 11 18361 #define tx_x2_control0_r_type_R_TYPE_OB 10 18362 #define tx_x2_control0_r_type_R_TYPE_B1 9 18363 #define tx_x2_control0_r_type_R_TYPE_DB 8 18364 #define tx_x2_control0_r_type_R_TYPE_FC 7 18365 #define tx_x2_control0_r_type_R_TYPE_TB 6 18366 #define tx_x2_control0_r_type_R_TYPE_LI 5 18367 #define tx_x2_control0_r_type_R_TYPE_C 4 18368 #define tx_x2_control0_r_type_R_TYPE_S 3 18369 #define tx_x2_control0_r_type_R_TYPE_T 2 18370 #define tx_x2_control0_r_type_R_TYPE_D 1 18371 #define tx_x2_control0_r_type_R_TYPE_E 0 18372 18373 /**************************************************************************** 18374 * Enums: tx_x2_control0_am_lock_state 18375 */ 18376 #define tx_x2_control0_am_lock_state_INVALID_AM 512 18377 #define tx_x2_control0_am_lock_state_GOOD_AM 256 18378 #define tx_x2_control0_am_lock_state_COMP_AM 128 18379 #define tx_x2_control0_am_lock_state_TIMER_2 64 18380 #define tx_x2_control0_am_lock_state_AM_2_GOOD 32 18381 #define tx_x2_control0_am_lock_state_COMP_2ND 16 18382 #define tx_x2_control0_am_lock_state_TIMER_1 8 18383 #define tx_x2_control0_am_lock_state_FIND_1ST 4 18384 #define tx_x2_control0_am_lock_state_AM_RESET_CNT 2 18385 #define tx_x2_control0_am_lock_state_AM_LOCK_INIT 1 18386 18387 /**************************************************************************** 18388 * Enums: tx_x2_control0_msg_selector 18389 */ 18390 #define tx_x2_control0_msg_selector_RESERVED 0 18391 #define tx_x2_control0_msg_selector_VALUE_802p3 1 18392 #define tx_x2_control0_msg_selector_VALUE_802p9 2 18393 #define tx_x2_control0_msg_selector_VALUE_802p5 3 18394 #define tx_x2_control0_msg_selector_VALUE_1394 4 18395 18396 /**************************************************************************** 18397 * Enums: tx_x2_control0_synce_enum 18398 */ 18399 #define tx_x2_control0_synce_enum_SYNCE_NO_DIV 0 18400 #define tx_x2_control0_synce_enum_SYNCE_DIV_7 1 18401 #define tx_x2_control0_synce_enum_SYNCE_DIV_11 2 18402 18403 /**************************************************************************** 18404 * Enums: tx_x2_control0_synce_enum_stage0 18405 */ 18406 #define tx_x2_control0_synce_enum_stage0_SYNCE_NO_DIV 0 18407 #define tx_x2_control0_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 18408 #define tx_x2_control0_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 18409 18410 /**************************************************************************** 18411 * Enums: tx_x2_control0_cl91_sync_state 18412 */ 18413 #define tx_x2_control0_cl91_sync_state_FIND_1ST 0 18414 #define tx_x2_control0_cl91_sync_state_COUNT_NEXT 1 18415 #define tx_x2_control0_cl91_sync_state_COMP_2ND 2 18416 #define tx_x2_control0_cl91_sync_state_TWO_GOOD 3 18417 18418 /**************************************************************************** 18419 * Enums: tx_x2_control0_cl91_algn_state 18420 */ 18421 #define tx_x2_control0_cl91_algn_state_LOSS_OF_ALIGNMENT 0 18422 #define tx_x2_control0_cl91_algn_state_DESKEW 1 18423 #define tx_x2_control0_cl91_algn_state_DESKEW_FAIL 2 18424 #define tx_x2_control0_cl91_algn_state_ALIGN_ACQUIRED 3 18425 #define tx_x2_control0_cl91_algn_state_CW_GOOD 4 18426 #define tx_x2_control0_cl91_algn_state_CW_BAD 5 18427 #define tx_x2_control0_cl91_algn_state_THREE_BAD 6 18428 18429 /**************************************************************************** 18430 * Enums: tx_x2_control0_fec_sel_override 18431 */ 18432 #define tx_x2_control0_fec_sel_override_NO_OVERRIDE 0 18433 #define tx_x2_control0_fec_sel_override_NO_FEC 1 18434 #define tx_x2_control0_fec_sel_override_FEC_CL74 2 18435 #define tx_x2_control0_fec_sel_override_FEC_CL91 3 18436 18437 /**************************************************************************** 18438 * Enums: tx_x2_control0_cl91_blksync_mode 18439 */ 18440 #define tx_x2_control0_cl91_blksync_mode_R_BLKSYNC_NO_CL91_FEC 0 18441 #define tx_x2_control0_cl91_blksync_mode_R_BLKSYNC_CL91_QUAD_LANE_FEC 1 18442 #define tx_x2_control0_cl91_blksync_mode_R_BLKSYNC_CL91_DUAL_LANE_FEC 2 18443 #define tx_x2_control0_cl91_blksync_mode_R_BLKSYNC_CL91_SINGLE_LANE_FEC 3 18444 #define tx_x2_control0_cl91_blksync_mode_R_BLKSYNC_CL91_FC_FEC 4 18445 18446 /**************************************************************************** 18447 * Enums: tx_x2_control0_r_merge_mode 18448 */ 18449 #define tx_x2_control0_r_merge_mode_R_MERGE_MODE_BYPASS 0 18450 #define tx_x2_control0_r_merge_mode_R_MERGE_MODE_CL91_FC 1 18451 #define tx_x2_control0_r_merge_mode_R_MERGE_MODE_CL91_SINGLE_LANE 2 18452 #define tx_x2_control0_r_merge_mode_R_MERGE_MODE_CL91_DUAL_LANE 3 18453 #define tx_x2_control0_r_merge_mode_R_MERGE_MODE_CL91_QUAD_LANE 4 18454 18455 /**************************************************************************** 18456 * Enums: tx_x2_control0_r_tc_mode 18457 */ 18458 #define tx_x2_control0_r_tc_mode_R_TC_MODE_SINGLE 0 18459 #define tx_x2_control0_r_tc_mode_R_TC_MODE_DUAL 1 18460 #define tx_x2_control0_r_tc_mode_R_TC_MODE_QUAD 2 18461 18462 /**************************************************************************** 18463 * Enums: tx_x2_control0_r_tc_out_mode 18464 */ 18465 #define tx_x2_control0_r_tc_out_mode_R_TC_OUT_MODE_SINGLE 0 18466 #define tx_x2_control0_r_tc_out_mode_R_TC_OUT_MODE_DUAL 1 18467 #define tx_x2_control0_r_tc_out_mode_R_TC_OUT_MODE_QUAD 2 18468 18469 /**************************************************************************** 18470 * Enums: tx_x2_control0_cl91_fec_mode 18471 */ 18472 #define tx_x2_control0_cl91_fec_mode_NO_CL91_FEC 0 18473 #define tx_x2_control0_cl91_fec_mode_CL91_SINGLE_LANE_FC 1 18474 #define tx_x2_control0_cl91_fec_mode_CL91_SINGLE_LANE_BRCM_PROP 2 18475 #define tx_x2_control0_cl91_fec_mode_CL91_DUAL_LANE_BRCM_PROP 3 18476 #define tx_x2_control0_cl91_fec_mode_CL91_QUAD_LANE 4 18477 #define tx_x2_control0_cl91_fec_mode_IEEE_25G_CL91_SINGLE_LANE 5 18478 18479 /**************************************************************************** 18480 * Enums: tx_x2_control0_am_spacing_mul 18481 */ 18482 #define tx_x2_control0_am_spacing_mul_AM_SPACING_MUL_2 0 18483 #define tx_x2_control0_am_spacing_mul_AM_SPACING_MUL_4 1 18484 #define tx_x2_control0_am_spacing_mul_AM_SPACING_MUL_5 2 18485 #define tx_x2_control0_am_spacing_mul_AM_SPACING_MUL_20 3 18486 18487 /**************************************************************************** 18488 * Enums: tx_x2_status0_cl36TxEEEStates_l 18489 */ 18490 #define tx_x2_status0_cl36TxEEEStates_l_TX_REFRESH 8 18491 #define tx_x2_status0_cl36TxEEEStates_l_TX_QUIET 4 18492 #define tx_x2_status0_cl36TxEEEStates_l_TX_SLEEP 2 18493 #define tx_x2_status0_cl36TxEEEStates_l_TX_ACTIVE 1 18494 18495 /**************************************************************************** 18496 * Enums: tx_x2_status0_cl36TxEEEStates_c 18497 */ 18498 #define tx_x2_status0_cl36TxEEEStates_c_TX_REFRESH 3 18499 #define tx_x2_status0_cl36TxEEEStates_c_TX_QUIET 2 18500 #define tx_x2_status0_cl36TxEEEStates_c_TX_SLEEP 1 18501 #define tx_x2_status0_cl36TxEEEStates_c_TX_ACTIVE 0 18502 18503 /**************************************************************************** 18504 * Enums: tx_x2_status0_cl49TxEEEStates_l 18505 */ 18506 #define tx_x2_status0_cl49TxEEEStates_l_SCR_RESET_2 64 18507 #define tx_x2_status0_cl49TxEEEStates_l_SCR_RESET_1 32 18508 #define tx_x2_status0_cl49TxEEEStates_l_TX_WAKE 16 18509 #define tx_x2_status0_cl49TxEEEStates_l_TX_REFRESH 8 18510 #define tx_x2_status0_cl49TxEEEStates_l_TX_QUIET 4 18511 #define tx_x2_status0_cl49TxEEEStates_l_TX_SLEEP 2 18512 #define tx_x2_status0_cl49TxEEEStates_l_TX_ACTIVE 1 18513 18514 /**************************************************************************** 18515 * Enums: tx_x2_status0_fec_req_enum 18516 */ 18517 #define tx_x2_status0_fec_req_enum_FEC_not_supported 0 18518 #define tx_x2_status0_fec_req_enum_FEC_supported_but_not_requested 1 18519 #define tx_x2_status0_fec_req_enum_invalid_setting 2 18520 #define tx_x2_status0_fec_req_enum_FEC_supported_and_requested 3 18521 18522 /**************************************************************************** 18523 * Enums: tx_x2_status0_cl73_pause_enum 18524 */ 18525 #define tx_x2_status0_cl73_pause_enum_No_PAUSE_ability 0 18526 #define tx_x2_status0_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 18527 #define tx_x2_status0_cl73_pause_enum_Symmetric_PAUSE_ability 1 18528 #define tx_x2_status0_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 18529 18530 /**************************************************************************** 18531 * Enums: tx_x2_status0_cl49TxEEEStates_c 18532 */ 18533 #define tx_x2_status0_cl49TxEEEStates_c_SCR_RESET_2 6 18534 #define tx_x2_status0_cl49TxEEEStates_c_SCR_RESET_1 5 18535 #define tx_x2_status0_cl49TxEEEStates_c_TX_WAKE 4 18536 #define tx_x2_status0_cl49TxEEEStates_c_TX_REFRESH 3 18537 #define tx_x2_status0_cl49TxEEEStates_c_TX_QUIET 2 18538 #define tx_x2_status0_cl49TxEEEStates_c_TX_SLEEP 1 18539 #define tx_x2_status0_cl49TxEEEStates_c_TX_ACTIVE 0 18540 18541 /**************************************************************************** 18542 * Enums: tx_x2_status0_cl36RxEEEStates_l 18543 */ 18544 #define tx_x2_status0_cl36RxEEEStates_l_RX_LINK_FAIL 32 18545 #define tx_x2_status0_cl36RxEEEStates_l_RX_WTF 16 18546 #define tx_x2_status0_cl36RxEEEStates_l_RX_WAKE 8 18547 #define tx_x2_status0_cl36RxEEEStates_l_RX_QUIET 4 18548 #define tx_x2_status0_cl36RxEEEStates_l_RX_SLEEP 2 18549 #define tx_x2_status0_cl36RxEEEStates_l_RX_ACTIVE 1 18550 18551 /**************************************************************************** 18552 * Enums: tx_x2_status0_cl36RxEEEStates_c 18553 */ 18554 #define tx_x2_status0_cl36RxEEEStates_c_RX_LINK_FAIL 5 18555 #define tx_x2_status0_cl36RxEEEStates_c_RX_WTF 4 18556 #define tx_x2_status0_cl36RxEEEStates_c_RX_WAKE 3 18557 #define tx_x2_status0_cl36RxEEEStates_c_RX_QUIET 2 18558 #define tx_x2_status0_cl36RxEEEStates_c_RX_SLEEP 1 18559 #define tx_x2_status0_cl36RxEEEStates_c_RX_ACTIVE 0 18560 18561 /**************************************************************************** 18562 * Enums: tx_x2_status0_cl49RxEEEStates_l 18563 */ 18564 #define tx_x2_status0_cl49RxEEEStates_l_RX_LINK_FAIL 32 18565 #define tx_x2_status0_cl49RxEEEStates_l_RX_WTF 16 18566 #define tx_x2_status0_cl49RxEEEStates_l_RX_WAKE 8 18567 #define tx_x2_status0_cl49RxEEEStates_l_RX_QUIET 4 18568 #define tx_x2_status0_cl49RxEEEStates_l_RX_SLEEP 2 18569 #define tx_x2_status0_cl49RxEEEStates_l_RX_ACTIVE 1 18570 18571 /**************************************************************************** 18572 * Enums: tx_x2_status0_cl49RxEEEStates_c 18573 */ 18574 #define tx_x2_status0_cl49RxEEEStates_c_RX_LINK_FAIL 5 18575 #define tx_x2_status0_cl49RxEEEStates_c_RX_WTF 4 18576 #define tx_x2_status0_cl49RxEEEStates_c_RX_WAKE 3 18577 #define tx_x2_status0_cl49RxEEEStates_c_RX_QUIET 2 18578 #define tx_x2_status0_cl49RxEEEStates_c_RX_SLEEP 1 18579 #define tx_x2_status0_cl49RxEEEStates_c_RX_ACTIVE 0 18580 18581 /**************************************************************************** 18582 * Enums: tx_x2_status0_cl48TxEEEStates_l 18583 */ 18584 #define tx_x2_status0_cl48TxEEEStates_l_TX_REFRESH 8 18585 #define tx_x2_status0_cl48TxEEEStates_l_TX_QUIET 4 18586 #define tx_x2_status0_cl48TxEEEStates_l_TX_SLEEP 2 18587 #define tx_x2_status0_cl48TxEEEStates_l_TX_ACTIVE 1 18588 18589 /**************************************************************************** 18590 * Enums: tx_x2_status0_cl48TxEEEStates_c 18591 */ 18592 #define tx_x2_status0_cl48TxEEEStates_c_TX_REFRESH 3 18593 #define tx_x2_status0_cl48TxEEEStates_c_TX_QUIET 2 18594 #define tx_x2_status0_cl48TxEEEStates_c_TX_SLEEP 1 18595 #define tx_x2_status0_cl48TxEEEStates_c_TX_ACTIVE 0 18596 18597 /**************************************************************************** 18598 * Enums: tx_x2_status0_cl48RxEEEStates_l 18599 */ 18600 #define tx_x2_status0_cl48RxEEEStates_l_RX_LINK_FAIL 32 18601 #define tx_x2_status0_cl48RxEEEStates_l_RX_WAKE 16 18602 #define tx_x2_status0_cl48RxEEEStates_l_RX_QUIET 8 18603 #define tx_x2_status0_cl48RxEEEStates_l_RX_DEACT 4 18604 #define tx_x2_status0_cl48RxEEEStates_l_RX_SLEEP 2 18605 #define tx_x2_status0_cl48RxEEEStates_l_RX_ACTIVE 1 18606 18607 /**************************************************************************** 18608 * Enums: tx_x2_status0_cl48RxEEEStates_c 18609 */ 18610 #define tx_x2_status0_cl48RxEEEStates_c_RX_LINK_FAIL 5 18611 #define tx_x2_status0_cl48RxEEEStates_c_RX_WAKE 4 18612 #define tx_x2_status0_cl48RxEEEStates_c_RX_QUIET 3 18613 #define tx_x2_status0_cl48RxEEEStates_c_RX_DEACT 2 18614 #define tx_x2_status0_cl48RxEEEStates_c_RX_SLEEP 1 18615 #define tx_x2_status0_cl48RxEEEStates_c_RX_ACTIVE 0 18616 18617 /**************************************************************************** 18618 * Enums: tx_x2_status0_IQP_Options 18619 */ 18620 #define tx_x2_status0_IQP_Options_i50uA 0 18621 #define tx_x2_status0_IQP_Options_i100uA 1 18622 #define tx_x2_status0_IQP_Options_i150uA 2 18623 #define tx_x2_status0_IQP_Options_i200uA 3 18624 #define tx_x2_status0_IQP_Options_i250uA 4 18625 #define tx_x2_status0_IQP_Options_i300uA 5 18626 #define tx_x2_status0_IQP_Options_i350uA 6 18627 #define tx_x2_status0_IQP_Options_i400uA 7 18628 #define tx_x2_status0_IQP_Options_i450uA 8 18629 #define tx_x2_status0_IQP_Options_i500uA 9 18630 #define tx_x2_status0_IQP_Options_i550uA 10 18631 #define tx_x2_status0_IQP_Options_i600uA 11 18632 #define tx_x2_status0_IQP_Options_i650uA 12 18633 #define tx_x2_status0_IQP_Options_i700uA 13 18634 #define tx_x2_status0_IQP_Options_i750uA 14 18635 #define tx_x2_status0_IQP_Options_i800uA 15 18636 18637 /**************************************************************************** 18638 * Enums: tx_x2_status0_IDriver_Options 18639 */ 18640 #define tx_x2_status0_IDriver_Options_v680mV 0 18641 #define tx_x2_status0_IDriver_Options_v730mV 1 18642 #define tx_x2_status0_IDriver_Options_v780mV 2 18643 #define tx_x2_status0_IDriver_Options_v830mV 3 18644 #define tx_x2_status0_IDriver_Options_v880mV 4 18645 #define tx_x2_status0_IDriver_Options_v930mV 5 18646 #define tx_x2_status0_IDriver_Options_v980mV 6 18647 #define tx_x2_status0_IDriver_Options_v1010mV 7 18648 #define tx_x2_status0_IDriver_Options_v1040mV 8 18649 #define tx_x2_status0_IDriver_Options_v1060mV 9 18650 #define tx_x2_status0_IDriver_Options_v1070mV 10 18651 #define tx_x2_status0_IDriver_Options_v1080mV 11 18652 #define tx_x2_status0_IDriver_Options_v1085mV 12 18653 #define tx_x2_status0_IDriver_Options_v1090mV 13 18654 #define tx_x2_status0_IDriver_Options_v1095mV 14 18655 #define tx_x2_status0_IDriver_Options_v1100mV 15 18656 18657 /**************************************************************************** 18658 * Enums: tx_x2_status0_operationModes 18659 */ 18660 #define tx_x2_status0_operationModes_XGXS 0 18661 #define tx_x2_status0_operationModes_XGXG_nCC 1 18662 #define tx_x2_status0_operationModes_Indlane_OS8 4 18663 #define tx_x2_status0_operationModes_IndLane_OS5 5 18664 #define tx_x2_status0_operationModes_PCI 7 18665 #define tx_x2_status0_operationModes_XGXS_nLQ 8 18666 #define tx_x2_status0_operationModes_XGXS_nLQnCC 9 18667 #define tx_x2_status0_operationModes_PBypass 10 18668 #define tx_x2_status0_operationModes_PBypass_nDSK 11 18669 #define tx_x2_status0_operationModes_ComboCoreMode 12 18670 #define tx_x2_status0_operationModes_Clocks_off 15 18671 18672 /**************************************************************************** 18673 * Enums: tx_x2_status0_actualSpeeds 18674 */ 18675 #define tx_x2_status0_actualSpeeds_dr_10M 0 18676 #define tx_x2_status0_actualSpeeds_dr_100M 1 18677 #define tx_x2_status0_actualSpeeds_dr_1G 2 18678 #define tx_x2_status0_actualSpeeds_dr_2p5G 3 18679 #define tx_x2_status0_actualSpeeds_dr_5G_X4 4 18680 #define tx_x2_status0_actualSpeeds_dr_6G_X4 5 18681 #define tx_x2_status0_actualSpeeds_dr_10G_HiG 6 18682 #define tx_x2_status0_actualSpeeds_dr_10G_CX4 7 18683 #define tx_x2_status0_actualSpeeds_dr_12G_HiG 8 18684 #define tx_x2_status0_actualSpeeds_dr_12p5G_X4 9 18685 #define tx_x2_status0_actualSpeeds_dr_13G_X4 10 18686 #define tx_x2_status0_actualSpeeds_dr_15G_X4 11 18687 #define tx_x2_status0_actualSpeeds_dr_16G_X4 12 18688 #define tx_x2_status0_actualSpeeds_dr_1G_KX 13 18689 #define tx_x2_status0_actualSpeeds_dr_10G_KX4 14 18690 #define tx_x2_status0_actualSpeeds_dr_10G_KR 15 18691 #define tx_x2_status0_actualSpeeds_dr_5G 16 18692 #define tx_x2_status0_actualSpeeds_dr_6p4G 17 18693 #define tx_x2_status0_actualSpeeds_dr_20G_X4 18 18694 #define tx_x2_status0_actualSpeeds_dr_21G_X4 19 18695 #define tx_x2_status0_actualSpeeds_dr_25G_X4 20 18696 #define tx_x2_status0_actualSpeeds_dr_10G_HiG_DXGXS 21 18697 #define tx_x2_status0_actualSpeeds_dr_10G_DXGXS 22 18698 #define tx_x2_status0_actualSpeeds_dr_10p5G_HiG_DXGXS 23 18699 #define tx_x2_status0_actualSpeeds_dr_10p5G_DXGXS 24 18700 #define tx_x2_status0_actualSpeeds_dr_12p773G_HiG_DXGXS 25 18701 #define tx_x2_status0_actualSpeeds_dr_12p773G_DXGXS 26 18702 #define tx_x2_status0_actualSpeeds_dr_10G_XFI 27 18703 #define tx_x2_status0_actualSpeeds_dr_40G 28 18704 #define tx_x2_status0_actualSpeeds_dr_20G_HiG_DXGXS 29 18705 #define tx_x2_status0_actualSpeeds_dr_20G_DXGXS 30 18706 #define tx_x2_status0_actualSpeeds_dr_10G_SFI 31 18707 #define tx_x2_status0_actualSpeeds_dr_31p5G 32 18708 #define tx_x2_status0_actualSpeeds_dr_32p7G 33 18709 #define tx_x2_status0_actualSpeeds_dr_20G_SCR 34 18710 #define tx_x2_status0_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 18711 #define tx_x2_status0_actualSpeeds_dr_10G_DXGXS_SCR 36 18712 #define tx_x2_status0_actualSpeeds_dr_12G_R2 37 18713 #define tx_x2_status0_actualSpeeds_dr_10G_X2 38 18714 #define tx_x2_status0_actualSpeeds_dr_40G_KR4 39 18715 #define tx_x2_status0_actualSpeeds_dr_40G_CR4 40 18716 #define tx_x2_status0_actualSpeeds_dr_100G_CR10 41 18717 #define tx_x2_status0_actualSpeeds_dr_15p75G_DXGXS 44 18718 #define tx_x2_status0_actualSpeeds_dr_20G_KR2 57 18719 #define tx_x2_status0_actualSpeeds_dr_20G_CR2 58 18720 18721 /**************************************************************************** 18722 * Enums: tx_x2_status0_actualSpeedsMisc1 18723 */ 18724 #define tx_x2_status0_actualSpeedsMisc1_dr_2500BRCM_X1 16 18725 #define tx_x2_status0_actualSpeedsMisc1_dr_5000BRCM_X4 17 18726 #define tx_x2_status0_actualSpeedsMisc1_dr_6000BRCM_X4 18 18727 #define tx_x2_status0_actualSpeedsMisc1_dr_10GHiGig_X4 19 18728 #define tx_x2_status0_actualSpeedsMisc1_dr_10GBASE_CX4 20 18729 #define tx_x2_status0_actualSpeedsMisc1_dr_12GHiGig_X4 21 18730 #define tx_x2_status0_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 18731 #define tx_x2_status0_actualSpeedsMisc1_dr_13GHiGig_X4 23 18732 #define tx_x2_status0_actualSpeedsMisc1_dr_15GHiGig_X4 24 18733 #define tx_x2_status0_actualSpeedsMisc1_dr_16GHiGig_X4 25 18734 #define tx_x2_status0_actualSpeedsMisc1_dr_5000BRCM_X1 26 18735 #define tx_x2_status0_actualSpeedsMisc1_dr_6363BRCM_X1 27 18736 #define tx_x2_status0_actualSpeedsMisc1_dr_20GHiGig_X4 28 18737 #define tx_x2_status0_actualSpeedsMisc1_dr_21GHiGig_X4 29 18738 #define tx_x2_status0_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 18739 #define tx_x2_status0_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 18740 18741 /**************************************************************************** 18742 * Enums: tx_x2_status0_IndLaneModes 18743 */ 18744 #define tx_x2_status0_IndLaneModes_SWSDR_div2 0 18745 #define tx_x2_status0_IndLaneModes_SWSDR_div1 1 18746 #define tx_x2_status0_IndLaneModes_DWSDR_div2 2 18747 #define tx_x2_status0_IndLaneModes_DWSDR_div1 3 18748 18749 /**************************************************************************** 18750 * Enums: tx_x2_status0_prbsSelect 18751 */ 18752 #define tx_x2_status0_prbsSelect_prbs7 0 18753 #define tx_x2_status0_prbsSelect_prbs15 1 18754 #define tx_x2_status0_prbsSelect_prbs23 2 18755 #define tx_x2_status0_prbsSelect_prbs31 3 18756 18757 /**************************************************************************** 18758 * Enums: tx_x2_status0_vcoDivider 18759 */ 18760 #define tx_x2_status0_vcoDivider_div32 0 18761 #define tx_x2_status0_vcoDivider_div36 1 18762 #define tx_x2_status0_vcoDivider_div40 2 18763 #define tx_x2_status0_vcoDivider_div42 3 18764 #define tx_x2_status0_vcoDivider_div48 4 18765 #define tx_x2_status0_vcoDivider_div50 5 18766 #define tx_x2_status0_vcoDivider_div52 6 18767 #define tx_x2_status0_vcoDivider_div54 7 18768 #define tx_x2_status0_vcoDivider_div60 8 18769 #define tx_x2_status0_vcoDivider_div64 9 18770 #define tx_x2_status0_vcoDivider_div66 10 18771 #define tx_x2_status0_vcoDivider_div68 11 18772 #define tx_x2_status0_vcoDivider_div70 12 18773 #define tx_x2_status0_vcoDivider_div80 13 18774 #define tx_x2_status0_vcoDivider_div92 14 18775 #define tx_x2_status0_vcoDivider_div100 15 18776 18777 /**************************************************************************** 18778 * Enums: tx_x2_status0_refClkSelect 18779 */ 18780 #define tx_x2_status0_refClkSelect_clk_25MHz 0 18781 #define tx_x2_status0_refClkSelect_clk_100MHz 1 18782 #define tx_x2_status0_refClkSelect_clk_125MHz 2 18783 #define tx_x2_status0_refClkSelect_clk_156p25MHz 3 18784 #define tx_x2_status0_refClkSelect_clk_187p5MHz 4 18785 #define tx_x2_status0_refClkSelect_clk_161p25Mhz 5 18786 #define tx_x2_status0_refClkSelect_clk_50Mhz 6 18787 #define tx_x2_status0_refClkSelect_clk_106p25Mhz 7 18788 18789 /**************************************************************************** 18790 * Enums: tx_x2_status0_aerMMDdevTypeSelect 18791 */ 18792 #define tx_x2_status0_aerMMDdevTypeSelect_combo_core 0 18793 #define tx_x2_status0_aerMMDdevTypeSelect_PMA_PMD 1 18794 #define tx_x2_status0_aerMMDdevTypeSelect_PCS 3 18795 #define tx_x2_status0_aerMMDdevTypeSelect_PHY 4 18796 #define tx_x2_status0_aerMMDdevTypeSelect_DTE 5 18797 #define tx_x2_status0_aerMMDdevTypeSelect_CL73_AN 7 18798 18799 /**************************************************************************** 18800 * Enums: tx_x2_status0_aerMMDportSelect 18801 */ 18802 #define tx_x2_status0_aerMMDportSelect_ln0 0 18803 #define tx_x2_status0_aerMMDportSelect_ln1 1 18804 #define tx_x2_status0_aerMMDportSelect_ln2 2 18805 #define tx_x2_status0_aerMMDportSelect_ln3 3 18806 #define tx_x2_status0_aerMMDportSelect_BCST_ln0_1_2_3 511 18807 #define tx_x2_status0_aerMMDportSelect_BCST_ln0_1 512 18808 #define tx_x2_status0_aerMMDportSelect_BCST_ln2_3 513 18809 18810 /**************************************************************************** 18811 * Enums: tx_x2_status0_firmwareModeSelect 18812 */ 18813 #define tx_x2_status0_firmwareModeSelect_DEFAULT 0 18814 #define tx_x2_status0_firmwareModeSelect_SFP_OPT_LR 1 18815 #define tx_x2_status0_firmwareModeSelect_SFP_DAC 2 18816 #define tx_x2_status0_firmwareModeSelect_XLAUI 3 18817 #define tx_x2_status0_firmwareModeSelect_LONG_CH_6G 4 18818 18819 /**************************************************************************** 18820 * Enums: tx_x2_status0_tempIdxSelect 18821 */ 18822 #define tx_x2_status0_tempIdxSelect_LTE__22p9C 15 18823 #define tx_x2_status0_tempIdxSelect_LTE__12p6C 14 18824 #define tx_x2_status0_tempIdxSelect_LTE__3p0C 13 18825 #define tx_x2_status0_tempIdxSelect_LTE_6p7C 12 18826 #define tx_x2_status0_tempIdxSelect_LTE_16p4C 11 18827 #define tx_x2_status0_tempIdxSelect_LTE_26p6C 10 18828 #define tx_x2_status0_tempIdxSelect_LTE_36p3C 9 18829 #define tx_x2_status0_tempIdxSelect_LTE_46p0C 8 18830 #define tx_x2_status0_tempIdxSelect_LTE_56p2C 7 18831 #define tx_x2_status0_tempIdxSelect_LTE_65p9C 6 18832 #define tx_x2_status0_tempIdxSelect_LTE_75p6C 5 18833 #define tx_x2_status0_tempIdxSelect_LTE_85p3C 4 18834 #define tx_x2_status0_tempIdxSelect_LTE_95p5C 3 18835 #define tx_x2_status0_tempIdxSelect_LTE_105p2C 2 18836 #define tx_x2_status0_tempIdxSelect_LTE_114p9C 1 18837 #define tx_x2_status0_tempIdxSelect_LTE_125p1C 0 18838 18839 /**************************************************************************** 18840 * Enums: tx_x2_status0_port_mode 18841 */ 18842 #define tx_x2_status0_port_mode_QUAD_PORT 0 18843 #define tx_x2_status0_port_mode_TRI_1_PORT 1 18844 #define tx_x2_status0_port_mode_TRI_2_PORT 2 18845 #define tx_x2_status0_port_mode_DUAL_PORT 3 18846 #define tx_x2_status0_port_mode_SINGLE_PORT 4 18847 18848 /**************************************************************************** 18849 * Enums: tx_x2_status0_rev_letter_enum 18850 */ 18851 #define tx_x2_status0_rev_letter_enum_REV_A 0 18852 #define tx_x2_status0_rev_letter_enum_REV_B 1 18853 #define tx_x2_status0_rev_letter_enum_REV_C 2 18854 #define tx_x2_status0_rev_letter_enum_REV_D 3 18855 18856 /**************************************************************************** 18857 * Enums: tx_x2_status0_rev_number_enum 18858 */ 18859 #define tx_x2_status0_rev_number_enum_REV_0 0 18860 #define tx_x2_status0_rev_number_enum_REV_1 1 18861 #define tx_x2_status0_rev_number_enum_REV_2 2 18862 #define tx_x2_status0_rev_number_enum_REV_3 3 18863 #define tx_x2_status0_rev_number_enum_REV_4 4 18864 #define tx_x2_status0_rev_number_enum_REV_5 5 18865 #define tx_x2_status0_rev_number_enum_REV_6 6 18866 #define tx_x2_status0_rev_number_enum_REV_7 7 18867 18868 /**************************************************************************** 18869 * Enums: tx_x2_status0_bonding_enum 18870 */ 18871 #define tx_x2_status0_bonding_enum_WIRE_BOND 0 18872 #define tx_x2_status0_bonding_enum_FLIP_CHIP 1 18873 18874 /**************************************************************************** 18875 * Enums: tx_x2_status0_tech_process 18876 */ 18877 #define tx_x2_status0_tech_process_PROCESS_90NM 0 18878 #define tx_x2_status0_tech_process_PROCESS_65NM 1 18879 #define tx_x2_status0_tech_process_PROCESS_40NM 2 18880 #define tx_x2_status0_tech_process_PROCESS_28NM 3 18881 #define tx_x2_status0_tech_process_PROCESS_16NM 4 18882 18883 /**************************************************************************** 18884 * Enums: tx_x2_status0_model_num 18885 */ 18886 #define tx_x2_status0_model_num_SERDES_CL73 0 18887 #define tx_x2_status0_model_num_XGXS_16G 1 18888 #define tx_x2_status0_model_num_HYPERCORE 2 18889 #define tx_x2_status0_model_num_HYPERLITE 3 18890 #define tx_x2_status0_model_num_PCIE_G2_PIPE 4 18891 #define tx_x2_status0_model_num_SERDES_1p25GBd 5 18892 #define tx_x2_status0_model_num_SATA2 6 18893 #define tx_x2_status0_model_num_QSGMII 7 18894 #define tx_x2_status0_model_num_XGXS10G 8 18895 #define tx_x2_status0_model_num_WARPCORE 9 18896 #define tx_x2_status0_model_num_XFICORE 10 18897 #define tx_x2_status0_model_num_RXFI 11 18898 #define tx_x2_status0_model_num_WARPLITE 12 18899 #define tx_x2_status0_model_num_PENTACORE 13 18900 #define tx_x2_status0_model_num_ESM 14 18901 #define tx_x2_status0_model_num_QUAD_SGMII 15 18902 #define tx_x2_status0_model_num_WARPCORE_3 16 18903 #define tx_x2_status0_model_num_TSC 17 18904 #define tx_x2_status0_model_num_TSC4E 18 18905 #define tx_x2_status0_model_num_TSC12E 19 18906 #define tx_x2_status0_model_num_TSC4F 20 18907 #define tx_x2_status0_model_num_TSC4F_GEN2 21 18908 #define tx_x2_status0_model_num_XGXS_CL73_90NM 29 18909 #define tx_x2_status0_model_num_SERDES_CL73_90NM 30 18910 #define tx_x2_status0_model_num_WARPCORE3 32 18911 #define tx_x2_status0_model_num_WARPCORE4_TSC 33 18912 #define tx_x2_status0_model_num_RXAUI 34 18913 18914 /**************************************************************************** 18915 * Enums: tx_x2_status0_payload 18916 */ 18917 #define tx_x2_status0_payload_REPEAT_2_BYTES 0 18918 #define tx_x2_status0_payload_RAMPING 1 18919 #define tx_x2_status0_payload_CL48_CRPAT 2 18920 #define tx_x2_status0_payload_CL48_CJPAT 3 18921 #define tx_x2_status0_payload_CL36_LONG_CRPAT 4 18922 #define tx_x2_status0_payload_CL36_SHORT_CRPAT 5 18923 18924 /**************************************************************************** 18925 * Enums: tx_x2_status0_sc 18926 */ 18927 #define tx_x2_status0_sc_S_10G_CR1 0 18928 #define tx_x2_status0_sc_S_10G_KR1 1 18929 #define tx_x2_status0_sc_S_10G_X1 2 18930 #define tx_x2_status0_sc_S_10G_HG2_CR1 4 18931 #define tx_x2_status0_sc_S_10G_HG2_KR1 5 18932 #define tx_x2_status0_sc_S_10G_HG2_X1 6 18933 #define tx_x2_status0_sc_S_20G_CR1 8 18934 #define tx_x2_status0_sc_S_20G_KR1 9 18935 #define tx_x2_status0_sc_S_20G_X1 10 18936 #define tx_x2_status0_sc_S_20G_HG2_CR1 12 18937 #define tx_x2_status0_sc_S_20G_HG2_KR1 13 18938 #define tx_x2_status0_sc_S_20G_HG2_X1 14 18939 #define tx_x2_status0_sc_S_25G_CR1 16 18940 #define tx_x2_status0_sc_S_25G_KR1 17 18941 #define tx_x2_status0_sc_S_25G_X1 18 18942 #define tx_x2_status0_sc_S_25G_HG2_CR1 20 18943 #define tx_x2_status0_sc_S_25G_HG2_KR1 21 18944 #define tx_x2_status0_sc_S_25G_HG2_X1 22 18945 #define tx_x2_status0_sc_S_20G_CR2 24 18946 #define tx_x2_status0_sc_S_20G_KR2 25 18947 #define tx_x2_status0_sc_S_20G_X2 26 18948 #define tx_x2_status0_sc_S_20G_HG2_CR2 28 18949 #define tx_x2_status0_sc_S_20G_HG2_KR2 29 18950 #define tx_x2_status0_sc_S_20G_HG2_X2 30 18951 #define tx_x2_status0_sc_S_40G_CR2 32 18952 #define tx_x2_status0_sc_S_40G_KR2 33 18953 #define tx_x2_status0_sc_S_40G_X2 34 18954 #define tx_x2_status0_sc_S_40G_HG2_CR2 36 18955 #define tx_x2_status0_sc_S_40G_HG2_KR2 37 18956 #define tx_x2_status0_sc_S_40G_HG2_X2 38 18957 #define tx_x2_status0_sc_S_40G_CR4 40 18958 #define tx_x2_status0_sc_S_40G_KR4 41 18959 #define tx_x2_status0_sc_S_40G_X4 42 18960 #define tx_x2_status0_sc_S_40G_HG2_CR4 44 18961 #define tx_x2_status0_sc_S_40G_HG2_KR4 45 18962 #define tx_x2_status0_sc_S_40G_HG2_X4 46 18963 #define tx_x2_status0_sc_S_50G_CR2 48 18964 #define tx_x2_status0_sc_S_50G_KR2 49 18965 #define tx_x2_status0_sc_S_50G_X2 50 18966 #define tx_x2_status0_sc_S_50G_HG2_CR2 52 18967 #define tx_x2_status0_sc_S_50G_HG2_KR2 53 18968 #define tx_x2_status0_sc_S_50G_HG2_X2 54 18969 #define tx_x2_status0_sc_S_50G_CR4 56 18970 #define tx_x2_status0_sc_S_50G_KR4 57 18971 #define tx_x2_status0_sc_S_50G_X4 58 18972 #define tx_x2_status0_sc_S_50G_HG2_CR4 60 18973 #define tx_x2_status0_sc_S_50G_HG2_KR4 61 18974 #define tx_x2_status0_sc_S_50G_HG2_X4 62 18975 #define tx_x2_status0_sc_S_100G_CR4 64 18976 #define tx_x2_status0_sc_S_100G_KR4 65 18977 #define tx_x2_status0_sc_S_100G_X4 66 18978 #define tx_x2_status0_sc_S_100G_HG2_CR4 68 18979 #define tx_x2_status0_sc_S_100G_HG2_KR4 69 18980 #define tx_x2_status0_sc_S_100G_HG2_X4 70 18981 #define tx_x2_status0_sc_S_CL73_20GVCO 72 18982 #define tx_x2_status0_sc_S_CL73_25GVCO 80 18983 #define tx_x2_status0_sc_S_CL36_20GVCO 88 18984 #define tx_x2_status0_sc_S_CL36_25GVCO 96 18985 #define tx_x2_status0_sc_S_25G_CR_IEEE 112 18986 #define tx_x2_status0_sc_S_25G_CRS_IEEE 113 18987 #define tx_x2_status0_sc_S_25G_KR_IEEE 114 18988 #define tx_x2_status0_sc_S_25G_KRS_IEEE 115 18989 18990 /**************************************************************************** 18991 * Enums: tx_x2_status0_t_fifo_modes 18992 */ 18993 #define tx_x2_status0_t_fifo_modes_T_FIFO_INSERT_NO_AM 0 18994 #define tx_x2_status0_t_fifo_modes_T_FIFO_INSERT_4_AM 1 18995 #define tx_x2_status0_t_fifo_modes_T_FIFO_INSERT_20_AM 2 18996 #define tx_x2_status0_t_fifo_modes_T_FIFO_INSERT_2_AM 3 18997 18998 /**************************************************************************** 18999 * Enums: tx_x2_status0_t_enc_modes 19000 */ 19001 #define tx_x2_status0_t_enc_modes_T_ENC_MODE_BYPASS 0 19002 #define tx_x2_status0_t_enc_modes_T_ENC_MODE_CL49 1 19003 #define tx_x2_status0_t_enc_modes_T_ENC_MODE_CL82 2 19004 19005 /**************************************************************************** 19006 * Enums: tx_x2_status0_btmx_mode 19007 */ 19008 #define tx_x2_status0_btmx_mode_BS_BTMX_MODE_1to1 0 19009 #define tx_x2_status0_btmx_mode_BS_BTMX_MODE_2to1 1 19010 #define tx_x2_status0_btmx_mode_BS_BTMX_MODE_5to1 2 19011 19012 /**************************************************************************** 19013 * Enums: tx_x2_status0_t_type_cl82 19014 */ 19015 #define tx_x2_status0_t_type_cl82_T_TYPE_B1 5 19016 #define tx_x2_status0_t_type_cl82_T_TYPE_C 4 19017 #define tx_x2_status0_t_type_cl82_T_TYPE_S 3 19018 #define tx_x2_status0_t_type_cl82_T_TYPE_T 2 19019 #define tx_x2_status0_t_type_cl82_T_TYPE_D 1 19020 #define tx_x2_status0_t_type_cl82_T_TYPE_E 0 19021 19022 /**************************************************************************** 19023 * Enums: tx_x2_status0_txsm_state_cl82 19024 */ 19025 #define tx_x2_status0_txsm_state_cl82_TX_HIG_END 6 19026 #define tx_x2_status0_txsm_state_cl82_TX_HIG_START 5 19027 #define tx_x2_status0_txsm_state_cl82_TX_E 4 19028 #define tx_x2_status0_txsm_state_cl82_TX_T 3 19029 #define tx_x2_status0_txsm_state_cl82_TX_D 2 19030 #define tx_x2_status0_txsm_state_cl82_TX_C 1 19031 #define tx_x2_status0_txsm_state_cl82_TX_INIT 0 19032 19033 /**************************************************************************** 19034 * Enums: tx_x2_status0_ltxsm_state_cl82 19035 */ 19036 #define tx_x2_status0_ltxsm_state_cl82_TX_HIG_END 64 19037 #define tx_x2_status0_ltxsm_state_cl82_TX_HIG_START 32 19038 #define tx_x2_status0_ltxsm_state_cl82_TX_E 16 19039 #define tx_x2_status0_ltxsm_state_cl82_TX_T 8 19040 #define tx_x2_status0_ltxsm_state_cl82_TX_D 4 19041 #define tx_x2_status0_ltxsm_state_cl82_TX_C 2 19042 #define tx_x2_status0_ltxsm_state_cl82_TX_INIT 1 19043 19044 /**************************************************************************** 19045 * Enums: tx_x2_status0_r_type_coded_cl82 19046 */ 19047 #define tx_x2_status0_r_type_coded_cl82_R_TYPE_B1 32 19048 #define tx_x2_status0_r_type_coded_cl82_R_TYPE_C 16 19049 #define tx_x2_status0_r_type_coded_cl82_R_TYPE_S 8 19050 #define tx_x2_status0_r_type_coded_cl82_R_TYPE_T 4 19051 #define tx_x2_status0_r_type_coded_cl82_R_TYPE_D 2 19052 #define tx_x2_status0_r_type_coded_cl82_R_TYPE_E 1 19053 19054 /**************************************************************************** 19055 * Enums: tx_x2_status0_rxsm_state_cl82 19056 */ 19057 #define tx_x2_status0_rxsm_state_cl82_RX_HIG_END 64 19058 #define tx_x2_status0_rxsm_state_cl82_RX_HIG_START 32 19059 #define tx_x2_status0_rxsm_state_cl82_RX_E 16 19060 #define tx_x2_status0_rxsm_state_cl82_RX_T 8 19061 #define tx_x2_status0_rxsm_state_cl82_RX_D 4 19062 #define tx_x2_status0_rxsm_state_cl82_RX_C 2 19063 #define tx_x2_status0_rxsm_state_cl82_RX_INIT 1 19064 19065 /**************************************************************************** 19066 * Enums: tx_x2_status0_deskew_state 19067 */ 19068 #define tx_x2_status0_deskew_state_ALIGN_ACQUIRED 2 19069 #define tx_x2_status0_deskew_state_LOSS_OF_ALIGNMENT 1 19070 19071 /**************************************************************************** 19072 * Enums: tx_x2_status0_os_mode_enum 19073 */ 19074 #define tx_x2_status0_os_mode_enum_OS_MODE_1 0 19075 #define tx_x2_status0_os_mode_enum_OS_MODE_2 1 19076 #define tx_x2_status0_os_mode_enum_OS_MODE_4 2 19077 #define tx_x2_status0_os_mode_enum_OS_MODE_16p5 8 19078 #define tx_x2_status0_os_mode_enum_OS_MODE_20p625 12 19079 19080 /**************************************************************************** 19081 * Enums: tx_x2_status0_scr_modes 19082 */ 19083 #define tx_x2_status0_scr_modes_T_SCR_MODE_BYPASS 0 19084 #define tx_x2_status0_scr_modes_T_SCR_MODE_CL49 1 19085 #define tx_x2_status0_scr_modes_T_SCR_MODE_40G_2_LANE 2 19086 #define tx_x2_status0_scr_modes_T_SCR_MODE_100G 3 19087 #define tx_x2_status0_scr_modes_T_SCR_MODE_20G 4 19088 #define tx_x2_status0_scr_modes_T_SCR_MODE_40G_4_LANE 5 19089 19090 /**************************************************************************** 19091 * Enums: tx_x2_status0_descr_modes 19092 */ 19093 #define tx_x2_status0_descr_modes_R_DESCR_MODE_BYPASS 0 19094 #define tx_x2_status0_descr_modes_R_DESCR_MODE_CL49 1 19095 #define tx_x2_status0_descr_modes_R_DESCR_MODE_CL82 2 19096 19097 /**************************************************************************** 19098 * Enums: tx_x2_status0_r_dec_tl_mode 19099 */ 19100 #define tx_x2_status0_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 19101 #define tx_x2_status0_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 19102 #define tx_x2_status0_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 19103 19104 /**************************************************************************** 19105 * Enums: tx_x2_status0_r_dec_fsm_mode 19106 */ 19107 #define tx_x2_status0_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 19108 #define tx_x2_status0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 19109 #define tx_x2_status0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 19110 19111 /**************************************************************************** 19112 * Enums: tx_x2_status0_r_deskew_mode 19113 */ 19114 #define tx_x2_status0_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 19115 #define tx_x2_status0_r_deskew_mode_R_DESKEW_MODE_20G 1 19116 #define tx_x2_status0_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 19117 #define tx_x2_status0_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 19118 #define tx_x2_status0_r_deskew_mode_R_DESKEW_MODE_100G 4 19119 #define tx_x2_status0_r_deskew_mode_R_DESKEW_MODE_CL49 5 19120 #define tx_x2_status0_r_deskew_mode_R_DESKEW_MODE_CL91_QUAD 6 19121 #define tx_x2_status0_r_deskew_mode_R_DESKEW_MODE_CL91_SINGLE_BRCM 7 19122 #define tx_x2_status0_r_deskew_mode_R_DESKEW_MODE_CL91_DUAL_BRCM 8 19123 #define tx_x2_status0_r_deskew_mode_R_DESKEW_MODE_CL91_FC 9 19124 19125 /**************************************************************************** 19126 * Enums: tx_x2_status0_bs_dist_modes 19127 */ 19128 #define tx_x2_status0_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 19129 #define tx_x2_status0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 19130 #define tx_x2_status0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 19131 #define tx_x2_status0_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 19132 19133 /**************************************************************************** 19134 * Enums: tx_x2_status0_cl49_t_type 19135 */ 19136 #define tx_x2_status0_cl49_t_type_BAD_T_TYPE 15 19137 #define tx_x2_status0_cl49_t_type_T_TYPE_B0 11 19138 #define tx_x2_status0_cl49_t_type_T_TYPE_OB 10 19139 #define tx_x2_status0_cl49_t_type_T_TYPE_B1 9 19140 #define tx_x2_status0_cl49_t_type_T_TYPE_DB 8 19141 #define tx_x2_status0_cl49_t_type_T_TYPE_FC 7 19142 #define tx_x2_status0_cl49_t_type_T_TYPE_TB 6 19143 #define tx_x2_status0_cl49_t_type_T_TYPE_LI 5 19144 #define tx_x2_status0_cl49_t_type_T_TYPE_C 4 19145 #define tx_x2_status0_cl49_t_type_T_TYPE_S 3 19146 #define tx_x2_status0_cl49_t_type_T_TYPE_T 2 19147 #define tx_x2_status0_cl49_t_type_T_TYPE_D 1 19148 #define tx_x2_status0_cl49_t_type_T_TYPE_E 0 19149 19150 /**************************************************************************** 19151 * Enums: tx_x2_status0_cl49_txsm_states 19152 */ 19153 #define tx_x2_status0_cl49_txsm_states_TX_HIG_END 7 19154 #define tx_x2_status0_cl49_txsm_states_TX_HIG_START 6 19155 #define tx_x2_status0_cl49_txsm_states_TX_LI 5 19156 #define tx_x2_status0_cl49_txsm_states_TX_E 4 19157 #define tx_x2_status0_cl49_txsm_states_TX_T 3 19158 #define tx_x2_status0_cl49_txsm_states_TX_D 2 19159 #define tx_x2_status0_cl49_txsm_states_TX_C 1 19160 #define tx_x2_status0_cl49_txsm_states_TX_INIT 0 19161 19162 /**************************************************************************** 19163 * Enums: tx_x2_status0_cl49_ltxsm_states 19164 */ 19165 #define tx_x2_status0_cl49_ltxsm_states_TX_HIG_END 128 19166 #define tx_x2_status0_cl49_ltxsm_states_TX_HIG_START 64 19167 #define tx_x2_status0_cl49_ltxsm_states_TX_LI 32 19168 #define tx_x2_status0_cl49_ltxsm_states_TX_E 16 19169 #define tx_x2_status0_cl49_ltxsm_states_TX_T 8 19170 #define tx_x2_status0_cl49_ltxsm_states_TX_D 4 19171 #define tx_x2_status0_cl49_ltxsm_states_TX_C 2 19172 #define tx_x2_status0_cl49_ltxsm_states_TX_INIT 1 19173 19174 /**************************************************************************** 19175 * Enums: tx_x2_status0_burst_error_mode 19176 */ 19177 #define tx_x2_status0_burst_error_mode_BURST_ERROR_11_BITS 0 19178 #define tx_x2_status0_burst_error_mode_BURST_ERROR_16_BITS 1 19179 #define tx_x2_status0_burst_error_mode_BURST_ERROR_17_BITS 2 19180 #define tx_x2_status0_burst_error_mode_BURST_ERROR_18_BITS 3 19181 #define tx_x2_status0_burst_error_mode_BURST_ERROR_19_BITS 4 19182 #define tx_x2_status0_burst_error_mode_BURST_ERROR_20_BITS 5 19183 #define tx_x2_status0_burst_error_mode_BURST_ERROR_21_BITS 6 19184 #define tx_x2_status0_burst_error_mode_BURST_ERROR_22_BITS 7 19185 #define tx_x2_status0_burst_error_mode_BURST_ERROR_23_BITS 8 19186 #define tx_x2_status0_burst_error_mode_BURST_ERROR_24_BITS 9 19187 #define tx_x2_status0_burst_error_mode_BURST_ERROR_25_BITS 10 19188 #define tx_x2_status0_burst_error_mode_BURST_ERROR_26_BITS 11 19189 #define tx_x2_status0_burst_error_mode_BURST_ERROR_27_BITS 12 19190 #define tx_x2_status0_burst_error_mode_BURST_ERROR_28_BITS 13 19191 #define tx_x2_status0_burst_error_mode_BURST_ERROR_29_BITS 14 19192 #define tx_x2_status0_burst_error_mode_BURST_ERROR_30_BITS 15 19193 #define tx_x2_status0_burst_error_mode_BURST_ERROR_31_BITS 16 19194 #define tx_x2_status0_burst_error_mode_BURST_ERROR_32_BITS 17 19195 #define tx_x2_status0_burst_error_mode_BURST_ERROR_33_BITS 18 19196 #define tx_x2_status0_burst_error_mode_BURST_ERROR_34_BITS 19 19197 #define tx_x2_status0_burst_error_mode_BURST_ERROR_35_BITS 20 19198 #define tx_x2_status0_burst_error_mode_BURST_ERROR_36_BITS 21 19199 #define tx_x2_status0_burst_error_mode_BURST_ERROR_37_BITS 22 19200 #define tx_x2_status0_burst_error_mode_BURST_ERROR_38_BITS 23 19201 #define tx_x2_status0_burst_error_mode_BURST_ERROR_39_BITS 24 19202 #define tx_x2_status0_burst_error_mode_BURST_ERROR_40_BITS 25 19203 #define tx_x2_status0_burst_error_mode_BURST_ERROR_41_BITS 26 19204 19205 /**************************************************************************** 19206 * Enums: tx_x2_status0_bermon_state 19207 */ 19208 #define tx_x2_status0_bermon_state_HI_BER 4 19209 #define tx_x2_status0_bermon_state_GOOD_BER 3 19210 #define tx_x2_status0_bermon_state_BER_TEST_SH 2 19211 #define tx_x2_status0_bermon_state_START_TIMER 1 19212 #define tx_x2_status0_bermon_state_BER_MT_INIT 0 19213 19214 /**************************************************************************** 19215 * Enums: tx_x2_status0_rxsm_state_cl49 19216 */ 19217 #define tx_x2_status0_rxsm_state_cl49_RX_HIG_END 128 19218 #define tx_x2_status0_rxsm_state_cl49_RX_HIG_START 64 19219 #define tx_x2_status0_rxsm_state_cl49_RX_LI 32 19220 #define tx_x2_status0_rxsm_state_cl49_RX_E 16 19221 #define tx_x2_status0_rxsm_state_cl49_RX_T 8 19222 #define tx_x2_status0_rxsm_state_cl49_RX_D 4 19223 #define tx_x2_status0_rxsm_state_cl49_RX_C 2 19224 #define tx_x2_status0_rxsm_state_cl49_RX_INIT 1 19225 19226 /**************************************************************************** 19227 * Enums: tx_x2_status0_r_type 19228 */ 19229 #define tx_x2_status0_r_type_BAD_R_TYPE 15 19230 #define tx_x2_status0_r_type_R_TYPE_B0 11 19231 #define tx_x2_status0_r_type_R_TYPE_OB 10 19232 #define tx_x2_status0_r_type_R_TYPE_B1 9 19233 #define tx_x2_status0_r_type_R_TYPE_DB 8 19234 #define tx_x2_status0_r_type_R_TYPE_FC 7 19235 #define tx_x2_status0_r_type_R_TYPE_TB 6 19236 #define tx_x2_status0_r_type_R_TYPE_LI 5 19237 #define tx_x2_status0_r_type_R_TYPE_C 4 19238 #define tx_x2_status0_r_type_R_TYPE_S 3 19239 #define tx_x2_status0_r_type_R_TYPE_T 2 19240 #define tx_x2_status0_r_type_R_TYPE_D 1 19241 #define tx_x2_status0_r_type_R_TYPE_E 0 19242 19243 /**************************************************************************** 19244 * Enums: tx_x2_status0_am_lock_state 19245 */ 19246 #define tx_x2_status0_am_lock_state_INVALID_AM 512 19247 #define tx_x2_status0_am_lock_state_GOOD_AM 256 19248 #define tx_x2_status0_am_lock_state_COMP_AM 128 19249 #define tx_x2_status0_am_lock_state_TIMER_2 64 19250 #define tx_x2_status0_am_lock_state_AM_2_GOOD 32 19251 #define tx_x2_status0_am_lock_state_COMP_2ND 16 19252 #define tx_x2_status0_am_lock_state_TIMER_1 8 19253 #define tx_x2_status0_am_lock_state_FIND_1ST 4 19254 #define tx_x2_status0_am_lock_state_AM_RESET_CNT 2 19255 #define tx_x2_status0_am_lock_state_AM_LOCK_INIT 1 19256 19257 /**************************************************************************** 19258 * Enums: tx_x2_status0_msg_selector 19259 */ 19260 #define tx_x2_status0_msg_selector_RESERVED 0 19261 #define tx_x2_status0_msg_selector_VALUE_802p3 1 19262 #define tx_x2_status0_msg_selector_VALUE_802p9 2 19263 #define tx_x2_status0_msg_selector_VALUE_802p5 3 19264 #define tx_x2_status0_msg_selector_VALUE_1394 4 19265 19266 /**************************************************************************** 19267 * Enums: tx_x2_status0_synce_enum 19268 */ 19269 #define tx_x2_status0_synce_enum_SYNCE_NO_DIV 0 19270 #define tx_x2_status0_synce_enum_SYNCE_DIV_7 1 19271 #define tx_x2_status0_synce_enum_SYNCE_DIV_11 2 19272 19273 /**************************************************************************** 19274 * Enums: tx_x2_status0_synce_enum_stage0 19275 */ 19276 #define tx_x2_status0_synce_enum_stage0_SYNCE_NO_DIV 0 19277 #define tx_x2_status0_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 19278 #define tx_x2_status0_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 19279 19280 /**************************************************************************** 19281 * Enums: tx_x2_status0_cl91_sync_state 19282 */ 19283 #define tx_x2_status0_cl91_sync_state_FIND_1ST 0 19284 #define tx_x2_status0_cl91_sync_state_COUNT_NEXT 1 19285 #define tx_x2_status0_cl91_sync_state_COMP_2ND 2 19286 #define tx_x2_status0_cl91_sync_state_TWO_GOOD 3 19287 19288 /**************************************************************************** 19289 * Enums: tx_x2_status0_cl91_algn_state 19290 */ 19291 #define tx_x2_status0_cl91_algn_state_LOSS_OF_ALIGNMENT 0 19292 #define tx_x2_status0_cl91_algn_state_DESKEW 1 19293 #define tx_x2_status0_cl91_algn_state_DESKEW_FAIL 2 19294 #define tx_x2_status0_cl91_algn_state_ALIGN_ACQUIRED 3 19295 #define tx_x2_status0_cl91_algn_state_CW_GOOD 4 19296 #define tx_x2_status0_cl91_algn_state_CW_BAD 5 19297 #define tx_x2_status0_cl91_algn_state_THREE_BAD 6 19298 19299 /**************************************************************************** 19300 * Enums: tx_x2_status0_fec_sel_override 19301 */ 19302 #define tx_x2_status0_fec_sel_override_NO_OVERRIDE 0 19303 #define tx_x2_status0_fec_sel_override_NO_FEC 1 19304 #define tx_x2_status0_fec_sel_override_FEC_CL74 2 19305 #define tx_x2_status0_fec_sel_override_FEC_CL91 3 19306 19307 /**************************************************************************** 19308 * Enums: tx_x2_status0_cl91_blksync_mode 19309 */ 19310 #define tx_x2_status0_cl91_blksync_mode_R_BLKSYNC_NO_CL91_FEC 0 19311 #define tx_x2_status0_cl91_blksync_mode_R_BLKSYNC_CL91_QUAD_LANE_FEC 1 19312 #define tx_x2_status0_cl91_blksync_mode_R_BLKSYNC_CL91_DUAL_LANE_FEC 2 19313 #define tx_x2_status0_cl91_blksync_mode_R_BLKSYNC_CL91_SINGLE_LANE_FEC 3 19314 #define tx_x2_status0_cl91_blksync_mode_R_BLKSYNC_CL91_FC_FEC 4 19315 19316 /**************************************************************************** 19317 * Enums: tx_x2_status0_r_merge_mode 19318 */ 19319 #define tx_x2_status0_r_merge_mode_R_MERGE_MODE_BYPASS 0 19320 #define tx_x2_status0_r_merge_mode_R_MERGE_MODE_CL91_FC 1 19321 #define tx_x2_status0_r_merge_mode_R_MERGE_MODE_CL91_SINGLE_LANE 2 19322 #define tx_x2_status0_r_merge_mode_R_MERGE_MODE_CL91_DUAL_LANE 3 19323 #define tx_x2_status0_r_merge_mode_R_MERGE_MODE_CL91_QUAD_LANE 4 19324 19325 /**************************************************************************** 19326 * Enums: tx_x2_status0_r_tc_mode 19327 */ 19328 #define tx_x2_status0_r_tc_mode_R_TC_MODE_SINGLE 0 19329 #define tx_x2_status0_r_tc_mode_R_TC_MODE_DUAL 1 19330 #define tx_x2_status0_r_tc_mode_R_TC_MODE_QUAD 2 19331 19332 /**************************************************************************** 19333 * Enums: tx_x2_status0_r_tc_out_mode 19334 */ 19335 #define tx_x2_status0_r_tc_out_mode_R_TC_OUT_MODE_SINGLE 0 19336 #define tx_x2_status0_r_tc_out_mode_R_TC_OUT_MODE_DUAL 1 19337 #define tx_x2_status0_r_tc_out_mode_R_TC_OUT_MODE_QUAD 2 19338 19339 /**************************************************************************** 19340 * Enums: tx_x2_status0_cl91_fec_mode 19341 */ 19342 #define tx_x2_status0_cl91_fec_mode_NO_CL91_FEC 0 19343 #define tx_x2_status0_cl91_fec_mode_CL91_SINGLE_LANE_FC 1 19344 #define tx_x2_status0_cl91_fec_mode_CL91_SINGLE_LANE_BRCM_PROP 2 19345 #define tx_x2_status0_cl91_fec_mode_CL91_DUAL_LANE_BRCM_PROP 3 19346 #define tx_x2_status0_cl91_fec_mode_CL91_QUAD_LANE 4 19347 #define tx_x2_status0_cl91_fec_mode_IEEE_25G_CL91_SINGLE_LANE 5 19348 19349 /**************************************************************************** 19350 * Enums: tx_x2_status0_am_spacing_mul 19351 */ 19352 #define tx_x2_status0_am_spacing_mul_AM_SPACING_MUL_2 0 19353 #define tx_x2_status0_am_spacing_mul_AM_SPACING_MUL_4 1 19354 #define tx_x2_status0_am_spacing_mul_AM_SPACING_MUL_5 2 19355 #define tx_x2_status0_am_spacing_mul_AM_SPACING_MUL_20 3 19356 19357 /**************************************************************************** 19358 * Enums: tx_x4_control0_cl36TxEEEStates_l 19359 */ 19360 #define tx_x4_control0_cl36TxEEEStates_l_TX_REFRESH 8 19361 #define tx_x4_control0_cl36TxEEEStates_l_TX_QUIET 4 19362 #define tx_x4_control0_cl36TxEEEStates_l_TX_SLEEP 2 19363 #define tx_x4_control0_cl36TxEEEStates_l_TX_ACTIVE 1 19364 19365 /**************************************************************************** 19366 * Enums: tx_x4_control0_cl36TxEEEStates_c 19367 */ 19368 #define tx_x4_control0_cl36TxEEEStates_c_TX_REFRESH 3 19369 #define tx_x4_control0_cl36TxEEEStates_c_TX_QUIET 2 19370 #define tx_x4_control0_cl36TxEEEStates_c_TX_SLEEP 1 19371 #define tx_x4_control0_cl36TxEEEStates_c_TX_ACTIVE 0 19372 19373 /**************************************************************************** 19374 * Enums: tx_x4_control0_cl49TxEEEStates_l 19375 */ 19376 #define tx_x4_control0_cl49TxEEEStates_l_SCR_RESET_2 64 19377 #define tx_x4_control0_cl49TxEEEStates_l_SCR_RESET_1 32 19378 #define tx_x4_control0_cl49TxEEEStates_l_TX_WAKE 16 19379 #define tx_x4_control0_cl49TxEEEStates_l_TX_REFRESH 8 19380 #define tx_x4_control0_cl49TxEEEStates_l_TX_QUIET 4 19381 #define tx_x4_control0_cl49TxEEEStates_l_TX_SLEEP 2 19382 #define tx_x4_control0_cl49TxEEEStates_l_TX_ACTIVE 1 19383 19384 /**************************************************************************** 19385 * Enums: tx_x4_control0_fec_req_enum 19386 */ 19387 #define tx_x4_control0_fec_req_enum_FEC_not_supported 0 19388 #define tx_x4_control0_fec_req_enum_FEC_supported_but_not_requested 1 19389 #define tx_x4_control0_fec_req_enum_invalid_setting 2 19390 #define tx_x4_control0_fec_req_enum_FEC_supported_and_requested 3 19391 19392 /**************************************************************************** 19393 * Enums: tx_x4_control0_cl73_pause_enum 19394 */ 19395 #define tx_x4_control0_cl73_pause_enum_No_PAUSE_ability 0 19396 #define tx_x4_control0_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 19397 #define tx_x4_control0_cl73_pause_enum_Symmetric_PAUSE_ability 1 19398 #define tx_x4_control0_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 19399 19400 /**************************************************************************** 19401 * Enums: tx_x4_control0_cl49TxEEEStates_c 19402 */ 19403 #define tx_x4_control0_cl49TxEEEStates_c_SCR_RESET_2 6 19404 #define tx_x4_control0_cl49TxEEEStates_c_SCR_RESET_1 5 19405 #define tx_x4_control0_cl49TxEEEStates_c_TX_WAKE 4 19406 #define tx_x4_control0_cl49TxEEEStates_c_TX_REFRESH 3 19407 #define tx_x4_control0_cl49TxEEEStates_c_TX_QUIET 2 19408 #define tx_x4_control0_cl49TxEEEStates_c_TX_SLEEP 1 19409 #define tx_x4_control0_cl49TxEEEStates_c_TX_ACTIVE 0 19410 19411 /**************************************************************************** 19412 * Enums: tx_x4_control0_cl36RxEEEStates_l 19413 */ 19414 #define tx_x4_control0_cl36RxEEEStates_l_RX_LINK_FAIL 32 19415 #define tx_x4_control0_cl36RxEEEStates_l_RX_WTF 16 19416 #define tx_x4_control0_cl36RxEEEStates_l_RX_WAKE 8 19417 #define tx_x4_control0_cl36RxEEEStates_l_RX_QUIET 4 19418 #define tx_x4_control0_cl36RxEEEStates_l_RX_SLEEP 2 19419 #define tx_x4_control0_cl36RxEEEStates_l_RX_ACTIVE 1 19420 19421 /**************************************************************************** 19422 * Enums: tx_x4_control0_cl36RxEEEStates_c 19423 */ 19424 #define tx_x4_control0_cl36RxEEEStates_c_RX_LINK_FAIL 5 19425 #define tx_x4_control0_cl36RxEEEStates_c_RX_WTF 4 19426 #define tx_x4_control0_cl36RxEEEStates_c_RX_WAKE 3 19427 #define tx_x4_control0_cl36RxEEEStates_c_RX_QUIET 2 19428 #define tx_x4_control0_cl36RxEEEStates_c_RX_SLEEP 1 19429 #define tx_x4_control0_cl36RxEEEStates_c_RX_ACTIVE 0 19430 19431 /**************************************************************************** 19432 * Enums: tx_x4_control0_cl49RxEEEStates_l 19433 */ 19434 #define tx_x4_control0_cl49RxEEEStates_l_RX_LINK_FAIL 32 19435 #define tx_x4_control0_cl49RxEEEStates_l_RX_WTF 16 19436 #define tx_x4_control0_cl49RxEEEStates_l_RX_WAKE 8 19437 #define tx_x4_control0_cl49RxEEEStates_l_RX_QUIET 4 19438 #define tx_x4_control0_cl49RxEEEStates_l_RX_SLEEP 2 19439 #define tx_x4_control0_cl49RxEEEStates_l_RX_ACTIVE 1 19440 19441 /**************************************************************************** 19442 * Enums: tx_x4_control0_cl49RxEEEStates_c 19443 */ 19444 #define tx_x4_control0_cl49RxEEEStates_c_RX_LINK_FAIL 5 19445 #define tx_x4_control0_cl49RxEEEStates_c_RX_WTF 4 19446 #define tx_x4_control0_cl49RxEEEStates_c_RX_WAKE 3 19447 #define tx_x4_control0_cl49RxEEEStates_c_RX_QUIET 2 19448 #define tx_x4_control0_cl49RxEEEStates_c_RX_SLEEP 1 19449 #define tx_x4_control0_cl49RxEEEStates_c_RX_ACTIVE 0 19450 19451 /**************************************************************************** 19452 * Enums: tx_x4_control0_cl48TxEEEStates_l 19453 */ 19454 #define tx_x4_control0_cl48TxEEEStates_l_TX_REFRESH 8 19455 #define tx_x4_control0_cl48TxEEEStates_l_TX_QUIET 4 19456 #define tx_x4_control0_cl48TxEEEStates_l_TX_SLEEP 2 19457 #define tx_x4_control0_cl48TxEEEStates_l_TX_ACTIVE 1 19458 19459 /**************************************************************************** 19460 * Enums: tx_x4_control0_cl48TxEEEStates_c 19461 */ 19462 #define tx_x4_control0_cl48TxEEEStates_c_TX_REFRESH 3 19463 #define tx_x4_control0_cl48TxEEEStates_c_TX_QUIET 2 19464 #define tx_x4_control0_cl48TxEEEStates_c_TX_SLEEP 1 19465 #define tx_x4_control0_cl48TxEEEStates_c_TX_ACTIVE 0 19466 19467 /**************************************************************************** 19468 * Enums: tx_x4_control0_cl48RxEEEStates_l 19469 */ 19470 #define tx_x4_control0_cl48RxEEEStates_l_RX_LINK_FAIL 32 19471 #define tx_x4_control0_cl48RxEEEStates_l_RX_WAKE 16 19472 #define tx_x4_control0_cl48RxEEEStates_l_RX_QUIET 8 19473 #define tx_x4_control0_cl48RxEEEStates_l_RX_DEACT 4 19474 #define tx_x4_control0_cl48RxEEEStates_l_RX_SLEEP 2 19475 #define tx_x4_control0_cl48RxEEEStates_l_RX_ACTIVE 1 19476 19477 /**************************************************************************** 19478 * Enums: tx_x4_control0_cl48RxEEEStates_c 19479 */ 19480 #define tx_x4_control0_cl48RxEEEStates_c_RX_LINK_FAIL 5 19481 #define tx_x4_control0_cl48RxEEEStates_c_RX_WAKE 4 19482 #define tx_x4_control0_cl48RxEEEStates_c_RX_QUIET 3 19483 #define tx_x4_control0_cl48RxEEEStates_c_RX_DEACT 2 19484 #define tx_x4_control0_cl48RxEEEStates_c_RX_SLEEP 1 19485 #define tx_x4_control0_cl48RxEEEStates_c_RX_ACTIVE 0 19486 19487 /**************************************************************************** 19488 * Enums: tx_x4_control0_IQP_Options 19489 */ 19490 #define tx_x4_control0_IQP_Options_i50uA 0 19491 #define tx_x4_control0_IQP_Options_i100uA 1 19492 #define tx_x4_control0_IQP_Options_i150uA 2 19493 #define tx_x4_control0_IQP_Options_i200uA 3 19494 #define tx_x4_control0_IQP_Options_i250uA 4 19495 #define tx_x4_control0_IQP_Options_i300uA 5 19496 #define tx_x4_control0_IQP_Options_i350uA 6 19497 #define tx_x4_control0_IQP_Options_i400uA 7 19498 #define tx_x4_control0_IQP_Options_i450uA 8 19499 #define tx_x4_control0_IQP_Options_i500uA 9 19500 #define tx_x4_control0_IQP_Options_i550uA 10 19501 #define tx_x4_control0_IQP_Options_i600uA 11 19502 #define tx_x4_control0_IQP_Options_i650uA 12 19503 #define tx_x4_control0_IQP_Options_i700uA 13 19504 #define tx_x4_control0_IQP_Options_i750uA 14 19505 #define tx_x4_control0_IQP_Options_i800uA 15 19506 19507 /**************************************************************************** 19508 * Enums: tx_x4_control0_IDriver_Options 19509 */ 19510 #define tx_x4_control0_IDriver_Options_v680mV 0 19511 #define tx_x4_control0_IDriver_Options_v730mV 1 19512 #define tx_x4_control0_IDriver_Options_v780mV 2 19513 #define tx_x4_control0_IDriver_Options_v830mV 3 19514 #define tx_x4_control0_IDriver_Options_v880mV 4 19515 #define tx_x4_control0_IDriver_Options_v930mV 5 19516 #define tx_x4_control0_IDriver_Options_v980mV 6 19517 #define tx_x4_control0_IDriver_Options_v1010mV 7 19518 #define tx_x4_control0_IDriver_Options_v1040mV 8 19519 #define tx_x4_control0_IDriver_Options_v1060mV 9 19520 #define tx_x4_control0_IDriver_Options_v1070mV 10 19521 #define tx_x4_control0_IDriver_Options_v1080mV 11 19522 #define tx_x4_control0_IDriver_Options_v1085mV 12 19523 #define tx_x4_control0_IDriver_Options_v1090mV 13 19524 #define tx_x4_control0_IDriver_Options_v1095mV 14 19525 #define tx_x4_control0_IDriver_Options_v1100mV 15 19526 19527 /**************************************************************************** 19528 * Enums: tx_x4_control0_operationModes 19529 */ 19530 #define tx_x4_control0_operationModes_XGXS 0 19531 #define tx_x4_control0_operationModes_XGXG_nCC 1 19532 #define tx_x4_control0_operationModes_Indlane_OS8 4 19533 #define tx_x4_control0_operationModes_IndLane_OS5 5 19534 #define tx_x4_control0_operationModes_PCI 7 19535 #define tx_x4_control0_operationModes_XGXS_nLQ 8 19536 #define tx_x4_control0_operationModes_XGXS_nLQnCC 9 19537 #define tx_x4_control0_operationModes_PBypass 10 19538 #define tx_x4_control0_operationModes_PBypass_nDSK 11 19539 #define tx_x4_control0_operationModes_ComboCoreMode 12 19540 #define tx_x4_control0_operationModes_Clocks_off 15 19541 19542 /**************************************************************************** 19543 * Enums: tx_x4_control0_actualSpeeds 19544 */ 19545 #define tx_x4_control0_actualSpeeds_dr_10M 0 19546 #define tx_x4_control0_actualSpeeds_dr_100M 1 19547 #define tx_x4_control0_actualSpeeds_dr_1G 2 19548 #define tx_x4_control0_actualSpeeds_dr_2p5G 3 19549 #define tx_x4_control0_actualSpeeds_dr_5G_X4 4 19550 #define tx_x4_control0_actualSpeeds_dr_6G_X4 5 19551 #define tx_x4_control0_actualSpeeds_dr_10G_HiG 6 19552 #define tx_x4_control0_actualSpeeds_dr_10G_CX4 7 19553 #define tx_x4_control0_actualSpeeds_dr_12G_HiG 8 19554 #define tx_x4_control0_actualSpeeds_dr_12p5G_X4 9 19555 #define tx_x4_control0_actualSpeeds_dr_13G_X4 10 19556 #define tx_x4_control0_actualSpeeds_dr_15G_X4 11 19557 #define tx_x4_control0_actualSpeeds_dr_16G_X4 12 19558 #define tx_x4_control0_actualSpeeds_dr_1G_KX 13 19559 #define tx_x4_control0_actualSpeeds_dr_10G_KX4 14 19560 #define tx_x4_control0_actualSpeeds_dr_10G_KR 15 19561 #define tx_x4_control0_actualSpeeds_dr_5G 16 19562 #define tx_x4_control0_actualSpeeds_dr_6p4G 17 19563 #define tx_x4_control0_actualSpeeds_dr_20G_X4 18 19564 #define tx_x4_control0_actualSpeeds_dr_21G_X4 19 19565 #define tx_x4_control0_actualSpeeds_dr_25G_X4 20 19566 #define tx_x4_control0_actualSpeeds_dr_10G_HiG_DXGXS 21 19567 #define tx_x4_control0_actualSpeeds_dr_10G_DXGXS 22 19568 #define tx_x4_control0_actualSpeeds_dr_10p5G_HiG_DXGXS 23 19569 #define tx_x4_control0_actualSpeeds_dr_10p5G_DXGXS 24 19570 #define tx_x4_control0_actualSpeeds_dr_12p773G_HiG_DXGXS 25 19571 #define tx_x4_control0_actualSpeeds_dr_12p773G_DXGXS 26 19572 #define tx_x4_control0_actualSpeeds_dr_10G_XFI 27 19573 #define tx_x4_control0_actualSpeeds_dr_40G 28 19574 #define tx_x4_control0_actualSpeeds_dr_20G_HiG_DXGXS 29 19575 #define tx_x4_control0_actualSpeeds_dr_20G_DXGXS 30 19576 #define tx_x4_control0_actualSpeeds_dr_10G_SFI 31 19577 #define tx_x4_control0_actualSpeeds_dr_31p5G 32 19578 #define tx_x4_control0_actualSpeeds_dr_32p7G 33 19579 #define tx_x4_control0_actualSpeeds_dr_20G_SCR 34 19580 #define tx_x4_control0_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 19581 #define tx_x4_control0_actualSpeeds_dr_10G_DXGXS_SCR 36 19582 #define tx_x4_control0_actualSpeeds_dr_12G_R2 37 19583 #define tx_x4_control0_actualSpeeds_dr_10G_X2 38 19584 #define tx_x4_control0_actualSpeeds_dr_40G_KR4 39 19585 #define tx_x4_control0_actualSpeeds_dr_40G_CR4 40 19586 #define tx_x4_control0_actualSpeeds_dr_100G_CR10 41 19587 #define tx_x4_control0_actualSpeeds_dr_15p75G_DXGXS 44 19588 #define tx_x4_control0_actualSpeeds_dr_20G_KR2 57 19589 #define tx_x4_control0_actualSpeeds_dr_20G_CR2 58 19590 19591 /**************************************************************************** 19592 * Enums: tx_x4_control0_actualSpeedsMisc1 19593 */ 19594 #define tx_x4_control0_actualSpeedsMisc1_dr_2500BRCM_X1 16 19595 #define tx_x4_control0_actualSpeedsMisc1_dr_5000BRCM_X4 17 19596 #define tx_x4_control0_actualSpeedsMisc1_dr_6000BRCM_X4 18 19597 #define tx_x4_control0_actualSpeedsMisc1_dr_10GHiGig_X4 19 19598 #define tx_x4_control0_actualSpeedsMisc1_dr_10GBASE_CX4 20 19599 #define tx_x4_control0_actualSpeedsMisc1_dr_12GHiGig_X4 21 19600 #define tx_x4_control0_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 19601 #define tx_x4_control0_actualSpeedsMisc1_dr_13GHiGig_X4 23 19602 #define tx_x4_control0_actualSpeedsMisc1_dr_15GHiGig_X4 24 19603 #define tx_x4_control0_actualSpeedsMisc1_dr_16GHiGig_X4 25 19604 #define tx_x4_control0_actualSpeedsMisc1_dr_5000BRCM_X1 26 19605 #define tx_x4_control0_actualSpeedsMisc1_dr_6363BRCM_X1 27 19606 #define tx_x4_control0_actualSpeedsMisc1_dr_20GHiGig_X4 28 19607 #define tx_x4_control0_actualSpeedsMisc1_dr_21GHiGig_X4 29 19608 #define tx_x4_control0_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 19609 #define tx_x4_control0_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 19610 19611 /**************************************************************************** 19612 * Enums: tx_x4_control0_IndLaneModes 19613 */ 19614 #define tx_x4_control0_IndLaneModes_SWSDR_div2 0 19615 #define tx_x4_control0_IndLaneModes_SWSDR_div1 1 19616 #define tx_x4_control0_IndLaneModes_DWSDR_div2 2 19617 #define tx_x4_control0_IndLaneModes_DWSDR_div1 3 19618 19619 /**************************************************************************** 19620 * Enums: tx_x4_control0_prbsSelect 19621 */ 19622 #define tx_x4_control0_prbsSelect_prbs7 0 19623 #define tx_x4_control0_prbsSelect_prbs15 1 19624 #define tx_x4_control0_prbsSelect_prbs23 2 19625 #define tx_x4_control0_prbsSelect_prbs31 3 19626 19627 /**************************************************************************** 19628 * Enums: tx_x4_control0_vcoDivider 19629 */ 19630 #define tx_x4_control0_vcoDivider_div32 0 19631 #define tx_x4_control0_vcoDivider_div36 1 19632 #define tx_x4_control0_vcoDivider_div40 2 19633 #define tx_x4_control0_vcoDivider_div42 3 19634 #define tx_x4_control0_vcoDivider_div48 4 19635 #define tx_x4_control0_vcoDivider_div50 5 19636 #define tx_x4_control0_vcoDivider_div52 6 19637 #define tx_x4_control0_vcoDivider_div54 7 19638 #define tx_x4_control0_vcoDivider_div60 8 19639 #define tx_x4_control0_vcoDivider_div64 9 19640 #define tx_x4_control0_vcoDivider_div66 10 19641 #define tx_x4_control0_vcoDivider_div68 11 19642 #define tx_x4_control0_vcoDivider_div70 12 19643 #define tx_x4_control0_vcoDivider_div80 13 19644 #define tx_x4_control0_vcoDivider_div92 14 19645 #define tx_x4_control0_vcoDivider_div100 15 19646 19647 /**************************************************************************** 19648 * Enums: tx_x4_control0_refClkSelect 19649 */ 19650 #define tx_x4_control0_refClkSelect_clk_25MHz 0 19651 #define tx_x4_control0_refClkSelect_clk_100MHz 1 19652 #define tx_x4_control0_refClkSelect_clk_125MHz 2 19653 #define tx_x4_control0_refClkSelect_clk_156p25MHz 3 19654 #define tx_x4_control0_refClkSelect_clk_187p5MHz 4 19655 #define tx_x4_control0_refClkSelect_clk_161p25Mhz 5 19656 #define tx_x4_control0_refClkSelect_clk_50Mhz 6 19657 #define tx_x4_control0_refClkSelect_clk_106p25Mhz 7 19658 19659 /**************************************************************************** 19660 * Enums: tx_x4_control0_aerMMDdevTypeSelect 19661 */ 19662 #define tx_x4_control0_aerMMDdevTypeSelect_combo_core 0 19663 #define tx_x4_control0_aerMMDdevTypeSelect_PMA_PMD 1 19664 #define tx_x4_control0_aerMMDdevTypeSelect_PCS 3 19665 #define tx_x4_control0_aerMMDdevTypeSelect_PHY 4 19666 #define tx_x4_control0_aerMMDdevTypeSelect_DTE 5 19667 #define tx_x4_control0_aerMMDdevTypeSelect_CL73_AN 7 19668 19669 /**************************************************************************** 19670 * Enums: tx_x4_control0_aerMMDportSelect 19671 */ 19672 #define tx_x4_control0_aerMMDportSelect_ln0 0 19673 #define tx_x4_control0_aerMMDportSelect_ln1 1 19674 #define tx_x4_control0_aerMMDportSelect_ln2 2 19675 #define tx_x4_control0_aerMMDportSelect_ln3 3 19676 #define tx_x4_control0_aerMMDportSelect_BCST_ln0_1_2_3 511 19677 #define tx_x4_control0_aerMMDportSelect_BCST_ln0_1 512 19678 #define tx_x4_control0_aerMMDportSelect_BCST_ln2_3 513 19679 19680 /**************************************************************************** 19681 * Enums: tx_x4_control0_firmwareModeSelect 19682 */ 19683 #define tx_x4_control0_firmwareModeSelect_DEFAULT 0 19684 #define tx_x4_control0_firmwareModeSelect_SFP_OPT_LR 1 19685 #define tx_x4_control0_firmwareModeSelect_SFP_DAC 2 19686 #define tx_x4_control0_firmwareModeSelect_XLAUI 3 19687 #define tx_x4_control0_firmwareModeSelect_LONG_CH_6G 4 19688 19689 /**************************************************************************** 19690 * Enums: tx_x4_control0_tempIdxSelect 19691 */ 19692 #define tx_x4_control0_tempIdxSelect_LTE__22p9C 15 19693 #define tx_x4_control0_tempIdxSelect_LTE__12p6C 14 19694 #define tx_x4_control0_tempIdxSelect_LTE__3p0C 13 19695 #define tx_x4_control0_tempIdxSelect_LTE_6p7C 12 19696 #define tx_x4_control0_tempIdxSelect_LTE_16p4C 11 19697 #define tx_x4_control0_tempIdxSelect_LTE_26p6C 10 19698 #define tx_x4_control0_tempIdxSelect_LTE_36p3C 9 19699 #define tx_x4_control0_tempIdxSelect_LTE_46p0C 8 19700 #define tx_x4_control0_tempIdxSelect_LTE_56p2C 7 19701 #define tx_x4_control0_tempIdxSelect_LTE_65p9C 6 19702 #define tx_x4_control0_tempIdxSelect_LTE_75p6C 5 19703 #define tx_x4_control0_tempIdxSelect_LTE_85p3C 4 19704 #define tx_x4_control0_tempIdxSelect_LTE_95p5C 3 19705 #define tx_x4_control0_tempIdxSelect_LTE_105p2C 2 19706 #define tx_x4_control0_tempIdxSelect_LTE_114p9C 1 19707 #define tx_x4_control0_tempIdxSelect_LTE_125p1C 0 19708 19709 /**************************************************************************** 19710 * Enums: tx_x4_control0_port_mode 19711 */ 19712 #define tx_x4_control0_port_mode_QUAD_PORT 0 19713 #define tx_x4_control0_port_mode_TRI_1_PORT 1 19714 #define tx_x4_control0_port_mode_TRI_2_PORT 2 19715 #define tx_x4_control0_port_mode_DUAL_PORT 3 19716 #define tx_x4_control0_port_mode_SINGLE_PORT 4 19717 19718 /**************************************************************************** 19719 * Enums: tx_x4_control0_rev_letter_enum 19720 */ 19721 #define tx_x4_control0_rev_letter_enum_REV_A 0 19722 #define tx_x4_control0_rev_letter_enum_REV_B 1 19723 #define tx_x4_control0_rev_letter_enum_REV_C 2 19724 #define tx_x4_control0_rev_letter_enum_REV_D 3 19725 19726 /**************************************************************************** 19727 * Enums: tx_x4_control0_rev_number_enum 19728 */ 19729 #define tx_x4_control0_rev_number_enum_REV_0 0 19730 #define tx_x4_control0_rev_number_enum_REV_1 1 19731 #define tx_x4_control0_rev_number_enum_REV_2 2 19732 #define tx_x4_control0_rev_number_enum_REV_3 3 19733 #define tx_x4_control0_rev_number_enum_REV_4 4 19734 #define tx_x4_control0_rev_number_enum_REV_5 5 19735 #define tx_x4_control0_rev_number_enum_REV_6 6 19736 #define tx_x4_control0_rev_number_enum_REV_7 7 19737 19738 /**************************************************************************** 19739 * Enums: tx_x4_control0_bonding_enum 19740 */ 19741 #define tx_x4_control0_bonding_enum_WIRE_BOND 0 19742 #define tx_x4_control0_bonding_enum_FLIP_CHIP 1 19743 19744 /**************************************************************************** 19745 * Enums: tx_x4_control0_tech_process 19746 */ 19747 #define tx_x4_control0_tech_process_PROCESS_90NM 0 19748 #define tx_x4_control0_tech_process_PROCESS_65NM 1 19749 #define tx_x4_control0_tech_process_PROCESS_40NM 2 19750 #define tx_x4_control0_tech_process_PROCESS_28NM 3 19751 #define tx_x4_control0_tech_process_PROCESS_16NM 4 19752 19753 /**************************************************************************** 19754 * Enums: tx_x4_control0_model_num 19755 */ 19756 #define tx_x4_control0_model_num_SERDES_CL73 0 19757 #define tx_x4_control0_model_num_XGXS_16G 1 19758 #define tx_x4_control0_model_num_HYPERCORE 2 19759 #define tx_x4_control0_model_num_HYPERLITE 3 19760 #define tx_x4_control0_model_num_PCIE_G2_PIPE 4 19761 #define tx_x4_control0_model_num_SERDES_1p25GBd 5 19762 #define tx_x4_control0_model_num_SATA2 6 19763 #define tx_x4_control0_model_num_QSGMII 7 19764 #define tx_x4_control0_model_num_XGXS10G 8 19765 #define tx_x4_control0_model_num_WARPCORE 9 19766 #define tx_x4_control0_model_num_XFICORE 10 19767 #define tx_x4_control0_model_num_RXFI 11 19768 #define tx_x4_control0_model_num_WARPLITE 12 19769 #define tx_x4_control0_model_num_PENTACORE 13 19770 #define tx_x4_control0_model_num_ESM 14 19771 #define tx_x4_control0_model_num_QUAD_SGMII 15 19772 #define tx_x4_control0_model_num_WARPCORE_3 16 19773 #define tx_x4_control0_model_num_TSC 17 19774 #define tx_x4_control0_model_num_TSC4E 18 19775 #define tx_x4_control0_model_num_TSC12E 19 19776 #define tx_x4_control0_model_num_TSC4F 20 19777 #define tx_x4_control0_model_num_TSC4F_GEN2 21 19778 #define tx_x4_control0_model_num_XGXS_CL73_90NM 29 19779 #define tx_x4_control0_model_num_SERDES_CL73_90NM 30 19780 #define tx_x4_control0_model_num_WARPCORE3 32 19781 #define tx_x4_control0_model_num_WARPCORE4_TSC 33 19782 #define tx_x4_control0_model_num_RXAUI 34 19783 19784 /**************************************************************************** 19785 * Enums: tx_x4_control0_payload 19786 */ 19787 #define tx_x4_control0_payload_REPEAT_2_BYTES 0 19788 #define tx_x4_control0_payload_RAMPING 1 19789 #define tx_x4_control0_payload_CL48_CRPAT 2 19790 #define tx_x4_control0_payload_CL48_CJPAT 3 19791 #define tx_x4_control0_payload_CL36_LONG_CRPAT 4 19792 #define tx_x4_control0_payload_CL36_SHORT_CRPAT 5 19793 19794 /**************************************************************************** 19795 * Enums: tx_x4_control0_sc 19796 */ 19797 #define tx_x4_control0_sc_S_10G_CR1 0 19798 #define tx_x4_control0_sc_S_10G_KR1 1 19799 #define tx_x4_control0_sc_S_10G_X1 2 19800 #define tx_x4_control0_sc_S_10G_HG2_CR1 4 19801 #define tx_x4_control0_sc_S_10G_HG2_KR1 5 19802 #define tx_x4_control0_sc_S_10G_HG2_X1 6 19803 #define tx_x4_control0_sc_S_20G_CR1 8 19804 #define tx_x4_control0_sc_S_20G_KR1 9 19805 #define tx_x4_control0_sc_S_20G_X1 10 19806 #define tx_x4_control0_sc_S_20G_HG2_CR1 12 19807 #define tx_x4_control0_sc_S_20G_HG2_KR1 13 19808 #define tx_x4_control0_sc_S_20G_HG2_X1 14 19809 #define tx_x4_control0_sc_S_25G_CR1 16 19810 #define tx_x4_control0_sc_S_25G_KR1 17 19811 #define tx_x4_control0_sc_S_25G_X1 18 19812 #define tx_x4_control0_sc_S_25G_HG2_CR1 20 19813 #define tx_x4_control0_sc_S_25G_HG2_KR1 21 19814 #define tx_x4_control0_sc_S_25G_HG2_X1 22 19815 #define tx_x4_control0_sc_S_20G_CR2 24 19816 #define tx_x4_control0_sc_S_20G_KR2 25 19817 #define tx_x4_control0_sc_S_20G_X2 26 19818 #define tx_x4_control0_sc_S_20G_HG2_CR2 28 19819 #define tx_x4_control0_sc_S_20G_HG2_KR2 29 19820 #define tx_x4_control0_sc_S_20G_HG2_X2 30 19821 #define tx_x4_control0_sc_S_40G_CR2 32 19822 #define tx_x4_control0_sc_S_40G_KR2 33 19823 #define tx_x4_control0_sc_S_40G_X2 34 19824 #define tx_x4_control0_sc_S_40G_HG2_CR2 36 19825 #define tx_x4_control0_sc_S_40G_HG2_KR2 37 19826 #define tx_x4_control0_sc_S_40G_HG2_X2 38 19827 #define tx_x4_control0_sc_S_40G_CR4 40 19828 #define tx_x4_control0_sc_S_40G_KR4 41 19829 #define tx_x4_control0_sc_S_40G_X4 42 19830 #define tx_x4_control0_sc_S_40G_HG2_CR4 44 19831 #define tx_x4_control0_sc_S_40G_HG2_KR4 45 19832 #define tx_x4_control0_sc_S_40G_HG2_X4 46 19833 #define tx_x4_control0_sc_S_50G_CR2 48 19834 #define tx_x4_control0_sc_S_50G_KR2 49 19835 #define tx_x4_control0_sc_S_50G_X2 50 19836 #define tx_x4_control0_sc_S_50G_HG2_CR2 52 19837 #define tx_x4_control0_sc_S_50G_HG2_KR2 53 19838 #define tx_x4_control0_sc_S_50G_HG2_X2 54 19839 #define tx_x4_control0_sc_S_50G_CR4 56 19840 #define tx_x4_control0_sc_S_50G_KR4 57 19841 #define tx_x4_control0_sc_S_50G_X4 58 19842 #define tx_x4_control0_sc_S_50G_HG2_CR4 60 19843 #define tx_x4_control0_sc_S_50G_HG2_KR4 61 19844 #define tx_x4_control0_sc_S_50G_HG2_X4 62 19845 #define tx_x4_control0_sc_S_100G_CR4 64 19846 #define tx_x4_control0_sc_S_100G_KR4 65 19847 #define tx_x4_control0_sc_S_100G_X4 66 19848 #define tx_x4_control0_sc_S_100G_HG2_CR4 68 19849 #define tx_x4_control0_sc_S_100G_HG2_KR4 69 19850 #define tx_x4_control0_sc_S_100G_HG2_X4 70 19851 #define tx_x4_control0_sc_S_CL73_20GVCO 72 19852 #define tx_x4_control0_sc_S_CL73_25GVCO 80 19853 #define tx_x4_control0_sc_S_CL36_20GVCO 88 19854 #define tx_x4_control0_sc_S_CL36_25GVCO 96 19855 #define tx_x4_control0_sc_S_25G_CR_IEEE 112 19856 #define tx_x4_control0_sc_S_25G_CRS_IEEE 113 19857 #define tx_x4_control0_sc_S_25G_KR_IEEE 114 19858 #define tx_x4_control0_sc_S_25G_KRS_IEEE 115 19859 19860 /**************************************************************************** 19861 * Enums: tx_x4_control0_t_fifo_modes 19862 */ 19863 #define tx_x4_control0_t_fifo_modes_T_FIFO_INSERT_NO_AM 0 19864 #define tx_x4_control0_t_fifo_modes_T_FIFO_INSERT_4_AM 1 19865 #define tx_x4_control0_t_fifo_modes_T_FIFO_INSERT_20_AM 2 19866 #define tx_x4_control0_t_fifo_modes_T_FIFO_INSERT_2_AM 3 19867 19868 /**************************************************************************** 19869 * Enums: tx_x4_control0_t_enc_modes 19870 */ 19871 #define tx_x4_control0_t_enc_modes_T_ENC_MODE_BYPASS 0 19872 #define tx_x4_control0_t_enc_modes_T_ENC_MODE_CL49 1 19873 #define tx_x4_control0_t_enc_modes_T_ENC_MODE_CL82 2 19874 19875 /**************************************************************************** 19876 * Enums: tx_x4_control0_btmx_mode 19877 */ 19878 #define tx_x4_control0_btmx_mode_BS_BTMX_MODE_1to1 0 19879 #define tx_x4_control0_btmx_mode_BS_BTMX_MODE_2to1 1 19880 #define tx_x4_control0_btmx_mode_BS_BTMX_MODE_5to1 2 19881 19882 /**************************************************************************** 19883 * Enums: tx_x4_control0_t_type_cl82 19884 */ 19885 #define tx_x4_control0_t_type_cl82_T_TYPE_B1 5 19886 #define tx_x4_control0_t_type_cl82_T_TYPE_C 4 19887 #define tx_x4_control0_t_type_cl82_T_TYPE_S 3 19888 #define tx_x4_control0_t_type_cl82_T_TYPE_T 2 19889 #define tx_x4_control0_t_type_cl82_T_TYPE_D 1 19890 #define tx_x4_control0_t_type_cl82_T_TYPE_E 0 19891 19892 /**************************************************************************** 19893 * Enums: tx_x4_control0_txsm_state_cl82 19894 */ 19895 #define tx_x4_control0_txsm_state_cl82_TX_HIG_END 6 19896 #define tx_x4_control0_txsm_state_cl82_TX_HIG_START 5 19897 #define tx_x4_control0_txsm_state_cl82_TX_E 4 19898 #define tx_x4_control0_txsm_state_cl82_TX_T 3 19899 #define tx_x4_control0_txsm_state_cl82_TX_D 2 19900 #define tx_x4_control0_txsm_state_cl82_TX_C 1 19901 #define tx_x4_control0_txsm_state_cl82_TX_INIT 0 19902 19903 /**************************************************************************** 19904 * Enums: tx_x4_control0_ltxsm_state_cl82 19905 */ 19906 #define tx_x4_control0_ltxsm_state_cl82_TX_HIG_END 64 19907 #define tx_x4_control0_ltxsm_state_cl82_TX_HIG_START 32 19908 #define tx_x4_control0_ltxsm_state_cl82_TX_E 16 19909 #define tx_x4_control0_ltxsm_state_cl82_TX_T 8 19910 #define tx_x4_control0_ltxsm_state_cl82_TX_D 4 19911 #define tx_x4_control0_ltxsm_state_cl82_TX_C 2 19912 #define tx_x4_control0_ltxsm_state_cl82_TX_INIT 1 19913 19914 /**************************************************************************** 19915 * Enums: tx_x4_control0_r_type_coded_cl82 19916 */ 19917 #define tx_x4_control0_r_type_coded_cl82_R_TYPE_B1 32 19918 #define tx_x4_control0_r_type_coded_cl82_R_TYPE_C 16 19919 #define tx_x4_control0_r_type_coded_cl82_R_TYPE_S 8 19920 #define tx_x4_control0_r_type_coded_cl82_R_TYPE_T 4 19921 #define tx_x4_control0_r_type_coded_cl82_R_TYPE_D 2 19922 #define tx_x4_control0_r_type_coded_cl82_R_TYPE_E 1 19923 19924 /**************************************************************************** 19925 * Enums: tx_x4_control0_rxsm_state_cl82 19926 */ 19927 #define tx_x4_control0_rxsm_state_cl82_RX_HIG_END 64 19928 #define tx_x4_control0_rxsm_state_cl82_RX_HIG_START 32 19929 #define tx_x4_control0_rxsm_state_cl82_RX_E 16 19930 #define tx_x4_control0_rxsm_state_cl82_RX_T 8 19931 #define tx_x4_control0_rxsm_state_cl82_RX_D 4 19932 #define tx_x4_control0_rxsm_state_cl82_RX_C 2 19933 #define tx_x4_control0_rxsm_state_cl82_RX_INIT 1 19934 19935 /**************************************************************************** 19936 * Enums: tx_x4_control0_deskew_state 19937 */ 19938 #define tx_x4_control0_deskew_state_ALIGN_ACQUIRED 2 19939 #define tx_x4_control0_deskew_state_LOSS_OF_ALIGNMENT 1 19940 19941 /**************************************************************************** 19942 * Enums: tx_x4_control0_os_mode_enum 19943 */ 19944 #define tx_x4_control0_os_mode_enum_OS_MODE_1 0 19945 #define tx_x4_control0_os_mode_enum_OS_MODE_2 1 19946 #define tx_x4_control0_os_mode_enum_OS_MODE_4 2 19947 #define tx_x4_control0_os_mode_enum_OS_MODE_16p5 8 19948 #define tx_x4_control0_os_mode_enum_OS_MODE_20p625 12 19949 19950 /**************************************************************************** 19951 * Enums: tx_x4_control0_scr_modes 19952 */ 19953 #define tx_x4_control0_scr_modes_T_SCR_MODE_BYPASS 0 19954 #define tx_x4_control0_scr_modes_T_SCR_MODE_CL49 1 19955 #define tx_x4_control0_scr_modes_T_SCR_MODE_40G_2_LANE 2 19956 #define tx_x4_control0_scr_modes_T_SCR_MODE_100G 3 19957 #define tx_x4_control0_scr_modes_T_SCR_MODE_20G 4 19958 #define tx_x4_control0_scr_modes_T_SCR_MODE_40G_4_LANE 5 19959 19960 /**************************************************************************** 19961 * Enums: tx_x4_control0_descr_modes 19962 */ 19963 #define tx_x4_control0_descr_modes_R_DESCR_MODE_BYPASS 0 19964 #define tx_x4_control0_descr_modes_R_DESCR_MODE_CL49 1 19965 #define tx_x4_control0_descr_modes_R_DESCR_MODE_CL82 2 19966 19967 /**************************************************************************** 19968 * Enums: tx_x4_control0_r_dec_tl_mode 19969 */ 19970 #define tx_x4_control0_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 19971 #define tx_x4_control0_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 19972 #define tx_x4_control0_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 19973 19974 /**************************************************************************** 19975 * Enums: tx_x4_control0_r_dec_fsm_mode 19976 */ 19977 #define tx_x4_control0_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 19978 #define tx_x4_control0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 19979 #define tx_x4_control0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 19980 19981 /**************************************************************************** 19982 * Enums: tx_x4_control0_r_deskew_mode 19983 */ 19984 #define tx_x4_control0_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 19985 #define tx_x4_control0_r_deskew_mode_R_DESKEW_MODE_20G 1 19986 #define tx_x4_control0_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 19987 #define tx_x4_control0_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 19988 #define tx_x4_control0_r_deskew_mode_R_DESKEW_MODE_100G 4 19989 #define tx_x4_control0_r_deskew_mode_R_DESKEW_MODE_CL49 5 19990 #define tx_x4_control0_r_deskew_mode_R_DESKEW_MODE_CL91_QUAD 6 19991 #define tx_x4_control0_r_deskew_mode_R_DESKEW_MODE_CL91_SINGLE_BRCM 7 19992 #define tx_x4_control0_r_deskew_mode_R_DESKEW_MODE_CL91_DUAL_BRCM 8 19993 #define tx_x4_control0_r_deskew_mode_R_DESKEW_MODE_CL91_FC 9 19994 19995 /**************************************************************************** 19996 * Enums: tx_x4_control0_bs_dist_modes 19997 */ 19998 #define tx_x4_control0_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 19999 #define tx_x4_control0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 20000 #define tx_x4_control0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 20001 #define tx_x4_control0_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 20002 20003 /**************************************************************************** 20004 * Enums: tx_x4_control0_cl49_t_type 20005 */ 20006 #define tx_x4_control0_cl49_t_type_BAD_T_TYPE 15 20007 #define tx_x4_control0_cl49_t_type_T_TYPE_B0 11 20008 #define tx_x4_control0_cl49_t_type_T_TYPE_OB 10 20009 #define tx_x4_control0_cl49_t_type_T_TYPE_B1 9 20010 #define tx_x4_control0_cl49_t_type_T_TYPE_DB 8 20011 #define tx_x4_control0_cl49_t_type_T_TYPE_FC 7 20012 #define tx_x4_control0_cl49_t_type_T_TYPE_TB 6 20013 #define tx_x4_control0_cl49_t_type_T_TYPE_LI 5 20014 #define tx_x4_control0_cl49_t_type_T_TYPE_C 4 20015 #define tx_x4_control0_cl49_t_type_T_TYPE_S 3 20016 #define tx_x4_control0_cl49_t_type_T_TYPE_T 2 20017 #define tx_x4_control0_cl49_t_type_T_TYPE_D 1 20018 #define tx_x4_control0_cl49_t_type_T_TYPE_E 0 20019 20020 /**************************************************************************** 20021 * Enums: tx_x4_control0_cl49_txsm_states 20022 */ 20023 #define tx_x4_control0_cl49_txsm_states_TX_HIG_END 7 20024 #define tx_x4_control0_cl49_txsm_states_TX_HIG_START 6 20025 #define tx_x4_control0_cl49_txsm_states_TX_LI 5 20026 #define tx_x4_control0_cl49_txsm_states_TX_E 4 20027 #define tx_x4_control0_cl49_txsm_states_TX_T 3 20028 #define tx_x4_control0_cl49_txsm_states_TX_D 2 20029 #define tx_x4_control0_cl49_txsm_states_TX_C 1 20030 #define tx_x4_control0_cl49_txsm_states_TX_INIT 0 20031 20032 /**************************************************************************** 20033 * Enums: tx_x4_control0_cl49_ltxsm_states 20034 */ 20035 #define tx_x4_control0_cl49_ltxsm_states_TX_HIG_END 128 20036 #define tx_x4_control0_cl49_ltxsm_states_TX_HIG_START 64 20037 #define tx_x4_control0_cl49_ltxsm_states_TX_LI 32 20038 #define tx_x4_control0_cl49_ltxsm_states_TX_E 16 20039 #define tx_x4_control0_cl49_ltxsm_states_TX_T 8 20040 #define tx_x4_control0_cl49_ltxsm_states_TX_D 4 20041 #define tx_x4_control0_cl49_ltxsm_states_TX_C 2 20042 #define tx_x4_control0_cl49_ltxsm_states_TX_INIT 1 20043 20044 /**************************************************************************** 20045 * Enums: tx_x4_control0_burst_error_mode 20046 */ 20047 #define tx_x4_control0_burst_error_mode_BURST_ERROR_11_BITS 0 20048 #define tx_x4_control0_burst_error_mode_BURST_ERROR_16_BITS 1 20049 #define tx_x4_control0_burst_error_mode_BURST_ERROR_17_BITS 2 20050 #define tx_x4_control0_burst_error_mode_BURST_ERROR_18_BITS 3 20051 #define tx_x4_control0_burst_error_mode_BURST_ERROR_19_BITS 4 20052 #define tx_x4_control0_burst_error_mode_BURST_ERROR_20_BITS 5 20053 #define tx_x4_control0_burst_error_mode_BURST_ERROR_21_BITS 6 20054 #define tx_x4_control0_burst_error_mode_BURST_ERROR_22_BITS 7 20055 #define tx_x4_control0_burst_error_mode_BURST_ERROR_23_BITS 8 20056 #define tx_x4_control0_burst_error_mode_BURST_ERROR_24_BITS 9 20057 #define tx_x4_control0_burst_error_mode_BURST_ERROR_25_BITS 10 20058 #define tx_x4_control0_burst_error_mode_BURST_ERROR_26_BITS 11 20059 #define tx_x4_control0_burst_error_mode_BURST_ERROR_27_BITS 12 20060 #define tx_x4_control0_burst_error_mode_BURST_ERROR_28_BITS 13 20061 #define tx_x4_control0_burst_error_mode_BURST_ERROR_29_BITS 14 20062 #define tx_x4_control0_burst_error_mode_BURST_ERROR_30_BITS 15 20063 #define tx_x4_control0_burst_error_mode_BURST_ERROR_31_BITS 16 20064 #define tx_x4_control0_burst_error_mode_BURST_ERROR_32_BITS 17 20065 #define tx_x4_control0_burst_error_mode_BURST_ERROR_33_BITS 18 20066 #define tx_x4_control0_burst_error_mode_BURST_ERROR_34_BITS 19 20067 #define tx_x4_control0_burst_error_mode_BURST_ERROR_35_BITS 20 20068 #define tx_x4_control0_burst_error_mode_BURST_ERROR_36_BITS 21 20069 #define tx_x4_control0_burst_error_mode_BURST_ERROR_37_BITS 22 20070 #define tx_x4_control0_burst_error_mode_BURST_ERROR_38_BITS 23 20071 #define tx_x4_control0_burst_error_mode_BURST_ERROR_39_BITS 24 20072 #define tx_x4_control0_burst_error_mode_BURST_ERROR_40_BITS 25 20073 #define tx_x4_control0_burst_error_mode_BURST_ERROR_41_BITS 26 20074 20075 /**************************************************************************** 20076 * Enums: tx_x4_control0_bermon_state 20077 */ 20078 #define tx_x4_control0_bermon_state_HI_BER 4 20079 #define tx_x4_control0_bermon_state_GOOD_BER 3 20080 #define tx_x4_control0_bermon_state_BER_TEST_SH 2 20081 #define tx_x4_control0_bermon_state_START_TIMER 1 20082 #define tx_x4_control0_bermon_state_BER_MT_INIT 0 20083 20084 /**************************************************************************** 20085 * Enums: tx_x4_control0_rxsm_state_cl49 20086 */ 20087 #define tx_x4_control0_rxsm_state_cl49_RX_HIG_END 128 20088 #define tx_x4_control0_rxsm_state_cl49_RX_HIG_START 64 20089 #define tx_x4_control0_rxsm_state_cl49_RX_LI 32 20090 #define tx_x4_control0_rxsm_state_cl49_RX_E 16 20091 #define tx_x4_control0_rxsm_state_cl49_RX_T 8 20092 #define tx_x4_control0_rxsm_state_cl49_RX_D 4 20093 #define tx_x4_control0_rxsm_state_cl49_RX_C 2 20094 #define tx_x4_control0_rxsm_state_cl49_RX_INIT 1 20095 20096 /**************************************************************************** 20097 * Enums: tx_x4_control0_r_type 20098 */ 20099 #define tx_x4_control0_r_type_BAD_R_TYPE 15 20100 #define tx_x4_control0_r_type_R_TYPE_B0 11 20101 #define tx_x4_control0_r_type_R_TYPE_OB 10 20102 #define tx_x4_control0_r_type_R_TYPE_B1 9 20103 #define tx_x4_control0_r_type_R_TYPE_DB 8 20104 #define tx_x4_control0_r_type_R_TYPE_FC 7 20105 #define tx_x4_control0_r_type_R_TYPE_TB 6 20106 #define tx_x4_control0_r_type_R_TYPE_LI 5 20107 #define tx_x4_control0_r_type_R_TYPE_C 4 20108 #define tx_x4_control0_r_type_R_TYPE_S 3 20109 #define tx_x4_control0_r_type_R_TYPE_T 2 20110 #define tx_x4_control0_r_type_R_TYPE_D 1 20111 #define tx_x4_control0_r_type_R_TYPE_E 0 20112 20113 /**************************************************************************** 20114 * Enums: tx_x4_control0_am_lock_state 20115 */ 20116 #define tx_x4_control0_am_lock_state_INVALID_AM 512 20117 #define tx_x4_control0_am_lock_state_GOOD_AM 256 20118 #define tx_x4_control0_am_lock_state_COMP_AM 128 20119 #define tx_x4_control0_am_lock_state_TIMER_2 64 20120 #define tx_x4_control0_am_lock_state_AM_2_GOOD 32 20121 #define tx_x4_control0_am_lock_state_COMP_2ND 16 20122 #define tx_x4_control0_am_lock_state_TIMER_1 8 20123 #define tx_x4_control0_am_lock_state_FIND_1ST 4 20124 #define tx_x4_control0_am_lock_state_AM_RESET_CNT 2 20125 #define tx_x4_control0_am_lock_state_AM_LOCK_INIT 1 20126 20127 /**************************************************************************** 20128 * Enums: tx_x4_control0_msg_selector 20129 */ 20130 #define tx_x4_control0_msg_selector_RESERVED 0 20131 #define tx_x4_control0_msg_selector_VALUE_802p3 1 20132 #define tx_x4_control0_msg_selector_VALUE_802p9 2 20133 #define tx_x4_control0_msg_selector_VALUE_802p5 3 20134 #define tx_x4_control0_msg_selector_VALUE_1394 4 20135 20136 /**************************************************************************** 20137 * Enums: tx_x4_control0_synce_enum 20138 */ 20139 #define tx_x4_control0_synce_enum_SYNCE_NO_DIV 0 20140 #define tx_x4_control0_synce_enum_SYNCE_DIV_7 1 20141 #define tx_x4_control0_synce_enum_SYNCE_DIV_11 2 20142 20143 /**************************************************************************** 20144 * Enums: tx_x4_control0_synce_enum_stage0 20145 */ 20146 #define tx_x4_control0_synce_enum_stage0_SYNCE_NO_DIV 0 20147 #define tx_x4_control0_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 20148 #define tx_x4_control0_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 20149 20150 /**************************************************************************** 20151 * Enums: tx_x4_control0_cl91_sync_state 20152 */ 20153 #define tx_x4_control0_cl91_sync_state_FIND_1ST 0 20154 #define tx_x4_control0_cl91_sync_state_COUNT_NEXT 1 20155 #define tx_x4_control0_cl91_sync_state_COMP_2ND 2 20156 #define tx_x4_control0_cl91_sync_state_TWO_GOOD 3 20157 20158 /**************************************************************************** 20159 * Enums: tx_x4_control0_cl91_algn_state 20160 */ 20161 #define tx_x4_control0_cl91_algn_state_LOSS_OF_ALIGNMENT 0 20162 #define tx_x4_control0_cl91_algn_state_DESKEW 1 20163 #define tx_x4_control0_cl91_algn_state_DESKEW_FAIL 2 20164 #define tx_x4_control0_cl91_algn_state_ALIGN_ACQUIRED 3 20165 #define tx_x4_control0_cl91_algn_state_CW_GOOD 4 20166 #define tx_x4_control0_cl91_algn_state_CW_BAD 5 20167 #define tx_x4_control0_cl91_algn_state_THREE_BAD 6 20168 20169 /**************************************************************************** 20170 * Enums: tx_x4_control0_fec_sel_override 20171 */ 20172 #define tx_x4_control0_fec_sel_override_NO_OVERRIDE 0 20173 #define tx_x4_control0_fec_sel_override_NO_FEC 1 20174 #define tx_x4_control0_fec_sel_override_FEC_CL74 2 20175 #define tx_x4_control0_fec_sel_override_FEC_CL91 3 20176 20177 /**************************************************************************** 20178 * Enums: tx_x4_control0_cl91_blksync_mode 20179 */ 20180 #define tx_x4_control0_cl91_blksync_mode_R_BLKSYNC_NO_CL91_FEC 0 20181 #define tx_x4_control0_cl91_blksync_mode_R_BLKSYNC_CL91_QUAD_LANE_FEC 1 20182 #define tx_x4_control0_cl91_blksync_mode_R_BLKSYNC_CL91_DUAL_LANE_FEC 2 20183 #define tx_x4_control0_cl91_blksync_mode_R_BLKSYNC_CL91_SINGLE_LANE_FEC 3 20184 #define tx_x4_control0_cl91_blksync_mode_R_BLKSYNC_CL91_FC_FEC 4 20185 20186 /**************************************************************************** 20187 * Enums: tx_x4_control0_r_merge_mode 20188 */ 20189 #define tx_x4_control0_r_merge_mode_R_MERGE_MODE_BYPASS 0 20190 #define tx_x4_control0_r_merge_mode_R_MERGE_MODE_CL91_FC 1 20191 #define tx_x4_control0_r_merge_mode_R_MERGE_MODE_CL91_SINGLE_LANE 2 20192 #define tx_x4_control0_r_merge_mode_R_MERGE_MODE_CL91_DUAL_LANE 3 20193 #define tx_x4_control0_r_merge_mode_R_MERGE_MODE_CL91_QUAD_LANE 4 20194 20195 /**************************************************************************** 20196 * Enums: tx_x4_control0_r_tc_mode 20197 */ 20198 #define tx_x4_control0_r_tc_mode_R_TC_MODE_SINGLE 0 20199 #define tx_x4_control0_r_tc_mode_R_TC_MODE_DUAL 1 20200 #define tx_x4_control0_r_tc_mode_R_TC_MODE_QUAD 2 20201 20202 /**************************************************************************** 20203 * Enums: tx_x4_control0_r_tc_out_mode 20204 */ 20205 #define tx_x4_control0_r_tc_out_mode_R_TC_OUT_MODE_SINGLE 0 20206 #define tx_x4_control0_r_tc_out_mode_R_TC_OUT_MODE_DUAL 1 20207 #define tx_x4_control0_r_tc_out_mode_R_TC_OUT_MODE_QUAD 2 20208 20209 /**************************************************************************** 20210 * Enums: tx_x4_control0_cl91_fec_mode 20211 */ 20212 #define tx_x4_control0_cl91_fec_mode_NO_CL91_FEC 0 20213 #define tx_x4_control0_cl91_fec_mode_CL91_SINGLE_LANE_FC 1 20214 #define tx_x4_control0_cl91_fec_mode_CL91_SINGLE_LANE_BRCM_PROP 2 20215 #define tx_x4_control0_cl91_fec_mode_CL91_DUAL_LANE_BRCM_PROP 3 20216 #define tx_x4_control0_cl91_fec_mode_CL91_QUAD_LANE 4 20217 #define tx_x4_control0_cl91_fec_mode_IEEE_25G_CL91_SINGLE_LANE 5 20218 20219 /**************************************************************************** 20220 * Enums: tx_x4_control0_am_spacing_mul 20221 */ 20222 #define tx_x4_control0_am_spacing_mul_AM_SPACING_MUL_2 0 20223 #define tx_x4_control0_am_spacing_mul_AM_SPACING_MUL_4 1 20224 #define tx_x4_control0_am_spacing_mul_AM_SPACING_MUL_5 2 20225 #define tx_x4_control0_am_spacing_mul_AM_SPACING_MUL_20 3 20226 20227 /**************************************************************************** 20228 * Enums: tx_x4_credit_gen0_cl36TxEEEStates_l 20229 */ 20230 #define tx_x4_credit_gen0_cl36TxEEEStates_l_TX_REFRESH 8 20231 #define tx_x4_credit_gen0_cl36TxEEEStates_l_TX_QUIET 4 20232 #define tx_x4_credit_gen0_cl36TxEEEStates_l_TX_SLEEP 2 20233 #define tx_x4_credit_gen0_cl36TxEEEStates_l_TX_ACTIVE 1 20234 20235 /**************************************************************************** 20236 * Enums: tx_x4_credit_gen0_cl36TxEEEStates_c 20237 */ 20238 #define tx_x4_credit_gen0_cl36TxEEEStates_c_TX_REFRESH 3 20239 #define tx_x4_credit_gen0_cl36TxEEEStates_c_TX_QUIET 2 20240 #define tx_x4_credit_gen0_cl36TxEEEStates_c_TX_SLEEP 1 20241 #define tx_x4_credit_gen0_cl36TxEEEStates_c_TX_ACTIVE 0 20242 20243 /**************************************************************************** 20244 * Enums: tx_x4_credit_gen0_cl49TxEEEStates_l 20245 */ 20246 #define tx_x4_credit_gen0_cl49TxEEEStates_l_SCR_RESET_2 64 20247 #define tx_x4_credit_gen0_cl49TxEEEStates_l_SCR_RESET_1 32 20248 #define tx_x4_credit_gen0_cl49TxEEEStates_l_TX_WAKE 16 20249 #define tx_x4_credit_gen0_cl49TxEEEStates_l_TX_REFRESH 8 20250 #define tx_x4_credit_gen0_cl49TxEEEStates_l_TX_QUIET 4 20251 #define tx_x4_credit_gen0_cl49TxEEEStates_l_TX_SLEEP 2 20252 #define tx_x4_credit_gen0_cl49TxEEEStates_l_TX_ACTIVE 1 20253 20254 /**************************************************************************** 20255 * Enums: tx_x4_credit_gen0_fec_req_enum 20256 */ 20257 #define tx_x4_credit_gen0_fec_req_enum_FEC_not_supported 0 20258 #define tx_x4_credit_gen0_fec_req_enum_FEC_supported_but_not_requested 1 20259 #define tx_x4_credit_gen0_fec_req_enum_invalid_setting 2 20260 #define tx_x4_credit_gen0_fec_req_enum_FEC_supported_and_requested 3 20261 20262 /**************************************************************************** 20263 * Enums: tx_x4_credit_gen0_cl73_pause_enum 20264 */ 20265 #define tx_x4_credit_gen0_cl73_pause_enum_No_PAUSE_ability 0 20266 #define tx_x4_credit_gen0_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 20267 #define tx_x4_credit_gen0_cl73_pause_enum_Symmetric_PAUSE_ability 1 20268 #define tx_x4_credit_gen0_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 20269 20270 /**************************************************************************** 20271 * Enums: tx_x4_credit_gen0_cl49TxEEEStates_c 20272 */ 20273 #define tx_x4_credit_gen0_cl49TxEEEStates_c_SCR_RESET_2 6 20274 #define tx_x4_credit_gen0_cl49TxEEEStates_c_SCR_RESET_1 5 20275 #define tx_x4_credit_gen0_cl49TxEEEStates_c_TX_WAKE 4 20276 #define tx_x4_credit_gen0_cl49TxEEEStates_c_TX_REFRESH 3 20277 #define tx_x4_credit_gen0_cl49TxEEEStates_c_TX_QUIET 2 20278 #define tx_x4_credit_gen0_cl49TxEEEStates_c_TX_SLEEP 1 20279 #define tx_x4_credit_gen0_cl49TxEEEStates_c_TX_ACTIVE 0 20280 20281 /**************************************************************************** 20282 * Enums: tx_x4_credit_gen0_cl36RxEEEStates_l 20283 */ 20284 #define tx_x4_credit_gen0_cl36RxEEEStates_l_RX_LINK_FAIL 32 20285 #define tx_x4_credit_gen0_cl36RxEEEStates_l_RX_WTF 16 20286 #define tx_x4_credit_gen0_cl36RxEEEStates_l_RX_WAKE 8 20287 #define tx_x4_credit_gen0_cl36RxEEEStates_l_RX_QUIET 4 20288 #define tx_x4_credit_gen0_cl36RxEEEStates_l_RX_SLEEP 2 20289 #define tx_x4_credit_gen0_cl36RxEEEStates_l_RX_ACTIVE 1 20290 20291 /**************************************************************************** 20292 * Enums: tx_x4_credit_gen0_cl36RxEEEStates_c 20293 */ 20294 #define tx_x4_credit_gen0_cl36RxEEEStates_c_RX_LINK_FAIL 5 20295 #define tx_x4_credit_gen0_cl36RxEEEStates_c_RX_WTF 4 20296 #define tx_x4_credit_gen0_cl36RxEEEStates_c_RX_WAKE 3 20297 #define tx_x4_credit_gen0_cl36RxEEEStates_c_RX_QUIET 2 20298 #define tx_x4_credit_gen0_cl36RxEEEStates_c_RX_SLEEP 1 20299 #define tx_x4_credit_gen0_cl36RxEEEStates_c_RX_ACTIVE 0 20300 20301 /**************************************************************************** 20302 * Enums: tx_x4_credit_gen0_cl49RxEEEStates_l 20303 */ 20304 #define tx_x4_credit_gen0_cl49RxEEEStates_l_RX_LINK_FAIL 32 20305 #define tx_x4_credit_gen0_cl49RxEEEStates_l_RX_WTF 16 20306 #define tx_x4_credit_gen0_cl49RxEEEStates_l_RX_WAKE 8 20307 #define tx_x4_credit_gen0_cl49RxEEEStates_l_RX_QUIET 4 20308 #define tx_x4_credit_gen0_cl49RxEEEStates_l_RX_SLEEP 2 20309 #define tx_x4_credit_gen0_cl49RxEEEStates_l_RX_ACTIVE 1 20310 20311 /**************************************************************************** 20312 * Enums: tx_x4_credit_gen0_cl49RxEEEStates_c 20313 */ 20314 #define tx_x4_credit_gen0_cl49RxEEEStates_c_RX_LINK_FAIL 5 20315 #define tx_x4_credit_gen0_cl49RxEEEStates_c_RX_WTF 4 20316 #define tx_x4_credit_gen0_cl49RxEEEStates_c_RX_WAKE 3 20317 #define tx_x4_credit_gen0_cl49RxEEEStates_c_RX_QUIET 2 20318 #define tx_x4_credit_gen0_cl49RxEEEStates_c_RX_SLEEP 1 20319 #define tx_x4_credit_gen0_cl49RxEEEStates_c_RX_ACTIVE 0 20320 20321 /**************************************************************************** 20322 * Enums: tx_x4_credit_gen0_cl48TxEEEStates_l 20323 */ 20324 #define tx_x4_credit_gen0_cl48TxEEEStates_l_TX_REFRESH 8 20325 #define tx_x4_credit_gen0_cl48TxEEEStates_l_TX_QUIET 4 20326 #define tx_x4_credit_gen0_cl48TxEEEStates_l_TX_SLEEP 2 20327 #define tx_x4_credit_gen0_cl48TxEEEStates_l_TX_ACTIVE 1 20328 20329 /**************************************************************************** 20330 * Enums: tx_x4_credit_gen0_cl48TxEEEStates_c 20331 */ 20332 #define tx_x4_credit_gen0_cl48TxEEEStates_c_TX_REFRESH 3 20333 #define tx_x4_credit_gen0_cl48TxEEEStates_c_TX_QUIET 2 20334 #define tx_x4_credit_gen0_cl48TxEEEStates_c_TX_SLEEP 1 20335 #define tx_x4_credit_gen0_cl48TxEEEStates_c_TX_ACTIVE 0 20336 20337 /**************************************************************************** 20338 * Enums: tx_x4_credit_gen0_cl48RxEEEStates_l 20339 */ 20340 #define tx_x4_credit_gen0_cl48RxEEEStates_l_RX_LINK_FAIL 32 20341 #define tx_x4_credit_gen0_cl48RxEEEStates_l_RX_WAKE 16 20342 #define tx_x4_credit_gen0_cl48RxEEEStates_l_RX_QUIET 8 20343 #define tx_x4_credit_gen0_cl48RxEEEStates_l_RX_DEACT 4 20344 #define tx_x4_credit_gen0_cl48RxEEEStates_l_RX_SLEEP 2 20345 #define tx_x4_credit_gen0_cl48RxEEEStates_l_RX_ACTIVE 1 20346 20347 /**************************************************************************** 20348 * Enums: tx_x4_credit_gen0_cl48RxEEEStates_c 20349 */ 20350 #define tx_x4_credit_gen0_cl48RxEEEStates_c_RX_LINK_FAIL 5 20351 #define tx_x4_credit_gen0_cl48RxEEEStates_c_RX_WAKE 4 20352 #define tx_x4_credit_gen0_cl48RxEEEStates_c_RX_QUIET 3 20353 #define tx_x4_credit_gen0_cl48RxEEEStates_c_RX_DEACT 2 20354 #define tx_x4_credit_gen0_cl48RxEEEStates_c_RX_SLEEP 1 20355 #define tx_x4_credit_gen0_cl48RxEEEStates_c_RX_ACTIVE 0 20356 20357 /**************************************************************************** 20358 * Enums: tx_x4_credit_gen0_IQP_Options 20359 */ 20360 #define tx_x4_credit_gen0_IQP_Options_i50uA 0 20361 #define tx_x4_credit_gen0_IQP_Options_i100uA 1 20362 #define tx_x4_credit_gen0_IQP_Options_i150uA 2 20363 #define tx_x4_credit_gen0_IQP_Options_i200uA 3 20364 #define tx_x4_credit_gen0_IQP_Options_i250uA 4 20365 #define tx_x4_credit_gen0_IQP_Options_i300uA 5 20366 #define tx_x4_credit_gen0_IQP_Options_i350uA 6 20367 #define tx_x4_credit_gen0_IQP_Options_i400uA 7 20368 #define tx_x4_credit_gen0_IQP_Options_i450uA 8 20369 #define tx_x4_credit_gen0_IQP_Options_i500uA 9 20370 #define tx_x4_credit_gen0_IQP_Options_i550uA 10 20371 #define tx_x4_credit_gen0_IQP_Options_i600uA 11 20372 #define tx_x4_credit_gen0_IQP_Options_i650uA 12 20373 #define tx_x4_credit_gen0_IQP_Options_i700uA 13 20374 #define tx_x4_credit_gen0_IQP_Options_i750uA 14 20375 #define tx_x4_credit_gen0_IQP_Options_i800uA 15 20376 20377 /**************************************************************************** 20378 * Enums: tx_x4_credit_gen0_IDriver_Options 20379 */ 20380 #define tx_x4_credit_gen0_IDriver_Options_v680mV 0 20381 #define tx_x4_credit_gen0_IDriver_Options_v730mV 1 20382 #define tx_x4_credit_gen0_IDriver_Options_v780mV 2 20383 #define tx_x4_credit_gen0_IDriver_Options_v830mV 3 20384 #define tx_x4_credit_gen0_IDriver_Options_v880mV 4 20385 #define tx_x4_credit_gen0_IDriver_Options_v930mV 5 20386 #define tx_x4_credit_gen0_IDriver_Options_v980mV 6 20387 #define tx_x4_credit_gen0_IDriver_Options_v1010mV 7 20388 #define tx_x4_credit_gen0_IDriver_Options_v1040mV 8 20389 #define tx_x4_credit_gen0_IDriver_Options_v1060mV 9 20390 #define tx_x4_credit_gen0_IDriver_Options_v1070mV 10 20391 #define tx_x4_credit_gen0_IDriver_Options_v1080mV 11 20392 #define tx_x4_credit_gen0_IDriver_Options_v1085mV 12 20393 #define tx_x4_credit_gen0_IDriver_Options_v1090mV 13 20394 #define tx_x4_credit_gen0_IDriver_Options_v1095mV 14 20395 #define tx_x4_credit_gen0_IDriver_Options_v1100mV 15 20396 20397 /**************************************************************************** 20398 * Enums: tx_x4_credit_gen0_operationModes 20399 */ 20400 #define tx_x4_credit_gen0_operationModes_XGXS 0 20401 #define tx_x4_credit_gen0_operationModes_XGXG_nCC 1 20402 #define tx_x4_credit_gen0_operationModes_Indlane_OS8 4 20403 #define tx_x4_credit_gen0_operationModes_IndLane_OS5 5 20404 #define tx_x4_credit_gen0_operationModes_PCI 7 20405 #define tx_x4_credit_gen0_operationModes_XGXS_nLQ 8 20406 #define tx_x4_credit_gen0_operationModes_XGXS_nLQnCC 9 20407 #define tx_x4_credit_gen0_operationModes_PBypass 10 20408 #define tx_x4_credit_gen0_operationModes_PBypass_nDSK 11 20409 #define tx_x4_credit_gen0_operationModes_ComboCoreMode 12 20410 #define tx_x4_credit_gen0_operationModes_Clocks_off 15 20411 20412 /**************************************************************************** 20413 * Enums: tx_x4_credit_gen0_actualSpeeds 20414 */ 20415 #define tx_x4_credit_gen0_actualSpeeds_dr_10M 0 20416 #define tx_x4_credit_gen0_actualSpeeds_dr_100M 1 20417 #define tx_x4_credit_gen0_actualSpeeds_dr_1G 2 20418 #define tx_x4_credit_gen0_actualSpeeds_dr_2p5G 3 20419 #define tx_x4_credit_gen0_actualSpeeds_dr_5G_X4 4 20420 #define tx_x4_credit_gen0_actualSpeeds_dr_6G_X4 5 20421 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_HiG 6 20422 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_CX4 7 20423 #define tx_x4_credit_gen0_actualSpeeds_dr_12G_HiG 8 20424 #define tx_x4_credit_gen0_actualSpeeds_dr_12p5G_X4 9 20425 #define tx_x4_credit_gen0_actualSpeeds_dr_13G_X4 10 20426 #define tx_x4_credit_gen0_actualSpeeds_dr_15G_X4 11 20427 #define tx_x4_credit_gen0_actualSpeeds_dr_16G_X4 12 20428 #define tx_x4_credit_gen0_actualSpeeds_dr_1G_KX 13 20429 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_KX4 14 20430 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_KR 15 20431 #define tx_x4_credit_gen0_actualSpeeds_dr_5G 16 20432 #define tx_x4_credit_gen0_actualSpeeds_dr_6p4G 17 20433 #define tx_x4_credit_gen0_actualSpeeds_dr_20G_X4 18 20434 #define tx_x4_credit_gen0_actualSpeeds_dr_21G_X4 19 20435 #define tx_x4_credit_gen0_actualSpeeds_dr_25G_X4 20 20436 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_HiG_DXGXS 21 20437 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_DXGXS 22 20438 #define tx_x4_credit_gen0_actualSpeeds_dr_10p5G_HiG_DXGXS 23 20439 #define tx_x4_credit_gen0_actualSpeeds_dr_10p5G_DXGXS 24 20440 #define tx_x4_credit_gen0_actualSpeeds_dr_12p773G_HiG_DXGXS 25 20441 #define tx_x4_credit_gen0_actualSpeeds_dr_12p773G_DXGXS 26 20442 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_XFI 27 20443 #define tx_x4_credit_gen0_actualSpeeds_dr_40G 28 20444 #define tx_x4_credit_gen0_actualSpeeds_dr_20G_HiG_DXGXS 29 20445 #define tx_x4_credit_gen0_actualSpeeds_dr_20G_DXGXS 30 20446 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_SFI 31 20447 #define tx_x4_credit_gen0_actualSpeeds_dr_31p5G 32 20448 #define tx_x4_credit_gen0_actualSpeeds_dr_32p7G 33 20449 #define tx_x4_credit_gen0_actualSpeeds_dr_20G_SCR 34 20450 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 20451 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_DXGXS_SCR 36 20452 #define tx_x4_credit_gen0_actualSpeeds_dr_12G_R2 37 20453 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_X2 38 20454 #define tx_x4_credit_gen0_actualSpeeds_dr_40G_KR4 39 20455 #define tx_x4_credit_gen0_actualSpeeds_dr_40G_CR4 40 20456 #define tx_x4_credit_gen0_actualSpeeds_dr_100G_CR10 41 20457 #define tx_x4_credit_gen0_actualSpeeds_dr_15p75G_DXGXS 44 20458 #define tx_x4_credit_gen0_actualSpeeds_dr_20G_KR2 57 20459 #define tx_x4_credit_gen0_actualSpeeds_dr_20G_CR2 58 20460 20461 /**************************************************************************** 20462 * Enums: tx_x4_credit_gen0_actualSpeedsMisc1 20463 */ 20464 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_2500BRCM_X1 16 20465 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_5000BRCM_X4 17 20466 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_6000BRCM_X4 18 20467 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_10GHiGig_X4 19 20468 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_10GBASE_CX4 20 20469 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_12GHiGig_X4 21 20470 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 20471 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_13GHiGig_X4 23 20472 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_15GHiGig_X4 24 20473 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_16GHiGig_X4 25 20474 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_5000BRCM_X1 26 20475 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_6363BRCM_X1 27 20476 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_20GHiGig_X4 28 20477 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_21GHiGig_X4 29 20478 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 20479 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 20480 20481 /**************************************************************************** 20482 * Enums: tx_x4_credit_gen0_IndLaneModes 20483 */ 20484 #define tx_x4_credit_gen0_IndLaneModes_SWSDR_div2 0 20485 #define tx_x4_credit_gen0_IndLaneModes_SWSDR_div1 1 20486 #define tx_x4_credit_gen0_IndLaneModes_DWSDR_div2 2 20487 #define tx_x4_credit_gen0_IndLaneModes_DWSDR_div1 3 20488 20489 /**************************************************************************** 20490 * Enums: tx_x4_credit_gen0_prbsSelect 20491 */ 20492 #define tx_x4_credit_gen0_prbsSelect_prbs7 0 20493 #define tx_x4_credit_gen0_prbsSelect_prbs15 1 20494 #define tx_x4_credit_gen0_prbsSelect_prbs23 2 20495 #define tx_x4_credit_gen0_prbsSelect_prbs31 3 20496 20497 /**************************************************************************** 20498 * Enums: tx_x4_credit_gen0_vcoDivider 20499 */ 20500 #define tx_x4_credit_gen0_vcoDivider_div32 0 20501 #define tx_x4_credit_gen0_vcoDivider_div36 1 20502 #define tx_x4_credit_gen0_vcoDivider_div40 2 20503 #define tx_x4_credit_gen0_vcoDivider_div42 3 20504 #define tx_x4_credit_gen0_vcoDivider_div48 4 20505 #define tx_x4_credit_gen0_vcoDivider_div50 5 20506 #define tx_x4_credit_gen0_vcoDivider_div52 6 20507 #define tx_x4_credit_gen0_vcoDivider_div54 7 20508 #define tx_x4_credit_gen0_vcoDivider_div60 8 20509 #define tx_x4_credit_gen0_vcoDivider_div64 9 20510 #define tx_x4_credit_gen0_vcoDivider_div66 10 20511 #define tx_x4_credit_gen0_vcoDivider_div68 11 20512 #define tx_x4_credit_gen0_vcoDivider_div70 12 20513 #define tx_x4_credit_gen0_vcoDivider_div80 13 20514 #define tx_x4_credit_gen0_vcoDivider_div92 14 20515 #define tx_x4_credit_gen0_vcoDivider_div100 15 20516 20517 /**************************************************************************** 20518 * Enums: tx_x4_credit_gen0_refClkSelect 20519 */ 20520 #define tx_x4_credit_gen0_refClkSelect_clk_25MHz 0 20521 #define tx_x4_credit_gen0_refClkSelect_clk_100MHz 1 20522 #define tx_x4_credit_gen0_refClkSelect_clk_125MHz 2 20523 #define tx_x4_credit_gen0_refClkSelect_clk_156p25MHz 3 20524 #define tx_x4_credit_gen0_refClkSelect_clk_187p5MHz 4 20525 #define tx_x4_credit_gen0_refClkSelect_clk_161p25Mhz 5 20526 #define tx_x4_credit_gen0_refClkSelect_clk_50Mhz 6 20527 #define tx_x4_credit_gen0_refClkSelect_clk_106p25Mhz 7 20528 20529 /**************************************************************************** 20530 * Enums: tx_x4_credit_gen0_aerMMDdevTypeSelect 20531 */ 20532 #define tx_x4_credit_gen0_aerMMDdevTypeSelect_combo_core 0 20533 #define tx_x4_credit_gen0_aerMMDdevTypeSelect_PMA_PMD 1 20534 #define tx_x4_credit_gen0_aerMMDdevTypeSelect_PCS 3 20535 #define tx_x4_credit_gen0_aerMMDdevTypeSelect_PHY 4 20536 #define tx_x4_credit_gen0_aerMMDdevTypeSelect_DTE 5 20537 #define tx_x4_credit_gen0_aerMMDdevTypeSelect_CL73_AN 7 20538 20539 /**************************************************************************** 20540 * Enums: tx_x4_credit_gen0_aerMMDportSelect 20541 */ 20542 #define tx_x4_credit_gen0_aerMMDportSelect_ln0 0 20543 #define tx_x4_credit_gen0_aerMMDportSelect_ln1 1 20544 #define tx_x4_credit_gen0_aerMMDportSelect_ln2 2 20545 #define tx_x4_credit_gen0_aerMMDportSelect_ln3 3 20546 #define tx_x4_credit_gen0_aerMMDportSelect_BCST_ln0_1_2_3 511 20547 #define tx_x4_credit_gen0_aerMMDportSelect_BCST_ln0_1 512 20548 #define tx_x4_credit_gen0_aerMMDportSelect_BCST_ln2_3 513 20549 20550 /**************************************************************************** 20551 * Enums: tx_x4_credit_gen0_firmwareModeSelect 20552 */ 20553 #define tx_x4_credit_gen0_firmwareModeSelect_DEFAULT 0 20554 #define tx_x4_credit_gen0_firmwareModeSelect_SFP_OPT_LR 1 20555 #define tx_x4_credit_gen0_firmwareModeSelect_SFP_DAC 2 20556 #define tx_x4_credit_gen0_firmwareModeSelect_XLAUI 3 20557 #define tx_x4_credit_gen0_firmwareModeSelect_LONG_CH_6G 4 20558 20559 /**************************************************************************** 20560 * Enums: tx_x4_credit_gen0_tempIdxSelect 20561 */ 20562 #define tx_x4_credit_gen0_tempIdxSelect_LTE__22p9C 15 20563 #define tx_x4_credit_gen0_tempIdxSelect_LTE__12p6C 14 20564 #define tx_x4_credit_gen0_tempIdxSelect_LTE__3p0C 13 20565 #define tx_x4_credit_gen0_tempIdxSelect_LTE_6p7C 12 20566 #define tx_x4_credit_gen0_tempIdxSelect_LTE_16p4C 11 20567 #define tx_x4_credit_gen0_tempIdxSelect_LTE_26p6C 10 20568 #define tx_x4_credit_gen0_tempIdxSelect_LTE_36p3C 9 20569 #define tx_x4_credit_gen0_tempIdxSelect_LTE_46p0C 8 20570 #define tx_x4_credit_gen0_tempIdxSelect_LTE_56p2C 7 20571 #define tx_x4_credit_gen0_tempIdxSelect_LTE_65p9C 6 20572 #define tx_x4_credit_gen0_tempIdxSelect_LTE_75p6C 5 20573 #define tx_x4_credit_gen0_tempIdxSelect_LTE_85p3C 4 20574 #define tx_x4_credit_gen0_tempIdxSelect_LTE_95p5C 3 20575 #define tx_x4_credit_gen0_tempIdxSelect_LTE_105p2C 2 20576 #define tx_x4_credit_gen0_tempIdxSelect_LTE_114p9C 1 20577 #define tx_x4_credit_gen0_tempIdxSelect_LTE_125p1C 0 20578 20579 /**************************************************************************** 20580 * Enums: tx_x4_credit_gen0_port_mode 20581 */ 20582 #define tx_x4_credit_gen0_port_mode_QUAD_PORT 0 20583 #define tx_x4_credit_gen0_port_mode_TRI_1_PORT 1 20584 #define tx_x4_credit_gen0_port_mode_TRI_2_PORT 2 20585 #define tx_x4_credit_gen0_port_mode_DUAL_PORT 3 20586 #define tx_x4_credit_gen0_port_mode_SINGLE_PORT 4 20587 20588 /**************************************************************************** 20589 * Enums: tx_x4_credit_gen0_rev_letter_enum 20590 */ 20591 #define tx_x4_credit_gen0_rev_letter_enum_REV_A 0 20592 #define tx_x4_credit_gen0_rev_letter_enum_REV_B 1 20593 #define tx_x4_credit_gen0_rev_letter_enum_REV_C 2 20594 #define tx_x4_credit_gen0_rev_letter_enum_REV_D 3 20595 20596 /**************************************************************************** 20597 * Enums: tx_x4_credit_gen0_rev_number_enum 20598 */ 20599 #define tx_x4_credit_gen0_rev_number_enum_REV_0 0 20600 #define tx_x4_credit_gen0_rev_number_enum_REV_1 1 20601 #define tx_x4_credit_gen0_rev_number_enum_REV_2 2 20602 #define tx_x4_credit_gen0_rev_number_enum_REV_3 3 20603 #define tx_x4_credit_gen0_rev_number_enum_REV_4 4 20604 #define tx_x4_credit_gen0_rev_number_enum_REV_5 5 20605 #define tx_x4_credit_gen0_rev_number_enum_REV_6 6 20606 #define tx_x4_credit_gen0_rev_number_enum_REV_7 7 20607 20608 /**************************************************************************** 20609 * Enums: tx_x4_credit_gen0_bonding_enum 20610 */ 20611 #define tx_x4_credit_gen0_bonding_enum_WIRE_BOND 0 20612 #define tx_x4_credit_gen0_bonding_enum_FLIP_CHIP 1 20613 20614 /**************************************************************************** 20615 * Enums: tx_x4_credit_gen0_tech_process 20616 */ 20617 #define tx_x4_credit_gen0_tech_process_PROCESS_90NM 0 20618 #define tx_x4_credit_gen0_tech_process_PROCESS_65NM 1 20619 #define tx_x4_credit_gen0_tech_process_PROCESS_40NM 2 20620 #define tx_x4_credit_gen0_tech_process_PROCESS_28NM 3 20621 #define tx_x4_credit_gen0_tech_process_PROCESS_16NM 4 20622 20623 /**************************************************************************** 20624 * Enums: tx_x4_credit_gen0_model_num 20625 */ 20626 #define tx_x4_credit_gen0_model_num_SERDES_CL73 0 20627 #define tx_x4_credit_gen0_model_num_XGXS_16G 1 20628 #define tx_x4_credit_gen0_model_num_HYPERCORE 2 20629 #define tx_x4_credit_gen0_model_num_HYPERLITE 3 20630 #define tx_x4_credit_gen0_model_num_PCIE_G2_PIPE 4 20631 #define tx_x4_credit_gen0_model_num_SERDES_1p25GBd 5 20632 #define tx_x4_credit_gen0_model_num_SATA2 6 20633 #define tx_x4_credit_gen0_model_num_QSGMII 7 20634 #define tx_x4_credit_gen0_model_num_XGXS10G 8 20635 #define tx_x4_credit_gen0_model_num_WARPCORE 9 20636 #define tx_x4_credit_gen0_model_num_XFICORE 10 20637 #define tx_x4_credit_gen0_model_num_RXFI 11 20638 #define tx_x4_credit_gen0_model_num_WARPLITE 12 20639 #define tx_x4_credit_gen0_model_num_PENTACORE 13 20640 #define tx_x4_credit_gen0_model_num_ESM 14 20641 #define tx_x4_credit_gen0_model_num_QUAD_SGMII 15 20642 #define tx_x4_credit_gen0_model_num_WARPCORE_3 16 20643 #define tx_x4_credit_gen0_model_num_TSC 17 20644 #define tx_x4_credit_gen0_model_num_TSC4E 18 20645 #define tx_x4_credit_gen0_model_num_TSC12E 19 20646 #define tx_x4_credit_gen0_model_num_TSC4F 20 20647 #define tx_x4_credit_gen0_model_num_TSC4F_GEN2 21 20648 #define tx_x4_credit_gen0_model_num_XGXS_CL73_90NM 29 20649 #define tx_x4_credit_gen0_model_num_SERDES_CL73_90NM 30 20650 #define tx_x4_credit_gen0_model_num_WARPCORE3 32 20651 #define tx_x4_credit_gen0_model_num_WARPCORE4_TSC 33 20652 #define tx_x4_credit_gen0_model_num_RXAUI 34 20653 20654 /**************************************************************************** 20655 * Enums: tx_x4_credit_gen0_payload 20656 */ 20657 #define tx_x4_credit_gen0_payload_REPEAT_2_BYTES 0 20658 #define tx_x4_credit_gen0_payload_RAMPING 1 20659 #define tx_x4_credit_gen0_payload_CL48_CRPAT 2 20660 #define tx_x4_credit_gen0_payload_CL48_CJPAT 3 20661 #define tx_x4_credit_gen0_payload_CL36_LONG_CRPAT 4 20662 #define tx_x4_credit_gen0_payload_CL36_SHORT_CRPAT 5 20663 20664 /**************************************************************************** 20665 * Enums: tx_x4_credit_gen0_sc 20666 */ 20667 #define tx_x4_credit_gen0_sc_S_10G_CR1 0 20668 #define tx_x4_credit_gen0_sc_S_10G_KR1 1 20669 #define tx_x4_credit_gen0_sc_S_10G_X1 2 20670 #define tx_x4_credit_gen0_sc_S_10G_HG2_CR1 4 20671 #define tx_x4_credit_gen0_sc_S_10G_HG2_KR1 5 20672 #define tx_x4_credit_gen0_sc_S_10G_HG2_X1 6 20673 #define tx_x4_credit_gen0_sc_S_20G_CR1 8 20674 #define tx_x4_credit_gen0_sc_S_20G_KR1 9 20675 #define tx_x4_credit_gen0_sc_S_20G_X1 10 20676 #define tx_x4_credit_gen0_sc_S_20G_HG2_CR1 12 20677 #define tx_x4_credit_gen0_sc_S_20G_HG2_KR1 13 20678 #define tx_x4_credit_gen0_sc_S_20G_HG2_X1 14 20679 #define tx_x4_credit_gen0_sc_S_25G_CR1 16 20680 #define tx_x4_credit_gen0_sc_S_25G_KR1 17 20681 #define tx_x4_credit_gen0_sc_S_25G_X1 18 20682 #define tx_x4_credit_gen0_sc_S_25G_HG2_CR1 20 20683 #define tx_x4_credit_gen0_sc_S_25G_HG2_KR1 21 20684 #define tx_x4_credit_gen0_sc_S_25G_HG2_X1 22 20685 #define tx_x4_credit_gen0_sc_S_20G_CR2 24 20686 #define tx_x4_credit_gen0_sc_S_20G_KR2 25 20687 #define tx_x4_credit_gen0_sc_S_20G_X2 26 20688 #define tx_x4_credit_gen0_sc_S_20G_HG2_CR2 28 20689 #define tx_x4_credit_gen0_sc_S_20G_HG2_KR2 29 20690 #define tx_x4_credit_gen0_sc_S_20G_HG2_X2 30 20691 #define tx_x4_credit_gen0_sc_S_40G_CR2 32 20692 #define tx_x4_credit_gen0_sc_S_40G_KR2 33 20693 #define tx_x4_credit_gen0_sc_S_40G_X2 34 20694 #define tx_x4_credit_gen0_sc_S_40G_HG2_CR2 36 20695 #define tx_x4_credit_gen0_sc_S_40G_HG2_KR2 37 20696 #define tx_x4_credit_gen0_sc_S_40G_HG2_X2 38 20697 #define tx_x4_credit_gen0_sc_S_40G_CR4 40 20698 #define tx_x4_credit_gen0_sc_S_40G_KR4 41 20699 #define tx_x4_credit_gen0_sc_S_40G_X4 42 20700 #define tx_x4_credit_gen0_sc_S_40G_HG2_CR4 44 20701 #define tx_x4_credit_gen0_sc_S_40G_HG2_KR4 45 20702 #define tx_x4_credit_gen0_sc_S_40G_HG2_X4 46 20703 #define tx_x4_credit_gen0_sc_S_50G_CR2 48 20704 #define tx_x4_credit_gen0_sc_S_50G_KR2 49 20705 #define tx_x4_credit_gen0_sc_S_50G_X2 50 20706 #define tx_x4_credit_gen0_sc_S_50G_HG2_CR2 52 20707 #define tx_x4_credit_gen0_sc_S_50G_HG2_KR2 53 20708 #define tx_x4_credit_gen0_sc_S_50G_HG2_X2 54 20709 #define tx_x4_credit_gen0_sc_S_50G_CR4 56 20710 #define tx_x4_credit_gen0_sc_S_50G_KR4 57 20711 #define tx_x4_credit_gen0_sc_S_50G_X4 58 20712 #define tx_x4_credit_gen0_sc_S_50G_HG2_CR4 60 20713 #define tx_x4_credit_gen0_sc_S_50G_HG2_KR4 61 20714 #define tx_x4_credit_gen0_sc_S_50G_HG2_X4 62 20715 #define tx_x4_credit_gen0_sc_S_100G_CR4 64 20716 #define tx_x4_credit_gen0_sc_S_100G_KR4 65 20717 #define tx_x4_credit_gen0_sc_S_100G_X4 66 20718 #define tx_x4_credit_gen0_sc_S_100G_HG2_CR4 68 20719 #define tx_x4_credit_gen0_sc_S_100G_HG2_KR4 69 20720 #define tx_x4_credit_gen0_sc_S_100G_HG2_X4 70 20721 #define tx_x4_credit_gen0_sc_S_CL73_20GVCO 72 20722 #define tx_x4_credit_gen0_sc_S_CL73_25GVCO 80 20723 #define tx_x4_credit_gen0_sc_S_CL36_20GVCO 88 20724 #define tx_x4_credit_gen0_sc_S_CL36_25GVCO 96 20725 #define tx_x4_credit_gen0_sc_S_25G_CR_IEEE 112 20726 #define tx_x4_credit_gen0_sc_S_25G_CRS_IEEE 113 20727 #define tx_x4_credit_gen0_sc_S_25G_KR_IEEE 114 20728 #define tx_x4_credit_gen0_sc_S_25G_KRS_IEEE 115 20729 20730 /**************************************************************************** 20731 * Enums: tx_x4_credit_gen0_t_fifo_modes 20732 */ 20733 #define tx_x4_credit_gen0_t_fifo_modes_T_FIFO_INSERT_NO_AM 0 20734 #define tx_x4_credit_gen0_t_fifo_modes_T_FIFO_INSERT_4_AM 1 20735 #define tx_x4_credit_gen0_t_fifo_modes_T_FIFO_INSERT_20_AM 2 20736 #define tx_x4_credit_gen0_t_fifo_modes_T_FIFO_INSERT_2_AM 3 20737 20738 /**************************************************************************** 20739 * Enums: tx_x4_credit_gen0_t_enc_modes 20740 */ 20741 #define tx_x4_credit_gen0_t_enc_modes_T_ENC_MODE_BYPASS 0 20742 #define tx_x4_credit_gen0_t_enc_modes_T_ENC_MODE_CL49 1 20743 #define tx_x4_credit_gen0_t_enc_modes_T_ENC_MODE_CL82 2 20744 20745 /**************************************************************************** 20746 * Enums: tx_x4_credit_gen0_btmx_mode 20747 */ 20748 #define tx_x4_credit_gen0_btmx_mode_BS_BTMX_MODE_1to1 0 20749 #define tx_x4_credit_gen0_btmx_mode_BS_BTMX_MODE_2to1 1 20750 #define tx_x4_credit_gen0_btmx_mode_BS_BTMX_MODE_5to1 2 20751 20752 /**************************************************************************** 20753 * Enums: tx_x4_credit_gen0_t_type_cl82 20754 */ 20755 #define tx_x4_credit_gen0_t_type_cl82_T_TYPE_B1 5 20756 #define tx_x4_credit_gen0_t_type_cl82_T_TYPE_C 4 20757 #define tx_x4_credit_gen0_t_type_cl82_T_TYPE_S 3 20758 #define tx_x4_credit_gen0_t_type_cl82_T_TYPE_T 2 20759 #define tx_x4_credit_gen0_t_type_cl82_T_TYPE_D 1 20760 #define tx_x4_credit_gen0_t_type_cl82_T_TYPE_E 0 20761 20762 /**************************************************************************** 20763 * Enums: tx_x4_credit_gen0_txsm_state_cl82 20764 */ 20765 #define tx_x4_credit_gen0_txsm_state_cl82_TX_HIG_END 6 20766 #define tx_x4_credit_gen0_txsm_state_cl82_TX_HIG_START 5 20767 #define tx_x4_credit_gen0_txsm_state_cl82_TX_E 4 20768 #define tx_x4_credit_gen0_txsm_state_cl82_TX_T 3 20769 #define tx_x4_credit_gen0_txsm_state_cl82_TX_D 2 20770 #define tx_x4_credit_gen0_txsm_state_cl82_TX_C 1 20771 #define tx_x4_credit_gen0_txsm_state_cl82_TX_INIT 0 20772 20773 /**************************************************************************** 20774 * Enums: tx_x4_credit_gen0_ltxsm_state_cl82 20775 */ 20776 #define tx_x4_credit_gen0_ltxsm_state_cl82_TX_HIG_END 64 20777 #define tx_x4_credit_gen0_ltxsm_state_cl82_TX_HIG_START 32 20778 #define tx_x4_credit_gen0_ltxsm_state_cl82_TX_E 16 20779 #define tx_x4_credit_gen0_ltxsm_state_cl82_TX_T 8 20780 #define tx_x4_credit_gen0_ltxsm_state_cl82_TX_D 4 20781 #define tx_x4_credit_gen0_ltxsm_state_cl82_TX_C 2 20782 #define tx_x4_credit_gen0_ltxsm_state_cl82_TX_INIT 1 20783 20784 /**************************************************************************** 20785 * Enums: tx_x4_credit_gen0_r_type_coded_cl82 20786 */ 20787 #define tx_x4_credit_gen0_r_type_coded_cl82_R_TYPE_B1 32 20788 #define tx_x4_credit_gen0_r_type_coded_cl82_R_TYPE_C 16 20789 #define tx_x4_credit_gen0_r_type_coded_cl82_R_TYPE_S 8 20790 #define tx_x4_credit_gen0_r_type_coded_cl82_R_TYPE_T 4 20791 #define tx_x4_credit_gen0_r_type_coded_cl82_R_TYPE_D 2 20792 #define tx_x4_credit_gen0_r_type_coded_cl82_R_TYPE_E 1 20793 20794 /**************************************************************************** 20795 * Enums: tx_x4_credit_gen0_rxsm_state_cl82 20796 */ 20797 #define tx_x4_credit_gen0_rxsm_state_cl82_RX_HIG_END 64 20798 #define tx_x4_credit_gen0_rxsm_state_cl82_RX_HIG_START 32 20799 #define tx_x4_credit_gen0_rxsm_state_cl82_RX_E 16 20800 #define tx_x4_credit_gen0_rxsm_state_cl82_RX_T 8 20801 #define tx_x4_credit_gen0_rxsm_state_cl82_RX_D 4 20802 #define tx_x4_credit_gen0_rxsm_state_cl82_RX_C 2 20803 #define tx_x4_credit_gen0_rxsm_state_cl82_RX_INIT 1 20804 20805 /**************************************************************************** 20806 * Enums: tx_x4_credit_gen0_deskew_state 20807 */ 20808 #define tx_x4_credit_gen0_deskew_state_ALIGN_ACQUIRED 2 20809 #define tx_x4_credit_gen0_deskew_state_LOSS_OF_ALIGNMENT 1 20810 20811 /**************************************************************************** 20812 * Enums: tx_x4_credit_gen0_os_mode_enum 20813 */ 20814 #define tx_x4_credit_gen0_os_mode_enum_OS_MODE_1 0 20815 #define tx_x4_credit_gen0_os_mode_enum_OS_MODE_2 1 20816 #define tx_x4_credit_gen0_os_mode_enum_OS_MODE_4 2 20817 #define tx_x4_credit_gen0_os_mode_enum_OS_MODE_16p5 8 20818 #define tx_x4_credit_gen0_os_mode_enum_OS_MODE_20p625 12 20819 20820 /**************************************************************************** 20821 * Enums: tx_x4_credit_gen0_scr_modes 20822 */ 20823 #define tx_x4_credit_gen0_scr_modes_T_SCR_MODE_BYPASS 0 20824 #define tx_x4_credit_gen0_scr_modes_T_SCR_MODE_CL49 1 20825 #define tx_x4_credit_gen0_scr_modes_T_SCR_MODE_40G_2_LANE 2 20826 #define tx_x4_credit_gen0_scr_modes_T_SCR_MODE_100G 3 20827 #define tx_x4_credit_gen0_scr_modes_T_SCR_MODE_20G 4 20828 #define tx_x4_credit_gen0_scr_modes_T_SCR_MODE_40G_4_LANE 5 20829 20830 /**************************************************************************** 20831 * Enums: tx_x4_credit_gen0_descr_modes 20832 */ 20833 #define tx_x4_credit_gen0_descr_modes_R_DESCR_MODE_BYPASS 0 20834 #define tx_x4_credit_gen0_descr_modes_R_DESCR_MODE_CL49 1 20835 #define tx_x4_credit_gen0_descr_modes_R_DESCR_MODE_CL82 2 20836 20837 /**************************************************************************** 20838 * Enums: tx_x4_credit_gen0_r_dec_tl_mode 20839 */ 20840 #define tx_x4_credit_gen0_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 20841 #define tx_x4_credit_gen0_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 20842 #define tx_x4_credit_gen0_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 20843 20844 /**************************************************************************** 20845 * Enums: tx_x4_credit_gen0_r_dec_fsm_mode 20846 */ 20847 #define tx_x4_credit_gen0_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 20848 #define tx_x4_credit_gen0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 20849 #define tx_x4_credit_gen0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 20850 20851 /**************************************************************************** 20852 * Enums: tx_x4_credit_gen0_r_deskew_mode 20853 */ 20854 #define tx_x4_credit_gen0_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 20855 #define tx_x4_credit_gen0_r_deskew_mode_R_DESKEW_MODE_20G 1 20856 #define tx_x4_credit_gen0_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 20857 #define tx_x4_credit_gen0_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 20858 #define tx_x4_credit_gen0_r_deskew_mode_R_DESKEW_MODE_100G 4 20859 #define tx_x4_credit_gen0_r_deskew_mode_R_DESKEW_MODE_CL49 5 20860 #define tx_x4_credit_gen0_r_deskew_mode_R_DESKEW_MODE_CL91_QUAD 6 20861 #define tx_x4_credit_gen0_r_deskew_mode_R_DESKEW_MODE_CL91_SINGLE_BRCM 7 20862 #define tx_x4_credit_gen0_r_deskew_mode_R_DESKEW_MODE_CL91_DUAL_BRCM 8 20863 #define tx_x4_credit_gen0_r_deskew_mode_R_DESKEW_MODE_CL91_FC 9 20864 20865 /**************************************************************************** 20866 * Enums: tx_x4_credit_gen0_bs_dist_modes 20867 */ 20868 #define tx_x4_credit_gen0_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 20869 #define tx_x4_credit_gen0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 20870 #define tx_x4_credit_gen0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 20871 #define tx_x4_credit_gen0_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 20872 20873 /**************************************************************************** 20874 * Enums: tx_x4_credit_gen0_cl49_t_type 20875 */ 20876 #define tx_x4_credit_gen0_cl49_t_type_BAD_T_TYPE 15 20877 #define tx_x4_credit_gen0_cl49_t_type_T_TYPE_B0 11 20878 #define tx_x4_credit_gen0_cl49_t_type_T_TYPE_OB 10 20879 #define tx_x4_credit_gen0_cl49_t_type_T_TYPE_B1 9 20880 #define tx_x4_credit_gen0_cl49_t_type_T_TYPE_DB 8 20881 #define tx_x4_credit_gen0_cl49_t_type_T_TYPE_FC 7 20882 #define tx_x4_credit_gen0_cl49_t_type_T_TYPE_TB 6 20883 #define tx_x4_credit_gen0_cl49_t_type_T_TYPE_LI 5 20884 #define tx_x4_credit_gen0_cl49_t_type_T_TYPE_C 4 20885 #define tx_x4_credit_gen0_cl49_t_type_T_TYPE_S 3 20886 #define tx_x4_credit_gen0_cl49_t_type_T_TYPE_T 2 20887 #define tx_x4_credit_gen0_cl49_t_type_T_TYPE_D 1 20888 #define tx_x4_credit_gen0_cl49_t_type_T_TYPE_E 0 20889 20890 /**************************************************************************** 20891 * Enums: tx_x4_credit_gen0_cl49_txsm_states 20892 */ 20893 #define tx_x4_credit_gen0_cl49_txsm_states_TX_HIG_END 7 20894 #define tx_x4_credit_gen0_cl49_txsm_states_TX_HIG_START 6 20895 #define tx_x4_credit_gen0_cl49_txsm_states_TX_LI 5 20896 #define tx_x4_credit_gen0_cl49_txsm_states_TX_E 4 20897 #define tx_x4_credit_gen0_cl49_txsm_states_TX_T 3 20898 #define tx_x4_credit_gen0_cl49_txsm_states_TX_D 2 20899 #define tx_x4_credit_gen0_cl49_txsm_states_TX_C 1 20900 #define tx_x4_credit_gen0_cl49_txsm_states_TX_INIT 0 20901 20902 /**************************************************************************** 20903 * Enums: tx_x4_credit_gen0_cl49_ltxsm_states 20904 */ 20905 #define tx_x4_credit_gen0_cl49_ltxsm_states_TX_HIG_END 128 20906 #define tx_x4_credit_gen0_cl49_ltxsm_states_TX_HIG_START 64 20907 #define tx_x4_credit_gen0_cl49_ltxsm_states_TX_LI 32 20908 #define tx_x4_credit_gen0_cl49_ltxsm_states_TX_E 16 20909 #define tx_x4_credit_gen0_cl49_ltxsm_states_TX_T 8 20910 #define tx_x4_credit_gen0_cl49_ltxsm_states_TX_D 4 20911 #define tx_x4_credit_gen0_cl49_ltxsm_states_TX_C 2 20912 #define tx_x4_credit_gen0_cl49_ltxsm_states_TX_INIT 1 20913 20914 /**************************************************************************** 20915 * Enums: tx_x4_credit_gen0_burst_error_mode 20916 */ 20917 #define tx_x4_credit_gen0_burst_error_mode_BURST_ERROR_11_BITS 0 20918 #define tx_x4_credit_gen0_burst_error_mode_BURST_ERROR_16_BITS 1 20919 #define tx_x4_credit_gen0_burst_error_mode_BURST_ERROR_17_BITS 2 20920 #define tx_x4_credit_gen0_burst_error_mode_BURST_ERROR_18_BITS 3 20921 #define tx_x4_credit_gen0_burst_error_mode_BURST_ERROR_19_BITS 4 20922 #define tx_x4_credit_gen0_burst_error_mode_BURST_ERROR_20_BITS 5 20923 #define tx_x4_credit_gen0_burst_error_mode_BURST_ERROR_21_BITS 6 20924 #define tx_x4_credit_gen0_burst_error_mode_BURST_ERROR_22_BITS 7 20925 #define tx_x4_credit_gen0_burst_error_mode_BURST_ERROR_23_BITS 8 20926 #define tx_x4_credit_gen0_burst_error_mode_BURST_ERROR_24_BITS 9 20927 #define tx_x4_credit_gen0_burst_error_mode_BURST_ERROR_25_BITS 10 20928 #define tx_x4_credit_gen0_burst_error_mode_BURST_ERROR_26_BITS 11 20929 #define tx_x4_credit_gen0_burst_error_mode_BURST_ERROR_27_BITS 12 20930 #define tx_x4_credit_gen0_burst_error_mode_BURST_ERROR_28_BITS 13 20931 #define tx_x4_credit_gen0_burst_error_mode_BURST_ERROR_29_BITS 14 20932 #define tx_x4_credit_gen0_burst_error_mode_BURST_ERROR_30_BITS 15 20933 #define tx_x4_credit_gen0_burst_error_mode_BURST_ERROR_31_BITS 16 20934 #define tx_x4_credit_gen0_burst_error_mode_BURST_ERROR_32_BITS 17 20935 #define tx_x4_credit_gen0_burst_error_mode_BURST_ERROR_33_BITS 18 20936 #define tx_x4_credit_gen0_burst_error_mode_BURST_ERROR_34_BITS 19 20937 #define tx_x4_credit_gen0_burst_error_mode_BURST_ERROR_35_BITS 20 20938 #define tx_x4_credit_gen0_burst_error_mode_BURST_ERROR_36_BITS 21 20939 #define tx_x4_credit_gen0_burst_error_mode_BURST_ERROR_37_BITS 22 20940 #define tx_x4_credit_gen0_burst_error_mode_BURST_ERROR_38_BITS 23 20941 #define tx_x4_credit_gen0_burst_error_mode_BURST_ERROR_39_BITS 24 20942 #define tx_x4_credit_gen0_burst_error_mode_BURST_ERROR_40_BITS 25 20943 #define tx_x4_credit_gen0_burst_error_mode_BURST_ERROR_41_BITS 26 20944 20945 /**************************************************************************** 20946 * Enums: tx_x4_credit_gen0_bermon_state 20947 */ 20948 #define tx_x4_credit_gen0_bermon_state_HI_BER 4 20949 #define tx_x4_credit_gen0_bermon_state_GOOD_BER 3 20950 #define tx_x4_credit_gen0_bermon_state_BER_TEST_SH 2 20951 #define tx_x4_credit_gen0_bermon_state_START_TIMER 1 20952 #define tx_x4_credit_gen0_bermon_state_BER_MT_INIT 0 20953 20954 /**************************************************************************** 20955 * Enums: tx_x4_credit_gen0_rxsm_state_cl49 20956 */ 20957 #define tx_x4_credit_gen0_rxsm_state_cl49_RX_HIG_END 128 20958 #define tx_x4_credit_gen0_rxsm_state_cl49_RX_HIG_START 64 20959 #define tx_x4_credit_gen0_rxsm_state_cl49_RX_LI 32 20960 #define tx_x4_credit_gen0_rxsm_state_cl49_RX_E 16 20961 #define tx_x4_credit_gen0_rxsm_state_cl49_RX_T 8 20962 #define tx_x4_credit_gen0_rxsm_state_cl49_RX_D 4 20963 #define tx_x4_credit_gen0_rxsm_state_cl49_RX_C 2 20964 #define tx_x4_credit_gen0_rxsm_state_cl49_RX_INIT 1 20965 20966 /**************************************************************************** 20967 * Enums: tx_x4_credit_gen0_r_type 20968 */ 20969 #define tx_x4_credit_gen0_r_type_BAD_R_TYPE 15 20970 #define tx_x4_credit_gen0_r_type_R_TYPE_B0 11 20971 #define tx_x4_credit_gen0_r_type_R_TYPE_OB 10 20972 #define tx_x4_credit_gen0_r_type_R_TYPE_B1 9 20973 #define tx_x4_credit_gen0_r_type_R_TYPE_DB 8 20974 #define tx_x4_credit_gen0_r_type_R_TYPE_FC 7 20975 #define tx_x4_credit_gen0_r_type_R_TYPE_TB 6 20976 #define tx_x4_credit_gen0_r_type_R_TYPE_LI 5 20977 #define tx_x4_credit_gen0_r_type_R_TYPE_C 4 20978 #define tx_x4_credit_gen0_r_type_R_TYPE_S 3 20979 #define tx_x4_credit_gen0_r_type_R_TYPE_T 2 20980 #define tx_x4_credit_gen0_r_type_R_TYPE_D 1 20981 #define tx_x4_credit_gen0_r_type_R_TYPE_E 0 20982 20983 /**************************************************************************** 20984 * Enums: tx_x4_credit_gen0_am_lock_state 20985 */ 20986 #define tx_x4_credit_gen0_am_lock_state_INVALID_AM 512 20987 #define tx_x4_credit_gen0_am_lock_state_GOOD_AM 256 20988 #define tx_x4_credit_gen0_am_lock_state_COMP_AM 128 20989 #define tx_x4_credit_gen0_am_lock_state_TIMER_2 64 20990 #define tx_x4_credit_gen0_am_lock_state_AM_2_GOOD 32 20991 #define tx_x4_credit_gen0_am_lock_state_COMP_2ND 16 20992 #define tx_x4_credit_gen0_am_lock_state_TIMER_1 8 20993 #define tx_x4_credit_gen0_am_lock_state_FIND_1ST 4 20994 #define tx_x4_credit_gen0_am_lock_state_AM_RESET_CNT 2 20995 #define tx_x4_credit_gen0_am_lock_state_AM_LOCK_INIT 1 20996 20997 /**************************************************************************** 20998 * Enums: tx_x4_credit_gen0_msg_selector 20999 */ 21000 #define tx_x4_credit_gen0_msg_selector_RESERVED 0 21001 #define tx_x4_credit_gen0_msg_selector_VALUE_802p3 1 21002 #define tx_x4_credit_gen0_msg_selector_VALUE_802p9 2 21003 #define tx_x4_credit_gen0_msg_selector_VALUE_802p5 3 21004 #define tx_x4_credit_gen0_msg_selector_VALUE_1394 4 21005 21006 /**************************************************************************** 21007 * Enums: tx_x4_credit_gen0_synce_enum 21008 */ 21009 #define tx_x4_credit_gen0_synce_enum_SYNCE_NO_DIV 0 21010 #define tx_x4_credit_gen0_synce_enum_SYNCE_DIV_7 1 21011 #define tx_x4_credit_gen0_synce_enum_SYNCE_DIV_11 2 21012 21013 /**************************************************************************** 21014 * Enums: tx_x4_credit_gen0_synce_enum_stage0 21015 */ 21016 #define tx_x4_credit_gen0_synce_enum_stage0_SYNCE_NO_DIV 0 21017 #define tx_x4_credit_gen0_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 21018 #define tx_x4_credit_gen0_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 21019 21020 /**************************************************************************** 21021 * Enums: tx_x4_credit_gen0_cl91_sync_state 21022 */ 21023 #define tx_x4_credit_gen0_cl91_sync_state_FIND_1ST 0 21024 #define tx_x4_credit_gen0_cl91_sync_state_COUNT_NEXT 1 21025 #define tx_x4_credit_gen0_cl91_sync_state_COMP_2ND 2 21026 #define tx_x4_credit_gen0_cl91_sync_state_TWO_GOOD 3 21027 21028 /**************************************************************************** 21029 * Enums: tx_x4_credit_gen0_cl91_algn_state 21030 */ 21031 #define tx_x4_credit_gen0_cl91_algn_state_LOSS_OF_ALIGNMENT 0 21032 #define tx_x4_credit_gen0_cl91_algn_state_DESKEW 1 21033 #define tx_x4_credit_gen0_cl91_algn_state_DESKEW_FAIL 2 21034 #define tx_x4_credit_gen0_cl91_algn_state_ALIGN_ACQUIRED 3 21035 #define tx_x4_credit_gen0_cl91_algn_state_CW_GOOD 4 21036 #define tx_x4_credit_gen0_cl91_algn_state_CW_BAD 5 21037 #define tx_x4_credit_gen0_cl91_algn_state_THREE_BAD 6 21038 21039 /**************************************************************************** 21040 * Enums: tx_x4_credit_gen0_fec_sel_override 21041 */ 21042 #define tx_x4_credit_gen0_fec_sel_override_NO_OVERRIDE 0 21043 #define tx_x4_credit_gen0_fec_sel_override_NO_FEC 1 21044 #define tx_x4_credit_gen0_fec_sel_override_FEC_CL74 2 21045 #define tx_x4_credit_gen0_fec_sel_override_FEC_CL91 3 21046 21047 /**************************************************************************** 21048 * Enums: tx_x4_credit_gen0_cl91_blksync_mode 21049 */ 21050 #define tx_x4_credit_gen0_cl91_blksync_mode_R_BLKSYNC_NO_CL91_FEC 0 21051 #define tx_x4_credit_gen0_cl91_blksync_mode_R_BLKSYNC_CL91_QUAD_LANE_FEC 1 21052 #define tx_x4_credit_gen0_cl91_blksync_mode_R_BLKSYNC_CL91_DUAL_LANE_FEC 2 21053 #define tx_x4_credit_gen0_cl91_blksync_mode_R_BLKSYNC_CL91_SINGLE_LANE_FEC 3 21054 #define tx_x4_credit_gen0_cl91_blksync_mode_R_BLKSYNC_CL91_FC_FEC 4 21055 21056 /**************************************************************************** 21057 * Enums: tx_x4_credit_gen0_r_merge_mode 21058 */ 21059 #define tx_x4_credit_gen0_r_merge_mode_R_MERGE_MODE_BYPASS 0 21060 #define tx_x4_credit_gen0_r_merge_mode_R_MERGE_MODE_CL91_FC 1 21061 #define tx_x4_credit_gen0_r_merge_mode_R_MERGE_MODE_CL91_SINGLE_LANE 2 21062 #define tx_x4_credit_gen0_r_merge_mode_R_MERGE_MODE_CL91_DUAL_LANE 3 21063 #define tx_x4_credit_gen0_r_merge_mode_R_MERGE_MODE_CL91_QUAD_LANE 4 21064 21065 /**************************************************************************** 21066 * Enums: tx_x4_credit_gen0_r_tc_mode 21067 */ 21068 #define tx_x4_credit_gen0_r_tc_mode_R_TC_MODE_SINGLE 0 21069 #define tx_x4_credit_gen0_r_tc_mode_R_TC_MODE_DUAL 1 21070 #define tx_x4_credit_gen0_r_tc_mode_R_TC_MODE_QUAD 2 21071 21072 /**************************************************************************** 21073 * Enums: tx_x4_credit_gen0_r_tc_out_mode 21074 */ 21075 #define tx_x4_credit_gen0_r_tc_out_mode_R_TC_OUT_MODE_SINGLE 0 21076 #define tx_x4_credit_gen0_r_tc_out_mode_R_TC_OUT_MODE_DUAL 1 21077 #define tx_x4_credit_gen0_r_tc_out_mode_R_TC_OUT_MODE_QUAD 2 21078 21079 /**************************************************************************** 21080 * Enums: tx_x4_credit_gen0_cl91_fec_mode 21081 */ 21082 #define tx_x4_credit_gen0_cl91_fec_mode_NO_CL91_FEC 0 21083 #define tx_x4_credit_gen0_cl91_fec_mode_CL91_SINGLE_LANE_FC 1 21084 #define tx_x4_credit_gen0_cl91_fec_mode_CL91_SINGLE_LANE_BRCM_PROP 2 21085 #define tx_x4_credit_gen0_cl91_fec_mode_CL91_DUAL_LANE_BRCM_PROP 3 21086 #define tx_x4_credit_gen0_cl91_fec_mode_CL91_QUAD_LANE 4 21087 #define tx_x4_credit_gen0_cl91_fec_mode_IEEE_25G_CL91_SINGLE_LANE 5 21088 21089 /**************************************************************************** 21090 * Enums: tx_x4_credit_gen0_am_spacing_mul 21091 */ 21092 #define tx_x4_credit_gen0_am_spacing_mul_AM_SPACING_MUL_2 0 21093 #define tx_x4_credit_gen0_am_spacing_mul_AM_SPACING_MUL_4 1 21094 #define tx_x4_credit_gen0_am_spacing_mul_AM_SPACING_MUL_5 2 21095 #define tx_x4_credit_gen0_am_spacing_mul_AM_SPACING_MUL_20 3 21096 21097 /**************************************************************************** 21098 * Enums: tx_x4_status0_cl36TxEEEStates_l 21099 */ 21100 #define tx_x4_status0_cl36TxEEEStates_l_TX_REFRESH 8 21101 #define tx_x4_status0_cl36TxEEEStates_l_TX_QUIET 4 21102 #define tx_x4_status0_cl36TxEEEStates_l_TX_SLEEP 2 21103 #define tx_x4_status0_cl36TxEEEStates_l_TX_ACTIVE 1 21104 21105 /**************************************************************************** 21106 * Enums: tx_x4_status0_cl36TxEEEStates_c 21107 */ 21108 #define tx_x4_status0_cl36TxEEEStates_c_TX_REFRESH 3 21109 #define tx_x4_status0_cl36TxEEEStates_c_TX_QUIET 2 21110 #define tx_x4_status0_cl36TxEEEStates_c_TX_SLEEP 1 21111 #define tx_x4_status0_cl36TxEEEStates_c_TX_ACTIVE 0 21112 21113 /**************************************************************************** 21114 * Enums: tx_x4_status0_cl49TxEEEStates_l 21115 */ 21116 #define tx_x4_status0_cl49TxEEEStates_l_SCR_RESET_2 64 21117 #define tx_x4_status0_cl49TxEEEStates_l_SCR_RESET_1 32 21118 #define tx_x4_status0_cl49TxEEEStates_l_TX_WAKE 16 21119 #define tx_x4_status0_cl49TxEEEStates_l_TX_REFRESH 8 21120 #define tx_x4_status0_cl49TxEEEStates_l_TX_QUIET 4 21121 #define tx_x4_status0_cl49TxEEEStates_l_TX_SLEEP 2 21122 #define tx_x4_status0_cl49TxEEEStates_l_TX_ACTIVE 1 21123 21124 /**************************************************************************** 21125 * Enums: tx_x4_status0_fec_req_enum 21126 */ 21127 #define tx_x4_status0_fec_req_enum_FEC_not_supported 0 21128 #define tx_x4_status0_fec_req_enum_FEC_supported_but_not_requested 1 21129 #define tx_x4_status0_fec_req_enum_invalid_setting 2 21130 #define tx_x4_status0_fec_req_enum_FEC_supported_and_requested 3 21131 21132 /**************************************************************************** 21133 * Enums: tx_x4_status0_cl73_pause_enum 21134 */ 21135 #define tx_x4_status0_cl73_pause_enum_No_PAUSE_ability 0 21136 #define tx_x4_status0_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 21137 #define tx_x4_status0_cl73_pause_enum_Symmetric_PAUSE_ability 1 21138 #define tx_x4_status0_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 21139 21140 /**************************************************************************** 21141 * Enums: tx_x4_status0_cl49TxEEEStates_c 21142 */ 21143 #define tx_x4_status0_cl49TxEEEStates_c_SCR_RESET_2 6 21144 #define tx_x4_status0_cl49TxEEEStates_c_SCR_RESET_1 5 21145 #define tx_x4_status0_cl49TxEEEStates_c_TX_WAKE 4 21146 #define tx_x4_status0_cl49TxEEEStates_c_TX_REFRESH 3 21147 #define tx_x4_status0_cl49TxEEEStates_c_TX_QUIET 2 21148 #define tx_x4_status0_cl49TxEEEStates_c_TX_SLEEP 1 21149 #define tx_x4_status0_cl49TxEEEStates_c_TX_ACTIVE 0 21150 21151 /**************************************************************************** 21152 * Enums: tx_x4_status0_cl36RxEEEStates_l 21153 */ 21154 #define tx_x4_status0_cl36RxEEEStates_l_RX_LINK_FAIL 32 21155 #define tx_x4_status0_cl36RxEEEStates_l_RX_WTF 16 21156 #define tx_x4_status0_cl36RxEEEStates_l_RX_WAKE 8 21157 #define tx_x4_status0_cl36RxEEEStates_l_RX_QUIET 4 21158 #define tx_x4_status0_cl36RxEEEStates_l_RX_SLEEP 2 21159 #define tx_x4_status0_cl36RxEEEStates_l_RX_ACTIVE 1 21160 21161 /**************************************************************************** 21162 * Enums: tx_x4_status0_cl36RxEEEStates_c 21163 */ 21164 #define tx_x4_status0_cl36RxEEEStates_c_RX_LINK_FAIL 5 21165 #define tx_x4_status0_cl36RxEEEStates_c_RX_WTF 4 21166 #define tx_x4_status0_cl36RxEEEStates_c_RX_WAKE 3 21167 #define tx_x4_status0_cl36RxEEEStates_c_RX_QUIET 2 21168 #define tx_x4_status0_cl36RxEEEStates_c_RX_SLEEP 1 21169 #define tx_x4_status0_cl36RxEEEStates_c_RX_ACTIVE 0 21170 21171 /**************************************************************************** 21172 * Enums: tx_x4_status0_cl49RxEEEStates_l 21173 */ 21174 #define tx_x4_status0_cl49RxEEEStates_l_RX_LINK_FAIL 32 21175 #define tx_x4_status0_cl49RxEEEStates_l_RX_WTF 16 21176 #define tx_x4_status0_cl49RxEEEStates_l_RX_WAKE 8 21177 #define tx_x4_status0_cl49RxEEEStates_l_RX_QUIET 4 21178 #define tx_x4_status0_cl49RxEEEStates_l_RX_SLEEP 2 21179 #define tx_x4_status0_cl49RxEEEStates_l_RX_ACTIVE 1 21180 21181 /**************************************************************************** 21182 * Enums: tx_x4_status0_cl49RxEEEStates_c 21183 */ 21184 #define tx_x4_status0_cl49RxEEEStates_c_RX_LINK_FAIL 5 21185 #define tx_x4_status0_cl49RxEEEStates_c_RX_WTF 4 21186 #define tx_x4_status0_cl49RxEEEStates_c_RX_WAKE 3 21187 #define tx_x4_status0_cl49RxEEEStates_c_RX_QUIET 2 21188 #define tx_x4_status0_cl49RxEEEStates_c_RX_SLEEP 1 21189 #define tx_x4_status0_cl49RxEEEStates_c_RX_ACTIVE 0 21190 21191 /**************************************************************************** 21192 * Enums: tx_x4_status0_cl48TxEEEStates_l 21193 */ 21194 #define tx_x4_status0_cl48TxEEEStates_l_TX_REFRESH 8 21195 #define tx_x4_status0_cl48TxEEEStates_l_TX_QUIET 4 21196 #define tx_x4_status0_cl48TxEEEStates_l_TX_SLEEP 2 21197 #define tx_x4_status0_cl48TxEEEStates_l_TX_ACTIVE 1 21198 21199 /**************************************************************************** 21200 * Enums: tx_x4_status0_cl48TxEEEStates_c 21201 */ 21202 #define tx_x4_status0_cl48TxEEEStates_c_TX_REFRESH 3 21203 #define tx_x4_status0_cl48TxEEEStates_c_TX_QUIET 2 21204 #define tx_x4_status0_cl48TxEEEStates_c_TX_SLEEP 1 21205 #define tx_x4_status0_cl48TxEEEStates_c_TX_ACTIVE 0 21206 21207 /**************************************************************************** 21208 * Enums: tx_x4_status0_cl48RxEEEStates_l 21209 */ 21210 #define tx_x4_status0_cl48RxEEEStates_l_RX_LINK_FAIL 32 21211 #define tx_x4_status0_cl48RxEEEStates_l_RX_WAKE 16 21212 #define tx_x4_status0_cl48RxEEEStates_l_RX_QUIET 8 21213 #define tx_x4_status0_cl48RxEEEStates_l_RX_DEACT 4 21214 #define tx_x4_status0_cl48RxEEEStates_l_RX_SLEEP 2 21215 #define tx_x4_status0_cl48RxEEEStates_l_RX_ACTIVE 1 21216 21217 /**************************************************************************** 21218 * Enums: tx_x4_status0_cl48RxEEEStates_c 21219 */ 21220 #define tx_x4_status0_cl48RxEEEStates_c_RX_LINK_FAIL 5 21221 #define tx_x4_status0_cl48RxEEEStates_c_RX_WAKE 4 21222 #define tx_x4_status0_cl48RxEEEStates_c_RX_QUIET 3 21223 #define tx_x4_status0_cl48RxEEEStates_c_RX_DEACT 2 21224 #define tx_x4_status0_cl48RxEEEStates_c_RX_SLEEP 1 21225 #define tx_x4_status0_cl48RxEEEStates_c_RX_ACTIVE 0 21226 21227 /**************************************************************************** 21228 * Enums: tx_x4_status0_IQP_Options 21229 */ 21230 #define tx_x4_status0_IQP_Options_i50uA 0 21231 #define tx_x4_status0_IQP_Options_i100uA 1 21232 #define tx_x4_status0_IQP_Options_i150uA 2 21233 #define tx_x4_status0_IQP_Options_i200uA 3 21234 #define tx_x4_status0_IQP_Options_i250uA 4 21235 #define tx_x4_status0_IQP_Options_i300uA 5 21236 #define tx_x4_status0_IQP_Options_i350uA 6 21237 #define tx_x4_status0_IQP_Options_i400uA 7 21238 #define tx_x4_status0_IQP_Options_i450uA 8 21239 #define tx_x4_status0_IQP_Options_i500uA 9 21240 #define tx_x4_status0_IQP_Options_i550uA 10 21241 #define tx_x4_status0_IQP_Options_i600uA 11 21242 #define tx_x4_status0_IQP_Options_i650uA 12 21243 #define tx_x4_status0_IQP_Options_i700uA 13 21244 #define tx_x4_status0_IQP_Options_i750uA 14 21245 #define tx_x4_status0_IQP_Options_i800uA 15 21246 21247 /**************************************************************************** 21248 * Enums: tx_x4_status0_IDriver_Options 21249 */ 21250 #define tx_x4_status0_IDriver_Options_v680mV 0 21251 #define tx_x4_status0_IDriver_Options_v730mV 1 21252 #define tx_x4_status0_IDriver_Options_v780mV 2 21253 #define tx_x4_status0_IDriver_Options_v830mV 3 21254 #define tx_x4_status0_IDriver_Options_v880mV 4 21255 #define tx_x4_status0_IDriver_Options_v930mV 5 21256 #define tx_x4_status0_IDriver_Options_v980mV 6 21257 #define tx_x4_status0_IDriver_Options_v1010mV 7 21258 #define tx_x4_status0_IDriver_Options_v1040mV 8 21259 #define tx_x4_status0_IDriver_Options_v1060mV 9 21260 #define tx_x4_status0_IDriver_Options_v1070mV 10 21261 #define tx_x4_status0_IDriver_Options_v1080mV 11 21262 #define tx_x4_status0_IDriver_Options_v1085mV 12 21263 #define tx_x4_status0_IDriver_Options_v1090mV 13 21264 #define tx_x4_status0_IDriver_Options_v1095mV 14 21265 #define tx_x4_status0_IDriver_Options_v1100mV 15 21266 21267 /**************************************************************************** 21268 * Enums: tx_x4_status0_operationModes 21269 */ 21270 #define tx_x4_status0_operationModes_XGXS 0 21271 #define tx_x4_status0_operationModes_XGXG_nCC 1 21272 #define tx_x4_status0_operationModes_Indlane_OS8 4 21273 #define tx_x4_status0_operationModes_IndLane_OS5 5 21274 #define tx_x4_status0_operationModes_PCI 7 21275 #define tx_x4_status0_operationModes_XGXS_nLQ 8 21276 #define tx_x4_status0_operationModes_XGXS_nLQnCC 9 21277 #define tx_x4_status0_operationModes_PBypass 10 21278 #define tx_x4_status0_operationModes_PBypass_nDSK 11 21279 #define tx_x4_status0_operationModes_ComboCoreMode 12 21280 #define tx_x4_status0_operationModes_Clocks_off 15 21281 21282 /**************************************************************************** 21283 * Enums: tx_x4_status0_actualSpeeds 21284 */ 21285 #define tx_x4_status0_actualSpeeds_dr_10M 0 21286 #define tx_x4_status0_actualSpeeds_dr_100M 1 21287 #define tx_x4_status0_actualSpeeds_dr_1G 2 21288 #define tx_x4_status0_actualSpeeds_dr_2p5G 3 21289 #define tx_x4_status0_actualSpeeds_dr_5G_X4 4 21290 #define tx_x4_status0_actualSpeeds_dr_6G_X4 5 21291 #define tx_x4_status0_actualSpeeds_dr_10G_HiG 6 21292 #define tx_x4_status0_actualSpeeds_dr_10G_CX4 7 21293 #define tx_x4_status0_actualSpeeds_dr_12G_HiG 8 21294 #define tx_x4_status0_actualSpeeds_dr_12p5G_X4 9 21295 #define tx_x4_status0_actualSpeeds_dr_13G_X4 10 21296 #define tx_x4_status0_actualSpeeds_dr_15G_X4 11 21297 #define tx_x4_status0_actualSpeeds_dr_16G_X4 12 21298 #define tx_x4_status0_actualSpeeds_dr_1G_KX 13 21299 #define tx_x4_status0_actualSpeeds_dr_10G_KX4 14 21300 #define tx_x4_status0_actualSpeeds_dr_10G_KR 15 21301 #define tx_x4_status0_actualSpeeds_dr_5G 16 21302 #define tx_x4_status0_actualSpeeds_dr_6p4G 17 21303 #define tx_x4_status0_actualSpeeds_dr_20G_X4 18 21304 #define tx_x4_status0_actualSpeeds_dr_21G_X4 19 21305 #define tx_x4_status0_actualSpeeds_dr_25G_X4 20 21306 #define tx_x4_status0_actualSpeeds_dr_10G_HiG_DXGXS 21 21307 #define tx_x4_status0_actualSpeeds_dr_10G_DXGXS 22 21308 #define tx_x4_status0_actualSpeeds_dr_10p5G_HiG_DXGXS 23 21309 #define tx_x4_status0_actualSpeeds_dr_10p5G_DXGXS 24 21310 #define tx_x4_status0_actualSpeeds_dr_12p773G_HiG_DXGXS 25 21311 #define tx_x4_status0_actualSpeeds_dr_12p773G_DXGXS 26 21312 #define tx_x4_status0_actualSpeeds_dr_10G_XFI 27 21313 #define tx_x4_status0_actualSpeeds_dr_40G 28 21314 #define tx_x4_status0_actualSpeeds_dr_20G_HiG_DXGXS 29 21315 #define tx_x4_status0_actualSpeeds_dr_20G_DXGXS 30 21316 #define tx_x4_status0_actualSpeeds_dr_10G_SFI 31 21317 #define tx_x4_status0_actualSpeeds_dr_31p5G 32 21318 #define tx_x4_status0_actualSpeeds_dr_32p7G 33 21319 #define tx_x4_status0_actualSpeeds_dr_20G_SCR 34 21320 #define tx_x4_status0_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 21321 #define tx_x4_status0_actualSpeeds_dr_10G_DXGXS_SCR 36 21322 #define tx_x4_status0_actualSpeeds_dr_12G_R2 37 21323 #define tx_x4_status0_actualSpeeds_dr_10G_X2 38 21324 #define tx_x4_status0_actualSpeeds_dr_40G_KR4 39 21325 #define tx_x4_status0_actualSpeeds_dr_40G_CR4 40 21326 #define tx_x4_status0_actualSpeeds_dr_100G_CR10 41 21327 #define tx_x4_status0_actualSpeeds_dr_15p75G_DXGXS 44 21328 #define tx_x4_status0_actualSpeeds_dr_20G_KR2 57 21329 #define tx_x4_status0_actualSpeeds_dr_20G_CR2 58 21330 21331 /**************************************************************************** 21332 * Enums: tx_x4_status0_actualSpeedsMisc1 21333 */ 21334 #define tx_x4_status0_actualSpeedsMisc1_dr_2500BRCM_X1 16 21335 #define tx_x4_status0_actualSpeedsMisc1_dr_5000BRCM_X4 17 21336 #define tx_x4_status0_actualSpeedsMisc1_dr_6000BRCM_X4 18 21337 #define tx_x4_status0_actualSpeedsMisc1_dr_10GHiGig_X4 19 21338 #define tx_x4_status0_actualSpeedsMisc1_dr_10GBASE_CX4 20 21339 #define tx_x4_status0_actualSpeedsMisc1_dr_12GHiGig_X4 21 21340 #define tx_x4_status0_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 21341 #define tx_x4_status0_actualSpeedsMisc1_dr_13GHiGig_X4 23 21342 #define tx_x4_status0_actualSpeedsMisc1_dr_15GHiGig_X4 24 21343 #define tx_x4_status0_actualSpeedsMisc1_dr_16GHiGig_X4 25 21344 #define tx_x4_status0_actualSpeedsMisc1_dr_5000BRCM_X1 26 21345 #define tx_x4_status0_actualSpeedsMisc1_dr_6363BRCM_X1 27 21346 #define tx_x4_status0_actualSpeedsMisc1_dr_20GHiGig_X4 28 21347 #define tx_x4_status0_actualSpeedsMisc1_dr_21GHiGig_X4 29 21348 #define tx_x4_status0_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 21349 #define tx_x4_status0_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 21350 21351 /**************************************************************************** 21352 * Enums: tx_x4_status0_IndLaneModes 21353 */ 21354 #define tx_x4_status0_IndLaneModes_SWSDR_div2 0 21355 #define tx_x4_status0_IndLaneModes_SWSDR_div1 1 21356 #define tx_x4_status0_IndLaneModes_DWSDR_div2 2 21357 #define tx_x4_status0_IndLaneModes_DWSDR_div1 3 21358 21359 /**************************************************************************** 21360 * Enums: tx_x4_status0_prbsSelect 21361 */ 21362 #define tx_x4_status0_prbsSelect_prbs7 0 21363 #define tx_x4_status0_prbsSelect_prbs15 1 21364 #define tx_x4_status0_prbsSelect_prbs23 2 21365 #define tx_x4_status0_prbsSelect_prbs31 3 21366 21367 /**************************************************************************** 21368 * Enums: tx_x4_status0_vcoDivider 21369 */ 21370 #define tx_x4_status0_vcoDivider_div32 0 21371 #define tx_x4_status0_vcoDivider_div36 1 21372 #define tx_x4_status0_vcoDivider_div40 2 21373 #define tx_x4_status0_vcoDivider_div42 3 21374 #define tx_x4_status0_vcoDivider_div48 4 21375 #define tx_x4_status0_vcoDivider_div50 5 21376 #define tx_x4_status0_vcoDivider_div52 6 21377 #define tx_x4_status0_vcoDivider_div54 7 21378 #define tx_x4_status0_vcoDivider_div60 8 21379 #define tx_x4_status0_vcoDivider_div64 9 21380 #define tx_x4_status0_vcoDivider_div66 10 21381 #define tx_x4_status0_vcoDivider_div68 11 21382 #define tx_x4_status0_vcoDivider_div70 12 21383 #define tx_x4_status0_vcoDivider_div80 13 21384 #define tx_x4_status0_vcoDivider_div92 14 21385 #define tx_x4_status0_vcoDivider_div100 15 21386 21387 /**************************************************************************** 21388 * Enums: tx_x4_status0_refClkSelect 21389 */ 21390 #define tx_x4_status0_refClkSelect_clk_25MHz 0 21391 #define tx_x4_status0_refClkSelect_clk_100MHz 1 21392 #define tx_x4_status0_refClkSelect_clk_125MHz 2 21393 #define tx_x4_status0_refClkSelect_clk_156p25MHz 3 21394 #define tx_x4_status0_refClkSelect_clk_187p5MHz 4 21395 #define tx_x4_status0_refClkSelect_clk_161p25Mhz 5 21396 #define tx_x4_status0_refClkSelect_clk_50Mhz 6 21397 #define tx_x4_status0_refClkSelect_clk_106p25Mhz 7 21398 21399 /**************************************************************************** 21400 * Enums: tx_x4_status0_aerMMDdevTypeSelect 21401 */ 21402 #define tx_x4_status0_aerMMDdevTypeSelect_combo_core 0 21403 #define tx_x4_status0_aerMMDdevTypeSelect_PMA_PMD 1 21404 #define tx_x4_status0_aerMMDdevTypeSelect_PCS 3 21405 #define tx_x4_status0_aerMMDdevTypeSelect_PHY 4 21406 #define tx_x4_status0_aerMMDdevTypeSelect_DTE 5 21407 #define tx_x4_status0_aerMMDdevTypeSelect_CL73_AN 7 21408 21409 /**************************************************************************** 21410 * Enums: tx_x4_status0_aerMMDportSelect 21411 */ 21412 #define tx_x4_status0_aerMMDportSelect_ln0 0 21413 #define tx_x4_status0_aerMMDportSelect_ln1 1 21414 #define tx_x4_status0_aerMMDportSelect_ln2 2 21415 #define tx_x4_status0_aerMMDportSelect_ln3 3 21416 #define tx_x4_status0_aerMMDportSelect_BCST_ln0_1_2_3 511 21417 #define tx_x4_status0_aerMMDportSelect_BCST_ln0_1 512 21418 #define tx_x4_status0_aerMMDportSelect_BCST_ln2_3 513 21419 21420 /**************************************************************************** 21421 * Enums: tx_x4_status0_firmwareModeSelect 21422 */ 21423 #define tx_x4_status0_firmwareModeSelect_DEFAULT 0 21424 #define tx_x4_status0_firmwareModeSelect_SFP_OPT_LR 1 21425 #define tx_x4_status0_firmwareModeSelect_SFP_DAC 2 21426 #define tx_x4_status0_firmwareModeSelect_XLAUI 3 21427 #define tx_x4_status0_firmwareModeSelect_LONG_CH_6G 4 21428 21429 /**************************************************************************** 21430 * Enums: tx_x4_status0_tempIdxSelect 21431 */ 21432 #define tx_x4_status0_tempIdxSelect_LTE__22p9C 15 21433 #define tx_x4_status0_tempIdxSelect_LTE__12p6C 14 21434 #define tx_x4_status0_tempIdxSelect_LTE__3p0C 13 21435 #define tx_x4_status0_tempIdxSelect_LTE_6p7C 12 21436 #define tx_x4_status0_tempIdxSelect_LTE_16p4C 11 21437 #define tx_x4_status0_tempIdxSelect_LTE_26p6C 10 21438 #define tx_x4_status0_tempIdxSelect_LTE_36p3C 9 21439 #define tx_x4_status0_tempIdxSelect_LTE_46p0C 8 21440 #define tx_x4_status0_tempIdxSelect_LTE_56p2C 7 21441 #define tx_x4_status0_tempIdxSelect_LTE_65p9C 6 21442 #define tx_x4_status0_tempIdxSelect_LTE_75p6C 5 21443 #define tx_x4_status0_tempIdxSelect_LTE_85p3C 4 21444 #define tx_x4_status0_tempIdxSelect_LTE_95p5C 3 21445 #define tx_x4_status0_tempIdxSelect_LTE_105p2C 2 21446 #define tx_x4_status0_tempIdxSelect_LTE_114p9C 1 21447 #define tx_x4_status0_tempIdxSelect_LTE_125p1C 0 21448 21449 /**************************************************************************** 21450 * Enums: tx_x4_status0_port_mode 21451 */ 21452 #define tx_x4_status0_port_mode_QUAD_PORT 0 21453 #define tx_x4_status0_port_mode_TRI_1_PORT 1 21454 #define tx_x4_status0_port_mode_TRI_2_PORT 2 21455 #define tx_x4_status0_port_mode_DUAL_PORT 3 21456 #define tx_x4_status0_port_mode_SINGLE_PORT 4 21457 21458 /**************************************************************************** 21459 * Enums: tx_x4_status0_rev_letter_enum 21460 */ 21461 #define tx_x4_status0_rev_letter_enum_REV_A 0 21462 #define tx_x4_status0_rev_letter_enum_REV_B 1 21463 #define tx_x4_status0_rev_letter_enum_REV_C 2 21464 #define tx_x4_status0_rev_letter_enum_REV_D 3 21465 21466 /**************************************************************************** 21467 * Enums: tx_x4_status0_rev_number_enum 21468 */ 21469 #define tx_x4_status0_rev_number_enum_REV_0 0 21470 #define tx_x4_status0_rev_number_enum_REV_1 1 21471 #define tx_x4_status0_rev_number_enum_REV_2 2 21472 #define tx_x4_status0_rev_number_enum_REV_3 3 21473 #define tx_x4_status0_rev_number_enum_REV_4 4 21474 #define tx_x4_status0_rev_number_enum_REV_5 5 21475 #define tx_x4_status0_rev_number_enum_REV_6 6 21476 #define tx_x4_status0_rev_number_enum_REV_7 7 21477 21478 /**************************************************************************** 21479 * Enums: tx_x4_status0_bonding_enum 21480 */ 21481 #define tx_x4_status0_bonding_enum_WIRE_BOND 0 21482 #define tx_x4_status0_bonding_enum_FLIP_CHIP 1 21483 21484 /**************************************************************************** 21485 * Enums: tx_x4_status0_tech_process 21486 */ 21487 #define tx_x4_status0_tech_process_PROCESS_90NM 0 21488 #define tx_x4_status0_tech_process_PROCESS_65NM 1 21489 #define tx_x4_status0_tech_process_PROCESS_40NM 2 21490 #define tx_x4_status0_tech_process_PROCESS_28NM 3 21491 #define tx_x4_status0_tech_process_PROCESS_16NM 4 21492 21493 /**************************************************************************** 21494 * Enums: tx_x4_status0_model_num 21495 */ 21496 #define tx_x4_status0_model_num_SERDES_CL73 0 21497 #define tx_x4_status0_model_num_XGXS_16G 1 21498 #define tx_x4_status0_model_num_HYPERCORE 2 21499 #define tx_x4_status0_model_num_HYPERLITE 3 21500 #define tx_x4_status0_model_num_PCIE_G2_PIPE 4 21501 #define tx_x4_status0_model_num_SERDES_1p25GBd 5 21502 #define tx_x4_status0_model_num_SATA2 6 21503 #define tx_x4_status0_model_num_QSGMII 7 21504 #define tx_x4_status0_model_num_XGXS10G 8 21505 #define tx_x4_status0_model_num_WARPCORE 9 21506 #define tx_x4_status0_model_num_XFICORE 10 21507 #define tx_x4_status0_model_num_RXFI 11 21508 #define tx_x4_status0_model_num_WARPLITE 12 21509 #define tx_x4_status0_model_num_PENTACORE 13 21510 #define tx_x4_status0_model_num_ESM 14 21511 #define tx_x4_status0_model_num_QUAD_SGMII 15 21512 #define tx_x4_status0_model_num_WARPCORE_3 16 21513 #define tx_x4_status0_model_num_TSC 17 21514 #define tx_x4_status0_model_num_TSC4E 18 21515 #define tx_x4_status0_model_num_TSC12E 19 21516 #define tx_x4_status0_model_num_TSC4F 20 21517 #define tx_x4_status0_model_num_TSC4F_GEN2 21 21518 #define tx_x4_status0_model_num_XGXS_CL73_90NM 29 21519 #define tx_x4_status0_model_num_SERDES_CL73_90NM 30 21520 #define tx_x4_status0_model_num_WARPCORE3 32 21521 #define tx_x4_status0_model_num_WARPCORE4_TSC 33 21522 #define tx_x4_status0_model_num_RXAUI 34 21523 21524 /**************************************************************************** 21525 * Enums: tx_x4_status0_payload 21526 */ 21527 #define tx_x4_status0_payload_REPEAT_2_BYTES 0 21528 #define tx_x4_status0_payload_RAMPING 1 21529 #define tx_x4_status0_payload_CL48_CRPAT 2 21530 #define tx_x4_status0_payload_CL48_CJPAT 3 21531 #define tx_x4_status0_payload_CL36_LONG_CRPAT 4 21532 #define tx_x4_status0_payload_CL36_SHORT_CRPAT 5 21533 21534 /**************************************************************************** 21535 * Enums: tx_x4_status0_sc 21536 */ 21537 #define tx_x4_status0_sc_S_10G_CR1 0 21538 #define tx_x4_status0_sc_S_10G_KR1 1 21539 #define tx_x4_status0_sc_S_10G_X1 2 21540 #define tx_x4_status0_sc_S_10G_HG2_CR1 4 21541 #define tx_x4_status0_sc_S_10G_HG2_KR1 5 21542 #define tx_x4_status0_sc_S_10G_HG2_X1 6 21543 #define tx_x4_status0_sc_S_20G_CR1 8 21544 #define tx_x4_status0_sc_S_20G_KR1 9 21545 #define tx_x4_status0_sc_S_20G_X1 10 21546 #define tx_x4_status0_sc_S_20G_HG2_CR1 12 21547 #define tx_x4_status0_sc_S_20G_HG2_KR1 13 21548 #define tx_x4_status0_sc_S_20G_HG2_X1 14 21549 #define tx_x4_status0_sc_S_25G_CR1 16 21550 #define tx_x4_status0_sc_S_25G_KR1 17 21551 #define tx_x4_status0_sc_S_25G_X1 18 21552 #define tx_x4_status0_sc_S_25G_HG2_CR1 20 21553 #define tx_x4_status0_sc_S_25G_HG2_KR1 21 21554 #define tx_x4_status0_sc_S_25G_HG2_X1 22 21555 #define tx_x4_status0_sc_S_20G_CR2 24 21556 #define tx_x4_status0_sc_S_20G_KR2 25 21557 #define tx_x4_status0_sc_S_20G_X2 26 21558 #define tx_x4_status0_sc_S_20G_HG2_CR2 28 21559 #define tx_x4_status0_sc_S_20G_HG2_KR2 29 21560 #define tx_x4_status0_sc_S_20G_HG2_X2 30 21561 #define tx_x4_status0_sc_S_40G_CR2 32 21562 #define tx_x4_status0_sc_S_40G_KR2 33 21563 #define tx_x4_status0_sc_S_40G_X2 34 21564 #define tx_x4_status0_sc_S_40G_HG2_CR2 36 21565 #define tx_x4_status0_sc_S_40G_HG2_KR2 37 21566 #define tx_x4_status0_sc_S_40G_HG2_X2 38 21567 #define tx_x4_status0_sc_S_40G_CR4 40 21568 #define tx_x4_status0_sc_S_40G_KR4 41 21569 #define tx_x4_status0_sc_S_40G_X4 42 21570 #define tx_x4_status0_sc_S_40G_HG2_CR4 44 21571 #define tx_x4_status0_sc_S_40G_HG2_KR4 45 21572 #define tx_x4_status0_sc_S_40G_HG2_X4 46 21573 #define tx_x4_status0_sc_S_50G_CR2 48 21574 #define tx_x4_status0_sc_S_50G_KR2 49 21575 #define tx_x4_status0_sc_S_50G_X2 50 21576 #define tx_x4_status0_sc_S_50G_HG2_CR2 52 21577 #define tx_x4_status0_sc_S_50G_HG2_KR2 53 21578 #define tx_x4_status0_sc_S_50G_HG2_X2 54 21579 #define tx_x4_status0_sc_S_50G_CR4 56 21580 #define tx_x4_status0_sc_S_50G_KR4 57 21581 #define tx_x4_status0_sc_S_50G_X4 58 21582 #define tx_x4_status0_sc_S_50G_HG2_CR4 60 21583 #define tx_x4_status0_sc_S_50G_HG2_KR4 61 21584 #define tx_x4_status0_sc_S_50G_HG2_X4 62 21585 #define tx_x4_status0_sc_S_100G_CR4 64 21586 #define tx_x4_status0_sc_S_100G_KR4 65 21587 #define tx_x4_status0_sc_S_100G_X4 66 21588 #define tx_x4_status0_sc_S_100G_HG2_CR4 68 21589 #define tx_x4_status0_sc_S_100G_HG2_KR4 69 21590 #define tx_x4_status0_sc_S_100G_HG2_X4 70 21591 #define tx_x4_status0_sc_S_CL73_20GVCO 72 21592 #define tx_x4_status0_sc_S_CL73_25GVCO 80 21593 #define tx_x4_status0_sc_S_CL36_20GVCO 88 21594 #define tx_x4_status0_sc_S_CL36_25GVCO 96 21595 #define tx_x4_status0_sc_S_25G_CR_IEEE 112 21596 #define tx_x4_status0_sc_S_25G_CRS_IEEE 113 21597 #define tx_x4_status0_sc_S_25G_KR_IEEE 114 21598 #define tx_x4_status0_sc_S_25G_KRS_IEEE 115 21599 21600 /**************************************************************************** 21601 * Enums: tx_x4_status0_t_fifo_modes 21602 */ 21603 #define tx_x4_status0_t_fifo_modes_T_FIFO_INSERT_NO_AM 0 21604 #define tx_x4_status0_t_fifo_modes_T_FIFO_INSERT_4_AM 1 21605 #define tx_x4_status0_t_fifo_modes_T_FIFO_INSERT_20_AM 2 21606 #define tx_x4_status0_t_fifo_modes_T_FIFO_INSERT_2_AM 3 21607 21608 /**************************************************************************** 21609 * Enums: tx_x4_status0_t_enc_modes 21610 */ 21611 #define tx_x4_status0_t_enc_modes_T_ENC_MODE_BYPASS 0 21612 #define tx_x4_status0_t_enc_modes_T_ENC_MODE_CL49 1 21613 #define tx_x4_status0_t_enc_modes_T_ENC_MODE_CL82 2 21614 21615 /**************************************************************************** 21616 * Enums: tx_x4_status0_btmx_mode 21617 */ 21618 #define tx_x4_status0_btmx_mode_BS_BTMX_MODE_1to1 0 21619 #define tx_x4_status0_btmx_mode_BS_BTMX_MODE_2to1 1 21620 #define tx_x4_status0_btmx_mode_BS_BTMX_MODE_5to1 2 21621 21622 /**************************************************************************** 21623 * Enums: tx_x4_status0_t_type_cl82 21624 */ 21625 #define tx_x4_status0_t_type_cl82_T_TYPE_B1 5 21626 #define tx_x4_status0_t_type_cl82_T_TYPE_C 4 21627 #define tx_x4_status0_t_type_cl82_T_TYPE_S 3 21628 #define tx_x4_status0_t_type_cl82_T_TYPE_T 2 21629 #define tx_x4_status0_t_type_cl82_T_TYPE_D 1 21630 #define tx_x4_status0_t_type_cl82_T_TYPE_E 0 21631 21632 /**************************************************************************** 21633 * Enums: tx_x4_status0_txsm_state_cl82 21634 */ 21635 #define tx_x4_status0_txsm_state_cl82_TX_HIG_END 6 21636 #define tx_x4_status0_txsm_state_cl82_TX_HIG_START 5 21637 #define tx_x4_status0_txsm_state_cl82_TX_E 4 21638 #define tx_x4_status0_txsm_state_cl82_TX_T 3 21639 #define tx_x4_status0_txsm_state_cl82_TX_D 2 21640 #define tx_x4_status0_txsm_state_cl82_TX_C 1 21641 #define tx_x4_status0_txsm_state_cl82_TX_INIT 0 21642 21643 /**************************************************************************** 21644 * Enums: tx_x4_status0_ltxsm_state_cl82 21645 */ 21646 #define tx_x4_status0_ltxsm_state_cl82_TX_HIG_END 64 21647 #define tx_x4_status0_ltxsm_state_cl82_TX_HIG_START 32 21648 #define tx_x4_status0_ltxsm_state_cl82_TX_E 16 21649 #define tx_x4_status0_ltxsm_state_cl82_TX_T 8 21650 #define tx_x4_status0_ltxsm_state_cl82_TX_D 4 21651 #define tx_x4_status0_ltxsm_state_cl82_TX_C 2 21652 #define tx_x4_status0_ltxsm_state_cl82_TX_INIT 1 21653 21654 /**************************************************************************** 21655 * Enums: tx_x4_status0_r_type_coded_cl82 21656 */ 21657 #define tx_x4_status0_r_type_coded_cl82_R_TYPE_B1 32 21658 #define tx_x4_status0_r_type_coded_cl82_R_TYPE_C 16 21659 #define tx_x4_status0_r_type_coded_cl82_R_TYPE_S 8 21660 #define tx_x4_status0_r_type_coded_cl82_R_TYPE_T 4 21661 #define tx_x4_status0_r_type_coded_cl82_R_TYPE_D 2 21662 #define tx_x4_status0_r_type_coded_cl82_R_TYPE_E 1 21663 21664 /**************************************************************************** 21665 * Enums: tx_x4_status0_rxsm_state_cl82 21666 */ 21667 #define tx_x4_status0_rxsm_state_cl82_RX_HIG_END 64 21668 #define tx_x4_status0_rxsm_state_cl82_RX_HIG_START 32 21669 #define tx_x4_status0_rxsm_state_cl82_RX_E 16 21670 #define tx_x4_status0_rxsm_state_cl82_RX_T 8 21671 #define tx_x4_status0_rxsm_state_cl82_RX_D 4 21672 #define tx_x4_status0_rxsm_state_cl82_RX_C 2 21673 #define tx_x4_status0_rxsm_state_cl82_RX_INIT 1 21674 21675 /**************************************************************************** 21676 * Enums: tx_x4_status0_deskew_state 21677 */ 21678 #define tx_x4_status0_deskew_state_ALIGN_ACQUIRED 2 21679 #define tx_x4_status0_deskew_state_LOSS_OF_ALIGNMENT 1 21680 21681 /**************************************************************************** 21682 * Enums: tx_x4_status0_os_mode_enum 21683 */ 21684 #define tx_x4_status0_os_mode_enum_OS_MODE_1 0 21685 #define tx_x4_status0_os_mode_enum_OS_MODE_2 1 21686 #define tx_x4_status0_os_mode_enum_OS_MODE_4 2 21687 #define tx_x4_status0_os_mode_enum_OS_MODE_16p5 8 21688 #define tx_x4_status0_os_mode_enum_OS_MODE_20p625 12 21689 21690 /**************************************************************************** 21691 * Enums: tx_x4_status0_scr_modes 21692 */ 21693 #define tx_x4_status0_scr_modes_T_SCR_MODE_BYPASS 0 21694 #define tx_x4_status0_scr_modes_T_SCR_MODE_CL49 1 21695 #define tx_x4_status0_scr_modes_T_SCR_MODE_40G_2_LANE 2 21696 #define tx_x4_status0_scr_modes_T_SCR_MODE_100G 3 21697 #define tx_x4_status0_scr_modes_T_SCR_MODE_20G 4 21698 #define tx_x4_status0_scr_modes_T_SCR_MODE_40G_4_LANE 5 21699 21700 /**************************************************************************** 21701 * Enums: tx_x4_status0_descr_modes 21702 */ 21703 #define tx_x4_status0_descr_modes_R_DESCR_MODE_BYPASS 0 21704 #define tx_x4_status0_descr_modes_R_DESCR_MODE_CL49 1 21705 #define tx_x4_status0_descr_modes_R_DESCR_MODE_CL82 2 21706 21707 /**************************************************************************** 21708 * Enums: tx_x4_status0_r_dec_tl_mode 21709 */ 21710 #define tx_x4_status0_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 21711 #define tx_x4_status0_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 21712 #define tx_x4_status0_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 21713 21714 /**************************************************************************** 21715 * Enums: tx_x4_status0_r_dec_fsm_mode 21716 */ 21717 #define tx_x4_status0_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 21718 #define tx_x4_status0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 21719 #define tx_x4_status0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 21720 21721 /**************************************************************************** 21722 * Enums: tx_x4_status0_r_deskew_mode 21723 */ 21724 #define tx_x4_status0_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 21725 #define tx_x4_status0_r_deskew_mode_R_DESKEW_MODE_20G 1 21726 #define tx_x4_status0_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 21727 #define tx_x4_status0_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 21728 #define tx_x4_status0_r_deskew_mode_R_DESKEW_MODE_100G 4 21729 #define tx_x4_status0_r_deskew_mode_R_DESKEW_MODE_CL49 5 21730 #define tx_x4_status0_r_deskew_mode_R_DESKEW_MODE_CL91_QUAD 6 21731 #define tx_x4_status0_r_deskew_mode_R_DESKEW_MODE_CL91_SINGLE_BRCM 7 21732 #define tx_x4_status0_r_deskew_mode_R_DESKEW_MODE_CL91_DUAL_BRCM 8 21733 #define tx_x4_status0_r_deskew_mode_R_DESKEW_MODE_CL91_FC 9 21734 21735 /**************************************************************************** 21736 * Enums: tx_x4_status0_bs_dist_modes 21737 */ 21738 #define tx_x4_status0_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 21739 #define tx_x4_status0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 21740 #define tx_x4_status0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 21741 #define tx_x4_status0_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 21742 21743 /**************************************************************************** 21744 * Enums: tx_x4_status0_cl49_t_type 21745 */ 21746 #define tx_x4_status0_cl49_t_type_BAD_T_TYPE 15 21747 #define tx_x4_status0_cl49_t_type_T_TYPE_B0 11 21748 #define tx_x4_status0_cl49_t_type_T_TYPE_OB 10 21749 #define tx_x4_status0_cl49_t_type_T_TYPE_B1 9 21750 #define tx_x4_status0_cl49_t_type_T_TYPE_DB 8 21751 #define tx_x4_status0_cl49_t_type_T_TYPE_FC 7 21752 #define tx_x4_status0_cl49_t_type_T_TYPE_TB 6 21753 #define tx_x4_status0_cl49_t_type_T_TYPE_LI 5 21754 #define tx_x4_status0_cl49_t_type_T_TYPE_C 4 21755 #define tx_x4_status0_cl49_t_type_T_TYPE_S 3 21756 #define tx_x4_status0_cl49_t_type_T_TYPE_T 2 21757 #define tx_x4_status0_cl49_t_type_T_TYPE_D 1 21758 #define tx_x4_status0_cl49_t_type_T_TYPE_E 0 21759 21760 /**************************************************************************** 21761 * Enums: tx_x4_status0_cl49_txsm_states 21762 */ 21763 #define tx_x4_status0_cl49_txsm_states_TX_HIG_END 7 21764 #define tx_x4_status0_cl49_txsm_states_TX_HIG_START 6 21765 #define tx_x4_status0_cl49_txsm_states_TX_LI 5 21766 #define tx_x4_status0_cl49_txsm_states_TX_E 4 21767 #define tx_x4_status0_cl49_txsm_states_TX_T 3 21768 #define tx_x4_status0_cl49_txsm_states_TX_D 2 21769 #define tx_x4_status0_cl49_txsm_states_TX_C 1 21770 #define tx_x4_status0_cl49_txsm_states_TX_INIT 0 21771 21772 /**************************************************************************** 21773 * Enums: tx_x4_status0_cl49_ltxsm_states 21774 */ 21775 #define tx_x4_status0_cl49_ltxsm_states_TX_HIG_END 128 21776 #define tx_x4_status0_cl49_ltxsm_states_TX_HIG_START 64 21777 #define tx_x4_status0_cl49_ltxsm_states_TX_LI 32 21778 #define tx_x4_status0_cl49_ltxsm_states_TX_E 16 21779 #define tx_x4_status0_cl49_ltxsm_states_TX_T 8 21780 #define tx_x4_status0_cl49_ltxsm_states_TX_D 4 21781 #define tx_x4_status0_cl49_ltxsm_states_TX_C 2 21782 #define tx_x4_status0_cl49_ltxsm_states_TX_INIT 1 21783 21784 /**************************************************************************** 21785 * Enums: tx_x4_status0_burst_error_mode 21786 */ 21787 #define tx_x4_status0_burst_error_mode_BURST_ERROR_11_BITS 0 21788 #define tx_x4_status0_burst_error_mode_BURST_ERROR_16_BITS 1 21789 #define tx_x4_status0_burst_error_mode_BURST_ERROR_17_BITS 2 21790 #define tx_x4_status0_burst_error_mode_BURST_ERROR_18_BITS 3 21791 #define tx_x4_status0_burst_error_mode_BURST_ERROR_19_BITS 4 21792 #define tx_x4_status0_burst_error_mode_BURST_ERROR_20_BITS 5 21793 #define tx_x4_status0_burst_error_mode_BURST_ERROR_21_BITS 6 21794 #define tx_x4_status0_burst_error_mode_BURST_ERROR_22_BITS 7 21795 #define tx_x4_status0_burst_error_mode_BURST_ERROR_23_BITS 8 21796 #define tx_x4_status0_burst_error_mode_BURST_ERROR_24_BITS 9 21797 #define tx_x4_status0_burst_error_mode_BURST_ERROR_25_BITS 10 21798 #define tx_x4_status0_burst_error_mode_BURST_ERROR_26_BITS 11 21799 #define tx_x4_status0_burst_error_mode_BURST_ERROR_27_BITS 12 21800 #define tx_x4_status0_burst_error_mode_BURST_ERROR_28_BITS 13 21801 #define tx_x4_status0_burst_error_mode_BURST_ERROR_29_BITS 14 21802 #define tx_x4_status0_burst_error_mode_BURST_ERROR_30_BITS 15 21803 #define tx_x4_status0_burst_error_mode_BURST_ERROR_31_BITS 16 21804 #define tx_x4_status0_burst_error_mode_BURST_ERROR_32_BITS 17 21805 #define tx_x4_status0_burst_error_mode_BURST_ERROR_33_BITS 18 21806 #define tx_x4_status0_burst_error_mode_BURST_ERROR_34_BITS 19 21807 #define tx_x4_status0_burst_error_mode_BURST_ERROR_35_BITS 20 21808 #define tx_x4_status0_burst_error_mode_BURST_ERROR_36_BITS 21 21809 #define tx_x4_status0_burst_error_mode_BURST_ERROR_37_BITS 22 21810 #define tx_x4_status0_burst_error_mode_BURST_ERROR_38_BITS 23 21811 #define tx_x4_status0_burst_error_mode_BURST_ERROR_39_BITS 24 21812 #define tx_x4_status0_burst_error_mode_BURST_ERROR_40_BITS 25 21813 #define tx_x4_status0_burst_error_mode_BURST_ERROR_41_BITS 26 21814 21815 /**************************************************************************** 21816 * Enums: tx_x4_status0_bermon_state 21817 */ 21818 #define tx_x4_status0_bermon_state_HI_BER 4 21819 #define tx_x4_status0_bermon_state_GOOD_BER 3 21820 #define tx_x4_status0_bermon_state_BER_TEST_SH 2 21821 #define tx_x4_status0_bermon_state_START_TIMER 1 21822 #define tx_x4_status0_bermon_state_BER_MT_INIT 0 21823 21824 /**************************************************************************** 21825 * Enums: tx_x4_status0_rxsm_state_cl49 21826 */ 21827 #define tx_x4_status0_rxsm_state_cl49_RX_HIG_END 128 21828 #define tx_x4_status0_rxsm_state_cl49_RX_HIG_START 64 21829 #define tx_x4_status0_rxsm_state_cl49_RX_LI 32 21830 #define tx_x4_status0_rxsm_state_cl49_RX_E 16 21831 #define tx_x4_status0_rxsm_state_cl49_RX_T 8 21832 #define tx_x4_status0_rxsm_state_cl49_RX_D 4 21833 #define tx_x4_status0_rxsm_state_cl49_RX_C 2 21834 #define tx_x4_status0_rxsm_state_cl49_RX_INIT 1 21835 21836 /**************************************************************************** 21837 * Enums: tx_x4_status0_r_type 21838 */ 21839 #define tx_x4_status0_r_type_BAD_R_TYPE 15 21840 #define tx_x4_status0_r_type_R_TYPE_B0 11 21841 #define tx_x4_status0_r_type_R_TYPE_OB 10 21842 #define tx_x4_status0_r_type_R_TYPE_B1 9 21843 #define tx_x4_status0_r_type_R_TYPE_DB 8 21844 #define tx_x4_status0_r_type_R_TYPE_FC 7 21845 #define tx_x4_status0_r_type_R_TYPE_TB 6 21846 #define tx_x4_status0_r_type_R_TYPE_LI 5 21847 #define tx_x4_status0_r_type_R_TYPE_C 4 21848 #define tx_x4_status0_r_type_R_TYPE_S 3 21849 #define tx_x4_status0_r_type_R_TYPE_T 2 21850 #define tx_x4_status0_r_type_R_TYPE_D 1 21851 #define tx_x4_status0_r_type_R_TYPE_E 0 21852 21853 /**************************************************************************** 21854 * Enums: tx_x4_status0_am_lock_state 21855 */ 21856 #define tx_x4_status0_am_lock_state_INVALID_AM 512 21857 #define tx_x4_status0_am_lock_state_GOOD_AM 256 21858 #define tx_x4_status0_am_lock_state_COMP_AM 128 21859 #define tx_x4_status0_am_lock_state_TIMER_2 64 21860 #define tx_x4_status0_am_lock_state_AM_2_GOOD 32 21861 #define tx_x4_status0_am_lock_state_COMP_2ND 16 21862 #define tx_x4_status0_am_lock_state_TIMER_1 8 21863 #define tx_x4_status0_am_lock_state_FIND_1ST 4 21864 #define tx_x4_status0_am_lock_state_AM_RESET_CNT 2 21865 #define tx_x4_status0_am_lock_state_AM_LOCK_INIT 1 21866 21867 /**************************************************************************** 21868 * Enums: tx_x4_status0_msg_selector 21869 */ 21870 #define tx_x4_status0_msg_selector_RESERVED 0 21871 #define tx_x4_status0_msg_selector_VALUE_802p3 1 21872 #define tx_x4_status0_msg_selector_VALUE_802p9 2 21873 #define tx_x4_status0_msg_selector_VALUE_802p5 3 21874 #define tx_x4_status0_msg_selector_VALUE_1394 4 21875 21876 /**************************************************************************** 21877 * Enums: tx_x4_status0_synce_enum 21878 */ 21879 #define tx_x4_status0_synce_enum_SYNCE_NO_DIV 0 21880 #define tx_x4_status0_synce_enum_SYNCE_DIV_7 1 21881 #define tx_x4_status0_synce_enum_SYNCE_DIV_11 2 21882 21883 /**************************************************************************** 21884 * Enums: tx_x4_status0_synce_enum_stage0 21885 */ 21886 #define tx_x4_status0_synce_enum_stage0_SYNCE_NO_DIV 0 21887 #define tx_x4_status0_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 21888 #define tx_x4_status0_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 21889 21890 /**************************************************************************** 21891 * Enums: tx_x4_status0_cl91_sync_state 21892 */ 21893 #define tx_x4_status0_cl91_sync_state_FIND_1ST 0 21894 #define tx_x4_status0_cl91_sync_state_COUNT_NEXT 1 21895 #define tx_x4_status0_cl91_sync_state_COMP_2ND 2 21896 #define tx_x4_status0_cl91_sync_state_TWO_GOOD 3 21897 21898 /**************************************************************************** 21899 * Enums: tx_x4_status0_cl91_algn_state 21900 */ 21901 #define tx_x4_status0_cl91_algn_state_LOSS_OF_ALIGNMENT 0 21902 #define tx_x4_status0_cl91_algn_state_DESKEW 1 21903 #define tx_x4_status0_cl91_algn_state_DESKEW_FAIL 2 21904 #define tx_x4_status0_cl91_algn_state_ALIGN_ACQUIRED 3 21905 #define tx_x4_status0_cl91_algn_state_CW_GOOD 4 21906 #define tx_x4_status0_cl91_algn_state_CW_BAD 5 21907 #define tx_x4_status0_cl91_algn_state_THREE_BAD 6 21908 21909 /**************************************************************************** 21910 * Enums: tx_x4_status0_fec_sel_override 21911 */ 21912 #define tx_x4_status0_fec_sel_override_NO_OVERRIDE 0 21913 #define tx_x4_status0_fec_sel_override_NO_FEC 1 21914 #define tx_x4_status0_fec_sel_override_FEC_CL74 2 21915 #define tx_x4_status0_fec_sel_override_FEC_CL91 3 21916 21917 /**************************************************************************** 21918 * Enums: tx_x4_status0_cl91_blksync_mode 21919 */ 21920 #define tx_x4_status0_cl91_blksync_mode_R_BLKSYNC_NO_CL91_FEC 0 21921 #define tx_x4_status0_cl91_blksync_mode_R_BLKSYNC_CL91_QUAD_LANE_FEC 1 21922 #define tx_x4_status0_cl91_blksync_mode_R_BLKSYNC_CL91_DUAL_LANE_FEC 2 21923 #define tx_x4_status0_cl91_blksync_mode_R_BLKSYNC_CL91_SINGLE_LANE_FEC 3 21924 #define tx_x4_status0_cl91_blksync_mode_R_BLKSYNC_CL91_FC_FEC 4 21925 21926 /**************************************************************************** 21927 * Enums: tx_x4_status0_r_merge_mode 21928 */ 21929 #define tx_x4_status0_r_merge_mode_R_MERGE_MODE_BYPASS 0 21930 #define tx_x4_status0_r_merge_mode_R_MERGE_MODE_CL91_FC 1 21931 #define tx_x4_status0_r_merge_mode_R_MERGE_MODE_CL91_SINGLE_LANE 2 21932 #define tx_x4_status0_r_merge_mode_R_MERGE_MODE_CL91_DUAL_LANE 3 21933 #define tx_x4_status0_r_merge_mode_R_MERGE_MODE_CL91_QUAD_LANE 4 21934 21935 /**************************************************************************** 21936 * Enums: tx_x4_status0_r_tc_mode 21937 */ 21938 #define tx_x4_status0_r_tc_mode_R_TC_MODE_SINGLE 0 21939 #define tx_x4_status0_r_tc_mode_R_TC_MODE_DUAL 1 21940 #define tx_x4_status0_r_tc_mode_R_TC_MODE_QUAD 2 21941 21942 /**************************************************************************** 21943 * Enums: tx_x4_status0_r_tc_out_mode 21944 */ 21945 #define tx_x4_status0_r_tc_out_mode_R_TC_OUT_MODE_SINGLE 0 21946 #define tx_x4_status0_r_tc_out_mode_R_TC_OUT_MODE_DUAL 1 21947 #define tx_x4_status0_r_tc_out_mode_R_TC_OUT_MODE_QUAD 2 21948 21949 /**************************************************************************** 21950 * Enums: tx_x4_status0_cl91_fec_mode 21951 */ 21952 #define tx_x4_status0_cl91_fec_mode_NO_CL91_FEC 0 21953 #define tx_x4_status0_cl91_fec_mode_CL91_SINGLE_LANE_FC 1 21954 #define tx_x4_status0_cl91_fec_mode_CL91_SINGLE_LANE_BRCM_PROP 2 21955 #define tx_x4_status0_cl91_fec_mode_CL91_DUAL_LANE_BRCM_PROP 3 21956 #define tx_x4_status0_cl91_fec_mode_CL91_QUAD_LANE 4 21957 #define tx_x4_status0_cl91_fec_mode_IEEE_25G_CL91_SINGLE_LANE 5 21958 21959 /**************************************************************************** 21960 * Enums: tx_x4_status0_am_spacing_mul 21961 */ 21962 #define tx_x4_status0_am_spacing_mul_AM_SPACING_MUL_2 0 21963 #define tx_x4_status0_am_spacing_mul_AM_SPACING_MUL_4 1 21964 #define tx_x4_status0_am_spacing_mul_AM_SPACING_MUL_5 2 21965 #define tx_x4_status0_am_spacing_mul_AM_SPACING_MUL_20 3 21966 21967 /**************************************************************************** 21968 * TSC_IEEE_CL22_CL22_B0 21969 */ 21970 21971 21972 21973 21974 21975 /**************************************************************************** 21976 * TSC_IEEE_CL22_CL22_B0 21977 */ 21978 /**************************************************************************** 21979 * CL22_B0 :: phyid2 21980 */ 21981 /* CL22_B0 :: phyid2 :: regid1 [15:00] */ 21982 #define CL22_B0_PHYID2_REGID1_MASK 0xffff 21983 #define CL22_B0_PHYID2_REGID1_ALIGN 0 21984 #define CL22_B0_PHYID2_REGID1_BITS 16 21985 #define CL22_B0_PHYID2_REGID1_SHIFT 0 21986 21987 21988 /**************************************************************************** 21989 * CL22_B0 :: phyid3 21990 */ 21991 /* CL22_B0 :: phyid3 :: regid2 [15:00] */ 21992 #define CL22_B0_PHYID3_REGID2_MASK 0xffff 21993 #define CL22_B0_PHYID3_REGID2_ALIGN 0 21994 #define CL22_B0_PHYID3_REGID2_BITS 16 21995 #define CL22_B0_PHYID3_REGID2_SHIFT 0 21996 21997 21998 /**************************************************************************** 21999 * TSC_WC4_TSC_USER1_Main0 22000 */ 22001 /**************************************************************************** 22002 * Main0 :: setup 22003 */ 22004 /* Main0 :: setup :: master_port_num [15:14] */ 22005 #define MAIN0_SETUP_MASTER_PORT_NUM_MASK 0xc000 22006 #define MAIN0_SETUP_MASTER_PORT_NUM_ALIGN 0 22007 #define MAIN0_SETUP_MASTER_PORT_NUM_BITS 2 22008 #define MAIN0_SETUP_MASTER_PORT_NUM_SHIFT 14 22009 22010 /* Main0 :: setup :: cl72_en [13:10] */ 22011 #define MAIN0_SETUP_CL72_EN_MASK 0x3c00 22012 #define MAIN0_SETUP_CL72_EN_ALIGN 0 22013 #define MAIN0_SETUP_CL72_EN_BITS 4 22014 #define MAIN0_SETUP_CL72_EN_SHIFT 10 22015 22016 /* Main0 :: setup :: refclk_sel [09:07] */ 22017 #define MAIN0_SETUP_REFCLK_SEL_MASK 0x0380 22018 #define MAIN0_SETUP_REFCLK_SEL_ALIGN 0 22019 #define MAIN0_SETUP_REFCLK_SEL_BITS 3 22020 #define MAIN0_SETUP_REFCLK_SEL_SHIFT 7 22021 #define MAIN0_SETUP_REFCLK_SEL_clk_25MHz 0 22022 #define MAIN0_SETUP_REFCLK_SEL_clk_100MHz 1 22023 #define MAIN0_SETUP_REFCLK_SEL_clk_125MHz 2 22024 #define MAIN0_SETUP_REFCLK_SEL_clk_156p25MHz 3 22025 #define MAIN0_SETUP_REFCLK_SEL_clk_187p5MHz 4 22026 #define MAIN0_SETUP_REFCLK_SEL_clk_161p25Mhz 5 22027 #define MAIN0_SETUP_REFCLK_SEL_clk_50Mhz 6 22028 #define MAIN0_SETUP_REFCLK_SEL_clk_106p25Mhz 7 22029 22030 /* Main0 :: setup :: port_mode_sel [06:04] */ 22031 #define MAIN0_SETUP_PORT_MODE_SEL_MASK 0x0070 22032 #define MAIN0_SETUP_PORT_MODE_SEL_ALIGN 0 22033 #define MAIN0_SETUP_PORT_MODE_SEL_BITS 3 22034 #define MAIN0_SETUP_PORT_MODE_SEL_SHIFT 4 22035 #define MAIN0_SETUP_PORT_MODE_SEL_QUAD_PORT 0 22036 #define MAIN0_SETUP_PORT_MODE_SEL_TRI_1_PORT 1 22037 #define MAIN0_SETUP_PORT_MODE_SEL_TRI_2_PORT 2 22038 #define MAIN0_SETUP_PORT_MODE_SEL_DUAL_PORT 3 22039 #define MAIN0_SETUP_PORT_MODE_SEL_SINGLE_PORT 4 22040 22041 /* Main0 :: setup :: single_port_mode [03:03] */ 22042 #define MAIN0_SETUP_SINGLE_PORT_MODE_MASK 0x0008 22043 #define MAIN0_SETUP_SINGLE_PORT_MODE_ALIGN 0 22044 #define MAIN0_SETUP_SINGLE_PORT_MODE_BITS 1 22045 #define MAIN0_SETUP_SINGLE_PORT_MODE_SHIFT 3 22046 22047 /* Main0 :: setup :: stand_alone_mode [02:02] */ 22048 #define MAIN0_SETUP_STAND_ALONE_MODE_MASK 0x0004 22049 #define MAIN0_SETUP_STAND_ALONE_MODE_ALIGN 0 22050 #define MAIN0_SETUP_STAND_ALONE_MODE_BITS 1 22051 #define MAIN0_SETUP_STAND_ALONE_MODE_SHIFT 2 22052 22053 /* Main0 :: setup :: cl73_VCO [01:01] */ 22054 #define MAIN0_SETUP_CL73_VCO_MASK 0x0002 22055 #define MAIN0_SETUP_CL73_VCO_ALIGN 0 22056 #define MAIN0_SETUP_CL73_VCO_BITS 1 22057 #define MAIN0_SETUP_CL73_VCO_SHIFT 1 22058 22059 /* Main0 :: setup :: tsc_clk_ctrl [00:00] */ 22060 #define MAIN0_SETUP_TSC_CLK_CTRL_MASK 0x0001 22061 #define MAIN0_SETUP_TSC_CLK_CTRL_ALIGN 0 22062 #define MAIN0_SETUP_TSC_CLK_CTRL_BITS 1 22063 #define MAIN0_SETUP_TSC_CLK_CTRL_SHIFT 0 22064 22065 22066 /**************************************************************************** 22067 * Main0 :: synce_control 22068 */ 22069 /* Main0 :: synce_control :: reserved0 [15:08] */ 22070 #define MAIN0_SYNCE_CONTROL_RESERVED0_MASK 0xff00 22071 #define MAIN0_SYNCE_CONTROL_RESERVED0_ALIGN 0 22072 #define MAIN0_SYNCE_CONTROL_RESERVED0_BITS 8 22073 #define MAIN0_SYNCE_CONTROL_RESERVED0_SHIFT 8 22074 22075 /* Main0 :: synce_control :: synce_mode_phy_lane3 [07:06] */ 22076 #define MAIN0_SYNCE_CONTROL_SYNCE_MODE_PHY_LANE3_MASK 0x00c0 22077 #define MAIN0_SYNCE_CONTROL_SYNCE_MODE_PHY_LANE3_ALIGN 0 22078 #define MAIN0_SYNCE_CONTROL_SYNCE_MODE_PHY_LANE3_BITS 2 22079 #define MAIN0_SYNCE_CONTROL_SYNCE_MODE_PHY_LANE3_SHIFT 6 22080 #define MAIN0_SYNCE_CONTROL_SYNCE_MODE_PHY_LANE3_SYNCE_NO_DIV 0 22081 #define MAIN0_SYNCE_CONTROL_SYNCE_MODE_PHY_LANE3_SYNCE_DIV_7 1 22082 #define MAIN0_SYNCE_CONTROL_SYNCE_MODE_PHY_LANE3_SYNCE_DIV_11 2 22083 22084 /* Main0 :: synce_control :: synce_mode_phy_lane2 [05:04] */ 22085 #define MAIN0_SYNCE_CONTROL_SYNCE_MODE_PHY_LANE2_MASK 0x0030 22086 #define MAIN0_SYNCE_CONTROL_SYNCE_MODE_PHY_LANE2_ALIGN 0 22087 #define MAIN0_SYNCE_CONTROL_SYNCE_MODE_PHY_LANE2_BITS 2 22088 #define MAIN0_SYNCE_CONTROL_SYNCE_MODE_PHY_LANE2_SHIFT 4 22089 #define MAIN0_SYNCE_CONTROL_SYNCE_MODE_PHY_LANE2_SYNCE_NO_DIV 0 22090 #define MAIN0_SYNCE_CONTROL_SYNCE_MODE_PHY_LANE2_SYNCE_DIV_7 1 22091 #define MAIN0_SYNCE_CONTROL_SYNCE_MODE_PHY_LANE2_SYNCE_DIV_11 2 22092 22093 /* Main0 :: synce_control :: synce_mode_phy_lane1 [03:02] */ 22094 #define MAIN0_SYNCE_CONTROL_SYNCE_MODE_PHY_LANE1_MASK 0x000c 22095 #define MAIN0_SYNCE_CONTROL_SYNCE_MODE_PHY_LANE1_ALIGN 0 22096 #define MAIN0_SYNCE_CONTROL_SYNCE_MODE_PHY_LANE1_BITS 2 22097 #define MAIN0_SYNCE_CONTROL_SYNCE_MODE_PHY_LANE1_SHIFT 2 22098 #define MAIN0_SYNCE_CONTROL_SYNCE_MODE_PHY_LANE1_SYNCE_NO_DIV 0 22099 #define MAIN0_SYNCE_CONTROL_SYNCE_MODE_PHY_LANE1_SYNCE_DIV_7 1 22100 #define MAIN0_SYNCE_CONTROL_SYNCE_MODE_PHY_LANE1_SYNCE_DIV_11 2 22101 22102 /* Main0 :: synce_control :: synce_mode_phy_lane0 [01:00] */ 22103 #define MAIN0_SYNCE_CONTROL_SYNCE_MODE_PHY_LANE0_MASK 0x0003 22104 #define MAIN0_SYNCE_CONTROL_SYNCE_MODE_PHY_LANE0_ALIGN 0 22105 #define MAIN0_SYNCE_CONTROL_SYNCE_MODE_PHY_LANE0_BITS 2 22106 #define MAIN0_SYNCE_CONTROL_SYNCE_MODE_PHY_LANE0_SHIFT 0 22107 #define MAIN0_SYNCE_CONTROL_SYNCE_MODE_PHY_LANE0_SYNCE_NO_DIV 0 22108 #define MAIN0_SYNCE_CONTROL_SYNCE_MODE_PHY_LANE0_SYNCE_DIV_7 1 22109 #define MAIN0_SYNCE_CONTROL_SYNCE_MODE_PHY_LANE0_SYNCE_DIV_11 2 22110 22111 22112 /**************************************************************************** 22113 * Main0 :: synce_control_stage0 22114 */ 22115 /* Main0 :: synce_control_stage0 :: reserved0 [15:08] */ 22116 #define MAIN0_SYNCE_CONTROL_STAGE0_RESERVED0_MASK 0xff00 22117 #define MAIN0_SYNCE_CONTROL_STAGE0_RESERVED0_ALIGN 0 22118 #define MAIN0_SYNCE_CONTROL_STAGE0_RESERVED0_BITS 8 22119 #define MAIN0_SYNCE_CONTROL_STAGE0_RESERVED0_SHIFT 8 22120 22121 /* Main0 :: synce_control_stage0 :: synce_stage0_mode_phy_lane3 [07:06] */ 22122 #define MAIN0_SYNCE_CONTROL_STAGE0_SYNCE_STAGE0_MODE_PHY_LANE3_MASK 0x00c0 22123 #define MAIN0_SYNCE_CONTROL_STAGE0_SYNCE_STAGE0_MODE_PHY_LANE3_ALIGN 0 22124 #define MAIN0_SYNCE_CONTROL_STAGE0_SYNCE_STAGE0_MODE_PHY_LANE3_BITS 2 22125 #define MAIN0_SYNCE_CONTROL_STAGE0_SYNCE_STAGE0_MODE_PHY_LANE3_SHIFT 6 22126 #define MAIN0_SYNCE_CONTROL_STAGE0_SYNCE_STAGE0_MODE_PHY_LANE3_SYNCE_NO_DIV 0 22127 #define MAIN0_SYNCE_CONTROL_STAGE0_SYNCE_STAGE0_MODE_PHY_LANE3_SYNCE_DIV_GAP_CLK_4_OVER_5 1 22128 #define MAIN0_SYNCE_CONTROL_STAGE0_SYNCE_STAGE0_MODE_PHY_LANE3_SYNCE_DIV_SDM_FRAC_DIV 2 22129 22130 /* Main0 :: synce_control_stage0 :: synce_stage0_mode_phy_lane2 [05:04] */ 22131 #define MAIN0_SYNCE_CONTROL_STAGE0_SYNCE_STAGE0_MODE_PHY_LANE2_MASK 0x0030 22132 #define MAIN0_SYNCE_CONTROL_STAGE0_SYNCE_STAGE0_MODE_PHY_LANE2_ALIGN 0 22133 #define MAIN0_SYNCE_CONTROL_STAGE0_SYNCE_STAGE0_MODE_PHY_LANE2_BITS 2 22134 #define MAIN0_SYNCE_CONTROL_STAGE0_SYNCE_STAGE0_MODE_PHY_LANE2_SHIFT 4 22135 #define MAIN0_SYNCE_CONTROL_STAGE0_SYNCE_STAGE0_MODE_PHY_LANE2_SYNCE_NO_DIV 0 22136 #define MAIN0_SYNCE_CONTROL_STAGE0_SYNCE_STAGE0_MODE_PHY_LANE2_SYNCE_DIV_GAP_CLK_4_OVER_5 1 22137 #define MAIN0_SYNCE_CONTROL_STAGE0_SYNCE_STAGE0_MODE_PHY_LANE2_SYNCE_DIV_SDM_FRAC_DIV 2 22138 22139 /* Main0 :: synce_control_stage0 :: synce_stage0_mode_phy_lane1 [03:02] */ 22140 #define MAIN0_SYNCE_CONTROL_STAGE0_SYNCE_STAGE0_MODE_PHY_LANE1_MASK 0x000c 22141 #define MAIN0_SYNCE_CONTROL_STAGE0_SYNCE_STAGE0_MODE_PHY_LANE1_ALIGN 0 22142 #define MAIN0_SYNCE_CONTROL_STAGE0_SYNCE_STAGE0_MODE_PHY_LANE1_BITS 2 22143 #define MAIN0_SYNCE_CONTROL_STAGE0_SYNCE_STAGE0_MODE_PHY_LANE1_SHIFT 2 22144 #define MAIN0_SYNCE_CONTROL_STAGE0_SYNCE_STAGE0_MODE_PHY_LANE1_SYNCE_NO_DIV 0 22145 #define MAIN0_SYNCE_CONTROL_STAGE0_SYNCE_STAGE0_MODE_PHY_LANE1_SYNCE_DIV_GAP_CLK_4_OVER_5 1 22146 #define MAIN0_SYNCE_CONTROL_STAGE0_SYNCE_STAGE0_MODE_PHY_LANE1_SYNCE_DIV_SDM_FRAC_DIV 2 22147 22148 /* Main0 :: synce_control_stage0 :: synce_stage0_mode_phy_lane0 [01:00] */ 22149 #define MAIN0_SYNCE_CONTROL_STAGE0_SYNCE_STAGE0_MODE_PHY_LANE0_MASK 0x0003 22150 #define MAIN0_SYNCE_CONTROL_STAGE0_SYNCE_STAGE0_MODE_PHY_LANE0_ALIGN 0 22151 #define MAIN0_SYNCE_CONTROL_STAGE0_SYNCE_STAGE0_MODE_PHY_LANE0_BITS 2 22152 #define MAIN0_SYNCE_CONTROL_STAGE0_SYNCE_STAGE0_MODE_PHY_LANE0_SHIFT 0 22153 #define MAIN0_SYNCE_CONTROL_STAGE0_SYNCE_STAGE0_MODE_PHY_LANE0_SYNCE_NO_DIV 0 22154 #define MAIN0_SYNCE_CONTROL_STAGE0_SYNCE_STAGE0_MODE_PHY_LANE0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 22155 #define MAIN0_SYNCE_CONTROL_STAGE0_SYNCE_STAGE0_MODE_PHY_LANE0_SYNCE_DIV_SDM_FRAC_DIV 2 22156 22157 22158 /**************************************************************************** 22159 * Main0 :: speed_ctrl 22160 */ 22161 /* Main0 :: speed_ctrl :: reserved0 [15:12] */ 22162 #define MAIN0_SPEED_CTRL_RESERVED0_MASK 0xf000 22163 #define MAIN0_SPEED_CTRL_RESERVED0_ALIGN 0 22164 #define MAIN0_SPEED_CTRL_RESERVED0_BITS 4 22165 #define MAIN0_SPEED_CTRL_RESERVED0_SHIFT 12 22166 22167 /* Main0 :: speed_ctrl :: tsc_credit_sel [11:11] */ 22168 #define MAIN0_SPEED_CTRL_TSC_CREDIT_SEL_MASK 0x0800 22169 #define MAIN0_SPEED_CTRL_TSC_CREDIT_SEL_ALIGN 0 22170 #define MAIN0_SPEED_CTRL_TSC_CREDIT_SEL_BITS 1 22171 #define MAIN0_SPEED_CTRL_TSC_CREDIT_SEL_SHIFT 11 22172 22173 /* Main0 :: speed_ctrl :: reserved1 [10:09] */ 22174 #define MAIN0_SPEED_CTRL_RESERVED1_MASK 0x0600 22175 #define MAIN0_SPEED_CTRL_RESERVED1_ALIGN 0 22176 #define MAIN0_SPEED_CTRL_RESERVED1_BITS 2 22177 #define MAIN0_SPEED_CTRL_RESERVED1_SHIFT 9 22178 22179 /* Main0 :: speed_ctrl :: pll_reset_en [08:08] */ 22180 #define MAIN0_SPEED_CTRL_PLL_RESET_EN_MASK 0x0100 22181 #define MAIN0_SPEED_CTRL_PLL_RESET_EN_ALIGN 0 22182 #define MAIN0_SPEED_CTRL_PLL_RESET_EN_BITS 1 22183 #define MAIN0_SPEED_CTRL_PLL_RESET_EN_SHIFT 8 22184 22185 /* Main0 :: speed_ctrl :: reserved2 [07:00] */ 22186 #define MAIN0_SPEED_CTRL_RESERVED2_MASK 0x00ff 22187 #define MAIN0_SPEED_CTRL_RESERVED2_ALIGN 0 22188 #define MAIN0_SPEED_CTRL_RESERVED2_BITS 8 22189 #define MAIN0_SPEED_CTRL_RESERVED2_SHIFT 0 22190 22191 22192 /**************************************************************************** 22193 * Main0 :: deviceInPkg5 22194 */ 22195 /* Main0 :: deviceInPkg5 :: reserved0 [15:08] */ 22196 #define MAIN0_DEVICEINPKG5_RESERVED0_MASK 0xff00 22197 #define MAIN0_DEVICEINPKG5_RESERVED0_ALIGN 0 22198 #define MAIN0_DEVICEINPKG5_RESERVED0_BITS 8 22199 #define MAIN0_DEVICEINPKG5_RESERVED0_SHIFT 8 22200 22201 /* Main0 :: deviceInPkg5 :: AN [07:07] */ 22202 #define MAIN0_DEVICEINPKG5_AN_MASK 0x0080 22203 #define MAIN0_DEVICEINPKG5_AN_ALIGN 0 22204 #define MAIN0_DEVICEINPKG5_AN_BITS 1 22205 #define MAIN0_DEVICEINPKG5_AN_SHIFT 7 22206 22207 /* Main0 :: deviceInPkg5 :: TC [06:06] */ 22208 #define MAIN0_DEVICEINPKG5_TC_MASK 0x0040 22209 #define MAIN0_DEVICEINPKG5_TC_ALIGN 0 22210 #define MAIN0_DEVICEINPKG5_TC_BITS 1 22211 #define MAIN0_DEVICEINPKG5_TC_SHIFT 6 22212 22213 /* Main0 :: deviceInPkg5 :: DTE_XS [05:05] */ 22214 #define MAIN0_DEVICEINPKG5_DTE_XS_MASK 0x0020 22215 #define MAIN0_DEVICEINPKG5_DTE_XS_ALIGN 0 22216 #define MAIN0_DEVICEINPKG5_DTE_XS_BITS 1 22217 #define MAIN0_DEVICEINPKG5_DTE_XS_SHIFT 5 22218 22219 /* Main0 :: deviceInPkg5 :: PHY_XS [04:04] */ 22220 #define MAIN0_DEVICEINPKG5_PHY_XS_MASK 0x0010 22221 #define MAIN0_DEVICEINPKG5_PHY_XS_ALIGN 0 22222 #define MAIN0_DEVICEINPKG5_PHY_XS_BITS 1 22223 #define MAIN0_DEVICEINPKG5_PHY_XS_SHIFT 4 22224 22225 /* Main0 :: deviceInPkg5 :: PCS_XS [03:03] */ 22226 #define MAIN0_DEVICEINPKG5_PCS_XS_MASK 0x0008 22227 #define MAIN0_DEVICEINPKG5_PCS_XS_ALIGN 0 22228 #define MAIN0_DEVICEINPKG5_PCS_XS_BITS 1 22229 #define MAIN0_DEVICEINPKG5_PCS_XS_SHIFT 3 22230 22231 /* Main0 :: deviceInPkg5 :: WIS [02:02] */ 22232 #define MAIN0_DEVICEINPKG5_WIS_MASK 0x0004 22233 #define MAIN0_DEVICEINPKG5_WIS_ALIGN 0 22234 #define MAIN0_DEVICEINPKG5_WIS_BITS 1 22235 #define MAIN0_DEVICEINPKG5_WIS_SHIFT 2 22236 22237 /* Main0 :: deviceInPkg5 :: PMA_PMD [01:01] */ 22238 #define MAIN0_DEVICEINPKG5_PMA_PMD_MASK 0x0002 22239 #define MAIN0_DEVICEINPKG5_PMA_PMD_ALIGN 0 22240 #define MAIN0_DEVICEINPKG5_PMA_PMD_BITS 1 22241 #define MAIN0_DEVICEINPKG5_PMA_PMD_SHIFT 1 22242 22243 /* Main0 :: deviceInPkg5 :: Clause22 [00:00] */ 22244 #define MAIN0_DEVICEINPKG5_CLAUSE22_MASK 0x0001 22245 #define MAIN0_DEVICEINPKG5_CLAUSE22_ALIGN 0 22246 #define MAIN0_DEVICEINPKG5_CLAUSE22_BITS 1 22247 #define MAIN0_DEVICEINPKG5_CLAUSE22_SHIFT 0 22248 22249 22250 /**************************************************************************** 22251 * Main0 :: tick_control_1 22252 */ 22253 /* Main0 :: tick_control_1 :: tick_override [15:15] */ 22254 #define MAIN0_TICK_CONTROL_1_TICK_OVERRIDE_MASK 0x8000 22255 #define MAIN0_TICK_CONTROL_1_TICK_OVERRIDE_ALIGN 0 22256 #define MAIN0_TICK_CONTROL_1_TICK_OVERRIDE_BITS 1 22257 #define MAIN0_TICK_CONTROL_1_TICK_OVERRIDE_SHIFT 15 22258 22259 /* Main0 :: tick_control_1 :: tick_numerator_upper [14:00] */ 22260 #define MAIN0_TICK_CONTROL_1_TICK_NUMERATOR_UPPER_MASK 0x7fff 22261 #define MAIN0_TICK_CONTROL_1_TICK_NUMERATOR_UPPER_ALIGN 0 22262 #define MAIN0_TICK_CONTROL_1_TICK_NUMERATOR_UPPER_BITS 15 22263 #define MAIN0_TICK_CONTROL_1_TICK_NUMERATOR_UPPER_SHIFT 0 22264 22265 22266 /**************************************************************************** 22267 * Main0 :: tick_control_0 22268 */ 22269 /* Main0 :: tick_control_0 :: tick_numerator_lower [15:12] */ 22270 #define MAIN0_TICK_CONTROL_0_TICK_NUMERATOR_LOWER_MASK 0xf000 22271 #define MAIN0_TICK_CONTROL_0_TICK_NUMERATOR_LOWER_ALIGN 0 22272 #define MAIN0_TICK_CONTROL_0_TICK_NUMERATOR_LOWER_BITS 4 22273 #define MAIN0_TICK_CONTROL_0_TICK_NUMERATOR_LOWER_SHIFT 12 22274 22275 /* Main0 :: tick_control_0 :: tick_denominator [11:02] */ 22276 #define MAIN0_TICK_CONTROL_0_TICK_DENOMINATOR_MASK 0x0ffc 22277 #define MAIN0_TICK_CONTROL_0_TICK_DENOMINATOR_ALIGN 0 22278 #define MAIN0_TICK_CONTROL_0_TICK_DENOMINATOR_BITS 10 22279 #define MAIN0_TICK_CONTROL_0_TICK_DENOMINATOR_SHIFT 2 22280 22281 /* Main0 :: tick_control_0 :: reserved0 [01:00] */ 22282 #define MAIN0_TICK_CONTROL_0_RESERVED0_MASK 0x0003 22283 #define MAIN0_TICK_CONTROL_0_RESERVED0_ALIGN 0 22284 #define MAIN0_TICK_CONTROL_0_RESERVED0_BITS 2 22285 #define MAIN0_TICK_CONTROL_0_RESERVED0_SHIFT 0 22286 22287 22288 /**************************************************************************** 22289 * Main0 :: loopback_control 22290 */ 22291 /* Main0 :: loopback_control :: reserved0 [15:08] */ 22292 #define MAIN0_LOOPBACK_CONTROL_RESERVED0_MASK 0xff00 22293 #define MAIN0_LOOPBACK_CONTROL_RESERVED0_ALIGN 0 22294 #define MAIN0_LOOPBACK_CONTROL_RESERVED0_BITS 8 22295 #define MAIN0_LOOPBACK_CONTROL_RESERVED0_SHIFT 8 22296 22297 /* Main0 :: loopback_control :: remote_pcs_loopback_enable [07:04] */ 22298 #define MAIN0_LOOPBACK_CONTROL_REMOTE_PCS_LOOPBACK_ENABLE_MASK 0x00f0 22299 #define MAIN0_LOOPBACK_CONTROL_REMOTE_PCS_LOOPBACK_ENABLE_ALIGN 0 22300 #define MAIN0_LOOPBACK_CONTROL_REMOTE_PCS_LOOPBACK_ENABLE_BITS 4 22301 #define MAIN0_LOOPBACK_CONTROL_REMOTE_PCS_LOOPBACK_ENABLE_SHIFT 4 22302 22303 /* Main0 :: loopback_control :: local_pcs_loopback_enable [03:00] */ 22304 #define MAIN0_LOOPBACK_CONTROL_LOCAL_PCS_LOOPBACK_ENABLE_MASK 0x000f 22305 #define MAIN0_LOOPBACK_CONTROL_LOCAL_PCS_LOOPBACK_ENABLE_ALIGN 0 22306 #define MAIN0_LOOPBACK_CONTROL_LOCAL_PCS_LOOPBACK_ENABLE_BITS 4 22307 #define MAIN0_LOOPBACK_CONTROL_LOCAL_PCS_LOOPBACK_ENABLE_SHIFT 0 22308 22309 22310 /**************************************************************************** 22311 * Main0 :: mdio_broadcast 22312 */ 22313 /* Main0 :: mdio_broadcast :: prtad_bcst [15:11] */ 22314 #define MAIN0_MDIO_BROADCAST_PRTAD_BCST_MASK 0xf800 22315 #define MAIN0_MDIO_BROADCAST_PRTAD_BCST_ALIGN 0 22316 #define MAIN0_MDIO_BROADCAST_PRTAD_BCST_BITS 5 22317 #define MAIN0_MDIO_BROADCAST_PRTAD_BCST_SHIFT 11 22318 22319 /* Main0 :: mdio_broadcast :: multiPRTs_en [10:07] */ 22320 #define MAIN0_MDIO_BROADCAST_MULTIPRTS_EN_MASK 0x0780 22321 #define MAIN0_MDIO_BROADCAST_MULTIPRTS_EN_ALIGN 0 22322 #define MAIN0_MDIO_BROADCAST_MULTIPRTS_EN_BITS 4 22323 #define MAIN0_MDIO_BROADCAST_MULTIPRTS_EN_SHIFT 7 22324 22325 /* Main0 :: mdio_broadcast :: reserved0 [06:00] */ 22326 #define MAIN0_MDIO_BROADCAST_RESERVED0_MASK 0x007f 22327 #define MAIN0_MDIO_BROADCAST_RESERVED0_ALIGN 0 22328 #define MAIN0_MDIO_BROADCAST_RESERVED0_BITS 7 22329 #define MAIN0_MDIO_BROADCAST_RESERVED0_SHIFT 0 22330 22331 22332 /**************************************************************************** 22333 * Main0 :: regaccess_timeout 22334 */ 22335 /* Main0 :: regaccess_timeout :: reserved0 [15:08] */ 22336 #define MAIN0_REGACCESS_TIMEOUT_RESERVED0_MASK 0xff00 22337 #define MAIN0_REGACCESS_TIMEOUT_RESERVED0_ALIGN 0 22338 #define MAIN0_REGACCESS_TIMEOUT_RESERVED0_BITS 8 22339 #define MAIN0_REGACCESS_TIMEOUT_RESERVED0_SHIFT 8 22340 22341 /* Main0 :: regaccess_timeout :: timeout_count [07:00] */ 22342 #define MAIN0_REGACCESS_TIMEOUT_TIMEOUT_COUNT_MASK 0x00ff 22343 #define MAIN0_REGACCESS_TIMEOUT_TIMEOUT_COUNT_ALIGN 0 22344 #define MAIN0_REGACCESS_TIMEOUT_TIMEOUT_COUNT_BITS 8 22345 #define MAIN0_REGACCESS_TIMEOUT_TIMEOUT_COUNT_SHIFT 0 22346 22347 22348 /**************************************************************************** 22349 * Main0 :: regaccess_timeout_status 22350 */ 22351 /* Main0 :: regaccess_timeout_status :: reserved0 [15:01] */ 22352 #define MAIN0_REGACCESS_TIMEOUT_STATUS_RESERVED0_MASK 0xfffe 22353 #define MAIN0_REGACCESS_TIMEOUT_STATUS_RESERVED0_ALIGN 0 22354 #define MAIN0_REGACCESS_TIMEOUT_STATUS_RESERVED0_BITS 15 22355 #define MAIN0_REGACCESS_TIMEOUT_STATUS_RESERVED0_SHIFT 1 22356 22357 /* Main0 :: regaccess_timeout_status :: timeout_error [00:00] */ 22358 #define MAIN0_REGACCESS_TIMEOUT_STATUS_TIMEOUT_ERROR_MASK 0x0001 22359 #define MAIN0_REGACCESS_TIMEOUT_STATUS_TIMEOUT_ERROR_ALIGN 0 22360 #define MAIN0_REGACCESS_TIMEOUT_STATUS_TIMEOUT_ERROR_BITS 1 22361 #define MAIN0_REGACCESS_TIMEOUT_STATUS_TIMEOUT_ERROR_SHIFT 0 22362 22363 22364 /**************************************************************************** 22365 * Main0 :: serdesID 22366 */ 22367 /* Main0 :: serdesID :: rev_letter [15:14] */ 22368 #define MAIN0_SERDESID_REV_LETTER_MASK 0xc000 22369 #define MAIN0_SERDESID_REV_LETTER_ALIGN 0 22370 #define MAIN0_SERDESID_REV_LETTER_BITS 2 22371 #define MAIN0_SERDESID_REV_LETTER_SHIFT 14 22372 #define MAIN0_SERDESID_REV_LETTER_REV_A 0 22373 #define MAIN0_SERDESID_REV_LETTER_REV_B 1 22374 #define MAIN0_SERDESID_REV_LETTER_REV_C 2 22375 #define MAIN0_SERDESID_REV_LETTER_REV_D 3 22376 22377 /* Main0 :: serdesID :: rev_number [13:11] */ 22378 #define MAIN0_SERDESID_REV_NUMBER_MASK 0x3800 22379 #define MAIN0_SERDESID_REV_NUMBER_ALIGN 0 22380 #define MAIN0_SERDESID_REV_NUMBER_BITS 3 22381 #define MAIN0_SERDESID_REV_NUMBER_SHIFT 11 22382 #define MAIN0_SERDESID_REV_NUMBER_REV_0 0 22383 #define MAIN0_SERDESID_REV_NUMBER_REV_1 1 22384 #define MAIN0_SERDESID_REV_NUMBER_REV_2 2 22385 #define MAIN0_SERDESID_REV_NUMBER_REV_3 3 22386 #define MAIN0_SERDESID_REV_NUMBER_REV_4 4 22387 #define MAIN0_SERDESID_REV_NUMBER_REV_5 5 22388 #define MAIN0_SERDESID_REV_NUMBER_REV_6 6 22389 #define MAIN0_SERDESID_REV_NUMBER_REV_7 7 22390 22391 /* Main0 :: serdesID :: bonding [10:09] */ 22392 #define MAIN0_SERDESID_BONDING_MASK 0x0600 22393 #define MAIN0_SERDESID_BONDING_ALIGN 0 22394 #define MAIN0_SERDESID_BONDING_BITS 2 22395 #define MAIN0_SERDESID_BONDING_SHIFT 9 22396 #define MAIN0_SERDESID_BONDING_WIRE_BOND 0 22397 #define MAIN0_SERDESID_BONDING_FLIP_CHIP 1 22398 22399 /* Main0 :: serdesID :: tech_proc [08:06] */ 22400 #define MAIN0_SERDESID_TECH_PROC_MASK 0x01c0 22401 #define MAIN0_SERDESID_TECH_PROC_ALIGN 0 22402 #define MAIN0_SERDESID_TECH_PROC_BITS 3 22403 #define MAIN0_SERDESID_TECH_PROC_SHIFT 6 22404 #define MAIN0_SERDESID_TECH_PROC_PROCESS_90NM 0 22405 #define MAIN0_SERDESID_TECH_PROC_PROCESS_65NM 1 22406 #define MAIN0_SERDESID_TECH_PROC_PROCESS_40NM 2 22407 #define MAIN0_SERDESID_TECH_PROC_PROCESS_28NM 3 22408 #define MAIN0_SERDESID_TECH_PROC_PROCESS_16NM 4 22409 22410 /* Main0 :: serdesID :: model_number [05:00] */ 22411 #define MAIN0_SERDESID_MODEL_NUMBER_MASK 0x003f 22412 #define MAIN0_SERDESID_MODEL_NUMBER_ALIGN 0 22413 #define MAIN0_SERDESID_MODEL_NUMBER_BITS 6 22414 #define MAIN0_SERDESID_MODEL_NUMBER_SHIFT 0 22415 #define MAIN0_SERDESID_MODEL_NUMBER_SERDES_CL73 0 22416 #define MAIN0_SERDESID_MODEL_NUMBER_XGXS_16G 1 22417 #define MAIN0_SERDESID_MODEL_NUMBER_HYPERCORE 2 22418 #define MAIN0_SERDESID_MODEL_NUMBER_HYPERLITE 3 22419 #define MAIN0_SERDESID_MODEL_NUMBER_PCIE_G2_PIPE 4 22420 #define MAIN0_SERDESID_MODEL_NUMBER_SERDES_1p25GBd 5 22421 #define MAIN0_SERDESID_MODEL_NUMBER_SATA2 6 22422 #define MAIN0_SERDESID_MODEL_NUMBER_QSGMII 7 22423 #define MAIN0_SERDESID_MODEL_NUMBER_XGXS10G 8 22424 #define MAIN0_SERDESID_MODEL_NUMBER_WARPCORE 9 22425 #define MAIN0_SERDESID_MODEL_NUMBER_XFICORE 10 22426 #define MAIN0_SERDESID_MODEL_NUMBER_RXFI 11 22427 #define MAIN0_SERDESID_MODEL_NUMBER_WARPLITE 12 22428 #define MAIN0_SERDESID_MODEL_NUMBER_PENTACORE 13 22429 #define MAIN0_SERDESID_MODEL_NUMBER_ESM 14 22430 #define MAIN0_SERDESID_MODEL_NUMBER_QUAD_SGMII 15 22431 #define MAIN0_SERDESID_MODEL_NUMBER_WARPCORE_3 16 22432 #define MAIN0_SERDESID_MODEL_NUMBER_TSC 17 22433 #define MAIN0_SERDESID_MODEL_NUMBER_TSC4E 18 22434 #define MAIN0_SERDESID_MODEL_NUMBER_TSC12E 19 22435 #define MAIN0_SERDESID_MODEL_NUMBER_TSC4F 20 22436 #define MAIN0_SERDESID_MODEL_NUMBER_TSC4F_GEN2 21 22437 #define MAIN0_SERDESID_MODEL_NUMBER_XGXS_CL73_90NM 29 22438 #define MAIN0_SERDESID_MODEL_NUMBER_SERDES_CL73_90NM 30 22439 #define MAIN0_SERDESID_MODEL_NUMBER_WARPCORE3 32 22440 #define MAIN0_SERDESID_MODEL_NUMBER_WARPCORE4_TSC 33 22441 #define MAIN0_SERDESID_MODEL_NUMBER_RXAUI 34 22442 22443 22444 /**************************************************************************** 22445 * Main0 :: ieee_25g_mode 22446 */ 22447 /* Main0 :: ieee_25g_mode :: reserved0 [15:06] */ 22448 #define MAIN0_IEEE_25G_MODE_RESERVED0_MASK 0xffc0 22449 #define MAIN0_IEEE_25G_MODE_RESERVED0_ALIGN 0 22450 #define MAIN0_IEEE_25G_MODE_RESERVED0_BITS 10 22451 #define MAIN0_IEEE_25G_MODE_RESERVED0_SHIFT 6 22452 22453 /* Main0 :: ieee_25g_mode :: cw_scr_en [05:05] */ 22454 #define MAIN0_IEEE_25G_MODE_CW_SCR_EN_MASK 0x0020 22455 #define MAIN0_IEEE_25G_MODE_CW_SCR_EN_ALIGN 0 22456 #define MAIN0_IEEE_25G_MODE_CW_SCR_EN_BITS 1 22457 #define MAIN0_IEEE_25G_MODE_CW_SCR_EN_SHIFT 5 22458 22459 /* Main0 :: ieee_25g_mode :: five_bit_xor [04:04] */ 22460 #define MAIN0_IEEE_25G_MODE_FIVE_BIT_XOR_MASK 0x0010 22461 #define MAIN0_IEEE_25G_MODE_FIVE_BIT_XOR_ALIGN 0 22462 #define MAIN0_IEEE_25G_MODE_FIVE_BIT_XOR_BITS 1 22463 #define MAIN0_IEEE_25G_MODE_FIVE_BIT_XOR_SHIFT 4 22464 22465 /* Main0 :: ieee_25g_mode :: cw_bndry_lock [03:03] */ 22466 #define MAIN0_IEEE_25G_MODE_CW_BNDRY_LOCK_MASK 0x0008 22467 #define MAIN0_IEEE_25G_MODE_CW_BNDRY_LOCK_ALIGN 0 22468 #define MAIN0_IEEE_25G_MODE_CW_BNDRY_LOCK_BITS 1 22469 #define MAIN0_IEEE_25G_MODE_CW_BNDRY_LOCK_SHIFT 3 22470 22471 /* Main0 :: ieee_25g_mode :: second_grp_corrupt [02:02] */ 22472 #define MAIN0_IEEE_25G_MODE_SECOND_GRP_CORRUPT_MASK 0x0004 22473 #define MAIN0_IEEE_25G_MODE_SECOND_GRP_CORRUPT_ALIGN 0 22474 #define MAIN0_IEEE_25G_MODE_SECOND_GRP_CORRUPT_BITS 1 22475 #define MAIN0_IEEE_25G_MODE_SECOND_GRP_CORRUPT_SHIFT 2 22476 22477 /* Main0 :: ieee_25g_mode :: am_mode [01:00] */ 22478 #define MAIN0_IEEE_25G_MODE_AM_MODE_MASK 0x0003 22479 #define MAIN0_IEEE_25G_MODE_AM_MODE_ALIGN 0 22480 #define MAIN0_IEEE_25G_MODE_AM_MODE_BITS 2 22481 #define MAIN0_IEEE_25G_MODE_AM_MODE_SHIFT 0 22482 22483 22484 /**************************************************************************** 22485 * TSC_WC4_TSC_USER1_pmd_x1 22486 */ 22487 /**************************************************************************** 22488 * pmd_x1 :: control 22489 */ 22490 /* pmd_x1 :: control :: reserved0 [15:02] */ 22491 #define PMD_X1_CONTROL_RESERVED0_MASK 0xfffc 22492 #define PMD_X1_CONTROL_RESERVED0_ALIGN 0 22493 #define PMD_X1_CONTROL_RESERVED0_BITS 14 22494 #define PMD_X1_CONTROL_RESERVED0_SHIFT 2 22495 22496 /* pmd_x1 :: control :: por_h_rstb [01:01] */ 22497 #define PMD_X1_CONTROL_POR_H_RSTB_MASK 0x0002 22498 #define PMD_X1_CONTROL_POR_H_RSTB_ALIGN 0 22499 #define PMD_X1_CONTROL_POR_H_RSTB_BITS 1 22500 #define PMD_X1_CONTROL_POR_H_RSTB_SHIFT 1 22501 22502 /* pmd_x1 :: control :: core_dp_h_rstb [00:00] */ 22503 #define PMD_X1_CONTROL_CORE_DP_H_RSTB_MASK 0x0001 22504 #define PMD_X1_CONTROL_CORE_DP_H_RSTB_ALIGN 0 22505 #define PMD_X1_CONTROL_CORE_DP_H_RSTB_BITS 1 22506 #define PMD_X1_CONTROL_CORE_DP_H_RSTB_SHIFT 0 22507 22508 22509 /**************************************************************************** 22510 * pmd_x1 :: mode 22511 */ 22512 /* pmd_x1 :: mode :: core_mode [15:00] */ 22513 #define PMD_X1_MODE_CORE_MODE_MASK 0xffff 22514 #define PMD_X1_MODE_CORE_MODE_ALIGN 0 22515 #define PMD_X1_MODE_CORE_MODE_BITS 16 22516 #define PMD_X1_MODE_CORE_MODE_SHIFT 0 22517 22518 22519 /**************************************************************************** 22520 * pmd_x1 :: status 22521 */ 22522 /* pmd_x1 :: status :: reserved0 [15:01] */ 22523 #define PMD_X1_STATUS_RESERVED0_MASK 0xfffe 22524 #define PMD_X1_STATUS_RESERVED0_ALIGN 0 22525 #define PMD_X1_STATUS_RESERVED0_BITS 15 22526 #define PMD_X1_STATUS_RESERVED0_SHIFT 1 22527 22528 /* pmd_x1 :: status :: pll_lock_sts [00:00] */ 22529 #define PMD_X1_STATUS_PLL_LOCK_STS_MASK 0x0001 22530 #define PMD_X1_STATUS_PLL_LOCK_STS_ALIGN 0 22531 #define PMD_X1_STATUS_PLL_LOCK_STS_BITS 1 22532 #define PMD_X1_STATUS_PLL_LOCK_STS_SHIFT 0 22533 22534 22535 /**************************************************************************** 22536 * pmd_x1 :: override 22537 */ 22538 /* pmd_x1 :: override :: reserved0 [15:04] */ 22539 #define PMD_X1_OVERRIDE_RESERVED0_MASK 0xfff0 22540 #define PMD_X1_OVERRIDE_RESERVED0_ALIGN 0 22541 #define PMD_X1_OVERRIDE_RESERVED0_BITS 12 22542 #define PMD_X1_OVERRIDE_RESERVED0_SHIFT 4 22543 22544 /* pmd_x1 :: override :: core_dp_h_rstb_oen [03:03] */ 22545 #define PMD_X1_OVERRIDE_CORE_DP_H_RSTB_OEN_MASK 0x0008 22546 #define PMD_X1_OVERRIDE_CORE_DP_H_RSTB_OEN_ALIGN 0 22547 #define PMD_X1_OVERRIDE_CORE_DP_H_RSTB_OEN_BITS 1 22548 #define PMD_X1_OVERRIDE_CORE_DP_H_RSTB_OEN_SHIFT 3 22549 22550 /* pmd_x1 :: override :: core_mode_oen [02:02] */ 22551 #define PMD_X1_OVERRIDE_CORE_MODE_OEN_MASK 0x0004 22552 #define PMD_X1_OVERRIDE_CORE_MODE_OEN_ALIGN 0 22553 #define PMD_X1_OVERRIDE_CORE_MODE_OEN_BITS 1 22554 #define PMD_X1_OVERRIDE_CORE_MODE_OEN_SHIFT 2 22555 22556 /* pmd_x1 :: override :: reserved1 [01:01] */ 22557 #define PMD_X1_OVERRIDE_RESERVED1_MASK 0x0002 22558 #define PMD_X1_OVERRIDE_RESERVED1_ALIGN 0 22559 #define PMD_X1_OVERRIDE_RESERVED1_BITS 1 22560 #define PMD_X1_OVERRIDE_RESERVED1_SHIFT 1 22561 22562 /* pmd_x1 :: override :: pll_lock_ovrd [00:00] */ 22563 #define PMD_X1_OVERRIDE_PLL_LOCK_OVRD_MASK 0x0001 22564 #define PMD_X1_OVERRIDE_PLL_LOCK_OVRD_ALIGN 0 22565 #define PMD_X1_OVERRIDE_PLL_LOCK_OVRD_BITS 1 22566 #define PMD_X1_OVERRIDE_PLL_LOCK_OVRD_SHIFT 0 22567 22568 22569 /**************************************************************************** 22570 * TSC_WC4_TSC_USER1_PktGen0 22571 */ 22572 /**************************************************************************** 22573 * PktGen0 :: PktGenCtrl1 22574 */ 22575 /* PktGen0 :: PktGenCtrl1 :: number_pkt [15:12] */ 22576 #define PKTGEN0_PKTGENCTRL1_NUMBER_PKT_MASK 0xf000 22577 #define PKTGEN0_PKTGENCTRL1_NUMBER_PKT_ALIGN 0 22578 #define PKTGEN0_PKTGENCTRL1_NUMBER_PKT_BITS 4 22579 #define PKTGEN0_PKTGENCTRL1_NUMBER_PKT_SHIFT 12 22580 22581 /* PktGen0 :: PktGenCtrl1 :: rx_pkt_check_en [11:11] */ 22582 #define PKTGEN0_PKTGENCTRL1_RX_PKT_CHECK_EN_MASK 0x0800 22583 #define PKTGEN0_PKTGENCTRL1_RX_PKT_CHECK_EN_ALIGN 0 22584 #define PKTGEN0_PKTGENCTRL1_RX_PKT_CHECK_EN_BITS 1 22585 #define PKTGEN0_PKTGENCTRL1_RX_PKT_CHECK_EN_SHIFT 11 22586 22587 /* PktGen0 :: PktGenCtrl1 :: rx_MSBUS_type [10:10] */ 22588 #define PKTGEN0_PKTGENCTRL1_RX_MSBUS_TYPE_MASK 0x0400 22589 #define PKTGEN0_PKTGENCTRL1_RX_MSBUS_TYPE_ALIGN 0 22590 #define PKTGEN0_PKTGENCTRL1_RX_MSBUS_TYPE_BITS 1 22591 #define PKTGEN0_PKTGENCTRL1_RX_MSBUS_TYPE_SHIFT 10 22592 22593 /* PktGen0 :: PktGenCtrl1 :: clr_crccnt [09:09] */ 22594 #define PKTGEN0_PKTGENCTRL1_CLR_CRCCNT_MASK 0x0200 22595 #define PKTGEN0_PKTGENCTRL1_CLR_CRCCNT_ALIGN 0 22596 #define PKTGEN0_PKTGENCTRL1_CLR_CRCCNT_BITS 1 22597 #define PKTGEN0_PKTGENCTRL1_CLR_CRCCNT_SHIFT 9 22598 22599 /* PktGen0 :: PktGenCtrl1 :: rx_port_sel [08:07] */ 22600 #define PKTGEN0_PKTGENCTRL1_RX_PORT_SEL_MASK 0x0180 22601 #define PKTGEN0_PKTGENCTRL1_RX_PORT_SEL_ALIGN 0 22602 #define PKTGEN0_PKTGENCTRL1_RX_PORT_SEL_BITS 2 22603 #define PKTGEN0_PKTGENCTRL1_RX_PORT_SEL_SHIFT 7 22604 22605 /* PktGen0 :: PktGenCtrl1 :: prtp_data_pattern_sel [06:03] */ 22606 #define PKTGEN0_PKTGENCTRL1_PRTP_DATA_PATTERN_SEL_MASK 0x0078 22607 #define PKTGEN0_PKTGENCTRL1_PRTP_DATA_PATTERN_SEL_ALIGN 0 22608 #define PKTGEN0_PKTGENCTRL1_PRTP_DATA_PATTERN_SEL_BITS 4 22609 #define PKTGEN0_PKTGENCTRL1_PRTP_DATA_PATTERN_SEL_SHIFT 3 22610 22611 /* PktGen0 :: PktGenCtrl1 :: lpi_en [02:02] */ 22612 #define PKTGEN0_PKTGENCTRL1_LPI_EN_MASK 0x0004 22613 #define PKTGEN0_PKTGENCTRL1_LPI_EN_ALIGN 0 22614 #define PKTGEN0_PKTGENCTRL1_LPI_EN_BITS 1 22615 #define PKTGEN0_PKTGENCTRL1_LPI_EN_SHIFT 2 22616 22617 /* PktGen0 :: PktGenCtrl1 :: tx_test_port_sel [01:00] */ 22618 #define PKTGEN0_PKTGENCTRL1_TX_TEST_PORT_SEL_MASK 0x0003 22619 #define PKTGEN0_PKTGENCTRL1_TX_TEST_PORT_SEL_ALIGN 0 22620 #define PKTGEN0_PKTGENCTRL1_TX_TEST_PORT_SEL_BITS 2 22621 #define PKTGEN0_PKTGENCTRL1_TX_TEST_PORT_SEL_SHIFT 0 22622 22623 22624 /**************************************************************************** 22625 * PktGen0 :: PktGenCtrl2 22626 */ 22627 /* PktGen0 :: PktGenCtrl2 :: pktgen_en [15:15] */ 22628 #define PKTGEN0_PKTGENCTRL2_PKTGEN_EN_MASK 0x8000 22629 #define PKTGEN0_PKTGENCTRL2_PKTGEN_EN_ALIGN 0 22630 #define PKTGEN0_PKTGENCTRL2_PKTGEN_EN_BITS 1 22631 #define PKTGEN0_PKTGENCTRL2_PKTGEN_EN_SHIFT 15 22632 22633 /* PktGen0 :: PktGenCtrl2 :: tx_MSBUS_type [14:14] */ 22634 #define PKTGEN0_PKTGENCTRL2_TX_MSBUS_TYPE_MASK 0x4000 22635 #define PKTGEN0_PKTGENCTRL2_TX_MSBUS_TYPE_ALIGN 0 22636 #define PKTGEN0_PKTGENCTRL2_TX_MSBUS_TYPE_BITS 1 22637 #define PKTGEN0_PKTGENCTRL2_TX_MSBUS_TYPE_SHIFT 14 22638 22639 /* PktGen0 :: PktGenCtrl2 :: payload_type [13:11] */ 22640 #define PKTGEN0_PKTGENCTRL2_PAYLOAD_TYPE_MASK 0x3800 22641 #define PKTGEN0_PKTGENCTRL2_PAYLOAD_TYPE_ALIGN 0 22642 #define PKTGEN0_PKTGENCTRL2_PAYLOAD_TYPE_BITS 3 22643 #define PKTGEN0_PKTGENCTRL2_PAYLOAD_TYPE_SHIFT 11 22644 #define PKTGEN0_PKTGENCTRL2_PAYLOAD_TYPE_REPEAT_2_BYTES 0 22645 #define PKTGEN0_PKTGENCTRL2_PAYLOAD_TYPE_RAMPING 1 22646 #define PKTGEN0_PKTGENCTRL2_PAYLOAD_TYPE_CL48_CRPAT 2 22647 #define PKTGEN0_PKTGENCTRL2_PAYLOAD_TYPE_CL48_CJPAT 3 22648 #define PKTGEN0_PKTGENCTRL2_PAYLOAD_TYPE_CL36_LONG_CRPAT 4 22649 #define PKTGEN0_PKTGENCTRL2_PAYLOAD_TYPE_CL36_SHORT_CRPAT 5 22650 22651 /* PktGen0 :: PktGenCtrl2 :: pkt_size [10:05] */ 22652 #define PKTGEN0_PKTGENCTRL2_PKT_SIZE_MASK 0x07e0 22653 #define PKTGEN0_PKTGENCTRL2_PKT_SIZE_ALIGN 0 22654 #define PKTGEN0_PKTGENCTRL2_PKT_SIZE_BITS 6 22655 #define PKTGEN0_PKTGENCTRL2_PKT_SIZE_SHIFT 5 22656 22657 /* PktGen0 :: PktGenCtrl2 :: ipg_size [04:00] */ 22658 #define PKTGEN0_PKTGENCTRL2_IPG_SIZE_MASK 0x001f 22659 #define PKTGEN0_PKTGENCTRL2_IPG_SIZE_ALIGN 0 22660 #define PKTGEN0_PKTGENCTRL2_IPG_SIZE_BITS 5 22661 #define PKTGEN0_PKTGENCTRL2_IPG_SIZE_SHIFT 0 22662 22663 22664 /**************************************************************************** 22665 * PktGen0 :: PktGenCtrl3 22666 */ 22667 /* PktGen0 :: PktGenCtrl3 :: reserved0 [15:09] */ 22668 #define PKTGEN0_PKTGENCTRL3_RESERVED0_MASK 0xfe00 22669 #define PKTGEN0_PKTGENCTRL3_RESERVED0_ALIGN 0 22670 #define PKTGEN0_PKTGENCTRL3_RESERVED0_BITS 7 22671 #define PKTGEN0_PKTGENCTRL3_RESERVED0_SHIFT 9 22672 22673 /* PktGen0 :: PktGenCtrl3 :: clr_rxcnt [08:05] */ 22674 #define PKTGEN0_PKTGENCTRL3_CLR_RXCNT_MASK 0x01e0 22675 #define PKTGEN0_PKTGENCTRL3_CLR_RXCNT_ALIGN 0 22676 #define PKTGEN0_PKTGENCTRL3_CLR_RXCNT_BITS 4 22677 #define PKTGEN0_PKTGENCTRL3_CLR_RXCNT_SHIFT 5 22678 22679 /* PktGen0 :: PktGenCtrl3 :: clr_txcnt [04:01] */ 22680 #define PKTGEN0_PKTGENCTRL3_CLR_TXCNT_MASK 0x001e 22681 #define PKTGEN0_PKTGENCTRL3_CLR_TXCNT_ALIGN 0 22682 #define PKTGEN0_PKTGENCTRL3_CLR_TXCNT_BITS 4 22683 #define PKTGEN0_PKTGENCTRL3_CLR_TXCNT_SHIFT 1 22684 22685 /* PktGen0 :: PktGenCtrl3 :: reserved1 [00:00] */ 22686 #define PKTGEN0_PKTGENCTRL3_RESERVED1_MASK 0x0001 22687 #define PKTGEN0_PKTGENCTRL3_RESERVED1_ALIGN 0 22688 #define PKTGEN0_PKTGENCTRL3_RESERVED1_BITS 1 22689 #define PKTGEN0_PKTGENCTRL3_RESERVED1_SHIFT 0 22690 22691 22692 /**************************************************************************** 22693 * PktGen0 :: PrtpControl 22694 */ 22695 /* PktGen0 :: PrtpControl :: tx_prtp_en [15:12] */ 22696 #define PKTGEN0_PRTPCONTROL_TX_PRTP_EN_MASK 0xf000 22697 #define PKTGEN0_PRTPCONTROL_TX_PRTP_EN_ALIGN 0 22698 #define PKTGEN0_PRTPCONTROL_TX_PRTP_EN_BITS 4 22699 #define PKTGEN0_PRTPCONTROL_TX_PRTP_EN_SHIFT 12 22700 22701 /* PktGen0 :: PrtpControl :: rx_prtp_en [11:08] */ 22702 #define PKTGEN0_PRTPCONTROL_RX_PRTP_EN_MASK 0x0f00 22703 #define PKTGEN0_PRTPCONTROL_RX_PRTP_EN_ALIGN 0 22704 #define PKTGEN0_PRTPCONTROL_RX_PRTP_EN_BITS 4 22705 #define PKTGEN0_PRTPCONTROL_RX_PRTP_EN_SHIFT 8 22706 22707 /* PktGen0 :: PrtpControl :: reserved0 [07:00] */ 22708 #define PKTGEN0_PRTPCONTROL_RESERVED0_MASK 0x00ff 22709 #define PKTGEN0_PRTPCONTROL_RESERVED0_ALIGN 0 22710 #define PKTGEN0_PRTPCONTROL_RESERVED0_BITS 8 22711 #define PKTGEN0_PRTPCONTROL_RESERVED0_SHIFT 0 22712 22713 22714 /**************************************************************************** 22715 * PktGen0 :: CrcErrorCount 22716 */ 22717 /* PktGen0 :: CrcErrorCount :: crcerrcnt [15:00] */ 22718 #define PKTGEN0_CRCERRORCOUNT_CRCERRCNT_MASK 0xffff 22719 #define PKTGEN0_CRCERRORCOUNT_CRCERRCNT_ALIGN 0 22720 #define PKTGEN0_CRCERRORCOUNT_CRCERRCNT_BITS 16 22721 #define PKTGEN0_CRCERRORCOUNT_CRCERRCNT_SHIFT 0 22722 22723 22724 /**************************************************************************** 22725 * PktGen0 :: PCS_seedA0 22726 */ 22727 /* PktGen0 :: PCS_seedA0 :: seedA0 [15:00] */ 22728 #define PKTGEN0_PCS_SEEDA0_SEEDA0_MASK 0xffff 22729 #define PKTGEN0_PCS_SEEDA0_SEEDA0_ALIGN 0 22730 #define PKTGEN0_PCS_SEEDA0_SEEDA0_BITS 16 22731 #define PKTGEN0_PCS_SEEDA0_SEEDA0_SHIFT 0 22732 22733 22734 /**************************************************************************** 22735 * PktGen0 :: PCS_seedA1 22736 */ 22737 /* PktGen0 :: PCS_seedA1 :: seedA1 [15:00] */ 22738 #define PKTGEN0_PCS_SEEDA1_SEEDA1_MASK 0xffff 22739 #define PKTGEN0_PCS_SEEDA1_SEEDA1_ALIGN 0 22740 #define PKTGEN0_PCS_SEEDA1_SEEDA1_BITS 16 22741 #define PKTGEN0_PCS_SEEDA1_SEEDA1_SHIFT 0 22742 22743 22744 /**************************************************************************** 22745 * PktGen0 :: PCS_seedA2 22746 */ 22747 /* PktGen0 :: PCS_seedA2 :: seedA2 [15:00] */ 22748 #define PKTGEN0_PCS_SEEDA2_SEEDA2_MASK 0xffff 22749 #define PKTGEN0_PCS_SEEDA2_SEEDA2_ALIGN 0 22750 #define PKTGEN0_PCS_SEEDA2_SEEDA2_BITS 16 22751 #define PKTGEN0_PCS_SEEDA2_SEEDA2_SHIFT 0 22752 22753 22754 /**************************************************************************** 22755 * PktGen0 :: PCS_seedA3 22756 */ 22757 /* PktGen0 :: PCS_seedA3 :: reserved0 [15:10] */ 22758 #define PKTGEN0_PCS_SEEDA3_RESERVED0_MASK 0xfc00 22759 #define PKTGEN0_PCS_SEEDA3_RESERVED0_ALIGN 0 22760 #define PKTGEN0_PCS_SEEDA3_RESERVED0_BITS 6 22761 #define PKTGEN0_PCS_SEEDA3_RESERVED0_SHIFT 10 22762 22763 /* PktGen0 :: PCS_seedA3 :: seedA3 [09:00] */ 22764 #define PKTGEN0_PCS_SEEDA3_SEEDA3_MASK 0x03ff 22765 #define PKTGEN0_PCS_SEEDA3_SEEDA3_ALIGN 0 22766 #define PKTGEN0_PCS_SEEDA3_SEEDA3_BITS 10 22767 #define PKTGEN0_PCS_SEEDA3_SEEDA3_SHIFT 0 22768 22769 22770 /**************************************************************************** 22771 * PktGen0 :: PCS_seedB0 22772 */ 22773 /* PktGen0 :: PCS_seedB0 :: seedB0 [15:00] */ 22774 #define PKTGEN0_PCS_SEEDB0_SEEDB0_MASK 0xffff 22775 #define PKTGEN0_PCS_SEEDB0_SEEDB0_ALIGN 0 22776 #define PKTGEN0_PCS_SEEDB0_SEEDB0_BITS 16 22777 #define PKTGEN0_PCS_SEEDB0_SEEDB0_SHIFT 0 22778 22779 22780 /**************************************************************************** 22781 * PktGen0 :: PCS_seedB1 22782 */ 22783 /* PktGen0 :: PCS_seedB1 :: seedB1 [15:00] */ 22784 #define PKTGEN0_PCS_SEEDB1_SEEDB1_MASK 0xffff 22785 #define PKTGEN0_PCS_SEEDB1_SEEDB1_ALIGN 0 22786 #define PKTGEN0_PCS_SEEDB1_SEEDB1_BITS 16 22787 #define PKTGEN0_PCS_SEEDB1_SEEDB1_SHIFT 0 22788 22789 22790 /**************************************************************************** 22791 * PktGen0 :: PCS_seedB2 22792 */ 22793 /* PktGen0 :: PCS_seedB2 :: seedB2 [15:00] */ 22794 #define PKTGEN0_PCS_SEEDB2_SEEDB2_MASK 0xffff 22795 #define PKTGEN0_PCS_SEEDB2_SEEDB2_ALIGN 0 22796 #define PKTGEN0_PCS_SEEDB2_SEEDB2_BITS 16 22797 #define PKTGEN0_PCS_SEEDB2_SEEDB2_SHIFT 0 22798 22799 22800 /**************************************************************************** 22801 * PktGen0 :: PCS_seedB3 22802 */ 22803 /* PktGen0 :: PCS_seedB3 :: reserved0 [15:10] */ 22804 #define PKTGEN0_PCS_SEEDB3_RESERVED0_MASK 0xfc00 22805 #define PKTGEN0_PCS_SEEDB3_RESERVED0_ALIGN 0 22806 #define PKTGEN0_PCS_SEEDB3_RESERVED0_BITS 6 22807 #define PKTGEN0_PCS_SEEDB3_RESERVED0_SHIFT 10 22808 22809 /* PktGen0 :: PCS_seedB3 :: seedB3 [09:00] */ 22810 #define PKTGEN0_PCS_SEEDB3_SEEDB3_MASK 0x03ff 22811 #define PKTGEN0_PCS_SEEDB3_SEEDB3_ALIGN 0 22812 #define PKTGEN0_PCS_SEEDB3_SEEDB3_BITS 10 22813 #define PKTGEN0_PCS_SEEDB3_SEEDB3_SHIFT 0 22814 22815 22816 /**************************************************************************** 22817 * TSC_WC4_TSC_USER1_PktGen1 22818 */ 22819 /**************************************************************************** 22820 * PktGen1 :: PayloadBytes 22821 */ 22822 /* PktGen1 :: PayloadBytes :: byte1 [15:08] */ 22823 #define PKTGEN1_PAYLOADBYTES_BYTE1_MASK 0xff00 22824 #define PKTGEN1_PAYLOADBYTES_BYTE1_ALIGN 0 22825 #define PKTGEN1_PAYLOADBYTES_BYTE1_BITS 8 22826 #define PKTGEN1_PAYLOADBYTES_BYTE1_SHIFT 8 22827 22828 /* PktGen1 :: PayloadBytes :: byte0 [07:00] */ 22829 #define PKTGEN1_PAYLOADBYTES_BYTE0_MASK 0x00ff 22830 #define PKTGEN1_PAYLOADBYTES_BYTE0_ALIGN 0 22831 #define PKTGEN1_PAYLOADBYTES_BYTE0_BITS 8 22832 #define PKTGEN1_PAYLOADBYTES_BYTE0_SHIFT 0 22833 22834 22835 /**************************************************************************** 22836 * PktGen1 :: ErrorMask4 22837 */ 22838 /* PktGen1 :: ErrorMask4 :: reserved0 [15:02] */ 22839 #define PKTGEN1_ERRORMASK4_RESERVED0_MASK 0xfffc 22840 #define PKTGEN1_ERRORMASK4_RESERVED0_ALIGN 0 22841 #define PKTGEN1_ERRORMASK4_RESERVED0_BITS 14 22842 #define PKTGEN1_ERRORMASK4_RESERVED0_SHIFT 2 22843 22844 /* PktGen1 :: ErrorMask4 :: error_mask_65_64 [01:00] */ 22845 #define PKTGEN1_ERRORMASK4_ERROR_MASK_65_64_MASK 0x0003 22846 #define PKTGEN1_ERRORMASK4_ERROR_MASK_65_64_ALIGN 0 22847 #define PKTGEN1_ERRORMASK4_ERROR_MASK_65_64_BITS 2 22848 #define PKTGEN1_ERRORMASK4_ERROR_MASK_65_64_SHIFT 0 22849 22850 22851 /**************************************************************************** 22852 * PktGen1 :: ErrorMask3 22853 */ 22854 /* PktGen1 :: ErrorMask3 :: error_mask_63_48 [15:00] */ 22855 #define PKTGEN1_ERRORMASK3_ERROR_MASK_63_48_MASK 0xffff 22856 #define PKTGEN1_ERRORMASK3_ERROR_MASK_63_48_ALIGN 0 22857 #define PKTGEN1_ERRORMASK3_ERROR_MASK_63_48_BITS 16 22858 #define PKTGEN1_ERRORMASK3_ERROR_MASK_63_48_SHIFT 0 22859 22860 22861 /**************************************************************************** 22862 * PktGen1 :: ErrorMask2 22863 */ 22864 /* PktGen1 :: ErrorMask2 :: error_mask_47_32 [15:00] */ 22865 #define PKTGEN1_ERRORMASK2_ERROR_MASK_47_32_MASK 0xffff 22866 #define PKTGEN1_ERRORMASK2_ERROR_MASK_47_32_ALIGN 0 22867 #define PKTGEN1_ERRORMASK2_ERROR_MASK_47_32_BITS 16 22868 #define PKTGEN1_ERRORMASK2_ERROR_MASK_47_32_SHIFT 0 22869 22870 22871 /**************************************************************************** 22872 * PktGen1 :: ErrorMask1 22873 */ 22874 /* PktGen1 :: ErrorMask1 :: error_mask_31_16 [15:00] */ 22875 #define PKTGEN1_ERRORMASK1_ERROR_MASK_31_16_MASK 0xffff 22876 #define PKTGEN1_ERRORMASK1_ERROR_MASK_31_16_ALIGN 0 22877 #define PKTGEN1_ERRORMASK1_ERROR_MASK_31_16_BITS 16 22878 #define PKTGEN1_ERRORMASK1_ERROR_MASK_31_16_SHIFT 0 22879 22880 22881 /**************************************************************************** 22882 * PktGen1 :: ErrorMask0 22883 */ 22884 /* PktGen1 :: ErrorMask0 :: error_mask_15_0 [15:00] */ 22885 #define PKTGEN1_ERRORMASK0_ERROR_MASK_15_0_MASK 0xffff 22886 #define PKTGEN1_ERRORMASK0_ERROR_MASK_15_0_ALIGN 0 22887 #define PKTGEN1_ERRORMASK0_ERROR_MASK_15_0_BITS 16 22888 #define PKTGEN1_ERRORMASK0_ERROR_MASK_15_0_SHIFT 0 22889 22890 22891 /**************************************************************************** 22892 * PktGen1 :: Err_inj_en0 22893 */ 22894 /* PktGen1 :: Err_inj_en0 :: reserved0 [15:15] */ 22895 #define PKTGEN1_ERR_INJ_EN0_RESERVED0_MASK 0x8000 22896 #define PKTGEN1_ERR_INJ_EN0_RESERVED0_ALIGN 0 22897 #define PKTGEN1_ERR_INJ_EN0_RESERVED0_BITS 1 22898 #define PKTGEN1_ERR_INJ_EN0_RESERVED0_SHIFT 15 22899 22900 /* PktGen1 :: Err_inj_en0 :: errgen_en_ph2 [14:10] */ 22901 #define PKTGEN1_ERR_INJ_EN0_ERRGEN_EN_PH2_MASK 0x7c00 22902 #define PKTGEN1_ERR_INJ_EN0_ERRGEN_EN_PH2_ALIGN 0 22903 #define PKTGEN1_ERR_INJ_EN0_ERRGEN_EN_PH2_BITS 5 22904 #define PKTGEN1_ERR_INJ_EN0_ERRGEN_EN_PH2_SHIFT 10 22905 22906 /* PktGen1 :: Err_inj_en0 :: errgen_en_ph1 [09:05] */ 22907 #define PKTGEN1_ERR_INJ_EN0_ERRGEN_EN_PH1_MASK 0x03e0 22908 #define PKTGEN1_ERR_INJ_EN0_ERRGEN_EN_PH1_ALIGN 0 22909 #define PKTGEN1_ERR_INJ_EN0_ERRGEN_EN_PH1_BITS 5 22910 #define PKTGEN1_ERR_INJ_EN0_ERRGEN_EN_PH1_SHIFT 5 22911 22912 /* PktGen1 :: Err_inj_en0 :: errgen_en_ph0 [04:00] */ 22913 #define PKTGEN1_ERR_INJ_EN0_ERRGEN_EN_PH0_MASK 0x001f 22914 #define PKTGEN1_ERR_INJ_EN0_ERRGEN_EN_PH0_ALIGN 0 22915 #define PKTGEN1_ERR_INJ_EN0_ERRGEN_EN_PH0_BITS 5 22916 #define PKTGEN1_ERR_INJ_EN0_ERRGEN_EN_PH0_SHIFT 0 22917 22918 22919 /**************************************************************************** 22920 * PktGen1 :: Err_inj_en1 22921 */ 22922 /* PktGen1 :: Err_inj_en1 :: reserved0 [15:13] */ 22923 #define PKTGEN1_ERR_INJ_EN1_RESERVED0_MASK 0xe000 22924 #define PKTGEN1_ERR_INJ_EN1_RESERVED0_ALIGN 0 22925 #define PKTGEN1_ERR_INJ_EN1_RESERVED0_BITS 3 22926 #define PKTGEN1_ERR_INJ_EN1_RESERVED0_SHIFT 13 22927 22928 /* PktGen1 :: Err_inj_en1 :: cl91_80b_errgen_en_p3 [12:12] */ 22929 #define PKTGEN1_ERR_INJ_EN1_CL91_80B_ERRGEN_EN_P3_MASK 0x1000 22930 #define PKTGEN1_ERR_INJ_EN1_CL91_80B_ERRGEN_EN_P3_ALIGN 0 22931 #define PKTGEN1_ERR_INJ_EN1_CL91_80B_ERRGEN_EN_P3_BITS 1 22932 #define PKTGEN1_ERR_INJ_EN1_CL91_80B_ERRGEN_EN_P3_SHIFT 12 22933 22934 /* PktGen1 :: Err_inj_en1 :: cl91_80b_errgen_en_p2 [11:11] */ 22935 #define PKTGEN1_ERR_INJ_EN1_CL91_80B_ERRGEN_EN_P2_MASK 0x0800 22936 #define PKTGEN1_ERR_INJ_EN1_CL91_80B_ERRGEN_EN_P2_ALIGN 0 22937 #define PKTGEN1_ERR_INJ_EN1_CL91_80B_ERRGEN_EN_P2_BITS 1 22938 #define PKTGEN1_ERR_INJ_EN1_CL91_80B_ERRGEN_EN_P2_SHIFT 11 22939 22940 /* PktGen1 :: Err_inj_en1 :: cl91_80b_errgen_en_p1 [10:10] */ 22941 #define PKTGEN1_ERR_INJ_EN1_CL91_80B_ERRGEN_EN_P1_MASK 0x0400 22942 #define PKTGEN1_ERR_INJ_EN1_CL91_80B_ERRGEN_EN_P1_ALIGN 0 22943 #define PKTGEN1_ERR_INJ_EN1_CL91_80B_ERRGEN_EN_P1_BITS 1 22944 #define PKTGEN1_ERR_INJ_EN1_CL91_80B_ERRGEN_EN_P1_SHIFT 10 22945 22946 /* PktGen1 :: Err_inj_en1 :: cl91_80b_errgen_en_p0 [09:09] */ 22947 #define PKTGEN1_ERR_INJ_EN1_CL91_80B_ERRGEN_EN_P0_MASK 0x0200 22948 #define PKTGEN1_ERR_INJ_EN1_CL91_80B_ERRGEN_EN_P0_ALIGN 0 22949 #define PKTGEN1_ERR_INJ_EN1_CL91_80B_ERRGEN_EN_P0_BITS 1 22950 #define PKTGEN1_ERR_INJ_EN1_CL91_80B_ERRGEN_EN_P0_SHIFT 9 22951 22952 /* PktGen1 :: Err_inj_en1 :: cl91_40b_errgen_en_p3 [08:08] */ 22953 #define PKTGEN1_ERR_INJ_EN1_CL91_40B_ERRGEN_EN_P3_MASK 0x0100 22954 #define PKTGEN1_ERR_INJ_EN1_CL91_40B_ERRGEN_EN_P3_ALIGN 0 22955 #define PKTGEN1_ERR_INJ_EN1_CL91_40B_ERRGEN_EN_P3_BITS 1 22956 #define PKTGEN1_ERR_INJ_EN1_CL91_40B_ERRGEN_EN_P3_SHIFT 8 22957 22958 /* PktGen1 :: Err_inj_en1 :: cl91_40b_errgen_en_p2 [07:07] */ 22959 #define PKTGEN1_ERR_INJ_EN1_CL91_40B_ERRGEN_EN_P2_MASK 0x0080 22960 #define PKTGEN1_ERR_INJ_EN1_CL91_40B_ERRGEN_EN_P2_ALIGN 0 22961 #define PKTGEN1_ERR_INJ_EN1_CL91_40B_ERRGEN_EN_P2_BITS 1 22962 #define PKTGEN1_ERR_INJ_EN1_CL91_40B_ERRGEN_EN_P2_SHIFT 7 22963 22964 /* PktGen1 :: Err_inj_en1 :: cl91_40b_errgen_en_p1 [06:06] */ 22965 #define PKTGEN1_ERR_INJ_EN1_CL91_40B_ERRGEN_EN_P1_MASK 0x0040 22966 #define PKTGEN1_ERR_INJ_EN1_CL91_40B_ERRGEN_EN_P1_ALIGN 0 22967 #define PKTGEN1_ERR_INJ_EN1_CL91_40B_ERRGEN_EN_P1_BITS 1 22968 #define PKTGEN1_ERR_INJ_EN1_CL91_40B_ERRGEN_EN_P1_SHIFT 6 22969 22970 /* PktGen1 :: Err_inj_en1 :: cl91_40b_errgen_en_p0 [05:05] */ 22971 #define PKTGEN1_ERR_INJ_EN1_CL91_40B_ERRGEN_EN_P0_MASK 0x0020 22972 #define PKTGEN1_ERR_INJ_EN1_CL91_40B_ERRGEN_EN_P0_ALIGN 0 22973 #define PKTGEN1_ERR_INJ_EN1_CL91_40B_ERRGEN_EN_P0_BITS 1 22974 #define PKTGEN1_ERR_INJ_EN1_CL91_40B_ERRGEN_EN_P0_SHIFT 5 22975 22976 /* PktGen1 :: Err_inj_en1 :: errgen_en_ph3 [04:00] */ 22977 #define PKTGEN1_ERR_INJ_EN1_ERRGEN_EN_PH3_MASK 0x001f 22978 #define PKTGEN1_ERR_INJ_EN1_ERRGEN_EN_PH3_ALIGN 0 22979 #define PKTGEN1_ERR_INJ_EN1_ERRGEN_EN_PH3_BITS 5 22980 #define PKTGEN1_ERR_INJ_EN1_ERRGEN_EN_PH3_SHIFT 0 22981 22982 22983 /**************************************************************************** 22984 * TSC_WC4_TSC_USER1_CL82_Shared 22985 */ 22986 /**************************************************************************** 22987 * CL82_Shared :: cl82_am_timer 22988 */ 22989 /* CL82_Shared :: cl82_am_timer :: AM_timer_init_val [15:00] */ 22990 #define CL82_SHARED_CL82_AM_TIMER_AM_TIMER_INIT_VAL_MASK 0xffff 22991 #define CL82_SHARED_CL82_AM_TIMER_AM_TIMER_INIT_VAL_ALIGN 0 22992 #define CL82_SHARED_CL82_AM_TIMER_AM_TIMER_INIT_VAL_BITS 16 22993 #define CL82_SHARED_CL82_AM_TIMER_AM_TIMER_INIT_VAL_SHIFT 0 22994 22995 22996 /**************************************************************************** 22997 * TSC_WC4_TSC_USER1_CL82_AM_regs 22998 */ 22999 /**************************************************************************** 23000 * CL82_AM_regs :: lane_0_am_byte10 23001 */ 23002 /* CL82_AM_regs :: lane_0_am_byte10 :: LANE_0_AM_1_0 [15:00] */ 23003 #define CL82_AM_REGS_LANE_0_AM_BYTE10_LANE_0_AM_1_0_MASK 0xffff 23004 #define CL82_AM_REGS_LANE_0_AM_BYTE10_LANE_0_AM_1_0_ALIGN 0 23005 #define CL82_AM_REGS_LANE_0_AM_BYTE10_LANE_0_AM_1_0_BITS 16 23006 #define CL82_AM_REGS_LANE_0_AM_BYTE10_LANE_0_AM_1_0_SHIFT 0 23007 23008 23009 /**************************************************************************** 23010 * CL82_AM_regs :: lane_1_am_byte10 23011 */ 23012 /* CL82_AM_regs :: lane_1_am_byte10 :: LANE_1_AM_1_0 [15:00] */ 23013 #define CL82_AM_REGS_LANE_1_AM_BYTE10_LANE_1_AM_1_0_MASK 0xffff 23014 #define CL82_AM_REGS_LANE_1_AM_BYTE10_LANE_1_AM_1_0_ALIGN 0 23015 #define CL82_AM_REGS_LANE_1_AM_BYTE10_LANE_1_AM_1_0_BITS 16 23016 #define CL82_AM_REGS_LANE_1_AM_BYTE10_LANE_1_AM_1_0_SHIFT 0 23017 23018 23019 /**************************************************************************** 23020 * CL82_AM_regs :: lanes_1_0_am_byte2 23021 */ 23022 /* CL82_AM_regs :: lanes_1_0_am_byte2 :: LANE_1_AM_2 [15:08] */ 23023 #define CL82_AM_REGS_LANES_1_0_AM_BYTE2_LANE_1_AM_2_MASK 0xff00 23024 #define CL82_AM_REGS_LANES_1_0_AM_BYTE2_LANE_1_AM_2_ALIGN 0 23025 #define CL82_AM_REGS_LANES_1_0_AM_BYTE2_LANE_1_AM_2_BITS 8 23026 #define CL82_AM_REGS_LANES_1_0_AM_BYTE2_LANE_1_AM_2_SHIFT 8 23027 23028 /* CL82_AM_regs :: lanes_1_0_am_byte2 :: LANE_0_AM_2 [07:00] */ 23029 #define CL82_AM_REGS_LANES_1_0_AM_BYTE2_LANE_0_AM_2_MASK 0x00ff 23030 #define CL82_AM_REGS_LANES_1_0_AM_BYTE2_LANE_0_AM_2_ALIGN 0 23031 #define CL82_AM_REGS_LANES_1_0_AM_BYTE2_LANE_0_AM_2_BITS 8 23032 #define CL82_AM_REGS_LANES_1_0_AM_BYTE2_LANE_0_AM_2_SHIFT 0 23033 23034 23035 /**************************************************************************** 23036 * TSC_WC4_TSC_USER1_TX_X1_Control0 23037 */ 23038 /**************************************************************************** 23039 * TX_X1_Control0 :: tx_lane_swap 23040 */ 23041 /* TX_X1_Control0 :: tx_lane_swap :: reserved0 [15:08] */ 23042 #define TX_X1_CONTROL0_TX_LANE_SWAP_RESERVED0_MASK 0xff00 23043 #define TX_X1_CONTROL0_TX_LANE_SWAP_RESERVED0_ALIGN 0 23044 #define TX_X1_CONTROL0_TX_LANE_SWAP_RESERVED0_BITS 8 23045 #define TX_X1_CONTROL0_TX_LANE_SWAP_RESERVED0_SHIFT 8 23046 23047 /* TX_X1_Control0 :: tx_lane_swap :: logical3_to_phy_sel [07:06] */ 23048 #define TX_X1_CONTROL0_TX_LANE_SWAP_LOGICAL3_TO_PHY_SEL_MASK 0x00c0 23049 #define TX_X1_CONTROL0_TX_LANE_SWAP_LOGICAL3_TO_PHY_SEL_ALIGN 0 23050 #define TX_X1_CONTROL0_TX_LANE_SWAP_LOGICAL3_TO_PHY_SEL_BITS 2 23051 #define TX_X1_CONTROL0_TX_LANE_SWAP_LOGICAL3_TO_PHY_SEL_SHIFT 6 23052 23053 /* TX_X1_Control0 :: tx_lane_swap :: logical2_to_phy_sel [05:04] */ 23054 #define TX_X1_CONTROL0_TX_LANE_SWAP_LOGICAL2_TO_PHY_SEL_MASK 0x0030 23055 #define TX_X1_CONTROL0_TX_LANE_SWAP_LOGICAL2_TO_PHY_SEL_ALIGN 0 23056 #define TX_X1_CONTROL0_TX_LANE_SWAP_LOGICAL2_TO_PHY_SEL_BITS 2 23057 #define TX_X1_CONTROL0_TX_LANE_SWAP_LOGICAL2_TO_PHY_SEL_SHIFT 4 23058 23059 /* TX_X1_Control0 :: tx_lane_swap :: logical1_to_phy_sel [03:02] */ 23060 #define TX_X1_CONTROL0_TX_LANE_SWAP_LOGICAL1_TO_PHY_SEL_MASK 0x000c 23061 #define TX_X1_CONTROL0_TX_LANE_SWAP_LOGICAL1_TO_PHY_SEL_ALIGN 0 23062 #define TX_X1_CONTROL0_TX_LANE_SWAP_LOGICAL1_TO_PHY_SEL_BITS 2 23063 #define TX_X1_CONTROL0_TX_LANE_SWAP_LOGICAL1_TO_PHY_SEL_SHIFT 2 23064 23065 /* TX_X1_Control0 :: tx_lane_swap :: logical0_to_phy_sel [01:00] */ 23066 #define TX_X1_CONTROL0_TX_LANE_SWAP_LOGICAL0_TO_PHY_SEL_MASK 0x0003 23067 #define TX_X1_CONTROL0_TX_LANE_SWAP_LOGICAL0_TO_PHY_SEL_ALIGN 0 23068 #define TX_X1_CONTROL0_TX_LANE_SWAP_LOGICAL0_TO_PHY_SEL_BITS 2 23069 #define TX_X1_CONTROL0_TX_LANE_SWAP_LOGICAL0_TO_PHY_SEL_SHIFT 0 23070 23071 23072 /**************************************************************************** 23073 * TSC_WC4_TSC_USER1_RX_X1_Control0 23074 */ 23075 /**************************************************************************** 23076 * RX_X1_Control0 :: decode_control_1 23077 */ 23078 /* RX_X1_Control0 :: decode_control_1 :: SET_BER_WINDOW_512 [15:15] */ 23079 #define RX_X1_CONTROL0_DECODE_CONTROL_1_SET_BER_WINDOW_512_MASK 0x8000 23080 #define RX_X1_CONTROL0_DECODE_CONTROL_1_SET_BER_WINDOW_512_ALIGN 0 23081 #define RX_X1_CONTROL0_DECODE_CONTROL_1_SET_BER_WINDOW_512_BITS 1 23082 #define RX_X1_CONTROL0_DECODE_CONTROL_1_SET_BER_WINDOW_512_SHIFT 15 23083 23084 /* RX_X1_Control0 :: decode_control_1 :: CL82_BER_LIMIT [14:08] */ 23085 #define RX_X1_CONTROL0_DECODE_CONTROL_1_CL82_BER_LIMIT_MASK 0x7f00 23086 #define RX_X1_CONTROL0_DECODE_CONTROL_1_CL82_BER_LIMIT_ALIGN 0 23087 #define RX_X1_CONTROL0_DECODE_CONTROL_1_CL82_BER_LIMIT_BITS 7 23088 #define RX_X1_CONTROL0_DECODE_CONTROL_1_CL82_BER_LIMIT_SHIFT 8 23089 23090 /* RX_X1_Control0 :: decode_control_1 :: CL49_BER_LIMIT [07:02] */ 23091 #define RX_X1_CONTROL0_DECODE_CONTROL_1_CL49_BER_LIMIT_MASK 0x00fc 23092 #define RX_X1_CONTROL0_DECODE_CONTROL_1_CL49_BER_LIMIT_ALIGN 0 23093 #define RX_X1_CONTROL0_DECODE_CONTROL_1_CL49_BER_LIMIT_BITS 6 23094 #define RX_X1_CONTROL0_DECODE_CONTROL_1_CL49_BER_LIMIT_SHIFT 2 23095 23096 /* RX_X1_Control0 :: decode_control_1 :: reserved0 [01:00] */ 23097 #define RX_X1_CONTROL0_DECODE_CONTROL_1_RESERVED0_MASK 0x0003 23098 #define RX_X1_CONTROL0_DECODE_CONTROL_1_RESERVED0_ALIGN 0 23099 #define RX_X1_CONTROL0_DECODE_CONTROL_1_RESERVED0_BITS 2 23100 #define RX_X1_CONTROL0_DECODE_CONTROL_1_RESERVED0_SHIFT 0 23101 23102 23103 /**************************************************************************** 23104 * RX_X1_Control0 :: deskew_windows_0 23105 */ 23106 /* RX_X1_Control0 :: deskew_windows_0 :: reserved0 [15:11] */ 23107 #define RX_X1_CONTROL0_DESKEW_WINDOWS_0_RESERVED0_MASK 0xf800 23108 #define RX_X1_CONTROL0_DESKEW_WINDOWS_0_RESERVED0_ALIGN 0 23109 #define RX_X1_CONTROL0_DESKEW_WINDOWS_0_RESERVED0_BITS 5 23110 #define RX_X1_CONTROL0_DESKEW_WINDOWS_0_RESERVED0_SHIFT 11 23111 23112 /* RX_X1_Control0 :: deskew_windows_0 :: cl82_dswin_100g [10:06] */ 23113 #define RX_X1_CONTROL0_DESKEW_WINDOWS_0_CL82_DSWIN_100G_MASK 0x07c0 23114 #define RX_X1_CONTROL0_DESKEW_WINDOWS_0_CL82_DSWIN_100G_ALIGN 0 23115 #define RX_X1_CONTROL0_DESKEW_WINDOWS_0_CL82_DSWIN_100G_BITS 5 23116 #define RX_X1_CONTROL0_DESKEW_WINDOWS_0_CL82_DSWIN_100G_SHIFT 6 23117 23118 /* RX_X1_Control0 :: deskew_windows_0 :: cl82_dswin [05:00] */ 23119 #define RX_X1_CONTROL0_DESKEW_WINDOWS_0_CL82_DSWIN_MASK 0x003f 23120 #define RX_X1_CONTROL0_DESKEW_WINDOWS_0_CL82_DSWIN_ALIGN 0 23121 #define RX_X1_CONTROL0_DESKEW_WINDOWS_0_CL82_DSWIN_BITS 6 23122 #define RX_X1_CONTROL0_DESKEW_WINDOWS_0_CL82_DSWIN_SHIFT 0 23123 23124 23125 /**************************************************************************** 23126 * RX_X1_Control0 :: cl91_config 23127 */ 23128 /* RX_X1_Control0 :: cl91_config :: reserved0 [15:07] */ 23129 #define RX_X1_CONTROL0_CL91_CONFIG_RESERVED0_MASK 0xff80 23130 #define RX_X1_CONTROL0_CL91_CONFIG_RESERVED0_ALIGN 0 23131 #define RX_X1_CONTROL0_CL91_CONFIG_RESERVED0_BITS 9 23132 #define RX_X1_CONTROL0_CL91_CONFIG_RESERVED0_SHIFT 7 23133 23134 /* RX_X1_Control0 :: cl91_config :: cl91_fc_lock_corr_cw [06:06] */ 23135 #define RX_X1_CONTROL0_CL91_CONFIG_CL91_FC_LOCK_CORR_CW_MASK 0x0040 23136 #define RX_X1_CONTROL0_CL91_CONFIG_CL91_FC_LOCK_CORR_CW_ALIGN 0 23137 #define RX_X1_CONTROL0_CL91_CONFIG_CL91_FC_LOCK_CORR_CW_BITS 1 23138 #define RX_X1_CONTROL0_CL91_CONFIG_CL91_FC_LOCK_CORR_CW_SHIFT 6 23139 23140 /* RX_X1_Control0 :: cl91_config :: cl91_am_spacing_1024 [05:05] */ 23141 #define RX_X1_CONTROL0_CL91_CONFIG_CL91_AM_SPACING_1024_MASK 0x0020 23142 #define RX_X1_CONTROL0_CL91_CONFIG_CL91_AM_SPACING_1024_ALIGN 0 23143 #define RX_X1_CONTROL0_CL91_CONFIG_CL91_AM_SPACING_1024_BITS 1 23144 #define RX_X1_CONTROL0_CL91_CONFIG_CL91_AM_SPACING_1024_SHIFT 5 23145 23146 /* RX_X1_Control0 :: cl91_config :: fec_dbg_byp_corr [04:04] */ 23147 #define RX_X1_CONTROL0_CL91_CONFIG_FEC_DBG_BYP_CORR_MASK 0x0010 23148 #define RX_X1_CONTROL0_CL91_CONFIG_FEC_DBG_BYP_CORR_ALIGN 0 23149 #define RX_X1_CONTROL0_CL91_CONFIG_FEC_DBG_BYP_CORR_BITS 1 23150 #define RX_X1_CONTROL0_CL91_CONFIG_FEC_DBG_BYP_CORR_SHIFT 4 23151 23152 /* RX_X1_Control0 :: cl91_config :: fec_byp_ind_en [03:03] */ 23153 #define RX_X1_CONTROL0_CL91_CONFIG_FEC_BYP_IND_EN_MASK 0x0008 23154 #define RX_X1_CONTROL0_CL91_CONFIG_FEC_BYP_IND_EN_ALIGN 0 23155 #define RX_X1_CONTROL0_CL91_CONFIG_FEC_BYP_IND_EN_BITS 1 23156 #define RX_X1_CONTROL0_CL91_CONFIG_FEC_BYP_IND_EN_SHIFT 3 23157 23158 /* RX_X1_Control0 :: cl91_config :: fec_byp_corr_en [02:02] */ 23159 #define RX_X1_CONTROL0_CL91_CONFIG_FEC_BYP_CORR_EN_MASK 0x0004 23160 #define RX_X1_CONTROL0_CL91_CONFIG_FEC_BYP_CORR_EN_ALIGN 0 23161 #define RX_X1_CONTROL0_CL91_CONFIG_FEC_BYP_CORR_EN_BITS 1 23162 #define RX_X1_CONTROL0_CL91_CONFIG_FEC_BYP_CORR_EN_SHIFT 2 23163 23164 /* RX_X1_Control0 :: cl91_config :: set_symb_err_window_128 [01:01] */ 23165 #define RX_X1_CONTROL0_CL91_CONFIG_SET_SYMB_ERR_WINDOW_128_MASK 0x0002 23166 #define RX_X1_CONTROL0_CL91_CONFIG_SET_SYMB_ERR_WINDOW_128_ALIGN 0 23167 #define RX_X1_CONTROL0_CL91_CONFIG_SET_SYMB_ERR_WINDOW_128_BITS 1 23168 #define RX_X1_CONTROL0_CL91_CONFIG_SET_SYMB_ERR_WINDOW_128_SHIFT 1 23169 23170 /* RX_X1_Control0 :: cl91_config :: reserved1 [00:00] */ 23171 #define RX_X1_CONTROL0_CL91_CONFIG_RESERVED1_MASK 0x0001 23172 #define RX_X1_CONTROL0_CL91_CONFIG_RESERVED1_ALIGN 0 23173 #define RX_X1_CONTROL0_CL91_CONFIG_RESERVED1_BITS 1 23174 #define RX_X1_CONTROL0_CL91_CONFIG_RESERVED1_SHIFT 0 23175 23176 23177 /**************************************************************************** 23178 * RX_X1_Control0 :: deskew_windows_1 23179 */ 23180 /* RX_X1_Control0 :: deskew_windows_1 :: reserved0 [15:07] */ 23181 #define RX_X1_CONTROL0_DESKEW_WINDOWS_1_RESERVED0_MASK 0xff80 23182 #define RX_X1_CONTROL0_DESKEW_WINDOWS_1_RESERVED0_ALIGN 0 23183 #define RX_X1_CONTROL0_DESKEW_WINDOWS_1_RESERVED0_BITS 9 23184 #define RX_X1_CONTROL0_DESKEW_WINDOWS_1_RESERVED0_SHIFT 7 23185 23186 /* RX_X1_Control0 :: deskew_windows_1 :: cl82_dswin_cl91 [06:00] */ 23187 #define RX_X1_CONTROL0_DESKEW_WINDOWS_1_CL82_DSWIN_CL91_MASK 0x007f 23188 #define RX_X1_CONTROL0_DESKEW_WINDOWS_1_CL82_DSWIN_CL91_ALIGN 0 23189 #define RX_X1_CONTROL0_DESKEW_WINDOWS_1_CL82_DSWIN_CL91_BITS 7 23190 #define RX_X1_CONTROL0_DESKEW_WINDOWS_1_CL82_DSWIN_CL91_SHIFT 0 23191 23192 23193 /**************************************************************************** 23194 * RX_X1_Control0 :: rx_lane_swap 23195 */ 23196 /* RX_X1_Control0 :: rx_lane_swap :: reserved0 [15:08] */ 23197 #define RX_X1_CONTROL0_RX_LANE_SWAP_RESERVED0_MASK 0xff00 23198 #define RX_X1_CONTROL0_RX_LANE_SWAP_RESERVED0_ALIGN 0 23199 #define RX_X1_CONTROL0_RX_LANE_SWAP_RESERVED0_BITS 8 23200 #define RX_X1_CONTROL0_RX_LANE_SWAP_RESERVED0_SHIFT 8 23201 23202 /* RX_X1_Control0 :: rx_lane_swap :: logical3_to_phy_sel [07:06] */ 23203 #define RX_X1_CONTROL0_RX_LANE_SWAP_LOGICAL3_TO_PHY_SEL_MASK 0x00c0 23204 #define RX_X1_CONTROL0_RX_LANE_SWAP_LOGICAL3_TO_PHY_SEL_ALIGN 0 23205 #define RX_X1_CONTROL0_RX_LANE_SWAP_LOGICAL3_TO_PHY_SEL_BITS 2 23206 #define RX_X1_CONTROL0_RX_LANE_SWAP_LOGICAL3_TO_PHY_SEL_SHIFT 6 23207 23208 /* RX_X1_Control0 :: rx_lane_swap :: logical2_to_phy_sel [05:04] */ 23209 #define RX_X1_CONTROL0_RX_LANE_SWAP_LOGICAL2_TO_PHY_SEL_MASK 0x0030 23210 #define RX_X1_CONTROL0_RX_LANE_SWAP_LOGICAL2_TO_PHY_SEL_ALIGN 0 23211 #define RX_X1_CONTROL0_RX_LANE_SWAP_LOGICAL2_TO_PHY_SEL_BITS 2 23212 #define RX_X1_CONTROL0_RX_LANE_SWAP_LOGICAL2_TO_PHY_SEL_SHIFT 4 23213 23214 /* RX_X1_Control0 :: rx_lane_swap :: logical1_to_phy_sel [03:02] */ 23215 #define RX_X1_CONTROL0_RX_LANE_SWAP_LOGICAL1_TO_PHY_SEL_MASK 0x000c 23216 #define RX_X1_CONTROL0_RX_LANE_SWAP_LOGICAL1_TO_PHY_SEL_ALIGN 0 23217 #define RX_X1_CONTROL0_RX_LANE_SWAP_LOGICAL1_TO_PHY_SEL_BITS 2 23218 #define RX_X1_CONTROL0_RX_LANE_SWAP_LOGICAL1_TO_PHY_SEL_SHIFT 2 23219 23220 /* RX_X1_Control0 :: rx_lane_swap :: logical0_to_phy_sel [01:00] */ 23221 #define RX_X1_CONTROL0_RX_LANE_SWAP_LOGICAL0_TO_PHY_SEL_MASK 0x0003 23222 #define RX_X1_CONTROL0_RX_LANE_SWAP_LOGICAL0_TO_PHY_SEL_ALIGN 0 23223 #define RX_X1_CONTROL0_RX_LANE_SWAP_LOGICAL0_TO_PHY_SEL_BITS 2 23224 #define RX_X1_CONTROL0_RX_LANE_SWAP_LOGICAL0_TO_PHY_SEL_SHIFT 0 23225 23226 23227 /**************************************************************************** 23228 * RX_X1_Control0 :: srf_mem_ctrl 23229 */ 23230 /* RX_X1_Control0 :: srf_mem_ctrl :: reserved0 [15:12] */ 23231 #define RX_X1_CONTROL0_SRF_MEM_CTRL_RESERVED0_MASK 0xf000 23232 #define RX_X1_CONTROL0_SRF_MEM_CTRL_RESERVED0_ALIGN 0 23233 #define RX_X1_CONTROL0_SRF_MEM_CTRL_RESERVED0_BITS 4 23234 #define RX_X1_CONTROL0_SRF_MEM_CTRL_RESERVED0_SHIFT 12 23235 23236 /* RX_X1_Control0 :: srf_mem_ctrl :: srf_mem_TM [11:00] */ 23237 #define RX_X1_CONTROL0_SRF_MEM_CTRL_SRF_MEM_TM_MASK 0x0fff 23238 #define RX_X1_CONTROL0_SRF_MEM_CTRL_SRF_MEM_TM_ALIGN 0 23239 #define RX_X1_CONTROL0_SRF_MEM_CTRL_SRF_MEM_TM_BITS 12 23240 #define RX_X1_CONTROL0_SRF_MEM_CTRL_SRF_MEM_TM_SHIFT 0 23241 23242 23243 /**************************************************************************** 23244 * RX_X1_Control0 :: rf_mem_ctrl 23245 */ 23246 /* RX_X1_Control0 :: rf_mem_ctrl :: reserved0 [15:10] */ 23247 #define RX_X1_CONTROL0_RF_MEM_CTRL_RESERVED0_MASK 0xfc00 23248 #define RX_X1_CONTROL0_RF_MEM_CTRL_RESERVED0_ALIGN 0 23249 #define RX_X1_CONTROL0_RF_MEM_CTRL_RESERVED0_BITS 6 23250 #define RX_X1_CONTROL0_RF_MEM_CTRL_RESERVED0_SHIFT 10 23251 23252 /* RX_X1_Control0 :: rf_mem_ctrl :: rf_mem_TM [09:00] */ 23253 #define RX_X1_CONTROL0_RF_MEM_CTRL_RF_MEM_TM_MASK 0x03ff 23254 #define RX_X1_CONTROL0_RF_MEM_CTRL_RF_MEM_TM_ALIGN 0 23255 #define RX_X1_CONTROL0_RF_MEM_CTRL_RF_MEM_TM_BITS 10 23256 #define RX_X1_CONTROL0_RF_MEM_CTRL_RF_MEM_TM_SHIFT 0 23257 23258 23259 /**************************************************************************** 23260 * RX_X1_Control0 :: ber_25g_window 23261 */ 23262 /* RX_X1_Control0 :: ber_25g_window :: ber_window_25g_ieee_size [15:00] */ 23263 #define RX_X1_CONTROL0_BER_25G_WINDOW_BER_WINDOW_25G_IEEE_SIZE_MASK 0xffff 23264 #define RX_X1_CONTROL0_BER_25G_WINDOW_BER_WINDOW_25G_IEEE_SIZE_ALIGN 0 23265 #define RX_X1_CONTROL0_BER_25G_WINDOW_BER_WINDOW_25G_IEEE_SIZE_BITS 16 23266 #define RX_X1_CONTROL0_BER_25G_WINDOW_BER_WINDOW_25G_IEEE_SIZE_SHIFT 0 23267 23268 23269 /**************************************************************************** 23270 * RX_X1_Control0 :: ber_25g_sm 23271 */ 23272 /* RX_X1_Control0 :: ber_25g_sm :: reserved0 [15:07] */ 23273 #define RX_X1_CONTROL0_BER_25G_SM_RESERVED0_MASK 0xff80 23274 #define RX_X1_CONTROL0_BER_25G_SM_RESERVED0_ALIGN 0 23275 #define RX_X1_CONTROL0_BER_25G_SM_RESERVED0_BITS 9 23276 #define RX_X1_CONTROL0_BER_25G_SM_RESERVED0_SHIFT 7 23277 23278 /* RX_X1_Control0 :: ber_25g_sm :: ber_sm_25g_ieee [06:00] */ 23279 #define RX_X1_CONTROL0_BER_25G_SM_BER_SM_25G_IEEE_MASK 0x007f 23280 #define RX_X1_CONTROL0_BER_25G_SM_BER_SM_25G_IEEE_ALIGN 0 23281 #define RX_X1_CONTROL0_BER_25G_SM_BER_SM_25G_IEEE_BITS 7 23282 #define RX_X1_CONTROL0_BER_25G_SM_BER_SM_25G_IEEE_SHIFT 0 23283 23284 23285 /**************************************************************************** 23286 * TSC_WC4_TSC_USER1_RX_X1_ECC 23287 */ 23288 /**************************************************************************** 23289 * RX_X1_ECC :: status_fec_mem_0 23290 */ 23291 /* RX_X1_ECC :: status_fec_mem_0 :: two_bit_err_event_fec_0 [15:15] */ 23292 #define RX_X1_ECC_STATUS_FEC_MEM_0_TWO_BIT_ERR_EVENT_FEC_0_MASK 0x8000 23293 #define RX_X1_ECC_STATUS_FEC_MEM_0_TWO_BIT_ERR_EVENT_FEC_0_ALIGN 0 23294 #define RX_X1_ECC_STATUS_FEC_MEM_0_TWO_BIT_ERR_EVENT_FEC_0_BITS 1 23295 #define RX_X1_ECC_STATUS_FEC_MEM_0_TWO_BIT_ERR_EVENT_FEC_0_SHIFT 15 23296 23297 /* RX_X1_ECC :: status_fec_mem_0 :: one_bit_err_event_fec_0 [14:14] */ 23298 #define RX_X1_ECC_STATUS_FEC_MEM_0_ONE_BIT_ERR_EVENT_FEC_0_MASK 0x4000 23299 #define RX_X1_ECC_STATUS_FEC_MEM_0_ONE_BIT_ERR_EVENT_FEC_0_ALIGN 0 23300 #define RX_X1_ECC_STATUS_FEC_MEM_0_ONE_BIT_ERR_EVENT_FEC_0_BITS 1 23301 #define RX_X1_ECC_STATUS_FEC_MEM_0_ONE_BIT_ERR_EVENT_FEC_0_SHIFT 14 23302 23303 /* RX_X1_ECC :: status_fec_mem_0 :: err_event_address_fec_0 [13:00] */ 23304 #define RX_X1_ECC_STATUS_FEC_MEM_0_ERR_EVENT_ADDRESS_FEC_0_MASK 0x3fff 23305 #define RX_X1_ECC_STATUS_FEC_MEM_0_ERR_EVENT_ADDRESS_FEC_0_ALIGN 0 23306 #define RX_X1_ECC_STATUS_FEC_MEM_0_ERR_EVENT_ADDRESS_FEC_0_BITS 14 23307 #define RX_X1_ECC_STATUS_FEC_MEM_0_ERR_EVENT_ADDRESS_FEC_0_SHIFT 0 23308 23309 23310 /**************************************************************************** 23311 * RX_X1_ECC :: status_fec_mem_1 23312 */ 23313 /* RX_X1_ECC :: status_fec_mem_1 :: two_bit_err_event_fec_1 [15:15] */ 23314 #define RX_X1_ECC_STATUS_FEC_MEM_1_TWO_BIT_ERR_EVENT_FEC_1_MASK 0x8000 23315 #define RX_X1_ECC_STATUS_FEC_MEM_1_TWO_BIT_ERR_EVENT_FEC_1_ALIGN 0 23316 #define RX_X1_ECC_STATUS_FEC_MEM_1_TWO_BIT_ERR_EVENT_FEC_1_BITS 1 23317 #define RX_X1_ECC_STATUS_FEC_MEM_1_TWO_BIT_ERR_EVENT_FEC_1_SHIFT 15 23318 23319 /* RX_X1_ECC :: status_fec_mem_1 :: one_bit_err_event_fec_1 [14:14] */ 23320 #define RX_X1_ECC_STATUS_FEC_MEM_1_ONE_BIT_ERR_EVENT_FEC_1_MASK 0x4000 23321 #define RX_X1_ECC_STATUS_FEC_MEM_1_ONE_BIT_ERR_EVENT_FEC_1_ALIGN 0 23322 #define RX_X1_ECC_STATUS_FEC_MEM_1_ONE_BIT_ERR_EVENT_FEC_1_BITS 1 23323 #define RX_X1_ECC_STATUS_FEC_MEM_1_ONE_BIT_ERR_EVENT_FEC_1_SHIFT 14 23324 23325 /* RX_X1_ECC :: status_fec_mem_1 :: err_event_address_fec_1 [13:00] */ 23326 #define RX_X1_ECC_STATUS_FEC_MEM_1_ERR_EVENT_ADDRESS_FEC_1_MASK 0x3fff 23327 #define RX_X1_ECC_STATUS_FEC_MEM_1_ERR_EVENT_ADDRESS_FEC_1_ALIGN 0 23328 #define RX_X1_ECC_STATUS_FEC_MEM_1_ERR_EVENT_ADDRESS_FEC_1_BITS 14 23329 #define RX_X1_ECC_STATUS_FEC_MEM_1_ERR_EVENT_ADDRESS_FEC_1_SHIFT 0 23330 23331 23332 /**************************************************************************** 23333 * RX_X1_ECC :: status_fec_mem_2 23334 */ 23335 /* RX_X1_ECC :: status_fec_mem_2 :: two_bit_err_event_fec_2 [15:15] */ 23336 #define RX_X1_ECC_STATUS_FEC_MEM_2_TWO_BIT_ERR_EVENT_FEC_2_MASK 0x8000 23337 #define RX_X1_ECC_STATUS_FEC_MEM_2_TWO_BIT_ERR_EVENT_FEC_2_ALIGN 0 23338 #define RX_X1_ECC_STATUS_FEC_MEM_2_TWO_BIT_ERR_EVENT_FEC_2_BITS 1 23339 #define RX_X1_ECC_STATUS_FEC_MEM_2_TWO_BIT_ERR_EVENT_FEC_2_SHIFT 15 23340 23341 /* RX_X1_ECC :: status_fec_mem_2 :: one_bit_err_event_fec_2 [14:14] */ 23342 #define RX_X1_ECC_STATUS_FEC_MEM_2_ONE_BIT_ERR_EVENT_FEC_2_MASK 0x4000 23343 #define RX_X1_ECC_STATUS_FEC_MEM_2_ONE_BIT_ERR_EVENT_FEC_2_ALIGN 0 23344 #define RX_X1_ECC_STATUS_FEC_MEM_2_ONE_BIT_ERR_EVENT_FEC_2_BITS 1 23345 #define RX_X1_ECC_STATUS_FEC_MEM_2_ONE_BIT_ERR_EVENT_FEC_2_SHIFT 14 23346 23347 /* RX_X1_ECC :: status_fec_mem_2 :: err_event_address_fec_2 [13:00] */ 23348 #define RX_X1_ECC_STATUS_FEC_MEM_2_ERR_EVENT_ADDRESS_FEC_2_MASK 0x3fff 23349 #define RX_X1_ECC_STATUS_FEC_MEM_2_ERR_EVENT_ADDRESS_FEC_2_ALIGN 0 23350 #define RX_X1_ECC_STATUS_FEC_MEM_2_ERR_EVENT_ADDRESS_FEC_2_BITS 14 23351 #define RX_X1_ECC_STATUS_FEC_MEM_2_ERR_EVENT_ADDRESS_FEC_2_SHIFT 0 23352 23353 23354 /**************************************************************************** 23355 * RX_X1_ECC :: status_fec_mem_3 23356 */ 23357 /* RX_X1_ECC :: status_fec_mem_3 :: two_bit_err_event_fec_3 [15:15] */ 23358 #define RX_X1_ECC_STATUS_FEC_MEM_3_TWO_BIT_ERR_EVENT_FEC_3_MASK 0x8000 23359 #define RX_X1_ECC_STATUS_FEC_MEM_3_TWO_BIT_ERR_EVENT_FEC_3_ALIGN 0 23360 #define RX_X1_ECC_STATUS_FEC_MEM_3_TWO_BIT_ERR_EVENT_FEC_3_BITS 1 23361 #define RX_X1_ECC_STATUS_FEC_MEM_3_TWO_BIT_ERR_EVENT_FEC_3_SHIFT 15 23362 23363 /* RX_X1_ECC :: status_fec_mem_3 :: one_bit_err_event_fec_3 [14:14] */ 23364 #define RX_X1_ECC_STATUS_FEC_MEM_3_ONE_BIT_ERR_EVENT_FEC_3_MASK 0x4000 23365 #define RX_X1_ECC_STATUS_FEC_MEM_3_ONE_BIT_ERR_EVENT_FEC_3_ALIGN 0 23366 #define RX_X1_ECC_STATUS_FEC_MEM_3_ONE_BIT_ERR_EVENT_FEC_3_BITS 1 23367 #define RX_X1_ECC_STATUS_FEC_MEM_3_ONE_BIT_ERR_EVENT_FEC_3_SHIFT 14 23368 23369 /* RX_X1_ECC :: status_fec_mem_3 :: err_event_address_fec_3 [13:00] */ 23370 #define RX_X1_ECC_STATUS_FEC_MEM_3_ERR_EVENT_ADDRESS_FEC_3_MASK 0x3fff 23371 #define RX_X1_ECC_STATUS_FEC_MEM_3_ERR_EVENT_ADDRESS_FEC_3_ALIGN 0 23372 #define RX_X1_ECC_STATUS_FEC_MEM_3_ERR_EVENT_ADDRESS_FEC_3_BITS 14 23373 #define RX_X1_ECC_STATUS_FEC_MEM_3_ERR_EVENT_ADDRESS_FEC_3_SHIFT 0 23374 23375 23376 /**************************************************************************** 23377 * RX_X1_ECC :: interrupt_status_1bit 23378 */ 23379 /* RX_X1_ECC :: interrupt_status_1bit :: reserved0 [15:08] */ 23380 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_RESERVED0_MASK 0xff00 23381 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_RESERVED0_ALIGN 0 23382 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_RESERVED0_BITS 8 23383 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_RESERVED0_SHIFT 8 23384 23385 /* RX_X1_ECC :: interrupt_status_1bit :: cl91_fec_ram2_hi_1bit_int_status [07:07] */ 23386 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_CL91_FEC_RAM2_HI_1BIT_INT_STATUS_MASK 0x0080 23387 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_CL91_FEC_RAM2_HI_1BIT_INT_STATUS_ALIGN 0 23388 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_CL91_FEC_RAM2_HI_1BIT_INT_STATUS_BITS 1 23389 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_CL91_FEC_RAM2_HI_1BIT_INT_STATUS_SHIFT 7 23390 23391 /* RX_X1_ECC :: interrupt_status_1bit :: cl91_fec_ram2_lo_1bit_int_status [06:06] */ 23392 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_CL91_FEC_RAM2_LO_1BIT_INT_STATUS_MASK 0x0040 23393 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_CL91_FEC_RAM2_LO_1BIT_INT_STATUS_ALIGN 0 23394 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_CL91_FEC_RAM2_LO_1BIT_INT_STATUS_BITS 1 23395 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_CL91_FEC_RAM2_LO_1BIT_INT_STATUS_SHIFT 6 23396 23397 /* RX_X1_ECC :: interrupt_status_1bit :: cl91_fec_ram1_hi_1bit_int_status [05:05] */ 23398 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_CL91_FEC_RAM1_HI_1BIT_INT_STATUS_MASK 0x0020 23399 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_CL91_FEC_RAM1_HI_1BIT_INT_STATUS_ALIGN 0 23400 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_CL91_FEC_RAM1_HI_1BIT_INT_STATUS_BITS 1 23401 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_CL91_FEC_RAM1_HI_1BIT_INT_STATUS_SHIFT 5 23402 23403 /* RX_X1_ECC :: interrupt_status_1bit :: cl91_fec_ram1_lo_1bit_int_status [04:04] */ 23404 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_CL91_FEC_RAM1_LO_1BIT_INT_STATUS_MASK 0x0010 23405 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_CL91_FEC_RAM1_LO_1BIT_INT_STATUS_ALIGN 0 23406 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_CL91_FEC_RAM1_LO_1BIT_INT_STATUS_BITS 1 23407 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_CL91_FEC_RAM1_LO_1BIT_INT_STATUS_SHIFT 4 23408 23409 /* RX_X1_ECC :: interrupt_status_1bit :: fec_mem_3_1bit_int_status [03:03] */ 23410 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_FEC_MEM_3_1BIT_INT_STATUS_MASK 0x0008 23411 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_FEC_MEM_3_1BIT_INT_STATUS_ALIGN 0 23412 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_FEC_MEM_3_1BIT_INT_STATUS_BITS 1 23413 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_FEC_MEM_3_1BIT_INT_STATUS_SHIFT 3 23414 23415 /* RX_X1_ECC :: interrupt_status_1bit :: fec_mem_2_1bit_int_status [02:02] */ 23416 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_FEC_MEM_2_1BIT_INT_STATUS_MASK 0x0004 23417 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_FEC_MEM_2_1BIT_INT_STATUS_ALIGN 0 23418 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_FEC_MEM_2_1BIT_INT_STATUS_BITS 1 23419 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_FEC_MEM_2_1BIT_INT_STATUS_SHIFT 2 23420 23421 /* RX_X1_ECC :: interrupt_status_1bit :: fec_mem_1_1bit_int_status [01:01] */ 23422 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_FEC_MEM_1_1BIT_INT_STATUS_MASK 0x0002 23423 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_FEC_MEM_1_1BIT_INT_STATUS_ALIGN 0 23424 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_FEC_MEM_1_1BIT_INT_STATUS_BITS 1 23425 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_FEC_MEM_1_1BIT_INT_STATUS_SHIFT 1 23426 23427 /* RX_X1_ECC :: interrupt_status_1bit :: fec_mem_0_1bit_int_status [00:00] */ 23428 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_FEC_MEM_0_1BIT_INT_STATUS_MASK 0x0001 23429 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_FEC_MEM_0_1BIT_INT_STATUS_ALIGN 0 23430 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_FEC_MEM_0_1BIT_INT_STATUS_BITS 1 23431 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_FEC_MEM_0_1BIT_INT_STATUS_SHIFT 0 23432 23433 23434 /**************************************************************************** 23435 * RX_X1_ECC :: interrupt_status_2bit 23436 */ 23437 /* RX_X1_ECC :: interrupt_status_2bit :: reserved0 [15:08] */ 23438 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_RESERVED0_MASK 0xff00 23439 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_RESERVED0_ALIGN 0 23440 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_RESERVED0_BITS 8 23441 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_RESERVED0_SHIFT 8 23442 23443 /* RX_X1_ECC :: interrupt_status_2bit :: cl91_fec_ram2_hi_2bit_int_status [07:07] */ 23444 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_CL91_FEC_RAM2_HI_2BIT_INT_STATUS_MASK 0x0080 23445 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_CL91_FEC_RAM2_HI_2BIT_INT_STATUS_ALIGN 0 23446 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_CL91_FEC_RAM2_HI_2BIT_INT_STATUS_BITS 1 23447 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_CL91_FEC_RAM2_HI_2BIT_INT_STATUS_SHIFT 7 23448 23449 /* RX_X1_ECC :: interrupt_status_2bit :: cl91_fec_ram2_lo_2bit_int_status [06:06] */ 23450 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_CL91_FEC_RAM2_LO_2BIT_INT_STATUS_MASK 0x0040 23451 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_CL91_FEC_RAM2_LO_2BIT_INT_STATUS_ALIGN 0 23452 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_CL91_FEC_RAM2_LO_2BIT_INT_STATUS_BITS 1 23453 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_CL91_FEC_RAM2_LO_2BIT_INT_STATUS_SHIFT 6 23454 23455 /* RX_X1_ECC :: interrupt_status_2bit :: cl91_fec_ram1_hi_2bit_int_status [05:05] */ 23456 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_CL91_FEC_RAM1_HI_2BIT_INT_STATUS_MASK 0x0020 23457 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_CL91_FEC_RAM1_HI_2BIT_INT_STATUS_ALIGN 0 23458 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_CL91_FEC_RAM1_HI_2BIT_INT_STATUS_BITS 1 23459 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_CL91_FEC_RAM1_HI_2BIT_INT_STATUS_SHIFT 5 23460 23461 /* RX_X1_ECC :: interrupt_status_2bit :: cl91_fec_ram1_lo_2bit_int_status [04:04] */ 23462 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_CL91_FEC_RAM1_LO_2BIT_INT_STATUS_MASK 0x0010 23463 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_CL91_FEC_RAM1_LO_2BIT_INT_STATUS_ALIGN 0 23464 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_CL91_FEC_RAM1_LO_2BIT_INT_STATUS_BITS 1 23465 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_CL91_FEC_RAM1_LO_2BIT_INT_STATUS_SHIFT 4 23466 23467 /* RX_X1_ECC :: interrupt_status_2bit :: fec_mem_3_2bit_int_status [03:03] */ 23468 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_FEC_MEM_3_2BIT_INT_STATUS_MASK 0x0008 23469 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_FEC_MEM_3_2BIT_INT_STATUS_ALIGN 0 23470 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_FEC_MEM_3_2BIT_INT_STATUS_BITS 1 23471 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_FEC_MEM_3_2BIT_INT_STATUS_SHIFT 3 23472 23473 /* RX_X1_ECC :: interrupt_status_2bit :: fec_mem_2_2bit_int_status [02:02] */ 23474 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_FEC_MEM_2_2BIT_INT_STATUS_MASK 0x0004 23475 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_FEC_MEM_2_2BIT_INT_STATUS_ALIGN 0 23476 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_FEC_MEM_2_2BIT_INT_STATUS_BITS 1 23477 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_FEC_MEM_2_2BIT_INT_STATUS_SHIFT 2 23478 23479 /* RX_X1_ECC :: interrupt_status_2bit :: fec_mem_1_2bit_int_status [01:01] */ 23480 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_FEC_MEM_1_2BIT_INT_STATUS_MASK 0x0002 23481 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_FEC_MEM_1_2BIT_INT_STATUS_ALIGN 0 23482 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_FEC_MEM_1_2BIT_INT_STATUS_BITS 1 23483 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_FEC_MEM_1_2BIT_INT_STATUS_SHIFT 1 23484 23485 /* RX_X1_ECC :: interrupt_status_2bit :: fec_mem_0_2bit_int_status [00:00] */ 23486 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_FEC_MEM_0_2BIT_INT_STATUS_MASK 0x0001 23487 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_FEC_MEM_0_2BIT_INT_STATUS_ALIGN 0 23488 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_FEC_MEM_0_2BIT_INT_STATUS_BITS 1 23489 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_FEC_MEM_0_2BIT_INT_STATUS_SHIFT 0 23490 23491 23492 /**************************************************************************** 23493 * RX_X1_ECC :: interrupt_en_1bit 23494 */ 23495 /* RX_X1_ECC :: interrupt_en_1bit :: reserved0 [15:08] */ 23496 #define RX_X1_ECC_INTERRUPT_EN_1BIT_RESERVED0_MASK 0xff00 23497 #define RX_X1_ECC_INTERRUPT_EN_1BIT_RESERVED0_ALIGN 0 23498 #define RX_X1_ECC_INTERRUPT_EN_1BIT_RESERVED0_BITS 8 23499 #define RX_X1_ECC_INTERRUPT_EN_1BIT_RESERVED0_SHIFT 8 23500 23501 /* RX_X1_ECC :: interrupt_en_1bit :: cl91_fec_ram2_hi_1bit_int_en [07:07] */ 23502 #define RX_X1_ECC_INTERRUPT_EN_1BIT_CL91_FEC_RAM2_HI_1BIT_INT_EN_MASK 0x0080 23503 #define RX_X1_ECC_INTERRUPT_EN_1BIT_CL91_FEC_RAM2_HI_1BIT_INT_EN_ALIGN 0 23504 #define RX_X1_ECC_INTERRUPT_EN_1BIT_CL91_FEC_RAM2_HI_1BIT_INT_EN_BITS 1 23505 #define RX_X1_ECC_INTERRUPT_EN_1BIT_CL91_FEC_RAM2_HI_1BIT_INT_EN_SHIFT 7 23506 23507 /* RX_X1_ECC :: interrupt_en_1bit :: cl91_fec_ram2_lo_1bit_int_en [06:06] */ 23508 #define RX_X1_ECC_INTERRUPT_EN_1BIT_CL91_FEC_RAM2_LO_1BIT_INT_EN_MASK 0x0040 23509 #define RX_X1_ECC_INTERRUPT_EN_1BIT_CL91_FEC_RAM2_LO_1BIT_INT_EN_ALIGN 0 23510 #define RX_X1_ECC_INTERRUPT_EN_1BIT_CL91_FEC_RAM2_LO_1BIT_INT_EN_BITS 1 23511 #define RX_X1_ECC_INTERRUPT_EN_1BIT_CL91_FEC_RAM2_LO_1BIT_INT_EN_SHIFT 6 23512 23513 /* RX_X1_ECC :: interrupt_en_1bit :: cl91_fec_ram1_hi_1bit_int_en [05:05] */ 23514 #define RX_X1_ECC_INTERRUPT_EN_1BIT_CL91_FEC_RAM1_HI_1BIT_INT_EN_MASK 0x0020 23515 #define RX_X1_ECC_INTERRUPT_EN_1BIT_CL91_FEC_RAM1_HI_1BIT_INT_EN_ALIGN 0 23516 #define RX_X1_ECC_INTERRUPT_EN_1BIT_CL91_FEC_RAM1_HI_1BIT_INT_EN_BITS 1 23517 #define RX_X1_ECC_INTERRUPT_EN_1BIT_CL91_FEC_RAM1_HI_1BIT_INT_EN_SHIFT 5 23518 23519 /* RX_X1_ECC :: interrupt_en_1bit :: cl91_fec_ram1_lo_1bit_int_en [04:04] */ 23520 #define RX_X1_ECC_INTERRUPT_EN_1BIT_CL91_FEC_RAM1_LO_1BIT_INT_EN_MASK 0x0010 23521 #define RX_X1_ECC_INTERRUPT_EN_1BIT_CL91_FEC_RAM1_LO_1BIT_INT_EN_ALIGN 0 23522 #define RX_X1_ECC_INTERRUPT_EN_1BIT_CL91_FEC_RAM1_LO_1BIT_INT_EN_BITS 1 23523 #define RX_X1_ECC_INTERRUPT_EN_1BIT_CL91_FEC_RAM1_LO_1BIT_INT_EN_SHIFT 4 23524 23525 /* RX_X1_ECC :: interrupt_en_1bit :: fec_mem_3_1bit_int_en [03:03] */ 23526 #define RX_X1_ECC_INTERRUPT_EN_1BIT_FEC_MEM_3_1BIT_INT_EN_MASK 0x0008 23527 #define RX_X1_ECC_INTERRUPT_EN_1BIT_FEC_MEM_3_1BIT_INT_EN_ALIGN 0 23528 #define RX_X1_ECC_INTERRUPT_EN_1BIT_FEC_MEM_3_1BIT_INT_EN_BITS 1 23529 #define RX_X1_ECC_INTERRUPT_EN_1BIT_FEC_MEM_3_1BIT_INT_EN_SHIFT 3 23530 23531 /* RX_X1_ECC :: interrupt_en_1bit :: fec_mem_2_1bit_int_en [02:02] */ 23532 #define RX_X1_ECC_INTERRUPT_EN_1BIT_FEC_MEM_2_1BIT_INT_EN_MASK 0x0004 23533 #define RX_X1_ECC_INTERRUPT_EN_1BIT_FEC_MEM_2_1BIT_INT_EN_ALIGN 0 23534 #define RX_X1_ECC_INTERRUPT_EN_1BIT_FEC_MEM_2_1BIT_INT_EN_BITS 1 23535 #define RX_X1_ECC_INTERRUPT_EN_1BIT_FEC_MEM_2_1BIT_INT_EN_SHIFT 2 23536 23537 /* RX_X1_ECC :: interrupt_en_1bit :: fec_mem_1_1bit_int_en [01:01] */ 23538 #define RX_X1_ECC_INTERRUPT_EN_1BIT_FEC_MEM_1_1BIT_INT_EN_MASK 0x0002 23539 #define RX_X1_ECC_INTERRUPT_EN_1BIT_FEC_MEM_1_1BIT_INT_EN_ALIGN 0 23540 #define RX_X1_ECC_INTERRUPT_EN_1BIT_FEC_MEM_1_1BIT_INT_EN_BITS 1 23541 #define RX_X1_ECC_INTERRUPT_EN_1BIT_FEC_MEM_1_1BIT_INT_EN_SHIFT 1 23542 23543 /* RX_X1_ECC :: interrupt_en_1bit :: fec_mem_0_1bit_int_en [00:00] */ 23544 #define RX_X1_ECC_INTERRUPT_EN_1BIT_FEC_MEM_0_1BIT_INT_EN_MASK 0x0001 23545 #define RX_X1_ECC_INTERRUPT_EN_1BIT_FEC_MEM_0_1BIT_INT_EN_ALIGN 0 23546 #define RX_X1_ECC_INTERRUPT_EN_1BIT_FEC_MEM_0_1BIT_INT_EN_BITS 1 23547 #define RX_X1_ECC_INTERRUPT_EN_1BIT_FEC_MEM_0_1BIT_INT_EN_SHIFT 0 23548 23549 23550 /**************************************************************************** 23551 * RX_X1_ECC :: interrupt_en_2bit 23552 */ 23553 /* RX_X1_ECC :: interrupt_en_2bit :: reserved0 [15:08] */ 23554 #define RX_X1_ECC_INTERRUPT_EN_2BIT_RESERVED0_MASK 0xff00 23555 #define RX_X1_ECC_INTERRUPT_EN_2BIT_RESERVED0_ALIGN 0 23556 #define RX_X1_ECC_INTERRUPT_EN_2BIT_RESERVED0_BITS 8 23557 #define RX_X1_ECC_INTERRUPT_EN_2BIT_RESERVED0_SHIFT 8 23558 23559 /* RX_X1_ECC :: interrupt_en_2bit :: cl91_fec_ram2_hi_2bit_int_en [07:07] */ 23560 #define RX_X1_ECC_INTERRUPT_EN_2BIT_CL91_FEC_RAM2_HI_2BIT_INT_EN_MASK 0x0080 23561 #define RX_X1_ECC_INTERRUPT_EN_2BIT_CL91_FEC_RAM2_HI_2BIT_INT_EN_ALIGN 0 23562 #define RX_X1_ECC_INTERRUPT_EN_2BIT_CL91_FEC_RAM2_HI_2BIT_INT_EN_BITS 1 23563 #define RX_X1_ECC_INTERRUPT_EN_2BIT_CL91_FEC_RAM2_HI_2BIT_INT_EN_SHIFT 7 23564 23565 /* RX_X1_ECC :: interrupt_en_2bit :: cl91_fec_ram2_lo_2bit_int_en [06:06] */ 23566 #define RX_X1_ECC_INTERRUPT_EN_2BIT_CL91_FEC_RAM2_LO_2BIT_INT_EN_MASK 0x0040 23567 #define RX_X1_ECC_INTERRUPT_EN_2BIT_CL91_FEC_RAM2_LO_2BIT_INT_EN_ALIGN 0 23568 #define RX_X1_ECC_INTERRUPT_EN_2BIT_CL91_FEC_RAM2_LO_2BIT_INT_EN_BITS 1 23569 #define RX_X1_ECC_INTERRUPT_EN_2BIT_CL91_FEC_RAM2_LO_2BIT_INT_EN_SHIFT 6 23570 23571 /* RX_X1_ECC :: interrupt_en_2bit :: cl91_fec_ram1_hi_2bit_int_en [05:05] */ 23572 #define RX_X1_ECC_INTERRUPT_EN_2BIT_CL91_FEC_RAM1_HI_2BIT_INT_EN_MASK 0x0020 23573 #define RX_X1_ECC_INTERRUPT_EN_2BIT_CL91_FEC_RAM1_HI_2BIT_INT_EN_ALIGN 0 23574 #define RX_X1_ECC_INTERRUPT_EN_2BIT_CL91_FEC_RAM1_HI_2BIT_INT_EN_BITS 1 23575 #define RX_X1_ECC_INTERRUPT_EN_2BIT_CL91_FEC_RAM1_HI_2BIT_INT_EN_SHIFT 5 23576 23577 /* RX_X1_ECC :: interrupt_en_2bit :: cl91_fec_ram1_lo_2bit_int_en [04:04] */ 23578 #define RX_X1_ECC_INTERRUPT_EN_2BIT_CL91_FEC_RAM1_LO_2BIT_INT_EN_MASK 0x0010 23579 #define RX_X1_ECC_INTERRUPT_EN_2BIT_CL91_FEC_RAM1_LO_2BIT_INT_EN_ALIGN 0 23580 #define RX_X1_ECC_INTERRUPT_EN_2BIT_CL91_FEC_RAM1_LO_2BIT_INT_EN_BITS 1 23581 #define RX_X1_ECC_INTERRUPT_EN_2BIT_CL91_FEC_RAM1_LO_2BIT_INT_EN_SHIFT 4 23582 23583 /* RX_X1_ECC :: interrupt_en_2bit :: fec_mem_3_2bit_int_en [03:03] */ 23584 #define RX_X1_ECC_INTERRUPT_EN_2BIT_FEC_MEM_3_2BIT_INT_EN_MASK 0x0008 23585 #define RX_X1_ECC_INTERRUPT_EN_2BIT_FEC_MEM_3_2BIT_INT_EN_ALIGN 0 23586 #define RX_X1_ECC_INTERRUPT_EN_2BIT_FEC_MEM_3_2BIT_INT_EN_BITS 1 23587 #define RX_X1_ECC_INTERRUPT_EN_2BIT_FEC_MEM_3_2BIT_INT_EN_SHIFT 3 23588 23589 /* RX_X1_ECC :: interrupt_en_2bit :: fec_mem_2_2bit_int_en [02:02] */ 23590 #define RX_X1_ECC_INTERRUPT_EN_2BIT_FEC_MEM_2_2BIT_INT_EN_MASK 0x0004 23591 #define RX_X1_ECC_INTERRUPT_EN_2BIT_FEC_MEM_2_2BIT_INT_EN_ALIGN 0 23592 #define RX_X1_ECC_INTERRUPT_EN_2BIT_FEC_MEM_2_2BIT_INT_EN_BITS 1 23593 #define RX_X1_ECC_INTERRUPT_EN_2BIT_FEC_MEM_2_2BIT_INT_EN_SHIFT 2 23594 23595 /* RX_X1_ECC :: interrupt_en_2bit :: fec_mem_1_2bit_int_en [01:01] */ 23596 #define RX_X1_ECC_INTERRUPT_EN_2BIT_FEC_MEM_1_2BIT_INT_EN_MASK 0x0002 23597 #define RX_X1_ECC_INTERRUPT_EN_2BIT_FEC_MEM_1_2BIT_INT_EN_ALIGN 0 23598 #define RX_X1_ECC_INTERRUPT_EN_2BIT_FEC_MEM_1_2BIT_INT_EN_BITS 1 23599 #define RX_X1_ECC_INTERRUPT_EN_2BIT_FEC_MEM_1_2BIT_INT_EN_SHIFT 1 23600 23601 /* RX_X1_ECC :: interrupt_en_2bit :: fec_mem_0_2bit_int_en [00:00] */ 23602 #define RX_X1_ECC_INTERRUPT_EN_2BIT_FEC_MEM_0_2BIT_INT_EN_MASK 0x0001 23603 #define RX_X1_ECC_INTERRUPT_EN_2BIT_FEC_MEM_0_2BIT_INT_EN_ALIGN 0 23604 #define RX_X1_ECC_INTERRUPT_EN_2BIT_FEC_MEM_0_2BIT_INT_EN_BITS 1 23605 #define RX_X1_ECC_INTERRUPT_EN_2BIT_FEC_MEM_0_2BIT_INT_EN_SHIFT 0 23606 23607 23608 /**************************************************************************** 23609 * RX_X1_ECC :: disable_ecc_mem 23610 */ 23611 /* RX_X1_ECC :: disable_ecc_mem :: reserved0 [15:08] */ 23612 #define RX_X1_ECC_DISABLE_ECC_MEM_RESERVED0_MASK 0xff00 23613 #define RX_X1_ECC_DISABLE_ECC_MEM_RESERVED0_ALIGN 0 23614 #define RX_X1_ECC_DISABLE_ECC_MEM_RESERVED0_BITS 8 23615 #define RX_X1_ECC_DISABLE_ECC_MEM_RESERVED0_SHIFT 8 23616 23617 /* RX_X1_ECC :: disable_ecc_mem :: disable_ecc_cl91_fec_ram2_hi [07:07] */ 23618 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_CL91_FEC_RAM2_HI_MASK 0x0080 23619 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_CL91_FEC_RAM2_HI_ALIGN 0 23620 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_CL91_FEC_RAM2_HI_BITS 1 23621 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_CL91_FEC_RAM2_HI_SHIFT 7 23622 23623 /* RX_X1_ECC :: disable_ecc_mem :: disable_ecc_cl91_fec_ram2_lo [06:06] */ 23624 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_CL91_FEC_RAM2_LO_MASK 0x0040 23625 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_CL91_FEC_RAM2_LO_ALIGN 0 23626 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_CL91_FEC_RAM2_LO_BITS 1 23627 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_CL91_FEC_RAM2_LO_SHIFT 6 23628 23629 /* RX_X1_ECC :: disable_ecc_mem :: disable_ecc_cl91_fec_ram1_hi [05:05] */ 23630 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_CL91_FEC_RAM1_HI_MASK 0x0020 23631 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_CL91_FEC_RAM1_HI_ALIGN 0 23632 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_CL91_FEC_RAM1_HI_BITS 1 23633 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_CL91_FEC_RAM1_HI_SHIFT 5 23634 23635 /* RX_X1_ECC :: disable_ecc_mem :: disable_ecc_cl91_fec_ram1_lo [04:04] */ 23636 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_CL91_FEC_RAM1_LO_MASK 0x0010 23637 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_CL91_FEC_RAM1_LO_ALIGN 0 23638 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_CL91_FEC_RAM1_LO_BITS 1 23639 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_CL91_FEC_RAM1_LO_SHIFT 4 23640 23641 /* RX_X1_ECC :: disable_ecc_mem :: disable_ecc_fec_mem_3 [03:03] */ 23642 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_FEC_MEM_3_MASK 0x0008 23643 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_FEC_MEM_3_ALIGN 0 23644 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_FEC_MEM_3_BITS 1 23645 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_FEC_MEM_3_SHIFT 3 23646 23647 /* RX_X1_ECC :: disable_ecc_mem :: disable_ecc_fec_mem_2 [02:02] */ 23648 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_FEC_MEM_2_MASK 0x0004 23649 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_FEC_MEM_2_ALIGN 0 23650 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_FEC_MEM_2_BITS 1 23651 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_FEC_MEM_2_SHIFT 2 23652 23653 /* RX_X1_ECC :: disable_ecc_mem :: disable_ecc_fec_mem_1 [01:01] */ 23654 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_FEC_MEM_1_MASK 0x0002 23655 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_FEC_MEM_1_ALIGN 0 23656 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_FEC_MEM_1_BITS 1 23657 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_FEC_MEM_1_SHIFT 1 23658 23659 /* RX_X1_ECC :: disable_ecc_mem :: disable_ecc_fec_mem_0 [00:00] */ 23660 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_FEC_MEM_0_MASK 0x0001 23661 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_FEC_MEM_0_ALIGN 0 23662 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_FEC_MEM_0_BITS 1 23663 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_FEC_MEM_0_SHIFT 0 23664 23665 23666 /**************************************************************************** 23667 * RX_X1_ECC :: corrupt_0 23668 */ 23669 /* RX_X1_ECC :: corrupt_0 :: corrupt_ecc_cl91_fec_ram2_hi [15:14] */ 23670 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_CL91_FEC_RAM2_HI_MASK 0xc000 23671 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_CL91_FEC_RAM2_HI_ALIGN 0 23672 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_CL91_FEC_RAM2_HI_BITS 2 23673 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_CL91_FEC_RAM2_HI_SHIFT 14 23674 23675 /* RX_X1_ECC :: corrupt_0 :: corrupt_ecc_cl91_fec_ram2_lo [13:12] */ 23676 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_CL91_FEC_RAM2_LO_MASK 0x3000 23677 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_CL91_FEC_RAM2_LO_ALIGN 0 23678 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_CL91_FEC_RAM2_LO_BITS 2 23679 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_CL91_FEC_RAM2_LO_SHIFT 12 23680 23681 /* RX_X1_ECC :: corrupt_0 :: corrupt_ecc_cl91_fec_ram1_hi [11:10] */ 23682 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_CL91_FEC_RAM1_HI_MASK 0x0c00 23683 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_CL91_FEC_RAM1_HI_ALIGN 0 23684 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_CL91_FEC_RAM1_HI_BITS 2 23685 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_CL91_FEC_RAM1_HI_SHIFT 10 23686 23687 /* RX_X1_ECC :: corrupt_0 :: corrupt_ecc_cl91_fec_ram1_lo [09:08] */ 23688 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_CL91_FEC_RAM1_LO_MASK 0x0300 23689 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_CL91_FEC_RAM1_LO_ALIGN 0 23690 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_CL91_FEC_RAM1_LO_BITS 2 23691 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_CL91_FEC_RAM1_LO_SHIFT 8 23692 23693 /* RX_X1_ECC :: corrupt_0 :: corrupt_ecc_fec_mem_3 [07:06] */ 23694 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_FEC_MEM_3_MASK 0x00c0 23695 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_FEC_MEM_3_ALIGN 0 23696 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_FEC_MEM_3_BITS 2 23697 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_FEC_MEM_3_SHIFT 6 23698 23699 /* RX_X1_ECC :: corrupt_0 :: corrupt_ecc_fec_mem_2 [05:04] */ 23700 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_FEC_MEM_2_MASK 0x0030 23701 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_FEC_MEM_2_ALIGN 0 23702 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_FEC_MEM_2_BITS 2 23703 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_FEC_MEM_2_SHIFT 4 23704 23705 /* RX_X1_ECC :: corrupt_0 :: corrupt_ecc_fec_mem_1 [03:02] */ 23706 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_FEC_MEM_1_MASK 0x000c 23707 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_FEC_MEM_1_ALIGN 0 23708 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_FEC_MEM_1_BITS 2 23709 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_FEC_MEM_1_SHIFT 2 23710 23711 /* RX_X1_ECC :: corrupt_0 :: corrupt_ecc_fec_mem_0 [01:00] */ 23712 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_FEC_MEM_0_MASK 0x0003 23713 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_FEC_MEM_0_ALIGN 0 23714 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_FEC_MEM_0_BITS 2 23715 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_FEC_MEM_0_SHIFT 0 23716 23717 23718 /**************************************************************************** 23719 * TSC_WC4_TSC_USER1_AN_X1_CONTROL 23720 */ 23721 /**************************************************************************** 23722 * AN_X1_CONTROL :: oui_upper 23723 */ 23724 /* AN_X1_CONTROL :: oui_upper :: reserved0 [15:08] */ 23725 #define AN_X1_CONTROL_OUI_UPPER_RESERVED0_MASK 0xff00 23726 #define AN_X1_CONTROL_OUI_UPPER_RESERVED0_ALIGN 0 23727 #define AN_X1_CONTROL_OUI_UPPER_RESERVED0_BITS 8 23728 #define AN_X1_CONTROL_OUI_UPPER_RESERVED0_SHIFT 8 23729 23730 /* AN_X1_CONTROL :: oui_upper :: oui_upper_data [07:00] */ 23731 #define AN_X1_CONTROL_OUI_UPPER_OUI_UPPER_DATA_MASK 0x00ff 23732 #define AN_X1_CONTROL_OUI_UPPER_OUI_UPPER_DATA_ALIGN 0 23733 #define AN_X1_CONTROL_OUI_UPPER_OUI_UPPER_DATA_BITS 8 23734 #define AN_X1_CONTROL_OUI_UPPER_OUI_UPPER_DATA_SHIFT 0 23735 23736 23737 /**************************************************************************** 23738 * AN_X1_CONTROL :: oui_lower 23739 */ 23740 /* AN_X1_CONTROL :: oui_lower :: oui_lower_data [15:00] */ 23741 #define AN_X1_CONTROL_OUI_LOWER_OUI_LOWER_DATA_MASK 0xffff 23742 #define AN_X1_CONTROL_OUI_LOWER_OUI_LOWER_DATA_ALIGN 0 23743 #define AN_X1_CONTROL_OUI_LOWER_OUI_LOWER_DATA_BITS 16 23744 #define AN_X1_CONTROL_OUI_LOWER_OUI_LOWER_DATA_SHIFT 0 23745 23746 23747 /**************************************************************************** 23748 * AN_X1_CONTROL :: bam_speed_pri_0 23749 */ 23750 /* AN_X1_CONTROL :: bam_speed_pri_0 :: an_priority_40G_HG2_KR4 [15:14] */ 23751 #define AN_X1_CONTROL_BAM_SPEED_PRI_0_AN_PRIORITY_40G_HG2_KR4_MASK 0xc000 23752 #define AN_X1_CONTROL_BAM_SPEED_PRI_0_AN_PRIORITY_40G_HG2_KR4_ALIGN 0 23753 #define AN_X1_CONTROL_BAM_SPEED_PRI_0_AN_PRIORITY_40G_HG2_KR4_BITS 2 23754 #define AN_X1_CONTROL_BAM_SPEED_PRI_0_AN_PRIORITY_40G_HG2_KR4_SHIFT 14 23755 23756 /* AN_X1_CONTROL :: bam_speed_pri_0 :: an_priority_40G_KR4 [13:12] */ 23757 #define AN_X1_CONTROL_BAM_SPEED_PRI_0_AN_PRIORITY_40G_KR4_MASK 0x3000 23758 #define AN_X1_CONTROL_BAM_SPEED_PRI_0_AN_PRIORITY_40G_KR4_ALIGN 0 23759 #define AN_X1_CONTROL_BAM_SPEED_PRI_0_AN_PRIORITY_40G_KR4_BITS 2 23760 #define AN_X1_CONTROL_BAM_SPEED_PRI_0_AN_PRIORITY_40G_KR4_SHIFT 12 23761 23762 /* AN_X1_CONTROL :: bam_speed_pri_0 :: an_priority_40G_HG2_CR4 [11:10] */ 23763 #define AN_X1_CONTROL_BAM_SPEED_PRI_0_AN_PRIORITY_40G_HG2_CR4_MASK 0x0c00 23764 #define AN_X1_CONTROL_BAM_SPEED_PRI_0_AN_PRIORITY_40G_HG2_CR4_ALIGN 0 23765 #define AN_X1_CONTROL_BAM_SPEED_PRI_0_AN_PRIORITY_40G_HG2_CR4_BITS 2 23766 #define AN_X1_CONTROL_BAM_SPEED_PRI_0_AN_PRIORITY_40G_HG2_CR4_SHIFT 10 23767 23768 /* AN_X1_CONTROL :: bam_speed_pri_0 :: an_priority_40G_CR4 [09:08] */ 23769 #define AN_X1_CONTROL_BAM_SPEED_PRI_0_AN_PRIORITY_40G_CR4_MASK 0x0300 23770 #define AN_X1_CONTROL_BAM_SPEED_PRI_0_AN_PRIORITY_40G_CR4_ALIGN 0 23771 #define AN_X1_CONTROL_BAM_SPEED_PRI_0_AN_PRIORITY_40G_CR4_BITS 2 23772 #define AN_X1_CONTROL_BAM_SPEED_PRI_0_AN_PRIORITY_40G_CR4_SHIFT 8 23773 23774 /* AN_X1_CONTROL :: bam_speed_pri_0 :: an_priority_100G_HG2_KR4 [07:06] */ 23775 #define AN_X1_CONTROL_BAM_SPEED_PRI_0_AN_PRIORITY_100G_HG2_KR4_MASK 0x00c0 23776 #define AN_X1_CONTROL_BAM_SPEED_PRI_0_AN_PRIORITY_100G_HG2_KR4_ALIGN 0 23777 #define AN_X1_CONTROL_BAM_SPEED_PRI_0_AN_PRIORITY_100G_HG2_KR4_BITS 2 23778 #define AN_X1_CONTROL_BAM_SPEED_PRI_0_AN_PRIORITY_100G_HG2_KR4_SHIFT 6 23779 23780 /* AN_X1_CONTROL :: bam_speed_pri_0 :: an_priority_100G_KR4 [05:04] */ 23781 #define AN_X1_CONTROL_BAM_SPEED_PRI_0_AN_PRIORITY_100G_KR4_MASK 0x0030 23782 #define AN_X1_CONTROL_BAM_SPEED_PRI_0_AN_PRIORITY_100G_KR4_ALIGN 0 23783 #define AN_X1_CONTROL_BAM_SPEED_PRI_0_AN_PRIORITY_100G_KR4_BITS 2 23784 #define AN_X1_CONTROL_BAM_SPEED_PRI_0_AN_PRIORITY_100G_KR4_SHIFT 4 23785 23786 /* AN_X1_CONTROL :: bam_speed_pri_0 :: an_priority_100G_HG2_CR4 [03:02] */ 23787 #define AN_X1_CONTROL_BAM_SPEED_PRI_0_AN_PRIORITY_100G_HG2_CR4_MASK 0x000c 23788 #define AN_X1_CONTROL_BAM_SPEED_PRI_0_AN_PRIORITY_100G_HG2_CR4_ALIGN 0 23789 #define AN_X1_CONTROL_BAM_SPEED_PRI_0_AN_PRIORITY_100G_HG2_CR4_BITS 2 23790 #define AN_X1_CONTROL_BAM_SPEED_PRI_0_AN_PRIORITY_100G_HG2_CR4_SHIFT 2 23791 23792 /* AN_X1_CONTROL :: bam_speed_pri_0 :: an_priority_100G_CR4 [01:00] */ 23793 #define AN_X1_CONTROL_BAM_SPEED_PRI_0_AN_PRIORITY_100G_CR4_MASK 0x0003 23794 #define AN_X1_CONTROL_BAM_SPEED_PRI_0_AN_PRIORITY_100G_CR4_ALIGN 0 23795 #define AN_X1_CONTROL_BAM_SPEED_PRI_0_AN_PRIORITY_100G_CR4_BITS 2 23796 #define AN_X1_CONTROL_BAM_SPEED_PRI_0_AN_PRIORITY_100G_CR4_SHIFT 0 23797 23798 23799 /**************************************************************************** 23800 * AN_X1_CONTROL :: bam_speed_pri_1 23801 */ 23802 /* AN_X1_CONTROL :: bam_speed_pri_1 :: an_priority_50G_HG2_KR2 [15:14] */ 23803 #define AN_X1_CONTROL_BAM_SPEED_PRI_1_AN_PRIORITY_50G_HG2_KR2_MASK 0xc000 23804 #define AN_X1_CONTROL_BAM_SPEED_PRI_1_AN_PRIORITY_50G_HG2_KR2_ALIGN 0 23805 #define AN_X1_CONTROL_BAM_SPEED_PRI_1_AN_PRIORITY_50G_HG2_KR2_BITS 2 23806 #define AN_X1_CONTROL_BAM_SPEED_PRI_1_AN_PRIORITY_50G_HG2_KR2_SHIFT 14 23807 23808 /* AN_X1_CONTROL :: bam_speed_pri_1 :: an_priority_50G_KR2 [13:12] */ 23809 #define AN_X1_CONTROL_BAM_SPEED_PRI_1_AN_PRIORITY_50G_KR2_MASK 0x3000 23810 #define AN_X1_CONTROL_BAM_SPEED_PRI_1_AN_PRIORITY_50G_KR2_ALIGN 0 23811 #define AN_X1_CONTROL_BAM_SPEED_PRI_1_AN_PRIORITY_50G_KR2_BITS 2 23812 #define AN_X1_CONTROL_BAM_SPEED_PRI_1_AN_PRIORITY_50G_KR2_SHIFT 12 23813 23814 /* AN_X1_CONTROL :: bam_speed_pri_1 :: an_priority_50G_HG2_CR2 [11:10] */ 23815 #define AN_X1_CONTROL_BAM_SPEED_PRI_1_AN_PRIORITY_50G_HG2_CR2_MASK 0x0c00 23816 #define AN_X1_CONTROL_BAM_SPEED_PRI_1_AN_PRIORITY_50G_HG2_CR2_ALIGN 0 23817 #define AN_X1_CONTROL_BAM_SPEED_PRI_1_AN_PRIORITY_50G_HG2_CR2_BITS 2 23818 #define AN_X1_CONTROL_BAM_SPEED_PRI_1_AN_PRIORITY_50G_HG2_CR2_SHIFT 10 23819 23820 /* AN_X1_CONTROL :: bam_speed_pri_1 :: an_priority_50G_CR2 [09:08] */ 23821 #define AN_X1_CONTROL_BAM_SPEED_PRI_1_AN_PRIORITY_50G_CR2_MASK 0x0300 23822 #define AN_X1_CONTROL_BAM_SPEED_PRI_1_AN_PRIORITY_50G_CR2_ALIGN 0 23823 #define AN_X1_CONTROL_BAM_SPEED_PRI_1_AN_PRIORITY_50G_CR2_BITS 2 23824 #define AN_X1_CONTROL_BAM_SPEED_PRI_1_AN_PRIORITY_50G_CR2_SHIFT 8 23825 23826 /* AN_X1_CONTROL :: bam_speed_pri_1 :: an_priority_50G_HG2_KR4 [07:06] */ 23827 #define AN_X1_CONTROL_BAM_SPEED_PRI_1_AN_PRIORITY_50G_HG2_KR4_MASK 0x00c0 23828 #define AN_X1_CONTROL_BAM_SPEED_PRI_1_AN_PRIORITY_50G_HG2_KR4_ALIGN 0 23829 #define AN_X1_CONTROL_BAM_SPEED_PRI_1_AN_PRIORITY_50G_HG2_KR4_BITS 2 23830 #define AN_X1_CONTROL_BAM_SPEED_PRI_1_AN_PRIORITY_50G_HG2_KR4_SHIFT 6 23831 23832 /* AN_X1_CONTROL :: bam_speed_pri_1 :: an_priority_50G_KR4 [05:04] */ 23833 #define AN_X1_CONTROL_BAM_SPEED_PRI_1_AN_PRIORITY_50G_KR4_MASK 0x0030 23834 #define AN_X1_CONTROL_BAM_SPEED_PRI_1_AN_PRIORITY_50G_KR4_ALIGN 0 23835 #define AN_X1_CONTROL_BAM_SPEED_PRI_1_AN_PRIORITY_50G_KR4_BITS 2 23836 #define AN_X1_CONTROL_BAM_SPEED_PRI_1_AN_PRIORITY_50G_KR4_SHIFT 4 23837 23838 /* AN_X1_CONTROL :: bam_speed_pri_1 :: an_priority_50G_HG2_CR4 [03:02] */ 23839 #define AN_X1_CONTROL_BAM_SPEED_PRI_1_AN_PRIORITY_50G_HG2_CR4_MASK 0x000c 23840 #define AN_X1_CONTROL_BAM_SPEED_PRI_1_AN_PRIORITY_50G_HG2_CR4_ALIGN 0 23841 #define AN_X1_CONTROL_BAM_SPEED_PRI_1_AN_PRIORITY_50G_HG2_CR4_BITS 2 23842 #define AN_X1_CONTROL_BAM_SPEED_PRI_1_AN_PRIORITY_50G_HG2_CR4_SHIFT 2 23843 23844 /* AN_X1_CONTROL :: bam_speed_pri_1 :: an_priority_50G_CR4 [01:00] */ 23845 #define AN_X1_CONTROL_BAM_SPEED_PRI_1_AN_PRIORITY_50G_CR4_MASK 0x0003 23846 #define AN_X1_CONTROL_BAM_SPEED_PRI_1_AN_PRIORITY_50G_CR4_ALIGN 0 23847 #define AN_X1_CONTROL_BAM_SPEED_PRI_1_AN_PRIORITY_50G_CR4_BITS 2 23848 #define AN_X1_CONTROL_BAM_SPEED_PRI_1_AN_PRIORITY_50G_CR4_SHIFT 0 23849 23850 23851 /**************************************************************************** 23852 * AN_X1_CONTROL :: bam_speed_pri_2 23853 */ 23854 /* AN_X1_CONTROL :: bam_speed_pri_2 :: an_priority_25G_HG2_KR1 [15:14] */ 23855 #define AN_X1_CONTROL_BAM_SPEED_PRI_2_AN_PRIORITY_25G_HG2_KR1_MASK 0xc000 23856 #define AN_X1_CONTROL_BAM_SPEED_PRI_2_AN_PRIORITY_25G_HG2_KR1_ALIGN 0 23857 #define AN_X1_CONTROL_BAM_SPEED_PRI_2_AN_PRIORITY_25G_HG2_KR1_BITS 2 23858 #define AN_X1_CONTROL_BAM_SPEED_PRI_2_AN_PRIORITY_25G_HG2_KR1_SHIFT 14 23859 23860 /* AN_X1_CONTROL :: bam_speed_pri_2 :: an_priority_25G_KR1 [13:12] */ 23861 #define AN_X1_CONTROL_BAM_SPEED_PRI_2_AN_PRIORITY_25G_KR1_MASK 0x3000 23862 #define AN_X1_CONTROL_BAM_SPEED_PRI_2_AN_PRIORITY_25G_KR1_ALIGN 0 23863 #define AN_X1_CONTROL_BAM_SPEED_PRI_2_AN_PRIORITY_25G_KR1_BITS 2 23864 #define AN_X1_CONTROL_BAM_SPEED_PRI_2_AN_PRIORITY_25G_KR1_SHIFT 12 23865 23866 /* AN_X1_CONTROL :: bam_speed_pri_2 :: an_priority_25G_HG2_CR1 [11:10] */ 23867 #define AN_X1_CONTROL_BAM_SPEED_PRI_2_AN_PRIORITY_25G_HG2_CR1_MASK 0x0c00 23868 #define AN_X1_CONTROL_BAM_SPEED_PRI_2_AN_PRIORITY_25G_HG2_CR1_ALIGN 0 23869 #define AN_X1_CONTROL_BAM_SPEED_PRI_2_AN_PRIORITY_25G_HG2_CR1_BITS 2 23870 #define AN_X1_CONTROL_BAM_SPEED_PRI_2_AN_PRIORITY_25G_HG2_CR1_SHIFT 10 23871 23872 /* AN_X1_CONTROL :: bam_speed_pri_2 :: an_priority_25G_CR1 [09:08] */ 23873 #define AN_X1_CONTROL_BAM_SPEED_PRI_2_AN_PRIORITY_25G_CR1_MASK 0x0300 23874 #define AN_X1_CONTROL_BAM_SPEED_PRI_2_AN_PRIORITY_25G_CR1_ALIGN 0 23875 #define AN_X1_CONTROL_BAM_SPEED_PRI_2_AN_PRIORITY_25G_CR1_BITS 2 23876 #define AN_X1_CONTROL_BAM_SPEED_PRI_2_AN_PRIORITY_25G_CR1_SHIFT 8 23877 23878 /* AN_X1_CONTROL :: bam_speed_pri_2 :: an_priority_40G_HG2_KR2 [07:06] */ 23879 #define AN_X1_CONTROL_BAM_SPEED_PRI_2_AN_PRIORITY_40G_HG2_KR2_MASK 0x00c0 23880 #define AN_X1_CONTROL_BAM_SPEED_PRI_2_AN_PRIORITY_40G_HG2_KR2_ALIGN 0 23881 #define AN_X1_CONTROL_BAM_SPEED_PRI_2_AN_PRIORITY_40G_HG2_KR2_BITS 2 23882 #define AN_X1_CONTROL_BAM_SPEED_PRI_2_AN_PRIORITY_40G_HG2_KR2_SHIFT 6 23883 23884 /* AN_X1_CONTROL :: bam_speed_pri_2 :: an_priority_40G_KR2 [05:04] */ 23885 #define AN_X1_CONTROL_BAM_SPEED_PRI_2_AN_PRIORITY_40G_KR2_MASK 0x0030 23886 #define AN_X1_CONTROL_BAM_SPEED_PRI_2_AN_PRIORITY_40G_KR2_ALIGN 0 23887 #define AN_X1_CONTROL_BAM_SPEED_PRI_2_AN_PRIORITY_40G_KR2_BITS 2 23888 #define AN_X1_CONTROL_BAM_SPEED_PRI_2_AN_PRIORITY_40G_KR2_SHIFT 4 23889 23890 /* AN_X1_CONTROL :: bam_speed_pri_2 :: an_priority_40G_HG2_CR2 [03:02] */ 23891 #define AN_X1_CONTROL_BAM_SPEED_PRI_2_AN_PRIORITY_40G_HG2_CR2_MASK 0x000c 23892 #define AN_X1_CONTROL_BAM_SPEED_PRI_2_AN_PRIORITY_40G_HG2_CR2_ALIGN 0 23893 #define AN_X1_CONTROL_BAM_SPEED_PRI_2_AN_PRIORITY_40G_HG2_CR2_BITS 2 23894 #define AN_X1_CONTROL_BAM_SPEED_PRI_2_AN_PRIORITY_40G_HG2_CR2_SHIFT 2 23895 23896 /* AN_X1_CONTROL :: bam_speed_pri_2 :: an_priority_40G_CR2 [01:00] */ 23897 #define AN_X1_CONTROL_BAM_SPEED_PRI_2_AN_PRIORITY_40G_CR2_MASK 0x0003 23898 #define AN_X1_CONTROL_BAM_SPEED_PRI_2_AN_PRIORITY_40G_CR2_ALIGN 0 23899 #define AN_X1_CONTROL_BAM_SPEED_PRI_2_AN_PRIORITY_40G_CR2_BITS 2 23900 #define AN_X1_CONTROL_BAM_SPEED_PRI_2_AN_PRIORITY_40G_CR2_SHIFT 0 23901 23902 23903 /**************************************************************************** 23904 * AN_X1_CONTROL :: bam_speed_pri_3 23905 */ 23906 /* AN_X1_CONTROL :: bam_speed_pri_3 :: an_priority_20G_HG2_KR2 [15:14] */ 23907 #define AN_X1_CONTROL_BAM_SPEED_PRI_3_AN_PRIORITY_20G_HG2_KR2_MASK 0xc000 23908 #define AN_X1_CONTROL_BAM_SPEED_PRI_3_AN_PRIORITY_20G_HG2_KR2_ALIGN 0 23909 #define AN_X1_CONTROL_BAM_SPEED_PRI_3_AN_PRIORITY_20G_HG2_KR2_BITS 2 23910 #define AN_X1_CONTROL_BAM_SPEED_PRI_3_AN_PRIORITY_20G_HG2_KR2_SHIFT 14 23911 23912 /* AN_X1_CONTROL :: bam_speed_pri_3 :: an_priority_20G_KR2 [13:12] */ 23913 #define AN_X1_CONTROL_BAM_SPEED_PRI_3_AN_PRIORITY_20G_KR2_MASK 0x3000 23914 #define AN_X1_CONTROL_BAM_SPEED_PRI_3_AN_PRIORITY_20G_KR2_ALIGN 0 23915 #define AN_X1_CONTROL_BAM_SPEED_PRI_3_AN_PRIORITY_20G_KR2_BITS 2 23916 #define AN_X1_CONTROL_BAM_SPEED_PRI_3_AN_PRIORITY_20G_KR2_SHIFT 12 23917 23918 /* AN_X1_CONTROL :: bam_speed_pri_3 :: an_priority_20G_HG2_CR2 [11:10] */ 23919 #define AN_X1_CONTROL_BAM_SPEED_PRI_3_AN_PRIORITY_20G_HG2_CR2_MASK 0x0c00 23920 #define AN_X1_CONTROL_BAM_SPEED_PRI_3_AN_PRIORITY_20G_HG2_CR2_ALIGN 0 23921 #define AN_X1_CONTROL_BAM_SPEED_PRI_3_AN_PRIORITY_20G_HG2_CR2_BITS 2 23922 #define AN_X1_CONTROL_BAM_SPEED_PRI_3_AN_PRIORITY_20G_HG2_CR2_SHIFT 10 23923 23924 /* AN_X1_CONTROL :: bam_speed_pri_3 :: an_priority_20G_CR2 [09:08] */ 23925 #define AN_X1_CONTROL_BAM_SPEED_PRI_3_AN_PRIORITY_20G_CR2_MASK 0x0300 23926 #define AN_X1_CONTROL_BAM_SPEED_PRI_3_AN_PRIORITY_20G_CR2_ALIGN 0 23927 #define AN_X1_CONTROL_BAM_SPEED_PRI_3_AN_PRIORITY_20G_CR2_BITS 2 23928 #define AN_X1_CONTROL_BAM_SPEED_PRI_3_AN_PRIORITY_20G_CR2_SHIFT 8 23929 23930 /* AN_X1_CONTROL :: bam_speed_pri_3 :: an_priority_20G_HG2_KR1 [07:06] */ 23931 #define AN_X1_CONTROL_BAM_SPEED_PRI_3_AN_PRIORITY_20G_HG2_KR1_MASK 0x00c0 23932 #define AN_X1_CONTROL_BAM_SPEED_PRI_3_AN_PRIORITY_20G_HG2_KR1_ALIGN 0 23933 #define AN_X1_CONTROL_BAM_SPEED_PRI_3_AN_PRIORITY_20G_HG2_KR1_BITS 2 23934 #define AN_X1_CONTROL_BAM_SPEED_PRI_3_AN_PRIORITY_20G_HG2_KR1_SHIFT 6 23935 23936 /* AN_X1_CONTROL :: bam_speed_pri_3 :: an_priority_20G_KR1 [05:04] */ 23937 #define AN_X1_CONTROL_BAM_SPEED_PRI_3_AN_PRIORITY_20G_KR1_MASK 0x0030 23938 #define AN_X1_CONTROL_BAM_SPEED_PRI_3_AN_PRIORITY_20G_KR1_ALIGN 0 23939 #define AN_X1_CONTROL_BAM_SPEED_PRI_3_AN_PRIORITY_20G_KR1_BITS 2 23940 #define AN_X1_CONTROL_BAM_SPEED_PRI_3_AN_PRIORITY_20G_KR1_SHIFT 4 23941 23942 /* AN_X1_CONTROL :: bam_speed_pri_3 :: an_priority_20G_HG2_CR1 [03:02] */ 23943 #define AN_X1_CONTROL_BAM_SPEED_PRI_3_AN_PRIORITY_20G_HG2_CR1_MASK 0x000c 23944 #define AN_X1_CONTROL_BAM_SPEED_PRI_3_AN_PRIORITY_20G_HG2_CR1_ALIGN 0 23945 #define AN_X1_CONTROL_BAM_SPEED_PRI_3_AN_PRIORITY_20G_HG2_CR1_BITS 2 23946 #define AN_X1_CONTROL_BAM_SPEED_PRI_3_AN_PRIORITY_20G_HG2_CR1_SHIFT 2 23947 23948 /* AN_X1_CONTROL :: bam_speed_pri_3 :: an_priority_20G_CR1 [01:00] */ 23949 #define AN_X1_CONTROL_BAM_SPEED_PRI_3_AN_PRIORITY_20G_CR1_MASK 0x0003 23950 #define AN_X1_CONTROL_BAM_SPEED_PRI_3_AN_PRIORITY_20G_CR1_ALIGN 0 23951 #define AN_X1_CONTROL_BAM_SPEED_PRI_3_AN_PRIORITY_20G_CR1_BITS 2 23952 #define AN_X1_CONTROL_BAM_SPEED_PRI_3_AN_PRIORITY_20G_CR1_SHIFT 0 23953 23954 23955 /**************************************************************************** 23956 * AN_X1_CONTROL :: bam_speed_pri_4 23957 */ 23958 /* AN_X1_CONTROL :: bam_speed_pri_4 :: reserved0 [15:06] */ 23959 #define AN_X1_CONTROL_BAM_SPEED_PRI_4_RESERVED0_MASK 0xffc0 23960 #define AN_X1_CONTROL_BAM_SPEED_PRI_4_RESERVED0_ALIGN 0 23961 #define AN_X1_CONTROL_BAM_SPEED_PRI_4_RESERVED0_BITS 10 23962 #define AN_X1_CONTROL_BAM_SPEED_PRI_4_RESERVED0_SHIFT 6 23963 23964 /* AN_X1_CONTROL :: bam_speed_pri_4 :: an_priority_1G_KX1 [05:04] */ 23965 #define AN_X1_CONTROL_BAM_SPEED_PRI_4_AN_PRIORITY_1G_KX1_MASK 0x0030 23966 #define AN_X1_CONTROL_BAM_SPEED_PRI_4_AN_PRIORITY_1G_KX1_ALIGN 0 23967 #define AN_X1_CONTROL_BAM_SPEED_PRI_4_AN_PRIORITY_1G_KX1_BITS 2 23968 #define AN_X1_CONTROL_BAM_SPEED_PRI_4_AN_PRIORITY_1G_KX1_SHIFT 4 23969 23970 /* AN_X1_CONTROL :: bam_speed_pri_4 :: an_priority_10G_HG2_KR1 [03:02] */ 23971 #define AN_X1_CONTROL_BAM_SPEED_PRI_4_AN_PRIORITY_10G_HG2_KR1_MASK 0x000c 23972 #define AN_X1_CONTROL_BAM_SPEED_PRI_4_AN_PRIORITY_10G_HG2_KR1_ALIGN 0 23973 #define AN_X1_CONTROL_BAM_SPEED_PRI_4_AN_PRIORITY_10G_HG2_KR1_BITS 2 23974 #define AN_X1_CONTROL_BAM_SPEED_PRI_4_AN_PRIORITY_10G_HG2_KR1_SHIFT 2 23975 23976 /* AN_X1_CONTROL :: bam_speed_pri_4 :: an_priority_10G_KR1 [01:00] */ 23977 #define AN_X1_CONTROL_BAM_SPEED_PRI_4_AN_PRIORITY_10G_KR1_MASK 0x0003 23978 #define AN_X1_CONTROL_BAM_SPEED_PRI_4_AN_PRIORITY_10G_KR1_ALIGN 0 23979 #define AN_X1_CONTROL_BAM_SPEED_PRI_4_AN_PRIORITY_10G_KR1_BITS 2 23980 #define AN_X1_CONTROL_BAM_SPEED_PRI_4_AN_PRIORITY_10G_KR1_SHIFT 0 23981 23982 23983 /**************************************************************************** 23984 * AN_X1_CONTROL :: ieee_speed_pri_1 23985 */ 23986 /* AN_X1_CONTROL :: ieee_speed_pri_1 :: reserved0 [15:08] */ 23987 #define AN_X1_CONTROL_IEEE_SPEED_PRI_1_RESERVED0_MASK 0xff00 23988 #define AN_X1_CONTROL_IEEE_SPEED_PRI_1_RESERVED0_ALIGN 0 23989 #define AN_X1_CONTROL_IEEE_SPEED_PRI_1_RESERVED0_BITS 8 23990 #define AN_X1_CONTROL_IEEE_SPEED_PRI_1_RESERVED0_SHIFT 8 23991 23992 /* AN_X1_CONTROL :: ieee_speed_pri_1 :: an_priority_25G_KRS1_IEEE [07:06] */ 23993 #define AN_X1_CONTROL_IEEE_SPEED_PRI_1_AN_PRIORITY_25G_KRS1_IEEE_MASK 0x00c0 23994 #define AN_X1_CONTROL_IEEE_SPEED_PRI_1_AN_PRIORITY_25G_KRS1_IEEE_ALIGN 0 23995 #define AN_X1_CONTROL_IEEE_SPEED_PRI_1_AN_PRIORITY_25G_KRS1_IEEE_BITS 2 23996 #define AN_X1_CONTROL_IEEE_SPEED_PRI_1_AN_PRIORITY_25G_KRS1_IEEE_SHIFT 6 23997 23998 /* AN_X1_CONTROL :: ieee_speed_pri_1 :: an_priority_25G_KR1_IEEE [05:04] */ 23999 #define AN_X1_CONTROL_IEEE_SPEED_PRI_1_AN_PRIORITY_25G_KR1_IEEE_MASK 0x0030 24000 #define AN_X1_CONTROL_IEEE_SPEED_PRI_1_AN_PRIORITY_25G_KR1_IEEE_ALIGN 0 24001 #define AN_X1_CONTROL_IEEE_SPEED_PRI_1_AN_PRIORITY_25G_KR1_IEEE_BITS 2 24002 #define AN_X1_CONTROL_IEEE_SPEED_PRI_1_AN_PRIORITY_25G_KR1_IEEE_SHIFT 4 24003 24004 /* AN_X1_CONTROL :: ieee_speed_pri_1 :: an_priority_25G_CRS1_IEEE [03:02] */ 24005 #define AN_X1_CONTROL_IEEE_SPEED_PRI_1_AN_PRIORITY_25G_CRS1_IEEE_MASK 0x000c 24006 #define AN_X1_CONTROL_IEEE_SPEED_PRI_1_AN_PRIORITY_25G_CRS1_IEEE_ALIGN 0 24007 #define AN_X1_CONTROL_IEEE_SPEED_PRI_1_AN_PRIORITY_25G_CRS1_IEEE_BITS 2 24008 #define AN_X1_CONTROL_IEEE_SPEED_PRI_1_AN_PRIORITY_25G_CRS1_IEEE_SHIFT 2 24009 24010 /* AN_X1_CONTROL :: ieee_speed_pri_1 :: an_priority_25G_CR1_IEEE [01:00] */ 24011 #define AN_X1_CONTROL_IEEE_SPEED_PRI_1_AN_PRIORITY_25G_CR1_IEEE_MASK 0x0003 24012 #define AN_X1_CONTROL_IEEE_SPEED_PRI_1_AN_PRIORITY_25G_CR1_IEEE_ALIGN 0 24013 #define AN_X1_CONTROL_IEEE_SPEED_PRI_1_AN_PRIORITY_25G_CR1_IEEE_BITS 2 24014 #define AN_X1_CONTROL_IEEE_SPEED_PRI_1_AN_PRIORITY_25G_CR1_IEEE_SHIFT 0 24015 24016 24017 /**************************************************************************** 24018 * TSC_WC4_TSC_USER1_AN_X1_TIMERS 24019 */ 24020 /**************************************************************************** 24021 * AN_X1_TIMERS :: cl73_break_link 24022 */ 24023 /* AN_X1_TIMERS :: cl73_break_link :: cl73_break_timer_period [15:00] */ 24024 #define AN_X1_TIMERS_CL73_BREAK_LINK_CL73_BREAK_TIMER_PERIOD_MASK 0xffff 24025 #define AN_X1_TIMERS_CL73_BREAK_LINK_CL73_BREAK_TIMER_PERIOD_ALIGN 0 24026 #define AN_X1_TIMERS_CL73_BREAK_LINK_CL73_BREAK_TIMER_PERIOD_BITS 16 24027 #define AN_X1_TIMERS_CL73_BREAK_LINK_CL73_BREAK_TIMER_PERIOD_SHIFT 0 24028 24029 24030 /**************************************************************************** 24031 * AN_X1_TIMERS :: cl73_error 24032 */ 24033 /* AN_X1_TIMERS :: cl73_error :: cl73_error_timer_period [15:00] */ 24034 #define AN_X1_TIMERS_CL73_ERROR_CL73_ERROR_TIMER_PERIOD_MASK 0xffff 24035 #define AN_X1_TIMERS_CL73_ERROR_CL73_ERROR_TIMER_PERIOD_ALIGN 0 24036 #define AN_X1_TIMERS_CL73_ERROR_CL73_ERROR_TIMER_PERIOD_BITS 16 24037 #define AN_X1_TIMERS_CL73_ERROR_CL73_ERROR_TIMER_PERIOD_SHIFT 0 24038 24039 24040 /**************************************************************************** 24041 * AN_X1_TIMERS :: cl73_dme_lock 24042 */ 24043 /* AN_X1_TIMERS :: cl73_dme_lock :: pd_dme_lock_timer_period [15:00] */ 24044 #define AN_X1_TIMERS_CL73_DME_LOCK_PD_DME_LOCK_TIMER_PERIOD_MASK 0xffff 24045 #define AN_X1_TIMERS_CL73_DME_LOCK_PD_DME_LOCK_TIMER_PERIOD_ALIGN 0 24046 #define AN_X1_TIMERS_CL73_DME_LOCK_PD_DME_LOCK_TIMER_PERIOD_BITS 16 24047 #define AN_X1_TIMERS_CL73_DME_LOCK_PD_DME_LOCK_TIMER_PERIOD_SHIFT 0 24048 24049 24050 /**************************************************************************** 24051 * AN_X1_TIMERS :: pd_sd_timer 24052 */ 24053 /* AN_X1_TIMERS :: pd_sd_timer :: pd_sd_timer_period [15:00] */ 24054 #define AN_X1_TIMERS_PD_SD_TIMER_PD_SD_TIMER_PERIOD_MASK 0xffff 24055 #define AN_X1_TIMERS_PD_SD_TIMER_PD_SD_TIMER_PERIOD_ALIGN 0 24056 #define AN_X1_TIMERS_PD_SD_TIMER_PD_SD_TIMER_PERIOD_BITS 16 24057 #define AN_X1_TIMERS_PD_SD_TIMER_PD_SD_TIMER_PERIOD_SHIFT 0 24058 24059 24060 /**************************************************************************** 24061 * AN_X1_TIMERS :: ignore_link_timer 24062 */ 24063 /* AN_X1_TIMERS :: ignore_link_timer :: ignore_link_timer_period [15:00] */ 24064 #define AN_X1_TIMERS_IGNORE_LINK_TIMER_IGNORE_LINK_TIMER_PERIOD_MASK 0xffff 24065 #define AN_X1_TIMERS_IGNORE_LINK_TIMER_IGNORE_LINK_TIMER_PERIOD_ALIGN 0 24066 #define AN_X1_TIMERS_IGNORE_LINK_TIMER_IGNORE_LINK_TIMER_PERIOD_BITS 16 24067 #define AN_X1_TIMERS_IGNORE_LINK_TIMER_IGNORE_LINK_TIMER_PERIOD_SHIFT 0 24068 24069 24070 /**************************************************************************** 24071 * AN_X1_TIMERS :: link_fail_inhibit_timer_cl72 24072 */ 24073 /* AN_X1_TIMERS :: link_fail_inhibit_timer_cl72 :: link_fail_inhibit_timer_cl72_period [15:00] */ 24074 #define AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_CL72_LINK_FAIL_INHIBIT_TIMER_CL72_PERIOD_MASK 0xffff 24075 #define AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_CL72_LINK_FAIL_INHIBIT_TIMER_CL72_PERIOD_ALIGN 0 24076 #define AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_CL72_LINK_FAIL_INHIBIT_TIMER_CL72_PERIOD_BITS 16 24077 #define AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_CL72_LINK_FAIL_INHIBIT_TIMER_CL72_PERIOD_SHIFT 0 24078 24079 24080 /**************************************************************************** 24081 * AN_X1_TIMERS :: link_fail_inhibit_timer_not_cl72 24082 */ 24083 /* AN_X1_TIMERS :: link_fail_inhibit_timer_not_cl72 :: link_fail_inhibit_timer_ncl72_period [15:00] */ 24084 #define AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_NOT_CL72_LINK_FAIL_INHIBIT_TIMER_NCL72_PERIOD_MASK 0xffff 24085 #define AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_NOT_CL72_LINK_FAIL_INHIBIT_TIMER_NCL72_PERIOD_ALIGN 0 24086 #define AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_NOT_CL72_LINK_FAIL_INHIBIT_TIMER_NCL72_PERIOD_BITS 16 24087 #define AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_NOT_CL72_LINK_FAIL_INHIBIT_TIMER_NCL72_PERIOD_SHIFT 0 24088 24089 24090 /**************************************************************************** 24091 * AN_X1_TIMERS :: dme_page_timer_type 24092 */ 24093 /* AN_X1_TIMERS :: dme_page_timer_type :: reserved0 [15:14] */ 24094 #define AN_X1_TIMERS_DME_PAGE_TIMER_TYPE_RESERVED0_MASK 0xc000 24095 #define AN_X1_TIMERS_DME_PAGE_TIMER_TYPE_RESERVED0_ALIGN 0 24096 #define AN_X1_TIMERS_DME_PAGE_TIMER_TYPE_RESERVED0_BITS 2 24097 #define AN_X1_TIMERS_DME_PAGE_TIMER_TYPE_RESERVED0_SHIFT 14 24098 24099 /* AN_X1_TIMERS :: dme_page_timer_type :: cl73_page_test_max_timer [13:07] */ 24100 #define AN_X1_TIMERS_DME_PAGE_TIMER_TYPE_CL73_PAGE_TEST_MAX_TIMER_MASK 0x3f80 24101 #define AN_X1_TIMERS_DME_PAGE_TIMER_TYPE_CL73_PAGE_TEST_MAX_TIMER_ALIGN 0 24102 #define AN_X1_TIMERS_DME_PAGE_TIMER_TYPE_CL73_PAGE_TEST_MAX_TIMER_BITS 7 24103 #define AN_X1_TIMERS_DME_PAGE_TIMER_TYPE_CL73_PAGE_TEST_MAX_TIMER_SHIFT 7 24104 24105 /* AN_X1_TIMERS :: dme_page_timer_type :: cl73_page_test_min_timer [06:00] */ 24106 #define AN_X1_TIMERS_DME_PAGE_TIMER_TYPE_CL73_PAGE_TEST_MIN_TIMER_MASK 0x007f 24107 #define AN_X1_TIMERS_DME_PAGE_TIMER_TYPE_CL73_PAGE_TEST_MIN_TIMER_ALIGN 0 24108 #define AN_X1_TIMERS_DME_PAGE_TIMER_TYPE_CL73_PAGE_TEST_MIN_TIMER_BITS 7 24109 #define AN_X1_TIMERS_DME_PAGE_TIMER_TYPE_CL73_PAGE_TEST_MIN_TIMER_SHIFT 0 24110 24111 24112 /**************************************************************************** 24113 * TSC_WC4_TSC_USER1_sc_x1_control 24114 */ 24115 /**************************************************************************** 24116 * sc_x1_control :: pll_lock_timer 24117 */ 24118 /* sc_x1_control :: pll_lock_timer :: pll_lock_timer_period [15:00] */ 24119 #define SC_X1_CONTROL_PLL_LOCK_TIMER_PLL_LOCK_TIMER_PERIOD_MASK 0xffff 24120 #define SC_X1_CONTROL_PLL_LOCK_TIMER_PLL_LOCK_TIMER_PERIOD_ALIGN 0 24121 #define SC_X1_CONTROL_PLL_LOCK_TIMER_PLL_LOCK_TIMER_PERIOD_BITS 16 24122 #define SC_X1_CONTROL_PLL_LOCK_TIMER_PLL_LOCK_TIMER_PERIOD_SHIFT 0 24123 24124 24125 /**************************************************************************** 24126 * sc_x1_control :: pmd_lock_timer 24127 */ 24128 /* sc_x1_control :: pmd_lock_timer :: pmd_lock_timer_period [15:00] */ 24129 #define SC_X1_CONTROL_PMD_LOCK_TIMER_PMD_LOCK_TIMER_PERIOD_MASK 0xffff 24130 #define SC_X1_CONTROL_PMD_LOCK_TIMER_PMD_LOCK_TIMER_PERIOD_ALIGN 0 24131 #define SC_X1_CONTROL_PMD_LOCK_TIMER_PMD_LOCK_TIMER_PERIOD_BITS 16 24132 #define SC_X1_CONTROL_PMD_LOCK_TIMER_PMD_LOCK_TIMER_PERIOD_SHIFT 0 24133 24134 24135 /**************************************************************************** 24136 * sc_x1_control :: pipeline_reset_count 24137 */ 24138 /* sc_x1_control :: pipeline_reset_count :: pipeline_reset_count [15:00] */ 24139 #define SC_X1_CONTROL_PIPELINE_RESET_COUNT_PIPELINE_RESET_COUNT_MASK 0xffff 24140 #define SC_X1_CONTROL_PIPELINE_RESET_COUNT_PIPELINE_RESET_COUNT_ALIGN 0 24141 #define SC_X1_CONTROL_PIPELINE_RESET_COUNT_PIPELINE_RESET_COUNT_BITS 16 24142 #define SC_X1_CONTROL_PIPELINE_RESET_COUNT_PIPELINE_RESET_COUNT_SHIFT 0 24143 24144 24145 /**************************************************************************** 24146 * sc_x1_control :: tx_reset_count 24147 */ 24148 /* sc_x1_control :: tx_reset_count :: tx_reset_count [15:00] */ 24149 #define SC_X1_CONTROL_TX_RESET_COUNT_TX_RESET_COUNT_MASK 0xffff 24150 #define SC_X1_CONTROL_TX_RESET_COUNT_TX_RESET_COUNT_ALIGN 0 24151 #define SC_X1_CONTROL_TX_RESET_COUNT_TX_RESET_COUNT_BITS 16 24152 #define SC_X1_CONTROL_TX_RESET_COUNT_TX_RESET_COUNT_SHIFT 0 24153 24154 24155 /**************************************************************************** 24156 * sc_x1_control :: status 24157 */ 24158 /* sc_x1_control :: status :: reserved0 [15:03] */ 24159 #define SC_X1_CONTROL_STATUS_RESERVED0_MASK 0xfff8 24160 #define SC_X1_CONTROL_STATUS_RESERVED0_ALIGN 0 24161 #define SC_X1_CONTROL_STATUS_RESERVED0_BITS 13 24162 #define SC_X1_CONTROL_STATUS_RESERVED0_SHIFT 3 24163 24164 /* sc_x1_control :: status :: resolved_port_mode [02:00] */ 24165 #define SC_X1_CONTROL_STATUS_RESOLVED_PORT_MODE_MASK 0x0007 24166 #define SC_X1_CONTROL_STATUS_RESOLVED_PORT_MODE_ALIGN 0 24167 #define SC_X1_CONTROL_STATUS_RESOLVED_PORT_MODE_BITS 3 24168 #define SC_X1_CONTROL_STATUS_RESOLVED_PORT_MODE_SHIFT 0 24169 24170 24171 /**************************************************************************** 24172 * TSC_WC4_TSC_USER1_sc_x1_speed_override0 24173 */ 24174 /**************************************************************************** 24175 * sc_x1_speed_override0 :: override_speed 24176 */ 24177 /* sc_x1_speed_override0 :: override_speed :: speed [15:08] */ 24178 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_MASK 0xff00 24179 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_ALIGN 0 24180 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_BITS 8 24181 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_SHIFT 8 24182 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_10G_CR1 0 24183 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_10G_KR1 1 24184 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_10G_X1 2 24185 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_10G_HG2_CR1 4 24186 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_10G_HG2_KR1 5 24187 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_10G_HG2_X1 6 24188 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_20G_CR1 8 24189 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_20G_KR1 9 24190 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_20G_X1 10 24191 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_20G_HG2_CR1 12 24192 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_20G_HG2_KR1 13 24193 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_20G_HG2_X1 14 24194 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_25G_CR1 16 24195 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_25G_KR1 17 24196 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_25G_X1 18 24197 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_25G_HG2_CR1 20 24198 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_25G_HG2_KR1 21 24199 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_25G_HG2_X1 22 24200 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_20G_CR2 24 24201 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_20G_KR2 25 24202 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_20G_X2 26 24203 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_20G_HG2_CR2 28 24204 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_20G_HG2_KR2 29 24205 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_20G_HG2_X2 30 24206 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_40G_CR2 32 24207 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_40G_KR2 33 24208 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_40G_X2 34 24209 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_40G_HG2_CR2 36 24210 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_40G_HG2_KR2 37 24211 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_40G_HG2_X2 38 24212 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_40G_CR4 40 24213 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_40G_KR4 41 24214 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_40G_X4 42 24215 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_40G_HG2_CR4 44 24216 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_40G_HG2_KR4 45 24217 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_40G_HG2_X4 46 24218 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_50G_CR2 48 24219 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_50G_KR2 49 24220 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_50G_X2 50 24221 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_50G_HG2_CR2 52 24222 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_50G_HG2_KR2 53 24223 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_50G_HG2_X2 54 24224 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_50G_CR4 56 24225 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_50G_KR4 57 24226 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_50G_X4 58 24227 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_50G_HG2_CR4 60 24228 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_50G_HG2_KR4 61 24229 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_50G_HG2_X4 62 24230 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_100G_CR4 64 24231 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_100G_KR4 65 24232 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_100G_X4 66 24233 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_100G_HG2_CR4 68 24234 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_100G_HG2_KR4 69 24235 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_100G_HG2_X4 70 24236 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_CL73_20GVCO 72 24237 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_CL73_25GVCO 80 24238 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_CL36_20GVCO 88 24239 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_CL36_25GVCO 96 24240 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_25G_CR_IEEE 112 24241 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_25G_CRS_IEEE 113 24242 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_25G_KR_IEEE 114 24243 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_S_25G_KRS_IEEE 115 24244 24245 /* sc_x1_speed_override0 :: override_speed :: reserved0 [07:06] */ 24246 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_RESERVED0_MASK 0x00c0 24247 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_RESERVED0_ALIGN 0 24248 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_RESERVED0_BITS 2 24249 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_RESERVED0_SHIFT 6 24250 24251 /* sc_x1_speed_override0 :: override_speed :: cl36rx_en [05:05] */ 24252 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_CL36RX_EN_MASK 0x0020 24253 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_CL36RX_EN_ALIGN 0 24254 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_CL36RX_EN_BITS 1 24255 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_CL36RX_EN_SHIFT 5 24256 24257 /* sc_x1_speed_override0 :: override_speed :: cl36tx_en [04:04] */ 24258 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_CL36TX_EN_MASK 0x0010 24259 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_CL36TX_EN_ALIGN 0 24260 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_CL36TX_EN_BITS 1 24261 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_CL36TX_EN_SHIFT 4 24262 24263 /* sc_x1_speed_override0 :: override_speed :: t_pma_40b_mode [03:03] */ 24264 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_T_PMA_40B_MODE_MASK 0x0008 24265 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_T_PMA_40B_MODE_ALIGN 0 24266 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_T_PMA_40B_MODE_BITS 1 24267 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_T_PMA_40B_MODE_SHIFT 3 24268 24269 /* sc_x1_speed_override0 :: override_speed :: num_lanes [02:00] */ 24270 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_NUM_LANES_MASK 0x0007 24271 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_NUM_LANES_ALIGN 0 24272 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_NUM_LANES_BITS 3 24273 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_NUM_LANES_SHIFT 0 24274 24275 24276 /**************************************************************************** 24277 * sc_x1_speed_override0 :: override_0 24278 */ 24279 /* sc_x1_speed_override0 :: override_0 :: cl72_en [15:15] */ 24280 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_CL72_EN_MASK 0x8000 24281 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_CL72_EN_ALIGN 0 24282 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_CL72_EN_BITS 1 24283 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_CL72_EN_SHIFT 15 24284 24285 /* sc_x1_speed_override0 :: override_0 :: os_mode [14:11] */ 24286 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_OS_MODE_MASK 0x7800 24287 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_OS_MODE_ALIGN 0 24288 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_OS_MODE_BITS 4 24289 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_OS_MODE_SHIFT 11 24290 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_OS_MODE_OS_MODE_1 0 24291 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_OS_MODE_OS_MODE_2 1 24292 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_OS_MODE_OS_MODE_4 2 24293 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_OS_MODE_OS_MODE_16p5 8 24294 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_OS_MODE_OS_MODE_20p625 12 24295 24296 /* sc_x1_speed_override0 :: override_0 :: t_fifo_mode [10:09] */ 24297 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_T_FIFO_MODE_MASK 0x0600 24298 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_T_FIFO_MODE_ALIGN 0 24299 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_T_FIFO_MODE_BITS 2 24300 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_T_FIFO_MODE_SHIFT 9 24301 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_T_FIFO_MODE_T_FIFO_INSERT_NO_AM 0 24302 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_T_FIFO_MODE_T_FIFO_INSERT_4_AM 1 24303 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_T_FIFO_MODE_T_FIFO_INSERT_20_AM 2 24304 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_T_FIFO_MODE_T_FIFO_INSERT_2_AM 3 24305 24306 /* sc_x1_speed_override0 :: override_0 :: t_enc_mode [08:07] */ 24307 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_T_ENC_MODE_MASK 0x0180 24308 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_T_ENC_MODE_ALIGN 0 24309 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_T_ENC_MODE_BITS 2 24310 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_T_ENC_MODE_SHIFT 7 24311 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_T_ENC_MODE_T_ENC_MODE_BYPASS 0 24312 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_T_ENC_MODE_T_ENC_MODE_CL49 1 24313 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_T_ENC_MODE_T_ENC_MODE_CL82 2 24314 24315 /* sc_x1_speed_override0 :: override_0 :: t_HG2_ENABLE [06:06] */ 24316 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_T_HG2_ENABLE_MASK 0x0040 24317 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_T_HG2_ENABLE_ALIGN 0 24318 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_T_HG2_ENABLE_BITS 1 24319 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_T_HG2_ENABLE_SHIFT 6 24320 24321 /* sc_x1_speed_override0 :: override_0 :: t_pma_btmx_mode [05:04] */ 24322 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_T_PMA_BTMX_MODE_MASK 0x0030 24323 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_T_PMA_BTMX_MODE_ALIGN 0 24324 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_T_PMA_BTMX_MODE_BITS 2 24325 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_T_PMA_BTMX_MODE_SHIFT 4 24326 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_T_PMA_BTMX_MODE_BS_BTMX_MODE_1to1 0 24327 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_T_PMA_BTMX_MODE_BS_BTMX_MODE_2to1 1 24328 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_T_PMA_BTMX_MODE_BS_BTMX_MODE_5to1 2 24329 24330 /* sc_x1_speed_override0 :: override_0 :: scr_mode [03:01] */ 24331 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_SCR_MODE_MASK 0x000e 24332 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_SCR_MODE_ALIGN 0 24333 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_SCR_MODE_BITS 3 24334 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_SCR_MODE_SHIFT 1 24335 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_SCR_MODE_T_SCR_MODE_BYPASS 0 24336 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_SCR_MODE_T_SCR_MODE_CL49 1 24337 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_SCR_MODE_T_SCR_MODE_40G_2_LANE 2 24338 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_SCR_MODE_T_SCR_MODE_100G 3 24339 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_SCR_MODE_T_SCR_MODE_20G 4 24340 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_SCR_MODE_T_SCR_MODE_40G_4_LANE 5 24341 24342 /* sc_x1_speed_override0 :: override_0 :: reserved0 [00:00] */ 24343 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_RESERVED0_MASK 0x0001 24344 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_RESERVED0_ALIGN 0 24345 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_RESERVED0_BITS 1 24346 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_RESERVED0_SHIFT 0 24347 24348 24349 /**************************************************************************** 24350 * sc_x1_speed_override0 :: override_1 24351 */ 24352 /* sc_x1_speed_override0 :: override_1 :: descr_mode [15:14] */ 24353 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_DESCR_MODE_MASK 0xc000 24354 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_DESCR_MODE_ALIGN 0 24355 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_DESCR_MODE_BITS 2 24356 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_DESCR_MODE_SHIFT 14 24357 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_DESCR_MODE_R_DESCR_MODE_BYPASS 0 24358 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_DESCR_MODE_R_DESCR_MODE_CL49 1 24359 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_DESCR_MODE_R_DESCR_MODE_CL82 2 24360 24361 /* sc_x1_speed_override0 :: override_1 :: dec_tl_mode [13:12] */ 24362 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_DEC_TL_MODE_MASK 0x3000 24363 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_DEC_TL_MODE_ALIGN 0 24364 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_DEC_TL_MODE_BITS 2 24365 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_DEC_TL_MODE_SHIFT 12 24366 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_DEC_TL_MODE_R_DEC_TL_MODE_BYPASS 0 24367 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_DEC_TL_MODE_R_DEC_TL_MODE_CL49 1 24368 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_DEC_TL_MODE_R_DEC_TL_MODE_CL82 2 24369 24370 /* sc_x1_speed_override0 :: override_1 :: deskew_mode [11:08] */ 24371 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_DESKEW_MODE_MASK 0x0f00 24372 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_DESKEW_MODE_ALIGN 0 24373 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_DESKEW_MODE_BITS 4 24374 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_DESKEW_MODE_SHIFT 8 24375 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_DESKEW_MODE_R_DESKEW_MODE_BYPASS 0 24376 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_DESKEW_MODE_R_DESKEW_MODE_20G 1 24377 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_DESKEW_MODE_R_DESKEW_MODE_40G_4_LANE 2 24378 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_DESKEW_MODE_R_DESKEW_MODE_40G_2_LANE 3 24379 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_DESKEW_MODE_R_DESKEW_MODE_100G 4 24380 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_DESKEW_MODE_R_DESKEW_MODE_CL49 5 24381 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_DESKEW_MODE_R_DESKEW_MODE_CL91_QUAD 6 24382 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_DESKEW_MODE_R_DESKEW_MODE_CL91_SINGLE_BRCM 7 24383 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_DESKEW_MODE_R_DESKEW_MODE_CL91_DUAL_BRCM 8 24384 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_DESKEW_MODE_R_DESKEW_MODE_CL91_FC 9 24385 24386 /* sc_x1_speed_override0 :: override_1 :: dec_fsm_mode [07:06] */ 24387 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_DEC_FSM_MODE_MASK 0x00c0 24388 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_DEC_FSM_MODE_ALIGN 0 24389 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_DEC_FSM_MODE_BITS 2 24390 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_DEC_FSM_MODE_SHIFT 6 24391 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_DEC_FSM_MODE_R_DEC_FSM_MODE_BYPASS 0 24392 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_DEC_FSM_MODE_R_DEC_FSM_MODE_CL49 1 24393 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_DEC_FSM_MODE_R_DEC_FSM_MODE_CL82 2 24394 24395 /* sc_x1_speed_override0 :: override_1 :: bs_sm_sync_mode [05:05] */ 24396 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_BS_SM_SYNC_MODE_MASK 0x0020 24397 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_BS_SM_SYNC_MODE_ALIGN 0 24398 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_BS_SM_SYNC_MODE_BITS 1 24399 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_BS_SM_SYNC_MODE_SHIFT 5 24400 24401 /* sc_x1_speed_override0 :: override_1 :: bs_sync_en [04:04] */ 24402 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_BS_SYNC_EN_MASK 0x0010 24403 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_BS_SYNC_EN_ALIGN 0 24404 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_BS_SYNC_EN_BITS 1 24405 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_BS_SYNC_EN_SHIFT 4 24406 24407 /* sc_x1_speed_override0 :: override_1 :: bs_dist_mode [03:02] */ 24408 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_BS_DIST_MODE_MASK 0x000c 24409 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_BS_DIST_MODE_ALIGN 0 24410 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_BS_DIST_MODE_BITS 2 24411 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_BS_DIST_MODE_SHIFT 2 24412 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_BS_DIST_MODE_BS_DIST_MODE_5_LANE_TDM 0 24413 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_BS_DIST_MODE_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 24414 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_BS_DIST_MODE_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 24415 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_BS_DIST_MODE_BS_DIST_MODE_NO_TDM 3 24416 24417 /* sc_x1_speed_override0 :: override_1 :: bs_btmx_mode [01:00] */ 24418 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_BS_BTMX_MODE_MASK 0x0003 24419 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_BS_BTMX_MODE_ALIGN 0 24420 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_BS_BTMX_MODE_BITS 2 24421 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_BS_BTMX_MODE_SHIFT 0 24422 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_BS_BTMX_MODE_BS_BTMX_MODE_1to1 0 24423 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_BS_BTMX_MODE_BS_BTMX_MODE_2to1 1 24424 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_BS_BTMX_MODE_BS_BTMX_MODE_5to1 2 24425 24426 24427 /**************************************************************************** 24428 * sc_x1_speed_override0 :: override_2 24429 */ 24430 /* sc_x1_speed_override0 :: override_2 :: reserved0 [15:14] */ 24431 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_2_RESERVED0_MASK 0xc000 24432 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_2_RESERVED0_ALIGN 0 24433 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_2_RESERVED0_BITS 2 24434 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_2_RESERVED0_SHIFT 14 24435 24436 /* sc_x1_speed_override0 :: override_2 :: clockcnt0 [13:00] */ 24437 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_2_CLOCKCNT0_MASK 0x3fff 24438 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_2_CLOCKCNT0_ALIGN 0 24439 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_2_CLOCKCNT0_BITS 14 24440 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_2_CLOCKCNT0_SHIFT 0 24441 24442 24443 /**************************************************************************** 24444 * sc_x1_speed_override0 :: override_3 24445 */ 24446 /* sc_x1_speed_override0 :: override_3 :: reserved0 [15:08] */ 24447 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_3_RESERVED0_MASK 0xff00 24448 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_3_RESERVED0_ALIGN 0 24449 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_3_RESERVED0_BITS 8 24450 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_3_RESERVED0_SHIFT 8 24451 24452 /* sc_x1_speed_override0 :: override_3 :: clockcnt1 [07:00] */ 24453 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_3_CLOCKCNT1_MASK 0x00ff 24454 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_3_CLOCKCNT1_ALIGN 0 24455 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_3_CLOCKCNT1_BITS 8 24456 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_3_CLOCKCNT1_SHIFT 0 24457 24458 24459 /**************************************************************************** 24460 * sc_x1_speed_override0 :: override_4 24461 */ 24462 /* sc_x1_speed_override0 :: override_4 :: reserved0 [15:14] */ 24463 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_4_RESERVED0_MASK 0xc000 24464 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_4_RESERVED0_ALIGN 0 24465 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_4_RESERVED0_BITS 2 24466 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_4_RESERVED0_SHIFT 14 24467 24468 /* sc_x1_speed_override0 :: override_4 :: loopcnt0 [13:06] */ 24469 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_4_LOOPCNT0_MASK 0x3fc0 24470 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_4_LOOPCNT0_ALIGN 0 24471 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_4_LOOPCNT0_BITS 8 24472 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_4_LOOPCNT0_SHIFT 6 24473 24474 /* sc_x1_speed_override0 :: override_4 :: loopcnt1 [05:00] */ 24475 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_4_LOOPCNT1_MASK 0x003f 24476 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_4_LOOPCNT1_ALIGN 0 24477 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_4_LOOPCNT1_BITS 6 24478 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_4_LOOPCNT1_SHIFT 0 24479 24480 24481 /**************************************************************************** 24482 * sc_x1_speed_override0 :: override_5 24483 */ 24484 /* sc_x1_speed_override0 :: override_5 :: reserved0 [15:13] */ 24485 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_5_RESERVED0_MASK 0xe000 24486 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_5_RESERVED0_ALIGN 0 24487 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_5_RESERVED0_BITS 3 24488 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_5_RESERVED0_SHIFT 13 24489 24490 /* sc_x1_speed_override0 :: override_5 :: mac_creditgencnt [12:00] */ 24491 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_5_MAC_CREDITGENCNT_MASK 0x1fff 24492 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_5_MAC_CREDITGENCNT_ALIGN 0 24493 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_5_MAC_CREDITGENCNT_BITS 13 24494 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_5_MAC_CREDITGENCNT_SHIFT 0 24495 24496 24497 /**************************************************************************** 24498 * sc_x1_speed_override0 :: override_6 24499 */ 24500 /* sc_x1_speed_override0 :: override_6 :: reserved0 [15:11] */ 24501 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_6_RESERVED0_MASK 0xf800 24502 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_6_RESERVED0_ALIGN 0 24503 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_6_RESERVED0_BITS 5 24504 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_6_RESERVED0_SHIFT 11 24505 24506 /* sc_x1_speed_override0 :: override_6 :: AM_spacing_mul [10:09] */ 24507 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_6_AM_SPACING_MUL_MASK 0x0600 24508 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_6_AM_SPACING_MUL_ALIGN 0 24509 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_6_AM_SPACING_MUL_BITS 2 24510 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_6_AM_SPACING_MUL_SHIFT 9 24511 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_6_AM_SPACING_MUL_AM_SPACING_MUL_2 0 24512 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_6_AM_SPACING_MUL_AM_SPACING_MUL_4 1 24513 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_6_AM_SPACING_MUL_AM_SPACING_MUL_5 2 24514 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_6_AM_SPACING_MUL_AM_SPACING_MUL_20 3 24515 24516 /* sc_x1_speed_override0 :: override_6 :: t_pma_bitmux_delay [08:07] */ 24517 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_6_T_PMA_BITMUX_DELAY_MASK 0x0180 24518 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_6_T_PMA_BITMUX_DELAY_ALIGN 0 24519 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_6_T_PMA_BITMUX_DELAY_BITS 2 24520 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_6_T_PMA_BITMUX_DELAY_SHIFT 7 24521 24522 /* sc_x1_speed_override0 :: override_6 :: t_pma_watermark [06:03] */ 24523 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_6_T_PMA_WATERMARK_MASK 0x0078 24524 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_6_T_PMA_WATERMARK_ALIGN 0 24525 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_6_T_PMA_WATERMARK_BITS 4 24526 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_6_T_PMA_WATERMARK_SHIFT 3 24527 24528 /* sc_x1_speed_override0 :: override_6 :: t_pma_cl91_mux_sel [02:02] */ 24529 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_6_T_PMA_CL91_MUX_SEL_MASK 0x0004 24530 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_6_T_PMA_CL91_MUX_SEL_ALIGN 0 24531 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_6_T_PMA_CL91_MUX_SEL_BITS 1 24532 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_6_T_PMA_CL91_MUX_SEL_SHIFT 2 24533 24534 /* sc_x1_speed_override0 :: override_6 :: t_five_bit_xor_en [01:01] */ 24535 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_6_T_FIVE_BIT_XOR_EN_MASK 0x0002 24536 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_6_T_FIVE_BIT_XOR_EN_ALIGN 0 24537 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_6_T_FIVE_BIT_XOR_EN_BITS 1 24538 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_6_T_FIVE_BIT_XOR_EN_SHIFT 1 24539 24540 /* sc_x1_speed_override0 :: override_6 :: t_cl91_cw_scramble [00:00] */ 24541 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_6_T_CL91_CW_SCRAMBLE_MASK 0x0001 24542 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_6_T_CL91_CW_SCRAMBLE_ALIGN 0 24543 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_6_T_CL91_CW_SCRAMBLE_BITS 1 24544 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_6_T_CL91_CW_SCRAMBLE_SHIFT 0 24545 24546 24547 /**************************************************************************** 24548 * sc_x1_speed_override0 :: override_7 24549 */ 24550 /* sc_x1_speed_override0 :: override_7 :: reserved0 [15:14] */ 24551 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_RESERVED0_MASK 0xc000 24552 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_RESERVED0_ALIGN 0 24553 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_RESERVED0_BITS 2 24554 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_RESERVED0_SHIFT 14 24555 24556 /* sc_x1_speed_override0 :: override_7 :: r_HG2_ENABLE [13:13] */ 24557 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_R_HG2_ENABLE_MASK 0x2000 24558 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_R_HG2_ENABLE_ALIGN 0 24559 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_R_HG2_ENABLE_BITS 1 24560 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_R_HG2_ENABLE_SHIFT 13 24561 24562 /* sc_x1_speed_override0 :: override_7 :: r_tc_out_mode [12:11] */ 24563 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_R_TC_OUT_MODE_MASK 0x1800 24564 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_R_TC_OUT_MODE_ALIGN 0 24565 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_R_TC_OUT_MODE_BITS 2 24566 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_R_TC_OUT_MODE_SHIFT 11 24567 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_R_TC_OUT_MODE_R_TC_OUT_MODE_SINGLE 0 24568 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_R_TC_OUT_MODE_R_TC_OUT_MODE_DUAL 1 24569 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_R_TC_OUT_MODE_R_TC_OUT_MODE_QUAD 2 24570 24571 /* sc_x1_speed_override0 :: override_7 :: r_five_bit_xor_en [10:10] */ 24572 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_R_FIVE_BIT_XOR_EN_MASK 0x0400 24573 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_R_FIVE_BIT_XOR_EN_ALIGN 0 24574 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_R_FIVE_BIT_XOR_EN_BITS 1 24575 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_R_FIVE_BIT_XOR_EN_SHIFT 10 24576 24577 /* sc_x1_speed_override0 :: override_7 :: r_tc_mode [09:08] */ 24578 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_R_TC_MODE_MASK 0x0300 24579 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_R_TC_MODE_ALIGN 0 24580 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_R_TC_MODE_BITS 2 24581 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_R_TC_MODE_SHIFT 8 24582 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_R_TC_MODE_R_TC_MODE_SINGLE 0 24583 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_R_TC_MODE_R_TC_MODE_DUAL 1 24584 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_R_TC_MODE_R_TC_MODE_QUAD 2 24585 24586 /* sc_x1_speed_override0 :: override_7 :: r_tc_in_mode [07:07] */ 24587 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_R_TC_IN_MODE_MASK 0x0080 24588 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_R_TC_IN_MODE_ALIGN 0 24589 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_R_TC_IN_MODE_BITS 1 24590 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_R_TC_IN_MODE_SHIFT 7 24591 24592 /* sc_x1_speed_override0 :: override_7 :: r_cl91_cw_scramble [06:06] */ 24593 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_R_CL91_CW_SCRAMBLE_MASK 0x0040 24594 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_R_CL91_CW_SCRAMBLE_ALIGN 0 24595 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_R_CL91_CW_SCRAMBLE_BITS 1 24596 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_R_CL91_CW_SCRAMBLE_SHIFT 6 24597 24598 /* sc_x1_speed_override0 :: override_7 :: r_merge_mode [05:03] */ 24599 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_R_MERGE_MODE_MASK 0x0038 24600 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_R_MERGE_MODE_ALIGN 0 24601 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_R_MERGE_MODE_BITS 3 24602 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_R_MERGE_MODE_SHIFT 3 24603 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_R_MERGE_MODE_R_MERGE_MODE_BYPASS 0 24604 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_R_MERGE_MODE_R_MERGE_MODE_CL91_FC 1 24605 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_R_MERGE_MODE_R_MERGE_MODE_CL91_SINGLE_LANE 2 24606 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_R_MERGE_MODE_R_MERGE_MODE_CL91_DUAL_LANE 3 24607 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_R_MERGE_MODE_R_MERGE_MODE_CL91_QUAD_LANE 4 24608 24609 /* sc_x1_speed_override0 :: override_7 :: cl91_blksync_mode [02:00] */ 24610 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_CL91_BLKSYNC_MODE_MASK 0x0007 24611 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_CL91_BLKSYNC_MODE_ALIGN 0 24612 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_CL91_BLKSYNC_MODE_BITS 3 24613 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_CL91_BLKSYNC_MODE_SHIFT 0 24614 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_CL91_BLKSYNC_MODE_R_BLKSYNC_NO_CL91_FEC 0 24615 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_CL91_BLKSYNC_MODE_R_BLKSYNC_CL91_QUAD_LANE_FEC 1 24616 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_CL91_BLKSYNC_MODE_R_BLKSYNC_CL91_DUAL_LANE_FEC 2 24617 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_CL91_BLKSYNC_MODE_R_BLKSYNC_CL91_SINGLE_LANE_FEC 3 24618 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_CL91_BLKSYNC_MODE_R_BLKSYNC_CL91_FC_FEC 4 24619 24620 24621 /**************************************************************************** 24622 * TSC_WC4_TSC_USER1_sc_x1_speed_override1 24623 */ 24624 /**************************************************************************** 24625 * sc_x1_speed_override1 :: override_speed 24626 */ 24627 /* sc_x1_speed_override1 :: override_speed :: speed [15:08] */ 24628 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_MASK 0xff00 24629 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_ALIGN 0 24630 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_BITS 8 24631 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_SHIFT 8 24632 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_10G_CR1 0 24633 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_10G_KR1 1 24634 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_10G_X1 2 24635 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_10G_HG2_CR1 4 24636 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_10G_HG2_KR1 5 24637 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_10G_HG2_X1 6 24638 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_20G_CR1 8 24639 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_20G_KR1 9 24640 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_20G_X1 10 24641 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_20G_HG2_CR1 12 24642 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_20G_HG2_KR1 13 24643 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_20G_HG2_X1 14 24644 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_25G_CR1 16 24645 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_25G_KR1 17 24646 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_25G_X1 18 24647 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_25G_HG2_CR1 20 24648 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_25G_HG2_KR1 21 24649 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_25G_HG2_X1 22 24650 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_20G_CR2 24 24651 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_20G_KR2 25 24652 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_20G_X2 26 24653 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_20G_HG2_CR2 28 24654 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_20G_HG2_KR2 29 24655 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_20G_HG2_X2 30 24656 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_40G_CR2 32 24657 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_40G_KR2 33 24658 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_40G_X2 34 24659 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_40G_HG2_CR2 36 24660 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_40G_HG2_KR2 37 24661 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_40G_HG2_X2 38 24662 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_40G_CR4 40 24663 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_40G_KR4 41 24664 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_40G_X4 42 24665 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_40G_HG2_CR4 44 24666 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_40G_HG2_KR4 45 24667 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_40G_HG2_X4 46 24668 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_50G_CR2 48 24669 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_50G_KR2 49 24670 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_50G_X2 50 24671 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_50G_HG2_CR2 52 24672 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_50G_HG2_KR2 53 24673 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_50G_HG2_X2 54 24674 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_50G_CR4 56 24675 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_50G_KR4 57 24676 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_50G_X4 58 24677 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_50G_HG2_CR4 60 24678 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_50G_HG2_KR4 61 24679 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_50G_HG2_X4 62 24680 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_100G_CR4 64 24681 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_100G_KR4 65 24682 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_100G_X4 66 24683 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_100G_HG2_CR4 68 24684 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_100G_HG2_KR4 69 24685 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_100G_HG2_X4 70 24686 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_CL73_20GVCO 72 24687 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_CL73_25GVCO 80 24688 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_CL36_20GVCO 88 24689 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_CL36_25GVCO 96 24690 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_25G_CR_IEEE 112 24691 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_25G_CRS_IEEE 113 24692 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_25G_KR_IEEE 114 24693 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_S_25G_KRS_IEEE 115 24694 24695 /* sc_x1_speed_override1 :: override_speed :: reserved0 [07:06] */ 24696 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_RESERVED0_MASK 0x00c0 24697 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_RESERVED0_ALIGN 0 24698 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_RESERVED0_BITS 2 24699 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_RESERVED0_SHIFT 6 24700 24701 /* sc_x1_speed_override1 :: override_speed :: cl36rx_en [05:05] */ 24702 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_CL36RX_EN_MASK 0x0020 24703 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_CL36RX_EN_ALIGN 0 24704 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_CL36RX_EN_BITS 1 24705 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_CL36RX_EN_SHIFT 5 24706 24707 /* sc_x1_speed_override1 :: override_speed :: cl36tx_en [04:04] */ 24708 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_CL36TX_EN_MASK 0x0010 24709 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_CL36TX_EN_ALIGN 0 24710 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_CL36TX_EN_BITS 1 24711 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_CL36TX_EN_SHIFT 4 24712 24713 /* sc_x1_speed_override1 :: override_speed :: t_pma_40b_mode [03:03] */ 24714 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_T_PMA_40B_MODE_MASK 0x0008 24715 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_T_PMA_40B_MODE_ALIGN 0 24716 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_T_PMA_40B_MODE_BITS 1 24717 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_T_PMA_40B_MODE_SHIFT 3 24718 24719 /* sc_x1_speed_override1 :: override_speed :: num_lanes [02:00] */ 24720 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_NUM_LANES_MASK 0x0007 24721 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_NUM_LANES_ALIGN 0 24722 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_NUM_LANES_BITS 3 24723 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_NUM_LANES_SHIFT 0 24724 24725 24726 /**************************************************************************** 24727 * sc_x1_speed_override1 :: override_0 24728 */ 24729 /* sc_x1_speed_override1 :: override_0 :: cl72_en [15:15] */ 24730 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_CL72_EN_MASK 0x8000 24731 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_CL72_EN_ALIGN 0 24732 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_CL72_EN_BITS 1 24733 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_CL72_EN_SHIFT 15 24734 24735 /* sc_x1_speed_override1 :: override_0 :: os_mode [14:11] */ 24736 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_OS_MODE_MASK 0x7800 24737 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_OS_MODE_ALIGN 0 24738 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_OS_MODE_BITS 4 24739 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_OS_MODE_SHIFT 11 24740 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_OS_MODE_OS_MODE_1 0 24741 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_OS_MODE_OS_MODE_2 1 24742 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_OS_MODE_OS_MODE_4 2 24743 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_OS_MODE_OS_MODE_16p5 8 24744 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_OS_MODE_OS_MODE_20p625 12 24745 24746 /* sc_x1_speed_override1 :: override_0 :: t_fifo_mode [10:09] */ 24747 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_T_FIFO_MODE_MASK 0x0600 24748 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_T_FIFO_MODE_ALIGN 0 24749 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_T_FIFO_MODE_BITS 2 24750 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_T_FIFO_MODE_SHIFT 9 24751 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_T_FIFO_MODE_T_FIFO_INSERT_NO_AM 0 24752 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_T_FIFO_MODE_T_FIFO_INSERT_4_AM 1 24753 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_T_FIFO_MODE_T_FIFO_INSERT_20_AM 2 24754 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_T_FIFO_MODE_T_FIFO_INSERT_2_AM 3 24755 24756 /* sc_x1_speed_override1 :: override_0 :: t_enc_mode [08:07] */ 24757 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_T_ENC_MODE_MASK 0x0180 24758 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_T_ENC_MODE_ALIGN 0 24759 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_T_ENC_MODE_BITS 2 24760 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_T_ENC_MODE_SHIFT 7 24761 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_T_ENC_MODE_T_ENC_MODE_BYPASS 0 24762 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_T_ENC_MODE_T_ENC_MODE_CL49 1 24763 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_T_ENC_MODE_T_ENC_MODE_CL82 2 24764 24765 /* sc_x1_speed_override1 :: override_0 :: t_HG2_ENABLE [06:06] */ 24766 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_T_HG2_ENABLE_MASK 0x0040 24767 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_T_HG2_ENABLE_ALIGN 0 24768 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_T_HG2_ENABLE_BITS 1 24769 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_T_HG2_ENABLE_SHIFT 6 24770 24771 /* sc_x1_speed_override1 :: override_0 :: t_pma_btmx_mode [05:04] */ 24772 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_T_PMA_BTMX_MODE_MASK 0x0030 24773 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_T_PMA_BTMX_MODE_ALIGN 0 24774 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_T_PMA_BTMX_MODE_BITS 2 24775 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_T_PMA_BTMX_MODE_SHIFT 4 24776 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_T_PMA_BTMX_MODE_BS_BTMX_MODE_1to1 0 24777 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_T_PMA_BTMX_MODE_BS_BTMX_MODE_2to1 1 24778 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_T_PMA_BTMX_MODE_BS_BTMX_MODE_5to1 2 24779 24780 /* sc_x1_speed_override1 :: override_0 :: scr_mode [03:01] */ 24781 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_SCR_MODE_MASK 0x000e 24782 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_SCR_MODE_ALIGN 0 24783 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_SCR_MODE_BITS 3 24784 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_SCR_MODE_SHIFT 1 24785 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_SCR_MODE_T_SCR_MODE_BYPASS 0 24786 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_SCR_MODE_T_SCR_MODE_CL49 1 24787 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_SCR_MODE_T_SCR_MODE_40G_2_LANE 2 24788 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_SCR_MODE_T_SCR_MODE_100G 3 24789 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_SCR_MODE_T_SCR_MODE_20G 4 24790 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_SCR_MODE_T_SCR_MODE_40G_4_LANE 5 24791 24792 /* sc_x1_speed_override1 :: override_0 :: reserved0 [00:00] */ 24793 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_RESERVED0_MASK 0x0001 24794 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_RESERVED0_ALIGN 0 24795 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_RESERVED0_BITS 1 24796 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_RESERVED0_SHIFT 0 24797 24798 24799 /**************************************************************************** 24800 * sc_x1_speed_override1 :: override_1 24801 */ 24802 /* sc_x1_speed_override1 :: override_1 :: descr_mode [15:14] */ 24803 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_DESCR_MODE_MASK 0xc000 24804 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_DESCR_MODE_ALIGN 0 24805 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_DESCR_MODE_BITS 2 24806 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_DESCR_MODE_SHIFT 14 24807 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_DESCR_MODE_R_DESCR_MODE_BYPASS 0 24808 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_DESCR_MODE_R_DESCR_MODE_CL49 1 24809 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_DESCR_MODE_R_DESCR_MODE_CL82 2 24810 24811 /* sc_x1_speed_override1 :: override_1 :: dec_tl_mode [13:12] */ 24812 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_DEC_TL_MODE_MASK 0x3000 24813 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_DEC_TL_MODE_ALIGN 0 24814 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_DEC_TL_MODE_BITS 2 24815 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_DEC_TL_MODE_SHIFT 12 24816 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_DEC_TL_MODE_R_DEC_TL_MODE_BYPASS 0 24817 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_DEC_TL_MODE_R_DEC_TL_MODE_CL49 1 24818 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_DEC_TL_MODE_R_DEC_TL_MODE_CL82 2 24819 24820 /* sc_x1_speed_override1 :: override_1 :: deskew_mode [11:08] */ 24821 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_DESKEW_MODE_MASK 0x0f00 24822 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_DESKEW_MODE_ALIGN 0 24823 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_DESKEW_MODE_BITS 4 24824 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_DESKEW_MODE_SHIFT 8 24825 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_DESKEW_MODE_R_DESKEW_MODE_BYPASS 0 24826 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_DESKEW_MODE_R_DESKEW_MODE_20G 1 24827 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_DESKEW_MODE_R_DESKEW_MODE_40G_4_LANE 2 24828 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_DESKEW_MODE_R_DESKEW_MODE_40G_2_LANE 3 24829 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_DESKEW_MODE_R_DESKEW_MODE_100G 4 24830 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_DESKEW_MODE_R_DESKEW_MODE_CL49 5 24831 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_DESKEW_MODE_R_DESKEW_MODE_CL91_QUAD 6 24832 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_DESKEW_MODE_R_DESKEW_MODE_CL91_SINGLE_BRCM 7 24833 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_DESKEW_MODE_R_DESKEW_MODE_CL91_DUAL_BRCM 8 24834 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_DESKEW_MODE_R_DESKEW_MODE_CL91_FC 9 24835 24836 /* sc_x1_speed_override1 :: override_1 :: dec_fsm_mode [07:06] */ 24837 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_DEC_FSM_MODE_MASK 0x00c0 24838 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_DEC_FSM_MODE_ALIGN 0 24839 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_DEC_FSM_MODE_BITS 2 24840 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_DEC_FSM_MODE_SHIFT 6 24841 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_DEC_FSM_MODE_R_DEC_FSM_MODE_BYPASS 0 24842 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_DEC_FSM_MODE_R_DEC_FSM_MODE_CL49 1 24843 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_DEC_FSM_MODE_R_DEC_FSM_MODE_CL82 2 24844 24845 /* sc_x1_speed_override1 :: override_1 :: bs_sm_sync_mode [05:05] */ 24846 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_BS_SM_SYNC_MODE_MASK 0x0020 24847 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_BS_SM_SYNC_MODE_ALIGN 0 24848 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_BS_SM_SYNC_MODE_BITS 1 24849 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_BS_SM_SYNC_MODE_SHIFT 5 24850 24851 /* sc_x1_speed_override1 :: override_1 :: bs_sync_en [04:04] */ 24852 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_BS_SYNC_EN_MASK 0x0010 24853 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_BS_SYNC_EN_ALIGN 0 24854 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_BS_SYNC_EN_BITS 1 24855 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_BS_SYNC_EN_SHIFT 4 24856 24857 /* sc_x1_speed_override1 :: override_1 :: bs_dist_mode [03:02] */ 24858 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_BS_DIST_MODE_MASK 0x000c 24859 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_BS_DIST_MODE_ALIGN 0 24860 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_BS_DIST_MODE_BITS 2 24861 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_BS_DIST_MODE_SHIFT 2 24862 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_BS_DIST_MODE_BS_DIST_MODE_5_LANE_TDM 0 24863 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_BS_DIST_MODE_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 24864 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_BS_DIST_MODE_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 24865 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_BS_DIST_MODE_BS_DIST_MODE_NO_TDM 3 24866 24867 /* sc_x1_speed_override1 :: override_1 :: bs_btmx_mode [01:00] */ 24868 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_BS_BTMX_MODE_MASK 0x0003 24869 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_BS_BTMX_MODE_ALIGN 0 24870 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_BS_BTMX_MODE_BITS 2 24871 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_BS_BTMX_MODE_SHIFT 0 24872 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_BS_BTMX_MODE_BS_BTMX_MODE_1to1 0 24873 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_BS_BTMX_MODE_BS_BTMX_MODE_2to1 1 24874 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_BS_BTMX_MODE_BS_BTMX_MODE_5to1 2 24875 24876 24877 /**************************************************************************** 24878 * sc_x1_speed_override1 :: override_2 24879 */ 24880 /* sc_x1_speed_override1 :: override_2 :: reserved0 [15:14] */ 24881 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_2_RESERVED0_MASK 0xc000 24882 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_2_RESERVED0_ALIGN 0 24883 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_2_RESERVED0_BITS 2 24884 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_2_RESERVED0_SHIFT 14 24885 24886 /* sc_x1_speed_override1 :: override_2 :: clockcnt0 [13:00] */ 24887 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_2_CLOCKCNT0_MASK 0x3fff 24888 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_2_CLOCKCNT0_ALIGN 0 24889 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_2_CLOCKCNT0_BITS 14 24890 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_2_CLOCKCNT0_SHIFT 0 24891 24892 24893 /**************************************************************************** 24894 * sc_x1_speed_override1 :: override_3 24895 */ 24896 /* sc_x1_speed_override1 :: override_3 :: reserved0 [15:08] */ 24897 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_3_RESERVED0_MASK 0xff00 24898 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_3_RESERVED0_ALIGN 0 24899 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_3_RESERVED0_BITS 8 24900 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_3_RESERVED0_SHIFT 8 24901 24902 /* sc_x1_speed_override1 :: override_3 :: clockcnt1 [07:00] */ 24903 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_3_CLOCKCNT1_MASK 0x00ff 24904 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_3_CLOCKCNT1_ALIGN 0 24905 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_3_CLOCKCNT1_BITS 8 24906 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_3_CLOCKCNT1_SHIFT 0 24907 24908 24909 /**************************************************************************** 24910 * sc_x1_speed_override1 :: override_4 24911 */ 24912 /* sc_x1_speed_override1 :: override_4 :: reserved0 [15:14] */ 24913 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_4_RESERVED0_MASK 0xc000 24914 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_4_RESERVED0_ALIGN 0 24915 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_4_RESERVED0_BITS 2 24916 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_4_RESERVED0_SHIFT 14 24917 24918 /* sc_x1_speed_override1 :: override_4 :: loopcnt0 [13:06] */ 24919 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_4_LOOPCNT0_MASK 0x3fc0 24920 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_4_LOOPCNT0_ALIGN 0 24921 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_4_LOOPCNT0_BITS 8 24922 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_4_LOOPCNT0_SHIFT 6 24923 24924 /* sc_x1_speed_override1 :: override_4 :: loopcnt1 [05:00] */ 24925 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_4_LOOPCNT1_MASK 0x003f 24926 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_4_LOOPCNT1_ALIGN 0 24927 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_4_LOOPCNT1_BITS 6 24928 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_4_LOOPCNT1_SHIFT 0 24929 24930 24931 /**************************************************************************** 24932 * sc_x1_speed_override1 :: override_5 24933 */ 24934 /* sc_x1_speed_override1 :: override_5 :: reserved0 [15:13] */ 24935 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_5_RESERVED0_MASK 0xe000 24936 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_5_RESERVED0_ALIGN 0 24937 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_5_RESERVED0_BITS 3 24938 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_5_RESERVED0_SHIFT 13 24939 24940 /* sc_x1_speed_override1 :: override_5 :: mac_creditgencnt [12:00] */ 24941 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_5_MAC_CREDITGENCNT_MASK 0x1fff 24942 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_5_MAC_CREDITGENCNT_ALIGN 0 24943 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_5_MAC_CREDITGENCNT_BITS 13 24944 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_5_MAC_CREDITGENCNT_SHIFT 0 24945 24946 24947 /**************************************************************************** 24948 * sc_x1_speed_override1 :: override_6 24949 */ 24950 /* sc_x1_speed_override1 :: override_6 :: reserved0 [15:11] */ 24951 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_6_RESERVED0_MASK 0xf800 24952 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_6_RESERVED0_ALIGN 0 24953 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_6_RESERVED0_BITS 5 24954 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_6_RESERVED0_SHIFT 11 24955 24956 /* sc_x1_speed_override1 :: override_6 :: AM_spacing_mul [10:09] */ 24957 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_6_AM_SPACING_MUL_MASK 0x0600 24958 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_6_AM_SPACING_MUL_ALIGN 0 24959 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_6_AM_SPACING_MUL_BITS 2 24960 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_6_AM_SPACING_MUL_SHIFT 9 24961 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_6_AM_SPACING_MUL_AM_SPACING_MUL_2 0 24962 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_6_AM_SPACING_MUL_AM_SPACING_MUL_4 1 24963 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_6_AM_SPACING_MUL_AM_SPACING_MUL_5 2 24964 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_6_AM_SPACING_MUL_AM_SPACING_MUL_20 3 24965 24966 /* sc_x1_speed_override1 :: override_6 :: t_pma_bitmux_delay [08:07] */ 24967 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_6_T_PMA_BITMUX_DELAY_MASK 0x0180 24968 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_6_T_PMA_BITMUX_DELAY_ALIGN 0 24969 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_6_T_PMA_BITMUX_DELAY_BITS 2 24970 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_6_T_PMA_BITMUX_DELAY_SHIFT 7 24971 24972 /* sc_x1_speed_override1 :: override_6 :: t_pma_watermark [06:03] */ 24973 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_6_T_PMA_WATERMARK_MASK 0x0078 24974 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_6_T_PMA_WATERMARK_ALIGN 0 24975 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_6_T_PMA_WATERMARK_BITS 4 24976 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_6_T_PMA_WATERMARK_SHIFT 3 24977 24978 /* sc_x1_speed_override1 :: override_6 :: t_pma_cl91_mux_sel [02:02] */ 24979 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_6_T_PMA_CL91_MUX_SEL_MASK 0x0004 24980 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_6_T_PMA_CL91_MUX_SEL_ALIGN 0 24981 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_6_T_PMA_CL91_MUX_SEL_BITS 1 24982 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_6_T_PMA_CL91_MUX_SEL_SHIFT 2 24983 24984 /* sc_x1_speed_override1 :: override_6 :: t_five_bit_xor_en [01:01] */ 24985 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_6_T_FIVE_BIT_XOR_EN_MASK 0x0002 24986 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_6_T_FIVE_BIT_XOR_EN_ALIGN 0 24987 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_6_T_FIVE_BIT_XOR_EN_BITS 1 24988 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_6_T_FIVE_BIT_XOR_EN_SHIFT 1 24989 24990 /* sc_x1_speed_override1 :: override_6 :: t_cl91_cw_scramble [00:00] */ 24991 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_6_T_CL91_CW_SCRAMBLE_MASK 0x0001 24992 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_6_T_CL91_CW_SCRAMBLE_ALIGN 0 24993 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_6_T_CL91_CW_SCRAMBLE_BITS 1 24994 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_6_T_CL91_CW_SCRAMBLE_SHIFT 0 24995 24996 24997 /**************************************************************************** 24998 * sc_x1_speed_override1 :: override_7 24999 */ 25000 /* sc_x1_speed_override1 :: override_7 :: reserved0 [15:14] */ 25001 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_RESERVED0_MASK 0xc000 25002 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_RESERVED0_ALIGN 0 25003 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_RESERVED0_BITS 2 25004 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_RESERVED0_SHIFT 14 25005 25006 /* sc_x1_speed_override1 :: override_7 :: r_HG2_ENABLE [13:13] */ 25007 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_R_HG2_ENABLE_MASK 0x2000 25008 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_R_HG2_ENABLE_ALIGN 0 25009 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_R_HG2_ENABLE_BITS 1 25010 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_R_HG2_ENABLE_SHIFT 13 25011 25012 /* sc_x1_speed_override1 :: override_7 :: r_tc_out_mode [12:11] */ 25013 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_R_TC_OUT_MODE_MASK 0x1800 25014 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_R_TC_OUT_MODE_ALIGN 0 25015 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_R_TC_OUT_MODE_BITS 2 25016 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_R_TC_OUT_MODE_SHIFT 11 25017 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_R_TC_OUT_MODE_R_TC_OUT_MODE_SINGLE 0 25018 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_R_TC_OUT_MODE_R_TC_OUT_MODE_DUAL 1 25019 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_R_TC_OUT_MODE_R_TC_OUT_MODE_QUAD 2 25020 25021 /* sc_x1_speed_override1 :: override_7 :: r_five_bit_xor_en [10:10] */ 25022 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_R_FIVE_BIT_XOR_EN_MASK 0x0400 25023 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_R_FIVE_BIT_XOR_EN_ALIGN 0 25024 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_R_FIVE_BIT_XOR_EN_BITS 1 25025 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_R_FIVE_BIT_XOR_EN_SHIFT 10 25026 25027 /* sc_x1_speed_override1 :: override_7 :: r_tc_mode [09:08] */ 25028 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_R_TC_MODE_MASK 0x0300 25029 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_R_TC_MODE_ALIGN 0 25030 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_R_TC_MODE_BITS 2 25031 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_R_TC_MODE_SHIFT 8 25032 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_R_TC_MODE_R_TC_MODE_SINGLE 0 25033 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_R_TC_MODE_R_TC_MODE_DUAL 1 25034 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_R_TC_MODE_R_TC_MODE_QUAD 2 25035 25036 /* sc_x1_speed_override1 :: override_7 :: r_tc_in_mode [07:07] */ 25037 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_R_TC_IN_MODE_MASK 0x0080 25038 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_R_TC_IN_MODE_ALIGN 0 25039 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_R_TC_IN_MODE_BITS 1 25040 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_R_TC_IN_MODE_SHIFT 7 25041 25042 /* sc_x1_speed_override1 :: override_7 :: r_cl91_cw_scramble [06:06] */ 25043 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_R_CL91_CW_SCRAMBLE_MASK 0x0040 25044 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_R_CL91_CW_SCRAMBLE_ALIGN 0 25045 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_R_CL91_CW_SCRAMBLE_BITS 1 25046 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_R_CL91_CW_SCRAMBLE_SHIFT 6 25047 25048 /* sc_x1_speed_override1 :: override_7 :: r_merge_mode [05:03] */ 25049 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_R_MERGE_MODE_MASK 0x0038 25050 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_R_MERGE_MODE_ALIGN 0 25051 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_R_MERGE_MODE_BITS 3 25052 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_R_MERGE_MODE_SHIFT 3 25053 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_R_MERGE_MODE_R_MERGE_MODE_BYPASS 0 25054 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_R_MERGE_MODE_R_MERGE_MODE_CL91_FC 1 25055 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_R_MERGE_MODE_R_MERGE_MODE_CL91_SINGLE_LANE 2 25056 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_R_MERGE_MODE_R_MERGE_MODE_CL91_DUAL_LANE 3 25057 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_R_MERGE_MODE_R_MERGE_MODE_CL91_QUAD_LANE 4 25058 25059 /* sc_x1_speed_override1 :: override_7 :: cl91_blksync_mode [02:00] */ 25060 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_CL91_BLKSYNC_MODE_MASK 0x0007 25061 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_CL91_BLKSYNC_MODE_ALIGN 0 25062 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_CL91_BLKSYNC_MODE_BITS 3 25063 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_CL91_BLKSYNC_MODE_SHIFT 0 25064 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_CL91_BLKSYNC_MODE_R_BLKSYNC_NO_CL91_FEC 0 25065 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_CL91_BLKSYNC_MODE_R_BLKSYNC_CL91_QUAD_LANE_FEC 1 25066 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_CL91_BLKSYNC_MODE_R_BLKSYNC_CL91_DUAL_LANE_FEC 2 25067 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_CL91_BLKSYNC_MODE_R_BLKSYNC_CL91_SINGLE_LANE_FEC 3 25068 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_CL91_BLKSYNC_MODE_R_BLKSYNC_CL91_FC_FEC 4 25069 25070 25071 /**************************************************************************** 25072 * TSC_WC4_TSC_USER1_sc_x1_speed_override2 25073 */ 25074 /**************************************************************************** 25075 * sc_x1_speed_override2 :: override_speed 25076 */ 25077 /* sc_x1_speed_override2 :: override_speed :: speed [15:08] */ 25078 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_MASK 0xff00 25079 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_ALIGN 0 25080 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_BITS 8 25081 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_SHIFT 8 25082 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_10G_CR1 0 25083 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_10G_KR1 1 25084 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_10G_X1 2 25085 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_10G_HG2_CR1 4 25086 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_10G_HG2_KR1 5 25087 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_10G_HG2_X1 6 25088 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_20G_CR1 8 25089 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_20G_KR1 9 25090 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_20G_X1 10 25091 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_20G_HG2_CR1 12 25092 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_20G_HG2_KR1 13 25093 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_20G_HG2_X1 14 25094 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_25G_CR1 16 25095 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_25G_KR1 17 25096 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_25G_X1 18 25097 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_25G_HG2_CR1 20 25098 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_25G_HG2_KR1 21 25099 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_25G_HG2_X1 22 25100 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_20G_CR2 24 25101 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_20G_KR2 25 25102 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_20G_X2 26 25103 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_20G_HG2_CR2 28 25104 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_20G_HG2_KR2 29 25105 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_20G_HG2_X2 30 25106 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_40G_CR2 32 25107 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_40G_KR2 33 25108 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_40G_X2 34 25109 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_40G_HG2_CR2 36 25110 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_40G_HG2_KR2 37 25111 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_40G_HG2_X2 38 25112 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_40G_CR4 40 25113 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_40G_KR4 41 25114 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_40G_X4 42 25115 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_40G_HG2_CR4 44 25116 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_40G_HG2_KR4 45 25117 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_40G_HG2_X4 46 25118 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_50G_CR2 48 25119 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_50G_KR2 49 25120 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_50G_X2 50 25121 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_50G_HG2_CR2 52 25122 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_50G_HG2_KR2 53 25123 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_50G_HG2_X2 54 25124 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_50G_CR4 56 25125 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_50G_KR4 57 25126 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_50G_X4 58 25127 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_50G_HG2_CR4 60 25128 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_50G_HG2_KR4 61 25129 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_50G_HG2_X4 62 25130 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_100G_CR4 64 25131 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_100G_KR4 65 25132 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_100G_X4 66 25133 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_100G_HG2_CR4 68 25134 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_100G_HG2_KR4 69 25135 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_100G_HG2_X4 70 25136 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_CL73_20GVCO 72 25137 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_CL73_25GVCO 80 25138 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_CL36_20GVCO 88 25139 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_CL36_25GVCO 96 25140 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_25G_CR_IEEE 112 25141 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_25G_CRS_IEEE 113 25142 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_25G_KR_IEEE 114 25143 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_S_25G_KRS_IEEE 115 25144 25145 /* sc_x1_speed_override2 :: override_speed :: reserved0 [07:06] */ 25146 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_RESERVED0_MASK 0x00c0 25147 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_RESERVED0_ALIGN 0 25148 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_RESERVED0_BITS 2 25149 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_RESERVED0_SHIFT 6 25150 25151 /* sc_x1_speed_override2 :: override_speed :: cl36rx_en [05:05] */ 25152 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_CL36RX_EN_MASK 0x0020 25153 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_CL36RX_EN_ALIGN 0 25154 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_CL36RX_EN_BITS 1 25155 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_CL36RX_EN_SHIFT 5 25156 25157 /* sc_x1_speed_override2 :: override_speed :: cl36tx_en [04:04] */ 25158 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_CL36TX_EN_MASK 0x0010 25159 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_CL36TX_EN_ALIGN 0 25160 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_CL36TX_EN_BITS 1 25161 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_CL36TX_EN_SHIFT 4 25162 25163 /* sc_x1_speed_override2 :: override_speed :: t_pma_40b_mode [03:03] */ 25164 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_T_PMA_40B_MODE_MASK 0x0008 25165 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_T_PMA_40B_MODE_ALIGN 0 25166 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_T_PMA_40B_MODE_BITS 1 25167 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_T_PMA_40B_MODE_SHIFT 3 25168 25169 /* sc_x1_speed_override2 :: override_speed :: num_lanes [02:00] */ 25170 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_NUM_LANES_MASK 0x0007 25171 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_NUM_LANES_ALIGN 0 25172 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_NUM_LANES_BITS 3 25173 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_NUM_LANES_SHIFT 0 25174 25175 25176 /**************************************************************************** 25177 * sc_x1_speed_override2 :: override_0 25178 */ 25179 /* sc_x1_speed_override2 :: override_0 :: cl72_en [15:15] */ 25180 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_CL72_EN_MASK 0x8000 25181 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_CL72_EN_ALIGN 0 25182 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_CL72_EN_BITS 1 25183 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_CL72_EN_SHIFT 15 25184 25185 /* sc_x1_speed_override2 :: override_0 :: os_mode [14:11] */ 25186 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_OS_MODE_MASK 0x7800 25187 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_OS_MODE_ALIGN 0 25188 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_OS_MODE_BITS 4 25189 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_OS_MODE_SHIFT 11 25190 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_OS_MODE_OS_MODE_1 0 25191 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_OS_MODE_OS_MODE_2 1 25192 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_OS_MODE_OS_MODE_4 2 25193 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_OS_MODE_OS_MODE_16p5 8 25194 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_OS_MODE_OS_MODE_20p625 12 25195 25196 /* sc_x1_speed_override2 :: override_0 :: t_fifo_mode [10:09] */ 25197 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_T_FIFO_MODE_MASK 0x0600 25198 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_T_FIFO_MODE_ALIGN 0 25199 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_T_FIFO_MODE_BITS 2 25200 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_T_FIFO_MODE_SHIFT 9 25201 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_T_FIFO_MODE_T_FIFO_INSERT_NO_AM 0 25202 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_T_FIFO_MODE_T_FIFO_INSERT_4_AM 1 25203 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_T_FIFO_MODE_T_FIFO_INSERT_20_AM 2 25204 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_T_FIFO_MODE_T_FIFO_INSERT_2_AM 3 25205 25206 /* sc_x1_speed_override2 :: override_0 :: t_enc_mode [08:07] */ 25207 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_T_ENC_MODE_MASK 0x0180 25208 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_T_ENC_MODE_ALIGN 0 25209 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_T_ENC_MODE_BITS 2 25210 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_T_ENC_MODE_SHIFT 7 25211 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_T_ENC_MODE_T_ENC_MODE_BYPASS 0 25212 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_T_ENC_MODE_T_ENC_MODE_CL49 1 25213 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_T_ENC_MODE_T_ENC_MODE_CL82 2 25214 25215 /* sc_x1_speed_override2 :: override_0 :: t_HG2_ENABLE [06:06] */ 25216 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_T_HG2_ENABLE_MASK 0x0040 25217 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_T_HG2_ENABLE_ALIGN 0 25218 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_T_HG2_ENABLE_BITS 1 25219 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_T_HG2_ENABLE_SHIFT 6 25220 25221 /* sc_x1_speed_override2 :: override_0 :: t_pma_btmx_mode [05:04] */ 25222 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_T_PMA_BTMX_MODE_MASK 0x0030 25223 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_T_PMA_BTMX_MODE_ALIGN 0 25224 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_T_PMA_BTMX_MODE_BITS 2 25225 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_T_PMA_BTMX_MODE_SHIFT 4 25226 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_T_PMA_BTMX_MODE_BS_BTMX_MODE_1to1 0 25227 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_T_PMA_BTMX_MODE_BS_BTMX_MODE_2to1 1 25228 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_T_PMA_BTMX_MODE_BS_BTMX_MODE_5to1 2 25229 25230 /* sc_x1_speed_override2 :: override_0 :: scr_mode [03:01] */ 25231 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_SCR_MODE_MASK 0x000e 25232 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_SCR_MODE_ALIGN 0 25233 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_SCR_MODE_BITS 3 25234 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_SCR_MODE_SHIFT 1 25235 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_SCR_MODE_T_SCR_MODE_BYPASS 0 25236 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_SCR_MODE_T_SCR_MODE_CL49 1 25237 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_SCR_MODE_T_SCR_MODE_40G_2_LANE 2 25238 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_SCR_MODE_T_SCR_MODE_100G 3 25239 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_SCR_MODE_T_SCR_MODE_20G 4 25240 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_SCR_MODE_T_SCR_MODE_40G_4_LANE 5 25241 25242 /* sc_x1_speed_override2 :: override_0 :: reserved0 [00:00] */ 25243 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_RESERVED0_MASK 0x0001 25244 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_RESERVED0_ALIGN 0 25245 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_RESERVED0_BITS 1 25246 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_RESERVED0_SHIFT 0 25247 25248 25249 /**************************************************************************** 25250 * sc_x1_speed_override2 :: override_1 25251 */ 25252 /* sc_x1_speed_override2 :: override_1 :: descr_mode [15:14] */ 25253 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_DESCR_MODE_MASK 0xc000 25254 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_DESCR_MODE_ALIGN 0 25255 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_DESCR_MODE_BITS 2 25256 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_DESCR_MODE_SHIFT 14 25257 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_DESCR_MODE_R_DESCR_MODE_BYPASS 0 25258 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_DESCR_MODE_R_DESCR_MODE_CL49 1 25259 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_DESCR_MODE_R_DESCR_MODE_CL82 2 25260 25261 /* sc_x1_speed_override2 :: override_1 :: dec_tl_mode [13:12] */ 25262 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_DEC_TL_MODE_MASK 0x3000 25263 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_DEC_TL_MODE_ALIGN 0 25264 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_DEC_TL_MODE_BITS 2 25265 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_DEC_TL_MODE_SHIFT 12 25266 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_DEC_TL_MODE_R_DEC_TL_MODE_BYPASS 0 25267 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_DEC_TL_MODE_R_DEC_TL_MODE_CL49 1 25268 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_DEC_TL_MODE_R_DEC_TL_MODE_CL82 2 25269 25270 /* sc_x1_speed_override2 :: override_1 :: deskew_mode [11:08] */ 25271 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_DESKEW_MODE_MASK 0x0f00 25272 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_DESKEW_MODE_ALIGN 0 25273 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_DESKEW_MODE_BITS 4 25274 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_DESKEW_MODE_SHIFT 8 25275 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_DESKEW_MODE_R_DESKEW_MODE_BYPASS 0 25276 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_DESKEW_MODE_R_DESKEW_MODE_20G 1 25277 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_DESKEW_MODE_R_DESKEW_MODE_40G_4_LANE 2 25278 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_DESKEW_MODE_R_DESKEW_MODE_40G_2_LANE 3 25279 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_DESKEW_MODE_R_DESKEW_MODE_100G 4 25280 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_DESKEW_MODE_R_DESKEW_MODE_CL49 5 25281 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_DESKEW_MODE_R_DESKEW_MODE_CL91_QUAD 6 25282 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_DESKEW_MODE_R_DESKEW_MODE_CL91_SINGLE_BRCM 7 25283 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_DESKEW_MODE_R_DESKEW_MODE_CL91_DUAL_BRCM 8 25284 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_DESKEW_MODE_R_DESKEW_MODE_CL91_FC 9 25285 25286 /* sc_x1_speed_override2 :: override_1 :: dec_fsm_mode [07:06] */ 25287 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_DEC_FSM_MODE_MASK 0x00c0 25288 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_DEC_FSM_MODE_ALIGN 0 25289 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_DEC_FSM_MODE_BITS 2 25290 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_DEC_FSM_MODE_SHIFT 6 25291 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_DEC_FSM_MODE_R_DEC_FSM_MODE_BYPASS 0 25292 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_DEC_FSM_MODE_R_DEC_FSM_MODE_CL49 1 25293 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_DEC_FSM_MODE_R_DEC_FSM_MODE_CL82 2 25294 25295 /* sc_x1_speed_override2 :: override_1 :: bs_sm_sync_mode [05:05] */ 25296 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_BS_SM_SYNC_MODE_MASK 0x0020 25297 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_BS_SM_SYNC_MODE_ALIGN 0 25298 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_BS_SM_SYNC_MODE_BITS 1 25299 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_BS_SM_SYNC_MODE_SHIFT 5 25300 25301 /* sc_x1_speed_override2 :: override_1 :: bs_sync_en [04:04] */ 25302 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_BS_SYNC_EN_MASK 0x0010 25303 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_BS_SYNC_EN_ALIGN 0 25304 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_BS_SYNC_EN_BITS 1 25305 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_BS_SYNC_EN_SHIFT 4 25306 25307 /* sc_x1_speed_override2 :: override_1 :: bs_dist_mode [03:02] */ 25308 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_BS_DIST_MODE_MASK 0x000c 25309 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_BS_DIST_MODE_ALIGN 0 25310 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_BS_DIST_MODE_BITS 2 25311 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_BS_DIST_MODE_SHIFT 2 25312 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_BS_DIST_MODE_BS_DIST_MODE_5_LANE_TDM 0 25313 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_BS_DIST_MODE_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 25314 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_BS_DIST_MODE_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 25315 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_BS_DIST_MODE_BS_DIST_MODE_NO_TDM 3 25316 25317 /* sc_x1_speed_override2 :: override_1 :: bs_btmx_mode [01:00] */ 25318 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_BS_BTMX_MODE_MASK 0x0003 25319 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_BS_BTMX_MODE_ALIGN 0 25320 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_BS_BTMX_MODE_BITS 2 25321 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_BS_BTMX_MODE_SHIFT 0 25322 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_BS_BTMX_MODE_BS_BTMX_MODE_1to1 0 25323 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_BS_BTMX_MODE_BS_BTMX_MODE_2to1 1 25324 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_BS_BTMX_MODE_BS_BTMX_MODE_5to1 2 25325 25326 25327 /**************************************************************************** 25328 * sc_x1_speed_override2 :: override_2 25329 */ 25330 /* sc_x1_speed_override2 :: override_2 :: reserved0 [15:14] */ 25331 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_2_RESERVED0_MASK 0xc000 25332 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_2_RESERVED0_ALIGN 0 25333 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_2_RESERVED0_BITS 2 25334 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_2_RESERVED0_SHIFT 14 25335 25336 /* sc_x1_speed_override2 :: override_2 :: clockcnt0 [13:00] */ 25337 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_2_CLOCKCNT0_MASK 0x3fff 25338 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_2_CLOCKCNT0_ALIGN 0 25339 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_2_CLOCKCNT0_BITS 14 25340 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_2_CLOCKCNT0_SHIFT 0 25341 25342 25343 /**************************************************************************** 25344 * sc_x1_speed_override2 :: override_3 25345 */ 25346 /* sc_x1_speed_override2 :: override_3 :: reserved0 [15:08] */ 25347 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_3_RESERVED0_MASK 0xff00 25348 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_3_RESERVED0_ALIGN 0 25349 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_3_RESERVED0_BITS 8 25350 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_3_RESERVED0_SHIFT 8 25351 25352 /* sc_x1_speed_override2 :: override_3 :: clockcnt1 [07:00] */ 25353 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_3_CLOCKCNT1_MASK 0x00ff 25354 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_3_CLOCKCNT1_ALIGN 0 25355 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_3_CLOCKCNT1_BITS 8 25356 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_3_CLOCKCNT1_SHIFT 0 25357 25358 25359 /**************************************************************************** 25360 * sc_x1_speed_override2 :: override_4 25361 */ 25362 /* sc_x1_speed_override2 :: override_4 :: reserved0 [15:14] */ 25363 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_4_RESERVED0_MASK 0xc000 25364 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_4_RESERVED0_ALIGN 0 25365 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_4_RESERVED0_BITS 2 25366 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_4_RESERVED0_SHIFT 14 25367 25368 /* sc_x1_speed_override2 :: override_4 :: loopcnt0 [13:06] */ 25369 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_4_LOOPCNT0_MASK 0x3fc0 25370 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_4_LOOPCNT0_ALIGN 0 25371 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_4_LOOPCNT0_BITS 8 25372 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_4_LOOPCNT0_SHIFT 6 25373 25374 /* sc_x1_speed_override2 :: override_4 :: loopcnt1 [05:00] */ 25375 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_4_LOOPCNT1_MASK 0x003f 25376 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_4_LOOPCNT1_ALIGN 0 25377 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_4_LOOPCNT1_BITS 6 25378 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_4_LOOPCNT1_SHIFT 0 25379 25380 25381 /**************************************************************************** 25382 * sc_x1_speed_override2 :: override_5 25383 */ 25384 /* sc_x1_speed_override2 :: override_5 :: reserved0 [15:13] */ 25385 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_5_RESERVED0_MASK 0xe000 25386 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_5_RESERVED0_ALIGN 0 25387 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_5_RESERVED0_BITS 3 25388 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_5_RESERVED0_SHIFT 13 25389 25390 /* sc_x1_speed_override2 :: override_5 :: mac_creditgencnt [12:00] */ 25391 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_5_MAC_CREDITGENCNT_MASK 0x1fff 25392 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_5_MAC_CREDITGENCNT_ALIGN 0 25393 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_5_MAC_CREDITGENCNT_BITS 13 25394 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_5_MAC_CREDITGENCNT_SHIFT 0 25395 25396 25397 /**************************************************************************** 25398 * sc_x1_speed_override2 :: override_6 25399 */ 25400 /* sc_x1_speed_override2 :: override_6 :: reserved0 [15:11] */ 25401 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_6_RESERVED0_MASK 0xf800 25402 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_6_RESERVED0_ALIGN 0 25403 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_6_RESERVED0_BITS 5 25404 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_6_RESERVED0_SHIFT 11 25405 25406 /* sc_x1_speed_override2 :: override_6 :: AM_spacing_mul [10:09] */ 25407 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_6_AM_SPACING_MUL_MASK 0x0600 25408 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_6_AM_SPACING_MUL_ALIGN 0 25409 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_6_AM_SPACING_MUL_BITS 2 25410 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_6_AM_SPACING_MUL_SHIFT 9 25411 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_6_AM_SPACING_MUL_AM_SPACING_MUL_2 0 25412 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_6_AM_SPACING_MUL_AM_SPACING_MUL_4 1 25413 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_6_AM_SPACING_MUL_AM_SPACING_MUL_5 2 25414 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_6_AM_SPACING_MUL_AM_SPACING_MUL_20 3 25415 25416 /* sc_x1_speed_override2 :: override_6 :: t_pma_bitmux_delay [08:07] */ 25417 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_6_T_PMA_BITMUX_DELAY_MASK 0x0180 25418 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_6_T_PMA_BITMUX_DELAY_ALIGN 0 25419 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_6_T_PMA_BITMUX_DELAY_BITS 2 25420 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_6_T_PMA_BITMUX_DELAY_SHIFT 7 25421 25422 /* sc_x1_speed_override2 :: override_6 :: t_pma_watermark [06:03] */ 25423 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_6_T_PMA_WATERMARK_MASK 0x0078 25424 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_6_T_PMA_WATERMARK_ALIGN 0 25425 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_6_T_PMA_WATERMARK_BITS 4 25426 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_6_T_PMA_WATERMARK_SHIFT 3 25427 25428 /* sc_x1_speed_override2 :: override_6 :: t_pma_cl91_mux_sel [02:02] */ 25429 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_6_T_PMA_CL91_MUX_SEL_MASK 0x0004 25430 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_6_T_PMA_CL91_MUX_SEL_ALIGN 0 25431 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_6_T_PMA_CL91_MUX_SEL_BITS 1 25432 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_6_T_PMA_CL91_MUX_SEL_SHIFT 2 25433 25434 /* sc_x1_speed_override2 :: override_6 :: t_five_bit_xor_en [01:01] */ 25435 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_6_T_FIVE_BIT_XOR_EN_MASK 0x0002 25436 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_6_T_FIVE_BIT_XOR_EN_ALIGN 0 25437 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_6_T_FIVE_BIT_XOR_EN_BITS 1 25438 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_6_T_FIVE_BIT_XOR_EN_SHIFT 1 25439 25440 /* sc_x1_speed_override2 :: override_6 :: t_cl91_cw_scramble [00:00] */ 25441 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_6_T_CL91_CW_SCRAMBLE_MASK 0x0001 25442 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_6_T_CL91_CW_SCRAMBLE_ALIGN 0 25443 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_6_T_CL91_CW_SCRAMBLE_BITS 1 25444 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_6_T_CL91_CW_SCRAMBLE_SHIFT 0 25445 25446 25447 /**************************************************************************** 25448 * sc_x1_speed_override2 :: override_7 25449 */ 25450 /* sc_x1_speed_override2 :: override_7 :: reserved0 [15:14] */ 25451 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_RESERVED0_MASK 0xc000 25452 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_RESERVED0_ALIGN 0 25453 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_RESERVED0_BITS 2 25454 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_RESERVED0_SHIFT 14 25455 25456 /* sc_x1_speed_override2 :: override_7 :: r_HG2_ENABLE [13:13] */ 25457 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_R_HG2_ENABLE_MASK 0x2000 25458 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_R_HG2_ENABLE_ALIGN 0 25459 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_R_HG2_ENABLE_BITS 1 25460 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_R_HG2_ENABLE_SHIFT 13 25461 25462 /* sc_x1_speed_override2 :: override_7 :: r_tc_out_mode [12:11] */ 25463 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_R_TC_OUT_MODE_MASK 0x1800 25464 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_R_TC_OUT_MODE_ALIGN 0 25465 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_R_TC_OUT_MODE_BITS 2 25466 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_R_TC_OUT_MODE_SHIFT 11 25467 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_R_TC_OUT_MODE_R_TC_OUT_MODE_SINGLE 0 25468 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_R_TC_OUT_MODE_R_TC_OUT_MODE_DUAL 1 25469 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_R_TC_OUT_MODE_R_TC_OUT_MODE_QUAD 2 25470 25471 /* sc_x1_speed_override2 :: override_7 :: r_five_bit_xor_en [10:10] */ 25472 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_R_FIVE_BIT_XOR_EN_MASK 0x0400 25473 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_R_FIVE_BIT_XOR_EN_ALIGN 0 25474 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_R_FIVE_BIT_XOR_EN_BITS 1 25475 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_R_FIVE_BIT_XOR_EN_SHIFT 10 25476 25477 /* sc_x1_speed_override2 :: override_7 :: r_tc_mode [09:08] */ 25478 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_R_TC_MODE_MASK 0x0300 25479 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_R_TC_MODE_ALIGN 0 25480 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_R_TC_MODE_BITS 2 25481 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_R_TC_MODE_SHIFT 8 25482 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_R_TC_MODE_R_TC_MODE_SINGLE 0 25483 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_R_TC_MODE_R_TC_MODE_DUAL 1 25484 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_R_TC_MODE_R_TC_MODE_QUAD 2 25485 25486 /* sc_x1_speed_override2 :: override_7 :: r_tc_in_mode [07:07] */ 25487 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_R_TC_IN_MODE_MASK 0x0080 25488 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_R_TC_IN_MODE_ALIGN 0 25489 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_R_TC_IN_MODE_BITS 1 25490 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_R_TC_IN_MODE_SHIFT 7 25491 25492 /* sc_x1_speed_override2 :: override_7 :: r_cl91_cw_scramble [06:06] */ 25493 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_R_CL91_CW_SCRAMBLE_MASK 0x0040 25494 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_R_CL91_CW_SCRAMBLE_ALIGN 0 25495 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_R_CL91_CW_SCRAMBLE_BITS 1 25496 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_R_CL91_CW_SCRAMBLE_SHIFT 6 25497 25498 /* sc_x1_speed_override2 :: override_7 :: r_merge_mode [05:03] */ 25499 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_R_MERGE_MODE_MASK 0x0038 25500 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_R_MERGE_MODE_ALIGN 0 25501 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_R_MERGE_MODE_BITS 3 25502 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_R_MERGE_MODE_SHIFT 3 25503 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_R_MERGE_MODE_R_MERGE_MODE_BYPASS 0 25504 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_R_MERGE_MODE_R_MERGE_MODE_CL91_FC 1 25505 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_R_MERGE_MODE_R_MERGE_MODE_CL91_SINGLE_LANE 2 25506 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_R_MERGE_MODE_R_MERGE_MODE_CL91_DUAL_LANE 3 25507 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_R_MERGE_MODE_R_MERGE_MODE_CL91_QUAD_LANE 4 25508 25509 /* sc_x1_speed_override2 :: override_7 :: cl91_blksync_mode [02:00] */ 25510 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_CL91_BLKSYNC_MODE_MASK 0x0007 25511 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_CL91_BLKSYNC_MODE_ALIGN 0 25512 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_CL91_BLKSYNC_MODE_BITS 3 25513 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_CL91_BLKSYNC_MODE_SHIFT 0 25514 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_CL91_BLKSYNC_MODE_R_BLKSYNC_NO_CL91_FEC 0 25515 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_CL91_BLKSYNC_MODE_R_BLKSYNC_CL91_QUAD_LANE_FEC 1 25516 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_CL91_BLKSYNC_MODE_R_BLKSYNC_CL91_DUAL_LANE_FEC 2 25517 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_CL91_BLKSYNC_MODE_R_BLKSYNC_CL91_SINGLE_LANE_FEC 3 25518 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_CL91_BLKSYNC_MODE_R_BLKSYNC_CL91_FC_FEC 4 25519 25520 25521 /**************************************************************************** 25522 * TSC_WC4_TSC_USER1_sc_x1_speed_override3 25523 */ 25524 /**************************************************************************** 25525 * sc_x1_speed_override3 :: override_speed 25526 */ 25527 /* sc_x1_speed_override3 :: override_speed :: speed [15:08] */ 25528 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_MASK 0xff00 25529 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_ALIGN 0 25530 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_BITS 8 25531 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_SHIFT 8 25532 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_10G_CR1 0 25533 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_10G_KR1 1 25534 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_10G_X1 2 25535 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_10G_HG2_CR1 4 25536 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_10G_HG2_KR1 5 25537 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_10G_HG2_X1 6 25538 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_20G_CR1 8 25539 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_20G_KR1 9 25540 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_20G_X1 10 25541 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_20G_HG2_CR1 12 25542 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_20G_HG2_KR1 13 25543 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_20G_HG2_X1 14 25544 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_25G_CR1 16 25545 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_25G_KR1 17 25546 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_25G_X1 18 25547 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_25G_HG2_CR1 20 25548 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_25G_HG2_KR1 21 25549 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_25G_HG2_X1 22 25550 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_20G_CR2 24 25551 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_20G_KR2 25 25552 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_20G_X2 26 25553 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_20G_HG2_CR2 28 25554 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_20G_HG2_KR2 29 25555 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_20G_HG2_X2 30 25556 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_40G_CR2 32 25557 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_40G_KR2 33 25558 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_40G_X2 34 25559 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_40G_HG2_CR2 36 25560 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_40G_HG2_KR2 37 25561 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_40G_HG2_X2 38 25562 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_40G_CR4 40 25563 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_40G_KR4 41 25564 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_40G_X4 42 25565 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_40G_HG2_CR4 44 25566 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_40G_HG2_KR4 45 25567 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_40G_HG2_X4 46 25568 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_50G_CR2 48 25569 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_50G_KR2 49 25570 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_50G_X2 50 25571 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_50G_HG2_CR2 52 25572 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_50G_HG2_KR2 53 25573 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_50G_HG2_X2 54 25574 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_50G_CR4 56 25575 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_50G_KR4 57 25576 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_50G_X4 58 25577 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_50G_HG2_CR4 60 25578 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_50G_HG2_KR4 61 25579 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_50G_HG2_X4 62 25580 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_100G_CR4 64 25581 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_100G_KR4 65 25582 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_100G_X4 66 25583 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_100G_HG2_CR4 68 25584 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_100G_HG2_KR4 69 25585 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_100G_HG2_X4 70 25586 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_CL73_20GVCO 72 25587 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_CL73_25GVCO 80 25588 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_CL36_20GVCO 88 25589 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_CL36_25GVCO 96 25590 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_25G_CR_IEEE 112 25591 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_25G_CRS_IEEE 113 25592 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_25G_KR_IEEE 114 25593 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_S_25G_KRS_IEEE 115 25594 25595 /* sc_x1_speed_override3 :: override_speed :: reserved0 [07:06] */ 25596 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_RESERVED0_MASK 0x00c0 25597 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_RESERVED0_ALIGN 0 25598 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_RESERVED0_BITS 2 25599 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_RESERVED0_SHIFT 6 25600 25601 /* sc_x1_speed_override3 :: override_speed :: cl36rx_en [05:05] */ 25602 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_CL36RX_EN_MASK 0x0020 25603 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_CL36RX_EN_ALIGN 0 25604 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_CL36RX_EN_BITS 1 25605 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_CL36RX_EN_SHIFT 5 25606 25607 /* sc_x1_speed_override3 :: override_speed :: cl36tx_en [04:04] */ 25608 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_CL36TX_EN_MASK 0x0010 25609 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_CL36TX_EN_ALIGN 0 25610 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_CL36TX_EN_BITS 1 25611 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_CL36TX_EN_SHIFT 4 25612 25613 /* sc_x1_speed_override3 :: override_speed :: t_pma_40b_mode [03:03] */ 25614 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_T_PMA_40B_MODE_MASK 0x0008 25615 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_T_PMA_40B_MODE_ALIGN 0 25616 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_T_PMA_40B_MODE_BITS 1 25617 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_T_PMA_40B_MODE_SHIFT 3 25618 25619 /* sc_x1_speed_override3 :: override_speed :: num_lanes [02:00] */ 25620 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_NUM_LANES_MASK 0x0007 25621 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_NUM_LANES_ALIGN 0 25622 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_NUM_LANES_BITS 3 25623 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_NUM_LANES_SHIFT 0 25624 25625 25626 /**************************************************************************** 25627 * sc_x1_speed_override3 :: override_0 25628 */ 25629 /* sc_x1_speed_override3 :: override_0 :: cl72_en [15:15] */ 25630 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_CL72_EN_MASK 0x8000 25631 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_CL72_EN_ALIGN 0 25632 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_CL72_EN_BITS 1 25633 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_CL72_EN_SHIFT 15 25634 25635 /* sc_x1_speed_override3 :: override_0 :: os_mode [14:11] */ 25636 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_OS_MODE_MASK 0x7800 25637 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_OS_MODE_ALIGN 0 25638 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_OS_MODE_BITS 4 25639 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_OS_MODE_SHIFT 11 25640 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_OS_MODE_OS_MODE_1 0 25641 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_OS_MODE_OS_MODE_2 1 25642 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_OS_MODE_OS_MODE_4 2 25643 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_OS_MODE_OS_MODE_16p5 8 25644 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_OS_MODE_OS_MODE_20p625 12 25645 25646 /* sc_x1_speed_override3 :: override_0 :: t_fifo_mode [10:09] */ 25647 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_T_FIFO_MODE_MASK 0x0600 25648 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_T_FIFO_MODE_ALIGN 0 25649 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_T_FIFO_MODE_BITS 2 25650 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_T_FIFO_MODE_SHIFT 9 25651 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_T_FIFO_MODE_T_FIFO_INSERT_NO_AM 0 25652 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_T_FIFO_MODE_T_FIFO_INSERT_4_AM 1 25653 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_T_FIFO_MODE_T_FIFO_INSERT_20_AM 2 25654 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_T_FIFO_MODE_T_FIFO_INSERT_2_AM 3 25655 25656 /* sc_x1_speed_override3 :: override_0 :: t_enc_mode [08:07] */ 25657 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_T_ENC_MODE_MASK 0x0180 25658 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_T_ENC_MODE_ALIGN 0 25659 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_T_ENC_MODE_BITS 2 25660 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_T_ENC_MODE_SHIFT 7 25661 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_T_ENC_MODE_T_ENC_MODE_BYPASS 0 25662 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_T_ENC_MODE_T_ENC_MODE_CL49 1 25663 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_T_ENC_MODE_T_ENC_MODE_CL82 2 25664 25665 /* sc_x1_speed_override3 :: override_0 :: t_HG2_ENABLE [06:06] */ 25666 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_T_HG2_ENABLE_MASK 0x0040 25667 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_T_HG2_ENABLE_ALIGN 0 25668 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_T_HG2_ENABLE_BITS 1 25669 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_T_HG2_ENABLE_SHIFT 6 25670 25671 /* sc_x1_speed_override3 :: override_0 :: t_pma_btmx_mode [05:04] */ 25672 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_T_PMA_BTMX_MODE_MASK 0x0030 25673 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_T_PMA_BTMX_MODE_ALIGN 0 25674 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_T_PMA_BTMX_MODE_BITS 2 25675 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_T_PMA_BTMX_MODE_SHIFT 4 25676 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_T_PMA_BTMX_MODE_BS_BTMX_MODE_1to1 0 25677 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_T_PMA_BTMX_MODE_BS_BTMX_MODE_2to1 1 25678 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_T_PMA_BTMX_MODE_BS_BTMX_MODE_5to1 2 25679 25680 /* sc_x1_speed_override3 :: override_0 :: scr_mode [03:01] */ 25681 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_SCR_MODE_MASK 0x000e 25682 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_SCR_MODE_ALIGN 0 25683 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_SCR_MODE_BITS 3 25684 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_SCR_MODE_SHIFT 1 25685 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_SCR_MODE_T_SCR_MODE_BYPASS 0 25686 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_SCR_MODE_T_SCR_MODE_CL49 1 25687 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_SCR_MODE_T_SCR_MODE_40G_2_LANE 2 25688 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_SCR_MODE_T_SCR_MODE_100G 3 25689 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_SCR_MODE_T_SCR_MODE_20G 4 25690 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_SCR_MODE_T_SCR_MODE_40G_4_LANE 5 25691 25692 /* sc_x1_speed_override3 :: override_0 :: reserved0 [00:00] */ 25693 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_RESERVED0_MASK 0x0001 25694 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_RESERVED0_ALIGN 0 25695 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_RESERVED0_BITS 1 25696 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_RESERVED0_SHIFT 0 25697 25698 25699 /**************************************************************************** 25700 * sc_x1_speed_override3 :: override_1 25701 */ 25702 /* sc_x1_speed_override3 :: override_1 :: descr_mode [15:14] */ 25703 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_DESCR_MODE_MASK 0xc000 25704 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_DESCR_MODE_ALIGN 0 25705 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_DESCR_MODE_BITS 2 25706 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_DESCR_MODE_SHIFT 14 25707 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_DESCR_MODE_R_DESCR_MODE_BYPASS 0 25708 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_DESCR_MODE_R_DESCR_MODE_CL49 1 25709 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_DESCR_MODE_R_DESCR_MODE_CL82 2 25710 25711 /* sc_x1_speed_override3 :: override_1 :: dec_tl_mode [13:12] */ 25712 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_DEC_TL_MODE_MASK 0x3000 25713 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_DEC_TL_MODE_ALIGN 0 25714 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_DEC_TL_MODE_BITS 2 25715 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_DEC_TL_MODE_SHIFT 12 25716 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_DEC_TL_MODE_R_DEC_TL_MODE_BYPASS 0 25717 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_DEC_TL_MODE_R_DEC_TL_MODE_CL49 1 25718 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_DEC_TL_MODE_R_DEC_TL_MODE_CL82 2 25719 25720 /* sc_x1_speed_override3 :: override_1 :: deskew_mode [11:08] */ 25721 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_DESKEW_MODE_MASK 0x0f00 25722 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_DESKEW_MODE_ALIGN 0 25723 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_DESKEW_MODE_BITS 4 25724 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_DESKEW_MODE_SHIFT 8 25725 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_DESKEW_MODE_R_DESKEW_MODE_BYPASS 0 25726 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_DESKEW_MODE_R_DESKEW_MODE_20G 1 25727 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_DESKEW_MODE_R_DESKEW_MODE_40G_4_LANE 2 25728 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_DESKEW_MODE_R_DESKEW_MODE_40G_2_LANE 3 25729 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_DESKEW_MODE_R_DESKEW_MODE_100G 4 25730 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_DESKEW_MODE_R_DESKEW_MODE_CL49 5 25731 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_DESKEW_MODE_R_DESKEW_MODE_CL91_QUAD 6 25732 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_DESKEW_MODE_R_DESKEW_MODE_CL91_SINGLE_BRCM 7 25733 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_DESKEW_MODE_R_DESKEW_MODE_CL91_DUAL_BRCM 8 25734 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_DESKEW_MODE_R_DESKEW_MODE_CL91_FC 9 25735 25736 /* sc_x1_speed_override3 :: override_1 :: dec_fsm_mode [07:06] */ 25737 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_DEC_FSM_MODE_MASK 0x00c0 25738 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_DEC_FSM_MODE_ALIGN 0 25739 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_DEC_FSM_MODE_BITS 2 25740 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_DEC_FSM_MODE_SHIFT 6 25741 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_DEC_FSM_MODE_R_DEC_FSM_MODE_BYPASS 0 25742 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_DEC_FSM_MODE_R_DEC_FSM_MODE_CL49 1 25743 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_DEC_FSM_MODE_R_DEC_FSM_MODE_CL82 2 25744 25745 /* sc_x1_speed_override3 :: override_1 :: bs_sm_sync_mode [05:05] */ 25746 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_BS_SM_SYNC_MODE_MASK 0x0020 25747 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_BS_SM_SYNC_MODE_ALIGN 0 25748 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_BS_SM_SYNC_MODE_BITS 1 25749 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_BS_SM_SYNC_MODE_SHIFT 5 25750 25751 /* sc_x1_speed_override3 :: override_1 :: bs_sync_en [04:04] */ 25752 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_BS_SYNC_EN_MASK 0x0010 25753 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_BS_SYNC_EN_ALIGN 0 25754 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_BS_SYNC_EN_BITS 1 25755 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_BS_SYNC_EN_SHIFT 4 25756 25757 /* sc_x1_speed_override3 :: override_1 :: bs_dist_mode [03:02] */ 25758 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_BS_DIST_MODE_MASK 0x000c 25759 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_BS_DIST_MODE_ALIGN 0 25760 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_BS_DIST_MODE_BITS 2 25761 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_BS_DIST_MODE_SHIFT 2 25762 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_BS_DIST_MODE_BS_DIST_MODE_5_LANE_TDM 0 25763 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_BS_DIST_MODE_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 25764 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_BS_DIST_MODE_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 25765 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_BS_DIST_MODE_BS_DIST_MODE_NO_TDM 3 25766 25767 /* sc_x1_speed_override3 :: override_1 :: bs_btmx_mode [01:00] */ 25768 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_BS_BTMX_MODE_MASK 0x0003 25769 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_BS_BTMX_MODE_ALIGN 0 25770 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_BS_BTMX_MODE_BITS 2 25771 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_BS_BTMX_MODE_SHIFT 0 25772 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_BS_BTMX_MODE_BS_BTMX_MODE_1to1 0 25773 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_BS_BTMX_MODE_BS_BTMX_MODE_2to1 1 25774 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_BS_BTMX_MODE_BS_BTMX_MODE_5to1 2 25775 25776 25777 /**************************************************************************** 25778 * sc_x1_speed_override3 :: override_2 25779 */ 25780 /* sc_x1_speed_override3 :: override_2 :: reserved0 [15:14] */ 25781 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_2_RESERVED0_MASK 0xc000 25782 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_2_RESERVED0_ALIGN 0 25783 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_2_RESERVED0_BITS 2 25784 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_2_RESERVED0_SHIFT 14 25785 25786 /* sc_x1_speed_override3 :: override_2 :: clockcnt0 [13:00] */ 25787 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_2_CLOCKCNT0_MASK 0x3fff 25788 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_2_CLOCKCNT0_ALIGN 0 25789 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_2_CLOCKCNT0_BITS 14 25790 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_2_CLOCKCNT0_SHIFT 0 25791 25792 25793 /**************************************************************************** 25794 * sc_x1_speed_override3 :: override_3 25795 */ 25796 /* sc_x1_speed_override3 :: override_3 :: reserved0 [15:08] */ 25797 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_3_RESERVED0_MASK 0xff00 25798 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_3_RESERVED0_ALIGN 0 25799 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_3_RESERVED0_BITS 8 25800 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_3_RESERVED0_SHIFT 8 25801 25802 /* sc_x1_speed_override3 :: override_3 :: clockcnt1 [07:00] */ 25803 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_3_CLOCKCNT1_MASK 0x00ff 25804 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_3_CLOCKCNT1_ALIGN 0 25805 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_3_CLOCKCNT1_BITS 8 25806 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_3_CLOCKCNT1_SHIFT 0 25807 25808 25809 /**************************************************************************** 25810 * sc_x1_speed_override3 :: override_4 25811 */ 25812 /* sc_x1_speed_override3 :: override_4 :: reserved0 [15:14] */ 25813 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_4_RESERVED0_MASK 0xc000 25814 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_4_RESERVED0_ALIGN 0 25815 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_4_RESERVED0_BITS 2 25816 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_4_RESERVED0_SHIFT 14 25817 25818 /* sc_x1_speed_override3 :: override_4 :: loopcnt0 [13:06] */ 25819 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_4_LOOPCNT0_MASK 0x3fc0 25820 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_4_LOOPCNT0_ALIGN 0 25821 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_4_LOOPCNT0_BITS 8 25822 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_4_LOOPCNT0_SHIFT 6 25823 25824 /* sc_x1_speed_override3 :: override_4 :: loopcnt1 [05:00] */ 25825 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_4_LOOPCNT1_MASK 0x003f 25826 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_4_LOOPCNT1_ALIGN 0 25827 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_4_LOOPCNT1_BITS 6 25828 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_4_LOOPCNT1_SHIFT 0 25829 25830 25831 /**************************************************************************** 25832 * sc_x1_speed_override3 :: override_5 25833 */ 25834 /* sc_x1_speed_override3 :: override_5 :: reserved0 [15:13] */ 25835 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_5_RESERVED0_MASK 0xe000 25836 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_5_RESERVED0_ALIGN 0 25837 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_5_RESERVED0_BITS 3 25838 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_5_RESERVED0_SHIFT 13 25839 25840 /* sc_x1_speed_override3 :: override_5 :: mac_creditgencnt [12:00] */ 25841 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_5_MAC_CREDITGENCNT_MASK 0x1fff 25842 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_5_MAC_CREDITGENCNT_ALIGN 0 25843 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_5_MAC_CREDITGENCNT_BITS 13 25844 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_5_MAC_CREDITGENCNT_SHIFT 0 25845 25846 25847 /**************************************************************************** 25848 * sc_x1_speed_override3 :: override_6 25849 */ 25850 /* sc_x1_speed_override3 :: override_6 :: reserved0 [15:11] */ 25851 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_6_RESERVED0_MASK 0xf800 25852 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_6_RESERVED0_ALIGN 0 25853 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_6_RESERVED0_BITS 5 25854 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_6_RESERVED0_SHIFT 11 25855 25856 /* sc_x1_speed_override3 :: override_6 :: AM_spacing_mul [10:09] */ 25857 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_6_AM_SPACING_MUL_MASK 0x0600 25858 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_6_AM_SPACING_MUL_ALIGN 0 25859 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_6_AM_SPACING_MUL_BITS 2 25860 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_6_AM_SPACING_MUL_SHIFT 9 25861 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_6_AM_SPACING_MUL_AM_SPACING_MUL_2 0 25862 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_6_AM_SPACING_MUL_AM_SPACING_MUL_4 1 25863 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_6_AM_SPACING_MUL_AM_SPACING_MUL_5 2 25864 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_6_AM_SPACING_MUL_AM_SPACING_MUL_20 3 25865 25866 /* sc_x1_speed_override3 :: override_6 :: t_pma_bitmux_delay [08:07] */ 25867 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_6_T_PMA_BITMUX_DELAY_MASK 0x0180 25868 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_6_T_PMA_BITMUX_DELAY_ALIGN 0 25869 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_6_T_PMA_BITMUX_DELAY_BITS 2 25870 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_6_T_PMA_BITMUX_DELAY_SHIFT 7 25871 25872 /* sc_x1_speed_override3 :: override_6 :: t_pma_watermark [06:03] */ 25873 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_6_T_PMA_WATERMARK_MASK 0x0078 25874 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_6_T_PMA_WATERMARK_ALIGN 0 25875 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_6_T_PMA_WATERMARK_BITS 4 25876 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_6_T_PMA_WATERMARK_SHIFT 3 25877 25878 /* sc_x1_speed_override3 :: override_6 :: t_pma_cl91_mux_sel [02:02] */ 25879 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_6_T_PMA_CL91_MUX_SEL_MASK 0x0004 25880 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_6_T_PMA_CL91_MUX_SEL_ALIGN 0 25881 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_6_T_PMA_CL91_MUX_SEL_BITS 1 25882 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_6_T_PMA_CL91_MUX_SEL_SHIFT 2 25883 25884 /* sc_x1_speed_override3 :: override_6 :: t_five_bit_xor_en [01:01] */ 25885 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_6_T_FIVE_BIT_XOR_EN_MASK 0x0002 25886 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_6_T_FIVE_BIT_XOR_EN_ALIGN 0 25887 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_6_T_FIVE_BIT_XOR_EN_BITS 1 25888 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_6_T_FIVE_BIT_XOR_EN_SHIFT 1 25889 25890 /* sc_x1_speed_override3 :: override_6 :: t_cl91_cw_scramble [00:00] */ 25891 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_6_T_CL91_CW_SCRAMBLE_MASK 0x0001 25892 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_6_T_CL91_CW_SCRAMBLE_ALIGN 0 25893 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_6_T_CL91_CW_SCRAMBLE_BITS 1 25894 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_6_T_CL91_CW_SCRAMBLE_SHIFT 0 25895 25896 25897 /**************************************************************************** 25898 * sc_x1_speed_override3 :: override_7 25899 */ 25900 /* sc_x1_speed_override3 :: override_7 :: reserved0 [15:14] */ 25901 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_RESERVED0_MASK 0xc000 25902 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_RESERVED0_ALIGN 0 25903 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_RESERVED0_BITS 2 25904 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_RESERVED0_SHIFT 14 25905 25906 /* sc_x1_speed_override3 :: override_7 :: r_HG2_ENABLE [13:13] */ 25907 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_R_HG2_ENABLE_MASK 0x2000 25908 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_R_HG2_ENABLE_ALIGN 0 25909 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_R_HG2_ENABLE_BITS 1 25910 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_R_HG2_ENABLE_SHIFT 13 25911 25912 /* sc_x1_speed_override3 :: override_7 :: r_tc_out_mode [12:11] */ 25913 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_R_TC_OUT_MODE_MASK 0x1800 25914 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_R_TC_OUT_MODE_ALIGN 0 25915 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_R_TC_OUT_MODE_BITS 2 25916 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_R_TC_OUT_MODE_SHIFT 11 25917 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_R_TC_OUT_MODE_R_TC_OUT_MODE_SINGLE 0 25918 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_R_TC_OUT_MODE_R_TC_OUT_MODE_DUAL 1 25919 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_R_TC_OUT_MODE_R_TC_OUT_MODE_QUAD 2 25920 25921 /* sc_x1_speed_override3 :: override_7 :: r_five_bit_xor_en [10:10] */ 25922 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_R_FIVE_BIT_XOR_EN_MASK 0x0400 25923 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_R_FIVE_BIT_XOR_EN_ALIGN 0 25924 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_R_FIVE_BIT_XOR_EN_BITS 1 25925 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_R_FIVE_BIT_XOR_EN_SHIFT 10 25926 25927 /* sc_x1_speed_override3 :: override_7 :: r_tc_mode [09:08] */ 25928 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_R_TC_MODE_MASK 0x0300 25929 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_R_TC_MODE_ALIGN 0 25930 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_R_TC_MODE_BITS 2 25931 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_R_TC_MODE_SHIFT 8 25932 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_R_TC_MODE_R_TC_MODE_SINGLE 0 25933 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_R_TC_MODE_R_TC_MODE_DUAL 1 25934 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_R_TC_MODE_R_TC_MODE_QUAD 2 25935 25936 /* sc_x1_speed_override3 :: override_7 :: r_tc_in_mode [07:07] */ 25937 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_R_TC_IN_MODE_MASK 0x0080 25938 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_R_TC_IN_MODE_ALIGN 0 25939 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_R_TC_IN_MODE_BITS 1 25940 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_R_TC_IN_MODE_SHIFT 7 25941 25942 /* sc_x1_speed_override3 :: override_7 :: r_cl91_cw_scramble [06:06] */ 25943 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_R_CL91_CW_SCRAMBLE_MASK 0x0040 25944 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_R_CL91_CW_SCRAMBLE_ALIGN 0 25945 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_R_CL91_CW_SCRAMBLE_BITS 1 25946 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_R_CL91_CW_SCRAMBLE_SHIFT 6 25947 25948 /* sc_x1_speed_override3 :: override_7 :: r_merge_mode [05:03] */ 25949 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_R_MERGE_MODE_MASK 0x0038 25950 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_R_MERGE_MODE_ALIGN 0 25951 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_R_MERGE_MODE_BITS 3 25952 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_R_MERGE_MODE_SHIFT 3 25953 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_R_MERGE_MODE_R_MERGE_MODE_BYPASS 0 25954 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_R_MERGE_MODE_R_MERGE_MODE_CL91_FC 1 25955 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_R_MERGE_MODE_R_MERGE_MODE_CL91_SINGLE_LANE 2 25956 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_R_MERGE_MODE_R_MERGE_MODE_CL91_DUAL_LANE 3 25957 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_R_MERGE_MODE_R_MERGE_MODE_CL91_QUAD_LANE 4 25958 25959 /* sc_x1_speed_override3 :: override_7 :: cl91_blksync_mode [02:00] */ 25960 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_CL91_BLKSYNC_MODE_MASK 0x0007 25961 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_CL91_BLKSYNC_MODE_ALIGN 0 25962 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_CL91_BLKSYNC_MODE_BITS 3 25963 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_CL91_BLKSYNC_MODE_SHIFT 0 25964 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_CL91_BLKSYNC_MODE_R_BLKSYNC_NO_CL91_FEC 0 25965 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_CL91_BLKSYNC_MODE_R_BLKSYNC_CL91_QUAD_LANE_FEC 1 25966 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_CL91_BLKSYNC_MODE_R_BLKSYNC_CL91_DUAL_LANE_FEC 2 25967 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_CL91_BLKSYNC_MODE_R_BLKSYNC_CL91_SINGLE_LANE_FEC 3 25968 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_CL91_BLKSYNC_MODE_R_BLKSYNC_CL91_FC_FEC 4 25969 25970 25971 /**************************************************************************** 25972 * TSC_WC4_TSC_USER1_rx_x1_status0 25973 */ 25974 /**************************************************************************** 25975 * rx_x1_status0 :: status_cl91_fec_ram1_lo 25976 */ 25977 /* rx_x1_status0 :: status_cl91_fec_ram1_lo :: two_bit_err_event_cl91_fec_ram1_lo [15:15] */ 25978 #define RX_X1_STATUS0_STATUS_CL91_FEC_RAM1_LO_TWO_BIT_ERR_EVENT_CL91_FEC_RAM1_LO_MASK 0x8000 25979 #define RX_X1_STATUS0_STATUS_CL91_FEC_RAM1_LO_TWO_BIT_ERR_EVENT_CL91_FEC_RAM1_LO_ALIGN 0 25980 #define RX_X1_STATUS0_STATUS_CL91_FEC_RAM1_LO_TWO_BIT_ERR_EVENT_CL91_FEC_RAM1_LO_BITS 1 25981 #define RX_X1_STATUS0_STATUS_CL91_FEC_RAM1_LO_TWO_BIT_ERR_EVENT_CL91_FEC_RAM1_LO_SHIFT 15 25982 25983 /* rx_x1_status0 :: status_cl91_fec_ram1_lo :: one_bit_err_event_cl91_fec_ram1_lo [14:14] */ 25984 #define RX_X1_STATUS0_STATUS_CL91_FEC_RAM1_LO_ONE_BIT_ERR_EVENT_CL91_FEC_RAM1_LO_MASK 0x4000 25985 #define RX_X1_STATUS0_STATUS_CL91_FEC_RAM1_LO_ONE_BIT_ERR_EVENT_CL91_FEC_RAM1_LO_ALIGN 0 25986 #define RX_X1_STATUS0_STATUS_CL91_FEC_RAM1_LO_ONE_BIT_ERR_EVENT_CL91_FEC_RAM1_LO_BITS 1 25987 #define RX_X1_STATUS0_STATUS_CL91_FEC_RAM1_LO_ONE_BIT_ERR_EVENT_CL91_FEC_RAM1_LO_SHIFT 14 25988 25989 /* rx_x1_status0 :: status_cl91_fec_ram1_lo :: err_event_address_cl91_fec_ram1_lo [13:00] */ 25990 #define RX_X1_STATUS0_STATUS_CL91_FEC_RAM1_LO_ERR_EVENT_ADDRESS_CL91_FEC_RAM1_LO_MASK 0x3fff 25991 #define RX_X1_STATUS0_STATUS_CL91_FEC_RAM1_LO_ERR_EVENT_ADDRESS_CL91_FEC_RAM1_LO_ALIGN 0 25992 #define RX_X1_STATUS0_STATUS_CL91_FEC_RAM1_LO_ERR_EVENT_ADDRESS_CL91_FEC_RAM1_LO_BITS 14 25993 #define RX_X1_STATUS0_STATUS_CL91_FEC_RAM1_LO_ERR_EVENT_ADDRESS_CL91_FEC_RAM1_LO_SHIFT 0 25994 25995 25996 /**************************************************************************** 25997 * rx_x1_status0 :: status_cl91_fec_ram1_hi 25998 */ 25999 /* rx_x1_status0 :: status_cl91_fec_ram1_hi :: two_bit_err_event_cl91_fec_ram1_hi [15:15] */ 26000 #define RX_X1_STATUS0_STATUS_CL91_FEC_RAM1_HI_TWO_BIT_ERR_EVENT_CL91_FEC_RAM1_HI_MASK 0x8000 26001 #define RX_X1_STATUS0_STATUS_CL91_FEC_RAM1_HI_TWO_BIT_ERR_EVENT_CL91_FEC_RAM1_HI_ALIGN 0 26002 #define RX_X1_STATUS0_STATUS_CL91_FEC_RAM1_HI_TWO_BIT_ERR_EVENT_CL91_FEC_RAM1_HI_BITS 1 26003 #define RX_X1_STATUS0_STATUS_CL91_FEC_RAM1_HI_TWO_BIT_ERR_EVENT_CL91_FEC_RAM1_HI_SHIFT 15 26004 26005 /* rx_x1_status0 :: status_cl91_fec_ram1_hi :: one_bit_err_event_cl91_fec_ram1_hi [14:14] */ 26006 #define RX_X1_STATUS0_STATUS_CL91_FEC_RAM1_HI_ONE_BIT_ERR_EVENT_CL91_FEC_RAM1_HI_MASK 0x4000 26007 #define RX_X1_STATUS0_STATUS_CL91_FEC_RAM1_HI_ONE_BIT_ERR_EVENT_CL91_FEC_RAM1_HI_ALIGN 0 26008 #define RX_X1_STATUS0_STATUS_CL91_FEC_RAM1_HI_ONE_BIT_ERR_EVENT_CL91_FEC_RAM1_HI_BITS 1 26009 #define RX_X1_STATUS0_STATUS_CL91_FEC_RAM1_HI_ONE_BIT_ERR_EVENT_CL91_FEC_RAM1_HI_SHIFT 14 26010 26011 /* rx_x1_status0 :: status_cl91_fec_ram1_hi :: err_event_address_cl91_fec_ram1_hi [13:00] */ 26012 #define RX_X1_STATUS0_STATUS_CL91_FEC_RAM1_HI_ERR_EVENT_ADDRESS_CL91_FEC_RAM1_HI_MASK 0x3fff 26013 #define RX_X1_STATUS0_STATUS_CL91_FEC_RAM1_HI_ERR_EVENT_ADDRESS_CL91_FEC_RAM1_HI_ALIGN 0 26014 #define RX_X1_STATUS0_STATUS_CL91_FEC_RAM1_HI_ERR_EVENT_ADDRESS_CL91_FEC_RAM1_HI_BITS 14 26015 #define RX_X1_STATUS0_STATUS_CL91_FEC_RAM1_HI_ERR_EVENT_ADDRESS_CL91_FEC_RAM1_HI_SHIFT 0 26016 26017 26018 /**************************************************************************** 26019 * rx_x1_status0 :: status_cl91_fec_ram2_lo 26020 */ 26021 /* rx_x1_status0 :: status_cl91_fec_ram2_lo :: two_bit_err_event_cl91_fec_ram2_lo [15:15] */ 26022 #define RX_X1_STATUS0_STATUS_CL91_FEC_RAM2_LO_TWO_BIT_ERR_EVENT_CL91_FEC_RAM2_LO_MASK 0x8000 26023 #define RX_X1_STATUS0_STATUS_CL91_FEC_RAM2_LO_TWO_BIT_ERR_EVENT_CL91_FEC_RAM2_LO_ALIGN 0 26024 #define RX_X1_STATUS0_STATUS_CL91_FEC_RAM2_LO_TWO_BIT_ERR_EVENT_CL91_FEC_RAM2_LO_BITS 1 26025 #define RX_X1_STATUS0_STATUS_CL91_FEC_RAM2_LO_TWO_BIT_ERR_EVENT_CL91_FEC_RAM2_LO_SHIFT 15 26026 26027 /* rx_x1_status0 :: status_cl91_fec_ram2_lo :: one_bit_err_event_cl91_fec_ram2_lo [14:14] */ 26028 #define RX_X1_STATUS0_STATUS_CL91_FEC_RAM2_LO_ONE_BIT_ERR_EVENT_CL91_FEC_RAM2_LO_MASK 0x4000 26029 #define RX_X1_STATUS0_STATUS_CL91_FEC_RAM2_LO_ONE_BIT_ERR_EVENT_CL91_FEC_RAM2_LO_ALIGN 0 26030 #define RX_X1_STATUS0_STATUS_CL91_FEC_RAM2_LO_ONE_BIT_ERR_EVENT_CL91_FEC_RAM2_LO_BITS 1 26031 #define RX_X1_STATUS0_STATUS_CL91_FEC_RAM2_LO_ONE_BIT_ERR_EVENT_CL91_FEC_RAM2_LO_SHIFT 14 26032 26033 /* rx_x1_status0 :: status_cl91_fec_ram2_lo :: err_event_address_cl91_fec_ram2_lo [13:00] */ 26034 #define RX_X1_STATUS0_STATUS_CL91_FEC_RAM2_LO_ERR_EVENT_ADDRESS_CL91_FEC_RAM2_LO_MASK 0x3fff 26035 #define RX_X1_STATUS0_STATUS_CL91_FEC_RAM2_LO_ERR_EVENT_ADDRESS_CL91_FEC_RAM2_LO_ALIGN 0 26036 #define RX_X1_STATUS0_STATUS_CL91_FEC_RAM2_LO_ERR_EVENT_ADDRESS_CL91_FEC_RAM2_LO_BITS 14 26037 #define RX_X1_STATUS0_STATUS_CL91_FEC_RAM2_LO_ERR_EVENT_ADDRESS_CL91_FEC_RAM2_LO_SHIFT 0 26038 26039 26040 /**************************************************************************** 26041 * rx_x1_status0 :: status_cl91_fec_ram2_hi 26042 */ 26043 /* rx_x1_status0 :: status_cl91_fec_ram2_hi :: two_bit_err_event_cl91_fec_ram2_hi [15:15] */ 26044 #define RX_X1_STATUS0_STATUS_CL91_FEC_RAM2_HI_TWO_BIT_ERR_EVENT_CL91_FEC_RAM2_HI_MASK 0x8000 26045 #define RX_X1_STATUS0_STATUS_CL91_FEC_RAM2_HI_TWO_BIT_ERR_EVENT_CL91_FEC_RAM2_HI_ALIGN 0 26046 #define RX_X1_STATUS0_STATUS_CL91_FEC_RAM2_HI_TWO_BIT_ERR_EVENT_CL91_FEC_RAM2_HI_BITS 1 26047 #define RX_X1_STATUS0_STATUS_CL91_FEC_RAM2_HI_TWO_BIT_ERR_EVENT_CL91_FEC_RAM2_HI_SHIFT 15 26048 26049 /* rx_x1_status0 :: status_cl91_fec_ram2_hi :: one_bit_err_event_cl91_fec_ram2_hi [14:14] */ 26050 #define RX_X1_STATUS0_STATUS_CL91_FEC_RAM2_HI_ONE_BIT_ERR_EVENT_CL91_FEC_RAM2_HI_MASK 0x4000 26051 #define RX_X1_STATUS0_STATUS_CL91_FEC_RAM2_HI_ONE_BIT_ERR_EVENT_CL91_FEC_RAM2_HI_ALIGN 0 26052 #define RX_X1_STATUS0_STATUS_CL91_FEC_RAM2_HI_ONE_BIT_ERR_EVENT_CL91_FEC_RAM2_HI_BITS 1 26053 #define RX_X1_STATUS0_STATUS_CL91_FEC_RAM2_HI_ONE_BIT_ERR_EVENT_CL91_FEC_RAM2_HI_SHIFT 14 26054 26055 /* rx_x1_status0 :: status_cl91_fec_ram2_hi :: err_event_address_cl91_fec_ram2_hi [13:00] */ 26056 #define RX_X1_STATUS0_STATUS_CL91_FEC_RAM2_HI_ERR_EVENT_ADDRESS_CL91_FEC_RAM2_HI_MASK 0x3fff 26057 #define RX_X1_STATUS0_STATUS_CL91_FEC_RAM2_HI_ERR_EVENT_ADDRESS_CL91_FEC_RAM2_HI_ALIGN 0 26058 #define RX_X1_STATUS0_STATUS_CL91_FEC_RAM2_HI_ERR_EVENT_ADDRESS_CL91_FEC_RAM2_HI_BITS 14 26059 #define RX_X1_STATUS0_STATUS_CL91_FEC_RAM2_HI_ERR_EVENT_ADDRESS_CL91_FEC_RAM2_HI_SHIFT 0 26060 26061 26062 /**************************************************************************** 26063 * TSC_WC4_TSC_USER1_AN_X1_SW_MGMT 26064 */ 26065 /**************************************************************************** 26066 * AN_X1_SW_MGMT :: glb_int 26067 */ 26068 /* AN_X1_SW_MGMT :: glb_int :: reserved0 [15:04] */ 26069 #define AN_X1_SW_MGMT_GLB_INT_RESERVED0_MASK 0xfff0 26070 #define AN_X1_SW_MGMT_GLB_INT_RESERVED0_ALIGN 0 26071 #define AN_X1_SW_MGMT_GLB_INT_RESERVED0_BITS 12 26072 #define AN_X1_SW_MGMT_GLB_INT_RESERVED0_SHIFT 4 26073 26074 /* AN_X1_SW_MGMT :: glb_int :: int_port3 [03:03] */ 26075 #define AN_X1_SW_MGMT_GLB_INT_INT_PORT3_MASK 0x0008 26076 #define AN_X1_SW_MGMT_GLB_INT_INT_PORT3_ALIGN 0 26077 #define AN_X1_SW_MGMT_GLB_INT_INT_PORT3_BITS 1 26078 #define AN_X1_SW_MGMT_GLB_INT_INT_PORT3_SHIFT 3 26079 26080 /* AN_X1_SW_MGMT :: glb_int :: int_port2 [02:02] */ 26081 #define AN_X1_SW_MGMT_GLB_INT_INT_PORT2_MASK 0x0004 26082 #define AN_X1_SW_MGMT_GLB_INT_INT_PORT2_ALIGN 0 26083 #define AN_X1_SW_MGMT_GLB_INT_INT_PORT2_BITS 1 26084 #define AN_X1_SW_MGMT_GLB_INT_INT_PORT2_SHIFT 2 26085 26086 /* AN_X1_SW_MGMT :: glb_int :: int_port1 [01:01] */ 26087 #define AN_X1_SW_MGMT_GLB_INT_INT_PORT1_MASK 0x0002 26088 #define AN_X1_SW_MGMT_GLB_INT_INT_PORT1_ALIGN 0 26089 #define AN_X1_SW_MGMT_GLB_INT_INT_PORT1_BITS 1 26090 #define AN_X1_SW_MGMT_GLB_INT_INT_PORT1_SHIFT 1 26091 26092 /* AN_X1_SW_MGMT :: glb_int :: int_port0 [00:00] */ 26093 #define AN_X1_SW_MGMT_GLB_INT_INT_PORT0_MASK 0x0001 26094 #define AN_X1_SW_MGMT_GLB_INT_INT_PORT0_ALIGN 0 26095 #define AN_X1_SW_MGMT_GLB_INT_INT_PORT0_BITS 1 26096 #define AN_X1_SW_MGMT_GLB_INT_INT_PORT0_SHIFT 0 26097 26098 26099 /**************************************************************************** 26100 * AN_X1_SW_MGMT :: glb_mask 26101 */ 26102 /* AN_X1_SW_MGMT :: glb_mask :: reserved0 [15:04] */ 26103 #define AN_X1_SW_MGMT_GLB_MASK_RESERVED0_MASK 0xfff0 26104 #define AN_X1_SW_MGMT_GLB_MASK_RESERVED0_ALIGN 0 26105 #define AN_X1_SW_MGMT_GLB_MASK_RESERVED0_BITS 12 26106 #define AN_X1_SW_MGMT_GLB_MASK_RESERVED0_SHIFT 4 26107 26108 /* AN_X1_SW_MGMT :: glb_mask :: int_port3_mask [03:03] */ 26109 #define AN_X1_SW_MGMT_GLB_MASK_INT_PORT3_MASK_MASK 0x0008 26110 #define AN_X1_SW_MGMT_GLB_MASK_INT_PORT3_MASK_ALIGN 0 26111 #define AN_X1_SW_MGMT_GLB_MASK_INT_PORT3_MASK_BITS 1 26112 #define AN_X1_SW_MGMT_GLB_MASK_INT_PORT3_MASK_SHIFT 3 26113 26114 /* AN_X1_SW_MGMT :: glb_mask :: int_port2_mask [02:02] */ 26115 #define AN_X1_SW_MGMT_GLB_MASK_INT_PORT2_MASK_MASK 0x0004 26116 #define AN_X1_SW_MGMT_GLB_MASK_INT_PORT2_MASK_ALIGN 0 26117 #define AN_X1_SW_MGMT_GLB_MASK_INT_PORT2_MASK_BITS 1 26118 #define AN_X1_SW_MGMT_GLB_MASK_INT_PORT2_MASK_SHIFT 2 26119 26120 /* AN_X1_SW_MGMT :: glb_mask :: int_port1_mask [01:01] */ 26121 #define AN_X1_SW_MGMT_GLB_MASK_INT_PORT1_MASK_MASK 0x0002 26122 #define AN_X1_SW_MGMT_GLB_MASK_INT_PORT1_MASK_ALIGN 0 26123 #define AN_X1_SW_MGMT_GLB_MASK_INT_PORT1_MASK_BITS 1 26124 #define AN_X1_SW_MGMT_GLB_MASK_INT_PORT1_MASK_SHIFT 1 26125 26126 /* AN_X1_SW_MGMT :: glb_mask :: int_port0_mask [00:00] */ 26127 #define AN_X1_SW_MGMT_GLB_MASK_INT_PORT0_MASK_MASK 0x0001 26128 #define AN_X1_SW_MGMT_GLB_MASK_INT_PORT0_MASK_ALIGN 0 26129 #define AN_X1_SW_MGMT_GLB_MASK_INT_PORT0_MASK_BITS 1 26130 #define AN_X1_SW_MGMT_GLB_MASK_INT_PORT0_MASK_SHIFT 0 26131 26132 26133 /**************************************************************************** 26134 * TSC_WC4_TSC_USER2_TX_X2_Control0 26135 */ 26136 /**************************************************************************** 26137 * TX_X2_Control0 :: cl82_0 26138 */ 26139 /* TX_X2_Control0 :: cl82_0 :: reserved0 [15:11] */ 26140 #define TX_X2_CONTROL0_CL82_0_RESERVED0_MASK 0xf800 26141 #define TX_X2_CONTROL0_CL82_0_RESERVED0_ALIGN 0 26142 #define TX_X2_CONTROL0_CL82_0_RESERVED0_BITS 5 26143 #define TX_X2_CONTROL0_CL82_0_RESERVED0_SHIFT 11 26144 26145 /* TX_X2_Control0 :: cl82_0 :: cl82_bypass_txsm [10:10] */ 26146 #define TX_X2_CONTROL0_CL82_0_CL82_BYPASS_TXSM_MASK 0x0400 26147 #define TX_X2_CONTROL0_CL82_0_CL82_BYPASS_TXSM_ALIGN 0 26148 #define TX_X2_CONTROL0_CL82_0_CL82_BYPASS_TXSM_BITS 1 26149 #define TX_X2_CONTROL0_CL82_0_CL82_BYPASS_TXSM_SHIFT 10 26150 26151 /* TX_X2_Control0 :: cl82_0 :: reserved1 [09:07] */ 26152 #define TX_X2_CONTROL0_CL82_0_RESERVED1_MASK 0x0380 26153 #define TX_X2_CONTROL0_CL82_0_RESERVED1_ALIGN 0 26154 #define TX_X2_CONTROL0_CL82_0_RESERVED1_BITS 3 26155 #define TX_X2_CONTROL0_CL82_0_RESERVED1_SHIFT 7 26156 26157 /* TX_X2_Control0 :: cl82_0 :: cl82_tx_li_enable [06:06] */ 26158 #define TX_X2_CONTROL0_CL82_0_CL82_TX_LI_ENABLE_MASK 0x0040 26159 #define TX_X2_CONTROL0_CL82_0_CL82_TX_LI_ENABLE_ALIGN 0 26160 #define TX_X2_CONTROL0_CL82_0_CL82_TX_LI_ENABLE_BITS 1 26161 #define TX_X2_CONTROL0_CL82_0_CL82_TX_LI_ENABLE_SHIFT 6 26162 26163 /* TX_X2_Control0 :: cl82_0 :: cl82_tx_lf_enable [05:05] */ 26164 #define TX_X2_CONTROL0_CL82_0_CL82_TX_LF_ENABLE_MASK 0x0020 26165 #define TX_X2_CONTROL0_CL82_0_CL82_TX_LF_ENABLE_ALIGN 0 26166 #define TX_X2_CONTROL0_CL82_0_CL82_TX_LF_ENABLE_BITS 1 26167 #define TX_X2_CONTROL0_CL82_0_CL82_TX_LF_ENABLE_SHIFT 5 26168 26169 /* TX_X2_Control0 :: cl82_0 :: cl82_tx_rf_enable [04:04] */ 26170 #define TX_X2_CONTROL0_CL82_0_CL82_TX_RF_ENABLE_MASK 0x0010 26171 #define TX_X2_CONTROL0_CL82_0_CL82_TX_RF_ENABLE_ALIGN 0 26172 #define TX_X2_CONTROL0_CL82_0_CL82_TX_RF_ENABLE_BITS 1 26173 #define TX_X2_CONTROL0_CL82_0_CL82_TX_RF_ENABLE_SHIFT 4 26174 26175 /* TX_X2_Control0 :: cl82_0 :: reserved2 [03:00] */ 26176 #define TX_X2_CONTROL0_CL82_0_RESERVED2_MASK 0x000f 26177 #define TX_X2_CONTROL0_CL82_0_RESERVED2_ALIGN 0 26178 #define TX_X2_CONTROL0_CL82_0_RESERVED2_BITS 4 26179 #define TX_X2_CONTROL0_CL82_0_RESERVED2_SHIFT 0 26180 26181 26182 /**************************************************************************** 26183 * TSC_WC4_TSC_USER2_TX_X2_Status0 26184 */ 26185 /**************************************************************************** 26186 * TX_X2_Status0 :: cl82_tx_status_0 26187 */ 26188 /* TX_X2_Status0 :: cl82_tx_status_0 :: reserved0 [15:06] */ 26189 #define TX_X2_STATUS0_CL82_TX_STATUS_0_RESERVED0_MASK 0xffc0 26190 #define TX_X2_STATUS0_CL82_TX_STATUS_0_RESERVED0_ALIGN 0 26191 #define TX_X2_STATUS0_CL82_TX_STATUS_0_RESERVED0_BITS 10 26192 #define TX_X2_STATUS0_CL82_TX_STATUS_0_RESERVED0_SHIFT 6 26193 26194 /* TX_X2_Status0 :: cl82_tx_status_0 :: t_type_coded [05:03] */ 26195 #define TX_X2_STATUS0_CL82_TX_STATUS_0_T_TYPE_CODED_MASK 0x0038 26196 #define TX_X2_STATUS0_CL82_TX_STATUS_0_T_TYPE_CODED_ALIGN 0 26197 #define TX_X2_STATUS0_CL82_TX_STATUS_0_T_TYPE_CODED_BITS 3 26198 #define TX_X2_STATUS0_CL82_TX_STATUS_0_T_TYPE_CODED_SHIFT 3 26199 #define TX_X2_STATUS0_CL82_TX_STATUS_0_T_TYPE_CODED_T_TYPE_B1 5 26200 #define TX_X2_STATUS0_CL82_TX_STATUS_0_T_TYPE_CODED_T_TYPE_C 4 26201 #define TX_X2_STATUS0_CL82_TX_STATUS_0_T_TYPE_CODED_T_TYPE_S 3 26202 #define TX_X2_STATUS0_CL82_TX_STATUS_0_T_TYPE_CODED_T_TYPE_T 2 26203 #define TX_X2_STATUS0_CL82_TX_STATUS_0_T_TYPE_CODED_T_TYPE_D 1 26204 #define TX_X2_STATUS0_CL82_TX_STATUS_0_T_TYPE_CODED_T_TYPE_E 0 26205 26206 /* TX_X2_Status0 :: cl82_tx_status_0 :: txsm_state [02:00] */ 26207 #define TX_X2_STATUS0_CL82_TX_STATUS_0_TXSM_STATE_MASK 0x0007 26208 #define TX_X2_STATUS0_CL82_TX_STATUS_0_TXSM_STATE_ALIGN 0 26209 #define TX_X2_STATUS0_CL82_TX_STATUS_0_TXSM_STATE_BITS 3 26210 #define TX_X2_STATUS0_CL82_TX_STATUS_0_TXSM_STATE_SHIFT 0 26211 #define TX_X2_STATUS0_CL82_TX_STATUS_0_TXSM_STATE_TX_HIG_END 6 26212 #define TX_X2_STATUS0_CL82_TX_STATUS_0_TXSM_STATE_TX_HIG_START 5 26213 #define TX_X2_STATUS0_CL82_TX_STATUS_0_TXSM_STATE_TX_E 4 26214 #define TX_X2_STATUS0_CL82_TX_STATUS_0_TXSM_STATE_TX_T 3 26215 #define TX_X2_STATUS0_CL82_TX_STATUS_0_TXSM_STATE_TX_D 2 26216 #define TX_X2_STATUS0_CL82_TX_STATUS_0_TXSM_STATE_TX_C 1 26217 #define TX_X2_STATUS0_CL82_TX_STATUS_0_TXSM_STATE_TX_INIT 0 26218 26219 26220 /**************************************************************************** 26221 * TX_X2_Status0 :: cl82_tx_status_1 26222 */ 26223 /* TX_X2_Status0 :: cl82_tx_status_1 :: reserved0 [15:07] */ 26224 #define TX_X2_STATUS0_CL82_TX_STATUS_1_RESERVED0_MASK 0xff80 26225 #define TX_X2_STATUS0_CL82_TX_STATUS_1_RESERVED0_ALIGN 0 26226 #define TX_X2_STATUS0_CL82_TX_STATUS_1_RESERVED0_BITS 9 26227 #define TX_X2_STATUS0_CL82_TX_STATUS_1_RESERVED0_SHIFT 7 26228 26229 /* TX_X2_Status0 :: cl82_tx_status_1 :: ltxsm_state [06:00] */ 26230 #define TX_X2_STATUS0_CL82_TX_STATUS_1_LTXSM_STATE_MASK 0x007f 26231 #define TX_X2_STATUS0_CL82_TX_STATUS_1_LTXSM_STATE_ALIGN 0 26232 #define TX_X2_STATUS0_CL82_TX_STATUS_1_LTXSM_STATE_BITS 7 26233 #define TX_X2_STATUS0_CL82_TX_STATUS_1_LTXSM_STATE_SHIFT 0 26234 #define TX_X2_STATUS0_CL82_TX_STATUS_1_LTXSM_STATE_TX_HIG_END 64 26235 #define TX_X2_STATUS0_CL82_TX_STATUS_1_LTXSM_STATE_TX_HIG_START 32 26236 #define TX_X2_STATUS0_CL82_TX_STATUS_1_LTXSM_STATE_TX_E 16 26237 #define TX_X2_STATUS0_CL82_TX_STATUS_1_LTXSM_STATE_TX_T 8 26238 #define TX_X2_STATUS0_CL82_TX_STATUS_1_LTXSM_STATE_TX_D 4 26239 #define TX_X2_STATUS0_CL82_TX_STATUS_1_LTXSM_STATE_TX_C 2 26240 #define TX_X2_STATUS0_CL82_TX_STATUS_1_LTXSM_STATE_TX_INIT 1 26241 26242 26243 /**************************************************************************** 26244 * TSC_WC4_TSC_USER2_RX_X2_Control0 26245 */ 26246 /**************************************************************************** 26247 * RX_X2_Control0 :: misc_0 26248 */ 26249 /* RX_X2_Control0 :: misc_0 :: reserved0 [15:02] */ 26250 #define RX_X2_CONTROL0_MISC_0_RESERVED0_MASK 0xfffc 26251 #define RX_X2_CONTROL0_MISC_0_RESERVED0_ALIGN 0 26252 #define RX_X2_CONTROL0_MISC_0_RESERVED0_BITS 14 26253 #define RX_X2_CONTROL0_MISC_0_RESERVED0_SHIFT 2 26254 26255 /* RX_X2_Control0 :: misc_0 :: dis_cl82_bermon [01:01] */ 26256 #define RX_X2_CONTROL0_MISC_0_DIS_CL82_BERMON_MASK 0x0002 26257 #define RX_X2_CONTROL0_MISC_0_DIS_CL82_BERMON_ALIGN 0 26258 #define RX_X2_CONTROL0_MISC_0_DIS_CL82_BERMON_BITS 1 26259 #define RX_X2_CONTROL0_MISC_0_DIS_CL82_BERMON_SHIFT 1 26260 26261 /* RX_X2_Control0 :: misc_0 :: bypass_cl82rxsm [00:00] */ 26262 #define RX_X2_CONTROL0_MISC_0_BYPASS_CL82RXSM_MASK 0x0001 26263 #define RX_X2_CONTROL0_MISC_0_BYPASS_CL82RXSM_ALIGN 0 26264 #define RX_X2_CONTROL0_MISC_0_BYPASS_CL82RXSM_BITS 1 26265 #define RX_X2_CONTROL0_MISC_0_BYPASS_CL82RXSM_SHIFT 0 26266 26267 26268 /**************************************************************************** 26269 * RX_X2_Control0 :: misc_1 26270 */ 26271 /* RX_X2_Control0 :: misc_1 :: reserved0 [15:10] */ 26272 #define RX_X2_CONTROL0_MISC_1_RESERVED0_MASK 0xfc00 26273 #define RX_X2_CONTROL0_MISC_1_RESERVED0_ALIGN 0 26274 #define RX_X2_CONTROL0_MISC_1_RESERVED0_BITS 6 26275 #define RX_X2_CONTROL0_MISC_1_RESERVED0_SHIFT 10 26276 26277 /* RX_X2_Control0 :: misc_1 :: cl82_rx_li_enable [09:09] */ 26278 #define RX_X2_CONTROL0_MISC_1_CL82_RX_LI_ENABLE_MASK 0x0200 26279 #define RX_X2_CONTROL0_MISC_1_CL82_RX_LI_ENABLE_ALIGN 0 26280 #define RX_X2_CONTROL0_MISC_1_CL82_RX_LI_ENABLE_BITS 1 26281 #define RX_X2_CONTROL0_MISC_1_CL82_RX_LI_ENABLE_SHIFT 9 26282 26283 /* RX_X2_Control0 :: misc_1 :: reserved1 [08:02] */ 26284 #define RX_X2_CONTROL0_MISC_1_RESERVED1_MASK 0x01fc 26285 #define RX_X2_CONTROL0_MISC_1_RESERVED1_ALIGN 0 26286 #define RX_X2_CONTROL0_MISC_1_RESERVED1_BITS 7 26287 #define RX_X2_CONTROL0_MISC_1_RESERVED1_SHIFT 2 26288 26289 /* RX_X2_Control0 :: misc_1 :: cl82_rx_lf_enable [01:01] */ 26290 #define RX_X2_CONTROL0_MISC_1_CL82_RX_LF_ENABLE_MASK 0x0002 26291 #define RX_X2_CONTROL0_MISC_1_CL82_RX_LF_ENABLE_ALIGN 0 26292 #define RX_X2_CONTROL0_MISC_1_CL82_RX_LF_ENABLE_BITS 1 26293 #define RX_X2_CONTROL0_MISC_1_CL82_RX_LF_ENABLE_SHIFT 1 26294 26295 /* RX_X2_Control0 :: misc_1 :: cl82_rx_rf_enable [00:00] */ 26296 #define RX_X2_CONTROL0_MISC_1_CL82_RX_RF_ENABLE_MASK 0x0001 26297 #define RX_X2_CONTROL0_MISC_1_CL82_RX_RF_ENABLE_ALIGN 0 26298 #define RX_X2_CONTROL0_MISC_1_CL82_RX_RF_ENABLE_BITS 1 26299 #define RX_X2_CONTROL0_MISC_1_CL82_RX_RF_ENABLE_SHIFT 0 26300 26301 26302 /**************************************************************************** 26303 * TSC_WC4_TSC_USER2_CL82 26304 */ 26305 /**************************************************************************** 26306 * CL82 :: rx_live_status 26307 */ 26308 /* CL82 :: rx_live_status :: reserved0 [15:15] */ 26309 #define CL82_RX_LIVE_STATUS_RESERVED0_MASK 0x8000 26310 #define CL82_RX_LIVE_STATUS_RESERVED0_ALIGN 0 26311 #define CL82_RX_LIVE_STATUS_RESERVED0_BITS 1 26312 #define CL82_RX_LIVE_STATUS_RESERVED0_SHIFT 15 26313 26314 /* CL82 :: rx_live_status :: deskew_state [14:13] */ 26315 #define CL82_RX_LIVE_STATUS_DESKEW_STATE_MASK 0x6000 26316 #define CL82_RX_LIVE_STATUS_DESKEW_STATE_ALIGN 0 26317 #define CL82_RX_LIVE_STATUS_DESKEW_STATE_BITS 2 26318 #define CL82_RX_LIVE_STATUS_DESKEW_STATE_SHIFT 13 26319 26320 /* CL82 :: rx_live_status :: r_type_coded [12:07] */ 26321 #define CL82_RX_LIVE_STATUS_R_TYPE_CODED_MASK 0x1f80 26322 #define CL82_RX_LIVE_STATUS_R_TYPE_CODED_ALIGN 0 26323 #define CL82_RX_LIVE_STATUS_R_TYPE_CODED_BITS 6 26324 #define CL82_RX_LIVE_STATUS_R_TYPE_CODED_SHIFT 7 26325 #define CL82_RX_LIVE_STATUS_R_TYPE_CODED_R_TYPE_B1 32 26326 #define CL82_RX_LIVE_STATUS_R_TYPE_CODED_R_TYPE_C 16 26327 #define CL82_RX_LIVE_STATUS_R_TYPE_CODED_R_TYPE_S 8 26328 #define CL82_RX_LIVE_STATUS_R_TYPE_CODED_R_TYPE_T 4 26329 #define CL82_RX_LIVE_STATUS_R_TYPE_CODED_R_TYPE_D 2 26330 #define CL82_RX_LIVE_STATUS_R_TYPE_CODED_R_TYPE_E 1 26331 26332 /* CL82 :: rx_live_status :: current_rxsm_state [06:00] */ 26333 #define CL82_RX_LIVE_STATUS_CURRENT_RXSM_STATE_MASK 0x007f 26334 #define CL82_RX_LIVE_STATUS_CURRENT_RXSM_STATE_ALIGN 0 26335 #define CL82_RX_LIVE_STATUS_CURRENT_RXSM_STATE_BITS 7 26336 #define CL82_RX_LIVE_STATUS_CURRENT_RXSM_STATE_SHIFT 0 26337 #define CL82_RX_LIVE_STATUS_CURRENT_RXSM_STATE_RX_HIG_END 64 26338 #define CL82_RX_LIVE_STATUS_CURRENT_RXSM_STATE_RX_HIG_START 32 26339 #define CL82_RX_LIVE_STATUS_CURRENT_RXSM_STATE_RX_E 16 26340 #define CL82_RX_LIVE_STATUS_CURRENT_RXSM_STATE_RX_T 8 26341 #define CL82_RX_LIVE_STATUS_CURRENT_RXSM_STATE_RX_D 4 26342 #define CL82_RX_LIVE_STATUS_CURRENT_RXSM_STATE_RX_C 2 26343 #define CL82_RX_LIVE_STATUS_CURRENT_RXSM_STATE_RX_INIT 1 26344 26345 26346 /**************************************************************************** 26347 * CL82 :: rx_latched_status 26348 */ 26349 /* CL82 :: rx_latched_status :: reserved0 [15:09] */ 26350 #define CL82_RX_LATCHED_STATUS_RESERVED0_MASK 0xfe00 26351 #define CL82_RX_LATCHED_STATUS_RESERVED0_ALIGN 0 26352 #define CL82_RX_LATCHED_STATUS_RESERVED0_BITS 7 26353 #define CL82_RX_LATCHED_STATUS_RESERVED0_SHIFT 9 26354 26355 /* CL82 :: rx_latched_status :: history_rxsm_state [08:02] */ 26356 #define CL82_RX_LATCHED_STATUS_HISTORY_RXSM_STATE_MASK 0x01fc 26357 #define CL82_RX_LATCHED_STATUS_HISTORY_RXSM_STATE_ALIGN 0 26358 #define CL82_RX_LATCHED_STATUS_HISTORY_RXSM_STATE_BITS 7 26359 #define CL82_RX_LATCHED_STATUS_HISTORY_RXSM_STATE_SHIFT 2 26360 #define CL82_RX_LATCHED_STATUS_HISTORY_RXSM_STATE_RX_HIG_END 64 26361 #define CL82_RX_LATCHED_STATUS_HISTORY_RXSM_STATE_RX_HIG_START 32 26362 #define CL82_RX_LATCHED_STATUS_HISTORY_RXSM_STATE_RX_E 16 26363 #define CL82_RX_LATCHED_STATUS_HISTORY_RXSM_STATE_RX_T 8 26364 #define CL82_RX_LATCHED_STATUS_HISTORY_RXSM_STATE_RX_D 4 26365 #define CL82_RX_LATCHED_STATUS_HISTORY_RXSM_STATE_RX_C 2 26366 #define CL82_RX_LATCHED_STATUS_HISTORY_RXSM_STATE_RX_INIT 1 26367 26368 /* CL82 :: rx_latched_status :: deskew_his_state [01:00] */ 26369 #define CL82_RX_LATCHED_STATUS_DESKEW_HIS_STATE_MASK 0x0003 26370 #define CL82_RX_LATCHED_STATUS_DESKEW_HIS_STATE_ALIGN 0 26371 #define CL82_RX_LATCHED_STATUS_DESKEW_HIS_STATE_BITS 2 26372 #define CL82_RX_LATCHED_STATUS_DESKEW_HIS_STATE_SHIFT 0 26373 #define CL82_RX_LATCHED_STATUS_DESKEW_HIS_STATE_ALIGN_ACQUIRED 2 26374 #define CL82_RX_LATCHED_STATUS_DESKEW_HIS_STATE_LOSS_OF_ALIGNMENT 1 26375 26376 26377 /**************************************************************************** 26378 * CL82 :: ber_lo 26379 */ 26380 /* CL82 :: ber_lo :: reserved0 [15:08] */ 26381 #define CL82_BER_LO_RESERVED0_MASK 0xff00 26382 #define CL82_BER_LO_RESERVED0_ALIGN 0 26383 #define CL82_BER_LO_RESERVED0_BITS 8 26384 #define CL82_BER_LO_RESERVED0_SHIFT 8 26385 26386 /* CL82 :: ber_lo :: ber_lo [07:00] */ 26387 #define CL82_BER_LO_BER_LO_MASK 0x00ff 26388 #define CL82_BER_LO_BER_LO_ALIGN 0 26389 #define CL82_BER_LO_BER_LO_BITS 8 26390 #define CL82_BER_LO_BER_LO_SHIFT 0 26391 26392 26393 /**************************************************************************** 26394 * CL82 :: ber_ho 26395 */ 26396 /* CL82 :: ber_ho :: reserved0 [15:14] */ 26397 #define CL82_BER_HO_RESERVED0_MASK 0xc000 26398 #define CL82_BER_HO_RESERVED0_ALIGN 0 26399 #define CL82_BER_HO_RESERVED0_BITS 2 26400 #define CL82_BER_HO_RESERVED0_SHIFT 14 26401 26402 /* CL82 :: ber_ho :: ber_ho [13:00] */ 26403 #define CL82_BER_HO_BER_HO_MASK 0x3fff 26404 #define CL82_BER_HO_BER_HO_ALIGN 0 26405 #define CL82_BER_HO_BER_HO_BITS 14 26406 #define CL82_BER_HO_BER_HO_SHIFT 0 26407 26408 26409 /**************************************************************************** 26410 * CL82 :: errored_blocks_ho 26411 */ 26412 /* CL82 :: errored_blocks_ho :: errored_blocks_ho_present [15:15] */ 26413 #define CL82_ERRORED_BLOCKS_HO_ERRORED_BLOCKS_HO_PRESENT_MASK 0x8000 26414 #define CL82_ERRORED_BLOCKS_HO_ERRORED_BLOCKS_HO_PRESENT_ALIGN 0 26415 #define CL82_ERRORED_BLOCKS_HO_ERRORED_BLOCKS_HO_PRESENT_BITS 1 26416 #define CL82_ERRORED_BLOCKS_HO_ERRORED_BLOCKS_HO_PRESENT_SHIFT 15 26417 26418 /* CL82 :: errored_blocks_ho :: reserved0 [14:14] */ 26419 #define CL82_ERRORED_BLOCKS_HO_RESERVED0_MASK 0x4000 26420 #define CL82_ERRORED_BLOCKS_HO_RESERVED0_ALIGN 0 26421 #define CL82_ERRORED_BLOCKS_HO_RESERVED0_BITS 1 26422 #define CL82_ERRORED_BLOCKS_HO_RESERVED0_SHIFT 14 26423 26424 /* CL82 :: errored_blocks_ho :: errored_blocks_ho [13:00] */ 26425 #define CL82_ERRORED_BLOCKS_HO_ERRORED_BLOCKS_HO_MASK 0x3fff 26426 #define CL82_ERRORED_BLOCKS_HO_ERRORED_BLOCKS_HO_ALIGN 0 26427 #define CL82_ERRORED_BLOCKS_HO_ERRORED_BLOCKS_HO_BITS 14 26428 #define CL82_ERRORED_BLOCKS_HO_ERRORED_BLOCKS_HO_SHIFT 0 26429 26430 26431 /**************************************************************************** 26432 * TSC_WC4_TSC_USER4_pmd_x4 26433 */ 26434 /**************************************************************************** 26435 * pmd_x4 :: control 26436 */ 26437 /* pmd_x4 :: control :: reserved0 [15:13] */ 26438 #define PMD_X4_CONTROL_RESERVED0_MASK 0xe000 26439 #define PMD_X4_CONTROL_RESERVED0_ALIGN 0 26440 #define PMD_X4_CONTROL_RESERVED0_BITS 3 26441 #define PMD_X4_CONTROL_RESERVED0_SHIFT 13 26442 26443 /* pmd_x4 :: control :: osr_mode [12:09] */ 26444 #define PMD_X4_CONTROL_OSR_MODE_MASK 0x1e00 26445 #define PMD_X4_CONTROL_OSR_MODE_ALIGN 0 26446 #define PMD_X4_CONTROL_OSR_MODE_BITS 4 26447 #define PMD_X4_CONTROL_OSR_MODE_SHIFT 9 26448 26449 /* pmd_x4 :: control :: tx_disable [08:08] */ 26450 #define PMD_X4_CONTROL_TX_DISABLE_MASK 0x0100 26451 #define PMD_X4_CONTROL_TX_DISABLE_ALIGN 0 26452 #define PMD_X4_CONTROL_TX_DISABLE_BITS 1 26453 #define PMD_X4_CONTROL_TX_DISABLE_SHIFT 8 26454 26455 /* pmd_x4 :: control :: reserved1 [07:04] */ 26456 #define PMD_X4_CONTROL_RESERVED1_MASK 0x00f0 26457 #define PMD_X4_CONTROL_RESERVED1_ALIGN 0 26458 #define PMD_X4_CONTROL_RESERVED1_BITS 4 26459 #define PMD_X4_CONTROL_RESERVED1_SHIFT 4 26460 26461 /* pmd_x4 :: control :: ln_rx_h_pwrdn [03:03] */ 26462 #define PMD_X4_CONTROL_LN_RX_H_PWRDN_MASK 0x0008 26463 #define PMD_X4_CONTROL_LN_RX_H_PWRDN_ALIGN 0 26464 #define PMD_X4_CONTROL_LN_RX_H_PWRDN_BITS 1 26465 #define PMD_X4_CONTROL_LN_RX_H_PWRDN_SHIFT 3 26466 26467 /* pmd_x4 :: control :: ln_tx_h_pwrdn [02:02] */ 26468 #define PMD_X4_CONTROL_LN_TX_H_PWRDN_MASK 0x0004 26469 #define PMD_X4_CONTROL_LN_TX_H_PWRDN_ALIGN 0 26470 #define PMD_X4_CONTROL_LN_TX_H_PWRDN_BITS 1 26471 #define PMD_X4_CONTROL_LN_TX_H_PWRDN_SHIFT 2 26472 26473 /* pmd_x4 :: control :: ln_h_rstb [01:01] */ 26474 #define PMD_X4_CONTROL_LN_H_RSTB_MASK 0x0002 26475 #define PMD_X4_CONTROL_LN_H_RSTB_ALIGN 0 26476 #define PMD_X4_CONTROL_LN_H_RSTB_BITS 1 26477 #define PMD_X4_CONTROL_LN_H_RSTB_SHIFT 1 26478 26479 /* pmd_x4 :: control :: ln_dp_h_rstb [00:00] */ 26480 #define PMD_X4_CONTROL_LN_DP_H_RSTB_MASK 0x0001 26481 #define PMD_X4_CONTROL_LN_DP_H_RSTB_ALIGN 0 26482 #define PMD_X4_CONTROL_LN_DP_H_RSTB_BITS 1 26483 #define PMD_X4_CONTROL_LN_DP_H_RSTB_SHIFT 0 26484 26485 26486 /**************************************************************************** 26487 * pmd_x4 :: mode 26488 */ 26489 /* pmd_x4 :: mode :: lane_mode [15:00] */ 26490 #define PMD_X4_MODE_LANE_MODE_MASK 0xffff 26491 #define PMD_X4_MODE_LANE_MODE_ALIGN 0 26492 #define PMD_X4_MODE_LANE_MODE_BITS 16 26493 #define PMD_X4_MODE_LANE_MODE_SHIFT 0 26494 26495 26496 /**************************************************************************** 26497 * pmd_x4 :: status 26498 */ 26499 /* pmd_x4 :: status :: reserved0 [15:04] */ 26500 #define PMD_X4_STATUS_RESERVED0_MASK 0xfff0 26501 #define PMD_X4_STATUS_RESERVED0_ALIGN 0 26502 #define PMD_X4_STATUS_RESERVED0_BITS 12 26503 #define PMD_X4_STATUS_RESERVED0_SHIFT 4 26504 26505 /* pmd_x4 :: status :: tx_clk_vld_sts [03:03] */ 26506 #define PMD_X4_STATUS_TX_CLK_VLD_STS_MASK 0x0008 26507 #define PMD_X4_STATUS_TX_CLK_VLD_STS_ALIGN 0 26508 #define PMD_X4_STATUS_TX_CLK_VLD_STS_BITS 1 26509 #define PMD_X4_STATUS_TX_CLK_VLD_STS_SHIFT 3 26510 26511 /* pmd_x4 :: status :: rx_clk_vld_sts [02:02] */ 26512 #define PMD_X4_STATUS_RX_CLK_VLD_STS_MASK 0x0004 26513 #define PMD_X4_STATUS_RX_CLK_VLD_STS_ALIGN 0 26514 #define PMD_X4_STATUS_RX_CLK_VLD_STS_BITS 1 26515 #define PMD_X4_STATUS_RX_CLK_VLD_STS_SHIFT 2 26516 26517 /* pmd_x4 :: status :: signal_detect_sts [01:01] */ 26518 #define PMD_X4_STATUS_SIGNAL_DETECT_STS_MASK 0x0002 26519 #define PMD_X4_STATUS_SIGNAL_DETECT_STS_ALIGN 0 26520 #define PMD_X4_STATUS_SIGNAL_DETECT_STS_BITS 1 26521 #define PMD_X4_STATUS_SIGNAL_DETECT_STS_SHIFT 1 26522 26523 /* pmd_x4 :: status :: rx_lock_sts [00:00] */ 26524 #define PMD_X4_STATUS_RX_LOCK_STS_MASK 0x0001 26525 #define PMD_X4_STATUS_RX_LOCK_STS_ALIGN 0 26526 #define PMD_X4_STATUS_RX_LOCK_STS_BITS 1 26527 #define PMD_X4_STATUS_RX_LOCK_STS_SHIFT 0 26528 26529 26530 /**************************************************************************** 26531 * pmd_x4 :: latch_status 26532 */ 26533 /* pmd_x4 :: latch_status :: reserved0 [15:11] */ 26534 #define PMD_X4_LATCH_STATUS_RESERVED0_MASK 0xf800 26535 #define PMD_X4_LATCH_STATUS_RESERVED0_ALIGN 0 26536 #define PMD_X4_LATCH_STATUS_RESERVED0_BITS 5 26537 #define PMD_X4_LATCH_STATUS_RESERVED0_SHIFT 11 26538 26539 /* pmd_x4 :: latch_status :: rx_clk_vld_live [10:10] */ 26540 #define PMD_X4_LATCH_STATUS_RX_CLK_VLD_LIVE_MASK 0x0400 26541 #define PMD_X4_LATCH_STATUS_RX_CLK_VLD_LIVE_ALIGN 0 26542 #define PMD_X4_LATCH_STATUS_RX_CLK_VLD_LIVE_BITS 1 26543 #define PMD_X4_LATCH_STATUS_RX_CLK_VLD_LIVE_SHIFT 10 26544 26545 /* pmd_x4 :: latch_status :: signal_detect_live [09:09] */ 26546 #define PMD_X4_LATCH_STATUS_SIGNAL_DETECT_LIVE_MASK 0x0200 26547 #define PMD_X4_LATCH_STATUS_SIGNAL_DETECT_LIVE_ALIGN 0 26548 #define PMD_X4_LATCH_STATUS_SIGNAL_DETECT_LIVE_BITS 1 26549 #define PMD_X4_LATCH_STATUS_SIGNAL_DETECT_LIVE_SHIFT 9 26550 26551 /* pmd_x4 :: latch_status :: rx_lock_live [08:08] */ 26552 #define PMD_X4_LATCH_STATUS_RX_LOCK_LIVE_MASK 0x0100 26553 #define PMD_X4_LATCH_STATUS_RX_LOCK_LIVE_ALIGN 0 26554 #define PMD_X4_LATCH_STATUS_RX_LOCK_LIVE_BITS 1 26555 #define PMD_X4_LATCH_STATUS_RX_LOCK_LIVE_SHIFT 8 26556 26557 /* pmd_x4 :: latch_status :: reserved1 [07:06] */ 26558 #define PMD_X4_LATCH_STATUS_RESERVED1_MASK 0x00c0 26559 #define PMD_X4_LATCH_STATUS_RESERVED1_ALIGN 0 26560 #define PMD_X4_LATCH_STATUS_RESERVED1_BITS 2 26561 #define PMD_X4_LATCH_STATUS_RESERVED1_SHIFT 6 26562 26563 /* pmd_x4 :: latch_status :: rx_clk_vld_LH [05:05] */ 26564 #define PMD_X4_LATCH_STATUS_RX_CLK_VLD_LH_MASK 0x0020 26565 #define PMD_X4_LATCH_STATUS_RX_CLK_VLD_LH_ALIGN 0 26566 #define PMD_X4_LATCH_STATUS_RX_CLK_VLD_LH_BITS 1 26567 #define PMD_X4_LATCH_STATUS_RX_CLK_VLD_LH_SHIFT 5 26568 26569 /* pmd_x4 :: latch_status :: rx_clk_vld_LL [04:04] */ 26570 #define PMD_X4_LATCH_STATUS_RX_CLK_VLD_LL_MASK 0x0010 26571 #define PMD_X4_LATCH_STATUS_RX_CLK_VLD_LL_ALIGN 0 26572 #define PMD_X4_LATCH_STATUS_RX_CLK_VLD_LL_BITS 1 26573 #define PMD_X4_LATCH_STATUS_RX_CLK_VLD_LL_SHIFT 4 26574 26575 /* pmd_x4 :: latch_status :: signal_detect_LH [03:03] */ 26576 #define PMD_X4_LATCH_STATUS_SIGNAL_DETECT_LH_MASK 0x0008 26577 #define PMD_X4_LATCH_STATUS_SIGNAL_DETECT_LH_ALIGN 0 26578 #define PMD_X4_LATCH_STATUS_SIGNAL_DETECT_LH_BITS 1 26579 #define PMD_X4_LATCH_STATUS_SIGNAL_DETECT_LH_SHIFT 3 26580 26581 /* pmd_x4 :: latch_status :: signal_detect_LL [02:02] */ 26582 #define PMD_X4_LATCH_STATUS_SIGNAL_DETECT_LL_MASK 0x0004 26583 #define PMD_X4_LATCH_STATUS_SIGNAL_DETECT_LL_ALIGN 0 26584 #define PMD_X4_LATCH_STATUS_SIGNAL_DETECT_LL_BITS 1 26585 #define PMD_X4_LATCH_STATUS_SIGNAL_DETECT_LL_SHIFT 2 26586 26587 /* pmd_x4 :: latch_status :: rx_lock_LH [01:01] */ 26588 #define PMD_X4_LATCH_STATUS_RX_LOCK_LH_MASK 0x0002 26589 #define PMD_X4_LATCH_STATUS_RX_LOCK_LH_ALIGN 0 26590 #define PMD_X4_LATCH_STATUS_RX_LOCK_LH_BITS 1 26591 #define PMD_X4_LATCH_STATUS_RX_LOCK_LH_SHIFT 1 26592 26593 /* pmd_x4 :: latch_status :: rx_lock_LL [00:00] */ 26594 #define PMD_X4_LATCH_STATUS_RX_LOCK_LL_MASK 0x0001 26595 #define PMD_X4_LATCH_STATUS_RX_LOCK_LL_ALIGN 0 26596 #define PMD_X4_LATCH_STATUS_RX_LOCK_LL_BITS 1 26597 #define PMD_X4_LATCH_STATUS_RX_LOCK_LL_SHIFT 0 26598 26599 26600 /**************************************************************************** 26601 * pmd_x4 :: override 26602 */ 26603 /* pmd_x4 :: override :: reserved0 [15:08] */ 26604 #define PMD_X4_OVERRIDE_RESERVED0_MASK 0xff00 26605 #define PMD_X4_OVERRIDE_RESERVED0_ALIGN 0 26606 #define PMD_X4_OVERRIDE_RESERVED0_BITS 8 26607 #define PMD_X4_OVERRIDE_RESERVED0_SHIFT 8 26608 26609 /* pmd_x4 :: override :: tx_clk_vld_ovrd [07:07] */ 26610 #define PMD_X4_OVERRIDE_TX_CLK_VLD_OVRD_MASK 0x0080 26611 #define PMD_X4_OVERRIDE_TX_CLK_VLD_OVRD_ALIGN 0 26612 #define PMD_X4_OVERRIDE_TX_CLK_VLD_OVRD_BITS 1 26613 #define PMD_X4_OVERRIDE_TX_CLK_VLD_OVRD_SHIFT 7 26614 26615 /* pmd_x4 :: override :: ln_dp_h_rstb_oen [06:06] */ 26616 #define PMD_X4_OVERRIDE_LN_DP_H_RSTB_OEN_MASK 0x0040 26617 #define PMD_X4_OVERRIDE_LN_DP_H_RSTB_OEN_ALIGN 0 26618 #define PMD_X4_OVERRIDE_LN_DP_H_RSTB_OEN_BITS 1 26619 #define PMD_X4_OVERRIDE_LN_DP_H_RSTB_OEN_SHIFT 6 26620 26621 /* pmd_x4 :: override :: tx_disable_oen [05:05] */ 26622 #define PMD_X4_OVERRIDE_TX_DISABLE_OEN_MASK 0x0020 26623 #define PMD_X4_OVERRIDE_TX_DISABLE_OEN_ALIGN 0 26624 #define PMD_X4_OVERRIDE_TX_DISABLE_OEN_BITS 1 26625 #define PMD_X4_OVERRIDE_TX_DISABLE_OEN_SHIFT 5 26626 26627 /* pmd_x4 :: override :: osr_mode_oen [04:04] */ 26628 #define PMD_X4_OVERRIDE_OSR_MODE_OEN_MASK 0x0010 26629 #define PMD_X4_OVERRIDE_OSR_MODE_OEN_ALIGN 0 26630 #define PMD_X4_OVERRIDE_OSR_MODE_OEN_BITS 1 26631 #define PMD_X4_OVERRIDE_OSR_MODE_OEN_SHIFT 4 26632 26633 /* pmd_x4 :: override :: lane_mode_oen [03:03] */ 26634 #define PMD_X4_OVERRIDE_LANE_MODE_OEN_MASK 0x0008 26635 #define PMD_X4_OVERRIDE_LANE_MODE_OEN_ALIGN 0 26636 #define PMD_X4_OVERRIDE_LANE_MODE_OEN_BITS 1 26637 #define PMD_X4_OVERRIDE_LANE_MODE_OEN_SHIFT 3 26638 26639 /* pmd_x4 :: override :: rx_clk_vld_ovrd [02:02] */ 26640 #define PMD_X4_OVERRIDE_RX_CLK_VLD_OVRD_MASK 0x0004 26641 #define PMD_X4_OVERRIDE_RX_CLK_VLD_OVRD_ALIGN 0 26642 #define PMD_X4_OVERRIDE_RX_CLK_VLD_OVRD_BITS 1 26643 #define PMD_X4_OVERRIDE_RX_CLK_VLD_OVRD_SHIFT 2 26644 26645 /* pmd_x4 :: override :: signal_detect_ovrd [01:01] */ 26646 #define PMD_X4_OVERRIDE_SIGNAL_DETECT_OVRD_MASK 0x0002 26647 #define PMD_X4_OVERRIDE_SIGNAL_DETECT_OVRD_ALIGN 0 26648 #define PMD_X4_OVERRIDE_SIGNAL_DETECT_OVRD_BITS 1 26649 #define PMD_X4_OVERRIDE_SIGNAL_DETECT_OVRD_SHIFT 1 26650 26651 /* pmd_x4 :: override :: rx_lock_ovrd [00:00] */ 26652 #define PMD_X4_OVERRIDE_RX_LOCK_OVRD_MASK 0x0001 26653 #define PMD_X4_OVERRIDE_RX_LOCK_OVRD_ALIGN 0 26654 #define PMD_X4_OVERRIDE_RX_LOCK_OVRD_BITS 1 26655 #define PMD_X4_OVERRIDE_RX_LOCK_OVRD_SHIFT 0 26656 26657 26658 /**************************************************************************** 26659 * pmd_x4 :: eee_control 26660 */ 26661 /* pmd_x4 :: eee_control :: reserved0 [15:03] */ 26662 #define PMD_X4_EEE_CONTROL_RESERVED0_MASK 0xfff8 26663 #define PMD_X4_EEE_CONTROL_RESERVED0_ALIGN 0 26664 #define PMD_X4_EEE_CONTROL_RESERVED0_BITS 13 26665 #define PMD_X4_EEE_CONTROL_RESERVED0_SHIFT 3 26666 26667 /* pmd_x4 :: eee_control :: rx_mode [02:02] */ 26668 #define PMD_X4_EEE_CONTROL_RX_MODE_MASK 0x0004 26669 #define PMD_X4_EEE_CONTROL_RX_MODE_ALIGN 0 26670 #define PMD_X4_EEE_CONTROL_RX_MODE_BITS 1 26671 #define PMD_X4_EEE_CONTROL_RX_MODE_SHIFT 2 26672 26673 /* pmd_x4 :: eee_control :: tx_mode [01:00] */ 26674 #define PMD_X4_EEE_CONTROL_TX_MODE_MASK 0x0003 26675 #define PMD_X4_EEE_CONTROL_TX_MODE_ALIGN 0 26676 #define PMD_X4_EEE_CONTROL_TX_MODE_BITS 2 26677 #define PMD_X4_EEE_CONTROL_TX_MODE_SHIFT 0 26678 26679 26680 /**************************************************************************** 26681 * pmd_x4 :: eee_status 26682 */ 26683 /* pmd_x4 :: eee_status :: reserved0 [15:01] */ 26684 #define PMD_X4_EEE_STATUS_RESERVED0_MASK 0xfffe 26685 #define PMD_X4_EEE_STATUS_RESERVED0_ALIGN 0 26686 #define PMD_X4_EEE_STATUS_RESERVED0_BITS 15 26687 #define PMD_X4_EEE_STATUS_RESERVED0_SHIFT 1 26688 26689 /* pmd_x4 :: eee_status :: energy_detect [00:00] */ 26690 #define PMD_X4_EEE_STATUS_ENERGY_DETECT_MASK 0x0001 26691 #define PMD_X4_EEE_STATUS_ENERGY_DETECT_ALIGN 0 26692 #define PMD_X4_EEE_STATUS_ENERGY_DETECT_BITS 1 26693 #define PMD_X4_EEE_STATUS_ENERGY_DETECT_SHIFT 0 26694 26695 26696 /**************************************************************************** 26697 * TSC_WC4_TSC_USER4_sc_x4_control 26698 */ 26699 /**************************************************************************** 26700 * sc_x4_control :: control 26701 */ 26702 /* sc_x4_control :: control :: reserved0 [15:09] */ 26703 #define SC_X4_CONTROL_CONTROL_RESERVED0_MASK 0xfe00 26704 #define SC_X4_CONTROL_CONTROL_RESERVED0_ALIGN 0 26705 #define SC_X4_CONTROL_CONTROL_RESERVED0_BITS 7 26706 #define SC_X4_CONTROL_CONTROL_RESERVED0_SHIFT 9 26707 26708 /* sc_x4_control :: control :: sw_speed_change [08:08] */ 26709 #define SC_X4_CONTROL_CONTROL_SW_SPEED_CHANGE_MASK 0x0100 26710 #define SC_X4_CONTROL_CONTROL_SW_SPEED_CHANGE_ALIGN 0 26711 #define SC_X4_CONTROL_CONTROL_SW_SPEED_CHANGE_BITS 1 26712 #define SC_X4_CONTROL_CONTROL_SW_SPEED_CHANGE_SHIFT 8 26713 26714 /* sc_x4_control :: control :: speed [07:00] */ 26715 #define SC_X4_CONTROL_CONTROL_SPEED_MASK 0x00ff 26716 #define SC_X4_CONTROL_CONTROL_SPEED_ALIGN 0 26717 #define SC_X4_CONTROL_CONTROL_SPEED_BITS 8 26718 #define SC_X4_CONTROL_CONTROL_SPEED_SHIFT 0 26719 #define SC_X4_CONTROL_CONTROL_SPEED_S_10G_CR1 0 26720 #define SC_X4_CONTROL_CONTROL_SPEED_S_10G_KR1 1 26721 #define SC_X4_CONTROL_CONTROL_SPEED_S_10G_X1 2 26722 #define SC_X4_CONTROL_CONTROL_SPEED_S_10G_HG2_CR1 4 26723 #define SC_X4_CONTROL_CONTROL_SPEED_S_10G_HG2_KR1 5 26724 #define SC_X4_CONTROL_CONTROL_SPEED_S_10G_HG2_X1 6 26725 #define SC_X4_CONTROL_CONTROL_SPEED_S_20G_CR1 8 26726 #define SC_X4_CONTROL_CONTROL_SPEED_S_20G_KR1 9 26727 #define SC_X4_CONTROL_CONTROL_SPEED_S_20G_X1 10 26728 #define SC_X4_CONTROL_CONTROL_SPEED_S_20G_HG2_CR1 12 26729 #define SC_X4_CONTROL_CONTROL_SPEED_S_20G_HG2_KR1 13 26730 #define SC_X4_CONTROL_CONTROL_SPEED_S_20G_HG2_X1 14 26731 #define SC_X4_CONTROL_CONTROL_SPEED_S_25G_CR1 16 26732 #define SC_X4_CONTROL_CONTROL_SPEED_S_25G_KR1 17 26733 #define SC_X4_CONTROL_CONTROL_SPEED_S_25G_X1 18 26734 #define SC_X4_CONTROL_CONTROL_SPEED_S_25G_HG2_CR1 20 26735 #define SC_X4_CONTROL_CONTROL_SPEED_S_25G_HG2_KR1 21 26736 #define SC_X4_CONTROL_CONTROL_SPEED_S_25G_HG2_X1 22 26737 #define SC_X4_CONTROL_CONTROL_SPEED_S_20G_CR2 24 26738 #define SC_X4_CONTROL_CONTROL_SPEED_S_20G_KR2 25 26739 #define SC_X4_CONTROL_CONTROL_SPEED_S_20G_X2 26 26740 #define SC_X4_CONTROL_CONTROL_SPEED_S_20G_HG2_CR2 28 26741 #define SC_X4_CONTROL_CONTROL_SPEED_S_20G_HG2_KR2 29 26742 #define SC_X4_CONTROL_CONTROL_SPEED_S_20G_HG2_X2 30 26743 #define SC_X4_CONTROL_CONTROL_SPEED_S_40G_CR2 32 26744 #define SC_X4_CONTROL_CONTROL_SPEED_S_40G_KR2 33 26745 #define SC_X4_CONTROL_CONTROL_SPEED_S_40G_X2 34 26746 #define SC_X4_CONTROL_CONTROL_SPEED_S_40G_HG2_CR2 36 26747 #define SC_X4_CONTROL_CONTROL_SPEED_S_40G_HG2_KR2 37 26748 #define SC_X4_CONTROL_CONTROL_SPEED_S_40G_HG2_X2 38 26749 #define SC_X4_CONTROL_CONTROL_SPEED_S_40G_CR4 40 26750 #define SC_X4_CONTROL_CONTROL_SPEED_S_40G_KR4 41 26751 #define SC_X4_CONTROL_CONTROL_SPEED_S_40G_X4 42 26752 #define SC_X4_CONTROL_CONTROL_SPEED_S_40G_HG2_CR4 44 26753 #define SC_X4_CONTROL_CONTROL_SPEED_S_40G_HG2_KR4 45 26754 #define SC_X4_CONTROL_CONTROL_SPEED_S_40G_HG2_X4 46 26755 #define SC_X4_CONTROL_CONTROL_SPEED_S_50G_CR2 48 26756 #define SC_X4_CONTROL_CONTROL_SPEED_S_50G_KR2 49 26757 #define SC_X4_CONTROL_CONTROL_SPEED_S_50G_X2 50 26758 #define SC_X4_CONTROL_CONTROL_SPEED_S_50G_HG2_CR2 52 26759 #define SC_X4_CONTROL_CONTROL_SPEED_S_50G_HG2_KR2 53 26760 #define SC_X4_CONTROL_CONTROL_SPEED_S_50G_HG2_X2 54 26761 #define SC_X4_CONTROL_CONTROL_SPEED_S_50G_CR4 56 26762 #define SC_X4_CONTROL_CONTROL_SPEED_S_50G_KR4 57 26763 #define SC_X4_CONTROL_CONTROL_SPEED_S_50G_X4 58 26764 #define SC_X4_CONTROL_CONTROL_SPEED_S_50G_HG2_CR4 60 26765 #define SC_X4_CONTROL_CONTROL_SPEED_S_50G_HG2_KR4 61 26766 #define SC_X4_CONTROL_CONTROL_SPEED_S_50G_HG2_X4 62 26767 #define SC_X4_CONTROL_CONTROL_SPEED_S_100G_CR4 64 26768 #define SC_X4_CONTROL_CONTROL_SPEED_S_100G_KR4 65 26769 #define SC_X4_CONTROL_CONTROL_SPEED_S_100G_X4 66 26770 #define SC_X4_CONTROL_CONTROL_SPEED_S_100G_HG2_CR4 68 26771 #define SC_X4_CONTROL_CONTROL_SPEED_S_100G_HG2_KR4 69 26772 #define SC_X4_CONTROL_CONTROL_SPEED_S_100G_HG2_X4 70 26773 #define SC_X4_CONTROL_CONTROL_SPEED_S_CL73_20GVCO 72 26774 #define SC_X4_CONTROL_CONTROL_SPEED_S_CL73_25GVCO 80 26775 #define SC_X4_CONTROL_CONTROL_SPEED_S_CL36_20GVCO 88 26776 #define SC_X4_CONTROL_CONTROL_SPEED_S_CL36_25GVCO 96 26777 #define SC_X4_CONTROL_CONTROL_SPEED_S_25G_CR_IEEE 112 26778 #define SC_X4_CONTROL_CONTROL_SPEED_S_25G_CRS_IEEE 113 26779 #define SC_X4_CONTROL_CONTROL_SPEED_S_25G_KR_IEEE 114 26780 #define SC_X4_CONTROL_CONTROL_SPEED_S_25G_KRS_IEEE 115 26781 26782 26783 /**************************************************************************** 26784 * sc_x4_control :: status 26785 */ 26786 /* sc_x4_control :: status :: reserved0 [15:02] */ 26787 #define SC_X4_CONTROL_STATUS_RESERVED0_MASK 0xfffc 26788 #define SC_X4_CONTROL_STATUS_RESERVED0_ALIGN 0 26789 #define SC_X4_CONTROL_STATUS_RESERVED0_BITS 14 26790 #define SC_X4_CONTROL_STATUS_RESERVED0_SHIFT 2 26791 26792 /* sc_x4_control :: status :: sw_speed_config_vld [01:01] */ 26793 #define SC_X4_CONTROL_STATUS_SW_SPEED_CONFIG_VLD_MASK 0x0002 26794 #define SC_X4_CONTROL_STATUS_SW_SPEED_CONFIG_VLD_ALIGN 0 26795 #define SC_X4_CONTROL_STATUS_SW_SPEED_CONFIG_VLD_BITS 1 26796 #define SC_X4_CONTROL_STATUS_SW_SPEED_CONFIG_VLD_SHIFT 1 26797 26798 /* sc_x4_control :: status :: sw_speed_change_done [00:00] */ 26799 #define SC_X4_CONTROL_STATUS_SW_SPEED_CHANGE_DONE_MASK 0x0001 26800 #define SC_X4_CONTROL_STATUS_SW_SPEED_CHANGE_DONE_ALIGN 0 26801 #define SC_X4_CONTROL_STATUS_SW_SPEED_CHANGE_DONE_BITS 1 26802 #define SC_X4_CONTROL_STATUS_SW_SPEED_CHANGE_DONE_SHIFT 0 26803 26804 26805 /**************************************************************************** 26806 * sc_x4_control :: error 26807 */ 26808 /* sc_x4_control :: error :: reserved0 [15:02] */ 26809 #define SC_X4_CONTROL_ERROR_RESERVED0_MASK 0xfffc 26810 #define SC_X4_CONTROL_ERROR_RESERVED0_ALIGN 0 26811 #define SC_X4_CONTROL_ERROR_RESERVED0_BITS 14 26812 #define SC_X4_CONTROL_ERROR_RESERVED0_SHIFT 2 26813 26814 /* sc_x4_control :: error :: pmd_lock_timed_out [01:01] */ 26815 #define SC_X4_CONTROL_ERROR_PMD_LOCK_TIMED_OUT_MASK 0x0002 26816 #define SC_X4_CONTROL_ERROR_PMD_LOCK_TIMED_OUT_ALIGN 0 26817 #define SC_X4_CONTROL_ERROR_PMD_LOCK_TIMED_OUT_BITS 1 26818 #define SC_X4_CONTROL_ERROR_PMD_LOCK_TIMED_OUT_SHIFT 1 26819 26820 /* sc_x4_control :: error :: pll_lock_timed_out [00:00] */ 26821 #define SC_X4_CONTROL_ERROR_PLL_LOCK_TIMED_OUT_MASK 0x0001 26822 #define SC_X4_CONTROL_ERROR_PLL_LOCK_TIMED_OUT_ALIGN 0 26823 #define SC_X4_CONTROL_ERROR_PLL_LOCK_TIMED_OUT_BITS 1 26824 #define SC_X4_CONTROL_ERROR_PLL_LOCK_TIMED_OUT_SHIFT 0 26825 26826 26827 /**************************************************************************** 26828 * sc_x4_control :: debug 26829 */ 26830 /* sc_x4_control :: debug :: sc_fsm_status [15:00] */ 26831 #define SC_X4_CONTROL_DEBUG_SC_FSM_STATUS_MASK 0xffff 26832 #define SC_X4_CONTROL_DEBUG_SC_FSM_STATUS_ALIGN 0 26833 #define SC_X4_CONTROL_DEBUG_SC_FSM_STATUS_BITS 16 26834 #define SC_X4_CONTROL_DEBUG_SC_FSM_STATUS_SHIFT 0 26835 26836 26837 /**************************************************************************** 26838 * sc_x4_control :: sc_x4_override 26839 */ 26840 /* sc_x4_control :: sc_x4_override :: reserved0 [15:05] */ 26841 #define SC_X4_CONTROL_SC_X4_OVERRIDE_RESERVED0_MASK 0xffe0 26842 #define SC_X4_CONTROL_SC_X4_OVERRIDE_RESERVED0_ALIGN 0 26843 #define SC_X4_CONTROL_SC_X4_OVERRIDE_RESERVED0_BITS 11 26844 #define SC_X4_CONTROL_SC_X4_OVERRIDE_RESERVED0_SHIFT 5 26845 26846 /* sc_x4_control :: sc_x4_override :: AN_fec_sel_override [04:03] */ 26847 #define SC_X4_CONTROL_SC_X4_OVERRIDE_AN_FEC_SEL_OVERRIDE_MASK 0x0018 26848 #define SC_X4_CONTROL_SC_X4_OVERRIDE_AN_FEC_SEL_OVERRIDE_ALIGN 0 26849 #define SC_X4_CONTROL_SC_X4_OVERRIDE_AN_FEC_SEL_OVERRIDE_BITS 2 26850 #define SC_X4_CONTROL_SC_X4_OVERRIDE_AN_FEC_SEL_OVERRIDE_SHIFT 3 26851 #define SC_X4_CONTROL_SC_X4_OVERRIDE_AN_FEC_SEL_OVERRIDE_NO_OVERRIDE 0 26852 #define SC_X4_CONTROL_SC_X4_OVERRIDE_AN_FEC_SEL_OVERRIDE_NO_FEC 1 26853 #define SC_X4_CONTROL_SC_X4_OVERRIDE_AN_FEC_SEL_OVERRIDE_FEC_CL74 2 26854 #define SC_X4_CONTROL_SC_X4_OVERRIDE_AN_FEC_SEL_OVERRIDE_FEC_CL91 3 26855 26856 /* sc_x4_control :: sc_x4_override :: num_lanes_override_value [02:00] */ 26857 #define SC_X4_CONTROL_SC_X4_OVERRIDE_NUM_LANES_OVERRIDE_VALUE_MASK 0x0007 26858 #define SC_X4_CONTROL_SC_X4_OVERRIDE_NUM_LANES_OVERRIDE_VALUE_ALIGN 0 26859 #define SC_X4_CONTROL_SC_X4_OVERRIDE_NUM_LANES_OVERRIDE_VALUE_BITS 3 26860 #define SC_X4_CONTROL_SC_X4_OVERRIDE_NUM_LANES_OVERRIDE_VALUE_SHIFT 0 26861 26862 26863 /**************************************************************************** 26864 * sc_x4_control :: bypass 26865 */ 26866 /* sc_x4_control :: bypass :: reserved0 [15:02] */ 26867 #define SC_X4_CONTROL_BYPASS_RESERVED0_MASK 0xfffc 26868 #define SC_X4_CONTROL_BYPASS_RESERVED0_ALIGN 0 26869 #define SC_X4_CONTROL_BYPASS_RESERVED0_BITS 14 26870 #define SC_X4_CONTROL_BYPASS_RESERVED0_SHIFT 2 26871 26872 /* sc_x4_control :: bypass :: sc_ignore_tx_data_vld [01:01] */ 26873 #define SC_X4_CONTROL_BYPASS_SC_IGNORE_TX_DATA_VLD_MASK 0x0002 26874 #define SC_X4_CONTROL_BYPASS_SC_IGNORE_TX_DATA_VLD_ALIGN 0 26875 #define SC_X4_CONTROL_BYPASS_SC_IGNORE_TX_DATA_VLD_BITS 1 26876 #define SC_X4_CONTROL_BYPASS_SC_IGNORE_TX_DATA_VLD_SHIFT 1 26877 26878 /* sc_x4_control :: bypass :: sc_bypass [00:00] */ 26879 #define SC_X4_CONTROL_BYPASS_SC_BYPASS_MASK 0x0001 26880 #define SC_X4_CONTROL_BYPASS_SC_BYPASS_ALIGN 0 26881 #define SC_X4_CONTROL_BYPASS_SC_BYPASS_BITS 1 26882 #define SC_X4_CONTROL_BYPASS_SC_BYPASS_SHIFT 0 26883 26884 26885 /**************************************************************************** 26886 * sc_x4_control :: spare0 26887 */ 26888 /* sc_x4_control :: spare0 :: spare0 [15:00] */ 26889 #define SC_X4_CONTROL_SPARE0_SPARE0_MASK 0xffff 26890 #define SC_X4_CONTROL_SPARE0_SPARE0_ALIGN 0 26891 #define SC_X4_CONTROL_SPARE0_SPARE0_BITS 16 26892 #define SC_X4_CONTROL_SPARE0_SPARE0_SHIFT 0 26893 26894 26895 /**************************************************************************** 26896 * sc_x4_control :: spare1 26897 */ 26898 /* sc_x4_control :: spare1 :: spare1 [15:00] */ 26899 #define SC_X4_CONTROL_SPARE1_SPARE1_MASK 0xffff 26900 #define SC_X4_CONTROL_SPARE1_SPARE1_ALIGN 0 26901 #define SC_X4_CONTROL_SPARE1_SPARE1_BITS 16 26902 #define SC_X4_CONTROL_SPARE1_SPARE1_SHIFT 0 26903 26904 26905 /**************************************************************************** 26906 * TSC_WC4_TSC_USER4_sc_x4_field_override_enable 26907 */ 26908 /**************************************************************************** 26909 * sc_x4_field_override_enable :: field_override_enable0_type 26910 */ 26911 /* sc_x4_field_override_enable :: field_override_enable0_type :: reserved0 [15:15] */ 26912 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_RESERVED0_MASK 0x8000 26913 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_RESERVED0_ALIGN 0 26914 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_RESERVED0_BITS 1 26915 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_RESERVED0_SHIFT 15 26916 26917 /* sc_x4_field_override_enable :: field_override_enable0_type :: num_lanes_oen [14:14] */ 26918 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_NUM_LANES_OEN_MASK 0x4000 26919 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_NUM_LANES_OEN_ALIGN 0 26920 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_NUM_LANES_OEN_BITS 1 26921 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_NUM_LANES_OEN_SHIFT 14 26922 26923 /* sc_x4_field_override_enable :: field_override_enable0_type :: os_mode_oen [13:13] */ 26924 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_OS_MODE_OEN_MASK 0x2000 26925 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_OS_MODE_OEN_ALIGN 0 26926 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_OS_MODE_OEN_BITS 1 26927 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_OS_MODE_OEN_SHIFT 13 26928 26929 /* sc_x4_field_override_enable :: field_override_enable0_type :: t_fifo_mode_oen [12:12] */ 26930 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_T_FIFO_MODE_OEN_MASK 0x1000 26931 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_T_FIFO_MODE_OEN_ALIGN 0 26932 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_T_FIFO_MODE_OEN_BITS 1 26933 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_T_FIFO_MODE_OEN_SHIFT 12 26934 26935 /* sc_x4_field_override_enable :: field_override_enable0_type :: t_enc_mode_oen [11:11] */ 26936 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_T_ENC_MODE_OEN_MASK 0x0800 26937 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_T_ENC_MODE_OEN_ALIGN 0 26938 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_T_ENC_MODE_OEN_BITS 1 26939 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_T_ENC_MODE_OEN_SHIFT 11 26940 26941 /* sc_x4_field_override_enable :: field_override_enable0_type :: t_HG2_ENABLE_oen [10:10] */ 26942 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_T_HG2_ENABLE_OEN_MASK 0x0400 26943 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_T_HG2_ENABLE_OEN_ALIGN 0 26944 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_T_HG2_ENABLE_OEN_BITS 1 26945 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_T_HG2_ENABLE_OEN_SHIFT 10 26946 26947 /* sc_x4_field_override_enable :: field_override_enable0_type :: t_pma_btmx_mode_oen [09:09] */ 26948 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_T_PMA_BTMX_MODE_OEN_MASK 0x0200 26949 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_T_PMA_BTMX_MODE_OEN_ALIGN 0 26950 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_T_PMA_BTMX_MODE_OEN_BITS 1 26951 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_T_PMA_BTMX_MODE_OEN_SHIFT 9 26952 26953 /* sc_x4_field_override_enable :: field_override_enable0_type :: scr_mode_oen [08:08] */ 26954 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_SCR_MODE_OEN_MASK 0x0100 26955 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_SCR_MODE_OEN_ALIGN 0 26956 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_SCR_MODE_OEN_BITS 1 26957 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_SCR_MODE_OEN_SHIFT 8 26958 26959 /* sc_x4_field_override_enable :: field_override_enable0_type :: cl72_en_oen [07:07] */ 26960 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_CL72_EN_OEN_MASK 0x0080 26961 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_CL72_EN_OEN_ALIGN 0 26962 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_CL72_EN_OEN_BITS 1 26963 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_CL72_EN_OEN_SHIFT 7 26964 26965 /* sc_x4_field_override_enable :: field_override_enable0_type :: descr_mode_oen [06:06] */ 26966 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_DESCR_MODE_OEN_MASK 0x0040 26967 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_DESCR_MODE_OEN_ALIGN 0 26968 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_DESCR_MODE_OEN_BITS 1 26969 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_DESCR_MODE_OEN_SHIFT 6 26970 26971 /* sc_x4_field_override_enable :: field_override_enable0_type :: dec_tl_mode_oen [05:05] */ 26972 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_DEC_TL_MODE_OEN_MASK 0x0020 26973 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_DEC_TL_MODE_OEN_ALIGN 0 26974 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_DEC_TL_MODE_OEN_BITS 1 26975 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_DEC_TL_MODE_OEN_SHIFT 5 26976 26977 /* sc_x4_field_override_enable :: field_override_enable0_type :: deskew_mode_oen [04:04] */ 26978 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_DESKEW_MODE_OEN_MASK 0x0010 26979 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_DESKEW_MODE_OEN_ALIGN 0 26980 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_DESKEW_MODE_OEN_BITS 1 26981 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_DESKEW_MODE_OEN_SHIFT 4 26982 26983 /* sc_x4_field_override_enable :: field_override_enable0_type :: dec_fsm_mode_oen [03:03] */ 26984 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_DEC_FSM_MODE_OEN_MASK 0x0008 26985 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_DEC_FSM_MODE_OEN_ALIGN 0 26986 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_DEC_FSM_MODE_OEN_BITS 1 26987 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_DEC_FSM_MODE_OEN_SHIFT 3 26988 26989 /* sc_x4_field_override_enable :: field_override_enable0_type :: t_pma_40b_mode_oen [02:02] */ 26990 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_T_PMA_40B_MODE_OEN_MASK 0x0004 26991 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_T_PMA_40B_MODE_OEN_ALIGN 0 26992 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_T_PMA_40B_MODE_OEN_BITS 1 26993 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_T_PMA_40B_MODE_OEN_SHIFT 2 26994 26995 /* sc_x4_field_override_enable :: field_override_enable0_type :: cl36tx_en_oen [01:01] */ 26996 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_CL36TX_EN_OEN_MASK 0x0002 26997 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_CL36TX_EN_OEN_ALIGN 0 26998 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_CL36TX_EN_OEN_BITS 1 26999 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_CL36TX_EN_OEN_SHIFT 1 27000 27001 /* sc_x4_field_override_enable :: field_override_enable0_type :: cl36rx_en_oen [00:00] */ 27002 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_CL36RX_EN_OEN_MASK 0x0001 27003 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_CL36RX_EN_OEN_ALIGN 0 27004 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_CL36RX_EN_OEN_BITS 1 27005 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_CL36RX_EN_OEN_SHIFT 0 27006 27007 27008 /**************************************************************************** 27009 * sc_x4_field_override_enable :: field_override_enable1_type 27010 */ 27011 /* sc_x4_field_override_enable :: field_override_enable1_type :: r_HG2_ENABLE_oen [15:15] */ 27012 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_R_HG2_ENABLE_OEN_MASK 0x8000 27013 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_R_HG2_ENABLE_OEN_ALIGN 0 27014 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_R_HG2_ENABLE_OEN_BITS 1 27015 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_R_HG2_ENABLE_OEN_SHIFT 15 27016 27017 /* sc_x4_field_override_enable :: field_override_enable1_type :: bs_sm_sync_mode_oen [14:14] */ 27018 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_BS_SM_SYNC_MODE_OEN_MASK 0x4000 27019 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_BS_SM_SYNC_MODE_OEN_ALIGN 0 27020 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_BS_SM_SYNC_MODE_OEN_BITS 1 27021 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_BS_SM_SYNC_MODE_OEN_SHIFT 14 27022 27023 /* sc_x4_field_override_enable :: field_override_enable1_type :: bs_sync_en_oen [13:13] */ 27024 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_BS_SYNC_EN_OEN_MASK 0x2000 27025 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_BS_SYNC_EN_OEN_ALIGN 0 27026 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_BS_SYNC_EN_OEN_BITS 1 27027 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_BS_SYNC_EN_OEN_SHIFT 13 27028 27029 /* sc_x4_field_override_enable :: field_override_enable1_type :: bs_dist_mode_oen [12:12] */ 27030 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_BS_DIST_MODE_OEN_MASK 0x1000 27031 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_BS_DIST_MODE_OEN_ALIGN 0 27032 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_BS_DIST_MODE_OEN_BITS 1 27033 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_BS_DIST_MODE_OEN_SHIFT 12 27034 27035 /* sc_x4_field_override_enable :: field_override_enable1_type :: bs_btmx_mode_oen [11:11] */ 27036 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_BS_BTMX_MODE_OEN_MASK 0x0800 27037 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_BS_BTMX_MODE_OEN_ALIGN 0 27038 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_BS_BTMX_MODE_OEN_BITS 1 27039 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_BS_BTMX_MODE_OEN_SHIFT 11 27040 27041 /* sc_x4_field_override_enable :: field_override_enable1_type :: creditenable_oen [10:10] */ 27042 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_CREDITENABLE_OEN_MASK 0x0400 27043 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_CREDITENABLE_OEN_ALIGN 0 27044 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_CREDITENABLE_OEN_BITS 1 27045 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_CREDITENABLE_OEN_SHIFT 10 27046 27047 /* sc_x4_field_override_enable :: field_override_enable1_type :: clockcnt0_oen [09:09] */ 27048 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_CLOCKCNT0_OEN_MASK 0x0200 27049 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_CLOCKCNT0_OEN_ALIGN 0 27050 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_CLOCKCNT0_OEN_BITS 1 27051 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_CLOCKCNT0_OEN_SHIFT 9 27052 27053 /* sc_x4_field_override_enable :: field_override_enable1_type :: clockcnt1_oen [08:08] */ 27054 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_CLOCKCNT1_OEN_MASK 0x0100 27055 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_CLOCKCNT1_OEN_ALIGN 0 27056 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_CLOCKCNT1_OEN_BITS 1 27057 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_CLOCKCNT1_OEN_SHIFT 8 27058 27059 /* sc_x4_field_override_enable :: field_override_enable1_type :: loopcnt0_oen [07:07] */ 27060 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_LOOPCNT0_OEN_MASK 0x0080 27061 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_LOOPCNT0_OEN_ALIGN 0 27062 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_LOOPCNT0_OEN_BITS 1 27063 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_LOOPCNT0_OEN_SHIFT 7 27064 27065 /* sc_x4_field_override_enable :: field_override_enable1_type :: loopcnt1_oen [06:06] */ 27066 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_LOOPCNT1_OEN_MASK 0x0040 27067 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_LOOPCNT1_OEN_ALIGN 0 27068 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_LOOPCNT1_OEN_BITS 1 27069 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_LOOPCNT1_OEN_SHIFT 6 27070 27071 /* sc_x4_field_override_enable :: field_override_enable1_type :: mac_creditgencnt_oen [05:05] */ 27072 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_MAC_CREDITGENCNT_OEN_MASK 0x0020 27073 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_MAC_CREDITGENCNT_OEN_ALIGN 0 27074 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_MAC_CREDITGENCNT_OEN_BITS 1 27075 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_MAC_CREDITGENCNT_OEN_SHIFT 5 27076 27077 /* sc_x4_field_override_enable :: field_override_enable1_type :: t_pma_bitmux_delay_oen [04:04] */ 27078 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_T_PMA_BITMUX_DELAY_OEN_MASK 0x0010 27079 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_T_PMA_BITMUX_DELAY_OEN_ALIGN 0 27080 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_T_PMA_BITMUX_DELAY_OEN_BITS 1 27081 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_T_PMA_BITMUX_DELAY_OEN_SHIFT 4 27082 27083 /* sc_x4_field_override_enable :: field_override_enable1_type :: t_pma_watermark_oen [03:03] */ 27084 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_T_PMA_WATERMARK_OEN_MASK 0x0008 27085 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_T_PMA_WATERMARK_OEN_ALIGN 0 27086 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_T_PMA_WATERMARK_OEN_BITS 1 27087 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_T_PMA_WATERMARK_OEN_SHIFT 3 27088 27089 /* sc_x4_field_override_enable :: field_override_enable1_type :: t_pma_cl91_mux_sel_oen [02:02] */ 27090 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_T_PMA_CL91_MUX_SEL_OEN_MASK 0x0004 27091 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_T_PMA_CL91_MUX_SEL_OEN_ALIGN 0 27092 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_T_PMA_CL91_MUX_SEL_OEN_BITS 1 27093 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_T_PMA_CL91_MUX_SEL_OEN_SHIFT 2 27094 27095 /* sc_x4_field_override_enable :: field_override_enable1_type :: t_five_bit_xor_en_oen [01:01] */ 27096 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_T_FIVE_BIT_XOR_EN_OEN_MASK 0x0002 27097 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_T_FIVE_BIT_XOR_EN_OEN_ALIGN 0 27098 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_T_FIVE_BIT_XOR_EN_OEN_BITS 1 27099 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_T_FIVE_BIT_XOR_EN_OEN_SHIFT 1 27100 27101 /* sc_x4_field_override_enable :: field_override_enable1_type :: t_cl91_cw_scramble_oen [00:00] */ 27102 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_T_CL91_CW_SCRAMBLE_OEN_MASK 0x0001 27103 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_T_CL91_CW_SCRAMBLE_OEN_ALIGN 0 27104 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_T_CL91_CW_SCRAMBLE_OEN_BITS 1 27105 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_T_CL91_CW_SCRAMBLE_OEN_SHIFT 0 27106 27107 27108 /**************************************************************************** 27109 * sc_x4_field_override_enable :: field_override_enable2_type 27110 */ 27111 /* sc_x4_field_override_enable :: field_override_enable2_type :: reserved0 [15:08] */ 27112 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE2_TYPE_RESERVED0_MASK 0xff00 27113 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE2_TYPE_RESERVED0_ALIGN 0 27114 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE2_TYPE_RESERVED0_BITS 8 27115 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE2_TYPE_RESERVED0_SHIFT 8 27116 27117 /* sc_x4_field_override_enable :: field_override_enable2_type :: r_tc_out_mode_oen [07:07] */ 27118 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE2_TYPE_R_TC_OUT_MODE_OEN_MASK 0x0080 27119 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE2_TYPE_R_TC_OUT_MODE_OEN_ALIGN 0 27120 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE2_TYPE_R_TC_OUT_MODE_OEN_BITS 1 27121 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE2_TYPE_R_TC_OUT_MODE_OEN_SHIFT 7 27122 27123 /* sc_x4_field_override_enable :: field_override_enable2_type :: r_five_bit_xor_en_oen [06:06] */ 27124 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE2_TYPE_R_FIVE_BIT_XOR_EN_OEN_MASK 0x0040 27125 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE2_TYPE_R_FIVE_BIT_XOR_EN_OEN_ALIGN 0 27126 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE2_TYPE_R_FIVE_BIT_XOR_EN_OEN_BITS 1 27127 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE2_TYPE_R_FIVE_BIT_XOR_EN_OEN_SHIFT 6 27128 27129 /* sc_x4_field_override_enable :: field_override_enable2_type :: r_tc_mode_oen [05:05] */ 27130 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE2_TYPE_R_TC_MODE_OEN_MASK 0x0020 27131 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE2_TYPE_R_TC_MODE_OEN_ALIGN 0 27132 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE2_TYPE_R_TC_MODE_OEN_BITS 1 27133 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE2_TYPE_R_TC_MODE_OEN_SHIFT 5 27134 27135 /* sc_x4_field_override_enable :: field_override_enable2_type :: r_tc_in_mode_oen [04:04] */ 27136 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE2_TYPE_R_TC_IN_MODE_OEN_MASK 0x0010 27137 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE2_TYPE_R_TC_IN_MODE_OEN_ALIGN 0 27138 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE2_TYPE_R_TC_IN_MODE_OEN_BITS 1 27139 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE2_TYPE_R_TC_IN_MODE_OEN_SHIFT 4 27140 27141 /* sc_x4_field_override_enable :: field_override_enable2_type :: r_cl91_cw_scramble_oen [03:03] */ 27142 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE2_TYPE_R_CL91_CW_SCRAMBLE_OEN_MASK 0x0008 27143 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE2_TYPE_R_CL91_CW_SCRAMBLE_OEN_ALIGN 0 27144 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE2_TYPE_R_CL91_CW_SCRAMBLE_OEN_BITS 1 27145 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE2_TYPE_R_CL91_CW_SCRAMBLE_OEN_SHIFT 3 27146 27147 /* sc_x4_field_override_enable :: field_override_enable2_type :: r_merge_mode_oen [02:02] */ 27148 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE2_TYPE_R_MERGE_MODE_OEN_MASK 0x0004 27149 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE2_TYPE_R_MERGE_MODE_OEN_ALIGN 0 27150 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE2_TYPE_R_MERGE_MODE_OEN_BITS 1 27151 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE2_TYPE_R_MERGE_MODE_OEN_SHIFT 2 27152 27153 /* sc_x4_field_override_enable :: field_override_enable2_type :: cl91_blksync_mode_oen [01:01] */ 27154 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE2_TYPE_CL91_BLKSYNC_MODE_OEN_MASK 0x0002 27155 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE2_TYPE_CL91_BLKSYNC_MODE_OEN_ALIGN 0 27156 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE2_TYPE_CL91_BLKSYNC_MODE_OEN_BITS 1 27157 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE2_TYPE_CL91_BLKSYNC_MODE_OEN_SHIFT 1 27158 27159 /* sc_x4_field_override_enable :: field_override_enable2_type :: AM_spacing_mul_oen [00:00] */ 27160 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE2_TYPE_AM_SPACING_MUL_OEN_MASK 0x0001 27161 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE2_TYPE_AM_SPACING_MUL_OEN_ALIGN 0 27162 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE2_TYPE_AM_SPACING_MUL_OEN_BITS 1 27163 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE2_TYPE_AM_SPACING_MUL_OEN_SHIFT 0 27164 27165 27166 /**************************************************************************** 27167 * TSC_WC4_TSC_USER4_sc_x4_final_config_status 27168 */ 27169 /**************************************************************************** 27170 * sc_x4_final_config_status :: resolved_speed 27171 */ 27172 /* sc_x4_final_config_status :: resolved_speed :: speed [15:08] */ 27173 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_MASK 0xff00 27174 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_ALIGN 0 27175 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_BITS 8 27176 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_SHIFT 8 27177 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_10G_CR1 0 27178 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_10G_KR1 1 27179 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_10G_X1 2 27180 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_10G_HG2_CR1 4 27181 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_10G_HG2_KR1 5 27182 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_10G_HG2_X1 6 27183 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_20G_CR1 8 27184 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_20G_KR1 9 27185 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_20G_X1 10 27186 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_20G_HG2_CR1 12 27187 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_20G_HG2_KR1 13 27188 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_20G_HG2_X1 14 27189 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_25G_CR1 16 27190 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_25G_KR1 17 27191 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_25G_X1 18 27192 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_25G_HG2_CR1 20 27193 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_25G_HG2_KR1 21 27194 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_25G_HG2_X1 22 27195 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_20G_CR2 24 27196 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_20G_KR2 25 27197 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_20G_X2 26 27198 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_20G_HG2_CR2 28 27199 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_20G_HG2_KR2 29 27200 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_20G_HG2_X2 30 27201 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_40G_CR2 32 27202 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_40G_KR2 33 27203 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_40G_X2 34 27204 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_40G_HG2_CR2 36 27205 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_40G_HG2_KR2 37 27206 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_40G_HG2_X2 38 27207 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_40G_CR4 40 27208 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_40G_KR4 41 27209 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_40G_X4 42 27210 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_40G_HG2_CR4 44 27211 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_40G_HG2_KR4 45 27212 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_40G_HG2_X4 46 27213 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_50G_CR2 48 27214 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_50G_KR2 49 27215 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_50G_X2 50 27216 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_50G_HG2_CR2 52 27217 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_50G_HG2_KR2 53 27218 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_50G_HG2_X2 54 27219 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_50G_CR4 56 27220 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_50G_KR4 57 27221 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_50G_X4 58 27222 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_50G_HG2_CR4 60 27223 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_50G_HG2_KR4 61 27224 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_50G_HG2_X4 62 27225 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_100G_CR4 64 27226 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_100G_KR4 65 27227 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_100G_X4 66 27228 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_100G_HG2_CR4 68 27229 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_100G_HG2_KR4 69 27230 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_100G_HG2_X4 70 27231 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_CL73_20GVCO 72 27232 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_CL73_25GVCO 80 27233 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_CL36_20GVCO 88 27234 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_CL36_25GVCO 96 27235 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_25G_CR_IEEE 112 27236 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_25G_CRS_IEEE 113 27237 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_25G_KR_IEEE 114 27238 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_S_25G_KRS_IEEE 115 27239 27240 /* sc_x4_final_config_status :: resolved_speed :: reserved0 [07:06] */ 27241 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_RESERVED0_MASK 0x00c0 27242 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_RESERVED0_ALIGN 0 27243 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_RESERVED0_BITS 2 27244 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_RESERVED0_SHIFT 6 27245 27246 /* sc_x4_final_config_status :: resolved_speed :: cl36rx_en [05:05] */ 27247 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_CL36RX_EN_MASK 0x0020 27248 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_CL36RX_EN_ALIGN 0 27249 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_CL36RX_EN_BITS 1 27250 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_CL36RX_EN_SHIFT 5 27251 27252 /* sc_x4_final_config_status :: resolved_speed :: cl36tx_en [04:04] */ 27253 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_CL36TX_EN_MASK 0x0010 27254 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_CL36TX_EN_ALIGN 0 27255 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_CL36TX_EN_BITS 1 27256 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_CL36TX_EN_SHIFT 4 27257 27258 /* sc_x4_final_config_status :: resolved_speed :: t_pma_40b_mode [03:03] */ 27259 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_T_PMA_40B_MODE_MASK 0x0008 27260 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_T_PMA_40B_MODE_ALIGN 0 27261 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_T_PMA_40B_MODE_BITS 1 27262 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_T_PMA_40B_MODE_SHIFT 3 27263 27264 /* sc_x4_final_config_status :: resolved_speed :: num_lanes [02:00] */ 27265 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_NUM_LANES_MASK 0x0007 27266 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_NUM_LANES_ALIGN 0 27267 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_NUM_LANES_BITS 3 27268 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_NUM_LANES_SHIFT 0 27269 27270 27271 /**************************************************************************** 27272 * sc_x4_final_config_status :: resolved_0 27273 */ 27274 /* sc_x4_final_config_status :: resolved_0 :: cl72_en [15:15] */ 27275 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_CL72_EN_MASK 0x8000 27276 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_CL72_EN_ALIGN 0 27277 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_CL72_EN_BITS 1 27278 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_CL72_EN_SHIFT 15 27279 27280 /* sc_x4_final_config_status :: resolved_0 :: os_mode [14:11] */ 27281 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_OS_MODE_MASK 0x7800 27282 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_OS_MODE_ALIGN 0 27283 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_OS_MODE_BITS 4 27284 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_OS_MODE_SHIFT 11 27285 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_OS_MODE_OS_MODE_1 0 27286 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_OS_MODE_OS_MODE_2 1 27287 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_OS_MODE_OS_MODE_4 2 27288 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_OS_MODE_OS_MODE_16p5 8 27289 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_OS_MODE_OS_MODE_20p625 12 27290 27291 /* sc_x4_final_config_status :: resolved_0 :: t_fifo_mode [10:09] */ 27292 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_T_FIFO_MODE_MASK 0x0600 27293 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_T_FIFO_MODE_ALIGN 0 27294 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_T_FIFO_MODE_BITS 2 27295 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_T_FIFO_MODE_SHIFT 9 27296 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_T_FIFO_MODE_T_FIFO_INSERT_NO_AM 0 27297 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_T_FIFO_MODE_T_FIFO_INSERT_4_AM 1 27298 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_T_FIFO_MODE_T_FIFO_INSERT_20_AM 2 27299 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_T_FIFO_MODE_T_FIFO_INSERT_2_AM 3 27300 27301 /* sc_x4_final_config_status :: resolved_0 :: t_enc_mode [08:07] */ 27302 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_T_ENC_MODE_MASK 0x0180 27303 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_T_ENC_MODE_ALIGN 0 27304 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_T_ENC_MODE_BITS 2 27305 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_T_ENC_MODE_SHIFT 7 27306 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_T_ENC_MODE_T_ENC_MODE_BYPASS 0 27307 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_T_ENC_MODE_T_ENC_MODE_CL49 1 27308 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_T_ENC_MODE_T_ENC_MODE_CL82 2 27309 27310 /* sc_x4_final_config_status :: resolved_0 :: t_HG2_ENABLE [06:06] */ 27311 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_T_HG2_ENABLE_MASK 0x0040 27312 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_T_HG2_ENABLE_ALIGN 0 27313 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_T_HG2_ENABLE_BITS 1 27314 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_T_HG2_ENABLE_SHIFT 6 27315 27316 /* sc_x4_final_config_status :: resolved_0 :: t_pma_btmx_mode [05:04] */ 27317 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_T_PMA_BTMX_MODE_MASK 0x0030 27318 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_T_PMA_BTMX_MODE_ALIGN 0 27319 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_T_PMA_BTMX_MODE_BITS 2 27320 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_T_PMA_BTMX_MODE_SHIFT 4 27321 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_T_PMA_BTMX_MODE_BS_BTMX_MODE_1to1 0 27322 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_T_PMA_BTMX_MODE_BS_BTMX_MODE_2to1 1 27323 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_T_PMA_BTMX_MODE_BS_BTMX_MODE_5to1 2 27324 27325 /* sc_x4_final_config_status :: resolved_0 :: scr_mode [03:01] */ 27326 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_SCR_MODE_MASK 0x000e 27327 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_SCR_MODE_ALIGN 0 27328 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_SCR_MODE_BITS 3 27329 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_SCR_MODE_SHIFT 1 27330 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_SCR_MODE_T_SCR_MODE_BYPASS 0 27331 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_SCR_MODE_T_SCR_MODE_CL49 1 27332 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_SCR_MODE_T_SCR_MODE_40G_2_LANE 2 27333 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_SCR_MODE_T_SCR_MODE_100G 3 27334 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_SCR_MODE_T_SCR_MODE_20G 4 27335 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_SCR_MODE_T_SCR_MODE_40G_4_LANE 5 27336 27337 /* sc_x4_final_config_status :: resolved_0 :: reserved0 [00:00] */ 27338 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_RESERVED0_MASK 0x0001 27339 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_RESERVED0_ALIGN 0 27340 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_RESERVED0_BITS 1 27341 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_RESERVED0_SHIFT 0 27342 27343 27344 /**************************************************************************** 27345 * sc_x4_final_config_status :: resolved_1 27346 */ 27347 /* sc_x4_final_config_status :: resolved_1 :: descr_mode [15:14] */ 27348 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_DESCR_MODE_MASK 0xc000 27349 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_DESCR_MODE_ALIGN 0 27350 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_DESCR_MODE_BITS 2 27351 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_DESCR_MODE_SHIFT 14 27352 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_DESCR_MODE_R_DESCR_MODE_BYPASS 0 27353 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_DESCR_MODE_R_DESCR_MODE_CL49 1 27354 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_DESCR_MODE_R_DESCR_MODE_CL82 2 27355 27356 /* sc_x4_final_config_status :: resolved_1 :: dec_tl_mode [13:12] */ 27357 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_DEC_TL_MODE_MASK 0x3000 27358 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_DEC_TL_MODE_ALIGN 0 27359 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_DEC_TL_MODE_BITS 2 27360 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_DEC_TL_MODE_SHIFT 12 27361 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_DEC_TL_MODE_R_DEC_TL_MODE_BYPASS 0 27362 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_DEC_TL_MODE_R_DEC_TL_MODE_CL49 1 27363 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_DEC_TL_MODE_R_DEC_TL_MODE_CL82 2 27364 27365 /* sc_x4_final_config_status :: resolved_1 :: deskew_mode [11:08] */ 27366 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_DESKEW_MODE_MASK 0x0f00 27367 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_DESKEW_MODE_ALIGN 0 27368 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_DESKEW_MODE_BITS 4 27369 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_DESKEW_MODE_SHIFT 8 27370 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_DESKEW_MODE_R_DESKEW_MODE_BYPASS 0 27371 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_DESKEW_MODE_R_DESKEW_MODE_20G 1 27372 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_DESKEW_MODE_R_DESKEW_MODE_40G_4_LANE 2 27373 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_DESKEW_MODE_R_DESKEW_MODE_40G_2_LANE 3 27374 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_DESKEW_MODE_R_DESKEW_MODE_100G 4 27375 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_DESKEW_MODE_R_DESKEW_MODE_CL49 5 27376 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_DESKEW_MODE_R_DESKEW_MODE_CL91_QUAD 6 27377 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_DESKEW_MODE_R_DESKEW_MODE_CL91_SINGLE_BRCM 7 27378 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_DESKEW_MODE_R_DESKEW_MODE_CL91_DUAL_BRCM 8 27379 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_DESKEW_MODE_R_DESKEW_MODE_CL91_FC 9 27380 27381 /* sc_x4_final_config_status :: resolved_1 :: dec_fsm_mode [07:06] */ 27382 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_DEC_FSM_MODE_MASK 0x00c0 27383 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_DEC_FSM_MODE_ALIGN 0 27384 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_DEC_FSM_MODE_BITS 2 27385 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_DEC_FSM_MODE_SHIFT 6 27386 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_DEC_FSM_MODE_R_DEC_FSM_MODE_BYPASS 0 27387 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_DEC_FSM_MODE_R_DEC_FSM_MODE_CL49 1 27388 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_DEC_FSM_MODE_R_DEC_FSM_MODE_CL82 2 27389 27390 /* sc_x4_final_config_status :: resolved_1 :: bs_sm_sync_mode [05:05] */ 27391 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_BS_SM_SYNC_MODE_MASK 0x0020 27392 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_BS_SM_SYNC_MODE_ALIGN 0 27393 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_BS_SM_SYNC_MODE_BITS 1 27394 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_BS_SM_SYNC_MODE_SHIFT 5 27395 27396 /* sc_x4_final_config_status :: resolved_1 :: bs_sync_en [04:04] */ 27397 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_BS_SYNC_EN_MASK 0x0010 27398 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_BS_SYNC_EN_ALIGN 0 27399 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_BS_SYNC_EN_BITS 1 27400 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_BS_SYNC_EN_SHIFT 4 27401 27402 /* sc_x4_final_config_status :: resolved_1 :: bs_dist_mode [03:02] */ 27403 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_BS_DIST_MODE_MASK 0x000c 27404 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_BS_DIST_MODE_ALIGN 0 27405 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_BS_DIST_MODE_BITS 2 27406 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_BS_DIST_MODE_SHIFT 2 27407 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_BS_DIST_MODE_BS_DIST_MODE_5_LANE_TDM 0 27408 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_BS_DIST_MODE_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 27409 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_BS_DIST_MODE_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 27410 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_BS_DIST_MODE_BS_DIST_MODE_NO_TDM 3 27411 27412 /* sc_x4_final_config_status :: resolved_1 :: bs_btmx_mode [01:00] */ 27413 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_BS_BTMX_MODE_MASK 0x0003 27414 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_BS_BTMX_MODE_ALIGN 0 27415 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_BS_BTMX_MODE_BITS 2 27416 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_BS_BTMX_MODE_SHIFT 0 27417 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_BS_BTMX_MODE_BS_BTMX_MODE_1to1 0 27418 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_BS_BTMX_MODE_BS_BTMX_MODE_2to1 1 27419 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_BS_BTMX_MODE_BS_BTMX_MODE_5to1 2 27420 27421 27422 /**************************************************************************** 27423 * sc_x4_final_config_status :: resolved_2 27424 */ 27425 /* sc_x4_final_config_status :: resolved_2 :: reserved0 [15:14] */ 27426 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_2_RESERVED0_MASK 0xc000 27427 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_2_RESERVED0_ALIGN 0 27428 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_2_RESERVED0_BITS 2 27429 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_2_RESERVED0_SHIFT 14 27430 27431 /* sc_x4_final_config_status :: resolved_2 :: clockcnt0 [13:00] */ 27432 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_2_CLOCKCNT0_MASK 0x3fff 27433 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_2_CLOCKCNT0_ALIGN 0 27434 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_2_CLOCKCNT0_BITS 14 27435 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_2_CLOCKCNT0_SHIFT 0 27436 27437 27438 /**************************************************************************** 27439 * sc_x4_final_config_status :: resolved_3 27440 */ 27441 /* sc_x4_final_config_status :: resolved_3 :: reserved0 [15:08] */ 27442 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_3_RESERVED0_MASK 0xff00 27443 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_3_RESERVED0_ALIGN 0 27444 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_3_RESERVED0_BITS 8 27445 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_3_RESERVED0_SHIFT 8 27446 27447 /* sc_x4_final_config_status :: resolved_3 :: clockcnt1 [07:00] */ 27448 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_3_CLOCKCNT1_MASK 0x00ff 27449 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_3_CLOCKCNT1_ALIGN 0 27450 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_3_CLOCKCNT1_BITS 8 27451 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_3_CLOCKCNT1_SHIFT 0 27452 27453 27454 /**************************************************************************** 27455 * sc_x4_final_config_status :: resolved_4 27456 */ 27457 /* sc_x4_final_config_status :: resolved_4 :: reserved0 [15:14] */ 27458 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_4_RESERVED0_MASK 0xc000 27459 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_4_RESERVED0_ALIGN 0 27460 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_4_RESERVED0_BITS 2 27461 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_4_RESERVED0_SHIFT 14 27462 27463 /* sc_x4_final_config_status :: resolved_4 :: loopcnt0 [13:06] */ 27464 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_4_LOOPCNT0_MASK 0x3fc0 27465 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_4_LOOPCNT0_ALIGN 0 27466 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_4_LOOPCNT0_BITS 8 27467 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_4_LOOPCNT0_SHIFT 6 27468 27469 /* sc_x4_final_config_status :: resolved_4 :: loopcnt1 [05:00] */ 27470 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_4_LOOPCNT1_MASK 0x003f 27471 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_4_LOOPCNT1_ALIGN 0 27472 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_4_LOOPCNT1_BITS 6 27473 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_4_LOOPCNT1_SHIFT 0 27474 27475 27476 /**************************************************************************** 27477 * sc_x4_final_config_status :: resolved_5 27478 */ 27479 /* sc_x4_final_config_status :: resolved_5 :: reserved0 [15:13] */ 27480 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_5_RESERVED0_MASK 0xe000 27481 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_5_RESERVED0_ALIGN 0 27482 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_5_RESERVED0_BITS 3 27483 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_5_RESERVED0_SHIFT 13 27484 27485 /* sc_x4_final_config_status :: resolved_5 :: mac_creditgencnt [12:00] */ 27486 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_5_MAC_CREDITGENCNT_MASK 0x1fff 27487 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_5_MAC_CREDITGENCNT_ALIGN 0 27488 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_5_MAC_CREDITGENCNT_BITS 13 27489 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_5_MAC_CREDITGENCNT_SHIFT 0 27490 27491 27492 /**************************************************************************** 27493 * sc_x4_final_config_status :: fec_status 27494 */ 27495 /* sc_x4_final_config_status :: fec_status :: reserved0 [15:08] */ 27496 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_RESERVED0_MASK 0xff00 27497 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_RESERVED0_ALIGN 0 27498 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_RESERVED0_BITS 8 27499 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_RESERVED0_SHIFT 8 27500 27501 /* sc_x4_final_config_status :: fec_status :: t_cl91_fec_mode [07:05] */ 27502 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_T_CL91_FEC_MODE_MASK 0x00e0 27503 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_T_CL91_FEC_MODE_ALIGN 0 27504 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_T_CL91_FEC_MODE_BITS 3 27505 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_T_CL91_FEC_MODE_SHIFT 5 27506 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_T_CL91_FEC_MODE_NO_CL91_FEC 0 27507 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_T_CL91_FEC_MODE_CL91_SINGLE_LANE_FC 1 27508 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_T_CL91_FEC_MODE_CL91_SINGLE_LANE_BRCM_PROP 2 27509 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_T_CL91_FEC_MODE_CL91_DUAL_LANE_BRCM_PROP 3 27510 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_T_CL91_FEC_MODE_CL91_QUAD_LANE 4 27511 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_T_CL91_FEC_MODE_IEEE_25G_CL91_SINGLE_LANE 5 27512 27513 /* sc_x4_final_config_status :: fec_status :: r_cl91_fec_mode [04:02] */ 27514 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_R_CL91_FEC_MODE_MASK 0x001c 27515 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_R_CL91_FEC_MODE_ALIGN 0 27516 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_R_CL91_FEC_MODE_BITS 3 27517 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_R_CL91_FEC_MODE_SHIFT 2 27518 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_R_CL91_FEC_MODE_NO_CL91_FEC 0 27519 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_R_CL91_FEC_MODE_CL91_SINGLE_LANE_FC 1 27520 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_R_CL91_FEC_MODE_CL91_SINGLE_LANE_BRCM_PROP 2 27521 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_R_CL91_FEC_MODE_CL91_DUAL_LANE_BRCM_PROP 3 27522 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_R_CL91_FEC_MODE_CL91_QUAD_LANE 4 27523 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_R_CL91_FEC_MODE_IEEE_25G_CL91_SINGLE_LANE 5 27524 27525 /* sc_x4_final_config_status :: fec_status :: t_fec_enable [01:01] */ 27526 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_T_FEC_ENABLE_MASK 0x0002 27527 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_T_FEC_ENABLE_ALIGN 0 27528 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_T_FEC_ENABLE_BITS 1 27529 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_T_FEC_ENABLE_SHIFT 1 27530 27531 /* sc_x4_final_config_status :: fec_status :: r_fec_enable [00:00] */ 27532 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_R_FEC_ENABLE_MASK 0x0001 27533 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_R_FEC_ENABLE_ALIGN 0 27534 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_R_FEC_ENABLE_BITS 1 27535 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_R_FEC_ENABLE_SHIFT 0 27536 27537 27538 /**************************************************************************** 27539 * sc_x4_final_config_status :: resolved_6 27540 */ 27541 /* sc_x4_final_config_status :: resolved_6 :: reserved0 [15:11] */ 27542 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_6_RESERVED0_MASK 0xf800 27543 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_6_RESERVED0_ALIGN 0 27544 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_6_RESERVED0_BITS 5 27545 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_6_RESERVED0_SHIFT 11 27546 27547 /* sc_x4_final_config_status :: resolved_6 :: AM_spacing_mul [10:09] */ 27548 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_6_AM_SPACING_MUL_MASK 0x0600 27549 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_6_AM_SPACING_MUL_ALIGN 0 27550 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_6_AM_SPACING_MUL_BITS 2 27551 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_6_AM_SPACING_MUL_SHIFT 9 27552 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_6_AM_SPACING_MUL_AM_SPACING_MUL_2 0 27553 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_6_AM_SPACING_MUL_AM_SPACING_MUL_4 1 27554 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_6_AM_SPACING_MUL_AM_SPACING_MUL_5 2 27555 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_6_AM_SPACING_MUL_AM_SPACING_MUL_20 3 27556 27557 /* sc_x4_final_config_status :: resolved_6 :: t_pma_bitmux_delay [08:07] */ 27558 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_6_T_PMA_BITMUX_DELAY_MASK 0x0180 27559 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_6_T_PMA_BITMUX_DELAY_ALIGN 0 27560 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_6_T_PMA_BITMUX_DELAY_BITS 2 27561 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_6_T_PMA_BITMUX_DELAY_SHIFT 7 27562 27563 /* sc_x4_final_config_status :: resolved_6 :: t_pma_watermark [06:03] */ 27564 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_6_T_PMA_WATERMARK_MASK 0x0078 27565 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_6_T_PMA_WATERMARK_ALIGN 0 27566 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_6_T_PMA_WATERMARK_BITS 4 27567 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_6_T_PMA_WATERMARK_SHIFT 3 27568 27569 /* sc_x4_final_config_status :: resolved_6 :: t_pma_cl91_mux_sel [02:02] */ 27570 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_6_T_PMA_CL91_MUX_SEL_MASK 0x0004 27571 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_6_T_PMA_CL91_MUX_SEL_ALIGN 0 27572 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_6_T_PMA_CL91_MUX_SEL_BITS 1 27573 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_6_T_PMA_CL91_MUX_SEL_SHIFT 2 27574 27575 /* sc_x4_final_config_status :: resolved_6 :: t_five_bit_xor_en [01:01] */ 27576 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_6_T_FIVE_BIT_XOR_EN_MASK 0x0002 27577 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_6_T_FIVE_BIT_XOR_EN_ALIGN 0 27578 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_6_T_FIVE_BIT_XOR_EN_BITS 1 27579 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_6_T_FIVE_BIT_XOR_EN_SHIFT 1 27580 27581 /* sc_x4_final_config_status :: resolved_6 :: t_cl91_cw_scramble [00:00] */ 27582 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_6_T_CL91_CW_SCRAMBLE_MASK 0x0001 27583 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_6_T_CL91_CW_SCRAMBLE_ALIGN 0 27584 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_6_T_CL91_CW_SCRAMBLE_BITS 1 27585 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_6_T_CL91_CW_SCRAMBLE_SHIFT 0 27586 27587 27588 /**************************************************************************** 27589 * sc_x4_final_config_status :: resolved_7 27590 */ 27591 /* sc_x4_final_config_status :: resolved_7 :: reserved0 [15:14] */ 27592 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_RESERVED0_MASK 0xc000 27593 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_RESERVED0_ALIGN 0 27594 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_RESERVED0_BITS 2 27595 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_RESERVED0_SHIFT 14 27596 27597 /* sc_x4_final_config_status :: resolved_7 :: r_HG2_ENABLE [13:13] */ 27598 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_R_HG2_ENABLE_MASK 0x2000 27599 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_R_HG2_ENABLE_ALIGN 0 27600 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_R_HG2_ENABLE_BITS 1 27601 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_R_HG2_ENABLE_SHIFT 13 27602 27603 /* sc_x4_final_config_status :: resolved_7 :: r_tc_out_mode [12:11] */ 27604 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_R_TC_OUT_MODE_MASK 0x1800 27605 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_R_TC_OUT_MODE_ALIGN 0 27606 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_R_TC_OUT_MODE_BITS 2 27607 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_R_TC_OUT_MODE_SHIFT 11 27608 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_R_TC_OUT_MODE_R_TC_OUT_MODE_SINGLE 0 27609 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_R_TC_OUT_MODE_R_TC_OUT_MODE_DUAL 1 27610 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_R_TC_OUT_MODE_R_TC_OUT_MODE_QUAD 2 27611 27612 /* sc_x4_final_config_status :: resolved_7 :: r_five_bit_xor_en [10:10] */ 27613 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_R_FIVE_BIT_XOR_EN_MASK 0x0400 27614 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_R_FIVE_BIT_XOR_EN_ALIGN 0 27615 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_R_FIVE_BIT_XOR_EN_BITS 1 27616 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_R_FIVE_BIT_XOR_EN_SHIFT 10 27617 27618 /* sc_x4_final_config_status :: resolved_7 :: r_tc_mode [09:08] */ 27619 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_R_TC_MODE_MASK 0x0300 27620 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_R_TC_MODE_ALIGN 0 27621 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_R_TC_MODE_BITS 2 27622 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_R_TC_MODE_SHIFT 8 27623 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_R_TC_MODE_R_TC_MODE_SINGLE 0 27624 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_R_TC_MODE_R_TC_MODE_DUAL 1 27625 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_R_TC_MODE_R_TC_MODE_QUAD 2 27626 27627 /* sc_x4_final_config_status :: resolved_7 :: r_tc_in_mode [07:07] */ 27628 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_R_TC_IN_MODE_MASK 0x0080 27629 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_R_TC_IN_MODE_ALIGN 0 27630 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_R_TC_IN_MODE_BITS 1 27631 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_R_TC_IN_MODE_SHIFT 7 27632 27633 /* sc_x4_final_config_status :: resolved_7 :: r_cl91_cw_scramble [06:06] */ 27634 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_R_CL91_CW_SCRAMBLE_MASK 0x0040 27635 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_R_CL91_CW_SCRAMBLE_ALIGN 0 27636 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_R_CL91_CW_SCRAMBLE_BITS 1 27637 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_R_CL91_CW_SCRAMBLE_SHIFT 6 27638 27639 /* sc_x4_final_config_status :: resolved_7 :: r_merge_mode [05:03] */ 27640 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_R_MERGE_MODE_MASK 0x0038 27641 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_R_MERGE_MODE_ALIGN 0 27642 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_R_MERGE_MODE_BITS 3 27643 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_R_MERGE_MODE_SHIFT 3 27644 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_R_MERGE_MODE_R_MERGE_MODE_BYPASS 0 27645 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_R_MERGE_MODE_R_MERGE_MODE_CL91_FC 1 27646 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_R_MERGE_MODE_R_MERGE_MODE_CL91_SINGLE_LANE 2 27647 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_R_MERGE_MODE_R_MERGE_MODE_CL91_DUAL_LANE 3 27648 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_R_MERGE_MODE_R_MERGE_MODE_CL91_QUAD_LANE 4 27649 27650 /* sc_x4_final_config_status :: resolved_7 :: cl91_blksync_mode [02:00] */ 27651 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_CL91_BLKSYNC_MODE_MASK 0x0007 27652 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_CL91_BLKSYNC_MODE_ALIGN 0 27653 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_CL91_BLKSYNC_MODE_BITS 3 27654 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_CL91_BLKSYNC_MODE_SHIFT 0 27655 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_CL91_BLKSYNC_MODE_R_BLKSYNC_NO_CL91_FEC 0 27656 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_CL91_BLKSYNC_MODE_R_BLKSYNC_CL91_QUAD_LANE_FEC 1 27657 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_CL91_BLKSYNC_MODE_R_BLKSYNC_CL91_DUAL_LANE_FEC 2 27658 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_CL91_BLKSYNC_MODE_R_BLKSYNC_CL91_SINGLE_LANE_FEC 3 27659 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_CL91_BLKSYNC_MODE_R_BLKSYNC_CL91_FC_FEC 4 27660 27661 27662 /**************************************************************************** 27663 * TSC_WC4_TSC_USER4_TX_X4_Credit0 27664 */ 27665 /**************************************************************************** 27666 * TX_X4_Credit0 :: credit0 27667 */ 27668 /* TX_X4_Credit0 :: credit0 :: reserved0 [15:15] */ 27669 #define TX_X4_CREDIT0_CREDIT0_RESERVED0_MASK 0x8000 27670 #define TX_X4_CREDIT0_CREDIT0_RESERVED0_ALIGN 0 27671 #define TX_X4_CREDIT0_CREDIT0_RESERVED0_BITS 1 27672 #define TX_X4_CREDIT0_CREDIT0_RESERVED0_SHIFT 15 27673 27674 /* TX_X4_Credit0 :: credit0 :: creditenable [14:14] */ 27675 #define TX_X4_CREDIT0_CREDIT0_CREDITENABLE_MASK 0x4000 27676 #define TX_X4_CREDIT0_CREDIT0_CREDITENABLE_ALIGN 0 27677 #define TX_X4_CREDIT0_CREDIT0_CREDITENABLE_BITS 1 27678 #define TX_X4_CREDIT0_CREDIT0_CREDITENABLE_SHIFT 14 27679 27680 /* TX_X4_Credit0 :: credit0 :: clockcnt0 [13:00] */ 27681 #define TX_X4_CREDIT0_CREDIT0_CLOCKCNT0_MASK 0x3fff 27682 #define TX_X4_CREDIT0_CREDIT0_CLOCKCNT0_ALIGN 0 27683 #define TX_X4_CREDIT0_CREDIT0_CLOCKCNT0_BITS 14 27684 #define TX_X4_CREDIT0_CREDIT0_CLOCKCNT0_SHIFT 0 27685 27686 27687 /**************************************************************************** 27688 * TX_X4_Credit0 :: credit1 27689 */ 27690 /* TX_X4_Credit0 :: credit1 :: reserved0 [15:08] */ 27691 #define TX_X4_CREDIT0_CREDIT1_RESERVED0_MASK 0xff00 27692 #define TX_X4_CREDIT0_CREDIT1_RESERVED0_ALIGN 0 27693 #define TX_X4_CREDIT0_CREDIT1_RESERVED0_BITS 8 27694 #define TX_X4_CREDIT0_CREDIT1_RESERVED0_SHIFT 8 27695 27696 /* TX_X4_Credit0 :: credit1 :: clockcnt1 [07:00] */ 27697 #define TX_X4_CREDIT0_CREDIT1_CLOCKCNT1_MASK 0x00ff 27698 #define TX_X4_CREDIT0_CREDIT1_CLOCKCNT1_ALIGN 0 27699 #define TX_X4_CREDIT0_CREDIT1_CLOCKCNT1_BITS 8 27700 #define TX_X4_CREDIT0_CREDIT1_CLOCKCNT1_SHIFT 0 27701 27702 27703 /**************************************************************************** 27704 * TX_X4_Credit0 :: loopcnt 27705 */ 27706 /* TX_X4_Credit0 :: loopcnt :: reserved0 [15:14] */ 27707 #define TX_X4_CREDIT0_LOOPCNT_RESERVED0_MASK 0xc000 27708 #define TX_X4_CREDIT0_LOOPCNT_RESERVED0_ALIGN 0 27709 #define TX_X4_CREDIT0_LOOPCNT_RESERVED0_BITS 2 27710 #define TX_X4_CREDIT0_LOOPCNT_RESERVED0_SHIFT 14 27711 27712 /* TX_X4_Credit0 :: loopcnt :: loopcnt0 [13:06] */ 27713 #define TX_X4_CREDIT0_LOOPCNT_LOOPCNT0_MASK 0x3fc0 27714 #define TX_X4_CREDIT0_LOOPCNT_LOOPCNT0_ALIGN 0 27715 #define TX_X4_CREDIT0_LOOPCNT_LOOPCNT0_BITS 8 27716 #define TX_X4_CREDIT0_LOOPCNT_LOOPCNT0_SHIFT 6 27717 27718 /* TX_X4_Credit0 :: loopcnt :: loopcnt1 [05:00] */ 27719 #define TX_X4_CREDIT0_LOOPCNT_LOOPCNT1_MASK 0x003f 27720 #define TX_X4_CREDIT0_LOOPCNT_LOOPCNT1_ALIGN 0 27721 #define TX_X4_CREDIT0_LOOPCNT_LOOPCNT1_BITS 6 27722 #define TX_X4_CREDIT0_LOOPCNT_LOOPCNT1_SHIFT 0 27723 27724 27725 /**************************************************************************** 27726 * TX_X4_Credit0 :: mac_creditgencnt 27727 */ 27728 /* TX_X4_Credit0 :: mac_creditgencnt :: reserved0 [15:13] */ 27729 #define TX_X4_CREDIT0_MAC_CREDITGENCNT_RESERVED0_MASK 0xe000 27730 #define TX_X4_CREDIT0_MAC_CREDITGENCNT_RESERVED0_ALIGN 0 27731 #define TX_X4_CREDIT0_MAC_CREDITGENCNT_RESERVED0_BITS 3 27732 #define TX_X4_CREDIT0_MAC_CREDITGENCNT_RESERVED0_SHIFT 13 27733 27734 /* TX_X4_Credit0 :: mac_creditgencnt :: mac_creditgencnt [12:00] */ 27735 #define TX_X4_CREDIT0_MAC_CREDITGENCNT_MAC_CREDITGENCNT_MASK 0x1fff 27736 #define TX_X4_CREDIT0_MAC_CREDITGENCNT_MAC_CREDITGENCNT_ALIGN 0 27737 #define TX_X4_CREDIT0_MAC_CREDITGENCNT_MAC_CREDITGENCNT_BITS 13 27738 #define TX_X4_CREDIT0_MAC_CREDITGENCNT_MAC_CREDITGENCNT_SHIFT 0 27739 27740 27741 /**************************************************************************** 27742 * TSC_WC4_TSC_USER4_TX_X4_Control0 27743 */ 27744 /**************************************************************************** 27745 * TX_X4_Control0 :: encode_0 27746 */ 27747 /* TX_X4_Control0 :: encode_0 :: reserved0 [15:15] */ 27748 #define TX_X4_CONTROL0_ENCODE_0_RESERVED0_MASK 0x8000 27749 #define TX_X4_CONTROL0_ENCODE_0_RESERVED0_ALIGN 0 27750 #define TX_X4_CONTROL0_ENCODE_0_RESERVED0_BITS 1 27751 #define TX_X4_CONTROL0_ENCODE_0_RESERVED0_SHIFT 15 27752 27753 /* TX_X4_Control0 :: encode_0 :: dis_scrambler [14:14] */ 27754 #define TX_X4_CONTROL0_ENCODE_0_DIS_SCRAMBLER_MASK 0x4000 27755 #define TX_X4_CONTROL0_ENCODE_0_DIS_SCRAMBLER_ALIGN 0 27756 #define TX_X4_CONTROL0_ENCODE_0_DIS_SCRAMBLER_BITS 1 27757 #define TX_X4_CONTROL0_ENCODE_0_DIS_SCRAMBLER_SHIFT 14 27758 27759 /* TX_X4_Control0 :: encode_0 :: block_non_fc_blk_types [13:13] */ 27760 #define TX_X4_CONTROL0_ENCODE_0_BLOCK_NON_FC_BLK_TYPES_MASK 0x2000 27761 #define TX_X4_CONTROL0_ENCODE_0_BLOCK_NON_FC_BLK_TYPES_ALIGN 0 27762 #define TX_X4_CONTROL0_ENCODE_0_BLOCK_NON_FC_BLK_TYPES_BITS 1 27763 #define TX_X4_CONTROL0_ENCODE_0_BLOCK_NON_FC_BLK_TYPES_SHIFT 13 27764 27765 /* TX_X4_Control0 :: encode_0 :: HG2_CODEC [12:12] */ 27766 #define TX_X4_CONTROL0_ENCODE_0_HG2_CODEC_MASK 0x1000 27767 #define TX_X4_CONTROL0_ENCODE_0_HG2_CODEC_ALIGN 0 27768 #define TX_X4_CONTROL0_ENCODE_0_HG2_CODEC_BITS 1 27769 #define TX_X4_CONTROL0_ENCODE_0_HG2_CODEC_SHIFT 12 27770 27771 /* TX_X4_Control0 :: encode_0 :: HG2_MESSAGE_INVALID_CODE_ENABLE [11:11] */ 27772 #define TX_X4_CONTROL0_ENCODE_0_HG2_MESSAGE_INVALID_CODE_ENABLE_MASK 0x0800 27773 #define TX_X4_CONTROL0_ENCODE_0_HG2_MESSAGE_INVALID_CODE_ENABLE_ALIGN 0 27774 #define TX_X4_CONTROL0_ENCODE_0_HG2_MESSAGE_INVALID_CODE_ENABLE_BITS 1 27775 #define TX_X4_CONTROL0_ENCODE_0_HG2_MESSAGE_INVALID_CODE_ENABLE_SHIFT 11 27776 27777 /* TX_X4_Control0 :: encode_0 :: HG2_ENABLE [10:10] */ 27778 #define TX_X4_CONTROL0_ENCODE_0_HG2_ENABLE_MASK 0x0400 27779 #define TX_X4_CONTROL0_ENCODE_0_HG2_ENABLE_ALIGN 0 27780 #define TX_X4_CONTROL0_ENCODE_0_HG2_ENABLE_BITS 1 27781 #define TX_X4_CONTROL0_ENCODE_0_HG2_ENABLE_SHIFT 10 27782 27783 /* TX_X4_Control0 :: encode_0 :: cl49_bypass_txsm [09:09] */ 27784 #define TX_X4_CONTROL0_ENCODE_0_CL49_BYPASS_TXSM_MASK 0x0200 27785 #define TX_X4_CONTROL0_ENCODE_0_CL49_BYPASS_TXSM_ALIGN 0 27786 #define TX_X4_CONTROL0_ENCODE_0_CL49_BYPASS_TXSM_BITS 1 27787 #define TX_X4_CONTROL0_ENCODE_0_CL49_BYPASS_TXSM_SHIFT 9 27788 27789 /* TX_X4_Control0 :: encode_0 :: cl49_tx_tl_mode [08:07] */ 27790 #define TX_X4_CONTROL0_ENCODE_0_CL49_TX_TL_MODE_MASK 0x0180 27791 #define TX_X4_CONTROL0_ENCODE_0_CL49_TX_TL_MODE_ALIGN 0 27792 #define TX_X4_CONTROL0_ENCODE_0_CL49_TX_TL_MODE_BITS 2 27793 #define TX_X4_CONTROL0_ENCODE_0_CL49_TX_TL_MODE_SHIFT 7 27794 27795 /* TX_X4_Control0 :: encode_0 :: reserved1 [06:06] */ 27796 #define TX_X4_CONTROL0_ENCODE_0_RESERVED1_MASK 0x0040 27797 #define TX_X4_CONTROL0_ENCODE_0_RESERVED1_ALIGN 0 27798 #define TX_X4_CONTROL0_ENCODE_0_RESERVED1_BITS 1 27799 #define TX_X4_CONTROL0_ENCODE_0_RESERVED1_SHIFT 6 27800 27801 /* TX_X4_Control0 :: encode_0 :: AM_spacing_mul [05:04] */ 27802 #define TX_X4_CONTROL0_ENCODE_0_AM_SPACING_MUL_MASK 0x0030 27803 #define TX_X4_CONTROL0_ENCODE_0_AM_SPACING_MUL_ALIGN 0 27804 #define TX_X4_CONTROL0_ENCODE_0_AM_SPACING_MUL_BITS 2 27805 #define TX_X4_CONTROL0_ENCODE_0_AM_SPACING_MUL_SHIFT 4 27806 #define TX_X4_CONTROL0_ENCODE_0_AM_SPACING_MUL_AM_SPACING_MUL_2 0 27807 #define TX_X4_CONTROL0_ENCODE_0_AM_SPACING_MUL_AM_SPACING_MUL_4 1 27808 #define TX_X4_CONTROL0_ENCODE_0_AM_SPACING_MUL_AM_SPACING_MUL_5 2 27809 #define TX_X4_CONTROL0_ENCODE_0_AM_SPACING_MUL_AM_SPACING_MUL_20 3 27810 27811 /* TX_X4_Control0 :: encode_0 :: t_fifo_mode [03:02] */ 27812 #define TX_X4_CONTROL0_ENCODE_0_T_FIFO_MODE_MASK 0x000c 27813 #define TX_X4_CONTROL0_ENCODE_0_T_FIFO_MODE_ALIGN 0 27814 #define TX_X4_CONTROL0_ENCODE_0_T_FIFO_MODE_BITS 2 27815 #define TX_X4_CONTROL0_ENCODE_0_T_FIFO_MODE_SHIFT 2 27816 #define TX_X4_CONTROL0_ENCODE_0_T_FIFO_MODE_T_FIFO_INSERT_NO_AM 0 27817 #define TX_X4_CONTROL0_ENCODE_0_T_FIFO_MODE_T_FIFO_INSERT_4_AM 1 27818 #define TX_X4_CONTROL0_ENCODE_0_T_FIFO_MODE_T_FIFO_INSERT_20_AM 2 27819 #define TX_X4_CONTROL0_ENCODE_0_T_FIFO_MODE_T_FIFO_INSERT_2_AM 3 27820 27821 /* TX_X4_Control0 :: encode_0 :: t_enc_mode [01:00] */ 27822 #define TX_X4_CONTROL0_ENCODE_0_T_ENC_MODE_MASK 0x0003 27823 #define TX_X4_CONTROL0_ENCODE_0_T_ENC_MODE_ALIGN 0 27824 #define TX_X4_CONTROL0_ENCODE_0_T_ENC_MODE_BITS 2 27825 #define TX_X4_CONTROL0_ENCODE_0_T_ENC_MODE_SHIFT 0 27826 #define TX_X4_CONTROL0_ENCODE_0_T_ENC_MODE_T_ENC_MODE_BYPASS 0 27827 #define TX_X4_CONTROL0_ENCODE_0_T_ENC_MODE_T_ENC_MODE_CL49 1 27828 #define TX_X4_CONTROL0_ENCODE_0_T_ENC_MODE_T_ENC_MODE_CL82 2 27829 27830 27831 /**************************************************************************** 27832 * TX_X4_Control0 :: misc 27833 */ 27834 /* TX_X4_Control0 :: misc :: scr_mode [15:13] */ 27835 #define TX_X4_CONTROL0_MISC_SCR_MODE_MASK 0xe000 27836 #define TX_X4_CONTROL0_MISC_SCR_MODE_ALIGN 0 27837 #define TX_X4_CONTROL0_MISC_SCR_MODE_BITS 3 27838 #define TX_X4_CONTROL0_MISC_SCR_MODE_SHIFT 13 27839 #define TX_X4_CONTROL0_MISC_SCR_MODE_T_SCR_MODE_BYPASS 0 27840 #define TX_X4_CONTROL0_MISC_SCR_MODE_T_SCR_MODE_CL49 1 27841 #define TX_X4_CONTROL0_MISC_SCR_MODE_T_SCR_MODE_40G_2_LANE 2 27842 #define TX_X4_CONTROL0_MISC_SCR_MODE_T_SCR_MODE_100G 3 27843 #define TX_X4_CONTROL0_MISC_SCR_MODE_T_SCR_MODE_20G 4 27844 #define TX_X4_CONTROL0_MISC_SCR_MODE_T_SCR_MODE_40G_4_LANE 5 27845 27846 /* TX_X4_Control0 :: misc :: t_pma_btmx_mode [12:11] */ 27847 #define TX_X4_CONTROL0_MISC_T_PMA_BTMX_MODE_MASK 0x1800 27848 #define TX_X4_CONTROL0_MISC_T_PMA_BTMX_MODE_ALIGN 0 27849 #define TX_X4_CONTROL0_MISC_T_PMA_BTMX_MODE_BITS 2 27850 #define TX_X4_CONTROL0_MISC_T_PMA_BTMX_MODE_SHIFT 11 27851 #define TX_X4_CONTROL0_MISC_T_PMA_BTMX_MODE_BS_BTMX_MODE_1to1 0 27852 #define TX_X4_CONTROL0_MISC_T_PMA_BTMX_MODE_BS_BTMX_MODE_2to1 1 27853 #define TX_X4_CONTROL0_MISC_T_PMA_BTMX_MODE_BS_BTMX_MODE_5to1 2 27854 27855 /* TX_X4_Control0 :: misc :: fec_enable [10:10] */ 27856 #define TX_X4_CONTROL0_MISC_FEC_ENABLE_MASK 0x0400 27857 #define TX_X4_CONTROL0_MISC_FEC_ENABLE_ALIGN 0 27858 #define TX_X4_CONTROL0_MISC_FEC_ENABLE_BITS 1 27859 #define TX_X4_CONTROL0_MISC_FEC_ENABLE_SHIFT 10 27860 27861 /* TX_X4_Control0 :: misc :: t_pma_40b_mode [09:09] */ 27862 #define TX_X4_CONTROL0_MISC_T_PMA_40B_MODE_MASK 0x0200 27863 #define TX_X4_CONTROL0_MISC_T_PMA_40B_MODE_ALIGN 0 27864 #define TX_X4_CONTROL0_MISC_T_PMA_40B_MODE_BITS 1 27865 #define TX_X4_CONTROL0_MISC_T_PMA_40B_MODE_SHIFT 9 27866 27867 /* TX_X4_Control0 :: misc :: cl49_tx_li_enable [08:08] */ 27868 #define TX_X4_CONTROL0_MISC_CL49_TX_LI_ENABLE_MASK 0x0100 27869 #define TX_X4_CONTROL0_MISC_CL49_TX_LI_ENABLE_ALIGN 0 27870 #define TX_X4_CONTROL0_MISC_CL49_TX_LI_ENABLE_BITS 1 27871 #define TX_X4_CONTROL0_MISC_CL49_TX_LI_ENABLE_SHIFT 8 27872 27873 /* TX_X4_Control0 :: misc :: cl49_tx_lf_enable [07:07] */ 27874 #define TX_X4_CONTROL0_MISC_CL49_TX_LF_ENABLE_MASK 0x0080 27875 #define TX_X4_CONTROL0_MISC_CL49_TX_LF_ENABLE_ALIGN 0 27876 #define TX_X4_CONTROL0_MISC_CL49_TX_LF_ENABLE_BITS 1 27877 #define TX_X4_CONTROL0_MISC_CL49_TX_LF_ENABLE_SHIFT 7 27878 27879 /* TX_X4_Control0 :: misc :: cl49_tx_rf_enable [06:06] */ 27880 #define TX_X4_CONTROL0_MISC_CL49_TX_RF_ENABLE_MASK 0x0040 27881 #define TX_X4_CONTROL0_MISC_CL49_TX_RF_ENABLE_ALIGN 0 27882 #define TX_X4_CONTROL0_MISC_CL49_TX_RF_ENABLE_BITS 1 27883 #define TX_X4_CONTROL0_MISC_CL49_TX_RF_ENABLE_SHIFT 6 27884 27885 /* TX_X4_Control0 :: misc :: os_mode [05:02] */ 27886 #define TX_X4_CONTROL0_MISC_OS_MODE_MASK 0x003c 27887 #define TX_X4_CONTROL0_MISC_OS_MODE_ALIGN 0 27888 #define TX_X4_CONTROL0_MISC_OS_MODE_BITS 4 27889 #define TX_X4_CONTROL0_MISC_OS_MODE_SHIFT 2 27890 #define TX_X4_CONTROL0_MISC_OS_MODE_OS_MODE_1 0 27891 #define TX_X4_CONTROL0_MISC_OS_MODE_OS_MODE_2 1 27892 #define TX_X4_CONTROL0_MISC_OS_MODE_OS_MODE_4 2 27893 #define TX_X4_CONTROL0_MISC_OS_MODE_OS_MODE_16p5 8 27894 #define TX_X4_CONTROL0_MISC_OS_MODE_OS_MODE_20p625 12 27895 27896 /* TX_X4_Control0 :: misc :: rstb_tx_lane [01:01] */ 27897 #define TX_X4_CONTROL0_MISC_RSTB_TX_LANE_MASK 0x0002 27898 #define TX_X4_CONTROL0_MISC_RSTB_TX_LANE_ALIGN 0 27899 #define TX_X4_CONTROL0_MISC_RSTB_TX_LANE_BITS 1 27900 #define TX_X4_CONTROL0_MISC_RSTB_TX_LANE_SHIFT 1 27901 27902 /* TX_X4_Control0 :: misc :: enable_tx_lane [00:00] */ 27903 #define TX_X4_CONTROL0_MISC_ENABLE_TX_LANE_MASK 0x0001 27904 #define TX_X4_CONTROL0_MISC_ENABLE_TX_LANE_ALIGN 0 27905 #define TX_X4_CONTROL0_MISC_ENABLE_TX_LANE_BITS 1 27906 #define TX_X4_CONTROL0_MISC_ENABLE_TX_LANE_SHIFT 0 27907 27908 27909 /**************************************************************************** 27910 * TX_X4_Control0 :: cl36tx_control 27911 */ 27912 /* TX_X4_Control0 :: cl36tx_control :: reserved0 [15:03] */ 27913 #define TX_X4_CONTROL0_CL36TX_CONTROL_RESERVED0_MASK 0xfff8 27914 #define TX_X4_CONTROL0_CL36TX_CONTROL_RESERVED0_ALIGN 0 27915 #define TX_X4_CONTROL0_CL36TX_CONTROL_RESERVED0_BITS 13 27916 #define TX_X4_CONTROL0_CL36TX_CONTROL_RESERVED0_SHIFT 3 27917 27918 /* TX_X4_Control0 :: cl36tx_control :: cl36tx_catch_all_8b10b_dis [02:02] */ 27919 #define TX_X4_CONTROL0_CL36TX_CONTROL_CL36TX_CATCH_ALL_8B10B_DIS_MASK 0x0004 27920 #define TX_X4_CONTROL0_CL36TX_CONTROL_CL36TX_CATCH_ALL_8B10B_DIS_ALIGN 0 27921 #define TX_X4_CONTROL0_CL36TX_CONTROL_CL36TX_CATCH_ALL_8B10B_DIS_BITS 1 27922 #define TX_X4_CONTROL0_CL36TX_CONTROL_CL36TX_CATCH_ALL_8B10B_DIS_SHIFT 2 27923 27924 /* TX_X4_Control0 :: cl36tx_control :: cl36tx_LPI_en [01:01] */ 27925 #define TX_X4_CONTROL0_CL36TX_CONTROL_CL36TX_LPI_EN_MASK 0x0002 27926 #define TX_X4_CONTROL0_CL36TX_CONTROL_CL36TX_LPI_EN_ALIGN 0 27927 #define TX_X4_CONTROL0_CL36TX_CONTROL_CL36TX_LPI_EN_BITS 1 27928 #define TX_X4_CONTROL0_CL36TX_CONTROL_CL36TX_LPI_EN_SHIFT 1 27929 27930 /* TX_X4_Control0 :: cl36tx_control :: cl36tx_en [00:00] */ 27931 #define TX_X4_CONTROL0_CL36TX_CONTROL_CL36TX_EN_MASK 0x0001 27932 #define TX_X4_CONTROL0_CL36TX_CONTROL_CL36TX_EN_ALIGN 0 27933 #define TX_X4_CONTROL0_CL36TX_CONTROL_CL36TX_EN_BITS 1 27934 #define TX_X4_CONTROL0_CL36TX_CONTROL_CL36TX_EN_SHIFT 0 27935 27936 27937 /**************************************************************************** 27938 * TX_X4_Control0 :: tx_control0 27939 */ 27940 /* TX_X4_Control0 :: tx_control0 :: reserved0 [15:12] */ 27941 #define TX_X4_CONTROL0_TX_CONTROL0_RESERVED0_MASK 0xf000 27942 #define TX_X4_CONTROL0_TX_CONTROL0_RESERVED0_ALIGN 0 27943 #define TX_X4_CONTROL0_TX_CONTROL0_RESERVED0_BITS 4 27944 #define TX_X4_CONTROL0_TX_CONTROL0_RESERVED0_SHIFT 12 27945 27946 /* TX_X4_Control0 :: tx_control0 :: cl91_fec_mode [11:09] */ 27947 #define TX_X4_CONTROL0_TX_CONTROL0_CL91_FEC_MODE_MASK 0x0e00 27948 #define TX_X4_CONTROL0_TX_CONTROL0_CL91_FEC_MODE_ALIGN 0 27949 #define TX_X4_CONTROL0_TX_CONTROL0_CL91_FEC_MODE_BITS 3 27950 #define TX_X4_CONTROL0_TX_CONTROL0_CL91_FEC_MODE_SHIFT 9 27951 #define TX_X4_CONTROL0_TX_CONTROL0_CL91_FEC_MODE_NO_CL91_FEC 0 27952 #define TX_X4_CONTROL0_TX_CONTROL0_CL91_FEC_MODE_CL91_SINGLE_LANE_FC 1 27953 #define TX_X4_CONTROL0_TX_CONTROL0_CL91_FEC_MODE_CL91_SINGLE_LANE_BRCM_PROP 2 27954 #define TX_X4_CONTROL0_TX_CONTROL0_CL91_FEC_MODE_CL91_DUAL_LANE_BRCM_PROP 3 27955 #define TX_X4_CONTROL0_TX_CONTROL0_CL91_FEC_MODE_CL91_QUAD_LANE 4 27956 #define TX_X4_CONTROL0_TX_CONTROL0_CL91_FEC_MODE_IEEE_25G_CL91_SINGLE_LANE 5 27957 27958 /* TX_X4_Control0 :: tx_control0 :: t_pma_bitmux_delay [08:07] */ 27959 #define TX_X4_CONTROL0_TX_CONTROL0_T_PMA_BITMUX_DELAY_MASK 0x0180 27960 #define TX_X4_CONTROL0_TX_CONTROL0_T_PMA_BITMUX_DELAY_ALIGN 0 27961 #define TX_X4_CONTROL0_TX_CONTROL0_T_PMA_BITMUX_DELAY_BITS 2 27962 #define TX_X4_CONTROL0_TX_CONTROL0_T_PMA_BITMUX_DELAY_SHIFT 7 27963 27964 /* TX_X4_Control0 :: tx_control0 :: t_pma_watermark [06:03] */ 27965 #define TX_X4_CONTROL0_TX_CONTROL0_T_PMA_WATERMARK_MASK 0x0078 27966 #define TX_X4_CONTROL0_TX_CONTROL0_T_PMA_WATERMARK_ALIGN 0 27967 #define TX_X4_CONTROL0_TX_CONTROL0_T_PMA_WATERMARK_BITS 4 27968 #define TX_X4_CONTROL0_TX_CONTROL0_T_PMA_WATERMARK_SHIFT 3 27969 27970 /* TX_X4_Control0 :: tx_control0 :: t_pma_cl91_mux_sel [02:02] */ 27971 #define TX_X4_CONTROL0_TX_CONTROL0_T_PMA_CL91_MUX_SEL_MASK 0x0004 27972 #define TX_X4_CONTROL0_TX_CONTROL0_T_PMA_CL91_MUX_SEL_ALIGN 0 27973 #define TX_X4_CONTROL0_TX_CONTROL0_T_PMA_CL91_MUX_SEL_BITS 1 27974 #define TX_X4_CONTROL0_TX_CONTROL0_T_PMA_CL91_MUX_SEL_SHIFT 2 27975 27976 /* TX_X4_Control0 :: tx_control0 :: five_bit_xor_en [01:01] */ 27977 #define TX_X4_CONTROL0_TX_CONTROL0_FIVE_BIT_XOR_EN_MASK 0x0002 27978 #define TX_X4_CONTROL0_TX_CONTROL0_FIVE_BIT_XOR_EN_ALIGN 0 27979 #define TX_X4_CONTROL0_TX_CONTROL0_FIVE_BIT_XOR_EN_BITS 1 27980 #define TX_X4_CONTROL0_TX_CONTROL0_FIVE_BIT_XOR_EN_SHIFT 1 27981 27982 /* TX_X4_Control0 :: tx_control0 :: cl91_cw_scramble [00:00] */ 27983 #define TX_X4_CONTROL0_TX_CONTROL0_CL91_CW_SCRAMBLE_MASK 0x0001 27984 #define TX_X4_CONTROL0_TX_CONTROL0_CL91_CW_SCRAMBLE_ALIGN 0 27985 #define TX_X4_CONTROL0_TX_CONTROL0_CL91_CW_SCRAMBLE_BITS 1 27986 #define TX_X4_CONTROL0_TX_CONTROL0_CL91_CW_SCRAMBLE_SHIFT 0 27987 27988 27989 /**************************************************************************** 27990 * TSC_WC4_TSC_USER4_TX_X4_Status0 27991 */ 27992 /**************************************************************************** 27993 * TX_X4_Status0 :: encode_status_0 27994 */ 27995 /* TX_X4_Status0 :: encode_status_0 :: reserved0 [15:08] */ 27996 #define TX_X4_STATUS0_ENCODE_STATUS_0_RESERVED0_MASK 0xff00 27997 #define TX_X4_STATUS0_ENCODE_STATUS_0_RESERVED0_ALIGN 0 27998 #define TX_X4_STATUS0_ENCODE_STATUS_0_RESERVED0_BITS 8 27999 #define TX_X4_STATUS0_ENCODE_STATUS_0_RESERVED0_SHIFT 8 28000 28001 /* TX_X4_Status0 :: encode_status_0 :: cl82_idle_deletion_underflow [07:07] */ 28002 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL82_IDLE_DELETION_UNDERFLOW_MASK 0x0080 28003 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL82_IDLE_DELETION_UNDERFLOW_ALIGN 0 28004 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL82_IDLE_DELETION_UNDERFLOW_BITS 1 28005 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL82_IDLE_DELETION_UNDERFLOW_SHIFT 7 28006 28007 /* TX_X4_Status0 :: encode_status_0 :: cl49_t_type_coded [06:03] */ 28008 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_T_TYPE_CODED_MASK 0x0078 28009 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_T_TYPE_CODED_ALIGN 0 28010 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_T_TYPE_CODED_BITS 4 28011 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_T_TYPE_CODED_SHIFT 3 28012 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_T_TYPE_CODED_BAD_T_TYPE 15 28013 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_T_TYPE_CODED_T_TYPE_B0 11 28014 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_T_TYPE_CODED_T_TYPE_OB 10 28015 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_T_TYPE_CODED_T_TYPE_B1 9 28016 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_T_TYPE_CODED_T_TYPE_DB 8 28017 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_T_TYPE_CODED_T_TYPE_FC 7 28018 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_T_TYPE_CODED_T_TYPE_TB 6 28019 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_T_TYPE_CODED_T_TYPE_LI 5 28020 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_T_TYPE_CODED_T_TYPE_C 4 28021 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_T_TYPE_CODED_T_TYPE_S 3 28022 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_T_TYPE_CODED_T_TYPE_T 2 28023 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_T_TYPE_CODED_T_TYPE_D 1 28024 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_T_TYPE_CODED_T_TYPE_E 0 28025 28026 /* TX_X4_Status0 :: encode_status_0 :: cl49_txsm_state [02:00] */ 28027 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_TXSM_STATE_MASK 0x0007 28028 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_TXSM_STATE_ALIGN 0 28029 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_TXSM_STATE_BITS 3 28030 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_TXSM_STATE_SHIFT 0 28031 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_TXSM_STATE_TX_HIG_END 7 28032 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_TXSM_STATE_TX_HIG_START 6 28033 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_TXSM_STATE_TX_LI 5 28034 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_TXSM_STATE_TX_E 4 28035 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_TXSM_STATE_TX_T 3 28036 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_TXSM_STATE_TX_D 2 28037 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_TXSM_STATE_TX_C 1 28038 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_TXSM_STATE_TX_INIT 0 28039 28040 28041 /**************************************************************************** 28042 * TX_X4_Status0 :: encode_status_1 28043 */ 28044 /* TX_X4_Status0 :: encode_status_1 :: reserved0 [15:09] */ 28045 #define TX_X4_STATUS0_ENCODE_STATUS_1_RESERVED0_MASK 0xfe00 28046 #define TX_X4_STATUS0_ENCODE_STATUS_1_RESERVED0_ALIGN 0 28047 #define TX_X4_STATUS0_ENCODE_STATUS_1_RESERVED0_BITS 7 28048 #define TX_X4_STATUS0_ENCODE_STATUS_1_RESERVED0_SHIFT 9 28049 28050 /* TX_X4_Status0 :: encode_status_1 :: cl49_tx_fault_det [08:08] */ 28051 #define TX_X4_STATUS0_ENCODE_STATUS_1_CL49_TX_FAULT_DET_MASK 0x0100 28052 #define TX_X4_STATUS0_ENCODE_STATUS_1_CL49_TX_FAULT_DET_ALIGN 0 28053 #define TX_X4_STATUS0_ENCODE_STATUS_1_CL49_TX_FAULT_DET_BITS 1 28054 #define TX_X4_STATUS0_ENCODE_STATUS_1_CL49_TX_FAULT_DET_SHIFT 8 28055 28056 /* TX_X4_Status0 :: encode_status_1 :: cl49_ltxsm_state [07:00] */ 28057 #define TX_X4_STATUS0_ENCODE_STATUS_1_CL49_LTXSM_STATE_MASK 0x00ff 28058 #define TX_X4_STATUS0_ENCODE_STATUS_1_CL49_LTXSM_STATE_ALIGN 0 28059 #define TX_X4_STATUS0_ENCODE_STATUS_1_CL49_LTXSM_STATE_BITS 8 28060 #define TX_X4_STATUS0_ENCODE_STATUS_1_CL49_LTXSM_STATE_SHIFT 0 28061 #define TX_X4_STATUS0_ENCODE_STATUS_1_CL49_LTXSM_STATE_TX_HIG_END 128 28062 #define TX_X4_STATUS0_ENCODE_STATUS_1_CL49_LTXSM_STATE_TX_HIG_START 64 28063 #define TX_X4_STATUS0_ENCODE_STATUS_1_CL49_LTXSM_STATE_TX_LI 32 28064 #define TX_X4_STATUS0_ENCODE_STATUS_1_CL49_LTXSM_STATE_TX_E 16 28065 #define TX_X4_STATUS0_ENCODE_STATUS_1_CL49_LTXSM_STATE_TX_T 8 28066 #define TX_X4_STATUS0_ENCODE_STATUS_1_CL49_LTXSM_STATE_TX_D 4 28067 #define TX_X4_STATUS0_ENCODE_STATUS_1_CL49_LTXSM_STATE_TX_C 2 28068 #define TX_X4_STATUS0_ENCODE_STATUS_1_CL49_LTXSM_STATE_TX_INIT 1 28069 28070 28071 /**************************************************************************** 28072 * TX_X4_Status0 :: pcs_status_live 28073 */ 28074 /* TX_X4_Status0 :: pcs_status_live :: reserved0 [15:04] */ 28075 #define TX_X4_STATUS0_PCS_STATUS_LIVE_RESERVED0_MASK 0xfff0 28076 #define TX_X4_STATUS0_PCS_STATUS_LIVE_RESERVED0_ALIGN 0 28077 #define TX_X4_STATUS0_PCS_STATUS_LIVE_RESERVED0_BITS 12 28078 #define TX_X4_STATUS0_PCS_STATUS_LIVE_RESERVED0_SHIFT 4 28079 28080 /* TX_X4_Status0 :: pcs_status_live :: tx_LOCAL_FAULT [03:03] */ 28081 #define TX_X4_STATUS0_PCS_STATUS_LIVE_TX_LOCAL_FAULT_MASK 0x0008 28082 #define TX_X4_STATUS0_PCS_STATUS_LIVE_TX_LOCAL_FAULT_ALIGN 0 28083 #define TX_X4_STATUS0_PCS_STATUS_LIVE_TX_LOCAL_FAULT_BITS 1 28084 #define TX_X4_STATUS0_PCS_STATUS_LIVE_TX_LOCAL_FAULT_SHIFT 3 28085 28086 /* TX_X4_Status0 :: pcs_status_live :: tx_REMOTE_FAULT [02:02] */ 28087 #define TX_X4_STATUS0_PCS_STATUS_LIVE_TX_REMOTE_FAULT_MASK 0x0004 28088 #define TX_X4_STATUS0_PCS_STATUS_LIVE_TX_REMOTE_FAULT_ALIGN 0 28089 #define TX_X4_STATUS0_PCS_STATUS_LIVE_TX_REMOTE_FAULT_BITS 1 28090 #define TX_X4_STATUS0_PCS_STATUS_LIVE_TX_REMOTE_FAULT_SHIFT 2 28091 28092 /* TX_X4_Status0 :: pcs_status_live :: tx_LINK_INTERRUPT [01:01] */ 28093 #define TX_X4_STATUS0_PCS_STATUS_LIVE_TX_LINK_INTERRUPT_MASK 0x0002 28094 #define TX_X4_STATUS0_PCS_STATUS_LIVE_TX_LINK_INTERRUPT_ALIGN 0 28095 #define TX_X4_STATUS0_PCS_STATUS_LIVE_TX_LINK_INTERRUPT_BITS 1 28096 #define TX_X4_STATUS0_PCS_STATUS_LIVE_TX_LINK_INTERRUPT_SHIFT 1 28097 28098 /* TX_X4_Status0 :: pcs_status_live :: tx_LPI_RECEIVED [00:00] */ 28099 #define TX_X4_STATUS0_PCS_STATUS_LIVE_TX_LPI_RECEIVED_MASK 0x0001 28100 #define TX_X4_STATUS0_PCS_STATUS_LIVE_TX_LPI_RECEIVED_ALIGN 0 28101 #define TX_X4_STATUS0_PCS_STATUS_LIVE_TX_LPI_RECEIVED_BITS 1 28102 #define TX_X4_STATUS0_PCS_STATUS_LIVE_TX_LPI_RECEIVED_SHIFT 0 28103 28104 28105 /**************************************************************************** 28106 * TX_X4_Status0 :: pcs_status_latched 28107 */ 28108 /* TX_X4_Status0 :: pcs_status_latched :: reserved0 [15:04] */ 28109 #define TX_X4_STATUS0_PCS_STATUS_LATCHED_RESERVED0_MASK 0xfff0 28110 #define TX_X4_STATUS0_PCS_STATUS_LATCHED_RESERVED0_ALIGN 0 28111 #define TX_X4_STATUS0_PCS_STATUS_LATCHED_RESERVED0_BITS 12 28112 #define TX_X4_STATUS0_PCS_STATUS_LATCHED_RESERVED0_SHIFT 4 28113 28114 /* TX_X4_Status0 :: pcs_status_latched :: LINK_INTERRUPT_LH [03:03] */ 28115 #define TX_X4_STATUS0_PCS_STATUS_LATCHED_LINK_INTERRUPT_LH_MASK 0x0008 28116 #define TX_X4_STATUS0_PCS_STATUS_LATCHED_LINK_INTERRUPT_LH_ALIGN 0 28117 #define TX_X4_STATUS0_PCS_STATUS_LATCHED_LINK_INTERRUPT_LH_BITS 1 28118 #define TX_X4_STATUS0_PCS_STATUS_LATCHED_LINK_INTERRUPT_LH_SHIFT 3 28119 28120 /* TX_X4_Status0 :: pcs_status_latched :: LOCAL_FAULT_LH [02:02] */ 28121 #define TX_X4_STATUS0_PCS_STATUS_LATCHED_LOCAL_FAULT_LH_MASK 0x0004 28122 #define TX_X4_STATUS0_PCS_STATUS_LATCHED_LOCAL_FAULT_LH_ALIGN 0 28123 #define TX_X4_STATUS0_PCS_STATUS_LATCHED_LOCAL_FAULT_LH_BITS 1 28124 #define TX_X4_STATUS0_PCS_STATUS_LATCHED_LOCAL_FAULT_LH_SHIFT 2 28125 28126 /* TX_X4_Status0 :: pcs_status_latched :: REMOTE_FAULT_LH [01:01] */ 28127 #define TX_X4_STATUS0_PCS_STATUS_LATCHED_REMOTE_FAULT_LH_MASK 0x0002 28128 #define TX_X4_STATUS0_PCS_STATUS_LATCHED_REMOTE_FAULT_LH_ALIGN 0 28129 #define TX_X4_STATUS0_PCS_STATUS_LATCHED_REMOTE_FAULT_LH_BITS 1 28130 #define TX_X4_STATUS0_PCS_STATUS_LATCHED_REMOTE_FAULT_LH_SHIFT 1 28131 28132 /* TX_X4_Status0 :: pcs_status_latched :: LPI_RECEIVED_LH [00:00] */ 28133 #define TX_X4_STATUS0_PCS_STATUS_LATCHED_LPI_RECEIVED_LH_MASK 0x0001 28134 #define TX_X4_STATUS0_PCS_STATUS_LATCHED_LPI_RECEIVED_LH_ALIGN 0 28135 #define TX_X4_STATUS0_PCS_STATUS_LATCHED_LPI_RECEIVED_LH_BITS 1 28136 #define TX_X4_STATUS0_PCS_STATUS_LATCHED_LPI_RECEIVED_LH_SHIFT 0 28137 28138 28139 /**************************************************************************** 28140 * TX_X4_Status0 :: pma_status 28141 */ 28142 /* TX_X4_Status0 :: pma_status :: reserved0 [15:04] */ 28143 #define TX_X4_STATUS0_PMA_STATUS_RESERVED0_MASK 0xfff0 28144 #define TX_X4_STATUS0_PMA_STATUS_RESERVED0_ALIGN 0 28145 #define TX_X4_STATUS0_PMA_STATUS_RESERVED0_BITS 12 28146 #define TX_X4_STATUS0_PMA_STATUS_RESERVED0_SHIFT 4 28147 28148 /* TX_X4_Status0 :: pma_status :: t_tc_out_underflow [03:03] */ 28149 #define TX_X4_STATUS0_PMA_STATUS_T_TC_OUT_UNDERFLOW_MASK 0x0008 28150 #define TX_X4_STATUS0_PMA_STATUS_T_TC_OUT_UNDERFLOW_ALIGN 0 28151 #define TX_X4_STATUS0_PMA_STATUS_T_TC_OUT_UNDERFLOW_BITS 1 28152 #define TX_X4_STATUS0_PMA_STATUS_T_TC_OUT_UNDERFLOW_SHIFT 3 28153 28154 /* TX_X4_Status0 :: pma_status :: t_tc_out_overflow [02:02] */ 28155 #define TX_X4_STATUS0_PMA_STATUS_T_TC_OUT_OVERFLOW_MASK 0x0004 28156 #define TX_X4_STATUS0_PMA_STATUS_T_TC_OUT_OVERFLOW_ALIGN 0 28157 #define TX_X4_STATUS0_PMA_STATUS_T_TC_OUT_OVERFLOW_BITS 1 28158 #define TX_X4_STATUS0_PMA_STATUS_T_TC_OUT_OVERFLOW_SHIFT 2 28159 28160 /* TX_X4_Status0 :: pma_status :: reserved1 [01:00] */ 28161 #define TX_X4_STATUS0_PMA_STATUS_RESERVED1_MASK 0x0003 28162 #define TX_X4_STATUS0_PMA_STATUS_RESERVED1_ALIGN 0 28163 #define TX_X4_STATUS0_PMA_STATUS_RESERVED1_BITS 2 28164 #define TX_X4_STATUS0_PMA_STATUS_RESERVED1_SHIFT 0 28165 28166 28167 /**************************************************************************** 28168 * TSC_WC4_TSC_USER4_RX_X4_Control0 28169 */ 28170 /**************************************************************************** 28171 * RX_X4_Control0 :: pcs_control_0 28172 */ 28173 /* RX_X4_Control0 :: pcs_control_0 :: descr_mode [15:14] */ 28174 #define RX_X4_CONTROL0_PCS_CONTROL_0_DESCR_MODE_MASK 0xc000 28175 #define RX_X4_CONTROL0_PCS_CONTROL_0_DESCR_MODE_ALIGN 0 28176 #define RX_X4_CONTROL0_PCS_CONTROL_0_DESCR_MODE_BITS 2 28177 #define RX_X4_CONTROL0_PCS_CONTROL_0_DESCR_MODE_SHIFT 14 28178 #define RX_X4_CONTROL0_PCS_CONTROL_0_DESCR_MODE_R_DESCR_MODE_BYPASS 0 28179 #define RX_X4_CONTROL0_PCS_CONTROL_0_DESCR_MODE_R_DESCR_MODE_CL49 1 28180 #define RX_X4_CONTROL0_PCS_CONTROL_0_DESCR_MODE_R_DESCR_MODE_CL82 2 28181 28182 /* RX_X4_Control0 :: pcs_control_0 :: dec_tl_mode [13:12] */ 28183 #define RX_X4_CONTROL0_PCS_CONTROL_0_DEC_TL_MODE_MASK 0x3000 28184 #define RX_X4_CONTROL0_PCS_CONTROL_0_DEC_TL_MODE_ALIGN 0 28185 #define RX_X4_CONTROL0_PCS_CONTROL_0_DEC_TL_MODE_BITS 2 28186 #define RX_X4_CONTROL0_PCS_CONTROL_0_DEC_TL_MODE_SHIFT 12 28187 #define RX_X4_CONTROL0_PCS_CONTROL_0_DEC_TL_MODE_R_DEC_TL_MODE_BYPASS 0 28188 #define RX_X4_CONTROL0_PCS_CONTROL_0_DEC_TL_MODE_R_DEC_TL_MODE_CL49 1 28189 #define RX_X4_CONTROL0_PCS_CONTROL_0_DEC_TL_MODE_R_DEC_TL_MODE_CL82 2 28190 28191 /* RX_X4_Control0 :: pcs_control_0 :: deskew_mode [11:08] */ 28192 #define RX_X4_CONTROL0_PCS_CONTROL_0_DESKEW_MODE_MASK 0x0f00 28193 #define RX_X4_CONTROL0_PCS_CONTROL_0_DESKEW_MODE_ALIGN 0 28194 #define RX_X4_CONTROL0_PCS_CONTROL_0_DESKEW_MODE_BITS 4 28195 #define RX_X4_CONTROL0_PCS_CONTROL_0_DESKEW_MODE_SHIFT 8 28196 #define RX_X4_CONTROL0_PCS_CONTROL_0_DESKEW_MODE_R_DESKEW_MODE_BYPASS 0 28197 #define RX_X4_CONTROL0_PCS_CONTROL_0_DESKEW_MODE_R_DESKEW_MODE_20G 1 28198 #define RX_X4_CONTROL0_PCS_CONTROL_0_DESKEW_MODE_R_DESKEW_MODE_40G_4_LANE 2 28199 #define RX_X4_CONTROL0_PCS_CONTROL_0_DESKEW_MODE_R_DESKEW_MODE_40G_2_LANE 3 28200 #define RX_X4_CONTROL0_PCS_CONTROL_0_DESKEW_MODE_R_DESKEW_MODE_100G 4 28201 #define RX_X4_CONTROL0_PCS_CONTROL_0_DESKEW_MODE_R_DESKEW_MODE_CL49 5 28202 #define RX_X4_CONTROL0_PCS_CONTROL_0_DESKEW_MODE_R_DESKEW_MODE_CL91_QUAD 6 28203 #define RX_X4_CONTROL0_PCS_CONTROL_0_DESKEW_MODE_R_DESKEW_MODE_CL91_SINGLE_BRCM 7 28204 #define RX_X4_CONTROL0_PCS_CONTROL_0_DESKEW_MODE_R_DESKEW_MODE_CL91_DUAL_BRCM 8 28205 #define RX_X4_CONTROL0_PCS_CONTROL_0_DESKEW_MODE_R_DESKEW_MODE_CL91_FC 9 28206 28207 /* RX_X4_Control0 :: pcs_control_0 :: dec_fsm_mode [07:06] */ 28208 #define RX_X4_CONTROL0_PCS_CONTROL_0_DEC_FSM_MODE_MASK 0x00c0 28209 #define RX_X4_CONTROL0_PCS_CONTROL_0_DEC_FSM_MODE_ALIGN 0 28210 #define RX_X4_CONTROL0_PCS_CONTROL_0_DEC_FSM_MODE_BITS 2 28211 #define RX_X4_CONTROL0_PCS_CONTROL_0_DEC_FSM_MODE_SHIFT 6 28212 #define RX_X4_CONTROL0_PCS_CONTROL_0_DEC_FSM_MODE_R_DEC_FSM_MODE_BYPASS 0 28213 #define RX_X4_CONTROL0_PCS_CONTROL_0_DEC_FSM_MODE_R_DEC_FSM_MODE_CL49 1 28214 #define RX_X4_CONTROL0_PCS_CONTROL_0_DEC_FSM_MODE_R_DEC_FSM_MODE_CL82 2 28215 28216 /* RX_X4_Control0 :: pcs_control_0 :: block_non_fc_blk_types [05:05] */ 28217 #define RX_X4_CONTROL0_PCS_CONTROL_0_BLOCK_NON_FC_BLK_TYPES_MASK 0x0020 28218 #define RX_X4_CONTROL0_PCS_CONTROL_0_BLOCK_NON_FC_BLK_TYPES_ALIGN 0 28219 #define RX_X4_CONTROL0_PCS_CONTROL_0_BLOCK_NON_FC_BLK_TYPES_BITS 1 28220 #define RX_X4_CONTROL0_PCS_CONTROL_0_BLOCK_NON_FC_BLK_TYPES_SHIFT 5 28221 28222 /* RX_X4_Control0 :: pcs_control_0 :: cl91_fec_mode [04:02] */ 28223 #define RX_X4_CONTROL0_PCS_CONTROL_0_CL91_FEC_MODE_MASK 0x001c 28224 #define RX_X4_CONTROL0_PCS_CONTROL_0_CL91_FEC_MODE_ALIGN 0 28225 #define RX_X4_CONTROL0_PCS_CONTROL_0_CL91_FEC_MODE_BITS 3 28226 #define RX_X4_CONTROL0_PCS_CONTROL_0_CL91_FEC_MODE_SHIFT 2 28227 #define RX_X4_CONTROL0_PCS_CONTROL_0_CL91_FEC_MODE_NO_CL91_FEC 0 28228 #define RX_X4_CONTROL0_PCS_CONTROL_0_CL91_FEC_MODE_CL91_SINGLE_LANE_FC 1 28229 #define RX_X4_CONTROL0_PCS_CONTROL_0_CL91_FEC_MODE_CL91_SINGLE_LANE_BRCM_PROP 2 28230 #define RX_X4_CONTROL0_PCS_CONTROL_0_CL91_FEC_MODE_CL91_DUAL_LANE_BRCM_PROP 3 28231 #define RX_X4_CONTROL0_PCS_CONTROL_0_CL91_FEC_MODE_CL91_QUAD_LANE 4 28232 #define RX_X4_CONTROL0_PCS_CONTROL_0_CL91_FEC_MODE_IEEE_25G_CL91_SINGLE_LANE 5 28233 28234 /* RX_X4_Control0 :: pcs_control_0 :: fec_enable [01:01] */ 28235 #define RX_X4_CONTROL0_PCS_CONTROL_0_FEC_ENABLE_MASK 0x0002 28236 #define RX_X4_CONTROL0_PCS_CONTROL_0_FEC_ENABLE_ALIGN 0 28237 #define RX_X4_CONTROL0_PCS_CONTROL_0_FEC_ENABLE_BITS 1 28238 #define RX_X4_CONTROL0_PCS_CONTROL_0_FEC_ENABLE_SHIFT 1 28239 28240 /* RX_X4_Control0 :: pcs_control_0 :: LPI_ENABLE [00:00] */ 28241 #define RX_X4_CONTROL0_PCS_CONTROL_0_LPI_ENABLE_MASK 0x0001 28242 #define RX_X4_CONTROL0_PCS_CONTROL_0_LPI_ENABLE_ALIGN 0 28243 #define RX_X4_CONTROL0_PCS_CONTROL_0_LPI_ENABLE_BITS 1 28244 #define RX_X4_CONTROL0_PCS_CONTROL_0_LPI_ENABLE_SHIFT 0 28245 28246 28247 /**************************************************************************** 28248 * RX_X4_Control0 :: cl91_threshold 28249 */ 28250 /* RX_X4_Control0 :: cl91_threshold :: reserved0 [15:13] */ 28251 #define RX_X4_CONTROL0_CL91_THRESHOLD_RESERVED0_MASK 0xe000 28252 #define RX_X4_CONTROL0_CL91_THRESHOLD_RESERVED0_ALIGN 0 28253 #define RX_X4_CONTROL0_CL91_THRESHOLD_RESERVED0_BITS 3 28254 #define RX_X4_CONTROL0_CL91_THRESHOLD_RESERVED0_SHIFT 13 28255 28256 /* RX_X4_Control0 :: cl91_threshold :: symbol_err_cnt_threshold [12:00] */ 28257 #define RX_X4_CONTROL0_CL91_THRESHOLD_SYMBOL_ERR_CNT_THRESHOLD_MASK 0x1fff 28258 #define RX_X4_CONTROL0_CL91_THRESHOLD_SYMBOL_ERR_CNT_THRESHOLD_ALIGN 0 28259 #define RX_X4_CONTROL0_CL91_THRESHOLD_SYMBOL_ERR_CNT_THRESHOLD_BITS 13 28260 #define RX_X4_CONTROL0_CL91_THRESHOLD_SYMBOL_ERR_CNT_THRESHOLD_SHIFT 0 28261 28262 28263 /**************************************************************************** 28264 * RX_X4_Control0 :: cl91_timer 28265 */ 28266 /* RX_X4_Control0 :: cl91_timer :: reserved0 [15:13] */ 28267 #define RX_X4_CONTROL0_CL91_TIMER_RESERVED0_MASK 0xe000 28268 #define RX_X4_CONTROL0_CL91_TIMER_RESERVED0_ALIGN 0 28269 #define RX_X4_CONTROL0_CL91_TIMER_RESERVED0_BITS 3 28270 #define RX_X4_CONTROL0_CL91_TIMER_RESERVED0_SHIFT 13 28271 28272 /* RX_X4_Control0 :: cl91_timer :: symbol_error_tmr_period [12:00] */ 28273 #define RX_X4_CONTROL0_CL91_TIMER_SYMBOL_ERROR_TMR_PERIOD_MASK 0x1fff 28274 #define RX_X4_CONTROL0_CL91_TIMER_SYMBOL_ERROR_TMR_PERIOD_ALIGN 0 28275 #define RX_X4_CONTROL0_CL91_TIMER_SYMBOL_ERROR_TMR_PERIOD_BITS 13 28276 #define RX_X4_CONTROL0_CL91_TIMER_SYMBOL_ERROR_TMR_PERIOD_SHIFT 0 28277 28278 28279 /**************************************************************************** 28280 * RX_X4_Control0 :: cl91_rx_control_0 28281 */ 28282 /* RX_X4_Control0 :: cl91_rx_control_0 :: reserved0 [15:15] */ 28283 #define RX_X4_CONTROL0_CL91_RX_CONTROL_0_RESERVED0_MASK 0x8000 28284 #define RX_X4_CONTROL0_CL91_RX_CONTROL_0_RESERVED0_ALIGN 0 28285 #define RX_X4_CONTROL0_CL91_RX_CONTROL_0_RESERVED0_BITS 1 28286 #define RX_X4_CONTROL0_CL91_RX_CONTROL_0_RESERVED0_SHIFT 15 28287 28288 /* RX_X4_Control0 :: cl91_rx_control_0 :: fec_byp_ind_en [14:14] */ 28289 #define RX_X4_CONTROL0_CL91_RX_CONTROL_0_FEC_BYP_IND_EN_MASK 0x4000 28290 #define RX_X4_CONTROL0_CL91_RX_CONTROL_0_FEC_BYP_IND_EN_ALIGN 0 28291 #define RX_X4_CONTROL0_CL91_RX_CONTROL_0_FEC_BYP_IND_EN_BITS 1 28292 #define RX_X4_CONTROL0_CL91_RX_CONTROL_0_FEC_BYP_IND_EN_SHIFT 14 28293 28294 /* RX_X4_Control0 :: cl91_rx_control_0 :: fec_byp_corr_en [13:13] */ 28295 #define RX_X4_CONTROL0_CL91_RX_CONTROL_0_FEC_BYP_CORR_EN_MASK 0x2000 28296 #define RX_X4_CONTROL0_CL91_RX_CONTROL_0_FEC_BYP_CORR_EN_ALIGN 0 28297 #define RX_X4_CONTROL0_CL91_RX_CONTROL_0_FEC_BYP_CORR_EN_BITS 1 28298 #define RX_X4_CONTROL0_CL91_RX_CONTROL_0_FEC_BYP_CORR_EN_SHIFT 13 28299 28300 /* RX_X4_Control0 :: cl91_rx_control_0 :: r_tc_out_mode [12:11] */ 28301 #define RX_X4_CONTROL0_CL91_RX_CONTROL_0_R_TC_OUT_MODE_MASK 0x1800 28302 #define RX_X4_CONTROL0_CL91_RX_CONTROL_0_R_TC_OUT_MODE_ALIGN 0 28303 #define RX_X4_CONTROL0_CL91_RX_CONTROL_0_R_TC_OUT_MODE_BITS 2 28304 #define RX_X4_CONTROL0_CL91_RX_CONTROL_0_R_TC_OUT_MODE_SHIFT 11 28305 #define RX_X4_CONTROL0_CL91_RX_CONTROL_0_R_TC_OUT_MODE_R_TC_OUT_MODE_SINGLE 0 28306 #define RX_X4_CONTROL0_CL91_RX_CONTROL_0_R_TC_OUT_MODE_R_TC_OUT_MODE_DUAL 1 28307 #define RX_X4_CONTROL0_CL91_RX_CONTROL_0_R_TC_OUT_MODE_R_TC_OUT_MODE_QUAD 2 28308 28309 /* RX_X4_Control0 :: cl91_rx_control_0 :: five_bit_xor_en [10:10] */ 28310 #define RX_X4_CONTROL0_CL91_RX_CONTROL_0_FIVE_BIT_XOR_EN_MASK 0x0400 28311 #define RX_X4_CONTROL0_CL91_RX_CONTROL_0_FIVE_BIT_XOR_EN_ALIGN 0 28312 #define RX_X4_CONTROL0_CL91_RX_CONTROL_0_FIVE_BIT_XOR_EN_BITS 1 28313 #define RX_X4_CONTROL0_CL91_RX_CONTROL_0_FIVE_BIT_XOR_EN_SHIFT 10 28314 28315 /* RX_X4_Control0 :: cl91_rx_control_0 :: r_tc_mode [09:08] */ 28316 #define RX_X4_CONTROL0_CL91_RX_CONTROL_0_R_TC_MODE_MASK 0x0300 28317 #define RX_X4_CONTROL0_CL91_RX_CONTROL_0_R_TC_MODE_ALIGN 0 28318 #define RX_X4_CONTROL0_CL91_RX_CONTROL_0_R_TC_MODE_BITS 2 28319 #define RX_X4_CONTROL0_CL91_RX_CONTROL_0_R_TC_MODE_SHIFT 8 28320 #define RX_X4_CONTROL0_CL91_RX_CONTROL_0_R_TC_MODE_R_TC_MODE_SINGLE 0 28321 #define RX_X4_CONTROL0_CL91_RX_CONTROL_0_R_TC_MODE_R_TC_MODE_DUAL 1 28322 #define RX_X4_CONTROL0_CL91_RX_CONTROL_0_R_TC_MODE_R_TC_MODE_QUAD 2 28323 28324 /* RX_X4_Control0 :: cl91_rx_control_0 :: r_tc_in_mode [07:07] */ 28325 #define RX_X4_CONTROL0_CL91_RX_CONTROL_0_R_TC_IN_MODE_MASK 0x0080 28326 #define RX_X4_CONTROL0_CL91_RX_CONTROL_0_R_TC_IN_MODE_ALIGN 0 28327 #define RX_X4_CONTROL0_CL91_RX_CONTROL_0_R_TC_IN_MODE_BITS 1 28328 #define RX_X4_CONTROL0_CL91_RX_CONTROL_0_R_TC_IN_MODE_SHIFT 7 28329 28330 /* RX_X4_Control0 :: cl91_rx_control_0 :: cl91_cw_scramble [06:06] */ 28331 #define RX_X4_CONTROL0_CL91_RX_CONTROL_0_CL91_CW_SCRAMBLE_MASK 0x0040 28332 #define RX_X4_CONTROL0_CL91_RX_CONTROL_0_CL91_CW_SCRAMBLE_ALIGN 0 28333 #define RX_X4_CONTROL0_CL91_RX_CONTROL_0_CL91_CW_SCRAMBLE_BITS 1 28334 #define RX_X4_CONTROL0_CL91_RX_CONTROL_0_CL91_CW_SCRAMBLE_SHIFT 6 28335 28336 /* RX_X4_Control0 :: cl91_rx_control_0 :: r_merge_mode [05:03] */ 28337 #define RX_X4_CONTROL0_CL91_RX_CONTROL_0_R_MERGE_MODE_MASK 0x0038 28338 #define RX_X4_CONTROL0_CL91_RX_CONTROL_0_R_MERGE_MODE_ALIGN 0 28339 #define RX_X4_CONTROL0_CL91_RX_CONTROL_0_R_MERGE_MODE_BITS 3 28340 #define RX_X4_CONTROL0_CL91_RX_CONTROL_0_R_MERGE_MODE_SHIFT 3 28341 #define RX_X4_CONTROL0_CL91_RX_CONTROL_0_R_MERGE_MODE_R_MERGE_MODE_BYPASS 0 28342 #define RX_X4_CONTROL0_CL91_RX_CONTROL_0_R_MERGE_MODE_R_MERGE_MODE_CL91_FC 1 28343 #define RX_X4_CONTROL0_CL91_RX_CONTROL_0_R_MERGE_MODE_R_MERGE_MODE_CL91_SINGLE_LANE 2 28344 #define RX_X4_CONTROL0_CL91_RX_CONTROL_0_R_MERGE_MODE_R_MERGE_MODE_CL91_DUAL_LANE 3 28345 #define RX_X4_CONTROL0_CL91_RX_CONTROL_0_R_MERGE_MODE_R_MERGE_MODE_CL91_QUAD_LANE 4 28346 28347 /* RX_X4_Control0 :: cl91_rx_control_0 :: cl91_blksync_mode [02:00] */ 28348 #define RX_X4_CONTROL0_CL91_RX_CONTROL_0_CL91_BLKSYNC_MODE_MASK 0x0007 28349 #define RX_X4_CONTROL0_CL91_RX_CONTROL_0_CL91_BLKSYNC_MODE_ALIGN 0 28350 #define RX_X4_CONTROL0_CL91_RX_CONTROL_0_CL91_BLKSYNC_MODE_BITS 3 28351 #define RX_X4_CONTROL0_CL91_RX_CONTROL_0_CL91_BLKSYNC_MODE_SHIFT 0 28352 #define RX_X4_CONTROL0_CL91_RX_CONTROL_0_CL91_BLKSYNC_MODE_R_BLKSYNC_NO_CL91_FEC 0 28353 #define RX_X4_CONTROL0_CL91_RX_CONTROL_0_CL91_BLKSYNC_MODE_R_BLKSYNC_CL91_QUAD_LANE_FEC 1 28354 #define RX_X4_CONTROL0_CL91_RX_CONTROL_0_CL91_BLKSYNC_MODE_R_BLKSYNC_CL91_DUAL_LANE_FEC 2 28355 #define RX_X4_CONTROL0_CL91_RX_CONTROL_0_CL91_BLKSYNC_MODE_R_BLKSYNC_CL91_SINGLE_LANE_FEC 3 28356 #define RX_X4_CONTROL0_CL91_RX_CONTROL_0_CL91_BLKSYNC_MODE_R_BLKSYNC_CL91_FC_FEC 4 28357 28358 28359 /**************************************************************************** 28360 * RX_X4_Control0 :: decode_control_0 28361 */ 28362 /* RX_X4_Control0 :: decode_control_0 :: bypass_cl49rxsm [15:15] */ 28363 #define RX_X4_CONTROL0_DECODE_CONTROL_0_BYPASS_CL49RXSM_MASK 0x8000 28364 #define RX_X4_CONTROL0_DECODE_CONTROL_0_BYPASS_CL49RXSM_ALIGN 0 28365 #define RX_X4_CONTROL0_DECODE_CONTROL_0_BYPASS_CL49RXSM_BITS 1 28366 #define RX_X4_CONTROL0_DECODE_CONTROL_0_BYPASS_CL49RXSM_SHIFT 15 28367 28368 /* RX_X4_Control0 :: decode_control_0 :: r_test_mode_cfg [14:14] */ 28369 #define RX_X4_CONTROL0_DECODE_CONTROL_0_R_TEST_MODE_CFG_MASK 0x4000 28370 #define RX_X4_CONTROL0_DECODE_CONTROL_0_R_TEST_MODE_CFG_ALIGN 0 28371 #define RX_X4_CONTROL0_DECODE_CONTROL_0_R_TEST_MODE_CFG_BITS 1 28372 #define RX_X4_CONTROL0_DECODE_CONTROL_0_R_TEST_MODE_CFG_SHIFT 14 28373 28374 /* RX_X4_Control0 :: decode_control_0 :: HG2_MESSAGE_INVALID_CODE_ENABLE [13:13] */ 28375 #define RX_X4_CONTROL0_DECODE_CONTROL_0_HG2_MESSAGE_INVALID_CODE_ENABLE_MASK 0x2000 28376 #define RX_X4_CONTROL0_DECODE_CONTROL_0_HG2_MESSAGE_INVALID_CODE_ENABLE_ALIGN 0 28377 #define RX_X4_CONTROL0_DECODE_CONTROL_0_HG2_MESSAGE_INVALID_CODE_ENABLE_BITS 1 28378 #define RX_X4_CONTROL0_DECODE_CONTROL_0_HG2_MESSAGE_INVALID_CODE_ENABLE_SHIFT 13 28379 28380 /* RX_X4_Control0 :: decode_control_0 :: HG2_ENABLE [12:12] */ 28381 #define RX_X4_CONTROL0_DECODE_CONTROL_0_HG2_ENABLE_MASK 0x1000 28382 #define RX_X4_CONTROL0_DECODE_CONTROL_0_HG2_ENABLE_ALIGN 0 28383 #define RX_X4_CONTROL0_DECODE_CONTROL_0_HG2_ENABLE_BITS 1 28384 #define RX_X4_CONTROL0_DECODE_CONTROL_0_HG2_ENABLE_SHIFT 12 28385 28386 /* RX_X4_Control0 :: decode_control_0 :: reserved0 [11:10] */ 28387 #define RX_X4_CONTROL0_DECODE_CONTROL_0_RESERVED0_MASK 0x0c00 28388 #define RX_X4_CONTROL0_DECODE_CONTROL_0_RESERVED0_ALIGN 0 28389 #define RX_X4_CONTROL0_DECODE_CONTROL_0_RESERVED0_BITS 2 28390 #define RX_X4_CONTROL0_DECODE_CONTROL_0_RESERVED0_SHIFT 10 28391 28392 /* RX_X4_Control0 :: decode_control_0 :: HG2_CODEC [09:09] */ 28393 #define RX_X4_CONTROL0_DECODE_CONTROL_0_HG2_CODEC_MASK 0x0200 28394 #define RX_X4_CONTROL0_DECODE_CONTROL_0_HG2_CODEC_ALIGN 0 28395 #define RX_X4_CONTROL0_DECODE_CONTROL_0_HG2_CODEC_BITS 1 28396 #define RX_X4_CONTROL0_DECODE_CONTROL_0_HG2_CODEC_SHIFT 9 28397 28398 /* RX_X4_Control0 :: decode_control_0 :: disable_cl49_bermon [08:08] */ 28399 #define RX_X4_CONTROL0_DECODE_CONTROL_0_DISABLE_CL49_BERMON_MASK 0x0100 28400 #define RX_X4_CONTROL0_DECODE_CONTROL_0_DISABLE_CL49_BERMON_ALIGN 0 28401 #define RX_X4_CONTROL0_DECODE_CONTROL_0_DISABLE_CL49_BERMON_BITS 1 28402 #define RX_X4_CONTROL0_DECODE_CONTROL_0_DISABLE_CL49_BERMON_SHIFT 8 28403 28404 /* RX_X4_Control0 :: decode_control_0 :: dis_scrambler [07:07] */ 28405 #define RX_X4_CONTROL0_DECODE_CONTROL_0_DIS_SCRAMBLER_MASK 0x0080 28406 #define RX_X4_CONTROL0_DECODE_CONTROL_0_DIS_SCRAMBLER_ALIGN 0 28407 #define RX_X4_CONTROL0_DECODE_CONTROL_0_DIS_SCRAMBLER_BITS 1 28408 #define RX_X4_CONTROL0_DECODE_CONTROL_0_DIS_SCRAMBLER_SHIFT 7 28409 28410 /* RX_X4_Control0 :: decode_control_0 :: cl49_rx_li_enable [06:06] */ 28411 #define RX_X4_CONTROL0_DECODE_CONTROL_0_CL49_RX_LI_ENABLE_MASK 0x0040 28412 #define RX_X4_CONTROL0_DECODE_CONTROL_0_CL49_RX_LI_ENABLE_ALIGN 0 28413 #define RX_X4_CONTROL0_DECODE_CONTROL_0_CL49_RX_LI_ENABLE_BITS 1 28414 #define RX_X4_CONTROL0_DECODE_CONTROL_0_CL49_RX_LI_ENABLE_SHIFT 6 28415 28416 /* RX_X4_Control0 :: decode_control_0 :: cl49_rx_lf_enable [05:05] */ 28417 #define RX_X4_CONTROL0_DECODE_CONTROL_0_CL49_RX_LF_ENABLE_MASK 0x0020 28418 #define RX_X4_CONTROL0_DECODE_CONTROL_0_CL49_RX_LF_ENABLE_ALIGN 0 28419 #define RX_X4_CONTROL0_DECODE_CONTROL_0_CL49_RX_LF_ENABLE_BITS 1 28420 #define RX_X4_CONTROL0_DECODE_CONTROL_0_CL49_RX_LF_ENABLE_SHIFT 5 28421 28422 /* RX_X4_Control0 :: decode_control_0 :: cl49_rx_rf_enable [04:04] */ 28423 #define RX_X4_CONTROL0_DECODE_CONTROL_0_CL49_RX_RF_ENABLE_MASK 0x0010 28424 #define RX_X4_CONTROL0_DECODE_CONTROL_0_CL49_RX_RF_ENABLE_ALIGN 0 28425 #define RX_X4_CONTROL0_DECODE_CONTROL_0_CL49_RX_RF_ENABLE_BITS 1 28426 #define RX_X4_CONTROL0_DECODE_CONTROL_0_CL49_RX_RF_ENABLE_SHIFT 4 28427 28428 /* RX_X4_Control0 :: decode_control_0 :: reserved1 [03:00] */ 28429 #define RX_X4_CONTROL0_DECODE_CONTROL_0_RESERVED1_MASK 0x000f 28430 #define RX_X4_CONTROL0_DECODE_CONTROL_0_RESERVED1_ALIGN 0 28431 #define RX_X4_CONTROL0_DECODE_CONTROL_0_RESERVED1_BITS 4 28432 #define RX_X4_CONTROL0_DECODE_CONTROL_0_RESERVED1_SHIFT 0 28433 28434 28435 /**************************************************************************** 28436 * RX_X4_Control0 :: blksync_config 28437 */ 28438 /* RX_X4_Control0 :: blksync_config :: reserved0 [15:07] */ 28439 #define RX_X4_CONTROL0_BLKSYNC_CONFIG_RESERVED0_MASK 0xff80 28440 #define RX_X4_CONTROL0_BLKSYNC_CONFIG_RESERVED0_ALIGN 0 28441 #define RX_X4_CONTROL0_BLKSYNC_CONFIG_RESERVED0_BITS 9 28442 #define RX_X4_CONTROL0_BLKSYNC_CONFIG_RESERVED0_SHIFT 7 28443 28444 /* RX_X4_Control0 :: blksync_config :: blk_lock_on_ctrl [06:06] */ 28445 #define RX_X4_CONTROL0_BLKSYNC_CONFIG_BLK_LOCK_ON_CTRL_MASK 0x0040 28446 #define RX_X4_CONTROL0_BLKSYNC_CONFIG_BLK_LOCK_ON_CTRL_ALIGN 0 28447 #define RX_X4_CONTROL0_BLKSYNC_CONFIG_BLK_LOCK_ON_CTRL_BITS 1 28448 #define RX_X4_CONTROL0_BLKSYNC_CONFIG_BLK_LOCK_ON_CTRL_SHIFT 6 28449 28450 /* RX_X4_Control0 :: blksync_config :: bs_sm_sync_mode [05:05] */ 28451 #define RX_X4_CONTROL0_BLKSYNC_CONFIG_BS_SM_SYNC_MODE_MASK 0x0020 28452 #define RX_X4_CONTROL0_BLKSYNC_CONFIG_BS_SM_SYNC_MODE_ALIGN 0 28453 #define RX_X4_CONTROL0_BLKSYNC_CONFIG_BS_SM_SYNC_MODE_BITS 1 28454 #define RX_X4_CONTROL0_BLKSYNC_CONFIG_BS_SM_SYNC_MODE_SHIFT 5 28455 28456 /* RX_X4_Control0 :: blksync_config :: bs_sync_en [04:04] */ 28457 #define RX_X4_CONTROL0_BLKSYNC_CONFIG_BS_SYNC_EN_MASK 0x0010 28458 #define RX_X4_CONTROL0_BLKSYNC_CONFIG_BS_SYNC_EN_ALIGN 0 28459 #define RX_X4_CONTROL0_BLKSYNC_CONFIG_BS_SYNC_EN_BITS 1 28460 #define RX_X4_CONTROL0_BLKSYNC_CONFIG_BS_SYNC_EN_SHIFT 4 28461 28462 /* RX_X4_Control0 :: blksync_config :: bs_dist_mode [03:02] */ 28463 #define RX_X4_CONTROL0_BLKSYNC_CONFIG_BS_DIST_MODE_MASK 0x000c 28464 #define RX_X4_CONTROL0_BLKSYNC_CONFIG_BS_DIST_MODE_ALIGN 0 28465 #define RX_X4_CONTROL0_BLKSYNC_CONFIG_BS_DIST_MODE_BITS 2 28466 #define RX_X4_CONTROL0_BLKSYNC_CONFIG_BS_DIST_MODE_SHIFT 2 28467 #define RX_X4_CONTROL0_BLKSYNC_CONFIG_BS_DIST_MODE_BS_DIST_MODE_5_LANE_TDM 0 28468 #define RX_X4_CONTROL0_BLKSYNC_CONFIG_BS_DIST_MODE_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 28469 #define RX_X4_CONTROL0_BLKSYNC_CONFIG_BS_DIST_MODE_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 28470 #define RX_X4_CONTROL0_BLKSYNC_CONFIG_BS_DIST_MODE_BS_DIST_MODE_NO_TDM 3 28471 28472 /* RX_X4_Control0 :: blksync_config :: bs_btmx_mode [01:00] */ 28473 #define RX_X4_CONTROL0_BLKSYNC_CONFIG_BS_BTMX_MODE_MASK 0x0003 28474 #define RX_X4_CONTROL0_BLKSYNC_CONFIG_BS_BTMX_MODE_ALIGN 0 28475 #define RX_X4_CONTROL0_BLKSYNC_CONFIG_BS_BTMX_MODE_BITS 2 28476 #define RX_X4_CONTROL0_BLKSYNC_CONFIG_BS_BTMX_MODE_SHIFT 0 28477 #define RX_X4_CONTROL0_BLKSYNC_CONFIG_BS_BTMX_MODE_BS_BTMX_MODE_1to1 0 28478 #define RX_X4_CONTROL0_BLKSYNC_CONFIG_BS_BTMX_MODE_BS_BTMX_MODE_2to1 1 28479 #define RX_X4_CONTROL0_BLKSYNC_CONFIG_BS_BTMX_MODE_BS_BTMX_MODE_5to1 2 28480 28481 28482 /**************************************************************************** 28483 * RX_X4_Control0 :: pma_control_0 28484 */ 28485 /* RX_X4_Control0 :: pma_control_0 :: reserved0 [15:01] */ 28486 #define RX_X4_CONTROL0_PMA_CONTROL_0_RESERVED0_MASK 0xfffe 28487 #define RX_X4_CONTROL0_PMA_CONTROL_0_RESERVED0_ALIGN 0 28488 #define RX_X4_CONTROL0_PMA_CONTROL_0_RESERVED0_BITS 15 28489 #define RX_X4_CONTROL0_PMA_CONTROL_0_RESERVED0_SHIFT 1 28490 28491 /* RX_X4_Control0 :: pma_control_0 :: rstb_lane [00:00] */ 28492 #define RX_X4_CONTROL0_PMA_CONTROL_0_RSTB_LANE_MASK 0x0001 28493 #define RX_X4_CONTROL0_PMA_CONTROL_0_RSTB_LANE_ALIGN 0 28494 #define RX_X4_CONTROL0_PMA_CONTROL_0_RSTB_LANE_BITS 1 28495 #define RX_X4_CONTROL0_PMA_CONTROL_0_RSTB_LANE_SHIFT 0 28496 28497 28498 /**************************************************************************** 28499 * RX_X4_Control0 :: link_control 28500 */ 28501 /* RX_X4_Control0 :: link_control :: reserved0 [15:01] */ 28502 #define RX_X4_CONTROL0_LINK_CONTROL_RESERVED0_MASK 0xfffe 28503 #define RX_X4_CONTROL0_LINK_CONTROL_RESERVED0_ALIGN 0 28504 #define RX_X4_CONTROL0_LINK_CONTROL_RESERVED0_BITS 15 28505 #define RX_X4_CONTROL0_LINK_CONTROL_RESERVED0_SHIFT 1 28506 28507 /* RX_X4_Control0 :: link_control :: latch_linkdown_enable [00:00] */ 28508 #define RX_X4_CONTROL0_LINK_CONTROL_LATCH_LINKDOWN_ENABLE_MASK 0x0001 28509 #define RX_X4_CONTROL0_LINK_CONTROL_LATCH_LINKDOWN_ENABLE_ALIGN 0 28510 #define RX_X4_CONTROL0_LINK_CONTROL_LATCH_LINKDOWN_ENABLE_BITS 1 28511 #define RX_X4_CONTROL0_LINK_CONTROL_LATCH_LINKDOWN_ENABLE_SHIFT 0 28512 28513 28514 /**************************************************************************** 28515 * RX_X4_Control0 :: cl36rx_control 28516 */ 28517 /* RX_X4_Control0 :: cl36rx_control :: reserved0 [15:05] */ 28518 #define RX_X4_CONTROL0_CL36RX_CONTROL_RESERVED0_MASK 0xffe0 28519 #define RX_X4_CONTROL0_CL36RX_CONTROL_RESERVED0_ALIGN 0 28520 #define RX_X4_CONTROL0_CL36RX_CONTROL_RESERVED0_BITS 11 28521 #define RX_X4_CONTROL0_CL36RX_CONTROL_RESERVED0_SHIFT 5 28522 28523 /* RX_X4_Control0 :: cl36rx_control :: cl36rx_BER_en [04:04] */ 28524 #define RX_X4_CONTROL0_CL36RX_CONTROL_CL36RX_BER_EN_MASK 0x0010 28525 #define RX_X4_CONTROL0_CL36RX_CONTROL_CL36RX_BER_EN_ALIGN 0 28526 #define RX_X4_CONTROL0_CL36RX_CONTROL_CL36RX_BER_EN_BITS 1 28527 #define RX_X4_CONTROL0_CL36RX_CONTROL_CL36RX_BER_EN_SHIFT 4 28528 28529 /* RX_X4_Control0 :: cl36rx_control :: cl36rx_force_comma_align_enable [03:03] */ 28530 #define RX_X4_CONTROL0_CL36RX_CONTROL_CL36RX_FORCE_COMMA_ALIGN_ENABLE_MASK 0x0008 28531 #define RX_X4_CONTROL0_CL36RX_CONTROL_CL36RX_FORCE_COMMA_ALIGN_ENABLE_ALIGN 0 28532 #define RX_X4_CONTROL0_CL36RX_CONTROL_CL36RX_FORCE_COMMA_ALIGN_ENABLE_BITS 1 28533 #define RX_X4_CONTROL0_CL36RX_CONTROL_CL36RX_FORCE_COMMA_ALIGN_ENABLE_SHIFT 3 28534 28535 /* RX_X4_Control0 :: cl36rx_control :: cl36rx_disable_carrier_extend [02:02] */ 28536 #define RX_X4_CONTROL0_CL36RX_CONTROL_CL36RX_DISABLE_CARRIER_EXTEND_MASK 0x0004 28537 #define RX_X4_CONTROL0_CL36RX_CONTROL_CL36RX_DISABLE_CARRIER_EXTEND_ALIGN 0 28538 #define RX_X4_CONTROL0_CL36RX_CONTROL_CL36RX_DISABLE_CARRIER_EXTEND_BITS 1 28539 #define RX_X4_CONTROL0_CL36RX_CONTROL_CL36RX_DISABLE_CARRIER_EXTEND_SHIFT 2 28540 28541 /* RX_X4_Control0 :: cl36rx_control :: cl36rx_LPI_en [01:01] */ 28542 #define RX_X4_CONTROL0_CL36RX_CONTROL_CL36RX_LPI_EN_MASK 0x0002 28543 #define RX_X4_CONTROL0_CL36RX_CONTROL_CL36RX_LPI_EN_ALIGN 0 28544 #define RX_X4_CONTROL0_CL36RX_CONTROL_CL36RX_LPI_EN_BITS 1 28545 #define RX_X4_CONTROL0_CL36RX_CONTROL_CL36RX_LPI_EN_SHIFT 1 28546 28547 /* RX_X4_Control0 :: cl36rx_control :: cl36rx_en [00:00] */ 28548 #define RX_X4_CONTROL0_CL36RX_CONTROL_CL36RX_EN_MASK 0x0001 28549 #define RX_X4_CONTROL0_CL36RX_CONTROL_CL36RX_EN_ALIGN 0 28550 #define RX_X4_CONTROL0_CL36RX_CONTROL_CL36RX_EN_BITS 1 28551 #define RX_X4_CONTROL0_CL36RX_CONTROL_CL36RX_EN_SHIFT 0 28552 28553 28554 /**************************************************************************** 28555 * RX_X4_Control0 :: synce_fractional_div 28556 */ 28557 /* RX_X4_Control0 :: synce_fractional_div :: syncE_fractional_divsor_cfg [15:00] */ 28558 #define RX_X4_CONTROL0_SYNCE_FRACTIONAL_DIV_SYNCE_FRACTIONAL_DIVSOR_CFG_MASK 0xffff 28559 #define RX_X4_CONTROL0_SYNCE_FRACTIONAL_DIV_SYNCE_FRACTIONAL_DIVSOR_CFG_ALIGN 0 28560 #define RX_X4_CONTROL0_SYNCE_FRACTIONAL_DIV_SYNCE_FRACTIONAL_DIVSOR_CFG_BITS 16 28561 #define RX_X4_CONTROL0_SYNCE_FRACTIONAL_DIV_SYNCE_FRACTIONAL_DIVSOR_CFG_SHIFT 0 28562 28563 28564 /**************************************************************************** 28565 * RX_X4_Control0 :: bermon_window_override 28566 */ 28567 /* RX_X4_Control0 :: bermon_window_override :: ber_window_override [15:15] */ 28568 #define RX_X4_CONTROL0_BERMON_WINDOW_OVERRIDE_BER_WINDOW_OVERRIDE_MASK 0x8000 28569 #define RX_X4_CONTROL0_BERMON_WINDOW_OVERRIDE_BER_WINDOW_OVERRIDE_ALIGN 0 28570 #define RX_X4_CONTROL0_BERMON_WINDOW_OVERRIDE_BER_WINDOW_OVERRIDE_BITS 1 28571 #define RX_X4_CONTROL0_BERMON_WINDOW_OVERRIDE_BER_WINDOW_OVERRIDE_SHIFT 15 28572 28573 /* RX_X4_Control0 :: bermon_window_override :: ber_window_size [14:00] */ 28574 #define RX_X4_CONTROL0_BERMON_WINDOW_OVERRIDE_BER_WINDOW_SIZE_MASK 0x7fff 28575 #define RX_X4_CONTROL0_BERMON_WINDOW_OVERRIDE_BER_WINDOW_SIZE_ALIGN 0 28576 #define RX_X4_CONTROL0_BERMON_WINDOW_OVERRIDE_BER_WINDOW_SIZE_BITS 15 28577 #define RX_X4_CONTROL0_BERMON_WINDOW_OVERRIDE_BER_WINDOW_SIZE_SHIFT 0 28578 28579 28580 /**************************************************************************** 28581 * RX_X4_Control0 :: ieee_25g_parllel_det_ctr 28582 */ 28583 /* RX_X4_Control0 :: ieee_25g_parllel_det_ctr :: msa_ieee_det_en [15:15] */ 28584 #define RX_X4_CONTROL0_IEEE_25G_PARLLEL_DET_CTR_MSA_IEEE_DET_EN_MASK 0x8000 28585 #define RX_X4_CONTROL0_IEEE_25G_PARLLEL_DET_CTR_MSA_IEEE_DET_EN_ALIGN 0 28586 #define RX_X4_CONTROL0_IEEE_25G_PARLLEL_DET_CTR_MSA_IEEE_DET_EN_BITS 1 28587 #define RX_X4_CONTROL0_IEEE_25G_PARLLEL_DET_CTR_MSA_IEEE_DET_EN_SHIFT 15 28588 28589 /* RX_X4_Control0 :: ieee_25g_parllel_det_ctr :: msa_ieee_det_timeperiod [14:00] */ 28590 #define RX_X4_CONTROL0_IEEE_25G_PARLLEL_DET_CTR_MSA_IEEE_DET_TIMEPERIOD_MASK 0x7fff 28591 #define RX_X4_CONTROL0_IEEE_25G_PARLLEL_DET_CTR_MSA_IEEE_DET_TIMEPERIOD_ALIGN 0 28592 #define RX_X4_CONTROL0_IEEE_25G_PARLLEL_DET_CTR_MSA_IEEE_DET_TIMEPERIOD_BITS 15 28593 #define RX_X4_CONTROL0_IEEE_25G_PARLLEL_DET_CTR_MSA_IEEE_DET_TIMEPERIOD_SHIFT 0 28594 28595 28596 /**************************************************************************** 28597 * TSC_WC4_TSC_USER4_RX_X4_Fec_Control 28598 */ 28599 /**************************************************************************** 28600 * RX_X4_Fec_Control :: fec_0 28601 */ 28602 /* RX_X4_Fec_Control :: fec_0 :: reserved0 [15:15] */ 28603 #define RX_X4_FEC_CONTROL_FEC_0_RESERVED0_MASK 0x8000 28604 #define RX_X4_FEC_CONTROL_FEC_0_RESERVED0_ALIGN 0 28605 #define RX_X4_FEC_CONTROL_FEC_0_RESERVED0_BITS 1 28606 #define RX_X4_FEC_CONTROL_FEC_0_RESERVED0_SHIFT 15 28607 28608 /* RX_X4_Fec_Control :: fec_0 :: good_parity_cnt [14:12] */ 28609 #define RX_X4_FEC_CONTROL_FEC_0_GOOD_PARITY_CNT_MASK 0x7000 28610 #define RX_X4_FEC_CONTROL_FEC_0_GOOD_PARITY_CNT_ALIGN 0 28611 #define RX_X4_FEC_CONTROL_FEC_0_GOOD_PARITY_CNT_BITS 3 28612 #define RX_X4_FEC_CONTROL_FEC_0_GOOD_PARITY_CNT_SHIFT 12 28613 28614 /* RX_X4_Fec_Control :: fec_0 :: invalid_parity_cnt [11:08] */ 28615 #define RX_X4_FEC_CONTROL_FEC_0_INVALID_PARITY_CNT_MASK 0x0f00 28616 #define RX_X4_FEC_CONTROL_FEC_0_INVALID_PARITY_CNT_ALIGN 0 28617 #define RX_X4_FEC_CONTROL_FEC_0_INVALID_PARITY_CNT_BITS 4 28618 #define RX_X4_FEC_CONTROL_FEC_0_INVALID_PARITY_CNT_SHIFT 8 28619 28620 /* RX_X4_Fec_Control :: fec_0 :: dec_max_pm [07:02] */ 28621 #define RX_X4_FEC_CONTROL_FEC_0_DEC_MAX_PM_MASK 0x00fc 28622 #define RX_X4_FEC_CONTROL_FEC_0_DEC_MAX_PM_ALIGN 0 28623 #define RX_X4_FEC_CONTROL_FEC_0_DEC_MAX_PM_BITS 6 28624 #define RX_X4_FEC_CONTROL_FEC_0_DEC_MAX_PM_SHIFT 2 28625 28626 /* RX_X4_Fec_Control :: fec_0 :: burst_err_status_mode [01:01] */ 28627 #define RX_X4_FEC_CONTROL_FEC_0_BURST_ERR_STATUS_MODE_MASK 0x0002 28628 #define RX_X4_FEC_CONTROL_FEC_0_BURST_ERR_STATUS_MODE_ALIGN 0 28629 #define RX_X4_FEC_CONTROL_FEC_0_BURST_ERR_STATUS_MODE_BITS 1 28630 #define RX_X4_FEC_CONTROL_FEC_0_BURST_ERR_STATUS_MODE_SHIFT 1 28631 28632 /* RX_X4_Fec_Control :: fec_0 :: dbg_err_mode [00:00] */ 28633 #define RX_X4_FEC_CONTROL_FEC_0_DBG_ERR_MODE_MASK 0x0001 28634 #define RX_X4_FEC_CONTROL_FEC_0_DBG_ERR_MODE_ALIGN 0 28635 #define RX_X4_FEC_CONTROL_FEC_0_DBG_ERR_MODE_BITS 1 28636 #define RX_X4_FEC_CONTROL_FEC_0_DBG_ERR_MODE_SHIFT 0 28637 28638 28639 /**************************************************************************** 28640 * RX_X4_Fec_Control :: fec_1 28641 */ 28642 /* RX_X4_Fec_Control :: fec_1 :: dec_pm_mode [15:11] */ 28643 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_MASK 0xf800 28644 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_ALIGN 0 28645 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_BITS 5 28646 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_SHIFT 11 28647 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_BURST_ERROR_11_BITS 0 28648 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_BURST_ERROR_16_BITS 1 28649 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_BURST_ERROR_17_BITS 2 28650 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_BURST_ERROR_18_BITS 3 28651 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_BURST_ERROR_19_BITS 4 28652 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_BURST_ERROR_20_BITS 5 28653 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_BURST_ERROR_21_BITS 6 28654 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_BURST_ERROR_22_BITS 7 28655 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_BURST_ERROR_23_BITS 8 28656 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_BURST_ERROR_24_BITS 9 28657 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_BURST_ERROR_25_BITS 10 28658 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_BURST_ERROR_26_BITS 11 28659 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_BURST_ERROR_27_BITS 12 28660 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_BURST_ERROR_28_BITS 13 28661 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_BURST_ERROR_29_BITS 14 28662 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_BURST_ERROR_30_BITS 15 28663 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_BURST_ERROR_31_BITS 16 28664 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_BURST_ERROR_32_BITS 17 28665 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_BURST_ERROR_33_BITS 18 28666 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_BURST_ERROR_34_BITS 19 28667 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_BURST_ERROR_35_BITS 20 28668 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_BURST_ERROR_36_BITS 21 28669 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_BURST_ERROR_37_BITS 22 28670 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_BURST_ERROR_38_BITS 23 28671 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_BURST_ERROR_39_BITS 24 28672 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_BURST_ERROR_40_BITS 25 28673 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_BURST_ERROR_41_BITS 26 28674 28675 /* RX_X4_Fec_Control :: fec_1 :: dec_19b_burst_gap_count [10:08] */ 28676 #define RX_X4_FEC_CONTROL_FEC_1_DEC_19B_BURST_GAP_COUNT_MASK 0x0700 28677 #define RX_X4_FEC_CONTROL_FEC_1_DEC_19B_BURST_GAP_COUNT_ALIGN 0 28678 #define RX_X4_FEC_CONTROL_FEC_1_DEC_19B_BURST_GAP_COUNT_BITS 3 28679 #define RX_X4_FEC_CONTROL_FEC_1_DEC_19B_BURST_GAP_COUNT_SHIFT 8 28680 28681 /* RX_X4_Fec_Control :: fec_1 :: dec_18b_burst_gap_count [07:05] */ 28682 #define RX_X4_FEC_CONTROL_FEC_1_DEC_18B_BURST_GAP_COUNT_MASK 0x00e0 28683 #define RX_X4_FEC_CONTROL_FEC_1_DEC_18B_BURST_GAP_COUNT_ALIGN 0 28684 #define RX_X4_FEC_CONTROL_FEC_1_DEC_18B_BURST_GAP_COUNT_BITS 3 28685 #define RX_X4_FEC_CONTROL_FEC_1_DEC_18B_BURST_GAP_COUNT_SHIFT 5 28686 28687 /* RX_X4_Fec_Control :: fec_1 :: dec_17b_burst_gap_count [04:02] */ 28688 #define RX_X4_FEC_CONTROL_FEC_1_DEC_17B_BURST_GAP_COUNT_MASK 0x001c 28689 #define RX_X4_FEC_CONTROL_FEC_1_DEC_17B_BURST_GAP_COUNT_ALIGN 0 28690 #define RX_X4_FEC_CONTROL_FEC_1_DEC_17B_BURST_GAP_COUNT_BITS 3 28691 #define RX_X4_FEC_CONTROL_FEC_1_DEC_17B_BURST_GAP_COUNT_SHIFT 2 28692 28693 /* RX_X4_Fec_Control :: fec_1 :: dec_gap_count_mode [01:01] */ 28694 #define RX_X4_FEC_CONTROL_FEC_1_DEC_GAP_COUNT_MODE_MASK 0x0002 28695 #define RX_X4_FEC_CONTROL_FEC_1_DEC_GAP_COUNT_MODE_ALIGN 0 28696 #define RX_X4_FEC_CONTROL_FEC_1_DEC_GAP_COUNT_MODE_BITS 1 28697 #define RX_X4_FEC_CONTROL_FEC_1_DEC_GAP_COUNT_MODE_SHIFT 1 28698 28699 /* RX_X4_Fec_Control :: fec_1 :: reserved0 [00:00] */ 28700 #define RX_X4_FEC_CONTROL_FEC_1_RESERVED0_MASK 0x0001 28701 #define RX_X4_FEC_CONTROL_FEC_1_RESERVED0_ALIGN 0 28702 #define RX_X4_FEC_CONTROL_FEC_1_RESERVED0_BITS 1 28703 #define RX_X4_FEC_CONTROL_FEC_1_RESERVED0_SHIFT 0 28704 28705 28706 /**************************************************************************** 28707 * RX_X4_Fec_Control :: fec_2 28708 */ 28709 /* RX_X4_Fec_Control :: fec_2 :: reserved0 [15:15] */ 28710 #define RX_X4_FEC_CONTROL_FEC_2_RESERVED0_MASK 0x8000 28711 #define RX_X4_FEC_CONTROL_FEC_2_RESERVED0_ALIGN 0 28712 #define RX_X4_FEC_CONTROL_FEC_2_RESERVED0_BITS 1 28713 #define RX_X4_FEC_CONTROL_FEC_2_RESERVED0_SHIFT 15 28714 28715 /* RX_X4_Fec_Control :: fec_2 :: fec_err_enable_per_stream [14:10] */ 28716 #define RX_X4_FEC_CONTROL_FEC_2_FEC_ERR_ENABLE_PER_STREAM_MASK 0x7c00 28717 #define RX_X4_FEC_CONTROL_FEC_2_FEC_ERR_ENABLE_PER_STREAM_ALIGN 0 28718 #define RX_X4_FEC_CONTROL_FEC_2_FEC_ERR_ENABLE_PER_STREAM_BITS 5 28719 #define RX_X4_FEC_CONTROL_FEC_2_FEC_ERR_ENABLE_PER_STREAM_SHIFT 10 28720 28721 /* RX_X4_Fec_Control :: fec_2 :: dbg_enable_per_stream [09:05] */ 28722 #define RX_X4_FEC_CONTROL_FEC_2_DBG_ENABLE_PER_STREAM_MASK 0x03e0 28723 #define RX_X4_FEC_CONTROL_FEC_2_DBG_ENABLE_PER_STREAM_ALIGN 0 28724 #define RX_X4_FEC_CONTROL_FEC_2_DBG_ENABLE_PER_STREAM_BITS 5 28725 #define RX_X4_FEC_CONTROL_FEC_2_DBG_ENABLE_PER_STREAM_SHIFT 5 28726 28727 /* RX_X4_Fec_Control :: fec_2 :: fec_error_code_all_per_stream [04:00] */ 28728 #define RX_X4_FEC_CONTROL_FEC_2_FEC_ERROR_CODE_ALL_PER_STREAM_MASK 0x001f 28729 #define RX_X4_FEC_CONTROL_FEC_2_FEC_ERROR_CODE_ALL_PER_STREAM_ALIGN 0 28730 #define RX_X4_FEC_CONTROL_FEC_2_FEC_ERROR_CODE_ALL_PER_STREAM_BITS 5 28731 #define RX_X4_FEC_CONTROL_FEC_2_FEC_ERROR_CODE_ALL_PER_STREAM_SHIFT 0 28732 28733 28734 /**************************************************************************** 28735 * RX_X4_Fec_Control :: fec_3 28736 */ 28737 /* RX_X4_Fec_Control :: fec_3 :: reserved0 [15:10] */ 28738 #define RX_X4_FEC_CONTROL_FEC_3_RESERVED0_MASK 0xfc00 28739 #define RX_X4_FEC_CONTROL_FEC_3_RESERVED0_ALIGN 0 28740 #define RX_X4_FEC_CONTROL_FEC_3_RESERVED0_BITS 6 28741 #define RX_X4_FEC_CONTROL_FEC_3_RESERVED0_SHIFT 10 28742 28743 /* RX_X4_Fec_Control :: fec_3 :: error_en_ovr_val_per_stream [09:05] */ 28744 #define RX_X4_FEC_CONTROL_FEC_3_ERROR_EN_OVR_VAL_PER_STREAM_MASK 0x03e0 28745 #define RX_X4_FEC_CONTROL_FEC_3_ERROR_EN_OVR_VAL_PER_STREAM_ALIGN 0 28746 #define RX_X4_FEC_CONTROL_FEC_3_ERROR_EN_OVR_VAL_PER_STREAM_BITS 5 28747 #define RX_X4_FEC_CONTROL_FEC_3_ERROR_EN_OVR_VAL_PER_STREAM_SHIFT 5 28748 28749 /* RX_X4_Fec_Control :: fec_3 :: error_en_ovr_per_stream [04:00] */ 28750 #define RX_X4_FEC_CONTROL_FEC_3_ERROR_EN_OVR_PER_STREAM_MASK 0x001f 28751 #define RX_X4_FEC_CONTROL_FEC_3_ERROR_EN_OVR_PER_STREAM_ALIGN 0 28752 #define RX_X4_FEC_CONTROL_FEC_3_ERROR_EN_OVR_PER_STREAM_BITS 5 28753 #define RX_X4_FEC_CONTROL_FEC_3_ERROR_EN_OVR_PER_STREAM_SHIFT 0 28754 28755 28756 /**************************************************************************** 28757 * TSC_WC4_TSC_USER4_RX_X4_Status0 28758 */ 28759 /**************************************************************************** 28760 * RX_X4_Status0 :: blksync_status 28761 */ 28762 /* RX_X4_Status0 :: blksync_status :: reserved0 [15:06] */ 28763 #define RX_X4_STATUS0_BLKSYNC_STATUS_RESERVED0_MASK 0xffc0 28764 #define RX_X4_STATUS0_BLKSYNC_STATUS_RESERVED0_ALIGN 0 28765 #define RX_X4_STATUS0_BLKSYNC_STATUS_RESERVED0_BITS 10 28766 #define RX_X4_STATUS0_BLKSYNC_STATUS_RESERVED0_SHIFT 6 28767 28768 /* RX_X4_Status0 :: blksync_status :: bs_pmd_lock [05:05] */ 28769 #define RX_X4_STATUS0_BLKSYNC_STATUS_BS_PMD_LOCK_MASK 0x0020 28770 #define RX_X4_STATUS0_BLKSYNC_STATUS_BS_PMD_LOCK_ALIGN 0 28771 #define RX_X4_STATUS0_BLKSYNC_STATUS_BS_PMD_LOCK_BITS 1 28772 #define RX_X4_STATUS0_BLKSYNC_STATUS_BS_PMD_LOCK_SHIFT 5 28773 28774 /* RX_X4_Status0 :: blksync_status :: bs_status [04:00] */ 28775 #define RX_X4_STATUS0_BLKSYNC_STATUS_BS_STATUS_MASK 0x001f 28776 #define RX_X4_STATUS0_BLKSYNC_STATUS_BS_STATUS_ALIGN 0 28777 #define RX_X4_STATUS0_BLKSYNC_STATUS_BS_STATUS_BITS 5 28778 #define RX_X4_STATUS0_BLKSYNC_STATUS_BS_STATUS_SHIFT 0 28779 28780 28781 /**************************************************************************** 28782 * RX_X4_Status0 :: blksync_dbg0 28783 */ 28784 /* RX_X4_Status0 :: blksync_dbg0 :: lane1_debug_info [15:08] */ 28785 #define RX_X4_STATUS0_BLKSYNC_DBG0_LANE1_DEBUG_INFO_MASK 0xff00 28786 #define RX_X4_STATUS0_BLKSYNC_DBG0_LANE1_DEBUG_INFO_ALIGN 0 28787 #define RX_X4_STATUS0_BLKSYNC_DBG0_LANE1_DEBUG_INFO_BITS 8 28788 #define RX_X4_STATUS0_BLKSYNC_DBG0_LANE1_DEBUG_INFO_SHIFT 8 28789 28790 /* RX_X4_Status0 :: blksync_dbg0 :: lane0_debug_info [07:00] */ 28791 #define RX_X4_STATUS0_BLKSYNC_DBG0_LANE0_DEBUG_INFO_MASK 0x00ff 28792 #define RX_X4_STATUS0_BLKSYNC_DBG0_LANE0_DEBUG_INFO_ALIGN 0 28793 #define RX_X4_STATUS0_BLKSYNC_DBG0_LANE0_DEBUG_INFO_BITS 8 28794 #define RX_X4_STATUS0_BLKSYNC_DBG0_LANE0_DEBUG_INFO_SHIFT 0 28795 28796 28797 /**************************************************************************** 28798 * RX_X4_Status0 :: blksync_dbg1 28799 */ 28800 /* RX_X4_Status0 :: blksync_dbg1 :: lane3_debug_info [15:08] */ 28801 #define RX_X4_STATUS0_BLKSYNC_DBG1_LANE3_DEBUG_INFO_MASK 0xff00 28802 #define RX_X4_STATUS0_BLKSYNC_DBG1_LANE3_DEBUG_INFO_ALIGN 0 28803 #define RX_X4_STATUS0_BLKSYNC_DBG1_LANE3_DEBUG_INFO_BITS 8 28804 #define RX_X4_STATUS0_BLKSYNC_DBG1_LANE3_DEBUG_INFO_SHIFT 8 28805 28806 /* RX_X4_Status0 :: blksync_dbg1 :: lane2_debug_info [07:00] */ 28807 #define RX_X4_STATUS0_BLKSYNC_DBG1_LANE2_DEBUG_INFO_MASK 0x00ff 28808 #define RX_X4_STATUS0_BLKSYNC_DBG1_LANE2_DEBUG_INFO_ALIGN 0 28809 #define RX_X4_STATUS0_BLKSYNC_DBG1_LANE2_DEBUG_INFO_BITS 8 28810 #define RX_X4_STATUS0_BLKSYNC_DBG1_LANE2_DEBUG_INFO_SHIFT 0 28811 28812 28813 /**************************************************************************** 28814 * RX_X4_Status0 :: blksync_dbg2 28815 */ 28816 /* RX_X4_Status0 :: blksync_dbg2 :: reserved0 [15:08] */ 28817 #define RX_X4_STATUS0_BLKSYNC_DBG2_RESERVED0_MASK 0xff00 28818 #define RX_X4_STATUS0_BLKSYNC_DBG2_RESERVED0_ALIGN 0 28819 #define RX_X4_STATUS0_BLKSYNC_DBG2_RESERVED0_BITS 8 28820 #define RX_X4_STATUS0_BLKSYNC_DBG2_RESERVED0_SHIFT 8 28821 28822 /* RX_X4_Status0 :: blksync_dbg2 :: lane4_debug_info [07:00] */ 28823 #define RX_X4_STATUS0_BLKSYNC_DBG2_LANE4_DEBUG_INFO_MASK 0x00ff 28824 #define RX_X4_STATUS0_BLKSYNC_DBG2_LANE4_DEBUG_INFO_ALIGN 0 28825 #define RX_X4_STATUS0_BLKSYNC_DBG2_LANE4_DEBUG_INFO_BITS 8 28826 #define RX_X4_STATUS0_BLKSYNC_DBG2_LANE4_DEBUG_INFO_SHIFT 0 28827 28828 28829 /**************************************************************************** 28830 * RX_X4_Status0 :: block_lock_latched_status 28831 */ 28832 /* RX_X4_Status0 :: block_lock_latched_status :: reserved0 [15:10] */ 28833 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_RESERVED0_MASK 0xfc00 28834 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_RESERVED0_ALIGN 0 28835 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_RESERVED0_BITS 6 28836 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_RESERVED0_SHIFT 10 28837 28838 /* RX_X4_Status0 :: block_lock_latched_status :: BLOCK_LOCK_LH_4 [09:09] */ 28839 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LH_4_MASK 0x0200 28840 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LH_4_ALIGN 0 28841 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LH_4_BITS 1 28842 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LH_4_SHIFT 9 28843 28844 /* RX_X4_Status0 :: block_lock_latched_status :: BLOCK_LOCK_LL_4 [08:08] */ 28845 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LL_4_MASK 0x0100 28846 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LL_4_ALIGN 0 28847 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LL_4_BITS 1 28848 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LL_4_SHIFT 8 28849 28850 /* RX_X4_Status0 :: block_lock_latched_status :: BLOCK_LOCK_LH_3 [07:07] */ 28851 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LH_3_MASK 0x0080 28852 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LH_3_ALIGN 0 28853 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LH_3_BITS 1 28854 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LH_3_SHIFT 7 28855 28856 /* RX_X4_Status0 :: block_lock_latched_status :: BLOCK_LOCK_LL_3 [06:06] */ 28857 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LL_3_MASK 0x0040 28858 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LL_3_ALIGN 0 28859 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LL_3_BITS 1 28860 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LL_3_SHIFT 6 28861 28862 /* RX_X4_Status0 :: block_lock_latched_status :: BLOCK_LOCK_LH_2 [05:05] */ 28863 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LH_2_MASK 0x0020 28864 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LH_2_ALIGN 0 28865 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LH_2_BITS 1 28866 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LH_2_SHIFT 5 28867 28868 /* RX_X4_Status0 :: block_lock_latched_status :: BLOCK_LOCK_LL_2 [04:04] */ 28869 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LL_2_MASK 0x0010 28870 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LL_2_ALIGN 0 28871 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LL_2_BITS 1 28872 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LL_2_SHIFT 4 28873 28874 /* RX_X4_Status0 :: block_lock_latched_status :: BLOCK_LOCK_LH_1 [03:03] */ 28875 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LH_1_MASK 0x0008 28876 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LH_1_ALIGN 0 28877 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LH_1_BITS 1 28878 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LH_1_SHIFT 3 28879 28880 /* RX_X4_Status0 :: block_lock_latched_status :: BLOCK_LOCK_LL_1 [02:02] */ 28881 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LL_1_MASK 0x0004 28882 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LL_1_ALIGN 0 28883 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LL_1_BITS 1 28884 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LL_1_SHIFT 2 28885 28886 /* RX_X4_Status0 :: block_lock_latched_status :: BLOCK_LOCK_LH_0 [01:01] */ 28887 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LH_0_MASK 0x0002 28888 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LH_0_ALIGN 0 28889 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LH_0_BITS 1 28890 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LH_0_SHIFT 1 28891 28892 /* RX_X4_Status0 :: block_lock_latched_status :: BLOCK_LOCK_LL_0 [00:00] */ 28893 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LL_0_MASK 0x0001 28894 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LL_0_ALIGN 0 28895 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LL_0_BITS 1 28896 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LL_0_SHIFT 0 28897 28898 28899 /**************************************************************************** 28900 * RX_X4_Status0 :: am_lock_latched_status 28901 */ 28902 /* RX_X4_Status0 :: am_lock_latched_status :: reserved0 [15:10] */ 28903 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_RESERVED0_MASK 0xfc00 28904 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_RESERVED0_ALIGN 0 28905 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_RESERVED0_BITS 6 28906 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_RESERVED0_SHIFT 10 28907 28908 /* RX_X4_Status0 :: am_lock_latched_status :: AM_LOCK_LH_4 [09:09] */ 28909 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LH_4_MASK 0x0200 28910 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LH_4_ALIGN 0 28911 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LH_4_BITS 1 28912 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LH_4_SHIFT 9 28913 28914 /* RX_X4_Status0 :: am_lock_latched_status :: AM_LOCK_LL_4 [08:08] */ 28915 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LL_4_MASK 0x0100 28916 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LL_4_ALIGN 0 28917 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LL_4_BITS 1 28918 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LL_4_SHIFT 8 28919 28920 /* RX_X4_Status0 :: am_lock_latched_status :: AM_LOCK_LH_3 [07:07] */ 28921 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LH_3_MASK 0x0080 28922 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LH_3_ALIGN 0 28923 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LH_3_BITS 1 28924 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LH_3_SHIFT 7 28925 28926 /* RX_X4_Status0 :: am_lock_latched_status :: AM_LOCK_LL_3 [06:06] */ 28927 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LL_3_MASK 0x0040 28928 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LL_3_ALIGN 0 28929 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LL_3_BITS 1 28930 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LL_3_SHIFT 6 28931 28932 /* RX_X4_Status0 :: am_lock_latched_status :: AM_LOCK_LH_2 [05:05] */ 28933 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LH_2_MASK 0x0020 28934 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LH_2_ALIGN 0 28935 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LH_2_BITS 1 28936 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LH_2_SHIFT 5 28937 28938 /* RX_X4_Status0 :: am_lock_latched_status :: AM_LOCK_LL_2 [04:04] */ 28939 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LL_2_MASK 0x0010 28940 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LL_2_ALIGN 0 28941 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LL_2_BITS 1 28942 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LL_2_SHIFT 4 28943 28944 /* RX_X4_Status0 :: am_lock_latched_status :: AM_LOCK_LH_1 [03:03] */ 28945 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LH_1_MASK 0x0008 28946 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LH_1_ALIGN 0 28947 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LH_1_BITS 1 28948 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LH_1_SHIFT 3 28949 28950 /* RX_X4_Status0 :: am_lock_latched_status :: AM_LOCK_LL_1 [02:02] */ 28951 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LL_1_MASK 0x0004 28952 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LL_1_ALIGN 0 28953 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LL_1_BITS 1 28954 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LL_1_SHIFT 2 28955 28956 /* RX_X4_Status0 :: am_lock_latched_status :: AM_LOCK_LH_0 [01:01] */ 28957 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LH_0_MASK 0x0002 28958 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LH_0_ALIGN 0 28959 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LH_0_BITS 1 28960 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LH_0_SHIFT 1 28961 28962 /* RX_X4_Status0 :: am_lock_latched_status :: AM_LOCK_LL_0 [00:00] */ 28963 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LL_0_MASK 0x0001 28964 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LL_0_ALIGN 0 28965 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LL_0_BITS 1 28966 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LL_0_SHIFT 0 28967 28968 28969 /**************************************************************************** 28970 * RX_X4_Status0 :: pcs_live_status_0 28971 */ 28972 /* RX_X4_Status0 :: pcs_live_status_0 :: reserved0 [15:10] */ 28973 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_RESERVED0_MASK 0xfc00 28974 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_RESERVED0_ALIGN 0 28975 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_RESERVED0_BITS 6 28976 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_RESERVED0_SHIFT 10 28977 28978 /* RX_X4_Status0 :: pcs_live_status_0 :: BLOCK_LOCK_4 [09:09] */ 28979 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_BLOCK_LOCK_4_MASK 0x0200 28980 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_BLOCK_LOCK_4_ALIGN 0 28981 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_BLOCK_LOCK_4_BITS 1 28982 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_BLOCK_LOCK_4_SHIFT 9 28983 28984 /* RX_X4_Status0 :: pcs_live_status_0 :: BLOCK_LOCK_3 [08:08] */ 28985 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_BLOCK_LOCK_3_MASK 0x0100 28986 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_BLOCK_LOCK_3_ALIGN 0 28987 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_BLOCK_LOCK_3_BITS 1 28988 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_BLOCK_LOCK_3_SHIFT 8 28989 28990 /* RX_X4_Status0 :: pcs_live_status_0 :: BLOCK_LOCK_2 [07:07] */ 28991 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_BLOCK_LOCK_2_MASK 0x0080 28992 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_BLOCK_LOCK_2_ALIGN 0 28993 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_BLOCK_LOCK_2_BITS 1 28994 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_BLOCK_LOCK_2_SHIFT 7 28995 28996 /* RX_X4_Status0 :: pcs_live_status_0 :: BLOCK_LOCK_1 [06:06] */ 28997 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_BLOCK_LOCK_1_MASK 0x0040 28998 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_BLOCK_LOCK_1_ALIGN 0 28999 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_BLOCK_LOCK_1_BITS 1 29000 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_BLOCK_LOCK_1_SHIFT 6 29001 29002 /* RX_X4_Status0 :: pcs_live_status_0 :: BLOCK_LOCK_0 [05:05] */ 29003 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_BLOCK_LOCK_0_MASK 0x0020 29004 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_BLOCK_LOCK_0_ALIGN 0 29005 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_BLOCK_LOCK_0_BITS 1 29006 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_BLOCK_LOCK_0_SHIFT 5 29007 29008 /* RX_X4_Status0 :: pcs_live_status_0 :: AM_LOCK_4 [04:04] */ 29009 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_AM_LOCK_4_MASK 0x0010 29010 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_AM_LOCK_4_ALIGN 0 29011 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_AM_LOCK_4_BITS 1 29012 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_AM_LOCK_4_SHIFT 4 29013 29014 /* RX_X4_Status0 :: pcs_live_status_0 :: AM_LOCK_3 [03:03] */ 29015 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_AM_LOCK_3_MASK 0x0008 29016 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_AM_LOCK_3_ALIGN 0 29017 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_AM_LOCK_3_BITS 1 29018 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_AM_LOCK_3_SHIFT 3 29019 29020 /* RX_X4_Status0 :: pcs_live_status_0 :: AM_LOCK_2 [02:02] */ 29021 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_AM_LOCK_2_MASK 0x0004 29022 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_AM_LOCK_2_ALIGN 0 29023 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_AM_LOCK_2_BITS 1 29024 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_AM_LOCK_2_SHIFT 2 29025 29026 /* RX_X4_Status0 :: pcs_live_status_0 :: AM_LOCK_1 [01:01] */ 29027 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_AM_LOCK_1_MASK 0x0002 29028 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_AM_LOCK_1_ALIGN 0 29029 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_AM_LOCK_1_BITS 1 29030 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_AM_LOCK_1_SHIFT 1 29031 29032 /* RX_X4_Status0 :: pcs_live_status_0 :: AM_LOCK_0 [00:00] */ 29033 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_AM_LOCK_0_MASK 0x0001 29034 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_AM_LOCK_0_ALIGN 0 29035 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_AM_LOCK_0_BITS 1 29036 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_AM_LOCK_0_SHIFT 0 29037 29038 29039 /**************************************************************************** 29040 * RX_X4_Status0 :: bipcount_0 29041 */ 29042 /* RX_X4_Status0 :: bipcount_0 :: BIP_ERROR_COUNT_1 [15:08] */ 29043 #define RX_X4_STATUS0_BIPCOUNT_0_BIP_ERROR_COUNT_1_MASK 0xff00 29044 #define RX_X4_STATUS0_BIPCOUNT_0_BIP_ERROR_COUNT_1_ALIGN 0 29045 #define RX_X4_STATUS0_BIPCOUNT_0_BIP_ERROR_COUNT_1_BITS 8 29046 #define RX_X4_STATUS0_BIPCOUNT_0_BIP_ERROR_COUNT_1_SHIFT 8 29047 29048 /* RX_X4_Status0 :: bipcount_0 :: BIP_ERROR_COUNT_0 [07:00] */ 29049 #define RX_X4_STATUS0_BIPCOUNT_0_BIP_ERROR_COUNT_0_MASK 0x00ff 29050 #define RX_X4_STATUS0_BIPCOUNT_0_BIP_ERROR_COUNT_0_ALIGN 0 29051 #define RX_X4_STATUS0_BIPCOUNT_0_BIP_ERROR_COUNT_0_BITS 8 29052 #define RX_X4_STATUS0_BIPCOUNT_0_BIP_ERROR_COUNT_0_SHIFT 0 29053 29054 29055 /**************************************************************************** 29056 * RX_X4_Status0 :: bipcount_1 29057 */ 29058 /* RX_X4_Status0 :: bipcount_1 :: BIP_ERROR_COUNT_3 [15:08] */ 29059 #define RX_X4_STATUS0_BIPCOUNT_1_BIP_ERROR_COUNT_3_MASK 0xff00 29060 #define RX_X4_STATUS0_BIPCOUNT_1_BIP_ERROR_COUNT_3_ALIGN 0 29061 #define RX_X4_STATUS0_BIPCOUNT_1_BIP_ERROR_COUNT_3_BITS 8 29062 #define RX_X4_STATUS0_BIPCOUNT_1_BIP_ERROR_COUNT_3_SHIFT 8 29063 29064 /* RX_X4_Status0 :: bipcount_1 :: BIP_ERROR_COUNT_2 [07:00] */ 29065 #define RX_X4_STATUS0_BIPCOUNT_1_BIP_ERROR_COUNT_2_MASK 0x00ff 29066 #define RX_X4_STATUS0_BIPCOUNT_1_BIP_ERROR_COUNT_2_ALIGN 0 29067 #define RX_X4_STATUS0_BIPCOUNT_1_BIP_ERROR_COUNT_2_BITS 8 29068 #define RX_X4_STATUS0_BIPCOUNT_1_BIP_ERROR_COUNT_2_SHIFT 0 29069 29070 29071 /**************************************************************************** 29072 * RX_X4_Status0 :: bipcount_2 29073 */ 29074 /* RX_X4_Status0 :: bipcount_2 :: reserved0 [15:08] */ 29075 #define RX_X4_STATUS0_BIPCOUNT_2_RESERVED0_MASK 0xff00 29076 #define RX_X4_STATUS0_BIPCOUNT_2_RESERVED0_ALIGN 0 29077 #define RX_X4_STATUS0_BIPCOUNT_2_RESERVED0_BITS 8 29078 #define RX_X4_STATUS0_BIPCOUNT_2_RESERVED0_SHIFT 8 29079 29080 /* RX_X4_Status0 :: bipcount_2 :: BIP_ERROR_COUNT_4 [07:00] */ 29081 #define RX_X4_STATUS0_BIPCOUNT_2_BIP_ERROR_COUNT_4_MASK 0x00ff 29082 #define RX_X4_STATUS0_BIPCOUNT_2_BIP_ERROR_COUNT_4_ALIGN 0 29083 #define RX_X4_STATUS0_BIPCOUNT_2_BIP_ERROR_COUNT_4_BITS 8 29084 #define RX_X4_STATUS0_BIPCOUNT_2_BIP_ERROR_COUNT_4_SHIFT 0 29085 29086 29087 /**************************************************************************** 29088 * RX_X4_Status0 :: psll_to_vl_mapping_0 29089 */ 29090 /* RX_X4_Status0 :: psll_to_vl_mapping_0 :: reserved0 [15:15] */ 29091 #define RX_X4_STATUS0_PSLL_TO_VL_MAPPING_0_RESERVED0_MASK 0x8000 29092 #define RX_X4_STATUS0_PSLL_TO_VL_MAPPING_0_RESERVED0_ALIGN 0 29093 #define RX_X4_STATUS0_PSLL_TO_VL_MAPPING_0_RESERVED0_BITS 1 29094 #define RX_X4_STATUS0_PSLL_TO_VL_MAPPING_0_RESERVED0_SHIFT 15 29095 29096 /* RX_X4_Status0 :: psll_to_vl_mapping_0 :: psll2_to_vl_mapping [14:10] */ 29097 #define RX_X4_STATUS0_PSLL_TO_VL_MAPPING_0_PSLL2_TO_VL_MAPPING_MASK 0x7c00 29098 #define RX_X4_STATUS0_PSLL_TO_VL_MAPPING_0_PSLL2_TO_VL_MAPPING_ALIGN 0 29099 #define RX_X4_STATUS0_PSLL_TO_VL_MAPPING_0_PSLL2_TO_VL_MAPPING_BITS 5 29100 #define RX_X4_STATUS0_PSLL_TO_VL_MAPPING_0_PSLL2_TO_VL_MAPPING_SHIFT 10 29101 29102 /* RX_X4_Status0 :: psll_to_vl_mapping_0 :: psll1_to_vl_mapping [09:05] */ 29103 #define RX_X4_STATUS0_PSLL_TO_VL_MAPPING_0_PSLL1_TO_VL_MAPPING_MASK 0x03e0 29104 #define RX_X4_STATUS0_PSLL_TO_VL_MAPPING_0_PSLL1_TO_VL_MAPPING_ALIGN 0 29105 #define RX_X4_STATUS0_PSLL_TO_VL_MAPPING_0_PSLL1_TO_VL_MAPPING_BITS 5 29106 #define RX_X4_STATUS0_PSLL_TO_VL_MAPPING_0_PSLL1_TO_VL_MAPPING_SHIFT 5 29107 29108 /* RX_X4_Status0 :: psll_to_vl_mapping_0 :: psll0_to_vl_mapping [04:00] */ 29109 #define RX_X4_STATUS0_PSLL_TO_VL_MAPPING_0_PSLL0_TO_VL_MAPPING_MASK 0x001f 29110 #define RX_X4_STATUS0_PSLL_TO_VL_MAPPING_0_PSLL0_TO_VL_MAPPING_ALIGN 0 29111 #define RX_X4_STATUS0_PSLL_TO_VL_MAPPING_0_PSLL0_TO_VL_MAPPING_BITS 5 29112 #define RX_X4_STATUS0_PSLL_TO_VL_MAPPING_0_PSLL0_TO_VL_MAPPING_SHIFT 0 29113 29114 29115 /**************************************************************************** 29116 * RX_X4_Status0 :: psll_to_vl_mapping_1 29117 */ 29118 /* RX_X4_Status0 :: psll_to_vl_mapping_1 :: reserved0 [15:10] */ 29119 #define RX_X4_STATUS0_PSLL_TO_VL_MAPPING_1_RESERVED0_MASK 0xfc00 29120 #define RX_X4_STATUS0_PSLL_TO_VL_MAPPING_1_RESERVED0_ALIGN 0 29121 #define RX_X4_STATUS0_PSLL_TO_VL_MAPPING_1_RESERVED0_BITS 6 29122 #define RX_X4_STATUS0_PSLL_TO_VL_MAPPING_1_RESERVED0_SHIFT 10 29123 29124 /* RX_X4_Status0 :: psll_to_vl_mapping_1 :: psll4_to_vl_mapping [09:05] */ 29125 #define RX_X4_STATUS0_PSLL_TO_VL_MAPPING_1_PSLL4_TO_VL_MAPPING_MASK 0x03e0 29126 #define RX_X4_STATUS0_PSLL_TO_VL_MAPPING_1_PSLL4_TO_VL_MAPPING_ALIGN 0 29127 #define RX_X4_STATUS0_PSLL_TO_VL_MAPPING_1_PSLL4_TO_VL_MAPPING_BITS 5 29128 #define RX_X4_STATUS0_PSLL_TO_VL_MAPPING_1_PSLL4_TO_VL_MAPPING_SHIFT 5 29129 29130 /* RX_X4_Status0 :: psll_to_vl_mapping_1 :: psll3_to_vl_mapping [04:00] */ 29131 #define RX_X4_STATUS0_PSLL_TO_VL_MAPPING_1_PSLL3_TO_VL_MAPPING_MASK 0x001f 29132 #define RX_X4_STATUS0_PSLL_TO_VL_MAPPING_1_PSLL3_TO_VL_MAPPING_ALIGN 0 29133 #define RX_X4_STATUS0_PSLL_TO_VL_MAPPING_1_PSLL3_TO_VL_MAPPING_BITS 5 29134 #define RX_X4_STATUS0_PSLL_TO_VL_MAPPING_1_PSLL3_TO_VL_MAPPING_SHIFT 0 29135 29136 29137 /**************************************************************************** 29138 * RX_X4_Status0 :: PrtpErrorCounter 29139 */ 29140 /* RX_X4_Status0 :: PrtpErrorCounter :: prtp_err_count [15:00] */ 29141 #define RX_X4_STATUS0_PRTPERRORCOUNTER_PRTP_ERR_COUNT_MASK 0xffff 29142 #define RX_X4_STATUS0_PRTPERRORCOUNTER_PRTP_ERR_COUNT_ALIGN 0 29143 #define RX_X4_STATUS0_PRTPERRORCOUNTER_PRTP_ERR_COUNT_BITS 16 29144 #define RX_X4_STATUS0_PRTPERRORCOUNTER_PRTP_ERR_COUNT_SHIFT 0 29145 29146 29147 /**************************************************************************** 29148 * RX_X4_Status0 :: PrtpStatus 29149 */ 29150 /* RX_X4_Status0 :: PrtpStatus :: reserved0 [15:01] */ 29151 #define RX_X4_STATUS0_PRTPSTATUS_RESERVED0_MASK 0xfffe 29152 #define RX_X4_STATUS0_PRTPSTATUS_RESERVED0_ALIGN 0 29153 #define RX_X4_STATUS0_PRTPSTATUS_RESERVED0_BITS 15 29154 #define RX_X4_STATUS0_PRTPSTATUS_RESERVED0_SHIFT 1 29155 29156 /* RX_X4_Status0 :: PrtpStatus :: prtp_lock [00:00] */ 29157 #define RX_X4_STATUS0_PRTPSTATUS_PRTP_LOCK_MASK 0x0001 29158 #define RX_X4_STATUS0_PRTPSTATUS_PRTP_LOCK_ALIGN 0 29159 #define RX_X4_STATUS0_PRTPSTATUS_PRTP_LOCK_BITS 1 29160 #define RX_X4_STATUS0_PRTPSTATUS_PRTP_LOCK_SHIFT 0 29161 29162 29163 /**************************************************************************** 29164 * RX_X4_Status0 :: Cl91_fc_status 29165 */ 29166 /* RX_X4_Status0 :: Cl91_fc_status :: reserved0 [15:13] */ 29167 #define RX_X4_STATUS0_CL91_FC_STATUS_RESERVED0_MASK 0xe000 29168 #define RX_X4_STATUS0_CL91_FC_STATUS_RESERVED0_ALIGN 0 29169 #define RX_X4_STATUS0_CL91_FC_STATUS_RESERVED0_BITS 3 29170 #define RX_X4_STATUS0_CL91_FC_STATUS_RESERVED0_SHIFT 13 29171 29172 /* RX_X4_Status0 :: Cl91_fc_status :: cl91_fc_cw_bad_cnt [12:11] */ 29173 #define RX_X4_STATUS0_CL91_FC_STATUS_CL91_FC_CW_BAD_CNT_MASK 0x1800 29174 #define RX_X4_STATUS0_CL91_FC_STATUS_CL91_FC_CW_BAD_CNT_ALIGN 0 29175 #define RX_X4_STATUS0_CL91_FC_STATUS_CL91_FC_CW_BAD_CNT_BITS 2 29176 #define RX_X4_STATUS0_CL91_FC_STATUS_CL91_FC_CW_BAD_CNT_SHIFT 11 29177 29178 /* RX_X4_Status0 :: Cl91_fc_status :: cl91_fc_cw_good_cnt [10:09] */ 29179 #define RX_X4_STATUS0_CL91_FC_STATUS_CL91_FC_CW_GOOD_CNT_MASK 0x0600 29180 #define RX_X4_STATUS0_CL91_FC_STATUS_CL91_FC_CW_GOOD_CNT_ALIGN 0 29181 #define RX_X4_STATUS0_CL91_FC_STATUS_CL91_FC_CW_GOOD_CNT_BITS 2 29182 #define RX_X4_STATUS0_CL91_FC_STATUS_CL91_FC_CW_GOOD_CNT_SHIFT 9 29183 29184 /* RX_X4_Status0 :: Cl91_fc_status :: cl91_fc_cw_sync_LH [08:08] */ 29185 #define RX_X4_STATUS0_CL91_FC_STATUS_CL91_FC_CW_SYNC_LH_MASK 0x0100 29186 #define RX_X4_STATUS0_CL91_FC_STATUS_CL91_FC_CW_SYNC_LH_ALIGN 0 29187 #define RX_X4_STATUS0_CL91_FC_STATUS_CL91_FC_CW_SYNC_LH_BITS 1 29188 #define RX_X4_STATUS0_CL91_FC_STATUS_CL91_FC_CW_SYNC_LH_SHIFT 8 29189 29190 /* RX_X4_Status0 :: Cl91_fc_status :: cl91_fc_cw_sync_LL [07:07] */ 29191 #define RX_X4_STATUS0_CL91_FC_STATUS_CL91_FC_CW_SYNC_LL_MASK 0x0080 29192 #define RX_X4_STATUS0_CL91_FC_STATUS_CL91_FC_CW_SYNC_LL_ALIGN 0 29193 #define RX_X4_STATUS0_CL91_FC_STATUS_CL91_FC_CW_SYNC_LL_BITS 1 29194 #define RX_X4_STATUS0_CL91_FC_STATUS_CL91_FC_CW_SYNC_LL_SHIFT 7 29195 29196 /* RX_X4_Status0 :: Cl91_fc_status :: cl91_fc_cw_sync_live [06:06] */ 29197 #define RX_X4_STATUS0_CL91_FC_STATUS_CL91_FC_CW_SYNC_LIVE_MASK 0x0040 29198 #define RX_X4_STATUS0_CL91_FC_STATUS_CL91_FC_CW_SYNC_LIVE_ALIGN 0 29199 #define RX_X4_STATUS0_CL91_FC_STATUS_CL91_FC_CW_SYNC_LIVE_BITS 1 29200 #define RX_X4_STATUS0_CL91_FC_STATUS_CL91_FC_CW_SYNC_LIVE_SHIFT 6 29201 29202 /* RX_X4_Status0 :: Cl91_fc_status :: cl91_fc_sync_latched_state [05:02] */ 29203 #define RX_X4_STATUS0_CL91_FC_STATUS_CL91_FC_SYNC_LATCHED_STATE_MASK 0x003c 29204 #define RX_X4_STATUS0_CL91_FC_STATUS_CL91_FC_SYNC_LATCHED_STATE_ALIGN 0 29205 #define RX_X4_STATUS0_CL91_FC_STATUS_CL91_FC_SYNC_LATCHED_STATE_BITS 4 29206 #define RX_X4_STATUS0_CL91_FC_STATUS_CL91_FC_SYNC_LATCHED_STATE_SHIFT 2 29207 29208 /* RX_X4_Status0 :: Cl91_fc_status :: cl91_fc_sync_live_state [01:00] */ 29209 #define RX_X4_STATUS0_CL91_FC_STATUS_CL91_FC_SYNC_LIVE_STATE_MASK 0x0003 29210 #define RX_X4_STATUS0_CL91_FC_STATUS_CL91_FC_SYNC_LIVE_STATE_ALIGN 0 29211 #define RX_X4_STATUS0_CL91_FC_STATUS_CL91_FC_SYNC_LIVE_STATE_BITS 2 29212 #define RX_X4_STATUS0_CL91_FC_STATUS_CL91_FC_SYNC_LIVE_STATE_SHIFT 0 29213 29214 29215 /**************************************************************************** 29216 * RX_X4_Status0 :: ieee_25g_parllel_det_sts 29217 */ 29218 /* RX_X4_Status0 :: ieee_25g_parllel_det_sts :: reserved0 [15:05] */ 29219 #define RX_X4_STATUS0_IEEE_25G_PARLLEL_DET_STS_RESERVED0_MASK 0xffe0 29220 #define RX_X4_STATUS0_IEEE_25G_PARLLEL_DET_STS_RESERVED0_ALIGN 0 29221 #define RX_X4_STATUS0_IEEE_25G_PARLLEL_DET_STS_RESERVED0_BITS 11 29222 #define RX_X4_STATUS0_IEEE_25G_PARLLEL_DET_STS_RESERVED0_SHIFT 5 29223 29224 /* RX_X4_Status0 :: ieee_25g_parllel_det_sts :: resolved_25_mode [04:03] */ 29225 #define RX_X4_STATUS0_IEEE_25G_PARLLEL_DET_STS_RESOLVED_25_MODE_MASK 0x0018 29226 #define RX_X4_STATUS0_IEEE_25G_PARLLEL_DET_STS_RESOLVED_25_MODE_ALIGN 0 29227 #define RX_X4_STATUS0_IEEE_25G_PARLLEL_DET_STS_RESOLVED_25_MODE_BITS 2 29228 #define RX_X4_STATUS0_IEEE_25G_PARLLEL_DET_STS_RESOLVED_25_MODE_SHIFT 3 29229 29230 /* RX_X4_Status0 :: ieee_25g_parllel_det_sts :: msa_ieee_det_state [02:00] */ 29231 #define RX_X4_STATUS0_IEEE_25G_PARLLEL_DET_STS_MSA_IEEE_DET_STATE_MASK 0x0007 29232 #define RX_X4_STATUS0_IEEE_25G_PARLLEL_DET_STS_MSA_IEEE_DET_STATE_ALIGN 0 29233 #define RX_X4_STATUS0_IEEE_25G_PARLLEL_DET_STS_MSA_IEEE_DET_STATE_BITS 3 29234 #define RX_X4_STATUS0_IEEE_25G_PARLLEL_DET_STS_MSA_IEEE_DET_STATE_SHIFT 0 29235 29236 29237 /**************************************************************************** 29238 * TSC_WC4_TSC_USER4_RX_X4_Status1 29239 */ 29240 /**************************************************************************** 29241 * RX_X4_Status1 :: pcs_latched_status_1 29242 */ 29243 /* RX_X4_Status1 :: pcs_latched_status_1 :: reserved0 [15:10] */ 29244 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_RESERVED0_MASK 0xfc00 29245 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_RESERVED0_ALIGN 0 29246 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_RESERVED0_BITS 6 29247 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_RESERVED0_SHIFT 10 29248 29249 /* RX_X4_Status1 :: pcs_latched_status_1 :: LOCAL_FAULT_LH [09:09] */ 29250 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LOCAL_FAULT_LH_MASK 0x0200 29251 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LOCAL_FAULT_LH_ALIGN 0 29252 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LOCAL_FAULT_LH_BITS 1 29253 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LOCAL_FAULT_LH_SHIFT 9 29254 29255 /* RX_X4_Status1 :: pcs_latched_status_1 :: REMOTE_FAULT_LH [08:08] */ 29256 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_REMOTE_FAULT_LH_MASK 0x0100 29257 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_REMOTE_FAULT_LH_ALIGN 0 29258 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_REMOTE_FAULT_LH_BITS 1 29259 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_REMOTE_FAULT_LH_SHIFT 8 29260 29261 /* RX_X4_Status1 :: pcs_latched_status_1 :: LINK_INTERRUPT_LH [07:07] */ 29262 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LINK_INTERRUPT_LH_MASK 0x0080 29263 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LINK_INTERRUPT_LH_ALIGN 0 29264 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LINK_INTERRUPT_LH_BITS 1 29265 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LINK_INTERRUPT_LH_SHIFT 7 29266 29267 /* RX_X4_Status1 :: pcs_latched_status_1 :: LPI_RECEIVED_LH [06:06] */ 29268 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LPI_RECEIVED_LH_MASK 0x0040 29269 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LPI_RECEIVED_LH_ALIGN 0 29270 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LPI_RECEIVED_LH_BITS 1 29271 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LPI_RECEIVED_LH_SHIFT 6 29272 29273 /* RX_X4_Status1 :: pcs_latched_status_1 :: HI_BER_LH [05:05] */ 29274 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_HI_BER_LH_MASK 0x0020 29275 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_HI_BER_LH_ALIGN 0 29276 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_HI_BER_LH_BITS 1 29277 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_HI_BER_LH_SHIFT 5 29278 29279 /* RX_X4_Status1 :: pcs_latched_status_1 :: HI_BER_LL [04:04] */ 29280 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_HI_BER_LL_MASK 0x0010 29281 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_HI_BER_LL_ALIGN 0 29282 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_HI_BER_LL_BITS 1 29283 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_HI_BER_LL_SHIFT 4 29284 29285 /* RX_X4_Status1 :: pcs_latched_status_1 :: LINK_STATUS_LH [03:03] */ 29286 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LINK_STATUS_LH_MASK 0x0008 29287 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LINK_STATUS_LH_ALIGN 0 29288 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LINK_STATUS_LH_BITS 1 29289 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LINK_STATUS_LH_SHIFT 3 29290 29291 /* RX_X4_Status1 :: pcs_latched_status_1 :: LINK_STATUS_LL [02:02] */ 29292 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LINK_STATUS_LL_MASK 0x0004 29293 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LINK_STATUS_LL_ALIGN 0 29294 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LINK_STATUS_LL_BITS 1 29295 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LINK_STATUS_LL_SHIFT 2 29296 29297 /* RX_X4_Status1 :: pcs_latched_status_1 :: DESKEW_STATUS_LH [01:01] */ 29298 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_DESKEW_STATUS_LH_MASK 0x0002 29299 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_DESKEW_STATUS_LH_ALIGN 0 29300 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_DESKEW_STATUS_LH_BITS 1 29301 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_DESKEW_STATUS_LH_SHIFT 1 29302 29303 /* RX_X4_Status1 :: pcs_latched_status_1 :: DESKEW_STATUS_LL [00:00] */ 29304 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_DESKEW_STATUS_LL_MASK 0x0001 29305 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_DESKEW_STATUS_LL_ALIGN 0 29306 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_DESKEW_STATUS_LL_BITS 1 29307 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_DESKEW_STATUS_LL_SHIFT 0 29308 29309 29310 /**************************************************************************** 29311 * RX_X4_Status1 :: pcs_live_status_1 29312 */ 29313 /* RX_X4_Status1 :: pcs_live_status_1 :: reserved0 [15:07] */ 29314 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_RESERVED0_MASK 0xff80 29315 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_RESERVED0_ALIGN 0 29316 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_RESERVED0_BITS 9 29317 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_RESERVED0_SHIFT 7 29318 29319 /* RX_X4_Status1 :: pcs_live_status_1 :: LOCAL_FAULT [06:06] */ 29320 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_LOCAL_FAULT_MASK 0x0040 29321 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_LOCAL_FAULT_ALIGN 0 29322 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_LOCAL_FAULT_BITS 1 29323 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_LOCAL_FAULT_SHIFT 6 29324 29325 /* RX_X4_Status1 :: pcs_live_status_1 :: REMOTE_FAULT [05:05] */ 29326 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_REMOTE_FAULT_MASK 0x0020 29327 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_REMOTE_FAULT_ALIGN 0 29328 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_REMOTE_FAULT_BITS 1 29329 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_REMOTE_FAULT_SHIFT 5 29330 29331 /* RX_X4_Status1 :: pcs_live_status_1 :: LINK_INTERRUPT [04:04] */ 29332 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_LINK_INTERRUPT_MASK 0x0010 29333 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_LINK_INTERRUPT_ALIGN 0 29334 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_LINK_INTERRUPT_BITS 1 29335 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_LINK_INTERRUPT_SHIFT 4 29336 29337 /* RX_X4_Status1 :: pcs_live_status_1 :: LPI_RECEIVED [03:03] */ 29338 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_LPI_RECEIVED_MASK 0x0008 29339 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_LPI_RECEIVED_ALIGN 0 29340 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_LPI_RECEIVED_BITS 1 29341 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_LPI_RECEIVED_SHIFT 3 29342 29343 /* RX_X4_Status1 :: pcs_live_status_1 :: HI_BER [02:02] */ 29344 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_HI_BER_MASK 0x0004 29345 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_HI_BER_ALIGN 0 29346 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_HI_BER_BITS 1 29347 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_HI_BER_SHIFT 2 29348 29349 /* RX_X4_Status1 :: pcs_live_status_1 :: LINK_STATUS [01:01] */ 29350 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_LINK_STATUS_MASK 0x0002 29351 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_LINK_STATUS_ALIGN 0 29352 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_LINK_STATUS_BITS 1 29353 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_LINK_STATUS_SHIFT 1 29354 29355 /* RX_X4_Status1 :: pcs_live_status_1 :: DESKEW_STATUS [00:00] */ 29356 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_DESKEW_STATUS_MASK 0x0001 29357 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_DESKEW_STATUS_ALIGN 0 29358 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_DESKEW_STATUS_BITS 1 29359 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_DESKEW_STATUS_SHIFT 0 29360 29361 29362 /**************************************************************************** 29363 * RX_X4_Status1 :: decode_status_0 29364 */ 29365 /* RX_X4_Status1 :: decode_status_0 :: reserved0 [15:05] */ 29366 #define RX_X4_STATUS1_DECODE_STATUS_0_RESERVED0_MASK 0xffe0 29367 #define RX_X4_STATUS1_DECODE_STATUS_0_RESERVED0_ALIGN 0 29368 #define RX_X4_STATUS1_DECODE_STATUS_0_RESERVED0_BITS 11 29369 #define RX_X4_STATUS1_DECODE_STATUS_0_RESERVED0_SHIFT 5 29370 29371 /* RX_X4_Status1 :: decode_status_0 :: bermon_current_state [04:00] */ 29372 #define RX_X4_STATUS1_DECODE_STATUS_0_BERMON_CURRENT_STATE_MASK 0x001f 29373 #define RX_X4_STATUS1_DECODE_STATUS_0_BERMON_CURRENT_STATE_ALIGN 0 29374 #define RX_X4_STATUS1_DECODE_STATUS_0_BERMON_CURRENT_STATE_BITS 5 29375 #define RX_X4_STATUS1_DECODE_STATUS_0_BERMON_CURRENT_STATE_SHIFT 0 29376 #define RX_X4_STATUS1_DECODE_STATUS_0_BERMON_CURRENT_STATE_HI_BER 4 29377 #define RX_X4_STATUS1_DECODE_STATUS_0_BERMON_CURRENT_STATE_GOOD_BER 3 29378 #define RX_X4_STATUS1_DECODE_STATUS_0_BERMON_CURRENT_STATE_BER_TEST_SH 2 29379 #define RX_X4_STATUS1_DECODE_STATUS_0_BERMON_CURRENT_STATE_START_TIMER 1 29380 #define RX_X4_STATUS1_DECODE_STATUS_0_BERMON_CURRENT_STATE_BER_MT_INIT 0 29381 29382 29383 /**************************************************************************** 29384 * RX_X4_Status1 :: decode_status_1 29385 */ 29386 /* RX_X4_Status1 :: decode_status_1 :: reserved0 [15:13] */ 29387 #define RX_X4_STATUS1_DECODE_STATUS_1_RESERVED0_MASK 0xe000 29388 #define RX_X4_STATUS1_DECODE_STATUS_1_RESERVED0_ALIGN 0 29389 #define RX_X4_STATUS1_DECODE_STATUS_1_RESERVED0_BITS 3 29390 #define RX_X4_STATUS1_DECODE_STATUS_1_RESERVED0_SHIFT 13 29391 29392 /* RX_X4_Status1 :: decode_status_1 :: cl49_rxsm_history_state [12:05] */ 29393 #define RX_X4_STATUS1_DECODE_STATUS_1_CL49_RXSM_HISTORY_STATE_MASK 0x1fe0 29394 #define RX_X4_STATUS1_DECODE_STATUS_1_CL49_RXSM_HISTORY_STATE_ALIGN 0 29395 #define RX_X4_STATUS1_DECODE_STATUS_1_CL49_RXSM_HISTORY_STATE_BITS 8 29396 #define RX_X4_STATUS1_DECODE_STATUS_1_CL49_RXSM_HISTORY_STATE_SHIFT 5 29397 #define RX_X4_STATUS1_DECODE_STATUS_1_CL49_RXSM_HISTORY_STATE_RX_HIG_END 128 29398 #define RX_X4_STATUS1_DECODE_STATUS_1_CL49_RXSM_HISTORY_STATE_RX_HIG_START 64 29399 #define RX_X4_STATUS1_DECODE_STATUS_1_CL49_RXSM_HISTORY_STATE_RX_LI 32 29400 #define RX_X4_STATUS1_DECODE_STATUS_1_CL49_RXSM_HISTORY_STATE_RX_E 16 29401 #define RX_X4_STATUS1_DECODE_STATUS_1_CL49_RXSM_HISTORY_STATE_RX_T 8 29402 #define RX_X4_STATUS1_DECODE_STATUS_1_CL49_RXSM_HISTORY_STATE_RX_D 4 29403 #define RX_X4_STATUS1_DECODE_STATUS_1_CL49_RXSM_HISTORY_STATE_RX_C 2 29404 #define RX_X4_STATUS1_DECODE_STATUS_1_CL49_RXSM_HISTORY_STATE_RX_INIT 1 29405 29406 /* RX_X4_Status1 :: decode_status_1 :: bermon_history_state [04:00] */ 29407 #define RX_X4_STATUS1_DECODE_STATUS_1_BERMON_HISTORY_STATE_MASK 0x001f 29408 #define RX_X4_STATUS1_DECODE_STATUS_1_BERMON_HISTORY_STATE_ALIGN 0 29409 #define RX_X4_STATUS1_DECODE_STATUS_1_BERMON_HISTORY_STATE_BITS 5 29410 #define RX_X4_STATUS1_DECODE_STATUS_1_BERMON_HISTORY_STATE_SHIFT 0 29411 #define RX_X4_STATUS1_DECODE_STATUS_1_BERMON_HISTORY_STATE_HI_BER 4 29412 #define RX_X4_STATUS1_DECODE_STATUS_1_BERMON_HISTORY_STATE_GOOD_BER 3 29413 #define RX_X4_STATUS1_DECODE_STATUS_1_BERMON_HISTORY_STATE_BER_TEST_SH 2 29414 #define RX_X4_STATUS1_DECODE_STATUS_1_BERMON_HISTORY_STATE_START_TIMER 1 29415 #define RX_X4_STATUS1_DECODE_STATUS_1_BERMON_HISTORY_STATE_BER_MT_INIT 0 29416 29417 29418 /**************************************************************************** 29419 * RX_X4_Status1 :: decode_status_2 29420 */ 29421 /* RX_X4_Status1 :: decode_status_2 :: reserved0 [15:12] */ 29422 #define RX_X4_STATUS1_DECODE_STATUS_2_RESERVED0_MASK 0xf000 29423 #define RX_X4_STATUS1_DECODE_STATUS_2_RESERVED0_ALIGN 0 29424 #define RX_X4_STATUS1_DECODE_STATUS_2_RESERVED0_BITS 4 29425 #define RX_X4_STATUS1_DECODE_STATUS_2_RESERVED0_SHIFT 12 29426 29427 /* RX_X4_Status1 :: decode_status_2 :: cl49_r_type_coded [11:08] */ 29428 #define RX_X4_STATUS1_DECODE_STATUS_2_CL49_R_TYPE_CODED_MASK 0x0f00 29429 #define RX_X4_STATUS1_DECODE_STATUS_2_CL49_R_TYPE_CODED_ALIGN 0 29430 #define RX_X4_STATUS1_DECODE_STATUS_2_CL49_R_TYPE_CODED_BITS 4 29431 #define RX_X4_STATUS1_DECODE_STATUS_2_CL49_R_TYPE_CODED_SHIFT 8 29432 29433 /* RX_X4_Status1 :: decode_status_2 :: cl49_rxsm_current_state [07:00] */ 29434 #define RX_X4_STATUS1_DECODE_STATUS_2_CL49_RXSM_CURRENT_STATE_MASK 0x00ff 29435 #define RX_X4_STATUS1_DECODE_STATUS_2_CL49_RXSM_CURRENT_STATE_ALIGN 0 29436 #define RX_X4_STATUS1_DECODE_STATUS_2_CL49_RXSM_CURRENT_STATE_BITS 8 29437 #define RX_X4_STATUS1_DECODE_STATUS_2_CL49_RXSM_CURRENT_STATE_SHIFT 0 29438 #define RX_X4_STATUS1_DECODE_STATUS_2_CL49_RXSM_CURRENT_STATE_RX_HIG_END 128 29439 #define RX_X4_STATUS1_DECODE_STATUS_2_CL49_RXSM_CURRENT_STATE_RX_HIG_START 64 29440 #define RX_X4_STATUS1_DECODE_STATUS_2_CL49_RXSM_CURRENT_STATE_RX_LI 32 29441 #define RX_X4_STATUS1_DECODE_STATUS_2_CL49_RXSM_CURRENT_STATE_RX_E 16 29442 #define RX_X4_STATUS1_DECODE_STATUS_2_CL49_RXSM_CURRENT_STATE_RX_T 8 29443 #define RX_X4_STATUS1_DECODE_STATUS_2_CL49_RXSM_CURRENT_STATE_RX_D 4 29444 #define RX_X4_STATUS1_DECODE_STATUS_2_CL49_RXSM_CURRENT_STATE_RX_C 2 29445 #define RX_X4_STATUS1_DECODE_STATUS_2_CL49_RXSM_CURRENT_STATE_RX_INIT 1 29446 29447 29448 /**************************************************************************** 29449 * RX_X4_Status1 :: decode_status_3 29450 */ 29451 /* RX_X4_Status1 :: decode_status_3 :: reserved0 [15:14] */ 29452 #define RX_X4_STATUS1_DECODE_STATUS_3_RESERVED0_MASK 0xc000 29453 #define RX_X4_STATUS1_DECODE_STATUS_3_RESERVED0_ALIGN 0 29454 #define RX_X4_STATUS1_DECODE_STATUS_3_RESERVED0_BITS 2 29455 #define RX_X4_STATUS1_DECODE_STATUS_3_RESERVED0_SHIFT 14 29456 29457 /* RX_X4_Status1 :: decode_status_3 :: cl49_ber_count [13:08] */ 29458 #define RX_X4_STATUS1_DECODE_STATUS_3_CL49_BER_COUNT_MASK 0x3f00 29459 #define RX_X4_STATUS1_DECODE_STATUS_3_CL49_BER_COUNT_ALIGN 0 29460 #define RX_X4_STATUS1_DECODE_STATUS_3_CL49_BER_COUNT_BITS 6 29461 #define RX_X4_STATUS1_DECODE_STATUS_3_CL49_BER_COUNT_SHIFT 8 29462 29463 /* RX_X4_Status1 :: decode_status_3 :: ieee_errored_blocks [07:00] */ 29464 #define RX_X4_STATUS1_DECODE_STATUS_3_IEEE_ERRORED_BLOCKS_MASK 0x00ff 29465 #define RX_X4_STATUS1_DECODE_STATUS_3_IEEE_ERRORED_BLOCKS_ALIGN 0 29466 #define RX_X4_STATUS1_DECODE_STATUS_3_IEEE_ERRORED_BLOCKS_BITS 8 29467 #define RX_X4_STATUS1_DECODE_STATUS_3_IEEE_ERRORED_BLOCKS_SHIFT 0 29468 29469 29470 /**************************************************************************** 29471 * RX_X4_Status1 :: cl36rx_syncacq_status_0 29472 */ 29473 /* RX_X4_Status1 :: cl36rx_syncacq_status_0 :: reserved0 [15:04] */ 29474 #define RX_X4_STATUS1_CL36RX_SYNCACQ_STATUS_0_RESERVED0_MASK 0xfff0 29475 #define RX_X4_STATUS1_CL36RX_SYNCACQ_STATUS_0_RESERVED0_ALIGN 0 29476 #define RX_X4_STATUS1_CL36RX_SYNCACQ_STATUS_0_RESERVED0_BITS 12 29477 #define RX_X4_STATUS1_CL36RX_SYNCACQ_STATUS_0_RESERVED0_SHIFT 4 29478 29479 /* RX_X4_Status1 :: cl36rx_syncacq_status_0 :: cl36rx_syncacq_state_coded_per_ln [03:00] */ 29480 #define RX_X4_STATUS1_CL36RX_SYNCACQ_STATUS_0_CL36RX_SYNCACQ_STATE_CODED_PER_LN_MASK 0x000f 29481 #define RX_X4_STATUS1_CL36RX_SYNCACQ_STATUS_0_CL36RX_SYNCACQ_STATE_CODED_PER_LN_ALIGN 0 29482 #define RX_X4_STATUS1_CL36RX_SYNCACQ_STATUS_0_CL36RX_SYNCACQ_STATE_CODED_PER_LN_BITS 4 29483 #define RX_X4_STATUS1_CL36RX_SYNCACQ_STATUS_0_CL36RX_SYNCACQ_STATE_CODED_PER_LN_SHIFT 0 29484 29485 29486 /**************************************************************************** 29487 * RX_X4_Status1 :: cl36rx_syncacq_status_1 29488 */ 29489 /* RX_X4_Status1 :: cl36rx_syncacq_status_1 :: reserved0 [15:13] */ 29490 #define RX_X4_STATUS1_CL36RX_SYNCACQ_STATUS_1_RESERVED0_MASK 0xe000 29491 #define RX_X4_STATUS1_CL36RX_SYNCACQ_STATUS_1_RESERVED0_ALIGN 0 29492 #define RX_X4_STATUS1_CL36RX_SYNCACQ_STATUS_1_RESERVED0_BITS 3 29493 #define RX_X4_STATUS1_CL36RX_SYNCACQ_STATUS_1_RESERVED0_SHIFT 13 29494 29495 /* RX_X4_Status1 :: cl36rx_syncacq_status_1 :: cl36rx_syncacq_his_state_per_ln [12:00] */ 29496 #define RX_X4_STATUS1_CL36RX_SYNCACQ_STATUS_1_CL36RX_SYNCACQ_HIS_STATE_PER_LN_MASK 0x1fff 29497 #define RX_X4_STATUS1_CL36RX_SYNCACQ_STATUS_1_CL36RX_SYNCACQ_HIS_STATE_PER_LN_ALIGN 0 29498 #define RX_X4_STATUS1_CL36RX_SYNCACQ_STATUS_1_CL36RX_SYNCACQ_HIS_STATE_PER_LN_BITS 13 29499 #define RX_X4_STATUS1_CL36RX_SYNCACQ_STATUS_1_CL36RX_SYNCACQ_HIS_STATE_PER_LN_SHIFT 0 29500 29501 29502 /**************************************************************************** 29503 * RX_X4_Status1 :: cl36rx_bercount 29504 */ 29505 /* RX_X4_Status1 :: cl36rx_bercount :: reserved0 [15:08] */ 29506 #define RX_X4_STATUS1_CL36RX_BERCOUNT_RESERVED0_MASK 0xff00 29507 #define RX_X4_STATUS1_CL36RX_BERCOUNT_RESERVED0_ALIGN 0 29508 #define RX_X4_STATUS1_CL36RX_BERCOUNT_RESERVED0_BITS 8 29509 #define RX_X4_STATUS1_CL36RX_BERCOUNT_RESERVED0_SHIFT 8 29510 29511 /* RX_X4_Status1 :: cl36rx_bercount :: cl36rx_BER_count_per_ln [07:00] */ 29512 #define RX_X4_STATUS1_CL36RX_BERCOUNT_CL36RX_BER_COUNT_PER_LN_MASK 0x00ff 29513 #define RX_X4_STATUS1_CL36RX_BERCOUNT_CL36RX_BER_COUNT_PER_LN_ALIGN 0 29514 #define RX_X4_STATUS1_CL36RX_BERCOUNT_CL36RX_BER_COUNT_PER_LN_BITS 8 29515 #define RX_X4_STATUS1_CL36RX_BERCOUNT_CL36RX_BER_COUNT_PER_LN_SHIFT 0 29516 29517 29518 /**************************************************************************** 29519 * TSC_WC4_TSC_USER4_RX_X4_Status2 29520 */ 29521 /**************************************************************************** 29522 * RX_X4_Status2 :: cl82_rx_am_latched_status_psll_0 29523 */ 29524 /* RX_X4_Status2 :: cl82_rx_am_latched_status_psll_0 :: reserved0 [15:11] */ 29525 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_0_RESERVED0_MASK 0xf800 29526 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_0_RESERVED0_ALIGN 0 29527 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_0_RESERVED0_BITS 5 29528 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_0_RESERVED0_SHIFT 11 29529 29530 /* RX_X4_Status2 :: cl82_rx_am_latched_status_psll_0 :: amrkr_spacing_err_latch_mux_psll_0 [10:10] */ 29531 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_0_AMRKR_SPACING_ERR_LATCH_MUX_PSLL_0_MASK 0x0400 29532 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_0_AMRKR_SPACING_ERR_LATCH_MUX_PSLL_0_ALIGN 0 29533 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_0_AMRKR_SPACING_ERR_LATCH_MUX_PSLL_0_BITS 1 29534 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_0_AMRKR_SPACING_ERR_LATCH_MUX_PSLL_0_SHIFT 10 29535 29536 /* RX_X4_Status2 :: cl82_rx_am_latched_status_psll_0 :: am_lock_his_state_psll_0 [09:00] */ 29537 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_0_AM_LOCK_HIS_STATE_PSLL_0_MASK 0x03ff 29538 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_0_AM_LOCK_HIS_STATE_PSLL_0_ALIGN 0 29539 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_0_AM_LOCK_HIS_STATE_PSLL_0_BITS 10 29540 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_0_AM_LOCK_HIS_STATE_PSLL_0_SHIFT 0 29541 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_0_AM_LOCK_HIS_STATE_PSLL_0_INVALID_AM 512 29542 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_0_AM_LOCK_HIS_STATE_PSLL_0_GOOD_AM 256 29543 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_0_AM_LOCK_HIS_STATE_PSLL_0_COMP_AM 128 29544 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_0_AM_LOCK_HIS_STATE_PSLL_0_TIMER_2 64 29545 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_0_AM_LOCK_HIS_STATE_PSLL_0_AM_2_GOOD 32 29546 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_0_AM_LOCK_HIS_STATE_PSLL_0_COMP_2ND 16 29547 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_0_AM_LOCK_HIS_STATE_PSLL_0_TIMER_1 8 29548 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_0_AM_LOCK_HIS_STATE_PSLL_0_FIND_1ST 4 29549 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_0_AM_LOCK_HIS_STATE_PSLL_0_AM_RESET_CNT 2 29550 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_0_AM_LOCK_HIS_STATE_PSLL_0_AM_LOCK_INIT 1 29551 29552 29553 /**************************************************************************** 29554 * RX_X4_Status2 :: cl82_rx_am_latched_status_psll_1 29555 */ 29556 /* RX_X4_Status2 :: cl82_rx_am_latched_status_psll_1 :: reserved0 [15:11] */ 29557 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_1_RESERVED0_MASK 0xf800 29558 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_1_RESERVED0_ALIGN 0 29559 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_1_RESERVED0_BITS 5 29560 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_1_RESERVED0_SHIFT 11 29561 29562 /* RX_X4_Status2 :: cl82_rx_am_latched_status_psll_1 :: amrkr_spacing_err_latch_mux_psll_1 [10:10] */ 29563 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_1_AMRKR_SPACING_ERR_LATCH_MUX_PSLL_1_MASK 0x0400 29564 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_1_AMRKR_SPACING_ERR_LATCH_MUX_PSLL_1_ALIGN 0 29565 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_1_AMRKR_SPACING_ERR_LATCH_MUX_PSLL_1_BITS 1 29566 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_1_AMRKR_SPACING_ERR_LATCH_MUX_PSLL_1_SHIFT 10 29567 29568 /* RX_X4_Status2 :: cl82_rx_am_latched_status_psll_1 :: am_lock_his_state_psll_1 [09:00] */ 29569 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_1_AM_LOCK_HIS_STATE_PSLL_1_MASK 0x03ff 29570 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_1_AM_LOCK_HIS_STATE_PSLL_1_ALIGN 0 29571 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_1_AM_LOCK_HIS_STATE_PSLL_1_BITS 10 29572 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_1_AM_LOCK_HIS_STATE_PSLL_1_SHIFT 0 29573 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_1_AM_LOCK_HIS_STATE_PSLL_1_INVALID_AM 512 29574 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_1_AM_LOCK_HIS_STATE_PSLL_1_GOOD_AM 256 29575 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_1_AM_LOCK_HIS_STATE_PSLL_1_COMP_AM 128 29576 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_1_AM_LOCK_HIS_STATE_PSLL_1_TIMER_2 64 29577 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_1_AM_LOCK_HIS_STATE_PSLL_1_AM_2_GOOD 32 29578 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_1_AM_LOCK_HIS_STATE_PSLL_1_COMP_2ND 16 29579 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_1_AM_LOCK_HIS_STATE_PSLL_1_TIMER_1 8 29580 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_1_AM_LOCK_HIS_STATE_PSLL_1_FIND_1ST 4 29581 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_1_AM_LOCK_HIS_STATE_PSLL_1_AM_RESET_CNT 2 29582 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_1_AM_LOCK_HIS_STATE_PSLL_1_AM_LOCK_INIT 1 29583 29584 29585 /**************************************************************************** 29586 * RX_X4_Status2 :: cl82_rx_am_latched_status_psll_2 29587 */ 29588 /* RX_X4_Status2 :: cl82_rx_am_latched_status_psll_2 :: reserved0 [15:11] */ 29589 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_2_RESERVED0_MASK 0xf800 29590 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_2_RESERVED0_ALIGN 0 29591 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_2_RESERVED0_BITS 5 29592 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_2_RESERVED0_SHIFT 11 29593 29594 /* RX_X4_Status2 :: cl82_rx_am_latched_status_psll_2 :: amrkr_spacing_err_latch_mux_psll_2 [10:10] */ 29595 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_2_AMRKR_SPACING_ERR_LATCH_MUX_PSLL_2_MASK 0x0400 29596 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_2_AMRKR_SPACING_ERR_LATCH_MUX_PSLL_2_ALIGN 0 29597 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_2_AMRKR_SPACING_ERR_LATCH_MUX_PSLL_2_BITS 1 29598 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_2_AMRKR_SPACING_ERR_LATCH_MUX_PSLL_2_SHIFT 10 29599 29600 /* RX_X4_Status2 :: cl82_rx_am_latched_status_psll_2 :: am_lock_his_state_psll_2 [09:00] */ 29601 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_2_AM_LOCK_HIS_STATE_PSLL_2_MASK 0x03ff 29602 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_2_AM_LOCK_HIS_STATE_PSLL_2_ALIGN 0 29603 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_2_AM_LOCK_HIS_STATE_PSLL_2_BITS 10 29604 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_2_AM_LOCK_HIS_STATE_PSLL_2_SHIFT 0 29605 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_2_AM_LOCK_HIS_STATE_PSLL_2_INVALID_AM 512 29606 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_2_AM_LOCK_HIS_STATE_PSLL_2_GOOD_AM 256 29607 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_2_AM_LOCK_HIS_STATE_PSLL_2_COMP_AM 128 29608 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_2_AM_LOCK_HIS_STATE_PSLL_2_TIMER_2 64 29609 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_2_AM_LOCK_HIS_STATE_PSLL_2_AM_2_GOOD 32 29610 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_2_AM_LOCK_HIS_STATE_PSLL_2_COMP_2ND 16 29611 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_2_AM_LOCK_HIS_STATE_PSLL_2_TIMER_1 8 29612 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_2_AM_LOCK_HIS_STATE_PSLL_2_FIND_1ST 4 29613 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_2_AM_LOCK_HIS_STATE_PSLL_2_AM_RESET_CNT 2 29614 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_2_AM_LOCK_HIS_STATE_PSLL_2_AM_LOCK_INIT 1 29615 29616 29617 /**************************************************************************** 29618 * RX_X4_Status2 :: cl82_rx_am_latched_status_psll_3 29619 */ 29620 /* RX_X4_Status2 :: cl82_rx_am_latched_status_psll_3 :: reserved0 [15:11] */ 29621 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_3_RESERVED0_MASK 0xf800 29622 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_3_RESERVED0_ALIGN 0 29623 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_3_RESERVED0_BITS 5 29624 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_3_RESERVED0_SHIFT 11 29625 29626 /* RX_X4_Status2 :: cl82_rx_am_latched_status_psll_3 :: amrkr_spacing_err_latch_mux_psll_3 [10:10] */ 29627 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_3_AMRKR_SPACING_ERR_LATCH_MUX_PSLL_3_MASK 0x0400 29628 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_3_AMRKR_SPACING_ERR_LATCH_MUX_PSLL_3_ALIGN 0 29629 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_3_AMRKR_SPACING_ERR_LATCH_MUX_PSLL_3_BITS 1 29630 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_3_AMRKR_SPACING_ERR_LATCH_MUX_PSLL_3_SHIFT 10 29631 29632 /* RX_X4_Status2 :: cl82_rx_am_latched_status_psll_3 :: am_lock_his_state_psll_3 [09:00] */ 29633 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_3_AM_LOCK_HIS_STATE_PSLL_3_MASK 0x03ff 29634 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_3_AM_LOCK_HIS_STATE_PSLL_3_ALIGN 0 29635 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_3_AM_LOCK_HIS_STATE_PSLL_3_BITS 10 29636 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_3_AM_LOCK_HIS_STATE_PSLL_3_SHIFT 0 29637 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_3_AM_LOCK_HIS_STATE_PSLL_3_INVALID_AM 512 29638 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_3_AM_LOCK_HIS_STATE_PSLL_3_GOOD_AM 256 29639 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_3_AM_LOCK_HIS_STATE_PSLL_3_COMP_AM 128 29640 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_3_AM_LOCK_HIS_STATE_PSLL_3_TIMER_2 64 29641 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_3_AM_LOCK_HIS_STATE_PSLL_3_AM_2_GOOD 32 29642 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_3_AM_LOCK_HIS_STATE_PSLL_3_COMP_2ND 16 29643 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_3_AM_LOCK_HIS_STATE_PSLL_3_TIMER_1 8 29644 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_3_AM_LOCK_HIS_STATE_PSLL_3_FIND_1ST 4 29645 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_3_AM_LOCK_HIS_STATE_PSLL_3_AM_RESET_CNT 2 29646 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_3_AM_LOCK_HIS_STATE_PSLL_3_AM_LOCK_INIT 1 29647 29648 29649 /**************************************************************************** 29650 * RX_X4_Status2 :: cl82_rx_am_latched_status_psll_4 29651 */ 29652 /* RX_X4_Status2 :: cl82_rx_am_latched_status_psll_4 :: reserved0 [15:11] */ 29653 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_4_RESERVED0_MASK 0xf800 29654 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_4_RESERVED0_ALIGN 0 29655 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_4_RESERVED0_BITS 5 29656 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_4_RESERVED0_SHIFT 11 29657 29658 /* RX_X4_Status2 :: cl82_rx_am_latched_status_psll_4 :: amrkr_spacing_err_latch_mux_psll_4 [10:10] */ 29659 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_4_AMRKR_SPACING_ERR_LATCH_MUX_PSLL_4_MASK 0x0400 29660 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_4_AMRKR_SPACING_ERR_LATCH_MUX_PSLL_4_ALIGN 0 29661 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_4_AMRKR_SPACING_ERR_LATCH_MUX_PSLL_4_BITS 1 29662 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_4_AMRKR_SPACING_ERR_LATCH_MUX_PSLL_4_SHIFT 10 29663 29664 /* RX_X4_Status2 :: cl82_rx_am_latched_status_psll_4 :: am_lock_his_state_psll_4 [09:00] */ 29665 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_4_AM_LOCK_HIS_STATE_PSLL_4_MASK 0x03ff 29666 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_4_AM_LOCK_HIS_STATE_PSLL_4_ALIGN 0 29667 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_4_AM_LOCK_HIS_STATE_PSLL_4_BITS 10 29668 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_4_AM_LOCK_HIS_STATE_PSLL_4_SHIFT 0 29669 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_4_AM_LOCK_HIS_STATE_PSLL_4_INVALID_AM 512 29670 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_4_AM_LOCK_HIS_STATE_PSLL_4_GOOD_AM 256 29671 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_4_AM_LOCK_HIS_STATE_PSLL_4_COMP_AM 128 29672 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_4_AM_LOCK_HIS_STATE_PSLL_4_TIMER_2 64 29673 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_4_AM_LOCK_HIS_STATE_PSLL_4_AM_2_GOOD 32 29674 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_4_AM_LOCK_HIS_STATE_PSLL_4_COMP_2ND 16 29675 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_4_AM_LOCK_HIS_STATE_PSLL_4_TIMER_1 8 29676 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_4_AM_LOCK_HIS_STATE_PSLL_4_FIND_1ST 4 29677 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_4_AM_LOCK_HIS_STATE_PSLL_4_AM_RESET_CNT 2 29678 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_4_AM_LOCK_HIS_STATE_PSLL_4_AM_LOCK_INIT 1 29679 29680 29681 /**************************************************************************** 29682 * RX_X4_Status2 :: cl82_rx_am_live_status_psll_0 29683 */ 29684 /* RX_X4_Status2 :: cl82_rx_am_live_status_psll_0 :: reserved0 [15:10] */ 29685 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_0_RESERVED0_MASK 0xfc00 29686 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_0_RESERVED0_ALIGN 0 29687 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_0_RESERVED0_BITS 6 29688 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_0_RESERVED0_SHIFT 10 29689 29690 /* RX_X4_Status2 :: cl82_rx_am_live_status_psll_0 :: am_lock_state_psll_0 [09:00] */ 29691 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_0_AM_LOCK_STATE_PSLL_0_MASK 0x03ff 29692 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_0_AM_LOCK_STATE_PSLL_0_ALIGN 0 29693 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_0_AM_LOCK_STATE_PSLL_0_BITS 10 29694 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_0_AM_LOCK_STATE_PSLL_0_SHIFT 0 29695 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_0_AM_LOCK_STATE_PSLL_0_INVALID_AM 512 29696 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_0_AM_LOCK_STATE_PSLL_0_GOOD_AM 256 29697 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_0_AM_LOCK_STATE_PSLL_0_COMP_AM 128 29698 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_0_AM_LOCK_STATE_PSLL_0_TIMER_2 64 29699 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_0_AM_LOCK_STATE_PSLL_0_AM_2_GOOD 32 29700 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_0_AM_LOCK_STATE_PSLL_0_COMP_2ND 16 29701 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_0_AM_LOCK_STATE_PSLL_0_TIMER_1 8 29702 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_0_AM_LOCK_STATE_PSLL_0_FIND_1ST 4 29703 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_0_AM_LOCK_STATE_PSLL_0_AM_RESET_CNT 2 29704 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_0_AM_LOCK_STATE_PSLL_0_AM_LOCK_INIT 1 29705 29706 29707 /**************************************************************************** 29708 * RX_X4_Status2 :: cl82_rx_am_live_status_psll_1 29709 */ 29710 /* RX_X4_Status2 :: cl82_rx_am_live_status_psll_1 :: reserved0 [15:10] */ 29711 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_1_RESERVED0_MASK 0xfc00 29712 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_1_RESERVED0_ALIGN 0 29713 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_1_RESERVED0_BITS 6 29714 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_1_RESERVED0_SHIFT 10 29715 29716 /* RX_X4_Status2 :: cl82_rx_am_live_status_psll_1 :: am_lock_state_psll_1 [09:00] */ 29717 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_1_AM_LOCK_STATE_PSLL_1_MASK 0x03ff 29718 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_1_AM_LOCK_STATE_PSLL_1_ALIGN 0 29719 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_1_AM_LOCK_STATE_PSLL_1_BITS 10 29720 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_1_AM_LOCK_STATE_PSLL_1_SHIFT 0 29721 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_1_AM_LOCK_STATE_PSLL_1_INVALID_AM 512 29722 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_1_AM_LOCK_STATE_PSLL_1_GOOD_AM 256 29723 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_1_AM_LOCK_STATE_PSLL_1_COMP_AM 128 29724 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_1_AM_LOCK_STATE_PSLL_1_TIMER_2 64 29725 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_1_AM_LOCK_STATE_PSLL_1_AM_2_GOOD 32 29726 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_1_AM_LOCK_STATE_PSLL_1_COMP_2ND 16 29727 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_1_AM_LOCK_STATE_PSLL_1_TIMER_1 8 29728 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_1_AM_LOCK_STATE_PSLL_1_FIND_1ST 4 29729 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_1_AM_LOCK_STATE_PSLL_1_AM_RESET_CNT 2 29730 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_1_AM_LOCK_STATE_PSLL_1_AM_LOCK_INIT 1 29731 29732 29733 /**************************************************************************** 29734 * RX_X4_Status2 :: cl82_rx_am_live_status_psll_2 29735 */ 29736 /* RX_X4_Status2 :: cl82_rx_am_live_status_psll_2 :: reserved0 [15:10] */ 29737 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_2_RESERVED0_MASK 0xfc00 29738 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_2_RESERVED0_ALIGN 0 29739 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_2_RESERVED0_BITS 6 29740 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_2_RESERVED0_SHIFT 10 29741 29742 /* RX_X4_Status2 :: cl82_rx_am_live_status_psll_2 :: am_lock_state_psll_2 [09:00] */ 29743 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_2_AM_LOCK_STATE_PSLL_2_MASK 0x03ff 29744 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_2_AM_LOCK_STATE_PSLL_2_ALIGN 0 29745 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_2_AM_LOCK_STATE_PSLL_2_BITS 10 29746 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_2_AM_LOCK_STATE_PSLL_2_SHIFT 0 29747 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_2_AM_LOCK_STATE_PSLL_2_INVALID_AM 512 29748 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_2_AM_LOCK_STATE_PSLL_2_GOOD_AM 256 29749 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_2_AM_LOCK_STATE_PSLL_2_COMP_AM 128 29750 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_2_AM_LOCK_STATE_PSLL_2_TIMER_2 64 29751 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_2_AM_LOCK_STATE_PSLL_2_AM_2_GOOD 32 29752 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_2_AM_LOCK_STATE_PSLL_2_COMP_2ND 16 29753 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_2_AM_LOCK_STATE_PSLL_2_TIMER_1 8 29754 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_2_AM_LOCK_STATE_PSLL_2_FIND_1ST 4 29755 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_2_AM_LOCK_STATE_PSLL_2_AM_RESET_CNT 2 29756 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_2_AM_LOCK_STATE_PSLL_2_AM_LOCK_INIT 1 29757 29758 29759 /**************************************************************************** 29760 * RX_X4_Status2 :: cl82_rx_am_live_status_psll_3 29761 */ 29762 /* RX_X4_Status2 :: cl82_rx_am_live_status_psll_3 :: reserved0 [15:10] */ 29763 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_3_RESERVED0_MASK 0xfc00 29764 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_3_RESERVED0_ALIGN 0 29765 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_3_RESERVED0_BITS 6 29766 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_3_RESERVED0_SHIFT 10 29767 29768 /* RX_X4_Status2 :: cl82_rx_am_live_status_psll_3 :: am_lock_state_psll_3 [09:00] */ 29769 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_3_AM_LOCK_STATE_PSLL_3_MASK 0x03ff 29770 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_3_AM_LOCK_STATE_PSLL_3_ALIGN 0 29771 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_3_AM_LOCK_STATE_PSLL_3_BITS 10 29772 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_3_AM_LOCK_STATE_PSLL_3_SHIFT 0 29773 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_3_AM_LOCK_STATE_PSLL_3_INVALID_AM 512 29774 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_3_AM_LOCK_STATE_PSLL_3_GOOD_AM 256 29775 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_3_AM_LOCK_STATE_PSLL_3_COMP_AM 128 29776 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_3_AM_LOCK_STATE_PSLL_3_TIMER_2 64 29777 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_3_AM_LOCK_STATE_PSLL_3_AM_2_GOOD 32 29778 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_3_AM_LOCK_STATE_PSLL_3_COMP_2ND 16 29779 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_3_AM_LOCK_STATE_PSLL_3_TIMER_1 8 29780 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_3_AM_LOCK_STATE_PSLL_3_FIND_1ST 4 29781 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_3_AM_LOCK_STATE_PSLL_3_AM_RESET_CNT 2 29782 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_3_AM_LOCK_STATE_PSLL_3_AM_LOCK_INIT 1 29783 29784 29785 /**************************************************************************** 29786 * RX_X4_Status2 :: cl82_rx_am_live_status_psll_4 29787 */ 29788 /* RX_X4_Status2 :: cl82_rx_am_live_status_psll_4 :: reserved0 [15:10] */ 29789 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_4_RESERVED0_MASK 0xfc00 29790 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_4_RESERVED0_ALIGN 0 29791 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_4_RESERVED0_BITS 6 29792 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_4_RESERVED0_SHIFT 10 29793 29794 /* RX_X4_Status2 :: cl82_rx_am_live_status_psll_4 :: am_lock_state_psll_4 [09:00] */ 29795 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_4_AM_LOCK_STATE_PSLL_4_MASK 0x03ff 29796 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_4_AM_LOCK_STATE_PSLL_4_ALIGN 0 29797 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_4_AM_LOCK_STATE_PSLL_4_BITS 10 29798 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_4_AM_LOCK_STATE_PSLL_4_SHIFT 0 29799 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_4_AM_LOCK_STATE_PSLL_4_INVALID_AM 512 29800 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_4_AM_LOCK_STATE_PSLL_4_GOOD_AM 256 29801 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_4_AM_LOCK_STATE_PSLL_4_COMP_AM 128 29802 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_4_AM_LOCK_STATE_PSLL_4_TIMER_2 64 29803 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_4_AM_LOCK_STATE_PSLL_4_AM_2_GOOD 32 29804 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_4_AM_LOCK_STATE_PSLL_4_COMP_2ND 16 29805 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_4_AM_LOCK_STATE_PSLL_4_TIMER_1 8 29806 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_4_AM_LOCK_STATE_PSLL_4_FIND_1ST 4 29807 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_4_AM_LOCK_STATE_PSLL_4_AM_RESET_CNT 2 29808 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_4_AM_LOCK_STATE_PSLL_4_AM_LOCK_INIT 1 29809 29810 29811 /**************************************************************************** 29812 * RX_X4_Status2 :: cl91_sync_status 29813 */ 29814 /* RX_X4_Status2 :: cl91_sync_status :: reserved0 [15:06] */ 29815 #define RX_X4_STATUS2_CL91_SYNC_STATUS_RESERVED0_MASK 0xffc0 29816 #define RX_X4_STATUS2_CL91_SYNC_STATUS_RESERVED0_ALIGN 0 29817 #define RX_X4_STATUS2_CL91_SYNC_STATUS_RESERVED0_BITS 10 29818 #define RX_X4_STATUS2_CL91_SYNC_STATUS_RESERVED0_SHIFT 6 29819 29820 /* RX_X4_Status2 :: cl91_sync_status :: cl91_fec_lane_map_valid [05:05] */ 29821 #define RX_X4_STATUS2_CL91_SYNC_STATUS_CL91_FEC_LANE_MAP_VALID_MASK 0x0020 29822 #define RX_X4_STATUS2_CL91_SYNC_STATUS_CL91_FEC_LANE_MAP_VALID_ALIGN 0 29823 #define RX_X4_STATUS2_CL91_SYNC_STATUS_CL91_FEC_LANE_MAP_VALID_BITS 1 29824 #define RX_X4_STATUS2_CL91_SYNC_STATUS_CL91_FEC_LANE_MAP_VALID_SHIFT 5 29825 29826 /* RX_X4_Status2 :: cl91_sync_status :: cl91_fec_lane_map [04:03] */ 29827 #define RX_X4_STATUS2_CL91_SYNC_STATUS_CL91_FEC_LANE_MAP_MASK 0x0018 29828 #define RX_X4_STATUS2_CL91_SYNC_STATUS_CL91_FEC_LANE_MAP_ALIGN 0 29829 #define RX_X4_STATUS2_CL91_SYNC_STATUS_CL91_FEC_LANE_MAP_BITS 2 29830 #define RX_X4_STATUS2_CL91_SYNC_STATUS_CL91_FEC_LANE_MAP_SHIFT 3 29831 29832 /* RX_X4_Status2 :: cl91_sync_status :: cl91_amps_lock_LH [02:02] */ 29833 #define RX_X4_STATUS2_CL91_SYNC_STATUS_CL91_AMPS_LOCK_LH_MASK 0x0004 29834 #define RX_X4_STATUS2_CL91_SYNC_STATUS_CL91_AMPS_LOCK_LH_ALIGN 0 29835 #define RX_X4_STATUS2_CL91_SYNC_STATUS_CL91_AMPS_LOCK_LH_BITS 1 29836 #define RX_X4_STATUS2_CL91_SYNC_STATUS_CL91_AMPS_LOCK_LH_SHIFT 2 29837 29838 /* RX_X4_Status2 :: cl91_sync_status :: cl91_amps_lock_LL [01:01] */ 29839 #define RX_X4_STATUS2_CL91_SYNC_STATUS_CL91_AMPS_LOCK_LL_MASK 0x0002 29840 #define RX_X4_STATUS2_CL91_SYNC_STATUS_CL91_AMPS_LOCK_LL_ALIGN 0 29841 #define RX_X4_STATUS2_CL91_SYNC_STATUS_CL91_AMPS_LOCK_LL_BITS 1 29842 #define RX_X4_STATUS2_CL91_SYNC_STATUS_CL91_AMPS_LOCK_LL_SHIFT 1 29843 29844 /* RX_X4_Status2 :: cl91_sync_status :: cl91_amps_lock_live [00:00] */ 29845 #define RX_X4_STATUS2_CL91_SYNC_STATUS_CL91_AMPS_LOCK_LIVE_MASK 0x0001 29846 #define RX_X4_STATUS2_CL91_SYNC_STATUS_CL91_AMPS_LOCK_LIVE_ALIGN 0 29847 #define RX_X4_STATUS2_CL91_SYNC_STATUS_CL91_AMPS_LOCK_LIVE_BITS 1 29848 #define RX_X4_STATUS2_CL91_SYNC_STATUS_CL91_AMPS_LOCK_LIVE_SHIFT 0 29849 29850 29851 /**************************************************************************** 29852 * RX_X4_Status2 :: fec_sync_fsm_state 29853 */ 29854 /* RX_X4_Status2 :: fec_sync_fsm_state :: reserved0 [15:06] */ 29855 #define RX_X4_STATUS2_FEC_SYNC_FSM_STATE_RESERVED0_MASK 0xffc0 29856 #define RX_X4_STATUS2_FEC_SYNC_FSM_STATE_RESERVED0_ALIGN 0 29857 #define RX_X4_STATUS2_FEC_SYNC_FSM_STATE_RESERVED0_BITS 10 29858 #define RX_X4_STATUS2_FEC_SYNC_FSM_STATE_RESERVED0_SHIFT 6 29859 29860 /* RX_X4_Status2 :: fec_sync_fsm_state :: cl91_fec_sync_fsm_latched_state [05:02] */ 29861 #define RX_X4_STATUS2_FEC_SYNC_FSM_STATE_CL91_FEC_SYNC_FSM_LATCHED_STATE_MASK 0x003c 29862 #define RX_X4_STATUS2_FEC_SYNC_FSM_STATE_CL91_FEC_SYNC_FSM_LATCHED_STATE_ALIGN 0 29863 #define RX_X4_STATUS2_FEC_SYNC_FSM_STATE_CL91_FEC_SYNC_FSM_LATCHED_STATE_BITS 4 29864 #define RX_X4_STATUS2_FEC_SYNC_FSM_STATE_CL91_FEC_SYNC_FSM_LATCHED_STATE_SHIFT 2 29865 #define RX_X4_STATUS2_FEC_SYNC_FSM_STATE_CL91_FEC_SYNC_FSM_LATCHED_STATE_FIND_1ST 0 29866 #define RX_X4_STATUS2_FEC_SYNC_FSM_STATE_CL91_FEC_SYNC_FSM_LATCHED_STATE_COUNT_NEXT 1 29867 #define RX_X4_STATUS2_FEC_SYNC_FSM_STATE_CL91_FEC_SYNC_FSM_LATCHED_STATE_COMP_2ND 2 29868 #define RX_X4_STATUS2_FEC_SYNC_FSM_STATE_CL91_FEC_SYNC_FSM_LATCHED_STATE_TWO_GOOD 3 29869 29870 /* RX_X4_Status2 :: fec_sync_fsm_state :: cl91_fec_sync_fsm_live_state [01:00] */ 29871 #define RX_X4_STATUS2_FEC_SYNC_FSM_STATE_CL91_FEC_SYNC_FSM_LIVE_STATE_MASK 0x0003 29872 #define RX_X4_STATUS2_FEC_SYNC_FSM_STATE_CL91_FEC_SYNC_FSM_LIVE_STATE_ALIGN 0 29873 #define RX_X4_STATUS2_FEC_SYNC_FSM_STATE_CL91_FEC_SYNC_FSM_LIVE_STATE_BITS 2 29874 #define RX_X4_STATUS2_FEC_SYNC_FSM_STATE_CL91_FEC_SYNC_FSM_LIVE_STATE_SHIFT 0 29875 #define RX_X4_STATUS2_FEC_SYNC_FSM_STATE_CL91_FEC_SYNC_FSM_LIVE_STATE_FIND_1ST 0 29876 #define RX_X4_STATUS2_FEC_SYNC_FSM_STATE_CL91_FEC_SYNC_FSM_LIVE_STATE_COUNT_NEXT 1 29877 #define RX_X4_STATUS2_FEC_SYNC_FSM_STATE_CL91_FEC_SYNC_FSM_LIVE_STATE_COMP_2ND 2 29878 #define RX_X4_STATUS2_FEC_SYNC_FSM_STATE_CL91_FEC_SYNC_FSM_LIVE_STATE_TWO_GOOD 3 29879 29880 29881 /**************************************************************************** 29882 * RX_X4_Status2 :: cl91_fc_slip_cnt 29883 */ 29884 /* RX_X4_Status2 :: cl91_fc_slip_cnt :: cl91_fc_slip_cnt [15:00] */ 29885 #define RX_X4_STATUS2_CL91_FC_SLIP_CNT_CL91_FC_SLIP_CNT_MASK 0xffff 29886 #define RX_X4_STATUS2_CL91_FC_SLIP_CNT_CL91_FC_SLIP_CNT_ALIGN 0 29887 #define RX_X4_STATUS2_CL91_FC_SLIP_CNT_CL91_FC_SLIP_CNT_BITS 16 29888 #define RX_X4_STATUS2_CL91_FC_SLIP_CNT_CL91_FC_SLIP_CNT_SHIFT 0 29889 29890 29891 /**************************************************************************** 29892 * TSC_WC4_TSC_USER4_RX_X4_Status3 29893 */ 29894 /**************************************************************************** 29895 * RX_X4_Status3 :: fec_dbg_errL_0 29896 */ 29897 /* RX_X4_Status3 :: fec_dbg_errL_0 :: dbg_errL_stream0 [15:00] */ 29898 #define RX_X4_STATUS3_FEC_DBG_ERRL_0_DBG_ERRL_STREAM0_MASK 0xffff 29899 #define RX_X4_STATUS3_FEC_DBG_ERRL_0_DBG_ERRL_STREAM0_ALIGN 0 29900 #define RX_X4_STATUS3_FEC_DBG_ERRL_0_DBG_ERRL_STREAM0_BITS 16 29901 #define RX_X4_STATUS3_FEC_DBG_ERRL_0_DBG_ERRL_STREAM0_SHIFT 0 29902 29903 29904 /**************************************************************************** 29905 * RX_X4_Status3 :: fec_dbg_errL_1 29906 */ 29907 /* RX_X4_Status3 :: fec_dbg_errL_1 :: dbg_errL_stream1 [15:00] */ 29908 #define RX_X4_STATUS3_FEC_DBG_ERRL_1_DBG_ERRL_STREAM1_MASK 0xffff 29909 #define RX_X4_STATUS3_FEC_DBG_ERRL_1_DBG_ERRL_STREAM1_ALIGN 0 29910 #define RX_X4_STATUS3_FEC_DBG_ERRL_1_DBG_ERRL_STREAM1_BITS 16 29911 #define RX_X4_STATUS3_FEC_DBG_ERRL_1_DBG_ERRL_STREAM1_SHIFT 0 29912 29913 29914 /**************************************************************************** 29915 * RX_X4_Status3 :: fec_dbg_errL_2 29916 */ 29917 /* RX_X4_Status3 :: fec_dbg_errL_2 :: dbg_errL_stream2 [15:00] */ 29918 #define RX_X4_STATUS3_FEC_DBG_ERRL_2_DBG_ERRL_STREAM2_MASK 0xffff 29919 #define RX_X4_STATUS3_FEC_DBG_ERRL_2_DBG_ERRL_STREAM2_ALIGN 0 29920 #define RX_X4_STATUS3_FEC_DBG_ERRL_2_DBG_ERRL_STREAM2_BITS 16 29921 #define RX_X4_STATUS3_FEC_DBG_ERRL_2_DBG_ERRL_STREAM2_SHIFT 0 29922 29923 29924 /**************************************************************************** 29925 * RX_X4_Status3 :: fec_dbg_errL_3 29926 */ 29927 /* RX_X4_Status3 :: fec_dbg_errL_3 :: dbg_errL_stream3 [15:00] */ 29928 #define RX_X4_STATUS3_FEC_DBG_ERRL_3_DBG_ERRL_STREAM3_MASK 0xffff 29929 #define RX_X4_STATUS3_FEC_DBG_ERRL_3_DBG_ERRL_STREAM3_ALIGN 0 29930 #define RX_X4_STATUS3_FEC_DBG_ERRL_3_DBG_ERRL_STREAM3_BITS 16 29931 #define RX_X4_STATUS3_FEC_DBG_ERRL_3_DBG_ERRL_STREAM3_SHIFT 0 29932 29933 29934 /**************************************************************************** 29935 * RX_X4_Status3 :: fec_dbg_errL_4 29936 */ 29937 /* RX_X4_Status3 :: fec_dbg_errL_4 :: dbg_errL_stream4 [15:00] */ 29938 #define RX_X4_STATUS3_FEC_DBG_ERRL_4_DBG_ERRL_STREAM4_MASK 0xffff 29939 #define RX_X4_STATUS3_FEC_DBG_ERRL_4_DBG_ERRL_STREAM4_ALIGN 0 29940 #define RX_X4_STATUS3_FEC_DBG_ERRL_4_DBG_ERRL_STREAM4_BITS 16 29941 #define RX_X4_STATUS3_FEC_DBG_ERRL_4_DBG_ERRL_STREAM4_SHIFT 0 29942 29943 29944 /**************************************************************************** 29945 * RX_X4_Status3 :: fec_dbg_erraH_0 29946 */ 29947 /* RX_X4_Status3 :: fec_dbg_erraH_0 :: dbg_errH_stream0 [15:00] */ 29948 #define RX_X4_STATUS3_FEC_DBG_ERRAH_0_DBG_ERRH_STREAM0_MASK 0xffff 29949 #define RX_X4_STATUS3_FEC_DBG_ERRAH_0_DBG_ERRH_STREAM0_ALIGN 0 29950 #define RX_X4_STATUS3_FEC_DBG_ERRAH_0_DBG_ERRH_STREAM0_BITS 16 29951 #define RX_X4_STATUS3_FEC_DBG_ERRAH_0_DBG_ERRH_STREAM0_SHIFT 0 29952 29953 29954 /**************************************************************************** 29955 * RX_X4_Status3 :: fec_dbg_erraH_1 29956 */ 29957 /* RX_X4_Status3 :: fec_dbg_erraH_1 :: dbg_errH_stream1 [15:00] */ 29958 #define RX_X4_STATUS3_FEC_DBG_ERRAH_1_DBG_ERRH_STREAM1_MASK 0xffff 29959 #define RX_X4_STATUS3_FEC_DBG_ERRAH_1_DBG_ERRH_STREAM1_ALIGN 0 29960 #define RX_X4_STATUS3_FEC_DBG_ERRAH_1_DBG_ERRH_STREAM1_BITS 16 29961 #define RX_X4_STATUS3_FEC_DBG_ERRAH_1_DBG_ERRH_STREAM1_SHIFT 0 29962 29963 29964 /**************************************************************************** 29965 * RX_X4_Status3 :: fec_dbg_erraH_2 29966 */ 29967 /* RX_X4_Status3 :: fec_dbg_erraH_2 :: dbg_errH_stream2 [15:00] */ 29968 #define RX_X4_STATUS3_FEC_DBG_ERRAH_2_DBG_ERRH_STREAM2_MASK 0xffff 29969 #define RX_X4_STATUS3_FEC_DBG_ERRAH_2_DBG_ERRH_STREAM2_ALIGN 0 29970 #define RX_X4_STATUS3_FEC_DBG_ERRAH_2_DBG_ERRH_STREAM2_BITS 16 29971 #define RX_X4_STATUS3_FEC_DBG_ERRAH_2_DBG_ERRH_STREAM2_SHIFT 0 29972 29973 29974 /**************************************************************************** 29975 * RX_X4_Status3 :: fec_dbg_erraH_3 29976 */ 29977 /* RX_X4_Status3 :: fec_dbg_erraH_3 :: dbg_errH_stream3 [15:00] */ 29978 #define RX_X4_STATUS3_FEC_DBG_ERRAH_3_DBG_ERRH_STREAM3_MASK 0xffff 29979 #define RX_X4_STATUS3_FEC_DBG_ERRAH_3_DBG_ERRH_STREAM3_ALIGN 0 29980 #define RX_X4_STATUS3_FEC_DBG_ERRAH_3_DBG_ERRH_STREAM3_BITS 16 29981 #define RX_X4_STATUS3_FEC_DBG_ERRAH_3_DBG_ERRH_STREAM3_SHIFT 0 29982 29983 29984 /**************************************************************************** 29985 * RX_X4_Status3 :: fec_dbg_erraH_4 29986 */ 29987 /* RX_X4_Status3 :: fec_dbg_erraH_4 :: dbg_errH_stream4 [15:00] */ 29988 #define RX_X4_STATUS3_FEC_DBG_ERRAH_4_DBG_ERRH_STREAM4_MASK 0xffff 29989 #define RX_X4_STATUS3_FEC_DBG_ERRAH_4_DBG_ERRH_STREAM4_ALIGN 0 29990 #define RX_X4_STATUS3_FEC_DBG_ERRAH_4_DBG_ERRH_STREAM4_BITS 16 29991 #define RX_X4_STATUS3_FEC_DBG_ERRAH_4_DBG_ERRH_STREAM4_SHIFT 0 29992 29993 29994 /**************************************************************************** 29995 * RX_X4_Status3 :: fec_burst_err_statusL_0 29996 */ 29997 /* RX_X4_Status3 :: fec_burst_err_statusL_0 :: burst_err_statusL_stream0 [15:00] */ 29998 #define RX_X4_STATUS3_FEC_BURST_ERR_STATUSL_0_BURST_ERR_STATUSL_STREAM0_MASK 0xffff 29999 #define RX_X4_STATUS3_FEC_BURST_ERR_STATUSL_0_BURST_ERR_STATUSL_STREAM0_ALIGN 0 30000 #define RX_X4_STATUS3_FEC_BURST_ERR_STATUSL_0_BURST_ERR_STATUSL_STREAM0_BITS 16 30001 #define RX_X4_STATUS3_FEC_BURST_ERR_STATUSL_0_BURST_ERR_STATUSL_STREAM0_SHIFT 0 30002 30003 30004 /**************************************************************************** 30005 * RX_X4_Status3 :: fec_burst_err_statusL_1 30006 */ 30007 /* RX_X4_Status3 :: fec_burst_err_statusL_1 :: burst_err_statusL_stream1 [15:00] */ 30008 #define RX_X4_STATUS3_FEC_BURST_ERR_STATUSL_1_BURST_ERR_STATUSL_STREAM1_MASK 0xffff 30009 #define RX_X4_STATUS3_FEC_BURST_ERR_STATUSL_1_BURST_ERR_STATUSL_STREAM1_ALIGN 0 30010 #define RX_X4_STATUS3_FEC_BURST_ERR_STATUSL_1_BURST_ERR_STATUSL_STREAM1_BITS 16 30011 #define RX_X4_STATUS3_FEC_BURST_ERR_STATUSL_1_BURST_ERR_STATUSL_STREAM1_SHIFT 0 30012 30013 30014 /**************************************************************************** 30015 * RX_X4_Status3 :: fec_burst_err_statusL_2 30016 */ 30017 /* RX_X4_Status3 :: fec_burst_err_statusL_2 :: burst_err_statusL_stream2 [15:00] */ 30018 #define RX_X4_STATUS3_FEC_BURST_ERR_STATUSL_2_BURST_ERR_STATUSL_STREAM2_MASK 0xffff 30019 #define RX_X4_STATUS3_FEC_BURST_ERR_STATUSL_2_BURST_ERR_STATUSL_STREAM2_ALIGN 0 30020 #define RX_X4_STATUS3_FEC_BURST_ERR_STATUSL_2_BURST_ERR_STATUSL_STREAM2_BITS 16 30021 #define RX_X4_STATUS3_FEC_BURST_ERR_STATUSL_2_BURST_ERR_STATUSL_STREAM2_SHIFT 0 30022 30023 30024 /**************************************************************************** 30025 * RX_X4_Status3 :: fec_burst_err_statusL_3 30026 */ 30027 /* RX_X4_Status3 :: fec_burst_err_statusL_3 :: burst_err_statusL_stream3 [15:00] */ 30028 #define RX_X4_STATUS3_FEC_BURST_ERR_STATUSL_3_BURST_ERR_STATUSL_STREAM3_MASK 0xffff 30029 #define RX_X4_STATUS3_FEC_BURST_ERR_STATUSL_3_BURST_ERR_STATUSL_STREAM3_ALIGN 0 30030 #define RX_X4_STATUS3_FEC_BURST_ERR_STATUSL_3_BURST_ERR_STATUSL_STREAM3_BITS 16 30031 #define RX_X4_STATUS3_FEC_BURST_ERR_STATUSL_3_BURST_ERR_STATUSL_STREAM3_SHIFT 0 30032 30033 30034 /**************************************************************************** 30035 * RX_X4_Status3 :: fec_burst_err_statusL_4 30036 */ 30037 /* RX_X4_Status3 :: fec_burst_err_statusL_4 :: burst_err_statusL_stream4 [15:00] */ 30038 #define RX_X4_STATUS3_FEC_BURST_ERR_STATUSL_4_BURST_ERR_STATUSL_STREAM4_MASK 0xffff 30039 #define RX_X4_STATUS3_FEC_BURST_ERR_STATUSL_4_BURST_ERR_STATUSL_STREAM4_ALIGN 0 30040 #define RX_X4_STATUS3_FEC_BURST_ERR_STATUSL_4_BURST_ERR_STATUSL_STREAM4_BITS 16 30041 #define RX_X4_STATUS3_FEC_BURST_ERR_STATUSL_4_BURST_ERR_STATUSL_STREAM4_SHIFT 0 30042 30043 30044 /**************************************************************************** 30045 * TSC_WC4_TSC_USER4_RX_X4_Status4 30046 */ 30047 /**************************************************************************** 30048 * RX_X4_Status4 :: fec_burst_err_statusH_0 30049 */ 30050 /* RX_X4_Status4 :: fec_burst_err_statusH_0 :: burst_err_statusH_stream0 [15:00] */ 30051 #define RX_X4_STATUS4_FEC_BURST_ERR_STATUSH_0_BURST_ERR_STATUSH_STREAM0_MASK 0xffff 30052 #define RX_X4_STATUS4_FEC_BURST_ERR_STATUSH_0_BURST_ERR_STATUSH_STREAM0_ALIGN 0 30053 #define RX_X4_STATUS4_FEC_BURST_ERR_STATUSH_0_BURST_ERR_STATUSH_STREAM0_BITS 16 30054 #define RX_X4_STATUS4_FEC_BURST_ERR_STATUSH_0_BURST_ERR_STATUSH_STREAM0_SHIFT 0 30055 30056 30057 /**************************************************************************** 30058 * RX_X4_Status4 :: fec_burst_err_statusH_1 30059 */ 30060 /* RX_X4_Status4 :: fec_burst_err_statusH_1 :: burst_err_statusH_stream1 [15:00] */ 30061 #define RX_X4_STATUS4_FEC_BURST_ERR_STATUSH_1_BURST_ERR_STATUSH_STREAM1_MASK 0xffff 30062 #define RX_X4_STATUS4_FEC_BURST_ERR_STATUSH_1_BURST_ERR_STATUSH_STREAM1_ALIGN 0 30063 #define RX_X4_STATUS4_FEC_BURST_ERR_STATUSH_1_BURST_ERR_STATUSH_STREAM1_BITS 16 30064 #define RX_X4_STATUS4_FEC_BURST_ERR_STATUSH_1_BURST_ERR_STATUSH_STREAM1_SHIFT 0 30065 30066 30067 /**************************************************************************** 30068 * RX_X4_Status4 :: fec_burst_err_statusH_2 30069 */ 30070 /* RX_X4_Status4 :: fec_burst_err_statusH_2 :: burst_err_statusH_stream2 [15:00] */ 30071 #define RX_X4_STATUS4_FEC_BURST_ERR_STATUSH_2_BURST_ERR_STATUSH_STREAM2_MASK 0xffff 30072 #define RX_X4_STATUS4_FEC_BURST_ERR_STATUSH_2_BURST_ERR_STATUSH_STREAM2_ALIGN 0 30073 #define RX_X4_STATUS4_FEC_BURST_ERR_STATUSH_2_BURST_ERR_STATUSH_STREAM2_BITS 16 30074 #define RX_X4_STATUS4_FEC_BURST_ERR_STATUSH_2_BURST_ERR_STATUSH_STREAM2_SHIFT 0 30075 30076 30077 /**************************************************************************** 30078 * RX_X4_Status4 :: fec_burst_err_statusH_3 30079 */ 30080 /* RX_X4_Status4 :: fec_burst_err_statusH_3 :: burst_err_statusH_stream3 [15:00] */ 30081 #define RX_X4_STATUS4_FEC_BURST_ERR_STATUSH_3_BURST_ERR_STATUSH_STREAM3_MASK 0xffff 30082 #define RX_X4_STATUS4_FEC_BURST_ERR_STATUSH_3_BURST_ERR_STATUSH_STREAM3_ALIGN 0 30083 #define RX_X4_STATUS4_FEC_BURST_ERR_STATUSH_3_BURST_ERR_STATUSH_STREAM3_BITS 16 30084 #define RX_X4_STATUS4_FEC_BURST_ERR_STATUSH_3_BURST_ERR_STATUSH_STREAM3_SHIFT 0 30085 30086 30087 /**************************************************************************** 30088 * RX_X4_Status4 :: fec_burst_err_statusH_4 30089 */ 30090 /* RX_X4_Status4 :: fec_burst_err_statusH_4 :: burst_err_statusH_stream4 [15:00] */ 30091 #define RX_X4_STATUS4_FEC_BURST_ERR_STATUSH_4_BURST_ERR_STATUSH_STREAM4_MASK 0xffff 30092 #define RX_X4_STATUS4_FEC_BURST_ERR_STATUSH_4_BURST_ERR_STATUSH_STREAM4_ALIGN 0 30093 #define RX_X4_STATUS4_FEC_BURST_ERR_STATUSH_4_BURST_ERR_STATUSH_STREAM4_BITS 16 30094 #define RX_X4_STATUS4_FEC_BURST_ERR_STATUSH_4_BURST_ERR_STATUSH_STREAM4_SHIFT 0 30095 30096 30097 /**************************************************************************** 30098 * RX_X4_Status4 :: fec_CorrectedBlksL_0 30099 */ 30100 /* RX_X4_Status4 :: fec_CorrectedBlksL_0 :: corCountL_stream0 [15:00] */ 30101 #define RX_X4_STATUS4_FEC_CORRECTEDBLKSL_0_CORCOUNTL_STREAM0_MASK 0xffff 30102 #define RX_X4_STATUS4_FEC_CORRECTEDBLKSL_0_CORCOUNTL_STREAM0_ALIGN 0 30103 #define RX_X4_STATUS4_FEC_CORRECTEDBLKSL_0_CORCOUNTL_STREAM0_BITS 16 30104 #define RX_X4_STATUS4_FEC_CORRECTEDBLKSL_0_CORCOUNTL_STREAM0_SHIFT 0 30105 30106 30107 /**************************************************************************** 30108 * RX_X4_Status4 :: fec_CorrectedBlksL_1 30109 */ 30110 /* RX_X4_Status4 :: fec_CorrectedBlksL_1 :: corCountL_stream1 [15:00] */ 30111 #define RX_X4_STATUS4_FEC_CORRECTEDBLKSL_1_CORCOUNTL_STREAM1_MASK 0xffff 30112 #define RX_X4_STATUS4_FEC_CORRECTEDBLKSL_1_CORCOUNTL_STREAM1_ALIGN 0 30113 #define RX_X4_STATUS4_FEC_CORRECTEDBLKSL_1_CORCOUNTL_STREAM1_BITS 16 30114 #define RX_X4_STATUS4_FEC_CORRECTEDBLKSL_1_CORCOUNTL_STREAM1_SHIFT 0 30115 30116 30117 /**************************************************************************** 30118 * RX_X4_Status4 :: fec_CorrectedBlksL_2 30119 */ 30120 /* RX_X4_Status4 :: fec_CorrectedBlksL_2 :: corCountL_stream2 [15:00] */ 30121 #define RX_X4_STATUS4_FEC_CORRECTEDBLKSL_2_CORCOUNTL_STREAM2_MASK 0xffff 30122 #define RX_X4_STATUS4_FEC_CORRECTEDBLKSL_2_CORCOUNTL_STREAM2_ALIGN 0 30123 #define RX_X4_STATUS4_FEC_CORRECTEDBLKSL_2_CORCOUNTL_STREAM2_BITS 16 30124 #define RX_X4_STATUS4_FEC_CORRECTEDBLKSL_2_CORCOUNTL_STREAM2_SHIFT 0 30125 30126 30127 /**************************************************************************** 30128 * RX_X4_Status4 :: fec_CorrectedBlksL_3 30129 */ 30130 /* RX_X4_Status4 :: fec_CorrectedBlksL_3 :: corCountL_stream3 [15:00] */ 30131 #define RX_X4_STATUS4_FEC_CORRECTEDBLKSL_3_CORCOUNTL_STREAM3_MASK 0xffff 30132 #define RX_X4_STATUS4_FEC_CORRECTEDBLKSL_3_CORCOUNTL_STREAM3_ALIGN 0 30133 #define RX_X4_STATUS4_FEC_CORRECTEDBLKSL_3_CORCOUNTL_STREAM3_BITS 16 30134 #define RX_X4_STATUS4_FEC_CORRECTEDBLKSL_3_CORCOUNTL_STREAM3_SHIFT 0 30135 30136 30137 /**************************************************************************** 30138 * RX_X4_Status4 :: fec_CorrectedBlksL_4 30139 */ 30140 /* RX_X4_Status4 :: fec_CorrectedBlksL_4 :: corCountL_stream4 [15:00] */ 30141 #define RX_X4_STATUS4_FEC_CORRECTEDBLKSL_4_CORCOUNTL_STREAM4_MASK 0xffff 30142 #define RX_X4_STATUS4_FEC_CORRECTEDBLKSL_4_CORCOUNTL_STREAM4_ALIGN 0 30143 #define RX_X4_STATUS4_FEC_CORRECTEDBLKSL_4_CORCOUNTL_STREAM4_BITS 16 30144 #define RX_X4_STATUS4_FEC_CORRECTEDBLKSL_4_CORCOUNTL_STREAM4_SHIFT 0 30145 30146 30147 /**************************************************************************** 30148 * RX_X4_Status4 :: fec_CorrectedBlksH_0 30149 */ 30150 /* RX_X4_Status4 :: fec_CorrectedBlksH_0 :: corCountH_stream0 [15:00] */ 30151 #define RX_X4_STATUS4_FEC_CORRECTEDBLKSH_0_CORCOUNTH_STREAM0_MASK 0xffff 30152 #define RX_X4_STATUS4_FEC_CORRECTEDBLKSH_0_CORCOUNTH_STREAM0_ALIGN 0 30153 #define RX_X4_STATUS4_FEC_CORRECTEDBLKSH_0_CORCOUNTH_STREAM0_BITS 16 30154 #define RX_X4_STATUS4_FEC_CORRECTEDBLKSH_0_CORCOUNTH_STREAM0_SHIFT 0 30155 30156 30157 /**************************************************************************** 30158 * RX_X4_Status4 :: fec_CorrectedBlksH_1 30159 */ 30160 /* RX_X4_Status4 :: fec_CorrectedBlksH_1 :: corCountH_stream1 [15:00] */ 30161 #define RX_X4_STATUS4_FEC_CORRECTEDBLKSH_1_CORCOUNTH_STREAM1_MASK 0xffff 30162 #define RX_X4_STATUS4_FEC_CORRECTEDBLKSH_1_CORCOUNTH_STREAM1_ALIGN 0 30163 #define RX_X4_STATUS4_FEC_CORRECTEDBLKSH_1_CORCOUNTH_STREAM1_BITS 16 30164 #define RX_X4_STATUS4_FEC_CORRECTEDBLKSH_1_CORCOUNTH_STREAM1_SHIFT 0 30165 30166 30167 /**************************************************************************** 30168 * RX_X4_Status4 :: fec_CorrectedBlksH_2 30169 */ 30170 /* RX_X4_Status4 :: fec_CorrectedBlksH_2 :: corCountH_stream2 [15:00] */ 30171 #define RX_X4_STATUS4_FEC_CORRECTEDBLKSH_2_CORCOUNTH_STREAM2_MASK 0xffff 30172 #define RX_X4_STATUS4_FEC_CORRECTEDBLKSH_2_CORCOUNTH_STREAM2_ALIGN 0 30173 #define RX_X4_STATUS4_FEC_CORRECTEDBLKSH_2_CORCOUNTH_STREAM2_BITS 16 30174 #define RX_X4_STATUS4_FEC_CORRECTEDBLKSH_2_CORCOUNTH_STREAM2_SHIFT 0 30175 30176 30177 /**************************************************************************** 30178 * RX_X4_Status4 :: fec_CorrectedBlksH_3 30179 */ 30180 /* RX_X4_Status4 :: fec_CorrectedBlksH_3 :: corCountH_stream3 [15:00] */ 30181 #define RX_X4_STATUS4_FEC_CORRECTEDBLKSH_3_CORCOUNTH_STREAM3_MASK 0xffff 30182 #define RX_X4_STATUS4_FEC_CORRECTEDBLKSH_3_CORCOUNTH_STREAM3_ALIGN 0 30183 #define RX_X4_STATUS4_FEC_CORRECTEDBLKSH_3_CORCOUNTH_STREAM3_BITS 16 30184 #define RX_X4_STATUS4_FEC_CORRECTEDBLKSH_3_CORCOUNTH_STREAM3_SHIFT 0 30185 30186 30187 /**************************************************************************** 30188 * RX_X4_Status4 :: fec_CorrectedBlksH_4 30189 */ 30190 /* RX_X4_Status4 :: fec_CorrectedBlksH_4 :: corCountH_stream4 [15:00] */ 30191 #define RX_X4_STATUS4_FEC_CORRECTEDBLKSH_4_CORCOUNTH_STREAM4_MASK 0xffff 30192 #define RX_X4_STATUS4_FEC_CORRECTEDBLKSH_4_CORCOUNTH_STREAM4_ALIGN 0 30193 #define RX_X4_STATUS4_FEC_CORRECTEDBLKSH_4_CORCOUNTH_STREAM4_BITS 16 30194 #define RX_X4_STATUS4_FEC_CORRECTEDBLKSH_4_CORCOUNTH_STREAM4_SHIFT 0 30195 30196 30197 /**************************************************************************** 30198 * TSC_WC4_TSC_USER4_RX_X4_Status5 30199 */ 30200 /**************************************************************************** 30201 * RX_X4_Status5 :: fec_UncorrectedBlksL_0 30202 */ 30203 /* RX_X4_Status5 :: fec_UncorrectedBlksL_0 :: uncorCountL_stream0 [15:00] */ 30204 #define RX_X4_STATUS5_FEC_UNCORRECTEDBLKSL_0_UNCORCOUNTL_STREAM0_MASK 0xffff 30205 #define RX_X4_STATUS5_FEC_UNCORRECTEDBLKSL_0_UNCORCOUNTL_STREAM0_ALIGN 0 30206 #define RX_X4_STATUS5_FEC_UNCORRECTEDBLKSL_0_UNCORCOUNTL_STREAM0_BITS 16 30207 #define RX_X4_STATUS5_FEC_UNCORRECTEDBLKSL_0_UNCORCOUNTL_STREAM0_SHIFT 0 30208 30209 30210 /**************************************************************************** 30211 * RX_X4_Status5 :: fec_UncorrectedBlksL_1 30212 */ 30213 /* RX_X4_Status5 :: fec_UncorrectedBlksL_1 :: uncorCountL_stream1 [15:00] */ 30214 #define RX_X4_STATUS5_FEC_UNCORRECTEDBLKSL_1_UNCORCOUNTL_STREAM1_MASK 0xffff 30215 #define RX_X4_STATUS5_FEC_UNCORRECTEDBLKSL_1_UNCORCOUNTL_STREAM1_ALIGN 0 30216 #define RX_X4_STATUS5_FEC_UNCORRECTEDBLKSL_1_UNCORCOUNTL_STREAM1_BITS 16 30217 #define RX_X4_STATUS5_FEC_UNCORRECTEDBLKSL_1_UNCORCOUNTL_STREAM1_SHIFT 0 30218 30219 30220 /**************************************************************************** 30221 * RX_X4_Status5 :: fec_UncorrectedBlksL_2 30222 */ 30223 /* RX_X4_Status5 :: fec_UncorrectedBlksL_2 :: uncorCountL_stream2 [15:00] */ 30224 #define RX_X4_STATUS5_FEC_UNCORRECTEDBLKSL_2_UNCORCOUNTL_STREAM2_MASK 0xffff 30225 #define RX_X4_STATUS5_FEC_UNCORRECTEDBLKSL_2_UNCORCOUNTL_STREAM2_ALIGN 0 30226 #define RX_X4_STATUS5_FEC_UNCORRECTEDBLKSL_2_UNCORCOUNTL_STREAM2_BITS 16 30227 #define RX_X4_STATUS5_FEC_UNCORRECTEDBLKSL_2_UNCORCOUNTL_STREAM2_SHIFT 0 30228 30229 30230 /**************************************************************************** 30231 * RX_X4_Status5 :: fec_UncorrectedBlksL_3 30232 */ 30233 /* RX_X4_Status5 :: fec_UncorrectedBlksL_3 :: uncorCountL_stream3 [15:00] */ 30234 #define RX_X4_STATUS5_FEC_UNCORRECTEDBLKSL_3_UNCORCOUNTL_STREAM3_MASK 0xffff 30235 #define RX_X4_STATUS5_FEC_UNCORRECTEDBLKSL_3_UNCORCOUNTL_STREAM3_ALIGN 0 30236 #define RX_X4_STATUS5_FEC_UNCORRECTEDBLKSL_3_UNCORCOUNTL_STREAM3_BITS 16 30237 #define RX_X4_STATUS5_FEC_UNCORRECTEDBLKSL_3_UNCORCOUNTL_STREAM3_SHIFT 0 30238 30239 30240 /**************************************************************************** 30241 * RX_X4_Status5 :: fec_UncorrectedBlksL_4 30242 */ 30243 /* RX_X4_Status5 :: fec_UncorrectedBlksL_4 :: uncorCountL_stream4 [15:00] */ 30244 #define RX_X4_STATUS5_FEC_UNCORRECTEDBLKSL_4_UNCORCOUNTL_STREAM4_MASK 0xffff 30245 #define RX_X4_STATUS5_FEC_UNCORRECTEDBLKSL_4_UNCORCOUNTL_STREAM4_ALIGN 0 30246 #define RX_X4_STATUS5_FEC_UNCORRECTEDBLKSL_4_UNCORCOUNTL_STREAM4_BITS 16 30247 #define RX_X4_STATUS5_FEC_UNCORRECTEDBLKSL_4_UNCORCOUNTL_STREAM4_SHIFT 0 30248 30249 30250 /**************************************************************************** 30251 * RX_X4_Status5 :: fec_UncorrectedBlksH_0 30252 */ 30253 /* RX_X4_Status5 :: fec_UncorrectedBlksH_0 :: uncorCountH_stream0 [15:00] */ 30254 #define RX_X4_STATUS5_FEC_UNCORRECTEDBLKSH_0_UNCORCOUNTH_STREAM0_MASK 0xffff 30255 #define RX_X4_STATUS5_FEC_UNCORRECTEDBLKSH_0_UNCORCOUNTH_STREAM0_ALIGN 0 30256 #define RX_X4_STATUS5_FEC_UNCORRECTEDBLKSH_0_UNCORCOUNTH_STREAM0_BITS 16 30257 #define RX_X4_STATUS5_FEC_UNCORRECTEDBLKSH_0_UNCORCOUNTH_STREAM0_SHIFT 0 30258 30259 30260 /**************************************************************************** 30261 * RX_X4_Status5 :: fec_UncorrectedBlksH_1 30262 */ 30263 /* RX_X4_Status5 :: fec_UncorrectedBlksH_1 :: uncorCountH_stream1 [15:00] */ 30264 #define RX_X4_STATUS5_FEC_UNCORRECTEDBLKSH_1_UNCORCOUNTH_STREAM1_MASK 0xffff 30265 #define RX_X4_STATUS5_FEC_UNCORRECTEDBLKSH_1_UNCORCOUNTH_STREAM1_ALIGN 0 30266 #define RX_X4_STATUS5_FEC_UNCORRECTEDBLKSH_1_UNCORCOUNTH_STREAM1_BITS 16 30267 #define RX_X4_STATUS5_FEC_UNCORRECTEDBLKSH_1_UNCORCOUNTH_STREAM1_SHIFT 0 30268 30269 30270 /**************************************************************************** 30271 * RX_X4_Status5 :: fec_UncorrectedBlksH_2 30272 */ 30273 /* RX_X4_Status5 :: fec_UncorrectedBlksH_2 :: uncorCountH_stream2 [15:00] */ 30274 #define RX_X4_STATUS5_FEC_UNCORRECTEDBLKSH_2_UNCORCOUNTH_STREAM2_MASK 0xffff 30275 #define RX_X4_STATUS5_FEC_UNCORRECTEDBLKSH_2_UNCORCOUNTH_STREAM2_ALIGN 0 30276 #define RX_X4_STATUS5_FEC_UNCORRECTEDBLKSH_2_UNCORCOUNTH_STREAM2_BITS 16 30277 #define RX_X4_STATUS5_FEC_UNCORRECTEDBLKSH_2_UNCORCOUNTH_STREAM2_SHIFT 0 30278 30279 30280 /**************************************************************************** 30281 * RX_X4_Status5 :: fec_UncorrectedBlksH_3 30282 */ 30283 /* RX_X4_Status5 :: fec_UncorrectedBlksH_3 :: uncorCountH_stream3 [15:00] */ 30284 #define RX_X4_STATUS5_FEC_UNCORRECTEDBLKSH_3_UNCORCOUNTH_STREAM3_MASK 0xffff 30285 #define RX_X4_STATUS5_FEC_UNCORRECTEDBLKSH_3_UNCORCOUNTH_STREAM3_ALIGN 0 30286 #define RX_X4_STATUS5_FEC_UNCORRECTEDBLKSH_3_UNCORCOUNTH_STREAM3_BITS 16 30287 #define RX_X4_STATUS5_FEC_UNCORRECTEDBLKSH_3_UNCORCOUNTH_STREAM3_SHIFT 0 30288 30289 30290 /**************************************************************************** 30291 * RX_X4_Status5 :: fec_UncorrectedBlksH_4 30292 */ 30293 /* RX_X4_Status5 :: fec_UncorrectedBlksH_4 :: uncorCountH_stream4 [15:00] */ 30294 #define RX_X4_STATUS5_FEC_UNCORRECTEDBLKSH_4_UNCORCOUNTH_STREAM4_MASK 0xffff 30295 #define RX_X4_STATUS5_FEC_UNCORRECTEDBLKSH_4_UNCORCOUNTH_STREAM4_ALIGN 0 30296 #define RX_X4_STATUS5_FEC_UNCORRECTEDBLKSH_4_UNCORCOUNTH_STREAM4_BITS 16 30297 #define RX_X4_STATUS5_FEC_UNCORRECTEDBLKSH_4_UNCORCOUNTH_STREAM4_SHIFT 0 30298 30299 30300 /**************************************************************************** 30301 * TSC_WC4_TSC_USER4_Test1 30302 */ 30303 /**************************************************************************** 30304 * Test1 :: txpktcnt_U 30305 */ 30306 /* Test1 :: txpktcnt_U :: txpktcnt_U [15:00] */ 30307 #define TEST1_TXPKTCNT_U_TXPKTCNT_U_MASK 0xffff 30308 #define TEST1_TXPKTCNT_U_TXPKTCNT_U_ALIGN 0 30309 #define TEST1_TXPKTCNT_U_TXPKTCNT_U_BITS 16 30310 #define TEST1_TXPKTCNT_U_TXPKTCNT_U_SHIFT 0 30311 30312 30313 /**************************************************************************** 30314 * Test1 :: txpktcnt_L 30315 */ 30316 /* Test1 :: txpktcnt_L :: txpktcnt_L [15:00] */ 30317 #define TEST1_TXPKTCNT_L_TXPKTCNT_L_MASK 0xffff 30318 #define TEST1_TXPKTCNT_L_TXPKTCNT_L_ALIGN 0 30319 #define TEST1_TXPKTCNT_L_TXPKTCNT_L_BITS 16 30320 #define TEST1_TXPKTCNT_L_TXPKTCNT_L_SHIFT 0 30321 30322 30323 /**************************************************************************** 30324 * Test1 :: rxpktcnt_U 30325 */ 30326 /* Test1 :: rxpktcnt_U :: rxpktcnt_U [15:00] */ 30327 #define TEST1_RXPKTCNT_U_RXPKTCNT_U_MASK 0xffff 30328 #define TEST1_RXPKTCNT_U_RXPKTCNT_U_ALIGN 0 30329 #define TEST1_RXPKTCNT_U_RXPKTCNT_U_BITS 16 30330 #define TEST1_RXPKTCNT_U_RXPKTCNT_U_SHIFT 0 30331 30332 30333 /**************************************************************************** 30334 * Test1 :: rxpktcnt_L 30335 */ 30336 /* Test1 :: rxpktcnt_L :: rxpktcnt_L [15:00] */ 30337 #define TEST1_RXPKTCNT_L_RXPKTCNT_L_MASK 0xffff 30338 #define TEST1_RXPKTCNT_L_RXPKTCNT_L_ALIGN 0 30339 #define TEST1_RXPKTCNT_L_RXPKTCNT_L_BITS 16 30340 #define TEST1_RXPKTCNT_L_RXPKTCNT_L_SHIFT 0 30341 30342 30343 /**************************************************************************** 30344 * TSC_WC4_TSC_USER4_AN_X4_ABILITIES 30345 */ 30346 /**************************************************************************** 30347 * AN_X4_ABILITIES :: cl73_cfg 30348 */ 30349 /* AN_X4_ABILITIES :: cl73_cfg :: reserved0 [15:14] */ 30350 #define AN_X4_ABILITIES_CL73_CFG_RESERVED0_MASK 0xc000 30351 #define AN_X4_ABILITIES_CL73_CFG_RESERVED0_ALIGN 0 30352 #define AN_X4_ABILITIES_CL73_CFG_RESERVED0_BITS 2 30353 #define AN_X4_ABILITIES_CL73_CFG_RESERVED0_SHIFT 14 30354 30355 /* AN_X4_ABILITIES :: cl73_cfg :: disable_remote_fault [13:13] */ 30356 #define AN_X4_ABILITIES_CL73_CFG_DISABLE_REMOTE_FAULT_MASK 0x2000 30357 #define AN_X4_ABILITIES_CL73_CFG_DISABLE_REMOTE_FAULT_ALIGN 0 30358 #define AN_X4_ABILITIES_CL73_CFG_DISABLE_REMOTE_FAULT_BITS 1 30359 #define AN_X4_ABILITIES_CL73_CFG_DISABLE_REMOTE_FAULT_SHIFT 13 30360 30361 /* AN_X4_ABILITIES :: cl73_cfg :: num_advertised_lanes [12:11] */ 30362 #define AN_X4_ABILITIES_CL73_CFG_NUM_ADVERTISED_LANES_MASK 0x1800 30363 #define AN_X4_ABILITIES_CL73_CFG_NUM_ADVERTISED_LANES_ALIGN 0 30364 #define AN_X4_ABILITIES_CL73_CFG_NUM_ADVERTISED_LANES_BITS 2 30365 #define AN_X4_ABILITIES_CL73_CFG_NUM_ADVERTISED_LANES_SHIFT 11 30366 30367 /* AN_X4_ABILITIES :: cl73_cfg :: cl73_bam_enable [10:10] */ 30368 #define AN_X4_ABILITIES_CL73_CFG_CL73_BAM_ENABLE_MASK 0x0400 30369 #define AN_X4_ABILITIES_CL73_CFG_CL73_BAM_ENABLE_ALIGN 0 30370 #define AN_X4_ABILITIES_CL73_CFG_CL73_BAM_ENABLE_BITS 1 30371 #define AN_X4_ABILITIES_CL73_CFG_CL73_BAM_ENABLE_SHIFT 10 30372 30373 /* AN_X4_ABILITIES :: cl73_cfg :: cl73_hpam_enable [09:09] */ 30374 #define AN_X4_ABILITIES_CL73_CFG_CL73_HPAM_ENABLE_MASK 0x0200 30375 #define AN_X4_ABILITIES_CL73_CFG_CL73_HPAM_ENABLE_ALIGN 0 30376 #define AN_X4_ABILITIES_CL73_CFG_CL73_HPAM_ENABLE_BITS 1 30377 #define AN_X4_ABILITIES_CL73_CFG_CL73_HPAM_ENABLE_SHIFT 9 30378 30379 /* AN_X4_ABILITIES :: cl73_cfg :: cl73_enable [08:08] */ 30380 #define AN_X4_ABILITIES_CL73_CFG_CL73_ENABLE_MASK 0x0100 30381 #define AN_X4_ABILITIES_CL73_CFG_CL73_ENABLE_ALIGN 0 30382 #define AN_X4_ABILITIES_CL73_CFG_CL73_ENABLE_BITS 1 30383 #define AN_X4_ABILITIES_CL73_CFG_CL73_ENABLE_SHIFT 8 30384 30385 /* AN_X4_ABILITIES :: cl73_cfg :: reserved1 [07:07] */ 30386 #define AN_X4_ABILITIES_CL73_CFG_RESERVED1_MASK 0x0080 30387 #define AN_X4_ABILITIES_CL73_CFG_RESERVED1_ALIGN 0 30388 #define AN_X4_ABILITIES_CL73_CFG_RESERVED1_BITS 1 30389 #define AN_X4_ABILITIES_CL73_CFG_RESERVED1_SHIFT 7 30390 30391 /* AN_X4_ABILITIES :: cl73_cfg :: cl73_nonce_match_over [06:06] */ 30392 #define AN_X4_ABILITIES_CL73_CFG_CL73_NONCE_MATCH_OVER_MASK 0x0040 30393 #define AN_X4_ABILITIES_CL73_CFG_CL73_NONCE_MATCH_OVER_ALIGN 0 30394 #define AN_X4_ABILITIES_CL73_CFG_CL73_NONCE_MATCH_OVER_BITS 1 30395 #define AN_X4_ABILITIES_CL73_CFG_CL73_NONCE_MATCH_OVER_SHIFT 6 30396 30397 /* AN_X4_ABILITIES :: cl73_cfg :: cl73_nonce_match_val [05:05] */ 30398 #define AN_X4_ABILITIES_CL73_CFG_CL73_NONCE_MATCH_VAL_MASK 0x0020 30399 #define AN_X4_ABILITIES_CL73_CFG_CL73_NONCE_MATCH_VAL_ALIGN 0 30400 #define AN_X4_ABILITIES_CL73_CFG_CL73_NONCE_MATCH_VAL_BITS 1 30401 #define AN_X4_ABILITIES_CL73_CFG_CL73_NONCE_MATCH_VAL_SHIFT 5 30402 30403 /* AN_X4_ABILITIES :: cl73_cfg :: reserved2 [04:04] */ 30404 #define AN_X4_ABILITIES_CL73_CFG_RESERVED2_MASK 0x0010 30405 #define AN_X4_ABILITIES_CL73_CFG_RESERVED2_ALIGN 0 30406 #define AN_X4_ABILITIES_CL73_CFG_RESERVED2_BITS 1 30407 #define AN_X4_ABILITIES_CL73_CFG_RESERVED2_SHIFT 4 30408 30409 /* AN_X4_ABILITIES :: cl73_cfg :: bam_to_hpam_ad_en [03:03] */ 30410 #define AN_X4_ABILITIES_CL73_CFG_BAM_TO_HPAM_AD_EN_MASK 0x0008 30411 #define AN_X4_ABILITIES_CL73_CFG_BAM_TO_HPAM_AD_EN_ALIGN 0 30412 #define AN_X4_ABILITIES_CL73_CFG_BAM_TO_HPAM_AD_EN_BITS 1 30413 #define AN_X4_ABILITIES_CL73_CFG_BAM_TO_HPAM_AD_EN_SHIFT 3 30414 30415 /* AN_X4_ABILITIES :: cl73_cfg :: ad_to_cl73_en [02:02] */ 30416 #define AN_X4_ABILITIES_CL73_CFG_AD_TO_CL73_EN_MASK 0x0004 30417 #define AN_X4_ABILITIES_CL73_CFG_AD_TO_CL73_EN_ALIGN 0 30418 #define AN_X4_ABILITIES_CL73_CFG_AD_TO_CL73_EN_BITS 1 30419 #define AN_X4_ABILITIES_CL73_CFG_AD_TO_CL73_EN_SHIFT 2 30420 30421 /* AN_X4_ABILITIES :: cl73_cfg :: reserved3 [01:01] */ 30422 #define AN_X4_ABILITIES_CL73_CFG_RESERVED3_MASK 0x0002 30423 #define AN_X4_ABILITIES_CL73_CFG_RESERVED3_ALIGN 0 30424 #define AN_X4_ABILITIES_CL73_CFG_RESERVED3_BITS 1 30425 #define AN_X4_ABILITIES_CL73_CFG_RESERVED3_SHIFT 1 30426 30427 /* AN_X4_ABILITIES :: cl73_cfg :: cl73_an_restart [00:00] */ 30428 #define AN_X4_ABILITIES_CL73_CFG_CL73_AN_RESTART_MASK 0x0001 30429 #define AN_X4_ABILITIES_CL73_CFG_CL73_AN_RESTART_ALIGN 0 30430 #define AN_X4_ABILITIES_CL73_CFG_CL73_AN_RESTART_BITS 1 30431 #define AN_X4_ABILITIES_CL73_CFG_CL73_AN_RESTART_SHIFT 0 30432 30433 30434 /**************************************************************************** 30435 * AN_X4_ABILITIES :: ld_up1_abilities_0 30436 */ 30437 /* AN_X4_ABILITIES :: ld_up1_abilities_0 :: BAM_HG2 [15:15] */ 30438 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_HG2_MASK 0x8000 30439 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_HG2_ALIGN 0 30440 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_HG2_BITS 1 30441 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_HG2_SHIFT 15 30442 30443 /* AN_X4_ABILITIES :: ld_up1_abilities_0 :: reserved0 [14:10] */ 30444 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_RESERVED0_MASK 0x7c00 30445 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_RESERVED0_ALIGN 0 30446 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_RESERVED0_BITS 5 30447 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_RESERVED0_SHIFT 10 30448 30449 /* AN_X4_ABILITIES :: ld_up1_abilities_0 :: BAM_50G_CR4 [09:09] */ 30450 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_50G_CR4_MASK 0x0200 30451 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_50G_CR4_ALIGN 0 30452 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_50G_CR4_BITS 1 30453 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_50G_CR4_SHIFT 9 30454 30455 /* AN_X4_ABILITIES :: ld_up1_abilities_0 :: BAM_50G_KR4 [08:08] */ 30456 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_50G_KR4_MASK 0x0100 30457 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_50G_KR4_ALIGN 0 30458 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_50G_KR4_BITS 1 30459 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_50G_KR4_SHIFT 8 30460 30461 /* AN_X4_ABILITIES :: ld_up1_abilities_0 :: BAM_50G_CR2 [07:07] */ 30462 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_50G_CR2_MASK 0x0080 30463 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_50G_CR2_ALIGN 0 30464 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_50G_CR2_BITS 1 30465 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_50G_CR2_SHIFT 7 30466 30467 /* AN_X4_ABILITIES :: ld_up1_abilities_0 :: BAM_50G_KR2 [06:06] */ 30468 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_50G_KR2_MASK 0x0040 30469 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_50G_KR2_ALIGN 0 30470 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_50G_KR2_BITS 1 30471 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_50G_KR2_SHIFT 6 30472 30473 /* AN_X4_ABILITIES :: ld_up1_abilities_0 :: reserved1 [05:04] */ 30474 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_RESERVED1_MASK 0x0030 30475 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_RESERVED1_ALIGN 0 30476 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_RESERVED1_BITS 2 30477 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_RESERVED1_SHIFT 4 30478 30479 /* AN_X4_ABILITIES :: ld_up1_abilities_0 :: BAM_40G_CR2 [03:03] */ 30480 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_40G_CR2_MASK 0x0008 30481 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_40G_CR2_ALIGN 0 30482 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_40G_CR2_BITS 1 30483 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_40G_CR2_SHIFT 3 30484 30485 /* AN_X4_ABILITIES :: ld_up1_abilities_0 :: BAM_40G_KR2 [02:02] */ 30486 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_40G_KR2_MASK 0x0004 30487 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_40G_KR2_ALIGN 0 30488 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_40G_KR2_BITS 1 30489 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_40G_KR2_SHIFT 2 30490 30491 /* AN_X4_ABILITIES :: ld_up1_abilities_0 :: BAM_20G_CR2 [01:01] */ 30492 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_20G_CR2_MASK 0x0002 30493 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_20G_CR2_ALIGN 0 30494 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_20G_CR2_BITS 1 30495 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_20G_CR2_SHIFT 1 30496 30497 /* AN_X4_ABILITIES :: ld_up1_abilities_0 :: BAM_20G_KR2 [00:00] */ 30498 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_20G_KR2_MASK 0x0001 30499 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_20G_KR2_ALIGN 0 30500 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_20G_KR2_BITS 1 30501 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_20G_KR2_SHIFT 0 30502 30503 30504 /**************************************************************************** 30505 * AN_X4_ABILITIES :: ld_up1_abilities_1 30506 */ 30507 /* AN_X4_ABILITIES :: ld_up1_abilities_1 :: cl74_req [15:14] */ 30508 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_CL74_REQ_MASK 0xc000 30509 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_CL74_REQ_ALIGN 0 30510 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_CL74_REQ_BITS 2 30511 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_CL74_REQ_SHIFT 14 30512 30513 /* AN_X4_ABILITIES :: ld_up1_abilities_1 :: cl91_req [13:12] */ 30514 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_CL91_REQ_MASK 0x3000 30515 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_CL91_REQ_ALIGN 0 30516 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_CL91_REQ_BITS 2 30517 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_CL91_REQ_SHIFT 12 30518 30519 /* AN_X4_ABILITIES :: ld_up1_abilities_1 :: reserved0 [11:05] */ 30520 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_RESERVED0_MASK 0x0fe0 30521 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_RESERVED0_ALIGN 0 30522 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_RESERVED0_BITS 7 30523 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_RESERVED0_SHIFT 5 30524 30525 /* AN_X4_ABILITIES :: ld_up1_abilities_1 :: BAM_25G_CR1 [04:04] */ 30526 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_BAM_25G_CR1_MASK 0x0010 30527 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_BAM_25G_CR1_ALIGN 0 30528 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_BAM_25G_CR1_BITS 1 30529 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_BAM_25G_CR1_SHIFT 4 30530 30531 /* AN_X4_ABILITIES :: ld_up1_abilities_1 :: BAM_25G_KR1 [03:03] */ 30532 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_BAM_25G_KR1_MASK 0x0008 30533 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_BAM_25G_KR1_ALIGN 0 30534 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_BAM_25G_KR1_BITS 1 30535 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_BAM_25G_KR1_SHIFT 3 30536 30537 /* AN_X4_ABILITIES :: ld_up1_abilities_1 :: BAM_20G_CR1 [02:02] */ 30538 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_BAM_20G_CR1_MASK 0x0004 30539 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_BAM_20G_CR1_ALIGN 0 30540 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_BAM_20G_CR1_BITS 1 30541 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_BAM_20G_CR1_SHIFT 2 30542 30543 /* AN_X4_ABILITIES :: ld_up1_abilities_1 :: BAM_20G_KR1 [01:01] */ 30544 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_BAM_20G_KR1_MASK 0x0002 30545 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_BAM_20G_KR1_ALIGN 0 30546 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_BAM_20G_KR1_BITS 1 30547 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_BAM_20G_KR1_SHIFT 1 30548 30549 /* AN_X4_ABILITIES :: ld_up1_abilities_1 :: reserved1 [00:00] */ 30550 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_RESERVED1_MASK 0x0001 30551 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_RESERVED1_ALIGN 0 30552 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_RESERVED1_BITS 1 30553 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_RESERVED1_SHIFT 0 30554 30555 30556 /**************************************************************************** 30557 * AN_X4_ABILITIES :: ld_base_abilities_0 30558 */ 30559 /* AN_X4_ABILITIES :: ld_base_abilities_0 :: reserved0 [15:10] */ 30560 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_0_RESERVED0_MASK 0xfc00 30561 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_0_RESERVED0_ALIGN 0 30562 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_0_RESERVED0_BITS 6 30563 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_0_RESERVED0_SHIFT 10 30564 30565 /* AN_X4_ABILITIES :: ld_base_abilities_0 :: tx_nonce [09:05] */ 30566 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_0_TX_NONCE_MASK 0x03e0 30567 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_0_TX_NONCE_ALIGN 0 30568 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_0_TX_NONCE_BITS 5 30569 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_0_TX_NONCE_SHIFT 5 30570 30571 /* AN_X4_ABILITIES :: ld_base_abilities_0 :: cl73_base_selector [04:00] */ 30572 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_0_CL73_BASE_SELECTOR_MASK 0x001f 30573 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_0_CL73_BASE_SELECTOR_ALIGN 0 30574 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_0_CL73_BASE_SELECTOR_BITS 5 30575 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_0_CL73_BASE_SELECTOR_SHIFT 0 30576 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_0_CL73_BASE_SELECTOR_RESERVED 0 30577 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_0_CL73_BASE_SELECTOR_VALUE_802p3 1 30578 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_0_CL73_BASE_SELECTOR_VALUE_802p9 2 30579 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_0_CL73_BASE_SELECTOR_VALUE_802p5 3 30580 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_0_CL73_BASE_SELECTOR_VALUE_1394 4 30581 30582 30583 /**************************************************************************** 30584 * AN_X4_ABILITIES :: ld_base_abilities_1 30585 */ 30586 /* AN_X4_ABILITIES :: ld_base_abilities_1 :: reserved0 [15:12] */ 30587 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_RESERVED0_MASK 0xf000 30588 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_RESERVED0_ALIGN 0 30589 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_RESERVED0_BITS 4 30590 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_RESERVED0_SHIFT 12 30591 30592 /* AN_X4_ABILITIES :: ld_base_abilities_1 :: cl73_remote_fault [11:11] */ 30593 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_CL73_REMOTE_FAULT_MASK 0x0800 30594 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_CL73_REMOTE_FAULT_ALIGN 0 30595 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_CL73_REMOTE_FAULT_BITS 1 30596 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_CL73_REMOTE_FAULT_SHIFT 11 30597 30598 /* AN_X4_ABILITIES :: ld_base_abilities_1 :: next_page [10:10] */ 30599 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_NEXT_PAGE_MASK 0x0400 30600 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_NEXT_PAGE_ALIGN 0 30601 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_NEXT_PAGE_BITS 1 30602 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_NEXT_PAGE_SHIFT 10 30603 30604 /* AN_X4_ABILITIES :: ld_base_abilities_1 :: fec_req [09:08] */ 30605 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_FEC_REQ_MASK 0x0300 30606 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_FEC_REQ_ALIGN 0 30607 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_FEC_REQ_BITS 2 30608 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_FEC_REQ_SHIFT 8 30609 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_FEC_REQ_FEC_not_supported 0 30610 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_FEC_REQ_FEC_supported_but_not_requested 1 30611 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_FEC_REQ_invalid_setting 2 30612 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_FEC_REQ_FEC_supported_and_requested 3 30613 30614 /* AN_X4_ABILITIES :: ld_base_abilities_1 :: cl73_pause [07:06] */ 30615 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_CL73_PAUSE_MASK 0x00c0 30616 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_CL73_PAUSE_ALIGN 0 30617 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_CL73_PAUSE_BITS 2 30618 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_CL73_PAUSE_SHIFT 6 30619 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_CL73_PAUSE_No_PAUSE_ability 0 30620 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_CL73_PAUSE_Asymmetric_toward_link_partner_PAUSE_ability 2 30621 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_CL73_PAUSE_Symmetric_PAUSE_ability 1 30622 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_CL73_PAUSE_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 30623 30624 /* AN_X4_ABILITIES :: ld_base_abilities_1 :: BASE_1G_KX1 [05:05] */ 30625 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_BASE_1G_KX1_MASK 0x0020 30626 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_BASE_1G_KX1_ALIGN 0 30627 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_BASE_1G_KX1_BITS 1 30628 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_BASE_1G_KX1_SHIFT 5 30629 30630 /* AN_X4_ABILITIES :: ld_base_abilities_1 :: BASE_100G_CR4 [04:04] */ 30631 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_BASE_100G_CR4_MASK 0x0010 30632 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_BASE_100G_CR4_ALIGN 0 30633 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_BASE_100G_CR4_BITS 1 30634 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_BASE_100G_CR4_SHIFT 4 30635 30636 /* AN_X4_ABILITIES :: ld_base_abilities_1 :: BASE_100G_KR4 [03:03] */ 30637 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_BASE_100G_KR4_MASK 0x0008 30638 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_BASE_100G_KR4_ALIGN 0 30639 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_BASE_100G_KR4_BITS 1 30640 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_BASE_100G_KR4_SHIFT 3 30641 30642 /* AN_X4_ABILITIES :: ld_base_abilities_1 :: BASE_40G_CR4 [02:02] */ 30643 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_BASE_40G_CR4_MASK 0x0004 30644 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_BASE_40G_CR4_ALIGN 0 30645 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_BASE_40G_CR4_BITS 1 30646 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_BASE_40G_CR4_SHIFT 2 30647 30648 /* AN_X4_ABILITIES :: ld_base_abilities_1 :: BASE_40G_KR4 [01:01] */ 30649 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_BASE_40G_KR4_MASK 0x0002 30650 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_BASE_40G_KR4_ALIGN 0 30651 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_BASE_40G_KR4_BITS 1 30652 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_BASE_40G_KR4_SHIFT 1 30653 30654 /* AN_X4_ABILITIES :: ld_base_abilities_1 :: BASE_10G_KR1 [00:00] */ 30655 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_BASE_10G_KR1_MASK 0x0001 30656 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_BASE_10G_KR1_ALIGN 0 30657 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_BASE_10G_KR1_BITS 1 30658 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_BASE_10G_KR1_SHIFT 0 30659 30660 30661 /**************************************************************************** 30662 * AN_X4_ABILITIES :: ld_bam_abilities 30663 */ 30664 /* AN_X4_ABILITIES :: ld_bam_abilities :: reserved0 [15:09] */ 30665 #define AN_X4_ABILITIES_LD_BAM_ABILITIES_RESERVED0_MASK 0xfe00 30666 #define AN_X4_ABILITIES_LD_BAM_ABILITIES_RESERVED0_ALIGN 0 30667 #define AN_X4_ABILITIES_LD_BAM_ABILITIES_RESERVED0_BITS 7 30668 #define AN_X4_ABILITIES_LD_BAM_ABILITIES_RESERVED0_SHIFT 9 30669 30670 /* AN_X4_ABILITIES :: ld_bam_abilities :: cl73_bam_code [08:00] */ 30671 #define AN_X4_ABILITIES_LD_BAM_ABILITIES_CL73_BAM_CODE_MASK 0x01ff 30672 #define AN_X4_ABILITIES_LD_BAM_ABILITIES_CL73_BAM_CODE_ALIGN 0 30673 #define AN_X4_ABILITIES_LD_BAM_ABILITIES_CL73_BAM_CODE_BITS 9 30674 #define AN_X4_ABILITIES_LD_BAM_ABILITIES_CL73_BAM_CODE_SHIFT 0 30675 30676 30677 /**************************************************************************** 30678 * AN_X4_ABILITIES :: cl73_controls 30679 */ 30680 /* AN_X4_ABILITIES :: cl73_controls :: an_oui_override_bam73_adv [15:15] */ 30681 #define AN_X4_ABILITIES_CL73_CONTROLS_AN_OUI_OVERRIDE_BAM73_ADV_MASK 0x8000 30682 #define AN_X4_ABILITIES_CL73_CONTROLS_AN_OUI_OVERRIDE_BAM73_ADV_ALIGN 0 30683 #define AN_X4_ABILITIES_CL73_CONTROLS_AN_OUI_OVERRIDE_BAM73_ADV_BITS 1 30684 #define AN_X4_ABILITIES_CL73_CONTROLS_AN_OUI_OVERRIDE_BAM73_ADV_SHIFT 15 30685 30686 /* AN_X4_ABILITIES :: cl73_controls :: an_oui_override_bam73_det [14:14] */ 30687 #define AN_X4_ABILITIES_CL73_CONTROLS_AN_OUI_OVERRIDE_BAM73_DET_MASK 0x4000 30688 #define AN_X4_ABILITIES_CL73_CONTROLS_AN_OUI_OVERRIDE_BAM73_DET_ALIGN 0 30689 #define AN_X4_ABILITIES_CL73_CONTROLS_AN_OUI_OVERRIDE_BAM73_DET_BITS 1 30690 #define AN_X4_ABILITIES_CL73_CONTROLS_AN_OUI_OVERRIDE_BAM73_DET_SHIFT 14 30691 30692 /* AN_X4_ABILITIES :: cl73_controls :: an_oui_override_hpam_adv [13:13] */ 30693 #define AN_X4_ABILITIES_CL73_CONTROLS_AN_OUI_OVERRIDE_HPAM_ADV_MASK 0x2000 30694 #define AN_X4_ABILITIES_CL73_CONTROLS_AN_OUI_OVERRIDE_HPAM_ADV_ALIGN 0 30695 #define AN_X4_ABILITIES_CL73_CONTROLS_AN_OUI_OVERRIDE_HPAM_ADV_BITS 1 30696 #define AN_X4_ABILITIES_CL73_CONTROLS_AN_OUI_OVERRIDE_HPAM_ADV_SHIFT 13 30697 30698 /* AN_X4_ABILITIES :: cl73_controls :: an_oui_override_hpam_det [12:12] */ 30699 #define AN_X4_ABILITIES_CL73_CONTROLS_AN_OUI_OVERRIDE_HPAM_DET_MASK 0x1000 30700 #define AN_X4_ABILITIES_CL73_CONTROLS_AN_OUI_OVERRIDE_HPAM_DET_ALIGN 0 30701 #define AN_X4_ABILITIES_CL73_CONTROLS_AN_OUI_OVERRIDE_HPAM_DET_BITS 1 30702 #define AN_X4_ABILITIES_CL73_CONTROLS_AN_OUI_OVERRIDE_HPAM_DET_SHIFT 12 30703 30704 /* AN_X4_ABILITIES :: cl73_controls :: reserved0 [11:10] */ 30705 #define AN_X4_ABILITIES_CL73_CONTROLS_RESERVED0_MASK 0x0c00 30706 #define AN_X4_ABILITIES_CL73_CONTROLS_RESERVED0_ALIGN 0 30707 #define AN_X4_ABILITIES_CL73_CONTROLS_RESERVED0_BITS 2 30708 #define AN_X4_ABILITIES_CL73_CONTROLS_RESERVED0_SHIFT 10 30709 30710 /* AN_X4_ABILITIES :: cl73_controls :: an_fail_count_limit [09:06] */ 30711 #define AN_X4_ABILITIES_CL73_CONTROLS_AN_FAIL_COUNT_LIMIT_MASK 0x03c0 30712 #define AN_X4_ABILITIES_CL73_CONTROLS_AN_FAIL_COUNT_LIMIT_ALIGN 0 30713 #define AN_X4_ABILITIES_CL73_CONTROLS_AN_FAIL_COUNT_LIMIT_BITS 4 30714 #define AN_X4_ABILITIES_CL73_CONTROLS_AN_FAIL_COUNT_LIMIT_SHIFT 6 30715 30716 /* AN_X4_ABILITIES :: cl73_controls :: linkFailTimerQual_en [05:05] */ 30717 #define AN_X4_ABILITIES_CL73_CONTROLS_LINKFAILTIMERQUAL_EN_MASK 0x0020 30718 #define AN_X4_ABILITIES_CL73_CONTROLS_LINKFAILTIMERQUAL_EN_ALIGN 0 30719 #define AN_X4_ABILITIES_CL73_CONTROLS_LINKFAILTIMERQUAL_EN_BITS 1 30720 #define AN_X4_ABILITIES_CL73_CONTROLS_LINKFAILTIMERQUAL_EN_SHIFT 5 30721 30722 /* AN_X4_ABILITIES :: cl73_controls :: linkFailTimer_dis [04:04] */ 30723 #define AN_X4_ABILITIES_CL73_CONTROLS_LINKFAILTIMER_DIS_MASK 0x0010 30724 #define AN_X4_ABILITIES_CL73_CONTROLS_LINKFAILTIMER_DIS_ALIGN 0 30725 #define AN_X4_ABILITIES_CL73_CONTROLS_LINKFAILTIMER_DIS_BITS 1 30726 #define AN_X4_ABILITIES_CL73_CONTROLS_LINKFAILTIMER_DIS_SHIFT 4 30727 30728 /* AN_X4_ABILITIES :: cl73_controls :: an_good_check_trap [03:03] */ 30729 #define AN_X4_ABILITIES_CL73_CONTROLS_AN_GOOD_CHECK_TRAP_MASK 0x0008 30730 #define AN_X4_ABILITIES_CL73_CONTROLS_AN_GOOD_CHECK_TRAP_ALIGN 0 30731 #define AN_X4_ABILITIES_CL73_CONTROLS_AN_GOOD_CHECK_TRAP_BITS 1 30732 #define AN_X4_ABILITIES_CL73_CONTROLS_AN_GOOD_CHECK_TRAP_SHIFT 3 30733 30734 /* AN_X4_ABILITIES :: cl73_controls :: an_good_trap [02:02] */ 30735 #define AN_X4_ABILITIES_CL73_CONTROLS_AN_GOOD_TRAP_MASK 0x0004 30736 #define AN_X4_ABILITIES_CL73_CONTROLS_AN_GOOD_TRAP_ALIGN 0 30737 #define AN_X4_ABILITIES_CL73_CONTROLS_AN_GOOD_TRAP_BITS 1 30738 #define AN_X4_ABILITIES_CL73_CONTROLS_AN_GOOD_TRAP_SHIFT 2 30739 30740 /* AN_X4_ABILITIES :: cl73_controls :: pd_KX_en [01:01] */ 30741 #define AN_X4_ABILITIES_CL73_CONTROLS_PD_KX_EN_MASK 0x0002 30742 #define AN_X4_ABILITIES_CL73_CONTROLS_PD_KX_EN_ALIGN 0 30743 #define AN_X4_ABILITIES_CL73_CONTROLS_PD_KX_EN_BITS 1 30744 #define AN_X4_ABILITIES_CL73_CONTROLS_PD_KX_EN_SHIFT 1 30745 30746 /* AN_X4_ABILITIES :: cl73_controls :: reserved1 [00:00] */ 30747 #define AN_X4_ABILITIES_CL73_CONTROLS_RESERVED1_MASK 0x0001 30748 #define AN_X4_ABILITIES_CL73_CONTROLS_RESERVED1_ALIGN 0 30749 #define AN_X4_ABILITIES_CL73_CONTROLS_RESERVED1_BITS 1 30750 #define AN_X4_ABILITIES_CL73_CONTROLS_RESERVED1_SHIFT 0 30751 30752 30753 /**************************************************************************** 30754 * AN_X4_ABILITIES :: ld_base_abilities_2 30755 */ 30756 /* AN_X4_ABILITIES :: ld_base_abilities_2 :: reserved0 [15:12] */ 30757 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_2_RESERVED0_MASK 0xf000 30758 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_2_RESERVED0_ALIGN 0 30759 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_2_RESERVED0_BITS 4 30760 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_2_RESERVED0_SHIFT 12 30761 30762 /* AN_X4_ABILITIES :: ld_base_abilities_2 :: BASE_50G_KR2_SEL [11:07] */ 30763 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_2_BASE_50G_KR2_SEL_MASK 0x0f80 30764 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_2_BASE_50G_KR2_SEL_ALIGN 0 30765 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_2_BASE_50G_KR2_SEL_BITS 5 30766 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_2_BASE_50G_KR2_SEL_SHIFT 7 30767 30768 /* AN_X4_ABILITIES :: ld_base_abilities_2 :: BASE_50G_KR2_EN [06:06] */ 30769 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_2_BASE_50G_KR2_EN_MASK 0x0040 30770 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_2_BASE_50G_KR2_EN_ALIGN 0 30771 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_2_BASE_50G_KR2_EN_BITS 1 30772 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_2_BASE_50G_KR2_EN_SHIFT 6 30773 30774 /* AN_X4_ABILITIES :: ld_base_abilities_2 :: BASE_50G_CR2_SEL [05:01] */ 30775 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_2_BASE_50G_CR2_SEL_MASK 0x003e 30776 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_2_BASE_50G_CR2_SEL_ALIGN 0 30777 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_2_BASE_50G_CR2_SEL_BITS 5 30778 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_2_BASE_50G_CR2_SEL_SHIFT 1 30779 30780 /* AN_X4_ABILITIES :: ld_base_abilities_2 :: BASE_50G_CR2_EN [00:00] */ 30781 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_2_BASE_50G_CR2_EN_MASK 0x0001 30782 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_2_BASE_50G_CR2_EN_ALIGN 0 30783 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_2_BASE_50G_CR2_EN_BITS 1 30784 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_2_BASE_50G_CR2_EN_SHIFT 0 30785 30786 30787 /**************************************************************************** 30788 * AN_X4_ABILITIES :: ld_base_abilities_3 30789 */ 30790 /* AN_X4_ABILITIES :: ld_base_abilities_3 :: reserved0 [15:12] */ 30791 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_3_RESERVED0_MASK 0xf000 30792 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_3_RESERVED0_ALIGN 0 30793 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_3_RESERVED0_BITS 4 30794 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_3_RESERVED0_SHIFT 12 30795 30796 /* AN_X4_ABILITIES :: ld_base_abilities_3 :: BASE_25G_KR1_SEL [11:07] */ 30797 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_3_BASE_25G_KR1_SEL_MASK 0x0f80 30798 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_3_BASE_25G_KR1_SEL_ALIGN 0 30799 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_3_BASE_25G_KR1_SEL_BITS 5 30800 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_3_BASE_25G_KR1_SEL_SHIFT 7 30801 30802 /* AN_X4_ABILITIES :: ld_base_abilities_3 :: BASE_25G_KR1_EN [06:06] */ 30803 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_3_BASE_25G_KR1_EN_MASK 0x0040 30804 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_3_BASE_25G_KR1_EN_ALIGN 0 30805 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_3_BASE_25G_KR1_EN_BITS 1 30806 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_3_BASE_25G_KR1_EN_SHIFT 6 30807 30808 /* AN_X4_ABILITIES :: ld_base_abilities_3 :: BASE_25G_CR1_SEL [05:01] */ 30809 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_3_BASE_25G_CR1_SEL_MASK 0x003e 30810 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_3_BASE_25G_CR1_SEL_ALIGN 0 30811 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_3_BASE_25G_CR1_SEL_BITS 5 30812 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_3_BASE_25G_CR1_SEL_SHIFT 1 30813 30814 /* AN_X4_ABILITIES :: ld_base_abilities_3 :: BASE_25G_CR1_EN [00:00] */ 30815 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_3_BASE_25G_CR1_EN_MASK 0x0001 30816 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_3_BASE_25G_CR1_EN_ALIGN 0 30817 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_3_BASE_25G_CR1_EN_BITS 1 30818 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_3_BASE_25G_CR1_EN_SHIFT 0 30819 30820 30821 /**************************************************************************** 30822 * AN_X4_ABILITIES :: ld_base_abilities_4 30823 */ 30824 /* AN_X4_ABILITIES :: ld_base_abilities_4 :: reserved0 [15:12] */ 30825 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_4_RESERVED0_MASK 0xf000 30826 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_4_RESERVED0_ALIGN 0 30827 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_4_RESERVED0_BITS 4 30828 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_4_RESERVED0_SHIFT 12 30829 30830 /* AN_X4_ABILITIES :: ld_base_abilities_4 :: BASE_25G_KRS1_SEL [11:07] */ 30831 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_4_BASE_25G_KRS1_SEL_MASK 0x0f80 30832 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_4_BASE_25G_KRS1_SEL_ALIGN 0 30833 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_4_BASE_25G_KRS1_SEL_BITS 5 30834 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_4_BASE_25G_KRS1_SEL_SHIFT 7 30835 30836 /* AN_X4_ABILITIES :: ld_base_abilities_4 :: BASE_25G_KRS1_EN [06:06] */ 30837 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_4_BASE_25G_KRS1_EN_MASK 0x0040 30838 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_4_BASE_25G_KRS1_EN_ALIGN 0 30839 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_4_BASE_25G_KRS1_EN_BITS 1 30840 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_4_BASE_25G_KRS1_EN_SHIFT 6 30841 30842 /* AN_X4_ABILITIES :: ld_base_abilities_4 :: BASE_25G_CRS1_SEL [05:01] */ 30843 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_4_BASE_25G_CRS1_SEL_MASK 0x003e 30844 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_4_BASE_25G_CRS1_SEL_ALIGN 0 30845 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_4_BASE_25G_CRS1_SEL_BITS 5 30846 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_4_BASE_25G_CRS1_SEL_SHIFT 1 30847 30848 /* AN_X4_ABILITIES :: ld_base_abilities_4 :: BASE_25G_CRS1_EN [00:00] */ 30849 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_4_BASE_25G_CRS1_EN_MASK 0x0001 30850 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_4_BASE_25G_CRS1_EN_ALIGN 0 30851 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_4_BASE_25G_CRS1_EN_BITS 1 30852 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_4_BASE_25G_CRS1_EN_SHIFT 0 30853 30854 30855 /**************************************************************************** 30856 * AN_X4_ABILITIES :: ld_fec_basepage_abilities 30857 */ 30858 /* AN_X4_ABILITIES :: ld_fec_basepage_abilities :: reserved0 [15:12] */ 30859 #define AN_X4_ABILITIES_LD_FEC_BASEPAGE_ABILITIES_RESERVED0_MASK 0xf000 30860 #define AN_X4_ABILITIES_LD_FEC_BASEPAGE_ABILITIES_RESERVED0_ALIGN 0 30861 #define AN_X4_ABILITIES_LD_FEC_BASEPAGE_ABILITIES_RESERVED0_BITS 4 30862 #define AN_X4_ABILITIES_LD_FEC_BASEPAGE_ABILITIES_RESERVED0_SHIFT 12 30863 30864 /* AN_X4_ABILITIES :: ld_fec_basepage_abilities :: BASE_R_FEC_REQ_SEL [11:07] */ 30865 #define AN_X4_ABILITIES_LD_FEC_BASEPAGE_ABILITIES_BASE_R_FEC_REQ_SEL_MASK 0x0f80 30866 #define AN_X4_ABILITIES_LD_FEC_BASEPAGE_ABILITIES_BASE_R_FEC_REQ_SEL_ALIGN 0 30867 #define AN_X4_ABILITIES_LD_FEC_BASEPAGE_ABILITIES_BASE_R_FEC_REQ_SEL_BITS 5 30868 #define AN_X4_ABILITIES_LD_FEC_BASEPAGE_ABILITIES_BASE_R_FEC_REQ_SEL_SHIFT 7 30869 30870 /* AN_X4_ABILITIES :: ld_fec_basepage_abilities :: BASE_R_FEC_REQ_EN [06:06] */ 30871 #define AN_X4_ABILITIES_LD_FEC_BASEPAGE_ABILITIES_BASE_R_FEC_REQ_EN_MASK 0x0040 30872 #define AN_X4_ABILITIES_LD_FEC_BASEPAGE_ABILITIES_BASE_R_FEC_REQ_EN_ALIGN 0 30873 #define AN_X4_ABILITIES_LD_FEC_BASEPAGE_ABILITIES_BASE_R_FEC_REQ_EN_BITS 1 30874 #define AN_X4_ABILITIES_LD_FEC_BASEPAGE_ABILITIES_BASE_R_FEC_REQ_EN_SHIFT 6 30875 30876 /* AN_X4_ABILITIES :: ld_fec_basepage_abilities :: RS_FEC_REQ_SEL [05:01] */ 30877 #define AN_X4_ABILITIES_LD_FEC_BASEPAGE_ABILITIES_RS_FEC_REQ_SEL_MASK 0x003e 30878 #define AN_X4_ABILITIES_LD_FEC_BASEPAGE_ABILITIES_RS_FEC_REQ_SEL_ALIGN 0 30879 #define AN_X4_ABILITIES_LD_FEC_BASEPAGE_ABILITIES_RS_FEC_REQ_SEL_BITS 5 30880 #define AN_X4_ABILITIES_LD_FEC_BASEPAGE_ABILITIES_RS_FEC_REQ_SEL_SHIFT 1 30881 30882 /* AN_X4_ABILITIES :: ld_fec_basepage_abilities :: RS_FEC_REQ_EN [00:00] */ 30883 #define AN_X4_ABILITIES_LD_FEC_BASEPAGE_ABILITIES_RS_FEC_REQ_EN_MASK 0x0001 30884 #define AN_X4_ABILITIES_LD_FEC_BASEPAGE_ABILITIES_RS_FEC_REQ_EN_ALIGN 0 30885 #define AN_X4_ABILITIES_LD_FEC_BASEPAGE_ABILITIES_RS_FEC_REQ_EN_BITS 1 30886 #define AN_X4_ABILITIES_LD_FEC_BASEPAGE_ABILITIES_RS_FEC_REQ_EN_SHIFT 0 30887 30888 30889 /**************************************************************************** 30890 * AN_X4_ABILITIES :: sw_an_base_page_0 30891 */ 30892 /* AN_X4_ABILITIES :: sw_an_base_page_0 :: sw_an_bp_0 [15:00] */ 30893 #define AN_X4_ABILITIES_SW_AN_BASE_PAGE_0_SW_AN_BP_0_MASK 0xffff 30894 #define AN_X4_ABILITIES_SW_AN_BASE_PAGE_0_SW_AN_BP_0_ALIGN 0 30895 #define AN_X4_ABILITIES_SW_AN_BASE_PAGE_0_SW_AN_BP_0_BITS 16 30896 #define AN_X4_ABILITIES_SW_AN_BASE_PAGE_0_SW_AN_BP_0_SHIFT 0 30897 30898 30899 /**************************************************************************** 30900 * AN_X4_ABILITIES :: sw_an_base_page_1 30901 */ 30902 /* AN_X4_ABILITIES :: sw_an_base_page_1 :: sw_an_bp_1 [15:00] */ 30903 #define AN_X4_ABILITIES_SW_AN_BASE_PAGE_1_SW_AN_BP_1_MASK 0xffff 30904 #define AN_X4_ABILITIES_SW_AN_BASE_PAGE_1_SW_AN_BP_1_ALIGN 0 30905 #define AN_X4_ABILITIES_SW_AN_BASE_PAGE_1_SW_AN_BP_1_BITS 16 30906 #define AN_X4_ABILITIES_SW_AN_BASE_PAGE_1_SW_AN_BP_1_SHIFT 0 30907 30908 30909 /**************************************************************************** 30910 * AN_X4_ABILITIES :: sw_an_base_page_2 30911 */ 30912 /* AN_X4_ABILITIES :: sw_an_base_page_2 :: sw_an_bp_2 [15:00] */ 30913 #define AN_X4_ABILITIES_SW_AN_BASE_PAGE_2_SW_AN_BP_2_MASK 0xffff 30914 #define AN_X4_ABILITIES_SW_AN_BASE_PAGE_2_SW_AN_BP_2_ALIGN 0 30915 #define AN_X4_ABILITIES_SW_AN_BASE_PAGE_2_SW_AN_BP_2_BITS 16 30916 #define AN_X4_ABILITIES_SW_AN_BASE_PAGE_2_SW_AN_BP_2_SHIFT 0 30917 30918 30919 /**************************************************************************** 30920 * TSC_WC4_TSC_USER4_AN_X4_STATUS 30921 */ 30922 /**************************************************************************** 30923 * AN_X4_STATUS :: r_cl73_status 30924 */ 30925 /* AN_X4_STATUS :: r_cl73_status :: reserved0 [15:12] */ 30926 #define AN_X4_STATUS_R_CL73_STATUS_RESERVED0_MASK 0xf000 30927 #define AN_X4_STATUS_R_CL73_STATUS_RESERVED0_ALIGN 0 30928 #define AN_X4_STATUS_R_CL73_STATUS_RESERVED0_BITS 4 30929 #define AN_X4_STATUS_R_CL73_STATUS_RESERVED0_SHIFT 12 30930 30931 /* AN_X4_STATUS :: r_cl73_status :: cl73_fifo_full [11:11] */ 30932 #define AN_X4_STATUS_R_CL73_STATUS_CL73_FIFO_FULL_MASK 0x0800 30933 #define AN_X4_STATUS_R_CL73_STATUS_CL73_FIFO_FULL_ALIGN 0 30934 #define AN_X4_STATUS_R_CL73_STATUS_CL73_FIFO_FULL_BITS 1 30935 #define AN_X4_STATUS_R_CL73_STATUS_CL73_FIFO_FULL_SHIFT 11 30936 30937 /* AN_X4_STATUS :: r_cl73_status :: dme_locked [10:10] */ 30938 #define AN_X4_STATUS_R_CL73_STATUS_DME_LOCKED_MASK 0x0400 30939 #define AN_X4_STATUS_R_CL73_STATUS_DME_LOCKED_ALIGN 0 30940 #define AN_X4_STATUS_R_CL73_STATUS_DME_LOCKED_BITS 1 30941 #define AN_X4_STATUS_R_CL73_STATUS_DME_LOCKED_SHIFT 10 30942 30943 /* AN_X4_STATUS :: r_cl73_status :: pulse_too_short [09:09] */ 30944 #define AN_X4_STATUS_R_CL73_STATUS_PULSE_TOO_SHORT_MASK 0x0200 30945 #define AN_X4_STATUS_R_CL73_STATUS_PULSE_TOO_SHORT_ALIGN 0 30946 #define AN_X4_STATUS_R_CL73_STATUS_PULSE_TOO_SHORT_BITS 1 30947 #define AN_X4_STATUS_R_CL73_STATUS_PULSE_TOO_SHORT_SHIFT 9 30948 30949 /* AN_X4_STATUS :: r_cl73_status :: pulse_too_moderate [08:08] */ 30950 #define AN_X4_STATUS_R_CL73_STATUS_PULSE_TOO_MODERATE_MASK 0x0100 30951 #define AN_X4_STATUS_R_CL73_STATUS_PULSE_TOO_MODERATE_ALIGN 0 30952 #define AN_X4_STATUS_R_CL73_STATUS_PULSE_TOO_MODERATE_BITS 1 30953 #define AN_X4_STATUS_R_CL73_STATUS_PULSE_TOO_MODERATE_SHIFT 8 30954 30955 /* AN_X4_STATUS :: r_cl73_status :: pulse_too_long [07:07] */ 30956 #define AN_X4_STATUS_R_CL73_STATUS_PULSE_TOO_LONG_MASK 0x0080 30957 #define AN_X4_STATUS_R_CL73_STATUS_PULSE_TOO_LONG_ALIGN 0 30958 #define AN_X4_STATUS_R_CL73_STATUS_PULSE_TOO_LONG_BITS 1 30959 #define AN_X4_STATUS_R_CL73_STATUS_PULSE_TOO_LONG_SHIFT 7 30960 30961 /* AN_X4_STATUS :: r_cl73_status :: page_too_short [06:06] */ 30962 #define AN_X4_STATUS_R_CL73_STATUS_PAGE_TOO_SHORT_MASK 0x0040 30963 #define AN_X4_STATUS_R_CL73_STATUS_PAGE_TOO_SHORT_ALIGN 0 30964 #define AN_X4_STATUS_R_CL73_STATUS_PAGE_TOO_SHORT_BITS 1 30965 #define AN_X4_STATUS_R_CL73_STATUS_PAGE_TOO_SHORT_SHIFT 6 30966 30967 /* AN_X4_STATUS :: r_cl73_status :: page_too_long [05:05] */ 30968 #define AN_X4_STATUS_R_CL73_STATUS_PAGE_TOO_LONG_MASK 0x0020 30969 #define AN_X4_STATUS_R_CL73_STATUS_PAGE_TOO_LONG_ALIGN 0 30970 #define AN_X4_STATUS_R_CL73_STATUS_PAGE_TOO_LONG_BITS 1 30971 #define AN_X4_STATUS_R_CL73_STATUS_PAGE_TOO_LONG_SHIFT 5 30972 30973 /* AN_X4_STATUS :: r_cl73_status :: clk_trans_miss [04:04] */ 30974 #define AN_X4_STATUS_R_CL73_STATUS_CLK_TRANS_MISS_MASK 0x0010 30975 #define AN_X4_STATUS_R_CL73_STATUS_CLK_TRANS_MISS_ALIGN 0 30976 #define AN_X4_STATUS_R_CL73_STATUS_CLK_TRANS_MISS_BITS 1 30977 #define AN_X4_STATUS_R_CL73_STATUS_CLK_TRANS_MISS_SHIFT 4 30978 30979 /* AN_X4_STATUS :: r_cl73_status :: dme_mv_pair [03:03] */ 30980 #define AN_X4_STATUS_R_CL73_STATUS_DME_MV_PAIR_MASK 0x0008 30981 #define AN_X4_STATUS_R_CL73_STATUS_DME_MV_PAIR_ALIGN 0 30982 #define AN_X4_STATUS_R_CL73_STATUS_DME_MV_PAIR_BITS 1 30983 #define AN_X4_STATUS_R_CL73_STATUS_DME_MV_PAIR_SHIFT 3 30984 30985 /* AN_X4_STATUS :: r_cl73_status :: dme_page [02:02] */ 30986 #define AN_X4_STATUS_R_CL73_STATUS_DME_PAGE_MASK 0x0004 30987 #define AN_X4_STATUS_R_CL73_STATUS_DME_PAGE_ALIGN 0 30988 #define AN_X4_STATUS_R_CL73_STATUS_DME_PAGE_BITS 1 30989 #define AN_X4_STATUS_R_CL73_STATUS_DME_PAGE_SHIFT 2 30990 30991 /* AN_X4_STATUS :: r_cl73_status :: dme_state [01:00] */ 30992 #define AN_X4_STATUS_R_CL73_STATUS_DME_STATE_MASK 0x0003 30993 #define AN_X4_STATUS_R_CL73_STATUS_DME_STATE_ALIGN 0 30994 #define AN_X4_STATUS_R_CL73_STATUS_DME_STATE_BITS 2 30995 #define AN_X4_STATUS_R_CL73_STATUS_DME_STATE_SHIFT 0 30996 30997 30998 /**************************************************************************** 30999 * AN_X4_STATUS :: pxng_status 31000 */ 31001 /* AN_X4_STATUS :: pxng_status :: reserved0 [15:09] */ 31002 #define AN_X4_STATUS_PXNG_STATUS_RESERVED0_MASK 0xfe00 31003 #define AN_X4_STATUS_PXNG_STATUS_RESERVED0_ALIGN 0 31004 #define AN_X4_STATUS_PXNG_STATUS_RESERVED0_BITS 7 31005 #define AN_X4_STATUS_PXNG_STATUS_RESERVED0_SHIFT 9 31006 31007 /* AN_X4_STATUS :: pxng_status :: an_good_check [08:08] */ 31008 #define AN_X4_STATUS_PXNG_STATUS_AN_GOOD_CHECK_MASK 0x0100 31009 #define AN_X4_STATUS_PXNG_STATUS_AN_GOOD_CHECK_ALIGN 0 31010 #define AN_X4_STATUS_PXNG_STATUS_AN_GOOD_CHECK_BITS 1 31011 #define AN_X4_STATUS_PXNG_STATUS_AN_GOOD_CHECK_SHIFT 8 31012 31013 /* AN_X4_STATUS :: pxng_status :: next_page_wait [07:07] */ 31014 #define AN_X4_STATUS_PXNG_STATUS_NEXT_PAGE_WAIT_MASK 0x0080 31015 #define AN_X4_STATUS_PXNG_STATUS_NEXT_PAGE_WAIT_ALIGN 0 31016 #define AN_X4_STATUS_PXNG_STATUS_NEXT_PAGE_WAIT_BITS 1 31017 #define AN_X4_STATUS_PXNG_STATUS_NEXT_PAGE_WAIT_SHIFT 7 31018 31019 /* AN_X4_STATUS :: pxng_status :: transmit_disable [06:06] */ 31020 #define AN_X4_STATUS_PXNG_STATUS_TRANSMIT_DISABLE_MASK 0x0040 31021 #define AN_X4_STATUS_PXNG_STATUS_TRANSMIT_DISABLE_ALIGN 0 31022 #define AN_X4_STATUS_PXNG_STATUS_TRANSMIT_DISABLE_BITS 1 31023 #define AN_X4_STATUS_PXNG_STATUS_TRANSMIT_DISABLE_SHIFT 6 31024 31025 /* AN_X4_STATUS :: pxng_status :: error_state [05:05] */ 31026 #define AN_X4_STATUS_PXNG_STATUS_ERROR_STATE_MASK 0x0020 31027 #define AN_X4_STATUS_PXNG_STATUS_ERROR_STATE_ALIGN 0 31028 #define AN_X4_STATUS_PXNG_STATUS_ERROR_STATE_BITS 1 31029 #define AN_X4_STATUS_PXNG_STATUS_ERROR_STATE_SHIFT 5 31030 31031 /* AN_X4_STATUS :: pxng_status :: an_enable [04:04] */ 31032 #define AN_X4_STATUS_PXNG_STATUS_AN_ENABLE_MASK 0x0010 31033 #define AN_X4_STATUS_PXNG_STATUS_AN_ENABLE_ALIGN 0 31034 #define AN_X4_STATUS_PXNG_STATUS_AN_ENABLE_BITS 1 31035 #define AN_X4_STATUS_PXNG_STATUS_AN_ENABLE_SHIFT 4 31036 31037 /* AN_X4_STATUS :: pxng_status :: ability_detect [03:03] */ 31038 #define AN_X4_STATUS_PXNG_STATUS_ABILITY_DETECT_MASK 0x0008 31039 #define AN_X4_STATUS_PXNG_STATUS_ABILITY_DETECT_ALIGN 0 31040 #define AN_X4_STATUS_PXNG_STATUS_ABILITY_DETECT_BITS 1 31041 #define AN_X4_STATUS_PXNG_STATUS_ABILITY_DETECT_SHIFT 3 31042 31043 /* AN_X4_STATUS :: pxng_status :: ack_detect [02:02] */ 31044 #define AN_X4_STATUS_PXNG_STATUS_ACK_DETECT_MASK 0x0004 31045 #define AN_X4_STATUS_PXNG_STATUS_ACK_DETECT_ALIGN 0 31046 #define AN_X4_STATUS_PXNG_STATUS_ACK_DETECT_BITS 1 31047 #define AN_X4_STATUS_PXNG_STATUS_ACK_DETECT_SHIFT 2 31048 31049 /* AN_X4_STATUS :: pxng_status :: complete_ack [01:01] */ 31050 #define AN_X4_STATUS_PXNG_STATUS_COMPLETE_ACK_MASK 0x0002 31051 #define AN_X4_STATUS_PXNG_STATUS_COMPLETE_ACK_ALIGN 0 31052 #define AN_X4_STATUS_PXNG_STATUS_COMPLETE_ACK_BITS 1 31053 #define AN_X4_STATUS_PXNG_STATUS_COMPLETE_ACK_SHIFT 1 31054 31055 /* AN_X4_STATUS :: pxng_status :: consistency_mismatch [00:00] */ 31056 #define AN_X4_STATUS_PXNG_STATUS_CONSISTENCY_MISMATCH_MASK 0x0001 31057 #define AN_X4_STATUS_PXNG_STATUS_CONSISTENCY_MISMATCH_ALIGN 0 31058 #define AN_X4_STATUS_PXNG_STATUS_CONSISTENCY_MISMATCH_BITS 1 31059 #define AN_X4_STATUS_PXNG_STATUS_CONSISTENCY_MISMATCH_SHIFT 0 31060 31061 31062 /**************************************************************************** 31063 * AN_X4_STATUS :: pseq_status 31064 */ 31065 /* AN_X4_STATUS :: pseq_status :: reserved0 [15:11] */ 31066 #define AN_X4_STATUS_PSEQ_STATUS_RESERVED0_MASK 0xf800 31067 #define AN_X4_STATUS_PSEQ_STATUS_RESERVED0_ALIGN 0 31068 #define AN_X4_STATUS_PSEQ_STATUS_RESERVED0_BITS 5 31069 #define AN_X4_STATUS_PSEQ_STATUS_RESERVED0_SHIFT 11 31070 31071 /* AN_X4_STATUS :: pseq_status :: cl73_an_complete [10:10] */ 31072 #define AN_X4_STATUS_PSEQ_STATUS_CL73_AN_COMPLETE_MASK 0x0400 31073 #define AN_X4_STATUS_PSEQ_STATUS_CL73_AN_COMPLETE_ALIGN 0 31074 #define AN_X4_STATUS_PSEQ_STATUS_CL73_AN_COMPLETE_BITS 1 31075 #define AN_X4_STATUS_PSEQ_STATUS_CL73_AN_COMPLETE_SHIFT 10 31076 31077 /* AN_X4_STATUS :: pseq_status :: rx_np_toggle_err [09:09] */ 31078 #define AN_X4_STATUS_PSEQ_STATUS_RX_NP_TOGGLE_ERR_MASK 0x0200 31079 #define AN_X4_STATUS_PSEQ_STATUS_RX_NP_TOGGLE_ERR_ALIGN 0 31080 #define AN_X4_STATUS_PSEQ_STATUS_RX_NP_TOGGLE_ERR_BITS 1 31081 #define AN_X4_STATUS_PSEQ_STATUS_RX_NP_TOGGLE_ERR_SHIFT 9 31082 31083 /* AN_X4_STATUS :: pseq_status :: rx_invalid_seq [08:08] */ 31084 #define AN_X4_STATUS_PSEQ_STATUS_RX_INVALID_SEQ_MASK 0x0100 31085 #define AN_X4_STATUS_PSEQ_STATUS_RX_INVALID_SEQ_ALIGN 0 31086 #define AN_X4_STATUS_PSEQ_STATUS_RX_INVALID_SEQ_BITS 1 31087 #define AN_X4_STATUS_PSEQ_STATUS_RX_INVALID_SEQ_SHIFT 8 31088 31089 /* AN_X4_STATUS :: pseq_status :: rx_up_oui_match [07:07] */ 31090 #define AN_X4_STATUS_PSEQ_STATUS_RX_UP_OUI_MATCH_MASK 0x0080 31091 #define AN_X4_STATUS_PSEQ_STATUS_RX_UP_OUI_MATCH_ALIGN 0 31092 #define AN_X4_STATUS_PSEQ_STATUS_RX_UP_OUI_MATCH_BITS 1 31093 #define AN_X4_STATUS_PSEQ_STATUS_RX_UP_OUI_MATCH_SHIFT 7 31094 31095 /* AN_X4_STATUS :: pseq_status :: rx_up_oui_mismatch [06:06] */ 31096 #define AN_X4_STATUS_PSEQ_STATUS_RX_UP_OUI_MISMATCH_MASK 0x0040 31097 #define AN_X4_STATUS_PSEQ_STATUS_RX_UP_OUI_MISMATCH_ALIGN 0 31098 #define AN_X4_STATUS_PSEQ_STATUS_RX_UP_OUI_MISMATCH_BITS 1 31099 #define AN_X4_STATUS_PSEQ_STATUS_RX_UP_OUI_MISMATCH_SHIFT 6 31100 31101 /* AN_X4_STATUS :: pseq_status :: rx_mp_mismatch [05:05] */ 31102 #define AN_X4_STATUS_PSEQ_STATUS_RX_MP_MISMATCH_MASK 0x0020 31103 #define AN_X4_STATUS_PSEQ_STATUS_RX_MP_MISMATCH_ALIGN 0 31104 #define AN_X4_STATUS_PSEQ_STATUS_RX_MP_MISMATCH_BITS 1 31105 #define AN_X4_STATUS_PSEQ_STATUS_RX_MP_MISMATCH_SHIFT 5 31106 31107 /* AN_X4_STATUS :: pseq_status :: rx_mp_oui [04:04] */ 31108 #define AN_X4_STATUS_PSEQ_STATUS_RX_MP_OUI_MASK 0x0010 31109 #define AN_X4_STATUS_PSEQ_STATUS_RX_MP_OUI_ALIGN 0 31110 #define AN_X4_STATUS_PSEQ_STATUS_RX_MP_OUI_BITS 1 31111 #define AN_X4_STATUS_PSEQ_STATUS_RX_MP_OUI_SHIFT 4 31112 31113 /* AN_X4_STATUS :: pseq_status :: rx_mp_null [03:03] */ 31114 #define AN_X4_STATUS_PSEQ_STATUS_RX_MP_NULL_MASK 0x0008 31115 #define AN_X4_STATUS_PSEQ_STATUS_RX_MP_NULL_ALIGN 0 31116 #define AN_X4_STATUS_PSEQ_STATUS_RX_MP_NULL_BITS 1 31117 #define AN_X4_STATUS_PSEQ_STATUS_RX_MP_NULL_SHIFT 3 31118 31119 /* AN_X4_STATUS :: pseq_status :: rx_np [02:02] */ 31120 #define AN_X4_STATUS_PSEQ_STATUS_RX_NP_MASK 0x0004 31121 #define AN_X4_STATUS_PSEQ_STATUS_RX_NP_ALIGN 0 31122 #define AN_X4_STATUS_PSEQ_STATUS_RX_NP_BITS 1 31123 #define AN_X4_STATUS_PSEQ_STATUS_RX_NP_SHIFT 2 31124 31125 /* AN_X4_STATUS :: pseq_status :: rx_bp [01:01] */ 31126 #define AN_X4_STATUS_PSEQ_STATUS_RX_BP_MASK 0x0002 31127 #define AN_X4_STATUS_PSEQ_STATUS_RX_BP_ALIGN 0 31128 #define AN_X4_STATUS_PSEQ_STATUS_RX_BP_BITS 1 31129 #define AN_X4_STATUS_PSEQ_STATUS_RX_BP_SHIFT 1 31130 31131 /* AN_X4_STATUS :: pseq_status :: hp_mode [00:00] */ 31132 #define AN_X4_STATUS_PSEQ_STATUS_HP_MODE_MASK 0x0001 31133 #define AN_X4_STATUS_PSEQ_STATUS_HP_MODE_ALIGN 0 31134 #define AN_X4_STATUS_PSEQ_STATUS_HP_MODE_BITS 1 31135 #define AN_X4_STATUS_PSEQ_STATUS_HP_MODE_SHIFT 0 31136 31137 31138 /**************************************************************************** 31139 * AN_X4_STATUS :: pseq_rf 31140 */ 31141 /* AN_X4_STATUS :: pseq_rf :: reserved0 [15:01] */ 31142 #define AN_X4_STATUS_PSEQ_RF_RESERVED0_MASK 0xfffe 31143 #define AN_X4_STATUS_PSEQ_RF_RESERVED0_ALIGN 0 31144 #define AN_X4_STATUS_PSEQ_RF_RESERVED0_BITS 15 31145 #define AN_X4_STATUS_PSEQ_RF_RESERVED0_SHIFT 1 31146 31147 /* AN_X4_STATUS :: pseq_rf :: remote_fault_set [00:00] */ 31148 #define AN_X4_STATUS_PSEQ_RF_REMOTE_FAULT_SET_MASK 0x0001 31149 #define AN_X4_STATUS_PSEQ_RF_REMOTE_FAULT_SET_ALIGN 0 31150 #define AN_X4_STATUS_PSEQ_RF_REMOTE_FAULT_SET_BITS 1 31151 #define AN_X4_STATUS_PSEQ_RF_REMOTE_FAULT_SET_SHIFT 0 31152 31153 31154 /**************************************************************************** 31155 * AN_X4_STATUS :: unexp_page 31156 */ 31157 /* AN_X4_STATUS :: unexp_page :: rx_unexpected_page [15:00] */ 31158 #define AN_X4_STATUS_UNEXP_PAGE_RX_UNEXPECTED_PAGE_MASK 0xffff 31159 #define AN_X4_STATUS_UNEXP_PAGE_RX_UNEXPECTED_PAGE_ALIGN 0 31160 #define AN_X4_STATUS_UNEXP_PAGE_RX_UNEXPECTED_PAGE_BITS 16 31161 #define AN_X4_STATUS_UNEXP_PAGE_RX_UNEXPECTED_PAGE_SHIFT 0 31162 31163 31164 /**************************************************************************** 31165 * AN_X4_STATUS :: lp_base1 31166 */ 31167 /* AN_X4_STATUS :: lp_base1 :: lp_base1 [15:00] */ 31168 #define AN_X4_STATUS_LP_BASE1_LP_BASE1_MASK 0xffff 31169 #define AN_X4_STATUS_LP_BASE1_LP_BASE1_ALIGN 0 31170 #define AN_X4_STATUS_LP_BASE1_LP_BASE1_BITS 16 31171 #define AN_X4_STATUS_LP_BASE1_LP_BASE1_SHIFT 0 31172 31173 31174 /**************************************************************************** 31175 * AN_X4_STATUS :: lp_base2 31176 */ 31177 /* AN_X4_STATUS :: lp_base2 :: lp_base2 [15:00] */ 31178 #define AN_X4_STATUS_LP_BASE2_LP_BASE2_MASK 0xffff 31179 #define AN_X4_STATUS_LP_BASE2_LP_BASE2_ALIGN 0 31180 #define AN_X4_STATUS_LP_BASE2_LP_BASE2_BITS 16 31181 #define AN_X4_STATUS_LP_BASE2_LP_BASE2_SHIFT 0 31182 31183 31184 /**************************************************************************** 31185 * AN_X4_STATUS :: lp_base3 31186 */ 31187 /* AN_X4_STATUS :: lp_base3 :: lp_base3 [15:00] */ 31188 #define AN_X4_STATUS_LP_BASE3_LP_BASE3_MASK 0xffff 31189 #define AN_X4_STATUS_LP_BASE3_LP_BASE3_ALIGN 0 31190 #define AN_X4_STATUS_LP_BASE3_LP_BASE3_BITS 16 31191 #define AN_X4_STATUS_LP_BASE3_LP_BASE3_SHIFT 0 31192 31193 31194 /**************************************************************************** 31195 * AN_X4_STATUS :: lp_oui_up1 31196 */ 31197 /* AN_X4_STATUS :: lp_oui_up1 :: lp_oui_up1 [15:00] */ 31198 #define AN_X4_STATUS_LP_OUI_UP1_LP_OUI_UP1_MASK 0xffff 31199 #define AN_X4_STATUS_LP_OUI_UP1_LP_OUI_UP1_ALIGN 0 31200 #define AN_X4_STATUS_LP_OUI_UP1_LP_OUI_UP1_BITS 16 31201 #define AN_X4_STATUS_LP_OUI_UP1_LP_OUI_UP1_SHIFT 0 31202 31203 31204 /**************************************************************************** 31205 * AN_X4_STATUS :: lp_oui_up2 31206 */ 31207 /* AN_X4_STATUS :: lp_oui_up2 :: lp_oui_up2 [15:00] */ 31208 #define AN_X4_STATUS_LP_OUI_UP2_LP_OUI_UP2_MASK 0xffff 31209 #define AN_X4_STATUS_LP_OUI_UP2_LP_OUI_UP2_ALIGN 0 31210 #define AN_X4_STATUS_LP_OUI_UP2_LP_OUI_UP2_BITS 16 31211 #define AN_X4_STATUS_LP_OUI_UP2_LP_OUI_UP2_SHIFT 0 31212 31213 31214 /**************************************************************************** 31215 * AN_X4_STATUS :: lp_oui_up3 31216 */ 31217 /* AN_X4_STATUS :: lp_oui_up3 :: lp_oui_up3 [15:00] */ 31218 #define AN_X4_STATUS_LP_OUI_UP3_LP_OUI_UP3_MASK 0xffff 31219 #define AN_X4_STATUS_LP_OUI_UP3_LP_OUI_UP3_ALIGN 0 31220 #define AN_X4_STATUS_LP_OUI_UP3_LP_OUI_UP3_BITS 16 31221 #define AN_X4_STATUS_LP_OUI_UP3_LP_OUI_UP3_SHIFT 0 31222 31223 31224 /**************************************************************************** 31225 * AN_X4_STATUS :: lp_oui_up4 31226 */ 31227 /* AN_X4_STATUS :: lp_oui_up4 :: lp_oui_up4 [15:00] */ 31228 #define AN_X4_STATUS_LP_OUI_UP4_LP_OUI_UP4_MASK 0xffff 31229 #define AN_X4_STATUS_LP_OUI_UP4_LP_OUI_UP4_ALIGN 0 31230 #define AN_X4_STATUS_LP_OUI_UP4_LP_OUI_UP4_BITS 16 31231 #define AN_X4_STATUS_LP_OUI_UP4_LP_OUI_UP4_SHIFT 0 31232 31233 31234 /**************************************************************************** 31235 * AN_X4_STATUS :: lp_oui_up5 31236 */ 31237 /* AN_X4_STATUS :: lp_oui_up5 :: reserved0 [15:13] */ 31238 #define AN_X4_STATUS_LP_OUI_UP5_RESERVED0_MASK 0xe000 31239 #define AN_X4_STATUS_LP_OUI_UP5_RESERVED0_ALIGN 0 31240 #define AN_X4_STATUS_LP_OUI_UP5_RESERVED0_BITS 3 31241 #define AN_X4_STATUS_LP_OUI_UP5_RESERVED0_SHIFT 13 31242 31243 /* AN_X4_STATUS :: lp_oui_up5 :: lp_oui_up5 [12:00] */ 31244 #define AN_X4_STATUS_LP_OUI_UP5_LP_OUI_UP5_MASK 0x1fff 31245 #define AN_X4_STATUS_LP_OUI_UP5_LP_OUI_UP5_ALIGN 0 31246 #define AN_X4_STATUS_LP_OUI_UP5_LP_OUI_UP5_BITS 13 31247 #define AN_X4_STATUS_LP_OUI_UP5_LP_OUI_UP5_SHIFT 0 31248 31249 31250 /**************************************************************************** 31251 * AN_X4_STATUS :: res_err 31252 */ 31253 /* AN_X4_STATUS :: res_err :: reserved0 [15:01] */ 31254 #define AN_X4_STATUS_RES_ERR_RESERVED0_MASK 0xfffe 31255 #define AN_X4_STATUS_RES_ERR_RESERVED0_ALIGN 0 31256 #define AN_X4_STATUS_RES_ERR_RESERVED0_BITS 15 31257 #define AN_X4_STATUS_RES_ERR_RESERVED0_SHIFT 1 31258 31259 /* AN_X4_STATUS :: res_err :: resolution_error [00:00] */ 31260 #define AN_X4_STATUS_RES_ERR_RESOLUTION_ERROR_MASK 0x0001 31261 #define AN_X4_STATUS_RES_ERR_RESOLUTION_ERROR_ALIGN 0 31262 #define AN_X4_STATUS_RES_ERR_RESOLUTION_ERROR_BITS 1 31263 #define AN_X4_STATUS_RES_ERR_RESOLUTION_ERROR_SHIFT 0 31264 31265 31266 /**************************************************************************** 31267 * TSC_WC4_TSC_USER4_AN_X4_SW_MGMT 31268 */ 31269 /**************************************************************************** 31270 * AN_X4_SW_MGMT :: ld_page_2 31271 */ 31272 /* AN_X4_SW_MGMT :: ld_page_2 :: ld_page_2 [15:00] */ 31273 #define AN_X4_SW_MGMT_LD_PAGE_2_LD_PAGE_2_MASK 0xffff 31274 #define AN_X4_SW_MGMT_LD_PAGE_2_LD_PAGE_2_ALIGN 0 31275 #define AN_X4_SW_MGMT_LD_PAGE_2_LD_PAGE_2_BITS 16 31276 #define AN_X4_SW_MGMT_LD_PAGE_2_LD_PAGE_2_SHIFT 0 31277 31278 31279 /**************************************************************************** 31280 * AN_X4_SW_MGMT :: ld_page_1 31281 */ 31282 /* AN_X4_SW_MGMT :: ld_page_1 :: ld_page_1 [15:00] */ 31283 #define AN_X4_SW_MGMT_LD_PAGE_1_LD_PAGE_1_MASK 0xffff 31284 #define AN_X4_SW_MGMT_LD_PAGE_1_LD_PAGE_1_ALIGN 0 31285 #define AN_X4_SW_MGMT_LD_PAGE_1_LD_PAGE_1_BITS 16 31286 #define AN_X4_SW_MGMT_LD_PAGE_1_LD_PAGE_1_SHIFT 0 31287 31288 31289 /**************************************************************************** 31290 * AN_X4_SW_MGMT :: ld_page_0 31291 */ 31292 /* AN_X4_SW_MGMT :: ld_page_0 :: ld_page_0 [15:00] */ 31293 #define AN_X4_SW_MGMT_LD_PAGE_0_LD_PAGE_0_MASK 0xffff 31294 #define AN_X4_SW_MGMT_LD_PAGE_0_LD_PAGE_0_ALIGN 0 31295 #define AN_X4_SW_MGMT_LD_PAGE_0_LD_PAGE_0_BITS 16 31296 #define AN_X4_SW_MGMT_LD_PAGE_0_LD_PAGE_0_SHIFT 0 31297 31298 31299 /**************************************************************************** 31300 * AN_X4_SW_MGMT :: lp_page_2 31301 */ 31302 /* AN_X4_SW_MGMT :: lp_page_2 :: lp_page_2 [15:00] */ 31303 #define AN_X4_SW_MGMT_LP_PAGE_2_LP_PAGE_2_MASK 0xffff 31304 #define AN_X4_SW_MGMT_LP_PAGE_2_LP_PAGE_2_ALIGN 0 31305 #define AN_X4_SW_MGMT_LP_PAGE_2_LP_PAGE_2_BITS 16 31306 #define AN_X4_SW_MGMT_LP_PAGE_2_LP_PAGE_2_SHIFT 0 31307 31308 31309 /**************************************************************************** 31310 * AN_X4_SW_MGMT :: lp_page_1 31311 */ 31312 /* AN_X4_SW_MGMT :: lp_page_1 :: lp_page_1 [15:00] */ 31313 #define AN_X4_SW_MGMT_LP_PAGE_1_LP_PAGE_1_MASK 0xffff 31314 #define AN_X4_SW_MGMT_LP_PAGE_1_LP_PAGE_1_ALIGN 0 31315 #define AN_X4_SW_MGMT_LP_PAGE_1_LP_PAGE_1_BITS 16 31316 #define AN_X4_SW_MGMT_LP_PAGE_1_LP_PAGE_1_SHIFT 0 31317 31318 31319 /**************************************************************************** 31320 * AN_X4_SW_MGMT :: lp_page_0 31321 */ 31322 /* AN_X4_SW_MGMT :: lp_page_0 :: lp_page_0 [15:00] */ 31323 #define AN_X4_SW_MGMT_LP_PAGE_0_LP_PAGE_0_MASK 0xffff 31324 #define AN_X4_SW_MGMT_LP_PAGE_0_LP_PAGE_0_ALIGN 0 31325 #define AN_X4_SW_MGMT_LP_PAGE_0_LP_PAGE_0_BITS 16 31326 #define AN_X4_SW_MGMT_LP_PAGE_0_LP_PAGE_0_SHIFT 0 31327 31328 31329 /**************************************************************************** 31330 * AN_X4_SW_MGMT :: sw_control_status 31331 */ 31332 /* AN_X4_SW_MGMT :: sw_control_status :: an_completed [15:15] */ 31333 #define AN_X4_SW_MGMT_SW_CONTROL_STATUS_AN_COMPLETED_MASK 0x8000 31334 #define AN_X4_SW_MGMT_SW_CONTROL_STATUS_AN_COMPLETED_ALIGN 0 31335 #define AN_X4_SW_MGMT_SW_CONTROL_STATUS_AN_COMPLETED_BITS 1 31336 #define AN_X4_SW_MGMT_SW_CONTROL_STATUS_AN_COMPLETED_SHIFT 15 31337 31338 /* AN_X4_SW_MGMT :: sw_control_status :: ld_control_valid [14:14] */ 31339 #define AN_X4_SW_MGMT_SW_CONTROL_STATUS_LD_CONTROL_VALID_MASK 0x4000 31340 #define AN_X4_SW_MGMT_SW_CONTROL_STATUS_LD_CONTROL_VALID_ALIGN 0 31341 #define AN_X4_SW_MGMT_SW_CONTROL_STATUS_LD_CONTROL_VALID_BITS 1 31342 #define AN_X4_SW_MGMT_SW_CONTROL_STATUS_LD_CONTROL_VALID_SHIFT 14 31343 31344 /* AN_X4_SW_MGMT :: sw_control_status :: ld_page_req [13:13] */ 31345 #define AN_X4_SW_MGMT_SW_CONTROL_STATUS_LD_PAGE_REQ_MASK 0x2000 31346 #define AN_X4_SW_MGMT_SW_CONTROL_STATUS_LD_PAGE_REQ_ALIGN 0 31347 #define AN_X4_SW_MGMT_SW_CONTROL_STATUS_LD_PAGE_REQ_BITS 1 31348 #define AN_X4_SW_MGMT_SW_CONTROL_STATUS_LD_PAGE_REQ_SHIFT 13 31349 31350 /* AN_X4_SW_MGMT :: sw_control_status :: lp_page_rdy [12:12] */ 31351 #define AN_X4_SW_MGMT_SW_CONTROL_STATUS_LP_PAGE_RDY_MASK 0x1000 31352 #define AN_X4_SW_MGMT_SW_CONTROL_STATUS_LP_PAGE_RDY_ALIGN 0 31353 #define AN_X4_SW_MGMT_SW_CONTROL_STATUS_LP_PAGE_RDY_BITS 1 31354 #define AN_X4_SW_MGMT_SW_CONTROL_STATUS_LP_PAGE_RDY_SHIFT 12 31355 31356 /* AN_X4_SW_MGMT :: sw_control_status :: ld_seq_restart [11:11] */ 31357 #define AN_X4_SW_MGMT_SW_CONTROL_STATUS_LD_SEQ_RESTART_MASK 0x0800 31358 #define AN_X4_SW_MGMT_SW_CONTROL_STATUS_LD_SEQ_RESTART_ALIGN 0 31359 #define AN_X4_SW_MGMT_SW_CONTROL_STATUS_LD_SEQ_RESTART_BITS 1 31360 #define AN_X4_SW_MGMT_SW_CONTROL_STATUS_LD_SEQ_RESTART_SHIFT 11 31361 31362 /* AN_X4_SW_MGMT :: sw_control_status :: reserved0 [10:09] */ 31363 #define AN_X4_SW_MGMT_SW_CONTROL_STATUS_RESERVED0_MASK 0x0600 31364 #define AN_X4_SW_MGMT_SW_CONTROL_STATUS_RESERVED0_ALIGN 0 31365 #define AN_X4_SW_MGMT_SW_CONTROL_STATUS_RESERVED0_BITS 2 31366 #define AN_X4_SW_MGMT_SW_CONTROL_STATUS_RESERVED0_SHIFT 9 31367 31368 /* AN_X4_SW_MGMT :: sw_control_status :: pd_cl37_completed [08:08] */ 31369 #define AN_X4_SW_MGMT_SW_CONTROL_STATUS_PD_CL37_COMPLETED_MASK 0x0100 31370 #define AN_X4_SW_MGMT_SW_CONTROL_STATUS_PD_CL37_COMPLETED_ALIGN 0 31371 #define AN_X4_SW_MGMT_SW_CONTROL_STATUS_PD_CL37_COMPLETED_BITS 1 31372 #define AN_X4_SW_MGMT_SW_CONTROL_STATUS_PD_CL37_COMPLETED_SHIFT 8 31373 31374 /* AN_X4_SW_MGMT :: sw_control_status :: tla_ln_sequencer_fsm_status1 [07:00] */ 31375 #define AN_X4_SW_MGMT_SW_CONTROL_STATUS_TLA_LN_SEQUENCER_FSM_STATUS1_MASK 0x00ff 31376 #define AN_X4_SW_MGMT_SW_CONTROL_STATUS_TLA_LN_SEQUENCER_FSM_STATUS1_ALIGN 0 31377 #define AN_X4_SW_MGMT_SW_CONTROL_STATUS_TLA_LN_SEQUENCER_FSM_STATUS1_BITS 8 31378 #define AN_X4_SW_MGMT_SW_CONTROL_STATUS_TLA_LN_SEQUENCER_FSM_STATUS1_SHIFT 0 31379 31380 31381 /**************************************************************************** 31382 * AN_X4_SW_MGMT :: ld_control 31383 */ 31384 /* AN_X4_SW_MGMT :: ld_control :: reserved0 [15:02] */ 31385 #define AN_X4_SW_MGMT_LD_CONTROL_RESERVED0_MASK 0xfffc 31386 #define AN_X4_SW_MGMT_LD_CONTROL_RESERVED0_ALIGN 0 31387 #define AN_X4_SW_MGMT_LD_CONTROL_RESERVED0_BITS 14 31388 #define AN_X4_SW_MGMT_LD_CONTROL_RESERVED0_SHIFT 2 31389 31390 /* AN_X4_SW_MGMT :: ld_control :: an_type_sw [01:01] */ 31391 #define AN_X4_SW_MGMT_LD_CONTROL_AN_TYPE_SW_MASK 0x0002 31392 #define AN_X4_SW_MGMT_LD_CONTROL_AN_TYPE_SW_ALIGN 0 31393 #define AN_X4_SW_MGMT_LD_CONTROL_AN_TYPE_SW_BITS 1 31394 #define AN_X4_SW_MGMT_LD_CONTROL_AN_TYPE_SW_SHIFT 1 31395 31396 /* AN_X4_SW_MGMT :: ld_control :: an_hcd_res_disable [00:00] */ 31397 #define AN_X4_SW_MGMT_LD_CONTROL_AN_HCD_RES_DISABLE_MASK 0x0001 31398 #define AN_X4_SW_MGMT_LD_CONTROL_AN_HCD_RES_DISABLE_ALIGN 0 31399 #define AN_X4_SW_MGMT_LD_CONTROL_AN_HCD_RES_DISABLE_BITS 1 31400 #define AN_X4_SW_MGMT_LD_CONTROL_AN_HCD_RES_DISABLE_SHIFT 0 31401 31402 31403 /**************************************************************************** 31404 * AN_X4_SW_MGMT :: an_ability_resolution_status 31405 */ 31406 /* AN_X4_SW_MGMT :: an_ability_resolution_status :: hcd_dbg_cl74_base_en [15:15] */ 31407 #define AN_X4_SW_MGMT_AN_ABILITY_RESOLUTION_STATUS_HCD_DBG_CL74_BASE_EN_MASK 0x8000 31408 #define AN_X4_SW_MGMT_AN_ABILITY_RESOLUTION_STATUS_HCD_DBG_CL74_BASE_EN_ALIGN 0 31409 #define AN_X4_SW_MGMT_AN_ABILITY_RESOLUTION_STATUS_HCD_DBG_CL74_BASE_EN_BITS 1 31410 #define AN_X4_SW_MGMT_AN_ABILITY_RESOLUTION_STATUS_HCD_DBG_CL74_BASE_EN_SHIFT 15 31411 31412 /* AN_X4_SW_MGMT :: an_ability_resolution_status :: hcd_dbg_cl74_up_en [14:14] */ 31413 #define AN_X4_SW_MGMT_AN_ABILITY_RESOLUTION_STATUS_HCD_DBG_CL74_UP_EN_MASK 0x4000 31414 #define AN_X4_SW_MGMT_AN_ABILITY_RESOLUTION_STATUS_HCD_DBG_CL74_UP_EN_ALIGN 0 31415 #define AN_X4_SW_MGMT_AN_ABILITY_RESOLUTION_STATUS_HCD_DBG_CL74_UP_EN_BITS 1 31416 #define AN_X4_SW_MGMT_AN_ABILITY_RESOLUTION_STATUS_HCD_DBG_CL74_UP_EN_SHIFT 14 31417 31418 /* AN_X4_SW_MGMT :: an_ability_resolution_status :: hcd_cl91_en [13:13] */ 31419 #define AN_X4_SW_MGMT_AN_ABILITY_RESOLUTION_STATUS_HCD_CL91_EN_MASK 0x2000 31420 #define AN_X4_SW_MGMT_AN_ABILITY_RESOLUTION_STATUS_HCD_CL91_EN_ALIGN 0 31421 #define AN_X4_SW_MGMT_AN_ABILITY_RESOLUTION_STATUS_HCD_CL91_EN_BITS 1 31422 #define AN_X4_SW_MGMT_AN_ABILITY_RESOLUTION_STATUS_HCD_CL91_EN_SHIFT 13 31423 31424 /* AN_X4_SW_MGMT :: an_ability_resolution_status :: an_hcd_duplex [12:12] */ 31425 #define AN_X4_SW_MGMT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_DUPLEX_MASK 0x1000 31426 #define AN_X4_SW_MGMT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_DUPLEX_ALIGN 0 31427 #define AN_X4_SW_MGMT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_DUPLEX_BITS 1 31428 #define AN_X4_SW_MGMT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_DUPLEX_SHIFT 12 31429 31430 /* AN_X4_SW_MGMT :: an_ability_resolution_status :: an_hcd_pause [11:10] */ 31431 #define AN_X4_SW_MGMT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_PAUSE_MASK 0x0c00 31432 #define AN_X4_SW_MGMT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_PAUSE_ALIGN 0 31433 #define AN_X4_SW_MGMT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_PAUSE_BITS 2 31434 #define AN_X4_SW_MGMT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_PAUSE_SHIFT 10 31435 31436 /* AN_X4_SW_MGMT :: an_ability_resolution_status :: an_hcd_speed [09:02] */ 31437 #define AN_X4_SW_MGMT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_MASK 0x03fc 31438 #define AN_X4_SW_MGMT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_ALIGN 0 31439 #define AN_X4_SW_MGMT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_BITS 8 31440 #define AN_X4_SW_MGMT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_SHIFT 2 31441 31442 /* AN_X4_SW_MGMT :: an_ability_resolution_status :: an_hcd_fec [01:01] */ 31443 #define AN_X4_SW_MGMT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_FEC_MASK 0x0002 31444 #define AN_X4_SW_MGMT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_FEC_ALIGN 0 31445 #define AN_X4_SW_MGMT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_FEC_BITS 1 31446 #define AN_X4_SW_MGMT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_FEC_SHIFT 1 31447 31448 /* AN_X4_SW_MGMT :: an_ability_resolution_status :: an_hcd_cl72 [00:00] */ 31449 #define AN_X4_SW_MGMT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_CL72_MASK 0x0001 31450 #define AN_X4_SW_MGMT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_CL72_ALIGN 0 31451 #define AN_X4_SW_MGMT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_CL72_BITS 1 31452 #define AN_X4_SW_MGMT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_CL72_SHIFT 0 31453 31454 31455 /**************************************************************************** 31456 * AN_X4_SW_MGMT :: an_misc_status 31457 */ 31458 /* AN_X4_SW_MGMT :: an_misc_status :: an_complete [15:15] */ 31459 #define AN_X4_SW_MGMT_AN_MISC_STATUS_AN_COMPLETE_MASK 0x8000 31460 #define AN_X4_SW_MGMT_AN_MISC_STATUS_AN_COMPLETE_ALIGN 0 31461 #define AN_X4_SW_MGMT_AN_MISC_STATUS_AN_COMPLETE_BITS 1 31462 #define AN_X4_SW_MGMT_AN_MISC_STATUS_AN_COMPLETE_SHIFT 15 31463 31464 /* AN_X4_SW_MGMT :: an_misc_status :: an_retry_count [14:09] */ 31465 #define AN_X4_SW_MGMT_AN_MISC_STATUS_AN_RETRY_COUNT_MASK 0x7e00 31466 #define AN_X4_SW_MGMT_AN_MISC_STATUS_AN_RETRY_COUNT_ALIGN 0 31467 #define AN_X4_SW_MGMT_AN_MISC_STATUS_AN_RETRY_COUNT_BITS 6 31468 #define AN_X4_SW_MGMT_AN_MISC_STATUS_AN_RETRY_COUNT_SHIFT 9 31469 31470 /* AN_X4_SW_MGMT :: an_misc_status :: speed_force [08:08] */ 31471 #define AN_X4_SW_MGMT_AN_MISC_STATUS_SPEED_FORCE_MASK 0x0100 31472 #define AN_X4_SW_MGMT_AN_MISC_STATUS_SPEED_FORCE_ALIGN 0 31473 #define AN_X4_SW_MGMT_AN_MISC_STATUS_SPEED_FORCE_BITS 1 31474 #define AN_X4_SW_MGMT_AN_MISC_STATUS_SPEED_FORCE_SHIFT 8 31475 31476 /* AN_X4_SW_MGMT :: an_misc_status :: pd_completed [07:07] */ 31477 #define AN_X4_SW_MGMT_AN_MISC_STATUS_PD_COMPLETED_MASK 0x0080 31478 #define AN_X4_SW_MGMT_AN_MISC_STATUS_PD_COMPLETED_ALIGN 0 31479 #define AN_X4_SW_MGMT_AN_MISC_STATUS_PD_COMPLETED_BITS 1 31480 #define AN_X4_SW_MGMT_AN_MISC_STATUS_PD_COMPLETED_SHIFT 7 31481 31482 /* AN_X4_SW_MGMT :: an_misc_status :: an_active [06:06] */ 31483 #define AN_X4_SW_MGMT_AN_MISC_STATUS_AN_ACTIVE_MASK 0x0040 31484 #define AN_X4_SW_MGMT_AN_MISC_STATUS_AN_ACTIVE_ALIGN 0 31485 #define AN_X4_SW_MGMT_AN_MISC_STATUS_AN_ACTIVE_BITS 1 31486 #define AN_X4_SW_MGMT_AN_MISC_STATUS_AN_ACTIVE_SHIFT 6 31487 31488 /* AN_X4_SW_MGMT :: an_misc_status :: an_fail_count [05:02] */ 31489 #define AN_X4_SW_MGMT_AN_MISC_STATUS_AN_FAIL_COUNT_MASK 0x003c 31490 #define AN_X4_SW_MGMT_AN_MISC_STATUS_AN_FAIL_COUNT_ALIGN 0 31491 #define AN_X4_SW_MGMT_AN_MISC_STATUS_AN_FAIL_COUNT_BITS 4 31492 #define AN_X4_SW_MGMT_AN_MISC_STATUS_AN_FAIL_COUNT_SHIFT 2 31493 31494 /* AN_X4_SW_MGMT :: an_misc_status :: pd_in_progress [01:01] */ 31495 #define AN_X4_SW_MGMT_AN_MISC_STATUS_PD_IN_PROGRESS_MASK 0x0002 31496 #define AN_X4_SW_MGMT_AN_MISC_STATUS_PD_IN_PROGRESS_ALIGN 0 31497 #define AN_X4_SW_MGMT_AN_MISC_STATUS_PD_IN_PROGRESS_BITS 1 31498 #define AN_X4_SW_MGMT_AN_MISC_STATUS_PD_IN_PROGRESS_SHIFT 1 31499 31500 /* AN_X4_SW_MGMT :: an_misc_status :: reserved0 [00:00] */ 31501 #define AN_X4_SW_MGMT_AN_MISC_STATUS_RESERVED0_MASK 0x0001 31502 #define AN_X4_SW_MGMT_AN_MISC_STATUS_RESERVED0_ALIGN 0 31503 #define AN_X4_SW_MGMT_AN_MISC_STATUS_RESERVED0_BITS 1 31504 #define AN_X4_SW_MGMT_AN_MISC_STATUS_RESERVED0_SHIFT 0 31505 31506 31507 /**************************************************************************** 31508 * AN_X4_SW_MGMT :: tla_sequencer_status 31509 */ 31510 /* AN_X4_SW_MGMT :: tla_sequencer_status :: tla_seq_fsm_status [15:00] */ 31511 #define AN_X4_SW_MGMT_TLA_SEQUENCER_STATUS_TLA_SEQ_FSM_STATUS_MASK 0xffff 31512 #define AN_X4_SW_MGMT_TLA_SEQUENCER_STATUS_TLA_SEQ_FSM_STATUS_ALIGN 0 31513 #define AN_X4_SW_MGMT_TLA_SEQUENCER_STATUS_TLA_SEQ_FSM_STATUS_BITS 16 31514 #define AN_X4_SW_MGMT_TLA_SEQUENCER_STATUS_TLA_SEQ_FSM_STATUS_SHIFT 0 31515 #define AN_X4_SW_MGMT_TLA_SEQUENCER_STATUS_TLA_SEQ_FSM_STATUS_INIT 1 31516 #define AN_X4_SW_MGMT_TLA_SEQUENCER_STATUS_TLA_SEQ_FSM_STATUS_SET_AN_SPEED 2 31517 #define AN_X4_SW_MGMT_TLA_SEQUENCER_STATUS_TLA_SEQ_FSM_STATUS_WAIT_AN_SPEED 4 31518 #define AN_X4_SW_MGMT_TLA_SEQUENCER_STATUS_TLA_SEQ_FSM_STATUS_WAIT_AN_DONE 8 31519 #define AN_X4_SW_MGMT_TLA_SEQUENCER_STATUS_TLA_SEQ_FSM_STATUS_SET_RS_SPEED 16 31520 #define AN_X4_SW_MGMT_TLA_SEQUENCER_STATUS_TLA_SEQ_FSM_STATUS_WAIT_RS_CL72EN 32 31521 #define AN_X4_SW_MGMT_TLA_SEQUENCER_STATUS_TLA_SEQ_FSM_STATUS_WAIT_RS_SPEED 64 31522 #define AN_X4_SW_MGMT_TLA_SEQUENCER_STATUS_TLA_SEQ_FSM_STATUS_AN_IGNORE_LINK 128 31523 #define AN_X4_SW_MGMT_TLA_SEQUENCER_STATUS_TLA_SEQ_FSM_STATUS_AN_GOOD_CHECK 256 31524 #define AN_X4_SW_MGMT_TLA_SEQUENCER_STATUS_TLA_SEQ_FSM_STATUS_AN_GOOD 512 31525 #define AN_X4_SW_MGMT_TLA_SEQUENCER_STATUS_TLA_SEQ_FSM_STATUS_AN_FAIL 1024 31526 #define AN_X4_SW_MGMT_TLA_SEQUENCER_STATUS_TLA_SEQ_FSM_STATUS_AN_DEAD 2048 31527 #define AN_X4_SW_MGMT_TLA_SEQUENCER_STATUS_TLA_SEQ_FSM_STATUS_WAIT_PD_SPEED 4096 31528 #define AN_X4_SW_MGMT_TLA_SEQUENCER_STATUS_TLA_SEQ_FSM_STATUS_PD_IGNORE_LINK 8192 31529 #define AN_X4_SW_MGMT_TLA_SEQUENCER_STATUS_TLA_SEQ_FSM_STATUS_PD_GOOD_CHECK 16384 31530 #define AN_X4_SW_MGMT_TLA_SEQUENCER_STATUS_TLA_SEQ_FSM_STATUS_SW_SPEED_CHANGE 32768 31531 31532 31533 /**************************************************************************** 31534 * AN_X4_SW_MGMT :: int 31535 */ 31536 /* AN_X4_SW_MGMT :: int :: reserved0 [15:04] */ 31537 #define AN_X4_SW_MGMT_INT_RESERVED0_MASK 0xfff0 31538 #define AN_X4_SW_MGMT_INT_RESERVED0_ALIGN 0 31539 #define AN_X4_SW_MGMT_INT_RESERVED0_BITS 12 31540 #define AN_X4_SW_MGMT_INT_RESERVED0_SHIFT 4 31541 31542 /* AN_X4_SW_MGMT :: int :: an_good_chk_int [03:03] */ 31543 #define AN_X4_SW_MGMT_INT_AN_GOOD_CHK_INT_MASK 0x0008 31544 #define AN_X4_SW_MGMT_INT_AN_GOOD_CHK_INT_ALIGN 0 31545 #define AN_X4_SW_MGMT_INT_AN_GOOD_CHK_INT_BITS 1 31546 #define AN_X4_SW_MGMT_INT_AN_GOOD_CHK_INT_SHIFT 3 31547 31548 /* AN_X4_SW_MGMT :: int :: an_completed_sw_int [02:02] */ 31549 #define AN_X4_SW_MGMT_INT_AN_COMPLETED_SW_INT_MASK 0x0004 31550 #define AN_X4_SW_MGMT_INT_AN_COMPLETED_SW_INT_ALIGN 0 31551 #define AN_X4_SW_MGMT_INT_AN_COMPLETED_SW_INT_BITS 1 31552 #define AN_X4_SW_MGMT_INT_AN_COMPLETED_SW_INT_SHIFT 2 31553 31554 /* AN_X4_SW_MGMT :: int :: ld_page_req_int [01:01] */ 31555 #define AN_X4_SW_MGMT_INT_LD_PAGE_REQ_INT_MASK 0x0002 31556 #define AN_X4_SW_MGMT_INT_LD_PAGE_REQ_INT_ALIGN 0 31557 #define AN_X4_SW_MGMT_INT_LD_PAGE_REQ_INT_BITS 1 31558 #define AN_X4_SW_MGMT_INT_LD_PAGE_REQ_INT_SHIFT 1 31559 31560 /* AN_X4_SW_MGMT :: int :: lp_page_rdy_int [00:00] */ 31561 #define AN_X4_SW_MGMT_INT_LP_PAGE_RDY_INT_MASK 0x0001 31562 #define AN_X4_SW_MGMT_INT_LP_PAGE_RDY_INT_ALIGN 0 31563 #define AN_X4_SW_MGMT_INT_LP_PAGE_RDY_INT_BITS 1 31564 #define AN_X4_SW_MGMT_INT_LP_PAGE_RDY_INT_SHIFT 0 31565 31566 31567 /**************************************************************************** 31568 * AN_X4_SW_MGMT :: int_en 31569 */ 31570 /* AN_X4_SW_MGMT :: int_en :: reserved0 [15:04] */ 31571 #define AN_X4_SW_MGMT_INT_EN_RESERVED0_MASK 0xfff0 31572 #define AN_X4_SW_MGMT_INT_EN_RESERVED0_ALIGN 0 31573 #define AN_X4_SW_MGMT_INT_EN_RESERVED0_BITS 12 31574 #define AN_X4_SW_MGMT_INT_EN_RESERVED0_SHIFT 4 31575 31576 /* AN_X4_SW_MGMT :: int_en :: an_good_chk_en [03:03] */ 31577 #define AN_X4_SW_MGMT_INT_EN_AN_GOOD_CHK_EN_MASK 0x0008 31578 #define AN_X4_SW_MGMT_INT_EN_AN_GOOD_CHK_EN_ALIGN 0 31579 #define AN_X4_SW_MGMT_INT_EN_AN_GOOD_CHK_EN_BITS 1 31580 #define AN_X4_SW_MGMT_INT_EN_AN_GOOD_CHK_EN_SHIFT 3 31581 31582 /* AN_X4_SW_MGMT :: int_en :: an_completed_sw_en [02:02] */ 31583 #define AN_X4_SW_MGMT_INT_EN_AN_COMPLETED_SW_EN_MASK 0x0004 31584 #define AN_X4_SW_MGMT_INT_EN_AN_COMPLETED_SW_EN_ALIGN 0 31585 #define AN_X4_SW_MGMT_INT_EN_AN_COMPLETED_SW_EN_BITS 1 31586 #define AN_X4_SW_MGMT_INT_EN_AN_COMPLETED_SW_EN_SHIFT 2 31587 31588 /* AN_X4_SW_MGMT :: int_en :: ld_page_req_en [01:01] */ 31589 #define AN_X4_SW_MGMT_INT_EN_LD_PAGE_REQ_EN_MASK 0x0002 31590 #define AN_X4_SW_MGMT_INT_EN_LD_PAGE_REQ_EN_ALIGN 0 31591 #define AN_X4_SW_MGMT_INT_EN_LD_PAGE_REQ_EN_BITS 1 31592 #define AN_X4_SW_MGMT_INT_EN_LD_PAGE_REQ_EN_SHIFT 1 31593 31594 /* AN_X4_SW_MGMT :: int_en :: lp_page_rdy_en [00:00] */ 31595 #define AN_X4_SW_MGMT_INT_EN_LP_PAGE_RDY_EN_MASK 0x0001 31596 #define AN_X4_SW_MGMT_INT_EN_LP_PAGE_RDY_EN_ALIGN 0 31597 #define AN_X4_SW_MGMT_INT_EN_LP_PAGE_RDY_EN_BITS 1 31598 #define AN_X4_SW_MGMT_INT_EN_LP_PAGE_RDY_EN_SHIFT 0 31599 31600 31601 /**************************************************************************** 31602 * AN_X4_SW_MGMT :: sw_an_resolve 31603 */ 31604 /* AN_X4_SW_MGMT :: sw_an_resolve :: reserved0 [15:09] */ 31605 #define AN_X4_SW_MGMT_SW_AN_RESOLVE_RESERVED0_MASK 0xfe00 31606 #define AN_X4_SW_MGMT_SW_AN_RESOLVE_RESERVED0_ALIGN 0 31607 #define AN_X4_SW_MGMT_SW_AN_RESOLVE_RESERVED0_BITS 7 31608 #define AN_X4_SW_MGMT_SW_AN_RESOLVE_RESERVED0_SHIFT 9 31609 31610 /* AN_X4_SW_MGMT :: sw_an_resolve :: enable_hw_speed_change [08:08] */ 31611 #define AN_X4_SW_MGMT_SW_AN_RESOLVE_ENABLE_HW_SPEED_CHANGE_MASK 0x0100 31612 #define AN_X4_SW_MGMT_SW_AN_RESOLVE_ENABLE_HW_SPEED_CHANGE_ALIGN 0 31613 #define AN_X4_SW_MGMT_SW_AN_RESOLVE_ENABLE_HW_SPEED_CHANGE_BITS 1 31614 #define AN_X4_SW_MGMT_SW_AN_RESOLVE_ENABLE_HW_SPEED_CHANGE_SHIFT 8 31615 31616 /* AN_X4_SW_MGMT :: sw_an_resolve :: sw_an_resolved_speed [07:00] */ 31617 #define AN_X4_SW_MGMT_SW_AN_RESOLVE_SW_AN_RESOLVED_SPEED_MASK 0x00ff 31618 #define AN_X4_SW_MGMT_SW_AN_RESOLVE_SW_AN_RESOLVED_SPEED_ALIGN 0 31619 #define AN_X4_SW_MGMT_SW_AN_RESOLVE_SW_AN_RESOLVED_SPEED_BITS 8 31620 #define AN_X4_SW_MGMT_SW_AN_RESOLVE_SW_AN_RESOLVED_SPEED_SHIFT 0 31621 31622 31623 /**************************************************************************** 31624 * AN_X4_SW_MGMT :: wait_ack_complete 31625 */ 31626 /* AN_X4_SW_MGMT :: wait_ack_complete :: reserved0 [15:02] */ 31627 #define AN_X4_SW_MGMT_WAIT_ACK_COMPLETE_RESERVED0_MASK 0xfffc 31628 #define AN_X4_SW_MGMT_WAIT_ACK_COMPLETE_RESERVED0_ALIGN 0 31629 #define AN_X4_SW_MGMT_WAIT_ACK_COMPLETE_RESERVED0_BITS 14 31630 #define AN_X4_SW_MGMT_WAIT_ACK_COMPLETE_RESERVED0_SHIFT 2 31631 31632 /* AN_X4_SW_MGMT :: wait_ack_complete :: send_ack [01:01] */ 31633 #define AN_X4_SW_MGMT_WAIT_ACK_COMPLETE_SEND_ACK_MASK 0x0002 31634 #define AN_X4_SW_MGMT_WAIT_ACK_COMPLETE_SEND_ACK_ALIGN 0 31635 #define AN_X4_SW_MGMT_WAIT_ACK_COMPLETE_SEND_ACK_BITS 1 31636 #define AN_X4_SW_MGMT_WAIT_ACK_COMPLETE_SEND_ACK_SHIFT 1 31637 31638 /* AN_X4_SW_MGMT :: wait_ack_complete :: wait_for_ack_en [00:00] */ 31639 #define AN_X4_SW_MGMT_WAIT_ACK_COMPLETE_WAIT_FOR_ACK_EN_MASK 0x0001 31640 #define AN_X4_SW_MGMT_WAIT_ACK_COMPLETE_WAIT_FOR_ACK_EN_ALIGN 0 31641 #define AN_X4_SW_MGMT_WAIT_ACK_COMPLETE_WAIT_FOR_ACK_EN_BITS 1 31642 #define AN_X4_SW_MGMT_WAIT_ACK_COMPLETE_WAIT_FOR_ACK_EN_SHIFT 0 31643 31644 31645 /**************************************************************************** 31646 * TSC_WC4_TSC_USER4_ilkn_x4_control0 31647 */ 31648 /**************************************************************************** 31649 * ilkn_x4_control0 :: ilkn_control0 31650 */ 31651 /* ilkn_x4_control0 :: ilkn_control0 :: credit_en [15:15] */ 31652 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_CREDIT_EN_MASK 0x8000 31653 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_CREDIT_EN_ALIGN 0 31654 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_CREDIT_EN_BITS 1 31655 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_CREDIT_EN_SHIFT 15 31656 31657 /* ilkn_x4_control0 :: ilkn_control0 :: reserved0 [14:10] */ 31658 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_RESERVED0_MASK 0x7c00 31659 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_RESERVED0_ALIGN 0 31660 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_RESERVED0_BITS 5 31661 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_RESERVED0_SHIFT 10 31662 31663 /* ilkn_x4_control0 :: ilkn_control0 :: soft_rst_rx [09:09] */ 31664 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_SOFT_RST_RX_MASK 0x0200 31665 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_SOFT_RST_RX_ALIGN 0 31666 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_SOFT_RST_RX_BITS 1 31667 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_SOFT_RST_RX_SHIFT 9 31668 31669 /* ilkn_x4_control0 :: ilkn_control0 :: soft_rst_tx [08:08] */ 31670 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_SOFT_RST_TX_MASK 0x0100 31671 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_SOFT_RST_TX_ALIGN 0 31672 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_SOFT_RST_TX_BITS 1 31673 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_SOFT_RST_TX_SHIFT 8 31674 31675 /* ilkn_x4_control0 :: ilkn_control0 :: inv_rx_order [07:07] */ 31676 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_INV_RX_ORDER_MASK 0x0080 31677 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_INV_RX_ORDER_ALIGN 0 31678 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_INV_RX_ORDER_BITS 1 31679 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_INV_RX_ORDER_SHIFT 7 31680 31681 /* ilkn_x4_control0 :: ilkn_control0 :: inv_tx_order [06:06] */ 31682 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_INV_TX_ORDER_MASK 0x0040 31683 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_INV_TX_ORDER_ALIGN 0 31684 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_INV_TX_ORDER_BITS 1 31685 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_INV_TX_ORDER_SHIFT 6 31686 31687 /* ilkn_x4_control0 :: ilkn_control0 :: reserved1 [05:05] */ 31688 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_RESERVED1_MASK 0x0020 31689 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_RESERVED1_ALIGN 0 31690 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_RESERVED1_BITS 1 31691 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_RESERVED1_SHIFT 5 31692 31693 /* ilkn_x4_control0 :: ilkn_control0 :: ilkn_sel [04:04] */ 31694 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_ILKN_SEL_MASK 0x0010 31695 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_ILKN_SEL_ALIGN 0 31696 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_ILKN_SEL_BITS 1 31697 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_ILKN_SEL_SHIFT 4 31698 31699 /* ilkn_x4_control0 :: ilkn_control0 :: wm [03:00] */ 31700 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_WM_MASK 0x000f 31701 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_WM_ALIGN 0 31702 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_WM_BITS 4 31703 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_WM_SHIFT 0 31704 31705 31706 /**************************************************************************** 31707 * TSC_WC4_TSC_USER4_ilkn_x4_status0 31708 */ 31709 /**************************************************************************** 31710 * ilkn_x4_status0 :: ilkn_status0 31711 */ 31712 /* ilkn_x4_status0 :: ilkn_status0 :: reserved0 [15:08] */ 31713 #define ILKN_X4_STATUS0_ILKN_STATUS0_RESERVED0_MASK 0xff00 31714 #define ILKN_X4_STATUS0_ILKN_STATUS0_RESERVED0_ALIGN 0 31715 #define ILKN_X4_STATUS0_ILKN_STATUS0_RESERVED0_BITS 8 31716 #define ILKN_X4_STATUS0_ILKN_STATUS0_RESERVED0_SHIFT 8 31717 31718 /* ilkn_x4_status0 :: ilkn_status0 :: txfifo_underrun [07:07] */ 31719 #define ILKN_X4_STATUS0_ILKN_STATUS0_TXFIFO_UNDERRUN_MASK 0x0080 31720 #define ILKN_X4_STATUS0_ILKN_STATUS0_TXFIFO_UNDERRUN_ALIGN 0 31721 #define ILKN_X4_STATUS0_ILKN_STATUS0_TXFIFO_UNDERRUN_BITS 1 31722 #define ILKN_X4_STATUS0_ILKN_STATUS0_TXFIFO_UNDERRUN_SHIFT 7 31723 31724 /* ilkn_x4_status0 :: ilkn_status0 :: txfifo_overrun [06:06] */ 31725 #define ILKN_X4_STATUS0_ILKN_STATUS0_TXFIFO_OVERRUN_MASK 0x0040 31726 #define ILKN_X4_STATUS0_ILKN_STATUS0_TXFIFO_OVERRUN_ALIGN 0 31727 #define ILKN_X4_STATUS0_ILKN_STATUS0_TXFIFO_OVERRUN_BITS 1 31728 #define ILKN_X4_STATUS0_ILKN_STATUS0_TXFIFO_OVERRUN_SHIFT 6 31729 31730 /* ilkn_x4_status0 :: ilkn_status0 :: txfifo_full [05:05] */ 31731 #define ILKN_X4_STATUS0_ILKN_STATUS0_TXFIFO_FULL_MASK 0x0020 31732 #define ILKN_X4_STATUS0_ILKN_STATUS0_TXFIFO_FULL_ALIGN 0 31733 #define ILKN_X4_STATUS0_ILKN_STATUS0_TXFIFO_FULL_BITS 1 31734 #define ILKN_X4_STATUS0_ILKN_STATUS0_TXFIFO_FULL_SHIFT 5 31735 31736 /* ilkn_x4_status0 :: ilkn_status0 :: txfifo_empty [04:04] */ 31737 #define ILKN_X4_STATUS0_ILKN_STATUS0_TXFIFO_EMPTY_MASK 0x0010 31738 #define ILKN_X4_STATUS0_ILKN_STATUS0_TXFIFO_EMPTY_ALIGN 0 31739 #define ILKN_X4_STATUS0_ILKN_STATUS0_TXFIFO_EMPTY_BITS 1 31740 #define ILKN_X4_STATUS0_ILKN_STATUS0_TXFIFO_EMPTY_SHIFT 4 31741 31742 /* ilkn_x4_status0 :: ilkn_status0 :: rxfifo_underrun [03:03] */ 31743 #define ILKN_X4_STATUS0_ILKN_STATUS0_RXFIFO_UNDERRUN_MASK 0x0008 31744 #define ILKN_X4_STATUS0_ILKN_STATUS0_RXFIFO_UNDERRUN_ALIGN 0 31745 #define ILKN_X4_STATUS0_ILKN_STATUS0_RXFIFO_UNDERRUN_BITS 1 31746 #define ILKN_X4_STATUS0_ILKN_STATUS0_RXFIFO_UNDERRUN_SHIFT 3 31747 31748 /* ilkn_x4_status0 :: ilkn_status0 :: rxfifo_overrun [02:02] */ 31749 #define ILKN_X4_STATUS0_ILKN_STATUS0_RXFIFO_OVERRUN_MASK 0x0004 31750 #define ILKN_X4_STATUS0_ILKN_STATUS0_RXFIFO_OVERRUN_ALIGN 0 31751 #define ILKN_X4_STATUS0_ILKN_STATUS0_RXFIFO_OVERRUN_BITS 1 31752 #define ILKN_X4_STATUS0_ILKN_STATUS0_RXFIFO_OVERRUN_SHIFT 2 31753 31754 /* ilkn_x4_status0 :: ilkn_status0 :: rxfifo_full [01:01] */ 31755 #define ILKN_X4_STATUS0_ILKN_STATUS0_RXFIFO_FULL_MASK 0x0002 31756 #define ILKN_X4_STATUS0_ILKN_STATUS0_RXFIFO_FULL_ALIGN 0 31757 #define ILKN_X4_STATUS0_ILKN_STATUS0_RXFIFO_FULL_BITS 1 31758 #define ILKN_X4_STATUS0_ILKN_STATUS0_RXFIFO_FULL_SHIFT 1 31759 31760 /* ilkn_x4_status0 :: ilkn_status0 :: rxfifo_empty [00:00] */ 31761 #define ILKN_X4_STATUS0_ILKN_STATUS0_RXFIFO_EMPTY_MASK 0x0001 31762 #define ILKN_X4_STATUS0_ILKN_STATUS0_RXFIFO_EMPTY_ALIGN 0 31763 #define ILKN_X4_STATUS0_ILKN_STATUS0_RXFIFO_EMPTY_BITS 1 31764 #define ILKN_X4_STATUS0_ILKN_STATUS0_RXFIFO_EMPTY_SHIFT 0 31765 31766 31767 /**************************************************************************** 31768 * TSC_WC4_TSC_USER4_RX_X4_CL91_Status0 31769 */ 31770 /**************************************************************************** 31771 * RX_X4_CL91_Status0 :: fec_algn_fsm_state 31772 */ 31773 /* RX_X4_CL91_Status0 :: fec_algn_fsm_state :: reserved0 [15:10] */ 31774 #define RX_X4_CL91_STATUS0_FEC_ALGN_FSM_STATE_RESERVED0_MASK 0xfc00 31775 #define RX_X4_CL91_STATUS0_FEC_ALGN_FSM_STATE_RESERVED0_ALIGN 0 31776 #define RX_X4_CL91_STATUS0_FEC_ALGN_FSM_STATE_RESERVED0_BITS 6 31777 #define RX_X4_CL91_STATUS0_FEC_ALGN_FSM_STATE_RESERVED0_SHIFT 10 31778 31779 /* RX_X4_CL91_Status0 :: fec_algn_fsm_state :: cl91_fec_algn_fsm_latched_state [09:03] */ 31780 #define RX_X4_CL91_STATUS0_FEC_ALGN_FSM_STATE_CL91_FEC_ALGN_FSM_LATCHED_STATE_MASK 0x03f8 31781 #define RX_X4_CL91_STATUS0_FEC_ALGN_FSM_STATE_CL91_FEC_ALGN_FSM_LATCHED_STATE_ALIGN 0 31782 #define RX_X4_CL91_STATUS0_FEC_ALGN_FSM_STATE_CL91_FEC_ALGN_FSM_LATCHED_STATE_BITS 7 31783 #define RX_X4_CL91_STATUS0_FEC_ALGN_FSM_STATE_CL91_FEC_ALGN_FSM_LATCHED_STATE_SHIFT 3 31784 #define RX_X4_CL91_STATUS0_FEC_ALGN_FSM_STATE_CL91_FEC_ALGN_FSM_LATCHED_STATE_LOSS_OF_ALIGNMENT 0 31785 #define RX_X4_CL91_STATUS0_FEC_ALGN_FSM_STATE_CL91_FEC_ALGN_FSM_LATCHED_STATE_DESKEW 1 31786 #define RX_X4_CL91_STATUS0_FEC_ALGN_FSM_STATE_CL91_FEC_ALGN_FSM_LATCHED_STATE_DESKEW_FAIL 2 31787 #define RX_X4_CL91_STATUS0_FEC_ALGN_FSM_STATE_CL91_FEC_ALGN_FSM_LATCHED_STATE_ALIGN_ACQUIRED 3 31788 #define RX_X4_CL91_STATUS0_FEC_ALGN_FSM_STATE_CL91_FEC_ALGN_FSM_LATCHED_STATE_CW_GOOD 4 31789 #define RX_X4_CL91_STATUS0_FEC_ALGN_FSM_STATE_CL91_FEC_ALGN_FSM_LATCHED_STATE_CW_BAD 5 31790 #define RX_X4_CL91_STATUS0_FEC_ALGN_FSM_STATE_CL91_FEC_ALGN_FSM_LATCHED_STATE_THREE_BAD 6 31791 31792 /* RX_X4_CL91_Status0 :: fec_algn_fsm_state :: cl91_fec_algn_fsm_live_state [02:00] */ 31793 #define RX_X4_CL91_STATUS0_FEC_ALGN_FSM_STATE_CL91_FEC_ALGN_FSM_LIVE_STATE_MASK 0x0007 31794 #define RX_X4_CL91_STATUS0_FEC_ALGN_FSM_STATE_CL91_FEC_ALGN_FSM_LIVE_STATE_ALIGN 0 31795 #define RX_X4_CL91_STATUS0_FEC_ALGN_FSM_STATE_CL91_FEC_ALGN_FSM_LIVE_STATE_BITS 3 31796 #define RX_X4_CL91_STATUS0_FEC_ALGN_FSM_STATE_CL91_FEC_ALGN_FSM_LIVE_STATE_SHIFT 0 31797 #define RX_X4_CL91_STATUS0_FEC_ALGN_FSM_STATE_CL91_FEC_ALGN_FSM_LIVE_STATE_LOSS_OF_ALIGNMENT 0 31798 #define RX_X4_CL91_STATUS0_FEC_ALGN_FSM_STATE_CL91_FEC_ALGN_FSM_LIVE_STATE_DESKEW 1 31799 #define RX_X4_CL91_STATUS0_FEC_ALGN_FSM_STATE_CL91_FEC_ALGN_FSM_LIVE_STATE_DESKEW_FAIL 2 31800 #define RX_X4_CL91_STATUS0_FEC_ALGN_FSM_STATE_CL91_FEC_ALGN_FSM_LIVE_STATE_ALIGN_ACQUIRED 3 31801 #define RX_X4_CL91_STATUS0_FEC_ALGN_FSM_STATE_CL91_FEC_ALGN_FSM_LIVE_STATE_CW_GOOD 4 31802 #define RX_X4_CL91_STATUS0_FEC_ALGN_FSM_STATE_CL91_FEC_ALGN_FSM_LIVE_STATE_CW_BAD 5 31803 #define RX_X4_CL91_STATUS0_FEC_ALGN_FSM_STATE_CL91_FEC_ALGN_FSM_LIVE_STATE_THREE_BAD 6 31804 31805 31806 /**************************************************************************** 31807 * RX_X4_CL91_Status0 :: cl91_rxp_status 31808 */ 31809 /* RX_X4_CL91_Status0 :: cl91_rxp_status :: reserved0 [15:11] */ 31810 #define RX_X4_CL91_STATUS0_CL91_RXP_STATUS_RESERVED0_MASK 0xf800 31811 #define RX_X4_CL91_STATUS0_CL91_RXP_STATUS_RESERVED0_ALIGN 0 31812 #define RX_X4_CL91_STATUS0_CL91_RXP_STATUS_RESERVED0_BITS 5 31813 #define RX_X4_CL91_STATUS0_CL91_RXP_STATUS_RESERVED0_SHIFT 11 31814 31815 /* RX_X4_CL91_Status0 :: cl91_rxp_status :: fec_byp_ind_ability [10:10] */ 31816 #define RX_X4_CL91_STATUS0_CL91_RXP_STATUS_FEC_BYP_IND_ABILITY_MASK 0x0400 31817 #define RX_X4_CL91_STATUS0_CL91_RXP_STATUS_FEC_BYP_IND_ABILITY_ALIGN 0 31818 #define RX_X4_CL91_STATUS0_CL91_RXP_STATUS_FEC_BYP_IND_ABILITY_BITS 1 31819 #define RX_X4_CL91_STATUS0_CL91_RXP_STATUS_FEC_BYP_IND_ABILITY_SHIFT 10 31820 31821 /* RX_X4_CL91_Status0 :: cl91_rxp_status :: fec_byp_corr_ability [09:09] */ 31822 #define RX_X4_CL91_STATUS0_CL91_RXP_STATUS_FEC_BYP_CORR_ABILITY_MASK 0x0200 31823 #define RX_X4_CL91_STATUS0_CL91_RXP_STATUS_FEC_BYP_CORR_ABILITY_ALIGN 0 31824 #define RX_X4_CL91_STATUS0_CL91_RXP_STATUS_FEC_BYP_CORR_ABILITY_BITS 1 31825 #define RX_X4_CL91_STATUS0_CL91_RXP_STATUS_FEC_BYP_CORR_ABILITY_SHIFT 9 31826 31827 /* RX_X4_CL91_Status0 :: cl91_rxp_status :: hi_ser_LH [08:08] */ 31828 #define RX_X4_CL91_STATUS0_CL91_RXP_STATUS_HI_SER_LH_MASK 0x0100 31829 #define RX_X4_CL91_STATUS0_CL91_RXP_STATUS_HI_SER_LH_ALIGN 0 31830 #define RX_X4_CL91_STATUS0_CL91_RXP_STATUS_HI_SER_LH_BITS 1 31831 #define RX_X4_CL91_STATUS0_CL91_RXP_STATUS_HI_SER_LH_SHIFT 8 31832 31833 /* RX_X4_CL91_Status0 :: cl91_rxp_status :: hi_ser_LL [07:07] */ 31834 #define RX_X4_CL91_STATUS0_CL91_RXP_STATUS_HI_SER_LL_MASK 0x0080 31835 #define RX_X4_CL91_STATUS0_CL91_RXP_STATUS_HI_SER_LL_ALIGN 0 31836 #define RX_X4_CL91_STATUS0_CL91_RXP_STATUS_HI_SER_LL_BITS 1 31837 #define RX_X4_CL91_STATUS0_CL91_RXP_STATUS_HI_SER_LL_SHIFT 7 31838 31839 /* RX_X4_CL91_Status0 :: cl91_rxp_status :: hi_ser_live [06:06] */ 31840 #define RX_X4_CL91_STATUS0_CL91_RXP_STATUS_HI_SER_LIVE_MASK 0x0040 31841 #define RX_X4_CL91_STATUS0_CL91_RXP_STATUS_HI_SER_LIVE_ALIGN 0 31842 #define RX_X4_CL91_STATUS0_CL91_RXP_STATUS_HI_SER_LIVE_BITS 1 31843 #define RX_X4_CL91_STATUS0_CL91_RXP_STATUS_HI_SER_LIVE_SHIFT 6 31844 31845 /* RX_X4_CL91_Status0 :: cl91_rxp_status :: fec_align_status_LH [05:05] */ 31846 #define RX_X4_CL91_STATUS0_CL91_RXP_STATUS_FEC_ALIGN_STATUS_LH_MASK 0x0020 31847 #define RX_X4_CL91_STATUS0_CL91_RXP_STATUS_FEC_ALIGN_STATUS_LH_ALIGN 0 31848 #define RX_X4_CL91_STATUS0_CL91_RXP_STATUS_FEC_ALIGN_STATUS_LH_BITS 1 31849 #define RX_X4_CL91_STATUS0_CL91_RXP_STATUS_FEC_ALIGN_STATUS_LH_SHIFT 5 31850 31851 /* RX_X4_CL91_Status0 :: cl91_rxp_status :: fec_align_status_LL [04:04] */ 31852 #define RX_X4_CL91_STATUS0_CL91_RXP_STATUS_FEC_ALIGN_STATUS_LL_MASK 0x0010 31853 #define RX_X4_CL91_STATUS0_CL91_RXP_STATUS_FEC_ALIGN_STATUS_LL_ALIGN 0 31854 #define RX_X4_CL91_STATUS0_CL91_RXP_STATUS_FEC_ALIGN_STATUS_LL_BITS 1 31855 #define RX_X4_CL91_STATUS0_CL91_RXP_STATUS_FEC_ALIGN_STATUS_LL_SHIFT 4 31856 31857 /* RX_X4_CL91_Status0 :: cl91_rxp_status :: fec_align_status_live [03:03] */ 31858 #define RX_X4_CL91_STATUS0_CL91_RXP_STATUS_FEC_ALIGN_STATUS_LIVE_MASK 0x0008 31859 #define RX_X4_CL91_STATUS0_CL91_RXP_STATUS_FEC_ALIGN_STATUS_LIVE_ALIGN 0 31860 #define RX_X4_CL91_STATUS0_CL91_RXP_STATUS_FEC_ALIGN_STATUS_LIVE_BITS 1 31861 #define RX_X4_CL91_STATUS0_CL91_RXP_STATUS_FEC_ALIGN_STATUS_LIVE_SHIFT 3 31862 31863 /* RX_X4_CL91_Status0 :: cl91_rxp_status :: restart_lock_LH [02:02] */ 31864 #define RX_X4_CL91_STATUS0_CL91_RXP_STATUS_RESTART_LOCK_LH_MASK 0x0004 31865 #define RX_X4_CL91_STATUS0_CL91_RXP_STATUS_RESTART_LOCK_LH_ALIGN 0 31866 #define RX_X4_CL91_STATUS0_CL91_RXP_STATUS_RESTART_LOCK_LH_BITS 1 31867 #define RX_X4_CL91_STATUS0_CL91_RXP_STATUS_RESTART_LOCK_LH_SHIFT 2 31868 31869 /* RX_X4_CL91_Status0 :: cl91_rxp_status :: restart_lock_LL [01:01] */ 31870 #define RX_X4_CL91_STATUS0_CL91_RXP_STATUS_RESTART_LOCK_LL_MASK 0x0002 31871 #define RX_X4_CL91_STATUS0_CL91_RXP_STATUS_RESTART_LOCK_LL_ALIGN 0 31872 #define RX_X4_CL91_STATUS0_CL91_RXP_STATUS_RESTART_LOCK_LL_BITS 1 31873 #define RX_X4_CL91_STATUS0_CL91_RXP_STATUS_RESTART_LOCK_LL_SHIFT 1 31874 31875 /* RX_X4_CL91_Status0 :: cl91_rxp_status :: restart_lock_live [00:00] */ 31876 #define RX_X4_CL91_STATUS0_CL91_RXP_STATUS_RESTART_LOCK_LIVE_MASK 0x0001 31877 #define RX_X4_CL91_STATUS0_CL91_RXP_STATUS_RESTART_LOCK_LIVE_ALIGN 0 31878 #define RX_X4_CL91_STATUS0_CL91_RXP_STATUS_RESTART_LOCK_LIVE_BITS 1 31879 #define RX_X4_CL91_STATUS0_CL91_RXP_STATUS_RESTART_LOCK_LIVE_SHIFT 0 31880 31881 31882 /**************************************************************************** 31883 * RX_X4_CL91_Status0 :: fec_corrected_counter_0 31884 */ 31885 /* RX_X4_CL91_Status0 :: fec_corrected_counter_0 :: cl91_fec_corr_cw_cntr_lower [15:00] */ 31886 #define RX_X4_CL91_STATUS0_FEC_CORRECTED_COUNTER_0_CL91_FEC_CORR_CW_CNTR_LOWER_MASK 0xffff 31887 #define RX_X4_CL91_STATUS0_FEC_CORRECTED_COUNTER_0_CL91_FEC_CORR_CW_CNTR_LOWER_ALIGN 0 31888 #define RX_X4_CL91_STATUS0_FEC_CORRECTED_COUNTER_0_CL91_FEC_CORR_CW_CNTR_LOWER_BITS 16 31889 #define RX_X4_CL91_STATUS0_FEC_CORRECTED_COUNTER_0_CL91_FEC_CORR_CW_CNTR_LOWER_SHIFT 0 31890 31891 31892 /**************************************************************************** 31893 * RX_X4_CL91_Status0 :: fec_corrected_counter_1 31894 */ 31895 /* RX_X4_CL91_Status0 :: fec_corrected_counter_1 :: cl91_fec_corr_cw_cntr_upper [15:00] */ 31896 #define RX_X4_CL91_STATUS0_FEC_CORRECTED_COUNTER_1_CL91_FEC_CORR_CW_CNTR_UPPER_MASK 0xffff 31897 #define RX_X4_CL91_STATUS0_FEC_CORRECTED_COUNTER_1_CL91_FEC_CORR_CW_CNTR_UPPER_ALIGN 0 31898 #define RX_X4_CL91_STATUS0_FEC_CORRECTED_COUNTER_1_CL91_FEC_CORR_CW_CNTR_UPPER_BITS 16 31899 #define RX_X4_CL91_STATUS0_FEC_CORRECTED_COUNTER_1_CL91_FEC_CORR_CW_CNTR_UPPER_SHIFT 0 31900 31901 31902 /**************************************************************************** 31903 * RX_X4_CL91_Status0 :: fec_uncorrected_counter_0 31904 */ 31905 /* RX_X4_CL91_Status0 :: fec_uncorrected_counter_0 :: cl91_fec_uncorr_cw_cntr_lower [15:00] */ 31906 #define RX_X4_CL91_STATUS0_FEC_UNCORRECTED_COUNTER_0_CL91_FEC_UNCORR_CW_CNTR_LOWER_MASK 0xffff 31907 #define RX_X4_CL91_STATUS0_FEC_UNCORRECTED_COUNTER_0_CL91_FEC_UNCORR_CW_CNTR_LOWER_ALIGN 0 31908 #define RX_X4_CL91_STATUS0_FEC_UNCORRECTED_COUNTER_0_CL91_FEC_UNCORR_CW_CNTR_LOWER_BITS 16 31909 #define RX_X4_CL91_STATUS0_FEC_UNCORRECTED_COUNTER_0_CL91_FEC_UNCORR_CW_CNTR_LOWER_SHIFT 0 31910 31911 31912 /**************************************************************************** 31913 * RX_X4_CL91_Status0 :: fec_uncorrected_counter_1 31914 */ 31915 /* RX_X4_CL91_Status0 :: fec_uncorrected_counter_1 :: cl91_fec_uncorr_cw_cntr_upper [15:00] */ 31916 #define RX_X4_CL91_STATUS0_FEC_UNCORRECTED_COUNTER_1_CL91_FEC_UNCORR_CW_CNTR_UPPER_MASK 0xffff 31917 #define RX_X4_CL91_STATUS0_FEC_UNCORRECTED_COUNTER_1_CL91_FEC_UNCORR_CW_CNTR_UPPER_ALIGN 0 31918 #define RX_X4_CL91_STATUS0_FEC_UNCORRECTED_COUNTER_1_CL91_FEC_UNCORR_CW_CNTR_UPPER_BITS 16 31919 #define RX_X4_CL91_STATUS0_FEC_UNCORRECTED_COUNTER_1_CL91_FEC_UNCORR_CW_CNTR_UPPER_SHIFT 0 31920 31921 31922 /**************************************************************************** 31923 * RX_X4_CL91_Status0 :: fec_bit_error_counter_0 31924 */ 31925 /* RX_X4_CL91_Status0 :: fec_bit_error_counter_0 :: cl91_fec_corr_bit_cntr_lower [15:00] */ 31926 #define RX_X4_CL91_STATUS0_FEC_BIT_ERROR_COUNTER_0_CL91_FEC_CORR_BIT_CNTR_LOWER_MASK 0xffff 31927 #define RX_X4_CL91_STATUS0_FEC_BIT_ERROR_COUNTER_0_CL91_FEC_CORR_BIT_CNTR_LOWER_ALIGN 0 31928 #define RX_X4_CL91_STATUS0_FEC_BIT_ERROR_COUNTER_0_CL91_FEC_CORR_BIT_CNTR_LOWER_BITS 16 31929 #define RX_X4_CL91_STATUS0_FEC_BIT_ERROR_COUNTER_0_CL91_FEC_CORR_BIT_CNTR_LOWER_SHIFT 0 31930 31931 31932 /**************************************************************************** 31933 * RX_X4_CL91_Status0 :: fec_bit_error_counter_1 31934 */ 31935 /* RX_X4_CL91_Status0 :: fec_bit_error_counter_1 :: cl91_fec_corr_bit_cntr_upper [15:00] */ 31936 #define RX_X4_CL91_STATUS0_FEC_BIT_ERROR_COUNTER_1_CL91_FEC_CORR_BIT_CNTR_UPPER_MASK 0xffff 31937 #define RX_X4_CL91_STATUS0_FEC_BIT_ERROR_COUNTER_1_CL91_FEC_CORR_BIT_CNTR_UPPER_ALIGN 0 31938 #define RX_X4_CL91_STATUS0_FEC_BIT_ERROR_COUNTER_1_CL91_FEC_CORR_BIT_CNTR_UPPER_BITS 16 31939 #define RX_X4_CL91_STATUS0_FEC_BIT_ERROR_COUNTER_1_CL91_FEC_CORR_BIT_CNTR_UPPER_SHIFT 0 31940 31941 31942 /**************************************************************************** 31943 * TSC_WC4_TSC_USER4_RX_X4_CL91_Status1 31944 */ 31945 /**************************************************************************** 31946 * RX_X4_CL91_Status1 :: cl91_fec_symb_err_cntr_low_0 31947 */ 31948 /* RX_X4_CL91_Status1 :: cl91_fec_symb_err_cntr_low_0 :: fec_symbol_error_counter_lower_0 [15:00] */ 31949 #define RX_X4_CL91_STATUS1_CL91_FEC_SYMB_ERR_CNTR_LOW_0_FEC_SYMBOL_ERROR_COUNTER_LOWER_0_MASK 0xffff 31950 #define RX_X4_CL91_STATUS1_CL91_FEC_SYMB_ERR_CNTR_LOW_0_FEC_SYMBOL_ERROR_COUNTER_LOWER_0_ALIGN 0 31951 #define RX_X4_CL91_STATUS1_CL91_FEC_SYMB_ERR_CNTR_LOW_0_FEC_SYMBOL_ERROR_COUNTER_LOWER_0_BITS 16 31952 #define RX_X4_CL91_STATUS1_CL91_FEC_SYMB_ERR_CNTR_LOW_0_FEC_SYMBOL_ERROR_COUNTER_LOWER_0_SHIFT 0 31953 31954 31955 /**************************************************************************** 31956 * RX_X4_CL91_Status1 :: cl91_fec_symb_err_cntr_up_0 31957 */ 31958 /* RX_X4_CL91_Status1 :: cl91_fec_symb_err_cntr_up_0 :: fec_symbol_error_counter_upper_0 [15:00] */ 31959 #define RX_X4_CL91_STATUS1_CL91_FEC_SYMB_ERR_CNTR_UP_0_FEC_SYMBOL_ERROR_COUNTER_UPPER_0_MASK 0xffff 31960 #define RX_X4_CL91_STATUS1_CL91_FEC_SYMB_ERR_CNTR_UP_0_FEC_SYMBOL_ERROR_COUNTER_UPPER_0_ALIGN 0 31961 #define RX_X4_CL91_STATUS1_CL91_FEC_SYMB_ERR_CNTR_UP_0_FEC_SYMBOL_ERROR_COUNTER_UPPER_0_BITS 16 31962 #define RX_X4_CL91_STATUS1_CL91_FEC_SYMB_ERR_CNTR_UP_0_FEC_SYMBOL_ERROR_COUNTER_UPPER_0_SHIFT 0 31963 31964 31965 /**************************************************************************** 31966 * RX_X4_CL91_Status1 :: cl91_fec_symb_err_cntr_low_1 31967 */ 31968 /* RX_X4_CL91_Status1 :: cl91_fec_symb_err_cntr_low_1 :: fec_symbol_error_counter_lower_1 [15:00] */ 31969 #define RX_X4_CL91_STATUS1_CL91_FEC_SYMB_ERR_CNTR_LOW_1_FEC_SYMBOL_ERROR_COUNTER_LOWER_1_MASK 0xffff 31970 #define RX_X4_CL91_STATUS1_CL91_FEC_SYMB_ERR_CNTR_LOW_1_FEC_SYMBOL_ERROR_COUNTER_LOWER_1_ALIGN 0 31971 #define RX_X4_CL91_STATUS1_CL91_FEC_SYMB_ERR_CNTR_LOW_1_FEC_SYMBOL_ERROR_COUNTER_LOWER_1_BITS 16 31972 #define RX_X4_CL91_STATUS1_CL91_FEC_SYMB_ERR_CNTR_LOW_1_FEC_SYMBOL_ERROR_COUNTER_LOWER_1_SHIFT 0 31973 31974 31975 /**************************************************************************** 31976 * RX_X4_CL91_Status1 :: cl91_fec_symb_err_cntr_up_1 31977 */ 31978 /* RX_X4_CL91_Status1 :: cl91_fec_symb_err_cntr_up_1 :: fec_symbol_error_counter_upper_1 [15:00] */ 31979 #define RX_X4_CL91_STATUS1_CL91_FEC_SYMB_ERR_CNTR_UP_1_FEC_SYMBOL_ERROR_COUNTER_UPPER_1_MASK 0xffff 31980 #define RX_X4_CL91_STATUS1_CL91_FEC_SYMB_ERR_CNTR_UP_1_FEC_SYMBOL_ERROR_COUNTER_UPPER_1_ALIGN 0 31981 #define RX_X4_CL91_STATUS1_CL91_FEC_SYMB_ERR_CNTR_UP_1_FEC_SYMBOL_ERROR_COUNTER_UPPER_1_BITS 16 31982 #define RX_X4_CL91_STATUS1_CL91_FEC_SYMB_ERR_CNTR_UP_1_FEC_SYMBOL_ERROR_COUNTER_UPPER_1_SHIFT 0 31983 31984 31985 /**************************************************************************** 31986 * RX_X4_CL91_Status1 :: cl91_fec_symb_err_cntr_low_2 31987 */ 31988 /* RX_X4_CL91_Status1 :: cl91_fec_symb_err_cntr_low_2 :: fec_symbol_error_counter_lower_2 [15:00] */ 31989 #define RX_X4_CL91_STATUS1_CL91_FEC_SYMB_ERR_CNTR_LOW_2_FEC_SYMBOL_ERROR_COUNTER_LOWER_2_MASK 0xffff 31990 #define RX_X4_CL91_STATUS1_CL91_FEC_SYMB_ERR_CNTR_LOW_2_FEC_SYMBOL_ERROR_COUNTER_LOWER_2_ALIGN 0 31991 #define RX_X4_CL91_STATUS1_CL91_FEC_SYMB_ERR_CNTR_LOW_2_FEC_SYMBOL_ERROR_COUNTER_LOWER_2_BITS 16 31992 #define RX_X4_CL91_STATUS1_CL91_FEC_SYMB_ERR_CNTR_LOW_2_FEC_SYMBOL_ERROR_COUNTER_LOWER_2_SHIFT 0 31993 31994 31995 /**************************************************************************** 31996 * RX_X4_CL91_Status1 :: cl91_fec_symb_err_cntr_up_2 31997 */ 31998 /* RX_X4_CL91_Status1 :: cl91_fec_symb_err_cntr_up_2 :: fec_symbol_error_counter_upper_2 [15:00] */ 31999 #define RX_X4_CL91_STATUS1_CL91_FEC_SYMB_ERR_CNTR_UP_2_FEC_SYMBOL_ERROR_COUNTER_UPPER_2_MASK 0xffff 32000 #define RX_X4_CL91_STATUS1_CL91_FEC_SYMB_ERR_CNTR_UP_2_FEC_SYMBOL_ERROR_COUNTER_UPPER_2_ALIGN 0 32001 #define RX_X4_CL91_STATUS1_CL91_FEC_SYMB_ERR_CNTR_UP_2_FEC_SYMBOL_ERROR_COUNTER_UPPER_2_BITS 16 32002 #define RX_X4_CL91_STATUS1_CL91_FEC_SYMB_ERR_CNTR_UP_2_FEC_SYMBOL_ERROR_COUNTER_UPPER_2_SHIFT 0 32003 32004 32005 /**************************************************************************** 32006 * RX_X4_CL91_Status1 :: cl91_fec_symb_err_cntr_low_3 32007 */ 32008 /* RX_X4_CL91_Status1 :: cl91_fec_symb_err_cntr_low_3 :: fec_symbol_error_counter_lower_3 [15:00] */ 32009 #define RX_X4_CL91_STATUS1_CL91_FEC_SYMB_ERR_CNTR_LOW_3_FEC_SYMBOL_ERROR_COUNTER_LOWER_3_MASK 0xffff 32010 #define RX_X4_CL91_STATUS1_CL91_FEC_SYMB_ERR_CNTR_LOW_3_FEC_SYMBOL_ERROR_COUNTER_LOWER_3_ALIGN 0 32011 #define RX_X4_CL91_STATUS1_CL91_FEC_SYMB_ERR_CNTR_LOW_3_FEC_SYMBOL_ERROR_COUNTER_LOWER_3_BITS 16 32012 #define RX_X4_CL91_STATUS1_CL91_FEC_SYMB_ERR_CNTR_LOW_3_FEC_SYMBOL_ERROR_COUNTER_LOWER_3_SHIFT 0 32013 32014 32015 /**************************************************************************** 32016 * RX_X4_CL91_Status1 :: cl91_fec_symb_err_cntr_up_3 32017 */ 32018 /* RX_X4_CL91_Status1 :: cl91_fec_symb_err_cntr_up_3 :: fec_symbol_error_counter_upper_3 [15:00] */ 32019 #define RX_X4_CL91_STATUS1_CL91_FEC_SYMB_ERR_CNTR_UP_3_FEC_SYMBOL_ERROR_COUNTER_UPPER_3_MASK 0xffff 32020 #define RX_X4_CL91_STATUS1_CL91_FEC_SYMB_ERR_CNTR_UP_3_FEC_SYMBOL_ERROR_COUNTER_UPPER_3_ALIGN 0 32021 #define RX_X4_CL91_STATUS1_CL91_FEC_SYMB_ERR_CNTR_UP_3_FEC_SYMBOL_ERROR_COUNTER_UPPER_3_BITS 16 32022 #define RX_X4_CL91_STATUS1_CL91_FEC_SYMB_ERR_CNTR_UP_3_FEC_SYMBOL_ERROR_COUNTER_UPPER_3_SHIFT 0 32023 32024 32025 /**************************************************************************** 32026 * TSC_WC4_TSC_USER4_RX_X4_ECC 32027 */ 32028 /**************************************************************************** 32029 * RX_X4_ECC :: status_cl91_buffer_blk_0 32030 */ 32031 /* RX_X4_ECC :: status_cl91_buffer_blk_0 :: two_bit_err_event_cl91_buffer_blk_0 [15:15] */ 32032 #define RX_X4_ECC_STATUS_CL91_BUFFER_BLK_0_TWO_BIT_ERR_EVENT_CL91_BUFFER_BLK_0_MASK 0x8000 32033 #define RX_X4_ECC_STATUS_CL91_BUFFER_BLK_0_TWO_BIT_ERR_EVENT_CL91_BUFFER_BLK_0_ALIGN 0 32034 #define RX_X4_ECC_STATUS_CL91_BUFFER_BLK_0_TWO_BIT_ERR_EVENT_CL91_BUFFER_BLK_0_BITS 1 32035 #define RX_X4_ECC_STATUS_CL91_BUFFER_BLK_0_TWO_BIT_ERR_EVENT_CL91_BUFFER_BLK_0_SHIFT 15 32036 32037 /* RX_X4_ECC :: status_cl91_buffer_blk_0 :: one_bit_err_event_cl91_buffer_blk_0 [14:14] */ 32038 #define RX_X4_ECC_STATUS_CL91_BUFFER_BLK_0_ONE_BIT_ERR_EVENT_CL91_BUFFER_BLK_0_MASK 0x4000 32039 #define RX_X4_ECC_STATUS_CL91_BUFFER_BLK_0_ONE_BIT_ERR_EVENT_CL91_BUFFER_BLK_0_ALIGN 0 32040 #define RX_X4_ECC_STATUS_CL91_BUFFER_BLK_0_ONE_BIT_ERR_EVENT_CL91_BUFFER_BLK_0_BITS 1 32041 #define RX_X4_ECC_STATUS_CL91_BUFFER_BLK_0_ONE_BIT_ERR_EVENT_CL91_BUFFER_BLK_0_SHIFT 14 32042 32043 /* RX_X4_ECC :: status_cl91_buffer_blk_0 :: err_event_address_cl91_buffer_blk_0 [13:00] */ 32044 #define RX_X4_ECC_STATUS_CL91_BUFFER_BLK_0_ERR_EVENT_ADDRESS_CL91_BUFFER_BLK_0_MASK 0x3fff 32045 #define RX_X4_ECC_STATUS_CL91_BUFFER_BLK_0_ERR_EVENT_ADDRESS_CL91_BUFFER_BLK_0_ALIGN 0 32046 #define RX_X4_ECC_STATUS_CL91_BUFFER_BLK_0_ERR_EVENT_ADDRESS_CL91_BUFFER_BLK_0_BITS 14 32047 #define RX_X4_ECC_STATUS_CL91_BUFFER_BLK_0_ERR_EVENT_ADDRESS_CL91_BUFFER_BLK_0_SHIFT 0 32048 32049 32050 /**************************************************************************** 32051 * RX_X4_ECC :: status_cl91_buffer_blk_1 32052 */ 32053 /* RX_X4_ECC :: status_cl91_buffer_blk_1 :: two_bit_err_event_cl91_buffer_blk_1 [15:15] */ 32054 #define RX_X4_ECC_STATUS_CL91_BUFFER_BLK_1_TWO_BIT_ERR_EVENT_CL91_BUFFER_BLK_1_MASK 0x8000 32055 #define RX_X4_ECC_STATUS_CL91_BUFFER_BLK_1_TWO_BIT_ERR_EVENT_CL91_BUFFER_BLK_1_ALIGN 0 32056 #define RX_X4_ECC_STATUS_CL91_BUFFER_BLK_1_TWO_BIT_ERR_EVENT_CL91_BUFFER_BLK_1_BITS 1 32057 #define RX_X4_ECC_STATUS_CL91_BUFFER_BLK_1_TWO_BIT_ERR_EVENT_CL91_BUFFER_BLK_1_SHIFT 15 32058 32059 /* RX_X4_ECC :: status_cl91_buffer_blk_1 :: one_bit_err_event_cl91_buffer_blk_1 [14:14] */ 32060 #define RX_X4_ECC_STATUS_CL91_BUFFER_BLK_1_ONE_BIT_ERR_EVENT_CL91_BUFFER_BLK_1_MASK 0x4000 32061 #define RX_X4_ECC_STATUS_CL91_BUFFER_BLK_1_ONE_BIT_ERR_EVENT_CL91_BUFFER_BLK_1_ALIGN 0 32062 #define RX_X4_ECC_STATUS_CL91_BUFFER_BLK_1_ONE_BIT_ERR_EVENT_CL91_BUFFER_BLK_1_BITS 1 32063 #define RX_X4_ECC_STATUS_CL91_BUFFER_BLK_1_ONE_BIT_ERR_EVENT_CL91_BUFFER_BLK_1_SHIFT 14 32064 32065 /* RX_X4_ECC :: status_cl91_buffer_blk_1 :: err_event_address_cl91_buffer_blk_1 [13:00] */ 32066 #define RX_X4_ECC_STATUS_CL91_BUFFER_BLK_1_ERR_EVENT_ADDRESS_CL91_BUFFER_BLK_1_MASK 0x3fff 32067 #define RX_X4_ECC_STATUS_CL91_BUFFER_BLK_1_ERR_EVENT_ADDRESS_CL91_BUFFER_BLK_1_ALIGN 0 32068 #define RX_X4_ECC_STATUS_CL91_BUFFER_BLK_1_ERR_EVENT_ADDRESS_CL91_BUFFER_BLK_1_BITS 14 32069 #define RX_X4_ECC_STATUS_CL91_BUFFER_BLK_1_ERR_EVENT_ADDRESS_CL91_BUFFER_BLK_1_SHIFT 0 32070 32071 32072 /**************************************************************************** 32073 * RX_X4_ECC :: status_cl91_buffer_blk_2 32074 */ 32075 /* RX_X4_ECC :: status_cl91_buffer_blk_2 :: two_bit_err_event_cl91_buffer_blk_2 [15:15] */ 32076 #define RX_X4_ECC_STATUS_CL91_BUFFER_BLK_2_TWO_BIT_ERR_EVENT_CL91_BUFFER_BLK_2_MASK 0x8000 32077 #define RX_X4_ECC_STATUS_CL91_BUFFER_BLK_2_TWO_BIT_ERR_EVENT_CL91_BUFFER_BLK_2_ALIGN 0 32078 #define RX_X4_ECC_STATUS_CL91_BUFFER_BLK_2_TWO_BIT_ERR_EVENT_CL91_BUFFER_BLK_2_BITS 1 32079 #define RX_X4_ECC_STATUS_CL91_BUFFER_BLK_2_TWO_BIT_ERR_EVENT_CL91_BUFFER_BLK_2_SHIFT 15 32080 32081 /* RX_X4_ECC :: status_cl91_buffer_blk_2 :: one_bit_err_event_cl91_buffer_blk_2 [14:14] */ 32082 #define RX_X4_ECC_STATUS_CL91_BUFFER_BLK_2_ONE_BIT_ERR_EVENT_CL91_BUFFER_BLK_2_MASK 0x4000 32083 #define RX_X4_ECC_STATUS_CL91_BUFFER_BLK_2_ONE_BIT_ERR_EVENT_CL91_BUFFER_BLK_2_ALIGN 0 32084 #define RX_X4_ECC_STATUS_CL91_BUFFER_BLK_2_ONE_BIT_ERR_EVENT_CL91_BUFFER_BLK_2_BITS 1 32085 #define RX_X4_ECC_STATUS_CL91_BUFFER_BLK_2_ONE_BIT_ERR_EVENT_CL91_BUFFER_BLK_2_SHIFT 14 32086 32087 /* RX_X4_ECC :: status_cl91_buffer_blk_2 :: err_event_address_cl91_buffer_blk_2 [13:00] */ 32088 #define RX_X4_ECC_STATUS_CL91_BUFFER_BLK_2_ERR_EVENT_ADDRESS_CL91_BUFFER_BLK_2_MASK 0x3fff 32089 #define RX_X4_ECC_STATUS_CL91_BUFFER_BLK_2_ERR_EVENT_ADDRESS_CL91_BUFFER_BLK_2_ALIGN 0 32090 #define RX_X4_ECC_STATUS_CL91_BUFFER_BLK_2_ERR_EVENT_ADDRESS_CL91_BUFFER_BLK_2_BITS 14 32091 #define RX_X4_ECC_STATUS_CL91_BUFFER_BLK_2_ERR_EVENT_ADDRESS_CL91_BUFFER_BLK_2_SHIFT 0 32092 32093 32094 /**************************************************************************** 32095 * RX_X4_ECC :: status_deskew_mem_0 32096 */ 32097 /* RX_X4_ECC :: status_deskew_mem_0 :: two_bit_err_event_deskew_0 [15:15] */ 32098 #define RX_X4_ECC_STATUS_DESKEW_MEM_0_TWO_BIT_ERR_EVENT_DESKEW_0_MASK 0x8000 32099 #define RX_X4_ECC_STATUS_DESKEW_MEM_0_TWO_BIT_ERR_EVENT_DESKEW_0_ALIGN 0 32100 #define RX_X4_ECC_STATUS_DESKEW_MEM_0_TWO_BIT_ERR_EVENT_DESKEW_0_BITS 1 32101 #define RX_X4_ECC_STATUS_DESKEW_MEM_0_TWO_BIT_ERR_EVENT_DESKEW_0_SHIFT 15 32102 32103 /* RX_X4_ECC :: status_deskew_mem_0 :: one_bit_err_event_deskew_0 [14:14] */ 32104 #define RX_X4_ECC_STATUS_DESKEW_MEM_0_ONE_BIT_ERR_EVENT_DESKEW_0_MASK 0x4000 32105 #define RX_X4_ECC_STATUS_DESKEW_MEM_0_ONE_BIT_ERR_EVENT_DESKEW_0_ALIGN 0 32106 #define RX_X4_ECC_STATUS_DESKEW_MEM_0_ONE_BIT_ERR_EVENT_DESKEW_0_BITS 1 32107 #define RX_X4_ECC_STATUS_DESKEW_MEM_0_ONE_BIT_ERR_EVENT_DESKEW_0_SHIFT 14 32108 32109 /* RX_X4_ECC :: status_deskew_mem_0 :: err_event_address_deskew_0 [13:00] */ 32110 #define RX_X4_ECC_STATUS_DESKEW_MEM_0_ERR_EVENT_ADDRESS_DESKEW_0_MASK 0x3fff 32111 #define RX_X4_ECC_STATUS_DESKEW_MEM_0_ERR_EVENT_ADDRESS_DESKEW_0_ALIGN 0 32112 #define RX_X4_ECC_STATUS_DESKEW_MEM_0_ERR_EVENT_ADDRESS_DESKEW_0_BITS 14 32113 #define RX_X4_ECC_STATUS_DESKEW_MEM_0_ERR_EVENT_ADDRESS_DESKEW_0_SHIFT 0 32114 32115 32116 /**************************************************************************** 32117 * RX_X4_ECC :: status_deskew_mem_1 32118 */ 32119 /* RX_X4_ECC :: status_deskew_mem_1 :: two_bit_err_event_deskew_1 [15:15] */ 32120 #define RX_X4_ECC_STATUS_DESKEW_MEM_1_TWO_BIT_ERR_EVENT_DESKEW_1_MASK 0x8000 32121 #define RX_X4_ECC_STATUS_DESKEW_MEM_1_TWO_BIT_ERR_EVENT_DESKEW_1_ALIGN 0 32122 #define RX_X4_ECC_STATUS_DESKEW_MEM_1_TWO_BIT_ERR_EVENT_DESKEW_1_BITS 1 32123 #define RX_X4_ECC_STATUS_DESKEW_MEM_1_TWO_BIT_ERR_EVENT_DESKEW_1_SHIFT 15 32124 32125 /* RX_X4_ECC :: status_deskew_mem_1 :: one_bit_err_event_deskew_1 [14:14] */ 32126 #define RX_X4_ECC_STATUS_DESKEW_MEM_1_ONE_BIT_ERR_EVENT_DESKEW_1_MASK 0x4000 32127 #define RX_X4_ECC_STATUS_DESKEW_MEM_1_ONE_BIT_ERR_EVENT_DESKEW_1_ALIGN 0 32128 #define RX_X4_ECC_STATUS_DESKEW_MEM_1_ONE_BIT_ERR_EVENT_DESKEW_1_BITS 1 32129 #define RX_X4_ECC_STATUS_DESKEW_MEM_1_ONE_BIT_ERR_EVENT_DESKEW_1_SHIFT 14 32130 32131 /* RX_X4_ECC :: status_deskew_mem_1 :: err_event_address_deskew_1 [13:00] */ 32132 #define RX_X4_ECC_STATUS_DESKEW_MEM_1_ERR_EVENT_ADDRESS_DESKEW_1_MASK 0x3fff 32133 #define RX_X4_ECC_STATUS_DESKEW_MEM_1_ERR_EVENT_ADDRESS_DESKEW_1_ALIGN 0 32134 #define RX_X4_ECC_STATUS_DESKEW_MEM_1_ERR_EVENT_ADDRESS_DESKEW_1_BITS 14 32135 #define RX_X4_ECC_STATUS_DESKEW_MEM_1_ERR_EVENT_ADDRESS_DESKEW_1_SHIFT 0 32136 32137 32138 /**************************************************************************** 32139 * RX_X4_ECC :: status_deskew_mem_2 32140 */ 32141 /* RX_X4_ECC :: status_deskew_mem_2 :: two_bit_err_event_deskew_2 [15:15] */ 32142 #define RX_X4_ECC_STATUS_DESKEW_MEM_2_TWO_BIT_ERR_EVENT_DESKEW_2_MASK 0x8000 32143 #define RX_X4_ECC_STATUS_DESKEW_MEM_2_TWO_BIT_ERR_EVENT_DESKEW_2_ALIGN 0 32144 #define RX_X4_ECC_STATUS_DESKEW_MEM_2_TWO_BIT_ERR_EVENT_DESKEW_2_BITS 1 32145 #define RX_X4_ECC_STATUS_DESKEW_MEM_2_TWO_BIT_ERR_EVENT_DESKEW_2_SHIFT 15 32146 32147 /* RX_X4_ECC :: status_deskew_mem_2 :: one_bit_err_event_deskew_2 [14:14] */ 32148 #define RX_X4_ECC_STATUS_DESKEW_MEM_2_ONE_BIT_ERR_EVENT_DESKEW_2_MASK 0x4000 32149 #define RX_X4_ECC_STATUS_DESKEW_MEM_2_ONE_BIT_ERR_EVENT_DESKEW_2_ALIGN 0 32150 #define RX_X4_ECC_STATUS_DESKEW_MEM_2_ONE_BIT_ERR_EVENT_DESKEW_2_BITS 1 32151 #define RX_X4_ECC_STATUS_DESKEW_MEM_2_ONE_BIT_ERR_EVENT_DESKEW_2_SHIFT 14 32152 32153 /* RX_X4_ECC :: status_deskew_mem_2 :: err_event_address_deskew_2 [13:00] */ 32154 #define RX_X4_ECC_STATUS_DESKEW_MEM_2_ERR_EVENT_ADDRESS_DESKEW_2_MASK 0x3fff 32155 #define RX_X4_ECC_STATUS_DESKEW_MEM_2_ERR_EVENT_ADDRESS_DESKEW_2_ALIGN 0 32156 #define RX_X4_ECC_STATUS_DESKEW_MEM_2_ERR_EVENT_ADDRESS_DESKEW_2_BITS 14 32157 #define RX_X4_ECC_STATUS_DESKEW_MEM_2_ERR_EVENT_ADDRESS_DESKEW_2_SHIFT 0 32158 32159 32160 /**************************************************************************** 32161 * RX_X4_ECC :: interrupt_status_1bit 32162 */ 32163 /* RX_X4_ECC :: interrupt_status_1bit :: reserved0 [15:06] */ 32164 #define RX_X4_ECC_INTERRUPT_STATUS_1BIT_RESERVED0_MASK 0xffc0 32165 #define RX_X4_ECC_INTERRUPT_STATUS_1BIT_RESERVED0_ALIGN 0 32166 #define RX_X4_ECC_INTERRUPT_STATUS_1BIT_RESERVED0_BITS 10 32167 #define RX_X4_ECC_INTERRUPT_STATUS_1BIT_RESERVED0_SHIFT 6 32168 32169 /* RX_X4_ECC :: interrupt_status_1bit :: deskew_mem_2_1bit_int_status [05:05] */ 32170 #define RX_X4_ECC_INTERRUPT_STATUS_1BIT_DESKEW_MEM_2_1BIT_INT_STATUS_MASK 0x0020 32171 #define RX_X4_ECC_INTERRUPT_STATUS_1BIT_DESKEW_MEM_2_1BIT_INT_STATUS_ALIGN 0 32172 #define RX_X4_ECC_INTERRUPT_STATUS_1BIT_DESKEW_MEM_2_1BIT_INT_STATUS_BITS 1 32173 #define RX_X4_ECC_INTERRUPT_STATUS_1BIT_DESKEW_MEM_2_1BIT_INT_STATUS_SHIFT 5 32174 32175 /* RX_X4_ECC :: interrupt_status_1bit :: deskew_mem_1_1bit_int_status [04:04] */ 32176 #define RX_X4_ECC_INTERRUPT_STATUS_1BIT_DESKEW_MEM_1_1BIT_INT_STATUS_MASK 0x0010 32177 #define RX_X4_ECC_INTERRUPT_STATUS_1BIT_DESKEW_MEM_1_1BIT_INT_STATUS_ALIGN 0 32178 #define RX_X4_ECC_INTERRUPT_STATUS_1BIT_DESKEW_MEM_1_1BIT_INT_STATUS_BITS 1 32179 #define RX_X4_ECC_INTERRUPT_STATUS_1BIT_DESKEW_MEM_1_1BIT_INT_STATUS_SHIFT 4 32180 32181 /* RX_X4_ECC :: interrupt_status_1bit :: deskew_mem_0_1bit_int_status [03:03] */ 32182 #define RX_X4_ECC_INTERRUPT_STATUS_1BIT_DESKEW_MEM_0_1BIT_INT_STATUS_MASK 0x0008 32183 #define RX_X4_ECC_INTERRUPT_STATUS_1BIT_DESKEW_MEM_0_1BIT_INT_STATUS_ALIGN 0 32184 #define RX_X4_ECC_INTERRUPT_STATUS_1BIT_DESKEW_MEM_0_1BIT_INT_STATUS_BITS 1 32185 #define RX_X4_ECC_INTERRUPT_STATUS_1BIT_DESKEW_MEM_0_1BIT_INT_STATUS_SHIFT 3 32186 32187 /* RX_X4_ECC :: interrupt_status_1bit :: cl91_buffer_blk2_1bit_int_status [02:02] */ 32188 #define RX_X4_ECC_INTERRUPT_STATUS_1BIT_CL91_BUFFER_BLK2_1BIT_INT_STATUS_MASK 0x0004 32189 #define RX_X4_ECC_INTERRUPT_STATUS_1BIT_CL91_BUFFER_BLK2_1BIT_INT_STATUS_ALIGN 0 32190 #define RX_X4_ECC_INTERRUPT_STATUS_1BIT_CL91_BUFFER_BLK2_1BIT_INT_STATUS_BITS 1 32191 #define RX_X4_ECC_INTERRUPT_STATUS_1BIT_CL91_BUFFER_BLK2_1BIT_INT_STATUS_SHIFT 2 32192 32193 /* RX_X4_ECC :: interrupt_status_1bit :: cl91_buffer_blk1_1bit_int_status [01:01] */ 32194 #define RX_X4_ECC_INTERRUPT_STATUS_1BIT_CL91_BUFFER_BLK1_1BIT_INT_STATUS_MASK 0x0002 32195 #define RX_X4_ECC_INTERRUPT_STATUS_1BIT_CL91_BUFFER_BLK1_1BIT_INT_STATUS_ALIGN 0 32196 #define RX_X4_ECC_INTERRUPT_STATUS_1BIT_CL91_BUFFER_BLK1_1BIT_INT_STATUS_BITS 1 32197 #define RX_X4_ECC_INTERRUPT_STATUS_1BIT_CL91_BUFFER_BLK1_1BIT_INT_STATUS_SHIFT 1 32198 32199 /* RX_X4_ECC :: interrupt_status_1bit :: cl91_buffer_blk0_1bit_int_status [00:00] */ 32200 #define RX_X4_ECC_INTERRUPT_STATUS_1BIT_CL91_BUFFER_BLK0_1BIT_INT_STATUS_MASK 0x0001 32201 #define RX_X4_ECC_INTERRUPT_STATUS_1BIT_CL91_BUFFER_BLK0_1BIT_INT_STATUS_ALIGN 0 32202 #define RX_X4_ECC_INTERRUPT_STATUS_1BIT_CL91_BUFFER_BLK0_1BIT_INT_STATUS_BITS 1 32203 #define RX_X4_ECC_INTERRUPT_STATUS_1BIT_CL91_BUFFER_BLK0_1BIT_INT_STATUS_SHIFT 0 32204 32205 32206 /**************************************************************************** 32207 * RX_X4_ECC :: interrupt_status_2bit 32208 */ 32209 /* RX_X4_ECC :: interrupt_status_2bit :: reserved0 [15:06] */ 32210 #define RX_X4_ECC_INTERRUPT_STATUS_2BIT_RESERVED0_MASK 0xffc0 32211 #define RX_X4_ECC_INTERRUPT_STATUS_2BIT_RESERVED0_ALIGN 0 32212 #define RX_X4_ECC_INTERRUPT_STATUS_2BIT_RESERVED0_BITS 10 32213 #define RX_X4_ECC_INTERRUPT_STATUS_2BIT_RESERVED0_SHIFT 6 32214 32215 /* RX_X4_ECC :: interrupt_status_2bit :: deskew_mem_2_2bit_int_status [05:05] */ 32216 #define RX_X4_ECC_INTERRUPT_STATUS_2BIT_DESKEW_MEM_2_2BIT_INT_STATUS_MASK 0x0020 32217 #define RX_X4_ECC_INTERRUPT_STATUS_2BIT_DESKEW_MEM_2_2BIT_INT_STATUS_ALIGN 0 32218 #define RX_X4_ECC_INTERRUPT_STATUS_2BIT_DESKEW_MEM_2_2BIT_INT_STATUS_BITS 1 32219 #define RX_X4_ECC_INTERRUPT_STATUS_2BIT_DESKEW_MEM_2_2BIT_INT_STATUS_SHIFT 5 32220 32221 /* RX_X4_ECC :: interrupt_status_2bit :: deskew_mem_1_2bit_int_status [04:04] */ 32222 #define RX_X4_ECC_INTERRUPT_STATUS_2BIT_DESKEW_MEM_1_2BIT_INT_STATUS_MASK 0x0010 32223 #define RX_X4_ECC_INTERRUPT_STATUS_2BIT_DESKEW_MEM_1_2BIT_INT_STATUS_ALIGN 0 32224 #define RX_X4_ECC_INTERRUPT_STATUS_2BIT_DESKEW_MEM_1_2BIT_INT_STATUS_BITS 1 32225 #define RX_X4_ECC_INTERRUPT_STATUS_2BIT_DESKEW_MEM_1_2BIT_INT_STATUS_SHIFT 4 32226 32227 /* RX_X4_ECC :: interrupt_status_2bit :: deskew_mem_0_2bit_int_status [03:03] */ 32228 #define RX_X4_ECC_INTERRUPT_STATUS_2BIT_DESKEW_MEM_0_2BIT_INT_STATUS_MASK 0x0008 32229 #define RX_X4_ECC_INTERRUPT_STATUS_2BIT_DESKEW_MEM_0_2BIT_INT_STATUS_ALIGN 0 32230 #define RX_X4_ECC_INTERRUPT_STATUS_2BIT_DESKEW_MEM_0_2BIT_INT_STATUS_BITS 1 32231 #define RX_X4_ECC_INTERRUPT_STATUS_2BIT_DESKEW_MEM_0_2BIT_INT_STATUS_SHIFT 3 32232 32233 /* RX_X4_ECC :: interrupt_status_2bit :: cl91_buffer_blk2_2bit_int_status [02:02] */ 32234 #define RX_X4_ECC_INTERRUPT_STATUS_2BIT_CL91_BUFFER_BLK2_2BIT_INT_STATUS_MASK 0x0004 32235 #define RX_X4_ECC_INTERRUPT_STATUS_2BIT_CL91_BUFFER_BLK2_2BIT_INT_STATUS_ALIGN 0 32236 #define RX_X4_ECC_INTERRUPT_STATUS_2BIT_CL91_BUFFER_BLK2_2BIT_INT_STATUS_BITS 1 32237 #define RX_X4_ECC_INTERRUPT_STATUS_2BIT_CL91_BUFFER_BLK2_2BIT_INT_STATUS_SHIFT 2 32238 32239 /* RX_X4_ECC :: interrupt_status_2bit :: cl91_buffer_blk1_2bit_int_status [01:01] */ 32240 #define RX_X4_ECC_INTERRUPT_STATUS_2BIT_CL91_BUFFER_BLK1_2BIT_INT_STATUS_MASK 0x0002 32241 #define RX_X4_ECC_INTERRUPT_STATUS_2BIT_CL91_BUFFER_BLK1_2BIT_INT_STATUS_ALIGN 0 32242 #define RX_X4_ECC_INTERRUPT_STATUS_2BIT_CL91_BUFFER_BLK1_2BIT_INT_STATUS_BITS 1 32243 #define RX_X4_ECC_INTERRUPT_STATUS_2BIT_CL91_BUFFER_BLK1_2BIT_INT_STATUS_SHIFT 1 32244 32245 /* RX_X4_ECC :: interrupt_status_2bit :: cl91_buffer_blk0_2bit_int_status [00:00] */ 32246 #define RX_X4_ECC_INTERRUPT_STATUS_2BIT_CL91_BUFFER_BLK0_2BIT_INT_STATUS_MASK 0x0001 32247 #define RX_X4_ECC_INTERRUPT_STATUS_2BIT_CL91_BUFFER_BLK0_2BIT_INT_STATUS_ALIGN 0 32248 #define RX_X4_ECC_INTERRUPT_STATUS_2BIT_CL91_BUFFER_BLK0_2BIT_INT_STATUS_BITS 1 32249 #define RX_X4_ECC_INTERRUPT_STATUS_2BIT_CL91_BUFFER_BLK0_2BIT_INT_STATUS_SHIFT 0 32250 32251 32252 /**************************************************************************** 32253 * RX_X4_ECC :: interrupt_en_1bit 32254 */ 32255 /* RX_X4_ECC :: interrupt_en_1bit :: reserved0 [15:06] */ 32256 #define RX_X4_ECC_INTERRUPT_EN_1BIT_RESERVED0_MASK 0xffc0 32257 #define RX_X4_ECC_INTERRUPT_EN_1BIT_RESERVED0_ALIGN 0 32258 #define RX_X4_ECC_INTERRUPT_EN_1BIT_RESERVED0_BITS 10 32259 #define RX_X4_ECC_INTERRUPT_EN_1BIT_RESERVED0_SHIFT 6 32260 32261 /* RX_X4_ECC :: interrupt_en_1bit :: deskew_mem_2_1bit_int_en [05:05] */ 32262 #define RX_X4_ECC_INTERRUPT_EN_1BIT_DESKEW_MEM_2_1BIT_INT_EN_MASK 0x0020 32263 #define RX_X4_ECC_INTERRUPT_EN_1BIT_DESKEW_MEM_2_1BIT_INT_EN_ALIGN 0 32264 #define RX_X4_ECC_INTERRUPT_EN_1BIT_DESKEW_MEM_2_1BIT_INT_EN_BITS 1 32265 #define RX_X4_ECC_INTERRUPT_EN_1BIT_DESKEW_MEM_2_1BIT_INT_EN_SHIFT 5 32266 32267 /* RX_X4_ECC :: interrupt_en_1bit :: deskew_mem_1_1bit_int_en [04:04] */ 32268 #define RX_X4_ECC_INTERRUPT_EN_1BIT_DESKEW_MEM_1_1BIT_INT_EN_MASK 0x0010 32269 #define RX_X4_ECC_INTERRUPT_EN_1BIT_DESKEW_MEM_1_1BIT_INT_EN_ALIGN 0 32270 #define RX_X4_ECC_INTERRUPT_EN_1BIT_DESKEW_MEM_1_1BIT_INT_EN_BITS 1 32271 #define RX_X4_ECC_INTERRUPT_EN_1BIT_DESKEW_MEM_1_1BIT_INT_EN_SHIFT 4 32272 32273 /* RX_X4_ECC :: interrupt_en_1bit :: deskew_mem_0_1bit_int_en [03:03] */ 32274 #define RX_X4_ECC_INTERRUPT_EN_1BIT_DESKEW_MEM_0_1BIT_INT_EN_MASK 0x0008 32275 #define RX_X4_ECC_INTERRUPT_EN_1BIT_DESKEW_MEM_0_1BIT_INT_EN_ALIGN 0 32276 #define RX_X4_ECC_INTERRUPT_EN_1BIT_DESKEW_MEM_0_1BIT_INT_EN_BITS 1 32277 #define RX_X4_ECC_INTERRUPT_EN_1BIT_DESKEW_MEM_0_1BIT_INT_EN_SHIFT 3 32278 32279 /* RX_X4_ECC :: interrupt_en_1bit :: cl91_buffer_blk2_1bit_int_en [02:02] */ 32280 #define RX_X4_ECC_INTERRUPT_EN_1BIT_CL91_BUFFER_BLK2_1BIT_INT_EN_MASK 0x0004 32281 #define RX_X4_ECC_INTERRUPT_EN_1BIT_CL91_BUFFER_BLK2_1BIT_INT_EN_ALIGN 0 32282 #define RX_X4_ECC_INTERRUPT_EN_1BIT_CL91_BUFFER_BLK2_1BIT_INT_EN_BITS 1 32283 #define RX_X4_ECC_INTERRUPT_EN_1BIT_CL91_BUFFER_BLK2_1BIT_INT_EN_SHIFT 2 32284 32285 /* RX_X4_ECC :: interrupt_en_1bit :: cl91_buffer_blk1_1bit_int_en [01:01] */ 32286 #define RX_X4_ECC_INTERRUPT_EN_1BIT_CL91_BUFFER_BLK1_1BIT_INT_EN_MASK 0x0002 32287 #define RX_X4_ECC_INTERRUPT_EN_1BIT_CL91_BUFFER_BLK1_1BIT_INT_EN_ALIGN 0 32288 #define RX_X4_ECC_INTERRUPT_EN_1BIT_CL91_BUFFER_BLK1_1BIT_INT_EN_BITS 1 32289 #define RX_X4_ECC_INTERRUPT_EN_1BIT_CL91_BUFFER_BLK1_1BIT_INT_EN_SHIFT 1 32290 32291 /* RX_X4_ECC :: interrupt_en_1bit :: cl91_buffer_blk0_1bit_int_en [00:00] */ 32292 #define RX_X4_ECC_INTERRUPT_EN_1BIT_CL91_BUFFER_BLK0_1BIT_INT_EN_MASK 0x0001 32293 #define RX_X4_ECC_INTERRUPT_EN_1BIT_CL91_BUFFER_BLK0_1BIT_INT_EN_ALIGN 0 32294 #define RX_X4_ECC_INTERRUPT_EN_1BIT_CL91_BUFFER_BLK0_1BIT_INT_EN_BITS 1 32295 #define RX_X4_ECC_INTERRUPT_EN_1BIT_CL91_BUFFER_BLK0_1BIT_INT_EN_SHIFT 0 32296 32297 32298 /**************************************************************************** 32299 * RX_X4_ECC :: interrupt_en_2bit 32300 */ 32301 /* RX_X4_ECC :: interrupt_en_2bit :: reserved0 [15:06] */ 32302 #define RX_X4_ECC_INTERRUPT_EN_2BIT_RESERVED0_MASK 0xffc0 32303 #define RX_X4_ECC_INTERRUPT_EN_2BIT_RESERVED0_ALIGN 0 32304 #define RX_X4_ECC_INTERRUPT_EN_2BIT_RESERVED0_BITS 10 32305 #define RX_X4_ECC_INTERRUPT_EN_2BIT_RESERVED0_SHIFT 6 32306 32307 /* RX_X4_ECC :: interrupt_en_2bit :: deskew_mem_2_2bit_int_en [05:05] */ 32308 #define RX_X4_ECC_INTERRUPT_EN_2BIT_DESKEW_MEM_2_2BIT_INT_EN_MASK 0x0020 32309 #define RX_X4_ECC_INTERRUPT_EN_2BIT_DESKEW_MEM_2_2BIT_INT_EN_ALIGN 0 32310 #define RX_X4_ECC_INTERRUPT_EN_2BIT_DESKEW_MEM_2_2BIT_INT_EN_BITS 1 32311 #define RX_X4_ECC_INTERRUPT_EN_2BIT_DESKEW_MEM_2_2BIT_INT_EN_SHIFT 5 32312 32313 /* RX_X4_ECC :: interrupt_en_2bit :: deskew_mem_1_2bit_int_en [04:04] */ 32314 #define RX_X4_ECC_INTERRUPT_EN_2BIT_DESKEW_MEM_1_2BIT_INT_EN_MASK 0x0010 32315 #define RX_X4_ECC_INTERRUPT_EN_2BIT_DESKEW_MEM_1_2BIT_INT_EN_ALIGN 0 32316 #define RX_X4_ECC_INTERRUPT_EN_2BIT_DESKEW_MEM_1_2BIT_INT_EN_BITS 1 32317 #define RX_X4_ECC_INTERRUPT_EN_2BIT_DESKEW_MEM_1_2BIT_INT_EN_SHIFT 4 32318 32319 /* RX_X4_ECC :: interrupt_en_2bit :: deskew_mem_0_2bit_int_en [03:03] */ 32320 #define RX_X4_ECC_INTERRUPT_EN_2BIT_DESKEW_MEM_0_2BIT_INT_EN_MASK 0x0008 32321 #define RX_X4_ECC_INTERRUPT_EN_2BIT_DESKEW_MEM_0_2BIT_INT_EN_ALIGN 0 32322 #define RX_X4_ECC_INTERRUPT_EN_2BIT_DESKEW_MEM_0_2BIT_INT_EN_BITS 1 32323 #define RX_X4_ECC_INTERRUPT_EN_2BIT_DESKEW_MEM_0_2BIT_INT_EN_SHIFT 3 32324 32325 /* RX_X4_ECC :: interrupt_en_2bit :: cl91_buffer_blk2_2bit_int_en [02:02] */ 32326 #define RX_X4_ECC_INTERRUPT_EN_2BIT_CL91_BUFFER_BLK2_2BIT_INT_EN_MASK 0x0004 32327 #define RX_X4_ECC_INTERRUPT_EN_2BIT_CL91_BUFFER_BLK2_2BIT_INT_EN_ALIGN 0 32328 #define RX_X4_ECC_INTERRUPT_EN_2BIT_CL91_BUFFER_BLK2_2BIT_INT_EN_BITS 1 32329 #define RX_X4_ECC_INTERRUPT_EN_2BIT_CL91_BUFFER_BLK2_2BIT_INT_EN_SHIFT 2 32330 32331 /* RX_X4_ECC :: interrupt_en_2bit :: cl91_buffer_blk1_2bit_int_en [01:01] */ 32332 #define RX_X4_ECC_INTERRUPT_EN_2BIT_CL91_BUFFER_BLK1_2BIT_INT_EN_MASK 0x0002 32333 #define RX_X4_ECC_INTERRUPT_EN_2BIT_CL91_BUFFER_BLK1_2BIT_INT_EN_ALIGN 0 32334 #define RX_X4_ECC_INTERRUPT_EN_2BIT_CL91_BUFFER_BLK1_2BIT_INT_EN_BITS 1 32335 #define RX_X4_ECC_INTERRUPT_EN_2BIT_CL91_BUFFER_BLK1_2BIT_INT_EN_SHIFT 1 32336 32337 /* RX_X4_ECC :: interrupt_en_2bit :: cl91_buffer_blk0_2bit_int_en [00:00] */ 32338 #define RX_X4_ECC_INTERRUPT_EN_2BIT_CL91_BUFFER_BLK0_2BIT_INT_EN_MASK 0x0001 32339 #define RX_X4_ECC_INTERRUPT_EN_2BIT_CL91_BUFFER_BLK0_2BIT_INT_EN_ALIGN 0 32340 #define RX_X4_ECC_INTERRUPT_EN_2BIT_CL91_BUFFER_BLK0_2BIT_INT_EN_BITS 1 32341 #define RX_X4_ECC_INTERRUPT_EN_2BIT_CL91_BUFFER_BLK0_2BIT_INT_EN_SHIFT 0 32342 32343 32344 /**************************************************************************** 32345 * RX_X4_ECC :: disable_ecc_mem 32346 */ 32347 /* RX_X4_ECC :: disable_ecc_mem :: reserved0 [15:06] */ 32348 #define RX_X4_ECC_DISABLE_ECC_MEM_RESERVED0_MASK 0xffc0 32349 #define RX_X4_ECC_DISABLE_ECC_MEM_RESERVED0_ALIGN 0 32350 #define RX_X4_ECC_DISABLE_ECC_MEM_RESERVED0_BITS 10 32351 #define RX_X4_ECC_DISABLE_ECC_MEM_RESERVED0_SHIFT 6 32352 32353 /* RX_X4_ECC :: disable_ecc_mem :: disable_ecc_deskew_mem_2 [05:05] */ 32354 #define RX_X4_ECC_DISABLE_ECC_MEM_DISABLE_ECC_DESKEW_MEM_2_MASK 0x0020 32355 #define RX_X4_ECC_DISABLE_ECC_MEM_DISABLE_ECC_DESKEW_MEM_2_ALIGN 0 32356 #define RX_X4_ECC_DISABLE_ECC_MEM_DISABLE_ECC_DESKEW_MEM_2_BITS 1 32357 #define RX_X4_ECC_DISABLE_ECC_MEM_DISABLE_ECC_DESKEW_MEM_2_SHIFT 5 32358 32359 /* RX_X4_ECC :: disable_ecc_mem :: disable_ecc_deskew_mem_1 [04:04] */ 32360 #define RX_X4_ECC_DISABLE_ECC_MEM_DISABLE_ECC_DESKEW_MEM_1_MASK 0x0010 32361 #define RX_X4_ECC_DISABLE_ECC_MEM_DISABLE_ECC_DESKEW_MEM_1_ALIGN 0 32362 #define RX_X4_ECC_DISABLE_ECC_MEM_DISABLE_ECC_DESKEW_MEM_1_BITS 1 32363 #define RX_X4_ECC_DISABLE_ECC_MEM_DISABLE_ECC_DESKEW_MEM_1_SHIFT 4 32364 32365 /* RX_X4_ECC :: disable_ecc_mem :: disable_ecc_deskew_mem_0 [03:03] */ 32366 #define RX_X4_ECC_DISABLE_ECC_MEM_DISABLE_ECC_DESKEW_MEM_0_MASK 0x0008 32367 #define RX_X4_ECC_DISABLE_ECC_MEM_DISABLE_ECC_DESKEW_MEM_0_ALIGN 0 32368 #define RX_X4_ECC_DISABLE_ECC_MEM_DISABLE_ECC_DESKEW_MEM_0_BITS 1 32369 #define RX_X4_ECC_DISABLE_ECC_MEM_DISABLE_ECC_DESKEW_MEM_0_SHIFT 3 32370 32371 /* RX_X4_ECC :: disable_ecc_mem :: disable_ecc_cl91_buffer_blk2 [02:02] */ 32372 #define RX_X4_ECC_DISABLE_ECC_MEM_DISABLE_ECC_CL91_BUFFER_BLK2_MASK 0x0004 32373 #define RX_X4_ECC_DISABLE_ECC_MEM_DISABLE_ECC_CL91_BUFFER_BLK2_ALIGN 0 32374 #define RX_X4_ECC_DISABLE_ECC_MEM_DISABLE_ECC_CL91_BUFFER_BLK2_BITS 1 32375 #define RX_X4_ECC_DISABLE_ECC_MEM_DISABLE_ECC_CL91_BUFFER_BLK2_SHIFT 2 32376 32377 /* RX_X4_ECC :: disable_ecc_mem :: disable_ecc_cl91_buffer_blk1 [01:01] */ 32378 #define RX_X4_ECC_DISABLE_ECC_MEM_DISABLE_ECC_CL91_BUFFER_BLK1_MASK 0x0002 32379 #define RX_X4_ECC_DISABLE_ECC_MEM_DISABLE_ECC_CL91_BUFFER_BLK1_ALIGN 0 32380 #define RX_X4_ECC_DISABLE_ECC_MEM_DISABLE_ECC_CL91_BUFFER_BLK1_BITS 1 32381 #define RX_X4_ECC_DISABLE_ECC_MEM_DISABLE_ECC_CL91_BUFFER_BLK1_SHIFT 1 32382 32383 /* RX_X4_ECC :: disable_ecc_mem :: disable_ecc_cl91_buffer_blk0 [00:00] */ 32384 #define RX_X4_ECC_DISABLE_ECC_MEM_DISABLE_ECC_CL91_BUFFER_BLK0_MASK 0x0001 32385 #define RX_X4_ECC_DISABLE_ECC_MEM_DISABLE_ECC_CL91_BUFFER_BLK0_ALIGN 0 32386 #define RX_X4_ECC_DISABLE_ECC_MEM_DISABLE_ECC_CL91_BUFFER_BLK0_BITS 1 32387 #define RX_X4_ECC_DISABLE_ECC_MEM_DISABLE_ECC_CL91_BUFFER_BLK0_SHIFT 0 32388 32389 32390 /**************************************************************************** 32391 * RX_X4_ECC :: corrupt 32392 */ 32393 /* RX_X4_ECC :: corrupt :: reserved0 [15:12] */ 32394 #define RX_X4_ECC_CORRUPT_RESERVED0_MASK 0xf000 32395 #define RX_X4_ECC_CORRUPT_RESERVED0_ALIGN 0 32396 #define RX_X4_ECC_CORRUPT_RESERVED0_BITS 4 32397 #define RX_X4_ECC_CORRUPT_RESERVED0_SHIFT 12 32398 32399 /* RX_X4_ECC :: corrupt :: corrupt_ecc_deskew_mem_2 [11:10] */ 32400 #define RX_X4_ECC_CORRUPT_CORRUPT_ECC_DESKEW_MEM_2_MASK 0x0c00 32401 #define RX_X4_ECC_CORRUPT_CORRUPT_ECC_DESKEW_MEM_2_ALIGN 0 32402 #define RX_X4_ECC_CORRUPT_CORRUPT_ECC_DESKEW_MEM_2_BITS 2 32403 #define RX_X4_ECC_CORRUPT_CORRUPT_ECC_DESKEW_MEM_2_SHIFT 10 32404 32405 /* RX_X4_ECC :: corrupt :: corrupt_ecc_deskew_mem_1 [09:08] */ 32406 #define RX_X4_ECC_CORRUPT_CORRUPT_ECC_DESKEW_MEM_1_MASK 0x0300 32407 #define RX_X4_ECC_CORRUPT_CORRUPT_ECC_DESKEW_MEM_1_ALIGN 0 32408 #define RX_X4_ECC_CORRUPT_CORRUPT_ECC_DESKEW_MEM_1_BITS 2 32409 #define RX_X4_ECC_CORRUPT_CORRUPT_ECC_DESKEW_MEM_1_SHIFT 8 32410 32411 /* RX_X4_ECC :: corrupt :: corrupt_ecc_deskew_mem_0 [07:06] */ 32412 #define RX_X4_ECC_CORRUPT_CORRUPT_ECC_DESKEW_MEM_0_MASK 0x00c0 32413 #define RX_X4_ECC_CORRUPT_CORRUPT_ECC_DESKEW_MEM_0_ALIGN 0 32414 #define RX_X4_ECC_CORRUPT_CORRUPT_ECC_DESKEW_MEM_0_BITS 2 32415 #define RX_X4_ECC_CORRUPT_CORRUPT_ECC_DESKEW_MEM_0_SHIFT 6 32416 32417 /* RX_X4_ECC :: corrupt :: corrupt_ecc_cl91_buffer_blk2 [05:04] */ 32418 #define RX_X4_ECC_CORRUPT_CORRUPT_ECC_CL91_BUFFER_BLK2_MASK 0x0030 32419 #define RX_X4_ECC_CORRUPT_CORRUPT_ECC_CL91_BUFFER_BLK2_ALIGN 0 32420 #define RX_X4_ECC_CORRUPT_CORRUPT_ECC_CL91_BUFFER_BLK2_BITS 2 32421 #define RX_X4_ECC_CORRUPT_CORRUPT_ECC_CL91_BUFFER_BLK2_SHIFT 4 32422 32423 /* RX_X4_ECC :: corrupt :: corrupt_ecc_cl91_buffer_blk1 [03:02] */ 32424 #define RX_X4_ECC_CORRUPT_CORRUPT_ECC_CL91_BUFFER_BLK1_MASK 0x000c 32425 #define RX_X4_ECC_CORRUPT_CORRUPT_ECC_CL91_BUFFER_BLK1_ALIGN 0 32426 #define RX_X4_ECC_CORRUPT_CORRUPT_ECC_CL91_BUFFER_BLK1_BITS 2 32427 #define RX_X4_ECC_CORRUPT_CORRUPT_ECC_CL91_BUFFER_BLK1_SHIFT 2 32428 32429 /* RX_X4_ECC :: corrupt :: corrupt_ecc_cl91_buffer_blk0 [01:00] */ 32430 #define RX_X4_ECC_CORRUPT_CORRUPT_ECC_CL91_BUFFER_BLK0_MASK 0x0003 32431 #define RX_X4_ECC_CORRUPT_CORRUPT_ECC_CL91_BUFFER_BLK0_ALIGN 0 32432 #define RX_X4_ECC_CORRUPT_CORRUPT_ECC_CL91_BUFFER_BLK0_BITS 2 32433 #define RX_X4_ECC_CORRUPT_CORRUPT_ECC_CL91_BUFFER_BLK0_SHIFT 0 32434 32435 32436 /**************************************************************************** 32437 * Datatype Definitions. 32438 */ 32439 #endif /* #ifndef TEF_TMP__ */ 32440 32441 /* End of File */ 32442