tefmod16_enum_defines.c (17276B)
1 /*---------------------------------------------------------------------- 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * $Copyright: (c) 2014 Broadcom Corporation All Rights Reserved.$ 8 * Broadcom Corporation 9 * Proprietary and Confidential information 10 * All rights reserved 11 * This source file is the property of Broadcom Corporation, and 12 * may not be copied or distributed in any isomorphic form without the 13 * prior written consent of Broadcom Corporation. 14 *--------------------------------------------------------------------- 15 ############### THIS FILE IS AUTOMATICALLY GENERATED. ############### 16 ############### DO !! NOT !! MANUALLY EDIT THIS FILE. ############### 17 *--------------------------------------------------------------------- 18 * Description: This file contains enums, elems and doxyten comments 19 * needed for SerDes Configuration programs. 20 *--------------------------------------------------------------------- 21 * CVS INFORMATION: 22 * Please see inc/enum_desc.txt for CVS information. 23 *---------------------------------------------------------------------- 24 */ 25 26 /* This file is automatically generated. Do not modify it. Modify the 27 * inc/enum_desc.txt to change enums, elems, or comments. For issues about 28 * the process that creates this file contact the tefmod16 development team. 29 */ 30 31 #include "tefmod16_enum_defines.h" 32 33 char* e2s_tefmod16_lane_select_t [CNT_tefmod_lane_select_t] = { 34 "TEFMOD16_LANE_0_0_0_0" , 35 "TEFMOD16_LANE_0_0_0_1" , 36 "TEFMOD16_LANE_0_0_1_0" , 37 "TEFMOD16_LANE_0_0_1_1" , 38 "TEFMOD16_LANE_0_1_0_0" , 39 "TEFMOD16_LANE_0_1_0_1" , 40 "TEFMOD16_LANE_0_1_1_0" , 41 "TEFMOD16_LANE_0_1_1_1" , 42 "TEFMOD16_LANE_1_0_0_0" , 43 "TEFMOD16_LANE_1_0_0_1" , 44 "TEFMOD16_LANE_1_0_1_0" , 45 "TEFMOD16_LANE_1_0_1_1" , 46 "TEFMOD16_LANE_1_1_0_0" , 47 "TEFMOD16_LANE_1_1_0_1" , 48 "TEFMOD16_LANE_1_1_1_0" , 49 "TEFMOD16_LANE_1_1_1_1" , 50 "TEFMOD16_LANE_BCST" , 51 "TEFMOD16_LANE_ILLEGAL" 52 }; /* e2s_tefmod16_lane_select_t */ 53 54 int e2n_tefmod16_lane_select_t [CNT_tefmod_lane_select_t] = { 55 0 , 56 1 , 57 2 , 58 3 , 59 4 , 60 5 , 61 6 , 62 7 , 63 8 , 64 9 , 65 10 , 66 11 , 67 12 , 68 13 , 69 14 , 70 15 , 71 15 , 72 0 73 }; /* e2n_tefmod16_lane_select_t */ 74 75 char* e2s_tefmod16_spd_intfc_type_t [CNT_tefmod_spd_intfc_type_t] = { 76 "TEFMOD16_SPD_ZERO" , 77 "TEFMOD16_SPD_10_SGMII" , 78 "TEFMOD16_SPD_100_SGMII" , 79 "TEFMOD16_SPD_1000_SGMII" , 80 "TEFMOD16_SPD_2500" , 81 "TEFMOD16_SPD_10000_XFI" , 82 "TEFMOD16_SPD_10600_XFI_HG" , 83 "TEFMOD16_SPD_20000_XFI" , 84 "TEFMOD16_SPD_21200_XFI_HG" , 85 "TEFMOD16_SPD_25000_XFI" , 86 "TEFMOD16_SPD_26500_XFI_HG" , 87 "TEFMOD16_SPD_20G_MLD_X2" , 88 "TEFMOD16_SPD_21G_MLD_HG_X2" , 89 "TEFMOD16_SPD_40G_MLD_X2" , 90 "TEFMOD16_SPD_42G_MLD_HG_X2" , 91 "TEFMOD16_SPD_40G_MLD_X4" , 92 "TEFMOD16_SPD_42G_MLD_HG_X4" , 93 "TEFMOD16_SPD_50G_MLD_X2" , 94 "TEFMOD16_SPD_53G_MLD_HG_X2" , 95 "TEFMOD16_SPD_100G_MLD_X4" , 96 "TEFMOD16_SPD_106G_MLD_HG_X4" , 97 "TEFMOD16_SPD_10000_HI" , 98 "TEFMOD16_SPD_10000" , 99 "TEFMOD16_SPD_12000_HI" , 100 "TEFMOD16_SPD_13000" , 101 "TEFMOD16_SPD_15000" , 102 "TEFMOD16_SPD_16000" , 103 "TEFMOD16_SPD_20000" , 104 "TEFMOD16_SPD_20000_SCR" , 105 "TEFMOD16_SPD_21000" , 106 "TEFMOD16_SPD_25455" , 107 "TEFMOD16_SPD_31500" , 108 "TEFMOD16_SPD_40G_X4" , 109 "TEFMOD16_SPD_42G_X4" , 110 "TEFMOD16_SPD_40G_XLAUI" , 111 "TEFMOD16_SPD_42G_XLAUI" , 112 "TEFMOD16_SPD_10000_X2" , 113 "TEFMOD16_SPD_10000_HI_DXGXS" , 114 "TEFMOD16_SPD_10000_DXGXS" , 115 "TEFMOD16_SPD_10000_HI_DXGXS_SCR" , 116 "TEFMOD16_SPD_10000_DXGXS_SCR" , 117 "TEFMOD16_SPD_10500_HI_DXGXS" , 118 "TEFMOD16_SPD_12773_HI_DXGXS" , 119 "TEFMOD16_SPD_12773_DXGXS" , 120 "TEFMOD16_SPD_15750_HI_DXGXS" , 121 "TEFMOD16_SPD_20G_MLD_DXGXS" , 122 "TEFMOD16_SPD_21G_HI_MLD_DXGXS" , 123 "TEFMOD16_SPD_20G_DXGXS" , 124 "TEFMOD16_SPD_21G_HI_DXGXS" , 125 "TEFMOD16_SPD_100G_CR10" , 126 "TEFMOD16_SPD_120G_CR12" , 127 "TEFMOD16_SPD_10000_XFI_HG2" , 128 "TEFMOD16_SPD_50G_MLD_X4" , 129 "TEFMOD16_SPD_53G_MLD_HG_X4" , 130 "TEFMOD16_SPD_10000_XFI_CR1" , 131 "TEFMOD16_SPD_10600_XFI_HG_CR1" , 132 "TEFMOD16_SPD_CL73_20G" , 133 "TEFMOD16_SPD_CL73_25G" , 134 "TEFMOD16_SPD_1G_20G" , 135 "TEFMOD16_SPD_1G_25G" , 136 "TEFMOD16_SPD_ILLEGAL" 137 }; /* e2s_tefmod16_spd_intfc_type_t */ 138 139 int e2n_tefmod16_spd_intfc_type_t [CNT_tefmod_spd_intfc_type_t] = { 140 0 , 141 10 , 142 100 , 143 1000 , 144 2500 , 145 10000 , 146 10560 , 147 20000 , 148 21200 , 149 25000 , 150 26500 , 151 20000 , 152 21000 , 153 40000 , 154 42400 , 155 40000 , 156 42400 , 157 50000 , 158 53000 , 159 100000 , 160 106000 , 161 10000 , 162 10000 , 163 12000 , 164 13000 , 165 15000 , 166 16000 , 167 20000 , 168 20000 , 169 21000 , 170 25000 , 171 31500 , 172 40000 , 173 40000 , 174 40000 , 175 42000 , 176 10000 , 177 10000 , 178 10000 , 179 10000 , 180 10000 , 181 10500 , 182 12773 , 183 12773 , 184 15750 , 185 20000 , 186 20000 , 187 20000 , 188 21000 , 189 100000 , 190 120000 , 191 10000 , 192 50000 , 193 53000 , 194 54000 , 195 55000 , 196 56000 , 197 57000 , 198 58000 , 199 59000 , 200 0 201 }; /* e2n_tefmod16_spd_intfc_type_t */ 202 203 char* e2s_tefmod16_regacc_type_t [CNT_tefmod_regacc_type_t] = { 204 "TEFMOD16_REGACC_CL22" , 205 "TEFMOD16_REGACC_CL45" , 206 "TEFMOD16_REGACC_TOTSC" , 207 "TEFMOD16_REGACC_SBUS_FD" , 208 "TEFMOD16_REGACC_SBUS_BD" , 209 "TEFMOD16_REGACC_ILLEGAL" 210 }; /* e2s_tefmod16_regacc_type_t */ 211 212 char* e2s_tefmod16_port_type_t [CNT_tefmod_port_type_t] = { 213 "TEFMOD16_MULTI_PORT" , 214 "TEFMOD16_TRI1_PORT" , 215 "TEFMOD16_TRI2_PORT" , 216 "TEFMOD16_DXGXS" , 217 "TEFMOD16_SINGLE_PORT" , 218 "TEFMOD16_PORT_MODE_ILLEGAL" 219 }; /* e2s_tefmod16_port_type_t */ 220 221 char* e2s_tefmod16_sc_mode_type_t [CNT_tefmod_sc_mode_type_t] = { 222 "TEFMOD16_SC_MODE_HT_WITH_BASIC_OVERRIDE" , 223 "TEFMOD16_SC_MODE_HT_OVERRIDE" , 224 "TEFMOD16_SC_MODE_ST" , 225 "TEFMOD16_SC_MODE_ST_OVERRIDE" , 226 "TEFMOD16_SC_MODE_AN_CL37" , 227 "TEFMOD16_SC_MODE_AN_CL73" , 228 "TEFMOD16_SC_MODE_BYPASS" , 229 "TEFMOD16_SC_MODE_ILLEGAL" 230 }; /* e2s_tefmod16_sc_mode_type_t */ 231 232 char* e2s_tefmod16_diag_type_t [CNT_tefmod_diag_type_t] = { 233 "TEFMOD16_DIAG_GENERAL" , 234 "TEFMOD16_DIAG_TOPOLOGY" , 235 "TEFMOD16_DIAG_LINK" , 236 "TEFMOD16_DIAG_SPEED" , 237 "TEFMOD16_DIAG_ANEG" , 238 "TEFMOD16_DIAG_TFC" , 239 "TEFMOD16_DIAG_AN_TIMERS" , 240 "TEFMOD16_DIAG_STATE" , 241 "TEFMOD16_DIAG_DEBUG" , 242 "TEFMOD16_DIAG_IEEE" , 243 "TEFMOD16_DIAG_EEE" , 244 "TEFMOD16_DIAG_BER" , 245 "TEFMOD16_DIAG_CFG" , 246 "TEFMOD16_DIAG_CL72" , 247 "TEFMOD16_DIAG_DSC" , 248 "TEFMOD16_SERDES_DIAG" , 249 "TEFMOD16_DIAG_ALL" , 250 "TEFMOD16_DIAG_ILLEGAL" 251 }; /* e2s_tefmod16_diag_type_t */ 252 253 char* e2s_tefmod16_model_type_t [CNT_tefmod_model_type_t] = { 254 "TEFMOD16_WC" , 255 "TEFMOD16_WC_A0" , 256 "TEFMOD16_WC_A1" , 257 "TEFMOD16_WC_A2" , 258 "TEFMOD16_WC_B0" , 259 "TEFMOD16_WC_B1" , 260 "TEFMOD16_WC_B2" , 261 "TEFMOD16_WC_C0" , 262 "TEFMOD16_WC_C1" , 263 "TEFMOD16_WC_C2" , 264 "TEFMOD16_WC_D0" , 265 "TEFMOD16_WC_D1" , 266 "TEFMOD16_WC_D2" , 267 "TEFMOD16_XN" , 268 "TEFMOD16_WL" , 269 "TEFMOD16_WL_A0" , 270 "TEFMOD16_QS" , 271 "TEFMOD16_QS_A0" , 272 "TEFMOD16_QS_B0" , 273 "TEFMOD16_MODEL_TYPE_ILLEGAL" 274 }; /* e2s_tefmod16_model_type_t */ 275 276 char* e2s_tefmod16_an_type_t [CNT_tefmod_an_type_t] = { 277 "TEFMOD16_CL73", 278 "TEFMOD16_CL73_BAM", 279 "TEFMOD16_HPAM", 280 "TEFMOD16_MSA", 281 "TEFMOD16_CL73_MSA", 282 "TEFMOD16_AN_TYPE_ILLEGAL" 283 }; /* e2s_tefmod16_an_type_t */ 284 285 char* e2s_tefmod16_eye_direction_t [CNT_tefmod_eye_direction_t] = { 286 "TEFMOD16_EYE_VU" , 287 "TEFMOD16_EYE_VD" , 288 "TEFMOD16_EYE_HL" , 289 "TEFMOD16_EYE_HR" , 290 "TEFMOD16_EYE_ILLEGAL" 291 }; /* e2s_tefmod16_eye_direction_t */ 292 293 char* e2s_tefmod16_aspd_type_t [CNT_tefmod_aspd_type_t] = { 294 "TEFMOD16_ASPD_10M" , 295 "TEFMOD16_ASPD_100M" , 296 "TEFMOD16_ASPD_1000M" , 297 "TEFMOD16_ASPD_2p5G_X1" , 298 "TEFMOD16_ASPD_5G_X4" , 299 "TEFMOD16_ASPD_6G_X4" , 300 "TEFMOD16_ASPD_10G_X4" , 301 "TEFMOD16_ASPD_10G_CX4" , 302 "TEFMOD16_ASPD_12G_X4" , 303 "TEFMOD16_ASPD_12p5G_X4" , 304 "TEFMOD16_ASPD_13G_X4" , 305 "TEFMOD16_ASPD_15G_X4" , 306 "TEFMOD16_ASPD_16G_X4" , 307 "TEFMOD16_ASPD_1G_KX1" , 308 "TEFMOD16_ASPD_10G_KX4" , 309 "TEFMOD16_ASPD_10G_KR1" , 310 "TEFMOD16_ASPD_5G_X1" , 311 "TEFMOD16_ASPD_6p36G_X1" , 312 "TEFMOD16_ASPD_20G_CX4" , 313 "TEFMOD16_ASPD_21G_X4" , 314 "TEFMOD16_ASPD_25p45G_X4" , 315 "TEFMOD16_ASPD_10G_X2_NOSCRAMBLE" , 316 "TEFMOD16_ASPD_10G_CX2_NOSCRAMBLE" , 317 "TEFMOD16_ASPD_10p5G_X2" , 318 "TEFMOD16_ASPD_10p5G_CX2_NOSCRAMBLE" , 319 "TEFMOD16_ASPD_12p7G_X2" , 320 "TEFMOD16_ASPD_12p7G_CX2" , 321 "TEFMOD16_ASPD_10G_X1" , 322 "TEFMOD16_ASPD_40G_X4" , 323 "TEFMOD16_ASPD_20G_X2" , 324 "TEFMOD16_ASPD_20G_CX2" , 325 "TEFMOD16_ASPD_10G_SFI" , 326 "TEFMOD16_ASPD_31p5G_X4" , 327 "TEFMOD16_ASPD_32p7G_X4" , 328 "TEFMOD16_ASPD_20G_X4" , 329 "TEFMOD16_ASPD_10G_X2" , 330 "TEFMOD16_ASPD_10G_CX2" , 331 "TEFMOD16_ASPD_12G_SCO_R2" , 332 "TEFMOD16_ASPD_10G_SCO_X2" , 333 "TEFMOD16_ASPD_40G_KR4" , 334 "TEFMOD16_ASPD_40G_CR4" , 335 "TEFMOD16_ASPD_100G_CR10" , 336 "TEFMOD16_ASPD_5G_X2" , 337 "TEFMOD16_ASPD_15p75G_X2" , 338 "TEFMOD16_ASPD_2G_FC" , 339 "TEFMOD16_ASPD_4G_FC" , 340 "TEFMOD16_ASPD_8G_FC" , 341 "TEFMOD16_ASPD_10G_CX1" , 342 "TEFMOD16_ASPD_1G_CX1" , 343 "TEFMOD16_ASPD_20G_KR2" , 344 "TEFMOD16_ASPD_20G_CR2" , 345 "TEFMOD16_ASPD_TYPE_ILLEGAL" 346 }; /* e2s_tefmod16_aspd_type_t */ 347 348 int e2n_tefmod16_aspd_type_t [CNT_tefmod_aspd_type_t] = { 349 0x0 , 350 0x1 , 351 0x2 , 352 0x3 , 353 0x4 , 354 0x5 , 355 0x6 , 356 0x7 , 357 0x8 , 358 0x9 , 359 0xa , 360 0xb , 361 0xc , 362 0xd , 363 0xe , 364 0xf , 365 0x10 , 366 0x11 , 367 0x12 , 368 0x13 , 369 0x14 , 370 0x15 , 371 0x16 , 372 0x17 , 373 0x18 , 374 0x19 , 375 0x1a , 376 0x1b , 377 0x1c , 378 0x1d , 379 0x1e , 380 0x1f , 381 0x20 , 382 0x21 , 383 0x22 , 384 0x23 , 385 0x24 , 386 0x25 , 387 0x26 , 388 0x27 , 389 0x28 , 390 0x29 , 391 0x2a , 392 0x2c , 393 0x2e , 394 0x2f , 395 0x30 , 396 0x33 , 397 0x34 , 398 0x39 , 399 0x3a , 400 0xff 401 }; /* e2n_tefmod16_aspd_type_t */ 402 403 char* e2s_tefmod16_tech_ability_t [CNT_tefmod_tech_ability_t] = { 404 "TEFMOD16_ABILITY_1G" , 405 "TEFMOD16_ABILITY_10G_KR" , 406 "TEFMOD16_ABILITY_40G_KR4" , 407 "TEFMOD16_ABILITY_40G_CR4" , 408 "TEFMOD16_ABILITY_100G_CR10" , 409 "TEFMOD16_ABILITY_10G_HIGIG" , 410 "TEFMOD16_ABILITY_10G_CX4" , 411 "TEFMOD16_ABILITY_20G_X4" , 412 "TEFMOD16_ABILITY_40G" , 413 "TEFMOD16_ABILITY_25P455G" , 414 "TEFMOD16_ABILITY_21G_X4" , 415 "TEFMOD16_ABILITY_20G_X4S" , 416 "TEFMOD16_ABILITY_10G_DXGXS_HIGIG" , 417 "TEFMOD16_ABILITY_10G_DXGXS" , 418 "TEFMOD16_ABILITY_10P5G_DXGXS" , 419 "TEFMOD16_ABILITY_12P5_DXGXS" , 420 "TEFMOD16_ABILITY_20G_KR2_HIGIG" , 421 "TEFMOD16_ABILITY_20G_KR2" , 422 "TEFMOD16_ABILITY_20G_CR2" , 423 "TEFMOD16_ABILITY_15P75G_R2" , 424 "TEFMOD16_ABILITY_100G_KR4" , 425 "TEFMOD16_ABILITY_100G_CR4" , 426 "TEFMOD16_ABILITY_40G_KR2" , 427 "TEFMOD16_ABILITY_40G_CR2" , 428 "TEFMOD16_ABILITY_50G_KR2" , 429 "TEFMOD16_ABILITY_50G_CR2" , 430 "TEFMOD16_ABILITY_50G_KR4" , 431 "TEFMOD16_ABILITY_50G_CR4" , 432 "TEFMOD16_ABILITY_20G_KR1" , 433 "TEFMOD16_ABILITY_20G_CR1" , 434 "TEFMOD16_ABILITY_25G_KR1" , 435 "TEFMOD16_ABILITY_25G_CR1" , 436 "TEFMOD16_ABILITY_ILLEGAL" 437 }; /* e2s_tefmod16_tech_ability_t */ 438 439 int e2n_tefmod16_tech_ability_t [CNT_tefmod_tech_ability_t] = { 440 0x6 , 441 0x7 , 442 0x8 , 443 0x9 , 444 0xa , 445 0x103 , 446 0x104 , 447 0x10a , 448 0x305 , 449 0x308 , 450 0x309 , 451 0x400 , 452 0x401 , 453 0x402 , 454 0x403 , 455 0x404 , 456 0x405 , 457 0x406 , 458 0x406 , 459 0x407 , 460 0x408 , 461 0x409 , 462 0x40a , 463 0x500 , 464 0x501 , 465 0x502 , 466 0x503 , 467 0x504 , 468 0x505 , 469 0x506 , 470 0x507 , 471 0x508 , 472 0x999 473 }; /* e2n_tefmod16_tech_ability_t */ 474 475 char* e2s_tefmod16_cl37bam_ability_t [CNT_tefmod_cl37bam_ability_t] = { 476 "TEFMOD16_BAM37ABL_2P5G" , 477 "TEFMOD16_BAM37ABL_5G_X4" , 478 "TEFMOD16_BAM37ABL_6G_X4" , 479 "TEFMOD16_BAM37ABL_10G_HIGIG" , 480 "TEFMOD16_BAM37ABL_10G_CX4" , 481 "TEFMOD16_BAM37ABL_12G_X4" , 482 "TEFMOD16_BAM37ABL_12P5_X4" , 483 "TEFMOD16_BAM37ABL_13G_X4" , 484 "TEFMOD16_BAM37ABL_15G_X4" , 485 "TEFMOD16_BAM37ABL_16G_X4" , 486 "TEFMOD16_BAM37ABL_20G_X4_CX4" , 487 "TEFMOD16_BAM37ABL_20G_X4" , 488 "TEFMOD16_BAM37ABL_21G_X4" , 489 "TEFMOD16_BAM37ABL_25P455G" , 490 "TEFMOD16_BAM37ABL_31P5G" , 491 "TEFMOD16_BAM37ABL_32P7G" , 492 "TEFMOD16_BAM37ABL_40G" , 493 "TEFMOD16_BAM37ABL_10G_X2_CX4" , 494 "TEFMOD16_BAM37ABL_10G_DXGXS" , 495 "TEFMOD16_BAM37ABL_10P5G_DXGXS" , 496 "TEFMOD16_BAM37ABL_12P7_DXGXS" , 497 "TEFMOD16_BAM37ABL_15P75G_R2" , 498 "TEFMOD16_BAM37ABL_20G_X2_CX4" , 499 "TEFMOD16_BAM37ABL_20G_X2" , 500 "TEFMOD16_BAM37ABL_ILLEGAL" 501 }; /* e2s_tefmod16_cl37bam_ability_t */ 502 503 char* e2s_tefmod16_diag_an_type_t [CNT_tefmod_diag_an_type_t] = { 504 "TEFMOD16_DIAG_AN_DONE" , 505 "TEFMOD16_DIAG_AN_HCD" , 506 "TEFMOD16_DIAG_AN_TYPE_ILLEGAL" 507 }; /* e2s_tefmod16_diag_an_type_t */ 508 509 char* e2s_tefmod16_tier1_function_type_t [CNT_tefmod_tier1_function_type_t] = { 510 "PCS_BYPASS_CTL" , 511 "CREDIT_SET" , 512 "ENCODE_SET" , 513 "DECODE_SET" , 514 "CREDIT_CONTROL" , 515 "AFE_SPEED_UP_DSC_VGA" , 516 "TX_LANE_CONTROL" , 517 "RX_LANE_CONTROL" , 518 "TX_LANE_DISABLE" , 519 "POWER_CONTROL" , 520 "AUTONEG_SET" , 521 "AUTONEG_GET" , 522 "AUTONEG_CONTROL" , 523 "AUTONEG_PAGE_SET" , 524 "REG_READ" , 525 "REG_WRITE" , 526 "PRBS_CHECK" , 527 "CJPAT_CRPAT_CONTROL" , 528 "CJPAT_CRPAT_CHECK" , 529 "TEFMOD16_DIAG" , 530 "LANE_SWAP" , 531 "PARALLEL_DETECT_CONTROL" , 532 "CLAUSE_72_CONTROL" , 533 "PLL_SEQUENCER_CONTROL" , 534 "PLL_LOCK_WAIT" , 535 "DUPLEX_CONTROL" , 536 "REVID_READ" , 537 "BYPASS_SC" , 538 "SET_POLARITY" , 539 "SET_PORT_MODE" , 540 "SET_AN_PORT_MODE" , 541 "PRBS_CONTROL" , 542 "PRBS_MODE" , 543 "SOFT_RESET" , 544 "SET_SPD_INTF" , 545 "TX_BERT_CONTROL" , 546 "RX_LOOPBACK_CONTROL" , 547 "RX_PMD_LOOPBACK_CONTROL" , 548 "TX_LOOPBACK_CONTROL" , 549 "TX_PMD_LOOPBACK_CONTROL" , 550 "CORE_RESET" , 551 "REFCLK_SET" , 552 "WAIT_PMD_LOCK" , 553 "FIRMWARE_SET" , 554 "INIT_PCS_FALCON" , 555 "DISABLE_PCS_FALCON" , 556 "INIT_PMD_FALCON" , 557 "PMD_LANE_SWAP_TX" , 558 "PMD_LANE_SWAP" , 559 "PCS_LANE_SWAP" , 560 "SET_SC_SPEED" , 561 "CHECK_SC_STATS" , 562 "SET_OVERRIDE_0" , 563 "SET_OVERRIDE_1" , 564 "PMD_RESET_REMOVE" , 565 "PMD_RESET_BYPASS" , 566 "INIT_PCS_ILKN" , 567 "TOGGLE_SW_SPEED_CHANGE" , 568 "TIER1_FUNCTION_ILLEGAL" 569 }; /* e2s_tefmod16_tier1_function_type_t */ 570 571 char* e2s_tefmod16_fec_en_parm_t [CNT_tefmod_fec_en_parm_t] = { 572 "TEFMOD16_CL91_TX_EN_DIS" , 573 "TEFMOD16_CL91_RX_EN_DIS" , 574 "TEFMOD16_CL91_IND_ONLY_EN_DIS" , 575 "TEFMOD16_CL91_COR_ONLY_EN_DIS" , 576 "TEFMOD16_CL74_TX_EN_DIS" , 577 "TEFMOD16_CL74_RX_EN_DIS" , 578 "TEFMOD16_CL74_CL91_EN_DIS" 579 }; /* e2s_tefmod16_fec_en_parm_t */ 580 581 char* e2s_tefmod16_fec_type_t [CNT_tefmod_fec_type_t] = { 582 "TEFMOD16_CL74" , 583 "TEFMOD16_CL91" , 584 "TEFMOD16_CL108" 585 }; /* e2s_tefmod16_fec_type_t */ 586 587 588 char* e2s_tefmod16_tx_disable_enum_t [CNT_tefmod_tx_disable_enum_t] = { 589 "TEFMOD16_TX_LANE_TRAFFIC" , 590 "TEFMOD16_TX_LANE_RESET" 591 }; /* e2s_tefmod16_tx_disable_enum_t */ 592 593 char* e2s_tefmod16_os_mode_type [CNT_tefmod_os_mode_type] = { 594 "TEFMOD16_PMA_OS_MODE_1" , 595 "TEFMOD16_PMA_OS_MODE_2" , 596 "TEFMOD16_PMA_OS_MODE_4" , 597 "TEFMOD16_PMA_OS_MODE_16_25" , 598 "TEFMOD16_PMA_OS_MODE_20_625" , 599 "TEFMOD16_PMA_OS_MODE_ILLEGAL" 600 }; /* e2s_tefmod16_os_mode_type */ 601 602 int e2n_tefmod16_os_mode_type [CNT_tefmod_os_mode_type] = { 603 1 , 604 2 , 605 4 , 606 16 , 607 10 , 608 0 609 }; /* e2n_tefmod16_os_mode_type */ 610 611 char* e2s_tefmod16_scr_mode [CNT_tefmod_scr_mode] = { 612 "TEFMOD16_SCR_MODE_BYPASS" , 613 "TEFMOD16_SCR_MODE_CL49" , 614 "TEFMOD16_SCR_MODE_40G_2_LANE" , 615 "TEFMOD16_SCR_MODE_100G" , 616 "TEFMOD16_SCR_MODE_20G" , 617 "TEFMOD16_SCR_MODE_40G_4_LANE" , 618 "TEFMOD16_SCR_MODE_ILLEGAL" 619 }; /* e2s_tefmod16_scr_mode */ 620 621 int e2n_tefmod16_scr_mode [CNT_tefmod_scr_mode] = { 622 0 , 623 1 , 624 2 , 625 3 , 626 4 , 627 5 , 628 0 629 }; /* e2n_tefmod16_scr_mode */ 630 631 char* e2s_tefmod16_encode_mode [CNT_tefmod_encode_mode] = { 632 "TEFMOD16_ENCODE_MODE_NONE" , 633 "TEFMOD16_ENCODE_MODE_CL49" , 634 "TEFMOD16_ENCODE_MODE_CL82" , 635 "TEFMOD16_ENCODE_MODE_ILLEGAL" 636 }; /* e2s_tefmod16_encode_mode */ 637 638 int e2n_tefmod16_encode_mode [CNT_tefmod_encode_mode] = { 639 0 , 640 1 , 641 2 , 642 15 643 }; /* e2n_tefmod16_encode_mode */ 644 645 char* e2s_tefmod16_descrambler_mode [CNT_tefmod_descrambler_mode] = { 646 "TEFMOD16_R_DESCR_MODE_BYPASS" , 647 "TEFMOD16_R_DESCR_MODE_CL49" , 648 "TEFMOD16_R_DESCR_MODE_CL82" , 649 "TEFMOD16_R_DESCR_MODE_ILLEGAL" 650 }; /* e2s_tefmod16_descrambler_mode */ 651 652 char* e2s_tefmod16_dec_tl_mode [CNT_tefmod_dec_tl_mode] = { 653 "TEFMOD16_DEC_TL_MODE_NONE" , 654 "TEFMOD16_DEC_TL_MODE_CL49" , 655 "TEFMOD16_DEC_TL_MODE_CL82" , 656 "TEFMOD16_DEC_TL_MODE_ILLEGAL" 657 }; /* e2s_tefmod16_dec_tl_mode */ 658 659 char* e2s_tefmod16_dec_fsm_mode [CNT_tefmod_dec_fsm_mode] = { 660 "TEFMOD16_DEC_FSM_MODE_NONE" , 661 "TEFMOD16_DEC_FSM_MODE_CL49" , 662 "TEFMOD16_DEC_FSM_MODE_CL82" , 663 "TEFMOD16_DEC_FSM_MODE_ILLEGAL" 664 }; /* e2s_tefmod16_dec_fsm_mode */ 665 666 char* e2s_tefmod16_deskew_mode [CNT_tefmod_deskew_mode] = { 667 "TEFMOD16_R_DESKEW_MODE_BYPASS" , 668 "TEFMOD16_R_DESKEW_MODE_10G" , 669 "TEFMOD16_R_DESKEW_MODE_40G_4_LANE" , 670 "TEFMOD16_R_DESKEW_MODE_40G_2_LANE" , 671 "TEFMOD16_R_DESKEW_MODE_100G" , 672 "TEFMOD16_R_DESKEW_MODE_CL49" , 673 "TEFMOD16_R_DESKEW_MODE_CL91" , 674 "TEFMOD16_R_DESKEW_MODE_ILLEGAL" 675 }; /* e2s_tefmod16_deskew_mode */ 676 677 char* e2s_tefmod16_t_fifo_mode [CNT_tefmod_t_fifo_mode] = { 678 "TEFMOD16_T_FIFO_MODE_NONE" , 679 "TEFMOD16_T_FIFO_MODE_40G" , 680 "TEFMOD16_T_FIFO_MODE_100G" , 681 "TEFMOD16_T_FIFO_MODE_20G" , 682 "TEFMOD16_T_FIFO_MODE_ILLEGAL" 683 }; /* e2s_tefmod16_t_fifo_mode */ 684 685 char* e2s_tefmod16_bs_btmx_mode [CNT_tefmod_bs_btmx_mode] = { 686 "TEFMOD16_BS_BTMX_MODE_NONE" , 687 "TEFMOD16_BS_BTMX_MODE_1to1" , 688 "TEFMOD16_BS_BTMX_MODE_2to1" , 689 "TEFMOD16_BS_BTMX_MODE_5to1" , 690 "TEFMOD16_BS_BTMX_MODE_ILLEGAL" 691 }; /* e2s_tefmod16_bs_btmx_mode */ 692 693 char* e2s_tefmod16_bs_dist_mode [CNT_tefmod_bs_dist_mode] = { 694 "TEFMOD16_BS_DIST_MODE_5_LANE_TDM" , 695 "TEFMOD16_BS_DIST_MODE_2_LANE_TDM_2_VLANE" , 696 "TEFMOD16_BS_DIST_MODE_2_LANE_TDM_1_VLANE" , 697 "TEFMOD16_BS_DIST_MODE_NO_TDM" , 698 "TEFMOD16_BS_DIST_MODE_ILLEGAL" 699 }; /* e2s_tefmod16_bs_dist_mode */ 700