tefmod16_diagnostics.c (35649B)
1 /*---------------------------------------------------------------------- 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * $Copyright: (c) 2014 Broadcom Corporation All Rights Reserved.$ 8 * Broadcom Corporation 9 * Proprietary and Confidential information 10 * Copyright: (c) 2012 Broadcom Corp. 11 * All rights reserved 12 * This source file is the property of Broadcom Corporation, and 13 * may not be copied or distributed in any isomorphic form without the 14 * prior written consent of Broadcom Corporation. 15 *--------------------------------------------------------------------- 16 * File : tefmod16_diagnostics.c 17 * Description: C sequences which utilize tier1s to build configurations 18 * which target only the diagnostic features of the Serdes 19 *-----------------------------------------------------------------------*/ 20 #ifndef _SDK_TEFMOD16_ 21 #ifndef _DV_TB_ 22 #define _SDK_TEFMOD16_ 1 23 #endif 24 #endif 25 26 #ifdef _DV_TB_ 27 #include "tefmod_main.h" 28 #include "tefmod_defines.h" 29 #include "tefmod_phyreg.h" 30 #include <math.h> 31 #endif 32 33 #ifdef _DV_TB_ 34 #include "bcmi_tscf_xgxs_defs.h" 35 #endif 36 37 #ifdef _SDK_TEFMOD16_ 38 #include <phymod/phymod_system.h> 39 #include <phymod/chip/bcmi_tscf_16nm_xgxs_defs.h> 40 #include "tefmod16_enum_defines.h" 41 #endif 42 43 #define _TRGO_(a,l) PHYMOD_DEBUG_ERROR(("<< PHY_TRG: Adr:%06d Ln:%02d\n",a,l)); 44 #define _TRGC_(a,l) PHYMOD_DEBUG_ERROR((">> PHY TRG: Adr:%06d Ln:%02d\n",a,l)); 45 #ifdef _SDK_TEFMOD16_ 46 #define PHYMOD_ST const phymod_access_t 47 #define _TRG_OPN(a) _TRGO_(a->addr, a->lane_mask) 48 #define _TRG_CLS(a) _TRGC_(a->addr, a->lane_mask) 49 #endif 50 #ifdef _DV_TB_ 51 #define PHYMOD_ST tefmod_st 52 #define _TRG_OPN(a) _TRGO_(a->prt_ad, a->this_lane) 53 #define _TRG_CLS(a) _TRGC_(a->prt_ad, a->this_lane) 54 #endif 55 56 extern int tefmod16_diag_st(PHYMOD_ST *pc, int resolved_speed); 57 58 /** 59 @brief Field OVR diagnostic function 60 @param pc handle to current TSCF context (#PHYMOD_ST) 61 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_ERROR else. 62 @details Field OVR Details 63 Check if the field OVR is set, and if OVR enabled, print the OVR value 64 */ 65 int tefmod16_diag_field_or(PHYMOD_ST *pc) 66 { 67 SC_X4_SC_X4_OVRRr_t num_lanes_or; 68 TX_X4_MISCr_t tx_misc_or; 69 TX_X4_ENC0r_t encode_or; 70 RX_X4_PCS_CTL0r_t rx_x4_pcs_ctrl_or; 71 TX_X4_CRED0r_t crd_or; 72 TX_X4_CRED1r_t crd1_or; 73 TX_X4_LOOPCNTr_t loopcnt_or; 74 TX_X4_MAC_CREDGENCNTr_t mac_cgc_or; 75 76 READ_SC_X4_SC_X4_OVRRr(pc,&num_lanes_or); 77 READ_RX_X4_PCS_CTL0r(pc,&rx_x4_pcs_ctrl_or); 78 READ_TX_X4_MISCr(pc,&tx_misc_or); 79 READ_TX_X4_ENC0r(pc,&encode_or); 80 READ_TX_X4_CRED0r(pc,&crd_or); 81 READ_TX_X4_CRED1r(pc,&crd1_or); 82 READ_TX_X4_LOOPCNTr(pc,&loopcnt_or); 83 READ_TX_X4_MAC_CREDGENCNTr(pc,&mac_cgc_or); 84 85 PHYMOD_DEBUG_ERROR(("| OEN SET OVR VALUE |\n")); 86 PHYMOD_DEBUG_ERROR(("+----------------+----------------+--------------------------------------------+\n")); 87 PHYMOD_DEBUG_ERROR(("| NUM LANES: 0x%X | FEC ENA: 0x%X | %-20s | %-20s |\n", 88 SC_X4_SC_X4_OVRRr_NUM_LANES_OVERRIDE_VALUEf_GET(num_lanes_or), 89 TX_X4_MISCr_FEC_ENABLEf_GET(tx_misc_or), 90 e2s_tefmod16_scr_mode[TX_X4_MISCr_SCR_MODEf_GET(tx_misc_or)]+9, 91 e2s_tefmod16_descrambler_mode[RX_X4_PCS_CTL0r_DESCR_MODEf_GET(rx_x4_pcs_ctrl_or)]+9)); 92 93 PHYMOD_DEBUG_ERROR(("| TXLN RSTB: 0x%X | TXLN ENA: 0x%X | %-20s | %-20s |\n", 94 TX_X4_MISCr_RSTB_TX_LANEf_GET(tx_misc_or), 95 TX_X4_MISCr_ENABLE_TX_LANEf_GET(tx_misc_or), 96 e2s_tefmod16_os_mode_type[TX_X4_MISCr_OS_MODEf_GET(tx_misc_or)]+9, 97 e2s_tefmod16_encode_mode[TX_X4_ENC0r_T_ENC_MODEf_GET(encode_or)]+9)); 98 99 PHYMOD_DEBUG_ERROR(("| CLKCNT0: 0x%x | CLKCNT1: 0x%X | LPCNT0: 0x%X | LPCNT1: 0x%X| %s |\n", 100 TX_X4_CRED0r_CLOCKCNT0f_GET(crd_or), 101 TX_X4_CRED1r_CLOCKCNT1f_GET(crd1_or), 102 TX_X4_LOOPCNTr_LOOPCNT0f_GET(loopcnt_or), 103 TX_X4_LOOPCNTr_LOOPCNT1f_GET(loopcnt_or), 104 e2s_tefmod16_dec_tl_mode[RX_X4_PCS_CTL0r_DEC_TL_MODEf_GET(rx_x4_pcs_ctrl_or)]+9)); 105 106 PHYMOD_DEBUG_ERROR(("| MACCRDGEN: 0x%x | CL74FECEN: %d | %-20s | %-20s | \n", 107 TX_X4_MAC_CREDGENCNTr_MAC_CREDITGENCNTf_GET(mac_cgc_or), 108 RX_X4_PCS_CTL0r_FEC_ENABLEf_GET(rx_x4_pcs_ctrl_or), 109 e2s_tefmod16_deskew_mode[RX_X4_PCS_CTL0r_DESKEW_MODEf_GET(rx_x4_pcs_ctrl_or)]+9, 110 e2s_tefmod16_dec_fsm_mode[RX_X4_PCS_CTL0r_DEC_FSM_MODEf_GET(rx_x4_pcs_ctrl_or)]+9)); 111 112 113 PHYMOD_DEBUG_ERROR(("+----------------+--+-------------+------+------------------+------------------+\n")); 114 115 return PHYMOD_E_NONE; 116 } 117 118 /** 119 @brief pmd pcs lane cfg diagnostic function 120 @param pc handle to current TSCF context (#PHYMOD_ST) 121 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_ERROR else. 122 @details Get the uc controls for pmd lane cfg 123 Read the pcs_lane_cfg information from uc RAM. To check if the pmd is to be 124 programmed from pcs lane cfg. 125 */ 126 int tefmod16_diag_pmd_pcs_lane_cfg(PHYMOD_ST *pc, int lane) 127 { 128 _TRG_OPN(pc); 129 _TRG_CLS(pc); 130 return PHYMOD_E_NONE; 131 } /* tefmod16_diag_pmd_pcs_lane_cfg */ 132 133 /** 134 @brief Speed diagnostic function 135 @param pc handle to current TSCF context (#PHYMOD_ST) 136 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_ERROR else. 137 @details Speed Details 138 1. Get the Speed set 139 2. Get the Speed valis and Speed Done Status 140 3. Get the final stats of the speed 141 */ 142 int tefmod16_diag_speed(PHYMOD_ST *pc) 143 { 144 SC_X4_STSr_t sc_ctrl_status; 145 SC_X4_RSLVD_SPDr_t sc_final_resolved_speed; 146 SC_X4_RSLVD0r_t sc_final_resolved_0; 147 SC_X4_RSLVD1r_t sc_final_resolved_1; 148 SC_X4_RSLVD2r_t sc_final_resolved_2; 149 SC_X4_RSLVD3r_t sc_final_resolved_3; 150 SC_X4_RSLVD4r_t sc_final_resolved_4; 151 MAIN0_SETUPr_t setup_reg; 152 PLL_CAL_CTL7r_t pll_div_reg; 153 154 PHYMOD_DEBUG_ERROR(("| SPEED |\n")); 155 PHYMOD_DEBUG_ERROR(("+---------------------+-----------------------------+-----------+--------------+\n")); 156 157 /*1. Get the Speed valid and Speed Done Status */ 158 READ_SC_X4_STSr(pc,&sc_ctrl_status); 159 160 /*2. Get the Speed set */ 161 /*2a PLLDIV and the refclk settings */ 162 READ_SC_X4_RSLVD_SPDr(pc,&sc_final_resolved_speed); 163 READ_MAIN0_SETUPr(pc,&setup_reg); 164 READ_PLL_CAL_CTL7r(pc,&pll_div_reg); 165 166 /*2b Check if the Speed id is existent in ST */ 167 tefmod16_diag_st(pc, 0); 168 tefmod16_diag_field_or(pc); 169 170 /*3. Get the final stats for the speed */ 171 READ_SC_X4_RSLVD0r(pc,&sc_final_resolved_0); 172 READ_SC_X4_RSLVD2r(pc,&sc_final_resolved_2); 173 174 175 READ_SC_X4_RSLVD1r(pc,&sc_final_resolved_1); 176 177 READ_SC_X4_RSLVD3r(pc,&sc_final_resolved_3); 178 READ_SC_X4_RSLVD4r(pc,&sc_final_resolved_4); 179 180 181 PHYMOD_DEBUG_ERROR(("| SPEED | STATS0 | STATS1 | CREDIT STATS |\n")); 182 PHYMOD_DEBUG_ERROR(("+-------------------+--------------------+------------------+------------------+\n")); 183 PHYMOD_DEBUG_ERROR(("| SPD CHG VLD: %-4d | OS_MODE: %-9s | DESCR_MODE: %s |\n", 184 SC_X4_STSr_SW_SPEED_CONFIG_VLDf_GET(sc_ctrl_status), 185 e2s_tefmod16_os_mode_type[SC_X4_RSLVD0r_OS_MODEf_GET(sc_final_resolved_0)]+16, 186 e2s_tefmod16_descrambler_mode[SC_X4_RSLVD1r_DESCR_MODEf_GET(sc_final_resolved_1)]+22)); 187 188 PHYMOD_DEBUG_ERROR(("| SPD CHG DONE: %-3d | SCR_MODE: %-8s | DECODE MODE: %-4s | CLK CNT0: %-5d |\n", 189 SC_X4_STSr_SW_SPEED_CHANGE_DONEf_GET(sc_ctrl_status), 190 e2s_tefmod16_scr_mode[SC_X4_RSLVD0r_SCR_MODEf_GET(sc_final_resolved_0)]+18, 191 e2s_tefmod16_dec_tl_mode[SC_X4_RSLVD1r_DEC_TL_MODEf_GET(sc_final_resolved_1)]+21, 192 SC_X4_RSLVD2r_CLOCKCNT0f_GET(sc_final_resolved_2))); 193 194 PHYMOD_DEBUG_ERROR(("| SPD RESOLVED: %-3d | ENC_MODE: %-8s | DESKEW_MODE: %-5s| CLK CNT1: %-5d |\n", 195 SC_X4_RSLVD_SPDr_SPEEDf_GET(sc_final_resolved_speed), 196 e2s_tefmod16_encode_mode[SC_X4_RSLVD0r_T_ENC_MODEf_GET(sc_final_resolved_0)]+21, 197 e2s_tefmod16_deskew_mode[SC_X4_RSLVD1r_DESKEW_MODEf_GET(sc_final_resolved_1)]+23, 198 SC_X4_RSLVD3r_CLOCKCNT1f_GET(sc_final_resolved_3))); 199 200 PHYMOD_DEBUG_ERROR(("| LN RESOLVED: %-4d | HG2 ENA : %-9d| DECFSM_MODE: %-5s| LP CNT0: %-6d |\n", 201 SC_X4_RSLVD_SPDr_NUM_LANESf_GET(sc_final_resolved_speed), 202 SC_X4_RSLVD0r_T_HG2_ENABLEf_GET(sc_final_resolved_0), 203 e2s_tefmod16_dec_fsm_mode[SC_X4_RSLVD1r_DEC_FSM_MODEf_GET(sc_final_resolved_1)]+22, 204 SC_X4_RSLVD4r_LOOPCNT0f_GET(sc_final_resolved_4))); 205 206 PHYMOD_DEBUG_ERROR(("| PLL DIV: %-8d | CL72 ENA : %-7d | REF CLOCK: %-6d | LP CNT1: %-6d |\n", 207 PLL_CAL_CTL7r_PLL_MODEf_GET(pll_div_reg), 208 SC_X4_RSLVD0r_CL72_ENf_GET(sc_final_resolved_0), 209 MAIN0_SETUPr_REFCLK_SELf_GET(setup_reg), 210 SC_X4_RSLVD4r_LOOPCNT1f_GET(sc_final_resolved_4))); 211 212 213 PHYMOD_DEBUG_ERROR(("+-------------------+--------------------+------------------+------------------+\n")); 214 215 return PHYMOD_E_NONE; 216 } 217 218 /** 219 @brief Autoneg diagnostic function 220 @param pc handle to current TSCF context (#PHYMOD_ST) 221 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_ERROR else. 222 @details Autoneg diags 223 1. Get the AN complete status for AN37/73 224 2. Get the resolved HCD 225 3. Get the link up status after AN 226 */ 227 int tefmod16_diag_autoneg(PHYMOD_ST *pc) 228 { 229 230 AN_X4_CL73_CFGr_t an_cfg; 231 AN_X4_LD_UP1_ABIL0r_t up1_abil0; 232 AN_X4_LD_UP1_ABIL1r_t up1_abil1; 233 AN_X4_LD_BASE_ABIL0r_t base_abil0; 234 AN_X4_LD_BASE_ABIL1r_t base_abil1; 235 AN_X4_LD_BAM_ABILr_t bam_abil; 236 AN_X4_CL73_CTLSr_t an_ctrl; 237 AN_X4_AN_MISC_STSr_t an_misc; 238 SC_X4_RSLVD_SPDr_t sc_spd; 239 AN_X4_LD_BASE_ABIL2r_t base_abil2; 240 AN_X4_LD_BASE_ABIL3r_t base_abil3; 241 AN_X4_LD_BASE_ABIL4r_t base_abil4; 242 uint8_t lane = 0; 243 244 READ_AN_X4_CL73_CFGr (pc, &an_cfg); 245 READ_AN_X4_LD_UP1_ABIL0r (pc, &up1_abil0); 246 READ_AN_X4_LD_UP1_ABIL1r (pc, &up1_abil1); 247 READ_AN_X4_LD_BASE_ABIL0r (pc, &base_abil0); 248 READ_AN_X4_LD_BASE_ABIL1r (pc, &base_abil1); 249 READ_AN_X4_LD_BAM_ABILr (pc, &bam_abil); 250 READ_AN_X4_CL73_CTLSr (pc, &an_ctrl); 251 READ_AN_X4_AN_MISC_STSr (pc, &an_misc); 252 READ_SC_X4_RSLVD_SPDr (pc, &sc_spd); 253 READ_AN_X4_LD_BASE_ABIL2r (pc, &base_abil2); 254 READ_AN_X4_LD_BASE_ABIL3r (pc, &base_abil3); 255 READ_AN_X4_LD_BASE_ABIL4r (pc, &base_abil4); 256 lane = AN_X4_CL73_CFGr_NUM_ADVERTISED_LANESf_GET(an_cfg); 257 258 PHYMOD_DEBUG_ERROR(("| AUTONEG |\n")); 259 PHYMOD_DEBUG_ERROR(("+-------------+-------------+------------------------------+-------------------+\n")); 260 PHYMOD_DEBUG_ERROR(("| AN 73: %c | AN 73 BAM: %c | AN 73 HPAM: %c |AN HCD SPD: 0x%x | NUM ADV LANE: %02d |\n", 261 (AN_X4_CL73_CFGr_CL73_ENABLEf_GET(an_cfg) == 1) ? 'Y' : 'N', 262 (AN_X4_CL73_CFGr_CL73_BAM_ENABLEf_GET(an_cfg) == 1) ? 'Y' : 'N', 263 (AN_X4_CL73_CFGr_CL73_HPAM_ENABLEf_GET(an_cfg) == 1) ? 'Y' : 'N', 264 SC_X4_RSLVD_SPDr_SPEEDf_GET(sc_spd), 265 ((lane == 0) ? 1 : (lane == 1) ? 2 : (lane == 2) ? 4 : 10))); 266 #if 0 267 PHYMOD_DEBUG_ERROR(("+-------------------+-------------------+--------------------------------------+\n")); 268 PHYMOD_DEBUG_ERROR(("| UP 0/1 ABILITIES | BASE 0/1/2/3 ABILITIES |\n")); 269 #endif 270 PHYMOD_DEBUG_ERROR(("+----------------+----------------+--------------------------------------------+\n")); 271 PHYMOD_DEBUG_ERROR(("| BAM 50G CR4: %d | BAM 50G KR4: %d | PAUSE: %d | RMT FLT: %d | NEXT PAGE: %d |\n", 272 AN_X4_LD_UP1_ABIL0r_BAM_50G_CR4f_GET(up1_abil0), 273 AN_X4_LD_UP1_ABIL0r_BAM_50G_KR4f_GET(up1_abil0), 274 AN_X4_LD_BASE_ABIL1r_CL73_PAUSEf_GET(base_abil1), 275 AN_X4_LD_BASE_ABIL1r_CL73_REMOTE_FAULTf_GET(base_abil1), 276 AN_X4_LD_BASE_ABIL1r_NEXT_PAGEf_GET(base_abil1))); 277 278 PHYMOD_DEBUG_ERROR(("| BAM 50G CR2: %d | BAM 50G KR2: %d | FEC : %d | BASE 1G KX1: %d | BASE 10G KR1: %d |\n", 279 AN_X4_LD_UP1_ABIL0r_BAM_50G_CR2f_GET(up1_abil0), 280 AN_X4_LD_UP1_ABIL0r_BAM_50G_KR2f_GET(up1_abil0), 281 AN_X4_LD_BASE_ABIL1r_FEC_REQf_GET(base_abil1), 282 AN_X4_LD_BASE_ABIL1r_BASE_1G_KX1f_GET(base_abil1), 283 AN_X4_LD_BASE_ABIL1r_BASE_10G_KR1f_GET(base_abil1))); 284 285 PHYMOD_DEBUG_ERROR(("| BAM 40G CR2: %d | BAM 40G KR2: %d | BASE 100G CR4: %d | BASE 40G CR4: %d |\n", 286 AN_X4_LD_UP1_ABIL0r_BAM_40G_CR2f_GET(up1_abil0), 287 AN_X4_LD_UP1_ABIL0r_BAM_40G_KR2f_GET(up1_abil0), 288 AN_X4_LD_BASE_ABIL1r_BASE_100G_CR4f_GET(base_abil1), 289 AN_X4_LD_BASE_ABIL1r_BASE_40G_CR4f_GET(base_abil1))); 290 291 PHYMOD_DEBUG_ERROR(("| BAM 20G CR2: %d | BAM 20G KR2: %d | BASE 100G KR4: %d | BASE 40G KR4: %d |\n", 292 AN_X4_LD_UP1_ABIL0r_BAM_20G_CR2f_GET(up1_abil0), 293 AN_X4_LD_UP1_ABIL0r_BAM_20G_KR2f_GET(up1_abil0), 294 AN_X4_LD_BASE_ABIL1r_BASE_100G_KR4f_GET(base_abil1), 295 AN_X4_LD_BASE_ABIL1r_BASE_40G_KR4f_GET(base_abil1))); 296 297 PHYMOD_DEBUG_ERROR(("| BAM 25G CR1: %d | BAM 25G KR1: %d | BASE 50G KR2: %d | BASE 50G CR2: %d |\n", 298 AN_X4_LD_UP1_ABIL1r_BAM_25G_CR1f_GET(up1_abil1), 299 AN_X4_LD_UP1_ABIL1r_BAM_25G_KR1f_GET(up1_abil1), 300 AN_X4_LD_BASE_ABIL2r_BASE_50G_KR2_ENf_GET(base_abil2), 301 AN_X4_LD_BASE_ABIL2r_BASE_50G_KR2_ENf_GET(base_abil2))); 302 303 PHYMOD_DEBUG_ERROR(("| BAM 20G CR1: %d | BAM 20G KR1: %d | BASE 25G KR1: %d |BASE 25G KRS1: %d |\n", 304 AN_X4_LD_UP1_ABIL1r_BAM_20G_CR1f_GET(up1_abil1), 305 AN_X4_LD_UP1_ABIL1r_BAM_20G_KR1f_GET(up1_abil1), 306 AN_X4_LD_BASE_ABIL3r_BASE_25G_KR1_ENf_GET(base_abil3), 307 AN_X4_LD_BASE_ABIL4r_BASE_25G_KRS1_SELf_GET(base_abil4))); 308 309 PHYMOD_DEBUG_ERROR(("| CL74_REQ: %d | CL91_REQ: %d | BAM HG2: %d | BASE 25G CR1: %d| BASE 25G CRS1: %d |\n", 310 AN_X4_LD_UP1_ABIL1r_CL74_REQf_GET(up1_abil1), 311 AN_X4_LD_UP1_ABIL1r_CL91_REQf_GET(up1_abil1), 312 AN_X4_LD_UP1_ABIL0r_BAM_HG2f_GET(up1_abil0), 313 AN_X4_LD_BASE_ABIL3r_BASE_25G_CR1_ENf_GET(base_abil3), 314 AN_X4_LD_BASE_ABIL4r_BASE_25G_CRS1_SELf_GET(base_abil4))); 315 316 PHYMOD_DEBUG_ERROR(("+-------------------+-------------------+--------------------------------------+\n")); 317 318 return PHYMOD_E_NONE; 319 } 320 321 /** 322 @brief Topology diagnostic function. 323 @param pc handle to current TSCF context (#PHYMOD_ST) 324 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_ERROR else. 325 @details Get the topology details 326 1. LoopBack 327 a. Remote Loopback - RX loopback 328 i. PCS loopback 329 ii. PMD loopback 330 b. Local loopback/gloop - TX loopback 331 i. PCS loopback 332 ii. PMD loopback 333 2. LaneSwap 334 a. PCS LaneSwap(RX) 335 b. PMD LaneSwap(TX) 336 3. Master PortNum, port mode and single port mode 337 338 */ 339 int tefmod16_diag_topology(PHYMOD_ST *pc) 340 { 341 MAIN0_LPBK_CTLr_t pcs_loopback_ctrl; 342 TLB_RX_DIG_LPBK_CFGr_t pmd_loopback_dig; 343 TLB_TX_RMT_LPBK_CFGr_t pmd_loopback_remote; 344 TX_X1_TX_LN_SWPr_t pcs_tx_lane_swap; 345 RX_X1_RX_LN_SWPr_t pcs_rx_lane_swap; 346 LN_ADDR0r_t ln_addr0; 347 LN_ADDR1r_t ln_addr1; 348 LN_ADDR2r_t ln_addr2; 349 LN_ADDR3r_t ln_addr3; 350 MAIN0_SPD_CTLr_t pcs_spd_ctrl; 351 SC_X4_SC_X4_OVRRr_t sc_x4_override; 352 MAIN0_SETUPr_t reg_main0_setup; 353 354 /* Main0 Setup Register */ 355 /*1. Loopback */ 356 READ_MAIN0_LPBK_CTLr(pc, &pcs_loopback_ctrl); 357 READ_TLB_RX_DIG_LPBK_CFGr(pc, &pmd_loopback_dig); 358 READ_TLB_TX_RMT_LPBK_CFGr(pc, &pmd_loopback_remote); 359 360 361 /*2. LaneSwap */ 362 READ_TX_X1_TX_LN_SWPr(pc, &pcs_tx_lane_swap); 363 READ_RX_X1_RX_LN_SWPr(pc, &pcs_rx_lane_swap); 364 READ_LN_ADDR0r(pc, &ln_addr0); 365 READ_LN_ADDR1r(pc, &ln_addr1); 366 READ_LN_ADDR2r(pc, &ln_addr2); 367 READ_LN_ADDR3r(pc, &ln_addr3); 368 369 370 /* 3. Master PortNum, port mode abd single port mode */ 371 READ_MAIN0_SETUPr(pc, ®_main0_setup); 372 373 /* 4. FEC, PLL reset enale */ 374 READ_SC_X4_SC_X4_OVRRr(pc, &sc_x4_override); 375 READ_MAIN0_SPD_CTLr(pc, &pcs_spd_ctrl); 376 377 /* Print the information here */ 378 { 379 uint16_t pcs_lcl_lb, pcs_rmt_lb, pmd_dig_lb, pmd_rmt_lb; 380 381 pcs_lcl_lb = MAIN0_LPBK_CTLr_LOCAL_PCS_LOOPBACK_ENABLEf_GET(pcs_loopback_ctrl); 382 pcs_rmt_lb = MAIN0_LPBK_CTLr_REMOTE_PCS_LOOPBACK_ENABLEf_GET(pcs_loopback_ctrl); 383 pmd_dig_lb = TLB_RX_DIG_LPBK_CFGr_DIG_LPBK_ENf_GET(pmd_loopback_dig); 384 pmd_rmt_lb = TLB_TX_RMT_LPBK_CFGr_RMT_LPBK_ENf_GET(pmd_loopback_remote); 385 386 PHYMOD_DEBUG_ERROR(("\n")); 387 PHYMOD_DEBUG_ERROR(("+------------------------------------------------------------------------------+\n")); 388 PHYMOD_DEBUG_ERROR(("| TOPOLOGY |\n")); 389 PHYMOD_DEBUG_ERROR(("+-------------------+--------------------------+---------------+---------------+\n")); 390 PHYMOD_DEBUG_ERROR(("| PCSLCL LPBK: %c%c%c%c | PCS TX LANE SWAP L2P : %d%d%d%d | FEC SEL: %d |\n", 391 (pcs_lcl_lb & 8) ? 'Y':'N', 392 (pcs_lcl_lb & 4) ? 'Y':'N', 393 (pcs_lcl_lb & 2) ? 'Y':'N', 394 (pcs_lcl_lb & 1) ? 'Y':'N', 395 TX_X1_TX_LN_SWPr_LOGICAL3_TO_PHY_SELf_GET(pcs_tx_lane_swap), 396 TX_X1_TX_LN_SWPr_LOGICAL2_TO_PHY_SELf_GET(pcs_tx_lane_swap), 397 TX_X1_TX_LN_SWPr_LOGICAL1_TO_PHY_SELf_GET(pcs_tx_lane_swap), 398 TX_X1_TX_LN_SWPr_LOGICAL0_TO_PHY_SELf_GET(pcs_tx_lane_swap), 399 SC_X4_SC_X4_OVRRr_AN_FEC_SEL_OVERRIDEf_GET(sc_x4_override))); 400 401 PHYMOD_DEBUG_ERROR(("| PCSRMT LPBK: %c%c%c%c | PCS RX LANE SWAP L2P : %d%d%d%d | PLLRST EN: %d |\n", 402 (pcs_rmt_lb & 8) ? 'Y':'N', 403 (pcs_rmt_lb & 4) ? 'Y':'N', 404 (pcs_rmt_lb & 2) ? 'Y':'N', 405 (pcs_rmt_lb & 1) ? 'Y':'N', 406 RX_X1_RX_LN_SWPr_LOGICAL3_TO_PHY_SELf_GET(pcs_rx_lane_swap), 407 RX_X1_RX_LN_SWPr_LOGICAL2_TO_PHY_SELf_GET(pcs_rx_lane_swap), 408 RX_X1_RX_LN_SWPr_LOGICAL1_TO_PHY_SELf_GET(pcs_rx_lane_swap), 409 RX_X1_RX_LN_SWPr_LOGICAL0_TO_PHY_SELf_GET(pcs_rx_lane_swap), 410 MAIN0_SPD_CTLr_PLL_RESET_ENf_GET(pcs_spd_ctrl))); 411 412 PHYMOD_DEBUG_ERROR(("| PMDDIG LPBK: %c%c%c%c | PMD TX LANE ADDR IDX : %d%d%d%d | PORT MODE: %d |\n", 413 (pmd_dig_lb & 8) ? 'Y':'N', 414 (pmd_dig_lb & 4) ? 'Y':'N', 415 (pmd_dig_lb & 2) ? 'Y':'N', 416 (pmd_dig_lb & 1) ? 'Y':'N', 417 LN_ADDR3r_TX_LANE_ADDR_3f_GET(ln_addr3), 418 LN_ADDR2r_TX_LANE_ADDR_2f_GET(ln_addr2), 419 LN_ADDR1r_TX_LANE_ADDR_1f_GET(ln_addr1), 420 LN_ADDR0r_TX_LANE_ADDR_0f_GET(ln_addr0), 421 MAIN0_SETUPr_PORT_MODE_SELf_GET(reg_main0_setup))); 422 423 PHYMOD_DEBUG_ERROR(("| PMDRET LPBK: %c%c%c%c | PMD RX LANE ADDR IDX : %d%d%d%d | SNGLMODE : %d |\n", 424 (pmd_rmt_lb & 8) ? 'Y':'N', 425 (pmd_rmt_lb & 4) ? 'Y':'N', 426 (pmd_rmt_lb & 2) ? 'Y':'N', 427 (pmd_rmt_lb & 1) ? 'Y':'N', 428 LN_ADDR3r_RX_LANE_ADDR_3f_GET(ln_addr3), 429 LN_ADDR2r_RX_LANE_ADDR_2f_GET(ln_addr2), 430 LN_ADDR1r_RX_LANE_ADDR_1f_GET(ln_addr1), 431 LN_ADDR0r_RX_LANE_ADDR_0f_GET(ln_addr0), 432 MAIN0_SETUPr_SINGLE_PORT_MODEf_GET(reg_main0_setup))); 433 PHYMOD_DEBUG_ERROR(("+-------------------+--------------------------+-------------------------------+\n")); 434 435 } 436 return PHYMOD_E_NONE; 437 } 438 439 /** 440 @brief Get the link status 441 @param pc handle to current TSCF context (#PHYMOD_ST) 442 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_ERROR else. 443 @details Print the link status. 444 1. pmd_live_status 445 a. pll_lock_sts : PMD PLL lock indication 446 b. tx_clk_vld_sts : The txclk is valid Don't see a need for this now, so will not check this bit 447 2a. pmd_lane_live_status 448 a. signal_detect_sts : The signal detected on the lane 449 b. rx_lock_sts : The recovery clock locked for the rx lane 450 c. rx_clk_vld_sts : The rxclk is valid for the lane. Don't see a need for this now, so will not check this bit 451 2b. pmd_lane_latched_status 452 3a. pcs_live_status 453 a. sync status : per port: Live Sync Status indicator for cl36, cl48, brcm mode. Comma detect/code sync 454 per lane: Live Block Lock Status indicator for cl49, cl82.Sync bits locked, on the 2 sync bits of the 66 bits(of 64/66 encoding) 455 b. link_status : Link status for that port 456 3b. pcs_latched_status 457 */ 458 int tefmod16_diag_link(PHYMOD_ST *pc) 459 { 460 PMD_X1_STSr_t pmd_live_status; 461 PMD_X4_STSr_t pmd_lane_live_status; 462 RX_X4_PCS_LATCH_STS1r_t rx_x4_latch_sts_reg; 463 RX_X4_PCS_LIVE_STS1r_t rx_x4_pcs_live_sts_reg; 464 phymod_access_t *lpc = (phymod_access_t*)pc; 465 466 int i,rx_lock_sts[4],sig_det_sts[4], this_lane; 467 int pcs_ber_sts[4], pcs_local_fault[4], pcs_remote_fault[4]; 468 int pcs_latch_link_h[4], pcs_latch_link_l[4], pcs_latch_ber_h[4], pcs_latch_ber_l[4]; 469 470 /*1. pmd_live_status */ 471 READ_PMD_X1_STSr(pc, &pmd_live_status); 472 473 /*2a. pmd_lane_live_status */ 474 475 this_lane = lpc->lane_mask; 476 for(i = 0; i < 4; i++) { 477 lpc->lane_mask = 1 << i; 478 READ_PMD_X4_STSr(lpc, &pmd_lane_live_status); 479 READ_RX_X4_PCS_LATCH_STS1r(lpc, &rx_x4_latch_sts_reg); 480 READ_RX_X4_PCS_LIVE_STS1r(lpc, &rx_x4_pcs_live_sts_reg); 481 sig_det_sts[i] = PMD_X4_STSr_SIGNAL_DETECT_STSf_GET(pmd_lane_live_status); 482 rx_lock_sts[i] = PMD_X4_STSr_RX_LOCK_STSf_GET(pmd_lane_live_status); 483 pcs_ber_sts[i] = RX_X4_PCS_LIVE_STS1r_HI_BERf_GET(rx_x4_pcs_live_sts_reg); 484 pcs_local_fault[i] = RX_X4_PCS_LIVE_STS1r_LOCAL_FAULTf_GET(rx_x4_pcs_live_sts_reg); 485 pcs_remote_fault[i] = RX_X4_PCS_LIVE_STS1r_REMOTE_FAULTf_GET(rx_x4_pcs_live_sts_reg); 486 pcs_latch_link_h[i] = RX_X4_PCS_LATCH_STS1r_LINK_STATUS_LHf_GET(rx_x4_latch_sts_reg); 487 pcs_latch_link_l[i] = RX_X4_PCS_LATCH_STS1r_LINK_STATUS_LLf_GET(rx_x4_latch_sts_reg); 488 pcs_latch_ber_h[i] = RX_X4_PCS_LATCH_STS1r_HI_BER_LHf_GET(rx_x4_latch_sts_reg); 489 pcs_latch_ber_l[i] = RX_X4_PCS_LATCH_STS1r_HI_BER_LLf_GET(rx_x4_latch_sts_reg); 490 } 491 lpc->lane_mask = this_lane; 492 493 494 /* Print the information here */ 495 PHYMOD_DEBUG_ERROR(("| LINK STATE | LH | LL |\n")); 496 PHYMOD_DEBUG_ERROR(("+-----------------------+-------------------+---------------+---------+--------+\n")); 497 PHYMOD_DEBUG_ERROR(("| PMD PLL LOCK : %c | | PCS LINK STAT : %c%c%c%c : %c%c%c%c |\n", 498 (PMD_X1_STSr_PLL_LOCK_STSf_GET(pmd_live_status) == 1) ? 'Y' : 'N', 499 (pcs_latch_link_h[3] == 1)? 'Y':'N', 500 (pcs_latch_link_h[2] == 1)? 'Y':'N', 501 (pcs_latch_link_h[1] == 1)? 'Y':'N', 502 (pcs_latch_link_h[0] == 1)? 'Y':'N', 503 (pcs_latch_link_l[3] == 1)? 'Y':'N', 504 (pcs_latch_link_l[2] == 1)? 'Y':'N', 505 (pcs_latch_link_l[1] == 1)? 'Y':'N', 506 (pcs_latch_link_l[0] == 1)? 'Y':'N')); 507 508 509 PHYMOD_DEBUG_ERROR(("| PMD SIG DETECT : %c%c%c%c | PCS BER : %c%c%c%c | PCS HI BER : %c%c%c%c : %c%c%c%c |\n", 510 (sig_det_sts[3] == 1)? 'Y':'N', 511 (sig_det_sts[2] == 1)? 'Y':'N', 512 (sig_det_sts[1] == 1)? 'Y':'N', 513 (sig_det_sts[0] == 1)? 'Y':'N', 514 (pcs_ber_sts[3] == 1)? 'Y':'N', 515 (pcs_ber_sts[2] == 1)? 'Y':'N', 516 (pcs_ber_sts[1] == 1)? 'Y':'N', 517 (pcs_ber_sts[0] == 1)? 'Y':'N', 518 (pcs_latch_ber_h[3] == 1)? 'Y':'N', 519 (pcs_latch_ber_h[2] == 1)? 'Y':'N', 520 (pcs_latch_ber_h[1] == 1)? 'Y':'N', 521 (pcs_latch_ber_h[0] == 1)? 'Y':'N', 522 (pcs_latch_ber_l[3] == 1)? 'Y':'N', 523 (pcs_latch_ber_l[2] == 1)? 'Y':'N', 524 (pcs_latch_ber_l[1] == 1)? 'Y':'N', 525 (pcs_latch_ber_l[0] == 1)? 'Y':'N')); 526 527 528 PHYMOD_DEBUG_ERROR(("| PMD LOCKED : %c%c%c%c | PCS Local Fault : %c%c%c%c | PCS Remote Fault : %c%c%c%c |\n", 529 (rx_lock_sts[3] == 1)? 'Y':'N', 530 (rx_lock_sts[2] == 1)? 'Y':'N', 531 (rx_lock_sts[1] == 1)? 'Y':'N', 532 (rx_lock_sts[0] == 1)? 'Y':'N', 533 (pcs_remote_fault[3] == 1)? 'Y':'N', 534 (pcs_remote_fault[2] == 1)? 'Y':'N', 535 (pcs_remote_fault[1] == 1)? 'Y':'N', 536 (pcs_remote_fault[0] == 1)? 'Y':'N', 537 (pcs_local_fault[3] == 1)? 'Y':'N', 538 (pcs_local_fault[2] == 1)? 'Y':'N', 539 (pcs_local_fault[1] == 1)? 'Y':'N', 540 (pcs_local_fault[0] == 1)? 'Y':'N')); 541 542 PHYMOD_DEBUG_ERROR(("+-----------------------+-------------------+----------------------------------+\n")); 543 544 return PHYMOD_E_NONE; 545 } 546 547 /** 548 @brief Get the link status 549 @param pc handle to current TSCF context (#PHYMOD_ST) 550 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_ERROR else. 551 @details Call all the Diags 552 */ 553 int tefmod16_diag_general(PHYMOD_ST *pc) 554 { 555 tefmod16_diag_topology(pc); 556 tefmod16_diag_link(pc); 557 tefmod16_diag_autoneg(pc); 558 tefmod16_diag_speed(pc); 559 560 return (PHYMOD_E_NONE); 561 } 562 563 /** 564 @brief Internal Tfc info (PRBS vs. PRTP. vs. PktGen etc.). 565 @param pc handle to current TSCF context (#PHYMOD_ST) 566 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_ERROR else. 567 @details Print the Internal Tfc types. 568 TBD. 569 */ 570 int tefmod16_diag_internal_tfc(PHYMOD_ST *pc) 571 { 572 PKTGEN_PRTPCTLr_t reg_prtp_ctl; 573 574 READ_PKTGEN_PRTPCTLr(pc, ®_prtp_ctl); 575 576 PHYMOD_DEBUG_ERROR(("| INTERNAL TFC |\n")); 577 PHYMOD_DEBUG_ERROR(("+------------------------------------------+-----------------------------------+\n")); 578 579 PHYMOD_DEBUG_ERROR(("| TX PRTP EN : %d | RX PRTP EN : %d | |\n", 580 PKTGEN_PRTPCTLr_TX_PRTP_ENf_GET(reg_prtp_ctl), 581 PKTGEN_PRTPCTLr_RX_PRTP_ENf_GET(reg_prtp_ctl))); 582 583 PHYMOD_DEBUG_ERROR(("+------------------------------------------+-----------------------------------+\n")); 584 585 return PHYMOD_E_NONE; 586 } 587 588 /** 589 @brief Soft Table diagnostic function 590 @param pc handle to current TSCF context (#PHYMOD_ST) 591 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_ERROR else. 592 @details ST diags 593 Print the soft table enteries 594 if the resolved_speed is not set, then all the table enteries are displayed 595 */ 596 597 #define _TRG_ST_PRINT(pc, st_num, ovr, sc_st) \ 598 { \ 599 SC_X1_SPD_##ovr##_SPDr_t sc_st##_speed; \ 600 SC_X1_SPD_##ovr##_0r_t sc_st##_0; \ 601 SC_X1_SPD_##ovr##_1r_t sc_st##_1; \ 602 SC_X1_SPD_##ovr##_2r_t sc_st##_2; \ 603 SC_X1_SPD_##ovr##_3r_t sc_st##_3; \ 604 SC_X1_SPD_##ovr##_4r_t sc_st##_4; \ 605 SC_X1_SPD_##ovr##_5r_t sc_st##_5; \ 606 uint8_t x1_speed; \ 607 \ 608 READ_SC_X1_SPD_##ovr##_SPDr(pc,&sc_st##_speed); \ 609 x1_speed = SC_X1_SPD_##ovr##_SPDr_SPEEDf_GET(sc_st##_speed); \ 610 x1_speed = (x1_speed >= TEFMOD16_SPD_ILLEGAL) ? TEFMOD16_SPD_ILLEGAL: x1_speed; \ 611 PHYMOD_DEBUG_ERROR(("| ST [%d] | %-28s| NUM LANES : %d |\n",\ 612 st_num, e2s_tefmod16_spd_intfc_type_t[x1_speed]+6, \ 613 SC_X1_SPD_##ovr##_SPDr_NUM_LANESf_GET(sc_st##_speed))); \ 614 \ 615 if((resolved_speed == 0xff) || \ 616 (resolved_speed==SC_X1_SPD_##ovr##_SPDr_SPEEDf_GET(sc_st##_speed))) { \ 617 READ_SC_X1_SPD_##ovr##_0r(pc,&sc_st##_0); \ 618 READ_SC_X1_SPD_##ovr##_1r(pc,&sc_st##_1); \ 619 READ_SC_X1_SPD_##ovr##_2r(pc,&sc_st##_2); \ 620 READ_SC_X1_SPD_##ovr##_3r(pc,&sc_st##_3); \ 621 READ_SC_X1_SPD_##ovr##_4r(pc,&sc_st##_4); \ 622 READ_SC_X1_SPD_##ovr##_5r(pc,&sc_st##_5); \ 623 \ 624 PHYMOD_DEBUG_ERROR(("| %-19s | |\n",\ 625 e2s_tefmod16_os_mode_type[SC_X1_SPD_##ovr##_0r_OS_MODEf_GET(sc_st##_0)]+6)); \ 626 \ 627 PHYMOD_DEBUG_ERROR(("| %-19s | |\n",\ 628 e2s_tefmod16_scr_mode[SC_X1_SPD_##ovr##_0r_SCR_MODEf_GET(sc_st##_0)]+6)); \ 629 \ 630 PHYMOD_DEBUG_ERROR(("+---------------------+-----------------------------+-----------+--------------+\n"));\ 631 } \ 632 } 633 634 /** 635 @brief Soft Table diagnostic function 636 @param pc handle to current TSCF context (#PHYMOD_ST) 637 @param resolved_speed The speed to which AN is already resolved. 638 @returns PHYMOD_E_NONE 639 @details Soft Table diags 640 Print the soft table enteries 641 if the resolved_speed is not set, then all the table enteries are displayed 642 */ 643 int tefmod16_diag_st(PHYMOD_ST *pc, int speed) 644 { 645 SC_X4_RSLVD_SPDr_t resolved_speed; 646 uint8_t x1_speed = 0; 647 uint8_t index = 0; 648 uint8_t lane_num = 0; 649 phymod_access_t phy_copy; 650 651 PHYMOD_MEMCPY(&phy_copy, pc, sizeof(phy_copy)); 652 for(index = 0; index < 4; index++) { 653 phy_copy.lane_mask = 1 << index; 654 READ_SC_X4_RSLVD_SPDr(&phy_copy, &resolved_speed); 655 x1_speed = SC_X4_RSLVD_SPDr_SPEEDf_GET(resolved_speed); 656 lane_num = SC_X4_RSLVD_SPDr_NUM_LANESf_GET(resolved_speed); 657 PHYMOD_DEBUG_ERROR(("| ST [%d] | SPD_ID : 0x%02X | NUM LANES : %-23d |\n", 658 index, x1_speed, 659 ((lane_num == 0)? 1 : (lane_num == 1)? 2 : 4 ))); 660 661 } 662 663 PHYMOD_DEBUG_ERROR(("+---------------------+-----------------------------+-----------+--------------+\n")); 664 665 return PHYMOD_E_NONE; 666 } 667 668 /** 669 @brief AN Timers diagnostic function 670 @param pc handle to current TSCF context (#PHYMOD_ST) 671 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_ERROR else. 672 @details Prints the AN timers 673 */ 674 int tefmod16_diag_an_timers(PHYMOD_ST* pc) 675 { 676 AN_X1_CL73_BRK_LNKr_t reg_cl73_break_link; 677 AN_X1_CL73_ERRr_t reg_cl73_err; 678 AN_X1_CL73_DME_LOCKr_t reg_cl73_dme_lock; 679 AN_X1_PD_SD_TMRr_t reg_pd_sd_timer; 680 AN_X1_IGNORE_LNK_TMRr_t reg_ignore_link_timer; 681 AN_X1_LNK_FAIL_INHBT_TMR_CL72r_t reg_inhibit_timer; 682 AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72r_t reg_inhibit_not_timer; 683 AN_X1_DME_PAGE_TMR_TYPEr_t reg_dme_page_timer; 684 685 686 READ_AN_X1_CL73_ERRr (pc, ®_cl73_err); 687 READ_AN_X1_PD_SD_TMRr (pc, ®_pd_sd_timer); 688 READ_AN_X1_CL73_BRK_LNKr (pc, ®_cl73_break_link); 689 READ_AN_X1_CL73_DME_LOCKr (pc, ®_cl73_dme_lock); 690 READ_AN_X1_IGNORE_LNK_TMRr (pc, ®_ignore_link_timer); 691 692 READ_AN_X1_DME_PAGE_TMR_TYPEr (pc, ®_dme_page_timer); 693 READ_AN_X1_LNK_FAIL_INHBT_TMR_CL72r (pc, ®_inhibit_timer); 694 READ_AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72r (pc, ®_inhibit_not_timer); 695 696 PHYMOD_DEBUG_ERROR(("| AN TIMERS |\n")); 697 PHYMOD_DEBUG_ERROR(("+--------------------------------------+---------------------------------------+\n")); 698 699 PHYMOD_DEBUG_ERROR(("| | CL73 BREAK TIMER PERIOD : 0x%08X |\n", 700 AN_X1_CL73_BRK_LNKr_CL73_BREAK_TIMER_PERIODf_GET(reg_cl73_break_link))); 701 702 PHYMOD_DEBUG_ERROR(("| CL73 ERR : 0x%08X | CL73 DME LOCK : 0x%08X |\n", 703 AN_X1_CL73_ERRr_CL73_ERROR_TIMER_PERIODf_GET(reg_cl73_err), 704 AN_X1_CL73_DME_LOCKr_PD_DME_LOCK_TIMER_PERIODf_GET(reg_cl73_dme_lock))); 705 706 PHYMOD_DEBUG_ERROR(("| IGNORE LINK : 0x%08X | PS SD : 0x%08x |\n", 707 AN_X1_IGNORE_LNK_TMRr_IGNORE_LINK_TIMER_PERIODf_GET(reg_ignore_link_timer), 708 AN_X1_PD_SD_TMRr_PD_SD_TIMER_PERIODf_GET(reg_pd_sd_timer))); 709 710 PHYMOD_DEBUG_ERROR(("| DME PAGE MIN : 0x%08X | DME PAGE MAX : 0x%08X |\n", 711 AN_X1_DME_PAGE_TMR_TYPEr_CL73_PAGE_TEST_MIN_TIMERf_GET(reg_dme_page_timer), 712 AN_X1_DME_PAGE_TMR_TYPEr_CL73_PAGE_TEST_MAX_TIMERf_GET(reg_dme_page_timer))); 713 714 PHYMOD_DEBUG_ERROR(("| FAIL INHIBIT W/O CL72 : 0x%08X | FAIL INHIBIT WITH CL72 : 0x%08X |\n", 715 AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72r_LINK_FAIL_INHIBIT_TIMER_NCL72_PERIODf_GET(reg_inhibit_not_timer), 716 AN_X1_LNK_FAIL_INHBT_TMR_CL72r_LINK_FAIL_INHIBIT_TIMER_CL72_PERIODf_GET(reg_inhibit_timer))); 717 718 PHYMOD_DEBUG_ERROR(("+--------------------------------------+---------------------------------------+\n")); 719 return PHYMOD_E_NONE; 720 } 721 722 /** 723 @brief Prints out the debug state register 724 @param pc handle to current TSCF context (#PHYMOD_ST) 725 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_ERROR else. 726 @details Prints the debug state regs. 727 */ 728 int tefmod16_diag_state(PHYMOD_ST* pc) 729 { 730 SC_X4_DBGr_t reg_sc_dbg_st; 731 AN_X4_TLA_SEQUENCER_STSr_t reg_an_tla_seq; 732 733 READ_SC_X4_DBGr(pc, ®_sc_dbg_st); 734 READ_AN_X4_TLA_SEQUENCER_STSr(pc, ®_an_tla_seq); 735 736 PHYMOD_DEBUG_ERROR(("| DEBUG STATE |\n")); 737 PHYMOD_DEBUG_ERROR(("+--------------------------------------+---------------------------------------+\n")); 738 PHYMOD_DEBUG_ERROR(("| SC_DEBUG_STATE : 0x%08x | FSM_STATUS : 0x%08X |\n", 739 SC_X4_DBGr_GET(reg_sc_dbg_st), SC_X4_DBGr_SC_FSM_STATUSf_GET(reg_sc_dbg_st))); 740 741 PHYMOD_DEBUG_ERROR(("| TLA_SEQUENCER STS : 0x%08x | |\n", 742 AN_X4_TLA_SEQUENCER_STSr_GET(reg_an_tla_seq))); 743 PHYMOD_DEBUG_ERROR(("+--------------------------------------+---------------------------------------+\n")); 744 745 return PHYMOD_E_NONE; 746 } 747 748 749 /** 750 @brief TBD 751 @param pc handle to current TSCF context (#PHYMOD_ST) 752 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_ERROR else. 753 @details Misc debug 754 */ 755 int tefmod16_diag_debug(PHYMOD_ST* pc) 756 { 757 _TRG_OPN(pc); 758 _TRG_CLS(pc); 759 return PHYMOD_E_NONE; 760 } 761 762 /** 763 @brief TBD 764 @param pc handle to current TSCF context (#PHYMOD_ST) 765 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_ERROR else. 766 @details Misc debug 767 */ 768 int tefmod16_diag_ieee(PHYMOD_ST *pc) 769 { 770 _TRG_OPN(pc); 771 _TRG_CLS(pc); 772 return PHYMOD_E_NONE; 773 } 774 775 /** 776 @brief TBD 777 @param pc handle to current TSCF context (#PHYMOD_ST) 778 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_ERROR else. 779 @details Misc debug 780 */ 781 int tefmod16_diag(PHYMOD_ST *pc, tefmod16_diag_type_t diag_type) 782 { 783 int rv; 784 rv = PHYMOD_E_NONE; 785 786 _TRG_OPN(pc); 787 788 if(diag_type & TEFMOD16_DIAG_GENERAL) rv |= tefmod16_diag_general(pc); 789 if(diag_type & TEFMOD16_DIAG_TOPOLOGY) rv |= tefmod16_diag_topology(pc); 790 if(diag_type & TEFMOD16_DIAG_LINK) rv |= tefmod16_diag_link(pc); 791 if(diag_type & TEFMOD16_DIAG_SPEED) rv |= tefmod16_diag_speed(pc); 792 if(diag_type & TEFMOD16_DIAG_ANEG) rv |= tefmod16_diag_autoneg(pc); 793 if(diag_type & TEFMOD16_DIAG_TFC) rv |= tefmod16_diag_internal_tfc(pc); 794 if(diag_type & TEFMOD16_DIAG_AN_TIMERS) rv |= tefmod16_diag_an_timers(pc); 795 if(diag_type & TEFMOD16_DIAG_STATE) rv |= tefmod16_diag_state(pc); 796 if(diag_type & TEFMOD16_DIAG_DEBUG) rv |= tefmod16_diag_debug(pc); 797 _TRG_CLS(pc); 798 return rv; 799 } 800 801 /*! 802 */ 803 int tefmod16_diag_disp(PHYMOD_ST *pc, const char* cmd_str) 804 { 805 tefmod16_diag_type_t type; 806 807 if (!cmd_str) 808 type = TEFMOD16_DIAG_GENERAL; 809 else if (!PHYMOD_STRCMP(cmd_str, "topo")) 810 type = TEFMOD16_DIAG_TOPOLOGY; 811 else if (!PHYMOD_STRCMP(cmd_str, "link")) 812 type = TEFMOD16_DIAG_LINK; 813 else if (!PHYMOD_STRCMP(cmd_str, "speed")) 814 type = TEFMOD16_DIAG_SPEED; 815 else if (!PHYMOD_STRCMP(cmd_str, "aneg")) 816 type = TEFMOD16_DIAG_ANEG; 817 else if (!PHYMOD_STRCMP(cmd_str, "tfc")) 818 type = TEFMOD16_DIAG_TFC; 819 else if (!PHYMOD_STRCMP(cmd_str, "antimers")) 820 type = TEFMOD16_DIAG_AN_TIMERS; 821 else if (!PHYMOD_STRCMP(cmd_str, "state")) 822 type = TEFMOD16_DIAG_STATE; 823 else if (!PHYMOD_STRCMP(cmd_str, "debug")) 824 type = TEFMOD16_DIAG_DEBUG; 825 else 826 type = TEFMOD16_DIAG_GENERAL; 827 828 return (tefmod16_diag(pc, type)); 829 }