tefmod16_cfg_seq.c (382907B)
1 /*---------------------------------------------------------------------- 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * $Copyright: (c) 2014 Broadcom Corporation All Rights Reserved.$ 8 * Broadcom Corporation 9 * Proprietary and Confidential information 10 * All rights reserved 11 * This source file is the property of Broadcom Corporation, and 12 * may not be copied or distributed in any isomorphic form without the 13 * prior written consent of Broadcom Corporation. 14 *--------------------------------------------------------------------- 15 * File : tefmod16_cfg_seq.c 16 * Description: c functions implementing Tier1s for TEFMod Serdes Driver 17 *---------------------------------------------------------------------*/ 18 19 #ifndef _DV_TB_ 20 #define _SDK_TEFMOD16_ 1 21 #endif 22 23 #ifdef _DV_TB_ 24 #include <stdint.h> 25 #include "tefmod_main.h" 26 #include "tefmod_defines.h" 27 #include "tefmod.h" 28 #include "tfPCSRegEnums.h" 29 #include "tfPMDRegEnums.h" 30 #include "phy_tsc_iblk.h" 31 #include "bcmi_tscf_16nm_xgxs_defs.h" 32 #endif /* _DV_TB_ */ 33 34 #ifdef _SDK_TEFMOD16_ 35 #include <phymod/phymod.h> 36 #include <phymod/phymod_system.h> 37 #include <phymod/phymod_util.h> 38 #include <phymod/phymod_debug.h> 39 #include <phymod/chip/bcmi_tscf_16nm_xgxs_defs.h> 40 #include "tefmod16.h" 41 #include "tefmod16_enum_defines.h" 42 #include "tefmod16_sc_lkup_table.h" 43 #include "tf16PCSRegEnums.h" 44 #endif /* _SDK_TEFMOD16_ */ 45 46 #ifdef _SDK_TEFMOD16_ 47 #define PHYMOD_ST const phymod_access_t 48 #else 49 #define PHYMOD_ST tefmod_st 50 #endif 51 52 #define TEFMOD16_CL73_25GBASE_FEC_POS 24 53 #define TEFMOD16_CL73_25G_RS_FEC_POS 23 54 #define TEFMOD16_BAM_CL74_REQ 0x3 55 #define TEFMOD16_BAM_CL91_REQ 0x3 56 #define REV_A 0x0 57 58 #ifdef _SDK_TEFMOD16_ 59 #define TEFMOD16_DBG_IN_FUNC_INFO(pc) \ 60 PHYMOD_VDBG(TEFMOD16_DBG_FUNC,pc,("-22%s: Adr:%08x Ln:%02d\n", __func__, (unsigned int)pc->addr, (int)pc->lane_mask)) 61 #define TEFMOD16_DBG_IN_FUNC_VIN_INFO(pc,_print_) \ 62 PHYMOD_VDBG(TEFMOD16_DBG_FUNCVALIN,pc,_print_) 63 #define TEFMOD16_DBG_IN_FUNC_VOUT_INFO(pc,_print_) \ 64 PHYMOD_VDBG(TEFMOD16_DBG_FUNCVALOUT,pc,_print_) 65 #endif 66 67 #ifdef _DV_TB_ 68 #define TEFMOD_DBG_IN_FUNC_INFO(pc) \ 69 PHYMOD_VDBG(TEFMOD_DBG_FUNC, pc, \ 70 ("TEFMOD IN Function : %s Port Add : %d Lane No: %d\n", \ 71 __func__, pc->prt_ad, pc->this_lane)) 72 #define TEFMOD_DBG_IN_FUNC_VIN_INFO(pc,_print_) \ 73 PHYMOD_VDBG(TEFMOD16_DBG_FUNCVALIN,pc,_print_) 74 #define TEFMOD_DBG_IN_FUNC_VOUT_INFO(pc,_print_) \ 75 PHYMOD_VDBG(TEFMOD_DBG_FUNCVALOUT,pc,_print_) 76 int phymod_debug_check(uint32_t flags, PHYMOD_ST *pc); 77 #endif 78 79 /** 80 @brief getRevDetails , calls revid_read 81 @param pc handle to current TSCF context (#PHYMOD_ST) 82 @returns The value PHYMOD_E_NONE upon successful completion 83 @details 84 */ 85 /* internal function */ 86 STATIC 87 int _tefmod16_getRevDetails(PHYMOD_ST* pc) 88 { 89 MAIN0_SERDESIDr_t MAIN0_SERDESIDr_reg; 90 MAIN0_SERDESIDr_CLR(MAIN0_SERDESIDr_reg); 91 PHYMOD_IF_ERR_RETURN(READ_MAIN0_SERDESIDr(pc, &MAIN0_SERDESIDr_reg)); 92 return MAIN0_SERDESIDr_GET(MAIN0_SERDESIDr_reg); 93 } 94 95 /** 96 @brief Read the 16 bit rev. id value etc. 97 @param pc handle to current TSCF context (#PHYMOD_ST) 98 @param revIdV receives the revid 99 @returns The value of the revid. 100 @details 101 This fucntion reads the revid register that contains core number, revision 102 number and returns it. 103 */ 104 int tefmod16_revid_read(PHYMOD_ST* pc, uint32_t *revIdV) /* REVID_READ */ 105 { 106 #ifdef _DV_TB_ 107 int laneselect; 108 #endif 109 TEFMOD16_DBG_IN_FUNC_INFO(pc); 110 #ifdef _DV_TB_ 111 laneselect = pc->lane_select; 112 pc->lane_select=TEFMOD16_LANE_0_0_0_1; 113 114 PHYMOD_DEBUG_ERROR(("%-22s u=%0d p=%0d sel=%x ln=%0d dxgxs=%0d\n", __func__, 115 pc->unit, pc->port, pc->lane_select, pc->this_lane, pc->dxgxs)); 116 #endif 117 *revIdV = _tefmod16_getRevDetails(pc); 118 #ifdef _DV_TB_ 119 pc->lane_select=laneselect; 120 #endif 121 return PHYMOD_E_NONE; 122 } 123 124 /** 125 @brief Read tscf model_number. 126 @param pc handle to current TSCF context (#PHYMOD_ST) 127 @param pc handle to current TSCF context (#PHYMOD_ST) 128 @returns The value of the model_number. 129 @details 130 This fucntion reads the revid register that contains core number, revision 131 number and returns it. 132 */ 133 int tefmod16_model_number_read(PHYMOD_ST* pc, uint32_t *model_number) /* model_number */ 134 { 135 MAIN0_SERDESIDr_t MAIN0_SERDESIDr_reg; 136 137 TEFMOD16_DBG_IN_FUNC_INFO(pc); 138 139 MAIN0_SERDESIDr_CLR(MAIN0_SERDESIDr_reg); 140 PHYMOD_IF_ERR_RETURN(READ_MAIN0_SERDESIDr(pc, &MAIN0_SERDESIDr_reg)); 141 *model_number = MAIN0_SERDESIDr_MODEL_NUMBERf_GET(MAIN0_SERDESIDr_reg); 142 143 return PHYMOD_E_NONE; 144 } 145 146 /** 147 @brief This function reads TX-PLL PLL_LOCK bit. 148 @param pc handle to current TSCF context (#PHYMOD_ST) 149 @param lockStatus reference which is updated with lock status. 150 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 151 @details Read PLL lock status. Returns 1 or 0 (locked/not) 152 */ 153 int tefmod16_pll_lock_get(PHYMOD_ST* pc, int* lockStatus) 154 { 155 PMD_X1_STSr_t reg_pmd_x1_sts; 156 TEFMOD16_DBG_IN_FUNC_INFO(pc); 157 READ_PMD_X1_STSr(pc, ®_pmd_x1_sts); 158 159 *lockStatus = PMD_X1_STSr_PLL_LOCK_STSf_GET(reg_pmd_x1_sts); 160 /* TEFMOD16_DBG_IN_FUNC_VOUT_INFO(pc,("PLL lockStatus: %d", *lockStatus)); */ 161 return PHYMOD_E_NONE; 162 } 163 164 /** 165 @brief This function reads RX-PMD PMD_LOCK bit. 166 @param pc handle to current TSCF context (#PHYMOD_ST) 167 @param lockStatus reference which is updated with pmd_lock status 168 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 169 @details Read PMD lock status Returns 1 or 0 (locked/not) 170 */ 171 #ifdef _DV_TB_ 172 int tefmod_pmd_lock_get(PHYMOD_ST* pc, uint32_t* lockStatus) 173 { 174 PMD_X4_STSr_t reg_pmd_x4_sts; 175 int i; 176 int lane_mask; 177 PHYMOD_ST* pc_copy; 178 TEFMOD16_DBG_IN_FUNC_INFO(pc); 179 180 pc_copy = pc; 181 pc_copy->port_type = TEFMOD16_MULTI_PORT; 182 lane_mask = 0; 183 switch(pc->port_type) { 184 case TEFMOD_MULTI_PORT: lane_mask = 0x1 << pc->this_lane; break; 185 case TEFMOD_TRI1_PORT: if(pc->this_lane == 3) lane_mask = 0xc; 186 else lane_mask = 0x1 << pc->this_lane; 187 break; 188 case TEFMOD_TRI2_PORT: if(pc->this_lane == 0) lane_mask = 0x3; 189 else lane_mask = 0x1 << pc->this_lane; 190 break; 191 case TEFMOD_DXGXS: if(pc->this_lane == 0) lane_mask = 0x3; 192 else lane_mask = 0xc; 193 break; 194 case TEFMOD_SINGLE_PORT: lane_mask = 0xf; break; 195 default: break; 196 } 197 198 *lockStatus = 0; 199 for(i=0; i<4; i++) { 200 if(((lane_mask >> i) & 0x1) == 1) { 201 pc_copy->this_lane = i; 202 READ_PMD_X4_STSr(pc_copy, ®_pmd_x4_sts); 203 *lockStatus = *lockStatus & PMD_X4_STSr_RX_LOCK_STSf_GET(reg_pmd_x4_sts); 204 } 205 } 206 /* TEFMOD_DBG_IN_FUNC_VOUT_INFO(pc,("PMD lockStatus: %d", *lockStatus)); */ 207 208 return PHYMOD_E_NONE; 209 } 210 #endif 211 212 #ifdef _SDK_TEFMOD16_ 213 int tefmod16_pmd_lock_get(PHYMOD_ST* pc, uint32_t* lockStatus) 214 { 215 PMD_X4_STSr_t reg_pmd_x4_sts; 216 int i; 217 phymod_access_t pa_copy; 218 TEFMOD16_DBG_IN_FUNC_INFO(pc); 219 220 *lockStatus = 1; 221 PHYMOD_MEMCPY(&pa_copy, pc, sizeof(pa_copy)); 222 223 for(i=0; i<4; i++) { 224 if(((pc->lane_mask >> i) & 0x1) == 1) { 225 pa_copy.lane_mask = 0x1 << i; 226 READ_PMD_X4_STSr(&pa_copy, ®_pmd_x4_sts); 227 *lockStatus = *lockStatus & PMD_X4_STSr_RX_LOCK_STSf_GET(reg_pmd_x4_sts); 228 } 229 } 230 231 /* TEFMOD16_DBG_IN_FUNC_VOUT_INFO(pc,("PMD lockStatus: %d", *lockStatus)); */ 232 233 return PHYMOD_E_NONE; 234 } 235 #endif 236 237 /** 238 @brief Init routine sets various operating modes of TSCF. 239 @param pc handle to current TSCF context (#PHYMOD_ST) 240 @param pmd_touched Is this the first time we are visiting the PMD. 241 @param spd_intf Input of enum type #tefmod16_spd_intfc_type_t 242 @param pll_mode to override the pll div 243 @returns PHYMOD_E_NONE if successful. PHYMOD_E_FAIL else. 244 @details 245 246 This function is called once per TSCF. It cannot be called multiple times 247 and should be called immediately after reset. Elements of #PHYMOD_ST should be 248 initialized to required values prior to calling this function. The following 249 sub-configurations are performed here. 250 251 \li Set pll divider for VCO setting in PMD. pll divider is calculated from max_speed. 252 */ 253 254 int tefmod16_set_pll_mode(PHYMOD_ST* pc, int pmd_touched, tefmod16_spd_intfc_type_t spd_intf, int pll_mode) /* SET_PLL_MODE */ 255 { 256 PLL_CAL_CTL7r_t reg_ctl7; 257 int speed; 258 259 TEFMOD16_DBG_IN_FUNC_INFO(pc); 260 /* TEFMOD16_DBG_IN_FUNC_VIN_INFO(pc,("pmd_touched: %d, spd_intf: %d, pll_mode: %d", pmd_touched, spd_intf, pll_mode)); */ 261 262 PLL_CAL_CTL7r_CLR(reg_ctl7); 263 if (pmd_touched == 0) { 264 tefmod16_get_mapped_speed(spd_intf, &speed); 265 /*Support Override PLL DIV */ 266 if(pll_mode & 0x80000000) { 267 PLL_CAL_CTL7r_PLL_MODEf_SET(reg_ctl7, (pll_mode) & 0x0000ffff); 268 } else { 269 PLL_CAL_CTL7r_PLL_MODEf_SET(reg_ctl7, (sc_pmd16_entry[speed].pll_mode)); 270 } 271 272 #ifdef _DV_TB_ 273 if( pc->verbosity) { 274 printf("%-22s: plldiv:%d data:%x\n", __func__, pc->plldiv, PLL_CAL_CTL7r_PLL_MODEf_GET(reg_ctl7)); 275 printf("%-22s: main0_setup=%x\n", __func__, PLL_CAL_CTL7r_PLL_MODEf_GET(reg_ctl7)); 276 } 277 #endif 278 PHYMOD_IF_ERR_RETURN (MODIFY_PLL_CAL_CTL7r(pc, reg_ctl7)); 279 } 280 return PHYMOD_E_NONE; 281 282 } /* tefmod16_set_pll_mode(PHYMOD_ST* pc) */ 283 284 /*! 285 @brief get port speed id configured 286 @param pc handle to current TSCF context (#PHYMOD_ST) 287 @param speed_id Receives the resolved speed cfg in the speed_id 288 @returns The value PHYMOD_E_NONE upon successful completion. 289 @details get port speed configured 290 */ 291 292 int tefmod16_speed_id_get(PHYMOD_ST* pc, int *speed_id) 293 { 294 SC_X4_RSLVD_SPDr_t sc_final_resolved_speed; 295 296 TEFMOD16_DBG_IN_FUNC_INFO(pc); 297 SC_X4_RSLVD_SPDr_CLR(sc_final_resolved_speed); 298 READ_SC_X4_RSLVD_SPDr(pc,&sc_final_resolved_speed); 299 *speed_id = SC_X4_RSLVD_SPDr_SPEEDf_GET(sc_final_resolved_speed); 300 /* TEFMOD16_DBG_IN_FUNC_VOUT_INFO(pc,("speed_id: %d", *speed_id)); */ 301 302 return PHYMOD_E_NONE; 303 } 304 305 int tefmod16_refclk_set(PHYMOD_ST* pc, phymod_ref_clk_t ref_clock) 306 { 307 DIG_TOP_USER_CTL0r_t dig_top_user_reg; 308 READ_DIG_TOP_USER_CTL0r(pc, &dig_top_user_reg); 309 switch (ref_clock) { 310 case phymodRefClk156Mhz: 311 DIG_TOP_USER_CTL0r_HEARTBEAT_COUNT_1USf_SET(dig_top_user_reg, 0x271); 312 break; 313 case phymodRefClk125Mhz: 314 DIG_TOP_USER_CTL0r_HEARTBEAT_COUNT_1USf_SET(dig_top_user_reg, 0x1f4); 315 break; 316 default: 317 DIG_TOP_USER_CTL0r_HEARTBEAT_COUNT_1USf_SET(dig_top_user_reg, 0x271); 318 break; 319 } 320 MODIFY_DIG_TOP_USER_CTL0r(pc, dig_top_user_reg); 321 322 return PHYMOD_E_NONE; 323 } 324 325 /** 326 @brief Init the PMD 327 @param pc handle to current TSCF context (#PHYMOD_ST) 328 @param pmd_touched If the PMD is already initialized 329 @returns The value PHYMOD_E_NONE upon successful completion 330 @details Per core PMD resets (both datapath and entire core) 331 We only intend to use this function if the PMD has never been initialized. 332 */ 333 int tefmod16_pmd_reset_seq(PHYMOD_ST* pc, int pmd_touched) /* PMD_RESET_SEQ */ 334 { 335 PMD_X1_CTLr_t reg_pmd_x1_ctrl; 336 TEFMOD16_DBG_IN_FUNC_INFO(pc); 337 /* TEFMOD16_DBG_IN_FUNC_VIN_INFO(pc,("pmd_touched: %x", pmd_touched)); */ 338 339 PMD_X1_CTLr_CLR(reg_pmd_x1_ctrl); 340 341 if (pmd_touched == 0) { 342 PMD_X1_CTLr_POR_H_RSTBf_SET(reg_pmd_x1_ctrl,1); 343 PMD_X1_CTLr_CORE_DP_H_RSTBf_SET(reg_pmd_x1_ctrl,1); 344 PHYMOD_IF_ERR_RETURN(WRITE_PMD_X1_CTLr(pc,reg_pmd_x1_ctrl)); 345 } 346 return PHYMOD_E_NONE; 347 } 348 349 /** 350 @brief Checks config valid status for the port 351 @param pc handle to current TSCF context (#PHYMOD_ST) 352 @param port_num Port Number 353 @returns The value PHYMOD_E_NONE upon successful completion 354 @details This register bit indicates that PCS is now programmed as required by 355 the HT entry for that speed 356 */ 357 358 int tefmod16_master_port_num_set( PHYMOD_ST *pc, int port_num) 359 { 360 MAIN0_SETUPr_t main_reg; 361 /* TEFMOD16_DBG_IN_FUNC_VIN_INFO(pc,("port_num: %d", port_num)); */ 362 363 MAIN0_SETUPr_CLR(main_reg); 364 MAIN0_SETUPr_MASTER_PORT_NUMf_SET(main_reg, port_num); 365 MODIFY_MAIN0_SETUPr(pc, main_reg); 366 367 return PHYMOD_E_NONE; 368 } 369 370 /** 371 @brief update the port mode 372 @param pc handle to current TSCF context (#PHYMOD_ST) 373 @param pll_restart Receives info. on whether to restart pll. 374 @returns The value PHYMOD_E_NONE upon successful completion 375 */ 376 int tefmod16_update_port_mode( PHYMOD_ST *pc, int *pll_restart) 377 { 378 MAIN0_SETUPr_t mode_reg; 379 int port_mode_sel, port_mode_sel_reg, temp_pll_restart; 380 uint32_t single_port_mode; 381 uint32_t first_couple_mode = 0, second_couple_mode = 0; 382 383 port_mode_sel = 0 ; 384 single_port_mode = 0 ; 385 temp_pll_restart = 0; 386 387 READ_MAIN0_SETUPr(pc, &mode_reg); 388 port_mode_sel_reg = MAIN0_SETUPr_PORT_MODE_SELf_GET(mode_reg); 389 390 if(pc->lane_mask == 0xf){ 391 port_mode_sel = 4; 392 if( port_mode_sel_reg != 4){ 393 temp_pll_restart = 1; 394 } 395 } else{ 396 first_couple_mode = ((port_mode_sel_reg == 2) || (port_mode_sel_reg == 3) || (port_mode_sel_reg == 4)); 397 second_couple_mode = ((port_mode_sel_reg == 1) || (port_mode_sel_reg == 3) || (port_mode_sel_reg == 4)); 398 switch(pc->lane_mask){ 399 case 1: 400 case 2: 401 first_couple_mode = 0; 402 break; 403 case 4: 404 case 8: 405 second_couple_mode = 0; 406 break; 407 case 3: 408 first_couple_mode = 1; 409 break; 410 case 0xc: 411 second_couple_mode = 1; 412 break; 413 default: 414 /* dprintf("%-22s: ERROR port_mode_sel=%0d undefined\n", 415 __func__, port_mode_sel_reg); */ 416 break ; 417 } 418 419 if(first_couple_mode ){ 420 port_mode_sel =(second_couple_mode)? 3: 2; 421 } else if(second_couple_mode) { 422 port_mode_sel = 1; 423 } else{ 424 port_mode_sel = 0 ; 425 } 426 } 427 428 *pll_restart = temp_pll_restart; 429 430 /*if(pc->verbosity & TEFMOD16_DBG_INIT) 431 dprintf("%-22s u=%0d p=%0d port_mode_sel old=%0d new=%0d\n", __func__, 432 pc->unit, pc->port, port_mode_sel_reg, port_mode_sel) ; */ 433 434 MAIN0_SETUPr_SINGLE_PORT_MODEf_SET(mode_reg, single_port_mode); 435 MAIN0_SETUPr_PORT_MODE_SELf_SET(mode_reg, port_mode_sel); 436 MODIFY_MAIN0_SETUPr(pc, mode_reg); 437 /* TEFMOD16_DBG_IN_FUNC_VOUT_INFO(pc,("pll_restart: %d", *pll_restart)); */ 438 return PHYMOD_E_NONE ; 439 } 440 441 /** 442 @brief Enable the pll reset bit 443 @param pc handle to current TSCF context (#PHYMOD_ST) 444 @param enable Controls whether to reset PLL 445 @returns The value PHYMOD_E_NONE upon successful completion 446 @details 447 Resets the PLL 448 */ 449 int tefmod16_pll_reset_enable_set (PHYMOD_ST *pc, int enable) 450 { 451 MAIN0_SPD_CTLr_t main_reg; 452 453 MAIN0_SPD_CTLr_CLR(main_reg); 454 MAIN0_SPD_CTLr_PLL_RESET_ENf_SET(main_reg, enable); 455 MODIFY_MAIN0_SPD_CTLr(pc, main_reg); 456 457 return PHYMOD_E_NONE ; 458 } 459 460 /** 461 @brief Read PCS Link status 462 @param pc handle to current TSCF context (#PHYMOD_ST) 463 @param *link Reference for Status of PCS Link 464 @returns The value PHYMOD_E_NONE upon successful completion 465 @details Return the status of the PCS link. The link up implies the PCS is able 466 to decode the digital bits coming in on the serdes. It automatically implies 467 that the PLL is stable and that the PMD sublayer has successfully recovered the 468 clock on the receive line. 469 */ 470 int tefmod16_get_pcs_link_status(PHYMOD_ST* pc, uint32_t *link) 471 { 472 RX_X4_PCS_LIVE_STS1r_t reg_pcs_live_sts; 473 474 TEFMOD16_DBG_IN_FUNC_INFO(pc); 475 RX_X4_PCS_LIVE_STS1r_CLR(reg_pcs_live_sts); 476 PHYMOD_IF_ERR_RETURN (READ_RX_X4_PCS_LIVE_STS1r(pc, ®_pcs_live_sts)); 477 *link = RX_X4_PCS_LIVE_STS1r_LINK_STATUSf_GET(reg_pcs_live_sts); 478 /* TEFMOD16_DBG_IN_FUNC_VOUT_INFO(pc,("pcs_live_stats_link: %d", *link)); */ 479 480 return PHYMOD_E_NONE; 481 } 482 483 int tefmod16_get_pcs_latched_link_status(PHYMOD_ST* pc, uint32_t *link) 484 { 485 RX_X4_PCS_LIVE_STS1r_t reg_pcs_live_sts; 486 RX_X4_PCS_LATCH_STS1r_t latched_sts ; 487 int latched_val ; 488 489 TEFMOD16_DBG_IN_FUNC_INFO(pc); 490 RX_X4_PCS_LIVE_STS1r_CLR(reg_pcs_live_sts); 491 RX_X4_PCS_LATCH_STS1r_CLR(latched_sts) ; 492 493 PHYMOD_IF_ERR_RETURN (READ_RX_X4_PCS_LIVE_STS1r(pc, ®_pcs_live_sts)); 494 PHYMOD_IF_ERR_RETURN (READ_RX_X4_PCS_LATCH_STS1r(pc, &latched_sts)) ; 495 latched_val = RX_X4_PCS_LATCH_STS1r_LINK_STATUS_LLf_GET(latched_sts) ; 496 if(latched_val) { 497 *link = 0 ; 498 } else { 499 *link = RX_X4_PCS_LIVE_STS1r_LINK_STATUSf_GET(reg_pcs_live_sts); 500 } 501 /* TEFMOD16_DBG_IN_FUNC_VOUT_INFO(pc,("pcs_live_stats_link: %d", *link)); */ 502 503 return PHYMOD_E_NONE; 504 } 505 506 /** 507 @brief Get the Port status 508 @param pc handle to current TSCF context (#PHYMOD_ST) 509 @param enabled Receives status on port enabled 510 @returns The value PHYMOD_E_NONE upon successful completion 511 */ 512 513 int tefmod16_enable_get(PHYMOD_ST* pc, uint32_t* enabled) 514 { 515 SC_X4_CTLr_t reg_sc_ctrl; 516 517 TEFMOD16_DBG_IN_FUNC_INFO(pc); 518 SC_X4_CTLr_CLR(reg_sc_ctrl); 519 520 PHYMOD_IF_ERR_RETURN(READ_SC_X4_CTLr(pc,®_sc_ctrl)); 521 *enabled = SC_X4_CTLr_SW_SPEED_CHANGEf_GET(reg_sc_ctrl); 522 523 return PHYMOD_E_NONE; 524 } 525 /** 526 @brief Get info on Disable status of the Port 527 @param pc handle to current TSCF context (#PHYMOD_ST) 528 @returns The value PHYMOD_E_NONE upon successful completion 529 @details Disables the port by writing 0 to the speed config logic in PCS. 530 This makes the PCS to bring down the PCS blocks and also apply lane datapath 531 reset to the PMD. There is no control input to this function since it only does 532 one thing. 533 */ 534 int tefmod16_disable_set(PHYMOD_ST* pc) 535 { 536 SC_X4_CTLr_t reg_sc_ctrl; 537 538 TEFMOD16_DBG_IN_FUNC_INFO(pc); 539 SC_X4_CTLr_CLR(reg_sc_ctrl); 540 READ_SC_X4_CTLr(pc, ®_sc_ctrl); 541 542 /* write 0 to the speed change */ 543 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(reg_sc_ctrl, 0); 544 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_CTLr(pc,reg_sc_ctrl)); 545 546 return PHYMOD_E_NONE; 547 } 548 549 int tefmod16_enable_set(PHYMOD_ST* pc) 550 { 551 SC_X4_CTLr_t reg_sc_ctrl; 552 553 TEFMOD16_DBG_IN_FUNC_INFO(pc); 554 SC_X4_CTLr_CLR(reg_sc_ctrl); 555 READ_SC_X4_CTLr(pc, ®_sc_ctrl); 556 557 /* write 0 to the speed change */ 558 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(reg_sc_ctrl, 1); 559 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_CTLr(pc,reg_sc_ctrl)); 560 561 return PHYMOD_E_NONE; 562 } 563 564 565 /** 566 @brief Get the plldiv from lookup table 567 @param pc handle to current TSCF context (#PHYMOD_ST) 568 @param spd_intf Input of enum type #tefmod16_spd_intfc_type_t 569 @param plldiv Receives PLL Divider value 570 @returns The value PHYMOD_E_NONE upon successful completion 571 @details Get the plldiv from lookup table as a function of the speed. 572 */ 573 574 int tefmod16_plldiv_lkup_get(PHYMOD_ST* pc, tefmod16_spd_intfc_type_t spd_intf, phymod_ref_clk_t refclk, uint32_t *plldiv) 575 { 576 int speed_id; 577 578 TEFMOD16_DBG_IN_FUNC_INFO(pc); 579 tefmod16_get_mapped_speed(spd_intf, &speed_id); 580 if (refclk == phymodRefClk125Mhz) { 581 *plldiv = sc_pmd16_entry_125M_ref[speed_id].pll_mode; 582 } else { 583 *plldiv = sc_pmd16_entry[speed_id].pll_mode; 584 } 585 /* TEFMOD16_DBG_IN_FUNC_VOUT_INFO(pc,("plldiv: %d", *plldiv)); */ 586 587 return PHYMOD_E_NONE; 588 589 } 590 591 /** 592 @brief Get the osmode from lookup table 593 @param pc handle to current TSCF context (#PHYMOD_ST) 594 @param spd_intf Input of enum type #tefmod16_spd_intfc_type_t 595 @param osmode Receives the OS mode as assumed in the hard table. 596 @returns The value PHYMOD_E_NONE upon successful completion 597 @details Get the osmode from software version of Speed table as a function of 598 the speed 599 */ 600 int tefmod16_osmode_lkup_get(PHYMOD_ST* pc, tefmod16_spd_intfc_type_t spd_intf, uint32_t *osmode) 601 { 602 int speed_id; 603 604 TEFMOD16_DBG_IN_FUNC_INFO(pc); 605 tefmod16_get_mapped_speed(spd_intf, &speed_id); 606 *osmode = sc_pmd16_entry[speed_id].t_pma_os_mode; 607 608 return PHYMOD_E_NONE; 609 } 610 611 /** 612 @brief sets both the RX and TX lane swap values for all lanes simultaneously. 613 @param pc handle to current TSCF context (#PHYMOD_ST) 614 @param tx_rx_swap Receives the PCS lane swap value 615 @returns The value PHYMOD_E_NONE upon successful completion 616 @details 617 This function gets the TX lane swap values for all lanes simultaneously. 618 */ 619 620 int tefmod16_pcs_tx_lane_swap_get ( PHYMOD_ST *pc, uint32_t *tx_swap) 621 { 622 unsigned int pcs_map; 623 TX_X1_TX_LN_SWPr_t reg; 624 625 TEFMOD16_DBG_IN_FUNC_INFO(pc); 626 627 TX_X1_TX_LN_SWPr_CLR(reg); 628 629 PHYMOD_IF_ERR_RETURN 630 (READ_TX_X1_TX_LN_SWPr(pc, ®)); 631 632 pcs_map = TX_X1_TX_LN_SWPr_GET(reg); 633 634 *tx_swap = (((pcs_map >> 0) & 0x3) << 0) | 635 (((pcs_map >> 2) & 0x3) << 4) | 636 (((pcs_map >> 4) & 0x3) << 8) | 637 (((pcs_map >> 6) & 0x3) << 12) ; 638 639 return PHYMOD_E_NONE ; 640 } 641 642 int tefmod16_pcs_rx_lane_swap_get ( PHYMOD_ST *pc, uint32_t *rx_swap) 643 { 644 unsigned int pcs_map; 645 RX_X1_RX_LN_SWPr_t reg; 646 647 TEFMOD16_DBG_IN_FUNC_INFO(pc); 648 649 RX_X1_RX_LN_SWPr_CLR(reg); 650 651 PHYMOD_IF_ERR_RETURN 652 (READ_RX_X1_RX_LN_SWPr(pc, ®)) ; 653 654 pcs_map = RX_X1_RX_LN_SWPr_GET(reg); 655 656 *rx_swap = (((pcs_map >> 0) & 0x3) << 0) | 657 (((pcs_map >> 2) & 0x3) << 4) | 658 (((pcs_map >> 4) & 0x3) << 8) | 659 (((pcs_map >> 6) & 0x3) << 12) ; 660 661 return PHYMOD_E_NONE ; 662 } 663 664 665 int tefmod16_pmd_lane_swap_tx_rx_get ( PHYMOD_ST *pc, uint32_t *tx_lane_map, uint32_t *rx_lane_map) 666 { 667 uint16_t tx_lane_map_0, tx_lane_map_1, tx_lane_map_2, tx_lane_map_3; 668 uint16_t rx_lane_map_0, rx_lane_map_1, rx_lane_map_2, rx_lane_map_3; 669 LN_ADDR0r_t ln0_reg; 670 LN_ADDR1r_t ln1_reg; 671 LN_ADDR2r_t ln2_reg; 672 LN_ADDR3r_t ln3_reg; 673 674 TEFMOD16_DBG_IN_FUNC_INFO(pc); 675 LN_ADDR0r_CLR(ln0_reg); 676 LN_ADDR1r_CLR(ln1_reg); 677 LN_ADDR2r_CLR(ln2_reg); 678 LN_ADDR3r_CLR(ln3_reg); 679 680 PHYMOD_IF_ERR_RETURN 681 (READ_LN_ADDR0r(pc, &ln0_reg)); 682 PHYMOD_IF_ERR_RETURN 683 (READ_LN_ADDR1r(pc, &ln1_reg)); 684 PHYMOD_IF_ERR_RETURN 685 (READ_LN_ADDR2r(pc, &ln2_reg)); 686 PHYMOD_IF_ERR_RETURN 687 (READ_LN_ADDR3r(pc, &ln3_reg)); 688 689 tx_lane_map_0 = LN_ADDR0r_TX_LANE_ADDR_0f_GET(ln0_reg); 690 rx_lane_map_0 = LN_ADDR0r_RX_LANE_ADDR_0f_GET(ln0_reg); 691 tx_lane_map_1 = LN_ADDR1r_TX_LANE_ADDR_1f_GET(ln1_reg); 692 rx_lane_map_1 = LN_ADDR1r_RX_LANE_ADDR_1f_GET(ln1_reg); 693 tx_lane_map_2 = LN_ADDR2r_TX_LANE_ADDR_2f_GET(ln2_reg); 694 rx_lane_map_2 = LN_ADDR2r_RX_LANE_ADDR_2f_GET(ln2_reg); 695 tx_lane_map_3 = LN_ADDR3r_TX_LANE_ADDR_3f_GET(ln3_reg); 696 rx_lane_map_3 = LN_ADDR3r_RX_LANE_ADDR_3f_GET(ln3_reg); 697 698 *tx_lane_map = ((tx_lane_map_0 & 0xf) << 0) 699 | ((tx_lane_map_1 & 0xf) << 4) 700 | ((tx_lane_map_2 & 0xf) << 8) 701 | ((tx_lane_map_3 & 0xf) << 12); 702 703 *rx_lane_map = ((rx_lane_map_0 & 0xf) << 0) 704 | ((rx_lane_map_1 & 0xf) << 4) 705 | ((rx_lane_map_2 & 0xf) << 8) 706 | ((rx_lane_map_3 & 0xf) << 12); 707 708 return PHYMOD_E_NONE ; 709 } 710 711 712 int tefmod16_pmd_lane_swap_tx_get ( PHYMOD_ST *pc, uint32_t *tx_lane_map) 713 { 714 /*TBD : check if PMD has lane swap control 715 uint16_t tx_lane_map_0, tx_lane_map_1, tx_lane_map_2, tx_lane_map_3; 716 DIG_TX_LN_MAP_0_1_2r_t reg; 717 DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r_t reg1; 718 719 TEFMOD16_DBG_IN_FUNC_INFO(pc); 720 DIG_TX_LN_MAP_0_1_2r_CLR(reg); 721 DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r_CLR(reg1); 722 723 PHYMOD_IF_ERR_RETURN 724 (READ_DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r(pc, ®1)); 725 PHYMOD_IF_ERR_RETURN 726 (READ_DIG_TX_LN_MAP_0_1_2r(pc, ®)); 727 728 tx_lane_map_0 = DIG_TX_LN_MAP_0_1_2r_TX_LANE_MAP_0f_GET(reg); 729 tx_lane_map_1 = DIG_TX_LN_MAP_0_1_2r_TX_LANE_MAP_1f_GET(reg); 730 tx_lane_map_2 = DIG_TX_LN_MAP_0_1_2r_TX_LANE_MAP_2f_GET(reg); 731 tx_lane_map_3 = DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r_TX_LANE_MAP_3f_GET(reg1); 732 733 *tx_lane_map = ((tx_lane_map_0 & 0xf) << 0) 734 | ((tx_lane_map_1 & 0xf) << 4) 735 | ((tx_lane_map_2 & 0xf) << 8) 736 | ((tx_lane_map_3 & 0xf) << 12); */ 737 738 739 return PHYMOD_E_NONE ; 740 } 741 742 743 int tefmod16_pmd_lane_dp_reset(PHYMOD_ST* pc, uint16_t reset_value) 744 { 745 return PHYMOD_E_NONE; 746 } 747 748 749 /** 750 @brief rx lane reset and enable of any particular lane 751 @param pc handle to current TSCF context (#PHYMOD_ST) 752 @param enable to reset the lane. 753 @returns The value PHYMOD_E_NONE upon successful completion. 754 @details 755 This function enables/disables rx lane (RSTB_LANE) or read back control bit for 756 that based on per_lane_control being 1 or 0. If per_lane_control is 0xa, only 757 read back RSTB_LANE. 758 */ 759 int tefmod16_rx_lane_control_set(PHYMOD_ST* pc, int enable) /* RX_LANE_CONTROL */ 760 { 761 RX_X4_PMA_CTL0r_t reg_pma_ctrl; 762 763 TEFMOD16_DBG_IN_FUNC_INFO(pc); 764 RX_X4_PMA_CTL0r_CLR(reg_pma_ctrl); 765 766 if (enable) { 767 RX_X4_PMA_CTL0r_RSTB_LANEf_SET( reg_pma_ctrl, 0); 768 PHYMOD_IF_ERR_RETURN (MODIFY_RX_X4_PMA_CTL0r(pc, reg_pma_ctrl)); 769 RX_X4_PMA_CTL0r_RSTB_LANEf_SET(reg_pma_ctrl, 1); 770 PHYMOD_IF_ERR_RETURN (MODIFY_RX_X4_PMA_CTL0r(pc, reg_pma_ctrl)); 771 } else { 772 /* bit set to 0 for disabling RXP */ 773 RX_X4_PMA_CTL0r_RSTB_LANEf_SET( reg_pma_ctrl, 0); 774 PHYMOD_IF_ERR_RETURN (MODIFY_RX_X4_PMA_CTL0r(pc, reg_pma_ctrl)); 775 } 776 return PHYMOD_E_NONE; 777 } 778 779 /** 780 @brief rx lane reset and enable of any particular lane 781 @param pc handle to current TSCF context (#PHYMOD_ST) 782 @param Get the configured reset lane. 783 @returns The value PHYMOD_E_NONE upon successful completion. 784 @details 785 This function read back control bit 786 */ 787 int tefmod16_rx_lane_control_get(PHYMOD_ST* pc, int *enable) /* RX_LANE_CONTROL */ 788 { 789 RX_X4_PMA_CTL0r_t reg_pma_ctrl; 790 791 TEFMOD16_DBG_IN_FUNC_INFO(pc); 792 RX_X4_PMA_CTL0r_CLR(reg_pma_ctrl); 793 PHYMOD_IF_ERR_RETURN (READ_RX_X4_PMA_CTL0r(pc, ®_pma_ctrl)); 794 *enable = RX_X4_PMA_CTL0r_RSTB_LANEf_GET( reg_pma_ctrl); 795 796 return PHYMOD_E_NONE; 797 } 798 799 800 801 /** 802 @brief Gets the TX And RX Polarity 803 @param pc handle to current TSCF context (#PHYMOD_ST) 804 @param tx_polarity Receives the TX polarity 805 @param rx_polarity Receives the RX polarity 806 @returns The value PHYMOD_E_NONE upon successful completion. 807 @details Gets the TX And RX Polarity from hardware. 808 809 */ 810 int tefmod16_tx_rx_polarity_get ( PHYMOD_ST *pc, uint32_t* tx_polarity, uint32_t* rx_polarity) 811 { 812 TLB_TX_TLB_TX_MISC_CFGr_t tx_pol_inv; 813 TLB_RX_TLB_RX_MISC_CFGr_t rx_pol_inv; 814 815 PHYMOD_IF_ERR_RETURN(READ_TLB_TX_TLB_TX_MISC_CFGr(pc, &tx_pol_inv)); 816 *tx_polarity = TLB_TX_TLB_TX_MISC_CFGr_TX_PMD_DP_INVERTf_GET(tx_pol_inv); 817 818 PHYMOD_IF_ERR_RETURN(READ_TLB_RX_TLB_RX_MISC_CFGr(pc, &rx_pol_inv)); 819 *rx_polarity = TLB_RX_TLB_RX_MISC_CFGr_RX_PMD_DP_INVERTf_GET(rx_pol_inv); 820 821 return PHYMOD_E_NONE; 822 } 823 824 /** 825 @brief Sets the TX And RX Polarity 826 @param pc handle to current TSCF context (#PHYMOD_ST) 827 @param tx_polarity Controls the TX polarity 828 @param rx_polarity Controls the RX polarity 829 @returns The value PHYMOD_E_NONE upon successful completion. 830 @details Sets the TX And RX Polarity 831 */ 832 int tefmod16_tx_rx_polarity_set ( PHYMOD_ST *pc, uint32_t tx_polarity, uint32_t rx_polarity) 833 { 834 TLB_TX_TLB_TX_MISC_CFGr_t tx_pol_inv; 835 TLB_RX_TLB_RX_MISC_CFGr_t rx_pol_inv; 836 837 TLB_TX_TLB_TX_MISC_CFGr_CLR(tx_pol_inv); 838 TLB_RX_TLB_RX_MISC_CFGr_CLR(rx_pol_inv); 839 840 TLB_TX_TLB_TX_MISC_CFGr_TX_PMD_DP_INVERTf_SET(tx_pol_inv, tx_polarity); 841 PHYMOD_IF_ERR_RETURN(MODIFY_TLB_TX_TLB_TX_MISC_CFGr(pc, tx_pol_inv)); 842 843 TLB_RX_TLB_RX_MISC_CFGr_RX_PMD_DP_INVERTf_SET(rx_pol_inv, rx_polarity); 844 PHYMOD_IF_ERR_RETURN(MODIFY_TLB_RX_TLB_RX_MISC_CFGr(pc, rx_pol_inv)); 845 846 return PHYMOD_E_NONE; 847 } 848 849 /** 850 @brief Read the 16 bit rev. id value etc. 851 @param pc handle to current TSCF context (#PHYMOD_ST) 852 @returns The value PHYMOD_E_NONE upon successful completion 853 @details Per Port PCS Init 854 */ 855 856 int tefmod16_trigger_speed_change(PHYMOD_ST* pc) 857 { 858 SC_X4_CTLr_t reg; 859 860 TEFMOD16_DBG_IN_FUNC_INFO(pc); 861 862 /* write 0 to the speed change */ 863 SC_X4_CTLr_CLR(reg); 864 PHYMOD_IF_ERR_RETURN(READ_SC_X4_CTLr(pc, ®)); 865 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(reg, 0); 866 PHYMOD_IF_ERR_RETURN(WRITE_SC_X4_CTLr(pc, reg)); 867 868 /* write 1 to the speed change. No need to read again before write*/ 869 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(reg, 1); 870 PHYMOD_IF_ERR_RETURN(WRITE_SC_X4_CTLr(pc, reg)); 871 872 return PHYMOD_E_NONE; 873 } 874 875 /*! 876 @brief Override TX lane output. 877 @param pc handle to current TSCF context (#PHYMOD_ST) 878 @param tx control lanes to disable 879 @returns PHYMOD_E_NONE if no errors. PHYMOD_ERROR else. 880 @details This function enables/disables, via override, transmission on a specific lane. No reset is 881 required to restart the transmission. Lane control is done through 'ovrr' and 'value' inputs. 882 <B>Set ovrr=0 & value=0 : No override of tx_disable to PMD lanes 0/1/2/3</B> 883 <B>Set ovrr=0 & value=1 : No override of tx_disable to PMD lanes 0/1/2/3</B> 884 <B>Set ovrr=1 & value=0 : Override tx_disable to inactive for PMD lanes 0/1/2/3</B> 885 <B>Set ovrr=1 & value=1 : Override tx_disable to active for PMD lanes 0/1/2/3</B> 886 */ 887 888 int tefmod16_tx_lane_disable (PHYMOD_ST* pc, int tx) 889 { 890 PMD_X4_CTLr_t PMD_X4_PMD_X4_CONTROLr_reg; 891 892 TEFMOD16_DBG_IN_FUNC_INFO(pc); 893 PMD_X4_CTLr_CLR(PMD_X4_PMD_X4_CONTROLr_reg); 894 895 PMD_X4_CTLr_TX_DISABLEf_SET(PMD_X4_PMD_X4_CONTROLr_reg, tx); 896 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X4_CTLr(pc, PMD_X4_PMD_X4_CONTROLr_reg)); 897 return PHYMOD_E_NONE; 898 } 899 900 /** 901 @brief Select the ILKN path and bypass TSCF PCS 902 @param pc handle to current TSCF context (#PHYMOD_ST) 903 @returns The value PHYMOD_E_NONE upon successful completion 904 @details This will enable ILKN path. PCS is set to bypass to relinquish PMD 905 control. Expect PMD to be programmed elsewhere. 906 */ 907 int tefmod16_init_pcs_ilkn(PHYMOD_ST* pc) /* INIT_PCS_ILKN */ 908 { 909 ILKN_CTL0r_t ILKN_CONTROL0r_reg; 910 911 TEFMOD16_DBG_IN_FUNC_INFO(pc); 912 913 PHYMOD_IF_ERR_RETURN(READ_ILKN_CTL0r(pc, &ILKN_CONTROL0r_reg)); 914 ILKN_CTL0r_CREDIT_ENf_SET(ILKN_CONTROL0r_reg, 1); 915 ILKN_CTL0r_ILKN_SELf_SET(ILKN_CONTROL0r_reg, 1); 916 PHYMOD_IF_ERR_RETURN(MODIFY_ILKN_CTL0r(pc, ILKN_CONTROL0r_reg)); 917 918 return PHYMOD_E_NONE; 919 } 920 921 /** 922 @brief Check if ILKN is set 923 @param pc handle to current TSCF context (#PHYMOD_ST), ilkn_set status 924 @returns The value PHYMOD_E_NONE upon successful completion 925 @details Check if ILKN is set, ilkn_set = 1 if it is set. 926 */ 927 int tefmod16_pcs_ilkn_chk(PHYMOD_ST* pc, int *ilkn_set) /* INIT_PCS_ILKN */ 928 { 929 ILKN_CTL0r_t ILKN_CONTROL0r_reg; 930 931 TEFMOD16_DBG_IN_FUNC_INFO(pc); 932 933 PHYMOD_IF_ERR_RETURN(READ_ILKN_CTL0r(pc, &ILKN_CONTROL0r_reg)); 934 *ilkn_set = ILKN_CTL0r_ILKN_SELf_GET(ILKN_CONTROL0r_reg); 935 936 return PHYMOD_E_NONE; 937 } 938 939 940 #ifdef _DV_TB_ 941 /*! 942 @brief Controls PMD reset pins irrespective of PCS is in Speed Control mode or not 943 aram pc handle to current TSCF context (#PHYMOD_ST) 944 @returns PHYMOD_E_NONE if no errors. PHYMOD_EERROR else. 945 @details Set the ::PHYMOD_ST::per_lane_control field of #PHYMOD_ST to <B>0 to 946 disable</B> PCS <B>1 to enable</B>. 947 */ 948 949 /* Ensure that tier2 and phymod control exist to access this function */ 950 int tefmod_pmd_lane_reset_bypass (PHYMOD_ST* pc, int pmd_reset_control) /* PMD_LANE_RESET_BYPASS */ 951 { 952 int cntl; 953 PMD_X4_OVRRr_t PMD_X4_OVERRIDEr_reg; 954 PMD_X4_CTLr_t PMD_X4_PMD_X4_CONTROLr_reg; 955 956 TEFMOD_DBG_IN_FUNC_INFO(pc); 957 958 cntl = pmd_reset_control & 0x10; 959 960 if (cntl) { 961 PMD_X4_OVRRr_CLR(PMD_X4_OVERRIDEr_reg); 962 PMD_X4_OVRRr_LN_DP_H_RSTB_OENf_SET(PMD_X4_OVERRIDEr_reg, 1); 963 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X4_OVRRr(pc, PMD_X4_OVERRIDEr_reg)); 964 965 PMD_X4_CTLr_CLR(PMD_X4_PMD_X4_CONTROLr_reg); 966 PMD_X4_CTLr_LN_DP_H_RSTBf_SET(PMD_X4_PMD_X4_CONTROLr_reg,0); 967 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X4_CTLr(pc, PMD_X4_PMD_X4_CONTROLr_reg)); 968 969 /* toggle added */ 970 PMD_X4_CTLr_CLR(PMD_X4_PMD_X4_CONTROLr_reg); 971 PMD_X4_CTLr_LN_DP_H_RSTBf_SET(PMD_X4_PMD_X4_CONTROLr_reg,1); 972 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X4_CTLr(pc, PMD_X4_PMD_X4_CONTROLr_reg)); 973 974 PMD_X4_OVRRr_CLR(PMD_X4_OVERRIDEr_reg); 975 PMD_X4_OVRRr_LN_DP_H_RSTB_OENf_SET(PMD_X4_OVERRIDEr_reg,0); 976 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X4_OVRRr(pc, PMD_X4_OVERRIDEr_reg)); 977 } else { 978 PMD_X4_OVRRr_CLR(PMD_X4_OVERRIDEr_reg); 979 PMD_X4_OVRRr_LN_DP_H_RSTB_OENf_SET(PMD_X4_OVERRIDEr_reg,0); 980 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X4_OVRRr(pc, PMD_X4_OVERRIDEr_reg)); 981 982 PMD_X4_CTLr_CLR(PMD_X4_PMD_X4_CONTROLr_reg); 983 PMD_X4_CTLr_LN_DP_H_RSTBf_SET(PMD_X4_PMD_X4_CONTROLr_reg,1); 984 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X4_CTLr(pc, PMD_X4_PMD_X4_CONTROLr_reg)); 985 } 986 987 cntl = pmd_reset_control & 0x1; 988 if (cntl) { 989 990 PMD_X1_OVRRr_CLR(PMD_X1_OVERRIDEr_reg); 991 PMD_X1_OVRRr_CORE_DP_H_RSTB_OENf_SET(PMD_X1_OVERRIDEr_reg,1); 992 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X1_OVRRr(pc, PMD_X1_OVERRIDEr_reg)); 993 994 PMD_X1_CTLr_CLR(PMD_X1_PMD_X1_CONTROLr_reg); 995 PMD_X1_CTLr_CORE_DP_H_RSTBf_SET(PMD_X1_PMD_X1_CONTROLr_reg,0); 996 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X1_CTLr(pc, PMD_X1_PMD_X1_CONTROLr_reg)); 997 998 /* toggle added */ 999 PMD_X1_CTLr_CLR(PMD_X1_PMD_X1_CONTROLr_reg); 1000 PMD_X1_CTLr_CORE_DP_H_RSTBf_SET(PMD_X1_PMD_X1_CONTROLr_reg,1); 1001 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X1_CTLr(pc, PMD_X1_PMD_X1_CONTROLr_reg)); 1002 1003 PMD_X1_OVRRr_CLR(PMD_X1_OVERRIDEr_reg); 1004 PMD_X1_OVRRr_CORE_DP_H_RSTB_OENf_SET(PMD_X1_OVERRIDEr_reg,0); 1005 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X1_OVRRr(pc, PMD_X1_OVERRIDEr_reg)); 1006 } else { 1007 PMD_X1_OVRRr_CLR(PMD_X1_OVERRIDEr_reg); 1008 PMD_X1_OVRRr_CORE_DP_H_RSTB_OENf_SET(PMD_X1_OVERRIDEr_reg,0); 1009 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X1_OVRRr(pc, PMD_X1_OVERRIDEr_reg)); 1010 1011 PMD_X1_CTLr_CLR(PMD_X1_PMD_X1_CONTROLr_reg); 1012 PMD_X1_CTLr_CORE_DP_H_RSTBf_SET(PMD_X1_PMD_X1_CONTROLr_reg,1); 1013 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X1_CTLr(pc, PMD_X1_PMD_X1_CONTROLr_reg)); 1014 } 1015 1016 SC_X4_CTLr_CLR(SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg); 1017 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg,0); 1018 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_CTLr(pc, SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg)); 1019 1020 SC_X4_CTLr_CLR(SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg); 1021 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg,1); 1022 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_CTLr(pc, SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg)); 1023 1024 return PHYMOD_E_NONE; 1025 } /* PMD_RESET_BYPASS */ 1026 1027 1028 int tefmod_pmd_core_reset_bypass(PHYMOD_ST* pc, int pmd_reset_control) { /* PMD_CORE_RESET_BYPASS */ 1029 1030 int cntl; 1031 PMD_X1_OVRRr_t PMD_X1_OVERRIDEr_reg; 1032 PMD_X1_CTLr_t PMD_X1_PMD_X1_CONTROLr_reg; 1033 1034 TEFMOD_DBG_IN_FUNC_INFO(pc); 1035 1036 cntl = pmd_reset_control & 0x1; 1037 1038 if (cntl) { 1039 1040 PMD_X1_OVRRr_CLR(PMD_X1_OVERRIDEr_reg); 1041 PMD_X1_OVRRr_CORE_DP_H_RSTB_OENf_SET(PMD_X1_OVERRIDEr_reg,1); 1042 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X1_OVRRr(pc, PMD_X1_OVERRIDEr_reg)); 1043 1044 PMD_X1_CTLr_CLR(PMD_X1_PMD_X1_CONTROLr_reg); 1045 PMD_X1_CTLr_CORE_DP_H_RSTBf_SET(PMD_X1_PMD_X1_CONTROLr_reg,1); 1046 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X1_CTLr(pc, PMD_X1_PMD_X1_CONTROLr_reg)); 1047 1048 } else { 1049 PMD_X1_OVRRr_CLR(PMD_X1_OVERRIDEr_reg); 1050 PMD_X1_OVRRr_CORE_DP_H_RSTB_OENf_SET(PMD_X1_OVERRIDEr_reg,0); 1051 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X1_OVRRr(pc, PMD_X1_OVERRIDEr_reg)); 1052 1053 PMD_X1_CTLr_CLR(PMD_X1_PMD_X1_CONTROLr_reg); 1054 PMD_X1_CTLr_CORE_DP_H_RSTBf_SET(PMD_X1_PMD_X1_CONTROLr_reg,1); 1055 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X1_CTLr(pc, PMD_X1_PMD_X1_CONTROLr_reg)); 1056 } 1057 1058 return PHYMOD_E_NONE; 1059 1060 } 1061 #endif 1062 1063 1064 /*! 1065 @brief Controls the setting/resetting of autoneg advertisement registers. 1066 @param pc handle to current TSCF context (#PHYMOD_ST) 1067 @param cl73_adv struct of type #tefmod16_an_adv_ability_t 1068 @returns PHYMOD_E_NONE if no errors. PHYMOD_EERROR else. 1069 @details 1070 TBD 1071 */ 1072 1073 #ifdef _DV_TB_ 1074 int tefmod16_autoneg_set(PHYMOD_ST* pc) /* AUTONEG_SET */ 1075 { 1076 uint16_t data; 1077 uint16_t cl73_bam_code; 1078 /* uint16_t tx_nonce; */ 1079 AN_X1_OUI_LWRr_t AN_X1_CONTROL_OUI_LOWERr_reg; 1080 AN_X1_OUI_UPRr_t AN_X1_CONTROL_OUI_UPPERr_reg; 1081 AN_X4_CL73_CTLSr_t AN_X4_ABILITIES_CL73_CONTROLSr_reg; 1082 AN_X4_LD_BAM_ABILr_t AN_X4_ABILITIES_LD_BAM_ABILITIESr_reg; 1083 AN_X4_LD_BASE_ABIL1r_t AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg; 1084 AN_X4_LD_BASE_ABIL0r_t AN_X4_ABILITIES_LD_BASE_ABILITIES_0r_reg; 1085 AN_X4_LD_UP1_ABIL0r_t AN_X4_ABILITIES_LD_UP1_ABILITIES_0r_reg; 1086 AN_X4_LD_UP1_ABIL1r_t AN_X4_ABILITIES_LD_UP1_ABILITIES_1r_reg; 1087 1088 AN_X1_BAM_SPD_PRI0r_t AN_X1_CONTROL_BAM_SPEED_PRI_0r_reg; 1089 AN_X1_BAM_SPD_PRI1r_t AN_X1_CONTROL_BAM_SPEED_PRI_1r_reg; 1090 AN_X1_BAM_SPD_PRI2r_t AN_X1_CONTROL_BAM_SPEED_PRI_2r_reg; 1091 AN_X1_BAM_SPD_PRI3r_t AN_X1_CONTROL_BAM_SPEED_PRI_3r_reg; 1092 AN_X1_BAM_SPD_PRI4r_t AN_X1_CONTROL_BAM_SPEED_PRI_4r_reg; 1093 AN_X1_IEEE_SPD_PRI1r_t AN_X1_IEEE_SPD_PRI1r_reg; 1094 1095 AN_X4_LD_BASE_ABIL2r_t AN_X4_LD_BASE_ABIL2r_reg; 1096 AN_X4_LD_BASE_ABIL3r_t AN_X4_LD_BASE_ABIL3r_reg; 1097 AN_X4_LD_BASE_ABIL4r_t AN_X4_LD_BASE_ABIL4r_reg; 1098 1099 1100 AN_X4_LD_FEC_BASEPAGE_ABILr_t AN_X4_LD_FEC_BASEPAGE_ABILr_reg; 1101 1102 TEFMOD16_DBG_IN_FUNC_INFO(pc); 1103 1104 /*****FEC Override ****/ 1105 tefmod16_an_fec_override(pc); 1106 1107 /***********Override programming ********/ 1108 AN_X4_CL73_CTLSr_CLR(AN_X4_ABILITIES_CL73_CONTROLSr_reg); 1109 data = pc->an_misc_ctrls; 1110 AN_X4_CL73_CTLSr_SET(AN_X4_ABILITIES_CL73_CONTROLSr_reg, data); 1111 /********Setting AN_X4_ABILITIES_cl73_controls 0xC186*****/ 1112 PHYMOD_IF_ERR_RETURN(WRITE_AN_X4_CL73_CTLSr(pc, AN_X4_ABILITIES_CL73_CONTROLSr_reg)); 1113 1114 if(pc->sw_an) { 1115 return PHYMOD_E_NONE; 1116 } 1117 AN_X1_OUI_LWRr_CLR(AN_X1_CONTROL_OUI_LOWERr_reg); 1118 AN_X1_OUI_LWRr_SET(AN_X1_CONTROL_OUI_LOWERr_reg, pc->oui & 0xffff); 1119 /********Setting AN_X1_OUI_LWR 0x9241*****/ 1120 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_OUI_LWRr(pc, AN_X1_CONTROL_OUI_LOWERr_reg)); 1121 1122 AN_X1_OUI_UPRr_CLR(AN_X1_CONTROL_OUI_UPPERr_reg); 1123 AN_X1_OUI_UPRr_SET(AN_X1_CONTROL_OUI_UPPERr_reg, (pc->oui >> 16) & 0xffff); 1124 /********Setting AN_X1_OUI_UPR 0x9240*****/ 1125 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_OUI_UPRr(pc, AN_X1_CONTROL_OUI_UPPERr_reg)); 1126 1127 1128 1129 1130 /********BAM Code********/ 1131 if(pc->an_type == TEFMOD16_CL73_BAM || pc->an_type == TEFMOD_HPAM) 1132 cl73_bam_code =3; 1133 else 1134 cl73_bam_code =0; 1135 1136 AN_X4_LD_BAM_ABILr_CLR(AN_X4_ABILITIES_LD_BAM_ABILITIESr_reg); 1137 AN_X4_LD_BAM_ABILr_CL73_BAM_CODEf_SET(AN_X4_ABILITIES_LD_BAM_ABILITIESr_reg, cl73_bam_code); 1138 /********Setting AN_X4_ABILITIES_ld_bam_abilities 0xC185*****/ 1139 PHYMOD_IF_ERR_RETURN(WRITE_AN_X4_LD_BAM_ABILr(pc, AN_X4_ABILITIES_LD_BAM_ABILITIESr_reg)); 1140 1141 1142 data=0; 1143 AN_X4_LD_BASE_ABIL1r_CLR(AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg); 1144 1145 /******* Base Abilities*****/ 1146 if( (pc->an_tech_ability >> TEFMOD16_ABILITY_1G ) & 1 ) { 1147 AN_X4_LD_BASE_ABIL1r_BASE_1G_KX1f_SET(AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg, 1); 1148 } 1149 if( (pc->an_tech_ability >> TEFMOD16_ABILITY_10G_KR ) & 1 ) { 1150 AN_X4_LD_BASE_ABIL1r_BASE_10G_KR1f_SET(AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg, 1); 1151 } 1152 if( (pc->an_tech_ability >> TEFMOD16_ABILITY_40G_KR4 ) & 1 ) { 1153 AN_X4_LD_BASE_ABIL1r_BASE_40G_KR4f_SET(AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg, 1); 1154 } 1155 if( (pc->an_tech_ability >> TEFMOD16_ABILITY_40G_CR4 ) & 1 ) { 1156 AN_X4_LD_BASE_ABIL1r_BASE_40G_CR4f_SET(AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg, 1); 1157 } 1158 if( (pc->an_tech_ability >> TEFMOD16_ABILITY_100G_KR4 ) & 1 ) { 1159 AN_X4_LD_BASE_ABIL1r_BASE_100G_KR4f_SET(AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg, 1); 1160 } 1161 if( (pc->an_tech_ability >> TEFMOD16_ABILITY_100G_CR4 ) & 1 ) { 1162 AN_X4_LD_BASE_ABIL1r_BASE_100G_CR4f_SET(AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg, 1); 1163 } 1164 1165 /******* Pause Settings ********/ 1166 if(pc->an_pause == TEFMOD16_NO_PAUSE) 1167 AN_X4_LD_BASE_ABIL1r_CL73_PAUSEf_SET(AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg, 0); 1168 if(pc->an_pause == TEFMOD16_ASYM_PAUSE) 1169 AN_X4_LD_BASE_ABIL1r_CL73_PAUSEf_SET(AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg, 1); 1170 if(pc->an_pause == TEFMOD16_SYM_PAUSE) 1171 AN_X4_LD_BASE_ABIL1r_CL73_PAUSEf_SET(AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg, 2); 1172 if(pc->an_pause == TEFMOD16_ASYM_SYM_PAUSE) 1173 AN_X4_LD_BASE_ABIL1r_CL73_PAUSEf_SET(AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg, 3); 1174 1175 /****** FEC Settings ********/ 1176 if(pc->an_fec == TEFMOD16_FEC_NOT_SUPRTD) 1177 AN_X4_LD_BASE_ABIL1r_FEC_REQf_SET(AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg, 0); 1178 if(pc->an_fec == TEFMOD16_FEC_SUPRTD_NOT_REQSTD) { 1179 AN_X4_LD_BASE_ABIL1r_FEC_REQf_SET(AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg, 1); 1180 } 1181 if(pc->an_fec == TEFMOD16_FEC_SUPRTD_REQSTD) { 1182 AN_X4_LD_BASE_ABIL1r_FEC_REQf_SET(AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg, 3); 1183 } 1184 1185 /****** Next page ******/ 1186 if(pc->cl73_bam_enable || pc->cl73_hpam_enable) 1187 AN_X4_LD_BASE_ABIL1r_NEXT_PAGEf_SET(AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg, 1); 1188 1189 1190 if(pc->an_rf == 1) { 1191 AN_X4_LD_BASE_ABIL1r_CL73_REMOTE_FAULTf_SET(AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg, 1); 1192 } 1193 1194 /***** Setting AN_X4_ABILITIES_ld_base_abilities_1 0xC184 *******/ 1195 PHYMOD_IF_ERR_RETURN(WRITE_AN_X4_LD_BASE_ABIL1r(pc, AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg)); 1196 1197 1198 data =0; 1199 1200 AN_X4_LD_BASE_ABIL0r_CLR(AN_X4_ABILITIES_LD_BASE_ABILITIES_0r_reg); 1201 /******tx nonce*****/ 1202 AN_X4_LD_BASE_ABIL0r_TX_NONCEf_SET(AN_X4_ABILITIES_LD_BASE_ABILITIES_0r_reg, pc->cl73_tx_nonce); 1203 1204 /****** Base selector *****/ 1205 AN_X4_LD_BASE_ABIL0r_CL73_BASE_SELECTORf_SET(AN_X4_ABILITIES_LD_BASE_ABILITIES_0r_reg, 1); 1206 1207 /***** Setting AN_X4_ABILITIES_ld_base_abilities_0 0xC183 *******/ 1208 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_LD_BASE_ABIL0r(pc, AN_X4_ABILITIES_LD_BASE_ABILITIES_0r_reg)); 1209 1210 AN_X4_LD_BASE_ABIL3r_CLR(AN_X4_LD_BASE_ABIL3r_reg); 1211 AN_X4_LD_BASE_ABIL3r_BASE_25G_KR1_SELf_SET(AN_X4_LD_BASE_ABIL3r_reg, (pc->base_25g_kr1 & 0x1f)); 1212 AN_X4_LD_BASE_ABIL3r_BASE_25G_KR1_ENf_SET(AN_X4_LD_BASE_ABIL3r_reg, (pc->base_25g_kr1 >> 16) & 1); 1213 AN_X4_LD_BASE_ABIL3r_BASE_25G_CR1_SELf_SET(AN_X4_LD_BASE_ABIL3r_reg, (pc->base_25g_cr1 & 0x1f)); 1214 AN_X4_LD_BASE_ABIL3r_BASE_25G_CR1_ENf_SET(AN_X4_LD_BASE_ABIL3r_reg, (pc->base_25g_cr1 >> 16) & 1); 1215 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_LD_BASE_ABIL3r(pc, AN_X4_LD_BASE_ABIL3r_reg )); 1216 1217 AN_X4_LD_BASE_ABIL4r_CLR(AN_X4_LD_BASE_ABIL4r_reg); 1218 AN_X4_LD_BASE_ABIL4r_BASE_25G_KRS1_SELf_SET(AN_X4_LD_BASE_ABIL4r_reg, (pc->base_25g_krs & 0x1f)); 1219 AN_X4_LD_BASE_ABIL4r_BASE_25G_KRS1_ENf_SET(AN_X4_LD_BASE_ABIL4r_reg, (pc->base_25g_krs >> 16) & 1); 1220 AN_X4_LD_BASE_ABIL4r_BASE_25G_CRS1_SELf_SET(AN_X4_LD_BASE_ABIL4r_reg, (pc->base_25g_crs & 0x1f)); 1221 AN_X4_LD_BASE_ABIL4r_BASE_25G_CRS1_ENf_SET(AN_X4_LD_BASE_ABIL4r_reg, (pc->base_25g_crs >> 16) & 1); 1222 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_LD_BASE_ABIL4r(pc, AN_X4_LD_BASE_ABIL4r_reg )); 1223 1224 /* 1225 * IEEE 50G Dual is not supported in TSCF16(TH2 and TD3) since it is removed from standard 1226 * 1227 AN_X4_LD_BASE_ABIL2r_CLR(AN_X4_LD_BASE_ABIL2r_reg); 1228 AN_X4_LD_BASE_ABIL2r_BASE_50G_KR2_SELf_SET(AN_X4_LD_BASE_ABIL2r_reg, (pc->base_50g_kr2 & 0x1f)); 1229 AN_X4_LD_BASE_ABIL2r_BASE_50G_KR2_ENf_SET(AN_X4_LD_BASE_ABIL2r_reg, (pc->base_50g_kr2 >> 16) & 1); 1230 AN_X4_LD_BASE_ABIL2r_BASE_50G_CR2_SELf_SET(AN_X4_LD_BASE_ABIL2r_reg, (pc->base_50g_cr2 & 0x1f)); 1231 AN_X4_LD_BASE_ABIL2r_BASE_50G_CR2_ENf_SET(AN_X4_LD_BASE_ABIL2r_reg, (pc->base_50g_cr2 >> 16) & 1); 1232 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_LD_BASE_ABIL2r(pc, AN_X4_LD_BASE_ABIL2r_reg )); 1233 */ 1234 1235 data =0; 1236 AN_X4_LD_UP1_ABIL0r_CLR(AN_X4_ABILITIES_LD_UP1_ABILITIES_0r_reg); 1237 /******* User page abilities*********/ 1238 if( (pc->an_tech_ability >> TEFMOD16_ABILITY_20G_KR2) & 1 ) 1239 AN_X4_LD_UP1_ABIL0r_BAM_20G_KR2f_SET(AN_X4_ABILITIES_LD_UP1_ABILITIES_0r_reg, 1); 1240 if( (pc->an_tech_ability >> TEFMOD16_ABILITY_20G_CR2) & 1 ) 1241 AN_X4_LD_UP1_ABIL0r_BAM_20G_CR2f_SET(AN_X4_ABILITIES_LD_UP1_ABILITIES_0r_reg, 1); 1242 if( (pc->an_tech_ability >> TEFMOD16_ABILITY_40G_KR2) & 1 ) 1243 AN_X4_LD_UP1_ABIL0r_BAM_40G_KR2f_SET(AN_X4_ABILITIES_LD_UP1_ABILITIES_0r_reg, 1); 1244 if( (pc->an_tech_ability >> TEFMOD16_ABILITY_40G_CR2) & 1 ) 1245 AN_X4_LD_UP1_ABIL0r_BAM_40G_CR2f_SET(AN_X4_ABILITIES_LD_UP1_ABILITIES_0r_reg, 1); 1246 if( (pc->an_tech_ability >> TEFMOD16_ABILITY_50G_KR2) & 1 ) 1247 AN_X4_LD_UP1_ABIL0r_BAM_50G_KR2f_SET(AN_X4_ABILITIES_LD_UP1_ABILITIES_0r_reg, 1); 1248 if( (pc->an_tech_ability >> TEFMOD16_ABILITY_50G_CR2) & 1 ) 1249 AN_X4_LD_UP1_ABIL0r_BAM_50G_CR2f_SET(AN_X4_ABILITIES_LD_UP1_ABILITIES_0r_reg, 1); 1250 /* 1251 * BAM 50G 4-lane is not supported in TSCF16(TH2 and TD3) chips. 1252 * 1253 if( (pc->an_tech_ability >> TEFMOD16_ABILITY_50G_KR4) & 1 ) 1254 AN_X4_LD_UP1_ABIL0r_BAM_50G_KR4f_SET(AN_X4_ABILITIES_LD_UP1_ABILITIES_0r_reg, 1); 1255 if( (pc->an_tech_ability >> TEFMOD16_ABILITY_50G_CR4) & 1 ) 1256 AN_X4_LD_UP1_ABIL0r_BAM_50G_CR4f_SET(AN_X4_ABILITIES_LD_UP1_ABILITIES_0r_reg, 1); 1257 */ 1258 AN_X4_LD_UP1_ABIL0r_BAM_HG2f_SET(AN_X4_ABILITIES_LD_UP1_ABILITIES_0r_reg, pc->an_higig2); 1259 1260 /******** Setting AN_X4_ABILITIES_ld_up1_abilities_0 0xC181******/ 1261 PHYMOD_IF_ERR_RETURN(WRITE_AN_X4_LD_UP1_ABIL0r(pc, AN_X4_ABILITIES_LD_UP1_ABILITIES_0r_reg)); 1262 1263 1264 data =0; 1265 AN_X4_LD_UP1_ABIL1r_CLR(AN_X4_ABILITIES_LD_UP1_ABILITIES_1r_reg); 1266 /******* User page abilities*********/ 1267 if( (pc->an_tech_ability >> TEFMOD16_ABILITY_20G_KR1) & 1 ) 1268 AN_X4_LD_UP1_ABIL1r_BAM_20G_KR1f_SET(AN_X4_ABILITIES_LD_UP1_ABILITIES_1r_reg, 1); 1269 if( (pc->an_tech_ability >> TEFMOD16_ABILITY_20G_CR1) & 1 ) 1270 AN_X4_LD_UP1_ABIL1r_BAM_20G_CR1f_SET(AN_X4_ABILITIES_LD_UP1_ABILITIES_1r_reg, 1); 1271 if( (pc->an_tech_ability >> TEFMOD16_ABILITY_25G_KR1) & 1 ) 1272 AN_X4_LD_UP1_ABIL1r_BAM_25G_KR1f_SET(AN_X4_ABILITIES_LD_UP1_ABILITIES_1r_reg, 1); 1273 if( (pc->an_tech_ability >> TEFMOD16_ABILITY_25G_CR1) & 1 ) 1274 AN_X4_LD_UP1_ABIL1r_BAM_25G_CR1f_SET(AN_X4_ABILITIES_LD_UP1_ABILITIES_1r_reg, 1); 1275 1276 AN_X4_LD_UP1_ABIL1r_CL91_REQf_SET(AN_X4_ABILITIES_LD_UP1_ABILITIES_1r_reg, pc->bam_cl91_fec); 1277 AN_X4_LD_UP1_ABIL1r_CL74_REQf_SET(AN_X4_ABILITIES_LD_UP1_ABILITIES_1r_reg, pc->bam_cl74_fec); 1278 1279 /******** Setting AN_X4_ABILITIES_ld_up1_abilities_1 0xC182******/ 1280 PHYMOD_IF_ERR_RETURN(WRITE_AN_X4_LD_UP1_ABIL1r(pc, AN_X4_ABILITIES_LD_UP1_ABILITIES_1r_reg)); 1281 1282 AN_X4_LD_FEC_BASEPAGE_ABILr_CLR(AN_X4_LD_FEC_BASEPAGE_ABILr_reg); 1283 AN_X4_LD_FEC_BASEPAGE_ABILr_RS_FEC_REQ_SELf_SET(AN_X4_LD_FEC_BASEPAGE_ABILr_reg, pc->rs_fec_req_sel); 1284 AN_X4_LD_FEC_BASEPAGE_ABILr_RS_FEC_REQ_ENf_SET(AN_X4_LD_FEC_BASEPAGE_ABILr_reg, pc->rs_fec_req_en); 1285 AN_X4_LD_FEC_BASEPAGE_ABILr_BASE_R_FEC_REQ_SELf_SET(AN_X4_LD_FEC_BASEPAGE_ABILr_reg, pc->base_r_fec_req_sel); 1286 AN_X4_LD_FEC_BASEPAGE_ABILr_BASE_R_FEC_REQ_ENf_SET(AN_X4_LD_FEC_BASEPAGE_ABILr_reg, pc->base_r_fec_req_en); 1287 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_LD_FEC_BASEPAGE_ABILr(pc, AN_X4_LD_FEC_BASEPAGE_ABILr_reg)); 1288 1289 AN_X1_BAM_SPD_PRI0r_CLR(AN_X1_CONTROL_BAM_SPEED_PRI_0r_reg); 1290 AN_X1_BAM_SPD_PRI1r_CLR(AN_X1_CONTROL_BAM_SPEED_PRI_1r_reg); 1291 AN_X1_BAM_SPD_PRI2r_CLR(AN_X1_CONTROL_BAM_SPEED_PRI_2r_reg); 1292 AN_X1_BAM_SPD_PRI3r_CLR(AN_X1_CONTROL_BAM_SPEED_PRI_3r_reg); 1293 AN_X1_BAM_SPD_PRI4r_CLR(AN_X1_CONTROL_BAM_SPEED_PRI_4r_reg); 1294 1295 data = pc->an_priority_remap_0; 1296 /********Setting AN_X1_BAM_SPD_PRI0 0x9242*****/ 1297 AN_X1_BAM_SPD_PRI0r_SET(AN_X1_CONTROL_BAM_SPEED_PRI_0r_reg, data); 1298 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_BAM_SPD_PRI0r(pc, AN_X1_CONTROL_BAM_SPEED_PRI_0r_reg)); 1299 1300 data = pc->an_priority_remap_1; 1301 AN_X1_BAM_SPD_PRI1r_SET(AN_X1_CONTROL_BAM_SPEED_PRI_1r_reg, data); 1302 /********Setting AN_X1_BAM_SPD_PRI1 0x9243*****/ 1303 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_BAM_SPD_PRI1r(pc, AN_X1_CONTROL_BAM_SPEED_PRI_1r_reg)); 1304 1305 data = pc->an_priority_remap_2; 1306 AN_X1_BAM_SPD_PRI2r_SET(AN_X1_CONTROL_BAM_SPEED_PRI_2r_reg, data); 1307 /********Setting AN_X1_BAM_SPD_PRI2 0x9244*****/ 1308 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_BAM_SPD_PRI2r(pc, AN_X1_CONTROL_BAM_SPEED_PRI_2r_reg)); 1309 1310 data = pc->an_priority_remap_3; 1311 AN_X1_BAM_SPD_PRI3r_SET(AN_X1_CONTROL_BAM_SPEED_PRI_3r_reg, data); 1312 /********Setting AN_X1_BAM_SPD_PRI3 0x9245*****/ 1313 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_BAM_SPD_PRI3r(pc, AN_X1_CONTROL_BAM_SPEED_PRI_3r_reg)); 1314 1315 data = pc->an_priority_remap_4; 1316 AN_X1_BAM_SPD_PRI4r_SET(AN_X1_CONTROL_BAM_SPEED_PRI_4r_reg, data); 1317 /********Setting AN_X1_BAM_SPD_PRI4 0x9246*****/ 1318 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_BAM_SPD_PRI4r(pc, AN_X1_CONTROL_BAM_SPEED_PRI_4r_reg)); 1319 1320 data = pc->an_priority_remap_5; 1321 AN_X1_IEEE_SPD_PRI1r_SET(AN_X1_IEEE_SPD_PRI1r_reg, data); 1322 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_IEEE_SPD_PRI1r(pc, AN_X1_IEEE_SPD_PRI1r_reg)); 1323 1324 return PHYMOD_E_NONE; 1325 } 1326 #endif 1327 1328 #ifdef _SDK_TEFMOD16_ 1329 1330 int tefmod16_autoneg_set(PHYMOD_ST* pc, tefmod16_an_adv_ability_t *cl73_adv) 1331 { 1332 uint32_t override_v; 1333 1334 AN_X4_LD_BASE_ABIL1r_t AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg; 1335 AN_X4_LD_BASE_ABIL0r_t AN_X4_ABILITIES_LD_BASE_ABILITIES_0r_reg; 1336 AN_X4_LD_UP1_ABIL0r_t AN_X4_ABILITIES_LD_UP1_ABILITIES_0r_reg; 1337 AN_X4_LD_UP1_ABIL1r_t AN_X4_ABILITIES_LD_UP1_ABILITIES_1r_reg; 1338 AN_X4_LD_BASE_ABIL3r_t AN_X4_LD_BASE_ABIL3r_reg; 1339 AN_X4_LD_BASE_ABIL4r_t AN_X4_LD_BASE_ABIL4r_reg; 1340 AN_X4_LD_FEC_BASEPAGE_ABILr_t AN_X4_LD_FEC_BASEPAGE_ABILr_reg; 1341 1342 AN_X4_LD_BASE_ABIL1r_CLR(AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg); 1343 1344 /******* Base Abilities 0xC1C4[5:0] *****/ 1345 if (cl73_adv->an_base_speed ) { 1346 AN_X4_LD_BASE_ABIL1r_SET(AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg, cl73_adv->an_base_speed & 0x3f); 1347 } 1348 1349 /******* Pause Settings 0xC1C4[7:6] ********/ 1350 if (cl73_adv->an_pause == TEFMOD16_NO_PAUSE) { 1351 AN_X4_LD_BASE_ABIL1r_CL73_PAUSEf_SET(AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg, 0); 1352 } 1353 if (cl73_adv->an_pause == TEFMOD16_SYMM_PAUSE) { 1354 AN_X4_LD_BASE_ABIL1r_CL73_PAUSEf_SET(AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg, 1); 1355 } 1356 if (cl73_adv->an_pause == TEFMOD16_ASYM_PAUSE) { 1357 AN_X4_LD_BASE_ABIL1r_CL73_PAUSEf_SET(AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg, 2); 1358 } 1359 if (cl73_adv->an_pause == TEFMOD16_ASYM_SYMM_PAUSE) { 1360 AN_X4_LD_BASE_ABIL1r_CL73_PAUSEf_SET(AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg, 3); 1361 } 1362 1363 /****** FEC Settings 0xC1C4 [9:8] ********/ 1364 if (cl73_adv->an_fec == TEFMOD16_FEC_NOT_SUPRTD) { 1365 AN_X4_LD_BASE_ABIL1r_FEC_REQf_SET(AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg, 0); 1366 } 1367 if (cl73_adv->an_fec == TEFMOD16_FEC_SUPRTD_NOT_REQSTD) { 1368 AN_X4_LD_BASE_ABIL1r_FEC_REQf_SET(AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg, 1); 1369 } 1370 if ((cl73_adv->an_fec & TEFMOD16_FEC_CL74_SUPRTD_REQSTD) || 1371 (cl73_adv->an_fec & TEFMOD16_FEC_CL91_SUPRTD_REQSTD)) { 1372 AN_X4_LD_BASE_ABIL1r_FEC_REQf_SET(AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg, 3); 1373 } 1374 1375 /***** Setting AN_X4_ABILITIES_ld_base_abilities_1 0xC1C4 *******/ 1376 PHYMOD_IF_ERR_RETURN(WRITE_AN_X4_LD_BASE_ABIL1r(pc, AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg)); 1377 1378 AN_X4_LD_BASE_ABIL3r_CLR(AN_X4_LD_BASE_ABIL3r_reg); 1379 AN_X4_LD_BASE_ABIL4r_CLR(AN_X4_LD_BASE_ABIL4r_reg); 1380 AN_X4_LD_FEC_BASEPAGE_ABILr_CLR(AN_X4_LD_FEC_BASEPAGE_ABILr_reg); 1381 AN_X4_LD_UP1_ABIL1r_CLR(AN_X4_ABILITIES_LD_UP1_ABILITIES_1r_reg); 1382 1383 /* check 25G IEEE base speed 0xC1C8 0xC1C9 */ 1384 if ((cl73_adv->an_base_speed >> TEFMOD16_CL73_25GBASE_KR1 ) & 1) { 1385 AN_X4_LD_BASE_ABIL3r_BASE_25G_KR1_ENf_SET(AN_X4_LD_BASE_ABIL3r_reg, 1); 1386 /* IEEE Technology Ability Field A10 25GBASE-KR */ 1387 AN_X4_LD_BASE_ABIL3r_BASE_25G_KR1_SELf_SET(AN_X4_LD_BASE_ABIL3r_reg, 10); 1388 } 1389 if ((cl73_adv->an_base_speed >> TEFMOD16_CL73_25GBASE_CR1 ) & 1) { 1390 AN_X4_LD_BASE_ABIL3r_BASE_25G_CR1_ENf_SET(AN_X4_LD_BASE_ABIL3r_reg, 1); 1391 /* IEEE Technology Ability Field A10 25GBASE-CR */ 1392 AN_X4_LD_BASE_ABIL3r_BASE_25G_CR1_SELf_SET(AN_X4_LD_BASE_ABIL3r_reg, 10); 1393 } 1394 if ((cl73_adv->an_base_speed >> TEFMOD16_CL73_25GBASE_KRS1 ) & 1) { 1395 AN_X4_LD_BASE_ABIL4r_BASE_25G_KRS1_ENf_SET(AN_X4_LD_BASE_ABIL4r_reg, 1); 1396 /* IEEE Technology Ability Field A9 25GBASE-KR-S */ 1397 AN_X4_LD_BASE_ABIL4r_BASE_25G_KRS1_SELf_SET(AN_X4_LD_BASE_ABIL4r_reg, 9); 1398 } 1399 if ((cl73_adv->an_base_speed >> TEFMOD16_CL73_25GBASE_CRS1 ) & 1) { 1400 AN_X4_LD_BASE_ABIL4r_BASE_25G_CRS1_ENf_SET(AN_X4_LD_BASE_ABIL4r_reg, 1); 1401 /* IEEE Technology Ability Field A9 25GBASE-CR-S */ 1402 AN_X4_LD_BASE_ABIL4r_BASE_25G_CRS1_SELf_SET(AN_X4_LD_BASE_ABIL4r_reg, 9); 1403 } 1404 PHYMOD_IF_ERR_RETURN(WRITE_AN_X4_LD_BASE_ABIL3r(pc, AN_X4_LD_BASE_ABIL3r_reg)); 1405 PHYMOD_IF_ERR_RETURN(WRITE_AN_X4_LD_BASE_ABIL4r(pc, AN_X4_LD_BASE_ABIL4r_reg)); 1406 1407 AN_X4_LD_FEC_BASEPAGE_ABILr_BASE_R_FEC_REQ_SELf_SET(AN_X4_LD_FEC_BASEPAGE_ABILr_reg, TEFMOD16_CL73_25GBASE_FEC_POS); 1408 AN_X4_LD_FEC_BASEPAGE_ABILr_BASE_R_FEC_REQ_ENf_SET(AN_X4_LD_FEC_BASEPAGE_ABILr_reg, 0); 1409 AN_X4_LD_FEC_BASEPAGE_ABILr_RS_FEC_REQ_SELf_SET(AN_X4_LD_FEC_BASEPAGE_ABILr_reg, TEFMOD16_CL73_25G_RS_FEC_POS); 1410 AN_X4_LD_FEC_BASEPAGE_ABILr_RS_FEC_REQ_ENf_SET(AN_X4_LD_FEC_BASEPAGE_ABILr_reg, 0); 1411 1412 /* check which fec to enable 0xC1CA */ 1413 if (cl73_adv->an_fec & TEFMOD16_FEC_CL74_SUPRTD_REQSTD) { 1414 AN_X4_LD_FEC_BASEPAGE_ABILr_BASE_R_FEC_REQ_ENf_SET(AN_X4_LD_FEC_BASEPAGE_ABILr_reg, 1); 1415 } 1416 if (cl73_adv->an_fec & TEFMOD16_FEC_CL91_SUPRTD_REQSTD) { 1417 AN_X4_LD_FEC_BASEPAGE_ABILr_RS_FEC_REQ_ENf_SET(AN_X4_LD_FEC_BASEPAGE_ABILr_reg, 1); 1418 } 1419 1420 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_LD_FEC_BASEPAGE_ABILr(pc, AN_X4_LD_FEC_BASEPAGE_ABILr_reg)); 1421 1422 /****** Base selector 0xC1C3[4:0] *****/ 1423 AN_X4_LD_BASE_ABIL0r_CLR(AN_X4_ABILITIES_LD_BASE_ABILITIES_0r_reg); 1424 AN_X4_LD_BASE_ABIL0r_CL73_BASE_SELECTORf_SET(AN_X4_ABILITIES_LD_BASE_ABILITIES_0r_reg, 1); 1425 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_LD_BASE_ABIL0r(pc, AN_X4_ABILITIES_LD_BASE_ABILITIES_0r_reg)); 1426 1427 /******* User page0 abilities 0xC1C1[9:6] and 0xC1C1[3:1] *********/ 1428 AN_X4_LD_UP1_ABIL0r_CLR(AN_X4_ABILITIES_LD_UP1_ABILITIES_0r_reg); 1429 AN_X4_LD_UP1_ABIL0r_SET(AN_X4_ABILITIES_LD_UP1_ABILITIES_0r_reg, cl73_adv->an_bam_speed & 0x3cf); 1430 PHYMOD_IF_ERR_RETURN(WRITE_AN_X4_LD_UP1_ABIL0r(pc, AN_X4_ABILITIES_LD_UP1_ABILITIES_0r_reg)); 1431 /******* User page0 abilities 0xC1C1[15]*********/ 1432 AN_X4_LD_UP1_ABIL0r_BAM_HG2f_SET(AN_X4_ABILITIES_LD_UP1_ABILITIES_0r_reg, cl73_adv->an_hg2); 1433 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_LD_UP1_ABIL0r(pc, AN_X4_ABILITIES_LD_UP1_ABILITIES_0r_reg)); 1434 1435 /******* User page1 abilities 0xC1C2[4:1] *********/ 1436 AN_X4_LD_UP1_ABIL1r_CLR(AN_X4_ABILITIES_LD_UP1_ABILITIES_1r_reg); 1437 AN_X4_LD_UP1_ABIL1r_SET(AN_X4_ABILITIES_LD_UP1_ABILITIES_1r_reg, cl73_adv->an_bam_speed1 & 0x1e); 1438 PHYMOD_IF_ERR_RETURN(WRITE_AN_X4_LD_UP1_ABIL1r(pc, AN_X4_ABILITIES_LD_UP1_ABILITIES_1r_reg)); 1439 1440 if ((cl73_adv->an_bam_speed) || (cl73_adv->an_bam_speed1)) { 1441 AN_X4_LD_UP1_ABIL1r_CLR(AN_X4_ABILITIES_LD_UP1_ABILITIES_1r_reg); 1442 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LD_UP1_ABIL1r(pc, &AN_X4_ABILITIES_LD_UP1_ABILITIES_1r_reg)); 1443 /******* User page abilities 0xC1C2[15:14] *********/ 1444 AN_X4_LD_UP1_ABIL1r_CL74_REQf_SET(AN_X4_ABILITIES_LD_UP1_ABILITIES_1r_reg, 0x1); 1445 /******* User page abilities 0xC1C2[13:12] *********/ 1446 AN_X4_LD_UP1_ABIL1r_CL91_REQf_SET(AN_X4_ABILITIES_LD_UP1_ABILITIES_1r_reg, 0x1); 1447 if (cl73_adv->an_fec & TEFMOD16_FEC_CL74_SUPRTD_REQSTD) { 1448 AN_X4_LD_UP1_ABIL1r_CL74_REQf_SET(AN_X4_ABILITIES_LD_UP1_ABILITIES_1r_reg, 0x3); 1449 } 1450 if (cl73_adv->an_fec & TEFMOD16_FEC_CL91_SUPRTD_REQSTD) { 1451 AN_X4_LD_UP1_ABIL1r_CL91_REQf_SET(AN_X4_ABILITIES_LD_UP1_ABILITIES_1r_reg, 0x3); 1452 } 1453 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_LD_UP1_ABIL1r(pc, AN_X4_ABILITIES_LD_UP1_ABILITIES_1r_reg)); 1454 } 1455 1456 /* 1457 * if cl72_en = 1, use default setting, no overrides 1458 * if cl72_en = 0, then override to disable cl72 1459 */ 1460 if ((cl73_adv->an_cl72 & 0x1) == 1) { 1461 override_v = ((OVERRIDE_CL72_EN_DIS<<16) | 1); 1462 tefmod16_set_override_1(pc, 0, override_v); 1463 } else { 1464 override_v = ((OVERRIDE_CL72_EN<<16) | 0); 1465 tefmod16_set_override_1(pc, 0, override_v); 1466 } 1467 1468 return PHYMOD_E_NONE; 1469 } 1470 1471 #endif /* _SDK_TEFMOD16_ */ 1472 1473 1474 /*! 1475 @brief To get autoneg advertisement registers. 1476 @param pc handle to current TSCF context (#PHYMOD_ST) 1477 @returns PHYMOD_E_NONE if no errors. PHYMOD_EERROR else. 1478 @details 1479 */ 1480 int tefmod16_autoneg_get(PHYMOD_ST* pc) /* AUTONEG_GET */ 1481 { 1482 TEFMOD16_DBG_IN_FUNC_INFO(pc); 1483 /* TBD */ 1484 return PHYMOD_E_NONE; 1485 } 1486 1487 /*! 1488 @brief Controls the setting/resetting of autoneg ability and enabling/disabling 1489 @param pc handle to current TSCF context (#PHYMOD_ST) 1490 @returns PHYMOD_E_NONE if no errors. PHYMOD_EERROR else. 1491 1492 @details 1493 This function programs auto-negotiation (AN) modes for the TEF. It can 1494 enable/disable clause37/clause73/BAM autonegotiation capabilities. Call this 1495 function once for combo mode and once per lane in independent lane mode. 1496 1497 The autonegotiation mode is indicated by setting an_control as required. 1498 */ 1499 1500 #ifdef _DV_TB_ 1501 int tefmod16_autoneg_control(PHYMOD_ST* pc) 1502 { 1503 uint16_t cl73_bam_enable, cl73_hpam_enable, cl73_enable; 1504 uint16_t cl73_nonce_match_over, cl73_nonce_match_val ; 1505 uint16_t bam_to_hpam_ad_en; 1506 uint16_t num_advertised_lanes; 1507 AN_X4_CL73_CFGr_t AN_X4_ABILITIES_CL73_CFGr_reg; 1508 AN_X4_WAIT_ACK_COMPLETEr_t AN_X4_WAIT_ACK_COMPLETEr_reg; 1509 1510 TEFMOD16_DBG_IN_FUNC_INFO(pc); 1511 cl73_enable = pc->an_en; 1512 cl73_nonce_match_over = pc->nonce_match_override; 1513 cl73_nonce_match_val = pc->nonce_match_val; 1514 cl73_bam_enable = pc->cl73_bam_enable; 1515 cl73_hpam_enable = pc->cl73_hpam_enable; 1516 bam_to_hpam_ad_en = pc->bam_to_hpam_ad_en; 1517 num_advertised_lanes = pc->num_advertised_lanes; 1518 1519 /****Added for cl73_disable test case ****/ 1520 #if defined (_DV_TB_) 1521 if(pc->override_an_en_as_disable==1) { 1522 cl73_enable =0; 1523 } 1524 #endif 1525 1526 AN_X4_WAIT_ACK_COMPLETEr_CLR(AN_X4_WAIT_ACK_COMPLETEr_reg); 1527 AN_X4_WAIT_ACK_COMPLETEr_WAIT_FOR_ACK_ENf_SET(AN_X4_WAIT_ACK_COMPLETEr_reg, pc->sw_an_wait_for_ack); 1528 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_WAIT_ACK_COMPLETEr(pc, AN_X4_WAIT_ACK_COMPLETEr_reg)); 1529 1530 AN_X4_CL73_CFGr_CLR(AN_X4_ABILITIES_CL73_CFGr_reg); 1531 1532 AN_X4_CL73_CFGr_NUM_ADVERTISED_LANESf_SET(AN_X4_ABILITIES_CL73_CFGr_reg, num_advertised_lanes); 1533 1534 AN_X4_CL73_CFGr_CL73_NONCE_MATCH_VALf_SET(AN_X4_ABILITIES_CL73_CFGr_reg, cl73_nonce_match_val); 1535 1536 AN_X4_CL73_CFGr_CL73_NONCE_MATCH_OVERf_SET(AN_X4_ABILITIES_CL73_CFGr_reg, cl73_nonce_match_over); 1537 1538 if(pc->sw_an) { 1539 cl73_enable = 0; 1540 } 1541 AN_X4_CL73_CFGr_CL73_ENABLEf_SET(AN_X4_ABILITIES_CL73_CFGr_reg, cl73_enable); 1542 1543 1544 AN_X4_CL73_CFGr_CL73_HPAM_ENABLEf_SET(AN_X4_ABILITIES_CL73_CFGr_reg, cl73_hpam_enable); 1545 1546 AN_X4_CL73_CFGr_CL73_BAM_ENABLEf_SET(AN_X4_ABILITIES_CL73_CFGr_reg, cl73_bam_enable); 1547 1548 AN_X4_CL73_CFGr_BAM_TO_HPAM_AD_ENf_SET(AN_X4_ABILITIES_CL73_CFGr_reg, bam_to_hpam_ad_en); 1549 1550 AN_X4_CL73_CFGr_AD_TO_CL73_ENf_SET(AN_X4_ABILITIES_CL73_CFGr_reg, pc->hpam_to_cl73_ad_en); 1551 /*********Setting AN_X4_ABILITIES_cl73_cfg 0xC180 ******/ 1552 PHYMOD_IF_ERR_RETURN(WRITE_AN_X4_CL73_CFGr(pc, AN_X4_ABILITIES_CL73_CFGr_reg)); 1553 1554 return PHYMOD_E_NONE; 1555 } /* tefmod16_autoneg_control(PHYMOD_ST* pc) */ 1556 #endif 1557 1558 #ifdef _SDK_TEFMOD16_ 1559 int tefmod16_autoneg_control(PHYMOD_ST* pc, tefmod16_an_control_t *an_control) 1560 { 1561 phymod_access_t pa_copy; 1562 uint16_t num_advertised_lanes, cl73_bam_enable ; 1563 int start_lane, num_of_lane, i; 1564 uint16_t cl73_hpam_enable, cl73_enable; 1565 uint16_t cl73_next_page; 1566 uint16_t cl73_restart ; 1567 uint16_t cl73_bam_code; 1568 uint16_t msa_overrides; 1569 uint32_t plldiv_r_val = 0; 1570 MAIN0_SETUPr_t reg_setup; 1571 AN_X4_CL73_CFGr_t AN_X4_CL73_CFGr_reg; 1572 AN_X1_CL73_ERRr_t AN_X1_CL73_ERRr_reg; 1573 AN_X4_CL73_CTLSr_t AN_X4_CL73_CTLSr_reg; 1574 AN_X4_LD_BASE_ABIL1r_t AN_X4_LD_BASE_ABIL1r_reg; 1575 AN_X4_LD_BAM_ABILr_t AN_X4_ABILITIES_LD_BAM_ABILITIESr_reg; 1576 1577 PHYMOD_IF_ERR_RETURN 1578 (phymod_util_lane_config_get(pc, &start_lane, &num_of_lane)); 1579 PHYMOD_MEMCPY(&pa_copy, pc, sizeof(pa_copy)); 1580 1581 TEFMOD16_DBG_IN_FUNC_INFO(pc); 1582 num_advertised_lanes = an_control->num_lane_adv; 1583 cl73_bam_code = 0x0; 1584 cl73_bam_enable = 0x0; 1585 cl73_hpam_enable = 0x0; 1586 cl73_enable = 0x0; 1587 cl73_next_page = 0x0; 1588 cl73_restart = 0x0; 1589 msa_overrides = 0x0; 1590 1591 switch (an_control->an_type) { 1592 case TEFMOD16_AN_MODE_CL73: 1593 cl73_restart = an_control->enable; 1594 cl73_enable = an_control->enable; 1595 break; 1596 case TEFMOD16_AN_MODE_CL73_BAM: 1597 cl73_restart = an_control->enable; 1598 cl73_enable = an_control->enable; 1599 cl73_bam_enable = an_control->enable; 1600 cl73_bam_code = 0x3; 1601 cl73_next_page = 0x1; 1602 break; 1603 case TEFMOD16_AN_MODE_CL73_MSA: 1604 cl73_restart = an_control->enable; 1605 cl73_enable = an_control->enable; 1606 cl73_bam_enable = an_control->enable; 1607 cl73_bam_code = 0x3; 1608 cl73_next_page = 0x1; 1609 msa_overrides = 0x1; 1610 break; 1611 case TEFMOD16_AN_MODE_MSA: 1612 cl73_restart = an_control->enable; 1613 cl73_enable = an_control->enable; 1614 cl73_bam_enable = an_control->enable; 1615 cl73_bam_code = 0x3; 1616 cl73_next_page = 0x1; 1617 msa_overrides = 0x1; 1618 break; 1619 case TEFMOD16_AN_MODE_HPAM: 1620 cl73_restart = an_control->enable; 1621 cl73_enable = an_control->enable; 1622 cl73_hpam_enable = an_control->enable; 1623 cl73_next_page = 0x1; 1624 break; 1625 default: 1626 return PHYMOD_E_FAIL; 1627 break; 1628 } 1629 if(msa_overrides == 0x1) { 1630 tefmod16_an_oui_t oui; 1631 oui.oui = 0x6a737d; 1632 oui.oui_override_bam73_adv = 0x1; 1633 oui.oui_override_bam73_det = 0x1; 1634 oui.oui_override_hpam_adv = 0x0; 1635 oui.oui_override_hpam_det = 0x0; 1636 PHYMOD_IF_ERR_RETURN(tefmod16_an_oui_set(pc, oui)); 1637 PHYMOD_IF_ERR_RETURN(tefmod16_an_msa_mode_set(pc, msa_overrides)); 1638 } 1639 /* RESET Speed Change bit */ 1640 if(an_control->enable){ 1641 tefmod16_disable_set(pc); 1642 } 1643 1644 MAIN0_SETUPr_CLR(reg_setup); 1645 if(an_control->enable){ 1646 /*next we decide which cl73_vco to set based on the current VCO */ 1647 PHYMOD_IF_ERR_RETURN(tefmod16_get_plldiv(pc, &plldiv_r_val)); 1648 1649 if(plldiv_r_val<=4) { /* pll_div <= 132; for 156MHz only */ 1650 MAIN0_SETUPr_CL73_VCOf_SET(reg_setup, 0); 1651 } else { 1652 MAIN0_SETUPr_CL73_VCOf_SET(reg_setup, 1); 1653 } 1654 PHYMOD_IF_ERR_RETURN(MODIFY_MAIN0_SETUPr(pc, reg_setup)); 1655 } 1656 1657 1658 /*0x9251 AN_X1_TIMERS_cl73_error*/ 1659 AN_X1_CL73_ERRr_CLR(AN_X1_CL73_ERRr_reg); 1660 if(an_control->an_type == TEFMOD16_AN_MODE_CL73) { 1661 AN_X1_CL73_ERRr_SET(AN_X1_CL73_ERRr_reg, 0); 1662 } else if(an_control->an_type == TEFMOD16_AN_MODE_HPAM){ 1663 AN_X1_CL73_ERRr_SET(AN_X1_CL73_ERRr_reg, 0xfff0); 1664 } else if (an_control->an_type == TEFMOD16_AN_MODE_CL73_BAM) { 1665 AN_X1_CL73_ERRr_SET(AN_X1_CL73_ERRr_reg, 0x1a10); 1666 } 1667 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_CL73_ERRr(pc, AN_X1_CL73_ERRr_reg)); 1668 1669 1670 /*need to set cl73 BAM next page 0xc1c4 probably*/ 1671 AN_X4_LD_BASE_ABIL1r_CLR(AN_X4_LD_BASE_ABIL1r_reg); 1672 AN_X4_LD_BASE_ABIL1r_NEXT_PAGEf_SET(AN_X4_LD_BASE_ABIL1r_reg, cl73_next_page & 1); 1673 PHYMOD_IF_ERR_RETURN ( MODIFY_AN_X4_LD_BASE_ABIL1r(pc, AN_X4_LD_BASE_ABIL1r_reg)); 1674 1675 /* Writing bam_code 0xc1c5*/ 1676 AN_X4_LD_BAM_ABILr_CLR(AN_X4_ABILITIES_LD_BAM_ABILITIESr_reg); 1677 AN_X4_LD_BAM_ABILr_CL73_BAM_CODEf_SET(AN_X4_ABILITIES_LD_BAM_ABILITIESr_reg, cl73_bam_code); 1678 PHYMOD_IF_ERR_RETURN(WRITE_AN_X4_LD_BAM_ABILr(pc, AN_X4_ABILITIES_LD_BAM_ABILITIESr_reg)); 1679 1680 /* 0xc1c6 */ 1681 AN_X4_CL73_CTLSr_CLR(AN_X4_CL73_CTLSr_reg); 1682 AN_X4_CL73_CTLSr_PD_KX_ENf_SET(AN_X4_CL73_CTLSr_reg, an_control->pd_kx_en & 0x1); 1683 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_CL73_CTLSr(pc, AN_X4_CL73_CTLSr_reg)); 1684 1685 /* 0xc1c0 */ 1686 AN_X4_CL73_CFGr_CLR(AN_X4_CL73_CFGr_reg); 1687 AN_X4_CL73_CFGr_CL73_ENABLEf_SET(AN_X4_CL73_CFGr_reg,0); 1688 AN_X4_CL73_CFGr_CL73_AN_RESTARTf_SET(AN_X4_CL73_CFGr_reg,0); 1689 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_CL73_CFGr(pc, AN_X4_CL73_CFGr_reg)); 1690 1691 /*Setting X4 abilities*/ 1692 AN_X4_CL73_CFGr_CLR(AN_X4_CL73_CFGr_reg); 1693 AN_X4_CL73_CFGr_CL73_BAM_ENABLEf_SET(AN_X4_CL73_CFGr_reg,cl73_bam_enable); 1694 AN_X4_CL73_CFGr_CL73_HPAM_ENABLEf_SET(AN_X4_CL73_CFGr_reg,cl73_hpam_enable); 1695 AN_X4_CL73_CFGr_CL73_ENABLEf_SET(AN_X4_CL73_CFGr_reg,cl73_enable); 1696 AN_X4_CL73_CFGr_CL73_AN_RESTARTf_SET(AN_X4_CL73_CFGr_reg,cl73_restart); 1697 if(an_control->an_property_type & TEFMOD16_AN_PROPERTY_ENABLE_HPAM_TO_CL73_AUTO ) 1698 AN_X4_CL73_CFGr_AD_TO_CL73_ENf_SET(AN_X4_CL73_CFGr_reg,0x1); 1699 else 1700 AN_X4_CL73_CFGr_AD_TO_CL73_ENf_SET(AN_X4_CL73_CFGr_reg,0x0); 1701 /* AN_X4_CL73_CFGr_HPAM_TO_CL73_AUTO_ENABLEf_SET(AN_X4_CL73_CFGr_reg,0x0); */ 1702 1703 if(an_control->an_property_type & TEFMOD16_AN_PROPERTY_ENABLE_CL73_BAM_TO_HPAM_AUTO ) 1704 AN_X4_CL73_CFGr_BAM_TO_HPAM_AD_ENf_SET(AN_X4_CL73_CFGr_reg,0x1); 1705 else 1706 AN_X4_CL73_CFGr_BAM_TO_HPAM_AD_ENf_SET(AN_X4_CL73_CFGr_reg,0x0); 1707 1708 AN_X4_CL73_CFGr_NUM_ADVERTISED_LANESf_SET(AN_X4_CL73_CFGr_reg,num_advertised_lanes); 1709 1710 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_CL73_CFGr(pc, AN_X4_CL73_CFGr_reg)); 1711 1712 /* if an is enabled, the restart bit needs to be cleared */ 1713 1714 if (an_control->enable) { 1715 AN_X4_CL73_CFGr_CLR(AN_X4_CL73_CFGr_reg); 1716 AN_X4_CL73_CFGr_CL73_AN_RESTARTf_SET(AN_X4_CL73_CFGr_reg,0); 1717 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_CL73_CFGr(pc, AN_X4_CL73_CFGr_reg)); 1718 } 1719 1720 /* Disable the cl72 , when AN port is disabled. */ 1721 if (an_control->cl72_config_allowed) { 1722 if(an_control->enable == 0) { 1723 if(an_control->num_lane_adv == 1) { 1724 num_of_lane = 2; 1725 } else if (an_control->num_lane_adv == 2) { 1726 num_of_lane = 4; 1727 } else { 1728 num_of_lane = 1; 1729 } 1730 for (i = (num_of_lane-1); i >= 0; i--) { 1731 pa_copy.lane_mask = 0x1 << (i + start_lane); 1732 tefmod16_clause72_control(&pa_copy, 0); 1733 } 1734 } 1735 } 1736 1737 return PHYMOD_E_NONE; 1738 } /* temod_autoneg_control */ 1739 #endif 1740 1741 /* internal supporting function */ 1742 int tefmod16_get_plldiv(PHYMOD_ST* pc, uint32_t *plldiv_r_val) 1743 { 1744 PLL_CAL_CTL7r_t PLL_CAL_CTL7r_reg; 1745 /* read back plldiv */ 1746 1747 TEFMOD16_DBG_IN_FUNC_INFO(pc); 1748 PHYMOD_IF_ERR_RETURN (READ_PLL_CAL_CTL7r(pc, &PLL_CAL_CTL7r_reg)); 1749 1750 *plldiv_r_val = PLL_CAL_CTL7r_PLL_MODEf_GET(PLL_CAL_CTL7r_reg); 1751 1752 return PHYMOD_E_NONE; 1753 } 1754 1755 /* to update port_mode_select value. If the update warrants a pll reset, 1756 then return accData=1, otherwise return accData=0. The update shall 1757 support flex port technology. Called forced speed modes */ 1758 1759 int tefmod16_update_port_mode_select(PHYMOD_ST* pc, tefmod16_port_type_t port_type, int master_port, int tsc_clk_freq_pll_by_48, int pll_reset_en) 1760 { 1761 MAIN0_SETUPr_t MAIN0_SETUPr_reg; 1762 MAIN0_SPD_CTLr_t MAIN0_SPEED_CTRLr_reg; 1763 1764 TEFMOD16_DBG_IN_FUNC_INFO(pc); 1765 1766 #ifdef _DV_TB_ 1767 pc->accData = 0; 1768 if(pc->tsc_touched == 1) { 1769 return PHYMOD_E_NONE; 1770 } 1771 #endif 1772 1773 PHYMOD_IF_ERR_RETURN (READ_MAIN0_SETUPr(pc, &MAIN0_SETUPr_reg)); 1774 1775 if((port_type ==TEFMOD16_MULTI_PORT) ||(port_type ==TEFMOD16_DXGXS)|| 1776 (port_type ==TEFMOD16_SINGLE_PORT)||(port_type ==TEFMOD16_TRI1_PORT)|| 1777 (port_type ==TEFMOD16_TRI2_PORT)){ 1778 } else { 1779 PHYMOD_DEBUG_ERROR(("%-22s: ERROR port_type=%0d undefined\n", __func__, port_type)); 1780 return PHYMOD_E_FAIL; 1781 } 1782 1783 MAIN0_SETUPr_CLR(MAIN0_SETUPr_reg); 1784 MAIN0_SETUPr_PORT_MODE_SELf_SET(MAIN0_SETUPr_reg, port_type); 1785 /* Leave port mode to quad in an_en */ 1786 1787 MAIN0_SETUPr_MASTER_PORT_NUMf_SET(MAIN0_SETUPr_reg, master_port); 1788 1789 PHYMOD_IF_ERR_RETURN (MODIFY_MAIN0_SETUPr(pc, MAIN0_SETUPr_reg)); 1790 1791 PHYMOD_IF_ERR_RETURN(READ_MAIN0_SETUPr(pc, &MAIN0_SETUPr_reg)); 1792 1793 1794 MAIN0_SETUPr_CLR(MAIN0_SETUPr_reg); 1795 1796 MAIN0_SETUPr_TSC_CLK_CTRLf_SET(MAIN0_SETUPr_reg, tsc_clk_freq_pll_by_48); 1797 1798 PHYMOD_IF_ERR_RETURN (MODIFY_MAIN0_SETUPr(pc, MAIN0_SETUPr_reg)); 1799 1800 PHYMOD_IF_ERR_RETURN(READ_MAIN0_SETUPr(pc, &MAIN0_SETUPr_reg)); 1801 1802 MAIN0_SPD_CTLr_CLR(MAIN0_SPEED_CTRLr_reg); 1803 MAIN0_SPD_CTLr_PLL_RESET_ENf_SET(MAIN0_SPEED_CTRLr_reg, pll_reset_en); 1804 PHYMOD_IF_ERR_RETURN (MODIFY_MAIN0_SPD_CTLr(pc, MAIN0_SPEED_CTRLr_reg)); 1805 1806 return PHYMOD_E_NONE; 1807 } 1808 1809 /*! 1810 @brief Init routine sets various operating modes of TEF. 1811 @param pc handle to current TSCF context (#PHYMOD_ST) 1812 @param refclk Reference clock 1813 @param plldiv PLL Divider value 1814 @param port_type Port type as in enum #tefmod16_port_type_t 1815 @param master_port master port (which controls the PLL) 1816 @param master_port master port (which controls the PLL) 1817 @param tsc_clk_freq_pll_by_48 TBD 1818 @param pll_reset_en TBD 1819 @returns PHYMOD_E_NONE if successful. PHYMOD_E_ERROR else. 1820 @details 1821 This function is called once per TEF. It cannot be called multiple times 1822 and should be called immediately after reset. Elements of #PHYMOD_ST should be 1823 initialized to required values prior to calling this function. The following 1824 sub-configurations are performed here. 1825 1826 \li Read the revision Id. 1827 \li Set reference clock (0x9000[15:13]) 1828 \li Set pll divider for VCO setting (0x9000[12, 11:8]). This is a function of max_speed. 1829 \li Port mode select single/dual/quad combo lane mode 1830 \li PMA/PMD mux/demux (lane swap) (0x9004[15:0]) 1831 \li Load Firmware. (In MDK/SDK this is done externally. The platform provides a 1832 method to load firmware. TEFMod cannot load firmware via MDIO.) 1833 */ 1834 1835 int tefmod16_set_port_mode(PHYMOD_ST* pc, int refclk, int plldiv, tefmod16_port_type_t port_type, int master_port, int tsc_clk_freq_pll_by_48, int pll_reset_en) 1836 { 1837 uint16_t dataref; 1838 MAIN0_SETUPr_t MAIN0_SETUPr_reg; 1839 1840 TEFMOD16_DBG_IN_FUNC_INFO(pc); 1841 tefmod16_update_port_mode_select(pc, port_type, master_port, tsc_clk_freq_pll_by_48, pll_reset_en); 1842 1843 switch(refclk) { 1844 case 25 : dataref=main0_refClkSelect_clk_25MHz; break; 1845 case 50 : dataref=main0_refClkSelect_clk_50Mhz; break; 1846 case 100: dataref=main0_refClkSelect_clk_100MHz; break; 1847 case 106: dataref=main0_refClkSelect_clk_106p25Mhz; break; 1848 case 125: dataref=main0_refClkSelect_clk_125MHz; break; 1849 case 156: dataref=main0_refClkSelect_clk_156p25MHz; break; 1850 case 161: dataref=main0_refClkSelect_clk_161p25Mhz; break; 1851 case 187: dataref=main0_refClkSelect_clk_187p5MHz; break; 1852 default : dataref=main0_refClkSelect_clk_156p25MHz; 1853 } 1854 1855 MAIN0_SETUPr_CLR(MAIN0_SETUPr_reg); 1856 1857 MAIN0_SETUPr_REFCLK_SELf_SET(MAIN0_SETUPr_reg, dataref); 1858 1859 switch(plldiv) { 1860 /* 1861 case 32 : datapll=MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_div32; break; 1862 case 36 : datapll=MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_div36; break; 1863 case 40 : datapll=MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_div40; break; 1864 case 42 : datapll=MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_div42; break; 1865 case 48 : datapll=MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_div48; break; 1866 case 50 : datapll=MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_div50; break; 1867 case 52 : datapll=MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_div52; break; 1868 case 54 : datapll=MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_div54; break; 1869 case 60 : datapll=MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_div60; break; 1870 case 64 : datapll=MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_div64; break; 1871 case 66 : datapll=MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_div66; break; 1872 case 68 : datapll=MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_div68; break; 1873 case 70 : datapll=MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_div70; break; 1874 case 80 : datapll=MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_div80; break; 1875 case 92 : datapll=MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_div92; break; 1876 case 100: datapll=MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_div100; break; 1877 default : datapll=MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_div40; 1878 */ 1879 } 1880 PHYMOD_IF_ERR_RETURN (MODIFY_MAIN0_SETUPr(pc, MAIN0_SETUPr_reg)); 1881 return PHYMOD_E_NONE; 1882 } /* tefmod16_set_port_mode(PHYMOD_ST* pc) */ 1883 1884 #ifdef _DV_TB_ 1885 /*! 1886 @brief Sets the core for autoneg 1887 @param pc handle to current TSCF context (#PHYMOD_ST) 1888 @returns The value PHYMOD_E_NONE upon successful completion 1889 This function sets the tsc core for autoneg generic settings. 1890 If per_lane_control=TEFMOD16_CTL_AN_CHIP_INIT(0x1) PLL and RX path are reset. 1891 If per_lane_control=TEFMOD16_CTL_AN_MODE_INIT(0x2) PLL and RX path are not reset. 1892 */ 1893 int tefmod16_set_an_port_mode(PHYMOD_ST* pc) /* SET_AN_PORT_MODE */ 1894 { 1895 #ifdef _DV_TB_ 1896 uint16_t ignore_link_timer_period; 1897 uint16_t tx_disable_timer_period; 1898 uint16_t link_fail_inhibit_no_cl72_period ; 1899 uint16_t link_fail_inhibit_cl72_period ; 1900 #endif 1901 #ifdef TSCF_GEN1 1902 uint16_t mld_swap_count; 1903 #endif 1904 uint16_t single_port_mode; 1905 uint16_t ref_clk_sel; 1906 uint16_t new_port_mode_sel; 1907 uint16_t modify_port_mode; 1908 uint16_t port_mode_sel_reg; 1909 1910 MAIN0_SETUPr_t MAIN0_SETUPr_reg; 1911 AN_X1_IGNORE_LNK_TMRr_t AN_X1_TIMERS_IGNORE_LINK_TIMERr_reg; 1912 MAIN0_TICK_CTL0r_t MAIN0_TICK_CONTROL_0r_reg; 1913 MAIN0_TICK_CTL1r_t MAIN0_TICK_CONTROL_1r_reg; 1914 AN_X1_CL73_DME_LOCKr_t AN_X1_TIMERS_CL73_DME_LOCKr_reg; 1915 AN_X1_PD_SD_TMRr_t AN_X1_TIMERS_PD_SD_TIMERr_reg; 1916 AN_X1_CL73_BRK_LNKr_t AN_X1_TIMERS_CL73_BREAK_LINKr_reg; 1917 AN_X1_CL73_ERRr_t AN_X1_TIMERS_CL73_ERRORr_reg; 1918 AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72r_t AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_NOT_CL72r_reg; 1919 AN_X1_LNK_FAIL_INHBT_TMR_CL72r_t AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_CL72r_reg; 1920 TX_X4_CRED0r_t TX_X4_CREDIT0_CREDIT0r_reg; 1921 #ifdef TSCF_GEN1 1922 TX_X2_MLD_SWP_CNTr_t TX_X2_CONTROL0_MLD_SWAP_COUNTr_reg; 1923 /* CL82_RX_AM_TMRr_t CL82_SHARED_CL82_RX_AM_TIMERr_reg; 1924 #else 1925 CL82_AM_TMRr_t CL82_SHARED_CL82_AM_TIMERr_reg; */ 1926 #endif 1927 1928 TEFMOD16_DBG_IN_FUNC_INFO(pc); 1929 modify_port_mode = 0; 1930 1931 #if defined (_DV_TB_) 1932 ignore_link_timer_period = 0xf; 1933 /* tick_denominator = 0x1; 1934 tick_numerator_lower = 0x0; 1935 tick_override = 0x1; 1936 tick_numerator_upper = 0x8; 1937 tx_disable_timer_period = 0x5; 1938 cl73_error_timer_period = 0x64; */ 1939 link_fail_inhibit_no_cl72_period = 0x64; 1940 link_fail_inhibit_cl72_period = 0xfff; 1941 1942 #endif 1943 /* cl48_dswin64b66b = 0x1; 1944 cl48_dswin8b10b = 0x7; */ 1945 #ifdef TSCF_GEN1 1946 mld_swap_count = 0xfffc; 1947 #endif 1948 /* am_timer_init_rx_val = 0x3fff; */ 1949 single_port_mode = 0x0; 1950 ref_clk_sel = 0x0; 1951 1952 1953 1954 PHYMOD_IF_ERR_RETURN (READ_MAIN0_SETUPr(pc, &MAIN0_SETUPr_reg)); 1955 port_mode_sel_reg = MAIN0_SETUPr_PORT_MODE_SELf_GET(MAIN0_SETUPr_reg); 1956 1957 MAIN0_SETUPr_CLR(MAIN0_SETUPr_reg); 1958 1959 /* if ((pc-> an_type == TEFMOD16_HPAM) | (pc-> an_type == TEFMOD_CL73_BAM)) { 1960 #if defined (_DV_TB_) 1961 cl73_error_timer_period = 0x64; 1962 #endif 1963 } */ 1964 1965 if ((pc-> an_type == TEFMOD16_CL73) | (pc-> an_type == TEFMOD_HPAM) | 1966 (pc-> an_type == TEFMOD16_CL73_BAM)) { 1967 1968 ref_clk_sel = main0_refClkSelect_clk_156p25MHz; 1969 if(pc->tsc_touched != 1) 1970 single_port_mode = 1; 1971 1972 /* plldiv = 66; */ 1973 } 1974 1975 if(pc->per_lane_control == TEFMOD16_CTL_AN_CHIP_INIT) { 1976 MAIN0_SETUPr_REFCLK_SELf_SET(MAIN0_SETUPr_reg, ref_clk_sel); 1977 } 1978 MAIN0_SETUPr_SINGLE_PORT_MODEf_SET(MAIN0_SETUPr_reg, single_port_mode); 1979 1980 1981 if(port_mode_sel_reg == TEFMOD16_DXGXS) { 1982 modify_port_mode = 1; 1983 if(pc->this_lane == 0) { 1984 new_port_mode_sel = TEFMOD16_TRI1_PORT; 1985 } 1986 else if(pc->this_lane == 2) { 1987 new_port_mode_sel = TEFMOD16_TRI2_PORT; 1988 } 1989 } 1990 if(port_mode_sel_reg == TEFMOD16_TRI1_PORT) { 1991 if(pc->this_lane == 2) { 1992 modify_port_mode = 1; 1993 new_port_mode_sel = TEFMOD16_MULTI_PORT; 1994 } 1995 } 1996 if(port_mode_sel_reg == TEFMOD16_TRI2_PORT) { 1997 if(pc->this_lane == 0) { 1998 modify_port_mode = 1; 1999 new_port_mode_sel = TEFMOD16_MULTI_PORT; 2000 } 2001 } 2002 if(port_mode_sel_reg == TEFMOD16_SINGLE_PORT) { 2003 modify_port_mode = 1; 2004 new_port_mode_sel = TEFMOD16_MULTI_PORT; 2005 } 2006 if(modify_port_mode == 1) { 2007 MAIN0_SETUPr_PORT_MODE_SELf_SET(MAIN0_SETUPr_reg, new_port_mode_sel); 2008 } 2009 2010 /*mask |= MAIN0_SETUP_PORT_MODE_SEL_MASK; */ 2011 2012 MAIN0_SETUPr_CL72_ENf_SET(MAIN0_SETUPr_reg, pc->cl72_en); 2013 2014 MAIN0_SETUPr_CL73_VCOf_SET(MAIN0_SETUPr_reg, pc->cl73_vco); 2015 2016 /* 0x9000 */ 2017 PHYMOD_IF_ERR_RETURN (MODIFY_MAIN0_SETUPr(pc, MAIN0_SETUPr_reg)); 2018 2019 pc->port_type = TEFMOD16_MULTI_PORT; 2020 2021 /* XXXX: need to do sleep sal_usleep(1000); */ 2022 2023 #if defined (_DV_TB_) 2024 /* ignore_link_timer_period 0x925c */ 2025 if(pc->ignore_link_timer_period !=0) ignore_link_timer_period = pc->ignore_link_timer_period; 2026 AN_X1_IGNORE_LNK_TMRr_CLR(AN_X1_TIMERS_IGNORE_LINK_TIMERr_reg); 2027 AN_X1_IGNORE_LNK_TMRr_IGNORE_LINK_TIMER_PERIODf_SET(AN_X1_TIMERS_IGNORE_LINK_TIMERr_reg, ignore_link_timer_period); 2028 2029 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X1_IGNORE_LNK_TMRr(pc, AN_X1_TIMERS_IGNORE_LINK_TIMERr_reg)); 2030 #endif 2031 2032 2033 #if defined (_DV_TB_) 2034 /* set tick values 0x9008 x1 (only in sim) */ 2035 MAIN0_TICK_CTL0r_CLR(MAIN0_TICK_CONTROL_0r_reg); 2036 MAIN0_TICK_CTL0r_TICK_DENOMINATORf_SET(MAIN0_TICK_CONTROL_0r_reg, pc->tick_denominator); 2037 2038 MAIN0_TICK_CTL0r_TICK_NUMERATOR_LOWERf_SET(MAIN0_TICK_CONTROL_0r_reg, pc->tick_numerator_lower); 2039 2040 PHYMOD_IF_ERR_RETURN (MODIFY_MAIN0_TICK_CTL0r(pc, MAIN0_TICK_CONTROL_0r_reg)); 2041 2042 /* set tick values 0x9007 (only in sim) */ 2043 MAIN0_TICK_CTL1r_CLR(MAIN0_TICK_CONTROL_1r_reg); 2044 MAIN0_TICK_CTL1r_TICK_OVERRIDEf_SET(MAIN0_TICK_CONTROL_1r_reg, pc->tick_override); 2045 MAIN0_TICK_CTL1r_TICK_NUMERATOR_UPPERf_SET(MAIN0_TICK_CONTROL_1r_reg, pc->tick_numerator_upper); 2046 2047 PHYMOD_IF_ERR_RETURN (MODIFY_MAIN0_TICK_CTL1r(pc, MAIN0_TICK_CONTROL_1r_reg)); 2048 2049 /*TBD::0x9255 AN_X1_TIMERS_cl73_dme_lock*/ 2050 AN_X1_CL73_DME_LOCKr_CLR(AN_X1_TIMERS_CL73_DME_LOCKr_reg); 2051 AN_X1_CL73_DME_LOCKr_SET(AN_X1_TIMERS_CL73_DME_LOCKr_reg, 100); 2052 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_CL73_DME_LOCKr(pc, AN_X1_TIMERS_CL73_DME_LOCKr_reg)); 2053 2054 /*TBD::0x9253 AN_X1_TIMERS_pd_sd_timer*/ 2055 AN_X1_PD_SD_TMRr_CLR(AN_X1_TIMERS_PD_SD_TIMERr_reg); 2056 AN_X1_PD_SD_TMRr_SET(AN_X1_TIMERS_PD_SD_TIMERr_reg, 50); 2057 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_PD_SD_TMRr(pc, AN_X1_TIMERS_PD_SD_TIMERr_reg)); 2058 /* set cl73 break link timer values 0x9253 (only in sim) need a production value */ 2059 if(pc->tx_disable_timer_period !=0) tx_disable_timer_period = pc->tx_disable_timer_period; 2060 if(pc->tsc_touched ==0) { 2061 AN_X1_CL73_BRK_LNKr_CLR(AN_X1_TIMERS_CL73_BREAK_LINKr_reg); 2062 AN_X1_CL73_BRK_LNKr_CL73_BREAK_TIMER_PERIODf_SET(AN_X1_TIMERS_CL73_BREAK_LINKr_reg, tx_disable_timer_period); 2063 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X1_CL73_BRK_LNKr(pc, AN_X1_TIMERS_CL73_BREAK_LINKr_reg)); 2064 } 2065 2066 2067 2068 /* set cl73 error timer period values 0x9254 write once per core (timeout timer) */ 2069 /*if(pc->cl73_error_timer_period !=0) cl73_error_timer_period = pc->cl73_error_timer_period;*/ 2070 AN_X1_CL73_ERRr_CLR(AN_X1_TIMERS_CL73_ERRORr_reg); 2071 AN_X1_CL73_ERRr_CL73_ERROR_TIMER_PERIODf_SET(AN_X1_TIMERS_CL73_ERRORr_reg, pc->cl73_error_timer_period); 2072 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X1_CL73_ERRr(pc, AN_X1_TIMERS_CL73_ERRORr_reg)); 2073 2074 /**** 0x9256*******/ 2075 if(pc->link_fail_inhibit_no_cl72_period !=0) link_fail_inhibit_no_cl72_period = pc->link_fail_inhibit_no_cl72_period; 2076 2077 AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72r_CLR(AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_NOT_CL72r_reg); 2078 AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72r_LINK_FAIL_INHIBIT_TIMER_NCL72_PERIODf_SET(AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_NOT_CL72r_reg, link_fail_inhibit_no_cl72_period); 2079 2080 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72r(pc, AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_NOT_CL72r_reg)); 2081 2082 /**** 0x9255*******/ 2083 if(pc->link_fail_inhibit_cl72_period !=0) link_fail_inhibit_cl72_period = pc->link_fail_inhibit_cl72_period; 2084 AN_X1_LNK_FAIL_INHBT_TMR_CL72r_CLR(AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_CL72r_reg); 2085 AN_X1_LNK_FAIL_INHBT_TMR_CL72r_LINK_FAIL_INHIBIT_TIMER_CL72_PERIODf_SET(AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_CL72r_reg, link_fail_inhibit_cl72_period); 2086 2087 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_LNK_FAIL_INHBT_TMR_CL72r(pc, AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_CL72r_reg)); 2088 #endif 2089 2090 2091 /* MLD swap_count 0xa000 */ 2092 #ifdef TSCF_GEN1 2093 2094 #if defined (_DV_TB_) 2095 mld_swap_count = 0xffc; 2096 #else 2097 mld_swap_count = 0xfffc; 2098 #endif 2099 2100 TX_X2_MLD_SWP_CNTr_CLR(TX_X2_CONTROL0_MLD_SWAP_COUNTr_reg); 2101 TX_X2_MLD_SWP_CNTr_MLD_SWAP_COUNTf_SET(TX_X2_CONTROL0_MLD_SWAP_COUNTr_reg, mld_swap_count); 2102 2103 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X2_MLD_SWP_CNTr(pc, TX_X2_CONTROL0_MLD_SWAP_COUNTr_reg)); 2104 #endif 2105 2106 /* cl82 shared rc_am_timer 0x9123 */ 2107 2108 /*#if defined (_DV_TB_) 2109 am_timer_init_rx_val = 0x3ff; 2110 #else 2111 am_timer_init_rx_val = 0x3fff; 2112 #endif */ 2113 2114 2115 2116 /* clear credtis 0xc100, 0xc104 */ 2117 TX_X4_CRED0r_CLR(TX_X4_CREDIT0_CREDIT0r_reg); 2118 TX_X4_CRED0r_SET(TX_X4_CREDIT0_CREDIT0r_reg, 0); 2119 PHYMOD_IF_ERR_RETURN (MODIFY_TX_X4_CRED0r(pc, TX_X4_CREDIT0_CREDIT0r_reg)); 2120 2121 return PHYMOD_E_NONE; 2122 } /* tefmod16_set_an_port_mode(PHYMOD_ST* pc) */ 2123 #endif 2124 2125 2126 /*! 2127 @brief Sets loopback mode from Tx to Rx at PCS/PMS parallel interface. (gloop). 2128 @param pc handle to current TSCF context (#PHYMOD_ST) 2129 @param pcs_gloop_en Enable or disable PCS loopback. 2130 @param starting_lane first of multiple lanes if in multi lane ports 2131 @param num_lanes Number of lanes to configure if in multi lane ports 2132 @returns The value PHYMOD_E_NONE upon successful completion 2133 @details 2134 This function sets the TX-to-RX digital loopback mode, which is set 2135 independently for each lane at the PCS/PMS parallel interface. If the port in 2136 question contains multiple lanes we specify the starting and the lane count and 2137 all those lanes are configured to loopback mode 2138 2139 The 1st, 2nd, 3rd and 4th byte of 'lane' input arg. is associated with lanes 0, 2140 1, 2, and 3 respectively. The bits of each byte control their lanes as follows. 2141 2142 \li 0:1 : Enable TX->RX loopback 2143 \li 0:0 : Disable TX-RX loopback 2144 2145 Note that this function can program <B>multiple lanes simultaneously</B>. 2146 As an example, to enable gloop on all lanes and enable TX on lane 0 only, 2147 set lane to 0x01010103 2148 */ 2149 2150 int tefmod16_tx_loopback_control(PHYMOD_ST* pc, int pcs_gloop_en, int starting_lane, int num_lanes) /* TX_LOOPBACK_CONTROL */ 2151 { 2152 MAIN0_LPBK_CTLr_t MAIN0_LOOPBACK_CONTROLr_reg; 2153 PMD_X4_OVRRr_t PMD_X4_OVERRIDEr_reg; 2154 PMD_X4_CTLr_t PMD_X4_PMD_X4_CONTROLr_reg; 2155 SC_X4_CTLr_t SC_X4_CTLr_reg; 2156 uint16_t lane_mask, i, data, tmp_data; 2157 2158 TEFMOD16_DBG_IN_FUNC_INFO(pc); 2159 2160 MAIN0_LPBK_CTLr_CLR(MAIN0_LOOPBACK_CONTROLr_reg); 2161 READ_MAIN0_LPBK_CTLr(pc, &MAIN0_LOOPBACK_CONTROLr_reg); 2162 tmp_data = MAIN0_LPBK_CTLr_LOCAL_PCS_LOOPBACK_ENABLEf_GET(MAIN0_LOOPBACK_CONTROLr_reg); 2163 2164 /* write 0 to the speed change */ 2165 SC_X4_CTLr_CLR(SC_X4_CTLr_reg); 2166 PHYMOD_IF_ERR_RETURN(READ_SC_X4_CTLr(pc, &SC_X4_CTLr_reg)); 2167 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(SC_X4_CTLr_reg, 0); 2168 PHYMOD_IF_ERR_RETURN(WRITE_SC_X4_CTLr(pc, SC_X4_CTLr_reg)); 2169 2170 lane_mask = 0; 2171 data = 0; 2172 2173 for (i = 0; i < num_lanes; i++) { 2174 if (!PHYMOD_LANEPBMP_MEMBER(pc->lane_mask, starting_lane + i)) { 2175 continue; 2176 } 2177 lane_mask |= 1 << (starting_lane + i); 2178 data |= pcs_gloop_en << (starting_lane + i); 2179 } 2180 2181 tmp_data &= ~lane_mask; 2182 tmp_data |= data; 2183 2184 MAIN0_LPBK_CTLr_LOCAL_PCS_LOOPBACK_ENABLEf_SET(MAIN0_LOOPBACK_CONTROLr_reg, tmp_data); 2185 PHYMOD_IF_ERR_RETURN(MODIFY_MAIN0_LPBK_CTLr(pc, MAIN0_LOOPBACK_CONTROLr_reg)); 2186 2187 /* signal_detect and rx_lock */ 2188 PMD_X4_OVRRr_CLR(PMD_X4_OVERRIDEr_reg); 2189 if (pcs_gloop_en) { 2190 PMD_X4_OVRRr_RX_LOCK_OVRDf_SET(PMD_X4_OVERRIDEr_reg, 1); 2191 PMD_X4_OVRRr_SIGNAL_DETECT_OVRDf_SET(PMD_X4_OVERRIDEr_reg, 1); 2192 PMD_X4_OVRRr_TX_DISABLE_OENf_SET(PMD_X4_OVERRIDEr_reg, 1); 2193 } else { 2194 PMD_X4_OVRRr_RX_LOCK_OVRDf_SET(PMD_X4_OVERRIDEr_reg, 0); 2195 PMD_X4_OVRRr_SIGNAL_DETECT_OVRDf_SET(PMD_X4_OVERRIDEr_reg, 0); 2196 PMD_X4_OVRRr_TX_DISABLE_OENf_SET(PMD_X4_OVERRIDEr_reg, 0); 2197 } 2198 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X4_OVRRr(pc, PMD_X4_OVERRIDEr_reg)); 2199 2200 /* set tx_disable */ 2201 PMD_X4_CTLr_CLR(PMD_X4_PMD_X4_CONTROLr_reg); 2202 PMD_X4_CTLr_TX_DISABLEf_SET(PMD_X4_PMD_X4_CONTROLr_reg, 1); 2203 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X4_CTLr(pc, PMD_X4_PMD_X4_CONTROLr_reg)); 2204 2205 /* write 1 to the speed change */ 2206 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(SC_X4_CTLr_reg, 1); 2207 PHYMOD_IF_ERR_RETURN(WRITE_SC_X4_CTLr(pc, SC_X4_CTLr_reg)); 2208 2209 return PHYMOD_E_NONE; 2210 } /* tefmod16_tx_loopback_control */ 2211 2212 2213 /*! 2214 @brief Set remote loopback mode for GMII, cl49, aggregate(XAUI) and R2 modes. 2215 @param pc handle to current TSCF context (#PHYMOD_ST) 2216 @param pcs_rloop_en controls rloop enable or disable 2217 @returns The value PHYMOD_E_NONE upon successful completion 2218 @details 2219 This function sets the remote loopback (RX-to-TX) mode for one lane at a time, 2220 where the lane is indicated by the field. To enable remote loopback, set 2221 pcs_rloop_en to 1; to disable remote loopback, set the it to 0. 2222 */ 2223 2224 int tefmod16_rx_loopback_control(PHYMOD_ST* pc, int pcs_rloop_en) 2225 { 2226 MAIN0_LPBK_CTLr_t MAIN0_LOOPBACK_CONTROLr_reg; 2227 DSC_CDR_CTL2r_t DSC_C_CDR_CONTROL_2r_reg; 2228 TX_PI_CTL0r_t TX_PI_PMD_COM_TX_PI_PMD_COM_CONTROL_0r_reg; 2229 2230 TEFMOD16_DBG_IN_FUNC_INFO(pc); 2231 /* remote device is set in rloop */ 2232 #ifdef _DV_TB_ 2233 /* remote device is set in rloop */ 2234 if ((pc->unit) == 2) { 2235 #endif 2236 MAIN0_LPBK_CTLr_CLR(MAIN0_LOOPBACK_CONTROLr_reg); 2237 MAIN0_LPBK_CTLr_REMOTE_PCS_LOOPBACK_ENABLEf_SET(MAIN0_LOOPBACK_CONTROLr_reg, pcs_rloop_en); 2238 PHYMOD_IF_ERR_RETURN(MODIFY_MAIN0_LPBK_CTLr(pc, MAIN0_LOOPBACK_CONTROLr_reg)); 2239 2240 /* set Tx_PI */ 2241 DSC_CDR_CTL2r_CLR(DSC_C_CDR_CONTROL_2r_reg); 2242 DSC_CDR_CTL2r_TX_PI_LOOP_TIMING_SRC_SELf_SET(DSC_C_CDR_CONTROL_2r_reg, 1); 2243 2244 PHYMOD_IF_ERR_RETURN(MODIFY_DSC_CDR_CTL2r(pc, DSC_C_CDR_CONTROL_2r_reg)); 2245 2246 /* NEW 16NM */ 2247 TX_PI_CTL0r_CLR(TX_PI_PMD_COM_TX_PI_PMD_COM_CONTROL_0r_reg); 2248 TX_PI_CTL0r_TX_PI_ENf_SET(TX_PI_PMD_COM_TX_PI_PMD_COM_CONTROL_0r_reg,1); 2249 2250 PHYMOD_IF_ERR_RETURN(MODIFY_TX_PI_CTL0r(pc, TX_PI_PMD_COM_TX_PI_PMD_COM_CONTROL_0r_reg)); 2251 2252 #ifdef _DV_TB_ 2253 } 2254 #endif 2255 return PHYMOD_E_NONE; 2256 } /* tefmod16_rx_loopback_control */ 2257 2258 int tefmod16_tx_loopback_get(PHYMOD_ST* pc, uint32_t *enable) /* TX_LOOPBACK_get */ 2259 { 2260 MAIN0_LPBK_CTLr_t loopReg; 2261 READ_MAIN0_LPBK_CTLr(pc, &loopReg); 2262 *enable = MAIN0_LPBK_CTLr_LOCAL_PCS_LOOPBACK_ENABLEf_GET(loopReg); 2263 2264 return PHYMOD_E_NONE; 2265 } 2266 2267 /** 2268 @brief PMD per lane reset 2269 @param pc handle to current TSCF context (#PHYMOD_ST) 2270 @returns The value PHYMOD_E_NONE upon successful completion 2271 @details Per lane PMD ln_rst and ln_dp_rst by writing to PMD_X4_CONTROL in pcs space 2272 */ 2273 int tefmod16_pmd_x4_reset(PHYMOD_ST* pc) /* PMD_X4_RESET */ 2274 { 2275 PMD_X4_CTLr_t reg_pmd_x4_ctrl; 2276 2277 TEFMOD16_DBG_IN_FUNC_INFO(pc); 2278 PMD_X4_CTLr_CLR(reg_pmd_x4_ctrl); 2279 PMD_X4_CTLr_LN_H_RSTBf_SET(reg_pmd_x4_ctrl,0); 2280 PMD_X4_CTLr_LN_DP_H_RSTBf_SET(reg_pmd_x4_ctrl,0); 2281 PHYMOD_IF_ERR_RETURN (MODIFY_PMD_X4_CTLr(pc, reg_pmd_x4_ctrl)); 2282 2283 PMD_X4_CTLr_CLR(reg_pmd_x4_ctrl); 2284 PMD_X4_CTLr_LN_H_RSTBf_SET(reg_pmd_x4_ctrl,1); 2285 PMD_X4_CTLr_LN_DP_H_RSTBf_SET(reg_pmd_x4_ctrl,1); 2286 PHYMOD_IF_ERR_RETURN (MODIFY_PMD_X4_CTLr(pc, reg_pmd_x4_ctrl)); 2287 2288 return PHYMOD_E_NONE; 2289 } 2290 2291 /** 2292 @brief PMD per lane reset get 2293 @param pc handle to current TSCF context (#PHYMOD_ST) 2294 @returns The value PHYMOD_E_NONE upon successful completion 2295 @details Per lane PMD ln_rst and ln_dp_rst by writing to PMD_X4_CONTROL in pcs space 2296 */ 2297 int tefmod16_pmd_x4_reset_get(PHYMOD_ST* pc, int *is_in_reset) /* PMD_X4_RESET */ 2298 { 2299 PMD_X4_CTLr_t reg_pmd_x4_ctrl; 2300 2301 TEFMOD16_DBG_IN_FUNC_INFO(pc); 2302 PMD_X4_CTLr_CLR(reg_pmd_x4_ctrl); 2303 PHYMOD_IF_ERR_RETURN (READ_PMD_X4_CTLr(pc, ®_pmd_x4_ctrl)); 2304 2305 if(PMD_X4_CTLr_LN_H_RSTBf_GET(reg_pmd_x4_ctrl) && 2306 PMD_X4_CTLr_LN_DP_H_RSTBf_GET(reg_pmd_x4_ctrl)) { 2307 *is_in_reset = 0 ; 2308 } else { 2309 *is_in_reset = 1 ; 2310 } 2311 2312 return PHYMOD_E_NONE; 2313 } 2314 2315 /** 2316 @brief Set Per lane OS mode set in PMD 2317 @param pc handle to current TSCF context (#PHYMOD_ST) 2318 @param spd_intf speed type #tefmod16_spd_intfc_type_t 2319 @param os_mode over sample rate. 2320 @returns The value PHYMOD_E_NONE upon successful completion 2321 @details Per Port PMD Init 2322 2323 */ 2324 int tefmod16_pmd_osmode_set(PHYMOD_ST* pc, tefmod16_spd_intfc_type_t spd_intf, phymod_ref_clk_t refclk, int os_mode) /* INIT_PMD */ 2325 { 2326 RXTXCOM_OSR_MODE_CTLr_t reg_osr_mode; 2327 int speed; 2328 2329 TEFMOD16_DBG_IN_FUNC_INFO(pc); 2330 RXTXCOM_OSR_MODE_CTLr_CLR(reg_osr_mode); 2331 tefmod16_get_mapped_speed(spd_intf, &speed); 2332 2333 /* 0=OS_MODE_1; 1=OS_MODE_2; 2334 2=OS_MODE_4; 8=OS MODE_16p5; 2335 12=OS_MODE_20p625; */ 2336 2337 if(os_mode & 0x80000000) { 2338 os_mode = (os_mode) & 0x0000ffff; 2339 2340 } else { 2341 if (refclk == phymodRefClk125Mhz) { 2342 os_mode = sc_pmd16_entry_125M_ref[speed].t_pma_os_mode; 2343 } else { 2344 os_mode = sc_pmd16_entry[speed].t_pma_os_mode; 2345 } 2346 } 2347 2348 RXTXCOM_OSR_MODE_CTLr_OSR_MODE_FRCf_SET(reg_osr_mode, 1); 2349 RXTXCOM_OSR_MODE_CTLr_OSR_MODE_FRC_VALf_SET(reg_osr_mode, os_mode); 2350 2351 PHYMOD_IF_ERR_RETURN 2352 (MODIFY_RXTXCOM_OSR_MODE_CTLr(pc, reg_osr_mode)); 2353 2354 return PHYMOD_E_NONE; 2355 } 2356 2357 /** 2358 @brief Checks config valid status for the port 2359 @param pc handle to current TSCF context (#PHYMOD_ST) 2360 @returns The value PHYMOD_E_NONE upon successful completion 2361 @details This register bit indicates that PCS is now programmed as required 2362 by the HT entry for that speed 2363 */ 2364 STATIC 2365 int _tefmod16_wait_sc_stats_set(PHYMOD_ST* pc) 2366 { 2367 #if defined(_DV_TB_) || defined(_SDK_TEFMOD16_) 2368 uint16_t data; 2369 uint16_t i; 2370 SC_X4_STSr_t reg_sc_ctrl_sts; 2371 2372 SC_X4_STSr_CLR(reg_sc_ctrl_sts); 2373 i = 0; 2374 data = 0; 2375 #endif /* _DV_TB_ || _SDK_TEFMOD16_ */ 2376 2377 #ifdef _DV_TB_ 2378 while(1){ 2379 i=i+1; /* added only to eliminate compile warning */ 2380 PHYMOD_IF_ERR_RETURN(READ_SC_X4_STSr(pc, ®_sc_ctrl_sts)); 2381 data = SC_X4_STSr_SW_SPEED_CONFIG_VLDf_GET(reg_sc_ctrl_sts); 2382 if(data == 1) 2383 break; 2384 } 2385 #endif /* _DV_TB_ */ 2386 #ifdef _SDK_TEFMOD16_ 2387 for (i= 0; i < 10; i++) { 2388 PHYMOD_USLEEP(1); 2389 PHYMOD_IF_ERR_RETURN(READ_SC_X4_STSr(pc, ®_sc_ctrl_sts)); 2390 data = SC_X4_STSr_SW_SPEED_CONFIG_VLDf_GET(reg_sc_ctrl_sts); 2391 if(data == 1) { 2392 return PHYMOD_E_NONE; 2393 } 2394 } 2395 if (data != 1) { 2396 return PHYMOD_E_TIMEOUT; 2397 } 2398 #endif /* _SDK_TEFMOD16_ */ 2399 /* Intentional check .if none of the above MACROs are defined,return PHYMOD_E_NONE */ 2400 /* coverity[dead_error_line] */ 2401 return PHYMOD_E_NONE; 2402 } 2403 2404 /*Enable 10G clock when VCO is 25G*/ 2405 int tefmod16_10g_clock_enable(PHYMOD_ST *pc, int enable) 2406 { 2407 RX_CTL8r_t RX_CTL8r_t_reg; 2408 TX_CTL3r_t TX_CTL3r_t_reg; 2409 2410 RX_CTL8r_CLR(RX_CTL8r_t_reg); 2411 TX_CTL3r_CLR(TX_CTL3r_t_reg); 2412 2413 RX_CTL8r_AMS_RX_SPARE_134f_SET(RX_CTL8r_t_reg, enable); 2414 PHYMOD_IF_ERR_RETURN(MODIFY_RX_CTL8r(pc, RX_CTL8r_t_reg)); 2415 2416 PHYMOD_IF_ERR_RETURN(READ_RX_CTL8r(pc, &RX_CTL8r_t_reg)); 2417 RX_CTL8r_AMS_RX_RXCLK_DIV2P5f_SET(RX_CTL8r_t_reg, enable); 2418 PHYMOD_IF_ERR_RETURN(MODIFY_RX_CTL8r(pc, RX_CTL8r_t_reg)); 2419 2420 TX_CTL3r_AMS_TX_SPARE_58f_SET(TX_CTL3r_t_reg, enable); 2421 PHYMOD_IF_ERR_RETURN(MODIFY_TX_CTL3r(pc, TX_CTL3r_t_reg)); 2422 2423 PHYMOD_IF_ERR_RETURN(READ_TX_CTL3r(pc, &TX_CTL3r_t_reg)); 2424 TX_CTL3r_AMS_TX_TXCLK_DIV2P5f_SET(TX_CTL3r_t_reg, enable); 2425 PHYMOD_IF_ERR_RETURN(MODIFY_TX_CTL3r(pc, TX_CTL3r_t_reg)); 2426 2427 return PHYMOD_E_NONE; 2428 } 2429 2430 /*override the speed id 0x1(S_10G_KR1)*/ 2431 int tefmod16_override_10g_kr1_spd_intf(PHYMOD_ST *pc, int override) 2432 { 2433 phymod_access_t pa_copy; 2434 int start_lane = 0, num_lane = 0; 2435 /*0x9280*/ 2436 SC_X1_SPD_OVRR1_SPDr_t SC_X1_SPD_OVRR1_SPDr_t_reg; 2437 /*0x9282*/ 2438 SC_X1_SPD_OVRR1_0r_t SC_X1_SPD_OVRR1_0r_t_reg; 2439 /*0x9283*/ 2440 SC_X1_SPD_OVRR1_1r_t SC_X1_SPD_OVRR1_1r_t_reg; 2441 /*0x9284*/ 2442 SC_X1_SPD_OVRR1_2r_t SC_X1_SPD_OVRR1_2r_t_reg; 2443 /*0x9285*/ 2444 SC_X1_SPD_OVRR1_3r_t SC_X1_SPD_OVRR1_3r_t_reg; 2445 /*0x9286*/ 2446 SC_X1_SPD_OVRR1_4r_t SC_X1_SPD_OVRR1_4r_t_reg; 2447 /*0x9287*/ 2448 SC_X1_SPD_OVRR1_5r_t SC_X1_SPD_OVRR1_5r_t_reg; 2449 /*0x9288*/ 2450 SC_X1_SPD_OVRR1_6r_t SC_X1_SPD_OVRR1_6r_t_reg; 2451 2452 PHYMOD_MEMCPY(&pa_copy, pc, sizeof(pa_copy)); 2453 PHYMOD_IF_ERR_RETURN 2454 (phymod_util_lane_config_get(pc, &start_lane, &num_lane)); 2455 pa_copy.lane_mask = 0x1 << start_lane; 2456 if (override) { 2457 /*0x9280*/ 2458 SC_X1_SPD_OVRR1_SPDr_CLR(SC_X1_SPD_OVRR1_SPDr_t_reg); 2459 SC_X1_SPD_OVRR1_SPDr_SPEEDf_SET(SC_X1_SPD_OVRR1_SPDr_t_reg, 0x1); 2460 SC_X1_SPD_OVRR1_SPDr_T_PMA_40B_MODEf_SET(SC_X1_SPD_OVRR1_SPDr_t_reg, 0x0); 2461 SC_X1_SPD_OVRR1_SPDr_NUM_LANESf_SET(SC_X1_SPD_OVRR1_SPDr_t_reg, 0x0); 2462 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR1_SPDr(&pa_copy, SC_X1_SPD_OVRR1_SPDr_t_reg)); 2463 2464 /*0x9282*/ 2465 SC_X1_SPD_OVRR1_0r_CLR(SC_X1_SPD_OVRR1_0r_t_reg); 2466 SC_X1_SPD_OVRR1_0r_SCR_MODEf_SET(SC_X1_SPD_OVRR1_0r_t_reg, 0x1); 2467 SC_X1_SPD_OVRR1_0r_T_PMA_BTMX_MODEf_SET(SC_X1_SPD_OVRR1_0r_t_reg, 0x0); 2468 SC_X1_SPD_OVRR1_0r_T_HG2_ENABLEf_SET(SC_X1_SPD_OVRR1_0r_t_reg, 0x0); 2469 SC_X1_SPD_OVRR1_0r_T_ENC_MODEf_SET(SC_X1_SPD_OVRR1_0r_t_reg, 0x01); 2470 SC_X1_SPD_OVRR1_0r_T_FIFO_MODEf_SET(SC_X1_SPD_OVRR1_0r_t_reg, 0x0); 2471 SC_X1_SPD_OVRR1_0r_OS_MODEf_SET(SC_X1_SPD_OVRR1_0r_t_reg, 0x0); 2472 SC_X1_SPD_OVRR1_0r_CL72_ENf_SET(SC_X1_SPD_OVRR1_0r_t_reg, 0x01); 2473 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR1_0r(&pa_copy, SC_X1_SPD_OVRR1_0r_t_reg)); 2474 2475 /**0x9283*/ 2476 SC_X1_SPD_OVRR1_1r_CLR(SC_X1_SPD_OVRR1_1r_t_reg); 2477 SC_X1_SPD_OVRR1_1r_SET(SC_X1_SPD_OVRR1_1r_t_reg, 0x5570); 2478 PHYMOD_IF_ERR_RETURN(WRITE_SC_X1_SPD_OVRR1_1r(&pa_copy, SC_X1_SPD_OVRR1_1r_t_reg)); 2479 2480 /*0x9284*/ 2481 SC_X1_SPD_OVRR1_2r_CLR(SC_X1_SPD_OVRR1_2r_t_reg); 2482 SC_X1_SPD_OVRR1_2r_CLOCKCNT0f_SET(SC_X1_SPD_OVRR1_2r_t_reg, 0x25); 2483 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR1_2r(&pa_copy, SC_X1_SPD_OVRR1_2r_t_reg)); 2484 2485 /*0x9285*/ 2486 SC_X1_SPD_OVRR1_3r_CLR(SC_X1_SPD_OVRR1_3r_t_reg); 2487 SC_X1_SPD_OVRR1_3r_CLOCKCNT1f_SET(SC_X1_SPD_OVRR1_3r_t_reg, 0x19); 2488 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR1_3r(&pa_copy, SC_X1_SPD_OVRR1_3r_t_reg)); 2489 2490 /*0x9286*/ 2491 SC_X1_SPD_OVRR1_4r_CLR(SC_X1_SPD_OVRR1_4r_t_reg); 2492 SC_X1_SPD_OVRR1_4r_LOOPCNT0f_SET(SC_X1_SPD_OVRR1_4r_t_reg, 0x2); 2493 SC_X1_SPD_OVRR1_4r_LOOPCNT1f_SET(SC_X1_SPD_OVRR1_4r_t_reg, 0x1); 2494 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR1_4r(&pa_copy, SC_X1_SPD_OVRR1_4r_t_reg)); 2495 2496 /*0x9287*/ 2497 SC_X1_SPD_OVRR1_5r_CLR(SC_X1_SPD_OVRR1_5r_t_reg); 2498 SC_X1_SPD_OVRR1_5r_MAC_CREDITGENCNTf_SET(SC_X1_SPD_OVRR1_5r_t_reg, 0xc); 2499 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR1_5r(&pa_copy, SC_X1_SPD_OVRR1_5r_t_reg)); 2500 2501 /*0x9288*/ 2502 SC_X1_SPD_OVRR1_6r_CLR(SC_X1_SPD_OVRR1_6r_t_reg); 2503 SC_X1_SPD_OVRR1_6r_T_CL91_CW_SCRAMBLEf_SET(SC_X1_SPD_OVRR1_6r_t_reg, 0); 2504 SC_X1_SPD_OVRR1_6r_T_FIVE_BIT_XOR_ENf_SET(SC_X1_SPD_OVRR1_6r_t_reg, 0); 2505 SC_X1_SPD_OVRR1_6r_T_PMA_CL91_MUX_SELf_SET(SC_X1_SPD_OVRR1_6r_t_reg, 0); 2506 SC_X1_SPD_OVRR1_6r_T_PMA_WATERMARKf_SET(SC_X1_SPD_OVRR1_6r_t_reg, 0x4); 2507 SC_X1_SPD_OVRR1_6r_T_PMA_BITMUX_DELAYf_SET(SC_X1_SPD_OVRR1_6r_t_reg, 0x1); 2508 SC_X1_SPD_OVRR1_6r_AM_SPACING_MULf_SET(SC_X1_SPD_OVRR1_6r_t_reg, 0x0); 2509 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR1_6r(&pa_copy, SC_X1_SPD_OVRR1_6r_t_reg)); 2510 } else { 2511 /*clear the override*/ 2512 2513 /*0x9280*/ 2514 SC_X1_SPD_OVRR1_SPDr_CLR(SC_X1_SPD_OVRR1_SPDr_t_reg); 2515 SC_X1_SPD_OVRR1_SPDr_SPEEDf_SET(SC_X1_SPD_OVRR1_SPDr_t_reg, 0xff); 2516 PHYMOD_IF_ERR_RETURN(WRITE_SC_X1_SPD_OVRR1_SPDr(&pa_copy, SC_X1_SPD_OVRR1_SPDr_t_reg)); 2517 2518 /*0x9282*/ 2519 SC_X1_SPD_OVRR1_0r_CLR(SC_X1_SPD_OVRR1_0r_t_reg); 2520 PHYMOD_IF_ERR_RETURN(WRITE_SC_X1_SPD_OVRR1_0r(&pa_copy, SC_X1_SPD_OVRR1_0r_t_reg)); 2521 2522 /**0x9283*/ 2523 SC_X1_SPD_OVRR1_1r_CLR(SC_X1_SPD_OVRR1_1r_t_reg); 2524 PHYMOD_IF_ERR_RETURN(WRITE_SC_X1_SPD_OVRR1_1r(&pa_copy, SC_X1_SPD_OVRR1_1r_t_reg)); 2525 2526 /*0x9284*/ 2527 SC_X1_SPD_OVRR1_2r_CLR(SC_X1_SPD_OVRR1_2r_t_reg); 2528 PHYMOD_IF_ERR_RETURN(WRITE_SC_X1_SPD_OVRR1_2r(&pa_copy, SC_X1_SPD_OVRR1_2r_t_reg)); 2529 2530 /*0x9285*/ 2531 SC_X1_SPD_OVRR1_3r_CLR(SC_X1_SPD_OVRR1_3r_t_reg); 2532 PHYMOD_IF_ERR_RETURN(WRITE_SC_X1_SPD_OVRR1_3r(&pa_copy, SC_X1_SPD_OVRR1_3r_t_reg)); 2533 2534 /*0x9286*/ 2535 SC_X1_SPD_OVRR1_4r_CLR(SC_X1_SPD_OVRR1_4r_t_reg); 2536 PHYMOD_IF_ERR_RETURN(WRITE_SC_X1_SPD_OVRR1_4r(&pa_copy, SC_X1_SPD_OVRR1_4r_t_reg)); 2537 2538 /*0x9287*/ 2539 SC_X1_SPD_OVRR1_5r_CLR(SC_X1_SPD_OVRR1_5r_t_reg); 2540 PHYMOD_IF_ERR_RETURN(WRITE_SC_X1_SPD_OVRR1_5r(&pa_copy, SC_X1_SPD_OVRR1_5r_t_reg)); 2541 2542 /*0x9288*/ 2543 SC_X1_SPD_OVRR1_6r_CLR(SC_X1_SPD_OVRR1_6r_t_reg); 2544 PHYMOD_IF_ERR_RETURN(WRITE_SC_X1_SPD_OVRR1_6r(&pa_copy, SC_X1_SPD_OVRR1_6r_t_reg)); 2545 } 2546 2547 return PHYMOD_E_NONE; 2548 } 2549 2550 /*override the speed id 0x2*/ 2551 int tefmod16_override_10g_x1_spd_intf(PHYMOD_ST *pc, int override) 2552 { 2553 phymod_access_t pa_copy; 2554 int start_lane = 0, num_lane = 0; 2555 /*0x9290*/ 2556 SC_X1_SPD_OVRR2_SPDr_t SC_X1_SPD_OVRR2_SPDr_t_reg; 2557 /*0x9292*/ 2558 SC_X1_SPD_OVRR2_0r_t SC_X1_SPD_OVRR2_0r_t_reg; 2559 /*0x9293*/ 2560 SC_X1_SPD_OVRR2_1r_t SC_X1_SPD_OVRR2_1r_t_reg; 2561 /*0x9294*/ 2562 SC_X1_SPD_OVRR2_2r_t SC_X1_SPD_OVRR2_2r_t_reg; 2563 /*0x9295*/ 2564 SC_X1_SPD_OVRR2_3r_t SC_X1_SPD_OVRR2_3r_t_reg; 2565 /*0x9296*/ 2566 SC_X1_SPD_OVRR2_4r_t SC_X1_SPD_OVRR2_4r_t_reg; 2567 /*0x9297*/ 2568 SC_X1_SPD_OVRR2_5r_t SC_X1_SPD_OVRR2_5r_t_reg; 2569 /*0x9298*/ 2570 SC_X1_SPD_OVRR2_6r_t SC_X1_SPD_OVRR2_6r_t_reg; 2571 2572 PHYMOD_MEMCPY(&pa_copy, pc, sizeof(pa_copy)); 2573 PHYMOD_IF_ERR_RETURN 2574 (phymod_util_lane_config_get(pc, &start_lane, &num_lane)); 2575 pa_copy.lane_mask = 0x1 << start_lane; 2576 if (override) { 2577 /*0x9290*/ 2578 SC_X1_SPD_OVRR2_SPDr_CLR(SC_X1_SPD_OVRR2_SPDr_t_reg); 2579 SC_X1_SPD_OVRR2_SPDr_SPEEDf_SET(SC_X1_SPD_OVRR2_SPDr_t_reg, 0x2); 2580 SC_X1_SPD_OVRR2_SPDr_T_PMA_40B_MODEf_SET(SC_X1_SPD_OVRR2_SPDr_t_reg, 0x0); 2581 SC_X1_SPD_OVRR2_SPDr_NUM_LANESf_SET(SC_X1_SPD_OVRR2_SPDr_t_reg, 0x0); 2582 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR2_SPDr(&pa_copy, SC_X1_SPD_OVRR2_SPDr_t_reg)); 2583 2584 /*0x9292*/ 2585 SC_X1_SPD_OVRR2_0r_CLR(SC_X1_SPD_OVRR2_0r_t_reg); 2586 SC_X1_SPD_OVRR2_0r_SCR_MODEf_SET(SC_X1_SPD_OVRR2_0r_t_reg, 0x1); 2587 SC_X1_SPD_OVRR2_0r_T_PMA_BTMX_MODEf_SET(SC_X1_SPD_OVRR2_0r_t_reg, 0x0); 2588 SC_X1_SPD_OVRR2_0r_T_HG2_ENABLEf_SET(SC_X1_SPD_OVRR2_0r_t_reg, 0x0); 2589 SC_X1_SPD_OVRR2_0r_T_ENC_MODEf_SET(SC_X1_SPD_OVRR2_0r_t_reg, 0x01); 2590 SC_X1_SPD_OVRR2_0r_T_FIFO_MODEf_SET(SC_X1_SPD_OVRR2_0r_t_reg, 0x0); 2591 SC_X1_SPD_OVRR2_0r_OS_MODEf_SET(SC_X1_SPD_OVRR2_0r_t_reg, 0x0); 2592 SC_X1_SPD_OVRR2_0r_CL72_ENf_SET(SC_X1_SPD_OVRR2_0r_t_reg, 0x01); 2593 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR2_0r(&pa_copy, SC_X1_SPD_OVRR2_0r_t_reg)); 2594 2595 /**0x9293*/ 2596 SC_X1_SPD_OVRR2_1r_CLR(SC_X1_SPD_OVRR2_1r_t_reg); 2597 SC_X1_SPD_OVRR2_1r_SET(SC_X1_SPD_OVRR2_1r_t_reg, 0x5570); 2598 PHYMOD_IF_ERR_RETURN(WRITE_SC_X1_SPD_OVRR2_1r(&pa_copy, SC_X1_SPD_OVRR2_1r_t_reg)); 2599 2600 /*0x9294*/ 2601 SC_X1_SPD_OVRR2_2r_CLR(SC_X1_SPD_OVRR2_2r_t_reg); 2602 SC_X1_SPD_OVRR2_2r_CLOCKCNT0f_SET(SC_X1_SPD_OVRR2_2r_t_reg, 0x25); 2603 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR2_2r(&pa_copy, SC_X1_SPD_OVRR2_2r_t_reg)); 2604 2605 /*0x9295*/ 2606 SC_X1_SPD_OVRR2_3r_CLR(SC_X1_SPD_OVRR2_3r_t_reg); 2607 SC_X1_SPD_OVRR2_3r_CLOCKCNT1f_SET(SC_X1_SPD_OVRR2_3r_t_reg, 0x19); 2608 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR2_3r(&pa_copy, SC_X1_SPD_OVRR2_3r_t_reg)); 2609 2610 /*0x9296*/ 2611 SC_X1_SPD_OVRR2_4r_CLR(SC_X1_SPD_OVRR2_4r_t_reg); 2612 SC_X1_SPD_OVRR2_4r_LOOPCNT0f_SET(SC_X1_SPD_OVRR2_4r_t_reg, 0x2); 2613 SC_X1_SPD_OVRR2_4r_LOOPCNT1f_SET(SC_X1_SPD_OVRR2_4r_t_reg, 0x1); 2614 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR2_4r(&pa_copy, SC_X1_SPD_OVRR2_4r_t_reg)); 2615 2616 /*0x9297*/ 2617 SC_X1_SPD_OVRR2_5r_CLR(SC_X1_SPD_OVRR2_5r_t_reg); 2618 SC_X1_SPD_OVRR2_5r_MAC_CREDITGENCNTf_SET(SC_X1_SPD_OVRR2_5r_t_reg, 0xc); 2619 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR2_5r(&pa_copy, SC_X1_SPD_OVRR2_5r_t_reg)); 2620 2621 /*0x9298*/ 2622 SC_X1_SPD_OVRR2_6r_CLR(SC_X1_SPD_OVRR2_6r_t_reg); 2623 SC_X1_SPD_OVRR2_6r_T_CL91_CW_SCRAMBLEf_SET(SC_X1_SPD_OVRR2_6r_t_reg, 0); 2624 SC_X1_SPD_OVRR2_6r_T_FIVE_BIT_XOR_ENf_SET(SC_X1_SPD_OVRR2_6r_t_reg, 0); 2625 SC_X1_SPD_OVRR2_6r_T_PMA_CL91_MUX_SELf_SET(SC_X1_SPD_OVRR2_6r_t_reg, 0); 2626 SC_X1_SPD_OVRR2_6r_T_PMA_WATERMARKf_SET(SC_X1_SPD_OVRR2_6r_t_reg, 0x4); 2627 SC_X1_SPD_OVRR2_6r_T_PMA_BITMUX_DELAYf_SET(SC_X1_SPD_OVRR2_6r_t_reg, 0x1); 2628 SC_X1_SPD_OVRR2_6r_AM_SPACING_MULf_SET(SC_X1_SPD_OVRR2_6r_t_reg, 0x0); 2629 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR2_6r(&pa_copy, SC_X1_SPD_OVRR2_6r_t_reg)); 2630 } else { 2631 /*clear the override*/ 2632 2633 /*0x9290*/ 2634 SC_X1_SPD_OVRR2_SPDr_CLR(SC_X1_SPD_OVRR2_SPDr_t_reg); 2635 SC_X1_SPD_OVRR2_SPDr_SPEEDf_SET(SC_X1_SPD_OVRR2_SPDr_t_reg, 0xff); 2636 PHYMOD_IF_ERR_RETURN(WRITE_SC_X1_SPD_OVRR2_SPDr(&pa_copy, SC_X1_SPD_OVRR2_SPDr_t_reg)); 2637 2638 /*0x9292*/ 2639 SC_X1_SPD_OVRR2_0r_CLR(SC_X1_SPD_OVRR2_0r_t_reg); 2640 PHYMOD_IF_ERR_RETURN(WRITE_SC_X1_SPD_OVRR2_0r(&pa_copy, SC_X1_SPD_OVRR2_0r_t_reg)); 2641 2642 /**0x9293*/ 2643 SC_X1_SPD_OVRR2_1r_CLR(SC_X1_SPD_OVRR2_1r_t_reg); 2644 PHYMOD_IF_ERR_RETURN(WRITE_SC_X1_SPD_OVRR2_1r(&pa_copy, SC_X1_SPD_OVRR2_1r_t_reg)); 2645 2646 /*0x9294*/ 2647 SC_X1_SPD_OVRR2_2r_CLR(SC_X1_SPD_OVRR2_2r_t_reg); 2648 PHYMOD_IF_ERR_RETURN(WRITE_SC_X1_SPD_OVRR2_2r(&pa_copy, SC_X1_SPD_OVRR2_2r_t_reg)); 2649 2650 /*0x9295*/ 2651 SC_X1_SPD_OVRR2_3r_CLR(SC_X1_SPD_OVRR2_3r_t_reg); 2652 PHYMOD_IF_ERR_RETURN(WRITE_SC_X1_SPD_OVRR2_3r(&pa_copy, SC_X1_SPD_OVRR2_3r_t_reg)); 2653 2654 /*0x9296*/ 2655 SC_X1_SPD_OVRR2_4r_CLR(SC_X1_SPD_OVRR2_4r_t_reg); 2656 PHYMOD_IF_ERR_RETURN(WRITE_SC_X1_SPD_OVRR2_4r(&pa_copy, SC_X1_SPD_OVRR2_4r_t_reg)); 2657 2658 /*0x9297*/ 2659 SC_X1_SPD_OVRR2_5r_CLR(SC_X1_SPD_OVRR2_5r_t_reg); 2660 PHYMOD_IF_ERR_RETURN(WRITE_SC_X1_SPD_OVRR2_5r(&pa_copy, SC_X1_SPD_OVRR2_5r_t_reg)); 2661 2662 /*0x9298*/ 2663 SC_X1_SPD_OVRR2_6r_CLR(SC_X1_SPD_OVRR2_6r_t_reg); 2664 PHYMOD_IF_ERR_RETURN(WRITE_SC_X1_SPD_OVRR2_6r(&pa_copy, SC_X1_SPD_OVRR2_6r_t_reg)); 2665 } 2666 2667 return PHYMOD_E_NONE; 2668 } 2669 /** 2670 @brief Set the port speed and enable the port 2671 @param pc handle to current TSCF context (#PHYMOD_ST) 2672 @param spd_intf the speed to set the port enum #tefmod16_set_spd_intf 2673 @returns The value PHYMOD_E_NONE upon successful completion 2674 @details Sets the port to the specified speed and triggers the port, and waits 2675 for the port to be configured 2676 */ 2677 int tefmod16_set_spd_intf(PHYMOD_ST *pc, tefmod16_spd_intfc_type_t spd_intf) 2678 { 2679 SC_X4_CTLr_t xgxs_x4_ctrl; 2680 phymod_access_t pa_copy; 2681 int speed_id = 0, start_lane = 0, num_lane = 0; 2682 TX_X4_TX_CTL0r_t TX_X4_TX_CTL0r_reg; 2683 RX_X4_PCS_CTL0r_t RX_X4_PCS_CTL0r_reg; 2684 int tx_fec_mode; 2685 int rx_fec_mode; 2686 2687 TEFMOD16_DBG_IN_FUNC_INFO(pc); 2688 TEFMOD16_DBG_IN_FUNC_VIN_INFO(pc,("spd_intf: %d", spd_intf)); 2689 2690 /* need to figure out what's the starting lane */ 2691 PHYMOD_MEMCPY(&pa_copy, pc, sizeof(pa_copy)); 2692 PHYMOD_IF_ERR_RETURN 2693 (phymod_util_lane_config_get(pc, &start_lane, &num_lane)); 2694 pa_copy.lane_mask = 0x1 << start_lane; 2695 2696 PHYMOD_IF_ERR_RETURN (tefmod16_get_mapped_speed(spd_intf, &speed_id)); 2697 2698 if (speed_id == sc_x4_control_sc_S_25G_X1) { 2699 TX_X4_TX_CTL0r_CLR(TX_X4_TX_CTL0r_reg); 2700 RX_X4_PCS_CTL0r_CLR(RX_X4_PCS_CTL0r_reg); 2701 2702 READ_TX_X4_TX_CTL0r(pc, &TX_X4_TX_CTL0r_reg); 2703 READ_RX_X4_PCS_CTL0r(pc, &RX_X4_PCS_CTL0r_reg); 2704 2705 tx_fec_mode = TX_X4_TX_CTL0r_CL91_FEC_MODEf_GET(TX_X4_TX_CTL0r_reg); 2706 rx_fec_mode = RX_X4_PCS_CTL0r_CL91_FEC_MODEf_GET(RX_X4_PCS_CTL0r_reg); 2707 2708 /*In IEEE 25G FEC, speed id is S_25G_KR_IEEE (0x72)*/ 2709 if ((tx_fec_mode == TEFMOD16_IEEE_25G_CL91_SINGLE_LANE) 2710 && (rx_fec_mode == TEFMOD16_IEEE_25G_CL91_SINGLE_LANE)) { 2711 speed_id = sc_x4_control_sc_S_25G_KR_IEEE; 2712 } 2713 } 2714 2715 /* write the speed_id into the speed_change register */ 2716 SC_X4_CTLr_CLR(xgxs_x4_ctrl); 2717 SC_X4_CTLr_SPEEDf_SET(xgxs_x4_ctrl, speed_id); 2718 MODIFY_SC_X4_CTLr(pc, xgxs_x4_ctrl); 2719 /*next call the speed_change routine */ 2720 PHYMOD_IF_ERR_RETURN (tefmod16_trigger_speed_change(&pa_copy)); 2721 /*check the speed_change_done bit*/ 2722 PHYMOD_IF_ERR_RETURN (_tefmod16_wait_sc_stats_set(pc)); 2723 2724 return PHYMOD_E_NONE; 2725 } 2726 2727 #ifdef _DV_TB_ 2728 /*! 2729 @brief Set remote loopback mode for GMII, cl49, aggregate(XAUI) and R2 modes. 2730 @param pc handle to current TSCF context (#PHYMOD_ST) 2731 @returns The value PHYMOD_E_NONE upon successful completion 2732 @details 2733 This function sets the remote loopback (RX-to-TX) mode for one lane at a time, 2734 where the lane is indicated by the lane field. To enable remote loopback, set 2735 the field #PHYMOD_ST::en_dis to 1; to disable remote loopback, set pmd_rloop_en 2736 to 0. 2737 2738 Note that the speed field PHYMOD_ST::spd_intf must be set prior to calling this 2739 function because the loopback register and path are speed/interface dependent. 2740 2741 The first two bits of #PHYMOD_ST::per_lane_control decide for PCS pr PMD. After 2742 right shifting the first two bits of #PHYMOD_ST::per_lane_control the 1st, 2nd, 2743 3rd and 4th byte is associated with lanes 0, 1, 2, and 3 respectively. 2744 2745 The bits of each byte control their lanes as follows. !! Also 1st byte decides 2746 it is for PCS or PMD remote loopback. 2747 2748 \li 0:0 : Enable PMD Loopback (rloop) 2749 \li 0:1 : Enable PCS Loopback (rloop) 2750 \li 1:1 : Enable loopback 2751 \li 1:0 : Disable loopback 2752 2753 The function modifies the following registers: 2754 \li 0x9009 (MAIN0_LPBK_CTLr) 2755 \li bit 15:12 for REMOTE_PCS_LOOPBACK_ENABLE 2756 \li bit 11:08 for REMOTE_PMD_LOOPBACK_ENABLE 2757 */ 2758 int tefmod16_rx_pmd_loopback_control(PHYMOD_ST* pc, int pcs_rloop_en, int pmd_rloop_en, int lane) 2759 { 2760 uint16_t data; 2761 int cntl; 2762 TLB_TX_RMT_LPBK_CFGr_t TLB_TX_RMT_LPBK_CONFIGr_reg; 2763 DSC_CDR_CTL2r_t DSC_C_CDR_CONTROL_2r_reg; 2764 TX_PI_PMD_CTL0r_t TX_PI_PMD_COM_TX_PI_PMD_COM_CONTROL_0r_reg; 2765 2766 TEFMOD16_DBG_IN_FUNC_INFO(pc); 2767 data = 0; 2768 2769 /* remote pmd device is set in rloop */ 2770 2771 #ifdef _DV_TB_ 2772 if ((pc->unit) == 2) { 2773 #endif 2774 cntl = (((pmd_rloop_en) >> lane) & 0x1); 2775 TLB_TX_RMT_LPBK_CFGr_CLR(TLB_TX_RMT_LPBK_CONFIGr_reg); 2776 if (cntl) { 2777 TLB_TX_RMT_LPBK_CFGr_RMT_LPBK_ENf_SET(TLB_TX_RMT_LPBK_CONFIGr_reg, 1); 2778 } else { 2779 TLB_TX_RMT_LPBK_CFGr_RMT_LPBK_ENf_SET(TLB_TX_RMT_LPBK_CONFIGr_reg, 0); 2780 } 2781 2782 PHYMOD_IF_ERR_RETURN (MODIFY_TLB_TX_RMT_LPBK_CFGr(pc, TLB_TX_RMT_LPBK_CONFIGr_reg)); 2783 2784 /* set Tx_PI */ 2785 2786 DSC_CDR_CTL2r_CLR(DSC_C_CDR_CONTROL_2r_reg); 2787 DSC_CDR_CTL2r_TX_PI_LOOP_TIMING_SRC_SELf_SET(DSC_C_CDR_CONTROL_2r_reg, 1); 2788 2789 PHYMOD_IF_ERR_RETURN(MODIFY_DSC_CDR_CTL2r(pc, DSC_C_CDR_CONTROL_2r_reg)); 2790 2791 TX_PI_CTL0r_CLR(TX_PI_PMD_COM_TX_PI_PMD_COM_CONTROL_0r_reg); 2792 TX_PI_CTL0r_TX_PI_ENf_SET(TX_PI_PMD_COM_TX_PI_PMD_COM_CONTROL_0r_reg, 1); 2793 2794 PHYMOD_IF_ERR_RETURN(MODIFY_TX_PI_CTL0r(pc, TX_PI_PMD_COM_TX_PI_PMD_COM_CONTROL_0r_reg)); 2795 #ifdef _DV_TB_ 2796 } else { 2797 2798 } 2799 #endif 2800 return PHYMOD_E_NONE; 2801 } /* tefmod16_rx_pmd_loopback_control */ 2802 #endif 2803 2804 #ifdef _DV_TB_ 2805 /*! 2806 @brief Control resetting/setting of credits based on speed interface selection 2807 @param pc handle to current TSCF context (#PHYMOD_ST) 2808 @returns The value PHYMOD_E_NONE upon successful completion. 2809 @details 2810 2811 This function sets/resets all credits for PCS and MAC as per speed interface 2812 selected. Set #PHYMOD_ST::per_lane_control to 1 to set the credits and set it 2813 to 0 to clear the credits. 2814 2815 This function is controlled by the following register bit: 2816 2817 \li set credits: clockcnt0 (0xC100[13:0]) 2818 \li clockcnt1 (0xC101[7:0]) 2819 \li loopcnt0 (0xC102[13:6]), loopcnt1 (0xC102[5:0]) 2820 \li mac_creditgencnt (0xC103[12:0]) 2821 \li pcs_clockcnt0 (0xC104[13:0]) 2822 \li pcs_creditgencnt (0xC105[12:0]) 2823 2824 */ 2825 2826 int tefmod16_credit_set(PHYMOD_ST* pc) /* CREDIT_SET */ 2827 { 2828 uint16_t data_loopcnt; 2829 uint16_t data_mac_credit; 2830 uint16_t clockcnt0, clockcnt1, loopcnt0, loopcnt1, mac_credit; 2831 2832 TX_X4_CRED0r_t TX_X4_CREDIT0_CREDIT0r_reg; 2833 TX_X4_CRED1r_t TX_X4_CREDIT0_CREDIT1r_reg; 2834 TX_X4_LOOPCNTr_t TX_X4_CREDIT0_LOOPCNTr_reg; 2835 TX_X4_MAC_CREDGENCNTr_t TX_X4_CREDIT0_MAC_CREDITGENCNTr_reg; 2836 /* uint16_t data_sgmii_spd_switch; */ 2837 int cntl; 2838 2839 TEFMOD16_DBG_IN_FUNC_INFO(pc); 2840 /*dv_tfmod_update_st(pc);*/ 2841 cntl = pc->per_lane_control; 2842 /* data_sgmii_spd_switch = 0; */ 2843 data_loopcnt = 0; 2844 data_mac_credit = 0; 2845 clockcnt0 = 0; 2846 clockcnt1 = 0; 2847 loopcnt0 = 1; 2848 loopcnt1 = 0; 2849 mac_credit = 0; 2850 2851 if (cntl) { 2852 if (pc->spd_intf == TEFMOD16_SPD_1000_SGMII) { 2853 2854 } else if ((pc->spd_intf == TEFMOD16_SPD_10000_XFI)|| 2855 (pc->spd_intf == TEFMOD16_SPD_10600_XFI_HG)) { 2856 clockcnt0 = 9; 2857 clockcnt1 = 10; 2858 loopcnt0 = 1; 2859 loopcnt1 = 9; 2860 mac_credit = 6; 2861 2862 } else if ((pc->spd_intf == TEFMOD16_SPD_20000_XFI) || 2863 (pc->spd_intf == TEFMOD16_SPD_21200_XFI_HG) || 2864 (pc->spd_intf == TEFMOD16_SPD_25000_XFI) || 2865 (pc->spd_intf == TEFMOD16_SPD_26500_XFI_HG)) { 2866 clockcnt0 = 9; 2867 clockcnt1 = 5; 2868 loopcnt0 = 1; 2869 loopcnt1 = 18; 2870 mac_credit = 4; 2871 2872 } else if ((pc->spd_intf == TEFMOD16_SPD_20G_MLD_X2) || 2873 (pc->spd_intf == TEFMOD16_SPD_21G_MLD_HG_X2)) { 2874 clockcnt0 = 9; 2875 clockcnt1 = 5; 2876 loopcnt0 = 1; 2877 loopcnt1 = 18; 2878 mac_credit = 4; 2879 2880 } else if ((pc->spd_intf == TEFMOD16_SPD_40G_MLD_X2) || 2881 (pc->spd_intf == TEFMOD16_SPD_42G_MLD_HG_X2) || 2882 (pc->spd_intf == TEFMOD16_SPD_50G_MLD_X2) || 2883 (pc->spd_intf == TEFMOD16_SPD_53G_MLD_HG_X2) || 2884 (pc->spd_intf == TEFMOD16_SPD_40G_MLD_X4) || 2885 (pc->spd_intf == TEFMOD16_SPD_42G_MLD_HG_X4) || 2886 (pc->spd_intf == TEFMOD16_SPD_50G_MLD_X4) || 2887 (pc->spd_intf == TEFMOD16_SPD_53G_MLD_HG_X4) ) { 2888 clockcnt0 = 9; 2889 clockcnt1 = 5; 2890 loopcnt0 = 1; 2891 loopcnt1 = 18; 2892 mac_credit = 2; 2893 2894 } else if ((pc->spd_intf == TEFMOD16_SPD_100G_MLD_X4) || 2895 (pc->spd_intf == TEFMOD16_SPD_106G_MLD_HG_X4)) { 2896 clockcnt0 = 9; 2897 clockcnt1 = 5; 2898 loopcnt0 = 1; 2899 loopcnt1 = 18; 2900 mac_credit = 1; 2901 2902 } else { 2903 PHYMOD_DEBUG_ERROR(("%-22s ERROR: p=%0d spd_intf=%d undefined %s cntl=%0x verb=%x\n", 2904 __func__, pc->port, pc->spd_intf, 2905 e2s_tefmod16_spd_intfc_type_t[pc->spd_intf], cntl, pc->verbosity)); 2906 return PHYMOD_E_FAIL; 2907 } 2908 /* set credtis 0xc100 */ 2909 TX_X4_CRED0r_CLR(TX_X4_CREDIT0_CREDIT0r_reg); 2910 TX_X4_CRED0r_CLOCKCNT0f_SET(TX_X4_CREDIT0_CREDIT0r_reg, clockcnt0); 2911 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_CRED0r(pc, TX_X4_CREDIT0_CREDIT0r_reg)); 2912 2913 /* 0xc101 */ 2914 TX_X4_CRED1r_CLR(TX_X4_CREDIT0_CREDIT1r_reg); 2915 TX_X4_CRED1r_CLOCKCNT1f_SET(TX_X4_CREDIT0_CREDIT1r_reg, clockcnt1); 2916 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_CRED1r(pc, TX_X4_CREDIT0_CREDIT1r_reg)); 2917 2918 /* 0xc102 */ 2919 TX_X4_LOOPCNTr_CLR(TX_X4_CREDIT0_LOOPCNTr_reg); 2920 TX_X4_LOOPCNTr_LOOPCNT0f_SET(TX_X4_CREDIT0_LOOPCNTr_reg, loopcnt0); 2921 TX_X4_LOOPCNTr_LOOPCNT1f_SET(TX_X4_CREDIT0_LOOPCNTr_reg, loopcnt1); 2922 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_LOOPCNTr(pc, TX_X4_CREDIT0_LOOPCNTr_reg)); 2923 2924 /* 0xc103 */ 2925 TX_X4_MAC_CREDGENCNTr_CLR(TX_X4_CREDIT0_MAC_CREDITGENCNTr_reg); 2926 TX_X4_MAC_CREDGENCNTr_MAC_CREDITGENCNTf_SET(TX_X4_CREDIT0_MAC_CREDITGENCNTr_reg, mac_credit); 2927 PHYMOD_IF_ERR_RETURN 2928 (MODIFY_TX_X4_MAC_CREDGENCNTr(pc, TX_X4_CREDIT0_MAC_CREDITGENCNTr_reg)); 2929 } else { 2930 /* clear credits */ 2931 TX_X4_CRED0r_CLR(TX_X4_CREDIT0_CREDIT0r_reg); 2932 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_CRED0r(pc, TX_X4_CREDIT0_CREDIT0r_reg)); 2933 } 2934 return PHYMOD_E_NONE; 2935 } /* CREDIT_SET */ 2936 #endif 2937 2938 #ifdef _DV_TB_ 2939 /*! 2940 @brief set tx encoder of any particular lane 2941 @param pc handle to current TSCF context (#PHYMOD_ST) 2942 @returns The value PHYMOD_E_NONE upon successful completion. 2943 @details 2944 This function is used to select encoder of any transmit lane. 2945 2946 \li select encodeMode 2947 2948 This function reads/modifies the following registers: 2949 \li Address (Name) 2950 \li 0xc111 (TX_X4_ENC0) 2951 \i field bit position variable defined in this function 2952 \li ENCODEMODE [4:2] encode_mode 2953 \li CL49_BYPASS_TXSM [9] - 2954 \li 2955 \li 0xc113 (TX_X4_MISC) 2956 \li SCR_MODE [15:14] scr_mode 2957 \li RESERVED0 [13:11] block_sync_mode 2958 \li CL49_TX_LI_ENABLE [8] - 2959 \li CL49_TX_LF_ENABLE [7] - 2960 \li CL49_TX_RF_ENABLE [6] - 2961 \li 2962 \li 0xa000 (TX_X2_MLD_SWP_CNT) 2963 \li MLD_SWAP_COUNT [15:0] - 2964 2965 <B> ENCODE_SET Progamming values 2966 \li 10G_XFI 2967 \li encodeMode : 5 2968 \li scr_mode : 3 2969 \li 2970 \li 10G_XAUI 2971 \li encode_mode : 0x1 cl48 8b10b 2972 \li CL49_BYPASS_TXSM : 0 2973 \li scr_mode : 0x0 bypass scramble 2974 \li 2975 \li 40G_MLD 2976 */ 2977 2978 /* for DV only ? CHECK Lpti */ 2979 int tefmod16_encode_set(PHYMOD_ST* pc, int per_lane_control, tefmod_spd_intfc_type_t spd_intf, int tx_am_timer_init_val) /* ENCODE_SET */ 2980 { 2981 uint16_t t_pma_btmx_mode, scr_mode, os_mode, hg2_en, t_fifo_mode, t_enc_mode; 2982 uint16_t cl82_bypass_txsm, cl49_tx_tl_mode, cl49_bypass_txsm; 2983 int cntl; 2984 #ifdef TSCF_GEN1 2985 uint16_t mld_swap_count; 2986 TX_X1_T_PMA_WTRMKr_t TX_X1_CONTROL0_T_PMA_WATERMARKr_reg; 2987 TX_X2_MLD_SWP_CNTr_t TX_X2_CONTROL0_MLD_SWAP_COUNTr_reg; 2988 #endif 2989 TX_X2_CL82_0r_t TX_X2_CONTROL0_CL82_0r_reg; 2990 TX_X4_ENC0r_t TX_X4_CONTROL0_ENCODE_0r_reg; 2991 TX_X4_MISCr_t TX_X4_CONTROL0_MISCr_reg; 2992 2993 TEFMOD16_DBG_IN_FUNC_INFO(pc); 2994 cntl = per_lane_control; 2995 2996 cl49_bypass_txsm = 0; 2997 hg2_en = 0; /* 001 cl48 8b10b 2998 010 cl48 8b10b rxaui 2999 011 cl36 8b10b 3000 100 cl82 64b66b 3001 101 cl49 64b66b 3002 110 brcm 64b66b */ 3003 scr_mode = 0; /* 00 bypass scrambler 3004 01 64b66b scrambler (all 66 bits) 3005 10 8b10b scrambler (all 80 bits) 3006 11 64b66b scrambler (sync bits not scrambled)*/ 3007 t_pma_btmx_mode = 0; 3008 t_fifo_mode = 0; 3009 t_enc_mode = 0; 3010 cl82_bypass_txsm = 0; 3011 cl49_tx_tl_mode = 0; 3012 cl49_bypass_txsm = 0; 3013 3014 #ifdef TSCF_GEN1 3015 mld_swap_count = 0; 3016 #endif 3017 3018 if((spd_intf == TEFMOD16_SPD_10_SGMII) | 3019 (spd_intf == TEFMOD16_SPD_100_SGMII) | 3020 (spd_intf == TEFMOD16_SPD_1000_SGMII) ) { 3021 /* ------------------------------------- 0xc114 */ 3022 } else if((spd_intf == TEFMOD16_SPD_10000_XFI) || 3023 (spd_intf == TEFMOD16_SPD_10600_XFI_HG)) { 3024 t_fifo_mode = 0; 3025 t_enc_mode = 1; 3026 cl49_tx_tl_mode = 0; 3027 cl49_bypass_txsm = 0; 3028 hg2_en = 0; 3029 scr_mode = 1; 3030 os_mode = 1; 3031 t_pma_btmx_mode = 0; 3032 /* ------------------------------------ 0xc111 */ 3033 cl49_bypass_txsm = 0; 3034 /* ------------------------------------ 0xc113 */ 3035 /* scr_mode = 0x1; */ 3036 /* ------------------------------------ 0xa000 */ 3037 } else if ((spd_intf == TEFMOD16_SPD_20000_XFI) || 3038 (spd_intf == TEFMOD16_SPD_25000_XFI) || 3039 (spd_intf == TEFMOD16_SPD_21200_XFI_HG) || 3040 (spd_intf == TEFMOD16_SPD_26500_XFI_HG) || 3041 (spd_intf == TEFMOD16_SPD_25G_CR_IEEE) || 3042 (spd_intf == TEFMOD16_SPD_25G_CRS_IEEE) || 3043 (spd_intf == TEFMOD16_SPD_25G_KR_IEEE) || 3044 (spd_intf == TEFMOD16_SPD_25G_KRS_IEEE) || 3045 (spd_intf == TEFMOD16_SPD_25G_CR1) || 3046 (spd_intf == TEFMOD16_SPD_25G_KR1) || 3047 (spd_intf == TEFMOD16_SPD_25G_CR1_HG2) || 3048 (spd_intf == TEFMOD16_SPD_25G_KR1_HG2)) { 3049 t_fifo_mode = 0; 3050 t_enc_mode = 1; 3051 cl49_tx_tl_mode = 0; 3052 cl49_bypass_txsm = 0; 3053 hg2_en = 0; 3054 scr_mode = 1; 3055 os_mode = 0; 3056 t_pma_btmx_mode = 0; 3057 } else if ((spd_intf == TEFMOD16_SPD_20G_MLD_X2) || 3058 (spd_intf == TEFMOD16_SPD_21G_MLD_HG_X2)) { 3059 t_fifo_mode = 3; 3060 t_enc_mode = 2; 3061 cl82_bypass_txsm = 0; 3062 hg2_en = 0; 3063 os_mode = 1; 3064 scr_mode = 4; 3065 t_pma_btmx_mode = 0; 3066 #ifdef TSCF_GEN1 3067 mld_swap_count = tx_am_timer_init_val; /* shorten from 0xfffc. For sim ? */ 3068 #endif 3069 } else if ((spd_intf == TEFMOD16_SPD_40G_MLD_X2) || 3070 (spd_intf == TEFMOD16_SPD_42G_MLD_HG_X2) || 3071 (spd_intf == TEFMOD16_SPD_50G_CR2) || 3072 (spd_intf == TEFMOD16_SPD_50G_KR2) || 3073 (spd_intf == TEFMOD16_SPD_50G_CR2_HG2) || 3074 (spd_intf == TEFMOD16_SPD_50G_KR2_HG2) || 3075 (spd_intf == TEFMOD16_SPD_53G_MLD_HG_X2)) { 3076 t_fifo_mode = 1; 3077 t_enc_mode = 2; 3078 cl82_bypass_txsm = 0; 3079 hg2_en = 0; 3080 scr_mode = 2; 3081 t_pma_btmx_mode = 1; 3082 os_mode = 0; 3083 #ifdef TSCF_GEN1 3084 mld_swap_count = tx_am_timer_init_val; /* shorten from 0xfffc. For sim ? */ 3085 #endif 3086 } else if ((spd_intf == TEFMOD16_SPD_40G_MLD_X4) || 3087 (spd_intf == TEFMOD16_SPD_50G_MLD_X4) || 3088 (spd_intf == TEFMOD16_SPD_42G_MLD_HG_X4) || 3089 (spd_intf == TEFMOD16_SPD_53G_MLD_HG_X4)) { 3090 t_fifo_mode = 1; 3091 t_enc_mode = 2; 3092 cl82_bypass_txsm = 0; 3093 hg2_en = 0; 3094 scr_mode = 5; 3095 t_pma_btmx_mode = 0; 3096 os_mode = 1; 3097 #ifdef TSCF_GEN1 3098 mld_swap_count = tx_am_timer_init_val; /* shorten from 0xfffc. For sim ? */ 3099 #endif 3100 } else if ((spd_intf == TEFMOD16_SPD_100G_MLD_X4) || 3101 (spd_intf == TEFMOD16_SPD_106G_MLD_HG_X4)) { 3102 t_fifo_mode = 2; 3103 t_enc_mode = 2; 3104 cl82_bypass_txsm = 0; 3105 hg2_en = 0; 3106 scr_mode = 3; 3107 t_pma_btmx_mode = 2; 3108 os_mode = 0; 3109 #ifdef TSCF_GEN1 3110 mld_swap_count = tx_am_timer_init_val; 3111 #endif 3112 } else if (spd_intf == TEFMOD16_SPD_10000 ) { /* 10G XAUI */ 3113 /* ------------------------------------ 0xc111 */ 3114 cl49_bypass_txsm = 1; 3115 /* ------------------------------------ 0xc113 */ 3116 scr_mode = 0x0; /* bypass scramble */ 3117 /* ------------------------------------ 0xa000 */ 3118 } else if (spd_intf == TEFMOD16_SPD_10000_HI ) { /* 10.6G HI XAUI */ 3119 /* ------------------------------------ 0xc111 */ 3120 cl49_bypass_txsm = 1; 3121 /* ------------------------------------ 0xc113 */ 3122 scr_mode = 0x0; /* bypass scramble */ 3123 /* ------------------------------------ 0xa000 */ 3124 } else if (spd_intf == TEFMOD16_SPD_10000_DXGXS) { 3125 /* ------------------------------------ 0xc111 */ 3126 cl49_bypass_txsm = 1; 3127 /* ------------------------------------ 0xc113 */ 3128 scr_mode = 0x0; /* bypass scramble */ 3129 /* ------------------------------------ 0xa000 */ 3130 } else if (spd_intf == TEFMOD16_SPD_20000) { /* 20G XAIU */ 3131 /* ------------------------------------ 0xc111 */ 3132 cl49_bypass_txsm = 1; 3133 /* ------------------------------------ 0xc113 */ 3134 scr_mode = 0x0; 3135 /* ------------------------------------ 0xa000 */ 3136 } else if (spd_intf == TEFMOD16_SPD_21000) { /* 20G XAIU */ 3137 /* ------------------------------------ 0xc111 */ 3138 cl49_bypass_txsm = 1; 3139 /* ------------------------------------ 0xc113 */ 3140 scr_mode = 0x2; 3141 /* ------------------------------------ 0xa000 */ 3142 } else if (spd_intf == TEFMOD16_SPD_20G_MLD_DXGXS ) { 3143 /* ------------------------------------ 0xc111 */ 3144 cl49_bypass_txsm = 0; 3145 /* --------------------- ---------------0xc113 */ 3146 scr_mode = 0x3; /* 64b66b scrambled */ 3147 /* ------------------------------------ 0xa000 */ 3148 #ifdef TSCF_GEN1 3149 mld_swap_count = tx_am_timer_init_val; /* shorten from 0xfffc. For sim ? */ 3150 #endif 3151 3152 /* 0xa000 default value in silicon is for dual port */ 3153 } else if ((spd_intf ==TEFMOD16_SPD_21G_HI_MLD_DXGXS)|| 3154 (spd_intf ==TEFMOD16_SPD_12773_HI_DXGXS)) { 3155 /* ------------------------------------ 0xc111 */ 3156 cl49_bypass_txsm = 0; 3157 hg2_en = 1; 3158 /*hg2_codec = 1; */ 3159 /* --------------------- ---------------0xc113 */ 3160 scr_mode = 0x3; /* 64b66b scrambled */ 3161 /* ------------------------------------ 0xa000 */ 3162 #ifdef TSCF_GEN1 3163 mld_swap_count = tx_am_timer_init_val; /* shorten from 0xfffc. For sim ? */ 3164 #endif 3165 3166 } else if ((spd_intf == TEFMOD16_SPD_20G_DXGXS)|| 3167 (spd_intf == TEFMOD16_SPD_21G_HI_DXGXS)) { 3168 /* ------------------------------------ 0xc111 */ 3169 cl49_bypass_txsm = 1; 3170 /* ------------------------------------ 0xc113 */ 3171 scr_mode = 0x1; /* 64b66b scrambled */ 3172 /* ------------------------------------ 0xa000 */ 3173 } else if ((spd_intf == TEFMOD16_SPD_42G_X4)|| 3174 (spd_intf == TEFMOD16_SPD_40G_X4)|| 3175 (spd_intf == TEFMOD16_SPD_25455) || 3176 (spd_intf == TEFMOD16_SPD_12773_DXGXS)) { 3177 /* ------------------------------------ 0xc111 */ 3178 cl49_bypass_txsm = 1; 3179 /* ------------------------------------ 0xc113 */ 3180 scr_mode = 0x1; /* 64b66b scrambled */ 3181 /* ------------------------------------ 0xa000 */ 3182 } else if (spd_intf == TEFMOD16_SPD_40G_XLAUI ) { 3183 /* ------------------------------------ 0xc111 */ 3184 cl49_bypass_txsm = 0; 3185 /* ------------------------------------ 0xc113 */ 3186 scr_mode = 0x3; /* 64b66b scrambled */ 3187 /* ------------------------------------ 0xa000 */ 3188 /* 3189 #if defined (_DV_TRIDENT2) 3190 mld_swap_count = tx_am_timer_init_val; 3191 #else 3192 mld_swap_count = 0xfffc; 3193 #endif 3194 */ 3195 } else if (spd_intf == TEFMOD16_SPD_42G_XLAUI ) { 3196 /* ------------------------------------ 0xc111 */ 3197 cl49_bypass_txsm = 0; 3198 hg2_en = 1; 3199 /*hg2_codec = 1;*/ 3200 /* ------------------------------------ 0xc113 */ 3201 scr_mode = 0x3; /* 64b66b scrambled */ 3202 /* ------------------------------------ 0xa000 */ 3203 /* 3204 #if defined (_DV_TRIDENT2) 3205 mld_swap_count = tx_am_timer_init_val; 3206 #else 3207 mld_swap_count = 0xfffc; 3208 #endif 3209 */ 3210 } 3211 if((spd_intf == TEFMOD16_SPD_10600_XFI_HG) || 3212 (spd_intf == TEFMOD16_SPD_21200_XFI_HG) || 3213 (spd_intf == TEFMOD16_SPD_26500_XFI_HG) || 3214 (spd_intf == TEFMOD16_SPD_21G_MLD_HG_X2) || 3215 (spd_intf == TEFMOD16_SPD_42G_MLD_HG_X4) || 3216 (spd_intf == TEFMOD16_SPD_53G_MLD_HG_X4) || 3217 (spd_intf == TEFMOD16_SPD_42G_MLD_HG_X2) || 3218 (spd_intf == TEFMOD16_SPD_53G_MLD_HG_X2) || 3219 (spd_intf == TEFMOD16_SPD_106G_MLD_HG_X4)) { 3220 /* not CL48 */ 3221 hg2_en = 1; 3222 } 3223 if (cntl) { 3224 TX_X4_MISCr_CLR(TX_X4_CONTROL0_MISCr_reg); 3225 TX_X4_MISCr_OS_MODEf_SET(TX_X4_CONTROL0_MISCr_reg, os_mode); 3226 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_MISCr(pc, TX_X4_CONTROL0_MISCr_reg)); 3227 3228 #ifdef TSCF_GEN1 3229 TX_X1_T_PMA_WTRMKr_CLR(TX_X1_CONTROL0_T_PMA_WATERMARKr_reg); 3230 TX_X1_T_PMA_WTRMKr_SINGLE_LANE_BITMUX_WATERMARKf_SET(TX_X1_CONTROL0_T_PMA_WATERMARKr_reg, 4); 3231 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X1_T_PMA_WTRMKr(pc, TX_X1_CONTROL0_T_PMA_WATERMARKr_reg)); 3232 #endif 3233 3234 TX_X2_CL82_0r_CLR(TX_X2_CONTROL0_CL82_0r_reg); 3235 #ifdef TSCF_GEN1 3236 TX_X2_CL82_0r_T_FIFO_MODEf_SET(TX_X2_CONTROL0_CL82_0r_reg, t_fifo_mode); 3237 #else 3238 TX_X4_ENC0r_CLR(TX_X4_CONTROL0_ENCODE_0r_reg); 3239 TX_X4_ENC0r_T_FIFO_MODEf_SET(TX_X4_CONTROL0_ENCODE_0r_reg, t_fifo_mode); 3240 #endif 3241 TX_X2_CL82_0r_CL82_BYPASS_TXSMf_SET(TX_X2_CONTROL0_CL82_0r_reg, cl82_bypass_txsm); 3242 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X2_CL82_0r(pc, TX_X2_CONTROL0_CL82_0r_reg)); 3243 3244 TX_X4_ENC0r_CLR(TX_X4_CONTROL0_ENCODE_0r_reg); 3245 TX_X4_ENC0r_T_ENC_MODEf_SET(TX_X4_CONTROL0_ENCODE_0r_reg, t_enc_mode); 3246 TX_X4_ENC0r_CL49_TX_TL_MODEf_SET(TX_X4_CONTROL0_ENCODE_0r_reg, cl49_tx_tl_mode); 3247 TX_X4_ENC0r_CL49_BYPASS_TXSMf_SET(TX_X4_CONTROL0_ENCODE_0r_reg, cl49_bypass_txsm); 3248 TX_X4_ENC0r_HG2_ENABLEf_SET(TX_X4_CONTROL0_ENCODE_0r_reg, hg2_en); 3249 PHYMOD_IF_ERR_RETURN 3250 (MODIFY_TX_X4_ENC0r(pc, TX_X4_CONTROL0_ENCODE_0r_reg)); 3251 3252 TX_X4_MISCr_CLR(TX_X4_CONTROL0_MISCr_reg); 3253 TX_X4_MISCr_SCR_MODEf_SET(TX_X4_CONTROL0_MISCr_reg, scr_mode); 3254 TX_X4_MISCr_T_PMA_BTMX_MODEf_SET(TX_X4_CONTROL0_MISCr_reg, t_pma_btmx_mode); 3255 PHYMOD_IF_ERR_RETURN 3256 (MODIFY_TX_X4_MISCr(pc, TX_X4_CONTROL0_MISCr_reg)); 3257 3258 #ifdef TSCF_GEN1 3259 /* 0xa000 */ 3260 TX_X2_MLD_SWP_CNTr_CLR(TX_X2_CONTROL0_MLD_SWAP_COUNTr_reg); 3261 TX_X2_MLD_SWP_CNTr_MLD_SWAP_COUNTf_SET(TX_X2_CONTROL0_MLD_SWAP_COUNTr_reg, mld_swap_count); 3262 /*if(mask) */ 3263 PHYMOD_IF_ERR_RETURN 3264 (MODIFY_TX_X2_MLD_SWP_CNTr(pc, TX_X2_CONTROL0_MLD_SWAP_COUNTr_reg)); 3265 #endif 3266 } else { 3267 /* no op */ 3268 return PHYMOD_E_NONE; 3269 } 3270 return PHYMOD_E_NONE; 3271 } 3272 #endif 3273 3274 #ifdef _DV_TB_ 3275 /*! 3276 @brief Local Fault/Remote Fault signalling enable for Tx and RX 3277 @param pc handle to current TSCF context (#PHYMOD_ST) 3278 @returns The value PHYMOD_E_NONE upon successful completion. 3279 @details 3280 This function is used to enable/disable Link Interrupt, Local Fault and 3281 Remote Fault signalling of any lane . 3282 3283 \li #PHYMOD_ST::per_lane_control[3:0] represents the mode (CL49, CL48, CL82). 3284 \li #PHYMOD_ST::per_lane_control[6] is for li; 3285 \li #PHYMOD_ST::per_lane_control[5] is for lf; 3286 \li #PHYMOD_ST::per_lane_control[4] is for rf; 3287 3288 This function reads/modifies the following registers: 3289 3290 \li cl49_tx : 0xc113 3291 \li cl49_rx : 0xc134 3292 \li cl48_tx : 0xa001 3293 \li cl82_tx : 0xa002 3294 \li cl48_cl82_rx : 0xa024 3295 */ 3296 3297 int tefmod16_lf_rf_control(PHYMOD_ST* pc) /* LF_RF_CONTROL */ 3298 { 3299 TEFMOD16_DBG_IN_FUNC_INFO(pc); 3300 return PHYMOD_E_NONE; 3301 } 3302 #endif 3303 3304 #ifdef _DV_TB_ 3305 /*! 3306 @brief set rx decoder of any particular lane 3307 3308 @param pc handle to current TSCF context (#PHYMOD_ST) 3309 3310 @returns The value PHYMOD_E_NONE upon successful completion. 3311 3312 This function is used to select decoder of any receive lane. 3313 3314 \li select encodeMode 3315 3316 This function reads/modifies the following registers: 3317 3318 \li descr_mode : 0xc130[15:14] 3319 \li dec_tl_mode : 0xc130[13:11] 3320 \li deskew_mode : 0xc130[10:8] 3321 \li dec_fsm_mode : 0xc130[7:5] 3322 \li cl36_en : 0xc134[0] 3323 3324 */ 3325 3326 /* for DV only ? CHECK Lpti */ 3327 int tefmod16_decode_set(PHYMOD_ST* pc) /* DECODE_SET */ 3328 { 3329 uint16_t descr_mode, dec_tl_mode, deskew_mode, dec_fsm_mode; 3330 uint16_t bypass_cl49rxsm, hg2_message_ivalid_code_enable, hg2_en; 3331 uint16_t bs_sm_sync_mode; 3332 uint16_t bs_sync_en; 3333 uint16_t bs_dist_mode; 3334 uint16_t bs_btmx_mode; 3335 /* uint16_t sync_code_sm_en; */ 3336 uint16_t rx_control0_misc0_en; 3337 int cntl; 3338 RX_X4_BLKSYNC_CFGr_t RX_X4_CONTROL0_BLKSYNC_CONFIGr_reg; 3339 RX_X4_DEC_CTL0r_t RX_X4_CONTROL0_DECODE_CONTROL_0r_reg; 3340 RX_X4_PCS_CTL0r_t RX_X4_CONTROL0_PCS_CONTROL_0r_reg; 3341 CL82_LANES_1_0_AM_BYTE2r_t CL82_AMS_LANES_1_0_AM_BYTE2r_reg; 3342 CL82_LN_1_AM_BYTE10r_t CL82_AMS_LANE_1_AM_BYTE10r_reg; 3343 CL82_LN_0_AM_BYTE10r_t CL82_AMS_LANE_0_AM_BYTE10r_reg; 3344 #ifdef TSCF_GEN1 3345 CL82_RX_AM_TMRr_t CL82_SHARED_CL82_RX_AM_TIMERr_reg; 3346 #else 3347 CL82_AM_TMRr_t CL82_SHARED_CL82_AM_TIMERr_reg; 3348 #endif 3349 3350 TEFMOD16_DBG_IN_FUNC_INFO(pc); 3351 cntl = pc->per_lane_control; 3352 descr_mode = 0x0; /* 00=bypass descrambler; 01=64b66b descrambler; 3353 10=8b10b descrambler */ 3354 dec_tl_mode = 0x0; /* 3'b000 - None; 3'b001 - cl49 64b66b mode; 3355 3'b010 - BRCM 64b66b mode; 3356 3'b011 - ATL - cl49/BRCM 64b66b mode; 3357 3'b100 - 8b10b mode - cl48 mode 3358 3'b101 - 8b10b mode - cl36 mode */ 3359 deskew_mode = 0x0; 3360 dec_fsm_mode = 0x0; /* {001:CL49}, {010:BRCM}, {011:ATL}, 3361 {100:CL48}, {101:CL36}, {110:CL82}, {111:NONE} */ 3362 bypass_cl49rxsm = 0x0; 3363 hg2_message_ivalid_code_enable = 0x1; 3364 hg2_en = 0; 3365 3366 /* cl48_dswin64b66b = 0; 3367 cl48_dswin8b10b = 0; 3368 sync_code_sm_en = 0; */ 3369 3370 rx_control0_misc0_en = 0; 3371 3372 if (cntl) { /* set decoder */ 3373 if(pc->spd_intf == TEFMOD16_SPD_1000_SGMII) { 3374 dec_tl_mode = 0x5; 3375 deskew_mode = 0x4; 3376 dec_fsm_mode = 0x5; 3377 hg2_message_ivalid_code_enable = 0x0; 3378 if (pc->plldiv == 40) { 3379 } else if (pc->plldiv == 66){ 3380 } 3381 } else if(pc->spd_intf == TEFMOD16_SPD_1G_20G) { 3382 } else if(pc->spd_intf == TEFMOD16_SPD_1G_25G) { 3383 } else if(pc->spd_intf == TEFMOD16_SPD_10000_XFI) { 3384 /* ------------------------------------ 0xc130 */ 3385 deskew_mode = 0x5; 3386 descr_mode = 0x1; 3387 dec_tl_mode = 0x1; 3388 dec_fsm_mode = 0x1; 3389 /* ------------------------------------ 0xc136 */ 3390 /* ------------------------------------ 0xc134 */ 3391 bypass_cl49rxsm = 0x0; 3392 3393 bs_sm_sync_mode = 1; 3394 bs_sync_en = 1; 3395 bs_dist_mode = 0; 3396 bs_btmx_mode = 0; 3397 } else if(pc->spd_intf == TEFMOD16_SPD_10600_XFI_HG) { 3398 /* ------------------------------------ 0xc130 */ 3399 deskew_mode = 0x5; 3400 descr_mode = 0x1; 3401 dec_tl_mode = 0x1; 3402 dec_fsm_mode = 0x1; 3403 /* ------------------------------------ 0xc136 */ 3404 /* ------------------------------------ 0xc134 */ 3405 bypass_cl49rxsm = 0x0; 3406 3407 bs_sm_sync_mode = 1; 3408 bs_sync_en = 1; 3409 bs_dist_mode = 0; 3410 bs_btmx_mode = 0; 3411 hg2_en = 1; 3412 } else if ((pc->spd_intf == TEFMOD16_SPD_20000_XFI) || 3413 (pc->spd_intf == TEFMOD16_SPD_21200_XFI_HG) || 3414 (pc->spd_intf == TEFMOD16_SPD_25000_XFI) || 3415 (pc->spd_intf == TEFMOD16_SPD_26500_XFI_HG)) { 3416 bs_sm_sync_mode = 1; 3417 bs_sync_en = 1; 3418 bs_dist_mode = 0; 3419 bs_btmx_mode = 0; 3420 deskew_mode = 5; 3421 descr_mode = 1; 3422 dec_tl_mode = 1; 3423 dec_fsm_mode = 1; 3424 } else if ((pc->spd_intf == TEFMOD16_SPD_20G_MLD_X2) || 3425 (pc->spd_intf == TEFMOD16_SPD_21G_MLD_HG_X2)) { 3426 bs_sm_sync_mode = 0; 3427 bs_sync_en = 1; 3428 bs_dist_mode = 2; 3429 bs_btmx_mode = 0; 3430 deskew_mode = 1; 3431 descr_mode = 2; 3432 dec_tl_mode = 2; 3433 dec_fsm_mode = 2; 3434 } else if ((pc->spd_intf == TEFMOD16_SPD_40G_MLD_X4) || 3435 (pc->spd_intf == TEFMOD16_SPD_50G_MLD_X4) || 3436 (pc->spd_intf == TEFMOD16_SPD_42G_MLD_HG_X4) || 3437 (pc->spd_intf == TEFMOD16_SPD_53G_MLD_HG_X4)) { 3438 bs_sm_sync_mode = 0; 3439 bs_sync_en = 1; 3440 bs_dist_mode = 2; 3441 bs_btmx_mode = 0; 3442 deskew_mode = 2; 3443 descr_mode = 2; 3444 dec_tl_mode = 2; 3445 dec_fsm_mode = 2; 3446 } else if ((pc->spd_intf == TEFMOD16_SPD_40G_MLD_X2) || 3447 (pc->spd_intf == TEFMOD16_SPD_42G_MLD_HG_X2) || 3448 (pc->spd_intf == TEFMOD16_SPD_50G_MLD_X2) || 3449 (pc->spd_intf == TEFMOD16_SPD_53G_MLD_HG_X2)) { 3450 bs_sm_sync_mode = 0; 3451 bs_sync_en = 1; 3452 bs_dist_mode = 1; 3453 bs_btmx_mode = 1; 3454 deskew_mode = 3; 3455 descr_mode = 2; 3456 dec_tl_mode = 2; 3457 dec_fsm_mode = 2; 3458 } else if ((pc->spd_intf == TEFMOD16_SPD_100G_MLD_X4) || 3459 (pc->spd_intf == TEFMOD16_SPD_106G_MLD_HG_X4)) { 3460 bs_sm_sync_mode = 0; 3461 bs_sync_en = 1; 3462 bs_dist_mode = 3; 3463 bs_btmx_mode = 2; 3464 deskew_mode = 4; 3465 descr_mode = 2; 3466 dec_tl_mode = 2; 3467 dec_fsm_mode = 2; 3468 } else { 3469 PHYMOD_DEBUG_ERROR(("%-22s ERROR: p=%0d undefined spd_intf=%0d(%s)\n", __func__, pc->port, pc->spd_intf, 3470 e2s_tefmod16_spd_intfc_type_t[pc->spd_intf])); 3471 return PHYMOD_E_FAIL; 3472 } 3473 /* HG setting */ 3474 /* if((pc->ctrl_type & TEFMOD16_CTRL_TYPE_HG)) {} */ 3475 if((pc->spd_intf == TEFMOD16_SPD_10600_XFI_HG) || 3476 (pc->spd_intf == TEFMOD16_SPD_21200_XFI_HG) || 3477 (pc->spd_intf == TEFMOD16_SPD_26500_XFI_HG) || 3478 (pc->spd_intf == TEFMOD16_SPD_21G_MLD_HG_X2) || 3479 (pc->spd_intf == TEFMOD16_SPD_42G_MLD_HG_X4) || 3480 (pc->spd_intf == TEFMOD16_SPD_53G_MLD_HG_X4) || 3481 (pc->spd_intf == TEFMOD16_SPD_42G_MLD_HG_X2) || 3482 (pc->spd_intf == TEFMOD16_SPD_53G_MLD_HG_X2) || 3483 (pc->spd_intf == TEFMOD16_SPD_106G_MLD_HG_X4)) { 3484 /* not CL48 */ 3485 hg2_en = 1; 3486 } 3487 3488 /* 0xc130 */ 3489 RX_X4_PCS_CTL0r_CLR(RX_X4_CONTROL0_PCS_CONTROL_0r_reg); 3490 RX_X4_PCS_CTL0r_DESCR_MODEf_SET(RX_X4_CONTROL0_PCS_CONTROL_0r_reg, descr_mode); 3491 RX_X4_PCS_CTL0r_DEC_TL_MODEf_SET(RX_X4_CONTROL0_PCS_CONTROL_0r_reg, dec_tl_mode); 3492 RX_X4_PCS_CTL0r_DESKEW_MODEf_SET(RX_X4_CONTROL0_PCS_CONTROL_0r_reg, deskew_mode); 3493 RX_X4_PCS_CTL0r_DEC_FSM_MODEf_SET(RX_X4_CONTROL0_PCS_CONTROL_0r_reg, dec_fsm_mode); 3494 3495 PHYMOD_IF_ERR_RETURN 3496 (MODIFY_RX_X4_PCS_CTL0r(pc, RX_X4_CONTROL0_PCS_CONTROL_0r_reg)); 3497 3498 /* 0xc134 */ 3499 RX_X4_DEC_CTL0r_CLR(RX_X4_CONTROL0_DECODE_CONTROL_0r_reg); 3500 RX_X4_DEC_CTL0r_BYPASS_CL49RXSMf_SET(RX_X4_CONTROL0_DECODE_CONTROL_0r_reg, bypass_cl49rxsm); 3501 RX_X4_DEC_CTL0r_HG2_MESSAGE_INVALID_CODE_ENABLEf_SET(RX_X4_CONTROL0_DECODE_CONTROL_0r_reg, hg2_message_ivalid_code_enable); 3502 RX_X4_DEC_CTL0r_HG2_ENABLEf_SET(RX_X4_CONTROL0_DECODE_CONTROL_0r_reg, hg2_en); 3503 3504 PHYMOD_IF_ERR_RETURN 3505 (MODIFY_RX_X4_DEC_CTL0r(pc, RX_X4_CONTROL0_DECODE_CONTROL_0r_reg)); 3506 3507 RX_X4_BLKSYNC_CFGr_CLR(RX_X4_CONTROL0_BLKSYNC_CONFIGr_reg); 3508 RX_X4_BLKSYNC_CFGr_BS_SM_SYNC_MODEf_SET(RX_X4_CONTROL0_BLKSYNC_CONFIGr_reg, bs_sm_sync_mode); 3509 RX_X4_BLKSYNC_CFGr_BS_SYNC_ENf_SET(RX_X4_CONTROL0_BLKSYNC_CONFIGr_reg, bs_sync_en); 3510 RX_X4_BLKSYNC_CFGr_BS_DIST_MODEf_SET(RX_X4_CONTROL0_BLKSYNC_CONFIGr_reg, bs_dist_mode); 3511 RX_X4_BLKSYNC_CFGr_BS_BTMX_MODEf_SET(RX_X4_CONTROL0_BLKSYNC_CONFIGr_reg, bs_btmx_mode); 3512 3513 PHYMOD_IF_ERR_RETURN 3514 (MODIFY_RX_X4_BLKSYNC_CFGr(pc, RX_X4_CONTROL0_BLKSYNC_CONFIGr_reg)); 3515 /* --Addr=0x9220 ------------------------- */ 3516 /* 3517 if((pc->spd_intf ==TEFMOD16_SPD_10000)|| 3518 (pc->spd_intf ==TEFMOD16_SPD_10000_HI)|| 3519 (pc->spd_intf ==TEFMOD16_SPD_10000_DXGXS)|| 3520 (pc->spd_intf ==TEFMOD16_SPD_20000)){ 3521 data = 0x0444; 3522 mask = 0xffff; 3523 sync_code_sm_en = 1; 3524 } else if ((pc->spd_intf ==TEFMOD16_SPD_42G_X4)|| 3525 (pc->spd_intf ==TEFMOD16_SPD_40G_X4)|| 3526 (pc->spd_intf ==TEFMOD16_SPD_25455)|| 3527 (pc->spd_intf ==TEFMOD16_SPD_21G_HI_DXGXS)|| 3528 (pc->spd_intf ==TEFMOD16_SPD_20G_DXGXS)|| 3529 (pc->spd_intf == TEFMOD16_SPD_12773_DXGXS) ) { 3530 data = 0x0323; 3531 mask = 0xffff; 3532 sync_code_sm_en = 1; 3533 } 3534 3535 if(sync_code_sm_en) { 3536 PHYMOD_IF_ERR_RETURN 3537 (MODIFY_RX_X1_CONTROL0_DECODE_CONTROL_0r(pc->unit, pc, data, mask)); 3538 } 3539 */ 3540 if(rx_control0_misc0_en) { 3541 /* rx_control0_misc0_en is made 0 3542 RX_X2_MISC0r_t RX_X2_CONTROL0_MISC_0r_reg; 3543 RX_X2_MISC0r_CLR(RX_X2_CONTROL0_MISC_0r_reg); 3544 RX_X2_MISC0r_SET(RX_X2_CONTROL0_MISC_0r_reg, ); 3545 PHYMOD_IF_ERR_RETURN(MODIFY_RX_X2_MISC0r(pc, RX_X2_CONTROL0_MISC_0r_reg)); 3546 */ 3547 } 3548 /* --Addr=0xc131 ------------------------- */ 3549 if((pc->spd_intf == TEFMOD16_SPD_20G_MLD_DXGXS) || 3550 (pc->spd_intf == TEFMOD16_SPD_21G_HI_MLD_DXGXS) || 3551 (pc->spd_intf == TEFMOD16_SPD_40G_XLAUI) || 3552 (pc->spd_intf == TEFMOD16_SPD_42G_XLAUI) || 3553 (pc->spd_intf == TEFMOD16_SPD_12773_HI_DXGXS) ) { 3554 /*data = 0; */ 3555 /*PHYMOD_IF_ERR_RETURN (MODIFY_RX_X4_CONTROL0_FEC_0r(pc->unit, pc, data, mask));*/ 3556 } 3557 /* --Addr=0x9123 ------------------------- */ 3558 /* for simualtion */ 3559 /* #if defined (_DV_TRIDENT2) */ 3560 3561 #ifdef TSCF_GEN1 3562 CL82_RX_AM_TMRr_CLR(CL82_SHARED_CL82_RX_AM_TIMERr_reg); 3563 #else 3564 CL82_AM_TMRr_CLR(CL82_SHARED_CL82_AM_TIMERr_reg); 3565 #endif 3566 3567 /*ABHIif((pc->spd_intf == TEFMOD16_SPD_40G_XLAUI)||(pc->spd_intf == TEFMOD_SPD_42G_XLAUI)) { 3568 data = pc->rx_am_timer_init_val; 3569 mask = 0xffff; 3570 CL82_RX_AM_TMRr_SET(CL82_SHARED_CL82_RX_AM_TIMERr_reg, pc->rx_am_timer_init_val); 3571 PHYMOD_IF_ERR_RETURN 3572 (MODIFY_CL82_RX_AM_TMRr(pc, CL82_SHARED_CL82_RX_AM_TIMERr_reg)); 3573 }*/ 3574 if((pc->spd_intf == TEFMOD16_SPD_20G_MLD_DXGXS) || 3575 (pc->spd_intf == TEFMOD16_SPD_20G_MLD_X2) || 3576 (pc->spd_intf == TEFMOD16_SPD_21G_MLD_HG_X2) || 3577 (pc->spd_intf == TEFMOD16_SPD_40G_MLD_X4) || 3578 (pc->spd_intf == TEFMOD16_SPD_50G_MLD_X4) || 3579 (pc->spd_intf == TEFMOD16_SPD_40G_MLD_X2) || 3580 (pc->spd_intf == TEFMOD16_SPD_42G_MLD_HG_X2) || 3581 (pc->spd_intf == TEFMOD16_SPD_50G_MLD_X2) || 3582 (pc->spd_intf == TEFMOD16_SPD_100G_MLD_X4) || 3583 (pc->spd_intf == TEFMOD16_SPD_53G_MLD_HG_X2) || 3584 (pc->spd_intf == TEFMOD16_SPD_42G_MLD_HG_X4) || 3585 (pc->spd_intf == TEFMOD16_SPD_53G_MLD_HG_X4) || 3586 (pc->spd_intf == TEFMOD16_SPD_106G_MLD_HG_X4)|| 3587 (pc->spd_intf == TEFMOD16_SPD_40G_XLAUI) || 3588 (pc->spd_intf == TEFMOD16_SPD_42G_XLAUI)) { 3589 #ifdef TSCF_GEN1 3590 CL82_RX_AM_TMRr_SET(CL82_SHARED_CL82_RX_AM_TIMERr_reg, pc->rx_am_timer_init_val); 3591 PHYMOD_IF_ERR_RETURN 3592 (MODIFY_CL82_RX_AM_TMRr(pc, CL82_SHARED_CL82_RX_AM_TIMERr_reg)); 3593 #else 3594 CL82_AM_TMRr_SET(CL82_SHARED_CL82_AM_TIMERr_reg, pc->rx_am_timer_init_val); 3595 PHYMOD_IF_ERR_RETURN 3596 (MODIFY_CL82_AM_TMRr(pc, CL82_SHARED_CL82_AM_TIMERr_reg)); 3597 #endif 3598 } 3599 /* #endif */ 3600 /* --Addr=0x9130 ------------------------- */ 3601 if((pc->spd_intf == TEFMOD16_SPD_20G_MLD_DXGXS)) { 3602 CL82_LN_0_AM_BYTE10r_CLR(CL82_AMS_LANE_0_AM_BYTE10r_reg); 3603 CL82_LN_0_AM_BYTE10r_SET(CL82_AMS_LANE_0_AM_BYTE10r_reg, 0x7690); 3604 PHYMOD_IF_ERR_RETURN 3605 (MODIFY_CL82_LN_0_AM_BYTE10r(pc, CL82_AMS_LANE_0_AM_BYTE10r_reg)); 3606 } 3607 /* --Addr=0x9131 ------------------------- */ 3608 if((pc->spd_intf == TEFMOD16_SPD_20G_MLD_DXGXS)) { 3609 CL82_LN_1_AM_BYTE10r_CLR(CL82_AMS_LANE_1_AM_BYTE10r_reg); 3610 CL82_LN_1_AM_BYTE10r_SET(CL82_AMS_LANE_1_AM_BYTE10r_reg, 0xc4f0); 3611 PHYMOD_IF_ERR_RETURN 3612 (MODIFY_CL82_LN_1_AM_BYTE10r(pc, CL82_AMS_LANE_1_AM_BYTE10r_reg)); 3613 } 3614 /* --Addr=0x9132 ------------------------- */ 3615 if((pc->spd_intf == TEFMOD16_SPD_20G_MLD_DXGXS)) { 3616 CL82_LANES_1_0_AM_BYTE2r_CLR(CL82_AMS_LANES_1_0_AM_BYTE2r_reg); 3617 CL82_LANES_1_0_AM_BYTE2r_SET(CL82_AMS_LANES_1_0_AM_BYTE2r_reg, 0xe647); 3618 PHYMOD_IF_ERR_RETURN 3619 (MODIFY_CL82_LANES_1_0_AM_BYTE2r(pc, CL82_AMS_LANES_1_0_AM_BYTE2r_reg)); 3620 } 3621 3622 if(pc->ctrl_type & TEFMOD16_CTRL_TYPE_FAULT_DIS) { 3623 pc->per_lane_control = TEFMOD16_FAULT_CL49 | TEFMOD_FAULT_CL48 | TEFMOD_FAULT_CL82; 3624 /* li, lf, rf =0 */ 3625 tefmod16_lf_rf_control(pc); 3626 } else { 3627 pc->per_lane_control = 3628 (TEFMOD16_FAULT_RF | TEFMOD_FAULT_LF | TEFMOD_FAULT_LI)<<4 | 3629 (TEFMOD16_FAULT_CL49 | TEFMOD_FAULT_CL48 | TEFMOD_FAULT_CL82); 3630 tefmod16_lf_rf_control(pc); 3631 } 3632 } else { /* if ~cntl */ 3633 /* no op */ 3634 return PHYMOD_E_NONE; 3635 } 3636 return PHYMOD_E_NONE; 3637 } 3638 #endif 3639 3640 #ifdef _SDK_TEFMOD16_ 3641 3642 /** 3643 @brief Set the AN Portmode and Single Port for AN of TSCF. 3644 @param pc handle to current TSCF context (#PHYMOD_ST) 3645 @param num_of_lanes Number of lanes in this port 3646 @param starting_lane first lane in the port 3647 @param single_port Single port or not 3648 @returns PHYMOD_E_NONE if successful. PHYMOD_E_FAIL else. 3649 @details 3650 3651 This function can be called multiple times.Elements of #PHYMOD_ST should be 3652 initialized to required values prior to calling this function. The following 3653 sub-configurations are performed here. 3654 3655 \li Set pll divider for VCO setting (0x9000[12, 11:8]). pll divider is calculated from max_speed. 3656 3657 */ 3658 3659 int tefmod16_set_an_single_port_mode(PHYMOD_ST* pc, int an_enable) /* SET_AN_PORT_MODE */ 3660 { 3661 MAIN0_SETUPr_t reg_setup; 3662 SC_X4_CTLr_t xgxs_x4_ctrl; 3663 phymod_access_t phy_copy; 3664 3665 3666 PHYMOD_MEMCPY(&phy_copy, pc, sizeof(phy_copy)); 3667 SC_X4_CTLr_CLR(xgxs_x4_ctrl); 3668 3669 TEFMOD16_DBG_IN_FUNC_INFO(pc); 3670 TEFMOD16_DBG_IN_FUNC_VIN_INFO(pc,("an_enable %d \n", an_enable)); 3671 3672 MAIN0_SETUPr_CLR(reg_setup); 3673 PHYMOD_IF_ERR_RETURN (READ_MAIN0_SETUPr(pc, ®_setup)); 3674 3675 /*Ref clock selection tied to 156.25MHz */ 3676 MAIN0_SETUPr_REFCLK_SELf_SET(reg_setup, 0x3); 3677 3678 /*Setting single port mode*/ 3679 MAIN0_SETUPr_SINGLE_PORT_MODEf_SET(reg_setup, an_enable); 3680 /*if signle port mode is set and not single port mode, we need 3681 to disable the sister port */ 3682 if (an_enable) { 3683 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(xgxs_x4_ctrl, 0); 3684 phy_copy.lane_mask= 0xf; 3685 MODIFY_SC_X4_CTLr(&phy_copy, xgxs_x4_ctrl); 3686 } else { 3687 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(xgxs_x4_ctrl, 1); 3688 phy_copy.lane_mask= 0xf; 3689 MODIFY_SC_X4_CTLr(pc, xgxs_x4_ctrl); 3690 } 3691 3692 PHYMOD_IF_ERR_RETURN(MODIFY_MAIN0_SETUPr(pc,reg_setup)); 3693 3694 return PHYMOD_E_NONE; 3695 3696 } 3697 3698 /** 3699 @brief Set the AN Portmode and Single Port for AN of TSCF. 3700 @param pc handle to current TSCF context (#PHYMOD_ST) 3701 @param num_of_lanes Number of lanes in this port 3702 @param starting_lane first lane in the port 3703 @param single_port Single port or not 3704 @returns PHYMOD_E_NONE if successful. PHYMOD_E_FAIL else. 3705 @details 3706 3707 This function can be called multiple times.Elements of #PHYMOD_ST should be 3708 initialized to required values prior to calling this function. The following 3709 sub-configurations are performed here. 3710 3711 \li Set pll divider for VCO setting (0x9000[12, 11:8]). pll divider is calculated from max_speed. 3712 3713 */ 3714 int tefmod16_set_an_port_mode(PHYMOD_ST* pc, int num_of_lanes, int starting_lane, int single_port) /* SET_AN_PORT_MODE */ 3715 { 3716 MAIN0_SETUPr_t reg_setup; 3717 SC_X4_CTLr_t xgxs_x4_ctrl; 3718 phymod_access_t phy_copy; 3719 3720 PHYMOD_MEMCPY(&phy_copy, pc, sizeof(phy_copy)); 3721 SC_X4_CTLr_CLR(xgxs_x4_ctrl); 3722 3723 TEFMOD16_DBG_IN_FUNC_INFO(pc); 3724 TEFMOD16_DBG_IN_FUNC_VIN_INFO(pc,("num_of_lanes: %d, starting_lane: %d, single_port: %d", num_of_lanes, starting_lane, single_port)); 3725 3726 MAIN0_SETUPr_CLR(reg_setup); 3727 PHYMOD_IF_ERR_RETURN (READ_MAIN0_SETUPr(pc, ®_setup)); 3728 3729 /*Ref clock selection tied to 156.25MHz */ 3730 MAIN0_SETUPr_REFCLK_SELf_SET(reg_setup, 0x3); 3731 3732 /*Setting single port mode*/ 3733 MAIN0_SETUPr_SINGLE_PORT_MODEf_SET(reg_setup, single_port); 3734 /*if signle port mode is set and not single port mode, we need 3735 to disable the sister port */ 3736 if (pc->lane_mask != 0xf) { 3737 if (single_port) { 3738 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(xgxs_x4_ctrl, 0); 3739 phy_copy.lane_mask= 0xf; 3740 MODIFY_SC_X4_CTLr(&phy_copy, xgxs_x4_ctrl); 3741 } else { 3742 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(xgxs_x4_ctrl, 1); 3743 MODIFY_SC_X4_CTLr(pc, xgxs_x4_ctrl); 3744 } 3745 /*phy_copy.lane_mask= 0xf; 3746 MODIFY_SC_X4_CTLr(&phy_copy, xgxs_x4_ctrl); */ 3747 } else { 3748 if (single_port) { 3749 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(xgxs_x4_ctrl, 0); 3750 MODIFY_SC_X4_CTLr(pc, xgxs_x4_ctrl); 3751 } else { 3752 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(xgxs_x4_ctrl, 1); 3753 MODIFY_SC_X4_CTLr(pc, xgxs_x4_ctrl); 3754 } 3755 } 3756 3757 PHYMOD_IF_ERR_RETURN(MODIFY_MAIN0_SETUPr(pc,reg_setup)); 3758 3759 return PHYMOD_E_NONE; 3760 3761 } /* tefmod16_set_an_port_mode(PHYMOD_ST* pc, int num_of_lanes, int starting_lane, int single_port) */ 3762 #endif /* _SDK_TEFMOD16_ */ 3763 3764 3765 #ifdef _DV_TB_ 3766 /*! 3767 @brief Programs the speed mode for a particular lane 3768 @param pc handle to current TSCF context (#PHYMOD_ST) 3769 @returns PHYMOD_E_NONE if no errors. PHYMOD_EERROR else. 3770 pc->accData nozero if PLL is needed to restarted with different value; 3771 @details 3772 This function sets the TEF into a particular speed mode if per_lane_control= 3773 (1|(aspd<<4)). If per_lane_control=0, the function tells us PLLdiv is required 3774 to be changed or not by return the new pll value in pc->accData. If no change 3775 is required, then return 0 in accData. 3776 If per_lane_control = 2; then pc->accData returns plldiv in the register. 3777 If per_lane_control = 1; set to the desired speed. 3778 3779 To set the desired speed, set the following fields of #PHYMOD_ST 3780 3781 \li #PHYMOD_ST::lane_select to the lane number(s) 3782 \li #PHYMOD_ST::spd_intf to a value from enumerated type #tefmod16_spd_intfc_type_t 3783 \li #PHYMOD_ST::port_type to a type from the enumerated type #tefmod16_port_type_t 3784 \li #PHYMOD_ST::os_type to a type from the enumerated type #tefmod16_os_type 3785 3786 Note that legitimate combinations for these fields must be used; otherwise 3787 ill-defined behavior may result. 3788 3789 This function must be called once for combo mode and once per lane for 3790 indepedent lane mode. Only if all lanes are being set to the same 3791 speed-interface can this function be called once for all lanes. Before calling 3792 this function, the PLL sequencer must be disabled via the function 3793 #tefmod16_pll_sequencer_control(). After calling this function, the PLL sequencer 3794 must be enabled via the same function. 3795 3796 To program multiple lanes in independent lane mode, it is recommended to 3797 disable the PLL sequencer, call this function once for every lane being 3798 programmed, and then enable the PLL sequencer. 3799 3800 This function modifies the following registers: 3801 3802 \li force_ln_mode (0xC001[8]), force_speed (0XC001[7:0]), force_oscdr_mode_val (0xC001[14:11]) 3803 \li set pcs mode (encodeMode) (0xC110[4:2]) 3804 3805 The following speeds are not implemented. 3806 \li TEFMOD16_SPD_10000_DXGXS_SCR 3807 \li TEFMOD16_SPD_15000 3808 \li TEFMOD16_SPD_2000 3809 \li TEFMOD16_SPD_6364_SINGLE 3810 3811 When accData return 1, upper layer needs to adjust the plldiv of other 3812 lanes/tefmod to prevent unnecessary PLL restart when other lanes/tefmod is 3813 called. 3814 */ 3815 3816 int tefmod16_set_spd_intf(PHYMOD_ST* pc) /* SET_SPD_INTF */ 3817 { 3818 int plldiv, rv; 3819 uint32_t plldiv_r_val; 3820 3821 tefmod16_spd_intfc_type_t spd_intf; 3822 int port_mode_sel_restart; 3823 /* 3824 0x0 = DEFAULT 3825 0x1 = SFP_OPT 3826 0x2 = SFP_DAC 3827 0x3 = XLAUI 3828 0x4 = FORCE_OSDFE 3829 0x5 = FORCE_BRDFE 3830 0x6 = SW_CL72 3831 0x7 = CL72_woAN 3832 0x8 = SFP_OPT_PF_TEMP_COMP 3833 */ 3834 /* #define SR4 0x1 3835 #define SFI_DAC 0x2 3836 #define XLAUI 0x3 3837 #define FORCE_OSDFE 0x4 3838 #define FORCE_BRDFE 0x5 3839 #define SW_CL72 0x6 3840 #define FORCED_MODE_CL72 0x7 3841 #define FORCE_OS 0xF 3842 */ 3843 TEFMOD16_DBG_IN_FUNC_INFO(pc); 3844 3845 #ifdef _DV_TB_ 3846 spd_intf = pc->spd_intf; 3847 pc->accAddr = ((pc->unit) << 16) | (pc->port); 3848 #endif 3849 3850 if (pc->spd_intf > TEFMOD16_SPD_ILLEGAL) { 3851 PHYMOD_DEBUG_ERROR(("%-22s ERROR: Bad spd-intf: %d > TEFMOD16_SPD_ILLEGAL\n", 3852 __func__, pc->spd_intf)); 3853 return PHYMOD_E_PARAM; 3854 } else { 3855 if (pc->verbosity ) 3856 PHYMOD_DEBUG_ERROR(("%-22s: %s[%d]\n",__func__,e2s_tefmod16_spd_intfc_type_t[pc->spd_intf], 3857 e2n_tefmod16_spd_intfc_type_t[pc->spd_intf])); 3858 } 3859 /* pll div calculation; assume refclk=156 */ 3860 plldiv = 66; /* default */ 3861 if (spd_intf == TEFMOD16_SPD_1000_SGMII) { 3862 if((pc->plldiv==40)||(pc->plldiv==66)) { 3863 plldiv = pc->plldiv; 3864 } else { 3865 plldiv = 40; 3866 } 3867 plldiv = 40; 3868 /* speed_mii = IEEE0BLK_MIICNTL_MANUAL_SPEED1_BITS << 3869 IEEE0BLK_MIICNTL_MANUAL_SPEED1_SHIFT; MII_CTRL_SS_1000; */ 3870 /* remove TEFMOD16_SPD_1000_FIBER */ 3871 /* speed_mii = PMD_IEEE0BLK_PMD_IEEECONTROL1_SPEEDSELECTION1_MASK; */ 3872 } else if (spd_intf == TEFMOD16_SPD_10000_XFI) { 3873 plldiv = 66; 3874 } else if (spd_intf == TEFMOD16_SPD_10600_XFI_HG) { 3875 plldiv = 70; 3876 } else if (spd_intf == TEFMOD16_SPD_20000_XFI) { 3877 plldiv = 132; 3878 } else if (spd_intf == TEFMOD16_SPD_21200_XFI_HG) { 3879 plldiv = 140; 3880 } else if (spd_intf == TEFMOD16_SPD_25000_XFI) { 3881 plldiv = 165; 3882 } else if (spd_intf == TEFMOD16_SPD_26500_XFI_HG) { 3883 plldiv = 175; 3884 } else if (spd_intf == TEFMOD16_SPD_20G_MLD_X2) { 3885 plldiv = 66; 3886 } else if (spd_intf == TEFMOD16_SPD_21G_MLD_HG_X2) { 3887 plldiv = 70; 3888 } else if (spd_intf == TEFMOD16_SPD_40G_MLD_X2) { 3889 plldiv = 132; 3890 } else if (spd_intf == TEFMOD16_SPD_42G_MLD_HG_X2) { 3891 plldiv = 140; 3892 } else if (spd_intf == TEFMOD16_SPD_50G_MLD_X2) { 3893 plldiv = 165; 3894 } else if (spd_intf == TEFMOD16_SPD_53G_MLD_HG_X2) { 3895 plldiv = 175; 3896 } else if (spd_intf == TEFMOD16_SPD_40G_MLD_X4) { 3897 plldiv = 66; 3898 } else if (spd_intf == TEFMOD16_SPD_42G_MLD_HG_X4) { 3899 plldiv = 70; 3900 } else if (spd_intf == TEFMOD16_SPD_50G_MLD_X4) { 3901 plldiv = 165; 3902 } else if (spd_intf == TEFMOD16_SPD_53G_MLD_HG_X4) { 3903 plldiv = 175; 3904 } else if (spd_intf == TEFMOD16_SPD_100G_MLD_X4) { 3905 plldiv = 165; 3906 } else if (spd_intf == TEFMOD16_SPD_106G_MLD_HG_X4) { 3907 plldiv = 175; 3908 } 3909 rv = PHYMOD_E_NONE; 3910 3911 port_mode_sel_restart = 0; 3912 3913 if(pc->per_lane_control !=0x2) { 3914 tefmod16_update_port_mode_select(pc, pc->port_type, pc->this_lane, pc->tsc_clk_freq_pll_by_48, pc->pll_reset_en); 3915 port_mode_sel_restart = pc->accData; 3916 } 3917 pc->accData = 0; 3918 /* read back plldiv */ 3919 tefmod16_get_plldiv(pc, &plldiv_r_val); 3920 3921 if( (pc->plldiv != plldiv_r_val)|| port_mode_sel_restart) { 3922 if( pc->verbosity ) 3923 PHYMOD_DEBUG_ERROR(("%-22s: p=%0d pc->plldiv:%d mismatched reg plldiv=%0d exp \ 3924 plldiv=%0d mode_restart=%0d\n", __func__, pc->port, pc->plldiv, 3925 plldiv_r_val, plldiv, port_mode_sel_restart)); 3926 pc->plldiv = 0 ; 3927 } 3928 rv = PHYMOD_E_NONE; 3929 3930 if(pc->per_lane_control == 0 ) { 3931 PHYMOD_DEBUG_ERROR(("%-22s: p=%0d set_spd_intf probed\n", __func__, pc->port)); 3932 return rv; 3933 } else if(pc->per_lane_control == 2) { 3934 pc->accData = plldiv_r_val; 3935 PHYMOD_DEBUG_ERROR(("%-22s: p=%0d set_spd_intf get reg plldiv=%0d\n", 3936 __func__, pc->port, plldiv_r_val)); 3937 return rv; 3938 } 3939 pc->per_lane_control=1; 3940 rv |= tefmod16_credit_set(pc); 3941 pc->per_lane_control=1; 3942 rv |= tefmod16_encode_set(pc, pc->per_lane_control, pc->spd_intf, pc->tx_am_timer_init_val); 3943 pc->per_lane_control=1; 3944 rv |= tefmod16_decode_set(pc); 3945 3946 return rv; 3947 3948 } /* tefmod16_set_spd_intf(PHYMOD_ST* pc) */ 3949 #endif /* _DV_TB_ */ 3950 3951 /*! 3952 @brief supports per field override 3953 @param pc handle to current TSCF context (#PHYMOD_ST) 3954 @param per_field_override_en Controls which field to override 3955 @returns PHYMOD_E_NONE if no errors. PHYMOD_EERROR else. 3956 @details 3957 TBD 3958 */ 3959 int tefmod16_set_override_0(PHYMOD_ST* pc, int per_field_override_en) /* OVERRIDE_SET */ 3960 { 3961 int or_value; 3962 override_type_t or_en; 3963 RX_X4_PCS_CTL0r_t RX_X4_CONTROL0_PCS_CONTROL_0r_reg; 3964 SC_X4_SC_X4_OVRRr_t SC_X4_CONTROL_LANE_OVERRIDEr_reg; 3965 SC_X1_SPD_OVRR0_0r_t SC_X1_SPEED_OVERRIDE0r_reg; 3966 TX_X4_ENC0r_t TX_X4_CONTROL0_ENCODE_0r_reg; 3967 TX_X4_MISCr_t TX_X4_CONTROL0_MISCr_reg; 3968 SC_X4_FLD_OVRR_EN0_TYPEr_t SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg; 3969 SC_X4_FLD_OVRR_EN1_TYPEr_t SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg; 3970 3971 TEFMOD16_DBG_IN_FUNC_INFO(pc); 3972 or_en = (override_type_t) (per_field_override_en >> 16); 3973 3974 or_value = per_field_override_en & 0x0000ffff; 3975 3976 switch(or_en) { 3977 case OVERRIDE_CLEAR: 3978 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 3979 SC_X4_FLD_OVRR_EN0_TYPEr_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, or_value); 3980 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg); 3981 SC_X4_FLD_OVRR_EN1_TYPEr_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg, or_value); 3982 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 3983 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg)); 3984 break; 3985 case OVERRIDE_NUM_LANES: 3986 SC_X4_SC_X4_OVRRr_CLR(SC_X4_CONTROL_LANE_OVERRIDEr_reg); 3987 SC_X4_SC_X4_OVRRr_NUM_LANES_OVERRIDE_VALUEf_SET(SC_X4_CONTROL_LANE_OVERRIDEr_reg, or_value); 3988 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_SC_X4_OVRRr(pc, SC_X4_CONTROL_LANE_OVERRIDEr_reg)); 3989 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 3990 SC_X4_FLD_OVRR_EN0_TYPEr_NUM_LANES_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 1); 3991 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 3992 break; 3993 case OVERRIDE_NUM_LANES_DIS: 3994 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 3995 SC_X4_FLD_OVRR_EN0_TYPEr_NUM_LANES_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 0); 3996 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 3997 break; 3998 case OVERRIDE_OS_MODE: 3999 TX_X4_MISCr_CLR(TX_X4_CONTROL0_MISCr_reg); 4000 TX_X4_MISCr_OS_MODEf_SET(TX_X4_CONTROL0_MISCr_reg, or_value); 4001 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_MISCr(pc, TX_X4_CONTROL0_MISCr_reg)); 4002 /*Set the override enable*/ 4003 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 4004 SC_X4_FLD_OVRR_EN0_TYPEr_OS_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 1); 4005 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 4006 break; 4007 case OVERRIDE_OS_MODE_DIS: 4008 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 4009 SC_X4_FLD_OVRR_EN0_TYPEr_OS_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 0); 4010 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 4011 break; 4012 case OVERRIDE_T_FIFO_MODE: 4013 SC_X1_SPD_OVRR0_0r_CLR(SC_X1_SPEED_OVERRIDE0r_reg); 4014 SC_X1_SPD_OVRR0_0r_T_FIFO_MODEf_SET(SC_X1_SPEED_OVERRIDE0r_reg, or_value); 4015 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR0_0r(pc, SC_X1_SPEED_OVERRIDE0r_reg)); 4016 /*Set the override enable*/ 4017 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 4018 SC_X4_FLD_OVRR_EN0_TYPEr_T_FIFO_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 1); 4019 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 4020 break; 4021 case OVERRIDE_T_FIFO_MODE_DIS: 4022 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 4023 SC_X4_FLD_OVRR_EN0_TYPEr_T_FIFO_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 0); 4024 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 4025 break; 4026 case OVERRIDE_T_ENC_MODE: 4027 TX_X4_ENC0r_CLR(TX_X4_CONTROL0_ENCODE_0r_reg); 4028 TX_X4_ENC0r_T_ENC_MODEf_SET(TX_X4_CONTROL0_ENCODE_0r_reg, or_value); 4029 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_ENC0r(pc, TX_X4_CONTROL0_ENCODE_0r_reg)); 4030 /*Set the override enable*/ 4031 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 4032 SC_X4_FLD_OVRR_EN0_TYPEr_T_ENC_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 1); 4033 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 4034 break; 4035 case OVERRIDE_T_ENC_MODE_DIS: 4036 /*Set the override enable*/ 4037 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 4038 SC_X4_FLD_OVRR_EN0_TYPEr_T_ENC_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 0); 4039 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 4040 break; 4041 case OVERRIDE_T_HG2_ENABLE: 4042 TX_X4_ENC0r_CLR(TX_X4_CONTROL0_ENCODE_0r_reg); 4043 TX_X4_ENC0r_HG2_ENABLEf_SET(TX_X4_CONTROL0_ENCODE_0r_reg, or_value); 4044 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_ENC0r(pc, TX_X4_CONTROL0_ENCODE_0r_reg)); 4045 /*Set the override enable*/ 4046 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 4047 SC_X4_FLD_OVRR_EN0_TYPEr_T_HG2_ENABLE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 1); 4048 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 4049 break; 4050 case OVERRIDE_T_HG2_ENABLE_DIS: 4051 /*Set the override enable*/ 4052 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 4053 SC_X4_FLD_OVRR_EN0_TYPEr_T_HG2_ENABLE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 0); 4054 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 4055 break; 4056 case OVERRIDE_T_PMA_BTMX_MODE_OEN: 4057 TX_X4_MISCr_CLR(TX_X4_CONTROL0_MISCr_reg); 4058 TX_X4_MISCr_T_PMA_BTMX_MODEf_SET(TX_X4_CONTROL0_MISCr_reg, or_value); 4059 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_MISCr(pc, TX_X4_CONTROL0_MISCr_reg)); 4060 /*Set the override enable*/ 4061 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 4062 SC_X4_FLD_OVRR_EN0_TYPEr_T_PMA_BTMX_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 1); 4063 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 4064 break; 4065 case OVERRIDE_T_PMA_BTMX_MODE_OEN_DIS: 4066 /*Set the override enable*/ 4067 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 4068 SC_X4_FLD_OVRR_EN0_TYPEr_T_PMA_BTMX_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 0); 4069 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 4070 /* No missing break. Intentional fall through case */ 4071 /* coverity[unterminated_case] */ 4072 break; 4073 case OVERRIDE_SCR_MODE: 4074 TX_X4_MISCr_CLR(TX_X4_CONTROL0_MISCr_reg); 4075 TX_X4_MISCr_SCR_MODEf_SET(TX_X4_CONTROL0_MISCr_reg, or_value); 4076 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_MISCr(pc, TX_X4_CONTROL0_MISCr_reg)); 4077 /*Set the override enable*/ 4078 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 4079 SC_X4_FLD_OVRR_EN0_TYPEr_SCR_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 1); 4080 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 4081 break; 4082 case OVERRIDE_SCR_MODE_DIS: 4083 /*Set the override enable*/ 4084 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 4085 SC_X4_FLD_OVRR_EN0_TYPEr_SCR_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 0); 4086 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 4087 break; 4088 case OVERRIDE_DESCR_MODE_OEN: 4089 RX_X4_PCS_CTL0r_CLR(RX_X4_CONTROL0_PCS_CONTROL_0r_reg); 4090 RX_X4_PCS_CTL0r_DESCR_MODEf_SET(RX_X4_CONTROL0_PCS_CONTROL_0r_reg, or_value); 4091 PHYMOD_IF_ERR_RETURN(MODIFY_RX_X4_PCS_CTL0r(pc, RX_X4_CONTROL0_PCS_CONTROL_0r_reg)); 4092 /*Set the override enable*/ 4093 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 4094 SC_X4_FLD_OVRR_EN0_TYPEr_DESCR_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 1); 4095 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 4096 break; 4097 case OVERRIDE_DESCR_MODE_OEN_DIS: 4098 /*Set the override disable*/ 4099 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 4100 SC_X4_FLD_OVRR_EN0_TYPEr_DESCR_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 0); 4101 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 4102 break; 4103 case OVERRIDE_DEC_TL_MODE: 4104 RX_X4_PCS_CTL0r_CLR(RX_X4_CONTROL0_PCS_CONTROL_0r_reg); 4105 RX_X4_PCS_CTL0r_DEC_TL_MODEf_SET(RX_X4_CONTROL0_PCS_CONTROL_0r_reg, or_value); 4106 PHYMOD_IF_ERR_RETURN(MODIFY_RX_X4_PCS_CTL0r(pc, RX_X4_CONTROL0_PCS_CONTROL_0r_reg)); 4107 /*Set the override enable*/ 4108 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 4109 SC_X4_FLD_OVRR_EN0_TYPEr_DEC_TL_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 1); 4110 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 4111 break; 4112 case OVERRIDE_DEC_TL_MODE_DIS: 4113 /*Set the override enable*/ 4114 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 4115 SC_X4_FLD_OVRR_EN0_TYPEr_DEC_TL_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 0); 4116 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 4117 break; 4118 case OVERRIDE_DESKEW_MODE: 4119 RX_X4_PCS_CTL0r_CLR(RX_X4_CONTROL0_PCS_CONTROL_0r_reg); 4120 RX_X4_PCS_CTL0r_DESKEW_MODEf_SET(RX_X4_CONTROL0_PCS_CONTROL_0r_reg, or_value); 4121 PHYMOD_IF_ERR_RETURN(MODIFY_RX_X4_PCS_CTL0r(pc, RX_X4_CONTROL0_PCS_CONTROL_0r_reg)); 4122 /*Set the override enable*/ 4123 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 4124 SC_X4_FLD_OVRR_EN0_TYPEr_DESKEW_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 1); 4125 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 4126 break; 4127 case OVERRIDE_DESKEW_MODE_DIS: 4128 /*Set the override disable*/ 4129 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 4130 SC_X4_FLD_OVRR_EN0_TYPEr_DESKEW_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 0); 4131 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 4132 break; 4133 case OVERRIDE_DEC_FSM_MODE: 4134 RX_X4_PCS_CTL0r_CLR(RX_X4_CONTROL0_PCS_CONTROL_0r_reg); 4135 RX_X4_PCS_CTL0r_DEC_FSM_MODEf_SET(RX_X4_CONTROL0_PCS_CONTROL_0r_reg, or_value); 4136 PHYMOD_IF_ERR_RETURN(MODIFY_RX_X4_PCS_CTL0r(pc, RX_X4_CONTROL0_PCS_CONTROL_0r_reg)); 4137 /*Set the override enable*/ 4138 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 4139 SC_X4_FLD_OVRR_EN0_TYPEr_DEC_FSM_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 1); 4140 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 4141 break; 4142 case OVERRIDE_DEC_FSM_MODE_DIS: 4143 /*Set the override enable*/ 4144 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 4145 SC_X4_FLD_OVRR_EN0_TYPEr_DEC_FSM_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 0); 4146 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 4147 break; 4148 default: 4149 break; 4150 } 4151 4152 return PHYMOD_E_NONE; 4153 } /* OVERRIDE_SET */ 4154 4155 /*! 4156 @brief TBD 4157 @param pc handle to current TSCF context (#PHYMOD_ST) 4158 @param per_lane_control 4159 @param per_field_override_en 4160 @returns PHYMOD_E_NONE if no errors. PHYMOD_EERROR else. 4161 @details 4162 TBD 4163 */ 4164 int tefmod16_set_override_1(PHYMOD_ST* pc, int per_lane_control, uint32_t per_field_override_en) /* OVERRIDE_SET */ 4165 { 4166 int or_value; 4167 override_type_t or_en; 4168 MAIN0_SETUPr_t MAIN0_SETUPr_reg; 4169 RX_X4_BLKSYNC_CFGr_t RX_X4_CONTROL0_BLKSYNC_CONFIGr_reg; 4170 TX_X4_MISCr_t TX_X4_CONTROL0_MISCr_reg; 4171 TX_X4_CRED0r_t TX_X4_CREDIT0_CREDIT0r_reg; 4172 TX_X4_CRED1r_t TX_X4_CREDIT0_CREDIT1r_reg; 4173 TX_X4_LOOPCNTr_t TX_X4_CREDIT0_LOOPCNTr_reg; 4174 TX_X4_MAC_CREDGENCNTr_t TX_X4_CREDIT0_MAC_CREDITGENCNTr_reg; 4175 SC_X4_FLD_OVRR_EN0_TYPEr_t SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg; 4176 SC_X4_FLD_OVRR_EN1_TYPEr_t SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg; 4177 4178 TEFMOD16_DBG_IN_FUNC_INFO(pc); 4179 or_en = (override_type_t) (per_field_override_en >> 16); 4180 4181 or_value = per_field_override_en & 0x0000ffff; 4182 4183 4184 switch(or_en) { 4185 case OVERRIDE_R_HG2_ENABLE: 4186 TX_X4_MISCr_CLR(TX_X4_CONTROL0_MISCr_reg); 4187 TX_X4_MISCr_SET(TX_X4_CONTROL0_MISCr_reg, or_value); 4188 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_MISCr(pc, TX_X4_CONTROL0_MISCr_reg)); 4189 4190 /*Set the override enable*/ 4191 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg); 4192 SC_X4_FLD_OVRR_EN1_TYPEr_R_HG2_ENABLE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg, 1); 4193 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg)); 4194 break; 4195 case OVERRIDE_R_HG2_ENABLE_DIS: 4196 /*Set the override disable*/ 4197 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg); 4198 SC_X4_FLD_OVRR_EN1_TYPEr_R_HG2_ENABLE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg, 0); 4199 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg)); 4200 break; 4201 case OVERRIDE_BS_SM_SYNC_MODE_OEN: 4202 RX_X4_BLKSYNC_CFGr_CLR(RX_X4_CONTROL0_BLKSYNC_CONFIGr_reg); 4203 RX_X4_BLKSYNC_CFGr_BS_SM_SYNC_MODEf_SET(RX_X4_CONTROL0_BLKSYNC_CONFIGr_reg, or_value); 4204 PHYMOD_IF_ERR_RETURN(MODIFY_RX_X4_BLKSYNC_CFGr(pc, RX_X4_CONTROL0_BLKSYNC_CONFIGr_reg)); 4205 4206 /*Set the override enable*/ 4207 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg); 4208 SC_X4_FLD_OVRR_EN1_TYPEr_BS_SM_SYNC_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg, 1); 4209 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg)); 4210 break; 4211 case OVERRIDE_BS_SM_SYNC_MODE_OEN_DIS: 4212 /*Set the override disable*/ 4213 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg); 4214 SC_X4_FLD_OVRR_EN1_TYPEr_BS_SM_SYNC_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg, 0); 4215 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg)); 4216 break; 4217 case OVERRIDE_BS_SYNC_EN_OEN: 4218 RX_X4_BLKSYNC_CFGr_CLR(RX_X4_CONTROL0_BLKSYNC_CONFIGr_reg); 4219 RX_X4_BLKSYNC_CFGr_BS_SYNC_ENf_SET(RX_X4_CONTROL0_BLKSYNC_CONFIGr_reg, or_value); 4220 PHYMOD_IF_ERR_RETURN(MODIFY_RX_X4_BLKSYNC_CFGr(pc, RX_X4_CONTROL0_BLKSYNC_CONFIGr_reg)); 4221 4222 /*Set the override enable*/ 4223 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg); 4224 SC_X4_FLD_OVRR_EN1_TYPEr_BS_SYNC_EN_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg, 1); 4225 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg)); 4226 break; 4227 case OVERRIDE_BS_SYNC_EN_OEN_DIS: 4228 /*Set the override disable*/ 4229 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg); 4230 SC_X4_FLD_OVRR_EN1_TYPEr_BS_SYNC_EN_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg, 0); 4231 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg)); 4232 break; 4233 case OVERRIDE_BS_DIST_MODE_OEN: 4234 RX_X4_BLKSYNC_CFGr_CLR(RX_X4_CONTROL0_BLKSYNC_CONFIGr_reg); 4235 RX_X4_BLKSYNC_CFGr_BS_DIST_MODEf_SET(RX_X4_CONTROL0_BLKSYNC_CONFIGr_reg, or_value); 4236 PHYMOD_IF_ERR_RETURN(MODIFY_RX_X4_BLKSYNC_CFGr(pc, RX_X4_CONTROL0_BLKSYNC_CONFIGr_reg)); 4237 4238 /*Set the override enable*/ 4239 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg); 4240 SC_X4_FLD_OVRR_EN1_TYPEr_BS_DIST_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg, 1); 4241 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg)); 4242 break; 4243 case OVERRIDE_BS_DIST_MODE_OEN_DIS: 4244 /*Set the override enable*/ 4245 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg); 4246 SC_X4_FLD_OVRR_EN1_TYPEr_BS_DIST_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg, 0); 4247 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg)); 4248 break; 4249 case OVERRIDE_BS_BTMX_MODE_OEN: 4250 RX_X4_BLKSYNC_CFGr_CLR(RX_X4_CONTROL0_BLKSYNC_CONFIGr_reg); 4251 RX_X4_BLKSYNC_CFGr_BS_BTMX_MODEf_SET(RX_X4_CONTROL0_BLKSYNC_CONFIGr_reg, or_value); 4252 PHYMOD_IF_ERR_RETURN(MODIFY_RX_X4_BLKSYNC_CFGr(pc, RX_X4_CONTROL0_BLKSYNC_CONFIGr_reg)); 4253 4254 /*Set the override enable*/ 4255 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg); 4256 SC_X4_FLD_OVRR_EN1_TYPEr_BS_BTMX_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg, 1); 4257 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg)); 4258 break; 4259 case OVERRIDE_BS_BTMX_MODE_OEN_DIS: 4260 /*Set the override disable*/ 4261 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg); 4262 SC_X4_FLD_OVRR_EN1_TYPEr_BS_BTMX_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg, 0); 4263 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg)); 4264 break; 4265 case OVERRIDE_CL72_EN: 4266 MAIN0_SETUPr_CLR(MAIN0_SETUPr_reg); 4267 MAIN0_SETUPr_CL72_ENf_SET(MAIN0_SETUPr_reg, or_value); 4268 PHYMOD_IF_ERR_RETURN(MODIFY_MAIN0_SETUPr(pc, MAIN0_SETUPr_reg)); 4269 4270 /*Set the override enable*/ 4271 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 4272 SC_X4_FLD_OVRR_EN0_TYPEr_CL72_EN_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 1); 4273 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 4274 break; 4275 case OVERRIDE_CL72_EN_DIS: 4276 /*Set the override disable*/ 4277 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 4278 SC_X4_FLD_OVRR_EN0_TYPEr_CL72_EN_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 0); 4279 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 4280 break; 4281 case OVERRIDE_CLOCKCNT0: 4282 TX_X4_CRED0r_CLR(TX_X4_CREDIT0_CREDIT0r_reg); 4283 TX_X4_CRED0r_CLOCKCNT0f_SET(TX_X4_CREDIT0_CREDIT0r_reg, or_value); 4284 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_CRED0r(pc, TX_X4_CREDIT0_CREDIT0r_reg)); 4285 4286 /*Set the override enable*/ 4287 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg); 4288 SC_X4_FLD_OVRR_EN1_TYPEr_CLOCKCNT0_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg, 1); 4289 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg)); 4290 break; 4291 case OVERRIDE_CLOCKCNT0_DIS: 4292 /*Set the override disable*/ 4293 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg); 4294 SC_X4_FLD_OVRR_EN1_TYPEr_CLOCKCNT0_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg, 0); 4295 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg)); 4296 4297 break; 4298 case OVERRIDE_CLOCKCNT1: 4299 TX_X4_CRED1r_CLR(TX_X4_CREDIT0_CREDIT1r_reg); 4300 TX_X4_CRED1r_CLOCKCNT1f_SET(TX_X4_CREDIT0_CREDIT1r_reg, or_value); 4301 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_CRED1r(pc, TX_X4_CREDIT0_CREDIT1r_reg)); 4302 4303 /*Set the override enable*/ 4304 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg); 4305 SC_X4_FLD_OVRR_EN1_TYPEr_CLOCKCNT1_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg, 1); 4306 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg)); 4307 break; 4308 case OVERRIDE_CLOCKCNT1_DIS: 4309 /*Set the override disable*/ 4310 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg); 4311 SC_X4_FLD_OVRR_EN1_TYPEr_CLOCKCNT1_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg, 0); 4312 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg)); 4313 4314 break; 4315 case OVERRIDE_LOOPCNT0: 4316 TX_X4_LOOPCNTr_CLR(TX_X4_CREDIT0_LOOPCNTr_reg); 4317 TX_X4_LOOPCNTr_LOOPCNT0f_SET(TX_X4_CREDIT0_LOOPCNTr_reg, or_value); 4318 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_LOOPCNTr(pc, TX_X4_CREDIT0_LOOPCNTr_reg)); 4319 4320 /*Set the override enable*/ 4321 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg); 4322 SC_X4_FLD_OVRR_EN1_TYPEr_LOOPCNT0_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg, 1); 4323 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg)); 4324 break; 4325 case OVERRIDE_LOOPCNT0_DIS: 4326 /*Set the override disable*/ 4327 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg); 4328 SC_X4_FLD_OVRR_EN1_TYPEr_LOOPCNT0_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg, 0); 4329 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg)); 4330 4331 break; 4332 case OVERRIDE_LOOPCNT1: 4333 TX_X4_LOOPCNTr_CLR(TX_X4_CREDIT0_LOOPCNTr_reg); 4334 TX_X4_LOOPCNTr_LOOPCNT1f_SET(TX_X4_CREDIT0_LOOPCNTr_reg, or_value); 4335 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_LOOPCNTr(pc, TX_X4_CREDIT0_LOOPCNTr_reg)); 4336 4337 /*Set the override enable*/ 4338 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg); 4339 SC_X4_FLD_OVRR_EN1_TYPEr_LOOPCNT1_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg, 1); 4340 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg)); 4341 break; 4342 case OVERRIDE_LOOPCNT1_DIS: 4343 /*Set the override enable*/ 4344 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg); 4345 SC_X4_FLD_OVRR_EN1_TYPEr_LOOPCNT1_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg, 0); 4346 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg)); 4347 4348 break; 4349 case OVERRIDE_MAC_CREDITGENCNT: 4350 TX_X4_MAC_CREDGENCNTr_CLR(TX_X4_CREDIT0_MAC_CREDITGENCNTr_reg); 4351 TX_X4_MAC_CREDGENCNTr_MAC_CREDITGENCNTf_SET(TX_X4_CREDIT0_MAC_CREDITGENCNTr_reg, or_value); 4352 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_MAC_CREDGENCNTr(pc, TX_X4_CREDIT0_MAC_CREDITGENCNTr_reg)); 4353 4354 /*Set the override enable*/ 4355 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg); 4356 SC_X4_FLD_OVRR_EN1_TYPEr_MAC_CREDITGENCNT_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg, 1); 4357 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg)); 4358 break; 4359 case OVERRIDE_MAC_CREDITGENCNT_DIS: 4360 /*Set the override disable*/ 4361 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg); 4362 SC_X4_FLD_OVRR_EN1_TYPEr_MAC_CREDITGENCNT_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg, 0); 4363 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg)); 4364 break; 4365 default: 4366 break; 4367 } 4368 return PHYMOD_E_NONE; 4369 } /* OVERRIDE_SET */ 4370 4371 /*! 4372 @brief Enable / Disable credits for any particular lane 4373 @param pc handle to current TSCF context (#PHYMOD_ST) 4374 @param per_lane_control Control to enable or disable credits 4375 @returns The value PHYMOD_E_NONE upon successful completion. 4376 @details 4377 This function is used to enable or disable the credit generation. 4378 4379 \li set to 0x1 to enable credit 4380 \li Set to 0x0 disable credit for selected lane. 4381 4382 This function reads/modifies the following registers: 4383 4384 \li enable credits: clockcnt0 (0xC100[14]) 4385 */ 4386 int tefmod16_credit_control(PHYMOD_ST* pc, int per_lane_control) /* CREDIT_CONTROL */ 4387 { 4388 int cntl; 4389 TX_X4_CRED0r_t TX_X4_CREDIT0_CREDIT0r_reg; 4390 cntl = per_lane_control; 4391 4392 TEFMOD16_DBG_IN_FUNC_INFO(pc); 4393 TX_X4_CRED0r_CLR(TX_X4_CREDIT0_CREDIT0r_reg); 4394 if (cntl) { /* enable credits */ 4395 TX_X4_CRED0r_CREDITENABLEf_SET(TX_X4_CREDIT0_CREDIT0r_reg, 1); 4396 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_CRED0r(pc, TX_X4_CREDIT0_CREDIT0r_reg)); 4397 } else { /* disable credits */ 4398 TX_X4_CRED0r_CREDITENABLEf_SET(TX_X4_CREDIT0_CREDIT0r_reg, 0); 4399 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_CRED0r(pc, TX_X4_CREDIT0_CREDIT0r_reg)); 4400 } 4401 return PHYMOD_E_NONE; 4402 } 4403 4404 /*! 4405 @brief tx lane reset and enable of any particular lane 4406 @param pc handle to current TSCF context (#PHYMOD_ST) 4407 @param en controls enabling properties of lane control 4408 @param dis controls what property to control enum #tefmod16_tx_disable_enum_t 4409 @returns The value PHYMOD_E_NONE upon successful completion. 4410 @details 4411 This function is used to reset tx lane and enable/disable tx lane of any 4412 transmit lane. Set bit 0 of per_lane_control to enable the TX_LANE 4413 (1) or disable the TX lane (0). 4414 When diable TX lane, two types of operations are inovked independently. 4415 If per_lane_control bit [7:4] = 1, only traffic is disabled. 4416 (TEFMOD16_TX_LANE_TRAFFIC =0x10) 4417 If bit [7:4] = 2, only reset function is invoked. 4418 (TEFMOD16_TX_LANE_RESET = 0x20) 4419 4420 This function reads/modifies the following registers: 4421 4422 \li rstb_tx_lane : 0xc113[1] 4423 \li enable_tx_lane: 0xc113[0] 4424 */ 4425 4426 4427 /*! 4428 @brief tx lane reset and enable of any particular lane 4429 @param pc handle to current TSCF context (#PHYMOD_ST) 4430 @param en controls enabling properties of lane control 4431 @param dis controls what property to control enum #tefmod16_tx_disable_enum_t 4432 @returns The value PHYMOD_E_NONE upon successful completion. 4433 @details 4434 This function is used to reset tx lane and enable/disable tx lane of any 4435 transmit lane. Set bit 0 of per_lane_control to enable the TX_LANE 4436 (1) or disable the TX lane (0). 4437 When diable TX lane, two types of operations are inovked independently. 4438 If per_lane_control bit [7:4] = 1, only traffic is disabled. 4439 (TEFMOD16_TX_LANE_TRAFFIC =0x10) 4440 If bit [7:4] = 2, only reset function is invoked. 4441 (TEFMOD16_TX_LANE_RESET = 0x20) 4442 4443 This function reads/modifies the following registers: 4444 4445 \li rstb_tx_lane : 0xc113[1] 4446 \li enable_tx_lane: 0xc113[0] 4447 */ 4448 /* TBD: Use this tier1 for DV, instead of tefmod16_tx_lane_control */ 4449 int tefmod16_tx_lane_control_set(PHYMOD_ST* pc, tefmod16_tx_disable_enum_t tx_dis_type) /* TX_LANE_CONTROL */ 4450 { 4451 TX_X4_MISCr_t TX_X4_CONTROL0_MISCr_reg; 4452 4453 TEFMOD16_DBG_IN_FUNC_INFO(pc); 4454 TX_X4_MISCr_CLR(TX_X4_CONTROL0_MISCr_reg); 4455 4456 switch(tx_dis_type) { 4457 case TEFMOD16_TX_LANE_RESET: 4458 TX_X4_MISCr_RSTB_TX_LANEf_SET(TX_X4_CONTROL0_MISCr_reg, 0); 4459 PHYMOD_IF_ERR_RETURN (MODIFY_TX_X4_MISCr(pc, TX_X4_CONTROL0_MISCr_reg)); 4460 TX_X4_MISCr_CLR(TX_X4_CONTROL0_MISCr_reg); 4461 TX_X4_MISCr_RSTB_TX_LANEf_SET(TX_X4_CONTROL0_MISCr_reg, 1); 4462 PHYMOD_IF_ERR_RETURN (MODIFY_TX_X4_MISCr(pc, TX_X4_CONTROL0_MISCr_reg)); 4463 break; 4464 case TEFMOD16_TX_LANE_TRAFFIC_ENABLE: 4465 TX_X4_MISCr_ENABLE_TX_LANEf_SET(TX_X4_CONTROL0_MISCr_reg, 1); 4466 PHYMOD_IF_ERR_RETURN (MODIFY_TX_X4_MISCr(pc, TX_X4_CONTROL0_MISCr_reg)); 4467 break; 4468 case TEFMOD16_TX_LANE_TRAFFIC_DISABLE: 4469 TX_X4_MISCr_ENABLE_TX_LANEf_SET(TX_X4_CONTROL0_MISCr_reg, 0); 4470 PHYMOD_IF_ERR_RETURN (MODIFY_TX_X4_MISCr(pc, TX_X4_CONTROL0_MISCr_reg)); 4471 break; 4472 case TEFMOD16_TX_LANE_RESET_TRAFFIC_ENABLE: 4473 TX_X4_MISCr_RSTB_TX_LANEf_SET(TX_X4_CONTROL0_MISCr_reg, 1); 4474 PHYMOD_IF_ERR_RETURN (MODIFY_TX_X4_MISCr(pc, TX_X4_CONTROL0_MISCr_reg)); 4475 TX_X4_MISCr_CLR(TX_X4_CONTROL0_MISCr_reg); 4476 TX_X4_MISCr_ENABLE_TX_LANEf_SET(TX_X4_CONTROL0_MISCr_reg, 1); 4477 PHYMOD_IF_ERR_RETURN (MODIFY_TX_X4_MISCr(pc, TX_X4_CONTROL0_MISCr_reg)); 4478 break; 4479 case TEFMOD16_TX_LANE_RESET_TRAFFIC_DISABLE: 4480 TX_X4_MISCr_RSTB_TX_LANEf_SET(TX_X4_CONTROL0_MISCr_reg, 0); 4481 PHYMOD_IF_ERR_RETURN (MODIFY_TX_X4_MISCr(pc, TX_X4_CONTROL0_MISCr_reg)); 4482 TX_X4_MISCr_CLR(TX_X4_CONTROL0_MISCr_reg); 4483 TX_X4_MISCr_ENABLE_TX_LANEf_SET(TX_X4_CONTROL0_MISCr_reg, 0); 4484 PHYMOD_IF_ERR_RETURN (MODIFY_TX_X4_MISCr(pc, TX_X4_CONTROL0_MISCr_reg)); 4485 break; 4486 default: 4487 break; 4488 } 4489 4490 return PHYMOD_E_NONE; 4491 } 4492 4493 4494 /*! 4495 @brief tx lane reset and enable of any particular lane 4496 @param pc handle to current TSCF context (#PHYMOD_ST) 4497 @param reset gets the configured tx rstb 4498 @param enable gets the configured tx enable 4499 @returns The value PHYMOD_E_NONE upon successful completion. 4500 @details 4501 This function reads the following registers: 4502 4503 \li rstb_tx_lane : 0xc113[1] 4504 \li enable_tx_lane: 0xc113[0] 4505 */ 4506 int tefmod16_tx_lane_control_get(PHYMOD_ST* pc, int *reset, int *enable) /* TX_LANE_CONTROL */ 4507 { 4508 TX_X4_MISCr_t TX_X4_CONTROL0_MISCr_reg; 4509 4510 TEFMOD16_DBG_IN_FUNC_INFO(pc); 4511 TX_X4_MISCr_CLR(TX_X4_CONTROL0_MISCr_reg); 4512 4513 PHYMOD_IF_ERR_RETURN (READ_TX_X4_MISCr(pc, &TX_X4_CONTROL0_MISCr_reg)); 4514 4515 *reset = TX_X4_MISCr_RSTB_TX_LANEf_GET(TX_X4_CONTROL0_MISCr_reg); 4516 *enable = TX_X4_MISCr_ENABLE_TX_LANEf_GET(TX_X4_CONTROL0_MISCr_reg); 4517 4518 return PHYMOD_E_NONE; 4519 } 4520 4521 #ifdef _DV_TB_ 4522 /*! 4523 @brief rx lane reset and enable of any particular lane 4524 @param pc handle to current TSCF context (#PHYMOD_ST) 4525 @param accData TBD 4526 @param per_lane_control TBD 4527 @returns The value PHYMOD_E_NONE upon successful completion. 4528 @details 4529 This function enables/disables rx lane (RSTB_LANE) or read back control bit for 4530 that based on per_lane_control being 1 or 0. If per_lane_control is 0xa, only 4531 read back RSTB_LANE. 4532 \li select encodeMode 4533 This function reads/modifies the following registers: 4534 \li rstb_rx_lane : 0xc137[0] 4535 */ 4536 4537 int tefmod16_rx_lane_control(PHYMOD_ST* pc, int accData, int per_lane_control) /* RX_LANE_CONTROL */ 4538 { 4539 int cntl; 4540 RX_X4_PMA_CTL0r_t RX_X4_CONTROL0_PMA_CONTROL_0r_reg; 4541 /* coverity[param_set_but_not_used]*/ 4542 accData = accData; 4543 4544 TEFMOD16_DBG_IN_FUNC_INFO(pc); 4545 cntl = per_lane_control; 4546 4547 PHYMOD_DEBUG_ERROR(("%-22s u=%0d p=%0d sel=%x ln=%0d dxgxs=%0d cntl=%x\n", __func__, 4548 pc->unit, pc->port, pc->lane_select, pc->this_lane, pc->dxgxs, cntl)); 4549 4550 RX_X4_PMA_CTL0r_CLR(RX_X4_CONTROL0_PMA_CONTROL_0r_reg); 4551 if (cntl==0xa) { 4552 /* set encoder */ 4553 PHYMOD_IF_ERR_RETURN(READ_RX_X4_PMA_CTL0r(pc, &RX_X4_CONTROL0_PMA_CONTROL_0r_reg)); 4554 if(RX_X4_PMA_CTL0r_RSTB_LANEf_GET(RX_X4_CONTROL0_PMA_CONTROL_0r_reg)) 4555 accData =1; 4556 else 4557 accData =0; 4558 } else if (cntl) { 4559 /* set encoder */ 4560 RX_X4_PMA_CTL0r_RSTB_LANEf_SET(RX_X4_CONTROL0_PMA_CONTROL_0r_reg, 1); 4561 PHYMOD_IF_ERR_RETURN(MODIFY_RX_X4_PMA_CTL0r(pc, RX_X4_CONTROL0_PMA_CONTROL_0r_reg)); 4562 } else { 4563 /* bit set to 0 for disabling RXP */ 4564 RX_X4_PMA_CTL0r_RSTB_LANEf_SET(RX_X4_CONTROL0_PMA_CONTROL_0r_reg, 0); 4565 PHYMOD_IF_ERR_RETURN(MODIFY_RX_X4_PMA_CTL0r(pc, RX_X4_CONTROL0_PMA_CONTROL_0r_reg)); 4566 } 4567 return PHYMOD_E_NONE; 4568 } 4569 #endif /* _DV_TB_ */ 4570 4571 #ifdef _DV_TB_ 4572 /*! 4573 @brief set broadcast enable and broadcast address 4574 4575 @param pc handle to current TSCF context (#PHYMOD_ST) 4576 4577 @returns The value PHYMOD_E_NONE upon successful completion. 4578 */ 4579 4580 int tefmod16_bypass_sc(PHYMOD_ST* pc) /* BYPASS_SC */ 4581 { 4582 uint16_t bypass_en, fild_override_enable0, fild_override_enable1; 4583 SC_X4_BYPASSr_t SC_X4_CONTROL_BYPASSr_reg; 4584 SC_X4_FLD_OVRR_EN0_TYPEr_t SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg; 4585 SC_X4_FLD_OVRR_EN1_TYPEr_t SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg; 4586 4587 TEFMOD16_DBG_IN_FUNC_INFO(pc); 4588 bypass_en = 0xf; 4589 fild_override_enable0 = 0xffff; 4590 fild_override_enable1 = 0xfff0; 4591 4592 SC_X4_BYPASSr_CLR(SC_X4_CONTROL_BYPASSr_reg); 4593 SC_X4_BYPASSr_SC_BYPASSf_SET(SC_X4_CONTROL_BYPASSr_reg, bypass_en); 4594 4595 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_BYPASSr(pc, SC_X4_CONTROL_BYPASSr_reg)); 4596 4597 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 4598 SC_X4_FLD_OVRR_EN0_TYPEr_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, fild_override_enable0); 4599 PHYMOD_IF_ERR_RETURN 4600 (MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 4601 4602 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg); 4603 SC_X4_FLD_OVRR_EN1_TYPEr_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg, fild_override_enable1); 4604 PHYMOD_IF_ERR_RETURN 4605 (MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg)); 4606 return PHYMOD_E_NONE; 4607 } 4608 #endif /* _DV_TB_ */ 4609 4610 #ifdef _DV_TB_ 4611 /*! 4612 @brief Control per lane clause 72 auto tuning function (training patterns) 4613 @param pc handle to current TSCF context (#PHYMOD_ST) 4614 @returns The value PHYMOD_E_NONE upon successful completion 4615 @details 4616 4617 This function enables/disables clause-72 auto-tuning per lane. It is used 4618 in 40G_KR4, 40G_CR4, 10G_KR modes etc. 4619 Lane is selected via #PHYMOD_ST::lane_select. 4620 This Function is controlled by #PHYMOD_ST::per_lane_control as follows. 4621 4622 \li 0Xxxxxxxx3 (b11): Enable CL72 hardware block 4623 \li 0Xxxxxxxx2 (b01): Disable CL72 hardware block 4624 \li 0Xxxxxxxx0 (b00): no changed. 4625 \li 0Xxxxxxx3- (b011----): Forced enable CL72 under AN. 4626 \li 0Xxxxxxx7- (b111----): Forced disable CL72 under AN. 4627 \li 0Xxxxxxx1- (b001----): Default CL72 under AN. 4628 \li 0Xxxxxxx0- (b000----): no changed 4629 \li 0Xxxxxx100 : read back CL72 HW en bit and put in accData. 4630 4631 This function modifies the following registers: 4632 4633 \li DEV1_IEEE9_PMD_10GBASE_KR_PMD_CONTROL_REGISTER_150 (0x0800_0096) 4634 \li CL72_MISC1_CONTROL (0xc253) 4635 4636 */ 4637 int tefmod16_clause72_control(PHYMOD_ST* pc, int cl72en) /* CLAUSE_72_CONTROL */ 4638 { 4639 int cntl; 4640 #ifdef _DV_TB_ 4641 int tmp_port_type; 4642 #endif 4643 int cl72_restart, cl72_enable; 4644 CL93N72_IT_BASE_R_PMD_CTLr_t CL93N72_IEEE_TX_CL93N72IT_BASE_R_PMD_CONTROLr_reg; 4645 SC_X4_CTLr_t SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg; 4646 CL93N72_UR_CTL0r_t CL93N72_USER_RX_CL93N72UR_CONTROL0r_reg; 4647 4648 TEFMOD_DBG_IN_FUNC_INFO(pc); 4649 cntl = cl72en; 4650 cl72_restart = cntl & 0x1; 4651 cl72_enable = (cntl & 0x2) ? 1 : 0; 4652 4653 #ifdef _DV_TB_ 4654 if(pc->verbosity) 4655 PHYMOD_DEBUG_ERROR(("%-22s: port %0d cl72_restart %0d cl72_en %0d\n", __func__, pc->this_lane, cl72_restart, cl72_enable)); 4656 #endif 4657 CL93N72_IT_BASE_R_PMD_CTLr_CLR(CL93N72_IEEE_TX_CL93N72IT_BASE_R_PMD_CONTROLr_reg); 4658 4659 CL93N72_IT_BASE_R_PMD_CTLr_CL93N72_IEEE_RESTART_TRAININGf_SET(CL93N72_IEEE_TX_CL93N72IT_BASE_R_PMD_CONTROLr_reg, cl72_restart); 4660 CL93N72_IT_BASE_R_PMD_CTLr_CL93N72_IEEE_TRAINING_ENABLEf_SET(CL93N72_IEEE_TX_CL93N72IT_BASE_R_PMD_CONTROLr_reg, cl72_enable); 4661 4662 PHYMOD_IF_ERR_RETURN(MODIFY_CL93N72_IT_BASE_R_PMD_CTLr(pc, CL93N72_IEEE_TX_CL93N72IT_BASE_R_PMD_CONTROLr_reg)); 4663 4664 4665 CL93N72_UR_CTL0r_CLR(CL93N72_USER_RX_CL93N72UR_CONTROL0r_reg); 4666 PHYMOD_IF_ERR_RETURN(READ_CL93N72_UR_CTL0r(pc, &CL93N72_USER_RX_CL93N72UR_CONTROL0r_reg)); 4667 4668 CL93N72_UR_CTL0r_CLR(CL93N72_USER_RX_CL93N72UR_CONTROL0r_reg); 4669 PHYMOD_IF_ERR_RETURN(READ_CL93N72_UR_CTL0r(pc, &CL93N72_USER_RX_CL93N72UR_CONTROL0r_reg)); 4670 4671 4672 CL93N72_UR_CTL0r_CL93N72_RX_TRAINING_ENf_SET(CL93N72_USER_RX_CL93N72UR_CONTROL0r_reg, 1); 4673 PHYMOD_IF_ERR_RETURN(WRITE_CL93N72_UR_CTL0r(pc, CL93N72_USER_RX_CL93N72UR_CONTROL0r_reg)); 4674 4675 if(cl72_restart) { 4676 #ifdef _DV_TB_ 4677 tmp_port_type = port_type; 4678 port_type = TEFMOD_MULTI_PORT; 4679 #endif 4680 4681 SC_X4_CTLr_CLR(SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg); 4682 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg, 0); 4683 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_CTLr(pc, SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg)); 4684 4685 SC_X4_CTLr_CLR(SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg); 4686 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg, 1); 4687 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_CTLr(pc, SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg)); 4688 4689 #ifdef _DV_TB_ 4690 port_type = tmp_port_type; 4691 #endif 4692 } 4693 return PHYMOD_E_NONE; 4694 } /* CLAUSE_72_CONTROL */ 4695 #endif /* _DV_TB_ */ 4696 4697 #ifdef _SDK_TEFMOD16_ 4698 int tefmod16_clause72_control(PHYMOD_ST* pc, int cl72en) /* CLAUSE_72_CONTROL */ 4699 { 4700 int cl72_enable; 4701 SC_X4_CTLr_t SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg; 4702 CL93N72_IT_BASE_R_PMD_CTLr_t CL93N72_IEEE_TX_CL93N72IT_BASE_R_PMD_CONTROLr_reg; 4703 int start_lane = 0, num_lane = 0 , i=0; 4704 uint32_t enable = 0; 4705 phymod_access_t pa_copy; 4706 4707 TEFMOD16_DBG_IN_FUNC_INFO(pc); 4708 cl72_enable = cl72en & 0x1; 4709 4710 /* need to figure out what's the starting lane */ 4711 PHYMOD_MEMCPY(&pa_copy, pc, sizeof(pa_copy)); 4712 PHYMOD_IF_ERR_RETURN 4713 (phymod_util_lane_config_get(pc, &start_lane, &num_lane)); 4714 pa_copy.lane_mask = 0x1 << start_lane; 4715 4716 4717 CL93N72_IT_BASE_R_PMD_CTLr_CLR(CL93N72_IEEE_TX_CL93N72IT_BASE_R_PMD_CONTROLr_reg); 4718 PHYMOD_IF_ERR_RETURN(READ_CL93N72_IT_BASE_R_PMD_CTLr(&pa_copy, &CL93N72_IEEE_TX_CL93N72IT_BASE_R_PMD_CONTROLr_reg)); 4719 4720 if(CL93N72_IT_BASE_R_PMD_CTLr_CL93N72_IEEE_TRAINING_ENABLEf_GET(CL93N72_IEEE_TX_CL93N72IT_BASE_R_PMD_CONTROLr_reg) != (uint32_t)cl72_enable) { 4721 4722 for (i = (num_lane-1); i >= 0; i--) { 4723 pa_copy.lane_mask = 0x1 << (i + start_lane); 4724 CL93N72_IT_BASE_R_PMD_CTLr_CLR(CL93N72_IEEE_TX_CL93N72IT_BASE_R_PMD_CONTROLr_reg); 4725 PHYMOD_IF_ERR_RETURN(READ_CL93N72_IT_BASE_R_PMD_CTLr(&pa_copy, &CL93N72_IEEE_TX_CL93N72IT_BASE_R_PMD_CONTROLr_reg)); 4726 CL93N72_IT_BASE_R_PMD_CTLr_CL93N72_IEEE_TRAINING_ENABLEf_SET(CL93N72_IEEE_TX_CL93N72IT_BASE_R_PMD_CONTROLr_reg, cl72_enable); 4727 4728 PHYMOD_IF_ERR_RETURN(MODIFY_CL93N72_IT_BASE_R_PMD_CTLr(&pa_copy, CL93N72_IEEE_TX_CL93N72IT_BASE_R_PMD_CONTROLr_reg)); 4729 } 4730 4731 pa_copy.lane_mask = 0x1 << start_lane; 4732 /* release pcs reset */ 4733 tefmod16_enable_get(&pa_copy, &enable); 4734 if(enable) { 4735 SC_X4_CTLr_CLR(SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg); 4736 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg, 0); 4737 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_CTLr(pc, SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg)); 4738 4739 SC_X4_CTLr_CLR(SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg); 4740 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg, 1); 4741 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_CTLr(&pa_copy, SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg)); 4742 } 4743 } 4744 4745 return PHYMOD_E_NONE; 4746 } /* CLAUSE_72_CONTROL */ 4747 #endif /* _SDK_TEFMOD16_ */ 4748 4749 4750 /*! 4751 @brief Sets CJPAT/CRPAT parameters for a particular port 4752 @param pc handle to current TSCF context (#PHYMOD_ST) 4753 @returns The value PHYMOD_E_NONE upon successful completion 4754 @details 4755 This function enables either a CJPAT or CRPAT for a particular port. 4756 */ 4757 4758 int tefmod16_cjpat_crpat_control(PHYMOD_ST* pc) /* CJPAT_CRPAT_CONTROL */ 4759 { 4760 TEFMOD16_DBG_IN_FUNC_INFO(pc); 4761 /* needed only for TSCF-B0 */ 4762 return PHYMOD_E_NONE; 4763 } 4764 4765 /*! 4766 @brief Checks CJPAT/CRPAT parameters for a particular port 4767 @param pc handle to current TSCF context (#PHYMOD_ST) 4768 @returns The value PHYMOD_E_NONE upon successful completion 4769 @details 4770 This function checks for CJPAT or CRPAT for a particular port. 4771 */ 4772 4773 int tefmod16_cjpat_crpat_check(PHYMOD_ST* pc) /* CJPAT_CRPAT_CHECK */ 4774 { 4775 TEFMOD16_DBG_IN_FUNC_INFO(pc); 4776 /* needed only for TSCF-B0 */ 4777 return PHYMOD_E_NONE; 4778 } 4779 /*! 4780 @brief Enables or disables the bit error rate testing for a particular lane. 4781 @param pc handle to current TSCF context (#PHYMOD_ST) 4782 @returns The value PHYMOD_E_NONE upon successful completion. 4783 @details 4784 4785 This function enables or disables bit-error-rate testing (BERT) 4786 4787 TBD 4788 */ 4789 int tefmod16_tx_bert_control(PHYMOD_ST* pc) /* TX_BERT_CONTROL */ 4790 { 4791 TEFMOD16_DBG_IN_FUNC_INFO(pc); 4792 /* needed only for TSCF-B0 */ 4793 return PHYMOD_E_NONE; 4794 } 4795 4796 /* ! 4797 @brief Allows user to set fec_override bit for disabling FEC in 100G AN 4798 @param pc handle to current TSCF context (#PHYMOD_ST) 4799 @param enable bit to enable (1) or disable (0) fec override bit 4800 4801 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_ERROR else 4802 4803 @details 4804 CL91 is ON in 100G AN mode by default.To disable cl91 in 100G the fec 4805 override bit need to be set to 1 by user before turning on AN 4806 4807 @Note 4808 This bit must be set to 0 for all the cases except the above mentioned. 4809 */ 4810 4811 int tefmod16_fec_override_set(PHYMOD_ST* pc, uint32_t enable) 4812 { 4813 SC_X4_SC_X4_OVRRr_t sc_x4_sc_x4_overr_reg; 4814 4815 SC_X4_SC_X4_OVRRr_CLR(sc_x4_sc_x4_overr_reg); 4816 SC_X4_SC_X4_OVRRr_AN_FEC_SEL_OVERRIDEf_SET(sc_x4_sc_x4_overr_reg, enable); 4817 PHYMOD_IF_ERR_RETURN 4818 (MODIFY_SC_X4_SC_X4_OVRRr(pc, sc_x4_sc_x4_overr_reg)); 4819 4820 return PHYMOD_E_NONE; 4821 } 4822 4823 4824 int tefmod16_fec_override_get(PHYMOD_ST* pc, uint32_t *enable) 4825 { 4826 SC_X4_SC_X4_OVRRr_t sc_x4_sc_x4_overr_reg; 4827 4828 PHYMOD_IF_ERR_RETURN 4829 (READ_SC_X4_SC_X4_OVRRr(pc, &sc_x4_sc_x4_overr_reg)); 4830 4831 *enable = SC_X4_SC_X4_OVRRr_AN_FEC_SEL_OVERRIDEf_GET(sc_x4_sc_x4_overr_reg); 4832 4833 return PHYMOD_E_NONE; 4834 4835 } 4836 4837 /*! 4838 @brief enables/disables FEC function. 4839 @brief Controls PMD reset pins irrespective of PCS is in Speed Control mode or not 4840 @param pc handle to current TSCF context (#PHYMOD_ST) 4841 @param fec_en Bit encoded enable for various fec feature 4842 TEFMOD16_CL91_TX_EN_DIS Enable CL91 TX 4843 TEFMOD16_CL91_RX_EN_DIS Enable CL91 RX 4844 TEFMOD16_CL91_IND_ONLY_EN_DIS Enable CL91 indication only 4845 TEFMOD16_CL91_COR_ONLY_EN_DIS Enable CL91 correction only 4846 TEFMOD16_CL74_TX_EN_DIS Enable CL74 TX 4847 TEFMOD16_CL74_RX_EN_DIS Enable CL74 RX 4848 4849 @param fec_dis Bit encoded disable for various fec feature 4850 TEFMOD16_CL91_TX_EN_DIS Disable CL91 TX 4851 TEFMOD16_CL91_RX_EN_DIS Disable CL91 RX 4852 TEFMOD16_CL91_IND_ONLY_EN_DIS Disable CL91 indication only 4853 TEFMOD16_CL91_COR_ONLY_EN_DIS Disable CL91 correction only 4854 TEFMOD16_CL74_TX_EN_DIS Disable CL74 TX 4855 TEFMOD16_CL74_RX_EN_DIS Disable CL74 RX 4856 4857 @param cl74or91 make 100G speed use cl74 after autoneg 4858 bit 1-0 cl74or91 value 4859 4860 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_ERROR else. 4861 4862 @details 4863 To use cl91 in forced speed mode (in 100G only) Tx only fec_en=TEFMOD16_CL91_TX_EN_DIS 4864 To use cl91 in forced speed mode (in 100G only) Rx only fec_en=TEFMOD16_CL91_RX_EN_DIS 4865 To use cl91 in forced speed mode (in 100G only) Tx Rx fec_en=(TEFMOD16_CL91_TX_EN_DIS|TEFMOD16_CL91_RX_EN_DIS) 4866 4867 To enable cl74 Tx only fec_en = TEFMOD16_CL74_TX_EN_DIS 4868 To disable cl74 Tx Rx fec_dis =(TEFMOD16_CL74_TX_EN_DIS|TEFMOD16_CL74_RX_EN_DIS) 4869 4870 Note: cl74 will be enabled per port. 4871 cl91 is used only in 100G (so all 4 lanes make a port) 4872 4873 cl74or91 is only used in autoneg. And other parm used in forced speed. 4874 */ 4875 int tefmod16_FEC_control(PHYMOD_ST* pc, tefmod16_fec_type_t fec_type, int enable, int cl74or91) 4876 { 4877 phymod_access_t pa_copy; 4878 int start_lane = 0, num_lane = 0 ; 4879 uint32_t local_enable = 0; 4880 tefmod16_cl91_fec_mode_t fec_mode = TEFMOD16_CL91_COUNT; 4881 tefmod16_cl91_fec_mode_t current_fec_mode = TEFMOD16_CL91_COUNT; 4882 TX_X4_TX_CTL0r_t TX_X4_TX_CTL0r_reg; 4883 RX_X4_PCS_CTL0r_t RX_X4_PCS_CTL0r_reg; 4884 TX_X4_MISCr_t TX_X4_MISCr_reg; 4885 SC_X4_CTLr_t SC_X4_CTL_reg; 4886 int speed_id; 4887 4888 TEFMOD16_DBG_IN_FUNC_INFO(pc); 4889 PHYMOD_MEMCPY(&pa_copy, pc, sizeof(pa_copy)); 4890 PHYMOD_IF_ERR_RETURN 4891 (phymod_util_lane_config_get(pc, &start_lane, &num_lane)); 4892 pa_copy.lane_mask = 0x1 << start_lane; 4893 4894 TX_X4_TX_CTL0r_CLR(TX_X4_TX_CTL0r_reg); 4895 RX_X4_PCS_CTL0r_CLR(RX_X4_PCS_CTL0r_reg); 4896 TX_X4_MISCr_CLR(TX_X4_MISCr_reg); 4897 SC_X4_CTLr_CLR(SC_X4_CTL_reg); 4898 4899 PHYMOD_IF_ERR_RETURN 4900 (READ_TX_X4_TX_CTL0r(pc, &TX_X4_TX_CTL0r_reg)); 4901 PHYMOD_IF_ERR_RETURN 4902 (READ_RX_X4_PCS_CTL0r(pc, &RX_X4_PCS_CTL0r_reg)); 4903 PHYMOD_IF_ERR_RETURN 4904 (READ_TX_X4_MISCr(pc, &TX_X4_MISCr_reg)); 4905 PHYMOD_IF_ERR_RETURN 4906 (READ_SC_X4_CTLr(pc, &SC_X4_CTL_reg)); 4907 4908 current_fec_mode = TX_X4_TX_CTL0r_CL91_FEC_MODEf_GET(TX_X4_TX_CTL0r_reg) ; 4909 4910 if(enable < TEFMOD16_PHY_CONTROL_FEC_AUTO) { 4911 if (fec_type == TEFMOD16_CL91) { 4912 if (enable) { 4913 switch (num_lane) { 4914 case 1: 4915 fec_mode = TEFMOD16_CL91_SINGLE_LANE_BRCM_PROP; 4916 break; 4917 case 2: 4918 fec_mode = TEFMOD16_CL91_DUAL_LANE_BRCM_PROP; 4919 break; 4920 case 4: 4921 fec_mode = TEFMOD16_CL91_QUAD_LANE; 4922 break; 4923 default: 4924 fec_mode = TEFMOD16_CL91_SINGLE_LANE_BRCM_PROP; 4925 break; 4926 } 4927 } else { 4928 if (current_fec_mode == TEFMOD16_IEEE_25G_CL91_SINGLE_LANE) { 4929 return PHYMOD_E_INTERNAL; 4930 } else { 4931 fec_mode = TEFMOD16_NO_CL91_FEC; 4932 } 4933 } 4934 4935 /*In Broadcom 25G FEC or in no FEC mode, speed id is S_25G_X1 (0x12)*/ 4936 if (num_lane == 1) { 4937 if((fec_mode == TEFMOD16_CL91_SINGLE_LANE_BRCM_PROP) 4938 || (fec_mode == TEFMOD16_NO_CL91_FEC)) 4939 { 4940 tefmod16_speed_id_get(pc, &speed_id); 4941 /*If current speed id is IEEE 25G, it need to be recoverd to Broadcom 25G*/ 4942 if (speed_id == sc_x4_control_sc_S_25G_KR_IEEE) { 4943 speed_id = sc_x4_control_sc_S_25G_X1; 4944 SC_X4_CTLr_SPEEDf_SET(SC_X4_CTL_reg, speed_id); 4945 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_CTLr(pc, SC_X4_CTL_reg)); 4946 } 4947 } 4948 } 4949 4950 TX_X4_TX_CTL0r_CL91_FEC_MODEf_SET(TX_X4_TX_CTL0r_reg, fec_mode); 4951 RX_X4_PCS_CTL0r_CL91_FEC_MODEf_SET(RX_X4_PCS_CTL0r_reg, fec_mode); 4952 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_TX_CTL0r(pc, TX_X4_TX_CTL0r_reg)); 4953 PHYMOD_IF_ERR_RETURN(MODIFY_RX_X4_PCS_CTL0r(pc, RX_X4_PCS_CTL0r_reg)); 4954 4955 } else if (fec_type == TEFMOD16_CL108) { 4956 int current_speed_id; 4957 4958 if (num_lane != 1) { 4959 return PHYMOD_E_INTERNAL; 4960 } 4961 4962 if (enable) { 4963 fec_mode = TEFMOD16_IEEE_25G_CL91_SINGLE_LANE; 4964 } else { 4965 if (current_fec_mode != TEFMOD16_IEEE_25G_CL91_SINGLE_LANE) { 4966 return PHYMOD_E_INTERNAL; 4967 } else { 4968 fec_mode = TEFMOD16_NO_CL91_FEC; 4969 } 4970 } 4971 4972 tefmod16_speed_id_get(pc, ¤t_speed_id); 4973 speed_id = current_speed_id; 4974 4975 if ((current_speed_id == sc_x4_control_sc_S_25G_KR_IEEE) 4976 || (current_speed_id == sc_x4_control_sc_S_25G_X1)) { 4977 if (fec_mode == TEFMOD16_NO_CL91_FEC) { 4978 speed_id = sc_x4_control_sc_S_25G_X1; 4979 } else if (fec_mode == TEFMOD16_IEEE_25G_CL91_SINGLE_LANE) { 4980 speed_id = sc_x4_control_sc_S_25G_KR_IEEE; 4981 } 4982 4983 if (speed_id != current_speed_id) { 4984 SC_X4_CTLr_SPEEDf_SET(SC_X4_CTL_reg, speed_id); 4985 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_CTLr(pc, SC_X4_CTL_reg)); 4986 } 4987 } 4988 4989 TX_X4_TX_CTL0r_CL91_FEC_MODEf_SET(TX_X4_TX_CTL0r_reg, fec_mode); 4990 RX_X4_PCS_CTL0r_CL91_FEC_MODEf_SET(RX_X4_PCS_CTL0r_reg, fec_mode); 4991 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_TX_CTL0r(pc, TX_X4_TX_CTL0r_reg)); 4992 PHYMOD_IF_ERR_RETURN(MODIFY_RX_X4_PCS_CTL0r(pc, RX_X4_PCS_CTL0r_reg)); 4993 } else {/* cl74 */ 4994 if (enable) { 4995 TX_X4_MISCr_FEC_ENABLEf_SET(TX_X4_MISCr_reg, 1); 4996 RX_X4_PCS_CTL0r_FEC_ENABLEf_SET(RX_X4_PCS_CTL0r_reg, 1); 4997 } else { 4998 TX_X4_MISCr_FEC_ENABLEf_SET(TX_X4_MISCr_reg, 0); 4999 RX_X4_PCS_CTL0r_FEC_ENABLEf_SET(RX_X4_PCS_CTL0r_reg, 0); 5000 } 5001 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_MISCr(pc, TX_X4_MISCr_reg)); 5002 PHYMOD_IF_ERR_RETURN(MODIFY_RX_X4_PCS_CTL0r(pc, RX_X4_PCS_CTL0r_reg)); 5003 } 5004 } 5005 5006 tefmod16_enable_get(&pa_copy, &local_enable); 5007 if (local_enable) { 5008 SC_X4_CTLr_t SC_X4_CTLr_reg; 5009 SC_X4_CTLr_CLR(SC_X4_CTLr_reg); 5010 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(SC_X4_CTLr_reg, 0); 5011 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_CTLr(&pa_copy, SC_X4_CTLr_reg)); 5012 5013 SC_X4_CTLr_CLR(SC_X4_CTLr_reg); 5014 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(SC_X4_CTLr_reg, 1); 5015 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_CTLr(&pa_copy, SC_X4_CTLr_reg)); 5016 } 5017 5018 return PHYMOD_E_NONE; 5019 } 5020 5021 int tefmod16_FEC_get(PHYMOD_ST* pc, tefmod16_fec_type_t fec_type, int *fec_en) 5022 { 5023 uint32_t fec_mode ; 5024 int speed_id; 5025 int rev_letter; 5026 SC_X4_FEC_STSr_t SC_X4_FINAL_CONFIG_STATUS_FEC_STATUSr_reg; 5027 MAIN0_SERDESIDr_t serdesid; 5028 5029 *fec_en = 0; 5030 5031 SC_X4_FEC_STSr_CLR(SC_X4_FINAL_CONFIG_STATUS_FEC_STATUSr_reg); 5032 READ_SC_X4_FEC_STSr(pc, &SC_X4_FINAL_CONFIG_STATUS_FEC_STATUSr_reg); 5033 5034 if ((fec_type == TEFMOD16_CL91) || (fec_type == TEFMOD16_CL108)) { 5035 fec_mode = SC_X4_FEC_STSr_T_CL91_FEC_MODEf_GET(SC_X4_FINAL_CONFIG_STATUS_FEC_STATUSr_reg); 5036 5037 switch (fec_mode) { 5038 case TEFMOD16_NO_CL91_FEC: 5039 *fec_en = 0; 5040 break; 5041 case TEFMOD16_CL91_SINGLE_LANE_BRCM_PROP: 5042 READ_MAIN0_SERDESIDr(pc, &serdesid); 5043 rev_letter = MAIN0_SERDESIDr_REV_LETTERf_GET(serdesid); 5044 5045 /* revision A can't distinguish CL91 and CL108 FEC, so check speed ID */ 5046 if (rev_letter == REV_A) { 5047 PHYMOD_IF_ERR_RETURN(tefmod16_speed_id_get(pc, &speed_id)); 5048 if (speed_id == sc_x4_control_sc_S_25G_KR_IEEE || speed_id == sc_x4_control_sc_S_25G_CR_IEEE) { 5049 *fec_en = (fec_type == TEFMOD16_CL108 ? 1 : 0); 5050 } else { 5051 *fec_en = (fec_type == TEFMOD16_CL91 ? 1 : 0); 5052 } 5053 } else { 5054 *fec_en = (fec_type == TEFMOD16_CL91 ? 1 : 0); 5055 } 5056 break; 5057 case TEFMOD16_CL91_SINGLE_LANE_FC: 5058 case TEFMOD16_CL91_DUAL_LANE_BRCM_PROP: 5059 case TEFMOD16_CL91_QUAD_LANE: 5060 *fec_en = (fec_type == TEFMOD16_CL91 ? 1 : 0); 5061 break; 5062 case TEFMOD16_IEEE_25G_CL91_SINGLE_LANE: 5063 *fec_en = (fec_type == TEFMOD16_CL108 ? 1 : 0); 5064 break; 5065 default: 5066 break; 5067 } 5068 } else { 5069 *fec_en = SC_X4_FEC_STSr_T_FEC_ENABLEf_GET(SC_X4_FINAL_CONFIG_STATUS_FEC_STATUSr_reg); 5070 } 5071 5072 return PHYMOD_E_NONE; 5073 } 5074 5075 int tefmod16_cl74_fec_control(PHYMOD_ST *pc, int cl74_en) /*CL74_FEC_CONTROL */ 5076 { 5077 TX_X4_MISCr_t TX_X4_MISCr_reg; 5078 RX_X4_PCS_CTL0r_t RX_X4_PCS_CTL0r_reg; 5079 5080 TEFMOD16_DBG_IN_FUNC_INFO(pc); 5081 5082 TX_X4_MISCr_CLR(TX_X4_MISCr_reg); 5083 TX_X4_MISCr_FEC_ENABLEf_SET(TX_X4_MISCr_reg, cl74_en); 5084 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_MISCr(pc, TX_X4_MISCr_reg)); 5085 5086 RX_X4_PCS_CTL0r_CLR(RX_X4_PCS_CTL0r_reg); 5087 RX_X4_PCS_CTL0r_FEC_ENABLEf_SET(RX_X4_PCS_CTL0r_reg, cl74_en); 5088 PHYMOD_IF_ERR_RETURN(MODIFY_RX_X4_PCS_CTL0r(pc, RX_X4_PCS_CTL0r_reg)); 5089 5090 return PHYMOD_E_NONE; 5091 5092 } 5093 5094 /*! 5095 @brief Power down transmitter or receiver per lane basis. 5096 @param pc handle to current TSCF context (a.k.a #PHYMOD_ST) 5097 @param tx control for power of TX path 5098 @param rx control for power of RX path 5099 @returns PHYMOD_E_NONE if no errors. PHYMOD_EERROR else. 5100 @details 5101 Indi 5102 */ 5103 int tefmod16_power_control(PHYMOD_ST* pc, int tx, int rx) 5104 { 5105 PMD_X4_CTLr_t PMD_X4_PMD_X4_CONTROLr_reg; 5106 5107 TEFMOD16_DBG_IN_FUNC_INFO(pc); 5108 PMD_X4_CTLr_CLR(PMD_X4_PMD_X4_CONTROLr_reg); 5109 5110 PMD_X4_CTLr_LN_RX_H_PWRDNf_SET(PMD_X4_PMD_X4_CONTROLr_reg, rx); 5111 PMD_X4_CTLr_LN_TX_H_PWRDNf_SET(PMD_X4_PMD_X4_CONTROLr_reg, tx); 5112 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X4_CTLr(pc, PMD_X4_PMD_X4_CONTROLr_reg)); 5113 return PHYMOD_E_NONE; 5114 } 5115 5116 /*! 5117 @brief sets the lanes in Full Duplex/ half duplex mode. 5118 @param pc handle to current TSCF context (a.k.a tefmod struct) 5119 @returns PHYMOD_E_NONE if no errors. PHYMOD_EERROR else. 5120 @details 5121 This is bit encoded function. Bit 3 to 0 is for lane 3 to 0. High sets full 5122 duplex. Low is for half duplex. 5123 5124 <B>Currently, this function is not implemented</B> 5125 */ 5126 int tefmod16_duplex_control(PHYMOD_ST* pc) 5127 { 5128 TEFMOD16_DBG_IN_FUNC_INFO(pc); 5129 /* needed for B0 */ 5130 return PHYMOD_E_NONE; 5131 } 5132 5133 /*! 5134 @brief Set reference clock 5135 @param pc handle to current TSCF context (a.k.a tefmod struct) 5136 @param ref_clk The reference clock to set the PHY to. 5137 @returns PHYMOD_E_NONE if no errors. PHYMOD_EERROR else. 5138 @details 5139 The reference clock is set to inform the micro. The value written into the 5140 register is interpreted by the micro as thus. 5141 5142 refclk = regVal * 2 + 100; 5143 5144 Since the refclk field is 7 bits, the range is 100 - 228 5145 5146 */ 5147 5148 int tefmod16_refclk_get(PHYMOD_ST* pc, phymod_ref_clk_t* ref_clk) 5149 { 5150 MAIN0_SETUPr_t MAIN0_SETUPr_reg; 5151 5152 TEFMOD16_DBG_IN_FUNC_INFO(pc); 5153 MAIN0_SETUPr_CLR(MAIN0_SETUPr_reg); 5154 READ_MAIN0_SETUPr(pc, &MAIN0_SETUPr_reg); 5155 *ref_clk = MAIN0_SETUPr_REFCLK_SELf_GET(MAIN0_SETUPr_reg); 5156 5157 return PHYMOD_E_NONE; 5158 } 5159 5160 /*! 5161 @brief disables the PCS by clearing the writing to Speed control reg 5162 @param pc handle to current TSCF context (#PHYMOD_ST) 5163 @returns The value PHYMOD_E_NONE upon successful completion. 5164 @details 5165 TBD 5166 */ 5167 5168 #ifdef _DV_TB_ 5169 int tefmod16_disable_pcs_falcon(PHYMOD_ST* pc) 5170 { 5171 SC_X4_CTLr_t SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg; 5172 5173 TEFMOD16_DBG_IN_FUNC_INFO(pc); 5174 SC_X4_CTLr_CLR(SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg); 5175 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg, 0); 5176 5177 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_CTLr(pc, SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg)); 5178 5179 return PHYMOD_E_NONE; 5180 } 5181 #endif /* _DV_TB_*/ 5182 5183 /*! 5184 @brief sets PMD TX lane swap values for all lanes simultaneously. 5185 @param pc handle to current TSCF context (#PHYMOD_ST) 5186 @param per_lane_control controls the lane feature 5187 @returns The value PHYMOD_E_NONE upon successful completion 5188 @details 5189 This function sets the TX lane swap values for all lanes simultaneously. 5190 5191 The TSCF has several two sets of lane swap registers per lane. This function 5192 uses the lane swap registers closest to the pads. For TX, the lane swap occurs 5193 after all other analog/digital functionality. For RX, the lane swap occurs 5194 prior to all other analog/digital functionality. 5195 5196 Swap must be the first thing to do after reset/PLL configuration. 5197 5198 How the swap is done is indicated in the per_lane_control argument. 5199 bits 0 through 15 represent the swap settings for RX while bits 16 5200 through 31 represent the swap settings for TX. 5201 5202 Each 4 bit chunk within both the RX and TX sections represent the swap settings 5203 for a particular lane as follows: 5204 5205 Bits lane assignment 5206 5207 \li 15:12 TX lane 3 5208 \li 11:8 TX lane 2 5209 \li 7:4 TX lane 1 5210 \li 3:0 TX lane 0 5211 5212 Each 4-bit value may be either 0, 1, 2 or 3, with the value indicating the lane 5213 mapping. By default, the equivalent per_lane_control settings are 0x3210_3210, 5214 indicating that there is no re-routing of traffic. As an example, to swap lanes 5215 0 and 1 for both RX and TX, the per_lane_control should be set to 0x3201_3201. 5216 To swap lanes 0 and 1, and also lanes 2 and 3 for both RX and TX, the 5217 per_lane_control should be set to 0x2301_2301. 5218 5219 This function modifies the following registers: 5220 5221 \li MAIN0_LN_SWP (0x9003) 5222 */ 5223 int tefmod16_pmd_addr_lane_swap(PHYMOD_ST *pc, int per_lane_control) 5224 { 5225 5226 return PHYMOD_E_NONE; 5227 } 5228 5229 /*! 5230 @brief sets PMD TX lane swap values for all lanes simultaneously. 5231 @param pc handle to current TSCF context (#PHYMOD_ST) 5232 @param per_lane_control controls the lane swap 5233 @returns The value PHYMOD_E_NONE upon successful completion 5234 @details 5235 This function sets the TX lane swap values for all lanes simultaneously. 5236 5237 The TSCF has several two sets of lane swap registers per lane. This function 5238 uses the lane swap registers closest to the pads. For TX, the lane swap occurs 5239 after all other analog/digital functionality. For RX, the lane swap occurs 5240 prior to all other analog/digital functionality. 5241 5242 It is not allowed to swap lanes without going through reset. 5243 5244 How the swap is done is indicated in the per_lane_control field; 5245 bits 0 through 15 represent the swap settings for RX while bits 16 5246 through 31 represent the swap settings for TX. 5247 5248 Each 4 bit chunk within both the RX and TX sections represent the swap settings 5249 for a particular lane as follows: 5250 5251 Bits lane assignment 5252 5253 \li 15:12 TX lane 3 5254 \li 11:8 TX lane 2 5255 \li 7:4 TX lane 1 5256 \li 3:0 TX lane 0 5257 5258 Each 4-bit value may be either 0, 1, 2 or 3, with the value indicating the lane 5259 mapping. By default, the equivalent per_lane_control settings are 0x3210_3210, 5260 indicating that there is no re-routing of traffic. As an example, to swap lanes 5261 0 and 1 for both RX and TX, the per_lane_control should be set to 0x3201_3201. 5262 To swap lanes 0 and 1, and also lanes 2 and 3 for both RX and TX, the 5263 per_lane_control should be set to 0x2301_2301. 5264 5265 This function modifies the following registers: 5266 5267 \li MAIN0_LN_SWP (0x9003) 5268 */ 5269 #if 0 5270 int tefmod16_pmd_lane_swap_tx(PHYMOD_ST *pc, int per_lane_control) 5271 { 5272 unsigned int map; 5273 unsigned int tx_lane_map_0, tx_lane_map_1, tx_lane_map_2, tx_lane_map_3; 5274 DIG_TX_LN_MAP_0_1_2r_t DIG_COM_TX_LANE_MAP_0_1_2r_reg; 5275 DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r_t DIG_COM_TX_LANE_MAP_3_N_LANE_ADDR_0_1r_reg; 5276 5277 TEFMOD16_DBG_IN_FUNC_INFO(pc); 5278 map = (unsigned int)per_lane_control; 5279 tx_lane_map_0 = (map >> 0) & 0xf; 5280 tx_lane_map_1 = (map >> 4) & 0xf; 5281 tx_lane_map_2 = (map >> 8) & 0xf; 5282 tx_lane_map_3 = (map >> 12)& 0xf; 5283 5284 #ifdef _DV_TB_ 5285 pc->adjust_port_mode = 1; 5286 #endif 5287 DIG_TX_LN_MAP_0_1_2r_CLR(DIG_COM_TX_LANE_MAP_0_1_2r_reg); 5288 5289 DIG_TX_LN_MAP_0_1_2r_TX_LANE_MAP_2f_SET(DIG_COM_TX_LANE_MAP_0_1_2r_reg, tx_lane_map_2); 5290 DIG_TX_LN_MAP_0_1_2r_TX_LANE_MAP_1f_SET(DIG_COM_TX_LANE_MAP_0_1_2r_reg, tx_lane_map_1); 5291 DIG_TX_LN_MAP_0_1_2r_TX_LANE_MAP_0f_SET(DIG_COM_TX_LANE_MAP_0_1_2r_reg, tx_lane_map_0); 5292 PHYMOD_IF_ERR_RETURN(MODIFY_DIG_TX_LN_MAP_0_1_2r(pc, DIG_COM_TX_LANE_MAP_0_1_2r_reg)); 5293 5294 DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r_CLR(DIG_COM_TX_LANE_MAP_3_N_LANE_ADDR_0_1r_reg); 5295 DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r_TX_LANE_MAP_3f_SET(DIG_COM_TX_LANE_MAP_3_N_LANE_ADDR_0_1r_reg, tx_lane_map_3); 5296 PHYMOD_IF_ERR_RETURN(MODIFY_DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r(pc, DIG_COM_TX_LANE_MAP_3_N_LANE_ADDR_0_1r_reg)); 5297 5298 #ifdef _DV_TB_ 5299 pc->adjust_port_mode = 0; 5300 #endif 5301 5302 return PHYMOD_E_NONE; 5303 } 5304 #endif /* end if 0*/ 5305 5306 int tefmod16_pmd_lane_swap(PHYMOD_ST *pc, int tx_lane_swap, int rx_lane_swap) 5307 { 5308 5309 unsigned int tx_map, rx_map; 5310 LN_ADDR0r_t LN_ADDR0r_reg; 5311 LN_ADDR1r_t LN_ADDR1r_reg; 5312 LN_ADDR2r_t LN_ADDR2r_reg; 5313 LN_ADDR3r_t LN_ADDR3r_reg; 5314 5315 TEFMOD16_DBG_IN_FUNC_INFO(pc); 5316 tx_map = (unsigned int)tx_lane_swap; 5317 rx_map = (unsigned int)rx_lane_swap; 5318 5319 LN_ADDR0r_CLR(LN_ADDR0r_reg); 5320 LN_ADDR1r_CLR(LN_ADDR1r_reg); 5321 LN_ADDR2r_CLR(LN_ADDR2r_reg); 5322 LN_ADDR3r_CLR(LN_ADDR3r_reg); 5323 5324 LN_ADDR0r_TX_LANE_ADDR_0f_SET(LN_ADDR0r_reg, ((tx_map >> 0) & 0xf)); 5325 LN_ADDR1r_TX_LANE_ADDR_1f_SET(LN_ADDR1r_reg, ((tx_map >> 4) & 0xf)); 5326 LN_ADDR2r_TX_LANE_ADDR_2f_SET(LN_ADDR2r_reg, ((tx_map >> 8) & 0xf)); 5327 LN_ADDR3r_TX_LANE_ADDR_3f_SET(LN_ADDR3r_reg, ((tx_map >> 12) & 0xf)); 5328 5329 LN_ADDR0r_RX_LANE_ADDR_0f_SET(LN_ADDR0r_reg, ((rx_map >> 0) & 0xf)); 5330 LN_ADDR1r_RX_LANE_ADDR_1f_SET(LN_ADDR1r_reg, ((rx_map >> 4) & 0xf)); 5331 LN_ADDR2r_RX_LANE_ADDR_2f_SET(LN_ADDR2r_reg, ((rx_map >> 8) & 0xf)); 5332 LN_ADDR3r_RX_LANE_ADDR_3f_SET(LN_ADDR3r_reg, ((rx_map >> 12) & 0xf)); 5333 5334 PHYMOD_IF_ERR_RETURN(MODIFY_LN_ADDR0r(pc, LN_ADDR0r_reg)); 5335 PHYMOD_IF_ERR_RETURN(MODIFY_LN_ADDR1r(pc, LN_ADDR1r_reg)); 5336 PHYMOD_IF_ERR_RETURN(MODIFY_LN_ADDR2r(pc, LN_ADDR2r_reg)); 5337 PHYMOD_IF_ERR_RETURN(MODIFY_LN_ADDR3r(pc, LN_ADDR3r_reg)); 5338 5339 return PHYMOD_E_NONE; 5340 } 5341 5342 5343 5344 #ifdef _DV_TB_ 5345 /*! 5346 @brief removes resets from all the PMD lanes 5347 @param pc handle to current TSCF context (#PHYMOD_ST) 5348 @returns The value PHYMOD_E_NONE upon successful completion 5349 @details 5350 Removes resets 5351 */ 5352 5353 int tefmod16_pmd_reset_remove(PHYMOD_ST *pc, int pmd_touched) 5354 { 5355 uint16_t data; 5356 PMD_X1_CTLr_t PMD_X1_PMD_X1_CONTROLr_reg; 5357 PMD_X4_CTLr_t PMD_X4_PMD_X4_CONTROLr_reg; 5358 5359 TEFMOD16_DBG_IN_FUNC_INFO(pc); 5360 data = 0; 5361 5362 if(pmd_touched == 0) { 5363 PMD_X1_CTLr_CLR(PMD_X1_PMD_X1_CONTROLr_reg); 5364 /* setup the PMD reset */ 5365 PMD_X1_CTLr_POR_H_RSTBf_SET(PMD_X1_PMD_X1_CONTROLr_reg, 1); 5366 PMD_X1_CTLr_CORE_DP_H_RSTBf_SET(PMD_X1_PMD_X1_CONTROLr_reg, 1); 5367 5368 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X1_CTLr(pc, PMD_X1_PMD_X1_CONTROLr_reg)); 5369 } 5370 5371 data = 0; 5372 5373 PMD_X4_CTLr_CLR(PMD_X4_PMD_X4_CONTROLr_reg); 5374 PMD_X4_CTLr_LN_RX_H_PWRDNf_SET(PMD_X4_PMD_X4_CONTROLr_reg, 0); 5375 PMD_X4_CTLr_LN_TX_H_PWRDNf_SET(PMD_X4_PMD_X4_CONTROLr_reg, 0); 5376 5377 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X4_CTLr(pc, PMD_X4_PMD_X4_CONTROLr_reg)); 5378 5379 PMD_X4_CTLr_CLR(PMD_X4_PMD_X4_CONTROLr_reg); 5380 PMD_X4_CTLr_LN_H_RSTBf_SET(PMD_X4_PMD_X4_CONTROLr_reg, 1); 5381 PMD_X4_CTLr_LN_DP_H_RSTBf_SET(PMD_X4_PMD_X4_CONTROLr_reg, 1); 5382 5383 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X4_CTLr(pc, PMD_X4_PMD_X4_CONTROLr_reg)); 5384 5385 return PHYMOD_E_NONE; 5386 } 5387 #endif 5388 5389 /*! 5390 @brief sets both the RX and TX lane swap values for all lanes simultaneously. 5391 @param pc handle to current TSCF context (#PHYMOD_ST) 5392 @param per_lane_control TBD 5393 @returns The value PHYMOD_E_NONE upon successful completion 5394 @details 5395 This function sets the TX lane swap values for all lanes simultaneously. 5396 5397 The TSCF has several two sets of lane swap registers per lane. This function 5398 uses the lane swap registers closest to the pads. For TX, the lane swap occurs 5399 after all other analog/digital functionality. For RX, the lane swap occurs 5400 prior to all other analog/digital functionality. 5401 5402 It is not advisable to swap lanes without going through reset. 5403 5404 How the swap is done is indicated in the per_lane_control field; bits 0 through 5405 15 represent the swap settings for RX while bits 16 through 31 represent the 5406 swap settings for TX. 5407 5408 Each 4 bit chunk within both the RX and TX sections represent the swap settings 5409 for a particular lane as follows: 5410 5411 Bits lane assignment 5412 5413 \li 15:12 TX lane 3 5414 \li 11:8 TX lane 2 5415 \li 7:4 TX lane 1 5416 \li 3:0 TX lane 0 5417 5418 Each 4-bit value may be either 0, 1, 2 or 3, with the value indicating the lane 5419 mapping. By default, the equivalent per_lane_control settings are 0x3210_3210, 5420 indicating that there is no re-routing of traffic. As an example, to swap lanes 5421 0 and 1 for both RX and TX, the per_lane_control should be set to 0x3201_3201. 5422 To swap lanes 0 and 1, and also lanes 2 and 3 for both RX and TX, the 5423 per_lane_control should be set to 0x2301_2301. 5424 5425 This function modifies the following registers: 5426 */ 5427 /* TSCF_GEN2 : Rx lane swap */ 5428 int tefmod16_pcs_rx_lane_swap(PHYMOD_ST *pc, int rx_lane_swap) 5429 { 5430 unsigned int map; 5431 RX_X1_RX_LN_SWPr_t RX_X1_RX_LN_SWPr_reg; 5432 5433 TEFMOD16_DBG_IN_FUNC_INFO(pc); 5434 map = (unsigned int)rx_lane_swap; 5435 5436 RX_X1_RX_LN_SWPr_CLR(RX_X1_RX_LN_SWPr_reg); 5437 RX_X1_RX_LN_SWPr_LOGICAL3_TO_PHY_SELf_SET(RX_X1_RX_LN_SWPr_reg, ((map >> 12) & 0x3)); 5438 RX_X1_RX_LN_SWPr_LOGICAL2_TO_PHY_SELf_SET(RX_X1_RX_LN_SWPr_reg, ((map >> 8) & 0x3)); 5439 RX_X1_RX_LN_SWPr_LOGICAL1_TO_PHY_SELf_SET(RX_X1_RX_LN_SWPr_reg, ((map >> 4) & 0x3)); 5440 RX_X1_RX_LN_SWPr_LOGICAL0_TO_PHY_SELf_SET(RX_X1_RX_LN_SWPr_reg, ((map >> 0) & 0x3)); 5441 5442 PHYMOD_IF_ERR_RETURN(MODIFY_RX_X1_RX_LN_SWPr(pc, RX_X1_RX_LN_SWPr_reg)); 5443 5444 return PHYMOD_E_NONE; 5445 } 5446 5447 /* TSCF_GEN2 : Tx lane swap */ 5448 int tefmod16_pcs_tx_lane_swap(PHYMOD_ST *pc, int tx_lane_swap) 5449 { 5450 unsigned int map; 5451 TX_X1_TX_LN_SWPr_t TX_X1_TX_LN_SWPr_reg; 5452 5453 TEFMOD16_DBG_IN_FUNC_INFO(pc); 5454 map = (unsigned int)tx_lane_swap; 5455 5456 TX_X1_TX_LN_SWPr_CLR(TX_X1_TX_LN_SWPr_reg); 5457 TX_X1_TX_LN_SWPr_LOGICAL2_TO_PHY_SELf_SET(TX_X1_TX_LN_SWPr_reg, ((map >> 8) & 0x3)); 5458 TX_X1_TX_LN_SWPr_LOGICAL3_TO_PHY_SELf_SET(TX_X1_TX_LN_SWPr_reg, ((map >> 12) & 0x3)); 5459 TX_X1_TX_LN_SWPr_LOGICAL1_TO_PHY_SELf_SET(TX_X1_TX_LN_SWPr_reg, ((map >> 4) & 0x3)); 5460 TX_X1_TX_LN_SWPr_LOGICAL0_TO_PHY_SELf_SET(TX_X1_TX_LN_SWPr_reg, ((map >> 0) & 0x3)); 5461 5462 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X1_TX_LN_SWPr(pc, TX_X1_TX_LN_SWPr_reg)); 5463 5464 return PHYMOD_E_NONE; 5465 } 5466 5467 #ifdef _DV_TB_ 5468 /*! 5469 @brief configure soft table entry 5470 @param pc handle to current TSCF context (#PHYMOD_ST) 5471 @returns The value PHYMOD_E_NONE upon successful completion 5472 @details 5473 5474 This is a tier2 function, whenever something from Hard table needs to be overwritten 5475 using soft table, this function is called. 5476 There are 4 sets of regs to override. These regs are global sc_x1_speed_override0 .. override3 5477 */ 5478 int configure_st_entry(int st_entry_num, int st_entry_speed, PHYMOD_ST* pc) 5479 { 5480 SC_X1_SPD_OVRR0_SPDr_t SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEEDr_reg; 5481 SC_X1_SPD_OVRR1_SPDr_t SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEEDr_reg; 5482 SC_X1_SPD_OVRR2_SPDr_t SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEEDr_reg; 5483 SC_X1_SPD_OVRR3_SPDr_t SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEEDr_reg; 5484 5485 SC_X1_SPD_OVRR0_0r_t SC_X1_SPEED_OVERRIDE0_OVERRIDE_0r_reg; 5486 SC_X1_SPD_OVRR1_0r_t SC_X1_SPEED_OVERRIDE1_OVERRIDE_0r_reg; 5487 SC_X1_SPD_OVRR2_0r_t SC_X1_SPEED_OVERRIDE2_OVERRIDE_0r_reg; 5488 SC_X1_SPD_OVRR3_0r_t SC_X1_SPEED_OVERRIDE3_OVERRIDE_0r_reg; 5489 5490 SC_X1_SPD_OVRR0_1r_t SC_X1_SPEED_OVERRIDE0_OVERRIDE_1r_reg; 5491 SC_X1_SPD_OVRR1_1r_t SC_X1_SPEED_OVERRIDE1_OVERRIDE_1r_reg; 5492 SC_X1_SPD_OVRR2_1r_t SC_X1_SPEED_OVERRIDE2_OVERRIDE_1r_reg; 5493 SC_X1_SPD_OVRR3_1r_t SC_X1_SPEED_OVERRIDE3_OVERRIDE_1r_reg; 5494 5495 SC_X1_SPD_OVRR0_2r_t SC_X1_SPEED_OVERRIDE0_OVERRIDE_2r_reg; 5496 SC_X1_SPD_OVRR1_2r_t SC_X1_SPEED_OVERRIDE1_OVERRIDE_2r_reg; 5497 SC_X1_SPD_OVRR2_2r_t SC_X1_SPEED_OVERRIDE2_OVERRIDE_2r_reg; 5498 SC_X1_SPD_OVRR3_2r_t SC_X1_SPEED_OVERRIDE3_OVERRIDE_2r_reg; 5499 5500 SC_X1_SPD_OVRR0_3r_t SC_X1_SPEED_OVERRIDE0_OVERRIDE_3r_reg; 5501 SC_X1_SPD_OVRR1_3r_t SC_X1_SPEED_OVERRIDE1_OVERRIDE_3r_reg; 5502 SC_X1_SPD_OVRR2_3r_t SC_X1_SPEED_OVERRIDE2_OVERRIDE_3r_reg; 5503 SC_X1_SPD_OVRR3_3r_t SC_X1_SPEED_OVERRIDE3_OVERRIDE_3r_reg; 5504 5505 SC_X1_SPD_OVRR0_4r_t SC_X1_SPEED_OVERRIDE0_OVERRIDE_4r_reg; 5506 SC_X1_SPD_OVRR1_4r_t SC_X1_SPEED_OVERRIDE1_OVERRIDE_4r_reg; 5507 SC_X1_SPD_OVRR2_4r_t SC_X1_SPEED_OVERRIDE2_OVERRIDE_4r_reg; 5508 SC_X1_SPD_OVRR3_4r_t SC_X1_SPEED_OVERRIDE3_OVERRIDE_4r_reg; 5509 5510 SC_X1_SPD_OVRR0_5r_t SC_X1_SPEED_OVERRIDE0_OVERRIDE_5r_reg; 5511 SC_X1_SPD_OVRR1_5r_t SC_X1_SPEED_OVERRIDE1_OVERRIDE_5r_reg; 5512 SC_X1_SPD_OVRR2_5r_t SC_X1_SPEED_OVERRIDE2_OVERRIDE_5r_reg; 5513 SC_X1_SPD_OVRR3_5r_t SC_X1_SPEED_OVERRIDE3_OVERRIDE_5r_reg; 5514 5515 SC_X1_SPD_OVRR0_6r_t SC_X1_SPD_OVRR0_6r_reg; 5516 SC_X1_SPD_OVRR1_6r_t SC_X1_SPD_OVRR1_6r_reg; 5517 SC_X1_SPD_OVRR2_6r_t SC_X1_SPD_OVRR2_6r_reg; 5518 SC_X1_SPD_OVRR3_6r_t SC_X1_SPD_OVRR3_6r_reg; 5519 5520 TEFMOD16_DBG_IN_FUNC_INFO(pc); 5521 5522 pc->speed = st_entry_speed; 5523 /* st_entry_num can be 0, 1, 2, or 3 */ 5524 if (pc->verbosity) 5525 PHYMOD_DEBUG_ERROR(("Using speed_id: %x and st_entry_num: %x", st_entry_speed, st_entry_num)); 5526 5527 if (st_entry_num == 0) { 5528 SC_X1_SPD_OVRR0_SPDr_CLR(SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEEDr_reg); 5529 SC_X1_SPD_OVRR0_SPDr_SPEEDf_SET(SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEEDr_reg, st_entry_speed); 5530 5531 SC_X1_SPD_OVRR0_SPDr_NUM_LANESf_SET(SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEEDr_reg, (pc->num_lanes)); 5532 5533 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR0_SPDr(pc, SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEEDr_reg)); 5534 5535 5536 SC_X1_SPD_OVRR0_0r_CLR(SC_X1_SPEED_OVERRIDE0_OVERRIDE_0r_reg); 5537 SC_X1_SPD_OVRR0_0r_OS_MODEf_SET(SC_X1_SPEED_OVERRIDE0_OVERRIDE_0r_reg, (pc->os_mode)); 5538 5539 SC_X1_SPD_OVRR0_0r_SCR_MODEf_SET(SC_X1_SPEED_OVERRIDE0_OVERRIDE_0r_reg, (pc->scr_mode)); 5540 5541 SC_X1_SPD_OVRR0_0r_T_ENC_MODEf_SET(SC_X1_SPEED_OVERRIDE0_OVERRIDE_0r_reg, (pc->t_enc_mode)); 5542 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR0_0r(pc, SC_X1_SPEED_OVERRIDE0_OVERRIDE_0r_reg)); 5543 5544 SC_X1_SPD_OVRR0_1r_CLR(SC_X1_SPEED_OVERRIDE0_OVERRIDE_1r_reg); 5545 SC_X1_SPD_OVRR0_1r_DESCR_MODEf_SET(SC_X1_SPEED_OVERRIDE0_OVERRIDE_1r_reg, (pc->descr_mode)); 5546 5547 SC_X1_SPD_OVRR0_1r_DEC_TL_MODEf_SET(SC_X1_SPEED_OVERRIDE0_OVERRIDE_1r_reg, (pc->dec_tl_mode)); 5548 5549 SC_X1_SPD_OVRR0_1r_DESKEW_MODEf_SET(SC_X1_SPEED_OVERRIDE0_OVERRIDE_1r_reg, (pc->deskew_mode)); 5550 5551 SC_X1_SPD_OVRR0_1r_DEC_FSM_MODEf_SET(SC_X1_SPEED_OVERRIDE0_OVERRIDE_1r_reg, (pc->dec_fsm_mode)); 5552 5553 SC_X1_SPD_OVRR0_1r_BS_SM_SYNC_MODEf_SET(SC_X1_SPEED_OVERRIDE0_OVERRIDE_1r_reg, (pc->bs_sm_sync_mode)); 5554 5555 SC_X1_SPD_OVRR0_1r_BS_SYNC_ENf_SET(SC_X1_SPEED_OVERRIDE0_OVERRIDE_1r_reg, (pc->bs_sync_en)); 5556 5557 SC_X1_SPD_OVRR0_1r_BS_DIST_MODEf_SET(SC_X1_SPEED_OVERRIDE0_OVERRIDE_1r_reg, (pc->bs_dist_mode)); 5558 5559 SC_X1_SPD_OVRR0_1r_BS_BTMX_MODEf_SET(SC_X1_SPEED_OVERRIDE0_OVERRIDE_1r_reg, (pc->bs_btmx_mode)); 5560 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR0_1r(pc, SC_X1_SPEED_OVERRIDE0_OVERRIDE_1r_reg)); 5561 5562 SC_X1_SPD_OVRR0_2r_CLR(SC_X1_SPEED_OVERRIDE0_OVERRIDE_2r_reg); 5563 SC_X1_SPD_OVRR0_2r_CLOCKCNT0f_SET(SC_X1_SPEED_OVERRIDE0_OVERRIDE_2r_reg, (pc->clkcnt0)); 5564 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR0_2r(pc, SC_X1_SPEED_OVERRIDE0_OVERRIDE_2r_reg)); 5565 5566 SC_X1_SPD_OVRR0_3r_CLR(SC_X1_SPEED_OVERRIDE0_OVERRIDE_3r_reg); 5567 SC_X1_SPD_OVRR0_3r_CLOCKCNT1f_SET(SC_X1_SPEED_OVERRIDE0_OVERRIDE_3r_reg, (pc->clkcnt1)); 5568 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR0_3r(pc, SC_X1_SPEED_OVERRIDE0_OVERRIDE_3r_reg)); 5569 5570 SC_X1_SPD_OVRR0_4r_CLR(SC_X1_SPEED_OVERRIDE0_OVERRIDE_4r_reg); 5571 SC_X1_SPD_OVRR0_4r_LOOPCNT0f_SET(SC_X1_SPEED_OVERRIDE0_OVERRIDE_4r_reg, (pc->lpcnt0)); 5572 5573 SC_X1_SPD_OVRR0_4r_LOOPCNT1f_SET(SC_X1_SPEED_OVERRIDE0_OVERRIDE_4r_reg, (pc->lpcnt1)); 5574 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR0_4r(pc, SC_X1_SPEED_OVERRIDE0_OVERRIDE_4r_reg)); 5575 5576 SC_X1_SPD_OVRR0_5r_CLR(SC_X1_SPEED_OVERRIDE0_OVERRIDE_5r_reg); 5577 SC_X1_SPD_OVRR0_5r_MAC_CREDITGENCNTf_SET(SC_X1_SPEED_OVERRIDE0_OVERRIDE_5r_reg, (pc->cgc)); 5578 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR0_5r(pc, SC_X1_SPEED_OVERRIDE0_OVERRIDE_5r_reg)); 5579 5580 SC_X1_SPD_OVRR0_6r_CLR(SC_X1_SPD_OVRR0_6r_reg); 5581 SC_X1_SPD_OVRR0_6r_AM_SPACING_MULf_SET(SC_X1_SPD_OVRR0_6r_reg, pc->am_spacing_mul); 5582 SC_X1_SPD_OVRR0_6r_T_PMA_BITMUX_DELAYf_SET(SC_X1_SPD_OVRR0_6r_reg, pc->t_pma_btmx_delay); 5583 SC_X1_SPD_OVRR0_6r_T_PMA_WATERMARKf_SET(SC_X1_SPD_OVRR0_6r_reg, pc->t_pma_watermark); 5584 SC_X1_SPD_OVRR0_6r_T_PMA_CL91_MUX_SELf_SET(SC_X1_SPD_OVRR0_6r_reg, pc->t_pma_cl91_mux_sel); 5585 SC_X1_SPD_OVRR0_6r_T_FIVE_BIT_XOR_ENf_SET(SC_X1_SPD_OVRR0_6r_reg, pc->t_5bit_xor_en); 5586 SC_X1_SPD_OVRR0_6r_T_CL91_CW_SCRAMBLEf_SET(SC_X1_SPD_OVRR0_6r_reg, pc->t_cl91_cw_scr); 5587 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR0_6r(pc, SC_X1_SPD_OVRR0_6r_reg)); 5588 5589 } 5590 if (st_entry_num == 1) { 5591 SC_X1_SPD_OVRR1_SPDr_CLR(SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEEDr_reg); 5592 SC_X1_SPD_OVRR1_SPDr_SPEEDf_SET(SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEEDr_reg, st_entry_speed); 5593 5594 SC_X1_SPD_OVRR1_SPDr_NUM_LANESf_SET(SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEEDr_reg, (pc->num_lanes)); 5595 5596 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR1_SPDr(pc, SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEEDr_reg)); 5597 5598 5599 SC_X1_SPD_OVRR1_0r_CLR(SC_X1_SPEED_OVERRIDE1_OVERRIDE_0r_reg); 5600 SC_X1_SPD_OVRR1_0r_OS_MODEf_SET(SC_X1_SPEED_OVERRIDE1_OVERRIDE_0r_reg, (pc->os_mode)); 5601 5602 SC_X1_SPD_OVRR1_0r_SCR_MODEf_SET(SC_X1_SPEED_OVERRIDE1_OVERRIDE_0r_reg, (pc->scr_mode)); 5603 5604 SC_X1_SPD_OVRR1_0r_T_ENC_MODEf_SET(SC_X1_SPEED_OVERRIDE1_OVERRIDE_0r_reg, (pc->t_enc_mode)); 5605 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR1_0r(pc, SC_X1_SPEED_OVERRIDE1_OVERRIDE_0r_reg)); 5606 5607 SC_X1_SPD_OVRR1_0r_SCR_MODEf_SET(SC_X1_SPEED_OVERRIDE1_OVERRIDE_0r_reg, (pc->scr_mode)); 5608 5609 SC_X1_SPD_OVRR1_0r_T_ENC_MODEf_SET(SC_X1_SPEED_OVERRIDE1_OVERRIDE_0r_reg, (pc->t_enc_mode)); 5610 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR1_0r(pc, SC_X1_SPEED_OVERRIDE1_OVERRIDE_0r_reg)); 5611 5612 SC_X1_SPD_OVRR1_1r_CLR(SC_X1_SPEED_OVERRIDE1_OVERRIDE_1r_reg); 5613 SC_X1_SPD_OVRR1_1r_DESCR_MODEf_SET(SC_X1_SPEED_OVERRIDE1_OVERRIDE_1r_reg, (pc->descr_mode)); 5614 5615 SC_X1_SPD_OVRR1_1r_DEC_TL_MODEf_SET(SC_X1_SPEED_OVERRIDE1_OVERRIDE_1r_reg, (pc->dec_tl_mode)); 5616 5617 SC_X1_SPD_OVRR1_1r_DESKEW_MODEf_SET(SC_X1_SPEED_OVERRIDE1_OVERRIDE_1r_reg, (pc->deskew_mode)); 5618 5619 SC_X1_SPD_OVRR1_1r_DEC_FSM_MODEf_SET(SC_X1_SPEED_OVERRIDE1_OVERRIDE_1r_reg, (pc->dec_fsm_mode)); 5620 5621 #ifdef TSCF_GEN1 5622 SC_X1_SPD_OVRR1_1r_R_HG2_ENABLEf_SET(SC_X1_SPEED_OVERRIDE1_OVERRIDE_1r_reg, (pc->r_HG2_ENABLE)); 5623 #endif 5624 5625 SC_X1_SPD_OVRR1_1r_BS_SM_SYNC_MODEf_SET(SC_X1_SPEED_OVERRIDE1_OVERRIDE_1r_reg, (pc->bs_sm_sync_mode)); 5626 5627 SC_X1_SPD_OVRR1_1r_BS_SYNC_ENf_SET(SC_X1_SPEED_OVERRIDE1_OVERRIDE_1r_reg, (pc->bs_sync_en)); 5628 5629 SC_X1_SPD_OVRR1_1r_BS_DIST_MODEf_SET(SC_X1_SPEED_OVERRIDE1_OVERRIDE_1r_reg, (pc->bs_dist_mode)); 5630 5631 SC_X1_SPD_OVRR1_1r_BS_BTMX_MODEf_SET(SC_X1_SPEED_OVERRIDE1_OVERRIDE_1r_reg, (pc->bs_btmx_mode)); 5632 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR1_1r(pc, SC_X1_SPEED_OVERRIDE1_OVERRIDE_1r_reg)); 5633 5634 SC_X1_SPD_OVRR1_2r_CLR(SC_X1_SPEED_OVERRIDE1_OVERRIDE_2r_reg); 5635 SC_X1_SPD_OVRR1_2r_CLOCKCNT0f_SET(SC_X1_SPEED_OVERRIDE1_OVERRIDE_2r_reg, (pc->clkcnt0)); 5636 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR1_2r(pc, SC_X1_SPEED_OVERRIDE1_OVERRIDE_2r_reg)); 5637 5638 SC_X1_SPD_OVRR1_3r_CLR(SC_X1_SPEED_OVERRIDE1_OVERRIDE_3r_reg); 5639 SC_X1_SPD_OVRR1_3r_CLOCKCNT1f_SET(SC_X1_SPEED_OVERRIDE1_OVERRIDE_3r_reg, (pc->clkcnt1)); 5640 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR1_3r(pc, SC_X1_SPEED_OVERRIDE1_OVERRIDE_3r_reg)); 5641 5642 SC_X1_SPD_OVRR1_4r_CLR(SC_X1_SPEED_OVERRIDE1_OVERRIDE_4r_reg); 5643 SC_X1_SPD_OVRR1_4r_LOOPCNT0f_SET(SC_X1_SPEED_OVERRIDE1_OVERRIDE_4r_reg, (pc->lpcnt0)); 5644 5645 SC_X1_SPD_OVRR1_4r_LOOPCNT1f_SET(SC_X1_SPEED_OVERRIDE1_OVERRIDE_4r_reg, (pc->lpcnt1)); 5646 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR1_4r(pc, SC_X1_SPEED_OVERRIDE1_OVERRIDE_4r_reg)); 5647 5648 SC_X1_SPD_OVRR1_5r_CLR(SC_X1_SPEED_OVERRIDE1_OVERRIDE_5r_reg); 5649 SC_X1_SPD_OVRR1_5r_MAC_CREDITGENCNTf_SET(SC_X1_SPEED_OVERRIDE1_OVERRIDE_5r_reg, (pc->cgc)); 5650 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR1_5r(pc, SC_X1_SPEED_OVERRIDE1_OVERRIDE_5r_reg)); 5651 5652 SC_X1_SPD_OVRR1_6r_CLR(SC_X1_SPD_OVRR1_6r_reg); 5653 SC_X1_SPD_OVRR1_6r_AM_SPACING_MULf_SET(SC_X1_SPD_OVRR1_6r_reg, pc->am_spacing_mul); 5654 SC_X1_SPD_OVRR1_6r_T_PMA_BITMUX_DELAYf_SET(SC_X1_SPD_OVRR1_6r_reg, pc->t_pma_btmx_delay); 5655 SC_X1_SPD_OVRR1_6r_T_PMA_WATERMARKf_SET(SC_X1_SPD_OVRR1_6r_reg, pc->t_pma_watermark); 5656 SC_X1_SPD_OVRR1_6r_T_PMA_CL91_MUX_SELf_SET(SC_X1_SPD_OVRR1_6r_reg, pc->t_pma_cl91_mux_sel); 5657 SC_X1_SPD_OVRR1_6r_T_FIVE_BIT_XOR_ENf_SET(SC_X1_SPD_OVRR1_6r_reg, pc->t_5bit_xor_en); 5658 SC_X1_SPD_OVRR1_6r_T_CL91_CW_SCRAMBLEf_SET(SC_X1_SPD_OVRR1_6r_reg, pc->t_cl91_cw_scr); 5659 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR1_6r(pc, SC_X1_SPD_OVRR1_6r_reg)); 5660 5661 } 5662 if (st_entry_num == 2) { 5663 SC_X1_SPD_OVRR2_SPDr_CLR(SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEEDr_reg); 5664 SC_X1_SPD_OVRR2_SPDr_SPEEDf_SET(SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEEDr_reg, st_entry_speed); 5665 5666 SC_X1_SPD_OVRR2_SPDr_NUM_LANESf_SET(SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEEDr_reg, (pc->num_lanes)); 5667 5668 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR2_SPDr(pc, SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEEDr_reg)); 5669 5670 SC_X1_SPD_OVRR2_0r_CLR(SC_X1_SPEED_OVERRIDE2_OVERRIDE_0r_reg); 5671 SC_X1_SPD_OVRR2_0r_CL72_ENf_SET(SC_X1_SPEED_OVERRIDE2_OVERRIDE_0r_reg, pc->cl72_en); 5672 SC_X1_SPD_OVRR2_0r_OS_MODEf_SET(SC_X1_SPEED_OVERRIDE2_OVERRIDE_0r_reg, pc->os_mode); 5673 SC_X1_SPD_OVRR2_0r_T_FIFO_MODEf_SET(SC_X1_SPEED_OVERRIDE2_OVERRIDE_0r_reg, pc->t_fifo_mode); 5674 SC_X1_SPD_OVRR2_0r_T_ENC_MODEf_SET(SC_X1_SPEED_OVERRIDE2_OVERRIDE_0r_reg, pc->t_enc_mode); 5675 SC_X1_SPD_OVRR2_0r_T_HG2_ENABLEf_SET(SC_X1_SPEED_OVERRIDE2_OVERRIDE_0r_reg, pc->t_HG2_ENABLE); 5676 SC_X1_SPD_OVRR2_0r_T_PMA_BTMX_MODEf_SET(SC_X1_SPEED_OVERRIDE2_OVERRIDE_0r_reg, pc->t_pma_btmx_mode); 5677 SC_X1_SPD_OVRR2_0r_SCR_MODEf_SET(SC_X1_SPEED_OVERRIDE2_OVERRIDE_0r_reg, pc->scr_mode); 5678 5679 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR2_0r(pc, SC_X1_SPEED_OVERRIDE2_OVERRIDE_0r_reg)); 5680 5681 5682 SC_X1_SPD_OVRR2_1r_CLR(SC_X1_SPEED_OVERRIDE2_OVERRIDE_1r_reg); 5683 SC_X1_SPD_OVRR2_1r_DESCR_MODEf_SET(SC_X1_SPEED_OVERRIDE2_OVERRIDE_1r_reg, (pc->descr_mode)); 5684 5685 SC_X1_SPD_OVRR2_1r_DEC_TL_MODEf_SET(SC_X1_SPEED_OVERRIDE2_OVERRIDE_1r_reg, (pc->dec_tl_mode)); 5686 5687 SC_X1_SPD_OVRR2_1r_DESKEW_MODEf_SET(SC_X1_SPEED_OVERRIDE2_OVERRIDE_1r_reg, (pc->deskew_mode)); 5688 5689 SC_X1_SPD_OVRR2_1r_DEC_FSM_MODEf_SET(SC_X1_SPEED_OVERRIDE2_OVERRIDE_1r_reg, (pc->dec_fsm_mode)); 5690 5691 #ifdef TSCF_GEN1 5692 SC_X1_SPD_OVRR2_1r_R_HG2_ENABLEf_SET(SC_X1_SPEED_OVERRIDE2_OVERRIDE_1r_reg, (pc->r_HG2_ENABLE)); 5693 #endif 5694 5695 SC_X1_SPD_OVRR2_1r_BS_SM_SYNC_MODEf_SET(SC_X1_SPEED_OVERRIDE2_OVERRIDE_1r_reg, (pc->bs_sm_sync_mode)); 5696 5697 SC_X1_SPD_OVRR2_1r_BS_SYNC_ENf_SET(SC_X1_SPEED_OVERRIDE2_OVERRIDE_1r_reg, (pc->bs_sync_en)); 5698 5699 SC_X1_SPD_OVRR2_1r_BS_DIST_MODEf_SET(SC_X1_SPEED_OVERRIDE2_OVERRIDE_1r_reg, (pc->bs_dist_mode)); 5700 5701 SC_X1_SPD_OVRR2_1r_BS_BTMX_MODEf_SET(SC_X1_SPEED_OVERRIDE2_OVERRIDE_1r_reg, (pc->bs_btmx_mode)); 5702 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR2_1r(pc, SC_X1_SPEED_OVERRIDE2_OVERRIDE_1r_reg)); 5703 5704 SC_X1_SPD_OVRR2_2r_CLR(SC_X1_SPEED_OVERRIDE2_OVERRIDE_2r_reg); 5705 SC_X1_SPD_OVRR2_2r_CLOCKCNT0f_SET(SC_X1_SPEED_OVERRIDE2_OVERRIDE_2r_reg, (pc->clkcnt0)); 5706 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR2_2r(pc, SC_X1_SPEED_OVERRIDE2_OVERRIDE_2r_reg)); 5707 5708 SC_X1_SPD_OVRR2_3r_CLR(SC_X1_SPEED_OVERRIDE2_OVERRIDE_3r_reg); 5709 SC_X1_SPD_OVRR2_3r_CLOCKCNT1f_SET(SC_X1_SPEED_OVERRIDE2_OVERRIDE_3r_reg, (pc->clkcnt1)); 5710 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR2_3r(pc, SC_X1_SPEED_OVERRIDE2_OVERRIDE_3r_reg)); 5711 5712 SC_X1_SPD_OVRR2_4r_CLR(SC_X1_SPEED_OVERRIDE2_OVERRIDE_4r_reg); 5713 SC_X1_SPD_OVRR2_4r_LOOPCNT0f_SET(SC_X1_SPEED_OVERRIDE2_OVERRIDE_4r_reg, (pc->lpcnt0)); 5714 5715 SC_X1_SPD_OVRR2_4r_LOOPCNT1f_SET(SC_X1_SPEED_OVERRIDE2_OVERRIDE_4r_reg, (pc->lpcnt1)); 5716 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR2_4r(pc, SC_X1_SPEED_OVERRIDE2_OVERRIDE_4r_reg)); 5717 5718 SC_X1_SPD_OVRR2_5r_CLR(SC_X1_SPEED_OVERRIDE2_OVERRIDE_5r_reg); 5719 SC_X1_SPD_OVRR2_5r_MAC_CREDITGENCNTf_SET(SC_X1_SPEED_OVERRIDE2_OVERRIDE_5r_reg, (pc->cgc)); 5720 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR2_5r(pc, SC_X1_SPEED_OVERRIDE2_OVERRIDE_5r_reg)); 5721 5722 SC_X1_SPD_OVRR2_6r_CLR(SC_X1_SPD_OVRR2_6r_reg); 5723 SC_X1_SPD_OVRR2_6r_AM_SPACING_MULf_SET(SC_X1_SPD_OVRR2_6r_reg, pc->am_spacing_mul); 5724 SC_X1_SPD_OVRR2_6r_T_PMA_BITMUX_DELAYf_SET(SC_X1_SPD_OVRR2_6r_reg, pc->t_pma_btmx_delay); 5725 SC_X1_SPD_OVRR2_6r_T_PMA_WATERMARKf_SET(SC_X1_SPD_OVRR2_6r_reg, pc->t_pma_watermark); 5726 SC_X1_SPD_OVRR2_6r_T_PMA_CL91_MUX_SELf_SET(SC_X1_SPD_OVRR2_6r_reg, pc->t_pma_cl91_mux_sel); 5727 SC_X1_SPD_OVRR2_6r_T_FIVE_BIT_XOR_ENf_SET(SC_X1_SPD_OVRR2_6r_reg, pc->t_5bit_xor_en); 5728 SC_X1_SPD_OVRR2_6r_T_CL91_CW_SCRAMBLEf_SET(SC_X1_SPD_OVRR2_6r_reg, pc->t_cl91_cw_scr); 5729 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR2_6r(pc, SC_X1_SPD_OVRR2_6r_reg)); 5730 5731 } 5732 if (st_entry_num == 3) { 5733 SC_X1_SPD_OVRR3_SPDr_CLR(SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEEDr_reg); 5734 SC_X1_SPD_OVRR3_SPDr_SPEEDf_SET(SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEEDr_reg, st_entry_speed); 5735 5736 SC_X1_SPD_OVRR3_SPDr_NUM_LANESf_SET(SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEEDr_reg, (pc->num_lanes)); 5737 5738 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR3_SPDr(pc, SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEEDr_reg)); 5739 5740 SC_X1_SPD_OVRR3_0r_CLR(SC_X1_SPEED_OVERRIDE3_OVERRIDE_0r_reg); 5741 SC_X1_SPD_OVRR3_0r_CL72_ENf_SET(SC_X1_SPEED_OVERRIDE3_OVERRIDE_0r_reg, pc->cl72_en); 5742 SC_X1_SPD_OVRR3_0r_OS_MODEf_SET(SC_X1_SPEED_OVERRIDE3_OVERRIDE_0r_reg, pc->os_mode); 5743 SC_X1_SPD_OVRR3_0r_T_FIFO_MODEf_SET(SC_X1_SPEED_OVERRIDE3_OVERRIDE_0r_reg, pc->t_fifo_mode); 5744 SC_X1_SPD_OVRR3_0r_T_ENC_MODEf_SET(SC_X1_SPEED_OVERRIDE3_OVERRIDE_0r_reg, pc->t_enc_mode); 5745 SC_X1_SPD_OVRR3_0r_T_HG2_ENABLEf_SET(SC_X1_SPEED_OVERRIDE3_OVERRIDE_0r_reg, pc->t_HG2_ENABLE); 5746 SC_X1_SPD_OVRR3_0r_T_PMA_BTMX_MODEf_SET(SC_X1_SPEED_OVERRIDE3_OVERRIDE_0r_reg, pc->t_pma_btmx_mode); 5747 SC_X1_SPD_OVRR3_0r_SCR_MODEf_SET(SC_X1_SPEED_OVERRIDE3_OVERRIDE_0r_reg, pc->scr_mode); 5748 5749 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR3_0r(pc, SC_X1_SPEED_OVERRIDE3_OVERRIDE_0r_reg)); 5750 5751 5752 SC_X1_SPD_OVRR3_1r_CLR(SC_X1_SPEED_OVERRIDE3_OVERRIDE_1r_reg); 5753 SC_X1_SPD_OVRR3_1r_DESCR_MODEf_SET(SC_X1_SPEED_OVERRIDE3_OVERRIDE_1r_reg, (pc->descr_mode)); 5754 5755 SC_X1_SPD_OVRR3_1r_DEC_TL_MODEf_SET(SC_X1_SPEED_OVERRIDE3_OVERRIDE_1r_reg, (pc->dec_tl_mode)); 5756 5757 SC_X1_SPD_OVRR3_1r_DESKEW_MODEf_SET(SC_X1_SPEED_OVERRIDE3_OVERRIDE_1r_reg, (pc->deskew_mode)); 5758 5759 SC_X1_SPD_OVRR3_1r_DEC_FSM_MODEf_SET(SC_X1_SPEED_OVERRIDE3_OVERRIDE_1r_reg, (pc->dec_fsm_mode)); 5760 5761 #ifdef TSCF_GEN1 5762 SC_X1_SPD_OVRR3_1r_R_HG2_ENABLEf_SET(SC_X1_SPEED_OVERRIDE3_OVERRIDE_1r_reg, (pc->r_HG2_ENABLE)); 5763 #endif 5764 5765 SC_X1_SPD_OVRR3_1r_BS_SM_SYNC_MODEf_SET(SC_X1_SPEED_OVERRIDE3_OVERRIDE_1r_reg, (pc->bs_sm_sync_mode)); 5766 5767 SC_X1_SPD_OVRR3_1r_BS_SYNC_ENf_SET(SC_X1_SPEED_OVERRIDE3_OVERRIDE_1r_reg, (pc->bs_sync_en)); 5768 5769 SC_X1_SPD_OVRR3_1r_BS_DIST_MODEf_SET(SC_X1_SPEED_OVERRIDE3_OVERRIDE_1r_reg, (pc->bs_dist_mode)); 5770 5771 SC_X1_SPD_OVRR3_1r_BS_BTMX_MODEf_SET(SC_X1_SPEED_OVERRIDE3_OVERRIDE_1r_reg, (pc->bs_btmx_mode)); 5772 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR3_1r(pc, SC_X1_SPEED_OVERRIDE3_OVERRIDE_1r_reg)); 5773 5774 SC_X1_SPD_OVRR3_2r_CLR(SC_X1_SPEED_OVERRIDE3_OVERRIDE_2r_reg); 5775 SC_X1_SPD_OVRR3_2r_CLOCKCNT0f_SET(SC_X1_SPEED_OVERRIDE3_OVERRIDE_2r_reg, (pc->clkcnt0)); 5776 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR3_2r(pc, SC_X1_SPEED_OVERRIDE3_OVERRIDE_2r_reg)); 5777 5778 SC_X1_SPD_OVRR3_3r_CLR(SC_X1_SPEED_OVERRIDE3_OVERRIDE_3r_reg); 5779 SC_X1_SPD_OVRR3_3r_CLOCKCNT1f_SET(SC_X1_SPEED_OVERRIDE3_OVERRIDE_3r_reg, (pc->clkcnt1)); 5780 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR3_3r(pc, SC_X1_SPEED_OVERRIDE3_OVERRIDE_3r_reg)); 5781 5782 SC_X1_SPD_OVRR3_4r_CLR(SC_X1_SPEED_OVERRIDE3_OVERRIDE_4r_reg); 5783 SC_X1_SPD_OVRR3_4r_LOOPCNT0f_SET(SC_X1_SPEED_OVERRIDE3_OVERRIDE_4r_reg, (pc->lpcnt0)); 5784 5785 SC_X1_SPD_OVRR3_4r_LOOPCNT1f_SET(SC_X1_SPEED_OVERRIDE3_OVERRIDE_4r_reg, (pc->lpcnt1)); 5786 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR3_4r(pc, SC_X1_SPEED_OVERRIDE3_OVERRIDE_4r_reg)); 5787 5788 SC_X1_SPD_OVRR3_5r_CLR(SC_X1_SPEED_OVERRIDE3_OVERRIDE_5r_reg); 5789 SC_X1_SPD_OVRR3_5r_MAC_CREDITGENCNTf_SET(SC_X1_SPEED_OVERRIDE3_OVERRIDE_5r_reg, (pc->cgc)); 5790 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR3_5r(pc, SC_X1_SPEED_OVERRIDE3_OVERRIDE_5r_reg)); 5791 5792 SC_X1_SPD_OVRR3_6r_CLR(SC_X1_SPD_OVRR3_6r_reg); 5793 SC_X1_SPD_OVRR3_6r_AM_SPACING_MULf_SET(SC_X1_SPD_OVRR3_6r_reg, pc->am_spacing_mul); 5794 SC_X1_SPD_OVRR3_6r_T_PMA_BITMUX_DELAYf_SET(SC_X1_SPD_OVRR3_6r_reg, pc->t_pma_btmx_delay); 5795 SC_X1_SPD_OVRR3_6r_T_PMA_WATERMARKf_SET(SC_X1_SPD_OVRR3_6r_reg, pc->t_pma_watermark); 5796 SC_X1_SPD_OVRR3_6r_T_PMA_CL91_MUX_SELf_SET(SC_X1_SPD_OVRR3_6r_reg, pc->t_pma_cl91_mux_sel); 5797 SC_X1_SPD_OVRR3_6r_T_FIVE_BIT_XOR_ENf_SET(SC_X1_SPD_OVRR3_6r_reg, pc->t_5bit_xor_en); 5798 SC_X1_SPD_OVRR3_6r_T_CL91_CW_SCRAMBLEf_SET(SC_X1_SPD_OVRR3_6r_reg, pc->t_cl91_cw_scr); 5799 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR3_6r(pc, SC_X1_SPD_OVRR3_6r_reg)); 5800 5801 } 5802 return PHYMOD_E_NONE; 5803 } 5804 #endif 5805 5806 #ifdef _DV_TB_ 5807 /*! 5808 @brief override soft table entry speed in AN mode 5809 @param pc handle to current TSCF context (#PHYMOD_ST) 5810 @returns The value PHYMOD_E_NONE upon successful completion. 5811 @details 5812 This is a tier2 function, it is called from init_pcs_an 5813 For instance, if a speed is resolved to 10G, but using Softtable entry 5814 if user likes to override to 20G XFI, the individual fields below are 5815 updated in pc for comparison and the configure_st_entry is called 5816 configure_st_entry func does the actual overriding 5817 returns The value PHYMOD_E_NONE upon successful completion. 5818 */ 5819 5820 int tefmod16_set_an_override(PHYMOD_ST* pc) 5821 { 5822 TEFMOD16_DBG_IN_FUNC_INFO(pc); 5823 5824 5825 5826 /* override_speed */ 5827 pc->speed= 64; /*100G CR4*/ 5828 pc->num_lanes = NUM_LANES_04; 5829 pc->cl36rx_en = 0; 5830 pc->cl36tx_en = 0; 5831 pc->t_pma_40b_mode = 0; 5832 5833 /* override_0 */ 5834 pc->cl72_en=1; 5835 pc->os_mode = OS_MODE_1; 5836 pc->t_fifo_mode=T_FIFO_MODE_100G; 5837 pc->t_enc_mode=T_ENC_MODE_CL82; 5838 pc->t_HG2_ENABLE=0; 5839 pc->t_pma_btmx_mode=T_PMA_BITMUX_MODE_5to1; 5840 pc->scr_mode=T_SCR_MODE_100G; 5841 5842 /* override_1 */ 5843 pc->descr_mode=R_DESCR_MODE_CL82; 5844 pc->dec_tl_mode=R_DEC_TL_MODE_CL82; 5845 pc->deskew_mode=R_DESKEW_MODE_100G; 5846 pc->dec_fsm_mode=R_DEC_FSM_MODE_CL82; 5847 pc->bs_sm_sync_mode=BS_CL82_SYNC_MODE; 5848 pc->bs_sync_en=1; 5849 pc->bs_dist_mode=BS_DIST_MODE_NO_TDM; 5850 pc->bs_btmx_mode=BS_BTMX_MODE_5to1; 5851 5852 5853 5854 /* override_2 */ 5855 pc->clkcnt0 = 9; 5856 5857 /* override_3 */ 5858 pc->clkcnt1 = 5; 5859 5860 /* override_4 */ 5861 pc->lpcnt0 = 1; 5862 pc->lpcnt1 = 18; 5863 5864 /* override_5 */ 5865 pc->cgc = 1; 5866 5867 /* override_6 */ 5868 pc->am_spacing_mul = 3; 5869 pc->t_pma_btmx_delay = 1; 5870 pc->t_pma_watermark = 7; 5871 pc->t_pma_cl91_mux_sel = 0; 5872 pc->t_5bit_xor_en = 0; 5873 pc->t_cl91_cw_scr = 0; 5874 5875 5876 /* override_7 */ 5877 pc->r_HG2_ENABLE=0; 5878 pc->r_tc_out_mode = 0; 5879 pc->r_5bit_xor_en = 0; 5880 pc->r_tc_mode = 0; 5881 pc->r_tc_in_mode = 0; 5882 pc->r_cl91_cw_scr = 0; 5883 pc->r_merge_mode = 0; 5884 pc->cl91_blksync_mode = 0; 5885 configure_st_entry(0, pc->speed, pc); 5886 5887 /*100G KR4 */ 5888 pc->speed= 65; 5889 configure_st_entry(2, pc->speed, pc); 5890 5891 /*100G CR4 HG2*/ 5892 pc->speed=68; 5893 pc->t_HG2_ENABLE=1; 5894 pc->r_HG2_ENABLE=1; 5895 configure_st_entry(1, pc->speed, pc); 5896 5897 /*100G KR4 HG2*/ 5898 pc->speed= 69; 5899 configure_st_entry(3, pc->speed, pc); 5900 5901 5902 return PHYMOD_E_NONE; 5903 } 5904 #endif 5905 5906 5907 #ifdef _DV_TB_ 5908 /*! 5909 @brief tefmod16_init_pcs_an , program PCS for AN 5910 @returns The value PHYMOD_E_NONE upon successful completion. 5911 @details 5912 If any override option switch is selected, it will call tier2 tefmod16_set_an_override 5913 This is a tier2 function, whenever something from Hard table needs to be overwritten 5914 calls the other autoneg routines to perform AN. 5915 Sets AN port mode 5916 Controls the setting/resetting of autoneg advertisement registers. 5917 tefmod16_autoneg_control starts the AN 5918 */ 5919 int tefmod16_init_pcs_an(PHYMOD_ST* pc) 5920 { 5921 TEFMOD16_DBG_IN_FUNC_INFO(pc); 5922 if(pc->sc_mode == TEFMOD16_SC_MODE_AN_CL73) { 5923 tefmod16_set_an_override(pc); 5924 } 5925 tefmod16_set_an_port_mode(pc); 5926 tefmod16_autoneg_set(pc); 5927 tefmod16_autoneg_control(pc); 5928 return PHYMOD_E_NONE; 5929 } 5930 #endif 5931 5932 #ifdef _DV_TB_ 5933 /*! 5934 @brief tefmod16_set_sc_speed , sets the required speed , 5935 @returns The value PHYMOD_E_NONE upon successful completion. 5936 @details 5937 After the resets, speed_ctrl regs are programmed(as per Ankits new init seq), fills up the lookup table by 5938 Updating the expected value 5939 */ 5940 int tefmod16_set_sc_speed(PHYMOD_ST* pc) /* SET_SC_SPEED */ 5941 { 5942 int mapped_speed; 5943 SC_X4_CTLr_t SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg; 5944 TX_X4_ENC0r_t TX_X4_ENC0r_reg; 5945 RX_X4_PCS_CTL0r_t RX_X4_PCS_CTL0r_reg; 5946 5947 5948 TEFMOD16_DBG_IN_FUNC_INFO(pc); 5949 /* write 0 to the speed change */ 5950 SC_X4_CTLr_CLR(SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg); 5951 PHYMOD_IF_ERR_RETURN(READ_SC_X4_CTLr(pc, &SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg)); 5952 5953 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg, 0); 5954 PHYMOD_IF_ERR_RETURN(WRITE_SC_X4_CTLr(pc, SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg)); 5955 5956 /* Set speed and write 1 */ 5957 SC_X4_CTLr_CLR(SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg); 5958 5959 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg, 1); 5960 tefmod16_get_mapped_speed(pc->spd_intf, &mapped_speed); 5961 if(pc->sc_mode == TEFMOD16_SC_MODE_HT_OVERRIDE || pc->sc_mode == TEFMOD_SC_MODE_ST_OVERRIDE) { mapped_speed = 2; 5962 } 5963 SC_X4_CTLr_SPEEDf_SET(SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg, mapped_speed); 5964 PHYMOD_IF_ERR_RETURN(WRITE_SC_X4_CTLr(pc, SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg)); 5965 5966 /* Update the speed */ 5967 pc->speed= mapped_speed; 5968 5969 /* Do lookup here */ 5970 tefmod16_fill_lkup_exp(pc); 5971 5972 return PHYMOD_E_NONE; 5973 } 5974 #endif 5975 5976 #ifdef _DV_TB_ 5977 /*! 5978 @brief tefmod16_init_pcs_fs , program PCS for Forced speed mode 5979 @returns The value PHYMOD_E_NONE upon successful completion. 5980 @details 5981 If any SW override option switch is selected, it will call tier2 which for eg will convert from 10G to 20G XFI 5982 Using HT, we do overrides of HT entries for eg will convert from 10G to 40G MLD 5983 If none of the override options are selected, we just program the SC table 5984 */ 5985 5986 int tefmod16_init_pcs_fs(PHYMOD_ST* pc) 5987 { 5988 int or_value; 5989 int st_entry; 5990 int speed_entry; 5991 SC_X4_FLD_OVRR_EN0_TYPEr_t SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg; 5992 SC_X4_FLD_OVRR_EN1_TYPEr_t SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg; 5993 SC_X4_SC_X4_OVRRr_t SC_X4_SC_X4_OVRRr_reg; 5994 TX_X2_CL82_0r_t TX_X2_CONTROL0_CL82_0r_reg; 5995 TX_X4_ENC0r_t TX_X4_CONTROL0_ENCODE_0r_reg; 5996 TX_X4_MISCr_t TX_X4_CONTROL0_MISCr_reg; 5997 RX_X4_PCS_CTL0r_t RX_X4_CONTROL0_PCS_CONTROL_0r_reg; 5998 RX_X4_BLKSYNC_CFGr_t RX_X4_CONTROL0_BLKSYNC_CONFIGr_reg; 5999 TX_X4_LOOPCNTr_t TX_X4_CREDIT0_LOOPCNTr_reg; 6000 TX_X4_CRED1r_t TX_X4_CREDIT0_CREDIT1r_reg; 6001 TX_X4_MAC_CREDGENCNTr_t TX_X4_CREDIT0_MAC_CREDITGENCNTr_reg; 6002 SC_X4_FLD_OVRR_EN2_TYPEr_t SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE2_TYPEr_reg; 6003 6004 TEFMOD16_DBG_IN_FUNC_INFO(pc); 6005 if(pc->sc_mode == TEFMOD16_SC_MODE_ST_OVERRIDE) { 6006 6007 /*Set the override enable*/ 6008 /*override from 10G XFI to 20G XFI */ 6009 configure_st_entry(pc->sw_table_entry, pc->speed, pc); 6010 } 6011 6012 if(pc->fc_mode) { 6013 /*write to address c062 and c133 Temp fix for override*/ 6014 6015 printf("PER_FIELD_OR is %x\n", pc->per_field_override_en); 6016 /*Set the override enable*/ 6017 6018 if(pc->per_field_override_en == 0x88000001) { 6019 SC_X4_FLD_OVRR_EN2_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE2_TYPEr_reg); 6020 SC_X4_FLD_OVRR_EN2_TYPEr_R_CL91_CW_SCRAMBLE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE2_TYPEr_reg, 1); 6021 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN2_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE2_TYPEr_reg)); 6022 6023 RX_X4_CL91_RX_CTL0r_CLR(RX_X4_CL91_RX_CTL0r_reg); 6024 RX_X4_CL91_RX_CTL0r_CL91_CW_SCRAMBLEf_SET(RX_X4_CL91_RX_CTL0r_reg, 0); 6025 PHYMOD_IF_ERR_RETURN(MODIFY_RX_X4_CL91_RX_CTL0r(pc, RX_X4_CL91_RX_CTL0r_reg)); 6026 6027 SC_X4_FLD_OVRR_EN2_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE2_TYPEr_reg); 6028 SC_X4_FLD_OVRR_EN2_TYPEr_R_FIVE_BIT_XOR_EN_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE2_TYPEr_reg, 1); 6029 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN2_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE2_TYPEr_reg)); 6030 6031 RX_X4_CL91_RX_CTL0r_CLR(RX_X4_CL91_RX_CTL0r_reg); 6032 RX_X4_CL91_RX_CTL0r_FIVE_BIT_XOR_ENf_SET(RX_X4_CL91_RX_CTL0r_reg, 1); 6033 PHYMOD_IF_ERR_RETURN(MODIFY_RX_X4_CL91_RX_CTL0r(pc, RX_X4_CL91_RX_CTL0r_reg)); 6034 } 6035 } 6036 6037 if(pc->sc_mode == TEFMOD16_SC_MODE_HT_OVERRIDE) { 6038 6039 /*override from 10G XFI to 40G MLD */ 6040 6041 SC_X4_SC_X4_OVRRr_CLR(SC_X4_SC_X4_OVRRr_reg); 6042 SC_X4_SC_X4_OVRRr_NUM_LANES_OVERRIDE_VALUEf_SET( SC_X4_SC_X4_OVRRr_reg, 0); 6043 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_SC_X4_OVRRr(pc, SC_X4_SC_X4_OVRRr_reg)); 6044 6045 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 6046 SC_X4_FLD_OVRR_EN0_TYPEr_NUM_LANES_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 1); 6047 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 6048 6049 /*write t_fifo_mode */ 6050 or_value = 1; 6051 6052 TX_X2_CL82_0r_CLR(TX_X2_CONTROL0_CL82_0r_reg); 6053 TX_X4_ENC0r_CLR(TX_X4_CONTROL0_ENCODE_0r_reg); 6054 TX_X4_ENC0r_T_FIFO_MODEf_SET(TX_X4_CONTROL0_ENCODE_0r_reg, or_value); 6055 6056 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X2_CL82_0r(pc, TX_X2_CONTROL0_CL82_0r_reg)); 6057 6058 /*Set the override enable*/ 6059 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 6060 SC_X4_FLD_OVRR_EN0_TYPEr_T_FIFO_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 1); 6061 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 6062 6063 /*write t_enc_mode */ 6064 or_value = 2; 6065 TX_X4_ENC0r_CLR(TX_X4_CONTROL0_ENCODE_0r_reg); 6066 TX_X4_ENC0r_T_ENC_MODEf_SET(TX_X4_CONTROL0_ENCODE_0r_reg, or_value); 6067 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_ENC0r(pc, TX_X4_CONTROL0_ENCODE_0r_reg)); 6068 6069 /*Set the override enable*/ 6070 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 6071 SC_X4_FLD_OVRR_EN0_TYPEr_T_ENC_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 1); 6072 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 6073 6074 6075 /* scrambler mode*/ 6076 or_value = 5; 6077 TX_X4_MISCr_CLR(TX_X4_CONTROL0_MISCr_reg); 6078 TX_X4_MISCr_SCR_MODEf_SET(TX_X4_CONTROL0_MISCr_reg, or_value); 6079 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_MISCr(pc, TX_X4_CONTROL0_MISCr_reg)); 6080 6081 /*Set the override enable*/ 6082 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 6083 SC_X4_FLD_OVRR_EN0_TYPEr_SCR_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 1); 6084 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 6085 6086 /*descrambler mode*/ 6087 or_value = 2; 6088 RX_X4_PCS_CTL0r_CLR(RX_X4_CONTROL0_PCS_CONTROL_0r_reg); 6089 RX_X4_PCS_CTL0r_DESCR_MODEf_SET(RX_X4_CONTROL0_PCS_CONTROL_0r_reg, or_value); 6090 PHYMOD_IF_ERR_RETURN(MODIFY_RX_X4_PCS_CTL0r(pc, RX_X4_CONTROL0_PCS_CONTROL_0r_reg)); 6091 6092 /*Set the override enable*/ 6093 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 6094 SC_X4_FLD_OVRR_EN0_TYPEr_DESCR_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 1); 6095 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 6096 6097 /*dec_tl_mode*/ 6098 or_value = 2; 6099 RX_X4_PCS_CTL0r_CLR(RX_X4_CONTROL0_PCS_CONTROL_0r_reg); 6100 RX_X4_PCS_CTL0r_DEC_TL_MODEf_SET(RX_X4_CONTROL0_PCS_CONTROL_0r_reg, or_value); 6101 PHYMOD_IF_ERR_RETURN(MODIFY_RX_X4_PCS_CTL0r(pc, RX_X4_CONTROL0_PCS_CONTROL_0r_reg)); 6102 6103 /*Set the override enable*/ 6104 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 6105 SC_X4_FLD_OVRR_EN0_TYPEr_DEC_TL_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 1); 6106 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 6107 6108 /*desjkew_mode*/ 6109 or_value = 2; 6110 RX_X4_PCS_CTL0r_CLR(RX_X4_CONTROL0_PCS_CONTROL_0r_reg); 6111 RX_X4_PCS_CTL0r_DESKEW_MODEf_SET(RX_X4_CONTROL0_PCS_CONTROL_0r_reg, or_value); 6112 PHYMOD_IF_ERR_RETURN(MODIFY_RX_X4_PCS_CTL0r(pc, RX_X4_CONTROL0_PCS_CONTROL_0r_reg)); 6113 /*Set the override enable*/ 6114 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 6115 SC_X4_FLD_OVRR_EN0_TYPEr_DESKEW_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 1); 6116 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 6117 6118 /*dec_fsm_mode*/ 6119 /*Set the override enable*/ 6120 or_value = 2; 6121 RX_X4_PCS_CTL0r_CLR(RX_X4_CONTROL0_PCS_CONTROL_0r_reg); 6122 RX_X4_PCS_CTL0r_DEC_FSM_MODEf_SET(RX_X4_CONTROL0_PCS_CONTROL_0r_reg, or_value); 6123 PHYMOD_IF_ERR_RETURN(MODIFY_RX_X4_PCS_CTL0r(pc, RX_X4_CONTROL0_PCS_CONTROL_0r_reg)); 6124 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 6125 SC_X4_FLD_OVRR_EN0_TYPEr_DEC_FSM_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 1); 6126 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 6127 6128 /*bs_sm_sync_mode*/ 6129 /*Set the override enable*/ 6130 or_value = 0; 6131 RX_X4_BLKSYNC_CFGr_CLR(RX_X4_CONTROL0_BLKSYNC_CONFIGr_reg); 6132 RX_X4_BLKSYNC_CFGr_BS_SM_SYNC_MODEf_SET(RX_X4_CONTROL0_BLKSYNC_CONFIGr_reg, or_value); 6133 PHYMOD_IF_ERR_RETURN(MODIFY_RX_X4_BLKSYNC_CFGr(pc, RX_X4_CONTROL0_BLKSYNC_CONFIGr_reg)); 6134 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg); 6135 SC_X4_FLD_OVRR_EN1_TYPEr_BS_SM_SYNC_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg, 1); 6136 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg)); 6137 6138 /*bs_dist_mode*/ 6139 /*Set the override enable*/ 6140 or_value = 2; 6141 RX_X4_BLKSYNC_CFGr_CLR(RX_X4_CONTROL0_BLKSYNC_CONFIGr_reg); 6142 RX_X4_BLKSYNC_CFGr_BS_DIST_MODEf_SET(RX_X4_CONTROL0_BLKSYNC_CONFIGr_reg, or_value); 6143 PHYMOD_IF_ERR_RETURN(MODIFY_RX_X4_BLKSYNC_CFGr(pc, RX_X4_CONTROL0_BLKSYNC_CONFIGr_reg)); 6144 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg); 6145 SC_X4_FLD_OVRR_EN1_TYPEr_BS_DIST_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg, 1); 6146 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg)); 6147 6148 /* Program resets and credits */ 6149 /*Set the override enable*/ 6150 or_value = 18; 6151 TX_X4_LOOPCNTr_CLR(TX_X4_CREDIT0_LOOPCNTr_reg); 6152 TX_X4_LOOPCNTr_LOOPCNT1f_SET(TX_X4_CREDIT0_LOOPCNTr_reg, or_value); 6153 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_LOOPCNTr(pc, TX_X4_CREDIT0_LOOPCNTr_reg)); 6154 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg); 6155 SC_X4_FLD_OVRR_EN1_TYPEr_LOOPCNT1_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg, 1); 6156 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg)); 6157 6158 or_value = 5; 6159 TX_X4_CRED1r_CLR(TX_X4_CREDIT0_CREDIT1r_reg); 6160 TX_X4_CRED1r_CLOCKCNT1f_SET(TX_X4_CREDIT0_CREDIT1r_reg, or_value); 6161 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_CRED1r(pc, TX_X4_CREDIT0_CREDIT1r_reg)); 6162 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg); 6163 SC_X4_FLD_OVRR_EN1_TYPEr_CLOCKCNT1_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg, 1); 6164 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg)); 6165 6166 or_value = 2; 6167 TX_X4_MAC_CREDGENCNTr_CLR(TX_X4_CREDIT0_MAC_CREDITGENCNTr_reg); 6168 TX_X4_MAC_CREDGENCNTr_MAC_CREDITGENCNTf_SET(TX_X4_CREDIT0_MAC_CREDITGENCNTr_reg, or_value); 6169 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_MAC_CREDGENCNTr(pc, TX_X4_CREDIT0_MAC_CREDITGENCNTr_reg)); 6170 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg); 6171 SC_X4_FLD_OVRR_EN1_TYPEr_MAC_CREDITGENCNT_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg, 1); 6172 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg)); 6173 6174 } 6175 6176 if(pc->sc_mode == TEFMOD16_SC_MODE_ST) { 6177 st_entry = pc->sw_table_entry & 0xff; 6178 speed_entry = (pc->sw_table_entry & 0xff00) >> 8; 6179 configure_st_entry(st_entry, speed_entry, pc); 6180 } 6181 #ifdef _DV_TB_ 6182 pc->adjust_port_mode = 1; 6183 #endif 6184 tefmod16_set_sc_speed(pc); 6185 #ifdef _DV_TB_ 6186 pc->adjust_port_mode = 0; 6187 #endif 6188 return PHYMOD_E_NONE; 6189 } 6190 #endif 6191 6192 6193 /*! 6194 @brief tefmod16_init_pcs_falcon , initializes PCS to the required speed , 6195 @returns The value PHYMOD_E_NONE upon successful completion. 6196 @details 6197 if gloop and rloops are set, calls the corresponding routines 6198 Sets watermark regs, AM timer regs, Higig en/dis controls 6199 calls init_pcs FS or AN, 6200 */ 6201 #ifdef _DV_TB_ 6202 int tefmod16_init_pcs_falcon(PHYMOD_ST* pc) 6203 { 6204 /* Set_port_mode is common to both Autoneg and Forced_speed mode */ 6205 int bypass_int_cor; 6206 int num_lane; 6207 6208 PMD_X4_CTLr_t PMD_X4_PMD_X4_CONTROLr_reg; 6209 #ifdef TSCF_GEN1 6210 TX_X1_T_PMA_WTRMKr_t TX_X1_CONTROL0_T_PMA_WATERMARKr_reg; 6211 CL82_RX_AM_TMRr_t CL82_SHARED_CL82_RX_AM_TIMERr_reg; 6212 TX_X2_MLD_SWP_CNTr_t TX_X2_CONTROL0_MLD_SWAP_COUNTr_reg; 6213 #else 6214 CL82_AM_TMRr_t CL82_SHARED_CL82_AM_TIMERr_reg; 6215 #endif 6216 RX_X1_CL91_CFGr_t RX_X1_CONTROL0_CL91_CONFIGr_reg; 6217 RX_X4_DEC_CTL0r_t RX_X4_CONTROL0_DECODE_CONTROL_0r_reg; 6218 TX_X4_ENC0r_t TX_X4_CONTROL0_ENCODE_0r_reg; 6219 SC_X4_FLD_OVRR_EN0_TYPEr_t SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg; 6220 SC_X4_FLD_OVRR_EN1_TYPEr_t SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg; 6221 AN_X4_INT_ENr_t AN_X4_INT_ENr_reg; 6222 MAIN0_SPD_CTLr_t MAIN0_SPD_CTLr_reg; 6223 TX_X4_TX_CTL0r_t TX_X4_TX_CTL0r_reg; 6224 6225 SC_X4_MSA_25G_50G_CTLr_t SC_X4_MSA_25G_50G_CTLr_reg; 6226 SC_X4_IEEE_25G_CTLr_t SC_X4_IEEE_25G_CTLr_reg; 6227 RX_X4_IEEE_25G_PARLLEL_DET_CTRr_t RX_X4_IEEE_25G_PARLLEL_DET_CTRr_reg; 6228 6229 TEFMOD16_DBG_IN_FUNC_INFO(pc); 6230 6231 if(pc->tsc_touched == 0 && pc->pcs_lane_swap_en) { 6232 tefmod16_pcs_rx_lane_swap(pc, pc->pcs_log_to_phy_rx_lane_swap); 6233 tefmod16_pcs_tx_lane_swap(pc, pc->pcs_log_to_phy_tx_lane_swap); 6234 } 6235 6236 if(pc->tsc_touched == 0) { 6237 MAIN0_SPD_CTLr_CLR(MAIN0_SPD_CTLr_reg); 6238 MAIN0_SPD_CTLr_TSC_CREDIT_SELf_SET(MAIN0_SPD_CTLr_reg, pc->credit_sel); 6239 PHYMOD_IF_ERR_RETURN(MODIFY_MAIN0_SPD_CTLr(pc, MAIN0_SPD_CTLr_reg)); 6240 #ifdef _DV_TB_ 6241 PHYMOD_DEBUG_ERROR(("FCSN_Info : tefmod16_init_pcs_falcon : fc_mode %0d : tsc_credit_sel %0d\n", pc->fc_mode, pc->credit_sel)); 6242 #endif 6243 } 6244 if ((pc->spd_intf == TEFMOD16_SPD_100G_MLD_X4) || 6245 (pc->spd_intf == TEFMOD16_SPD_106G_MLD_HG_X4)) { 6246 TX_X4_TX_CTL0r_CLR(TX_X4_TX_CTL0r_reg); 6247 TX_X4_TX_CTL0r_T_PMA_WATERMARKf_SET( TX_X4_TX_CTL0r_reg , 7); 6248 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_TX_CTL0r(pc,TX_X4_TX_CTL0r_reg)); 6249 6250 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg); 6251 SC_X4_FLD_OVRR_EN1_TYPEr_T_PMA_WATERMARK_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg, 1); 6252 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc,SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg)); 6253 6254 } 6255 else { 6256 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg); 6257 SC_X4_FLD_OVRR_EN1_TYPEr_T_PMA_WATERMARK_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg, 0); 6258 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc,SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg)); 6259 } 6260 6261 switch(pc->port_type) { 6262 case TEFMOD16_MULTI_PORT: num_lane = 1; break; 6263 case TEFMOD16_TRI1_PORT: if(pc->this_lane == 2) num_lane = 2; 6264 else num_lane = 1; 6265 break; 6266 case TEFMOD16_TRI2_PORT: if(pc->this_lane == 0) num_lane = 2; 6267 else num_lane = 1; 6268 break; 6269 case TEFMOD16_DXGXS: num_lane = 2; break; 6270 case TEFMOD16_SINGLE_PORT: num_lane = 4; break; 6271 default : num_lane = 0; 6272 } 6273 6274 if(pc->pcs_gloop_en != 0) { 6275 tefmod16_tx_loopback_control(pc, pc->pcs_gloop_en, pc->this_lane, num_lane); 6276 } 6277 6278 if(pc->pcs_rloop_en != 0) { 6279 tefmod16_rx_loopback_control(pc, pc->pcs_rloop_en, pc->this_lane, num_lane); 6280 } 6281 6282 /* FCSN */ 6283 if(pc->fc_mode) { 6284 #ifdef _DV_TB_ 6285 PHYMOD_DEBUG_ERROR(("FCSN_Info : tefmod16_init_pcs_falcon : port %0d : fc_mode %0d : tx_fcsn_mode %02x : rx_fcsn_mode %02x\n", pc->this_lane, pc->fc_mode, pc->tx_fcsn_mode, pc->rx_fcsn_mode)); 6286 #endif 6287 6288 if(pc->pmd_touched == 0) { 6289 pc->pmd_reset_control = 0x1; 6290 tefmod16_pmd_core_reset_bypass(pc, pc->pmd_reset_control); 6291 } 6292 pc->pmd_reset_control = 0x10; 6293 tefmod16_pmd_lane_reset_bypass(pc, pc->pmd_reset_control); 6294 } 6295 6296 if(pc->pmd_rloop_en != 0) { 6297 tefmod16_rx_pmd_loopback_control(pc, pc->pcs_rloop_en, pc->pmd_rloop_en, pc->this_lane); 6298 } 6299 tefmod16_update_port_mode_select(pc, pc->port_type, pc->this_lane, pc->tsc_clk_freq_pll_by_48, pc->pll_reset_en); 6300 pc->per_lane_control = 3; 6301 6302 PMD_X4_CTLr_CLR(PMD_X4_PMD_X4_CONTROLr_reg); 6303 6304 PMD_X4_CTLr_LN_RX_H_PWRDNf_SET(PMD_X4_PMD_X4_CONTROLr_reg, 0); 6305 PMD_X4_CTLr_LN_TX_H_PWRDNf_SET(PMD_X4_PMD_X4_CONTROLr_reg, 0); 6306 6307 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X4_CTLr(pc, PMD_X4_PMD_X4_CONTROLr_reg)); 6308 6309 PMD_X4_CTLr_CLR(PMD_X4_PMD_X4_CONTROLr_reg); 6310 PMD_X4_CTLr_LN_H_RSTBf_SET(PMD_X4_PMD_X4_CONTROLr_reg, 1); 6311 PMD_X4_CTLr_LN_DP_H_RSTBf_SET(PMD_X4_PMD_X4_CONTROLr_reg, 1); 6312 6313 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X4_CTLr(pc, PMD_X4_PMD_X4_CONTROLr_reg)); 6314 6315 #ifdef TSCF_GEN1 6316 TX_X1_T_PMA_WTRMKr_CLR(TX_X1_CONTROL0_T_PMA_WATERMARKr_reg); 6317 TX_X1_T_PMA_WTRMKr_FIVE_LANE_BITMUX_WATERMARKf_SET(TX_X1_CONTROL0_T_PMA_WATERMARKr_reg, 7); 6318 TX_X1_T_PMA_WTRMKr_TWO_LANE_BITMUX_WATERMARKf_SET(TX_X1_CONTROL0_T_PMA_WATERMARKr_reg, 5); 6319 TX_X1_T_PMA_WTRMKr_SINGLE_LANE_BITMUX_WATERMARKf_SET(TX_X1_CONTROL0_T_PMA_WATERMARKr_reg, 4); 6320 6321 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X1_T_PMA_WTRMKr(pc, TX_X1_CONTROL0_T_PMA_WATERMARKr_reg)); 6322 #endif 6323 6324 if(pc->cl91_en != 0 && pc->an_en != 1) { 6325 bypass_int_cor = 0; 6326 if(pc->cl91_bypass_indication) { 6327 bypass_int_cor |= TEFMOD16_CL91_IND_ONLY_EN_DIS; 6328 } 6329 if(pc->cl91_bypass_correction) { 6330 bypass_int_cor |= TEFMOD16_CL91_COR_ONLY_EN_DIS; 6331 } 6332 tefmod16_FEC_control(pc, (TEFMOD16_CL91_TX_EN_DIS|TEFMOD_CL91_RX_EN_DIS|bypass_int_cor), 0, 0); 6333 } else if(pc->cl91_en == 0 && pc->an_en != 1) { 6334 tefmod16_FEC_control(pc, 0, (TEFMOD16_CL91_TX_EN_DIS|TEFMOD_CL91_RX_EN_DIS), 0); 6335 } 6336 6337 if(pc->cl91_nofec == 1) { 6338 tefmod16_FEC_control(pc, TEFMOD16_CL74_CL91_EN_DIS, 0, 0); 6339 } 6340 if(pc->cl91_cl74 == 1) { 6341 tefmod16_FEC_control(pc, TEFMOD16_CL74_CL91_EN_DIS, 0, 1); 6342 } 6343 6344 tefmod16_tx_lane_control(pc, pc->per_lane_control&1, 0); 6345 tefmod16_rx_lane_control(pc, pc->accData, pc->per_lane_control); 6346 6347 6348 RX_X1_CL91_CFGr_CLR(RX_X1_CONTROL0_CL91_CONFIGr_reg); 6349 if(pc->rx_am_timer_init_val == 0x400) { 6350 printf("CL91_AM_SPACING_1024 set.\n"); 6351 RX_X1_CL91_CFGr_CL91_AM_SPACING_1024f_SET(RX_X1_CONTROL0_CL91_CONFIGr_reg, 1); 6352 } 6353 6354 #ifdef TSC_MT2 6355 printf("CL91_FC_LOCK_CORR_CW set.\n"); 6356 RX_X1_CL91_CFGr_CL91_FC_LOCK_CORR_CWf_SET(RX_X1_CONTROL0_CL91_CONFIGr_reg, 1); 6357 #else 6358 printf("CL91_FC_LOCK_CORR_CW clr.\n"); 6359 RX_X1_CL91_CFGr_CL91_FC_LOCK_CORR_CWf_SET(RX_X1_CONTROL0_CL91_CONFIGr_reg, 0); 6360 #endif 6361 PHYMOD_IF_ERR_RETURN(MODIFY_RX_X1_CL91_CFGr(pc, RX_X1_CONTROL0_CL91_CONFIGr_reg)); 6362 6363 tefmod16_cl74_control_fec_0(pc); 6364 tefmod16_cl74_control_fec_1(pc); 6365 tefmod16_cl74_control_fec_2(pc); 6366 tefmod16_cl74_control_fec_3(pc); 6367 6368 /* cfg_rx_am_timer_init_val=3ff cfg_tx_am_timer_init_val=ffc */ 6369 #ifdef TSCF_GEN1 6370 CL82_RX_AM_TMRr_CLR(CL82_SHARED_CL82_RX_AM_TIMERr_reg); 6371 TX_X2_MLD_SWP_CNTr_CLR(TX_X2_CONTROL0_MLD_SWAP_COUNTr_reg); 6372 6373 6374 if(pc->rx_am_timer_init_val != 0x3fff) { 6375 CL82_RX_AM_TMRr_SET(CL82_SHARED_CL82_RX_AM_TIMERr_reg, pc->rx_am_timer_init_val); 6376 PHYMOD_IF_ERR_RETURN(WRITE_CL82_RX_AM_TMRr(pc, CL82_SHARED_CL82_RX_AM_TIMERr_reg)); 6377 } 6378 if(pc->tx_am_timer_init_val != 0xffff) { 6379 TX_X2_MLD_SWP_CNTr_SET(TX_X2_CONTROL0_MLD_SWAP_COUNTr_reg, pc->tx_am_timer_init_val); 6380 PHYMOD_IF_ERR_RETURN(WRITE_TX_X2_MLD_SWP_CNTr(pc, TX_X2_CONTROL0_MLD_SWAP_COUNTr_reg)); 6381 } 6382 #else 6383 CL82_AM_TMRr_CLR(CL82_SHARED_CL82_AM_TIMERr_reg); 6384 if(pc->rx_am_timer_init_val != 0x3fff) { 6385 CL82_AM_TMRr_SET(CL82_SHARED_CL82_AM_TIMERr_reg, pc->rx_am_timer_init_val); 6386 PHYMOD_IF_ERR_RETURN(WRITE_CL82_AM_TMRr(pc, CL82_SHARED_CL82_AM_TIMERr_reg)); 6387 } 6388 6389 #endif 6390 6391 /* +cfg_rx_higig2_oen +cfg_tx_higig2_oen */ 6392 /* Set t_HG2_ENABLE_oen bit 10 in 0xc060 */ 6393 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 6394 SC_X4_FLD_OVRR_EN0_TYPEr_T_HG2_ENABLE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, pc->tx_higig2_oen & 0x1); 6395 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 6396 6397 /* Clr/Set HG2_ENABLE bit 10 in 0xc111 */ 6398 TX_X4_ENC0r_CLR(TX_X4_CONTROL0_ENCODE_0r_reg); 6399 TX_X4_ENC0r_HG2_ENABLEf_SET(TX_X4_CONTROL0_ENCODE_0r_reg, pc->tx_higig2_en); 6400 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_ENC0r(pc,TX_X4_CONTROL0_ENCODE_0r_reg)); 6401 6402 /* +cfg_tefmod16_use_higig2_knobs +cfg_tx_higig2_codec */ 6403 if(pc->tefmod16_use_higig2_knobs == 0x1) { 6404 TX_X4_ENC0r_CLR(TX_X4_CONTROL0_ENCODE_0r_reg); 6405 TX_X4_ENC0r_HG2_CODECf_SET(TX_X4_CONTROL0_ENCODE_0r_reg, pc->tx_higig2_codec); 6406 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_ENC0r(pc,TX_X4_CONTROL0_ENCODE_0r_reg)); 6407 } 6408 6409 /*CHAK setting tx scramble idle test mode*/ 6410 6411 if(pc->scramble_idle_tx_test_mode==0x1) { 6412 printf("CHAK:eabling tx testmode cfg"); 6413 TX_X4_ENC0r_CLR(TX_X4_CONTROL0_ENCODE_0r_reg); 6414 TX_X4_ENC0r_TX_TEST_MODE_CFGf_SET(TX_X4_CONTROL0_ENCODE_0r_reg, pc->scramble_idle_tx_test_mode); 6415 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_ENC0r(pc,TX_X4_CONTROL0_ENCODE_0r_reg)); 6416 6417 } 6418 /* Set r_HG2_ENABLE_oen bit 15 in 0xc061 */ 6419 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg); 6420 SC_X4_FLD_OVRR_EN1_TYPEr_R_HG2_ENABLE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg, pc->rx_higig2_oen & 0x1); 6421 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg)); 6422 6423 /* Clr/Set HG2_ENABLE bit 12 in 0xc134 */ 6424 RX_X4_DEC_CTL0r_CLR(RX_X4_CONTROL0_DECODE_CONTROL_0r_reg); 6425 RX_X4_DEC_CTL0r_HG2_ENABLEf_SET(RX_X4_CONTROL0_DECODE_CONTROL_0r_reg, pc->rx_higig2_en); 6426 PHYMOD_IF_ERR_RETURN(MODIFY_RX_X4_DEC_CTL0r(pc, RX_X4_CONTROL0_DECODE_CONTROL_0r_reg)); 6427 6428 /* CHAK:set rx_test_mode to 1 */ 6429 if(pc->scramble_idle_rx_test_mode == 0x1) { 6430 printf("CHAK:enabling testmode in rx"); 6431 RX_X4_DEC_CTL0r_CLR(RX_X4_CONTROL0_DECODE_CONTROL_0r_reg); 6432 RX_X4_DEC_CTL0r_R_TEST_MODE_CFGf_SET(RX_X4_CONTROL0_DECODE_CONTROL_0r_reg, pc->scramble_idle_rx_test_mode); 6433 PHYMOD_IF_ERR_RETURN(MODIFY_RX_X4_DEC_CTL0r(pc, RX_X4_CONTROL0_DECODE_CONTROL_0r_reg)); 6434 } 6435 6436 /* +cfg_tefmod16_use_higig2_knobs +cfg_rx_higig2_codec */ 6437 if(pc->tefmod16_use_higig2_knobs == 0x1) { 6438 RX_X4_DEC_CTL0r_CLR(RX_X4_CONTROL0_DECODE_CONTROL_0r_reg); 6439 RX_X4_DEC_CTL0r_HG2_CODECf_SET(RX_X4_CONTROL0_DECODE_CONTROL_0r_reg, pc->rx_higig2_codec); 6440 PHYMOD_IF_ERR_RETURN(MODIFY_RX_X4_DEC_CTL0r(pc, RX_X4_CONTROL0_DECODE_CONTROL_0r_reg)); 6441 } 6442 6443 #ifdef _DV_TB_ 6444 RX_X4_DEC_CTL0r_CLR(RX_X4_CONTROL0_DECODE_CONTROL_0r_reg); 6445 RX_X4_DEC_CTL0r_DISABLE_CL49_BERMONf_SET(RX_X4_CONTROL0_DECODE_CONTROL_0r_reg, pc->disable_cl49_bermon); 6446 PHYMOD_IF_ERR_RETURN(MODIFY_RX_X4_DEC_CTL0r(pc, RX_X4_CONTROL0_DECODE_CONTROL_0r_reg)); 6447 #endif 6448 6449 6450 6451 /* MSA Related configurations */ 6452 printf("In tefmod16_init_pcs_falcon and configuring the MSA registers msa_25G_am0_mode:%0d msa_25G_am123_mode:%0d msa_50G_am0_mode:%0d msa_50G_am123_mode:%0d cl74_shcorrupt_50msa: %0d cl74_shcorrupt_25msa :%0d \n", 6453 pc->msa_25G_am0_mode,pc->msa_25G_am123_mode,pc->msa_50G_am0_mode,pc->msa_50G_am123_mode,pc->cl74_shcorrupt_50msa,pc->cl74_shcorrupt_25msa); 6454 SC_X4_MSA_25G_50G_CTLr_CLR(SC_X4_MSA_25G_50G_CTLr_reg); 6455 SC_X4_MSA_25G_50G_CTLr_MSA_25G_CWSCR_ENf_SET(SC_X4_MSA_25G_50G_CTLr_reg, pc->msa_25G_cw_scr_en); 6456 SC_X4_MSA_25G_50G_CTLr_MSA_25G_5BIT_XORf_SET(SC_X4_MSA_25G_50G_CTLr_reg, pc->msa_25G_5bit_XOR); 6457 SC_X4_MSA_25G_50G_CTLr_MSA_25G_AM_ENf_SET(SC_X4_MSA_25G_50G_CTLr_reg, pc->msa_25G_am_en); 6458 SC_X4_MSA_25G_50G_CTLr_MSA_25G_AM0_FORMATf_SET(SC_X4_MSA_25G_50G_CTLr_reg, pc->msa_25G_am0_mode); 6459 SC_X4_MSA_25G_50G_CTLr_MSA_25G_AM123_FORMATf_SET(SC_X4_MSA_25G_50G_CTLr_reg, pc->msa_25G_am123_mode); 6460 SC_X4_MSA_25G_50G_CTLr_MSA_50G_AM0_FORMATf_SET(SC_X4_MSA_25G_50G_CTLr_reg, pc->msa_50G_am0_mode); 6461 SC_X4_MSA_25G_50G_CTLr_MSA_50G_AM123_FORMATf_SET(SC_X4_MSA_25G_50G_CTLr_reg, pc->msa_50G_am123_mode); 6462 SC_X4_MSA_25G_50G_CTLr_MSA_WINDOW_SELf_SET(SC_X4_MSA_25G_50G_CTLr_reg,pc->msa_window_sel); 6463 SC_X4_MSA_25G_50G_CTLr_MSA_COUNT_SELf_SET(SC_X4_MSA_25G_50G_CTLr_reg,pc->msa_count_sel); 6464 SC_X4_MSA_25G_50G_CTLr_CL74_SHCORRUPT_50GMSAf_SET(SC_X4_MSA_25G_50G_CTLr_reg,pc->cl74_shcorrupt_50msa); 6465 SC_X4_MSA_25G_50G_CTLr_CL74_SHCORRUPT_25GMSAf_SET(SC_X4_MSA_25G_50G_CTLr_reg,pc->cl74_shcorrupt_25msa); 6466 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_MSA_25G_50G_CTLr(pc, SC_X4_MSA_25G_50G_CTLr_reg)); 6467 6468 6469 6470 /* IEEE Related configurations */ 6471 printf("In tefmod16_init_pcs_falcon and configuring the IEEE registers ieee_25G_am0_mode:%0d ieee_25G_am123_mode:%0d 25G shcorrupt :%0d \n",pc->ieee_25G_am0_mode,pc->ieee_25G_am123_mode,pc->cl74_shcorrupt_25ieee); 6472 SC_X4_IEEE_25G_CTLr_CLR(SC_X4_IEEE_25G_CTLr_reg); 6473 SC_X4_IEEE_25G_CTLr_IEEE_25G_CWSCR_ENf_SET(SC_X4_IEEE_25G_CTLr_reg, pc->ieee_25G_cw_scr_en); 6474 SC_X4_IEEE_25G_CTLr_IEEE_25G_5BIT_XORf_SET(SC_X4_IEEE_25G_CTLr_reg, pc->ieee_25G_5bit_XOR); 6475 SC_X4_IEEE_25G_CTLr_IEEE_25G_AM_ENf_SET(SC_X4_IEEE_25G_CTLr_reg, pc->ieee_25G_am_en); 6476 SC_X4_IEEE_25G_CTLr_IEEE_25G_AM0_FORMATf_SET(SC_X4_IEEE_25G_CTLr_reg, pc->ieee_25G_am0_mode); 6477 SC_X4_IEEE_25G_CTLr_IEEE_25G_AM123_FORMATf_SET(SC_X4_IEEE_25G_CTLr_reg, pc->ieee_25G_am123_mode); 6478 SC_X4_IEEE_25G_CTLr_IEEE_WINDOW_SELf_SET(SC_X4_IEEE_25G_CTLr_reg,pc->ieee_window_sel); 6479 SC_X4_IEEE_25G_CTLr_IEEE_COUNT_SELf_SET(SC_X4_IEEE_25G_CTLr_reg,pc->ieee_count_sel); 6480 SC_X4_IEEE_25G_CTLr_CL74_SHCORRUPT_25IEEEf_SET(SC_X4_IEEE_25G_CTLr_reg,pc->cl74_shcorrupt_25ieee); 6481 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_IEEE_25G_CTLr(pc, SC_X4_IEEE_25G_CTLr_reg)); 6482 6483 /* 6484 SC_X4_IEEE_25G_CTLr_IEEE_WINDOW_SELf_SET(SC_X4_IEEE_25G_CTLr_reg,); 6485 SC_X4_IEEE_25G_CTLr_IEEE_COUNT_SELf_SET(SC_X4_IEEE_25G_CTLr_reg,); 6486 SC_X4_IEEE_25G_CTLr_CL74_SHCORRUPT_25IEEEf_SET(SC_X4_IEEE_25G_CTLr_reg,); 6487 */ 6488 6489 /* Auto detect settings */ 6490 printf("In tefmod16_init_pcs_falcon and configuring the parallel detect registers msa_ieee_det_en:%0x \n",pc->msa_ieee_det_en); 6491 RX_X4_IEEE_25G_PARLLEL_DET_CTRr_CLR(RX_X4_IEEE_25G_PARLLEL_DET_CTRr_reg); 6492 RX_X4_IEEE_25G_PARLLEL_DET_CTRr_MSA_IEEE_DET_ENf_SET(RX_X4_IEEE_25G_PARLLEL_DET_CTRr_reg, pc->msa_ieee_det_en); 6493 PHYMOD_IF_ERR_RETURN(MODIFY_RX_X4_IEEE_25G_PARLLEL_DET_CTRr(pc, RX_X4_IEEE_25G_PARLLEL_DET_CTRr_reg)); 6494 6495 6496 6497 6498 /*if FEC enabled */ 6499 if(pc->t_fec_enable) { 6500 tefmod16_FEC_control(pc, (TEFMOD16_CL74_TX_EN_DIS|TEFMOD_CL74_RX_EN_DIS), 0, 0); 6501 } 6502 6503 /* Programming the an_good_check_entry, an_completed_sw, ld_page_req, lp_page_rdy interrupt enable */ 6504 AN_X4_INT_ENr_CLR(AN_X4_INT_ENr_reg); 6505 AN_X4_INT_ENr_AN_GOOD_CHK_ENf_SET(AN_X4_INT_ENr_reg, pc->an_gc_entry_int_en); 6506 AN_X4_INT_ENr_AN_COMPLETED_SW_ENf_SET(AN_X4_INT_ENr_reg, pc->sw_an_completed_en); 6507 AN_X4_INT_ENr_LD_PAGE_REQ_ENf_SET(AN_X4_INT_ENr_reg, pc->ld_page_req_en); 6508 AN_X4_INT_ENr_LP_PAGE_RDY_ENf_SET(AN_X4_INT_ENr_reg, pc->lp_page_rdy_en); 6509 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_INT_ENr(pc, AN_X4_INT_ENr_reg)); 6510 6511 6512 /* call FS or AN mode */ 6513 if(pc->an_en) { 6514 tefmod16_init_pcs_an(pc); 6515 } else { 6516 tefmod16_init_pcs_fs(pc); 6517 } 6518 if(pc->pmd_gloop_en != 0) { 6519 tefmod16_tx_pmd_loopback_control(pc, pc->pmd_gloop_en); 6520 } 6521 6522 6523 if(pc->cl72_training_restart || pc->cl72_training_enabled) { 6524 pc->per_lane_control = pc->cl72_training_restart | (pc->cl72_training_enabled<<1); 6525 tefmod16_clause72_control(pc, pc->per_lane_control, pc->port_type); 6526 } 6527 return PHYMOD_E_NONE; 6528 } 6529 #endif 6530 6531 /*! 6532 @brief tefmod16_poll_for_sc_done , polls for the sc_done bit , 6533 @returns The value PHYMOD_E_NONE upon successful completion. 6534 @details 6535 Reads the SC_X4_COntrol_status reg and polls it to see if sc_done bit is set 6536 Sets the sc_done flag=1/0, if speed control is done, after resolving to the correct speed 6537 */ 6538 int tefmod16_poll_for_sc_done(PHYMOD_ST* pc, int mapped_speed) 6539 { 6540 int done; 6541 int spd_match, sc_done; 6542 int cnt; 6543 uint16_t data; 6544 6545 SC_X4_STSr_t SC_X4_CONTROL_SC_X4_CONTROL_STATUSr_reg; 6546 SC_X4_RSLVD_SPDr_t SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEEDr_reg; 6547 6548 TEFMOD16_DBG_IN_FUNC_INFO(pc); 6549 cnt=0; 6550 sc_done = 0; 6551 spd_match = 0; 6552 6553 SC_X4_STSr_CLR(SC_X4_CONTROL_SC_X4_CONTROL_STATUSr_reg); 6554 while (cnt <=2000) { 6555 PHYMOD_IF_ERR_RETURN(READ_SC_X4_STSr(pc, &SC_X4_CONTROL_SC_X4_CONTROL_STATUSr_reg)); 6556 cnt = cnt + 1; 6557 if(SC_X4_STSr_SW_SPEED_CHANGE_DONEf_GET(SC_X4_CONTROL_SC_X4_CONTROL_STATUSr_reg)) { 6558 sc_done = 1; 6559 break; 6560 } else { 6561 if(cnt == 2000) { 6562 sc_done = 0; 6563 break; 6564 } 6565 } 6566 } 6567 6568 cnt=0; 6569 while (cnt <=400) { 6570 SC_X4_RSLVD_SPDr_CLR(SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEEDr_reg); 6571 PHYMOD_IF_ERR_RETURN(READ_SC_X4_RSLVD_SPDr(pc, &SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEEDr_reg)); 6572 data = SC_X4_RSLVD_SPDr_SPEEDf_GET(SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEEDr_reg); 6573 #ifdef _DV_TB_ 6574 if(pc->verbosity) 6575 PHYMOD_DEBUG_ERROR(("Resolved speed is %x :: need %x :: uint :: %d :: lane :: %d\n", data, mapped_speed, pc->unit, pc->this_lane)); 6576 #endif 6577 cnt = cnt + 1; 6578 if(data == mapped_speed) { 6579 spd_match = 1; 6580 break; 6581 } else { 6582 if(cnt == 400) { 6583 spd_match = 0; 6584 break; 6585 } 6586 } 6587 } 6588 if(sc_done && spd_match) { 6589 done = 1; 6590 } else { 6591 done = 0; 6592 } 6593 return done; 6594 } 6595 6596 /*! 6597 @brief tefmod16_check_status , checks the statistics port_mode, 6598 @returns The value PHYMOD_E_NONE upon successful completion. 6599 @details 6600 Populates the HT entries, based on the speed 6601 In this routine, the following regs are read:RESOLVED_0r_STATUS to RESOLVED_5r_STATUS 6602 The read value from these are what is the actual (RTL sends this)and whatever was stored in lookup is what DV expects 6603 Sets the sc_done flag=1, if there are no mismatches 6604 */ 6605 6606 #ifdef _DV_TB_ 6607 int tefmod16_check_status(PHYMOD_ST* pc) 6608 { 6609 uint16_t fail; 6610 int actual_speed; 6611 int mapped_speed; 6612 int spd_change_done; 6613 PHYMOD_ST sc_stats_actual; 6614 PHYMOD_ST* sc_stats_print_actual; 6615 SC_X4_RSLVD_SPDr_t SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEEDr_reg; 6616 SC_X4_RSLVD0r_t SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0r_reg; 6617 SC_X4_RSLVD1r_t SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1r_reg; 6618 SC_X4_RSLVD2r_t SC_X4_FINAL_CONFIG_STATUS_RESOLVED_2r_reg; 6619 SC_X4_RSLVD3r_t SC_X4_FINAL_CONFIG_STATUS_RESOLVED_3r_reg; 6620 SC_X4_RSLVD4r_t SC_X4_FINAL_CONFIG_STATUS_RESOLVED_4r_reg; 6621 SC_X4_RSLVD5r_t SC_X4_FINAL_CONFIG_STATUS_RESOLVED_5r_reg; 6622 /*SC_X4_RSLVD6r_t SC_X4_FINAL_CONFIG_STATUS_RESOLVED_6r_reg;*/ 6623 SC_X4_RSLVD7r_t SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7r_reg; 6624 SC_X4_RSLVD8r_t SC_X4_FINAL_CONFIG_STATUS_RESOLVED_8r_reg; 6625 SC_X4_FEC_STSr_t SC_X4_FINAL_CONFIG_STATUS_FEC_STATUSr_reg; 6626 6627 TEFMOD16_DBG_IN_FUNC_INFO(pc); 6628 spd_change_done = 0; 6629 6630 6631 if(!pc->an_en) { 6632 tefmod16_get_mapped_speed(pc->spd_intf, &mapped_speed); 6633 pc->speed = mapped_speed; 6634 spd_change_done = tefmod16_poll_for_sc_done(pc, pc->speed); 6635 if(spd_change_done) { 6636 printf("Speed change done for :: unit %0d port %0d \n", pc->unit, pc->this_lane); 6637 } 6638 } 6639 6640 printf("\nSTATS_Info : tefmod16_check_status (1a) : pc->an_en %01x : pc->speed %02x : pc->an_fec_sel_override %01x : pc->cl91_en %01x : pc->an_fec %01x : pc->bam_cl74_fec %01x : pc->t_fec_enable %1x : pc->cl91_nofec %1x : pc->cl91_cl74 %1x\n", pc->an_en, pc->speed, pc->an_fec_sel_override, pc->cl91_en, pc->an_fec, pc->bam_cl74_fec, pc->t_fec_enable, pc->t_fec_enable, pc->cl91_nofec, pc->cl91_cl74) ; 6641 6642 printf("STATS_Info : tefmod16_check_status (1b) : pc->sc_mode %2d : pc->fc_mode %1x : pc->fc_rx_spd_intf %02d : pc->fc_tx_spd_intf %02d\n", pc->sc_mode, pc->fc_mode, pc->fc_rx_spd_intf, pc->fc_tx_spd_intf) ; 6643 6644 printf("STATS_Info : tefmod16_check_status (1c) : pc->t_pma_btmx_mode %1x : pc->deskew_mode %1x : pc->bs_sync_en %1x : pc->bs_dist_mode %1x : pc->bs_btmx_mode %1x : pc->t_fifo_mode %1x : pc->bs_sm_sync_mode %1x\n\n", pc->t_pma_btmx_mode, pc->deskew_mode, pc->bs_sync_en, pc->bs_dist_mode, pc->bs_btmx_mode, pc->t_fifo_mode, pc->bs_sm_sync_mode) ; 6645 6646 if(pc->an_en) { 6647 6648 if(pc->speed == SC_X4_CONTROL_CONTROL_SPEED_S_100G_CR4 || 6649 pc->speed == SC_X4_CONTROL_CONTROL_SPEED_S_100G_KR4 || 6650 pc->speed == SC_X4_CONTROL_CONTROL_SPEED_S_100G_HG2_CR4 || 6651 pc->speed == SC_X4_CONTROL_CONTROL_SPEED_S_100G_HG2_KR4 6652 ) { 6653 pc->cl91_en = 1; 6654 } 6655 6656 if(cl91_valid_speed(pc)) { 6657 printf("Resolved speed is %0d an_fec_sel_override %0d \n", pc->speed, pc->an_fec_sel_override); 6658 if(pc->an_fec_sel_override == 1) { 6659 pc->cl91_en = 0; 6660 pc->an_hcd_fec = 0; 6661 } 6662 else if(pc->an_fec_sel_override == 2) { 6663 pc->cl91_en = 0; 6664 pc->an_hcd_fec = 1; 6665 } 6666 else if(pc->an_fec_sel_override == 3) { 6667 pc->cl91_en = 1; 6668 pc->an_hcd_fec = 0; 6669 } 6670 } 6671 } 6672 6673 printf("STATS_Info : tefmod16_check_status (2a) : pc->an_en %01x : pc->speed %02x : pc->an_fec_sel_override %01x : pc->cl91_en %01x : pc->an_fec %01x : pc->bam_cl74_fec %01x : pc->t_fec_enable %1x : pc->cl91_nofec %1x : pc->cl91_cl74 %1x\n", pc->an_en, pc->speed, pc->an_fec_sel_override, pc->cl91_en, pc->an_fec, pc->bam_cl74_fec, pc->t_fec_enable, pc->t_fec_enable, pc->cl91_nofec, pc->cl91_cl74) ; 6674 6675 printf("STATS_Info : tefmod16_check_status (2b) : pc->sc_mode %2d : pc->fc_mode %1x : pc->fc_rx_spd_intf %02d : pc->fc_tx_spd_intf %02d\n", pc->sc_mode, pc->fc_mode, pc->fc_rx_spd_intf, pc->fc_tx_spd_intf) ; 6676 6677 printf("STATS_Info : tefmod16_check_status (2c) : pc->t_pma_btmx_mode %1x : pc->deskew_mode %1x : pc->bs_sync_en %1x : pc->bs_dist_mode %1x : pc->bs_btmx_mode %1x : pc->t_fifo_mode %1x : pc->bs_sm_sync_mode %1x\n\n", pc->t_pma_btmx_mode, pc->deskew_mode, pc->bs_sync_en, pc->bs_dist_mode, pc->bs_btmx_mode, pc->t_fifo_mode, pc->bs_sm_sync_mode) ; 6678 6679 tefmod16_get_ht_entries(pc); /* Must be after an_fec_sel_override code */ 6680 6681 printf("\nSTATS_Info : tefmod16_check_status (3a) : pc->an_en %01x : pc->speed %02x : pc->an_fec_sel_override %01x : pc->cl91_en %01x : pc->an_fec %01x : pc->bam_cl74_fec %01x : pc->t_fec_enable %1x : pc->cl91_nofec %1x : pc->cl91_cl74 %1x\n", pc->an_en, pc->speed, pc->an_fec_sel_override, pc->cl91_en, pc->an_fec, pc->bam_cl74_fec, pc->t_fec_enable, pc->t_fec_enable, pc->cl91_nofec, pc->cl91_cl74) ; 6682 6683 printf("STATS_Info : tefmod16_check_status (3b) : pc->sc_mode %2d : pc->fc_mode %1x : pc->fc_rx_spd_intf %02d : pc->fc_tx_spd_intf %02d\n", pc->sc_mode, pc->fc_mode, pc->fc_rx_spd_intf, pc->fc_tx_spd_intf) ; 6684 6685 printf("STATS_Info : tefmod16_check_status (3c) : pc->t_pma_btmx_mode %1x : pc->deskew_mode %1x : pc->bs_sync_en %1x : pc->bs_dist_mode %1x : pc->bs_btmx_mode %1x : pc->t_fifo_mode %1x : pc->bs_sm_sync_mode %1x\n\n", pc->t_pma_btmx_mode, pc->deskew_mode, pc->bs_sync_en, pc->bs_dist_mode, pc->bs_btmx_mode, pc->t_fifo_mode, pc->bs_sm_sync_mode) ; 6686 6687 if(pc->sc_mode == TEFMOD16_SC_MODE_ST_OVERRIDE) { 6688 pc->os_mode=0; 6689 pc->clkcnt1 = 0x5; 6690 pc->lpcnt0 = 0x1; 6691 pc->lpcnt1 = 0x12; 6692 pc->cgc = 0x4; 6693 pc->cl72_en = 0; 6694 } 6695 6696 if(pc->sc_mode == TEFMOD16_SC_MODE_AN_CL73) { 6697 pc->speed = 0x01; 6698 } 6699 6700 6701 printf("STATS_Info : tefmod16_check_status (4a) : pc->t_pma_btmx_mode %1x : pc->deskew_mode %1x : pc->bs_sync_en %1x : pc->bs_dist_mode %1x : pc->bs_btmx_mode %1x : pc->t_fifo_mode %1x : pc->bs_sm_sync_mode %1x\n", pc->t_pma_btmx_mode, pc->deskew_mode, pc->bs_sync_en, pc->bs_dist_mode, pc->bs_btmx_mode, pc->t_fifo_mode, pc->bs_sm_sync_mode) ; 6702 6703 6704 /* This code below is used only in the case where AN resolves to 100G, and you want to 6705 * override the default 100G FEC */ 6706 if(pc->cl91_nofec != 0 || pc->cl91_cl74) { 6707 pc->t_pma_btmx_mode = 2; 6708 pc->deskew_mode = 4; 6709 pc->bs_sync_en = 1; 6710 pc->bs_dist_mode = 3; 6711 pc->bs_btmx_mode = 2; 6712 6713 printf("STATS_Info : tefmod16_check_status (4d) : pc->t_pma_btmx_mode %1x : pc->deskew_mode %1x : pc->bs_sync_en %1x : pc->bs_dist_mode %1x : pc->bs_btmx_mode %1x : pc->t_fifo_mode %1x : pc->bs_sm_sync_mode %1x\n", pc->t_pma_btmx_mode, pc->deskew_mode, pc->bs_sync_en, pc->bs_dist_mode, pc->bs_btmx_mode, pc->t_fifo_mode, pc->bs_sm_sync_mode) ; 6714 } 6715 6716 if(pc->cl91_cl74 != 0) { 6717 pc->bs_sync_en = 0; 6718 6719 printf("STATS_Info : tefmod16_check_status (4e) : pc->t_pma_btmx_mode %1x : pc->deskew_mode %1x : pc->bs_sync_en %1x : pc->bs_dist_mode %1x : pc->bs_btmx_mode %1x : pc->t_fifo_mode %1x : pc->bs_sm_sync_mode %1x\n", pc->t_pma_btmx_mode, pc->deskew_mode, pc->bs_sync_en, pc->bs_dist_mode, pc->bs_btmx_mode, pc->t_fifo_mode, pc->bs_sm_sync_mode) ; 6720 } 6721 6722 if(pc->cl91_en != 0) { 6723 if(pc->speed == 0x30 || pc->speed == 0x31 || pc->speed == 0x32 || 6724 pc->speed == 0x34 || pc->speed == 0x35 || pc->speed == 0x36) { 6725 pc->deskew_mode = 8; 6726 pc->bs_dist_mode = 0; 6727 pc->bs_btmx_mode = 0; 6728 6729 printf("STATS_Info : tefmod16_check_status (4f) : pc->t_pma_btmx_mode %1x : pc->deskew_mode %1x : pc->bs_sync_en %1x : pc->bs_dist_mode %1x : pc->bs_btmx_mode %1x : pc->t_fifo_mode %1x : pc->bs_sm_sync_mode %1x\n", pc->t_pma_btmx_mode, pc->deskew_mode, pc->bs_sync_en, pc->bs_dist_mode, pc->bs_btmx_mode, pc->t_fifo_mode, pc->bs_sm_sync_mode) ; 6730 } 6731 6732 if(pc->speed == 0x10 || pc->speed == 0x11 || pc->speed == 0x12 || 6733 pc->speed == 0x14 || pc->speed == 0x15 || pc->speed == 0x16) { 6734 if(pc->msa_25G_am_en == 1) { 6735 pc->t_fifo_mode = 1; 6736 pc->deskew_mode = 7; 6737 pc->bs_sm_sync_mode = 0; 6738 } 6739 else { 6740 pc->t_fifo_mode = 0; 6741 pc->deskew_mode = 9; 6742 pc->bs_sm_sync_mode = 0; 6743 } 6744 6745 printf("STATS_Info : tefmod16_check_status (4g) : pc->t_pma_btmx_mode %1x : pc->deskew_mode %1x : pc->bs_sync_en %1x : pc->bs_dist_mode %1x : pc->bs_btmx_mode %1x : pc->t_fifo_mode %1x : pc->bs_sm_sync_mode %1x\n", pc->t_pma_btmx_mode, pc->deskew_mode, pc->bs_sync_en, pc->bs_dist_mode, pc->bs_btmx_mode, pc->t_fifo_mode, pc->bs_sm_sync_mode) ; 6746 } 6747 6748 if(pc->speed == 0x70 || pc->speed == 0x71 || pc->speed == 0x72 || pc->speed == 0x73) { 6749 if(pc->ieee_25G_am_en == 1) { 6750 pc->t_fifo_mode = 1; 6751 pc->deskew_mode = 7; 6752 pc->bs_sm_sync_mode = 0; 6753 } 6754 else { 6755 pc->t_fifo_mode = 0; 6756 pc->deskew_mode = 9; 6757 pc->bs_sm_sync_mode = 0; 6758 } 6759 6760 printf("STATS_Info : tefmod16_check_status (4h) : pc->t_pma_btmx_mode %1x : pc->deskew_mode %1x : pc->bs_sync_en %1x : pc->bs_dist_mode %1x : pc->bs_btmx_mode %1x : pc->t_fifo_mode %1x : pc->bs_sm_sync_mode %1x\n", pc->t_pma_btmx_mode, pc->deskew_mode, pc->bs_sync_en, pc->bs_dist_mode, pc->bs_btmx_mode, pc->t_fifo_mode, pc->bs_sm_sync_mode) ; 6761 } 6762 6763 if(pc->fc_rx_spd_intf == TEFMOD16_SPD_32G_FC || pc->fc_tx_spd_intf == TEFMOD_SPD_32G_FC) { 6764 if(pc->fc_mode == 1) { 6765 pc->t_fifo_mode = 0; 6766 pc->deskew_mode = 9; 6767 pc->bs_sm_sync_mode = 0; 6768 6769 printf("STATS_Info : tefmod16_check_status (4i) : pc->t_pma_btmx_mode %1x : pc->deskew_mode %1x : pc->bs_sync_en %1x : pc->bs_dist_mode %1x : pc->bs_btmx_mode %1x : pc->t_fifo_mode %1x : pc->bs_sm_sync_mode %1x\n\n", pc->t_pma_btmx_mode, pc->deskew_mode, pc->bs_sync_en, pc->bs_dist_mode, pc->bs_btmx_mode, pc->t_fifo_mode, pc->bs_sm_sync_mode) ; 6770 } 6771 } 6772 } 6773 6774 printf("\nSTATS_Info : tefmod16_check_status (5a) : pc->an_en %01x : pc->speed %02x : pc->an_fec_sel_override %01x : pc->cl91_en %01x : pc->an_fec %01x : pc->bam_cl74_fec %01x : pc->t_fec_enable %1x : pc->cl91_nofec %1x : pc->cl91_cl74 %1x\n", pc->an_en, pc->speed, pc->an_fec_sel_override, pc->cl91_en, pc->an_fec, pc->bam_cl74_fec, pc->t_fec_enable, pc->t_fec_enable, pc->cl91_nofec, pc->cl91_cl74) ; 6775 6776 printf("STATS_Info : tefmod16_check_status (5b) : pc->sc_mode %2d : pc->fc_mode %1x : pc->fc_rx_spd_intf %02d : pc->fc_tx_spd_intf %02d\n", pc->sc_mode, pc->fc_mode, pc->fc_rx_spd_intf, pc->fc_tx_spd_intf) ; 6777 6778 printf("STATS_Info : tefmod16_check_status (5c) : pc->t_pma_btmx_mode %1x : pc->deskew_mode %1x : pc->bs_sync_en %1x : pc->bs_dist_mode %1x : pc->bs_btmx_mode %1x : pc->t_fifo_mode %1x : pc->bs_sm_sync_mode %1x\n\n", pc->t_pma_btmx_mode, pc->deskew_mode, pc->bs_sync_en, pc->bs_dist_mode, pc->bs_btmx_mode, pc->t_fifo_mode, pc->bs_sm_sync_mode) ; 6779 6780 /* Read resolved speed */ 6781 6782 SC_X4_RSLVD_SPDr_CLR(SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEEDr_reg); 6783 PHYMOD_IF_ERR_RETURN(READ_SC_X4_RSLVD_SPDr(pc, &SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEEDr_reg)); 6784 6785 sc_stats_actual.num_lanes = SC_X4_RSLVD_SPDr_NUM_LANESf_GET(SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEEDr_reg); 6786 6787 actual_speed = SC_X4_RSLVD_SPDr_SPEEDf_GET(SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEEDr_reg); 6788 6789 6790 /* RESOLVED 0 */ 6791 /* cl72_en, scr_mode, os_mode, enc_mode, fifo_mode, HG2_en, t_pma_btmx_mode */ 6792 6793 PHYMOD_IF_ERR_RETURN(READ_SC_X4_RSLVD0r(pc, &SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0r_reg)); 6794 6795 sc_stats_actual.cl72_en = SC_X4_RSLVD0r_CL72_ENf_GET(SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0r_reg); 6796 sc_stats_actual.os_mode = SC_X4_RSLVD0r_OS_MODEf_GET(SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0r_reg); 6797 sc_stats_actual.t_fifo_mode = SC_X4_RSLVD0r_T_FIFO_MODEf_GET(SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0r_reg); 6798 sc_stats_actual.t_enc_mode = SC_X4_RSLVD0r_T_ENC_MODEf_GET(SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0r_reg); 6799 sc_stats_actual.t_HG2_ENABLE = SC_X4_RSLVD0r_T_HG2_ENABLEf_GET(SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0r_reg); 6800 sc_stats_actual.t_pma_btmx_mode = SC_X4_RSLVD0r_T_PMA_BTMX_MODEf_GET(SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0r_reg); 6801 sc_stats_actual.scr_mode = SC_X4_RSLVD0r_SCR_MODEf_GET(SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0r_reg); 6802 6803 /* RESOLVED 1 */ 6804 PHYMOD_IF_ERR_RETURN(READ_SC_X4_RSLVD1r(pc, &SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1r_reg)); 6805 sc_stats_actual.descr_mode = SC_X4_RSLVD1r_DESCR_MODEf_GET(SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1r_reg); 6806 sc_stats_actual.dec_tl_mode = SC_X4_RSLVD1r_DEC_TL_MODEf_GET(SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1r_reg); 6807 sc_stats_actual.deskew_mode = SC_X4_RSLVD1r_DESKEW_MODEf_GET(SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1r_reg); 6808 sc_stats_actual.dec_fsm_mode = SC_X4_RSLVD1r_DEC_FSM_MODEf_GET(SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1r_reg); 6809 #ifdef TSCF_GEN1 6810 sc_stats_actual.r_HG2_ENABLE = SC_X4_RSLVD1r_R_HG2_ENABLEf_GET(SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1r_reg); 6811 #endif 6812 sc_stats_actual.bs_sm_sync_mode = SC_X4_RSLVD1r_BS_SM_SYNC_MODEf_GET(SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1r_reg); 6813 sc_stats_actual.bs_sync_en = SC_X4_RSLVD1r_BS_SYNC_ENf_GET(SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1r_reg); 6814 sc_stats_actual.bs_dist_mode = SC_X4_RSLVD1r_BS_DIST_MODEf_GET(SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1r_reg); 6815 sc_stats_actual.bs_btmx_mode = SC_X4_RSLVD1r_BS_BTMX_MODEf_GET(SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1r_reg); 6816 6817 6818 /*RESOLVED 2 */ 6819 PHYMOD_IF_ERR_RETURN(READ_SC_X4_RSLVD2r(pc, &SC_X4_FINAL_CONFIG_STATUS_RESOLVED_2r_reg)); 6820 sc_stats_actual.clkcnt0 = SC_X4_RSLVD2r_CLOCKCNT0f_GET(SC_X4_FINAL_CONFIG_STATUS_RESOLVED_2r_reg); 6821 /*RESOLVED 3 */ 6822 PHYMOD_IF_ERR_RETURN(READ_SC_X4_RSLVD3r(pc, &SC_X4_FINAL_CONFIG_STATUS_RESOLVED_3r_reg)); 6823 sc_stats_actual.clkcnt1 = SC_X4_RSLVD3r_CLOCKCNT1f_GET(SC_X4_FINAL_CONFIG_STATUS_RESOLVED_3r_reg); 6824 /*RESOLVED 4 */ 6825 PHYMOD_IF_ERR_RETURN(READ_SC_X4_RSLVD4r(pc, &SC_X4_FINAL_CONFIG_STATUS_RESOLVED_4r_reg)); 6826 sc_stats_actual.lpcnt0 = SC_X4_RSLVD4r_LOOPCNT0f_GET(SC_X4_FINAL_CONFIG_STATUS_RESOLVED_4r_reg); 6827 sc_stats_actual.lpcnt1 = SC_X4_RSLVD4r_LOOPCNT1f_GET(SC_X4_FINAL_CONFIG_STATUS_RESOLVED_4r_reg); 6828 /*RESOLVED 5 */ 6829 PHYMOD_IF_ERR_RETURN(READ_SC_X4_RSLVD5r(pc, &SC_X4_FINAL_CONFIG_STATUS_RESOLVED_5r_reg)); 6830 sc_stats_actual.cgc = SC_X4_RSLVD5r_MAC_CREDITGENCNTf_GET(SC_X4_FINAL_CONFIG_STATUS_RESOLVED_5r_reg); 6831 6832 /*RESOVLED 7 */ 6833 #ifndef TSCF_GEN1 6834 PHYMOD_IF_ERR_RETURN(READ_SC_X4_RSLVD7r(pc, &SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7r_reg)); 6835 sc_stats_actual.r_HG2_ENABLE = SC_X4_RSLVD7r_R_HG2_ENABLEf_GET(SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7r_reg); 6836 #endif 6837 6838 /*RESOVLED 8 */ 6839 #ifndef TSCF_GEN1 6840 PHYMOD_IF_ERR_RETURN(READ_SC_X4_RSLVD8r(pc, &SC_X4_FINAL_CONFIG_STATUS_RESOLVED_8r_reg)); 6841 sc_stats_actual.USE_100G_AM0 = SC_X4_RSLVD8r_USE_100G_AM0f_GET(SC_X4_FINAL_CONFIG_STATUS_RESOLVED_8r_reg); 6842 sc_stats_actual.USE_100G_AM123 = SC_X4_RSLVD8r_USE_100G_AM123f_GET(SC_X4_FINAL_CONFIG_STATUS_RESOLVED_8r_reg); 6843 sc_stats_actual.ber_window_sel = SC_X4_RSLVD8r_BER_WINDOW_SELf_GET(SC_X4_FINAL_CONFIG_STATUS_RESOLVED_8r_reg); 6844 sc_stats_actual.ber_count_sel = SC_X4_RSLVD8r_BER_COUNT_SELf_GET(SC_X4_FINAL_CONFIG_STATUS_RESOLVED_8r_reg); 6845 sc_stats_actual.cl74_shcorrupt = SC_X4_RSLVD8r_CL74_SHCORRUPTf_GET(SC_X4_FINAL_CONFIG_STATUS_RESOLVED_8r_reg); 6846 sc_stats_actual.corrupt_6th_group = SC_X4_RSLVD8r_CORRUPT_6TH_GROUPf_GET(SC_X4_FINAL_CONFIG_STATUS_RESOLVED_8r_reg); 6847 sc_stats_actual.corrupt_2nd_group = SC_X4_RSLVD8r_CORRUPT_2ND_GROUPf_GET(SC_X4_FINAL_CONFIG_STATUS_RESOLVED_8r_reg); 6848 #endif 6849 6850 6851 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FEC_STSr(pc, &SC_X4_FINAL_CONFIG_STATUS_FEC_STATUSr_reg)); 6852 if(pc->an_hcd_fec || pc->t_fec_enable) { 6853 /* if(data != 3) {} */ 6854 if((SC_X4_FEC_STSr_T_FEC_ENABLEf_GET(SC_X4_FINAL_CONFIG_STATUS_FEC_STATUSr_reg) & 6855 SC_X4_FEC_STSr_R_FEC_ENABLEf_GET(SC_X4_FINAL_CONFIG_STATUS_FEC_STATUSr_reg)) != 1) { 6856 fail=1; 6857 } 6858 } 6859 6860 if(pc->cl91_en) { 6861 /* if(data != 0xc) {} */ 6862 #ifdef TSCF_GEN1 6863 if((SC_X4_FEC_STSr_T_CL91_FEC_ENABLEf_GET(SC_X4_FINAL_CONFIG_STATUS_FEC_STATUSr_reg) & 6864 SC_X4_FEC_STSr_R_CL91_FEC_ENABLEf_GET(SC_X4_FINAL_CONFIG_STATUS_FEC_STATUSr_reg)) != 1) { 6865 fail=1; 6866 } 6867 #endif 6868 } 6869 6870 if(pc->tx_higig2_oen == 0x1) { pc->t_HG2_ENABLE = pc->tx_higig2_en; } 6871 if(pc->rx_higig2_oen == 0x1) { pc->r_HG2_ENABLE = pc->rx_higig2_en; } 6872 6873 /* Compare actual vs expected stats */ 6874 6875 fail = 0; 6876 6877 #ifdef _DV_TB_ 6878 printf("SC_Info : tefmod16_cfg_seq.c : tefmod_check_status() : pc->spd_intf %02x : mapped_speed %02x : pc->speed %02x : actual_speed %02x\n", 6879 pc->spd_intf, mapped_speed, pc->speed, actual_speed); 6880 #endif 6881 6882 if(actual_speed != pc->speed) { 6883 printf("ACTUAL is %x and EXP is %x and SPDI is %x\n", actual_speed, pc->speed, pc->spd_intf); 6884 if(pc->verbosity) 6885 #ifdef _DV_TB_ 6886 PHYMOD_DEBUG_ERROR(("Act speed is %d and exp_speed is %d\n", actual_speed, pc->speed)); 6887 #endif 6888 fail=1; 6889 } else { 6890 #ifdef _DV_TB_ 6891 if(pc->verbosity) 6892 PHYMOD_DEBUG_ERROR(("speed %d executed correctly \n", actual_speed)); 6893 #endif 6894 } 6895 6896 /*Resolved 0 comparison */ 6897 if(sc_stats_actual.cl72_en != pc->cl72_en) fail=1; 6898 if(sc_stats_actual.os_mode != pc->os_mode) fail=1; 6899 if(sc_stats_actual.t_fifo_mode != pc->t_fifo_mode) fail=1; 6900 if(sc_stats_actual.t_enc_mode != pc->t_enc_mode) fail=1; 6901 if(sc_stats_actual.t_HG2_ENABLE != pc->t_HG2_ENABLE) fail=1; 6902 if(sc_stats_actual.t_pma_btmx_mode != pc->t_pma_btmx_mode) fail=1; 6903 if(sc_stats_actual.scr_mode != pc->scr_mode) fail=1; 6904 6905 /*Resolved 1 comparison */ 6906 if(sc_stats_actual.descr_mode != pc->descr_mode) fail=1; 6907 if(sc_stats_actual.dec_tl_mode != pc->dec_tl_mode) fail=1; 6908 if(sc_stats_actual.deskew_mode != pc->deskew_mode) fail=1; 6909 if(sc_stats_actual.dec_fsm_mode != pc->dec_fsm_mode) fail=1; 6910 if(sc_stats_actual.r_HG2_ENABLE != pc->r_HG2_ENABLE) fail=1; 6911 if(sc_stats_actual.bs_sm_sync_mode != pc->bs_sm_sync_mode) fail=1; 6912 if(sc_stats_actual.bs_sync_en != pc->bs_sync_en) fail=1; 6913 if(sc_stats_actual.bs_dist_mode != pc->bs_dist_mode) fail=1; 6914 if(sc_stats_actual.bs_btmx_mode != pc->bs_btmx_mode) fail=1; 6915 6916 6917 /*Resolved 2 comparison */ 6918 if(sc_stats_actual.clkcnt0 != pc->clkcnt0) fail=1; 6919 6920 /*Resolved 3 comparison */ 6921 if(sc_stats_actual.clkcnt1 != pc->clkcnt1) fail=1; 6922 6923 /*Resolved 4 comparison */ 6924 if(sc_stats_actual.lpcnt0 != pc->lpcnt0) fail=1; 6925 if(sc_stats_actual.lpcnt1 != pc->lpcnt1) fail=1; 6926 6927 /*Resolved 5 comparison */ 6928 if(sc_stats_actual.cgc != pc->cgc) fail=1; 6929 6930 6931 /*Resolved 8 comparison */ 6932 if(pc->speed == SC_X4_CONTROL_CONTROL_SPEED_S_25G_CR1 || pc->speed == SC_X4_CONTROL_CONTROL_SPEED_S_25G_KR1 || 6933 pc->speed == SC_X4_CONTROL_CONTROL_SPEED_S_25G_X1 || pc->speed == SC_X4_CONTROL_CONTROL_SPEED_S_25G_HG2_CR1 || 6934 pc->speed == SC_X4_CONTROL_CONTROL_SPEED_S_25G_HG2_KR1 || pc->speed == SC_X4_CONTROL_CONTROL_SPEED_S_25G_HG2_X1 ){ 6935 6936 pc->USE_100G_AM0 = pc->msa_25G_am0_mode ; 6937 pc->USE_100G_AM123 = pc->msa_25G_am123_mode ; 6938 pc->cl74_shcorrupt = pc->cl74_shcorrupt_25msa; 6939 pc->corrupt_6th_group = 0 ; 6940 pc->corrupt_2nd_group = 1 ; 6941 pc->ber_window_sel = pc->msa_window_sel ; 6942 pc->ber_count_sel = pc->msa_count_sel ; 6943 6944 if(sc_stats_actual.USE_100G_AM0 != pc->USE_100G_AM0) fail=1; 6945 if(sc_stats_actual.USE_100G_AM123 != pc->USE_100G_AM123) fail=1; 6946 if(sc_stats_actual.corrupt_6th_group != pc->corrupt_6th_group) fail=1; 6947 if(sc_stats_actual.corrupt_2nd_group != pc->corrupt_2nd_group) fail=1; 6948 if(sc_stats_actual.ber_window_sel != pc->ber_window_sel) fail=1; 6949 if(sc_stats_actual.ber_count_sel != pc->ber_count_sel) fail=1; 6950 } 6951 if(pc->speed == SC_X4_CONTROL_CONTROL_SPEED_S_25G_CR_IEEE || pc->speed == SC_X4_CONTROL_CONTROL_SPEED_S_25G_CRS_IEEE || 6952 pc->speed == SC_X4_CONTROL_CONTROL_SPEED_S_25G_KR_IEEE || pc->speed == SC_X4_CONTROL_CONTROL_SPEED_S_25G_KRS_IEEE) { 6953 6954 pc->USE_100G_AM0 = pc->ieee_25G_am0_mode ; 6955 pc->USE_100G_AM123 = pc->ieee_25G_am123_mode ; 6956 pc->cl74_shcorrupt = pc->cl74_shcorrupt_25ieee ; 6957 pc->corrupt_6th_group = 0 ; 6958 pc->corrupt_2nd_group = 1 ; 6959 pc->ber_window_sel = pc->ieee_window_sel ; 6960 pc->ber_count_sel = pc->ieee_count_sel ; 6961 6962 6963 if(sc_stats_actual.USE_100G_AM0 != pc->USE_100G_AM0) fail=1; 6964 if(sc_stats_actual.USE_100G_AM123 != pc->USE_100G_AM123) fail=1; 6965 if(sc_stats_actual.corrupt_6th_group != pc->corrupt_6th_group) fail=1; 6966 if(sc_stats_actual.corrupt_2nd_group != pc->corrupt_2nd_group) fail=1; 6967 if(sc_stats_actual.ber_window_sel != pc->ber_window_sel) fail=1; 6968 if(sc_stats_actual.ber_count_sel != pc->ber_count_sel) fail=1; 6969 } 6970 if(pc->speed == SC_X4_CONTROL_CONTROL_SPEED_S_50G_CR2 || pc->speed == SC_X4_CONTROL_CONTROL_SPEED_S_50G_KR2 || 6971 pc->speed == SC_X4_CONTROL_CONTROL_SPEED_S_50G_HG2_X2 || pc->speed == SC_X4_CONTROL_CONTROL_SPEED_S_50G_HG2_KR2 || 6972 pc->speed == SC_X4_CONTROL_CONTROL_SPEED_S_50G_X2 || pc->speed == SC_X4_CONTROL_CONTROL_SPEED_S_50G_HG2_CR2) { 6973 pc->USE_100G_AM0 = pc->msa_50G_am0_mode; 6974 pc->USE_100G_AM123 = pc->msa_50G_am123_mode; 6975 pc->cl74_shcorrupt = pc->cl74_shcorrupt_50msa; 6976 pc->corrupt_6th_group = 0 ; 6977 pc->corrupt_2nd_group = 1 ; 6978 pc->ber_window_sel = pc->msa_window_sel ; 6979 pc->ber_count_sel = pc->msa_count_sel ; 6980 6981 6982 if(sc_stats_actual.USE_100G_AM0 != pc->USE_100G_AM0) fail=1; 6983 if(sc_stats_actual.USE_100G_AM123 != pc->USE_100G_AM123) fail=1; 6984 if(sc_stats_actual.corrupt_6th_group != pc->corrupt_6th_group) fail=1; 6985 if(sc_stats_actual.corrupt_2nd_group != pc->corrupt_2nd_group) fail=1; 6986 if(sc_stats_actual.ber_window_sel != pc->ber_window_sel) fail=1; 6987 if(sc_stats_actual.ber_count_sel != pc->ber_count_sel) fail=1; 6988 } 6989 if(pc->speed == SC_X4_CONTROL_CONTROL_SPEED_S_100G_CR4 || pc->speed == SC_X4_CONTROL_CONTROL_SPEED_S_100G_KR4 || 6990 pc->speed == SC_X4_CONTROL_CONTROL_SPEED_S_100G_X4 || pc->speed == SC_X4_CONTROL_CONTROL_SPEED_S_100G_HG2_CR4 || 6991 pc->speed == SC_X4_CONTROL_CONTROL_SPEED_S_100G_HG2_KR4 || pc->speed == SC_X4_CONTROL_CONTROL_SPEED_S_100G_HG2_X4) { 6992 pc->corrupt_6th_group = 1 ; 6993 pc->corrupt_2nd_group = 0 ; 6994 if(sc_stats_actual.corrupt_6th_group != pc->corrupt_6th_group) fail=1; 6995 if(sc_stats_actual.corrupt_2nd_group != pc->corrupt_2nd_group) fail=1; 6996 6997 } 6998 6999 7000 /* pc-> = fail; */ 7001 if(fail == 1) { 7002 #ifdef _DV_TB_ 7003 PHYMOD_DEBUG_ERROR(("Actual stats\n")); 7004 sc_stats_print_actual = &sc_stats_actual; 7005 print_tefmod16_sc_lkup_table(sc_stats_print_actual); 7006 PHYMOD_DEBUG_ERROR(("Expected stats\n")); 7007 print_tefmod16_sc_lkup_table(pc); 7008 return PHYMOD_E_FAIL; 7009 #endif 7010 pc->sc_done = 0; 7011 } else { 7012 pc->sc_done=1; 7013 #ifdef _DV_TB_ 7014 PHYMOD_DEBUG_ERROR(("SC_DONE set\n")); 7015 if(pc->tefmod16_st_print==1) { 7016 print_tefmod16_st(pc); 7017 } 7018 return PHYMOD_E_NONE; 7019 #endif 7020 } 7021 } 7022 #endif 7023 7024 /*! 7025 @brief tefmod16_set_port_mode_sel , selects the port_mode, 7026 @returns The value PHYMOD_E_NONE upon successful completion. 7027 @details 7028 This is used when we are not using any speed control logic, but instead when bypassing this entire SC logic, this has to be programmed 7029 */ 7030 int tefmod16_set_port_mode_sel(PHYMOD_ST* pc, int tsc_touched, tefmod16_port_type_t port_type) 7031 { 7032 int port_mode_sel; 7033 uint16_t single_port_mode; 7034 MAIN0_SETUPr_t main0_reg; 7035 7036 TEFMOD16_DBG_IN_FUNC_INFO(pc); 7037 port_mode_sel = 0; 7038 if(tsc_touched == 1) 7039 single_port_mode = 0; 7040 else 7041 single_port_mode = 1; 7042 7043 switch(port_type) { 7044 case TEFMOD16_MULTI_PORT: port_mode_sel = 0; break; 7045 case TEFMOD16_TRI1_PORT: port_mode_sel = 2; break; 7046 case TEFMOD16_TRI2_PORT: port_mode_sel = 1; break; 7047 case TEFMOD16_DXGXS: port_mode_sel = 3; break; 7048 case TEFMOD16_SINGLE_PORT: port_mode_sel = 4; break; 7049 default: break; 7050 } 7051 MAIN0_SETUPr_CLR(main0_reg); 7052 MAIN0_SETUPr_PORT_MODE_SELf_SET(main0_reg, port_mode_sel); 7053 MAIN0_SETUPr_SINGLE_PORT_MODEf_SET(main0_reg, single_port_mode); 7054 PHYMOD_IF_ERR_RETURN(MODIFY_MAIN0_SETUPr(pc, main0_reg)); 7055 7056 return PHYMOD_E_NONE; 7057 } 7058 7059 /*! 7060 @brief firmware load request 7061 @param pc handle to current TSCF context (#PHYMOD_ST) 7062 @returns The value PHYMOD_E_NONE upon successful completion. 7063 @details 7064 */ 7065 int tefmod16_firmware_set(PHYMOD_ST* pc) 7066 { 7067 TEFMOD16_DBG_IN_FUNC_INFO(pc); 7068 return PHYMOD_E_NONE; 7069 } 7070 7071 #ifdef _SDK_TEFMOD16_ 7072 /*! 7073 @brief Controls the init setting/resetting of autoneg registers. 7074 @param pc handle to current TSCF context (#PHYMOD_ST) 7075 @param an_init_st structure tefmod16_an_init_t with all the one time autoneg init cfg. 7076 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 7077 @details Get aneg features via #tefmod16_an_init_t. 7078 This does not start the autoneg. That is done in tefmod16_autoneg_control 7079 */ 7080 int tefmod16_autoneg_set_init(PHYMOD_ST* pc, tefmod16_an_init_t *an_init_st) /* AUTONEG_SET */ 7081 { 7082 AN_X4_CL73_CTLSr_t AN_X4_CL73_CTLSr_t_reg; 7083 AN_X4_LD_BASE_ABIL1r_t AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg; 7084 AN_X4_LD_BASE_ABIL0r_t AN_X4_ABILITIES_LD_BASE_ABILITIES_0r_reg; 7085 AN_X4_CL73_CFGr_t AN_X4_CL73_CFGr_t_reg; 7086 7087 TEFMOD16_DBG_IN_FUNC_INFO(pc); 7088 AN_X4_CL73_CTLSr_CLR(AN_X4_CL73_CTLSr_t_reg); 7089 AN_X4_CL73_CTLSr_AN_GOOD_TRAPf_SET(AN_X4_CL73_CTLSr_t_reg, an_init_st->an_good_trap); 7090 AN_X4_CL73_CTLSr_AN_GOOD_CHECK_TRAPf_SET(AN_X4_CL73_CTLSr_t_reg, an_init_st->an_good_check_trap); 7091 AN_X4_CL73_CTLSr_LINKFAILTIMER_DISf_SET(AN_X4_CL73_CTLSr_t_reg, an_init_st->linkfailtimer_dis); 7092 AN_X4_CL73_CTLSr_LINKFAILTIMERQUAL_ENf_SET(AN_X4_CL73_CTLSr_t_reg, an_init_st->linkfailtimerqua_en); 7093 AN_X4_CL73_CTLSr_AN_FAIL_COUNT_LIMITf_SET(AN_X4_CL73_CTLSr_t_reg, an_init_st->an_fail_cnt); 7094 AN_X4_CL73_CTLSr_AN_OUI_OVERRIDE_BAM73_ADVf_SET(AN_X4_CL73_CTLSr_t_reg, an_init_st->bam73_adv_oui); 7095 AN_X4_CL73_CTLSr_AN_OUI_OVERRIDE_BAM73_DETf_SET(AN_X4_CL73_CTLSr_t_reg, an_init_st->bam73_det_oui); 7096 AN_X4_CL73_CTLSr_AN_OUI_OVERRIDE_HPAM_ADVf_SET(AN_X4_CL73_CTLSr_t_reg, an_init_st->hpam_adv_oui); 7097 AN_X4_CL73_CTLSr_AN_OUI_OVERRIDE_HPAM_DETf_SET(AN_X4_CL73_CTLSr_t_reg, an_init_st->hpam_det_oui); 7098 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_CL73_CTLSr(pc, AN_X4_CL73_CTLSr_t_reg)); 7099 7100 AN_X4_LD_BASE_ABIL1r_CLR(AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg); 7101 if(an_init_st->disable_rf_report == 1) { 7102 AN_X4_LD_BASE_ABIL1r_CL73_REMOTE_FAULTf_SET(AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg, 1); 7103 } 7104 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_LD_BASE_ABIL1r(pc, AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg)); 7105 7106 AN_X4_LD_BASE_ABIL0r_CLR(AN_X4_ABILITIES_LD_BASE_ABILITIES_0r_reg); 7107 AN_X4_LD_BASE_ABIL0r_TX_NONCEf_SET(AN_X4_ABILITIES_LD_BASE_ABILITIES_0r_reg, (an_init_st->cl73_transmit_nonce) & 0x1f); 7108 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_LD_BASE_ABIL0r(pc, AN_X4_ABILITIES_LD_BASE_ABILITIES_0r_reg)); 7109 7110 AN_X4_CL73_CFGr_CLR(AN_X4_CL73_CFGr_t_reg); 7111 AN_X4_CL73_CFGr_CL73_NONCE_MATCH_OVERf_SET(AN_X4_CL73_CFGr_t_reg, an_init_st->cl73_nonce_match_over); 7112 AN_X4_CL73_CFGr_CL73_NONCE_MATCH_VALf_SET(AN_X4_CL73_CFGr_t_reg, an_init_st->cl73_nonce_match_val); 7113 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_CL73_CFGr(pc, AN_X4_CL73_CFGr_t_reg)); 7114 7115 return PHYMOD_E_NONE; 7116 } 7117 #endif /* _SDK_TEFMOD16_ */ 7118 7119 #ifdef _SDK_TEFMOD16_ 7120 /*! 7121 @brief Controls the setting/resetting of autoneg timers. 7122 @param pc handle to current TSCF context (#PHYMOD_ST) 7123 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 7124 @details 7125 7126 */ 7127 int tefmod16_autoneg_timer_init(PHYMOD_ST* pc) /* AUTONEG timer set*/ 7128 { 7129 7130 AN_X1_IGNORE_LNK_TMRr_t AN_X1_IGNORE_LNK_TMRr_reg; 7131 AN_X1_CL73_DME_LOCKr_t AN_X1_TIMERS_CL73_DME_LOCKr_reg; 7132 AN_X1_PD_SD_TMRr_t AN_X1_TIMERS_PD_SD_TIMERr_reg; 7133 AN_X1_CL73_BRK_LNKr_t AN_X1_TIMERS_CL73_BREAK_LINKr_reg; 7134 AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72r_t AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_NOT_CL72r_reg; 7135 AN_X1_LNK_FAIL_INHBT_TMR_CL72r_t AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_CL72r_reg; 7136 7137 AN_X1_IGNORE_LNK_TMRr_SET(AN_X1_IGNORE_LNK_TMRr_reg, 0x29a ); 7138 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_IGNORE_LNK_TMRr(pc,AN_X1_IGNORE_LNK_TMRr_reg)); 7139 7140 AN_X1_CL73_DME_LOCKr_SET(AN_X1_TIMERS_CL73_DME_LOCKr_reg, 0x14d4); 7141 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_CL73_DME_LOCKr(pc, AN_X1_TIMERS_CL73_DME_LOCKr_reg)); 7142 7143 AN_X1_PD_SD_TMRr_SET(AN_X1_TIMERS_PD_SD_TIMERr_reg, 0xa6a); 7144 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_PD_SD_TMRr(pc, AN_X1_TIMERS_PD_SD_TIMERr_reg)); 7145 7146 AN_X1_CL73_BRK_LNKr_SET(AN_X1_TIMERS_CL73_BREAK_LINKr_reg, 0x10ed); 7147 PHYMOD_IF_ERR_RETURN (WRITE_AN_X1_CL73_BRK_LNKr(pc, AN_X1_TIMERS_CL73_BREAK_LINKr_reg)); 7148 7149 /* AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72r_SET(AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_NOT_CL72r_reg, 0xbb8); */ 7150 /* Change based on finding in eagle */ 7151 AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72r_SET(AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_NOT_CL72r_reg, 0x3080); 7152 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72r(pc, AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_NOT_CL72r_reg)); 7153 7154 AN_X1_LNK_FAIL_INHBT_TMR_CL72r_SET(AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_CL72r_reg, 0x8382); 7155 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_LNK_FAIL_INHBT_TMR_CL72r(pc, AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_CL72r_reg)); 7156 7157 return PHYMOD_E_NONE; 7158 } 7159 #endif /* _SDK_TEFMOD16_ */ 7160 7161 int tefmod16_toggle_sw_speed_change(PHYMOD_ST* pc) 7162 { 7163 int cnt; 7164 int sw_sp_cfg_vld; 7165 SC_X4_CTLr_t SC_X4_CTLr_reg; 7166 SC_X4_STSr_t SC_X4_STSr_reg; 7167 #ifdef TSCF_GEN1 7168 TX_X1_T_CL91_FECr_t TX_X1_T_CL91_FECr_reg; 7169 RX_X1_CL91_CFGr_t RX_X1_CL91_CFGr_reg; 7170 #endif 7171 7172 cnt=0; 7173 sw_sp_cfg_vld = 0; 7174 7175 #ifdef _DV_TB_ 7176 printf("Inside toggle_sw_speed_change\n"); 7177 #endif 7178 7179 #ifdef TSCF_GEN1 7180 TX_X1_T_CL91_FECr_CLR(TX_X1_T_CL91_FECr_reg); 7181 TX_X1_T_CL91_FECr_SET(TX_X1_T_CL91_FECr_reg, 0); 7182 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X1_T_CL91_FECr(pc, TX_X1_T_CL91_FECr_reg)); 7183 7184 RX_X1_CL91_CFGr_CLR(RX_X1_CL91_CFGr_reg); 7185 RX_X1_CL91_CFGr_RX_CL91_FEC_ENf_SET (RX_X1_CL91_CFGr_reg, 0); 7186 PHYMOD_IF_ERR_RETURN(MODIFY_RX_X1_CL91_CFGr(pc, RX_X1_CL91_CFGr_reg)); 7187 #endif 7188 7189 SC_X4_CTLr_CLR(SC_X4_CTLr_reg); 7190 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(SC_X4_CTLr_reg, 0); 7191 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_CTLr(pc, SC_X4_CTLr_reg)); 7192 7193 SC_X4_CTLr_CLR(SC_X4_CTLr_reg); 7194 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(SC_X4_CTLr_reg, 1); 7195 SC_X4_CTLr_SPEEDf_SET(SC_X4_CTLr_reg, 0); 7196 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_CTLr(pc, SC_X4_CTLr_reg)); 7197 7198 while (cnt <=2000) { 7199 SC_X4_STSr_CLR(SC_X4_STSr_reg); 7200 PHYMOD_IF_ERR_RETURN(READ_SC_X4_STSr(pc, &SC_X4_STSr_reg)); 7201 cnt = cnt + 1; 7202 if(SC_X4_STSr_SW_SPEED_CONFIG_VLDf_GET(SC_X4_STSr_reg)) { 7203 sw_sp_cfg_vld = 1; 7204 #ifdef _DV_TB_ 7205 printf("sw_speed_cfg_vld set uint :: %d :: lane :: %d\n",pc->unit, pc->this_lane); 7206 #endif 7207 break; 7208 } 7209 } 7210 7211 SC_X4_CTLr_CLR(SC_X4_CTLr_reg); 7212 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(SC_X4_CTLr_reg, 0); 7213 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_CTLr(pc, SC_X4_CTLr_reg)); 7214 7215 if(!sw_sp_cfg_vld) { 7216 return PHYMOD_E_FAIL; 7217 } 7218 return PHYMOD_E_NONE; 7219 } 7220 7221 #ifdef _SDK_TEFMOD16_ 7222 /** 7223 @brief To get autoneg control registers. 7224 @param pc handle to current TSCF context (#PHYMOD_ST) 7225 @param an_control reference to struct with autoneg parms #tefmod16_an_control_t 7226 @param an_complete status of AN completion 7227 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 7228 @details Upper layer software calls this function to get autoneg 7229 info. 7230 7231 <B>How to call:</B><br> 7232 <p>Call directly </p> 7233 */ 7234 int tefmod16_autoneg_control_get(PHYMOD_ST* pc, tefmod16_an_control_t *an_control, int *an_complete) 7235 { 7236 AN_X4_CL73_CFGr_t AN_X4_CL73_CFGr_reg; 7237 AN_X4_CL73_CTLSr_t AN_X4_CL73_CTLSr_reg; 7238 AN_X4_AN_MISC_STSr_t AN_X4_AN_MISC_STSr_reg; 7239 uint32_t msa_mode, base_ability,base_ability1; 7240 AN_X4_LD_BASE_ABIL3r_t AN_X4_LD_BASE_ABIL3r_reg; 7241 AN_X4_LD_BASE_ABIL4r_t AN_X4_LD_BASE_ABIL4r_reg; 7242 7243 TEFMOD16_DBG_IN_FUNC_INFO(pc); 7244 7245 /* CL73 AN MISC CONTROL 0xC1C6 */ 7246 PHYMOD_IF_ERR_RETURN(READ_AN_X4_CL73_CTLSr(pc, &AN_X4_CL73_CTLSr_reg)); 7247 an_control->pd_kx_en = AN_X4_CL73_CTLSr_PD_KX_ENf_GET(AN_X4_CL73_CTLSr_reg); 7248 7249 /* CL73 AN CONFIG 0xC1C0 */ 7250 PHYMOD_IF_ERR_RETURN(READ_AN_X4_CL73_CFGr(pc, &AN_X4_CL73_CFGr_reg)); 7251 if (AN_X4_CL73_CFGr_CL73_BAM_ENABLEf_GET(AN_X4_CL73_CFGr_reg) == 1) { 7252 PHYMOD_IF_ERR_RETURN(tefmod16_an_msa_mode_get(pc, &msa_mode)); 7253 7254 if (msa_mode) { 7255 /* 7256 * Read the msa_mode value. 7257 * If it is 1, it is a MSA/IEEE_MSA AN mode. 7258 * Read the base page values (abil_3 & abil4). 7259 * If it is set, then set AN mode to IEEE_MSA, else set it to MSA mode. 7260 */ 7261 7262 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LD_BASE_ABIL3r(pc, &AN_X4_LD_BASE_ABIL3r_reg)); 7263 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LD_BASE_ABIL4r(pc, &AN_X4_LD_BASE_ABIL4r_reg)); 7264 base_ability = AN_X4_LD_BASE_ABIL3r_GET(AN_X4_LD_BASE_ABIL3r_reg) & 0x0fff; 7265 base_ability1 = AN_X4_LD_BASE_ABIL4r_GET(AN_X4_LD_BASE_ABIL4r_reg) & 0x0fff; 7266 7267 if (!(base_ability) && !(base_ability1)) { 7268 an_control->an_type = TEFMOD16_AN_MODE_MSA; 7269 an_control->enable = 1; 7270 } else { 7271 an_control->an_type = TEFMOD16_AN_MODE_CL73_MSA; 7272 an_control->enable = 1; 7273 } 7274 } 7275 else { 7276 an_control->an_type = TEFMOD16_AN_MODE_CL73_BAM; 7277 an_control->enable = 1; 7278 } 7279 } else if (AN_X4_CL73_CFGr_CL73_HPAM_ENABLEf_GET(AN_X4_CL73_CFGr_reg) == 1) { 7280 an_control->an_type = TEFMOD16_AN_MODE_HPAM; 7281 an_control->enable = 1; 7282 } else if (AN_X4_CL73_CFGr_CL73_ENABLEf_GET(AN_X4_CL73_CFGr_reg) == 1) { 7283 an_control->an_type = TEFMOD16_AN_MODE_CL73; 7284 an_control->enable = 1; 7285 } else { 7286 an_control->an_type = TEFMOD16_AN_MODE_NONE; 7287 an_control->enable = 0; 7288 } 7289 7290 if(AN_X4_CL73_CFGr_AD_TO_CL73_ENf_GET(AN_X4_CL73_CFGr_reg) == 1) { 7291 an_control->an_property_type = TEFMOD16_AN_PROPERTY_ENABLE_HPAM_TO_CL73_AUTO; 7292 } else if(AN_X4_CL73_CFGr_BAM_TO_HPAM_AD_ENf_GET(AN_X4_CL73_CFGr_reg) == 1) { 7293 an_control->an_property_type = TEFMOD16_AN_PROPERTY_ENABLE_CL73_BAM_TO_HPAM_AUTO; 7294 } 7295 7296 an_control->num_lane_adv = AN_X4_CL73_CFGr_NUM_ADVERTISED_LANESf_GET(AN_X4_CL73_CFGr_reg); 7297 7298 /* an_complete status 0xC1E9 */ 7299 AN_X4_AN_MISC_STSr_CLR(AN_X4_AN_MISC_STSr_reg); 7300 PHYMOD_IF_ERR_RETURN (READ_AN_X4_AN_MISC_STSr(pc, &AN_X4_AN_MISC_STSr_reg)); 7301 *an_complete = AN_X4_AN_MISC_STSr_AN_COMPLETEf_GET(AN_X4_AN_MISC_STSr_reg); 7302 7303 return PHYMOD_E_NONE; 7304 7305 } 7306 #endif /* _SDK_TEFMOD16_ */ 7307 7308 #ifdef _SDK_TEFMOD16_ 7309 /** 7310 @brief To get local autoneg advertisement registers. 7311 @param pc handle to current TSCF context (#PHYMOD_ST) 7312 @param an_ability_st receives autoneg info. #tefmod16_an_adv_ability_t) 7313 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 7314 @details Upper layer software calls this function to get local autoneg 7315 info. This function is currently not implemented 7316 */ 7317 7318 int tefmod16_autoneg_local_ability_get(PHYMOD_ST* pc, tefmod16_an_adv_ability_t *an_ability_st) 7319 { 7320 AN_X4_LD_BASE_ABIL1r_t AN_X4_LD_BASE_ABIL1r_reg; 7321 AN_X4_LD_UP1_ABIL0r_t AN_X4_LD_UP1_ABIL0r_reg; 7322 AN_X4_LD_UP1_ABIL1r_t AN_X4_LD_UP1_ABIL1r_reg; 7323 AN_X4_LD_BASE_ABIL3r_t AN_X4_LD_BASE_ABIL3r_reg; 7324 AN_X4_LD_BASE_ABIL4r_t AN_X4_LD_BASE_ABIL4r_reg; 7325 AN_X4_LD_FEC_BASEPAGE_ABILr_t AN_X4_LD_FEC_BASEPAGE_ABILr_reg; 7326 int an_fec = 0; 7327 7328 TEFMOD16_DBG_IN_FUNC_INFO(pc); 7329 7330 /***** AN_X4_ABILITIES_ld_up0_abilities_1 0xC1C1 *******/ 7331 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LD_UP1_ABIL0r(pc, &AN_X4_LD_UP1_ABIL0r_reg)); 7332 an_ability_st->an_bam_speed = AN_X4_LD_UP1_ABIL0r_GET(AN_X4_LD_UP1_ABIL0r_reg) & 0x3ff; 7333 an_ability_st->an_hg2 = AN_X4_LD_UP1_ABIL0r_BAM_HG2f_GET(AN_X4_LD_UP1_ABIL0r_reg); 7334 7335 /***** AN_X4_ABILITIES_ld_up1_abilities_1 0xC1C2 *******/ 7336 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LD_UP1_ABIL1r(pc, &AN_X4_LD_UP1_ABIL1r_reg)); 7337 an_ability_st->an_bam_speed1 = AN_X4_LD_UP1_ABIL1r_GET(AN_X4_LD_UP1_ABIL1r_reg) & 0x1f; 7338 7339 /***** AN_X4_ABILITIES_ld_base_abilities_1 0xC1C4 *******/ 7340 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LD_BASE_ABIL1r(pc, &AN_X4_LD_BASE_ABIL1r_reg)); 7341 an_ability_st->an_base_speed = AN_X4_LD_BASE_ABIL1r_GET(AN_X4_LD_BASE_ABIL1r_reg) & 0x3f; 7342 an_ability_st->an_pause = AN_X4_LD_BASE_ABIL1r_CL73_PAUSEf_GET(AN_X4_LD_BASE_ABIL1r_reg); 7343 an_fec = AN_X4_LD_BASE_ABIL1r_FEC_REQf_GET(AN_X4_LD_BASE_ABIL1r_reg); 7344 7345 /***** AN_X4_ABILITIES_ld_base_abilities_3 0xC1C8 *******/ 7346 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LD_BASE_ABIL3r(pc, &AN_X4_LD_BASE_ABIL3r_reg)); 7347 if (AN_X4_LD_BASE_ABIL3r_BASE_25G_CR1_ENf_GET(AN_X4_LD_BASE_ABIL3r_reg)) { 7348 an_ability_st->an_base_speed |= (1 << TEFMOD16_CL73_25GBASE_CR1); 7349 } 7350 if (AN_X4_LD_BASE_ABIL3r_BASE_25G_KR1_ENf_GET(AN_X4_LD_BASE_ABIL3r_reg)) { 7351 an_ability_st->an_base_speed |= (1 << TEFMOD16_CL73_25GBASE_KR1); 7352 } 7353 7354 /***** AN_X4_ABILITIES_ld_base_abilities_4 0xC1C9 *******/ 7355 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LD_BASE_ABIL4r(pc, &AN_X4_LD_BASE_ABIL4r_reg)); 7356 if (AN_X4_LD_BASE_ABIL4r_BASE_25G_CRS1_ENf_GET(AN_X4_LD_BASE_ABIL4r_reg)) { 7357 an_ability_st->an_base_speed |= (1 << TEFMOD16_CL73_25GBASE_CRS1); 7358 } 7359 if (AN_X4_LD_BASE_ABIL4r_BASE_25G_KRS1_ENf_GET(AN_X4_LD_BASE_ABIL4r_reg)) { 7360 an_ability_st->an_base_speed |= (1 << TEFMOD16_CL73_25GBASE_KRS1); 7361 } 7362 7363 /***** AN_X4_ABILITIES_ld_fec_base_abilities 0xC1CA *******/ 7364 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LD_FEC_BASEPAGE_ABILr(pc, &AN_X4_LD_FEC_BASEPAGE_ABILr_reg)); 7365 7366 if (an_fec == 0x3) { 7367 if (AN_X4_LD_FEC_BASEPAGE_ABILr_RS_FEC_REQ_ENf_GET(AN_X4_LD_FEC_BASEPAGE_ABILr_reg)) { 7368 an_ability_st->an_fec = TEFMOD16_FEC_CL91_SUPRTD_REQSTD; 7369 } 7370 if (AN_X4_LD_FEC_BASEPAGE_ABILr_BASE_R_FEC_REQ_ENf_GET(AN_X4_LD_FEC_BASEPAGE_ABILr_reg)) { 7371 an_ability_st->an_fec = TEFMOD16_FEC_CL74_SUPRTD_REQSTD; 7372 } 7373 } else { 7374 an_ability_st->an_fec = (an_fec == 0x1) ? TEFMOD16_FEC_SUPRTD_NOT_REQSTD : TEFMOD16_FEC_NOT_SUPRTD; 7375 } 7376 7377 return PHYMOD_E_NONE; 7378 7379 } 7380 #endif /* _SDK_TEFMOD16_ */ 7381 7382 /** 7383 @brief Controls port RX squelch 7384 @param pc handle to current TSCE context (#PHYMOD_ST) 7385 @param enable is the control to RX squelch 7386 @returns The value PHYMOD_E_NONE upon successful completion. 7387 @details Controls port RX squelch 7388 */ 7389 int tefmod16_rx_squelch_set(PHYMOD_ST *pc, int enable) 7390 { 7391 SIGDET_CTL1r_t sigdet_ctl; 7392 7393 SIGDET_CTL1r_CLR(sigdet_ctl); 7394 READ_SIGDET_CTL1r(pc, &sigdet_ctl); 7395 7396 if(enable){ 7397 SIGDET_CTL1r_SIGNAL_DETECT_FRCf_SET(sigdet_ctl, 1); 7398 SIGDET_CTL1r_SIGNAL_DETECT_FRC_VALf_SET(sigdet_ctl, 0); 7399 } else { 7400 SIGDET_CTL1r_SIGNAL_DETECT_FRCf_SET(sigdet_ctl, 0); 7401 SIGDET_CTL1r_SIGNAL_DETECT_FRC_VALf_SET(sigdet_ctl, 0); 7402 } 7403 PHYMOD_IF_ERR_RETURN(MODIFY_SIGDET_CTL1r(pc, sigdet_ctl)); 7404 7405 return PHYMOD_E_NONE; 7406 } 7407 7408 /** 7409 @brief Controls port TX squelch 7410 @param pc handle to current TSCE context (#PHYMOD_ST) 7411 @param enable is the control to TX squelch 7412 @returns The value PHYMOD_E_NONE upon successful completion. 7413 @details Controls port TX squelch 7414 */ 7415 int tefmod16_tx_squelch_set(PHYMOD_ST *pc, int enable) 7416 { 7417 TXFIR_MISC_CTL0r_t tx_misc_ctl; 7418 7419 TXFIR_MISC_CTL0r_CLR(tx_misc_ctl); 7420 READ_TXFIR_MISC_CTL0r(pc, &tx_misc_ctl); 7421 7422 TXFIR_MISC_CTL0r_SDK_TX_DISABLEf_SET(tx_misc_ctl, enable); 7423 PHYMOD_IF_ERR_RETURN(MODIFY_TXFIR_MISC_CTL0r(pc, tx_misc_ctl)); 7424 7425 return PHYMOD_E_NONE; 7426 } 7427 7428 7429 /** 7430 @brief Controls port TX/RX squelch 7431 @param pc handle to current TSCE context (#PHYMOD_ST) 7432 @param enable is the control to TX/RX squelch. Enable=1 means enable the port,no squelch 7433 @returns The value PHYMOD_E_NONE upon successful completion. 7434 @details Controls port TX/RX squelch 7435 */ 7436 int tefmod16_port_enable_set(PHYMOD_ST *pc, int enable) 7437 { 7438 if (enable) { 7439 tefmod16_rx_squelch_set(pc, 0); 7440 tefmod16_tx_squelch_set(pc, 0); 7441 } else { 7442 tefmod16_rx_squelch_set(pc, 1); 7443 tefmod16_tx_squelch_set(pc, 1); 7444 } 7445 7446 return PHYMOD_E_NONE; 7447 } 7448 7449 /** 7450 @brief Get port TX squelch control settings 7451 @param pc handle to current TSCE context (#PHYMOD_ST) 7452 @param val Receiver for status of TX squelch 7453 @returns The value PHYMOD_E_NONE upon successful completion. 7454 @details Get port TX squelch control settings 7455 */ 7456 int tefmod16_tx_squelch_get(PHYMOD_ST *pc, int *val) 7457 { 7458 TXFIR_MISC_CTL0r_t tx_misc_ctl; 7459 7460 TXFIR_MISC_CTL0r_CLR(tx_misc_ctl); 7461 7462 PHYMOD_IF_ERR_RETURN(READ_TXFIR_MISC_CTL0r(pc, &tx_misc_ctl)); 7463 *val = TXFIR_MISC_CTL0r_SDK_TX_DISABLEf_GET(tx_misc_ctl); 7464 7465 return PHYMOD_E_NONE; 7466 } 7467 7468 /** 7469 @brief Gets port RX squelch settings 7470 @param pc handle to current TSCE context (#PHYMOD_ST) 7471 @param val Receiver for status of RX squelch 7472 @returns The value PHYMOD_E_NONE upon successful completion. 7473 @details Gets port RX squelch settings 7474 */ 7475 int tefmod16_rx_squelch_get(PHYMOD_ST *pc, int *val) 7476 { 7477 SIGDET_CTL1r_t sigdet_ctl; 7478 7479 SIGDET_CTL1r_CLR(sigdet_ctl); 7480 7481 PHYMOD_IF_ERR_RETURN(READ_SIGDET_CTL1r(pc, &sigdet_ctl)); 7482 *val = SIGDET_CTL1r_SIGNAL_DETECT_FRCf_GET(sigdet_ctl); 7483 7484 return PHYMOD_E_NONE; 7485 } 7486 7487 /** 7488 @brief Get port TX/RX squelch Settings 7489 @param pc handle to current TSCE context (#PHYMOD_ST) 7490 @param tx_enable - get the TX squelch settings 7491 @param rx_enable - get the RX squelch settings 7492 @returns The value PHYMOD_E_NONE upon successful completion. 7493 @details Controls port TX/RX squelch 7494 */ 7495 int tefmod16_port_enable_get(PHYMOD_ST *pc, int *tx_enable, int *rx_enable) 7496 { 7497 7498 tefmod16_rx_squelch_get(pc, rx_enable); 7499 tefmod16_tx_squelch_get(pc, tx_enable); 7500 7501 return PHYMOD_E_NONE; 7502 } 7503 7504 #ifdef _SDK_TEFMOD16_ 7505 /** 7506 @brief To get remote autoneg advertisement registers. 7507 @param pc handle to current TSCF context (#PHYMOD_ST) 7508 @param an_ability_st receives autoneg info. #tefmod16_an_adv_ability_t) 7509 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 7510 @details Upper layer software calls this function to get autoneg 7511 info. This function is not currently implemented. 7512 */ 7513 int tefmod16_autoneg_remote_ability_get(PHYMOD_ST* pc, tefmod16_an_adv_ability_t *an_ability_st) 7514 { 7515 uint32_t data; 7516 uint32_t user_code; 7517 AN_X4_LP_BASE1r_t AN_X4_LP_BASE1r_reg; 7518 AN_X4_LP_BASE3r_t AN_X4_LP_BASE3r_reg; 7519 7520 AN_X4_LP_OUI_UP3r_t AN_X4_LP_OUI_UP3r_reg; 7521 AN_X4_LP_OUI_UP4r_t AN_X4_LP_OUI_UP4r_reg; 7522 7523 TEFMOD16_DBG_IN_FUNC_INFO(pc); 7524 7525 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LP_BASE1r(pc, &AN_X4_LP_BASE1r_reg)); 7526 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LP_BASE3r(pc, &AN_X4_LP_BASE3r_reg)); 7527 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LP_OUI_UP3r(pc, &AN_X4_LP_OUI_UP3r_reg)); 7528 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LP_OUI_UP4r(pc, &AN_X4_LP_OUI_UP4r_reg)); 7529 7530 7531 /*an_ability_st->cl73_adv.an_bam_speed = 0xdead;*/ 7532 an_ability_st->an_bam_speed = 0x0; 7533 7534 user_code = (AN_X4_LP_OUI_UP3r_reg.v[0] & 0x1ff) << 11 ; 7535 7536 data = AN_X4_LP_OUI_UP4r_reg.v[0]; 7537 /* 0xc193 */ 7538 if(AN_X4_LP_OUI_UP4r_reg.v[0]&(1<<1)) { 7539 an_ability_st->an_bam_speed |=(1<<0) ; 7540 } else { 7541 user_code |= (AN_X4_LP_OUI_UP4r_reg.v[0] & 0x7ff) ; 7542 if(user_code == 0xabe20) 7543 an_ability_st->an_bam_speed |=(1<<0) ; 7544 } 7545 if(data&(1<<0)) an_ability_st->an_bam_speed |=(1<<1) ; 7546 7547 an_ability_st->an_pause = (AN_X4_LP_BASE1r_reg.v[0] >> 10 ) & 0x3;; 7548 an_ability_st->an_fec = (AN_X4_LP_BASE3r_reg.v[0] >> 14) & 0x3; 7549 7550 return PHYMOD_E_NONE; 7551 7552 } 7553 7554 7555 /** 7556 @brief Sets the field of the Soft Table 7557 @param pc handle to current TSCF context (#PHYMOD_ST) 7558 @param st_entry_no: The ST to write to(0..3) 7559 @param st_control_field,: The ST field to write to 7560 @param st_field_value: The ST value to write to the field 7561 returns The value PHYMOD_E_NONE upon successful completion. 7562 @details Sets the field of the Soft Table 7563 */ 7564 int tefmod16_st_control_field_set (PHYMOD_ST* pc,uint16_t st_entry_no, override_type_t st_control_field, uint16_t st_field_value) 7565 { 7566 SC_X1_SPD_OVRR0_SPDr_t SC_X1_SPD_OVRR0_SPDr_reg; 7567 SC_X1_SPD_OVRR1_SPDr_t SC_X1_SPD_OVRR1_SPDr_reg; 7568 SC_X1_SPD_OVRR2_SPDr_t SC_X1_SPD_OVRR2_SPDr_reg; 7569 SC_X1_SPD_OVRR3_SPDr_t SC_X1_SPD_OVRR3_SPDr_reg; 7570 7571 SC_X1_SPD_OVRR0_0r_t SC_X1_SPD_OVRR0_0r_reg; 7572 SC_X1_SPD_OVRR1_0r_t SC_X1_SPD_OVRR1_0r_reg; 7573 SC_X1_SPD_OVRR2_0r_t SC_X1_SPD_OVRR2_0r_reg; 7574 SC_X1_SPD_OVRR3_0r_t SC_X1_SPD_OVRR3_0r_reg; 7575 7576 SC_X1_SPD_OVRR0_1r_t SC_X1_SPD_OVRR0_1r_reg; 7577 SC_X1_SPD_OVRR1_1r_t SC_X1_SPD_OVRR1_1r_reg; 7578 SC_X1_SPD_OVRR2_1r_t SC_X1_SPD_OVRR2_1r_reg; 7579 SC_X1_SPD_OVRR3_1r_t SC_X1_SPD_OVRR3_1r_reg; 7580 7581 SC_X1_SPD_OVRR0_2r_t SC_X1_SPD_OVRR0_2r_reg; 7582 SC_X1_SPD_OVRR1_2r_t SC_X1_SPD_OVRR1_2r_reg; 7583 SC_X1_SPD_OVRR2_2r_t SC_X1_SPD_OVRR2_2r_reg; 7584 SC_X1_SPD_OVRR3_2r_t SC_X1_SPD_OVRR3_2r_reg; 7585 7586 SC_X1_SPD_OVRR0_3r_t SC_X1_SPD_OVRR0_3r_reg; 7587 SC_X1_SPD_OVRR1_3r_t SC_X1_SPD_OVRR1_3r_reg; 7588 SC_X1_SPD_OVRR2_3r_t SC_X1_SPD_OVRR2_3r_reg; 7589 SC_X1_SPD_OVRR3_3r_t SC_X1_SPD_OVRR3_3r_reg; 7590 7591 SC_X1_SPD_OVRR0_4r_t SC_X1_SPD_OVRR0_4r_reg; 7592 SC_X1_SPD_OVRR1_4r_t SC_X1_SPD_OVRR1_4r_reg; 7593 SC_X1_SPD_OVRR2_4r_t SC_X1_SPD_OVRR2_4r_reg; 7594 SC_X1_SPD_OVRR3_4r_t SC_X1_SPD_OVRR3_4r_reg; 7595 7596 SC_X1_SPD_OVRR0_5r_t SC_X1_SPD_OVRR0_5r_reg; 7597 SC_X1_SPD_OVRR1_5r_t SC_X1_SPD_OVRR1_5r_reg; 7598 SC_X1_SPD_OVRR2_5r_t SC_X1_SPD_OVRR2_5r_reg; 7599 SC_X1_SPD_OVRR3_5r_t SC_X1_SPD_OVRR3_5r_reg; 7600 7601 TEFMOD16_DBG_IN_FUNC_INFO(pc); 7602 7603 switch (st_entry_no){ 7604 case 0: 7605 SC_X1_SPD_OVRR0_SPDr_CLR(SC_X1_SPD_OVRR0_SPDr_reg); 7606 SC_X1_SPD_OVRR0_0r_CLR(SC_X1_SPD_OVRR0_0r_reg); 7607 SC_X1_SPD_OVRR0_1r_CLR(SC_X1_SPD_OVRR0_1r_reg); 7608 SC_X1_SPD_OVRR0_2r_CLR(SC_X1_SPD_OVRR0_2r_reg); 7609 SC_X1_SPD_OVRR0_3r_CLR(SC_X1_SPD_OVRR0_3r_reg); 7610 SC_X1_SPD_OVRR0_4r_CLR(SC_X1_SPD_OVRR0_4r_reg); 7611 SC_X1_SPD_OVRR0_5r_CLR(SC_X1_SPD_OVRR0_5r_reg); 7612 break; 7613 case 1: 7614 SC_X1_SPD_OVRR1_SPDr_CLR(SC_X1_SPD_OVRR1_SPDr_reg); 7615 SC_X1_SPD_OVRR1_0r_CLR(SC_X1_SPD_OVRR1_0r_reg); 7616 SC_X1_SPD_OVRR1_1r_CLR(SC_X1_SPD_OVRR1_1r_reg); 7617 SC_X1_SPD_OVRR1_2r_CLR(SC_X1_SPD_OVRR1_2r_reg); 7618 SC_X1_SPD_OVRR1_3r_CLR(SC_X1_SPD_OVRR1_3r_reg); 7619 SC_X1_SPD_OVRR1_4r_CLR(SC_X1_SPD_OVRR1_4r_reg); 7620 SC_X1_SPD_OVRR1_5r_CLR(SC_X1_SPD_OVRR1_5r_reg); 7621 break; 7622 case 2: 7623 SC_X1_SPD_OVRR2_SPDr_CLR(SC_X1_SPD_OVRR2_SPDr_reg); 7624 SC_X1_SPD_OVRR2_0r_CLR(SC_X1_SPD_OVRR2_0r_reg); 7625 SC_X1_SPD_OVRR2_1r_CLR(SC_X1_SPD_OVRR2_1r_reg); 7626 SC_X1_SPD_OVRR2_2r_CLR(SC_X1_SPD_OVRR2_2r_reg); 7627 SC_X1_SPD_OVRR2_3r_CLR(SC_X1_SPD_OVRR2_3r_reg); 7628 SC_X1_SPD_OVRR2_4r_CLR(SC_X1_SPD_OVRR2_4r_reg); 7629 SC_X1_SPD_OVRR2_5r_CLR(SC_X1_SPD_OVRR2_5r_reg); 7630 break; 7631 case 3: 7632 SC_X1_SPD_OVRR3_SPDr_CLR(SC_X1_SPD_OVRR3_SPDr_reg); 7633 SC_X1_SPD_OVRR3_0r_CLR(SC_X1_SPD_OVRR3_0r_reg); 7634 SC_X1_SPD_OVRR3_1r_CLR(SC_X1_SPD_OVRR3_1r_reg); 7635 SC_X1_SPD_OVRR3_2r_CLR(SC_X1_SPD_OVRR3_2r_reg); 7636 SC_X1_SPD_OVRR3_3r_CLR(SC_X1_SPD_OVRR3_3r_reg); 7637 SC_X1_SPD_OVRR3_4r_CLR(SC_X1_SPD_OVRR3_4r_reg); 7638 SC_X1_SPD_OVRR3_5r_CLR(SC_X1_SPD_OVRR3_5r_reg); 7639 break; 7640 } 7641 switch (st_entry_no){ 7642 case 0: 7643 switch (st_control_field){ 7644 case OVERRIDE_NUM_LANES: 7645 SC_X1_SPD_OVRR0_SPDr_NUM_LANESf_SET(SC_X1_SPD_OVRR0_SPDr_reg, st_field_value); 7646 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_SPDr(pc, SC_X1_SPD_OVRR0_SPDr_reg)); 7647 break; 7648 case OVERRIDE_OS_MODE: 7649 SC_X1_SPD_OVRR0_0r_OS_MODEf_SET(SC_X1_SPD_OVRR0_0r_reg, st_field_value); 7650 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_0r(pc, SC_X1_SPD_OVRR0_0r_reg)); 7651 break; 7652 case OVERRIDE_T_FIFO_MODE: 7653 SC_X1_SPD_OVRR0_0r_T_FIFO_MODEf_SET(SC_X1_SPD_OVRR0_0r_reg, st_field_value); 7654 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_0r(pc, SC_X1_SPD_OVRR0_0r_reg)); 7655 break; 7656 case OVERRIDE_T_ENC_MODE: 7657 SC_X1_SPD_OVRR0_0r_T_ENC_MODEf_SET(SC_X1_SPD_OVRR0_0r_reg, st_field_value); 7658 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_0r(pc, SC_X1_SPD_OVRR0_0r_reg)); 7659 break; 7660 case OVERRIDE_T_HG2_ENABLE: 7661 SC_X1_SPD_OVRR0_0r_T_HG2_ENABLEf_SET(SC_X1_SPD_OVRR0_0r_reg, st_field_value); 7662 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_0r(pc, SC_X1_SPD_OVRR0_0r_reg)); 7663 break; 7664 case OVERRIDE_SCR_MODE: 7665 SC_X1_SPD_OVRR0_0r_SCR_MODEf_SET(SC_X1_SPD_OVRR0_0r_reg, st_field_value); 7666 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_0r(pc, SC_X1_SPD_OVRR0_0r_reg)); 7667 break; 7668 case OVERRIDE_DESCR_MODE_OEN: 7669 SC_X1_SPD_OVRR0_1r_DESCR_MODEf_SET(SC_X1_SPD_OVRR0_1r_reg, st_field_value); 7670 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_1r(pc, SC_X1_SPD_OVRR0_1r_reg)); 7671 break; 7672 case OVERRIDE_DEC_TL_MODE: 7673 SC_X1_SPD_OVRR0_1r_DEC_TL_MODEf_SET(SC_X1_SPD_OVRR0_1r_reg, st_field_value); 7674 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_1r(pc, SC_X1_SPD_OVRR0_1r_reg)); 7675 break; 7676 case OVERRIDE_DESKEW_MODE: 7677 SC_X1_SPD_OVRR0_1r_DESKEW_MODEf_SET(SC_X1_SPD_OVRR0_1r_reg, st_field_value); 7678 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_1r(pc, SC_X1_SPD_OVRR0_1r_reg)); 7679 break; 7680 case OVERRIDE_DEC_FSM_MODE: 7681 SC_X1_SPD_OVRR0_1r_DEC_FSM_MODEf_SET(SC_X1_SPD_OVRR0_1r_reg, st_field_value); 7682 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_1r(pc, SC_X1_SPD_OVRR0_1r_reg)); 7683 break; 7684 case OVERRIDE_CL72_EN: 7685 SC_X1_SPD_OVRR0_0r_CL72_ENf_SET(SC_X1_SPD_OVRR0_0r_reg, st_field_value); 7686 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_0r(pc, SC_X1_SPD_OVRR0_0r_reg)); 7687 break; 7688 case OVERRIDE_CLOCKCNT0: 7689 SC_X1_SPD_OVRR0_2r_CLOCKCNT0f_SET(SC_X1_SPD_OVRR0_2r_reg, st_field_value); 7690 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_2r(pc, SC_X1_SPD_OVRR0_2r_reg)); 7691 break; 7692 case OVERRIDE_CLOCKCNT1: 7693 SC_X1_SPD_OVRR0_3r_CLOCKCNT1f_SET(SC_X1_SPD_OVRR0_3r_reg, st_field_value); 7694 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_3r(pc, SC_X1_SPD_OVRR0_3r_reg)); 7695 break; 7696 case OVERRIDE_LOOPCNT0: 7697 SC_X1_SPD_OVRR0_4r_LOOPCNT0f_SET(SC_X1_SPD_OVRR0_4r_reg, st_field_value); 7698 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_4r(pc, SC_X1_SPD_OVRR0_4r_reg)); 7699 break; 7700 case OVERRIDE_LOOPCNT1: 7701 SC_X1_SPD_OVRR0_4r_LOOPCNT1f_SET(SC_X1_SPD_OVRR0_4r_reg, st_field_value); 7702 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_4r(pc, SC_X1_SPD_OVRR0_4r_reg)); 7703 break; 7704 case OVERRIDE_MAC_CREDITGENCNT: 7705 SC_X1_SPD_OVRR0_5r_MAC_CREDITGENCNTf_SET(SC_X1_SPD_OVRR0_5r_reg, st_field_value); 7706 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_5r(pc, SC_X1_SPD_OVRR0_5r_reg)); 7707 break; 7708 default: 7709 return PHYMOD_E_FAIL; 7710 break; 7711 } 7712 break; 7713 case 1: 7714 switch (st_control_field){ 7715 case OVERRIDE_NUM_LANES: 7716 SC_X1_SPD_OVRR1_SPDr_NUM_LANESf_SET(SC_X1_SPD_OVRR1_SPDr_reg, st_field_value); 7717 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_SPDr(pc, SC_X1_SPD_OVRR1_SPDr_reg)); 7718 break; 7719 case OVERRIDE_OS_MODE: 7720 SC_X1_SPD_OVRR1_0r_OS_MODEf_SET(SC_X1_SPD_OVRR1_0r_reg, st_field_value); 7721 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_0r(pc, SC_X1_SPD_OVRR1_0r_reg)); 7722 break; 7723 case OVERRIDE_T_FIFO_MODE: 7724 SC_X1_SPD_OVRR1_0r_T_FIFO_MODEf_SET(SC_X1_SPD_OVRR1_0r_reg, st_field_value); 7725 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_0r(pc, SC_X1_SPD_OVRR1_0r_reg)); 7726 break; 7727 case OVERRIDE_T_ENC_MODE: 7728 SC_X1_SPD_OVRR1_0r_T_ENC_MODEf_SET(SC_X1_SPD_OVRR1_0r_reg, st_field_value); 7729 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_0r(pc, SC_X1_SPD_OVRR1_0r_reg)); 7730 break; 7731 case OVERRIDE_T_HG2_ENABLE: 7732 SC_X1_SPD_OVRR1_0r_T_HG2_ENABLEf_SET(SC_X1_SPD_OVRR1_0r_reg, st_field_value); 7733 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_0r(pc, SC_X1_SPD_OVRR1_0r_reg)); 7734 break; 7735 case OVERRIDE_SCR_MODE: 7736 SC_X1_SPD_OVRR1_0r_SCR_MODEf_SET(SC_X1_SPD_OVRR1_0r_reg, st_field_value); 7737 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_0r(pc, SC_X1_SPD_OVRR1_0r_reg)); 7738 break; 7739 case OVERRIDE_DESCR_MODE_OEN: 7740 SC_X1_SPD_OVRR1_1r_DESCR_MODEf_SET(SC_X1_SPD_OVRR1_1r_reg, st_field_value); 7741 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_1r(pc, SC_X1_SPD_OVRR1_1r_reg)); 7742 break; 7743 case OVERRIDE_DEC_TL_MODE: 7744 SC_X1_SPD_OVRR1_1r_DEC_TL_MODEf_SET(SC_X1_SPD_OVRR1_1r_reg, st_field_value); 7745 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_1r(pc, SC_X1_SPD_OVRR1_1r_reg)); 7746 break; 7747 case OVERRIDE_DESKEW_MODE: 7748 SC_X1_SPD_OVRR1_1r_DESKEW_MODEf_SET(SC_X1_SPD_OVRR1_1r_reg, st_field_value); 7749 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_1r(pc, SC_X1_SPD_OVRR1_1r_reg)); 7750 break; 7751 case OVERRIDE_DEC_FSM_MODE: 7752 SC_X1_SPD_OVRR1_1r_DEC_FSM_MODEf_SET(SC_X1_SPD_OVRR1_1r_reg, st_field_value); 7753 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_1r(pc, SC_X1_SPD_OVRR1_1r_reg)); 7754 break; 7755 case OVERRIDE_CL72_EN: 7756 SC_X1_SPD_OVRR1_0r_CL72_ENf_SET(SC_X1_SPD_OVRR1_0r_reg, st_field_value); 7757 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_0r(pc, SC_X1_SPD_OVRR1_0r_reg)); 7758 break; 7759 case OVERRIDE_CLOCKCNT0: 7760 SC_X1_SPD_OVRR1_2r_CLOCKCNT0f_SET(SC_X1_SPD_OVRR1_2r_reg, st_field_value); 7761 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_2r(pc, SC_X1_SPD_OVRR1_2r_reg)); 7762 break; 7763 case OVERRIDE_CLOCKCNT1: 7764 SC_X1_SPD_OVRR1_3r_CLOCKCNT1f_SET(SC_X1_SPD_OVRR1_3r_reg, st_field_value); 7765 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_3r(pc, SC_X1_SPD_OVRR1_3r_reg)); 7766 break; 7767 case OVERRIDE_LOOPCNT0: 7768 SC_X1_SPD_OVRR1_4r_LOOPCNT0f_SET(SC_X1_SPD_OVRR1_4r_reg, st_field_value); 7769 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_4r(pc, SC_X1_SPD_OVRR1_4r_reg)); 7770 break; 7771 case OVERRIDE_LOOPCNT1: 7772 SC_X1_SPD_OVRR1_4r_LOOPCNT1f_SET(SC_X1_SPD_OVRR1_4r_reg, st_field_value); 7773 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_4r(pc, SC_X1_SPD_OVRR1_4r_reg)); 7774 break; 7775 case OVERRIDE_MAC_CREDITGENCNT: 7776 SC_X1_SPD_OVRR1_5r_MAC_CREDITGENCNTf_SET(SC_X1_SPD_OVRR1_5r_reg, st_field_value); 7777 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_5r(pc, SC_X1_SPD_OVRR1_5r_reg)); 7778 break; 7779 default: 7780 return PHYMOD_E_FAIL; 7781 break; 7782 } 7783 break; 7784 case 2: 7785 switch (st_control_field){ 7786 case OVERRIDE_NUM_LANES: 7787 SC_X1_SPD_OVRR2_SPDr_NUM_LANESf_SET(SC_X1_SPD_OVRR2_SPDr_reg, st_field_value); 7788 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_SPDr(pc, SC_X1_SPD_OVRR2_SPDr_reg)); 7789 break; 7790 case OVERRIDE_OS_MODE: 7791 SC_X1_SPD_OVRR2_0r_OS_MODEf_SET(SC_X1_SPD_OVRR2_0r_reg, st_field_value); 7792 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_0r(pc, SC_X1_SPD_OVRR2_0r_reg)); 7793 break; 7794 case OVERRIDE_T_FIFO_MODE: 7795 SC_X1_SPD_OVRR2_0r_T_FIFO_MODEf_SET(SC_X1_SPD_OVRR2_0r_reg, st_field_value); 7796 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_0r(pc, SC_X1_SPD_OVRR2_0r_reg)); 7797 break; 7798 case OVERRIDE_T_ENC_MODE: 7799 SC_X1_SPD_OVRR2_0r_T_ENC_MODEf_SET(SC_X1_SPD_OVRR2_0r_reg, st_field_value); 7800 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_0r(pc, SC_X1_SPD_OVRR2_0r_reg)); 7801 break; 7802 case OVERRIDE_T_HG2_ENABLE: 7803 SC_X1_SPD_OVRR2_0r_T_HG2_ENABLEf_SET(SC_X1_SPD_OVRR2_0r_reg, st_field_value); 7804 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_0r(pc, SC_X1_SPD_OVRR2_0r_reg)); 7805 break; 7806 case OVERRIDE_SCR_MODE: 7807 SC_X1_SPD_OVRR2_0r_SCR_MODEf_SET(SC_X1_SPD_OVRR2_0r_reg, st_field_value); 7808 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_0r(pc, SC_X1_SPD_OVRR2_0r_reg)); 7809 break; 7810 case OVERRIDE_DESCR_MODE_OEN: 7811 SC_X1_SPD_OVRR2_1r_DESCR_MODEf_SET(SC_X1_SPD_OVRR2_1r_reg, st_field_value); 7812 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_1r(pc, SC_X1_SPD_OVRR2_1r_reg)); 7813 break; 7814 case OVERRIDE_DEC_TL_MODE: 7815 SC_X1_SPD_OVRR2_1r_DEC_TL_MODEf_SET(SC_X1_SPD_OVRR2_1r_reg, st_field_value); 7816 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_1r(pc, SC_X1_SPD_OVRR2_1r_reg)); 7817 break; 7818 case OVERRIDE_DESKEW_MODE: 7819 SC_X1_SPD_OVRR2_1r_DESKEW_MODEf_SET(SC_X1_SPD_OVRR2_1r_reg, st_field_value); 7820 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_1r(pc, SC_X1_SPD_OVRR2_1r_reg)); 7821 break; 7822 case OVERRIDE_DEC_FSM_MODE: 7823 SC_X1_SPD_OVRR2_1r_DEC_FSM_MODEf_SET(SC_X1_SPD_OVRR2_1r_reg, st_field_value); 7824 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_1r(pc, SC_X1_SPD_OVRR2_1r_reg)); 7825 break; 7826 case OVERRIDE_CL72_EN: 7827 SC_X1_SPD_OVRR2_0r_CL72_ENf_SET(SC_X1_SPD_OVRR2_0r_reg, st_field_value); 7828 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_0r(pc, SC_X1_SPD_OVRR2_0r_reg)); 7829 break; 7830 case OVERRIDE_CLOCKCNT0: 7831 SC_X1_SPD_OVRR2_2r_CLOCKCNT0f_SET(SC_X1_SPD_OVRR2_2r_reg, st_field_value); 7832 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_2r(pc, SC_X1_SPD_OVRR2_2r_reg)); 7833 break; 7834 case OVERRIDE_CLOCKCNT1: 7835 SC_X1_SPD_OVRR2_3r_CLOCKCNT1f_SET(SC_X1_SPD_OVRR2_3r_reg, st_field_value); 7836 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_3r(pc, SC_X1_SPD_OVRR2_3r_reg)); 7837 break; 7838 case OVERRIDE_LOOPCNT0: 7839 SC_X1_SPD_OVRR2_4r_LOOPCNT0f_SET(SC_X1_SPD_OVRR2_4r_reg, st_field_value); 7840 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_4r(pc, SC_X1_SPD_OVRR2_4r_reg)); 7841 break; 7842 case OVERRIDE_LOOPCNT1: 7843 SC_X1_SPD_OVRR2_4r_LOOPCNT1f_SET(SC_X1_SPD_OVRR2_4r_reg, st_field_value); 7844 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_4r(pc, SC_X1_SPD_OVRR2_4r_reg)); 7845 break; 7846 case OVERRIDE_MAC_CREDITGENCNT: 7847 SC_X1_SPD_OVRR2_5r_MAC_CREDITGENCNTf_SET(SC_X1_SPD_OVRR2_5r_reg, st_field_value); 7848 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_5r(pc, SC_X1_SPD_OVRR2_5r_reg)); 7849 break; 7850 default: 7851 return PHYMOD_E_FAIL; 7852 break; 7853 } 7854 break; 7855 case 3: 7856 switch (st_control_field){ 7857 case OVERRIDE_NUM_LANES: 7858 SC_X1_SPD_OVRR3_SPDr_NUM_LANESf_SET(SC_X1_SPD_OVRR3_SPDr_reg, st_field_value); 7859 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_SPDr(pc, SC_X1_SPD_OVRR3_SPDr_reg)); 7860 break; 7861 case OVERRIDE_OS_MODE: 7862 SC_X1_SPD_OVRR3_0r_OS_MODEf_SET(SC_X1_SPD_OVRR3_0r_reg, st_field_value); 7863 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_0r(pc, SC_X1_SPD_OVRR3_0r_reg)); 7864 break; 7865 case OVERRIDE_T_FIFO_MODE: 7866 SC_X1_SPD_OVRR3_0r_T_FIFO_MODEf_SET(SC_X1_SPD_OVRR3_0r_reg, st_field_value); 7867 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_0r(pc, SC_X1_SPD_OVRR3_0r_reg)); 7868 break; 7869 case OVERRIDE_T_ENC_MODE: 7870 SC_X1_SPD_OVRR3_0r_T_ENC_MODEf_SET(SC_X1_SPD_OVRR3_0r_reg, st_field_value); 7871 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_0r(pc, SC_X1_SPD_OVRR3_0r_reg)); 7872 break; 7873 case OVERRIDE_T_HG2_ENABLE: 7874 SC_X1_SPD_OVRR3_0r_T_HG2_ENABLEf_SET(SC_X1_SPD_OVRR3_0r_reg, st_field_value); 7875 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_0r(pc, SC_X1_SPD_OVRR3_0r_reg)); 7876 break; 7877 case OVERRIDE_SCR_MODE: 7878 SC_X1_SPD_OVRR3_0r_SCR_MODEf_SET(SC_X1_SPD_OVRR3_0r_reg, st_field_value); 7879 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_0r(pc, SC_X1_SPD_OVRR3_0r_reg)); 7880 break; 7881 case OVERRIDE_DESCR_MODE_OEN: 7882 SC_X1_SPD_OVRR3_1r_DESCR_MODEf_SET(SC_X1_SPD_OVRR3_1r_reg, st_field_value); 7883 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_1r(pc, SC_X1_SPD_OVRR3_1r_reg)); 7884 break; 7885 case OVERRIDE_DEC_TL_MODE: 7886 SC_X1_SPD_OVRR3_1r_DEC_TL_MODEf_SET(SC_X1_SPD_OVRR3_1r_reg, st_field_value); 7887 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_1r(pc, SC_X1_SPD_OVRR3_1r_reg)); 7888 break; 7889 case OVERRIDE_DESKEW_MODE: 7890 SC_X1_SPD_OVRR3_1r_DESKEW_MODEf_SET(SC_X1_SPD_OVRR3_1r_reg, st_field_value); 7891 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_1r(pc, SC_X1_SPD_OVRR3_1r_reg)); 7892 break; 7893 case OVERRIDE_DEC_FSM_MODE: 7894 SC_X1_SPD_OVRR3_1r_DEC_FSM_MODEf_SET(SC_X1_SPD_OVRR3_1r_reg, st_field_value); 7895 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_1r(pc, SC_X1_SPD_OVRR3_1r_reg)); 7896 break; 7897 case OVERRIDE_CL72_EN: 7898 SC_X1_SPD_OVRR3_0r_CL72_ENf_SET(SC_X1_SPD_OVRR3_0r_reg, st_field_value); 7899 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_0r(pc, SC_X1_SPD_OVRR3_0r_reg)); 7900 break; 7901 case OVERRIDE_CLOCKCNT0: 7902 SC_X1_SPD_OVRR3_2r_CLOCKCNT0f_SET(SC_X1_SPD_OVRR3_2r_reg, st_field_value); 7903 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_2r(pc, SC_X1_SPD_OVRR3_2r_reg)); 7904 break; 7905 case OVERRIDE_CLOCKCNT1: 7906 SC_X1_SPD_OVRR3_3r_CLOCKCNT1f_SET(SC_X1_SPD_OVRR3_3r_reg, st_field_value); 7907 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_3r(pc, SC_X1_SPD_OVRR3_3r_reg)); 7908 break; 7909 case OVERRIDE_LOOPCNT0: 7910 SC_X1_SPD_OVRR3_4r_LOOPCNT0f_SET(SC_X1_SPD_OVRR3_4r_reg, st_field_value); 7911 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_4r(pc, SC_X1_SPD_OVRR3_4r_reg)); 7912 break; 7913 case OVERRIDE_LOOPCNT1: 7914 SC_X1_SPD_OVRR3_4r_LOOPCNT1f_SET(SC_X1_SPD_OVRR3_4r_reg, st_field_value); 7915 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_4r(pc, SC_X1_SPD_OVRR3_4r_reg)); 7916 break; 7917 case OVERRIDE_MAC_CREDITGENCNT: 7918 SC_X1_SPD_OVRR3_5r_MAC_CREDITGENCNTf_SET(SC_X1_SPD_OVRR3_5r_reg, st_field_value); 7919 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_5r(pc, SC_X1_SPD_OVRR3_5r_reg)); 7920 break; 7921 default: 7922 return PHYMOD_E_FAIL; 7923 break; 7924 } 7925 break; 7926 } 7927 return PHYMOD_E_NONE; 7928 } 7929 7930 /** 7931 @brief EEE Control Set 7932 @param pc handle to current TSCF context (#PHYMOD_ST) 7933 @param enable EEE control(enable/disable) 7934 @returns The value PHYMOD_E_NONE upon successful completion 7935 @details EEE Control 7936 enable =1 : Allow LPI pass through. i.e. dont convert LPI. 7937 enable =0 : Convert LPI to idle. So MAC will not see it. 7938 7939 */ 7940 int tefmod16_eee_control_set(PHYMOD_ST* pc, uint32_t enable) 7941 { 7942 RX_X4_PCS_CTL0r_t reg_pcs_ctrl0; 7943 7944 TEFMOD16_DBG_IN_FUNC_INFO(pc); 7945 RX_X4_PCS_CTL0r_CLR(reg_pcs_ctrl0); 7946 READ_RX_X4_PCS_CTL0r(pc, ®_pcs_ctrl0); 7947 7948 RX_X4_PCS_CTL0r_LPI_ENABLEf_SET(reg_pcs_ctrl0, enable & 0x1); 7949 PHYMOD_IF_ERR_RETURN (MODIFY_RX_X4_PCS_CTL0r(pc, reg_pcs_ctrl0)); 7950 return PHYMOD_E_NONE; 7951 } 7952 7953 /** 7954 @brief EEE Control Get 7955 @param pc handle to current TSCF context (#PHYMOD_ST) 7956 @param enable handle to receive EEE control 7957 @returns The value PHYMOD_E_NONE upon successful completion 7958 @details EEE Control 7959 enable =1 : Allow LPI pass through. i.e. dont convert LPI. 7960 enable =0 : Convert LPI to idle. So MAC will not see it. 7961 7962 */ 7963 int tefmod16_eee_control_get(PHYMOD_ST* pc, uint32_t *enable) 7964 { 7965 RX_X4_PCS_CTL0r_t reg_pcs_ctrl0; 7966 7967 TEFMOD16_DBG_IN_FUNC_INFO(pc); 7968 RX_X4_PCS_CTL0r_CLR(reg_pcs_ctrl0); 7969 7970 PHYMOD_IF_ERR_RETURN (READ_RX_X4_PCS_CTL0r(pc, ®_pcs_ctrl0)); 7971 *enable = RX_X4_PCS_CTL0r_LPI_ENABLEf_GET(reg_pcs_ctrl0); 7972 return PHYMOD_E_NONE; 7973 } 7974 7975 /** 7976 @brief Setup the default for cl74 to ieee compliance 7977 @param pc handle to current TSCE context (#PHYMOD_ST) 7978 @returns The value PHYMOD_E_NONE upon successful completion 7979 @details cl74 control set to ieee compliance 7980 */ 7981 int tefmod16_cl74_chng_default (PHYMOD_ST* pc) 7982 { 7983 RX_X4_FEC1r_t RX_X4_FEC1reg; 7984 phymod_access_t pa_copy; 7985 int i; 7986 7987 TEFMOD16_DBG_IN_FUNC_INFO(pc); 7988 7989 PHYMOD_MEMCPY(&pa_copy, pc, sizeof(pa_copy)); 7990 RX_X4_FEC1r_CLR(RX_X4_FEC1reg); 7991 7992 for (i = 0; i <4; i++) { 7993 pa_copy.lane_mask = 0x1 << i; 7994 PHYMOD_IF_ERR_RETURN(WRITE_RX_X4_FEC1r(&pa_copy, RX_X4_FEC1reg)); 7995 } 7996 return PHYMOD_E_NONE; 7997 } 7998 7999 int tefmod16_an_msa_mode_set(PHYMOD_ST* pc, uint32_t val) 8000 { 8001 8002 AN_X4_LD_PAGE0r_t AN_X4_LD_PAGE0r_reg; 8003 TEFMOD16_DBG_IN_FUNC_INFO(pc); 8004 AN_X4_LD_PAGE0r_CLR(AN_X4_LD_PAGE0r_reg); 8005 AN_X4_LD_PAGE0r_SET(AN_X4_LD_PAGE0r_reg, val & 0x1); 8006 8007 /********Setting AN_X4_LD_PAGE0r_t 0xc1e2*****/ 8008 PHYMOD_IF_ERR_RETURN(WRITE_AN_X4_LD_PAGE0r(pc, AN_X4_LD_PAGE0r_reg)); 8009 8010 return PHYMOD_E_NONE; 8011 } 8012 8013 int tefmod16_an_msa_mode_get(PHYMOD_ST* pc, uint32_t* val) 8014 { 8015 8016 AN_X4_LD_PAGE0r_t AN_X4_LD_PAGE0r_reg; 8017 TEFMOD16_DBG_IN_FUNC_INFO(pc); 8018 AN_X4_LD_PAGE0r_CLR(AN_X4_LD_PAGE0r_reg); 8019 /********Getting AN_X4_LD_PAGE0r_t 0xc1e2*****/ 8020 PHYMOD_IF_ERR_RETURN (READ_AN_X4_LD_PAGE0r(pc, &AN_X4_LD_PAGE0r_reg)); 8021 *val = AN_X4_LD_PAGE0r_LD_PAGE_0f_GET(AN_X4_LD_PAGE0r_reg); 8022 return PHYMOD_E_NONE; 8023 } 8024 8025 int tefmod16_an_oui_set(PHYMOD_ST* pc, tefmod16_an_oui_t oui) 8026 { 8027 8028 AN_X1_OUI_LWRr_t AN_X1_CONTROL_OUI_LOWERr_reg; 8029 AN_X1_OUI_UPRr_t AN_X1_CONTROL_OUI_UPPERr_reg; 8030 AN_X4_CL73_CTLSr_t AN_X4_CL73_CTLSr_t_reg; 8031 8032 TEFMOD16_DBG_IN_FUNC_INFO(pc); 8033 8034 /********Setting AN X1 OUI LOWER 16 BITS 0x9241*****/ 8035 AN_X1_OUI_LWRr_CLR(AN_X1_CONTROL_OUI_LOWERr_reg); 8036 AN_X1_OUI_LWRr_SET(AN_X1_CONTROL_OUI_LOWERr_reg, oui.oui & 0xffff); 8037 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_OUI_LWRr(pc, AN_X1_CONTROL_OUI_LOWERr_reg)); 8038 8039 /********Setting AN X1 OUI UPPER 8 BITS 0x9240*****/ 8040 AN_X1_OUI_UPRr_CLR(AN_X1_CONTROL_OUI_UPPERr_reg); 8041 AN_X1_OUI_UPRr_SET(AN_X1_CONTROL_OUI_UPPERr_reg, (oui.oui >> 16) & 0xff); 8042 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_OUI_UPRr(pc, AN_X1_CONTROL_OUI_UPPERr_reg)); 8043 8044 /********CL73 AN MISC CONTROL 0xC1C6*****/ 8045 AN_X4_CL73_CTLSr_CLR(AN_X4_CL73_CTLSr_t_reg); 8046 AN_X4_CL73_CTLSr_AN_OUI_OVERRIDE_BAM73_ADVf_SET(AN_X4_CL73_CTLSr_t_reg, oui.oui_override_bam73_adv); 8047 AN_X4_CL73_CTLSr_AN_OUI_OVERRIDE_BAM73_DETf_SET(AN_X4_CL73_CTLSr_t_reg, oui.oui_override_bam73_det); 8048 AN_X4_CL73_CTLSr_AN_OUI_OVERRIDE_HPAM_ADVf_SET(AN_X4_CL73_CTLSr_t_reg, oui.oui_override_hpam_adv); 8049 AN_X4_CL73_CTLSr_AN_OUI_OVERRIDE_HPAM_DETf_SET(AN_X4_CL73_CTLSr_t_reg, oui.oui_override_hpam_det); 8050 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_CL73_CTLSr(pc, AN_X4_CL73_CTLSr_t_reg)); 8051 8052 return PHYMOD_E_NONE; 8053 } 8054 8055 int tefmod16_an_oui_get(PHYMOD_ST* pc, tefmod16_an_oui_t* oui) 8056 { 8057 8058 AN_X1_OUI_LWRr_t AN_X1_CONTROL_OUI_LOWERr_reg; 8059 AN_X1_OUI_UPRr_t AN_X1_CONTROL_OUI_UPPERr_reg; 8060 AN_X4_CL73_CTLSr_t AN_X4_CL73_CTLSr_t_reg; 8061 8062 TEFMOD16_DBG_IN_FUNC_INFO(pc); 8063 8064 /********Setting AN X1 OUI LOWER 16 BITS 0x9241*****/ 8065 PHYMOD_IF_ERR_RETURN(READ_AN_X1_OUI_LWRr(pc, &AN_X1_CONTROL_OUI_LOWERr_reg)); 8066 /********Setting AN X1 OUI UPPER 8 BITS 0x9240*****/ 8067 PHYMOD_IF_ERR_RETURN(READ_AN_X1_OUI_UPRr(pc, &AN_X1_CONTROL_OUI_UPPERr_reg)); 8068 /********CL73 AN MISC CONTROL 0xC1C6*****/ 8069 PHYMOD_IF_ERR_RETURN(READ_AN_X4_CL73_CTLSr(pc, &AN_X4_CL73_CTLSr_t_reg)); 8070 8071 oui->oui = AN_X1_OUI_LWRr_GET(AN_X1_CONTROL_OUI_LOWERr_reg); 8072 oui->oui |= ((AN_X1_OUI_UPRr_GET(AN_X1_CONTROL_OUI_UPPERr_reg)) << 16); 8073 8074 oui->oui_override_bam73_adv = AN_X4_CL73_CTLSr_AN_OUI_OVERRIDE_BAM73_ADVf_GET(AN_X4_CL73_CTLSr_t_reg); 8075 oui->oui_override_bam73_det = AN_X4_CL73_CTLSr_AN_OUI_OVERRIDE_BAM73_DETf_GET(AN_X4_CL73_CTLSr_t_reg); 8076 oui->oui_override_hpam_adv = AN_X4_CL73_CTLSr_AN_OUI_OVERRIDE_HPAM_ADVf_GET(AN_X4_CL73_CTLSr_t_reg); 8077 oui->oui_override_hpam_det = AN_X4_CL73_CTLSr_AN_OUI_OVERRIDE_HPAM_DETf_GET(AN_X4_CL73_CTLSr_t_reg); 8078 8079 return PHYMOD_E_NONE; 8080 } 8081 8082 int tefmod16_autoneg_status_get(PHYMOD_ST* pc, int *an_en, int *an_done) 8083 { 8084 AN_X4_CL73_CFGr_t AN_X4_CL73_CFGr_reg; 8085 AN_X4_AN_MISC_STSr_t AN_X4_AN_MISC_STSr_reg; 8086 8087 AN_X4_CL73_CFGr_CLR(AN_X4_CL73_CFGr_reg); 8088 AN_X4_AN_MISC_STSr_CLR(AN_X4_AN_MISC_STSr_reg); 8089 8090 PHYMOD_IF_ERR_RETURN (READ_AN_X4_CL73_CFGr(pc, &AN_X4_CL73_CFGr_reg)); 8091 PHYMOD_IF_ERR_RETURN (READ_AN_X4_AN_MISC_STSr(pc, &AN_X4_AN_MISC_STSr_reg)); 8092 8093 *an_en = AN_X4_CL73_CFGr_CL73_AN_RESTARTf_GET(AN_X4_CL73_CFGr_reg); 8094 *an_done = AN_X4_AN_MISC_STSr_AN_COMPLETEf_GET(AN_X4_AN_MISC_STSr_reg); 8095 8096 return PHYMOD_E_NONE; 8097 } 8098 8099 int tefmod16_autoneg_lp_status_get(PHYMOD_ST* pc, tefmod16_an_adv_ability_t *an_ability_st) 8100 { 8101 AN_X4_LP_BASE1r_t AN_X4_LP_BASE1r_reg; 8102 AN_X4_LP_BASE2r_t AN_X4_LP_BASE2r_reg; 8103 AN_X4_LP_BASE3r_t AN_X4_LP_BASE3r_reg; 8104 AN_X4_LP_OUI_UP4r_t AN_X4_LP_OUI_UP4r_reg; 8105 AN_X4_LP_OUI_UP5r_t AN_X4_LP_OUI_UP5r_reg; 8106 uint32_t lp_base2; 8107 uint32_t lp_base3; 8108 8109 AN_X4_LP_BASE1r_CLR( AN_X4_LP_BASE1r_reg); 8110 AN_X4_LP_BASE2r_CLR( AN_X4_LP_BASE2r_reg); 8111 AN_X4_LP_BASE3r_CLR( AN_X4_LP_BASE3r_reg); 8112 AN_X4_LP_OUI_UP4r_CLR(AN_X4_LP_OUI_UP4r_reg); 8113 AN_X4_LP_OUI_UP5r_CLR(AN_X4_LP_OUI_UP5r_reg); 8114 8115 /**** 0xC1D5 ****/ 8116 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LP_BASE1r(pc, &AN_X4_LP_BASE1r_reg)); 8117 /**** 0xC1D6 ****/ 8118 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LP_BASE2r(pc, &AN_X4_LP_BASE2r_reg)); 8119 /**** 0xC1D7 ****/ 8120 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LP_BASE3r(pc, &AN_X4_LP_BASE3r_reg)); 8121 /**** 0xC1DB ****/ 8122 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LP_OUI_UP4r(pc,&AN_X4_LP_OUI_UP4r_reg)); 8123 /**** 0xC1DC ****/ 8124 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LP_OUI_UP5r(pc,&AN_X4_LP_OUI_UP5r_reg)); 8125 8126 /* cl73 technology abilities A0 - D21 */ 8127 if (AN_X4_LP_BASE2r_BASE_1G_KXf_GET(AN_X4_LP_BASE2r_reg)){ 8128 an_ability_st->an_base_speed |= (1 << TEFMOD16_CL73_1GBASE_KX); 8129 } 8130 /* cl73 technology abilities A2 - D23 */ 8131 if (AN_X4_LP_BASE2r_BASE_10G_KRf_GET(AN_X4_LP_BASE2r_reg)){ 8132 an_ability_st->an_base_speed |= (1 << TEFMOD16_CL73_10GBASE_KR1); 8133 } 8134 /* cl73 technology abilities A3 - D24 */ 8135 if (AN_X4_LP_BASE2r_BASE_40G_KR4f_GET(AN_X4_LP_BASE2r_reg)){ 8136 an_ability_st->an_base_speed |= (1 << TEFMOD16_CL73_40GBASE_KR4); 8137 } 8138 /* cl73 technology abilities A4 - D25 */ 8139 if (AN_X4_LP_BASE2r_BASE_40G_CR4f_GET(AN_X4_LP_BASE2r_reg)){ 8140 an_ability_st->an_base_speed |= (1 << TEFMOD16_CL73_40GBASE_CR4); 8141 } 8142 /* cl73 technology abilities A7 - D28 */ 8143 if (AN_X4_LP_BASE2r_BASE_100G_KR4f_GET(AN_X4_LP_BASE2r_reg)){ 8144 an_ability_st->an_base_speed |= (1 << TEFMOD16_CL73_100GBASE_KR4); 8145 } 8146 /* cl73 technology abilities A8 - D29 */ 8147 if (AN_X4_LP_BASE2r_BASE_100G_CR4f_GET(AN_X4_LP_BASE2r_reg)){ 8148 an_ability_st->an_base_speed |= (1 << TEFMOD16_CL73_100GBASE_CR4); 8149 } 8150 8151 lp_base2 = AN_X4_LP_BASE2r_GET(AN_X4_LP_BASE2r_reg); 8152 /* Below two 25G Base abilities are not defined in RDB. 8153 * So here we use SW defined macros to get the ability bits. 8154 */ 8155 /* cl73 technology abilities A9 - D30 */ 8156 /* 25GBASE_KRS and 25GBASE_CRS share the same bit. */ 8157 if ((lp_base2 >> AN_BASE_TECH_ABILITY_25GKRS_OFFSET) & AN_BASE_TECH_ABILITY_25GKRS_MASK) { 8158 an_ability_st->an_base_speed |= (1 << TEFMOD16_CL73_25GBASE_KRS1); 8159 an_ability_st->an_base_speed |= (1 << TEFMOD16_CL73_25GBASE_CRS1); 8160 } 8161 /* cl73 technology abilities A10 - D31 */ 8162 /* 25GBASE_KR and 25GBASE_CR share the same bit. */ 8163 if ((lp_base2 >> AN_BASE_TECH_ABILITY_25GKR_OFFSET) & AN_BASE_TECH_ABILITY_25GKR_MASK) { 8164 an_ability_st->an_base_speed |= (1 << TEFMOD16_CL73_25GBASE_KR1); 8165 an_ability_st->an_base_speed |= (1 << TEFMOD16_CL73_25GBASE_CR1); 8166 } 8167 8168 an_ability_st->an_fec = 0; 8169 8170 /* FEC[F0:F1] is encoded in bits [D46:D47] */ 8171 if((AN_X4_LP_BASE3r_FEC_REQUESTEDf_GET(AN_X4_LP_BASE3r_reg)) && 8172 (AN_X4_LP_BASE3r_FEC_ABILITYf_GET(AN_X4_LP_BASE3r_reg))) { 8173 an_ability_st->an_fec |= TEFMOD16_FEC_CL74_SUPRTD_REQSTD; 8174 } 8175 8176 /* FEC[F2:F3] is encoded in bits [D44:D45] */ 8177 lp_base3 = AN_X4_LP_BASE3r_GET(AN_X4_LP_BASE3r_reg); 8178 /* Below 25G FEC abilities are not defined in RDB. 8179 * So here we use SW defined macros to get 25G FEC abilities. 8180 */ 8181 if ((lp_base3 >> AN_BASE_CL91_ABILITY_REQ_OFFSET) & AN_BASE_CL91_ABILITY_REQ_MASK) { 8182 an_ability_st->an_fec |= TEFMOD16_FEC_CL91_SUPRTD_REQSTD; 8183 } 8184 if ((lp_base3 >> AN_BASE_CL74_25GKRS_REQ_OFFSET) & AN_BASE_CL74_25GKRS_REQ_MASK) { 8185 an_ability_st->an_fec |= TEFMOD16_FEC_CL74_SUPRTD_REQSTD; 8186 } 8187 8188 if (an_ability_st->an_fec == 0) { 8189 if (AN_X4_LP_BASE3r_FEC_ABILITYf_GET(AN_X4_LP_BASE3r_reg)) { 8190 an_ability_st->an_fec = TEFMOD16_FEC_SUPRTD_NOT_REQSTD; 8191 } else { 8192 an_ability_st->an_fec = TEFMOD16_FEC_NOT_SUPRTD; 8193 } 8194 } 8195 8196 /* advertise pause capabilities C[0:1] - D[10:11]*/ 8197 if (AN_X4_LP_BASE1r_SYMMETRIC_PAUSEf_GET(AN_X4_LP_BASE1r_reg)) { 8198 an_ability_st->an_pause |= TEFMOD16_SYMM_PAUSE; 8199 } 8200 if (AN_X4_LP_BASE1r_ASYMMETRIC_PAUSEf_GET(AN_X4_LP_BASE1r_reg)) { 8201 an_ability_st->an_pause |= TEFMOD16_ASYM_PAUSE; 8202 } 8203 8204 /* BAM73 OUI UP bit 16 */ 8205 if(AN_X4_LP_OUI_UP4r_BAM_20G_KR2f_GET(AN_X4_LP_OUI_UP4r_reg)) { 8206 an_ability_st->an_bam_speed |= (1 << TEFMOD16_CL73_BAM_20GBASE_KR2); 8207 } 8208 /* BAM73 OUI UP bit 17 */ 8209 if(AN_X4_LP_OUI_UP4r_BAM_20G_CR2f_GET(AN_X4_LP_OUI_UP4r_reg)) { 8210 an_ability_st->an_bam_speed |= (1 << TEFMOD16_CL73_BAM_20GBASE_CR2); 8211 } 8212 /* BAM73 OUI UP bit 18 */ 8213 if(AN_X4_LP_OUI_UP4r_BAM_20G_KR1f_GET(AN_X4_LP_OUI_UP4r_reg)) { 8214 an_ability_st->an_bam_speed1 |= (1 << TEFMOD16_CL73_BAM_20GBASE_KR1); 8215 } 8216 /* BAM73 OUI UP bit 19 */ 8217 if(AN_X4_LP_OUI_UP4r_BAM_20G_CR1f_GET(AN_X4_LP_OUI_UP4r_reg)) { 8218 an_ability_st->an_bam_speed1 |= (1 << TEFMOD16_CL73_BAM_20GBASE_CR1); 8219 } 8220 /* BAM73 OUI UP bit 20 */ 8221 if(AN_X4_LP_OUI_UP4r_BAM_25G_KR1f_GET(AN_X4_LP_OUI_UP4r_reg)) { 8222 an_ability_st->an_bam_speed1 |= (1 << TEFMOD16_CL73_BAM_25GBASE_KR1); 8223 } 8224 /* BAM73 OUI UP bit 21 */ 8225 if(AN_X4_LP_OUI_UP4r_BAM_25G_CR1f_GET(AN_X4_LP_OUI_UP4r_reg)) { 8226 an_ability_st->an_bam_speed1 |= (1 << TEFMOD16_CL73_BAM_25GBASE_CR1); 8227 } 8228 /* BAM73 OUI UP bit 22 */ 8229 if(AN_X4_LP_OUI_UP4r_BAM_40G_KR2f_GET(AN_X4_LP_OUI_UP4r_reg)) { 8230 an_ability_st->an_bam_speed |= (1 << TEFMOD16_CL73_BAM_40GBASE_KR2); 8231 } 8232 /* BAM73 OUI UP bit 23 */ 8233 if(AN_X4_LP_OUI_UP4r_BAM_40G_CR2f_GET(AN_X4_LP_OUI_UP4r_reg)) { 8234 an_ability_st->an_bam_speed |= (1 << TEFMOD16_CL73_BAM_40GBASE_CR2); 8235 } 8236 /* BAM73 OUI UP bit 24 */ 8237 if(AN_X4_LP_OUI_UP4r_BAM_50G_KR2f_GET(AN_X4_LP_OUI_UP4r_reg)) { 8238 an_ability_st->an_bam_speed |= (1 << TEFMOD16_CL73_BAM_50GBASE_KR2); 8239 } 8240 /* BAM73 OUI UP bit 25 */ 8241 if(AN_X4_LP_OUI_UP4r_BAM_50G_CR2f_GET(AN_X4_LP_OUI_UP4r_reg)) { 8242 an_ability_st->an_bam_speed |= (1 << TEFMOD16_CL73_BAM_50GBASE_CR2); 8243 } 8244 8245 /* 8246 * BAM 50G 4-lane is not supported in TSCF16(TH2 and TD3) chips. 8247 * 8248 * BAM73 OUI UP bit 32 */ 8249 /* 8250 if(AN_X4_LP_OUI_UP5r_BAM_50G_KR4f_GET(AN_X4_LP_OUI_UP5r_reg)) { 8251 an_ability_st->an_bam_speed |= (1 << TEFMOD16_CL73_BAM_50GBASE_KR4); 8252 } */ 8253 /* BAM73 OUI UP bit 33 */ 8254 /* 8255 if(AN_X4_LP_OUI_UP5r_BAM_50G_CR4f_GET(AN_X4_LP_OUI_UP5r_reg)) { 8256 an_ability_st->an_bam_speed |= (1 << TEFMOD16_CL73_BAM_50GBASE_CR4); 8257 } 8258 */ 8259 8260 return PHYMOD_E_NONE; 8261 } 8262 8263 8264 int tefmod16_hg2_codec_set(PHYMOD_ST* pc, tefmod16_hg2_codec_t hg2_codec) 8265 { 8266 TX_X4_ENC0r_t TX_X4_ENC0_reg; 8267 RX_X4_DEC_CTL0r_t RX_X4_DEC_CTL0_reg; 8268 8269 READ_TX_X4_ENC0r(pc, &TX_X4_ENC0_reg); 8270 READ_RX_X4_DEC_CTL0r(pc, &RX_X4_DEC_CTL0_reg); 8271 switch (hg2_codec) { 8272 case TEFMOD16_HG2_CODEC_OFF: 8273 TX_X4_ENC0r_HG2_ENABLEf_SET(TX_X4_ENC0_reg, 0); 8274 TX_X4_ENC0r_HG2_CODECf_SET(TX_X4_ENC0_reg, 1); 8275 TX_X4_ENC0r_HG2_MESSAGE_INVALID_CODE_ENABLEf_SET(TX_X4_ENC0_reg, 1); 8276 RX_X4_DEC_CTL0r_HG2_ENABLEf_SET(RX_X4_DEC_CTL0_reg, 0); 8277 RX_X4_DEC_CTL0r_HG2_CODECf_SET(RX_X4_DEC_CTL0_reg, 1); 8278 RX_X4_DEC_CTL0r_HG2_MESSAGE_INVALID_CODE_ENABLEf_SET(RX_X4_DEC_CTL0_reg, 1); 8279 break; 8280 case TEFMOD16_HG2_CODEC_ON_8BYTE_IPG: 8281 TX_X4_ENC0r_HG2_ENABLEf_SET(TX_X4_ENC0_reg, 1); 8282 TX_X4_ENC0r_HG2_CODECf_SET(TX_X4_ENC0_reg, 1); 8283 TX_X4_ENC0r_HG2_MESSAGE_INVALID_CODE_ENABLEf_SET(TX_X4_ENC0_reg, 1); 8284 RX_X4_DEC_CTL0r_HG2_ENABLEf_SET(RX_X4_DEC_CTL0_reg, 1); 8285 RX_X4_DEC_CTL0r_HG2_CODECf_SET(RX_X4_DEC_CTL0_reg, 1); 8286 RX_X4_DEC_CTL0r_HG2_MESSAGE_INVALID_CODE_ENABLEf_SET(RX_X4_DEC_CTL0_reg, 1); 8287 break; 8288 case TEFMOD16_HG2_CODEC_ON_9BYTE_IPG: 8289 TX_X4_ENC0r_HG2_ENABLEf_SET(TX_X4_ENC0_reg, 1); 8290 TX_X4_ENC0r_HG2_CODECf_SET(TX_X4_ENC0_reg, 0); 8291 TX_X4_ENC0r_HG2_MESSAGE_INVALID_CODE_ENABLEf_SET(TX_X4_ENC0_reg, 1); 8292 RX_X4_DEC_CTL0r_HG2_ENABLEf_SET(RX_X4_DEC_CTL0_reg, 1); 8293 RX_X4_DEC_CTL0r_HG2_CODECf_SET(RX_X4_DEC_CTL0_reg, 0); 8294 RX_X4_DEC_CTL0r_HG2_MESSAGE_INVALID_CODE_ENABLEf_SET(RX_X4_DEC_CTL0_reg, 1); 8295 break; 8296 default: 8297 TX_X4_ENC0r_HG2_ENABLEf_SET(TX_X4_ENC0_reg, 0); 8298 TX_X4_ENC0r_HG2_CODECf_SET(TX_X4_ENC0_reg, 1); 8299 TX_X4_ENC0r_HG2_MESSAGE_INVALID_CODE_ENABLEf_SET(TX_X4_ENC0_reg, 1); 8300 RX_X4_DEC_CTL0r_HG2_ENABLEf_SET(RX_X4_DEC_CTL0_reg, 0); 8301 RX_X4_DEC_CTL0r_HG2_CODECf_SET(RX_X4_DEC_CTL0_reg, 1); 8302 RX_X4_DEC_CTL0r_HG2_MESSAGE_INVALID_CODE_ENABLEf_SET(RX_X4_DEC_CTL0_reg, 1); 8303 break; 8304 } 8305 MODIFY_RX_X4_DEC_CTL0r(pc, RX_X4_DEC_CTL0_reg); 8306 MODIFY_TX_X4_ENC0r(pc,TX_X4_ENC0_reg); 8307 8308 return PHYMOD_E_NONE; 8309 } 8310 8311 int tefmod16_hg2_codec_get(PHYMOD_ST* pc, tefmod16_hg2_codec_t* hg2_codec) 8312 { 8313 TX_X4_ENC0r_t TX_X4_ENC0_reg; 8314 8315 READ_TX_X4_ENC0r(pc, &TX_X4_ENC0_reg); 8316 if (TX_X4_ENC0r_HG2_ENABLEf_GET(TX_X4_ENC0_reg)) { 8317 if (TX_X4_ENC0r_HG2_CODECf_GET(TX_X4_ENC0_reg)) { 8318 *hg2_codec = TEFMOD16_HG2_CODEC_ON_8BYTE_IPG; 8319 } else { 8320 *hg2_codec = TEFMOD16_HG2_CODEC_ON_9BYTE_IPG; 8321 } 8322 } else { 8323 *hg2_codec = TEFMOD16_HG2_CODEC_OFF; 8324 8325 } 8326 return PHYMOD_E_NONE; 8327 } 8328 8329 int tefmod16_ams_pll_drv_hv_disable_set(PHYMOD_ST* pc, int disable) 8330 { 8331 AMS_PLL_CTL1r_t AMS_PLL_CTL1_reg; 8332 8333 TEFMOD16_DBG_IN_FUNC_INFO(pc); 8334 AMS_PLL_CTL1r_CLR(AMS_PLL_CTL1_reg); 8335 READ_AMS_PLL_CTL1r(pc, &AMS_PLL_CTL1_reg); 8336 AMS_PLL_CTL1r_AMS_PLL_DRV_HV_DISABLEf_SET(AMS_PLL_CTL1_reg, disable & 0x1); 8337 PHYMOD_IF_ERR_RETURN (MODIFY_AMS_PLL_CTL1r(pc, AMS_PLL_CTL1_reg)); 8338 8339 return PHYMOD_E_NONE; 8340 } 8341 8342 int tefmod16_ams_pll_drv_hv_disable_get(PHYMOD_ST* pc, int* disable) 8343 { 8344 AMS_PLL_CTL1r_t AMS_PLL_CTL1_reg; 8345 8346 TEFMOD16_DBG_IN_FUNC_INFO(pc); 8347 READ_AMS_PLL_CTL1r(pc, &AMS_PLL_CTL1_reg); 8348 *disable = AMS_PLL_CTL1r_AMS_PLL_DRV_HV_DISABLEf_GET(AMS_PLL_CTL1_reg); 8349 8350 return PHYMOD_E_NONE; 8351 } 8352 8353 int tefmod16_pll_vco2_select(PHYMOD_ST* pc, uint32_t vco_rate) 8354 { 8355 AMS_PLL_CTL1r_t AMS_PLL_CTL1_reg; 8356 8357 TEFMOD16_DBG_IN_FUNC_INFO(pc); 8358 AMS_PLL_CTL1r_CLR(AMS_PLL_CTL1_reg); 8359 READ_AMS_PLL_CTL1r(pc, &AMS_PLL_CTL1_reg); 8360 AMS_PLL_CTL1r_AMS_PLL_VCO2_15Gf_SET(AMS_PLL_CTL1_reg, (vco_rate <= TEFMOD16_VCO_RATE_15G)? 1 : 0 ); 8361 PHYMOD_IF_ERR_RETURN(MODIFY_AMS_PLL_CTL1r(pc, AMS_PLL_CTL1_reg)); 8362 8363 return PHYMOD_E_NONE; 8364 8365 } 8366 8367 int tefmod16_default_init(PHYMOD_ST* pc) /* default set*/ 8368 { 8369 MAIN0_SPD_CTLr_t MAIN0_SPD_CTLr_reg; 8370 MAIN0_SPD_CTLr_CLR(MAIN0_SPD_CTLr_reg); 8371 /* select tsc_clk_credit default is pmd_tx_clk */ 8372 MAIN0_SPD_CTLr_TSC_CREDIT_SELf_SET(MAIN0_SPD_CTLr_reg, 1); 8373 PHYMOD_IF_ERR_RETURN(MODIFY_MAIN0_SPD_CTLr(pc, MAIN0_SPD_CTLr_reg)); 8374 8375 return PHYMOD_E_NONE; 8376 8377 } 8378 8379 int tefmod16_fec_correctable_counter_get(PHYMOD_ST* pc, uint32_t* count) 8380 { 8381 RX_X4_FEC_CORRBLKSL0r_t countl_0; 8382 RX_X4_FEC_CORRBLKSL1r_t countl_1; 8383 RX_X4_FEC_CORRBLKSL2r_t countl_2; 8384 RX_X4_FEC_CORRBLKSL3r_t countl_3; 8385 RX_X4_FEC_CORRBLKSL4r_t countl_4; 8386 RX_X4_FEC_CORRBLKSH0r_t counth_0; 8387 RX_X4_FEC_CORRBLKSH1r_t counth_1; 8388 RX_X4_FEC_CORRBLKSH2r_t counth_2; 8389 RX_X4_FEC_CORRBLKSH3r_t counth_3; 8390 RX_X4_FEC_CORRBLKSH4r_t counth_4; 8391 uint32_t sum = 0, count_vl =0; 8392 8393 /* Per lane based counter */ 8394 /* 1 physical lane can map to 5 virtual lane */ 8395 PHYMOD_IF_ERR_RETURN (READ_RX_X4_FEC_CORRBLKSL0r(pc, &countl_0)); 8396 PHYMOD_IF_ERR_RETURN (READ_RX_X4_FEC_CORRBLKSH0r(pc, &counth_0)); 8397 sum = (RX_X4_FEC_CORRBLKSH0r_GET(counth_0) << 16) | (RX_X4_FEC_CORRBLKSL0r_GET(countl_0) & 0xffff); 8398 PHYMOD_IF_ERR_RETURN (READ_RX_X4_FEC_CORRBLKSL1r(pc, &countl_1)); 8399 PHYMOD_IF_ERR_RETURN (READ_RX_X4_FEC_CORRBLKSH1r(pc, &counth_1)); 8400 count_vl = (RX_X4_FEC_CORRBLKSH1r_GET(counth_1) << 16) | (RX_X4_FEC_CORRBLKSL1r_GET(countl_1) & 0xffff); 8401 /* Check overflow */ 8402 /* If sum+count_vl > 0xffffffff, will cause overflow, set sum=0xffffffff */ 8403 if (count_vl > 0xffffffff - sum) { 8404 sum = 0xffffffff; 8405 } else { 8406 sum += count_vl; 8407 } 8408 PHYMOD_IF_ERR_RETURN (READ_RX_X4_FEC_CORRBLKSL2r(pc, &countl_2)); 8409 PHYMOD_IF_ERR_RETURN (READ_RX_X4_FEC_CORRBLKSH2r(pc, &counth_2)); 8410 count_vl = (RX_X4_FEC_CORRBLKSH2r_GET(counth_2) << 16) | (RX_X4_FEC_CORRBLKSL2r_GET(countl_2) & 0xffff); 8411 /* Check overflow */ 8412 if (count_vl > 0xffffffff - sum) { 8413 sum = 0xffffffff; 8414 } else { 8415 sum += count_vl; 8416 } 8417 PHYMOD_IF_ERR_RETURN (READ_RX_X4_FEC_CORRBLKSL3r(pc, &countl_3)); 8418 PHYMOD_IF_ERR_RETURN (READ_RX_X4_FEC_CORRBLKSH3r(pc, &counth_3)); 8419 count_vl = (RX_X4_FEC_CORRBLKSH3r_GET(counth_3) << 16) | (RX_X4_FEC_CORRBLKSL3r_GET(countl_3) & 0xffff); 8420 /* Check overflow */ 8421 if (count_vl > 0xffffffff - sum) { 8422 sum = 0xffffffff; 8423 } else { 8424 sum += count_vl; 8425 } 8426 PHYMOD_IF_ERR_RETURN (READ_RX_X4_FEC_CORRBLKSL4r(pc, &countl_4)); 8427 PHYMOD_IF_ERR_RETURN (READ_RX_X4_FEC_CORRBLKSH4r(pc, &counth_4)); 8428 count_vl = (RX_X4_FEC_CORRBLKSH4r_GET(counth_4) << 16) | (RX_X4_FEC_CORRBLKSL4r_GET(countl_4) & 0xffff); 8429 /* Check overflow */ 8430 if (count_vl > 0xffffffff - sum) { 8431 *count = 0xffffffff; 8432 } else { 8433 *count = sum + count_vl; 8434 } 8435 8436 return PHYMOD_E_NONE; 8437 } 8438 8439 int tefmod16_fec_uncorrectable_counter_get(PHYMOD_ST* pc, uint32_t* count) 8440 { 8441 RX_X4_FEC_UNCORRBLKSL0r_t countl_0; 8442 RX_X4_FEC_UNCORRBLKSL1r_t countl_1; 8443 RX_X4_FEC_UNCORRBLKSL2r_t countl_2; 8444 RX_X4_FEC_UNCORRBLKSL3r_t countl_3; 8445 RX_X4_FEC_UNCORRBLKSL4r_t countl_4; 8446 RX_X4_FEC_UNCORRBLKSH0r_t counth_0; 8447 RX_X4_FEC_UNCORRBLKSH1r_t counth_1; 8448 RX_X4_FEC_UNCORRBLKSH2r_t counth_2; 8449 RX_X4_FEC_UNCORRBLKSH3r_t counth_3; 8450 RX_X4_FEC_UNCORRBLKSH4r_t counth_4; 8451 uint32_t sum = 0, count_vl = 0; 8452 8453 /* Per lane based counter */ 8454 /* 1 physical lane can map to 5 virtual lane */ 8455 PHYMOD_IF_ERR_RETURN (READ_RX_X4_FEC_UNCORRBLKSL0r(pc, &countl_0)); 8456 PHYMOD_IF_ERR_RETURN (READ_RX_X4_FEC_UNCORRBLKSH0r(pc, &counth_0)); 8457 sum = (RX_X4_FEC_UNCORRBLKSH0r_GET(counth_0) << 16) | (RX_X4_FEC_UNCORRBLKSL0r_GET(countl_0) & 0xffff); 8458 PHYMOD_IF_ERR_RETURN (READ_RX_X4_FEC_UNCORRBLKSL1r(pc, &countl_1)); 8459 PHYMOD_IF_ERR_RETURN (READ_RX_X4_FEC_UNCORRBLKSH1r(pc, &counth_1)); 8460 count_vl = (RX_X4_FEC_UNCORRBLKSH1r_GET(counth_1) << 16) | (RX_X4_FEC_UNCORRBLKSL1r_GET(countl_1) & 0xffff); 8461 /* Check overflow */ 8462 /* If sum+count_vl > 0xffffffff, will cause overflow, set sum=0xffffffff */ 8463 if (count_vl > 0xffffffff - sum) { 8464 sum = 0xffffffff; 8465 } else { 8466 sum += count_vl; 8467 } 8468 PHYMOD_IF_ERR_RETURN (READ_RX_X4_FEC_UNCORRBLKSL2r(pc, &countl_2)); 8469 PHYMOD_IF_ERR_RETURN (READ_RX_X4_FEC_UNCORRBLKSH2r(pc, &counth_2)); 8470 count_vl = (RX_X4_FEC_UNCORRBLKSH2r_GET(counth_2) << 16) | (RX_X4_FEC_UNCORRBLKSL2r_GET(countl_2) & 0xffff); 8471 /* Check overflow */ 8472 if (count_vl > 0xffffffff - sum) { 8473 sum = 0xffffffff; 8474 } else { 8475 sum += count_vl; 8476 } 8477 PHYMOD_IF_ERR_RETURN (READ_RX_X4_FEC_UNCORRBLKSL3r(pc, &countl_3)); 8478 PHYMOD_IF_ERR_RETURN (READ_RX_X4_FEC_UNCORRBLKSH3r(pc, &counth_3)); 8479 count_vl = (RX_X4_FEC_UNCORRBLKSH3r_GET(counth_3) << 16) | (RX_X4_FEC_UNCORRBLKSL3r_GET(countl_3) & 0xffff); 8480 /* Check overflow */ 8481 if (count_vl > 0xffffffff - sum) { 8482 sum = 0xffffffff; 8483 } else { 8484 sum += count_vl; 8485 } 8486 PHYMOD_IF_ERR_RETURN (READ_RX_X4_FEC_UNCORRBLKSL4r(pc, &countl_4)); 8487 PHYMOD_IF_ERR_RETURN (READ_RX_X4_FEC_UNCORRBLKSH4r(pc, &counth_4)); 8488 count_vl = (RX_X4_FEC_UNCORRBLKSH4r_GET(counth_4) << 16) | (RX_X4_FEC_UNCORRBLKSL4r_GET(countl_4) & 0xffff); 8489 /* Check overflow */ 8490 if (count_vl > 0xffffffff - sum) { 8491 *count = 0xffffffff; 8492 } else { 8493 *count = sum + count_vl; 8494 } 8495 8496 return PHYMOD_E_NONE; 8497 } 8498 8499 int tefmod16_fec_cl91_correctable_counter_get(PHYMOD_ST* pc, uint32_t* count) 8500 { 8501 RX_X4_FEC_CORR_CTR0r_t count0; 8502 RX_X4_FEC_CORR_CTR1r_t count1; 8503 8504 /* Per port based counter */ 8505 PHYMOD_IF_ERR_RETURN (READ_RX_X4_FEC_CORR_CTR0r(pc, &count0)); 8506 PHYMOD_IF_ERR_RETURN (READ_RX_X4_FEC_CORR_CTR1r(pc, &count1)); 8507 *count = (RX_X4_FEC_CORR_CTR1r_GET(count1) << 16) | (RX_X4_FEC_CORR_CTR0r_GET(count0) & 0xffff); 8508 8509 return PHYMOD_E_NONE; 8510 } 8511 8512 int tefmod16_fec_cl91_uncorrectable_counter_get(PHYMOD_ST* pc, uint32_t* count) 8513 { 8514 RX_X4_FEC_UNCORR_CTR0r_t count0; 8515 RX_X4_FEC_UNCORR_CTR1r_t count1; 8516 8517 /* Per port based counter */ 8518 PHYMOD_IF_ERR_RETURN (READ_RX_X4_FEC_UNCORR_CTR0r(pc, &count0)); 8519 PHYMOD_IF_ERR_RETURN (READ_RX_X4_FEC_UNCORR_CTR1r(pc, &count1)); 8520 *count = (RX_X4_FEC_UNCORR_CTR1r_GET(count1) << 16) | (RX_X4_FEC_UNCORR_CTR0r_GET(count0) & 0xffff); 8521 8522 return PHYMOD_E_NONE; 8523 } 8524 8525 int tefmod16_setup_for_sw_an(PHYMOD_ST* pc, int num_lanes) 8526 { 8527 AN_X4_LD_CTLr_t AN_X4_LD_CTLr_reg; 8528 AN_X4_CL73_CFGr_t AN_X4_ABILITIES_CL73_CFGr_reg; 8529 AN_X4_WAIT_ACK_COMPLETEr_t AN_X4_WAIT_ACK_COMPLETE_reg; 8530 AN_X1_CL73_ERRr_t AN_X1_CL73_ERR_reg; 8531 MAIN0_SETUPr_t MAIN0_SETUP_reg; 8532 uint32_t plldiv_r_val; 8533 int num_lane_adv; 8534 8535 8536 /* Set cl73 err timer to 0 */ 8537 AN_X1_CL73_ERRr_CLR(AN_X1_CL73_ERR_reg); 8538 AN_X1_CL73_ERRr_SET(AN_X1_CL73_ERR_reg, 0); 8539 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_CL73_ERRr(pc, AN_X1_CL73_ERR_reg)); 8540 8541 /* disable tscf */ 8542 tefmod16_disable_set(pc); 8543 8544 /* set the cl73 vc0 mode 1 */ 8545 PHYMOD_IF_ERR_RETURN(tefmod16_get_plldiv(pc, &plldiv_r_val)); 8546 MAIN0_SETUPr_CLR(MAIN0_SETUP_reg); 8547 PHYMOD_IF_ERR_RETURN(READ_MAIN0_SETUPr(pc, &MAIN0_SETUP_reg)); 8548 8549 if (plldiv_r_val<=4) { /* pll_div <= 132; for 156MHz only */ 8550 /* for 25G VCO set the cl73 VCO bit to1 otherwise 0*/ 8551 MAIN0_SETUPr_CL73_VCOf_SET(MAIN0_SETUP_reg, 0); 8552 } else { 8553 MAIN0_SETUPr_CL73_VCOf_SET(MAIN0_SETUP_reg, 1); 8554 } 8555 PHYMOD_IF_ERR_RETURN(WRITE_MAIN0_SETUPr(pc, MAIN0_SETUP_reg)); 8556 8557 /* clear the SW AN and cl73 an enable to 0 */ 8558 AN_X4_LD_CTLr_CLR(AN_X4_LD_CTLr_reg); 8559 AN_X4_LD_CTLr_AN_TYPE_SWf_SET(AN_X4_LD_CTLr_reg, 0); 8560 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_LD_CTLr(pc, AN_X4_LD_CTLr_reg)); 8561 8562 switch(num_lanes) { 8563 case 1: 8564 num_lane_adv = 0; 8565 break; 8566 case 2: 8567 num_lane_adv = 1; 8568 break; 8569 case 4: 8570 num_lane_adv = 2; 8571 break; 8572 default: 8573 return PHYMOD_E_PARAM; 8574 } 8575 8576 AN_X4_CL73_CFGr_CLR(AN_X4_ABILITIES_CL73_CFGr_reg); 8577 AN_X4_CL73_CFGr_CL73_BAM_ENABLEf_SET(AN_X4_ABILITIES_CL73_CFGr_reg, 0); 8578 AN_X4_CL73_CFGr_CL73_ENABLEf_SET(AN_X4_ABILITIES_CL73_CFGr_reg, 0); 8579 AN_X4_CL73_CFGr_NUM_ADVERTISED_LANESf_SET(AN_X4_ABILITIES_CL73_CFGr_reg, num_lane_adv); 8580 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_CL73_CFGr(pc, AN_X4_ABILITIES_CL73_CFGr_reg)); 8581 8582 /* set the wait for ack FSM to 1 */ 8583 AN_X4_WAIT_ACK_COMPLETEr_CLR(AN_X4_WAIT_ACK_COMPLETE_reg); 8584 PHYMOD_IF_ERR_RETURN(READ_AN_X4_WAIT_ACK_COMPLETEr(pc, &AN_X4_WAIT_ACK_COMPLETE_reg)); 8585 AN_X4_WAIT_ACK_COMPLETEr_WAIT_FOR_ACK_ENf_SET(AN_X4_WAIT_ACK_COMPLETE_reg, 1); 8586 PHYMOD_IF_ERR_RETURN(WRITE_AN_X4_WAIT_ACK_COMPLETEr(pc, AN_X4_WAIT_ACK_COMPLETE_reg)); 8587 8588 return PHYMOD_E_NONE; 8589 } 8590 8591 int tefmod16_sw_an_control(PHYMOD_ST* pc, int enable) 8592 { 8593 AN_X4_LD_CTLr_t AN_X4_LD_CTLr_reg; 8594 AN_X4_CL73_CFGr_t AN_X4_ABILITIES_CL73_CFGr_reg; 8595 8596 /* Enabling SW AN if sw_an is set */ 8597 AN_X4_LD_CTLr_CLR(AN_X4_LD_CTLr_reg); 8598 AN_X4_LD_CTLr_AN_TYPE_SWf_SET(AN_X4_LD_CTLr_reg, enable); 8599 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_LD_CTLr(pc, AN_X4_LD_CTLr_reg)); 8600 8601 AN_X4_CL73_CFGr_CLR(AN_X4_ABILITIES_CL73_CFGr_reg); 8602 AN_X4_CL73_CFGr_CL73_ENABLEf_SET(AN_X4_ABILITIES_CL73_CFGr_reg, enable); 8603 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_CL73_CFGr(pc, AN_X4_ABILITIES_CL73_CFGr_reg)); 8604 8605 return PHYMOD_E_NONE; 8606 } 8607 8608 /*! 8609 @brief Programs the SW AN local device pages 8610 @param pc handle to current TSCF context (#PHYMOD_ST) 8611 @returns PHYMOD_E_NONE if no errors. PHYMOD_EERROR else. 8612 8613 @details 8614 This function programs SW AN local device pages. 8615 per_lane_control bits [17:16] indicate 8616 the page its trying to write, per_lane_control bits [15:0] 8617 has the actual page contents 8618 */ 8619 int tefmod16_sw_an_ld_page_load(PHYMOD_ST* pc, phymod_an_page_t *pages, int is_base_page) 8620 { 8621 AN_X4_LD_PAGE0r_t AN_X4_LD_PAGE0r_reg; 8622 AN_X4_LD_PAGE1r_t AN_X4_LD_PAGE1r_reg; 8623 AN_X4_LD_PAGE2r_t AN_X4_LD_PAGE2r_reg; 8624 8625 AN_X4_SW_AN_BASE_PAGE0r_t AN_X4_SW_AN_BASE_PAGE0r_reg; 8626 AN_X4_SW_AN_BASE_PAGE1r_t AN_X4_SW_AN_BASE_PAGE1r_reg; 8627 AN_X4_SW_AN_BASE_PAGE2r_t AN_X4_SW_AN_BASE_PAGE2r_reg; 8628 8629 8630 if (is_base_page) { 8631 8632 AN_X4_SW_AN_BASE_PAGE2r_CLR(AN_X4_SW_AN_BASE_PAGE2r_reg); 8633 AN_X4_SW_AN_BASE_PAGE2r_SET(AN_X4_SW_AN_BASE_PAGE2r_reg, pages->page_2); 8634 PHYMOD_IF_ERR_RETURN(WRITE_AN_X4_SW_AN_BASE_PAGE2r(pc, AN_X4_SW_AN_BASE_PAGE2r_reg)); 8635 8636 AN_X4_SW_AN_BASE_PAGE1r_CLR(AN_X4_SW_AN_BASE_PAGE1r_reg); 8637 AN_X4_SW_AN_BASE_PAGE1r_SET(AN_X4_SW_AN_BASE_PAGE1r_reg, pages->page_1); 8638 PHYMOD_IF_ERR_RETURN(WRITE_AN_X4_SW_AN_BASE_PAGE1r(pc, AN_X4_SW_AN_BASE_PAGE1r_reg)); 8639 8640 AN_X4_SW_AN_BASE_PAGE0r_CLR(AN_X4_SW_AN_BASE_PAGE0r_reg); 8641 AN_X4_SW_AN_BASE_PAGE0r_SET(AN_X4_SW_AN_BASE_PAGE0r_reg, pages->page_0); 8642 PHYMOD_IF_ERR_RETURN(WRITE_AN_X4_SW_AN_BASE_PAGE0r(pc, AN_X4_SW_AN_BASE_PAGE0r_reg)); 8643 8644 } else { 8645 8646 AN_X4_LD_PAGE2r_CLR(AN_X4_LD_PAGE2r_reg); 8647 AN_X4_LD_PAGE2r_LD_PAGE_2f_SET(AN_X4_LD_PAGE2r_reg, pages->page_2); 8648 PHYMOD_IF_ERR_RETURN(WRITE_AN_X4_LD_PAGE2r(pc, AN_X4_LD_PAGE2r_reg)); 8649 8650 AN_X4_LD_PAGE1r_CLR(AN_X4_LD_PAGE1r_reg); 8651 AN_X4_LD_PAGE1r_LD_PAGE_1f_SET(AN_X4_LD_PAGE1r_reg, pages->page_1); 8652 PHYMOD_IF_ERR_RETURN(WRITE_AN_X4_LD_PAGE1r(pc, AN_X4_LD_PAGE1r_reg)); 8653 8654 AN_X4_LD_PAGE0r_CLR(AN_X4_LD_PAGE0r_reg); 8655 AN_X4_LD_PAGE0r_LD_PAGE_0f_SET(AN_X4_LD_PAGE0r_reg, pages->page_0); 8656 PHYMOD_IF_ERR_RETURN(WRITE_AN_X4_LD_PAGE0r(pc, AN_X4_LD_PAGE0r_reg)); 8657 8658 } 8659 return PHYMOD_E_NONE; 8660 } 8661 8662 /*! 8663 @brief Reads the SW AN link partner pages 8664 @param pc handle to current TSCF context (#PHYMOD_ST) 8665 @returns PHYMOD_E_NONE if no errors. PHYMOD_EERROR else. 8666 8667 @details 8668 This function reads SW AN link partner pages. The HW 8669 requires you to read page0 register last. 8670 8671 */ 8672 int tefmod16_sw_an_lp_page_read(PHYMOD_ST* pc, phymod_an_page_t *pages) 8673 { 8674 AN_X4_LP_PAGE0r_t AN_X4_LP_PAGE0r_reg; 8675 AN_X4_LP_PAGE1r_t AN_X4_LP_PAGE1r_reg; 8676 AN_X4_LP_PAGE2r_t AN_X4_LP_PAGE2r_reg; 8677 8678 AN_X4_LP_PAGE2r_CLR(AN_X4_LP_PAGE2r_reg); 8679 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LP_PAGE2r(pc, &AN_X4_LP_PAGE2r_reg)); 8680 pages->page_2 = AN_X4_LP_PAGE2r_LP_PAGE_2f_GET(AN_X4_LP_PAGE2r_reg); 8681 8682 AN_X4_LP_PAGE1r_CLR(AN_X4_LP_PAGE1r_reg); 8683 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LP_PAGE1r(pc, &AN_X4_LP_PAGE1r_reg)); 8684 pages->page_1 = AN_X4_LP_PAGE1r_LP_PAGE_1f_GET(AN_X4_LP_PAGE1r_reg); 8685 8686 AN_X4_LP_PAGE0r_CLR(AN_X4_LP_PAGE0r_reg); 8687 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LP_PAGE0r(pc, &AN_X4_LP_PAGE0r_reg)); 8688 pages->page_0 = AN_X4_LP_PAGE0r_LP_PAGE_0f_GET(AN_X4_LP_PAGE0r_reg); 8689 8690 return PHYMOD_E_NONE; 8691 8692 } 8693 8694 8695 int tefmod16_sw_an_ctl_sts_get(PHYMOD_ST* pc, phymod_sw_an_ctrl_status_t *an_ctrl_status) 8696 { 8697 AN_X4_SW_CTL_STSr_t AN_X4_SW_CTL_STSr_reg; 8698 8699 AN_X4_SW_CTL_STSr_CLR(AN_X4_SW_CTL_STSr_reg); 8700 PHYMOD_IF_ERR_RETURN (READ_AN_X4_SW_CTL_STSr(pc, &AN_X4_SW_CTL_STSr_reg)); 8701 8702 an_ctrl_status->seq_restart = AN_X4_SW_CTL_STSr_LD_SEQ_RESTARTf_GET(AN_X4_SW_CTL_STSr_reg); 8703 an_ctrl_status->lp_page_rdy = AN_X4_SW_CTL_STSr_LP_PAGE_RDYf_GET(AN_X4_SW_CTL_STSr_reg); 8704 an_ctrl_status->page_req = AN_X4_SW_CTL_STSr_LD_PAGE_REQf_GET(AN_X4_SW_CTL_STSr_reg); 8705 an_ctrl_status->an_completed = AN_X4_SW_CTL_STSr_AN_COMPLETEDf_GET(AN_X4_SW_CTL_STSr_reg); 8706 8707 if (!an_ctrl_status->an_completed) { 8708 PHYMOD_IF_ERR_RETURN 8709 (tefmod16_pxgng_status_an_good_chk_get(pc, &an_ctrl_status->an_completed)); 8710 } 8711 8712 return PHYMOD_E_NONE; 8713 } 8714 8715 int tefmod16_sw_an_set_ack(PHYMOD_ST* pc) 8716 { 8717 AN_X4_WAIT_ACK_COMPLETEr_t AN_X4_WAIT_ACK_COMPLETEr_reg; 8718 8719 AN_X4_WAIT_ACK_COMPLETEr_CLR(AN_X4_WAIT_ACK_COMPLETEr_reg); 8720 AN_X4_WAIT_ACK_COMPLETEr_SEND_ACKf_SET(AN_X4_WAIT_ACK_COMPLETEr_reg, 1); 8721 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_WAIT_ACK_COMPLETEr(pc, AN_X4_WAIT_ACK_COMPLETEr_reg)); 8722 8723 return PHYMOD_E_NONE; 8724 } 8725 8726 int tefmod16_set_speed_id(PHYMOD_ST *pc, int speed_id) 8727 { 8728 SC_X4_CTLr_t xgxs_x4_ctrl; 8729 phymod_access_t pa_copy; 8730 int start_lane = 0, num_lane = 0; 8731 8732 8733 /* need to figure out what's the starting lane */ 8734 PHYMOD_MEMCPY(&pa_copy, pc, sizeof(pa_copy)); 8735 PHYMOD_IF_ERR_RETURN 8736 (phymod_util_lane_config_get(pc, &start_lane, &num_lane)); 8737 pa_copy.lane_mask = 0x1 << start_lane; 8738 8739 /* write the speed_id into the speed_change register */ 8740 SC_X4_CTLr_CLR(xgxs_x4_ctrl); 8741 SC_X4_CTLr_SPEEDf_SET(xgxs_x4_ctrl, speed_id); 8742 MODIFY_SC_X4_CTLr(pc, xgxs_x4_ctrl); 8743 8744 return PHYMOD_E_NONE; 8745 } 8746 8747 8748 8749 int tefmod16_pxgng_status_an_ack_complete_get(PHYMOD_ST *pc, int *ack_complte) 8750 { 8751 8752 AN_X4_PXNG_STSr_t an_pxng_status_reg; 8753 8754 AN_X4_PXNG_STSr_CLR(an_pxng_status_reg); 8755 PHYMOD_IF_ERR_RETURN 8756 (READ_AN_X4_PXNG_STSr(pc, &an_pxng_status_reg)); 8757 PHYMOD_IF_ERR_RETURN 8758 (READ_AN_X4_PXNG_STSr(pc, &an_pxng_status_reg)); 8759 8760 *ack_complte = AN_X4_PXNG_STSr_COMPLETE_ACKf_GET(an_pxng_status_reg); 8761 8762 return PHYMOD_E_NONE; 8763 } 8764 8765 int tefmod16_pxgng_status_an_good_chk_get(PHYMOD_ST *pc, uint8_t *an_good_chk) 8766 { 8767 8768 AN_X4_PXNG_STSr_t an_pxng_status_reg; 8769 8770 AN_X4_PXNG_STSr_CLR(an_pxng_status_reg); 8771 PHYMOD_IF_ERR_RETURN 8772 (READ_AN_X4_PXNG_STSr(pc, &an_pxng_status_reg)); 8773 PHYMOD_IF_ERR_RETURN 8774 (READ_AN_X4_PXNG_STSr(pc, &an_pxng_status_reg)); 8775 8776 *an_good_chk = AN_X4_PXNG_STSr_AN_GOOD_CHECKf_GET(an_pxng_status_reg); 8777 8778 return PHYMOD_E_NONE; 8779 8780 } 8781 8782 8783 int tefmod16_sw_an_fec_override(PHYMOD_ST *pc, tefmod16_fec_type_t fec_type, int enable) 8784 { 8785 SC_X4_SC_X4_OVRRr_t SC_X4_SC_X4_OVRR_reg; 8786 int fec_value = 0; 8787 8788 if (enable) { 8789 if (fec_type == TEFMOD16_CL91) { 8790 fec_value = 0x3; 8791 } else if (fec_type == TEFMOD16_CL74) { 8792 fec_value = 0x2; 8793 } else { 8794 /* NO FEC */ 8795 fec_value = 0x1; 8796 } 8797 } else { 8798 fec_value = 0x0; 8799 } 8800 SC_X4_SC_X4_OVRRr_CLR(SC_X4_SC_X4_OVRR_reg); 8801 SC_X4_SC_X4_OVRRr_AN_FEC_SEL_OVERRIDEf_SET(SC_X4_SC_X4_OVRR_reg, fec_value); 8802 PHYMOD_IF_ERR_RETURN 8803 (MODIFY_SC_X4_SC_X4_OVRRr(pc, SC_X4_SC_X4_OVRR_reg)); 8804 8805 return PHYMOD_E_NONE; 8806 } 8807 8808 8809 int tefmod16_sw_an_advert_set(PHYMOD_ST* pc, tefmod16_an_adv_ability_t *cl73_adv, phymod_sw_an_ctxt_t *an_ctxt) 8810 { 8811 uint8_t pause_cap = 0; 8812 /* Initialize the base page */ 8813 an_ctxt->tx_pages.base_page.page_0 = 0; 8814 an_ctxt->tx_pages.base_page.page_1 = 0; 8815 an_ctxt->tx_pages.base_page.page_2 = 0; 8816 8817 8818 an_ctxt->no_pages_to_be_txed = 1; 8819 8820 an_ctxt->tx_pages.base_page.page_0 |= ((AN_BASE0_PAGE_IEEE_SEL_MASK & IEEE_SEL_802P3) << 8821 AN_BASE0_PAGE_IEEE_SEL_OFFSET); 8822 8823 an_ctxt->tx_pages.base_page.page_0 &= ~(AN_BASE0_PAGE_CL73_NOUNCE_MASK << 8824 AN_BASE0_PAGE_CL73_NOUNCE_OFFSET); /* HW will set this bit */ 8825 8826 if (cl73_adv->an_pause == TEFMOD16_NO_PAUSE) { 8827 pause_cap = 0; 8828 } else if (cl73_adv->an_pause == TEFMOD16_SYMM_PAUSE) { 8829 pause_cap = 1; 8830 } else if (cl73_adv->an_pause == TEFMOD16_ASYM_PAUSE) { 8831 pause_cap = 2; 8832 } else if (cl73_adv->an_pause == TEFMOD16_ASYM_SYMM_PAUSE) { 8833 pause_cap = 3; 8834 } else { 8835 /* default to no pause ability */ 8836 pause_cap = 0; 8837 } 8838 an_ctxt->tx_pages.base_page.page_0 |= ((AN_BASE0_PAGE_CAP_MASK & pause_cap) << 8839 AN_BASE0_PAGE_CAP_OFFSET); 8840 8841 an_ctxt->tx_pages.base_page.page_0 &= ~(AN_BASE0_PAGE_REMOTE_FAULT_MASK << 8842 AN_BASE0_PAGE_REMOTE_FAULT_OFFSET); /* Need more clarity */ 8843 8844 an_ctxt->tx_pages.base_page.page_0 &= ~(AN_BASE0_PAGE_ACK_MASK << 8845 AN_BASE0_PAGE_ACK_OFFSET); /* Set by HW */ 8846 8847 /* set tech Next page to 0*/ 8848 an_ctxt->tx_pages.base_page.page_0 &= ~(AN_BASE0_PAGE_NP_MASK << 8849 AN_BASE0_PAGE_NP_OFFSET); 8850 PHYMOD_SRAND(PHYMOD_TIME_USECS()); 8851 /* need to generate a 5 bit random number for Tx nounce for now set to 1 */ 8852 an_ctxt->tx_pages.base_page.page_1 |= ((AN_BASE1_PAGE_TX_NOUNCE_MASK & (PHYMOD_RAND())) << 8853 AN_BASE1_PAGE_TX_NOUNCE_OFFSET); 8854 8855 if (an_ctxt->an_mode == phymod_AN_MODE_MSA) { 8856 cl73_adv->an_base_speed = 0; 8857 } 8858 8859 if (cl73_adv->an_base_speed) { 8860 /* populate the IEE base ability */ 8861 if (((cl73_adv->an_base_speed >> TEFMOD16_CL73_25GBASE_KR1 ) & 1) || 8862 ((cl73_adv->an_base_speed >> TEFMOD16_CL73_25GBASE_CR1 ) & 1)) { 8863 an_ctxt->tx_pages.base_page.page_1 |= (AN_BASE_TECH_ABILITY_25GKR_MASK << 8864 AN_BASE_TECH_ABILITY_25GKR_OFFSET); 8865 } 8866 if (((cl73_adv->an_base_speed >> TEFMOD16_CL73_25GBASE_KRS1 ) & 1) || 8867 ((cl73_adv->an_base_speed >> TEFMOD16_CL73_25GBASE_CRS1 ) & 1)) { 8868 an_ctxt->tx_pages.base_page.page_1 |= (AN_BASE_TECH_ABILITY_25GKRS_MASK << 8869 AN_BASE_TECH_ABILITY_25GKRS_OFFSET); 8870 } 8871 8872 /* Set cl91/74 supported to 1 */ 8873 an_ctxt->tx_pages.base_page.page_2 |= (AN_BASE_CL74_ABILITY_SUP_MASK << 8874 AN_BASE_CL74_ABILITY_SUP_OFFSET); 8875 8876 if (cl73_adv->an_fec == TEFMOD16_FEC_SUPRTD_NOT_REQSTD) { 8877 an_ctxt->tx_pages.base_page.page_2 &= ~(AN_BASE_CL74_ABILITY_REQ_MASK << 8878 AN_BASE_CL74_ABILITY_REQ_OFFSET); 8879 an_ctxt->tx_pages.base_page.page_2 &= ~(AN_BASE_CL91_ABILITY_REQ_MASK << 8880 AN_BASE_CL91_ABILITY_REQ_OFFSET); 8881 an_ctxt->tx_pages.base_page.page_2 &= ~(AN_BASE_CL74_25GKRS_REQ_MASK << 8882 AN_BASE_CL74_25GKRS_REQ_OFFSET); 8883 } else { 8884 if (cl73_adv->an_fec & TEFMOD16_FEC_CL74_SUPRTD_REQSTD) { 8885 an_ctxt->tx_pages.base_page.page_2 |= (AN_BASE_CL74_ABILITY_REQ_MASK << 8886 AN_BASE_CL74_ABILITY_REQ_OFFSET); 8887 an_ctxt->tx_pages.base_page.page_2 |= (AN_BASE_CL74_25GKRS_REQ_MASK << 8888 AN_BASE_CL74_25GKRS_REQ_OFFSET); 8889 } 8890 if (cl73_adv->an_fec & TEFMOD16_FEC_CL91_SUPRTD_REQSTD) { 8891 an_ctxt->tx_pages.base_page.page_2 |= (AN_BASE_CL91_ABILITY_REQ_MASK << 8892 AN_BASE_CL91_ABILITY_REQ_OFFSET); 8893 } 8894 } 8895 } 8896 8897 8898 8899 if (cl73_adv->an_bam_speed || cl73_adv->an_bam_speed1) { 8900 8901 /* If BAM speed is enabled set the NP bit in base page to 1*/ 8902 an_ctxt->tx_pages.base_page.page_0 |= (AN_BASE0_PAGE_NP_MASK << AN_BASE0_PAGE_NP_OFFSET); 8903 8904 an_ctxt->tx_pages.msg_page.page_0 = 0; 8905 an_ctxt->tx_pages.msg_page.page_1 = 0; 8906 an_ctxt->tx_pages.msg_page.page_2 = 0; 8907 8908 /* populate the Message page with Consortium information */ 8909 8910 /* Populate page0 with 8911 * 1. Msg code 8912 * 2. Toggle bit ==> set to 0 (will be handled by HW) 8913 * 3. ACK2 ==> Set to 0 (will be handled buy HW) 8914 * 4. set MP bit to 1 8915 * 5. Set NP bit to 1 8916 */ 8917 an_ctxt->tx_pages.msg_page.page_0 |= ((AN_MSG_PAGE0_MSG_CODE_MASK & MSA_MSG_CODE) << AN_MSG_PAGE0_MSG_CODE_OFFSET); 8918 an_ctxt->tx_pages.msg_page.page_0 |= (AN_MSG_PAGE0_MSG_PAGE_MASK << AN_MSG_PAGE0_MSG_PAGE_OFFSET); 8919 an_ctxt->tx_pages.msg_page.page_0 |= (AN_MSG_PAGE0_NP_MASK << AN_MSG_PAGE0_NP_OFFSET); 8920 8921 /* populate msg page 1 & 2 with consortium information 8922 * OUI 13:23 8923 * OUI 2:12 8924 */ 8925 an_ctxt->tx_pages.msg_page.page_1 |= ((AN_MSG_PAGE1_OUI_13to23_MASK & MSA_OUI_13to23) << 8926 AN_MSG_PAGE1_OUI_13to23_OFFSET); 8927 an_ctxt->tx_pages.msg_page.page_2 |= ((AN_MSG_PAGE2_OUI_2to12_MASK & MSA_OUT_2to12) << 8928 AN_MSG_PAGE2_OUI_2to12_OFFSET); 8929 8930 an_ctxt->tx_pages.ufmt_page.page_0 = 0; 8931 an_ctxt->tx_pages.ufmt_page.page_1 = 0; 8932 an_ctxt->tx_pages.ufmt_page.page_2 = 0; 8933 8934 /* Populate UFMT page */ 8935 8936 an_ctxt->tx_pages.ufmt_page.page_0 |= ((AN_UF_PAGE0_EXT_TECH_ABILITY_MASK & EXT_TECH_ABILITY_CODE) << 8937 AN_UF_PAGE0_EXT_TECH_ABILITY_OFFSET); 8938 an_ctxt->tx_pages.ufmt_page.page_0 |= ((AN_UF_PAGE0_OUI_MASK & MSA_OUI_0to1) << 8939 AN_UF_PAGE0_OUI_OFFSET); 8940 8941 if ((cl73_adv->an_bam_speed1 >> TEFMOD16_CL73_BAM_25GBASE_KR1) & 0x1) { 8942 an_ctxt->tx_pages.ufmt_page.page_1 |= (AN_UF_PAGE1_25G_KR1_ABILITY_MASK << 8943 AN_UF_PAGE1_25G_KR1_ABILITY_OFFSET); 8944 } 8945 if ((cl73_adv->an_bam_speed1 >> TEFMOD16_CL73_BAM_25GBASE_CR1) & 0x1) { 8946 an_ctxt->tx_pages.ufmt_page.page_1 |= (AN_UF_PAGE1_25G_CR1_ABILITY_MASK << 8947 AN_UF_PAGE1_25G_CR1_ABILITY_OFFSET); 8948 } 8949 if ((cl73_adv->an_bam_speed >> TEFMOD16_CL73_BAM_50GBASE_KR2) & 0x1) { 8950 an_ctxt->tx_pages.ufmt_page.page_1 |= (AN_UF_PAGE1_50G_KR2_ABILITY_MASK << 8951 AN_UF_PAGE1_50G_KR2_ABILITY_OFFSET); 8952 } 8953 if ((cl73_adv->an_bam_speed >> TEFMOD16_CL73_BAM_50GBASE_CR2) & 0x1) { 8954 an_ctxt->tx_pages.ufmt_page.page_1 |= (AN_UF_PAGE1_50G_CR2_ABILITY_MASK << 8955 AN_UF_PAGE1_50G_CR2_ABILITY_OFFSET); 8956 } 8957 8958 /* Update FEC Information */ 8959 an_ctxt->tx_pages.ufmt_page.page_2 |= (AN_UF_PAGE2_CL91_SUPPORT_MASK << 8960 AN_UF_PAGE2_CL91_SUPPORT_OFFSET); 8961 an_ctxt->tx_pages.ufmt_page.page_2 |= (AN_UF_PAGE2_CL74_SUPPORT_MASK << 8962 AN_UF_PAGE2_CL74_SUPPORT_OFFSET); 8963 8964 if (cl73_adv->an_fec & TEFMOD16_FEC_CL74_SUPRTD_REQSTD) { 8965 an_ctxt->tx_pages.ufmt_page.page_2 |= (AN_UF_PAGE2_CL74_REQ_MASK << 8966 AN_UF_PAGE2_CL74_REQ_OFFSET); 8967 } 8968 if (cl73_adv->an_fec & TEFMOD16_FEC_CL91_SUPRTD_REQSTD) { 8969 an_ctxt->tx_pages.ufmt_page.page_2 |= (AN_UF_PAGE2_CL91_REQ_MASK << 8970 AN_UF_PAGE2_CL91_REQ_OFFSET); 8971 } 8972 } 8973 8974 /* Populate the null page */ 8975 an_ctxt->tx_pages.null_page.page_2 = 0; 8976 an_ctxt->tx_pages.null_page.page_1 = 0; 8977 an_ctxt->tx_pages.null_page.page_0 = 1; 8978 8979 return PHYMOD_E_NONE; 8980 8981 } 8982 8983 int tefmod16_25g_rsfec_am_init(PHYMOD_ST *pc) 8984 { 8985 SC_X4_IEEE_25G_CTLr_t ieee_25G_am_reg; 8986 RX_X4_IEEE_25G_PARLLEL_DET_CTRr_t ieee_25g_parallel_det_reg; 8987 SC_X4_MSA_25G_50G_CTLr_t msa_25g_50g_am_reg; 8988 8989 SC_X4_IEEE_25G_CTLr_CLR(ieee_25G_am_reg); 8990 RX_X4_IEEE_25G_PARLLEL_DET_CTRr_CLR(ieee_25g_parallel_det_reg); 8991 SC_X4_MSA_25G_50G_CTLr_CLR(msa_25g_50g_am_reg); 8992 8993 /* Program AM0 value to use 100G AM AM123 should use 40G AM 8994 * which is a default 8995 */ 8996 PHYMOD_IF_ERR_RETURN( 8997 READ_SC_X4_IEEE_25G_CTLr(pc, &ieee_25G_am_reg)); 8998 SC_X4_IEEE_25G_CTLr_IEEE_25G_AM0_FORMATf_SET(ieee_25G_am_reg, 1); 8999 PHYMOD_IF_ERR_RETURN( 9000 WRITE_SC_X4_IEEE_25G_CTLr(pc, ieee_25G_am_reg)); 9001 9002 /* MSA Mode Program 25G AM0 value to use 100G AM 9003 * The rest AM should use 40G AM, which is a default 9004 */ 9005 PHYMOD_IF_ERR_RETURN( 9006 READ_SC_X4_MSA_25G_50G_CTLr(pc, &msa_25g_50g_am_reg)); 9007 SC_X4_MSA_25G_50G_CTLr_MSA_25G_AM0_FORMATf_SET(msa_25g_50g_am_reg, 1); 9008 PHYMOD_IF_ERR_RETURN( 9009 WRITE_SC_X4_MSA_25G_50G_CTLr(pc, msa_25g_50g_am_reg)); 9010 9011 /* Enable AM parallel detect for incase if the legacy devices use 40G AM */ 9012 PHYMOD_IF_ERR_RETURN( 9013 READ_RX_X4_IEEE_25G_PARLLEL_DET_CTRr(pc, &ieee_25g_parallel_det_reg)); 9014 RX_X4_IEEE_25G_PARLLEL_DET_CTRr_SET(ieee_25g_parallel_det_reg, 1); 9015 PHYMOD_IF_ERR_RETURN( 9016 WRITE_RX_X4_IEEE_25G_PARLLEL_DET_CTRr(pc, ieee_25g_parallel_det_reg)); 9017 9018 return PHYMOD_E_NONE; 9019 9020 } 9021 9022 9023 /* clear ECC status register for FEC memory */ 9024 int tefmod16_cl91_ecc_clear(PHYMOD_ST *pc) 9025 { 9026 RX_X1_ECC_STS_FEC_MEM0r_t RX_X1_ECC_STS_FEC_MEM0r_reg; 9027 RX_X1_ECC_STS_FEC_MEM1r_t RX_X1_ECC_STS_FEC_MEM1r_reg; 9028 RX_X1_ECC_STS_FEC_MEM2r_t RX_X1_ECC_STS_FEC_MEM2r_reg; 9029 RX_X1_ECC_STS_FEC_MEM3r_t RX_X1_ECC_STS_FEC_MEM3r_reg; 9030 RX_X1_ECC_INTR_STS_1BITr_t RX_X1_ECC_INTR_STS_1BITr_reg; 9031 RX_X1_ECC_INTR_STS_2BITr_t RX_X1_ECC_INTR_STS_2BITr_reg; 9032 RX_X4_ECC_STS_CL91_BUFFER_BLK0r_t RX_X4_ECC_STS_CL91_BUFFER_BLK0r_reg; 9033 RX_X4_ECC_STS_CL91_BUFFER_BLK1r_t RX_X4_ECC_STS_CL91_BUFFER_BLK1r_reg; 9034 RX_X4_ECC_STS_CL91_BUFFER_BLK2r_t RX_X4_ECC_STS_CL91_BUFFER_BLK2r_reg; 9035 RX_X4_ECC_STS_DESKEW_MEM0r_t RX_X4_ECC_STS_DESKEW_MEM0r_reg; 9036 RX_X4_ECC_STS_DESKEW_MEM1r_t RX_X4_ECC_STS_DESKEW_MEM1r_reg; 9037 RX_X4_ECC_STS_DESKEW_MEM2r_t RX_X4_ECC_STS_DESKEW_MEM2r_reg; 9038 RX_X4_ECC_INTR_STS_1BITr_t RX_X4_ECC_INTR_STS_1BITr_reg; 9039 RX_X4_ECC_INTR_STS_2BITr_t RX_X4_ECC_INTR_STS_2BITr_reg; 9040 phymod_access_t pa_copy; 9041 int lane = 0; 9042 9043 TEFMOD16_DBG_IN_FUNC_INFO(pc); 9044 9045 PHYMOD_MEMCPY(&pa_copy, pc, sizeof(pa_copy)); 9046 RX_X1_ECC_STS_FEC_MEM0r_CLR(RX_X1_ECC_STS_FEC_MEM0r_reg); 9047 RX_X1_ECC_STS_FEC_MEM1r_CLR(RX_X1_ECC_STS_FEC_MEM1r_reg); 9048 RX_X1_ECC_STS_FEC_MEM2r_CLR(RX_X1_ECC_STS_FEC_MEM2r_reg); 9049 RX_X1_ECC_STS_FEC_MEM3r_CLR(RX_X1_ECC_STS_FEC_MEM3r_reg); 9050 RX_X1_ECC_INTR_STS_1BITr_CLR(RX_X1_ECC_INTR_STS_1BITr_reg); 9051 RX_X1_ECC_INTR_STS_2BITr_CLR(RX_X1_ECC_INTR_STS_2BITr_reg); 9052 RX_X4_ECC_STS_CL91_BUFFER_BLK0r_CLR(RX_X4_ECC_STS_CL91_BUFFER_BLK0r_reg); 9053 RX_X4_ECC_STS_CL91_BUFFER_BLK1r_CLR(RX_X4_ECC_STS_CL91_BUFFER_BLK1r_reg); 9054 RX_X4_ECC_STS_CL91_BUFFER_BLK2r_CLR(RX_X4_ECC_STS_CL91_BUFFER_BLK2r_reg); 9055 RX_X4_ECC_STS_DESKEW_MEM0r_CLR(RX_X4_ECC_STS_DESKEW_MEM0r_reg); 9056 RX_X4_ECC_STS_DESKEW_MEM1r_CLR(RX_X4_ECC_STS_DESKEW_MEM1r_reg); 9057 RX_X4_ECC_STS_DESKEW_MEM2r_CLR(RX_X4_ECC_STS_DESKEW_MEM2r_reg); 9058 RX_X4_ECC_INTR_STS_1BITr_CLR(RX_X4_ECC_INTR_STS_1BITr_reg); 9059 RX_X4_ECC_INTR_STS_2BITr_CLR(RX_X4_ECC_INTR_STS_2BITr_reg); 9060 9061 /* Read clear */ 9062 PHYMOD_IF_ERR_RETURN(READ_RX_X1_ECC_STS_FEC_MEM0r(&pa_copy, &RX_X1_ECC_STS_FEC_MEM0r_reg)); 9063 PHYMOD_IF_ERR_RETURN(READ_RX_X1_ECC_STS_FEC_MEM1r(&pa_copy, &RX_X1_ECC_STS_FEC_MEM1r_reg)); 9064 PHYMOD_IF_ERR_RETURN(READ_RX_X1_ECC_STS_FEC_MEM2r(&pa_copy, &RX_X1_ECC_STS_FEC_MEM2r_reg)); 9065 PHYMOD_IF_ERR_RETURN(READ_RX_X1_ECC_STS_FEC_MEM3r(&pa_copy, &RX_X1_ECC_STS_FEC_MEM3r_reg)); 9066 PHYMOD_IF_ERR_RETURN(READ_RX_X1_ECC_INTR_STS_1BITr(&pa_copy, &RX_X1_ECC_INTR_STS_1BITr_reg)); 9067 PHYMOD_IF_ERR_RETURN(READ_RX_X1_ECC_INTR_STS_2BITr(&pa_copy, &RX_X1_ECC_INTR_STS_2BITr_reg)); 9068 9069 for (lane = 0; lane < 4; lane++) { 9070 pa_copy.lane_mask = 0x1 << lane; 9071 PHYMOD_IF_ERR_RETURN(READ_RX_X4_ECC_STS_CL91_BUFFER_BLK0r(&pa_copy, &RX_X4_ECC_STS_CL91_BUFFER_BLK0r_reg)); 9072 PHYMOD_IF_ERR_RETURN(READ_RX_X4_ECC_STS_CL91_BUFFER_BLK1r(&pa_copy, &RX_X4_ECC_STS_CL91_BUFFER_BLK1r_reg)); 9073 PHYMOD_IF_ERR_RETURN(READ_RX_X4_ECC_STS_CL91_BUFFER_BLK2r(&pa_copy, &RX_X4_ECC_STS_CL91_BUFFER_BLK2r_reg)); 9074 PHYMOD_IF_ERR_RETURN(READ_RX_X4_ECC_STS_DESKEW_MEM0r(&pa_copy, &RX_X4_ECC_STS_DESKEW_MEM0r_reg)); 9075 PHYMOD_IF_ERR_RETURN(READ_RX_X4_ECC_STS_DESKEW_MEM1r(&pa_copy, &RX_X4_ECC_STS_DESKEW_MEM1r_reg)); 9076 PHYMOD_IF_ERR_RETURN(READ_RX_X4_ECC_STS_DESKEW_MEM2r(&pa_copy, &RX_X4_ECC_STS_DESKEW_MEM2r_reg)); 9077 PHYMOD_IF_ERR_RETURN(READ_RX_X4_ECC_INTR_STS_1BITr(&pa_copy, &RX_X4_ECC_INTR_STS_1BITr_reg)); 9078 PHYMOD_IF_ERR_RETURN(READ_RX_X4_ECC_INTR_STS_2BITr(&pa_copy, &RX_X4_ECC_INTR_STS_2BITr_reg)); 9079 } 9080 9081 return PHYMOD_E_NONE; 9082 } 9083 9084 /* 9085 Set FEC Bypass Error Indictator. 9086 Note: FEC_bypass_indication_enable has no effect when FEC_bypass_correction_enable is asserted. 9087 */ 9088 int tefmod16_fec_bypass_indication_set(PHYMOD_ST *pc, uint32_t enable) 9089 { 9090 RX_X4_CL91_RX_CTL0r_t RX_X4_CL91_RX_CTL0r_reg; 9091 9092 RX_X4_CL91_RX_CTL0r_CLR(RX_X4_CL91_RX_CTL0r_reg); 9093 9094 RX_X4_CL91_RX_CTL0r_FEC_BYP_IND_ENf_SET(RX_X4_CL91_RX_CTL0r_reg, enable); 9095 PHYMOD_IF_ERR_RETURN(MODIFY_RX_X4_CL91_RX_CTL0r(pc, RX_X4_CL91_RX_CTL0r_reg)); 9096 9097 return PHYMOD_E_NONE; 9098 } 9099 9100 /* Get FEC Bypass Error Indictator */ 9101 int tefmod16_fec_bypass_indication_get(PHYMOD_ST *pc, uint32_t *enable) 9102 { 9103 RX_X4_CL91_RX_CTL0r_t RX_X4_CL91_RX_CTL0r_reg; 9104 9105 RX_X4_CL91_RX_CTL0r_CLR(RX_X4_CL91_RX_CTL0r_reg); 9106 9107 PHYMOD_IF_ERR_RETURN(READ_RX_X4_CL91_RX_CTL0r(pc, &RX_X4_CL91_RX_CTL0r_reg)); 9108 *enable = RX_X4_CL91_RX_CTL0r_FEC_BYP_IND_ENf_GET(RX_X4_CL91_RX_CTL0r_reg); 9109 9110 return PHYMOD_E_NONE; 9111 9112 } 9113 9114 STATIC 9115 int _tefmod16_rx_phy_lane_get(PHYMOD_ST *pc, int rx_logical_lane, 9116 int* rx_phy_lane) 9117 { 9118 RX_X1_RX_LN_SWPr_t rx_lane_swap_reg; 9119 phymod_access_t pa_copy; 9120 9121 PHYMOD_MEMCPY(&pa_copy, pc, sizeof(pa_copy)); 9122 9123 /*always use lane 0 copy since register is single copy */ 9124 pa_copy.lane_mask = 0x1; 9125 9126 PHYMOD_IF_ERR_RETURN 9127 (READ_RX_X1_RX_LN_SWPr(&pa_copy, &rx_lane_swap_reg)); 9128 9129 switch (rx_logical_lane) { 9130 case 0: 9131 *rx_phy_lane = 9132 RX_X1_RX_LN_SWPr_LOGICAL0_TO_PHY_SELf_GET(rx_lane_swap_reg); 9133 break; 9134 case 1: 9135 *rx_phy_lane = 9136 RX_X1_RX_LN_SWPr_LOGICAL1_TO_PHY_SELf_GET(rx_lane_swap_reg); 9137 break; 9138 case 2: 9139 *rx_phy_lane = 9140 RX_X1_RX_LN_SWPr_LOGICAL2_TO_PHY_SELf_GET(rx_lane_swap_reg); 9141 break; 9142 case 3: 9143 *rx_phy_lane = 9144 RX_X1_RX_LN_SWPr_LOGICAL3_TO_PHY_SELf_GET(rx_lane_swap_reg); 9145 break; 9146 default: 9147 return PHYMOD_E_PARAM; 9148 } 9149 return PHYMOD_E_NONE; 9150 } 9151 9152 int tefmod16_synce_stg0_mode_set(PHYMOD_ST *pc, int mode) 9153 { 9154 int start_lane = 0, num_lane = 0, phy_lane = 0; 9155 MAIN0_SYNCE_CTL_STAGE0r_t MAIN0_SYNCE_CTL_STAGE0r_reg; 9156 9157 PHYMOD_IF_ERR_RETURN 9158 (phymod_util_lane_config_get(pc, &start_lane, &num_lane)); 9159 9160 MAIN0_SYNCE_CTL_STAGE0r_CLR(MAIN0_SYNCE_CTL_STAGE0r_reg); 9161 9162 PHYMOD_IF_ERR_RETURN 9163 (_tefmod16_rx_phy_lane_get(pc, start_lane, &phy_lane)); 9164 9165 PHYMOD_IF_ERR_RETURN(READ_MAIN0_SYNCE_CTL_STAGE0r(pc, 9166 &MAIN0_SYNCE_CTL_STAGE0r_reg)); 9167 9168 switch(phy_lane) { 9169 case 0: 9170 MAIN0_SYNCE_CTL_STAGE0r_SYNCE_STAGE0_MODE_PHY_LANE0f_SET( 9171 MAIN0_SYNCE_CTL_STAGE0r_reg, mode); 9172 break; 9173 case 1: 9174 MAIN0_SYNCE_CTL_STAGE0r_SYNCE_STAGE0_MODE_PHY_LANE1f_SET( 9175 MAIN0_SYNCE_CTL_STAGE0r_reg, mode); 9176 break; 9177 case 2: 9178 MAIN0_SYNCE_CTL_STAGE0r_SYNCE_STAGE0_MODE_PHY_LANE2f_SET( 9179 MAIN0_SYNCE_CTL_STAGE0r_reg, mode); 9180 break; 9181 case 3: 9182 MAIN0_SYNCE_CTL_STAGE0r_SYNCE_STAGE0_MODE_PHY_LANE3f_SET( 9183 MAIN0_SYNCE_CTL_STAGE0r_reg, mode); 9184 break; 9185 default: 9186 return PHYMOD_E_PARAM; 9187 } 9188 9189 PHYMOD_IF_ERR_RETURN(MODIFY_MAIN0_SYNCE_CTL_STAGE0r(pc, 9190 MAIN0_SYNCE_CTL_STAGE0r_reg)); 9191 9192 return PHYMOD_E_NONE; 9193 } 9194 9195 int tefmod16_synce_stg1_mode_set(PHYMOD_ST *pc, int mode) 9196 { 9197 int start_lane = 0, num_lane = 0, phy_lane = 0; 9198 MAIN0_SYNCE_CTLr_t MAIN0_SYNCE_CTLr_reg; 9199 9200 PHYMOD_IF_ERR_RETURN 9201 (phymod_util_lane_config_get(pc, &start_lane, &num_lane)); 9202 9203 MAIN0_SYNCE_CTLr_CLR(MAIN0_SYNCE_CTLr_reg); 9204 9205 PHYMOD_IF_ERR_RETURN 9206 (_tefmod16_rx_phy_lane_get(pc, start_lane, &phy_lane)); 9207 9208 PHYMOD_IF_ERR_RETURN(READ_MAIN0_SYNCE_CTLr(pc, &MAIN0_SYNCE_CTLr_reg)); 9209 9210 switch(phy_lane) { 9211 case 0: 9212 MAIN0_SYNCE_CTLr_SYNCE_MODE_PHY_LANE0f_SET( 9213 MAIN0_SYNCE_CTLr_reg, mode); 9214 break; 9215 case 1: 9216 MAIN0_SYNCE_CTLr_SYNCE_MODE_PHY_LANE1f_SET( 9217 MAIN0_SYNCE_CTLr_reg, mode); 9218 break; 9219 case 2: 9220 MAIN0_SYNCE_CTLr_SYNCE_MODE_PHY_LANE2f_SET( 9221 MAIN0_SYNCE_CTLr_reg, mode); 9222 break; 9223 case 3: 9224 MAIN0_SYNCE_CTLr_SYNCE_MODE_PHY_LANE3f_SET( 9225 MAIN0_SYNCE_CTLr_reg, mode); 9226 break; 9227 default: 9228 return PHYMOD_E_PARAM; 9229 } 9230 9231 PHYMOD_IF_ERR_RETURN(MODIFY_MAIN0_SYNCE_CTLr(pc, MAIN0_SYNCE_CTLr_reg)); 9232 9233 return PHYMOD_E_NONE; 9234 } 9235 9236 int tefmod16_synce_clk_ctrl_set(PHYMOD_ST *pc, uint32_t val) 9237 { 9238 int start_lane = 0, num_lane = 0, phy_lane = 0; 9239 phymod_access_t pa_copy; 9240 RX_X4_SYNCE_FRACTIONAL_DIVr_t RX_X4_SYNCE_FRACTIONAL_DIVr_reg; 9241 9242 PHYMOD_IF_ERR_RETURN 9243 (phymod_util_lane_config_get(pc, &start_lane, &num_lane)); 9244 9245 PHYMOD_IF_ERR_RETURN 9246 (_tefmod16_rx_phy_lane_get(pc, start_lane, &phy_lane)); 9247 9248 PHYMOD_MEMCPY(&pa_copy, pc, sizeof(pa_copy)); 9249 pa_copy.lane_mask = 0x1 << phy_lane; 9250 9251 RX_X4_SYNCE_FRACTIONAL_DIVr_CLR(RX_X4_SYNCE_FRACTIONAL_DIVr_reg); 9252 RX_X4_SYNCE_FRACTIONAL_DIVr_SET(RX_X4_SYNCE_FRACTIONAL_DIVr_reg, val); 9253 PHYMOD_IF_ERR_RETURN(MODIFY_RX_X4_SYNCE_FRACTIONAL_DIVr(&pa_copy, 9254 RX_X4_SYNCE_FRACTIONAL_DIVr_reg)); 9255 9256 return PHYMOD_E_NONE; 9257 } 9258 9259 int tefmod16_synce_stg0_mode_get(PHYMOD_ST *pc, int *mode) 9260 { 9261 int start_lane = 0, num_lane = 0, phy_lane = 0; 9262 MAIN0_SYNCE_CTL_STAGE0r_t MAIN0_SYNCE_CTL_STAGE0r_reg; 9263 9264 PHYMOD_IF_ERR_RETURN 9265 (phymod_util_lane_config_get(pc, &start_lane, &num_lane)); 9266 9267 MAIN0_SYNCE_CTL_STAGE0r_CLR(MAIN0_SYNCE_CTL_STAGE0r_reg); 9268 9269 PHYMOD_IF_ERR_RETURN 9270 (_tefmod16_rx_phy_lane_get(pc, start_lane, &phy_lane)); 9271 9272 PHYMOD_IF_ERR_RETURN(READ_MAIN0_SYNCE_CTL_STAGE0r(pc, 9273 &MAIN0_SYNCE_CTL_STAGE0r_reg)); 9274 9275 switch(phy_lane) { 9276 case 0: 9277 *mode = MAIN0_SYNCE_CTL_STAGE0r_SYNCE_STAGE0_MODE_PHY_LANE0f_GET( 9278 MAIN0_SYNCE_CTL_STAGE0r_reg); 9279 break; 9280 case 1: 9281 *mode = MAIN0_SYNCE_CTL_STAGE0r_SYNCE_STAGE0_MODE_PHY_LANE1f_GET( 9282 MAIN0_SYNCE_CTL_STAGE0r_reg); 9283 break; 9284 case 2: 9285 *mode = MAIN0_SYNCE_CTL_STAGE0r_SYNCE_STAGE0_MODE_PHY_LANE2f_GET( 9286 MAIN0_SYNCE_CTL_STAGE0r_reg); 9287 break; 9288 case 3: 9289 *mode = MAIN0_SYNCE_CTL_STAGE0r_SYNCE_STAGE0_MODE_PHY_LANE3f_GET( 9290 MAIN0_SYNCE_CTL_STAGE0r_reg); 9291 break; 9292 default: 9293 return PHYMOD_E_PARAM; 9294 } 9295 9296 return PHYMOD_E_NONE; 9297 } 9298 9299 int tefmod16_synce_stg1_mode_get(PHYMOD_ST *pc, int *mode) 9300 { 9301 int start_lane = 0, num_lane = 0, phy_lane = 0; 9302 MAIN0_SYNCE_CTLr_t MAIN0_SYNCE_CTLr_reg; 9303 9304 PHYMOD_IF_ERR_RETURN 9305 (phymod_util_lane_config_get(pc, &start_lane, &num_lane)); 9306 9307 MAIN0_SYNCE_CTLr_CLR(MAIN0_SYNCE_CTLr_reg); 9308 9309 PHYMOD_IF_ERR_RETURN 9310 (_tefmod16_rx_phy_lane_get(pc, start_lane, &phy_lane)); 9311 9312 PHYMOD_IF_ERR_RETURN(READ_MAIN0_SYNCE_CTLr(pc, &MAIN0_SYNCE_CTLr_reg)); 9313 9314 switch(phy_lane) { 9315 case 0: 9316 *mode = MAIN0_SYNCE_CTLr_SYNCE_MODE_PHY_LANE0f_GET( 9317 MAIN0_SYNCE_CTLr_reg); 9318 break; 9319 case 1: 9320 *mode = MAIN0_SYNCE_CTLr_SYNCE_MODE_PHY_LANE1f_GET( 9321 MAIN0_SYNCE_CTLr_reg); 9322 break; 9323 case 2: 9324 *mode = MAIN0_SYNCE_CTLr_SYNCE_MODE_PHY_LANE2f_GET( 9325 MAIN0_SYNCE_CTLr_reg); 9326 break; 9327 case 3: 9328 *mode = MAIN0_SYNCE_CTLr_SYNCE_MODE_PHY_LANE3f_GET( 9329 MAIN0_SYNCE_CTLr_reg); 9330 break; 9331 default: 9332 return PHYMOD_E_PARAM; 9333 } 9334 return PHYMOD_E_NONE; 9335 } 9336 9337 int tefmod16_synce_clk_ctrl_get(PHYMOD_ST *pc, uint32_t *val) 9338 { 9339 int start_lane = 0, num_lane = 0, phy_lane = 0; 9340 phymod_access_t pa_copy; 9341 RX_X4_SYNCE_FRACTIONAL_DIVr_t RX_X4_SYNCE_FRACTIONAL_DIVr_reg; 9342 9343 PHYMOD_IF_ERR_RETURN 9344 (phymod_util_lane_config_get(pc, &start_lane, &num_lane)); 9345 9346 PHYMOD_IF_ERR_RETURN 9347 (_tefmod16_rx_phy_lane_get(pc, start_lane, &phy_lane)); 9348 9349 PHYMOD_MEMCPY(&pa_copy, pc, sizeof(pa_copy)); 9350 pa_copy.lane_mask = 0x1 << phy_lane; 9351 9352 RX_X4_SYNCE_FRACTIONAL_DIVr_CLR(RX_X4_SYNCE_FRACTIONAL_DIVr_reg); 9353 9354 PHYMOD_IF_ERR_RETURN(READ_RX_X4_SYNCE_FRACTIONAL_DIVr(&pa_copy, 9355 &RX_X4_SYNCE_FRACTIONAL_DIVr_reg)); 9356 9357 *val = RX_X4_SYNCE_FRACTIONAL_DIVr_GET(RX_X4_SYNCE_FRACTIONAL_DIVr_reg); 9358 9359 return PHYMOD_E_NONE; 9360 } 9361 9362 #endif /* _SDK_TEFMOD16_ */