tefmod16.h (27546B)
1 /*---------------------------------------------------------------------- 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * $Copyright: (c) 2014 Broadcom Corporation All Rights Reserved.$ 8 * Broadcom Corporation 9 * Proprietary and Confidential information 10 * All rights reserved 11 * This source file is the property of Broadcom Corporation, and 12 * may not be copied or distributed in any isomorphic form without the 13 * prior written consent of Broadcom Corporation. 14 *---------------------------------------------------------------------- 15 * Description: define enumerators 16 *----------------------------------------------------------------------*/ 17 /* 18 * 19 * $Copyright: 20 * All Rights Reserved.$ 21 */ 22 23 #ifndef _tefmod16_H_ 24 #define _tefmod16_H_ 25 26 #ifndef _DV_TB_ 27 #define _SDK_TEFMOD16_ 1 28 #endif 29 30 #ifdef _DV_TB_ 31 #ifdef LINUX 32 #include <stdint.h> 33 #endif 34 #include <stdio.h> 35 #include <string.h> 36 #include <stdlib.h> 37 #include "errno.h" 38 #endif 39 40 #ifdef _SDK_TEFMOD16_ 41 #include <phymod/phymod.h> 42 #include <phymod/phymod_debug.h> 43 #include "tefmod16_enum_defines.h" 44 #endif 45 46 #ifdef _SDK_TEFMOD16_ 47 #define PHYMOD_ST const phymod_access_t 48 #else 49 #define PHYMOD_ST tefmod16_st 50 #endif 51 52 #define TEFMOD16_FEC_NOT_SUPRTD 0 53 #define TEFMOD16_FEC_SUPRTD_NOT_REQSTD 1 54 #define TEFMOD16_FEC_CL74_SUPRTD_REQSTD 4 55 #define TEFMOD16_FEC_CL91_SUPRTD_REQSTD 8 56 57 /* matching SOC_PHY_CONTROL_FEC_OFF 58 * SOC_PHY_CONTROL_FEC_ON 59 * SOC_PHY_CONTROL_FEC_AUTO 60 */ 61 #define TEFMOD16_PHY_CONTROL_FEC_OFF 0 62 #define TEFMOD16_PHY_CONTROL_FEC_ON 1 63 #define TEFMOD16_PHY_CONTROL_FEC_AUTO 2 64 #define TEFMOD16_PHY_CONTROL_FEC_MASK 3 65 66 /* So far 4 bits debug mask are used by TEFMOD16 */ 67 #define TEFMOD16_DBG_MEM (1L << 4) /* allocation/object */ 68 #define TEFMOD16_DBG_REGACC (1L << 3) /* Print all register accesses */ 69 #define TEFMOD16_DBG_FUNCVALOUT (1L << 2) /* All values returned by Tier1*/ 70 #define TEFMOD16_DBG_FUNCVALIN (1L << 1) /* All values pumped into Tier1*/ 71 #define TEFMOD16_DBG_FUNC (1L << 0) /* Every time we enter a Tier1*/ 72 73 #define TEFMOD16_VCO_RATE_15G 22500 74 75 76 typedef enum { 77 TEFMOD16_AN_MODE_CL73 = 0, 78 TEFMOD16_AN_MODE_CL73_BAM, 79 TEFMOD16_AN_MODE_HPAM, 80 TEFMOD16_AN_MODE_MSA, 81 TEFMOD16_AN_MODE_CL73_MSA, 82 TEFMOD16_AN_MODE_NONE, 83 TEFMOD16_AN_MODE_TYPE_COUNT 84 }tefmod16_an_mode_type_t; 85 86 87 typedef enum { 88 TEFMOD16_AN_SET_RF_DISABLE = 0, 89 TEFMOD16_AN_SET_SGMII_SPEED, 90 TEFMOD16_AN_SET_SGMII_MASTER, 91 TEFMOD16_AN_SET_HG_MODE, 92 TEFMOD16_AN_SET_FEC_MODE, 93 TEFMOD16_AN_SET_CL72_MODE, 94 TEFMOD16_AN_SET_CL37_ATTR, 95 TEFMOD16_AN_SET_CL48_SYNC, 96 TEFMOD16_AN_SET_LK_FAIL_INHIBIT_TIMER_NO_CL72, 97 TEFMOD16_AN_SET_CL73_FEC_OFF, 98 TEFMOD16_AN_SET_CL73_FEC_ON, 99 TEFMOD16_AN_SET_SPEED_PAUSE, 100 TEFMOD16_AN_SET_TYPE_COUNT 101 }tefmod16_an_set_type_t; 102 103 typedef union { 104 int tefmod16_an_set_rf_disable; 105 int tefmod16_an_set_sgmii_speed; 106 int tefmod16_an_set_sgmii_master; 107 tefmod16_an_set_type_t tefmod16_an_set_cl37_attr; 108 }tefmod16_an_set_value_t; 109 110 typedef enum { 111 TEFMOD16_CL73_10GBASE_KR1 = 0, 112 TEFMOD16_CL73_40GBASE_KR4, 113 TEFMOD16_CL73_40GBASE_CR4, 114 TEFMOD16_CL73_100GBASE_KR4, 115 TEFMOD16_CL73_100GBASE_CR4, 116 TEFMOD16_CL73_1GBASE_KX, 117 TEFMOD16_CL73_25GBASE_KR1, 118 TEFMOD16_CL73_25GBASE_CR1, 119 TEFMOD16_CL73_25GBASE_KRS1, 120 TEFMOD16_CL73_25GBASE_CRS1, 121 TEFMOD16_CL73_50GBASE_KR2, 122 TEFMOD16_CL73_50GBASE_CR2, 123 TEFMOD16_CL73_SPEED_COUNT 124 }tefmod16_cl73_speed_t; 125 126 typedef enum { 127 TEFMOD16_CL73_BAM_20GBASE_KR2 = 0, 128 TEFMOD16_CL73_BAM_20GBASE_CR2, 129 TEFMOD16_CL73_BAM_40GBASE_KR2, 130 TEFMOD16_CL73_BAM_40GBASE_CR2, 131 TEFMOD16_CL73_BAM_RESERVED_1, 132 TEFMOD16_CL73_BAM_RESERVED_2, 133 TEFMOD16_CL73_BAM_50GBASE_KR2, 134 TEFMOD16_CL73_BAM_50GBASE_CR2, 135 TEFMOD16_CL73_BAM_50GBASE_KR4, 136 TEFMOD16_CL73_BAM_50GBASE_CR4, 137 TEFMOD16_CL73_BAM_SPEED_COUNT 138 }tefmod16_cl73_bam_speed_t; 139 140 typedef enum { 141 TEFMOD16_CL73_BAM_20GBASE_KR1 = 1, 142 TEFMOD16_CL73_BAM_20GBASE_CR1, 143 TEFMOD16_CL73_BAM_25GBASE_KR1, 144 TEFMOD16_CL73_BAM_25GBASE_CR1, 145 TEFMOD16_CL73_BAM_SPEED1_COUNT 146 }tefmod16_cl73_bam_speed1_t; 147 148 typedef enum { 149 TEFMOD16_NO_PAUSE = 0, 150 TEFMOD16_SYMM_PAUSE, 151 TEFMOD16_ASYM_PAUSE, 152 TEFMOD16_ASYM_SYMM_PAUSE, 153 TEFMOD16_AN_PAUSE_COUNT 154 }tefmod16_an_pause_t; 155 156 typedef enum { 157 OVERRIDE_CLEAR = 0x0000, 158 OVERRIDE_NUM_LANES = 0x0001, 159 OVERRIDE_OS_MODE = 0x0002, 160 OVERRIDE_T_FIFO_MODE = 0x0004, 161 OVERRIDE_T_ENC_MODE = 0x0008, 162 OVERRIDE_T_HG2_ENABLE = 0x0010, 163 OVERRIDE_T_PMA_BTMX_MODE_OEN = 0x0020, 164 OVERRIDE_SCR_MODE = 0x0040, 165 OVERRIDE_DESCR_MODE_OEN = 0x0100, 166 OVERRIDE_DEC_TL_MODE = 0x0200, 167 OVERRIDE_DESKEW_MODE = 0x0400, 168 OVERRIDE_DEC_FSM_MODE = 0x0800, 169 OVERRIDE_R_HG2_ENABLE = 0x8001, 170 OVERRIDE_BS_SM_SYNC_MODE_OEN = 0x8002, 171 OVERRIDE_BS_SYNC_EN_OEN = 0x8004, 172 OVERRIDE_BS_DIST_MODE_OEN = 0x8008, 173 OVERRIDE_BS_BTMX_MODE_OEN = 0x8010, 174 OVERRIDE_CL72_EN = 0x8020, 175 OVERRIDE_CLOCKCNT0 = 0xf040, 176 OVERRIDE_CLOCKCNT1 = 0x8080, 177 OVERRIDE_LOOPCNT0 = 0x8100, 178 OVERRIDE_LOOPCNT1 = 0x8200, 179 OVERRIDE_MAC_CREDITGENCNT = 0x8400, 180 OVERRIDE_NUM_LANES_DIS = 0xff01, 181 OVERRIDE_OS_MODE_DIS = 0xff02, 182 OVERRIDE_T_FIFO_MODE_DIS = 0xff03, 183 OVERRIDE_T_ENC_MODE_DIS = 0xff04, 184 OVERRIDE_T_HG2_ENABLE_DIS = 0xff05, 185 OVERRIDE_T_PMA_BTMX_MODE_OEN_DIS= 0xff06, 186 OVERRIDE_SCR_MODE_DIS = 0xff07, 187 OVERRIDE_DESCR_MODE_OEN_DIS = 0xff08, 188 OVERRIDE_DEC_TL_MODE_DIS = 0xff09, 189 OVERRIDE_DESKEW_MODE_DIS = 0xff0a, 190 OVERRIDE_DEC_FSM_MODE_DIS = 0xff0b, 191 OVERRIDE_R_HG2_ENABLE_DIS = 0xff0c, 192 OVERRIDE_BS_SM_SYNC_MODE_OEN_DIS= 0xff0d, 193 OVERRIDE_BS_SYNC_EN_OEN_DIS = 0xff0e, 194 OVERRIDE_BS_DIST_MODE_OEN_DIS = 0xff0f, 195 OVERRIDE_BS_BTMX_MODE_OEN_DIS = 0xff10, 196 OVERRIDE_CL72_EN_DIS = 0xff11, 197 OVERRIDE_CLOCKCNT0_DIS = 0xff12, 198 OVERRIDE_CLOCKCNT1_DIS = 0xff13, 199 OVERRIDE_LOOPCNT0_DIS = 0xff14, 200 OVERRIDE_LOOPCNT1_DIS = 0xff15, 201 OVERRIDE_MAC_CREDITGENCNT_DIS = 0xff16 202 } override_type_t; 203 204 typedef enum { 205 TEFMOD16_HG2_CODEC_OFF = 0, 206 TEFMOD16_HG2_CODEC_ON_8BYTE_IPG, 207 TEFMOD16_HG2_CODEC_ON_9BYTE_IPG, 208 TEFMOD16_HG2_CODEC_COUNT 209 }tefmod16_hg2_codec_t; 210 211 /** 212 \struct tefmod16_an_adv_ability_s 213 TBD 214 */ 215 216 typedef struct tefmod16_an_adv_ability_s{ 217 tefmod16_cl73_speed_t an_base_speed; 218 tefmod16_cl73_bam_speed_t an_bam_speed; 219 tefmod16_cl73_bam_speed1_t an_bam_speed1; 220 uint16_t an_nxt_page; 221 tefmod16_an_pause_t an_pause; 222 uint16_t an_fec; 223 uint16_t an_cl72; 224 uint16_t an_hg2; 225 }tefmod16_an_adv_ability_t; 226 227 typedef struct tefmod16_an_ability_s{ 228 tefmod16_an_adv_ability_t cl73_adv; /*includes cl73 and cl73-bam related */ 229 }tefmod16_an_ability_t; 230 231 /** 232 \struct tefmod16_an_oui_s 233 oui : New oui 234 override_bam73_adv : Adv new OUI for BAM73 235 override_bam73_det : Detect new OUI for BAM73 236 override_hpam_adv : Adv new OUI for HPAM 237 override_hpam_det : Detect new OUI for HPAM 238 */ 239 typedef struct tefmod16_an_oui_s { 240 uint32_t oui; 241 uint16_t oui_override_bam73_adv; 242 uint16_t oui_override_bam73_det; 243 uint16_t oui_override_hpam_adv; 244 uint16_t oui_override_hpam_det; 245 } tefmod16_an_oui_t; 246 247 typedef struct tefmod16_an_control_s { 248 tefmod16_an_mode_type_t an_type; 249 uint16_t num_lane_adv; 250 uint16_t enable; 251 uint16_t pd_kx_en; 252 an_property_enable an_property_type; 253 uint16_t cl72_config_allowed; 254 } tefmod16_an_control_t; 255 256 /** 257 \struct tefmod16_an_init_s 258 259 This embodies all parameters required to program autonegotiation features in the 260 PHY for both CL37 and CL73 type autonegotiation and the BAM variants. 261 For details of individual fields, please refer to microarchitectural doc. 262 */ 263 typedef struct tefmod16_an_init_s{ 264 uint16_t an_fail_cnt; 265 uint16_t linkfailtimer_dis; 266 uint16_t linkfailtimerqua_en; 267 uint16_t an_good_check_trap; 268 uint16_t an_good_trap; 269 uint16_t bam73_adv_oui; 270 uint16_t bam73_det_oui; 271 uint16_t hpam_adv_oui; 272 uint16_t hpam_det_oui; 273 uint16_t disable_rf_report; 274 uint16_t cl73_remote_fault; 275 uint16_t cl73_nonce_match_over; 276 uint16_t cl73_nonce_match_val; 277 uint16_t cl73_transmit_nonce; 278 uint16_t base_selector; 279 } tefmod16_an_init_t; 280 281 typedef enum { 282 TEFMOD16_NO_CL91_FEC = 0, 283 TEFMOD16_CL91_SINGLE_LANE_FC, 284 TEFMOD16_CL91_SINGLE_LANE_BRCM_PROP, 285 TEFMOD16_CL91_DUAL_LANE_BRCM_PROP, 286 TEFMOD16_CL91_QUAD_LANE, 287 TEFMOD16_IEEE_25G_CL91_SINGLE_LANE, 288 TEFMOD16_CL91_COUNT 289 }tefmod16_cl91_fec_mode_t; 290 291 typedef enum { 292 TEFMOD16_NO_OVERRIDE = 0, 293 TEFMOD16_NO_FEC, 294 TEFMOD16_FEC_CL74, 295 TEFMOD16_FEC_CL91 296 }tefmod16_an_fec_sel_override_t; 297 298 299 /** 300 \struct tefmod16_an_timers_s 301 TBD 302 */ 303 typedef struct tefmod16_an_timers_s{ 304 uint16_t value; 305 } tefmod16_an_timers_t; 306 307 /* definitions for SW AN PAGE */ 308 #define BRCM_OUI 0xAF7 309 #define BRCM_BAM_CODE 0x3 310 #define HP_OUI 0x643150 311 #define HP_USR_DEF_FIELD 0xABE20 312 #define MSA_OUI 0x6A737D /* OUI defined for consortium 25G */ 313 #define MSA_OUI_13to23 0x353 314 #define MSA_OUT_2to12 0x4DF 315 #define MSA_OUI_0to1 0x1 316 #define EXT_TECH_ABILITY_CODE 0x3 317 #define MSA_MSG_CODE 0x5 318 319 320 /* Below macros are defined based on IEEE and MSA 25G spec 321 * for detailed information Please refer to the 322 * IEEE 802.3by section 73.6 Link codeword encoding 323 * MSA Spec section 3.2.5 Auto-negotiation Figure 10 324 */ 325 326 #define AN_BASE0_PAGE_IEEE_SEL_MASK 0x1F 327 #define AN_BASE0_PAGE_IEEE_SEL_OFFSET 0x0 328 329 #define AN_BASE0_PAGE_CL73_NOUNCE_MASK 0x1F 330 #define AN_BASE0_PAGE_CL73_NOUNCE_OFFSET 0x5 331 332 /* pause capability not related to PHY */ 333 #define AN_BASE0_PAGE_CAP_MASK 0x3 334 #define AN_BASE0_PAGE_CAP_OFFSET 0xA 335 336 #define AN_BASE0_PAGE_REMOTE_FAULT_MASK 0x1 337 #define AN_BASE0_PAGE_REMOTE_FAULT_OFFSET 0xD 338 339 /* acknowledgement bit postion */ 340 #define AN_BASE0_PAGE_ACK_MASK 0x1 341 #define AN_BASE0_PAGE_ACK_OFFSET 0xE 342 343 /* Next Page bit postion */ 344 #define AN_BASE0_PAGE_NP_MASK 0x1 345 #define AN_BASE0_PAGE_NP_OFFSET 0xF 346 347 348 #define AN_BASE1_PAGE_TX_NOUNCE_MASK 0x1F 349 #define AN_BASE1_PAGE_TX_NOUNCE_OFFSET 0x0 350 351 #define AN_BASE1_PAGE_ABILITY_MASK 0x7FF 352 #define AN_BASE1_PAGE_ABILITY_OFFSET 0x5 353 354 #define AN_BASE_TECH_ABILITY_1000KX_MASK 0x1 355 #define AN_BASE_TECH_ABILITY_1000KX_OFFSET 0x5 356 357 #define AN_BASE_TECH_ABILITY_10GKX4_MASK 0x1 358 #define AN_BASE_TECH_ABILITY_10GKX4_OFFSET 0x6 359 360 #define AN_BASE_TECH_ABILITY_10GKR_MASK 0x1 361 #define AN_BASE_TECH_ABILITY_10GKR_OFFSET 0x7 362 363 #define AN_BASE_TECH_ABILITY_40GKR4_MASK 0x1 364 #define AN_BASE_TECH_ABILITY_40GKR4_OFFSET 0x8 365 366 #define AN_BASE_TECH_ABILITY_40GCR4_MASK 0x1 367 #define AN_BASE_TECH_ABILITY_40GCR4_OFFSET 0x9 368 369 #define AN_BASE_TECH_ABILITY_100GCR10_MASK 0x1 370 #define AN_BASE_TECH_ABILITY_100GCR10_OFFSET 0xA 371 372 #define AN_BASE_TECH_ABILITY_100GKP4_MASK 0x1 373 #define AN_BASE_TECH_ABILITY_100GKP4_OFFSET 0xB 374 375 #define AN_BASE_TECH_ABILITY_100GKR4_MASK 0x1 376 #define AN_BASE_TECH_ABILITY_100GKR4_OFFSET 0xC 377 378 #define AN_BASE_TECH_ABILITY_100GCR4_MASK 0x1 379 #define AN_BASE_TECH_ABILITY_100GCR4_OFFSET 0xD 380 381 #define AN_BASE_TECH_ABILITY_25GKRS_MASK 0x1 382 #define AN_BASE_TECH_ABILITY_25GKRS_OFFSET 0xE 383 384 #define AN_BASE_TECH_ABILITY_25GKR_MASK 0x1 385 #define AN_BASE_TECH_ABILITY_25GKR_OFFSET 0xF 386 387 #define AN_BASE2_PAGE_ABILITY_RSVD_MASK 0xFF7 388 #define AN_BASE2_PAGE_ABILITY_RSVD_OFFSET 0x0 389 390 #define AN_BASE2_PAGE_FEC_ABILITY_MASK 0xF 391 #define AN_BASE2_PAGE_FEC_ABILITY_OFFSET 0xC 392 393 #define AN_BASE_CL74_ABILITY_SUP_MASK 0x1 394 #define AN_BASE_CL74_ABILITY_SUP_OFFSET 0xE 395 396 #define AN_BASE_CL74_ABILITY_REQ_MASK 0x1 397 #define AN_BASE_CL74_ABILITY_REQ_OFFSET 0xF 398 399 #define AN_BASE_CL91_ABILITY_REQ_MASK 0x1 400 #define AN_BASE_CL91_ABILITY_REQ_OFFSET 0xC 401 402 #define AN_BASE_CL74_25GKRS_REQ_MASK 0x1 403 #define AN_BASE_CL74_25GKRS_REQ_OFFSET 0xD 404 405 /* Message Page definitions */ 406 407 #define AN_MSG_PAGE0_MSG_CODE_MASK 0x3FF 408 #define AN_MSG_PAGE0_MSG_CODE_OFFSET 0x0 409 410 #define AN_MSG_PAGE0_TOGGLE_MASK 0x1 411 #define AN_MSG_PAGE0_TOGGLE_OFFSET 0xB 412 413 #define AN_MSG_PAGE0_ACK2_MASK 0x1 414 #define AN_MSG_PAGE0_ACK2_OFFSET 0xC 415 416 #define AN_MSG_PAGE0_MSG_PAGE_MASK 0x1 417 #define AN_MSG_PAGE0_MSG_PAGE_OFFSET 0xD 418 419 #define AN_MSG_PAGE0_ACK_MASK 0x1 420 #define AN_MSG_PAGE0_ACK_OFFSET 0xE 421 422 #define AN_MSG_PAGE0_NP_MASK 0x1 423 #define AN_MSG_PAGE0_NP_OFFSET 0xF 424 425 #define AN_MSG_PAGE1_OUI_13to23_MASK 0x7FF 426 #define AN_MSG_PAGE1_OUI_13to23_OFFSET 0x0 427 428 #define AN_MSG_PAGE2_OUI_2to12_MASK 0x7FF 429 #define AN_MSG_PAGE2_OUI_2to12_OFFSET 0x0 430 431 /* Unformatted Page for MSA */ 432 433 #define AN_UF_PAGE0_EXT_TECH_ABILITY_MASK 0xFF 434 #define AN_UF_PAGE0_EXT_TECH_ABILITY_OFFSET 0x0 435 436 #define AN_UF_PAGE0_OUI_MASK 0x3 437 #define AN_UF_PAGE0_OUI_OFFSET 0x9 438 439 #define AN_UF_PAGE0_TOGGLE_MASK 0x1 440 #define AN_UF_PAGE0_TOGGLE_OFFSET 0xB 441 442 #define AN_UF_PAGE0_ACK_MASK 0x1 443 #define AN_UF_PAGE0_ACK_OFFSET 0xE 444 445 #define AN_UF_PAGE0_NP_MASK 0x1 446 #define AN_UF_PAGE0_NP_OFFSET 0xF 447 448 #define AN_UF_PAGE1_25G_KR1_ABILITY_MASK 0x1 449 #define AN_UF_PAGE1_25G_KR1_ABILITY_OFFSET 0x4 450 451 #define AN_UF_PAGE1_25G_CR1_ABILITY_MASK 0x1 452 #define AN_UF_PAGE1_25G_CR1_ABILITY_OFFSET 0x5 453 454 #define AN_UF_PAGE1_50G_KR2_ABILITY_MASK 0x1 455 #define AN_UF_PAGE1_50G_KR2_ABILITY_OFFSET 0x8 456 457 #define AN_UF_PAGE1_50G_CR2_ABILITY_MASK 0x1 458 #define AN_UF_PAGE1_50G_CR2_ABILITY_OFFSET 0x9 459 460 #define AN_UF_PAGE2_CL91_SUPPORT_MASK 0x1 461 #define AN_UF_PAGE2_CL91_SUPPORT_OFFSET 0x8 462 463 #define AN_UF_PAGE2_CL74_SUPPORT_MASK 0x1 464 #define AN_UF_PAGE2_CL74_SUPPORT_OFFSET 0x9 465 466 #define AN_UF_PAGE2_CL91_REQ_MASK 0x1 467 #define AN_UF_PAGE2_CL91_REQ_OFFSET 0xA 468 469 #define AN_UF_PAGE2_CL74_REQ_MASK 0x1 470 #define AN_UF_PAGE2_CL74_REQ_OFFSET 0xB 471 472 #define TEFMOD16_25G_KR_IEEE_SPD_IF 0x72 473 #define TEFMOD16_25G_KRS_IEEE_SPD_IF 0x73 474 475 #define TEFMOD16_25G_KR_SPD_IF 0x11 476 #define TEFMOD16_25G_CR_SPD_IF 0x10 477 478 #define TEFMOD16_50G_KR2_SPD_IF 0x31 479 #define TEFMOD16_50G_CR2_SPD_IF 0x30 480 481 #define TEFMOD16_100G_KR4_SPD_IF 0x41 482 #define TEFMOD16_100G_CR4_SPD_IF 0x40 483 484 #define HCD_SPEED_ID_UNDEFINED 0xFF 485 486 typedef enum ieee_sel_e { 487 IEEE_SEL_RSVD = 0, 488 IEEE_SEL_802P3, 489 IEEE_SEL_802P9, 490 IEEE_SEL_802P5, 491 IEEE_SEL_1394 492 } ieee_sel_t; 493 494 typedef enum an_page_id_e { 495 TEFMOD16_AN_PAGE_ID_NONE = 0, 496 TEFMOD16_AN_PAGE_ID_BASE_PAGE, 497 TEFMOD16_AN_PAGE_ID_MSG_PAGE, 498 TEFMOD16_AN_PAGE_ID_UP_PAGE, 499 TEFMOD16_AN_PAGE_ID_NULL_PAGE, 500 TEFMOD16_AN_PAGE_ID_MAX 501 } an_page_id_t; 502 503 #ifdef CHECKIFNEEDED 504 505 extern int get_mapped_speed(tefmod16_spd_intfc_type spd_intf, int *speed); 506 extern int get_actual_speed(int speed_id, int *speed); 507 508 #endif 509 extern int phymod_debug_check(uint32_t flags, PHYMOD_ST *pc); 510 511 extern int configure_st_entry(int st_entry_num, int st_entry_speed, PHYMOD_ST* pc); 512 513 extern int tefmod16_pmd_osmode_set(PHYMOD_ST* pc, tefmod16_spd_intfc_type_t spd_intf, phymod_ref_clk_t refclk, int os_mode); 514 extern int tefmod16_pmd_x4_reset(PHYMOD_ST* pc); 515 extern int tefmod16_pmd_x4_reset_get(PHYMOD_ST* pc, int *is_in_reset); 516 extern int tefmod16_tx_loopback_get(PHYMOD_ST* pc, uint32_t *enable); 517 extern int tefmod16_firmware_set(PHYMOD_ST* pc); 518 extern int tefmod16_tx_lane_disable (PHYMOD_ST* pc, int tx); 519 extern int tefmod16_init_pcs_ilkn(PHYMOD_ST* pc); 520 521 522 #ifdef CHECKIFNEEDED 523 524 extern int get_mapped_speed(tefmod16_spd_intfc_type spd_intf, int *speed); 525 extern int get_actual_speed(int speed_id, int *speed); 526 527 #endif 528 extern int phymod_debug_check(uint32_t flags, PHYMOD_ST *pc); 529 530 extern int configure_st_entry(int st_entry_num, int st_entry_speed, PHYMOD_ST* pc); 531 532 extern int tefmod16_pmd_osmode_set(PHYMOD_ST* pc, tefmod16_spd_intfc_type_t spd_intf, phymod_ref_clk_t refclk, int os_mode); 533 extern int tefmod16_pmd_x4_reset(PHYMOD_ST* pc); 534 extern int tefmod16_tx_loopback_get(PHYMOD_ST* pc, uint32_t *enable); 535 extern int tefmod16_firmware_set(PHYMOD_ST* pc); 536 extern int tefmod16_tx_lane_disable (PHYMOD_ST* pc, int tx); 537 extern int tefmod16_init_pcs_ilkn(PHYMOD_ST* pc); 538 extern int tefmod16_pcs_ilkn_chk(PHYMOD_ST* pc, int *ilkn_set); 539 extern int tefmod16_pmd_reset_bypass (PHYMOD_ST* pc, int pmd_reset_control); 540 extern int tefmod16_afe_speed_up_dsc_vga(PHYMOD_ST* pc); 541 extern int tefmod16_get_plldiv(PHYMOD_ST* pc, uint32_t *plldiv_r_val); 542 extern int tefmod16_update_port_mode_select(PHYMOD_ST* pc, tefmod16_port_type_t port_type, int master_port, int tsc_clk_freq_pll_by_48, int pll_reset_en); 543 extern int tefmod16_set_port_mode(PHYMOD_ST* pc, int refclk, int plldiv, tefmod16_port_type_t port_type, int master_port, int tsc_clk_freq_pll_by_48, int pll_reset_en); 544 extern int tefmod16_tx_loopback_control(PHYMOD_ST* pc, int pcs_gloop_en, int starting_lane, int num_lanes); 545 extern int tefmod16_tx_pmd_loopback_control(PHYMOD_ST* pc, int pmd_gloop_en); 546 extern int tefmod16_rx_loopback_control(PHYMOD_ST* pc, int pcs_rloop_en); 547 extern int tefmod16_rx_pmd_loopback_control(PHYMOD_ST* pc, int pcs_rloop_en, int pmd_rloop_en, int lane); 548 extern int tefmod16_credit_set(PHYMOD_ST* pc); 549 extern int tefmod16_encode_set(PHYMOD_ST* pc, int per_lane_control, tefmod16_spd_intfc_type_t spd_intf, int tx_am_timer_init_val); 550 extern int tefmod16_lf_rf_control(PHYMOD_ST* pc); 551 extern int tefmod16_decode_set(PHYMOD_ST* pc); 552 extern int tefmod16_trigger_speed_change(PHYMOD_ST* pc); 553 extern int tefmod16_set_override_0(PHYMOD_ST* pc, int per_field_override_en); 554 extern int tefmod16_set_override_1(PHYMOD_ST* pc, int per_lane_control, uint32_t per_field_override_en); 555 extern int tefmod16_credit_control(PHYMOD_ST* pc, int per_lane_control); 556 extern int tefmod16_tx_lane_control_set(PHYMOD_ST* pc, tefmod16_tx_disable_enum_t dis); 557 extern int tefmod16_tx_lane_control_get(PHYMOD_ST* pc, int *reset, int *enable); 558 extern int tefmod16_rx_lane_control(PHYMOD_ST* pc, int accData, int per_lane_control); 559 extern int tefmod16_bypass_sc(PHYMOD_ST* pc); 560 extern int tefmod16_revid_read(PHYMOD_ST* pc, uint32_t *revIdV); 561 extern int tefmod16_clause72_control(PHYMOD_ST* pc, int per_lane_control); 562 extern int tefmod16_prbs_check(PHYMOD_ST* pc, int accData); 563 extern int tefmod16_prbs_mode(PHYMOD_ST* pc, int per_lane_control); 564 extern int tefmod16_prbs_control(PHYMOD_ST* pc, int per_lane_control); 565 extern int tefmod16_cjpat_crpat_control(PHYMOD_ST* pc); 566 extern int tefmod16_cjpat_crpat_check(PHYMOD_ST* pc); 567 extern int tefmod16_tx_bert_control(PHYMOD_ST* pc); 568 extern int tefmod16_FEC_control(PHYMOD_ST* pc, tefmod16_fec_type_t fec_type, int enable, int cl74or91); 569 extern int tefmod16_FEC_get(PHYMOD_ST* pc, tefmod16_fec_type_t fec_type, int *fec_en); 570 extern int tefmod16_power_control(PHYMOD_ST* pc, int tx, int rx); 571 extern int tefmod16_duplex_control(PHYMOD_ST* pc); 572 extern int tefmod16_disable_pcs_falcon(PHYMOD_ST* pc); 573 extern int tefmod16_pmd_addr_lane_swap(PHYMOD_ST *pc, int per_lane_control); 574 extern int tefmod16_pmd_lane_swap_tx(PHYMOD_ST *pc, int per_lane_control); 575 extern int tefmod16_pmd_reset_remove(PHYMOD_ST *pc, int pmd_touched); 576 extern int tefmod16_pcs_lane_swap(PHYMOD_ST *pc, int per_lane_control); 577 extern int tefmod16_init_pcs_falcon(PHYMOD_ST* pc); 578 extern int tefmod16_init_pmd_falcon(PHYMOD_ST* pc); 579 extern int tefmod16_set_sc_speed(PHYMOD_ST* pc); 580 extern int tefmod16_poll_for_sc_done(PHYMOD_ST* pc, int mapped_speed); 581 extern int tefmod16_check_status(PHYMOD_ST* pc); 582 extern int tefmod16_set_port_mode_sel(PHYMOD_ST* pc, int tsc_touched, tefmod16_port_type_t port_type); 583 extern int tefmod16_init_pcs_fs(PHYMOD_ST* pc); 584 extern int tefmod16_init_pcs_an(PHYMOD_ST* pc); 585 extern int tefmod16_set_an_override(PHYMOD_ST* pc); 586 extern int tefmod16_tx_squelch_get(PHYMOD_ST *pc, int *val); 587 extern int tefmod16_refclk_get(PHYMOD_ST* pc, phymod_ref_clk_t* ref_clk); 588 extern int tefmod16_refclk_set(PHYMOD_ST* pc, phymod_ref_clk_t ref_clock); 589 590 extern int tefmod16_get_mapped_speed(tefmod16_spd_intfc_type_t spd_intf, int *speed); 591 extern int tefmod16_toggle_sw_speed_change(PHYMOD_ST* pc); 592 593 extern int tefmod16_autoneg_get(PHYMOD_ST* pc); 594 #ifdef _DV_TB_ 595 extern int tefmod16_autoneg_set(PHYMOD_ST* pc); 596 extern int tefmod16_autoneg_control(PHYMOD_ST* pc); 597 extern int tefmod16_set_spd_intf(PHYMOD_ST* pc); 598 extern int tefmod16_set_an_port_mode(PHYMOD_ST* pc); 599 #endif /* _DV_TB_ */ 600 #ifdef _SDK_TEFMOD16_ 601 int tefmod16_set_an_port_mode(PHYMOD_ST* pc, int num_of_lanes, int starting_lane, int single_port); 602 extern int tefmod16_set_an_single_port_mode(PHYMOD_ST* pc, int an_enable); 603 extern int tefmod16_set_spd_intf(PHYMOD_ST *pc, tefmod16_spd_intfc_type_t spd_intf); 604 extern int tefmod16_autoneg_set_init(PHYMOD_ST* pc, tefmod16_an_init_t *an_init_st); 605 extern int tefmod16_autoneg_timer_init(PHYMOD_ST* pc); 606 extern int tefmod16_autoneg_control(PHYMOD_ST* pc, tefmod16_an_control_t *an_control); 607 extern int tefmod16_autoneg_set(PHYMOD_ST* pc, tefmod16_an_adv_ability_t *an_ability_st); 608 extern int tefmod16_diag(PHYMOD_ST *ws, tefmod16_diag_type_t diag_type); 609 extern int tefmod16_diag_disp(PHYMOD_ST *ws, const char* arg); 610 extern int tefmod16_autoneg_control_get(PHYMOD_ST* pc, tefmod16_an_control_t *an_control, int *an_complete); 611 extern int tefmod16_autoneg_local_ability_get(PHYMOD_ST* pc, tefmod16_an_adv_ability_t *an_ability_st); 612 extern int tefmod16_autoneg_remote_ability_get(PHYMOD_ST* pc, tefmod16_an_adv_ability_t *an_ability_st); 613 extern int tefmod16_st_control_field_set (PHYMOD_ST* pc,uint16_t st_entry_no, override_type_t st_control_field, uint16_t st_field_value); 614 extern int tefmod16_port_enable_set(PHYMOD_ST *pc, int enable); 615 extern int tefmod16_tx_squelch_set(PHYMOD_ST *pc, int enable); 616 extern int tefmod16_rx_squelch_set(PHYMOD_ST *pc, int enable); 617 extern int tefmod16_rx_squelch_get(PHYMOD_ST *pc, int *enable); 618 619 #endif /* _SDK_TEFMOD16_ */ 620 621 extern int tefmod16_port_enable_get(PHYMOD_ST *pc, int *tx_enable, int *rx_enable); 622 extern int tefmod16_pll_lock_get(PHYMOD_ST* pc, int* lockStatus); 623 extern int tefmod16_pmd_lock_get(PHYMOD_ST* pc, uint32_t* lockStatus); 624 extern int tefmod16_set_pll_mode(PHYMOD_ST* pc, int pmd_touched, tefmod16_spd_intfc_type_t spd_intf, int pll_mode); /* SET_PLL_MODE */ 625 extern int tefmod16_speed_id_get(PHYMOD_ST* pc, int *speed_id); 626 extern int tefmod16_pmd_reset_seq(PHYMOD_ST* pc, int pmd_touched); /* PMD_RESET_SEQ */ 627 extern int tefmod16_master_port_num_set( PHYMOD_ST *pc, int port_num); 628 extern int tefmod16_update_port_mode( PHYMOD_ST *pa, int *pll_restart); 629 extern int tefmod16_pll_reset_enable_set (PHYMOD_ST *pa , int enable); 630 extern int tefmod16_get_pcs_link_status(PHYMOD_ST* pc, uint32_t *link); 631 extern int tefmod16_get_pcs_latched_link_status(PHYMOD_ST* pc, uint32_t *link); 632 extern int tefmod16_enable_get(PHYMOD_ST* pc, uint32_t* enable); 633 extern int tefmod16_disable_set(PHYMOD_ST* pc); 634 extern int tefmod16_enable_set(PHYMOD_ST* pc); 635 extern int tefmod16_plldiv_lkup_get(PHYMOD_ST* pc, tefmod16_spd_intfc_type_t spd_intf, phymod_ref_clk_t refclk, uint32_t *plldiv); 636 extern int tefmod16_osmode_lkup_get(PHYMOD_ST* pc, tefmod16_spd_intfc_type_t spd_intf, uint32_t *osmode); 637 extern int tefmod16_pcs_lane_swap_get ( PHYMOD_ST *pc, uint32_t *tx_rx_swap); 638 extern int tefmod16_pmd_lane_swap_tx_get ( PHYMOD_ST *pc, uint32_t *tx_lane_map); 639 extern int tefmod16_rx_lane_control_set(PHYMOD_ST* pc, int enable); /* RX_LANE_CONTROL */ 640 extern int tefmod16_rx_lane_control_get(PHYMOD_ST* pc, int *enable); 641 extern int tefmod16_tx_rx_polarity_get ( PHYMOD_ST *pc, uint32_t* tx_polarity, uint32_t* rx_polarity); 642 extern int tefmod16_tx_rx_polarity_set ( PHYMOD_ST *pc, uint32_t tx_polarity, uint32_t rx_polarity); 643 644 int tefmod16_eee_control_set(PHYMOD_ST* pc, uint32_t enable); 645 int tefmod16_eee_control_get(PHYMOD_ST* pc, uint32_t* enable); 646 int tefmod16_cl74_chng_default (PHYMOD_ST* pc); 647 int tefmod16_cl91_ecc_clear(PHYMOD_ST* pc); 648 649 extern int tefmod16_an_msa_mode_set(PHYMOD_ST* pc, uint32_t val); 650 extern int tefmod16_an_msa_mode_get(PHYMOD_ST* pc, uint32_t* val); 651 extern int tefmod16_an_oui_set(PHYMOD_ST* pc, tefmod16_an_oui_t oui); 652 extern int tefmod16_an_oui_get(PHYMOD_ST* pc, tefmod16_an_oui_t *oui); 653 extern int tefmod16_autoneg_status_get(PHYMOD_ST* pc, int *an_en, int *an_done); 654 extern int tefmod16_autoneg_lp_status_get(PHYMOD_ST* pc, tefmod16_an_adv_ability_t *an_ability_st); 655 extern int tefmod16_hg2_codec_set(PHYMOD_ST* pc, tefmod16_hg2_codec_t hg2_codec); 656 extern int tefmod16_hg2_codec_get(PHYMOD_ST* pc, tefmod16_hg2_codec_t* hg2_codec); 657 extern int tefmod16_pmd_lane_swap(PHYMOD_ST *pc, int tx_lane_swap, int rx_lane_swap); 658 extern int tefmod16_pmd_lane_swap_tx_rx_get ( PHYMOD_ST *pc, uint32_t *tx_lane_map, uint32_t *rx_lane_map); 659 extern int tefmod16_pcs_tx_lane_swap_get ( PHYMOD_ST *pc, uint32_t *tx_swap); 660 extern int tefmod16_pcs_rx_lane_swap_get ( PHYMOD_ST *pc, uint32_t *rx_swap); 661 extern int tefmod16_pmd_lane_swap(PHYMOD_ST *pc, int tx_lane_swap, int rx_lane_swap); 662 extern int tefmod16_pcs_tx_lane_swap(PHYMOD_ST *pc, int tx_lane_swap); 663 extern int tefmod16_pcs_rx_lane_swap(PHYMOD_ST *pc, int rx_lane_swap); 664 extern int tefmod16_pll_vco2_select(PHYMOD_ST* pc, uint32_t vco_rate); 665 extern int tefmod16_default_init(PHYMOD_ST* pc); 666 extern int tefmod16_fec_correctable_counter_get(PHYMOD_ST* pc, uint32_t* count); 667 extern int tefmod16_fec_uncorrectable_counter_get(PHYMOD_ST* pc, uint32_t* count); 668 extern int tefmod16_fec_cl91_correctable_counter_get(PHYMOD_ST* pc, uint32_t* count); 669 extern int tefmod16_fec_cl91_uncorrectable_counter_get(PHYMOD_ST* pc, uint32_t* count); 670 extern int tefmod16_25g_rsfec_am_init(PHYMOD_ST *pc); 671 672 extern int tefmod16_sw_an_control(PHYMOD_ST* pc, int enable); 673 extern int tefmod16_sw_an_ld_page_load(PHYMOD_ST* pc, phymod_an_page_t *pages, int is_base_page); 674 extern int tefmod16_sw_an_lp_page_read(PHYMOD_ST* pc, phymod_an_page_t *pages); 675 extern int tefmod16_sw_an_ctl_sts_get(PHYMOD_ST* pc, phymod_sw_an_ctrl_status_t *an_ctrl_status); 676 extern int tefmod16_sw_an_set_ack(PHYMOD_ST* pc); 677 extern int tefmod16_set_speed_id(PHYMOD_ST *pc, int speed_id); 678 extern int tefmod16_setup_for_sw_an(PHYMOD_ST* pc, int num_lanes); 679 extern int tefmod16_pxgng_status_an_ack_complete_get(PHYMOD_ST *pc, int *ack_complte); 680 extern int tefmod16_pxgng_status_an_good_chk_get(PHYMOD_ST *pc, uint8_t *an_good_chk); 681 extern int tefmod16_sw_an_control(PHYMOD_ST *pc, int enable); 682 extern int tefmod16_sw_an_advert_set(PHYMOD_ST* pc, tefmod16_an_adv_ability_t *cl73_adv, phymod_sw_an_ctxt_t *an_ctxt); 683 extern int tefmod16_sw_an_fec_override(PHYMOD_ST *pc, tefmod16_fec_type_t fec_type, int enable); 684 extern int tefmod16_fec_bypass_indication_set(PHYMOD_ST *pc, uint32_t enable); 685 extern int tefmod16_fec_bypass_indication_get(PHYMOD_ST *pc, uint32_t* enable); 686 extern int tefmod16_override_10g_x1_spd_intf(PHYMOD_ST *pc, int override); 687 extern int tefmod16_override_10g_kr1_spd_intf(PHYMOD_ST *pc, int override); 688 extern int tefmod16_10g_clock_enable(PHYMOD_ST *pc, int enable); 689 extern int tefmod16_synce_stg0_mode_set(PHYMOD_ST *pc, int mode); 690 extern int tefmod16_synce_stg0_mode_get(PHYMOD_ST *pc, int *mode); 691 extern int tefmod16_synce_stg1_mode_set(PHYMOD_ST *pc, int mode); 692 extern int tefmod16_synce_stg1_mode_get(PHYMOD_ST *pc, int *mode); 693 extern int tefmod16_synce_clk_ctrl_set(PHYMOD_ST *pc, uint32_t val); 694 extern int tefmod16_synce_clk_ctrl_get(PHYMOD_ST *pc, uint32_t *val); 695 extern int tefmod16_fec_override_set(PHYMOD_ST *pc, uint32_t enable); 696 extern int tefmod16_fec_override_get(PHYMOD_ST *pc, uint32_t *enable); 697 #endif /* _tefmod16_H_ */ 698