tfPCSRegEnums.h (969426B)
1 /*---------------------------------------------------------------------- 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * $Copyright: (c) 2014 Broadcom Corporation All Rights Reserved.$ 8 * Broadcom Corporation 9 * Proprietary and Confidential information 10 * All rights reserved 11 * This source file is the property of Broadcom Corporation, and 12 * may not be copied or distributed in any isomorphic form without the 13 * prior written consent of Broadcom Corporation. 14 *---------------------------------------------------------------------- 15 * Description: define enumerators 16 *----------------------------------------------------------------------*/ 17 /**************************************************************************** 18 * Core Enums. 19 */ 20 /**************************************************************************** 21 * Enums: an_x4_abilities_cl36TxEEEStates_l 22 */ 23 #define an_x4_abilities_cl36TxEEEStates_l_TX_REFRESH 8 24 #define an_x4_abilities_cl36TxEEEStates_l_TX_QUIET 4 25 #define an_x4_abilities_cl36TxEEEStates_l_TX_SLEEP 2 26 #define an_x4_abilities_cl36TxEEEStates_l_TX_ACTIVE 1 27 28 /**************************************************************************** 29 * Enums: an_x4_abilities_cl36TxEEEStates_c 30 */ 31 #define an_x4_abilities_cl36TxEEEStates_c_TX_REFRESH 3 32 #define an_x4_abilities_cl36TxEEEStates_c_TX_QUIET 2 33 #define an_x4_abilities_cl36TxEEEStates_c_TX_SLEEP 1 34 #define an_x4_abilities_cl36TxEEEStates_c_TX_ACTIVE 0 35 36 /**************************************************************************** 37 * Enums: an_x4_abilities_cl49TxEEEStates_l 38 */ 39 #define an_x4_abilities_cl49TxEEEStates_l_SCR_RESET_2 64 40 #define an_x4_abilities_cl49TxEEEStates_l_SCR_RESET_1 32 41 #define an_x4_abilities_cl49TxEEEStates_l_TX_WAKE 16 42 #define an_x4_abilities_cl49TxEEEStates_l_TX_REFRESH 8 43 #define an_x4_abilities_cl49TxEEEStates_l_TX_QUIET 4 44 #define an_x4_abilities_cl49TxEEEStates_l_TX_SLEEP 2 45 #define an_x4_abilities_cl49TxEEEStates_l_TX_ACTIVE 1 46 47 /**************************************************************************** 48 * Enums: an_x4_abilities_fec_req_enum 49 */ 50 #define an_x4_abilities_fec_req_enum_FEC_not_supported 0 51 #define an_x4_abilities_fec_req_enum_FEC_supported_but_not_requested 1 52 #define an_x4_abilities_fec_req_enum_invalid_setting 2 53 #define an_x4_abilities_fec_req_enum_FEC_supported_and_requested 3 54 55 /**************************************************************************** 56 * Enums: an_x4_abilities_cl73_pause_enum 57 */ 58 #define an_x4_abilities_cl73_pause_enum_No_PAUSE_ability 0 59 #define an_x4_abilities_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 60 #define an_x4_abilities_cl73_pause_enum_Symmetric_PAUSE_ability 1 61 #define an_x4_abilities_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 62 63 /**************************************************************************** 64 * Enums: an_x4_abilities_cl49TxEEEStates_c 65 */ 66 #define an_x4_abilities_cl49TxEEEStates_c_SCR_RESET_2 6 67 #define an_x4_abilities_cl49TxEEEStates_c_SCR_RESET_1 5 68 #define an_x4_abilities_cl49TxEEEStates_c_TX_WAKE 4 69 #define an_x4_abilities_cl49TxEEEStates_c_TX_REFRESH 3 70 #define an_x4_abilities_cl49TxEEEStates_c_TX_QUIET 2 71 #define an_x4_abilities_cl49TxEEEStates_c_TX_SLEEP 1 72 #define an_x4_abilities_cl49TxEEEStates_c_TX_ACTIVE 0 73 74 /**************************************************************************** 75 * Enums: an_x4_abilities_cl36RxEEEStates_l 76 */ 77 #define an_x4_abilities_cl36RxEEEStates_l_RX_LINK_FAIL 32 78 #define an_x4_abilities_cl36RxEEEStates_l_RX_WTF 16 79 #define an_x4_abilities_cl36RxEEEStates_l_RX_WAKE 8 80 #define an_x4_abilities_cl36RxEEEStates_l_RX_QUIET 4 81 #define an_x4_abilities_cl36RxEEEStates_l_RX_SLEEP 2 82 #define an_x4_abilities_cl36RxEEEStates_l_RX_ACTIVE 1 83 84 /**************************************************************************** 85 * Enums: an_x4_abilities_cl36RxEEEStates_c 86 */ 87 #define an_x4_abilities_cl36RxEEEStates_c_RX_LINK_FAIL 5 88 #define an_x4_abilities_cl36RxEEEStates_c_RX_WTF 4 89 #define an_x4_abilities_cl36RxEEEStates_c_RX_WAKE 3 90 #define an_x4_abilities_cl36RxEEEStates_c_RX_QUIET 2 91 #define an_x4_abilities_cl36RxEEEStates_c_RX_SLEEP 1 92 #define an_x4_abilities_cl36RxEEEStates_c_RX_ACTIVE 0 93 94 /**************************************************************************** 95 * Enums: an_x4_abilities_cl49RxEEEStates_l 96 */ 97 #define an_x4_abilities_cl49RxEEEStates_l_RX_LINK_FAIL 32 98 #define an_x4_abilities_cl49RxEEEStates_l_RX_WTF 16 99 #define an_x4_abilities_cl49RxEEEStates_l_RX_WAKE 8 100 #define an_x4_abilities_cl49RxEEEStates_l_RX_QUIET 4 101 #define an_x4_abilities_cl49RxEEEStates_l_RX_SLEEP 2 102 #define an_x4_abilities_cl49RxEEEStates_l_RX_ACTIVE 1 103 104 /**************************************************************************** 105 * Enums: an_x4_abilities_cl49RxEEEStates_c 106 */ 107 #define an_x4_abilities_cl49RxEEEStates_c_RX_LINK_FAIL 5 108 #define an_x4_abilities_cl49RxEEEStates_c_RX_WTF 4 109 #define an_x4_abilities_cl49RxEEEStates_c_RX_WAKE 3 110 #define an_x4_abilities_cl49RxEEEStates_c_RX_QUIET 2 111 #define an_x4_abilities_cl49RxEEEStates_c_RX_SLEEP 1 112 #define an_x4_abilities_cl49RxEEEStates_c_RX_ACTIVE 0 113 114 /**************************************************************************** 115 * Enums: an_x4_abilities_cl48TxEEEStates_l 116 */ 117 #define an_x4_abilities_cl48TxEEEStates_l_TX_REFRESH 8 118 #define an_x4_abilities_cl48TxEEEStates_l_TX_QUIET 4 119 #define an_x4_abilities_cl48TxEEEStates_l_TX_SLEEP 2 120 #define an_x4_abilities_cl48TxEEEStates_l_TX_ACTIVE 1 121 122 /**************************************************************************** 123 * Enums: an_x4_abilities_cl48TxEEEStates_c 124 */ 125 #define an_x4_abilities_cl48TxEEEStates_c_TX_REFRESH 3 126 #define an_x4_abilities_cl48TxEEEStates_c_TX_QUIET 2 127 #define an_x4_abilities_cl48TxEEEStates_c_TX_SLEEP 1 128 #define an_x4_abilities_cl48TxEEEStates_c_TX_ACTIVE 0 129 130 /**************************************************************************** 131 * Enums: an_x4_abilities_cl48RxEEEStates_l 132 */ 133 #define an_x4_abilities_cl48RxEEEStates_l_RX_LINK_FAIL 32 134 #define an_x4_abilities_cl48RxEEEStates_l_RX_WAKE 16 135 #define an_x4_abilities_cl48RxEEEStates_l_RX_QUIET 8 136 #define an_x4_abilities_cl48RxEEEStates_l_RX_DEACT 4 137 #define an_x4_abilities_cl48RxEEEStates_l_RX_SLEEP 2 138 #define an_x4_abilities_cl48RxEEEStates_l_RX_ACTIVE 1 139 140 /**************************************************************************** 141 * Enums: an_x4_abilities_cl48RxEEEStates_c 142 */ 143 #define an_x4_abilities_cl48RxEEEStates_c_RX_LINK_FAIL 5 144 #define an_x4_abilities_cl48RxEEEStates_c_RX_WAKE 4 145 #define an_x4_abilities_cl48RxEEEStates_c_RX_QUIET 3 146 #define an_x4_abilities_cl48RxEEEStates_c_RX_DEACT 2 147 #define an_x4_abilities_cl48RxEEEStates_c_RX_SLEEP 1 148 #define an_x4_abilities_cl48RxEEEStates_c_RX_ACTIVE 0 149 150 /**************************************************************************** 151 * Enums: an_x4_abilities_IQP_Options 152 */ 153 #define an_x4_abilities_IQP_Options_i50uA 0 154 #define an_x4_abilities_IQP_Options_i100uA 1 155 #define an_x4_abilities_IQP_Options_i150uA 2 156 #define an_x4_abilities_IQP_Options_i200uA 3 157 #define an_x4_abilities_IQP_Options_i250uA 4 158 #define an_x4_abilities_IQP_Options_i300uA 5 159 #define an_x4_abilities_IQP_Options_i350uA 6 160 #define an_x4_abilities_IQP_Options_i400uA 7 161 #define an_x4_abilities_IQP_Options_i450uA 8 162 #define an_x4_abilities_IQP_Options_i500uA 9 163 #define an_x4_abilities_IQP_Options_i550uA 10 164 #define an_x4_abilities_IQP_Options_i600uA 11 165 #define an_x4_abilities_IQP_Options_i650uA 12 166 #define an_x4_abilities_IQP_Options_i700uA 13 167 #define an_x4_abilities_IQP_Options_i750uA 14 168 #define an_x4_abilities_IQP_Options_i800uA 15 169 170 /**************************************************************************** 171 * Enums: an_x4_abilities_IDriver_Options 172 */ 173 #define an_x4_abilities_IDriver_Options_v680mV 0 174 #define an_x4_abilities_IDriver_Options_v730mV 1 175 #define an_x4_abilities_IDriver_Options_v780mV 2 176 #define an_x4_abilities_IDriver_Options_v830mV 3 177 #define an_x4_abilities_IDriver_Options_v880mV 4 178 #define an_x4_abilities_IDriver_Options_v930mV 5 179 #define an_x4_abilities_IDriver_Options_v980mV 6 180 #define an_x4_abilities_IDriver_Options_v1010mV 7 181 #define an_x4_abilities_IDriver_Options_v1040mV 8 182 #define an_x4_abilities_IDriver_Options_v1060mV 9 183 #define an_x4_abilities_IDriver_Options_v1070mV 10 184 #define an_x4_abilities_IDriver_Options_v1080mV 11 185 #define an_x4_abilities_IDriver_Options_v1085mV 12 186 #define an_x4_abilities_IDriver_Options_v1090mV 13 187 #define an_x4_abilities_IDriver_Options_v1095mV 14 188 #define an_x4_abilities_IDriver_Options_v1100mV 15 189 190 /**************************************************************************** 191 * Enums: an_x4_abilities_operationModes 192 */ 193 #define an_x4_abilities_operationModes_XGXS 0 194 #define an_x4_abilities_operationModes_XGXG_nCC 1 195 #define an_x4_abilities_operationModes_Indlane_OS8 4 196 #define an_x4_abilities_operationModes_IndLane_OS5 5 197 #define an_x4_abilities_operationModes_PCI 7 198 #define an_x4_abilities_operationModes_XGXS_nLQ 8 199 #define an_x4_abilities_operationModes_XGXS_nLQnCC 9 200 #define an_x4_abilities_operationModes_PBypass 10 201 #define an_x4_abilities_operationModes_PBypass_nDSK 11 202 #define an_x4_abilities_operationModes_ComboCoreMode 12 203 #define an_x4_abilities_operationModes_Clocks_off 15 204 205 /**************************************************************************** 206 * Enums: an_x4_abilities_actualSpeeds 207 */ 208 #define an_x4_abilities_actualSpeeds_dr_10M 0 209 #define an_x4_abilities_actualSpeeds_dr_100M 1 210 #define an_x4_abilities_actualSpeeds_dr_1G 2 211 #define an_x4_abilities_actualSpeeds_dr_2p5G 3 212 #define an_x4_abilities_actualSpeeds_dr_5G_X4 4 213 #define an_x4_abilities_actualSpeeds_dr_6G_X4 5 214 #define an_x4_abilities_actualSpeeds_dr_10G_HiG 6 215 #define an_x4_abilities_actualSpeeds_dr_10G_CX4 7 216 #define an_x4_abilities_actualSpeeds_dr_12G_HiG 8 217 #define an_x4_abilities_actualSpeeds_dr_12p5G_X4 9 218 #define an_x4_abilities_actualSpeeds_dr_13G_X4 10 219 #define an_x4_abilities_actualSpeeds_dr_15G_X4 11 220 #define an_x4_abilities_actualSpeeds_dr_16G_X4 12 221 #define an_x4_abilities_actualSpeeds_dr_1G_KX 13 222 #define an_x4_abilities_actualSpeeds_dr_10G_KX4 14 223 #define an_x4_abilities_actualSpeeds_dr_10G_KR 15 224 #define an_x4_abilities_actualSpeeds_dr_5G 16 225 #define an_x4_abilities_actualSpeeds_dr_6p4G 17 226 #define an_x4_abilities_actualSpeeds_dr_20G_X4 18 227 #define an_x4_abilities_actualSpeeds_dr_21G_X4 19 228 #define an_x4_abilities_actualSpeeds_dr_25G_X4 20 229 #define an_x4_abilities_actualSpeeds_dr_10G_HiG_DXGXS 21 230 #define an_x4_abilities_actualSpeeds_dr_10G_DXGXS 22 231 #define an_x4_abilities_actualSpeeds_dr_10p5G_HiG_DXGXS 23 232 #define an_x4_abilities_actualSpeeds_dr_10p5G_DXGXS 24 233 #define an_x4_abilities_actualSpeeds_dr_12p773G_HiG_DXGXS 25 234 #define an_x4_abilities_actualSpeeds_dr_12p773G_DXGXS 26 235 #define an_x4_abilities_actualSpeeds_dr_10G_XFI 27 236 #define an_x4_abilities_actualSpeeds_dr_40G 28 237 #define an_x4_abilities_actualSpeeds_dr_20G_HiG_DXGXS 29 238 #define an_x4_abilities_actualSpeeds_dr_20G_DXGXS 30 239 #define an_x4_abilities_actualSpeeds_dr_10G_SFI 31 240 #define an_x4_abilities_actualSpeeds_dr_31p5G 32 241 #define an_x4_abilities_actualSpeeds_dr_32p7G 33 242 #define an_x4_abilities_actualSpeeds_dr_20G_SCR 34 243 #define an_x4_abilities_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 244 #define an_x4_abilities_actualSpeeds_dr_10G_DXGXS_SCR 36 245 #define an_x4_abilities_actualSpeeds_dr_12G_R2 37 246 #define an_x4_abilities_actualSpeeds_dr_10G_X2 38 247 #define an_x4_abilities_actualSpeeds_dr_40G_KR4 39 248 #define an_x4_abilities_actualSpeeds_dr_40G_CR4 40 249 #define an_x4_abilities_actualSpeeds_dr_100G_CR10 41 250 #define an_x4_abilities_actualSpeeds_dr_15p75G_DXGXS 44 251 #define an_x4_abilities_actualSpeeds_dr_20G_KR2 57 252 #define an_x4_abilities_actualSpeeds_dr_20G_CR2 58 253 254 /**************************************************************************** 255 * Enums: an_x4_abilities_actualSpeedsMisc1 256 */ 257 #define an_x4_abilities_actualSpeedsMisc1_dr_2500BRCM_X1 16 258 #define an_x4_abilities_actualSpeedsMisc1_dr_5000BRCM_X4 17 259 #define an_x4_abilities_actualSpeedsMisc1_dr_6000BRCM_X4 18 260 #define an_x4_abilities_actualSpeedsMisc1_dr_10GHiGig_X4 19 261 #define an_x4_abilities_actualSpeedsMisc1_dr_10GBASE_CX4 20 262 #define an_x4_abilities_actualSpeedsMisc1_dr_12GHiGig_X4 21 263 #define an_x4_abilities_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 264 #define an_x4_abilities_actualSpeedsMisc1_dr_13GHiGig_X4 23 265 #define an_x4_abilities_actualSpeedsMisc1_dr_15GHiGig_X4 24 266 #define an_x4_abilities_actualSpeedsMisc1_dr_16GHiGig_X4 25 267 #define an_x4_abilities_actualSpeedsMisc1_dr_5000BRCM_X1 26 268 #define an_x4_abilities_actualSpeedsMisc1_dr_6363BRCM_X1 27 269 #define an_x4_abilities_actualSpeedsMisc1_dr_20GHiGig_X4 28 270 #define an_x4_abilities_actualSpeedsMisc1_dr_21GHiGig_X4 29 271 #define an_x4_abilities_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 272 #define an_x4_abilities_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 273 274 /**************************************************************************** 275 * Enums: an_x4_abilities_IndLaneModes 276 */ 277 #define an_x4_abilities_IndLaneModes_SWSDR_div2 0 278 #define an_x4_abilities_IndLaneModes_SWSDR_div1 1 279 #define an_x4_abilities_IndLaneModes_DWSDR_div2 2 280 #define an_x4_abilities_IndLaneModes_DWSDR_div1 3 281 282 /**************************************************************************** 283 * Enums: an_x4_abilities_prbsSelect 284 */ 285 #define an_x4_abilities_prbsSelect_prbs7 0 286 #define an_x4_abilities_prbsSelect_prbs15 1 287 #define an_x4_abilities_prbsSelect_prbs23 2 288 #define an_x4_abilities_prbsSelect_prbs31 3 289 290 /**************************************************************************** 291 * Enums: an_x4_abilities_vcoDivider 292 */ 293 #define an_x4_abilities_vcoDivider_div32 0 294 #define an_x4_abilities_vcoDivider_div36 1 295 #define an_x4_abilities_vcoDivider_div40 2 296 #define an_x4_abilities_vcoDivider_div42 3 297 #define an_x4_abilities_vcoDivider_div48 4 298 #define an_x4_abilities_vcoDivider_div50 5 299 #define an_x4_abilities_vcoDivider_div52 6 300 #define an_x4_abilities_vcoDivider_div54 7 301 #define an_x4_abilities_vcoDivider_div60 8 302 #define an_x4_abilities_vcoDivider_div64 9 303 #define an_x4_abilities_vcoDivider_div66 10 304 #define an_x4_abilities_vcoDivider_div68 11 305 #define an_x4_abilities_vcoDivider_div70 12 306 #define an_x4_abilities_vcoDivider_div80 13 307 #define an_x4_abilities_vcoDivider_div92 14 308 #define an_x4_abilities_vcoDivider_div100 15 309 310 /**************************************************************************** 311 * Enums: an_x4_abilities_refClkSelect 312 */ 313 #define an_x4_abilities_refClkSelect_clk_25MHz 0 314 #define an_x4_abilities_refClkSelect_clk_100MHz 1 315 #define an_x4_abilities_refClkSelect_clk_125MHz 2 316 #define an_x4_abilities_refClkSelect_clk_156p25MHz 3 317 #define an_x4_abilities_refClkSelect_clk_187p5MHz 4 318 #define an_x4_abilities_refClkSelect_clk_161p25Mhz 5 319 #define an_x4_abilities_refClkSelect_clk_50Mhz 6 320 #define an_x4_abilities_refClkSelect_clk_106p25Mhz 7 321 322 /**************************************************************************** 323 * Enums: an_x4_abilities_aerMMDdevTypeSelect 324 */ 325 #define an_x4_abilities_aerMMDdevTypeSelect_combo_core 0 326 #define an_x4_abilities_aerMMDdevTypeSelect_PMA_PMD 1 327 #define an_x4_abilities_aerMMDdevTypeSelect_PCS 3 328 #define an_x4_abilities_aerMMDdevTypeSelect_PHY 4 329 #define an_x4_abilities_aerMMDdevTypeSelect_DTE 5 330 #define an_x4_abilities_aerMMDdevTypeSelect_CL73_AN 7 331 332 /**************************************************************************** 333 * Enums: an_x4_abilities_aerMMDportSelect 334 */ 335 #define an_x4_abilities_aerMMDportSelect_ln0 0 336 #define an_x4_abilities_aerMMDportSelect_ln1 1 337 #define an_x4_abilities_aerMMDportSelect_ln2 2 338 #define an_x4_abilities_aerMMDportSelect_ln3 3 339 #define an_x4_abilities_aerMMDportSelect_BCST_ln0_1_2_3 511 340 #define an_x4_abilities_aerMMDportSelect_BCST_ln0_1 512 341 #define an_x4_abilities_aerMMDportSelect_BCST_ln2_3 513 342 343 /**************************************************************************** 344 * Enums: an_x4_abilities_firmwareModeSelect 345 */ 346 #define an_x4_abilities_firmwareModeSelect_DEFAULT 0 347 #define an_x4_abilities_firmwareModeSelect_SFP_OPT_LR 1 348 #define an_x4_abilities_firmwareModeSelect_SFP_DAC 2 349 #define an_x4_abilities_firmwareModeSelect_XLAUI 3 350 #define an_x4_abilities_firmwareModeSelect_LONG_CH_6G 4 351 352 /**************************************************************************** 353 * Enums: an_x4_abilities_tempIdxSelect 354 */ 355 #define an_x4_abilities_tempIdxSelect_LTE__22p9C 15 356 #define an_x4_abilities_tempIdxSelect_LTE__12p6C 14 357 #define an_x4_abilities_tempIdxSelect_LTE__3p0C 13 358 #define an_x4_abilities_tempIdxSelect_LTE_6p7C 12 359 #define an_x4_abilities_tempIdxSelect_LTE_16p4C 11 360 #define an_x4_abilities_tempIdxSelect_LTE_26p6C 10 361 #define an_x4_abilities_tempIdxSelect_LTE_36p3C 9 362 #define an_x4_abilities_tempIdxSelect_LTE_46p0C 8 363 #define an_x4_abilities_tempIdxSelect_LTE_56p2C 7 364 #define an_x4_abilities_tempIdxSelect_LTE_65p9C 6 365 #define an_x4_abilities_tempIdxSelect_LTE_75p6C 5 366 #define an_x4_abilities_tempIdxSelect_LTE_85p3C 4 367 #define an_x4_abilities_tempIdxSelect_LTE_95p5C 3 368 #define an_x4_abilities_tempIdxSelect_LTE_105p2C 2 369 #define an_x4_abilities_tempIdxSelect_LTE_114p9C 1 370 #define an_x4_abilities_tempIdxSelect_LTE_125p1C 0 371 372 /**************************************************************************** 373 * Enums: an_x4_abilities_port_mode 374 */ 375 #define an_x4_abilities_port_mode_QUAD_PORT 0 376 #define an_x4_abilities_port_mode_TRI_1_PORT 1 377 #define an_x4_abilities_port_mode_TRI_2_PORT 2 378 #define an_x4_abilities_port_mode_DUAL_PORT 3 379 #define an_x4_abilities_port_mode_SINGLE_PORT 4 380 381 /**************************************************************************** 382 * Enums: an_x4_abilities_rev_letter_enum 383 */ 384 #define an_x4_abilities_rev_letter_enum_REV_A 0 385 #define an_x4_abilities_rev_letter_enum_REV_B 1 386 #define an_x4_abilities_rev_letter_enum_REV_C 2 387 #define an_x4_abilities_rev_letter_enum_REV_D 3 388 389 /**************************************************************************** 390 * Enums: an_x4_abilities_rev_number_enum 391 */ 392 #define an_x4_abilities_rev_number_enum_REV_0 0 393 #define an_x4_abilities_rev_number_enum_REV_1 1 394 #define an_x4_abilities_rev_number_enum_REV_2 2 395 #define an_x4_abilities_rev_number_enum_REV_3 3 396 #define an_x4_abilities_rev_number_enum_REV_4 4 397 #define an_x4_abilities_rev_number_enum_REV_5 5 398 #define an_x4_abilities_rev_number_enum_REV_6 6 399 #define an_x4_abilities_rev_number_enum_REV_7 7 400 401 /**************************************************************************** 402 * Enums: an_x4_abilities_bonding_enum 403 */ 404 #define an_x4_abilities_bonding_enum_WIRE_BOND 0 405 #define an_x4_abilities_bonding_enum_FLIP_CHIP 1 406 407 /**************************************************************************** 408 * Enums: an_x4_abilities_tech_process 409 */ 410 #define an_x4_abilities_tech_process_PROCESS_90NM 0 411 #define an_x4_abilities_tech_process_PROCESS_65NM 1 412 #define an_x4_abilities_tech_process_PROCESS_40NM 2 413 #define an_x4_abilities_tech_process_PROCESS_28NM 3 414 415 /**************************************************************************** 416 * Enums: an_x4_abilities_model_num 417 */ 418 #define an_x4_abilities_model_num_SERDES_CL73 0 419 #define an_x4_abilities_model_num_XGXS_16G 1 420 #define an_x4_abilities_model_num_HYPERCORE 2 421 #define an_x4_abilities_model_num_HYPERLITE 3 422 #define an_x4_abilities_model_num_PCIE_G2_PIPE 4 423 #define an_x4_abilities_model_num_SERDES_1p25GBd 5 424 #define an_x4_abilities_model_num_SATA2 6 425 #define an_x4_abilities_model_num_QSGMII 7 426 #define an_x4_abilities_model_num_XGXS10G 8 427 #define an_x4_abilities_model_num_WARPCORE 9 428 #define an_x4_abilities_model_num_XFICORE 10 429 #define an_x4_abilities_model_num_RXFI 11 430 #define an_x4_abilities_model_num_WARPLITE 12 431 #define an_x4_abilities_model_num_PENTACORE 13 432 #define an_x4_abilities_model_num_ESM 14 433 #define an_x4_abilities_model_num_QUAD_SGMII 15 434 #define an_x4_abilities_model_num_WARPCORE_3 16 435 #define an_x4_abilities_model_num_TSC 17 436 #define an_x4_abilities_model_num_TSC4E 18 437 #define an_x4_abilities_model_num_TSC12E 19 438 #define an_x4_abilities_model_num_TSC4F 20 439 #define an_x4_abilities_model_num_XGXS_CL73_90NM 29 440 #define an_x4_abilities_model_num_SERDES_CL73_90NM 30 441 #define an_x4_abilities_model_num_WARPCORE3 32 442 #define an_x4_abilities_model_num_WARPCORE4_TSC 33 443 #define an_x4_abilities_model_num_RXAUI 34 444 445 /**************************************************************************** 446 * Enums: an_x4_abilities_payload 447 */ 448 #define an_x4_abilities_payload_REPEAT_2_BYTES 0 449 #define an_x4_abilities_payload_RAMPING 1 450 #define an_x4_abilities_payload_CL48_CRPAT 2 451 #define an_x4_abilities_payload_CL48_CJPAT 3 452 #define an_x4_abilities_payload_CL36_LONG_CRPAT 4 453 #define an_x4_abilities_payload_CL36_SHORT_CRPAT 5 454 455 /**************************************************************************** 456 * Enums: an_x4_abilities_sc 457 */ 458 #define an_x4_abilities_sc_S_10G_CR1 0 459 #define an_x4_abilities_sc_S_10G_KR1 1 460 #define an_x4_abilities_sc_S_10G_X1 2 461 #define an_x4_abilities_sc_S_10G_HG2_CR1 4 462 #define an_x4_abilities_sc_S_10G_HG2_KR1 5 463 #define an_x4_abilities_sc_S_10G_HG2_X1 6 464 #define an_x4_abilities_sc_S_20G_CR1 8 465 #define an_x4_abilities_sc_S_20G_KR1 9 466 #define an_x4_abilities_sc_S_20G_X1 10 467 #define an_x4_abilities_sc_S_20G_HG2_CR1 12 468 #define an_x4_abilities_sc_S_20G_HG2_KR1 13 469 #define an_x4_abilities_sc_S_20G_HG2_X1 14 470 #define an_x4_abilities_sc_S_25G_CR1 16 471 #define an_x4_abilities_sc_S_25G_KR1 17 472 #define an_x4_abilities_sc_S_25G_X1 18 473 #define an_x4_abilities_sc_S_25G_HG2_CR1 20 474 #define an_x4_abilities_sc_S_25G_HG2_KR1 21 475 #define an_x4_abilities_sc_S_25G_HG2_X1 22 476 #define an_x4_abilities_sc_S_20G_CR2 24 477 #define an_x4_abilities_sc_S_20G_KR2 25 478 #define an_x4_abilities_sc_S_20G_X2 26 479 #define an_x4_abilities_sc_S_20G_HG2_CR2 28 480 #define an_x4_abilities_sc_S_20G_HG2_KR2 29 481 #define an_x4_abilities_sc_S_20G_HG2_X2 30 482 #define an_x4_abilities_sc_S_40G_CR2 32 483 #define an_x4_abilities_sc_S_40G_KR2 33 484 #define an_x4_abilities_sc_S_40G_X2 34 485 #define an_x4_abilities_sc_S_40G_HG2_CR2 36 486 #define an_x4_abilities_sc_S_40G_HG2_KR2 37 487 #define an_x4_abilities_sc_S_40G_HG2_X2 38 488 #define an_x4_abilities_sc_S_40G_CR4 40 489 #define an_x4_abilities_sc_S_40G_KR4 41 490 #define an_x4_abilities_sc_S_40G_X4 42 491 #define an_x4_abilities_sc_S_40G_HG2_CR4 44 492 #define an_x4_abilities_sc_S_40G_HG2_KR4 45 493 #define an_x4_abilities_sc_S_40G_HG2_X4 46 494 #define an_x4_abilities_sc_S_50G_CR2 48 495 #define an_x4_abilities_sc_S_50G_KR2 49 496 #define an_x4_abilities_sc_S_50G_X2 50 497 #define an_x4_abilities_sc_S_50G_HG2_CR2 52 498 #define an_x4_abilities_sc_S_50G_HG2_KR2 53 499 #define an_x4_abilities_sc_S_50G_HG2_X2 54 500 #define an_x4_abilities_sc_S_50G_CR4 56 501 #define an_x4_abilities_sc_S_50G_KR4 57 502 #define an_x4_abilities_sc_S_50G_X4 58 503 #define an_x4_abilities_sc_S_50G_HG2_CR4 60 504 #define an_x4_abilities_sc_S_50G_HG2_KR4 61 505 #define an_x4_abilities_sc_S_50G_HG2_X4 62 506 #define an_x4_abilities_sc_S_100G_CR4 64 507 #define an_x4_abilities_sc_S_100G_KR4 65 508 #define an_x4_abilities_sc_S_100G_X4 66 509 #define an_x4_abilities_sc_S_100G_HG2_CR4 68 510 #define an_x4_abilities_sc_S_100G_HG2_KR4 69 511 #define an_x4_abilities_sc_S_100G_HG2_X4 70 512 #define an_x4_abilities_sc_S_CL73_20GVCO 72 513 #define an_x4_abilities_sc_S_CL73_25GVCO 80 514 #define an_x4_abilities_sc_S_CL36_20GVCO 88 515 #define an_x4_abilities_sc_S_CL36_25GVCO 96 516 517 /**************************************************************************** 518 * Enums: an_x4_abilities_t_fifo_modes 519 */ 520 #define an_x4_abilities_t_fifo_modes_T_FIFO_MODE_BYPASS 0 521 #define an_x4_abilities_t_fifo_modes_T_FIFO_MODE_40G 1 522 #define an_x4_abilities_t_fifo_modes_T_FIFO_MODE_100G 2 523 #define an_x4_abilities_t_fifo_modes_T_FIFO_MODE_20G 3 524 525 /**************************************************************************** 526 * Enums: an_x4_abilities_t_enc_modes 527 */ 528 #define an_x4_abilities_t_enc_modes_T_ENC_MODE_BYPASS 0 529 #define an_x4_abilities_t_enc_modes_T_ENC_MODE_CL49 1 530 #define an_x4_abilities_t_enc_modes_T_ENC_MODE_CL82 2 531 532 /**************************************************************************** 533 * Enums: an_x4_abilities_btmx_mode 534 */ 535 #define an_x4_abilities_btmx_mode_BS_BTMX_MODE_1to1 0 536 #define an_x4_abilities_btmx_mode_BS_BTMX_MODE_2to1 1 537 #define an_x4_abilities_btmx_mode_BS_BTMX_MODE_5to1 2 538 539 /**************************************************************************** 540 * Enums: an_x4_abilities_t_type_cl82 541 */ 542 #define an_x4_abilities_t_type_cl82_T_TYPE_B1 5 543 #define an_x4_abilities_t_type_cl82_T_TYPE_C 4 544 #define an_x4_abilities_t_type_cl82_T_TYPE_S 3 545 #define an_x4_abilities_t_type_cl82_T_TYPE_T 2 546 #define an_x4_abilities_t_type_cl82_T_TYPE_D 1 547 #define an_x4_abilities_t_type_cl82_T_TYPE_E 0 548 549 /**************************************************************************** 550 * Enums: an_x4_abilities_txsm_state_cl82 551 */ 552 #define an_x4_abilities_txsm_state_cl82_TX_HIG_END 6 553 #define an_x4_abilities_txsm_state_cl82_TX_HIG_START 5 554 #define an_x4_abilities_txsm_state_cl82_TX_E 4 555 #define an_x4_abilities_txsm_state_cl82_TX_T 3 556 #define an_x4_abilities_txsm_state_cl82_TX_D 2 557 #define an_x4_abilities_txsm_state_cl82_TX_C 1 558 #define an_x4_abilities_txsm_state_cl82_TX_INIT 0 559 560 /**************************************************************************** 561 * Enums: an_x4_abilities_ltxsm_state_cl82 562 */ 563 #define an_x4_abilities_ltxsm_state_cl82_TX_HIG_END 64 564 #define an_x4_abilities_ltxsm_state_cl82_TX_HIG_START 32 565 #define an_x4_abilities_ltxsm_state_cl82_TX_E 16 566 #define an_x4_abilities_ltxsm_state_cl82_TX_T 8 567 #define an_x4_abilities_ltxsm_state_cl82_TX_D 4 568 #define an_x4_abilities_ltxsm_state_cl82_TX_C 2 569 #define an_x4_abilities_ltxsm_state_cl82_TX_INIT 1 570 571 /**************************************************************************** 572 * Enums: an_x4_abilities_r_type_coded_cl82 573 */ 574 #define an_x4_abilities_r_type_coded_cl82_R_TYPE_B1 32 575 #define an_x4_abilities_r_type_coded_cl82_R_TYPE_C 16 576 #define an_x4_abilities_r_type_coded_cl82_R_TYPE_S 8 577 #define an_x4_abilities_r_type_coded_cl82_R_TYPE_T 4 578 #define an_x4_abilities_r_type_coded_cl82_R_TYPE_D 2 579 #define an_x4_abilities_r_type_coded_cl82_R_TYPE_E 1 580 581 /**************************************************************************** 582 * Enums: an_x4_abilities_rxsm_state_cl82 583 */ 584 #define an_x4_abilities_rxsm_state_cl82_RX_HIG_END 64 585 #define an_x4_abilities_rxsm_state_cl82_RX_HIG_START 32 586 #define an_x4_abilities_rxsm_state_cl82_RX_E 16 587 #define an_x4_abilities_rxsm_state_cl82_RX_T 8 588 #define an_x4_abilities_rxsm_state_cl82_RX_D 4 589 #define an_x4_abilities_rxsm_state_cl82_RX_C 2 590 #define an_x4_abilities_rxsm_state_cl82_RX_INIT 1 591 592 /**************************************************************************** 593 * Enums: an_x4_abilities_deskew_state 594 */ 595 #define an_x4_abilities_deskew_state_ALIGN_ACQUIRED 2 596 #define an_x4_abilities_deskew_state_LOSS_OF_ALIGNMENT 1 597 598 /**************************************************************************** 599 * Enums: an_x4_abilities_os_mode_enum 600 */ 601 #define an_x4_abilities_os_mode_enum_OS_MODE_1 0 602 #define an_x4_abilities_os_mode_enum_OS_MODE_2 1 603 #define an_x4_abilities_os_mode_enum_OS_MODE_4 2 604 #define an_x4_abilities_os_mode_enum_OS_MODE_16p5 8 605 #define an_x4_abilities_os_mode_enum_OS_MODE_20p625 12 606 607 /**************************************************************************** 608 * Enums: an_x4_abilities_scr_modes 609 */ 610 #define an_x4_abilities_scr_modes_T_SCR_MODE_BYPASS 0 611 #define an_x4_abilities_scr_modes_T_SCR_MODE_CL49 1 612 #define an_x4_abilities_scr_modes_T_SCR_MODE_40G_2_LANE 2 613 #define an_x4_abilities_scr_modes_T_SCR_MODE_100G 3 614 #define an_x4_abilities_scr_modes_T_SCR_MODE_20G 4 615 #define an_x4_abilities_scr_modes_T_SCR_MODE_40G_4_LANE 5 616 617 /**************************************************************************** 618 * Enums: an_x4_abilities_descr_modes 619 */ 620 #define an_x4_abilities_descr_modes_R_DESCR_MODE_BYPASS 0 621 #define an_x4_abilities_descr_modes_R_DESCR_MODE_CL49 1 622 #define an_x4_abilities_descr_modes_R_DESCR_MODE_CL82 2 623 624 /**************************************************************************** 625 * Enums: an_x4_abilities_r_dec_tl_mode 626 */ 627 #define an_x4_abilities_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 628 #define an_x4_abilities_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 629 #define an_x4_abilities_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 630 631 /**************************************************************************** 632 * Enums: an_x4_abilities_r_dec_fsm_mode 633 */ 634 #define an_x4_abilities_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 635 #define an_x4_abilities_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 636 #define an_x4_abilities_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 637 638 /**************************************************************************** 639 * Enums: an_x4_abilities_r_deskew_mode 640 */ 641 #define an_x4_abilities_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 642 #define an_x4_abilities_r_deskew_mode_R_DESKEW_MODE_20G 1 643 #define an_x4_abilities_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 644 #define an_x4_abilities_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 645 #define an_x4_abilities_r_deskew_mode_R_DESKEW_MODE_100G 4 646 #define an_x4_abilities_r_deskew_mode_R_DESKEW_MODE_CL49 5 647 #define an_x4_abilities_r_deskew_mode_R_DESKEW_MODE_CL91 6 648 649 /**************************************************************************** 650 * Enums: an_x4_abilities_bs_dist_modes 651 */ 652 #define an_x4_abilities_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 653 #define an_x4_abilities_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 654 #define an_x4_abilities_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 655 #define an_x4_abilities_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 656 657 /**************************************************************************** 658 * Enums: an_x4_abilities_cl49_t_type 659 */ 660 #define an_x4_abilities_cl49_t_type_BAD_T_TYPE 15 661 #define an_x4_abilities_cl49_t_type_T_TYPE_B0 11 662 #define an_x4_abilities_cl49_t_type_T_TYPE_OB 10 663 #define an_x4_abilities_cl49_t_type_T_TYPE_B1 9 664 #define an_x4_abilities_cl49_t_type_T_TYPE_DB 8 665 #define an_x4_abilities_cl49_t_type_T_TYPE_FC 7 666 #define an_x4_abilities_cl49_t_type_T_TYPE_TB 6 667 #define an_x4_abilities_cl49_t_type_T_TYPE_LI 5 668 #define an_x4_abilities_cl49_t_type_T_TYPE_C 4 669 #define an_x4_abilities_cl49_t_type_T_TYPE_S 3 670 #define an_x4_abilities_cl49_t_type_T_TYPE_T 2 671 #define an_x4_abilities_cl49_t_type_T_TYPE_D 1 672 #define an_x4_abilities_cl49_t_type_T_TYPE_E 0 673 674 /**************************************************************************** 675 * Enums: an_x4_abilities_cl49_txsm_states 676 */ 677 #define an_x4_abilities_cl49_txsm_states_TX_HIG_END 7 678 #define an_x4_abilities_cl49_txsm_states_TX_HIG_START 6 679 #define an_x4_abilities_cl49_txsm_states_TX_LI 5 680 #define an_x4_abilities_cl49_txsm_states_TX_E 4 681 #define an_x4_abilities_cl49_txsm_states_TX_T 3 682 #define an_x4_abilities_cl49_txsm_states_TX_D 2 683 #define an_x4_abilities_cl49_txsm_states_TX_C 1 684 #define an_x4_abilities_cl49_txsm_states_TX_INIT 0 685 686 /**************************************************************************** 687 * Enums: an_x4_abilities_cl49_ltxsm_states 688 */ 689 #define an_x4_abilities_cl49_ltxsm_states_TX_HIG_END 128 690 #define an_x4_abilities_cl49_ltxsm_states_TX_HIG_START 64 691 #define an_x4_abilities_cl49_ltxsm_states_TX_LI 32 692 #define an_x4_abilities_cl49_ltxsm_states_TX_E 16 693 #define an_x4_abilities_cl49_ltxsm_states_TX_T 8 694 #define an_x4_abilities_cl49_ltxsm_states_TX_D 4 695 #define an_x4_abilities_cl49_ltxsm_states_TX_C 2 696 #define an_x4_abilities_cl49_ltxsm_states_TX_INIT 1 697 698 /**************************************************************************** 699 * Enums: an_x4_abilities_burst_error_mode 700 */ 701 #define an_x4_abilities_burst_error_mode_BURST_ERROR_11_BITS 0 702 #define an_x4_abilities_burst_error_mode_BURST_ERROR_16_BITS 1 703 #define an_x4_abilities_burst_error_mode_BURST_ERROR_17_BITS 2 704 #define an_x4_abilities_burst_error_mode_BURST_ERROR_18_BITS 3 705 #define an_x4_abilities_burst_error_mode_BURST_ERROR_19_BITS 4 706 #define an_x4_abilities_burst_error_mode_BURST_ERROR_20_BITS 5 707 #define an_x4_abilities_burst_error_mode_BURST_ERROR_21_BITS 6 708 #define an_x4_abilities_burst_error_mode_BURST_ERROR_22_BITS 7 709 #define an_x4_abilities_burst_error_mode_BURST_ERROR_23_BITS 8 710 #define an_x4_abilities_burst_error_mode_BURST_ERROR_24_BITS 9 711 #define an_x4_abilities_burst_error_mode_BURST_ERROR_25_BITS 10 712 #define an_x4_abilities_burst_error_mode_BURST_ERROR_26_BITS 11 713 #define an_x4_abilities_burst_error_mode_BURST_ERROR_27_BITS 12 714 #define an_x4_abilities_burst_error_mode_BURST_ERROR_28_BITS 13 715 #define an_x4_abilities_burst_error_mode_BURST_ERROR_29_BITS 14 716 #define an_x4_abilities_burst_error_mode_BURST_ERROR_30_BITS 15 717 #define an_x4_abilities_burst_error_mode_BURST_ERROR_31_BITS 16 718 #define an_x4_abilities_burst_error_mode_BURST_ERROR_32_BITS 17 719 #define an_x4_abilities_burst_error_mode_BURST_ERROR_33_BITS 18 720 #define an_x4_abilities_burst_error_mode_BURST_ERROR_34_BITS 19 721 #define an_x4_abilities_burst_error_mode_BURST_ERROR_35_BITS 20 722 #define an_x4_abilities_burst_error_mode_BURST_ERROR_36_BITS 21 723 #define an_x4_abilities_burst_error_mode_BURST_ERROR_37_BITS 22 724 #define an_x4_abilities_burst_error_mode_BURST_ERROR_38_BITS 23 725 #define an_x4_abilities_burst_error_mode_BURST_ERROR_39_BITS 24 726 #define an_x4_abilities_burst_error_mode_BURST_ERROR_40_BITS 25 727 #define an_x4_abilities_burst_error_mode_BURST_ERROR_41_BITS 26 728 729 /**************************************************************************** 730 * Enums: an_x4_abilities_bermon_state 731 */ 732 #define an_x4_abilities_bermon_state_HI_BER 4 733 #define an_x4_abilities_bermon_state_GOOD_BER 3 734 #define an_x4_abilities_bermon_state_BER_TEST_SH 2 735 #define an_x4_abilities_bermon_state_START_TIMER 1 736 #define an_x4_abilities_bermon_state_BER_MT_INIT 0 737 738 /**************************************************************************** 739 * Enums: an_x4_abilities_rxsm_state_cl49 740 */ 741 #define an_x4_abilities_rxsm_state_cl49_RX_HIG_END 128 742 #define an_x4_abilities_rxsm_state_cl49_RX_HIG_START 64 743 #define an_x4_abilities_rxsm_state_cl49_RX_LI 32 744 #define an_x4_abilities_rxsm_state_cl49_RX_E 16 745 #define an_x4_abilities_rxsm_state_cl49_RX_T 8 746 #define an_x4_abilities_rxsm_state_cl49_RX_D 4 747 #define an_x4_abilities_rxsm_state_cl49_RX_C 2 748 #define an_x4_abilities_rxsm_state_cl49_RX_INIT 1 749 750 /**************************************************************************** 751 * Enums: an_x4_abilities_r_type 752 */ 753 #define an_x4_abilities_r_type_BAD_R_TYPE 15 754 #define an_x4_abilities_r_type_R_TYPE_B0 11 755 #define an_x4_abilities_r_type_R_TYPE_OB 10 756 #define an_x4_abilities_r_type_R_TYPE_B1 9 757 #define an_x4_abilities_r_type_R_TYPE_DB 8 758 #define an_x4_abilities_r_type_R_TYPE_FC 7 759 #define an_x4_abilities_r_type_R_TYPE_TB 6 760 #define an_x4_abilities_r_type_R_TYPE_LI 5 761 #define an_x4_abilities_r_type_R_TYPE_C 4 762 #define an_x4_abilities_r_type_R_TYPE_S 3 763 #define an_x4_abilities_r_type_R_TYPE_T 2 764 #define an_x4_abilities_r_type_R_TYPE_D 1 765 #define an_x4_abilities_r_type_R_TYPE_E 0 766 767 /**************************************************************************** 768 * Enums: an_x4_abilities_am_lock_state 769 */ 770 #define an_x4_abilities_am_lock_state_INVALID_AM 512 771 #define an_x4_abilities_am_lock_state_GOOD_AM 256 772 #define an_x4_abilities_am_lock_state_COMP_AM 128 773 #define an_x4_abilities_am_lock_state_TIMER_2 64 774 #define an_x4_abilities_am_lock_state_AM_2_GOOD 32 775 #define an_x4_abilities_am_lock_state_COMP_2ND 16 776 #define an_x4_abilities_am_lock_state_TIMER_1 8 777 #define an_x4_abilities_am_lock_state_FIND_1ST 4 778 #define an_x4_abilities_am_lock_state_AM_RESET_CNT 2 779 #define an_x4_abilities_am_lock_state_AM_LOCK_INIT 1 780 781 /**************************************************************************** 782 * Enums: an_x4_abilities_msg_selector 783 */ 784 #define an_x4_abilities_msg_selector_RESERVED 0 785 #define an_x4_abilities_msg_selector_VALUE_802p3 1 786 #define an_x4_abilities_msg_selector_VALUE_802p9 2 787 #define an_x4_abilities_msg_selector_VALUE_802p5 3 788 #define an_x4_abilities_msg_selector_VALUE_1394 4 789 790 /**************************************************************************** 791 * Enums: an_x4_abilities_synce_enum 792 */ 793 #define an_x4_abilities_synce_enum_SYNCE_NO_DIV 0 794 #define an_x4_abilities_synce_enum_SYNCE_DIV_7 1 795 #define an_x4_abilities_synce_enum_SYNCE_DIV_11 2 796 797 /**************************************************************************** 798 * Enums: an_x4_abilities_synce_enum_stage0 799 */ 800 #define an_x4_abilities_synce_enum_stage0_SYNCE_NO_DIV 0 801 #define an_x4_abilities_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 802 #define an_x4_abilities_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 803 804 /**************************************************************************** 805 * Enums: an_x4_abilities_cl91_sync_state 806 */ 807 #define an_x4_abilities_cl91_sync_state_FIND_1ST 0 808 #define an_x4_abilities_cl91_sync_state_COUNT_NEXT 1 809 #define an_x4_abilities_cl91_sync_state_COMP_2ND 2 810 #define an_x4_abilities_cl91_sync_state_TWO_GOOD 3 811 812 /**************************************************************************** 813 * Enums: an_x4_abilities_cl91_algn_state 814 */ 815 #define an_x4_abilities_cl91_algn_state_LOSS_OF_ALIGNMENT 0 816 #define an_x4_abilities_cl91_algn_state_DESKEW 1 817 #define an_x4_abilities_cl91_algn_state_DESKEW_FAIL 2 818 #define an_x4_abilities_cl91_algn_state_ALIGN_ACQUIRED 3 819 #define an_x4_abilities_cl91_algn_state_CW_GOOD 4 820 #define an_x4_abilities_cl91_algn_state_CW_BAD 5 821 #define an_x4_abilities_cl91_algn_state_THREE_BAD 6 822 823 /**************************************************************************** 824 * Enums: an_x4_abilities_fec_sel 825 */ 826 #define an_x4_abilities_fec_sel_NO_FEC 0 827 #define an_x4_abilities_fec_sel_FEC_CL74 1 828 #define an_x4_abilities_fec_sel_FEC_CL91 2 829 830 /**************************************************************************** 831 * Enums: an_x4_sw_mgmt_tla_ln_seq_status 832 */ 833 #define an_x4_sw_mgmt_tla_ln_seq_status_INIT 1 834 #define an_x4_sw_mgmt_tla_ln_seq_status_SET_AN_SPEED 2 835 #define an_x4_sw_mgmt_tla_ln_seq_status_WAIT_AN_SPEED 4 836 #define an_x4_sw_mgmt_tla_ln_seq_status_WAIT_AN_DONE 8 837 #define an_x4_sw_mgmt_tla_ln_seq_status_SET_RS_SPEED 16 838 #define an_x4_sw_mgmt_tla_ln_seq_status_WAIT_RS_CL72EN 32 839 #define an_x4_sw_mgmt_tla_ln_seq_status_WAIT_RS_SPEED 64 840 #define an_x4_sw_mgmt_tla_ln_seq_status_AN_IGNORE_LINK 128 841 #define an_x4_sw_mgmt_tla_ln_seq_status_AN_GOOD_CHECK 256 842 #define an_x4_sw_mgmt_tla_ln_seq_status_AN_GOOD 512 843 #define an_x4_sw_mgmt_tla_ln_seq_status_AN_FAIL 1024 844 #define an_x4_sw_mgmt_tla_ln_seq_status_AN_DEAD 2048 845 #define an_x4_sw_mgmt_tla_ln_seq_status_WAIT_PD_SPEED 4096 846 #define an_x4_sw_mgmt_tla_ln_seq_status_PD_IGNORE_LINK 8192 847 #define an_x4_sw_mgmt_tla_ln_seq_status_PD_GOOD_CHECK 16384 848 #define an_x4_sw_mgmt_tla_ln_seq_status_SW_SPEED_CHANGE 32768 849 850 /**************************************************************************** 851 * Enums: cl82_cl36TxEEEStates_l 852 */ 853 #define cl82_cl36TxEEEStates_l_TX_REFRESH 8 854 #define cl82_cl36TxEEEStates_l_TX_QUIET 4 855 #define cl82_cl36TxEEEStates_l_TX_SLEEP 2 856 #define cl82_cl36TxEEEStates_l_TX_ACTIVE 1 857 858 /**************************************************************************** 859 * Enums: cl82_cl36TxEEEStates_c 860 */ 861 #define cl82_cl36TxEEEStates_c_TX_REFRESH 3 862 #define cl82_cl36TxEEEStates_c_TX_QUIET 2 863 #define cl82_cl36TxEEEStates_c_TX_SLEEP 1 864 #define cl82_cl36TxEEEStates_c_TX_ACTIVE 0 865 866 /**************************************************************************** 867 * Enums: cl82_cl49TxEEEStates_l 868 */ 869 #define cl82_cl49TxEEEStates_l_SCR_RESET_2 64 870 #define cl82_cl49TxEEEStates_l_SCR_RESET_1 32 871 #define cl82_cl49TxEEEStates_l_TX_WAKE 16 872 #define cl82_cl49TxEEEStates_l_TX_REFRESH 8 873 #define cl82_cl49TxEEEStates_l_TX_QUIET 4 874 #define cl82_cl49TxEEEStates_l_TX_SLEEP 2 875 #define cl82_cl49TxEEEStates_l_TX_ACTIVE 1 876 877 /**************************************************************************** 878 * Enums: cl82_fec_req_enum 879 */ 880 #define cl82_fec_req_enum_FEC_not_supported 0 881 #define cl82_fec_req_enum_FEC_supported_but_not_requested 1 882 #define cl82_fec_req_enum_invalid_setting 2 883 #define cl82_fec_req_enum_FEC_supported_and_requested 3 884 885 /**************************************************************************** 886 * Enums: cl82_cl73_pause_enum 887 */ 888 #define cl82_cl73_pause_enum_No_PAUSE_ability 0 889 #define cl82_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 890 #define cl82_cl73_pause_enum_Symmetric_PAUSE_ability 1 891 #define cl82_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 892 893 /**************************************************************************** 894 * Enums: cl82_cl49TxEEEStates_c 895 */ 896 #define cl82_cl49TxEEEStates_c_SCR_RESET_2 6 897 #define cl82_cl49TxEEEStates_c_SCR_RESET_1 5 898 #define cl82_cl49TxEEEStates_c_TX_WAKE 4 899 #define cl82_cl49TxEEEStates_c_TX_REFRESH 3 900 #define cl82_cl49TxEEEStates_c_TX_QUIET 2 901 #define cl82_cl49TxEEEStates_c_TX_SLEEP 1 902 #define cl82_cl49TxEEEStates_c_TX_ACTIVE 0 903 904 /**************************************************************************** 905 * Enums: cl82_cl36RxEEEStates_l 906 */ 907 #define cl82_cl36RxEEEStates_l_RX_LINK_FAIL 32 908 #define cl82_cl36RxEEEStates_l_RX_WTF 16 909 #define cl82_cl36RxEEEStates_l_RX_WAKE 8 910 #define cl82_cl36RxEEEStates_l_RX_QUIET 4 911 #define cl82_cl36RxEEEStates_l_RX_SLEEP 2 912 #define cl82_cl36RxEEEStates_l_RX_ACTIVE 1 913 914 /**************************************************************************** 915 * Enums: cl82_cl36RxEEEStates_c 916 */ 917 #define cl82_cl36RxEEEStates_c_RX_LINK_FAIL 5 918 #define cl82_cl36RxEEEStates_c_RX_WTF 4 919 #define cl82_cl36RxEEEStates_c_RX_WAKE 3 920 #define cl82_cl36RxEEEStates_c_RX_QUIET 2 921 #define cl82_cl36RxEEEStates_c_RX_SLEEP 1 922 #define cl82_cl36RxEEEStates_c_RX_ACTIVE 0 923 924 /**************************************************************************** 925 * Enums: cl82_cl49RxEEEStates_l 926 */ 927 #define cl82_cl49RxEEEStates_l_RX_LINK_FAIL 32 928 #define cl82_cl49RxEEEStates_l_RX_WTF 16 929 #define cl82_cl49RxEEEStates_l_RX_WAKE 8 930 #define cl82_cl49RxEEEStates_l_RX_QUIET 4 931 #define cl82_cl49RxEEEStates_l_RX_SLEEP 2 932 #define cl82_cl49RxEEEStates_l_RX_ACTIVE 1 933 934 /**************************************************************************** 935 * Enums: cl82_cl49RxEEEStates_c 936 */ 937 #define cl82_cl49RxEEEStates_c_RX_LINK_FAIL 5 938 #define cl82_cl49RxEEEStates_c_RX_WTF 4 939 #define cl82_cl49RxEEEStates_c_RX_WAKE 3 940 #define cl82_cl49RxEEEStates_c_RX_QUIET 2 941 #define cl82_cl49RxEEEStates_c_RX_SLEEP 1 942 #define cl82_cl49RxEEEStates_c_RX_ACTIVE 0 943 944 /**************************************************************************** 945 * Enums: cl82_cl48TxEEEStates_l 946 */ 947 #define cl82_cl48TxEEEStates_l_TX_REFRESH 8 948 #define cl82_cl48TxEEEStates_l_TX_QUIET 4 949 #define cl82_cl48TxEEEStates_l_TX_SLEEP 2 950 #define cl82_cl48TxEEEStates_l_TX_ACTIVE 1 951 952 /**************************************************************************** 953 * Enums: cl82_cl48TxEEEStates_c 954 */ 955 #define cl82_cl48TxEEEStates_c_TX_REFRESH 3 956 #define cl82_cl48TxEEEStates_c_TX_QUIET 2 957 #define cl82_cl48TxEEEStates_c_TX_SLEEP 1 958 #define cl82_cl48TxEEEStates_c_TX_ACTIVE 0 959 960 /**************************************************************************** 961 * Enums: cl82_cl48RxEEEStates_l 962 */ 963 #define cl82_cl48RxEEEStates_l_RX_LINK_FAIL 32 964 #define cl82_cl48RxEEEStates_l_RX_WAKE 16 965 #define cl82_cl48RxEEEStates_l_RX_QUIET 8 966 #define cl82_cl48RxEEEStates_l_RX_DEACT 4 967 #define cl82_cl48RxEEEStates_l_RX_SLEEP 2 968 #define cl82_cl48RxEEEStates_l_RX_ACTIVE 1 969 970 /**************************************************************************** 971 * Enums: cl82_cl48RxEEEStates_c 972 */ 973 #define cl82_cl48RxEEEStates_c_RX_LINK_FAIL 5 974 #define cl82_cl48RxEEEStates_c_RX_WAKE 4 975 #define cl82_cl48RxEEEStates_c_RX_QUIET 3 976 #define cl82_cl48RxEEEStates_c_RX_DEACT 2 977 #define cl82_cl48RxEEEStates_c_RX_SLEEP 1 978 #define cl82_cl48RxEEEStates_c_RX_ACTIVE 0 979 980 /**************************************************************************** 981 * Enums: cl82_IQP_Options 982 */ 983 #define cl82_IQP_Options_i50uA 0 984 #define cl82_IQP_Options_i100uA 1 985 #define cl82_IQP_Options_i150uA 2 986 #define cl82_IQP_Options_i200uA 3 987 #define cl82_IQP_Options_i250uA 4 988 #define cl82_IQP_Options_i300uA 5 989 #define cl82_IQP_Options_i350uA 6 990 #define cl82_IQP_Options_i400uA 7 991 #define cl82_IQP_Options_i450uA 8 992 #define cl82_IQP_Options_i500uA 9 993 #define cl82_IQP_Options_i550uA 10 994 #define cl82_IQP_Options_i600uA 11 995 #define cl82_IQP_Options_i650uA 12 996 #define cl82_IQP_Options_i700uA 13 997 #define cl82_IQP_Options_i750uA 14 998 #define cl82_IQP_Options_i800uA 15 999 1000 /**************************************************************************** 1001 * Enums: cl82_IDriver_Options 1002 */ 1003 #define cl82_IDriver_Options_v680mV 0 1004 #define cl82_IDriver_Options_v730mV 1 1005 #define cl82_IDriver_Options_v780mV 2 1006 #define cl82_IDriver_Options_v830mV 3 1007 #define cl82_IDriver_Options_v880mV 4 1008 #define cl82_IDriver_Options_v930mV 5 1009 #define cl82_IDriver_Options_v980mV 6 1010 #define cl82_IDriver_Options_v1010mV 7 1011 #define cl82_IDriver_Options_v1040mV 8 1012 #define cl82_IDriver_Options_v1060mV 9 1013 #define cl82_IDriver_Options_v1070mV 10 1014 #define cl82_IDriver_Options_v1080mV 11 1015 #define cl82_IDriver_Options_v1085mV 12 1016 #define cl82_IDriver_Options_v1090mV 13 1017 #define cl82_IDriver_Options_v1095mV 14 1018 #define cl82_IDriver_Options_v1100mV 15 1019 1020 /**************************************************************************** 1021 * Enums: cl82_operationModes 1022 */ 1023 #define cl82_operationModes_XGXS 0 1024 #define cl82_operationModes_XGXG_nCC 1 1025 #define cl82_operationModes_Indlane_OS8 4 1026 #define cl82_operationModes_IndLane_OS5 5 1027 #define cl82_operationModes_PCI 7 1028 #define cl82_operationModes_XGXS_nLQ 8 1029 #define cl82_operationModes_XGXS_nLQnCC 9 1030 #define cl82_operationModes_PBypass 10 1031 #define cl82_operationModes_PBypass_nDSK 11 1032 #define cl82_operationModes_ComboCoreMode 12 1033 #define cl82_operationModes_Clocks_off 15 1034 1035 /**************************************************************************** 1036 * Enums: cl82_actualSpeeds 1037 */ 1038 #define cl82_actualSpeeds_dr_10M 0 1039 #define cl82_actualSpeeds_dr_100M 1 1040 #define cl82_actualSpeeds_dr_1G 2 1041 #define cl82_actualSpeeds_dr_2p5G 3 1042 #define cl82_actualSpeeds_dr_5G_X4 4 1043 #define cl82_actualSpeeds_dr_6G_X4 5 1044 #define cl82_actualSpeeds_dr_10G_HiG 6 1045 #define cl82_actualSpeeds_dr_10G_CX4 7 1046 #define cl82_actualSpeeds_dr_12G_HiG 8 1047 #define cl82_actualSpeeds_dr_12p5G_X4 9 1048 #define cl82_actualSpeeds_dr_13G_X4 10 1049 #define cl82_actualSpeeds_dr_15G_X4 11 1050 #define cl82_actualSpeeds_dr_16G_X4 12 1051 #define cl82_actualSpeeds_dr_1G_KX 13 1052 #define cl82_actualSpeeds_dr_10G_KX4 14 1053 #define cl82_actualSpeeds_dr_10G_KR 15 1054 #define cl82_actualSpeeds_dr_5G 16 1055 #define cl82_actualSpeeds_dr_6p4G 17 1056 #define cl82_actualSpeeds_dr_20G_X4 18 1057 #define cl82_actualSpeeds_dr_21G_X4 19 1058 #define cl82_actualSpeeds_dr_25G_X4 20 1059 #define cl82_actualSpeeds_dr_10G_HiG_DXGXS 21 1060 #define cl82_actualSpeeds_dr_10G_DXGXS 22 1061 #define cl82_actualSpeeds_dr_10p5G_HiG_DXGXS 23 1062 #define cl82_actualSpeeds_dr_10p5G_DXGXS 24 1063 #define cl82_actualSpeeds_dr_12p773G_HiG_DXGXS 25 1064 #define cl82_actualSpeeds_dr_12p773G_DXGXS 26 1065 #define cl82_actualSpeeds_dr_10G_XFI 27 1066 #define cl82_actualSpeeds_dr_40G 28 1067 #define cl82_actualSpeeds_dr_20G_HiG_DXGXS 29 1068 #define cl82_actualSpeeds_dr_20G_DXGXS 30 1069 #define cl82_actualSpeeds_dr_10G_SFI 31 1070 #define cl82_actualSpeeds_dr_31p5G 32 1071 #define cl82_actualSpeeds_dr_32p7G 33 1072 #define cl82_actualSpeeds_dr_20G_SCR 34 1073 #define cl82_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 1074 #define cl82_actualSpeeds_dr_10G_DXGXS_SCR 36 1075 #define cl82_actualSpeeds_dr_12G_R2 37 1076 #define cl82_actualSpeeds_dr_10G_X2 38 1077 #define cl82_actualSpeeds_dr_40G_KR4 39 1078 #define cl82_actualSpeeds_dr_40G_CR4 40 1079 #define cl82_actualSpeeds_dr_100G_CR10 41 1080 #define cl82_actualSpeeds_dr_15p75G_DXGXS 44 1081 #define cl82_actualSpeeds_dr_20G_KR2 57 1082 #define cl82_actualSpeeds_dr_20G_CR2 58 1083 1084 /**************************************************************************** 1085 * Enums: cl82_actualSpeedsMisc1 1086 */ 1087 #define cl82_actualSpeedsMisc1_dr_2500BRCM_X1 16 1088 #define cl82_actualSpeedsMisc1_dr_5000BRCM_X4 17 1089 #define cl82_actualSpeedsMisc1_dr_6000BRCM_X4 18 1090 #define cl82_actualSpeedsMisc1_dr_10GHiGig_X4 19 1091 #define cl82_actualSpeedsMisc1_dr_10GBASE_CX4 20 1092 #define cl82_actualSpeedsMisc1_dr_12GHiGig_X4 21 1093 #define cl82_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 1094 #define cl82_actualSpeedsMisc1_dr_13GHiGig_X4 23 1095 #define cl82_actualSpeedsMisc1_dr_15GHiGig_X4 24 1096 #define cl82_actualSpeedsMisc1_dr_16GHiGig_X4 25 1097 #define cl82_actualSpeedsMisc1_dr_5000BRCM_X1 26 1098 #define cl82_actualSpeedsMisc1_dr_6363BRCM_X1 27 1099 #define cl82_actualSpeedsMisc1_dr_20GHiGig_X4 28 1100 #define cl82_actualSpeedsMisc1_dr_21GHiGig_X4 29 1101 #define cl82_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 1102 #define cl82_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 1103 1104 /**************************************************************************** 1105 * Enums: cl82_IndLaneModes 1106 */ 1107 #define cl82_IndLaneModes_SWSDR_div2 0 1108 #define cl82_IndLaneModes_SWSDR_div1 1 1109 #define cl82_IndLaneModes_DWSDR_div2 2 1110 #define cl82_IndLaneModes_DWSDR_div1 3 1111 1112 /**************************************************************************** 1113 * Enums: cl82_prbsSelect 1114 */ 1115 #define cl82_prbsSelect_prbs7 0 1116 #define cl82_prbsSelect_prbs15 1 1117 #define cl82_prbsSelect_prbs23 2 1118 #define cl82_prbsSelect_prbs31 3 1119 1120 /**************************************************************************** 1121 * Enums: cl82_vcoDivider 1122 */ 1123 #define cl82_vcoDivider_div32 0 1124 #define cl82_vcoDivider_div36 1 1125 #define cl82_vcoDivider_div40 2 1126 #define cl82_vcoDivider_div42 3 1127 #define cl82_vcoDivider_div48 4 1128 #define cl82_vcoDivider_div50 5 1129 #define cl82_vcoDivider_div52 6 1130 #define cl82_vcoDivider_div54 7 1131 #define cl82_vcoDivider_div60 8 1132 #define cl82_vcoDivider_div64 9 1133 #define cl82_vcoDivider_div66 10 1134 #define cl82_vcoDivider_div68 11 1135 #define cl82_vcoDivider_div70 12 1136 #define cl82_vcoDivider_div80 13 1137 #define cl82_vcoDivider_div92 14 1138 #define cl82_vcoDivider_div100 15 1139 1140 /**************************************************************************** 1141 * Enums: cl82_refClkSelect 1142 */ 1143 #define cl82_refClkSelect_clk_25MHz 0 1144 #define cl82_refClkSelect_clk_100MHz 1 1145 #define cl82_refClkSelect_clk_125MHz 2 1146 #define cl82_refClkSelect_clk_156p25MHz 3 1147 #define cl82_refClkSelect_clk_187p5MHz 4 1148 #define cl82_refClkSelect_clk_161p25Mhz 5 1149 #define cl82_refClkSelect_clk_50Mhz 6 1150 #define cl82_refClkSelect_clk_106p25Mhz 7 1151 1152 /**************************************************************************** 1153 * Enums: cl82_aerMMDdevTypeSelect 1154 */ 1155 #define cl82_aerMMDdevTypeSelect_combo_core 0 1156 #define cl82_aerMMDdevTypeSelect_PMA_PMD 1 1157 #define cl82_aerMMDdevTypeSelect_PCS 3 1158 #define cl82_aerMMDdevTypeSelect_PHY 4 1159 #define cl82_aerMMDdevTypeSelect_DTE 5 1160 #define cl82_aerMMDdevTypeSelect_CL73_AN 7 1161 1162 /**************************************************************************** 1163 * Enums: cl82_aerMMDportSelect 1164 */ 1165 #define cl82_aerMMDportSelect_ln0 0 1166 #define cl82_aerMMDportSelect_ln1 1 1167 #define cl82_aerMMDportSelect_ln2 2 1168 #define cl82_aerMMDportSelect_ln3 3 1169 #define cl82_aerMMDportSelect_BCST_ln0_1_2_3 511 1170 #define cl82_aerMMDportSelect_BCST_ln0_1 512 1171 #define cl82_aerMMDportSelect_BCST_ln2_3 513 1172 1173 /**************************************************************************** 1174 * Enums: cl82_firmwareModeSelect 1175 */ 1176 #define cl82_firmwareModeSelect_DEFAULT 0 1177 #define cl82_firmwareModeSelect_SFP_OPT_LR 1 1178 #define cl82_firmwareModeSelect_SFP_DAC 2 1179 #define cl82_firmwareModeSelect_XLAUI 3 1180 #define cl82_firmwareModeSelect_LONG_CH_6G 4 1181 1182 /**************************************************************************** 1183 * Enums: cl82_tempIdxSelect 1184 */ 1185 #define cl82_tempIdxSelect_LTE__22p9C 15 1186 #define cl82_tempIdxSelect_LTE__12p6C 14 1187 #define cl82_tempIdxSelect_LTE__3p0C 13 1188 #define cl82_tempIdxSelect_LTE_6p7C 12 1189 #define cl82_tempIdxSelect_LTE_16p4C 11 1190 #define cl82_tempIdxSelect_LTE_26p6C 10 1191 #define cl82_tempIdxSelect_LTE_36p3C 9 1192 #define cl82_tempIdxSelect_LTE_46p0C 8 1193 #define cl82_tempIdxSelect_LTE_56p2C 7 1194 #define cl82_tempIdxSelect_LTE_65p9C 6 1195 #define cl82_tempIdxSelect_LTE_75p6C 5 1196 #define cl82_tempIdxSelect_LTE_85p3C 4 1197 #define cl82_tempIdxSelect_LTE_95p5C 3 1198 #define cl82_tempIdxSelect_LTE_105p2C 2 1199 #define cl82_tempIdxSelect_LTE_114p9C 1 1200 #define cl82_tempIdxSelect_LTE_125p1C 0 1201 1202 /**************************************************************************** 1203 * Enums: cl82_port_mode 1204 */ 1205 #define cl82_port_mode_QUAD_PORT 0 1206 #define cl82_port_mode_TRI_1_PORT 1 1207 #define cl82_port_mode_TRI_2_PORT 2 1208 #define cl82_port_mode_DUAL_PORT 3 1209 #define cl82_port_mode_SINGLE_PORT 4 1210 1211 /**************************************************************************** 1212 * Enums: cl82_rev_letter_enum 1213 */ 1214 #define cl82_rev_letter_enum_REV_A 0 1215 #define cl82_rev_letter_enum_REV_B 1 1216 #define cl82_rev_letter_enum_REV_C 2 1217 #define cl82_rev_letter_enum_REV_D 3 1218 1219 /**************************************************************************** 1220 * Enums: cl82_rev_number_enum 1221 */ 1222 #define cl82_rev_number_enum_REV_0 0 1223 #define cl82_rev_number_enum_REV_1 1 1224 #define cl82_rev_number_enum_REV_2 2 1225 #define cl82_rev_number_enum_REV_3 3 1226 #define cl82_rev_number_enum_REV_4 4 1227 #define cl82_rev_number_enum_REV_5 5 1228 #define cl82_rev_number_enum_REV_6 6 1229 #define cl82_rev_number_enum_REV_7 7 1230 1231 /**************************************************************************** 1232 * Enums: cl82_bonding_enum 1233 */ 1234 #define cl82_bonding_enum_WIRE_BOND 0 1235 #define cl82_bonding_enum_FLIP_CHIP 1 1236 1237 /**************************************************************************** 1238 * Enums: cl82_tech_process 1239 */ 1240 #define cl82_tech_process_PROCESS_90NM 0 1241 #define cl82_tech_process_PROCESS_65NM 1 1242 #define cl82_tech_process_PROCESS_40NM 2 1243 #define cl82_tech_process_PROCESS_28NM 3 1244 1245 /**************************************************************************** 1246 * Enums: cl82_model_num 1247 */ 1248 #define cl82_model_num_SERDES_CL73 0 1249 #define cl82_model_num_XGXS_16G 1 1250 #define cl82_model_num_HYPERCORE 2 1251 #define cl82_model_num_HYPERLITE 3 1252 #define cl82_model_num_PCIE_G2_PIPE 4 1253 #define cl82_model_num_SERDES_1p25GBd 5 1254 #define cl82_model_num_SATA2 6 1255 #define cl82_model_num_QSGMII 7 1256 #define cl82_model_num_XGXS10G 8 1257 #define cl82_model_num_WARPCORE 9 1258 #define cl82_model_num_XFICORE 10 1259 #define cl82_model_num_RXFI 11 1260 #define cl82_model_num_WARPLITE 12 1261 #define cl82_model_num_PENTACORE 13 1262 #define cl82_model_num_ESM 14 1263 #define cl82_model_num_QUAD_SGMII 15 1264 #define cl82_model_num_WARPCORE_3 16 1265 #define cl82_model_num_TSC 17 1266 #define cl82_model_num_TSC4E 18 1267 #define cl82_model_num_TSC12E 19 1268 #define cl82_model_num_TSC4F 20 1269 #define cl82_model_num_XGXS_CL73_90NM 29 1270 #define cl82_model_num_SERDES_CL73_90NM 30 1271 #define cl82_model_num_WARPCORE3 32 1272 #define cl82_model_num_WARPCORE4_TSC 33 1273 #define cl82_model_num_RXAUI 34 1274 1275 /**************************************************************************** 1276 * Enums: cl82_payload 1277 */ 1278 #define cl82_payload_REPEAT_2_BYTES 0 1279 #define cl82_payload_RAMPING 1 1280 #define cl82_payload_CL48_CRPAT 2 1281 #define cl82_payload_CL48_CJPAT 3 1282 #define cl82_payload_CL36_LONG_CRPAT 4 1283 #define cl82_payload_CL36_SHORT_CRPAT 5 1284 1285 /**************************************************************************** 1286 * Enums: cl82_sc 1287 */ 1288 #define cl82_sc_S_10G_CR1 0 1289 #define cl82_sc_S_10G_KR1 1 1290 #define cl82_sc_S_10G_X1 2 1291 #define cl82_sc_S_10G_HG2_CR1 4 1292 #define cl82_sc_S_10G_HG2_KR1 5 1293 #define cl82_sc_S_10G_HG2_X1 6 1294 #define cl82_sc_S_20G_CR1 8 1295 #define cl82_sc_S_20G_KR1 9 1296 #define cl82_sc_S_20G_X1 10 1297 #define cl82_sc_S_20G_HG2_CR1 12 1298 #define cl82_sc_S_20G_HG2_KR1 13 1299 #define cl82_sc_S_20G_HG2_X1 14 1300 #define cl82_sc_S_25G_CR1 16 1301 #define cl82_sc_S_25G_KR1 17 1302 #define cl82_sc_S_25G_X1 18 1303 #define cl82_sc_S_25G_HG2_CR1 20 1304 #define cl82_sc_S_25G_HG2_KR1 21 1305 #define cl82_sc_S_25G_HG2_X1 22 1306 #define cl82_sc_S_20G_CR2 24 1307 #define cl82_sc_S_20G_KR2 25 1308 #define cl82_sc_S_20G_X2 26 1309 #define cl82_sc_S_20G_HG2_CR2 28 1310 #define cl82_sc_S_20G_HG2_KR2 29 1311 #define cl82_sc_S_20G_HG2_X2 30 1312 #define cl82_sc_S_40G_CR2 32 1313 #define cl82_sc_S_40G_KR2 33 1314 #define cl82_sc_S_40G_X2 34 1315 #define cl82_sc_S_40G_HG2_CR2 36 1316 #define cl82_sc_S_40G_HG2_KR2 37 1317 #define cl82_sc_S_40G_HG2_X2 38 1318 #define cl82_sc_S_40G_CR4 40 1319 #define cl82_sc_S_40G_KR4 41 1320 #define cl82_sc_S_40G_X4 42 1321 #define cl82_sc_S_40G_HG2_CR4 44 1322 #define cl82_sc_S_40G_HG2_KR4 45 1323 #define cl82_sc_S_40G_HG2_X4 46 1324 #define cl82_sc_S_50G_CR2 48 1325 #define cl82_sc_S_50G_KR2 49 1326 #define cl82_sc_S_50G_X2 50 1327 #define cl82_sc_S_50G_HG2_CR2 52 1328 #define cl82_sc_S_50G_HG2_KR2 53 1329 #define cl82_sc_S_50G_HG2_X2 54 1330 #define cl82_sc_S_50G_CR4 56 1331 #define cl82_sc_S_50G_KR4 57 1332 #define cl82_sc_S_50G_X4 58 1333 #define cl82_sc_S_50G_HG2_CR4 60 1334 #define cl82_sc_S_50G_HG2_KR4 61 1335 #define cl82_sc_S_50G_HG2_X4 62 1336 #define cl82_sc_S_100G_CR4 64 1337 #define cl82_sc_S_100G_KR4 65 1338 #define cl82_sc_S_100G_X4 66 1339 #define cl82_sc_S_100G_HG2_CR4 68 1340 #define cl82_sc_S_100G_HG2_KR4 69 1341 #define cl82_sc_S_100G_HG2_X4 70 1342 #define cl82_sc_S_CL73_20GVCO 72 1343 #define cl82_sc_S_CL73_25GVCO 80 1344 #define cl82_sc_S_CL36_20GVCO 88 1345 #define cl82_sc_S_CL36_25GVCO 96 1346 1347 /**************************************************************************** 1348 * Enums: cl82_t_fifo_modes 1349 */ 1350 #define cl82_t_fifo_modes_T_FIFO_MODE_BYPASS 0 1351 #define cl82_t_fifo_modes_T_FIFO_MODE_40G 1 1352 #define cl82_t_fifo_modes_T_FIFO_MODE_100G 2 1353 #define cl82_t_fifo_modes_T_FIFO_MODE_20G 3 1354 1355 /**************************************************************************** 1356 * Enums: cl82_t_enc_modes 1357 */ 1358 #define cl82_t_enc_modes_T_ENC_MODE_BYPASS 0 1359 #define cl82_t_enc_modes_T_ENC_MODE_CL49 1 1360 #define cl82_t_enc_modes_T_ENC_MODE_CL82 2 1361 1362 /**************************************************************************** 1363 * Enums: cl82_btmx_mode 1364 */ 1365 #define cl82_btmx_mode_BS_BTMX_MODE_1to1 0 1366 #define cl82_btmx_mode_BS_BTMX_MODE_2to1 1 1367 #define cl82_btmx_mode_BS_BTMX_MODE_5to1 2 1368 1369 /**************************************************************************** 1370 * Enums: cl82_t_type_cl82 1371 */ 1372 #define cl82_t_type_cl82_T_TYPE_B1 5 1373 #define cl82_t_type_cl82_T_TYPE_C 4 1374 #define cl82_t_type_cl82_T_TYPE_S 3 1375 #define cl82_t_type_cl82_T_TYPE_T 2 1376 #define cl82_t_type_cl82_T_TYPE_D 1 1377 #define cl82_t_type_cl82_T_TYPE_E 0 1378 1379 /**************************************************************************** 1380 * Enums: cl82_txsm_state_cl82 1381 */ 1382 #define cl82_txsm_state_cl82_TX_HIG_END 6 1383 #define cl82_txsm_state_cl82_TX_HIG_START 5 1384 #define cl82_txsm_state_cl82_TX_E 4 1385 #define cl82_txsm_state_cl82_TX_T 3 1386 #define cl82_txsm_state_cl82_TX_D 2 1387 #define cl82_txsm_state_cl82_TX_C 1 1388 #define cl82_txsm_state_cl82_TX_INIT 0 1389 1390 /**************************************************************************** 1391 * Enums: cl82_ltxsm_state_cl82 1392 */ 1393 #define cl82_ltxsm_state_cl82_TX_HIG_END 64 1394 #define cl82_ltxsm_state_cl82_TX_HIG_START 32 1395 #define cl82_ltxsm_state_cl82_TX_E 16 1396 #define cl82_ltxsm_state_cl82_TX_T 8 1397 #define cl82_ltxsm_state_cl82_TX_D 4 1398 #define cl82_ltxsm_state_cl82_TX_C 2 1399 #define cl82_ltxsm_state_cl82_TX_INIT 1 1400 1401 /**************************************************************************** 1402 * Enums: cl82_r_type_coded_cl82 1403 */ 1404 #define cl82_r_type_coded_cl82_R_TYPE_B1 32 1405 #define cl82_r_type_coded_cl82_R_TYPE_C 16 1406 #define cl82_r_type_coded_cl82_R_TYPE_S 8 1407 #define cl82_r_type_coded_cl82_R_TYPE_T 4 1408 #define cl82_r_type_coded_cl82_R_TYPE_D 2 1409 #define cl82_r_type_coded_cl82_R_TYPE_E 1 1410 1411 /**************************************************************************** 1412 * Enums: cl82_rxsm_state_cl82 1413 */ 1414 #define cl82_rxsm_state_cl82_RX_HIG_END 64 1415 #define cl82_rxsm_state_cl82_RX_HIG_START 32 1416 #define cl82_rxsm_state_cl82_RX_E 16 1417 #define cl82_rxsm_state_cl82_RX_T 8 1418 #define cl82_rxsm_state_cl82_RX_D 4 1419 #define cl82_rxsm_state_cl82_RX_C 2 1420 #define cl82_rxsm_state_cl82_RX_INIT 1 1421 1422 /**************************************************************************** 1423 * Enums: cl82_deskew_state 1424 */ 1425 #define cl82_deskew_state_ALIGN_ACQUIRED 2 1426 #define cl82_deskew_state_LOSS_OF_ALIGNMENT 1 1427 1428 /**************************************************************************** 1429 * Enums: cl82_os_mode_enum 1430 */ 1431 #define cl82_os_mode_enum_OS_MODE_1 0 1432 #define cl82_os_mode_enum_OS_MODE_2 1 1433 #define cl82_os_mode_enum_OS_MODE_4 2 1434 #define cl82_os_mode_enum_OS_MODE_16p5 8 1435 #define cl82_os_mode_enum_OS_MODE_20p625 12 1436 1437 /**************************************************************************** 1438 * Enums: cl82_scr_modes 1439 */ 1440 #define cl82_scr_modes_T_SCR_MODE_BYPASS 0 1441 #define cl82_scr_modes_T_SCR_MODE_CL49 1 1442 #define cl82_scr_modes_T_SCR_MODE_40G_2_LANE 2 1443 #define cl82_scr_modes_T_SCR_MODE_100G 3 1444 #define cl82_scr_modes_T_SCR_MODE_20G 4 1445 #define cl82_scr_modes_T_SCR_MODE_40G_4_LANE 5 1446 1447 /**************************************************************************** 1448 * Enums: cl82_descr_modes 1449 */ 1450 #define cl82_descr_modes_R_DESCR_MODE_BYPASS 0 1451 #define cl82_descr_modes_R_DESCR_MODE_CL49 1 1452 #define cl82_descr_modes_R_DESCR_MODE_CL82 2 1453 1454 /**************************************************************************** 1455 * Enums: cl82_r_dec_tl_mode 1456 */ 1457 #define cl82_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 1458 #define cl82_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 1459 #define cl82_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 1460 1461 /**************************************************************************** 1462 * Enums: cl82_r_dec_fsm_mode 1463 */ 1464 #define cl82_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 1465 #define cl82_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 1466 #define cl82_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 1467 1468 /**************************************************************************** 1469 * Enums: cl82_r_deskew_mode 1470 */ 1471 #define cl82_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 1472 #define cl82_r_deskew_mode_R_DESKEW_MODE_20G 1 1473 #define cl82_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 1474 #define cl82_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 1475 #define cl82_r_deskew_mode_R_DESKEW_MODE_100G 4 1476 #define cl82_r_deskew_mode_R_DESKEW_MODE_CL49 5 1477 #define cl82_r_deskew_mode_R_DESKEW_MODE_CL91 6 1478 1479 /**************************************************************************** 1480 * Enums: cl82_bs_dist_modes 1481 */ 1482 #define cl82_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 1483 #define cl82_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 1484 #define cl82_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 1485 #define cl82_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 1486 1487 /**************************************************************************** 1488 * Enums: cl82_cl49_t_type 1489 */ 1490 #define cl82_cl49_t_type_BAD_T_TYPE 15 1491 #define cl82_cl49_t_type_T_TYPE_B0 11 1492 #define cl82_cl49_t_type_T_TYPE_OB 10 1493 #define cl82_cl49_t_type_T_TYPE_B1 9 1494 #define cl82_cl49_t_type_T_TYPE_DB 8 1495 #define cl82_cl49_t_type_T_TYPE_FC 7 1496 #define cl82_cl49_t_type_T_TYPE_TB 6 1497 #define cl82_cl49_t_type_T_TYPE_LI 5 1498 #define cl82_cl49_t_type_T_TYPE_C 4 1499 #define cl82_cl49_t_type_T_TYPE_S 3 1500 #define cl82_cl49_t_type_T_TYPE_T 2 1501 #define cl82_cl49_t_type_T_TYPE_D 1 1502 #define cl82_cl49_t_type_T_TYPE_E 0 1503 1504 /**************************************************************************** 1505 * Enums: cl82_cl49_txsm_states 1506 */ 1507 #define cl82_cl49_txsm_states_TX_HIG_END 7 1508 #define cl82_cl49_txsm_states_TX_HIG_START 6 1509 #define cl82_cl49_txsm_states_TX_LI 5 1510 #define cl82_cl49_txsm_states_TX_E 4 1511 #define cl82_cl49_txsm_states_TX_T 3 1512 #define cl82_cl49_txsm_states_TX_D 2 1513 #define cl82_cl49_txsm_states_TX_C 1 1514 #define cl82_cl49_txsm_states_TX_INIT 0 1515 1516 /**************************************************************************** 1517 * Enums: cl82_cl49_ltxsm_states 1518 */ 1519 #define cl82_cl49_ltxsm_states_TX_HIG_END 128 1520 #define cl82_cl49_ltxsm_states_TX_HIG_START 64 1521 #define cl82_cl49_ltxsm_states_TX_LI 32 1522 #define cl82_cl49_ltxsm_states_TX_E 16 1523 #define cl82_cl49_ltxsm_states_TX_T 8 1524 #define cl82_cl49_ltxsm_states_TX_D 4 1525 #define cl82_cl49_ltxsm_states_TX_C 2 1526 #define cl82_cl49_ltxsm_states_TX_INIT 1 1527 1528 /**************************************************************************** 1529 * Enums: cl82_burst_error_mode 1530 */ 1531 #define cl82_burst_error_mode_BURST_ERROR_11_BITS 0 1532 #define cl82_burst_error_mode_BURST_ERROR_16_BITS 1 1533 #define cl82_burst_error_mode_BURST_ERROR_17_BITS 2 1534 #define cl82_burst_error_mode_BURST_ERROR_18_BITS 3 1535 #define cl82_burst_error_mode_BURST_ERROR_19_BITS 4 1536 #define cl82_burst_error_mode_BURST_ERROR_20_BITS 5 1537 #define cl82_burst_error_mode_BURST_ERROR_21_BITS 6 1538 #define cl82_burst_error_mode_BURST_ERROR_22_BITS 7 1539 #define cl82_burst_error_mode_BURST_ERROR_23_BITS 8 1540 #define cl82_burst_error_mode_BURST_ERROR_24_BITS 9 1541 #define cl82_burst_error_mode_BURST_ERROR_25_BITS 10 1542 #define cl82_burst_error_mode_BURST_ERROR_26_BITS 11 1543 #define cl82_burst_error_mode_BURST_ERROR_27_BITS 12 1544 #define cl82_burst_error_mode_BURST_ERROR_28_BITS 13 1545 #define cl82_burst_error_mode_BURST_ERROR_29_BITS 14 1546 #define cl82_burst_error_mode_BURST_ERROR_30_BITS 15 1547 #define cl82_burst_error_mode_BURST_ERROR_31_BITS 16 1548 #define cl82_burst_error_mode_BURST_ERROR_32_BITS 17 1549 #define cl82_burst_error_mode_BURST_ERROR_33_BITS 18 1550 #define cl82_burst_error_mode_BURST_ERROR_34_BITS 19 1551 #define cl82_burst_error_mode_BURST_ERROR_35_BITS 20 1552 #define cl82_burst_error_mode_BURST_ERROR_36_BITS 21 1553 #define cl82_burst_error_mode_BURST_ERROR_37_BITS 22 1554 #define cl82_burst_error_mode_BURST_ERROR_38_BITS 23 1555 #define cl82_burst_error_mode_BURST_ERROR_39_BITS 24 1556 #define cl82_burst_error_mode_BURST_ERROR_40_BITS 25 1557 #define cl82_burst_error_mode_BURST_ERROR_41_BITS 26 1558 1559 /**************************************************************************** 1560 * Enums: cl82_bermon_state 1561 */ 1562 #define cl82_bermon_state_HI_BER 4 1563 #define cl82_bermon_state_GOOD_BER 3 1564 #define cl82_bermon_state_BER_TEST_SH 2 1565 #define cl82_bermon_state_START_TIMER 1 1566 #define cl82_bermon_state_BER_MT_INIT 0 1567 1568 /**************************************************************************** 1569 * Enums: cl82_rxsm_state_cl49 1570 */ 1571 #define cl82_rxsm_state_cl49_RX_HIG_END 128 1572 #define cl82_rxsm_state_cl49_RX_HIG_START 64 1573 #define cl82_rxsm_state_cl49_RX_LI 32 1574 #define cl82_rxsm_state_cl49_RX_E 16 1575 #define cl82_rxsm_state_cl49_RX_T 8 1576 #define cl82_rxsm_state_cl49_RX_D 4 1577 #define cl82_rxsm_state_cl49_RX_C 2 1578 #define cl82_rxsm_state_cl49_RX_INIT 1 1579 1580 /**************************************************************************** 1581 * Enums: cl82_r_type 1582 */ 1583 #define cl82_r_type_BAD_R_TYPE 15 1584 #define cl82_r_type_R_TYPE_B0 11 1585 #define cl82_r_type_R_TYPE_OB 10 1586 #define cl82_r_type_R_TYPE_B1 9 1587 #define cl82_r_type_R_TYPE_DB 8 1588 #define cl82_r_type_R_TYPE_FC 7 1589 #define cl82_r_type_R_TYPE_TB 6 1590 #define cl82_r_type_R_TYPE_LI 5 1591 #define cl82_r_type_R_TYPE_C 4 1592 #define cl82_r_type_R_TYPE_S 3 1593 #define cl82_r_type_R_TYPE_T 2 1594 #define cl82_r_type_R_TYPE_D 1 1595 #define cl82_r_type_R_TYPE_E 0 1596 1597 /**************************************************************************** 1598 * Enums: cl82_am_lock_state 1599 */ 1600 #define cl82_am_lock_state_INVALID_AM 512 1601 #define cl82_am_lock_state_GOOD_AM 256 1602 #define cl82_am_lock_state_COMP_AM 128 1603 #define cl82_am_lock_state_TIMER_2 64 1604 #define cl82_am_lock_state_AM_2_GOOD 32 1605 #define cl82_am_lock_state_COMP_2ND 16 1606 #define cl82_am_lock_state_TIMER_1 8 1607 #define cl82_am_lock_state_FIND_1ST 4 1608 #define cl82_am_lock_state_AM_RESET_CNT 2 1609 #define cl82_am_lock_state_AM_LOCK_INIT 1 1610 1611 /**************************************************************************** 1612 * Enums: cl82_msg_selector 1613 */ 1614 #define cl82_msg_selector_RESERVED 0 1615 #define cl82_msg_selector_VALUE_802p3 1 1616 #define cl82_msg_selector_VALUE_802p9 2 1617 #define cl82_msg_selector_VALUE_802p5 3 1618 #define cl82_msg_selector_VALUE_1394 4 1619 1620 /**************************************************************************** 1621 * Enums: cl82_synce_enum 1622 */ 1623 #define cl82_synce_enum_SYNCE_NO_DIV 0 1624 #define cl82_synce_enum_SYNCE_DIV_7 1 1625 #define cl82_synce_enum_SYNCE_DIV_11 2 1626 1627 /**************************************************************************** 1628 * Enums: cl82_synce_enum_stage0 1629 */ 1630 #define cl82_synce_enum_stage0_SYNCE_NO_DIV 0 1631 #define cl82_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 1632 #define cl82_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 1633 1634 /**************************************************************************** 1635 * Enums: cl82_cl91_sync_state 1636 */ 1637 #define cl82_cl91_sync_state_FIND_1ST 0 1638 #define cl82_cl91_sync_state_COUNT_NEXT 1 1639 #define cl82_cl91_sync_state_COMP_2ND 2 1640 #define cl82_cl91_sync_state_TWO_GOOD 3 1641 1642 /**************************************************************************** 1643 * Enums: cl82_cl91_algn_state 1644 */ 1645 #define cl82_cl91_algn_state_LOSS_OF_ALIGNMENT 0 1646 #define cl82_cl91_algn_state_DESKEW 1 1647 #define cl82_cl91_algn_state_DESKEW_FAIL 2 1648 #define cl82_cl91_algn_state_ALIGN_ACQUIRED 3 1649 #define cl82_cl91_algn_state_CW_GOOD 4 1650 #define cl82_cl91_algn_state_CW_BAD 5 1651 #define cl82_cl91_algn_state_THREE_BAD 6 1652 1653 /**************************************************************************** 1654 * Enums: cl82_fec_sel 1655 */ 1656 #define cl82_fec_sel_NO_FEC 0 1657 #define cl82_fec_sel_FEC_CL74 1 1658 #define cl82_fec_sel_FEC_CL91 2 1659 1660 /**************************************************************************** 1661 * Enums: main0_cl36TxEEEStates_l 1662 */ 1663 #define main0_cl36TxEEEStates_l_TX_REFRESH 8 1664 #define main0_cl36TxEEEStates_l_TX_QUIET 4 1665 #define main0_cl36TxEEEStates_l_TX_SLEEP 2 1666 #define main0_cl36TxEEEStates_l_TX_ACTIVE 1 1667 1668 /**************************************************************************** 1669 * Enums: main0_cl36TxEEEStates_c 1670 */ 1671 #define main0_cl36TxEEEStates_c_TX_REFRESH 3 1672 #define main0_cl36TxEEEStates_c_TX_QUIET 2 1673 #define main0_cl36TxEEEStates_c_TX_SLEEP 1 1674 #define main0_cl36TxEEEStates_c_TX_ACTIVE 0 1675 1676 /**************************************************************************** 1677 * Enums: main0_cl49TxEEEStates_l 1678 */ 1679 #define main0_cl49TxEEEStates_l_SCR_RESET_2 64 1680 #define main0_cl49TxEEEStates_l_SCR_RESET_1 32 1681 #define main0_cl49TxEEEStates_l_TX_WAKE 16 1682 #define main0_cl49TxEEEStates_l_TX_REFRESH 8 1683 #define main0_cl49TxEEEStates_l_TX_QUIET 4 1684 #define main0_cl49TxEEEStates_l_TX_SLEEP 2 1685 #define main0_cl49TxEEEStates_l_TX_ACTIVE 1 1686 1687 /**************************************************************************** 1688 * Enums: main0_fec_req_enum 1689 */ 1690 #define main0_fec_req_enum_FEC_not_supported 0 1691 #define main0_fec_req_enum_FEC_supported_but_not_requested 1 1692 #define main0_fec_req_enum_invalid_setting 2 1693 #define main0_fec_req_enum_FEC_supported_and_requested 3 1694 1695 /**************************************************************************** 1696 * Enums: main0_cl73_pause_enum 1697 */ 1698 #define main0_cl73_pause_enum_No_PAUSE_ability 0 1699 #define main0_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 1700 #define main0_cl73_pause_enum_Symmetric_PAUSE_ability 1 1701 #define main0_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 1702 1703 /**************************************************************************** 1704 * Enums: main0_cl49TxEEEStates_c 1705 */ 1706 #define main0_cl49TxEEEStates_c_SCR_RESET_2 6 1707 #define main0_cl49TxEEEStates_c_SCR_RESET_1 5 1708 #define main0_cl49TxEEEStates_c_TX_WAKE 4 1709 #define main0_cl49TxEEEStates_c_TX_REFRESH 3 1710 #define main0_cl49TxEEEStates_c_TX_QUIET 2 1711 #define main0_cl49TxEEEStates_c_TX_SLEEP 1 1712 #define main0_cl49TxEEEStates_c_TX_ACTIVE 0 1713 1714 /**************************************************************************** 1715 * Enums: main0_cl36RxEEEStates_l 1716 */ 1717 #define main0_cl36RxEEEStates_l_RX_LINK_FAIL 32 1718 #define main0_cl36RxEEEStates_l_RX_WTF 16 1719 #define main0_cl36RxEEEStates_l_RX_WAKE 8 1720 #define main0_cl36RxEEEStates_l_RX_QUIET 4 1721 #define main0_cl36RxEEEStates_l_RX_SLEEP 2 1722 #define main0_cl36RxEEEStates_l_RX_ACTIVE 1 1723 1724 /**************************************************************************** 1725 * Enums: main0_cl36RxEEEStates_c 1726 */ 1727 #define main0_cl36RxEEEStates_c_RX_LINK_FAIL 5 1728 #define main0_cl36RxEEEStates_c_RX_WTF 4 1729 #define main0_cl36RxEEEStates_c_RX_WAKE 3 1730 #define main0_cl36RxEEEStates_c_RX_QUIET 2 1731 #define main0_cl36RxEEEStates_c_RX_SLEEP 1 1732 #define main0_cl36RxEEEStates_c_RX_ACTIVE 0 1733 1734 /**************************************************************************** 1735 * Enums: main0_cl49RxEEEStates_l 1736 */ 1737 #define main0_cl49RxEEEStates_l_RX_LINK_FAIL 32 1738 #define main0_cl49RxEEEStates_l_RX_WTF 16 1739 #define main0_cl49RxEEEStates_l_RX_WAKE 8 1740 #define main0_cl49RxEEEStates_l_RX_QUIET 4 1741 #define main0_cl49RxEEEStates_l_RX_SLEEP 2 1742 #define main0_cl49RxEEEStates_l_RX_ACTIVE 1 1743 1744 /**************************************************************************** 1745 * Enums: main0_cl49RxEEEStates_c 1746 */ 1747 #define main0_cl49RxEEEStates_c_RX_LINK_FAIL 5 1748 #define main0_cl49RxEEEStates_c_RX_WTF 4 1749 #define main0_cl49RxEEEStates_c_RX_WAKE 3 1750 #define main0_cl49RxEEEStates_c_RX_QUIET 2 1751 #define main0_cl49RxEEEStates_c_RX_SLEEP 1 1752 #define main0_cl49RxEEEStates_c_RX_ACTIVE 0 1753 1754 /**************************************************************************** 1755 * Enums: main0_cl48TxEEEStates_l 1756 */ 1757 #define main0_cl48TxEEEStates_l_TX_REFRESH 8 1758 #define main0_cl48TxEEEStates_l_TX_QUIET 4 1759 #define main0_cl48TxEEEStates_l_TX_SLEEP 2 1760 #define main0_cl48TxEEEStates_l_TX_ACTIVE 1 1761 1762 /**************************************************************************** 1763 * Enums: main0_cl48TxEEEStates_c 1764 */ 1765 #define main0_cl48TxEEEStates_c_TX_REFRESH 3 1766 #define main0_cl48TxEEEStates_c_TX_QUIET 2 1767 #define main0_cl48TxEEEStates_c_TX_SLEEP 1 1768 #define main0_cl48TxEEEStates_c_TX_ACTIVE 0 1769 1770 /**************************************************************************** 1771 * Enums: main0_cl48RxEEEStates_l 1772 */ 1773 #define main0_cl48RxEEEStates_l_RX_LINK_FAIL 32 1774 #define main0_cl48RxEEEStates_l_RX_WAKE 16 1775 #define main0_cl48RxEEEStates_l_RX_QUIET 8 1776 #define main0_cl48RxEEEStates_l_RX_DEACT 4 1777 #define main0_cl48RxEEEStates_l_RX_SLEEP 2 1778 #define main0_cl48RxEEEStates_l_RX_ACTIVE 1 1779 1780 /**************************************************************************** 1781 * Enums: main0_cl48RxEEEStates_c 1782 */ 1783 #define main0_cl48RxEEEStates_c_RX_LINK_FAIL 5 1784 #define main0_cl48RxEEEStates_c_RX_WAKE 4 1785 #define main0_cl48RxEEEStates_c_RX_QUIET 3 1786 #define main0_cl48RxEEEStates_c_RX_DEACT 2 1787 #define main0_cl48RxEEEStates_c_RX_SLEEP 1 1788 #define main0_cl48RxEEEStates_c_RX_ACTIVE 0 1789 1790 /**************************************************************************** 1791 * Enums: main0_IQP_Options 1792 */ 1793 #define main0_IQP_Options_i50uA 0 1794 #define main0_IQP_Options_i100uA 1 1795 #define main0_IQP_Options_i150uA 2 1796 #define main0_IQP_Options_i200uA 3 1797 #define main0_IQP_Options_i250uA 4 1798 #define main0_IQP_Options_i300uA 5 1799 #define main0_IQP_Options_i350uA 6 1800 #define main0_IQP_Options_i400uA 7 1801 #define main0_IQP_Options_i450uA 8 1802 #define main0_IQP_Options_i500uA 9 1803 #define main0_IQP_Options_i550uA 10 1804 #define main0_IQP_Options_i600uA 11 1805 #define main0_IQP_Options_i650uA 12 1806 #define main0_IQP_Options_i700uA 13 1807 #define main0_IQP_Options_i750uA 14 1808 #define main0_IQP_Options_i800uA 15 1809 1810 /**************************************************************************** 1811 * Enums: main0_IDriver_Options 1812 */ 1813 #define main0_IDriver_Options_v680mV 0 1814 #define main0_IDriver_Options_v730mV 1 1815 #define main0_IDriver_Options_v780mV 2 1816 #define main0_IDriver_Options_v830mV 3 1817 #define main0_IDriver_Options_v880mV 4 1818 #define main0_IDriver_Options_v930mV 5 1819 #define main0_IDriver_Options_v980mV 6 1820 #define main0_IDriver_Options_v1010mV 7 1821 #define main0_IDriver_Options_v1040mV 8 1822 #define main0_IDriver_Options_v1060mV 9 1823 #define main0_IDriver_Options_v1070mV 10 1824 #define main0_IDriver_Options_v1080mV 11 1825 #define main0_IDriver_Options_v1085mV 12 1826 #define main0_IDriver_Options_v1090mV 13 1827 #define main0_IDriver_Options_v1095mV 14 1828 #define main0_IDriver_Options_v1100mV 15 1829 1830 /**************************************************************************** 1831 * Enums: main0_operationModes 1832 */ 1833 #define main0_operationModes_XGXS 0 1834 #define main0_operationModes_XGXG_nCC 1 1835 #define main0_operationModes_Indlane_OS8 4 1836 #define main0_operationModes_IndLane_OS5 5 1837 #define main0_operationModes_PCI 7 1838 #define main0_operationModes_XGXS_nLQ 8 1839 #define main0_operationModes_XGXS_nLQnCC 9 1840 #define main0_operationModes_PBypass 10 1841 #define main0_operationModes_PBypass_nDSK 11 1842 #define main0_operationModes_ComboCoreMode 12 1843 #define main0_operationModes_Clocks_off 15 1844 1845 /**************************************************************************** 1846 * Enums: main0_actualSpeeds 1847 */ 1848 #define main0_actualSpeeds_dr_10M 0 1849 #define main0_actualSpeeds_dr_100M 1 1850 #define main0_actualSpeeds_dr_1G 2 1851 #define main0_actualSpeeds_dr_2p5G 3 1852 #define main0_actualSpeeds_dr_5G_X4 4 1853 #define main0_actualSpeeds_dr_6G_X4 5 1854 #define main0_actualSpeeds_dr_10G_HiG 6 1855 #define main0_actualSpeeds_dr_10G_CX4 7 1856 #define main0_actualSpeeds_dr_12G_HiG 8 1857 #define main0_actualSpeeds_dr_12p5G_X4 9 1858 #define main0_actualSpeeds_dr_13G_X4 10 1859 #define main0_actualSpeeds_dr_15G_X4 11 1860 #define main0_actualSpeeds_dr_16G_X4 12 1861 #define main0_actualSpeeds_dr_1G_KX 13 1862 #define main0_actualSpeeds_dr_10G_KX4 14 1863 #define main0_actualSpeeds_dr_10G_KR 15 1864 #define main0_actualSpeeds_dr_5G 16 1865 #define main0_actualSpeeds_dr_6p4G 17 1866 #define main0_actualSpeeds_dr_20G_X4 18 1867 #define main0_actualSpeeds_dr_21G_X4 19 1868 #define main0_actualSpeeds_dr_25G_X4 20 1869 #define main0_actualSpeeds_dr_10G_HiG_DXGXS 21 1870 #define main0_actualSpeeds_dr_10G_DXGXS 22 1871 #define main0_actualSpeeds_dr_10p5G_HiG_DXGXS 23 1872 #define main0_actualSpeeds_dr_10p5G_DXGXS 24 1873 #define main0_actualSpeeds_dr_12p773G_HiG_DXGXS 25 1874 #define main0_actualSpeeds_dr_12p773G_DXGXS 26 1875 #define main0_actualSpeeds_dr_10G_XFI 27 1876 #define main0_actualSpeeds_dr_40G 28 1877 #define main0_actualSpeeds_dr_20G_HiG_DXGXS 29 1878 #define main0_actualSpeeds_dr_20G_DXGXS 30 1879 #define main0_actualSpeeds_dr_10G_SFI 31 1880 #define main0_actualSpeeds_dr_31p5G 32 1881 #define main0_actualSpeeds_dr_32p7G 33 1882 #define main0_actualSpeeds_dr_20G_SCR 34 1883 #define main0_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 1884 #define main0_actualSpeeds_dr_10G_DXGXS_SCR 36 1885 #define main0_actualSpeeds_dr_12G_R2 37 1886 #define main0_actualSpeeds_dr_10G_X2 38 1887 #define main0_actualSpeeds_dr_40G_KR4 39 1888 #define main0_actualSpeeds_dr_40G_CR4 40 1889 #define main0_actualSpeeds_dr_100G_CR10 41 1890 #define main0_actualSpeeds_dr_15p75G_DXGXS 44 1891 #define main0_actualSpeeds_dr_20G_KR2 57 1892 #define main0_actualSpeeds_dr_20G_CR2 58 1893 1894 /**************************************************************************** 1895 * Enums: main0_actualSpeedsMisc1 1896 */ 1897 #define main0_actualSpeedsMisc1_dr_2500BRCM_X1 16 1898 #define main0_actualSpeedsMisc1_dr_5000BRCM_X4 17 1899 #define main0_actualSpeedsMisc1_dr_6000BRCM_X4 18 1900 #define main0_actualSpeedsMisc1_dr_10GHiGig_X4 19 1901 #define main0_actualSpeedsMisc1_dr_10GBASE_CX4 20 1902 #define main0_actualSpeedsMisc1_dr_12GHiGig_X4 21 1903 #define main0_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 1904 #define main0_actualSpeedsMisc1_dr_13GHiGig_X4 23 1905 #define main0_actualSpeedsMisc1_dr_15GHiGig_X4 24 1906 #define main0_actualSpeedsMisc1_dr_16GHiGig_X4 25 1907 #define main0_actualSpeedsMisc1_dr_5000BRCM_X1 26 1908 #define main0_actualSpeedsMisc1_dr_6363BRCM_X1 27 1909 #define main0_actualSpeedsMisc1_dr_20GHiGig_X4 28 1910 #define main0_actualSpeedsMisc1_dr_21GHiGig_X4 29 1911 #define main0_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 1912 #define main0_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 1913 1914 /**************************************************************************** 1915 * Enums: main0_IndLaneModes 1916 */ 1917 #define main0_IndLaneModes_SWSDR_div2 0 1918 #define main0_IndLaneModes_SWSDR_div1 1 1919 #define main0_IndLaneModes_DWSDR_div2 2 1920 #define main0_IndLaneModes_DWSDR_div1 3 1921 1922 /**************************************************************************** 1923 * Enums: main0_prbsSelect 1924 */ 1925 #define main0_prbsSelect_prbs7 0 1926 #define main0_prbsSelect_prbs15 1 1927 #define main0_prbsSelect_prbs23 2 1928 #define main0_prbsSelect_prbs31 3 1929 1930 /**************************************************************************** 1931 * Enums: main0_vcoDivider 1932 */ 1933 #define main0_vcoDivider_div32 0 1934 #define main0_vcoDivider_div36 1 1935 #define main0_vcoDivider_div40 2 1936 #define main0_vcoDivider_div42 3 1937 #define main0_vcoDivider_div48 4 1938 #define main0_vcoDivider_div50 5 1939 #define main0_vcoDivider_div52 6 1940 #define main0_vcoDivider_div54 7 1941 #define main0_vcoDivider_div60 8 1942 #define main0_vcoDivider_div64 9 1943 #define main0_vcoDivider_div66 10 1944 #define main0_vcoDivider_div68 11 1945 #define main0_vcoDivider_div70 12 1946 #define main0_vcoDivider_div80 13 1947 #define main0_vcoDivider_div92 14 1948 #define main0_vcoDivider_div100 15 1949 1950 /**************************************************************************** 1951 * Enums: main0_refClkSelect 1952 */ 1953 #define main0_refClkSelect_clk_25MHz 0 1954 #define main0_refClkSelect_clk_100MHz 1 1955 #define main0_refClkSelect_clk_125MHz 2 1956 #define main0_refClkSelect_clk_156p25MHz 3 1957 #define main0_refClkSelect_clk_187p5MHz 4 1958 #define main0_refClkSelect_clk_161p25Mhz 5 1959 #define main0_refClkSelect_clk_50Mhz 6 1960 #define main0_refClkSelect_clk_106p25Mhz 7 1961 1962 /**************************************************************************** 1963 * Enums: main0_aerMMDdevTypeSelect 1964 */ 1965 #define main0_aerMMDdevTypeSelect_combo_core 0 1966 #define main0_aerMMDdevTypeSelect_PMA_PMD 1 1967 #define main0_aerMMDdevTypeSelect_PCS 3 1968 #define main0_aerMMDdevTypeSelect_PHY 4 1969 #define main0_aerMMDdevTypeSelect_DTE 5 1970 #define main0_aerMMDdevTypeSelect_CL73_AN 7 1971 1972 /**************************************************************************** 1973 * Enums: main0_aerMMDportSelect 1974 */ 1975 #define main0_aerMMDportSelect_ln0 0 1976 #define main0_aerMMDportSelect_ln1 1 1977 #define main0_aerMMDportSelect_ln2 2 1978 #define main0_aerMMDportSelect_ln3 3 1979 #define main0_aerMMDportSelect_BCST_ln0_1_2_3 511 1980 #define main0_aerMMDportSelect_BCST_ln0_1 512 1981 #define main0_aerMMDportSelect_BCST_ln2_3 513 1982 1983 /**************************************************************************** 1984 * Enums: main0_firmwareModeSelect 1985 */ 1986 #define main0_firmwareModeSelect_DEFAULT 0 1987 #define main0_firmwareModeSelect_SFP_OPT_LR 1 1988 #define main0_firmwareModeSelect_SFP_DAC 2 1989 #define main0_firmwareModeSelect_XLAUI 3 1990 #define main0_firmwareModeSelect_LONG_CH_6G 4 1991 1992 /**************************************************************************** 1993 * Enums: main0_tempIdxSelect 1994 */ 1995 #define main0_tempIdxSelect_LTE__22p9C 15 1996 #define main0_tempIdxSelect_LTE__12p6C 14 1997 #define main0_tempIdxSelect_LTE__3p0C 13 1998 #define main0_tempIdxSelect_LTE_6p7C 12 1999 #define main0_tempIdxSelect_LTE_16p4C 11 2000 #define main0_tempIdxSelect_LTE_26p6C 10 2001 #define main0_tempIdxSelect_LTE_36p3C 9 2002 #define main0_tempIdxSelect_LTE_46p0C 8 2003 #define main0_tempIdxSelect_LTE_56p2C 7 2004 #define main0_tempIdxSelect_LTE_65p9C 6 2005 #define main0_tempIdxSelect_LTE_75p6C 5 2006 #define main0_tempIdxSelect_LTE_85p3C 4 2007 #define main0_tempIdxSelect_LTE_95p5C 3 2008 #define main0_tempIdxSelect_LTE_105p2C 2 2009 #define main0_tempIdxSelect_LTE_114p9C 1 2010 #define main0_tempIdxSelect_LTE_125p1C 0 2011 2012 /**************************************************************************** 2013 * Enums: main0_port_mode 2014 */ 2015 #define main0_port_mode_QUAD_PORT 0 2016 #define main0_port_mode_TRI_1_PORT 1 2017 #define main0_port_mode_TRI_2_PORT 2 2018 #define main0_port_mode_DUAL_PORT 3 2019 #define main0_port_mode_SINGLE_PORT 4 2020 2021 /**************************************************************************** 2022 * Enums: main0_rev_letter_enum 2023 */ 2024 #define main0_rev_letter_enum_REV_A 0 2025 #define main0_rev_letter_enum_REV_B 1 2026 #define main0_rev_letter_enum_REV_C 2 2027 #define main0_rev_letter_enum_REV_D 3 2028 2029 /**************************************************************************** 2030 * Enums: main0_rev_number_enum 2031 */ 2032 #define main0_rev_number_enum_REV_0 0 2033 #define main0_rev_number_enum_REV_1 1 2034 #define main0_rev_number_enum_REV_2 2 2035 #define main0_rev_number_enum_REV_3 3 2036 #define main0_rev_number_enum_REV_4 4 2037 #define main0_rev_number_enum_REV_5 5 2038 #define main0_rev_number_enum_REV_6 6 2039 #define main0_rev_number_enum_REV_7 7 2040 2041 /**************************************************************************** 2042 * Enums: main0_bonding_enum 2043 */ 2044 #define main0_bonding_enum_WIRE_BOND 0 2045 #define main0_bonding_enum_FLIP_CHIP 1 2046 2047 /**************************************************************************** 2048 * Enums: main0_tech_process 2049 */ 2050 #define main0_tech_process_PROCESS_90NM 0 2051 #define main0_tech_process_PROCESS_65NM 1 2052 #define main0_tech_process_PROCESS_40NM 2 2053 #define main0_tech_process_PROCESS_28NM 3 2054 2055 /**************************************************************************** 2056 * Enums: main0_model_num 2057 */ 2058 #define main0_model_num_SERDES_CL73 0 2059 #define main0_model_num_XGXS_16G 1 2060 #define main0_model_num_HYPERCORE 2 2061 #define main0_model_num_HYPERLITE 3 2062 #define main0_model_num_PCIE_G2_PIPE 4 2063 #define main0_model_num_SERDES_1p25GBd 5 2064 #define main0_model_num_SATA2 6 2065 #define main0_model_num_QSGMII 7 2066 #define main0_model_num_XGXS10G 8 2067 #define main0_model_num_WARPCORE 9 2068 #define main0_model_num_XFICORE 10 2069 #define main0_model_num_RXFI 11 2070 #define main0_model_num_WARPLITE 12 2071 #define main0_model_num_PENTACORE 13 2072 #define main0_model_num_ESM 14 2073 #define main0_model_num_QUAD_SGMII 15 2074 #define main0_model_num_WARPCORE_3 16 2075 #define main0_model_num_TSC 17 2076 #define main0_model_num_TSC4E 18 2077 #define main0_model_num_TSC12E 19 2078 #define main0_model_num_TSC4F 20 2079 #define main0_model_num_XGXS_CL73_90NM 29 2080 #define main0_model_num_SERDES_CL73_90NM 30 2081 #define main0_model_num_WARPCORE3 32 2082 #define main0_model_num_WARPCORE4_TSC 33 2083 #define main0_model_num_RXAUI 34 2084 2085 /**************************************************************************** 2086 * Enums: main0_payload 2087 */ 2088 #define main0_payload_REPEAT_2_BYTES 0 2089 #define main0_payload_RAMPING 1 2090 #define main0_payload_CL48_CRPAT 2 2091 #define main0_payload_CL48_CJPAT 3 2092 #define main0_payload_CL36_LONG_CRPAT 4 2093 #define main0_payload_CL36_SHORT_CRPAT 5 2094 2095 /**************************************************************************** 2096 * Enums: main0_sc 2097 */ 2098 #define main0_sc_S_10G_CR1 0 2099 #define main0_sc_S_10G_KR1 1 2100 #define main0_sc_S_10G_X1 2 2101 #define main0_sc_S_10G_HG2_CR1 4 2102 #define main0_sc_S_10G_HG2_KR1 5 2103 #define main0_sc_S_10G_HG2_X1 6 2104 #define main0_sc_S_20G_CR1 8 2105 #define main0_sc_S_20G_KR1 9 2106 #define main0_sc_S_20G_X1 10 2107 #define main0_sc_S_20G_HG2_CR1 12 2108 #define main0_sc_S_20G_HG2_KR1 13 2109 #define main0_sc_S_20G_HG2_X1 14 2110 #define main0_sc_S_25G_CR1 16 2111 #define main0_sc_S_25G_KR1 17 2112 #define main0_sc_S_25G_X1 18 2113 #define main0_sc_S_25G_HG2_CR1 20 2114 #define main0_sc_S_25G_HG2_KR1 21 2115 #define main0_sc_S_25G_HG2_X1 22 2116 #define main0_sc_S_20G_CR2 24 2117 #define main0_sc_S_20G_KR2 25 2118 #define main0_sc_S_20G_X2 26 2119 #define main0_sc_S_20G_HG2_CR2 28 2120 #define main0_sc_S_20G_HG2_KR2 29 2121 #define main0_sc_S_20G_HG2_X2 30 2122 #define main0_sc_S_40G_CR2 32 2123 #define main0_sc_S_40G_KR2 33 2124 #define main0_sc_S_40G_X2 34 2125 #define main0_sc_S_40G_HG2_CR2 36 2126 #define main0_sc_S_40G_HG2_KR2 37 2127 #define main0_sc_S_40G_HG2_X2 38 2128 #define main0_sc_S_40G_CR4 40 2129 #define main0_sc_S_40G_KR4 41 2130 #define main0_sc_S_40G_X4 42 2131 #define main0_sc_S_40G_HG2_CR4 44 2132 #define main0_sc_S_40G_HG2_KR4 45 2133 #define main0_sc_S_40G_HG2_X4 46 2134 #define main0_sc_S_50G_CR2 48 2135 #define main0_sc_S_50G_KR2 49 2136 #define main0_sc_S_50G_X2 50 2137 #define main0_sc_S_50G_HG2_CR2 52 2138 #define main0_sc_S_50G_HG2_KR2 53 2139 #define main0_sc_S_50G_HG2_X2 54 2140 #define main0_sc_S_50G_CR4 56 2141 #define main0_sc_S_50G_KR4 57 2142 #define main0_sc_S_50G_X4 58 2143 #define main0_sc_S_50G_HG2_CR4 60 2144 #define main0_sc_S_50G_HG2_KR4 61 2145 #define main0_sc_S_50G_HG2_X4 62 2146 #define main0_sc_S_100G_CR4 64 2147 #define main0_sc_S_100G_KR4 65 2148 #define main0_sc_S_100G_X4 66 2149 #define main0_sc_S_100G_HG2_CR4 68 2150 #define main0_sc_S_100G_HG2_KR4 69 2151 #define main0_sc_S_100G_HG2_X4 70 2152 #define main0_sc_S_CL73_20GVCO 72 2153 #define main0_sc_S_CL73_25GVCO 80 2154 #define main0_sc_S_CL36_20GVCO 88 2155 #define main0_sc_S_CL36_25GVCO 96 2156 2157 /**************************************************************************** 2158 * Enums: main0_t_fifo_modes 2159 */ 2160 #define main0_t_fifo_modes_T_FIFO_MODE_BYPASS 0 2161 #define main0_t_fifo_modes_T_FIFO_MODE_40G 1 2162 #define main0_t_fifo_modes_T_FIFO_MODE_100G 2 2163 #define main0_t_fifo_modes_T_FIFO_MODE_20G 3 2164 2165 /**************************************************************************** 2166 * Enums: main0_t_enc_modes 2167 */ 2168 #define main0_t_enc_modes_T_ENC_MODE_BYPASS 0 2169 #define main0_t_enc_modes_T_ENC_MODE_CL49 1 2170 #define main0_t_enc_modes_T_ENC_MODE_CL82 2 2171 2172 /**************************************************************************** 2173 * Enums: main0_btmx_mode 2174 */ 2175 #define main0_btmx_mode_BS_BTMX_MODE_1to1 0 2176 #define main0_btmx_mode_BS_BTMX_MODE_2to1 1 2177 #define main0_btmx_mode_BS_BTMX_MODE_5to1 2 2178 2179 /**************************************************************************** 2180 * Enums: main0_t_type_cl82 2181 */ 2182 #define main0_t_type_cl82_T_TYPE_B1 5 2183 #define main0_t_type_cl82_T_TYPE_C 4 2184 #define main0_t_type_cl82_T_TYPE_S 3 2185 #define main0_t_type_cl82_T_TYPE_T 2 2186 #define main0_t_type_cl82_T_TYPE_D 1 2187 #define main0_t_type_cl82_T_TYPE_E 0 2188 2189 /**************************************************************************** 2190 * Enums: main0_txsm_state_cl82 2191 */ 2192 #define main0_txsm_state_cl82_TX_HIG_END 6 2193 #define main0_txsm_state_cl82_TX_HIG_START 5 2194 #define main0_txsm_state_cl82_TX_E 4 2195 #define main0_txsm_state_cl82_TX_T 3 2196 #define main0_txsm_state_cl82_TX_D 2 2197 #define main0_txsm_state_cl82_TX_C 1 2198 #define main0_txsm_state_cl82_TX_INIT 0 2199 2200 /**************************************************************************** 2201 * Enums: main0_ltxsm_state_cl82 2202 */ 2203 #define main0_ltxsm_state_cl82_TX_HIG_END 64 2204 #define main0_ltxsm_state_cl82_TX_HIG_START 32 2205 #define main0_ltxsm_state_cl82_TX_E 16 2206 #define main0_ltxsm_state_cl82_TX_T 8 2207 #define main0_ltxsm_state_cl82_TX_D 4 2208 #define main0_ltxsm_state_cl82_TX_C 2 2209 #define main0_ltxsm_state_cl82_TX_INIT 1 2210 2211 /**************************************************************************** 2212 * Enums: main0_r_type_coded_cl82 2213 */ 2214 #define main0_r_type_coded_cl82_R_TYPE_B1 32 2215 #define main0_r_type_coded_cl82_R_TYPE_C 16 2216 #define main0_r_type_coded_cl82_R_TYPE_S 8 2217 #define main0_r_type_coded_cl82_R_TYPE_T 4 2218 #define main0_r_type_coded_cl82_R_TYPE_D 2 2219 #define main0_r_type_coded_cl82_R_TYPE_E 1 2220 2221 /**************************************************************************** 2222 * Enums: main0_rxsm_state_cl82 2223 */ 2224 #define main0_rxsm_state_cl82_RX_HIG_END 64 2225 #define main0_rxsm_state_cl82_RX_HIG_START 32 2226 #define main0_rxsm_state_cl82_RX_E 16 2227 #define main0_rxsm_state_cl82_RX_T 8 2228 #define main0_rxsm_state_cl82_RX_D 4 2229 #define main0_rxsm_state_cl82_RX_C 2 2230 #define main0_rxsm_state_cl82_RX_INIT 1 2231 2232 /**************************************************************************** 2233 * Enums: main0_deskew_state 2234 */ 2235 #define main0_deskew_state_ALIGN_ACQUIRED 2 2236 #define main0_deskew_state_LOSS_OF_ALIGNMENT 1 2237 2238 /**************************************************************************** 2239 * Enums: main0_os_mode_enum 2240 */ 2241 #define main0_os_mode_enum_OS_MODE_1 0 2242 #define main0_os_mode_enum_OS_MODE_2 1 2243 #define main0_os_mode_enum_OS_MODE_4 2 2244 #define main0_os_mode_enum_OS_MODE_16p5 8 2245 #define main0_os_mode_enum_OS_MODE_20p625 12 2246 2247 /**************************************************************************** 2248 * Enums: main0_scr_modes 2249 */ 2250 #define main0_scr_modes_T_SCR_MODE_BYPASS 0 2251 #define main0_scr_modes_T_SCR_MODE_CL49 1 2252 #define main0_scr_modes_T_SCR_MODE_40G_2_LANE 2 2253 #define main0_scr_modes_T_SCR_MODE_100G 3 2254 #define main0_scr_modes_T_SCR_MODE_20G 4 2255 #define main0_scr_modes_T_SCR_MODE_40G_4_LANE 5 2256 2257 /**************************************************************************** 2258 * Enums: main0_descr_modes 2259 */ 2260 #define main0_descr_modes_R_DESCR_MODE_BYPASS 0 2261 #define main0_descr_modes_R_DESCR_MODE_CL49 1 2262 #define main0_descr_modes_R_DESCR_MODE_CL82 2 2263 2264 /**************************************************************************** 2265 * Enums: main0_r_dec_tl_mode 2266 */ 2267 #define main0_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 2268 #define main0_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 2269 #define main0_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 2270 2271 /**************************************************************************** 2272 * Enums: main0_r_dec_fsm_mode 2273 */ 2274 #define main0_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 2275 #define main0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 2276 #define main0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 2277 2278 /**************************************************************************** 2279 * Enums: main0_r_deskew_mode 2280 */ 2281 #define main0_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 2282 #define main0_r_deskew_mode_R_DESKEW_MODE_20G 1 2283 #define main0_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 2284 #define main0_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 2285 #define main0_r_deskew_mode_R_DESKEW_MODE_100G 4 2286 #define main0_r_deskew_mode_R_DESKEW_MODE_CL49 5 2287 #define main0_r_deskew_mode_R_DESKEW_MODE_CL91 6 2288 2289 /**************************************************************************** 2290 * Enums: main0_bs_dist_modes 2291 */ 2292 #define main0_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 2293 #define main0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 2294 #define main0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 2295 #define main0_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 2296 2297 /**************************************************************************** 2298 * Enums: main0_cl49_t_type 2299 */ 2300 #define main0_cl49_t_type_BAD_T_TYPE 15 2301 #define main0_cl49_t_type_T_TYPE_B0 11 2302 #define main0_cl49_t_type_T_TYPE_OB 10 2303 #define main0_cl49_t_type_T_TYPE_B1 9 2304 #define main0_cl49_t_type_T_TYPE_DB 8 2305 #define main0_cl49_t_type_T_TYPE_FC 7 2306 #define main0_cl49_t_type_T_TYPE_TB 6 2307 #define main0_cl49_t_type_T_TYPE_LI 5 2308 #define main0_cl49_t_type_T_TYPE_C 4 2309 #define main0_cl49_t_type_T_TYPE_S 3 2310 #define main0_cl49_t_type_T_TYPE_T 2 2311 #define main0_cl49_t_type_T_TYPE_D 1 2312 #define main0_cl49_t_type_T_TYPE_E 0 2313 2314 /**************************************************************************** 2315 * Enums: main0_cl49_txsm_states 2316 */ 2317 #define main0_cl49_txsm_states_TX_HIG_END 7 2318 #define main0_cl49_txsm_states_TX_HIG_START 6 2319 #define main0_cl49_txsm_states_TX_LI 5 2320 #define main0_cl49_txsm_states_TX_E 4 2321 #define main0_cl49_txsm_states_TX_T 3 2322 #define main0_cl49_txsm_states_TX_D 2 2323 #define main0_cl49_txsm_states_TX_C 1 2324 #define main0_cl49_txsm_states_TX_INIT 0 2325 2326 /**************************************************************************** 2327 * Enums: main0_cl49_ltxsm_states 2328 */ 2329 #define main0_cl49_ltxsm_states_TX_HIG_END 128 2330 #define main0_cl49_ltxsm_states_TX_HIG_START 64 2331 #define main0_cl49_ltxsm_states_TX_LI 32 2332 #define main0_cl49_ltxsm_states_TX_E 16 2333 #define main0_cl49_ltxsm_states_TX_T 8 2334 #define main0_cl49_ltxsm_states_TX_D 4 2335 #define main0_cl49_ltxsm_states_TX_C 2 2336 #define main0_cl49_ltxsm_states_TX_INIT 1 2337 2338 /**************************************************************************** 2339 * Enums: main0_burst_error_mode 2340 */ 2341 #define main0_burst_error_mode_BURST_ERROR_11_BITS 0 2342 #define main0_burst_error_mode_BURST_ERROR_16_BITS 1 2343 #define main0_burst_error_mode_BURST_ERROR_17_BITS 2 2344 #define main0_burst_error_mode_BURST_ERROR_18_BITS 3 2345 #define main0_burst_error_mode_BURST_ERROR_19_BITS 4 2346 #define main0_burst_error_mode_BURST_ERROR_20_BITS 5 2347 #define main0_burst_error_mode_BURST_ERROR_21_BITS 6 2348 #define main0_burst_error_mode_BURST_ERROR_22_BITS 7 2349 #define main0_burst_error_mode_BURST_ERROR_23_BITS 8 2350 #define main0_burst_error_mode_BURST_ERROR_24_BITS 9 2351 #define main0_burst_error_mode_BURST_ERROR_25_BITS 10 2352 #define main0_burst_error_mode_BURST_ERROR_26_BITS 11 2353 #define main0_burst_error_mode_BURST_ERROR_27_BITS 12 2354 #define main0_burst_error_mode_BURST_ERROR_28_BITS 13 2355 #define main0_burst_error_mode_BURST_ERROR_29_BITS 14 2356 #define main0_burst_error_mode_BURST_ERROR_30_BITS 15 2357 #define main0_burst_error_mode_BURST_ERROR_31_BITS 16 2358 #define main0_burst_error_mode_BURST_ERROR_32_BITS 17 2359 #define main0_burst_error_mode_BURST_ERROR_33_BITS 18 2360 #define main0_burst_error_mode_BURST_ERROR_34_BITS 19 2361 #define main0_burst_error_mode_BURST_ERROR_35_BITS 20 2362 #define main0_burst_error_mode_BURST_ERROR_36_BITS 21 2363 #define main0_burst_error_mode_BURST_ERROR_37_BITS 22 2364 #define main0_burst_error_mode_BURST_ERROR_38_BITS 23 2365 #define main0_burst_error_mode_BURST_ERROR_39_BITS 24 2366 #define main0_burst_error_mode_BURST_ERROR_40_BITS 25 2367 #define main0_burst_error_mode_BURST_ERROR_41_BITS 26 2368 2369 /**************************************************************************** 2370 * Enums: main0_bermon_state 2371 */ 2372 #define main0_bermon_state_HI_BER 4 2373 #define main0_bermon_state_GOOD_BER 3 2374 #define main0_bermon_state_BER_TEST_SH 2 2375 #define main0_bermon_state_START_TIMER 1 2376 #define main0_bermon_state_BER_MT_INIT 0 2377 2378 /**************************************************************************** 2379 * Enums: main0_rxsm_state_cl49 2380 */ 2381 #define main0_rxsm_state_cl49_RX_HIG_END 128 2382 #define main0_rxsm_state_cl49_RX_HIG_START 64 2383 #define main0_rxsm_state_cl49_RX_LI 32 2384 #define main0_rxsm_state_cl49_RX_E 16 2385 #define main0_rxsm_state_cl49_RX_T 8 2386 #define main0_rxsm_state_cl49_RX_D 4 2387 #define main0_rxsm_state_cl49_RX_C 2 2388 #define main0_rxsm_state_cl49_RX_INIT 1 2389 2390 /**************************************************************************** 2391 * Enums: main0_r_type 2392 */ 2393 #define main0_r_type_BAD_R_TYPE 15 2394 #define main0_r_type_R_TYPE_B0 11 2395 #define main0_r_type_R_TYPE_OB 10 2396 #define main0_r_type_R_TYPE_B1 9 2397 #define main0_r_type_R_TYPE_DB 8 2398 #define main0_r_type_R_TYPE_FC 7 2399 #define main0_r_type_R_TYPE_TB 6 2400 #define main0_r_type_R_TYPE_LI 5 2401 #define main0_r_type_R_TYPE_C 4 2402 #define main0_r_type_R_TYPE_S 3 2403 #define main0_r_type_R_TYPE_T 2 2404 #define main0_r_type_R_TYPE_D 1 2405 #define main0_r_type_R_TYPE_E 0 2406 2407 /**************************************************************************** 2408 * Enums: main0_am_lock_state 2409 */ 2410 #define main0_am_lock_state_INVALID_AM 512 2411 #define main0_am_lock_state_GOOD_AM 256 2412 #define main0_am_lock_state_COMP_AM 128 2413 #define main0_am_lock_state_TIMER_2 64 2414 #define main0_am_lock_state_AM_2_GOOD 32 2415 #define main0_am_lock_state_COMP_2ND 16 2416 #define main0_am_lock_state_TIMER_1 8 2417 #define main0_am_lock_state_FIND_1ST 4 2418 #define main0_am_lock_state_AM_RESET_CNT 2 2419 #define main0_am_lock_state_AM_LOCK_INIT 1 2420 2421 /**************************************************************************** 2422 * Enums: main0_msg_selector 2423 */ 2424 #define main0_msg_selector_RESERVED 0 2425 #define main0_msg_selector_VALUE_802p3 1 2426 #define main0_msg_selector_VALUE_802p9 2 2427 #define main0_msg_selector_VALUE_802p5 3 2428 #define main0_msg_selector_VALUE_1394 4 2429 2430 /**************************************************************************** 2431 * Enums: main0_synce_enum 2432 */ 2433 #define main0_synce_enum_SYNCE_NO_DIV 0 2434 #define main0_synce_enum_SYNCE_DIV_7 1 2435 #define main0_synce_enum_SYNCE_DIV_11 2 2436 2437 /**************************************************************************** 2438 * Enums: main0_synce_enum_stage0 2439 */ 2440 #define main0_synce_enum_stage0_SYNCE_NO_DIV 0 2441 #define main0_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 2442 #define main0_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 2443 2444 /**************************************************************************** 2445 * Enums: main0_cl91_sync_state 2446 */ 2447 #define main0_cl91_sync_state_FIND_1ST 0 2448 #define main0_cl91_sync_state_COUNT_NEXT 1 2449 #define main0_cl91_sync_state_COMP_2ND 2 2450 #define main0_cl91_sync_state_TWO_GOOD 3 2451 2452 /**************************************************************************** 2453 * Enums: main0_cl91_algn_state 2454 */ 2455 #define main0_cl91_algn_state_LOSS_OF_ALIGNMENT 0 2456 #define main0_cl91_algn_state_DESKEW 1 2457 #define main0_cl91_algn_state_DESKEW_FAIL 2 2458 #define main0_cl91_algn_state_ALIGN_ACQUIRED 3 2459 #define main0_cl91_algn_state_CW_GOOD 4 2460 #define main0_cl91_algn_state_CW_BAD 5 2461 #define main0_cl91_algn_state_THREE_BAD 6 2462 2463 /**************************************************************************** 2464 * Enums: main0_fec_sel 2465 */ 2466 #define main0_fec_sel_NO_FEC 0 2467 #define main0_fec_sel_FEC_CL74 1 2468 #define main0_fec_sel_FEC_CL91 2 2469 2470 /**************************************************************************** 2471 * Enums: rx_x1_status0_cl36TxEEEStates_l 2472 */ 2473 #define rx_x1_status0_cl36TxEEEStates_l_TX_REFRESH 8 2474 #define rx_x1_status0_cl36TxEEEStates_l_TX_QUIET 4 2475 #define rx_x1_status0_cl36TxEEEStates_l_TX_SLEEP 2 2476 #define rx_x1_status0_cl36TxEEEStates_l_TX_ACTIVE 1 2477 2478 /**************************************************************************** 2479 * Enums: rx_x1_status0_cl36TxEEEStates_c 2480 */ 2481 #define rx_x1_status0_cl36TxEEEStates_c_TX_REFRESH 3 2482 #define rx_x1_status0_cl36TxEEEStates_c_TX_QUIET 2 2483 #define rx_x1_status0_cl36TxEEEStates_c_TX_SLEEP 1 2484 #define rx_x1_status0_cl36TxEEEStates_c_TX_ACTIVE 0 2485 2486 /**************************************************************************** 2487 * Enums: rx_x1_status0_cl49TxEEEStates_l 2488 */ 2489 #define rx_x1_status0_cl49TxEEEStates_l_SCR_RESET_2 64 2490 #define rx_x1_status0_cl49TxEEEStates_l_SCR_RESET_1 32 2491 #define rx_x1_status0_cl49TxEEEStates_l_TX_WAKE 16 2492 #define rx_x1_status0_cl49TxEEEStates_l_TX_REFRESH 8 2493 #define rx_x1_status0_cl49TxEEEStates_l_TX_QUIET 4 2494 #define rx_x1_status0_cl49TxEEEStates_l_TX_SLEEP 2 2495 #define rx_x1_status0_cl49TxEEEStates_l_TX_ACTIVE 1 2496 2497 /**************************************************************************** 2498 * Enums: rx_x1_status0_fec_req_enum 2499 */ 2500 #define rx_x1_status0_fec_req_enum_FEC_not_supported 0 2501 #define rx_x1_status0_fec_req_enum_FEC_supported_but_not_requested 1 2502 #define rx_x1_status0_fec_req_enum_invalid_setting 2 2503 #define rx_x1_status0_fec_req_enum_FEC_supported_and_requested 3 2504 2505 /**************************************************************************** 2506 * Enums: rx_x1_status0_cl73_pause_enum 2507 */ 2508 #define rx_x1_status0_cl73_pause_enum_No_PAUSE_ability 0 2509 #define rx_x1_status0_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 2510 #define rx_x1_status0_cl73_pause_enum_Symmetric_PAUSE_ability 1 2511 #define rx_x1_status0_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 2512 2513 /**************************************************************************** 2514 * Enums: rx_x1_status0_cl49TxEEEStates_c 2515 */ 2516 #define rx_x1_status0_cl49TxEEEStates_c_SCR_RESET_2 6 2517 #define rx_x1_status0_cl49TxEEEStates_c_SCR_RESET_1 5 2518 #define rx_x1_status0_cl49TxEEEStates_c_TX_WAKE 4 2519 #define rx_x1_status0_cl49TxEEEStates_c_TX_REFRESH 3 2520 #define rx_x1_status0_cl49TxEEEStates_c_TX_QUIET 2 2521 #define rx_x1_status0_cl49TxEEEStates_c_TX_SLEEP 1 2522 #define rx_x1_status0_cl49TxEEEStates_c_TX_ACTIVE 0 2523 2524 /**************************************************************************** 2525 * Enums: rx_x1_status0_cl36RxEEEStates_l 2526 */ 2527 #define rx_x1_status0_cl36RxEEEStates_l_RX_LINK_FAIL 32 2528 #define rx_x1_status0_cl36RxEEEStates_l_RX_WTF 16 2529 #define rx_x1_status0_cl36RxEEEStates_l_RX_WAKE 8 2530 #define rx_x1_status0_cl36RxEEEStates_l_RX_QUIET 4 2531 #define rx_x1_status0_cl36RxEEEStates_l_RX_SLEEP 2 2532 #define rx_x1_status0_cl36RxEEEStates_l_RX_ACTIVE 1 2533 2534 /**************************************************************************** 2535 * Enums: rx_x1_status0_cl36RxEEEStates_c 2536 */ 2537 #define rx_x1_status0_cl36RxEEEStates_c_RX_LINK_FAIL 5 2538 #define rx_x1_status0_cl36RxEEEStates_c_RX_WTF 4 2539 #define rx_x1_status0_cl36RxEEEStates_c_RX_WAKE 3 2540 #define rx_x1_status0_cl36RxEEEStates_c_RX_QUIET 2 2541 #define rx_x1_status0_cl36RxEEEStates_c_RX_SLEEP 1 2542 #define rx_x1_status0_cl36RxEEEStates_c_RX_ACTIVE 0 2543 2544 /**************************************************************************** 2545 * Enums: rx_x1_status0_cl49RxEEEStates_l 2546 */ 2547 #define rx_x1_status0_cl49RxEEEStates_l_RX_LINK_FAIL 32 2548 #define rx_x1_status0_cl49RxEEEStates_l_RX_WTF 16 2549 #define rx_x1_status0_cl49RxEEEStates_l_RX_WAKE 8 2550 #define rx_x1_status0_cl49RxEEEStates_l_RX_QUIET 4 2551 #define rx_x1_status0_cl49RxEEEStates_l_RX_SLEEP 2 2552 #define rx_x1_status0_cl49RxEEEStates_l_RX_ACTIVE 1 2553 2554 /**************************************************************************** 2555 * Enums: rx_x1_status0_cl49RxEEEStates_c 2556 */ 2557 #define rx_x1_status0_cl49RxEEEStates_c_RX_LINK_FAIL 5 2558 #define rx_x1_status0_cl49RxEEEStates_c_RX_WTF 4 2559 #define rx_x1_status0_cl49RxEEEStates_c_RX_WAKE 3 2560 #define rx_x1_status0_cl49RxEEEStates_c_RX_QUIET 2 2561 #define rx_x1_status0_cl49RxEEEStates_c_RX_SLEEP 1 2562 #define rx_x1_status0_cl49RxEEEStates_c_RX_ACTIVE 0 2563 2564 /**************************************************************************** 2565 * Enums: rx_x1_status0_cl48TxEEEStates_l 2566 */ 2567 #define rx_x1_status0_cl48TxEEEStates_l_TX_REFRESH 8 2568 #define rx_x1_status0_cl48TxEEEStates_l_TX_QUIET 4 2569 #define rx_x1_status0_cl48TxEEEStates_l_TX_SLEEP 2 2570 #define rx_x1_status0_cl48TxEEEStates_l_TX_ACTIVE 1 2571 2572 /**************************************************************************** 2573 * Enums: rx_x1_status0_cl48TxEEEStates_c 2574 */ 2575 #define rx_x1_status0_cl48TxEEEStates_c_TX_REFRESH 3 2576 #define rx_x1_status0_cl48TxEEEStates_c_TX_QUIET 2 2577 #define rx_x1_status0_cl48TxEEEStates_c_TX_SLEEP 1 2578 #define rx_x1_status0_cl48TxEEEStates_c_TX_ACTIVE 0 2579 2580 /**************************************************************************** 2581 * Enums: rx_x1_status0_cl48RxEEEStates_l 2582 */ 2583 #define rx_x1_status0_cl48RxEEEStates_l_RX_LINK_FAIL 32 2584 #define rx_x1_status0_cl48RxEEEStates_l_RX_WAKE 16 2585 #define rx_x1_status0_cl48RxEEEStates_l_RX_QUIET 8 2586 #define rx_x1_status0_cl48RxEEEStates_l_RX_DEACT 4 2587 #define rx_x1_status0_cl48RxEEEStates_l_RX_SLEEP 2 2588 #define rx_x1_status0_cl48RxEEEStates_l_RX_ACTIVE 1 2589 2590 /**************************************************************************** 2591 * Enums: rx_x1_status0_cl48RxEEEStates_c 2592 */ 2593 #define rx_x1_status0_cl48RxEEEStates_c_RX_LINK_FAIL 5 2594 #define rx_x1_status0_cl48RxEEEStates_c_RX_WAKE 4 2595 #define rx_x1_status0_cl48RxEEEStates_c_RX_QUIET 3 2596 #define rx_x1_status0_cl48RxEEEStates_c_RX_DEACT 2 2597 #define rx_x1_status0_cl48RxEEEStates_c_RX_SLEEP 1 2598 #define rx_x1_status0_cl48RxEEEStates_c_RX_ACTIVE 0 2599 2600 /**************************************************************************** 2601 * Enums: rx_x1_status0_IQP_Options 2602 */ 2603 #define rx_x1_status0_IQP_Options_i50uA 0 2604 #define rx_x1_status0_IQP_Options_i100uA 1 2605 #define rx_x1_status0_IQP_Options_i150uA 2 2606 #define rx_x1_status0_IQP_Options_i200uA 3 2607 #define rx_x1_status0_IQP_Options_i250uA 4 2608 #define rx_x1_status0_IQP_Options_i300uA 5 2609 #define rx_x1_status0_IQP_Options_i350uA 6 2610 #define rx_x1_status0_IQP_Options_i400uA 7 2611 #define rx_x1_status0_IQP_Options_i450uA 8 2612 #define rx_x1_status0_IQP_Options_i500uA 9 2613 #define rx_x1_status0_IQP_Options_i550uA 10 2614 #define rx_x1_status0_IQP_Options_i600uA 11 2615 #define rx_x1_status0_IQP_Options_i650uA 12 2616 #define rx_x1_status0_IQP_Options_i700uA 13 2617 #define rx_x1_status0_IQP_Options_i750uA 14 2618 #define rx_x1_status0_IQP_Options_i800uA 15 2619 2620 /**************************************************************************** 2621 * Enums: rx_x1_status0_IDriver_Options 2622 */ 2623 #define rx_x1_status0_IDriver_Options_v680mV 0 2624 #define rx_x1_status0_IDriver_Options_v730mV 1 2625 #define rx_x1_status0_IDriver_Options_v780mV 2 2626 #define rx_x1_status0_IDriver_Options_v830mV 3 2627 #define rx_x1_status0_IDriver_Options_v880mV 4 2628 #define rx_x1_status0_IDriver_Options_v930mV 5 2629 #define rx_x1_status0_IDriver_Options_v980mV 6 2630 #define rx_x1_status0_IDriver_Options_v1010mV 7 2631 #define rx_x1_status0_IDriver_Options_v1040mV 8 2632 #define rx_x1_status0_IDriver_Options_v1060mV 9 2633 #define rx_x1_status0_IDriver_Options_v1070mV 10 2634 #define rx_x1_status0_IDriver_Options_v1080mV 11 2635 #define rx_x1_status0_IDriver_Options_v1085mV 12 2636 #define rx_x1_status0_IDriver_Options_v1090mV 13 2637 #define rx_x1_status0_IDriver_Options_v1095mV 14 2638 #define rx_x1_status0_IDriver_Options_v1100mV 15 2639 2640 /**************************************************************************** 2641 * Enums: rx_x1_status0_operationModes 2642 */ 2643 #define rx_x1_status0_operationModes_XGXS 0 2644 #define rx_x1_status0_operationModes_XGXG_nCC 1 2645 #define rx_x1_status0_operationModes_Indlane_OS8 4 2646 #define rx_x1_status0_operationModes_IndLane_OS5 5 2647 #define rx_x1_status0_operationModes_PCI 7 2648 #define rx_x1_status0_operationModes_XGXS_nLQ 8 2649 #define rx_x1_status0_operationModes_XGXS_nLQnCC 9 2650 #define rx_x1_status0_operationModes_PBypass 10 2651 #define rx_x1_status0_operationModes_PBypass_nDSK 11 2652 #define rx_x1_status0_operationModes_ComboCoreMode 12 2653 #define rx_x1_status0_operationModes_Clocks_off 15 2654 2655 /**************************************************************************** 2656 * Enums: rx_x1_status0_actualSpeeds 2657 */ 2658 #define rx_x1_status0_actualSpeeds_dr_10M 0 2659 #define rx_x1_status0_actualSpeeds_dr_100M 1 2660 #define rx_x1_status0_actualSpeeds_dr_1G 2 2661 #define rx_x1_status0_actualSpeeds_dr_2p5G 3 2662 #define rx_x1_status0_actualSpeeds_dr_5G_X4 4 2663 #define rx_x1_status0_actualSpeeds_dr_6G_X4 5 2664 #define rx_x1_status0_actualSpeeds_dr_10G_HiG 6 2665 #define rx_x1_status0_actualSpeeds_dr_10G_CX4 7 2666 #define rx_x1_status0_actualSpeeds_dr_12G_HiG 8 2667 #define rx_x1_status0_actualSpeeds_dr_12p5G_X4 9 2668 #define rx_x1_status0_actualSpeeds_dr_13G_X4 10 2669 #define rx_x1_status0_actualSpeeds_dr_15G_X4 11 2670 #define rx_x1_status0_actualSpeeds_dr_16G_X4 12 2671 #define rx_x1_status0_actualSpeeds_dr_1G_KX 13 2672 #define rx_x1_status0_actualSpeeds_dr_10G_KX4 14 2673 #define rx_x1_status0_actualSpeeds_dr_10G_KR 15 2674 #define rx_x1_status0_actualSpeeds_dr_5G 16 2675 #define rx_x1_status0_actualSpeeds_dr_6p4G 17 2676 #define rx_x1_status0_actualSpeeds_dr_20G_X4 18 2677 #define rx_x1_status0_actualSpeeds_dr_21G_X4 19 2678 #define rx_x1_status0_actualSpeeds_dr_25G_X4 20 2679 #define rx_x1_status0_actualSpeeds_dr_10G_HiG_DXGXS 21 2680 #define rx_x1_status0_actualSpeeds_dr_10G_DXGXS 22 2681 #define rx_x1_status0_actualSpeeds_dr_10p5G_HiG_DXGXS 23 2682 #define rx_x1_status0_actualSpeeds_dr_10p5G_DXGXS 24 2683 #define rx_x1_status0_actualSpeeds_dr_12p773G_HiG_DXGXS 25 2684 #define rx_x1_status0_actualSpeeds_dr_12p773G_DXGXS 26 2685 #define rx_x1_status0_actualSpeeds_dr_10G_XFI 27 2686 #define rx_x1_status0_actualSpeeds_dr_40G 28 2687 #define rx_x1_status0_actualSpeeds_dr_20G_HiG_DXGXS 29 2688 #define rx_x1_status0_actualSpeeds_dr_20G_DXGXS 30 2689 #define rx_x1_status0_actualSpeeds_dr_10G_SFI 31 2690 #define rx_x1_status0_actualSpeeds_dr_31p5G 32 2691 #define rx_x1_status0_actualSpeeds_dr_32p7G 33 2692 #define rx_x1_status0_actualSpeeds_dr_20G_SCR 34 2693 #define rx_x1_status0_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 2694 #define rx_x1_status0_actualSpeeds_dr_10G_DXGXS_SCR 36 2695 #define rx_x1_status0_actualSpeeds_dr_12G_R2 37 2696 #define rx_x1_status0_actualSpeeds_dr_10G_X2 38 2697 #define rx_x1_status0_actualSpeeds_dr_40G_KR4 39 2698 #define rx_x1_status0_actualSpeeds_dr_40G_CR4 40 2699 #define rx_x1_status0_actualSpeeds_dr_100G_CR10 41 2700 #define rx_x1_status0_actualSpeeds_dr_15p75G_DXGXS 44 2701 #define rx_x1_status0_actualSpeeds_dr_20G_KR2 57 2702 #define rx_x1_status0_actualSpeeds_dr_20G_CR2 58 2703 2704 /**************************************************************************** 2705 * Enums: rx_x1_status0_actualSpeedsMisc1 2706 */ 2707 #define rx_x1_status0_actualSpeedsMisc1_dr_2500BRCM_X1 16 2708 #define rx_x1_status0_actualSpeedsMisc1_dr_5000BRCM_X4 17 2709 #define rx_x1_status0_actualSpeedsMisc1_dr_6000BRCM_X4 18 2710 #define rx_x1_status0_actualSpeedsMisc1_dr_10GHiGig_X4 19 2711 #define rx_x1_status0_actualSpeedsMisc1_dr_10GBASE_CX4 20 2712 #define rx_x1_status0_actualSpeedsMisc1_dr_12GHiGig_X4 21 2713 #define rx_x1_status0_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 2714 #define rx_x1_status0_actualSpeedsMisc1_dr_13GHiGig_X4 23 2715 #define rx_x1_status0_actualSpeedsMisc1_dr_15GHiGig_X4 24 2716 #define rx_x1_status0_actualSpeedsMisc1_dr_16GHiGig_X4 25 2717 #define rx_x1_status0_actualSpeedsMisc1_dr_5000BRCM_X1 26 2718 #define rx_x1_status0_actualSpeedsMisc1_dr_6363BRCM_X1 27 2719 #define rx_x1_status0_actualSpeedsMisc1_dr_20GHiGig_X4 28 2720 #define rx_x1_status0_actualSpeedsMisc1_dr_21GHiGig_X4 29 2721 #define rx_x1_status0_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 2722 #define rx_x1_status0_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 2723 2724 /**************************************************************************** 2725 * Enums: rx_x1_status0_IndLaneModes 2726 */ 2727 #define rx_x1_status0_IndLaneModes_SWSDR_div2 0 2728 #define rx_x1_status0_IndLaneModes_SWSDR_div1 1 2729 #define rx_x1_status0_IndLaneModes_DWSDR_div2 2 2730 #define rx_x1_status0_IndLaneModes_DWSDR_div1 3 2731 2732 /**************************************************************************** 2733 * Enums: rx_x1_status0_prbsSelect 2734 */ 2735 #define rx_x1_status0_prbsSelect_prbs7 0 2736 #define rx_x1_status0_prbsSelect_prbs15 1 2737 #define rx_x1_status0_prbsSelect_prbs23 2 2738 #define rx_x1_status0_prbsSelect_prbs31 3 2739 2740 /**************************************************************************** 2741 * Enums: rx_x1_status0_vcoDivider 2742 */ 2743 #define rx_x1_status0_vcoDivider_div32 0 2744 #define rx_x1_status0_vcoDivider_div36 1 2745 #define rx_x1_status0_vcoDivider_div40 2 2746 #define rx_x1_status0_vcoDivider_div42 3 2747 #define rx_x1_status0_vcoDivider_div48 4 2748 #define rx_x1_status0_vcoDivider_div50 5 2749 #define rx_x1_status0_vcoDivider_div52 6 2750 #define rx_x1_status0_vcoDivider_div54 7 2751 #define rx_x1_status0_vcoDivider_div60 8 2752 #define rx_x1_status0_vcoDivider_div64 9 2753 #define rx_x1_status0_vcoDivider_div66 10 2754 #define rx_x1_status0_vcoDivider_div68 11 2755 #define rx_x1_status0_vcoDivider_div70 12 2756 #define rx_x1_status0_vcoDivider_div80 13 2757 #define rx_x1_status0_vcoDivider_div92 14 2758 #define rx_x1_status0_vcoDivider_div100 15 2759 2760 /**************************************************************************** 2761 * Enums: rx_x1_status0_refClkSelect 2762 */ 2763 #define rx_x1_status0_refClkSelect_clk_25MHz 0 2764 #define rx_x1_status0_refClkSelect_clk_100MHz 1 2765 #define rx_x1_status0_refClkSelect_clk_125MHz 2 2766 #define rx_x1_status0_refClkSelect_clk_156p25MHz 3 2767 #define rx_x1_status0_refClkSelect_clk_187p5MHz 4 2768 #define rx_x1_status0_refClkSelect_clk_161p25Mhz 5 2769 #define rx_x1_status0_refClkSelect_clk_50Mhz 6 2770 #define rx_x1_status0_refClkSelect_clk_106p25Mhz 7 2771 2772 /**************************************************************************** 2773 * Enums: rx_x1_status0_aerMMDdevTypeSelect 2774 */ 2775 #define rx_x1_status0_aerMMDdevTypeSelect_combo_core 0 2776 #define rx_x1_status0_aerMMDdevTypeSelect_PMA_PMD 1 2777 #define rx_x1_status0_aerMMDdevTypeSelect_PCS 3 2778 #define rx_x1_status0_aerMMDdevTypeSelect_PHY 4 2779 #define rx_x1_status0_aerMMDdevTypeSelect_DTE 5 2780 #define rx_x1_status0_aerMMDdevTypeSelect_CL73_AN 7 2781 2782 /**************************************************************************** 2783 * Enums: rx_x1_status0_aerMMDportSelect 2784 */ 2785 #define rx_x1_status0_aerMMDportSelect_ln0 0 2786 #define rx_x1_status0_aerMMDportSelect_ln1 1 2787 #define rx_x1_status0_aerMMDportSelect_ln2 2 2788 #define rx_x1_status0_aerMMDportSelect_ln3 3 2789 #define rx_x1_status0_aerMMDportSelect_BCST_ln0_1_2_3 511 2790 #define rx_x1_status0_aerMMDportSelect_BCST_ln0_1 512 2791 #define rx_x1_status0_aerMMDportSelect_BCST_ln2_3 513 2792 2793 /**************************************************************************** 2794 * Enums: rx_x1_status0_firmwareModeSelect 2795 */ 2796 #define rx_x1_status0_firmwareModeSelect_DEFAULT 0 2797 #define rx_x1_status0_firmwareModeSelect_SFP_OPT_LR 1 2798 #define rx_x1_status0_firmwareModeSelect_SFP_DAC 2 2799 #define rx_x1_status0_firmwareModeSelect_XLAUI 3 2800 #define rx_x1_status0_firmwareModeSelect_LONG_CH_6G 4 2801 2802 /**************************************************************************** 2803 * Enums: rx_x1_status0_tempIdxSelect 2804 */ 2805 #define rx_x1_status0_tempIdxSelect_LTE__22p9C 15 2806 #define rx_x1_status0_tempIdxSelect_LTE__12p6C 14 2807 #define rx_x1_status0_tempIdxSelect_LTE__3p0C 13 2808 #define rx_x1_status0_tempIdxSelect_LTE_6p7C 12 2809 #define rx_x1_status0_tempIdxSelect_LTE_16p4C 11 2810 #define rx_x1_status0_tempIdxSelect_LTE_26p6C 10 2811 #define rx_x1_status0_tempIdxSelect_LTE_36p3C 9 2812 #define rx_x1_status0_tempIdxSelect_LTE_46p0C 8 2813 #define rx_x1_status0_tempIdxSelect_LTE_56p2C 7 2814 #define rx_x1_status0_tempIdxSelect_LTE_65p9C 6 2815 #define rx_x1_status0_tempIdxSelect_LTE_75p6C 5 2816 #define rx_x1_status0_tempIdxSelect_LTE_85p3C 4 2817 #define rx_x1_status0_tempIdxSelect_LTE_95p5C 3 2818 #define rx_x1_status0_tempIdxSelect_LTE_105p2C 2 2819 #define rx_x1_status0_tempIdxSelect_LTE_114p9C 1 2820 #define rx_x1_status0_tempIdxSelect_LTE_125p1C 0 2821 2822 /**************************************************************************** 2823 * Enums: rx_x1_status0_port_mode 2824 */ 2825 #define rx_x1_status0_port_mode_QUAD_PORT 0 2826 #define rx_x1_status0_port_mode_TRI_1_PORT 1 2827 #define rx_x1_status0_port_mode_TRI_2_PORT 2 2828 #define rx_x1_status0_port_mode_DUAL_PORT 3 2829 #define rx_x1_status0_port_mode_SINGLE_PORT 4 2830 2831 /**************************************************************************** 2832 * Enums: rx_x1_status0_rev_letter_enum 2833 */ 2834 #define rx_x1_status0_rev_letter_enum_REV_A 0 2835 #define rx_x1_status0_rev_letter_enum_REV_B 1 2836 #define rx_x1_status0_rev_letter_enum_REV_C 2 2837 #define rx_x1_status0_rev_letter_enum_REV_D 3 2838 2839 /**************************************************************************** 2840 * Enums: rx_x1_status0_rev_number_enum 2841 */ 2842 #define rx_x1_status0_rev_number_enum_REV_0 0 2843 #define rx_x1_status0_rev_number_enum_REV_1 1 2844 #define rx_x1_status0_rev_number_enum_REV_2 2 2845 #define rx_x1_status0_rev_number_enum_REV_3 3 2846 #define rx_x1_status0_rev_number_enum_REV_4 4 2847 #define rx_x1_status0_rev_number_enum_REV_5 5 2848 #define rx_x1_status0_rev_number_enum_REV_6 6 2849 #define rx_x1_status0_rev_number_enum_REV_7 7 2850 2851 /**************************************************************************** 2852 * Enums: rx_x1_status0_bonding_enum 2853 */ 2854 #define rx_x1_status0_bonding_enum_WIRE_BOND 0 2855 #define rx_x1_status0_bonding_enum_FLIP_CHIP 1 2856 2857 /**************************************************************************** 2858 * Enums: rx_x1_status0_tech_process 2859 */ 2860 #define rx_x1_status0_tech_process_PROCESS_90NM 0 2861 #define rx_x1_status0_tech_process_PROCESS_65NM 1 2862 #define rx_x1_status0_tech_process_PROCESS_40NM 2 2863 #define rx_x1_status0_tech_process_PROCESS_28NM 3 2864 2865 /**************************************************************************** 2866 * Enums: rx_x1_status0_model_num 2867 */ 2868 #define rx_x1_status0_model_num_SERDES_CL73 0 2869 #define rx_x1_status0_model_num_XGXS_16G 1 2870 #define rx_x1_status0_model_num_HYPERCORE 2 2871 #define rx_x1_status0_model_num_HYPERLITE 3 2872 #define rx_x1_status0_model_num_PCIE_G2_PIPE 4 2873 #define rx_x1_status0_model_num_SERDES_1p25GBd 5 2874 #define rx_x1_status0_model_num_SATA2 6 2875 #define rx_x1_status0_model_num_QSGMII 7 2876 #define rx_x1_status0_model_num_XGXS10G 8 2877 #define rx_x1_status0_model_num_WARPCORE 9 2878 #define rx_x1_status0_model_num_XFICORE 10 2879 #define rx_x1_status0_model_num_RXFI 11 2880 #define rx_x1_status0_model_num_WARPLITE 12 2881 #define rx_x1_status0_model_num_PENTACORE 13 2882 #define rx_x1_status0_model_num_ESM 14 2883 #define rx_x1_status0_model_num_QUAD_SGMII 15 2884 #define rx_x1_status0_model_num_WARPCORE_3 16 2885 #define rx_x1_status0_model_num_TSC 17 2886 #define rx_x1_status0_model_num_TSC4E 18 2887 #define rx_x1_status0_model_num_TSC12E 19 2888 #define rx_x1_status0_model_num_TSC4F 20 2889 #define rx_x1_status0_model_num_XGXS_CL73_90NM 29 2890 #define rx_x1_status0_model_num_SERDES_CL73_90NM 30 2891 #define rx_x1_status0_model_num_WARPCORE3 32 2892 #define rx_x1_status0_model_num_WARPCORE4_TSC 33 2893 #define rx_x1_status0_model_num_RXAUI 34 2894 2895 /**************************************************************************** 2896 * Enums: rx_x1_status0_payload 2897 */ 2898 #define rx_x1_status0_payload_REPEAT_2_BYTES 0 2899 #define rx_x1_status0_payload_RAMPING 1 2900 #define rx_x1_status0_payload_CL48_CRPAT 2 2901 #define rx_x1_status0_payload_CL48_CJPAT 3 2902 #define rx_x1_status0_payload_CL36_LONG_CRPAT 4 2903 #define rx_x1_status0_payload_CL36_SHORT_CRPAT 5 2904 2905 /**************************************************************************** 2906 * Enums: rx_x1_status0_sc 2907 */ 2908 #define rx_x1_status0_sc_S_10G_CR1 0 2909 #define rx_x1_status0_sc_S_10G_KR1 1 2910 #define rx_x1_status0_sc_S_10G_X1 2 2911 #define rx_x1_status0_sc_S_10G_HG2_CR1 4 2912 #define rx_x1_status0_sc_S_10G_HG2_KR1 5 2913 #define rx_x1_status0_sc_S_10G_HG2_X1 6 2914 #define rx_x1_status0_sc_S_20G_CR1 8 2915 #define rx_x1_status0_sc_S_20G_KR1 9 2916 #define rx_x1_status0_sc_S_20G_X1 10 2917 #define rx_x1_status0_sc_S_20G_HG2_CR1 12 2918 #define rx_x1_status0_sc_S_20G_HG2_KR1 13 2919 #define rx_x1_status0_sc_S_20G_HG2_X1 14 2920 #define rx_x1_status0_sc_S_25G_CR1 16 2921 #define rx_x1_status0_sc_S_25G_KR1 17 2922 #define rx_x1_status0_sc_S_25G_X1 18 2923 #define rx_x1_status0_sc_S_25G_HG2_CR1 20 2924 #define rx_x1_status0_sc_S_25G_HG2_KR1 21 2925 #define rx_x1_status0_sc_S_25G_HG2_X1 22 2926 #define rx_x1_status0_sc_S_20G_CR2 24 2927 #define rx_x1_status0_sc_S_20G_KR2 25 2928 #define rx_x1_status0_sc_S_20G_X2 26 2929 #define rx_x1_status0_sc_S_20G_HG2_CR2 28 2930 #define rx_x1_status0_sc_S_20G_HG2_KR2 29 2931 #define rx_x1_status0_sc_S_20G_HG2_X2 30 2932 #define rx_x1_status0_sc_S_40G_CR2 32 2933 #define rx_x1_status0_sc_S_40G_KR2 33 2934 #define rx_x1_status0_sc_S_40G_X2 34 2935 #define rx_x1_status0_sc_S_40G_HG2_CR2 36 2936 #define rx_x1_status0_sc_S_40G_HG2_KR2 37 2937 #define rx_x1_status0_sc_S_40G_HG2_X2 38 2938 #define rx_x1_status0_sc_S_40G_CR4 40 2939 #define rx_x1_status0_sc_S_40G_KR4 41 2940 #define rx_x1_status0_sc_S_40G_X4 42 2941 #define rx_x1_status0_sc_S_40G_HG2_CR4 44 2942 #define rx_x1_status0_sc_S_40G_HG2_KR4 45 2943 #define rx_x1_status0_sc_S_40G_HG2_X4 46 2944 #define rx_x1_status0_sc_S_50G_CR2 48 2945 #define rx_x1_status0_sc_S_50G_KR2 49 2946 #define rx_x1_status0_sc_S_50G_X2 50 2947 #define rx_x1_status0_sc_S_50G_HG2_CR2 52 2948 #define rx_x1_status0_sc_S_50G_HG2_KR2 53 2949 #define rx_x1_status0_sc_S_50G_HG2_X2 54 2950 #define rx_x1_status0_sc_S_50G_CR4 56 2951 #define rx_x1_status0_sc_S_50G_KR4 57 2952 #define rx_x1_status0_sc_S_50G_X4 58 2953 #define rx_x1_status0_sc_S_50G_HG2_CR4 60 2954 #define rx_x1_status0_sc_S_50G_HG2_KR4 61 2955 #define rx_x1_status0_sc_S_50G_HG2_X4 62 2956 #define rx_x1_status0_sc_S_100G_CR4 64 2957 #define rx_x1_status0_sc_S_100G_KR4 65 2958 #define rx_x1_status0_sc_S_100G_X4 66 2959 #define rx_x1_status0_sc_S_100G_HG2_CR4 68 2960 #define rx_x1_status0_sc_S_100G_HG2_KR4 69 2961 #define rx_x1_status0_sc_S_100G_HG2_X4 70 2962 #define rx_x1_status0_sc_S_CL73_20GVCO 72 2963 #define rx_x1_status0_sc_S_CL73_25GVCO 80 2964 #define rx_x1_status0_sc_S_CL36_20GVCO 88 2965 #define rx_x1_status0_sc_S_CL36_25GVCO 96 2966 2967 /**************************************************************************** 2968 * Enums: rx_x1_status0_t_fifo_modes 2969 */ 2970 #define rx_x1_status0_t_fifo_modes_T_FIFO_MODE_BYPASS 0 2971 #define rx_x1_status0_t_fifo_modes_T_FIFO_MODE_40G 1 2972 #define rx_x1_status0_t_fifo_modes_T_FIFO_MODE_100G 2 2973 #define rx_x1_status0_t_fifo_modes_T_FIFO_MODE_20G 3 2974 2975 /**************************************************************************** 2976 * Enums: rx_x1_status0_t_enc_modes 2977 */ 2978 #define rx_x1_status0_t_enc_modes_T_ENC_MODE_BYPASS 0 2979 #define rx_x1_status0_t_enc_modes_T_ENC_MODE_CL49 1 2980 #define rx_x1_status0_t_enc_modes_T_ENC_MODE_CL82 2 2981 2982 /**************************************************************************** 2983 * Enums: rx_x1_status0_btmx_mode 2984 */ 2985 #define rx_x1_status0_btmx_mode_BS_BTMX_MODE_1to1 0 2986 #define rx_x1_status0_btmx_mode_BS_BTMX_MODE_2to1 1 2987 #define rx_x1_status0_btmx_mode_BS_BTMX_MODE_5to1 2 2988 2989 /**************************************************************************** 2990 * Enums: rx_x1_status0_t_type_cl82 2991 */ 2992 #define rx_x1_status0_t_type_cl82_T_TYPE_B1 5 2993 #define rx_x1_status0_t_type_cl82_T_TYPE_C 4 2994 #define rx_x1_status0_t_type_cl82_T_TYPE_S 3 2995 #define rx_x1_status0_t_type_cl82_T_TYPE_T 2 2996 #define rx_x1_status0_t_type_cl82_T_TYPE_D 1 2997 #define rx_x1_status0_t_type_cl82_T_TYPE_E 0 2998 2999 /**************************************************************************** 3000 * Enums: rx_x1_status0_txsm_state_cl82 3001 */ 3002 #define rx_x1_status0_txsm_state_cl82_TX_HIG_END 6 3003 #define rx_x1_status0_txsm_state_cl82_TX_HIG_START 5 3004 #define rx_x1_status0_txsm_state_cl82_TX_E 4 3005 #define rx_x1_status0_txsm_state_cl82_TX_T 3 3006 #define rx_x1_status0_txsm_state_cl82_TX_D 2 3007 #define rx_x1_status0_txsm_state_cl82_TX_C 1 3008 #define rx_x1_status0_txsm_state_cl82_TX_INIT 0 3009 3010 /**************************************************************************** 3011 * Enums: rx_x1_status0_ltxsm_state_cl82 3012 */ 3013 #define rx_x1_status0_ltxsm_state_cl82_TX_HIG_END 64 3014 #define rx_x1_status0_ltxsm_state_cl82_TX_HIG_START 32 3015 #define rx_x1_status0_ltxsm_state_cl82_TX_E 16 3016 #define rx_x1_status0_ltxsm_state_cl82_TX_T 8 3017 #define rx_x1_status0_ltxsm_state_cl82_TX_D 4 3018 #define rx_x1_status0_ltxsm_state_cl82_TX_C 2 3019 #define rx_x1_status0_ltxsm_state_cl82_TX_INIT 1 3020 3021 /**************************************************************************** 3022 * Enums: rx_x1_status0_r_type_coded_cl82 3023 */ 3024 #define rx_x1_status0_r_type_coded_cl82_R_TYPE_B1 32 3025 #define rx_x1_status0_r_type_coded_cl82_R_TYPE_C 16 3026 #define rx_x1_status0_r_type_coded_cl82_R_TYPE_S 8 3027 #define rx_x1_status0_r_type_coded_cl82_R_TYPE_T 4 3028 #define rx_x1_status0_r_type_coded_cl82_R_TYPE_D 2 3029 #define rx_x1_status0_r_type_coded_cl82_R_TYPE_E 1 3030 3031 /**************************************************************************** 3032 * Enums: rx_x1_status0_rxsm_state_cl82 3033 */ 3034 #define rx_x1_status0_rxsm_state_cl82_RX_HIG_END 64 3035 #define rx_x1_status0_rxsm_state_cl82_RX_HIG_START 32 3036 #define rx_x1_status0_rxsm_state_cl82_RX_E 16 3037 #define rx_x1_status0_rxsm_state_cl82_RX_T 8 3038 #define rx_x1_status0_rxsm_state_cl82_RX_D 4 3039 #define rx_x1_status0_rxsm_state_cl82_RX_C 2 3040 #define rx_x1_status0_rxsm_state_cl82_RX_INIT 1 3041 3042 /**************************************************************************** 3043 * Enums: rx_x1_status0_deskew_state 3044 */ 3045 #define rx_x1_status0_deskew_state_ALIGN_ACQUIRED 2 3046 #define rx_x1_status0_deskew_state_LOSS_OF_ALIGNMENT 1 3047 3048 /**************************************************************************** 3049 * Enums: rx_x1_status0_os_mode_enum 3050 */ 3051 #define rx_x1_status0_os_mode_enum_OS_MODE_1 0 3052 #define rx_x1_status0_os_mode_enum_OS_MODE_2 1 3053 #define rx_x1_status0_os_mode_enum_OS_MODE_4 2 3054 #define rx_x1_status0_os_mode_enum_OS_MODE_16p5 8 3055 #define rx_x1_status0_os_mode_enum_OS_MODE_20p625 12 3056 3057 /**************************************************************************** 3058 * Enums: rx_x1_status0_scr_modes 3059 */ 3060 #define rx_x1_status0_scr_modes_T_SCR_MODE_BYPASS 0 3061 #define rx_x1_status0_scr_modes_T_SCR_MODE_CL49 1 3062 #define rx_x1_status0_scr_modes_T_SCR_MODE_40G_2_LANE 2 3063 #define rx_x1_status0_scr_modes_T_SCR_MODE_100G 3 3064 #define rx_x1_status0_scr_modes_T_SCR_MODE_20G 4 3065 #define rx_x1_status0_scr_modes_T_SCR_MODE_40G_4_LANE 5 3066 3067 /**************************************************************************** 3068 * Enums: rx_x1_status0_descr_modes 3069 */ 3070 #define rx_x1_status0_descr_modes_R_DESCR_MODE_BYPASS 0 3071 #define rx_x1_status0_descr_modes_R_DESCR_MODE_CL49 1 3072 #define rx_x1_status0_descr_modes_R_DESCR_MODE_CL82 2 3073 3074 /**************************************************************************** 3075 * Enums: rx_x1_status0_r_dec_tl_mode 3076 */ 3077 #define rx_x1_status0_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 3078 #define rx_x1_status0_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 3079 #define rx_x1_status0_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 3080 3081 /**************************************************************************** 3082 * Enums: rx_x1_status0_r_dec_fsm_mode 3083 */ 3084 #define rx_x1_status0_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 3085 #define rx_x1_status0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 3086 #define rx_x1_status0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 3087 3088 /**************************************************************************** 3089 * Enums: rx_x1_status0_r_deskew_mode 3090 */ 3091 #define rx_x1_status0_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 3092 #define rx_x1_status0_r_deskew_mode_R_DESKEW_MODE_20G 1 3093 #define rx_x1_status0_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 3094 #define rx_x1_status0_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 3095 #define rx_x1_status0_r_deskew_mode_R_DESKEW_MODE_100G 4 3096 #define rx_x1_status0_r_deskew_mode_R_DESKEW_MODE_CL49 5 3097 #define rx_x1_status0_r_deskew_mode_R_DESKEW_MODE_CL91 6 3098 3099 /**************************************************************************** 3100 * Enums: rx_x1_status0_bs_dist_modes 3101 */ 3102 #define rx_x1_status0_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 3103 #define rx_x1_status0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 3104 #define rx_x1_status0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 3105 #define rx_x1_status0_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 3106 3107 /**************************************************************************** 3108 * Enums: rx_x1_status0_cl49_t_type 3109 */ 3110 #define rx_x1_status0_cl49_t_type_BAD_T_TYPE 15 3111 #define rx_x1_status0_cl49_t_type_T_TYPE_B0 11 3112 #define rx_x1_status0_cl49_t_type_T_TYPE_OB 10 3113 #define rx_x1_status0_cl49_t_type_T_TYPE_B1 9 3114 #define rx_x1_status0_cl49_t_type_T_TYPE_DB 8 3115 #define rx_x1_status0_cl49_t_type_T_TYPE_FC 7 3116 #define rx_x1_status0_cl49_t_type_T_TYPE_TB 6 3117 #define rx_x1_status0_cl49_t_type_T_TYPE_LI 5 3118 #define rx_x1_status0_cl49_t_type_T_TYPE_C 4 3119 #define rx_x1_status0_cl49_t_type_T_TYPE_S 3 3120 #define rx_x1_status0_cl49_t_type_T_TYPE_T 2 3121 #define rx_x1_status0_cl49_t_type_T_TYPE_D 1 3122 #define rx_x1_status0_cl49_t_type_T_TYPE_E 0 3123 3124 /**************************************************************************** 3125 * Enums: rx_x1_status0_cl49_txsm_states 3126 */ 3127 #define rx_x1_status0_cl49_txsm_states_TX_HIG_END 7 3128 #define rx_x1_status0_cl49_txsm_states_TX_HIG_START 6 3129 #define rx_x1_status0_cl49_txsm_states_TX_LI 5 3130 #define rx_x1_status0_cl49_txsm_states_TX_E 4 3131 #define rx_x1_status0_cl49_txsm_states_TX_T 3 3132 #define rx_x1_status0_cl49_txsm_states_TX_D 2 3133 #define rx_x1_status0_cl49_txsm_states_TX_C 1 3134 #define rx_x1_status0_cl49_txsm_states_TX_INIT 0 3135 3136 /**************************************************************************** 3137 * Enums: rx_x1_status0_cl49_ltxsm_states 3138 */ 3139 #define rx_x1_status0_cl49_ltxsm_states_TX_HIG_END 128 3140 #define rx_x1_status0_cl49_ltxsm_states_TX_HIG_START 64 3141 #define rx_x1_status0_cl49_ltxsm_states_TX_LI 32 3142 #define rx_x1_status0_cl49_ltxsm_states_TX_E 16 3143 #define rx_x1_status0_cl49_ltxsm_states_TX_T 8 3144 #define rx_x1_status0_cl49_ltxsm_states_TX_D 4 3145 #define rx_x1_status0_cl49_ltxsm_states_TX_C 2 3146 #define rx_x1_status0_cl49_ltxsm_states_TX_INIT 1 3147 3148 /**************************************************************************** 3149 * Enums: rx_x1_status0_burst_error_mode 3150 */ 3151 #define rx_x1_status0_burst_error_mode_BURST_ERROR_11_BITS 0 3152 #define rx_x1_status0_burst_error_mode_BURST_ERROR_16_BITS 1 3153 #define rx_x1_status0_burst_error_mode_BURST_ERROR_17_BITS 2 3154 #define rx_x1_status0_burst_error_mode_BURST_ERROR_18_BITS 3 3155 #define rx_x1_status0_burst_error_mode_BURST_ERROR_19_BITS 4 3156 #define rx_x1_status0_burst_error_mode_BURST_ERROR_20_BITS 5 3157 #define rx_x1_status0_burst_error_mode_BURST_ERROR_21_BITS 6 3158 #define rx_x1_status0_burst_error_mode_BURST_ERROR_22_BITS 7 3159 #define rx_x1_status0_burst_error_mode_BURST_ERROR_23_BITS 8 3160 #define rx_x1_status0_burst_error_mode_BURST_ERROR_24_BITS 9 3161 #define rx_x1_status0_burst_error_mode_BURST_ERROR_25_BITS 10 3162 #define rx_x1_status0_burst_error_mode_BURST_ERROR_26_BITS 11 3163 #define rx_x1_status0_burst_error_mode_BURST_ERROR_27_BITS 12 3164 #define rx_x1_status0_burst_error_mode_BURST_ERROR_28_BITS 13 3165 #define rx_x1_status0_burst_error_mode_BURST_ERROR_29_BITS 14 3166 #define rx_x1_status0_burst_error_mode_BURST_ERROR_30_BITS 15 3167 #define rx_x1_status0_burst_error_mode_BURST_ERROR_31_BITS 16 3168 #define rx_x1_status0_burst_error_mode_BURST_ERROR_32_BITS 17 3169 #define rx_x1_status0_burst_error_mode_BURST_ERROR_33_BITS 18 3170 #define rx_x1_status0_burst_error_mode_BURST_ERROR_34_BITS 19 3171 #define rx_x1_status0_burst_error_mode_BURST_ERROR_35_BITS 20 3172 #define rx_x1_status0_burst_error_mode_BURST_ERROR_36_BITS 21 3173 #define rx_x1_status0_burst_error_mode_BURST_ERROR_37_BITS 22 3174 #define rx_x1_status0_burst_error_mode_BURST_ERROR_38_BITS 23 3175 #define rx_x1_status0_burst_error_mode_BURST_ERROR_39_BITS 24 3176 #define rx_x1_status0_burst_error_mode_BURST_ERROR_40_BITS 25 3177 #define rx_x1_status0_burst_error_mode_BURST_ERROR_41_BITS 26 3178 3179 /**************************************************************************** 3180 * Enums: rx_x1_status0_bermon_state 3181 */ 3182 #define rx_x1_status0_bermon_state_HI_BER 4 3183 #define rx_x1_status0_bermon_state_GOOD_BER 3 3184 #define rx_x1_status0_bermon_state_BER_TEST_SH 2 3185 #define rx_x1_status0_bermon_state_START_TIMER 1 3186 #define rx_x1_status0_bermon_state_BER_MT_INIT 0 3187 3188 /**************************************************************************** 3189 * Enums: rx_x1_status0_rxsm_state_cl49 3190 */ 3191 #define rx_x1_status0_rxsm_state_cl49_RX_HIG_END 128 3192 #define rx_x1_status0_rxsm_state_cl49_RX_HIG_START 64 3193 #define rx_x1_status0_rxsm_state_cl49_RX_LI 32 3194 #define rx_x1_status0_rxsm_state_cl49_RX_E 16 3195 #define rx_x1_status0_rxsm_state_cl49_RX_T 8 3196 #define rx_x1_status0_rxsm_state_cl49_RX_D 4 3197 #define rx_x1_status0_rxsm_state_cl49_RX_C 2 3198 #define rx_x1_status0_rxsm_state_cl49_RX_INIT 1 3199 3200 /**************************************************************************** 3201 * Enums: rx_x1_status0_r_type 3202 */ 3203 #define rx_x1_status0_r_type_BAD_R_TYPE 15 3204 #define rx_x1_status0_r_type_R_TYPE_B0 11 3205 #define rx_x1_status0_r_type_R_TYPE_OB 10 3206 #define rx_x1_status0_r_type_R_TYPE_B1 9 3207 #define rx_x1_status0_r_type_R_TYPE_DB 8 3208 #define rx_x1_status0_r_type_R_TYPE_FC 7 3209 #define rx_x1_status0_r_type_R_TYPE_TB 6 3210 #define rx_x1_status0_r_type_R_TYPE_LI 5 3211 #define rx_x1_status0_r_type_R_TYPE_C 4 3212 #define rx_x1_status0_r_type_R_TYPE_S 3 3213 #define rx_x1_status0_r_type_R_TYPE_T 2 3214 #define rx_x1_status0_r_type_R_TYPE_D 1 3215 #define rx_x1_status0_r_type_R_TYPE_E 0 3216 3217 /**************************************************************************** 3218 * Enums: rx_x1_status0_am_lock_state 3219 */ 3220 #define rx_x1_status0_am_lock_state_INVALID_AM 512 3221 #define rx_x1_status0_am_lock_state_GOOD_AM 256 3222 #define rx_x1_status0_am_lock_state_COMP_AM 128 3223 #define rx_x1_status0_am_lock_state_TIMER_2 64 3224 #define rx_x1_status0_am_lock_state_AM_2_GOOD 32 3225 #define rx_x1_status0_am_lock_state_COMP_2ND 16 3226 #define rx_x1_status0_am_lock_state_TIMER_1 8 3227 #define rx_x1_status0_am_lock_state_FIND_1ST 4 3228 #define rx_x1_status0_am_lock_state_AM_RESET_CNT 2 3229 #define rx_x1_status0_am_lock_state_AM_LOCK_INIT 1 3230 3231 /**************************************************************************** 3232 * Enums: rx_x1_status0_msg_selector 3233 */ 3234 #define rx_x1_status0_msg_selector_RESERVED 0 3235 #define rx_x1_status0_msg_selector_VALUE_802p3 1 3236 #define rx_x1_status0_msg_selector_VALUE_802p9 2 3237 #define rx_x1_status0_msg_selector_VALUE_802p5 3 3238 #define rx_x1_status0_msg_selector_VALUE_1394 4 3239 3240 /**************************************************************************** 3241 * Enums: rx_x1_status0_synce_enum 3242 */ 3243 #define rx_x1_status0_synce_enum_SYNCE_NO_DIV 0 3244 #define rx_x1_status0_synce_enum_SYNCE_DIV_7 1 3245 #define rx_x1_status0_synce_enum_SYNCE_DIV_11 2 3246 3247 /**************************************************************************** 3248 * Enums: rx_x1_status0_synce_enum_stage0 3249 */ 3250 #define rx_x1_status0_synce_enum_stage0_SYNCE_NO_DIV 0 3251 #define rx_x1_status0_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 3252 #define rx_x1_status0_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 3253 3254 /**************************************************************************** 3255 * Enums: rx_x1_status0_cl91_sync_state 3256 */ 3257 #define rx_x1_status0_cl91_sync_state_FIND_1ST 0 3258 #define rx_x1_status0_cl91_sync_state_COUNT_NEXT 1 3259 #define rx_x1_status0_cl91_sync_state_COMP_2ND 2 3260 #define rx_x1_status0_cl91_sync_state_TWO_GOOD 3 3261 3262 /**************************************************************************** 3263 * Enums: rx_x1_status0_cl91_algn_state 3264 */ 3265 #define rx_x1_status0_cl91_algn_state_LOSS_OF_ALIGNMENT 0 3266 #define rx_x1_status0_cl91_algn_state_DESKEW 1 3267 #define rx_x1_status0_cl91_algn_state_DESKEW_FAIL 2 3268 #define rx_x1_status0_cl91_algn_state_ALIGN_ACQUIRED 3 3269 #define rx_x1_status0_cl91_algn_state_CW_GOOD 4 3270 #define rx_x1_status0_cl91_algn_state_CW_BAD 5 3271 #define rx_x1_status0_cl91_algn_state_THREE_BAD 6 3272 3273 /**************************************************************************** 3274 * Enums: rx_x1_status0_fec_sel 3275 */ 3276 #define rx_x1_status0_fec_sel_NO_FEC 0 3277 #define rx_x1_status0_fec_sel_FEC_CL74 1 3278 #define rx_x1_status0_fec_sel_FEC_CL91 2 3279 3280 /**************************************************************************** 3281 * Enums: rx_x4_control0_cl36TxEEEStates_l 3282 */ 3283 #define rx_x4_control0_cl36TxEEEStates_l_TX_REFRESH 8 3284 #define rx_x4_control0_cl36TxEEEStates_l_TX_QUIET 4 3285 #define rx_x4_control0_cl36TxEEEStates_l_TX_SLEEP 2 3286 #define rx_x4_control0_cl36TxEEEStates_l_TX_ACTIVE 1 3287 3288 /**************************************************************************** 3289 * Enums: rx_x4_control0_cl36TxEEEStates_c 3290 */ 3291 #define rx_x4_control0_cl36TxEEEStates_c_TX_REFRESH 3 3292 #define rx_x4_control0_cl36TxEEEStates_c_TX_QUIET 2 3293 #define rx_x4_control0_cl36TxEEEStates_c_TX_SLEEP 1 3294 #define rx_x4_control0_cl36TxEEEStates_c_TX_ACTIVE 0 3295 3296 /**************************************************************************** 3297 * Enums: rx_x4_control0_cl49TxEEEStates_l 3298 */ 3299 #define rx_x4_control0_cl49TxEEEStates_l_SCR_RESET_2 64 3300 #define rx_x4_control0_cl49TxEEEStates_l_SCR_RESET_1 32 3301 #define rx_x4_control0_cl49TxEEEStates_l_TX_WAKE 16 3302 #define rx_x4_control0_cl49TxEEEStates_l_TX_REFRESH 8 3303 #define rx_x4_control0_cl49TxEEEStates_l_TX_QUIET 4 3304 #define rx_x4_control0_cl49TxEEEStates_l_TX_SLEEP 2 3305 #define rx_x4_control0_cl49TxEEEStates_l_TX_ACTIVE 1 3306 3307 /**************************************************************************** 3308 * Enums: rx_x4_control0_fec_req_enum 3309 */ 3310 #define rx_x4_control0_fec_req_enum_FEC_not_supported 0 3311 #define rx_x4_control0_fec_req_enum_FEC_supported_but_not_requested 1 3312 #define rx_x4_control0_fec_req_enum_invalid_setting 2 3313 #define rx_x4_control0_fec_req_enum_FEC_supported_and_requested 3 3314 3315 /**************************************************************************** 3316 * Enums: rx_x4_control0_cl73_pause_enum 3317 */ 3318 #define rx_x4_control0_cl73_pause_enum_No_PAUSE_ability 0 3319 #define rx_x4_control0_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 3320 #define rx_x4_control0_cl73_pause_enum_Symmetric_PAUSE_ability 1 3321 #define rx_x4_control0_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 3322 3323 /**************************************************************************** 3324 * Enums: rx_x4_control0_cl49TxEEEStates_c 3325 */ 3326 #define rx_x4_control0_cl49TxEEEStates_c_SCR_RESET_2 6 3327 #define rx_x4_control0_cl49TxEEEStates_c_SCR_RESET_1 5 3328 #define rx_x4_control0_cl49TxEEEStates_c_TX_WAKE 4 3329 #define rx_x4_control0_cl49TxEEEStates_c_TX_REFRESH 3 3330 #define rx_x4_control0_cl49TxEEEStates_c_TX_QUIET 2 3331 #define rx_x4_control0_cl49TxEEEStates_c_TX_SLEEP 1 3332 #define rx_x4_control0_cl49TxEEEStates_c_TX_ACTIVE 0 3333 3334 /**************************************************************************** 3335 * Enums: rx_x4_control0_cl36RxEEEStates_l 3336 */ 3337 #define rx_x4_control0_cl36RxEEEStates_l_RX_LINK_FAIL 32 3338 #define rx_x4_control0_cl36RxEEEStates_l_RX_WTF 16 3339 #define rx_x4_control0_cl36RxEEEStates_l_RX_WAKE 8 3340 #define rx_x4_control0_cl36RxEEEStates_l_RX_QUIET 4 3341 #define rx_x4_control0_cl36RxEEEStates_l_RX_SLEEP 2 3342 #define rx_x4_control0_cl36RxEEEStates_l_RX_ACTIVE 1 3343 3344 /**************************************************************************** 3345 * Enums: rx_x4_control0_cl36RxEEEStates_c 3346 */ 3347 #define rx_x4_control0_cl36RxEEEStates_c_RX_LINK_FAIL 5 3348 #define rx_x4_control0_cl36RxEEEStates_c_RX_WTF 4 3349 #define rx_x4_control0_cl36RxEEEStates_c_RX_WAKE 3 3350 #define rx_x4_control0_cl36RxEEEStates_c_RX_QUIET 2 3351 #define rx_x4_control0_cl36RxEEEStates_c_RX_SLEEP 1 3352 #define rx_x4_control0_cl36RxEEEStates_c_RX_ACTIVE 0 3353 3354 /**************************************************************************** 3355 * Enums: rx_x4_control0_cl49RxEEEStates_l 3356 */ 3357 #define rx_x4_control0_cl49RxEEEStates_l_RX_LINK_FAIL 32 3358 #define rx_x4_control0_cl49RxEEEStates_l_RX_WTF 16 3359 #define rx_x4_control0_cl49RxEEEStates_l_RX_WAKE 8 3360 #define rx_x4_control0_cl49RxEEEStates_l_RX_QUIET 4 3361 #define rx_x4_control0_cl49RxEEEStates_l_RX_SLEEP 2 3362 #define rx_x4_control0_cl49RxEEEStates_l_RX_ACTIVE 1 3363 3364 /**************************************************************************** 3365 * Enums: rx_x4_control0_cl49RxEEEStates_c 3366 */ 3367 #define rx_x4_control0_cl49RxEEEStates_c_RX_LINK_FAIL 5 3368 #define rx_x4_control0_cl49RxEEEStates_c_RX_WTF 4 3369 #define rx_x4_control0_cl49RxEEEStates_c_RX_WAKE 3 3370 #define rx_x4_control0_cl49RxEEEStates_c_RX_QUIET 2 3371 #define rx_x4_control0_cl49RxEEEStates_c_RX_SLEEP 1 3372 #define rx_x4_control0_cl49RxEEEStates_c_RX_ACTIVE 0 3373 3374 /**************************************************************************** 3375 * Enums: rx_x4_control0_cl48TxEEEStates_l 3376 */ 3377 #define rx_x4_control0_cl48TxEEEStates_l_TX_REFRESH 8 3378 #define rx_x4_control0_cl48TxEEEStates_l_TX_QUIET 4 3379 #define rx_x4_control0_cl48TxEEEStates_l_TX_SLEEP 2 3380 #define rx_x4_control0_cl48TxEEEStates_l_TX_ACTIVE 1 3381 3382 /**************************************************************************** 3383 * Enums: rx_x4_control0_cl48TxEEEStates_c 3384 */ 3385 #define rx_x4_control0_cl48TxEEEStates_c_TX_REFRESH 3 3386 #define rx_x4_control0_cl48TxEEEStates_c_TX_QUIET 2 3387 #define rx_x4_control0_cl48TxEEEStates_c_TX_SLEEP 1 3388 #define rx_x4_control0_cl48TxEEEStates_c_TX_ACTIVE 0 3389 3390 /**************************************************************************** 3391 * Enums: rx_x4_control0_cl48RxEEEStates_l 3392 */ 3393 #define rx_x4_control0_cl48RxEEEStates_l_RX_LINK_FAIL 32 3394 #define rx_x4_control0_cl48RxEEEStates_l_RX_WAKE 16 3395 #define rx_x4_control0_cl48RxEEEStates_l_RX_QUIET 8 3396 #define rx_x4_control0_cl48RxEEEStates_l_RX_DEACT 4 3397 #define rx_x4_control0_cl48RxEEEStates_l_RX_SLEEP 2 3398 #define rx_x4_control0_cl48RxEEEStates_l_RX_ACTIVE 1 3399 3400 /**************************************************************************** 3401 * Enums: rx_x4_control0_cl48RxEEEStates_c 3402 */ 3403 #define rx_x4_control0_cl48RxEEEStates_c_RX_LINK_FAIL 5 3404 #define rx_x4_control0_cl48RxEEEStates_c_RX_WAKE 4 3405 #define rx_x4_control0_cl48RxEEEStates_c_RX_QUIET 3 3406 #define rx_x4_control0_cl48RxEEEStates_c_RX_DEACT 2 3407 #define rx_x4_control0_cl48RxEEEStates_c_RX_SLEEP 1 3408 #define rx_x4_control0_cl48RxEEEStates_c_RX_ACTIVE 0 3409 3410 /**************************************************************************** 3411 * Enums: rx_x4_control0_IQP_Options 3412 */ 3413 #define rx_x4_control0_IQP_Options_i50uA 0 3414 #define rx_x4_control0_IQP_Options_i100uA 1 3415 #define rx_x4_control0_IQP_Options_i150uA 2 3416 #define rx_x4_control0_IQP_Options_i200uA 3 3417 #define rx_x4_control0_IQP_Options_i250uA 4 3418 #define rx_x4_control0_IQP_Options_i300uA 5 3419 #define rx_x4_control0_IQP_Options_i350uA 6 3420 #define rx_x4_control0_IQP_Options_i400uA 7 3421 #define rx_x4_control0_IQP_Options_i450uA 8 3422 #define rx_x4_control0_IQP_Options_i500uA 9 3423 #define rx_x4_control0_IQP_Options_i550uA 10 3424 #define rx_x4_control0_IQP_Options_i600uA 11 3425 #define rx_x4_control0_IQP_Options_i650uA 12 3426 #define rx_x4_control0_IQP_Options_i700uA 13 3427 #define rx_x4_control0_IQP_Options_i750uA 14 3428 #define rx_x4_control0_IQP_Options_i800uA 15 3429 3430 /**************************************************************************** 3431 * Enums: rx_x4_control0_IDriver_Options 3432 */ 3433 #define rx_x4_control0_IDriver_Options_v680mV 0 3434 #define rx_x4_control0_IDriver_Options_v730mV 1 3435 #define rx_x4_control0_IDriver_Options_v780mV 2 3436 #define rx_x4_control0_IDriver_Options_v830mV 3 3437 #define rx_x4_control0_IDriver_Options_v880mV 4 3438 #define rx_x4_control0_IDriver_Options_v930mV 5 3439 #define rx_x4_control0_IDriver_Options_v980mV 6 3440 #define rx_x4_control0_IDriver_Options_v1010mV 7 3441 #define rx_x4_control0_IDriver_Options_v1040mV 8 3442 #define rx_x4_control0_IDriver_Options_v1060mV 9 3443 #define rx_x4_control0_IDriver_Options_v1070mV 10 3444 #define rx_x4_control0_IDriver_Options_v1080mV 11 3445 #define rx_x4_control0_IDriver_Options_v1085mV 12 3446 #define rx_x4_control0_IDriver_Options_v1090mV 13 3447 #define rx_x4_control0_IDriver_Options_v1095mV 14 3448 #define rx_x4_control0_IDriver_Options_v1100mV 15 3449 3450 /**************************************************************************** 3451 * Enums: rx_x4_control0_operationModes 3452 */ 3453 #define rx_x4_control0_operationModes_XGXS 0 3454 #define rx_x4_control0_operationModes_XGXG_nCC 1 3455 #define rx_x4_control0_operationModes_Indlane_OS8 4 3456 #define rx_x4_control0_operationModes_IndLane_OS5 5 3457 #define rx_x4_control0_operationModes_PCI 7 3458 #define rx_x4_control0_operationModes_XGXS_nLQ 8 3459 #define rx_x4_control0_operationModes_XGXS_nLQnCC 9 3460 #define rx_x4_control0_operationModes_PBypass 10 3461 #define rx_x4_control0_operationModes_PBypass_nDSK 11 3462 #define rx_x4_control0_operationModes_ComboCoreMode 12 3463 #define rx_x4_control0_operationModes_Clocks_off 15 3464 3465 /**************************************************************************** 3466 * Enums: rx_x4_control0_actualSpeeds 3467 */ 3468 #define rx_x4_control0_actualSpeeds_dr_10M 0 3469 #define rx_x4_control0_actualSpeeds_dr_100M 1 3470 #define rx_x4_control0_actualSpeeds_dr_1G 2 3471 #define rx_x4_control0_actualSpeeds_dr_2p5G 3 3472 #define rx_x4_control0_actualSpeeds_dr_5G_X4 4 3473 #define rx_x4_control0_actualSpeeds_dr_6G_X4 5 3474 #define rx_x4_control0_actualSpeeds_dr_10G_HiG 6 3475 #define rx_x4_control0_actualSpeeds_dr_10G_CX4 7 3476 #define rx_x4_control0_actualSpeeds_dr_12G_HiG 8 3477 #define rx_x4_control0_actualSpeeds_dr_12p5G_X4 9 3478 #define rx_x4_control0_actualSpeeds_dr_13G_X4 10 3479 #define rx_x4_control0_actualSpeeds_dr_15G_X4 11 3480 #define rx_x4_control0_actualSpeeds_dr_16G_X4 12 3481 #define rx_x4_control0_actualSpeeds_dr_1G_KX 13 3482 #define rx_x4_control0_actualSpeeds_dr_10G_KX4 14 3483 #define rx_x4_control0_actualSpeeds_dr_10G_KR 15 3484 #define rx_x4_control0_actualSpeeds_dr_5G 16 3485 #define rx_x4_control0_actualSpeeds_dr_6p4G 17 3486 #define rx_x4_control0_actualSpeeds_dr_20G_X4 18 3487 #define rx_x4_control0_actualSpeeds_dr_21G_X4 19 3488 #define rx_x4_control0_actualSpeeds_dr_25G_X4 20 3489 #define rx_x4_control0_actualSpeeds_dr_10G_HiG_DXGXS 21 3490 #define rx_x4_control0_actualSpeeds_dr_10G_DXGXS 22 3491 #define rx_x4_control0_actualSpeeds_dr_10p5G_HiG_DXGXS 23 3492 #define rx_x4_control0_actualSpeeds_dr_10p5G_DXGXS 24 3493 #define rx_x4_control0_actualSpeeds_dr_12p773G_HiG_DXGXS 25 3494 #define rx_x4_control0_actualSpeeds_dr_12p773G_DXGXS 26 3495 #define rx_x4_control0_actualSpeeds_dr_10G_XFI 27 3496 #define rx_x4_control0_actualSpeeds_dr_40G 28 3497 #define rx_x4_control0_actualSpeeds_dr_20G_HiG_DXGXS 29 3498 #define rx_x4_control0_actualSpeeds_dr_20G_DXGXS 30 3499 #define rx_x4_control0_actualSpeeds_dr_10G_SFI 31 3500 #define rx_x4_control0_actualSpeeds_dr_31p5G 32 3501 #define rx_x4_control0_actualSpeeds_dr_32p7G 33 3502 #define rx_x4_control0_actualSpeeds_dr_20G_SCR 34 3503 #define rx_x4_control0_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 3504 #define rx_x4_control0_actualSpeeds_dr_10G_DXGXS_SCR 36 3505 #define rx_x4_control0_actualSpeeds_dr_12G_R2 37 3506 #define rx_x4_control0_actualSpeeds_dr_10G_X2 38 3507 #define rx_x4_control0_actualSpeeds_dr_40G_KR4 39 3508 #define rx_x4_control0_actualSpeeds_dr_40G_CR4 40 3509 #define rx_x4_control0_actualSpeeds_dr_100G_CR10 41 3510 #define rx_x4_control0_actualSpeeds_dr_15p75G_DXGXS 44 3511 #define rx_x4_control0_actualSpeeds_dr_20G_KR2 57 3512 #define rx_x4_control0_actualSpeeds_dr_20G_CR2 58 3513 3514 /**************************************************************************** 3515 * Enums: rx_x4_control0_actualSpeedsMisc1 3516 */ 3517 #define rx_x4_control0_actualSpeedsMisc1_dr_2500BRCM_X1 16 3518 #define rx_x4_control0_actualSpeedsMisc1_dr_5000BRCM_X4 17 3519 #define rx_x4_control0_actualSpeedsMisc1_dr_6000BRCM_X4 18 3520 #define rx_x4_control0_actualSpeedsMisc1_dr_10GHiGig_X4 19 3521 #define rx_x4_control0_actualSpeedsMisc1_dr_10GBASE_CX4 20 3522 #define rx_x4_control0_actualSpeedsMisc1_dr_12GHiGig_X4 21 3523 #define rx_x4_control0_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 3524 #define rx_x4_control0_actualSpeedsMisc1_dr_13GHiGig_X4 23 3525 #define rx_x4_control0_actualSpeedsMisc1_dr_15GHiGig_X4 24 3526 #define rx_x4_control0_actualSpeedsMisc1_dr_16GHiGig_X4 25 3527 #define rx_x4_control0_actualSpeedsMisc1_dr_5000BRCM_X1 26 3528 #define rx_x4_control0_actualSpeedsMisc1_dr_6363BRCM_X1 27 3529 #define rx_x4_control0_actualSpeedsMisc1_dr_20GHiGig_X4 28 3530 #define rx_x4_control0_actualSpeedsMisc1_dr_21GHiGig_X4 29 3531 #define rx_x4_control0_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 3532 #define rx_x4_control0_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 3533 3534 /**************************************************************************** 3535 * Enums: rx_x4_control0_IndLaneModes 3536 */ 3537 #define rx_x4_control0_IndLaneModes_SWSDR_div2 0 3538 #define rx_x4_control0_IndLaneModes_SWSDR_div1 1 3539 #define rx_x4_control0_IndLaneModes_DWSDR_div2 2 3540 #define rx_x4_control0_IndLaneModes_DWSDR_div1 3 3541 3542 /**************************************************************************** 3543 * Enums: rx_x4_control0_prbsSelect 3544 */ 3545 #define rx_x4_control0_prbsSelect_prbs7 0 3546 #define rx_x4_control0_prbsSelect_prbs15 1 3547 #define rx_x4_control0_prbsSelect_prbs23 2 3548 #define rx_x4_control0_prbsSelect_prbs31 3 3549 3550 /**************************************************************************** 3551 * Enums: rx_x4_control0_vcoDivider 3552 */ 3553 #define rx_x4_control0_vcoDivider_div32 0 3554 #define rx_x4_control0_vcoDivider_div36 1 3555 #define rx_x4_control0_vcoDivider_div40 2 3556 #define rx_x4_control0_vcoDivider_div42 3 3557 #define rx_x4_control0_vcoDivider_div48 4 3558 #define rx_x4_control0_vcoDivider_div50 5 3559 #define rx_x4_control0_vcoDivider_div52 6 3560 #define rx_x4_control0_vcoDivider_div54 7 3561 #define rx_x4_control0_vcoDivider_div60 8 3562 #define rx_x4_control0_vcoDivider_div64 9 3563 #define rx_x4_control0_vcoDivider_div66 10 3564 #define rx_x4_control0_vcoDivider_div68 11 3565 #define rx_x4_control0_vcoDivider_div70 12 3566 #define rx_x4_control0_vcoDivider_div80 13 3567 #define rx_x4_control0_vcoDivider_div92 14 3568 #define rx_x4_control0_vcoDivider_div100 15 3569 3570 /**************************************************************************** 3571 * Enums: rx_x4_control0_refClkSelect 3572 */ 3573 #define rx_x4_control0_refClkSelect_clk_25MHz 0 3574 #define rx_x4_control0_refClkSelect_clk_100MHz 1 3575 #define rx_x4_control0_refClkSelect_clk_125MHz 2 3576 #define rx_x4_control0_refClkSelect_clk_156p25MHz 3 3577 #define rx_x4_control0_refClkSelect_clk_187p5MHz 4 3578 #define rx_x4_control0_refClkSelect_clk_161p25Mhz 5 3579 #define rx_x4_control0_refClkSelect_clk_50Mhz 6 3580 #define rx_x4_control0_refClkSelect_clk_106p25Mhz 7 3581 3582 /**************************************************************************** 3583 * Enums: rx_x4_control0_aerMMDdevTypeSelect 3584 */ 3585 #define rx_x4_control0_aerMMDdevTypeSelect_combo_core 0 3586 #define rx_x4_control0_aerMMDdevTypeSelect_PMA_PMD 1 3587 #define rx_x4_control0_aerMMDdevTypeSelect_PCS 3 3588 #define rx_x4_control0_aerMMDdevTypeSelect_PHY 4 3589 #define rx_x4_control0_aerMMDdevTypeSelect_DTE 5 3590 #define rx_x4_control0_aerMMDdevTypeSelect_CL73_AN 7 3591 3592 /**************************************************************************** 3593 * Enums: rx_x4_control0_aerMMDportSelect 3594 */ 3595 #define rx_x4_control0_aerMMDportSelect_ln0 0 3596 #define rx_x4_control0_aerMMDportSelect_ln1 1 3597 #define rx_x4_control0_aerMMDportSelect_ln2 2 3598 #define rx_x4_control0_aerMMDportSelect_ln3 3 3599 #define rx_x4_control0_aerMMDportSelect_BCST_ln0_1_2_3 511 3600 #define rx_x4_control0_aerMMDportSelect_BCST_ln0_1 512 3601 #define rx_x4_control0_aerMMDportSelect_BCST_ln2_3 513 3602 3603 /**************************************************************************** 3604 * Enums: rx_x4_control0_firmwareModeSelect 3605 */ 3606 #define rx_x4_control0_firmwareModeSelect_DEFAULT 0 3607 #define rx_x4_control0_firmwareModeSelect_SFP_OPT_LR 1 3608 #define rx_x4_control0_firmwareModeSelect_SFP_DAC 2 3609 #define rx_x4_control0_firmwareModeSelect_XLAUI 3 3610 #define rx_x4_control0_firmwareModeSelect_LONG_CH_6G 4 3611 3612 /**************************************************************************** 3613 * Enums: rx_x4_control0_tempIdxSelect 3614 */ 3615 #define rx_x4_control0_tempIdxSelect_LTE__22p9C 15 3616 #define rx_x4_control0_tempIdxSelect_LTE__12p6C 14 3617 #define rx_x4_control0_tempIdxSelect_LTE__3p0C 13 3618 #define rx_x4_control0_tempIdxSelect_LTE_6p7C 12 3619 #define rx_x4_control0_tempIdxSelect_LTE_16p4C 11 3620 #define rx_x4_control0_tempIdxSelect_LTE_26p6C 10 3621 #define rx_x4_control0_tempIdxSelect_LTE_36p3C 9 3622 #define rx_x4_control0_tempIdxSelect_LTE_46p0C 8 3623 #define rx_x4_control0_tempIdxSelect_LTE_56p2C 7 3624 #define rx_x4_control0_tempIdxSelect_LTE_65p9C 6 3625 #define rx_x4_control0_tempIdxSelect_LTE_75p6C 5 3626 #define rx_x4_control0_tempIdxSelect_LTE_85p3C 4 3627 #define rx_x4_control0_tempIdxSelect_LTE_95p5C 3 3628 #define rx_x4_control0_tempIdxSelect_LTE_105p2C 2 3629 #define rx_x4_control0_tempIdxSelect_LTE_114p9C 1 3630 #define rx_x4_control0_tempIdxSelect_LTE_125p1C 0 3631 3632 /**************************************************************************** 3633 * Enums: rx_x4_control0_port_mode 3634 */ 3635 #define rx_x4_control0_port_mode_QUAD_PORT 0 3636 #define rx_x4_control0_port_mode_TRI_1_PORT 1 3637 #define rx_x4_control0_port_mode_TRI_2_PORT 2 3638 #define rx_x4_control0_port_mode_DUAL_PORT 3 3639 #define rx_x4_control0_port_mode_SINGLE_PORT 4 3640 3641 /**************************************************************************** 3642 * Enums: rx_x4_control0_rev_letter_enum 3643 */ 3644 #define rx_x4_control0_rev_letter_enum_REV_A 0 3645 #define rx_x4_control0_rev_letter_enum_REV_B 1 3646 #define rx_x4_control0_rev_letter_enum_REV_C 2 3647 #define rx_x4_control0_rev_letter_enum_REV_D 3 3648 3649 /**************************************************************************** 3650 * Enums: rx_x4_control0_rev_number_enum 3651 */ 3652 #define rx_x4_control0_rev_number_enum_REV_0 0 3653 #define rx_x4_control0_rev_number_enum_REV_1 1 3654 #define rx_x4_control0_rev_number_enum_REV_2 2 3655 #define rx_x4_control0_rev_number_enum_REV_3 3 3656 #define rx_x4_control0_rev_number_enum_REV_4 4 3657 #define rx_x4_control0_rev_number_enum_REV_5 5 3658 #define rx_x4_control0_rev_number_enum_REV_6 6 3659 #define rx_x4_control0_rev_number_enum_REV_7 7 3660 3661 /**************************************************************************** 3662 * Enums: rx_x4_control0_bonding_enum 3663 */ 3664 #define rx_x4_control0_bonding_enum_WIRE_BOND 0 3665 #define rx_x4_control0_bonding_enum_FLIP_CHIP 1 3666 3667 /**************************************************************************** 3668 * Enums: rx_x4_control0_tech_process 3669 */ 3670 #define rx_x4_control0_tech_process_PROCESS_90NM 0 3671 #define rx_x4_control0_tech_process_PROCESS_65NM 1 3672 #define rx_x4_control0_tech_process_PROCESS_40NM 2 3673 #define rx_x4_control0_tech_process_PROCESS_28NM 3 3674 3675 /**************************************************************************** 3676 * Enums: rx_x4_control0_model_num 3677 */ 3678 #define rx_x4_control0_model_num_SERDES_CL73 0 3679 #define rx_x4_control0_model_num_XGXS_16G 1 3680 #define rx_x4_control0_model_num_HYPERCORE 2 3681 #define rx_x4_control0_model_num_HYPERLITE 3 3682 #define rx_x4_control0_model_num_PCIE_G2_PIPE 4 3683 #define rx_x4_control0_model_num_SERDES_1p25GBd 5 3684 #define rx_x4_control0_model_num_SATA2 6 3685 #define rx_x4_control0_model_num_QSGMII 7 3686 #define rx_x4_control0_model_num_XGXS10G 8 3687 #define rx_x4_control0_model_num_WARPCORE 9 3688 #define rx_x4_control0_model_num_XFICORE 10 3689 #define rx_x4_control0_model_num_RXFI 11 3690 #define rx_x4_control0_model_num_WARPLITE 12 3691 #define rx_x4_control0_model_num_PENTACORE 13 3692 #define rx_x4_control0_model_num_ESM 14 3693 #define rx_x4_control0_model_num_QUAD_SGMII 15 3694 #define rx_x4_control0_model_num_WARPCORE_3 16 3695 #define rx_x4_control0_model_num_TSC 17 3696 #define rx_x4_control0_model_num_TSC4E 18 3697 #define rx_x4_control0_model_num_TSC12E 19 3698 #define rx_x4_control0_model_num_TSC4F 20 3699 #define rx_x4_control0_model_num_XGXS_CL73_90NM 29 3700 #define rx_x4_control0_model_num_SERDES_CL73_90NM 30 3701 #define rx_x4_control0_model_num_WARPCORE3 32 3702 #define rx_x4_control0_model_num_WARPCORE4_TSC 33 3703 #define rx_x4_control0_model_num_RXAUI 34 3704 3705 /**************************************************************************** 3706 * Enums: rx_x4_control0_payload 3707 */ 3708 #define rx_x4_control0_payload_REPEAT_2_BYTES 0 3709 #define rx_x4_control0_payload_RAMPING 1 3710 #define rx_x4_control0_payload_CL48_CRPAT 2 3711 #define rx_x4_control0_payload_CL48_CJPAT 3 3712 #define rx_x4_control0_payload_CL36_LONG_CRPAT 4 3713 #define rx_x4_control0_payload_CL36_SHORT_CRPAT 5 3714 3715 /**************************************************************************** 3716 * Enums: rx_x4_control0_sc 3717 */ 3718 #define rx_x4_control0_sc_S_10G_CR1 0 3719 #define rx_x4_control0_sc_S_10G_KR1 1 3720 #define rx_x4_control0_sc_S_10G_X1 2 3721 #define rx_x4_control0_sc_S_10G_HG2_CR1 4 3722 #define rx_x4_control0_sc_S_10G_HG2_KR1 5 3723 #define rx_x4_control0_sc_S_10G_HG2_X1 6 3724 #define rx_x4_control0_sc_S_20G_CR1 8 3725 #define rx_x4_control0_sc_S_20G_KR1 9 3726 #define rx_x4_control0_sc_S_20G_X1 10 3727 #define rx_x4_control0_sc_S_20G_HG2_CR1 12 3728 #define rx_x4_control0_sc_S_20G_HG2_KR1 13 3729 #define rx_x4_control0_sc_S_20G_HG2_X1 14 3730 #define rx_x4_control0_sc_S_25G_CR1 16 3731 #define rx_x4_control0_sc_S_25G_KR1 17 3732 #define rx_x4_control0_sc_S_25G_X1 18 3733 #define rx_x4_control0_sc_S_25G_HG2_CR1 20 3734 #define rx_x4_control0_sc_S_25G_HG2_KR1 21 3735 #define rx_x4_control0_sc_S_25G_HG2_X1 22 3736 #define rx_x4_control0_sc_S_20G_CR2 24 3737 #define rx_x4_control0_sc_S_20G_KR2 25 3738 #define rx_x4_control0_sc_S_20G_X2 26 3739 #define rx_x4_control0_sc_S_20G_HG2_CR2 28 3740 #define rx_x4_control0_sc_S_20G_HG2_KR2 29 3741 #define rx_x4_control0_sc_S_20G_HG2_X2 30 3742 #define rx_x4_control0_sc_S_40G_CR2 32 3743 #define rx_x4_control0_sc_S_40G_KR2 33 3744 #define rx_x4_control0_sc_S_40G_X2 34 3745 #define rx_x4_control0_sc_S_40G_HG2_CR2 36 3746 #define rx_x4_control0_sc_S_40G_HG2_KR2 37 3747 #define rx_x4_control0_sc_S_40G_HG2_X2 38 3748 #define rx_x4_control0_sc_S_40G_CR4 40 3749 #define rx_x4_control0_sc_S_40G_KR4 41 3750 #define rx_x4_control0_sc_S_40G_X4 42 3751 #define rx_x4_control0_sc_S_40G_HG2_CR4 44 3752 #define rx_x4_control0_sc_S_40G_HG2_KR4 45 3753 #define rx_x4_control0_sc_S_40G_HG2_X4 46 3754 #define rx_x4_control0_sc_S_50G_CR2 48 3755 #define rx_x4_control0_sc_S_50G_KR2 49 3756 #define rx_x4_control0_sc_S_50G_X2 50 3757 #define rx_x4_control0_sc_S_50G_HG2_CR2 52 3758 #define rx_x4_control0_sc_S_50G_HG2_KR2 53 3759 #define rx_x4_control0_sc_S_50G_HG2_X2 54 3760 #define rx_x4_control0_sc_S_50G_CR4 56 3761 #define rx_x4_control0_sc_S_50G_KR4 57 3762 #define rx_x4_control0_sc_S_50G_X4 58 3763 #define rx_x4_control0_sc_S_50G_HG2_CR4 60 3764 #define rx_x4_control0_sc_S_50G_HG2_KR4 61 3765 #define rx_x4_control0_sc_S_50G_HG2_X4 62 3766 #define rx_x4_control0_sc_S_100G_CR4 64 3767 #define rx_x4_control0_sc_S_100G_KR4 65 3768 #define rx_x4_control0_sc_S_100G_X4 66 3769 #define rx_x4_control0_sc_S_100G_HG2_CR4 68 3770 #define rx_x4_control0_sc_S_100G_HG2_KR4 69 3771 #define rx_x4_control0_sc_S_100G_HG2_X4 70 3772 #define rx_x4_control0_sc_S_CL73_20GVCO 72 3773 #define rx_x4_control0_sc_S_CL73_25GVCO 80 3774 #define rx_x4_control0_sc_S_CL36_20GVCO 88 3775 #define rx_x4_control0_sc_S_CL36_25GVCO 96 3776 3777 /**************************************************************************** 3778 * Enums: rx_x4_control0_t_fifo_modes 3779 */ 3780 #define rx_x4_control0_t_fifo_modes_T_FIFO_MODE_BYPASS 0 3781 #define rx_x4_control0_t_fifo_modes_T_FIFO_MODE_40G 1 3782 #define rx_x4_control0_t_fifo_modes_T_FIFO_MODE_100G 2 3783 #define rx_x4_control0_t_fifo_modes_T_FIFO_MODE_20G 3 3784 3785 /**************************************************************************** 3786 * Enums: rx_x4_control0_t_enc_modes 3787 */ 3788 #define rx_x4_control0_t_enc_modes_T_ENC_MODE_BYPASS 0 3789 #define rx_x4_control0_t_enc_modes_T_ENC_MODE_CL49 1 3790 #define rx_x4_control0_t_enc_modes_T_ENC_MODE_CL82 2 3791 3792 /**************************************************************************** 3793 * Enums: rx_x4_control0_btmx_mode 3794 */ 3795 #define rx_x4_control0_btmx_mode_BS_BTMX_MODE_1to1 0 3796 #define rx_x4_control0_btmx_mode_BS_BTMX_MODE_2to1 1 3797 #define rx_x4_control0_btmx_mode_BS_BTMX_MODE_5to1 2 3798 3799 /**************************************************************************** 3800 * Enums: rx_x4_control0_t_type_cl82 3801 */ 3802 #define rx_x4_control0_t_type_cl82_T_TYPE_B1 5 3803 #define rx_x4_control0_t_type_cl82_T_TYPE_C 4 3804 #define rx_x4_control0_t_type_cl82_T_TYPE_S 3 3805 #define rx_x4_control0_t_type_cl82_T_TYPE_T 2 3806 #define rx_x4_control0_t_type_cl82_T_TYPE_D 1 3807 #define rx_x4_control0_t_type_cl82_T_TYPE_E 0 3808 3809 /**************************************************************************** 3810 * Enums: rx_x4_control0_txsm_state_cl82 3811 */ 3812 #define rx_x4_control0_txsm_state_cl82_TX_HIG_END 6 3813 #define rx_x4_control0_txsm_state_cl82_TX_HIG_START 5 3814 #define rx_x4_control0_txsm_state_cl82_TX_E 4 3815 #define rx_x4_control0_txsm_state_cl82_TX_T 3 3816 #define rx_x4_control0_txsm_state_cl82_TX_D 2 3817 #define rx_x4_control0_txsm_state_cl82_TX_C 1 3818 #define rx_x4_control0_txsm_state_cl82_TX_INIT 0 3819 3820 /**************************************************************************** 3821 * Enums: rx_x4_control0_ltxsm_state_cl82 3822 */ 3823 #define rx_x4_control0_ltxsm_state_cl82_TX_HIG_END 64 3824 #define rx_x4_control0_ltxsm_state_cl82_TX_HIG_START 32 3825 #define rx_x4_control0_ltxsm_state_cl82_TX_E 16 3826 #define rx_x4_control0_ltxsm_state_cl82_TX_T 8 3827 #define rx_x4_control0_ltxsm_state_cl82_TX_D 4 3828 #define rx_x4_control0_ltxsm_state_cl82_TX_C 2 3829 #define rx_x4_control0_ltxsm_state_cl82_TX_INIT 1 3830 3831 /**************************************************************************** 3832 * Enums: rx_x4_control0_r_type_coded_cl82 3833 */ 3834 #define rx_x4_control0_r_type_coded_cl82_R_TYPE_B1 32 3835 #define rx_x4_control0_r_type_coded_cl82_R_TYPE_C 16 3836 #define rx_x4_control0_r_type_coded_cl82_R_TYPE_S 8 3837 #define rx_x4_control0_r_type_coded_cl82_R_TYPE_T 4 3838 #define rx_x4_control0_r_type_coded_cl82_R_TYPE_D 2 3839 #define rx_x4_control0_r_type_coded_cl82_R_TYPE_E 1 3840 3841 /**************************************************************************** 3842 * Enums: rx_x4_control0_rxsm_state_cl82 3843 */ 3844 #define rx_x4_control0_rxsm_state_cl82_RX_HIG_END 64 3845 #define rx_x4_control0_rxsm_state_cl82_RX_HIG_START 32 3846 #define rx_x4_control0_rxsm_state_cl82_RX_E 16 3847 #define rx_x4_control0_rxsm_state_cl82_RX_T 8 3848 #define rx_x4_control0_rxsm_state_cl82_RX_D 4 3849 #define rx_x4_control0_rxsm_state_cl82_RX_C 2 3850 #define rx_x4_control0_rxsm_state_cl82_RX_INIT 1 3851 3852 /**************************************************************************** 3853 * Enums: rx_x4_control0_deskew_state 3854 */ 3855 #define rx_x4_control0_deskew_state_ALIGN_ACQUIRED 2 3856 #define rx_x4_control0_deskew_state_LOSS_OF_ALIGNMENT 1 3857 3858 /**************************************************************************** 3859 * Enums: rx_x4_control0_os_mode_enum 3860 */ 3861 #define rx_x4_control0_os_mode_enum_OS_MODE_1 0 3862 #define rx_x4_control0_os_mode_enum_OS_MODE_2 1 3863 #define rx_x4_control0_os_mode_enum_OS_MODE_4 2 3864 #define rx_x4_control0_os_mode_enum_OS_MODE_16p5 8 3865 #define rx_x4_control0_os_mode_enum_OS_MODE_20p625 12 3866 3867 /**************************************************************************** 3868 * Enums: rx_x4_control0_scr_modes 3869 */ 3870 #define rx_x4_control0_scr_modes_T_SCR_MODE_BYPASS 0 3871 #define rx_x4_control0_scr_modes_T_SCR_MODE_CL49 1 3872 #define rx_x4_control0_scr_modes_T_SCR_MODE_40G_2_LANE 2 3873 #define rx_x4_control0_scr_modes_T_SCR_MODE_100G 3 3874 #define rx_x4_control0_scr_modes_T_SCR_MODE_20G 4 3875 #define rx_x4_control0_scr_modes_T_SCR_MODE_40G_4_LANE 5 3876 3877 /**************************************************************************** 3878 * Enums: rx_x4_control0_descr_modes 3879 */ 3880 #define rx_x4_control0_descr_modes_R_DESCR_MODE_BYPASS 0 3881 #define rx_x4_control0_descr_modes_R_DESCR_MODE_CL49 1 3882 #define rx_x4_control0_descr_modes_R_DESCR_MODE_CL82 2 3883 3884 /**************************************************************************** 3885 * Enums: rx_x4_control0_r_dec_tl_mode 3886 */ 3887 #define rx_x4_control0_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 3888 #define rx_x4_control0_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 3889 #define rx_x4_control0_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 3890 3891 /**************************************************************************** 3892 * Enums: rx_x4_control0_r_dec_fsm_mode 3893 */ 3894 #define rx_x4_control0_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 3895 #define rx_x4_control0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 3896 #define rx_x4_control0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 3897 3898 /**************************************************************************** 3899 * Enums: rx_x4_control0_r_deskew_mode 3900 */ 3901 #define rx_x4_control0_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 3902 #define rx_x4_control0_r_deskew_mode_R_DESKEW_MODE_20G 1 3903 #define rx_x4_control0_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 3904 #define rx_x4_control0_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 3905 #define rx_x4_control0_r_deskew_mode_R_DESKEW_MODE_100G 4 3906 #define rx_x4_control0_r_deskew_mode_R_DESKEW_MODE_CL49 5 3907 #define rx_x4_control0_r_deskew_mode_R_DESKEW_MODE_CL91 6 3908 3909 /**************************************************************************** 3910 * Enums: rx_x4_control0_bs_dist_modes 3911 */ 3912 #define rx_x4_control0_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 3913 #define rx_x4_control0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 3914 #define rx_x4_control0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 3915 #define rx_x4_control0_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 3916 3917 /**************************************************************************** 3918 * Enums: rx_x4_control0_cl49_t_type 3919 */ 3920 #define rx_x4_control0_cl49_t_type_BAD_T_TYPE 15 3921 #define rx_x4_control0_cl49_t_type_T_TYPE_B0 11 3922 #define rx_x4_control0_cl49_t_type_T_TYPE_OB 10 3923 #define rx_x4_control0_cl49_t_type_T_TYPE_B1 9 3924 #define rx_x4_control0_cl49_t_type_T_TYPE_DB 8 3925 #define rx_x4_control0_cl49_t_type_T_TYPE_FC 7 3926 #define rx_x4_control0_cl49_t_type_T_TYPE_TB 6 3927 #define rx_x4_control0_cl49_t_type_T_TYPE_LI 5 3928 #define rx_x4_control0_cl49_t_type_T_TYPE_C 4 3929 #define rx_x4_control0_cl49_t_type_T_TYPE_S 3 3930 #define rx_x4_control0_cl49_t_type_T_TYPE_T 2 3931 #define rx_x4_control0_cl49_t_type_T_TYPE_D 1 3932 #define rx_x4_control0_cl49_t_type_T_TYPE_E 0 3933 3934 /**************************************************************************** 3935 * Enums: rx_x4_control0_cl49_txsm_states 3936 */ 3937 #define rx_x4_control0_cl49_txsm_states_TX_HIG_END 7 3938 #define rx_x4_control0_cl49_txsm_states_TX_HIG_START 6 3939 #define rx_x4_control0_cl49_txsm_states_TX_LI 5 3940 #define rx_x4_control0_cl49_txsm_states_TX_E 4 3941 #define rx_x4_control0_cl49_txsm_states_TX_T 3 3942 #define rx_x4_control0_cl49_txsm_states_TX_D 2 3943 #define rx_x4_control0_cl49_txsm_states_TX_C 1 3944 #define rx_x4_control0_cl49_txsm_states_TX_INIT 0 3945 3946 /**************************************************************************** 3947 * Enums: rx_x4_control0_cl49_ltxsm_states 3948 */ 3949 #define rx_x4_control0_cl49_ltxsm_states_TX_HIG_END 128 3950 #define rx_x4_control0_cl49_ltxsm_states_TX_HIG_START 64 3951 #define rx_x4_control0_cl49_ltxsm_states_TX_LI 32 3952 #define rx_x4_control0_cl49_ltxsm_states_TX_E 16 3953 #define rx_x4_control0_cl49_ltxsm_states_TX_T 8 3954 #define rx_x4_control0_cl49_ltxsm_states_TX_D 4 3955 #define rx_x4_control0_cl49_ltxsm_states_TX_C 2 3956 #define rx_x4_control0_cl49_ltxsm_states_TX_INIT 1 3957 3958 /**************************************************************************** 3959 * Enums: rx_x4_control0_burst_error_mode 3960 */ 3961 #define rx_x4_control0_burst_error_mode_BURST_ERROR_11_BITS 0 3962 #define rx_x4_control0_burst_error_mode_BURST_ERROR_16_BITS 1 3963 #define rx_x4_control0_burst_error_mode_BURST_ERROR_17_BITS 2 3964 #define rx_x4_control0_burst_error_mode_BURST_ERROR_18_BITS 3 3965 #define rx_x4_control0_burst_error_mode_BURST_ERROR_19_BITS 4 3966 #define rx_x4_control0_burst_error_mode_BURST_ERROR_20_BITS 5 3967 #define rx_x4_control0_burst_error_mode_BURST_ERROR_21_BITS 6 3968 #define rx_x4_control0_burst_error_mode_BURST_ERROR_22_BITS 7 3969 #define rx_x4_control0_burst_error_mode_BURST_ERROR_23_BITS 8 3970 #define rx_x4_control0_burst_error_mode_BURST_ERROR_24_BITS 9 3971 #define rx_x4_control0_burst_error_mode_BURST_ERROR_25_BITS 10 3972 #define rx_x4_control0_burst_error_mode_BURST_ERROR_26_BITS 11 3973 #define rx_x4_control0_burst_error_mode_BURST_ERROR_27_BITS 12 3974 #define rx_x4_control0_burst_error_mode_BURST_ERROR_28_BITS 13 3975 #define rx_x4_control0_burst_error_mode_BURST_ERROR_29_BITS 14 3976 #define rx_x4_control0_burst_error_mode_BURST_ERROR_30_BITS 15 3977 #define rx_x4_control0_burst_error_mode_BURST_ERROR_31_BITS 16 3978 #define rx_x4_control0_burst_error_mode_BURST_ERROR_32_BITS 17 3979 #define rx_x4_control0_burst_error_mode_BURST_ERROR_33_BITS 18 3980 #define rx_x4_control0_burst_error_mode_BURST_ERROR_34_BITS 19 3981 #define rx_x4_control0_burst_error_mode_BURST_ERROR_35_BITS 20 3982 #define rx_x4_control0_burst_error_mode_BURST_ERROR_36_BITS 21 3983 #define rx_x4_control0_burst_error_mode_BURST_ERROR_37_BITS 22 3984 #define rx_x4_control0_burst_error_mode_BURST_ERROR_38_BITS 23 3985 #define rx_x4_control0_burst_error_mode_BURST_ERROR_39_BITS 24 3986 #define rx_x4_control0_burst_error_mode_BURST_ERROR_40_BITS 25 3987 #define rx_x4_control0_burst_error_mode_BURST_ERROR_41_BITS 26 3988 3989 /**************************************************************************** 3990 * Enums: rx_x4_control0_bermon_state 3991 */ 3992 #define rx_x4_control0_bermon_state_HI_BER 4 3993 #define rx_x4_control0_bermon_state_GOOD_BER 3 3994 #define rx_x4_control0_bermon_state_BER_TEST_SH 2 3995 #define rx_x4_control0_bermon_state_START_TIMER 1 3996 #define rx_x4_control0_bermon_state_BER_MT_INIT 0 3997 3998 /**************************************************************************** 3999 * Enums: rx_x4_control0_rxsm_state_cl49 4000 */ 4001 #define rx_x4_control0_rxsm_state_cl49_RX_HIG_END 128 4002 #define rx_x4_control0_rxsm_state_cl49_RX_HIG_START 64 4003 #define rx_x4_control0_rxsm_state_cl49_RX_LI 32 4004 #define rx_x4_control0_rxsm_state_cl49_RX_E 16 4005 #define rx_x4_control0_rxsm_state_cl49_RX_T 8 4006 #define rx_x4_control0_rxsm_state_cl49_RX_D 4 4007 #define rx_x4_control0_rxsm_state_cl49_RX_C 2 4008 #define rx_x4_control0_rxsm_state_cl49_RX_INIT 1 4009 4010 /**************************************************************************** 4011 * Enums: rx_x4_control0_r_type 4012 */ 4013 #define rx_x4_control0_r_type_BAD_R_TYPE 15 4014 #define rx_x4_control0_r_type_R_TYPE_B0 11 4015 #define rx_x4_control0_r_type_R_TYPE_OB 10 4016 #define rx_x4_control0_r_type_R_TYPE_B1 9 4017 #define rx_x4_control0_r_type_R_TYPE_DB 8 4018 #define rx_x4_control0_r_type_R_TYPE_FC 7 4019 #define rx_x4_control0_r_type_R_TYPE_TB 6 4020 #define rx_x4_control0_r_type_R_TYPE_LI 5 4021 #define rx_x4_control0_r_type_R_TYPE_C 4 4022 #define rx_x4_control0_r_type_R_TYPE_S 3 4023 #define rx_x4_control0_r_type_R_TYPE_T 2 4024 #define rx_x4_control0_r_type_R_TYPE_D 1 4025 #define rx_x4_control0_r_type_R_TYPE_E 0 4026 4027 /**************************************************************************** 4028 * Enums: rx_x4_control0_am_lock_state 4029 */ 4030 #define rx_x4_control0_am_lock_state_INVALID_AM 512 4031 #define rx_x4_control0_am_lock_state_GOOD_AM 256 4032 #define rx_x4_control0_am_lock_state_COMP_AM 128 4033 #define rx_x4_control0_am_lock_state_TIMER_2 64 4034 #define rx_x4_control0_am_lock_state_AM_2_GOOD 32 4035 #define rx_x4_control0_am_lock_state_COMP_2ND 16 4036 #define rx_x4_control0_am_lock_state_TIMER_1 8 4037 #define rx_x4_control0_am_lock_state_FIND_1ST 4 4038 #define rx_x4_control0_am_lock_state_AM_RESET_CNT 2 4039 #define rx_x4_control0_am_lock_state_AM_LOCK_INIT 1 4040 4041 /**************************************************************************** 4042 * Enums: rx_x4_control0_msg_selector 4043 */ 4044 #define rx_x4_control0_msg_selector_RESERVED 0 4045 #define rx_x4_control0_msg_selector_VALUE_802p3 1 4046 #define rx_x4_control0_msg_selector_VALUE_802p9 2 4047 #define rx_x4_control0_msg_selector_VALUE_802p5 3 4048 #define rx_x4_control0_msg_selector_VALUE_1394 4 4049 4050 /**************************************************************************** 4051 * Enums: rx_x4_control0_synce_enum 4052 */ 4053 #define rx_x4_control0_synce_enum_SYNCE_NO_DIV 0 4054 #define rx_x4_control0_synce_enum_SYNCE_DIV_7 1 4055 #define rx_x4_control0_synce_enum_SYNCE_DIV_11 2 4056 4057 /**************************************************************************** 4058 * Enums: rx_x4_control0_synce_enum_stage0 4059 */ 4060 #define rx_x4_control0_synce_enum_stage0_SYNCE_NO_DIV 0 4061 #define rx_x4_control0_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 4062 #define rx_x4_control0_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 4063 4064 /**************************************************************************** 4065 * Enums: rx_x4_control0_cl91_sync_state 4066 */ 4067 #define rx_x4_control0_cl91_sync_state_FIND_1ST 0 4068 #define rx_x4_control0_cl91_sync_state_COUNT_NEXT 1 4069 #define rx_x4_control0_cl91_sync_state_COMP_2ND 2 4070 #define rx_x4_control0_cl91_sync_state_TWO_GOOD 3 4071 4072 /**************************************************************************** 4073 * Enums: rx_x4_control0_cl91_algn_state 4074 */ 4075 #define rx_x4_control0_cl91_algn_state_LOSS_OF_ALIGNMENT 0 4076 #define rx_x4_control0_cl91_algn_state_DESKEW 1 4077 #define rx_x4_control0_cl91_algn_state_DESKEW_FAIL 2 4078 #define rx_x4_control0_cl91_algn_state_ALIGN_ACQUIRED 3 4079 #define rx_x4_control0_cl91_algn_state_CW_GOOD 4 4080 #define rx_x4_control0_cl91_algn_state_CW_BAD 5 4081 #define rx_x4_control0_cl91_algn_state_THREE_BAD 6 4082 4083 /**************************************************************************** 4084 * Enums: rx_x4_control0_fec_sel 4085 */ 4086 #define rx_x4_control0_fec_sel_NO_FEC 0 4087 #define rx_x4_control0_fec_sel_FEC_CL74 1 4088 #define rx_x4_control0_fec_sel_FEC_CL91 2 4089 4090 /**************************************************************************** 4091 * Enums: rx_x4_fec_control_cl36TxEEEStates_l 4092 */ 4093 #define rx_x4_fec_control_cl36TxEEEStates_l_TX_REFRESH 8 4094 #define rx_x4_fec_control_cl36TxEEEStates_l_TX_QUIET 4 4095 #define rx_x4_fec_control_cl36TxEEEStates_l_TX_SLEEP 2 4096 #define rx_x4_fec_control_cl36TxEEEStates_l_TX_ACTIVE 1 4097 4098 /**************************************************************************** 4099 * Enums: rx_x4_fec_control_cl36TxEEEStates_c 4100 */ 4101 #define rx_x4_fec_control_cl36TxEEEStates_c_TX_REFRESH 3 4102 #define rx_x4_fec_control_cl36TxEEEStates_c_TX_QUIET 2 4103 #define rx_x4_fec_control_cl36TxEEEStates_c_TX_SLEEP 1 4104 #define rx_x4_fec_control_cl36TxEEEStates_c_TX_ACTIVE 0 4105 4106 /**************************************************************************** 4107 * Enums: rx_x4_fec_control_cl49TxEEEStates_l 4108 */ 4109 #define rx_x4_fec_control_cl49TxEEEStates_l_SCR_RESET_2 64 4110 #define rx_x4_fec_control_cl49TxEEEStates_l_SCR_RESET_1 32 4111 #define rx_x4_fec_control_cl49TxEEEStates_l_TX_WAKE 16 4112 #define rx_x4_fec_control_cl49TxEEEStates_l_TX_REFRESH 8 4113 #define rx_x4_fec_control_cl49TxEEEStates_l_TX_QUIET 4 4114 #define rx_x4_fec_control_cl49TxEEEStates_l_TX_SLEEP 2 4115 #define rx_x4_fec_control_cl49TxEEEStates_l_TX_ACTIVE 1 4116 4117 /**************************************************************************** 4118 * Enums: rx_x4_fec_control_fec_req_enum 4119 */ 4120 #define rx_x4_fec_control_fec_req_enum_FEC_not_supported 0 4121 #define rx_x4_fec_control_fec_req_enum_FEC_supported_but_not_requested 1 4122 #define rx_x4_fec_control_fec_req_enum_invalid_setting 2 4123 #define rx_x4_fec_control_fec_req_enum_FEC_supported_and_requested 3 4124 4125 /**************************************************************************** 4126 * Enums: rx_x4_fec_control_cl73_pause_enum 4127 */ 4128 #define rx_x4_fec_control_cl73_pause_enum_No_PAUSE_ability 0 4129 #define rx_x4_fec_control_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 4130 #define rx_x4_fec_control_cl73_pause_enum_Symmetric_PAUSE_ability 1 4131 #define rx_x4_fec_control_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 4132 4133 /**************************************************************************** 4134 * Enums: rx_x4_fec_control_cl49TxEEEStates_c 4135 */ 4136 #define rx_x4_fec_control_cl49TxEEEStates_c_SCR_RESET_2 6 4137 #define rx_x4_fec_control_cl49TxEEEStates_c_SCR_RESET_1 5 4138 #define rx_x4_fec_control_cl49TxEEEStates_c_TX_WAKE 4 4139 #define rx_x4_fec_control_cl49TxEEEStates_c_TX_REFRESH 3 4140 #define rx_x4_fec_control_cl49TxEEEStates_c_TX_QUIET 2 4141 #define rx_x4_fec_control_cl49TxEEEStates_c_TX_SLEEP 1 4142 #define rx_x4_fec_control_cl49TxEEEStates_c_TX_ACTIVE 0 4143 4144 /**************************************************************************** 4145 * Enums: rx_x4_fec_control_cl36RxEEEStates_l 4146 */ 4147 #define rx_x4_fec_control_cl36RxEEEStates_l_RX_LINK_FAIL 32 4148 #define rx_x4_fec_control_cl36RxEEEStates_l_RX_WTF 16 4149 #define rx_x4_fec_control_cl36RxEEEStates_l_RX_WAKE 8 4150 #define rx_x4_fec_control_cl36RxEEEStates_l_RX_QUIET 4 4151 #define rx_x4_fec_control_cl36RxEEEStates_l_RX_SLEEP 2 4152 #define rx_x4_fec_control_cl36RxEEEStates_l_RX_ACTIVE 1 4153 4154 /**************************************************************************** 4155 * Enums: rx_x4_fec_control_cl36RxEEEStates_c 4156 */ 4157 #define rx_x4_fec_control_cl36RxEEEStates_c_RX_LINK_FAIL 5 4158 #define rx_x4_fec_control_cl36RxEEEStates_c_RX_WTF 4 4159 #define rx_x4_fec_control_cl36RxEEEStates_c_RX_WAKE 3 4160 #define rx_x4_fec_control_cl36RxEEEStates_c_RX_QUIET 2 4161 #define rx_x4_fec_control_cl36RxEEEStates_c_RX_SLEEP 1 4162 #define rx_x4_fec_control_cl36RxEEEStates_c_RX_ACTIVE 0 4163 4164 /**************************************************************************** 4165 * Enums: rx_x4_fec_control_cl49RxEEEStates_l 4166 */ 4167 #define rx_x4_fec_control_cl49RxEEEStates_l_RX_LINK_FAIL 32 4168 #define rx_x4_fec_control_cl49RxEEEStates_l_RX_WTF 16 4169 #define rx_x4_fec_control_cl49RxEEEStates_l_RX_WAKE 8 4170 #define rx_x4_fec_control_cl49RxEEEStates_l_RX_QUIET 4 4171 #define rx_x4_fec_control_cl49RxEEEStates_l_RX_SLEEP 2 4172 #define rx_x4_fec_control_cl49RxEEEStates_l_RX_ACTIVE 1 4173 4174 /**************************************************************************** 4175 * Enums: rx_x4_fec_control_cl49RxEEEStates_c 4176 */ 4177 #define rx_x4_fec_control_cl49RxEEEStates_c_RX_LINK_FAIL 5 4178 #define rx_x4_fec_control_cl49RxEEEStates_c_RX_WTF 4 4179 #define rx_x4_fec_control_cl49RxEEEStates_c_RX_WAKE 3 4180 #define rx_x4_fec_control_cl49RxEEEStates_c_RX_QUIET 2 4181 #define rx_x4_fec_control_cl49RxEEEStates_c_RX_SLEEP 1 4182 #define rx_x4_fec_control_cl49RxEEEStates_c_RX_ACTIVE 0 4183 4184 /**************************************************************************** 4185 * Enums: rx_x4_fec_control_cl48TxEEEStates_l 4186 */ 4187 #define rx_x4_fec_control_cl48TxEEEStates_l_TX_REFRESH 8 4188 #define rx_x4_fec_control_cl48TxEEEStates_l_TX_QUIET 4 4189 #define rx_x4_fec_control_cl48TxEEEStates_l_TX_SLEEP 2 4190 #define rx_x4_fec_control_cl48TxEEEStates_l_TX_ACTIVE 1 4191 4192 /**************************************************************************** 4193 * Enums: rx_x4_fec_control_cl48TxEEEStates_c 4194 */ 4195 #define rx_x4_fec_control_cl48TxEEEStates_c_TX_REFRESH 3 4196 #define rx_x4_fec_control_cl48TxEEEStates_c_TX_QUIET 2 4197 #define rx_x4_fec_control_cl48TxEEEStates_c_TX_SLEEP 1 4198 #define rx_x4_fec_control_cl48TxEEEStates_c_TX_ACTIVE 0 4199 4200 /**************************************************************************** 4201 * Enums: rx_x4_fec_control_cl48RxEEEStates_l 4202 */ 4203 #define rx_x4_fec_control_cl48RxEEEStates_l_RX_LINK_FAIL 32 4204 #define rx_x4_fec_control_cl48RxEEEStates_l_RX_WAKE 16 4205 #define rx_x4_fec_control_cl48RxEEEStates_l_RX_QUIET 8 4206 #define rx_x4_fec_control_cl48RxEEEStates_l_RX_DEACT 4 4207 #define rx_x4_fec_control_cl48RxEEEStates_l_RX_SLEEP 2 4208 #define rx_x4_fec_control_cl48RxEEEStates_l_RX_ACTIVE 1 4209 4210 /**************************************************************************** 4211 * Enums: rx_x4_fec_control_cl48RxEEEStates_c 4212 */ 4213 #define rx_x4_fec_control_cl48RxEEEStates_c_RX_LINK_FAIL 5 4214 #define rx_x4_fec_control_cl48RxEEEStates_c_RX_WAKE 4 4215 #define rx_x4_fec_control_cl48RxEEEStates_c_RX_QUIET 3 4216 #define rx_x4_fec_control_cl48RxEEEStates_c_RX_DEACT 2 4217 #define rx_x4_fec_control_cl48RxEEEStates_c_RX_SLEEP 1 4218 #define rx_x4_fec_control_cl48RxEEEStates_c_RX_ACTIVE 0 4219 4220 /**************************************************************************** 4221 * Enums: rx_x4_fec_control_IQP_Options 4222 */ 4223 #define rx_x4_fec_control_IQP_Options_i50uA 0 4224 #define rx_x4_fec_control_IQP_Options_i100uA 1 4225 #define rx_x4_fec_control_IQP_Options_i150uA 2 4226 #define rx_x4_fec_control_IQP_Options_i200uA 3 4227 #define rx_x4_fec_control_IQP_Options_i250uA 4 4228 #define rx_x4_fec_control_IQP_Options_i300uA 5 4229 #define rx_x4_fec_control_IQP_Options_i350uA 6 4230 #define rx_x4_fec_control_IQP_Options_i400uA 7 4231 #define rx_x4_fec_control_IQP_Options_i450uA 8 4232 #define rx_x4_fec_control_IQP_Options_i500uA 9 4233 #define rx_x4_fec_control_IQP_Options_i550uA 10 4234 #define rx_x4_fec_control_IQP_Options_i600uA 11 4235 #define rx_x4_fec_control_IQP_Options_i650uA 12 4236 #define rx_x4_fec_control_IQP_Options_i700uA 13 4237 #define rx_x4_fec_control_IQP_Options_i750uA 14 4238 #define rx_x4_fec_control_IQP_Options_i800uA 15 4239 4240 /**************************************************************************** 4241 * Enums: rx_x4_fec_control_IDriver_Options 4242 */ 4243 #define rx_x4_fec_control_IDriver_Options_v680mV 0 4244 #define rx_x4_fec_control_IDriver_Options_v730mV 1 4245 #define rx_x4_fec_control_IDriver_Options_v780mV 2 4246 #define rx_x4_fec_control_IDriver_Options_v830mV 3 4247 #define rx_x4_fec_control_IDriver_Options_v880mV 4 4248 #define rx_x4_fec_control_IDriver_Options_v930mV 5 4249 #define rx_x4_fec_control_IDriver_Options_v980mV 6 4250 #define rx_x4_fec_control_IDriver_Options_v1010mV 7 4251 #define rx_x4_fec_control_IDriver_Options_v1040mV 8 4252 #define rx_x4_fec_control_IDriver_Options_v1060mV 9 4253 #define rx_x4_fec_control_IDriver_Options_v1070mV 10 4254 #define rx_x4_fec_control_IDriver_Options_v1080mV 11 4255 #define rx_x4_fec_control_IDriver_Options_v1085mV 12 4256 #define rx_x4_fec_control_IDriver_Options_v1090mV 13 4257 #define rx_x4_fec_control_IDriver_Options_v1095mV 14 4258 #define rx_x4_fec_control_IDriver_Options_v1100mV 15 4259 4260 /**************************************************************************** 4261 * Enums: rx_x4_fec_control_operationModes 4262 */ 4263 #define rx_x4_fec_control_operationModes_XGXS 0 4264 #define rx_x4_fec_control_operationModes_XGXG_nCC 1 4265 #define rx_x4_fec_control_operationModes_Indlane_OS8 4 4266 #define rx_x4_fec_control_operationModes_IndLane_OS5 5 4267 #define rx_x4_fec_control_operationModes_PCI 7 4268 #define rx_x4_fec_control_operationModes_XGXS_nLQ 8 4269 #define rx_x4_fec_control_operationModes_XGXS_nLQnCC 9 4270 #define rx_x4_fec_control_operationModes_PBypass 10 4271 #define rx_x4_fec_control_operationModes_PBypass_nDSK 11 4272 #define rx_x4_fec_control_operationModes_ComboCoreMode 12 4273 #define rx_x4_fec_control_operationModes_Clocks_off 15 4274 4275 /**************************************************************************** 4276 * Enums: rx_x4_fec_control_actualSpeeds 4277 */ 4278 #define rx_x4_fec_control_actualSpeeds_dr_10M 0 4279 #define rx_x4_fec_control_actualSpeeds_dr_100M 1 4280 #define rx_x4_fec_control_actualSpeeds_dr_1G 2 4281 #define rx_x4_fec_control_actualSpeeds_dr_2p5G 3 4282 #define rx_x4_fec_control_actualSpeeds_dr_5G_X4 4 4283 #define rx_x4_fec_control_actualSpeeds_dr_6G_X4 5 4284 #define rx_x4_fec_control_actualSpeeds_dr_10G_HiG 6 4285 #define rx_x4_fec_control_actualSpeeds_dr_10G_CX4 7 4286 #define rx_x4_fec_control_actualSpeeds_dr_12G_HiG 8 4287 #define rx_x4_fec_control_actualSpeeds_dr_12p5G_X4 9 4288 #define rx_x4_fec_control_actualSpeeds_dr_13G_X4 10 4289 #define rx_x4_fec_control_actualSpeeds_dr_15G_X4 11 4290 #define rx_x4_fec_control_actualSpeeds_dr_16G_X4 12 4291 #define rx_x4_fec_control_actualSpeeds_dr_1G_KX 13 4292 #define rx_x4_fec_control_actualSpeeds_dr_10G_KX4 14 4293 #define rx_x4_fec_control_actualSpeeds_dr_10G_KR 15 4294 #define rx_x4_fec_control_actualSpeeds_dr_5G 16 4295 #define rx_x4_fec_control_actualSpeeds_dr_6p4G 17 4296 #define rx_x4_fec_control_actualSpeeds_dr_20G_X4 18 4297 #define rx_x4_fec_control_actualSpeeds_dr_21G_X4 19 4298 #define rx_x4_fec_control_actualSpeeds_dr_25G_X4 20 4299 #define rx_x4_fec_control_actualSpeeds_dr_10G_HiG_DXGXS 21 4300 #define rx_x4_fec_control_actualSpeeds_dr_10G_DXGXS 22 4301 #define rx_x4_fec_control_actualSpeeds_dr_10p5G_HiG_DXGXS 23 4302 #define rx_x4_fec_control_actualSpeeds_dr_10p5G_DXGXS 24 4303 #define rx_x4_fec_control_actualSpeeds_dr_12p773G_HiG_DXGXS 25 4304 #define rx_x4_fec_control_actualSpeeds_dr_12p773G_DXGXS 26 4305 #define rx_x4_fec_control_actualSpeeds_dr_10G_XFI 27 4306 #define rx_x4_fec_control_actualSpeeds_dr_40G 28 4307 #define rx_x4_fec_control_actualSpeeds_dr_20G_HiG_DXGXS 29 4308 #define rx_x4_fec_control_actualSpeeds_dr_20G_DXGXS 30 4309 #define rx_x4_fec_control_actualSpeeds_dr_10G_SFI 31 4310 #define rx_x4_fec_control_actualSpeeds_dr_31p5G 32 4311 #define rx_x4_fec_control_actualSpeeds_dr_32p7G 33 4312 #define rx_x4_fec_control_actualSpeeds_dr_20G_SCR 34 4313 #define rx_x4_fec_control_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 4314 #define rx_x4_fec_control_actualSpeeds_dr_10G_DXGXS_SCR 36 4315 #define rx_x4_fec_control_actualSpeeds_dr_12G_R2 37 4316 #define rx_x4_fec_control_actualSpeeds_dr_10G_X2 38 4317 #define rx_x4_fec_control_actualSpeeds_dr_40G_KR4 39 4318 #define rx_x4_fec_control_actualSpeeds_dr_40G_CR4 40 4319 #define rx_x4_fec_control_actualSpeeds_dr_100G_CR10 41 4320 #define rx_x4_fec_control_actualSpeeds_dr_15p75G_DXGXS 44 4321 #define rx_x4_fec_control_actualSpeeds_dr_20G_KR2 57 4322 #define rx_x4_fec_control_actualSpeeds_dr_20G_CR2 58 4323 4324 /**************************************************************************** 4325 * Enums: rx_x4_fec_control_actualSpeedsMisc1 4326 */ 4327 #define rx_x4_fec_control_actualSpeedsMisc1_dr_2500BRCM_X1 16 4328 #define rx_x4_fec_control_actualSpeedsMisc1_dr_5000BRCM_X4 17 4329 #define rx_x4_fec_control_actualSpeedsMisc1_dr_6000BRCM_X4 18 4330 #define rx_x4_fec_control_actualSpeedsMisc1_dr_10GHiGig_X4 19 4331 #define rx_x4_fec_control_actualSpeedsMisc1_dr_10GBASE_CX4 20 4332 #define rx_x4_fec_control_actualSpeedsMisc1_dr_12GHiGig_X4 21 4333 #define rx_x4_fec_control_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 4334 #define rx_x4_fec_control_actualSpeedsMisc1_dr_13GHiGig_X4 23 4335 #define rx_x4_fec_control_actualSpeedsMisc1_dr_15GHiGig_X4 24 4336 #define rx_x4_fec_control_actualSpeedsMisc1_dr_16GHiGig_X4 25 4337 #define rx_x4_fec_control_actualSpeedsMisc1_dr_5000BRCM_X1 26 4338 #define rx_x4_fec_control_actualSpeedsMisc1_dr_6363BRCM_X1 27 4339 #define rx_x4_fec_control_actualSpeedsMisc1_dr_20GHiGig_X4 28 4340 #define rx_x4_fec_control_actualSpeedsMisc1_dr_21GHiGig_X4 29 4341 #define rx_x4_fec_control_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 4342 #define rx_x4_fec_control_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 4343 4344 /**************************************************************************** 4345 * Enums: rx_x4_fec_control_IndLaneModes 4346 */ 4347 #define rx_x4_fec_control_IndLaneModes_SWSDR_div2 0 4348 #define rx_x4_fec_control_IndLaneModes_SWSDR_div1 1 4349 #define rx_x4_fec_control_IndLaneModes_DWSDR_div2 2 4350 #define rx_x4_fec_control_IndLaneModes_DWSDR_div1 3 4351 4352 /**************************************************************************** 4353 * Enums: rx_x4_fec_control_prbsSelect 4354 */ 4355 #define rx_x4_fec_control_prbsSelect_prbs7 0 4356 #define rx_x4_fec_control_prbsSelect_prbs15 1 4357 #define rx_x4_fec_control_prbsSelect_prbs23 2 4358 #define rx_x4_fec_control_prbsSelect_prbs31 3 4359 4360 /**************************************************************************** 4361 * Enums: rx_x4_fec_control_vcoDivider 4362 */ 4363 #define rx_x4_fec_control_vcoDivider_div32 0 4364 #define rx_x4_fec_control_vcoDivider_div36 1 4365 #define rx_x4_fec_control_vcoDivider_div40 2 4366 #define rx_x4_fec_control_vcoDivider_div42 3 4367 #define rx_x4_fec_control_vcoDivider_div48 4 4368 #define rx_x4_fec_control_vcoDivider_div50 5 4369 #define rx_x4_fec_control_vcoDivider_div52 6 4370 #define rx_x4_fec_control_vcoDivider_div54 7 4371 #define rx_x4_fec_control_vcoDivider_div60 8 4372 #define rx_x4_fec_control_vcoDivider_div64 9 4373 #define rx_x4_fec_control_vcoDivider_div66 10 4374 #define rx_x4_fec_control_vcoDivider_div68 11 4375 #define rx_x4_fec_control_vcoDivider_div70 12 4376 #define rx_x4_fec_control_vcoDivider_div80 13 4377 #define rx_x4_fec_control_vcoDivider_div92 14 4378 #define rx_x4_fec_control_vcoDivider_div100 15 4379 4380 /**************************************************************************** 4381 * Enums: rx_x4_fec_control_refClkSelect 4382 */ 4383 #define rx_x4_fec_control_refClkSelect_clk_25MHz 0 4384 #define rx_x4_fec_control_refClkSelect_clk_100MHz 1 4385 #define rx_x4_fec_control_refClkSelect_clk_125MHz 2 4386 #define rx_x4_fec_control_refClkSelect_clk_156p25MHz 3 4387 #define rx_x4_fec_control_refClkSelect_clk_187p5MHz 4 4388 #define rx_x4_fec_control_refClkSelect_clk_161p25Mhz 5 4389 #define rx_x4_fec_control_refClkSelect_clk_50Mhz 6 4390 #define rx_x4_fec_control_refClkSelect_clk_106p25Mhz 7 4391 4392 /**************************************************************************** 4393 * Enums: rx_x4_fec_control_aerMMDdevTypeSelect 4394 */ 4395 #define rx_x4_fec_control_aerMMDdevTypeSelect_combo_core 0 4396 #define rx_x4_fec_control_aerMMDdevTypeSelect_PMA_PMD 1 4397 #define rx_x4_fec_control_aerMMDdevTypeSelect_PCS 3 4398 #define rx_x4_fec_control_aerMMDdevTypeSelect_PHY 4 4399 #define rx_x4_fec_control_aerMMDdevTypeSelect_DTE 5 4400 #define rx_x4_fec_control_aerMMDdevTypeSelect_CL73_AN 7 4401 4402 /**************************************************************************** 4403 * Enums: rx_x4_fec_control_aerMMDportSelect 4404 */ 4405 #define rx_x4_fec_control_aerMMDportSelect_ln0 0 4406 #define rx_x4_fec_control_aerMMDportSelect_ln1 1 4407 #define rx_x4_fec_control_aerMMDportSelect_ln2 2 4408 #define rx_x4_fec_control_aerMMDportSelect_ln3 3 4409 #define rx_x4_fec_control_aerMMDportSelect_BCST_ln0_1_2_3 511 4410 #define rx_x4_fec_control_aerMMDportSelect_BCST_ln0_1 512 4411 #define rx_x4_fec_control_aerMMDportSelect_BCST_ln2_3 513 4412 4413 /**************************************************************************** 4414 * Enums: rx_x4_fec_control_firmwareModeSelect 4415 */ 4416 #define rx_x4_fec_control_firmwareModeSelect_DEFAULT 0 4417 #define rx_x4_fec_control_firmwareModeSelect_SFP_OPT_LR 1 4418 #define rx_x4_fec_control_firmwareModeSelect_SFP_DAC 2 4419 #define rx_x4_fec_control_firmwareModeSelect_XLAUI 3 4420 #define rx_x4_fec_control_firmwareModeSelect_LONG_CH_6G 4 4421 4422 /**************************************************************************** 4423 * Enums: rx_x4_fec_control_tempIdxSelect 4424 */ 4425 #define rx_x4_fec_control_tempIdxSelect_LTE__22p9C 15 4426 #define rx_x4_fec_control_tempIdxSelect_LTE__12p6C 14 4427 #define rx_x4_fec_control_tempIdxSelect_LTE__3p0C 13 4428 #define rx_x4_fec_control_tempIdxSelect_LTE_6p7C 12 4429 #define rx_x4_fec_control_tempIdxSelect_LTE_16p4C 11 4430 #define rx_x4_fec_control_tempIdxSelect_LTE_26p6C 10 4431 #define rx_x4_fec_control_tempIdxSelect_LTE_36p3C 9 4432 #define rx_x4_fec_control_tempIdxSelect_LTE_46p0C 8 4433 #define rx_x4_fec_control_tempIdxSelect_LTE_56p2C 7 4434 #define rx_x4_fec_control_tempIdxSelect_LTE_65p9C 6 4435 #define rx_x4_fec_control_tempIdxSelect_LTE_75p6C 5 4436 #define rx_x4_fec_control_tempIdxSelect_LTE_85p3C 4 4437 #define rx_x4_fec_control_tempIdxSelect_LTE_95p5C 3 4438 #define rx_x4_fec_control_tempIdxSelect_LTE_105p2C 2 4439 #define rx_x4_fec_control_tempIdxSelect_LTE_114p9C 1 4440 #define rx_x4_fec_control_tempIdxSelect_LTE_125p1C 0 4441 4442 /**************************************************************************** 4443 * Enums: rx_x4_fec_control_port_mode 4444 */ 4445 #define rx_x4_fec_control_port_mode_QUAD_PORT 0 4446 #define rx_x4_fec_control_port_mode_TRI_1_PORT 1 4447 #define rx_x4_fec_control_port_mode_TRI_2_PORT 2 4448 #define rx_x4_fec_control_port_mode_DUAL_PORT 3 4449 #define rx_x4_fec_control_port_mode_SINGLE_PORT 4 4450 4451 /**************************************************************************** 4452 * Enums: rx_x4_fec_control_rev_letter_enum 4453 */ 4454 #define rx_x4_fec_control_rev_letter_enum_REV_A 0 4455 #define rx_x4_fec_control_rev_letter_enum_REV_B 1 4456 #define rx_x4_fec_control_rev_letter_enum_REV_C 2 4457 #define rx_x4_fec_control_rev_letter_enum_REV_D 3 4458 4459 /**************************************************************************** 4460 * Enums: rx_x4_fec_control_rev_number_enum 4461 */ 4462 #define rx_x4_fec_control_rev_number_enum_REV_0 0 4463 #define rx_x4_fec_control_rev_number_enum_REV_1 1 4464 #define rx_x4_fec_control_rev_number_enum_REV_2 2 4465 #define rx_x4_fec_control_rev_number_enum_REV_3 3 4466 #define rx_x4_fec_control_rev_number_enum_REV_4 4 4467 #define rx_x4_fec_control_rev_number_enum_REV_5 5 4468 #define rx_x4_fec_control_rev_number_enum_REV_6 6 4469 #define rx_x4_fec_control_rev_number_enum_REV_7 7 4470 4471 /**************************************************************************** 4472 * Enums: rx_x4_fec_control_bonding_enum 4473 */ 4474 #define rx_x4_fec_control_bonding_enum_WIRE_BOND 0 4475 #define rx_x4_fec_control_bonding_enum_FLIP_CHIP 1 4476 4477 /**************************************************************************** 4478 * Enums: rx_x4_fec_control_tech_process 4479 */ 4480 #define rx_x4_fec_control_tech_process_PROCESS_90NM 0 4481 #define rx_x4_fec_control_tech_process_PROCESS_65NM 1 4482 #define rx_x4_fec_control_tech_process_PROCESS_40NM 2 4483 #define rx_x4_fec_control_tech_process_PROCESS_28NM 3 4484 4485 /**************************************************************************** 4486 * Enums: rx_x4_fec_control_model_num 4487 */ 4488 #define rx_x4_fec_control_model_num_SERDES_CL73 0 4489 #define rx_x4_fec_control_model_num_XGXS_16G 1 4490 #define rx_x4_fec_control_model_num_HYPERCORE 2 4491 #define rx_x4_fec_control_model_num_HYPERLITE 3 4492 #define rx_x4_fec_control_model_num_PCIE_G2_PIPE 4 4493 #define rx_x4_fec_control_model_num_SERDES_1p25GBd 5 4494 #define rx_x4_fec_control_model_num_SATA2 6 4495 #define rx_x4_fec_control_model_num_QSGMII 7 4496 #define rx_x4_fec_control_model_num_XGXS10G 8 4497 #define rx_x4_fec_control_model_num_WARPCORE 9 4498 #define rx_x4_fec_control_model_num_XFICORE 10 4499 #define rx_x4_fec_control_model_num_RXFI 11 4500 #define rx_x4_fec_control_model_num_WARPLITE 12 4501 #define rx_x4_fec_control_model_num_PENTACORE 13 4502 #define rx_x4_fec_control_model_num_ESM 14 4503 #define rx_x4_fec_control_model_num_QUAD_SGMII 15 4504 #define rx_x4_fec_control_model_num_WARPCORE_3 16 4505 #define rx_x4_fec_control_model_num_TSC 17 4506 #define rx_x4_fec_control_model_num_TSC4E 18 4507 #define rx_x4_fec_control_model_num_TSC12E 19 4508 #define rx_x4_fec_control_model_num_TSC4F 20 4509 #define rx_x4_fec_control_model_num_XGXS_CL73_90NM 29 4510 #define rx_x4_fec_control_model_num_SERDES_CL73_90NM 30 4511 #define rx_x4_fec_control_model_num_WARPCORE3 32 4512 #define rx_x4_fec_control_model_num_WARPCORE4_TSC 33 4513 #define rx_x4_fec_control_model_num_RXAUI 34 4514 4515 /**************************************************************************** 4516 * Enums: rx_x4_fec_control_payload 4517 */ 4518 #define rx_x4_fec_control_payload_REPEAT_2_BYTES 0 4519 #define rx_x4_fec_control_payload_RAMPING 1 4520 #define rx_x4_fec_control_payload_CL48_CRPAT 2 4521 #define rx_x4_fec_control_payload_CL48_CJPAT 3 4522 #define rx_x4_fec_control_payload_CL36_LONG_CRPAT 4 4523 #define rx_x4_fec_control_payload_CL36_SHORT_CRPAT 5 4524 4525 /**************************************************************************** 4526 * Enums: rx_x4_fec_control_sc 4527 */ 4528 #define rx_x4_fec_control_sc_S_10G_CR1 0 4529 #define rx_x4_fec_control_sc_S_10G_KR1 1 4530 #define rx_x4_fec_control_sc_S_10G_X1 2 4531 #define rx_x4_fec_control_sc_S_10G_HG2_CR1 4 4532 #define rx_x4_fec_control_sc_S_10G_HG2_KR1 5 4533 #define rx_x4_fec_control_sc_S_10G_HG2_X1 6 4534 #define rx_x4_fec_control_sc_S_20G_CR1 8 4535 #define rx_x4_fec_control_sc_S_20G_KR1 9 4536 #define rx_x4_fec_control_sc_S_20G_X1 10 4537 #define rx_x4_fec_control_sc_S_20G_HG2_CR1 12 4538 #define rx_x4_fec_control_sc_S_20G_HG2_KR1 13 4539 #define rx_x4_fec_control_sc_S_20G_HG2_X1 14 4540 #define rx_x4_fec_control_sc_S_25G_CR1 16 4541 #define rx_x4_fec_control_sc_S_25G_KR1 17 4542 #define rx_x4_fec_control_sc_S_25G_X1 18 4543 #define rx_x4_fec_control_sc_S_25G_HG2_CR1 20 4544 #define rx_x4_fec_control_sc_S_25G_HG2_KR1 21 4545 #define rx_x4_fec_control_sc_S_25G_HG2_X1 22 4546 #define rx_x4_fec_control_sc_S_20G_CR2 24 4547 #define rx_x4_fec_control_sc_S_20G_KR2 25 4548 #define rx_x4_fec_control_sc_S_20G_X2 26 4549 #define rx_x4_fec_control_sc_S_20G_HG2_CR2 28 4550 #define rx_x4_fec_control_sc_S_20G_HG2_KR2 29 4551 #define rx_x4_fec_control_sc_S_20G_HG2_X2 30 4552 #define rx_x4_fec_control_sc_S_40G_CR2 32 4553 #define rx_x4_fec_control_sc_S_40G_KR2 33 4554 #define rx_x4_fec_control_sc_S_40G_X2 34 4555 #define rx_x4_fec_control_sc_S_40G_HG2_CR2 36 4556 #define rx_x4_fec_control_sc_S_40G_HG2_KR2 37 4557 #define rx_x4_fec_control_sc_S_40G_HG2_X2 38 4558 #define rx_x4_fec_control_sc_S_40G_CR4 40 4559 #define rx_x4_fec_control_sc_S_40G_KR4 41 4560 #define rx_x4_fec_control_sc_S_40G_X4 42 4561 #define rx_x4_fec_control_sc_S_40G_HG2_CR4 44 4562 #define rx_x4_fec_control_sc_S_40G_HG2_KR4 45 4563 #define rx_x4_fec_control_sc_S_40G_HG2_X4 46 4564 #define rx_x4_fec_control_sc_S_50G_CR2 48 4565 #define rx_x4_fec_control_sc_S_50G_KR2 49 4566 #define rx_x4_fec_control_sc_S_50G_X2 50 4567 #define rx_x4_fec_control_sc_S_50G_HG2_CR2 52 4568 #define rx_x4_fec_control_sc_S_50G_HG2_KR2 53 4569 #define rx_x4_fec_control_sc_S_50G_HG2_X2 54 4570 #define rx_x4_fec_control_sc_S_50G_CR4 56 4571 #define rx_x4_fec_control_sc_S_50G_KR4 57 4572 #define rx_x4_fec_control_sc_S_50G_X4 58 4573 #define rx_x4_fec_control_sc_S_50G_HG2_CR4 60 4574 #define rx_x4_fec_control_sc_S_50G_HG2_KR4 61 4575 #define rx_x4_fec_control_sc_S_50G_HG2_X4 62 4576 #define rx_x4_fec_control_sc_S_100G_CR4 64 4577 #define rx_x4_fec_control_sc_S_100G_KR4 65 4578 #define rx_x4_fec_control_sc_S_100G_X4 66 4579 #define rx_x4_fec_control_sc_S_100G_HG2_CR4 68 4580 #define rx_x4_fec_control_sc_S_100G_HG2_KR4 69 4581 #define rx_x4_fec_control_sc_S_100G_HG2_X4 70 4582 #define rx_x4_fec_control_sc_S_CL73_20GVCO 72 4583 #define rx_x4_fec_control_sc_S_CL73_25GVCO 80 4584 #define rx_x4_fec_control_sc_S_CL36_20GVCO 88 4585 #define rx_x4_fec_control_sc_S_CL36_25GVCO 96 4586 4587 /**************************************************************************** 4588 * Enums: rx_x4_fec_control_t_fifo_modes 4589 */ 4590 #define rx_x4_fec_control_t_fifo_modes_T_FIFO_MODE_BYPASS 0 4591 #define rx_x4_fec_control_t_fifo_modes_T_FIFO_MODE_40G 1 4592 #define rx_x4_fec_control_t_fifo_modes_T_FIFO_MODE_100G 2 4593 #define rx_x4_fec_control_t_fifo_modes_T_FIFO_MODE_20G 3 4594 4595 /**************************************************************************** 4596 * Enums: rx_x4_fec_control_t_enc_modes 4597 */ 4598 #define rx_x4_fec_control_t_enc_modes_T_ENC_MODE_BYPASS 0 4599 #define rx_x4_fec_control_t_enc_modes_T_ENC_MODE_CL49 1 4600 #define rx_x4_fec_control_t_enc_modes_T_ENC_MODE_CL82 2 4601 4602 /**************************************************************************** 4603 * Enums: rx_x4_fec_control_btmx_mode 4604 */ 4605 #define rx_x4_fec_control_btmx_mode_BS_BTMX_MODE_1to1 0 4606 #define rx_x4_fec_control_btmx_mode_BS_BTMX_MODE_2to1 1 4607 #define rx_x4_fec_control_btmx_mode_BS_BTMX_MODE_5to1 2 4608 4609 /**************************************************************************** 4610 * Enums: rx_x4_fec_control_t_type_cl82 4611 */ 4612 #define rx_x4_fec_control_t_type_cl82_T_TYPE_B1 5 4613 #define rx_x4_fec_control_t_type_cl82_T_TYPE_C 4 4614 #define rx_x4_fec_control_t_type_cl82_T_TYPE_S 3 4615 #define rx_x4_fec_control_t_type_cl82_T_TYPE_T 2 4616 #define rx_x4_fec_control_t_type_cl82_T_TYPE_D 1 4617 #define rx_x4_fec_control_t_type_cl82_T_TYPE_E 0 4618 4619 /**************************************************************************** 4620 * Enums: rx_x4_fec_control_txsm_state_cl82 4621 */ 4622 #define rx_x4_fec_control_txsm_state_cl82_TX_HIG_END 6 4623 #define rx_x4_fec_control_txsm_state_cl82_TX_HIG_START 5 4624 #define rx_x4_fec_control_txsm_state_cl82_TX_E 4 4625 #define rx_x4_fec_control_txsm_state_cl82_TX_T 3 4626 #define rx_x4_fec_control_txsm_state_cl82_TX_D 2 4627 #define rx_x4_fec_control_txsm_state_cl82_TX_C 1 4628 #define rx_x4_fec_control_txsm_state_cl82_TX_INIT 0 4629 4630 /**************************************************************************** 4631 * Enums: rx_x4_fec_control_ltxsm_state_cl82 4632 */ 4633 #define rx_x4_fec_control_ltxsm_state_cl82_TX_HIG_END 64 4634 #define rx_x4_fec_control_ltxsm_state_cl82_TX_HIG_START 32 4635 #define rx_x4_fec_control_ltxsm_state_cl82_TX_E 16 4636 #define rx_x4_fec_control_ltxsm_state_cl82_TX_T 8 4637 #define rx_x4_fec_control_ltxsm_state_cl82_TX_D 4 4638 #define rx_x4_fec_control_ltxsm_state_cl82_TX_C 2 4639 #define rx_x4_fec_control_ltxsm_state_cl82_TX_INIT 1 4640 4641 /**************************************************************************** 4642 * Enums: rx_x4_fec_control_r_type_coded_cl82 4643 */ 4644 #define rx_x4_fec_control_r_type_coded_cl82_R_TYPE_B1 32 4645 #define rx_x4_fec_control_r_type_coded_cl82_R_TYPE_C 16 4646 #define rx_x4_fec_control_r_type_coded_cl82_R_TYPE_S 8 4647 #define rx_x4_fec_control_r_type_coded_cl82_R_TYPE_T 4 4648 #define rx_x4_fec_control_r_type_coded_cl82_R_TYPE_D 2 4649 #define rx_x4_fec_control_r_type_coded_cl82_R_TYPE_E 1 4650 4651 /**************************************************************************** 4652 * Enums: rx_x4_fec_control_rxsm_state_cl82 4653 */ 4654 #define rx_x4_fec_control_rxsm_state_cl82_RX_HIG_END 64 4655 #define rx_x4_fec_control_rxsm_state_cl82_RX_HIG_START 32 4656 #define rx_x4_fec_control_rxsm_state_cl82_RX_E 16 4657 #define rx_x4_fec_control_rxsm_state_cl82_RX_T 8 4658 #define rx_x4_fec_control_rxsm_state_cl82_RX_D 4 4659 #define rx_x4_fec_control_rxsm_state_cl82_RX_C 2 4660 #define rx_x4_fec_control_rxsm_state_cl82_RX_INIT 1 4661 4662 /**************************************************************************** 4663 * Enums: rx_x4_fec_control_deskew_state 4664 */ 4665 #define rx_x4_fec_control_deskew_state_ALIGN_ACQUIRED 2 4666 #define rx_x4_fec_control_deskew_state_LOSS_OF_ALIGNMENT 1 4667 4668 /**************************************************************************** 4669 * Enums: rx_x4_fec_control_os_mode_enum 4670 */ 4671 #define rx_x4_fec_control_os_mode_enum_OS_MODE_1 0 4672 #define rx_x4_fec_control_os_mode_enum_OS_MODE_2 1 4673 #define rx_x4_fec_control_os_mode_enum_OS_MODE_4 2 4674 #define rx_x4_fec_control_os_mode_enum_OS_MODE_16p5 8 4675 #define rx_x4_fec_control_os_mode_enum_OS_MODE_20p625 12 4676 4677 /**************************************************************************** 4678 * Enums: rx_x4_fec_control_scr_modes 4679 */ 4680 #define rx_x4_fec_control_scr_modes_T_SCR_MODE_BYPASS 0 4681 #define rx_x4_fec_control_scr_modes_T_SCR_MODE_CL49 1 4682 #define rx_x4_fec_control_scr_modes_T_SCR_MODE_40G_2_LANE 2 4683 #define rx_x4_fec_control_scr_modes_T_SCR_MODE_100G 3 4684 #define rx_x4_fec_control_scr_modes_T_SCR_MODE_20G 4 4685 #define rx_x4_fec_control_scr_modes_T_SCR_MODE_40G_4_LANE 5 4686 4687 /**************************************************************************** 4688 * Enums: rx_x4_fec_control_descr_modes 4689 */ 4690 #define rx_x4_fec_control_descr_modes_R_DESCR_MODE_BYPASS 0 4691 #define rx_x4_fec_control_descr_modes_R_DESCR_MODE_CL49 1 4692 #define rx_x4_fec_control_descr_modes_R_DESCR_MODE_CL82 2 4693 4694 /**************************************************************************** 4695 * Enums: rx_x4_fec_control_r_dec_tl_mode 4696 */ 4697 #define rx_x4_fec_control_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 4698 #define rx_x4_fec_control_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 4699 #define rx_x4_fec_control_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 4700 4701 /**************************************************************************** 4702 * Enums: rx_x4_fec_control_r_dec_fsm_mode 4703 */ 4704 #define rx_x4_fec_control_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 4705 #define rx_x4_fec_control_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 4706 #define rx_x4_fec_control_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 4707 4708 /**************************************************************************** 4709 * Enums: rx_x4_fec_control_r_deskew_mode 4710 */ 4711 #define rx_x4_fec_control_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 4712 #define rx_x4_fec_control_r_deskew_mode_R_DESKEW_MODE_20G 1 4713 #define rx_x4_fec_control_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 4714 #define rx_x4_fec_control_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 4715 #define rx_x4_fec_control_r_deskew_mode_R_DESKEW_MODE_100G 4 4716 #define rx_x4_fec_control_r_deskew_mode_R_DESKEW_MODE_CL49 5 4717 #define rx_x4_fec_control_r_deskew_mode_R_DESKEW_MODE_CL91 6 4718 4719 /**************************************************************************** 4720 * Enums: rx_x4_fec_control_bs_dist_modes 4721 */ 4722 #define rx_x4_fec_control_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 4723 #define rx_x4_fec_control_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 4724 #define rx_x4_fec_control_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 4725 #define rx_x4_fec_control_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 4726 4727 /**************************************************************************** 4728 * Enums: rx_x4_fec_control_cl49_t_type 4729 */ 4730 #define rx_x4_fec_control_cl49_t_type_BAD_T_TYPE 15 4731 #define rx_x4_fec_control_cl49_t_type_T_TYPE_B0 11 4732 #define rx_x4_fec_control_cl49_t_type_T_TYPE_OB 10 4733 #define rx_x4_fec_control_cl49_t_type_T_TYPE_B1 9 4734 #define rx_x4_fec_control_cl49_t_type_T_TYPE_DB 8 4735 #define rx_x4_fec_control_cl49_t_type_T_TYPE_FC 7 4736 #define rx_x4_fec_control_cl49_t_type_T_TYPE_TB 6 4737 #define rx_x4_fec_control_cl49_t_type_T_TYPE_LI 5 4738 #define rx_x4_fec_control_cl49_t_type_T_TYPE_C 4 4739 #define rx_x4_fec_control_cl49_t_type_T_TYPE_S 3 4740 #define rx_x4_fec_control_cl49_t_type_T_TYPE_T 2 4741 #define rx_x4_fec_control_cl49_t_type_T_TYPE_D 1 4742 #define rx_x4_fec_control_cl49_t_type_T_TYPE_E 0 4743 4744 /**************************************************************************** 4745 * Enums: rx_x4_fec_control_cl49_txsm_states 4746 */ 4747 #define rx_x4_fec_control_cl49_txsm_states_TX_HIG_END 7 4748 #define rx_x4_fec_control_cl49_txsm_states_TX_HIG_START 6 4749 #define rx_x4_fec_control_cl49_txsm_states_TX_LI 5 4750 #define rx_x4_fec_control_cl49_txsm_states_TX_E 4 4751 #define rx_x4_fec_control_cl49_txsm_states_TX_T 3 4752 #define rx_x4_fec_control_cl49_txsm_states_TX_D 2 4753 #define rx_x4_fec_control_cl49_txsm_states_TX_C 1 4754 #define rx_x4_fec_control_cl49_txsm_states_TX_INIT 0 4755 4756 /**************************************************************************** 4757 * Enums: rx_x4_fec_control_cl49_ltxsm_states 4758 */ 4759 #define rx_x4_fec_control_cl49_ltxsm_states_TX_HIG_END 128 4760 #define rx_x4_fec_control_cl49_ltxsm_states_TX_HIG_START 64 4761 #define rx_x4_fec_control_cl49_ltxsm_states_TX_LI 32 4762 #define rx_x4_fec_control_cl49_ltxsm_states_TX_E 16 4763 #define rx_x4_fec_control_cl49_ltxsm_states_TX_T 8 4764 #define rx_x4_fec_control_cl49_ltxsm_states_TX_D 4 4765 #define rx_x4_fec_control_cl49_ltxsm_states_TX_C 2 4766 #define rx_x4_fec_control_cl49_ltxsm_states_TX_INIT 1 4767 4768 /**************************************************************************** 4769 * Enums: rx_x4_fec_control_burst_error_mode 4770 */ 4771 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_11_BITS 0 4772 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_16_BITS 1 4773 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_17_BITS 2 4774 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_18_BITS 3 4775 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_19_BITS 4 4776 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_20_BITS 5 4777 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_21_BITS 6 4778 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_22_BITS 7 4779 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_23_BITS 8 4780 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_24_BITS 9 4781 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_25_BITS 10 4782 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_26_BITS 11 4783 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_27_BITS 12 4784 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_28_BITS 13 4785 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_29_BITS 14 4786 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_30_BITS 15 4787 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_31_BITS 16 4788 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_32_BITS 17 4789 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_33_BITS 18 4790 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_34_BITS 19 4791 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_35_BITS 20 4792 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_36_BITS 21 4793 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_37_BITS 22 4794 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_38_BITS 23 4795 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_39_BITS 24 4796 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_40_BITS 25 4797 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_41_BITS 26 4798 4799 /**************************************************************************** 4800 * Enums: rx_x4_fec_control_bermon_state 4801 */ 4802 #define rx_x4_fec_control_bermon_state_HI_BER 4 4803 #define rx_x4_fec_control_bermon_state_GOOD_BER 3 4804 #define rx_x4_fec_control_bermon_state_BER_TEST_SH 2 4805 #define rx_x4_fec_control_bermon_state_START_TIMER 1 4806 #define rx_x4_fec_control_bermon_state_BER_MT_INIT 0 4807 4808 /**************************************************************************** 4809 * Enums: rx_x4_fec_control_rxsm_state_cl49 4810 */ 4811 #define rx_x4_fec_control_rxsm_state_cl49_RX_HIG_END 128 4812 #define rx_x4_fec_control_rxsm_state_cl49_RX_HIG_START 64 4813 #define rx_x4_fec_control_rxsm_state_cl49_RX_LI 32 4814 #define rx_x4_fec_control_rxsm_state_cl49_RX_E 16 4815 #define rx_x4_fec_control_rxsm_state_cl49_RX_T 8 4816 #define rx_x4_fec_control_rxsm_state_cl49_RX_D 4 4817 #define rx_x4_fec_control_rxsm_state_cl49_RX_C 2 4818 #define rx_x4_fec_control_rxsm_state_cl49_RX_INIT 1 4819 4820 /**************************************************************************** 4821 * Enums: rx_x4_fec_control_r_type 4822 */ 4823 #define rx_x4_fec_control_r_type_BAD_R_TYPE 15 4824 #define rx_x4_fec_control_r_type_R_TYPE_B0 11 4825 #define rx_x4_fec_control_r_type_R_TYPE_OB 10 4826 #define rx_x4_fec_control_r_type_R_TYPE_B1 9 4827 #define rx_x4_fec_control_r_type_R_TYPE_DB 8 4828 #define rx_x4_fec_control_r_type_R_TYPE_FC 7 4829 #define rx_x4_fec_control_r_type_R_TYPE_TB 6 4830 #define rx_x4_fec_control_r_type_R_TYPE_LI 5 4831 #define rx_x4_fec_control_r_type_R_TYPE_C 4 4832 #define rx_x4_fec_control_r_type_R_TYPE_S 3 4833 #define rx_x4_fec_control_r_type_R_TYPE_T 2 4834 #define rx_x4_fec_control_r_type_R_TYPE_D 1 4835 #define rx_x4_fec_control_r_type_R_TYPE_E 0 4836 4837 /**************************************************************************** 4838 * Enums: rx_x4_fec_control_am_lock_state 4839 */ 4840 #define rx_x4_fec_control_am_lock_state_INVALID_AM 512 4841 #define rx_x4_fec_control_am_lock_state_GOOD_AM 256 4842 #define rx_x4_fec_control_am_lock_state_COMP_AM 128 4843 #define rx_x4_fec_control_am_lock_state_TIMER_2 64 4844 #define rx_x4_fec_control_am_lock_state_AM_2_GOOD 32 4845 #define rx_x4_fec_control_am_lock_state_COMP_2ND 16 4846 #define rx_x4_fec_control_am_lock_state_TIMER_1 8 4847 #define rx_x4_fec_control_am_lock_state_FIND_1ST 4 4848 #define rx_x4_fec_control_am_lock_state_AM_RESET_CNT 2 4849 #define rx_x4_fec_control_am_lock_state_AM_LOCK_INIT 1 4850 4851 /**************************************************************************** 4852 * Enums: rx_x4_fec_control_msg_selector 4853 */ 4854 #define rx_x4_fec_control_msg_selector_RESERVED 0 4855 #define rx_x4_fec_control_msg_selector_VALUE_802p3 1 4856 #define rx_x4_fec_control_msg_selector_VALUE_802p9 2 4857 #define rx_x4_fec_control_msg_selector_VALUE_802p5 3 4858 #define rx_x4_fec_control_msg_selector_VALUE_1394 4 4859 4860 /**************************************************************************** 4861 * Enums: rx_x4_fec_control_synce_enum 4862 */ 4863 #define rx_x4_fec_control_synce_enum_SYNCE_NO_DIV 0 4864 #define rx_x4_fec_control_synce_enum_SYNCE_DIV_7 1 4865 #define rx_x4_fec_control_synce_enum_SYNCE_DIV_11 2 4866 4867 /**************************************************************************** 4868 * Enums: rx_x4_fec_control_synce_enum_stage0 4869 */ 4870 #define rx_x4_fec_control_synce_enum_stage0_SYNCE_NO_DIV 0 4871 #define rx_x4_fec_control_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 4872 #define rx_x4_fec_control_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 4873 4874 /**************************************************************************** 4875 * Enums: rx_x4_fec_control_cl91_sync_state 4876 */ 4877 #define rx_x4_fec_control_cl91_sync_state_FIND_1ST 0 4878 #define rx_x4_fec_control_cl91_sync_state_COUNT_NEXT 1 4879 #define rx_x4_fec_control_cl91_sync_state_COMP_2ND 2 4880 #define rx_x4_fec_control_cl91_sync_state_TWO_GOOD 3 4881 4882 /**************************************************************************** 4883 * Enums: rx_x4_fec_control_cl91_algn_state 4884 */ 4885 #define rx_x4_fec_control_cl91_algn_state_LOSS_OF_ALIGNMENT 0 4886 #define rx_x4_fec_control_cl91_algn_state_DESKEW 1 4887 #define rx_x4_fec_control_cl91_algn_state_DESKEW_FAIL 2 4888 #define rx_x4_fec_control_cl91_algn_state_ALIGN_ACQUIRED 3 4889 #define rx_x4_fec_control_cl91_algn_state_CW_GOOD 4 4890 #define rx_x4_fec_control_cl91_algn_state_CW_BAD 5 4891 #define rx_x4_fec_control_cl91_algn_state_THREE_BAD 6 4892 4893 /**************************************************************************** 4894 * Enums: rx_x4_fec_control_fec_sel 4895 */ 4896 #define rx_x4_fec_control_fec_sel_NO_FEC 0 4897 #define rx_x4_fec_control_fec_sel_FEC_CL74 1 4898 #define rx_x4_fec_control_fec_sel_FEC_CL91 2 4899 4900 /**************************************************************************** 4901 * Enums: rx_x4_status1_cl36TxEEEStates_l 4902 */ 4903 #define rx_x4_status1_cl36TxEEEStates_l_TX_REFRESH 8 4904 #define rx_x4_status1_cl36TxEEEStates_l_TX_QUIET 4 4905 #define rx_x4_status1_cl36TxEEEStates_l_TX_SLEEP 2 4906 #define rx_x4_status1_cl36TxEEEStates_l_TX_ACTIVE 1 4907 4908 /**************************************************************************** 4909 * Enums: rx_x4_status1_cl36TxEEEStates_c 4910 */ 4911 #define rx_x4_status1_cl36TxEEEStates_c_TX_REFRESH 3 4912 #define rx_x4_status1_cl36TxEEEStates_c_TX_QUIET 2 4913 #define rx_x4_status1_cl36TxEEEStates_c_TX_SLEEP 1 4914 #define rx_x4_status1_cl36TxEEEStates_c_TX_ACTIVE 0 4915 4916 /**************************************************************************** 4917 * Enums: rx_x4_status1_cl49TxEEEStates_l 4918 */ 4919 #define rx_x4_status1_cl49TxEEEStates_l_SCR_RESET_2 64 4920 #define rx_x4_status1_cl49TxEEEStates_l_SCR_RESET_1 32 4921 #define rx_x4_status1_cl49TxEEEStates_l_TX_WAKE 16 4922 #define rx_x4_status1_cl49TxEEEStates_l_TX_REFRESH 8 4923 #define rx_x4_status1_cl49TxEEEStates_l_TX_QUIET 4 4924 #define rx_x4_status1_cl49TxEEEStates_l_TX_SLEEP 2 4925 #define rx_x4_status1_cl49TxEEEStates_l_TX_ACTIVE 1 4926 4927 /**************************************************************************** 4928 * Enums: rx_x4_status1_fec_req_enum 4929 */ 4930 #define rx_x4_status1_fec_req_enum_FEC_not_supported 0 4931 #define rx_x4_status1_fec_req_enum_FEC_supported_but_not_requested 1 4932 #define rx_x4_status1_fec_req_enum_invalid_setting 2 4933 #define rx_x4_status1_fec_req_enum_FEC_supported_and_requested 3 4934 4935 /**************************************************************************** 4936 * Enums: rx_x4_status1_cl73_pause_enum 4937 */ 4938 #define rx_x4_status1_cl73_pause_enum_No_PAUSE_ability 0 4939 #define rx_x4_status1_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 4940 #define rx_x4_status1_cl73_pause_enum_Symmetric_PAUSE_ability 1 4941 #define rx_x4_status1_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 4942 4943 /**************************************************************************** 4944 * Enums: rx_x4_status1_cl49TxEEEStates_c 4945 */ 4946 #define rx_x4_status1_cl49TxEEEStates_c_SCR_RESET_2 6 4947 #define rx_x4_status1_cl49TxEEEStates_c_SCR_RESET_1 5 4948 #define rx_x4_status1_cl49TxEEEStates_c_TX_WAKE 4 4949 #define rx_x4_status1_cl49TxEEEStates_c_TX_REFRESH 3 4950 #define rx_x4_status1_cl49TxEEEStates_c_TX_QUIET 2 4951 #define rx_x4_status1_cl49TxEEEStates_c_TX_SLEEP 1 4952 #define rx_x4_status1_cl49TxEEEStates_c_TX_ACTIVE 0 4953 4954 /**************************************************************************** 4955 * Enums: rx_x4_status1_cl36RxEEEStates_l 4956 */ 4957 #define rx_x4_status1_cl36RxEEEStates_l_RX_LINK_FAIL 32 4958 #define rx_x4_status1_cl36RxEEEStates_l_RX_WTF 16 4959 #define rx_x4_status1_cl36RxEEEStates_l_RX_WAKE 8 4960 #define rx_x4_status1_cl36RxEEEStates_l_RX_QUIET 4 4961 #define rx_x4_status1_cl36RxEEEStates_l_RX_SLEEP 2 4962 #define rx_x4_status1_cl36RxEEEStates_l_RX_ACTIVE 1 4963 4964 /**************************************************************************** 4965 * Enums: rx_x4_status1_cl36RxEEEStates_c 4966 */ 4967 #define rx_x4_status1_cl36RxEEEStates_c_RX_LINK_FAIL 5 4968 #define rx_x4_status1_cl36RxEEEStates_c_RX_WTF 4 4969 #define rx_x4_status1_cl36RxEEEStates_c_RX_WAKE 3 4970 #define rx_x4_status1_cl36RxEEEStates_c_RX_QUIET 2 4971 #define rx_x4_status1_cl36RxEEEStates_c_RX_SLEEP 1 4972 #define rx_x4_status1_cl36RxEEEStates_c_RX_ACTIVE 0 4973 4974 /**************************************************************************** 4975 * Enums: rx_x4_status1_cl49RxEEEStates_l 4976 */ 4977 #define rx_x4_status1_cl49RxEEEStates_l_RX_LINK_FAIL 32 4978 #define rx_x4_status1_cl49RxEEEStates_l_RX_WTF 16 4979 #define rx_x4_status1_cl49RxEEEStates_l_RX_WAKE 8 4980 #define rx_x4_status1_cl49RxEEEStates_l_RX_QUIET 4 4981 #define rx_x4_status1_cl49RxEEEStates_l_RX_SLEEP 2 4982 #define rx_x4_status1_cl49RxEEEStates_l_RX_ACTIVE 1 4983 4984 /**************************************************************************** 4985 * Enums: rx_x4_status1_cl49RxEEEStates_c 4986 */ 4987 #define rx_x4_status1_cl49RxEEEStates_c_RX_LINK_FAIL 5 4988 #define rx_x4_status1_cl49RxEEEStates_c_RX_WTF 4 4989 #define rx_x4_status1_cl49RxEEEStates_c_RX_WAKE 3 4990 #define rx_x4_status1_cl49RxEEEStates_c_RX_QUIET 2 4991 #define rx_x4_status1_cl49RxEEEStates_c_RX_SLEEP 1 4992 #define rx_x4_status1_cl49RxEEEStates_c_RX_ACTIVE 0 4993 4994 /**************************************************************************** 4995 * Enums: rx_x4_status1_cl48TxEEEStates_l 4996 */ 4997 #define rx_x4_status1_cl48TxEEEStates_l_TX_REFRESH 8 4998 #define rx_x4_status1_cl48TxEEEStates_l_TX_QUIET 4 4999 #define rx_x4_status1_cl48TxEEEStates_l_TX_SLEEP 2 5000 #define rx_x4_status1_cl48TxEEEStates_l_TX_ACTIVE 1 5001 5002 /**************************************************************************** 5003 * Enums: rx_x4_status1_cl48TxEEEStates_c 5004 */ 5005 #define rx_x4_status1_cl48TxEEEStates_c_TX_REFRESH 3 5006 #define rx_x4_status1_cl48TxEEEStates_c_TX_QUIET 2 5007 #define rx_x4_status1_cl48TxEEEStates_c_TX_SLEEP 1 5008 #define rx_x4_status1_cl48TxEEEStates_c_TX_ACTIVE 0 5009 5010 /**************************************************************************** 5011 * Enums: rx_x4_status1_cl48RxEEEStates_l 5012 */ 5013 #define rx_x4_status1_cl48RxEEEStates_l_RX_LINK_FAIL 32 5014 #define rx_x4_status1_cl48RxEEEStates_l_RX_WAKE 16 5015 #define rx_x4_status1_cl48RxEEEStates_l_RX_QUIET 8 5016 #define rx_x4_status1_cl48RxEEEStates_l_RX_DEACT 4 5017 #define rx_x4_status1_cl48RxEEEStates_l_RX_SLEEP 2 5018 #define rx_x4_status1_cl48RxEEEStates_l_RX_ACTIVE 1 5019 5020 /**************************************************************************** 5021 * Enums: rx_x4_status1_cl48RxEEEStates_c 5022 */ 5023 #define rx_x4_status1_cl48RxEEEStates_c_RX_LINK_FAIL 5 5024 #define rx_x4_status1_cl48RxEEEStates_c_RX_WAKE 4 5025 #define rx_x4_status1_cl48RxEEEStates_c_RX_QUIET 3 5026 #define rx_x4_status1_cl48RxEEEStates_c_RX_DEACT 2 5027 #define rx_x4_status1_cl48RxEEEStates_c_RX_SLEEP 1 5028 #define rx_x4_status1_cl48RxEEEStates_c_RX_ACTIVE 0 5029 5030 /**************************************************************************** 5031 * Enums: rx_x4_status1_IQP_Options 5032 */ 5033 #define rx_x4_status1_IQP_Options_i50uA 0 5034 #define rx_x4_status1_IQP_Options_i100uA 1 5035 #define rx_x4_status1_IQP_Options_i150uA 2 5036 #define rx_x4_status1_IQP_Options_i200uA 3 5037 #define rx_x4_status1_IQP_Options_i250uA 4 5038 #define rx_x4_status1_IQP_Options_i300uA 5 5039 #define rx_x4_status1_IQP_Options_i350uA 6 5040 #define rx_x4_status1_IQP_Options_i400uA 7 5041 #define rx_x4_status1_IQP_Options_i450uA 8 5042 #define rx_x4_status1_IQP_Options_i500uA 9 5043 #define rx_x4_status1_IQP_Options_i550uA 10 5044 #define rx_x4_status1_IQP_Options_i600uA 11 5045 #define rx_x4_status1_IQP_Options_i650uA 12 5046 #define rx_x4_status1_IQP_Options_i700uA 13 5047 #define rx_x4_status1_IQP_Options_i750uA 14 5048 #define rx_x4_status1_IQP_Options_i800uA 15 5049 5050 /**************************************************************************** 5051 * Enums: rx_x4_status1_IDriver_Options 5052 */ 5053 #define rx_x4_status1_IDriver_Options_v680mV 0 5054 #define rx_x4_status1_IDriver_Options_v730mV 1 5055 #define rx_x4_status1_IDriver_Options_v780mV 2 5056 #define rx_x4_status1_IDriver_Options_v830mV 3 5057 #define rx_x4_status1_IDriver_Options_v880mV 4 5058 #define rx_x4_status1_IDriver_Options_v930mV 5 5059 #define rx_x4_status1_IDriver_Options_v980mV 6 5060 #define rx_x4_status1_IDriver_Options_v1010mV 7 5061 #define rx_x4_status1_IDriver_Options_v1040mV 8 5062 #define rx_x4_status1_IDriver_Options_v1060mV 9 5063 #define rx_x4_status1_IDriver_Options_v1070mV 10 5064 #define rx_x4_status1_IDriver_Options_v1080mV 11 5065 #define rx_x4_status1_IDriver_Options_v1085mV 12 5066 #define rx_x4_status1_IDriver_Options_v1090mV 13 5067 #define rx_x4_status1_IDriver_Options_v1095mV 14 5068 #define rx_x4_status1_IDriver_Options_v1100mV 15 5069 5070 /**************************************************************************** 5071 * Enums: rx_x4_status1_operationModes 5072 */ 5073 #define rx_x4_status1_operationModes_XGXS 0 5074 #define rx_x4_status1_operationModes_XGXG_nCC 1 5075 #define rx_x4_status1_operationModes_Indlane_OS8 4 5076 #define rx_x4_status1_operationModes_IndLane_OS5 5 5077 #define rx_x4_status1_operationModes_PCI 7 5078 #define rx_x4_status1_operationModes_XGXS_nLQ 8 5079 #define rx_x4_status1_operationModes_XGXS_nLQnCC 9 5080 #define rx_x4_status1_operationModes_PBypass 10 5081 #define rx_x4_status1_operationModes_PBypass_nDSK 11 5082 #define rx_x4_status1_operationModes_ComboCoreMode 12 5083 #define rx_x4_status1_operationModes_Clocks_off 15 5084 5085 /**************************************************************************** 5086 * Enums: rx_x4_status1_actualSpeeds 5087 */ 5088 #define rx_x4_status1_actualSpeeds_dr_10M 0 5089 #define rx_x4_status1_actualSpeeds_dr_100M 1 5090 #define rx_x4_status1_actualSpeeds_dr_1G 2 5091 #define rx_x4_status1_actualSpeeds_dr_2p5G 3 5092 #define rx_x4_status1_actualSpeeds_dr_5G_X4 4 5093 #define rx_x4_status1_actualSpeeds_dr_6G_X4 5 5094 #define rx_x4_status1_actualSpeeds_dr_10G_HiG 6 5095 #define rx_x4_status1_actualSpeeds_dr_10G_CX4 7 5096 #define rx_x4_status1_actualSpeeds_dr_12G_HiG 8 5097 #define rx_x4_status1_actualSpeeds_dr_12p5G_X4 9 5098 #define rx_x4_status1_actualSpeeds_dr_13G_X4 10 5099 #define rx_x4_status1_actualSpeeds_dr_15G_X4 11 5100 #define rx_x4_status1_actualSpeeds_dr_16G_X4 12 5101 #define rx_x4_status1_actualSpeeds_dr_1G_KX 13 5102 #define rx_x4_status1_actualSpeeds_dr_10G_KX4 14 5103 #define rx_x4_status1_actualSpeeds_dr_10G_KR 15 5104 #define rx_x4_status1_actualSpeeds_dr_5G 16 5105 #define rx_x4_status1_actualSpeeds_dr_6p4G 17 5106 #define rx_x4_status1_actualSpeeds_dr_20G_X4 18 5107 #define rx_x4_status1_actualSpeeds_dr_21G_X4 19 5108 #define rx_x4_status1_actualSpeeds_dr_25G_X4 20 5109 #define rx_x4_status1_actualSpeeds_dr_10G_HiG_DXGXS 21 5110 #define rx_x4_status1_actualSpeeds_dr_10G_DXGXS 22 5111 #define rx_x4_status1_actualSpeeds_dr_10p5G_HiG_DXGXS 23 5112 #define rx_x4_status1_actualSpeeds_dr_10p5G_DXGXS 24 5113 #define rx_x4_status1_actualSpeeds_dr_12p773G_HiG_DXGXS 25 5114 #define rx_x4_status1_actualSpeeds_dr_12p773G_DXGXS 26 5115 #define rx_x4_status1_actualSpeeds_dr_10G_XFI 27 5116 #define rx_x4_status1_actualSpeeds_dr_40G 28 5117 #define rx_x4_status1_actualSpeeds_dr_20G_HiG_DXGXS 29 5118 #define rx_x4_status1_actualSpeeds_dr_20G_DXGXS 30 5119 #define rx_x4_status1_actualSpeeds_dr_10G_SFI 31 5120 #define rx_x4_status1_actualSpeeds_dr_31p5G 32 5121 #define rx_x4_status1_actualSpeeds_dr_32p7G 33 5122 #define rx_x4_status1_actualSpeeds_dr_20G_SCR 34 5123 #define rx_x4_status1_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 5124 #define rx_x4_status1_actualSpeeds_dr_10G_DXGXS_SCR 36 5125 #define rx_x4_status1_actualSpeeds_dr_12G_R2 37 5126 #define rx_x4_status1_actualSpeeds_dr_10G_X2 38 5127 #define rx_x4_status1_actualSpeeds_dr_40G_KR4 39 5128 #define rx_x4_status1_actualSpeeds_dr_40G_CR4 40 5129 #define rx_x4_status1_actualSpeeds_dr_100G_CR10 41 5130 #define rx_x4_status1_actualSpeeds_dr_15p75G_DXGXS 44 5131 #define rx_x4_status1_actualSpeeds_dr_20G_KR2 57 5132 #define rx_x4_status1_actualSpeeds_dr_20G_CR2 58 5133 5134 /**************************************************************************** 5135 * Enums: rx_x4_status1_actualSpeedsMisc1 5136 */ 5137 #define rx_x4_status1_actualSpeedsMisc1_dr_2500BRCM_X1 16 5138 #define rx_x4_status1_actualSpeedsMisc1_dr_5000BRCM_X4 17 5139 #define rx_x4_status1_actualSpeedsMisc1_dr_6000BRCM_X4 18 5140 #define rx_x4_status1_actualSpeedsMisc1_dr_10GHiGig_X4 19 5141 #define rx_x4_status1_actualSpeedsMisc1_dr_10GBASE_CX4 20 5142 #define rx_x4_status1_actualSpeedsMisc1_dr_12GHiGig_X4 21 5143 #define rx_x4_status1_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 5144 #define rx_x4_status1_actualSpeedsMisc1_dr_13GHiGig_X4 23 5145 #define rx_x4_status1_actualSpeedsMisc1_dr_15GHiGig_X4 24 5146 #define rx_x4_status1_actualSpeedsMisc1_dr_16GHiGig_X4 25 5147 #define rx_x4_status1_actualSpeedsMisc1_dr_5000BRCM_X1 26 5148 #define rx_x4_status1_actualSpeedsMisc1_dr_6363BRCM_X1 27 5149 #define rx_x4_status1_actualSpeedsMisc1_dr_20GHiGig_X4 28 5150 #define rx_x4_status1_actualSpeedsMisc1_dr_21GHiGig_X4 29 5151 #define rx_x4_status1_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 5152 #define rx_x4_status1_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 5153 5154 /**************************************************************************** 5155 * Enums: rx_x4_status1_IndLaneModes 5156 */ 5157 #define rx_x4_status1_IndLaneModes_SWSDR_div2 0 5158 #define rx_x4_status1_IndLaneModes_SWSDR_div1 1 5159 #define rx_x4_status1_IndLaneModes_DWSDR_div2 2 5160 #define rx_x4_status1_IndLaneModes_DWSDR_div1 3 5161 5162 /**************************************************************************** 5163 * Enums: rx_x4_status1_prbsSelect 5164 */ 5165 #define rx_x4_status1_prbsSelect_prbs7 0 5166 #define rx_x4_status1_prbsSelect_prbs15 1 5167 #define rx_x4_status1_prbsSelect_prbs23 2 5168 #define rx_x4_status1_prbsSelect_prbs31 3 5169 5170 /**************************************************************************** 5171 * Enums: rx_x4_status1_vcoDivider 5172 */ 5173 #define rx_x4_status1_vcoDivider_div32 0 5174 #define rx_x4_status1_vcoDivider_div36 1 5175 #define rx_x4_status1_vcoDivider_div40 2 5176 #define rx_x4_status1_vcoDivider_div42 3 5177 #define rx_x4_status1_vcoDivider_div48 4 5178 #define rx_x4_status1_vcoDivider_div50 5 5179 #define rx_x4_status1_vcoDivider_div52 6 5180 #define rx_x4_status1_vcoDivider_div54 7 5181 #define rx_x4_status1_vcoDivider_div60 8 5182 #define rx_x4_status1_vcoDivider_div64 9 5183 #define rx_x4_status1_vcoDivider_div66 10 5184 #define rx_x4_status1_vcoDivider_div68 11 5185 #define rx_x4_status1_vcoDivider_div70 12 5186 #define rx_x4_status1_vcoDivider_div80 13 5187 #define rx_x4_status1_vcoDivider_div92 14 5188 #define rx_x4_status1_vcoDivider_div100 15 5189 5190 /**************************************************************************** 5191 * Enums: rx_x4_status1_refClkSelect 5192 */ 5193 #define rx_x4_status1_refClkSelect_clk_25MHz 0 5194 #define rx_x4_status1_refClkSelect_clk_100MHz 1 5195 #define rx_x4_status1_refClkSelect_clk_125MHz 2 5196 #define rx_x4_status1_refClkSelect_clk_156p25MHz 3 5197 #define rx_x4_status1_refClkSelect_clk_187p5MHz 4 5198 #define rx_x4_status1_refClkSelect_clk_161p25Mhz 5 5199 #define rx_x4_status1_refClkSelect_clk_50Mhz 6 5200 #define rx_x4_status1_refClkSelect_clk_106p25Mhz 7 5201 5202 /**************************************************************************** 5203 * Enums: rx_x4_status1_aerMMDdevTypeSelect 5204 */ 5205 #define rx_x4_status1_aerMMDdevTypeSelect_combo_core 0 5206 #define rx_x4_status1_aerMMDdevTypeSelect_PMA_PMD 1 5207 #define rx_x4_status1_aerMMDdevTypeSelect_PCS 3 5208 #define rx_x4_status1_aerMMDdevTypeSelect_PHY 4 5209 #define rx_x4_status1_aerMMDdevTypeSelect_DTE 5 5210 #define rx_x4_status1_aerMMDdevTypeSelect_CL73_AN 7 5211 5212 /**************************************************************************** 5213 * Enums: rx_x4_status1_aerMMDportSelect 5214 */ 5215 #define rx_x4_status1_aerMMDportSelect_ln0 0 5216 #define rx_x4_status1_aerMMDportSelect_ln1 1 5217 #define rx_x4_status1_aerMMDportSelect_ln2 2 5218 #define rx_x4_status1_aerMMDportSelect_ln3 3 5219 #define rx_x4_status1_aerMMDportSelect_BCST_ln0_1_2_3 511 5220 #define rx_x4_status1_aerMMDportSelect_BCST_ln0_1 512 5221 #define rx_x4_status1_aerMMDportSelect_BCST_ln2_3 513 5222 5223 /**************************************************************************** 5224 * Enums: rx_x4_status1_firmwareModeSelect 5225 */ 5226 #define rx_x4_status1_firmwareModeSelect_DEFAULT 0 5227 #define rx_x4_status1_firmwareModeSelect_SFP_OPT_LR 1 5228 #define rx_x4_status1_firmwareModeSelect_SFP_DAC 2 5229 #define rx_x4_status1_firmwareModeSelect_XLAUI 3 5230 #define rx_x4_status1_firmwareModeSelect_LONG_CH_6G 4 5231 5232 /**************************************************************************** 5233 * Enums: rx_x4_status1_tempIdxSelect 5234 */ 5235 #define rx_x4_status1_tempIdxSelect_LTE__22p9C 15 5236 #define rx_x4_status1_tempIdxSelect_LTE__12p6C 14 5237 #define rx_x4_status1_tempIdxSelect_LTE__3p0C 13 5238 #define rx_x4_status1_tempIdxSelect_LTE_6p7C 12 5239 #define rx_x4_status1_tempIdxSelect_LTE_16p4C 11 5240 #define rx_x4_status1_tempIdxSelect_LTE_26p6C 10 5241 #define rx_x4_status1_tempIdxSelect_LTE_36p3C 9 5242 #define rx_x4_status1_tempIdxSelect_LTE_46p0C 8 5243 #define rx_x4_status1_tempIdxSelect_LTE_56p2C 7 5244 #define rx_x4_status1_tempIdxSelect_LTE_65p9C 6 5245 #define rx_x4_status1_tempIdxSelect_LTE_75p6C 5 5246 #define rx_x4_status1_tempIdxSelect_LTE_85p3C 4 5247 #define rx_x4_status1_tempIdxSelect_LTE_95p5C 3 5248 #define rx_x4_status1_tempIdxSelect_LTE_105p2C 2 5249 #define rx_x4_status1_tempIdxSelect_LTE_114p9C 1 5250 #define rx_x4_status1_tempIdxSelect_LTE_125p1C 0 5251 5252 /**************************************************************************** 5253 * Enums: rx_x4_status1_port_mode 5254 */ 5255 #define rx_x4_status1_port_mode_QUAD_PORT 0 5256 #define rx_x4_status1_port_mode_TRI_1_PORT 1 5257 #define rx_x4_status1_port_mode_TRI_2_PORT 2 5258 #define rx_x4_status1_port_mode_DUAL_PORT 3 5259 #define rx_x4_status1_port_mode_SINGLE_PORT 4 5260 5261 /**************************************************************************** 5262 * Enums: rx_x4_status1_rev_letter_enum 5263 */ 5264 #define rx_x4_status1_rev_letter_enum_REV_A 0 5265 #define rx_x4_status1_rev_letter_enum_REV_B 1 5266 #define rx_x4_status1_rev_letter_enum_REV_C 2 5267 #define rx_x4_status1_rev_letter_enum_REV_D 3 5268 5269 /**************************************************************************** 5270 * Enums: rx_x4_status1_rev_number_enum 5271 */ 5272 #define rx_x4_status1_rev_number_enum_REV_0 0 5273 #define rx_x4_status1_rev_number_enum_REV_1 1 5274 #define rx_x4_status1_rev_number_enum_REV_2 2 5275 #define rx_x4_status1_rev_number_enum_REV_3 3 5276 #define rx_x4_status1_rev_number_enum_REV_4 4 5277 #define rx_x4_status1_rev_number_enum_REV_5 5 5278 #define rx_x4_status1_rev_number_enum_REV_6 6 5279 #define rx_x4_status1_rev_number_enum_REV_7 7 5280 5281 /**************************************************************************** 5282 * Enums: rx_x4_status1_bonding_enum 5283 */ 5284 #define rx_x4_status1_bonding_enum_WIRE_BOND 0 5285 #define rx_x4_status1_bonding_enum_FLIP_CHIP 1 5286 5287 /**************************************************************************** 5288 * Enums: rx_x4_status1_tech_process 5289 */ 5290 #define rx_x4_status1_tech_process_PROCESS_90NM 0 5291 #define rx_x4_status1_tech_process_PROCESS_65NM 1 5292 #define rx_x4_status1_tech_process_PROCESS_40NM 2 5293 #define rx_x4_status1_tech_process_PROCESS_28NM 3 5294 5295 /**************************************************************************** 5296 * Enums: rx_x4_status1_model_num 5297 */ 5298 #define rx_x4_status1_model_num_SERDES_CL73 0 5299 #define rx_x4_status1_model_num_XGXS_16G 1 5300 #define rx_x4_status1_model_num_HYPERCORE 2 5301 #define rx_x4_status1_model_num_HYPERLITE 3 5302 #define rx_x4_status1_model_num_PCIE_G2_PIPE 4 5303 #define rx_x4_status1_model_num_SERDES_1p25GBd 5 5304 #define rx_x4_status1_model_num_SATA2 6 5305 #define rx_x4_status1_model_num_QSGMII 7 5306 #define rx_x4_status1_model_num_XGXS10G 8 5307 #define rx_x4_status1_model_num_WARPCORE 9 5308 #define rx_x4_status1_model_num_XFICORE 10 5309 #define rx_x4_status1_model_num_RXFI 11 5310 #define rx_x4_status1_model_num_WARPLITE 12 5311 #define rx_x4_status1_model_num_PENTACORE 13 5312 #define rx_x4_status1_model_num_ESM 14 5313 #define rx_x4_status1_model_num_QUAD_SGMII 15 5314 #define rx_x4_status1_model_num_WARPCORE_3 16 5315 #define rx_x4_status1_model_num_TSC 17 5316 #define rx_x4_status1_model_num_TSC4E 18 5317 #define rx_x4_status1_model_num_TSC12E 19 5318 #define rx_x4_status1_model_num_TSC4F 20 5319 #define rx_x4_status1_model_num_XGXS_CL73_90NM 29 5320 #define rx_x4_status1_model_num_SERDES_CL73_90NM 30 5321 #define rx_x4_status1_model_num_WARPCORE3 32 5322 #define rx_x4_status1_model_num_WARPCORE4_TSC 33 5323 #define rx_x4_status1_model_num_RXAUI 34 5324 5325 /**************************************************************************** 5326 * Enums: rx_x4_status1_payload 5327 */ 5328 #define rx_x4_status1_payload_REPEAT_2_BYTES 0 5329 #define rx_x4_status1_payload_RAMPING 1 5330 #define rx_x4_status1_payload_CL48_CRPAT 2 5331 #define rx_x4_status1_payload_CL48_CJPAT 3 5332 #define rx_x4_status1_payload_CL36_LONG_CRPAT 4 5333 #define rx_x4_status1_payload_CL36_SHORT_CRPAT 5 5334 5335 /**************************************************************************** 5336 * Enums: rx_x4_status1_sc 5337 */ 5338 #define rx_x4_status1_sc_S_10G_CR1 0 5339 #define rx_x4_status1_sc_S_10G_KR1 1 5340 #define rx_x4_status1_sc_S_10G_X1 2 5341 #define rx_x4_status1_sc_S_10G_HG2_CR1 4 5342 #define rx_x4_status1_sc_S_10G_HG2_KR1 5 5343 #define rx_x4_status1_sc_S_10G_HG2_X1 6 5344 #define rx_x4_status1_sc_S_20G_CR1 8 5345 #define rx_x4_status1_sc_S_20G_KR1 9 5346 #define rx_x4_status1_sc_S_20G_X1 10 5347 #define rx_x4_status1_sc_S_20G_HG2_CR1 12 5348 #define rx_x4_status1_sc_S_20G_HG2_KR1 13 5349 #define rx_x4_status1_sc_S_20G_HG2_X1 14 5350 #define rx_x4_status1_sc_S_25G_CR1 16 5351 #define rx_x4_status1_sc_S_25G_KR1 17 5352 #define rx_x4_status1_sc_S_25G_X1 18 5353 #define rx_x4_status1_sc_S_25G_HG2_CR1 20 5354 #define rx_x4_status1_sc_S_25G_HG2_KR1 21 5355 #define rx_x4_status1_sc_S_25G_HG2_X1 22 5356 #define rx_x4_status1_sc_S_20G_CR2 24 5357 #define rx_x4_status1_sc_S_20G_KR2 25 5358 #define rx_x4_status1_sc_S_20G_X2 26 5359 #define rx_x4_status1_sc_S_20G_HG2_CR2 28 5360 #define rx_x4_status1_sc_S_20G_HG2_KR2 29 5361 #define rx_x4_status1_sc_S_20G_HG2_X2 30 5362 #define rx_x4_status1_sc_S_40G_CR2 32 5363 #define rx_x4_status1_sc_S_40G_KR2 33 5364 #define rx_x4_status1_sc_S_40G_X2 34 5365 #define rx_x4_status1_sc_S_40G_HG2_CR2 36 5366 #define rx_x4_status1_sc_S_40G_HG2_KR2 37 5367 #define rx_x4_status1_sc_S_40G_HG2_X2 38 5368 #define rx_x4_status1_sc_S_40G_CR4 40 5369 #define rx_x4_status1_sc_S_40G_KR4 41 5370 #define rx_x4_status1_sc_S_40G_X4 42 5371 #define rx_x4_status1_sc_S_40G_HG2_CR4 44 5372 #define rx_x4_status1_sc_S_40G_HG2_KR4 45 5373 #define rx_x4_status1_sc_S_40G_HG2_X4 46 5374 #define rx_x4_status1_sc_S_50G_CR2 48 5375 #define rx_x4_status1_sc_S_50G_KR2 49 5376 #define rx_x4_status1_sc_S_50G_X2 50 5377 #define rx_x4_status1_sc_S_50G_HG2_CR2 52 5378 #define rx_x4_status1_sc_S_50G_HG2_KR2 53 5379 #define rx_x4_status1_sc_S_50G_HG2_X2 54 5380 #define rx_x4_status1_sc_S_50G_CR4 56 5381 #define rx_x4_status1_sc_S_50G_KR4 57 5382 #define rx_x4_status1_sc_S_50G_X4 58 5383 #define rx_x4_status1_sc_S_50G_HG2_CR4 60 5384 #define rx_x4_status1_sc_S_50G_HG2_KR4 61 5385 #define rx_x4_status1_sc_S_50G_HG2_X4 62 5386 #define rx_x4_status1_sc_S_100G_CR4 64 5387 #define rx_x4_status1_sc_S_100G_KR4 65 5388 #define rx_x4_status1_sc_S_100G_X4 66 5389 #define rx_x4_status1_sc_S_100G_HG2_CR4 68 5390 #define rx_x4_status1_sc_S_100G_HG2_KR4 69 5391 #define rx_x4_status1_sc_S_100G_HG2_X4 70 5392 #define rx_x4_status1_sc_S_CL73_20GVCO 72 5393 #define rx_x4_status1_sc_S_CL73_25GVCO 80 5394 #define rx_x4_status1_sc_S_CL36_20GVCO 88 5395 #define rx_x4_status1_sc_S_CL36_25GVCO 96 5396 5397 /**************************************************************************** 5398 * Enums: rx_x4_status1_t_fifo_modes 5399 */ 5400 #define rx_x4_status1_t_fifo_modes_T_FIFO_MODE_BYPASS 0 5401 #define rx_x4_status1_t_fifo_modes_T_FIFO_MODE_40G 1 5402 #define rx_x4_status1_t_fifo_modes_T_FIFO_MODE_100G 2 5403 #define rx_x4_status1_t_fifo_modes_T_FIFO_MODE_20G 3 5404 5405 /**************************************************************************** 5406 * Enums: rx_x4_status1_t_enc_modes 5407 */ 5408 #define rx_x4_status1_t_enc_modes_T_ENC_MODE_BYPASS 0 5409 #define rx_x4_status1_t_enc_modes_T_ENC_MODE_CL49 1 5410 #define rx_x4_status1_t_enc_modes_T_ENC_MODE_CL82 2 5411 5412 /**************************************************************************** 5413 * Enums: rx_x4_status1_btmx_mode 5414 */ 5415 #define rx_x4_status1_btmx_mode_BS_BTMX_MODE_1to1 0 5416 #define rx_x4_status1_btmx_mode_BS_BTMX_MODE_2to1 1 5417 #define rx_x4_status1_btmx_mode_BS_BTMX_MODE_5to1 2 5418 5419 /**************************************************************************** 5420 * Enums: rx_x4_status1_t_type_cl82 5421 */ 5422 #define rx_x4_status1_t_type_cl82_T_TYPE_B1 5 5423 #define rx_x4_status1_t_type_cl82_T_TYPE_C 4 5424 #define rx_x4_status1_t_type_cl82_T_TYPE_S 3 5425 #define rx_x4_status1_t_type_cl82_T_TYPE_T 2 5426 #define rx_x4_status1_t_type_cl82_T_TYPE_D 1 5427 #define rx_x4_status1_t_type_cl82_T_TYPE_E 0 5428 5429 /**************************************************************************** 5430 * Enums: rx_x4_status1_txsm_state_cl82 5431 */ 5432 #define rx_x4_status1_txsm_state_cl82_TX_HIG_END 6 5433 #define rx_x4_status1_txsm_state_cl82_TX_HIG_START 5 5434 #define rx_x4_status1_txsm_state_cl82_TX_E 4 5435 #define rx_x4_status1_txsm_state_cl82_TX_T 3 5436 #define rx_x4_status1_txsm_state_cl82_TX_D 2 5437 #define rx_x4_status1_txsm_state_cl82_TX_C 1 5438 #define rx_x4_status1_txsm_state_cl82_TX_INIT 0 5439 5440 /**************************************************************************** 5441 * Enums: rx_x4_status1_ltxsm_state_cl82 5442 */ 5443 #define rx_x4_status1_ltxsm_state_cl82_TX_HIG_END 64 5444 #define rx_x4_status1_ltxsm_state_cl82_TX_HIG_START 32 5445 #define rx_x4_status1_ltxsm_state_cl82_TX_E 16 5446 #define rx_x4_status1_ltxsm_state_cl82_TX_T 8 5447 #define rx_x4_status1_ltxsm_state_cl82_TX_D 4 5448 #define rx_x4_status1_ltxsm_state_cl82_TX_C 2 5449 #define rx_x4_status1_ltxsm_state_cl82_TX_INIT 1 5450 5451 /**************************************************************************** 5452 * Enums: rx_x4_status1_r_type_coded_cl82 5453 */ 5454 #define rx_x4_status1_r_type_coded_cl82_R_TYPE_B1 32 5455 #define rx_x4_status1_r_type_coded_cl82_R_TYPE_C 16 5456 #define rx_x4_status1_r_type_coded_cl82_R_TYPE_S 8 5457 #define rx_x4_status1_r_type_coded_cl82_R_TYPE_T 4 5458 #define rx_x4_status1_r_type_coded_cl82_R_TYPE_D 2 5459 #define rx_x4_status1_r_type_coded_cl82_R_TYPE_E 1 5460 5461 /**************************************************************************** 5462 * Enums: rx_x4_status1_rxsm_state_cl82 5463 */ 5464 #define rx_x4_status1_rxsm_state_cl82_RX_HIG_END 64 5465 #define rx_x4_status1_rxsm_state_cl82_RX_HIG_START 32 5466 #define rx_x4_status1_rxsm_state_cl82_RX_E 16 5467 #define rx_x4_status1_rxsm_state_cl82_RX_T 8 5468 #define rx_x4_status1_rxsm_state_cl82_RX_D 4 5469 #define rx_x4_status1_rxsm_state_cl82_RX_C 2 5470 #define rx_x4_status1_rxsm_state_cl82_RX_INIT 1 5471 5472 /**************************************************************************** 5473 * Enums: rx_x4_status1_deskew_state 5474 */ 5475 #define rx_x4_status1_deskew_state_ALIGN_ACQUIRED 2 5476 #define rx_x4_status1_deskew_state_LOSS_OF_ALIGNMENT 1 5477 5478 /**************************************************************************** 5479 * Enums: rx_x4_status1_os_mode_enum 5480 */ 5481 #define rx_x4_status1_os_mode_enum_OS_MODE_1 0 5482 #define rx_x4_status1_os_mode_enum_OS_MODE_2 1 5483 #define rx_x4_status1_os_mode_enum_OS_MODE_4 2 5484 #define rx_x4_status1_os_mode_enum_OS_MODE_16p5 8 5485 #define rx_x4_status1_os_mode_enum_OS_MODE_20p625 12 5486 5487 /**************************************************************************** 5488 * Enums: rx_x4_status1_scr_modes 5489 */ 5490 #define rx_x4_status1_scr_modes_T_SCR_MODE_BYPASS 0 5491 #define rx_x4_status1_scr_modes_T_SCR_MODE_CL49 1 5492 #define rx_x4_status1_scr_modes_T_SCR_MODE_40G_2_LANE 2 5493 #define rx_x4_status1_scr_modes_T_SCR_MODE_100G 3 5494 #define rx_x4_status1_scr_modes_T_SCR_MODE_20G 4 5495 #define rx_x4_status1_scr_modes_T_SCR_MODE_40G_4_LANE 5 5496 5497 /**************************************************************************** 5498 * Enums: rx_x4_status1_descr_modes 5499 */ 5500 #define rx_x4_status1_descr_modes_R_DESCR_MODE_BYPASS 0 5501 #define rx_x4_status1_descr_modes_R_DESCR_MODE_CL49 1 5502 #define rx_x4_status1_descr_modes_R_DESCR_MODE_CL82 2 5503 5504 /**************************************************************************** 5505 * Enums: rx_x4_status1_r_dec_tl_mode 5506 */ 5507 #define rx_x4_status1_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 5508 #define rx_x4_status1_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 5509 #define rx_x4_status1_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 5510 5511 /**************************************************************************** 5512 * Enums: rx_x4_status1_r_dec_fsm_mode 5513 */ 5514 #define rx_x4_status1_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 5515 #define rx_x4_status1_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 5516 #define rx_x4_status1_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 5517 5518 /**************************************************************************** 5519 * Enums: rx_x4_status1_r_deskew_mode 5520 */ 5521 #define rx_x4_status1_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 5522 #define rx_x4_status1_r_deskew_mode_R_DESKEW_MODE_20G 1 5523 #define rx_x4_status1_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 5524 #define rx_x4_status1_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 5525 #define rx_x4_status1_r_deskew_mode_R_DESKEW_MODE_100G 4 5526 #define rx_x4_status1_r_deskew_mode_R_DESKEW_MODE_CL49 5 5527 #define rx_x4_status1_r_deskew_mode_R_DESKEW_MODE_CL91 6 5528 5529 /**************************************************************************** 5530 * Enums: rx_x4_status1_bs_dist_modes 5531 */ 5532 #define rx_x4_status1_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 5533 #define rx_x4_status1_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 5534 #define rx_x4_status1_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 5535 #define rx_x4_status1_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 5536 5537 /**************************************************************************** 5538 * Enums: rx_x4_status1_cl49_t_type 5539 */ 5540 #define rx_x4_status1_cl49_t_type_BAD_T_TYPE 15 5541 #define rx_x4_status1_cl49_t_type_T_TYPE_B0 11 5542 #define rx_x4_status1_cl49_t_type_T_TYPE_OB 10 5543 #define rx_x4_status1_cl49_t_type_T_TYPE_B1 9 5544 #define rx_x4_status1_cl49_t_type_T_TYPE_DB 8 5545 #define rx_x4_status1_cl49_t_type_T_TYPE_FC 7 5546 #define rx_x4_status1_cl49_t_type_T_TYPE_TB 6 5547 #define rx_x4_status1_cl49_t_type_T_TYPE_LI 5 5548 #define rx_x4_status1_cl49_t_type_T_TYPE_C 4 5549 #define rx_x4_status1_cl49_t_type_T_TYPE_S 3 5550 #define rx_x4_status1_cl49_t_type_T_TYPE_T 2 5551 #define rx_x4_status1_cl49_t_type_T_TYPE_D 1 5552 #define rx_x4_status1_cl49_t_type_T_TYPE_E 0 5553 5554 /**************************************************************************** 5555 * Enums: rx_x4_status1_cl49_txsm_states 5556 */ 5557 #define rx_x4_status1_cl49_txsm_states_TX_HIG_END 7 5558 #define rx_x4_status1_cl49_txsm_states_TX_HIG_START 6 5559 #define rx_x4_status1_cl49_txsm_states_TX_LI 5 5560 #define rx_x4_status1_cl49_txsm_states_TX_E 4 5561 #define rx_x4_status1_cl49_txsm_states_TX_T 3 5562 #define rx_x4_status1_cl49_txsm_states_TX_D 2 5563 #define rx_x4_status1_cl49_txsm_states_TX_C 1 5564 #define rx_x4_status1_cl49_txsm_states_TX_INIT 0 5565 5566 /**************************************************************************** 5567 * Enums: rx_x4_status1_cl49_ltxsm_states 5568 */ 5569 #define rx_x4_status1_cl49_ltxsm_states_TX_HIG_END 128 5570 #define rx_x4_status1_cl49_ltxsm_states_TX_HIG_START 64 5571 #define rx_x4_status1_cl49_ltxsm_states_TX_LI 32 5572 #define rx_x4_status1_cl49_ltxsm_states_TX_E 16 5573 #define rx_x4_status1_cl49_ltxsm_states_TX_T 8 5574 #define rx_x4_status1_cl49_ltxsm_states_TX_D 4 5575 #define rx_x4_status1_cl49_ltxsm_states_TX_C 2 5576 #define rx_x4_status1_cl49_ltxsm_states_TX_INIT 1 5577 5578 /**************************************************************************** 5579 * Enums: rx_x4_status1_burst_error_mode 5580 */ 5581 #define rx_x4_status1_burst_error_mode_BURST_ERROR_11_BITS 0 5582 #define rx_x4_status1_burst_error_mode_BURST_ERROR_16_BITS 1 5583 #define rx_x4_status1_burst_error_mode_BURST_ERROR_17_BITS 2 5584 #define rx_x4_status1_burst_error_mode_BURST_ERROR_18_BITS 3 5585 #define rx_x4_status1_burst_error_mode_BURST_ERROR_19_BITS 4 5586 #define rx_x4_status1_burst_error_mode_BURST_ERROR_20_BITS 5 5587 #define rx_x4_status1_burst_error_mode_BURST_ERROR_21_BITS 6 5588 #define rx_x4_status1_burst_error_mode_BURST_ERROR_22_BITS 7 5589 #define rx_x4_status1_burst_error_mode_BURST_ERROR_23_BITS 8 5590 #define rx_x4_status1_burst_error_mode_BURST_ERROR_24_BITS 9 5591 #define rx_x4_status1_burst_error_mode_BURST_ERROR_25_BITS 10 5592 #define rx_x4_status1_burst_error_mode_BURST_ERROR_26_BITS 11 5593 #define rx_x4_status1_burst_error_mode_BURST_ERROR_27_BITS 12 5594 #define rx_x4_status1_burst_error_mode_BURST_ERROR_28_BITS 13 5595 #define rx_x4_status1_burst_error_mode_BURST_ERROR_29_BITS 14 5596 #define rx_x4_status1_burst_error_mode_BURST_ERROR_30_BITS 15 5597 #define rx_x4_status1_burst_error_mode_BURST_ERROR_31_BITS 16 5598 #define rx_x4_status1_burst_error_mode_BURST_ERROR_32_BITS 17 5599 #define rx_x4_status1_burst_error_mode_BURST_ERROR_33_BITS 18 5600 #define rx_x4_status1_burst_error_mode_BURST_ERROR_34_BITS 19 5601 #define rx_x4_status1_burst_error_mode_BURST_ERROR_35_BITS 20 5602 #define rx_x4_status1_burst_error_mode_BURST_ERROR_36_BITS 21 5603 #define rx_x4_status1_burst_error_mode_BURST_ERROR_37_BITS 22 5604 #define rx_x4_status1_burst_error_mode_BURST_ERROR_38_BITS 23 5605 #define rx_x4_status1_burst_error_mode_BURST_ERROR_39_BITS 24 5606 #define rx_x4_status1_burst_error_mode_BURST_ERROR_40_BITS 25 5607 #define rx_x4_status1_burst_error_mode_BURST_ERROR_41_BITS 26 5608 5609 /**************************************************************************** 5610 * Enums: rx_x4_status1_bermon_state 5611 */ 5612 #define rx_x4_status1_bermon_state_HI_BER 4 5613 #define rx_x4_status1_bermon_state_GOOD_BER 3 5614 #define rx_x4_status1_bermon_state_BER_TEST_SH 2 5615 #define rx_x4_status1_bermon_state_START_TIMER 1 5616 #define rx_x4_status1_bermon_state_BER_MT_INIT 0 5617 5618 /**************************************************************************** 5619 * Enums: rx_x4_status1_rxsm_state_cl49 5620 */ 5621 #define rx_x4_status1_rxsm_state_cl49_RX_HIG_END 128 5622 #define rx_x4_status1_rxsm_state_cl49_RX_HIG_START 64 5623 #define rx_x4_status1_rxsm_state_cl49_RX_LI 32 5624 #define rx_x4_status1_rxsm_state_cl49_RX_E 16 5625 #define rx_x4_status1_rxsm_state_cl49_RX_T 8 5626 #define rx_x4_status1_rxsm_state_cl49_RX_D 4 5627 #define rx_x4_status1_rxsm_state_cl49_RX_C 2 5628 #define rx_x4_status1_rxsm_state_cl49_RX_INIT 1 5629 5630 /**************************************************************************** 5631 * Enums: rx_x4_status1_r_type 5632 */ 5633 #define rx_x4_status1_r_type_BAD_R_TYPE 15 5634 #define rx_x4_status1_r_type_R_TYPE_B0 11 5635 #define rx_x4_status1_r_type_R_TYPE_OB 10 5636 #define rx_x4_status1_r_type_R_TYPE_B1 9 5637 #define rx_x4_status1_r_type_R_TYPE_DB 8 5638 #define rx_x4_status1_r_type_R_TYPE_FC 7 5639 #define rx_x4_status1_r_type_R_TYPE_TB 6 5640 #define rx_x4_status1_r_type_R_TYPE_LI 5 5641 #define rx_x4_status1_r_type_R_TYPE_C 4 5642 #define rx_x4_status1_r_type_R_TYPE_S 3 5643 #define rx_x4_status1_r_type_R_TYPE_T 2 5644 #define rx_x4_status1_r_type_R_TYPE_D 1 5645 #define rx_x4_status1_r_type_R_TYPE_E 0 5646 5647 /**************************************************************************** 5648 * Enums: rx_x4_status1_am_lock_state 5649 */ 5650 #define rx_x4_status1_am_lock_state_INVALID_AM 512 5651 #define rx_x4_status1_am_lock_state_GOOD_AM 256 5652 #define rx_x4_status1_am_lock_state_COMP_AM 128 5653 #define rx_x4_status1_am_lock_state_TIMER_2 64 5654 #define rx_x4_status1_am_lock_state_AM_2_GOOD 32 5655 #define rx_x4_status1_am_lock_state_COMP_2ND 16 5656 #define rx_x4_status1_am_lock_state_TIMER_1 8 5657 #define rx_x4_status1_am_lock_state_FIND_1ST 4 5658 #define rx_x4_status1_am_lock_state_AM_RESET_CNT 2 5659 #define rx_x4_status1_am_lock_state_AM_LOCK_INIT 1 5660 5661 /**************************************************************************** 5662 * Enums: rx_x4_status1_msg_selector 5663 */ 5664 #define rx_x4_status1_msg_selector_RESERVED 0 5665 #define rx_x4_status1_msg_selector_VALUE_802p3 1 5666 #define rx_x4_status1_msg_selector_VALUE_802p9 2 5667 #define rx_x4_status1_msg_selector_VALUE_802p5 3 5668 #define rx_x4_status1_msg_selector_VALUE_1394 4 5669 5670 /**************************************************************************** 5671 * Enums: rx_x4_status1_synce_enum 5672 */ 5673 #define rx_x4_status1_synce_enum_SYNCE_NO_DIV 0 5674 #define rx_x4_status1_synce_enum_SYNCE_DIV_7 1 5675 #define rx_x4_status1_synce_enum_SYNCE_DIV_11 2 5676 5677 /**************************************************************************** 5678 * Enums: rx_x4_status1_synce_enum_stage0 5679 */ 5680 #define rx_x4_status1_synce_enum_stage0_SYNCE_NO_DIV 0 5681 #define rx_x4_status1_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 5682 #define rx_x4_status1_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 5683 5684 /**************************************************************************** 5685 * Enums: rx_x4_status1_cl91_sync_state 5686 */ 5687 #define rx_x4_status1_cl91_sync_state_FIND_1ST 0 5688 #define rx_x4_status1_cl91_sync_state_COUNT_NEXT 1 5689 #define rx_x4_status1_cl91_sync_state_COMP_2ND 2 5690 #define rx_x4_status1_cl91_sync_state_TWO_GOOD 3 5691 5692 /**************************************************************************** 5693 * Enums: rx_x4_status1_cl91_algn_state 5694 */ 5695 #define rx_x4_status1_cl91_algn_state_LOSS_OF_ALIGNMENT 0 5696 #define rx_x4_status1_cl91_algn_state_DESKEW 1 5697 #define rx_x4_status1_cl91_algn_state_DESKEW_FAIL 2 5698 #define rx_x4_status1_cl91_algn_state_ALIGN_ACQUIRED 3 5699 #define rx_x4_status1_cl91_algn_state_CW_GOOD 4 5700 #define rx_x4_status1_cl91_algn_state_CW_BAD 5 5701 #define rx_x4_status1_cl91_algn_state_THREE_BAD 6 5702 5703 /**************************************************************************** 5704 * Enums: rx_x4_status1_fec_sel 5705 */ 5706 #define rx_x4_status1_fec_sel_NO_FEC 0 5707 #define rx_x4_status1_fec_sel_FEC_CL74 1 5708 #define rx_x4_status1_fec_sel_FEC_CL91 2 5709 5710 /**************************************************************************** 5711 * Enums: rx_x4_status2_cl36TxEEEStates_l 5712 */ 5713 #define rx_x4_status2_cl36TxEEEStates_l_TX_REFRESH 8 5714 #define rx_x4_status2_cl36TxEEEStates_l_TX_QUIET 4 5715 #define rx_x4_status2_cl36TxEEEStates_l_TX_SLEEP 2 5716 #define rx_x4_status2_cl36TxEEEStates_l_TX_ACTIVE 1 5717 5718 /**************************************************************************** 5719 * Enums: rx_x4_status2_cl36TxEEEStates_c 5720 */ 5721 #define rx_x4_status2_cl36TxEEEStates_c_TX_REFRESH 3 5722 #define rx_x4_status2_cl36TxEEEStates_c_TX_QUIET 2 5723 #define rx_x4_status2_cl36TxEEEStates_c_TX_SLEEP 1 5724 #define rx_x4_status2_cl36TxEEEStates_c_TX_ACTIVE 0 5725 5726 /**************************************************************************** 5727 * Enums: rx_x4_status2_cl49TxEEEStates_l 5728 */ 5729 #define rx_x4_status2_cl49TxEEEStates_l_SCR_RESET_2 64 5730 #define rx_x4_status2_cl49TxEEEStates_l_SCR_RESET_1 32 5731 #define rx_x4_status2_cl49TxEEEStates_l_TX_WAKE 16 5732 #define rx_x4_status2_cl49TxEEEStates_l_TX_REFRESH 8 5733 #define rx_x4_status2_cl49TxEEEStates_l_TX_QUIET 4 5734 #define rx_x4_status2_cl49TxEEEStates_l_TX_SLEEP 2 5735 #define rx_x4_status2_cl49TxEEEStates_l_TX_ACTIVE 1 5736 5737 /**************************************************************************** 5738 * Enums: rx_x4_status2_fec_req_enum 5739 */ 5740 #define rx_x4_status2_fec_req_enum_FEC_not_supported 0 5741 #define rx_x4_status2_fec_req_enum_FEC_supported_but_not_requested 1 5742 #define rx_x4_status2_fec_req_enum_invalid_setting 2 5743 #define rx_x4_status2_fec_req_enum_FEC_supported_and_requested 3 5744 5745 /**************************************************************************** 5746 * Enums: rx_x4_status2_cl73_pause_enum 5747 */ 5748 #define rx_x4_status2_cl73_pause_enum_No_PAUSE_ability 0 5749 #define rx_x4_status2_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 5750 #define rx_x4_status2_cl73_pause_enum_Symmetric_PAUSE_ability 1 5751 #define rx_x4_status2_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 5752 5753 /**************************************************************************** 5754 * Enums: rx_x4_status2_cl49TxEEEStates_c 5755 */ 5756 #define rx_x4_status2_cl49TxEEEStates_c_SCR_RESET_2 6 5757 #define rx_x4_status2_cl49TxEEEStates_c_SCR_RESET_1 5 5758 #define rx_x4_status2_cl49TxEEEStates_c_TX_WAKE 4 5759 #define rx_x4_status2_cl49TxEEEStates_c_TX_REFRESH 3 5760 #define rx_x4_status2_cl49TxEEEStates_c_TX_QUIET 2 5761 #define rx_x4_status2_cl49TxEEEStates_c_TX_SLEEP 1 5762 #define rx_x4_status2_cl49TxEEEStates_c_TX_ACTIVE 0 5763 5764 /**************************************************************************** 5765 * Enums: rx_x4_status2_cl36RxEEEStates_l 5766 */ 5767 #define rx_x4_status2_cl36RxEEEStates_l_RX_LINK_FAIL 32 5768 #define rx_x4_status2_cl36RxEEEStates_l_RX_WTF 16 5769 #define rx_x4_status2_cl36RxEEEStates_l_RX_WAKE 8 5770 #define rx_x4_status2_cl36RxEEEStates_l_RX_QUIET 4 5771 #define rx_x4_status2_cl36RxEEEStates_l_RX_SLEEP 2 5772 #define rx_x4_status2_cl36RxEEEStates_l_RX_ACTIVE 1 5773 5774 /**************************************************************************** 5775 * Enums: rx_x4_status2_cl36RxEEEStates_c 5776 */ 5777 #define rx_x4_status2_cl36RxEEEStates_c_RX_LINK_FAIL 5 5778 #define rx_x4_status2_cl36RxEEEStates_c_RX_WTF 4 5779 #define rx_x4_status2_cl36RxEEEStates_c_RX_WAKE 3 5780 #define rx_x4_status2_cl36RxEEEStates_c_RX_QUIET 2 5781 #define rx_x4_status2_cl36RxEEEStates_c_RX_SLEEP 1 5782 #define rx_x4_status2_cl36RxEEEStates_c_RX_ACTIVE 0 5783 5784 /**************************************************************************** 5785 * Enums: rx_x4_status2_cl49RxEEEStates_l 5786 */ 5787 #define rx_x4_status2_cl49RxEEEStates_l_RX_LINK_FAIL 32 5788 #define rx_x4_status2_cl49RxEEEStates_l_RX_WTF 16 5789 #define rx_x4_status2_cl49RxEEEStates_l_RX_WAKE 8 5790 #define rx_x4_status2_cl49RxEEEStates_l_RX_QUIET 4 5791 #define rx_x4_status2_cl49RxEEEStates_l_RX_SLEEP 2 5792 #define rx_x4_status2_cl49RxEEEStates_l_RX_ACTIVE 1 5793 5794 /**************************************************************************** 5795 * Enums: rx_x4_status2_cl49RxEEEStates_c 5796 */ 5797 #define rx_x4_status2_cl49RxEEEStates_c_RX_LINK_FAIL 5 5798 #define rx_x4_status2_cl49RxEEEStates_c_RX_WTF 4 5799 #define rx_x4_status2_cl49RxEEEStates_c_RX_WAKE 3 5800 #define rx_x4_status2_cl49RxEEEStates_c_RX_QUIET 2 5801 #define rx_x4_status2_cl49RxEEEStates_c_RX_SLEEP 1 5802 #define rx_x4_status2_cl49RxEEEStates_c_RX_ACTIVE 0 5803 5804 /**************************************************************************** 5805 * Enums: rx_x4_status2_cl48TxEEEStates_l 5806 */ 5807 #define rx_x4_status2_cl48TxEEEStates_l_TX_REFRESH 8 5808 #define rx_x4_status2_cl48TxEEEStates_l_TX_QUIET 4 5809 #define rx_x4_status2_cl48TxEEEStates_l_TX_SLEEP 2 5810 #define rx_x4_status2_cl48TxEEEStates_l_TX_ACTIVE 1 5811 5812 /**************************************************************************** 5813 * Enums: rx_x4_status2_cl48TxEEEStates_c 5814 */ 5815 #define rx_x4_status2_cl48TxEEEStates_c_TX_REFRESH 3 5816 #define rx_x4_status2_cl48TxEEEStates_c_TX_QUIET 2 5817 #define rx_x4_status2_cl48TxEEEStates_c_TX_SLEEP 1 5818 #define rx_x4_status2_cl48TxEEEStates_c_TX_ACTIVE 0 5819 5820 /**************************************************************************** 5821 * Enums: rx_x4_status2_cl48RxEEEStates_l 5822 */ 5823 #define rx_x4_status2_cl48RxEEEStates_l_RX_LINK_FAIL 32 5824 #define rx_x4_status2_cl48RxEEEStates_l_RX_WAKE 16 5825 #define rx_x4_status2_cl48RxEEEStates_l_RX_QUIET 8 5826 #define rx_x4_status2_cl48RxEEEStates_l_RX_DEACT 4 5827 #define rx_x4_status2_cl48RxEEEStates_l_RX_SLEEP 2 5828 #define rx_x4_status2_cl48RxEEEStates_l_RX_ACTIVE 1 5829 5830 /**************************************************************************** 5831 * Enums: rx_x4_status2_cl48RxEEEStates_c 5832 */ 5833 #define rx_x4_status2_cl48RxEEEStates_c_RX_LINK_FAIL 5 5834 #define rx_x4_status2_cl48RxEEEStates_c_RX_WAKE 4 5835 #define rx_x4_status2_cl48RxEEEStates_c_RX_QUIET 3 5836 #define rx_x4_status2_cl48RxEEEStates_c_RX_DEACT 2 5837 #define rx_x4_status2_cl48RxEEEStates_c_RX_SLEEP 1 5838 #define rx_x4_status2_cl48RxEEEStates_c_RX_ACTIVE 0 5839 5840 /**************************************************************************** 5841 * Enums: rx_x4_status2_IQP_Options 5842 */ 5843 #define rx_x4_status2_IQP_Options_i50uA 0 5844 #define rx_x4_status2_IQP_Options_i100uA 1 5845 #define rx_x4_status2_IQP_Options_i150uA 2 5846 #define rx_x4_status2_IQP_Options_i200uA 3 5847 #define rx_x4_status2_IQP_Options_i250uA 4 5848 #define rx_x4_status2_IQP_Options_i300uA 5 5849 #define rx_x4_status2_IQP_Options_i350uA 6 5850 #define rx_x4_status2_IQP_Options_i400uA 7 5851 #define rx_x4_status2_IQP_Options_i450uA 8 5852 #define rx_x4_status2_IQP_Options_i500uA 9 5853 #define rx_x4_status2_IQP_Options_i550uA 10 5854 #define rx_x4_status2_IQP_Options_i600uA 11 5855 #define rx_x4_status2_IQP_Options_i650uA 12 5856 #define rx_x4_status2_IQP_Options_i700uA 13 5857 #define rx_x4_status2_IQP_Options_i750uA 14 5858 #define rx_x4_status2_IQP_Options_i800uA 15 5859 5860 /**************************************************************************** 5861 * Enums: rx_x4_status2_IDriver_Options 5862 */ 5863 #define rx_x4_status2_IDriver_Options_v680mV 0 5864 #define rx_x4_status2_IDriver_Options_v730mV 1 5865 #define rx_x4_status2_IDriver_Options_v780mV 2 5866 #define rx_x4_status2_IDriver_Options_v830mV 3 5867 #define rx_x4_status2_IDriver_Options_v880mV 4 5868 #define rx_x4_status2_IDriver_Options_v930mV 5 5869 #define rx_x4_status2_IDriver_Options_v980mV 6 5870 #define rx_x4_status2_IDriver_Options_v1010mV 7 5871 #define rx_x4_status2_IDriver_Options_v1040mV 8 5872 #define rx_x4_status2_IDriver_Options_v1060mV 9 5873 #define rx_x4_status2_IDriver_Options_v1070mV 10 5874 #define rx_x4_status2_IDriver_Options_v1080mV 11 5875 #define rx_x4_status2_IDriver_Options_v1085mV 12 5876 #define rx_x4_status2_IDriver_Options_v1090mV 13 5877 #define rx_x4_status2_IDriver_Options_v1095mV 14 5878 #define rx_x4_status2_IDriver_Options_v1100mV 15 5879 5880 /**************************************************************************** 5881 * Enums: rx_x4_status2_operationModes 5882 */ 5883 #define rx_x4_status2_operationModes_XGXS 0 5884 #define rx_x4_status2_operationModes_XGXG_nCC 1 5885 #define rx_x4_status2_operationModes_Indlane_OS8 4 5886 #define rx_x4_status2_operationModes_IndLane_OS5 5 5887 #define rx_x4_status2_operationModes_PCI 7 5888 #define rx_x4_status2_operationModes_XGXS_nLQ 8 5889 #define rx_x4_status2_operationModes_XGXS_nLQnCC 9 5890 #define rx_x4_status2_operationModes_PBypass 10 5891 #define rx_x4_status2_operationModes_PBypass_nDSK 11 5892 #define rx_x4_status2_operationModes_ComboCoreMode 12 5893 #define rx_x4_status2_operationModes_Clocks_off 15 5894 5895 /**************************************************************************** 5896 * Enums: rx_x4_status2_actualSpeeds 5897 */ 5898 #define rx_x4_status2_actualSpeeds_dr_10M 0 5899 #define rx_x4_status2_actualSpeeds_dr_100M 1 5900 #define rx_x4_status2_actualSpeeds_dr_1G 2 5901 #define rx_x4_status2_actualSpeeds_dr_2p5G 3 5902 #define rx_x4_status2_actualSpeeds_dr_5G_X4 4 5903 #define rx_x4_status2_actualSpeeds_dr_6G_X4 5 5904 #define rx_x4_status2_actualSpeeds_dr_10G_HiG 6 5905 #define rx_x4_status2_actualSpeeds_dr_10G_CX4 7 5906 #define rx_x4_status2_actualSpeeds_dr_12G_HiG 8 5907 #define rx_x4_status2_actualSpeeds_dr_12p5G_X4 9 5908 #define rx_x4_status2_actualSpeeds_dr_13G_X4 10 5909 #define rx_x4_status2_actualSpeeds_dr_15G_X4 11 5910 #define rx_x4_status2_actualSpeeds_dr_16G_X4 12 5911 #define rx_x4_status2_actualSpeeds_dr_1G_KX 13 5912 #define rx_x4_status2_actualSpeeds_dr_10G_KX4 14 5913 #define rx_x4_status2_actualSpeeds_dr_10G_KR 15 5914 #define rx_x4_status2_actualSpeeds_dr_5G 16 5915 #define rx_x4_status2_actualSpeeds_dr_6p4G 17 5916 #define rx_x4_status2_actualSpeeds_dr_20G_X4 18 5917 #define rx_x4_status2_actualSpeeds_dr_21G_X4 19 5918 #define rx_x4_status2_actualSpeeds_dr_25G_X4 20 5919 #define rx_x4_status2_actualSpeeds_dr_10G_HiG_DXGXS 21 5920 #define rx_x4_status2_actualSpeeds_dr_10G_DXGXS 22 5921 #define rx_x4_status2_actualSpeeds_dr_10p5G_HiG_DXGXS 23 5922 #define rx_x4_status2_actualSpeeds_dr_10p5G_DXGXS 24 5923 #define rx_x4_status2_actualSpeeds_dr_12p773G_HiG_DXGXS 25 5924 #define rx_x4_status2_actualSpeeds_dr_12p773G_DXGXS 26 5925 #define rx_x4_status2_actualSpeeds_dr_10G_XFI 27 5926 #define rx_x4_status2_actualSpeeds_dr_40G 28 5927 #define rx_x4_status2_actualSpeeds_dr_20G_HiG_DXGXS 29 5928 #define rx_x4_status2_actualSpeeds_dr_20G_DXGXS 30 5929 #define rx_x4_status2_actualSpeeds_dr_10G_SFI 31 5930 #define rx_x4_status2_actualSpeeds_dr_31p5G 32 5931 #define rx_x4_status2_actualSpeeds_dr_32p7G 33 5932 #define rx_x4_status2_actualSpeeds_dr_20G_SCR 34 5933 #define rx_x4_status2_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 5934 #define rx_x4_status2_actualSpeeds_dr_10G_DXGXS_SCR 36 5935 #define rx_x4_status2_actualSpeeds_dr_12G_R2 37 5936 #define rx_x4_status2_actualSpeeds_dr_10G_X2 38 5937 #define rx_x4_status2_actualSpeeds_dr_40G_KR4 39 5938 #define rx_x4_status2_actualSpeeds_dr_40G_CR4 40 5939 #define rx_x4_status2_actualSpeeds_dr_100G_CR10 41 5940 #define rx_x4_status2_actualSpeeds_dr_15p75G_DXGXS 44 5941 #define rx_x4_status2_actualSpeeds_dr_20G_KR2 57 5942 #define rx_x4_status2_actualSpeeds_dr_20G_CR2 58 5943 5944 /**************************************************************************** 5945 * Enums: rx_x4_status2_actualSpeedsMisc1 5946 */ 5947 #define rx_x4_status2_actualSpeedsMisc1_dr_2500BRCM_X1 16 5948 #define rx_x4_status2_actualSpeedsMisc1_dr_5000BRCM_X4 17 5949 #define rx_x4_status2_actualSpeedsMisc1_dr_6000BRCM_X4 18 5950 #define rx_x4_status2_actualSpeedsMisc1_dr_10GHiGig_X4 19 5951 #define rx_x4_status2_actualSpeedsMisc1_dr_10GBASE_CX4 20 5952 #define rx_x4_status2_actualSpeedsMisc1_dr_12GHiGig_X4 21 5953 #define rx_x4_status2_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 5954 #define rx_x4_status2_actualSpeedsMisc1_dr_13GHiGig_X4 23 5955 #define rx_x4_status2_actualSpeedsMisc1_dr_15GHiGig_X4 24 5956 #define rx_x4_status2_actualSpeedsMisc1_dr_16GHiGig_X4 25 5957 #define rx_x4_status2_actualSpeedsMisc1_dr_5000BRCM_X1 26 5958 #define rx_x4_status2_actualSpeedsMisc1_dr_6363BRCM_X1 27 5959 #define rx_x4_status2_actualSpeedsMisc1_dr_20GHiGig_X4 28 5960 #define rx_x4_status2_actualSpeedsMisc1_dr_21GHiGig_X4 29 5961 #define rx_x4_status2_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 5962 #define rx_x4_status2_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 5963 5964 /**************************************************************************** 5965 * Enums: rx_x4_status2_IndLaneModes 5966 */ 5967 #define rx_x4_status2_IndLaneModes_SWSDR_div2 0 5968 #define rx_x4_status2_IndLaneModes_SWSDR_div1 1 5969 #define rx_x4_status2_IndLaneModes_DWSDR_div2 2 5970 #define rx_x4_status2_IndLaneModes_DWSDR_div1 3 5971 5972 /**************************************************************************** 5973 * Enums: rx_x4_status2_prbsSelect 5974 */ 5975 #define rx_x4_status2_prbsSelect_prbs7 0 5976 #define rx_x4_status2_prbsSelect_prbs15 1 5977 #define rx_x4_status2_prbsSelect_prbs23 2 5978 #define rx_x4_status2_prbsSelect_prbs31 3 5979 5980 /**************************************************************************** 5981 * Enums: rx_x4_status2_vcoDivider 5982 */ 5983 #define rx_x4_status2_vcoDivider_div32 0 5984 #define rx_x4_status2_vcoDivider_div36 1 5985 #define rx_x4_status2_vcoDivider_div40 2 5986 #define rx_x4_status2_vcoDivider_div42 3 5987 #define rx_x4_status2_vcoDivider_div48 4 5988 #define rx_x4_status2_vcoDivider_div50 5 5989 #define rx_x4_status2_vcoDivider_div52 6 5990 #define rx_x4_status2_vcoDivider_div54 7 5991 #define rx_x4_status2_vcoDivider_div60 8 5992 #define rx_x4_status2_vcoDivider_div64 9 5993 #define rx_x4_status2_vcoDivider_div66 10 5994 #define rx_x4_status2_vcoDivider_div68 11 5995 #define rx_x4_status2_vcoDivider_div70 12 5996 #define rx_x4_status2_vcoDivider_div80 13 5997 #define rx_x4_status2_vcoDivider_div92 14 5998 #define rx_x4_status2_vcoDivider_div100 15 5999 6000 /**************************************************************************** 6001 * Enums: rx_x4_status2_refClkSelect 6002 */ 6003 #define rx_x4_status2_refClkSelect_clk_25MHz 0 6004 #define rx_x4_status2_refClkSelect_clk_100MHz 1 6005 #define rx_x4_status2_refClkSelect_clk_125MHz 2 6006 #define rx_x4_status2_refClkSelect_clk_156p25MHz 3 6007 #define rx_x4_status2_refClkSelect_clk_187p5MHz 4 6008 #define rx_x4_status2_refClkSelect_clk_161p25Mhz 5 6009 #define rx_x4_status2_refClkSelect_clk_50Mhz 6 6010 #define rx_x4_status2_refClkSelect_clk_106p25Mhz 7 6011 6012 /**************************************************************************** 6013 * Enums: rx_x4_status2_aerMMDdevTypeSelect 6014 */ 6015 #define rx_x4_status2_aerMMDdevTypeSelect_combo_core 0 6016 #define rx_x4_status2_aerMMDdevTypeSelect_PMA_PMD 1 6017 #define rx_x4_status2_aerMMDdevTypeSelect_PCS 3 6018 #define rx_x4_status2_aerMMDdevTypeSelect_PHY 4 6019 #define rx_x4_status2_aerMMDdevTypeSelect_DTE 5 6020 #define rx_x4_status2_aerMMDdevTypeSelect_CL73_AN 7 6021 6022 /**************************************************************************** 6023 * Enums: rx_x4_status2_aerMMDportSelect 6024 */ 6025 #define rx_x4_status2_aerMMDportSelect_ln0 0 6026 #define rx_x4_status2_aerMMDportSelect_ln1 1 6027 #define rx_x4_status2_aerMMDportSelect_ln2 2 6028 #define rx_x4_status2_aerMMDportSelect_ln3 3 6029 #define rx_x4_status2_aerMMDportSelect_BCST_ln0_1_2_3 511 6030 #define rx_x4_status2_aerMMDportSelect_BCST_ln0_1 512 6031 #define rx_x4_status2_aerMMDportSelect_BCST_ln2_3 513 6032 6033 /**************************************************************************** 6034 * Enums: rx_x4_status2_firmwareModeSelect 6035 */ 6036 #define rx_x4_status2_firmwareModeSelect_DEFAULT 0 6037 #define rx_x4_status2_firmwareModeSelect_SFP_OPT_LR 1 6038 #define rx_x4_status2_firmwareModeSelect_SFP_DAC 2 6039 #define rx_x4_status2_firmwareModeSelect_XLAUI 3 6040 #define rx_x4_status2_firmwareModeSelect_LONG_CH_6G 4 6041 6042 /**************************************************************************** 6043 * Enums: rx_x4_status2_tempIdxSelect 6044 */ 6045 #define rx_x4_status2_tempIdxSelect_LTE__22p9C 15 6046 #define rx_x4_status2_tempIdxSelect_LTE__12p6C 14 6047 #define rx_x4_status2_tempIdxSelect_LTE__3p0C 13 6048 #define rx_x4_status2_tempIdxSelect_LTE_6p7C 12 6049 #define rx_x4_status2_tempIdxSelect_LTE_16p4C 11 6050 #define rx_x4_status2_tempIdxSelect_LTE_26p6C 10 6051 #define rx_x4_status2_tempIdxSelect_LTE_36p3C 9 6052 #define rx_x4_status2_tempIdxSelect_LTE_46p0C 8 6053 #define rx_x4_status2_tempIdxSelect_LTE_56p2C 7 6054 #define rx_x4_status2_tempIdxSelect_LTE_65p9C 6 6055 #define rx_x4_status2_tempIdxSelect_LTE_75p6C 5 6056 #define rx_x4_status2_tempIdxSelect_LTE_85p3C 4 6057 #define rx_x4_status2_tempIdxSelect_LTE_95p5C 3 6058 #define rx_x4_status2_tempIdxSelect_LTE_105p2C 2 6059 #define rx_x4_status2_tempIdxSelect_LTE_114p9C 1 6060 #define rx_x4_status2_tempIdxSelect_LTE_125p1C 0 6061 6062 /**************************************************************************** 6063 * Enums: rx_x4_status2_port_mode 6064 */ 6065 #define rx_x4_status2_port_mode_QUAD_PORT 0 6066 #define rx_x4_status2_port_mode_TRI_1_PORT 1 6067 #define rx_x4_status2_port_mode_TRI_2_PORT 2 6068 #define rx_x4_status2_port_mode_DUAL_PORT 3 6069 #define rx_x4_status2_port_mode_SINGLE_PORT 4 6070 6071 /**************************************************************************** 6072 * Enums: rx_x4_status2_rev_letter_enum 6073 */ 6074 #define rx_x4_status2_rev_letter_enum_REV_A 0 6075 #define rx_x4_status2_rev_letter_enum_REV_B 1 6076 #define rx_x4_status2_rev_letter_enum_REV_C 2 6077 #define rx_x4_status2_rev_letter_enum_REV_D 3 6078 6079 /**************************************************************************** 6080 * Enums: rx_x4_status2_rev_number_enum 6081 */ 6082 #define rx_x4_status2_rev_number_enum_REV_0 0 6083 #define rx_x4_status2_rev_number_enum_REV_1 1 6084 #define rx_x4_status2_rev_number_enum_REV_2 2 6085 #define rx_x4_status2_rev_number_enum_REV_3 3 6086 #define rx_x4_status2_rev_number_enum_REV_4 4 6087 #define rx_x4_status2_rev_number_enum_REV_5 5 6088 #define rx_x4_status2_rev_number_enum_REV_6 6 6089 #define rx_x4_status2_rev_number_enum_REV_7 7 6090 6091 /**************************************************************************** 6092 * Enums: rx_x4_status2_bonding_enum 6093 */ 6094 #define rx_x4_status2_bonding_enum_WIRE_BOND 0 6095 #define rx_x4_status2_bonding_enum_FLIP_CHIP 1 6096 6097 /**************************************************************************** 6098 * Enums: rx_x4_status2_tech_process 6099 */ 6100 #define rx_x4_status2_tech_process_PROCESS_90NM 0 6101 #define rx_x4_status2_tech_process_PROCESS_65NM 1 6102 #define rx_x4_status2_tech_process_PROCESS_40NM 2 6103 #define rx_x4_status2_tech_process_PROCESS_28NM 3 6104 6105 /**************************************************************************** 6106 * Enums: rx_x4_status2_model_num 6107 */ 6108 #define rx_x4_status2_model_num_SERDES_CL73 0 6109 #define rx_x4_status2_model_num_XGXS_16G 1 6110 #define rx_x4_status2_model_num_HYPERCORE 2 6111 #define rx_x4_status2_model_num_HYPERLITE 3 6112 #define rx_x4_status2_model_num_PCIE_G2_PIPE 4 6113 #define rx_x4_status2_model_num_SERDES_1p25GBd 5 6114 #define rx_x4_status2_model_num_SATA2 6 6115 #define rx_x4_status2_model_num_QSGMII 7 6116 #define rx_x4_status2_model_num_XGXS10G 8 6117 #define rx_x4_status2_model_num_WARPCORE 9 6118 #define rx_x4_status2_model_num_XFICORE 10 6119 #define rx_x4_status2_model_num_RXFI 11 6120 #define rx_x4_status2_model_num_WARPLITE 12 6121 #define rx_x4_status2_model_num_PENTACORE 13 6122 #define rx_x4_status2_model_num_ESM 14 6123 #define rx_x4_status2_model_num_QUAD_SGMII 15 6124 #define rx_x4_status2_model_num_WARPCORE_3 16 6125 #define rx_x4_status2_model_num_TSC 17 6126 #define rx_x4_status2_model_num_TSC4E 18 6127 #define rx_x4_status2_model_num_TSC12E 19 6128 #define rx_x4_status2_model_num_TSC4F 20 6129 #define rx_x4_status2_model_num_XGXS_CL73_90NM 29 6130 #define rx_x4_status2_model_num_SERDES_CL73_90NM 30 6131 #define rx_x4_status2_model_num_WARPCORE3 32 6132 #define rx_x4_status2_model_num_WARPCORE4_TSC 33 6133 #define rx_x4_status2_model_num_RXAUI 34 6134 6135 /**************************************************************************** 6136 * Enums: rx_x4_status2_payload 6137 */ 6138 #define rx_x4_status2_payload_REPEAT_2_BYTES 0 6139 #define rx_x4_status2_payload_RAMPING 1 6140 #define rx_x4_status2_payload_CL48_CRPAT 2 6141 #define rx_x4_status2_payload_CL48_CJPAT 3 6142 #define rx_x4_status2_payload_CL36_LONG_CRPAT 4 6143 #define rx_x4_status2_payload_CL36_SHORT_CRPAT 5 6144 6145 /**************************************************************************** 6146 * Enums: rx_x4_status2_sc 6147 */ 6148 #define rx_x4_status2_sc_S_10G_CR1 0 6149 #define rx_x4_status2_sc_S_10G_KR1 1 6150 #define rx_x4_status2_sc_S_10G_X1 2 6151 #define rx_x4_status2_sc_S_10G_HG2_CR1 4 6152 #define rx_x4_status2_sc_S_10G_HG2_KR1 5 6153 #define rx_x4_status2_sc_S_10G_HG2_X1 6 6154 #define rx_x4_status2_sc_S_20G_CR1 8 6155 #define rx_x4_status2_sc_S_20G_KR1 9 6156 #define rx_x4_status2_sc_S_20G_X1 10 6157 #define rx_x4_status2_sc_S_20G_HG2_CR1 12 6158 #define rx_x4_status2_sc_S_20G_HG2_KR1 13 6159 #define rx_x4_status2_sc_S_20G_HG2_X1 14 6160 #define rx_x4_status2_sc_S_25G_CR1 16 6161 #define rx_x4_status2_sc_S_25G_KR1 17 6162 #define rx_x4_status2_sc_S_25G_X1 18 6163 #define rx_x4_status2_sc_S_25G_HG2_CR1 20 6164 #define rx_x4_status2_sc_S_25G_HG2_KR1 21 6165 #define rx_x4_status2_sc_S_25G_HG2_X1 22 6166 #define rx_x4_status2_sc_S_20G_CR2 24 6167 #define rx_x4_status2_sc_S_20G_KR2 25 6168 #define rx_x4_status2_sc_S_20G_X2 26 6169 #define rx_x4_status2_sc_S_20G_HG2_CR2 28 6170 #define rx_x4_status2_sc_S_20G_HG2_KR2 29 6171 #define rx_x4_status2_sc_S_20G_HG2_X2 30 6172 #define rx_x4_status2_sc_S_40G_CR2 32 6173 #define rx_x4_status2_sc_S_40G_KR2 33 6174 #define rx_x4_status2_sc_S_40G_X2 34 6175 #define rx_x4_status2_sc_S_40G_HG2_CR2 36 6176 #define rx_x4_status2_sc_S_40G_HG2_KR2 37 6177 #define rx_x4_status2_sc_S_40G_HG2_X2 38 6178 #define rx_x4_status2_sc_S_40G_CR4 40 6179 #define rx_x4_status2_sc_S_40G_KR4 41 6180 #define rx_x4_status2_sc_S_40G_X4 42 6181 #define rx_x4_status2_sc_S_40G_HG2_CR4 44 6182 #define rx_x4_status2_sc_S_40G_HG2_KR4 45 6183 #define rx_x4_status2_sc_S_40G_HG2_X4 46 6184 #define rx_x4_status2_sc_S_50G_CR2 48 6185 #define rx_x4_status2_sc_S_50G_KR2 49 6186 #define rx_x4_status2_sc_S_50G_X2 50 6187 #define rx_x4_status2_sc_S_50G_HG2_CR2 52 6188 #define rx_x4_status2_sc_S_50G_HG2_KR2 53 6189 #define rx_x4_status2_sc_S_50G_HG2_X2 54 6190 #define rx_x4_status2_sc_S_50G_CR4 56 6191 #define rx_x4_status2_sc_S_50G_KR4 57 6192 #define rx_x4_status2_sc_S_50G_X4 58 6193 #define rx_x4_status2_sc_S_50G_HG2_CR4 60 6194 #define rx_x4_status2_sc_S_50G_HG2_KR4 61 6195 #define rx_x4_status2_sc_S_50G_HG2_X4 62 6196 #define rx_x4_status2_sc_S_100G_CR4 64 6197 #define rx_x4_status2_sc_S_100G_KR4 65 6198 #define rx_x4_status2_sc_S_100G_X4 66 6199 #define rx_x4_status2_sc_S_100G_HG2_CR4 68 6200 #define rx_x4_status2_sc_S_100G_HG2_KR4 69 6201 #define rx_x4_status2_sc_S_100G_HG2_X4 70 6202 #define rx_x4_status2_sc_S_CL73_20GVCO 72 6203 #define rx_x4_status2_sc_S_CL73_25GVCO 80 6204 #define rx_x4_status2_sc_S_CL36_20GVCO 88 6205 #define rx_x4_status2_sc_S_CL36_25GVCO 96 6206 6207 /**************************************************************************** 6208 * Enums: rx_x4_status2_t_fifo_modes 6209 */ 6210 #define rx_x4_status2_t_fifo_modes_T_FIFO_MODE_BYPASS 0 6211 #define rx_x4_status2_t_fifo_modes_T_FIFO_MODE_40G 1 6212 #define rx_x4_status2_t_fifo_modes_T_FIFO_MODE_100G 2 6213 #define rx_x4_status2_t_fifo_modes_T_FIFO_MODE_20G 3 6214 6215 /**************************************************************************** 6216 * Enums: rx_x4_status2_t_enc_modes 6217 */ 6218 #define rx_x4_status2_t_enc_modes_T_ENC_MODE_BYPASS 0 6219 #define rx_x4_status2_t_enc_modes_T_ENC_MODE_CL49 1 6220 #define rx_x4_status2_t_enc_modes_T_ENC_MODE_CL82 2 6221 6222 /**************************************************************************** 6223 * Enums: rx_x4_status2_btmx_mode 6224 */ 6225 #define rx_x4_status2_btmx_mode_BS_BTMX_MODE_1to1 0 6226 #define rx_x4_status2_btmx_mode_BS_BTMX_MODE_2to1 1 6227 #define rx_x4_status2_btmx_mode_BS_BTMX_MODE_5to1 2 6228 6229 /**************************************************************************** 6230 * Enums: rx_x4_status2_t_type_cl82 6231 */ 6232 #define rx_x4_status2_t_type_cl82_T_TYPE_B1 5 6233 #define rx_x4_status2_t_type_cl82_T_TYPE_C 4 6234 #define rx_x4_status2_t_type_cl82_T_TYPE_S 3 6235 #define rx_x4_status2_t_type_cl82_T_TYPE_T 2 6236 #define rx_x4_status2_t_type_cl82_T_TYPE_D 1 6237 #define rx_x4_status2_t_type_cl82_T_TYPE_E 0 6238 6239 /**************************************************************************** 6240 * Enums: rx_x4_status2_txsm_state_cl82 6241 */ 6242 #define rx_x4_status2_txsm_state_cl82_TX_HIG_END 6 6243 #define rx_x4_status2_txsm_state_cl82_TX_HIG_START 5 6244 #define rx_x4_status2_txsm_state_cl82_TX_E 4 6245 #define rx_x4_status2_txsm_state_cl82_TX_T 3 6246 #define rx_x4_status2_txsm_state_cl82_TX_D 2 6247 #define rx_x4_status2_txsm_state_cl82_TX_C 1 6248 #define rx_x4_status2_txsm_state_cl82_TX_INIT 0 6249 6250 /**************************************************************************** 6251 * Enums: rx_x4_status2_ltxsm_state_cl82 6252 */ 6253 #define rx_x4_status2_ltxsm_state_cl82_TX_HIG_END 64 6254 #define rx_x4_status2_ltxsm_state_cl82_TX_HIG_START 32 6255 #define rx_x4_status2_ltxsm_state_cl82_TX_E 16 6256 #define rx_x4_status2_ltxsm_state_cl82_TX_T 8 6257 #define rx_x4_status2_ltxsm_state_cl82_TX_D 4 6258 #define rx_x4_status2_ltxsm_state_cl82_TX_C 2 6259 #define rx_x4_status2_ltxsm_state_cl82_TX_INIT 1 6260 6261 /**************************************************************************** 6262 * Enums: rx_x4_status2_r_type_coded_cl82 6263 */ 6264 #define rx_x4_status2_r_type_coded_cl82_R_TYPE_B1 32 6265 #define rx_x4_status2_r_type_coded_cl82_R_TYPE_C 16 6266 #define rx_x4_status2_r_type_coded_cl82_R_TYPE_S 8 6267 #define rx_x4_status2_r_type_coded_cl82_R_TYPE_T 4 6268 #define rx_x4_status2_r_type_coded_cl82_R_TYPE_D 2 6269 #define rx_x4_status2_r_type_coded_cl82_R_TYPE_E 1 6270 6271 /**************************************************************************** 6272 * Enums: rx_x4_status2_rxsm_state_cl82 6273 */ 6274 #define rx_x4_status2_rxsm_state_cl82_RX_HIG_END 64 6275 #define rx_x4_status2_rxsm_state_cl82_RX_HIG_START 32 6276 #define rx_x4_status2_rxsm_state_cl82_RX_E 16 6277 #define rx_x4_status2_rxsm_state_cl82_RX_T 8 6278 #define rx_x4_status2_rxsm_state_cl82_RX_D 4 6279 #define rx_x4_status2_rxsm_state_cl82_RX_C 2 6280 #define rx_x4_status2_rxsm_state_cl82_RX_INIT 1 6281 6282 /**************************************************************************** 6283 * Enums: rx_x4_status2_deskew_state 6284 */ 6285 #define rx_x4_status2_deskew_state_ALIGN_ACQUIRED 2 6286 #define rx_x4_status2_deskew_state_LOSS_OF_ALIGNMENT 1 6287 6288 /**************************************************************************** 6289 * Enums: rx_x4_status2_os_mode_enum 6290 */ 6291 #define rx_x4_status2_os_mode_enum_OS_MODE_1 0 6292 #define rx_x4_status2_os_mode_enum_OS_MODE_2 1 6293 #define rx_x4_status2_os_mode_enum_OS_MODE_4 2 6294 #define rx_x4_status2_os_mode_enum_OS_MODE_16p5 8 6295 #define rx_x4_status2_os_mode_enum_OS_MODE_20p625 12 6296 6297 /**************************************************************************** 6298 * Enums: rx_x4_status2_scr_modes 6299 */ 6300 #define rx_x4_status2_scr_modes_T_SCR_MODE_BYPASS 0 6301 #define rx_x4_status2_scr_modes_T_SCR_MODE_CL49 1 6302 #define rx_x4_status2_scr_modes_T_SCR_MODE_40G_2_LANE 2 6303 #define rx_x4_status2_scr_modes_T_SCR_MODE_100G 3 6304 #define rx_x4_status2_scr_modes_T_SCR_MODE_20G 4 6305 #define rx_x4_status2_scr_modes_T_SCR_MODE_40G_4_LANE 5 6306 6307 /**************************************************************************** 6308 * Enums: rx_x4_status2_descr_modes 6309 */ 6310 #define rx_x4_status2_descr_modes_R_DESCR_MODE_BYPASS 0 6311 #define rx_x4_status2_descr_modes_R_DESCR_MODE_CL49 1 6312 #define rx_x4_status2_descr_modes_R_DESCR_MODE_CL82 2 6313 6314 /**************************************************************************** 6315 * Enums: rx_x4_status2_r_dec_tl_mode 6316 */ 6317 #define rx_x4_status2_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 6318 #define rx_x4_status2_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 6319 #define rx_x4_status2_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 6320 6321 /**************************************************************************** 6322 * Enums: rx_x4_status2_r_dec_fsm_mode 6323 */ 6324 #define rx_x4_status2_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 6325 #define rx_x4_status2_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 6326 #define rx_x4_status2_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 6327 6328 /**************************************************************************** 6329 * Enums: rx_x4_status2_r_deskew_mode 6330 */ 6331 #define rx_x4_status2_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 6332 #define rx_x4_status2_r_deskew_mode_R_DESKEW_MODE_20G 1 6333 #define rx_x4_status2_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 6334 #define rx_x4_status2_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 6335 #define rx_x4_status2_r_deskew_mode_R_DESKEW_MODE_100G 4 6336 #define rx_x4_status2_r_deskew_mode_R_DESKEW_MODE_CL49 5 6337 #define rx_x4_status2_r_deskew_mode_R_DESKEW_MODE_CL91 6 6338 6339 /**************************************************************************** 6340 * Enums: rx_x4_status2_bs_dist_modes 6341 */ 6342 #define rx_x4_status2_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 6343 #define rx_x4_status2_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 6344 #define rx_x4_status2_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 6345 #define rx_x4_status2_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 6346 6347 /**************************************************************************** 6348 * Enums: rx_x4_status2_cl49_t_type 6349 */ 6350 #define rx_x4_status2_cl49_t_type_BAD_T_TYPE 15 6351 #define rx_x4_status2_cl49_t_type_T_TYPE_B0 11 6352 #define rx_x4_status2_cl49_t_type_T_TYPE_OB 10 6353 #define rx_x4_status2_cl49_t_type_T_TYPE_B1 9 6354 #define rx_x4_status2_cl49_t_type_T_TYPE_DB 8 6355 #define rx_x4_status2_cl49_t_type_T_TYPE_FC 7 6356 #define rx_x4_status2_cl49_t_type_T_TYPE_TB 6 6357 #define rx_x4_status2_cl49_t_type_T_TYPE_LI 5 6358 #define rx_x4_status2_cl49_t_type_T_TYPE_C 4 6359 #define rx_x4_status2_cl49_t_type_T_TYPE_S 3 6360 #define rx_x4_status2_cl49_t_type_T_TYPE_T 2 6361 #define rx_x4_status2_cl49_t_type_T_TYPE_D 1 6362 #define rx_x4_status2_cl49_t_type_T_TYPE_E 0 6363 6364 /**************************************************************************** 6365 * Enums: rx_x4_status2_cl49_txsm_states 6366 */ 6367 #define rx_x4_status2_cl49_txsm_states_TX_HIG_END 7 6368 #define rx_x4_status2_cl49_txsm_states_TX_HIG_START 6 6369 #define rx_x4_status2_cl49_txsm_states_TX_LI 5 6370 #define rx_x4_status2_cl49_txsm_states_TX_E 4 6371 #define rx_x4_status2_cl49_txsm_states_TX_T 3 6372 #define rx_x4_status2_cl49_txsm_states_TX_D 2 6373 #define rx_x4_status2_cl49_txsm_states_TX_C 1 6374 #define rx_x4_status2_cl49_txsm_states_TX_INIT 0 6375 6376 /**************************************************************************** 6377 * Enums: rx_x4_status2_cl49_ltxsm_states 6378 */ 6379 #define rx_x4_status2_cl49_ltxsm_states_TX_HIG_END 128 6380 #define rx_x4_status2_cl49_ltxsm_states_TX_HIG_START 64 6381 #define rx_x4_status2_cl49_ltxsm_states_TX_LI 32 6382 #define rx_x4_status2_cl49_ltxsm_states_TX_E 16 6383 #define rx_x4_status2_cl49_ltxsm_states_TX_T 8 6384 #define rx_x4_status2_cl49_ltxsm_states_TX_D 4 6385 #define rx_x4_status2_cl49_ltxsm_states_TX_C 2 6386 #define rx_x4_status2_cl49_ltxsm_states_TX_INIT 1 6387 6388 /**************************************************************************** 6389 * Enums: rx_x4_status2_burst_error_mode 6390 */ 6391 #define rx_x4_status2_burst_error_mode_BURST_ERROR_11_BITS 0 6392 #define rx_x4_status2_burst_error_mode_BURST_ERROR_16_BITS 1 6393 #define rx_x4_status2_burst_error_mode_BURST_ERROR_17_BITS 2 6394 #define rx_x4_status2_burst_error_mode_BURST_ERROR_18_BITS 3 6395 #define rx_x4_status2_burst_error_mode_BURST_ERROR_19_BITS 4 6396 #define rx_x4_status2_burst_error_mode_BURST_ERROR_20_BITS 5 6397 #define rx_x4_status2_burst_error_mode_BURST_ERROR_21_BITS 6 6398 #define rx_x4_status2_burst_error_mode_BURST_ERROR_22_BITS 7 6399 #define rx_x4_status2_burst_error_mode_BURST_ERROR_23_BITS 8 6400 #define rx_x4_status2_burst_error_mode_BURST_ERROR_24_BITS 9 6401 #define rx_x4_status2_burst_error_mode_BURST_ERROR_25_BITS 10 6402 #define rx_x4_status2_burst_error_mode_BURST_ERROR_26_BITS 11 6403 #define rx_x4_status2_burst_error_mode_BURST_ERROR_27_BITS 12 6404 #define rx_x4_status2_burst_error_mode_BURST_ERROR_28_BITS 13 6405 #define rx_x4_status2_burst_error_mode_BURST_ERROR_29_BITS 14 6406 #define rx_x4_status2_burst_error_mode_BURST_ERROR_30_BITS 15 6407 #define rx_x4_status2_burst_error_mode_BURST_ERROR_31_BITS 16 6408 #define rx_x4_status2_burst_error_mode_BURST_ERROR_32_BITS 17 6409 #define rx_x4_status2_burst_error_mode_BURST_ERROR_33_BITS 18 6410 #define rx_x4_status2_burst_error_mode_BURST_ERROR_34_BITS 19 6411 #define rx_x4_status2_burst_error_mode_BURST_ERROR_35_BITS 20 6412 #define rx_x4_status2_burst_error_mode_BURST_ERROR_36_BITS 21 6413 #define rx_x4_status2_burst_error_mode_BURST_ERROR_37_BITS 22 6414 #define rx_x4_status2_burst_error_mode_BURST_ERROR_38_BITS 23 6415 #define rx_x4_status2_burst_error_mode_BURST_ERROR_39_BITS 24 6416 #define rx_x4_status2_burst_error_mode_BURST_ERROR_40_BITS 25 6417 #define rx_x4_status2_burst_error_mode_BURST_ERROR_41_BITS 26 6418 6419 /**************************************************************************** 6420 * Enums: rx_x4_status2_bermon_state 6421 */ 6422 #define rx_x4_status2_bermon_state_HI_BER 4 6423 #define rx_x4_status2_bermon_state_GOOD_BER 3 6424 #define rx_x4_status2_bermon_state_BER_TEST_SH 2 6425 #define rx_x4_status2_bermon_state_START_TIMER 1 6426 #define rx_x4_status2_bermon_state_BER_MT_INIT 0 6427 6428 /**************************************************************************** 6429 * Enums: rx_x4_status2_rxsm_state_cl49 6430 */ 6431 #define rx_x4_status2_rxsm_state_cl49_RX_HIG_END 128 6432 #define rx_x4_status2_rxsm_state_cl49_RX_HIG_START 64 6433 #define rx_x4_status2_rxsm_state_cl49_RX_LI 32 6434 #define rx_x4_status2_rxsm_state_cl49_RX_E 16 6435 #define rx_x4_status2_rxsm_state_cl49_RX_T 8 6436 #define rx_x4_status2_rxsm_state_cl49_RX_D 4 6437 #define rx_x4_status2_rxsm_state_cl49_RX_C 2 6438 #define rx_x4_status2_rxsm_state_cl49_RX_INIT 1 6439 6440 /**************************************************************************** 6441 * Enums: rx_x4_status2_r_type 6442 */ 6443 #define rx_x4_status2_r_type_BAD_R_TYPE 15 6444 #define rx_x4_status2_r_type_R_TYPE_B0 11 6445 #define rx_x4_status2_r_type_R_TYPE_OB 10 6446 #define rx_x4_status2_r_type_R_TYPE_B1 9 6447 #define rx_x4_status2_r_type_R_TYPE_DB 8 6448 #define rx_x4_status2_r_type_R_TYPE_FC 7 6449 #define rx_x4_status2_r_type_R_TYPE_TB 6 6450 #define rx_x4_status2_r_type_R_TYPE_LI 5 6451 #define rx_x4_status2_r_type_R_TYPE_C 4 6452 #define rx_x4_status2_r_type_R_TYPE_S 3 6453 #define rx_x4_status2_r_type_R_TYPE_T 2 6454 #define rx_x4_status2_r_type_R_TYPE_D 1 6455 #define rx_x4_status2_r_type_R_TYPE_E 0 6456 6457 /**************************************************************************** 6458 * Enums: rx_x4_status2_am_lock_state 6459 */ 6460 #define rx_x4_status2_am_lock_state_INVALID_AM 512 6461 #define rx_x4_status2_am_lock_state_GOOD_AM 256 6462 #define rx_x4_status2_am_lock_state_COMP_AM 128 6463 #define rx_x4_status2_am_lock_state_TIMER_2 64 6464 #define rx_x4_status2_am_lock_state_AM_2_GOOD 32 6465 #define rx_x4_status2_am_lock_state_COMP_2ND 16 6466 #define rx_x4_status2_am_lock_state_TIMER_1 8 6467 #define rx_x4_status2_am_lock_state_FIND_1ST 4 6468 #define rx_x4_status2_am_lock_state_AM_RESET_CNT 2 6469 #define rx_x4_status2_am_lock_state_AM_LOCK_INIT 1 6470 6471 /**************************************************************************** 6472 * Enums: rx_x4_status2_msg_selector 6473 */ 6474 #define rx_x4_status2_msg_selector_RESERVED 0 6475 #define rx_x4_status2_msg_selector_VALUE_802p3 1 6476 #define rx_x4_status2_msg_selector_VALUE_802p9 2 6477 #define rx_x4_status2_msg_selector_VALUE_802p5 3 6478 #define rx_x4_status2_msg_selector_VALUE_1394 4 6479 6480 /**************************************************************************** 6481 * Enums: rx_x4_status2_synce_enum 6482 */ 6483 #define rx_x4_status2_synce_enum_SYNCE_NO_DIV 0 6484 #define rx_x4_status2_synce_enum_SYNCE_DIV_7 1 6485 #define rx_x4_status2_synce_enum_SYNCE_DIV_11 2 6486 6487 /**************************************************************************** 6488 * Enums: rx_x4_status2_synce_enum_stage0 6489 */ 6490 #define rx_x4_status2_synce_enum_stage0_SYNCE_NO_DIV 0 6491 #define rx_x4_status2_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 6492 #define rx_x4_status2_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 6493 6494 /**************************************************************************** 6495 * Enums: rx_x4_status2_cl91_sync_state 6496 */ 6497 #define rx_x4_status2_cl91_sync_state_FIND_1ST 0 6498 #define rx_x4_status2_cl91_sync_state_COUNT_NEXT 1 6499 #define rx_x4_status2_cl91_sync_state_COMP_2ND 2 6500 #define rx_x4_status2_cl91_sync_state_TWO_GOOD 3 6501 6502 /**************************************************************************** 6503 * Enums: rx_x4_status2_cl91_algn_state 6504 */ 6505 #define rx_x4_status2_cl91_algn_state_LOSS_OF_ALIGNMENT 0 6506 #define rx_x4_status2_cl91_algn_state_DESKEW 1 6507 #define rx_x4_status2_cl91_algn_state_DESKEW_FAIL 2 6508 #define rx_x4_status2_cl91_algn_state_ALIGN_ACQUIRED 3 6509 #define rx_x4_status2_cl91_algn_state_CW_GOOD 4 6510 #define rx_x4_status2_cl91_algn_state_CW_BAD 5 6511 #define rx_x4_status2_cl91_algn_state_THREE_BAD 6 6512 6513 /**************************************************************************** 6514 * Enums: rx_x4_status2_fec_sel 6515 */ 6516 #define rx_x4_status2_fec_sel_NO_FEC 0 6517 #define rx_x4_status2_fec_sel_FEC_CL74 1 6518 #define rx_x4_status2_fec_sel_FEC_CL91 2 6519 6520 /**************************************************************************** 6521 * Enums: rx_x4_status3_cl36TxEEEStates_l 6522 */ 6523 #define rx_x4_status3_cl36TxEEEStates_l_TX_REFRESH 8 6524 #define rx_x4_status3_cl36TxEEEStates_l_TX_QUIET 4 6525 #define rx_x4_status3_cl36TxEEEStates_l_TX_SLEEP 2 6526 #define rx_x4_status3_cl36TxEEEStates_l_TX_ACTIVE 1 6527 6528 /**************************************************************************** 6529 * Enums: rx_x4_status3_cl36TxEEEStates_c 6530 */ 6531 #define rx_x4_status3_cl36TxEEEStates_c_TX_REFRESH 3 6532 #define rx_x4_status3_cl36TxEEEStates_c_TX_QUIET 2 6533 #define rx_x4_status3_cl36TxEEEStates_c_TX_SLEEP 1 6534 #define rx_x4_status3_cl36TxEEEStates_c_TX_ACTIVE 0 6535 6536 /**************************************************************************** 6537 * Enums: rx_x4_status3_cl49TxEEEStates_l 6538 */ 6539 #define rx_x4_status3_cl49TxEEEStates_l_SCR_RESET_2 64 6540 #define rx_x4_status3_cl49TxEEEStates_l_SCR_RESET_1 32 6541 #define rx_x4_status3_cl49TxEEEStates_l_TX_WAKE 16 6542 #define rx_x4_status3_cl49TxEEEStates_l_TX_REFRESH 8 6543 #define rx_x4_status3_cl49TxEEEStates_l_TX_QUIET 4 6544 #define rx_x4_status3_cl49TxEEEStates_l_TX_SLEEP 2 6545 #define rx_x4_status3_cl49TxEEEStates_l_TX_ACTIVE 1 6546 6547 /**************************************************************************** 6548 * Enums: rx_x4_status3_fec_req_enum 6549 */ 6550 #define rx_x4_status3_fec_req_enum_FEC_not_supported 0 6551 #define rx_x4_status3_fec_req_enum_FEC_supported_but_not_requested 1 6552 #define rx_x4_status3_fec_req_enum_invalid_setting 2 6553 #define rx_x4_status3_fec_req_enum_FEC_supported_and_requested 3 6554 6555 /**************************************************************************** 6556 * Enums: rx_x4_status3_cl73_pause_enum 6557 */ 6558 #define rx_x4_status3_cl73_pause_enum_No_PAUSE_ability 0 6559 #define rx_x4_status3_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 6560 #define rx_x4_status3_cl73_pause_enum_Symmetric_PAUSE_ability 1 6561 #define rx_x4_status3_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 6562 6563 /**************************************************************************** 6564 * Enums: rx_x4_status3_cl49TxEEEStates_c 6565 */ 6566 #define rx_x4_status3_cl49TxEEEStates_c_SCR_RESET_2 6 6567 #define rx_x4_status3_cl49TxEEEStates_c_SCR_RESET_1 5 6568 #define rx_x4_status3_cl49TxEEEStates_c_TX_WAKE 4 6569 #define rx_x4_status3_cl49TxEEEStates_c_TX_REFRESH 3 6570 #define rx_x4_status3_cl49TxEEEStates_c_TX_QUIET 2 6571 #define rx_x4_status3_cl49TxEEEStates_c_TX_SLEEP 1 6572 #define rx_x4_status3_cl49TxEEEStates_c_TX_ACTIVE 0 6573 6574 /**************************************************************************** 6575 * Enums: rx_x4_status3_cl36RxEEEStates_l 6576 */ 6577 #define rx_x4_status3_cl36RxEEEStates_l_RX_LINK_FAIL 32 6578 #define rx_x4_status3_cl36RxEEEStates_l_RX_WTF 16 6579 #define rx_x4_status3_cl36RxEEEStates_l_RX_WAKE 8 6580 #define rx_x4_status3_cl36RxEEEStates_l_RX_QUIET 4 6581 #define rx_x4_status3_cl36RxEEEStates_l_RX_SLEEP 2 6582 #define rx_x4_status3_cl36RxEEEStates_l_RX_ACTIVE 1 6583 6584 /**************************************************************************** 6585 * Enums: rx_x4_status3_cl36RxEEEStates_c 6586 */ 6587 #define rx_x4_status3_cl36RxEEEStates_c_RX_LINK_FAIL 5 6588 #define rx_x4_status3_cl36RxEEEStates_c_RX_WTF 4 6589 #define rx_x4_status3_cl36RxEEEStates_c_RX_WAKE 3 6590 #define rx_x4_status3_cl36RxEEEStates_c_RX_QUIET 2 6591 #define rx_x4_status3_cl36RxEEEStates_c_RX_SLEEP 1 6592 #define rx_x4_status3_cl36RxEEEStates_c_RX_ACTIVE 0 6593 6594 /**************************************************************************** 6595 * Enums: rx_x4_status3_cl49RxEEEStates_l 6596 */ 6597 #define rx_x4_status3_cl49RxEEEStates_l_RX_LINK_FAIL 32 6598 #define rx_x4_status3_cl49RxEEEStates_l_RX_WTF 16 6599 #define rx_x4_status3_cl49RxEEEStates_l_RX_WAKE 8 6600 #define rx_x4_status3_cl49RxEEEStates_l_RX_QUIET 4 6601 #define rx_x4_status3_cl49RxEEEStates_l_RX_SLEEP 2 6602 #define rx_x4_status3_cl49RxEEEStates_l_RX_ACTIVE 1 6603 6604 /**************************************************************************** 6605 * Enums: rx_x4_status3_cl49RxEEEStates_c 6606 */ 6607 #define rx_x4_status3_cl49RxEEEStates_c_RX_LINK_FAIL 5 6608 #define rx_x4_status3_cl49RxEEEStates_c_RX_WTF 4 6609 #define rx_x4_status3_cl49RxEEEStates_c_RX_WAKE 3 6610 #define rx_x4_status3_cl49RxEEEStates_c_RX_QUIET 2 6611 #define rx_x4_status3_cl49RxEEEStates_c_RX_SLEEP 1 6612 #define rx_x4_status3_cl49RxEEEStates_c_RX_ACTIVE 0 6613 6614 /**************************************************************************** 6615 * Enums: rx_x4_status3_cl48TxEEEStates_l 6616 */ 6617 #define rx_x4_status3_cl48TxEEEStates_l_TX_REFRESH 8 6618 #define rx_x4_status3_cl48TxEEEStates_l_TX_QUIET 4 6619 #define rx_x4_status3_cl48TxEEEStates_l_TX_SLEEP 2 6620 #define rx_x4_status3_cl48TxEEEStates_l_TX_ACTIVE 1 6621 6622 /**************************************************************************** 6623 * Enums: rx_x4_status3_cl48TxEEEStates_c 6624 */ 6625 #define rx_x4_status3_cl48TxEEEStates_c_TX_REFRESH 3 6626 #define rx_x4_status3_cl48TxEEEStates_c_TX_QUIET 2 6627 #define rx_x4_status3_cl48TxEEEStates_c_TX_SLEEP 1 6628 #define rx_x4_status3_cl48TxEEEStates_c_TX_ACTIVE 0 6629 6630 /**************************************************************************** 6631 * Enums: rx_x4_status3_cl48RxEEEStates_l 6632 */ 6633 #define rx_x4_status3_cl48RxEEEStates_l_RX_LINK_FAIL 32 6634 #define rx_x4_status3_cl48RxEEEStates_l_RX_WAKE 16 6635 #define rx_x4_status3_cl48RxEEEStates_l_RX_QUIET 8 6636 #define rx_x4_status3_cl48RxEEEStates_l_RX_DEACT 4 6637 #define rx_x4_status3_cl48RxEEEStates_l_RX_SLEEP 2 6638 #define rx_x4_status3_cl48RxEEEStates_l_RX_ACTIVE 1 6639 6640 /**************************************************************************** 6641 * Enums: rx_x4_status3_cl48RxEEEStates_c 6642 */ 6643 #define rx_x4_status3_cl48RxEEEStates_c_RX_LINK_FAIL 5 6644 #define rx_x4_status3_cl48RxEEEStates_c_RX_WAKE 4 6645 #define rx_x4_status3_cl48RxEEEStates_c_RX_QUIET 3 6646 #define rx_x4_status3_cl48RxEEEStates_c_RX_DEACT 2 6647 #define rx_x4_status3_cl48RxEEEStates_c_RX_SLEEP 1 6648 #define rx_x4_status3_cl48RxEEEStates_c_RX_ACTIVE 0 6649 6650 /**************************************************************************** 6651 * Enums: rx_x4_status3_IQP_Options 6652 */ 6653 #define rx_x4_status3_IQP_Options_i50uA 0 6654 #define rx_x4_status3_IQP_Options_i100uA 1 6655 #define rx_x4_status3_IQP_Options_i150uA 2 6656 #define rx_x4_status3_IQP_Options_i200uA 3 6657 #define rx_x4_status3_IQP_Options_i250uA 4 6658 #define rx_x4_status3_IQP_Options_i300uA 5 6659 #define rx_x4_status3_IQP_Options_i350uA 6 6660 #define rx_x4_status3_IQP_Options_i400uA 7 6661 #define rx_x4_status3_IQP_Options_i450uA 8 6662 #define rx_x4_status3_IQP_Options_i500uA 9 6663 #define rx_x4_status3_IQP_Options_i550uA 10 6664 #define rx_x4_status3_IQP_Options_i600uA 11 6665 #define rx_x4_status3_IQP_Options_i650uA 12 6666 #define rx_x4_status3_IQP_Options_i700uA 13 6667 #define rx_x4_status3_IQP_Options_i750uA 14 6668 #define rx_x4_status3_IQP_Options_i800uA 15 6669 6670 /**************************************************************************** 6671 * Enums: rx_x4_status3_IDriver_Options 6672 */ 6673 #define rx_x4_status3_IDriver_Options_v680mV 0 6674 #define rx_x4_status3_IDriver_Options_v730mV 1 6675 #define rx_x4_status3_IDriver_Options_v780mV 2 6676 #define rx_x4_status3_IDriver_Options_v830mV 3 6677 #define rx_x4_status3_IDriver_Options_v880mV 4 6678 #define rx_x4_status3_IDriver_Options_v930mV 5 6679 #define rx_x4_status3_IDriver_Options_v980mV 6 6680 #define rx_x4_status3_IDriver_Options_v1010mV 7 6681 #define rx_x4_status3_IDriver_Options_v1040mV 8 6682 #define rx_x4_status3_IDriver_Options_v1060mV 9 6683 #define rx_x4_status3_IDriver_Options_v1070mV 10 6684 #define rx_x4_status3_IDriver_Options_v1080mV 11 6685 #define rx_x4_status3_IDriver_Options_v1085mV 12 6686 #define rx_x4_status3_IDriver_Options_v1090mV 13 6687 #define rx_x4_status3_IDriver_Options_v1095mV 14 6688 #define rx_x4_status3_IDriver_Options_v1100mV 15 6689 6690 /**************************************************************************** 6691 * Enums: rx_x4_status3_operationModes 6692 */ 6693 #define rx_x4_status3_operationModes_XGXS 0 6694 #define rx_x4_status3_operationModes_XGXG_nCC 1 6695 #define rx_x4_status3_operationModes_Indlane_OS8 4 6696 #define rx_x4_status3_operationModes_IndLane_OS5 5 6697 #define rx_x4_status3_operationModes_PCI 7 6698 #define rx_x4_status3_operationModes_XGXS_nLQ 8 6699 #define rx_x4_status3_operationModes_XGXS_nLQnCC 9 6700 #define rx_x4_status3_operationModes_PBypass 10 6701 #define rx_x4_status3_operationModes_PBypass_nDSK 11 6702 #define rx_x4_status3_operationModes_ComboCoreMode 12 6703 #define rx_x4_status3_operationModes_Clocks_off 15 6704 6705 /**************************************************************************** 6706 * Enums: rx_x4_status3_actualSpeeds 6707 */ 6708 #define rx_x4_status3_actualSpeeds_dr_10M 0 6709 #define rx_x4_status3_actualSpeeds_dr_100M 1 6710 #define rx_x4_status3_actualSpeeds_dr_1G 2 6711 #define rx_x4_status3_actualSpeeds_dr_2p5G 3 6712 #define rx_x4_status3_actualSpeeds_dr_5G_X4 4 6713 #define rx_x4_status3_actualSpeeds_dr_6G_X4 5 6714 #define rx_x4_status3_actualSpeeds_dr_10G_HiG 6 6715 #define rx_x4_status3_actualSpeeds_dr_10G_CX4 7 6716 #define rx_x4_status3_actualSpeeds_dr_12G_HiG 8 6717 #define rx_x4_status3_actualSpeeds_dr_12p5G_X4 9 6718 #define rx_x4_status3_actualSpeeds_dr_13G_X4 10 6719 #define rx_x4_status3_actualSpeeds_dr_15G_X4 11 6720 #define rx_x4_status3_actualSpeeds_dr_16G_X4 12 6721 #define rx_x4_status3_actualSpeeds_dr_1G_KX 13 6722 #define rx_x4_status3_actualSpeeds_dr_10G_KX4 14 6723 #define rx_x4_status3_actualSpeeds_dr_10G_KR 15 6724 #define rx_x4_status3_actualSpeeds_dr_5G 16 6725 #define rx_x4_status3_actualSpeeds_dr_6p4G 17 6726 #define rx_x4_status3_actualSpeeds_dr_20G_X4 18 6727 #define rx_x4_status3_actualSpeeds_dr_21G_X4 19 6728 #define rx_x4_status3_actualSpeeds_dr_25G_X4 20 6729 #define rx_x4_status3_actualSpeeds_dr_10G_HiG_DXGXS 21 6730 #define rx_x4_status3_actualSpeeds_dr_10G_DXGXS 22 6731 #define rx_x4_status3_actualSpeeds_dr_10p5G_HiG_DXGXS 23 6732 #define rx_x4_status3_actualSpeeds_dr_10p5G_DXGXS 24 6733 #define rx_x4_status3_actualSpeeds_dr_12p773G_HiG_DXGXS 25 6734 #define rx_x4_status3_actualSpeeds_dr_12p773G_DXGXS 26 6735 #define rx_x4_status3_actualSpeeds_dr_10G_XFI 27 6736 #define rx_x4_status3_actualSpeeds_dr_40G 28 6737 #define rx_x4_status3_actualSpeeds_dr_20G_HiG_DXGXS 29 6738 #define rx_x4_status3_actualSpeeds_dr_20G_DXGXS 30 6739 #define rx_x4_status3_actualSpeeds_dr_10G_SFI 31 6740 #define rx_x4_status3_actualSpeeds_dr_31p5G 32 6741 #define rx_x4_status3_actualSpeeds_dr_32p7G 33 6742 #define rx_x4_status3_actualSpeeds_dr_20G_SCR 34 6743 #define rx_x4_status3_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 6744 #define rx_x4_status3_actualSpeeds_dr_10G_DXGXS_SCR 36 6745 #define rx_x4_status3_actualSpeeds_dr_12G_R2 37 6746 #define rx_x4_status3_actualSpeeds_dr_10G_X2 38 6747 #define rx_x4_status3_actualSpeeds_dr_40G_KR4 39 6748 #define rx_x4_status3_actualSpeeds_dr_40G_CR4 40 6749 #define rx_x4_status3_actualSpeeds_dr_100G_CR10 41 6750 #define rx_x4_status3_actualSpeeds_dr_15p75G_DXGXS 44 6751 #define rx_x4_status3_actualSpeeds_dr_20G_KR2 57 6752 #define rx_x4_status3_actualSpeeds_dr_20G_CR2 58 6753 6754 /**************************************************************************** 6755 * Enums: rx_x4_status3_actualSpeedsMisc1 6756 */ 6757 #define rx_x4_status3_actualSpeedsMisc1_dr_2500BRCM_X1 16 6758 #define rx_x4_status3_actualSpeedsMisc1_dr_5000BRCM_X4 17 6759 #define rx_x4_status3_actualSpeedsMisc1_dr_6000BRCM_X4 18 6760 #define rx_x4_status3_actualSpeedsMisc1_dr_10GHiGig_X4 19 6761 #define rx_x4_status3_actualSpeedsMisc1_dr_10GBASE_CX4 20 6762 #define rx_x4_status3_actualSpeedsMisc1_dr_12GHiGig_X4 21 6763 #define rx_x4_status3_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 6764 #define rx_x4_status3_actualSpeedsMisc1_dr_13GHiGig_X4 23 6765 #define rx_x4_status3_actualSpeedsMisc1_dr_15GHiGig_X4 24 6766 #define rx_x4_status3_actualSpeedsMisc1_dr_16GHiGig_X4 25 6767 #define rx_x4_status3_actualSpeedsMisc1_dr_5000BRCM_X1 26 6768 #define rx_x4_status3_actualSpeedsMisc1_dr_6363BRCM_X1 27 6769 #define rx_x4_status3_actualSpeedsMisc1_dr_20GHiGig_X4 28 6770 #define rx_x4_status3_actualSpeedsMisc1_dr_21GHiGig_X4 29 6771 #define rx_x4_status3_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 6772 #define rx_x4_status3_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 6773 6774 /**************************************************************************** 6775 * Enums: rx_x4_status3_IndLaneModes 6776 */ 6777 #define rx_x4_status3_IndLaneModes_SWSDR_div2 0 6778 #define rx_x4_status3_IndLaneModes_SWSDR_div1 1 6779 #define rx_x4_status3_IndLaneModes_DWSDR_div2 2 6780 #define rx_x4_status3_IndLaneModes_DWSDR_div1 3 6781 6782 /**************************************************************************** 6783 * Enums: rx_x4_status3_prbsSelect 6784 */ 6785 #define rx_x4_status3_prbsSelect_prbs7 0 6786 #define rx_x4_status3_prbsSelect_prbs15 1 6787 #define rx_x4_status3_prbsSelect_prbs23 2 6788 #define rx_x4_status3_prbsSelect_prbs31 3 6789 6790 /**************************************************************************** 6791 * Enums: rx_x4_status3_vcoDivider 6792 */ 6793 #define rx_x4_status3_vcoDivider_div32 0 6794 #define rx_x4_status3_vcoDivider_div36 1 6795 #define rx_x4_status3_vcoDivider_div40 2 6796 #define rx_x4_status3_vcoDivider_div42 3 6797 #define rx_x4_status3_vcoDivider_div48 4 6798 #define rx_x4_status3_vcoDivider_div50 5 6799 #define rx_x4_status3_vcoDivider_div52 6 6800 #define rx_x4_status3_vcoDivider_div54 7 6801 #define rx_x4_status3_vcoDivider_div60 8 6802 #define rx_x4_status3_vcoDivider_div64 9 6803 #define rx_x4_status3_vcoDivider_div66 10 6804 #define rx_x4_status3_vcoDivider_div68 11 6805 #define rx_x4_status3_vcoDivider_div70 12 6806 #define rx_x4_status3_vcoDivider_div80 13 6807 #define rx_x4_status3_vcoDivider_div92 14 6808 #define rx_x4_status3_vcoDivider_div100 15 6809 6810 /**************************************************************************** 6811 * Enums: rx_x4_status3_refClkSelect 6812 */ 6813 #define rx_x4_status3_refClkSelect_clk_25MHz 0 6814 #define rx_x4_status3_refClkSelect_clk_100MHz 1 6815 #define rx_x4_status3_refClkSelect_clk_125MHz 2 6816 #define rx_x4_status3_refClkSelect_clk_156p25MHz 3 6817 #define rx_x4_status3_refClkSelect_clk_187p5MHz 4 6818 #define rx_x4_status3_refClkSelect_clk_161p25Mhz 5 6819 #define rx_x4_status3_refClkSelect_clk_50Mhz 6 6820 #define rx_x4_status3_refClkSelect_clk_106p25Mhz 7 6821 6822 /**************************************************************************** 6823 * Enums: rx_x4_status3_aerMMDdevTypeSelect 6824 */ 6825 #define rx_x4_status3_aerMMDdevTypeSelect_combo_core 0 6826 #define rx_x4_status3_aerMMDdevTypeSelect_PMA_PMD 1 6827 #define rx_x4_status3_aerMMDdevTypeSelect_PCS 3 6828 #define rx_x4_status3_aerMMDdevTypeSelect_PHY 4 6829 #define rx_x4_status3_aerMMDdevTypeSelect_DTE 5 6830 #define rx_x4_status3_aerMMDdevTypeSelect_CL73_AN 7 6831 6832 /**************************************************************************** 6833 * Enums: rx_x4_status3_aerMMDportSelect 6834 */ 6835 #define rx_x4_status3_aerMMDportSelect_ln0 0 6836 #define rx_x4_status3_aerMMDportSelect_ln1 1 6837 #define rx_x4_status3_aerMMDportSelect_ln2 2 6838 #define rx_x4_status3_aerMMDportSelect_ln3 3 6839 #define rx_x4_status3_aerMMDportSelect_BCST_ln0_1_2_3 511 6840 #define rx_x4_status3_aerMMDportSelect_BCST_ln0_1 512 6841 #define rx_x4_status3_aerMMDportSelect_BCST_ln2_3 513 6842 6843 /**************************************************************************** 6844 * Enums: rx_x4_status3_firmwareModeSelect 6845 */ 6846 #define rx_x4_status3_firmwareModeSelect_DEFAULT 0 6847 #define rx_x4_status3_firmwareModeSelect_SFP_OPT_LR 1 6848 #define rx_x4_status3_firmwareModeSelect_SFP_DAC 2 6849 #define rx_x4_status3_firmwareModeSelect_XLAUI 3 6850 #define rx_x4_status3_firmwareModeSelect_LONG_CH_6G 4 6851 6852 /**************************************************************************** 6853 * Enums: rx_x4_status3_tempIdxSelect 6854 */ 6855 #define rx_x4_status3_tempIdxSelect_LTE__22p9C 15 6856 #define rx_x4_status3_tempIdxSelect_LTE__12p6C 14 6857 #define rx_x4_status3_tempIdxSelect_LTE__3p0C 13 6858 #define rx_x4_status3_tempIdxSelect_LTE_6p7C 12 6859 #define rx_x4_status3_tempIdxSelect_LTE_16p4C 11 6860 #define rx_x4_status3_tempIdxSelect_LTE_26p6C 10 6861 #define rx_x4_status3_tempIdxSelect_LTE_36p3C 9 6862 #define rx_x4_status3_tempIdxSelect_LTE_46p0C 8 6863 #define rx_x4_status3_tempIdxSelect_LTE_56p2C 7 6864 #define rx_x4_status3_tempIdxSelect_LTE_65p9C 6 6865 #define rx_x4_status3_tempIdxSelect_LTE_75p6C 5 6866 #define rx_x4_status3_tempIdxSelect_LTE_85p3C 4 6867 #define rx_x4_status3_tempIdxSelect_LTE_95p5C 3 6868 #define rx_x4_status3_tempIdxSelect_LTE_105p2C 2 6869 #define rx_x4_status3_tempIdxSelect_LTE_114p9C 1 6870 #define rx_x4_status3_tempIdxSelect_LTE_125p1C 0 6871 6872 /**************************************************************************** 6873 * Enums: rx_x4_status3_port_mode 6874 */ 6875 #define rx_x4_status3_port_mode_QUAD_PORT 0 6876 #define rx_x4_status3_port_mode_TRI_1_PORT 1 6877 #define rx_x4_status3_port_mode_TRI_2_PORT 2 6878 #define rx_x4_status3_port_mode_DUAL_PORT 3 6879 #define rx_x4_status3_port_mode_SINGLE_PORT 4 6880 6881 /**************************************************************************** 6882 * Enums: rx_x4_status3_rev_letter_enum 6883 */ 6884 #define rx_x4_status3_rev_letter_enum_REV_A 0 6885 #define rx_x4_status3_rev_letter_enum_REV_B 1 6886 #define rx_x4_status3_rev_letter_enum_REV_C 2 6887 #define rx_x4_status3_rev_letter_enum_REV_D 3 6888 6889 /**************************************************************************** 6890 * Enums: rx_x4_status3_rev_number_enum 6891 */ 6892 #define rx_x4_status3_rev_number_enum_REV_0 0 6893 #define rx_x4_status3_rev_number_enum_REV_1 1 6894 #define rx_x4_status3_rev_number_enum_REV_2 2 6895 #define rx_x4_status3_rev_number_enum_REV_3 3 6896 #define rx_x4_status3_rev_number_enum_REV_4 4 6897 #define rx_x4_status3_rev_number_enum_REV_5 5 6898 #define rx_x4_status3_rev_number_enum_REV_6 6 6899 #define rx_x4_status3_rev_number_enum_REV_7 7 6900 6901 /**************************************************************************** 6902 * Enums: rx_x4_status3_bonding_enum 6903 */ 6904 #define rx_x4_status3_bonding_enum_WIRE_BOND 0 6905 #define rx_x4_status3_bonding_enum_FLIP_CHIP 1 6906 6907 /**************************************************************************** 6908 * Enums: rx_x4_status3_tech_process 6909 */ 6910 #define rx_x4_status3_tech_process_PROCESS_90NM 0 6911 #define rx_x4_status3_tech_process_PROCESS_65NM 1 6912 #define rx_x4_status3_tech_process_PROCESS_40NM 2 6913 #define rx_x4_status3_tech_process_PROCESS_28NM 3 6914 6915 /**************************************************************************** 6916 * Enums: rx_x4_status3_model_num 6917 */ 6918 #define rx_x4_status3_model_num_SERDES_CL73 0 6919 #define rx_x4_status3_model_num_XGXS_16G 1 6920 #define rx_x4_status3_model_num_HYPERCORE 2 6921 #define rx_x4_status3_model_num_HYPERLITE 3 6922 #define rx_x4_status3_model_num_PCIE_G2_PIPE 4 6923 #define rx_x4_status3_model_num_SERDES_1p25GBd 5 6924 #define rx_x4_status3_model_num_SATA2 6 6925 #define rx_x4_status3_model_num_QSGMII 7 6926 #define rx_x4_status3_model_num_XGXS10G 8 6927 #define rx_x4_status3_model_num_WARPCORE 9 6928 #define rx_x4_status3_model_num_XFICORE 10 6929 #define rx_x4_status3_model_num_RXFI 11 6930 #define rx_x4_status3_model_num_WARPLITE 12 6931 #define rx_x4_status3_model_num_PENTACORE 13 6932 #define rx_x4_status3_model_num_ESM 14 6933 #define rx_x4_status3_model_num_QUAD_SGMII 15 6934 #define rx_x4_status3_model_num_WARPCORE_3 16 6935 #define rx_x4_status3_model_num_TSC 17 6936 #define rx_x4_status3_model_num_TSC4E 18 6937 #define rx_x4_status3_model_num_TSC12E 19 6938 #define rx_x4_status3_model_num_TSC4F 20 6939 #define rx_x4_status3_model_num_XGXS_CL73_90NM 29 6940 #define rx_x4_status3_model_num_SERDES_CL73_90NM 30 6941 #define rx_x4_status3_model_num_WARPCORE3 32 6942 #define rx_x4_status3_model_num_WARPCORE4_TSC 33 6943 #define rx_x4_status3_model_num_RXAUI 34 6944 6945 /**************************************************************************** 6946 * Enums: rx_x4_status3_payload 6947 */ 6948 #define rx_x4_status3_payload_REPEAT_2_BYTES 0 6949 #define rx_x4_status3_payload_RAMPING 1 6950 #define rx_x4_status3_payload_CL48_CRPAT 2 6951 #define rx_x4_status3_payload_CL48_CJPAT 3 6952 #define rx_x4_status3_payload_CL36_LONG_CRPAT 4 6953 #define rx_x4_status3_payload_CL36_SHORT_CRPAT 5 6954 6955 /**************************************************************************** 6956 * Enums: rx_x4_status3_sc 6957 */ 6958 #define rx_x4_status3_sc_S_10G_CR1 0 6959 #define rx_x4_status3_sc_S_10G_KR1 1 6960 #define rx_x4_status3_sc_S_10G_X1 2 6961 #define rx_x4_status3_sc_S_10G_HG2_CR1 4 6962 #define rx_x4_status3_sc_S_10G_HG2_KR1 5 6963 #define rx_x4_status3_sc_S_10G_HG2_X1 6 6964 #define rx_x4_status3_sc_S_20G_CR1 8 6965 #define rx_x4_status3_sc_S_20G_KR1 9 6966 #define rx_x4_status3_sc_S_20G_X1 10 6967 #define rx_x4_status3_sc_S_20G_HG2_CR1 12 6968 #define rx_x4_status3_sc_S_20G_HG2_KR1 13 6969 #define rx_x4_status3_sc_S_20G_HG2_X1 14 6970 #define rx_x4_status3_sc_S_25G_CR1 16 6971 #define rx_x4_status3_sc_S_25G_KR1 17 6972 #define rx_x4_status3_sc_S_25G_X1 18 6973 #define rx_x4_status3_sc_S_25G_HG2_CR1 20 6974 #define rx_x4_status3_sc_S_25G_HG2_KR1 21 6975 #define rx_x4_status3_sc_S_25G_HG2_X1 22 6976 #define rx_x4_status3_sc_S_20G_CR2 24 6977 #define rx_x4_status3_sc_S_20G_KR2 25 6978 #define rx_x4_status3_sc_S_20G_X2 26 6979 #define rx_x4_status3_sc_S_20G_HG2_CR2 28 6980 #define rx_x4_status3_sc_S_20G_HG2_KR2 29 6981 #define rx_x4_status3_sc_S_20G_HG2_X2 30 6982 #define rx_x4_status3_sc_S_40G_CR2 32 6983 #define rx_x4_status3_sc_S_40G_KR2 33 6984 #define rx_x4_status3_sc_S_40G_X2 34 6985 #define rx_x4_status3_sc_S_40G_HG2_CR2 36 6986 #define rx_x4_status3_sc_S_40G_HG2_KR2 37 6987 #define rx_x4_status3_sc_S_40G_HG2_X2 38 6988 #define rx_x4_status3_sc_S_40G_CR4 40 6989 #define rx_x4_status3_sc_S_40G_KR4 41 6990 #define rx_x4_status3_sc_S_40G_X4 42 6991 #define rx_x4_status3_sc_S_40G_HG2_CR4 44 6992 #define rx_x4_status3_sc_S_40G_HG2_KR4 45 6993 #define rx_x4_status3_sc_S_40G_HG2_X4 46 6994 #define rx_x4_status3_sc_S_50G_CR2 48 6995 #define rx_x4_status3_sc_S_50G_KR2 49 6996 #define rx_x4_status3_sc_S_50G_X2 50 6997 #define rx_x4_status3_sc_S_50G_HG2_CR2 52 6998 #define rx_x4_status3_sc_S_50G_HG2_KR2 53 6999 #define rx_x4_status3_sc_S_50G_HG2_X2 54 7000 #define rx_x4_status3_sc_S_50G_CR4 56 7001 #define rx_x4_status3_sc_S_50G_KR4 57 7002 #define rx_x4_status3_sc_S_50G_X4 58 7003 #define rx_x4_status3_sc_S_50G_HG2_CR4 60 7004 #define rx_x4_status3_sc_S_50G_HG2_KR4 61 7005 #define rx_x4_status3_sc_S_50G_HG2_X4 62 7006 #define rx_x4_status3_sc_S_100G_CR4 64 7007 #define rx_x4_status3_sc_S_100G_KR4 65 7008 #define rx_x4_status3_sc_S_100G_X4 66 7009 #define rx_x4_status3_sc_S_100G_HG2_CR4 68 7010 #define rx_x4_status3_sc_S_100G_HG2_KR4 69 7011 #define rx_x4_status3_sc_S_100G_HG2_X4 70 7012 #define rx_x4_status3_sc_S_CL73_20GVCO 72 7013 #define rx_x4_status3_sc_S_CL73_25GVCO 80 7014 #define rx_x4_status3_sc_S_CL36_20GVCO 88 7015 #define rx_x4_status3_sc_S_CL36_25GVCO 96 7016 7017 /**************************************************************************** 7018 * Enums: rx_x4_status3_t_fifo_modes 7019 */ 7020 #define rx_x4_status3_t_fifo_modes_T_FIFO_MODE_BYPASS 0 7021 #define rx_x4_status3_t_fifo_modes_T_FIFO_MODE_40G 1 7022 #define rx_x4_status3_t_fifo_modes_T_FIFO_MODE_100G 2 7023 #define rx_x4_status3_t_fifo_modes_T_FIFO_MODE_20G 3 7024 7025 /**************************************************************************** 7026 * Enums: rx_x4_status3_t_enc_modes 7027 */ 7028 #define rx_x4_status3_t_enc_modes_T_ENC_MODE_BYPASS 0 7029 #define rx_x4_status3_t_enc_modes_T_ENC_MODE_CL49 1 7030 #define rx_x4_status3_t_enc_modes_T_ENC_MODE_CL82 2 7031 7032 /**************************************************************************** 7033 * Enums: rx_x4_status3_btmx_mode 7034 */ 7035 #define rx_x4_status3_btmx_mode_BS_BTMX_MODE_1to1 0 7036 #define rx_x4_status3_btmx_mode_BS_BTMX_MODE_2to1 1 7037 #define rx_x4_status3_btmx_mode_BS_BTMX_MODE_5to1 2 7038 7039 /**************************************************************************** 7040 * Enums: rx_x4_status3_t_type_cl82 7041 */ 7042 #define rx_x4_status3_t_type_cl82_T_TYPE_B1 5 7043 #define rx_x4_status3_t_type_cl82_T_TYPE_C 4 7044 #define rx_x4_status3_t_type_cl82_T_TYPE_S 3 7045 #define rx_x4_status3_t_type_cl82_T_TYPE_T 2 7046 #define rx_x4_status3_t_type_cl82_T_TYPE_D 1 7047 #define rx_x4_status3_t_type_cl82_T_TYPE_E 0 7048 7049 /**************************************************************************** 7050 * Enums: rx_x4_status3_txsm_state_cl82 7051 */ 7052 #define rx_x4_status3_txsm_state_cl82_TX_HIG_END 6 7053 #define rx_x4_status3_txsm_state_cl82_TX_HIG_START 5 7054 #define rx_x4_status3_txsm_state_cl82_TX_E 4 7055 #define rx_x4_status3_txsm_state_cl82_TX_T 3 7056 #define rx_x4_status3_txsm_state_cl82_TX_D 2 7057 #define rx_x4_status3_txsm_state_cl82_TX_C 1 7058 #define rx_x4_status3_txsm_state_cl82_TX_INIT 0 7059 7060 /**************************************************************************** 7061 * Enums: rx_x4_status3_ltxsm_state_cl82 7062 */ 7063 #define rx_x4_status3_ltxsm_state_cl82_TX_HIG_END 64 7064 #define rx_x4_status3_ltxsm_state_cl82_TX_HIG_START 32 7065 #define rx_x4_status3_ltxsm_state_cl82_TX_E 16 7066 #define rx_x4_status3_ltxsm_state_cl82_TX_T 8 7067 #define rx_x4_status3_ltxsm_state_cl82_TX_D 4 7068 #define rx_x4_status3_ltxsm_state_cl82_TX_C 2 7069 #define rx_x4_status3_ltxsm_state_cl82_TX_INIT 1 7070 7071 /**************************************************************************** 7072 * Enums: rx_x4_status3_r_type_coded_cl82 7073 */ 7074 #define rx_x4_status3_r_type_coded_cl82_R_TYPE_B1 32 7075 #define rx_x4_status3_r_type_coded_cl82_R_TYPE_C 16 7076 #define rx_x4_status3_r_type_coded_cl82_R_TYPE_S 8 7077 #define rx_x4_status3_r_type_coded_cl82_R_TYPE_T 4 7078 #define rx_x4_status3_r_type_coded_cl82_R_TYPE_D 2 7079 #define rx_x4_status3_r_type_coded_cl82_R_TYPE_E 1 7080 7081 /**************************************************************************** 7082 * Enums: rx_x4_status3_rxsm_state_cl82 7083 */ 7084 #define rx_x4_status3_rxsm_state_cl82_RX_HIG_END 64 7085 #define rx_x4_status3_rxsm_state_cl82_RX_HIG_START 32 7086 #define rx_x4_status3_rxsm_state_cl82_RX_E 16 7087 #define rx_x4_status3_rxsm_state_cl82_RX_T 8 7088 #define rx_x4_status3_rxsm_state_cl82_RX_D 4 7089 #define rx_x4_status3_rxsm_state_cl82_RX_C 2 7090 #define rx_x4_status3_rxsm_state_cl82_RX_INIT 1 7091 7092 /**************************************************************************** 7093 * Enums: rx_x4_status3_deskew_state 7094 */ 7095 #define rx_x4_status3_deskew_state_ALIGN_ACQUIRED 2 7096 #define rx_x4_status3_deskew_state_LOSS_OF_ALIGNMENT 1 7097 7098 /**************************************************************************** 7099 * Enums: rx_x4_status3_os_mode_enum 7100 */ 7101 #define rx_x4_status3_os_mode_enum_OS_MODE_1 0 7102 #define rx_x4_status3_os_mode_enum_OS_MODE_2 1 7103 #define rx_x4_status3_os_mode_enum_OS_MODE_4 2 7104 #define rx_x4_status3_os_mode_enum_OS_MODE_16p5 8 7105 #define rx_x4_status3_os_mode_enum_OS_MODE_20p625 12 7106 7107 /**************************************************************************** 7108 * Enums: rx_x4_status3_scr_modes 7109 */ 7110 #define rx_x4_status3_scr_modes_T_SCR_MODE_BYPASS 0 7111 #define rx_x4_status3_scr_modes_T_SCR_MODE_CL49 1 7112 #define rx_x4_status3_scr_modes_T_SCR_MODE_40G_2_LANE 2 7113 #define rx_x4_status3_scr_modes_T_SCR_MODE_100G 3 7114 #define rx_x4_status3_scr_modes_T_SCR_MODE_20G 4 7115 #define rx_x4_status3_scr_modes_T_SCR_MODE_40G_4_LANE 5 7116 7117 /**************************************************************************** 7118 * Enums: rx_x4_status3_descr_modes 7119 */ 7120 #define rx_x4_status3_descr_modes_R_DESCR_MODE_BYPASS 0 7121 #define rx_x4_status3_descr_modes_R_DESCR_MODE_CL49 1 7122 #define rx_x4_status3_descr_modes_R_DESCR_MODE_CL82 2 7123 7124 /**************************************************************************** 7125 * Enums: rx_x4_status3_r_dec_tl_mode 7126 */ 7127 #define rx_x4_status3_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 7128 #define rx_x4_status3_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 7129 #define rx_x4_status3_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 7130 7131 /**************************************************************************** 7132 * Enums: rx_x4_status3_r_dec_fsm_mode 7133 */ 7134 #define rx_x4_status3_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 7135 #define rx_x4_status3_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 7136 #define rx_x4_status3_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 7137 7138 /**************************************************************************** 7139 * Enums: rx_x4_status3_r_deskew_mode 7140 */ 7141 #define rx_x4_status3_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 7142 #define rx_x4_status3_r_deskew_mode_R_DESKEW_MODE_20G 1 7143 #define rx_x4_status3_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 7144 #define rx_x4_status3_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 7145 #define rx_x4_status3_r_deskew_mode_R_DESKEW_MODE_100G 4 7146 #define rx_x4_status3_r_deskew_mode_R_DESKEW_MODE_CL49 5 7147 #define rx_x4_status3_r_deskew_mode_R_DESKEW_MODE_CL91 6 7148 7149 /**************************************************************************** 7150 * Enums: rx_x4_status3_bs_dist_modes 7151 */ 7152 #define rx_x4_status3_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 7153 #define rx_x4_status3_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 7154 #define rx_x4_status3_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 7155 #define rx_x4_status3_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 7156 7157 /**************************************************************************** 7158 * Enums: rx_x4_status3_cl49_t_type 7159 */ 7160 #define rx_x4_status3_cl49_t_type_BAD_T_TYPE 15 7161 #define rx_x4_status3_cl49_t_type_T_TYPE_B0 11 7162 #define rx_x4_status3_cl49_t_type_T_TYPE_OB 10 7163 #define rx_x4_status3_cl49_t_type_T_TYPE_B1 9 7164 #define rx_x4_status3_cl49_t_type_T_TYPE_DB 8 7165 #define rx_x4_status3_cl49_t_type_T_TYPE_FC 7 7166 #define rx_x4_status3_cl49_t_type_T_TYPE_TB 6 7167 #define rx_x4_status3_cl49_t_type_T_TYPE_LI 5 7168 #define rx_x4_status3_cl49_t_type_T_TYPE_C 4 7169 #define rx_x4_status3_cl49_t_type_T_TYPE_S 3 7170 #define rx_x4_status3_cl49_t_type_T_TYPE_T 2 7171 #define rx_x4_status3_cl49_t_type_T_TYPE_D 1 7172 #define rx_x4_status3_cl49_t_type_T_TYPE_E 0 7173 7174 /**************************************************************************** 7175 * Enums: rx_x4_status3_cl49_txsm_states 7176 */ 7177 #define rx_x4_status3_cl49_txsm_states_TX_HIG_END 7 7178 #define rx_x4_status3_cl49_txsm_states_TX_HIG_START 6 7179 #define rx_x4_status3_cl49_txsm_states_TX_LI 5 7180 #define rx_x4_status3_cl49_txsm_states_TX_E 4 7181 #define rx_x4_status3_cl49_txsm_states_TX_T 3 7182 #define rx_x4_status3_cl49_txsm_states_TX_D 2 7183 #define rx_x4_status3_cl49_txsm_states_TX_C 1 7184 #define rx_x4_status3_cl49_txsm_states_TX_INIT 0 7185 7186 /**************************************************************************** 7187 * Enums: rx_x4_status3_cl49_ltxsm_states 7188 */ 7189 #define rx_x4_status3_cl49_ltxsm_states_TX_HIG_END 128 7190 #define rx_x4_status3_cl49_ltxsm_states_TX_HIG_START 64 7191 #define rx_x4_status3_cl49_ltxsm_states_TX_LI 32 7192 #define rx_x4_status3_cl49_ltxsm_states_TX_E 16 7193 #define rx_x4_status3_cl49_ltxsm_states_TX_T 8 7194 #define rx_x4_status3_cl49_ltxsm_states_TX_D 4 7195 #define rx_x4_status3_cl49_ltxsm_states_TX_C 2 7196 #define rx_x4_status3_cl49_ltxsm_states_TX_INIT 1 7197 7198 /**************************************************************************** 7199 * Enums: rx_x4_status3_burst_error_mode 7200 */ 7201 #define rx_x4_status3_burst_error_mode_BURST_ERROR_11_BITS 0 7202 #define rx_x4_status3_burst_error_mode_BURST_ERROR_16_BITS 1 7203 #define rx_x4_status3_burst_error_mode_BURST_ERROR_17_BITS 2 7204 #define rx_x4_status3_burst_error_mode_BURST_ERROR_18_BITS 3 7205 #define rx_x4_status3_burst_error_mode_BURST_ERROR_19_BITS 4 7206 #define rx_x4_status3_burst_error_mode_BURST_ERROR_20_BITS 5 7207 #define rx_x4_status3_burst_error_mode_BURST_ERROR_21_BITS 6 7208 #define rx_x4_status3_burst_error_mode_BURST_ERROR_22_BITS 7 7209 #define rx_x4_status3_burst_error_mode_BURST_ERROR_23_BITS 8 7210 #define rx_x4_status3_burst_error_mode_BURST_ERROR_24_BITS 9 7211 #define rx_x4_status3_burst_error_mode_BURST_ERROR_25_BITS 10 7212 #define rx_x4_status3_burst_error_mode_BURST_ERROR_26_BITS 11 7213 #define rx_x4_status3_burst_error_mode_BURST_ERROR_27_BITS 12 7214 #define rx_x4_status3_burst_error_mode_BURST_ERROR_28_BITS 13 7215 #define rx_x4_status3_burst_error_mode_BURST_ERROR_29_BITS 14 7216 #define rx_x4_status3_burst_error_mode_BURST_ERROR_30_BITS 15 7217 #define rx_x4_status3_burst_error_mode_BURST_ERROR_31_BITS 16 7218 #define rx_x4_status3_burst_error_mode_BURST_ERROR_32_BITS 17 7219 #define rx_x4_status3_burst_error_mode_BURST_ERROR_33_BITS 18 7220 #define rx_x4_status3_burst_error_mode_BURST_ERROR_34_BITS 19 7221 #define rx_x4_status3_burst_error_mode_BURST_ERROR_35_BITS 20 7222 #define rx_x4_status3_burst_error_mode_BURST_ERROR_36_BITS 21 7223 #define rx_x4_status3_burst_error_mode_BURST_ERROR_37_BITS 22 7224 #define rx_x4_status3_burst_error_mode_BURST_ERROR_38_BITS 23 7225 #define rx_x4_status3_burst_error_mode_BURST_ERROR_39_BITS 24 7226 #define rx_x4_status3_burst_error_mode_BURST_ERROR_40_BITS 25 7227 #define rx_x4_status3_burst_error_mode_BURST_ERROR_41_BITS 26 7228 7229 /**************************************************************************** 7230 * Enums: rx_x4_status3_bermon_state 7231 */ 7232 #define rx_x4_status3_bermon_state_HI_BER 4 7233 #define rx_x4_status3_bermon_state_GOOD_BER 3 7234 #define rx_x4_status3_bermon_state_BER_TEST_SH 2 7235 #define rx_x4_status3_bermon_state_START_TIMER 1 7236 #define rx_x4_status3_bermon_state_BER_MT_INIT 0 7237 7238 /**************************************************************************** 7239 * Enums: rx_x4_status3_rxsm_state_cl49 7240 */ 7241 #define rx_x4_status3_rxsm_state_cl49_RX_HIG_END 128 7242 #define rx_x4_status3_rxsm_state_cl49_RX_HIG_START 64 7243 #define rx_x4_status3_rxsm_state_cl49_RX_LI 32 7244 #define rx_x4_status3_rxsm_state_cl49_RX_E 16 7245 #define rx_x4_status3_rxsm_state_cl49_RX_T 8 7246 #define rx_x4_status3_rxsm_state_cl49_RX_D 4 7247 #define rx_x4_status3_rxsm_state_cl49_RX_C 2 7248 #define rx_x4_status3_rxsm_state_cl49_RX_INIT 1 7249 7250 /**************************************************************************** 7251 * Enums: rx_x4_status3_r_type 7252 */ 7253 #define rx_x4_status3_r_type_BAD_R_TYPE 15 7254 #define rx_x4_status3_r_type_R_TYPE_B0 11 7255 #define rx_x4_status3_r_type_R_TYPE_OB 10 7256 #define rx_x4_status3_r_type_R_TYPE_B1 9 7257 #define rx_x4_status3_r_type_R_TYPE_DB 8 7258 #define rx_x4_status3_r_type_R_TYPE_FC 7 7259 #define rx_x4_status3_r_type_R_TYPE_TB 6 7260 #define rx_x4_status3_r_type_R_TYPE_LI 5 7261 #define rx_x4_status3_r_type_R_TYPE_C 4 7262 #define rx_x4_status3_r_type_R_TYPE_S 3 7263 #define rx_x4_status3_r_type_R_TYPE_T 2 7264 #define rx_x4_status3_r_type_R_TYPE_D 1 7265 #define rx_x4_status3_r_type_R_TYPE_E 0 7266 7267 /**************************************************************************** 7268 * Enums: rx_x4_status3_am_lock_state 7269 */ 7270 #define rx_x4_status3_am_lock_state_INVALID_AM 512 7271 #define rx_x4_status3_am_lock_state_GOOD_AM 256 7272 #define rx_x4_status3_am_lock_state_COMP_AM 128 7273 #define rx_x4_status3_am_lock_state_TIMER_2 64 7274 #define rx_x4_status3_am_lock_state_AM_2_GOOD 32 7275 #define rx_x4_status3_am_lock_state_COMP_2ND 16 7276 #define rx_x4_status3_am_lock_state_TIMER_1 8 7277 #define rx_x4_status3_am_lock_state_FIND_1ST 4 7278 #define rx_x4_status3_am_lock_state_AM_RESET_CNT 2 7279 #define rx_x4_status3_am_lock_state_AM_LOCK_INIT 1 7280 7281 /**************************************************************************** 7282 * Enums: rx_x4_status3_msg_selector 7283 */ 7284 #define rx_x4_status3_msg_selector_RESERVED 0 7285 #define rx_x4_status3_msg_selector_VALUE_802p3 1 7286 #define rx_x4_status3_msg_selector_VALUE_802p9 2 7287 #define rx_x4_status3_msg_selector_VALUE_802p5 3 7288 #define rx_x4_status3_msg_selector_VALUE_1394 4 7289 7290 /**************************************************************************** 7291 * Enums: rx_x4_status3_synce_enum 7292 */ 7293 #define rx_x4_status3_synce_enum_SYNCE_NO_DIV 0 7294 #define rx_x4_status3_synce_enum_SYNCE_DIV_7 1 7295 #define rx_x4_status3_synce_enum_SYNCE_DIV_11 2 7296 7297 /**************************************************************************** 7298 * Enums: rx_x4_status3_synce_enum_stage0 7299 */ 7300 #define rx_x4_status3_synce_enum_stage0_SYNCE_NO_DIV 0 7301 #define rx_x4_status3_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 7302 #define rx_x4_status3_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 7303 7304 /**************************************************************************** 7305 * Enums: rx_x4_status3_cl91_sync_state 7306 */ 7307 #define rx_x4_status3_cl91_sync_state_FIND_1ST 0 7308 #define rx_x4_status3_cl91_sync_state_COUNT_NEXT 1 7309 #define rx_x4_status3_cl91_sync_state_COMP_2ND 2 7310 #define rx_x4_status3_cl91_sync_state_TWO_GOOD 3 7311 7312 /**************************************************************************** 7313 * Enums: rx_x4_status3_cl91_algn_state 7314 */ 7315 #define rx_x4_status3_cl91_algn_state_LOSS_OF_ALIGNMENT 0 7316 #define rx_x4_status3_cl91_algn_state_DESKEW 1 7317 #define rx_x4_status3_cl91_algn_state_DESKEW_FAIL 2 7318 #define rx_x4_status3_cl91_algn_state_ALIGN_ACQUIRED 3 7319 #define rx_x4_status3_cl91_algn_state_CW_GOOD 4 7320 #define rx_x4_status3_cl91_algn_state_CW_BAD 5 7321 #define rx_x4_status3_cl91_algn_state_THREE_BAD 6 7322 7323 /**************************************************************************** 7324 * Enums: rx_x4_status3_fec_sel 7325 */ 7326 #define rx_x4_status3_fec_sel_NO_FEC 0 7327 #define rx_x4_status3_fec_sel_FEC_CL74 1 7328 #define rx_x4_status3_fec_sel_FEC_CL91 2 7329 7330 /**************************************************************************** 7331 * Enums: rx_x4_status4_cl36TxEEEStates_l 7332 */ 7333 #define rx_x4_status4_cl36TxEEEStates_l_TX_REFRESH 8 7334 #define rx_x4_status4_cl36TxEEEStates_l_TX_QUIET 4 7335 #define rx_x4_status4_cl36TxEEEStates_l_TX_SLEEP 2 7336 #define rx_x4_status4_cl36TxEEEStates_l_TX_ACTIVE 1 7337 7338 /**************************************************************************** 7339 * Enums: rx_x4_status4_cl36TxEEEStates_c 7340 */ 7341 #define rx_x4_status4_cl36TxEEEStates_c_TX_REFRESH 3 7342 #define rx_x4_status4_cl36TxEEEStates_c_TX_QUIET 2 7343 #define rx_x4_status4_cl36TxEEEStates_c_TX_SLEEP 1 7344 #define rx_x4_status4_cl36TxEEEStates_c_TX_ACTIVE 0 7345 7346 /**************************************************************************** 7347 * Enums: rx_x4_status4_cl49TxEEEStates_l 7348 */ 7349 #define rx_x4_status4_cl49TxEEEStates_l_SCR_RESET_2 64 7350 #define rx_x4_status4_cl49TxEEEStates_l_SCR_RESET_1 32 7351 #define rx_x4_status4_cl49TxEEEStates_l_TX_WAKE 16 7352 #define rx_x4_status4_cl49TxEEEStates_l_TX_REFRESH 8 7353 #define rx_x4_status4_cl49TxEEEStates_l_TX_QUIET 4 7354 #define rx_x4_status4_cl49TxEEEStates_l_TX_SLEEP 2 7355 #define rx_x4_status4_cl49TxEEEStates_l_TX_ACTIVE 1 7356 7357 /**************************************************************************** 7358 * Enums: rx_x4_status4_fec_req_enum 7359 */ 7360 #define rx_x4_status4_fec_req_enum_FEC_not_supported 0 7361 #define rx_x4_status4_fec_req_enum_FEC_supported_but_not_requested 1 7362 #define rx_x4_status4_fec_req_enum_invalid_setting 2 7363 #define rx_x4_status4_fec_req_enum_FEC_supported_and_requested 3 7364 7365 /**************************************************************************** 7366 * Enums: rx_x4_status4_cl73_pause_enum 7367 */ 7368 #define rx_x4_status4_cl73_pause_enum_No_PAUSE_ability 0 7369 #define rx_x4_status4_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 7370 #define rx_x4_status4_cl73_pause_enum_Symmetric_PAUSE_ability 1 7371 #define rx_x4_status4_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 7372 7373 /**************************************************************************** 7374 * Enums: rx_x4_status4_cl49TxEEEStates_c 7375 */ 7376 #define rx_x4_status4_cl49TxEEEStates_c_SCR_RESET_2 6 7377 #define rx_x4_status4_cl49TxEEEStates_c_SCR_RESET_1 5 7378 #define rx_x4_status4_cl49TxEEEStates_c_TX_WAKE 4 7379 #define rx_x4_status4_cl49TxEEEStates_c_TX_REFRESH 3 7380 #define rx_x4_status4_cl49TxEEEStates_c_TX_QUIET 2 7381 #define rx_x4_status4_cl49TxEEEStates_c_TX_SLEEP 1 7382 #define rx_x4_status4_cl49TxEEEStates_c_TX_ACTIVE 0 7383 7384 /**************************************************************************** 7385 * Enums: rx_x4_status4_cl36RxEEEStates_l 7386 */ 7387 #define rx_x4_status4_cl36RxEEEStates_l_RX_LINK_FAIL 32 7388 #define rx_x4_status4_cl36RxEEEStates_l_RX_WTF 16 7389 #define rx_x4_status4_cl36RxEEEStates_l_RX_WAKE 8 7390 #define rx_x4_status4_cl36RxEEEStates_l_RX_QUIET 4 7391 #define rx_x4_status4_cl36RxEEEStates_l_RX_SLEEP 2 7392 #define rx_x4_status4_cl36RxEEEStates_l_RX_ACTIVE 1 7393 7394 /**************************************************************************** 7395 * Enums: rx_x4_status4_cl36RxEEEStates_c 7396 */ 7397 #define rx_x4_status4_cl36RxEEEStates_c_RX_LINK_FAIL 5 7398 #define rx_x4_status4_cl36RxEEEStates_c_RX_WTF 4 7399 #define rx_x4_status4_cl36RxEEEStates_c_RX_WAKE 3 7400 #define rx_x4_status4_cl36RxEEEStates_c_RX_QUIET 2 7401 #define rx_x4_status4_cl36RxEEEStates_c_RX_SLEEP 1 7402 #define rx_x4_status4_cl36RxEEEStates_c_RX_ACTIVE 0 7403 7404 /**************************************************************************** 7405 * Enums: rx_x4_status4_cl49RxEEEStates_l 7406 */ 7407 #define rx_x4_status4_cl49RxEEEStates_l_RX_LINK_FAIL 32 7408 #define rx_x4_status4_cl49RxEEEStates_l_RX_WTF 16 7409 #define rx_x4_status4_cl49RxEEEStates_l_RX_WAKE 8 7410 #define rx_x4_status4_cl49RxEEEStates_l_RX_QUIET 4 7411 #define rx_x4_status4_cl49RxEEEStates_l_RX_SLEEP 2 7412 #define rx_x4_status4_cl49RxEEEStates_l_RX_ACTIVE 1 7413 7414 /**************************************************************************** 7415 * Enums: rx_x4_status4_cl49RxEEEStates_c 7416 */ 7417 #define rx_x4_status4_cl49RxEEEStates_c_RX_LINK_FAIL 5 7418 #define rx_x4_status4_cl49RxEEEStates_c_RX_WTF 4 7419 #define rx_x4_status4_cl49RxEEEStates_c_RX_WAKE 3 7420 #define rx_x4_status4_cl49RxEEEStates_c_RX_QUIET 2 7421 #define rx_x4_status4_cl49RxEEEStates_c_RX_SLEEP 1 7422 #define rx_x4_status4_cl49RxEEEStates_c_RX_ACTIVE 0 7423 7424 /**************************************************************************** 7425 * Enums: rx_x4_status4_cl48TxEEEStates_l 7426 */ 7427 #define rx_x4_status4_cl48TxEEEStates_l_TX_REFRESH 8 7428 #define rx_x4_status4_cl48TxEEEStates_l_TX_QUIET 4 7429 #define rx_x4_status4_cl48TxEEEStates_l_TX_SLEEP 2 7430 #define rx_x4_status4_cl48TxEEEStates_l_TX_ACTIVE 1 7431 7432 /**************************************************************************** 7433 * Enums: rx_x4_status4_cl48TxEEEStates_c 7434 */ 7435 #define rx_x4_status4_cl48TxEEEStates_c_TX_REFRESH 3 7436 #define rx_x4_status4_cl48TxEEEStates_c_TX_QUIET 2 7437 #define rx_x4_status4_cl48TxEEEStates_c_TX_SLEEP 1 7438 #define rx_x4_status4_cl48TxEEEStates_c_TX_ACTIVE 0 7439 7440 /**************************************************************************** 7441 * Enums: rx_x4_status4_cl48RxEEEStates_l 7442 */ 7443 #define rx_x4_status4_cl48RxEEEStates_l_RX_LINK_FAIL 32 7444 #define rx_x4_status4_cl48RxEEEStates_l_RX_WAKE 16 7445 #define rx_x4_status4_cl48RxEEEStates_l_RX_QUIET 8 7446 #define rx_x4_status4_cl48RxEEEStates_l_RX_DEACT 4 7447 #define rx_x4_status4_cl48RxEEEStates_l_RX_SLEEP 2 7448 #define rx_x4_status4_cl48RxEEEStates_l_RX_ACTIVE 1 7449 7450 /**************************************************************************** 7451 * Enums: rx_x4_status4_cl48RxEEEStates_c 7452 */ 7453 #define rx_x4_status4_cl48RxEEEStates_c_RX_LINK_FAIL 5 7454 #define rx_x4_status4_cl48RxEEEStates_c_RX_WAKE 4 7455 #define rx_x4_status4_cl48RxEEEStates_c_RX_QUIET 3 7456 #define rx_x4_status4_cl48RxEEEStates_c_RX_DEACT 2 7457 #define rx_x4_status4_cl48RxEEEStates_c_RX_SLEEP 1 7458 #define rx_x4_status4_cl48RxEEEStates_c_RX_ACTIVE 0 7459 7460 /**************************************************************************** 7461 * Enums: rx_x4_status4_IQP_Options 7462 */ 7463 #define rx_x4_status4_IQP_Options_i50uA 0 7464 #define rx_x4_status4_IQP_Options_i100uA 1 7465 #define rx_x4_status4_IQP_Options_i150uA 2 7466 #define rx_x4_status4_IQP_Options_i200uA 3 7467 #define rx_x4_status4_IQP_Options_i250uA 4 7468 #define rx_x4_status4_IQP_Options_i300uA 5 7469 #define rx_x4_status4_IQP_Options_i350uA 6 7470 #define rx_x4_status4_IQP_Options_i400uA 7 7471 #define rx_x4_status4_IQP_Options_i450uA 8 7472 #define rx_x4_status4_IQP_Options_i500uA 9 7473 #define rx_x4_status4_IQP_Options_i550uA 10 7474 #define rx_x4_status4_IQP_Options_i600uA 11 7475 #define rx_x4_status4_IQP_Options_i650uA 12 7476 #define rx_x4_status4_IQP_Options_i700uA 13 7477 #define rx_x4_status4_IQP_Options_i750uA 14 7478 #define rx_x4_status4_IQP_Options_i800uA 15 7479 7480 /**************************************************************************** 7481 * Enums: rx_x4_status4_IDriver_Options 7482 */ 7483 #define rx_x4_status4_IDriver_Options_v680mV 0 7484 #define rx_x4_status4_IDriver_Options_v730mV 1 7485 #define rx_x4_status4_IDriver_Options_v780mV 2 7486 #define rx_x4_status4_IDriver_Options_v830mV 3 7487 #define rx_x4_status4_IDriver_Options_v880mV 4 7488 #define rx_x4_status4_IDriver_Options_v930mV 5 7489 #define rx_x4_status4_IDriver_Options_v980mV 6 7490 #define rx_x4_status4_IDriver_Options_v1010mV 7 7491 #define rx_x4_status4_IDriver_Options_v1040mV 8 7492 #define rx_x4_status4_IDriver_Options_v1060mV 9 7493 #define rx_x4_status4_IDriver_Options_v1070mV 10 7494 #define rx_x4_status4_IDriver_Options_v1080mV 11 7495 #define rx_x4_status4_IDriver_Options_v1085mV 12 7496 #define rx_x4_status4_IDriver_Options_v1090mV 13 7497 #define rx_x4_status4_IDriver_Options_v1095mV 14 7498 #define rx_x4_status4_IDriver_Options_v1100mV 15 7499 7500 /**************************************************************************** 7501 * Enums: rx_x4_status4_operationModes 7502 */ 7503 #define rx_x4_status4_operationModes_XGXS 0 7504 #define rx_x4_status4_operationModes_XGXG_nCC 1 7505 #define rx_x4_status4_operationModes_Indlane_OS8 4 7506 #define rx_x4_status4_operationModes_IndLane_OS5 5 7507 #define rx_x4_status4_operationModes_PCI 7 7508 #define rx_x4_status4_operationModes_XGXS_nLQ 8 7509 #define rx_x4_status4_operationModes_XGXS_nLQnCC 9 7510 #define rx_x4_status4_operationModes_PBypass 10 7511 #define rx_x4_status4_operationModes_PBypass_nDSK 11 7512 #define rx_x4_status4_operationModes_ComboCoreMode 12 7513 #define rx_x4_status4_operationModes_Clocks_off 15 7514 7515 /**************************************************************************** 7516 * Enums: rx_x4_status4_actualSpeeds 7517 */ 7518 #define rx_x4_status4_actualSpeeds_dr_10M 0 7519 #define rx_x4_status4_actualSpeeds_dr_100M 1 7520 #define rx_x4_status4_actualSpeeds_dr_1G 2 7521 #define rx_x4_status4_actualSpeeds_dr_2p5G 3 7522 #define rx_x4_status4_actualSpeeds_dr_5G_X4 4 7523 #define rx_x4_status4_actualSpeeds_dr_6G_X4 5 7524 #define rx_x4_status4_actualSpeeds_dr_10G_HiG 6 7525 #define rx_x4_status4_actualSpeeds_dr_10G_CX4 7 7526 #define rx_x4_status4_actualSpeeds_dr_12G_HiG 8 7527 #define rx_x4_status4_actualSpeeds_dr_12p5G_X4 9 7528 #define rx_x4_status4_actualSpeeds_dr_13G_X4 10 7529 #define rx_x4_status4_actualSpeeds_dr_15G_X4 11 7530 #define rx_x4_status4_actualSpeeds_dr_16G_X4 12 7531 #define rx_x4_status4_actualSpeeds_dr_1G_KX 13 7532 #define rx_x4_status4_actualSpeeds_dr_10G_KX4 14 7533 #define rx_x4_status4_actualSpeeds_dr_10G_KR 15 7534 #define rx_x4_status4_actualSpeeds_dr_5G 16 7535 #define rx_x4_status4_actualSpeeds_dr_6p4G 17 7536 #define rx_x4_status4_actualSpeeds_dr_20G_X4 18 7537 #define rx_x4_status4_actualSpeeds_dr_21G_X4 19 7538 #define rx_x4_status4_actualSpeeds_dr_25G_X4 20 7539 #define rx_x4_status4_actualSpeeds_dr_10G_HiG_DXGXS 21 7540 #define rx_x4_status4_actualSpeeds_dr_10G_DXGXS 22 7541 #define rx_x4_status4_actualSpeeds_dr_10p5G_HiG_DXGXS 23 7542 #define rx_x4_status4_actualSpeeds_dr_10p5G_DXGXS 24 7543 #define rx_x4_status4_actualSpeeds_dr_12p773G_HiG_DXGXS 25 7544 #define rx_x4_status4_actualSpeeds_dr_12p773G_DXGXS 26 7545 #define rx_x4_status4_actualSpeeds_dr_10G_XFI 27 7546 #define rx_x4_status4_actualSpeeds_dr_40G 28 7547 #define rx_x4_status4_actualSpeeds_dr_20G_HiG_DXGXS 29 7548 #define rx_x4_status4_actualSpeeds_dr_20G_DXGXS 30 7549 #define rx_x4_status4_actualSpeeds_dr_10G_SFI 31 7550 #define rx_x4_status4_actualSpeeds_dr_31p5G 32 7551 #define rx_x4_status4_actualSpeeds_dr_32p7G 33 7552 #define rx_x4_status4_actualSpeeds_dr_20G_SCR 34 7553 #define rx_x4_status4_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 7554 #define rx_x4_status4_actualSpeeds_dr_10G_DXGXS_SCR 36 7555 #define rx_x4_status4_actualSpeeds_dr_12G_R2 37 7556 #define rx_x4_status4_actualSpeeds_dr_10G_X2 38 7557 #define rx_x4_status4_actualSpeeds_dr_40G_KR4 39 7558 #define rx_x4_status4_actualSpeeds_dr_40G_CR4 40 7559 #define rx_x4_status4_actualSpeeds_dr_100G_CR10 41 7560 #define rx_x4_status4_actualSpeeds_dr_15p75G_DXGXS 44 7561 #define rx_x4_status4_actualSpeeds_dr_20G_KR2 57 7562 #define rx_x4_status4_actualSpeeds_dr_20G_CR2 58 7563 7564 /**************************************************************************** 7565 * Enums: rx_x4_status4_actualSpeedsMisc1 7566 */ 7567 #define rx_x4_status4_actualSpeedsMisc1_dr_2500BRCM_X1 16 7568 #define rx_x4_status4_actualSpeedsMisc1_dr_5000BRCM_X4 17 7569 #define rx_x4_status4_actualSpeedsMisc1_dr_6000BRCM_X4 18 7570 #define rx_x4_status4_actualSpeedsMisc1_dr_10GHiGig_X4 19 7571 #define rx_x4_status4_actualSpeedsMisc1_dr_10GBASE_CX4 20 7572 #define rx_x4_status4_actualSpeedsMisc1_dr_12GHiGig_X4 21 7573 #define rx_x4_status4_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 7574 #define rx_x4_status4_actualSpeedsMisc1_dr_13GHiGig_X4 23 7575 #define rx_x4_status4_actualSpeedsMisc1_dr_15GHiGig_X4 24 7576 #define rx_x4_status4_actualSpeedsMisc1_dr_16GHiGig_X4 25 7577 #define rx_x4_status4_actualSpeedsMisc1_dr_5000BRCM_X1 26 7578 #define rx_x4_status4_actualSpeedsMisc1_dr_6363BRCM_X1 27 7579 #define rx_x4_status4_actualSpeedsMisc1_dr_20GHiGig_X4 28 7580 #define rx_x4_status4_actualSpeedsMisc1_dr_21GHiGig_X4 29 7581 #define rx_x4_status4_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 7582 #define rx_x4_status4_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 7583 7584 /**************************************************************************** 7585 * Enums: rx_x4_status4_IndLaneModes 7586 */ 7587 #define rx_x4_status4_IndLaneModes_SWSDR_div2 0 7588 #define rx_x4_status4_IndLaneModes_SWSDR_div1 1 7589 #define rx_x4_status4_IndLaneModes_DWSDR_div2 2 7590 #define rx_x4_status4_IndLaneModes_DWSDR_div1 3 7591 7592 /**************************************************************************** 7593 * Enums: rx_x4_status4_prbsSelect 7594 */ 7595 #define rx_x4_status4_prbsSelect_prbs7 0 7596 #define rx_x4_status4_prbsSelect_prbs15 1 7597 #define rx_x4_status4_prbsSelect_prbs23 2 7598 #define rx_x4_status4_prbsSelect_prbs31 3 7599 7600 /**************************************************************************** 7601 * Enums: rx_x4_status4_vcoDivider 7602 */ 7603 #define rx_x4_status4_vcoDivider_div32 0 7604 #define rx_x4_status4_vcoDivider_div36 1 7605 #define rx_x4_status4_vcoDivider_div40 2 7606 #define rx_x4_status4_vcoDivider_div42 3 7607 #define rx_x4_status4_vcoDivider_div48 4 7608 #define rx_x4_status4_vcoDivider_div50 5 7609 #define rx_x4_status4_vcoDivider_div52 6 7610 #define rx_x4_status4_vcoDivider_div54 7 7611 #define rx_x4_status4_vcoDivider_div60 8 7612 #define rx_x4_status4_vcoDivider_div64 9 7613 #define rx_x4_status4_vcoDivider_div66 10 7614 #define rx_x4_status4_vcoDivider_div68 11 7615 #define rx_x4_status4_vcoDivider_div70 12 7616 #define rx_x4_status4_vcoDivider_div80 13 7617 #define rx_x4_status4_vcoDivider_div92 14 7618 #define rx_x4_status4_vcoDivider_div100 15 7619 7620 /**************************************************************************** 7621 * Enums: rx_x4_status4_refClkSelect 7622 */ 7623 #define rx_x4_status4_refClkSelect_clk_25MHz 0 7624 #define rx_x4_status4_refClkSelect_clk_100MHz 1 7625 #define rx_x4_status4_refClkSelect_clk_125MHz 2 7626 #define rx_x4_status4_refClkSelect_clk_156p25MHz 3 7627 #define rx_x4_status4_refClkSelect_clk_187p5MHz 4 7628 #define rx_x4_status4_refClkSelect_clk_161p25Mhz 5 7629 #define rx_x4_status4_refClkSelect_clk_50Mhz 6 7630 #define rx_x4_status4_refClkSelect_clk_106p25Mhz 7 7631 7632 /**************************************************************************** 7633 * Enums: rx_x4_status4_aerMMDdevTypeSelect 7634 */ 7635 #define rx_x4_status4_aerMMDdevTypeSelect_combo_core 0 7636 #define rx_x4_status4_aerMMDdevTypeSelect_PMA_PMD 1 7637 #define rx_x4_status4_aerMMDdevTypeSelect_PCS 3 7638 #define rx_x4_status4_aerMMDdevTypeSelect_PHY 4 7639 #define rx_x4_status4_aerMMDdevTypeSelect_DTE 5 7640 #define rx_x4_status4_aerMMDdevTypeSelect_CL73_AN 7 7641 7642 /**************************************************************************** 7643 * Enums: rx_x4_status4_aerMMDportSelect 7644 */ 7645 #define rx_x4_status4_aerMMDportSelect_ln0 0 7646 #define rx_x4_status4_aerMMDportSelect_ln1 1 7647 #define rx_x4_status4_aerMMDportSelect_ln2 2 7648 #define rx_x4_status4_aerMMDportSelect_ln3 3 7649 #define rx_x4_status4_aerMMDportSelect_BCST_ln0_1_2_3 511 7650 #define rx_x4_status4_aerMMDportSelect_BCST_ln0_1 512 7651 #define rx_x4_status4_aerMMDportSelect_BCST_ln2_3 513 7652 7653 /**************************************************************************** 7654 * Enums: rx_x4_status4_firmwareModeSelect 7655 */ 7656 #define rx_x4_status4_firmwareModeSelect_DEFAULT 0 7657 #define rx_x4_status4_firmwareModeSelect_SFP_OPT_LR 1 7658 #define rx_x4_status4_firmwareModeSelect_SFP_DAC 2 7659 #define rx_x4_status4_firmwareModeSelect_XLAUI 3 7660 #define rx_x4_status4_firmwareModeSelect_LONG_CH_6G 4 7661 7662 /**************************************************************************** 7663 * Enums: rx_x4_status4_tempIdxSelect 7664 */ 7665 #define rx_x4_status4_tempIdxSelect_LTE__22p9C 15 7666 #define rx_x4_status4_tempIdxSelect_LTE__12p6C 14 7667 #define rx_x4_status4_tempIdxSelect_LTE__3p0C 13 7668 #define rx_x4_status4_tempIdxSelect_LTE_6p7C 12 7669 #define rx_x4_status4_tempIdxSelect_LTE_16p4C 11 7670 #define rx_x4_status4_tempIdxSelect_LTE_26p6C 10 7671 #define rx_x4_status4_tempIdxSelect_LTE_36p3C 9 7672 #define rx_x4_status4_tempIdxSelect_LTE_46p0C 8 7673 #define rx_x4_status4_tempIdxSelect_LTE_56p2C 7 7674 #define rx_x4_status4_tempIdxSelect_LTE_65p9C 6 7675 #define rx_x4_status4_tempIdxSelect_LTE_75p6C 5 7676 #define rx_x4_status4_tempIdxSelect_LTE_85p3C 4 7677 #define rx_x4_status4_tempIdxSelect_LTE_95p5C 3 7678 #define rx_x4_status4_tempIdxSelect_LTE_105p2C 2 7679 #define rx_x4_status4_tempIdxSelect_LTE_114p9C 1 7680 #define rx_x4_status4_tempIdxSelect_LTE_125p1C 0 7681 7682 /**************************************************************************** 7683 * Enums: rx_x4_status4_port_mode 7684 */ 7685 #define rx_x4_status4_port_mode_QUAD_PORT 0 7686 #define rx_x4_status4_port_mode_TRI_1_PORT 1 7687 #define rx_x4_status4_port_mode_TRI_2_PORT 2 7688 #define rx_x4_status4_port_mode_DUAL_PORT 3 7689 #define rx_x4_status4_port_mode_SINGLE_PORT 4 7690 7691 /**************************************************************************** 7692 * Enums: rx_x4_status4_rev_letter_enum 7693 */ 7694 #define rx_x4_status4_rev_letter_enum_REV_A 0 7695 #define rx_x4_status4_rev_letter_enum_REV_B 1 7696 #define rx_x4_status4_rev_letter_enum_REV_C 2 7697 #define rx_x4_status4_rev_letter_enum_REV_D 3 7698 7699 /**************************************************************************** 7700 * Enums: rx_x4_status4_rev_number_enum 7701 */ 7702 #define rx_x4_status4_rev_number_enum_REV_0 0 7703 #define rx_x4_status4_rev_number_enum_REV_1 1 7704 #define rx_x4_status4_rev_number_enum_REV_2 2 7705 #define rx_x4_status4_rev_number_enum_REV_3 3 7706 #define rx_x4_status4_rev_number_enum_REV_4 4 7707 #define rx_x4_status4_rev_number_enum_REV_5 5 7708 #define rx_x4_status4_rev_number_enum_REV_6 6 7709 #define rx_x4_status4_rev_number_enum_REV_7 7 7710 7711 /**************************************************************************** 7712 * Enums: rx_x4_status4_bonding_enum 7713 */ 7714 #define rx_x4_status4_bonding_enum_WIRE_BOND 0 7715 #define rx_x4_status4_bonding_enum_FLIP_CHIP 1 7716 7717 /**************************************************************************** 7718 * Enums: rx_x4_status4_tech_process 7719 */ 7720 #define rx_x4_status4_tech_process_PROCESS_90NM 0 7721 #define rx_x4_status4_tech_process_PROCESS_65NM 1 7722 #define rx_x4_status4_tech_process_PROCESS_40NM 2 7723 #define rx_x4_status4_tech_process_PROCESS_28NM 3 7724 7725 /**************************************************************************** 7726 * Enums: rx_x4_status4_model_num 7727 */ 7728 #define rx_x4_status4_model_num_SERDES_CL73 0 7729 #define rx_x4_status4_model_num_XGXS_16G 1 7730 #define rx_x4_status4_model_num_HYPERCORE 2 7731 #define rx_x4_status4_model_num_HYPERLITE 3 7732 #define rx_x4_status4_model_num_PCIE_G2_PIPE 4 7733 #define rx_x4_status4_model_num_SERDES_1p25GBd 5 7734 #define rx_x4_status4_model_num_SATA2 6 7735 #define rx_x4_status4_model_num_QSGMII 7 7736 #define rx_x4_status4_model_num_XGXS10G 8 7737 #define rx_x4_status4_model_num_WARPCORE 9 7738 #define rx_x4_status4_model_num_XFICORE 10 7739 #define rx_x4_status4_model_num_RXFI 11 7740 #define rx_x4_status4_model_num_WARPLITE 12 7741 #define rx_x4_status4_model_num_PENTACORE 13 7742 #define rx_x4_status4_model_num_ESM 14 7743 #define rx_x4_status4_model_num_QUAD_SGMII 15 7744 #define rx_x4_status4_model_num_WARPCORE_3 16 7745 #define rx_x4_status4_model_num_TSC 17 7746 #define rx_x4_status4_model_num_TSC4E 18 7747 #define rx_x4_status4_model_num_TSC12E 19 7748 #define rx_x4_status4_model_num_TSC4F 20 7749 #define rx_x4_status4_model_num_XGXS_CL73_90NM 29 7750 #define rx_x4_status4_model_num_SERDES_CL73_90NM 30 7751 #define rx_x4_status4_model_num_WARPCORE3 32 7752 #define rx_x4_status4_model_num_WARPCORE4_TSC 33 7753 #define rx_x4_status4_model_num_RXAUI 34 7754 7755 /**************************************************************************** 7756 * Enums: rx_x4_status4_payload 7757 */ 7758 #define rx_x4_status4_payload_REPEAT_2_BYTES 0 7759 #define rx_x4_status4_payload_RAMPING 1 7760 #define rx_x4_status4_payload_CL48_CRPAT 2 7761 #define rx_x4_status4_payload_CL48_CJPAT 3 7762 #define rx_x4_status4_payload_CL36_LONG_CRPAT 4 7763 #define rx_x4_status4_payload_CL36_SHORT_CRPAT 5 7764 7765 /**************************************************************************** 7766 * Enums: rx_x4_status4_sc 7767 */ 7768 #define rx_x4_status4_sc_S_10G_CR1 0 7769 #define rx_x4_status4_sc_S_10G_KR1 1 7770 #define rx_x4_status4_sc_S_10G_X1 2 7771 #define rx_x4_status4_sc_S_10G_HG2_CR1 4 7772 #define rx_x4_status4_sc_S_10G_HG2_KR1 5 7773 #define rx_x4_status4_sc_S_10G_HG2_X1 6 7774 #define rx_x4_status4_sc_S_20G_CR1 8 7775 #define rx_x4_status4_sc_S_20G_KR1 9 7776 #define rx_x4_status4_sc_S_20G_X1 10 7777 #define rx_x4_status4_sc_S_20G_HG2_CR1 12 7778 #define rx_x4_status4_sc_S_20G_HG2_KR1 13 7779 #define rx_x4_status4_sc_S_20G_HG2_X1 14 7780 #define rx_x4_status4_sc_S_25G_CR1 16 7781 #define rx_x4_status4_sc_S_25G_KR1 17 7782 #define rx_x4_status4_sc_S_25G_X1 18 7783 #define rx_x4_status4_sc_S_25G_HG2_CR1 20 7784 #define rx_x4_status4_sc_S_25G_HG2_KR1 21 7785 #define rx_x4_status4_sc_S_25G_HG2_X1 22 7786 #define rx_x4_status4_sc_S_20G_CR2 24 7787 #define rx_x4_status4_sc_S_20G_KR2 25 7788 #define rx_x4_status4_sc_S_20G_X2 26 7789 #define rx_x4_status4_sc_S_20G_HG2_CR2 28 7790 #define rx_x4_status4_sc_S_20G_HG2_KR2 29 7791 #define rx_x4_status4_sc_S_20G_HG2_X2 30 7792 #define rx_x4_status4_sc_S_40G_CR2 32 7793 #define rx_x4_status4_sc_S_40G_KR2 33 7794 #define rx_x4_status4_sc_S_40G_X2 34 7795 #define rx_x4_status4_sc_S_40G_HG2_CR2 36 7796 #define rx_x4_status4_sc_S_40G_HG2_KR2 37 7797 #define rx_x4_status4_sc_S_40G_HG2_X2 38 7798 #define rx_x4_status4_sc_S_40G_CR4 40 7799 #define rx_x4_status4_sc_S_40G_KR4 41 7800 #define rx_x4_status4_sc_S_40G_X4 42 7801 #define rx_x4_status4_sc_S_40G_HG2_CR4 44 7802 #define rx_x4_status4_sc_S_40G_HG2_KR4 45 7803 #define rx_x4_status4_sc_S_40G_HG2_X4 46 7804 #define rx_x4_status4_sc_S_50G_CR2 48 7805 #define rx_x4_status4_sc_S_50G_KR2 49 7806 #define rx_x4_status4_sc_S_50G_X2 50 7807 #define rx_x4_status4_sc_S_50G_HG2_CR2 52 7808 #define rx_x4_status4_sc_S_50G_HG2_KR2 53 7809 #define rx_x4_status4_sc_S_50G_HG2_X2 54 7810 #define rx_x4_status4_sc_S_50G_CR4 56 7811 #define rx_x4_status4_sc_S_50G_KR4 57 7812 #define rx_x4_status4_sc_S_50G_X4 58 7813 #define rx_x4_status4_sc_S_50G_HG2_CR4 60 7814 #define rx_x4_status4_sc_S_50G_HG2_KR4 61 7815 #define rx_x4_status4_sc_S_50G_HG2_X4 62 7816 #define rx_x4_status4_sc_S_100G_CR4 64 7817 #define rx_x4_status4_sc_S_100G_KR4 65 7818 #define rx_x4_status4_sc_S_100G_X4 66 7819 #define rx_x4_status4_sc_S_100G_HG2_CR4 68 7820 #define rx_x4_status4_sc_S_100G_HG2_KR4 69 7821 #define rx_x4_status4_sc_S_100G_HG2_X4 70 7822 #define rx_x4_status4_sc_S_CL73_20GVCO 72 7823 #define rx_x4_status4_sc_S_CL73_25GVCO 80 7824 #define rx_x4_status4_sc_S_CL36_20GVCO 88 7825 #define rx_x4_status4_sc_S_CL36_25GVCO 96 7826 7827 /**************************************************************************** 7828 * Enums: rx_x4_status4_t_fifo_modes 7829 */ 7830 #define rx_x4_status4_t_fifo_modes_T_FIFO_MODE_BYPASS 0 7831 #define rx_x4_status4_t_fifo_modes_T_FIFO_MODE_40G 1 7832 #define rx_x4_status4_t_fifo_modes_T_FIFO_MODE_100G 2 7833 #define rx_x4_status4_t_fifo_modes_T_FIFO_MODE_20G 3 7834 7835 /**************************************************************************** 7836 * Enums: rx_x4_status4_t_enc_modes 7837 */ 7838 #define rx_x4_status4_t_enc_modes_T_ENC_MODE_BYPASS 0 7839 #define rx_x4_status4_t_enc_modes_T_ENC_MODE_CL49 1 7840 #define rx_x4_status4_t_enc_modes_T_ENC_MODE_CL82 2 7841 7842 /**************************************************************************** 7843 * Enums: rx_x4_status4_btmx_mode 7844 */ 7845 #define rx_x4_status4_btmx_mode_BS_BTMX_MODE_1to1 0 7846 #define rx_x4_status4_btmx_mode_BS_BTMX_MODE_2to1 1 7847 #define rx_x4_status4_btmx_mode_BS_BTMX_MODE_5to1 2 7848 7849 /**************************************************************************** 7850 * Enums: rx_x4_status4_t_type_cl82 7851 */ 7852 #define rx_x4_status4_t_type_cl82_T_TYPE_B1 5 7853 #define rx_x4_status4_t_type_cl82_T_TYPE_C 4 7854 #define rx_x4_status4_t_type_cl82_T_TYPE_S 3 7855 #define rx_x4_status4_t_type_cl82_T_TYPE_T 2 7856 #define rx_x4_status4_t_type_cl82_T_TYPE_D 1 7857 #define rx_x4_status4_t_type_cl82_T_TYPE_E 0 7858 7859 /**************************************************************************** 7860 * Enums: rx_x4_status4_txsm_state_cl82 7861 */ 7862 #define rx_x4_status4_txsm_state_cl82_TX_HIG_END 6 7863 #define rx_x4_status4_txsm_state_cl82_TX_HIG_START 5 7864 #define rx_x4_status4_txsm_state_cl82_TX_E 4 7865 #define rx_x4_status4_txsm_state_cl82_TX_T 3 7866 #define rx_x4_status4_txsm_state_cl82_TX_D 2 7867 #define rx_x4_status4_txsm_state_cl82_TX_C 1 7868 #define rx_x4_status4_txsm_state_cl82_TX_INIT 0 7869 7870 /**************************************************************************** 7871 * Enums: rx_x4_status4_ltxsm_state_cl82 7872 */ 7873 #define rx_x4_status4_ltxsm_state_cl82_TX_HIG_END 64 7874 #define rx_x4_status4_ltxsm_state_cl82_TX_HIG_START 32 7875 #define rx_x4_status4_ltxsm_state_cl82_TX_E 16 7876 #define rx_x4_status4_ltxsm_state_cl82_TX_T 8 7877 #define rx_x4_status4_ltxsm_state_cl82_TX_D 4 7878 #define rx_x4_status4_ltxsm_state_cl82_TX_C 2 7879 #define rx_x4_status4_ltxsm_state_cl82_TX_INIT 1 7880 7881 /**************************************************************************** 7882 * Enums: rx_x4_status4_r_type_coded_cl82 7883 */ 7884 #define rx_x4_status4_r_type_coded_cl82_R_TYPE_B1 32 7885 #define rx_x4_status4_r_type_coded_cl82_R_TYPE_C 16 7886 #define rx_x4_status4_r_type_coded_cl82_R_TYPE_S 8 7887 #define rx_x4_status4_r_type_coded_cl82_R_TYPE_T 4 7888 #define rx_x4_status4_r_type_coded_cl82_R_TYPE_D 2 7889 #define rx_x4_status4_r_type_coded_cl82_R_TYPE_E 1 7890 7891 /**************************************************************************** 7892 * Enums: rx_x4_status4_rxsm_state_cl82 7893 */ 7894 #define rx_x4_status4_rxsm_state_cl82_RX_HIG_END 64 7895 #define rx_x4_status4_rxsm_state_cl82_RX_HIG_START 32 7896 #define rx_x4_status4_rxsm_state_cl82_RX_E 16 7897 #define rx_x4_status4_rxsm_state_cl82_RX_T 8 7898 #define rx_x4_status4_rxsm_state_cl82_RX_D 4 7899 #define rx_x4_status4_rxsm_state_cl82_RX_C 2 7900 #define rx_x4_status4_rxsm_state_cl82_RX_INIT 1 7901 7902 /**************************************************************************** 7903 * Enums: rx_x4_status4_deskew_state 7904 */ 7905 #define rx_x4_status4_deskew_state_ALIGN_ACQUIRED 2 7906 #define rx_x4_status4_deskew_state_LOSS_OF_ALIGNMENT 1 7907 7908 /**************************************************************************** 7909 * Enums: rx_x4_status4_os_mode_enum 7910 */ 7911 #define rx_x4_status4_os_mode_enum_OS_MODE_1 0 7912 #define rx_x4_status4_os_mode_enum_OS_MODE_2 1 7913 #define rx_x4_status4_os_mode_enum_OS_MODE_4 2 7914 #define rx_x4_status4_os_mode_enum_OS_MODE_16p5 8 7915 #define rx_x4_status4_os_mode_enum_OS_MODE_20p625 12 7916 7917 /**************************************************************************** 7918 * Enums: rx_x4_status4_scr_modes 7919 */ 7920 #define rx_x4_status4_scr_modes_T_SCR_MODE_BYPASS 0 7921 #define rx_x4_status4_scr_modes_T_SCR_MODE_CL49 1 7922 #define rx_x4_status4_scr_modes_T_SCR_MODE_40G_2_LANE 2 7923 #define rx_x4_status4_scr_modes_T_SCR_MODE_100G 3 7924 #define rx_x4_status4_scr_modes_T_SCR_MODE_20G 4 7925 #define rx_x4_status4_scr_modes_T_SCR_MODE_40G_4_LANE 5 7926 7927 /**************************************************************************** 7928 * Enums: rx_x4_status4_descr_modes 7929 */ 7930 #define rx_x4_status4_descr_modes_R_DESCR_MODE_BYPASS 0 7931 #define rx_x4_status4_descr_modes_R_DESCR_MODE_CL49 1 7932 #define rx_x4_status4_descr_modes_R_DESCR_MODE_CL82 2 7933 7934 /**************************************************************************** 7935 * Enums: rx_x4_status4_r_dec_tl_mode 7936 */ 7937 #define rx_x4_status4_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 7938 #define rx_x4_status4_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 7939 #define rx_x4_status4_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 7940 7941 /**************************************************************************** 7942 * Enums: rx_x4_status4_r_dec_fsm_mode 7943 */ 7944 #define rx_x4_status4_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 7945 #define rx_x4_status4_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 7946 #define rx_x4_status4_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 7947 7948 /**************************************************************************** 7949 * Enums: rx_x4_status4_r_deskew_mode 7950 */ 7951 #define rx_x4_status4_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 7952 #define rx_x4_status4_r_deskew_mode_R_DESKEW_MODE_20G 1 7953 #define rx_x4_status4_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 7954 #define rx_x4_status4_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 7955 #define rx_x4_status4_r_deskew_mode_R_DESKEW_MODE_100G 4 7956 #define rx_x4_status4_r_deskew_mode_R_DESKEW_MODE_CL49 5 7957 #define rx_x4_status4_r_deskew_mode_R_DESKEW_MODE_CL91 6 7958 7959 /**************************************************************************** 7960 * Enums: rx_x4_status4_bs_dist_modes 7961 */ 7962 #define rx_x4_status4_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 7963 #define rx_x4_status4_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 7964 #define rx_x4_status4_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 7965 #define rx_x4_status4_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 7966 7967 /**************************************************************************** 7968 * Enums: rx_x4_status4_cl49_t_type 7969 */ 7970 #define rx_x4_status4_cl49_t_type_BAD_T_TYPE 15 7971 #define rx_x4_status4_cl49_t_type_T_TYPE_B0 11 7972 #define rx_x4_status4_cl49_t_type_T_TYPE_OB 10 7973 #define rx_x4_status4_cl49_t_type_T_TYPE_B1 9 7974 #define rx_x4_status4_cl49_t_type_T_TYPE_DB 8 7975 #define rx_x4_status4_cl49_t_type_T_TYPE_FC 7 7976 #define rx_x4_status4_cl49_t_type_T_TYPE_TB 6 7977 #define rx_x4_status4_cl49_t_type_T_TYPE_LI 5 7978 #define rx_x4_status4_cl49_t_type_T_TYPE_C 4 7979 #define rx_x4_status4_cl49_t_type_T_TYPE_S 3 7980 #define rx_x4_status4_cl49_t_type_T_TYPE_T 2 7981 #define rx_x4_status4_cl49_t_type_T_TYPE_D 1 7982 #define rx_x4_status4_cl49_t_type_T_TYPE_E 0 7983 7984 /**************************************************************************** 7985 * Enums: rx_x4_status4_cl49_txsm_states 7986 */ 7987 #define rx_x4_status4_cl49_txsm_states_TX_HIG_END 7 7988 #define rx_x4_status4_cl49_txsm_states_TX_HIG_START 6 7989 #define rx_x4_status4_cl49_txsm_states_TX_LI 5 7990 #define rx_x4_status4_cl49_txsm_states_TX_E 4 7991 #define rx_x4_status4_cl49_txsm_states_TX_T 3 7992 #define rx_x4_status4_cl49_txsm_states_TX_D 2 7993 #define rx_x4_status4_cl49_txsm_states_TX_C 1 7994 #define rx_x4_status4_cl49_txsm_states_TX_INIT 0 7995 7996 /**************************************************************************** 7997 * Enums: rx_x4_status4_cl49_ltxsm_states 7998 */ 7999 #define rx_x4_status4_cl49_ltxsm_states_TX_HIG_END 128 8000 #define rx_x4_status4_cl49_ltxsm_states_TX_HIG_START 64 8001 #define rx_x4_status4_cl49_ltxsm_states_TX_LI 32 8002 #define rx_x4_status4_cl49_ltxsm_states_TX_E 16 8003 #define rx_x4_status4_cl49_ltxsm_states_TX_T 8 8004 #define rx_x4_status4_cl49_ltxsm_states_TX_D 4 8005 #define rx_x4_status4_cl49_ltxsm_states_TX_C 2 8006 #define rx_x4_status4_cl49_ltxsm_states_TX_INIT 1 8007 8008 /**************************************************************************** 8009 * Enums: rx_x4_status4_burst_error_mode 8010 */ 8011 #define rx_x4_status4_burst_error_mode_BURST_ERROR_11_BITS 0 8012 #define rx_x4_status4_burst_error_mode_BURST_ERROR_16_BITS 1 8013 #define rx_x4_status4_burst_error_mode_BURST_ERROR_17_BITS 2 8014 #define rx_x4_status4_burst_error_mode_BURST_ERROR_18_BITS 3 8015 #define rx_x4_status4_burst_error_mode_BURST_ERROR_19_BITS 4 8016 #define rx_x4_status4_burst_error_mode_BURST_ERROR_20_BITS 5 8017 #define rx_x4_status4_burst_error_mode_BURST_ERROR_21_BITS 6 8018 #define rx_x4_status4_burst_error_mode_BURST_ERROR_22_BITS 7 8019 #define rx_x4_status4_burst_error_mode_BURST_ERROR_23_BITS 8 8020 #define rx_x4_status4_burst_error_mode_BURST_ERROR_24_BITS 9 8021 #define rx_x4_status4_burst_error_mode_BURST_ERROR_25_BITS 10 8022 #define rx_x4_status4_burst_error_mode_BURST_ERROR_26_BITS 11 8023 #define rx_x4_status4_burst_error_mode_BURST_ERROR_27_BITS 12 8024 #define rx_x4_status4_burst_error_mode_BURST_ERROR_28_BITS 13 8025 #define rx_x4_status4_burst_error_mode_BURST_ERROR_29_BITS 14 8026 #define rx_x4_status4_burst_error_mode_BURST_ERROR_30_BITS 15 8027 #define rx_x4_status4_burst_error_mode_BURST_ERROR_31_BITS 16 8028 #define rx_x4_status4_burst_error_mode_BURST_ERROR_32_BITS 17 8029 #define rx_x4_status4_burst_error_mode_BURST_ERROR_33_BITS 18 8030 #define rx_x4_status4_burst_error_mode_BURST_ERROR_34_BITS 19 8031 #define rx_x4_status4_burst_error_mode_BURST_ERROR_35_BITS 20 8032 #define rx_x4_status4_burst_error_mode_BURST_ERROR_36_BITS 21 8033 #define rx_x4_status4_burst_error_mode_BURST_ERROR_37_BITS 22 8034 #define rx_x4_status4_burst_error_mode_BURST_ERROR_38_BITS 23 8035 #define rx_x4_status4_burst_error_mode_BURST_ERROR_39_BITS 24 8036 #define rx_x4_status4_burst_error_mode_BURST_ERROR_40_BITS 25 8037 #define rx_x4_status4_burst_error_mode_BURST_ERROR_41_BITS 26 8038 8039 /**************************************************************************** 8040 * Enums: rx_x4_status4_bermon_state 8041 */ 8042 #define rx_x4_status4_bermon_state_HI_BER 4 8043 #define rx_x4_status4_bermon_state_GOOD_BER 3 8044 #define rx_x4_status4_bermon_state_BER_TEST_SH 2 8045 #define rx_x4_status4_bermon_state_START_TIMER 1 8046 #define rx_x4_status4_bermon_state_BER_MT_INIT 0 8047 8048 /**************************************************************************** 8049 * Enums: rx_x4_status4_rxsm_state_cl49 8050 */ 8051 #define rx_x4_status4_rxsm_state_cl49_RX_HIG_END 128 8052 #define rx_x4_status4_rxsm_state_cl49_RX_HIG_START 64 8053 #define rx_x4_status4_rxsm_state_cl49_RX_LI 32 8054 #define rx_x4_status4_rxsm_state_cl49_RX_E 16 8055 #define rx_x4_status4_rxsm_state_cl49_RX_T 8 8056 #define rx_x4_status4_rxsm_state_cl49_RX_D 4 8057 #define rx_x4_status4_rxsm_state_cl49_RX_C 2 8058 #define rx_x4_status4_rxsm_state_cl49_RX_INIT 1 8059 8060 /**************************************************************************** 8061 * Enums: rx_x4_status4_r_type 8062 */ 8063 #define rx_x4_status4_r_type_BAD_R_TYPE 15 8064 #define rx_x4_status4_r_type_R_TYPE_B0 11 8065 #define rx_x4_status4_r_type_R_TYPE_OB 10 8066 #define rx_x4_status4_r_type_R_TYPE_B1 9 8067 #define rx_x4_status4_r_type_R_TYPE_DB 8 8068 #define rx_x4_status4_r_type_R_TYPE_FC 7 8069 #define rx_x4_status4_r_type_R_TYPE_TB 6 8070 #define rx_x4_status4_r_type_R_TYPE_LI 5 8071 #define rx_x4_status4_r_type_R_TYPE_C 4 8072 #define rx_x4_status4_r_type_R_TYPE_S 3 8073 #define rx_x4_status4_r_type_R_TYPE_T 2 8074 #define rx_x4_status4_r_type_R_TYPE_D 1 8075 #define rx_x4_status4_r_type_R_TYPE_E 0 8076 8077 /**************************************************************************** 8078 * Enums: rx_x4_status4_am_lock_state 8079 */ 8080 #define rx_x4_status4_am_lock_state_INVALID_AM 512 8081 #define rx_x4_status4_am_lock_state_GOOD_AM 256 8082 #define rx_x4_status4_am_lock_state_COMP_AM 128 8083 #define rx_x4_status4_am_lock_state_TIMER_2 64 8084 #define rx_x4_status4_am_lock_state_AM_2_GOOD 32 8085 #define rx_x4_status4_am_lock_state_COMP_2ND 16 8086 #define rx_x4_status4_am_lock_state_TIMER_1 8 8087 #define rx_x4_status4_am_lock_state_FIND_1ST 4 8088 #define rx_x4_status4_am_lock_state_AM_RESET_CNT 2 8089 #define rx_x4_status4_am_lock_state_AM_LOCK_INIT 1 8090 8091 /**************************************************************************** 8092 * Enums: rx_x4_status4_msg_selector 8093 */ 8094 #define rx_x4_status4_msg_selector_RESERVED 0 8095 #define rx_x4_status4_msg_selector_VALUE_802p3 1 8096 #define rx_x4_status4_msg_selector_VALUE_802p9 2 8097 #define rx_x4_status4_msg_selector_VALUE_802p5 3 8098 #define rx_x4_status4_msg_selector_VALUE_1394 4 8099 8100 /**************************************************************************** 8101 * Enums: rx_x4_status4_synce_enum 8102 */ 8103 #define rx_x4_status4_synce_enum_SYNCE_NO_DIV 0 8104 #define rx_x4_status4_synce_enum_SYNCE_DIV_7 1 8105 #define rx_x4_status4_synce_enum_SYNCE_DIV_11 2 8106 8107 /**************************************************************************** 8108 * Enums: rx_x4_status4_synce_enum_stage0 8109 */ 8110 #define rx_x4_status4_synce_enum_stage0_SYNCE_NO_DIV 0 8111 #define rx_x4_status4_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 8112 #define rx_x4_status4_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 8113 8114 /**************************************************************************** 8115 * Enums: rx_x4_status4_cl91_sync_state 8116 */ 8117 #define rx_x4_status4_cl91_sync_state_FIND_1ST 0 8118 #define rx_x4_status4_cl91_sync_state_COUNT_NEXT 1 8119 #define rx_x4_status4_cl91_sync_state_COMP_2ND 2 8120 #define rx_x4_status4_cl91_sync_state_TWO_GOOD 3 8121 8122 /**************************************************************************** 8123 * Enums: rx_x4_status4_cl91_algn_state 8124 */ 8125 #define rx_x4_status4_cl91_algn_state_LOSS_OF_ALIGNMENT 0 8126 #define rx_x4_status4_cl91_algn_state_DESKEW 1 8127 #define rx_x4_status4_cl91_algn_state_DESKEW_FAIL 2 8128 #define rx_x4_status4_cl91_algn_state_ALIGN_ACQUIRED 3 8129 #define rx_x4_status4_cl91_algn_state_CW_GOOD 4 8130 #define rx_x4_status4_cl91_algn_state_CW_BAD 5 8131 #define rx_x4_status4_cl91_algn_state_THREE_BAD 6 8132 8133 /**************************************************************************** 8134 * Enums: rx_x4_status4_fec_sel 8135 */ 8136 #define rx_x4_status4_fec_sel_NO_FEC 0 8137 #define rx_x4_status4_fec_sel_FEC_CL74 1 8138 #define rx_x4_status4_fec_sel_FEC_CL91 2 8139 8140 /**************************************************************************** 8141 * Enums: rx_x4_status5_cl36TxEEEStates_l 8142 */ 8143 #define rx_x4_status5_cl36TxEEEStates_l_TX_REFRESH 8 8144 #define rx_x4_status5_cl36TxEEEStates_l_TX_QUIET 4 8145 #define rx_x4_status5_cl36TxEEEStates_l_TX_SLEEP 2 8146 #define rx_x4_status5_cl36TxEEEStates_l_TX_ACTIVE 1 8147 8148 /**************************************************************************** 8149 * Enums: rx_x4_status5_cl36TxEEEStates_c 8150 */ 8151 #define rx_x4_status5_cl36TxEEEStates_c_TX_REFRESH 3 8152 #define rx_x4_status5_cl36TxEEEStates_c_TX_QUIET 2 8153 #define rx_x4_status5_cl36TxEEEStates_c_TX_SLEEP 1 8154 #define rx_x4_status5_cl36TxEEEStates_c_TX_ACTIVE 0 8155 8156 /**************************************************************************** 8157 * Enums: rx_x4_status5_cl49TxEEEStates_l 8158 */ 8159 #define rx_x4_status5_cl49TxEEEStates_l_SCR_RESET_2 64 8160 #define rx_x4_status5_cl49TxEEEStates_l_SCR_RESET_1 32 8161 #define rx_x4_status5_cl49TxEEEStates_l_TX_WAKE 16 8162 #define rx_x4_status5_cl49TxEEEStates_l_TX_REFRESH 8 8163 #define rx_x4_status5_cl49TxEEEStates_l_TX_QUIET 4 8164 #define rx_x4_status5_cl49TxEEEStates_l_TX_SLEEP 2 8165 #define rx_x4_status5_cl49TxEEEStates_l_TX_ACTIVE 1 8166 8167 /**************************************************************************** 8168 * Enums: rx_x4_status5_fec_req_enum 8169 */ 8170 #define rx_x4_status5_fec_req_enum_FEC_not_supported 0 8171 #define rx_x4_status5_fec_req_enum_FEC_supported_but_not_requested 1 8172 #define rx_x4_status5_fec_req_enum_invalid_setting 2 8173 #define rx_x4_status5_fec_req_enum_FEC_supported_and_requested 3 8174 8175 /**************************************************************************** 8176 * Enums: rx_x4_status5_cl73_pause_enum 8177 */ 8178 #define rx_x4_status5_cl73_pause_enum_No_PAUSE_ability 0 8179 #define rx_x4_status5_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 8180 #define rx_x4_status5_cl73_pause_enum_Symmetric_PAUSE_ability 1 8181 #define rx_x4_status5_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 8182 8183 /**************************************************************************** 8184 * Enums: rx_x4_status5_cl49TxEEEStates_c 8185 */ 8186 #define rx_x4_status5_cl49TxEEEStates_c_SCR_RESET_2 6 8187 #define rx_x4_status5_cl49TxEEEStates_c_SCR_RESET_1 5 8188 #define rx_x4_status5_cl49TxEEEStates_c_TX_WAKE 4 8189 #define rx_x4_status5_cl49TxEEEStates_c_TX_REFRESH 3 8190 #define rx_x4_status5_cl49TxEEEStates_c_TX_QUIET 2 8191 #define rx_x4_status5_cl49TxEEEStates_c_TX_SLEEP 1 8192 #define rx_x4_status5_cl49TxEEEStates_c_TX_ACTIVE 0 8193 8194 /**************************************************************************** 8195 * Enums: rx_x4_status5_cl36RxEEEStates_l 8196 */ 8197 #define rx_x4_status5_cl36RxEEEStates_l_RX_LINK_FAIL 32 8198 #define rx_x4_status5_cl36RxEEEStates_l_RX_WTF 16 8199 #define rx_x4_status5_cl36RxEEEStates_l_RX_WAKE 8 8200 #define rx_x4_status5_cl36RxEEEStates_l_RX_QUIET 4 8201 #define rx_x4_status5_cl36RxEEEStates_l_RX_SLEEP 2 8202 #define rx_x4_status5_cl36RxEEEStates_l_RX_ACTIVE 1 8203 8204 /**************************************************************************** 8205 * Enums: rx_x4_status5_cl36RxEEEStates_c 8206 */ 8207 #define rx_x4_status5_cl36RxEEEStates_c_RX_LINK_FAIL 5 8208 #define rx_x4_status5_cl36RxEEEStates_c_RX_WTF 4 8209 #define rx_x4_status5_cl36RxEEEStates_c_RX_WAKE 3 8210 #define rx_x4_status5_cl36RxEEEStates_c_RX_QUIET 2 8211 #define rx_x4_status5_cl36RxEEEStates_c_RX_SLEEP 1 8212 #define rx_x4_status5_cl36RxEEEStates_c_RX_ACTIVE 0 8213 8214 /**************************************************************************** 8215 * Enums: rx_x4_status5_cl49RxEEEStates_l 8216 */ 8217 #define rx_x4_status5_cl49RxEEEStates_l_RX_LINK_FAIL 32 8218 #define rx_x4_status5_cl49RxEEEStates_l_RX_WTF 16 8219 #define rx_x4_status5_cl49RxEEEStates_l_RX_WAKE 8 8220 #define rx_x4_status5_cl49RxEEEStates_l_RX_QUIET 4 8221 #define rx_x4_status5_cl49RxEEEStates_l_RX_SLEEP 2 8222 #define rx_x4_status5_cl49RxEEEStates_l_RX_ACTIVE 1 8223 8224 /**************************************************************************** 8225 * Enums: rx_x4_status5_cl49RxEEEStates_c 8226 */ 8227 #define rx_x4_status5_cl49RxEEEStates_c_RX_LINK_FAIL 5 8228 #define rx_x4_status5_cl49RxEEEStates_c_RX_WTF 4 8229 #define rx_x4_status5_cl49RxEEEStates_c_RX_WAKE 3 8230 #define rx_x4_status5_cl49RxEEEStates_c_RX_QUIET 2 8231 #define rx_x4_status5_cl49RxEEEStates_c_RX_SLEEP 1 8232 #define rx_x4_status5_cl49RxEEEStates_c_RX_ACTIVE 0 8233 8234 /**************************************************************************** 8235 * Enums: rx_x4_status5_cl48TxEEEStates_l 8236 */ 8237 #define rx_x4_status5_cl48TxEEEStates_l_TX_REFRESH 8 8238 #define rx_x4_status5_cl48TxEEEStates_l_TX_QUIET 4 8239 #define rx_x4_status5_cl48TxEEEStates_l_TX_SLEEP 2 8240 #define rx_x4_status5_cl48TxEEEStates_l_TX_ACTIVE 1 8241 8242 /**************************************************************************** 8243 * Enums: rx_x4_status5_cl48TxEEEStates_c 8244 */ 8245 #define rx_x4_status5_cl48TxEEEStates_c_TX_REFRESH 3 8246 #define rx_x4_status5_cl48TxEEEStates_c_TX_QUIET 2 8247 #define rx_x4_status5_cl48TxEEEStates_c_TX_SLEEP 1 8248 #define rx_x4_status5_cl48TxEEEStates_c_TX_ACTIVE 0 8249 8250 /**************************************************************************** 8251 * Enums: rx_x4_status5_cl48RxEEEStates_l 8252 */ 8253 #define rx_x4_status5_cl48RxEEEStates_l_RX_LINK_FAIL 32 8254 #define rx_x4_status5_cl48RxEEEStates_l_RX_WAKE 16 8255 #define rx_x4_status5_cl48RxEEEStates_l_RX_QUIET 8 8256 #define rx_x4_status5_cl48RxEEEStates_l_RX_DEACT 4 8257 #define rx_x4_status5_cl48RxEEEStates_l_RX_SLEEP 2 8258 #define rx_x4_status5_cl48RxEEEStates_l_RX_ACTIVE 1 8259 8260 /**************************************************************************** 8261 * Enums: rx_x4_status5_cl48RxEEEStates_c 8262 */ 8263 #define rx_x4_status5_cl48RxEEEStates_c_RX_LINK_FAIL 5 8264 #define rx_x4_status5_cl48RxEEEStates_c_RX_WAKE 4 8265 #define rx_x4_status5_cl48RxEEEStates_c_RX_QUIET 3 8266 #define rx_x4_status5_cl48RxEEEStates_c_RX_DEACT 2 8267 #define rx_x4_status5_cl48RxEEEStates_c_RX_SLEEP 1 8268 #define rx_x4_status5_cl48RxEEEStates_c_RX_ACTIVE 0 8269 8270 /**************************************************************************** 8271 * Enums: rx_x4_status5_IQP_Options 8272 */ 8273 #define rx_x4_status5_IQP_Options_i50uA 0 8274 #define rx_x4_status5_IQP_Options_i100uA 1 8275 #define rx_x4_status5_IQP_Options_i150uA 2 8276 #define rx_x4_status5_IQP_Options_i200uA 3 8277 #define rx_x4_status5_IQP_Options_i250uA 4 8278 #define rx_x4_status5_IQP_Options_i300uA 5 8279 #define rx_x4_status5_IQP_Options_i350uA 6 8280 #define rx_x4_status5_IQP_Options_i400uA 7 8281 #define rx_x4_status5_IQP_Options_i450uA 8 8282 #define rx_x4_status5_IQP_Options_i500uA 9 8283 #define rx_x4_status5_IQP_Options_i550uA 10 8284 #define rx_x4_status5_IQP_Options_i600uA 11 8285 #define rx_x4_status5_IQP_Options_i650uA 12 8286 #define rx_x4_status5_IQP_Options_i700uA 13 8287 #define rx_x4_status5_IQP_Options_i750uA 14 8288 #define rx_x4_status5_IQP_Options_i800uA 15 8289 8290 /**************************************************************************** 8291 * Enums: rx_x4_status5_IDriver_Options 8292 */ 8293 #define rx_x4_status5_IDriver_Options_v680mV 0 8294 #define rx_x4_status5_IDriver_Options_v730mV 1 8295 #define rx_x4_status5_IDriver_Options_v780mV 2 8296 #define rx_x4_status5_IDriver_Options_v830mV 3 8297 #define rx_x4_status5_IDriver_Options_v880mV 4 8298 #define rx_x4_status5_IDriver_Options_v930mV 5 8299 #define rx_x4_status5_IDriver_Options_v980mV 6 8300 #define rx_x4_status5_IDriver_Options_v1010mV 7 8301 #define rx_x4_status5_IDriver_Options_v1040mV 8 8302 #define rx_x4_status5_IDriver_Options_v1060mV 9 8303 #define rx_x4_status5_IDriver_Options_v1070mV 10 8304 #define rx_x4_status5_IDriver_Options_v1080mV 11 8305 #define rx_x4_status5_IDriver_Options_v1085mV 12 8306 #define rx_x4_status5_IDriver_Options_v1090mV 13 8307 #define rx_x4_status5_IDriver_Options_v1095mV 14 8308 #define rx_x4_status5_IDriver_Options_v1100mV 15 8309 8310 /**************************************************************************** 8311 * Enums: rx_x4_status5_operationModes 8312 */ 8313 #define rx_x4_status5_operationModes_XGXS 0 8314 #define rx_x4_status5_operationModes_XGXG_nCC 1 8315 #define rx_x4_status5_operationModes_Indlane_OS8 4 8316 #define rx_x4_status5_operationModes_IndLane_OS5 5 8317 #define rx_x4_status5_operationModes_PCI 7 8318 #define rx_x4_status5_operationModes_XGXS_nLQ 8 8319 #define rx_x4_status5_operationModes_XGXS_nLQnCC 9 8320 #define rx_x4_status5_operationModes_PBypass 10 8321 #define rx_x4_status5_operationModes_PBypass_nDSK 11 8322 #define rx_x4_status5_operationModes_ComboCoreMode 12 8323 #define rx_x4_status5_operationModes_Clocks_off 15 8324 8325 /**************************************************************************** 8326 * Enums: rx_x4_status5_actualSpeeds 8327 */ 8328 #define rx_x4_status5_actualSpeeds_dr_10M 0 8329 #define rx_x4_status5_actualSpeeds_dr_100M 1 8330 #define rx_x4_status5_actualSpeeds_dr_1G 2 8331 #define rx_x4_status5_actualSpeeds_dr_2p5G 3 8332 #define rx_x4_status5_actualSpeeds_dr_5G_X4 4 8333 #define rx_x4_status5_actualSpeeds_dr_6G_X4 5 8334 #define rx_x4_status5_actualSpeeds_dr_10G_HiG 6 8335 #define rx_x4_status5_actualSpeeds_dr_10G_CX4 7 8336 #define rx_x4_status5_actualSpeeds_dr_12G_HiG 8 8337 #define rx_x4_status5_actualSpeeds_dr_12p5G_X4 9 8338 #define rx_x4_status5_actualSpeeds_dr_13G_X4 10 8339 #define rx_x4_status5_actualSpeeds_dr_15G_X4 11 8340 #define rx_x4_status5_actualSpeeds_dr_16G_X4 12 8341 #define rx_x4_status5_actualSpeeds_dr_1G_KX 13 8342 #define rx_x4_status5_actualSpeeds_dr_10G_KX4 14 8343 #define rx_x4_status5_actualSpeeds_dr_10G_KR 15 8344 #define rx_x4_status5_actualSpeeds_dr_5G 16 8345 #define rx_x4_status5_actualSpeeds_dr_6p4G 17 8346 #define rx_x4_status5_actualSpeeds_dr_20G_X4 18 8347 #define rx_x4_status5_actualSpeeds_dr_21G_X4 19 8348 #define rx_x4_status5_actualSpeeds_dr_25G_X4 20 8349 #define rx_x4_status5_actualSpeeds_dr_10G_HiG_DXGXS 21 8350 #define rx_x4_status5_actualSpeeds_dr_10G_DXGXS 22 8351 #define rx_x4_status5_actualSpeeds_dr_10p5G_HiG_DXGXS 23 8352 #define rx_x4_status5_actualSpeeds_dr_10p5G_DXGXS 24 8353 #define rx_x4_status5_actualSpeeds_dr_12p773G_HiG_DXGXS 25 8354 #define rx_x4_status5_actualSpeeds_dr_12p773G_DXGXS 26 8355 #define rx_x4_status5_actualSpeeds_dr_10G_XFI 27 8356 #define rx_x4_status5_actualSpeeds_dr_40G 28 8357 #define rx_x4_status5_actualSpeeds_dr_20G_HiG_DXGXS 29 8358 #define rx_x4_status5_actualSpeeds_dr_20G_DXGXS 30 8359 #define rx_x4_status5_actualSpeeds_dr_10G_SFI 31 8360 #define rx_x4_status5_actualSpeeds_dr_31p5G 32 8361 #define rx_x4_status5_actualSpeeds_dr_32p7G 33 8362 #define rx_x4_status5_actualSpeeds_dr_20G_SCR 34 8363 #define rx_x4_status5_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 8364 #define rx_x4_status5_actualSpeeds_dr_10G_DXGXS_SCR 36 8365 #define rx_x4_status5_actualSpeeds_dr_12G_R2 37 8366 #define rx_x4_status5_actualSpeeds_dr_10G_X2 38 8367 #define rx_x4_status5_actualSpeeds_dr_40G_KR4 39 8368 #define rx_x4_status5_actualSpeeds_dr_40G_CR4 40 8369 #define rx_x4_status5_actualSpeeds_dr_100G_CR10 41 8370 #define rx_x4_status5_actualSpeeds_dr_15p75G_DXGXS 44 8371 #define rx_x4_status5_actualSpeeds_dr_20G_KR2 57 8372 #define rx_x4_status5_actualSpeeds_dr_20G_CR2 58 8373 8374 /**************************************************************************** 8375 * Enums: rx_x4_status5_actualSpeedsMisc1 8376 */ 8377 #define rx_x4_status5_actualSpeedsMisc1_dr_2500BRCM_X1 16 8378 #define rx_x4_status5_actualSpeedsMisc1_dr_5000BRCM_X4 17 8379 #define rx_x4_status5_actualSpeedsMisc1_dr_6000BRCM_X4 18 8380 #define rx_x4_status5_actualSpeedsMisc1_dr_10GHiGig_X4 19 8381 #define rx_x4_status5_actualSpeedsMisc1_dr_10GBASE_CX4 20 8382 #define rx_x4_status5_actualSpeedsMisc1_dr_12GHiGig_X4 21 8383 #define rx_x4_status5_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 8384 #define rx_x4_status5_actualSpeedsMisc1_dr_13GHiGig_X4 23 8385 #define rx_x4_status5_actualSpeedsMisc1_dr_15GHiGig_X4 24 8386 #define rx_x4_status5_actualSpeedsMisc1_dr_16GHiGig_X4 25 8387 #define rx_x4_status5_actualSpeedsMisc1_dr_5000BRCM_X1 26 8388 #define rx_x4_status5_actualSpeedsMisc1_dr_6363BRCM_X1 27 8389 #define rx_x4_status5_actualSpeedsMisc1_dr_20GHiGig_X4 28 8390 #define rx_x4_status5_actualSpeedsMisc1_dr_21GHiGig_X4 29 8391 #define rx_x4_status5_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 8392 #define rx_x4_status5_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 8393 8394 /**************************************************************************** 8395 * Enums: rx_x4_status5_IndLaneModes 8396 */ 8397 #define rx_x4_status5_IndLaneModes_SWSDR_div2 0 8398 #define rx_x4_status5_IndLaneModes_SWSDR_div1 1 8399 #define rx_x4_status5_IndLaneModes_DWSDR_div2 2 8400 #define rx_x4_status5_IndLaneModes_DWSDR_div1 3 8401 8402 /**************************************************************************** 8403 * Enums: rx_x4_status5_prbsSelect 8404 */ 8405 #define rx_x4_status5_prbsSelect_prbs7 0 8406 #define rx_x4_status5_prbsSelect_prbs15 1 8407 #define rx_x4_status5_prbsSelect_prbs23 2 8408 #define rx_x4_status5_prbsSelect_prbs31 3 8409 8410 /**************************************************************************** 8411 * Enums: rx_x4_status5_vcoDivider 8412 */ 8413 #define rx_x4_status5_vcoDivider_div32 0 8414 #define rx_x4_status5_vcoDivider_div36 1 8415 #define rx_x4_status5_vcoDivider_div40 2 8416 #define rx_x4_status5_vcoDivider_div42 3 8417 #define rx_x4_status5_vcoDivider_div48 4 8418 #define rx_x4_status5_vcoDivider_div50 5 8419 #define rx_x4_status5_vcoDivider_div52 6 8420 #define rx_x4_status5_vcoDivider_div54 7 8421 #define rx_x4_status5_vcoDivider_div60 8 8422 #define rx_x4_status5_vcoDivider_div64 9 8423 #define rx_x4_status5_vcoDivider_div66 10 8424 #define rx_x4_status5_vcoDivider_div68 11 8425 #define rx_x4_status5_vcoDivider_div70 12 8426 #define rx_x4_status5_vcoDivider_div80 13 8427 #define rx_x4_status5_vcoDivider_div92 14 8428 #define rx_x4_status5_vcoDivider_div100 15 8429 8430 /**************************************************************************** 8431 * Enums: rx_x4_status5_refClkSelect 8432 */ 8433 #define rx_x4_status5_refClkSelect_clk_25MHz 0 8434 #define rx_x4_status5_refClkSelect_clk_100MHz 1 8435 #define rx_x4_status5_refClkSelect_clk_125MHz 2 8436 #define rx_x4_status5_refClkSelect_clk_156p25MHz 3 8437 #define rx_x4_status5_refClkSelect_clk_187p5MHz 4 8438 #define rx_x4_status5_refClkSelect_clk_161p25Mhz 5 8439 #define rx_x4_status5_refClkSelect_clk_50Mhz 6 8440 #define rx_x4_status5_refClkSelect_clk_106p25Mhz 7 8441 8442 /**************************************************************************** 8443 * Enums: rx_x4_status5_aerMMDdevTypeSelect 8444 */ 8445 #define rx_x4_status5_aerMMDdevTypeSelect_combo_core 0 8446 #define rx_x4_status5_aerMMDdevTypeSelect_PMA_PMD 1 8447 #define rx_x4_status5_aerMMDdevTypeSelect_PCS 3 8448 #define rx_x4_status5_aerMMDdevTypeSelect_PHY 4 8449 #define rx_x4_status5_aerMMDdevTypeSelect_DTE 5 8450 #define rx_x4_status5_aerMMDdevTypeSelect_CL73_AN 7 8451 8452 /**************************************************************************** 8453 * Enums: rx_x4_status5_aerMMDportSelect 8454 */ 8455 #define rx_x4_status5_aerMMDportSelect_ln0 0 8456 #define rx_x4_status5_aerMMDportSelect_ln1 1 8457 #define rx_x4_status5_aerMMDportSelect_ln2 2 8458 #define rx_x4_status5_aerMMDportSelect_ln3 3 8459 #define rx_x4_status5_aerMMDportSelect_BCST_ln0_1_2_3 511 8460 #define rx_x4_status5_aerMMDportSelect_BCST_ln0_1 512 8461 #define rx_x4_status5_aerMMDportSelect_BCST_ln2_3 513 8462 8463 /**************************************************************************** 8464 * Enums: rx_x4_status5_firmwareModeSelect 8465 */ 8466 #define rx_x4_status5_firmwareModeSelect_DEFAULT 0 8467 #define rx_x4_status5_firmwareModeSelect_SFP_OPT_LR 1 8468 #define rx_x4_status5_firmwareModeSelect_SFP_DAC 2 8469 #define rx_x4_status5_firmwareModeSelect_XLAUI 3 8470 #define rx_x4_status5_firmwareModeSelect_LONG_CH_6G 4 8471 8472 /**************************************************************************** 8473 * Enums: rx_x4_status5_tempIdxSelect 8474 */ 8475 #define rx_x4_status5_tempIdxSelect_LTE__22p9C 15 8476 #define rx_x4_status5_tempIdxSelect_LTE__12p6C 14 8477 #define rx_x4_status5_tempIdxSelect_LTE__3p0C 13 8478 #define rx_x4_status5_tempIdxSelect_LTE_6p7C 12 8479 #define rx_x4_status5_tempIdxSelect_LTE_16p4C 11 8480 #define rx_x4_status5_tempIdxSelect_LTE_26p6C 10 8481 #define rx_x4_status5_tempIdxSelect_LTE_36p3C 9 8482 #define rx_x4_status5_tempIdxSelect_LTE_46p0C 8 8483 #define rx_x4_status5_tempIdxSelect_LTE_56p2C 7 8484 #define rx_x4_status5_tempIdxSelect_LTE_65p9C 6 8485 #define rx_x4_status5_tempIdxSelect_LTE_75p6C 5 8486 #define rx_x4_status5_tempIdxSelect_LTE_85p3C 4 8487 #define rx_x4_status5_tempIdxSelect_LTE_95p5C 3 8488 #define rx_x4_status5_tempIdxSelect_LTE_105p2C 2 8489 #define rx_x4_status5_tempIdxSelect_LTE_114p9C 1 8490 #define rx_x4_status5_tempIdxSelect_LTE_125p1C 0 8491 8492 /**************************************************************************** 8493 * Enums: rx_x4_status5_port_mode 8494 */ 8495 #define rx_x4_status5_port_mode_QUAD_PORT 0 8496 #define rx_x4_status5_port_mode_TRI_1_PORT 1 8497 #define rx_x4_status5_port_mode_TRI_2_PORT 2 8498 #define rx_x4_status5_port_mode_DUAL_PORT 3 8499 #define rx_x4_status5_port_mode_SINGLE_PORT 4 8500 8501 /**************************************************************************** 8502 * Enums: rx_x4_status5_rev_letter_enum 8503 */ 8504 #define rx_x4_status5_rev_letter_enum_REV_A 0 8505 #define rx_x4_status5_rev_letter_enum_REV_B 1 8506 #define rx_x4_status5_rev_letter_enum_REV_C 2 8507 #define rx_x4_status5_rev_letter_enum_REV_D 3 8508 8509 /**************************************************************************** 8510 * Enums: rx_x4_status5_rev_number_enum 8511 */ 8512 #define rx_x4_status5_rev_number_enum_REV_0 0 8513 #define rx_x4_status5_rev_number_enum_REV_1 1 8514 #define rx_x4_status5_rev_number_enum_REV_2 2 8515 #define rx_x4_status5_rev_number_enum_REV_3 3 8516 #define rx_x4_status5_rev_number_enum_REV_4 4 8517 #define rx_x4_status5_rev_number_enum_REV_5 5 8518 #define rx_x4_status5_rev_number_enum_REV_6 6 8519 #define rx_x4_status5_rev_number_enum_REV_7 7 8520 8521 /**************************************************************************** 8522 * Enums: rx_x4_status5_bonding_enum 8523 */ 8524 #define rx_x4_status5_bonding_enum_WIRE_BOND 0 8525 #define rx_x4_status5_bonding_enum_FLIP_CHIP 1 8526 8527 /**************************************************************************** 8528 * Enums: rx_x4_status5_tech_process 8529 */ 8530 #define rx_x4_status5_tech_process_PROCESS_90NM 0 8531 #define rx_x4_status5_tech_process_PROCESS_65NM 1 8532 #define rx_x4_status5_tech_process_PROCESS_40NM 2 8533 #define rx_x4_status5_tech_process_PROCESS_28NM 3 8534 8535 /**************************************************************************** 8536 * Enums: rx_x4_status5_model_num 8537 */ 8538 #define rx_x4_status5_model_num_SERDES_CL73 0 8539 #define rx_x4_status5_model_num_XGXS_16G 1 8540 #define rx_x4_status5_model_num_HYPERCORE 2 8541 #define rx_x4_status5_model_num_HYPERLITE 3 8542 #define rx_x4_status5_model_num_PCIE_G2_PIPE 4 8543 #define rx_x4_status5_model_num_SERDES_1p25GBd 5 8544 #define rx_x4_status5_model_num_SATA2 6 8545 #define rx_x4_status5_model_num_QSGMII 7 8546 #define rx_x4_status5_model_num_XGXS10G 8 8547 #define rx_x4_status5_model_num_WARPCORE 9 8548 #define rx_x4_status5_model_num_XFICORE 10 8549 #define rx_x4_status5_model_num_RXFI 11 8550 #define rx_x4_status5_model_num_WARPLITE 12 8551 #define rx_x4_status5_model_num_PENTACORE 13 8552 #define rx_x4_status5_model_num_ESM 14 8553 #define rx_x4_status5_model_num_QUAD_SGMII 15 8554 #define rx_x4_status5_model_num_WARPCORE_3 16 8555 #define rx_x4_status5_model_num_TSC 17 8556 #define rx_x4_status5_model_num_TSC4E 18 8557 #define rx_x4_status5_model_num_TSC12E 19 8558 #define rx_x4_status5_model_num_TSC4F 20 8559 #define rx_x4_status5_model_num_XGXS_CL73_90NM 29 8560 #define rx_x4_status5_model_num_SERDES_CL73_90NM 30 8561 #define rx_x4_status5_model_num_WARPCORE3 32 8562 #define rx_x4_status5_model_num_WARPCORE4_TSC 33 8563 #define rx_x4_status5_model_num_RXAUI 34 8564 8565 /**************************************************************************** 8566 * Enums: rx_x4_status5_payload 8567 */ 8568 #define rx_x4_status5_payload_REPEAT_2_BYTES 0 8569 #define rx_x4_status5_payload_RAMPING 1 8570 #define rx_x4_status5_payload_CL48_CRPAT 2 8571 #define rx_x4_status5_payload_CL48_CJPAT 3 8572 #define rx_x4_status5_payload_CL36_LONG_CRPAT 4 8573 #define rx_x4_status5_payload_CL36_SHORT_CRPAT 5 8574 8575 /**************************************************************************** 8576 * Enums: rx_x4_status5_sc 8577 */ 8578 #define rx_x4_status5_sc_S_10G_CR1 0 8579 #define rx_x4_status5_sc_S_10G_KR1 1 8580 #define rx_x4_status5_sc_S_10G_X1 2 8581 #define rx_x4_status5_sc_S_10G_HG2_CR1 4 8582 #define rx_x4_status5_sc_S_10G_HG2_KR1 5 8583 #define rx_x4_status5_sc_S_10G_HG2_X1 6 8584 #define rx_x4_status5_sc_S_20G_CR1 8 8585 #define rx_x4_status5_sc_S_20G_KR1 9 8586 #define rx_x4_status5_sc_S_20G_X1 10 8587 #define rx_x4_status5_sc_S_20G_HG2_CR1 12 8588 #define rx_x4_status5_sc_S_20G_HG2_KR1 13 8589 #define rx_x4_status5_sc_S_20G_HG2_X1 14 8590 #define rx_x4_status5_sc_S_25G_CR1 16 8591 #define rx_x4_status5_sc_S_25G_KR1 17 8592 #define rx_x4_status5_sc_S_25G_X1 18 8593 #define rx_x4_status5_sc_S_25G_HG2_CR1 20 8594 #define rx_x4_status5_sc_S_25G_HG2_KR1 21 8595 #define rx_x4_status5_sc_S_25G_HG2_X1 22 8596 #define rx_x4_status5_sc_S_20G_CR2 24 8597 #define rx_x4_status5_sc_S_20G_KR2 25 8598 #define rx_x4_status5_sc_S_20G_X2 26 8599 #define rx_x4_status5_sc_S_20G_HG2_CR2 28 8600 #define rx_x4_status5_sc_S_20G_HG2_KR2 29 8601 #define rx_x4_status5_sc_S_20G_HG2_X2 30 8602 #define rx_x4_status5_sc_S_40G_CR2 32 8603 #define rx_x4_status5_sc_S_40G_KR2 33 8604 #define rx_x4_status5_sc_S_40G_X2 34 8605 #define rx_x4_status5_sc_S_40G_HG2_CR2 36 8606 #define rx_x4_status5_sc_S_40G_HG2_KR2 37 8607 #define rx_x4_status5_sc_S_40G_HG2_X2 38 8608 #define rx_x4_status5_sc_S_40G_CR4 40 8609 #define rx_x4_status5_sc_S_40G_KR4 41 8610 #define rx_x4_status5_sc_S_40G_X4 42 8611 #define rx_x4_status5_sc_S_40G_HG2_CR4 44 8612 #define rx_x4_status5_sc_S_40G_HG2_KR4 45 8613 #define rx_x4_status5_sc_S_40G_HG2_X4 46 8614 #define rx_x4_status5_sc_S_50G_CR2 48 8615 #define rx_x4_status5_sc_S_50G_KR2 49 8616 #define rx_x4_status5_sc_S_50G_X2 50 8617 #define rx_x4_status5_sc_S_50G_HG2_CR2 52 8618 #define rx_x4_status5_sc_S_50G_HG2_KR2 53 8619 #define rx_x4_status5_sc_S_50G_HG2_X2 54 8620 #define rx_x4_status5_sc_S_50G_CR4 56 8621 #define rx_x4_status5_sc_S_50G_KR4 57 8622 #define rx_x4_status5_sc_S_50G_X4 58 8623 #define rx_x4_status5_sc_S_50G_HG2_CR4 60 8624 #define rx_x4_status5_sc_S_50G_HG2_KR4 61 8625 #define rx_x4_status5_sc_S_50G_HG2_X4 62 8626 #define rx_x4_status5_sc_S_100G_CR4 64 8627 #define rx_x4_status5_sc_S_100G_KR4 65 8628 #define rx_x4_status5_sc_S_100G_X4 66 8629 #define rx_x4_status5_sc_S_100G_HG2_CR4 68 8630 #define rx_x4_status5_sc_S_100G_HG2_KR4 69 8631 #define rx_x4_status5_sc_S_100G_HG2_X4 70 8632 #define rx_x4_status5_sc_S_CL73_20GVCO 72 8633 #define rx_x4_status5_sc_S_CL73_25GVCO 80 8634 #define rx_x4_status5_sc_S_CL36_20GVCO 88 8635 #define rx_x4_status5_sc_S_CL36_25GVCO 96 8636 8637 /**************************************************************************** 8638 * Enums: rx_x4_status5_t_fifo_modes 8639 */ 8640 #define rx_x4_status5_t_fifo_modes_T_FIFO_MODE_BYPASS 0 8641 #define rx_x4_status5_t_fifo_modes_T_FIFO_MODE_40G 1 8642 #define rx_x4_status5_t_fifo_modes_T_FIFO_MODE_100G 2 8643 #define rx_x4_status5_t_fifo_modes_T_FIFO_MODE_20G 3 8644 8645 /**************************************************************************** 8646 * Enums: rx_x4_status5_t_enc_modes 8647 */ 8648 #define rx_x4_status5_t_enc_modes_T_ENC_MODE_BYPASS 0 8649 #define rx_x4_status5_t_enc_modes_T_ENC_MODE_CL49 1 8650 #define rx_x4_status5_t_enc_modes_T_ENC_MODE_CL82 2 8651 8652 /**************************************************************************** 8653 * Enums: rx_x4_status5_btmx_mode 8654 */ 8655 #define rx_x4_status5_btmx_mode_BS_BTMX_MODE_1to1 0 8656 #define rx_x4_status5_btmx_mode_BS_BTMX_MODE_2to1 1 8657 #define rx_x4_status5_btmx_mode_BS_BTMX_MODE_5to1 2 8658 8659 /**************************************************************************** 8660 * Enums: rx_x4_status5_t_type_cl82 8661 */ 8662 #define rx_x4_status5_t_type_cl82_T_TYPE_B1 5 8663 #define rx_x4_status5_t_type_cl82_T_TYPE_C 4 8664 #define rx_x4_status5_t_type_cl82_T_TYPE_S 3 8665 #define rx_x4_status5_t_type_cl82_T_TYPE_T 2 8666 #define rx_x4_status5_t_type_cl82_T_TYPE_D 1 8667 #define rx_x4_status5_t_type_cl82_T_TYPE_E 0 8668 8669 /**************************************************************************** 8670 * Enums: rx_x4_status5_txsm_state_cl82 8671 */ 8672 #define rx_x4_status5_txsm_state_cl82_TX_HIG_END 6 8673 #define rx_x4_status5_txsm_state_cl82_TX_HIG_START 5 8674 #define rx_x4_status5_txsm_state_cl82_TX_E 4 8675 #define rx_x4_status5_txsm_state_cl82_TX_T 3 8676 #define rx_x4_status5_txsm_state_cl82_TX_D 2 8677 #define rx_x4_status5_txsm_state_cl82_TX_C 1 8678 #define rx_x4_status5_txsm_state_cl82_TX_INIT 0 8679 8680 /**************************************************************************** 8681 * Enums: rx_x4_status5_ltxsm_state_cl82 8682 */ 8683 #define rx_x4_status5_ltxsm_state_cl82_TX_HIG_END 64 8684 #define rx_x4_status5_ltxsm_state_cl82_TX_HIG_START 32 8685 #define rx_x4_status5_ltxsm_state_cl82_TX_E 16 8686 #define rx_x4_status5_ltxsm_state_cl82_TX_T 8 8687 #define rx_x4_status5_ltxsm_state_cl82_TX_D 4 8688 #define rx_x4_status5_ltxsm_state_cl82_TX_C 2 8689 #define rx_x4_status5_ltxsm_state_cl82_TX_INIT 1 8690 8691 /**************************************************************************** 8692 * Enums: rx_x4_status5_r_type_coded_cl82 8693 */ 8694 #define rx_x4_status5_r_type_coded_cl82_R_TYPE_B1 32 8695 #define rx_x4_status5_r_type_coded_cl82_R_TYPE_C 16 8696 #define rx_x4_status5_r_type_coded_cl82_R_TYPE_S 8 8697 #define rx_x4_status5_r_type_coded_cl82_R_TYPE_T 4 8698 #define rx_x4_status5_r_type_coded_cl82_R_TYPE_D 2 8699 #define rx_x4_status5_r_type_coded_cl82_R_TYPE_E 1 8700 8701 /**************************************************************************** 8702 * Enums: rx_x4_status5_rxsm_state_cl82 8703 */ 8704 #define rx_x4_status5_rxsm_state_cl82_RX_HIG_END 64 8705 #define rx_x4_status5_rxsm_state_cl82_RX_HIG_START 32 8706 #define rx_x4_status5_rxsm_state_cl82_RX_E 16 8707 #define rx_x4_status5_rxsm_state_cl82_RX_T 8 8708 #define rx_x4_status5_rxsm_state_cl82_RX_D 4 8709 #define rx_x4_status5_rxsm_state_cl82_RX_C 2 8710 #define rx_x4_status5_rxsm_state_cl82_RX_INIT 1 8711 8712 /**************************************************************************** 8713 * Enums: rx_x4_status5_deskew_state 8714 */ 8715 #define rx_x4_status5_deskew_state_ALIGN_ACQUIRED 2 8716 #define rx_x4_status5_deskew_state_LOSS_OF_ALIGNMENT 1 8717 8718 /**************************************************************************** 8719 * Enums: rx_x4_status5_os_mode_enum 8720 */ 8721 #define rx_x4_status5_os_mode_enum_OS_MODE_1 0 8722 #define rx_x4_status5_os_mode_enum_OS_MODE_2 1 8723 #define rx_x4_status5_os_mode_enum_OS_MODE_4 2 8724 #define rx_x4_status5_os_mode_enum_OS_MODE_16p5 8 8725 #define rx_x4_status5_os_mode_enum_OS_MODE_20p625 12 8726 8727 /**************************************************************************** 8728 * Enums: rx_x4_status5_scr_modes 8729 */ 8730 #define rx_x4_status5_scr_modes_T_SCR_MODE_BYPASS 0 8731 #define rx_x4_status5_scr_modes_T_SCR_MODE_CL49 1 8732 #define rx_x4_status5_scr_modes_T_SCR_MODE_40G_2_LANE 2 8733 #define rx_x4_status5_scr_modes_T_SCR_MODE_100G 3 8734 #define rx_x4_status5_scr_modes_T_SCR_MODE_20G 4 8735 #define rx_x4_status5_scr_modes_T_SCR_MODE_40G_4_LANE 5 8736 8737 /**************************************************************************** 8738 * Enums: rx_x4_status5_descr_modes 8739 */ 8740 #define rx_x4_status5_descr_modes_R_DESCR_MODE_BYPASS 0 8741 #define rx_x4_status5_descr_modes_R_DESCR_MODE_CL49 1 8742 #define rx_x4_status5_descr_modes_R_DESCR_MODE_CL82 2 8743 8744 /**************************************************************************** 8745 * Enums: rx_x4_status5_r_dec_tl_mode 8746 */ 8747 #define rx_x4_status5_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 8748 #define rx_x4_status5_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 8749 #define rx_x4_status5_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 8750 8751 /**************************************************************************** 8752 * Enums: rx_x4_status5_r_dec_fsm_mode 8753 */ 8754 #define rx_x4_status5_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 8755 #define rx_x4_status5_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 8756 #define rx_x4_status5_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 8757 8758 /**************************************************************************** 8759 * Enums: rx_x4_status5_r_deskew_mode 8760 */ 8761 #define rx_x4_status5_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 8762 #define rx_x4_status5_r_deskew_mode_R_DESKEW_MODE_20G 1 8763 #define rx_x4_status5_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 8764 #define rx_x4_status5_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 8765 #define rx_x4_status5_r_deskew_mode_R_DESKEW_MODE_100G 4 8766 #define rx_x4_status5_r_deskew_mode_R_DESKEW_MODE_CL49 5 8767 #define rx_x4_status5_r_deskew_mode_R_DESKEW_MODE_CL91 6 8768 8769 /**************************************************************************** 8770 * Enums: rx_x4_status5_bs_dist_modes 8771 */ 8772 #define rx_x4_status5_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 8773 #define rx_x4_status5_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 8774 #define rx_x4_status5_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 8775 #define rx_x4_status5_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 8776 8777 /**************************************************************************** 8778 * Enums: rx_x4_status5_cl49_t_type 8779 */ 8780 #define rx_x4_status5_cl49_t_type_BAD_T_TYPE 15 8781 #define rx_x4_status5_cl49_t_type_T_TYPE_B0 11 8782 #define rx_x4_status5_cl49_t_type_T_TYPE_OB 10 8783 #define rx_x4_status5_cl49_t_type_T_TYPE_B1 9 8784 #define rx_x4_status5_cl49_t_type_T_TYPE_DB 8 8785 #define rx_x4_status5_cl49_t_type_T_TYPE_FC 7 8786 #define rx_x4_status5_cl49_t_type_T_TYPE_TB 6 8787 #define rx_x4_status5_cl49_t_type_T_TYPE_LI 5 8788 #define rx_x4_status5_cl49_t_type_T_TYPE_C 4 8789 #define rx_x4_status5_cl49_t_type_T_TYPE_S 3 8790 #define rx_x4_status5_cl49_t_type_T_TYPE_T 2 8791 #define rx_x4_status5_cl49_t_type_T_TYPE_D 1 8792 #define rx_x4_status5_cl49_t_type_T_TYPE_E 0 8793 8794 /**************************************************************************** 8795 * Enums: rx_x4_status5_cl49_txsm_states 8796 */ 8797 #define rx_x4_status5_cl49_txsm_states_TX_HIG_END 7 8798 #define rx_x4_status5_cl49_txsm_states_TX_HIG_START 6 8799 #define rx_x4_status5_cl49_txsm_states_TX_LI 5 8800 #define rx_x4_status5_cl49_txsm_states_TX_E 4 8801 #define rx_x4_status5_cl49_txsm_states_TX_T 3 8802 #define rx_x4_status5_cl49_txsm_states_TX_D 2 8803 #define rx_x4_status5_cl49_txsm_states_TX_C 1 8804 #define rx_x4_status5_cl49_txsm_states_TX_INIT 0 8805 8806 /**************************************************************************** 8807 * Enums: rx_x4_status5_cl49_ltxsm_states 8808 */ 8809 #define rx_x4_status5_cl49_ltxsm_states_TX_HIG_END 128 8810 #define rx_x4_status5_cl49_ltxsm_states_TX_HIG_START 64 8811 #define rx_x4_status5_cl49_ltxsm_states_TX_LI 32 8812 #define rx_x4_status5_cl49_ltxsm_states_TX_E 16 8813 #define rx_x4_status5_cl49_ltxsm_states_TX_T 8 8814 #define rx_x4_status5_cl49_ltxsm_states_TX_D 4 8815 #define rx_x4_status5_cl49_ltxsm_states_TX_C 2 8816 #define rx_x4_status5_cl49_ltxsm_states_TX_INIT 1 8817 8818 /**************************************************************************** 8819 * Enums: rx_x4_status5_burst_error_mode 8820 */ 8821 #define rx_x4_status5_burst_error_mode_BURST_ERROR_11_BITS 0 8822 #define rx_x4_status5_burst_error_mode_BURST_ERROR_16_BITS 1 8823 #define rx_x4_status5_burst_error_mode_BURST_ERROR_17_BITS 2 8824 #define rx_x4_status5_burst_error_mode_BURST_ERROR_18_BITS 3 8825 #define rx_x4_status5_burst_error_mode_BURST_ERROR_19_BITS 4 8826 #define rx_x4_status5_burst_error_mode_BURST_ERROR_20_BITS 5 8827 #define rx_x4_status5_burst_error_mode_BURST_ERROR_21_BITS 6 8828 #define rx_x4_status5_burst_error_mode_BURST_ERROR_22_BITS 7 8829 #define rx_x4_status5_burst_error_mode_BURST_ERROR_23_BITS 8 8830 #define rx_x4_status5_burst_error_mode_BURST_ERROR_24_BITS 9 8831 #define rx_x4_status5_burst_error_mode_BURST_ERROR_25_BITS 10 8832 #define rx_x4_status5_burst_error_mode_BURST_ERROR_26_BITS 11 8833 #define rx_x4_status5_burst_error_mode_BURST_ERROR_27_BITS 12 8834 #define rx_x4_status5_burst_error_mode_BURST_ERROR_28_BITS 13 8835 #define rx_x4_status5_burst_error_mode_BURST_ERROR_29_BITS 14 8836 #define rx_x4_status5_burst_error_mode_BURST_ERROR_30_BITS 15 8837 #define rx_x4_status5_burst_error_mode_BURST_ERROR_31_BITS 16 8838 #define rx_x4_status5_burst_error_mode_BURST_ERROR_32_BITS 17 8839 #define rx_x4_status5_burst_error_mode_BURST_ERROR_33_BITS 18 8840 #define rx_x4_status5_burst_error_mode_BURST_ERROR_34_BITS 19 8841 #define rx_x4_status5_burst_error_mode_BURST_ERROR_35_BITS 20 8842 #define rx_x4_status5_burst_error_mode_BURST_ERROR_36_BITS 21 8843 #define rx_x4_status5_burst_error_mode_BURST_ERROR_37_BITS 22 8844 #define rx_x4_status5_burst_error_mode_BURST_ERROR_38_BITS 23 8845 #define rx_x4_status5_burst_error_mode_BURST_ERROR_39_BITS 24 8846 #define rx_x4_status5_burst_error_mode_BURST_ERROR_40_BITS 25 8847 #define rx_x4_status5_burst_error_mode_BURST_ERROR_41_BITS 26 8848 8849 /**************************************************************************** 8850 * Enums: rx_x4_status5_bermon_state 8851 */ 8852 #define rx_x4_status5_bermon_state_HI_BER 4 8853 #define rx_x4_status5_bermon_state_GOOD_BER 3 8854 #define rx_x4_status5_bermon_state_BER_TEST_SH 2 8855 #define rx_x4_status5_bermon_state_START_TIMER 1 8856 #define rx_x4_status5_bermon_state_BER_MT_INIT 0 8857 8858 /**************************************************************************** 8859 * Enums: rx_x4_status5_rxsm_state_cl49 8860 */ 8861 #define rx_x4_status5_rxsm_state_cl49_RX_HIG_END 128 8862 #define rx_x4_status5_rxsm_state_cl49_RX_HIG_START 64 8863 #define rx_x4_status5_rxsm_state_cl49_RX_LI 32 8864 #define rx_x4_status5_rxsm_state_cl49_RX_E 16 8865 #define rx_x4_status5_rxsm_state_cl49_RX_T 8 8866 #define rx_x4_status5_rxsm_state_cl49_RX_D 4 8867 #define rx_x4_status5_rxsm_state_cl49_RX_C 2 8868 #define rx_x4_status5_rxsm_state_cl49_RX_INIT 1 8869 8870 /**************************************************************************** 8871 * Enums: rx_x4_status5_r_type 8872 */ 8873 #define rx_x4_status5_r_type_BAD_R_TYPE 15 8874 #define rx_x4_status5_r_type_R_TYPE_B0 11 8875 #define rx_x4_status5_r_type_R_TYPE_OB 10 8876 #define rx_x4_status5_r_type_R_TYPE_B1 9 8877 #define rx_x4_status5_r_type_R_TYPE_DB 8 8878 #define rx_x4_status5_r_type_R_TYPE_FC 7 8879 #define rx_x4_status5_r_type_R_TYPE_TB 6 8880 #define rx_x4_status5_r_type_R_TYPE_LI 5 8881 #define rx_x4_status5_r_type_R_TYPE_C 4 8882 #define rx_x4_status5_r_type_R_TYPE_S 3 8883 #define rx_x4_status5_r_type_R_TYPE_T 2 8884 #define rx_x4_status5_r_type_R_TYPE_D 1 8885 #define rx_x4_status5_r_type_R_TYPE_E 0 8886 8887 /**************************************************************************** 8888 * Enums: rx_x4_status5_am_lock_state 8889 */ 8890 #define rx_x4_status5_am_lock_state_INVALID_AM 512 8891 #define rx_x4_status5_am_lock_state_GOOD_AM 256 8892 #define rx_x4_status5_am_lock_state_COMP_AM 128 8893 #define rx_x4_status5_am_lock_state_TIMER_2 64 8894 #define rx_x4_status5_am_lock_state_AM_2_GOOD 32 8895 #define rx_x4_status5_am_lock_state_COMP_2ND 16 8896 #define rx_x4_status5_am_lock_state_TIMER_1 8 8897 #define rx_x4_status5_am_lock_state_FIND_1ST 4 8898 #define rx_x4_status5_am_lock_state_AM_RESET_CNT 2 8899 #define rx_x4_status5_am_lock_state_AM_LOCK_INIT 1 8900 8901 /**************************************************************************** 8902 * Enums: rx_x4_status5_msg_selector 8903 */ 8904 #define rx_x4_status5_msg_selector_RESERVED 0 8905 #define rx_x4_status5_msg_selector_VALUE_802p3 1 8906 #define rx_x4_status5_msg_selector_VALUE_802p9 2 8907 #define rx_x4_status5_msg_selector_VALUE_802p5 3 8908 #define rx_x4_status5_msg_selector_VALUE_1394 4 8909 8910 /**************************************************************************** 8911 * Enums: rx_x4_status5_synce_enum 8912 */ 8913 #define rx_x4_status5_synce_enum_SYNCE_NO_DIV 0 8914 #define rx_x4_status5_synce_enum_SYNCE_DIV_7 1 8915 #define rx_x4_status5_synce_enum_SYNCE_DIV_11 2 8916 8917 /**************************************************************************** 8918 * Enums: rx_x4_status5_synce_enum_stage0 8919 */ 8920 #define rx_x4_status5_synce_enum_stage0_SYNCE_NO_DIV 0 8921 #define rx_x4_status5_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 8922 #define rx_x4_status5_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 8923 8924 /**************************************************************************** 8925 * Enums: rx_x4_status5_cl91_sync_state 8926 */ 8927 #define rx_x4_status5_cl91_sync_state_FIND_1ST 0 8928 #define rx_x4_status5_cl91_sync_state_COUNT_NEXT 1 8929 #define rx_x4_status5_cl91_sync_state_COMP_2ND 2 8930 #define rx_x4_status5_cl91_sync_state_TWO_GOOD 3 8931 8932 /**************************************************************************** 8933 * Enums: rx_x4_status5_cl91_algn_state 8934 */ 8935 #define rx_x4_status5_cl91_algn_state_LOSS_OF_ALIGNMENT 0 8936 #define rx_x4_status5_cl91_algn_state_DESKEW 1 8937 #define rx_x4_status5_cl91_algn_state_DESKEW_FAIL 2 8938 #define rx_x4_status5_cl91_algn_state_ALIGN_ACQUIRED 3 8939 #define rx_x4_status5_cl91_algn_state_CW_GOOD 4 8940 #define rx_x4_status5_cl91_algn_state_CW_BAD 5 8941 #define rx_x4_status5_cl91_algn_state_THREE_BAD 6 8942 8943 /**************************************************************************** 8944 * Enums: rx_x4_status5_fec_sel 8945 */ 8946 #define rx_x4_status5_fec_sel_NO_FEC 0 8947 #define rx_x4_status5_fec_sel_FEC_CL74 1 8948 #define rx_x4_status5_fec_sel_FEC_CL91 2 8949 8950 /**************************************************************************** 8951 * Enums: sc_x1_speed_override0_cl36TxEEEStates_l 8952 */ 8953 #define sc_x1_speed_override0_cl36TxEEEStates_l_TX_REFRESH 8 8954 #define sc_x1_speed_override0_cl36TxEEEStates_l_TX_QUIET 4 8955 #define sc_x1_speed_override0_cl36TxEEEStates_l_TX_SLEEP 2 8956 #define sc_x1_speed_override0_cl36TxEEEStates_l_TX_ACTIVE 1 8957 8958 /**************************************************************************** 8959 * Enums: sc_x1_speed_override0_cl36TxEEEStates_c 8960 */ 8961 #define sc_x1_speed_override0_cl36TxEEEStates_c_TX_REFRESH 3 8962 #define sc_x1_speed_override0_cl36TxEEEStates_c_TX_QUIET 2 8963 #define sc_x1_speed_override0_cl36TxEEEStates_c_TX_SLEEP 1 8964 #define sc_x1_speed_override0_cl36TxEEEStates_c_TX_ACTIVE 0 8965 8966 /**************************************************************************** 8967 * Enums: sc_x1_speed_override0_cl49TxEEEStates_l 8968 */ 8969 #define sc_x1_speed_override0_cl49TxEEEStates_l_SCR_RESET_2 64 8970 #define sc_x1_speed_override0_cl49TxEEEStates_l_SCR_RESET_1 32 8971 #define sc_x1_speed_override0_cl49TxEEEStates_l_TX_WAKE 16 8972 #define sc_x1_speed_override0_cl49TxEEEStates_l_TX_REFRESH 8 8973 #define sc_x1_speed_override0_cl49TxEEEStates_l_TX_QUIET 4 8974 #define sc_x1_speed_override0_cl49TxEEEStates_l_TX_SLEEP 2 8975 #define sc_x1_speed_override0_cl49TxEEEStates_l_TX_ACTIVE 1 8976 8977 /**************************************************************************** 8978 * Enums: sc_x1_speed_override0_fec_req_enum 8979 */ 8980 #define sc_x1_speed_override0_fec_req_enum_FEC_not_supported 0 8981 #define sc_x1_speed_override0_fec_req_enum_FEC_supported_but_not_requested 1 8982 #define sc_x1_speed_override0_fec_req_enum_invalid_setting 2 8983 #define sc_x1_speed_override0_fec_req_enum_FEC_supported_and_requested 3 8984 8985 /**************************************************************************** 8986 * Enums: sc_x1_speed_override0_cl73_pause_enum 8987 */ 8988 #define sc_x1_speed_override0_cl73_pause_enum_No_PAUSE_ability 0 8989 #define sc_x1_speed_override0_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 8990 #define sc_x1_speed_override0_cl73_pause_enum_Symmetric_PAUSE_ability 1 8991 #define sc_x1_speed_override0_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 8992 8993 /**************************************************************************** 8994 * Enums: sc_x1_speed_override0_cl49TxEEEStates_c 8995 */ 8996 #define sc_x1_speed_override0_cl49TxEEEStates_c_SCR_RESET_2 6 8997 #define sc_x1_speed_override0_cl49TxEEEStates_c_SCR_RESET_1 5 8998 #define sc_x1_speed_override0_cl49TxEEEStates_c_TX_WAKE 4 8999 #define sc_x1_speed_override0_cl49TxEEEStates_c_TX_REFRESH 3 9000 #define sc_x1_speed_override0_cl49TxEEEStates_c_TX_QUIET 2 9001 #define sc_x1_speed_override0_cl49TxEEEStates_c_TX_SLEEP 1 9002 #define sc_x1_speed_override0_cl49TxEEEStates_c_TX_ACTIVE 0 9003 9004 /**************************************************************************** 9005 * Enums: sc_x1_speed_override0_cl36RxEEEStates_l 9006 */ 9007 #define sc_x1_speed_override0_cl36RxEEEStates_l_RX_LINK_FAIL 32 9008 #define sc_x1_speed_override0_cl36RxEEEStates_l_RX_WTF 16 9009 #define sc_x1_speed_override0_cl36RxEEEStates_l_RX_WAKE 8 9010 #define sc_x1_speed_override0_cl36RxEEEStates_l_RX_QUIET 4 9011 #define sc_x1_speed_override0_cl36RxEEEStates_l_RX_SLEEP 2 9012 #define sc_x1_speed_override0_cl36RxEEEStates_l_RX_ACTIVE 1 9013 9014 /**************************************************************************** 9015 * Enums: sc_x1_speed_override0_cl36RxEEEStates_c 9016 */ 9017 #define sc_x1_speed_override0_cl36RxEEEStates_c_RX_LINK_FAIL 5 9018 #define sc_x1_speed_override0_cl36RxEEEStates_c_RX_WTF 4 9019 #define sc_x1_speed_override0_cl36RxEEEStates_c_RX_WAKE 3 9020 #define sc_x1_speed_override0_cl36RxEEEStates_c_RX_QUIET 2 9021 #define sc_x1_speed_override0_cl36RxEEEStates_c_RX_SLEEP 1 9022 #define sc_x1_speed_override0_cl36RxEEEStates_c_RX_ACTIVE 0 9023 9024 /**************************************************************************** 9025 * Enums: sc_x1_speed_override0_cl49RxEEEStates_l 9026 */ 9027 #define sc_x1_speed_override0_cl49RxEEEStates_l_RX_LINK_FAIL 32 9028 #define sc_x1_speed_override0_cl49RxEEEStates_l_RX_WTF 16 9029 #define sc_x1_speed_override0_cl49RxEEEStates_l_RX_WAKE 8 9030 #define sc_x1_speed_override0_cl49RxEEEStates_l_RX_QUIET 4 9031 #define sc_x1_speed_override0_cl49RxEEEStates_l_RX_SLEEP 2 9032 #define sc_x1_speed_override0_cl49RxEEEStates_l_RX_ACTIVE 1 9033 9034 /**************************************************************************** 9035 * Enums: sc_x1_speed_override0_cl49RxEEEStates_c 9036 */ 9037 #define sc_x1_speed_override0_cl49RxEEEStates_c_RX_LINK_FAIL 5 9038 #define sc_x1_speed_override0_cl49RxEEEStates_c_RX_WTF 4 9039 #define sc_x1_speed_override0_cl49RxEEEStates_c_RX_WAKE 3 9040 #define sc_x1_speed_override0_cl49RxEEEStates_c_RX_QUIET 2 9041 #define sc_x1_speed_override0_cl49RxEEEStates_c_RX_SLEEP 1 9042 #define sc_x1_speed_override0_cl49RxEEEStates_c_RX_ACTIVE 0 9043 9044 /**************************************************************************** 9045 * Enums: sc_x1_speed_override0_cl48TxEEEStates_l 9046 */ 9047 #define sc_x1_speed_override0_cl48TxEEEStates_l_TX_REFRESH 8 9048 #define sc_x1_speed_override0_cl48TxEEEStates_l_TX_QUIET 4 9049 #define sc_x1_speed_override0_cl48TxEEEStates_l_TX_SLEEP 2 9050 #define sc_x1_speed_override0_cl48TxEEEStates_l_TX_ACTIVE 1 9051 9052 /**************************************************************************** 9053 * Enums: sc_x1_speed_override0_cl48TxEEEStates_c 9054 */ 9055 #define sc_x1_speed_override0_cl48TxEEEStates_c_TX_REFRESH 3 9056 #define sc_x1_speed_override0_cl48TxEEEStates_c_TX_QUIET 2 9057 #define sc_x1_speed_override0_cl48TxEEEStates_c_TX_SLEEP 1 9058 #define sc_x1_speed_override0_cl48TxEEEStates_c_TX_ACTIVE 0 9059 9060 /**************************************************************************** 9061 * Enums: sc_x1_speed_override0_cl48RxEEEStates_l 9062 */ 9063 #define sc_x1_speed_override0_cl48RxEEEStates_l_RX_LINK_FAIL 32 9064 #define sc_x1_speed_override0_cl48RxEEEStates_l_RX_WAKE 16 9065 #define sc_x1_speed_override0_cl48RxEEEStates_l_RX_QUIET 8 9066 #define sc_x1_speed_override0_cl48RxEEEStates_l_RX_DEACT 4 9067 #define sc_x1_speed_override0_cl48RxEEEStates_l_RX_SLEEP 2 9068 #define sc_x1_speed_override0_cl48RxEEEStates_l_RX_ACTIVE 1 9069 9070 /**************************************************************************** 9071 * Enums: sc_x1_speed_override0_cl48RxEEEStates_c 9072 */ 9073 #define sc_x1_speed_override0_cl48RxEEEStates_c_RX_LINK_FAIL 5 9074 #define sc_x1_speed_override0_cl48RxEEEStates_c_RX_WAKE 4 9075 #define sc_x1_speed_override0_cl48RxEEEStates_c_RX_QUIET 3 9076 #define sc_x1_speed_override0_cl48RxEEEStates_c_RX_DEACT 2 9077 #define sc_x1_speed_override0_cl48RxEEEStates_c_RX_SLEEP 1 9078 #define sc_x1_speed_override0_cl48RxEEEStates_c_RX_ACTIVE 0 9079 9080 /**************************************************************************** 9081 * Enums: sc_x1_speed_override0_IQP_Options 9082 */ 9083 #define sc_x1_speed_override0_IQP_Options_i50uA 0 9084 #define sc_x1_speed_override0_IQP_Options_i100uA 1 9085 #define sc_x1_speed_override0_IQP_Options_i150uA 2 9086 #define sc_x1_speed_override0_IQP_Options_i200uA 3 9087 #define sc_x1_speed_override0_IQP_Options_i250uA 4 9088 #define sc_x1_speed_override0_IQP_Options_i300uA 5 9089 #define sc_x1_speed_override0_IQP_Options_i350uA 6 9090 #define sc_x1_speed_override0_IQP_Options_i400uA 7 9091 #define sc_x1_speed_override0_IQP_Options_i450uA 8 9092 #define sc_x1_speed_override0_IQP_Options_i500uA 9 9093 #define sc_x1_speed_override0_IQP_Options_i550uA 10 9094 #define sc_x1_speed_override0_IQP_Options_i600uA 11 9095 #define sc_x1_speed_override0_IQP_Options_i650uA 12 9096 #define sc_x1_speed_override0_IQP_Options_i700uA 13 9097 #define sc_x1_speed_override0_IQP_Options_i750uA 14 9098 #define sc_x1_speed_override0_IQP_Options_i800uA 15 9099 9100 /**************************************************************************** 9101 * Enums: sc_x1_speed_override0_IDriver_Options 9102 */ 9103 #define sc_x1_speed_override0_IDriver_Options_v680mV 0 9104 #define sc_x1_speed_override0_IDriver_Options_v730mV 1 9105 #define sc_x1_speed_override0_IDriver_Options_v780mV 2 9106 #define sc_x1_speed_override0_IDriver_Options_v830mV 3 9107 #define sc_x1_speed_override0_IDriver_Options_v880mV 4 9108 #define sc_x1_speed_override0_IDriver_Options_v930mV 5 9109 #define sc_x1_speed_override0_IDriver_Options_v980mV 6 9110 #define sc_x1_speed_override0_IDriver_Options_v1010mV 7 9111 #define sc_x1_speed_override0_IDriver_Options_v1040mV 8 9112 #define sc_x1_speed_override0_IDriver_Options_v1060mV 9 9113 #define sc_x1_speed_override0_IDriver_Options_v1070mV 10 9114 #define sc_x1_speed_override0_IDriver_Options_v1080mV 11 9115 #define sc_x1_speed_override0_IDriver_Options_v1085mV 12 9116 #define sc_x1_speed_override0_IDriver_Options_v1090mV 13 9117 #define sc_x1_speed_override0_IDriver_Options_v1095mV 14 9118 #define sc_x1_speed_override0_IDriver_Options_v1100mV 15 9119 9120 /**************************************************************************** 9121 * Enums: sc_x1_speed_override0_operationModes 9122 */ 9123 #define sc_x1_speed_override0_operationModes_XGXS 0 9124 #define sc_x1_speed_override0_operationModes_XGXG_nCC 1 9125 #define sc_x1_speed_override0_operationModes_Indlane_OS8 4 9126 #define sc_x1_speed_override0_operationModes_IndLane_OS5 5 9127 #define sc_x1_speed_override0_operationModes_PCI 7 9128 #define sc_x1_speed_override0_operationModes_XGXS_nLQ 8 9129 #define sc_x1_speed_override0_operationModes_XGXS_nLQnCC 9 9130 #define sc_x1_speed_override0_operationModes_PBypass 10 9131 #define sc_x1_speed_override0_operationModes_PBypass_nDSK 11 9132 #define sc_x1_speed_override0_operationModes_ComboCoreMode 12 9133 #define sc_x1_speed_override0_operationModes_Clocks_off 15 9134 9135 /**************************************************************************** 9136 * Enums: sc_x1_speed_override0_actualSpeeds 9137 */ 9138 #define sc_x1_speed_override0_actualSpeeds_dr_10M 0 9139 #define sc_x1_speed_override0_actualSpeeds_dr_100M 1 9140 #define sc_x1_speed_override0_actualSpeeds_dr_1G 2 9141 #define sc_x1_speed_override0_actualSpeeds_dr_2p5G 3 9142 #define sc_x1_speed_override0_actualSpeeds_dr_5G_X4 4 9143 #define sc_x1_speed_override0_actualSpeeds_dr_6G_X4 5 9144 #define sc_x1_speed_override0_actualSpeeds_dr_10G_HiG 6 9145 #define sc_x1_speed_override0_actualSpeeds_dr_10G_CX4 7 9146 #define sc_x1_speed_override0_actualSpeeds_dr_12G_HiG 8 9147 #define sc_x1_speed_override0_actualSpeeds_dr_12p5G_X4 9 9148 #define sc_x1_speed_override0_actualSpeeds_dr_13G_X4 10 9149 #define sc_x1_speed_override0_actualSpeeds_dr_15G_X4 11 9150 #define sc_x1_speed_override0_actualSpeeds_dr_16G_X4 12 9151 #define sc_x1_speed_override0_actualSpeeds_dr_1G_KX 13 9152 #define sc_x1_speed_override0_actualSpeeds_dr_10G_KX4 14 9153 #define sc_x1_speed_override0_actualSpeeds_dr_10G_KR 15 9154 #define sc_x1_speed_override0_actualSpeeds_dr_5G 16 9155 #define sc_x1_speed_override0_actualSpeeds_dr_6p4G 17 9156 #define sc_x1_speed_override0_actualSpeeds_dr_20G_X4 18 9157 #define sc_x1_speed_override0_actualSpeeds_dr_21G_X4 19 9158 #define sc_x1_speed_override0_actualSpeeds_dr_25G_X4 20 9159 #define sc_x1_speed_override0_actualSpeeds_dr_10G_HiG_DXGXS 21 9160 #define sc_x1_speed_override0_actualSpeeds_dr_10G_DXGXS 22 9161 #define sc_x1_speed_override0_actualSpeeds_dr_10p5G_HiG_DXGXS 23 9162 #define sc_x1_speed_override0_actualSpeeds_dr_10p5G_DXGXS 24 9163 #define sc_x1_speed_override0_actualSpeeds_dr_12p773G_HiG_DXGXS 25 9164 #define sc_x1_speed_override0_actualSpeeds_dr_12p773G_DXGXS 26 9165 #define sc_x1_speed_override0_actualSpeeds_dr_10G_XFI 27 9166 #define sc_x1_speed_override0_actualSpeeds_dr_40G 28 9167 #define sc_x1_speed_override0_actualSpeeds_dr_20G_HiG_DXGXS 29 9168 #define sc_x1_speed_override0_actualSpeeds_dr_20G_DXGXS 30 9169 #define sc_x1_speed_override0_actualSpeeds_dr_10G_SFI 31 9170 #define sc_x1_speed_override0_actualSpeeds_dr_31p5G 32 9171 #define sc_x1_speed_override0_actualSpeeds_dr_32p7G 33 9172 #define sc_x1_speed_override0_actualSpeeds_dr_20G_SCR 34 9173 #define sc_x1_speed_override0_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 9174 #define sc_x1_speed_override0_actualSpeeds_dr_10G_DXGXS_SCR 36 9175 #define sc_x1_speed_override0_actualSpeeds_dr_12G_R2 37 9176 #define sc_x1_speed_override0_actualSpeeds_dr_10G_X2 38 9177 #define sc_x1_speed_override0_actualSpeeds_dr_40G_KR4 39 9178 #define sc_x1_speed_override0_actualSpeeds_dr_40G_CR4 40 9179 #define sc_x1_speed_override0_actualSpeeds_dr_100G_CR10 41 9180 #define sc_x1_speed_override0_actualSpeeds_dr_15p75G_DXGXS 44 9181 #define sc_x1_speed_override0_actualSpeeds_dr_20G_KR2 57 9182 #define sc_x1_speed_override0_actualSpeeds_dr_20G_CR2 58 9183 9184 /**************************************************************************** 9185 * Enums: sc_x1_speed_override0_actualSpeedsMisc1 9186 */ 9187 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_2500BRCM_X1 16 9188 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_5000BRCM_X4 17 9189 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_6000BRCM_X4 18 9190 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_10GHiGig_X4 19 9191 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_10GBASE_CX4 20 9192 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_12GHiGig_X4 21 9193 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 9194 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_13GHiGig_X4 23 9195 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_15GHiGig_X4 24 9196 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_16GHiGig_X4 25 9197 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_5000BRCM_X1 26 9198 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_6363BRCM_X1 27 9199 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_20GHiGig_X4 28 9200 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_21GHiGig_X4 29 9201 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 9202 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 9203 9204 /**************************************************************************** 9205 * Enums: sc_x1_speed_override0_IndLaneModes 9206 */ 9207 #define sc_x1_speed_override0_IndLaneModes_SWSDR_div2 0 9208 #define sc_x1_speed_override0_IndLaneModes_SWSDR_div1 1 9209 #define sc_x1_speed_override0_IndLaneModes_DWSDR_div2 2 9210 #define sc_x1_speed_override0_IndLaneModes_DWSDR_div1 3 9211 9212 /**************************************************************************** 9213 * Enums: sc_x1_speed_override0_prbsSelect 9214 */ 9215 #define sc_x1_speed_override0_prbsSelect_prbs7 0 9216 #define sc_x1_speed_override0_prbsSelect_prbs15 1 9217 #define sc_x1_speed_override0_prbsSelect_prbs23 2 9218 #define sc_x1_speed_override0_prbsSelect_prbs31 3 9219 9220 /**************************************************************************** 9221 * Enums: sc_x1_speed_override0_vcoDivider 9222 */ 9223 #define sc_x1_speed_override0_vcoDivider_div32 0 9224 #define sc_x1_speed_override0_vcoDivider_div36 1 9225 #define sc_x1_speed_override0_vcoDivider_div40 2 9226 #define sc_x1_speed_override0_vcoDivider_div42 3 9227 #define sc_x1_speed_override0_vcoDivider_div48 4 9228 #define sc_x1_speed_override0_vcoDivider_div50 5 9229 #define sc_x1_speed_override0_vcoDivider_div52 6 9230 #define sc_x1_speed_override0_vcoDivider_div54 7 9231 #define sc_x1_speed_override0_vcoDivider_div60 8 9232 #define sc_x1_speed_override0_vcoDivider_div64 9 9233 #define sc_x1_speed_override0_vcoDivider_div66 10 9234 #define sc_x1_speed_override0_vcoDivider_div68 11 9235 #define sc_x1_speed_override0_vcoDivider_div70 12 9236 #define sc_x1_speed_override0_vcoDivider_div80 13 9237 #define sc_x1_speed_override0_vcoDivider_div92 14 9238 #define sc_x1_speed_override0_vcoDivider_div100 15 9239 9240 /**************************************************************************** 9241 * Enums: sc_x1_speed_override0_refClkSelect 9242 */ 9243 #define sc_x1_speed_override0_refClkSelect_clk_25MHz 0 9244 #define sc_x1_speed_override0_refClkSelect_clk_100MHz 1 9245 #define sc_x1_speed_override0_refClkSelect_clk_125MHz 2 9246 #define sc_x1_speed_override0_refClkSelect_clk_156p25MHz 3 9247 #define sc_x1_speed_override0_refClkSelect_clk_187p5MHz 4 9248 #define sc_x1_speed_override0_refClkSelect_clk_161p25Mhz 5 9249 #define sc_x1_speed_override0_refClkSelect_clk_50Mhz 6 9250 #define sc_x1_speed_override0_refClkSelect_clk_106p25Mhz 7 9251 9252 /**************************************************************************** 9253 * Enums: sc_x1_speed_override0_aerMMDdevTypeSelect 9254 */ 9255 #define sc_x1_speed_override0_aerMMDdevTypeSelect_combo_core 0 9256 #define sc_x1_speed_override0_aerMMDdevTypeSelect_PMA_PMD 1 9257 #define sc_x1_speed_override0_aerMMDdevTypeSelect_PCS 3 9258 #define sc_x1_speed_override0_aerMMDdevTypeSelect_PHY 4 9259 #define sc_x1_speed_override0_aerMMDdevTypeSelect_DTE 5 9260 #define sc_x1_speed_override0_aerMMDdevTypeSelect_CL73_AN 7 9261 9262 /**************************************************************************** 9263 * Enums: sc_x1_speed_override0_aerMMDportSelect 9264 */ 9265 #define sc_x1_speed_override0_aerMMDportSelect_ln0 0 9266 #define sc_x1_speed_override0_aerMMDportSelect_ln1 1 9267 #define sc_x1_speed_override0_aerMMDportSelect_ln2 2 9268 #define sc_x1_speed_override0_aerMMDportSelect_ln3 3 9269 #define sc_x1_speed_override0_aerMMDportSelect_BCST_ln0_1_2_3 511 9270 #define sc_x1_speed_override0_aerMMDportSelect_BCST_ln0_1 512 9271 #define sc_x1_speed_override0_aerMMDportSelect_BCST_ln2_3 513 9272 9273 /**************************************************************************** 9274 * Enums: sc_x1_speed_override0_firmwareModeSelect 9275 */ 9276 #define sc_x1_speed_override0_firmwareModeSelect_DEFAULT 0 9277 #define sc_x1_speed_override0_firmwareModeSelect_SFP_OPT_LR 1 9278 #define sc_x1_speed_override0_firmwareModeSelect_SFP_DAC 2 9279 #define sc_x1_speed_override0_firmwareModeSelect_XLAUI 3 9280 #define sc_x1_speed_override0_firmwareModeSelect_LONG_CH_6G 4 9281 9282 /**************************************************************************** 9283 * Enums: sc_x1_speed_override0_tempIdxSelect 9284 */ 9285 #define sc_x1_speed_override0_tempIdxSelect_LTE__22p9C 15 9286 #define sc_x1_speed_override0_tempIdxSelect_LTE__12p6C 14 9287 #define sc_x1_speed_override0_tempIdxSelect_LTE__3p0C 13 9288 #define sc_x1_speed_override0_tempIdxSelect_LTE_6p7C 12 9289 #define sc_x1_speed_override0_tempIdxSelect_LTE_16p4C 11 9290 #define sc_x1_speed_override0_tempIdxSelect_LTE_26p6C 10 9291 #define sc_x1_speed_override0_tempIdxSelect_LTE_36p3C 9 9292 #define sc_x1_speed_override0_tempIdxSelect_LTE_46p0C 8 9293 #define sc_x1_speed_override0_tempIdxSelect_LTE_56p2C 7 9294 #define sc_x1_speed_override0_tempIdxSelect_LTE_65p9C 6 9295 #define sc_x1_speed_override0_tempIdxSelect_LTE_75p6C 5 9296 #define sc_x1_speed_override0_tempIdxSelect_LTE_85p3C 4 9297 #define sc_x1_speed_override0_tempIdxSelect_LTE_95p5C 3 9298 #define sc_x1_speed_override0_tempIdxSelect_LTE_105p2C 2 9299 #define sc_x1_speed_override0_tempIdxSelect_LTE_114p9C 1 9300 #define sc_x1_speed_override0_tempIdxSelect_LTE_125p1C 0 9301 9302 /**************************************************************************** 9303 * Enums: sc_x1_speed_override0_port_mode 9304 */ 9305 #define sc_x1_speed_override0_port_mode_QUAD_PORT 0 9306 #define sc_x1_speed_override0_port_mode_TRI_1_PORT 1 9307 #define sc_x1_speed_override0_port_mode_TRI_2_PORT 2 9308 #define sc_x1_speed_override0_port_mode_DUAL_PORT 3 9309 #define sc_x1_speed_override0_port_mode_SINGLE_PORT 4 9310 9311 /**************************************************************************** 9312 * Enums: sc_x1_speed_override0_rev_letter_enum 9313 */ 9314 #define sc_x1_speed_override0_rev_letter_enum_REV_A 0 9315 #define sc_x1_speed_override0_rev_letter_enum_REV_B 1 9316 #define sc_x1_speed_override0_rev_letter_enum_REV_C 2 9317 #define sc_x1_speed_override0_rev_letter_enum_REV_D 3 9318 9319 /**************************************************************************** 9320 * Enums: sc_x1_speed_override0_rev_number_enum 9321 */ 9322 #define sc_x1_speed_override0_rev_number_enum_REV_0 0 9323 #define sc_x1_speed_override0_rev_number_enum_REV_1 1 9324 #define sc_x1_speed_override0_rev_number_enum_REV_2 2 9325 #define sc_x1_speed_override0_rev_number_enum_REV_3 3 9326 #define sc_x1_speed_override0_rev_number_enum_REV_4 4 9327 #define sc_x1_speed_override0_rev_number_enum_REV_5 5 9328 #define sc_x1_speed_override0_rev_number_enum_REV_6 6 9329 #define sc_x1_speed_override0_rev_number_enum_REV_7 7 9330 9331 /**************************************************************************** 9332 * Enums: sc_x1_speed_override0_bonding_enum 9333 */ 9334 #define sc_x1_speed_override0_bonding_enum_WIRE_BOND 0 9335 #define sc_x1_speed_override0_bonding_enum_FLIP_CHIP 1 9336 9337 /**************************************************************************** 9338 * Enums: sc_x1_speed_override0_tech_process 9339 */ 9340 #define sc_x1_speed_override0_tech_process_PROCESS_90NM 0 9341 #define sc_x1_speed_override0_tech_process_PROCESS_65NM 1 9342 #define sc_x1_speed_override0_tech_process_PROCESS_40NM 2 9343 #define sc_x1_speed_override0_tech_process_PROCESS_28NM 3 9344 9345 /**************************************************************************** 9346 * Enums: sc_x1_speed_override0_model_num 9347 */ 9348 #define sc_x1_speed_override0_model_num_SERDES_CL73 0 9349 #define sc_x1_speed_override0_model_num_XGXS_16G 1 9350 #define sc_x1_speed_override0_model_num_HYPERCORE 2 9351 #define sc_x1_speed_override0_model_num_HYPERLITE 3 9352 #define sc_x1_speed_override0_model_num_PCIE_G2_PIPE 4 9353 #define sc_x1_speed_override0_model_num_SERDES_1p25GBd 5 9354 #define sc_x1_speed_override0_model_num_SATA2 6 9355 #define sc_x1_speed_override0_model_num_QSGMII 7 9356 #define sc_x1_speed_override0_model_num_XGXS10G 8 9357 #define sc_x1_speed_override0_model_num_WARPCORE 9 9358 #define sc_x1_speed_override0_model_num_XFICORE 10 9359 #define sc_x1_speed_override0_model_num_RXFI 11 9360 #define sc_x1_speed_override0_model_num_WARPLITE 12 9361 #define sc_x1_speed_override0_model_num_PENTACORE 13 9362 #define sc_x1_speed_override0_model_num_ESM 14 9363 #define sc_x1_speed_override0_model_num_QUAD_SGMII 15 9364 #define sc_x1_speed_override0_model_num_WARPCORE_3 16 9365 #define sc_x1_speed_override0_model_num_TSC 17 9366 #define sc_x1_speed_override0_model_num_TSC4E 18 9367 #define sc_x1_speed_override0_model_num_TSC12E 19 9368 #define sc_x1_speed_override0_model_num_TSC4F 20 9369 #define sc_x1_speed_override0_model_num_XGXS_CL73_90NM 29 9370 #define sc_x1_speed_override0_model_num_SERDES_CL73_90NM 30 9371 #define sc_x1_speed_override0_model_num_WARPCORE3 32 9372 #define sc_x1_speed_override0_model_num_WARPCORE4_TSC 33 9373 #define sc_x1_speed_override0_model_num_RXAUI 34 9374 9375 /**************************************************************************** 9376 * Enums: sc_x1_speed_override0_payload 9377 */ 9378 #define sc_x1_speed_override0_payload_REPEAT_2_BYTES 0 9379 #define sc_x1_speed_override0_payload_RAMPING 1 9380 #define sc_x1_speed_override0_payload_CL48_CRPAT 2 9381 #define sc_x1_speed_override0_payload_CL48_CJPAT 3 9382 #define sc_x1_speed_override0_payload_CL36_LONG_CRPAT 4 9383 #define sc_x1_speed_override0_payload_CL36_SHORT_CRPAT 5 9384 9385 /**************************************************************************** 9386 * Enums: sc_x1_speed_override0_sc 9387 */ 9388 #define sc_x1_speed_override0_sc_S_10G_CR1 0 9389 #define sc_x1_speed_override0_sc_S_10G_KR1 1 9390 #define sc_x1_speed_override0_sc_S_10G_X1 2 9391 #define sc_x1_speed_override0_sc_S_10G_HG2_CR1 4 9392 #define sc_x1_speed_override0_sc_S_10G_HG2_KR1 5 9393 #define sc_x1_speed_override0_sc_S_10G_HG2_X1 6 9394 #define sc_x1_speed_override0_sc_S_20G_CR1 8 9395 #define sc_x1_speed_override0_sc_S_20G_KR1 9 9396 #define sc_x1_speed_override0_sc_S_20G_X1 10 9397 #define sc_x1_speed_override0_sc_S_20G_HG2_CR1 12 9398 #define sc_x1_speed_override0_sc_S_20G_HG2_KR1 13 9399 #define sc_x1_speed_override0_sc_S_20G_HG2_X1 14 9400 #define sc_x1_speed_override0_sc_S_25G_CR1 16 9401 #define sc_x1_speed_override0_sc_S_25G_KR1 17 9402 #define sc_x1_speed_override0_sc_S_25G_X1 18 9403 #define sc_x1_speed_override0_sc_S_25G_HG2_CR1 20 9404 #define sc_x1_speed_override0_sc_S_25G_HG2_KR1 21 9405 #define sc_x1_speed_override0_sc_S_25G_HG2_X1 22 9406 #define sc_x1_speed_override0_sc_S_20G_CR2 24 9407 #define sc_x1_speed_override0_sc_S_20G_KR2 25 9408 #define sc_x1_speed_override0_sc_S_20G_X2 26 9409 #define sc_x1_speed_override0_sc_S_20G_HG2_CR2 28 9410 #define sc_x1_speed_override0_sc_S_20G_HG2_KR2 29 9411 #define sc_x1_speed_override0_sc_S_20G_HG2_X2 30 9412 #define sc_x1_speed_override0_sc_S_40G_CR2 32 9413 #define sc_x1_speed_override0_sc_S_40G_KR2 33 9414 #define sc_x1_speed_override0_sc_S_40G_X2 34 9415 #define sc_x1_speed_override0_sc_S_40G_HG2_CR2 36 9416 #define sc_x1_speed_override0_sc_S_40G_HG2_KR2 37 9417 #define sc_x1_speed_override0_sc_S_40G_HG2_X2 38 9418 #define sc_x1_speed_override0_sc_S_40G_CR4 40 9419 #define sc_x1_speed_override0_sc_S_40G_KR4 41 9420 #define sc_x1_speed_override0_sc_S_40G_X4 42 9421 #define sc_x1_speed_override0_sc_S_40G_HG2_CR4 44 9422 #define sc_x1_speed_override0_sc_S_40G_HG2_KR4 45 9423 #define sc_x1_speed_override0_sc_S_40G_HG2_X4 46 9424 #define sc_x1_speed_override0_sc_S_50G_CR2 48 9425 #define sc_x1_speed_override0_sc_S_50G_KR2 49 9426 #define sc_x1_speed_override0_sc_S_50G_X2 50 9427 #define sc_x1_speed_override0_sc_S_50G_HG2_CR2 52 9428 #define sc_x1_speed_override0_sc_S_50G_HG2_KR2 53 9429 #define sc_x1_speed_override0_sc_S_50G_HG2_X2 54 9430 #define sc_x1_speed_override0_sc_S_50G_CR4 56 9431 #define sc_x1_speed_override0_sc_S_50G_KR4 57 9432 #define sc_x1_speed_override0_sc_S_50G_X4 58 9433 #define sc_x1_speed_override0_sc_S_50G_HG2_CR4 60 9434 #define sc_x1_speed_override0_sc_S_50G_HG2_KR4 61 9435 #define sc_x1_speed_override0_sc_S_50G_HG2_X4 62 9436 #define sc_x1_speed_override0_sc_S_100G_CR4 64 9437 #define sc_x1_speed_override0_sc_S_100G_KR4 65 9438 #define sc_x1_speed_override0_sc_S_100G_X4 66 9439 #define sc_x1_speed_override0_sc_S_100G_HG2_CR4 68 9440 #define sc_x1_speed_override0_sc_S_100G_HG2_KR4 69 9441 #define sc_x1_speed_override0_sc_S_100G_HG2_X4 70 9442 #define sc_x1_speed_override0_sc_S_CL73_20GVCO 72 9443 #define sc_x1_speed_override0_sc_S_CL73_25GVCO 80 9444 #define sc_x1_speed_override0_sc_S_CL36_20GVCO 88 9445 #define sc_x1_speed_override0_sc_S_CL36_25GVCO 96 9446 9447 /**************************************************************************** 9448 * Enums: sc_x1_speed_override0_t_fifo_modes 9449 */ 9450 #define sc_x1_speed_override0_t_fifo_modes_T_FIFO_MODE_BYPASS 0 9451 #define sc_x1_speed_override0_t_fifo_modes_T_FIFO_MODE_40G 1 9452 #define sc_x1_speed_override0_t_fifo_modes_T_FIFO_MODE_100G 2 9453 #define sc_x1_speed_override0_t_fifo_modes_T_FIFO_MODE_20G 3 9454 9455 /**************************************************************************** 9456 * Enums: sc_x1_speed_override0_t_enc_modes 9457 */ 9458 #define sc_x1_speed_override0_t_enc_modes_T_ENC_MODE_BYPASS 0 9459 #define sc_x1_speed_override0_t_enc_modes_T_ENC_MODE_CL49 1 9460 #define sc_x1_speed_override0_t_enc_modes_T_ENC_MODE_CL82 2 9461 9462 /**************************************************************************** 9463 * Enums: sc_x1_speed_override0_btmx_mode 9464 */ 9465 #define sc_x1_speed_override0_btmx_mode_BS_BTMX_MODE_1to1 0 9466 #define sc_x1_speed_override0_btmx_mode_BS_BTMX_MODE_2to1 1 9467 #define sc_x1_speed_override0_btmx_mode_BS_BTMX_MODE_5to1 2 9468 9469 /**************************************************************************** 9470 * Enums: sc_x1_speed_override0_t_type_cl82 9471 */ 9472 #define sc_x1_speed_override0_t_type_cl82_T_TYPE_B1 5 9473 #define sc_x1_speed_override0_t_type_cl82_T_TYPE_C 4 9474 #define sc_x1_speed_override0_t_type_cl82_T_TYPE_S 3 9475 #define sc_x1_speed_override0_t_type_cl82_T_TYPE_T 2 9476 #define sc_x1_speed_override0_t_type_cl82_T_TYPE_D 1 9477 #define sc_x1_speed_override0_t_type_cl82_T_TYPE_E 0 9478 9479 /**************************************************************************** 9480 * Enums: sc_x1_speed_override0_txsm_state_cl82 9481 */ 9482 #define sc_x1_speed_override0_txsm_state_cl82_TX_HIG_END 6 9483 #define sc_x1_speed_override0_txsm_state_cl82_TX_HIG_START 5 9484 #define sc_x1_speed_override0_txsm_state_cl82_TX_E 4 9485 #define sc_x1_speed_override0_txsm_state_cl82_TX_T 3 9486 #define sc_x1_speed_override0_txsm_state_cl82_TX_D 2 9487 #define sc_x1_speed_override0_txsm_state_cl82_TX_C 1 9488 #define sc_x1_speed_override0_txsm_state_cl82_TX_INIT 0 9489 9490 /**************************************************************************** 9491 * Enums: sc_x1_speed_override0_ltxsm_state_cl82 9492 */ 9493 #define sc_x1_speed_override0_ltxsm_state_cl82_TX_HIG_END 64 9494 #define sc_x1_speed_override0_ltxsm_state_cl82_TX_HIG_START 32 9495 #define sc_x1_speed_override0_ltxsm_state_cl82_TX_E 16 9496 #define sc_x1_speed_override0_ltxsm_state_cl82_TX_T 8 9497 #define sc_x1_speed_override0_ltxsm_state_cl82_TX_D 4 9498 #define sc_x1_speed_override0_ltxsm_state_cl82_TX_C 2 9499 #define sc_x1_speed_override0_ltxsm_state_cl82_TX_INIT 1 9500 9501 /**************************************************************************** 9502 * Enums: sc_x1_speed_override0_r_type_coded_cl82 9503 */ 9504 #define sc_x1_speed_override0_r_type_coded_cl82_R_TYPE_B1 32 9505 #define sc_x1_speed_override0_r_type_coded_cl82_R_TYPE_C 16 9506 #define sc_x1_speed_override0_r_type_coded_cl82_R_TYPE_S 8 9507 #define sc_x1_speed_override0_r_type_coded_cl82_R_TYPE_T 4 9508 #define sc_x1_speed_override0_r_type_coded_cl82_R_TYPE_D 2 9509 #define sc_x1_speed_override0_r_type_coded_cl82_R_TYPE_E 1 9510 9511 /**************************************************************************** 9512 * Enums: sc_x1_speed_override0_rxsm_state_cl82 9513 */ 9514 #define sc_x1_speed_override0_rxsm_state_cl82_RX_HIG_END 64 9515 #define sc_x1_speed_override0_rxsm_state_cl82_RX_HIG_START 32 9516 #define sc_x1_speed_override0_rxsm_state_cl82_RX_E 16 9517 #define sc_x1_speed_override0_rxsm_state_cl82_RX_T 8 9518 #define sc_x1_speed_override0_rxsm_state_cl82_RX_D 4 9519 #define sc_x1_speed_override0_rxsm_state_cl82_RX_C 2 9520 #define sc_x1_speed_override0_rxsm_state_cl82_RX_INIT 1 9521 9522 /**************************************************************************** 9523 * Enums: sc_x1_speed_override0_deskew_state 9524 */ 9525 #define sc_x1_speed_override0_deskew_state_ALIGN_ACQUIRED 2 9526 #define sc_x1_speed_override0_deskew_state_LOSS_OF_ALIGNMENT 1 9527 9528 /**************************************************************************** 9529 * Enums: sc_x1_speed_override0_os_mode_enum 9530 */ 9531 #define sc_x1_speed_override0_os_mode_enum_OS_MODE_1 0 9532 #define sc_x1_speed_override0_os_mode_enum_OS_MODE_2 1 9533 #define sc_x1_speed_override0_os_mode_enum_OS_MODE_4 2 9534 #define sc_x1_speed_override0_os_mode_enum_OS_MODE_16p5 8 9535 #define sc_x1_speed_override0_os_mode_enum_OS_MODE_20p625 12 9536 9537 /**************************************************************************** 9538 * Enums: sc_x1_speed_override0_scr_modes 9539 */ 9540 #define sc_x1_speed_override0_scr_modes_T_SCR_MODE_BYPASS 0 9541 #define sc_x1_speed_override0_scr_modes_T_SCR_MODE_CL49 1 9542 #define sc_x1_speed_override0_scr_modes_T_SCR_MODE_40G_2_LANE 2 9543 #define sc_x1_speed_override0_scr_modes_T_SCR_MODE_100G 3 9544 #define sc_x1_speed_override0_scr_modes_T_SCR_MODE_20G 4 9545 #define sc_x1_speed_override0_scr_modes_T_SCR_MODE_40G_4_LANE 5 9546 9547 /**************************************************************************** 9548 * Enums: sc_x1_speed_override0_descr_modes 9549 */ 9550 #define sc_x1_speed_override0_descr_modes_R_DESCR_MODE_BYPASS 0 9551 #define sc_x1_speed_override0_descr_modes_R_DESCR_MODE_CL49 1 9552 #define sc_x1_speed_override0_descr_modes_R_DESCR_MODE_CL82 2 9553 9554 /**************************************************************************** 9555 * Enums: sc_x1_speed_override0_r_dec_tl_mode 9556 */ 9557 #define sc_x1_speed_override0_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 9558 #define sc_x1_speed_override0_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 9559 #define sc_x1_speed_override0_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 9560 9561 /**************************************************************************** 9562 * Enums: sc_x1_speed_override0_r_dec_fsm_mode 9563 */ 9564 #define sc_x1_speed_override0_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 9565 #define sc_x1_speed_override0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 9566 #define sc_x1_speed_override0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 9567 9568 /**************************************************************************** 9569 * Enums: sc_x1_speed_override0_r_deskew_mode 9570 */ 9571 #define sc_x1_speed_override0_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 9572 #define sc_x1_speed_override0_r_deskew_mode_R_DESKEW_MODE_20G 1 9573 #define sc_x1_speed_override0_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 9574 #define sc_x1_speed_override0_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 9575 #define sc_x1_speed_override0_r_deskew_mode_R_DESKEW_MODE_100G 4 9576 #define sc_x1_speed_override0_r_deskew_mode_R_DESKEW_MODE_CL49 5 9577 #define sc_x1_speed_override0_r_deskew_mode_R_DESKEW_MODE_CL91 6 9578 9579 /**************************************************************************** 9580 * Enums: sc_x1_speed_override0_bs_dist_modes 9581 */ 9582 #define sc_x1_speed_override0_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 9583 #define sc_x1_speed_override0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 9584 #define sc_x1_speed_override0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 9585 #define sc_x1_speed_override0_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 9586 9587 /**************************************************************************** 9588 * Enums: sc_x1_speed_override0_cl49_t_type 9589 */ 9590 #define sc_x1_speed_override0_cl49_t_type_BAD_T_TYPE 15 9591 #define sc_x1_speed_override0_cl49_t_type_T_TYPE_B0 11 9592 #define sc_x1_speed_override0_cl49_t_type_T_TYPE_OB 10 9593 #define sc_x1_speed_override0_cl49_t_type_T_TYPE_B1 9 9594 #define sc_x1_speed_override0_cl49_t_type_T_TYPE_DB 8 9595 #define sc_x1_speed_override0_cl49_t_type_T_TYPE_FC 7 9596 #define sc_x1_speed_override0_cl49_t_type_T_TYPE_TB 6 9597 #define sc_x1_speed_override0_cl49_t_type_T_TYPE_LI 5 9598 #define sc_x1_speed_override0_cl49_t_type_T_TYPE_C 4 9599 #define sc_x1_speed_override0_cl49_t_type_T_TYPE_S 3 9600 #define sc_x1_speed_override0_cl49_t_type_T_TYPE_T 2 9601 #define sc_x1_speed_override0_cl49_t_type_T_TYPE_D 1 9602 #define sc_x1_speed_override0_cl49_t_type_T_TYPE_E 0 9603 9604 /**************************************************************************** 9605 * Enums: sc_x1_speed_override0_cl49_txsm_states 9606 */ 9607 #define sc_x1_speed_override0_cl49_txsm_states_TX_HIG_END 7 9608 #define sc_x1_speed_override0_cl49_txsm_states_TX_HIG_START 6 9609 #define sc_x1_speed_override0_cl49_txsm_states_TX_LI 5 9610 #define sc_x1_speed_override0_cl49_txsm_states_TX_E 4 9611 #define sc_x1_speed_override0_cl49_txsm_states_TX_T 3 9612 #define sc_x1_speed_override0_cl49_txsm_states_TX_D 2 9613 #define sc_x1_speed_override0_cl49_txsm_states_TX_C 1 9614 #define sc_x1_speed_override0_cl49_txsm_states_TX_INIT 0 9615 9616 /**************************************************************************** 9617 * Enums: sc_x1_speed_override0_cl49_ltxsm_states 9618 */ 9619 #define sc_x1_speed_override0_cl49_ltxsm_states_TX_HIG_END 128 9620 #define sc_x1_speed_override0_cl49_ltxsm_states_TX_HIG_START 64 9621 #define sc_x1_speed_override0_cl49_ltxsm_states_TX_LI 32 9622 #define sc_x1_speed_override0_cl49_ltxsm_states_TX_E 16 9623 #define sc_x1_speed_override0_cl49_ltxsm_states_TX_T 8 9624 #define sc_x1_speed_override0_cl49_ltxsm_states_TX_D 4 9625 #define sc_x1_speed_override0_cl49_ltxsm_states_TX_C 2 9626 #define sc_x1_speed_override0_cl49_ltxsm_states_TX_INIT 1 9627 9628 /**************************************************************************** 9629 * Enums: sc_x1_speed_override0_burst_error_mode 9630 */ 9631 #define sc_x1_speed_override0_burst_error_mode_BURST_ERROR_11_BITS 0 9632 #define sc_x1_speed_override0_burst_error_mode_BURST_ERROR_16_BITS 1 9633 #define sc_x1_speed_override0_burst_error_mode_BURST_ERROR_17_BITS 2 9634 #define sc_x1_speed_override0_burst_error_mode_BURST_ERROR_18_BITS 3 9635 #define sc_x1_speed_override0_burst_error_mode_BURST_ERROR_19_BITS 4 9636 #define sc_x1_speed_override0_burst_error_mode_BURST_ERROR_20_BITS 5 9637 #define sc_x1_speed_override0_burst_error_mode_BURST_ERROR_21_BITS 6 9638 #define sc_x1_speed_override0_burst_error_mode_BURST_ERROR_22_BITS 7 9639 #define sc_x1_speed_override0_burst_error_mode_BURST_ERROR_23_BITS 8 9640 #define sc_x1_speed_override0_burst_error_mode_BURST_ERROR_24_BITS 9 9641 #define sc_x1_speed_override0_burst_error_mode_BURST_ERROR_25_BITS 10 9642 #define sc_x1_speed_override0_burst_error_mode_BURST_ERROR_26_BITS 11 9643 #define sc_x1_speed_override0_burst_error_mode_BURST_ERROR_27_BITS 12 9644 #define sc_x1_speed_override0_burst_error_mode_BURST_ERROR_28_BITS 13 9645 #define sc_x1_speed_override0_burst_error_mode_BURST_ERROR_29_BITS 14 9646 #define sc_x1_speed_override0_burst_error_mode_BURST_ERROR_30_BITS 15 9647 #define sc_x1_speed_override0_burst_error_mode_BURST_ERROR_31_BITS 16 9648 #define sc_x1_speed_override0_burst_error_mode_BURST_ERROR_32_BITS 17 9649 #define sc_x1_speed_override0_burst_error_mode_BURST_ERROR_33_BITS 18 9650 #define sc_x1_speed_override0_burst_error_mode_BURST_ERROR_34_BITS 19 9651 #define sc_x1_speed_override0_burst_error_mode_BURST_ERROR_35_BITS 20 9652 #define sc_x1_speed_override0_burst_error_mode_BURST_ERROR_36_BITS 21 9653 #define sc_x1_speed_override0_burst_error_mode_BURST_ERROR_37_BITS 22 9654 #define sc_x1_speed_override0_burst_error_mode_BURST_ERROR_38_BITS 23 9655 #define sc_x1_speed_override0_burst_error_mode_BURST_ERROR_39_BITS 24 9656 #define sc_x1_speed_override0_burst_error_mode_BURST_ERROR_40_BITS 25 9657 #define sc_x1_speed_override0_burst_error_mode_BURST_ERROR_41_BITS 26 9658 9659 /**************************************************************************** 9660 * Enums: sc_x1_speed_override0_bermon_state 9661 */ 9662 #define sc_x1_speed_override0_bermon_state_HI_BER 4 9663 #define sc_x1_speed_override0_bermon_state_GOOD_BER 3 9664 #define sc_x1_speed_override0_bermon_state_BER_TEST_SH 2 9665 #define sc_x1_speed_override0_bermon_state_START_TIMER 1 9666 #define sc_x1_speed_override0_bermon_state_BER_MT_INIT 0 9667 9668 /**************************************************************************** 9669 * Enums: sc_x1_speed_override0_rxsm_state_cl49 9670 */ 9671 #define sc_x1_speed_override0_rxsm_state_cl49_RX_HIG_END 128 9672 #define sc_x1_speed_override0_rxsm_state_cl49_RX_HIG_START 64 9673 #define sc_x1_speed_override0_rxsm_state_cl49_RX_LI 32 9674 #define sc_x1_speed_override0_rxsm_state_cl49_RX_E 16 9675 #define sc_x1_speed_override0_rxsm_state_cl49_RX_T 8 9676 #define sc_x1_speed_override0_rxsm_state_cl49_RX_D 4 9677 #define sc_x1_speed_override0_rxsm_state_cl49_RX_C 2 9678 #define sc_x1_speed_override0_rxsm_state_cl49_RX_INIT 1 9679 9680 /**************************************************************************** 9681 * Enums: sc_x1_speed_override0_r_type 9682 */ 9683 #define sc_x1_speed_override0_r_type_BAD_R_TYPE 15 9684 #define sc_x1_speed_override0_r_type_R_TYPE_B0 11 9685 #define sc_x1_speed_override0_r_type_R_TYPE_OB 10 9686 #define sc_x1_speed_override0_r_type_R_TYPE_B1 9 9687 #define sc_x1_speed_override0_r_type_R_TYPE_DB 8 9688 #define sc_x1_speed_override0_r_type_R_TYPE_FC 7 9689 #define sc_x1_speed_override0_r_type_R_TYPE_TB 6 9690 #define sc_x1_speed_override0_r_type_R_TYPE_LI 5 9691 #define sc_x1_speed_override0_r_type_R_TYPE_C 4 9692 #define sc_x1_speed_override0_r_type_R_TYPE_S 3 9693 #define sc_x1_speed_override0_r_type_R_TYPE_T 2 9694 #define sc_x1_speed_override0_r_type_R_TYPE_D 1 9695 #define sc_x1_speed_override0_r_type_R_TYPE_E 0 9696 9697 /**************************************************************************** 9698 * Enums: sc_x1_speed_override0_am_lock_state 9699 */ 9700 #define sc_x1_speed_override0_am_lock_state_INVALID_AM 512 9701 #define sc_x1_speed_override0_am_lock_state_GOOD_AM 256 9702 #define sc_x1_speed_override0_am_lock_state_COMP_AM 128 9703 #define sc_x1_speed_override0_am_lock_state_TIMER_2 64 9704 #define sc_x1_speed_override0_am_lock_state_AM_2_GOOD 32 9705 #define sc_x1_speed_override0_am_lock_state_COMP_2ND 16 9706 #define sc_x1_speed_override0_am_lock_state_TIMER_1 8 9707 #define sc_x1_speed_override0_am_lock_state_FIND_1ST 4 9708 #define sc_x1_speed_override0_am_lock_state_AM_RESET_CNT 2 9709 #define sc_x1_speed_override0_am_lock_state_AM_LOCK_INIT 1 9710 9711 /**************************************************************************** 9712 * Enums: sc_x1_speed_override0_msg_selector 9713 */ 9714 #define sc_x1_speed_override0_msg_selector_RESERVED 0 9715 #define sc_x1_speed_override0_msg_selector_VALUE_802p3 1 9716 #define sc_x1_speed_override0_msg_selector_VALUE_802p9 2 9717 #define sc_x1_speed_override0_msg_selector_VALUE_802p5 3 9718 #define sc_x1_speed_override0_msg_selector_VALUE_1394 4 9719 9720 /**************************************************************************** 9721 * Enums: sc_x1_speed_override0_synce_enum 9722 */ 9723 #define sc_x1_speed_override0_synce_enum_SYNCE_NO_DIV 0 9724 #define sc_x1_speed_override0_synce_enum_SYNCE_DIV_7 1 9725 #define sc_x1_speed_override0_synce_enum_SYNCE_DIV_11 2 9726 9727 /**************************************************************************** 9728 * Enums: sc_x1_speed_override0_synce_enum_stage0 9729 */ 9730 #define sc_x1_speed_override0_synce_enum_stage0_SYNCE_NO_DIV 0 9731 #define sc_x1_speed_override0_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 9732 #define sc_x1_speed_override0_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 9733 9734 /**************************************************************************** 9735 * Enums: sc_x1_speed_override0_cl91_sync_state 9736 */ 9737 #define sc_x1_speed_override0_cl91_sync_state_FIND_1ST 0 9738 #define sc_x1_speed_override0_cl91_sync_state_COUNT_NEXT 1 9739 #define sc_x1_speed_override0_cl91_sync_state_COMP_2ND 2 9740 #define sc_x1_speed_override0_cl91_sync_state_TWO_GOOD 3 9741 9742 /**************************************************************************** 9743 * Enums: sc_x1_speed_override0_cl91_algn_state 9744 */ 9745 #define sc_x1_speed_override0_cl91_algn_state_LOSS_OF_ALIGNMENT 0 9746 #define sc_x1_speed_override0_cl91_algn_state_DESKEW 1 9747 #define sc_x1_speed_override0_cl91_algn_state_DESKEW_FAIL 2 9748 #define sc_x1_speed_override0_cl91_algn_state_ALIGN_ACQUIRED 3 9749 #define sc_x1_speed_override0_cl91_algn_state_CW_GOOD 4 9750 #define sc_x1_speed_override0_cl91_algn_state_CW_BAD 5 9751 #define sc_x1_speed_override0_cl91_algn_state_THREE_BAD 6 9752 9753 /**************************************************************************** 9754 * Enums: sc_x1_speed_override0_fec_sel 9755 */ 9756 #define sc_x1_speed_override0_fec_sel_NO_FEC 0 9757 #define sc_x1_speed_override0_fec_sel_FEC_CL74 1 9758 #define sc_x1_speed_override0_fec_sel_FEC_CL91 2 9759 9760 /**************************************************************************** 9761 * Enums: sc_x1_speed_override1_cl36TxEEEStates_l 9762 */ 9763 #define sc_x1_speed_override1_cl36TxEEEStates_l_TX_REFRESH 8 9764 #define sc_x1_speed_override1_cl36TxEEEStates_l_TX_QUIET 4 9765 #define sc_x1_speed_override1_cl36TxEEEStates_l_TX_SLEEP 2 9766 #define sc_x1_speed_override1_cl36TxEEEStates_l_TX_ACTIVE 1 9767 9768 /**************************************************************************** 9769 * Enums: sc_x1_speed_override1_cl36TxEEEStates_c 9770 */ 9771 #define sc_x1_speed_override1_cl36TxEEEStates_c_TX_REFRESH 3 9772 #define sc_x1_speed_override1_cl36TxEEEStates_c_TX_QUIET 2 9773 #define sc_x1_speed_override1_cl36TxEEEStates_c_TX_SLEEP 1 9774 #define sc_x1_speed_override1_cl36TxEEEStates_c_TX_ACTIVE 0 9775 9776 /**************************************************************************** 9777 * Enums: sc_x1_speed_override1_cl49TxEEEStates_l 9778 */ 9779 #define sc_x1_speed_override1_cl49TxEEEStates_l_SCR_RESET_2 64 9780 #define sc_x1_speed_override1_cl49TxEEEStates_l_SCR_RESET_1 32 9781 #define sc_x1_speed_override1_cl49TxEEEStates_l_TX_WAKE 16 9782 #define sc_x1_speed_override1_cl49TxEEEStates_l_TX_REFRESH 8 9783 #define sc_x1_speed_override1_cl49TxEEEStates_l_TX_QUIET 4 9784 #define sc_x1_speed_override1_cl49TxEEEStates_l_TX_SLEEP 2 9785 #define sc_x1_speed_override1_cl49TxEEEStates_l_TX_ACTIVE 1 9786 9787 /**************************************************************************** 9788 * Enums: sc_x1_speed_override1_fec_req_enum 9789 */ 9790 #define sc_x1_speed_override1_fec_req_enum_FEC_not_supported 0 9791 #define sc_x1_speed_override1_fec_req_enum_FEC_supported_but_not_requested 1 9792 #define sc_x1_speed_override1_fec_req_enum_invalid_setting 2 9793 #define sc_x1_speed_override1_fec_req_enum_FEC_supported_and_requested 3 9794 9795 /**************************************************************************** 9796 * Enums: sc_x1_speed_override1_cl73_pause_enum 9797 */ 9798 #define sc_x1_speed_override1_cl73_pause_enum_No_PAUSE_ability 0 9799 #define sc_x1_speed_override1_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 9800 #define sc_x1_speed_override1_cl73_pause_enum_Symmetric_PAUSE_ability 1 9801 #define sc_x1_speed_override1_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 9802 9803 /**************************************************************************** 9804 * Enums: sc_x1_speed_override1_cl49TxEEEStates_c 9805 */ 9806 #define sc_x1_speed_override1_cl49TxEEEStates_c_SCR_RESET_2 6 9807 #define sc_x1_speed_override1_cl49TxEEEStates_c_SCR_RESET_1 5 9808 #define sc_x1_speed_override1_cl49TxEEEStates_c_TX_WAKE 4 9809 #define sc_x1_speed_override1_cl49TxEEEStates_c_TX_REFRESH 3 9810 #define sc_x1_speed_override1_cl49TxEEEStates_c_TX_QUIET 2 9811 #define sc_x1_speed_override1_cl49TxEEEStates_c_TX_SLEEP 1 9812 #define sc_x1_speed_override1_cl49TxEEEStates_c_TX_ACTIVE 0 9813 9814 /**************************************************************************** 9815 * Enums: sc_x1_speed_override1_cl36RxEEEStates_l 9816 */ 9817 #define sc_x1_speed_override1_cl36RxEEEStates_l_RX_LINK_FAIL 32 9818 #define sc_x1_speed_override1_cl36RxEEEStates_l_RX_WTF 16 9819 #define sc_x1_speed_override1_cl36RxEEEStates_l_RX_WAKE 8 9820 #define sc_x1_speed_override1_cl36RxEEEStates_l_RX_QUIET 4 9821 #define sc_x1_speed_override1_cl36RxEEEStates_l_RX_SLEEP 2 9822 #define sc_x1_speed_override1_cl36RxEEEStates_l_RX_ACTIVE 1 9823 9824 /**************************************************************************** 9825 * Enums: sc_x1_speed_override1_cl36RxEEEStates_c 9826 */ 9827 #define sc_x1_speed_override1_cl36RxEEEStates_c_RX_LINK_FAIL 5 9828 #define sc_x1_speed_override1_cl36RxEEEStates_c_RX_WTF 4 9829 #define sc_x1_speed_override1_cl36RxEEEStates_c_RX_WAKE 3 9830 #define sc_x1_speed_override1_cl36RxEEEStates_c_RX_QUIET 2 9831 #define sc_x1_speed_override1_cl36RxEEEStates_c_RX_SLEEP 1 9832 #define sc_x1_speed_override1_cl36RxEEEStates_c_RX_ACTIVE 0 9833 9834 /**************************************************************************** 9835 * Enums: sc_x1_speed_override1_cl49RxEEEStates_l 9836 */ 9837 #define sc_x1_speed_override1_cl49RxEEEStates_l_RX_LINK_FAIL 32 9838 #define sc_x1_speed_override1_cl49RxEEEStates_l_RX_WTF 16 9839 #define sc_x1_speed_override1_cl49RxEEEStates_l_RX_WAKE 8 9840 #define sc_x1_speed_override1_cl49RxEEEStates_l_RX_QUIET 4 9841 #define sc_x1_speed_override1_cl49RxEEEStates_l_RX_SLEEP 2 9842 #define sc_x1_speed_override1_cl49RxEEEStates_l_RX_ACTIVE 1 9843 9844 /**************************************************************************** 9845 * Enums: sc_x1_speed_override1_cl49RxEEEStates_c 9846 */ 9847 #define sc_x1_speed_override1_cl49RxEEEStates_c_RX_LINK_FAIL 5 9848 #define sc_x1_speed_override1_cl49RxEEEStates_c_RX_WTF 4 9849 #define sc_x1_speed_override1_cl49RxEEEStates_c_RX_WAKE 3 9850 #define sc_x1_speed_override1_cl49RxEEEStates_c_RX_QUIET 2 9851 #define sc_x1_speed_override1_cl49RxEEEStates_c_RX_SLEEP 1 9852 #define sc_x1_speed_override1_cl49RxEEEStates_c_RX_ACTIVE 0 9853 9854 /**************************************************************************** 9855 * Enums: sc_x1_speed_override1_cl48TxEEEStates_l 9856 */ 9857 #define sc_x1_speed_override1_cl48TxEEEStates_l_TX_REFRESH 8 9858 #define sc_x1_speed_override1_cl48TxEEEStates_l_TX_QUIET 4 9859 #define sc_x1_speed_override1_cl48TxEEEStates_l_TX_SLEEP 2 9860 #define sc_x1_speed_override1_cl48TxEEEStates_l_TX_ACTIVE 1 9861 9862 /**************************************************************************** 9863 * Enums: sc_x1_speed_override1_cl48TxEEEStates_c 9864 */ 9865 #define sc_x1_speed_override1_cl48TxEEEStates_c_TX_REFRESH 3 9866 #define sc_x1_speed_override1_cl48TxEEEStates_c_TX_QUIET 2 9867 #define sc_x1_speed_override1_cl48TxEEEStates_c_TX_SLEEP 1 9868 #define sc_x1_speed_override1_cl48TxEEEStates_c_TX_ACTIVE 0 9869 9870 /**************************************************************************** 9871 * Enums: sc_x1_speed_override1_cl48RxEEEStates_l 9872 */ 9873 #define sc_x1_speed_override1_cl48RxEEEStates_l_RX_LINK_FAIL 32 9874 #define sc_x1_speed_override1_cl48RxEEEStates_l_RX_WAKE 16 9875 #define sc_x1_speed_override1_cl48RxEEEStates_l_RX_QUIET 8 9876 #define sc_x1_speed_override1_cl48RxEEEStates_l_RX_DEACT 4 9877 #define sc_x1_speed_override1_cl48RxEEEStates_l_RX_SLEEP 2 9878 #define sc_x1_speed_override1_cl48RxEEEStates_l_RX_ACTIVE 1 9879 9880 /**************************************************************************** 9881 * Enums: sc_x1_speed_override1_cl48RxEEEStates_c 9882 */ 9883 #define sc_x1_speed_override1_cl48RxEEEStates_c_RX_LINK_FAIL 5 9884 #define sc_x1_speed_override1_cl48RxEEEStates_c_RX_WAKE 4 9885 #define sc_x1_speed_override1_cl48RxEEEStates_c_RX_QUIET 3 9886 #define sc_x1_speed_override1_cl48RxEEEStates_c_RX_DEACT 2 9887 #define sc_x1_speed_override1_cl48RxEEEStates_c_RX_SLEEP 1 9888 #define sc_x1_speed_override1_cl48RxEEEStates_c_RX_ACTIVE 0 9889 9890 /**************************************************************************** 9891 * Enums: sc_x1_speed_override1_IQP_Options 9892 */ 9893 #define sc_x1_speed_override1_IQP_Options_i50uA 0 9894 #define sc_x1_speed_override1_IQP_Options_i100uA 1 9895 #define sc_x1_speed_override1_IQP_Options_i150uA 2 9896 #define sc_x1_speed_override1_IQP_Options_i200uA 3 9897 #define sc_x1_speed_override1_IQP_Options_i250uA 4 9898 #define sc_x1_speed_override1_IQP_Options_i300uA 5 9899 #define sc_x1_speed_override1_IQP_Options_i350uA 6 9900 #define sc_x1_speed_override1_IQP_Options_i400uA 7 9901 #define sc_x1_speed_override1_IQP_Options_i450uA 8 9902 #define sc_x1_speed_override1_IQP_Options_i500uA 9 9903 #define sc_x1_speed_override1_IQP_Options_i550uA 10 9904 #define sc_x1_speed_override1_IQP_Options_i600uA 11 9905 #define sc_x1_speed_override1_IQP_Options_i650uA 12 9906 #define sc_x1_speed_override1_IQP_Options_i700uA 13 9907 #define sc_x1_speed_override1_IQP_Options_i750uA 14 9908 #define sc_x1_speed_override1_IQP_Options_i800uA 15 9909 9910 /**************************************************************************** 9911 * Enums: sc_x1_speed_override1_IDriver_Options 9912 */ 9913 #define sc_x1_speed_override1_IDriver_Options_v680mV 0 9914 #define sc_x1_speed_override1_IDriver_Options_v730mV 1 9915 #define sc_x1_speed_override1_IDriver_Options_v780mV 2 9916 #define sc_x1_speed_override1_IDriver_Options_v830mV 3 9917 #define sc_x1_speed_override1_IDriver_Options_v880mV 4 9918 #define sc_x1_speed_override1_IDriver_Options_v930mV 5 9919 #define sc_x1_speed_override1_IDriver_Options_v980mV 6 9920 #define sc_x1_speed_override1_IDriver_Options_v1010mV 7 9921 #define sc_x1_speed_override1_IDriver_Options_v1040mV 8 9922 #define sc_x1_speed_override1_IDriver_Options_v1060mV 9 9923 #define sc_x1_speed_override1_IDriver_Options_v1070mV 10 9924 #define sc_x1_speed_override1_IDriver_Options_v1080mV 11 9925 #define sc_x1_speed_override1_IDriver_Options_v1085mV 12 9926 #define sc_x1_speed_override1_IDriver_Options_v1090mV 13 9927 #define sc_x1_speed_override1_IDriver_Options_v1095mV 14 9928 #define sc_x1_speed_override1_IDriver_Options_v1100mV 15 9929 9930 /**************************************************************************** 9931 * Enums: sc_x1_speed_override1_operationModes 9932 */ 9933 #define sc_x1_speed_override1_operationModes_XGXS 0 9934 #define sc_x1_speed_override1_operationModes_XGXG_nCC 1 9935 #define sc_x1_speed_override1_operationModes_Indlane_OS8 4 9936 #define sc_x1_speed_override1_operationModes_IndLane_OS5 5 9937 #define sc_x1_speed_override1_operationModes_PCI 7 9938 #define sc_x1_speed_override1_operationModes_XGXS_nLQ 8 9939 #define sc_x1_speed_override1_operationModes_XGXS_nLQnCC 9 9940 #define sc_x1_speed_override1_operationModes_PBypass 10 9941 #define sc_x1_speed_override1_operationModes_PBypass_nDSK 11 9942 #define sc_x1_speed_override1_operationModes_ComboCoreMode 12 9943 #define sc_x1_speed_override1_operationModes_Clocks_off 15 9944 9945 /**************************************************************************** 9946 * Enums: sc_x1_speed_override1_actualSpeeds 9947 */ 9948 #define sc_x1_speed_override1_actualSpeeds_dr_10M 0 9949 #define sc_x1_speed_override1_actualSpeeds_dr_100M 1 9950 #define sc_x1_speed_override1_actualSpeeds_dr_1G 2 9951 #define sc_x1_speed_override1_actualSpeeds_dr_2p5G 3 9952 #define sc_x1_speed_override1_actualSpeeds_dr_5G_X4 4 9953 #define sc_x1_speed_override1_actualSpeeds_dr_6G_X4 5 9954 #define sc_x1_speed_override1_actualSpeeds_dr_10G_HiG 6 9955 #define sc_x1_speed_override1_actualSpeeds_dr_10G_CX4 7 9956 #define sc_x1_speed_override1_actualSpeeds_dr_12G_HiG 8 9957 #define sc_x1_speed_override1_actualSpeeds_dr_12p5G_X4 9 9958 #define sc_x1_speed_override1_actualSpeeds_dr_13G_X4 10 9959 #define sc_x1_speed_override1_actualSpeeds_dr_15G_X4 11 9960 #define sc_x1_speed_override1_actualSpeeds_dr_16G_X4 12 9961 #define sc_x1_speed_override1_actualSpeeds_dr_1G_KX 13 9962 #define sc_x1_speed_override1_actualSpeeds_dr_10G_KX4 14 9963 #define sc_x1_speed_override1_actualSpeeds_dr_10G_KR 15 9964 #define sc_x1_speed_override1_actualSpeeds_dr_5G 16 9965 #define sc_x1_speed_override1_actualSpeeds_dr_6p4G 17 9966 #define sc_x1_speed_override1_actualSpeeds_dr_20G_X4 18 9967 #define sc_x1_speed_override1_actualSpeeds_dr_21G_X4 19 9968 #define sc_x1_speed_override1_actualSpeeds_dr_25G_X4 20 9969 #define sc_x1_speed_override1_actualSpeeds_dr_10G_HiG_DXGXS 21 9970 #define sc_x1_speed_override1_actualSpeeds_dr_10G_DXGXS 22 9971 #define sc_x1_speed_override1_actualSpeeds_dr_10p5G_HiG_DXGXS 23 9972 #define sc_x1_speed_override1_actualSpeeds_dr_10p5G_DXGXS 24 9973 #define sc_x1_speed_override1_actualSpeeds_dr_12p773G_HiG_DXGXS 25 9974 #define sc_x1_speed_override1_actualSpeeds_dr_12p773G_DXGXS 26 9975 #define sc_x1_speed_override1_actualSpeeds_dr_10G_XFI 27 9976 #define sc_x1_speed_override1_actualSpeeds_dr_40G 28 9977 #define sc_x1_speed_override1_actualSpeeds_dr_20G_HiG_DXGXS 29 9978 #define sc_x1_speed_override1_actualSpeeds_dr_20G_DXGXS 30 9979 #define sc_x1_speed_override1_actualSpeeds_dr_10G_SFI 31 9980 #define sc_x1_speed_override1_actualSpeeds_dr_31p5G 32 9981 #define sc_x1_speed_override1_actualSpeeds_dr_32p7G 33 9982 #define sc_x1_speed_override1_actualSpeeds_dr_20G_SCR 34 9983 #define sc_x1_speed_override1_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 9984 #define sc_x1_speed_override1_actualSpeeds_dr_10G_DXGXS_SCR 36 9985 #define sc_x1_speed_override1_actualSpeeds_dr_12G_R2 37 9986 #define sc_x1_speed_override1_actualSpeeds_dr_10G_X2 38 9987 #define sc_x1_speed_override1_actualSpeeds_dr_40G_KR4 39 9988 #define sc_x1_speed_override1_actualSpeeds_dr_40G_CR4 40 9989 #define sc_x1_speed_override1_actualSpeeds_dr_100G_CR10 41 9990 #define sc_x1_speed_override1_actualSpeeds_dr_15p75G_DXGXS 44 9991 #define sc_x1_speed_override1_actualSpeeds_dr_20G_KR2 57 9992 #define sc_x1_speed_override1_actualSpeeds_dr_20G_CR2 58 9993 9994 /**************************************************************************** 9995 * Enums: sc_x1_speed_override1_actualSpeedsMisc1 9996 */ 9997 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_2500BRCM_X1 16 9998 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_5000BRCM_X4 17 9999 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_6000BRCM_X4 18 10000 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_10GHiGig_X4 19 10001 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_10GBASE_CX4 20 10002 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_12GHiGig_X4 21 10003 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 10004 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_13GHiGig_X4 23 10005 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_15GHiGig_X4 24 10006 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_16GHiGig_X4 25 10007 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_5000BRCM_X1 26 10008 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_6363BRCM_X1 27 10009 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_20GHiGig_X4 28 10010 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_21GHiGig_X4 29 10011 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 10012 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 10013 10014 /**************************************************************************** 10015 * Enums: sc_x1_speed_override1_IndLaneModes 10016 */ 10017 #define sc_x1_speed_override1_IndLaneModes_SWSDR_div2 0 10018 #define sc_x1_speed_override1_IndLaneModes_SWSDR_div1 1 10019 #define sc_x1_speed_override1_IndLaneModes_DWSDR_div2 2 10020 #define sc_x1_speed_override1_IndLaneModes_DWSDR_div1 3 10021 10022 /**************************************************************************** 10023 * Enums: sc_x1_speed_override1_prbsSelect 10024 */ 10025 #define sc_x1_speed_override1_prbsSelect_prbs7 0 10026 #define sc_x1_speed_override1_prbsSelect_prbs15 1 10027 #define sc_x1_speed_override1_prbsSelect_prbs23 2 10028 #define sc_x1_speed_override1_prbsSelect_prbs31 3 10029 10030 /**************************************************************************** 10031 * Enums: sc_x1_speed_override1_vcoDivider 10032 */ 10033 #define sc_x1_speed_override1_vcoDivider_div32 0 10034 #define sc_x1_speed_override1_vcoDivider_div36 1 10035 #define sc_x1_speed_override1_vcoDivider_div40 2 10036 #define sc_x1_speed_override1_vcoDivider_div42 3 10037 #define sc_x1_speed_override1_vcoDivider_div48 4 10038 #define sc_x1_speed_override1_vcoDivider_div50 5 10039 #define sc_x1_speed_override1_vcoDivider_div52 6 10040 #define sc_x1_speed_override1_vcoDivider_div54 7 10041 #define sc_x1_speed_override1_vcoDivider_div60 8 10042 #define sc_x1_speed_override1_vcoDivider_div64 9 10043 #define sc_x1_speed_override1_vcoDivider_div66 10 10044 #define sc_x1_speed_override1_vcoDivider_div68 11 10045 #define sc_x1_speed_override1_vcoDivider_div70 12 10046 #define sc_x1_speed_override1_vcoDivider_div80 13 10047 #define sc_x1_speed_override1_vcoDivider_div92 14 10048 #define sc_x1_speed_override1_vcoDivider_div100 15 10049 10050 /**************************************************************************** 10051 * Enums: sc_x1_speed_override1_refClkSelect 10052 */ 10053 #define sc_x1_speed_override1_refClkSelect_clk_25MHz 0 10054 #define sc_x1_speed_override1_refClkSelect_clk_100MHz 1 10055 #define sc_x1_speed_override1_refClkSelect_clk_125MHz 2 10056 #define sc_x1_speed_override1_refClkSelect_clk_156p25MHz 3 10057 #define sc_x1_speed_override1_refClkSelect_clk_187p5MHz 4 10058 #define sc_x1_speed_override1_refClkSelect_clk_161p25Mhz 5 10059 #define sc_x1_speed_override1_refClkSelect_clk_50Mhz 6 10060 #define sc_x1_speed_override1_refClkSelect_clk_106p25Mhz 7 10061 10062 /**************************************************************************** 10063 * Enums: sc_x1_speed_override1_aerMMDdevTypeSelect 10064 */ 10065 #define sc_x1_speed_override1_aerMMDdevTypeSelect_combo_core 0 10066 #define sc_x1_speed_override1_aerMMDdevTypeSelect_PMA_PMD 1 10067 #define sc_x1_speed_override1_aerMMDdevTypeSelect_PCS 3 10068 #define sc_x1_speed_override1_aerMMDdevTypeSelect_PHY 4 10069 #define sc_x1_speed_override1_aerMMDdevTypeSelect_DTE 5 10070 #define sc_x1_speed_override1_aerMMDdevTypeSelect_CL73_AN 7 10071 10072 /**************************************************************************** 10073 * Enums: sc_x1_speed_override1_aerMMDportSelect 10074 */ 10075 #define sc_x1_speed_override1_aerMMDportSelect_ln0 0 10076 #define sc_x1_speed_override1_aerMMDportSelect_ln1 1 10077 #define sc_x1_speed_override1_aerMMDportSelect_ln2 2 10078 #define sc_x1_speed_override1_aerMMDportSelect_ln3 3 10079 #define sc_x1_speed_override1_aerMMDportSelect_BCST_ln0_1_2_3 511 10080 #define sc_x1_speed_override1_aerMMDportSelect_BCST_ln0_1 512 10081 #define sc_x1_speed_override1_aerMMDportSelect_BCST_ln2_3 513 10082 10083 /**************************************************************************** 10084 * Enums: sc_x1_speed_override1_firmwareModeSelect 10085 */ 10086 #define sc_x1_speed_override1_firmwareModeSelect_DEFAULT 0 10087 #define sc_x1_speed_override1_firmwareModeSelect_SFP_OPT_LR 1 10088 #define sc_x1_speed_override1_firmwareModeSelect_SFP_DAC 2 10089 #define sc_x1_speed_override1_firmwareModeSelect_XLAUI 3 10090 #define sc_x1_speed_override1_firmwareModeSelect_LONG_CH_6G 4 10091 10092 /**************************************************************************** 10093 * Enums: sc_x1_speed_override1_tempIdxSelect 10094 */ 10095 #define sc_x1_speed_override1_tempIdxSelect_LTE__22p9C 15 10096 #define sc_x1_speed_override1_tempIdxSelect_LTE__12p6C 14 10097 #define sc_x1_speed_override1_tempIdxSelect_LTE__3p0C 13 10098 #define sc_x1_speed_override1_tempIdxSelect_LTE_6p7C 12 10099 #define sc_x1_speed_override1_tempIdxSelect_LTE_16p4C 11 10100 #define sc_x1_speed_override1_tempIdxSelect_LTE_26p6C 10 10101 #define sc_x1_speed_override1_tempIdxSelect_LTE_36p3C 9 10102 #define sc_x1_speed_override1_tempIdxSelect_LTE_46p0C 8 10103 #define sc_x1_speed_override1_tempIdxSelect_LTE_56p2C 7 10104 #define sc_x1_speed_override1_tempIdxSelect_LTE_65p9C 6 10105 #define sc_x1_speed_override1_tempIdxSelect_LTE_75p6C 5 10106 #define sc_x1_speed_override1_tempIdxSelect_LTE_85p3C 4 10107 #define sc_x1_speed_override1_tempIdxSelect_LTE_95p5C 3 10108 #define sc_x1_speed_override1_tempIdxSelect_LTE_105p2C 2 10109 #define sc_x1_speed_override1_tempIdxSelect_LTE_114p9C 1 10110 #define sc_x1_speed_override1_tempIdxSelect_LTE_125p1C 0 10111 10112 /**************************************************************************** 10113 * Enums: sc_x1_speed_override1_port_mode 10114 */ 10115 #define sc_x1_speed_override1_port_mode_QUAD_PORT 0 10116 #define sc_x1_speed_override1_port_mode_TRI_1_PORT 1 10117 #define sc_x1_speed_override1_port_mode_TRI_2_PORT 2 10118 #define sc_x1_speed_override1_port_mode_DUAL_PORT 3 10119 #define sc_x1_speed_override1_port_mode_SINGLE_PORT 4 10120 10121 /**************************************************************************** 10122 * Enums: sc_x1_speed_override1_rev_letter_enum 10123 */ 10124 #define sc_x1_speed_override1_rev_letter_enum_REV_A 0 10125 #define sc_x1_speed_override1_rev_letter_enum_REV_B 1 10126 #define sc_x1_speed_override1_rev_letter_enum_REV_C 2 10127 #define sc_x1_speed_override1_rev_letter_enum_REV_D 3 10128 10129 /**************************************************************************** 10130 * Enums: sc_x1_speed_override1_rev_number_enum 10131 */ 10132 #define sc_x1_speed_override1_rev_number_enum_REV_0 0 10133 #define sc_x1_speed_override1_rev_number_enum_REV_1 1 10134 #define sc_x1_speed_override1_rev_number_enum_REV_2 2 10135 #define sc_x1_speed_override1_rev_number_enum_REV_3 3 10136 #define sc_x1_speed_override1_rev_number_enum_REV_4 4 10137 #define sc_x1_speed_override1_rev_number_enum_REV_5 5 10138 #define sc_x1_speed_override1_rev_number_enum_REV_6 6 10139 #define sc_x1_speed_override1_rev_number_enum_REV_7 7 10140 10141 /**************************************************************************** 10142 * Enums: sc_x1_speed_override1_bonding_enum 10143 */ 10144 #define sc_x1_speed_override1_bonding_enum_WIRE_BOND 0 10145 #define sc_x1_speed_override1_bonding_enum_FLIP_CHIP 1 10146 10147 /**************************************************************************** 10148 * Enums: sc_x1_speed_override1_tech_process 10149 */ 10150 #define sc_x1_speed_override1_tech_process_PROCESS_90NM 0 10151 #define sc_x1_speed_override1_tech_process_PROCESS_65NM 1 10152 #define sc_x1_speed_override1_tech_process_PROCESS_40NM 2 10153 #define sc_x1_speed_override1_tech_process_PROCESS_28NM 3 10154 10155 /**************************************************************************** 10156 * Enums: sc_x1_speed_override1_model_num 10157 */ 10158 #define sc_x1_speed_override1_model_num_SERDES_CL73 0 10159 #define sc_x1_speed_override1_model_num_XGXS_16G 1 10160 #define sc_x1_speed_override1_model_num_HYPERCORE 2 10161 #define sc_x1_speed_override1_model_num_HYPERLITE 3 10162 #define sc_x1_speed_override1_model_num_PCIE_G2_PIPE 4 10163 #define sc_x1_speed_override1_model_num_SERDES_1p25GBd 5 10164 #define sc_x1_speed_override1_model_num_SATA2 6 10165 #define sc_x1_speed_override1_model_num_QSGMII 7 10166 #define sc_x1_speed_override1_model_num_XGXS10G 8 10167 #define sc_x1_speed_override1_model_num_WARPCORE 9 10168 #define sc_x1_speed_override1_model_num_XFICORE 10 10169 #define sc_x1_speed_override1_model_num_RXFI 11 10170 #define sc_x1_speed_override1_model_num_WARPLITE 12 10171 #define sc_x1_speed_override1_model_num_PENTACORE 13 10172 #define sc_x1_speed_override1_model_num_ESM 14 10173 #define sc_x1_speed_override1_model_num_QUAD_SGMII 15 10174 #define sc_x1_speed_override1_model_num_WARPCORE_3 16 10175 #define sc_x1_speed_override1_model_num_TSC 17 10176 #define sc_x1_speed_override1_model_num_TSC4E 18 10177 #define sc_x1_speed_override1_model_num_TSC12E 19 10178 #define sc_x1_speed_override1_model_num_TSC4F 20 10179 #define sc_x1_speed_override1_model_num_XGXS_CL73_90NM 29 10180 #define sc_x1_speed_override1_model_num_SERDES_CL73_90NM 30 10181 #define sc_x1_speed_override1_model_num_WARPCORE3 32 10182 #define sc_x1_speed_override1_model_num_WARPCORE4_TSC 33 10183 #define sc_x1_speed_override1_model_num_RXAUI 34 10184 10185 /**************************************************************************** 10186 * Enums: sc_x1_speed_override1_payload 10187 */ 10188 #define sc_x1_speed_override1_payload_REPEAT_2_BYTES 0 10189 #define sc_x1_speed_override1_payload_RAMPING 1 10190 #define sc_x1_speed_override1_payload_CL48_CRPAT 2 10191 #define sc_x1_speed_override1_payload_CL48_CJPAT 3 10192 #define sc_x1_speed_override1_payload_CL36_LONG_CRPAT 4 10193 #define sc_x1_speed_override1_payload_CL36_SHORT_CRPAT 5 10194 10195 /**************************************************************************** 10196 * Enums: sc_x1_speed_override1_sc 10197 */ 10198 #define sc_x1_speed_override1_sc_S_10G_CR1 0 10199 #define sc_x1_speed_override1_sc_S_10G_KR1 1 10200 #define sc_x1_speed_override1_sc_S_10G_X1 2 10201 #define sc_x1_speed_override1_sc_S_10G_HG2_CR1 4 10202 #define sc_x1_speed_override1_sc_S_10G_HG2_KR1 5 10203 #define sc_x1_speed_override1_sc_S_10G_HG2_X1 6 10204 #define sc_x1_speed_override1_sc_S_20G_CR1 8 10205 #define sc_x1_speed_override1_sc_S_20G_KR1 9 10206 #define sc_x1_speed_override1_sc_S_20G_X1 10 10207 #define sc_x1_speed_override1_sc_S_20G_HG2_CR1 12 10208 #define sc_x1_speed_override1_sc_S_20G_HG2_KR1 13 10209 #define sc_x1_speed_override1_sc_S_20G_HG2_X1 14 10210 #define sc_x1_speed_override1_sc_S_25G_CR1 16 10211 #define sc_x1_speed_override1_sc_S_25G_KR1 17 10212 #define sc_x1_speed_override1_sc_S_25G_X1 18 10213 #define sc_x1_speed_override1_sc_S_25G_HG2_CR1 20 10214 #define sc_x1_speed_override1_sc_S_25G_HG2_KR1 21 10215 #define sc_x1_speed_override1_sc_S_25G_HG2_X1 22 10216 #define sc_x1_speed_override1_sc_S_20G_CR2 24 10217 #define sc_x1_speed_override1_sc_S_20G_KR2 25 10218 #define sc_x1_speed_override1_sc_S_20G_X2 26 10219 #define sc_x1_speed_override1_sc_S_20G_HG2_CR2 28 10220 #define sc_x1_speed_override1_sc_S_20G_HG2_KR2 29 10221 #define sc_x1_speed_override1_sc_S_20G_HG2_X2 30 10222 #define sc_x1_speed_override1_sc_S_40G_CR2 32 10223 #define sc_x1_speed_override1_sc_S_40G_KR2 33 10224 #define sc_x1_speed_override1_sc_S_40G_X2 34 10225 #define sc_x1_speed_override1_sc_S_40G_HG2_CR2 36 10226 #define sc_x1_speed_override1_sc_S_40G_HG2_KR2 37 10227 #define sc_x1_speed_override1_sc_S_40G_HG2_X2 38 10228 #define sc_x1_speed_override1_sc_S_40G_CR4 40 10229 #define sc_x1_speed_override1_sc_S_40G_KR4 41 10230 #define sc_x1_speed_override1_sc_S_40G_X4 42 10231 #define sc_x1_speed_override1_sc_S_40G_HG2_CR4 44 10232 #define sc_x1_speed_override1_sc_S_40G_HG2_KR4 45 10233 #define sc_x1_speed_override1_sc_S_40G_HG2_X4 46 10234 #define sc_x1_speed_override1_sc_S_50G_CR2 48 10235 #define sc_x1_speed_override1_sc_S_50G_KR2 49 10236 #define sc_x1_speed_override1_sc_S_50G_X2 50 10237 #define sc_x1_speed_override1_sc_S_50G_HG2_CR2 52 10238 #define sc_x1_speed_override1_sc_S_50G_HG2_KR2 53 10239 #define sc_x1_speed_override1_sc_S_50G_HG2_X2 54 10240 #define sc_x1_speed_override1_sc_S_50G_CR4 56 10241 #define sc_x1_speed_override1_sc_S_50G_KR4 57 10242 #define sc_x1_speed_override1_sc_S_50G_X4 58 10243 #define sc_x1_speed_override1_sc_S_50G_HG2_CR4 60 10244 #define sc_x1_speed_override1_sc_S_50G_HG2_KR4 61 10245 #define sc_x1_speed_override1_sc_S_50G_HG2_X4 62 10246 #define sc_x1_speed_override1_sc_S_100G_CR4 64 10247 #define sc_x1_speed_override1_sc_S_100G_KR4 65 10248 #define sc_x1_speed_override1_sc_S_100G_X4 66 10249 #define sc_x1_speed_override1_sc_S_100G_HG2_CR4 68 10250 #define sc_x1_speed_override1_sc_S_100G_HG2_KR4 69 10251 #define sc_x1_speed_override1_sc_S_100G_HG2_X4 70 10252 #define sc_x1_speed_override1_sc_S_CL73_20GVCO 72 10253 #define sc_x1_speed_override1_sc_S_CL73_25GVCO 80 10254 #define sc_x1_speed_override1_sc_S_CL36_20GVCO 88 10255 #define sc_x1_speed_override1_sc_S_CL36_25GVCO 96 10256 10257 /**************************************************************************** 10258 * Enums: sc_x1_speed_override1_t_fifo_modes 10259 */ 10260 #define sc_x1_speed_override1_t_fifo_modes_T_FIFO_MODE_BYPASS 0 10261 #define sc_x1_speed_override1_t_fifo_modes_T_FIFO_MODE_40G 1 10262 #define sc_x1_speed_override1_t_fifo_modes_T_FIFO_MODE_100G 2 10263 #define sc_x1_speed_override1_t_fifo_modes_T_FIFO_MODE_20G 3 10264 10265 /**************************************************************************** 10266 * Enums: sc_x1_speed_override1_t_enc_modes 10267 */ 10268 #define sc_x1_speed_override1_t_enc_modes_T_ENC_MODE_BYPASS 0 10269 #define sc_x1_speed_override1_t_enc_modes_T_ENC_MODE_CL49 1 10270 #define sc_x1_speed_override1_t_enc_modes_T_ENC_MODE_CL82 2 10271 10272 /**************************************************************************** 10273 * Enums: sc_x1_speed_override1_btmx_mode 10274 */ 10275 #define sc_x1_speed_override1_btmx_mode_BS_BTMX_MODE_1to1 0 10276 #define sc_x1_speed_override1_btmx_mode_BS_BTMX_MODE_2to1 1 10277 #define sc_x1_speed_override1_btmx_mode_BS_BTMX_MODE_5to1 2 10278 10279 /**************************************************************************** 10280 * Enums: sc_x1_speed_override1_t_type_cl82 10281 */ 10282 #define sc_x1_speed_override1_t_type_cl82_T_TYPE_B1 5 10283 #define sc_x1_speed_override1_t_type_cl82_T_TYPE_C 4 10284 #define sc_x1_speed_override1_t_type_cl82_T_TYPE_S 3 10285 #define sc_x1_speed_override1_t_type_cl82_T_TYPE_T 2 10286 #define sc_x1_speed_override1_t_type_cl82_T_TYPE_D 1 10287 #define sc_x1_speed_override1_t_type_cl82_T_TYPE_E 0 10288 10289 /**************************************************************************** 10290 * Enums: sc_x1_speed_override1_txsm_state_cl82 10291 */ 10292 #define sc_x1_speed_override1_txsm_state_cl82_TX_HIG_END 6 10293 #define sc_x1_speed_override1_txsm_state_cl82_TX_HIG_START 5 10294 #define sc_x1_speed_override1_txsm_state_cl82_TX_E 4 10295 #define sc_x1_speed_override1_txsm_state_cl82_TX_T 3 10296 #define sc_x1_speed_override1_txsm_state_cl82_TX_D 2 10297 #define sc_x1_speed_override1_txsm_state_cl82_TX_C 1 10298 #define sc_x1_speed_override1_txsm_state_cl82_TX_INIT 0 10299 10300 /**************************************************************************** 10301 * Enums: sc_x1_speed_override1_ltxsm_state_cl82 10302 */ 10303 #define sc_x1_speed_override1_ltxsm_state_cl82_TX_HIG_END 64 10304 #define sc_x1_speed_override1_ltxsm_state_cl82_TX_HIG_START 32 10305 #define sc_x1_speed_override1_ltxsm_state_cl82_TX_E 16 10306 #define sc_x1_speed_override1_ltxsm_state_cl82_TX_T 8 10307 #define sc_x1_speed_override1_ltxsm_state_cl82_TX_D 4 10308 #define sc_x1_speed_override1_ltxsm_state_cl82_TX_C 2 10309 #define sc_x1_speed_override1_ltxsm_state_cl82_TX_INIT 1 10310 10311 /**************************************************************************** 10312 * Enums: sc_x1_speed_override1_r_type_coded_cl82 10313 */ 10314 #define sc_x1_speed_override1_r_type_coded_cl82_R_TYPE_B1 32 10315 #define sc_x1_speed_override1_r_type_coded_cl82_R_TYPE_C 16 10316 #define sc_x1_speed_override1_r_type_coded_cl82_R_TYPE_S 8 10317 #define sc_x1_speed_override1_r_type_coded_cl82_R_TYPE_T 4 10318 #define sc_x1_speed_override1_r_type_coded_cl82_R_TYPE_D 2 10319 #define sc_x1_speed_override1_r_type_coded_cl82_R_TYPE_E 1 10320 10321 /**************************************************************************** 10322 * Enums: sc_x1_speed_override1_rxsm_state_cl82 10323 */ 10324 #define sc_x1_speed_override1_rxsm_state_cl82_RX_HIG_END 64 10325 #define sc_x1_speed_override1_rxsm_state_cl82_RX_HIG_START 32 10326 #define sc_x1_speed_override1_rxsm_state_cl82_RX_E 16 10327 #define sc_x1_speed_override1_rxsm_state_cl82_RX_T 8 10328 #define sc_x1_speed_override1_rxsm_state_cl82_RX_D 4 10329 #define sc_x1_speed_override1_rxsm_state_cl82_RX_C 2 10330 #define sc_x1_speed_override1_rxsm_state_cl82_RX_INIT 1 10331 10332 /**************************************************************************** 10333 * Enums: sc_x1_speed_override1_deskew_state 10334 */ 10335 #define sc_x1_speed_override1_deskew_state_ALIGN_ACQUIRED 2 10336 #define sc_x1_speed_override1_deskew_state_LOSS_OF_ALIGNMENT 1 10337 10338 /**************************************************************************** 10339 * Enums: sc_x1_speed_override1_os_mode_enum 10340 */ 10341 #define sc_x1_speed_override1_os_mode_enum_OS_MODE_1 0 10342 #define sc_x1_speed_override1_os_mode_enum_OS_MODE_2 1 10343 #define sc_x1_speed_override1_os_mode_enum_OS_MODE_4 2 10344 #define sc_x1_speed_override1_os_mode_enum_OS_MODE_16p5 8 10345 #define sc_x1_speed_override1_os_mode_enum_OS_MODE_20p625 12 10346 10347 /**************************************************************************** 10348 * Enums: sc_x1_speed_override1_scr_modes 10349 */ 10350 #define sc_x1_speed_override1_scr_modes_T_SCR_MODE_BYPASS 0 10351 #define sc_x1_speed_override1_scr_modes_T_SCR_MODE_CL49 1 10352 #define sc_x1_speed_override1_scr_modes_T_SCR_MODE_40G_2_LANE 2 10353 #define sc_x1_speed_override1_scr_modes_T_SCR_MODE_100G 3 10354 #define sc_x1_speed_override1_scr_modes_T_SCR_MODE_20G 4 10355 #define sc_x1_speed_override1_scr_modes_T_SCR_MODE_40G_4_LANE 5 10356 10357 /**************************************************************************** 10358 * Enums: sc_x1_speed_override1_descr_modes 10359 */ 10360 #define sc_x1_speed_override1_descr_modes_R_DESCR_MODE_BYPASS 0 10361 #define sc_x1_speed_override1_descr_modes_R_DESCR_MODE_CL49 1 10362 #define sc_x1_speed_override1_descr_modes_R_DESCR_MODE_CL82 2 10363 10364 /**************************************************************************** 10365 * Enums: sc_x1_speed_override1_r_dec_tl_mode 10366 */ 10367 #define sc_x1_speed_override1_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 10368 #define sc_x1_speed_override1_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 10369 #define sc_x1_speed_override1_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 10370 10371 /**************************************************************************** 10372 * Enums: sc_x1_speed_override1_r_dec_fsm_mode 10373 */ 10374 #define sc_x1_speed_override1_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 10375 #define sc_x1_speed_override1_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 10376 #define sc_x1_speed_override1_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 10377 10378 /**************************************************************************** 10379 * Enums: sc_x1_speed_override1_r_deskew_mode 10380 */ 10381 #define sc_x1_speed_override1_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 10382 #define sc_x1_speed_override1_r_deskew_mode_R_DESKEW_MODE_20G 1 10383 #define sc_x1_speed_override1_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 10384 #define sc_x1_speed_override1_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 10385 #define sc_x1_speed_override1_r_deskew_mode_R_DESKEW_MODE_100G 4 10386 #define sc_x1_speed_override1_r_deskew_mode_R_DESKEW_MODE_CL49 5 10387 #define sc_x1_speed_override1_r_deskew_mode_R_DESKEW_MODE_CL91 6 10388 10389 /**************************************************************************** 10390 * Enums: sc_x1_speed_override1_bs_dist_modes 10391 */ 10392 #define sc_x1_speed_override1_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 10393 #define sc_x1_speed_override1_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 10394 #define sc_x1_speed_override1_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 10395 #define sc_x1_speed_override1_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 10396 10397 /**************************************************************************** 10398 * Enums: sc_x1_speed_override1_cl49_t_type 10399 */ 10400 #define sc_x1_speed_override1_cl49_t_type_BAD_T_TYPE 15 10401 #define sc_x1_speed_override1_cl49_t_type_T_TYPE_B0 11 10402 #define sc_x1_speed_override1_cl49_t_type_T_TYPE_OB 10 10403 #define sc_x1_speed_override1_cl49_t_type_T_TYPE_B1 9 10404 #define sc_x1_speed_override1_cl49_t_type_T_TYPE_DB 8 10405 #define sc_x1_speed_override1_cl49_t_type_T_TYPE_FC 7 10406 #define sc_x1_speed_override1_cl49_t_type_T_TYPE_TB 6 10407 #define sc_x1_speed_override1_cl49_t_type_T_TYPE_LI 5 10408 #define sc_x1_speed_override1_cl49_t_type_T_TYPE_C 4 10409 #define sc_x1_speed_override1_cl49_t_type_T_TYPE_S 3 10410 #define sc_x1_speed_override1_cl49_t_type_T_TYPE_T 2 10411 #define sc_x1_speed_override1_cl49_t_type_T_TYPE_D 1 10412 #define sc_x1_speed_override1_cl49_t_type_T_TYPE_E 0 10413 10414 /**************************************************************************** 10415 * Enums: sc_x1_speed_override1_cl49_txsm_states 10416 */ 10417 #define sc_x1_speed_override1_cl49_txsm_states_TX_HIG_END 7 10418 #define sc_x1_speed_override1_cl49_txsm_states_TX_HIG_START 6 10419 #define sc_x1_speed_override1_cl49_txsm_states_TX_LI 5 10420 #define sc_x1_speed_override1_cl49_txsm_states_TX_E 4 10421 #define sc_x1_speed_override1_cl49_txsm_states_TX_T 3 10422 #define sc_x1_speed_override1_cl49_txsm_states_TX_D 2 10423 #define sc_x1_speed_override1_cl49_txsm_states_TX_C 1 10424 #define sc_x1_speed_override1_cl49_txsm_states_TX_INIT 0 10425 10426 /**************************************************************************** 10427 * Enums: sc_x1_speed_override1_cl49_ltxsm_states 10428 */ 10429 #define sc_x1_speed_override1_cl49_ltxsm_states_TX_HIG_END 128 10430 #define sc_x1_speed_override1_cl49_ltxsm_states_TX_HIG_START 64 10431 #define sc_x1_speed_override1_cl49_ltxsm_states_TX_LI 32 10432 #define sc_x1_speed_override1_cl49_ltxsm_states_TX_E 16 10433 #define sc_x1_speed_override1_cl49_ltxsm_states_TX_T 8 10434 #define sc_x1_speed_override1_cl49_ltxsm_states_TX_D 4 10435 #define sc_x1_speed_override1_cl49_ltxsm_states_TX_C 2 10436 #define sc_x1_speed_override1_cl49_ltxsm_states_TX_INIT 1 10437 10438 /**************************************************************************** 10439 * Enums: sc_x1_speed_override1_burst_error_mode 10440 */ 10441 #define sc_x1_speed_override1_burst_error_mode_BURST_ERROR_11_BITS 0 10442 #define sc_x1_speed_override1_burst_error_mode_BURST_ERROR_16_BITS 1 10443 #define sc_x1_speed_override1_burst_error_mode_BURST_ERROR_17_BITS 2 10444 #define sc_x1_speed_override1_burst_error_mode_BURST_ERROR_18_BITS 3 10445 #define sc_x1_speed_override1_burst_error_mode_BURST_ERROR_19_BITS 4 10446 #define sc_x1_speed_override1_burst_error_mode_BURST_ERROR_20_BITS 5 10447 #define sc_x1_speed_override1_burst_error_mode_BURST_ERROR_21_BITS 6 10448 #define sc_x1_speed_override1_burst_error_mode_BURST_ERROR_22_BITS 7 10449 #define sc_x1_speed_override1_burst_error_mode_BURST_ERROR_23_BITS 8 10450 #define sc_x1_speed_override1_burst_error_mode_BURST_ERROR_24_BITS 9 10451 #define sc_x1_speed_override1_burst_error_mode_BURST_ERROR_25_BITS 10 10452 #define sc_x1_speed_override1_burst_error_mode_BURST_ERROR_26_BITS 11 10453 #define sc_x1_speed_override1_burst_error_mode_BURST_ERROR_27_BITS 12 10454 #define sc_x1_speed_override1_burst_error_mode_BURST_ERROR_28_BITS 13 10455 #define sc_x1_speed_override1_burst_error_mode_BURST_ERROR_29_BITS 14 10456 #define sc_x1_speed_override1_burst_error_mode_BURST_ERROR_30_BITS 15 10457 #define sc_x1_speed_override1_burst_error_mode_BURST_ERROR_31_BITS 16 10458 #define sc_x1_speed_override1_burst_error_mode_BURST_ERROR_32_BITS 17 10459 #define sc_x1_speed_override1_burst_error_mode_BURST_ERROR_33_BITS 18 10460 #define sc_x1_speed_override1_burst_error_mode_BURST_ERROR_34_BITS 19 10461 #define sc_x1_speed_override1_burst_error_mode_BURST_ERROR_35_BITS 20 10462 #define sc_x1_speed_override1_burst_error_mode_BURST_ERROR_36_BITS 21 10463 #define sc_x1_speed_override1_burst_error_mode_BURST_ERROR_37_BITS 22 10464 #define sc_x1_speed_override1_burst_error_mode_BURST_ERROR_38_BITS 23 10465 #define sc_x1_speed_override1_burst_error_mode_BURST_ERROR_39_BITS 24 10466 #define sc_x1_speed_override1_burst_error_mode_BURST_ERROR_40_BITS 25 10467 #define sc_x1_speed_override1_burst_error_mode_BURST_ERROR_41_BITS 26 10468 10469 /**************************************************************************** 10470 * Enums: sc_x1_speed_override1_bermon_state 10471 */ 10472 #define sc_x1_speed_override1_bermon_state_HI_BER 4 10473 #define sc_x1_speed_override1_bermon_state_GOOD_BER 3 10474 #define sc_x1_speed_override1_bermon_state_BER_TEST_SH 2 10475 #define sc_x1_speed_override1_bermon_state_START_TIMER 1 10476 #define sc_x1_speed_override1_bermon_state_BER_MT_INIT 0 10477 10478 /**************************************************************************** 10479 * Enums: sc_x1_speed_override1_rxsm_state_cl49 10480 */ 10481 #define sc_x1_speed_override1_rxsm_state_cl49_RX_HIG_END 128 10482 #define sc_x1_speed_override1_rxsm_state_cl49_RX_HIG_START 64 10483 #define sc_x1_speed_override1_rxsm_state_cl49_RX_LI 32 10484 #define sc_x1_speed_override1_rxsm_state_cl49_RX_E 16 10485 #define sc_x1_speed_override1_rxsm_state_cl49_RX_T 8 10486 #define sc_x1_speed_override1_rxsm_state_cl49_RX_D 4 10487 #define sc_x1_speed_override1_rxsm_state_cl49_RX_C 2 10488 #define sc_x1_speed_override1_rxsm_state_cl49_RX_INIT 1 10489 10490 /**************************************************************************** 10491 * Enums: sc_x1_speed_override1_r_type 10492 */ 10493 #define sc_x1_speed_override1_r_type_BAD_R_TYPE 15 10494 #define sc_x1_speed_override1_r_type_R_TYPE_B0 11 10495 #define sc_x1_speed_override1_r_type_R_TYPE_OB 10 10496 #define sc_x1_speed_override1_r_type_R_TYPE_B1 9 10497 #define sc_x1_speed_override1_r_type_R_TYPE_DB 8 10498 #define sc_x1_speed_override1_r_type_R_TYPE_FC 7 10499 #define sc_x1_speed_override1_r_type_R_TYPE_TB 6 10500 #define sc_x1_speed_override1_r_type_R_TYPE_LI 5 10501 #define sc_x1_speed_override1_r_type_R_TYPE_C 4 10502 #define sc_x1_speed_override1_r_type_R_TYPE_S 3 10503 #define sc_x1_speed_override1_r_type_R_TYPE_T 2 10504 #define sc_x1_speed_override1_r_type_R_TYPE_D 1 10505 #define sc_x1_speed_override1_r_type_R_TYPE_E 0 10506 10507 /**************************************************************************** 10508 * Enums: sc_x1_speed_override1_am_lock_state 10509 */ 10510 #define sc_x1_speed_override1_am_lock_state_INVALID_AM 512 10511 #define sc_x1_speed_override1_am_lock_state_GOOD_AM 256 10512 #define sc_x1_speed_override1_am_lock_state_COMP_AM 128 10513 #define sc_x1_speed_override1_am_lock_state_TIMER_2 64 10514 #define sc_x1_speed_override1_am_lock_state_AM_2_GOOD 32 10515 #define sc_x1_speed_override1_am_lock_state_COMP_2ND 16 10516 #define sc_x1_speed_override1_am_lock_state_TIMER_1 8 10517 #define sc_x1_speed_override1_am_lock_state_FIND_1ST 4 10518 #define sc_x1_speed_override1_am_lock_state_AM_RESET_CNT 2 10519 #define sc_x1_speed_override1_am_lock_state_AM_LOCK_INIT 1 10520 10521 /**************************************************************************** 10522 * Enums: sc_x1_speed_override1_msg_selector 10523 */ 10524 #define sc_x1_speed_override1_msg_selector_RESERVED 0 10525 #define sc_x1_speed_override1_msg_selector_VALUE_802p3 1 10526 #define sc_x1_speed_override1_msg_selector_VALUE_802p9 2 10527 #define sc_x1_speed_override1_msg_selector_VALUE_802p5 3 10528 #define sc_x1_speed_override1_msg_selector_VALUE_1394 4 10529 10530 /**************************************************************************** 10531 * Enums: sc_x1_speed_override1_synce_enum 10532 */ 10533 #define sc_x1_speed_override1_synce_enum_SYNCE_NO_DIV 0 10534 #define sc_x1_speed_override1_synce_enum_SYNCE_DIV_7 1 10535 #define sc_x1_speed_override1_synce_enum_SYNCE_DIV_11 2 10536 10537 /**************************************************************************** 10538 * Enums: sc_x1_speed_override1_synce_enum_stage0 10539 */ 10540 #define sc_x1_speed_override1_synce_enum_stage0_SYNCE_NO_DIV 0 10541 #define sc_x1_speed_override1_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 10542 #define sc_x1_speed_override1_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 10543 10544 /**************************************************************************** 10545 * Enums: sc_x1_speed_override1_cl91_sync_state 10546 */ 10547 #define sc_x1_speed_override1_cl91_sync_state_FIND_1ST 0 10548 #define sc_x1_speed_override1_cl91_sync_state_COUNT_NEXT 1 10549 #define sc_x1_speed_override1_cl91_sync_state_COMP_2ND 2 10550 #define sc_x1_speed_override1_cl91_sync_state_TWO_GOOD 3 10551 10552 /**************************************************************************** 10553 * Enums: sc_x1_speed_override1_cl91_algn_state 10554 */ 10555 #define sc_x1_speed_override1_cl91_algn_state_LOSS_OF_ALIGNMENT 0 10556 #define sc_x1_speed_override1_cl91_algn_state_DESKEW 1 10557 #define sc_x1_speed_override1_cl91_algn_state_DESKEW_FAIL 2 10558 #define sc_x1_speed_override1_cl91_algn_state_ALIGN_ACQUIRED 3 10559 #define sc_x1_speed_override1_cl91_algn_state_CW_GOOD 4 10560 #define sc_x1_speed_override1_cl91_algn_state_CW_BAD 5 10561 #define sc_x1_speed_override1_cl91_algn_state_THREE_BAD 6 10562 10563 /**************************************************************************** 10564 * Enums: sc_x1_speed_override1_fec_sel 10565 */ 10566 #define sc_x1_speed_override1_fec_sel_NO_FEC 0 10567 #define sc_x1_speed_override1_fec_sel_FEC_CL74 1 10568 #define sc_x1_speed_override1_fec_sel_FEC_CL91 2 10569 10570 /**************************************************************************** 10571 * Enums: sc_x1_speed_override2_cl36TxEEEStates_l 10572 */ 10573 #define sc_x1_speed_override2_cl36TxEEEStates_l_TX_REFRESH 8 10574 #define sc_x1_speed_override2_cl36TxEEEStates_l_TX_QUIET 4 10575 #define sc_x1_speed_override2_cl36TxEEEStates_l_TX_SLEEP 2 10576 #define sc_x1_speed_override2_cl36TxEEEStates_l_TX_ACTIVE 1 10577 10578 /**************************************************************************** 10579 * Enums: sc_x1_speed_override2_cl36TxEEEStates_c 10580 */ 10581 #define sc_x1_speed_override2_cl36TxEEEStates_c_TX_REFRESH 3 10582 #define sc_x1_speed_override2_cl36TxEEEStates_c_TX_QUIET 2 10583 #define sc_x1_speed_override2_cl36TxEEEStates_c_TX_SLEEP 1 10584 #define sc_x1_speed_override2_cl36TxEEEStates_c_TX_ACTIVE 0 10585 10586 /**************************************************************************** 10587 * Enums: sc_x1_speed_override2_cl49TxEEEStates_l 10588 */ 10589 #define sc_x1_speed_override2_cl49TxEEEStates_l_SCR_RESET_2 64 10590 #define sc_x1_speed_override2_cl49TxEEEStates_l_SCR_RESET_1 32 10591 #define sc_x1_speed_override2_cl49TxEEEStates_l_TX_WAKE 16 10592 #define sc_x1_speed_override2_cl49TxEEEStates_l_TX_REFRESH 8 10593 #define sc_x1_speed_override2_cl49TxEEEStates_l_TX_QUIET 4 10594 #define sc_x1_speed_override2_cl49TxEEEStates_l_TX_SLEEP 2 10595 #define sc_x1_speed_override2_cl49TxEEEStates_l_TX_ACTIVE 1 10596 10597 /**************************************************************************** 10598 * Enums: sc_x1_speed_override2_fec_req_enum 10599 */ 10600 #define sc_x1_speed_override2_fec_req_enum_FEC_not_supported 0 10601 #define sc_x1_speed_override2_fec_req_enum_FEC_supported_but_not_requested 1 10602 #define sc_x1_speed_override2_fec_req_enum_invalid_setting 2 10603 #define sc_x1_speed_override2_fec_req_enum_FEC_supported_and_requested 3 10604 10605 /**************************************************************************** 10606 * Enums: sc_x1_speed_override2_cl73_pause_enum 10607 */ 10608 #define sc_x1_speed_override2_cl73_pause_enum_No_PAUSE_ability 0 10609 #define sc_x1_speed_override2_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 10610 #define sc_x1_speed_override2_cl73_pause_enum_Symmetric_PAUSE_ability 1 10611 #define sc_x1_speed_override2_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 10612 10613 /**************************************************************************** 10614 * Enums: sc_x1_speed_override2_cl49TxEEEStates_c 10615 */ 10616 #define sc_x1_speed_override2_cl49TxEEEStates_c_SCR_RESET_2 6 10617 #define sc_x1_speed_override2_cl49TxEEEStates_c_SCR_RESET_1 5 10618 #define sc_x1_speed_override2_cl49TxEEEStates_c_TX_WAKE 4 10619 #define sc_x1_speed_override2_cl49TxEEEStates_c_TX_REFRESH 3 10620 #define sc_x1_speed_override2_cl49TxEEEStates_c_TX_QUIET 2 10621 #define sc_x1_speed_override2_cl49TxEEEStates_c_TX_SLEEP 1 10622 #define sc_x1_speed_override2_cl49TxEEEStates_c_TX_ACTIVE 0 10623 10624 /**************************************************************************** 10625 * Enums: sc_x1_speed_override2_cl36RxEEEStates_l 10626 */ 10627 #define sc_x1_speed_override2_cl36RxEEEStates_l_RX_LINK_FAIL 32 10628 #define sc_x1_speed_override2_cl36RxEEEStates_l_RX_WTF 16 10629 #define sc_x1_speed_override2_cl36RxEEEStates_l_RX_WAKE 8 10630 #define sc_x1_speed_override2_cl36RxEEEStates_l_RX_QUIET 4 10631 #define sc_x1_speed_override2_cl36RxEEEStates_l_RX_SLEEP 2 10632 #define sc_x1_speed_override2_cl36RxEEEStates_l_RX_ACTIVE 1 10633 10634 /**************************************************************************** 10635 * Enums: sc_x1_speed_override2_cl36RxEEEStates_c 10636 */ 10637 #define sc_x1_speed_override2_cl36RxEEEStates_c_RX_LINK_FAIL 5 10638 #define sc_x1_speed_override2_cl36RxEEEStates_c_RX_WTF 4 10639 #define sc_x1_speed_override2_cl36RxEEEStates_c_RX_WAKE 3 10640 #define sc_x1_speed_override2_cl36RxEEEStates_c_RX_QUIET 2 10641 #define sc_x1_speed_override2_cl36RxEEEStates_c_RX_SLEEP 1 10642 #define sc_x1_speed_override2_cl36RxEEEStates_c_RX_ACTIVE 0 10643 10644 /**************************************************************************** 10645 * Enums: sc_x1_speed_override2_cl49RxEEEStates_l 10646 */ 10647 #define sc_x1_speed_override2_cl49RxEEEStates_l_RX_LINK_FAIL 32 10648 #define sc_x1_speed_override2_cl49RxEEEStates_l_RX_WTF 16 10649 #define sc_x1_speed_override2_cl49RxEEEStates_l_RX_WAKE 8 10650 #define sc_x1_speed_override2_cl49RxEEEStates_l_RX_QUIET 4 10651 #define sc_x1_speed_override2_cl49RxEEEStates_l_RX_SLEEP 2 10652 #define sc_x1_speed_override2_cl49RxEEEStates_l_RX_ACTIVE 1 10653 10654 /**************************************************************************** 10655 * Enums: sc_x1_speed_override2_cl49RxEEEStates_c 10656 */ 10657 #define sc_x1_speed_override2_cl49RxEEEStates_c_RX_LINK_FAIL 5 10658 #define sc_x1_speed_override2_cl49RxEEEStates_c_RX_WTF 4 10659 #define sc_x1_speed_override2_cl49RxEEEStates_c_RX_WAKE 3 10660 #define sc_x1_speed_override2_cl49RxEEEStates_c_RX_QUIET 2 10661 #define sc_x1_speed_override2_cl49RxEEEStates_c_RX_SLEEP 1 10662 #define sc_x1_speed_override2_cl49RxEEEStates_c_RX_ACTIVE 0 10663 10664 /**************************************************************************** 10665 * Enums: sc_x1_speed_override2_cl48TxEEEStates_l 10666 */ 10667 #define sc_x1_speed_override2_cl48TxEEEStates_l_TX_REFRESH 8 10668 #define sc_x1_speed_override2_cl48TxEEEStates_l_TX_QUIET 4 10669 #define sc_x1_speed_override2_cl48TxEEEStates_l_TX_SLEEP 2 10670 #define sc_x1_speed_override2_cl48TxEEEStates_l_TX_ACTIVE 1 10671 10672 /**************************************************************************** 10673 * Enums: sc_x1_speed_override2_cl48TxEEEStates_c 10674 */ 10675 #define sc_x1_speed_override2_cl48TxEEEStates_c_TX_REFRESH 3 10676 #define sc_x1_speed_override2_cl48TxEEEStates_c_TX_QUIET 2 10677 #define sc_x1_speed_override2_cl48TxEEEStates_c_TX_SLEEP 1 10678 #define sc_x1_speed_override2_cl48TxEEEStates_c_TX_ACTIVE 0 10679 10680 /**************************************************************************** 10681 * Enums: sc_x1_speed_override2_cl48RxEEEStates_l 10682 */ 10683 #define sc_x1_speed_override2_cl48RxEEEStates_l_RX_LINK_FAIL 32 10684 #define sc_x1_speed_override2_cl48RxEEEStates_l_RX_WAKE 16 10685 #define sc_x1_speed_override2_cl48RxEEEStates_l_RX_QUIET 8 10686 #define sc_x1_speed_override2_cl48RxEEEStates_l_RX_DEACT 4 10687 #define sc_x1_speed_override2_cl48RxEEEStates_l_RX_SLEEP 2 10688 #define sc_x1_speed_override2_cl48RxEEEStates_l_RX_ACTIVE 1 10689 10690 /**************************************************************************** 10691 * Enums: sc_x1_speed_override2_cl48RxEEEStates_c 10692 */ 10693 #define sc_x1_speed_override2_cl48RxEEEStates_c_RX_LINK_FAIL 5 10694 #define sc_x1_speed_override2_cl48RxEEEStates_c_RX_WAKE 4 10695 #define sc_x1_speed_override2_cl48RxEEEStates_c_RX_QUIET 3 10696 #define sc_x1_speed_override2_cl48RxEEEStates_c_RX_DEACT 2 10697 #define sc_x1_speed_override2_cl48RxEEEStates_c_RX_SLEEP 1 10698 #define sc_x1_speed_override2_cl48RxEEEStates_c_RX_ACTIVE 0 10699 10700 /**************************************************************************** 10701 * Enums: sc_x1_speed_override2_IQP_Options 10702 */ 10703 #define sc_x1_speed_override2_IQP_Options_i50uA 0 10704 #define sc_x1_speed_override2_IQP_Options_i100uA 1 10705 #define sc_x1_speed_override2_IQP_Options_i150uA 2 10706 #define sc_x1_speed_override2_IQP_Options_i200uA 3 10707 #define sc_x1_speed_override2_IQP_Options_i250uA 4 10708 #define sc_x1_speed_override2_IQP_Options_i300uA 5 10709 #define sc_x1_speed_override2_IQP_Options_i350uA 6 10710 #define sc_x1_speed_override2_IQP_Options_i400uA 7 10711 #define sc_x1_speed_override2_IQP_Options_i450uA 8 10712 #define sc_x1_speed_override2_IQP_Options_i500uA 9 10713 #define sc_x1_speed_override2_IQP_Options_i550uA 10 10714 #define sc_x1_speed_override2_IQP_Options_i600uA 11 10715 #define sc_x1_speed_override2_IQP_Options_i650uA 12 10716 #define sc_x1_speed_override2_IQP_Options_i700uA 13 10717 #define sc_x1_speed_override2_IQP_Options_i750uA 14 10718 #define sc_x1_speed_override2_IQP_Options_i800uA 15 10719 10720 /**************************************************************************** 10721 * Enums: sc_x1_speed_override2_IDriver_Options 10722 */ 10723 #define sc_x1_speed_override2_IDriver_Options_v680mV 0 10724 #define sc_x1_speed_override2_IDriver_Options_v730mV 1 10725 #define sc_x1_speed_override2_IDriver_Options_v780mV 2 10726 #define sc_x1_speed_override2_IDriver_Options_v830mV 3 10727 #define sc_x1_speed_override2_IDriver_Options_v880mV 4 10728 #define sc_x1_speed_override2_IDriver_Options_v930mV 5 10729 #define sc_x1_speed_override2_IDriver_Options_v980mV 6 10730 #define sc_x1_speed_override2_IDriver_Options_v1010mV 7 10731 #define sc_x1_speed_override2_IDriver_Options_v1040mV 8 10732 #define sc_x1_speed_override2_IDriver_Options_v1060mV 9 10733 #define sc_x1_speed_override2_IDriver_Options_v1070mV 10 10734 #define sc_x1_speed_override2_IDriver_Options_v1080mV 11 10735 #define sc_x1_speed_override2_IDriver_Options_v1085mV 12 10736 #define sc_x1_speed_override2_IDriver_Options_v1090mV 13 10737 #define sc_x1_speed_override2_IDriver_Options_v1095mV 14 10738 #define sc_x1_speed_override2_IDriver_Options_v1100mV 15 10739 10740 /**************************************************************************** 10741 * Enums: sc_x1_speed_override2_operationModes 10742 */ 10743 #define sc_x1_speed_override2_operationModes_XGXS 0 10744 #define sc_x1_speed_override2_operationModes_XGXG_nCC 1 10745 #define sc_x1_speed_override2_operationModes_Indlane_OS8 4 10746 #define sc_x1_speed_override2_operationModes_IndLane_OS5 5 10747 #define sc_x1_speed_override2_operationModes_PCI 7 10748 #define sc_x1_speed_override2_operationModes_XGXS_nLQ 8 10749 #define sc_x1_speed_override2_operationModes_XGXS_nLQnCC 9 10750 #define sc_x1_speed_override2_operationModes_PBypass 10 10751 #define sc_x1_speed_override2_operationModes_PBypass_nDSK 11 10752 #define sc_x1_speed_override2_operationModes_ComboCoreMode 12 10753 #define sc_x1_speed_override2_operationModes_Clocks_off 15 10754 10755 /**************************************************************************** 10756 * Enums: sc_x1_speed_override2_actualSpeeds 10757 */ 10758 #define sc_x1_speed_override2_actualSpeeds_dr_10M 0 10759 #define sc_x1_speed_override2_actualSpeeds_dr_100M 1 10760 #define sc_x1_speed_override2_actualSpeeds_dr_1G 2 10761 #define sc_x1_speed_override2_actualSpeeds_dr_2p5G 3 10762 #define sc_x1_speed_override2_actualSpeeds_dr_5G_X4 4 10763 #define sc_x1_speed_override2_actualSpeeds_dr_6G_X4 5 10764 #define sc_x1_speed_override2_actualSpeeds_dr_10G_HiG 6 10765 #define sc_x1_speed_override2_actualSpeeds_dr_10G_CX4 7 10766 #define sc_x1_speed_override2_actualSpeeds_dr_12G_HiG 8 10767 #define sc_x1_speed_override2_actualSpeeds_dr_12p5G_X4 9 10768 #define sc_x1_speed_override2_actualSpeeds_dr_13G_X4 10 10769 #define sc_x1_speed_override2_actualSpeeds_dr_15G_X4 11 10770 #define sc_x1_speed_override2_actualSpeeds_dr_16G_X4 12 10771 #define sc_x1_speed_override2_actualSpeeds_dr_1G_KX 13 10772 #define sc_x1_speed_override2_actualSpeeds_dr_10G_KX4 14 10773 #define sc_x1_speed_override2_actualSpeeds_dr_10G_KR 15 10774 #define sc_x1_speed_override2_actualSpeeds_dr_5G 16 10775 #define sc_x1_speed_override2_actualSpeeds_dr_6p4G 17 10776 #define sc_x1_speed_override2_actualSpeeds_dr_20G_X4 18 10777 #define sc_x1_speed_override2_actualSpeeds_dr_21G_X4 19 10778 #define sc_x1_speed_override2_actualSpeeds_dr_25G_X4 20 10779 #define sc_x1_speed_override2_actualSpeeds_dr_10G_HiG_DXGXS 21 10780 #define sc_x1_speed_override2_actualSpeeds_dr_10G_DXGXS 22 10781 #define sc_x1_speed_override2_actualSpeeds_dr_10p5G_HiG_DXGXS 23 10782 #define sc_x1_speed_override2_actualSpeeds_dr_10p5G_DXGXS 24 10783 #define sc_x1_speed_override2_actualSpeeds_dr_12p773G_HiG_DXGXS 25 10784 #define sc_x1_speed_override2_actualSpeeds_dr_12p773G_DXGXS 26 10785 #define sc_x1_speed_override2_actualSpeeds_dr_10G_XFI 27 10786 #define sc_x1_speed_override2_actualSpeeds_dr_40G 28 10787 #define sc_x1_speed_override2_actualSpeeds_dr_20G_HiG_DXGXS 29 10788 #define sc_x1_speed_override2_actualSpeeds_dr_20G_DXGXS 30 10789 #define sc_x1_speed_override2_actualSpeeds_dr_10G_SFI 31 10790 #define sc_x1_speed_override2_actualSpeeds_dr_31p5G 32 10791 #define sc_x1_speed_override2_actualSpeeds_dr_32p7G 33 10792 #define sc_x1_speed_override2_actualSpeeds_dr_20G_SCR 34 10793 #define sc_x1_speed_override2_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 10794 #define sc_x1_speed_override2_actualSpeeds_dr_10G_DXGXS_SCR 36 10795 #define sc_x1_speed_override2_actualSpeeds_dr_12G_R2 37 10796 #define sc_x1_speed_override2_actualSpeeds_dr_10G_X2 38 10797 #define sc_x1_speed_override2_actualSpeeds_dr_40G_KR4 39 10798 #define sc_x1_speed_override2_actualSpeeds_dr_40G_CR4 40 10799 #define sc_x1_speed_override2_actualSpeeds_dr_100G_CR10 41 10800 #define sc_x1_speed_override2_actualSpeeds_dr_15p75G_DXGXS 44 10801 #define sc_x1_speed_override2_actualSpeeds_dr_20G_KR2 57 10802 #define sc_x1_speed_override2_actualSpeeds_dr_20G_CR2 58 10803 10804 /**************************************************************************** 10805 * Enums: sc_x1_speed_override2_actualSpeedsMisc1 10806 */ 10807 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_2500BRCM_X1 16 10808 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_5000BRCM_X4 17 10809 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_6000BRCM_X4 18 10810 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_10GHiGig_X4 19 10811 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_10GBASE_CX4 20 10812 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_12GHiGig_X4 21 10813 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 10814 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_13GHiGig_X4 23 10815 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_15GHiGig_X4 24 10816 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_16GHiGig_X4 25 10817 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_5000BRCM_X1 26 10818 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_6363BRCM_X1 27 10819 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_20GHiGig_X4 28 10820 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_21GHiGig_X4 29 10821 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 10822 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 10823 10824 /**************************************************************************** 10825 * Enums: sc_x1_speed_override2_IndLaneModes 10826 */ 10827 #define sc_x1_speed_override2_IndLaneModes_SWSDR_div2 0 10828 #define sc_x1_speed_override2_IndLaneModes_SWSDR_div1 1 10829 #define sc_x1_speed_override2_IndLaneModes_DWSDR_div2 2 10830 #define sc_x1_speed_override2_IndLaneModes_DWSDR_div1 3 10831 10832 /**************************************************************************** 10833 * Enums: sc_x1_speed_override2_prbsSelect 10834 */ 10835 #define sc_x1_speed_override2_prbsSelect_prbs7 0 10836 #define sc_x1_speed_override2_prbsSelect_prbs15 1 10837 #define sc_x1_speed_override2_prbsSelect_prbs23 2 10838 #define sc_x1_speed_override2_prbsSelect_prbs31 3 10839 10840 /**************************************************************************** 10841 * Enums: sc_x1_speed_override2_vcoDivider 10842 */ 10843 #define sc_x1_speed_override2_vcoDivider_div32 0 10844 #define sc_x1_speed_override2_vcoDivider_div36 1 10845 #define sc_x1_speed_override2_vcoDivider_div40 2 10846 #define sc_x1_speed_override2_vcoDivider_div42 3 10847 #define sc_x1_speed_override2_vcoDivider_div48 4 10848 #define sc_x1_speed_override2_vcoDivider_div50 5 10849 #define sc_x1_speed_override2_vcoDivider_div52 6 10850 #define sc_x1_speed_override2_vcoDivider_div54 7 10851 #define sc_x1_speed_override2_vcoDivider_div60 8 10852 #define sc_x1_speed_override2_vcoDivider_div64 9 10853 #define sc_x1_speed_override2_vcoDivider_div66 10 10854 #define sc_x1_speed_override2_vcoDivider_div68 11 10855 #define sc_x1_speed_override2_vcoDivider_div70 12 10856 #define sc_x1_speed_override2_vcoDivider_div80 13 10857 #define sc_x1_speed_override2_vcoDivider_div92 14 10858 #define sc_x1_speed_override2_vcoDivider_div100 15 10859 10860 /**************************************************************************** 10861 * Enums: sc_x1_speed_override2_refClkSelect 10862 */ 10863 #define sc_x1_speed_override2_refClkSelect_clk_25MHz 0 10864 #define sc_x1_speed_override2_refClkSelect_clk_100MHz 1 10865 #define sc_x1_speed_override2_refClkSelect_clk_125MHz 2 10866 #define sc_x1_speed_override2_refClkSelect_clk_156p25MHz 3 10867 #define sc_x1_speed_override2_refClkSelect_clk_187p5MHz 4 10868 #define sc_x1_speed_override2_refClkSelect_clk_161p25Mhz 5 10869 #define sc_x1_speed_override2_refClkSelect_clk_50Mhz 6 10870 #define sc_x1_speed_override2_refClkSelect_clk_106p25Mhz 7 10871 10872 /**************************************************************************** 10873 * Enums: sc_x1_speed_override2_aerMMDdevTypeSelect 10874 */ 10875 #define sc_x1_speed_override2_aerMMDdevTypeSelect_combo_core 0 10876 #define sc_x1_speed_override2_aerMMDdevTypeSelect_PMA_PMD 1 10877 #define sc_x1_speed_override2_aerMMDdevTypeSelect_PCS 3 10878 #define sc_x1_speed_override2_aerMMDdevTypeSelect_PHY 4 10879 #define sc_x1_speed_override2_aerMMDdevTypeSelect_DTE 5 10880 #define sc_x1_speed_override2_aerMMDdevTypeSelect_CL73_AN 7 10881 10882 /**************************************************************************** 10883 * Enums: sc_x1_speed_override2_aerMMDportSelect 10884 */ 10885 #define sc_x1_speed_override2_aerMMDportSelect_ln0 0 10886 #define sc_x1_speed_override2_aerMMDportSelect_ln1 1 10887 #define sc_x1_speed_override2_aerMMDportSelect_ln2 2 10888 #define sc_x1_speed_override2_aerMMDportSelect_ln3 3 10889 #define sc_x1_speed_override2_aerMMDportSelect_BCST_ln0_1_2_3 511 10890 #define sc_x1_speed_override2_aerMMDportSelect_BCST_ln0_1 512 10891 #define sc_x1_speed_override2_aerMMDportSelect_BCST_ln2_3 513 10892 10893 /**************************************************************************** 10894 * Enums: sc_x1_speed_override2_firmwareModeSelect 10895 */ 10896 #define sc_x1_speed_override2_firmwareModeSelect_DEFAULT 0 10897 #define sc_x1_speed_override2_firmwareModeSelect_SFP_OPT_LR 1 10898 #define sc_x1_speed_override2_firmwareModeSelect_SFP_DAC 2 10899 #define sc_x1_speed_override2_firmwareModeSelect_XLAUI 3 10900 #define sc_x1_speed_override2_firmwareModeSelect_LONG_CH_6G 4 10901 10902 /**************************************************************************** 10903 * Enums: sc_x1_speed_override2_tempIdxSelect 10904 */ 10905 #define sc_x1_speed_override2_tempIdxSelect_LTE__22p9C 15 10906 #define sc_x1_speed_override2_tempIdxSelect_LTE__12p6C 14 10907 #define sc_x1_speed_override2_tempIdxSelect_LTE__3p0C 13 10908 #define sc_x1_speed_override2_tempIdxSelect_LTE_6p7C 12 10909 #define sc_x1_speed_override2_tempIdxSelect_LTE_16p4C 11 10910 #define sc_x1_speed_override2_tempIdxSelect_LTE_26p6C 10 10911 #define sc_x1_speed_override2_tempIdxSelect_LTE_36p3C 9 10912 #define sc_x1_speed_override2_tempIdxSelect_LTE_46p0C 8 10913 #define sc_x1_speed_override2_tempIdxSelect_LTE_56p2C 7 10914 #define sc_x1_speed_override2_tempIdxSelect_LTE_65p9C 6 10915 #define sc_x1_speed_override2_tempIdxSelect_LTE_75p6C 5 10916 #define sc_x1_speed_override2_tempIdxSelect_LTE_85p3C 4 10917 #define sc_x1_speed_override2_tempIdxSelect_LTE_95p5C 3 10918 #define sc_x1_speed_override2_tempIdxSelect_LTE_105p2C 2 10919 #define sc_x1_speed_override2_tempIdxSelect_LTE_114p9C 1 10920 #define sc_x1_speed_override2_tempIdxSelect_LTE_125p1C 0 10921 10922 /**************************************************************************** 10923 * Enums: sc_x1_speed_override2_port_mode 10924 */ 10925 #define sc_x1_speed_override2_port_mode_QUAD_PORT 0 10926 #define sc_x1_speed_override2_port_mode_TRI_1_PORT 1 10927 #define sc_x1_speed_override2_port_mode_TRI_2_PORT 2 10928 #define sc_x1_speed_override2_port_mode_DUAL_PORT 3 10929 #define sc_x1_speed_override2_port_mode_SINGLE_PORT 4 10930 10931 /**************************************************************************** 10932 * Enums: sc_x1_speed_override2_rev_letter_enum 10933 */ 10934 #define sc_x1_speed_override2_rev_letter_enum_REV_A 0 10935 #define sc_x1_speed_override2_rev_letter_enum_REV_B 1 10936 #define sc_x1_speed_override2_rev_letter_enum_REV_C 2 10937 #define sc_x1_speed_override2_rev_letter_enum_REV_D 3 10938 10939 /**************************************************************************** 10940 * Enums: sc_x1_speed_override2_rev_number_enum 10941 */ 10942 #define sc_x1_speed_override2_rev_number_enum_REV_0 0 10943 #define sc_x1_speed_override2_rev_number_enum_REV_1 1 10944 #define sc_x1_speed_override2_rev_number_enum_REV_2 2 10945 #define sc_x1_speed_override2_rev_number_enum_REV_3 3 10946 #define sc_x1_speed_override2_rev_number_enum_REV_4 4 10947 #define sc_x1_speed_override2_rev_number_enum_REV_5 5 10948 #define sc_x1_speed_override2_rev_number_enum_REV_6 6 10949 #define sc_x1_speed_override2_rev_number_enum_REV_7 7 10950 10951 /**************************************************************************** 10952 * Enums: sc_x1_speed_override2_bonding_enum 10953 */ 10954 #define sc_x1_speed_override2_bonding_enum_WIRE_BOND 0 10955 #define sc_x1_speed_override2_bonding_enum_FLIP_CHIP 1 10956 10957 /**************************************************************************** 10958 * Enums: sc_x1_speed_override2_tech_process 10959 */ 10960 #define sc_x1_speed_override2_tech_process_PROCESS_90NM 0 10961 #define sc_x1_speed_override2_tech_process_PROCESS_65NM 1 10962 #define sc_x1_speed_override2_tech_process_PROCESS_40NM 2 10963 #define sc_x1_speed_override2_tech_process_PROCESS_28NM 3 10964 10965 /**************************************************************************** 10966 * Enums: sc_x1_speed_override2_model_num 10967 */ 10968 #define sc_x1_speed_override2_model_num_SERDES_CL73 0 10969 #define sc_x1_speed_override2_model_num_XGXS_16G 1 10970 #define sc_x1_speed_override2_model_num_HYPERCORE 2 10971 #define sc_x1_speed_override2_model_num_HYPERLITE 3 10972 #define sc_x1_speed_override2_model_num_PCIE_G2_PIPE 4 10973 #define sc_x1_speed_override2_model_num_SERDES_1p25GBd 5 10974 #define sc_x1_speed_override2_model_num_SATA2 6 10975 #define sc_x1_speed_override2_model_num_QSGMII 7 10976 #define sc_x1_speed_override2_model_num_XGXS10G 8 10977 #define sc_x1_speed_override2_model_num_WARPCORE 9 10978 #define sc_x1_speed_override2_model_num_XFICORE 10 10979 #define sc_x1_speed_override2_model_num_RXFI 11 10980 #define sc_x1_speed_override2_model_num_WARPLITE 12 10981 #define sc_x1_speed_override2_model_num_PENTACORE 13 10982 #define sc_x1_speed_override2_model_num_ESM 14 10983 #define sc_x1_speed_override2_model_num_QUAD_SGMII 15 10984 #define sc_x1_speed_override2_model_num_WARPCORE_3 16 10985 #define sc_x1_speed_override2_model_num_TSC 17 10986 #define sc_x1_speed_override2_model_num_TSC4E 18 10987 #define sc_x1_speed_override2_model_num_TSC12E 19 10988 #define sc_x1_speed_override2_model_num_TSC4F 20 10989 #define sc_x1_speed_override2_model_num_XGXS_CL73_90NM 29 10990 #define sc_x1_speed_override2_model_num_SERDES_CL73_90NM 30 10991 #define sc_x1_speed_override2_model_num_WARPCORE3 32 10992 #define sc_x1_speed_override2_model_num_WARPCORE4_TSC 33 10993 #define sc_x1_speed_override2_model_num_RXAUI 34 10994 10995 /**************************************************************************** 10996 * Enums: sc_x1_speed_override2_payload 10997 */ 10998 #define sc_x1_speed_override2_payload_REPEAT_2_BYTES 0 10999 #define sc_x1_speed_override2_payload_RAMPING 1 11000 #define sc_x1_speed_override2_payload_CL48_CRPAT 2 11001 #define sc_x1_speed_override2_payload_CL48_CJPAT 3 11002 #define sc_x1_speed_override2_payload_CL36_LONG_CRPAT 4 11003 #define sc_x1_speed_override2_payload_CL36_SHORT_CRPAT 5 11004 11005 /**************************************************************************** 11006 * Enums: sc_x1_speed_override2_sc 11007 */ 11008 #define sc_x1_speed_override2_sc_S_10G_CR1 0 11009 #define sc_x1_speed_override2_sc_S_10G_KR1 1 11010 #define sc_x1_speed_override2_sc_S_10G_X1 2 11011 #define sc_x1_speed_override2_sc_S_10G_HG2_CR1 4 11012 #define sc_x1_speed_override2_sc_S_10G_HG2_KR1 5 11013 #define sc_x1_speed_override2_sc_S_10G_HG2_X1 6 11014 #define sc_x1_speed_override2_sc_S_20G_CR1 8 11015 #define sc_x1_speed_override2_sc_S_20G_KR1 9 11016 #define sc_x1_speed_override2_sc_S_20G_X1 10 11017 #define sc_x1_speed_override2_sc_S_20G_HG2_CR1 12 11018 #define sc_x1_speed_override2_sc_S_20G_HG2_KR1 13 11019 #define sc_x1_speed_override2_sc_S_20G_HG2_X1 14 11020 #define sc_x1_speed_override2_sc_S_25G_CR1 16 11021 #define sc_x1_speed_override2_sc_S_25G_KR1 17 11022 #define sc_x1_speed_override2_sc_S_25G_X1 18 11023 #define sc_x1_speed_override2_sc_S_25G_HG2_CR1 20 11024 #define sc_x1_speed_override2_sc_S_25G_HG2_KR1 21 11025 #define sc_x1_speed_override2_sc_S_25G_HG2_X1 22 11026 #define sc_x1_speed_override2_sc_S_20G_CR2 24 11027 #define sc_x1_speed_override2_sc_S_20G_KR2 25 11028 #define sc_x1_speed_override2_sc_S_20G_X2 26 11029 #define sc_x1_speed_override2_sc_S_20G_HG2_CR2 28 11030 #define sc_x1_speed_override2_sc_S_20G_HG2_KR2 29 11031 #define sc_x1_speed_override2_sc_S_20G_HG2_X2 30 11032 #define sc_x1_speed_override2_sc_S_40G_CR2 32 11033 #define sc_x1_speed_override2_sc_S_40G_KR2 33 11034 #define sc_x1_speed_override2_sc_S_40G_X2 34 11035 #define sc_x1_speed_override2_sc_S_40G_HG2_CR2 36 11036 #define sc_x1_speed_override2_sc_S_40G_HG2_KR2 37 11037 #define sc_x1_speed_override2_sc_S_40G_HG2_X2 38 11038 #define sc_x1_speed_override2_sc_S_40G_CR4 40 11039 #define sc_x1_speed_override2_sc_S_40G_KR4 41 11040 #define sc_x1_speed_override2_sc_S_40G_X4 42 11041 #define sc_x1_speed_override2_sc_S_40G_HG2_CR4 44 11042 #define sc_x1_speed_override2_sc_S_40G_HG2_KR4 45 11043 #define sc_x1_speed_override2_sc_S_40G_HG2_X4 46 11044 #define sc_x1_speed_override2_sc_S_50G_CR2 48 11045 #define sc_x1_speed_override2_sc_S_50G_KR2 49 11046 #define sc_x1_speed_override2_sc_S_50G_X2 50 11047 #define sc_x1_speed_override2_sc_S_50G_HG2_CR2 52 11048 #define sc_x1_speed_override2_sc_S_50G_HG2_KR2 53 11049 #define sc_x1_speed_override2_sc_S_50G_HG2_X2 54 11050 #define sc_x1_speed_override2_sc_S_50G_CR4 56 11051 #define sc_x1_speed_override2_sc_S_50G_KR4 57 11052 #define sc_x1_speed_override2_sc_S_50G_X4 58 11053 #define sc_x1_speed_override2_sc_S_50G_HG2_CR4 60 11054 #define sc_x1_speed_override2_sc_S_50G_HG2_KR4 61 11055 #define sc_x1_speed_override2_sc_S_50G_HG2_X4 62 11056 #define sc_x1_speed_override2_sc_S_100G_CR4 64 11057 #define sc_x1_speed_override2_sc_S_100G_KR4 65 11058 #define sc_x1_speed_override2_sc_S_100G_X4 66 11059 #define sc_x1_speed_override2_sc_S_100G_HG2_CR4 68 11060 #define sc_x1_speed_override2_sc_S_100G_HG2_KR4 69 11061 #define sc_x1_speed_override2_sc_S_100G_HG2_X4 70 11062 #define sc_x1_speed_override2_sc_S_CL73_20GVCO 72 11063 #define sc_x1_speed_override2_sc_S_CL73_25GVCO 80 11064 #define sc_x1_speed_override2_sc_S_CL36_20GVCO 88 11065 #define sc_x1_speed_override2_sc_S_CL36_25GVCO 96 11066 11067 /**************************************************************************** 11068 * Enums: sc_x1_speed_override2_t_fifo_modes 11069 */ 11070 #define sc_x1_speed_override2_t_fifo_modes_T_FIFO_MODE_BYPASS 0 11071 #define sc_x1_speed_override2_t_fifo_modes_T_FIFO_MODE_40G 1 11072 #define sc_x1_speed_override2_t_fifo_modes_T_FIFO_MODE_100G 2 11073 #define sc_x1_speed_override2_t_fifo_modes_T_FIFO_MODE_20G 3 11074 11075 /**************************************************************************** 11076 * Enums: sc_x1_speed_override2_t_enc_modes 11077 */ 11078 #define sc_x1_speed_override2_t_enc_modes_T_ENC_MODE_BYPASS 0 11079 #define sc_x1_speed_override2_t_enc_modes_T_ENC_MODE_CL49 1 11080 #define sc_x1_speed_override2_t_enc_modes_T_ENC_MODE_CL82 2 11081 11082 /**************************************************************************** 11083 * Enums: sc_x1_speed_override2_btmx_mode 11084 */ 11085 #define sc_x1_speed_override2_btmx_mode_BS_BTMX_MODE_1to1 0 11086 #define sc_x1_speed_override2_btmx_mode_BS_BTMX_MODE_2to1 1 11087 #define sc_x1_speed_override2_btmx_mode_BS_BTMX_MODE_5to1 2 11088 11089 /**************************************************************************** 11090 * Enums: sc_x1_speed_override2_t_type_cl82 11091 */ 11092 #define sc_x1_speed_override2_t_type_cl82_T_TYPE_B1 5 11093 #define sc_x1_speed_override2_t_type_cl82_T_TYPE_C 4 11094 #define sc_x1_speed_override2_t_type_cl82_T_TYPE_S 3 11095 #define sc_x1_speed_override2_t_type_cl82_T_TYPE_T 2 11096 #define sc_x1_speed_override2_t_type_cl82_T_TYPE_D 1 11097 #define sc_x1_speed_override2_t_type_cl82_T_TYPE_E 0 11098 11099 /**************************************************************************** 11100 * Enums: sc_x1_speed_override2_txsm_state_cl82 11101 */ 11102 #define sc_x1_speed_override2_txsm_state_cl82_TX_HIG_END 6 11103 #define sc_x1_speed_override2_txsm_state_cl82_TX_HIG_START 5 11104 #define sc_x1_speed_override2_txsm_state_cl82_TX_E 4 11105 #define sc_x1_speed_override2_txsm_state_cl82_TX_T 3 11106 #define sc_x1_speed_override2_txsm_state_cl82_TX_D 2 11107 #define sc_x1_speed_override2_txsm_state_cl82_TX_C 1 11108 #define sc_x1_speed_override2_txsm_state_cl82_TX_INIT 0 11109 11110 /**************************************************************************** 11111 * Enums: sc_x1_speed_override2_ltxsm_state_cl82 11112 */ 11113 #define sc_x1_speed_override2_ltxsm_state_cl82_TX_HIG_END 64 11114 #define sc_x1_speed_override2_ltxsm_state_cl82_TX_HIG_START 32 11115 #define sc_x1_speed_override2_ltxsm_state_cl82_TX_E 16 11116 #define sc_x1_speed_override2_ltxsm_state_cl82_TX_T 8 11117 #define sc_x1_speed_override2_ltxsm_state_cl82_TX_D 4 11118 #define sc_x1_speed_override2_ltxsm_state_cl82_TX_C 2 11119 #define sc_x1_speed_override2_ltxsm_state_cl82_TX_INIT 1 11120 11121 /**************************************************************************** 11122 * Enums: sc_x1_speed_override2_r_type_coded_cl82 11123 */ 11124 #define sc_x1_speed_override2_r_type_coded_cl82_R_TYPE_B1 32 11125 #define sc_x1_speed_override2_r_type_coded_cl82_R_TYPE_C 16 11126 #define sc_x1_speed_override2_r_type_coded_cl82_R_TYPE_S 8 11127 #define sc_x1_speed_override2_r_type_coded_cl82_R_TYPE_T 4 11128 #define sc_x1_speed_override2_r_type_coded_cl82_R_TYPE_D 2 11129 #define sc_x1_speed_override2_r_type_coded_cl82_R_TYPE_E 1 11130 11131 /**************************************************************************** 11132 * Enums: sc_x1_speed_override2_rxsm_state_cl82 11133 */ 11134 #define sc_x1_speed_override2_rxsm_state_cl82_RX_HIG_END 64 11135 #define sc_x1_speed_override2_rxsm_state_cl82_RX_HIG_START 32 11136 #define sc_x1_speed_override2_rxsm_state_cl82_RX_E 16 11137 #define sc_x1_speed_override2_rxsm_state_cl82_RX_T 8 11138 #define sc_x1_speed_override2_rxsm_state_cl82_RX_D 4 11139 #define sc_x1_speed_override2_rxsm_state_cl82_RX_C 2 11140 #define sc_x1_speed_override2_rxsm_state_cl82_RX_INIT 1 11141 11142 /**************************************************************************** 11143 * Enums: sc_x1_speed_override2_deskew_state 11144 */ 11145 #define sc_x1_speed_override2_deskew_state_ALIGN_ACQUIRED 2 11146 #define sc_x1_speed_override2_deskew_state_LOSS_OF_ALIGNMENT 1 11147 11148 /**************************************************************************** 11149 * Enums: sc_x1_speed_override2_os_mode_enum 11150 */ 11151 #define sc_x1_speed_override2_os_mode_enum_OS_MODE_1 0 11152 #define sc_x1_speed_override2_os_mode_enum_OS_MODE_2 1 11153 #define sc_x1_speed_override2_os_mode_enum_OS_MODE_4 2 11154 #define sc_x1_speed_override2_os_mode_enum_OS_MODE_16p5 8 11155 #define sc_x1_speed_override2_os_mode_enum_OS_MODE_20p625 12 11156 11157 /**************************************************************************** 11158 * Enums: sc_x1_speed_override2_scr_modes 11159 */ 11160 #define sc_x1_speed_override2_scr_modes_T_SCR_MODE_BYPASS 0 11161 #define sc_x1_speed_override2_scr_modes_T_SCR_MODE_CL49 1 11162 #define sc_x1_speed_override2_scr_modes_T_SCR_MODE_40G_2_LANE 2 11163 #define sc_x1_speed_override2_scr_modes_T_SCR_MODE_100G 3 11164 #define sc_x1_speed_override2_scr_modes_T_SCR_MODE_20G 4 11165 #define sc_x1_speed_override2_scr_modes_T_SCR_MODE_40G_4_LANE 5 11166 11167 /**************************************************************************** 11168 * Enums: sc_x1_speed_override2_descr_modes 11169 */ 11170 #define sc_x1_speed_override2_descr_modes_R_DESCR_MODE_BYPASS 0 11171 #define sc_x1_speed_override2_descr_modes_R_DESCR_MODE_CL49 1 11172 #define sc_x1_speed_override2_descr_modes_R_DESCR_MODE_CL82 2 11173 11174 /**************************************************************************** 11175 * Enums: sc_x1_speed_override2_r_dec_tl_mode 11176 */ 11177 #define sc_x1_speed_override2_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 11178 #define sc_x1_speed_override2_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 11179 #define sc_x1_speed_override2_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 11180 11181 /**************************************************************************** 11182 * Enums: sc_x1_speed_override2_r_dec_fsm_mode 11183 */ 11184 #define sc_x1_speed_override2_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 11185 #define sc_x1_speed_override2_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 11186 #define sc_x1_speed_override2_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 11187 11188 /**************************************************************************** 11189 * Enums: sc_x1_speed_override2_r_deskew_mode 11190 */ 11191 #define sc_x1_speed_override2_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 11192 #define sc_x1_speed_override2_r_deskew_mode_R_DESKEW_MODE_20G 1 11193 #define sc_x1_speed_override2_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 11194 #define sc_x1_speed_override2_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 11195 #define sc_x1_speed_override2_r_deskew_mode_R_DESKEW_MODE_100G 4 11196 #define sc_x1_speed_override2_r_deskew_mode_R_DESKEW_MODE_CL49 5 11197 #define sc_x1_speed_override2_r_deskew_mode_R_DESKEW_MODE_CL91 6 11198 11199 /**************************************************************************** 11200 * Enums: sc_x1_speed_override2_bs_dist_modes 11201 */ 11202 #define sc_x1_speed_override2_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 11203 #define sc_x1_speed_override2_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 11204 #define sc_x1_speed_override2_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 11205 #define sc_x1_speed_override2_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 11206 11207 /**************************************************************************** 11208 * Enums: sc_x1_speed_override2_cl49_t_type 11209 */ 11210 #define sc_x1_speed_override2_cl49_t_type_BAD_T_TYPE 15 11211 #define sc_x1_speed_override2_cl49_t_type_T_TYPE_B0 11 11212 #define sc_x1_speed_override2_cl49_t_type_T_TYPE_OB 10 11213 #define sc_x1_speed_override2_cl49_t_type_T_TYPE_B1 9 11214 #define sc_x1_speed_override2_cl49_t_type_T_TYPE_DB 8 11215 #define sc_x1_speed_override2_cl49_t_type_T_TYPE_FC 7 11216 #define sc_x1_speed_override2_cl49_t_type_T_TYPE_TB 6 11217 #define sc_x1_speed_override2_cl49_t_type_T_TYPE_LI 5 11218 #define sc_x1_speed_override2_cl49_t_type_T_TYPE_C 4 11219 #define sc_x1_speed_override2_cl49_t_type_T_TYPE_S 3 11220 #define sc_x1_speed_override2_cl49_t_type_T_TYPE_T 2 11221 #define sc_x1_speed_override2_cl49_t_type_T_TYPE_D 1 11222 #define sc_x1_speed_override2_cl49_t_type_T_TYPE_E 0 11223 11224 /**************************************************************************** 11225 * Enums: sc_x1_speed_override2_cl49_txsm_states 11226 */ 11227 #define sc_x1_speed_override2_cl49_txsm_states_TX_HIG_END 7 11228 #define sc_x1_speed_override2_cl49_txsm_states_TX_HIG_START 6 11229 #define sc_x1_speed_override2_cl49_txsm_states_TX_LI 5 11230 #define sc_x1_speed_override2_cl49_txsm_states_TX_E 4 11231 #define sc_x1_speed_override2_cl49_txsm_states_TX_T 3 11232 #define sc_x1_speed_override2_cl49_txsm_states_TX_D 2 11233 #define sc_x1_speed_override2_cl49_txsm_states_TX_C 1 11234 #define sc_x1_speed_override2_cl49_txsm_states_TX_INIT 0 11235 11236 /**************************************************************************** 11237 * Enums: sc_x1_speed_override2_cl49_ltxsm_states 11238 */ 11239 #define sc_x1_speed_override2_cl49_ltxsm_states_TX_HIG_END 128 11240 #define sc_x1_speed_override2_cl49_ltxsm_states_TX_HIG_START 64 11241 #define sc_x1_speed_override2_cl49_ltxsm_states_TX_LI 32 11242 #define sc_x1_speed_override2_cl49_ltxsm_states_TX_E 16 11243 #define sc_x1_speed_override2_cl49_ltxsm_states_TX_T 8 11244 #define sc_x1_speed_override2_cl49_ltxsm_states_TX_D 4 11245 #define sc_x1_speed_override2_cl49_ltxsm_states_TX_C 2 11246 #define sc_x1_speed_override2_cl49_ltxsm_states_TX_INIT 1 11247 11248 /**************************************************************************** 11249 * Enums: sc_x1_speed_override2_burst_error_mode 11250 */ 11251 #define sc_x1_speed_override2_burst_error_mode_BURST_ERROR_11_BITS 0 11252 #define sc_x1_speed_override2_burst_error_mode_BURST_ERROR_16_BITS 1 11253 #define sc_x1_speed_override2_burst_error_mode_BURST_ERROR_17_BITS 2 11254 #define sc_x1_speed_override2_burst_error_mode_BURST_ERROR_18_BITS 3 11255 #define sc_x1_speed_override2_burst_error_mode_BURST_ERROR_19_BITS 4 11256 #define sc_x1_speed_override2_burst_error_mode_BURST_ERROR_20_BITS 5 11257 #define sc_x1_speed_override2_burst_error_mode_BURST_ERROR_21_BITS 6 11258 #define sc_x1_speed_override2_burst_error_mode_BURST_ERROR_22_BITS 7 11259 #define sc_x1_speed_override2_burst_error_mode_BURST_ERROR_23_BITS 8 11260 #define sc_x1_speed_override2_burst_error_mode_BURST_ERROR_24_BITS 9 11261 #define sc_x1_speed_override2_burst_error_mode_BURST_ERROR_25_BITS 10 11262 #define sc_x1_speed_override2_burst_error_mode_BURST_ERROR_26_BITS 11 11263 #define sc_x1_speed_override2_burst_error_mode_BURST_ERROR_27_BITS 12 11264 #define sc_x1_speed_override2_burst_error_mode_BURST_ERROR_28_BITS 13 11265 #define sc_x1_speed_override2_burst_error_mode_BURST_ERROR_29_BITS 14 11266 #define sc_x1_speed_override2_burst_error_mode_BURST_ERROR_30_BITS 15 11267 #define sc_x1_speed_override2_burst_error_mode_BURST_ERROR_31_BITS 16 11268 #define sc_x1_speed_override2_burst_error_mode_BURST_ERROR_32_BITS 17 11269 #define sc_x1_speed_override2_burst_error_mode_BURST_ERROR_33_BITS 18 11270 #define sc_x1_speed_override2_burst_error_mode_BURST_ERROR_34_BITS 19 11271 #define sc_x1_speed_override2_burst_error_mode_BURST_ERROR_35_BITS 20 11272 #define sc_x1_speed_override2_burst_error_mode_BURST_ERROR_36_BITS 21 11273 #define sc_x1_speed_override2_burst_error_mode_BURST_ERROR_37_BITS 22 11274 #define sc_x1_speed_override2_burst_error_mode_BURST_ERROR_38_BITS 23 11275 #define sc_x1_speed_override2_burst_error_mode_BURST_ERROR_39_BITS 24 11276 #define sc_x1_speed_override2_burst_error_mode_BURST_ERROR_40_BITS 25 11277 #define sc_x1_speed_override2_burst_error_mode_BURST_ERROR_41_BITS 26 11278 11279 /**************************************************************************** 11280 * Enums: sc_x1_speed_override2_bermon_state 11281 */ 11282 #define sc_x1_speed_override2_bermon_state_HI_BER 4 11283 #define sc_x1_speed_override2_bermon_state_GOOD_BER 3 11284 #define sc_x1_speed_override2_bermon_state_BER_TEST_SH 2 11285 #define sc_x1_speed_override2_bermon_state_START_TIMER 1 11286 #define sc_x1_speed_override2_bermon_state_BER_MT_INIT 0 11287 11288 /**************************************************************************** 11289 * Enums: sc_x1_speed_override2_rxsm_state_cl49 11290 */ 11291 #define sc_x1_speed_override2_rxsm_state_cl49_RX_HIG_END 128 11292 #define sc_x1_speed_override2_rxsm_state_cl49_RX_HIG_START 64 11293 #define sc_x1_speed_override2_rxsm_state_cl49_RX_LI 32 11294 #define sc_x1_speed_override2_rxsm_state_cl49_RX_E 16 11295 #define sc_x1_speed_override2_rxsm_state_cl49_RX_T 8 11296 #define sc_x1_speed_override2_rxsm_state_cl49_RX_D 4 11297 #define sc_x1_speed_override2_rxsm_state_cl49_RX_C 2 11298 #define sc_x1_speed_override2_rxsm_state_cl49_RX_INIT 1 11299 11300 /**************************************************************************** 11301 * Enums: sc_x1_speed_override2_r_type 11302 */ 11303 #define sc_x1_speed_override2_r_type_BAD_R_TYPE 15 11304 #define sc_x1_speed_override2_r_type_R_TYPE_B0 11 11305 #define sc_x1_speed_override2_r_type_R_TYPE_OB 10 11306 #define sc_x1_speed_override2_r_type_R_TYPE_B1 9 11307 #define sc_x1_speed_override2_r_type_R_TYPE_DB 8 11308 #define sc_x1_speed_override2_r_type_R_TYPE_FC 7 11309 #define sc_x1_speed_override2_r_type_R_TYPE_TB 6 11310 #define sc_x1_speed_override2_r_type_R_TYPE_LI 5 11311 #define sc_x1_speed_override2_r_type_R_TYPE_C 4 11312 #define sc_x1_speed_override2_r_type_R_TYPE_S 3 11313 #define sc_x1_speed_override2_r_type_R_TYPE_T 2 11314 #define sc_x1_speed_override2_r_type_R_TYPE_D 1 11315 #define sc_x1_speed_override2_r_type_R_TYPE_E 0 11316 11317 /**************************************************************************** 11318 * Enums: sc_x1_speed_override2_am_lock_state 11319 */ 11320 #define sc_x1_speed_override2_am_lock_state_INVALID_AM 512 11321 #define sc_x1_speed_override2_am_lock_state_GOOD_AM 256 11322 #define sc_x1_speed_override2_am_lock_state_COMP_AM 128 11323 #define sc_x1_speed_override2_am_lock_state_TIMER_2 64 11324 #define sc_x1_speed_override2_am_lock_state_AM_2_GOOD 32 11325 #define sc_x1_speed_override2_am_lock_state_COMP_2ND 16 11326 #define sc_x1_speed_override2_am_lock_state_TIMER_1 8 11327 #define sc_x1_speed_override2_am_lock_state_FIND_1ST 4 11328 #define sc_x1_speed_override2_am_lock_state_AM_RESET_CNT 2 11329 #define sc_x1_speed_override2_am_lock_state_AM_LOCK_INIT 1 11330 11331 /**************************************************************************** 11332 * Enums: sc_x1_speed_override2_msg_selector 11333 */ 11334 #define sc_x1_speed_override2_msg_selector_RESERVED 0 11335 #define sc_x1_speed_override2_msg_selector_VALUE_802p3 1 11336 #define sc_x1_speed_override2_msg_selector_VALUE_802p9 2 11337 #define sc_x1_speed_override2_msg_selector_VALUE_802p5 3 11338 #define sc_x1_speed_override2_msg_selector_VALUE_1394 4 11339 11340 /**************************************************************************** 11341 * Enums: sc_x1_speed_override2_synce_enum 11342 */ 11343 #define sc_x1_speed_override2_synce_enum_SYNCE_NO_DIV 0 11344 #define sc_x1_speed_override2_synce_enum_SYNCE_DIV_7 1 11345 #define sc_x1_speed_override2_synce_enum_SYNCE_DIV_11 2 11346 11347 /**************************************************************************** 11348 * Enums: sc_x1_speed_override2_synce_enum_stage0 11349 */ 11350 #define sc_x1_speed_override2_synce_enum_stage0_SYNCE_NO_DIV 0 11351 #define sc_x1_speed_override2_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 11352 #define sc_x1_speed_override2_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 11353 11354 /**************************************************************************** 11355 * Enums: sc_x1_speed_override2_cl91_sync_state 11356 */ 11357 #define sc_x1_speed_override2_cl91_sync_state_FIND_1ST 0 11358 #define sc_x1_speed_override2_cl91_sync_state_COUNT_NEXT 1 11359 #define sc_x1_speed_override2_cl91_sync_state_COMP_2ND 2 11360 #define sc_x1_speed_override2_cl91_sync_state_TWO_GOOD 3 11361 11362 /**************************************************************************** 11363 * Enums: sc_x1_speed_override2_cl91_algn_state 11364 */ 11365 #define sc_x1_speed_override2_cl91_algn_state_LOSS_OF_ALIGNMENT 0 11366 #define sc_x1_speed_override2_cl91_algn_state_DESKEW 1 11367 #define sc_x1_speed_override2_cl91_algn_state_DESKEW_FAIL 2 11368 #define sc_x1_speed_override2_cl91_algn_state_ALIGN_ACQUIRED 3 11369 #define sc_x1_speed_override2_cl91_algn_state_CW_GOOD 4 11370 #define sc_x1_speed_override2_cl91_algn_state_CW_BAD 5 11371 #define sc_x1_speed_override2_cl91_algn_state_THREE_BAD 6 11372 11373 /**************************************************************************** 11374 * Enums: sc_x1_speed_override2_fec_sel 11375 */ 11376 #define sc_x1_speed_override2_fec_sel_NO_FEC 0 11377 #define sc_x1_speed_override2_fec_sel_FEC_CL74 1 11378 #define sc_x1_speed_override2_fec_sel_FEC_CL91 2 11379 11380 /**************************************************************************** 11381 * Enums: sc_x1_speed_override3_cl36TxEEEStates_l 11382 */ 11383 #define sc_x1_speed_override3_cl36TxEEEStates_l_TX_REFRESH 8 11384 #define sc_x1_speed_override3_cl36TxEEEStates_l_TX_QUIET 4 11385 #define sc_x1_speed_override3_cl36TxEEEStates_l_TX_SLEEP 2 11386 #define sc_x1_speed_override3_cl36TxEEEStates_l_TX_ACTIVE 1 11387 11388 /**************************************************************************** 11389 * Enums: sc_x1_speed_override3_cl36TxEEEStates_c 11390 */ 11391 #define sc_x1_speed_override3_cl36TxEEEStates_c_TX_REFRESH 3 11392 #define sc_x1_speed_override3_cl36TxEEEStates_c_TX_QUIET 2 11393 #define sc_x1_speed_override3_cl36TxEEEStates_c_TX_SLEEP 1 11394 #define sc_x1_speed_override3_cl36TxEEEStates_c_TX_ACTIVE 0 11395 11396 /**************************************************************************** 11397 * Enums: sc_x1_speed_override3_cl49TxEEEStates_l 11398 */ 11399 #define sc_x1_speed_override3_cl49TxEEEStates_l_SCR_RESET_2 64 11400 #define sc_x1_speed_override3_cl49TxEEEStates_l_SCR_RESET_1 32 11401 #define sc_x1_speed_override3_cl49TxEEEStates_l_TX_WAKE 16 11402 #define sc_x1_speed_override3_cl49TxEEEStates_l_TX_REFRESH 8 11403 #define sc_x1_speed_override3_cl49TxEEEStates_l_TX_QUIET 4 11404 #define sc_x1_speed_override3_cl49TxEEEStates_l_TX_SLEEP 2 11405 #define sc_x1_speed_override3_cl49TxEEEStates_l_TX_ACTIVE 1 11406 11407 /**************************************************************************** 11408 * Enums: sc_x1_speed_override3_fec_req_enum 11409 */ 11410 #define sc_x1_speed_override3_fec_req_enum_FEC_not_supported 0 11411 #define sc_x1_speed_override3_fec_req_enum_FEC_supported_but_not_requested 1 11412 #define sc_x1_speed_override3_fec_req_enum_invalid_setting 2 11413 #define sc_x1_speed_override3_fec_req_enum_FEC_supported_and_requested 3 11414 11415 /**************************************************************************** 11416 * Enums: sc_x1_speed_override3_cl73_pause_enum 11417 */ 11418 #define sc_x1_speed_override3_cl73_pause_enum_No_PAUSE_ability 0 11419 #define sc_x1_speed_override3_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 11420 #define sc_x1_speed_override3_cl73_pause_enum_Symmetric_PAUSE_ability 1 11421 #define sc_x1_speed_override3_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 11422 11423 /**************************************************************************** 11424 * Enums: sc_x1_speed_override3_cl49TxEEEStates_c 11425 */ 11426 #define sc_x1_speed_override3_cl49TxEEEStates_c_SCR_RESET_2 6 11427 #define sc_x1_speed_override3_cl49TxEEEStates_c_SCR_RESET_1 5 11428 #define sc_x1_speed_override3_cl49TxEEEStates_c_TX_WAKE 4 11429 #define sc_x1_speed_override3_cl49TxEEEStates_c_TX_REFRESH 3 11430 #define sc_x1_speed_override3_cl49TxEEEStates_c_TX_QUIET 2 11431 #define sc_x1_speed_override3_cl49TxEEEStates_c_TX_SLEEP 1 11432 #define sc_x1_speed_override3_cl49TxEEEStates_c_TX_ACTIVE 0 11433 11434 /**************************************************************************** 11435 * Enums: sc_x1_speed_override3_cl36RxEEEStates_l 11436 */ 11437 #define sc_x1_speed_override3_cl36RxEEEStates_l_RX_LINK_FAIL 32 11438 #define sc_x1_speed_override3_cl36RxEEEStates_l_RX_WTF 16 11439 #define sc_x1_speed_override3_cl36RxEEEStates_l_RX_WAKE 8 11440 #define sc_x1_speed_override3_cl36RxEEEStates_l_RX_QUIET 4 11441 #define sc_x1_speed_override3_cl36RxEEEStates_l_RX_SLEEP 2 11442 #define sc_x1_speed_override3_cl36RxEEEStates_l_RX_ACTIVE 1 11443 11444 /**************************************************************************** 11445 * Enums: sc_x1_speed_override3_cl36RxEEEStates_c 11446 */ 11447 #define sc_x1_speed_override3_cl36RxEEEStates_c_RX_LINK_FAIL 5 11448 #define sc_x1_speed_override3_cl36RxEEEStates_c_RX_WTF 4 11449 #define sc_x1_speed_override3_cl36RxEEEStates_c_RX_WAKE 3 11450 #define sc_x1_speed_override3_cl36RxEEEStates_c_RX_QUIET 2 11451 #define sc_x1_speed_override3_cl36RxEEEStates_c_RX_SLEEP 1 11452 #define sc_x1_speed_override3_cl36RxEEEStates_c_RX_ACTIVE 0 11453 11454 /**************************************************************************** 11455 * Enums: sc_x1_speed_override3_cl49RxEEEStates_l 11456 */ 11457 #define sc_x1_speed_override3_cl49RxEEEStates_l_RX_LINK_FAIL 32 11458 #define sc_x1_speed_override3_cl49RxEEEStates_l_RX_WTF 16 11459 #define sc_x1_speed_override3_cl49RxEEEStates_l_RX_WAKE 8 11460 #define sc_x1_speed_override3_cl49RxEEEStates_l_RX_QUIET 4 11461 #define sc_x1_speed_override3_cl49RxEEEStates_l_RX_SLEEP 2 11462 #define sc_x1_speed_override3_cl49RxEEEStates_l_RX_ACTIVE 1 11463 11464 /**************************************************************************** 11465 * Enums: sc_x1_speed_override3_cl49RxEEEStates_c 11466 */ 11467 #define sc_x1_speed_override3_cl49RxEEEStates_c_RX_LINK_FAIL 5 11468 #define sc_x1_speed_override3_cl49RxEEEStates_c_RX_WTF 4 11469 #define sc_x1_speed_override3_cl49RxEEEStates_c_RX_WAKE 3 11470 #define sc_x1_speed_override3_cl49RxEEEStates_c_RX_QUIET 2 11471 #define sc_x1_speed_override3_cl49RxEEEStates_c_RX_SLEEP 1 11472 #define sc_x1_speed_override3_cl49RxEEEStates_c_RX_ACTIVE 0 11473 11474 /**************************************************************************** 11475 * Enums: sc_x1_speed_override3_cl48TxEEEStates_l 11476 */ 11477 #define sc_x1_speed_override3_cl48TxEEEStates_l_TX_REFRESH 8 11478 #define sc_x1_speed_override3_cl48TxEEEStates_l_TX_QUIET 4 11479 #define sc_x1_speed_override3_cl48TxEEEStates_l_TX_SLEEP 2 11480 #define sc_x1_speed_override3_cl48TxEEEStates_l_TX_ACTIVE 1 11481 11482 /**************************************************************************** 11483 * Enums: sc_x1_speed_override3_cl48TxEEEStates_c 11484 */ 11485 #define sc_x1_speed_override3_cl48TxEEEStates_c_TX_REFRESH 3 11486 #define sc_x1_speed_override3_cl48TxEEEStates_c_TX_QUIET 2 11487 #define sc_x1_speed_override3_cl48TxEEEStates_c_TX_SLEEP 1 11488 #define sc_x1_speed_override3_cl48TxEEEStates_c_TX_ACTIVE 0 11489 11490 /**************************************************************************** 11491 * Enums: sc_x1_speed_override3_cl48RxEEEStates_l 11492 */ 11493 #define sc_x1_speed_override3_cl48RxEEEStates_l_RX_LINK_FAIL 32 11494 #define sc_x1_speed_override3_cl48RxEEEStates_l_RX_WAKE 16 11495 #define sc_x1_speed_override3_cl48RxEEEStates_l_RX_QUIET 8 11496 #define sc_x1_speed_override3_cl48RxEEEStates_l_RX_DEACT 4 11497 #define sc_x1_speed_override3_cl48RxEEEStates_l_RX_SLEEP 2 11498 #define sc_x1_speed_override3_cl48RxEEEStates_l_RX_ACTIVE 1 11499 11500 /**************************************************************************** 11501 * Enums: sc_x1_speed_override3_cl48RxEEEStates_c 11502 */ 11503 #define sc_x1_speed_override3_cl48RxEEEStates_c_RX_LINK_FAIL 5 11504 #define sc_x1_speed_override3_cl48RxEEEStates_c_RX_WAKE 4 11505 #define sc_x1_speed_override3_cl48RxEEEStates_c_RX_QUIET 3 11506 #define sc_x1_speed_override3_cl48RxEEEStates_c_RX_DEACT 2 11507 #define sc_x1_speed_override3_cl48RxEEEStates_c_RX_SLEEP 1 11508 #define sc_x1_speed_override3_cl48RxEEEStates_c_RX_ACTIVE 0 11509 11510 /**************************************************************************** 11511 * Enums: sc_x1_speed_override3_IQP_Options 11512 */ 11513 #define sc_x1_speed_override3_IQP_Options_i50uA 0 11514 #define sc_x1_speed_override3_IQP_Options_i100uA 1 11515 #define sc_x1_speed_override3_IQP_Options_i150uA 2 11516 #define sc_x1_speed_override3_IQP_Options_i200uA 3 11517 #define sc_x1_speed_override3_IQP_Options_i250uA 4 11518 #define sc_x1_speed_override3_IQP_Options_i300uA 5 11519 #define sc_x1_speed_override3_IQP_Options_i350uA 6 11520 #define sc_x1_speed_override3_IQP_Options_i400uA 7 11521 #define sc_x1_speed_override3_IQP_Options_i450uA 8 11522 #define sc_x1_speed_override3_IQP_Options_i500uA 9 11523 #define sc_x1_speed_override3_IQP_Options_i550uA 10 11524 #define sc_x1_speed_override3_IQP_Options_i600uA 11 11525 #define sc_x1_speed_override3_IQP_Options_i650uA 12 11526 #define sc_x1_speed_override3_IQP_Options_i700uA 13 11527 #define sc_x1_speed_override3_IQP_Options_i750uA 14 11528 #define sc_x1_speed_override3_IQP_Options_i800uA 15 11529 11530 /**************************************************************************** 11531 * Enums: sc_x1_speed_override3_IDriver_Options 11532 */ 11533 #define sc_x1_speed_override3_IDriver_Options_v680mV 0 11534 #define sc_x1_speed_override3_IDriver_Options_v730mV 1 11535 #define sc_x1_speed_override3_IDriver_Options_v780mV 2 11536 #define sc_x1_speed_override3_IDriver_Options_v830mV 3 11537 #define sc_x1_speed_override3_IDriver_Options_v880mV 4 11538 #define sc_x1_speed_override3_IDriver_Options_v930mV 5 11539 #define sc_x1_speed_override3_IDriver_Options_v980mV 6 11540 #define sc_x1_speed_override3_IDriver_Options_v1010mV 7 11541 #define sc_x1_speed_override3_IDriver_Options_v1040mV 8 11542 #define sc_x1_speed_override3_IDriver_Options_v1060mV 9 11543 #define sc_x1_speed_override3_IDriver_Options_v1070mV 10 11544 #define sc_x1_speed_override3_IDriver_Options_v1080mV 11 11545 #define sc_x1_speed_override3_IDriver_Options_v1085mV 12 11546 #define sc_x1_speed_override3_IDriver_Options_v1090mV 13 11547 #define sc_x1_speed_override3_IDriver_Options_v1095mV 14 11548 #define sc_x1_speed_override3_IDriver_Options_v1100mV 15 11549 11550 /**************************************************************************** 11551 * Enums: sc_x1_speed_override3_operationModes 11552 */ 11553 #define sc_x1_speed_override3_operationModes_XGXS 0 11554 #define sc_x1_speed_override3_operationModes_XGXG_nCC 1 11555 #define sc_x1_speed_override3_operationModes_Indlane_OS8 4 11556 #define sc_x1_speed_override3_operationModes_IndLane_OS5 5 11557 #define sc_x1_speed_override3_operationModes_PCI 7 11558 #define sc_x1_speed_override3_operationModes_XGXS_nLQ 8 11559 #define sc_x1_speed_override3_operationModes_XGXS_nLQnCC 9 11560 #define sc_x1_speed_override3_operationModes_PBypass 10 11561 #define sc_x1_speed_override3_operationModes_PBypass_nDSK 11 11562 #define sc_x1_speed_override3_operationModes_ComboCoreMode 12 11563 #define sc_x1_speed_override3_operationModes_Clocks_off 15 11564 11565 /**************************************************************************** 11566 * Enums: sc_x1_speed_override3_actualSpeeds 11567 */ 11568 #define sc_x1_speed_override3_actualSpeeds_dr_10M 0 11569 #define sc_x1_speed_override3_actualSpeeds_dr_100M 1 11570 #define sc_x1_speed_override3_actualSpeeds_dr_1G 2 11571 #define sc_x1_speed_override3_actualSpeeds_dr_2p5G 3 11572 #define sc_x1_speed_override3_actualSpeeds_dr_5G_X4 4 11573 #define sc_x1_speed_override3_actualSpeeds_dr_6G_X4 5 11574 #define sc_x1_speed_override3_actualSpeeds_dr_10G_HiG 6 11575 #define sc_x1_speed_override3_actualSpeeds_dr_10G_CX4 7 11576 #define sc_x1_speed_override3_actualSpeeds_dr_12G_HiG 8 11577 #define sc_x1_speed_override3_actualSpeeds_dr_12p5G_X4 9 11578 #define sc_x1_speed_override3_actualSpeeds_dr_13G_X4 10 11579 #define sc_x1_speed_override3_actualSpeeds_dr_15G_X4 11 11580 #define sc_x1_speed_override3_actualSpeeds_dr_16G_X4 12 11581 #define sc_x1_speed_override3_actualSpeeds_dr_1G_KX 13 11582 #define sc_x1_speed_override3_actualSpeeds_dr_10G_KX4 14 11583 #define sc_x1_speed_override3_actualSpeeds_dr_10G_KR 15 11584 #define sc_x1_speed_override3_actualSpeeds_dr_5G 16 11585 #define sc_x1_speed_override3_actualSpeeds_dr_6p4G 17 11586 #define sc_x1_speed_override3_actualSpeeds_dr_20G_X4 18 11587 #define sc_x1_speed_override3_actualSpeeds_dr_21G_X4 19 11588 #define sc_x1_speed_override3_actualSpeeds_dr_25G_X4 20 11589 #define sc_x1_speed_override3_actualSpeeds_dr_10G_HiG_DXGXS 21 11590 #define sc_x1_speed_override3_actualSpeeds_dr_10G_DXGXS 22 11591 #define sc_x1_speed_override3_actualSpeeds_dr_10p5G_HiG_DXGXS 23 11592 #define sc_x1_speed_override3_actualSpeeds_dr_10p5G_DXGXS 24 11593 #define sc_x1_speed_override3_actualSpeeds_dr_12p773G_HiG_DXGXS 25 11594 #define sc_x1_speed_override3_actualSpeeds_dr_12p773G_DXGXS 26 11595 #define sc_x1_speed_override3_actualSpeeds_dr_10G_XFI 27 11596 #define sc_x1_speed_override3_actualSpeeds_dr_40G 28 11597 #define sc_x1_speed_override3_actualSpeeds_dr_20G_HiG_DXGXS 29 11598 #define sc_x1_speed_override3_actualSpeeds_dr_20G_DXGXS 30 11599 #define sc_x1_speed_override3_actualSpeeds_dr_10G_SFI 31 11600 #define sc_x1_speed_override3_actualSpeeds_dr_31p5G 32 11601 #define sc_x1_speed_override3_actualSpeeds_dr_32p7G 33 11602 #define sc_x1_speed_override3_actualSpeeds_dr_20G_SCR 34 11603 #define sc_x1_speed_override3_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 11604 #define sc_x1_speed_override3_actualSpeeds_dr_10G_DXGXS_SCR 36 11605 #define sc_x1_speed_override3_actualSpeeds_dr_12G_R2 37 11606 #define sc_x1_speed_override3_actualSpeeds_dr_10G_X2 38 11607 #define sc_x1_speed_override3_actualSpeeds_dr_40G_KR4 39 11608 #define sc_x1_speed_override3_actualSpeeds_dr_40G_CR4 40 11609 #define sc_x1_speed_override3_actualSpeeds_dr_100G_CR10 41 11610 #define sc_x1_speed_override3_actualSpeeds_dr_15p75G_DXGXS 44 11611 #define sc_x1_speed_override3_actualSpeeds_dr_20G_KR2 57 11612 #define sc_x1_speed_override3_actualSpeeds_dr_20G_CR2 58 11613 11614 /**************************************************************************** 11615 * Enums: sc_x1_speed_override3_actualSpeedsMisc1 11616 */ 11617 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_2500BRCM_X1 16 11618 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_5000BRCM_X4 17 11619 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_6000BRCM_X4 18 11620 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_10GHiGig_X4 19 11621 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_10GBASE_CX4 20 11622 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_12GHiGig_X4 21 11623 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 11624 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_13GHiGig_X4 23 11625 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_15GHiGig_X4 24 11626 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_16GHiGig_X4 25 11627 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_5000BRCM_X1 26 11628 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_6363BRCM_X1 27 11629 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_20GHiGig_X4 28 11630 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_21GHiGig_X4 29 11631 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 11632 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 11633 11634 /**************************************************************************** 11635 * Enums: sc_x1_speed_override3_IndLaneModes 11636 */ 11637 #define sc_x1_speed_override3_IndLaneModes_SWSDR_div2 0 11638 #define sc_x1_speed_override3_IndLaneModes_SWSDR_div1 1 11639 #define sc_x1_speed_override3_IndLaneModes_DWSDR_div2 2 11640 #define sc_x1_speed_override3_IndLaneModes_DWSDR_div1 3 11641 11642 /**************************************************************************** 11643 * Enums: sc_x1_speed_override3_prbsSelect 11644 */ 11645 #define sc_x1_speed_override3_prbsSelect_prbs7 0 11646 #define sc_x1_speed_override3_prbsSelect_prbs15 1 11647 #define sc_x1_speed_override3_prbsSelect_prbs23 2 11648 #define sc_x1_speed_override3_prbsSelect_prbs31 3 11649 11650 /**************************************************************************** 11651 * Enums: sc_x1_speed_override3_vcoDivider 11652 */ 11653 #define sc_x1_speed_override3_vcoDivider_div32 0 11654 #define sc_x1_speed_override3_vcoDivider_div36 1 11655 #define sc_x1_speed_override3_vcoDivider_div40 2 11656 #define sc_x1_speed_override3_vcoDivider_div42 3 11657 #define sc_x1_speed_override3_vcoDivider_div48 4 11658 #define sc_x1_speed_override3_vcoDivider_div50 5 11659 #define sc_x1_speed_override3_vcoDivider_div52 6 11660 #define sc_x1_speed_override3_vcoDivider_div54 7 11661 #define sc_x1_speed_override3_vcoDivider_div60 8 11662 #define sc_x1_speed_override3_vcoDivider_div64 9 11663 #define sc_x1_speed_override3_vcoDivider_div66 10 11664 #define sc_x1_speed_override3_vcoDivider_div68 11 11665 #define sc_x1_speed_override3_vcoDivider_div70 12 11666 #define sc_x1_speed_override3_vcoDivider_div80 13 11667 #define sc_x1_speed_override3_vcoDivider_div92 14 11668 #define sc_x1_speed_override3_vcoDivider_div100 15 11669 11670 /**************************************************************************** 11671 * Enums: sc_x1_speed_override3_refClkSelect 11672 */ 11673 #define sc_x1_speed_override3_refClkSelect_clk_25MHz 0 11674 #define sc_x1_speed_override3_refClkSelect_clk_100MHz 1 11675 #define sc_x1_speed_override3_refClkSelect_clk_125MHz 2 11676 #define sc_x1_speed_override3_refClkSelect_clk_156p25MHz 3 11677 #define sc_x1_speed_override3_refClkSelect_clk_187p5MHz 4 11678 #define sc_x1_speed_override3_refClkSelect_clk_161p25Mhz 5 11679 #define sc_x1_speed_override3_refClkSelect_clk_50Mhz 6 11680 #define sc_x1_speed_override3_refClkSelect_clk_106p25Mhz 7 11681 11682 /**************************************************************************** 11683 * Enums: sc_x1_speed_override3_aerMMDdevTypeSelect 11684 */ 11685 #define sc_x1_speed_override3_aerMMDdevTypeSelect_combo_core 0 11686 #define sc_x1_speed_override3_aerMMDdevTypeSelect_PMA_PMD 1 11687 #define sc_x1_speed_override3_aerMMDdevTypeSelect_PCS 3 11688 #define sc_x1_speed_override3_aerMMDdevTypeSelect_PHY 4 11689 #define sc_x1_speed_override3_aerMMDdevTypeSelect_DTE 5 11690 #define sc_x1_speed_override3_aerMMDdevTypeSelect_CL73_AN 7 11691 11692 /**************************************************************************** 11693 * Enums: sc_x1_speed_override3_aerMMDportSelect 11694 */ 11695 #define sc_x1_speed_override3_aerMMDportSelect_ln0 0 11696 #define sc_x1_speed_override3_aerMMDportSelect_ln1 1 11697 #define sc_x1_speed_override3_aerMMDportSelect_ln2 2 11698 #define sc_x1_speed_override3_aerMMDportSelect_ln3 3 11699 #define sc_x1_speed_override3_aerMMDportSelect_BCST_ln0_1_2_3 511 11700 #define sc_x1_speed_override3_aerMMDportSelect_BCST_ln0_1 512 11701 #define sc_x1_speed_override3_aerMMDportSelect_BCST_ln2_3 513 11702 11703 /**************************************************************************** 11704 * Enums: sc_x1_speed_override3_firmwareModeSelect 11705 */ 11706 #define sc_x1_speed_override3_firmwareModeSelect_DEFAULT 0 11707 #define sc_x1_speed_override3_firmwareModeSelect_SFP_OPT_LR 1 11708 #define sc_x1_speed_override3_firmwareModeSelect_SFP_DAC 2 11709 #define sc_x1_speed_override3_firmwareModeSelect_XLAUI 3 11710 #define sc_x1_speed_override3_firmwareModeSelect_LONG_CH_6G 4 11711 11712 /**************************************************************************** 11713 * Enums: sc_x1_speed_override3_tempIdxSelect 11714 */ 11715 #define sc_x1_speed_override3_tempIdxSelect_LTE__22p9C 15 11716 #define sc_x1_speed_override3_tempIdxSelect_LTE__12p6C 14 11717 #define sc_x1_speed_override3_tempIdxSelect_LTE__3p0C 13 11718 #define sc_x1_speed_override3_tempIdxSelect_LTE_6p7C 12 11719 #define sc_x1_speed_override3_tempIdxSelect_LTE_16p4C 11 11720 #define sc_x1_speed_override3_tempIdxSelect_LTE_26p6C 10 11721 #define sc_x1_speed_override3_tempIdxSelect_LTE_36p3C 9 11722 #define sc_x1_speed_override3_tempIdxSelect_LTE_46p0C 8 11723 #define sc_x1_speed_override3_tempIdxSelect_LTE_56p2C 7 11724 #define sc_x1_speed_override3_tempIdxSelect_LTE_65p9C 6 11725 #define sc_x1_speed_override3_tempIdxSelect_LTE_75p6C 5 11726 #define sc_x1_speed_override3_tempIdxSelect_LTE_85p3C 4 11727 #define sc_x1_speed_override3_tempIdxSelect_LTE_95p5C 3 11728 #define sc_x1_speed_override3_tempIdxSelect_LTE_105p2C 2 11729 #define sc_x1_speed_override3_tempIdxSelect_LTE_114p9C 1 11730 #define sc_x1_speed_override3_tempIdxSelect_LTE_125p1C 0 11731 11732 /**************************************************************************** 11733 * Enums: sc_x1_speed_override3_port_mode 11734 */ 11735 #define sc_x1_speed_override3_port_mode_QUAD_PORT 0 11736 #define sc_x1_speed_override3_port_mode_TRI_1_PORT 1 11737 #define sc_x1_speed_override3_port_mode_TRI_2_PORT 2 11738 #define sc_x1_speed_override3_port_mode_DUAL_PORT 3 11739 #define sc_x1_speed_override3_port_mode_SINGLE_PORT 4 11740 11741 /**************************************************************************** 11742 * Enums: sc_x1_speed_override3_rev_letter_enum 11743 */ 11744 #define sc_x1_speed_override3_rev_letter_enum_REV_A 0 11745 #define sc_x1_speed_override3_rev_letter_enum_REV_B 1 11746 #define sc_x1_speed_override3_rev_letter_enum_REV_C 2 11747 #define sc_x1_speed_override3_rev_letter_enum_REV_D 3 11748 11749 /**************************************************************************** 11750 * Enums: sc_x1_speed_override3_rev_number_enum 11751 */ 11752 #define sc_x1_speed_override3_rev_number_enum_REV_0 0 11753 #define sc_x1_speed_override3_rev_number_enum_REV_1 1 11754 #define sc_x1_speed_override3_rev_number_enum_REV_2 2 11755 #define sc_x1_speed_override3_rev_number_enum_REV_3 3 11756 #define sc_x1_speed_override3_rev_number_enum_REV_4 4 11757 #define sc_x1_speed_override3_rev_number_enum_REV_5 5 11758 #define sc_x1_speed_override3_rev_number_enum_REV_6 6 11759 #define sc_x1_speed_override3_rev_number_enum_REV_7 7 11760 11761 /**************************************************************************** 11762 * Enums: sc_x1_speed_override3_bonding_enum 11763 */ 11764 #define sc_x1_speed_override3_bonding_enum_WIRE_BOND 0 11765 #define sc_x1_speed_override3_bonding_enum_FLIP_CHIP 1 11766 11767 /**************************************************************************** 11768 * Enums: sc_x1_speed_override3_tech_process 11769 */ 11770 #define sc_x1_speed_override3_tech_process_PROCESS_90NM 0 11771 #define sc_x1_speed_override3_tech_process_PROCESS_65NM 1 11772 #define sc_x1_speed_override3_tech_process_PROCESS_40NM 2 11773 #define sc_x1_speed_override3_tech_process_PROCESS_28NM 3 11774 11775 /**************************************************************************** 11776 * Enums: sc_x1_speed_override3_model_num 11777 */ 11778 #define sc_x1_speed_override3_model_num_SERDES_CL73 0 11779 #define sc_x1_speed_override3_model_num_XGXS_16G 1 11780 #define sc_x1_speed_override3_model_num_HYPERCORE 2 11781 #define sc_x1_speed_override3_model_num_HYPERLITE 3 11782 #define sc_x1_speed_override3_model_num_PCIE_G2_PIPE 4 11783 #define sc_x1_speed_override3_model_num_SERDES_1p25GBd 5 11784 #define sc_x1_speed_override3_model_num_SATA2 6 11785 #define sc_x1_speed_override3_model_num_QSGMII 7 11786 #define sc_x1_speed_override3_model_num_XGXS10G 8 11787 #define sc_x1_speed_override3_model_num_WARPCORE 9 11788 #define sc_x1_speed_override3_model_num_XFICORE 10 11789 #define sc_x1_speed_override3_model_num_RXFI 11 11790 #define sc_x1_speed_override3_model_num_WARPLITE 12 11791 #define sc_x1_speed_override3_model_num_PENTACORE 13 11792 #define sc_x1_speed_override3_model_num_ESM 14 11793 #define sc_x1_speed_override3_model_num_QUAD_SGMII 15 11794 #define sc_x1_speed_override3_model_num_WARPCORE_3 16 11795 #define sc_x1_speed_override3_model_num_TSC 17 11796 #define sc_x1_speed_override3_model_num_TSC4E 18 11797 #define sc_x1_speed_override3_model_num_TSC12E 19 11798 #define sc_x1_speed_override3_model_num_TSC4F 20 11799 #define sc_x1_speed_override3_model_num_XGXS_CL73_90NM 29 11800 #define sc_x1_speed_override3_model_num_SERDES_CL73_90NM 30 11801 #define sc_x1_speed_override3_model_num_WARPCORE3 32 11802 #define sc_x1_speed_override3_model_num_WARPCORE4_TSC 33 11803 #define sc_x1_speed_override3_model_num_RXAUI 34 11804 11805 /**************************************************************************** 11806 * Enums: sc_x1_speed_override3_payload 11807 */ 11808 #define sc_x1_speed_override3_payload_REPEAT_2_BYTES 0 11809 #define sc_x1_speed_override3_payload_RAMPING 1 11810 #define sc_x1_speed_override3_payload_CL48_CRPAT 2 11811 #define sc_x1_speed_override3_payload_CL48_CJPAT 3 11812 #define sc_x1_speed_override3_payload_CL36_LONG_CRPAT 4 11813 #define sc_x1_speed_override3_payload_CL36_SHORT_CRPAT 5 11814 11815 /**************************************************************************** 11816 * Enums: sc_x1_speed_override3_sc 11817 */ 11818 #define sc_x1_speed_override3_sc_S_10G_CR1 0 11819 #define sc_x1_speed_override3_sc_S_10G_KR1 1 11820 #define sc_x1_speed_override3_sc_S_10G_X1 2 11821 #define sc_x1_speed_override3_sc_S_10G_HG2_CR1 4 11822 #define sc_x1_speed_override3_sc_S_10G_HG2_KR1 5 11823 #define sc_x1_speed_override3_sc_S_10G_HG2_X1 6 11824 #define sc_x1_speed_override3_sc_S_20G_CR1 8 11825 #define sc_x1_speed_override3_sc_S_20G_KR1 9 11826 #define sc_x1_speed_override3_sc_S_20G_X1 10 11827 #define sc_x1_speed_override3_sc_S_20G_HG2_CR1 12 11828 #define sc_x1_speed_override3_sc_S_20G_HG2_KR1 13 11829 #define sc_x1_speed_override3_sc_S_20G_HG2_X1 14 11830 #define sc_x1_speed_override3_sc_S_25G_CR1 16 11831 #define sc_x1_speed_override3_sc_S_25G_KR1 17 11832 #define sc_x1_speed_override3_sc_S_25G_X1 18 11833 #define sc_x1_speed_override3_sc_S_25G_HG2_CR1 20 11834 #define sc_x1_speed_override3_sc_S_25G_HG2_KR1 21 11835 #define sc_x1_speed_override3_sc_S_25G_HG2_X1 22 11836 #define sc_x1_speed_override3_sc_S_20G_CR2 24 11837 #define sc_x1_speed_override3_sc_S_20G_KR2 25 11838 #define sc_x1_speed_override3_sc_S_20G_X2 26 11839 #define sc_x1_speed_override3_sc_S_20G_HG2_CR2 28 11840 #define sc_x1_speed_override3_sc_S_20G_HG2_KR2 29 11841 #define sc_x1_speed_override3_sc_S_20G_HG2_X2 30 11842 #define sc_x1_speed_override3_sc_S_40G_CR2 32 11843 #define sc_x1_speed_override3_sc_S_40G_KR2 33 11844 #define sc_x1_speed_override3_sc_S_40G_X2 34 11845 #define sc_x1_speed_override3_sc_S_40G_HG2_CR2 36 11846 #define sc_x1_speed_override3_sc_S_40G_HG2_KR2 37 11847 #define sc_x1_speed_override3_sc_S_40G_HG2_X2 38 11848 #define sc_x1_speed_override3_sc_S_40G_CR4 40 11849 #define sc_x1_speed_override3_sc_S_40G_KR4 41 11850 #define sc_x1_speed_override3_sc_S_40G_X4 42 11851 #define sc_x1_speed_override3_sc_S_40G_HG2_CR4 44 11852 #define sc_x1_speed_override3_sc_S_40G_HG2_KR4 45 11853 #define sc_x1_speed_override3_sc_S_40G_HG2_X4 46 11854 #define sc_x1_speed_override3_sc_S_50G_CR2 48 11855 #define sc_x1_speed_override3_sc_S_50G_KR2 49 11856 #define sc_x1_speed_override3_sc_S_50G_X2 50 11857 #define sc_x1_speed_override3_sc_S_50G_HG2_CR2 52 11858 #define sc_x1_speed_override3_sc_S_50G_HG2_KR2 53 11859 #define sc_x1_speed_override3_sc_S_50G_HG2_X2 54 11860 #define sc_x1_speed_override3_sc_S_50G_CR4 56 11861 #define sc_x1_speed_override3_sc_S_50G_KR4 57 11862 #define sc_x1_speed_override3_sc_S_50G_X4 58 11863 #define sc_x1_speed_override3_sc_S_50G_HG2_CR4 60 11864 #define sc_x1_speed_override3_sc_S_50G_HG2_KR4 61 11865 #define sc_x1_speed_override3_sc_S_50G_HG2_X4 62 11866 #define sc_x1_speed_override3_sc_S_100G_CR4 64 11867 #define sc_x1_speed_override3_sc_S_100G_KR4 65 11868 #define sc_x1_speed_override3_sc_S_100G_X4 66 11869 #define sc_x1_speed_override3_sc_S_100G_HG2_CR4 68 11870 #define sc_x1_speed_override3_sc_S_100G_HG2_KR4 69 11871 #define sc_x1_speed_override3_sc_S_100G_HG2_X4 70 11872 #define sc_x1_speed_override3_sc_S_CL73_20GVCO 72 11873 #define sc_x1_speed_override3_sc_S_CL73_25GVCO 80 11874 #define sc_x1_speed_override3_sc_S_CL36_20GVCO 88 11875 #define sc_x1_speed_override3_sc_S_CL36_25GVCO 96 11876 11877 /**************************************************************************** 11878 * Enums: sc_x1_speed_override3_t_fifo_modes 11879 */ 11880 #define sc_x1_speed_override3_t_fifo_modes_T_FIFO_MODE_BYPASS 0 11881 #define sc_x1_speed_override3_t_fifo_modes_T_FIFO_MODE_40G 1 11882 #define sc_x1_speed_override3_t_fifo_modes_T_FIFO_MODE_100G 2 11883 #define sc_x1_speed_override3_t_fifo_modes_T_FIFO_MODE_20G 3 11884 11885 /**************************************************************************** 11886 * Enums: sc_x1_speed_override3_t_enc_modes 11887 */ 11888 #define sc_x1_speed_override3_t_enc_modes_T_ENC_MODE_BYPASS 0 11889 #define sc_x1_speed_override3_t_enc_modes_T_ENC_MODE_CL49 1 11890 #define sc_x1_speed_override3_t_enc_modes_T_ENC_MODE_CL82 2 11891 11892 /**************************************************************************** 11893 * Enums: sc_x1_speed_override3_btmx_mode 11894 */ 11895 #define sc_x1_speed_override3_btmx_mode_BS_BTMX_MODE_1to1 0 11896 #define sc_x1_speed_override3_btmx_mode_BS_BTMX_MODE_2to1 1 11897 #define sc_x1_speed_override3_btmx_mode_BS_BTMX_MODE_5to1 2 11898 11899 /**************************************************************************** 11900 * Enums: sc_x1_speed_override3_t_type_cl82 11901 */ 11902 #define sc_x1_speed_override3_t_type_cl82_T_TYPE_B1 5 11903 #define sc_x1_speed_override3_t_type_cl82_T_TYPE_C 4 11904 #define sc_x1_speed_override3_t_type_cl82_T_TYPE_S 3 11905 #define sc_x1_speed_override3_t_type_cl82_T_TYPE_T 2 11906 #define sc_x1_speed_override3_t_type_cl82_T_TYPE_D 1 11907 #define sc_x1_speed_override3_t_type_cl82_T_TYPE_E 0 11908 11909 /**************************************************************************** 11910 * Enums: sc_x1_speed_override3_txsm_state_cl82 11911 */ 11912 #define sc_x1_speed_override3_txsm_state_cl82_TX_HIG_END 6 11913 #define sc_x1_speed_override3_txsm_state_cl82_TX_HIG_START 5 11914 #define sc_x1_speed_override3_txsm_state_cl82_TX_E 4 11915 #define sc_x1_speed_override3_txsm_state_cl82_TX_T 3 11916 #define sc_x1_speed_override3_txsm_state_cl82_TX_D 2 11917 #define sc_x1_speed_override3_txsm_state_cl82_TX_C 1 11918 #define sc_x1_speed_override3_txsm_state_cl82_TX_INIT 0 11919 11920 /**************************************************************************** 11921 * Enums: sc_x1_speed_override3_ltxsm_state_cl82 11922 */ 11923 #define sc_x1_speed_override3_ltxsm_state_cl82_TX_HIG_END 64 11924 #define sc_x1_speed_override3_ltxsm_state_cl82_TX_HIG_START 32 11925 #define sc_x1_speed_override3_ltxsm_state_cl82_TX_E 16 11926 #define sc_x1_speed_override3_ltxsm_state_cl82_TX_T 8 11927 #define sc_x1_speed_override3_ltxsm_state_cl82_TX_D 4 11928 #define sc_x1_speed_override3_ltxsm_state_cl82_TX_C 2 11929 #define sc_x1_speed_override3_ltxsm_state_cl82_TX_INIT 1 11930 11931 /**************************************************************************** 11932 * Enums: sc_x1_speed_override3_r_type_coded_cl82 11933 */ 11934 #define sc_x1_speed_override3_r_type_coded_cl82_R_TYPE_B1 32 11935 #define sc_x1_speed_override3_r_type_coded_cl82_R_TYPE_C 16 11936 #define sc_x1_speed_override3_r_type_coded_cl82_R_TYPE_S 8 11937 #define sc_x1_speed_override3_r_type_coded_cl82_R_TYPE_T 4 11938 #define sc_x1_speed_override3_r_type_coded_cl82_R_TYPE_D 2 11939 #define sc_x1_speed_override3_r_type_coded_cl82_R_TYPE_E 1 11940 11941 /**************************************************************************** 11942 * Enums: sc_x1_speed_override3_rxsm_state_cl82 11943 */ 11944 #define sc_x1_speed_override3_rxsm_state_cl82_RX_HIG_END 64 11945 #define sc_x1_speed_override3_rxsm_state_cl82_RX_HIG_START 32 11946 #define sc_x1_speed_override3_rxsm_state_cl82_RX_E 16 11947 #define sc_x1_speed_override3_rxsm_state_cl82_RX_T 8 11948 #define sc_x1_speed_override3_rxsm_state_cl82_RX_D 4 11949 #define sc_x1_speed_override3_rxsm_state_cl82_RX_C 2 11950 #define sc_x1_speed_override3_rxsm_state_cl82_RX_INIT 1 11951 11952 /**************************************************************************** 11953 * Enums: sc_x1_speed_override3_deskew_state 11954 */ 11955 #define sc_x1_speed_override3_deskew_state_ALIGN_ACQUIRED 2 11956 #define sc_x1_speed_override3_deskew_state_LOSS_OF_ALIGNMENT 1 11957 11958 /**************************************************************************** 11959 * Enums: sc_x1_speed_override3_os_mode_enum 11960 */ 11961 #define sc_x1_speed_override3_os_mode_enum_OS_MODE_1 0 11962 #define sc_x1_speed_override3_os_mode_enum_OS_MODE_2 1 11963 #define sc_x1_speed_override3_os_mode_enum_OS_MODE_4 2 11964 #define sc_x1_speed_override3_os_mode_enum_OS_MODE_16p5 8 11965 #define sc_x1_speed_override3_os_mode_enum_OS_MODE_20p625 12 11966 11967 /**************************************************************************** 11968 * Enums: sc_x1_speed_override3_scr_modes 11969 */ 11970 #define sc_x1_speed_override3_scr_modes_T_SCR_MODE_BYPASS 0 11971 #define sc_x1_speed_override3_scr_modes_T_SCR_MODE_CL49 1 11972 #define sc_x1_speed_override3_scr_modes_T_SCR_MODE_40G_2_LANE 2 11973 #define sc_x1_speed_override3_scr_modes_T_SCR_MODE_100G 3 11974 #define sc_x1_speed_override3_scr_modes_T_SCR_MODE_20G 4 11975 #define sc_x1_speed_override3_scr_modes_T_SCR_MODE_40G_4_LANE 5 11976 11977 /**************************************************************************** 11978 * Enums: sc_x1_speed_override3_descr_modes 11979 */ 11980 #define sc_x1_speed_override3_descr_modes_R_DESCR_MODE_BYPASS 0 11981 #define sc_x1_speed_override3_descr_modes_R_DESCR_MODE_CL49 1 11982 #define sc_x1_speed_override3_descr_modes_R_DESCR_MODE_CL82 2 11983 11984 /**************************************************************************** 11985 * Enums: sc_x1_speed_override3_r_dec_tl_mode 11986 */ 11987 #define sc_x1_speed_override3_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 11988 #define sc_x1_speed_override3_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 11989 #define sc_x1_speed_override3_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 11990 11991 /**************************************************************************** 11992 * Enums: sc_x1_speed_override3_r_dec_fsm_mode 11993 */ 11994 #define sc_x1_speed_override3_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 11995 #define sc_x1_speed_override3_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 11996 #define sc_x1_speed_override3_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 11997 11998 /**************************************************************************** 11999 * Enums: sc_x1_speed_override3_r_deskew_mode 12000 */ 12001 #define sc_x1_speed_override3_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 12002 #define sc_x1_speed_override3_r_deskew_mode_R_DESKEW_MODE_20G 1 12003 #define sc_x1_speed_override3_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 12004 #define sc_x1_speed_override3_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 12005 #define sc_x1_speed_override3_r_deskew_mode_R_DESKEW_MODE_100G 4 12006 #define sc_x1_speed_override3_r_deskew_mode_R_DESKEW_MODE_CL49 5 12007 #define sc_x1_speed_override3_r_deskew_mode_R_DESKEW_MODE_CL91 6 12008 12009 /**************************************************************************** 12010 * Enums: sc_x1_speed_override3_bs_dist_modes 12011 */ 12012 #define sc_x1_speed_override3_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 12013 #define sc_x1_speed_override3_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 12014 #define sc_x1_speed_override3_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 12015 #define sc_x1_speed_override3_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 12016 12017 /**************************************************************************** 12018 * Enums: sc_x1_speed_override3_cl49_t_type 12019 */ 12020 #define sc_x1_speed_override3_cl49_t_type_BAD_T_TYPE 15 12021 #define sc_x1_speed_override3_cl49_t_type_T_TYPE_B0 11 12022 #define sc_x1_speed_override3_cl49_t_type_T_TYPE_OB 10 12023 #define sc_x1_speed_override3_cl49_t_type_T_TYPE_B1 9 12024 #define sc_x1_speed_override3_cl49_t_type_T_TYPE_DB 8 12025 #define sc_x1_speed_override3_cl49_t_type_T_TYPE_FC 7 12026 #define sc_x1_speed_override3_cl49_t_type_T_TYPE_TB 6 12027 #define sc_x1_speed_override3_cl49_t_type_T_TYPE_LI 5 12028 #define sc_x1_speed_override3_cl49_t_type_T_TYPE_C 4 12029 #define sc_x1_speed_override3_cl49_t_type_T_TYPE_S 3 12030 #define sc_x1_speed_override3_cl49_t_type_T_TYPE_T 2 12031 #define sc_x1_speed_override3_cl49_t_type_T_TYPE_D 1 12032 #define sc_x1_speed_override3_cl49_t_type_T_TYPE_E 0 12033 12034 /**************************************************************************** 12035 * Enums: sc_x1_speed_override3_cl49_txsm_states 12036 */ 12037 #define sc_x1_speed_override3_cl49_txsm_states_TX_HIG_END 7 12038 #define sc_x1_speed_override3_cl49_txsm_states_TX_HIG_START 6 12039 #define sc_x1_speed_override3_cl49_txsm_states_TX_LI 5 12040 #define sc_x1_speed_override3_cl49_txsm_states_TX_E 4 12041 #define sc_x1_speed_override3_cl49_txsm_states_TX_T 3 12042 #define sc_x1_speed_override3_cl49_txsm_states_TX_D 2 12043 #define sc_x1_speed_override3_cl49_txsm_states_TX_C 1 12044 #define sc_x1_speed_override3_cl49_txsm_states_TX_INIT 0 12045 12046 /**************************************************************************** 12047 * Enums: sc_x1_speed_override3_cl49_ltxsm_states 12048 */ 12049 #define sc_x1_speed_override3_cl49_ltxsm_states_TX_HIG_END 128 12050 #define sc_x1_speed_override3_cl49_ltxsm_states_TX_HIG_START 64 12051 #define sc_x1_speed_override3_cl49_ltxsm_states_TX_LI 32 12052 #define sc_x1_speed_override3_cl49_ltxsm_states_TX_E 16 12053 #define sc_x1_speed_override3_cl49_ltxsm_states_TX_T 8 12054 #define sc_x1_speed_override3_cl49_ltxsm_states_TX_D 4 12055 #define sc_x1_speed_override3_cl49_ltxsm_states_TX_C 2 12056 #define sc_x1_speed_override3_cl49_ltxsm_states_TX_INIT 1 12057 12058 /**************************************************************************** 12059 * Enums: sc_x1_speed_override3_burst_error_mode 12060 */ 12061 #define sc_x1_speed_override3_burst_error_mode_BURST_ERROR_11_BITS 0 12062 #define sc_x1_speed_override3_burst_error_mode_BURST_ERROR_16_BITS 1 12063 #define sc_x1_speed_override3_burst_error_mode_BURST_ERROR_17_BITS 2 12064 #define sc_x1_speed_override3_burst_error_mode_BURST_ERROR_18_BITS 3 12065 #define sc_x1_speed_override3_burst_error_mode_BURST_ERROR_19_BITS 4 12066 #define sc_x1_speed_override3_burst_error_mode_BURST_ERROR_20_BITS 5 12067 #define sc_x1_speed_override3_burst_error_mode_BURST_ERROR_21_BITS 6 12068 #define sc_x1_speed_override3_burst_error_mode_BURST_ERROR_22_BITS 7 12069 #define sc_x1_speed_override3_burst_error_mode_BURST_ERROR_23_BITS 8 12070 #define sc_x1_speed_override3_burst_error_mode_BURST_ERROR_24_BITS 9 12071 #define sc_x1_speed_override3_burst_error_mode_BURST_ERROR_25_BITS 10 12072 #define sc_x1_speed_override3_burst_error_mode_BURST_ERROR_26_BITS 11 12073 #define sc_x1_speed_override3_burst_error_mode_BURST_ERROR_27_BITS 12 12074 #define sc_x1_speed_override3_burst_error_mode_BURST_ERROR_28_BITS 13 12075 #define sc_x1_speed_override3_burst_error_mode_BURST_ERROR_29_BITS 14 12076 #define sc_x1_speed_override3_burst_error_mode_BURST_ERROR_30_BITS 15 12077 #define sc_x1_speed_override3_burst_error_mode_BURST_ERROR_31_BITS 16 12078 #define sc_x1_speed_override3_burst_error_mode_BURST_ERROR_32_BITS 17 12079 #define sc_x1_speed_override3_burst_error_mode_BURST_ERROR_33_BITS 18 12080 #define sc_x1_speed_override3_burst_error_mode_BURST_ERROR_34_BITS 19 12081 #define sc_x1_speed_override3_burst_error_mode_BURST_ERROR_35_BITS 20 12082 #define sc_x1_speed_override3_burst_error_mode_BURST_ERROR_36_BITS 21 12083 #define sc_x1_speed_override3_burst_error_mode_BURST_ERROR_37_BITS 22 12084 #define sc_x1_speed_override3_burst_error_mode_BURST_ERROR_38_BITS 23 12085 #define sc_x1_speed_override3_burst_error_mode_BURST_ERROR_39_BITS 24 12086 #define sc_x1_speed_override3_burst_error_mode_BURST_ERROR_40_BITS 25 12087 #define sc_x1_speed_override3_burst_error_mode_BURST_ERROR_41_BITS 26 12088 12089 /**************************************************************************** 12090 * Enums: sc_x1_speed_override3_bermon_state 12091 */ 12092 #define sc_x1_speed_override3_bermon_state_HI_BER 4 12093 #define sc_x1_speed_override3_bermon_state_GOOD_BER 3 12094 #define sc_x1_speed_override3_bermon_state_BER_TEST_SH 2 12095 #define sc_x1_speed_override3_bermon_state_START_TIMER 1 12096 #define sc_x1_speed_override3_bermon_state_BER_MT_INIT 0 12097 12098 /**************************************************************************** 12099 * Enums: sc_x1_speed_override3_rxsm_state_cl49 12100 */ 12101 #define sc_x1_speed_override3_rxsm_state_cl49_RX_HIG_END 128 12102 #define sc_x1_speed_override3_rxsm_state_cl49_RX_HIG_START 64 12103 #define sc_x1_speed_override3_rxsm_state_cl49_RX_LI 32 12104 #define sc_x1_speed_override3_rxsm_state_cl49_RX_E 16 12105 #define sc_x1_speed_override3_rxsm_state_cl49_RX_T 8 12106 #define sc_x1_speed_override3_rxsm_state_cl49_RX_D 4 12107 #define sc_x1_speed_override3_rxsm_state_cl49_RX_C 2 12108 #define sc_x1_speed_override3_rxsm_state_cl49_RX_INIT 1 12109 12110 /**************************************************************************** 12111 * Enums: sc_x1_speed_override3_r_type 12112 */ 12113 #define sc_x1_speed_override3_r_type_BAD_R_TYPE 15 12114 #define sc_x1_speed_override3_r_type_R_TYPE_B0 11 12115 #define sc_x1_speed_override3_r_type_R_TYPE_OB 10 12116 #define sc_x1_speed_override3_r_type_R_TYPE_B1 9 12117 #define sc_x1_speed_override3_r_type_R_TYPE_DB 8 12118 #define sc_x1_speed_override3_r_type_R_TYPE_FC 7 12119 #define sc_x1_speed_override3_r_type_R_TYPE_TB 6 12120 #define sc_x1_speed_override3_r_type_R_TYPE_LI 5 12121 #define sc_x1_speed_override3_r_type_R_TYPE_C 4 12122 #define sc_x1_speed_override3_r_type_R_TYPE_S 3 12123 #define sc_x1_speed_override3_r_type_R_TYPE_T 2 12124 #define sc_x1_speed_override3_r_type_R_TYPE_D 1 12125 #define sc_x1_speed_override3_r_type_R_TYPE_E 0 12126 12127 /**************************************************************************** 12128 * Enums: sc_x1_speed_override3_am_lock_state 12129 */ 12130 #define sc_x1_speed_override3_am_lock_state_INVALID_AM 512 12131 #define sc_x1_speed_override3_am_lock_state_GOOD_AM 256 12132 #define sc_x1_speed_override3_am_lock_state_COMP_AM 128 12133 #define sc_x1_speed_override3_am_lock_state_TIMER_2 64 12134 #define sc_x1_speed_override3_am_lock_state_AM_2_GOOD 32 12135 #define sc_x1_speed_override3_am_lock_state_COMP_2ND 16 12136 #define sc_x1_speed_override3_am_lock_state_TIMER_1 8 12137 #define sc_x1_speed_override3_am_lock_state_FIND_1ST 4 12138 #define sc_x1_speed_override3_am_lock_state_AM_RESET_CNT 2 12139 #define sc_x1_speed_override3_am_lock_state_AM_LOCK_INIT 1 12140 12141 /**************************************************************************** 12142 * Enums: sc_x1_speed_override3_msg_selector 12143 */ 12144 #define sc_x1_speed_override3_msg_selector_RESERVED 0 12145 #define sc_x1_speed_override3_msg_selector_VALUE_802p3 1 12146 #define sc_x1_speed_override3_msg_selector_VALUE_802p9 2 12147 #define sc_x1_speed_override3_msg_selector_VALUE_802p5 3 12148 #define sc_x1_speed_override3_msg_selector_VALUE_1394 4 12149 12150 /**************************************************************************** 12151 * Enums: sc_x1_speed_override3_synce_enum 12152 */ 12153 #define sc_x1_speed_override3_synce_enum_SYNCE_NO_DIV 0 12154 #define sc_x1_speed_override3_synce_enum_SYNCE_DIV_7 1 12155 #define sc_x1_speed_override3_synce_enum_SYNCE_DIV_11 2 12156 12157 /**************************************************************************** 12158 * Enums: sc_x1_speed_override3_synce_enum_stage0 12159 */ 12160 #define sc_x1_speed_override3_synce_enum_stage0_SYNCE_NO_DIV 0 12161 #define sc_x1_speed_override3_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 12162 #define sc_x1_speed_override3_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 12163 12164 /**************************************************************************** 12165 * Enums: sc_x1_speed_override3_cl91_sync_state 12166 */ 12167 #define sc_x1_speed_override3_cl91_sync_state_FIND_1ST 0 12168 #define sc_x1_speed_override3_cl91_sync_state_COUNT_NEXT 1 12169 #define sc_x1_speed_override3_cl91_sync_state_COMP_2ND 2 12170 #define sc_x1_speed_override3_cl91_sync_state_TWO_GOOD 3 12171 12172 /**************************************************************************** 12173 * Enums: sc_x1_speed_override3_cl91_algn_state 12174 */ 12175 #define sc_x1_speed_override3_cl91_algn_state_LOSS_OF_ALIGNMENT 0 12176 #define sc_x1_speed_override3_cl91_algn_state_DESKEW 1 12177 #define sc_x1_speed_override3_cl91_algn_state_DESKEW_FAIL 2 12178 #define sc_x1_speed_override3_cl91_algn_state_ALIGN_ACQUIRED 3 12179 #define sc_x1_speed_override3_cl91_algn_state_CW_GOOD 4 12180 #define sc_x1_speed_override3_cl91_algn_state_CW_BAD 5 12181 #define sc_x1_speed_override3_cl91_algn_state_THREE_BAD 6 12182 12183 /**************************************************************************** 12184 * Enums: sc_x1_speed_override3_fec_sel 12185 */ 12186 #define sc_x1_speed_override3_fec_sel_NO_FEC 0 12187 #define sc_x1_speed_override3_fec_sel_FEC_CL74 1 12188 #define sc_x1_speed_override3_fec_sel_FEC_CL91 2 12189 12190 /**************************************************************************** 12191 * Enums: sc_x4_control_cl36TxEEEStates_l 12192 */ 12193 #define sc_x4_control_cl36TxEEEStates_l_TX_REFRESH 8 12194 #define sc_x4_control_cl36TxEEEStates_l_TX_QUIET 4 12195 #define sc_x4_control_cl36TxEEEStates_l_TX_SLEEP 2 12196 #define sc_x4_control_cl36TxEEEStates_l_TX_ACTIVE 1 12197 12198 /**************************************************************************** 12199 * Enums: sc_x4_control_cl36TxEEEStates_c 12200 */ 12201 #define sc_x4_control_cl36TxEEEStates_c_TX_REFRESH 3 12202 #define sc_x4_control_cl36TxEEEStates_c_TX_QUIET 2 12203 #define sc_x4_control_cl36TxEEEStates_c_TX_SLEEP 1 12204 #define sc_x4_control_cl36TxEEEStates_c_TX_ACTIVE 0 12205 12206 /**************************************************************************** 12207 * Enums: sc_x4_control_cl49TxEEEStates_l 12208 */ 12209 #define sc_x4_control_cl49TxEEEStates_l_SCR_RESET_2 64 12210 #define sc_x4_control_cl49TxEEEStates_l_SCR_RESET_1 32 12211 #define sc_x4_control_cl49TxEEEStates_l_TX_WAKE 16 12212 #define sc_x4_control_cl49TxEEEStates_l_TX_REFRESH 8 12213 #define sc_x4_control_cl49TxEEEStates_l_TX_QUIET 4 12214 #define sc_x4_control_cl49TxEEEStates_l_TX_SLEEP 2 12215 #define sc_x4_control_cl49TxEEEStates_l_TX_ACTIVE 1 12216 12217 /**************************************************************************** 12218 * Enums: sc_x4_control_fec_req_enum 12219 */ 12220 #define sc_x4_control_fec_req_enum_FEC_not_supported 0 12221 #define sc_x4_control_fec_req_enum_FEC_supported_but_not_requested 1 12222 #define sc_x4_control_fec_req_enum_invalid_setting 2 12223 #define sc_x4_control_fec_req_enum_FEC_supported_and_requested 3 12224 12225 /**************************************************************************** 12226 * Enums: sc_x4_control_cl73_pause_enum 12227 */ 12228 #define sc_x4_control_cl73_pause_enum_No_PAUSE_ability 0 12229 #define sc_x4_control_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 12230 #define sc_x4_control_cl73_pause_enum_Symmetric_PAUSE_ability 1 12231 #define sc_x4_control_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 12232 12233 /**************************************************************************** 12234 * Enums: sc_x4_control_cl49TxEEEStates_c 12235 */ 12236 #define sc_x4_control_cl49TxEEEStates_c_SCR_RESET_2 6 12237 #define sc_x4_control_cl49TxEEEStates_c_SCR_RESET_1 5 12238 #define sc_x4_control_cl49TxEEEStates_c_TX_WAKE 4 12239 #define sc_x4_control_cl49TxEEEStates_c_TX_REFRESH 3 12240 #define sc_x4_control_cl49TxEEEStates_c_TX_QUIET 2 12241 #define sc_x4_control_cl49TxEEEStates_c_TX_SLEEP 1 12242 #define sc_x4_control_cl49TxEEEStates_c_TX_ACTIVE 0 12243 12244 /**************************************************************************** 12245 * Enums: sc_x4_control_cl36RxEEEStates_l 12246 */ 12247 #define sc_x4_control_cl36RxEEEStates_l_RX_LINK_FAIL 32 12248 #define sc_x4_control_cl36RxEEEStates_l_RX_WTF 16 12249 #define sc_x4_control_cl36RxEEEStates_l_RX_WAKE 8 12250 #define sc_x4_control_cl36RxEEEStates_l_RX_QUIET 4 12251 #define sc_x4_control_cl36RxEEEStates_l_RX_SLEEP 2 12252 #define sc_x4_control_cl36RxEEEStates_l_RX_ACTIVE 1 12253 12254 /**************************************************************************** 12255 * Enums: sc_x4_control_cl36RxEEEStates_c 12256 */ 12257 #define sc_x4_control_cl36RxEEEStates_c_RX_LINK_FAIL 5 12258 #define sc_x4_control_cl36RxEEEStates_c_RX_WTF 4 12259 #define sc_x4_control_cl36RxEEEStates_c_RX_WAKE 3 12260 #define sc_x4_control_cl36RxEEEStates_c_RX_QUIET 2 12261 #define sc_x4_control_cl36RxEEEStates_c_RX_SLEEP 1 12262 #define sc_x4_control_cl36RxEEEStates_c_RX_ACTIVE 0 12263 12264 /**************************************************************************** 12265 * Enums: sc_x4_control_cl49RxEEEStates_l 12266 */ 12267 #define sc_x4_control_cl49RxEEEStates_l_RX_LINK_FAIL 32 12268 #define sc_x4_control_cl49RxEEEStates_l_RX_WTF 16 12269 #define sc_x4_control_cl49RxEEEStates_l_RX_WAKE 8 12270 #define sc_x4_control_cl49RxEEEStates_l_RX_QUIET 4 12271 #define sc_x4_control_cl49RxEEEStates_l_RX_SLEEP 2 12272 #define sc_x4_control_cl49RxEEEStates_l_RX_ACTIVE 1 12273 12274 /**************************************************************************** 12275 * Enums: sc_x4_control_cl49RxEEEStates_c 12276 */ 12277 #define sc_x4_control_cl49RxEEEStates_c_RX_LINK_FAIL 5 12278 #define sc_x4_control_cl49RxEEEStates_c_RX_WTF 4 12279 #define sc_x4_control_cl49RxEEEStates_c_RX_WAKE 3 12280 #define sc_x4_control_cl49RxEEEStates_c_RX_QUIET 2 12281 #define sc_x4_control_cl49RxEEEStates_c_RX_SLEEP 1 12282 #define sc_x4_control_cl49RxEEEStates_c_RX_ACTIVE 0 12283 12284 /**************************************************************************** 12285 * Enums: sc_x4_control_cl48TxEEEStates_l 12286 */ 12287 #define sc_x4_control_cl48TxEEEStates_l_TX_REFRESH 8 12288 #define sc_x4_control_cl48TxEEEStates_l_TX_QUIET 4 12289 #define sc_x4_control_cl48TxEEEStates_l_TX_SLEEP 2 12290 #define sc_x4_control_cl48TxEEEStates_l_TX_ACTIVE 1 12291 12292 /**************************************************************************** 12293 * Enums: sc_x4_control_cl48TxEEEStates_c 12294 */ 12295 #define sc_x4_control_cl48TxEEEStates_c_TX_REFRESH 3 12296 #define sc_x4_control_cl48TxEEEStates_c_TX_QUIET 2 12297 #define sc_x4_control_cl48TxEEEStates_c_TX_SLEEP 1 12298 #define sc_x4_control_cl48TxEEEStates_c_TX_ACTIVE 0 12299 12300 /**************************************************************************** 12301 * Enums: sc_x4_control_cl48RxEEEStates_l 12302 */ 12303 #define sc_x4_control_cl48RxEEEStates_l_RX_LINK_FAIL 32 12304 #define sc_x4_control_cl48RxEEEStates_l_RX_WAKE 16 12305 #define sc_x4_control_cl48RxEEEStates_l_RX_QUIET 8 12306 #define sc_x4_control_cl48RxEEEStates_l_RX_DEACT 4 12307 #define sc_x4_control_cl48RxEEEStates_l_RX_SLEEP 2 12308 #define sc_x4_control_cl48RxEEEStates_l_RX_ACTIVE 1 12309 12310 /**************************************************************************** 12311 * Enums: sc_x4_control_cl48RxEEEStates_c 12312 */ 12313 #define sc_x4_control_cl48RxEEEStates_c_RX_LINK_FAIL 5 12314 #define sc_x4_control_cl48RxEEEStates_c_RX_WAKE 4 12315 #define sc_x4_control_cl48RxEEEStates_c_RX_QUIET 3 12316 #define sc_x4_control_cl48RxEEEStates_c_RX_DEACT 2 12317 #define sc_x4_control_cl48RxEEEStates_c_RX_SLEEP 1 12318 #define sc_x4_control_cl48RxEEEStates_c_RX_ACTIVE 0 12319 12320 /**************************************************************************** 12321 * Enums: sc_x4_control_IQP_Options 12322 */ 12323 #define sc_x4_control_IQP_Options_i50uA 0 12324 #define sc_x4_control_IQP_Options_i100uA 1 12325 #define sc_x4_control_IQP_Options_i150uA 2 12326 #define sc_x4_control_IQP_Options_i200uA 3 12327 #define sc_x4_control_IQP_Options_i250uA 4 12328 #define sc_x4_control_IQP_Options_i300uA 5 12329 #define sc_x4_control_IQP_Options_i350uA 6 12330 #define sc_x4_control_IQP_Options_i400uA 7 12331 #define sc_x4_control_IQP_Options_i450uA 8 12332 #define sc_x4_control_IQP_Options_i500uA 9 12333 #define sc_x4_control_IQP_Options_i550uA 10 12334 #define sc_x4_control_IQP_Options_i600uA 11 12335 #define sc_x4_control_IQP_Options_i650uA 12 12336 #define sc_x4_control_IQP_Options_i700uA 13 12337 #define sc_x4_control_IQP_Options_i750uA 14 12338 #define sc_x4_control_IQP_Options_i800uA 15 12339 12340 /**************************************************************************** 12341 * Enums: sc_x4_control_IDriver_Options 12342 */ 12343 #define sc_x4_control_IDriver_Options_v680mV 0 12344 #define sc_x4_control_IDriver_Options_v730mV 1 12345 #define sc_x4_control_IDriver_Options_v780mV 2 12346 #define sc_x4_control_IDriver_Options_v830mV 3 12347 #define sc_x4_control_IDriver_Options_v880mV 4 12348 #define sc_x4_control_IDriver_Options_v930mV 5 12349 #define sc_x4_control_IDriver_Options_v980mV 6 12350 #define sc_x4_control_IDriver_Options_v1010mV 7 12351 #define sc_x4_control_IDriver_Options_v1040mV 8 12352 #define sc_x4_control_IDriver_Options_v1060mV 9 12353 #define sc_x4_control_IDriver_Options_v1070mV 10 12354 #define sc_x4_control_IDriver_Options_v1080mV 11 12355 #define sc_x4_control_IDriver_Options_v1085mV 12 12356 #define sc_x4_control_IDriver_Options_v1090mV 13 12357 #define sc_x4_control_IDriver_Options_v1095mV 14 12358 #define sc_x4_control_IDriver_Options_v1100mV 15 12359 12360 /**************************************************************************** 12361 * Enums: sc_x4_control_operationModes 12362 */ 12363 #define sc_x4_control_operationModes_XGXS 0 12364 #define sc_x4_control_operationModes_XGXG_nCC 1 12365 #define sc_x4_control_operationModes_Indlane_OS8 4 12366 #define sc_x4_control_operationModes_IndLane_OS5 5 12367 #define sc_x4_control_operationModes_PCI 7 12368 #define sc_x4_control_operationModes_XGXS_nLQ 8 12369 #define sc_x4_control_operationModes_XGXS_nLQnCC 9 12370 #define sc_x4_control_operationModes_PBypass 10 12371 #define sc_x4_control_operationModes_PBypass_nDSK 11 12372 #define sc_x4_control_operationModes_ComboCoreMode 12 12373 #define sc_x4_control_operationModes_Clocks_off 15 12374 12375 /**************************************************************************** 12376 * Enums: sc_x4_control_actualSpeeds 12377 */ 12378 #define sc_x4_control_actualSpeeds_dr_10M 0 12379 #define sc_x4_control_actualSpeeds_dr_100M 1 12380 #define sc_x4_control_actualSpeeds_dr_1G 2 12381 #define sc_x4_control_actualSpeeds_dr_2p5G 3 12382 #define sc_x4_control_actualSpeeds_dr_5G_X4 4 12383 #define sc_x4_control_actualSpeeds_dr_6G_X4 5 12384 #define sc_x4_control_actualSpeeds_dr_10G_HiG 6 12385 #define sc_x4_control_actualSpeeds_dr_10G_CX4 7 12386 #define sc_x4_control_actualSpeeds_dr_12G_HiG 8 12387 #define sc_x4_control_actualSpeeds_dr_12p5G_X4 9 12388 #define sc_x4_control_actualSpeeds_dr_13G_X4 10 12389 #define sc_x4_control_actualSpeeds_dr_15G_X4 11 12390 #define sc_x4_control_actualSpeeds_dr_16G_X4 12 12391 #define sc_x4_control_actualSpeeds_dr_1G_KX 13 12392 #define sc_x4_control_actualSpeeds_dr_10G_KX4 14 12393 #define sc_x4_control_actualSpeeds_dr_10G_KR 15 12394 #define sc_x4_control_actualSpeeds_dr_5G 16 12395 #define sc_x4_control_actualSpeeds_dr_6p4G 17 12396 #define sc_x4_control_actualSpeeds_dr_20G_X4 18 12397 #define sc_x4_control_actualSpeeds_dr_21G_X4 19 12398 #define sc_x4_control_actualSpeeds_dr_25G_X4 20 12399 #define sc_x4_control_actualSpeeds_dr_10G_HiG_DXGXS 21 12400 #define sc_x4_control_actualSpeeds_dr_10G_DXGXS 22 12401 #define sc_x4_control_actualSpeeds_dr_10p5G_HiG_DXGXS 23 12402 #define sc_x4_control_actualSpeeds_dr_10p5G_DXGXS 24 12403 #define sc_x4_control_actualSpeeds_dr_12p773G_HiG_DXGXS 25 12404 #define sc_x4_control_actualSpeeds_dr_12p773G_DXGXS 26 12405 #define sc_x4_control_actualSpeeds_dr_10G_XFI 27 12406 #define sc_x4_control_actualSpeeds_dr_40G 28 12407 #define sc_x4_control_actualSpeeds_dr_20G_HiG_DXGXS 29 12408 #define sc_x4_control_actualSpeeds_dr_20G_DXGXS 30 12409 #define sc_x4_control_actualSpeeds_dr_10G_SFI 31 12410 #define sc_x4_control_actualSpeeds_dr_31p5G 32 12411 #define sc_x4_control_actualSpeeds_dr_32p7G 33 12412 #define sc_x4_control_actualSpeeds_dr_20G_SCR 34 12413 #define sc_x4_control_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 12414 #define sc_x4_control_actualSpeeds_dr_10G_DXGXS_SCR 36 12415 #define sc_x4_control_actualSpeeds_dr_12G_R2 37 12416 #define sc_x4_control_actualSpeeds_dr_10G_X2 38 12417 #define sc_x4_control_actualSpeeds_dr_40G_KR4 39 12418 #define sc_x4_control_actualSpeeds_dr_40G_CR4 40 12419 #define sc_x4_control_actualSpeeds_dr_100G_CR10 41 12420 #define sc_x4_control_actualSpeeds_dr_15p75G_DXGXS 44 12421 #define sc_x4_control_actualSpeeds_dr_20G_KR2 57 12422 #define sc_x4_control_actualSpeeds_dr_20G_CR2 58 12423 12424 /**************************************************************************** 12425 * Enums: sc_x4_control_actualSpeedsMisc1 12426 */ 12427 #define sc_x4_control_actualSpeedsMisc1_dr_2500BRCM_X1 16 12428 #define sc_x4_control_actualSpeedsMisc1_dr_5000BRCM_X4 17 12429 #define sc_x4_control_actualSpeedsMisc1_dr_6000BRCM_X4 18 12430 #define sc_x4_control_actualSpeedsMisc1_dr_10GHiGig_X4 19 12431 #define sc_x4_control_actualSpeedsMisc1_dr_10GBASE_CX4 20 12432 #define sc_x4_control_actualSpeedsMisc1_dr_12GHiGig_X4 21 12433 #define sc_x4_control_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 12434 #define sc_x4_control_actualSpeedsMisc1_dr_13GHiGig_X4 23 12435 #define sc_x4_control_actualSpeedsMisc1_dr_15GHiGig_X4 24 12436 #define sc_x4_control_actualSpeedsMisc1_dr_16GHiGig_X4 25 12437 #define sc_x4_control_actualSpeedsMisc1_dr_5000BRCM_X1 26 12438 #define sc_x4_control_actualSpeedsMisc1_dr_6363BRCM_X1 27 12439 #define sc_x4_control_actualSpeedsMisc1_dr_20GHiGig_X4 28 12440 #define sc_x4_control_actualSpeedsMisc1_dr_21GHiGig_X4 29 12441 #define sc_x4_control_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 12442 #define sc_x4_control_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 12443 12444 /**************************************************************************** 12445 * Enums: sc_x4_control_IndLaneModes 12446 */ 12447 #define sc_x4_control_IndLaneModes_SWSDR_div2 0 12448 #define sc_x4_control_IndLaneModes_SWSDR_div1 1 12449 #define sc_x4_control_IndLaneModes_DWSDR_div2 2 12450 #define sc_x4_control_IndLaneModes_DWSDR_div1 3 12451 12452 /**************************************************************************** 12453 * Enums: sc_x4_control_prbsSelect 12454 */ 12455 #define sc_x4_control_prbsSelect_prbs7 0 12456 #define sc_x4_control_prbsSelect_prbs15 1 12457 #define sc_x4_control_prbsSelect_prbs23 2 12458 #define sc_x4_control_prbsSelect_prbs31 3 12459 12460 /**************************************************************************** 12461 * Enums: sc_x4_control_vcoDivider 12462 */ 12463 #define sc_x4_control_vcoDivider_div32 0 12464 #define sc_x4_control_vcoDivider_div36 1 12465 #define sc_x4_control_vcoDivider_div40 2 12466 #define sc_x4_control_vcoDivider_div42 3 12467 #define sc_x4_control_vcoDivider_div48 4 12468 #define sc_x4_control_vcoDivider_div50 5 12469 #define sc_x4_control_vcoDivider_div52 6 12470 #define sc_x4_control_vcoDivider_div54 7 12471 #define sc_x4_control_vcoDivider_div60 8 12472 #define sc_x4_control_vcoDivider_div64 9 12473 #define sc_x4_control_vcoDivider_div66 10 12474 #define sc_x4_control_vcoDivider_div68 11 12475 #define sc_x4_control_vcoDivider_div70 12 12476 #define sc_x4_control_vcoDivider_div80 13 12477 #define sc_x4_control_vcoDivider_div92 14 12478 #define sc_x4_control_vcoDivider_div100 15 12479 12480 /**************************************************************************** 12481 * Enums: sc_x4_control_refClkSelect 12482 */ 12483 #define sc_x4_control_refClkSelect_clk_25MHz 0 12484 #define sc_x4_control_refClkSelect_clk_100MHz 1 12485 #define sc_x4_control_refClkSelect_clk_125MHz 2 12486 #define sc_x4_control_refClkSelect_clk_156p25MHz 3 12487 #define sc_x4_control_refClkSelect_clk_187p5MHz 4 12488 #define sc_x4_control_refClkSelect_clk_161p25Mhz 5 12489 #define sc_x4_control_refClkSelect_clk_50Mhz 6 12490 #define sc_x4_control_refClkSelect_clk_106p25Mhz 7 12491 12492 /**************************************************************************** 12493 * Enums: sc_x4_control_aerMMDdevTypeSelect 12494 */ 12495 #define sc_x4_control_aerMMDdevTypeSelect_combo_core 0 12496 #define sc_x4_control_aerMMDdevTypeSelect_PMA_PMD 1 12497 #define sc_x4_control_aerMMDdevTypeSelect_PCS 3 12498 #define sc_x4_control_aerMMDdevTypeSelect_PHY 4 12499 #define sc_x4_control_aerMMDdevTypeSelect_DTE 5 12500 #define sc_x4_control_aerMMDdevTypeSelect_CL73_AN 7 12501 12502 /**************************************************************************** 12503 * Enums: sc_x4_control_aerMMDportSelect 12504 */ 12505 #define sc_x4_control_aerMMDportSelect_ln0 0 12506 #define sc_x4_control_aerMMDportSelect_ln1 1 12507 #define sc_x4_control_aerMMDportSelect_ln2 2 12508 #define sc_x4_control_aerMMDportSelect_ln3 3 12509 #define sc_x4_control_aerMMDportSelect_BCST_ln0_1_2_3 511 12510 #define sc_x4_control_aerMMDportSelect_BCST_ln0_1 512 12511 #define sc_x4_control_aerMMDportSelect_BCST_ln2_3 513 12512 12513 /**************************************************************************** 12514 * Enums: sc_x4_control_firmwareModeSelect 12515 */ 12516 #define sc_x4_control_firmwareModeSelect_DEFAULT 0 12517 #define sc_x4_control_firmwareModeSelect_SFP_OPT_LR 1 12518 #define sc_x4_control_firmwareModeSelect_SFP_DAC 2 12519 #define sc_x4_control_firmwareModeSelect_XLAUI 3 12520 #define sc_x4_control_firmwareModeSelect_LONG_CH_6G 4 12521 12522 /**************************************************************************** 12523 * Enums: sc_x4_control_tempIdxSelect 12524 */ 12525 #define sc_x4_control_tempIdxSelect_LTE__22p9C 15 12526 #define sc_x4_control_tempIdxSelect_LTE__12p6C 14 12527 #define sc_x4_control_tempIdxSelect_LTE__3p0C 13 12528 #define sc_x4_control_tempIdxSelect_LTE_6p7C 12 12529 #define sc_x4_control_tempIdxSelect_LTE_16p4C 11 12530 #define sc_x4_control_tempIdxSelect_LTE_26p6C 10 12531 #define sc_x4_control_tempIdxSelect_LTE_36p3C 9 12532 #define sc_x4_control_tempIdxSelect_LTE_46p0C 8 12533 #define sc_x4_control_tempIdxSelect_LTE_56p2C 7 12534 #define sc_x4_control_tempIdxSelect_LTE_65p9C 6 12535 #define sc_x4_control_tempIdxSelect_LTE_75p6C 5 12536 #define sc_x4_control_tempIdxSelect_LTE_85p3C 4 12537 #define sc_x4_control_tempIdxSelect_LTE_95p5C 3 12538 #define sc_x4_control_tempIdxSelect_LTE_105p2C 2 12539 #define sc_x4_control_tempIdxSelect_LTE_114p9C 1 12540 #define sc_x4_control_tempIdxSelect_LTE_125p1C 0 12541 12542 /**************************************************************************** 12543 * Enums: sc_x4_control_port_mode 12544 */ 12545 #define sc_x4_control_port_mode_QUAD_PORT 0 12546 #define sc_x4_control_port_mode_TRI_1_PORT 1 12547 #define sc_x4_control_port_mode_TRI_2_PORT 2 12548 #define sc_x4_control_port_mode_DUAL_PORT 3 12549 #define sc_x4_control_port_mode_SINGLE_PORT 4 12550 12551 /**************************************************************************** 12552 * Enums: sc_x4_control_rev_letter_enum 12553 */ 12554 #define sc_x4_control_rev_letter_enum_REV_A 0 12555 #define sc_x4_control_rev_letter_enum_REV_B 1 12556 #define sc_x4_control_rev_letter_enum_REV_C 2 12557 #define sc_x4_control_rev_letter_enum_REV_D 3 12558 12559 /**************************************************************************** 12560 * Enums: sc_x4_control_rev_number_enum 12561 */ 12562 #define sc_x4_control_rev_number_enum_REV_0 0 12563 #define sc_x4_control_rev_number_enum_REV_1 1 12564 #define sc_x4_control_rev_number_enum_REV_2 2 12565 #define sc_x4_control_rev_number_enum_REV_3 3 12566 #define sc_x4_control_rev_number_enum_REV_4 4 12567 #define sc_x4_control_rev_number_enum_REV_5 5 12568 #define sc_x4_control_rev_number_enum_REV_6 6 12569 #define sc_x4_control_rev_number_enum_REV_7 7 12570 12571 /**************************************************************************** 12572 * Enums: sc_x4_control_bonding_enum 12573 */ 12574 #define sc_x4_control_bonding_enum_WIRE_BOND 0 12575 #define sc_x4_control_bonding_enum_FLIP_CHIP 1 12576 12577 /**************************************************************************** 12578 * Enums: sc_x4_control_tech_process 12579 */ 12580 #define sc_x4_control_tech_process_PROCESS_90NM 0 12581 #define sc_x4_control_tech_process_PROCESS_65NM 1 12582 #define sc_x4_control_tech_process_PROCESS_40NM 2 12583 #define sc_x4_control_tech_process_PROCESS_28NM 3 12584 12585 /**************************************************************************** 12586 * Enums: sc_x4_control_model_num 12587 */ 12588 #define sc_x4_control_model_num_SERDES_CL73 0 12589 #define sc_x4_control_model_num_XGXS_16G 1 12590 #define sc_x4_control_model_num_HYPERCORE 2 12591 #define sc_x4_control_model_num_HYPERLITE 3 12592 #define sc_x4_control_model_num_PCIE_G2_PIPE 4 12593 #define sc_x4_control_model_num_SERDES_1p25GBd 5 12594 #define sc_x4_control_model_num_SATA2 6 12595 #define sc_x4_control_model_num_QSGMII 7 12596 #define sc_x4_control_model_num_XGXS10G 8 12597 #define sc_x4_control_model_num_WARPCORE 9 12598 #define sc_x4_control_model_num_XFICORE 10 12599 #define sc_x4_control_model_num_RXFI 11 12600 #define sc_x4_control_model_num_WARPLITE 12 12601 #define sc_x4_control_model_num_PENTACORE 13 12602 #define sc_x4_control_model_num_ESM 14 12603 #define sc_x4_control_model_num_QUAD_SGMII 15 12604 #define sc_x4_control_model_num_WARPCORE_3 16 12605 #define sc_x4_control_model_num_TSC 17 12606 #define sc_x4_control_model_num_TSC4E 18 12607 #define sc_x4_control_model_num_TSC12E 19 12608 #define sc_x4_control_model_num_TSC4F 20 12609 #define sc_x4_control_model_num_XGXS_CL73_90NM 29 12610 #define sc_x4_control_model_num_SERDES_CL73_90NM 30 12611 #define sc_x4_control_model_num_WARPCORE3 32 12612 #define sc_x4_control_model_num_WARPCORE4_TSC 33 12613 #define sc_x4_control_model_num_RXAUI 34 12614 12615 /**************************************************************************** 12616 * Enums: sc_x4_control_payload 12617 */ 12618 #define sc_x4_control_payload_REPEAT_2_BYTES 0 12619 #define sc_x4_control_payload_RAMPING 1 12620 #define sc_x4_control_payload_CL48_CRPAT 2 12621 #define sc_x4_control_payload_CL48_CJPAT 3 12622 #define sc_x4_control_payload_CL36_LONG_CRPAT 4 12623 #define sc_x4_control_payload_CL36_SHORT_CRPAT 5 12624 12625 /**************************************************************************** 12626 * Enums: sc_x4_control_sc 12627 */ 12628 #define sc_x4_control_sc_S_10G_CR1 0 12629 #define sc_x4_control_sc_S_10G_KR1 1 12630 #define sc_x4_control_sc_S_10G_X1 2 12631 #define sc_x4_control_sc_S_10G_HG2_CR1 4 12632 #define sc_x4_control_sc_S_10G_HG2_KR1 5 12633 #define sc_x4_control_sc_S_10G_HG2_X1 6 12634 #define sc_x4_control_sc_S_20G_CR1 8 12635 #define sc_x4_control_sc_S_20G_KR1 9 12636 #define sc_x4_control_sc_S_20G_X1 10 12637 #define sc_x4_control_sc_S_20G_HG2_CR1 12 12638 #define sc_x4_control_sc_S_20G_HG2_KR1 13 12639 #define sc_x4_control_sc_S_20G_HG2_X1 14 12640 #define sc_x4_control_sc_S_25G_CR1 16 12641 #define sc_x4_control_sc_S_25G_KR1 17 12642 #define sc_x4_control_sc_S_25G_X1 18 12643 #define sc_x4_control_sc_S_25G_HG2_CR1 20 12644 #define sc_x4_control_sc_S_25G_HG2_KR1 21 12645 #define sc_x4_control_sc_S_25G_HG2_X1 22 12646 #define sc_x4_control_sc_S_20G_CR2 24 12647 #define sc_x4_control_sc_S_20G_KR2 25 12648 #define sc_x4_control_sc_S_20G_X2 26 12649 #define sc_x4_control_sc_S_20G_HG2_CR2 28 12650 #define sc_x4_control_sc_S_20G_HG2_KR2 29 12651 #define sc_x4_control_sc_S_20G_HG2_X2 30 12652 #define sc_x4_control_sc_S_40G_CR2 32 12653 #define sc_x4_control_sc_S_40G_KR2 33 12654 #define sc_x4_control_sc_S_40G_X2 34 12655 #define sc_x4_control_sc_S_40G_HG2_CR2 36 12656 #define sc_x4_control_sc_S_40G_HG2_KR2 37 12657 #define sc_x4_control_sc_S_40G_HG2_X2 38 12658 #define sc_x4_control_sc_S_40G_CR4 40 12659 #define sc_x4_control_sc_S_40G_KR4 41 12660 #define sc_x4_control_sc_S_40G_X4 42 12661 #define sc_x4_control_sc_S_40G_HG2_CR4 44 12662 #define sc_x4_control_sc_S_40G_HG2_KR4 45 12663 #define sc_x4_control_sc_S_40G_HG2_X4 46 12664 #define sc_x4_control_sc_S_50G_CR2 48 12665 #define sc_x4_control_sc_S_50G_KR2 49 12666 #define sc_x4_control_sc_S_50G_X2 50 12667 #define sc_x4_control_sc_S_50G_HG2_CR2 52 12668 #define sc_x4_control_sc_S_50G_HG2_KR2 53 12669 #define sc_x4_control_sc_S_50G_HG2_X2 54 12670 #define sc_x4_control_sc_S_50G_CR4 56 12671 #define sc_x4_control_sc_S_50G_KR4 57 12672 #define sc_x4_control_sc_S_50G_X4 58 12673 #define sc_x4_control_sc_S_50G_HG2_CR4 60 12674 #define sc_x4_control_sc_S_50G_HG2_KR4 61 12675 #define sc_x4_control_sc_S_50G_HG2_X4 62 12676 #define sc_x4_control_sc_S_100G_CR4 64 12677 #define sc_x4_control_sc_S_100G_KR4 65 12678 #define sc_x4_control_sc_S_100G_X4 66 12679 #define sc_x4_control_sc_S_100G_HG2_CR4 68 12680 #define sc_x4_control_sc_S_100G_HG2_KR4 69 12681 #define sc_x4_control_sc_S_100G_HG2_X4 70 12682 #define sc_x4_control_sc_S_CL73_20GVCO 72 12683 #define sc_x4_control_sc_S_CL73_25GVCO 80 12684 #define sc_x4_control_sc_S_CL36_20GVCO 88 12685 #define sc_x4_control_sc_S_CL36_25GVCO 96 12686 #define sc_x4_control_sc_S_10G_25GVCO 98 12687 #define sc_x4_control_sc_S_25G_CR_IEEE 112 12688 #define sc_x4_control_sc_S_25G_CRS_IEEE 113 12689 #define sc_x4_control_sc_S_25G_KR_IEEE 114 12690 #define sc_x4_control_sc_S_25G_KRS_IEEE 115 12691 12692 12693 12694 /**************************************************************************** 12695 * Enums: sc_x4_control_t_fifo_modes 12696 */ 12697 #define sc_x4_control_t_fifo_modes_T_FIFO_MODE_BYPASS 0 12698 #define sc_x4_control_t_fifo_modes_T_FIFO_MODE_40G 1 12699 #define sc_x4_control_t_fifo_modes_T_FIFO_MODE_100G 2 12700 #define sc_x4_control_t_fifo_modes_T_FIFO_MODE_20G 3 12701 12702 /**************************************************************************** 12703 * Enums: sc_x4_control_t_enc_modes 12704 */ 12705 #define sc_x4_control_t_enc_modes_T_ENC_MODE_BYPASS 0 12706 #define sc_x4_control_t_enc_modes_T_ENC_MODE_CL49 1 12707 #define sc_x4_control_t_enc_modes_T_ENC_MODE_CL82 2 12708 12709 /**************************************************************************** 12710 * Enums: sc_x4_control_btmx_mode 12711 */ 12712 #define sc_x4_control_btmx_mode_BS_BTMX_MODE_1to1 0 12713 #define sc_x4_control_btmx_mode_BS_BTMX_MODE_2to1 1 12714 #define sc_x4_control_btmx_mode_BS_BTMX_MODE_5to1 2 12715 12716 /**************************************************************************** 12717 * Enums: sc_x4_control_t_type_cl82 12718 */ 12719 #define sc_x4_control_t_type_cl82_T_TYPE_B1 5 12720 #define sc_x4_control_t_type_cl82_T_TYPE_C 4 12721 #define sc_x4_control_t_type_cl82_T_TYPE_S 3 12722 #define sc_x4_control_t_type_cl82_T_TYPE_T 2 12723 #define sc_x4_control_t_type_cl82_T_TYPE_D 1 12724 #define sc_x4_control_t_type_cl82_T_TYPE_E 0 12725 12726 /**************************************************************************** 12727 * Enums: sc_x4_control_txsm_state_cl82 12728 */ 12729 #define sc_x4_control_txsm_state_cl82_TX_HIG_END 6 12730 #define sc_x4_control_txsm_state_cl82_TX_HIG_START 5 12731 #define sc_x4_control_txsm_state_cl82_TX_E 4 12732 #define sc_x4_control_txsm_state_cl82_TX_T 3 12733 #define sc_x4_control_txsm_state_cl82_TX_D 2 12734 #define sc_x4_control_txsm_state_cl82_TX_C 1 12735 #define sc_x4_control_txsm_state_cl82_TX_INIT 0 12736 12737 /**************************************************************************** 12738 * Enums: sc_x4_control_ltxsm_state_cl82 12739 */ 12740 #define sc_x4_control_ltxsm_state_cl82_TX_HIG_END 64 12741 #define sc_x4_control_ltxsm_state_cl82_TX_HIG_START 32 12742 #define sc_x4_control_ltxsm_state_cl82_TX_E 16 12743 #define sc_x4_control_ltxsm_state_cl82_TX_T 8 12744 #define sc_x4_control_ltxsm_state_cl82_TX_D 4 12745 #define sc_x4_control_ltxsm_state_cl82_TX_C 2 12746 #define sc_x4_control_ltxsm_state_cl82_TX_INIT 1 12747 12748 /**************************************************************************** 12749 * Enums: sc_x4_control_r_type_coded_cl82 12750 */ 12751 #define sc_x4_control_r_type_coded_cl82_R_TYPE_B1 32 12752 #define sc_x4_control_r_type_coded_cl82_R_TYPE_C 16 12753 #define sc_x4_control_r_type_coded_cl82_R_TYPE_S 8 12754 #define sc_x4_control_r_type_coded_cl82_R_TYPE_T 4 12755 #define sc_x4_control_r_type_coded_cl82_R_TYPE_D 2 12756 #define sc_x4_control_r_type_coded_cl82_R_TYPE_E 1 12757 12758 /**************************************************************************** 12759 * Enums: sc_x4_control_rxsm_state_cl82 12760 */ 12761 #define sc_x4_control_rxsm_state_cl82_RX_HIG_END 64 12762 #define sc_x4_control_rxsm_state_cl82_RX_HIG_START 32 12763 #define sc_x4_control_rxsm_state_cl82_RX_E 16 12764 #define sc_x4_control_rxsm_state_cl82_RX_T 8 12765 #define sc_x4_control_rxsm_state_cl82_RX_D 4 12766 #define sc_x4_control_rxsm_state_cl82_RX_C 2 12767 #define sc_x4_control_rxsm_state_cl82_RX_INIT 1 12768 12769 /**************************************************************************** 12770 * Enums: sc_x4_control_deskew_state 12771 */ 12772 #define sc_x4_control_deskew_state_ALIGN_ACQUIRED 2 12773 #define sc_x4_control_deskew_state_LOSS_OF_ALIGNMENT 1 12774 12775 /**************************************************************************** 12776 * Enums: sc_x4_control_os_mode_enum 12777 */ 12778 #define sc_x4_control_os_mode_enum_OS_MODE_1 0 12779 #define sc_x4_control_os_mode_enum_OS_MODE_2 1 12780 #define sc_x4_control_os_mode_enum_OS_MODE_4 2 12781 #define sc_x4_control_os_mode_enum_OS_MODE_16p5 8 12782 #define sc_x4_control_os_mode_enum_OS_MODE_20p625 12 12783 12784 /**************************************************************************** 12785 * Enums: sc_x4_control_scr_modes 12786 */ 12787 #define sc_x4_control_scr_modes_T_SCR_MODE_BYPASS 0 12788 #define sc_x4_control_scr_modes_T_SCR_MODE_CL49 1 12789 #define sc_x4_control_scr_modes_T_SCR_MODE_40G_2_LANE 2 12790 #define sc_x4_control_scr_modes_T_SCR_MODE_100G 3 12791 #define sc_x4_control_scr_modes_T_SCR_MODE_20G 4 12792 #define sc_x4_control_scr_modes_T_SCR_MODE_40G_4_LANE 5 12793 12794 /**************************************************************************** 12795 * Enums: sc_x4_control_descr_modes 12796 */ 12797 #define sc_x4_control_descr_modes_R_DESCR_MODE_BYPASS 0 12798 #define sc_x4_control_descr_modes_R_DESCR_MODE_CL49 1 12799 #define sc_x4_control_descr_modes_R_DESCR_MODE_CL82 2 12800 12801 /**************************************************************************** 12802 * Enums: sc_x4_control_r_dec_tl_mode 12803 */ 12804 #define sc_x4_control_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 12805 #define sc_x4_control_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 12806 #define sc_x4_control_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 12807 12808 /**************************************************************************** 12809 * Enums: sc_x4_control_r_dec_fsm_mode 12810 */ 12811 #define sc_x4_control_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 12812 #define sc_x4_control_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 12813 #define sc_x4_control_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 12814 12815 /**************************************************************************** 12816 * Enums: sc_x4_control_r_deskew_mode 12817 */ 12818 #define sc_x4_control_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 12819 #define sc_x4_control_r_deskew_mode_R_DESKEW_MODE_20G 1 12820 #define sc_x4_control_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 12821 #define sc_x4_control_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 12822 #define sc_x4_control_r_deskew_mode_R_DESKEW_MODE_100G 4 12823 #define sc_x4_control_r_deskew_mode_R_DESKEW_MODE_CL49 5 12824 #define sc_x4_control_r_deskew_mode_R_DESKEW_MODE_CL91 6 12825 12826 /**************************************************************************** 12827 * Enums: sc_x4_control_bs_dist_modes 12828 */ 12829 #define sc_x4_control_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 12830 #define sc_x4_control_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 12831 #define sc_x4_control_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 12832 #define sc_x4_control_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 12833 12834 /**************************************************************************** 12835 * Enums: sc_x4_control_cl49_t_type 12836 */ 12837 #define sc_x4_control_cl49_t_type_BAD_T_TYPE 15 12838 #define sc_x4_control_cl49_t_type_T_TYPE_B0 11 12839 #define sc_x4_control_cl49_t_type_T_TYPE_OB 10 12840 #define sc_x4_control_cl49_t_type_T_TYPE_B1 9 12841 #define sc_x4_control_cl49_t_type_T_TYPE_DB 8 12842 #define sc_x4_control_cl49_t_type_T_TYPE_FC 7 12843 #define sc_x4_control_cl49_t_type_T_TYPE_TB 6 12844 #define sc_x4_control_cl49_t_type_T_TYPE_LI 5 12845 #define sc_x4_control_cl49_t_type_T_TYPE_C 4 12846 #define sc_x4_control_cl49_t_type_T_TYPE_S 3 12847 #define sc_x4_control_cl49_t_type_T_TYPE_T 2 12848 #define sc_x4_control_cl49_t_type_T_TYPE_D 1 12849 #define sc_x4_control_cl49_t_type_T_TYPE_E 0 12850 12851 /**************************************************************************** 12852 * Enums: sc_x4_control_cl49_txsm_states 12853 */ 12854 #define sc_x4_control_cl49_txsm_states_TX_HIG_END 7 12855 #define sc_x4_control_cl49_txsm_states_TX_HIG_START 6 12856 #define sc_x4_control_cl49_txsm_states_TX_LI 5 12857 #define sc_x4_control_cl49_txsm_states_TX_E 4 12858 #define sc_x4_control_cl49_txsm_states_TX_T 3 12859 #define sc_x4_control_cl49_txsm_states_TX_D 2 12860 #define sc_x4_control_cl49_txsm_states_TX_C 1 12861 #define sc_x4_control_cl49_txsm_states_TX_INIT 0 12862 12863 /**************************************************************************** 12864 * Enums: sc_x4_control_cl49_ltxsm_states 12865 */ 12866 #define sc_x4_control_cl49_ltxsm_states_TX_HIG_END 128 12867 #define sc_x4_control_cl49_ltxsm_states_TX_HIG_START 64 12868 #define sc_x4_control_cl49_ltxsm_states_TX_LI 32 12869 #define sc_x4_control_cl49_ltxsm_states_TX_E 16 12870 #define sc_x4_control_cl49_ltxsm_states_TX_T 8 12871 #define sc_x4_control_cl49_ltxsm_states_TX_D 4 12872 #define sc_x4_control_cl49_ltxsm_states_TX_C 2 12873 #define sc_x4_control_cl49_ltxsm_states_TX_INIT 1 12874 12875 /**************************************************************************** 12876 * Enums: sc_x4_control_burst_error_mode 12877 */ 12878 #define sc_x4_control_burst_error_mode_BURST_ERROR_11_BITS 0 12879 #define sc_x4_control_burst_error_mode_BURST_ERROR_16_BITS 1 12880 #define sc_x4_control_burst_error_mode_BURST_ERROR_17_BITS 2 12881 #define sc_x4_control_burst_error_mode_BURST_ERROR_18_BITS 3 12882 #define sc_x4_control_burst_error_mode_BURST_ERROR_19_BITS 4 12883 #define sc_x4_control_burst_error_mode_BURST_ERROR_20_BITS 5 12884 #define sc_x4_control_burst_error_mode_BURST_ERROR_21_BITS 6 12885 #define sc_x4_control_burst_error_mode_BURST_ERROR_22_BITS 7 12886 #define sc_x4_control_burst_error_mode_BURST_ERROR_23_BITS 8 12887 #define sc_x4_control_burst_error_mode_BURST_ERROR_24_BITS 9 12888 #define sc_x4_control_burst_error_mode_BURST_ERROR_25_BITS 10 12889 #define sc_x4_control_burst_error_mode_BURST_ERROR_26_BITS 11 12890 #define sc_x4_control_burst_error_mode_BURST_ERROR_27_BITS 12 12891 #define sc_x4_control_burst_error_mode_BURST_ERROR_28_BITS 13 12892 #define sc_x4_control_burst_error_mode_BURST_ERROR_29_BITS 14 12893 #define sc_x4_control_burst_error_mode_BURST_ERROR_30_BITS 15 12894 #define sc_x4_control_burst_error_mode_BURST_ERROR_31_BITS 16 12895 #define sc_x4_control_burst_error_mode_BURST_ERROR_32_BITS 17 12896 #define sc_x4_control_burst_error_mode_BURST_ERROR_33_BITS 18 12897 #define sc_x4_control_burst_error_mode_BURST_ERROR_34_BITS 19 12898 #define sc_x4_control_burst_error_mode_BURST_ERROR_35_BITS 20 12899 #define sc_x4_control_burst_error_mode_BURST_ERROR_36_BITS 21 12900 #define sc_x4_control_burst_error_mode_BURST_ERROR_37_BITS 22 12901 #define sc_x4_control_burst_error_mode_BURST_ERROR_38_BITS 23 12902 #define sc_x4_control_burst_error_mode_BURST_ERROR_39_BITS 24 12903 #define sc_x4_control_burst_error_mode_BURST_ERROR_40_BITS 25 12904 #define sc_x4_control_burst_error_mode_BURST_ERROR_41_BITS 26 12905 12906 /**************************************************************************** 12907 * Enums: sc_x4_control_bermon_state 12908 */ 12909 #define sc_x4_control_bermon_state_HI_BER 4 12910 #define sc_x4_control_bermon_state_GOOD_BER 3 12911 #define sc_x4_control_bermon_state_BER_TEST_SH 2 12912 #define sc_x4_control_bermon_state_START_TIMER 1 12913 #define sc_x4_control_bermon_state_BER_MT_INIT 0 12914 12915 /**************************************************************************** 12916 * Enums: sc_x4_control_rxsm_state_cl49 12917 */ 12918 #define sc_x4_control_rxsm_state_cl49_RX_HIG_END 128 12919 #define sc_x4_control_rxsm_state_cl49_RX_HIG_START 64 12920 #define sc_x4_control_rxsm_state_cl49_RX_LI 32 12921 #define sc_x4_control_rxsm_state_cl49_RX_E 16 12922 #define sc_x4_control_rxsm_state_cl49_RX_T 8 12923 #define sc_x4_control_rxsm_state_cl49_RX_D 4 12924 #define sc_x4_control_rxsm_state_cl49_RX_C 2 12925 #define sc_x4_control_rxsm_state_cl49_RX_INIT 1 12926 12927 /**************************************************************************** 12928 * Enums: sc_x4_control_r_type 12929 */ 12930 #define sc_x4_control_r_type_BAD_R_TYPE 15 12931 #define sc_x4_control_r_type_R_TYPE_B0 11 12932 #define sc_x4_control_r_type_R_TYPE_OB 10 12933 #define sc_x4_control_r_type_R_TYPE_B1 9 12934 #define sc_x4_control_r_type_R_TYPE_DB 8 12935 #define sc_x4_control_r_type_R_TYPE_FC 7 12936 #define sc_x4_control_r_type_R_TYPE_TB 6 12937 #define sc_x4_control_r_type_R_TYPE_LI 5 12938 #define sc_x4_control_r_type_R_TYPE_C 4 12939 #define sc_x4_control_r_type_R_TYPE_S 3 12940 #define sc_x4_control_r_type_R_TYPE_T 2 12941 #define sc_x4_control_r_type_R_TYPE_D 1 12942 #define sc_x4_control_r_type_R_TYPE_E 0 12943 12944 /**************************************************************************** 12945 * Enums: sc_x4_control_am_lock_state 12946 */ 12947 #define sc_x4_control_am_lock_state_INVALID_AM 512 12948 #define sc_x4_control_am_lock_state_GOOD_AM 256 12949 #define sc_x4_control_am_lock_state_COMP_AM 128 12950 #define sc_x4_control_am_lock_state_TIMER_2 64 12951 #define sc_x4_control_am_lock_state_AM_2_GOOD 32 12952 #define sc_x4_control_am_lock_state_COMP_2ND 16 12953 #define sc_x4_control_am_lock_state_TIMER_1 8 12954 #define sc_x4_control_am_lock_state_FIND_1ST 4 12955 #define sc_x4_control_am_lock_state_AM_RESET_CNT 2 12956 #define sc_x4_control_am_lock_state_AM_LOCK_INIT 1 12957 12958 /**************************************************************************** 12959 * Enums: sc_x4_control_msg_selector 12960 */ 12961 #define sc_x4_control_msg_selector_RESERVED 0 12962 #define sc_x4_control_msg_selector_VALUE_802p3 1 12963 #define sc_x4_control_msg_selector_VALUE_802p9 2 12964 #define sc_x4_control_msg_selector_VALUE_802p5 3 12965 #define sc_x4_control_msg_selector_VALUE_1394 4 12966 12967 /**************************************************************************** 12968 * Enums: sc_x4_control_synce_enum 12969 */ 12970 #define sc_x4_control_synce_enum_SYNCE_NO_DIV 0 12971 #define sc_x4_control_synce_enum_SYNCE_DIV_7 1 12972 #define sc_x4_control_synce_enum_SYNCE_DIV_11 2 12973 12974 /**************************************************************************** 12975 * Enums: sc_x4_control_synce_enum_stage0 12976 */ 12977 #define sc_x4_control_synce_enum_stage0_SYNCE_NO_DIV 0 12978 #define sc_x4_control_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 12979 #define sc_x4_control_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 12980 12981 /**************************************************************************** 12982 * Enums: sc_x4_control_cl91_sync_state 12983 */ 12984 #define sc_x4_control_cl91_sync_state_FIND_1ST 0 12985 #define sc_x4_control_cl91_sync_state_COUNT_NEXT 1 12986 #define sc_x4_control_cl91_sync_state_COMP_2ND 2 12987 #define sc_x4_control_cl91_sync_state_TWO_GOOD 3 12988 12989 /**************************************************************************** 12990 * Enums: sc_x4_control_cl91_algn_state 12991 */ 12992 #define sc_x4_control_cl91_algn_state_LOSS_OF_ALIGNMENT 0 12993 #define sc_x4_control_cl91_algn_state_DESKEW 1 12994 #define sc_x4_control_cl91_algn_state_DESKEW_FAIL 2 12995 #define sc_x4_control_cl91_algn_state_ALIGN_ACQUIRED 3 12996 #define sc_x4_control_cl91_algn_state_CW_GOOD 4 12997 #define sc_x4_control_cl91_algn_state_CW_BAD 5 12998 #define sc_x4_control_cl91_algn_state_THREE_BAD 6 12999 13000 /**************************************************************************** 13001 * Enums: sc_x4_control_fec_sel 13002 */ 13003 #define sc_x4_control_fec_sel_NO_FEC 0 13004 #define sc_x4_control_fec_sel_FEC_CL74 1 13005 #define sc_x4_control_fec_sel_FEC_CL91 2 13006 13007 /**************************************************************************** 13008 * Enums: sc_x4_final_config_status_cl36TxEEEStates_l 13009 */ 13010 #define sc_x4_final_config_status_cl36TxEEEStates_l_TX_REFRESH 8 13011 #define sc_x4_final_config_status_cl36TxEEEStates_l_TX_QUIET 4 13012 #define sc_x4_final_config_status_cl36TxEEEStates_l_TX_SLEEP 2 13013 #define sc_x4_final_config_status_cl36TxEEEStates_l_TX_ACTIVE 1 13014 13015 /**************************************************************************** 13016 * Enums: sc_x4_final_config_status_cl36TxEEEStates_c 13017 */ 13018 #define sc_x4_final_config_status_cl36TxEEEStates_c_TX_REFRESH 3 13019 #define sc_x4_final_config_status_cl36TxEEEStates_c_TX_QUIET 2 13020 #define sc_x4_final_config_status_cl36TxEEEStates_c_TX_SLEEP 1 13021 #define sc_x4_final_config_status_cl36TxEEEStates_c_TX_ACTIVE 0 13022 13023 /**************************************************************************** 13024 * Enums: sc_x4_final_config_status_cl49TxEEEStates_l 13025 */ 13026 #define sc_x4_final_config_status_cl49TxEEEStates_l_SCR_RESET_2 64 13027 #define sc_x4_final_config_status_cl49TxEEEStates_l_SCR_RESET_1 32 13028 #define sc_x4_final_config_status_cl49TxEEEStates_l_TX_WAKE 16 13029 #define sc_x4_final_config_status_cl49TxEEEStates_l_TX_REFRESH 8 13030 #define sc_x4_final_config_status_cl49TxEEEStates_l_TX_QUIET 4 13031 #define sc_x4_final_config_status_cl49TxEEEStates_l_TX_SLEEP 2 13032 #define sc_x4_final_config_status_cl49TxEEEStates_l_TX_ACTIVE 1 13033 13034 /**************************************************************************** 13035 * Enums: sc_x4_final_config_status_fec_req_enum 13036 */ 13037 #define sc_x4_final_config_status_fec_req_enum_FEC_not_supported 0 13038 #define sc_x4_final_config_status_fec_req_enum_FEC_supported_but_not_requested 1 13039 #define sc_x4_final_config_status_fec_req_enum_invalid_setting 2 13040 #define sc_x4_final_config_status_fec_req_enum_FEC_supported_and_requested 3 13041 13042 /**************************************************************************** 13043 * Enums: sc_x4_final_config_status_cl73_pause_enum 13044 */ 13045 #define sc_x4_final_config_status_cl73_pause_enum_No_PAUSE_ability 0 13046 #define sc_x4_final_config_status_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 13047 #define sc_x4_final_config_status_cl73_pause_enum_Symmetric_PAUSE_ability 1 13048 #define sc_x4_final_config_status_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 13049 13050 /**************************************************************************** 13051 * Enums: sc_x4_final_config_status_cl49TxEEEStates_c 13052 */ 13053 #define sc_x4_final_config_status_cl49TxEEEStates_c_SCR_RESET_2 6 13054 #define sc_x4_final_config_status_cl49TxEEEStates_c_SCR_RESET_1 5 13055 #define sc_x4_final_config_status_cl49TxEEEStates_c_TX_WAKE 4 13056 #define sc_x4_final_config_status_cl49TxEEEStates_c_TX_REFRESH 3 13057 #define sc_x4_final_config_status_cl49TxEEEStates_c_TX_QUIET 2 13058 #define sc_x4_final_config_status_cl49TxEEEStates_c_TX_SLEEP 1 13059 #define sc_x4_final_config_status_cl49TxEEEStates_c_TX_ACTIVE 0 13060 13061 /**************************************************************************** 13062 * Enums: sc_x4_final_config_status_cl36RxEEEStates_l 13063 */ 13064 #define sc_x4_final_config_status_cl36RxEEEStates_l_RX_LINK_FAIL 32 13065 #define sc_x4_final_config_status_cl36RxEEEStates_l_RX_WTF 16 13066 #define sc_x4_final_config_status_cl36RxEEEStates_l_RX_WAKE 8 13067 #define sc_x4_final_config_status_cl36RxEEEStates_l_RX_QUIET 4 13068 #define sc_x4_final_config_status_cl36RxEEEStates_l_RX_SLEEP 2 13069 #define sc_x4_final_config_status_cl36RxEEEStates_l_RX_ACTIVE 1 13070 13071 /**************************************************************************** 13072 * Enums: sc_x4_final_config_status_cl36RxEEEStates_c 13073 */ 13074 #define sc_x4_final_config_status_cl36RxEEEStates_c_RX_LINK_FAIL 5 13075 #define sc_x4_final_config_status_cl36RxEEEStates_c_RX_WTF 4 13076 #define sc_x4_final_config_status_cl36RxEEEStates_c_RX_WAKE 3 13077 #define sc_x4_final_config_status_cl36RxEEEStates_c_RX_QUIET 2 13078 #define sc_x4_final_config_status_cl36RxEEEStates_c_RX_SLEEP 1 13079 #define sc_x4_final_config_status_cl36RxEEEStates_c_RX_ACTIVE 0 13080 13081 /**************************************************************************** 13082 * Enums: sc_x4_final_config_status_cl49RxEEEStates_l 13083 */ 13084 #define sc_x4_final_config_status_cl49RxEEEStates_l_RX_LINK_FAIL 32 13085 #define sc_x4_final_config_status_cl49RxEEEStates_l_RX_WTF 16 13086 #define sc_x4_final_config_status_cl49RxEEEStates_l_RX_WAKE 8 13087 #define sc_x4_final_config_status_cl49RxEEEStates_l_RX_QUIET 4 13088 #define sc_x4_final_config_status_cl49RxEEEStates_l_RX_SLEEP 2 13089 #define sc_x4_final_config_status_cl49RxEEEStates_l_RX_ACTIVE 1 13090 13091 /**************************************************************************** 13092 * Enums: sc_x4_final_config_status_cl49RxEEEStates_c 13093 */ 13094 #define sc_x4_final_config_status_cl49RxEEEStates_c_RX_LINK_FAIL 5 13095 #define sc_x4_final_config_status_cl49RxEEEStates_c_RX_WTF 4 13096 #define sc_x4_final_config_status_cl49RxEEEStates_c_RX_WAKE 3 13097 #define sc_x4_final_config_status_cl49RxEEEStates_c_RX_QUIET 2 13098 #define sc_x4_final_config_status_cl49RxEEEStates_c_RX_SLEEP 1 13099 #define sc_x4_final_config_status_cl49RxEEEStates_c_RX_ACTIVE 0 13100 13101 /**************************************************************************** 13102 * Enums: sc_x4_final_config_status_cl48TxEEEStates_l 13103 */ 13104 #define sc_x4_final_config_status_cl48TxEEEStates_l_TX_REFRESH 8 13105 #define sc_x4_final_config_status_cl48TxEEEStates_l_TX_QUIET 4 13106 #define sc_x4_final_config_status_cl48TxEEEStates_l_TX_SLEEP 2 13107 #define sc_x4_final_config_status_cl48TxEEEStates_l_TX_ACTIVE 1 13108 13109 /**************************************************************************** 13110 * Enums: sc_x4_final_config_status_cl48TxEEEStates_c 13111 */ 13112 #define sc_x4_final_config_status_cl48TxEEEStates_c_TX_REFRESH 3 13113 #define sc_x4_final_config_status_cl48TxEEEStates_c_TX_QUIET 2 13114 #define sc_x4_final_config_status_cl48TxEEEStates_c_TX_SLEEP 1 13115 #define sc_x4_final_config_status_cl48TxEEEStates_c_TX_ACTIVE 0 13116 13117 /**************************************************************************** 13118 * Enums: sc_x4_final_config_status_cl48RxEEEStates_l 13119 */ 13120 #define sc_x4_final_config_status_cl48RxEEEStates_l_RX_LINK_FAIL 32 13121 #define sc_x4_final_config_status_cl48RxEEEStates_l_RX_WAKE 16 13122 #define sc_x4_final_config_status_cl48RxEEEStates_l_RX_QUIET 8 13123 #define sc_x4_final_config_status_cl48RxEEEStates_l_RX_DEACT 4 13124 #define sc_x4_final_config_status_cl48RxEEEStates_l_RX_SLEEP 2 13125 #define sc_x4_final_config_status_cl48RxEEEStates_l_RX_ACTIVE 1 13126 13127 /**************************************************************************** 13128 * Enums: sc_x4_final_config_status_cl48RxEEEStates_c 13129 */ 13130 #define sc_x4_final_config_status_cl48RxEEEStates_c_RX_LINK_FAIL 5 13131 #define sc_x4_final_config_status_cl48RxEEEStates_c_RX_WAKE 4 13132 #define sc_x4_final_config_status_cl48RxEEEStates_c_RX_QUIET 3 13133 #define sc_x4_final_config_status_cl48RxEEEStates_c_RX_DEACT 2 13134 #define sc_x4_final_config_status_cl48RxEEEStates_c_RX_SLEEP 1 13135 #define sc_x4_final_config_status_cl48RxEEEStates_c_RX_ACTIVE 0 13136 13137 /**************************************************************************** 13138 * Enums: sc_x4_final_config_status_IQP_Options 13139 */ 13140 #define sc_x4_final_config_status_IQP_Options_i50uA 0 13141 #define sc_x4_final_config_status_IQP_Options_i100uA 1 13142 #define sc_x4_final_config_status_IQP_Options_i150uA 2 13143 #define sc_x4_final_config_status_IQP_Options_i200uA 3 13144 #define sc_x4_final_config_status_IQP_Options_i250uA 4 13145 #define sc_x4_final_config_status_IQP_Options_i300uA 5 13146 #define sc_x4_final_config_status_IQP_Options_i350uA 6 13147 #define sc_x4_final_config_status_IQP_Options_i400uA 7 13148 #define sc_x4_final_config_status_IQP_Options_i450uA 8 13149 #define sc_x4_final_config_status_IQP_Options_i500uA 9 13150 #define sc_x4_final_config_status_IQP_Options_i550uA 10 13151 #define sc_x4_final_config_status_IQP_Options_i600uA 11 13152 #define sc_x4_final_config_status_IQP_Options_i650uA 12 13153 #define sc_x4_final_config_status_IQP_Options_i700uA 13 13154 #define sc_x4_final_config_status_IQP_Options_i750uA 14 13155 #define sc_x4_final_config_status_IQP_Options_i800uA 15 13156 13157 /**************************************************************************** 13158 * Enums: sc_x4_final_config_status_IDriver_Options 13159 */ 13160 #define sc_x4_final_config_status_IDriver_Options_v680mV 0 13161 #define sc_x4_final_config_status_IDriver_Options_v730mV 1 13162 #define sc_x4_final_config_status_IDriver_Options_v780mV 2 13163 #define sc_x4_final_config_status_IDriver_Options_v830mV 3 13164 #define sc_x4_final_config_status_IDriver_Options_v880mV 4 13165 #define sc_x4_final_config_status_IDriver_Options_v930mV 5 13166 #define sc_x4_final_config_status_IDriver_Options_v980mV 6 13167 #define sc_x4_final_config_status_IDriver_Options_v1010mV 7 13168 #define sc_x4_final_config_status_IDriver_Options_v1040mV 8 13169 #define sc_x4_final_config_status_IDriver_Options_v1060mV 9 13170 #define sc_x4_final_config_status_IDriver_Options_v1070mV 10 13171 #define sc_x4_final_config_status_IDriver_Options_v1080mV 11 13172 #define sc_x4_final_config_status_IDriver_Options_v1085mV 12 13173 #define sc_x4_final_config_status_IDriver_Options_v1090mV 13 13174 #define sc_x4_final_config_status_IDriver_Options_v1095mV 14 13175 #define sc_x4_final_config_status_IDriver_Options_v1100mV 15 13176 13177 /**************************************************************************** 13178 * Enums: sc_x4_final_config_status_operationModes 13179 */ 13180 #define sc_x4_final_config_status_operationModes_XGXS 0 13181 #define sc_x4_final_config_status_operationModes_XGXG_nCC 1 13182 #define sc_x4_final_config_status_operationModes_Indlane_OS8 4 13183 #define sc_x4_final_config_status_operationModes_IndLane_OS5 5 13184 #define sc_x4_final_config_status_operationModes_PCI 7 13185 #define sc_x4_final_config_status_operationModes_XGXS_nLQ 8 13186 #define sc_x4_final_config_status_operationModes_XGXS_nLQnCC 9 13187 #define sc_x4_final_config_status_operationModes_PBypass 10 13188 #define sc_x4_final_config_status_operationModes_PBypass_nDSK 11 13189 #define sc_x4_final_config_status_operationModes_ComboCoreMode 12 13190 #define sc_x4_final_config_status_operationModes_Clocks_off 15 13191 13192 /**************************************************************************** 13193 * Enums: sc_x4_final_config_status_actualSpeeds 13194 */ 13195 #define sc_x4_final_config_status_actualSpeeds_dr_10M 0 13196 #define sc_x4_final_config_status_actualSpeeds_dr_100M 1 13197 #define sc_x4_final_config_status_actualSpeeds_dr_1G 2 13198 #define sc_x4_final_config_status_actualSpeeds_dr_2p5G 3 13199 #define sc_x4_final_config_status_actualSpeeds_dr_5G_X4 4 13200 #define sc_x4_final_config_status_actualSpeeds_dr_6G_X4 5 13201 #define sc_x4_final_config_status_actualSpeeds_dr_10G_HiG 6 13202 #define sc_x4_final_config_status_actualSpeeds_dr_10G_CX4 7 13203 #define sc_x4_final_config_status_actualSpeeds_dr_12G_HiG 8 13204 #define sc_x4_final_config_status_actualSpeeds_dr_12p5G_X4 9 13205 #define sc_x4_final_config_status_actualSpeeds_dr_13G_X4 10 13206 #define sc_x4_final_config_status_actualSpeeds_dr_15G_X4 11 13207 #define sc_x4_final_config_status_actualSpeeds_dr_16G_X4 12 13208 #define sc_x4_final_config_status_actualSpeeds_dr_1G_KX 13 13209 #define sc_x4_final_config_status_actualSpeeds_dr_10G_KX4 14 13210 #define sc_x4_final_config_status_actualSpeeds_dr_10G_KR 15 13211 #define sc_x4_final_config_status_actualSpeeds_dr_5G 16 13212 #define sc_x4_final_config_status_actualSpeeds_dr_6p4G 17 13213 #define sc_x4_final_config_status_actualSpeeds_dr_20G_X4 18 13214 #define sc_x4_final_config_status_actualSpeeds_dr_21G_X4 19 13215 #define sc_x4_final_config_status_actualSpeeds_dr_25G_X4 20 13216 #define sc_x4_final_config_status_actualSpeeds_dr_10G_HiG_DXGXS 21 13217 #define sc_x4_final_config_status_actualSpeeds_dr_10G_DXGXS 22 13218 #define sc_x4_final_config_status_actualSpeeds_dr_10p5G_HiG_DXGXS 23 13219 #define sc_x4_final_config_status_actualSpeeds_dr_10p5G_DXGXS 24 13220 #define sc_x4_final_config_status_actualSpeeds_dr_12p773G_HiG_DXGXS 25 13221 #define sc_x4_final_config_status_actualSpeeds_dr_12p773G_DXGXS 26 13222 #define sc_x4_final_config_status_actualSpeeds_dr_10G_XFI 27 13223 #define sc_x4_final_config_status_actualSpeeds_dr_40G 28 13224 #define sc_x4_final_config_status_actualSpeeds_dr_20G_HiG_DXGXS 29 13225 #define sc_x4_final_config_status_actualSpeeds_dr_20G_DXGXS 30 13226 #define sc_x4_final_config_status_actualSpeeds_dr_10G_SFI 31 13227 #define sc_x4_final_config_status_actualSpeeds_dr_31p5G 32 13228 #define sc_x4_final_config_status_actualSpeeds_dr_32p7G 33 13229 #define sc_x4_final_config_status_actualSpeeds_dr_20G_SCR 34 13230 #define sc_x4_final_config_status_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 13231 #define sc_x4_final_config_status_actualSpeeds_dr_10G_DXGXS_SCR 36 13232 #define sc_x4_final_config_status_actualSpeeds_dr_12G_R2 37 13233 #define sc_x4_final_config_status_actualSpeeds_dr_10G_X2 38 13234 #define sc_x4_final_config_status_actualSpeeds_dr_40G_KR4 39 13235 #define sc_x4_final_config_status_actualSpeeds_dr_40G_CR4 40 13236 #define sc_x4_final_config_status_actualSpeeds_dr_100G_CR10 41 13237 #define sc_x4_final_config_status_actualSpeeds_dr_15p75G_DXGXS 44 13238 #define sc_x4_final_config_status_actualSpeeds_dr_20G_KR2 57 13239 #define sc_x4_final_config_status_actualSpeeds_dr_20G_CR2 58 13240 13241 /**************************************************************************** 13242 * Enums: sc_x4_final_config_status_actualSpeedsMisc1 13243 */ 13244 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_2500BRCM_X1 16 13245 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_5000BRCM_X4 17 13246 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_6000BRCM_X4 18 13247 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_10GHiGig_X4 19 13248 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_10GBASE_CX4 20 13249 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_12GHiGig_X4 21 13250 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 13251 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_13GHiGig_X4 23 13252 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_15GHiGig_X4 24 13253 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_16GHiGig_X4 25 13254 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_5000BRCM_X1 26 13255 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_6363BRCM_X1 27 13256 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_20GHiGig_X4 28 13257 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_21GHiGig_X4 29 13258 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 13259 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 13260 13261 /**************************************************************************** 13262 * Enums: sc_x4_final_config_status_IndLaneModes 13263 */ 13264 #define sc_x4_final_config_status_IndLaneModes_SWSDR_div2 0 13265 #define sc_x4_final_config_status_IndLaneModes_SWSDR_div1 1 13266 #define sc_x4_final_config_status_IndLaneModes_DWSDR_div2 2 13267 #define sc_x4_final_config_status_IndLaneModes_DWSDR_div1 3 13268 13269 /**************************************************************************** 13270 * Enums: sc_x4_final_config_status_prbsSelect 13271 */ 13272 #define sc_x4_final_config_status_prbsSelect_prbs7 0 13273 #define sc_x4_final_config_status_prbsSelect_prbs15 1 13274 #define sc_x4_final_config_status_prbsSelect_prbs23 2 13275 #define sc_x4_final_config_status_prbsSelect_prbs31 3 13276 13277 /**************************************************************************** 13278 * Enums: sc_x4_final_config_status_vcoDivider 13279 */ 13280 #define sc_x4_final_config_status_vcoDivider_div32 0 13281 #define sc_x4_final_config_status_vcoDivider_div36 1 13282 #define sc_x4_final_config_status_vcoDivider_div40 2 13283 #define sc_x4_final_config_status_vcoDivider_div42 3 13284 #define sc_x4_final_config_status_vcoDivider_div48 4 13285 #define sc_x4_final_config_status_vcoDivider_div50 5 13286 #define sc_x4_final_config_status_vcoDivider_div52 6 13287 #define sc_x4_final_config_status_vcoDivider_div54 7 13288 #define sc_x4_final_config_status_vcoDivider_div60 8 13289 #define sc_x4_final_config_status_vcoDivider_div64 9 13290 #define sc_x4_final_config_status_vcoDivider_div66 10 13291 #define sc_x4_final_config_status_vcoDivider_div68 11 13292 #define sc_x4_final_config_status_vcoDivider_div70 12 13293 #define sc_x4_final_config_status_vcoDivider_div80 13 13294 #define sc_x4_final_config_status_vcoDivider_div92 14 13295 #define sc_x4_final_config_status_vcoDivider_div100 15 13296 13297 /**************************************************************************** 13298 * Enums: sc_x4_final_config_status_refClkSelect 13299 */ 13300 #define sc_x4_final_config_status_refClkSelect_clk_25MHz 0 13301 #define sc_x4_final_config_status_refClkSelect_clk_100MHz 1 13302 #define sc_x4_final_config_status_refClkSelect_clk_125MHz 2 13303 #define sc_x4_final_config_status_refClkSelect_clk_156p25MHz 3 13304 #define sc_x4_final_config_status_refClkSelect_clk_187p5MHz 4 13305 #define sc_x4_final_config_status_refClkSelect_clk_161p25Mhz 5 13306 #define sc_x4_final_config_status_refClkSelect_clk_50Mhz 6 13307 #define sc_x4_final_config_status_refClkSelect_clk_106p25Mhz 7 13308 13309 /**************************************************************************** 13310 * Enums: sc_x4_final_config_status_aerMMDdevTypeSelect 13311 */ 13312 #define sc_x4_final_config_status_aerMMDdevTypeSelect_combo_core 0 13313 #define sc_x4_final_config_status_aerMMDdevTypeSelect_PMA_PMD 1 13314 #define sc_x4_final_config_status_aerMMDdevTypeSelect_PCS 3 13315 #define sc_x4_final_config_status_aerMMDdevTypeSelect_PHY 4 13316 #define sc_x4_final_config_status_aerMMDdevTypeSelect_DTE 5 13317 #define sc_x4_final_config_status_aerMMDdevTypeSelect_CL73_AN 7 13318 13319 /**************************************************************************** 13320 * Enums: sc_x4_final_config_status_aerMMDportSelect 13321 */ 13322 #define sc_x4_final_config_status_aerMMDportSelect_ln0 0 13323 #define sc_x4_final_config_status_aerMMDportSelect_ln1 1 13324 #define sc_x4_final_config_status_aerMMDportSelect_ln2 2 13325 #define sc_x4_final_config_status_aerMMDportSelect_ln3 3 13326 #define sc_x4_final_config_status_aerMMDportSelect_BCST_ln0_1_2_3 511 13327 #define sc_x4_final_config_status_aerMMDportSelect_BCST_ln0_1 512 13328 #define sc_x4_final_config_status_aerMMDportSelect_BCST_ln2_3 513 13329 13330 /**************************************************************************** 13331 * Enums: sc_x4_final_config_status_firmwareModeSelect 13332 */ 13333 #define sc_x4_final_config_status_firmwareModeSelect_DEFAULT 0 13334 #define sc_x4_final_config_status_firmwareModeSelect_SFP_OPT_LR 1 13335 #define sc_x4_final_config_status_firmwareModeSelect_SFP_DAC 2 13336 #define sc_x4_final_config_status_firmwareModeSelect_XLAUI 3 13337 #define sc_x4_final_config_status_firmwareModeSelect_LONG_CH_6G 4 13338 13339 /**************************************************************************** 13340 * Enums: sc_x4_final_config_status_tempIdxSelect 13341 */ 13342 #define sc_x4_final_config_status_tempIdxSelect_LTE__22p9C 15 13343 #define sc_x4_final_config_status_tempIdxSelect_LTE__12p6C 14 13344 #define sc_x4_final_config_status_tempIdxSelect_LTE__3p0C 13 13345 #define sc_x4_final_config_status_tempIdxSelect_LTE_6p7C 12 13346 #define sc_x4_final_config_status_tempIdxSelect_LTE_16p4C 11 13347 #define sc_x4_final_config_status_tempIdxSelect_LTE_26p6C 10 13348 #define sc_x4_final_config_status_tempIdxSelect_LTE_36p3C 9 13349 #define sc_x4_final_config_status_tempIdxSelect_LTE_46p0C 8 13350 #define sc_x4_final_config_status_tempIdxSelect_LTE_56p2C 7 13351 #define sc_x4_final_config_status_tempIdxSelect_LTE_65p9C 6 13352 #define sc_x4_final_config_status_tempIdxSelect_LTE_75p6C 5 13353 #define sc_x4_final_config_status_tempIdxSelect_LTE_85p3C 4 13354 #define sc_x4_final_config_status_tempIdxSelect_LTE_95p5C 3 13355 #define sc_x4_final_config_status_tempIdxSelect_LTE_105p2C 2 13356 #define sc_x4_final_config_status_tempIdxSelect_LTE_114p9C 1 13357 #define sc_x4_final_config_status_tempIdxSelect_LTE_125p1C 0 13358 13359 /**************************************************************************** 13360 * Enums: sc_x4_final_config_status_port_mode 13361 */ 13362 #define sc_x4_final_config_status_port_mode_QUAD_PORT 0 13363 #define sc_x4_final_config_status_port_mode_TRI_1_PORT 1 13364 #define sc_x4_final_config_status_port_mode_TRI_2_PORT 2 13365 #define sc_x4_final_config_status_port_mode_DUAL_PORT 3 13366 #define sc_x4_final_config_status_port_mode_SINGLE_PORT 4 13367 13368 /**************************************************************************** 13369 * Enums: sc_x4_final_config_status_rev_letter_enum 13370 */ 13371 #define sc_x4_final_config_status_rev_letter_enum_REV_A 0 13372 #define sc_x4_final_config_status_rev_letter_enum_REV_B 1 13373 #define sc_x4_final_config_status_rev_letter_enum_REV_C 2 13374 #define sc_x4_final_config_status_rev_letter_enum_REV_D 3 13375 13376 /**************************************************************************** 13377 * Enums: sc_x4_final_config_status_rev_number_enum 13378 */ 13379 #define sc_x4_final_config_status_rev_number_enum_REV_0 0 13380 #define sc_x4_final_config_status_rev_number_enum_REV_1 1 13381 #define sc_x4_final_config_status_rev_number_enum_REV_2 2 13382 #define sc_x4_final_config_status_rev_number_enum_REV_3 3 13383 #define sc_x4_final_config_status_rev_number_enum_REV_4 4 13384 #define sc_x4_final_config_status_rev_number_enum_REV_5 5 13385 #define sc_x4_final_config_status_rev_number_enum_REV_6 6 13386 #define sc_x4_final_config_status_rev_number_enum_REV_7 7 13387 13388 /**************************************************************************** 13389 * Enums: sc_x4_final_config_status_bonding_enum 13390 */ 13391 #define sc_x4_final_config_status_bonding_enum_WIRE_BOND 0 13392 #define sc_x4_final_config_status_bonding_enum_FLIP_CHIP 1 13393 13394 /**************************************************************************** 13395 * Enums: sc_x4_final_config_status_tech_process 13396 */ 13397 #define sc_x4_final_config_status_tech_process_PROCESS_90NM 0 13398 #define sc_x4_final_config_status_tech_process_PROCESS_65NM 1 13399 #define sc_x4_final_config_status_tech_process_PROCESS_40NM 2 13400 #define sc_x4_final_config_status_tech_process_PROCESS_28NM 3 13401 13402 /**************************************************************************** 13403 * Enums: sc_x4_final_config_status_model_num 13404 */ 13405 #define sc_x4_final_config_status_model_num_SERDES_CL73 0 13406 #define sc_x4_final_config_status_model_num_XGXS_16G 1 13407 #define sc_x4_final_config_status_model_num_HYPERCORE 2 13408 #define sc_x4_final_config_status_model_num_HYPERLITE 3 13409 #define sc_x4_final_config_status_model_num_PCIE_G2_PIPE 4 13410 #define sc_x4_final_config_status_model_num_SERDES_1p25GBd 5 13411 #define sc_x4_final_config_status_model_num_SATA2 6 13412 #define sc_x4_final_config_status_model_num_QSGMII 7 13413 #define sc_x4_final_config_status_model_num_XGXS10G 8 13414 #define sc_x4_final_config_status_model_num_WARPCORE 9 13415 #define sc_x4_final_config_status_model_num_XFICORE 10 13416 #define sc_x4_final_config_status_model_num_RXFI 11 13417 #define sc_x4_final_config_status_model_num_WARPLITE 12 13418 #define sc_x4_final_config_status_model_num_PENTACORE 13 13419 #define sc_x4_final_config_status_model_num_ESM 14 13420 #define sc_x4_final_config_status_model_num_QUAD_SGMII 15 13421 #define sc_x4_final_config_status_model_num_WARPCORE_3 16 13422 #define sc_x4_final_config_status_model_num_TSC 17 13423 #define sc_x4_final_config_status_model_num_TSC4E 18 13424 #define sc_x4_final_config_status_model_num_TSC12E 19 13425 #define sc_x4_final_config_status_model_num_TSC4F 20 13426 #define sc_x4_final_config_status_model_num_XGXS_CL73_90NM 29 13427 #define sc_x4_final_config_status_model_num_SERDES_CL73_90NM 30 13428 #define sc_x4_final_config_status_model_num_WARPCORE3 32 13429 #define sc_x4_final_config_status_model_num_WARPCORE4_TSC 33 13430 #define sc_x4_final_config_status_model_num_RXAUI 34 13431 13432 /**************************************************************************** 13433 * Enums: sc_x4_final_config_status_payload 13434 */ 13435 #define sc_x4_final_config_status_payload_REPEAT_2_BYTES 0 13436 #define sc_x4_final_config_status_payload_RAMPING 1 13437 #define sc_x4_final_config_status_payload_CL48_CRPAT 2 13438 #define sc_x4_final_config_status_payload_CL48_CJPAT 3 13439 #define sc_x4_final_config_status_payload_CL36_LONG_CRPAT 4 13440 #define sc_x4_final_config_status_payload_CL36_SHORT_CRPAT 5 13441 13442 /**************************************************************************** 13443 * Enums: sc_x4_final_config_status_sc 13444 */ 13445 #define sc_x4_final_config_status_sc_S_10G_CR1 0 13446 #define sc_x4_final_config_status_sc_S_10G_KR1 1 13447 #define sc_x4_final_config_status_sc_S_10G_X1 2 13448 #define sc_x4_final_config_status_sc_S_10G_HG2_CR1 4 13449 #define sc_x4_final_config_status_sc_S_10G_HG2_KR1 5 13450 #define sc_x4_final_config_status_sc_S_10G_HG2_X1 6 13451 #define sc_x4_final_config_status_sc_S_20G_CR1 8 13452 #define sc_x4_final_config_status_sc_S_20G_KR1 9 13453 #define sc_x4_final_config_status_sc_S_20G_X1 10 13454 #define sc_x4_final_config_status_sc_S_20G_HG2_CR1 12 13455 #define sc_x4_final_config_status_sc_S_20G_HG2_KR1 13 13456 #define sc_x4_final_config_status_sc_S_20G_HG2_X1 14 13457 #define sc_x4_final_config_status_sc_S_25G_CR1 16 13458 #define sc_x4_final_config_status_sc_S_25G_KR1 17 13459 #define sc_x4_final_config_status_sc_S_25G_X1 18 13460 #define sc_x4_final_config_status_sc_S_25G_HG2_CR1 20 13461 #define sc_x4_final_config_status_sc_S_25G_HG2_KR1 21 13462 #define sc_x4_final_config_status_sc_S_25G_HG2_X1 22 13463 #define sc_x4_final_config_status_sc_S_20G_CR2 24 13464 #define sc_x4_final_config_status_sc_S_20G_KR2 25 13465 #define sc_x4_final_config_status_sc_S_20G_X2 26 13466 #define sc_x4_final_config_status_sc_S_20G_HG2_CR2 28 13467 #define sc_x4_final_config_status_sc_S_20G_HG2_KR2 29 13468 #define sc_x4_final_config_status_sc_S_20G_HG2_X2 30 13469 #define sc_x4_final_config_status_sc_S_40G_CR2 32 13470 #define sc_x4_final_config_status_sc_S_40G_KR2 33 13471 #define sc_x4_final_config_status_sc_S_40G_X2 34 13472 #define sc_x4_final_config_status_sc_S_40G_HG2_CR2 36 13473 #define sc_x4_final_config_status_sc_S_40G_HG2_KR2 37 13474 #define sc_x4_final_config_status_sc_S_40G_HG2_X2 38 13475 #define sc_x4_final_config_status_sc_S_40G_CR4 40 13476 #define sc_x4_final_config_status_sc_S_40G_KR4 41 13477 #define sc_x4_final_config_status_sc_S_40G_X4 42 13478 #define sc_x4_final_config_status_sc_S_40G_HG2_CR4 44 13479 #define sc_x4_final_config_status_sc_S_40G_HG2_KR4 45 13480 #define sc_x4_final_config_status_sc_S_40G_HG2_X4 46 13481 #define sc_x4_final_config_status_sc_S_50G_CR2 48 13482 #define sc_x4_final_config_status_sc_S_50G_KR2 49 13483 #define sc_x4_final_config_status_sc_S_50G_X2 50 13484 #define sc_x4_final_config_status_sc_S_50G_HG2_CR2 52 13485 #define sc_x4_final_config_status_sc_S_50G_HG2_KR2 53 13486 #define sc_x4_final_config_status_sc_S_50G_HG2_X2 54 13487 #define sc_x4_final_config_status_sc_S_50G_CR4 56 13488 #define sc_x4_final_config_status_sc_S_50G_KR4 57 13489 #define sc_x4_final_config_status_sc_S_50G_X4 58 13490 #define sc_x4_final_config_status_sc_S_50G_HG2_CR4 60 13491 #define sc_x4_final_config_status_sc_S_50G_HG2_KR4 61 13492 #define sc_x4_final_config_status_sc_S_50G_HG2_X4 62 13493 #define sc_x4_final_config_status_sc_S_100G_CR4 64 13494 #define sc_x4_final_config_status_sc_S_100G_KR4 65 13495 #define sc_x4_final_config_status_sc_S_100G_X4 66 13496 #define sc_x4_final_config_status_sc_S_100G_HG2_CR4 68 13497 #define sc_x4_final_config_status_sc_S_100G_HG2_KR4 69 13498 #define sc_x4_final_config_status_sc_S_100G_HG2_X4 70 13499 #define sc_x4_final_config_status_sc_S_CL73_20GVCO 72 13500 #define sc_x4_final_config_status_sc_S_CL73_25GVCO 80 13501 #define sc_x4_final_config_status_sc_S_CL36_20GVCO 88 13502 #define sc_x4_final_config_status_sc_S_CL36_25GVCO 96 13503 13504 /**************************************************************************** 13505 * Enums: sc_x4_final_config_status_t_fifo_modes 13506 */ 13507 #define sc_x4_final_config_status_t_fifo_modes_T_FIFO_MODE_BYPASS 0 13508 #define sc_x4_final_config_status_t_fifo_modes_T_FIFO_MODE_40G 1 13509 #define sc_x4_final_config_status_t_fifo_modes_T_FIFO_MODE_100G 2 13510 #define sc_x4_final_config_status_t_fifo_modes_T_FIFO_MODE_20G 3 13511 13512 /**************************************************************************** 13513 * Enums: sc_x4_final_config_status_t_enc_modes 13514 */ 13515 #define sc_x4_final_config_status_t_enc_modes_T_ENC_MODE_BYPASS 0 13516 #define sc_x4_final_config_status_t_enc_modes_T_ENC_MODE_CL49 1 13517 #define sc_x4_final_config_status_t_enc_modes_T_ENC_MODE_CL82 2 13518 13519 /**************************************************************************** 13520 * Enums: sc_x4_final_config_status_btmx_mode 13521 */ 13522 #define sc_x4_final_config_status_btmx_mode_BS_BTMX_MODE_1to1 0 13523 #define sc_x4_final_config_status_btmx_mode_BS_BTMX_MODE_2to1 1 13524 #define sc_x4_final_config_status_btmx_mode_BS_BTMX_MODE_5to1 2 13525 13526 /**************************************************************************** 13527 * Enums: sc_x4_final_config_status_t_type_cl82 13528 */ 13529 #define sc_x4_final_config_status_t_type_cl82_T_TYPE_B1 5 13530 #define sc_x4_final_config_status_t_type_cl82_T_TYPE_C 4 13531 #define sc_x4_final_config_status_t_type_cl82_T_TYPE_S 3 13532 #define sc_x4_final_config_status_t_type_cl82_T_TYPE_T 2 13533 #define sc_x4_final_config_status_t_type_cl82_T_TYPE_D 1 13534 #define sc_x4_final_config_status_t_type_cl82_T_TYPE_E 0 13535 13536 /**************************************************************************** 13537 * Enums: sc_x4_final_config_status_txsm_state_cl82 13538 */ 13539 #define sc_x4_final_config_status_txsm_state_cl82_TX_HIG_END 6 13540 #define sc_x4_final_config_status_txsm_state_cl82_TX_HIG_START 5 13541 #define sc_x4_final_config_status_txsm_state_cl82_TX_E 4 13542 #define sc_x4_final_config_status_txsm_state_cl82_TX_T 3 13543 #define sc_x4_final_config_status_txsm_state_cl82_TX_D 2 13544 #define sc_x4_final_config_status_txsm_state_cl82_TX_C 1 13545 #define sc_x4_final_config_status_txsm_state_cl82_TX_INIT 0 13546 13547 /**************************************************************************** 13548 * Enums: sc_x4_final_config_status_ltxsm_state_cl82 13549 */ 13550 #define sc_x4_final_config_status_ltxsm_state_cl82_TX_HIG_END 64 13551 #define sc_x4_final_config_status_ltxsm_state_cl82_TX_HIG_START 32 13552 #define sc_x4_final_config_status_ltxsm_state_cl82_TX_E 16 13553 #define sc_x4_final_config_status_ltxsm_state_cl82_TX_T 8 13554 #define sc_x4_final_config_status_ltxsm_state_cl82_TX_D 4 13555 #define sc_x4_final_config_status_ltxsm_state_cl82_TX_C 2 13556 #define sc_x4_final_config_status_ltxsm_state_cl82_TX_INIT 1 13557 13558 /**************************************************************************** 13559 * Enums: sc_x4_final_config_status_r_type_coded_cl82 13560 */ 13561 #define sc_x4_final_config_status_r_type_coded_cl82_R_TYPE_B1 32 13562 #define sc_x4_final_config_status_r_type_coded_cl82_R_TYPE_C 16 13563 #define sc_x4_final_config_status_r_type_coded_cl82_R_TYPE_S 8 13564 #define sc_x4_final_config_status_r_type_coded_cl82_R_TYPE_T 4 13565 #define sc_x4_final_config_status_r_type_coded_cl82_R_TYPE_D 2 13566 #define sc_x4_final_config_status_r_type_coded_cl82_R_TYPE_E 1 13567 13568 /**************************************************************************** 13569 * Enums: sc_x4_final_config_status_rxsm_state_cl82 13570 */ 13571 #define sc_x4_final_config_status_rxsm_state_cl82_RX_HIG_END 64 13572 #define sc_x4_final_config_status_rxsm_state_cl82_RX_HIG_START 32 13573 #define sc_x4_final_config_status_rxsm_state_cl82_RX_E 16 13574 #define sc_x4_final_config_status_rxsm_state_cl82_RX_T 8 13575 #define sc_x4_final_config_status_rxsm_state_cl82_RX_D 4 13576 #define sc_x4_final_config_status_rxsm_state_cl82_RX_C 2 13577 #define sc_x4_final_config_status_rxsm_state_cl82_RX_INIT 1 13578 13579 /**************************************************************************** 13580 * Enums: sc_x4_final_config_status_deskew_state 13581 */ 13582 #define sc_x4_final_config_status_deskew_state_ALIGN_ACQUIRED 2 13583 #define sc_x4_final_config_status_deskew_state_LOSS_OF_ALIGNMENT 1 13584 13585 /**************************************************************************** 13586 * Enums: sc_x4_final_config_status_os_mode_enum 13587 */ 13588 #define sc_x4_final_config_status_os_mode_enum_OS_MODE_1 0 13589 #define sc_x4_final_config_status_os_mode_enum_OS_MODE_2 1 13590 #define sc_x4_final_config_status_os_mode_enum_OS_MODE_4 2 13591 #define sc_x4_final_config_status_os_mode_enum_OS_MODE_16p5 8 13592 #define sc_x4_final_config_status_os_mode_enum_OS_MODE_20p625 12 13593 13594 /**************************************************************************** 13595 * Enums: sc_x4_final_config_status_scr_modes 13596 */ 13597 #define sc_x4_final_config_status_scr_modes_T_SCR_MODE_BYPASS 0 13598 #define sc_x4_final_config_status_scr_modes_T_SCR_MODE_CL49 1 13599 #define sc_x4_final_config_status_scr_modes_T_SCR_MODE_40G_2_LANE 2 13600 #define sc_x4_final_config_status_scr_modes_T_SCR_MODE_100G 3 13601 #define sc_x4_final_config_status_scr_modes_T_SCR_MODE_20G 4 13602 #define sc_x4_final_config_status_scr_modes_T_SCR_MODE_40G_4_LANE 5 13603 13604 /**************************************************************************** 13605 * Enums: sc_x4_final_config_status_descr_modes 13606 */ 13607 #define sc_x4_final_config_status_descr_modes_R_DESCR_MODE_BYPASS 0 13608 #define sc_x4_final_config_status_descr_modes_R_DESCR_MODE_CL49 1 13609 #define sc_x4_final_config_status_descr_modes_R_DESCR_MODE_CL82 2 13610 13611 /**************************************************************************** 13612 * Enums: sc_x4_final_config_status_r_dec_tl_mode 13613 */ 13614 #define sc_x4_final_config_status_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 13615 #define sc_x4_final_config_status_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 13616 #define sc_x4_final_config_status_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 13617 13618 /**************************************************************************** 13619 * Enums: sc_x4_final_config_status_r_dec_fsm_mode 13620 */ 13621 #define sc_x4_final_config_status_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 13622 #define sc_x4_final_config_status_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 13623 #define sc_x4_final_config_status_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 13624 13625 /**************************************************************************** 13626 * Enums: sc_x4_final_config_status_r_deskew_mode 13627 */ 13628 #define sc_x4_final_config_status_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 13629 #define sc_x4_final_config_status_r_deskew_mode_R_DESKEW_MODE_20G 1 13630 #define sc_x4_final_config_status_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 13631 #define sc_x4_final_config_status_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 13632 #define sc_x4_final_config_status_r_deskew_mode_R_DESKEW_MODE_100G 4 13633 #define sc_x4_final_config_status_r_deskew_mode_R_DESKEW_MODE_CL49 5 13634 #define sc_x4_final_config_status_r_deskew_mode_R_DESKEW_MODE_CL91 6 13635 13636 /**************************************************************************** 13637 * Enums: sc_x4_final_config_status_bs_dist_modes 13638 */ 13639 #define sc_x4_final_config_status_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 13640 #define sc_x4_final_config_status_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 13641 #define sc_x4_final_config_status_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 13642 #define sc_x4_final_config_status_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 13643 13644 /**************************************************************************** 13645 * Enums: sc_x4_final_config_status_cl49_t_type 13646 */ 13647 #define sc_x4_final_config_status_cl49_t_type_BAD_T_TYPE 15 13648 #define sc_x4_final_config_status_cl49_t_type_T_TYPE_B0 11 13649 #define sc_x4_final_config_status_cl49_t_type_T_TYPE_OB 10 13650 #define sc_x4_final_config_status_cl49_t_type_T_TYPE_B1 9 13651 #define sc_x4_final_config_status_cl49_t_type_T_TYPE_DB 8 13652 #define sc_x4_final_config_status_cl49_t_type_T_TYPE_FC 7 13653 #define sc_x4_final_config_status_cl49_t_type_T_TYPE_TB 6 13654 #define sc_x4_final_config_status_cl49_t_type_T_TYPE_LI 5 13655 #define sc_x4_final_config_status_cl49_t_type_T_TYPE_C 4 13656 #define sc_x4_final_config_status_cl49_t_type_T_TYPE_S 3 13657 #define sc_x4_final_config_status_cl49_t_type_T_TYPE_T 2 13658 #define sc_x4_final_config_status_cl49_t_type_T_TYPE_D 1 13659 #define sc_x4_final_config_status_cl49_t_type_T_TYPE_E 0 13660 13661 /**************************************************************************** 13662 * Enums: sc_x4_final_config_status_cl49_txsm_states 13663 */ 13664 #define sc_x4_final_config_status_cl49_txsm_states_TX_HIG_END 7 13665 #define sc_x4_final_config_status_cl49_txsm_states_TX_HIG_START 6 13666 #define sc_x4_final_config_status_cl49_txsm_states_TX_LI 5 13667 #define sc_x4_final_config_status_cl49_txsm_states_TX_E 4 13668 #define sc_x4_final_config_status_cl49_txsm_states_TX_T 3 13669 #define sc_x4_final_config_status_cl49_txsm_states_TX_D 2 13670 #define sc_x4_final_config_status_cl49_txsm_states_TX_C 1 13671 #define sc_x4_final_config_status_cl49_txsm_states_TX_INIT 0 13672 13673 /**************************************************************************** 13674 * Enums: sc_x4_final_config_status_cl49_ltxsm_states 13675 */ 13676 #define sc_x4_final_config_status_cl49_ltxsm_states_TX_HIG_END 128 13677 #define sc_x4_final_config_status_cl49_ltxsm_states_TX_HIG_START 64 13678 #define sc_x4_final_config_status_cl49_ltxsm_states_TX_LI 32 13679 #define sc_x4_final_config_status_cl49_ltxsm_states_TX_E 16 13680 #define sc_x4_final_config_status_cl49_ltxsm_states_TX_T 8 13681 #define sc_x4_final_config_status_cl49_ltxsm_states_TX_D 4 13682 #define sc_x4_final_config_status_cl49_ltxsm_states_TX_C 2 13683 #define sc_x4_final_config_status_cl49_ltxsm_states_TX_INIT 1 13684 13685 /**************************************************************************** 13686 * Enums: sc_x4_final_config_status_burst_error_mode 13687 */ 13688 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_11_BITS 0 13689 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_16_BITS 1 13690 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_17_BITS 2 13691 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_18_BITS 3 13692 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_19_BITS 4 13693 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_20_BITS 5 13694 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_21_BITS 6 13695 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_22_BITS 7 13696 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_23_BITS 8 13697 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_24_BITS 9 13698 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_25_BITS 10 13699 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_26_BITS 11 13700 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_27_BITS 12 13701 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_28_BITS 13 13702 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_29_BITS 14 13703 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_30_BITS 15 13704 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_31_BITS 16 13705 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_32_BITS 17 13706 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_33_BITS 18 13707 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_34_BITS 19 13708 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_35_BITS 20 13709 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_36_BITS 21 13710 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_37_BITS 22 13711 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_38_BITS 23 13712 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_39_BITS 24 13713 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_40_BITS 25 13714 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_41_BITS 26 13715 13716 /**************************************************************************** 13717 * Enums: sc_x4_final_config_status_bermon_state 13718 */ 13719 #define sc_x4_final_config_status_bermon_state_HI_BER 4 13720 #define sc_x4_final_config_status_bermon_state_GOOD_BER 3 13721 #define sc_x4_final_config_status_bermon_state_BER_TEST_SH 2 13722 #define sc_x4_final_config_status_bermon_state_START_TIMER 1 13723 #define sc_x4_final_config_status_bermon_state_BER_MT_INIT 0 13724 13725 /**************************************************************************** 13726 * Enums: sc_x4_final_config_status_rxsm_state_cl49 13727 */ 13728 #define sc_x4_final_config_status_rxsm_state_cl49_RX_HIG_END 128 13729 #define sc_x4_final_config_status_rxsm_state_cl49_RX_HIG_START 64 13730 #define sc_x4_final_config_status_rxsm_state_cl49_RX_LI 32 13731 #define sc_x4_final_config_status_rxsm_state_cl49_RX_E 16 13732 #define sc_x4_final_config_status_rxsm_state_cl49_RX_T 8 13733 #define sc_x4_final_config_status_rxsm_state_cl49_RX_D 4 13734 #define sc_x4_final_config_status_rxsm_state_cl49_RX_C 2 13735 #define sc_x4_final_config_status_rxsm_state_cl49_RX_INIT 1 13736 13737 /**************************************************************************** 13738 * Enums: sc_x4_final_config_status_r_type 13739 */ 13740 #define sc_x4_final_config_status_r_type_BAD_R_TYPE 15 13741 #define sc_x4_final_config_status_r_type_R_TYPE_B0 11 13742 #define sc_x4_final_config_status_r_type_R_TYPE_OB 10 13743 #define sc_x4_final_config_status_r_type_R_TYPE_B1 9 13744 #define sc_x4_final_config_status_r_type_R_TYPE_DB 8 13745 #define sc_x4_final_config_status_r_type_R_TYPE_FC 7 13746 #define sc_x4_final_config_status_r_type_R_TYPE_TB 6 13747 #define sc_x4_final_config_status_r_type_R_TYPE_LI 5 13748 #define sc_x4_final_config_status_r_type_R_TYPE_C 4 13749 #define sc_x4_final_config_status_r_type_R_TYPE_S 3 13750 #define sc_x4_final_config_status_r_type_R_TYPE_T 2 13751 #define sc_x4_final_config_status_r_type_R_TYPE_D 1 13752 #define sc_x4_final_config_status_r_type_R_TYPE_E 0 13753 13754 /**************************************************************************** 13755 * Enums: sc_x4_final_config_status_am_lock_state 13756 */ 13757 #define sc_x4_final_config_status_am_lock_state_INVALID_AM 512 13758 #define sc_x4_final_config_status_am_lock_state_GOOD_AM 256 13759 #define sc_x4_final_config_status_am_lock_state_COMP_AM 128 13760 #define sc_x4_final_config_status_am_lock_state_TIMER_2 64 13761 #define sc_x4_final_config_status_am_lock_state_AM_2_GOOD 32 13762 #define sc_x4_final_config_status_am_lock_state_COMP_2ND 16 13763 #define sc_x4_final_config_status_am_lock_state_TIMER_1 8 13764 #define sc_x4_final_config_status_am_lock_state_FIND_1ST 4 13765 #define sc_x4_final_config_status_am_lock_state_AM_RESET_CNT 2 13766 #define sc_x4_final_config_status_am_lock_state_AM_LOCK_INIT 1 13767 13768 /**************************************************************************** 13769 * Enums: sc_x4_final_config_status_msg_selector 13770 */ 13771 #define sc_x4_final_config_status_msg_selector_RESERVED 0 13772 #define sc_x4_final_config_status_msg_selector_VALUE_802p3 1 13773 #define sc_x4_final_config_status_msg_selector_VALUE_802p9 2 13774 #define sc_x4_final_config_status_msg_selector_VALUE_802p5 3 13775 #define sc_x4_final_config_status_msg_selector_VALUE_1394 4 13776 13777 /**************************************************************************** 13778 * Enums: sc_x4_final_config_status_synce_enum 13779 */ 13780 #define sc_x4_final_config_status_synce_enum_SYNCE_NO_DIV 0 13781 #define sc_x4_final_config_status_synce_enum_SYNCE_DIV_7 1 13782 #define sc_x4_final_config_status_synce_enum_SYNCE_DIV_11 2 13783 13784 /**************************************************************************** 13785 * Enums: sc_x4_final_config_status_synce_enum_stage0 13786 */ 13787 #define sc_x4_final_config_status_synce_enum_stage0_SYNCE_NO_DIV 0 13788 #define sc_x4_final_config_status_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 13789 #define sc_x4_final_config_status_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 13790 13791 /**************************************************************************** 13792 * Enums: sc_x4_final_config_status_cl91_sync_state 13793 */ 13794 #define sc_x4_final_config_status_cl91_sync_state_FIND_1ST 0 13795 #define sc_x4_final_config_status_cl91_sync_state_COUNT_NEXT 1 13796 #define sc_x4_final_config_status_cl91_sync_state_COMP_2ND 2 13797 #define sc_x4_final_config_status_cl91_sync_state_TWO_GOOD 3 13798 13799 /**************************************************************************** 13800 * Enums: sc_x4_final_config_status_cl91_algn_state 13801 */ 13802 #define sc_x4_final_config_status_cl91_algn_state_LOSS_OF_ALIGNMENT 0 13803 #define sc_x4_final_config_status_cl91_algn_state_DESKEW 1 13804 #define sc_x4_final_config_status_cl91_algn_state_DESKEW_FAIL 2 13805 #define sc_x4_final_config_status_cl91_algn_state_ALIGN_ACQUIRED 3 13806 #define sc_x4_final_config_status_cl91_algn_state_CW_GOOD 4 13807 #define sc_x4_final_config_status_cl91_algn_state_CW_BAD 5 13808 #define sc_x4_final_config_status_cl91_algn_state_THREE_BAD 6 13809 13810 /**************************************************************************** 13811 * Enums: sc_x4_final_config_status_fec_sel 13812 */ 13813 #define sc_x4_final_config_status_fec_sel_NO_FEC 0 13814 #define sc_x4_final_config_status_fec_sel_FEC_CL74 1 13815 #define sc_x4_final_config_status_fec_sel_FEC_CL91 2 13816 13817 /**************************************************************************** 13818 * Enums: testshared0_cl36TxEEEStates_l 13819 */ 13820 #define testshared0_cl36TxEEEStates_l_TX_REFRESH 8 13821 #define testshared0_cl36TxEEEStates_l_TX_QUIET 4 13822 #define testshared0_cl36TxEEEStates_l_TX_SLEEP 2 13823 #define testshared0_cl36TxEEEStates_l_TX_ACTIVE 1 13824 13825 /**************************************************************************** 13826 * Enums: testshared0_cl36TxEEEStates_c 13827 */ 13828 #define testshared0_cl36TxEEEStates_c_TX_REFRESH 3 13829 #define testshared0_cl36TxEEEStates_c_TX_QUIET 2 13830 #define testshared0_cl36TxEEEStates_c_TX_SLEEP 1 13831 #define testshared0_cl36TxEEEStates_c_TX_ACTIVE 0 13832 13833 /**************************************************************************** 13834 * Enums: testshared0_cl49TxEEEStates_l 13835 */ 13836 #define testshared0_cl49TxEEEStates_l_SCR_RESET_2 64 13837 #define testshared0_cl49TxEEEStates_l_SCR_RESET_1 32 13838 #define testshared0_cl49TxEEEStates_l_TX_WAKE 16 13839 #define testshared0_cl49TxEEEStates_l_TX_REFRESH 8 13840 #define testshared0_cl49TxEEEStates_l_TX_QUIET 4 13841 #define testshared0_cl49TxEEEStates_l_TX_SLEEP 2 13842 #define testshared0_cl49TxEEEStates_l_TX_ACTIVE 1 13843 13844 /**************************************************************************** 13845 * Enums: testshared0_fec_req_enum 13846 */ 13847 #define testshared0_fec_req_enum_FEC_not_supported 0 13848 #define testshared0_fec_req_enum_FEC_supported_but_not_requested 1 13849 #define testshared0_fec_req_enum_invalid_setting 2 13850 #define testshared0_fec_req_enum_FEC_supported_and_requested 3 13851 13852 /**************************************************************************** 13853 * Enums: testshared0_cl73_pause_enum 13854 */ 13855 #define testshared0_cl73_pause_enum_No_PAUSE_ability 0 13856 #define testshared0_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 13857 #define testshared0_cl73_pause_enum_Symmetric_PAUSE_ability 1 13858 #define testshared0_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 13859 13860 /**************************************************************************** 13861 * Enums: testshared0_cl49TxEEEStates_c 13862 */ 13863 #define testshared0_cl49TxEEEStates_c_SCR_RESET_2 6 13864 #define testshared0_cl49TxEEEStates_c_SCR_RESET_1 5 13865 #define testshared0_cl49TxEEEStates_c_TX_WAKE 4 13866 #define testshared0_cl49TxEEEStates_c_TX_REFRESH 3 13867 #define testshared0_cl49TxEEEStates_c_TX_QUIET 2 13868 #define testshared0_cl49TxEEEStates_c_TX_SLEEP 1 13869 #define testshared0_cl49TxEEEStates_c_TX_ACTIVE 0 13870 13871 /**************************************************************************** 13872 * Enums: testshared0_cl36RxEEEStates_l 13873 */ 13874 #define testshared0_cl36RxEEEStates_l_RX_LINK_FAIL 32 13875 #define testshared0_cl36RxEEEStates_l_RX_WTF 16 13876 #define testshared0_cl36RxEEEStates_l_RX_WAKE 8 13877 #define testshared0_cl36RxEEEStates_l_RX_QUIET 4 13878 #define testshared0_cl36RxEEEStates_l_RX_SLEEP 2 13879 #define testshared0_cl36RxEEEStates_l_RX_ACTIVE 1 13880 13881 /**************************************************************************** 13882 * Enums: testshared0_cl36RxEEEStates_c 13883 */ 13884 #define testshared0_cl36RxEEEStates_c_RX_LINK_FAIL 5 13885 #define testshared0_cl36RxEEEStates_c_RX_WTF 4 13886 #define testshared0_cl36RxEEEStates_c_RX_WAKE 3 13887 #define testshared0_cl36RxEEEStates_c_RX_QUIET 2 13888 #define testshared0_cl36RxEEEStates_c_RX_SLEEP 1 13889 #define testshared0_cl36RxEEEStates_c_RX_ACTIVE 0 13890 13891 /**************************************************************************** 13892 * Enums: testshared0_cl49RxEEEStates_l 13893 */ 13894 #define testshared0_cl49RxEEEStates_l_RX_LINK_FAIL 32 13895 #define testshared0_cl49RxEEEStates_l_RX_WTF 16 13896 #define testshared0_cl49RxEEEStates_l_RX_WAKE 8 13897 #define testshared0_cl49RxEEEStates_l_RX_QUIET 4 13898 #define testshared0_cl49RxEEEStates_l_RX_SLEEP 2 13899 #define testshared0_cl49RxEEEStates_l_RX_ACTIVE 1 13900 13901 /**************************************************************************** 13902 * Enums: testshared0_cl49RxEEEStates_c 13903 */ 13904 #define testshared0_cl49RxEEEStates_c_RX_LINK_FAIL 5 13905 #define testshared0_cl49RxEEEStates_c_RX_WTF 4 13906 #define testshared0_cl49RxEEEStates_c_RX_WAKE 3 13907 #define testshared0_cl49RxEEEStates_c_RX_QUIET 2 13908 #define testshared0_cl49RxEEEStates_c_RX_SLEEP 1 13909 #define testshared0_cl49RxEEEStates_c_RX_ACTIVE 0 13910 13911 /**************************************************************************** 13912 * Enums: testshared0_cl48TxEEEStates_l 13913 */ 13914 #define testshared0_cl48TxEEEStates_l_TX_REFRESH 8 13915 #define testshared0_cl48TxEEEStates_l_TX_QUIET 4 13916 #define testshared0_cl48TxEEEStates_l_TX_SLEEP 2 13917 #define testshared0_cl48TxEEEStates_l_TX_ACTIVE 1 13918 13919 /**************************************************************************** 13920 * Enums: testshared0_cl48TxEEEStates_c 13921 */ 13922 #define testshared0_cl48TxEEEStates_c_TX_REFRESH 3 13923 #define testshared0_cl48TxEEEStates_c_TX_QUIET 2 13924 #define testshared0_cl48TxEEEStates_c_TX_SLEEP 1 13925 #define testshared0_cl48TxEEEStates_c_TX_ACTIVE 0 13926 13927 /**************************************************************************** 13928 * Enums: testshared0_cl48RxEEEStates_l 13929 */ 13930 #define testshared0_cl48RxEEEStates_l_RX_LINK_FAIL 32 13931 #define testshared0_cl48RxEEEStates_l_RX_WAKE 16 13932 #define testshared0_cl48RxEEEStates_l_RX_QUIET 8 13933 #define testshared0_cl48RxEEEStates_l_RX_DEACT 4 13934 #define testshared0_cl48RxEEEStates_l_RX_SLEEP 2 13935 #define testshared0_cl48RxEEEStates_l_RX_ACTIVE 1 13936 13937 /**************************************************************************** 13938 * Enums: testshared0_cl48RxEEEStates_c 13939 */ 13940 #define testshared0_cl48RxEEEStates_c_RX_LINK_FAIL 5 13941 #define testshared0_cl48RxEEEStates_c_RX_WAKE 4 13942 #define testshared0_cl48RxEEEStates_c_RX_QUIET 3 13943 #define testshared0_cl48RxEEEStates_c_RX_DEACT 2 13944 #define testshared0_cl48RxEEEStates_c_RX_SLEEP 1 13945 #define testshared0_cl48RxEEEStates_c_RX_ACTIVE 0 13946 13947 /**************************************************************************** 13948 * Enums: testshared0_IQP_Options 13949 */ 13950 #define testshared0_IQP_Options_i50uA 0 13951 #define testshared0_IQP_Options_i100uA 1 13952 #define testshared0_IQP_Options_i150uA 2 13953 #define testshared0_IQP_Options_i200uA 3 13954 #define testshared0_IQP_Options_i250uA 4 13955 #define testshared0_IQP_Options_i300uA 5 13956 #define testshared0_IQP_Options_i350uA 6 13957 #define testshared0_IQP_Options_i400uA 7 13958 #define testshared0_IQP_Options_i450uA 8 13959 #define testshared0_IQP_Options_i500uA 9 13960 #define testshared0_IQP_Options_i550uA 10 13961 #define testshared0_IQP_Options_i600uA 11 13962 #define testshared0_IQP_Options_i650uA 12 13963 #define testshared0_IQP_Options_i700uA 13 13964 #define testshared0_IQP_Options_i750uA 14 13965 #define testshared0_IQP_Options_i800uA 15 13966 13967 /**************************************************************************** 13968 * Enums: testshared0_IDriver_Options 13969 */ 13970 #define testshared0_IDriver_Options_v680mV 0 13971 #define testshared0_IDriver_Options_v730mV 1 13972 #define testshared0_IDriver_Options_v780mV 2 13973 #define testshared0_IDriver_Options_v830mV 3 13974 #define testshared0_IDriver_Options_v880mV 4 13975 #define testshared0_IDriver_Options_v930mV 5 13976 #define testshared0_IDriver_Options_v980mV 6 13977 #define testshared0_IDriver_Options_v1010mV 7 13978 #define testshared0_IDriver_Options_v1040mV 8 13979 #define testshared0_IDriver_Options_v1060mV 9 13980 #define testshared0_IDriver_Options_v1070mV 10 13981 #define testshared0_IDriver_Options_v1080mV 11 13982 #define testshared0_IDriver_Options_v1085mV 12 13983 #define testshared0_IDriver_Options_v1090mV 13 13984 #define testshared0_IDriver_Options_v1095mV 14 13985 #define testshared0_IDriver_Options_v1100mV 15 13986 13987 /**************************************************************************** 13988 * Enums: testshared0_operationModes 13989 */ 13990 #define testshared0_operationModes_XGXS 0 13991 #define testshared0_operationModes_XGXG_nCC 1 13992 #define testshared0_operationModes_Indlane_OS8 4 13993 #define testshared0_operationModes_IndLane_OS5 5 13994 #define testshared0_operationModes_PCI 7 13995 #define testshared0_operationModes_XGXS_nLQ 8 13996 #define testshared0_operationModes_XGXS_nLQnCC 9 13997 #define testshared0_operationModes_PBypass 10 13998 #define testshared0_operationModes_PBypass_nDSK 11 13999 #define testshared0_operationModes_ComboCoreMode 12 14000 #define testshared0_operationModes_Clocks_off 15 14001 14002 /**************************************************************************** 14003 * Enums: testshared0_actualSpeeds 14004 */ 14005 #define testshared0_actualSpeeds_dr_10M 0 14006 #define testshared0_actualSpeeds_dr_100M 1 14007 #define testshared0_actualSpeeds_dr_1G 2 14008 #define testshared0_actualSpeeds_dr_2p5G 3 14009 #define testshared0_actualSpeeds_dr_5G_X4 4 14010 #define testshared0_actualSpeeds_dr_6G_X4 5 14011 #define testshared0_actualSpeeds_dr_10G_HiG 6 14012 #define testshared0_actualSpeeds_dr_10G_CX4 7 14013 #define testshared0_actualSpeeds_dr_12G_HiG 8 14014 #define testshared0_actualSpeeds_dr_12p5G_X4 9 14015 #define testshared0_actualSpeeds_dr_13G_X4 10 14016 #define testshared0_actualSpeeds_dr_15G_X4 11 14017 #define testshared0_actualSpeeds_dr_16G_X4 12 14018 #define testshared0_actualSpeeds_dr_1G_KX 13 14019 #define testshared0_actualSpeeds_dr_10G_KX4 14 14020 #define testshared0_actualSpeeds_dr_10G_KR 15 14021 #define testshared0_actualSpeeds_dr_5G 16 14022 #define testshared0_actualSpeeds_dr_6p4G 17 14023 #define testshared0_actualSpeeds_dr_20G_X4 18 14024 #define testshared0_actualSpeeds_dr_21G_X4 19 14025 #define testshared0_actualSpeeds_dr_25G_X4 20 14026 #define testshared0_actualSpeeds_dr_10G_HiG_DXGXS 21 14027 #define testshared0_actualSpeeds_dr_10G_DXGXS 22 14028 #define testshared0_actualSpeeds_dr_10p5G_HiG_DXGXS 23 14029 #define testshared0_actualSpeeds_dr_10p5G_DXGXS 24 14030 #define testshared0_actualSpeeds_dr_12p773G_HiG_DXGXS 25 14031 #define testshared0_actualSpeeds_dr_12p773G_DXGXS 26 14032 #define testshared0_actualSpeeds_dr_10G_XFI 27 14033 #define testshared0_actualSpeeds_dr_40G 28 14034 #define testshared0_actualSpeeds_dr_20G_HiG_DXGXS 29 14035 #define testshared0_actualSpeeds_dr_20G_DXGXS 30 14036 #define testshared0_actualSpeeds_dr_10G_SFI 31 14037 #define testshared0_actualSpeeds_dr_31p5G 32 14038 #define testshared0_actualSpeeds_dr_32p7G 33 14039 #define testshared0_actualSpeeds_dr_20G_SCR 34 14040 #define testshared0_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 14041 #define testshared0_actualSpeeds_dr_10G_DXGXS_SCR 36 14042 #define testshared0_actualSpeeds_dr_12G_R2 37 14043 #define testshared0_actualSpeeds_dr_10G_X2 38 14044 #define testshared0_actualSpeeds_dr_40G_KR4 39 14045 #define testshared0_actualSpeeds_dr_40G_CR4 40 14046 #define testshared0_actualSpeeds_dr_100G_CR10 41 14047 #define testshared0_actualSpeeds_dr_15p75G_DXGXS 44 14048 #define testshared0_actualSpeeds_dr_20G_KR2 57 14049 #define testshared0_actualSpeeds_dr_20G_CR2 58 14050 14051 /**************************************************************************** 14052 * Enums: testshared0_actualSpeedsMisc1 14053 */ 14054 #define testshared0_actualSpeedsMisc1_dr_2500BRCM_X1 16 14055 #define testshared0_actualSpeedsMisc1_dr_5000BRCM_X4 17 14056 #define testshared0_actualSpeedsMisc1_dr_6000BRCM_X4 18 14057 #define testshared0_actualSpeedsMisc1_dr_10GHiGig_X4 19 14058 #define testshared0_actualSpeedsMisc1_dr_10GBASE_CX4 20 14059 #define testshared0_actualSpeedsMisc1_dr_12GHiGig_X4 21 14060 #define testshared0_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 14061 #define testshared0_actualSpeedsMisc1_dr_13GHiGig_X4 23 14062 #define testshared0_actualSpeedsMisc1_dr_15GHiGig_X4 24 14063 #define testshared0_actualSpeedsMisc1_dr_16GHiGig_X4 25 14064 #define testshared0_actualSpeedsMisc1_dr_5000BRCM_X1 26 14065 #define testshared0_actualSpeedsMisc1_dr_6363BRCM_X1 27 14066 #define testshared0_actualSpeedsMisc1_dr_20GHiGig_X4 28 14067 #define testshared0_actualSpeedsMisc1_dr_21GHiGig_X4 29 14068 #define testshared0_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 14069 #define testshared0_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 14070 14071 /**************************************************************************** 14072 * Enums: testshared0_IndLaneModes 14073 */ 14074 #define testshared0_IndLaneModes_SWSDR_div2 0 14075 #define testshared0_IndLaneModes_SWSDR_div1 1 14076 #define testshared0_IndLaneModes_DWSDR_div2 2 14077 #define testshared0_IndLaneModes_DWSDR_div1 3 14078 14079 /**************************************************************************** 14080 * Enums: testshared0_prbsSelect 14081 */ 14082 #define testshared0_prbsSelect_prbs7 0 14083 #define testshared0_prbsSelect_prbs15 1 14084 #define testshared0_prbsSelect_prbs23 2 14085 #define testshared0_prbsSelect_prbs31 3 14086 14087 /**************************************************************************** 14088 * Enums: testshared0_vcoDivider 14089 */ 14090 #define testshared0_vcoDivider_div32 0 14091 #define testshared0_vcoDivider_div36 1 14092 #define testshared0_vcoDivider_div40 2 14093 #define testshared0_vcoDivider_div42 3 14094 #define testshared0_vcoDivider_div48 4 14095 #define testshared0_vcoDivider_div50 5 14096 #define testshared0_vcoDivider_div52 6 14097 #define testshared0_vcoDivider_div54 7 14098 #define testshared0_vcoDivider_div60 8 14099 #define testshared0_vcoDivider_div64 9 14100 #define testshared0_vcoDivider_div66 10 14101 #define testshared0_vcoDivider_div68 11 14102 #define testshared0_vcoDivider_div70 12 14103 #define testshared0_vcoDivider_div80 13 14104 #define testshared0_vcoDivider_div92 14 14105 #define testshared0_vcoDivider_div100 15 14106 14107 /**************************************************************************** 14108 * Enums: testshared0_refClkSelect 14109 */ 14110 #define testshared0_refClkSelect_clk_25MHz 0 14111 #define testshared0_refClkSelect_clk_100MHz 1 14112 #define testshared0_refClkSelect_clk_125MHz 2 14113 #define testshared0_refClkSelect_clk_156p25MHz 3 14114 #define testshared0_refClkSelect_clk_187p5MHz 4 14115 #define testshared0_refClkSelect_clk_161p25Mhz 5 14116 #define testshared0_refClkSelect_clk_50Mhz 6 14117 #define testshared0_refClkSelect_clk_106p25Mhz 7 14118 14119 /**************************************************************************** 14120 * Enums: testshared0_aerMMDdevTypeSelect 14121 */ 14122 #define testshared0_aerMMDdevTypeSelect_combo_core 0 14123 #define testshared0_aerMMDdevTypeSelect_PMA_PMD 1 14124 #define testshared0_aerMMDdevTypeSelect_PCS 3 14125 #define testshared0_aerMMDdevTypeSelect_PHY 4 14126 #define testshared0_aerMMDdevTypeSelect_DTE 5 14127 #define testshared0_aerMMDdevTypeSelect_CL73_AN 7 14128 14129 /**************************************************************************** 14130 * Enums: testshared0_aerMMDportSelect 14131 */ 14132 #define testshared0_aerMMDportSelect_ln0 0 14133 #define testshared0_aerMMDportSelect_ln1 1 14134 #define testshared0_aerMMDportSelect_ln2 2 14135 #define testshared0_aerMMDportSelect_ln3 3 14136 #define testshared0_aerMMDportSelect_BCST_ln0_1_2_3 511 14137 #define testshared0_aerMMDportSelect_BCST_ln0_1 512 14138 #define testshared0_aerMMDportSelect_BCST_ln2_3 513 14139 14140 /**************************************************************************** 14141 * Enums: testshared0_firmwareModeSelect 14142 */ 14143 #define testshared0_firmwareModeSelect_DEFAULT 0 14144 #define testshared0_firmwareModeSelect_SFP_OPT_LR 1 14145 #define testshared0_firmwareModeSelect_SFP_DAC 2 14146 #define testshared0_firmwareModeSelect_XLAUI 3 14147 #define testshared0_firmwareModeSelect_LONG_CH_6G 4 14148 14149 /**************************************************************************** 14150 * Enums: testshared0_tempIdxSelect 14151 */ 14152 #define testshared0_tempIdxSelect_LTE__22p9C 15 14153 #define testshared0_tempIdxSelect_LTE__12p6C 14 14154 #define testshared0_tempIdxSelect_LTE__3p0C 13 14155 #define testshared0_tempIdxSelect_LTE_6p7C 12 14156 #define testshared0_tempIdxSelect_LTE_16p4C 11 14157 #define testshared0_tempIdxSelect_LTE_26p6C 10 14158 #define testshared0_tempIdxSelect_LTE_36p3C 9 14159 #define testshared0_tempIdxSelect_LTE_46p0C 8 14160 #define testshared0_tempIdxSelect_LTE_56p2C 7 14161 #define testshared0_tempIdxSelect_LTE_65p9C 6 14162 #define testshared0_tempIdxSelect_LTE_75p6C 5 14163 #define testshared0_tempIdxSelect_LTE_85p3C 4 14164 #define testshared0_tempIdxSelect_LTE_95p5C 3 14165 #define testshared0_tempIdxSelect_LTE_105p2C 2 14166 #define testshared0_tempIdxSelect_LTE_114p9C 1 14167 #define testshared0_tempIdxSelect_LTE_125p1C 0 14168 14169 /**************************************************************************** 14170 * Enums: testshared0_port_mode 14171 */ 14172 #define testshared0_port_mode_QUAD_PORT 0 14173 #define testshared0_port_mode_TRI_1_PORT 1 14174 #define testshared0_port_mode_TRI_2_PORT 2 14175 #define testshared0_port_mode_DUAL_PORT 3 14176 #define testshared0_port_mode_SINGLE_PORT 4 14177 14178 /**************************************************************************** 14179 * Enums: testshared0_rev_letter_enum 14180 */ 14181 #define testshared0_rev_letter_enum_REV_A 0 14182 #define testshared0_rev_letter_enum_REV_B 1 14183 #define testshared0_rev_letter_enum_REV_C 2 14184 #define testshared0_rev_letter_enum_REV_D 3 14185 14186 /**************************************************************************** 14187 * Enums: testshared0_rev_number_enum 14188 */ 14189 #define testshared0_rev_number_enum_REV_0 0 14190 #define testshared0_rev_number_enum_REV_1 1 14191 #define testshared0_rev_number_enum_REV_2 2 14192 #define testshared0_rev_number_enum_REV_3 3 14193 #define testshared0_rev_number_enum_REV_4 4 14194 #define testshared0_rev_number_enum_REV_5 5 14195 #define testshared0_rev_number_enum_REV_6 6 14196 #define testshared0_rev_number_enum_REV_7 7 14197 14198 /**************************************************************************** 14199 * Enums: testshared0_bonding_enum 14200 */ 14201 #define testshared0_bonding_enum_WIRE_BOND 0 14202 #define testshared0_bonding_enum_FLIP_CHIP 1 14203 14204 /**************************************************************************** 14205 * Enums: testshared0_tech_process 14206 */ 14207 #define testshared0_tech_process_PROCESS_90NM 0 14208 #define testshared0_tech_process_PROCESS_65NM 1 14209 #define testshared0_tech_process_PROCESS_40NM 2 14210 #define testshared0_tech_process_PROCESS_28NM 3 14211 14212 /**************************************************************************** 14213 * Enums: testshared0_model_num 14214 */ 14215 #define testshared0_model_num_SERDES_CL73 0 14216 #define testshared0_model_num_XGXS_16G 1 14217 #define testshared0_model_num_HYPERCORE 2 14218 #define testshared0_model_num_HYPERLITE 3 14219 #define testshared0_model_num_PCIE_G2_PIPE 4 14220 #define testshared0_model_num_SERDES_1p25GBd 5 14221 #define testshared0_model_num_SATA2 6 14222 #define testshared0_model_num_QSGMII 7 14223 #define testshared0_model_num_XGXS10G 8 14224 #define testshared0_model_num_WARPCORE 9 14225 #define testshared0_model_num_XFICORE 10 14226 #define testshared0_model_num_RXFI 11 14227 #define testshared0_model_num_WARPLITE 12 14228 #define testshared0_model_num_PENTACORE 13 14229 #define testshared0_model_num_ESM 14 14230 #define testshared0_model_num_QUAD_SGMII 15 14231 #define testshared0_model_num_WARPCORE_3 16 14232 #define testshared0_model_num_TSC 17 14233 #define testshared0_model_num_TSC4E 18 14234 #define testshared0_model_num_TSC12E 19 14235 #define testshared0_model_num_TSC4F 20 14236 #define testshared0_model_num_XGXS_CL73_90NM 29 14237 #define testshared0_model_num_SERDES_CL73_90NM 30 14238 #define testshared0_model_num_WARPCORE3 32 14239 #define testshared0_model_num_WARPCORE4_TSC 33 14240 #define testshared0_model_num_RXAUI 34 14241 14242 /**************************************************************************** 14243 * Enums: testshared0_payload 14244 */ 14245 #define testshared0_payload_REPEAT_2_BYTES 0 14246 #define testshared0_payload_RAMPING 1 14247 #define testshared0_payload_CL48_CRPAT 2 14248 #define testshared0_payload_CL48_CJPAT 3 14249 #define testshared0_payload_CL36_LONG_CRPAT 4 14250 #define testshared0_payload_CL36_SHORT_CRPAT 5 14251 14252 /**************************************************************************** 14253 * Enums: testshared0_sc 14254 */ 14255 #define testshared0_sc_S_10G_CR1 0 14256 #define testshared0_sc_S_10G_KR1 1 14257 #define testshared0_sc_S_10G_X1 2 14258 #define testshared0_sc_S_10G_HG2_CR1 4 14259 #define testshared0_sc_S_10G_HG2_KR1 5 14260 #define testshared0_sc_S_10G_HG2_X1 6 14261 #define testshared0_sc_S_20G_CR1 8 14262 #define testshared0_sc_S_20G_KR1 9 14263 #define testshared0_sc_S_20G_X1 10 14264 #define testshared0_sc_S_20G_HG2_CR1 12 14265 #define testshared0_sc_S_20G_HG2_KR1 13 14266 #define testshared0_sc_S_20G_HG2_X1 14 14267 #define testshared0_sc_S_25G_CR1 16 14268 #define testshared0_sc_S_25G_KR1 17 14269 #define testshared0_sc_S_25G_X1 18 14270 #define testshared0_sc_S_25G_HG2_CR1 20 14271 #define testshared0_sc_S_25G_HG2_KR1 21 14272 #define testshared0_sc_S_25G_HG2_X1 22 14273 #define testshared0_sc_S_20G_CR2 24 14274 #define testshared0_sc_S_20G_KR2 25 14275 #define testshared0_sc_S_20G_X2 26 14276 #define testshared0_sc_S_20G_HG2_CR2 28 14277 #define testshared0_sc_S_20G_HG2_KR2 29 14278 #define testshared0_sc_S_20G_HG2_X2 30 14279 #define testshared0_sc_S_40G_CR2 32 14280 #define testshared0_sc_S_40G_KR2 33 14281 #define testshared0_sc_S_40G_X2 34 14282 #define testshared0_sc_S_40G_HG2_CR2 36 14283 #define testshared0_sc_S_40G_HG2_KR2 37 14284 #define testshared0_sc_S_40G_HG2_X2 38 14285 #define testshared0_sc_S_40G_CR4 40 14286 #define testshared0_sc_S_40G_KR4 41 14287 #define testshared0_sc_S_40G_X4 42 14288 #define testshared0_sc_S_40G_HG2_CR4 44 14289 #define testshared0_sc_S_40G_HG2_KR4 45 14290 #define testshared0_sc_S_40G_HG2_X4 46 14291 #define testshared0_sc_S_50G_CR2 48 14292 #define testshared0_sc_S_50G_KR2 49 14293 #define testshared0_sc_S_50G_X2 50 14294 #define testshared0_sc_S_50G_HG2_CR2 52 14295 #define testshared0_sc_S_50G_HG2_KR2 53 14296 #define testshared0_sc_S_50G_HG2_X2 54 14297 #define testshared0_sc_S_50G_CR4 56 14298 #define testshared0_sc_S_50G_KR4 57 14299 #define testshared0_sc_S_50G_X4 58 14300 #define testshared0_sc_S_50G_HG2_CR4 60 14301 #define testshared0_sc_S_50G_HG2_KR4 61 14302 #define testshared0_sc_S_50G_HG2_X4 62 14303 #define testshared0_sc_S_100G_CR4 64 14304 #define testshared0_sc_S_100G_KR4 65 14305 #define testshared0_sc_S_100G_X4 66 14306 #define testshared0_sc_S_100G_HG2_CR4 68 14307 #define testshared0_sc_S_100G_HG2_KR4 69 14308 #define testshared0_sc_S_100G_HG2_X4 70 14309 #define testshared0_sc_S_CL73_20GVCO 72 14310 #define testshared0_sc_S_CL73_25GVCO 80 14311 #define testshared0_sc_S_CL36_20GVCO 88 14312 #define testshared0_sc_S_CL36_25GVCO 96 14313 14314 /**************************************************************************** 14315 * Enums: testshared0_t_fifo_modes 14316 */ 14317 #define testshared0_t_fifo_modes_T_FIFO_MODE_BYPASS 0 14318 #define testshared0_t_fifo_modes_T_FIFO_MODE_40G 1 14319 #define testshared0_t_fifo_modes_T_FIFO_MODE_100G 2 14320 #define testshared0_t_fifo_modes_T_FIFO_MODE_20G 3 14321 14322 /**************************************************************************** 14323 * Enums: testshared0_t_enc_modes 14324 */ 14325 #define testshared0_t_enc_modes_T_ENC_MODE_BYPASS 0 14326 #define testshared0_t_enc_modes_T_ENC_MODE_CL49 1 14327 #define testshared0_t_enc_modes_T_ENC_MODE_CL82 2 14328 14329 /**************************************************************************** 14330 * Enums: testshared0_btmx_mode 14331 */ 14332 #define testshared0_btmx_mode_BS_BTMX_MODE_1to1 0 14333 #define testshared0_btmx_mode_BS_BTMX_MODE_2to1 1 14334 #define testshared0_btmx_mode_BS_BTMX_MODE_5to1 2 14335 14336 /**************************************************************************** 14337 * Enums: testshared0_t_type_cl82 14338 */ 14339 #define testshared0_t_type_cl82_T_TYPE_B1 5 14340 #define testshared0_t_type_cl82_T_TYPE_C 4 14341 #define testshared0_t_type_cl82_T_TYPE_S 3 14342 #define testshared0_t_type_cl82_T_TYPE_T 2 14343 #define testshared0_t_type_cl82_T_TYPE_D 1 14344 #define testshared0_t_type_cl82_T_TYPE_E 0 14345 14346 /**************************************************************************** 14347 * Enums: testshared0_txsm_state_cl82 14348 */ 14349 #define testshared0_txsm_state_cl82_TX_HIG_END 6 14350 #define testshared0_txsm_state_cl82_TX_HIG_START 5 14351 #define testshared0_txsm_state_cl82_TX_E 4 14352 #define testshared0_txsm_state_cl82_TX_T 3 14353 #define testshared0_txsm_state_cl82_TX_D 2 14354 #define testshared0_txsm_state_cl82_TX_C 1 14355 #define testshared0_txsm_state_cl82_TX_INIT 0 14356 14357 /**************************************************************************** 14358 * Enums: testshared0_ltxsm_state_cl82 14359 */ 14360 #define testshared0_ltxsm_state_cl82_TX_HIG_END 64 14361 #define testshared0_ltxsm_state_cl82_TX_HIG_START 32 14362 #define testshared0_ltxsm_state_cl82_TX_E 16 14363 #define testshared0_ltxsm_state_cl82_TX_T 8 14364 #define testshared0_ltxsm_state_cl82_TX_D 4 14365 #define testshared0_ltxsm_state_cl82_TX_C 2 14366 #define testshared0_ltxsm_state_cl82_TX_INIT 1 14367 14368 /**************************************************************************** 14369 * Enums: testshared0_r_type_coded_cl82 14370 */ 14371 #define testshared0_r_type_coded_cl82_R_TYPE_B1 32 14372 #define testshared0_r_type_coded_cl82_R_TYPE_C 16 14373 #define testshared0_r_type_coded_cl82_R_TYPE_S 8 14374 #define testshared0_r_type_coded_cl82_R_TYPE_T 4 14375 #define testshared0_r_type_coded_cl82_R_TYPE_D 2 14376 #define testshared0_r_type_coded_cl82_R_TYPE_E 1 14377 14378 /**************************************************************************** 14379 * Enums: testshared0_rxsm_state_cl82 14380 */ 14381 #define testshared0_rxsm_state_cl82_RX_HIG_END 64 14382 #define testshared0_rxsm_state_cl82_RX_HIG_START 32 14383 #define testshared0_rxsm_state_cl82_RX_E 16 14384 #define testshared0_rxsm_state_cl82_RX_T 8 14385 #define testshared0_rxsm_state_cl82_RX_D 4 14386 #define testshared0_rxsm_state_cl82_RX_C 2 14387 #define testshared0_rxsm_state_cl82_RX_INIT 1 14388 14389 /**************************************************************************** 14390 * Enums: testshared0_deskew_state 14391 */ 14392 #define testshared0_deskew_state_ALIGN_ACQUIRED 2 14393 #define testshared0_deskew_state_LOSS_OF_ALIGNMENT 1 14394 14395 /**************************************************************************** 14396 * Enums: testshared0_os_mode_enum 14397 */ 14398 #define testshared0_os_mode_enum_OS_MODE_1 0 14399 #define testshared0_os_mode_enum_OS_MODE_2 1 14400 #define testshared0_os_mode_enum_OS_MODE_4 2 14401 #define testshared0_os_mode_enum_OS_MODE_16p5 8 14402 #define testshared0_os_mode_enum_OS_MODE_20p625 12 14403 14404 /**************************************************************************** 14405 * Enums: testshared0_scr_modes 14406 */ 14407 #define testshared0_scr_modes_T_SCR_MODE_BYPASS 0 14408 #define testshared0_scr_modes_T_SCR_MODE_CL49 1 14409 #define testshared0_scr_modes_T_SCR_MODE_40G_2_LANE 2 14410 #define testshared0_scr_modes_T_SCR_MODE_100G 3 14411 #define testshared0_scr_modes_T_SCR_MODE_20G 4 14412 #define testshared0_scr_modes_T_SCR_MODE_40G_4_LANE 5 14413 14414 /**************************************************************************** 14415 * Enums: testshared0_descr_modes 14416 */ 14417 #define testshared0_descr_modes_R_DESCR_MODE_BYPASS 0 14418 #define testshared0_descr_modes_R_DESCR_MODE_CL49 1 14419 #define testshared0_descr_modes_R_DESCR_MODE_CL82 2 14420 14421 /**************************************************************************** 14422 * Enums: testshared0_r_dec_tl_mode 14423 */ 14424 #define testshared0_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 14425 #define testshared0_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 14426 #define testshared0_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 14427 14428 /**************************************************************************** 14429 * Enums: testshared0_r_dec_fsm_mode 14430 */ 14431 #define testshared0_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 14432 #define testshared0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 14433 #define testshared0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 14434 14435 /**************************************************************************** 14436 * Enums: testshared0_r_deskew_mode 14437 */ 14438 #define testshared0_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 14439 #define testshared0_r_deskew_mode_R_DESKEW_MODE_20G 1 14440 #define testshared0_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 14441 #define testshared0_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 14442 #define testshared0_r_deskew_mode_R_DESKEW_MODE_100G 4 14443 #define testshared0_r_deskew_mode_R_DESKEW_MODE_CL49 5 14444 #define testshared0_r_deskew_mode_R_DESKEW_MODE_CL91 6 14445 14446 /**************************************************************************** 14447 * Enums: testshared0_bs_dist_modes 14448 */ 14449 #define testshared0_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 14450 #define testshared0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 14451 #define testshared0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 14452 #define testshared0_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 14453 14454 /**************************************************************************** 14455 * Enums: testshared0_cl49_t_type 14456 */ 14457 #define testshared0_cl49_t_type_BAD_T_TYPE 15 14458 #define testshared0_cl49_t_type_T_TYPE_B0 11 14459 #define testshared0_cl49_t_type_T_TYPE_OB 10 14460 #define testshared0_cl49_t_type_T_TYPE_B1 9 14461 #define testshared0_cl49_t_type_T_TYPE_DB 8 14462 #define testshared0_cl49_t_type_T_TYPE_FC 7 14463 #define testshared0_cl49_t_type_T_TYPE_TB 6 14464 #define testshared0_cl49_t_type_T_TYPE_LI 5 14465 #define testshared0_cl49_t_type_T_TYPE_C 4 14466 #define testshared0_cl49_t_type_T_TYPE_S 3 14467 #define testshared0_cl49_t_type_T_TYPE_T 2 14468 #define testshared0_cl49_t_type_T_TYPE_D 1 14469 #define testshared0_cl49_t_type_T_TYPE_E 0 14470 14471 /**************************************************************************** 14472 * Enums: testshared0_cl49_txsm_states 14473 */ 14474 #define testshared0_cl49_txsm_states_TX_HIG_END 7 14475 #define testshared0_cl49_txsm_states_TX_HIG_START 6 14476 #define testshared0_cl49_txsm_states_TX_LI 5 14477 #define testshared0_cl49_txsm_states_TX_E 4 14478 #define testshared0_cl49_txsm_states_TX_T 3 14479 #define testshared0_cl49_txsm_states_TX_D 2 14480 #define testshared0_cl49_txsm_states_TX_C 1 14481 #define testshared0_cl49_txsm_states_TX_INIT 0 14482 14483 /**************************************************************************** 14484 * Enums: testshared0_cl49_ltxsm_states 14485 */ 14486 #define testshared0_cl49_ltxsm_states_TX_HIG_END 128 14487 #define testshared0_cl49_ltxsm_states_TX_HIG_START 64 14488 #define testshared0_cl49_ltxsm_states_TX_LI 32 14489 #define testshared0_cl49_ltxsm_states_TX_E 16 14490 #define testshared0_cl49_ltxsm_states_TX_T 8 14491 #define testshared0_cl49_ltxsm_states_TX_D 4 14492 #define testshared0_cl49_ltxsm_states_TX_C 2 14493 #define testshared0_cl49_ltxsm_states_TX_INIT 1 14494 14495 /**************************************************************************** 14496 * Enums: testshared0_burst_error_mode 14497 */ 14498 #define testshared0_burst_error_mode_BURST_ERROR_11_BITS 0 14499 #define testshared0_burst_error_mode_BURST_ERROR_16_BITS 1 14500 #define testshared0_burst_error_mode_BURST_ERROR_17_BITS 2 14501 #define testshared0_burst_error_mode_BURST_ERROR_18_BITS 3 14502 #define testshared0_burst_error_mode_BURST_ERROR_19_BITS 4 14503 #define testshared0_burst_error_mode_BURST_ERROR_20_BITS 5 14504 #define testshared0_burst_error_mode_BURST_ERROR_21_BITS 6 14505 #define testshared0_burst_error_mode_BURST_ERROR_22_BITS 7 14506 #define testshared0_burst_error_mode_BURST_ERROR_23_BITS 8 14507 #define testshared0_burst_error_mode_BURST_ERROR_24_BITS 9 14508 #define testshared0_burst_error_mode_BURST_ERROR_25_BITS 10 14509 #define testshared0_burst_error_mode_BURST_ERROR_26_BITS 11 14510 #define testshared0_burst_error_mode_BURST_ERROR_27_BITS 12 14511 #define testshared0_burst_error_mode_BURST_ERROR_28_BITS 13 14512 #define testshared0_burst_error_mode_BURST_ERROR_29_BITS 14 14513 #define testshared0_burst_error_mode_BURST_ERROR_30_BITS 15 14514 #define testshared0_burst_error_mode_BURST_ERROR_31_BITS 16 14515 #define testshared0_burst_error_mode_BURST_ERROR_32_BITS 17 14516 #define testshared0_burst_error_mode_BURST_ERROR_33_BITS 18 14517 #define testshared0_burst_error_mode_BURST_ERROR_34_BITS 19 14518 #define testshared0_burst_error_mode_BURST_ERROR_35_BITS 20 14519 #define testshared0_burst_error_mode_BURST_ERROR_36_BITS 21 14520 #define testshared0_burst_error_mode_BURST_ERROR_37_BITS 22 14521 #define testshared0_burst_error_mode_BURST_ERROR_38_BITS 23 14522 #define testshared0_burst_error_mode_BURST_ERROR_39_BITS 24 14523 #define testshared0_burst_error_mode_BURST_ERROR_40_BITS 25 14524 #define testshared0_burst_error_mode_BURST_ERROR_41_BITS 26 14525 14526 /**************************************************************************** 14527 * Enums: testshared0_bermon_state 14528 */ 14529 #define testshared0_bermon_state_HI_BER 4 14530 #define testshared0_bermon_state_GOOD_BER 3 14531 #define testshared0_bermon_state_BER_TEST_SH 2 14532 #define testshared0_bermon_state_START_TIMER 1 14533 #define testshared0_bermon_state_BER_MT_INIT 0 14534 14535 /**************************************************************************** 14536 * Enums: testshared0_rxsm_state_cl49 14537 */ 14538 #define testshared0_rxsm_state_cl49_RX_HIG_END 128 14539 #define testshared0_rxsm_state_cl49_RX_HIG_START 64 14540 #define testshared0_rxsm_state_cl49_RX_LI 32 14541 #define testshared0_rxsm_state_cl49_RX_E 16 14542 #define testshared0_rxsm_state_cl49_RX_T 8 14543 #define testshared0_rxsm_state_cl49_RX_D 4 14544 #define testshared0_rxsm_state_cl49_RX_C 2 14545 #define testshared0_rxsm_state_cl49_RX_INIT 1 14546 14547 /**************************************************************************** 14548 * Enums: testshared0_r_type 14549 */ 14550 #define testshared0_r_type_BAD_R_TYPE 15 14551 #define testshared0_r_type_R_TYPE_B0 11 14552 #define testshared0_r_type_R_TYPE_OB 10 14553 #define testshared0_r_type_R_TYPE_B1 9 14554 #define testshared0_r_type_R_TYPE_DB 8 14555 #define testshared0_r_type_R_TYPE_FC 7 14556 #define testshared0_r_type_R_TYPE_TB 6 14557 #define testshared0_r_type_R_TYPE_LI 5 14558 #define testshared0_r_type_R_TYPE_C 4 14559 #define testshared0_r_type_R_TYPE_S 3 14560 #define testshared0_r_type_R_TYPE_T 2 14561 #define testshared0_r_type_R_TYPE_D 1 14562 #define testshared0_r_type_R_TYPE_E 0 14563 14564 /**************************************************************************** 14565 * Enums: testshared0_am_lock_state 14566 */ 14567 #define testshared0_am_lock_state_INVALID_AM 512 14568 #define testshared0_am_lock_state_GOOD_AM 256 14569 #define testshared0_am_lock_state_COMP_AM 128 14570 #define testshared0_am_lock_state_TIMER_2 64 14571 #define testshared0_am_lock_state_AM_2_GOOD 32 14572 #define testshared0_am_lock_state_COMP_2ND 16 14573 #define testshared0_am_lock_state_TIMER_1 8 14574 #define testshared0_am_lock_state_FIND_1ST 4 14575 #define testshared0_am_lock_state_AM_RESET_CNT 2 14576 #define testshared0_am_lock_state_AM_LOCK_INIT 1 14577 14578 /**************************************************************************** 14579 * Enums: testshared0_msg_selector 14580 */ 14581 #define testshared0_msg_selector_RESERVED 0 14582 #define testshared0_msg_selector_VALUE_802p3 1 14583 #define testshared0_msg_selector_VALUE_802p9 2 14584 #define testshared0_msg_selector_VALUE_802p5 3 14585 #define testshared0_msg_selector_VALUE_1394 4 14586 14587 /**************************************************************************** 14588 * Enums: testshared0_synce_enum 14589 */ 14590 #define testshared0_synce_enum_SYNCE_NO_DIV 0 14591 #define testshared0_synce_enum_SYNCE_DIV_7 1 14592 #define testshared0_synce_enum_SYNCE_DIV_11 2 14593 14594 /**************************************************************************** 14595 * Enums: testshared0_synce_enum_stage0 14596 */ 14597 #define testshared0_synce_enum_stage0_SYNCE_NO_DIV 0 14598 #define testshared0_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 14599 #define testshared0_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 14600 14601 /**************************************************************************** 14602 * Enums: testshared0_cl91_sync_state 14603 */ 14604 #define testshared0_cl91_sync_state_FIND_1ST 0 14605 #define testshared0_cl91_sync_state_COUNT_NEXT 1 14606 #define testshared0_cl91_sync_state_COMP_2ND 2 14607 #define testshared0_cl91_sync_state_TWO_GOOD 3 14608 14609 /**************************************************************************** 14610 * Enums: testshared0_cl91_algn_state 14611 */ 14612 #define testshared0_cl91_algn_state_LOSS_OF_ALIGNMENT 0 14613 #define testshared0_cl91_algn_state_DESKEW 1 14614 #define testshared0_cl91_algn_state_DESKEW_FAIL 2 14615 #define testshared0_cl91_algn_state_ALIGN_ACQUIRED 3 14616 #define testshared0_cl91_algn_state_CW_GOOD 4 14617 #define testshared0_cl91_algn_state_CW_BAD 5 14618 #define testshared0_cl91_algn_state_THREE_BAD 6 14619 14620 /**************************************************************************** 14621 * Enums: testshared0_fec_sel 14622 */ 14623 #define testshared0_fec_sel_NO_FEC 0 14624 #define testshared0_fec_sel_FEC_CL74 1 14625 #define testshared0_fec_sel_FEC_CL91 2 14626 14627 /**************************************************************************** 14628 * Enums: tx_x2_control0_cl36TxEEEStates_l 14629 */ 14630 #define tx_x2_control0_cl36TxEEEStates_l_TX_REFRESH 8 14631 #define tx_x2_control0_cl36TxEEEStates_l_TX_QUIET 4 14632 #define tx_x2_control0_cl36TxEEEStates_l_TX_SLEEP 2 14633 #define tx_x2_control0_cl36TxEEEStates_l_TX_ACTIVE 1 14634 14635 /**************************************************************************** 14636 * Enums: tx_x2_control0_cl36TxEEEStates_c 14637 */ 14638 #define tx_x2_control0_cl36TxEEEStates_c_TX_REFRESH 3 14639 #define tx_x2_control0_cl36TxEEEStates_c_TX_QUIET 2 14640 #define tx_x2_control0_cl36TxEEEStates_c_TX_SLEEP 1 14641 #define tx_x2_control0_cl36TxEEEStates_c_TX_ACTIVE 0 14642 14643 /**************************************************************************** 14644 * Enums: tx_x2_control0_cl49TxEEEStates_l 14645 */ 14646 #define tx_x2_control0_cl49TxEEEStates_l_SCR_RESET_2 64 14647 #define tx_x2_control0_cl49TxEEEStates_l_SCR_RESET_1 32 14648 #define tx_x2_control0_cl49TxEEEStates_l_TX_WAKE 16 14649 #define tx_x2_control0_cl49TxEEEStates_l_TX_REFRESH 8 14650 #define tx_x2_control0_cl49TxEEEStates_l_TX_QUIET 4 14651 #define tx_x2_control0_cl49TxEEEStates_l_TX_SLEEP 2 14652 #define tx_x2_control0_cl49TxEEEStates_l_TX_ACTIVE 1 14653 14654 /**************************************************************************** 14655 * Enums: tx_x2_control0_fec_req_enum 14656 */ 14657 #define tx_x2_control0_fec_req_enum_FEC_not_supported 0 14658 #define tx_x2_control0_fec_req_enum_FEC_supported_but_not_requested 1 14659 #define tx_x2_control0_fec_req_enum_invalid_setting 2 14660 #define tx_x2_control0_fec_req_enum_FEC_supported_and_requested 3 14661 14662 /**************************************************************************** 14663 * Enums: tx_x2_control0_cl73_pause_enum 14664 */ 14665 #define tx_x2_control0_cl73_pause_enum_No_PAUSE_ability 0 14666 #define tx_x2_control0_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 14667 #define tx_x2_control0_cl73_pause_enum_Symmetric_PAUSE_ability 1 14668 #define tx_x2_control0_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 14669 14670 /**************************************************************************** 14671 * Enums: tx_x2_control0_cl49TxEEEStates_c 14672 */ 14673 #define tx_x2_control0_cl49TxEEEStates_c_SCR_RESET_2 6 14674 #define tx_x2_control0_cl49TxEEEStates_c_SCR_RESET_1 5 14675 #define tx_x2_control0_cl49TxEEEStates_c_TX_WAKE 4 14676 #define tx_x2_control0_cl49TxEEEStates_c_TX_REFRESH 3 14677 #define tx_x2_control0_cl49TxEEEStates_c_TX_QUIET 2 14678 #define tx_x2_control0_cl49TxEEEStates_c_TX_SLEEP 1 14679 #define tx_x2_control0_cl49TxEEEStates_c_TX_ACTIVE 0 14680 14681 /**************************************************************************** 14682 * Enums: tx_x2_control0_cl36RxEEEStates_l 14683 */ 14684 #define tx_x2_control0_cl36RxEEEStates_l_RX_LINK_FAIL 32 14685 #define tx_x2_control0_cl36RxEEEStates_l_RX_WTF 16 14686 #define tx_x2_control0_cl36RxEEEStates_l_RX_WAKE 8 14687 #define tx_x2_control0_cl36RxEEEStates_l_RX_QUIET 4 14688 #define tx_x2_control0_cl36RxEEEStates_l_RX_SLEEP 2 14689 #define tx_x2_control0_cl36RxEEEStates_l_RX_ACTIVE 1 14690 14691 /**************************************************************************** 14692 * Enums: tx_x2_control0_cl36RxEEEStates_c 14693 */ 14694 #define tx_x2_control0_cl36RxEEEStates_c_RX_LINK_FAIL 5 14695 #define tx_x2_control0_cl36RxEEEStates_c_RX_WTF 4 14696 #define tx_x2_control0_cl36RxEEEStates_c_RX_WAKE 3 14697 #define tx_x2_control0_cl36RxEEEStates_c_RX_QUIET 2 14698 #define tx_x2_control0_cl36RxEEEStates_c_RX_SLEEP 1 14699 #define tx_x2_control0_cl36RxEEEStates_c_RX_ACTIVE 0 14700 14701 /**************************************************************************** 14702 * Enums: tx_x2_control0_cl49RxEEEStates_l 14703 */ 14704 #define tx_x2_control0_cl49RxEEEStates_l_RX_LINK_FAIL 32 14705 #define tx_x2_control0_cl49RxEEEStates_l_RX_WTF 16 14706 #define tx_x2_control0_cl49RxEEEStates_l_RX_WAKE 8 14707 #define tx_x2_control0_cl49RxEEEStates_l_RX_QUIET 4 14708 #define tx_x2_control0_cl49RxEEEStates_l_RX_SLEEP 2 14709 #define tx_x2_control0_cl49RxEEEStates_l_RX_ACTIVE 1 14710 14711 /**************************************************************************** 14712 * Enums: tx_x2_control0_cl49RxEEEStates_c 14713 */ 14714 #define tx_x2_control0_cl49RxEEEStates_c_RX_LINK_FAIL 5 14715 #define tx_x2_control0_cl49RxEEEStates_c_RX_WTF 4 14716 #define tx_x2_control0_cl49RxEEEStates_c_RX_WAKE 3 14717 #define tx_x2_control0_cl49RxEEEStates_c_RX_QUIET 2 14718 #define tx_x2_control0_cl49RxEEEStates_c_RX_SLEEP 1 14719 #define tx_x2_control0_cl49RxEEEStates_c_RX_ACTIVE 0 14720 14721 /**************************************************************************** 14722 * Enums: tx_x2_control0_cl48TxEEEStates_l 14723 */ 14724 #define tx_x2_control0_cl48TxEEEStates_l_TX_REFRESH 8 14725 #define tx_x2_control0_cl48TxEEEStates_l_TX_QUIET 4 14726 #define tx_x2_control0_cl48TxEEEStates_l_TX_SLEEP 2 14727 #define tx_x2_control0_cl48TxEEEStates_l_TX_ACTIVE 1 14728 14729 /**************************************************************************** 14730 * Enums: tx_x2_control0_cl48TxEEEStates_c 14731 */ 14732 #define tx_x2_control0_cl48TxEEEStates_c_TX_REFRESH 3 14733 #define tx_x2_control0_cl48TxEEEStates_c_TX_QUIET 2 14734 #define tx_x2_control0_cl48TxEEEStates_c_TX_SLEEP 1 14735 #define tx_x2_control0_cl48TxEEEStates_c_TX_ACTIVE 0 14736 14737 /**************************************************************************** 14738 * Enums: tx_x2_control0_cl48RxEEEStates_l 14739 */ 14740 #define tx_x2_control0_cl48RxEEEStates_l_RX_LINK_FAIL 32 14741 #define tx_x2_control0_cl48RxEEEStates_l_RX_WAKE 16 14742 #define tx_x2_control0_cl48RxEEEStates_l_RX_QUIET 8 14743 #define tx_x2_control0_cl48RxEEEStates_l_RX_DEACT 4 14744 #define tx_x2_control0_cl48RxEEEStates_l_RX_SLEEP 2 14745 #define tx_x2_control0_cl48RxEEEStates_l_RX_ACTIVE 1 14746 14747 /**************************************************************************** 14748 * Enums: tx_x2_control0_cl48RxEEEStates_c 14749 */ 14750 #define tx_x2_control0_cl48RxEEEStates_c_RX_LINK_FAIL 5 14751 #define tx_x2_control0_cl48RxEEEStates_c_RX_WAKE 4 14752 #define tx_x2_control0_cl48RxEEEStates_c_RX_QUIET 3 14753 #define tx_x2_control0_cl48RxEEEStates_c_RX_DEACT 2 14754 #define tx_x2_control0_cl48RxEEEStates_c_RX_SLEEP 1 14755 #define tx_x2_control0_cl48RxEEEStates_c_RX_ACTIVE 0 14756 14757 /**************************************************************************** 14758 * Enums: tx_x2_control0_IQP_Options 14759 */ 14760 #define tx_x2_control0_IQP_Options_i50uA 0 14761 #define tx_x2_control0_IQP_Options_i100uA 1 14762 #define tx_x2_control0_IQP_Options_i150uA 2 14763 #define tx_x2_control0_IQP_Options_i200uA 3 14764 #define tx_x2_control0_IQP_Options_i250uA 4 14765 #define tx_x2_control0_IQP_Options_i300uA 5 14766 #define tx_x2_control0_IQP_Options_i350uA 6 14767 #define tx_x2_control0_IQP_Options_i400uA 7 14768 #define tx_x2_control0_IQP_Options_i450uA 8 14769 #define tx_x2_control0_IQP_Options_i500uA 9 14770 #define tx_x2_control0_IQP_Options_i550uA 10 14771 #define tx_x2_control0_IQP_Options_i600uA 11 14772 #define tx_x2_control0_IQP_Options_i650uA 12 14773 #define tx_x2_control0_IQP_Options_i700uA 13 14774 #define tx_x2_control0_IQP_Options_i750uA 14 14775 #define tx_x2_control0_IQP_Options_i800uA 15 14776 14777 /**************************************************************************** 14778 * Enums: tx_x2_control0_IDriver_Options 14779 */ 14780 #define tx_x2_control0_IDriver_Options_v680mV 0 14781 #define tx_x2_control0_IDriver_Options_v730mV 1 14782 #define tx_x2_control0_IDriver_Options_v780mV 2 14783 #define tx_x2_control0_IDriver_Options_v830mV 3 14784 #define tx_x2_control0_IDriver_Options_v880mV 4 14785 #define tx_x2_control0_IDriver_Options_v930mV 5 14786 #define tx_x2_control0_IDriver_Options_v980mV 6 14787 #define tx_x2_control0_IDriver_Options_v1010mV 7 14788 #define tx_x2_control0_IDriver_Options_v1040mV 8 14789 #define tx_x2_control0_IDriver_Options_v1060mV 9 14790 #define tx_x2_control0_IDriver_Options_v1070mV 10 14791 #define tx_x2_control0_IDriver_Options_v1080mV 11 14792 #define tx_x2_control0_IDriver_Options_v1085mV 12 14793 #define tx_x2_control0_IDriver_Options_v1090mV 13 14794 #define tx_x2_control0_IDriver_Options_v1095mV 14 14795 #define tx_x2_control0_IDriver_Options_v1100mV 15 14796 14797 /**************************************************************************** 14798 * Enums: tx_x2_control0_operationModes 14799 */ 14800 #define tx_x2_control0_operationModes_XGXS 0 14801 #define tx_x2_control0_operationModes_XGXG_nCC 1 14802 #define tx_x2_control0_operationModes_Indlane_OS8 4 14803 #define tx_x2_control0_operationModes_IndLane_OS5 5 14804 #define tx_x2_control0_operationModes_PCI 7 14805 #define tx_x2_control0_operationModes_XGXS_nLQ 8 14806 #define tx_x2_control0_operationModes_XGXS_nLQnCC 9 14807 #define tx_x2_control0_operationModes_PBypass 10 14808 #define tx_x2_control0_operationModes_PBypass_nDSK 11 14809 #define tx_x2_control0_operationModes_ComboCoreMode 12 14810 #define tx_x2_control0_operationModes_Clocks_off 15 14811 14812 /**************************************************************************** 14813 * Enums: tx_x2_control0_actualSpeeds 14814 */ 14815 #define tx_x2_control0_actualSpeeds_dr_10M 0 14816 #define tx_x2_control0_actualSpeeds_dr_100M 1 14817 #define tx_x2_control0_actualSpeeds_dr_1G 2 14818 #define tx_x2_control0_actualSpeeds_dr_2p5G 3 14819 #define tx_x2_control0_actualSpeeds_dr_5G_X4 4 14820 #define tx_x2_control0_actualSpeeds_dr_6G_X4 5 14821 #define tx_x2_control0_actualSpeeds_dr_10G_HiG 6 14822 #define tx_x2_control0_actualSpeeds_dr_10G_CX4 7 14823 #define tx_x2_control0_actualSpeeds_dr_12G_HiG 8 14824 #define tx_x2_control0_actualSpeeds_dr_12p5G_X4 9 14825 #define tx_x2_control0_actualSpeeds_dr_13G_X4 10 14826 #define tx_x2_control0_actualSpeeds_dr_15G_X4 11 14827 #define tx_x2_control0_actualSpeeds_dr_16G_X4 12 14828 #define tx_x2_control0_actualSpeeds_dr_1G_KX 13 14829 #define tx_x2_control0_actualSpeeds_dr_10G_KX4 14 14830 #define tx_x2_control0_actualSpeeds_dr_10G_KR 15 14831 #define tx_x2_control0_actualSpeeds_dr_5G 16 14832 #define tx_x2_control0_actualSpeeds_dr_6p4G 17 14833 #define tx_x2_control0_actualSpeeds_dr_20G_X4 18 14834 #define tx_x2_control0_actualSpeeds_dr_21G_X4 19 14835 #define tx_x2_control0_actualSpeeds_dr_25G_X4 20 14836 #define tx_x2_control0_actualSpeeds_dr_10G_HiG_DXGXS 21 14837 #define tx_x2_control0_actualSpeeds_dr_10G_DXGXS 22 14838 #define tx_x2_control0_actualSpeeds_dr_10p5G_HiG_DXGXS 23 14839 #define tx_x2_control0_actualSpeeds_dr_10p5G_DXGXS 24 14840 #define tx_x2_control0_actualSpeeds_dr_12p773G_HiG_DXGXS 25 14841 #define tx_x2_control0_actualSpeeds_dr_12p773G_DXGXS 26 14842 #define tx_x2_control0_actualSpeeds_dr_10G_XFI 27 14843 #define tx_x2_control0_actualSpeeds_dr_40G 28 14844 #define tx_x2_control0_actualSpeeds_dr_20G_HiG_DXGXS 29 14845 #define tx_x2_control0_actualSpeeds_dr_20G_DXGXS 30 14846 #define tx_x2_control0_actualSpeeds_dr_10G_SFI 31 14847 #define tx_x2_control0_actualSpeeds_dr_31p5G 32 14848 #define tx_x2_control0_actualSpeeds_dr_32p7G 33 14849 #define tx_x2_control0_actualSpeeds_dr_20G_SCR 34 14850 #define tx_x2_control0_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 14851 #define tx_x2_control0_actualSpeeds_dr_10G_DXGXS_SCR 36 14852 #define tx_x2_control0_actualSpeeds_dr_12G_R2 37 14853 #define tx_x2_control0_actualSpeeds_dr_10G_X2 38 14854 #define tx_x2_control0_actualSpeeds_dr_40G_KR4 39 14855 #define tx_x2_control0_actualSpeeds_dr_40G_CR4 40 14856 #define tx_x2_control0_actualSpeeds_dr_100G_CR10 41 14857 #define tx_x2_control0_actualSpeeds_dr_15p75G_DXGXS 44 14858 #define tx_x2_control0_actualSpeeds_dr_20G_KR2 57 14859 #define tx_x2_control0_actualSpeeds_dr_20G_CR2 58 14860 14861 /**************************************************************************** 14862 * Enums: tx_x2_control0_actualSpeedsMisc1 14863 */ 14864 #define tx_x2_control0_actualSpeedsMisc1_dr_2500BRCM_X1 16 14865 #define tx_x2_control0_actualSpeedsMisc1_dr_5000BRCM_X4 17 14866 #define tx_x2_control0_actualSpeedsMisc1_dr_6000BRCM_X4 18 14867 #define tx_x2_control0_actualSpeedsMisc1_dr_10GHiGig_X4 19 14868 #define tx_x2_control0_actualSpeedsMisc1_dr_10GBASE_CX4 20 14869 #define tx_x2_control0_actualSpeedsMisc1_dr_12GHiGig_X4 21 14870 #define tx_x2_control0_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 14871 #define tx_x2_control0_actualSpeedsMisc1_dr_13GHiGig_X4 23 14872 #define tx_x2_control0_actualSpeedsMisc1_dr_15GHiGig_X4 24 14873 #define tx_x2_control0_actualSpeedsMisc1_dr_16GHiGig_X4 25 14874 #define tx_x2_control0_actualSpeedsMisc1_dr_5000BRCM_X1 26 14875 #define tx_x2_control0_actualSpeedsMisc1_dr_6363BRCM_X1 27 14876 #define tx_x2_control0_actualSpeedsMisc1_dr_20GHiGig_X4 28 14877 #define tx_x2_control0_actualSpeedsMisc1_dr_21GHiGig_X4 29 14878 #define tx_x2_control0_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 14879 #define tx_x2_control0_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 14880 14881 /**************************************************************************** 14882 * Enums: tx_x2_control0_IndLaneModes 14883 */ 14884 #define tx_x2_control0_IndLaneModes_SWSDR_div2 0 14885 #define tx_x2_control0_IndLaneModes_SWSDR_div1 1 14886 #define tx_x2_control0_IndLaneModes_DWSDR_div2 2 14887 #define tx_x2_control0_IndLaneModes_DWSDR_div1 3 14888 14889 /**************************************************************************** 14890 * Enums: tx_x2_control0_prbsSelect 14891 */ 14892 #define tx_x2_control0_prbsSelect_prbs7 0 14893 #define tx_x2_control0_prbsSelect_prbs15 1 14894 #define tx_x2_control0_prbsSelect_prbs23 2 14895 #define tx_x2_control0_prbsSelect_prbs31 3 14896 14897 /**************************************************************************** 14898 * Enums: tx_x2_control0_vcoDivider 14899 */ 14900 #define tx_x2_control0_vcoDivider_div32 0 14901 #define tx_x2_control0_vcoDivider_div36 1 14902 #define tx_x2_control0_vcoDivider_div40 2 14903 #define tx_x2_control0_vcoDivider_div42 3 14904 #define tx_x2_control0_vcoDivider_div48 4 14905 #define tx_x2_control0_vcoDivider_div50 5 14906 #define tx_x2_control0_vcoDivider_div52 6 14907 #define tx_x2_control0_vcoDivider_div54 7 14908 #define tx_x2_control0_vcoDivider_div60 8 14909 #define tx_x2_control0_vcoDivider_div64 9 14910 #define tx_x2_control0_vcoDivider_div66 10 14911 #define tx_x2_control0_vcoDivider_div68 11 14912 #define tx_x2_control0_vcoDivider_div70 12 14913 #define tx_x2_control0_vcoDivider_div80 13 14914 #define tx_x2_control0_vcoDivider_div92 14 14915 #define tx_x2_control0_vcoDivider_div100 15 14916 14917 /**************************************************************************** 14918 * Enums: tx_x2_control0_refClkSelect 14919 */ 14920 #define tx_x2_control0_refClkSelect_clk_25MHz 0 14921 #define tx_x2_control0_refClkSelect_clk_100MHz 1 14922 #define tx_x2_control0_refClkSelect_clk_125MHz 2 14923 #define tx_x2_control0_refClkSelect_clk_156p25MHz 3 14924 #define tx_x2_control0_refClkSelect_clk_187p5MHz 4 14925 #define tx_x2_control0_refClkSelect_clk_161p25Mhz 5 14926 #define tx_x2_control0_refClkSelect_clk_50Mhz 6 14927 #define tx_x2_control0_refClkSelect_clk_106p25Mhz 7 14928 14929 /**************************************************************************** 14930 * Enums: tx_x2_control0_aerMMDdevTypeSelect 14931 */ 14932 #define tx_x2_control0_aerMMDdevTypeSelect_combo_core 0 14933 #define tx_x2_control0_aerMMDdevTypeSelect_PMA_PMD 1 14934 #define tx_x2_control0_aerMMDdevTypeSelect_PCS 3 14935 #define tx_x2_control0_aerMMDdevTypeSelect_PHY 4 14936 #define tx_x2_control0_aerMMDdevTypeSelect_DTE 5 14937 #define tx_x2_control0_aerMMDdevTypeSelect_CL73_AN 7 14938 14939 /**************************************************************************** 14940 * Enums: tx_x2_control0_aerMMDportSelect 14941 */ 14942 #define tx_x2_control0_aerMMDportSelect_ln0 0 14943 #define tx_x2_control0_aerMMDportSelect_ln1 1 14944 #define tx_x2_control0_aerMMDportSelect_ln2 2 14945 #define tx_x2_control0_aerMMDportSelect_ln3 3 14946 #define tx_x2_control0_aerMMDportSelect_BCST_ln0_1_2_3 511 14947 #define tx_x2_control0_aerMMDportSelect_BCST_ln0_1 512 14948 #define tx_x2_control0_aerMMDportSelect_BCST_ln2_3 513 14949 14950 /**************************************************************************** 14951 * Enums: tx_x2_control0_firmwareModeSelect 14952 */ 14953 #define tx_x2_control0_firmwareModeSelect_DEFAULT 0 14954 #define tx_x2_control0_firmwareModeSelect_SFP_OPT_LR 1 14955 #define tx_x2_control0_firmwareModeSelect_SFP_DAC 2 14956 #define tx_x2_control0_firmwareModeSelect_XLAUI 3 14957 #define tx_x2_control0_firmwareModeSelect_LONG_CH_6G 4 14958 14959 /**************************************************************************** 14960 * Enums: tx_x2_control0_tempIdxSelect 14961 */ 14962 #define tx_x2_control0_tempIdxSelect_LTE__22p9C 15 14963 #define tx_x2_control0_tempIdxSelect_LTE__12p6C 14 14964 #define tx_x2_control0_tempIdxSelect_LTE__3p0C 13 14965 #define tx_x2_control0_tempIdxSelect_LTE_6p7C 12 14966 #define tx_x2_control0_tempIdxSelect_LTE_16p4C 11 14967 #define tx_x2_control0_tempIdxSelect_LTE_26p6C 10 14968 #define tx_x2_control0_tempIdxSelect_LTE_36p3C 9 14969 #define tx_x2_control0_tempIdxSelect_LTE_46p0C 8 14970 #define tx_x2_control0_tempIdxSelect_LTE_56p2C 7 14971 #define tx_x2_control0_tempIdxSelect_LTE_65p9C 6 14972 #define tx_x2_control0_tempIdxSelect_LTE_75p6C 5 14973 #define tx_x2_control0_tempIdxSelect_LTE_85p3C 4 14974 #define tx_x2_control0_tempIdxSelect_LTE_95p5C 3 14975 #define tx_x2_control0_tempIdxSelect_LTE_105p2C 2 14976 #define tx_x2_control0_tempIdxSelect_LTE_114p9C 1 14977 #define tx_x2_control0_tempIdxSelect_LTE_125p1C 0 14978 14979 /**************************************************************************** 14980 * Enums: tx_x2_control0_port_mode 14981 */ 14982 #define tx_x2_control0_port_mode_QUAD_PORT 0 14983 #define tx_x2_control0_port_mode_TRI_1_PORT 1 14984 #define tx_x2_control0_port_mode_TRI_2_PORT 2 14985 #define tx_x2_control0_port_mode_DUAL_PORT 3 14986 #define tx_x2_control0_port_mode_SINGLE_PORT 4 14987 14988 /**************************************************************************** 14989 * Enums: tx_x2_control0_rev_letter_enum 14990 */ 14991 #define tx_x2_control0_rev_letter_enum_REV_A 0 14992 #define tx_x2_control0_rev_letter_enum_REV_B 1 14993 #define tx_x2_control0_rev_letter_enum_REV_C 2 14994 #define tx_x2_control0_rev_letter_enum_REV_D 3 14995 14996 /**************************************************************************** 14997 * Enums: tx_x2_control0_rev_number_enum 14998 */ 14999 #define tx_x2_control0_rev_number_enum_REV_0 0 15000 #define tx_x2_control0_rev_number_enum_REV_1 1 15001 #define tx_x2_control0_rev_number_enum_REV_2 2 15002 #define tx_x2_control0_rev_number_enum_REV_3 3 15003 #define tx_x2_control0_rev_number_enum_REV_4 4 15004 #define tx_x2_control0_rev_number_enum_REV_5 5 15005 #define tx_x2_control0_rev_number_enum_REV_6 6 15006 #define tx_x2_control0_rev_number_enum_REV_7 7 15007 15008 /**************************************************************************** 15009 * Enums: tx_x2_control0_bonding_enum 15010 */ 15011 #define tx_x2_control0_bonding_enum_WIRE_BOND 0 15012 #define tx_x2_control0_bonding_enum_FLIP_CHIP 1 15013 15014 /**************************************************************************** 15015 * Enums: tx_x2_control0_tech_process 15016 */ 15017 #define tx_x2_control0_tech_process_PROCESS_90NM 0 15018 #define tx_x2_control0_tech_process_PROCESS_65NM 1 15019 #define tx_x2_control0_tech_process_PROCESS_40NM 2 15020 #define tx_x2_control0_tech_process_PROCESS_28NM 3 15021 15022 /**************************************************************************** 15023 * Enums: tx_x2_control0_model_num 15024 */ 15025 #define tx_x2_control0_model_num_SERDES_CL73 0 15026 #define tx_x2_control0_model_num_XGXS_16G 1 15027 #define tx_x2_control0_model_num_HYPERCORE 2 15028 #define tx_x2_control0_model_num_HYPERLITE 3 15029 #define tx_x2_control0_model_num_PCIE_G2_PIPE 4 15030 #define tx_x2_control0_model_num_SERDES_1p25GBd 5 15031 #define tx_x2_control0_model_num_SATA2 6 15032 #define tx_x2_control0_model_num_QSGMII 7 15033 #define tx_x2_control0_model_num_XGXS10G 8 15034 #define tx_x2_control0_model_num_WARPCORE 9 15035 #define tx_x2_control0_model_num_XFICORE 10 15036 #define tx_x2_control0_model_num_RXFI 11 15037 #define tx_x2_control0_model_num_WARPLITE 12 15038 #define tx_x2_control0_model_num_PENTACORE 13 15039 #define tx_x2_control0_model_num_ESM 14 15040 #define tx_x2_control0_model_num_QUAD_SGMII 15 15041 #define tx_x2_control0_model_num_WARPCORE_3 16 15042 #define tx_x2_control0_model_num_TSC 17 15043 #define tx_x2_control0_model_num_TSC4E 18 15044 #define tx_x2_control0_model_num_TSC12E 19 15045 #define tx_x2_control0_model_num_TSC4F 20 15046 #define tx_x2_control0_model_num_XGXS_CL73_90NM 29 15047 #define tx_x2_control0_model_num_SERDES_CL73_90NM 30 15048 #define tx_x2_control0_model_num_WARPCORE3 32 15049 #define tx_x2_control0_model_num_WARPCORE4_TSC 33 15050 #define tx_x2_control0_model_num_RXAUI 34 15051 15052 /**************************************************************************** 15053 * Enums: tx_x2_control0_payload 15054 */ 15055 #define tx_x2_control0_payload_REPEAT_2_BYTES 0 15056 #define tx_x2_control0_payload_RAMPING 1 15057 #define tx_x2_control0_payload_CL48_CRPAT 2 15058 #define tx_x2_control0_payload_CL48_CJPAT 3 15059 #define tx_x2_control0_payload_CL36_LONG_CRPAT 4 15060 #define tx_x2_control0_payload_CL36_SHORT_CRPAT 5 15061 15062 /**************************************************************************** 15063 * Enums: tx_x2_control0_sc 15064 */ 15065 #define tx_x2_control0_sc_S_10G_CR1 0 15066 #define tx_x2_control0_sc_S_10G_KR1 1 15067 #define tx_x2_control0_sc_S_10G_X1 2 15068 #define tx_x2_control0_sc_S_10G_HG2_CR1 4 15069 #define tx_x2_control0_sc_S_10G_HG2_KR1 5 15070 #define tx_x2_control0_sc_S_10G_HG2_X1 6 15071 #define tx_x2_control0_sc_S_20G_CR1 8 15072 #define tx_x2_control0_sc_S_20G_KR1 9 15073 #define tx_x2_control0_sc_S_20G_X1 10 15074 #define tx_x2_control0_sc_S_20G_HG2_CR1 12 15075 #define tx_x2_control0_sc_S_20G_HG2_KR1 13 15076 #define tx_x2_control0_sc_S_20G_HG2_X1 14 15077 #define tx_x2_control0_sc_S_25G_CR1 16 15078 #define tx_x2_control0_sc_S_25G_KR1 17 15079 #define tx_x2_control0_sc_S_25G_X1 18 15080 #define tx_x2_control0_sc_S_25G_HG2_CR1 20 15081 #define tx_x2_control0_sc_S_25G_HG2_KR1 21 15082 #define tx_x2_control0_sc_S_25G_HG2_X1 22 15083 #define tx_x2_control0_sc_S_20G_CR2 24 15084 #define tx_x2_control0_sc_S_20G_KR2 25 15085 #define tx_x2_control0_sc_S_20G_X2 26 15086 #define tx_x2_control0_sc_S_20G_HG2_CR2 28 15087 #define tx_x2_control0_sc_S_20G_HG2_KR2 29 15088 #define tx_x2_control0_sc_S_20G_HG2_X2 30 15089 #define tx_x2_control0_sc_S_40G_CR2 32 15090 #define tx_x2_control0_sc_S_40G_KR2 33 15091 #define tx_x2_control0_sc_S_40G_X2 34 15092 #define tx_x2_control0_sc_S_40G_HG2_CR2 36 15093 #define tx_x2_control0_sc_S_40G_HG2_KR2 37 15094 #define tx_x2_control0_sc_S_40G_HG2_X2 38 15095 #define tx_x2_control0_sc_S_40G_CR4 40 15096 #define tx_x2_control0_sc_S_40G_KR4 41 15097 #define tx_x2_control0_sc_S_40G_X4 42 15098 #define tx_x2_control0_sc_S_40G_HG2_CR4 44 15099 #define tx_x2_control0_sc_S_40G_HG2_KR4 45 15100 #define tx_x2_control0_sc_S_40G_HG2_X4 46 15101 #define tx_x2_control0_sc_S_50G_CR2 48 15102 #define tx_x2_control0_sc_S_50G_KR2 49 15103 #define tx_x2_control0_sc_S_50G_X2 50 15104 #define tx_x2_control0_sc_S_50G_HG2_CR2 52 15105 #define tx_x2_control0_sc_S_50G_HG2_KR2 53 15106 #define tx_x2_control0_sc_S_50G_HG2_X2 54 15107 #define tx_x2_control0_sc_S_50G_CR4 56 15108 #define tx_x2_control0_sc_S_50G_KR4 57 15109 #define tx_x2_control0_sc_S_50G_X4 58 15110 #define tx_x2_control0_sc_S_50G_HG2_CR4 60 15111 #define tx_x2_control0_sc_S_50G_HG2_KR4 61 15112 #define tx_x2_control0_sc_S_50G_HG2_X4 62 15113 #define tx_x2_control0_sc_S_100G_CR4 64 15114 #define tx_x2_control0_sc_S_100G_KR4 65 15115 #define tx_x2_control0_sc_S_100G_X4 66 15116 #define tx_x2_control0_sc_S_100G_HG2_CR4 68 15117 #define tx_x2_control0_sc_S_100G_HG2_KR4 69 15118 #define tx_x2_control0_sc_S_100G_HG2_X4 70 15119 #define tx_x2_control0_sc_S_CL73_20GVCO 72 15120 #define tx_x2_control0_sc_S_CL73_25GVCO 80 15121 #define tx_x2_control0_sc_S_CL36_20GVCO 88 15122 #define tx_x2_control0_sc_S_CL36_25GVCO 96 15123 15124 /**************************************************************************** 15125 * Enums: tx_x2_control0_t_fifo_modes 15126 */ 15127 #define tx_x2_control0_t_fifo_modes_T_FIFO_MODE_BYPASS 0 15128 #define tx_x2_control0_t_fifo_modes_T_FIFO_MODE_40G 1 15129 #define tx_x2_control0_t_fifo_modes_T_FIFO_MODE_100G 2 15130 #define tx_x2_control0_t_fifo_modes_T_FIFO_MODE_20G 3 15131 15132 /**************************************************************************** 15133 * Enums: tx_x2_control0_t_enc_modes 15134 */ 15135 #define tx_x2_control0_t_enc_modes_T_ENC_MODE_BYPASS 0 15136 #define tx_x2_control0_t_enc_modes_T_ENC_MODE_CL49 1 15137 #define tx_x2_control0_t_enc_modes_T_ENC_MODE_CL82 2 15138 15139 /**************************************************************************** 15140 * Enums: tx_x2_control0_btmx_mode 15141 */ 15142 #define tx_x2_control0_btmx_mode_BS_BTMX_MODE_1to1 0 15143 #define tx_x2_control0_btmx_mode_BS_BTMX_MODE_2to1 1 15144 #define tx_x2_control0_btmx_mode_BS_BTMX_MODE_5to1 2 15145 15146 /**************************************************************************** 15147 * Enums: tx_x2_control0_t_type_cl82 15148 */ 15149 #define tx_x2_control0_t_type_cl82_T_TYPE_B1 5 15150 #define tx_x2_control0_t_type_cl82_T_TYPE_C 4 15151 #define tx_x2_control0_t_type_cl82_T_TYPE_S 3 15152 #define tx_x2_control0_t_type_cl82_T_TYPE_T 2 15153 #define tx_x2_control0_t_type_cl82_T_TYPE_D 1 15154 #define tx_x2_control0_t_type_cl82_T_TYPE_E 0 15155 15156 /**************************************************************************** 15157 * Enums: tx_x2_control0_txsm_state_cl82 15158 */ 15159 #define tx_x2_control0_txsm_state_cl82_TX_HIG_END 6 15160 #define tx_x2_control0_txsm_state_cl82_TX_HIG_START 5 15161 #define tx_x2_control0_txsm_state_cl82_TX_E 4 15162 #define tx_x2_control0_txsm_state_cl82_TX_T 3 15163 #define tx_x2_control0_txsm_state_cl82_TX_D 2 15164 #define tx_x2_control0_txsm_state_cl82_TX_C 1 15165 #define tx_x2_control0_txsm_state_cl82_TX_INIT 0 15166 15167 /**************************************************************************** 15168 * Enums: tx_x2_control0_ltxsm_state_cl82 15169 */ 15170 #define tx_x2_control0_ltxsm_state_cl82_TX_HIG_END 64 15171 #define tx_x2_control0_ltxsm_state_cl82_TX_HIG_START 32 15172 #define tx_x2_control0_ltxsm_state_cl82_TX_E 16 15173 #define tx_x2_control0_ltxsm_state_cl82_TX_T 8 15174 #define tx_x2_control0_ltxsm_state_cl82_TX_D 4 15175 #define tx_x2_control0_ltxsm_state_cl82_TX_C 2 15176 #define tx_x2_control0_ltxsm_state_cl82_TX_INIT 1 15177 15178 /**************************************************************************** 15179 * Enums: tx_x2_control0_r_type_coded_cl82 15180 */ 15181 #define tx_x2_control0_r_type_coded_cl82_R_TYPE_B1 32 15182 #define tx_x2_control0_r_type_coded_cl82_R_TYPE_C 16 15183 #define tx_x2_control0_r_type_coded_cl82_R_TYPE_S 8 15184 #define tx_x2_control0_r_type_coded_cl82_R_TYPE_T 4 15185 #define tx_x2_control0_r_type_coded_cl82_R_TYPE_D 2 15186 #define tx_x2_control0_r_type_coded_cl82_R_TYPE_E 1 15187 15188 /**************************************************************************** 15189 * Enums: tx_x2_control0_rxsm_state_cl82 15190 */ 15191 #define tx_x2_control0_rxsm_state_cl82_RX_HIG_END 64 15192 #define tx_x2_control0_rxsm_state_cl82_RX_HIG_START 32 15193 #define tx_x2_control0_rxsm_state_cl82_RX_E 16 15194 #define tx_x2_control0_rxsm_state_cl82_RX_T 8 15195 #define tx_x2_control0_rxsm_state_cl82_RX_D 4 15196 #define tx_x2_control0_rxsm_state_cl82_RX_C 2 15197 #define tx_x2_control0_rxsm_state_cl82_RX_INIT 1 15198 15199 /**************************************************************************** 15200 * Enums: tx_x2_control0_deskew_state 15201 */ 15202 #define tx_x2_control0_deskew_state_ALIGN_ACQUIRED 2 15203 #define tx_x2_control0_deskew_state_LOSS_OF_ALIGNMENT 1 15204 15205 /**************************************************************************** 15206 * Enums: tx_x2_control0_os_mode_enum 15207 */ 15208 #define tx_x2_control0_os_mode_enum_OS_MODE_1 0 15209 #define tx_x2_control0_os_mode_enum_OS_MODE_2 1 15210 #define tx_x2_control0_os_mode_enum_OS_MODE_4 2 15211 #define tx_x2_control0_os_mode_enum_OS_MODE_16p5 8 15212 #define tx_x2_control0_os_mode_enum_OS_MODE_20p625 12 15213 15214 /**************************************************************************** 15215 * Enums: tx_x2_control0_scr_modes 15216 */ 15217 #define tx_x2_control0_scr_modes_T_SCR_MODE_BYPASS 0 15218 #define tx_x2_control0_scr_modes_T_SCR_MODE_CL49 1 15219 #define tx_x2_control0_scr_modes_T_SCR_MODE_40G_2_LANE 2 15220 #define tx_x2_control0_scr_modes_T_SCR_MODE_100G 3 15221 #define tx_x2_control0_scr_modes_T_SCR_MODE_20G 4 15222 #define tx_x2_control0_scr_modes_T_SCR_MODE_40G_4_LANE 5 15223 15224 /**************************************************************************** 15225 * Enums: tx_x2_control0_descr_modes 15226 */ 15227 #define tx_x2_control0_descr_modes_R_DESCR_MODE_BYPASS 0 15228 #define tx_x2_control0_descr_modes_R_DESCR_MODE_CL49 1 15229 #define tx_x2_control0_descr_modes_R_DESCR_MODE_CL82 2 15230 15231 /**************************************************************************** 15232 * Enums: tx_x2_control0_r_dec_tl_mode 15233 */ 15234 #define tx_x2_control0_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 15235 #define tx_x2_control0_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 15236 #define tx_x2_control0_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 15237 15238 /**************************************************************************** 15239 * Enums: tx_x2_control0_r_dec_fsm_mode 15240 */ 15241 #define tx_x2_control0_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 15242 #define tx_x2_control0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 15243 #define tx_x2_control0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 15244 15245 /**************************************************************************** 15246 * Enums: tx_x2_control0_r_deskew_mode 15247 */ 15248 #define tx_x2_control0_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 15249 #define tx_x2_control0_r_deskew_mode_R_DESKEW_MODE_20G 1 15250 #define tx_x2_control0_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 15251 #define tx_x2_control0_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 15252 #define tx_x2_control0_r_deskew_mode_R_DESKEW_MODE_100G 4 15253 #define tx_x2_control0_r_deskew_mode_R_DESKEW_MODE_CL49 5 15254 #define tx_x2_control0_r_deskew_mode_R_DESKEW_MODE_CL91 6 15255 15256 /**************************************************************************** 15257 * Enums: tx_x2_control0_bs_dist_modes 15258 */ 15259 #define tx_x2_control0_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 15260 #define tx_x2_control0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 15261 #define tx_x2_control0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 15262 #define tx_x2_control0_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 15263 15264 /**************************************************************************** 15265 * Enums: tx_x2_control0_cl49_t_type 15266 */ 15267 #define tx_x2_control0_cl49_t_type_BAD_T_TYPE 15 15268 #define tx_x2_control0_cl49_t_type_T_TYPE_B0 11 15269 #define tx_x2_control0_cl49_t_type_T_TYPE_OB 10 15270 #define tx_x2_control0_cl49_t_type_T_TYPE_B1 9 15271 #define tx_x2_control0_cl49_t_type_T_TYPE_DB 8 15272 #define tx_x2_control0_cl49_t_type_T_TYPE_FC 7 15273 #define tx_x2_control0_cl49_t_type_T_TYPE_TB 6 15274 #define tx_x2_control0_cl49_t_type_T_TYPE_LI 5 15275 #define tx_x2_control0_cl49_t_type_T_TYPE_C 4 15276 #define tx_x2_control0_cl49_t_type_T_TYPE_S 3 15277 #define tx_x2_control0_cl49_t_type_T_TYPE_T 2 15278 #define tx_x2_control0_cl49_t_type_T_TYPE_D 1 15279 #define tx_x2_control0_cl49_t_type_T_TYPE_E 0 15280 15281 /**************************************************************************** 15282 * Enums: tx_x2_control0_cl49_txsm_states 15283 */ 15284 #define tx_x2_control0_cl49_txsm_states_TX_HIG_END 7 15285 #define tx_x2_control0_cl49_txsm_states_TX_HIG_START 6 15286 #define tx_x2_control0_cl49_txsm_states_TX_LI 5 15287 #define tx_x2_control0_cl49_txsm_states_TX_E 4 15288 #define tx_x2_control0_cl49_txsm_states_TX_T 3 15289 #define tx_x2_control0_cl49_txsm_states_TX_D 2 15290 #define tx_x2_control0_cl49_txsm_states_TX_C 1 15291 #define tx_x2_control0_cl49_txsm_states_TX_INIT 0 15292 15293 /**************************************************************************** 15294 * Enums: tx_x2_control0_cl49_ltxsm_states 15295 */ 15296 #define tx_x2_control0_cl49_ltxsm_states_TX_HIG_END 128 15297 #define tx_x2_control0_cl49_ltxsm_states_TX_HIG_START 64 15298 #define tx_x2_control0_cl49_ltxsm_states_TX_LI 32 15299 #define tx_x2_control0_cl49_ltxsm_states_TX_E 16 15300 #define tx_x2_control0_cl49_ltxsm_states_TX_T 8 15301 #define tx_x2_control0_cl49_ltxsm_states_TX_D 4 15302 #define tx_x2_control0_cl49_ltxsm_states_TX_C 2 15303 #define tx_x2_control0_cl49_ltxsm_states_TX_INIT 1 15304 15305 /**************************************************************************** 15306 * Enums: tx_x2_control0_burst_error_mode 15307 */ 15308 #define tx_x2_control0_burst_error_mode_BURST_ERROR_11_BITS 0 15309 #define tx_x2_control0_burst_error_mode_BURST_ERROR_16_BITS 1 15310 #define tx_x2_control0_burst_error_mode_BURST_ERROR_17_BITS 2 15311 #define tx_x2_control0_burst_error_mode_BURST_ERROR_18_BITS 3 15312 #define tx_x2_control0_burst_error_mode_BURST_ERROR_19_BITS 4 15313 #define tx_x2_control0_burst_error_mode_BURST_ERROR_20_BITS 5 15314 #define tx_x2_control0_burst_error_mode_BURST_ERROR_21_BITS 6 15315 #define tx_x2_control0_burst_error_mode_BURST_ERROR_22_BITS 7 15316 #define tx_x2_control0_burst_error_mode_BURST_ERROR_23_BITS 8 15317 #define tx_x2_control0_burst_error_mode_BURST_ERROR_24_BITS 9 15318 #define tx_x2_control0_burst_error_mode_BURST_ERROR_25_BITS 10 15319 #define tx_x2_control0_burst_error_mode_BURST_ERROR_26_BITS 11 15320 #define tx_x2_control0_burst_error_mode_BURST_ERROR_27_BITS 12 15321 #define tx_x2_control0_burst_error_mode_BURST_ERROR_28_BITS 13 15322 #define tx_x2_control0_burst_error_mode_BURST_ERROR_29_BITS 14 15323 #define tx_x2_control0_burst_error_mode_BURST_ERROR_30_BITS 15 15324 #define tx_x2_control0_burst_error_mode_BURST_ERROR_31_BITS 16 15325 #define tx_x2_control0_burst_error_mode_BURST_ERROR_32_BITS 17 15326 #define tx_x2_control0_burst_error_mode_BURST_ERROR_33_BITS 18 15327 #define tx_x2_control0_burst_error_mode_BURST_ERROR_34_BITS 19 15328 #define tx_x2_control0_burst_error_mode_BURST_ERROR_35_BITS 20 15329 #define tx_x2_control0_burst_error_mode_BURST_ERROR_36_BITS 21 15330 #define tx_x2_control0_burst_error_mode_BURST_ERROR_37_BITS 22 15331 #define tx_x2_control0_burst_error_mode_BURST_ERROR_38_BITS 23 15332 #define tx_x2_control0_burst_error_mode_BURST_ERROR_39_BITS 24 15333 #define tx_x2_control0_burst_error_mode_BURST_ERROR_40_BITS 25 15334 #define tx_x2_control0_burst_error_mode_BURST_ERROR_41_BITS 26 15335 15336 /**************************************************************************** 15337 * Enums: tx_x2_control0_bermon_state 15338 */ 15339 #define tx_x2_control0_bermon_state_HI_BER 4 15340 #define tx_x2_control0_bermon_state_GOOD_BER 3 15341 #define tx_x2_control0_bermon_state_BER_TEST_SH 2 15342 #define tx_x2_control0_bermon_state_START_TIMER 1 15343 #define tx_x2_control0_bermon_state_BER_MT_INIT 0 15344 15345 /**************************************************************************** 15346 * Enums: tx_x2_control0_rxsm_state_cl49 15347 */ 15348 #define tx_x2_control0_rxsm_state_cl49_RX_HIG_END 128 15349 #define tx_x2_control0_rxsm_state_cl49_RX_HIG_START 64 15350 #define tx_x2_control0_rxsm_state_cl49_RX_LI 32 15351 #define tx_x2_control0_rxsm_state_cl49_RX_E 16 15352 #define tx_x2_control0_rxsm_state_cl49_RX_T 8 15353 #define tx_x2_control0_rxsm_state_cl49_RX_D 4 15354 #define tx_x2_control0_rxsm_state_cl49_RX_C 2 15355 #define tx_x2_control0_rxsm_state_cl49_RX_INIT 1 15356 15357 /**************************************************************************** 15358 * Enums: tx_x2_control0_r_type 15359 */ 15360 #define tx_x2_control0_r_type_BAD_R_TYPE 15 15361 #define tx_x2_control0_r_type_R_TYPE_B0 11 15362 #define tx_x2_control0_r_type_R_TYPE_OB 10 15363 #define tx_x2_control0_r_type_R_TYPE_B1 9 15364 #define tx_x2_control0_r_type_R_TYPE_DB 8 15365 #define tx_x2_control0_r_type_R_TYPE_FC 7 15366 #define tx_x2_control0_r_type_R_TYPE_TB 6 15367 #define tx_x2_control0_r_type_R_TYPE_LI 5 15368 #define tx_x2_control0_r_type_R_TYPE_C 4 15369 #define tx_x2_control0_r_type_R_TYPE_S 3 15370 #define tx_x2_control0_r_type_R_TYPE_T 2 15371 #define tx_x2_control0_r_type_R_TYPE_D 1 15372 #define tx_x2_control0_r_type_R_TYPE_E 0 15373 15374 /**************************************************************************** 15375 * Enums: tx_x2_control0_am_lock_state 15376 */ 15377 #define tx_x2_control0_am_lock_state_INVALID_AM 512 15378 #define tx_x2_control0_am_lock_state_GOOD_AM 256 15379 #define tx_x2_control0_am_lock_state_COMP_AM 128 15380 #define tx_x2_control0_am_lock_state_TIMER_2 64 15381 #define tx_x2_control0_am_lock_state_AM_2_GOOD 32 15382 #define tx_x2_control0_am_lock_state_COMP_2ND 16 15383 #define tx_x2_control0_am_lock_state_TIMER_1 8 15384 #define tx_x2_control0_am_lock_state_FIND_1ST 4 15385 #define tx_x2_control0_am_lock_state_AM_RESET_CNT 2 15386 #define tx_x2_control0_am_lock_state_AM_LOCK_INIT 1 15387 15388 /**************************************************************************** 15389 * Enums: tx_x2_control0_msg_selector 15390 */ 15391 #define tx_x2_control0_msg_selector_RESERVED 0 15392 #define tx_x2_control0_msg_selector_VALUE_802p3 1 15393 #define tx_x2_control0_msg_selector_VALUE_802p9 2 15394 #define tx_x2_control0_msg_selector_VALUE_802p5 3 15395 #define tx_x2_control0_msg_selector_VALUE_1394 4 15396 15397 /**************************************************************************** 15398 * Enums: tx_x2_control0_synce_enum 15399 */ 15400 #define tx_x2_control0_synce_enum_SYNCE_NO_DIV 0 15401 #define tx_x2_control0_synce_enum_SYNCE_DIV_7 1 15402 #define tx_x2_control0_synce_enum_SYNCE_DIV_11 2 15403 15404 /**************************************************************************** 15405 * Enums: tx_x2_control0_synce_enum_stage0 15406 */ 15407 #define tx_x2_control0_synce_enum_stage0_SYNCE_NO_DIV 0 15408 #define tx_x2_control0_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 15409 #define tx_x2_control0_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 15410 15411 /**************************************************************************** 15412 * Enums: tx_x2_control0_cl91_sync_state 15413 */ 15414 #define tx_x2_control0_cl91_sync_state_FIND_1ST 0 15415 #define tx_x2_control0_cl91_sync_state_COUNT_NEXT 1 15416 #define tx_x2_control0_cl91_sync_state_COMP_2ND 2 15417 #define tx_x2_control0_cl91_sync_state_TWO_GOOD 3 15418 15419 /**************************************************************************** 15420 * Enums: tx_x2_control0_cl91_algn_state 15421 */ 15422 #define tx_x2_control0_cl91_algn_state_LOSS_OF_ALIGNMENT 0 15423 #define tx_x2_control0_cl91_algn_state_DESKEW 1 15424 #define tx_x2_control0_cl91_algn_state_DESKEW_FAIL 2 15425 #define tx_x2_control0_cl91_algn_state_ALIGN_ACQUIRED 3 15426 #define tx_x2_control0_cl91_algn_state_CW_GOOD 4 15427 #define tx_x2_control0_cl91_algn_state_CW_BAD 5 15428 #define tx_x2_control0_cl91_algn_state_THREE_BAD 6 15429 15430 /**************************************************************************** 15431 * Enums: tx_x2_control0_fec_sel 15432 */ 15433 #define tx_x2_control0_fec_sel_NO_FEC 0 15434 #define tx_x2_control0_fec_sel_FEC_CL74 1 15435 #define tx_x2_control0_fec_sel_FEC_CL91 2 15436 15437 /**************************************************************************** 15438 * Enums: tx_x2_status0_cl36TxEEEStates_l 15439 */ 15440 #define tx_x2_status0_cl36TxEEEStates_l_TX_REFRESH 8 15441 #define tx_x2_status0_cl36TxEEEStates_l_TX_QUIET 4 15442 #define tx_x2_status0_cl36TxEEEStates_l_TX_SLEEP 2 15443 #define tx_x2_status0_cl36TxEEEStates_l_TX_ACTIVE 1 15444 15445 /**************************************************************************** 15446 * Enums: tx_x2_status0_cl36TxEEEStates_c 15447 */ 15448 #define tx_x2_status0_cl36TxEEEStates_c_TX_REFRESH 3 15449 #define tx_x2_status0_cl36TxEEEStates_c_TX_QUIET 2 15450 #define tx_x2_status0_cl36TxEEEStates_c_TX_SLEEP 1 15451 #define tx_x2_status0_cl36TxEEEStates_c_TX_ACTIVE 0 15452 15453 /**************************************************************************** 15454 * Enums: tx_x2_status0_cl49TxEEEStates_l 15455 */ 15456 #define tx_x2_status0_cl49TxEEEStates_l_SCR_RESET_2 64 15457 #define tx_x2_status0_cl49TxEEEStates_l_SCR_RESET_1 32 15458 #define tx_x2_status0_cl49TxEEEStates_l_TX_WAKE 16 15459 #define tx_x2_status0_cl49TxEEEStates_l_TX_REFRESH 8 15460 #define tx_x2_status0_cl49TxEEEStates_l_TX_QUIET 4 15461 #define tx_x2_status0_cl49TxEEEStates_l_TX_SLEEP 2 15462 #define tx_x2_status0_cl49TxEEEStates_l_TX_ACTIVE 1 15463 15464 /**************************************************************************** 15465 * Enums: tx_x2_status0_fec_req_enum 15466 */ 15467 #define tx_x2_status0_fec_req_enum_FEC_not_supported 0 15468 #define tx_x2_status0_fec_req_enum_FEC_supported_but_not_requested 1 15469 #define tx_x2_status0_fec_req_enum_invalid_setting 2 15470 #define tx_x2_status0_fec_req_enum_FEC_supported_and_requested 3 15471 15472 /**************************************************************************** 15473 * Enums: tx_x2_status0_cl73_pause_enum 15474 */ 15475 #define tx_x2_status0_cl73_pause_enum_No_PAUSE_ability 0 15476 #define tx_x2_status0_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 15477 #define tx_x2_status0_cl73_pause_enum_Symmetric_PAUSE_ability 1 15478 #define tx_x2_status0_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 15479 15480 /**************************************************************************** 15481 * Enums: tx_x2_status0_cl49TxEEEStates_c 15482 */ 15483 #define tx_x2_status0_cl49TxEEEStates_c_SCR_RESET_2 6 15484 #define tx_x2_status0_cl49TxEEEStates_c_SCR_RESET_1 5 15485 #define tx_x2_status0_cl49TxEEEStates_c_TX_WAKE 4 15486 #define tx_x2_status0_cl49TxEEEStates_c_TX_REFRESH 3 15487 #define tx_x2_status0_cl49TxEEEStates_c_TX_QUIET 2 15488 #define tx_x2_status0_cl49TxEEEStates_c_TX_SLEEP 1 15489 #define tx_x2_status0_cl49TxEEEStates_c_TX_ACTIVE 0 15490 15491 /**************************************************************************** 15492 * Enums: tx_x2_status0_cl36RxEEEStates_l 15493 */ 15494 #define tx_x2_status0_cl36RxEEEStates_l_RX_LINK_FAIL 32 15495 #define tx_x2_status0_cl36RxEEEStates_l_RX_WTF 16 15496 #define tx_x2_status0_cl36RxEEEStates_l_RX_WAKE 8 15497 #define tx_x2_status0_cl36RxEEEStates_l_RX_QUIET 4 15498 #define tx_x2_status0_cl36RxEEEStates_l_RX_SLEEP 2 15499 #define tx_x2_status0_cl36RxEEEStates_l_RX_ACTIVE 1 15500 15501 /**************************************************************************** 15502 * Enums: tx_x2_status0_cl36RxEEEStates_c 15503 */ 15504 #define tx_x2_status0_cl36RxEEEStates_c_RX_LINK_FAIL 5 15505 #define tx_x2_status0_cl36RxEEEStates_c_RX_WTF 4 15506 #define tx_x2_status0_cl36RxEEEStates_c_RX_WAKE 3 15507 #define tx_x2_status0_cl36RxEEEStates_c_RX_QUIET 2 15508 #define tx_x2_status0_cl36RxEEEStates_c_RX_SLEEP 1 15509 #define tx_x2_status0_cl36RxEEEStates_c_RX_ACTIVE 0 15510 15511 /**************************************************************************** 15512 * Enums: tx_x2_status0_cl49RxEEEStates_l 15513 */ 15514 #define tx_x2_status0_cl49RxEEEStates_l_RX_LINK_FAIL 32 15515 #define tx_x2_status0_cl49RxEEEStates_l_RX_WTF 16 15516 #define tx_x2_status0_cl49RxEEEStates_l_RX_WAKE 8 15517 #define tx_x2_status0_cl49RxEEEStates_l_RX_QUIET 4 15518 #define tx_x2_status0_cl49RxEEEStates_l_RX_SLEEP 2 15519 #define tx_x2_status0_cl49RxEEEStates_l_RX_ACTIVE 1 15520 15521 /**************************************************************************** 15522 * Enums: tx_x2_status0_cl49RxEEEStates_c 15523 */ 15524 #define tx_x2_status0_cl49RxEEEStates_c_RX_LINK_FAIL 5 15525 #define tx_x2_status0_cl49RxEEEStates_c_RX_WTF 4 15526 #define tx_x2_status0_cl49RxEEEStates_c_RX_WAKE 3 15527 #define tx_x2_status0_cl49RxEEEStates_c_RX_QUIET 2 15528 #define tx_x2_status0_cl49RxEEEStates_c_RX_SLEEP 1 15529 #define tx_x2_status0_cl49RxEEEStates_c_RX_ACTIVE 0 15530 15531 /**************************************************************************** 15532 * Enums: tx_x2_status0_cl48TxEEEStates_l 15533 */ 15534 #define tx_x2_status0_cl48TxEEEStates_l_TX_REFRESH 8 15535 #define tx_x2_status0_cl48TxEEEStates_l_TX_QUIET 4 15536 #define tx_x2_status0_cl48TxEEEStates_l_TX_SLEEP 2 15537 #define tx_x2_status0_cl48TxEEEStates_l_TX_ACTIVE 1 15538 15539 /**************************************************************************** 15540 * Enums: tx_x2_status0_cl48TxEEEStates_c 15541 */ 15542 #define tx_x2_status0_cl48TxEEEStates_c_TX_REFRESH 3 15543 #define tx_x2_status0_cl48TxEEEStates_c_TX_QUIET 2 15544 #define tx_x2_status0_cl48TxEEEStates_c_TX_SLEEP 1 15545 #define tx_x2_status0_cl48TxEEEStates_c_TX_ACTIVE 0 15546 15547 /**************************************************************************** 15548 * Enums: tx_x2_status0_cl48RxEEEStates_l 15549 */ 15550 #define tx_x2_status0_cl48RxEEEStates_l_RX_LINK_FAIL 32 15551 #define tx_x2_status0_cl48RxEEEStates_l_RX_WAKE 16 15552 #define tx_x2_status0_cl48RxEEEStates_l_RX_QUIET 8 15553 #define tx_x2_status0_cl48RxEEEStates_l_RX_DEACT 4 15554 #define tx_x2_status0_cl48RxEEEStates_l_RX_SLEEP 2 15555 #define tx_x2_status0_cl48RxEEEStates_l_RX_ACTIVE 1 15556 15557 /**************************************************************************** 15558 * Enums: tx_x2_status0_cl48RxEEEStates_c 15559 */ 15560 #define tx_x2_status0_cl48RxEEEStates_c_RX_LINK_FAIL 5 15561 #define tx_x2_status0_cl48RxEEEStates_c_RX_WAKE 4 15562 #define tx_x2_status0_cl48RxEEEStates_c_RX_QUIET 3 15563 #define tx_x2_status0_cl48RxEEEStates_c_RX_DEACT 2 15564 #define tx_x2_status0_cl48RxEEEStates_c_RX_SLEEP 1 15565 #define tx_x2_status0_cl48RxEEEStates_c_RX_ACTIVE 0 15566 15567 /**************************************************************************** 15568 * Enums: tx_x2_status0_IQP_Options 15569 */ 15570 #define tx_x2_status0_IQP_Options_i50uA 0 15571 #define tx_x2_status0_IQP_Options_i100uA 1 15572 #define tx_x2_status0_IQP_Options_i150uA 2 15573 #define tx_x2_status0_IQP_Options_i200uA 3 15574 #define tx_x2_status0_IQP_Options_i250uA 4 15575 #define tx_x2_status0_IQP_Options_i300uA 5 15576 #define tx_x2_status0_IQP_Options_i350uA 6 15577 #define tx_x2_status0_IQP_Options_i400uA 7 15578 #define tx_x2_status0_IQP_Options_i450uA 8 15579 #define tx_x2_status0_IQP_Options_i500uA 9 15580 #define tx_x2_status0_IQP_Options_i550uA 10 15581 #define tx_x2_status0_IQP_Options_i600uA 11 15582 #define tx_x2_status0_IQP_Options_i650uA 12 15583 #define tx_x2_status0_IQP_Options_i700uA 13 15584 #define tx_x2_status0_IQP_Options_i750uA 14 15585 #define tx_x2_status0_IQP_Options_i800uA 15 15586 15587 /**************************************************************************** 15588 * Enums: tx_x2_status0_IDriver_Options 15589 */ 15590 #define tx_x2_status0_IDriver_Options_v680mV 0 15591 #define tx_x2_status0_IDriver_Options_v730mV 1 15592 #define tx_x2_status0_IDriver_Options_v780mV 2 15593 #define tx_x2_status0_IDriver_Options_v830mV 3 15594 #define tx_x2_status0_IDriver_Options_v880mV 4 15595 #define tx_x2_status0_IDriver_Options_v930mV 5 15596 #define tx_x2_status0_IDriver_Options_v980mV 6 15597 #define tx_x2_status0_IDriver_Options_v1010mV 7 15598 #define tx_x2_status0_IDriver_Options_v1040mV 8 15599 #define tx_x2_status0_IDriver_Options_v1060mV 9 15600 #define tx_x2_status0_IDriver_Options_v1070mV 10 15601 #define tx_x2_status0_IDriver_Options_v1080mV 11 15602 #define tx_x2_status0_IDriver_Options_v1085mV 12 15603 #define tx_x2_status0_IDriver_Options_v1090mV 13 15604 #define tx_x2_status0_IDriver_Options_v1095mV 14 15605 #define tx_x2_status0_IDriver_Options_v1100mV 15 15606 15607 /**************************************************************************** 15608 * Enums: tx_x2_status0_operationModes 15609 */ 15610 #define tx_x2_status0_operationModes_XGXS 0 15611 #define tx_x2_status0_operationModes_XGXG_nCC 1 15612 #define tx_x2_status0_operationModes_Indlane_OS8 4 15613 #define tx_x2_status0_operationModes_IndLane_OS5 5 15614 #define tx_x2_status0_operationModes_PCI 7 15615 #define tx_x2_status0_operationModes_XGXS_nLQ 8 15616 #define tx_x2_status0_operationModes_XGXS_nLQnCC 9 15617 #define tx_x2_status0_operationModes_PBypass 10 15618 #define tx_x2_status0_operationModes_PBypass_nDSK 11 15619 #define tx_x2_status0_operationModes_ComboCoreMode 12 15620 #define tx_x2_status0_operationModes_Clocks_off 15 15621 15622 /**************************************************************************** 15623 * Enums: tx_x2_status0_actualSpeeds 15624 */ 15625 #define tx_x2_status0_actualSpeeds_dr_10M 0 15626 #define tx_x2_status0_actualSpeeds_dr_100M 1 15627 #define tx_x2_status0_actualSpeeds_dr_1G 2 15628 #define tx_x2_status0_actualSpeeds_dr_2p5G 3 15629 #define tx_x2_status0_actualSpeeds_dr_5G_X4 4 15630 #define tx_x2_status0_actualSpeeds_dr_6G_X4 5 15631 #define tx_x2_status0_actualSpeeds_dr_10G_HiG 6 15632 #define tx_x2_status0_actualSpeeds_dr_10G_CX4 7 15633 #define tx_x2_status0_actualSpeeds_dr_12G_HiG 8 15634 #define tx_x2_status0_actualSpeeds_dr_12p5G_X4 9 15635 #define tx_x2_status0_actualSpeeds_dr_13G_X4 10 15636 #define tx_x2_status0_actualSpeeds_dr_15G_X4 11 15637 #define tx_x2_status0_actualSpeeds_dr_16G_X4 12 15638 #define tx_x2_status0_actualSpeeds_dr_1G_KX 13 15639 #define tx_x2_status0_actualSpeeds_dr_10G_KX4 14 15640 #define tx_x2_status0_actualSpeeds_dr_10G_KR 15 15641 #define tx_x2_status0_actualSpeeds_dr_5G 16 15642 #define tx_x2_status0_actualSpeeds_dr_6p4G 17 15643 #define tx_x2_status0_actualSpeeds_dr_20G_X4 18 15644 #define tx_x2_status0_actualSpeeds_dr_21G_X4 19 15645 #define tx_x2_status0_actualSpeeds_dr_25G_X4 20 15646 #define tx_x2_status0_actualSpeeds_dr_10G_HiG_DXGXS 21 15647 #define tx_x2_status0_actualSpeeds_dr_10G_DXGXS 22 15648 #define tx_x2_status0_actualSpeeds_dr_10p5G_HiG_DXGXS 23 15649 #define tx_x2_status0_actualSpeeds_dr_10p5G_DXGXS 24 15650 #define tx_x2_status0_actualSpeeds_dr_12p773G_HiG_DXGXS 25 15651 #define tx_x2_status0_actualSpeeds_dr_12p773G_DXGXS 26 15652 #define tx_x2_status0_actualSpeeds_dr_10G_XFI 27 15653 #define tx_x2_status0_actualSpeeds_dr_40G 28 15654 #define tx_x2_status0_actualSpeeds_dr_20G_HiG_DXGXS 29 15655 #define tx_x2_status0_actualSpeeds_dr_20G_DXGXS 30 15656 #define tx_x2_status0_actualSpeeds_dr_10G_SFI 31 15657 #define tx_x2_status0_actualSpeeds_dr_31p5G 32 15658 #define tx_x2_status0_actualSpeeds_dr_32p7G 33 15659 #define tx_x2_status0_actualSpeeds_dr_20G_SCR 34 15660 #define tx_x2_status0_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 15661 #define tx_x2_status0_actualSpeeds_dr_10G_DXGXS_SCR 36 15662 #define tx_x2_status0_actualSpeeds_dr_12G_R2 37 15663 #define tx_x2_status0_actualSpeeds_dr_10G_X2 38 15664 #define tx_x2_status0_actualSpeeds_dr_40G_KR4 39 15665 #define tx_x2_status0_actualSpeeds_dr_40G_CR4 40 15666 #define tx_x2_status0_actualSpeeds_dr_100G_CR10 41 15667 #define tx_x2_status0_actualSpeeds_dr_15p75G_DXGXS 44 15668 #define tx_x2_status0_actualSpeeds_dr_20G_KR2 57 15669 #define tx_x2_status0_actualSpeeds_dr_20G_CR2 58 15670 15671 /**************************************************************************** 15672 * Enums: tx_x2_status0_actualSpeedsMisc1 15673 */ 15674 #define tx_x2_status0_actualSpeedsMisc1_dr_2500BRCM_X1 16 15675 #define tx_x2_status0_actualSpeedsMisc1_dr_5000BRCM_X4 17 15676 #define tx_x2_status0_actualSpeedsMisc1_dr_6000BRCM_X4 18 15677 #define tx_x2_status0_actualSpeedsMisc1_dr_10GHiGig_X4 19 15678 #define tx_x2_status0_actualSpeedsMisc1_dr_10GBASE_CX4 20 15679 #define tx_x2_status0_actualSpeedsMisc1_dr_12GHiGig_X4 21 15680 #define tx_x2_status0_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 15681 #define tx_x2_status0_actualSpeedsMisc1_dr_13GHiGig_X4 23 15682 #define tx_x2_status0_actualSpeedsMisc1_dr_15GHiGig_X4 24 15683 #define tx_x2_status0_actualSpeedsMisc1_dr_16GHiGig_X4 25 15684 #define tx_x2_status0_actualSpeedsMisc1_dr_5000BRCM_X1 26 15685 #define tx_x2_status0_actualSpeedsMisc1_dr_6363BRCM_X1 27 15686 #define tx_x2_status0_actualSpeedsMisc1_dr_20GHiGig_X4 28 15687 #define tx_x2_status0_actualSpeedsMisc1_dr_21GHiGig_X4 29 15688 #define tx_x2_status0_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 15689 #define tx_x2_status0_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 15690 15691 /**************************************************************************** 15692 * Enums: tx_x2_status0_IndLaneModes 15693 */ 15694 #define tx_x2_status0_IndLaneModes_SWSDR_div2 0 15695 #define tx_x2_status0_IndLaneModes_SWSDR_div1 1 15696 #define tx_x2_status0_IndLaneModes_DWSDR_div2 2 15697 #define tx_x2_status0_IndLaneModes_DWSDR_div1 3 15698 15699 /**************************************************************************** 15700 * Enums: tx_x2_status0_prbsSelect 15701 */ 15702 #define tx_x2_status0_prbsSelect_prbs7 0 15703 #define tx_x2_status0_prbsSelect_prbs15 1 15704 #define tx_x2_status0_prbsSelect_prbs23 2 15705 #define tx_x2_status0_prbsSelect_prbs31 3 15706 15707 /**************************************************************************** 15708 * Enums: tx_x2_status0_vcoDivider 15709 */ 15710 #define tx_x2_status0_vcoDivider_div32 0 15711 #define tx_x2_status0_vcoDivider_div36 1 15712 #define tx_x2_status0_vcoDivider_div40 2 15713 #define tx_x2_status0_vcoDivider_div42 3 15714 #define tx_x2_status0_vcoDivider_div48 4 15715 #define tx_x2_status0_vcoDivider_div50 5 15716 #define tx_x2_status0_vcoDivider_div52 6 15717 #define tx_x2_status0_vcoDivider_div54 7 15718 #define tx_x2_status0_vcoDivider_div60 8 15719 #define tx_x2_status0_vcoDivider_div64 9 15720 #define tx_x2_status0_vcoDivider_div66 10 15721 #define tx_x2_status0_vcoDivider_div68 11 15722 #define tx_x2_status0_vcoDivider_div70 12 15723 #define tx_x2_status0_vcoDivider_div80 13 15724 #define tx_x2_status0_vcoDivider_div92 14 15725 #define tx_x2_status0_vcoDivider_div100 15 15726 15727 /**************************************************************************** 15728 * Enums: tx_x2_status0_refClkSelect 15729 */ 15730 #define tx_x2_status0_refClkSelect_clk_25MHz 0 15731 #define tx_x2_status0_refClkSelect_clk_100MHz 1 15732 #define tx_x2_status0_refClkSelect_clk_125MHz 2 15733 #define tx_x2_status0_refClkSelect_clk_156p25MHz 3 15734 #define tx_x2_status0_refClkSelect_clk_187p5MHz 4 15735 #define tx_x2_status0_refClkSelect_clk_161p25Mhz 5 15736 #define tx_x2_status0_refClkSelect_clk_50Mhz 6 15737 #define tx_x2_status0_refClkSelect_clk_106p25Mhz 7 15738 15739 /**************************************************************************** 15740 * Enums: tx_x2_status0_aerMMDdevTypeSelect 15741 */ 15742 #define tx_x2_status0_aerMMDdevTypeSelect_combo_core 0 15743 #define tx_x2_status0_aerMMDdevTypeSelect_PMA_PMD 1 15744 #define tx_x2_status0_aerMMDdevTypeSelect_PCS 3 15745 #define tx_x2_status0_aerMMDdevTypeSelect_PHY 4 15746 #define tx_x2_status0_aerMMDdevTypeSelect_DTE 5 15747 #define tx_x2_status0_aerMMDdevTypeSelect_CL73_AN 7 15748 15749 /**************************************************************************** 15750 * Enums: tx_x2_status0_aerMMDportSelect 15751 */ 15752 #define tx_x2_status0_aerMMDportSelect_ln0 0 15753 #define tx_x2_status0_aerMMDportSelect_ln1 1 15754 #define tx_x2_status0_aerMMDportSelect_ln2 2 15755 #define tx_x2_status0_aerMMDportSelect_ln3 3 15756 #define tx_x2_status0_aerMMDportSelect_BCST_ln0_1_2_3 511 15757 #define tx_x2_status0_aerMMDportSelect_BCST_ln0_1 512 15758 #define tx_x2_status0_aerMMDportSelect_BCST_ln2_3 513 15759 15760 /**************************************************************************** 15761 * Enums: tx_x2_status0_firmwareModeSelect 15762 */ 15763 #define tx_x2_status0_firmwareModeSelect_DEFAULT 0 15764 #define tx_x2_status0_firmwareModeSelect_SFP_OPT_LR 1 15765 #define tx_x2_status0_firmwareModeSelect_SFP_DAC 2 15766 #define tx_x2_status0_firmwareModeSelect_XLAUI 3 15767 #define tx_x2_status0_firmwareModeSelect_LONG_CH_6G 4 15768 15769 /**************************************************************************** 15770 * Enums: tx_x2_status0_tempIdxSelect 15771 */ 15772 #define tx_x2_status0_tempIdxSelect_LTE__22p9C 15 15773 #define tx_x2_status0_tempIdxSelect_LTE__12p6C 14 15774 #define tx_x2_status0_tempIdxSelect_LTE__3p0C 13 15775 #define tx_x2_status0_tempIdxSelect_LTE_6p7C 12 15776 #define tx_x2_status0_tempIdxSelect_LTE_16p4C 11 15777 #define tx_x2_status0_tempIdxSelect_LTE_26p6C 10 15778 #define tx_x2_status0_tempIdxSelect_LTE_36p3C 9 15779 #define tx_x2_status0_tempIdxSelect_LTE_46p0C 8 15780 #define tx_x2_status0_tempIdxSelect_LTE_56p2C 7 15781 #define tx_x2_status0_tempIdxSelect_LTE_65p9C 6 15782 #define tx_x2_status0_tempIdxSelect_LTE_75p6C 5 15783 #define tx_x2_status0_tempIdxSelect_LTE_85p3C 4 15784 #define tx_x2_status0_tempIdxSelect_LTE_95p5C 3 15785 #define tx_x2_status0_tempIdxSelect_LTE_105p2C 2 15786 #define tx_x2_status0_tempIdxSelect_LTE_114p9C 1 15787 #define tx_x2_status0_tempIdxSelect_LTE_125p1C 0 15788 15789 /**************************************************************************** 15790 * Enums: tx_x2_status0_port_mode 15791 */ 15792 #define tx_x2_status0_port_mode_QUAD_PORT 0 15793 #define tx_x2_status0_port_mode_TRI_1_PORT 1 15794 #define tx_x2_status0_port_mode_TRI_2_PORT 2 15795 #define tx_x2_status0_port_mode_DUAL_PORT 3 15796 #define tx_x2_status0_port_mode_SINGLE_PORT 4 15797 15798 /**************************************************************************** 15799 * Enums: tx_x2_status0_rev_letter_enum 15800 */ 15801 #define tx_x2_status0_rev_letter_enum_REV_A 0 15802 #define tx_x2_status0_rev_letter_enum_REV_B 1 15803 #define tx_x2_status0_rev_letter_enum_REV_C 2 15804 #define tx_x2_status0_rev_letter_enum_REV_D 3 15805 15806 /**************************************************************************** 15807 * Enums: tx_x2_status0_rev_number_enum 15808 */ 15809 #define tx_x2_status0_rev_number_enum_REV_0 0 15810 #define tx_x2_status0_rev_number_enum_REV_1 1 15811 #define tx_x2_status0_rev_number_enum_REV_2 2 15812 #define tx_x2_status0_rev_number_enum_REV_3 3 15813 #define tx_x2_status0_rev_number_enum_REV_4 4 15814 #define tx_x2_status0_rev_number_enum_REV_5 5 15815 #define tx_x2_status0_rev_number_enum_REV_6 6 15816 #define tx_x2_status0_rev_number_enum_REV_7 7 15817 15818 /**************************************************************************** 15819 * Enums: tx_x2_status0_bonding_enum 15820 */ 15821 #define tx_x2_status0_bonding_enum_WIRE_BOND 0 15822 #define tx_x2_status0_bonding_enum_FLIP_CHIP 1 15823 15824 /**************************************************************************** 15825 * Enums: tx_x2_status0_tech_process 15826 */ 15827 #define tx_x2_status0_tech_process_PROCESS_90NM 0 15828 #define tx_x2_status0_tech_process_PROCESS_65NM 1 15829 #define tx_x2_status0_tech_process_PROCESS_40NM 2 15830 #define tx_x2_status0_tech_process_PROCESS_28NM 3 15831 15832 /**************************************************************************** 15833 * Enums: tx_x2_status0_model_num 15834 */ 15835 #define tx_x2_status0_model_num_SERDES_CL73 0 15836 #define tx_x2_status0_model_num_XGXS_16G 1 15837 #define tx_x2_status0_model_num_HYPERCORE 2 15838 #define tx_x2_status0_model_num_HYPERLITE 3 15839 #define tx_x2_status0_model_num_PCIE_G2_PIPE 4 15840 #define tx_x2_status0_model_num_SERDES_1p25GBd 5 15841 #define tx_x2_status0_model_num_SATA2 6 15842 #define tx_x2_status0_model_num_QSGMII 7 15843 #define tx_x2_status0_model_num_XGXS10G 8 15844 #define tx_x2_status0_model_num_WARPCORE 9 15845 #define tx_x2_status0_model_num_XFICORE 10 15846 #define tx_x2_status0_model_num_RXFI 11 15847 #define tx_x2_status0_model_num_WARPLITE 12 15848 #define tx_x2_status0_model_num_PENTACORE 13 15849 #define tx_x2_status0_model_num_ESM 14 15850 #define tx_x2_status0_model_num_QUAD_SGMII 15 15851 #define tx_x2_status0_model_num_WARPCORE_3 16 15852 #define tx_x2_status0_model_num_TSC 17 15853 #define tx_x2_status0_model_num_TSC4E 18 15854 #define tx_x2_status0_model_num_TSC12E 19 15855 #define tx_x2_status0_model_num_TSC4F 20 15856 #define tx_x2_status0_model_num_XGXS_CL73_90NM 29 15857 #define tx_x2_status0_model_num_SERDES_CL73_90NM 30 15858 #define tx_x2_status0_model_num_WARPCORE3 32 15859 #define tx_x2_status0_model_num_WARPCORE4_TSC 33 15860 #define tx_x2_status0_model_num_RXAUI 34 15861 15862 /**************************************************************************** 15863 * Enums: tx_x2_status0_payload 15864 */ 15865 #define tx_x2_status0_payload_REPEAT_2_BYTES 0 15866 #define tx_x2_status0_payload_RAMPING 1 15867 #define tx_x2_status0_payload_CL48_CRPAT 2 15868 #define tx_x2_status0_payload_CL48_CJPAT 3 15869 #define tx_x2_status0_payload_CL36_LONG_CRPAT 4 15870 #define tx_x2_status0_payload_CL36_SHORT_CRPAT 5 15871 15872 /**************************************************************************** 15873 * Enums: tx_x2_status0_sc 15874 */ 15875 #define tx_x2_status0_sc_S_10G_CR1 0 15876 #define tx_x2_status0_sc_S_10G_KR1 1 15877 #define tx_x2_status0_sc_S_10G_X1 2 15878 #define tx_x2_status0_sc_S_10G_HG2_CR1 4 15879 #define tx_x2_status0_sc_S_10G_HG2_KR1 5 15880 #define tx_x2_status0_sc_S_10G_HG2_X1 6 15881 #define tx_x2_status0_sc_S_20G_CR1 8 15882 #define tx_x2_status0_sc_S_20G_KR1 9 15883 #define tx_x2_status0_sc_S_20G_X1 10 15884 #define tx_x2_status0_sc_S_20G_HG2_CR1 12 15885 #define tx_x2_status0_sc_S_20G_HG2_KR1 13 15886 #define tx_x2_status0_sc_S_20G_HG2_X1 14 15887 #define tx_x2_status0_sc_S_25G_CR1 16 15888 #define tx_x2_status0_sc_S_25G_KR1 17 15889 #define tx_x2_status0_sc_S_25G_X1 18 15890 #define tx_x2_status0_sc_S_25G_HG2_CR1 20 15891 #define tx_x2_status0_sc_S_25G_HG2_KR1 21 15892 #define tx_x2_status0_sc_S_25G_HG2_X1 22 15893 #define tx_x2_status0_sc_S_20G_CR2 24 15894 #define tx_x2_status0_sc_S_20G_KR2 25 15895 #define tx_x2_status0_sc_S_20G_X2 26 15896 #define tx_x2_status0_sc_S_20G_HG2_CR2 28 15897 #define tx_x2_status0_sc_S_20G_HG2_KR2 29 15898 #define tx_x2_status0_sc_S_20G_HG2_X2 30 15899 #define tx_x2_status0_sc_S_40G_CR2 32 15900 #define tx_x2_status0_sc_S_40G_KR2 33 15901 #define tx_x2_status0_sc_S_40G_X2 34 15902 #define tx_x2_status0_sc_S_40G_HG2_CR2 36 15903 #define tx_x2_status0_sc_S_40G_HG2_KR2 37 15904 #define tx_x2_status0_sc_S_40G_HG2_X2 38 15905 #define tx_x2_status0_sc_S_40G_CR4 40 15906 #define tx_x2_status0_sc_S_40G_KR4 41 15907 #define tx_x2_status0_sc_S_40G_X4 42 15908 #define tx_x2_status0_sc_S_40G_HG2_CR4 44 15909 #define tx_x2_status0_sc_S_40G_HG2_KR4 45 15910 #define tx_x2_status0_sc_S_40G_HG2_X4 46 15911 #define tx_x2_status0_sc_S_50G_CR2 48 15912 #define tx_x2_status0_sc_S_50G_KR2 49 15913 #define tx_x2_status0_sc_S_50G_X2 50 15914 #define tx_x2_status0_sc_S_50G_HG2_CR2 52 15915 #define tx_x2_status0_sc_S_50G_HG2_KR2 53 15916 #define tx_x2_status0_sc_S_50G_HG2_X2 54 15917 #define tx_x2_status0_sc_S_50G_CR4 56 15918 #define tx_x2_status0_sc_S_50G_KR4 57 15919 #define tx_x2_status0_sc_S_50G_X4 58 15920 #define tx_x2_status0_sc_S_50G_HG2_CR4 60 15921 #define tx_x2_status0_sc_S_50G_HG2_KR4 61 15922 #define tx_x2_status0_sc_S_50G_HG2_X4 62 15923 #define tx_x2_status0_sc_S_100G_CR4 64 15924 #define tx_x2_status0_sc_S_100G_KR4 65 15925 #define tx_x2_status0_sc_S_100G_X4 66 15926 #define tx_x2_status0_sc_S_100G_HG2_CR4 68 15927 #define tx_x2_status0_sc_S_100G_HG2_KR4 69 15928 #define tx_x2_status0_sc_S_100G_HG2_X4 70 15929 #define tx_x2_status0_sc_S_CL73_20GVCO 72 15930 #define tx_x2_status0_sc_S_CL73_25GVCO 80 15931 #define tx_x2_status0_sc_S_CL36_20GVCO 88 15932 #define tx_x2_status0_sc_S_CL36_25GVCO 96 15933 15934 /**************************************************************************** 15935 * Enums: tx_x2_status0_t_fifo_modes 15936 */ 15937 #define tx_x2_status0_t_fifo_modes_T_FIFO_MODE_BYPASS 0 15938 #define tx_x2_status0_t_fifo_modes_T_FIFO_MODE_40G 1 15939 #define tx_x2_status0_t_fifo_modes_T_FIFO_MODE_100G 2 15940 #define tx_x2_status0_t_fifo_modes_T_FIFO_MODE_20G 3 15941 15942 /**************************************************************************** 15943 * Enums: tx_x2_status0_t_enc_modes 15944 */ 15945 #define tx_x2_status0_t_enc_modes_T_ENC_MODE_BYPASS 0 15946 #define tx_x2_status0_t_enc_modes_T_ENC_MODE_CL49 1 15947 #define tx_x2_status0_t_enc_modes_T_ENC_MODE_CL82 2 15948 15949 /**************************************************************************** 15950 * Enums: tx_x2_status0_btmx_mode 15951 */ 15952 #define tx_x2_status0_btmx_mode_BS_BTMX_MODE_1to1 0 15953 #define tx_x2_status0_btmx_mode_BS_BTMX_MODE_2to1 1 15954 #define tx_x2_status0_btmx_mode_BS_BTMX_MODE_5to1 2 15955 15956 /**************************************************************************** 15957 * Enums: tx_x2_status0_t_type_cl82 15958 */ 15959 #define tx_x2_status0_t_type_cl82_T_TYPE_B1 5 15960 #define tx_x2_status0_t_type_cl82_T_TYPE_C 4 15961 #define tx_x2_status0_t_type_cl82_T_TYPE_S 3 15962 #define tx_x2_status0_t_type_cl82_T_TYPE_T 2 15963 #define tx_x2_status0_t_type_cl82_T_TYPE_D 1 15964 #define tx_x2_status0_t_type_cl82_T_TYPE_E 0 15965 15966 /**************************************************************************** 15967 * Enums: tx_x2_status0_txsm_state_cl82 15968 */ 15969 #define tx_x2_status0_txsm_state_cl82_TX_HIG_END 6 15970 #define tx_x2_status0_txsm_state_cl82_TX_HIG_START 5 15971 #define tx_x2_status0_txsm_state_cl82_TX_E 4 15972 #define tx_x2_status0_txsm_state_cl82_TX_T 3 15973 #define tx_x2_status0_txsm_state_cl82_TX_D 2 15974 #define tx_x2_status0_txsm_state_cl82_TX_C 1 15975 #define tx_x2_status0_txsm_state_cl82_TX_INIT 0 15976 15977 /**************************************************************************** 15978 * Enums: tx_x2_status0_ltxsm_state_cl82 15979 */ 15980 #define tx_x2_status0_ltxsm_state_cl82_TX_HIG_END 64 15981 #define tx_x2_status0_ltxsm_state_cl82_TX_HIG_START 32 15982 #define tx_x2_status0_ltxsm_state_cl82_TX_E 16 15983 #define tx_x2_status0_ltxsm_state_cl82_TX_T 8 15984 #define tx_x2_status0_ltxsm_state_cl82_TX_D 4 15985 #define tx_x2_status0_ltxsm_state_cl82_TX_C 2 15986 #define tx_x2_status0_ltxsm_state_cl82_TX_INIT 1 15987 15988 /**************************************************************************** 15989 * Enums: tx_x2_status0_r_type_coded_cl82 15990 */ 15991 #define tx_x2_status0_r_type_coded_cl82_R_TYPE_B1 32 15992 #define tx_x2_status0_r_type_coded_cl82_R_TYPE_C 16 15993 #define tx_x2_status0_r_type_coded_cl82_R_TYPE_S 8 15994 #define tx_x2_status0_r_type_coded_cl82_R_TYPE_T 4 15995 #define tx_x2_status0_r_type_coded_cl82_R_TYPE_D 2 15996 #define tx_x2_status0_r_type_coded_cl82_R_TYPE_E 1 15997 15998 /**************************************************************************** 15999 * Enums: tx_x2_status0_rxsm_state_cl82 16000 */ 16001 #define tx_x2_status0_rxsm_state_cl82_RX_HIG_END 64 16002 #define tx_x2_status0_rxsm_state_cl82_RX_HIG_START 32 16003 #define tx_x2_status0_rxsm_state_cl82_RX_E 16 16004 #define tx_x2_status0_rxsm_state_cl82_RX_T 8 16005 #define tx_x2_status0_rxsm_state_cl82_RX_D 4 16006 #define tx_x2_status0_rxsm_state_cl82_RX_C 2 16007 #define tx_x2_status0_rxsm_state_cl82_RX_INIT 1 16008 16009 /**************************************************************************** 16010 * Enums: tx_x2_status0_deskew_state 16011 */ 16012 #define tx_x2_status0_deskew_state_ALIGN_ACQUIRED 2 16013 #define tx_x2_status0_deskew_state_LOSS_OF_ALIGNMENT 1 16014 16015 /**************************************************************************** 16016 * Enums: tx_x2_status0_os_mode_enum 16017 */ 16018 #define tx_x2_status0_os_mode_enum_OS_MODE_1 0 16019 #define tx_x2_status0_os_mode_enum_OS_MODE_2 1 16020 #define tx_x2_status0_os_mode_enum_OS_MODE_4 2 16021 #define tx_x2_status0_os_mode_enum_OS_MODE_16p5 8 16022 #define tx_x2_status0_os_mode_enum_OS_MODE_20p625 12 16023 16024 /**************************************************************************** 16025 * Enums: tx_x2_status0_scr_modes 16026 */ 16027 #define tx_x2_status0_scr_modes_T_SCR_MODE_BYPASS 0 16028 #define tx_x2_status0_scr_modes_T_SCR_MODE_CL49 1 16029 #define tx_x2_status0_scr_modes_T_SCR_MODE_40G_2_LANE 2 16030 #define tx_x2_status0_scr_modes_T_SCR_MODE_100G 3 16031 #define tx_x2_status0_scr_modes_T_SCR_MODE_20G 4 16032 #define tx_x2_status0_scr_modes_T_SCR_MODE_40G_4_LANE 5 16033 16034 /**************************************************************************** 16035 * Enums: tx_x2_status0_descr_modes 16036 */ 16037 #define tx_x2_status0_descr_modes_R_DESCR_MODE_BYPASS 0 16038 #define tx_x2_status0_descr_modes_R_DESCR_MODE_CL49 1 16039 #define tx_x2_status0_descr_modes_R_DESCR_MODE_CL82 2 16040 16041 /**************************************************************************** 16042 * Enums: tx_x2_status0_r_dec_tl_mode 16043 */ 16044 #define tx_x2_status0_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 16045 #define tx_x2_status0_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 16046 #define tx_x2_status0_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 16047 16048 /**************************************************************************** 16049 * Enums: tx_x2_status0_r_dec_fsm_mode 16050 */ 16051 #define tx_x2_status0_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 16052 #define tx_x2_status0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 16053 #define tx_x2_status0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 16054 16055 /**************************************************************************** 16056 * Enums: tx_x2_status0_r_deskew_mode 16057 */ 16058 #define tx_x2_status0_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 16059 #define tx_x2_status0_r_deskew_mode_R_DESKEW_MODE_20G 1 16060 #define tx_x2_status0_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 16061 #define tx_x2_status0_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 16062 #define tx_x2_status0_r_deskew_mode_R_DESKEW_MODE_100G 4 16063 #define tx_x2_status0_r_deskew_mode_R_DESKEW_MODE_CL49 5 16064 #define tx_x2_status0_r_deskew_mode_R_DESKEW_MODE_CL91 6 16065 16066 /**************************************************************************** 16067 * Enums: tx_x2_status0_bs_dist_modes 16068 */ 16069 #define tx_x2_status0_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 16070 #define tx_x2_status0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 16071 #define tx_x2_status0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 16072 #define tx_x2_status0_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 16073 16074 /**************************************************************************** 16075 * Enums: tx_x2_status0_cl49_t_type 16076 */ 16077 #define tx_x2_status0_cl49_t_type_BAD_T_TYPE 15 16078 #define tx_x2_status0_cl49_t_type_T_TYPE_B0 11 16079 #define tx_x2_status0_cl49_t_type_T_TYPE_OB 10 16080 #define tx_x2_status0_cl49_t_type_T_TYPE_B1 9 16081 #define tx_x2_status0_cl49_t_type_T_TYPE_DB 8 16082 #define tx_x2_status0_cl49_t_type_T_TYPE_FC 7 16083 #define tx_x2_status0_cl49_t_type_T_TYPE_TB 6 16084 #define tx_x2_status0_cl49_t_type_T_TYPE_LI 5 16085 #define tx_x2_status0_cl49_t_type_T_TYPE_C 4 16086 #define tx_x2_status0_cl49_t_type_T_TYPE_S 3 16087 #define tx_x2_status0_cl49_t_type_T_TYPE_T 2 16088 #define tx_x2_status0_cl49_t_type_T_TYPE_D 1 16089 #define tx_x2_status0_cl49_t_type_T_TYPE_E 0 16090 16091 /**************************************************************************** 16092 * Enums: tx_x2_status0_cl49_txsm_states 16093 */ 16094 #define tx_x2_status0_cl49_txsm_states_TX_HIG_END 7 16095 #define tx_x2_status0_cl49_txsm_states_TX_HIG_START 6 16096 #define tx_x2_status0_cl49_txsm_states_TX_LI 5 16097 #define tx_x2_status0_cl49_txsm_states_TX_E 4 16098 #define tx_x2_status0_cl49_txsm_states_TX_T 3 16099 #define tx_x2_status0_cl49_txsm_states_TX_D 2 16100 #define tx_x2_status0_cl49_txsm_states_TX_C 1 16101 #define tx_x2_status0_cl49_txsm_states_TX_INIT 0 16102 16103 /**************************************************************************** 16104 * Enums: tx_x2_status0_cl49_ltxsm_states 16105 */ 16106 #define tx_x2_status0_cl49_ltxsm_states_TX_HIG_END 128 16107 #define tx_x2_status0_cl49_ltxsm_states_TX_HIG_START 64 16108 #define tx_x2_status0_cl49_ltxsm_states_TX_LI 32 16109 #define tx_x2_status0_cl49_ltxsm_states_TX_E 16 16110 #define tx_x2_status0_cl49_ltxsm_states_TX_T 8 16111 #define tx_x2_status0_cl49_ltxsm_states_TX_D 4 16112 #define tx_x2_status0_cl49_ltxsm_states_TX_C 2 16113 #define tx_x2_status0_cl49_ltxsm_states_TX_INIT 1 16114 16115 /**************************************************************************** 16116 * Enums: tx_x2_status0_burst_error_mode 16117 */ 16118 #define tx_x2_status0_burst_error_mode_BURST_ERROR_11_BITS 0 16119 #define tx_x2_status0_burst_error_mode_BURST_ERROR_16_BITS 1 16120 #define tx_x2_status0_burst_error_mode_BURST_ERROR_17_BITS 2 16121 #define tx_x2_status0_burst_error_mode_BURST_ERROR_18_BITS 3 16122 #define tx_x2_status0_burst_error_mode_BURST_ERROR_19_BITS 4 16123 #define tx_x2_status0_burst_error_mode_BURST_ERROR_20_BITS 5 16124 #define tx_x2_status0_burst_error_mode_BURST_ERROR_21_BITS 6 16125 #define tx_x2_status0_burst_error_mode_BURST_ERROR_22_BITS 7 16126 #define tx_x2_status0_burst_error_mode_BURST_ERROR_23_BITS 8 16127 #define tx_x2_status0_burst_error_mode_BURST_ERROR_24_BITS 9 16128 #define tx_x2_status0_burst_error_mode_BURST_ERROR_25_BITS 10 16129 #define tx_x2_status0_burst_error_mode_BURST_ERROR_26_BITS 11 16130 #define tx_x2_status0_burst_error_mode_BURST_ERROR_27_BITS 12 16131 #define tx_x2_status0_burst_error_mode_BURST_ERROR_28_BITS 13 16132 #define tx_x2_status0_burst_error_mode_BURST_ERROR_29_BITS 14 16133 #define tx_x2_status0_burst_error_mode_BURST_ERROR_30_BITS 15 16134 #define tx_x2_status0_burst_error_mode_BURST_ERROR_31_BITS 16 16135 #define tx_x2_status0_burst_error_mode_BURST_ERROR_32_BITS 17 16136 #define tx_x2_status0_burst_error_mode_BURST_ERROR_33_BITS 18 16137 #define tx_x2_status0_burst_error_mode_BURST_ERROR_34_BITS 19 16138 #define tx_x2_status0_burst_error_mode_BURST_ERROR_35_BITS 20 16139 #define tx_x2_status0_burst_error_mode_BURST_ERROR_36_BITS 21 16140 #define tx_x2_status0_burst_error_mode_BURST_ERROR_37_BITS 22 16141 #define tx_x2_status0_burst_error_mode_BURST_ERROR_38_BITS 23 16142 #define tx_x2_status0_burst_error_mode_BURST_ERROR_39_BITS 24 16143 #define tx_x2_status0_burst_error_mode_BURST_ERROR_40_BITS 25 16144 #define tx_x2_status0_burst_error_mode_BURST_ERROR_41_BITS 26 16145 16146 /**************************************************************************** 16147 * Enums: tx_x2_status0_bermon_state 16148 */ 16149 #define tx_x2_status0_bermon_state_HI_BER 4 16150 #define tx_x2_status0_bermon_state_GOOD_BER 3 16151 #define tx_x2_status0_bermon_state_BER_TEST_SH 2 16152 #define tx_x2_status0_bermon_state_START_TIMER 1 16153 #define tx_x2_status0_bermon_state_BER_MT_INIT 0 16154 16155 /**************************************************************************** 16156 * Enums: tx_x2_status0_rxsm_state_cl49 16157 */ 16158 #define tx_x2_status0_rxsm_state_cl49_RX_HIG_END 128 16159 #define tx_x2_status0_rxsm_state_cl49_RX_HIG_START 64 16160 #define tx_x2_status0_rxsm_state_cl49_RX_LI 32 16161 #define tx_x2_status0_rxsm_state_cl49_RX_E 16 16162 #define tx_x2_status0_rxsm_state_cl49_RX_T 8 16163 #define tx_x2_status0_rxsm_state_cl49_RX_D 4 16164 #define tx_x2_status0_rxsm_state_cl49_RX_C 2 16165 #define tx_x2_status0_rxsm_state_cl49_RX_INIT 1 16166 16167 /**************************************************************************** 16168 * Enums: tx_x2_status0_r_type 16169 */ 16170 #define tx_x2_status0_r_type_BAD_R_TYPE 15 16171 #define tx_x2_status0_r_type_R_TYPE_B0 11 16172 #define tx_x2_status0_r_type_R_TYPE_OB 10 16173 #define tx_x2_status0_r_type_R_TYPE_B1 9 16174 #define tx_x2_status0_r_type_R_TYPE_DB 8 16175 #define tx_x2_status0_r_type_R_TYPE_FC 7 16176 #define tx_x2_status0_r_type_R_TYPE_TB 6 16177 #define tx_x2_status0_r_type_R_TYPE_LI 5 16178 #define tx_x2_status0_r_type_R_TYPE_C 4 16179 #define tx_x2_status0_r_type_R_TYPE_S 3 16180 #define tx_x2_status0_r_type_R_TYPE_T 2 16181 #define tx_x2_status0_r_type_R_TYPE_D 1 16182 #define tx_x2_status0_r_type_R_TYPE_E 0 16183 16184 /**************************************************************************** 16185 * Enums: tx_x2_status0_am_lock_state 16186 */ 16187 #define tx_x2_status0_am_lock_state_INVALID_AM 512 16188 #define tx_x2_status0_am_lock_state_GOOD_AM 256 16189 #define tx_x2_status0_am_lock_state_COMP_AM 128 16190 #define tx_x2_status0_am_lock_state_TIMER_2 64 16191 #define tx_x2_status0_am_lock_state_AM_2_GOOD 32 16192 #define tx_x2_status0_am_lock_state_COMP_2ND 16 16193 #define tx_x2_status0_am_lock_state_TIMER_1 8 16194 #define tx_x2_status0_am_lock_state_FIND_1ST 4 16195 #define tx_x2_status0_am_lock_state_AM_RESET_CNT 2 16196 #define tx_x2_status0_am_lock_state_AM_LOCK_INIT 1 16197 16198 /**************************************************************************** 16199 * Enums: tx_x2_status0_msg_selector 16200 */ 16201 #define tx_x2_status0_msg_selector_RESERVED 0 16202 #define tx_x2_status0_msg_selector_VALUE_802p3 1 16203 #define tx_x2_status0_msg_selector_VALUE_802p9 2 16204 #define tx_x2_status0_msg_selector_VALUE_802p5 3 16205 #define tx_x2_status0_msg_selector_VALUE_1394 4 16206 16207 /**************************************************************************** 16208 * Enums: tx_x2_status0_synce_enum 16209 */ 16210 #define tx_x2_status0_synce_enum_SYNCE_NO_DIV 0 16211 #define tx_x2_status0_synce_enum_SYNCE_DIV_7 1 16212 #define tx_x2_status0_synce_enum_SYNCE_DIV_11 2 16213 16214 /**************************************************************************** 16215 * Enums: tx_x2_status0_synce_enum_stage0 16216 */ 16217 #define tx_x2_status0_synce_enum_stage0_SYNCE_NO_DIV 0 16218 #define tx_x2_status0_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 16219 #define tx_x2_status0_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 16220 16221 /**************************************************************************** 16222 * Enums: tx_x2_status0_cl91_sync_state 16223 */ 16224 #define tx_x2_status0_cl91_sync_state_FIND_1ST 0 16225 #define tx_x2_status0_cl91_sync_state_COUNT_NEXT 1 16226 #define tx_x2_status0_cl91_sync_state_COMP_2ND 2 16227 #define tx_x2_status0_cl91_sync_state_TWO_GOOD 3 16228 16229 /**************************************************************************** 16230 * Enums: tx_x2_status0_cl91_algn_state 16231 */ 16232 #define tx_x2_status0_cl91_algn_state_LOSS_OF_ALIGNMENT 0 16233 #define tx_x2_status0_cl91_algn_state_DESKEW 1 16234 #define tx_x2_status0_cl91_algn_state_DESKEW_FAIL 2 16235 #define tx_x2_status0_cl91_algn_state_ALIGN_ACQUIRED 3 16236 #define tx_x2_status0_cl91_algn_state_CW_GOOD 4 16237 #define tx_x2_status0_cl91_algn_state_CW_BAD 5 16238 #define tx_x2_status0_cl91_algn_state_THREE_BAD 6 16239 16240 /**************************************************************************** 16241 * Enums: tx_x2_status0_fec_sel 16242 */ 16243 #define tx_x2_status0_fec_sel_NO_FEC 0 16244 #define tx_x2_status0_fec_sel_FEC_CL74 1 16245 #define tx_x2_status0_fec_sel_FEC_CL91 2 16246 16247 /**************************************************************************** 16248 * Enums: tx_x4_control0_cl36TxEEEStates_l 16249 */ 16250 #define tx_x4_control0_cl36TxEEEStates_l_TX_REFRESH 8 16251 #define tx_x4_control0_cl36TxEEEStates_l_TX_QUIET 4 16252 #define tx_x4_control0_cl36TxEEEStates_l_TX_SLEEP 2 16253 #define tx_x4_control0_cl36TxEEEStates_l_TX_ACTIVE 1 16254 16255 /**************************************************************************** 16256 * Enums: tx_x4_control0_cl36TxEEEStates_c 16257 */ 16258 #define tx_x4_control0_cl36TxEEEStates_c_TX_REFRESH 3 16259 #define tx_x4_control0_cl36TxEEEStates_c_TX_QUIET 2 16260 #define tx_x4_control0_cl36TxEEEStates_c_TX_SLEEP 1 16261 #define tx_x4_control0_cl36TxEEEStates_c_TX_ACTIVE 0 16262 16263 /**************************************************************************** 16264 * Enums: tx_x4_control0_cl49TxEEEStates_l 16265 */ 16266 #define tx_x4_control0_cl49TxEEEStates_l_SCR_RESET_2 64 16267 #define tx_x4_control0_cl49TxEEEStates_l_SCR_RESET_1 32 16268 #define tx_x4_control0_cl49TxEEEStates_l_TX_WAKE 16 16269 #define tx_x4_control0_cl49TxEEEStates_l_TX_REFRESH 8 16270 #define tx_x4_control0_cl49TxEEEStates_l_TX_QUIET 4 16271 #define tx_x4_control0_cl49TxEEEStates_l_TX_SLEEP 2 16272 #define tx_x4_control0_cl49TxEEEStates_l_TX_ACTIVE 1 16273 16274 /**************************************************************************** 16275 * Enums: tx_x4_control0_fec_req_enum 16276 */ 16277 #define tx_x4_control0_fec_req_enum_FEC_not_supported 0 16278 #define tx_x4_control0_fec_req_enum_FEC_supported_but_not_requested 1 16279 #define tx_x4_control0_fec_req_enum_invalid_setting 2 16280 #define tx_x4_control0_fec_req_enum_FEC_supported_and_requested 3 16281 16282 /**************************************************************************** 16283 * Enums: tx_x4_control0_cl73_pause_enum 16284 */ 16285 #define tx_x4_control0_cl73_pause_enum_No_PAUSE_ability 0 16286 #define tx_x4_control0_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 16287 #define tx_x4_control0_cl73_pause_enum_Symmetric_PAUSE_ability 1 16288 #define tx_x4_control0_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 16289 16290 /**************************************************************************** 16291 * Enums: tx_x4_control0_cl49TxEEEStates_c 16292 */ 16293 #define tx_x4_control0_cl49TxEEEStates_c_SCR_RESET_2 6 16294 #define tx_x4_control0_cl49TxEEEStates_c_SCR_RESET_1 5 16295 #define tx_x4_control0_cl49TxEEEStates_c_TX_WAKE 4 16296 #define tx_x4_control0_cl49TxEEEStates_c_TX_REFRESH 3 16297 #define tx_x4_control0_cl49TxEEEStates_c_TX_QUIET 2 16298 #define tx_x4_control0_cl49TxEEEStates_c_TX_SLEEP 1 16299 #define tx_x4_control0_cl49TxEEEStates_c_TX_ACTIVE 0 16300 16301 /**************************************************************************** 16302 * Enums: tx_x4_control0_cl36RxEEEStates_l 16303 */ 16304 #define tx_x4_control0_cl36RxEEEStates_l_RX_LINK_FAIL 32 16305 #define tx_x4_control0_cl36RxEEEStates_l_RX_WTF 16 16306 #define tx_x4_control0_cl36RxEEEStates_l_RX_WAKE 8 16307 #define tx_x4_control0_cl36RxEEEStates_l_RX_QUIET 4 16308 #define tx_x4_control0_cl36RxEEEStates_l_RX_SLEEP 2 16309 #define tx_x4_control0_cl36RxEEEStates_l_RX_ACTIVE 1 16310 16311 /**************************************************************************** 16312 * Enums: tx_x4_control0_cl36RxEEEStates_c 16313 */ 16314 #define tx_x4_control0_cl36RxEEEStates_c_RX_LINK_FAIL 5 16315 #define tx_x4_control0_cl36RxEEEStates_c_RX_WTF 4 16316 #define tx_x4_control0_cl36RxEEEStates_c_RX_WAKE 3 16317 #define tx_x4_control0_cl36RxEEEStates_c_RX_QUIET 2 16318 #define tx_x4_control0_cl36RxEEEStates_c_RX_SLEEP 1 16319 #define tx_x4_control0_cl36RxEEEStates_c_RX_ACTIVE 0 16320 16321 /**************************************************************************** 16322 * Enums: tx_x4_control0_cl49RxEEEStates_l 16323 */ 16324 #define tx_x4_control0_cl49RxEEEStates_l_RX_LINK_FAIL 32 16325 #define tx_x4_control0_cl49RxEEEStates_l_RX_WTF 16 16326 #define tx_x4_control0_cl49RxEEEStates_l_RX_WAKE 8 16327 #define tx_x4_control0_cl49RxEEEStates_l_RX_QUIET 4 16328 #define tx_x4_control0_cl49RxEEEStates_l_RX_SLEEP 2 16329 #define tx_x4_control0_cl49RxEEEStates_l_RX_ACTIVE 1 16330 16331 /**************************************************************************** 16332 * Enums: tx_x4_control0_cl49RxEEEStates_c 16333 */ 16334 #define tx_x4_control0_cl49RxEEEStates_c_RX_LINK_FAIL 5 16335 #define tx_x4_control0_cl49RxEEEStates_c_RX_WTF 4 16336 #define tx_x4_control0_cl49RxEEEStates_c_RX_WAKE 3 16337 #define tx_x4_control0_cl49RxEEEStates_c_RX_QUIET 2 16338 #define tx_x4_control0_cl49RxEEEStates_c_RX_SLEEP 1 16339 #define tx_x4_control0_cl49RxEEEStates_c_RX_ACTIVE 0 16340 16341 /**************************************************************************** 16342 * Enums: tx_x4_control0_cl48TxEEEStates_l 16343 */ 16344 #define tx_x4_control0_cl48TxEEEStates_l_TX_REFRESH 8 16345 #define tx_x4_control0_cl48TxEEEStates_l_TX_QUIET 4 16346 #define tx_x4_control0_cl48TxEEEStates_l_TX_SLEEP 2 16347 #define tx_x4_control0_cl48TxEEEStates_l_TX_ACTIVE 1 16348 16349 /**************************************************************************** 16350 * Enums: tx_x4_control0_cl48TxEEEStates_c 16351 */ 16352 #define tx_x4_control0_cl48TxEEEStates_c_TX_REFRESH 3 16353 #define tx_x4_control0_cl48TxEEEStates_c_TX_QUIET 2 16354 #define tx_x4_control0_cl48TxEEEStates_c_TX_SLEEP 1 16355 #define tx_x4_control0_cl48TxEEEStates_c_TX_ACTIVE 0 16356 16357 /**************************************************************************** 16358 * Enums: tx_x4_control0_cl48RxEEEStates_l 16359 */ 16360 #define tx_x4_control0_cl48RxEEEStates_l_RX_LINK_FAIL 32 16361 #define tx_x4_control0_cl48RxEEEStates_l_RX_WAKE 16 16362 #define tx_x4_control0_cl48RxEEEStates_l_RX_QUIET 8 16363 #define tx_x4_control0_cl48RxEEEStates_l_RX_DEACT 4 16364 #define tx_x4_control0_cl48RxEEEStates_l_RX_SLEEP 2 16365 #define tx_x4_control0_cl48RxEEEStates_l_RX_ACTIVE 1 16366 16367 /**************************************************************************** 16368 * Enums: tx_x4_control0_cl48RxEEEStates_c 16369 */ 16370 #define tx_x4_control0_cl48RxEEEStates_c_RX_LINK_FAIL 5 16371 #define tx_x4_control0_cl48RxEEEStates_c_RX_WAKE 4 16372 #define tx_x4_control0_cl48RxEEEStates_c_RX_QUIET 3 16373 #define tx_x4_control0_cl48RxEEEStates_c_RX_DEACT 2 16374 #define tx_x4_control0_cl48RxEEEStates_c_RX_SLEEP 1 16375 #define tx_x4_control0_cl48RxEEEStates_c_RX_ACTIVE 0 16376 16377 /**************************************************************************** 16378 * Enums: tx_x4_control0_IQP_Options 16379 */ 16380 #define tx_x4_control0_IQP_Options_i50uA 0 16381 #define tx_x4_control0_IQP_Options_i100uA 1 16382 #define tx_x4_control0_IQP_Options_i150uA 2 16383 #define tx_x4_control0_IQP_Options_i200uA 3 16384 #define tx_x4_control0_IQP_Options_i250uA 4 16385 #define tx_x4_control0_IQP_Options_i300uA 5 16386 #define tx_x4_control0_IQP_Options_i350uA 6 16387 #define tx_x4_control0_IQP_Options_i400uA 7 16388 #define tx_x4_control0_IQP_Options_i450uA 8 16389 #define tx_x4_control0_IQP_Options_i500uA 9 16390 #define tx_x4_control0_IQP_Options_i550uA 10 16391 #define tx_x4_control0_IQP_Options_i600uA 11 16392 #define tx_x4_control0_IQP_Options_i650uA 12 16393 #define tx_x4_control0_IQP_Options_i700uA 13 16394 #define tx_x4_control0_IQP_Options_i750uA 14 16395 #define tx_x4_control0_IQP_Options_i800uA 15 16396 16397 /**************************************************************************** 16398 * Enums: tx_x4_control0_IDriver_Options 16399 */ 16400 #define tx_x4_control0_IDriver_Options_v680mV 0 16401 #define tx_x4_control0_IDriver_Options_v730mV 1 16402 #define tx_x4_control0_IDriver_Options_v780mV 2 16403 #define tx_x4_control0_IDriver_Options_v830mV 3 16404 #define tx_x4_control0_IDriver_Options_v880mV 4 16405 #define tx_x4_control0_IDriver_Options_v930mV 5 16406 #define tx_x4_control0_IDriver_Options_v980mV 6 16407 #define tx_x4_control0_IDriver_Options_v1010mV 7 16408 #define tx_x4_control0_IDriver_Options_v1040mV 8 16409 #define tx_x4_control0_IDriver_Options_v1060mV 9 16410 #define tx_x4_control0_IDriver_Options_v1070mV 10 16411 #define tx_x4_control0_IDriver_Options_v1080mV 11 16412 #define tx_x4_control0_IDriver_Options_v1085mV 12 16413 #define tx_x4_control0_IDriver_Options_v1090mV 13 16414 #define tx_x4_control0_IDriver_Options_v1095mV 14 16415 #define tx_x4_control0_IDriver_Options_v1100mV 15 16416 16417 /**************************************************************************** 16418 * Enums: tx_x4_control0_operationModes 16419 */ 16420 #define tx_x4_control0_operationModes_XGXS 0 16421 #define tx_x4_control0_operationModes_XGXG_nCC 1 16422 #define tx_x4_control0_operationModes_Indlane_OS8 4 16423 #define tx_x4_control0_operationModes_IndLane_OS5 5 16424 #define tx_x4_control0_operationModes_PCI 7 16425 #define tx_x4_control0_operationModes_XGXS_nLQ 8 16426 #define tx_x4_control0_operationModes_XGXS_nLQnCC 9 16427 #define tx_x4_control0_operationModes_PBypass 10 16428 #define tx_x4_control0_operationModes_PBypass_nDSK 11 16429 #define tx_x4_control0_operationModes_ComboCoreMode 12 16430 #define tx_x4_control0_operationModes_Clocks_off 15 16431 16432 /**************************************************************************** 16433 * Enums: tx_x4_control0_actualSpeeds 16434 */ 16435 #define tx_x4_control0_actualSpeeds_dr_10M 0 16436 #define tx_x4_control0_actualSpeeds_dr_100M 1 16437 #define tx_x4_control0_actualSpeeds_dr_1G 2 16438 #define tx_x4_control0_actualSpeeds_dr_2p5G 3 16439 #define tx_x4_control0_actualSpeeds_dr_5G_X4 4 16440 #define tx_x4_control0_actualSpeeds_dr_6G_X4 5 16441 #define tx_x4_control0_actualSpeeds_dr_10G_HiG 6 16442 #define tx_x4_control0_actualSpeeds_dr_10G_CX4 7 16443 #define tx_x4_control0_actualSpeeds_dr_12G_HiG 8 16444 #define tx_x4_control0_actualSpeeds_dr_12p5G_X4 9 16445 #define tx_x4_control0_actualSpeeds_dr_13G_X4 10 16446 #define tx_x4_control0_actualSpeeds_dr_15G_X4 11 16447 #define tx_x4_control0_actualSpeeds_dr_16G_X4 12 16448 #define tx_x4_control0_actualSpeeds_dr_1G_KX 13 16449 #define tx_x4_control0_actualSpeeds_dr_10G_KX4 14 16450 #define tx_x4_control0_actualSpeeds_dr_10G_KR 15 16451 #define tx_x4_control0_actualSpeeds_dr_5G 16 16452 #define tx_x4_control0_actualSpeeds_dr_6p4G 17 16453 #define tx_x4_control0_actualSpeeds_dr_20G_X4 18 16454 #define tx_x4_control0_actualSpeeds_dr_21G_X4 19 16455 #define tx_x4_control0_actualSpeeds_dr_25G_X4 20 16456 #define tx_x4_control0_actualSpeeds_dr_10G_HiG_DXGXS 21 16457 #define tx_x4_control0_actualSpeeds_dr_10G_DXGXS 22 16458 #define tx_x4_control0_actualSpeeds_dr_10p5G_HiG_DXGXS 23 16459 #define tx_x4_control0_actualSpeeds_dr_10p5G_DXGXS 24 16460 #define tx_x4_control0_actualSpeeds_dr_12p773G_HiG_DXGXS 25 16461 #define tx_x4_control0_actualSpeeds_dr_12p773G_DXGXS 26 16462 #define tx_x4_control0_actualSpeeds_dr_10G_XFI 27 16463 #define tx_x4_control0_actualSpeeds_dr_40G 28 16464 #define tx_x4_control0_actualSpeeds_dr_20G_HiG_DXGXS 29 16465 #define tx_x4_control0_actualSpeeds_dr_20G_DXGXS 30 16466 #define tx_x4_control0_actualSpeeds_dr_10G_SFI 31 16467 #define tx_x4_control0_actualSpeeds_dr_31p5G 32 16468 #define tx_x4_control0_actualSpeeds_dr_32p7G 33 16469 #define tx_x4_control0_actualSpeeds_dr_20G_SCR 34 16470 #define tx_x4_control0_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 16471 #define tx_x4_control0_actualSpeeds_dr_10G_DXGXS_SCR 36 16472 #define tx_x4_control0_actualSpeeds_dr_12G_R2 37 16473 #define tx_x4_control0_actualSpeeds_dr_10G_X2 38 16474 #define tx_x4_control0_actualSpeeds_dr_40G_KR4 39 16475 #define tx_x4_control0_actualSpeeds_dr_40G_CR4 40 16476 #define tx_x4_control0_actualSpeeds_dr_100G_CR10 41 16477 #define tx_x4_control0_actualSpeeds_dr_15p75G_DXGXS 44 16478 #define tx_x4_control0_actualSpeeds_dr_20G_KR2 57 16479 #define tx_x4_control0_actualSpeeds_dr_20G_CR2 58 16480 16481 /**************************************************************************** 16482 * Enums: tx_x4_control0_actualSpeedsMisc1 16483 */ 16484 #define tx_x4_control0_actualSpeedsMisc1_dr_2500BRCM_X1 16 16485 #define tx_x4_control0_actualSpeedsMisc1_dr_5000BRCM_X4 17 16486 #define tx_x4_control0_actualSpeedsMisc1_dr_6000BRCM_X4 18 16487 #define tx_x4_control0_actualSpeedsMisc1_dr_10GHiGig_X4 19 16488 #define tx_x4_control0_actualSpeedsMisc1_dr_10GBASE_CX4 20 16489 #define tx_x4_control0_actualSpeedsMisc1_dr_12GHiGig_X4 21 16490 #define tx_x4_control0_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 16491 #define tx_x4_control0_actualSpeedsMisc1_dr_13GHiGig_X4 23 16492 #define tx_x4_control0_actualSpeedsMisc1_dr_15GHiGig_X4 24 16493 #define tx_x4_control0_actualSpeedsMisc1_dr_16GHiGig_X4 25 16494 #define tx_x4_control0_actualSpeedsMisc1_dr_5000BRCM_X1 26 16495 #define tx_x4_control0_actualSpeedsMisc1_dr_6363BRCM_X1 27 16496 #define tx_x4_control0_actualSpeedsMisc1_dr_20GHiGig_X4 28 16497 #define tx_x4_control0_actualSpeedsMisc1_dr_21GHiGig_X4 29 16498 #define tx_x4_control0_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 16499 #define tx_x4_control0_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 16500 16501 /**************************************************************************** 16502 * Enums: tx_x4_control0_IndLaneModes 16503 */ 16504 #define tx_x4_control0_IndLaneModes_SWSDR_div2 0 16505 #define tx_x4_control0_IndLaneModes_SWSDR_div1 1 16506 #define tx_x4_control0_IndLaneModes_DWSDR_div2 2 16507 #define tx_x4_control0_IndLaneModes_DWSDR_div1 3 16508 16509 /**************************************************************************** 16510 * Enums: tx_x4_control0_prbsSelect 16511 */ 16512 #define tx_x4_control0_prbsSelect_prbs7 0 16513 #define tx_x4_control0_prbsSelect_prbs15 1 16514 #define tx_x4_control0_prbsSelect_prbs23 2 16515 #define tx_x4_control0_prbsSelect_prbs31 3 16516 16517 /**************************************************************************** 16518 * Enums: tx_x4_control0_vcoDivider 16519 */ 16520 #define tx_x4_control0_vcoDivider_div32 0 16521 #define tx_x4_control0_vcoDivider_div36 1 16522 #define tx_x4_control0_vcoDivider_div40 2 16523 #define tx_x4_control0_vcoDivider_div42 3 16524 #define tx_x4_control0_vcoDivider_div48 4 16525 #define tx_x4_control0_vcoDivider_div50 5 16526 #define tx_x4_control0_vcoDivider_div52 6 16527 #define tx_x4_control0_vcoDivider_div54 7 16528 #define tx_x4_control0_vcoDivider_div60 8 16529 #define tx_x4_control0_vcoDivider_div64 9 16530 #define tx_x4_control0_vcoDivider_div66 10 16531 #define tx_x4_control0_vcoDivider_div68 11 16532 #define tx_x4_control0_vcoDivider_div70 12 16533 #define tx_x4_control0_vcoDivider_div80 13 16534 #define tx_x4_control0_vcoDivider_div92 14 16535 #define tx_x4_control0_vcoDivider_div100 15 16536 16537 /**************************************************************************** 16538 * Enums: tx_x4_control0_refClkSelect 16539 */ 16540 #define tx_x4_control0_refClkSelect_clk_25MHz 0 16541 #define tx_x4_control0_refClkSelect_clk_100MHz 1 16542 #define tx_x4_control0_refClkSelect_clk_125MHz 2 16543 #define tx_x4_control0_refClkSelect_clk_156p25MHz 3 16544 #define tx_x4_control0_refClkSelect_clk_187p5MHz 4 16545 #define tx_x4_control0_refClkSelect_clk_161p25Mhz 5 16546 #define tx_x4_control0_refClkSelect_clk_50Mhz 6 16547 #define tx_x4_control0_refClkSelect_clk_106p25Mhz 7 16548 16549 /**************************************************************************** 16550 * Enums: tx_x4_control0_aerMMDdevTypeSelect 16551 */ 16552 #define tx_x4_control0_aerMMDdevTypeSelect_combo_core 0 16553 #define tx_x4_control0_aerMMDdevTypeSelect_PMA_PMD 1 16554 #define tx_x4_control0_aerMMDdevTypeSelect_PCS 3 16555 #define tx_x4_control0_aerMMDdevTypeSelect_PHY 4 16556 #define tx_x4_control0_aerMMDdevTypeSelect_DTE 5 16557 #define tx_x4_control0_aerMMDdevTypeSelect_CL73_AN 7 16558 16559 /**************************************************************************** 16560 * Enums: tx_x4_control0_aerMMDportSelect 16561 */ 16562 #define tx_x4_control0_aerMMDportSelect_ln0 0 16563 #define tx_x4_control0_aerMMDportSelect_ln1 1 16564 #define tx_x4_control0_aerMMDportSelect_ln2 2 16565 #define tx_x4_control0_aerMMDportSelect_ln3 3 16566 #define tx_x4_control0_aerMMDportSelect_BCST_ln0_1_2_3 511 16567 #define tx_x4_control0_aerMMDportSelect_BCST_ln0_1 512 16568 #define tx_x4_control0_aerMMDportSelect_BCST_ln2_3 513 16569 16570 /**************************************************************************** 16571 * Enums: tx_x4_control0_firmwareModeSelect 16572 */ 16573 #define tx_x4_control0_firmwareModeSelect_DEFAULT 0 16574 #define tx_x4_control0_firmwareModeSelect_SFP_OPT_LR 1 16575 #define tx_x4_control0_firmwareModeSelect_SFP_DAC 2 16576 #define tx_x4_control0_firmwareModeSelect_XLAUI 3 16577 #define tx_x4_control0_firmwareModeSelect_LONG_CH_6G 4 16578 16579 /**************************************************************************** 16580 * Enums: tx_x4_control0_tempIdxSelect 16581 */ 16582 #define tx_x4_control0_tempIdxSelect_LTE__22p9C 15 16583 #define tx_x4_control0_tempIdxSelect_LTE__12p6C 14 16584 #define tx_x4_control0_tempIdxSelect_LTE__3p0C 13 16585 #define tx_x4_control0_tempIdxSelect_LTE_6p7C 12 16586 #define tx_x4_control0_tempIdxSelect_LTE_16p4C 11 16587 #define tx_x4_control0_tempIdxSelect_LTE_26p6C 10 16588 #define tx_x4_control0_tempIdxSelect_LTE_36p3C 9 16589 #define tx_x4_control0_tempIdxSelect_LTE_46p0C 8 16590 #define tx_x4_control0_tempIdxSelect_LTE_56p2C 7 16591 #define tx_x4_control0_tempIdxSelect_LTE_65p9C 6 16592 #define tx_x4_control0_tempIdxSelect_LTE_75p6C 5 16593 #define tx_x4_control0_tempIdxSelect_LTE_85p3C 4 16594 #define tx_x4_control0_tempIdxSelect_LTE_95p5C 3 16595 #define tx_x4_control0_tempIdxSelect_LTE_105p2C 2 16596 #define tx_x4_control0_tempIdxSelect_LTE_114p9C 1 16597 #define tx_x4_control0_tempIdxSelect_LTE_125p1C 0 16598 16599 /**************************************************************************** 16600 * Enums: tx_x4_control0_port_mode 16601 */ 16602 #define tx_x4_control0_port_mode_QUAD_PORT 0 16603 #define tx_x4_control0_port_mode_TRI_1_PORT 1 16604 #define tx_x4_control0_port_mode_TRI_2_PORT 2 16605 #define tx_x4_control0_port_mode_DUAL_PORT 3 16606 #define tx_x4_control0_port_mode_SINGLE_PORT 4 16607 16608 /**************************************************************************** 16609 * Enums: tx_x4_control0_rev_letter_enum 16610 */ 16611 #define tx_x4_control0_rev_letter_enum_REV_A 0 16612 #define tx_x4_control0_rev_letter_enum_REV_B 1 16613 #define tx_x4_control0_rev_letter_enum_REV_C 2 16614 #define tx_x4_control0_rev_letter_enum_REV_D 3 16615 16616 /**************************************************************************** 16617 * Enums: tx_x4_control0_rev_number_enum 16618 */ 16619 #define tx_x4_control0_rev_number_enum_REV_0 0 16620 #define tx_x4_control0_rev_number_enum_REV_1 1 16621 #define tx_x4_control0_rev_number_enum_REV_2 2 16622 #define tx_x4_control0_rev_number_enum_REV_3 3 16623 #define tx_x4_control0_rev_number_enum_REV_4 4 16624 #define tx_x4_control0_rev_number_enum_REV_5 5 16625 #define tx_x4_control0_rev_number_enum_REV_6 6 16626 #define tx_x4_control0_rev_number_enum_REV_7 7 16627 16628 /**************************************************************************** 16629 * Enums: tx_x4_control0_bonding_enum 16630 */ 16631 #define tx_x4_control0_bonding_enum_WIRE_BOND 0 16632 #define tx_x4_control0_bonding_enum_FLIP_CHIP 1 16633 16634 /**************************************************************************** 16635 * Enums: tx_x4_control0_tech_process 16636 */ 16637 #define tx_x4_control0_tech_process_PROCESS_90NM 0 16638 #define tx_x4_control0_tech_process_PROCESS_65NM 1 16639 #define tx_x4_control0_tech_process_PROCESS_40NM 2 16640 #define tx_x4_control0_tech_process_PROCESS_28NM 3 16641 16642 /**************************************************************************** 16643 * Enums: tx_x4_control0_model_num 16644 */ 16645 #define tx_x4_control0_model_num_SERDES_CL73 0 16646 #define tx_x4_control0_model_num_XGXS_16G 1 16647 #define tx_x4_control0_model_num_HYPERCORE 2 16648 #define tx_x4_control0_model_num_HYPERLITE 3 16649 #define tx_x4_control0_model_num_PCIE_G2_PIPE 4 16650 #define tx_x4_control0_model_num_SERDES_1p25GBd 5 16651 #define tx_x4_control0_model_num_SATA2 6 16652 #define tx_x4_control0_model_num_QSGMII 7 16653 #define tx_x4_control0_model_num_XGXS10G 8 16654 #define tx_x4_control0_model_num_WARPCORE 9 16655 #define tx_x4_control0_model_num_XFICORE 10 16656 #define tx_x4_control0_model_num_RXFI 11 16657 #define tx_x4_control0_model_num_WARPLITE 12 16658 #define tx_x4_control0_model_num_PENTACORE 13 16659 #define tx_x4_control0_model_num_ESM 14 16660 #define tx_x4_control0_model_num_QUAD_SGMII 15 16661 #define tx_x4_control0_model_num_WARPCORE_3 16 16662 #define tx_x4_control0_model_num_TSC 17 16663 #define tx_x4_control0_model_num_TSC4E 18 16664 #define tx_x4_control0_model_num_TSC12E 19 16665 #define tx_x4_control0_model_num_TSC4F 20 16666 #define tx_x4_control0_model_num_XGXS_CL73_90NM 29 16667 #define tx_x4_control0_model_num_SERDES_CL73_90NM 30 16668 #define tx_x4_control0_model_num_WARPCORE3 32 16669 #define tx_x4_control0_model_num_WARPCORE4_TSC 33 16670 #define tx_x4_control0_model_num_RXAUI 34 16671 16672 /**************************************************************************** 16673 * Enums: tx_x4_control0_payload 16674 */ 16675 #define tx_x4_control0_payload_REPEAT_2_BYTES 0 16676 #define tx_x4_control0_payload_RAMPING 1 16677 #define tx_x4_control0_payload_CL48_CRPAT 2 16678 #define tx_x4_control0_payload_CL48_CJPAT 3 16679 #define tx_x4_control0_payload_CL36_LONG_CRPAT 4 16680 #define tx_x4_control0_payload_CL36_SHORT_CRPAT 5 16681 16682 /**************************************************************************** 16683 * Enums: tx_x4_control0_sc 16684 */ 16685 #define tx_x4_control0_sc_S_10G_CR1 0 16686 #define tx_x4_control0_sc_S_10G_KR1 1 16687 #define tx_x4_control0_sc_S_10G_X1 2 16688 #define tx_x4_control0_sc_S_10G_HG2_CR1 4 16689 #define tx_x4_control0_sc_S_10G_HG2_KR1 5 16690 #define tx_x4_control0_sc_S_10G_HG2_X1 6 16691 #define tx_x4_control0_sc_S_20G_CR1 8 16692 #define tx_x4_control0_sc_S_20G_KR1 9 16693 #define tx_x4_control0_sc_S_20G_X1 10 16694 #define tx_x4_control0_sc_S_20G_HG2_CR1 12 16695 #define tx_x4_control0_sc_S_20G_HG2_KR1 13 16696 #define tx_x4_control0_sc_S_20G_HG2_X1 14 16697 #define tx_x4_control0_sc_S_25G_CR1 16 16698 #define tx_x4_control0_sc_S_25G_KR1 17 16699 #define tx_x4_control0_sc_S_25G_X1 18 16700 #define tx_x4_control0_sc_S_25G_HG2_CR1 20 16701 #define tx_x4_control0_sc_S_25G_HG2_KR1 21 16702 #define tx_x4_control0_sc_S_25G_HG2_X1 22 16703 #define tx_x4_control0_sc_S_20G_CR2 24 16704 #define tx_x4_control0_sc_S_20G_KR2 25 16705 #define tx_x4_control0_sc_S_20G_X2 26 16706 #define tx_x4_control0_sc_S_20G_HG2_CR2 28 16707 #define tx_x4_control0_sc_S_20G_HG2_KR2 29 16708 #define tx_x4_control0_sc_S_20G_HG2_X2 30 16709 #define tx_x4_control0_sc_S_40G_CR2 32 16710 #define tx_x4_control0_sc_S_40G_KR2 33 16711 #define tx_x4_control0_sc_S_40G_X2 34 16712 #define tx_x4_control0_sc_S_40G_HG2_CR2 36 16713 #define tx_x4_control0_sc_S_40G_HG2_KR2 37 16714 #define tx_x4_control0_sc_S_40G_HG2_X2 38 16715 #define tx_x4_control0_sc_S_40G_CR4 40 16716 #define tx_x4_control0_sc_S_40G_KR4 41 16717 #define tx_x4_control0_sc_S_40G_X4 42 16718 #define tx_x4_control0_sc_S_40G_HG2_CR4 44 16719 #define tx_x4_control0_sc_S_40G_HG2_KR4 45 16720 #define tx_x4_control0_sc_S_40G_HG2_X4 46 16721 #define tx_x4_control0_sc_S_50G_CR2 48 16722 #define tx_x4_control0_sc_S_50G_KR2 49 16723 #define tx_x4_control0_sc_S_50G_X2 50 16724 #define tx_x4_control0_sc_S_50G_HG2_CR2 52 16725 #define tx_x4_control0_sc_S_50G_HG2_KR2 53 16726 #define tx_x4_control0_sc_S_50G_HG2_X2 54 16727 #define tx_x4_control0_sc_S_50G_CR4 56 16728 #define tx_x4_control0_sc_S_50G_KR4 57 16729 #define tx_x4_control0_sc_S_50G_X4 58 16730 #define tx_x4_control0_sc_S_50G_HG2_CR4 60 16731 #define tx_x4_control0_sc_S_50G_HG2_KR4 61 16732 #define tx_x4_control0_sc_S_50G_HG2_X4 62 16733 #define tx_x4_control0_sc_S_100G_CR4 64 16734 #define tx_x4_control0_sc_S_100G_KR4 65 16735 #define tx_x4_control0_sc_S_100G_X4 66 16736 #define tx_x4_control0_sc_S_100G_HG2_CR4 68 16737 #define tx_x4_control0_sc_S_100G_HG2_KR4 69 16738 #define tx_x4_control0_sc_S_100G_HG2_X4 70 16739 #define tx_x4_control0_sc_S_CL73_20GVCO 72 16740 #define tx_x4_control0_sc_S_CL73_25GVCO 80 16741 #define tx_x4_control0_sc_S_CL36_20GVCO 88 16742 #define tx_x4_control0_sc_S_CL36_25GVCO 96 16743 16744 /**************************************************************************** 16745 * Enums: tx_x4_control0_t_fifo_modes 16746 */ 16747 #define tx_x4_control0_t_fifo_modes_T_FIFO_MODE_BYPASS 0 16748 #define tx_x4_control0_t_fifo_modes_T_FIFO_MODE_40G 1 16749 #define tx_x4_control0_t_fifo_modes_T_FIFO_MODE_100G 2 16750 #define tx_x4_control0_t_fifo_modes_T_FIFO_MODE_20G 3 16751 16752 /**************************************************************************** 16753 * Enums: tx_x4_control0_t_enc_modes 16754 */ 16755 #define tx_x4_control0_t_enc_modes_T_ENC_MODE_BYPASS 0 16756 #define tx_x4_control0_t_enc_modes_T_ENC_MODE_CL49 1 16757 #define tx_x4_control0_t_enc_modes_T_ENC_MODE_CL82 2 16758 16759 /**************************************************************************** 16760 * Enums: tx_x4_control0_btmx_mode 16761 */ 16762 #define tx_x4_control0_btmx_mode_BS_BTMX_MODE_1to1 0 16763 #define tx_x4_control0_btmx_mode_BS_BTMX_MODE_2to1 1 16764 #define tx_x4_control0_btmx_mode_BS_BTMX_MODE_5to1 2 16765 16766 /**************************************************************************** 16767 * Enums: tx_x4_control0_t_type_cl82 16768 */ 16769 #define tx_x4_control0_t_type_cl82_T_TYPE_B1 5 16770 #define tx_x4_control0_t_type_cl82_T_TYPE_C 4 16771 #define tx_x4_control0_t_type_cl82_T_TYPE_S 3 16772 #define tx_x4_control0_t_type_cl82_T_TYPE_T 2 16773 #define tx_x4_control0_t_type_cl82_T_TYPE_D 1 16774 #define tx_x4_control0_t_type_cl82_T_TYPE_E 0 16775 16776 /**************************************************************************** 16777 * Enums: tx_x4_control0_txsm_state_cl82 16778 */ 16779 #define tx_x4_control0_txsm_state_cl82_TX_HIG_END 6 16780 #define tx_x4_control0_txsm_state_cl82_TX_HIG_START 5 16781 #define tx_x4_control0_txsm_state_cl82_TX_E 4 16782 #define tx_x4_control0_txsm_state_cl82_TX_T 3 16783 #define tx_x4_control0_txsm_state_cl82_TX_D 2 16784 #define tx_x4_control0_txsm_state_cl82_TX_C 1 16785 #define tx_x4_control0_txsm_state_cl82_TX_INIT 0 16786 16787 /**************************************************************************** 16788 * Enums: tx_x4_control0_ltxsm_state_cl82 16789 */ 16790 #define tx_x4_control0_ltxsm_state_cl82_TX_HIG_END 64 16791 #define tx_x4_control0_ltxsm_state_cl82_TX_HIG_START 32 16792 #define tx_x4_control0_ltxsm_state_cl82_TX_E 16 16793 #define tx_x4_control0_ltxsm_state_cl82_TX_T 8 16794 #define tx_x4_control0_ltxsm_state_cl82_TX_D 4 16795 #define tx_x4_control0_ltxsm_state_cl82_TX_C 2 16796 #define tx_x4_control0_ltxsm_state_cl82_TX_INIT 1 16797 16798 /**************************************************************************** 16799 * Enums: tx_x4_control0_r_type_coded_cl82 16800 */ 16801 #define tx_x4_control0_r_type_coded_cl82_R_TYPE_B1 32 16802 #define tx_x4_control0_r_type_coded_cl82_R_TYPE_C 16 16803 #define tx_x4_control0_r_type_coded_cl82_R_TYPE_S 8 16804 #define tx_x4_control0_r_type_coded_cl82_R_TYPE_T 4 16805 #define tx_x4_control0_r_type_coded_cl82_R_TYPE_D 2 16806 #define tx_x4_control0_r_type_coded_cl82_R_TYPE_E 1 16807 16808 /**************************************************************************** 16809 * Enums: tx_x4_control0_rxsm_state_cl82 16810 */ 16811 #define tx_x4_control0_rxsm_state_cl82_RX_HIG_END 64 16812 #define tx_x4_control0_rxsm_state_cl82_RX_HIG_START 32 16813 #define tx_x4_control0_rxsm_state_cl82_RX_E 16 16814 #define tx_x4_control0_rxsm_state_cl82_RX_T 8 16815 #define tx_x4_control0_rxsm_state_cl82_RX_D 4 16816 #define tx_x4_control0_rxsm_state_cl82_RX_C 2 16817 #define tx_x4_control0_rxsm_state_cl82_RX_INIT 1 16818 16819 /**************************************************************************** 16820 * Enums: tx_x4_control0_deskew_state 16821 */ 16822 #define tx_x4_control0_deskew_state_ALIGN_ACQUIRED 2 16823 #define tx_x4_control0_deskew_state_LOSS_OF_ALIGNMENT 1 16824 16825 /**************************************************************************** 16826 * Enums: tx_x4_control0_os_mode_enum 16827 */ 16828 #define tx_x4_control0_os_mode_enum_OS_MODE_1 0 16829 #define tx_x4_control0_os_mode_enum_OS_MODE_2 1 16830 #define tx_x4_control0_os_mode_enum_OS_MODE_4 2 16831 #define tx_x4_control0_os_mode_enum_OS_MODE_16p5 8 16832 #define tx_x4_control0_os_mode_enum_OS_MODE_20p625 12 16833 16834 /**************************************************************************** 16835 * Enums: tx_x4_control0_scr_modes 16836 */ 16837 #define tx_x4_control0_scr_modes_T_SCR_MODE_BYPASS 0 16838 #define tx_x4_control0_scr_modes_T_SCR_MODE_CL49 1 16839 #define tx_x4_control0_scr_modes_T_SCR_MODE_40G_2_LANE 2 16840 #define tx_x4_control0_scr_modes_T_SCR_MODE_100G 3 16841 #define tx_x4_control0_scr_modes_T_SCR_MODE_20G 4 16842 #define tx_x4_control0_scr_modes_T_SCR_MODE_40G_4_LANE 5 16843 16844 /**************************************************************************** 16845 * Enums: tx_x4_control0_descr_modes 16846 */ 16847 #define tx_x4_control0_descr_modes_R_DESCR_MODE_BYPASS 0 16848 #define tx_x4_control0_descr_modes_R_DESCR_MODE_CL49 1 16849 #define tx_x4_control0_descr_modes_R_DESCR_MODE_CL82 2 16850 16851 /**************************************************************************** 16852 * Enums: tx_x4_control0_r_dec_tl_mode 16853 */ 16854 #define tx_x4_control0_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 16855 #define tx_x4_control0_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 16856 #define tx_x4_control0_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 16857 16858 /**************************************************************************** 16859 * Enums: tx_x4_control0_r_dec_fsm_mode 16860 */ 16861 #define tx_x4_control0_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 16862 #define tx_x4_control0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 16863 #define tx_x4_control0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 16864 16865 /**************************************************************************** 16866 * Enums: tx_x4_control0_r_deskew_mode 16867 */ 16868 #define tx_x4_control0_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 16869 #define tx_x4_control0_r_deskew_mode_R_DESKEW_MODE_20G 1 16870 #define tx_x4_control0_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 16871 #define tx_x4_control0_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 16872 #define tx_x4_control0_r_deskew_mode_R_DESKEW_MODE_100G 4 16873 #define tx_x4_control0_r_deskew_mode_R_DESKEW_MODE_CL49 5 16874 #define tx_x4_control0_r_deskew_mode_R_DESKEW_MODE_CL91 6 16875 16876 /**************************************************************************** 16877 * Enums: tx_x4_control0_bs_dist_modes 16878 */ 16879 #define tx_x4_control0_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 16880 #define tx_x4_control0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 16881 #define tx_x4_control0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 16882 #define tx_x4_control0_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 16883 16884 /**************************************************************************** 16885 * Enums: tx_x4_control0_cl49_t_type 16886 */ 16887 #define tx_x4_control0_cl49_t_type_BAD_T_TYPE 15 16888 #define tx_x4_control0_cl49_t_type_T_TYPE_B0 11 16889 #define tx_x4_control0_cl49_t_type_T_TYPE_OB 10 16890 #define tx_x4_control0_cl49_t_type_T_TYPE_B1 9 16891 #define tx_x4_control0_cl49_t_type_T_TYPE_DB 8 16892 #define tx_x4_control0_cl49_t_type_T_TYPE_FC 7 16893 #define tx_x4_control0_cl49_t_type_T_TYPE_TB 6 16894 #define tx_x4_control0_cl49_t_type_T_TYPE_LI 5 16895 #define tx_x4_control0_cl49_t_type_T_TYPE_C 4 16896 #define tx_x4_control0_cl49_t_type_T_TYPE_S 3 16897 #define tx_x4_control0_cl49_t_type_T_TYPE_T 2 16898 #define tx_x4_control0_cl49_t_type_T_TYPE_D 1 16899 #define tx_x4_control0_cl49_t_type_T_TYPE_E 0 16900 16901 /**************************************************************************** 16902 * Enums: tx_x4_control0_cl49_txsm_states 16903 */ 16904 #define tx_x4_control0_cl49_txsm_states_TX_HIG_END 7 16905 #define tx_x4_control0_cl49_txsm_states_TX_HIG_START 6 16906 #define tx_x4_control0_cl49_txsm_states_TX_LI 5 16907 #define tx_x4_control0_cl49_txsm_states_TX_E 4 16908 #define tx_x4_control0_cl49_txsm_states_TX_T 3 16909 #define tx_x4_control0_cl49_txsm_states_TX_D 2 16910 #define tx_x4_control0_cl49_txsm_states_TX_C 1 16911 #define tx_x4_control0_cl49_txsm_states_TX_INIT 0 16912 16913 /**************************************************************************** 16914 * Enums: tx_x4_control0_cl49_ltxsm_states 16915 */ 16916 #define tx_x4_control0_cl49_ltxsm_states_TX_HIG_END 128 16917 #define tx_x4_control0_cl49_ltxsm_states_TX_HIG_START 64 16918 #define tx_x4_control0_cl49_ltxsm_states_TX_LI 32 16919 #define tx_x4_control0_cl49_ltxsm_states_TX_E 16 16920 #define tx_x4_control0_cl49_ltxsm_states_TX_T 8 16921 #define tx_x4_control0_cl49_ltxsm_states_TX_D 4 16922 #define tx_x4_control0_cl49_ltxsm_states_TX_C 2 16923 #define tx_x4_control0_cl49_ltxsm_states_TX_INIT 1 16924 16925 /**************************************************************************** 16926 * Enums: tx_x4_control0_burst_error_mode 16927 */ 16928 #define tx_x4_control0_burst_error_mode_BURST_ERROR_11_BITS 0 16929 #define tx_x4_control0_burst_error_mode_BURST_ERROR_16_BITS 1 16930 #define tx_x4_control0_burst_error_mode_BURST_ERROR_17_BITS 2 16931 #define tx_x4_control0_burst_error_mode_BURST_ERROR_18_BITS 3 16932 #define tx_x4_control0_burst_error_mode_BURST_ERROR_19_BITS 4 16933 #define tx_x4_control0_burst_error_mode_BURST_ERROR_20_BITS 5 16934 #define tx_x4_control0_burst_error_mode_BURST_ERROR_21_BITS 6 16935 #define tx_x4_control0_burst_error_mode_BURST_ERROR_22_BITS 7 16936 #define tx_x4_control0_burst_error_mode_BURST_ERROR_23_BITS 8 16937 #define tx_x4_control0_burst_error_mode_BURST_ERROR_24_BITS 9 16938 #define tx_x4_control0_burst_error_mode_BURST_ERROR_25_BITS 10 16939 #define tx_x4_control0_burst_error_mode_BURST_ERROR_26_BITS 11 16940 #define tx_x4_control0_burst_error_mode_BURST_ERROR_27_BITS 12 16941 #define tx_x4_control0_burst_error_mode_BURST_ERROR_28_BITS 13 16942 #define tx_x4_control0_burst_error_mode_BURST_ERROR_29_BITS 14 16943 #define tx_x4_control0_burst_error_mode_BURST_ERROR_30_BITS 15 16944 #define tx_x4_control0_burst_error_mode_BURST_ERROR_31_BITS 16 16945 #define tx_x4_control0_burst_error_mode_BURST_ERROR_32_BITS 17 16946 #define tx_x4_control0_burst_error_mode_BURST_ERROR_33_BITS 18 16947 #define tx_x4_control0_burst_error_mode_BURST_ERROR_34_BITS 19 16948 #define tx_x4_control0_burst_error_mode_BURST_ERROR_35_BITS 20 16949 #define tx_x4_control0_burst_error_mode_BURST_ERROR_36_BITS 21 16950 #define tx_x4_control0_burst_error_mode_BURST_ERROR_37_BITS 22 16951 #define tx_x4_control0_burst_error_mode_BURST_ERROR_38_BITS 23 16952 #define tx_x4_control0_burst_error_mode_BURST_ERROR_39_BITS 24 16953 #define tx_x4_control0_burst_error_mode_BURST_ERROR_40_BITS 25 16954 #define tx_x4_control0_burst_error_mode_BURST_ERROR_41_BITS 26 16955 16956 /**************************************************************************** 16957 * Enums: tx_x4_control0_bermon_state 16958 */ 16959 #define tx_x4_control0_bermon_state_HI_BER 4 16960 #define tx_x4_control0_bermon_state_GOOD_BER 3 16961 #define tx_x4_control0_bermon_state_BER_TEST_SH 2 16962 #define tx_x4_control0_bermon_state_START_TIMER 1 16963 #define tx_x4_control0_bermon_state_BER_MT_INIT 0 16964 16965 /**************************************************************************** 16966 * Enums: tx_x4_control0_rxsm_state_cl49 16967 */ 16968 #define tx_x4_control0_rxsm_state_cl49_RX_HIG_END 128 16969 #define tx_x4_control0_rxsm_state_cl49_RX_HIG_START 64 16970 #define tx_x4_control0_rxsm_state_cl49_RX_LI 32 16971 #define tx_x4_control0_rxsm_state_cl49_RX_E 16 16972 #define tx_x4_control0_rxsm_state_cl49_RX_T 8 16973 #define tx_x4_control0_rxsm_state_cl49_RX_D 4 16974 #define tx_x4_control0_rxsm_state_cl49_RX_C 2 16975 #define tx_x4_control0_rxsm_state_cl49_RX_INIT 1 16976 16977 /**************************************************************************** 16978 * Enums: tx_x4_control0_r_type 16979 */ 16980 #define tx_x4_control0_r_type_BAD_R_TYPE 15 16981 #define tx_x4_control0_r_type_R_TYPE_B0 11 16982 #define tx_x4_control0_r_type_R_TYPE_OB 10 16983 #define tx_x4_control0_r_type_R_TYPE_B1 9 16984 #define tx_x4_control0_r_type_R_TYPE_DB 8 16985 #define tx_x4_control0_r_type_R_TYPE_FC 7 16986 #define tx_x4_control0_r_type_R_TYPE_TB 6 16987 #define tx_x4_control0_r_type_R_TYPE_LI 5 16988 #define tx_x4_control0_r_type_R_TYPE_C 4 16989 #define tx_x4_control0_r_type_R_TYPE_S 3 16990 #define tx_x4_control0_r_type_R_TYPE_T 2 16991 #define tx_x4_control0_r_type_R_TYPE_D 1 16992 #define tx_x4_control0_r_type_R_TYPE_E 0 16993 16994 /**************************************************************************** 16995 * Enums: tx_x4_control0_am_lock_state 16996 */ 16997 #define tx_x4_control0_am_lock_state_INVALID_AM 512 16998 #define tx_x4_control0_am_lock_state_GOOD_AM 256 16999 #define tx_x4_control0_am_lock_state_COMP_AM 128 17000 #define tx_x4_control0_am_lock_state_TIMER_2 64 17001 #define tx_x4_control0_am_lock_state_AM_2_GOOD 32 17002 #define tx_x4_control0_am_lock_state_COMP_2ND 16 17003 #define tx_x4_control0_am_lock_state_TIMER_1 8 17004 #define tx_x4_control0_am_lock_state_FIND_1ST 4 17005 #define tx_x4_control0_am_lock_state_AM_RESET_CNT 2 17006 #define tx_x4_control0_am_lock_state_AM_LOCK_INIT 1 17007 17008 /**************************************************************************** 17009 * Enums: tx_x4_control0_msg_selector 17010 */ 17011 #define tx_x4_control0_msg_selector_RESERVED 0 17012 #define tx_x4_control0_msg_selector_VALUE_802p3 1 17013 #define tx_x4_control0_msg_selector_VALUE_802p9 2 17014 #define tx_x4_control0_msg_selector_VALUE_802p5 3 17015 #define tx_x4_control0_msg_selector_VALUE_1394 4 17016 17017 /**************************************************************************** 17018 * Enums: tx_x4_control0_synce_enum 17019 */ 17020 #define tx_x4_control0_synce_enum_SYNCE_NO_DIV 0 17021 #define tx_x4_control0_synce_enum_SYNCE_DIV_7 1 17022 #define tx_x4_control0_synce_enum_SYNCE_DIV_11 2 17023 17024 /**************************************************************************** 17025 * Enums: tx_x4_control0_synce_enum_stage0 17026 */ 17027 #define tx_x4_control0_synce_enum_stage0_SYNCE_NO_DIV 0 17028 #define tx_x4_control0_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 17029 #define tx_x4_control0_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 17030 17031 /**************************************************************************** 17032 * Enums: tx_x4_control0_cl91_sync_state 17033 */ 17034 #define tx_x4_control0_cl91_sync_state_FIND_1ST 0 17035 #define tx_x4_control0_cl91_sync_state_COUNT_NEXT 1 17036 #define tx_x4_control0_cl91_sync_state_COMP_2ND 2 17037 #define tx_x4_control0_cl91_sync_state_TWO_GOOD 3 17038 17039 /**************************************************************************** 17040 * Enums: tx_x4_control0_cl91_algn_state 17041 */ 17042 #define tx_x4_control0_cl91_algn_state_LOSS_OF_ALIGNMENT 0 17043 #define tx_x4_control0_cl91_algn_state_DESKEW 1 17044 #define tx_x4_control0_cl91_algn_state_DESKEW_FAIL 2 17045 #define tx_x4_control0_cl91_algn_state_ALIGN_ACQUIRED 3 17046 #define tx_x4_control0_cl91_algn_state_CW_GOOD 4 17047 #define tx_x4_control0_cl91_algn_state_CW_BAD 5 17048 #define tx_x4_control0_cl91_algn_state_THREE_BAD 6 17049 17050 /**************************************************************************** 17051 * Enums: tx_x4_control0_fec_sel 17052 */ 17053 #define tx_x4_control0_fec_sel_NO_FEC 0 17054 #define tx_x4_control0_fec_sel_FEC_CL74 1 17055 #define tx_x4_control0_fec_sel_FEC_CL91 2 17056 17057 /**************************************************************************** 17058 * Enums: tx_x4_credit_gen0_cl36TxEEEStates_l 17059 */ 17060 #define tx_x4_credit_gen0_cl36TxEEEStates_l_TX_REFRESH 8 17061 #define tx_x4_credit_gen0_cl36TxEEEStates_l_TX_QUIET 4 17062 #define tx_x4_credit_gen0_cl36TxEEEStates_l_TX_SLEEP 2 17063 #define tx_x4_credit_gen0_cl36TxEEEStates_l_TX_ACTIVE 1 17064 17065 /**************************************************************************** 17066 * Enums: tx_x4_credit_gen0_cl36TxEEEStates_c 17067 */ 17068 #define tx_x4_credit_gen0_cl36TxEEEStates_c_TX_REFRESH 3 17069 #define tx_x4_credit_gen0_cl36TxEEEStates_c_TX_QUIET 2 17070 #define tx_x4_credit_gen0_cl36TxEEEStates_c_TX_SLEEP 1 17071 #define tx_x4_credit_gen0_cl36TxEEEStates_c_TX_ACTIVE 0 17072 17073 /**************************************************************************** 17074 * Enums: tx_x4_credit_gen0_cl49TxEEEStates_l 17075 */ 17076 #define tx_x4_credit_gen0_cl49TxEEEStates_l_SCR_RESET_2 64 17077 #define tx_x4_credit_gen0_cl49TxEEEStates_l_SCR_RESET_1 32 17078 #define tx_x4_credit_gen0_cl49TxEEEStates_l_TX_WAKE 16 17079 #define tx_x4_credit_gen0_cl49TxEEEStates_l_TX_REFRESH 8 17080 #define tx_x4_credit_gen0_cl49TxEEEStates_l_TX_QUIET 4 17081 #define tx_x4_credit_gen0_cl49TxEEEStates_l_TX_SLEEP 2 17082 #define tx_x4_credit_gen0_cl49TxEEEStates_l_TX_ACTIVE 1 17083 17084 /**************************************************************************** 17085 * Enums: tx_x4_credit_gen0_fec_req_enum 17086 */ 17087 #define tx_x4_credit_gen0_fec_req_enum_FEC_not_supported 0 17088 #define tx_x4_credit_gen0_fec_req_enum_FEC_supported_but_not_requested 1 17089 #define tx_x4_credit_gen0_fec_req_enum_invalid_setting 2 17090 #define tx_x4_credit_gen0_fec_req_enum_FEC_supported_and_requested 3 17091 17092 /**************************************************************************** 17093 * Enums: tx_x4_credit_gen0_cl73_pause_enum 17094 */ 17095 #define tx_x4_credit_gen0_cl73_pause_enum_No_PAUSE_ability 0 17096 #define tx_x4_credit_gen0_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 17097 #define tx_x4_credit_gen0_cl73_pause_enum_Symmetric_PAUSE_ability 1 17098 #define tx_x4_credit_gen0_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 17099 17100 /**************************************************************************** 17101 * Enums: tx_x4_credit_gen0_cl49TxEEEStates_c 17102 */ 17103 #define tx_x4_credit_gen0_cl49TxEEEStates_c_SCR_RESET_2 6 17104 #define tx_x4_credit_gen0_cl49TxEEEStates_c_SCR_RESET_1 5 17105 #define tx_x4_credit_gen0_cl49TxEEEStates_c_TX_WAKE 4 17106 #define tx_x4_credit_gen0_cl49TxEEEStates_c_TX_REFRESH 3 17107 #define tx_x4_credit_gen0_cl49TxEEEStates_c_TX_QUIET 2 17108 #define tx_x4_credit_gen0_cl49TxEEEStates_c_TX_SLEEP 1 17109 #define tx_x4_credit_gen0_cl49TxEEEStates_c_TX_ACTIVE 0 17110 17111 /**************************************************************************** 17112 * Enums: tx_x4_credit_gen0_cl36RxEEEStates_l 17113 */ 17114 #define tx_x4_credit_gen0_cl36RxEEEStates_l_RX_LINK_FAIL 32 17115 #define tx_x4_credit_gen0_cl36RxEEEStates_l_RX_WTF 16 17116 #define tx_x4_credit_gen0_cl36RxEEEStates_l_RX_WAKE 8 17117 #define tx_x4_credit_gen0_cl36RxEEEStates_l_RX_QUIET 4 17118 #define tx_x4_credit_gen0_cl36RxEEEStates_l_RX_SLEEP 2 17119 #define tx_x4_credit_gen0_cl36RxEEEStates_l_RX_ACTIVE 1 17120 17121 /**************************************************************************** 17122 * Enums: tx_x4_credit_gen0_cl36RxEEEStates_c 17123 */ 17124 #define tx_x4_credit_gen0_cl36RxEEEStates_c_RX_LINK_FAIL 5 17125 #define tx_x4_credit_gen0_cl36RxEEEStates_c_RX_WTF 4 17126 #define tx_x4_credit_gen0_cl36RxEEEStates_c_RX_WAKE 3 17127 #define tx_x4_credit_gen0_cl36RxEEEStates_c_RX_QUIET 2 17128 #define tx_x4_credit_gen0_cl36RxEEEStates_c_RX_SLEEP 1 17129 #define tx_x4_credit_gen0_cl36RxEEEStates_c_RX_ACTIVE 0 17130 17131 /**************************************************************************** 17132 * Enums: tx_x4_credit_gen0_cl49RxEEEStates_l 17133 */ 17134 #define tx_x4_credit_gen0_cl49RxEEEStates_l_RX_LINK_FAIL 32 17135 #define tx_x4_credit_gen0_cl49RxEEEStates_l_RX_WTF 16 17136 #define tx_x4_credit_gen0_cl49RxEEEStates_l_RX_WAKE 8 17137 #define tx_x4_credit_gen0_cl49RxEEEStates_l_RX_QUIET 4 17138 #define tx_x4_credit_gen0_cl49RxEEEStates_l_RX_SLEEP 2 17139 #define tx_x4_credit_gen0_cl49RxEEEStates_l_RX_ACTIVE 1 17140 17141 /**************************************************************************** 17142 * Enums: tx_x4_credit_gen0_cl49RxEEEStates_c 17143 */ 17144 #define tx_x4_credit_gen0_cl49RxEEEStates_c_RX_LINK_FAIL 5 17145 #define tx_x4_credit_gen0_cl49RxEEEStates_c_RX_WTF 4 17146 #define tx_x4_credit_gen0_cl49RxEEEStates_c_RX_WAKE 3 17147 #define tx_x4_credit_gen0_cl49RxEEEStates_c_RX_QUIET 2 17148 #define tx_x4_credit_gen0_cl49RxEEEStates_c_RX_SLEEP 1 17149 #define tx_x4_credit_gen0_cl49RxEEEStates_c_RX_ACTIVE 0 17150 17151 /**************************************************************************** 17152 * Enums: tx_x4_credit_gen0_cl48TxEEEStates_l 17153 */ 17154 #define tx_x4_credit_gen0_cl48TxEEEStates_l_TX_REFRESH 8 17155 #define tx_x4_credit_gen0_cl48TxEEEStates_l_TX_QUIET 4 17156 #define tx_x4_credit_gen0_cl48TxEEEStates_l_TX_SLEEP 2 17157 #define tx_x4_credit_gen0_cl48TxEEEStates_l_TX_ACTIVE 1 17158 17159 /**************************************************************************** 17160 * Enums: tx_x4_credit_gen0_cl48TxEEEStates_c 17161 */ 17162 #define tx_x4_credit_gen0_cl48TxEEEStates_c_TX_REFRESH 3 17163 #define tx_x4_credit_gen0_cl48TxEEEStates_c_TX_QUIET 2 17164 #define tx_x4_credit_gen0_cl48TxEEEStates_c_TX_SLEEP 1 17165 #define tx_x4_credit_gen0_cl48TxEEEStates_c_TX_ACTIVE 0 17166 17167 /**************************************************************************** 17168 * Enums: tx_x4_credit_gen0_cl48RxEEEStates_l 17169 */ 17170 #define tx_x4_credit_gen0_cl48RxEEEStates_l_RX_LINK_FAIL 32 17171 #define tx_x4_credit_gen0_cl48RxEEEStates_l_RX_WAKE 16 17172 #define tx_x4_credit_gen0_cl48RxEEEStates_l_RX_QUIET 8 17173 #define tx_x4_credit_gen0_cl48RxEEEStates_l_RX_DEACT 4 17174 #define tx_x4_credit_gen0_cl48RxEEEStates_l_RX_SLEEP 2 17175 #define tx_x4_credit_gen0_cl48RxEEEStates_l_RX_ACTIVE 1 17176 17177 /**************************************************************************** 17178 * Enums: tx_x4_credit_gen0_cl48RxEEEStates_c 17179 */ 17180 #define tx_x4_credit_gen0_cl48RxEEEStates_c_RX_LINK_FAIL 5 17181 #define tx_x4_credit_gen0_cl48RxEEEStates_c_RX_WAKE 4 17182 #define tx_x4_credit_gen0_cl48RxEEEStates_c_RX_QUIET 3 17183 #define tx_x4_credit_gen0_cl48RxEEEStates_c_RX_DEACT 2 17184 #define tx_x4_credit_gen0_cl48RxEEEStates_c_RX_SLEEP 1 17185 #define tx_x4_credit_gen0_cl48RxEEEStates_c_RX_ACTIVE 0 17186 17187 /**************************************************************************** 17188 * Enums: tx_x4_credit_gen0_IQP_Options 17189 */ 17190 #define tx_x4_credit_gen0_IQP_Options_i50uA 0 17191 #define tx_x4_credit_gen0_IQP_Options_i100uA 1 17192 #define tx_x4_credit_gen0_IQP_Options_i150uA 2 17193 #define tx_x4_credit_gen0_IQP_Options_i200uA 3 17194 #define tx_x4_credit_gen0_IQP_Options_i250uA 4 17195 #define tx_x4_credit_gen0_IQP_Options_i300uA 5 17196 #define tx_x4_credit_gen0_IQP_Options_i350uA 6 17197 #define tx_x4_credit_gen0_IQP_Options_i400uA 7 17198 #define tx_x4_credit_gen0_IQP_Options_i450uA 8 17199 #define tx_x4_credit_gen0_IQP_Options_i500uA 9 17200 #define tx_x4_credit_gen0_IQP_Options_i550uA 10 17201 #define tx_x4_credit_gen0_IQP_Options_i600uA 11 17202 #define tx_x4_credit_gen0_IQP_Options_i650uA 12 17203 #define tx_x4_credit_gen0_IQP_Options_i700uA 13 17204 #define tx_x4_credit_gen0_IQP_Options_i750uA 14 17205 #define tx_x4_credit_gen0_IQP_Options_i800uA 15 17206 17207 /**************************************************************************** 17208 * Enums: tx_x4_credit_gen0_IDriver_Options 17209 */ 17210 #define tx_x4_credit_gen0_IDriver_Options_v680mV 0 17211 #define tx_x4_credit_gen0_IDriver_Options_v730mV 1 17212 #define tx_x4_credit_gen0_IDriver_Options_v780mV 2 17213 #define tx_x4_credit_gen0_IDriver_Options_v830mV 3 17214 #define tx_x4_credit_gen0_IDriver_Options_v880mV 4 17215 #define tx_x4_credit_gen0_IDriver_Options_v930mV 5 17216 #define tx_x4_credit_gen0_IDriver_Options_v980mV 6 17217 #define tx_x4_credit_gen0_IDriver_Options_v1010mV 7 17218 #define tx_x4_credit_gen0_IDriver_Options_v1040mV 8 17219 #define tx_x4_credit_gen0_IDriver_Options_v1060mV 9 17220 #define tx_x4_credit_gen0_IDriver_Options_v1070mV 10 17221 #define tx_x4_credit_gen0_IDriver_Options_v1080mV 11 17222 #define tx_x4_credit_gen0_IDriver_Options_v1085mV 12 17223 #define tx_x4_credit_gen0_IDriver_Options_v1090mV 13 17224 #define tx_x4_credit_gen0_IDriver_Options_v1095mV 14 17225 #define tx_x4_credit_gen0_IDriver_Options_v1100mV 15 17226 17227 /**************************************************************************** 17228 * Enums: tx_x4_credit_gen0_operationModes 17229 */ 17230 #define tx_x4_credit_gen0_operationModes_XGXS 0 17231 #define tx_x4_credit_gen0_operationModes_XGXG_nCC 1 17232 #define tx_x4_credit_gen0_operationModes_Indlane_OS8 4 17233 #define tx_x4_credit_gen0_operationModes_IndLane_OS5 5 17234 #define tx_x4_credit_gen0_operationModes_PCI 7 17235 #define tx_x4_credit_gen0_operationModes_XGXS_nLQ 8 17236 #define tx_x4_credit_gen0_operationModes_XGXS_nLQnCC 9 17237 #define tx_x4_credit_gen0_operationModes_PBypass 10 17238 #define tx_x4_credit_gen0_operationModes_PBypass_nDSK 11 17239 #define tx_x4_credit_gen0_operationModes_ComboCoreMode 12 17240 #define tx_x4_credit_gen0_operationModes_Clocks_off 15 17241 17242 /**************************************************************************** 17243 * Enums: tx_x4_credit_gen0_actualSpeeds 17244 */ 17245 #define tx_x4_credit_gen0_actualSpeeds_dr_10M 0 17246 #define tx_x4_credit_gen0_actualSpeeds_dr_100M 1 17247 #define tx_x4_credit_gen0_actualSpeeds_dr_1G 2 17248 #define tx_x4_credit_gen0_actualSpeeds_dr_2p5G 3 17249 #define tx_x4_credit_gen0_actualSpeeds_dr_5G_X4 4 17250 #define tx_x4_credit_gen0_actualSpeeds_dr_6G_X4 5 17251 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_HiG 6 17252 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_CX4 7 17253 #define tx_x4_credit_gen0_actualSpeeds_dr_12G_HiG 8 17254 #define tx_x4_credit_gen0_actualSpeeds_dr_12p5G_X4 9 17255 #define tx_x4_credit_gen0_actualSpeeds_dr_13G_X4 10 17256 #define tx_x4_credit_gen0_actualSpeeds_dr_15G_X4 11 17257 #define tx_x4_credit_gen0_actualSpeeds_dr_16G_X4 12 17258 #define tx_x4_credit_gen0_actualSpeeds_dr_1G_KX 13 17259 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_KX4 14 17260 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_KR 15 17261 #define tx_x4_credit_gen0_actualSpeeds_dr_5G 16 17262 #define tx_x4_credit_gen0_actualSpeeds_dr_6p4G 17 17263 #define tx_x4_credit_gen0_actualSpeeds_dr_20G_X4 18 17264 #define tx_x4_credit_gen0_actualSpeeds_dr_21G_X4 19 17265 #define tx_x4_credit_gen0_actualSpeeds_dr_25G_X4 20 17266 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_HiG_DXGXS 21 17267 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_DXGXS 22 17268 #define tx_x4_credit_gen0_actualSpeeds_dr_10p5G_HiG_DXGXS 23 17269 #define tx_x4_credit_gen0_actualSpeeds_dr_10p5G_DXGXS 24 17270 #define tx_x4_credit_gen0_actualSpeeds_dr_12p773G_HiG_DXGXS 25 17271 #define tx_x4_credit_gen0_actualSpeeds_dr_12p773G_DXGXS 26 17272 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_XFI 27 17273 #define tx_x4_credit_gen0_actualSpeeds_dr_40G 28 17274 #define tx_x4_credit_gen0_actualSpeeds_dr_20G_HiG_DXGXS 29 17275 #define tx_x4_credit_gen0_actualSpeeds_dr_20G_DXGXS 30 17276 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_SFI 31 17277 #define tx_x4_credit_gen0_actualSpeeds_dr_31p5G 32 17278 #define tx_x4_credit_gen0_actualSpeeds_dr_32p7G 33 17279 #define tx_x4_credit_gen0_actualSpeeds_dr_20G_SCR 34 17280 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 17281 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_DXGXS_SCR 36 17282 #define tx_x4_credit_gen0_actualSpeeds_dr_12G_R2 37 17283 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_X2 38 17284 #define tx_x4_credit_gen0_actualSpeeds_dr_40G_KR4 39 17285 #define tx_x4_credit_gen0_actualSpeeds_dr_40G_CR4 40 17286 #define tx_x4_credit_gen0_actualSpeeds_dr_100G_CR10 41 17287 #define tx_x4_credit_gen0_actualSpeeds_dr_15p75G_DXGXS 44 17288 #define tx_x4_credit_gen0_actualSpeeds_dr_20G_KR2 57 17289 #define tx_x4_credit_gen0_actualSpeeds_dr_20G_CR2 58 17290 17291 /**************************************************************************** 17292 * Enums: tx_x4_credit_gen0_actualSpeedsMisc1 17293 */ 17294 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_2500BRCM_X1 16 17295 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_5000BRCM_X4 17 17296 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_6000BRCM_X4 18 17297 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_10GHiGig_X4 19 17298 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_10GBASE_CX4 20 17299 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_12GHiGig_X4 21 17300 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 17301 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_13GHiGig_X4 23 17302 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_15GHiGig_X4 24 17303 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_16GHiGig_X4 25 17304 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_5000BRCM_X1 26 17305 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_6363BRCM_X1 27 17306 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_20GHiGig_X4 28 17307 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_21GHiGig_X4 29 17308 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 17309 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 17310 17311 /**************************************************************************** 17312 * Enums: tx_x4_credit_gen0_IndLaneModes 17313 */ 17314 #define tx_x4_credit_gen0_IndLaneModes_SWSDR_div2 0 17315 #define tx_x4_credit_gen0_IndLaneModes_SWSDR_div1 1 17316 #define tx_x4_credit_gen0_IndLaneModes_DWSDR_div2 2 17317 #define tx_x4_credit_gen0_IndLaneModes_DWSDR_div1 3 17318 17319 /**************************************************************************** 17320 * Enums: tx_x4_credit_gen0_prbsSelect 17321 */ 17322 #define tx_x4_credit_gen0_prbsSelect_prbs7 0 17323 #define tx_x4_credit_gen0_prbsSelect_prbs15 1 17324 #define tx_x4_credit_gen0_prbsSelect_prbs23 2 17325 #define tx_x4_credit_gen0_prbsSelect_prbs31 3 17326 17327 /**************************************************************************** 17328 * Enums: tx_x4_credit_gen0_vcoDivider 17329 */ 17330 #define tx_x4_credit_gen0_vcoDivider_div32 0 17331 #define tx_x4_credit_gen0_vcoDivider_div36 1 17332 #define tx_x4_credit_gen0_vcoDivider_div40 2 17333 #define tx_x4_credit_gen0_vcoDivider_div42 3 17334 #define tx_x4_credit_gen0_vcoDivider_div48 4 17335 #define tx_x4_credit_gen0_vcoDivider_div50 5 17336 #define tx_x4_credit_gen0_vcoDivider_div52 6 17337 #define tx_x4_credit_gen0_vcoDivider_div54 7 17338 #define tx_x4_credit_gen0_vcoDivider_div60 8 17339 #define tx_x4_credit_gen0_vcoDivider_div64 9 17340 #define tx_x4_credit_gen0_vcoDivider_div66 10 17341 #define tx_x4_credit_gen0_vcoDivider_div68 11 17342 #define tx_x4_credit_gen0_vcoDivider_div70 12 17343 #define tx_x4_credit_gen0_vcoDivider_div80 13 17344 #define tx_x4_credit_gen0_vcoDivider_div92 14 17345 #define tx_x4_credit_gen0_vcoDivider_div100 15 17346 17347 /**************************************************************************** 17348 * Enums: tx_x4_credit_gen0_refClkSelect 17349 */ 17350 #define tx_x4_credit_gen0_refClkSelect_clk_25MHz 0 17351 #define tx_x4_credit_gen0_refClkSelect_clk_100MHz 1 17352 #define tx_x4_credit_gen0_refClkSelect_clk_125MHz 2 17353 #define tx_x4_credit_gen0_refClkSelect_clk_156p25MHz 3 17354 #define tx_x4_credit_gen0_refClkSelect_clk_187p5MHz 4 17355 #define tx_x4_credit_gen0_refClkSelect_clk_161p25Mhz 5 17356 #define tx_x4_credit_gen0_refClkSelect_clk_50Mhz 6 17357 #define tx_x4_credit_gen0_refClkSelect_clk_106p25Mhz 7 17358 17359 /**************************************************************************** 17360 * Enums: tx_x4_credit_gen0_aerMMDdevTypeSelect 17361 */ 17362 #define tx_x4_credit_gen0_aerMMDdevTypeSelect_combo_core 0 17363 #define tx_x4_credit_gen0_aerMMDdevTypeSelect_PMA_PMD 1 17364 #define tx_x4_credit_gen0_aerMMDdevTypeSelect_PCS 3 17365 #define tx_x4_credit_gen0_aerMMDdevTypeSelect_PHY 4 17366 #define tx_x4_credit_gen0_aerMMDdevTypeSelect_DTE 5 17367 #define tx_x4_credit_gen0_aerMMDdevTypeSelect_CL73_AN 7 17368 17369 /**************************************************************************** 17370 * Enums: tx_x4_credit_gen0_aerMMDportSelect 17371 */ 17372 #define tx_x4_credit_gen0_aerMMDportSelect_ln0 0 17373 #define tx_x4_credit_gen0_aerMMDportSelect_ln1 1 17374 #define tx_x4_credit_gen0_aerMMDportSelect_ln2 2 17375 #define tx_x4_credit_gen0_aerMMDportSelect_ln3 3 17376 #define tx_x4_credit_gen0_aerMMDportSelect_BCST_ln0_1_2_3 511 17377 #define tx_x4_credit_gen0_aerMMDportSelect_BCST_ln0_1 512 17378 #define tx_x4_credit_gen0_aerMMDportSelect_BCST_ln2_3 513 17379 17380 /**************************************************************************** 17381 * Enums: tx_x4_credit_gen0_firmwareModeSelect 17382 */ 17383 #define tx_x4_credit_gen0_firmwareModeSelect_DEFAULT 0 17384 #define tx_x4_credit_gen0_firmwareModeSelect_SFP_OPT_LR 1 17385 #define tx_x4_credit_gen0_firmwareModeSelect_SFP_DAC 2 17386 #define tx_x4_credit_gen0_firmwareModeSelect_XLAUI 3 17387 #define tx_x4_credit_gen0_firmwareModeSelect_LONG_CH_6G 4 17388 17389 /**************************************************************************** 17390 * Enums: tx_x4_credit_gen0_tempIdxSelect 17391 */ 17392 #define tx_x4_credit_gen0_tempIdxSelect_LTE__22p9C 15 17393 #define tx_x4_credit_gen0_tempIdxSelect_LTE__12p6C 14 17394 #define tx_x4_credit_gen0_tempIdxSelect_LTE__3p0C 13 17395 #define tx_x4_credit_gen0_tempIdxSelect_LTE_6p7C 12 17396 #define tx_x4_credit_gen0_tempIdxSelect_LTE_16p4C 11 17397 #define tx_x4_credit_gen0_tempIdxSelect_LTE_26p6C 10 17398 #define tx_x4_credit_gen0_tempIdxSelect_LTE_36p3C 9 17399 #define tx_x4_credit_gen0_tempIdxSelect_LTE_46p0C 8 17400 #define tx_x4_credit_gen0_tempIdxSelect_LTE_56p2C 7 17401 #define tx_x4_credit_gen0_tempIdxSelect_LTE_65p9C 6 17402 #define tx_x4_credit_gen0_tempIdxSelect_LTE_75p6C 5 17403 #define tx_x4_credit_gen0_tempIdxSelect_LTE_85p3C 4 17404 #define tx_x4_credit_gen0_tempIdxSelect_LTE_95p5C 3 17405 #define tx_x4_credit_gen0_tempIdxSelect_LTE_105p2C 2 17406 #define tx_x4_credit_gen0_tempIdxSelect_LTE_114p9C 1 17407 #define tx_x4_credit_gen0_tempIdxSelect_LTE_125p1C 0 17408 17409 /**************************************************************************** 17410 * Enums: tx_x4_credit_gen0_port_mode 17411 */ 17412 #define tx_x4_credit_gen0_port_mode_QUAD_PORT 0 17413 #define tx_x4_credit_gen0_port_mode_TRI_1_PORT 1 17414 #define tx_x4_credit_gen0_port_mode_TRI_2_PORT 2 17415 #define tx_x4_credit_gen0_port_mode_DUAL_PORT 3 17416 #define tx_x4_credit_gen0_port_mode_SINGLE_PORT 4 17417 17418 /**************************************************************************** 17419 * Enums: tx_x4_credit_gen0_rev_letter_enum 17420 */ 17421 #define tx_x4_credit_gen0_rev_letter_enum_REV_A 0 17422 #define tx_x4_credit_gen0_rev_letter_enum_REV_B 1 17423 #define tx_x4_credit_gen0_rev_letter_enum_REV_C 2 17424 #define tx_x4_credit_gen0_rev_letter_enum_REV_D 3 17425 17426 /**************************************************************************** 17427 * Enums: tx_x4_credit_gen0_rev_number_enum 17428 */ 17429 #define tx_x4_credit_gen0_rev_number_enum_REV_0 0 17430 #define tx_x4_credit_gen0_rev_number_enum_REV_1 1 17431 #define tx_x4_credit_gen0_rev_number_enum_REV_2 2 17432 #define tx_x4_credit_gen0_rev_number_enum_REV_3 3 17433 #define tx_x4_credit_gen0_rev_number_enum_REV_4 4 17434 #define tx_x4_credit_gen0_rev_number_enum_REV_5 5 17435 #define tx_x4_credit_gen0_rev_number_enum_REV_6 6 17436 #define tx_x4_credit_gen0_rev_number_enum_REV_7 7 17437 17438 /**************************************************************************** 17439 * Enums: tx_x4_credit_gen0_bonding_enum 17440 */ 17441 #define tx_x4_credit_gen0_bonding_enum_WIRE_BOND 0 17442 #define tx_x4_credit_gen0_bonding_enum_FLIP_CHIP 1 17443 17444 /**************************************************************************** 17445 * Enums: tx_x4_credit_gen0_tech_process 17446 */ 17447 #define tx_x4_credit_gen0_tech_process_PROCESS_90NM 0 17448 #define tx_x4_credit_gen0_tech_process_PROCESS_65NM 1 17449 #define tx_x4_credit_gen0_tech_process_PROCESS_40NM 2 17450 #define tx_x4_credit_gen0_tech_process_PROCESS_28NM 3 17451 17452 /**************************************************************************** 17453 * Enums: tx_x4_credit_gen0_model_num 17454 */ 17455 #define tx_x4_credit_gen0_model_num_SERDES_CL73 0 17456 #define tx_x4_credit_gen0_model_num_XGXS_16G 1 17457 #define tx_x4_credit_gen0_model_num_HYPERCORE 2 17458 #define tx_x4_credit_gen0_model_num_HYPERLITE 3 17459 #define tx_x4_credit_gen0_model_num_PCIE_G2_PIPE 4 17460 #define tx_x4_credit_gen0_model_num_SERDES_1p25GBd 5 17461 #define tx_x4_credit_gen0_model_num_SATA2 6 17462 #define tx_x4_credit_gen0_model_num_QSGMII 7 17463 #define tx_x4_credit_gen0_model_num_XGXS10G 8 17464 #define tx_x4_credit_gen0_model_num_WARPCORE 9 17465 #define tx_x4_credit_gen0_model_num_XFICORE 10 17466 #define tx_x4_credit_gen0_model_num_RXFI 11 17467 #define tx_x4_credit_gen0_model_num_WARPLITE 12 17468 #define tx_x4_credit_gen0_model_num_PENTACORE 13 17469 #define tx_x4_credit_gen0_model_num_ESM 14 17470 #define tx_x4_credit_gen0_model_num_QUAD_SGMII 15 17471 #define tx_x4_credit_gen0_model_num_WARPCORE_3 16 17472 #define tx_x4_credit_gen0_model_num_TSC 17 17473 #define tx_x4_credit_gen0_model_num_TSC4E 18 17474 #define tx_x4_credit_gen0_model_num_TSC12E 19 17475 #define tx_x4_credit_gen0_model_num_TSC4F 20 17476 #define tx_x4_credit_gen0_model_num_XGXS_CL73_90NM 29 17477 #define tx_x4_credit_gen0_model_num_SERDES_CL73_90NM 30 17478 #define tx_x4_credit_gen0_model_num_WARPCORE3 32 17479 #define tx_x4_credit_gen0_model_num_WARPCORE4_TSC 33 17480 #define tx_x4_credit_gen0_model_num_RXAUI 34 17481 17482 /**************************************************************************** 17483 * Enums: tx_x4_credit_gen0_payload 17484 */ 17485 #define tx_x4_credit_gen0_payload_REPEAT_2_BYTES 0 17486 #define tx_x4_credit_gen0_payload_RAMPING 1 17487 #define tx_x4_credit_gen0_payload_CL48_CRPAT 2 17488 #define tx_x4_credit_gen0_payload_CL48_CJPAT 3 17489 #define tx_x4_credit_gen0_payload_CL36_LONG_CRPAT 4 17490 #define tx_x4_credit_gen0_payload_CL36_SHORT_CRPAT 5 17491 17492 /**************************************************************************** 17493 * Enums: tx_x4_credit_gen0_sc 17494 */ 17495 #define tx_x4_credit_gen0_sc_S_10G_CR1 0 17496 #define tx_x4_credit_gen0_sc_S_10G_KR1 1 17497 #define tx_x4_credit_gen0_sc_S_10G_X1 2 17498 #define tx_x4_credit_gen0_sc_S_10G_HG2_CR1 4 17499 #define tx_x4_credit_gen0_sc_S_10G_HG2_KR1 5 17500 #define tx_x4_credit_gen0_sc_S_10G_HG2_X1 6 17501 #define tx_x4_credit_gen0_sc_S_20G_CR1 8 17502 #define tx_x4_credit_gen0_sc_S_20G_KR1 9 17503 #define tx_x4_credit_gen0_sc_S_20G_X1 10 17504 #define tx_x4_credit_gen0_sc_S_20G_HG2_CR1 12 17505 #define tx_x4_credit_gen0_sc_S_20G_HG2_KR1 13 17506 #define tx_x4_credit_gen0_sc_S_20G_HG2_X1 14 17507 #define tx_x4_credit_gen0_sc_S_25G_CR1 16 17508 #define tx_x4_credit_gen0_sc_S_25G_KR1 17 17509 #define tx_x4_credit_gen0_sc_S_25G_X1 18 17510 #define tx_x4_credit_gen0_sc_S_25G_HG2_CR1 20 17511 #define tx_x4_credit_gen0_sc_S_25G_HG2_KR1 21 17512 #define tx_x4_credit_gen0_sc_S_25G_HG2_X1 22 17513 #define tx_x4_credit_gen0_sc_S_20G_CR2 24 17514 #define tx_x4_credit_gen0_sc_S_20G_KR2 25 17515 #define tx_x4_credit_gen0_sc_S_20G_X2 26 17516 #define tx_x4_credit_gen0_sc_S_20G_HG2_CR2 28 17517 #define tx_x4_credit_gen0_sc_S_20G_HG2_KR2 29 17518 #define tx_x4_credit_gen0_sc_S_20G_HG2_X2 30 17519 #define tx_x4_credit_gen0_sc_S_40G_CR2 32 17520 #define tx_x4_credit_gen0_sc_S_40G_KR2 33 17521 #define tx_x4_credit_gen0_sc_S_40G_X2 34 17522 #define tx_x4_credit_gen0_sc_S_40G_HG2_CR2 36 17523 #define tx_x4_credit_gen0_sc_S_40G_HG2_KR2 37 17524 #define tx_x4_credit_gen0_sc_S_40G_HG2_X2 38 17525 #define tx_x4_credit_gen0_sc_S_40G_CR4 40 17526 #define tx_x4_credit_gen0_sc_S_40G_KR4 41 17527 #define tx_x4_credit_gen0_sc_S_40G_X4 42 17528 #define tx_x4_credit_gen0_sc_S_40G_HG2_CR4 44 17529 #define tx_x4_credit_gen0_sc_S_40G_HG2_KR4 45 17530 #define tx_x4_credit_gen0_sc_S_40G_HG2_X4 46 17531 #define tx_x4_credit_gen0_sc_S_50G_CR2 48 17532 #define tx_x4_credit_gen0_sc_S_50G_KR2 49 17533 #define tx_x4_credit_gen0_sc_S_50G_X2 50 17534 #define tx_x4_credit_gen0_sc_S_50G_HG2_CR2 52 17535 #define tx_x4_credit_gen0_sc_S_50G_HG2_KR2 53 17536 #define tx_x4_credit_gen0_sc_S_50G_HG2_X2 54 17537 #define tx_x4_credit_gen0_sc_S_50G_CR4 56 17538 #define tx_x4_credit_gen0_sc_S_50G_KR4 57 17539 #define tx_x4_credit_gen0_sc_S_50G_X4 58 17540 #define tx_x4_credit_gen0_sc_S_50G_HG2_CR4 60 17541 #define tx_x4_credit_gen0_sc_S_50G_HG2_KR4 61 17542 #define tx_x4_credit_gen0_sc_S_50G_HG2_X4 62 17543 #define tx_x4_credit_gen0_sc_S_100G_CR4 64 17544 #define tx_x4_credit_gen0_sc_S_100G_KR4 65 17545 #define tx_x4_credit_gen0_sc_S_100G_X4 66 17546 #define tx_x4_credit_gen0_sc_S_100G_HG2_CR4 68 17547 #define tx_x4_credit_gen0_sc_S_100G_HG2_KR4 69 17548 #define tx_x4_credit_gen0_sc_S_100G_HG2_X4 70 17549 #define tx_x4_credit_gen0_sc_S_CL73_20GVCO 72 17550 #define tx_x4_credit_gen0_sc_S_CL73_25GVCO 80 17551 #define tx_x4_credit_gen0_sc_S_CL36_20GVCO 88 17552 #define tx_x4_credit_gen0_sc_S_CL36_25GVCO 96 17553 17554 /**************************************************************************** 17555 * Enums: tx_x4_credit_gen0_t_fifo_modes 17556 */ 17557 #define tx_x4_credit_gen0_t_fifo_modes_T_FIFO_MODE_BYPASS 0 17558 #define tx_x4_credit_gen0_t_fifo_modes_T_FIFO_MODE_40G 1 17559 #define tx_x4_credit_gen0_t_fifo_modes_T_FIFO_MODE_100G 2 17560 #define tx_x4_credit_gen0_t_fifo_modes_T_FIFO_MODE_20G 3 17561 17562 /**************************************************************************** 17563 * Enums: tx_x4_credit_gen0_t_enc_modes 17564 */ 17565 #define tx_x4_credit_gen0_t_enc_modes_T_ENC_MODE_BYPASS 0 17566 #define tx_x4_credit_gen0_t_enc_modes_T_ENC_MODE_CL49 1 17567 #define tx_x4_credit_gen0_t_enc_modes_T_ENC_MODE_CL82 2 17568 17569 /**************************************************************************** 17570 * Enums: tx_x4_credit_gen0_btmx_mode 17571 */ 17572 #define tx_x4_credit_gen0_btmx_mode_BS_BTMX_MODE_1to1 0 17573 #define tx_x4_credit_gen0_btmx_mode_BS_BTMX_MODE_2to1 1 17574 #define tx_x4_credit_gen0_btmx_mode_BS_BTMX_MODE_5to1 2 17575 17576 /**************************************************************************** 17577 * Enums: tx_x4_credit_gen0_t_type_cl82 17578 */ 17579 #define tx_x4_credit_gen0_t_type_cl82_T_TYPE_B1 5 17580 #define tx_x4_credit_gen0_t_type_cl82_T_TYPE_C 4 17581 #define tx_x4_credit_gen0_t_type_cl82_T_TYPE_S 3 17582 #define tx_x4_credit_gen0_t_type_cl82_T_TYPE_T 2 17583 #define tx_x4_credit_gen0_t_type_cl82_T_TYPE_D 1 17584 #define tx_x4_credit_gen0_t_type_cl82_T_TYPE_E 0 17585 17586 /**************************************************************************** 17587 * Enums: tx_x4_credit_gen0_txsm_state_cl82 17588 */ 17589 #define tx_x4_credit_gen0_txsm_state_cl82_TX_HIG_END 6 17590 #define tx_x4_credit_gen0_txsm_state_cl82_TX_HIG_START 5 17591 #define tx_x4_credit_gen0_txsm_state_cl82_TX_E 4 17592 #define tx_x4_credit_gen0_txsm_state_cl82_TX_T 3 17593 #define tx_x4_credit_gen0_txsm_state_cl82_TX_D 2 17594 #define tx_x4_credit_gen0_txsm_state_cl82_TX_C 1 17595 #define tx_x4_credit_gen0_txsm_state_cl82_TX_INIT 0 17596 17597 /**************************************************************************** 17598 * Enums: tx_x4_credit_gen0_ltxsm_state_cl82 17599 */ 17600 #define tx_x4_credit_gen0_ltxsm_state_cl82_TX_HIG_END 64 17601 #define tx_x4_credit_gen0_ltxsm_state_cl82_TX_HIG_START 32 17602 #define tx_x4_credit_gen0_ltxsm_state_cl82_TX_E 16 17603 #define tx_x4_credit_gen0_ltxsm_state_cl82_TX_T 8 17604 #define tx_x4_credit_gen0_ltxsm_state_cl82_TX_D 4 17605 #define tx_x4_credit_gen0_ltxsm_state_cl82_TX_C 2 17606 #define tx_x4_credit_gen0_ltxsm_state_cl82_TX_INIT 1 17607 17608 /**************************************************************************** 17609 * Enums: tx_x4_credit_gen0_r_type_coded_cl82 17610 */ 17611 #define tx_x4_credit_gen0_r_type_coded_cl82_R_TYPE_B1 32 17612 #define tx_x4_credit_gen0_r_type_coded_cl82_R_TYPE_C 16 17613 #define tx_x4_credit_gen0_r_type_coded_cl82_R_TYPE_S 8 17614 #define tx_x4_credit_gen0_r_type_coded_cl82_R_TYPE_T 4 17615 #define tx_x4_credit_gen0_r_type_coded_cl82_R_TYPE_D 2 17616 #define tx_x4_credit_gen0_r_type_coded_cl82_R_TYPE_E 1 17617 17618 /**************************************************************************** 17619 * Enums: tx_x4_credit_gen0_rxsm_state_cl82 17620 */ 17621 #define tx_x4_credit_gen0_rxsm_state_cl82_RX_HIG_END 64 17622 #define tx_x4_credit_gen0_rxsm_state_cl82_RX_HIG_START 32 17623 #define tx_x4_credit_gen0_rxsm_state_cl82_RX_E 16 17624 #define tx_x4_credit_gen0_rxsm_state_cl82_RX_T 8 17625 #define tx_x4_credit_gen0_rxsm_state_cl82_RX_D 4 17626 #define tx_x4_credit_gen0_rxsm_state_cl82_RX_C 2 17627 #define tx_x4_credit_gen0_rxsm_state_cl82_RX_INIT 1 17628 17629 /**************************************************************************** 17630 * Enums: tx_x4_credit_gen0_deskew_state 17631 */ 17632 #define tx_x4_credit_gen0_deskew_state_ALIGN_ACQUIRED 2 17633 #define tx_x4_credit_gen0_deskew_state_LOSS_OF_ALIGNMENT 1 17634 17635 /**************************************************************************** 17636 * Enums: tx_x4_credit_gen0_os_mode_enum 17637 */ 17638 #define tx_x4_credit_gen0_os_mode_enum_OS_MODE_1 0 17639 #define tx_x4_credit_gen0_os_mode_enum_OS_MODE_2 1 17640 #define tx_x4_credit_gen0_os_mode_enum_OS_MODE_4 2 17641 #define tx_x4_credit_gen0_os_mode_enum_OS_MODE_16p5 8 17642 #define tx_x4_credit_gen0_os_mode_enum_OS_MODE_20p625 12 17643 17644 /**************************************************************************** 17645 * Enums: tx_x4_credit_gen0_scr_modes 17646 */ 17647 #define tx_x4_credit_gen0_scr_modes_T_SCR_MODE_BYPASS 0 17648 #define tx_x4_credit_gen0_scr_modes_T_SCR_MODE_CL49 1 17649 #define tx_x4_credit_gen0_scr_modes_T_SCR_MODE_40G_2_LANE 2 17650 #define tx_x4_credit_gen0_scr_modes_T_SCR_MODE_100G 3 17651 #define tx_x4_credit_gen0_scr_modes_T_SCR_MODE_20G 4 17652 #define tx_x4_credit_gen0_scr_modes_T_SCR_MODE_40G_4_LANE 5 17653 17654 /**************************************************************************** 17655 * Enums: tx_x4_credit_gen0_descr_modes 17656 */ 17657 #define tx_x4_credit_gen0_descr_modes_R_DESCR_MODE_BYPASS 0 17658 #define tx_x4_credit_gen0_descr_modes_R_DESCR_MODE_CL49 1 17659 #define tx_x4_credit_gen0_descr_modes_R_DESCR_MODE_CL82 2 17660 17661 /**************************************************************************** 17662 * Enums: tx_x4_credit_gen0_r_dec_tl_mode 17663 */ 17664 #define tx_x4_credit_gen0_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 17665 #define tx_x4_credit_gen0_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 17666 #define tx_x4_credit_gen0_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 17667 17668 /**************************************************************************** 17669 * Enums: tx_x4_credit_gen0_r_dec_fsm_mode 17670 */ 17671 #define tx_x4_credit_gen0_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 17672 #define tx_x4_credit_gen0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 17673 #define tx_x4_credit_gen0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 17674 17675 /**************************************************************************** 17676 * Enums: tx_x4_credit_gen0_r_deskew_mode 17677 */ 17678 #define tx_x4_credit_gen0_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 17679 #define tx_x4_credit_gen0_r_deskew_mode_R_DESKEW_MODE_20G 1 17680 #define tx_x4_credit_gen0_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 17681 #define tx_x4_credit_gen0_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 17682 #define tx_x4_credit_gen0_r_deskew_mode_R_DESKEW_MODE_100G 4 17683 #define tx_x4_credit_gen0_r_deskew_mode_R_DESKEW_MODE_CL49 5 17684 #define tx_x4_credit_gen0_r_deskew_mode_R_DESKEW_MODE_CL91 6 17685 17686 /**************************************************************************** 17687 * Enums: tx_x4_credit_gen0_bs_dist_modes 17688 */ 17689 #define tx_x4_credit_gen0_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 17690 #define tx_x4_credit_gen0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 17691 #define tx_x4_credit_gen0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 17692 #define tx_x4_credit_gen0_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 17693 17694 /**************************************************************************** 17695 * Enums: tx_x4_credit_gen0_cl49_t_type 17696 */ 17697 #define tx_x4_credit_gen0_cl49_t_type_BAD_T_TYPE 15 17698 #define tx_x4_credit_gen0_cl49_t_type_T_TYPE_B0 11 17699 #define tx_x4_credit_gen0_cl49_t_type_T_TYPE_OB 10 17700 #define tx_x4_credit_gen0_cl49_t_type_T_TYPE_B1 9 17701 #define tx_x4_credit_gen0_cl49_t_type_T_TYPE_DB 8 17702 #define tx_x4_credit_gen0_cl49_t_type_T_TYPE_FC 7 17703 #define tx_x4_credit_gen0_cl49_t_type_T_TYPE_TB 6 17704 #define tx_x4_credit_gen0_cl49_t_type_T_TYPE_LI 5 17705 #define tx_x4_credit_gen0_cl49_t_type_T_TYPE_C 4 17706 #define tx_x4_credit_gen0_cl49_t_type_T_TYPE_S 3 17707 #define tx_x4_credit_gen0_cl49_t_type_T_TYPE_T 2 17708 #define tx_x4_credit_gen0_cl49_t_type_T_TYPE_D 1 17709 #define tx_x4_credit_gen0_cl49_t_type_T_TYPE_E 0 17710 17711 /**************************************************************************** 17712 * Enums: tx_x4_credit_gen0_cl49_txsm_states 17713 */ 17714 #define tx_x4_credit_gen0_cl49_txsm_states_TX_HIG_END 7 17715 #define tx_x4_credit_gen0_cl49_txsm_states_TX_HIG_START 6 17716 #define tx_x4_credit_gen0_cl49_txsm_states_TX_LI 5 17717 #define tx_x4_credit_gen0_cl49_txsm_states_TX_E 4 17718 #define tx_x4_credit_gen0_cl49_txsm_states_TX_T 3 17719 #define tx_x4_credit_gen0_cl49_txsm_states_TX_D 2 17720 #define tx_x4_credit_gen0_cl49_txsm_states_TX_C 1 17721 #define tx_x4_credit_gen0_cl49_txsm_states_TX_INIT 0 17722 17723 /**************************************************************************** 17724 * Enums: tx_x4_credit_gen0_cl49_ltxsm_states 17725 */ 17726 #define tx_x4_credit_gen0_cl49_ltxsm_states_TX_HIG_END 128 17727 #define tx_x4_credit_gen0_cl49_ltxsm_states_TX_HIG_START 64 17728 #define tx_x4_credit_gen0_cl49_ltxsm_states_TX_LI 32 17729 #define tx_x4_credit_gen0_cl49_ltxsm_states_TX_E 16 17730 #define tx_x4_credit_gen0_cl49_ltxsm_states_TX_T 8 17731 #define tx_x4_credit_gen0_cl49_ltxsm_states_TX_D 4 17732 #define tx_x4_credit_gen0_cl49_ltxsm_states_TX_C 2 17733 #define tx_x4_credit_gen0_cl49_ltxsm_states_TX_INIT 1 17734 17735 /**************************************************************************** 17736 * Enums: tx_x4_credit_gen0_burst_error_mode 17737 */ 17738 #define tx_x4_credit_gen0_burst_error_mode_BURST_ERROR_11_BITS 0 17739 #define tx_x4_credit_gen0_burst_error_mode_BURST_ERROR_16_BITS 1 17740 #define tx_x4_credit_gen0_burst_error_mode_BURST_ERROR_17_BITS 2 17741 #define tx_x4_credit_gen0_burst_error_mode_BURST_ERROR_18_BITS 3 17742 #define tx_x4_credit_gen0_burst_error_mode_BURST_ERROR_19_BITS 4 17743 #define tx_x4_credit_gen0_burst_error_mode_BURST_ERROR_20_BITS 5 17744 #define tx_x4_credit_gen0_burst_error_mode_BURST_ERROR_21_BITS 6 17745 #define tx_x4_credit_gen0_burst_error_mode_BURST_ERROR_22_BITS 7 17746 #define tx_x4_credit_gen0_burst_error_mode_BURST_ERROR_23_BITS 8 17747 #define tx_x4_credit_gen0_burst_error_mode_BURST_ERROR_24_BITS 9 17748 #define tx_x4_credit_gen0_burst_error_mode_BURST_ERROR_25_BITS 10 17749 #define tx_x4_credit_gen0_burst_error_mode_BURST_ERROR_26_BITS 11 17750 #define tx_x4_credit_gen0_burst_error_mode_BURST_ERROR_27_BITS 12 17751 #define tx_x4_credit_gen0_burst_error_mode_BURST_ERROR_28_BITS 13 17752 #define tx_x4_credit_gen0_burst_error_mode_BURST_ERROR_29_BITS 14 17753 #define tx_x4_credit_gen0_burst_error_mode_BURST_ERROR_30_BITS 15 17754 #define tx_x4_credit_gen0_burst_error_mode_BURST_ERROR_31_BITS 16 17755 #define tx_x4_credit_gen0_burst_error_mode_BURST_ERROR_32_BITS 17 17756 #define tx_x4_credit_gen0_burst_error_mode_BURST_ERROR_33_BITS 18 17757 #define tx_x4_credit_gen0_burst_error_mode_BURST_ERROR_34_BITS 19 17758 #define tx_x4_credit_gen0_burst_error_mode_BURST_ERROR_35_BITS 20 17759 #define tx_x4_credit_gen0_burst_error_mode_BURST_ERROR_36_BITS 21 17760 #define tx_x4_credit_gen0_burst_error_mode_BURST_ERROR_37_BITS 22 17761 #define tx_x4_credit_gen0_burst_error_mode_BURST_ERROR_38_BITS 23 17762 #define tx_x4_credit_gen0_burst_error_mode_BURST_ERROR_39_BITS 24 17763 #define tx_x4_credit_gen0_burst_error_mode_BURST_ERROR_40_BITS 25 17764 #define tx_x4_credit_gen0_burst_error_mode_BURST_ERROR_41_BITS 26 17765 17766 /**************************************************************************** 17767 * Enums: tx_x4_credit_gen0_bermon_state 17768 */ 17769 #define tx_x4_credit_gen0_bermon_state_HI_BER 4 17770 #define tx_x4_credit_gen0_bermon_state_GOOD_BER 3 17771 #define tx_x4_credit_gen0_bermon_state_BER_TEST_SH 2 17772 #define tx_x4_credit_gen0_bermon_state_START_TIMER 1 17773 #define tx_x4_credit_gen0_bermon_state_BER_MT_INIT 0 17774 17775 /**************************************************************************** 17776 * Enums: tx_x4_credit_gen0_rxsm_state_cl49 17777 */ 17778 #define tx_x4_credit_gen0_rxsm_state_cl49_RX_HIG_END 128 17779 #define tx_x4_credit_gen0_rxsm_state_cl49_RX_HIG_START 64 17780 #define tx_x4_credit_gen0_rxsm_state_cl49_RX_LI 32 17781 #define tx_x4_credit_gen0_rxsm_state_cl49_RX_E 16 17782 #define tx_x4_credit_gen0_rxsm_state_cl49_RX_T 8 17783 #define tx_x4_credit_gen0_rxsm_state_cl49_RX_D 4 17784 #define tx_x4_credit_gen0_rxsm_state_cl49_RX_C 2 17785 #define tx_x4_credit_gen0_rxsm_state_cl49_RX_INIT 1 17786 17787 /**************************************************************************** 17788 * Enums: tx_x4_credit_gen0_r_type 17789 */ 17790 #define tx_x4_credit_gen0_r_type_BAD_R_TYPE 15 17791 #define tx_x4_credit_gen0_r_type_R_TYPE_B0 11 17792 #define tx_x4_credit_gen0_r_type_R_TYPE_OB 10 17793 #define tx_x4_credit_gen0_r_type_R_TYPE_B1 9 17794 #define tx_x4_credit_gen0_r_type_R_TYPE_DB 8 17795 #define tx_x4_credit_gen0_r_type_R_TYPE_FC 7 17796 #define tx_x4_credit_gen0_r_type_R_TYPE_TB 6 17797 #define tx_x4_credit_gen0_r_type_R_TYPE_LI 5 17798 #define tx_x4_credit_gen0_r_type_R_TYPE_C 4 17799 #define tx_x4_credit_gen0_r_type_R_TYPE_S 3 17800 #define tx_x4_credit_gen0_r_type_R_TYPE_T 2 17801 #define tx_x4_credit_gen0_r_type_R_TYPE_D 1 17802 #define tx_x4_credit_gen0_r_type_R_TYPE_E 0 17803 17804 /**************************************************************************** 17805 * Enums: tx_x4_credit_gen0_am_lock_state 17806 */ 17807 #define tx_x4_credit_gen0_am_lock_state_INVALID_AM 512 17808 #define tx_x4_credit_gen0_am_lock_state_GOOD_AM 256 17809 #define tx_x4_credit_gen0_am_lock_state_COMP_AM 128 17810 #define tx_x4_credit_gen0_am_lock_state_TIMER_2 64 17811 #define tx_x4_credit_gen0_am_lock_state_AM_2_GOOD 32 17812 #define tx_x4_credit_gen0_am_lock_state_COMP_2ND 16 17813 #define tx_x4_credit_gen0_am_lock_state_TIMER_1 8 17814 #define tx_x4_credit_gen0_am_lock_state_FIND_1ST 4 17815 #define tx_x4_credit_gen0_am_lock_state_AM_RESET_CNT 2 17816 #define tx_x4_credit_gen0_am_lock_state_AM_LOCK_INIT 1 17817 17818 /**************************************************************************** 17819 * Enums: tx_x4_credit_gen0_msg_selector 17820 */ 17821 #define tx_x4_credit_gen0_msg_selector_RESERVED 0 17822 #define tx_x4_credit_gen0_msg_selector_VALUE_802p3 1 17823 #define tx_x4_credit_gen0_msg_selector_VALUE_802p9 2 17824 #define tx_x4_credit_gen0_msg_selector_VALUE_802p5 3 17825 #define tx_x4_credit_gen0_msg_selector_VALUE_1394 4 17826 17827 /**************************************************************************** 17828 * Enums: tx_x4_credit_gen0_synce_enum 17829 */ 17830 #define tx_x4_credit_gen0_synce_enum_SYNCE_NO_DIV 0 17831 #define tx_x4_credit_gen0_synce_enum_SYNCE_DIV_7 1 17832 #define tx_x4_credit_gen0_synce_enum_SYNCE_DIV_11 2 17833 17834 /**************************************************************************** 17835 * Enums: tx_x4_credit_gen0_synce_enum_stage0 17836 */ 17837 #define tx_x4_credit_gen0_synce_enum_stage0_SYNCE_NO_DIV 0 17838 #define tx_x4_credit_gen0_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 17839 #define tx_x4_credit_gen0_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 17840 17841 /**************************************************************************** 17842 * Enums: tx_x4_credit_gen0_cl91_sync_state 17843 */ 17844 #define tx_x4_credit_gen0_cl91_sync_state_FIND_1ST 0 17845 #define tx_x4_credit_gen0_cl91_sync_state_COUNT_NEXT 1 17846 #define tx_x4_credit_gen0_cl91_sync_state_COMP_2ND 2 17847 #define tx_x4_credit_gen0_cl91_sync_state_TWO_GOOD 3 17848 17849 /**************************************************************************** 17850 * Enums: tx_x4_credit_gen0_cl91_algn_state 17851 */ 17852 #define tx_x4_credit_gen0_cl91_algn_state_LOSS_OF_ALIGNMENT 0 17853 #define tx_x4_credit_gen0_cl91_algn_state_DESKEW 1 17854 #define tx_x4_credit_gen0_cl91_algn_state_DESKEW_FAIL 2 17855 #define tx_x4_credit_gen0_cl91_algn_state_ALIGN_ACQUIRED 3 17856 #define tx_x4_credit_gen0_cl91_algn_state_CW_GOOD 4 17857 #define tx_x4_credit_gen0_cl91_algn_state_CW_BAD 5 17858 #define tx_x4_credit_gen0_cl91_algn_state_THREE_BAD 6 17859 17860 /**************************************************************************** 17861 * Enums: tx_x4_credit_gen0_fec_sel 17862 */ 17863 #define tx_x4_credit_gen0_fec_sel_NO_FEC 0 17864 #define tx_x4_credit_gen0_fec_sel_FEC_CL74 1 17865 #define tx_x4_credit_gen0_fec_sel_FEC_CL91 2 17866 17867 /**************************************************************************** 17868 * Enums: tx_x4_status0_cl36TxEEEStates_l 17869 */ 17870 #define tx_x4_status0_cl36TxEEEStates_l_TX_REFRESH 8 17871 #define tx_x4_status0_cl36TxEEEStates_l_TX_QUIET 4 17872 #define tx_x4_status0_cl36TxEEEStates_l_TX_SLEEP 2 17873 #define tx_x4_status0_cl36TxEEEStates_l_TX_ACTIVE 1 17874 17875 /**************************************************************************** 17876 * Enums: tx_x4_status0_cl36TxEEEStates_c 17877 */ 17878 #define tx_x4_status0_cl36TxEEEStates_c_TX_REFRESH 3 17879 #define tx_x4_status0_cl36TxEEEStates_c_TX_QUIET 2 17880 #define tx_x4_status0_cl36TxEEEStates_c_TX_SLEEP 1 17881 #define tx_x4_status0_cl36TxEEEStates_c_TX_ACTIVE 0 17882 17883 /**************************************************************************** 17884 * Enums: tx_x4_status0_cl49TxEEEStates_l 17885 */ 17886 #define tx_x4_status0_cl49TxEEEStates_l_SCR_RESET_2 64 17887 #define tx_x4_status0_cl49TxEEEStates_l_SCR_RESET_1 32 17888 #define tx_x4_status0_cl49TxEEEStates_l_TX_WAKE 16 17889 #define tx_x4_status0_cl49TxEEEStates_l_TX_REFRESH 8 17890 #define tx_x4_status0_cl49TxEEEStates_l_TX_QUIET 4 17891 #define tx_x4_status0_cl49TxEEEStates_l_TX_SLEEP 2 17892 #define tx_x4_status0_cl49TxEEEStates_l_TX_ACTIVE 1 17893 17894 /**************************************************************************** 17895 * Enums: tx_x4_status0_fec_req_enum 17896 */ 17897 #define tx_x4_status0_fec_req_enum_FEC_not_supported 0 17898 #define tx_x4_status0_fec_req_enum_FEC_supported_but_not_requested 1 17899 #define tx_x4_status0_fec_req_enum_invalid_setting 2 17900 #define tx_x4_status0_fec_req_enum_FEC_supported_and_requested 3 17901 17902 /**************************************************************************** 17903 * Enums: tx_x4_status0_cl73_pause_enum 17904 */ 17905 #define tx_x4_status0_cl73_pause_enum_No_PAUSE_ability 0 17906 #define tx_x4_status0_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 17907 #define tx_x4_status0_cl73_pause_enum_Symmetric_PAUSE_ability 1 17908 #define tx_x4_status0_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 17909 17910 /**************************************************************************** 17911 * Enums: tx_x4_status0_cl49TxEEEStates_c 17912 */ 17913 #define tx_x4_status0_cl49TxEEEStates_c_SCR_RESET_2 6 17914 #define tx_x4_status0_cl49TxEEEStates_c_SCR_RESET_1 5 17915 #define tx_x4_status0_cl49TxEEEStates_c_TX_WAKE 4 17916 #define tx_x4_status0_cl49TxEEEStates_c_TX_REFRESH 3 17917 #define tx_x4_status0_cl49TxEEEStates_c_TX_QUIET 2 17918 #define tx_x4_status0_cl49TxEEEStates_c_TX_SLEEP 1 17919 #define tx_x4_status0_cl49TxEEEStates_c_TX_ACTIVE 0 17920 17921 /**************************************************************************** 17922 * Enums: tx_x4_status0_cl36RxEEEStates_l 17923 */ 17924 #define tx_x4_status0_cl36RxEEEStates_l_RX_LINK_FAIL 32 17925 #define tx_x4_status0_cl36RxEEEStates_l_RX_WTF 16 17926 #define tx_x4_status0_cl36RxEEEStates_l_RX_WAKE 8 17927 #define tx_x4_status0_cl36RxEEEStates_l_RX_QUIET 4 17928 #define tx_x4_status0_cl36RxEEEStates_l_RX_SLEEP 2 17929 #define tx_x4_status0_cl36RxEEEStates_l_RX_ACTIVE 1 17930 17931 /**************************************************************************** 17932 * Enums: tx_x4_status0_cl36RxEEEStates_c 17933 */ 17934 #define tx_x4_status0_cl36RxEEEStates_c_RX_LINK_FAIL 5 17935 #define tx_x4_status0_cl36RxEEEStates_c_RX_WTF 4 17936 #define tx_x4_status0_cl36RxEEEStates_c_RX_WAKE 3 17937 #define tx_x4_status0_cl36RxEEEStates_c_RX_QUIET 2 17938 #define tx_x4_status0_cl36RxEEEStates_c_RX_SLEEP 1 17939 #define tx_x4_status0_cl36RxEEEStates_c_RX_ACTIVE 0 17940 17941 /**************************************************************************** 17942 * Enums: tx_x4_status0_cl49RxEEEStates_l 17943 */ 17944 #define tx_x4_status0_cl49RxEEEStates_l_RX_LINK_FAIL 32 17945 #define tx_x4_status0_cl49RxEEEStates_l_RX_WTF 16 17946 #define tx_x4_status0_cl49RxEEEStates_l_RX_WAKE 8 17947 #define tx_x4_status0_cl49RxEEEStates_l_RX_QUIET 4 17948 #define tx_x4_status0_cl49RxEEEStates_l_RX_SLEEP 2 17949 #define tx_x4_status0_cl49RxEEEStates_l_RX_ACTIVE 1 17950 17951 /**************************************************************************** 17952 * Enums: tx_x4_status0_cl49RxEEEStates_c 17953 */ 17954 #define tx_x4_status0_cl49RxEEEStates_c_RX_LINK_FAIL 5 17955 #define tx_x4_status0_cl49RxEEEStates_c_RX_WTF 4 17956 #define tx_x4_status0_cl49RxEEEStates_c_RX_WAKE 3 17957 #define tx_x4_status0_cl49RxEEEStates_c_RX_QUIET 2 17958 #define tx_x4_status0_cl49RxEEEStates_c_RX_SLEEP 1 17959 #define tx_x4_status0_cl49RxEEEStates_c_RX_ACTIVE 0 17960 17961 /**************************************************************************** 17962 * Enums: tx_x4_status0_cl48TxEEEStates_l 17963 */ 17964 #define tx_x4_status0_cl48TxEEEStates_l_TX_REFRESH 8 17965 #define tx_x4_status0_cl48TxEEEStates_l_TX_QUIET 4 17966 #define tx_x4_status0_cl48TxEEEStates_l_TX_SLEEP 2 17967 #define tx_x4_status0_cl48TxEEEStates_l_TX_ACTIVE 1 17968 17969 /**************************************************************************** 17970 * Enums: tx_x4_status0_cl48TxEEEStates_c 17971 */ 17972 #define tx_x4_status0_cl48TxEEEStates_c_TX_REFRESH 3 17973 #define tx_x4_status0_cl48TxEEEStates_c_TX_QUIET 2 17974 #define tx_x4_status0_cl48TxEEEStates_c_TX_SLEEP 1 17975 #define tx_x4_status0_cl48TxEEEStates_c_TX_ACTIVE 0 17976 17977 /**************************************************************************** 17978 * Enums: tx_x4_status0_cl48RxEEEStates_l 17979 */ 17980 #define tx_x4_status0_cl48RxEEEStates_l_RX_LINK_FAIL 32 17981 #define tx_x4_status0_cl48RxEEEStates_l_RX_WAKE 16 17982 #define tx_x4_status0_cl48RxEEEStates_l_RX_QUIET 8 17983 #define tx_x4_status0_cl48RxEEEStates_l_RX_DEACT 4 17984 #define tx_x4_status0_cl48RxEEEStates_l_RX_SLEEP 2 17985 #define tx_x4_status0_cl48RxEEEStates_l_RX_ACTIVE 1 17986 17987 /**************************************************************************** 17988 * Enums: tx_x4_status0_cl48RxEEEStates_c 17989 */ 17990 #define tx_x4_status0_cl48RxEEEStates_c_RX_LINK_FAIL 5 17991 #define tx_x4_status0_cl48RxEEEStates_c_RX_WAKE 4 17992 #define tx_x4_status0_cl48RxEEEStates_c_RX_QUIET 3 17993 #define tx_x4_status0_cl48RxEEEStates_c_RX_DEACT 2 17994 #define tx_x4_status0_cl48RxEEEStates_c_RX_SLEEP 1 17995 #define tx_x4_status0_cl48RxEEEStates_c_RX_ACTIVE 0 17996 17997 /**************************************************************************** 17998 * Enums: tx_x4_status0_IQP_Options 17999 */ 18000 #define tx_x4_status0_IQP_Options_i50uA 0 18001 #define tx_x4_status0_IQP_Options_i100uA 1 18002 #define tx_x4_status0_IQP_Options_i150uA 2 18003 #define tx_x4_status0_IQP_Options_i200uA 3 18004 #define tx_x4_status0_IQP_Options_i250uA 4 18005 #define tx_x4_status0_IQP_Options_i300uA 5 18006 #define tx_x4_status0_IQP_Options_i350uA 6 18007 #define tx_x4_status0_IQP_Options_i400uA 7 18008 #define tx_x4_status0_IQP_Options_i450uA 8 18009 #define tx_x4_status0_IQP_Options_i500uA 9 18010 #define tx_x4_status0_IQP_Options_i550uA 10 18011 #define tx_x4_status0_IQP_Options_i600uA 11 18012 #define tx_x4_status0_IQP_Options_i650uA 12 18013 #define tx_x4_status0_IQP_Options_i700uA 13 18014 #define tx_x4_status0_IQP_Options_i750uA 14 18015 #define tx_x4_status0_IQP_Options_i800uA 15 18016 18017 /**************************************************************************** 18018 * Enums: tx_x4_status0_IDriver_Options 18019 */ 18020 #define tx_x4_status0_IDriver_Options_v680mV 0 18021 #define tx_x4_status0_IDriver_Options_v730mV 1 18022 #define tx_x4_status0_IDriver_Options_v780mV 2 18023 #define tx_x4_status0_IDriver_Options_v830mV 3 18024 #define tx_x4_status0_IDriver_Options_v880mV 4 18025 #define tx_x4_status0_IDriver_Options_v930mV 5 18026 #define tx_x4_status0_IDriver_Options_v980mV 6 18027 #define tx_x4_status0_IDriver_Options_v1010mV 7 18028 #define tx_x4_status0_IDriver_Options_v1040mV 8 18029 #define tx_x4_status0_IDriver_Options_v1060mV 9 18030 #define tx_x4_status0_IDriver_Options_v1070mV 10 18031 #define tx_x4_status0_IDriver_Options_v1080mV 11 18032 #define tx_x4_status0_IDriver_Options_v1085mV 12 18033 #define tx_x4_status0_IDriver_Options_v1090mV 13 18034 #define tx_x4_status0_IDriver_Options_v1095mV 14 18035 #define tx_x4_status0_IDriver_Options_v1100mV 15 18036 18037 /**************************************************************************** 18038 * Enums: tx_x4_status0_operationModes 18039 */ 18040 #define tx_x4_status0_operationModes_XGXS 0 18041 #define tx_x4_status0_operationModes_XGXG_nCC 1 18042 #define tx_x4_status0_operationModes_Indlane_OS8 4 18043 #define tx_x4_status0_operationModes_IndLane_OS5 5 18044 #define tx_x4_status0_operationModes_PCI 7 18045 #define tx_x4_status0_operationModes_XGXS_nLQ 8 18046 #define tx_x4_status0_operationModes_XGXS_nLQnCC 9 18047 #define tx_x4_status0_operationModes_PBypass 10 18048 #define tx_x4_status0_operationModes_PBypass_nDSK 11 18049 #define tx_x4_status0_operationModes_ComboCoreMode 12 18050 #define tx_x4_status0_operationModes_Clocks_off 15 18051 18052 /**************************************************************************** 18053 * Enums: tx_x4_status0_actualSpeeds 18054 */ 18055 #define tx_x4_status0_actualSpeeds_dr_10M 0 18056 #define tx_x4_status0_actualSpeeds_dr_100M 1 18057 #define tx_x4_status0_actualSpeeds_dr_1G 2 18058 #define tx_x4_status0_actualSpeeds_dr_2p5G 3 18059 #define tx_x4_status0_actualSpeeds_dr_5G_X4 4 18060 #define tx_x4_status0_actualSpeeds_dr_6G_X4 5 18061 #define tx_x4_status0_actualSpeeds_dr_10G_HiG 6 18062 #define tx_x4_status0_actualSpeeds_dr_10G_CX4 7 18063 #define tx_x4_status0_actualSpeeds_dr_12G_HiG 8 18064 #define tx_x4_status0_actualSpeeds_dr_12p5G_X4 9 18065 #define tx_x4_status0_actualSpeeds_dr_13G_X4 10 18066 #define tx_x4_status0_actualSpeeds_dr_15G_X4 11 18067 #define tx_x4_status0_actualSpeeds_dr_16G_X4 12 18068 #define tx_x4_status0_actualSpeeds_dr_1G_KX 13 18069 #define tx_x4_status0_actualSpeeds_dr_10G_KX4 14 18070 #define tx_x4_status0_actualSpeeds_dr_10G_KR 15 18071 #define tx_x4_status0_actualSpeeds_dr_5G 16 18072 #define tx_x4_status0_actualSpeeds_dr_6p4G 17 18073 #define tx_x4_status0_actualSpeeds_dr_20G_X4 18 18074 #define tx_x4_status0_actualSpeeds_dr_21G_X4 19 18075 #define tx_x4_status0_actualSpeeds_dr_25G_X4 20 18076 #define tx_x4_status0_actualSpeeds_dr_10G_HiG_DXGXS 21 18077 #define tx_x4_status0_actualSpeeds_dr_10G_DXGXS 22 18078 #define tx_x4_status0_actualSpeeds_dr_10p5G_HiG_DXGXS 23 18079 #define tx_x4_status0_actualSpeeds_dr_10p5G_DXGXS 24 18080 #define tx_x4_status0_actualSpeeds_dr_12p773G_HiG_DXGXS 25 18081 #define tx_x4_status0_actualSpeeds_dr_12p773G_DXGXS 26 18082 #define tx_x4_status0_actualSpeeds_dr_10G_XFI 27 18083 #define tx_x4_status0_actualSpeeds_dr_40G 28 18084 #define tx_x4_status0_actualSpeeds_dr_20G_HiG_DXGXS 29 18085 #define tx_x4_status0_actualSpeeds_dr_20G_DXGXS 30 18086 #define tx_x4_status0_actualSpeeds_dr_10G_SFI 31 18087 #define tx_x4_status0_actualSpeeds_dr_31p5G 32 18088 #define tx_x4_status0_actualSpeeds_dr_32p7G 33 18089 #define tx_x4_status0_actualSpeeds_dr_20G_SCR 34 18090 #define tx_x4_status0_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 18091 #define tx_x4_status0_actualSpeeds_dr_10G_DXGXS_SCR 36 18092 #define tx_x4_status0_actualSpeeds_dr_12G_R2 37 18093 #define tx_x4_status0_actualSpeeds_dr_10G_X2 38 18094 #define tx_x4_status0_actualSpeeds_dr_40G_KR4 39 18095 #define tx_x4_status0_actualSpeeds_dr_40G_CR4 40 18096 #define tx_x4_status0_actualSpeeds_dr_100G_CR10 41 18097 #define tx_x4_status0_actualSpeeds_dr_15p75G_DXGXS 44 18098 #define tx_x4_status0_actualSpeeds_dr_20G_KR2 57 18099 #define tx_x4_status0_actualSpeeds_dr_20G_CR2 58 18100 18101 /**************************************************************************** 18102 * Enums: tx_x4_status0_actualSpeedsMisc1 18103 */ 18104 #define tx_x4_status0_actualSpeedsMisc1_dr_2500BRCM_X1 16 18105 #define tx_x4_status0_actualSpeedsMisc1_dr_5000BRCM_X4 17 18106 #define tx_x4_status0_actualSpeedsMisc1_dr_6000BRCM_X4 18 18107 #define tx_x4_status0_actualSpeedsMisc1_dr_10GHiGig_X4 19 18108 #define tx_x4_status0_actualSpeedsMisc1_dr_10GBASE_CX4 20 18109 #define tx_x4_status0_actualSpeedsMisc1_dr_12GHiGig_X4 21 18110 #define tx_x4_status0_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 18111 #define tx_x4_status0_actualSpeedsMisc1_dr_13GHiGig_X4 23 18112 #define tx_x4_status0_actualSpeedsMisc1_dr_15GHiGig_X4 24 18113 #define tx_x4_status0_actualSpeedsMisc1_dr_16GHiGig_X4 25 18114 #define tx_x4_status0_actualSpeedsMisc1_dr_5000BRCM_X1 26 18115 #define tx_x4_status0_actualSpeedsMisc1_dr_6363BRCM_X1 27 18116 #define tx_x4_status0_actualSpeedsMisc1_dr_20GHiGig_X4 28 18117 #define tx_x4_status0_actualSpeedsMisc1_dr_21GHiGig_X4 29 18118 #define tx_x4_status0_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 18119 #define tx_x4_status0_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 18120 18121 /**************************************************************************** 18122 * Enums: tx_x4_status0_IndLaneModes 18123 */ 18124 #define tx_x4_status0_IndLaneModes_SWSDR_div2 0 18125 #define tx_x4_status0_IndLaneModes_SWSDR_div1 1 18126 #define tx_x4_status0_IndLaneModes_DWSDR_div2 2 18127 #define tx_x4_status0_IndLaneModes_DWSDR_div1 3 18128 18129 /**************************************************************************** 18130 * Enums: tx_x4_status0_prbsSelect 18131 */ 18132 #define tx_x4_status0_prbsSelect_prbs7 0 18133 #define tx_x4_status0_prbsSelect_prbs15 1 18134 #define tx_x4_status0_prbsSelect_prbs23 2 18135 #define tx_x4_status0_prbsSelect_prbs31 3 18136 18137 /**************************************************************************** 18138 * Enums: tx_x4_status0_vcoDivider 18139 */ 18140 #define tx_x4_status0_vcoDivider_div32 0 18141 #define tx_x4_status0_vcoDivider_div36 1 18142 #define tx_x4_status0_vcoDivider_div40 2 18143 #define tx_x4_status0_vcoDivider_div42 3 18144 #define tx_x4_status0_vcoDivider_div48 4 18145 #define tx_x4_status0_vcoDivider_div50 5 18146 #define tx_x4_status0_vcoDivider_div52 6 18147 #define tx_x4_status0_vcoDivider_div54 7 18148 #define tx_x4_status0_vcoDivider_div60 8 18149 #define tx_x4_status0_vcoDivider_div64 9 18150 #define tx_x4_status0_vcoDivider_div66 10 18151 #define tx_x4_status0_vcoDivider_div68 11 18152 #define tx_x4_status0_vcoDivider_div70 12 18153 #define tx_x4_status0_vcoDivider_div80 13 18154 #define tx_x4_status0_vcoDivider_div92 14 18155 #define tx_x4_status0_vcoDivider_div100 15 18156 18157 /**************************************************************************** 18158 * Enums: tx_x4_status0_refClkSelect 18159 */ 18160 #define tx_x4_status0_refClkSelect_clk_25MHz 0 18161 #define tx_x4_status0_refClkSelect_clk_100MHz 1 18162 #define tx_x4_status0_refClkSelect_clk_125MHz 2 18163 #define tx_x4_status0_refClkSelect_clk_156p25MHz 3 18164 #define tx_x4_status0_refClkSelect_clk_187p5MHz 4 18165 #define tx_x4_status0_refClkSelect_clk_161p25Mhz 5 18166 #define tx_x4_status0_refClkSelect_clk_50Mhz 6 18167 #define tx_x4_status0_refClkSelect_clk_106p25Mhz 7 18168 18169 /**************************************************************************** 18170 * Enums: tx_x4_status0_aerMMDdevTypeSelect 18171 */ 18172 #define tx_x4_status0_aerMMDdevTypeSelect_combo_core 0 18173 #define tx_x4_status0_aerMMDdevTypeSelect_PMA_PMD 1 18174 #define tx_x4_status0_aerMMDdevTypeSelect_PCS 3 18175 #define tx_x4_status0_aerMMDdevTypeSelect_PHY 4 18176 #define tx_x4_status0_aerMMDdevTypeSelect_DTE 5 18177 #define tx_x4_status0_aerMMDdevTypeSelect_CL73_AN 7 18178 18179 /**************************************************************************** 18180 * Enums: tx_x4_status0_aerMMDportSelect 18181 */ 18182 #define tx_x4_status0_aerMMDportSelect_ln0 0 18183 #define tx_x4_status0_aerMMDportSelect_ln1 1 18184 #define tx_x4_status0_aerMMDportSelect_ln2 2 18185 #define tx_x4_status0_aerMMDportSelect_ln3 3 18186 #define tx_x4_status0_aerMMDportSelect_BCST_ln0_1_2_3 511 18187 #define tx_x4_status0_aerMMDportSelect_BCST_ln0_1 512 18188 #define tx_x4_status0_aerMMDportSelect_BCST_ln2_3 513 18189 18190 /**************************************************************************** 18191 * Enums: tx_x4_status0_firmwareModeSelect 18192 */ 18193 #define tx_x4_status0_firmwareModeSelect_DEFAULT 0 18194 #define tx_x4_status0_firmwareModeSelect_SFP_OPT_LR 1 18195 #define tx_x4_status0_firmwareModeSelect_SFP_DAC 2 18196 #define tx_x4_status0_firmwareModeSelect_XLAUI 3 18197 #define tx_x4_status0_firmwareModeSelect_LONG_CH_6G 4 18198 18199 /**************************************************************************** 18200 * Enums: tx_x4_status0_tempIdxSelect 18201 */ 18202 #define tx_x4_status0_tempIdxSelect_LTE__22p9C 15 18203 #define tx_x4_status0_tempIdxSelect_LTE__12p6C 14 18204 #define tx_x4_status0_tempIdxSelect_LTE__3p0C 13 18205 #define tx_x4_status0_tempIdxSelect_LTE_6p7C 12 18206 #define tx_x4_status0_tempIdxSelect_LTE_16p4C 11 18207 #define tx_x4_status0_tempIdxSelect_LTE_26p6C 10 18208 #define tx_x4_status0_tempIdxSelect_LTE_36p3C 9 18209 #define tx_x4_status0_tempIdxSelect_LTE_46p0C 8 18210 #define tx_x4_status0_tempIdxSelect_LTE_56p2C 7 18211 #define tx_x4_status0_tempIdxSelect_LTE_65p9C 6 18212 #define tx_x4_status0_tempIdxSelect_LTE_75p6C 5 18213 #define tx_x4_status0_tempIdxSelect_LTE_85p3C 4 18214 #define tx_x4_status0_tempIdxSelect_LTE_95p5C 3 18215 #define tx_x4_status0_tempIdxSelect_LTE_105p2C 2 18216 #define tx_x4_status0_tempIdxSelect_LTE_114p9C 1 18217 #define tx_x4_status0_tempIdxSelect_LTE_125p1C 0 18218 18219 /**************************************************************************** 18220 * Enums: tx_x4_status0_port_mode 18221 */ 18222 #define tx_x4_status0_port_mode_QUAD_PORT 0 18223 #define tx_x4_status0_port_mode_TRI_1_PORT 1 18224 #define tx_x4_status0_port_mode_TRI_2_PORT 2 18225 #define tx_x4_status0_port_mode_DUAL_PORT 3 18226 #define tx_x4_status0_port_mode_SINGLE_PORT 4 18227 18228 /**************************************************************************** 18229 * Enums: tx_x4_status0_rev_letter_enum 18230 */ 18231 #define tx_x4_status0_rev_letter_enum_REV_A 0 18232 #define tx_x4_status0_rev_letter_enum_REV_B 1 18233 #define tx_x4_status0_rev_letter_enum_REV_C 2 18234 #define tx_x4_status0_rev_letter_enum_REV_D 3 18235 18236 /**************************************************************************** 18237 * Enums: tx_x4_status0_rev_number_enum 18238 */ 18239 #define tx_x4_status0_rev_number_enum_REV_0 0 18240 #define tx_x4_status0_rev_number_enum_REV_1 1 18241 #define tx_x4_status0_rev_number_enum_REV_2 2 18242 #define tx_x4_status0_rev_number_enum_REV_3 3 18243 #define tx_x4_status0_rev_number_enum_REV_4 4 18244 #define tx_x4_status0_rev_number_enum_REV_5 5 18245 #define tx_x4_status0_rev_number_enum_REV_6 6 18246 #define tx_x4_status0_rev_number_enum_REV_7 7 18247 18248 /**************************************************************************** 18249 * Enums: tx_x4_status0_bonding_enum 18250 */ 18251 #define tx_x4_status0_bonding_enum_WIRE_BOND 0 18252 #define tx_x4_status0_bonding_enum_FLIP_CHIP 1 18253 18254 /**************************************************************************** 18255 * Enums: tx_x4_status0_tech_process 18256 */ 18257 #define tx_x4_status0_tech_process_PROCESS_90NM 0 18258 #define tx_x4_status0_tech_process_PROCESS_65NM 1 18259 #define tx_x4_status0_tech_process_PROCESS_40NM 2 18260 #define tx_x4_status0_tech_process_PROCESS_28NM 3 18261 18262 /**************************************************************************** 18263 * Enums: tx_x4_status0_model_num 18264 */ 18265 #define tx_x4_status0_model_num_SERDES_CL73 0 18266 #define tx_x4_status0_model_num_XGXS_16G 1 18267 #define tx_x4_status0_model_num_HYPERCORE 2 18268 #define tx_x4_status0_model_num_HYPERLITE 3 18269 #define tx_x4_status0_model_num_PCIE_G2_PIPE 4 18270 #define tx_x4_status0_model_num_SERDES_1p25GBd 5 18271 #define tx_x4_status0_model_num_SATA2 6 18272 #define tx_x4_status0_model_num_QSGMII 7 18273 #define tx_x4_status0_model_num_XGXS10G 8 18274 #define tx_x4_status0_model_num_WARPCORE 9 18275 #define tx_x4_status0_model_num_XFICORE 10 18276 #define tx_x4_status0_model_num_RXFI 11 18277 #define tx_x4_status0_model_num_WARPLITE 12 18278 #define tx_x4_status0_model_num_PENTACORE 13 18279 #define tx_x4_status0_model_num_ESM 14 18280 #define tx_x4_status0_model_num_QUAD_SGMII 15 18281 #define tx_x4_status0_model_num_WARPCORE_3 16 18282 #define tx_x4_status0_model_num_TSC 17 18283 #define tx_x4_status0_model_num_TSC4E 18 18284 #define tx_x4_status0_model_num_TSC12E 19 18285 #define tx_x4_status0_model_num_TSC4F 20 18286 #define tx_x4_status0_model_num_XGXS_CL73_90NM 29 18287 #define tx_x4_status0_model_num_SERDES_CL73_90NM 30 18288 #define tx_x4_status0_model_num_WARPCORE3 32 18289 #define tx_x4_status0_model_num_WARPCORE4_TSC 33 18290 #define tx_x4_status0_model_num_RXAUI 34 18291 18292 /**************************************************************************** 18293 * Enums: tx_x4_status0_payload 18294 */ 18295 #define tx_x4_status0_payload_REPEAT_2_BYTES 0 18296 #define tx_x4_status0_payload_RAMPING 1 18297 #define tx_x4_status0_payload_CL48_CRPAT 2 18298 #define tx_x4_status0_payload_CL48_CJPAT 3 18299 #define tx_x4_status0_payload_CL36_LONG_CRPAT 4 18300 #define tx_x4_status0_payload_CL36_SHORT_CRPAT 5 18301 18302 /**************************************************************************** 18303 * Enums: tx_x4_status0_sc 18304 */ 18305 #define tx_x4_status0_sc_S_10G_CR1 0 18306 #define tx_x4_status0_sc_S_10G_KR1 1 18307 #define tx_x4_status0_sc_S_10G_X1 2 18308 #define tx_x4_status0_sc_S_10G_HG2_CR1 4 18309 #define tx_x4_status0_sc_S_10G_HG2_KR1 5 18310 #define tx_x4_status0_sc_S_10G_HG2_X1 6 18311 #define tx_x4_status0_sc_S_20G_CR1 8 18312 #define tx_x4_status0_sc_S_20G_KR1 9 18313 #define tx_x4_status0_sc_S_20G_X1 10 18314 #define tx_x4_status0_sc_S_20G_HG2_CR1 12 18315 #define tx_x4_status0_sc_S_20G_HG2_KR1 13 18316 #define tx_x4_status0_sc_S_20G_HG2_X1 14 18317 #define tx_x4_status0_sc_S_25G_CR1 16 18318 #define tx_x4_status0_sc_S_25G_KR1 17 18319 #define tx_x4_status0_sc_S_25G_X1 18 18320 #define tx_x4_status0_sc_S_25G_HG2_CR1 20 18321 #define tx_x4_status0_sc_S_25G_HG2_KR1 21 18322 #define tx_x4_status0_sc_S_25G_HG2_X1 22 18323 #define tx_x4_status0_sc_S_20G_CR2 24 18324 #define tx_x4_status0_sc_S_20G_KR2 25 18325 #define tx_x4_status0_sc_S_20G_X2 26 18326 #define tx_x4_status0_sc_S_20G_HG2_CR2 28 18327 #define tx_x4_status0_sc_S_20G_HG2_KR2 29 18328 #define tx_x4_status0_sc_S_20G_HG2_X2 30 18329 #define tx_x4_status0_sc_S_40G_CR2 32 18330 #define tx_x4_status0_sc_S_40G_KR2 33 18331 #define tx_x4_status0_sc_S_40G_X2 34 18332 #define tx_x4_status0_sc_S_40G_HG2_CR2 36 18333 #define tx_x4_status0_sc_S_40G_HG2_KR2 37 18334 #define tx_x4_status0_sc_S_40G_HG2_X2 38 18335 #define tx_x4_status0_sc_S_40G_CR4 40 18336 #define tx_x4_status0_sc_S_40G_KR4 41 18337 #define tx_x4_status0_sc_S_40G_X4 42 18338 #define tx_x4_status0_sc_S_40G_HG2_CR4 44 18339 #define tx_x4_status0_sc_S_40G_HG2_KR4 45 18340 #define tx_x4_status0_sc_S_40G_HG2_X4 46 18341 #define tx_x4_status0_sc_S_50G_CR2 48 18342 #define tx_x4_status0_sc_S_50G_KR2 49 18343 #define tx_x4_status0_sc_S_50G_X2 50 18344 #define tx_x4_status0_sc_S_50G_HG2_CR2 52 18345 #define tx_x4_status0_sc_S_50G_HG2_KR2 53 18346 #define tx_x4_status0_sc_S_50G_HG2_X2 54 18347 #define tx_x4_status0_sc_S_50G_CR4 56 18348 #define tx_x4_status0_sc_S_50G_KR4 57 18349 #define tx_x4_status0_sc_S_50G_X4 58 18350 #define tx_x4_status0_sc_S_50G_HG2_CR4 60 18351 #define tx_x4_status0_sc_S_50G_HG2_KR4 61 18352 #define tx_x4_status0_sc_S_50G_HG2_X4 62 18353 #define tx_x4_status0_sc_S_100G_CR4 64 18354 #define tx_x4_status0_sc_S_100G_KR4 65 18355 #define tx_x4_status0_sc_S_100G_X4 66 18356 #define tx_x4_status0_sc_S_100G_HG2_CR4 68 18357 #define tx_x4_status0_sc_S_100G_HG2_KR4 69 18358 #define tx_x4_status0_sc_S_100G_HG2_X4 70 18359 #define tx_x4_status0_sc_S_CL73_20GVCO 72 18360 #define tx_x4_status0_sc_S_CL73_25GVCO 80 18361 #define tx_x4_status0_sc_S_CL36_20GVCO 88 18362 #define tx_x4_status0_sc_S_CL36_25GVCO 96 18363 18364 /**************************************************************************** 18365 * Enums: tx_x4_status0_t_fifo_modes 18366 */ 18367 #define tx_x4_status0_t_fifo_modes_T_FIFO_MODE_BYPASS 0 18368 #define tx_x4_status0_t_fifo_modes_T_FIFO_MODE_40G 1 18369 #define tx_x4_status0_t_fifo_modes_T_FIFO_MODE_100G 2 18370 #define tx_x4_status0_t_fifo_modes_T_FIFO_MODE_20G 3 18371 18372 /**************************************************************************** 18373 * Enums: tx_x4_status0_t_enc_modes 18374 */ 18375 #define tx_x4_status0_t_enc_modes_T_ENC_MODE_BYPASS 0 18376 #define tx_x4_status0_t_enc_modes_T_ENC_MODE_CL49 1 18377 #define tx_x4_status0_t_enc_modes_T_ENC_MODE_CL82 2 18378 18379 /**************************************************************************** 18380 * Enums: tx_x4_status0_btmx_mode 18381 */ 18382 #define tx_x4_status0_btmx_mode_BS_BTMX_MODE_1to1 0 18383 #define tx_x4_status0_btmx_mode_BS_BTMX_MODE_2to1 1 18384 #define tx_x4_status0_btmx_mode_BS_BTMX_MODE_5to1 2 18385 18386 /**************************************************************************** 18387 * Enums: tx_x4_status0_t_type_cl82 18388 */ 18389 #define tx_x4_status0_t_type_cl82_T_TYPE_B1 5 18390 #define tx_x4_status0_t_type_cl82_T_TYPE_C 4 18391 #define tx_x4_status0_t_type_cl82_T_TYPE_S 3 18392 #define tx_x4_status0_t_type_cl82_T_TYPE_T 2 18393 #define tx_x4_status0_t_type_cl82_T_TYPE_D 1 18394 #define tx_x4_status0_t_type_cl82_T_TYPE_E 0 18395 18396 /**************************************************************************** 18397 * Enums: tx_x4_status0_txsm_state_cl82 18398 */ 18399 #define tx_x4_status0_txsm_state_cl82_TX_HIG_END 6 18400 #define tx_x4_status0_txsm_state_cl82_TX_HIG_START 5 18401 #define tx_x4_status0_txsm_state_cl82_TX_E 4 18402 #define tx_x4_status0_txsm_state_cl82_TX_T 3 18403 #define tx_x4_status0_txsm_state_cl82_TX_D 2 18404 #define tx_x4_status0_txsm_state_cl82_TX_C 1 18405 #define tx_x4_status0_txsm_state_cl82_TX_INIT 0 18406 18407 /**************************************************************************** 18408 * Enums: tx_x4_status0_ltxsm_state_cl82 18409 */ 18410 #define tx_x4_status0_ltxsm_state_cl82_TX_HIG_END 64 18411 #define tx_x4_status0_ltxsm_state_cl82_TX_HIG_START 32 18412 #define tx_x4_status0_ltxsm_state_cl82_TX_E 16 18413 #define tx_x4_status0_ltxsm_state_cl82_TX_T 8 18414 #define tx_x4_status0_ltxsm_state_cl82_TX_D 4 18415 #define tx_x4_status0_ltxsm_state_cl82_TX_C 2 18416 #define tx_x4_status0_ltxsm_state_cl82_TX_INIT 1 18417 18418 /**************************************************************************** 18419 * Enums: tx_x4_status0_r_type_coded_cl82 18420 */ 18421 #define tx_x4_status0_r_type_coded_cl82_R_TYPE_B1 32 18422 #define tx_x4_status0_r_type_coded_cl82_R_TYPE_C 16 18423 #define tx_x4_status0_r_type_coded_cl82_R_TYPE_S 8 18424 #define tx_x4_status0_r_type_coded_cl82_R_TYPE_T 4 18425 #define tx_x4_status0_r_type_coded_cl82_R_TYPE_D 2 18426 #define tx_x4_status0_r_type_coded_cl82_R_TYPE_E 1 18427 18428 /**************************************************************************** 18429 * Enums: tx_x4_status0_rxsm_state_cl82 18430 */ 18431 #define tx_x4_status0_rxsm_state_cl82_RX_HIG_END 64 18432 #define tx_x4_status0_rxsm_state_cl82_RX_HIG_START 32 18433 #define tx_x4_status0_rxsm_state_cl82_RX_E 16 18434 #define tx_x4_status0_rxsm_state_cl82_RX_T 8 18435 #define tx_x4_status0_rxsm_state_cl82_RX_D 4 18436 #define tx_x4_status0_rxsm_state_cl82_RX_C 2 18437 #define tx_x4_status0_rxsm_state_cl82_RX_INIT 1 18438 18439 /**************************************************************************** 18440 * Enums: tx_x4_status0_deskew_state 18441 */ 18442 #define tx_x4_status0_deskew_state_ALIGN_ACQUIRED 2 18443 #define tx_x4_status0_deskew_state_LOSS_OF_ALIGNMENT 1 18444 18445 /**************************************************************************** 18446 * Enums: tx_x4_status0_os_mode_enum 18447 */ 18448 #define tx_x4_status0_os_mode_enum_OS_MODE_1 0 18449 #define tx_x4_status0_os_mode_enum_OS_MODE_2 1 18450 #define tx_x4_status0_os_mode_enum_OS_MODE_4 2 18451 #define tx_x4_status0_os_mode_enum_OS_MODE_16p5 8 18452 #define tx_x4_status0_os_mode_enum_OS_MODE_20p625 12 18453 18454 /**************************************************************************** 18455 * Enums: tx_x4_status0_scr_modes 18456 */ 18457 #define tx_x4_status0_scr_modes_T_SCR_MODE_BYPASS 0 18458 #define tx_x4_status0_scr_modes_T_SCR_MODE_CL49 1 18459 #define tx_x4_status0_scr_modes_T_SCR_MODE_40G_2_LANE 2 18460 #define tx_x4_status0_scr_modes_T_SCR_MODE_100G 3 18461 #define tx_x4_status0_scr_modes_T_SCR_MODE_20G 4 18462 #define tx_x4_status0_scr_modes_T_SCR_MODE_40G_4_LANE 5 18463 18464 /**************************************************************************** 18465 * Enums: tx_x4_status0_descr_modes 18466 */ 18467 #define tx_x4_status0_descr_modes_R_DESCR_MODE_BYPASS 0 18468 #define tx_x4_status0_descr_modes_R_DESCR_MODE_CL49 1 18469 #define tx_x4_status0_descr_modes_R_DESCR_MODE_CL82 2 18470 18471 /**************************************************************************** 18472 * Enums: tx_x4_status0_r_dec_tl_mode 18473 */ 18474 #define tx_x4_status0_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 18475 #define tx_x4_status0_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 18476 #define tx_x4_status0_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 18477 18478 /**************************************************************************** 18479 * Enums: tx_x4_status0_r_dec_fsm_mode 18480 */ 18481 #define tx_x4_status0_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 18482 #define tx_x4_status0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 18483 #define tx_x4_status0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 18484 18485 /**************************************************************************** 18486 * Enums: tx_x4_status0_r_deskew_mode 18487 */ 18488 #define tx_x4_status0_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 18489 #define tx_x4_status0_r_deskew_mode_R_DESKEW_MODE_20G 1 18490 #define tx_x4_status0_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 18491 #define tx_x4_status0_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 18492 #define tx_x4_status0_r_deskew_mode_R_DESKEW_MODE_100G 4 18493 #define tx_x4_status0_r_deskew_mode_R_DESKEW_MODE_CL49 5 18494 #define tx_x4_status0_r_deskew_mode_R_DESKEW_MODE_CL91 6 18495 18496 /**************************************************************************** 18497 * Enums: tx_x4_status0_bs_dist_modes 18498 */ 18499 #define tx_x4_status0_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 18500 #define tx_x4_status0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 18501 #define tx_x4_status0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 18502 #define tx_x4_status0_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 18503 18504 /**************************************************************************** 18505 * Enums: tx_x4_status0_cl49_t_type 18506 */ 18507 #define tx_x4_status0_cl49_t_type_BAD_T_TYPE 15 18508 #define tx_x4_status0_cl49_t_type_T_TYPE_B0 11 18509 #define tx_x4_status0_cl49_t_type_T_TYPE_OB 10 18510 #define tx_x4_status0_cl49_t_type_T_TYPE_B1 9 18511 #define tx_x4_status0_cl49_t_type_T_TYPE_DB 8 18512 #define tx_x4_status0_cl49_t_type_T_TYPE_FC 7 18513 #define tx_x4_status0_cl49_t_type_T_TYPE_TB 6 18514 #define tx_x4_status0_cl49_t_type_T_TYPE_LI 5 18515 #define tx_x4_status0_cl49_t_type_T_TYPE_C 4 18516 #define tx_x4_status0_cl49_t_type_T_TYPE_S 3 18517 #define tx_x4_status0_cl49_t_type_T_TYPE_T 2 18518 #define tx_x4_status0_cl49_t_type_T_TYPE_D 1 18519 #define tx_x4_status0_cl49_t_type_T_TYPE_E 0 18520 18521 /**************************************************************************** 18522 * Enums: tx_x4_status0_cl49_txsm_states 18523 */ 18524 #define tx_x4_status0_cl49_txsm_states_TX_HIG_END 7 18525 #define tx_x4_status0_cl49_txsm_states_TX_HIG_START 6 18526 #define tx_x4_status0_cl49_txsm_states_TX_LI 5 18527 #define tx_x4_status0_cl49_txsm_states_TX_E 4 18528 #define tx_x4_status0_cl49_txsm_states_TX_T 3 18529 #define tx_x4_status0_cl49_txsm_states_TX_D 2 18530 #define tx_x4_status0_cl49_txsm_states_TX_C 1 18531 #define tx_x4_status0_cl49_txsm_states_TX_INIT 0 18532 18533 /**************************************************************************** 18534 * Enums: tx_x4_status0_cl49_ltxsm_states 18535 */ 18536 #define tx_x4_status0_cl49_ltxsm_states_TX_HIG_END 128 18537 #define tx_x4_status0_cl49_ltxsm_states_TX_HIG_START 64 18538 #define tx_x4_status0_cl49_ltxsm_states_TX_LI 32 18539 #define tx_x4_status0_cl49_ltxsm_states_TX_E 16 18540 #define tx_x4_status0_cl49_ltxsm_states_TX_T 8 18541 #define tx_x4_status0_cl49_ltxsm_states_TX_D 4 18542 #define tx_x4_status0_cl49_ltxsm_states_TX_C 2 18543 #define tx_x4_status0_cl49_ltxsm_states_TX_INIT 1 18544 18545 /**************************************************************************** 18546 * Enums: tx_x4_status0_burst_error_mode 18547 */ 18548 #define tx_x4_status0_burst_error_mode_BURST_ERROR_11_BITS 0 18549 #define tx_x4_status0_burst_error_mode_BURST_ERROR_16_BITS 1 18550 #define tx_x4_status0_burst_error_mode_BURST_ERROR_17_BITS 2 18551 #define tx_x4_status0_burst_error_mode_BURST_ERROR_18_BITS 3 18552 #define tx_x4_status0_burst_error_mode_BURST_ERROR_19_BITS 4 18553 #define tx_x4_status0_burst_error_mode_BURST_ERROR_20_BITS 5 18554 #define tx_x4_status0_burst_error_mode_BURST_ERROR_21_BITS 6 18555 #define tx_x4_status0_burst_error_mode_BURST_ERROR_22_BITS 7 18556 #define tx_x4_status0_burst_error_mode_BURST_ERROR_23_BITS 8 18557 #define tx_x4_status0_burst_error_mode_BURST_ERROR_24_BITS 9 18558 #define tx_x4_status0_burst_error_mode_BURST_ERROR_25_BITS 10 18559 #define tx_x4_status0_burst_error_mode_BURST_ERROR_26_BITS 11 18560 #define tx_x4_status0_burst_error_mode_BURST_ERROR_27_BITS 12 18561 #define tx_x4_status0_burst_error_mode_BURST_ERROR_28_BITS 13 18562 #define tx_x4_status0_burst_error_mode_BURST_ERROR_29_BITS 14 18563 #define tx_x4_status0_burst_error_mode_BURST_ERROR_30_BITS 15 18564 #define tx_x4_status0_burst_error_mode_BURST_ERROR_31_BITS 16 18565 #define tx_x4_status0_burst_error_mode_BURST_ERROR_32_BITS 17 18566 #define tx_x4_status0_burst_error_mode_BURST_ERROR_33_BITS 18 18567 #define tx_x4_status0_burst_error_mode_BURST_ERROR_34_BITS 19 18568 #define tx_x4_status0_burst_error_mode_BURST_ERROR_35_BITS 20 18569 #define tx_x4_status0_burst_error_mode_BURST_ERROR_36_BITS 21 18570 #define tx_x4_status0_burst_error_mode_BURST_ERROR_37_BITS 22 18571 #define tx_x4_status0_burst_error_mode_BURST_ERROR_38_BITS 23 18572 #define tx_x4_status0_burst_error_mode_BURST_ERROR_39_BITS 24 18573 #define tx_x4_status0_burst_error_mode_BURST_ERROR_40_BITS 25 18574 #define tx_x4_status0_burst_error_mode_BURST_ERROR_41_BITS 26 18575 18576 /**************************************************************************** 18577 * Enums: tx_x4_status0_bermon_state 18578 */ 18579 #define tx_x4_status0_bermon_state_HI_BER 4 18580 #define tx_x4_status0_bermon_state_GOOD_BER 3 18581 #define tx_x4_status0_bermon_state_BER_TEST_SH 2 18582 #define tx_x4_status0_bermon_state_START_TIMER 1 18583 #define tx_x4_status0_bermon_state_BER_MT_INIT 0 18584 18585 /**************************************************************************** 18586 * Enums: tx_x4_status0_rxsm_state_cl49 18587 */ 18588 #define tx_x4_status0_rxsm_state_cl49_RX_HIG_END 128 18589 #define tx_x4_status0_rxsm_state_cl49_RX_HIG_START 64 18590 #define tx_x4_status0_rxsm_state_cl49_RX_LI 32 18591 #define tx_x4_status0_rxsm_state_cl49_RX_E 16 18592 #define tx_x4_status0_rxsm_state_cl49_RX_T 8 18593 #define tx_x4_status0_rxsm_state_cl49_RX_D 4 18594 #define tx_x4_status0_rxsm_state_cl49_RX_C 2 18595 #define tx_x4_status0_rxsm_state_cl49_RX_INIT 1 18596 18597 /**************************************************************************** 18598 * Enums: tx_x4_status0_r_type 18599 */ 18600 #define tx_x4_status0_r_type_BAD_R_TYPE 15 18601 #define tx_x4_status0_r_type_R_TYPE_B0 11 18602 #define tx_x4_status0_r_type_R_TYPE_OB 10 18603 #define tx_x4_status0_r_type_R_TYPE_B1 9 18604 #define tx_x4_status0_r_type_R_TYPE_DB 8 18605 #define tx_x4_status0_r_type_R_TYPE_FC 7 18606 #define tx_x4_status0_r_type_R_TYPE_TB 6 18607 #define tx_x4_status0_r_type_R_TYPE_LI 5 18608 #define tx_x4_status0_r_type_R_TYPE_C 4 18609 #define tx_x4_status0_r_type_R_TYPE_S 3 18610 #define tx_x4_status0_r_type_R_TYPE_T 2 18611 #define tx_x4_status0_r_type_R_TYPE_D 1 18612 #define tx_x4_status0_r_type_R_TYPE_E 0 18613 18614 /**************************************************************************** 18615 * Enums: tx_x4_status0_am_lock_state 18616 */ 18617 #define tx_x4_status0_am_lock_state_INVALID_AM 512 18618 #define tx_x4_status0_am_lock_state_GOOD_AM 256 18619 #define tx_x4_status0_am_lock_state_COMP_AM 128 18620 #define tx_x4_status0_am_lock_state_TIMER_2 64 18621 #define tx_x4_status0_am_lock_state_AM_2_GOOD 32 18622 #define tx_x4_status0_am_lock_state_COMP_2ND 16 18623 #define tx_x4_status0_am_lock_state_TIMER_1 8 18624 #define tx_x4_status0_am_lock_state_FIND_1ST 4 18625 #define tx_x4_status0_am_lock_state_AM_RESET_CNT 2 18626 #define tx_x4_status0_am_lock_state_AM_LOCK_INIT 1 18627 18628 /**************************************************************************** 18629 * Enums: tx_x4_status0_msg_selector 18630 */ 18631 #define tx_x4_status0_msg_selector_RESERVED 0 18632 #define tx_x4_status0_msg_selector_VALUE_802p3 1 18633 #define tx_x4_status0_msg_selector_VALUE_802p9 2 18634 #define tx_x4_status0_msg_selector_VALUE_802p5 3 18635 #define tx_x4_status0_msg_selector_VALUE_1394 4 18636 18637 /**************************************************************************** 18638 * Enums: tx_x4_status0_synce_enum 18639 */ 18640 #define tx_x4_status0_synce_enum_SYNCE_NO_DIV 0 18641 #define tx_x4_status0_synce_enum_SYNCE_DIV_7 1 18642 #define tx_x4_status0_synce_enum_SYNCE_DIV_11 2 18643 18644 /**************************************************************************** 18645 * Enums: tx_x4_status0_synce_enum_stage0 18646 */ 18647 #define tx_x4_status0_synce_enum_stage0_SYNCE_NO_DIV 0 18648 #define tx_x4_status0_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 18649 #define tx_x4_status0_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 18650 18651 /**************************************************************************** 18652 * Enums: tx_x4_status0_cl91_sync_state 18653 */ 18654 #define tx_x4_status0_cl91_sync_state_FIND_1ST 0 18655 #define tx_x4_status0_cl91_sync_state_COUNT_NEXT 1 18656 #define tx_x4_status0_cl91_sync_state_COMP_2ND 2 18657 #define tx_x4_status0_cl91_sync_state_TWO_GOOD 3 18658 18659 /**************************************************************************** 18660 * Enums: tx_x4_status0_cl91_algn_state 18661 */ 18662 #define tx_x4_status0_cl91_algn_state_LOSS_OF_ALIGNMENT 0 18663 #define tx_x4_status0_cl91_algn_state_DESKEW 1 18664 #define tx_x4_status0_cl91_algn_state_DESKEW_FAIL 2 18665 #define tx_x4_status0_cl91_algn_state_ALIGN_ACQUIRED 3 18666 #define tx_x4_status0_cl91_algn_state_CW_GOOD 4 18667 #define tx_x4_status0_cl91_algn_state_CW_BAD 5 18668 #define tx_x4_status0_cl91_algn_state_THREE_BAD 6 18669 18670 /**************************************************************************** 18671 * Enums: tx_x4_status0_fec_sel 18672 */ 18673 #define tx_x4_status0_fec_sel_NO_FEC 0 18674 #define tx_x4_status0_fec_sel_FEC_CL74 1 18675 #define tx_x4_status0_fec_sel_FEC_CL91 2 18676 18677 /**************************************************************************** 18678 * End of RDB defined Enums 18679 */