tefmod_enum_defines.c (16550B)
1 /*---------------------------------------------------------------------- 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * $Copyright: (c) 2014 Broadcom Corporation All Rights Reserved.$ 8 * Broadcom Corporation 9 * Proprietary and Confidential information 10 * All rights reserved 11 * This source file is the property of Broadcom Corporation, and 12 * may not be copied or distributed in any isomorphic form without the 13 * prior written consent of Broadcom Corporation. 14 *--------------------------------------------------------------------- 15 ############### THIS FILE IS AUTOMATICALLY GENERATED. ############### 16 ############### DO !! NOT !! MANUALLY EDIT THIS FILE. ############### 17 *--------------------------------------------------------------------- 18 * Description: This file contains enums, elems and doxyten comments 19 * needed for SerDes Configuration programs. 20 *--------------------------------------------------------------------- 21 * CVS INFORMATION: 22 * Please see inc/enum_desc.txt for CVS information. 23 *---------------------------------------------------------------------- 24 */ 25 26 /* This file is automatically generated. Do not modify it. Modify the 27 * inc/enum_desc.txt to change enums, elems, or comments. For issues about 28 * the process that creates this file contact the tefmod development team. 29 */ 30 31 #include "tefmod_enum_defines.h" 32 33 char* e2s_tefmod_lane_select_t [CNT_tefmod_lane_select_t] = { 34 "TEFMOD_LANE_0_0_0_0" , 35 "TEFMOD_LANE_0_0_0_1" , 36 "TEFMOD_LANE_0_0_1_0" , 37 "TEFMOD_LANE_0_0_1_1" , 38 "TEFMOD_LANE_0_1_0_0" , 39 "TEFMOD_LANE_0_1_0_1" , 40 "TEFMOD_LANE_0_1_1_0" , 41 "TEFMOD_LANE_0_1_1_1" , 42 "TEFMOD_LANE_1_0_0_0" , 43 "TEFMOD_LANE_1_0_0_1" , 44 "TEFMOD_LANE_1_0_1_0" , 45 "TEFMOD_LANE_1_0_1_1" , 46 "TEFMOD_LANE_1_1_0_0" , 47 "TEFMOD_LANE_1_1_0_1" , 48 "TEFMOD_LANE_1_1_1_0" , 49 "TEFMOD_LANE_1_1_1_1" , 50 "TEFMOD_LANE_BCST" , 51 "TEFMOD_LANE_ILLEGAL" 52 }; /* e2s_tefmod_lane_select_t */ 53 54 int e2n_tefmod_lane_select_t [CNT_tefmod_lane_select_t] = { 55 0 , 56 1 , 57 2 , 58 3 , 59 4 , 60 5 , 61 6 , 62 7 , 63 8 , 64 9 , 65 10 , 66 11 , 67 12 , 68 13 , 69 14 , 70 15 , 71 15 , 72 0 73 }; /* e2n_tefmod_lane_select_t */ 74 75 char* e2s_tefmod_spd_intfc_type_t [CNT_tefmod_spd_intfc_type_t] = { 76 "TEFMOD_SPD_ZERO" , 77 "TEFMOD_SPD_10_SGMII" , 78 "TEFMOD_SPD_100_SGMII" , 79 "TEFMOD_SPD_1000_SGMII" , 80 "TEFMOD_SPD_2500" , 81 "TEFMOD_SPD_10000_XFI" , 82 "TEFMOD_SPD_10600_XFI_HG" , 83 "TEFMOD_SPD_20000_XFI" , 84 "TEFMOD_SPD_21200_XFI_HG" , 85 "TEFMOD_SPD_25000_XFI" , 86 "TEFMOD_SPD_26500_XFI_HG" , 87 "TEFMOD_SPD_20G_MLD_X2" , 88 "TEFMOD_SPD_21G_MLD_HG_X2" , 89 "TEFMOD_SPD_40G_MLD_X2" , 90 "TEFMOD_SPD_42G_MLD_HG_X2" , 91 "TEFMOD_SPD_40G_MLD_X4" , 92 "TEFMOD_SPD_42G_MLD_HG_X4" , 93 "TEFMOD_SPD_50G_MLD_X2" , 94 "TEFMOD_SPD_53G_MLD_HG_X2" , 95 "TEFMOD_SPD_100G_MLD_X4" , 96 "TEFMOD_SPD_106G_MLD_HG_X4" , 97 "TEFMOD_SPD_10000_HI" , 98 "TEFMOD_SPD_10000" , 99 "TEFMOD_SPD_12000_HI" , 100 "TEFMOD_SPD_13000" , 101 "TEFMOD_SPD_15000" , 102 "TEFMOD_SPD_16000" , 103 "TEFMOD_SPD_20000" , 104 "TEFMOD_SPD_20000_SCR" , 105 "TEFMOD_SPD_21000" , 106 "TEFMOD_SPD_25455" , 107 "TEFMOD_SPD_31500" , 108 "TEFMOD_SPD_40G_X4" , 109 "TEFMOD_SPD_42G_X4" , 110 "TEFMOD_SPD_40G_XLAUI" , 111 "TEFMOD_SPD_42G_XLAUI" , 112 "TEFMOD_SPD_10000_X2" , 113 "TEFMOD_SPD_10000_HI_DXGXS" , 114 "TEFMOD_SPD_10000_DXGXS" , 115 "TEFMOD_SPD_10000_HI_DXGXS_SCR" , 116 "TEFMOD_SPD_10000_DXGXS_SCR" , 117 "TEFMOD_SPD_10500_HI_DXGXS" , 118 "TEFMOD_SPD_12773_HI_DXGXS" , 119 "TEFMOD_SPD_12773_DXGXS" , 120 "TEFMOD_SPD_15750_HI_DXGXS" , 121 "TEFMOD_SPD_20G_MLD_DXGXS" , 122 "TEFMOD_SPD_21G_HI_MLD_DXGXS" , 123 "TEFMOD_SPD_20G_DXGXS" , 124 "TEFMOD_SPD_21G_HI_DXGXS" , 125 "TEFMOD_SPD_100G_CR10" , 126 "TEFMOD_SPD_120G_CR12" , 127 "TEFMOD_SPD_10000_XFI_HG2" , 128 "TEFMOD_SPD_50G_MLD_X4" , 129 "TEFMOD_SPD_53G_MLD_HG_X4" , 130 "TEFMOD_SPD_10000_XFI_CR1" , 131 "TEFMOD_SPD_10600_XFI_HG_CR1" , 132 "TEFMOD_SPD_CL73_20G" , 133 "TEFMOD_SPD_CL73_25G" , 134 "TEFMOD_SPD_1G_20G" , 135 "TEFMOD_SPD_1G_25G" , 136 "TEFMOD_SPD_10G_25G" , 137 "TEFMOD_SPD_ILLEGAL" 138 }; /* e2s_tefmod_spd_intfc_type_t */ 139 140 int e2n_tefmod_spd_intfc_type_t [CNT_tefmod_spd_intfc_type_t] = { 141 0 , 142 10 , 143 100 , 144 1000 , 145 2500 , 146 10000 , 147 10560 , 148 20000 , 149 21200 , 150 25000 , 151 26500 , 152 20000 , 153 21000 , 154 40000 , 155 42400 , 156 40000 , 157 42400 , 158 50000 , 159 53000 , 160 100000 , 161 106000 , 162 10000 , 163 10000 , 164 12000 , 165 13000 , 166 15000 , 167 16000 , 168 20000 , 169 20000 , 170 21000 , 171 25000 , 172 31500 , 173 40000 , 174 40000 , 175 40000 , 176 42000 , 177 10000 , 178 10000 , 179 10000 , 180 10000 , 181 10000 , 182 10500 , 183 12773 , 184 12773 , 185 15750 , 186 20000 , 187 20000 , 188 20000 , 189 21000 , 190 100000 , 191 120000 , 192 10000 , 193 50000 , 194 53000 , 195 54000 , 196 55000 , 197 56000 , 198 57000 , 199 58000 , 200 59000 , 201 10000 , 202 0 203 }; /* e2n_tefmod_spd_intfc_type_t */ 204 205 char* e2s_tefmod_regacc_type_t [CNT_tefmod_regacc_type_t] = { 206 "TEFMOD_REGACC_CL22" , 207 "TEFMOD_REGACC_CL45" , 208 "TEFMOD_REGACC_TOTSC" , 209 "TEFMOD_REGACC_SBUS_FD" , 210 "TEFMOD_REGACC_SBUS_BD" , 211 "TEFMOD_REGACC_ILLEGAL" 212 }; /* e2s_tefmod_regacc_type_t */ 213 214 char* e2s_tefmod_port_type_t [CNT_tefmod_port_type_t] = { 215 "TEFMOD_MULTI_PORT" , 216 "TEFMOD_TRI1_PORT" , 217 "TEFMOD_TRI2_PORT" , 218 "TEFMOD_DXGXS" , 219 "TEFMOD_SINGLE_PORT" , 220 "TEFMOD_PORT_MODE_ILLEGAL" 221 }; /* e2s_tefmod_port_type_t */ 222 223 char* e2s_tefmod_sc_mode_type_t [CNT_tefmod_sc_mode_type_t] = { 224 "TEFMOD_SC_MODE_HT_WITH_BASIC_OVERRIDE" , 225 "TEFMOD_SC_MODE_HT_OVERRIDE" , 226 "TEFMOD_SC_MODE_ST" , 227 "TEFMOD_SC_MODE_ST_OVERRIDE" , 228 "TEFMOD_SC_MODE_AN_CL37" , 229 "TEFMOD_SC_MODE_AN_CL73" , 230 "TEFMOD_SC_MODE_BYPASS" , 231 "TEFMOD_SC_MODE_ILLEGAL" 232 }; /* e2s_tefmod_sc_mode_type_t */ 233 234 char* e2s_tefmod_diag_type_t [CNT_tefmod_diag_type_t] = { 235 "TEFMOD_DIAG_GENERAL" , 236 "TEFMOD_DIAG_TOPOLOGY" , 237 "TEFMOD_DIAG_LINK" , 238 "TEFMOD_DIAG_SPEED" , 239 "TEFMOD_DIAG_ANEG" , 240 "TEFMOD_DIAG_TFC" , 241 "TEFMOD_DIAG_AN_TIMERS" , 242 "TEFMOD_DIAG_STATE" , 243 "TEFMOD_DIAG_DEBUG" , 244 "TEFMOD_DIAG_IEEE" , 245 "TEFMOD_DIAG_EEE" , 246 "TEFMOD_DIAG_BER" , 247 "TEFMOD_DIAG_CFG" , 248 "TEFMOD_DIAG_CL72" , 249 "TEFMOD_DIAG_DSC" , 250 "TEFMOD_SERDES_DIAG" , 251 "TEFMOD_DIAG_ALL" , 252 "TEFMOD_DIAG_ILLEGAL" 253 }; /* e2s_tefmod_diag_type_t */ 254 255 char* e2s_tefmod_model_type_t [CNT_tefmod_model_type_t] = { 256 "TEFMOD_WC" , 257 "TEFMOD_WC_A0" , 258 "TEFMOD_WC_A1" , 259 "TEFMOD_WC_A2" , 260 "TEFMOD_WC_B0" , 261 "TEFMOD_WC_B1" , 262 "TEFMOD_WC_B2" , 263 "TEFMOD_WC_C0" , 264 "TEFMOD_WC_C1" , 265 "TEFMOD_WC_C2" , 266 "TEFMOD_WC_D0" , 267 "TEFMOD_WC_D1" , 268 "TEFMOD_WC_D2" , 269 "TEFMOD_XN" , 270 "TEFMOD_WL" , 271 "TEFMOD_WL_A0" , 272 "TEFMOD_QS" , 273 "TEFMOD_QS_A0" , 274 "TEFMOD_QS_B0" , 275 "TEFMOD_MODEL_TYPE_ILLEGAL" 276 }; /* e2s_tefmod_model_type_t */ 277 278 char* e2s_tefmod_an_type_t [CNT_tefmod_an_type_t] = { 279 "TEFMOD_CL73" , 280 "TEFMOD_CL37" , 281 "TEFMOD_CL73_BAM" , 282 "TEFMOD_CL37_BAM" , 283 "TEFMOD_CL37_SGMII" , 284 "TEFMOD_HPAM" , 285 "TEFMOD_AN_TYPE_ILLEGAL" 286 }; /* e2s_tefmod_an_type_t */ 287 288 char* e2s_tefmod_eye_direction_t [CNT_tefmod_eye_direction_t] = { 289 "TEFMOD_EYE_VU" , 290 "TEFMOD_EYE_VD" , 291 "TEFMOD_EYE_HL" , 292 "TEFMOD_EYE_HR" , 293 "TEFMOD_EYE_ILLEGAL" 294 }; /* e2s_tefmod_eye_direction_t */ 295 296 char* e2s_tefmod_aspd_type_t [CNT_tefmod_aspd_type_t] = { 297 "TEFMOD_ASPD_10M" , 298 "TEFMOD_ASPD_100M" , 299 "TEFMOD_ASPD_1000M" , 300 "TEFMOD_ASPD_2p5G_X1" , 301 "TEFMOD_ASPD_5G_X4" , 302 "TEFMOD_ASPD_6G_X4" , 303 "TEFMOD_ASPD_10G_X4" , 304 "TEFMOD_ASPD_10G_CX4" , 305 "TEFMOD_ASPD_12G_X4" , 306 "TEFMOD_ASPD_12p5G_X4" , 307 "TEFMOD_ASPD_13G_X4" , 308 "TEFMOD_ASPD_15G_X4" , 309 "TEFMOD_ASPD_16G_X4" , 310 "TEFMOD_ASPD_1G_KX1" , 311 "TEFMOD_ASPD_10G_KX4" , 312 "TEFMOD_ASPD_10G_KR1" , 313 "TEFMOD_ASPD_5G_X1" , 314 "TEFMOD_ASPD_6p36G_X1" , 315 "TEFMOD_ASPD_20G_CX4" , 316 "TEFMOD_ASPD_21G_X4" , 317 "TEFMOD_ASPD_25p45G_X4" , 318 "TEFMOD_ASPD_10G_X2_NOSCRAMBLE" , 319 "TEFMOD_ASPD_10G_CX2_NOSCRAMBLE" , 320 "TEFMOD_ASPD_10p5G_X2" , 321 "TEFMOD_ASPD_10p5G_CX2_NOSCRAMBLE" , 322 "TEFMOD_ASPD_12p7G_X2" , 323 "TEFMOD_ASPD_12p7G_CX2" , 324 "TEFMOD_ASPD_10G_X1" , 325 "TEFMOD_ASPD_40G_X4" , 326 "TEFMOD_ASPD_20G_X2" , 327 "TEFMOD_ASPD_20G_CX2" , 328 "TEFMOD_ASPD_10G_SFI" , 329 "TEFMOD_ASPD_31p5G_X4" , 330 "TEFMOD_ASPD_32p7G_X4" , 331 "TEFMOD_ASPD_20G_X4" , 332 "TEFMOD_ASPD_10G_X2" , 333 "TEFMOD_ASPD_10G_CX2" , 334 "TEFMOD_ASPD_12G_SCO_R2" , 335 "TEFMOD_ASPD_10G_SCO_X2" , 336 "TEFMOD_ASPD_40G_KR4" , 337 "TEFMOD_ASPD_40G_CR4" , 338 "TEFMOD_ASPD_100G_CR10" , 339 "TEFMOD_ASPD_5G_X2" , 340 "TEFMOD_ASPD_15p75G_X2" , 341 "TEFMOD_ASPD_2G_FC" , 342 "TEFMOD_ASPD_4G_FC" , 343 "TEFMOD_ASPD_8G_FC" , 344 "TEFMOD_ASPD_10G_CX1" , 345 "TEFMOD_ASPD_1G_CX1" , 346 "TEFMOD_ASPD_20G_KR2" , 347 "TEFMOD_ASPD_20G_CR2" , 348 "TEFMOD_ASPD_TYPE_ILLEGAL" 349 }; /* e2s_tefmod_aspd_type_t */ 350 351 int e2n_tefmod_aspd_type_t [CNT_tefmod_aspd_type_t] = { 352 0x0 , 353 0x1 , 354 0x2 , 355 0x3 , 356 0x4 , 357 0x5 , 358 0x6 , 359 0x7 , 360 0x8 , 361 0x9 , 362 0xa , 363 0xb , 364 0xc , 365 0xd , 366 0xe , 367 0xf , 368 0x10 , 369 0x11 , 370 0x12 , 371 0x13 , 372 0x14 , 373 0x15 , 374 0x16 , 375 0x17 , 376 0x18 , 377 0x19 , 378 0x1a , 379 0x1b , 380 0x1c , 381 0x1d , 382 0x1e , 383 0x1f , 384 0x20 , 385 0x21 , 386 0x22 , 387 0x23 , 388 0x24 , 389 0x25 , 390 0x26 , 391 0x27 , 392 0x28 , 393 0x29 , 394 0x2a , 395 0x2c , 396 0x2e , 397 0x2f , 398 0x30 , 399 0x33 , 400 0x34 , 401 0x39 , 402 0x3a , 403 0xff 404 }; /* e2n_tefmod_aspd_type_t */ 405 406 char* e2s_tefmod_tech_ability_t [CNT_tefmod_tech_ability_t] = { 407 "TEFMOD_ABILITY_1G" , 408 "TEFMOD_ABILITY_10G_KR" , 409 "TEFMOD_ABILITY_40G_KR4" , 410 "TEFMOD_ABILITY_40G_CR4" , 411 "TEFMOD_ABILITY_100G_CR10" , 412 "TEFMOD_ABILITY_10G_HIGIG" , 413 "TEFMOD_ABILITY_10G_CX4" , 414 "TEFMOD_ABILITY_20G_X4" , 415 "TEFMOD_ABILITY_40G" , 416 "TEFMOD_ABILITY_25P455G" , 417 "TEFMOD_ABILITY_21G_X4" , 418 "TEFMOD_ABILITY_20G_X4S" , 419 "TEFMOD_ABILITY_10G_DXGXS_HIGIG" , 420 "TEFMOD_ABILITY_10G_DXGXS" , 421 "TEFMOD_ABILITY_10P5G_DXGXS" , 422 "TEFMOD_ABILITY_12P5_DXGXS" , 423 "TEFMOD_ABILITY_20G_KR2_HIGIG" , 424 "TEFMOD_ABILITY_20G_KR2" , 425 "TEFMOD_ABILITY_20G_CR2" , 426 "TEFMOD_ABILITY_15P75G_R2" , 427 "TEFMOD_ABILITY_100G_KR4" , 428 "TEFMOD_ABILITY_100G_CR4" , 429 "TEFMOD_ABILITY_40G_KR2" , 430 "TEFMOD_ABILITY_40G_CR2" , 431 "TEFMOD_ABILITY_50G_KR2" , 432 "TEFMOD_ABILITY_50G_CR2" , 433 "TEFMOD_ABILITY_50G_KR4" , 434 "TEFMOD_ABILITY_50G_CR4" , 435 "TEFMOD_ABILITY_20G_KR1" , 436 "TEFMOD_ABILITY_20G_CR1" , 437 "TEFMOD_ABILITY_25G_KR1" , 438 "TEFMOD_ABILITY_25G_CR1" , 439 "TEFMOD_ABILITY_ILLEGAL" 440 }; /* e2s_tefmod_tech_ability_t */ 441 442 int e2n_tefmod_tech_ability_t [CNT_tefmod_tech_ability_t] = { 443 0x6 , 444 0x7 , 445 0x8 , 446 0x9 , 447 0xa , 448 0x103 , 449 0x104 , 450 0x10a , 451 0x305 , 452 0x308 , 453 0x309 , 454 0x400 , 455 0x401 , 456 0x402 , 457 0x403 , 458 0x404 , 459 0x405 , 460 0x406 , 461 0x406 , 462 0x407 , 463 0x408 , 464 0x409 , 465 0x40a , 466 0x500 , 467 0x501 , 468 0x502 , 469 0x503 , 470 0x504 , 471 0x505 , 472 0x506 , 473 0x507 , 474 0x508 , 475 0x999 476 }; /* e2n_tefmod_tech_ability_t */ 477 478 char* e2s_tefmod_cl37bam_ability_t [CNT_tefmod_cl37bam_ability_t] = { 479 "TEFMOD_BAM37ABL_2P5G" , 480 "TEFMOD_BAM37ABL_5G_X4" , 481 "TEFMOD_BAM37ABL_6G_X4" , 482 "TEFMOD_BAM37ABL_10G_HIGIG" , 483 "TEFMOD_BAM37ABL_10G_CX4" , 484 "TEFMOD_BAM37ABL_12G_X4" , 485 "TEFMOD_BAM37ABL_12P5_X4" , 486 "TEFMOD_BAM37ABL_13G_X4" , 487 "TEFMOD_BAM37ABL_15G_X4" , 488 "TEFMOD_BAM37ABL_16G_X4" , 489 "TEFMOD_BAM37ABL_20G_X4_CX4" , 490 "TEFMOD_BAM37ABL_20G_X4" , 491 "TEFMOD_BAM37ABL_21G_X4" , 492 "TEFMOD_BAM37ABL_25P455G" , 493 "TEFMOD_BAM37ABL_31P5G" , 494 "TEFMOD_BAM37ABL_32P7G" , 495 "TEFMOD_BAM37ABL_40G" , 496 "TEFMOD_BAM37ABL_10G_X2_CX4" , 497 "TEFMOD_BAM37ABL_10G_DXGXS" , 498 "TEFMOD_BAM37ABL_10P5G_DXGXS" , 499 "TEFMOD_BAM37ABL_12P7_DXGXS" , 500 "TEFMOD_BAM37ABL_15P75G_R2" , 501 "TEFMOD_BAM37ABL_20G_X2_CX4" , 502 "TEFMOD_BAM37ABL_20G_X2" , 503 "TEFMOD_BAM37ABL_ILLEGAL" 504 }; /* e2s_tefmod_cl37bam_ability_t */ 505 506 char* e2s_tefmod_diag_an_type_t [CNT_tefmod_diag_an_type_t] = { 507 "TEFMOD_DIAG_AN_DONE" , 508 "TEFMOD_DIAG_AN_HCD" , 509 "TEFMOD_DIAG_AN_TYPE_ILLEGAL" 510 }; /* e2s_tefmod_diag_an_type_t */ 511 512 char* e2s_tefmod_tier1_function_type_t [CNT_tefmod_tier1_function_type_t] = { 513 "PCS_BYPASS_CTL" , 514 "CREDIT_SET" , 515 "ENCODE_SET" , 516 "DECODE_SET" , 517 "CREDIT_CONTROL" , 518 "AFE_SPEED_UP_DSC_VGA" , 519 "TX_LANE_CONTROL" , 520 "RX_LANE_CONTROL" , 521 "TX_LANE_DISABLE" , 522 "POWER_CONTROL" , 523 "AUTONEG_SET" , 524 "AUTONEG_GET" , 525 "AUTONEG_CONTROL" , 526 "AUTONEG_PAGE_SET" , 527 "REG_READ" , 528 "REG_WRITE" , 529 "PRBS_CHECK" , 530 "CJPAT_CRPAT_CONTROL" , 531 "CJPAT_CRPAT_CHECK" , 532 "TEFMOD_DIAG" , 533 "LANE_SWAP" , 534 "PARALLEL_DETECT_CONTROL" , 535 "CLAUSE_72_CONTROL" , 536 "PLL_SEQUENCER_CONTROL" , 537 "PLL_LOCK_WAIT" , 538 "DUPLEX_CONTROL" , 539 "REVID_READ" , 540 "BYPASS_SC" , 541 "SET_POLARITY" , 542 "SET_PORT_MODE" , 543 "SET_AN_PORT_MODE" , 544 "PRBS_CONTROL" , 545 "PRBS_MODE" , 546 "SOFT_RESET" , 547 "SET_SPD_INTF" , 548 "TX_BERT_CONTROL" , 549 "RX_LOOPBACK_CONTROL" , 550 "RX_PMD_LOOPBACK_CONTROL" , 551 "TX_LOOPBACK_CONTROL" , 552 "TX_PMD_LOOPBACK_CONTROL" , 553 "CORE_RESET" , 554 "REFCLK_SET" , 555 "WAIT_PMD_LOCK" , 556 "FIRMWARE_SET" , 557 "INIT_PCS_FALCON" , 558 "DISABLE_PCS_FALCON" , 559 "INIT_PMD_FALCON" , 560 "PMD_LANE_SWAP_TX" , 561 "PMD_LANE_SWAP" , 562 "PCS_LANE_SWAP" , 563 "SET_SC_SPEED" , 564 "CHECK_SC_STATS" , 565 "SET_OVERRIDE_0" , 566 "SET_OVERRIDE_1" , 567 "PMD_RESET_REMOVE" , 568 "PMD_RESET_BYPASS" , 569 "INIT_PCS_ILKN" , 570 "TOGGLE_SW_SPEED_CHANGE" , 571 "TIER1_FUNCTION_ILLEGAL" 572 }; /* e2s_tefmod_tier1_function_type_t */ 573 574 char* e2s_tefmod_fec_en_parm_t [CNT_tefmod_fec_en_parm_t] = { 575 "TEFMOD_CL91_TX_EN_DIS" , 576 "TEFMOD_CL91_RX_EN_DIS" , 577 "TEFMOD_CL91_IND_ONLY_EN_DIS" , 578 "TEFMOD_CL91_COR_ONLY_EN_DIS" , 579 "TEFMOD_CL74_TX_EN_DIS" , 580 "TEFMOD_CL74_RX_EN_DIS" , 581 "TEFMOD_CL74_CL91_EN_DIS" 582 }; /* e2s_tefmod_fec_en_parm_t */ 583 584 char* e2s_tefmod_fec_type_t [CNT_tefmod_fec_type_t] = { 585 "TEFMOD_CL74" , 586 "TEFMOD_CL91" , 587 "TEFMOD_CL108" 588 }; /* e2s_tefmod_fec_type_t */ 589 590 591 char* e2s_tefmod_tx_disable_enum_t [CNT_tefmod_tx_disable_enum_t] = { 592 "TEFMOD_TX_LANE_TRAFFIC" , 593 "TEFMOD_TX_LANE_RESET" 594 }; /* e2s_tefmod_tx_disable_enum_t */ 595 596 char* e2s_tefmod_os_mode_type [CNT_tefmod_os_mode_type] = { 597 "TEFMOD_PMA_OS_MODE_1" , 598 "TEFMOD_PMA_OS_MODE_2" , 599 "TEFMOD_PMA_OS_MODE_4" , 600 "TEFMOD_PMA_OS_MODE_16_25" , 601 "TEFMOD_PMA_OS_MODE_20_625" , 602 "TEFMOD_PMA_OS_MODE_ILLEGAL" 603 }; /* e2s_tefmod_os_mode_type */ 604 605 int e2n_tefmod_os_mode_type [CNT_tefmod_os_mode_type] = { 606 1 , 607 2 , 608 4 , 609 16 , 610 10 , 611 0 612 }; /* e2n_tefmod_os_mode_type */ 613 614 char* e2s_tefmod_scr_mode [CNT_tefmod_scr_mode] = { 615 "TEFMOD_SCR_MODE_BYPASS" , 616 "TEFMOD_SCR_MODE_CL49" , 617 "TEFMOD_SCR_MODE_40G_2_LANE" , 618 "TEFMOD_SCR_MODE_100G" , 619 "TEFMOD_SCR_MODE_20G" , 620 "TEFMOD_SCR_MODE_40G_4_LANE" , 621 "TEFMOD_SCR_MODE_ILLEGAL" 622 }; /* e2s_tefmod_scr_mode */ 623 624 int e2n_tefmod_scr_mode [CNT_tefmod_scr_mode] = { 625 0 , 626 1 , 627 2 , 628 3 , 629 4 , 630 5 , 631 0 632 }; /* e2n_tefmod_scr_mode */ 633 634 char* e2s_tefmod_encode_mode [CNT_tefmod_encode_mode] = { 635 "TEFMOD_ENCODE_MODE_NONE" , 636 "TEFMOD_ENCODE_MODE_CL49" , 637 "TEFMOD_ENCODE_MODE_CL82" , 638 "TEFMOD_ENCODE_MODE_ILLEGAL" 639 }; /* e2s_tefmod_encode_mode */ 640 641 int e2n_tefmod_encode_mode [CNT_tefmod_encode_mode] = { 642 0 , 643 1 , 644 2 , 645 15 646 }; /* e2n_tefmod_encode_mode */ 647 648 char* e2s_tefmod_descrambler_mode [CNT_tefmod_descrambler_mode] = { 649 "TEFMOD_R_DESCR_MODE_BYPASS" , 650 "TEFMOD_R_DESCR_MODE_CL49" , 651 "TEFMOD_R_DESCR_MODE_CL82" , 652 "TEFMOD_R_DESCR_MODE_ILLEGAL" 653 }; /* e2s_tefmod_descrambler_mode */ 654 655 char* e2s_tefmod_dec_tl_mode [CNT_tefmod_dec_tl_mode] = { 656 "TEFMOD_DEC_TL_MODE_NONE" , 657 "TEFMOD_DEC_TL_MODE_CL49" , 658 "TEFMOD_DEC_TL_MODE_CL82" , 659 "TEFMOD_DEC_TL_MODE_ILLEGAL" 660 }; /* e2s_tefmod_dec_tl_mode */ 661 662 char* e2s_tefmod_dec_fsm_mode [CNT_tefmod_dec_fsm_mode] = { 663 "TEFMOD_DEC_FSM_MODE_NONE" , 664 "TEFMOD_DEC_FSM_MODE_CL49" , 665 "TEFMOD_DEC_FSM_MODE_CL82" , 666 "TEFMOD_DEC_FSM_MODE_ILLEGAL" 667 }; /* e2s_tefmod_dec_fsm_mode */ 668 669 char* e2s_tefmod_deskew_mode [CNT_tefmod_deskew_mode] = { 670 "TEFMOD_R_DESKEW_MODE_BYPASSi" , 671 "TEFMOD_R_DESKEW_MODE_10G" , 672 "TEFMOD_R_DESKEW_MODE_40G_4_LANE" , 673 "TEFMOD_R_DESKEW_MODE_40G_2_LANE" , 674 "TEFMOD_R_DESKEW_MODE_100G" , 675 "TEFMOD_R_DESKEW_MODE_CL49" , 676 "TEFMOD_R_DESKEW_MODE_CL91" , 677 "TEFMOD_R_DESKEW_MODE_ILLEGAL" 678 }; /* e2s_tefmod_deskew_mode */ 679 680 char* e2s_tefmod_t_fifo_mode [CNT_tefmod_t_fifo_mode] = { 681 "TEFMOD_T_FIFO_MODE_NONE" , 682 "TEFMOD_T_FIFO_MODE_40G" , 683 "TEFMOD_T_FIFO_MODE_100G" , 684 "TEFMOD_T_FIFO_MODE_20G" , 685 "TEFMOD_T_FIFO_MODE_ILLEGAL" 686 }; /* e2s_tefmod_t_fifo_mode */ 687 688 char* e2s_tefmod_bs_btmx_mode [CNT_tefmod_bs_btmx_mode] = { 689 "TEFMOD_BS_BTMX_MODE_NONE" , 690 "TEFMOD_BS_BTMX_MODE_1to1" , 691 "TEFMOD_BS_BTMX_MODE_2to1" , 692 "TEFMOD_BS_BTMX_MODE_5to1" , 693 "TEFMOD_BS_BTMX_MODE_ILLEGAL" 694 }; /* e2s_tefmod_bs_btmx_mode */ 695 696 char* e2s_tefmod_bs_dist_mode [CNT_tefmod_bs_dist_mode] = { 697 "TEFMOD_BS_DIST_MODE_5_LANE_TDM" , 698 "TEFMOD_BS_DIST_MODE_2_LANE_TDM_2_VLANE" , 699 "TEFMOD_BS_DIST_MODE_2_LANE_TDM_1_VLANE" , 700 "TEFMOD_BS_DIST_MODE_NO_TDM" , 701 "TEFMOD_BS_DIST_MODE_ILLEGAL" 702 }; /* e2s_tefmod_bs_dist_mode */ 703