tefmod_doc.h (16094B)
1 /*---------------------------------------------------------------------- 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * Broadcom Corporation 8 * Proprietary and Confidential information 9 * $Copyright: (c) 2012 Broadcom Corp. 10 * All Rights Reserved.$ 11 * This source file is the property of Broadcom Corporation, and 12 * may not be copied or distributed in any isomorphic form without the 13 * prior written consent of Broadcom Corporation. 14 *---------------------------------------------------------------------- 15 * Description: Main doc header file for TEFMod. 16 *---------------------------------------------------------------------*/ 17 18 19 The PMD data dump has similarly controls. The DSC states are shown with the 20 command below. 21 22 \code 23 BCM.0> phy diag xe0 dsc 24 25 26 27 *********************************** 28 **** SERDES CORE DISPLAY STATE **** 29 *********************************** 30 31 Average Die TMON_reg13bit = 5720 32 Temperature Force Val = 0 33 Temperature Index = 12 [56C to 64C] 34 Core Event Log Level = 1 35 36 Core DP Reset State = 0 37 38 Common Ucode Version = 0xd107 39 Common Ucode Minor Version = 0x0 40 AFE Hardware Version = 0xb0 41 42 LN (CDRxN ,UC_CFG) SD LCK RXPPM PF(M,L) VGA DCO DFE(1,2,3,4,5,6) TXPPM TXEQ(n1,m,p1,p2,p3) EYE(L,R,U,D) LINK_TIME 43 0 (OSx1 ,0x 4) 1 1 0 0,2 16 4 48, -7, 5, 2, 0, 0 0 0,100,12, 0, 0 171,359, 82, 82 94.5 44 45 46 ------------------------------------------------------------------------ 47 Falcon PMD State 48 PARAMETER LN0 LN1 LN2 LN3 49 ------------------------------------------------------------------------ 50 TX drv_hv_disable 0 0 0 0 51 TX ana_rescal 8 8 8 8 52 TX amp_ctrl 8 8 8 8 53 TX pre_tap 0 0 0 0 54 TX main_tap 100 100 100 100 55 TX post1_tap 12 12 12 12 56 TX post2_tap 0 0 0 0 57 TX post3_tap 0 0 0 0 58 ------------------------------------------------------------------------ 59 Sigdet 1 1 1 1 60 PMD_lock 1 1 1 1 61 DSC_SM (1st read) 3feh 3feh 3feh 3feh 62 DSC_SM (2nd read) 80h 80h 80h 80h 63 ------------------------------------------------------------------------ 64 PPM 0 0 0 0 65 VGA 16 17 18 17 66 PF 0 0 0 0 67 PF2 2 1 1 2 68 main_tap -28 -28 -28 -28 69 data_thresh 48 47 48 51 70 phase_thresh 63 63 63 63 71 lms_thresh 0 0 0 0 72 ------------------------------------------------------------------------ 73 d/dq hoffset 64 64 64 64 74 p/pq hoffset 65 65 66 66 75 l/lq hoffset 66 64 66 67 76 d/p hoffset 31 31 32 30 77 d/l hoffset 0 0 0 255 78 ------------------------------------------------------------------------ 79 dfe[2][a,b] -7, -8 -3, -4 -4, -5 -5, -6 80 dfe[2][c,d] -7, -6 -3, -3 -5, -5 -6, -6 81 dfe[3][a,b] 6, 6 7, 7 6, 6 5, 5 82 dfe[3][c,d] 5, 6 7, 7 6, 6 5, 6 83 dfe[4][a,b] 2, 2 1, 1 5, 5 2, 2 84 dfe[4][c,d] 2, 3 0, 1 6, 5 2, 2 85 dfe[5][a,b] 1, 1 4, 4 1, 1 -1, -1 86 dfe[5][c,d] 0, 0 4, 3 1, 1 -1, 0 87 dfe[6][a,b] 0, 1 1, 1 1, 1 1, 1 88 dfe[6][c,d] 1, 1 1, 1 1, 1 1, 1 89 ------------------------------------------------------------------------ 90 dfe[7][a,b] 0, 0 0, 0 0, 0 0, 0 91 dfe[7][c,d] 0, 0 0, 0 0, 0 0, 0 92 dfe[8][a,b] 0, 0 0, 0 0, 0 0, 0 93 dfe[8][c,d] 0, 0 0, 0 0, 0 0, 0 94 dfe[9][a,b] 0, 0 0, 0 0, 0 0, 0 95 dfe[9][c,d] 0, 0 0, 0 0, 0 0, 0 96 dfe[10][a,b] 0, 0 0, 0 0, 0 0, 0 97 dfe[10][c,d] 0, 0 0, 0 0, 0 0, 0 98 dfe[11][a,b] 0, 0 0, 0 0, 0 0, 0 99 dfe[11][c,d] 0, 0 0, 0 0, 0 0, 0 100 dfe[12][a,b] 0, 0 0, 0 0, 0 0, 0 101 dfe[12][c,d] 0, 0 0, 0 0, 0 0, 0 102 dfe[13][a,b] 0, 0 0, 0 0, 0 0, 0 103 dfe[13][c,d] 0, 0 0, 0 0, 0 0, 0 104 dfe[14][a,b] 0, 0 0, 0 0, 0 0, 0 105 dfe[14][c,d] 0, 0 0, 0 0, 0 0, 0 106 dfe[15][a,b] 0, 0 0, 0 0, 0 0, 0 107 dfe[15][c,d] 0, 0 0, 0 0, 0 0, 0 108 dfe[16][a,b] 0, 0 0, 0 0, 0 0, 0 109 dfe[16][c,d] 0, 0 0, 0 0, 0 0, 0 110 dfe[17][a,b] 0, 0 0, 0 0, 0 0, 0 111 dfe[17][c,d] 0, 0 0, 0 0, 0 0, 0 112 dfe[18][a,b] 0, 0 0, 0 0, 0 0, 0 113 dfe[18][c,d] 0, 0 0, 0 0, 0 0, 0 114 dfe[19][a,b] 0, 0 0, 0 0, 0 0, 0 115 dfe[19][c,d] 0, 0 0, 0 0, 0 0, 0 116 dfe[20][a,b] 0, 0 0, 0 0, 0 0, 0 117 dfe[20][c,d] 0, 0 0, 0 0, 0 0, 0 118 dfe[21][a,b] 0, 0 0, 0 0, 0 0, 0 119 dfe[21][c,d] 0, 0 0, 0 0, 0 0, 0 120 dfe[22][a,b] 0, 0 0, 0 0, 0 0, 0 121 dfe[22][c,d] 0, 0 0, 0 0, 0 0, 0 122 dfe[23][a,b] 0, 0 0, 0 0, 0 0, 0 123 dfe[23][c,d] 0, 0 0, 0 0, 0 0, 0 124 dfe[24][a,b] 0, 0 0, 0 0, 0 0, 0 125 dfe[24][c,d] 0, 0 0, 0 0, 0 0, 0 126 dfe[25][a,b] 0, 0 0, 0 0, 0 0, 0 127 dfe[25][c,d] 0, 0 0, 0 0, 0 0, 0 128 dfe[26][a,b] 0, 0 0, 0 0, 0 0, 0 129 dfe[26][c,d] 0, 0 0, 0 0, 0 0, 0 130 ------------------------------------------------------------------------ 131 dc_offset 4 -7 13 12 132 data_p[a,b] -9, 4 -1, -1 -3, 3 -9, -3 133 data_p[c,d] 2, -3 -4, -5 2, 0 1, 0 134 data_n[a,b] -3, 0 -1, 0 -2, -9 4, -6 135 data_n[c,d] -7, 2 1, 0 -2, -2 -4, -2 136 phase_p[a,b] -5, 4 0, -5 -9, -6 -5, -9 137 phase_p[c,d] -4, -1 4, 0 -4, -1 5, 9 138 phase_n[a,b] -5, 6 -11, -1 0, 0 0, -2 139 phase_n[c,d] 2, 4 -1, -7 -3, 2 -1, -2 140 lms[a,b] -11, 3 5,-14 -3, -1 -1, 1 141 lms[c,d] -1, -3 -9, -4 -7, -4 1,-10 142 ------------------------------------------------------------------------ 143 PRBS_CHECKER 0 0 0 0 144 PRBS_ORDER 31 31 31 31 145 PRBS_LOCK 0 0 0 0 146 PRBS_ERRCNT 2147483648 2147483648 2147483648 2147483648 147 ------------------------------------------------------------------------ 148 149 150 151 ******************************************** 152 **** SERDES UC TRACE MEMORY DUMP *********** 153 ******************************************** 154 155 DEBUG INFO: trace memory read index = 0x0026 156 DEBUG INFO: trace memory size = 0x0300 157 158 0x8017 0xd911 0xff00 0x0283 0xff94 0x0e81 0xfdc3 0x0e80 0 159 0xfd24 0x0e82 0xfcad 0x0e80 0xd81a 0x0783 0xd818 0x0782 16 160 0xd816 0x0781 0xd815 0x0700 0x0000 0x0000 0x0000 0x0000 32 161 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 48 162 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 64 163 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 80 164 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 96 165 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 112 166 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 128 167 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 144 168 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 160 169 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 176 170 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 192 171 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 208 172 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 224 173 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 240 174 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 256 175 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 272 176 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 288 177 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 304 178 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 320 179 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 336 180 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 352 181 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 368 182 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 384 183 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 400 184 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 416 185 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 432 186 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 448 187 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 464 188 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 480 189 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 496 190 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 512 191 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 528 192 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 544 193 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 560 194 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 576 195 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 592 196 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 608 197 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 624 198 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 640 199 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 656 200 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 672 201 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 688 202 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 704 203 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 720 204 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 736 205 0x0000 0x0000 0x0000 0x0000 0x041c 0x0df8 0x0000 0x0000 752 206 Lane 0: t= 0 ms, Start reading event log 207 208 2 timestamp wraparound(s). 209 210 Lane 3: t= -717 ms (+5), Rx PMD lock 211 Lane 1: t= -722 ms (+1), Rx PMD lock 212 Lane 0: t= -723 ms (+1), Rx PMD lock 213 Lane 2: t= -724 ms (+94), Rx PMD lock 214 Lane 0: t= -818 ms (+0), Exit from restart 215 Lane 3: t= -818 ms (+0), Exit from restart 216 Lane 2: t= -818 ms (+0), Exit from restart 217 Lane 1: t= -818 ms 218 ========== End of Event Log ================== 219 \endcode 220 221 The command below is yet to be implemented. 222 223 \code 224 BCM.0> phy diag xe0 dsc ber 225 \endcode 226 The command below shows a variety of PMD core AND lane configurations. 227 \code 228 229 BCM.0> phy diag xe0 dsc config 230 231 232 *********************************** 233 **** SERDES CORE CONFIGURATION **** 234 *********************************** 235 236 uC Config VCO Rate = 19 (10.250GHz) 237 Core Config from PCS = 0 238 239 Lane Addr 0 = 0 240 Lane Addr 1 = 1 241 Lane Addr 2 = 2 242 Lane Addr 3 = 3 243 TX Lane Map 0 = 0 244 TX Lane Map 1 = 1 245 TX Lane Map 2 = 2 246 TX Lane Map 3 = 3 247 248 249 250 ************************************* 251 **** SERDES LANE 0 CONFIGURATION **** 252 ************************************* 253 254 Auto-Neg Enabled = 0 255 DFE on = 1 256 Brdfe_on = 0 257 Media Type = 0 258 Unreliable LOS = 0 259 Scrambling Disable = 0 260 CL72 Emulation Enable = 0 261 Lane Config from PCS = 0 262 263 CL72 Training Enable = 0 264 EEE Mode Enable = 0 265 OSR Mode Force = 1 266 OSR Mode Force Val = 0 267 TX Polarity Invert = 0 268 RX Polarity Invert = 0 269 270 TXFIR Post2 = 0 271 TXFIR Post3 = 0 272 TXFIR Override Enable = 0 273 TXFIR Main Override = 102 274 TXFIR Pre Override = 12 275 TXFIR Post Override = 0 276 277 \endcode 278 Get CL72 specific information with this command 279 \code 280 BCM.0> phy diag ce0 dsc CL72 281 tscf_phy_pmd_info_dump:449 type = 8192 laneMask = 0xF 282 tscf_phy_pmd_info_dump:469 type = CL72 283 284 285 *************************** 286 ** LANE 0 CL93n72 Status ** 287 *************************** 288 cl93n72_signal_detect = 1 (1 = CL93n72 training FSM in SEND_DATA state: 0 = CL93n72 in training state) 289 cl93n72_ieee_training_failure = 0 (1 = Training failure detected: 0 = Training failure not detected) 290 cl93n72_ieee_training_status = 0 (1 = Start-up protocol in progress: 0 = Start-up protocol complete) 291 cl93n72_ieee_receiver_status = 1 (1 = Receiver trained and ready to receive: 0 = Receiver training) 292 293 tscf_phy_pmd_info_dump:469 type = CL72 294 \endcode 295 Get DSC specific information with this command 296 \code 297 BCM.0> phy diag xe0 dsc debug 298 299 300 ************************************ 301 **** SERDES LANE 0 DEBUG STATUS **** 302 ************************************ 303 304 Restart Count = 5 305 Reset Count = 6 306 PMD Lock Count = 3 307 308 Disable Startup PF Adaptation = 0 309 Disable Startup DC Adaptation = 0 310 Disable Startup Slicer Offset Tuning = 0 311 Disable Startup Clk90 offset Adaptation = 1 312 Disable Startup P1 level Tuning = 0 313 Disable Startup Eye Adaptaion = 0 314 Disable Startup All Adaptaion = 0 315 316 Disable Startup DFE Tap1 Adaptation = 0 317 Disable Startup DFE Tap2 Adaptation = 0 318 Disable Startup DFE Tap3 Adaptation = 0 319 Disable Startup DFE Tap4 Adaptation = 0 320 Disable Startup DFE Tap5 Adaptation = 0 321 Disable Startup DFE Tap1 DCD = 0 322 Disable Startup DFE Tap2 DCD = 0 323 324 Disable Steady State PF Adaptation = 0 325 Disable Steady State DC Adaptation = 0 326 Disable Steady State Slicer Offset Tuning = 0 327 Disable Steady State Clk90 offset Adaptation = 1 328 Disable Steady State P1 level Tuning = 0 329 Disable Steady State Eye Adaptaion = 0 330 Disable Steady State All Adaptaion = 0 331 332 Disable Steady State DFE Tap1 Adaptation = 0 333 Disable Steady State DFE Tap2 Adaptation = 0 334 Disable Steady State DFE Tap3 Adaptation = 0 335 Disable Steady State DFE Tap4 Adaptation = 0 336 Disable Steady State DFE Tap5 Adaptation = 0 337 Disable Steady State DFE Tap1 DCD = 0 338 Disable Steady State DFE Tap2 DCD = 0 339 340 Retune after Reset = 1 341 Clk90 offset Adjust = 57 342 Clk90 offset Override = 0 343 Lane Event Log Level = 2 344 345 \endcode