tefmod_diagnostics.c (36586B)
1 /*---------------------------------------------------------------------- 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * $Copyright: (c) 2014 Broadcom Corporation All Rights Reserved.$ 8 * Broadcom Corporation 9 * Proprietary and Confidential information 10 * Copyright: (c) 2012 Broadcom Corp. 11 * All rights reserved 12 * This source file is the property of Broadcom Corporation, and 13 * may not be copied or distributed in any isomorphic form without the 14 * prior written consent of Broadcom Corporation. 15 *--------------------------------------------------------------------- 16 * File : tefmod_diagnostics.c 17 * Description: C sequences which utilize tier1s to build configurations 18 * which target only the diagnostic features of the Serdes 19 *-----------------------------------------------------------------------*/ 20 #ifndef _SDK_TEFMOD_ 21 #ifndef _DV_TB_ 22 #define _SDK_TEFMOD_ 1 23 #endif 24 #endif 25 26 #ifdef _DV_TB_ 27 #include "tefmod_main.h" 28 #include "tefmod_defines.h" 29 #include "tefmod_phyreg.h" 30 #include <math.h> 31 #endif 32 33 #ifdef _DV_TB_ 34 #include "bcmi_tscf_xgxs_defs.h" 35 #endif 36 37 #ifdef _SDK_TEFMOD_ 38 #include <phymod/phymod_system.h> 39 #include <phymod/chip/bcmi_tscf_xgxs_defs.h> 40 #include "tefmod_enum_defines.h" 41 #endif 42 43 #define _TRGO_(a,l) PHYMOD_DEBUG_ERROR(("<< PHY_TRG: Adr:%06d Ln:%02d\n",a,l)); 44 #define _TRGC_(a,l) PHYMOD_DEBUG_ERROR((">> PHY TRG: Adr:%06d Ln:%02d\n",a,l)); 45 #ifdef _SDK_TEFMOD_ 46 #define PHYMOD_ST const phymod_access_t 47 #define _TRG_OPN(a) _TRGO_(a->addr, a->lane_mask) 48 #define _TRG_CLS(a) _TRGC_(a->addr, a->lane_mask) 49 #endif 50 #ifdef _DV_TB_ 51 #define PHYMOD_ST tefmod_st 52 #define _TRG_OPN(a) _TRGO_(a->prt_ad, a->this_lane) 53 #define _TRG_CLS(a) _TRGC_(a->prt_ad, a->this_lane) 54 #endif 55 56 extern int tefmod_diag_st(PHYMOD_ST *pc, int resolved_speed); 57 58 /** 59 @brief Field OVR diagnostic function 60 @param pc handle to current TSCE context (#PHYMOD_ST) 61 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_ERROR else. 62 @details Field OVR Details 63 Check if the field OVR is set, and if OVR enabled, print the OVR value 64 */ 65 int tefmod_diag_field_or(PHYMOD_ST *pc) 66 { 67 SC_X4_LN_NUM_OVRRr_t num_lanes_or; 68 TX_X4_MISCr_t tx_misc_or; 69 TX_X4_ENC0r_t encode_or; 70 RX_X4_PCS_CTL0r_t rx_x4_pcs_ctrl_or; 71 TX_X4_CRED0r_t crd_or; 72 TX_X4_CRED1r_t crd1_or; 73 TX_X4_LOOPCNTr_t loopcnt_or; 74 TX_X4_MAC_CREDGENCNTr_t mac_cgc_or; 75 76 77 READ_SC_X4_LN_NUM_OVRRr(pc,&num_lanes_or); 78 79 READ_RX_X4_PCS_CTL0r(pc,&rx_x4_pcs_ctrl_or); 80 81 READ_TX_X4_MISCr(pc,&tx_misc_or); 82 READ_TX_X4_ENC0r(pc,&encode_or); 83 READ_TX_X4_CRED0r(pc,&crd_or); 84 READ_TX_X4_CRED1r(pc,&crd1_or); 85 READ_TX_X4_LOOPCNTr(pc,&loopcnt_or); 86 READ_TX_X4_MAC_CREDGENCNTr(pc,&mac_cgc_or); 87 88 PHYMOD_DEBUG_ERROR(("| OEN SET OVR VALUE |\n")); 89 PHYMOD_DEBUG_ERROR(("+----------------+----------------+--------------------------------------------+\n")); 90 PHYMOD_DEBUG_ERROR(("| NUM LANES: 0x%x | FEC ENA : 0x%X | %-43s|\n", 91 SC_X4_LN_NUM_OVRRr_NUM_LANES_OVERRIDE_VALUEf_GET(num_lanes_or), 92 TX_X4_MISCr_FEC_ENABLEf_GET(tx_misc_or), 93 e2s_tefmod_scr_mode[TX_X4_MISCr_SCR_MODEf_GET(tx_misc_or)]+6)); 94 95 PHYMOD_DEBUG_ERROR(("| | %-15s| %-43s|\n", 96 e2s_tefmod_os_mode_type[TX_X4_MISCr_OS_MODEf_GET(tx_misc_or)]+6, 97 e2s_tefmod_encode_mode[TX_X4_ENC0r_T_ENC_MODEf_GET(encode_or)]+6)); 98 99 PHYMOD_DEBUG_ERROR(("| TXLN RSTB: 0x%X | TX LN ENA: 0x%X | %-43s|\n", 100 TX_X4_MISCr_RSTB_TX_LANEf_GET(tx_misc_or), 101 TX_X4_MISCr_ENABLE_TX_LANEf_GET(tx_misc_or), 102 e2s_tefmod_descrambler_mode[RX_X4_PCS_CTL0r_DESCR_MODEf_GET(rx_x4_pcs_ctrl_or)]+6)); 103 104 PHYMOD_DEBUG_ERROR(("| CLKCNT0 : 0x%x | CLKCNT1 : 0x%X | %-43s|\n", 105 TX_X4_CRED0r_CLOCKCNT0f_GET(crd_or), 106 TX_X4_CRED1r_CLOCKCNT1f_GET(crd1_or), 107 e2s_tefmod_dec_tl_mode[RX_X4_PCS_CTL0r_DEC_TL_MODEf_GET(rx_x4_pcs_ctrl_or)]+6)); 108 109 PHYMOD_DEBUG_ERROR(("| LP CNT0 : 0x%x | LP CNT1 : 0x%X | %-43s|\n", 110 TX_X4_LOOPCNTr_LOOPCNT0f_GET(loopcnt_or), 111 TX_X4_LOOPCNTr_LOOPCNT1f_GET(loopcnt_or), 112 e2s_tefmod_deskew_mode[RX_X4_PCS_CTL0r_DESKEW_MODEf_GET(rx_x4_pcs_ctrl_or)]+6)); 113 114 PHYMOD_DEBUG_ERROR(("| MACCRDGEN: 0x%x | CL74FECEN: %d | %-43s|\n", 115 TX_X4_MAC_CREDGENCNTr_MAC_CREDITGENCNTf_GET(mac_cgc_or), 116 RX_X4_PCS_CTL0r_FEC_ENABLEf_GET(rx_x4_pcs_ctrl_or), 117 e2s_tefmod_dec_fsm_mode[RX_X4_PCS_CTL0r_DEC_FSM_MODEf_GET(rx_x4_pcs_ctrl_or)]+6)); 118 119 120 PHYMOD_DEBUG_ERROR(("+----------------+--+-------------+------+------------------+------------------+\n")); 121 122 return PHYMOD_E_NONE; 123 } 124 125 /** 126 @brief pmd pcs lane cfg diagnostic function 127 @param pc handle to current TSCE context (#PHYMOD_ST) 128 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_ERROR else. 129 @details Get the uc controls for pmd lane cfg 130 Read the pcs_lane_cfg information from uc RAM. To check if the pmd is to be 131 programmed from pcs lane cfg. 132 */ 133 int tefmod_diag_pmd_pcs_lane_cfg(PHYMOD_ST *pc, int lane) 134 { 135 _TRG_OPN(pc); 136 _TRG_CLS(pc); 137 return PHYMOD_E_NONE; 138 } /* tefmod_diag_pmd_pcs_lane_cfg */ 139 140 /** 141 @brief Speed diagnostic function 142 @param pc handle to current TSCE context (#PHYMOD_ST) 143 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_ERROR else. 144 @details Speed Details 145 1. Get the Speed set 146 2. Get the Speed valis and Speed Done Status 147 3. Get the final stats of the speed 148 */ 149 int tefmod_diag_speed(PHYMOD_ST *pc) 150 { 151 SC_X4_STSr_t sc_ctrl_status; 152 SC_X4_RSLVD_SPDr_t sc_final_resolved_speed; 153 SC_X4_RSLVD0r_t sc_final_resolved_0; 154 SC_X4_RSLVD1r_t sc_final_resolved_1; 155 SC_X4_RSLVD2r_t sc_final_resolved_2; 156 SC_X4_RSLVD3r_t sc_final_resolved_3; 157 SC_X4_RSLVD4r_t sc_final_resolved_4; 158 SC_X4_RSLVD5r_t sc_final_resolved_5; 159 MAIN0_SETUPr_t setup_reg; 160 PLL_CAL_CTL7r_t pll_div_reg; 161 162 PHYMOD_DEBUG_ERROR(("| TRG ADR : %06d LANE: %02d SPEED |\n", pc->addr, pc->lane_mask)); 163 PHYMOD_DEBUG_ERROR(("+---------------------+-----------------------------+-----------+--------------+\n")); 164 165 /*1. Get the Speed valid and Speed Done Status */ 166 READ_SC_X4_STSr(pc,&sc_ctrl_status); 167 168 /*2. Get the Speed set */ 169 /*2a PLLDIV and the refclk settings */ 170 READ_SC_X4_RSLVD_SPDr(pc,&sc_final_resolved_speed); 171 READ_MAIN0_SETUPr(pc,&setup_reg); 172 READ_PLL_CAL_CTL7r(pc,&pll_div_reg); 173 174 /*2b Check if the Speed id is existent in ST */ 175 tefmod_diag_st(pc, SC_X4_RSLVD_SPDr_SPEEDf_GET(sc_final_resolved_speed)); 176 tefmod_diag_field_or(pc); 177 178 /*3. Get the final stats for the speed */ 179 READ_SC_X4_RSLVD0r(pc,&sc_final_resolved_0); 180 READ_SC_X4_RSLVD2r(pc,&sc_final_resolved_2); 181 182 183 READ_SC_X4_RSLVD1r(pc,&sc_final_resolved_1); 184 185 READ_SC_X4_RSLVD3r(pc,&sc_final_resolved_3); 186 READ_SC_X4_RSLVD4r(pc,&sc_final_resolved_4); 187 READ_SC_X4_RSLVD5r(pc,&sc_final_resolved_5); 188 189 190 PHYMOD_DEBUG_ERROR(("| SPEED | STATS0 | STATS1 | CREDIT STATS |\n")); 191 PHYMOD_DEBUG_ERROR(("+-------------------+--------------------+------------------+------------------+\n")); 192 PHYMOD_DEBUG_ERROR(("| SPD CHG VLD %d | OS MODE %-6s | DESCR MODE %-6s| |\n", 193 SC_X4_STSr_SW_SPEED_CONFIG_VLDf_GET(sc_ctrl_status), 194 e2s_tefmod_os_mode_type[SC_X4_RSLVD0r_OS_MODEf_GET(sc_final_resolved_0)]+18, 195 e2s_tefmod_descrambler_mode[SC_X4_RSLVD1r_DESCR_MODEf_GET(sc_final_resolved_1)]+20)); 196 197 PHYMOD_DEBUG_ERROR(("| SPD CHG DONE %d |SCR MODE %-6s|DECODE MODE %-6s| CLK CNT0 : %04d |\n", 198 SC_X4_STSr_SW_SPEED_CHANGE_DONEf_GET(sc_ctrl_status), 199 e2s_tefmod_scr_mode[SC_X4_RSLVD0r_SCR_MODEf_GET(sc_final_resolved_0)]+15, 200 e2s_tefmod_dec_tl_mode[SC_X4_RSLVD1r_DEC_TL_MODEf_GET(sc_final_resolved_1)]+19, 201 SC_X4_RSLVD2r_CLOCKCNT0f_GET(sc_final_resolved_2))); 202 203 PHYMOD_DEBUG_ERROR(("| SPD RESOLVED %04d | ENC MODE %-6s |DESKEW MODE %-6s| CLK CNT1 : %04d |\n", 204 SC_X4_RSLVD_SPDr_SPEEDf_GET(sc_final_resolved_speed), 205 e2s_tefmod_encode_mode[SC_X4_RSLVD0r_T_ENC_MODEf_GET(sc_final_resolved_0)]+18, 206 e2s_tefmod_deskew_mode[SC_X4_RSLVD1r_DESKEW_MODEf_GET(sc_final_resolved_1)]+20, 207 SC_X4_RSLVD3r_CLOCKCNT1f_GET(sc_final_resolved_3))); 208 209 PHYMOD_DEBUG_ERROR(("| #LN RESOLVED %04d |BS SM SYNC MODE %d |DECFSM MODE %-6s| LP CNT0 : %04d |\n", 210 SC_X4_RSLVD_SPDr_NUM_LANESf_GET(sc_final_resolved_speed), 211 SC_X4_RSLVD1r_BS_SM_SYNC_MODEf_GET(sc_final_resolved_1), 212 e2s_tefmod_dec_fsm_mode[SC_X4_RSLVD1r_DEC_FSM_MODEf_GET(sc_final_resolved_1)]+17, 213 SC_X4_RSLVD4r_LOOPCNT0f_GET(sc_final_resolved_4))); 214 215 PHYMOD_DEBUG_ERROR(("| PLL DIV %04d | CL72 ENA : %02d | REF CLOCK :%04d | LP CNT1 : %04d |\n", 216 PLL_CAL_CTL7r_PLL_MODEf_GET(pll_div_reg), 217 SC_X4_RSLVD0r_CL72_ENf_GET(sc_final_resolved_0), 218 MAIN0_SETUPr_REFCLK_SELf_GET(setup_reg), 219 SC_X4_RSLVD4r_LOOPCNT1f_GET(sc_final_resolved_4))); 220 221 PHYMOD_DEBUG_ERROR(("+-------------------+--------------------+------------------+------------------+\n")); 222 223 return PHYMOD_E_NONE; 224 } 225 226 /** 227 @brief Autoneg diagnostic function 228 @param pc handle to current TSCE context (#PHYMOD_ST) 229 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_ERROR else. 230 @details Autoneg diags 231 1. Get the AN complete status for AN37/73 232 2. Get the resolved HCD 233 3. Get the link up status after AN 234 */ 235 int tefmod_diag_autoneg(PHYMOD_ST *pc) 236 { 237 238 AN_X4_CL73_CFGr_t an_cfg; 239 AN_X4_LD_UP1_ABIL0r_t up1_abil0; 240 AN_X4_LD_UP1_ABIL1r_t up1_abil1; 241 AN_X4_LD_BASE_ABIL0r_t base_abil0; 242 AN_X4_LD_BASE_ABIL1r_t base_abil1; 243 AN_X4_LD_BAM_ABILr_t bam_abil; 244 AN_X4_CL73_CTLSr_t an_ctrl; 245 uint16_t base_sel, lanes; 246 247 READ_AN_X4_CL73_CFGr (pc, &an_cfg); 248 READ_AN_X4_LD_UP1_ABIL0r (pc, &up1_abil0); 249 READ_AN_X4_LD_UP1_ABIL1r (pc, &up1_abil1); 250 READ_AN_X4_LD_BASE_ABIL0r (pc, &base_abil0); 251 READ_AN_X4_LD_BASE_ABIL1r (pc, &base_abil1); 252 READ_AN_X4_LD_BAM_ABILr (pc, &bam_abil); 253 READ_AN_X4_CL73_CTLSr (pc, &an_ctrl); 254 255 PHYMOD_DEBUG_ERROR(("+-------------------+-------+------+-----------------------+-------------------+\n")); 256 PHYMOD_DEBUG_ERROR(("| ANX4 CFG : 0x%04X | UP1 ABIL0 : 0x%04X | UP1 ABIL1 : 0x%04X |\n", 257 AN_X4_CL73_CFGr_GET(an_cfg), AN_X4_LD_UP1_ABIL0r_GET(up1_abil0), AN_X4_LD_UP1_ABIL1r_GET(up1_abil1))); 258 PHYMOD_DEBUG_ERROR(("| BASE ABIL0: 0x%04X | BASE ABIL1: 0x%04X | BAM ABIL :0x%04X CTLS:0x%04X |\n", 259 AN_X4_LD_BASE_ABIL0r_GET(base_abil0), AN_X4_LD_BASE_ABIL1r_GET(base_abil1), 260 AN_X4_LD_BAM_ABILr_GET(bam_abil), AN_X4_CL73_CTLSr_GET(an_ctrl))); 261 262 lanes = AN_X4_CL73_CFGr_NUM_ADVERTISED_LANESf_GET(an_cfg); 263 PHYMOD_DEBUG_ERROR(("+-------------------+--------------+----+--------------------------------------+\n")); 264 PHYMOD_DEBUG_ERROR(("| BAM ENA : %d | HPAM ENA : %d | NUM ADV LANES : %d |\n", 265 AN_X4_CL73_CFGr_CL73_BAM_ENABLEf_GET(an_cfg), 266 AN_X4_CL73_CFGr_CL73_HPAM_ENABLEf_GET(an_cfg), 267 (lanes == 0? 1 : (lanes == 1? 2 : (lanes == 3? 10 : 1))))); 268 269 PHYMOD_DEBUG_ERROR(("| AN RESTART : %d | BAM2HPAM ENA : %d | FAIL COUNT LIM: %d |\n", 270 AN_X4_CL73_CFGr_CL73_AN_RESTARTf_GET(an_cfg), 271 AN_X4_CL73_CFGr_BAM_TO_HPAM_AD_ENf_GET(an_cfg), 272 AN_X4_CL73_CTLSr_AN_FAIL_COUNT_LIMITf_GET(an_ctrl))); 273 274 base_sel = AN_X4_LD_BASE_ABIL0r_CL73_BASE_SELECTORf_GET(base_abil0); 275 276 PHYMOD_DEBUG_ERROR(("+-------------------+-------------------+--------------------------------------+\n")); 277 PHYMOD_DEBUG_ERROR(("| UP 0/1 ABILITIES | BASE 0/1 ABILITIES |\n")); 278 PHYMOD_DEBUG_ERROR(("+----------+---------------+------------+-----------------+--------------------+\n")); 279 280 PHYMOD_DEBUG_ERROR(("| HG2 :%d | BAM CODE : 0x%X | TX NONCE : 0x%X | BASE SEL : %-7s |\n", 281 AN_X4_LD_UP1_ABIL0r_BAM_HG2f_GET(up1_abil0), 282 AN_X4_LD_BAM_ABILr_CL73_BAM_CODEf_GET(bam_abil), 283 AN_X4_LD_BASE_ABIL0r_TX_NONCEf_GET(base_abil0), 284 (base_sel == 0? "Rsvd" : 285 (base_sel == 1? "802.3" : 286 (base_sel == 2? "802.9" : 287 (base_sel == 3? "802.5": 288 (base_sel == 4? "1394": "UNKNOWN"))))) )); 289 290 PHYMOD_DEBUG_ERROR(("| 50G CR4:%d | 40G CR2:%d | 20G CR2 :%d | PAUSE : %d | FEC : %d RMT FLT : %d |\n", 291 AN_X4_LD_UP1_ABIL0r_BAM_50G_CR4f_GET(up1_abil0), 292 AN_X4_LD_UP1_ABIL0r_BAM_40G_CR2f_GET(up1_abil0), 293 AN_X4_LD_UP1_ABIL0r_BAM_20G_CR2f_GET(up1_abil0), 294 AN_X4_LD_BASE_ABIL1r_CL73_PAUSEf_GET(base_abil1), 295 AN_X4_LD_BASE_ABIL1r_FEC_REQf_GET(base_abil1), 296 AN_X4_LD_BASE_ABIL1r_CL73_REMOTE_FAULTf_GET(base_abil1))); 297 298 PHYMOD_DEBUG_ERROR(("| 50G KR4:%d | 40G KR2:%d | 20G KR2 :%d | BASE 1G KX1: %d | BASE 100G CR4 : %d |\n", 299 AN_X4_LD_UP1_ABIL0r_BAM_50G_KR4f_GET(up1_abil0), 300 AN_X4_LD_UP1_ABIL0r_BAM_40G_KR2f_GET(up1_abil0), 301 AN_X4_LD_UP1_ABIL0r_BAM_20G_KR2f_GET(up1_abil0), 302 AN_X4_LD_BASE_ABIL1r_BASE_1G_KX1f_GET(base_abil1), 303 AN_X4_LD_BASE_ABIL1r_BASE_100G_CR4f_GET(base_abil1))); 304 305 PHYMOD_DEBUG_ERROR(("| 50G CR2:%d | 25G CR1:%d | 20G CR1 :%d | BASE 40G CR4: %d | BASE 40G KR4 : %d |\n", 306 AN_X4_LD_UP1_ABIL0r_BAM_50G_CR2f_GET(up1_abil0), 307 AN_X4_LD_UP1_ABIL1r_BAM_25G_CR1f_GET(up1_abil1), 308 AN_X4_LD_UP1_ABIL1r_BAM_20G_CR1f_GET(up1_abil1), 309 AN_X4_LD_BASE_ABIL1r_BASE_40G_CR4f_GET(base_abil1), 310 AN_X4_LD_BASE_ABIL1r_BASE_40G_KR4f_GET(base_abil1))); 311 312 PHYMOD_DEBUG_ERROR(("| 50G KR2:%d | 25G KR1:%d | 20G KR1 :%d | BASE 10G KR1 : %d | NEXT PAGE : %d |\n", 313 AN_X4_LD_UP1_ABIL0r_BAM_50G_KR2f_GET(up1_abil0), 314 AN_X4_LD_UP1_ABIL1r_BAM_25G_KR1f_GET(up1_abil1), 315 AN_X4_LD_UP1_ABIL1r_BAM_20G_KR1f_GET(up1_abil1), 316 AN_X4_LD_BASE_ABIL1r_BASE_10G_KR1f_GET(base_abil1), 317 AN_X4_LD_BASE_ABIL1r_NEXT_PAGEf_GET(base_abil1))); 318 319 return PHYMOD_E_NONE; 320 } 321 322 323 /** 324 @brief Topology diagnostic function. 325 @param pc handle to current TSCE context (#PHYMOD_ST) 326 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_ERROR else. 327 @details Get the topology details 328 1. LoopBack 329 a. Remote Loopback - RX loopback 330 i. PCS loopback 331 ii. PMD loopback //Not tested in TSCE 332 b. Local loopback/gloop - TX loopback 333 i. PCS loopback 334 ii. PMD loopback 335 2. LaneSwap 336 a. PCS LaneSwap(RX) 337 b. PMD LaneSwap(TX) 338 3. Master PortNum, port mode and single port mode 339 340 */ 341 int tefmod_diag_topology(PHYMOD_ST *pc) 342 { 343 MAIN0_LPBK_CTLr_t pcs_loopback_ctrl; 344 TLB_RX_DIG_LPBK_CFGr_t pmd_loopback_dig; 345 TLB_TX_RMT_LPBK_CFGr_t pmd_loopback_remote; 346 MAIN0_LN_SWPr_t pcs_lane_swap; 347 DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r_t pmd_lane_addr_swap_1; 348 DIG_LN_ADDR_2_3r_t pmd_lane_addr_swap_2; 349 DIG_TX_LN_MAP_0_1_2r_t pmd_lane_addr_swap_3; 350 MAIN0_SETUPr_t reg_main0_setup; 351 352 /* Main0 Setup Register */ 353 /*1. Loopback */ 354 READ_MAIN0_LPBK_CTLr(pc, &pcs_loopback_ctrl); 355 READ_TLB_RX_DIG_LPBK_CFGr(pc, &pmd_loopback_dig); 356 READ_TLB_TX_RMT_LPBK_CFGr(pc, &pmd_loopback_remote); 357 358 /*2. LaneSwap */ 359 READ_MAIN0_LN_SWPr(pc, &pcs_lane_swap); 360 READ_DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r(pc, &pmd_lane_addr_swap_1); 361 READ_DIG_LN_ADDR_2_3r(pc, &pmd_lane_addr_swap_2); 362 READ_DIG_TX_LN_MAP_0_1_2r(pc, &pmd_lane_addr_swap_3); 363 364 /* 3. Master PortNum, port mode abd single port mode */ 365 READ_MAIN0_SETUPr(pc, ®_main0_setup); 366 367 368 /* Print the information here */ 369 { 370 uint16_t pcs_lcl_lb, pcs_rmt_lb, pmd_dig_lb, pmd_rmt_lb; 371 372 pcs_lcl_lb = MAIN0_LPBK_CTLr_LOCAL_PCS_LOOPBACK_ENABLEf_GET(pcs_loopback_ctrl); 373 pcs_rmt_lb = MAIN0_LPBK_CTLr_REMOTE_PCS_LOOPBACK_ENABLEf_GET(pcs_loopback_ctrl); 374 pmd_dig_lb = TLB_RX_DIG_LPBK_CFGr_DIG_LPBK_ENf_GET(pmd_loopback_dig); 375 pmd_rmt_lb = TLB_TX_RMT_LPBK_CFGr_RMT_LPBK_ENf_GET(pmd_loopback_remote); 376 377 PHYMOD_DEBUG_ERROR(("\n")); 378 PHYMOD_DEBUG_ERROR(("+------------------------------------------------------------------------------+\n")); 379 PHYMOD_DEBUG_ERROR(("| TRG ADR : %06d LANE: %02d TOPOLOGY |\n", pc->addr, pc->lane_mask)); 380 PHYMOD_DEBUG_ERROR(("+-------------------+--------------------------+---------------+---------------+\n")); 381 PHYMOD_DEBUG_ERROR(("| PCSLCL LPBK: %c%c%c%c | PCS LANE SWAP L2P : %d%d%d%d | FEC SEL: %d | PLLRST EN: %d |\n", 382 (pcs_lcl_lb & 8) ? 'Y':'N', 383 (pcs_lcl_lb & 4) ? 'Y':'N', 384 (pcs_lcl_lb & 2) ? 'Y':'N', 385 (pcs_lcl_lb & 1) ? 'Y':'N', 386 MAIN0_LN_SWPr_LOGICAL3_TO_PHY_SELf_GET(pcs_lane_swap), 387 MAIN0_LN_SWPr_LOGICAL2_TO_PHY_SELf_GET(pcs_lane_swap), 388 MAIN0_LN_SWPr_LOGICAL1_TO_PHY_SELf_GET(pcs_lane_swap), 389 MAIN0_LN_SWPr_LOGICAL0_TO_PHY_SELf_GET(pcs_lane_swap), 390 MAIN0_LN_SWPr_SPEED_100G_FEC_SELf_GET(pcs_lane_swap), 391 MAIN0_LN_SWPr_PLL_RESET_ENf_GET(pcs_lane_swap))); 392 393 PHYMOD_DEBUG_ERROR(("| PCSRMT LPBK: %c%c%c%c | PMD LANE ADDR IDX : %d%d%d%d | | SNGLMODE : %d |\n", 394 (pcs_rmt_lb & 8) ? 'Y':'N', 395 (pcs_rmt_lb & 4) ? 'Y':'N', 396 (pcs_rmt_lb & 2) ? 'Y':'N', 397 (pcs_rmt_lb & 1) ? 'Y':'N', 398 DIG_LN_ADDR_2_3r_LANE_ADDR_3f_GET(pmd_lane_addr_swap_2), 399 DIG_LN_ADDR_2_3r_LANE_ADDR_2f_GET(pmd_lane_addr_swap_2), 400 DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r_LANE_ADDR_1f_GET(pmd_lane_addr_swap_1), 401 DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r_LANE_ADDR_0f_GET(pmd_lane_addr_swap_1), 402 MAIN0_SETUPr_SINGLE_PORT_MODEf_GET(reg_main0_setup))); 403 404 PHYMOD_DEBUG_ERROR(("| PMDDIG LPBK: %c%c%c%c | PMD TO AFE : %d%d%d%d | | PORT MODE: %d |\n", 405 (pmd_dig_lb & 8) ? 'Y':'N', 406 (pmd_dig_lb & 4) ? 'Y':'N', 407 (pmd_dig_lb & 2) ? 'Y':'N', 408 (pmd_dig_lb & 1) ? 'Y':'N', 409 DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r_TX_LANE_MAP_3f_GET(pmd_lane_addr_swap_1), 410 DIG_TX_LN_MAP_0_1_2r_TX_LANE_MAP_2f_GET(pmd_lane_addr_swap_3), 411 DIG_TX_LN_MAP_0_1_2r_TX_LANE_MAP_1f_GET(pmd_lane_addr_swap_3), 412 DIG_TX_LN_MAP_0_1_2r_TX_LANE_MAP_0f_GET(pmd_lane_addr_swap_3), 413 MAIN0_SETUPr_PORT_MODE_SELf_GET(reg_main0_setup))); 414 415 PHYMOD_DEBUG_ERROR(("| PMDREM LPBK: %c%c%c%c | | |\n", 416 (pmd_rmt_lb & 8) ? 'Y':'N', 417 (pmd_rmt_lb & 4) ? 'Y':'N', 418 (pmd_rmt_lb & 2) ? 'Y':'N', 419 (pmd_rmt_lb & 1) ? 'Y':'N')); 420 PHYMOD_DEBUG_ERROR(("+-------------------+--------------------------+-------------------------------+\n")); 421 422 } 423 return PHYMOD_E_NONE; 424 } 425 426 /** 427 @brief Get the link status 428 @param pc handle to current TSCE context (#PHYMOD_ST) 429 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_ERROR else. 430 @details Print the link status. 431 1. pmd_live_status 432 a. pll_lock_sts : PMD PLL lock indication 433 //b. tx_clk_vld_sts : The txclk is valid Don't see a need for this now, so will not check this bit 434 2a. pmd_lane_live_status 435 a. signal_detect_sts : The signal detected on the lane 436 b. rx_lock_sts : The recovery clock locked for the rx lane 437 //c. rx_clk_vld_sts : The rxclk is valid for the lane. Don't see a need for this now, so will not check this bit 438 2b. pmd_lane_latched_status 439 3a. pcs_live_status 440 a. sync status : per port: Live Sync Status indicator for cl36, cl48, brcm mode. Comma detect/code sync 441 per lane: Live Block Lock Status indicator for cl49, cl82.Sync bits locked, on the 2 sync bits of the 66 bits(of 64/66 encoding) 442 b. link_status : Link status for that port 443 3b. pcs_latched_status 444 */ 445 int tefmod_diag_link(PHYMOD_ST *pc) 446 { 447 PMD_X1_STSr_t pmd_live_status; 448 PMD_X4_STSr_t pmd_lane_live_status; 449 phymod_access_t *lpc = (phymod_access_t*)pc; 450 451 int i,rx_lock_sts[4],sig_det_sts[4], this_lane; 452 453 454 /*1. pmd_live_status */ 455 READ_PMD_X1_STSr(pc, &pmd_live_status); 456 457 /*2a. pmd_lane_live_status */ 458 459 this_lane = lpc->lane_mask; 460 for(i=0; i < 4; i++) { 461 lpc->lane_mask = 1<<i; 462 READ_PMD_X4_STSr(lpc, &pmd_lane_live_status); 463 sig_det_sts[i] = PMD_X4_STSr_SIGNAL_DETECT_STSf_GET(pmd_lane_live_status); 464 rx_lock_sts[i] = PMD_X4_STSr_RX_LOCK_STSf_GET(pmd_lane_live_status); 465 } 466 lpc->lane_mask = this_lane; 467 468 469 470 /* Print the information here */ 471 PHYMOD_DEBUG_ERROR(("| TRG ADR : %06d LANE: %02d LINK STATE | LH | LL |\n", pc->addr, pc->lane_mask)); 472 PHYMOD_DEBUG_ERROR(("+-----------------------+-------------------+---------------+---------+--------+\n")); 473 PHYMOD_DEBUG_ERROR(("| PMD PLL LOCK : %c | PCS SYNC : ?? | |\n", 474 (PMD_X1_STSr_PLL_LOCK_STSf_GET(pmd_live_status) == 1) ? 'Y' : 'N')); 475 476 PHYMOD_DEBUG_ERROR(("| PMD SIG DETECT : %c%c%c%c | PCS LINK : ?? | |\n", 477 (sig_det_sts[3] == 1)? 'Y':'N', 478 (sig_det_sts[2] == 1)? 'Y':'N', 479 (sig_det_sts[1] == 1)? 'Y':'N', 480 (sig_det_sts[0] == 1)? 'Y':'N')); 481 482 PHYMOD_DEBUG_ERROR(("| PMD LOCKED : %c%c%c%c | PCS HI BER : ?? | |\n", 483 (rx_lock_sts[3] == 1)? 'Y':'N', 484 (rx_lock_sts[2] == 1)? 'Y':'N', 485 (rx_lock_sts[1] == 1)? 'Y':'N', 486 (rx_lock_sts[0] == 1)? 'Y':'N')); 487 488 489 PHYMOD_DEBUG_ERROR(("| | PCS AMLOCK : ?? | PCS AM LOCK : ?? : ?? |\n")); 490 491 PHYMOD_DEBUG_ERROR(("+-----------------------+-------------------+----------------------------------+\n")); 492 493 return PHYMOD_E_NONE; 494 } 495 496 /** 497 @brief Get the link status 498 @param pc handle to current TSCE context (#PHYMOD_ST) 499 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_ERROR else. 500 @details Call all the Diags 501 */ 502 int tefmod_diag_general(PHYMOD_ST *pc) 503 { 504 tefmod_diag_topology(pc); 505 tefmod_diag_link(pc); 506 tefmod_diag_autoneg(pc); 507 tefmod_diag_speed(pc); 508 509 return (PHYMOD_E_NONE); 510 } 511 512 /** 513 @brief Internal Tfc info (PRBS vs. PRTP. vs. PktGen etc.). 514 @param pc handle to current TSCE context (#PHYMOD_ST) 515 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_ERROR else. 516 @details Print the Internal Tfc types. 517 TBD. 518 */ 519 int tefmod_diag_internal_tfc(PHYMOD_ST *pc) 520 { 521 /* 522 PKTGEN_CTL1r_t reg_pktgen_ctl1; 523 PKTGEN_CTL2r_t reg_pktgen_ctl2; 524 PKTGEN_CTL3r_t reg_pktgen_ctl3; 525 */ 526 PKTGEN_PRTPCTLr_t reg_prtp_ctl; 527 528 /* 529 READ_PKTGEN_CTL1r(pc, ®_pktgen_ctl1); 530 READ_PKTGEN_CTL2r(pc, ®_pktgen_ctl2); 531 READ_PKTGEN_CTL3r(pc, ®_pktgen_ctl3); 532 */ 533 READ_PKTGEN_PRTPCTLr(pc, ®_prtp_ctl); 534 535 PHYMOD_DEBUG_ERROR(("| TRG ADR : %06d LANE: %02d INTERNAL TFC |\n", 536 pc->addr, pc->lane_mask)); 537 PHYMOD_DEBUG_ERROR(("+------------------------------------------+-----------------------------------+\n")); 538 539 PHYMOD_DEBUG_ERROR(("| TX PRTP EN : %d | RX PRTP EN : %d | |\n", 540 PKTGEN_PRTPCTLr_TX_PRTP_ENf_GET(reg_prtp_ctl), 541 PKTGEN_PRTPCTLr_RX_PRTP_ENf_GET(reg_prtp_ctl))); 542 543 PHYMOD_DEBUG_ERROR(("+------------------------------------------+-----------------------------------+\n")); 544 545 return PHYMOD_E_NONE; 546 } 547 548 /** 549 @brief Soft Table diagnostic function 550 @param pc handle to current TSCE context (#PHYMOD_ST) 551 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_ERROR else. 552 @details ST diags 553 Print the soft table enteries 554 if the resolved_speed is not set, then all the table enteries are displayed 555 */ 556 557 #define _TRG_ST_PRINT(pc, st_num, ovr, sc_st) \ 558 { \ 559 SC_X1_SPD_##ovr##_SPDr_t sc_st##_speed; \ 560 SC_X1_SPD_##ovr##_0r_t sc_st##_0; \ 561 SC_X1_SPD_##ovr##_1r_t sc_st##_1; \ 562 SC_X1_SPD_##ovr##_2r_t sc_st##_2; \ 563 SC_X1_SPD_##ovr##_3r_t sc_st##_3; \ 564 SC_X1_SPD_##ovr##_4r_t sc_st##_4; \ 565 SC_X1_SPD_##ovr##_5r_t sc_st##_5; \ 566 uint8_t x1_speed; \ 567 \ 568 READ_SC_X1_SPD_##ovr##_SPDr(pc,&sc_st##_speed); \ 569 x1_speed = SC_X1_SPD_##ovr##_SPDr_SPEEDf_GET(sc_st##_speed); \ 570 x1_speed = (x1_speed >= TEFMOD_SPD_ILLEGAL) ? TEFMOD_SPD_ILLEGAL: x1_speed; \ 571 PHYMOD_DEBUG_ERROR(("| ST [%d] | %-28s| NUM LANES : %d |\n",\ 572 st_num, e2s_tefmod_spd_intfc_type_t[x1_speed]+6, \ 573 SC_X1_SPD_##ovr##_SPDr_NUM_LANESf_GET(sc_st##_speed))); \ 574 \ 575 if((resolved_speed == 0xff) || \ 576 (resolved_speed==SC_X1_SPD_##ovr##_SPDr_SPEEDf_GET(sc_st##_speed))) { \ 577 READ_SC_X1_SPD_##ovr##_0r(pc,&sc_st##_0); \ 578 READ_SC_X1_SPD_##ovr##_1r(pc,&sc_st##_1); \ 579 READ_SC_X1_SPD_##ovr##_2r(pc,&sc_st##_2); \ 580 READ_SC_X1_SPD_##ovr##_3r(pc,&sc_st##_3); \ 581 READ_SC_X1_SPD_##ovr##_4r(pc,&sc_st##_4); \ 582 READ_SC_X1_SPD_##ovr##_5r(pc,&sc_st##_5); \ 583 \ 584 PHYMOD_DEBUG_ERROR(("| %-19s | |\n",\ 585 e2s_tefmod_os_mode_type[SC_X1_SPD_##ovr##_0r_OS_MODEf_GET(sc_st##_0)]+6)); \ 586 \ 587 PHYMOD_DEBUG_ERROR(("| %-19s | |\n",\ 588 e2s_tefmod_scr_mode[SC_X1_SPD_##ovr##_0r_SCR_MODEf_GET(sc_st##_0)]+6)); \ 589 \ 590 PHYMOD_DEBUG_ERROR(("+---------------------+-----------------------------+-----------+--------------+\n"));\ 591 } \ 592 } 593 594 /** 595 @brief Soft Table diagnostic function 596 @param pc handle to current TSCE context (#PHYMOD_ST) 597 @param resolved_speed The speed to which AN is already resolved. 598 @returns PHYMOD_E_NONE 599 @details Soft Table diags 600 Print the soft table enteries 601 if the resolved_speed is not set, then all the table enteries are displayed 602 */ 603 int tefmod_diag_st(PHYMOD_ST *pc, int resolved_speed) 604 { 605 _TRG_ST_PRINT(pc, 0, OVRR0, sc_st0) 606 _TRG_ST_PRINT(pc, 1, OVRR1, sc_st1) 607 _TRG_ST_PRINT(pc, 2, OVRR2, sc_st2) 608 _TRG_ST_PRINT(pc, 3, OVRR2, sc_st3) 609 610 PHYMOD_DEBUG_ERROR(("+---------------------+-----------------------------+-----------+--------------+\n")); 611 return PHYMOD_E_NONE; 612 } 613 614 /** 615 @brief AN Timers diagnostic function 616 @param pc handle to current TSCE context (#PHYMOD_ST) 617 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_ERROR else. 618 @details Prints the AN timers 619 */ 620 int tefmod_diag_an_timers(PHYMOD_ST* pc) 621 { 622 AN_X1_CL73_BRK_LNKr_t reg_cl73_break_link; 623 AN_X1_CL73_ERRr_t reg_cl73_err; 624 AN_X1_CL73_DME_LOCKr_t reg_cl73_dme_lock; 625 AN_X1_PD_SD_TMRr_t reg_pd_sd_timer; 626 AN_X1_IGNORE_LNK_TMRr_t reg_ignore_link_timer; 627 AN_X1_LNK_FAIL_INHBT_TMR_CL72r_t reg_inhibit_timer; 628 AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72r_t reg_inhibit_not_timer; 629 AN_X1_DME_PAGE_TMR_TYPEr_t reg_dme_page_timer; 630 631 632 READ_AN_X1_CL73_ERRr (pc, ®_cl73_err); 633 READ_AN_X1_PD_SD_TMRr (pc, ®_pd_sd_timer); 634 READ_AN_X1_CL73_BRK_LNKr (pc, ®_cl73_break_link); 635 READ_AN_X1_CL73_DME_LOCKr (pc, ®_cl73_dme_lock); 636 READ_AN_X1_IGNORE_LNK_TMRr (pc, ®_ignore_link_timer); 637 638 READ_AN_X1_DME_PAGE_TMR_TYPEr (pc, ®_dme_page_timer); 639 READ_AN_X1_LNK_FAIL_INHBT_TMR_CL72r (pc, ®_inhibit_timer); 640 READ_AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72r (pc, ®_inhibit_not_timer); 641 642 PHYMOD_DEBUG_ERROR(("| TRG ADR : %06d LANE: %02d AN TIMERS |\n", 643 pc->addr, pc->lane_mask)); 644 PHYMOD_DEBUG_ERROR(("+--------------------------------------+---------------------------------------+\n")); 645 646 PHYMOD_DEBUG_ERROR(("| | CL73 BREAK TIMER PERIOD : 0x%08X |\n", 647 AN_X1_CL73_BRK_LNKr_CL73_BREAK_TIMER_PERIODf_GET(reg_cl73_break_link))); 648 649 PHYMOD_DEBUG_ERROR(("| CL73 ERR : 0x%08X | CL73 DME LOCK : 0x%08X |\n", 650 AN_X1_CL73_ERRr_CL73_ERROR_TIMER_PERIODf_GET(reg_cl73_err), 651 AN_X1_CL73_DME_LOCKr_PD_DME_LOCK_TIMER_PERIODf_GET(reg_cl73_dme_lock))); 652 653 PHYMOD_DEBUG_ERROR(("| IGNORE LINK : 0x%08X | PS SD : 0x%08x |\n", 654 AN_X1_IGNORE_LNK_TMRr_IGNORE_LINK_TIMER_PERIODf_GET(reg_ignore_link_timer), 655 AN_X1_PD_SD_TMRr_PD_SD_TIMER_PERIODf_GET(reg_pd_sd_timer))); 656 657 PHYMOD_DEBUG_ERROR(("| DME PAGE MIN : 0x%08X | DME PAGE MAX : 0x%08X |\n", 658 AN_X1_DME_PAGE_TMR_TYPEr_CL73_PAGE_TEST_MIN_TIMERf_GET(reg_dme_page_timer), 659 AN_X1_DME_PAGE_TMR_TYPEr_CL73_PAGE_TEST_MAX_TIMERf_GET(reg_dme_page_timer))); 660 661 PHYMOD_DEBUG_ERROR(("| FAIL INHIBIT W/O CL72 : 0x%08X | FAIL INHIBIT WITH CL72 : 0x%08X |\n", 662 AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72r_LINK_FAIL_INHIBIT_TIMER_NCL72_PERIODf_GET(reg_inhibit_not_timer), 663 AN_X1_LNK_FAIL_INHBT_TMR_CL72r_LINK_FAIL_INHIBIT_TIMER_CL72_PERIODf_GET(reg_inhibit_timer))); 664 665 PHYMOD_DEBUG_ERROR(("+--------------------------------------+---------------------------------------+\n")); 666 return PHYMOD_E_NONE; 667 } 668 669 /** 670 @brief Prints out the debug state register 671 @param pc handle to current TSCE context (#PHYMOD_ST) 672 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_ERROR else. 673 @details Prints the debug state regs. 674 */ 675 int tefmod_diag_state(PHYMOD_ST* pc) 676 { 677 SC_X4_DBGr_t reg_sc_dbg_st; 678 AN_X4_TLA_SEQUENCER_STSr_t reg_an_tla_seq; 679 680 READ_SC_X4_DBGr(pc, ®_sc_dbg_st); 681 READ_AN_X4_TLA_SEQUENCER_STSr(pc, ®_an_tla_seq); 682 683 PHYMOD_DEBUG_ERROR(("| DEBUG STATE |\n")); 684 PHYMOD_DEBUG_ERROR(("+--------------------------------------+---------------------------------------+\n")); 685 PHYMOD_DEBUG_ERROR(("| SC_DEBUG_STATE : 0x%08x | FSM_STATUS : 0x%08X |\n", 686 SC_X4_DBGr_GET(reg_sc_dbg_st), SC_X4_DBGr_SC_FSM_STATUSf_GET(reg_sc_dbg_st))); 687 688 PHYMOD_DEBUG_ERROR(("| TLA_SEQUENCER STS : 0x%08x | |\n", 689 AN_X4_TLA_SEQUENCER_STSr_GET(reg_an_tla_seq))); 690 PHYMOD_DEBUG_ERROR(("+--------------------------------------+---------------------------------------+\n")); 691 692 return PHYMOD_E_NONE; 693 } 694 695 696 /** 697 @brief TBD 698 @param pc handle to current TSCE context (#PHYMOD_ST) 699 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_ERROR else. 700 @details Misc debug 701 */ 702 int tefmod_diag_debug(PHYMOD_ST* pc) 703 { 704 _TRG_OPN(pc); 705 _TRG_CLS(pc); 706 return PHYMOD_E_NONE; 707 } 708 709 /** 710 @brief TBD 711 @param pc handle to current TSCE context (#PHYMOD_ST) 712 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_ERROR else. 713 @details Misc debug 714 */ 715 int tefmod_diag_ieee(PHYMOD_ST *pc) 716 { 717 _TRG_OPN(pc); 718 _TRG_CLS(pc); 719 return PHYMOD_E_NONE; 720 } 721 722 /** 723 @brief TBD 724 @param pc handle to current TSCE context (#PHYMOD_ST) 725 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_ERROR else. 726 @details Misc debug 727 */ 728 int tefmod_diag(PHYMOD_ST *pc, tefmod_diag_type_t diag_type) 729 { 730 int rv; 731 rv = PHYMOD_E_NONE; 732 733 _TRG_OPN(pc); 734 735 if(diag_type & TEFMOD_DIAG_GENERAL) rv |= tefmod_diag_general(pc); 736 if(diag_type & TEFMOD_DIAG_TOPOLOGY) rv |= tefmod_diag_topology(pc); 737 if(diag_type & TEFMOD_DIAG_LINK) rv |= tefmod_diag_link(pc); 738 if(diag_type & TEFMOD_DIAG_SPEED) rv |= tefmod_diag_speed(pc); 739 if(diag_type & TEFMOD_DIAG_ANEG) rv |= tefmod_diag_autoneg(pc); 740 if(diag_type & TEFMOD_DIAG_TFC) rv |= tefmod_diag_internal_tfc(pc); 741 if(diag_type & TEFMOD_DIAG_AN_TIMERS) rv |= tefmod_diag_an_timers(pc); 742 if(diag_type & TEFMOD_DIAG_STATE) rv |= tefmod_diag_state(pc); 743 if(diag_type & TEFMOD_DIAG_DEBUG) rv |= tefmod_diag_debug(pc); 744 _TRG_CLS(pc); 745 return rv; 746 } 747 748 /*! 749 */ 750 int tefmod_diag_disp(PHYMOD_ST *pc, const char* cmd_str) 751 { 752 tefmod_diag_type_t type; 753 754 if (!cmd_str) 755 type = TEFMOD_DIAG_GENERAL; 756 else if (!PHYMOD_STRCMP(cmd_str, "topo")) 757 type = TEFMOD_DIAG_TOPOLOGY; 758 else if (!PHYMOD_STRCMP(cmd_str, "link")) 759 type = TEFMOD_DIAG_LINK; 760 else if (!PHYMOD_STRCMP(cmd_str, "speed")) 761 type = TEFMOD_DIAG_SPEED; 762 else if (!PHYMOD_STRCMP(cmd_str, "aneg")) 763 type = TEFMOD_DIAG_ANEG; 764 else if (!PHYMOD_STRCMP(cmd_str, "tfc")) 765 type = TEFMOD_DIAG_TFC; 766 else if (!PHYMOD_STRCMP(cmd_str, "antimers")) 767 type = TEFMOD_DIAG_AN_TIMERS; 768 else if (!PHYMOD_STRCMP(cmd_str, "state")) 769 type = TEFMOD_DIAG_STATE; 770 else if (!PHYMOD_STRCMP(cmd_str, "debug")) 771 type = TEFMOD_DIAG_DEBUG; 772 else 773 type = TEFMOD_DIAG_GENERAL; 774 775 return (tefmod_diag(pc, type)); 776 } 777 778 int tfmod_diag_set_poly_tx(PHYMOD_ST *pc, uint32_t lane, uint32_t poly) { 779 phymod_access_t copy; 780 TLB_TX_PRBS_GEN_CFGr_t gen_cfg; 781 782 PHYMOD_MEMCPY(©, pc, sizeof(copy)); 783 copy.lane_mask = lane; 784 READ_TLB_TX_PRBS_GEN_CFGr(©, &gen_cfg); 785 TLB_TX_PRBS_GEN_CFGr_PRBS_GEN_MODE_SELf_SET(gen_cfg, poly); 786 WRITE_TLB_TX_PRBS_GEN_CFGr(©, gen_cfg); 787 return PHYMOD_E_NONE; 788 } 789 790 int tfmod_diag_set_poly_rx(PHYMOD_ST *pc, uint32_t lane, uint32_t poly) { 791 phymod_access_t copy; 792 TLB_RX_PRBS_CHK_CFGr_t chk_cfg; 793 794 PHYMOD_MEMCPY(©, pc, sizeof(copy)); 795 copy.lane_mask = lane; 796 READ_TLB_RX_PRBS_CHK_CFGr(©, &chk_cfg); 797 TLB_RX_PRBS_CHK_CFGr_PRBS_CHK_MODEf_SET(chk_cfg, poly); 798 WRITE_TLB_RX_PRBS_CHK_CFGr(©, chk_cfg); 799 return PHYMOD_E_NONE; 800 } 801 802 int tfmod_diag_inject_error(PHYMOD_ST *pc, uint32_t lane) { 803 phymod_access_t copy; 804 TLB_TX_PRBS_GEN_CFGr_t gen_cfg; 805 806 PHYMOD_MEMCPY(©, pc, sizeof(copy)); 807 copy.lane_mask = lane; 808 READ_TLB_TX_PRBS_GEN_CFGr(©, &gen_cfg); 809 TLB_TX_PRBS_GEN_CFGr_PRBS_GEN_ERR_INSf_SET(gen_cfg, 0x1); 810 WRITE_TLB_TX_PRBS_GEN_CFGr(©, gen_cfg); 811 return PHYMOD_E_NONE; 812 } 813 814 int tfmod_diag_gen_set(PHYMOD_ST *pc, uint32_t lane, uint32_t action) { 815 phymod_access_t copy; 816 TLB_TX_PRBS_GEN_CFGr_t gen_cfg; 817 818 PHYMOD_MEMCPY(©, pc, sizeof(copy)); 819 copy.lane_mask = lane; 820 READ_TLB_TX_PRBS_GEN_CFGr(©, &gen_cfg); 821 TLB_TX_PRBS_GEN_CFGr_PRBS_GEN_ENf_SET(gen_cfg, action); 822 WRITE_TLB_TX_PRBS_GEN_CFGr(©, gen_cfg); 823 return PHYMOD_E_NONE; 824 } 825 826 int tfmod_diag_chk_set(PHYMOD_ST *pc, uint32_t lane, uint32_t action) { 827 phymod_access_t copy; 828 TLB_RX_PRBS_CHK_CFGr_t chk_cfg; 829 830 PHYMOD_MEMCPY(©, pc, sizeof(copy)); 831 copy.lane_mask = lane; 832 READ_TLB_RX_PRBS_CHK_CFGr(©, &chk_cfg); 833 TLB_RX_PRBS_CHK_CFGr_PRBS_CHK_CLK_EN_FRC_ONf_SET(chk_cfg, action); 834 TLB_RX_PRBS_CHK_CFGr_PRBS_CHK_ENf_SET(chk_cfg, action); 835 TLB_RX_PRBS_CHK_CFGr_PRBS_CHK_MODE_SELf_SET(chk_cfg, action); 836 WRITE_TLB_RX_PRBS_CHK_CFGr(©, chk_cfg); 837 return PHYMOD_E_NONE; 838 } 839 840 int tfmod_diag_get_lock(PHYMOD_ST *pc, uint32_t lane, uint32_t *lock_status) { 841 phymod_access_t copy; 842 TLB_RX_PRBS_CHK_LOCK_STSr_t chk_lock; 843 844 PHYMOD_MEMCPY(©, pc, sizeof(copy)); 845 copy.lane_mask = lane; 846 READ_TLB_RX_PRBS_CHK_LOCK_STSr(©, &chk_lock); 847 *lock_status = TLB_RX_PRBS_CHK_LOCK_STSr_GET(chk_lock); 848 return PHYMOD_E_NONE; 849 } 850 851 int tfmod_diag_clear_count(PHYMOD_ST *pc, uint32_t lane) { 852 phymod_access_t copy; 853 BCMI_TSCF_XGXS_TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr_t msb; 854 BCMI_TSCF_XGXS_TLB_RX_PRBS_CHK_ERR_CNT_LSB_STSr_t lsb; 855 856 PHYMOD_MEMCPY(©, pc, sizeof(copy)); 857 copy.lane_mask = lane; 858 859 READ_TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr(©, &msb); 860 READ_TLB_RX_PRBS_CHK_ERR_CNT_LSB_STSr(©, &lsb); 861 return PHYMOD_E_NONE; 862 } 863 864 int tfmod_diag_get_count(PHYMOD_ST *pc, uint32_t lane, uint32_t *count) { 865 phymod_access_t copy; 866 BCMI_TSCF_XGXS_TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr_t msb; 867 BCMI_TSCF_XGXS_TLB_RX_PRBS_CHK_ERR_CNT_LSB_STSr_t lsb; 868 uint32_t val; 869 870 PHYMOD_MEMCPY(©, pc, sizeof(copy)); 871 copy.lane_mask = lane; 872 873 READ_TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr(©, &msb); 874 val = TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr_GET(msb); 875 *count = ( val & 0xff) << 16; 876 READ_TLB_RX_PRBS_CHK_ERR_CNT_LSB_STSr(©, &lsb); 877 val = TLB_RX_PRBS_CHK_ERR_CNT_LSB_STSr_GET(lsb); 878 *count |= (val & 0xff); 879 return PHYMOD_E_NONE; 880 }