tefmod_cfg_seq.c (363285B)
1 /*---------------------------------------------------------------------- 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * $Copyright: (c) 2014 Broadcom Corporation All Rights Reserved.$ 8 * Broadcom Corporation 9 * Proprietary and Confidential information 10 * All rights reserved 11 * This source file is the property of Broadcom Corporation, and 12 * may not be copied or distributed in any isomorphic form without the 13 * prior written consent of Broadcom Corporation. 14 *--------------------------------------------------------------------- 15 * File : tefmod_cfg_seq.c 16 * Description: c functions implementing Tier1s for TEFMod Serdes Driver 17 *---------------------------------------------------------------------*/ 18 19 #ifndef _DV_TB_ 20 #define _SDK_TEFMOD_ 1 21 #endif 22 23 #ifdef _DV_TB_ 24 #include <stdint.h> 25 #include "tefmod_main.h" 26 #include "tefmod_defines.h" 27 #include "tfPCSRegEnums.h" 28 #include "tfPMDRegEnums.h" 29 #include "phy_tsc_iblk.h" 30 #include "bcmi_tscf_xgxs_defs.h" 31 #endif /* _DV_TB_ */ 32 33 #ifdef _SDK_TEFMOD_ 34 #include <phymod/phymod.h> 35 #include <phymod/phymod_system.h> 36 #include <phymod/phymod_types.h> 37 #include <phymod/phymod_util.h> 38 #include <phymod/phymod_debug.h> 39 #include <phymod/chip/bcmi_tscf_xgxs_defs.h> 40 #include <phymod/chip/bcmi_tscf_xgxs_gen2_defs.h> 41 #include "tefmod_enum_defines.h" 42 #include "tefmod.h" 43 #include "tefmod_sc_lkup_table.h" 44 #include "tfPCSRegEnums.h" 45 /* #include "tefmod_sc_lkup_table.c" */ 46 #endif /* _SDK_TEFMOD_ */ 47 48 #ifdef _SDK_TEFMOD_ 49 #define PHYMOD_ST const phymod_access_t 50 #else 51 #define PHYMOD_ST tefmod_st 52 #endif 53 54 #define TSCF_GEN1 0x14 55 #define TSCF_GEN2 0x15 56 #define REV_D 0x3 57 #define TEFMOD_CL73_25GBASE_KR1_POS 10 58 #define TEFMOD_CL73_25GBASE_CR1_POS 10 59 #define TEFMOD_CL73_25GBASE_KRS1_POS 9 60 #define TEFMOD_CL73_25GBASE_CRS1_POS 9 61 #define TEFMOD_CL73_25GBASE_FEC_POS 24 62 #define TEFMOD_CL73_25G_RS_FEC_POS 23 63 #define TEFMOD_BAM_CL74_REQ 0x3 64 #define TEFMOD_BAM_CL91_REQ 0x3 65 66 67 #ifdef _SDK_TEFMOD_ 68 #define TEFMOD_DBG_IN_FUNC_INFO(pc) \ 69 PHYMOD_VDBG(TEFMOD_DBG_FUNC,pc,("-22%s: Adr:%08x Ln:%02d\n", __func__, (unsigned int)pc->addr, (int)pc->lane_mask)) 70 #define TEFMOD_DBG_IN_FUNC_VIN_INFO(pc,_print_) \ 71 PHYMOD_VDBG(TEFMOD_DBG_FUNCVALIN,pc,_print_) 72 #define TEFMOD_DBG_IN_FUNC_VOUT_INFO(pc,_print_) \ 73 PHYMOD_VDBG(TEFMOD_DBG_FUNCVALOUT,pc,_print_) 74 #endif 75 76 #ifdef _DV_TB_ 77 #define TEFMOD_DBG_IN_FUNC_INFO(pc) \ 78 PHYMOD_VDBG(TEFMOD_DBG_FUNC, pc, \ 79 ("TEFMOD IN Function : %s Port Add : %d Lane No: %d\n", \ 80 __func__, pc->prt_ad, pc->this_lane)) 81 #define TEFMOD_DBG_IN_FUNC_VIN_INFO(pc,_print_) \ 82 PHYMOD_VDBG(TEFMOD_DBG_FUNCVALIN,pc,_print_) 83 #define TEFMOD_DBG_IN_FUNC_VOUT_INFO(pc,_print_) \ 84 PHYMOD_VDBG(TEFMOD_DBG_FUNCVALOUT,pc,_print_) 85 int phymod_debug_check(uint32_t flags, PHYMOD_ST *pc); 86 #endif 87 88 /*! 89 @brief This function reads TX-PLL PLL_LOCK bit. 90 @param pc handle to current TSCF context (#PHYMOD_ST) 91 @param lockStatus reference which is updated with lock status. 92 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 93 @details Read PLL lock status. Returns 1 or 0 (locked/not) 94 */ 95 96 int tefmod_pll_lock_get(PHYMOD_ST* pc, int* lockStatus) 97 { 98 PMD_X1_STSr_t reg_pmd_x1_sts; 99 TEFMOD_DBG_IN_FUNC_INFO(pc); 100 READ_PMD_X1_STSr(pc, ®_pmd_x1_sts); 101 102 *lockStatus = PMD_X1_STSr_PLL_LOCK_STSf_GET(reg_pmd_x1_sts); 103 /* TEFMOD_DBG_IN_FUNC_VOUT_INFO(pc,("PLL lockStatus: %d", *lockStatus)); */ 104 return PHYMOD_E_NONE; 105 } 106 107 /** 108 @brief This function reads RX-PMD PMD_LOCK bit. 109 @param pc handle to current TSCF context (#PHYMOD_ST) 110 @param lockStatus reference which is updated with pmd_lock status 111 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 112 @details Read PMD lock status Returns 1 or 0 (locked/not) 113 */ 114 #ifdef _DV_TB_ 115 int tefmod_pmd_lock_get(PHYMOD_ST* pc, uint32_t* lockStatus) 116 { 117 PMD_X4_STSr_t reg_pmd_x4_sts; 118 int i; 119 int lane_mask; 120 PHYMOD_ST* pc_copy; 121 TEFMOD_DBG_IN_FUNC_INFO(pc); 122 123 pc_copy = pc; 124 pc_copy->port_type = TEFMOD_MULTI_PORT; 125 lane_mask = 0; 126 switch(pc->port_type) { 127 case TEFMOD_MULTI_PORT: lane_mask = 0x1 << pc->this_lane; break; 128 case TEFMOD_TRI1_PORT: if(pc->this_lane == 3) lane_mask = 0xc; 129 else lane_mask = 0x1 << pc->this_lane; 130 break; 131 case TEFMOD_TRI2_PORT: if(pc->this_lane == 0) lane_mask = 0x3; 132 else lane_mask = 0x1 << pc->this_lane; 133 break; 134 case TEFMOD_DXGXS: if(pc->this_lane == 0) lane_mask = 0x3; 135 else lane_mask = 0xc; 136 break; 137 case TEFMOD_SINGLE_PORT: lane_mask = 0xf; break; 138 default: break; 139 } 140 141 *lockStatus = 0; 142 for(i=0; i<4; i++) { 143 if(((lane_mask >> i) & 0x1) == 1) { 144 pc_copy.this_lane = i; 145 READ_PMD_X4_STSr(pc_copy, ®_pmd_x4_sts); 146 *lockStatus = *lockStatus & PMD_X4_STSr_RX_LOCK_STSf_GET(reg_pmd_x4_sts); 147 } 148 } 149 /* TEFMOD_DBG_IN_FUNC_VOUT_INFO(pc,("PMD lockStatus: %d", *lockStatus)); */ 150 151 return PHYMOD_E_NONE; 152 } 153 154 #endif 155 156 157 #ifdef _SDK_TEFMOD_ 158 int tefmod_pmd_lock_get(PHYMOD_ST* pc, uint32_t* lockStatus) 159 { 160 PMD_X4_STSr_t reg_pmd_x4_sts; 161 int i; 162 phymod_access_t pa_copy; 163 TEFMOD_DBG_IN_FUNC_INFO(pc); 164 165 *lockStatus = 1; 166 PHYMOD_MEMCPY(&pa_copy, pc, sizeof(pa_copy)); 167 168 for(i=0; i<4; i++) { 169 if(((pc->lane_mask >> i) & 0x1) == 1) { 170 pa_copy.lane_mask = 0x1 << i; 171 READ_PMD_X4_STSr(&pa_copy, ®_pmd_x4_sts); 172 *lockStatus = *lockStatus & PMD_X4_STSr_RX_LOCK_STSf_GET(reg_pmd_x4_sts); 173 } 174 } 175 176 /* TEFMOD_DBG_IN_FUNC_VOUT_INFO(pc,("PMD lockStatus: %d", *lockStatus)); */ 177 178 return PHYMOD_E_NONE; 179 } 180 #endif 181 182 /** 183 @brief Init routine sets various operating modes of TSCF. 184 @param pc handle to current TSCF context (#PHYMOD_ST) 185 @param pmd_touched Is this the first time we are visiting the PMD. 186 @param spd_intf Input of enum type #tefmod_spd_intfc_type_t 187 @param pll_mode to override the pll div 188 @returns PHYMOD_E_NONE if successful. PHYMOD_E_FAIL else. 189 @details 190 191 This function is called once per TSCF. It cannot be called multiple times 192 and should be called immediately after reset. Elements of #PHYMOD_ST should be 193 initialized to required values prior to calling this function. The following 194 sub-configurations are performed here. 195 196 \li Set pll divider for VCO setting in PMD. pll divider is calculated from max_speed. 197 */ 198 199 int tefmod_set_pll_mode(PHYMOD_ST* pc, int pmd_touched, tefmod_spd_intfc_type_t spd_intf, int pll_mode) /* SET_PLL_MODE */ 200 { 201 PLL_CAL_CTL7r_t reg_ctl7; 202 int speed; 203 204 TEFMOD_DBG_IN_FUNC_INFO(pc); 205 /* TEFMOD_DBG_IN_FUNC_VIN_INFO(pc,("pmd_touched: %d, spd_intf: %d, pll_mode: %d", pmd_touched, spd_intf, pll_mode)); */ 206 207 PLL_CAL_CTL7r_CLR(reg_ctl7); 208 if (pmd_touched == 0) { 209 tefmod_get_mapped_speed(spd_intf, &speed); 210 /*Support Override PLL DIV */ 211 if(pll_mode & 0x80000000) { 212 PLL_CAL_CTL7r_PLL_MODEf_SET(reg_ctl7, (pll_mode) & 0x0000ffff); 213 } else { 214 PLL_CAL_CTL7r_PLL_MODEf_SET(reg_ctl7, (sc_pmd_entry[speed].pll_mode)); 215 } 216 217 #ifdef _DV_TB_ 218 if( pc->verbosity) { 219 printf("%-22s: plldiv:%d data:%x\n", __func__, pc->plldiv, PLL_CAL_CTL7r_PLL_MODEf_GET(reg_ctl7)); 220 printf("%-22s: main0_setup=%x\n", __func__, PLL_CAL_CTL7r_PLL_MODEf_GET(reg_ctl7)); 221 } 222 #endif 223 PHYMOD_IF_ERR_RETURN (MODIFY_PLL_CAL_CTL7r(pc, reg_ctl7)); 224 } 225 return PHYMOD_E_NONE; 226 227 } /* tefmod_set_pll_mode(PHYMOD_ST* pc) */ 228 229 /*! 230 @brief get port speed id configured 231 @param pc handle to current TSCF context (#PHYMOD_ST) 232 @param speed_id Receives the resolved speed cfg in the speed_id 233 @returns The value PHYMOD_E_NONE upon successful completion. 234 @details get port speed configured 235 */ 236 int tefmod_speed_id_get(PHYMOD_ST* pc, int *speed_id) 237 { 238 SC_X4_RSLVD_SPDr_t sc_final_resolved_speed; 239 240 TEFMOD_DBG_IN_FUNC_INFO(pc); 241 SC_X4_RSLVD_SPDr_CLR(sc_final_resolved_speed); 242 READ_SC_X4_RSLVD_SPDr(pc,&sc_final_resolved_speed); 243 *speed_id = SC_X4_RSLVD_SPDr_SPEEDf_GET(sc_final_resolved_speed); 244 /* get_actual_speed(SC_X4_RSLVD_SPDr_SPEEDf_GET(sc_final_resolved_speed), spd_intf); */ 245 /* TEFMOD_DBG_IN_FUNC_VOUT_INFO(pc,("speed_id: %d", *speed_id)); */ 246 247 return PHYMOD_E_NONE; 248 } 249 250 int tefmod_refclk_set(PHYMOD_ST* pc, phymod_ref_clk_t ref_clock) 251 { 252 DIG_TOP_USER_CTL0r_t dig_top_user_reg; 253 READ_DIG_TOP_USER_CTL0r(pc, &dig_top_user_reg); 254 switch (ref_clock) { 255 case phymodRefClk156Mhz: 256 DIG_TOP_USER_CTL0r_HEARTBEAT_COUNT_1USf_SET(dig_top_user_reg, 0x271); 257 break; 258 case phymodRefClk125Mhz: 259 DIG_TOP_USER_CTL0r_HEARTBEAT_COUNT_1USf_SET(dig_top_user_reg, 0x1f4); 260 break; 261 default: 262 DIG_TOP_USER_CTL0r_HEARTBEAT_COUNT_1USf_SET(dig_top_user_reg, 0x271); 263 break; 264 } 265 MODIFY_DIG_TOP_USER_CTL0r(pc, dig_top_user_reg); 266 return PHYMOD_E_NONE; 267 } 268 269 /** 270 @brief Init the PMD 271 @param pc handle to current TSCF context (#PHYMOD_ST) 272 @param pmd_touched If the PMD is already initialized 273 @returns The value PHYMOD_E_NONE upon successful completion 274 @details Per core PMD resets (both datapath and entire core) 275 We only intend to use this function if the PMD has never been initialized. 276 */ 277 int tefmod_pmd_reset_seq(PHYMOD_ST* pc, int pmd_touched) /* PMD_RESET_SEQ */ 278 { 279 PMD_X1_CTLr_t reg_pmd_x1_ctrl; 280 TEFMOD_DBG_IN_FUNC_INFO(pc); 281 /* TEFMOD_DBG_IN_FUNC_VIN_INFO(pc,("pmd_touched: %x", pmd_touched)); */ 282 283 PMD_X1_CTLr_CLR(reg_pmd_x1_ctrl); 284 285 if (pmd_touched == 0) { 286 PMD_X1_CTLr_POR_H_RSTBf_SET(reg_pmd_x1_ctrl,1); 287 PMD_X1_CTLr_CORE_DP_H_RSTBf_SET(reg_pmd_x1_ctrl,1); 288 PHYMOD_IF_ERR_RETURN(WRITE_PMD_X1_CTLr(pc,reg_pmd_x1_ctrl)); 289 } 290 return PHYMOD_E_NONE; 291 } 292 293 /** 294 @brief Checks config valid status for the port 295 @param pc handle to current TSCF context (#PHYMOD_ST) 296 @param port_num Port Number 297 @returns The value PHYMOD_E_NONE upon successful completion 298 @details This register bit indicates that PCS is now programmed as required by 299 the HT entry for that speed 300 */ 301 int tefmod_master_port_num_set( PHYMOD_ST *pc, int port_num) 302 { 303 MAIN0_SETUPr_t main_reg; 304 /* TEFMOD_DBG_IN_FUNC_VIN_INFO(pc,("port_num: %d", port_num)); */ 305 306 MAIN0_SETUPr_CLR(main_reg); 307 MAIN0_SETUPr_MASTER_PORT_NUMf_SET(main_reg, port_num); 308 MODIFY_MAIN0_SETUPr(pc, main_reg); 309 310 return PHYMOD_E_NONE; 311 } 312 313 /** 314 @brief update the port mode 315 @param pc handle to current TSCF context (#PHYMOD_ST) 316 @param pll_restart Receives info. on whether to restart pll. 317 @returns The value PHYMOD_E_NONE upon successful completion 318 */ 319 int tefmod_update_port_mode( PHYMOD_ST *pc, int *pll_restart) 320 { 321 MAIN0_SETUPr_t mode_reg; 322 int port_mode_sel, port_mode_sel_reg, temp_pll_restart; 323 uint32_t single_port_mode; 324 uint32_t first_couple_mode = 0, second_couple_mode = 0; 325 326 port_mode_sel = 0 ; 327 single_port_mode = 0 ; 328 temp_pll_restart = 0; 329 330 READ_MAIN0_SETUPr(pc, &mode_reg); 331 port_mode_sel_reg = MAIN0_SETUPr_PORT_MODE_SELf_GET(mode_reg); 332 333 /* if(pc->lane == 0xf){ */ 334 if(pc->lane_mask == 0xf){ 335 port_mode_sel = 4; 336 if( port_mode_sel_reg != 4){ 337 temp_pll_restart = 1; 338 } 339 } else{ 340 first_couple_mode = ((port_mode_sel_reg == 2) || (port_mode_sel_reg == 3) || (port_mode_sel_reg == 4)); 341 second_couple_mode = ((port_mode_sel_reg == 1) || (port_mode_sel_reg == 3) || (port_mode_sel_reg == 4)); 342 /* switch(pc->lane){ */ 343 switch(pc->lane_mask){ 344 case 1: 345 case 2: 346 first_couple_mode = 0; 347 break; 348 case 4: 349 case 8: 350 second_couple_mode = 0; 351 break; 352 case 3: 353 first_couple_mode = 1; 354 break; 355 case 0xc: 356 second_couple_mode = 1; 357 break; 358 default: 359 /* dprintf("%-22s: ERROR port_mode_sel=%0d undefined\n", 360 __func__, port_mode_sel_reg); */ 361 break ; 362 } 363 364 if(first_couple_mode ){ 365 port_mode_sel =(second_couple_mode)? 3: 2; 366 } else if(second_couple_mode) { 367 port_mode_sel = 1; 368 } else{ 369 port_mode_sel = 0 ; 370 } 371 } 372 373 *pll_restart = temp_pll_restart; 374 375 /*if(pc->verbosity & TEFMOD_DBG_INIT) 376 dprintf("%-22s u=%0d p=%0d port_mode_sel old=%0d new=%0d\n", __func__, 377 pc->unit, pc->port, port_mode_sel_reg, port_mode_sel) ; */ 378 379 MAIN0_SETUPr_SINGLE_PORT_MODEf_SET(mode_reg, single_port_mode); 380 MAIN0_SETUPr_PORT_MODE_SELf_SET(mode_reg, port_mode_sel); 381 MODIFY_MAIN0_SETUPr(pc, mode_reg); 382 /* TEFMOD_DBG_IN_FUNC_VOUT_INFO(pc,("pll_restart: %d", *pll_restart)); */ 383 return PHYMOD_E_NONE ; 384 } 385 386 /** 387 @brief Enable the pll reset bit 388 @param pc handle to current TSCF context (#PHYMOD_ST) 389 @param enable Controls whether to reset PLL 390 @returns The value PHYMOD_E_NONE upon successful completion 391 @details 392 Resets the PLL 393 */ 394 int tefmod_pll_reset_enable_set (PHYMOD_ST *pc, int enable) 395 { 396 MAIN0_LN_SWPr_t main_reg; 397 398 MAIN0_LN_SWPr_CLR(main_reg); 399 MAIN0_LN_SWPr_PLL_RESET_ENf_SET(main_reg, enable); 400 MODIFY_MAIN0_LN_SWPr(pc, main_reg); 401 return PHYMOD_E_NONE ; 402 } 403 404 /** 405 @brief Read PCS Link status 406 @param pc handle to current TSCF context (#PHYMOD_ST) 407 @param *link Reference for Status of PCS Link 408 @returns The value PHYMOD_E_NONE upon successful completion 409 @details Return the status of the PCS link. The link up implies the PCS is able 410 to decode the digital bits coming in on the serdes. It automatically implies 411 that the PLL is stable and that the PMD sublayer has successfully recovered the 412 clock on the receive line. 413 */ 414 int tefmod_get_pcs_link_status(PHYMOD_ST* pc, uint32_t *link) 415 { 416 RX_X4_PCS_LIVE_STS1r_t reg_pcs_live_sts; 417 418 TEFMOD_DBG_IN_FUNC_INFO(pc); 419 RX_X4_PCS_LIVE_STS1r_CLR(reg_pcs_live_sts); 420 PHYMOD_IF_ERR_RETURN (READ_RX_X4_PCS_LIVE_STS1r(pc, ®_pcs_live_sts)); 421 *link = RX_X4_PCS_LIVE_STS1r_LINK_STATUSf_GET(reg_pcs_live_sts); 422 /* TEFMOD_DBG_IN_FUNC_VOUT_INFO(pc,("pcs_live_stats_link: %d", *link)); */ 423 424 return PHYMOD_E_NONE; 425 } 426 427 int tefmod_get_pcs_latched_link_status(PHYMOD_ST* pc, uint32_t *link) 428 { 429 RX_X4_PCS_LIVE_STS1r_t reg_pcs_live_sts; 430 RX_X4_PCS_LATCH_STS1r_t latched_sts ; 431 int latched_val ; 432 433 TEFMOD_DBG_IN_FUNC_INFO(pc); 434 RX_X4_PCS_LIVE_STS1r_CLR(reg_pcs_live_sts); 435 RX_X4_PCS_LATCH_STS1r_CLR(latched_sts) ; 436 437 PHYMOD_IF_ERR_RETURN (READ_RX_X4_PCS_LIVE_STS1r(pc, ®_pcs_live_sts)); 438 PHYMOD_IF_ERR_RETURN (READ_RX_X4_PCS_LATCH_STS1r(pc, &latched_sts)) ; 439 latched_val = RX_X4_PCS_LATCH_STS1r_LINK_STATUS_LLf_GET(latched_sts) ; 440 if(latched_val) { 441 *link = 0 ; 442 } else { 443 *link = RX_X4_PCS_LIVE_STS1r_LINK_STATUSf_GET(reg_pcs_live_sts); 444 } 445 /* TEFMOD_DBG_IN_FUNC_VOUT_INFO(pc,("pcs_live_stats_link: %d", *link)); */ 446 447 return PHYMOD_E_NONE; 448 } 449 450 /** 451 @brief Get the Port status 452 @param pc handle to current TSCF context (#PHYMOD_ST) 453 @param disabled Receives status on port disabledness 454 @returns The value PHYMOD_E_NONE upon successful completion 455 @details Ports can be disabled in several ways. In this function we simply write 456 0 to the speed change which will bring the PCS down for that lane. 457 458 */ 459 int tefmod_disable_get(PHYMOD_ST* pc, uint32_t* disabled) 460 { 461 SC_X4_CTLr_t reg_sc_ctrl; 462 463 TEFMOD_DBG_IN_FUNC_INFO(pc); 464 SC_X4_CTLr_CLR(reg_sc_ctrl); 465 466 PHYMOD_IF_ERR_RETURN(READ_SC_X4_CTLr(pc,®_sc_ctrl)); 467 *disabled = SC_X4_CTLr_SW_SPEED_CHANGEf_GET(reg_sc_ctrl); 468 469 return PHYMOD_E_NONE; 470 } 471 /** 472 @brief Get info on Disable status of the Port 473 @param pc handle to current TSCF context (#PHYMOD_ST) 474 @returns The value PHYMOD_E_NONE upon successful completion 475 @details Disables the port by writing 0 to the speed config logic in PCS. 476 This makes the PCS to bring down the PCS blocks and also apply lane datapath 477 reset to the PMD. There is no control input to this function since it only does 478 one thing. 479 */ 480 int tefmod_disable_set(PHYMOD_ST* pc) 481 { 482 SC_X4_CTLr_t reg_sc_ctrl; 483 484 TEFMOD_DBG_IN_FUNC_INFO(pc); 485 SC_X4_CTLr_CLR(reg_sc_ctrl); 486 READ_SC_X4_CTLr(pc, ®_sc_ctrl); 487 488 /* write 0 to the speed change */ 489 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(reg_sc_ctrl, 0); 490 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_CTLr(pc,reg_sc_ctrl)); 491 492 return PHYMOD_E_NONE; 493 } 494 495 int tefmod_enable_set(PHYMOD_ST* pc) 496 { 497 SC_X4_CTLr_t reg_sc_ctrl; 498 499 TEFMOD_DBG_IN_FUNC_INFO(pc); 500 SC_X4_CTLr_CLR(reg_sc_ctrl); 501 READ_SC_X4_CTLr(pc, ®_sc_ctrl); 502 503 /* write 0 to the speed change */ 504 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(reg_sc_ctrl, 1); 505 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_CTLr(pc,reg_sc_ctrl)); 506 507 return PHYMOD_E_NONE; 508 } 509 510 511 /** 512 @brief Get the plldiv from lookup table 513 @param pc handle to current TSCF context (#PHYMOD_ST) 514 @param spd_intf Input of enum type #tefmod_spd_intfc_type_t 515 @param plldiv Receives PLL Divider value 516 @returns The value PHYMOD_E_NONE upon successful completion 517 @details Get the plldiv from lookup table as a function of the speed. 518 */ 519 520 int tefmod_plldiv_lkup_get(PHYMOD_ST* pc, tefmod_spd_intfc_type_t spd_intf, phymod_ref_clk_t refclk, uint32_t *plldiv) 521 { 522 int speed_id; 523 524 TEFMOD_DBG_IN_FUNC_INFO(pc); 525 tefmod_get_mapped_speed(spd_intf, &speed_id); 526 if (refclk == phymodRefClk125Mhz) { 527 *plldiv = sc_pmd_entry_125M_ref[speed_id].pll_mode; 528 } else { 529 *plldiv = sc_pmd_entry[speed_id].pll_mode; 530 } 531 /* TEFMOD_DBG_IN_FUNC_VOUT_INFO(pc,("plldiv: %d", *plldiv)); */ 532 533 return PHYMOD_E_NONE; 534 535 } 536 537 /** 538 @brief Get the osmode from lookup table 539 @param pc handle to current TSCF context (#PHYMOD_ST) 540 @param spd_intf Input of enum type #tefmod_spd_intfc_type_t 541 @param osmode Receives the OS mode as assumed in the hard table. 542 @returns The value PHYMOD_E_NONE upon successful completion 543 @details Get the osmode from software version of Speed table as a function of 544 the speed 545 */ 546 int tefmod_osmode_lkup_get(PHYMOD_ST* pc, tefmod_spd_intfc_type_t spd_intf, uint32_t *osmode) 547 { 548 int speed_id; 549 550 TEFMOD_DBG_IN_FUNC_INFO(pc); 551 tefmod_get_mapped_speed(spd_intf, &speed_id); 552 *osmode = sc_pmd_entry[speed_id].t_pma_os_mode; 553 554 return PHYMOD_E_NONE; 555 } 556 557 /** 558 @brief sets both the RX and TX lane swap values for all lanes simultaneously. 559 @param pc handle to current TSCF context (#PHYMOD_ST) 560 @param tx_rx_swap Receives the PCS lane swap value 561 @returns The value PHYMOD_E_NONE upon successful completion 562 @details 563 This function gets the TX lane swap values for all lanes simultaneously. 564 */ 565 566 int tefmod_pcs_lane_swap_get ( PHYMOD_ST *pc, uint32_t *tx_rx_swap) 567 { 568 unsigned int pcs_map; 569 MAIN0_LN_SWPr_t reg; 570 RX_X1_RX_LN_SWP_GEN2r_t rx_lane_map_r; 571 MAIN0_SERDESIDr_t serdesid; 572 uint32_t model; 573 574 TEFMOD_DBG_IN_FUNC_INFO(pc); 575 576 READ_MAIN0_SERDESIDr(pc, &serdesid); 577 model = MAIN0_SERDESIDr_MODEL_NUMBERf_GET(serdesid); 578 579 if (model == TSCF_GEN2) { 580 /* tx and rx lane map are the same */ 581 RX_X1_RX_LN_SWP_GEN2r_CLR(rx_lane_map_r); 582 583 PHYMOD_IF_ERR_RETURN(READ_RX_X1_RX_LN_SWP_GEN2r(pc, &rx_lane_map_r)); 584 585 pcs_map = RX_X1_RX_LN_SWP_GEN2r_GET(rx_lane_map_r); 586 } else { 587 MAIN0_LN_SWPr_CLR(reg); 588 589 PHYMOD_IF_ERR_RETURN 590 (READ_MAIN0_LN_SWPr(pc, ®)) ; 591 592 pcs_map = MAIN0_LN_SWPr_GET(reg); 593 } 594 595 *tx_rx_swap = (((pcs_map >> 0) & 0x3) << 0) | 596 (((pcs_map >> 2) & 0x3) << 4) | 597 (((pcs_map >> 4) & 0x3) << 8) | 598 (((pcs_map >> 6) & 0x3) << 12) ; 599 600 return PHYMOD_E_NONE ; 601 } 602 603 /** 604 @brief Gets PMD TX lane swap values for all lanes simultaneously. 605 @param pc handle to current TSCF context (#PHYMOD_ST) 606 @param tx_lane_map returns the pmd tx lane map 607 @returns The value PHYMOD_E_NONE upon successful completion 608 @details 609 This function gets the TX lane swap values for all lanes simultaneously. 610 611 */ 612 int tefmod_pmd_lane_swap_tx_get ( PHYMOD_ST *pc, uint32_t *tx_lane_map) 613 { 614 uint16_t tx_lane_map_0, tx_lane_map_1, tx_lane_map_2, tx_lane_map_3; 615 DIG_TX_LN_MAP_0_1_2r_t reg; 616 DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r_t reg1; 617 618 TEFMOD_DBG_IN_FUNC_INFO(pc); 619 DIG_TX_LN_MAP_0_1_2r_CLR(reg); 620 DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r_CLR(reg1); 621 622 PHYMOD_IF_ERR_RETURN 623 (READ_DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r(pc, ®1)); 624 PHYMOD_IF_ERR_RETURN 625 (READ_DIG_TX_LN_MAP_0_1_2r(pc, ®)); 626 627 tx_lane_map_0 = DIG_TX_LN_MAP_0_1_2r_TX_LANE_MAP_0f_GET(reg); 628 tx_lane_map_1 = DIG_TX_LN_MAP_0_1_2r_TX_LANE_MAP_1f_GET(reg); 629 tx_lane_map_2 = DIG_TX_LN_MAP_0_1_2r_TX_LANE_MAP_2f_GET(reg); 630 tx_lane_map_3 = DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r_TX_LANE_MAP_3f_GET(reg1); 631 632 *tx_lane_map = ((tx_lane_map_0 & 0xf) << 0) 633 | ((tx_lane_map_1 & 0xf) << 4) 634 | ((tx_lane_map_2 & 0xf) << 8) 635 | ((tx_lane_map_3 & 0xf) << 12); 636 637 return PHYMOD_E_NONE ; 638 } 639 640 /** 641 @brief rx lane reset and enable of any particular lane 642 @param pc handle to current TSCF context (#PHYMOD_ST) 643 @param enable to reset the lane. 644 @returns The value PHYMOD_E_NONE upon successful completion. 645 @details 646 This function enables/disables rx lane (RSTB_LANE) or read back control bit for 647 that based on per_lane_control being 1 or 0. If per_lane_control is 0xa, only 648 read back RSTB_LANE. 649 */ 650 int tefmod_rx_lane_control_set(PHYMOD_ST* pc, int enable) /* RX_LANE_CONTROL */ 651 { 652 RX_X4_PMA_CTL0r_t reg_pma_ctrl; 653 654 TEFMOD_DBG_IN_FUNC_INFO(pc); 655 RX_X4_PMA_CTL0r_CLR(reg_pma_ctrl); 656 if (enable) { 657 RX_X4_PMA_CTL0r_RSTB_LANEf_SET( reg_pma_ctrl, 0); 658 PHYMOD_IF_ERR_RETURN (MODIFY_RX_X4_PMA_CTL0r(pc, reg_pma_ctrl)); 659 RX_X4_PMA_CTL0r_RSTB_LANEf_SET(reg_pma_ctrl, 1); 660 PHYMOD_IF_ERR_RETURN (MODIFY_RX_X4_PMA_CTL0r(pc, reg_pma_ctrl)); 661 } else { 662 /* bit set to 0 for disabling RXP */ 663 RX_X4_PMA_CTL0r_RSTB_LANEf_SET( reg_pma_ctrl, 0); 664 PHYMOD_IF_ERR_RETURN (MODIFY_RX_X4_PMA_CTL0r(pc, reg_pma_ctrl)); 665 } 666 return PHYMOD_E_NONE; 667 } 668 669 /** 670 @brief rx lane reset and enable of any particular lane 671 @param pc handle to current TSCF context (#PHYMOD_ST) 672 @param enable Handle to get the configured reset lane. 673 @returns The value PHYMOD_E_NONE upon successful completion. 674 @details 675 This function read back control bit 676 */ 677 int tefmod_rx_lane_control_get(PHYMOD_ST* pc, int *enable) /* RX_LANE_CONTROL */ 678 { 679 RX_X4_PMA_CTL0r_t reg_pma_ctrl; 680 681 TEFMOD_DBG_IN_FUNC_INFO(pc); 682 RX_X4_PMA_CTL0r_CLR(reg_pma_ctrl); 683 PHYMOD_IF_ERR_RETURN (READ_RX_X4_PMA_CTL0r(pc, ®_pma_ctrl)); 684 *enable = RX_X4_PMA_CTL0r_RSTB_LANEf_GET( reg_pma_ctrl); 685 686 return PHYMOD_E_NONE; 687 } 688 689 690 691 /** 692 @brief Gets the TX And RX Polarity 693 @param pc handle to current TSCF context (#PHYMOD_ST) 694 @param tx_polarity Receives the TX polarity 695 @param rx_polarity Receives the RX polarity 696 @returns The value PHYMOD_E_NONE upon successful completion. 697 @details Gets the TX And RX Polarity from hardware. 698 699 */ 700 int tefmod_tx_rx_polarity_get ( PHYMOD_ST *pc, uint32_t* tx_polarity, uint32_t* rx_polarity) 701 { 702 TLB_TX_MISC_CFGr_t tx_pol_inv; 703 TLB_RX_MISC_CFGr_t rx_pol_inv; 704 705 PHYMOD_IF_ERR_RETURN(READ_TLB_TX_MISC_CFGr(pc, &tx_pol_inv)); 706 *tx_polarity = TLB_TX_MISC_CFGr_TX_PMD_DP_INVERTf_GET(tx_pol_inv); 707 708 PHYMOD_IF_ERR_RETURN(READ_TLB_RX_MISC_CFGr(pc, &rx_pol_inv)); 709 *rx_polarity = TLB_RX_MISC_CFGr_RX_PMD_DP_INVERTf_GET(rx_pol_inv); 710 711 return PHYMOD_E_NONE; 712 } 713 714 /** 715 @brief Sets the TX And RX Polarity 716 @param pc handle to current TSCF context (#PHYMOD_ST) 717 @param tx_polarity Controls the TX polarity 718 @param rx_polarity Controls the RX polarity 719 @returns The value PHYMOD_E_NONE upon successful completion. 720 @details Sets the TX And RX Polarity 721 */ 722 int tefmod_tx_rx_polarity_set ( PHYMOD_ST *pc, uint32_t tx_polarity, uint32_t rx_polarity) 723 { 724 TLB_TX_MISC_CFGr_t tx_pol_inv; 725 TLB_RX_MISC_CFGr_t rx_pol_inv; 726 727 TLB_TX_MISC_CFGr_CLR(tx_pol_inv); 728 TLB_RX_MISC_CFGr_CLR(rx_pol_inv); 729 730 TLB_TX_MISC_CFGr_TX_PMD_DP_INVERTf_SET(tx_pol_inv, tx_polarity); 731 PHYMOD_IF_ERR_RETURN(MODIFY_TLB_TX_MISC_CFGr(pc, tx_pol_inv)); 732 733 TLB_RX_MISC_CFGr_RX_PMD_DP_INVERTf_SET(rx_pol_inv, rx_polarity); 734 PHYMOD_IF_ERR_RETURN(MODIFY_TLB_RX_MISC_CFGr(pc, rx_pol_inv)); 735 736 return PHYMOD_E_NONE; 737 } 738 739 /** 740 @brief Read the 16 bit rev. id value etc. 741 @param pc handle to current TSCF context (#PHYMOD_ST) 742 @returns The value PHYMOD_E_NONE upon successful completion 743 @details Per Port PCS Init 744 */ 745 746 int tefmod_trigger_speed_change(PHYMOD_ST* pc) 747 { 748 SC_X4_CTLr_t reg; 749 750 TEFMOD_DBG_IN_FUNC_INFO(pc); 751 752 /* write 0 to the speed change */ 753 SC_X4_CTLr_CLR(reg); 754 PHYMOD_IF_ERR_RETURN(READ_SC_X4_CTLr(pc, ®)); 755 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(reg, 0); 756 PHYMOD_IF_ERR_RETURN(WRITE_SC_X4_CTLr(pc, reg)); 757 758 /* write 1 to the speed change. No need to read again before write*/ 759 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(reg, 1); 760 PHYMOD_IF_ERR_RETURN(WRITE_SC_X4_CTLr(pc, reg)); 761 762 return PHYMOD_E_NONE; 763 } 764 765 /*! 766 @brief Squelch TX lane output. 767 @param pc handle to current TSCF context (#PHYMOD_ST) 768 @param tx control lanes to disable 769 @returns PHYMOD_E_NONE if no errors. PHYMOD_EERROR else. 770 @details This function disables transmission on a specific lane. No reset is 771 required to restart the transmission. Lane control is done through 'tx' input. 772 Set bits 0, 8, 16, or 24 to <B>0 to disable TX on lanes 0/1/2/3</B> 773 Set the bits to <B>1 to enable TX</B> 774 */ 775 776 int tefmod_tx_lane_disable (PHYMOD_ST* pc, int tx) 777 { 778 PMD_X4_CTLr_t PMD_X4_PMD_X4_CONTROLr_reg; 779 780 TEFMOD_DBG_IN_FUNC_INFO(pc); 781 PMD_X4_CTLr_CLR(PMD_X4_PMD_X4_CONTROLr_reg); 782 783 PMD_X4_CTLr_TX_DISABLEf_SET(PMD_X4_PMD_X4_CONTROLr_reg, tx); 784 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X4_CTLr(pc, PMD_X4_PMD_X4_CONTROLr_reg)); 785 return PHYMOD_E_NONE; 786 } 787 788 /** 789 @brief Select the ILKN path and bypass TSCF PCS 790 @param pc handle to current TSCF context (#PHYMOD_ST) 791 @returns The value PHYMOD_E_NONE upon successful completion 792 @details This will enable ILKN path. PCS is set to bypass to relinquish PMD 793 control. Expect PMD to be programmed elsewhere. 794 */ 795 int tefmod_pcs_ilkn_mode_set(PHYMOD_ST* pc) /* INIT_PCS_ILKN */ 796 { 797 SC_X4_BYPASSr_t reg_sc_bypass; 798 799 TEFMOD_DBG_IN_FUNC_INFO(pc); 800 SC_X4_BYPASSr_CLR(reg_sc_bypass); 801 SC_X4_BYPASSr_SC_BYPASSf_SET(reg_sc_bypass, 1); 802 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_BYPASSr(pc,reg_sc_bypass)); 803 804 return PHYMOD_E_NONE; 805 } 806 807 808 /** 809 @brief Select the ILKN path and bypass TSCF PCS 810 @param pc handle to current TSCF context (#PHYMOD_ST) 811 @returns The value PHYMOD_E_NONE upon successful completion 812 @details This will enable ILKN path. PCS is set to bypass to relinquish PMD 813 control. Expect PMD to be programmed elsewhere. 814 */ 815 int tefmod_init_pcs_ilkn(PHYMOD_ST* pc) /* INIT_PCS_ILKN */ 816 { 817 818 ILKN_CTL0r_t ILKN_CONTROL0r_reg; 819 MAIN0_SERDESIDr_t serdesid; 820 uint32_t model; 821 822 /* next check serdes ID to see if gen2 or not */ 823 READ_MAIN0_SERDESIDr(pc, &serdesid); 824 model = MAIN0_SERDESIDr_MODEL_NUMBERf_GET(serdesid); 825 826 /* check if tscf_gen2 version */ 827 if (model == TSCF_GEN2) { 828 ILKN_CTL0_GEN2r_t ILKN_CTL0_GEN2r_reg; 829 READ_ILKN_CTL0_GEN2r(pc, & ILKN_CTL0_GEN2r_reg); 830 ILKN_CTL0_GEN2r_ILKN_SELf_SET(ILKN_CTL0_GEN2r_reg, 1); 831 ILKN_CTL0_GEN2r_CREDIT_ENf_SET(ILKN_CTL0_GEN2r_reg, 1); 832 MODIFY_ILKN_CTL0_GEN2r(pc, ILKN_CTL0_GEN2r_reg); 833 834 } else { 835 PHYMOD_IF_ERR_RETURN(READ_ILKN_CTL0r(pc, &ILKN_CONTROL0r_reg)); 836 ILKN_CTL0r_CREDIT_ENf_SET(ILKN_CONTROL0r_reg, 1); 837 ILKN_CTL0r_ILKN_SELf_SET(ILKN_CONTROL0r_reg, 1); 838 PHYMOD_IF_ERR_RETURN(MODIFY_ILKN_CTL0r(pc, ILKN_CONTROL0r_reg)); 839 } 840 841 return PHYMOD_E_NONE; 842 } 843 844 /** 845 @brief Check if ILKN is set 846 @param pc handle to current TSCF context (#PHYMOD_ST), ilkn_set status 847 @returns The value PHYMOD_E_NONE upon successful completion 848 @details Check if ILKN is set, ilkn_set = 1 if it is set. 849 */ 850 int tefmod_pcs_ilkn_chk(PHYMOD_ST* pc, int *ilkn_set) /* INIT_PCS_ILKN */ 851 { 852 ILKN_CTL0r_t ILKN_CONTROL0r_reg; 853 MAIN0_SERDESIDr_t serdesid; 854 uint32_t model; 855 856 TEFMOD_DBG_IN_FUNC_INFO(pc); 857 858 /* next check serdes ID to see if gen2 or not */ 859 PHYMOD_IF_ERR_RETURN(READ_MAIN0_SERDESIDr(pc, &serdesid)); 860 model = MAIN0_SERDESIDr_MODEL_NUMBERf_GET(serdesid); 861 862 /* check if tscf_gen2 version */ 863 if (model == TSCF_GEN2) { 864 ILKN_CTL0_GEN2r_t ILKN_CTL0_GEN2r_reg; 865 PHYMOD_IF_ERR_RETURN(READ_ILKN_CTL0_GEN2r(pc, &ILKN_CTL0_GEN2r_reg)); 866 *ilkn_set = ILKN_CTL0_GEN2r_ILKN_SELf_GET(ILKN_CTL0_GEN2r_reg); 867 } else { 868 PHYMOD_IF_ERR_RETURN(READ_ILKN_CTL0r(pc, &ILKN_CONTROL0r_reg)); 869 *ilkn_set = ILKN_CTL0r_ILKN_SELf_GET(ILKN_CONTROL0r_reg); 870 } 871 872 return PHYMOD_E_NONE; 873 } 874 875 #ifdef _DV_TB_ 876 /*! 877 @brief Controls PMD reset pins irrespective of PCS is in Speed Control mode or not 878 aram pc handle to current TSCF context (#PHYMOD_ST) 879 @returns PHYMOD_E_NONE if no errors. PHYMOD_EERROR else. 880 @details Set the ::PHYMOD_ST::per_lane_control field of #PHYMOD_ST to <B>0 to 881 disable</B> PCS <B>1 to enable</B>. 882 */ 883 884 /* Ensure that tier2 and phymod control exist to access this function */ 885 int tefmod_pmd_reset_bypass (PHYMOD_ST* pc, int pmd_reset_control) /* PMD_RESET_BYPASS */ 886 { 887 int cntl; 888 PMD_X4_OVRRr_t PMD_X4_OVERRIDEr_reg; 889 PMD_X4_CTLr_t PMD_X4_PMD_X4_CONTROLr_reg; 890 PMD_X1_OVRRr_t PMD_X1_OVERRIDEr_reg; 891 PMD_X1_CTLr_t PMD_X1_PMD_X1_CONTROLr_reg; 892 SC_X4_CTLr_t SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg; 893 894 TEFMOD_DBG_IN_FUNC_INFO(pc); 895 cntl = pmd_reset_control & 0x10; 896 if (cntl) { 897 PMD_X4_OVRRr_CLR(PMD_X4_OVERRIDEr_reg); 898 PMD_X4_OVRRr_LN_DP_H_RSTB_OENf_SET(PMD_X4_OVERRIDEr_reg, 1); 899 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X4_OVRRr(pc, PMD_X4_OVERRIDEr_reg)); 900 901 PMD_X4_CTLr_CLR(PMD_X4_PMD_X4_CONTROLr_reg); 902 PMD_X4_CTLr_LN_DP_H_RSTBf_SET(PMD_X4_PMD_X4_CONTROLr_reg,0); 903 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X4_CTLr(pc, PMD_X4_PMD_X4_CONTROLr_reg)); 904 905 /* toggle added */ 906 PMD_X4_CTLr_CLR(PMD_X4_PMD_X4_CONTROLr_reg); 907 PMD_X4_CTLr_LN_DP_H_RSTBf_SET(PMD_X4_PMD_X4_CONTROLr_reg,1); 908 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X4_CTLr(pc, PMD_X4_PMD_X4_CONTROLr_reg)); 909 910 PMD_X4_OVRRr_CLR(PMD_X4_OVERRIDEr_reg); 911 PMD_X4_OVRRr_LN_DP_H_RSTB_OENf_SET(PMD_X4_OVERRIDEr_reg,0); 912 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X4_OVRRr(pc, PMD_X4_OVERRIDEr_reg)); 913 } else { 914 PMD_X4_OVRRr_CLR(PMD_X4_OVERRIDEr_reg); 915 PMD_X4_OVRRr_LN_DP_H_RSTB_OENf_SET(PMD_X4_OVERRIDEr_reg,0); 916 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X4_OVRRr(pc, PMD_X4_OVERRIDEr_reg)); 917 918 PMD_X4_CTLr_CLR(PMD_X4_PMD_X4_CONTROLr_reg); 919 PMD_X4_CTLr_LN_DP_H_RSTBf_SET(PMD_X4_PMD_X4_CONTROLr_reg,1); 920 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X4_CTLr(pc, PMD_X4_PMD_X4_CONTROLr_reg)); 921 } 922 923 924 cntl = pmd_reset_control & 0x1; 925 if (cntl) { 926 927 PMD_X1_OVRRr_CLR(PMD_X1_OVERRIDEr_reg); 928 PMD_X1_OVRRr_CORE_DP_H_RSTB_OENf_SET(PMD_X1_OVERRIDEr_reg,1); 929 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X1_OVRRr(pc, PMD_X1_OVERRIDEr_reg)); 930 931 PMD_X1_CTLr_CLR(PMD_X1_PMD_X1_CONTROLr_reg); 932 PMD_X1_CTLr_CORE_DP_H_RSTBf_SET(PMD_X1_PMD_X1_CONTROLr_reg,0); 933 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X1_CTLr(pc, PMD_X1_PMD_X1_CONTROLr_reg)); 934 935 /* toggle added */ 936 PMD_X1_CTLr_CLR(PMD_X1_PMD_X1_CONTROLr_reg); 937 PMD_X1_CTLr_CORE_DP_H_RSTBf_SET(PMD_X1_PMD_X1_CONTROLr_reg,1); 938 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X1_CTLr(pc, PMD_X1_PMD_X1_CONTROLr_reg)); 939 940 PMD_X1_OVRRr_CLR(PMD_X1_OVERRIDEr_reg); 941 PMD_X1_OVRRr_CORE_DP_H_RSTB_OENf_SET(PMD_X1_OVERRIDEr_reg,0); 942 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X1_OVRRr(pc, PMD_X1_OVERRIDEr_reg)); 943 } else { 944 PMD_X1_OVRRr_CLR(PMD_X1_OVERRIDEr_reg); 945 PMD_X1_OVRRr_CORE_DP_H_RSTB_OENf_SET(PMD_X1_OVERRIDEr_reg,0); 946 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X1_OVRRr(pc, PMD_X1_OVERRIDEr_reg)); 947 948 PMD_X1_CTLr_CLR(PMD_X1_PMD_X1_CONTROLr_reg); 949 PMD_X1_CTLr_CORE_DP_H_RSTBf_SET(PMD_X1_PMD_X1_CONTROLr_reg,1); 950 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X1_CTLr(pc, PMD_X1_PMD_X1_CONTROLr_reg)); 951 } 952 953 SC_X4_CTLr_CLR(SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg); 954 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg,0); 955 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_CTLr(pc, SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg)); 956 957 SC_X4_CTLr_CLR(SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg); 958 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg,1); 959 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_CTLr(pc, SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg)); 960 961 return PHYMOD_E_NONE; 962 } /* PMD_RESET_BYPASS */ 963 #endif 964 965 /*! 966 @brief Controls the setting/resetting of autoneg advertisement registers. 967 @param pc handle to current TSCF context (#PHYMOD_ST) 968 @param cl73_adv struct of type #tefmod_an_adv_ability_t 969 @returns PHYMOD_E_NONE if no errors. PHYMOD_EERROR else. 970 @details 971 TBD 972 */ 973 974 #ifdef _DV_TB_ 975 int tefmod_autoneg_set(PHYMOD_ST* pc) /* AUTONEG_SET */ 976 { 977 uint16_t data, mask; 978 uint16_t cl73_bam_code; 979 /* uint16_t tx_nonce; */ 980 AN_X1_OUI_LWRr_t AN_X1_CONTROL_OUI_LOWERr_reg; 981 AN_X1_OUI_UPRr_t AN_X1_CONTROL_OUI_UPPERr_reg; 982 AN_X4_CL73_CTLSr_t AN_X4_ABILITIES_CL73_CONTROLSr_reg; 983 AN_X4_LD_BAM_ABILr_t AN_X4_ABILITIES_LD_BAM_ABILITIESr_reg; 984 AN_X4_LD_BASE_ABIL1r_t AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg; 985 AN_X4_LD_BASE_ABIL0r_t AN_X4_ABILITIES_LD_BASE_ABILITIES_0r_reg; 986 AN_X4_LD_UP1_ABIL0r_t AN_X4_ABILITIES_LD_UP1_ABILITIES_0r_reg; 987 AN_X4_LD_UP1_ABIL1r_t AN_X4_ABILITIES_LD_UP1_ABILITIES_1r_reg; 988 989 AN_X1_BAM_SPD_PRI0r_t AN_X1_CONTROL_BAM_SPEED_PRI_0r_reg; 990 AN_X1_BAM_SPD_PRI1r_t AN_X1_CONTROL_BAM_SPEED_PRI_1r_reg; 991 AN_X1_BAM_SPD_PRI2r_t AN_X1_CONTROL_BAM_SPEED_PRI_2r_reg; 992 AN_X1_BAM_SPD_PRI3r_t AN_X1_CONTROL_BAM_SPEED_PRI_3r_reg; 993 AN_X1_BAM_SPD_PRI4r_t AN_X1_CONTROL_BAM_SPEED_PRI_4r_reg; 994 995 996 TEFMOD_DBG_IN_FUNC_INFO(pc); 997 AN_X1_OUI_LWRr_CLR(AN_X1_CONTROL_OUI_LOWERr_reg); 998 AN_X1_OUI_LWRr_SET(AN_X1_CONTROL_OUI_LOWERr_reg, pc->oui & 0xffff); 999 /********Setting AN_X1_OUI_LWR 0x9241*****/ 1000 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_OUI_LWRr(pc, AN_X1_CONTROL_OUI_LOWERr_reg)); 1001 1002 AN_X1_OUI_UPRr_CLR(AN_X1_CONTROL_OUI_UPPERr_reg); 1003 AN_X1_OUI_UPRr_SET(AN_X1_CONTROL_OUI_UPPERr_reg, (pc->oui >> 16) & 0xffff); 1004 /********Setting AN_X1_OUI_UPR 0x9240*****/ 1005 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_OUI_UPRr(pc, AN_X1_CONTROL_OUI_UPPERr_reg)); 1006 1007 1008 /***********Override programming ********/ 1009 AN_X4_CL73_CTLSr_CLR(AN_X4_ABILITIES_CL73_CONTROLSr_reg); 1010 data = pc->an_misc_ctrls; 1011 AN_X4_CL73_CTLSr_SET(AN_X4_ABILITIES_CL73_CONTROLSr_reg, data); 1012 /********Setting AN_X4_ABILITIES_cl73_controls 0xC186*****/ 1013 PHYMOD_IF_ERR_RETURN(WRITE_AN_X4_CL73_CTLSr(pc, AN_X4_ABILITIES_CL73_CONTROLSr_reg)); 1014 1015 1016 /********BAM Code********/ 1017 if(pc->an_type == TEFMOD_CL73_BAM || pc->an_type == TEFMOD_HPAM) 1018 cl73_bam_code =3; 1019 else 1020 cl73_bam_code =0; 1021 1022 AN_X4_LD_BAM_ABILr_CLR(AN_X4_ABILITIES_LD_BAM_ABILITIESr_reg); 1023 AN_X4_LD_BAM_ABILr_CL73_BAM_CODEf_SET(AN_X4_ABILITIES_LD_BAM_ABILITIESr_reg, cl73_bam_code); 1024 /********Setting AN_X4_ABILITIES_ld_bam_abilities 0xC185*****/ 1025 PHYMOD_IF_ERR_RETURN(WRITE_AN_X4_LD_BAM_ABILr(pc, AN_X4_ABILITIES_LD_BAM_ABILITIESr_reg)); 1026 1027 1028 data=0; 1029 mask=0; 1030 AN_X4_LD_BASE_ABIL1r_CLR(AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg); 1031 1032 /******* Base Abilities*****/ 1033 if( (pc->an_tech_ability >> TEFMOD_ABILITY_1G ) & 1 ) { 1034 AN_X4_LD_BASE_ABIL1r_BASE_1G_KX1f_SET(AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg, 1); 1035 } 1036 if( (pc->an_tech_ability >> TEFMOD_ABILITY_10G_KR ) & 1 ) { 1037 AN_X4_LD_BASE_ABIL1r_BASE_10G_KR1f_SET(AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg, 1); 1038 } 1039 if( (pc->an_tech_ability >> TEFMOD_ABILITY_40G_KR4 ) & 1 ) { 1040 AN_X4_LD_BASE_ABIL1r_BASE_40G_KR4f_SET(AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg, 1); 1041 } 1042 if( (pc->an_tech_ability >> TEFMOD_ABILITY_40G_CR4 ) & 1 ) { 1043 AN_X4_LD_BASE_ABIL1r_BASE_40G_CR4f_SET(AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg, 1); 1044 } 1045 if( (pc->an_tech_ability >> TEFMOD_ABILITY_100G_KR4 ) & 1 ) { 1046 AN_X4_LD_BASE_ABIL1r_BASE_100G_KR4f_SET(AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg, 1); 1047 } 1048 if( (pc->an_tech_ability >> TEFMOD_ABILITY_100G_CR4 ) & 1 ) { 1049 AN_X4_LD_BASE_ABIL1r_BASE_100G_CR4f_SET(AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg, 1); 1050 } 1051 1052 /******* Pause Settings ********/ 1053 if(pc->an_pause == TEFMOD_NO_PAUSE) 1054 AN_X4_LD_BASE_ABIL1r_CL73_PAUSEf_SET(AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg, 0); 1055 if(pc->an_pause == TEFMOD_SYMM_PAUSE) 1056 AN_X4_LD_BASE_ABIL1r_CL73_PAUSEf_SET(AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg, 1); 1057 if(pc->an_pause == TEFMOD_ASYM_PAUSE) 1058 AN_X4_LD_BASE_ABIL1r_CL73_PAUSEf_SET(AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg, 2); 1059 if(pc->an_pause == TEFMOD_ASYM_SYMM_PAUSE) 1060 AN_X4_LD_BASE_ABIL1r_CL73_PAUSEf_SET(AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg, 3); 1061 1062 /****** FEC Settings ********/ 1063 if(pc->an_fec == TEFMOD_FEC_NOT_SUPRTD) 1064 AN_X4_LD_BASE_ABIL1r_FEC_REQf_SET(AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg, 0); 1065 if(pc->an_fec == TEFMOD_FEC_SUPRTD_NOT_REQSTD) { 1066 AN_X4_LD_BASE_ABIL1r_FEC_REQf_SET(AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg, 1); 1067 } 1068 if(pc->an_fec == TEFMOD_FEC_CL74_SUPRTD_REQSTD) { 1069 AN_X4_LD_BASE_ABIL1r_FEC_REQf_SET(AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg, 3); 1070 } 1071 1072 /****** Next page ******/ 1073 if(pc->cl73_bam_enable || pc->cl73_hpam_enable) 1074 AN_X4_LD_BASE_ABIL1r_NEXT_PAGEf_SET(AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg, 1); 1075 1076 1077 if(pc->an_rf == 1) { 1078 AN_X4_LD_BASE_ABIL1r_CL73_REMOTE_FAULTf_SET(AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg, 1); 1079 } 1080 1081 /***** Setting AN_X4_ABILITIES_ld_base_abilities_1 0xC184 *******/ 1082 PHYMOD_IF_ERR_RETURN(WRITE_AN_X4_LD_BASE_ABIL1r(pc, AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg)); 1083 1084 1085 data =0; 1086 mask =0; 1087 1088 AN_X4_LD_BASE_ABIL0r_CLR(AN_X4_ABILITIES_LD_BASE_ABILITIES_0r_reg); 1089 /******tx nonce*****/ 1090 AN_X4_LD_BASE_ABIL0r_TX_NONCEf_SET(AN_X4_ABILITIES_LD_BASE_ABILITIES_0r_reg, pc->cl73_tx_nonce); 1091 1092 /****** Base selector *****/ 1093 AN_X4_LD_BASE_ABIL0r_CL73_BASE_SELECTORf_SET(AN_X4_ABILITIES_LD_BASE_ABILITIES_0r_reg, 1); 1094 1095 /***** Setting AN_X4_ABILITIES_ld_base_abilities_0 0xC183 *******/ 1096 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_LD_BASE_ABIL0r(pc, AN_X4_ABILITIES_LD_BASE_ABILITIES_0r_reg)); 1097 1098 data =0; 1099 AN_X4_LD_UP1_ABIL0r_CLR(AN_X4_ABILITIES_LD_UP1_ABILITIES_0r_reg); 1100 /******* User page abilities*********/ 1101 if( (pc->an_tech_ability >> TEFMOD_ABILITY_20G_KR2) & 1 ) 1102 AN_X4_LD_UP1_ABIL0r_BAM_20G_KR2f_SET(AN_X4_ABILITIES_LD_UP1_ABILITIES_0r_reg, 1); 1103 if( (pc->an_tech_ability >> TEFMOD_ABILITY_20G_CR2) & 1 ) 1104 AN_X4_LD_UP1_ABIL0r_BAM_20G_CR2f_SET(AN_X4_ABILITIES_LD_UP1_ABILITIES_0r_reg, 1); 1105 if( (pc->an_tech_ability >> TEFMOD_ABILITY_40G_KR2) & 1 ) 1106 AN_X4_LD_UP1_ABIL0r_BAM_40G_KR2f_SET(AN_X4_ABILITIES_LD_UP1_ABILITIES_0r_reg, 1); 1107 if( (pc->an_tech_ability >> TEFMOD_ABILITY_40G_CR2) & 1 ) 1108 AN_X4_LD_UP1_ABIL0r_BAM_40G_CR2f_SET(AN_X4_ABILITIES_LD_UP1_ABILITIES_0r_reg, 1); 1109 if( (pc->an_tech_ability >> TEFMOD_ABILITY_50G_KR2) & 1 ) 1110 AN_X4_LD_UP1_ABIL0r_BAM_50G_KR2f_SET(AN_X4_ABILITIES_LD_UP1_ABILITIES_0r_reg, 1); 1111 if( (pc->an_tech_ability >> TEFMOD_ABILITY_50G_CR2) & 1 ) 1112 AN_X4_LD_UP1_ABIL0r_BAM_50G_CR2f_SET(AN_X4_ABILITIES_LD_UP1_ABILITIES_0r_reg, 1); 1113 if( (pc->an_tech_ability >> TEFMOD_ABILITY_50G_KR4) & 1 ) 1114 AN_X4_LD_UP1_ABIL0r_BAM_50G_KR4f_SET(AN_X4_ABILITIES_LD_UP1_ABILITIES_0r_reg, 1); 1115 if( (pc->an_tech_ability >> TEFMOD_ABILITY_50G_CR4) & 1 ) 1116 AN_X4_LD_UP1_ABIL0r_BAM_50G_CR4f_SET(AN_X4_ABILITIES_LD_UP1_ABILITIES_0r_reg, 1); 1117 1118 AN_X4_LD_UP1_ABIL0r_BAM_HG2f_SET(AN_X4_ABILITIES_LD_UP1_ABILITIES_0r_reg, pc->an_higig2); 1119 1120 /******** Setting AN_X4_ABILITIES_ld_up1_abilities_0 0xC181******/ 1121 PHYMOD_IF_ERR_RETURN(WRITE_AN_X4_LD_UP1_ABIL0r(pc, AN_X4_ABILITIES_LD_UP1_ABILITIES_0r_reg)); 1122 1123 1124 data =0; 1125 AN_X4_LD_UP1_ABIL1r_CLR(AN_X4_ABILITIES_LD_UP1_ABILITIES_1r_reg); 1126 /******* User page abilities*********/ 1127 if( (pc->an_tech_ability >> TEFMOD_ABILITY_20G_KR1) & 1 ) 1128 AN_X4_LD_UP1_ABIL1r_BAM_20G_KR1f_SET(AN_X4_ABILITIES_LD_UP1_ABILITIES_1r_reg, 1); 1129 if( (pc->an_tech_ability >> TEFMOD_ABILITY_20G_CR1) & 1 ) 1130 AN_X4_LD_UP1_ABIL1r_BAM_20G_CR1f_SET(AN_X4_ABILITIES_LD_UP1_ABILITIES_1r_reg, 1); 1131 if( (pc->an_tech_ability >> TEFMOD_ABILITY_25G_KR1) & 1 ) 1132 AN_X4_LD_UP1_ABIL1r_BAM_25G_KR1f_SET(AN_X4_ABILITIES_LD_UP1_ABILITIES_1r_reg, 1); 1133 if( (pc->an_tech_ability >> TEFMOD_ABILITY_25G_CR1) & 1 ) 1134 AN_X4_LD_UP1_ABIL1r_BAM_25G_CR1f_SET(AN_X4_ABILITIES_LD_UP1_ABILITIES_1r_reg, 1); 1135 1136 /******** Setting AN_X4_ABILITIES_ld_up1_abilities_1 0xC182******/ 1137 PHYMOD_IF_ERR_RETURN(WRITE_AN_X4_LD_UP1_ABIL1r(pc, AN_X4_ABILITIES_LD_UP1_ABILITIES_1r_reg)); 1138 1139 AN_X1_BAM_SPD_PRI0r_CLR(AN_X1_CONTROL_BAM_SPEED_PRI_0r_reg); 1140 AN_X1_BAM_SPD_PRI1r_CLR(AN_X1_CONTROL_BAM_SPEED_PRI_1r_reg); 1141 AN_X1_BAM_SPD_PRI2r_CLR(AN_X1_CONTROL_BAM_SPEED_PRI_2r_reg); 1142 AN_X1_BAM_SPD_PRI3r_CLR(AN_X1_CONTROL_BAM_SPEED_PRI_3r_reg); 1143 AN_X1_BAM_SPD_PRI4r_CLR(AN_X1_CONTROL_BAM_SPEED_PRI_4r_reg); 1144 1145 data = pc->an_priority_remap_0; 1146 /********Setting AN_X1_BAM_SPD_PRI0 0x9242*****/ 1147 AN_X1_BAM_SPD_PRI0r_SET(AN_X1_CONTROL_BAM_SPEED_PRI_0r_reg, data); 1148 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_BAM_SPD_PRI0r(pc, AN_X1_CONTROL_BAM_SPEED_PRI_0r_reg)); 1149 1150 data = pc->an_priority_remap_1; 1151 AN_X1_BAM_SPD_PRI1r_SET(AN_X1_CONTROL_BAM_SPEED_PRI_1r_reg, data); 1152 /********Setting AN_X1_BAM_SPD_PRI1 0x9243*****/ 1153 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_BAM_SPD_PRI1r(pc, AN_X1_CONTROL_BAM_SPEED_PRI_1r_reg)); 1154 1155 data = pc->an_priority_remap_2; 1156 AN_X1_BAM_SPD_PRI2r_SET(AN_X1_CONTROL_BAM_SPEED_PRI_2r_reg, data); 1157 /********Setting AN_X1_BAM_SPD_PRI2 0x9244*****/ 1158 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_BAM_SPD_PRI2r(pc, AN_X1_CONTROL_BAM_SPEED_PRI_2r_reg)); 1159 1160 data = pc->an_priority_remap_3; 1161 AN_X1_BAM_SPD_PRI3r_SET(AN_X1_CONTROL_BAM_SPEED_PRI_3r_reg, data); 1162 /********Setting AN_X1_BAM_SPD_PRI3 0x9245*****/ 1163 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_BAM_SPD_PRI3r(pc, AN_X1_CONTROL_BAM_SPEED_PRI_3r_reg)); 1164 1165 data = pc->an_priority_remap_4; 1166 AN_X1_BAM_SPD_PRI4r_SET(AN_X1_CONTROL_BAM_SPEED_PRI_4r_reg, data); 1167 /********Setting AN_X1_BAM_SPD_PRI4 0x9246*****/ 1168 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_BAM_SPD_PRI4r(pc, AN_X1_CONTROL_BAM_SPEED_PRI_4r_reg)); 1169 1170 return PHYMOD_E_NONE; 1171 } 1172 #endif 1173 1174 #ifdef _SDK_TEFMOD_ 1175 1176 int tefmod_autoneg_ability_set(PHYMOD_ST* pc, tefmod_an_adv_ability_t *cl73_adv) 1177 { 1178 1179 uint32_t override_v; 1180 1181 AN_X4_LD_BASE_ABIL1r_t AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg; 1182 AN_X4_LD_BASE_ABIL0r_t AN_X4_ABILITIES_LD_BASE_ABILITIES_0r_reg; 1183 AN_X4_LD_UP1_ABIL0r_t AN_X4_ABILITIES_LD_UP1_ABILITIES_0r_reg; 1184 AN_X4_LD_UP1_ABIL1r_t AN_X4_ABILITIES_LD_UP1_ABILITIES_1r_reg; 1185 MAIN0_SERDESIDr_t serdesid; 1186 AN_X4_LD_BASE_ABIL_3_GEN2r_t AN_X4_LD_BASE_ABIL_3_GEN2r_reg; 1187 AN_X4_LD_BASE_ABIL_4_GEN2r_t AN_X4_LD_BASE_ABIL_4_GEN2r_reg; 1188 AN_X4_LD_UP1_ABIL_1_GEN2r_t AN_X4_LD_UP1_ABIL_1_GEN2r_reg; 1189 AN_X4_LD_FEC_BASEPAGE_ABIL_GEN2r_t AN_X4_LD_FEC_BASEPAGE_ABIL_GEN2r_reg; 1190 uint32_t model; 1191 int adv100g = 0; 1192 1193 /* next check serdes ID to see if gen2 or not */ 1194 READ_MAIN0_SERDESIDr(pc, &serdesid); 1195 model = MAIN0_SERDESIDr_MODEL_NUMBERf_GET(serdesid); 1196 1197 AN_X4_LD_BASE_ABIL1r_CLR(AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg); 1198 1199 /******* Base Abilities*****/ 1200 AN_X4_LD_BASE_ABIL1r_SET(AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg, cl73_adv->an_base_speed & 0x3f); 1201 1202 /******* Pause Settings ********/ 1203 if (cl73_adv->an_pause == TEFMOD_NO_PAUSE) 1204 AN_X4_LD_BASE_ABIL1r_CL73_PAUSEf_SET(AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg, 0); 1205 if (cl73_adv->an_pause == TEFMOD_SYMM_PAUSE) 1206 AN_X4_LD_BASE_ABIL1r_CL73_PAUSEf_SET(AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg, 1); 1207 if (cl73_adv->an_pause == TEFMOD_ASYM_PAUSE) 1208 AN_X4_LD_BASE_ABIL1r_CL73_PAUSEf_SET(AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg, 2); 1209 if (cl73_adv->an_pause == TEFMOD_ASYM_SYMM_PAUSE) 1210 AN_X4_LD_BASE_ABIL1r_CL73_PAUSEf_SET(AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg, 3); 1211 1212 /****** FEC Settings ********/ 1213 if (cl73_adv->an_fec == TEFMOD_FEC_NOT_SUPRTD) 1214 AN_X4_LD_BASE_ABIL1r_FEC_REQf_SET(AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg, 0); 1215 if(cl73_adv->an_fec == TEFMOD_FEC_SUPRTD_NOT_REQSTD) { 1216 AN_X4_LD_BASE_ABIL1r_FEC_REQf_SET(AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg, 1); 1217 } 1218 if (AN_X4_LD_BASE_ABIL1r_BASE_100G_CR4f_GET(AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg) || 1219 AN_X4_LD_BASE_ABIL1r_BASE_100G_KR4f_GET(AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg)) { 1220 adv100g = 1; 1221 } 1222 if ((cl73_adv->an_fec & TEFMOD_FEC_CL74_SUPRTD_REQSTD) || 1223 ((cl73_adv->an_fec & TEFMOD_FEC_CL91_SUPRTD_REQSTD) && adv100g)) { 1224 AN_X4_LD_BASE_ABIL1r_FEC_REQf_SET(AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg, 3); 1225 } 1226 1227 /*next if model number is gen2, then we need to check 25G IEEE base speed */ 1228 if (model == TSCF_GEN2) { 1229 AN_X4_LD_BASE_ABIL_3_GEN2r_CLR(AN_X4_LD_BASE_ABIL_3_GEN2r_reg); 1230 AN_X4_LD_BASE_ABIL_4_GEN2r_CLR(AN_X4_LD_BASE_ABIL_4_GEN2r_reg); 1231 AN_X4_LD_FEC_BASEPAGE_ABIL_GEN2r_CLR(AN_X4_LD_FEC_BASEPAGE_ABIL_GEN2r_reg); 1232 AN_X4_LD_UP1_ABIL_1_GEN2r_CLR(AN_X4_LD_UP1_ABIL_1_GEN2r_reg); 1233 1234 if((cl73_adv->an_base_speed >> TEFMOD_CL73_25GBASE_KR1 ) & 1) { 1235 AN_X4_LD_BASE_ABIL_3_GEN2r_BASE_25G_KR1_ENf_SET(AN_X4_LD_BASE_ABIL_3_GEN2r_reg, 1); 1236 /* IEEE bit location for KR1/Cr1 is 10 */ 1237 AN_X4_LD_BASE_ABIL_3_GEN2r_BASE_25G_KR1_SELf_SET(AN_X4_LD_BASE_ABIL_3_GEN2r_reg, TEFMOD_CL73_25GBASE_KR1_POS); 1238 } 1239 if((cl73_adv->an_base_speed >> TEFMOD_CL73_25GBASE_CR1 ) & 1) { 1240 AN_X4_LD_BASE_ABIL_3_GEN2r_BASE_25G_CR1_ENf_SET(AN_X4_LD_BASE_ABIL_3_GEN2r_reg, 1); 1241 /* IEEE bit location for KR1/Cr1 is 10 */ 1242 AN_X4_LD_BASE_ABIL_3_GEN2r_BASE_25G_CR1_SELf_SET(AN_X4_LD_BASE_ABIL_3_GEN2r_reg, TEFMOD_CL73_25GBASE_CR1_POS); 1243 } 1244 if((cl73_adv->an_base_speed >> TEFMOD_CL73_25GBASE_KRS1 ) & 1) { 1245 AN_X4_LD_BASE_ABIL_4_GEN2r_BASE_25G_KRS1_ENf_SET(AN_X4_LD_BASE_ABIL_4_GEN2r_reg, 1); 1246 /* IEEE bit location for KRS1/CrS1 is 9 */ 1247 AN_X4_LD_BASE_ABIL_4_GEN2r_BASE_25G_KRS1_SELf_SET(AN_X4_LD_BASE_ABIL_4_GEN2r_reg, TEFMOD_CL73_25GBASE_KRS1_POS); 1248 } 1249 if((cl73_adv->an_base_speed >> TEFMOD_CL73_25GBASE_CRS1 ) & 1) { 1250 AN_X4_LD_BASE_ABIL_4_GEN2r_BASE_25G_CRS1_ENf_SET(AN_X4_LD_BASE_ABIL_4_GEN2r_reg, 1); 1251 /* IEEE bit location for KRS1/CrS1 is 9 */ 1252 AN_X4_LD_BASE_ABIL_4_GEN2r_BASE_25G_CRS1_SELf_SET(AN_X4_LD_BASE_ABIL_4_GEN2r_reg, TEFMOD_CL73_25GBASE_CRS1_POS); 1253 } 1254 PHYMOD_IF_ERR_RETURN(WRITE_AN_X4_LD_BASE_ABIL_3_GEN2r(pc, AN_X4_LD_BASE_ABIL_3_GEN2r_reg)); 1255 PHYMOD_IF_ERR_RETURN(WRITE_AN_X4_LD_BASE_ABIL_4_GEN2r(pc, AN_X4_LD_BASE_ABIL_4_GEN2r_reg)); 1256 1257 /* 1258 * In case of Gen2 we always set the SEL bit for BASE_FEC (CL74 bits 11:07=24) and RS_FEC (CL91 bits 05:01 =23) 1259 * Irrespective of whether FEC74/FEC91 is requested or not. 1260 */ 1261 AN_X4_LD_FEC_BASEPAGE_ABIL_GEN2r_BASE_R_FEC_REQ_SELf_SET(AN_X4_LD_FEC_BASEPAGE_ABIL_GEN2r_reg, TEFMOD_CL73_25GBASE_FEC_POS); 1262 AN_X4_LD_FEC_BASEPAGE_ABIL_GEN2r_RS_FEC_REQ_SELf_SET(AN_X4_LD_FEC_BASEPAGE_ABIL_GEN2r_reg, TEFMOD_CL73_25G_RS_FEC_POS); 1263 AN_X4_LD_FEC_BASEPAGE_ABIL_GEN2r_BASE_R_FEC_REQ_ENf_SET(AN_X4_LD_FEC_BASEPAGE_ABIL_GEN2r_reg, 0); 1264 AN_X4_LD_FEC_BASEPAGE_ABIL_GEN2r_RS_FEC_REQ_ENf_SET(AN_X4_LD_FEC_BASEPAGE_ABIL_GEN2r_reg, 0); 1265 1266 /*next we need to check which fec to enable */ 1267 if (cl73_adv->an_fec & TEFMOD_FEC_CL74_SUPRTD_REQSTD) { 1268 AN_X4_LD_FEC_BASEPAGE_ABIL_GEN2r_BASE_R_FEC_REQ_ENf_SET(AN_X4_LD_FEC_BASEPAGE_ABIL_GEN2r_reg, 1); 1269 } else { 1270 AN_X4_LD_FEC_BASEPAGE_ABIL_GEN2r_BASE_R_FEC_REQ_ENf_SET(AN_X4_LD_FEC_BASEPAGE_ABIL_GEN2r_reg, 0); 1271 } 1272 if (cl73_adv->an_fec & TEFMOD_FEC_CL91_SUPRTD_REQSTD) { 1273 AN_X4_LD_FEC_BASEPAGE_ABIL_GEN2r_RS_FEC_REQ_ENf_SET(AN_X4_LD_FEC_BASEPAGE_ABIL_GEN2r_reg, 1); 1274 } else { 1275 AN_X4_LD_FEC_BASEPAGE_ABIL_GEN2r_RS_FEC_REQ_ENf_SET(AN_X4_LD_FEC_BASEPAGE_ABIL_GEN2r_reg, 0); 1276 } 1277 1278 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_LD_FEC_BASEPAGE_ABIL_GEN2r(pc, AN_X4_LD_FEC_BASEPAGE_ABIL_GEN2r_reg)); 1279 } 1280 1281 /***** Setting AN_X4_ABILITIES_ld_base_abilities_1 0xC184 *******/ 1282 PHYMOD_IF_ERR_RETURN(WRITE_AN_X4_LD_BASE_ABIL1r(pc, AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg)); 1283 1284 AN_X4_LD_BASE_ABIL0r_CLR(AN_X4_ABILITIES_LD_BASE_ABILITIES_0r_reg); 1285 1286 /****** Base selector *****/ 1287 AN_X4_LD_BASE_ABIL0r_CL73_BASE_SELECTORf_SET(AN_X4_ABILITIES_LD_BASE_ABILITIES_0r_reg, 1); 1288 /***** Setting AN_X4_ABILITIES_ld_base_abilities_0 0xC1C3 *******/ 1289 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_LD_BASE_ABIL0r(pc, AN_X4_ABILITIES_LD_BASE_ABILITIES_0r_reg)); 1290 1291 AN_X4_LD_UP1_ABIL0r_CLR(AN_X4_ABILITIES_LD_UP1_ABILITIES_0r_reg); 1292 /******** Setting AN_X4_ABILITIES_ld_up1_abilities_0 0xC1C1[3:0]&[9:6] ******/ 1293 AN_X4_LD_UP1_ABIL0r_SET(AN_X4_ABILITIES_LD_UP1_ABILITIES_0r_reg, cl73_adv->an_bam_speed & 0x3cf); 1294 /******** Setting AN_X4_ABILITIES_ld_up1_abilities_0 0xC1C1 ******/ 1295 PHYMOD_IF_ERR_RETURN(WRITE_AN_X4_LD_UP1_ABIL0r(pc, AN_X4_ABILITIES_LD_UP1_ABILITIES_0r_reg)); 1296 /******** Setting AN_X4_ABILITIES_ld_up1_abilities_0 0xC1C1[15] ******/ 1297 AN_X4_LD_UP1_ABIL0r_BAM_HG2f_SET(AN_X4_ABILITIES_LD_UP1_ABILITIES_0r_reg, cl73_adv->an_hg2); 1298 1299 /******** Setting AN_X4_ABILITIES_ld_up1_abilities_0 0xC1C1******/ 1300 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_LD_UP1_ABIL0r(pc, AN_X4_ABILITIES_LD_UP1_ABILITIES_0r_reg)); 1301 1302 /******** Setting AN_X4_ABILITIES_ld_up1_abilities_1 0xC1C2 ******/ 1303 AN_X4_LD_UP1_ABIL1r_CLR(AN_X4_ABILITIES_LD_UP1_ABILITIES_1r_reg); 1304 /******* Setting AN_X4_ABILITIES_ld_up1_abilities_1 0xC1C2[4:1] *********/ 1305 AN_X4_LD_UP1_ABIL1r_SET(AN_X4_ABILITIES_LD_UP1_ABILITIES_1r_reg, cl73_adv->an_bam_speed1 & 0x1e); 1306 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_LD_UP1_ABIL1r(pc, AN_X4_ABILITIES_LD_UP1_ABILITIES_1r_reg)); 1307 1308 /* next need to check if TH+ for cl74 or cl91 support on BAM speed */ 1309 /*next if model number is gen2, then we need to check 25G IEEE base speed */ 1310 if (model == TSCF_GEN2) { 1311 /*next check if BAM speed */ 1312 if ((cl73_adv->an_bam_speed) || (cl73_adv->an_bam_speed1)) { 1313 AN_X4_LD_UP1_ABIL_1_GEN2r_CLR(AN_X4_LD_UP1_ABIL_1_GEN2r_reg); 1314 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LD_UP1_ABIL_1_GEN2r(pc, &AN_X4_LD_UP1_ABIL_1_GEN2r_reg)); 1315 AN_X4_LD_UP1_ABIL_1_GEN2r_CL74_REQf_SET(AN_X4_LD_UP1_ABIL_1_GEN2r_reg, 0x1); 1316 AN_X4_LD_UP1_ABIL_1_GEN2r_CL91_REQf_SET(AN_X4_LD_UP1_ABIL_1_GEN2r_reg, 0x1); 1317 if (cl73_adv->an_fec & TEFMOD_FEC_CL74_SUPRTD_REQSTD) { 1318 AN_X4_LD_UP1_ABIL_1_GEN2r_CL74_REQf_SET(AN_X4_LD_UP1_ABIL_1_GEN2r_reg, TEFMOD_BAM_CL74_REQ); 1319 } 1320 if (cl73_adv->an_fec & TEFMOD_FEC_CL91_SUPRTD_REQSTD) { 1321 AN_X4_LD_UP1_ABIL_1_GEN2r_CL91_REQf_SET(AN_X4_LD_UP1_ABIL_1_GEN2r_reg, TEFMOD_BAM_CL91_REQ); 1322 } 1323 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_LD_UP1_ABIL_1_GEN2r(pc, AN_X4_LD_UP1_ABIL_1_GEN2r_reg)); 1324 } 1325 } 1326 1327 1328 if((cl73_adv->an_cl72 & 0x1) == 1) { 1329 override_v = ((OVERRIDE_CL72_EN_DIS<<16) | 1); 1330 tefmod_set_override_1(pc, 0, override_v); 1331 } else { 1332 override_v = ((OVERRIDE_CL72_EN<<16) | 0); 1333 tefmod_set_override_1(pc, 0, override_v); 1334 } 1335 1336 return PHYMOD_E_NONE; 1337 } 1338 1339 #endif /* _SDK_TEFMOD_ */ 1340 1341 1342 /*! 1343 @brief To get autoneg advertisement registers. 1344 @param pc handle to current TSCF context (#PHYMOD_ST) 1345 @returns PHYMOD_E_NONE if no errors. PHYMOD_EERROR else. 1346 @details 1347 */ 1348 int tefmod_autoneg_get(PHYMOD_ST* pc) /* AUTONEG_GET */ 1349 { 1350 TEFMOD_DBG_IN_FUNC_INFO(pc); 1351 /* TBD */ 1352 return PHYMOD_E_NONE; 1353 } 1354 1355 /*! 1356 @brief Controls the setting/resetting of autoneg ability and enabling/disabling 1357 @param pc handle to current TSCF context (#PHYMOD_ST) 1358 @param an_control handle to TSCF an control struct #tefmod_an_control_t 1359 @returns PHYMOD_E_NONE if no errors. PHYMOD_EERROR else. 1360 1361 @details 1362 This function programs auto-negotiation (AN) modes for the TEF. It can 1363 enable/disable clause37/clause73/BAM autonegotiation capabilities. Call this 1364 function once for combo mode and once per lane in independent lane mode. 1365 1366 The autonegotiation mode is indicated by setting an_control as required. 1367 */ 1368 1369 #ifdef _DV_TB_ 1370 int tefmod_autoneg_control(PHYMOD_ST* pc) 1371 { 1372 uint16_t cl73_bam_enable, cl73_hpam_enable, cl73_enable; 1373 uint16_t cl73_nonce_match_over, cl73_nonce_match_val ; 1374 uint16_t bam_to_hpam_ad_en; 1375 uint16_t num_advertised_lanes; 1376 AN_X4_CL73_CFGr_t AN_X4_ABILITIES_CL73_CFGr_reg; 1377 1378 TEFMOD_DBG_IN_FUNC_INFO(pc); 1379 cl73_enable = pc->an_en; 1380 cl73_nonce_match_over = pc->nonce_match_override; 1381 cl73_nonce_match_val = pc->nonce_match_val; 1382 cl73_bam_enable = pc->cl73_bam_enable; 1383 cl73_hpam_enable = pc->cl73_hpam_enable; 1384 bam_to_hpam_ad_en = pc->bam_to_hpam_ad_en; 1385 num_advertised_lanes = pc->num_advertised_lanes; 1386 1387 /****Added for cl73_disable test case ****/ 1388 #if defined (_DV_TB_) 1389 if(pc->override_an_en_as_disable==1) { 1390 cl73_enable =0; 1391 } 1392 #endif 1393 1394 AN_X4_CL73_CFGr_CLR(AN_X4_ABILITIES_CL73_CFGr_reg); 1395 1396 AN_X4_CL73_CFGr_NUM_ADVERTISED_LANESf_SET(AN_X4_ABILITIES_CL73_CFGr_reg, num_advertised_lanes); 1397 1398 AN_X4_CL73_CFGr_CL73_NONCE_MATCH_VALf_SET(AN_X4_ABILITIES_CL73_CFGr_reg, cl73_nonce_match_val); 1399 1400 AN_X4_CL73_CFGr_CL73_NONCE_MATCH_OVERf_SET(AN_X4_ABILITIES_CL73_CFGr_reg, cl73_nonce_match_over); 1401 1402 AN_X4_CL73_CFGr_CL73_ENABLEf_SET(AN_X4_ABILITIES_CL73_CFGr_reg, cl73_enable); 1403 1404 AN_X4_CL73_CFGr_CL73_HPAM_ENABLEf_SET(AN_X4_ABILITIES_CL73_CFGr_reg, cl73_hpam_enable); 1405 1406 AN_X4_CL73_CFGr_CL73_BAM_ENABLEf_SET(AN_X4_ABILITIES_CL73_CFGr_reg, cl73_bam_enable); 1407 1408 AN_X4_CL73_CFGr_BAM_TO_HPAM_AD_ENf_SET(AN_X4_ABILITIES_CL73_CFGr_reg, bam_to_hpam_ad_en); 1409 1410 AN_X4_CL73_CFGr_AD_TO_CL73_ENf_SET(AN_X4_ABILITIES_CL73_CFGr_reg, pc->hpam_to_cl73_ad_en); 1411 /*********Setting AN_X4_ABILITIES_cl73_cfg 0xC180 ******/ 1412 PHYMOD_IF_ERR_RETURN(WRITE_AN_X4_CL73_CFGr(pc, AN_X4_ABILITIES_CL73_CFGr_reg)); 1413 1414 1415 1416 return PHYMOD_E_NONE; 1417 } /* tefmod_autoneg_control(PHYMOD_ST* pc) */ 1418 #endif 1419 1420 #ifdef _SDK_TEFMOD_ 1421 int tefmod_autoneg_control(PHYMOD_ST* pc, tefmod_an_control_t *an_control) 1422 { 1423 phymod_access_t pa_copy; 1424 uint16_t num_advertised_lanes, cl73_bam_enable ; 1425 int start_lane, num_of_lane, i; 1426 uint16_t cl73_hpam_enable, cl73_enable; 1427 uint16_t cl73_next_page; 1428 uint16_t cl73_restart ; 1429 uint16_t cl73_bam_code; 1430 uint16_t msa_overrides; 1431 uint32_t plldiv_r_val = 0; 1432 MAIN0_SETUPr_t reg_setup; 1433 1434 AN_X4_CL73_CFGr_t AN_X4_CL73_CFGr_reg; 1435 AN_X1_CL73_ERRr_t AN_X1_CL73_ERRr_reg; 1436 AN_X4_CL73_CTLSr_t AN_X4_CL73_CTLSr_reg; 1437 AN_X4_LD_BASE_ABIL1r_t AN_X4_LD_BASE_ABIL1r_reg; 1438 AN_X4_LD_BAM_ABILr_t AN_X4_ABILITIES_LD_BAM_ABILITIESr_reg; 1439 1440 PHYMOD_IF_ERR_RETURN 1441 (phymod_util_lane_config_get(pc, &start_lane, &num_of_lane)); 1442 PHYMOD_MEMCPY(&pa_copy, pc, sizeof(pa_copy)); 1443 1444 TEFMOD_DBG_IN_FUNC_INFO(pc); 1445 num_advertised_lanes = an_control->num_lane_adv; 1446 cl73_bam_code = 0x0; 1447 cl73_bam_enable = 0x0; 1448 cl73_hpam_enable = 0x0; 1449 cl73_enable = 0x0; 1450 cl73_next_page = 0x0; 1451 cl73_restart = 0x0; 1452 msa_overrides = 0x0; 1453 1454 switch (an_control->an_type) { 1455 case TEFMOD_AN_MODE_CL73: 1456 cl73_restart = an_control->enable; 1457 cl73_enable = an_control->enable; 1458 break; 1459 case TEFMOD_AN_MODE_CL73BAM: 1460 cl73_restart = an_control->enable; 1461 cl73_enable = an_control->enable; 1462 cl73_bam_enable = an_control->enable; 1463 cl73_bam_code = 0x3; 1464 cl73_next_page = 0x1; 1465 break; 1466 case TEFMOD_AN_MODE_CL73_MSA: 1467 cl73_restart = an_control->enable; 1468 cl73_enable = an_control->enable; 1469 cl73_bam_enable = an_control->enable; 1470 cl73_bam_code = 0x3; 1471 cl73_next_page = 0x1; 1472 msa_overrides = 0x1; 1473 break; 1474 case TEFMOD_AN_MODE_MSA: 1475 cl73_restart = an_control->enable; 1476 cl73_enable = an_control->enable; 1477 cl73_bam_enable = an_control->enable; 1478 cl73_bam_code = 0x3; 1479 cl73_next_page = 0x1; 1480 msa_overrides = 0x1; 1481 break; 1482 case TEFMOD_AN_MODE_HPAM: 1483 cl73_restart = an_control->enable; 1484 cl73_enable = an_control->enable; 1485 cl73_hpam_enable = an_control->enable; 1486 /* cl73_bam_code = 0x4; */ 1487 cl73_next_page = 0x1; 1488 break; 1489 default: 1490 return PHYMOD_E_FAIL; 1491 break; 1492 } 1493 if(msa_overrides == 0x1) { 1494 tefmod_an_oui_t oui; 1495 oui.oui = 0x6a737d; 1496 oui.oui_override_bam73_adv = 0x1; 1497 oui.oui_override_bam73_det = 0x1; 1498 oui.oui_override_hpam_adv = 0x0; 1499 oui.oui_override_hpam_det = 0x0; 1500 PHYMOD_IF_ERR_RETURN(tefmod_an_oui_set(pc, oui)); 1501 PHYMOD_IF_ERR_RETURN(tefmod_an_msa_mode_set(pc, msa_overrides)); 1502 } 1503 /* RESET Speed Change bit */ 1504 if(an_control->enable){ 1505 tefmod_disable_set(pc); 1506 } 1507 1508 BCMI_TSCF_XGXS_MAIN0_SETUPr_CLR(reg_setup); 1509 if(an_control->enable){ 1510 /*next we decide which cl73_vco to set based on the current VCO */ 1511 PHYMOD_IF_ERR_RETURN(tefmod_get_plldiv(pc, &plldiv_r_val)); 1512 1513 if(plldiv_r_val<=4) { /* pll_div <= 132; for 156MHz only */ 1514 MAIN0_SETUPr_CL73_VCOf_SET(reg_setup, 0); 1515 } else { 1516 MAIN0_SETUPr_CL73_VCOf_SET(reg_setup, 1); 1517 } 1518 PHYMOD_IF_ERR_RETURN(MODIFY_MAIN0_SETUPr(pc, reg_setup)); 1519 } 1520 1521 /*0x9254 AN_X1_TIMERS_cl73_error*/ 1522 AN_X1_CL73_ERRr_CLR(AN_X1_CL73_ERRr_reg); 1523 if(an_control->an_type == (tefmod_an_type_t)TEFMOD_AN_MODE_CL73) { 1524 AN_X1_CL73_ERRr_SET(AN_X1_CL73_ERRr_reg, 0); 1525 } else if(an_control->an_type == (tefmod_an_type_t)TEFMOD_AN_MODE_HPAM){ 1526 AN_X1_CL73_ERRr_SET(AN_X1_CL73_ERRr_reg, 0xfff0); 1527 } else if (an_control->an_type == (tefmod_an_type_t)TEFMOD_AN_MODE_CL73BAM) { 1528 AN_X1_CL73_ERRr_SET(AN_X1_CL73_ERRr_reg, 0x1a10); 1529 } 1530 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_CL73_ERRr(pc, AN_X1_CL73_ERRr_reg)); 1531 1532 1533 /*need to set cl73 BAM next page probably*/ 1534 AN_X4_LD_BASE_ABIL1r_CLR(AN_X4_LD_BASE_ABIL1r_reg); 1535 AN_X4_LD_BASE_ABIL1r_NEXT_PAGEf_SET(AN_X4_LD_BASE_ABIL1r_reg, cl73_next_page & 1); 1536 PHYMOD_IF_ERR_RETURN ( MODIFY_AN_X4_LD_BASE_ABIL1r(pc, AN_X4_LD_BASE_ABIL1r_reg)); 1537 1538 /* Writing bam_code */ 1539 AN_X4_LD_BAM_ABILr_CLR(AN_X4_ABILITIES_LD_BAM_ABILITIESr_reg); 1540 AN_X4_LD_BAM_ABILr_CL73_BAM_CODEf_SET(AN_X4_ABILITIES_LD_BAM_ABILITIESr_reg, cl73_bam_code); 1541 PHYMOD_IF_ERR_RETURN(WRITE_AN_X4_LD_BAM_ABILr(pc, AN_X4_ABILITIES_LD_BAM_ABILITIESr_reg)); 1542 1543 AN_X4_CL73_CTLSr_CLR(AN_X4_CL73_CTLSr_reg); 1544 /* disable 1G PD function for now */ 1545 AN_X4_CL73_CTLSr_PD_KX_ENf_SET(AN_X4_CL73_CTLSr_reg, 0); 1546 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_CL73_CTLSr(pc, AN_X4_CL73_CTLSr_reg)); 1547 1548 AN_X4_CL73_CFGr_CLR(AN_X4_CL73_CFGr_reg); 1549 1550 AN_X4_CL73_CFGr_CL73_ENABLEf_SET(AN_X4_CL73_CFGr_reg,0); 1551 AN_X4_CL73_CFGr_CL73_AN_RESTARTf_SET(AN_X4_CL73_CFGr_reg,0); 1552 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_CL73_CFGr(pc, AN_X4_CL73_CFGr_reg)); 1553 1554 /*Setting X4 abilities*/ 1555 AN_X4_CL73_CFGr_CLR(AN_X4_CL73_CFGr_reg); 1556 AN_X4_CL73_CFGr_CL73_BAM_ENABLEf_SET(AN_X4_CL73_CFGr_reg,cl73_bam_enable); 1557 AN_X4_CL73_CFGr_CL73_HPAM_ENABLEf_SET(AN_X4_CL73_CFGr_reg,cl73_hpam_enable); 1558 AN_X4_CL73_CFGr_CL73_ENABLEf_SET(AN_X4_CL73_CFGr_reg,cl73_enable); 1559 AN_X4_CL73_CFGr_CL73_AN_RESTARTf_SET(AN_X4_CL73_CFGr_reg,cl73_restart); 1560 if(an_control->an_property_type & TEFMOD_AN_PROPERTY_ENABLE_HPAM_TO_CL73_AUTO ) 1561 AN_X4_CL73_CFGr_AD_TO_CL73_ENf_SET(AN_X4_CL73_CFGr_reg,0x1); 1562 else 1563 AN_X4_CL73_CFGr_AD_TO_CL73_ENf_SET(AN_X4_CL73_CFGr_reg,0x0); 1564 /* AN_X4_CL73_CFGr_HPAM_TO_CL73_AUTO_ENABLEf_SET(AN_X4_CL73_CFGr_reg,0x0); */ 1565 1566 if(an_control->an_property_type & TEFMOD_AN_PROPERTY_ENABLE_CL73_BAM_TO_HPAM_AUTO ) 1567 AN_X4_CL73_CFGr_BAM_TO_HPAM_AD_ENf_SET(AN_X4_CL73_CFGr_reg,0x1); 1568 else 1569 AN_X4_CL73_CFGr_BAM_TO_HPAM_AD_ENf_SET(AN_X4_CL73_CFGr_reg,0x0); 1570 1571 AN_X4_CL73_CFGr_NUM_ADVERTISED_LANESf_SET(AN_X4_CL73_CFGr_reg,num_advertised_lanes); 1572 1573 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_CL73_CFGr(pc, AN_X4_CL73_CFGr_reg)); 1574 1575 /* if an is enabled, the restart bit needs to be cleared */ 1576 1577 if (an_control->enable) { 1578 AN_X4_CL73_CFGr_CLR(AN_X4_CL73_CFGr_reg); 1579 AN_X4_CL73_CFGr_CL73_AN_RESTARTf_SET(AN_X4_CL73_CFGr_reg,0); 1580 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_CL73_CFGr(pc, AN_X4_CL73_CFGr_reg)); 1581 } 1582 1583 /* Disable the cl72 , when AN port is disabled. */ 1584 if (an_control->cl72_config_allowed) { 1585 if(an_control->enable == 0) { 1586 if(an_control->num_lane_adv == 1) { 1587 num_of_lane = 2; 1588 } else if (an_control->num_lane_adv == 2) { 1589 num_of_lane = 4; 1590 } else { 1591 num_of_lane = 1; 1592 } 1593 for (i = (num_of_lane-1); i >= 0; i--) { 1594 pa_copy.lane_mask = 0x1 << (i + start_lane); 1595 tefmod_clause72_control(&pa_copy, 0); 1596 } 1597 } 1598 } 1599 return PHYMOD_E_NONE; 1600 } /* temod_autoneg_control */ 1601 #endif 1602 1603 1604 /** 1605 @brief getRevDetails , calls revid_read 1606 @param pc handle to current TSCF context (#PHYMOD_ST) 1607 @returns The value PHYMOD_E_NONE upon successful completion 1608 @details 1609 */ 1610 /* internal function */ 1611 STATIC 1612 int _tefmod_getRevDetails(PHYMOD_ST* pc) 1613 { 1614 MAIN0_SERDESIDr_t MAIN0_SERDESIDr_reg; 1615 MAIN0_SERDESIDr_CLR(MAIN0_SERDESIDr_reg); 1616 PHYMOD_IF_ERR_RETURN(READ_MAIN0_SERDESIDr(pc, &MAIN0_SERDESIDr_reg)); 1617 return MAIN0_SERDESIDr_GET(MAIN0_SERDESIDr_reg); 1618 } 1619 1620 #ifdef _DV_TB_ 1621 /*! 1622 @brief Speeds up DSC and VGA funnctions for simulation purpose only 1623 @param pc handle to current TSCF context (#PHYMOD_ST) 1624 @returns The value PHYMOD_E_NONE upon successful completion. 1625 @details 1626 1627 This function speeds up DSC and VGA functions for any speed mode. Please don't 1628 call this function in normal operatio. 1629 Set #PHYMOD_ST::per_lane_control to 1 for speed up. 1630 1631 This function is controlled by the following register bit: 1632 1633 \li acq2_timeout, acq1_timeout, acqcdr_timeout (0xc210) -> 0x0421 1634 \li acqvga_timeout (0xc211) -> 0x0800 1635 */ 1636 1637 int tefmod_afe_speed_up_dsc_vga(PHYMOD_ST* pc) /* AFE_SPEED_UP_DSC_VGA */ 1638 { 1639 uint16_t data , pll_mode; 1640 int mapped_speed; 1641 AMS_PLL_CTL0r_t AMS_COM_PLL_CONTROL_0r_reg; 1642 DIG_TOP_USER_CTL0r_t DIG_COM_TOP_USER_CONTROL_0r_reg; 1643 TXFIR_MISC_CTL1r_t TX_FED_TXFIR_MISC_CONTROL1r_reg; 1644 DIG_RST_CTL_CORE_DPr_t DIG_COM_RESET_CONTROL_CORE_DPr_reg; 1645 PLL_CAL_CTL0r_t PLL_CAL_COM_CTL_0r_reg; 1646 PLL_CAL_CTL1r_t PLL_CAL_COM_CTL_1r_reg; 1647 PLL_CAL_CTL2r_t PLL_CAL_COM_CTL_2r_reg; 1648 1649 PLL_CAL_CTL5r_t PLL_CAL_COM_CTL_5r_reg; 1650 PLL_CAL_CTL6r_t PLL_CAL_COM_CTL_6r_reg; 1651 PLL_CAL_CTL7r_t PLL_CAL_COM_CTL_7r_reg; 1652 1653 TEFMOD_DBG_IN_FUNC_INFO(pc); 1654 AMS_PLL_CTL0r_CLR(AMS_COM_PLL_CONTROL_0r_reg); 1655 if(pc->tsc_clk_freq_pll_by_48) { 1656 AMS_PLL_CTL0r_AMS_PLL_SET_CLK4TSCf_SET(AMS_COM_PLL_CONTROL_0r_reg, 1); 1657 PHYMOD_IF_ERR_RETURN (MODIFY_AMS_PLL_CTL0r(pc, AMS_COM_PLL_CONTROL_0r_reg)); 1658 } 1659 /* removing reset for pll lock */ 1660 DIG_TOP_USER_CTL0r_CLR(DIG_COM_TOP_USER_CONTROL_0r_reg); 1661 if(pc->pmd_touched == 0) { 1662 if(pc->uc_active == 1){ 1663 1664 DIG_TOP_USER_CTL0r_UC_ACTIVEf_SET(DIG_COM_TOP_USER_CONTROL_0r_reg, 1); 1665 DIG_TOP_USER_CTL0r_CORE_DP_S_RSTBf_SET(DIG_COM_TOP_USER_CONTROL_0r_reg, 1); 1666 1667 /* release reset to pll data path. TBD need for all lanes and uc_active set */ 1668 PHYMOD_IF_ERR_RETURN (MODIFY_DIG_TOP_USER_CTL0r(pc, DIG_COM_TOP_USER_CONTROL_0r_reg)); 1669 1670 } 1671 else{ 1672 DIG_TOP_USER_CTL0r_CORE_DP_S_RSTBf_SET(DIG_COM_TOP_USER_CONTROL_0r_reg, 1); 1673 PHYMOD_IF_ERR_RETURN (MODIFY_DIG_TOP_USER_CTL0r(pc, DIG_COM_TOP_USER_CONTROL_0r_reg)); 1674 } 1675 } 1676 /* removeing electric idle */ 1677 1678 data = 0; 1679 TXFIR_MISC_CTL1r_CLR(TX_FED_TXFIR_MISC_CONTROL1r_reg); 1680 TXFIR_MISC_CTL1r_TX_DISABLE_OUTPUT_SELf_SET(TX_FED_TXFIR_MISC_CONTROL1r_reg, 0); 1681 TXFIR_MISC_CTL1r_DP_RESET_TX_DISABLE_DISf_SET(TX_FED_TXFIR_MISC_CONTROL1r_reg, 0); 1682 TXFIR_MISC_CTL1r_TX_EEE_QUIET_ENf_SET(TX_FED_TXFIR_MISC_CONTROL1r_reg, 0); 1683 PHYMOD_IF_ERR_RETURN (MODIFY_TXFIR_MISC_CTL1r(pc, TX_FED_TXFIR_MISC_CONTROL1r_reg)); 1684 1685 /* Loop filter stable other PLL signal */ 1686 DIG_RST_CTL_CORE_DPr_CLR(DIG_COM_RESET_CONTROL_CORE_DPr_reg); 1687 if(pc->pmd_touched == 0) { 1688 DIG_RST_CTL_CORE_DPr_TX_PI_LOOP_FILTER_STABLEf_SET(DIG_COM_RESET_CONTROL_CORE_DPr_reg, 1); 1689 1690 PHYMOD_IF_ERR_RETURN (MODIFY_DIG_RST_CTL_CORE_DPr(pc, DIG_COM_RESET_CONTROL_CORE_DPr_reg)); 1691 1692 /* PLL speed_up begin */ 1693 /* refclk_divcnt = 5 (default 16'h186a ) */ 1694 PLL_CAL_CTL5r_CLR(PLL_CAL_COM_CTL_5r_reg); 1695 1696 PLL_CAL_CTL5r_REFCLK_DIVCNTf_SET(PLL_CAL_COM_CTL_5r_reg, 5); 1697 PHYMOD_IF_ERR_RETURN (MODIFY_PLL_CAL_CTL5r(pc, PLL_CAL_COM_CTL_5r_reg)); 1698 1699 PLL_CAL_CTL6r_CLR(PLL_CAL_COM_CTL_6r_reg); 1700 /* refclk_divcnt_sel = 7 */ 1701 1702 PLL_CAL_CTL6r_REFCLK_DIVCNT_SELf_SET(PLL_CAL_COM_CTL_6r_reg, 7); 1703 PHYMOD_IF_ERR_RETURN (MODIFY_PLL_CAL_CTL6r(pc, PLL_CAL_COM_CTL_6r_reg)); 1704 1705 /* vco_start_time = 5 */ 1706 PLL_CAL_CTL0r_CLR(PLL_CAL_COM_CTL_0r_reg); 1707 1708 PLL_CAL_CTL0r_VCO_START_TIMEf_SET(PLL_CAL_COM_CTL_0r_reg, 5); 1709 PHYMOD_IF_ERR_RETURN (MODIFY_PLL_CAL_CTL0r(pc, PLL_CAL_COM_CTL_0r_reg)); 1710 1711 /* pre_freq_det_time = 8'd100 , retry_time = 8'd100 */ 1712 PLL_CAL_CTL1r_CLR(PLL_CAL_COM_CTL_1r_reg); 1713 1714 PLL_CAL_CTL1r_PRE_FREQ_DET_TIMEf_SET(PLL_CAL_COM_CTL_1r_reg, 0x64); 1715 1716 PLL_CAL_CTL1r_RETRY_TIMEf_SET(PLL_CAL_COM_CTL_1r_reg, 0x64); 1717 PHYMOD_IF_ERR_RETURN (MODIFY_PLL_CAL_CTL1r(pc, PLL_CAL_COM_CTL_1r_reg)); 1718 1719 /* res_cal_cntr = 0 */ 1720 PLL_CAL_CTL2r_CLR(PLL_CAL_COM_CTL_2r_reg); 1721 PLL_CAL_CTL2r_RES_CAL_CNTRf_SET(PLL_CAL_COM_CTL_2r_reg, 0); 1722 1723 PLL_CAL_CTL2r_WIN_CAL_CNTRf_SET(PLL_CAL_COM_CTL_2r_reg, 1); 1724 PHYMOD_IF_ERR_RETURN (MODIFY_PLL_CAL_CTL2r(pc, PLL_CAL_COM_CTL_2r_reg)); 1725 } 1726 /* PLL speed_up end */ 1727 1728 PLL_CAL_CTL7r_CLR(PLL_CAL_COM_CTL_7r_reg); 1729 if(pc->pmd_touched == 0) { 1730 if(pc->uc_active == 0){ 1731 tefmod_get_mapped_speed(pc->spd_intf, &mapped_speed); 1732 1733 /* data = (sc_pmd_entry[speed].pll_mode) << PLL_CAL_CTL7_PLL_MODE_SHIFT; */ 1734 if ((pc->spd_intf == TEFMOD_SPD_10000_XFI) || 1735 (pc->spd_intf == TEFMOD_SPD_1G_20G) || 1736 (pc->spd_intf == TEFMOD_SPD_10000_XFI_CR1) || 1737 (pc->spd_intf == TEFMOD_SPD_40G_MLD_X4) || 1738 (pc->spd_intf == TEFMOD_SPD_20000_XFI) || 1739 (pc->spd_intf == TEFMOD_SPD_40G_MLD_X2) || 1740 (pc->spd_intf == TEFMOD_SPD_20G_MLD_X2)) { 1741 pll_mode = 4; 1742 } else if ((pc->spd_intf == TEFMOD_SPD_10600_XFI_HG) || 1743 (pc->spd_intf == TEFMOD_SPD_10600_XFI_HG_CR1) || 1744 (pc->spd_intf == TEFMOD_SPD_21200_XFI_HG) || 1745 (pc->spd_intf == TEFMOD_SPD_21G_MLD_HG_X2) || 1746 (pc->spd_intf == TEFMOD_SPD_42G_MLD_HG_X2) || 1747 (pc->spd_intf == TEFMOD_SPD_42G_MLD_HG_X4)) { 1748 pll_mode = 5; 1749 1750 } else if ((pc->spd_intf == TEFMOD_SPD_25000_XFI) || 1751 (pc->spd_intf == TEFMOD_SPD_1G_25G) || 1752 (pc->spd_intf == TEFMOD_SPD_50G_MLD_X2) || 1753 (pc->spd_intf == TEFMOD_SPD_50G_MLD_X4) || 1754 (pc->spd_intf == TEFMOD_SPD_100G_MLD_X4)) { 1755 pll_mode = 7; 1756 1757 } else if ((pc->spd_intf == TEFMOD_SPD_26500_XFI_HG) || 1758 (pc->spd_intf == TEFMOD_SPD_53G_MLD_HG_X2) || 1759 (pc->spd_intf == TEFMOD_SPD_53G_MLD_HG_X4) || 1760 (pc->spd_intf == TEFMOD_SPD_106G_MLD_HG_X4)) { 1761 pll_mode = 10; 1762 } 1763 PLL_CAL_CTL7r_PLL_MODEf_SET(PLL_CAL_COM_CTL_7r_reg, pll_mode); 1764 1765 PHYMOD_IF_ERR_RETURN(MODIFY_PLL_CAL_CTL7r(pc, PLL_CAL_COM_CTL_7r_reg)); 1766 1767 } 1768 } 1769 return PHYMOD_E_NONE; 1770 } 1771 #endif /* _DV_TB_ */ 1772 1773 /* internal supporting function */ 1774 int tefmod_get_plldiv(PHYMOD_ST* pc, uint32_t *plldiv_r_val) 1775 { 1776 PLL_CAL_CTL7r_t PLL_CAL_CTL7r_reg; 1777 /* read back plldiv */ 1778 1779 TEFMOD_DBG_IN_FUNC_INFO(pc); 1780 PHYMOD_IF_ERR_RETURN (READ_PLL_CAL_CTL7r(pc, &PLL_CAL_CTL7r_reg)); 1781 1782 *plldiv_r_val = PLL_CAL_CTL7r_PLL_MODEf_GET(PLL_CAL_CTL7r_reg); 1783 1784 return PHYMOD_E_NONE; 1785 } 1786 1787 /* to update port_mode_select value. If the update warrants a pll reset, 1788 then return accData=1, otherwise return accData=0. The update shall 1789 support flex port technology. Called forced speed modes */ 1790 1791 int tefmod_update_port_mode_select(PHYMOD_ST* pc, tefmod_port_type_t port_type, int master_port, int tsc_clk_freq_pll_by_48, int pll_reset_en) 1792 { 1793 MAIN0_SETUPr_t MAIN0_SETUPr_reg; 1794 MAIN0_LN_SWPr_t MAIN0_LANE_SWAPr_reg; 1795 1796 TEFMOD_DBG_IN_FUNC_INFO(pc); 1797 1798 #ifdef _DV_TB_ 1799 pc->accData = 0; 1800 if(pc->tsc_touched == 1) { 1801 return PHYMOD_E_NONE; 1802 } 1803 #endif 1804 1805 PHYMOD_IF_ERR_RETURN (READ_MAIN0_SETUPr(pc, &MAIN0_SETUPr_reg)); 1806 1807 if((port_type ==TEFMOD_MULTI_PORT) ||(port_type ==TEFMOD_DXGXS)|| 1808 (port_type ==TEFMOD_SINGLE_PORT)||(port_type ==TEFMOD_TRI1_PORT)|| 1809 (port_type ==TEFMOD_TRI2_PORT)){ 1810 } else { 1811 PHYMOD_DEBUG_ERROR(("%-22s: ERROR port_type=%0d undefined\n", __func__, port_type)); 1812 return PHYMOD_E_FAIL; 1813 } 1814 1815 MAIN0_SETUPr_CLR(MAIN0_SETUPr_reg); 1816 MAIN0_SETUPr_PORT_MODE_SELf_SET(MAIN0_SETUPr_reg, port_type); 1817 /* Leave port mode to quad in an_en */ 1818 1819 MAIN0_SETUPr_MASTER_PORT_NUMf_SET(MAIN0_SETUPr_reg, master_port); 1820 1821 PHYMOD_IF_ERR_RETURN (MODIFY_MAIN0_SETUPr(pc, MAIN0_SETUPr_reg)); 1822 1823 PHYMOD_IF_ERR_RETURN(READ_MAIN0_SETUPr(pc, &MAIN0_SETUPr_reg)); 1824 1825 1826 MAIN0_SETUPr_CLR(MAIN0_SETUPr_reg); 1827 1828 MAIN0_SETUPr_TSC_CLK_CTRLf_SET(MAIN0_SETUPr_reg, tsc_clk_freq_pll_by_48); 1829 1830 PHYMOD_IF_ERR_RETURN (MODIFY_MAIN0_SETUPr(pc, MAIN0_SETUPr_reg)); 1831 1832 PHYMOD_IF_ERR_RETURN(READ_MAIN0_SETUPr(pc, &MAIN0_SETUPr_reg)); 1833 1834 MAIN0_LN_SWPr_CLR(MAIN0_LANE_SWAPr_reg); 1835 MAIN0_LN_SWPr_PLL_RESET_ENf_SET(MAIN0_LANE_SWAPr_reg, pll_reset_en); 1836 PHYMOD_IF_ERR_RETURN (MODIFY_MAIN0_LN_SWPr(pc, MAIN0_LANE_SWAPr_reg)); 1837 1838 return PHYMOD_E_NONE; 1839 } 1840 1841 /*! 1842 @brief Init routine sets various operating modes of TEF. 1843 @param pc handle to current TSCF context (#PHYMOD_ST) 1844 @param refclk Reference clock 1845 @param plldiv PLL Divider value 1846 @param port_type Port type as in enum #tefmod_port_type_t 1847 @param master_port master port (which controls the PLL) 1848 @param master_port master port (which controls the PLL) 1849 @param tsc_clk_freq_pll_by_48 TBD 1850 @param pll_reset_en TBD 1851 @returns PHYMOD_E_NONE if successful. PHYMOD_E_ERROR else. 1852 @details 1853 This function is called once per TEF. It cannot be called multiple times 1854 and should be called immediately after reset. Elements of #PHYMOD_ST should be 1855 initialized to required values prior to calling this function. The following 1856 sub-configurations are performed here. 1857 1858 \li Read the revision Id. 1859 \li Set reference clock (0x9000[15:13]) 1860 \li Set pll divider for VCO setting (0x9000[12, 11:8]). This is a function of max_speed. 1861 \li Port mode select single/dual/quad combo lane mode 1862 \li PMA/PMD mux/demux (lane swap) (0x9004[15:0]) 1863 \li Load Firmware. (In MDK/SDK this is done externally. The platform provides a 1864 method to load firmware. TEFMod cannot load firmware via MDIO.) 1865 */ 1866 1867 int tefmod_set_port_mode(PHYMOD_ST* pc, int refclk, int plldiv, tefmod_port_type_t port_type, int master_port, int tsc_clk_freq_pll_by_48, int pll_reset_en) 1868 { 1869 uint16_t dataref; 1870 MAIN0_SETUPr_t MAIN0_SETUPr_reg; 1871 1872 TEFMOD_DBG_IN_FUNC_INFO(pc); 1873 tefmod_update_port_mode_select(pc, port_type, master_port, tsc_clk_freq_pll_by_48, pll_reset_en); 1874 1875 switch(refclk) { 1876 case 25 : dataref=main0_refClkSelect_clk_25MHz; break; 1877 case 50 : dataref=main0_refClkSelect_clk_50Mhz; break; 1878 case 100: dataref=main0_refClkSelect_clk_100MHz; break; 1879 case 106: dataref=main0_refClkSelect_clk_106p25Mhz; break; 1880 case 125: dataref=main0_refClkSelect_clk_125MHz; break; 1881 case 156: dataref=main0_refClkSelect_clk_156p25MHz; break; 1882 case 161: dataref=main0_refClkSelect_clk_161p25Mhz; break; 1883 case 187: dataref=main0_refClkSelect_clk_187p5MHz; break; 1884 default : dataref=main0_refClkSelect_clk_156p25MHz; 1885 } 1886 1887 MAIN0_SETUPr_CLR(MAIN0_SETUPr_reg); 1888 1889 MAIN0_SETUPr_REFCLK_SELf_SET(MAIN0_SETUPr_reg, dataref); 1890 1891 switch(plldiv) { 1892 /* 1893 case 32 : datapll=MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_div32; break; 1894 case 36 : datapll=MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_div36; break; 1895 case 40 : datapll=MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_div40; break; 1896 case 42 : datapll=MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_div42; break; 1897 case 48 : datapll=MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_div48; break; 1898 case 50 : datapll=MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_div50; break; 1899 case 52 : datapll=MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_div52; break; 1900 case 54 : datapll=MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_div54; break; 1901 case 60 : datapll=MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_div60; break; 1902 case 64 : datapll=MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_div64; break; 1903 case 66 : datapll=MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_div66; break; 1904 case 68 : datapll=MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_div68; break; 1905 case 70 : datapll=MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_div70; break; 1906 case 80 : datapll=MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_div80; break; 1907 case 92 : datapll=MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_div92; break; 1908 case 100: datapll=MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_div100; break; 1909 default : datapll=MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_div40; 1910 */ 1911 } 1912 PHYMOD_IF_ERR_RETURN (MODIFY_MAIN0_SETUPr(pc, MAIN0_SETUPr_reg)); 1913 return PHYMOD_E_NONE; 1914 } /* tefmod_set_port_mode(PHYMOD_ST* pc) */ 1915 1916 #ifdef _DV_TB_ 1917 /*! 1918 @brief Sets the core for autoneg 1919 @param pc handle to current TSCF context (#PHYMOD_ST) 1920 @returns The value PHYMOD_E_NONE upon successful completion 1921 This function sets the tsc core for autoneg generic settings. 1922 If per_lane_control=TEFMOD_CTL_AN_CHIP_INIT(0x1) PLL and RX path are reset. 1923 If per_lane_control=TEFMOD_CTL_AN_MODE_INIT(0x2) PLL and RX path are not reset. 1924 */ 1925 int tefmod_set_an_port_mode(PHYMOD_ST* pc) /* SET_AN_PORT_MODE */ 1926 { 1927 int plldiv; /*, plldiv_r_val;*/ 1928 uint16_t data, ram_base; 1929 #ifdef _DV_TB_ 1930 uint16_t ignore_link_timer_period, tick_denominator, tick_numerator_lower; 1931 uint16_t tick_override, tick_numerator_upper; 1932 uint16_t tx_disable_timer_period, cl73_error_timer_period; 1933 uint16_t cl73_link_up_timer_period; 1934 uint16_t link_fail_inhibit_no_cl72_period ; 1935 uint16_t link_fail_inhibit_cl72_period ; 1936 #endif 1937 uint16_t cl82_dswin, cl48_dswin64b66b, cl48_dswin8b10b; 1938 uint16_t mld_swap_count, am_timer_init_rx_val; 1939 uint16_t single_port_mode; 1940 uint16_t ref_clk_sel; 1941 uint16_t new_port_mode_sel; 1942 uint16_t modify_port_mode; 1943 uint16_t port_mode_sel_reg; 1944 1945 MAIN0_SETUPr_t MAIN0_SETUPr_reg; 1946 AN_X1_IGNORE_LNK_TMRr_t AN_X1_TIMERS_IGNORE_LINK_TIMERr_reg; 1947 MAIN0_TICK_CTL0r_t MAIN0_TICK_CONTROL_0r_reg; 1948 MAIN0_TICK_CTL1r_t MAIN0_TICK_CONTROL_1r_reg; 1949 AN_X1_CL73_DME_LOCKr_t AN_X1_TIMERS_CL73_DME_LOCKr_reg; 1950 AN_X1_PD_SD_TMRr_t AN_X1_TIMERS_PD_SD_TIMERr_reg; 1951 AN_X1_CL73_BRK_LNKr_t AN_X1_TIMERS_CL73_BREAK_LINKr_reg; 1952 AN_X1_CL73_ERRr_t AN_X1_TIMERS_CL73_ERRORr_reg; 1953 AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72r_t AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_NOT_CL72r_reg; 1954 AN_X1_LNK_FAIL_INHBT_TMR_CL72r_t AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_CL72r_reg; 1955 RX_X1_DESKEW_WINSr_t RX_X1_CONTROL0_DESKEW_WINDOWSr_reg; 1956 TX_X2_MLD_SWP_CNTr_t TX_X2_CONTROL0_MLD_SWAP_COUNTr_reg; 1957 CL82_RX_AM_TMRr_t CL82_SHARED_CL82_RX_AM_TIMERr_reg; 1958 TX_X4_CRED0r_t TX_X4_CREDIT0_CREDIT0r_reg; 1959 1960 TEFMOD_DBG_IN_FUNC_INFO(pc); 1961 modify_port_mode = 0; 1962 1963 data = 0; 1964 ram_base = 0x0f00; 1965 #if defined (_DV_TB_) 1966 ignore_link_timer_period = 0xf; 1967 tick_denominator = 0x1; 1968 tick_numerator_lower = 0x0; 1969 tick_override = 0x1; 1970 tick_numerator_upper = 0x8; 1971 tx_disable_timer_period = 0x5; 1972 cl73_error_timer_period = 0x64; 1973 cl73_link_up_timer_period = 0x0; 1974 link_fail_inhibit_no_cl72_period = 0x64; 1975 link_fail_inhibit_cl72_period = 0xc8; 1976 #endif 1977 cl82_dswin = 0x11; 1978 cl48_dswin64b66b = 0x1; 1979 cl48_dswin8b10b = 0x7; 1980 mld_swap_count = 0xfffc; 1981 am_timer_init_rx_val = 0x3fff; 1982 single_port_mode = 0x0; 1983 ref_clk_sel = 0x0; 1984 1985 1986 1987 PHYMOD_IF_ERR_RETURN (READ_MAIN0_SETUPr(pc, &MAIN0_SETUPr_reg)); 1988 port_mode_sel_reg = MAIN0_SETUPr_PORT_MODE_SELf_GET(MAIN0_SETUPr_reg); 1989 1990 MAIN0_SETUPr_CLR(MAIN0_SETUPr_reg); 1991 1992 if ((pc-> an_type == TEFMOD_HPAM) | (pc-> an_type == TEFMOD_CL73_BAM)) { 1993 #if defined (_DV_TB_) 1994 cl73_error_timer_period = 0x64; 1995 #endif 1996 cl82_dswin = 0x1e; 1997 } 1998 1999 if ((pc-> an_type == TEFMOD_CL73) | (pc-> an_type == TEFMOD_HPAM) | 2000 (pc-> an_type == TEFMOD_CL73_BAM)) { 2001 2002 ref_clk_sel = main0_refClkSelect_clk_156p25MHz; 2003 if(pc->tsc_touched != 1) 2004 single_port_mode = 1; 2005 2006 plldiv = 66; 2007 } 2008 2009 if(pc->per_lane_control == TEFMOD_CTL_AN_CHIP_INIT) { 2010 MAIN0_SETUPr_REFCLK_SELf_SET(MAIN0_SETUPr_reg, ref_clk_sel); 2011 } 2012 MAIN0_SETUPr_SINGLE_PORT_MODEf_SET(MAIN0_SETUPr_reg, single_port_mode); 2013 2014 2015 if(port_mode_sel_reg == TEFMOD_DXGXS) { 2016 modify_port_mode = 1; 2017 if(pc->this_lane == 0) { 2018 new_port_mode_sel = TEFMOD_TRI1_PORT; 2019 } 2020 else if(pc->this_lane == 2) { 2021 new_port_mode_sel = TEFMOD_TRI2_PORT; 2022 } 2023 } 2024 if(port_mode_sel_reg == TEFMOD_TRI1_PORT) { 2025 if(pc->this_lane == 2) { 2026 modify_port_mode = 1; 2027 new_port_mode_sel = TEFMOD_MULTI_PORT; 2028 } 2029 } 2030 if(port_mode_sel_reg == TEFMOD_TRI2_PORT) { 2031 if(pc->this_lane == 0) { 2032 modify_port_mode = 1; 2033 new_port_mode_sel = TEFMOD_MULTI_PORT; 2034 } 2035 } 2036 if(port_mode_sel_reg == TEFMOD_SINGLE_PORT) { 2037 modify_port_mode = 1; 2038 new_port_mode_sel = TEFMOD_MULTI_PORT; 2039 } 2040 if(modify_port_mode == 1) { 2041 MAIN0_SETUPr_PORT_MODE_SELf_SET(MAIN0_SETUPr_reg, new_port_mode_sel); 2042 } 2043 2044 /*mask |= MAIN0_SETUP_PORT_MODE_SEL_MASK; */ 2045 2046 MAIN0_SETUPr_CL72_ENf_SET(MAIN0_SETUPr_reg, pc->cl72_en); 2047 2048 MAIN0_SETUPr_CL73_VCOf_SET(MAIN0_SETUPr_reg, pc->cl73_vco); 2049 2050 /* 0x9000 */ 2051 PHYMOD_IF_ERR_RETURN (MODIFY_MAIN0_SETUPr(pc, MAIN0_SETUPr_reg)); 2052 2053 pc->port_type = TEFMOD_MULTI_PORT; 2054 2055 /* XXXX: need to do sleep sal_usleep(1000); */ 2056 2057 #if defined (_DV_TB_) 2058 /* ignore_link_timer_period 0x925c */ 2059 if(pc->ignore_link_timer_period !=0) ignore_link_timer_period = pc->ignore_link_timer_period; 2060 AN_X1_IGNORE_LNK_TMRr_CLR(AN_X1_TIMERS_IGNORE_LINK_TIMERr_reg); 2061 AN_X1_IGNORE_LNK_TMRr_IGNORE_LINK_TIMER_PERIODf_SET(AN_X1_TIMERS_IGNORE_LINK_TIMERr_reg, ignore_link_timer_period); 2062 2063 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X1_IGNORE_LNK_TMRr(pc, AN_X1_TIMERS_IGNORE_LINK_TIMERr_reg)); 2064 #endif 2065 2066 2067 #if defined (_DV_TB_) 2068 /* set tick values 0x9008 x1 (only in sim) */ 2069 MAIN0_TICK_CTL0r_CLR(MAIN0_TICK_CONTROL_0r_reg); 2070 MAIN0_TICK_CTL0r_TICK_DENOMINATORf_SET(MAIN0_TICK_CONTROL_0r_reg, pc->tick_denominator); 2071 2072 MAIN0_TICK_CTL0r_TICK_NUMERATOR_LOWERf_SET(MAIN0_TICK_CONTROL_0r_reg, pc->tick_numerator_lower); 2073 2074 PHYMOD_IF_ERR_RETURN (MODIFY_MAIN0_TICK_CTL0r(pc, MAIN0_TICK_CONTROL_0r_reg)); 2075 2076 /* set tick values 0x9007 (only in sim) */ 2077 MAIN0_TICK_CTL1r_CLR(MAIN0_TICK_CONTROL_1r_reg); 2078 MAIN0_TICK_CTL1r_TICK_OVERRIDEf_SET(MAIN0_TICK_CONTROL_1r_reg, pc->tick_override); 2079 MAIN0_TICK_CTL1r_TICK_NUMERATOR_UPPERf_SET(MAIN0_TICK_CONTROL_1r_reg, pc->tick_numerator_upper); 2080 2081 PHYMOD_IF_ERR_RETURN (MODIFY_MAIN0_TICK_CTL1r(pc, MAIN0_TICK_CONTROL_1r_reg)); 2082 2083 /*TBD::0x9255 AN_X1_TIMERS_cl73_dme_lock*/ 2084 data = 100; 2085 AN_X1_CL73_DME_LOCKr_CLR(AN_X1_TIMERS_CL73_DME_LOCKr_reg); 2086 AN_X1_CL73_DME_LOCKr_SET(AN_X1_TIMERS_CL73_DME_LOCKr_reg, 100); 2087 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_CL73_DME_LOCKr(pc, AN_X1_TIMERS_CL73_DME_LOCKr_reg)); 2088 2089 /*TBD::0x9253 AN_X1_TIMERS_pd_sd_timer*/ 2090 data = 50; 2091 AN_X1_PD_SD_TMRr_CLR(AN_X1_TIMERS_PD_SD_TIMERr_reg); 2092 AN_X1_PD_SD_TMRr_SET(AN_X1_TIMERS_PD_SD_TIMERr_reg, 50); 2093 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_PD_SD_TMRr(pc, AN_X1_TIMERS_PD_SD_TIMERr_reg)); 2094 /* set cl73 break link timer values 0x9253 (only in sim) need a production value */ 2095 if(pc->tx_disable_timer_period !=0) tx_disable_timer_period = pc->tx_disable_timer_period; 2096 AN_X1_CL73_BRK_LNKr_CLR(AN_X1_TIMERS_CL73_BREAK_LINKr_reg); 2097 AN_X1_CL73_BRK_LNKr_CL73_BREAK_TIMER_PERIODf_SET(AN_X1_TIMERS_CL73_BREAK_LINKr_reg, tx_disable_timer_period); 2098 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X1_CL73_BRK_LNKr(pc, AN_X1_TIMERS_CL73_BREAK_LINKr_reg)); 2099 2100 2101 2102 /* set cl73 error timer period values 0x9254 write once per core (timeout timer) */ 2103 /*if(pc->cl73_error_timer_period !=0) cl73_error_timer_period = pc->cl73_error_timer_period;*/ 2104 AN_X1_CL73_ERRr_CLR(AN_X1_TIMERS_CL73_ERRORr_reg); 2105 AN_X1_CL73_ERRr_CL73_ERROR_TIMER_PERIODf_SET(AN_X1_TIMERS_CL73_ERRORr_reg, pc->cl73_error_timer_period); 2106 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X1_CL73_ERRr(pc, AN_X1_TIMERS_CL73_ERRORr_reg)); 2107 2108 /**** 0x9256*******/ 2109 if(pc->link_fail_inhibit_no_cl72_period !=0) link_fail_inhibit_no_cl72_period = pc->link_fail_inhibit_no_cl72_period; 2110 2111 AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72r_CLR(AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_NOT_CL72r_reg); 2112 AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72r_LINK_FAIL_INHIBIT_TIMER_NCL72_PERIODf_SET(AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_NOT_CL72r_reg, link_fail_inhibit_no_cl72_period); 2113 2114 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72r(pc, AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_NOT_CL72r_reg)); 2115 2116 /**** 0x9255*******/ 2117 if(pc->link_fail_inhibit_cl72_period !=0) link_fail_inhibit_cl72_period = pc->link_fail_inhibit_cl72_period; 2118 AN_X1_LNK_FAIL_INHBT_TMR_CL72r_CLR(AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_CL72r_reg); 2119 AN_X1_LNK_FAIL_INHBT_TMR_CL72r_LINK_FAIL_INHIBIT_TIMER_CL72_PERIODf_SET(AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_CL72r_reg, link_fail_inhibit_cl72_period); 2120 2121 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_LNK_FAIL_INHBT_TMR_CL72r(pc, AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_CL72r_reg)); 2122 #endif 2123 2124 /* --Addr=0x9222 ------------------------- */ 2125 RX_X1_DESKEW_WINSr_CLR(RX_X1_CONTROL0_DESKEW_WINDOWSr_reg); 2126 RX_X1_DESKEW_WINSr_CL82_DSWINf_SET(RX_X1_CONTROL0_DESKEW_WINDOWSr_reg, cl82_dswin); 2127 PHYMOD_IF_ERR_RETURN(MODIFY_RX_X1_DESKEW_WINSr(pc, RX_X1_CONTROL0_DESKEW_WINDOWSr_reg)); 2128 2129 /* MLD swap_count 0xa000 */ 2130 2131 #if defined (_DV_TB_) 2132 mld_swap_count = 0xffc; 2133 #else 2134 mld_swap_count = 0xfffc; 2135 #endif 2136 2137 TX_X2_MLD_SWP_CNTr_CLR(TX_X2_CONTROL0_MLD_SWAP_COUNTr_reg); 2138 TX_X2_MLD_SWP_CNTr_MLD_SWAP_COUNTf_SET(TX_X2_CONTROL0_MLD_SWAP_COUNTr_reg, mld_swap_count); 2139 2140 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X2_MLD_SWP_CNTr(pc, TX_X2_CONTROL0_MLD_SWAP_COUNTr_reg)); 2141 2142 /* cl82 shared rc_am_timer 0x9123 */ 2143 2144 #if defined (_DV_TB_) 2145 am_timer_init_rx_val = 0x3ff; 2146 #else 2147 am_timer_init_rx_val = 0x3fff; 2148 #endif 2149 2150 CL82_RX_AM_TMRr_CLR(CL82_SHARED_CL82_RX_AM_TIMERr_reg); 2151 CL82_RX_AM_TMRr_AM_TIMER_INIT_RX_VALf_SET(CL82_SHARED_CL82_RX_AM_TIMERr_reg, am_timer_init_rx_val); 2152 2153 PHYMOD_IF_ERR_RETURN(MODIFY_CL82_RX_AM_TMRr(pc, CL82_SHARED_CL82_RX_AM_TIMERr_reg)); 2154 2155 /* clear credtis 0xc100, 0xc104 */ 2156 TX_X4_CRED0r_CLR(TX_X4_CREDIT0_CREDIT0r_reg); 2157 TX_X4_CRED0r_SET(TX_X4_CREDIT0_CREDIT0r_reg, 0); 2158 PHYMOD_IF_ERR_RETURN (MODIFY_TX_X4_CRED0r(pc, TX_X4_CREDIT0_CREDIT0r_reg)); 2159 2160 return PHYMOD_E_NONE; 2161 } /* tefmod_set_an_port_mode(PHYMOD_ST* pc) */ 2162 #endif 2163 2164 /*! 2165 @brief Sets loopback mode from Tx to Rx at PCS/PMS parallel interface. (gloop). 2166 @param pc handle to current TSCF context (#PHYMOD_ST) 2167 @param pcs_gloop_en Enable or disable PCS loopback. 2168 @param starting_lane first of multiple lanes if in multi lane ports 2169 @param num_lanes Number of lanes to configure if in multi lane ports 2170 @returns The value PHYMOD_E_NONE upon successful completion 2171 @details 2172 This function sets the TX-to-RX digital loopback mode, which is set 2173 independently for each lane at the PCS/PMS parallel interface. If the port in 2174 question contains multiple lanes we specify the starting and the lane count and 2175 all those lanes are configured to loopback mode 2176 2177 The 1st, 2nd, 3rd and 4th byte of 'lane' input arg. is associated with lanes 0, 2178 1, 2, and 3 respectively. The bits of each byte control their lanes as follows. 2179 2180 \li 0:1 : Enable TX->RX loopback 2181 \li 0:0 : Disable TX-RX loopback 2182 2183 Note that this function can program <B>multiple lanes simultaneously</B>. 2184 As an example, to enable gloop on all lanes and enable TX on lane 0 only, 2185 set lane to 0x01010103 2186 */ 2187 2188 int tefmod_tx_loopback_control(PHYMOD_ST* pc, int pcs_gloop_en, int starting_lane, int num_lanes) /* TX_LOOPBACK_CONTROL */ 2189 { 2190 MAIN0_LPBK_CTLr_t MAIN0_LOOPBACK_CONTROLr_reg; 2191 PMD_X4_OVRRr_t PMD_X4_OVERRIDEr_reg; 2192 PMD_X4_CTLr_t PMD_X4_PMD_X4_CONTROLr_reg; 2193 uint16_t lane_mask, i, data, tmp_data; 2194 phymod_access_t pa_copy; 2195 2196 PHYMOD_MEMCPY(&pa_copy, pc, sizeof(pa_copy)); 2197 pa_copy.lane_mask = 0x1 << starting_lane; 2198 2199 TEFMOD_DBG_IN_FUNC_INFO(pc); 2200 MAIN0_LPBK_CTLr_CLR(MAIN0_LOOPBACK_CONTROLr_reg); 2201 READ_MAIN0_LPBK_CTLr(pc, &MAIN0_LOOPBACK_CONTROLr_reg); 2202 tmp_data = MAIN0_LPBK_CTLr_LOCAL_PCS_LOOPBACK_ENABLEf_GET(MAIN0_LOOPBACK_CONTROLr_reg); 2203 2204 lane_mask = 0; 2205 data = 0; 2206 2207 for (i = 0; i < num_lanes; i++) { 2208 if (!PHYMOD_LANEPBMP_MEMBER(pc->lane_mask, starting_lane + i)) { 2209 continue; 2210 } 2211 lane_mask |= 1 << (starting_lane + i); 2212 data |= pcs_gloop_en << (starting_lane + i); 2213 } 2214 2215 tmp_data &= ~lane_mask; 2216 tmp_data |= data; 2217 2218 MAIN0_LPBK_CTLr_LOCAL_PCS_LOOPBACK_ENABLEf_SET(MAIN0_LOOPBACK_CONTROLr_reg, tmp_data); 2219 PHYMOD_IF_ERR_RETURN(MODIFY_MAIN0_LPBK_CTLr(pc, MAIN0_LOOPBACK_CONTROLr_reg)); 2220 2221 /* signal_detect and rx_lock */ 2222 PMD_X4_OVRRr_CLR(PMD_X4_OVERRIDEr_reg); 2223 if (pcs_gloop_en) { 2224 PMD_X4_OVRRr_RX_LOCK_OVRDf_SET(PMD_X4_OVERRIDEr_reg, 1); 2225 PMD_X4_OVRRr_SIGNAL_DETECT_OVRDf_SET(PMD_X4_OVERRIDEr_reg, 1); 2226 PMD_X4_OVRRr_TX_DISABLE_OENf_SET(PMD_X4_OVERRIDEr_reg, 1); 2227 } else { 2228 PMD_X4_OVRRr_RX_LOCK_OVRDf_SET(PMD_X4_OVERRIDEr_reg, 0); 2229 PMD_X4_OVRRr_SIGNAL_DETECT_OVRDf_SET(PMD_X4_OVERRIDEr_reg, 0); 2230 PMD_X4_OVRRr_TX_DISABLE_OENf_SET(PMD_X4_OVERRIDEr_reg, 0); 2231 } 2232 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X4_OVRRr(pc, PMD_X4_OVERRIDEr_reg)); 2233 2234 /* set tx_disable */ 2235 PMD_X4_CTLr_CLR(PMD_X4_PMD_X4_CONTROLr_reg); 2236 PMD_X4_CTLr_TX_DISABLEf_SET(PMD_X4_PMD_X4_CONTROLr_reg, 1); 2237 2238 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X4_CTLr(pc, PMD_X4_PMD_X4_CONTROLr_reg)); 2239 /* PHYMOD_IF_ERR_RETURN(tefmod_rx_lane_control_set(pc, 1)); */ 2240 2241 /* trigger speed change */ 2242 tefmod_trigger_speed_change(&pa_copy); 2243 2244 return PHYMOD_E_NONE; 2245 } /* tefmod_tx_loopback_control */ 2246 2247 #ifdef _DV_TB_ 2248 /*! 2249 @brief Sets loopback mode from Tx to Rx at PCS/PMS parallel interface. (gloop). 2250 @param pc handle to current TSCF context (#PHYMOD_ST) 2251 @returns The value PHYMOD_E_NONE upon successful completion 2252 @details 2253 This function sets the TX-to-RX digital loopback mode, which is set 2254 independently for each lane at the PCS/PMS parallel interface. 2255 2256 The 1st, 2nd, 3rd and 4th byte of 'lane' is associated with lanes 0, 1, 2, and 3 2257 respectively. The bits of each byte control their lanes as follows. 2258 2259 \li 0:1 : Enable TX->RX loopback 2260 \li 0:0 : Disable TX-RX loopback 2261 2262 Note that this function can program <B>multiple lanes simultaneously</B>. As an 2263 example, to enable gloop on all lanes and enable TX on lane 0 only, set 'lane' 2264 to 0x01010103 2265 */ 2266 int tefmod_tx_pmd_loopback_control(PHYMOD_ST* pc, int pmd_gloop_en) /* TX_PMD_LOOPBACK_CONTROL */ 2267 { 2268 int cntl; 2269 TLB_RX_DIG_LPBK_CFGr_t TLB_RX_DIG_LPBK_CFGr_reg; 2270 TXFIR_UC_CTL0r_t TXFIR_UC_CTL0r_reg; 2271 2272 TEFMOD_DBG_IN_FUNC_INFO(pc); 2273 TLB_RX_DIG_LPBK_CFGr_CLR(TLB_RX_DIG_LPBK_CFGr_reg); 2274 TXFIR_UC_CTL0r_CLR(TXFIR_UC_CTL0r_reg); 2275 2276 cntl = (pmd_gloop_en); 2277 if (cntl) { 2278 TLB_RX_DIG_LPBK_CFGr_DIG_LPBK_ENf_SET(TLB_RX_DIG_LPBK_CFGr_reg, 1); 2279 } else { 2280 TLB_RX_DIG_LPBK_CFGr_DIG_LPBK_ENf_SET(TLB_RX_DIG_LPBK_CFGr_reg, 0); 2281 } 2282 PHYMOD_IF_ERR_RETURN(MODIFY_TLB_RX_DIG_LPBK_CFGr(pc, TLB_RX_DIG_LPBK_CFGr_reg)); 2283 2284 if (cntl) { 2285 TXFIR_UC_CTL0r_MICRO_TX_DISABLEf_SET(TXFIR_UC_CTL0r_reg, 1); 2286 } else { 2287 TXFIR_UC_CTL0r_MICRO_TX_DISABLEf_SET(TXFIR_UC_CTL0r_reg, 0); 2288 } 2289 PHYMOD_IF_ERR_RETURN(MODIFY_TXFIR_UC_CTL0r(pc, TXFIR_UC_CTL0r_reg)); 2290 2291 return PHYMOD_E_NONE; 2292 } /* tefmod_tx_pmd_loopback_control */ 2293 #endif 2294 2295 /*! 2296 @brief Set remote loopback mode for GMII, cl49, aggregate(XAUI) and R2 modes. 2297 @param pc handle to current TSCF context (#PHYMOD_ST) 2298 @param pcs_rloop_en controls rloop enable or disable 2299 @returns The value PHYMOD_E_NONE upon successful completion 2300 @details 2301 This function sets the remote loopback (RX-to-TX) mode for one lane at a time, 2302 where the lane is indicated by the field. To enable remote loopback, set 2303 pcs_rloop_en to 1; to disable remote loopback, set the it to 0. 2304 */ 2305 2306 int tefmod_rx_loopback_control(PHYMOD_ST* pc, int pcs_rloop_en) 2307 { 2308 MAIN0_LPBK_CTLr_t MAIN0_LOOPBACK_CONTROLr_reg; 2309 DSC_CDR_CTL2r_t DSC_C_CDR_CONTROL_2r_reg; 2310 TX_PI_PMD_CTL0r_t TX_PI_PMD_COM_TX_PI_PMD_COM_CONTROL_0r_reg; 2311 TEFMOD_DBG_IN_FUNC_INFO(pc); 2312 /* remote device is set in rloop */ 2313 #ifdef _DV_TB_ 2314 if ((pc->unit) == 2) { 2315 #endif 2316 MAIN0_LPBK_CTLr_CLR(MAIN0_LOOPBACK_CONTROLr_reg); 2317 MAIN0_LPBK_CTLr_REMOTE_PCS_LOOPBACK_ENABLEf_SET(MAIN0_LOOPBACK_CONTROLr_reg, pcs_rloop_en); 2318 PHYMOD_IF_ERR_RETURN(MODIFY_MAIN0_LPBK_CTLr(pc, MAIN0_LOOPBACK_CONTROLr_reg)); 2319 2320 /* set Tx_PI */ 2321 DSC_CDR_CTL2r_CLR(DSC_C_CDR_CONTROL_2r_reg); 2322 DSC_CDR_CTL2r_TX_PI_LOOP_TIMING_SRC_SELf_SET(DSC_C_CDR_CONTROL_2r_reg, 1); 2323 2324 PHYMOD_IF_ERR_RETURN(MODIFY_DSC_CDR_CTL2r(pc, DSC_C_CDR_CONTROL_2r_reg)); 2325 2326 TX_PI_PMD_CTL0r_CLR(TX_PI_PMD_COM_TX_PI_PMD_COM_CONTROL_0r_reg); 2327 TX_PI_PMD_CTL0r_TX_PI_ENf_SET(TX_PI_PMD_COM_TX_PI_PMD_COM_CONTROL_0r_reg,1); 2328 2329 PHYMOD_IF_ERR_RETURN(MODIFY_TX_PI_PMD_CTL0r(pc, TX_PI_PMD_COM_TX_PI_PMD_COM_CONTROL_0r_reg)); 2330 #ifdef _DV_TB_ 2331 } 2332 #endif 2333 return PHYMOD_E_NONE; 2334 } /* tefmod_rx_loopback_control */ 2335 2336 int tefmod_tx_loopback_get(PHYMOD_ST* pc, uint32_t *enable) /* TX_LOOPBACK_get */ 2337 { 2338 MAIN0_LPBK_CTLr_t loopReg; 2339 READ_MAIN0_LPBK_CTLr(pc, &loopReg); 2340 *enable = MAIN0_LPBK_CTLr_LOCAL_PCS_LOOPBACK_ENABLEf_GET(loopReg); 2341 2342 return PHYMOD_E_NONE; 2343 } 2344 2345 2346 /** 2347 @brief PMD per lane reset 2348 @param pc handle to current TSCF context (#PHYMOD_ST) 2349 @returns The value PHYMOD_E_NONE upon successful completion 2350 @details Per lane PMD ln_rst and ln_dp_rst by writing to PMD_X4_CONTROL in pcs space 2351 */ 2352 int tefmod_pmd_x4_reset(PHYMOD_ST* pc) /* PMD_X4_RESET */ 2353 { 2354 PMD_X4_CTLr_t reg_pmd_x4_ctrl; 2355 2356 TEFMOD_DBG_IN_FUNC_INFO(pc); 2357 PMD_X4_CTLr_CLR(reg_pmd_x4_ctrl); 2358 PMD_X4_CTLr_LN_H_RSTBf_SET(reg_pmd_x4_ctrl,0); 2359 PMD_X4_CTLr_LN_DP_H_RSTBf_SET(reg_pmd_x4_ctrl,0); 2360 PHYMOD_IF_ERR_RETURN (MODIFY_PMD_X4_CTLr(pc, reg_pmd_x4_ctrl)); 2361 2362 PMD_X4_CTLr_CLR(reg_pmd_x4_ctrl); 2363 PMD_X4_CTLr_LN_H_RSTBf_SET(reg_pmd_x4_ctrl,1); 2364 PMD_X4_CTLr_LN_DP_H_RSTBf_SET(reg_pmd_x4_ctrl,1); 2365 PHYMOD_IF_ERR_RETURN (MODIFY_PMD_X4_CTLr(pc, reg_pmd_x4_ctrl)); 2366 2367 return PHYMOD_E_NONE; 2368 } 2369 2370 /** 2371 @brief PMD per lane reset get 2372 @param pc handle to current TSCF context (#PHYMOD_ST) 2373 @returns The value PHYMOD_E_NONE upon successful completion 2374 @details Per lane PMD ln_rst and ln_dp_rst by writing to PMD_X4_CONTROL in pcs space 2375 */ 2376 int tefmod_pmd_x4_reset_get(PHYMOD_ST* pc, int *is_in_reset) /* PMD_X4_RESET */ 2377 { 2378 PMD_X4_CTLr_t reg_pmd_x4_ctrl; 2379 2380 2381 TEFMOD_DBG_IN_FUNC_INFO(pc); 2382 PMD_X4_CTLr_CLR(reg_pmd_x4_ctrl); 2383 PHYMOD_IF_ERR_RETURN (READ_PMD_X4_CTLr(pc, ®_pmd_x4_ctrl)); 2384 2385 if(PMD_X4_CTLr_LN_H_RSTBf_GET(reg_pmd_x4_ctrl) && 2386 PMD_X4_CTLr_LN_DP_H_RSTBf_GET(reg_pmd_x4_ctrl)) { 2387 *is_in_reset = 0 ; 2388 } else { 2389 *is_in_reset = 1 ; 2390 } 2391 return PHYMOD_E_NONE; 2392 2393 return PHYMOD_E_NONE; 2394 } 2395 2396 2397 /** 2398 @brief Set Per lane OS mode set in PMD 2399 @param pc handle to current TSCF context (#PHYMOD_ST) 2400 @param spd_intf speed type #tefmod_spd_intfc_type_t 2401 @param os_mode over sample rate. 2402 @returns The value PHYMOD_E_NONE upon successful completion 2403 @details Per Port PMD Init 2404 2405 */ 2406 int tefmod_pmd_osmode_set(PHYMOD_ST* pc, tefmod_spd_intfc_type_t spd_intf, phymod_ref_clk_t refclk, int os_mode) /* INIT_PMD */ 2407 { 2408 CKRST_OSR_MODE_CTLr_t reg_osr_mode; 2409 int speed; 2410 phymod_access_t pa_copy; 2411 int i, start_lane = 0, num_lane = 0; 2412 uint32_t lane_mask; 2413 2414 TEFMOD_DBG_IN_FUNC_INFO(pc); 2415 PHYMOD_MEMCPY(&pa_copy, pc, sizeof(pa_copy)); 2416 PHYMOD_IF_ERR_RETURN 2417 (phymod_util_lane_config_get(pc, &start_lane, &num_lane)); 2418 2419 lane_mask = pa_copy.lane_mask; 2420 2421 CKRST_OSR_MODE_CTLr_CLR(reg_osr_mode); 2422 tefmod_get_mapped_speed(spd_intf, &speed); 2423 2424 /*os_mode = 0x0; */ /* 0= OS MODE 1; 1= OS MODE 2; 2=OS MODE 3; 2425 3=OS MODE 3.3; 4=OS MODE 4; 5=OS MODE 5; 2426 6=OS MODE 8; 7=OS MODE 8.25; 8: OS MODE 10*/ 2427 if(os_mode & 0x80000000) { 2428 os_mode = (os_mode) & 0x0000ffff; 2429 } 2430 else { 2431 if (refclk == phymodRefClk125Mhz) { 2432 os_mode = sc_pmd_entry_125M_ref[speed].t_pma_os_mode; 2433 } else { 2434 os_mode = sc_pmd_entry[speed].t_pma_os_mode; 2435 } 2436 } 2437 2438 CKRST_OSR_MODE_CTLr_OSR_MODE_FRCf_SET(reg_osr_mode, 1); 2439 CKRST_OSR_MODE_CTLr_OSR_MODE_FRC_VALf_SET(reg_osr_mode, os_mode); 2440 2441 for (i = 0; i < num_lane; i++) { 2442 if (!PHYMOD_LANEPBMP_MEMBER(lane_mask, start_lane + i)) { 2443 continue; 2444 } 2445 pa_copy.lane_mask = 0x1 << (i + start_lane); 2446 2447 PHYMOD_IF_ERR_RETURN 2448 (MODIFY_CKRST_OSR_MODE_CTLr(&pa_copy, reg_osr_mode)); 2449 } 2450 2451 return PHYMOD_E_NONE; 2452 } 2453 2454 2455 #ifdef _DV_TB_ 2456 /*! 2457 @brief Set remote loopback mode for GMII, cl49, aggregate(XAUI) and R2 modes. 2458 @param pc handle to current TSCF context (#PHYMOD_ST) 2459 @returns The value PHYMOD_E_NONE upon successful completion 2460 @details 2461 This function sets the remote loopback (RX-to-TX) mode for one lane at a time, 2462 where the lane is indicated by the lane field. To enable remote loopback, set 2463 the field #PHYMOD_ST::en_dis to 1; to disable remote loopback, set pmd_rloop_en 2464 to 0. 2465 2466 Note that the speed field PHYMOD_ST::spd_intf must be set prior to calling this 2467 function because the loopback register and path are speed/interface dependent. 2468 2469 The first two bits of #PHYMOD_ST::per_lane_control decide for PCS pr PMD. After 2470 right shifting the first two bits of #PHYMOD_ST::per_lane_control the 1st, 2nd, 2471 3rd and 4th byte is associated with lanes 0, 1, 2, and 3 respectively. 2472 2473 The bits of each byte control their lanes as follows. !! Also 1st byte decides 2474 it is for PCS or PMD remote loopback. 2475 2476 \li 0:0 : Enable PMD Loopback (rloop) 2477 \li 0:1 : Enable PCS Loopback (rloop) 2478 \li 1:1 : Enable loopback 2479 \li 1:0 : Disable loopback 2480 2481 The function modifies the following registers: 2482 \li 0x9009 (MAIN0_LPBK_CTLr) 2483 \li bit 15:12 for REMOTE_PCS_LOOPBACK_ENABLE 2484 \li bit 11:08 for REMOTE_PMD_LOOPBACK_ENABLE 2485 */ 2486 2487 int tefmod_rx_pmd_loopback_control(PHYMOD_ST* pc, int pcs_rloop_en, int pmd_rloop_en, int lane) 2488 { 2489 uint16_t data; 2490 int cntl; 2491 TLB_TX_RMT_LPBK_CFGr_t TLB_TX_RMT_LPBK_CONFIGr_reg; 2492 DSC_CDR_CTL2r_t DSC_C_CDR_CONTROL_2r_reg; 2493 TX_PI_PMD_CTL0r_t TX_PI_PMD_COM_TX_PI_PMD_COM_CONTROL_0r_reg; 2494 2495 TEFMOD_DBG_IN_FUNC_INFO(pc); 2496 data = 0; 2497 2498 /* remote pmd device is set in rloop */ 2499 2500 #ifdef _DV_TB_ 2501 if ((pc->unit) == 2) { 2502 #endif 2503 cntl = (((pmd_rloop_en) >> lane) & 0x1); 2504 TLB_TX_RMT_LPBK_CFGr_CLR(TLB_TX_RMT_LPBK_CONFIGr_reg); 2505 if (cntl) { 2506 TLB_TX_RMT_LPBK_CFGr_RMT_LPBK_ENf_SET(TLB_TX_RMT_LPBK_CONFIGr_reg, 1); 2507 } else { 2508 TLB_TX_RMT_LPBK_CFGr_RMT_LPBK_ENf_SET(TLB_TX_RMT_LPBK_CONFIGr_reg, 0); 2509 } 2510 2511 PHYMOD_IF_ERR_RETURN (MODIFY_TLB_TX_RMT_LPBK_CFGr(pc, TLB_TX_RMT_LPBK_CONFIGr_reg)); 2512 2513 /* set Tx_PI */ 2514 2515 DSC_CDR_CTL2r_CLR(DSC_C_CDR_CONTROL_2r_reg); 2516 DSC_CDR_CTL2r_TX_PI_LOOP_TIMING_SRC_SELf_SET(DSC_C_CDR_CONTROL_2r_reg, 1); 2517 2518 PHYMOD_IF_ERR_RETURN(MODIFY_DSC_CDR_CTL2r(pc, DSC_C_CDR_CONTROL_2r_reg)); 2519 2520 TX_PI_PMD_CTL0r_CLR(TX_PI_PMD_COM_TX_PI_PMD_COM_CONTROL_0r_reg); 2521 TX_PI_PMD_CTL0r_TX_PI_ENf_SET(TX_PI_PMD_COM_TX_PI_PMD_COM_CONTROL_0r_reg, 1); 2522 2523 PHYMOD_IF_ERR_RETURN(MODIFY_TX_PI_PMD_CTL0r(pc, TX_PI_PMD_COM_TX_PI_PMD_COM_CONTROL_0r_reg)); 2524 #ifdef _DV_TB_ 2525 } else { 2526 2527 } 2528 #endif 2529 return PHYMOD_E_NONE; 2530 } /* tefmod_rx_pmd_loopback_control */ 2531 #endif 2532 2533 #ifdef _DV_TB_ 2534 /*! 2535 @brief Control resetting/setting of credits based on speed interface selection 2536 @param pc handle to current TSCF context (#PHYMOD_ST) 2537 @returns The value PHYMOD_E_NONE upon successful completion. 2538 @details 2539 2540 This function sets/resets all credits for PCS and MAC as per speed interface 2541 selected. Set #PHYMOD_ST::per_lane_control to 1 to set the credits and set it 2542 to 0 to clear the credits. 2543 2544 This function is controlled by the following register bit: 2545 2546 \li set credits: clockcnt0 (0xC100[13:0]) 2547 \li clockcnt1 (0xC101[7:0]) 2548 \li loopcnt0 (0xC102[13:6]), loopcnt1 (0xC102[5:0]) 2549 \li mac_creditgencnt (0xC103[12:0]) 2550 \li pcs_clockcnt0 (0xC104[13:0]) 2551 \li pcs_creditgencnt (0xC105[12:0]) 2552 2553 */ 2554 2555 int tefmod_credit_set(PHYMOD_ST* pc) /* CREDIT_SET */ 2556 { 2557 uint16_t data_loopcnt; 2558 uint16_t data_mac_credit; 2559 uint16_t clockcnt0, clockcnt1, loopcnt0, loopcnt1, mac_credit; 2560 2561 TX_X4_CRED0r_t TX_X4_CREDIT0_CREDIT0r_reg; 2562 TX_X4_CRED1r_t TX_X4_CREDIT0_CREDIT1r_reg; 2563 TX_X4_LOOPCNTr_t TX_X4_CREDIT0_LOOPCNTr_reg; 2564 TX_X4_MAC_CREDGENCNTr_t TX_X4_CREDIT0_MAC_CREDITGENCNTr_reg; 2565 /* uint16_t data_sgmii_spd_switch; */ 2566 int cntl; 2567 2568 TEFMOD_DBG_IN_FUNC_INFO(pc); 2569 /*dv_tfmod_update_st(pc);*/ 2570 cntl = pc->per_lane_control; 2571 /* data_sgmii_spd_switch = 0; */ 2572 data_loopcnt = 0; 2573 data_mac_credit = 0; 2574 clockcnt0 = 0; 2575 clockcnt1 = 0; 2576 loopcnt0 = 1; 2577 loopcnt1 = 0; 2578 mac_credit = 0; 2579 2580 if (cntl) { 2581 if (pc->spd_intf == TEFMOD_SPD_1000_SGMII) { 2582 2583 } else if ((pc->spd_intf == TEFMOD_SPD_10000_XFI)|| 2584 (pc->spd_intf == TEFMOD_SPD_10600_XFI_HG)) { 2585 clockcnt0 = 9; 2586 clockcnt1 = 10; 2587 loopcnt0 = 1; 2588 loopcnt1 = 9; 2589 mac_credit = 6; 2590 2591 } else if ((pc->spd_intf == TEFMOD_SPD_20000_XFI) || 2592 (pc->spd_intf == TEFMOD_SPD_21200_XFI_HG) || 2593 (pc->spd_intf == TEFMOD_SPD_25000_XFI) || 2594 (pc->spd_intf == TEFMOD_SPD_26500_XFI_HG)) { 2595 clockcnt0 = 9; 2596 clockcnt1 = 5; 2597 loopcnt0 = 1; 2598 loopcnt1 = 18; 2599 mac_credit = 4; 2600 2601 } else if ((pc->spd_intf == TEFMOD_SPD_20G_MLD_X2) || 2602 (pc->spd_intf == TEFMOD_SPD_21G_MLD_HG_X2)) { 2603 clockcnt0 = 9; 2604 clockcnt1 = 5; 2605 loopcnt0 = 1; 2606 loopcnt1 = 18; 2607 mac_credit = 4; 2608 2609 } else if ((pc->spd_intf == TEFMOD_SPD_40G_MLD_X2) || 2610 (pc->spd_intf == TEFMOD_SPD_42G_MLD_HG_X2) || 2611 (pc->spd_intf == TEFMOD_SPD_50G_MLD_X2) || 2612 (pc->spd_intf == TEFMOD_SPD_53G_MLD_HG_X2) || 2613 (pc->spd_intf == TEFMOD_SPD_40G_MLD_X4) || 2614 (pc->spd_intf == TEFMOD_SPD_42G_MLD_HG_X4) || 2615 (pc->spd_intf == TEFMOD_SPD_50G_MLD_X4) || 2616 (pc->spd_intf == TEFMOD_SPD_53G_MLD_HG_X4) ) { 2617 clockcnt0 = 9; 2618 clockcnt1 = 5; 2619 loopcnt0 = 1; 2620 loopcnt1 = 18; 2621 mac_credit = 2; 2622 2623 } else if ((pc->spd_intf == TEFMOD_SPD_100G_MLD_X4) || 2624 (pc->spd_intf == TEFMOD_SPD_106G_MLD_HG_X4)) { 2625 clockcnt0 = 9; 2626 clockcnt1 = 5; 2627 loopcnt0 = 1; 2628 loopcnt1 = 18; 2629 mac_credit = 1; 2630 2631 } else { 2632 PHYMOD_DEBUG_ERROR(("%-22s ERROR: p=%0d spd_intf=%d undefined %s cntl=%0x verb=%x\n", 2633 __func__, pc->port, pc->spd_intf, 2634 e2s_tefmod_spd_intfc_type_t[pc->spd_intf], cntl, pc->verbosity)); 2635 return PHYMOD_E_FAIL; 2636 } 2637 /* set credtis 0xc100 */ 2638 TX_X4_CRED0r_CLR(TX_X4_CREDIT0_CREDIT0r_reg); 2639 TX_X4_CRED0r_CLOCKCNT0f_SET(TX_X4_CREDIT0_CREDIT0r_reg, clockcnt0); 2640 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_CRED0r(pc, TX_X4_CREDIT0_CREDIT0r_reg)); 2641 2642 /* 0xc101 */ 2643 TX_X4_CRED1r_CLR(TX_X4_CREDIT0_CREDIT1r_reg); 2644 TX_X4_CRED1r_CLOCKCNT1f_SET(TX_X4_CREDIT0_CREDIT1r_reg, clockcnt1); 2645 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_CRED1r(pc, TX_X4_CREDIT0_CREDIT1r_reg)); 2646 2647 /* 0xc102 */ 2648 TX_X4_LOOPCNTr_CLR(TX_X4_CREDIT0_LOOPCNTr_reg); 2649 TX_X4_LOOPCNTr_LOOPCNT0f_SET(TX_X4_CREDIT0_LOOPCNTr_reg, loopcnt0); 2650 TX_X4_LOOPCNTr_LOOPCNT1f_SET(TX_X4_CREDIT0_LOOPCNTr_reg, loopcnt1); 2651 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_LOOPCNTr(pc, TX_X4_CREDIT0_LOOPCNTr_reg)); 2652 2653 /* 0xc103 */ 2654 TX_X4_MAC_CREDGENCNTr_CLR(TX_X4_CREDIT0_MAC_CREDITGENCNTr_reg); 2655 TX_X4_MAC_CREDGENCNTr_MAC_CREDITGENCNTf_SET(TX_X4_CREDIT0_MAC_CREDITGENCNTr_reg, mac_credit); 2656 PHYMOD_IF_ERR_RETURN 2657 (MODIFY_TX_X4_MAC_CREDGENCNTr(pc, TX_X4_CREDIT0_MAC_CREDITGENCNTr_reg)); 2658 } else { 2659 /* clear credits */ 2660 TX_X4_CRED0r_CLR(TX_X4_CREDIT0_CREDIT0r_reg); 2661 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_CRED0r(pc, TX_X4_CREDIT0_CREDIT0r_reg)); 2662 } 2663 return PHYMOD_E_NONE; 2664 } /* CREDIT_SET */ 2665 #endif 2666 2667 #ifdef _DV_TB_ 2668 /*! 2669 @brief set tx encoder of any particular lane 2670 @param pc handle to current TSCF context (#PHYMOD_ST) 2671 @returns The value PHYMOD_E_NONE upon successful completion. 2672 @details 2673 This function is used to select encoder of any transmit lane. 2674 2675 \li select encodeMode 2676 2677 This function reads/modifies the following registers: 2678 \li Address (Name) 2679 \li 0xc111 (TX_X4_ENC0) 2680 \i field bit position variable defined in this function 2681 \li ENCODEMODE [4:2] encode_mode 2682 \li CL49_BYPASS_TXSM [9] - 2683 \li 2684 \li 0xc113 (TX_X4_MISC) 2685 \li SCR_MODE [15:14] scr_mode 2686 \li RESERVED0 [13:11] block_sync_mode 2687 \li CL49_TX_LI_ENABLE [8] - 2688 \li CL49_TX_LF_ENABLE [7] - 2689 \li CL49_TX_RF_ENABLE [6] - 2690 \li 2691 \li 0xa000 (TX_X2_MLD_SWP_CNT) 2692 \li MLD_SWAP_COUNT [15:0] - 2693 2694 <B> ENCODE_SET Progamming values 2695 \li 10G_XFI 2696 \li encodeMode : 5 2697 \li scr_mode : 3 2698 \li 2699 \li 10G_XAUI 2700 \li encode_mode : 0x1 cl48 8b10b 2701 \li CL49_BYPASS_TXSM : 0 2702 \li scr_mode : 0x0 bypass scramble 2703 \li 2704 \li 40G_MLD 2705 */ 2706 2707 /* for DV only ? CHECK Lpti */ 2708 int tefmod_encode_set(PHYMOD_ST* pc, int per_lane_control, tefmod_spd_intfc_type_t spd_intf, int tx_am_timer_init_val) /* ENCODE_SET */ 2709 { 2710 uint16_t encode_mode, hg2_message_invalid_code_enable, hg2_codec; 2711 uint16_t disable_packet_misalign; 2712 uint16_t mld_swap_count, mld_swap_en; 2713 uint16_t t_pma_btmx_mode, scr_mode, os_mode, hg2_en, t_fifo_mode, t_enc_mode; 2714 uint16_t cl82_bypass_txsm, cl49_tx_tl_mode, cl49_bypass_txsm; 2715 uint16_t data, mask; 2716 int cntl; 2717 TX_X1_T_PMA_WTRMKr_t TX_X1_CONTROL0_T_PMA_WATERMARKr_reg; 2718 TX_X2_CL82_0r_t TX_X2_CONTROL0_CL82_0r_reg; 2719 TX_X4_ENC0r_t TX_X4_CONTROL0_ENCODE_0r_reg; 2720 TX_X4_MISCr_t TX_X4_CONTROL0_MISCr_reg; 2721 TX_X2_MLD_SWP_CNTr_t TX_X2_CONTROL0_MLD_SWAP_COUNTr_reg; 2722 2723 TEFMOD_DBG_IN_FUNC_INFO(pc); 2724 cntl = per_lane_control; 2725 data = 0; mask = 0 ; 2726 2727 encode_mode = 0; 2728 cl49_bypass_txsm = 0; 2729 hg2_message_invalid_code_enable = 0; 2730 hg2_en = 0; /* 001 cl48 8b10b 2731 010 cl48 8b10b rxaui 2732 011 cl36 8b10b 2733 100 cl82 64b66b 2734 101 cl49 64b66b 2735 110 brcm 64b66b */ 2736 hg2_codec = 0; 2737 scr_mode = 0; /* 00 bypass scrambler 2738 01 64b66b scrambler (all 66 bits) 2739 10 8b10b scrambler (all 80 bits) 2740 11 64b66b scrambler (sync bits not scrambled)*/ 2741 t_pma_btmx_mode = 0; 2742 t_fifo_mode = 0; 2743 t_enc_mode = 0; 2744 cl82_bypass_txsm = 0; 2745 cl49_tx_tl_mode = 0; 2746 cl49_bypass_txsm = 0; 2747 2748 mld_swap_count = 0; 2749 mld_swap_en = 0; 2750 disable_packet_misalign = 0x0; 2751 2752 if((spd_intf == TEFMOD_SPD_10_SGMII) | 2753 (spd_intf == TEFMOD_SPD_100_SGMII) | 2754 (spd_intf == TEFMOD_SPD_1000_SGMII) ) { 2755 encode_mode = 0x3; /* cl36 8b10b */ 2756 hg2_message_invalid_code_enable = 0x0; 2757 /* ------------------------------------- 0xc114 */ 2758 disable_packet_misalign = 0x1; 2759 } else if((spd_intf == TEFMOD_SPD_10000_XFI) || 2760 (spd_intf == TEFMOD_SPD_10600_XFI_HG)) { 2761 t_fifo_mode = 0; 2762 t_enc_mode = 1; 2763 cl49_tx_tl_mode = 0; 2764 cl49_bypass_txsm = 0; 2765 hg2_en = 0; 2766 scr_mode = 1; 2767 os_mode = 1; 2768 t_pma_btmx_mode = 0; 2769 /* ------------------------------------ 0xc111 */ 2770 /* encode_mode = 0x5; 2771 cl49_bypass_txsm = 0; 2772 hg2_message_invalid_code_enable = 0; */ 2773 /* ------------------------------------ 0xc113 */ 2774 /* scr_mode = 0x1; */ 2775 /* ------------------------------------ 0xa000 */ 2776 /* mld_swap_en = 0; */ 2777 } else if ((spd_intf == TEFMOD_SPD_20000_XFI) || 2778 (spd_intf == TEFMOD_SPD_25000_XFI) || 2779 (spd_intf == TEFMOD_SPD_21200_XFI_HG) || 2780 (spd_intf == TEFMOD_SPD_26500_XFI_HG)) { 2781 t_fifo_mode = 0; 2782 t_enc_mode = 1; 2783 cl49_tx_tl_mode = 0; 2784 cl49_bypass_txsm = 0; 2785 hg2_en = 0; 2786 scr_mode = 1; 2787 os_mode = 0; 2788 t_pma_btmx_mode = 0; 2789 } else if ((spd_intf == TEFMOD_SPD_20G_MLD_X2) || 2790 (spd_intf == TEFMOD_SPD_21G_MLD_HG_X2)) { 2791 t_fifo_mode = 3; 2792 t_enc_mode = 2; 2793 cl82_bypass_txsm = 0; 2794 hg2_en = 0; 2795 os_mode = 1; 2796 scr_mode = 4; 2797 t_pma_btmx_mode = 0; 2798 mld_swap_count = tx_am_timer_init_val; /* shorten from 0xfffc. For sim ? */ 2799 mld_swap_en = 1; 2800 } else if ((spd_intf == TEFMOD_SPD_40G_MLD_X2) || 2801 (spd_intf == TEFMOD_SPD_42G_MLD_HG_X2) || 2802 (spd_intf == TEFMOD_SPD_50G_MLD_X2) || 2803 (spd_intf == TEFMOD_SPD_53G_MLD_HG_X2)) { 2804 t_fifo_mode = 1; 2805 t_enc_mode = 2; 2806 cl82_bypass_txsm = 0; 2807 hg2_en = 0; 2808 scr_mode = 2; 2809 t_pma_btmx_mode = 1; 2810 os_mode = 0; 2811 mld_swap_count = tx_am_timer_init_val; /* shorten from 0xfffc. For sim ? */ 2812 mld_swap_en = 1; 2813 } else if ((spd_intf == TEFMOD_SPD_40G_MLD_X4) || 2814 (spd_intf == TEFMOD_SPD_50G_MLD_X4) || 2815 (spd_intf == TEFMOD_SPD_42G_MLD_HG_X4) || 2816 (spd_intf == TEFMOD_SPD_53G_MLD_HG_X4)) { 2817 t_fifo_mode = 1; 2818 t_enc_mode = 2; 2819 cl82_bypass_txsm = 0; 2820 hg2_en = 0; 2821 scr_mode = 5; 2822 t_pma_btmx_mode = 0; 2823 os_mode = 1; 2824 mld_swap_count = tx_am_timer_init_val; /* shorten from 0xfffc. For sim ? */ 2825 mld_swap_en = 1; 2826 } else if ((spd_intf == TEFMOD_SPD_100G_MLD_X4) || 2827 (spd_intf == TEFMOD_SPD_106G_MLD_HG_X4)) { 2828 t_fifo_mode = 2; 2829 t_enc_mode = 2; 2830 cl82_bypass_txsm = 0; 2831 hg2_en = 0; 2832 scr_mode = 3; 2833 t_pma_btmx_mode = 2; 2834 os_mode = 0; 2835 mld_swap_count = tx_am_timer_init_val; 2836 mld_swap_en = 1; 2837 } else if (spd_intf == TEFMOD_SPD_10000 ) { /* 10G XAUI */ 2838 /* ------------------------------------ 0xc111 */ 2839 encode_mode = 0x1; /* cl48 8b10b */ 2840 cl49_bypass_txsm = 1; 2841 hg2_message_invalid_code_enable = 0; 2842 /* ------------------------------------ 0xc113 */ 2843 scr_mode = 0x0; /* bypass scramble */ 2844 /* ------------------------------------ 0xa000 */ 2845 mld_swap_en = 0; 2846 } else if (spd_intf == TEFMOD_SPD_10000_HI ) { /* 10.6G HI XAUI */ 2847 /* ------------------------------------ 0xc111 */ 2848 encode_mode = 0x1; /* cl48 8b10b */ 2849 cl49_bypass_txsm = 1; 2850 hg2_message_invalid_code_enable = 0; 2851 /* ------------------------------------ 0xc113 */ 2852 scr_mode = 0x0; /* bypass scramble */ 2853 /* ------------------------------------ 0xa000 */ 2854 mld_swap_en = 0; 2855 } else if (spd_intf == TEFMOD_SPD_10000_DXGXS) { 2856 /* ------------------------------------ 0xc111 */ 2857 encode_mode = 0x2; /* rxaui */ 2858 cl49_bypass_txsm = 1; 2859 hg2_message_invalid_code_enable = 0; 2860 /* ------------------------------------ 0xc113 */ 2861 scr_mode = 0x0; /* bypass scramble */ 2862 /* ------------------------------------ 0xa000 */ 2863 mld_swap_en = 0; 2864 } else if (spd_intf == TEFMOD_SPD_20000) { /* 20G XAIU */ 2865 /* ------------------------------------ 0xc111 */ 2866 encode_mode = 0x01; 2867 cl49_bypass_txsm = 1; 2868 hg2_message_invalid_code_enable = 0; 2869 /* ------------------------------------ 0xc113 */ 2870 scr_mode = 0x0; 2871 /* ------------------------------------ 0xa000 */ 2872 mld_swap_en = 0; 2873 } else if (spd_intf == TEFMOD_SPD_21000) { /* 20G XAIU */ 2874 /* ------------------------------------ 0xc111 */ 2875 encode_mode = 0x01; 2876 cl49_bypass_txsm = 1; 2877 hg2_message_invalid_code_enable = 0; 2878 /* ------------------------------------ 0xc113 */ 2879 scr_mode = 0x2; 2880 /* ------------------------------------ 0xa000 */ 2881 mld_swap_en = 0; 2882 } else if (spd_intf == TEFMOD_SPD_20G_MLD_DXGXS ) { 2883 /* ------------------------------------ 0xc111 */ 2884 encode_mode = 0x4; /* cl82 64b/66b */ 2885 cl49_bypass_txsm = 0; 2886 hg2_message_invalid_code_enable = 0; 2887 /* --------------------- ---------------0xc113 */ 2888 scr_mode = 0x3; /* 64b66b scrambled */ 2889 /* ------------------------------------ 0xa000 */ 2890 mld_swap_count = tx_am_timer_init_val; /* shorten from 0xfffc. For sim ? */ 2891 mld_swap_en = 1; 2892 2893 /* 0xa000 default value in silicon is for dual port */ 2894 } else if ((spd_intf ==TEFMOD_SPD_21G_HI_MLD_DXGXS)|| 2895 (spd_intf ==TEFMOD_SPD_12773_HI_DXGXS)) { 2896 /* ------------------------------------ 0xc111 */ 2897 encode_mode = 0x4; /* cl82 64b/66b */ 2898 cl49_bypass_txsm = 0; 2899 hg2_message_invalid_code_enable = 1; 2900 hg2_en = 1; 2901 hg2_codec = 1; 2902 /* --------------------- ---------------0xc113 */ 2903 scr_mode = 0x3; /* 64b66b scrambled */ 2904 /* ------------------------------------ 0xa000 */ 2905 mld_swap_count = tx_am_timer_init_val; /* shorten from 0xfffc. For sim ? */ 2906 mld_swap_en = 1; 2907 2908 } else if ((spd_intf == TEFMOD_SPD_20G_DXGXS)|| 2909 (spd_intf == TEFMOD_SPD_21G_HI_DXGXS)) { 2910 /* ------------------------------------ 0xc111 */ 2911 encode_mode = 0x6; /* brcm 64b/66b */ 2912 cl49_bypass_txsm = 1; 2913 hg2_message_invalid_code_enable = 0; 2914 /* ------------------------------------ 0xc113 */ 2915 scr_mode = 0x1; /* 64b66b scrambled */ 2916 /* ------------------------------------ 0xa000 */ 2917 mld_swap_en = 0; 2918 } else if ((spd_intf == TEFMOD_SPD_42G_X4)|| 2919 (spd_intf == TEFMOD_SPD_40G_X4)|| 2920 (spd_intf == TEFMOD_SPD_25455) || 2921 (spd_intf == TEFMOD_SPD_12773_DXGXS)) { 2922 /* ------------------------------------ 0xc111 */ 2923 encode_mode = 0x6; /* brcm 64b/66b */ 2924 cl49_bypass_txsm = 1; 2925 hg2_message_invalid_code_enable = 0; 2926 /* ------------------------------------ 0xc113 */ 2927 scr_mode = 0x1; /* 64b66b scrambled */ 2928 /* ------------------------------------ 0xa000 */ 2929 mld_swap_en = 0; 2930 } else if (spd_intf == TEFMOD_SPD_40G_XLAUI ) { 2931 /* ------------------------------------ 0xc111 */ 2932 encode_mode = 0x4; /* cl82 64b/66b */ 2933 cl49_bypass_txsm = 0; 2934 hg2_message_invalid_code_enable = 0; 2935 /* ------------------------------------ 0xc113 */ 2936 scr_mode = 0x3; /* 64b66b scrambled */ 2937 /* ------------------------------------ 0xa000 */ 2938 /* 2939 #if defined (_DV_TRIDENT2) 2940 mld_swap_count = tx_am_timer_init_val; 2941 #else 2942 mld_swap_count = 0xfffc; 2943 #endif 2944 */ 2945 mld_swap_en = 1; 2946 } else if (spd_intf == TEFMOD_SPD_42G_XLAUI ) { 2947 /* ------------------------------------ 0xc111 */ 2948 encode_mode = 0x4; /* cl82 64b/66b */ 2949 cl49_bypass_txsm = 0; 2950 hg2_message_invalid_code_enable = 1; 2951 hg2_en = 1; 2952 hg2_codec = 1; 2953 /* ------------------------------------ 0xc113 */ 2954 scr_mode = 0x3; /* 64b66b scrambled */ 2955 /* ------------------------------------ 0xa000 */ 2956 /* 2957 #if defined (_DV_TRIDENT2) 2958 mld_swap_count = tx_am_timer_init_val; 2959 #else 2960 mld_swap_count = 0xfffc; 2961 #endif 2962 */ 2963 mld_swap_en = 1; 2964 } 2965 if((spd_intf == TEFMOD_SPD_10600_XFI_HG) || 2966 (spd_intf == TEFMOD_SPD_21200_XFI_HG) || 2967 (spd_intf == TEFMOD_SPD_26500_XFI_HG) || 2968 (spd_intf == TEFMOD_SPD_21G_MLD_HG_X2) || 2969 (spd_intf == TEFMOD_SPD_42G_MLD_HG_X4) || 2970 (spd_intf == TEFMOD_SPD_53G_MLD_HG_X4) || 2971 (spd_intf == TEFMOD_SPD_42G_MLD_HG_X2) || 2972 (spd_intf == TEFMOD_SPD_53G_MLD_HG_X2) || 2973 (spd_intf == TEFMOD_SPD_106G_MLD_HG_X4)) { 2974 /* not CL48 */ 2975 hg2_en = 1; 2976 } 2977 if (cntl) { 2978 TX_X4_MISCr_CLR(TX_X4_CONTROL0_MISCr_reg); 2979 TX_X4_MISCr_OS_MODEf_SET(TX_X4_CONTROL0_MISCr_reg, os_mode); 2980 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_MISCr(pc, TX_X4_CONTROL0_MISCr_reg)); 2981 2982 TX_X1_T_PMA_WTRMKr_CLR(TX_X1_CONTROL0_T_PMA_WATERMARKr_reg); 2983 TX_X1_T_PMA_WTRMKr_SINGLE_LANE_BITMUX_WATERMARKf_SET(TX_X1_CONTROL0_T_PMA_WATERMARKr_reg, 4); 2984 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X1_T_PMA_WTRMKr(pc, TX_X1_CONTROL0_T_PMA_WATERMARKr_reg)); 2985 2986 TX_X2_CL82_0r_CLR(TX_X2_CONTROL0_CL82_0r_reg); 2987 TX_X2_CL82_0r_T_FIFO_MODEf_SET(TX_X2_CONTROL0_CL82_0r_reg, t_fifo_mode); 2988 TX_X2_CL82_0r_CL82_BYPASS_TXSMf_SET(TX_X2_CONTROL0_CL82_0r_reg, cl82_bypass_txsm); 2989 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X2_CL82_0r(pc, TX_X2_CONTROL0_CL82_0r_reg)); 2990 2991 TX_X4_ENC0r_CLR(TX_X4_CONTROL0_ENCODE_0r_reg); 2992 TX_X4_ENC0r_T_ENC_MODEf_SET(TX_X4_CONTROL0_ENCODE_0r_reg, t_enc_mode); 2993 TX_X4_ENC0r_CL49_TX_TL_MODEf_SET(TX_X4_CONTROL0_ENCODE_0r_reg, cl49_tx_tl_mode); 2994 TX_X4_ENC0r_CL49_BYPASS_TXSMf_SET(TX_X4_CONTROL0_ENCODE_0r_reg, cl49_bypass_txsm); 2995 TX_X4_ENC0r_HG2_ENABLEf_SET(TX_X4_CONTROL0_ENCODE_0r_reg, hg2_en); 2996 PHYMOD_IF_ERR_RETURN 2997 (MODIFY_TX_X4_ENC0r(pc, TX_X4_CONTROL0_ENCODE_0r_reg)); 2998 2999 TX_X4_MISCr_CLR(TX_X4_CONTROL0_MISCr_reg); 3000 TX_X4_MISCr_SCR_MODEf_SET(TX_X4_CONTROL0_MISCr_reg, scr_mode); 3001 TX_X4_MISCr_T_PMA_BTMX_MODEf_SET(TX_X4_CONTROL0_MISCr_reg, t_pma_btmx_mode); 3002 PHYMOD_IF_ERR_RETURN 3003 (MODIFY_TX_X4_MISCr(pc, TX_X4_CONTROL0_MISCr_reg)); 3004 3005 /* 0xa000 */ 3006 TX_X2_MLD_SWP_CNTr_CLR(TX_X2_CONTROL0_MLD_SWAP_COUNTr_reg); 3007 TX_X2_MLD_SWP_CNTr_MLD_SWAP_COUNTf_SET(TX_X2_CONTROL0_MLD_SWAP_COUNTr_reg, mld_swap_count); 3008 /*if(mask) */ 3009 PHYMOD_IF_ERR_RETURN 3010 (MODIFY_TX_X2_MLD_SWP_CNTr(pc, TX_X2_CONTROL0_MLD_SWAP_COUNTr_reg)); 3011 } else { 3012 /* no op */ 3013 return PHYMOD_E_NONE; 3014 } 3015 return PHYMOD_E_NONE; 3016 } 3017 #endif 3018 3019 #ifdef _DV_TB_ 3020 /*! 3021 @brief Local Fault/Remote Fault signalling enable for Tx and RX 3022 @param pc handle to current TSCF context (#PHYMOD_ST) 3023 @returns The value PHYMOD_E_NONE upon successful completion. 3024 @details 3025 This function is used to enable/disable Link Interrupt, Local Fault and 3026 Remote Fault signalling of any lane . 3027 3028 \li #PHYMOD_ST::per_lane_control[3:0] represents the mode (CL49, CL48, CL82). 3029 \li #PHYMOD_ST::per_lane_control[6] is for li; 3030 \li #PHYMOD_ST::per_lane_control[5] is for lf; 3031 \li #PHYMOD_ST::per_lane_control[4] is for rf; 3032 3033 This function reads/modifies the following registers: 3034 3035 \li cl49_tx : 0xc113 3036 \li cl49_rx : 0xc134 3037 \li cl48_tx : 0xa001 3038 \li cl82_tx : 0xa002 3039 \li cl48_cl82_rx : 0xa024 3040 */ 3041 3042 int tefmod_lf_rf_control(PHYMOD_ST* pc) /* LF_RF_CONTROL */ 3043 { 3044 TEFMOD_DBG_IN_FUNC_INFO(pc); 3045 return PHYMOD_E_NONE; 3046 } 3047 #endif 3048 3049 #ifdef _DV_TB_ 3050 /*! 3051 @brief set rx decoder of any particular lane 3052 3053 @param pc handle to current TSCF context (#PHYMOD_ST) 3054 3055 @returns The value PHYMOD_E_NONE upon successful completion. 3056 3057 This function is used to select decoder of any receive lane. 3058 3059 \li select encodeMode 3060 3061 This function reads/modifies the following registers: 3062 3063 \li descr_mode : 0xc130[15:14] 3064 \li dec_tl_mode : 0xc130[13:11] 3065 \li deskew_mode : 0xc130[10:8] 3066 \li dec_fsm_mode : 0xc130[7:5] 3067 \li cl36_en : 0xc134[0] 3068 3069 */ 3070 3071 3072 /* for DV only ? CHECK Lpti */ 3073 int tefmod_decode_set(PHYMOD_ST* pc) /* DECODE_SET */ 3074 { 3075 uint16_t descr_mode, dec_tl_mode, deskew_mode, dec_fsm_mode; 3076 uint16_t bypass_cl49rxsm, hg2_message_ivalid_code_enable, hg2_en; 3077 uint16_t cl36byte_delete_mode, os_mode, rx_gbox_afrst_en; 3078 uint16_t cl82_dswin, cl48_dswin64b66b, cl48_dswin8b10b, rx_x1_cntl0_deskw_en; 3079 uint16_t bs_sm_sync_mode; 3080 uint16_t bs_sync_en; 3081 uint16_t bs_dist_mode; 3082 uint16_t bs_btmx_mode; 3083 uint16_t sync_code_sm_en; 3084 uint16_t rx_control0_misc0_en; 3085 uint16_t data, mask; 3086 int cntl; 3087 RX_X4_BLKSYNC_CFGr_t RX_X4_CONTROL0_BLKSYNC_CONFIGr_reg; 3088 RX_X4_DEC_CTL0r_t RX_X4_CONTROL0_DECODE_CONTROL_0r_reg; 3089 RX_X4_PCS_CTL0r_t RX_X4_CONTROL0_PCS_CONTROL_0r_reg; 3090 CL82_LANES_1_0_AM_BYTE2r_t CL82_AMS_LANES_1_0_AM_BYTE2r_reg; 3091 CL82_LN_1_AM_BYTE10r_t CL82_AMS_LANE_1_AM_BYTE10r_reg; 3092 CL82_LN_0_AM_BYTE10r_t CL82_AMS_LANE_0_AM_BYTE10r_reg; 3093 CL82_RX_AM_TMRr_t CL82_SHARED_CL82_RX_AM_TIMERr_reg; 3094 3095 TEFMOD_DBG_IN_FUNC_INFO(pc); 3096 cntl = pc->per_lane_control; 3097 descr_mode = 0x0; /* 00=bypass descrambler; 01=64b66b descrambler; 3098 10=8b10b descrambler */ 3099 dec_tl_mode = 0x0; /* 3'b000 - None; 3'b001 - cl49 64b66b mode; 3100 3'b010 - BRCM 64b66b mode; 3101 3'b011 - ATL - cl49/BRCM 64b66b mode; 3102 3'b100 - 8b10b mode - cl48 mode 3103 3'b101 - 8b10b mode - cl36 mode */ 3104 deskew_mode = 0x0; 3105 dec_fsm_mode = 0x0; /* {001:CL49}, {010:BRCM}, {011:ATL}, 3106 {100:CL48}, {101:CL36}, {110:CL82}, {111:NONE} */ 3107 cl36byte_delete_mode = 0x0; 3108 bypass_cl49rxsm = 0x0; 3109 hg2_message_ivalid_code_enable = 0x1; 3110 hg2_en = 0; 3111 os_mode = 0x0; /* 0= OS MODE 1; 1= OS MODE 2; 2=OS MODE 3; 3112 3=OS MODE 3.3; 4=OS MODE 4; 5=OS MODE 5; 3113 6=OS MODE 8; 7=OS MODE 8.25; 8: OS MODE 10*/ 3114 rx_gbox_afrst_en = 0x0; 3115 rx_x1_cntl0_deskw_en = 0; 3116 cl82_dswin = 0; 3117 cl48_dswin64b66b = 0; 3118 cl48_dswin8b10b = 0; 3119 sync_code_sm_en = 0; 3120 rx_control0_misc0_en = 0; 3121 3122 if (cntl) { /* set decoder */ 3123 if(pc->spd_intf == TEFMOD_SPD_1000_SGMII) { 3124 dec_tl_mode = 0x5; 3125 deskew_mode = 0x4; 3126 dec_fsm_mode = 0x5; 3127 cl36byte_delete_mode = 0x2; 3128 hg2_message_ivalid_code_enable = 0x0; 3129 rx_gbox_afrst_en = 0x1; 3130 if (pc->plldiv == 40) { 3131 os_mode = 0x5; 3132 } else if (pc->plldiv == 66){ 3133 os_mode = 0x7; 3134 } 3135 } else if(pc->spd_intf == TEFMOD_SPD_1G_20G) { 3136 os_mode = 0x8; 3137 } else if(pc->spd_intf == TEFMOD_SPD_1G_25G) { 3138 os_mode = 0x12; 3139 } else if(pc->spd_intf == TEFMOD_SPD_10000_XFI) { 3140 os_mode = 0x1; 3141 /* ------------------------------------ 0xc130 */ 3142 deskew_mode = 0x5; 3143 descr_mode = 0x1; 3144 dec_tl_mode = 0x1; 3145 dec_fsm_mode = 0x1; 3146 /* ------------------------------------ 0xc136 */ 3147 /* ------------------------------------ 0xc134 */ 3148 bypass_cl49rxsm = 0x0; 3149 3150 bs_sm_sync_mode = 1; 3151 bs_sync_en = 1; 3152 bs_dist_mode = 0; 3153 bs_btmx_mode = 0; 3154 } else if(pc->spd_intf == TEFMOD_SPD_10600_XFI_HG) { 3155 os_mode = 0x1; 3156 /* ------------------------------------ 0xc130 */ 3157 deskew_mode = 0x5; 3158 descr_mode = 0x1; 3159 dec_tl_mode = 0x1; 3160 dec_fsm_mode = 0x1; 3161 /* ------------------------------------ 0xc136 */ 3162 /* ------------------------------------ 0xc134 */ 3163 bypass_cl49rxsm = 0x0; 3164 3165 bs_sm_sync_mode = 1; 3166 bs_sync_en = 1; 3167 bs_dist_mode = 0; 3168 bs_btmx_mode = 0; 3169 hg2_en = 1; 3170 } else if ((pc->spd_intf == TEFMOD_SPD_20000_XFI) || 3171 (pc->spd_intf == TEFMOD_SPD_21200_XFI_HG) || 3172 (pc->spd_intf == TEFMOD_SPD_25000_XFI) || 3173 (pc->spd_intf == TEFMOD_SPD_26500_XFI_HG)) { 3174 os_mode = 0; 3175 bs_sm_sync_mode = 1; 3176 bs_sync_en = 1; 3177 bs_dist_mode = 0; 3178 bs_btmx_mode = 0; 3179 deskew_mode = 5; 3180 descr_mode = 1; 3181 dec_tl_mode = 1; 3182 dec_fsm_mode = 1; 3183 } else if ((pc->spd_intf == TEFMOD_SPD_20G_MLD_X2) || 3184 (pc->spd_intf == TEFMOD_SPD_21G_MLD_HG_X2)) { 3185 os_mode = 1; 3186 bs_sm_sync_mode = 0; 3187 bs_sync_en = 1; 3188 bs_dist_mode = 2; 3189 bs_btmx_mode = 0; 3190 deskew_mode = 1; 3191 descr_mode = 2; 3192 dec_tl_mode = 2; 3193 dec_fsm_mode = 2; 3194 } else if ((pc->spd_intf == TEFMOD_SPD_40G_MLD_X4) || 3195 (pc->spd_intf == TEFMOD_SPD_50G_MLD_X4) || 3196 (pc->spd_intf == TEFMOD_SPD_42G_MLD_HG_X4) || 3197 (pc->spd_intf == TEFMOD_SPD_53G_MLD_HG_X4)) { 3198 os_mode = 1; 3199 bs_sm_sync_mode = 0; 3200 bs_sync_en = 1; 3201 bs_dist_mode = 2; 3202 bs_btmx_mode = 0; 3203 deskew_mode = 2; 3204 descr_mode = 2; 3205 dec_tl_mode = 2; 3206 dec_fsm_mode = 2; 3207 } else if ((pc->spd_intf == TEFMOD_SPD_40G_MLD_X2) || 3208 (pc->spd_intf == TEFMOD_SPD_42G_MLD_HG_X2) || 3209 (pc->spd_intf == TEFMOD_SPD_50G_MLD_X2) || 3210 (pc->spd_intf == TEFMOD_SPD_53G_MLD_HG_X2)) { 3211 os_mode = 0; 3212 bs_sm_sync_mode = 0; 3213 bs_sync_en = 1; 3214 bs_dist_mode = 1; 3215 bs_btmx_mode = 1; 3216 deskew_mode = 3; 3217 descr_mode = 2; 3218 dec_tl_mode = 2; 3219 dec_fsm_mode = 2; 3220 } else if ((pc->spd_intf == TEFMOD_SPD_100G_MLD_X4) || 3221 (pc->spd_intf == TEFMOD_SPD_106G_MLD_HG_X4)) { 3222 os_mode = 0; 3223 bs_sm_sync_mode = 0; 3224 bs_sync_en = 1; 3225 bs_dist_mode = 3; 3226 bs_btmx_mode = 2; 3227 deskew_mode = 4; 3228 descr_mode = 2; 3229 dec_tl_mode = 2; 3230 dec_fsm_mode = 2; 3231 } else { 3232 PHYMOD_DEBUG_ERROR(("%-22s ERROR: p=%0d undefined spd_intf=%0d(%s)\n", __func__, pc->port, pc->spd_intf, 3233 e2s_tefmod_spd_intfc_type_t[pc->spd_intf])); 3234 return PHYMOD_E_FAIL; 3235 } 3236 /* HG setting */ 3237 /* if((pc->ctrl_type & TEFMOD_CTRL_TYPE_HG)) {} */ 3238 if((pc->spd_intf == TEFMOD_SPD_10600_XFI_HG) || 3239 (pc->spd_intf == TEFMOD_SPD_21200_XFI_HG) || 3240 (pc->spd_intf == TEFMOD_SPD_26500_XFI_HG) || 3241 (pc->spd_intf == TEFMOD_SPD_21G_MLD_HG_X2) || 3242 (pc->spd_intf == TEFMOD_SPD_42G_MLD_HG_X4) || 3243 (pc->spd_intf == TEFMOD_SPD_53G_MLD_HG_X4) || 3244 (pc->spd_intf == TEFMOD_SPD_42G_MLD_HG_X2) || 3245 (pc->spd_intf == TEFMOD_SPD_53G_MLD_HG_X2) || 3246 (pc->spd_intf == TEFMOD_SPD_106G_MLD_HG_X4)) { 3247 /* not CL48 */ 3248 hg2_en = 1; 3249 } 3250 3251 /* 0xc130 */ 3252 RX_X4_PCS_CTL0r_CLR(RX_X4_CONTROL0_PCS_CONTROL_0r_reg); 3253 RX_X4_PCS_CTL0r_DESCR_MODEf_SET(RX_X4_CONTROL0_PCS_CONTROL_0r_reg, descr_mode); 3254 RX_X4_PCS_CTL0r_DEC_TL_MODEf_SET(RX_X4_CONTROL0_PCS_CONTROL_0r_reg, dec_tl_mode); 3255 RX_X4_PCS_CTL0r_DESKEW_MODEf_SET(RX_X4_CONTROL0_PCS_CONTROL_0r_reg, deskew_mode); 3256 RX_X4_PCS_CTL0r_DEC_FSM_MODEf_SET(RX_X4_CONTROL0_PCS_CONTROL_0r_reg, dec_fsm_mode); 3257 3258 PHYMOD_IF_ERR_RETURN 3259 (MODIFY_RX_X4_PCS_CTL0r(pc, RX_X4_CONTROL0_PCS_CONTROL_0r_reg)); 3260 3261 /* 0xc134 */ 3262 RX_X4_DEC_CTL0r_CLR(RX_X4_CONTROL0_DECODE_CONTROL_0r_reg); 3263 RX_X4_DEC_CTL0r_BYPASS_CL49RXSMf_SET(RX_X4_CONTROL0_DECODE_CONTROL_0r_reg, bypass_cl49rxsm); 3264 RX_X4_DEC_CTL0r_HG2_MESSAGE_INVALID_CODE_ENABLEf_SET(RX_X4_CONTROL0_DECODE_CONTROL_0r_reg, hg2_message_ivalid_code_enable); 3265 RX_X4_DEC_CTL0r_HG2_ENABLEf_SET(RX_X4_CONTROL0_DECODE_CONTROL_0r_reg, hg2_en); 3266 3267 PHYMOD_IF_ERR_RETURN 3268 (MODIFY_RX_X4_DEC_CTL0r(pc, RX_X4_CONTROL0_DECODE_CONTROL_0r_reg)); 3269 3270 RX_X4_BLKSYNC_CFGr_CLR(RX_X4_CONTROL0_BLKSYNC_CONFIGr_reg); 3271 RX_X4_BLKSYNC_CFGr_BS_SM_SYNC_MODEf_SET(RX_X4_CONTROL0_BLKSYNC_CONFIGr_reg, bs_sm_sync_mode); 3272 RX_X4_BLKSYNC_CFGr_BS_SYNC_ENf_SET(RX_X4_CONTROL0_BLKSYNC_CONFIGr_reg, bs_sync_en); 3273 RX_X4_BLKSYNC_CFGr_BS_DIST_MODEf_SET(RX_X4_CONTROL0_BLKSYNC_CONFIGr_reg, bs_dist_mode); 3274 RX_X4_BLKSYNC_CFGr_BS_BTMX_MODEf_SET(RX_X4_CONTROL0_BLKSYNC_CONFIGr_reg, bs_btmx_mode); 3275 3276 PHYMOD_IF_ERR_RETURN 3277 (MODIFY_RX_X4_BLKSYNC_CFGr(pc, RX_X4_CONTROL0_BLKSYNC_CONFIGr_reg)); 3278 /* --Addr=0x9220 ------------------------- */ 3279 /* 3280 if((pc->spd_intf ==TEFMOD_SPD_10000)|| 3281 (pc->spd_intf ==TEFMOD_SPD_10000_HI)|| 3282 (pc->spd_intf ==TEFMOD_SPD_10000_DXGXS)|| 3283 (pc->spd_intf ==TEFMOD_SPD_20000)){ 3284 data = 0x0444; 3285 mask = 0xffff; 3286 sync_code_sm_en = 1; 3287 } else if ((pc->spd_intf ==TEFMOD_SPD_42G_X4)|| 3288 (pc->spd_intf ==TEFMOD_SPD_40G_X4)|| 3289 (pc->spd_intf ==TEFMOD_SPD_25455)|| 3290 (pc->spd_intf ==TEFMOD_SPD_21G_HI_DXGXS)|| 3291 (pc->spd_intf ==TEFMOD_SPD_20G_DXGXS)|| 3292 (pc->spd_intf == TEFMOD_SPD_12773_DXGXS) ) { 3293 data = 0x0323; 3294 mask = 0xffff; 3295 sync_code_sm_en = 1; 3296 } 3297 3298 if(sync_code_sm_en) { 3299 PHYMOD_IF_ERR_RETURN 3300 (MODIFY_RX_X1_CONTROL0_DECODE_CONTROL_0r(pc->unit, pc, data, mask)); 3301 } 3302 */ 3303 if(rx_control0_misc0_en) { 3304 /* rx_control0_misc0_en is made 0 3305 RX_X2_MISC0r_t RX_X2_CONTROL0_MISC_0r_reg; 3306 RX_X2_MISC0r_CLR(RX_X2_CONTROL0_MISC_0r_reg); 3307 RX_X2_MISC0r_SET(RX_X2_CONTROL0_MISC_0r_reg, ); 3308 PHYMOD_IF_ERR_RETURN(MODIFY_RX_X2_MISC0r(pc, RX_X2_CONTROL0_MISC_0r_reg)); 3309 */ 3310 } 3311 /* --Addr=0xc131 ------------------------- */ 3312 if((pc->spd_intf == TEFMOD_SPD_20G_MLD_DXGXS) || 3313 (pc->spd_intf == TEFMOD_SPD_21G_HI_MLD_DXGXS) || 3314 (pc->spd_intf == TEFMOD_SPD_40G_XLAUI) || 3315 (pc->spd_intf == TEFMOD_SPD_42G_XLAUI) || 3316 (pc->spd_intf == TEFMOD_SPD_12773_HI_DXGXS) ) { 3317 data = 0; 3318 mask = 0xffff; 3319 /*PHYMOD_IF_ERR_RETURN (MODIFY_RX_X4_CONTROL0_FEC_0r(pc->unit, pc, data, mask));*/ 3320 } 3321 /* --Addr=0x9123 ------------------------- */ 3322 /* for simualtion */ 3323 /* #if defined (_DV_TRIDENT2) */ 3324 CL82_RX_AM_TMRr_CLR(CL82_SHARED_CL82_RX_AM_TIMERr_reg); 3325 3326 if((pc->spd_intf == TEFMOD_SPD_40G_XLAUI)||(pc->spd_intf == TEFMOD_SPD_42G_XLAUI)) { 3327 data = pc->rx_am_timer_init_val; 3328 mask = 0xffff; 3329 CL82_RX_AM_TMRr_SET(CL82_SHARED_CL82_RX_AM_TIMERr_reg, pc->rx_am_timer_init_val); 3330 PHYMOD_IF_ERR_RETURN 3331 (MODIFY_CL82_RX_AM_TMRr(pc, CL82_SHARED_CL82_RX_AM_TIMERr_reg)); 3332 } 3333 if((pc->spd_intf == TEFMOD_SPD_20G_MLD_DXGXS) || 3334 (pc->spd_intf == TEFMOD_SPD_20G_MLD_X2) || 3335 (pc->spd_intf == TEFMOD_SPD_21G_MLD_HG_X2) || 3336 (pc->spd_intf == TEFMOD_SPD_40G_MLD_X4) || 3337 (pc->spd_intf == TEFMOD_SPD_50G_MLD_X4) || 3338 (pc->spd_intf == TEFMOD_SPD_40G_MLD_X2) || 3339 (pc->spd_intf == TEFMOD_SPD_42G_MLD_HG_X2) || 3340 (pc->spd_intf == TEFMOD_SPD_50G_MLD_X2) || 3341 (pc->spd_intf == TEFMOD_SPD_100G_MLD_X4) || 3342 (pc->spd_intf == TEFMOD_SPD_53G_MLD_HG_X2) || 3343 (pc->spd_intf == TEFMOD_SPD_42G_MLD_HG_X4) || 3344 (pc->spd_intf == TEFMOD_SPD_53G_MLD_HG_X4) || 3345 (pc->spd_intf == TEFMOD_SPD_106G_MLD_HG_X4)) { 3346 data = pc->rx_am_timer_init_val; /* shorthen from 0x3fff */ 3347 mask = 0xffff; 3348 CL82_RX_AM_TMRr_SET(CL82_SHARED_CL82_RX_AM_TIMERr_reg, pc->rx_am_timer_init_val); 3349 PHYMOD_IF_ERR_RETURN 3350 (MODIFY_CL82_RX_AM_TMRr(pc, CL82_SHARED_CL82_RX_AM_TIMERr_reg)); 3351 } 3352 /* #endif */ 3353 /* --Addr=0x9130 ------------------------- */ 3354 if((pc->spd_intf == TEFMOD_SPD_20G_MLD_DXGXS)) { 3355 data = 0x7690; 3356 mask = 0xffff; 3357 CL82_LN_0_AM_BYTE10r_CLR(CL82_AMS_LANE_0_AM_BYTE10r_reg); 3358 CL82_LN_0_AM_BYTE10r_SET(CL82_AMS_LANE_0_AM_BYTE10r_reg, 0x7690); 3359 PHYMOD_IF_ERR_RETURN 3360 (MODIFY_CL82_LN_0_AM_BYTE10r(pc, CL82_AMS_LANE_0_AM_BYTE10r_reg)); 3361 } 3362 /* --Addr=0x9131 ------------------------- */ 3363 if((pc->spd_intf == TEFMOD_SPD_20G_MLD_DXGXS)) { 3364 data = 0xc4f0; 3365 mask = 0xffff; 3366 CL82_LN_1_AM_BYTE10r_CLR(CL82_AMS_LANE_1_AM_BYTE10r_reg); 3367 CL82_LN_1_AM_BYTE10r_SET(CL82_AMS_LANE_1_AM_BYTE10r_reg, 0xc4f0); 3368 PHYMOD_IF_ERR_RETURN 3369 (MODIFY_CL82_LN_1_AM_BYTE10r(pc, CL82_AMS_LANE_1_AM_BYTE10r_reg)); 3370 } 3371 /* --Addr=0x9132 ------------------------- */ 3372 if((pc->spd_intf == TEFMOD_SPD_20G_MLD_DXGXS)) { 3373 data = 0xe647; 3374 mask = 0xffff; 3375 CL82_LANES_1_0_AM_BYTE2r_CLR(CL82_AMS_LANES_1_0_AM_BYTE2r_reg); 3376 CL82_LANES_1_0_AM_BYTE2r_SET(CL82_AMS_LANES_1_0_AM_BYTE2r_reg, 0xe647); 3377 PHYMOD_IF_ERR_RETURN 3378 (MODIFY_CL82_LANES_1_0_AM_BYTE2r(pc, CL82_AMS_LANES_1_0_AM_BYTE2r_reg)); 3379 } 3380 3381 if(pc->ctrl_type & TEFMOD_CTRL_TYPE_FAULT_DIS) { 3382 pc->per_lane_control = TEFMOD_FAULT_CL49 | TEFMOD_FAULT_CL48 | TEFMOD_FAULT_CL82; 3383 /* li, lf, rf =0 */ 3384 tefmod_lf_rf_control(pc); 3385 } else { 3386 pc->per_lane_control = 3387 (TEFMOD_FAULT_RF | TEFMOD_FAULT_LF | TEFMOD_FAULT_LI)<<4 | 3388 (TEFMOD_FAULT_CL49 | TEFMOD_FAULT_CL48 | TEFMOD_FAULT_CL82); 3389 tefmod_lf_rf_control(pc); 3390 } 3391 } else { /* if ~cntl */ 3392 /* no op */ 3393 return PHYMOD_E_NONE; 3394 } 3395 return PHYMOD_E_NONE; 3396 } 3397 #endif 3398 3399 /** 3400 @brief Checks config valid status for the port 3401 @param pc handle to current TSCF context (#PHYMOD_ST) 3402 @returns The value PHYMOD_E_NONE upon successful completion 3403 @details This register bit indicates that PCS is now programmed as required 3404 by the HT entry for that speed 3405 */ 3406 STATIC 3407 int _tefmod_wait_sc_stats_set(PHYMOD_ST* pc) 3408 { 3409 #if defined(_DV_TB_) || defined(_SDK_TEFMOD_) 3410 uint16_t data; 3411 uint16_t i; 3412 SC_X4_STSr_t reg_sc_ctrl_sts; 3413 SC_X4_STSr_CLR(reg_sc_ctrl_sts); 3414 i = 0; 3415 data = 0; 3416 #endif /* _DV_TB_ || _SDK_TEFMOD_ */ 3417 3418 #ifdef _DV_TB_ 3419 while(1){ 3420 i=i+1; /* added only to eliminate compile warning */ 3421 PHYMOD_IF_ERR_RETURN(READ_SC_X4_STSr(pc, ®_sc_ctrl_sts)); 3422 data = SC_X4_STSr_SW_SPEED_CONFIG_VLDf_GET(reg_sc_ctrl_sts); 3423 if(data == 1) 3424 break; 3425 } 3426 #endif /* _DV_TB_ */ 3427 #ifdef _SDK_TEFMOD_ 3428 for (i= 0; i < 10; i++) { 3429 PHYMOD_USLEEP(1); 3430 PHYMOD_IF_ERR_RETURN(READ_SC_X4_STSr(pc, ®_sc_ctrl_sts)); 3431 data = SC_X4_STSr_SW_SPEED_CONFIG_VLDf_GET(reg_sc_ctrl_sts); 3432 if(data == 1) { 3433 return PHYMOD_E_NONE; 3434 } 3435 } 3436 if (data != 1) { 3437 return PHYMOD_E_TIMEOUT; 3438 } 3439 #endif /* _SDK_TEFMOD_ */ 3440 /* Intentional check .if none of the above MACROs are defined,return PHYMOD_E_NONE */ 3441 /* coverity[dead_error_line] */ 3442 return PHYMOD_E_NONE; 3443 } 3444 3445 3446 #ifdef _SDK_TEFMOD_ 3447 /** 3448 @brief Set the port speed and enable the port 3449 @param pc handle to current TSCF context (#PHYMOD_ST) 3450 @param spd_intf the speed to set the port enum #tefmod_set_spd_intf 3451 @returns The value PHYMOD_E_NONE upon successful completion 3452 @details Sets the port to the specified speed and triggers the port, and waits 3453 for the port to be configured 3454 */ 3455 int tefmod_set_spd_intf(PHYMOD_ST *pc, tefmod_spd_intfc_type_t spd_intf) 3456 { 3457 SC_X4_CTLr_t xgxs_x4_ctrl; 3458 phymod_access_t pa_copy; 3459 int speed_id = 0, start_lane = 0, num_lane = 0; 3460 MAIN0_SERDESIDr_t serdesid; 3461 uint32_t model; 3462 TX_X4_TX_CTL0_GEN2r_t tx_x4_tx_ctrl_reg; 3463 RX_X4_PCS_CTL_0_GEN2r_t rx_x4_pcs_crtl_reg; 3464 int tx_cl91_fec_mode; 3465 int rx_cl91_fec_mode; 3466 3467 TEFMOD_DBG_IN_FUNC_INFO(pc); 3468 TEFMOD_DBG_IN_FUNC_VIN_INFO(pc,("spd_intf: %d", spd_intf)); 3469 3470 /* need to figure out what's the starting lane */ 3471 PHYMOD_MEMCPY(&pa_copy, pc, sizeof(pa_copy)); 3472 PHYMOD_IF_ERR_RETURN 3473 (phymod_util_lane_config_get(pc, &start_lane, &num_lane)); 3474 pa_copy.lane_mask = 0x1 << start_lane; 3475 3476 PHYMOD_IF_ERR_RETURN (tefmod_get_mapped_speed(spd_intf, &speed_id)); 3477 3478 /* next check serdes ID to see if gen2 or not */ 3479 READ_MAIN0_SERDESIDr(pc, &serdesid); 3480 model = MAIN0_SERDESIDr_MODEL_NUMBERf_GET(serdesid); 3481 3482 /*TSCF gen2 support IEEE 25G FEC (CL108)*/ 3483 if ((model == TSCF_GEN2) && (speed_id == sc_x4_control_sc_S_25G_X1)) { 3484 READ_TX_X4_TX_CTL0_GEN2r(pc, &tx_x4_tx_ctrl_reg); 3485 READ_RX_X4_PCS_CTL_0_GEN2r(pc, &rx_x4_pcs_crtl_reg); 3486 3487 tx_cl91_fec_mode = TX_X4_TX_CTL0_GEN2r_CL91_FEC_MODEf_GET(tx_x4_tx_ctrl_reg); 3488 rx_cl91_fec_mode = RX_X4_PCS_CTL_0_GEN2r_CL91_FEC_MODEf_GET(rx_x4_pcs_crtl_reg); 3489 3490 /*In IEEE 25G FEC, speed id is S_25G_KR_IEEE (0x72)*/ 3491 if ((tx_cl91_fec_mode == TEFMOD_IEEE_25G_CL91_SINGLE_LANE) 3492 && (rx_cl91_fec_mode == TEFMOD_IEEE_25G_CL91_SINGLE_LANE)) { 3493 speed_id = sc_x4_control_sc_S_25G_KR_IEEE; 3494 } 3495 } 3496 3497 /* write the speed_id into the speed_change register */ 3498 SC_X4_CTLr_CLR(xgxs_x4_ctrl); 3499 SC_X4_CTLr_SPEEDf_SET(xgxs_x4_ctrl, speed_id); 3500 MODIFY_SC_X4_CTLr(pc, xgxs_x4_ctrl); 3501 /*next call the speed_change routine */ 3502 PHYMOD_IF_ERR_RETURN (tefmod_trigger_speed_change(&pa_copy)); 3503 /*check the speed_change_done nit*/ 3504 PHYMOD_IF_ERR_RETURN (_tefmod_wait_sc_stats_set(pc)); 3505 3506 return PHYMOD_E_NONE; 3507 } 3508 3509 /** 3510 @brief Set the AN Portmode and Single Port for AN of TSCF. 3511 @param pc handle to current TSCF context (#PHYMOD_ST) 3512 @param num_of_lanes Number of lanes in this port 3513 @param starting_lane first lane in the port 3514 @param single_port Single port or not 3515 @returns PHYMOD_E_NONE if successful. PHYMOD_E_FAIL else. 3516 @details 3517 3518 This function can be called multiple times.Elements of #PHYMOD_ST should be 3519 initialized to required values prior to calling this function. The following 3520 sub-configurations are performed here. 3521 3522 \li Set pll divider for VCO setting (0x9000[12, 11:8]). pll divider is calculated from max_speed. 3523 3524 */ 3525 int tefmod_set_an_single_port_mode(PHYMOD_ST* pc, int an_enable) /* SET_AN_PORT_MODE */ 3526 { 3527 /* uint16_t rdata; */ 3528 MAIN0_SETUPr_t reg_setup; 3529 SC_X4_CTLr_t xgxs_x4_ctrl; 3530 phymod_access_t phy_copy; 3531 3532 3533 PHYMOD_MEMCPY(&phy_copy, pc, sizeof(phy_copy)); 3534 SC_X4_CTLr_CLR(xgxs_x4_ctrl); 3535 3536 TEFMOD_DBG_IN_FUNC_INFO(pc); 3537 TEFMOD_DBG_IN_FUNC_VIN_INFO(pc,("an_enable %d \n", an_enable)); 3538 3539 MAIN0_SETUPr_CLR(reg_setup); 3540 PHYMOD_IF_ERR_RETURN (READ_MAIN0_SETUPr(pc, ®_setup)); 3541 3542 /*Ref clock selection tied to 156.25MHz */ 3543 MAIN0_SETUPr_REFCLK_SELf_SET(reg_setup, 0x3); 3544 3545 /*Setting single port mode*/ 3546 MAIN0_SETUPr_SINGLE_PORT_MODEf_SET(reg_setup, an_enable); 3547 /*if signle port mode is set and not single port mode, we need 3548 to disable the sister port */ 3549 if (an_enable) { 3550 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(xgxs_x4_ctrl, 0); 3551 phy_copy.lane_mask= 0xf; 3552 MODIFY_SC_X4_CTLr(&phy_copy, xgxs_x4_ctrl); 3553 } else { 3554 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(xgxs_x4_ctrl, 1); 3555 phy_copy.lane_mask= 0xf; 3556 MODIFY_SC_X4_CTLr(pc, xgxs_x4_ctrl); 3557 } 3558 3559 PHYMOD_IF_ERR_RETURN(MODIFY_MAIN0_SETUPr(pc,reg_setup)); 3560 3561 return PHYMOD_E_NONE; 3562 } 3563 3564 /** 3565 @brief Set port_mode_sel for AN of TSCF. 3566 @param pc handle to current TSCF context (#PHYMOD_ST) 3567 @param num_of_lanes Number of lanes in this port 3568 @param starting_lane first lane in the port 3569 @returns PHYMOD_E_NONE if successful. PHYMOD_E_FAIL else. 3570 @details 3571 3572 This function is called to set the proper port_mode_sel when AN mode is enabled. 3573 */ 3574 int tefmod_set_an_port_mode(PHYMOD_ST* pc, int num_of_lanes, int starting_lane) /* SET_AN_PORT_MODE */ 3575 { 3576 MAIN0_SETUPr_t reg_setup; 3577 int port_mode_sel=0, new_port_mode_sel=0; 3578 3579 MAIN0_SETUPr_CLR(reg_setup); 3580 PHYMOD_IF_ERR_RETURN(READ_MAIN0_SETUPr(pc, ®_setup)); 3581 port_mode_sel = MAIN0_SETUPr_PORT_MODE_SELf_GET(reg_setup); 3582 3583 switch(port_mode_sel) { 3584 case TEFMOD_MULTI_PORT: /* 3, 2, 1, 0; QUAD */ 3585 if (num_of_lanes==2) { 3586 if(starting_lane==0) { 3587 new_port_mode_sel = TEFMOD_TRI2_PORT; 3588 } else { 3589 new_port_mode_sel = TEFMOD_TRI1_PORT; 3590 } 3591 } else { 3592 new_port_mode_sel = TEFMOD_MULTI_PORT; 3593 } 3594 break; 3595 case TEFMOD_TRI1_PORT: /* 3-2, 1, 0; TRI_1 */ 3596 if (num_of_lanes==2 && starting_lane==0) { 3597 new_port_mode_sel = TEFMOD_DXGXS; 3598 } else if (num_of_lanes==4 || (num_of_lanes==1 && starting_lane >= 2)) { 3599 new_port_mode_sel = TEFMOD_MULTI_PORT; 3600 } else { 3601 new_port_mode_sel = TEFMOD_TRI1_PORT; 3602 } 3603 break; 3604 case TEFMOD_TRI2_PORT: /* 3, 2, 1-0; TRI_2 */ 3605 if (num_of_lanes==2 && starting_lane==2) { 3606 new_port_mode_sel = TEFMOD_DXGXS; 3607 } else if (num_of_lanes==4 || (num_of_lanes==1 && starting_lane <= 1)) { 3608 new_port_mode_sel = TEFMOD_MULTI_PORT; 3609 } else { 3610 new_port_mode_sel = TEFMOD_TRI2_PORT; 3611 } 3612 break; 3613 case TEFMOD_DXGXS: /* 3-2, 1-0; DUAL */ 3614 if (num_of_lanes==1 && starting_lane <= 1) { 3615 new_port_mode_sel = TEFMOD_TRI1_PORT; 3616 } else if (num_of_lanes==1 && starting_lane >= 2) { 3617 new_port_mode_sel = TEFMOD_TRI2_PORT; 3618 } else if (num_of_lanes==2) { 3619 new_port_mode_sel = TEFMOD_DXGXS; 3620 } else { 3621 new_port_mode_sel = TEFMOD_MULTI_PORT; 3622 } 3623 break; 3624 case TEFMOD_SINGLE_PORT: /* 3-2-1-0; SINGLE PORT */ 3625 if (num_of_lanes==2) { 3626 new_port_mode_sel = TEFMOD_DXGXS; 3627 } else if (num_of_lanes==1 && starting_lane <= 1) { 3628 new_port_mode_sel = TEFMOD_TRI1_PORT; 3629 } else if (num_of_lanes==1 && starting_lane >= 2) { 3630 new_port_mode_sel = TEFMOD_TRI2_PORT; 3631 } else { 3632 new_port_mode_sel = TEFMOD_MULTI_PORT; 3633 } 3634 break; 3635 default: 3636 return PHYMOD_E_FAIL; 3637 break ; 3638 } 3639 MAIN0_SETUPr_PORT_MODE_SELf_SET(reg_setup, new_port_mode_sel); 3640 PHYMOD_IF_ERR_RETURN(MODIFY_MAIN0_SETUPr(pc, reg_setup)); 3641 3642 return PHYMOD_E_NONE; 3643 } 3644 #endif /* _SDK_TEFMOD_ */ 3645 3646 3647 3648 #ifdef _DV_TB_ 3649 /*! 3650 @brief Programs the speed mode for a particular lane 3651 @param pc handle to current TSCF context (#PHYMOD_ST) 3652 @returns PHYMOD_E_NONE if no errors. PHYMOD_EERROR else. 3653 pc->accData nozero if PLL is needed to restarted with different value; 3654 @details 3655 This function sets the TEF into a particular speed mode if per_lane_control= 3656 (1|(aspd<<4)). If per_lane_control=0, the function tells us PLLdiv is required 3657 to be changed or not by return the new pll value in pc->accData. If no change 3658 is required, then return 0 in accData. 3659 If per_lane_control = 2; then pc->accData returns plldiv in the register. 3660 If per_lane_control = 1; set to the desired speed. 3661 3662 To set the desired speed, set the following fields of #PHYMOD_ST 3663 3664 \li #PHYMOD_ST::lane_select to the lane number(s) 3665 \li #PHYMOD_ST::spd_intf to a value from enumerated type #tefmod_spd_intfc_type_t 3666 \li #PHYMOD_ST::port_type to a type from the enumerated type #tefmod_port_type_t 3667 \li #PHYMOD_ST::os_type to a type from the enumerated type #tefmod_os_type 3668 3669 Note that legitimate combinations for these fields must be used; otherwise 3670 ill-defined behavior may result. 3671 3672 This function must be called once for combo mode and once per lane for 3673 indepedent lane mode. Only if all lanes are being set to the same 3674 speed-interface can this function be called once for all lanes. Before calling 3675 this function, the PLL sequencer must be disabled via the function 3676 #tefmod_pll_sequencer_control(). After calling this function, the PLL sequencer 3677 must be enabled via the same function. 3678 3679 To program multiple lanes in independent lane mode, it is recommended to 3680 disable the PLL sequencer, call this function once for every lane being 3681 programmed, and then enable the PLL sequencer. 3682 3683 This function modifies the following registers: 3684 3685 \li force_ln_mode (0xC001[8]), force_speed (0XC001[7:0]), force_oscdr_mode_val (0xC001[14:11]) 3686 \li set pcs mode (encodeMode) (0xC110[4:2]) 3687 3688 The following speeds are not implemented. 3689 \li TEFMOD_SPD_10000_DXGXS_SCR 3690 \li TEFMOD_SPD_15000 3691 \li TEFMOD_SPD_2000 3692 \li TEFMOD_SPD_6364_SINGLE 3693 3694 When accData return 1, upper layer needs to adjust the plldiv of other 3695 lanes/tefmod to prevent unnecessary PLL restart when other lanes/tefmod is 3696 called. 3697 */ 3698 3699 int tefmod_set_spd_intf(PHYMOD_ST* pc) /* SET_SPD_INTF */ 3700 { 3701 int plldiv, rv; 3702 uint32_t plldiv_r_val; 3703 3704 tefmod_spd_intfc_type_t spd_intf; 3705 int port_mode_sel_restart; 3706 int firmware_mode; 3707 /* 3708 0x0 = DEFAULT 3709 0x1 = SFP_OPT 3710 0x2 = SFP_DAC 3711 0x3 = XLAUI 3712 0x4 = FORCE_OSDFE 3713 0x5 = FORCE_BRDFE 3714 0x6 = SW_CL72 3715 0x7 = CL72_woAN 3716 0x8 = SFP_OPT_PF_TEMP_COMP 3717 */ 3718 /* #define SR4 0x1 3719 #define SFI_DAC 0x2 3720 #define XLAUI 0x3 3721 #define FORCE_OSDFE 0x4 3722 #define FORCE_BRDFE 0x5 3723 #define SW_CL72 0x6 3724 #define FORCED_MODE_CL72 0x7 3725 #define FORCE_OS 0xF 3726 */ 3727 TEFMOD_DBG_IN_FUNC_INFO(pc); 3728 firmware_mode = 0; 3729 3730 #ifdef _DV_TB_ 3731 spd_intf = pc->spd_intf; 3732 pc->accAddr = ((pc->unit) << 16) | (pc->port); 3733 #endif 3734 3735 if (pc->spd_intf > TEFMOD_SPD_ILLEGAL) { 3736 PHYMOD_DEBUG_ERROR(("%-22s ERROR: Bad spd-intf: %d > TEFMOD_SPD_ILLEGAL\n", 3737 __func__, pc->spd_intf)); 3738 return PHYMOD_E_PARAM; 3739 } else { 3740 if (pc->verbosity ) 3741 PHYMOD_DEBUG_ERROR(("%-22s: %s[%d]\n",__func__,e2s_tefmod_spd_intfc_type_t[pc->spd_intf], 3742 e2n_tefmod_spd_intfc_type_t[pc->spd_intf])); 3743 } 3744 /* pll div calculation; assume refclk=156 */ 3745 plldiv = 66; /* default */ 3746 if (spd_intf == TEFMOD_SPD_1000_SGMII) { 3747 if((pc->plldiv==40)||(pc->plldiv==66)) { 3748 plldiv = pc->plldiv; 3749 } else { 3750 plldiv = 40; 3751 } 3752 plldiv = 40; 3753 /* speed_mii = IEEE0BLK_MIICNTL_MANUAL_SPEED1_BITS << 3754 IEEE0BLK_MIICNTL_MANUAL_SPEED1_SHIFT; MII_CTRL_SS_1000; */ 3755 /* remove TEFMOD_SPD_1000_FIBER */ 3756 /* speed_mii = PMD_IEEE0BLK_PMD_IEEECONTROL1_SPEEDSELECTION1_MASK; */ 3757 } else if (spd_intf == TEFMOD_SPD_10000_XFI) { 3758 plldiv = 66; 3759 firmware_mode = 0; /* 4=OS-DFE mode */ 3760 } else if (spd_intf == TEFMOD_SPD_10600_XFI_HG) { 3761 plldiv = 70; 3762 firmware_mode = 0; 3763 } else if (spd_intf == TEFMOD_SPD_20000_XFI) { 3764 plldiv = 132; 3765 } else if (spd_intf == TEFMOD_SPD_21200_XFI_HG) { 3766 plldiv = 140; 3767 } else if (spd_intf == TEFMOD_SPD_25000_XFI) { 3768 plldiv = 165; 3769 } else if (spd_intf == TEFMOD_SPD_26500_XFI_HG) { 3770 plldiv = 175; 3771 } else if (spd_intf == TEFMOD_SPD_20G_MLD_X2) { 3772 plldiv = 66; 3773 } else if (spd_intf == TEFMOD_SPD_21G_MLD_HG_X2) { 3774 plldiv = 70; 3775 } else if (spd_intf == TEFMOD_SPD_40G_MLD_X2) { 3776 plldiv = 132; 3777 } else if (spd_intf == TEFMOD_SPD_42G_MLD_HG_X2) { 3778 plldiv = 140; 3779 } else if (spd_intf == TEFMOD_SPD_50G_MLD_X2) { 3780 plldiv = 165; 3781 } else if (spd_intf == TEFMOD_SPD_53G_MLD_HG_X2) { 3782 plldiv = 175; 3783 } else if (spd_intf == TEFMOD_SPD_40G_MLD_X4) { 3784 plldiv = 66; 3785 } else if (spd_intf == TEFMOD_SPD_42G_MLD_HG_X4) { 3786 plldiv = 70; 3787 } else if (spd_intf == TEFMOD_SPD_50G_MLD_X4) { 3788 plldiv = 165; /* NICK was 66 */ 3789 } else if (spd_intf == TEFMOD_SPD_53G_MLD_HG_X4) { 3790 plldiv = 175; /* NICK was 70 */ 3791 } else if (spd_intf == TEFMOD_SPD_100G_MLD_X4) { 3792 plldiv = 165; 3793 } else if (spd_intf == TEFMOD_SPD_106G_MLD_HG_X4) { 3794 plldiv = 175; 3795 } 3796 rv = PHYMOD_E_NONE; 3797 3798 port_mode_sel_restart = 0; 3799 3800 if(pc->per_lane_control !=0x2) { 3801 tefmod_update_port_mode_select(pc, pc->port_type, pc->this_lane, pc->tsc_clk_freq_pll_by_48, pc->pll_reset_en); 3802 port_mode_sel_restart = pc->accData; 3803 } 3804 pc->accData = 0; 3805 /* read back plldiv */ 3806 PHYMOD_IF_ERR_RETURN(tefmod_get_plldiv(pc, &plldiv_r_val)); 3807 3808 if( (pc->plldiv != plldiv_r_val)|| port_mode_sel_restart) { 3809 if( pc->verbosity ) 3810 PHYMOD_DEBUG_ERROR(("%-22s: p=%0d pc->plldiv:%d mismatched reg plldiv=%0d exp \ 3811 plldiv=%0d mode_restart=%0d\n", __func__, pc->port, pc->plldiv, 3812 plldiv_r_val, plldiv, port_mode_sel_restart)); 3813 pc->plldiv = 0 ; 3814 } 3815 rv = PHYMOD_E_NONE; 3816 3817 if(pc->per_lane_control == 0 ) { 3818 PHYMOD_DEBUG_ERROR(("%-22s: p=%0d set_spd_intf probed\n", __func__, pc->port)); 3819 return rv; 3820 } else if(pc->per_lane_control == 2) { 3821 pc->accData = plldiv_r_val; 3822 PHYMOD_DEBUG_ERROR(("%-22s: p=%0d set_spd_intf get reg plldiv=%0d\n", 3823 __func__, pc->port, plldiv_r_val)); 3824 return rv; 3825 } 3826 if(pc->firmware_mode>=0) { 3827 firmware_mode = pc->firmware_mode; 3828 } 3829 pc->per_lane_control=1; 3830 rv |= tefmod_credit_set(pc); 3831 pc->per_lane_control=1; 3832 rv |= tefmod_encode_set(pc, pc->per_lane_control, pc->spd_intf, pc->tx_am_timer_init_val); 3833 pc->per_lane_control=1; 3834 rv |= tefmod_decode_set(pc); 3835 3836 return rv; 3837 3838 } /* tefmod_set_spd_intf(PHYMOD_ST* pc) */ 3839 #endif /* _DV_TB_ */ 3840 3841 /*! 3842 @brief supports per field override 3843 @param pc handle to current TSCF context (#PHYMOD_ST) 3844 @param per_field_override_en Controls which field to override 3845 @returns PHYMOD_E_NONE if no errors. PHYMOD_EERROR else. 3846 @details 3847 TBD 3848 */ 3849 int tefmod_set_override_0(PHYMOD_ST* pc, int per_field_override_en) /* OVERRIDE_SET */ 3850 { 3851 int or_value; 3852 override_type_t or_en; 3853 RX_X4_PCS_CTL0r_t RX_X4_CONTROL0_PCS_CONTROL_0r_reg; 3854 SC_X4_LN_NUM_OVRRr_t SC_X4_CONTROL_LANE_NUM_OVERRIDEr_reg; 3855 TX_X2_CL82_0r_t TX_X2_CONTROL0_CL82_0r_reg; 3856 TX_X4_ENC0r_t TX_X4_CONTROL0_ENCODE_0r_reg; 3857 TX_X4_MISCr_t TX_X4_CONTROL0_MISCr_reg; 3858 SC_X4_FLD_OVRR_EN0_TYPEr_t SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg; 3859 SC_X4_FLD_OVRR_EN1_TYPEr_t SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg; 3860 3861 TEFMOD_DBG_IN_FUNC_INFO(pc); 3862 or_en = (override_type_t) (per_field_override_en >> 16); 3863 3864 or_value = per_field_override_en & 0x0000ffff; 3865 3866 switch(or_en) { 3867 case OVERRIDE_CLEAR: 3868 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 3869 SC_X4_FLD_OVRR_EN0_TYPEr_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, or_value); 3870 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg); 3871 SC_X4_FLD_OVRR_EN1_TYPEr_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg, or_value); 3872 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 3873 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg)); 3874 break; 3875 case OVERRIDE_NUM_LANES: 3876 3877 SC_X4_LN_NUM_OVRRr_CLR(SC_X4_CONTROL_LANE_NUM_OVERRIDEr_reg); 3878 SC_X4_LN_NUM_OVRRr_NUM_LANES_OVERRIDE_VALUEf_SET(SC_X4_CONTROL_LANE_NUM_OVERRIDEr_reg, or_value); 3879 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_LN_NUM_OVRRr(pc, SC_X4_CONTROL_LANE_NUM_OVERRIDEr_reg)); 3880 3881 3882 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 3883 SC_X4_FLD_OVRR_EN0_TYPEr_NUM_LANES_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 1); 3884 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 3885 break; 3886 case OVERRIDE_NUM_LANES_DIS: 3887 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 3888 SC_X4_FLD_OVRR_EN0_TYPEr_NUM_LANES_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 0); 3889 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 3890 3891 break; 3892 case OVERRIDE_OS_MODE: 3893 3894 TX_X4_MISCr_CLR(TX_X4_CONTROL0_MISCr_reg); 3895 TX_X4_MISCr_OS_MODEf_SET(TX_X4_CONTROL0_MISCr_reg, or_value); 3896 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_MISCr(pc, TX_X4_CONTROL0_MISCr_reg)); 3897 3898 /*Set the override enable*/ 3899 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 3900 SC_X4_FLD_OVRR_EN0_TYPEr_OS_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 1); 3901 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 3902 break; 3903 case OVERRIDE_OS_MODE_DIS: 3904 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 3905 SC_X4_FLD_OVRR_EN0_TYPEr_OS_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 0); 3906 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 3907 3908 break; 3909 case OVERRIDE_T_FIFO_MODE: 3910 3911 TX_X2_CL82_0r_CLR(TX_X2_CONTROL0_CL82_0r_reg); 3912 TX_X2_CL82_0r_T_FIFO_MODEf_SET(TX_X2_CONTROL0_CL82_0r_reg, or_value); 3913 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X2_CL82_0r(pc, TX_X2_CONTROL0_CL82_0r_reg)); 3914 3915 /*Set the override enable*/ 3916 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 3917 SC_X4_FLD_OVRR_EN0_TYPEr_T_FIFO_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 1); 3918 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 3919 break; 3920 case OVERRIDE_T_FIFO_MODE_DIS: 3921 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 3922 SC_X4_FLD_OVRR_EN0_TYPEr_T_FIFO_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 0); 3923 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 3924 3925 break; 3926 case OVERRIDE_T_ENC_MODE: 3927 3928 TX_X4_ENC0r_CLR(TX_X4_CONTROL0_ENCODE_0r_reg); 3929 TX_X4_ENC0r_T_ENC_MODEf_SET(TX_X4_CONTROL0_ENCODE_0r_reg, or_value); 3930 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_ENC0r(pc, TX_X4_CONTROL0_ENCODE_0r_reg)); 3931 3932 /*Set the override enable*/ 3933 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 3934 SC_X4_FLD_OVRR_EN0_TYPEr_T_ENC_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 1); 3935 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 3936 3937 break; 3938 case OVERRIDE_T_ENC_MODE_DIS: 3939 /*Set the override enable*/ 3940 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 3941 SC_X4_FLD_OVRR_EN0_TYPEr_T_ENC_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 0); 3942 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 3943 break; 3944 case OVERRIDE_T_HG2_ENABLE: 3945 TX_X4_ENC0r_CLR(TX_X4_CONTROL0_ENCODE_0r_reg); 3946 TX_X4_ENC0r_HG2_ENABLEf_SET(TX_X4_CONTROL0_ENCODE_0r_reg, or_value); 3947 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_ENC0r(pc, TX_X4_CONTROL0_ENCODE_0r_reg)); 3948 /*Set the override enable*/ 3949 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 3950 SC_X4_FLD_OVRR_EN0_TYPEr_T_HG2_ENABLE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 1); 3951 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 3952 3953 break; 3954 case OVERRIDE_T_HG2_ENABLE_DIS: 3955 /*Set the override enable*/ 3956 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 3957 SC_X4_FLD_OVRR_EN0_TYPEr_T_HG2_ENABLE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 0); 3958 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 3959 break; 3960 case OVERRIDE_T_PMA_BTMX_MODE_OEN: 3961 3962 TX_X4_MISCr_CLR(TX_X4_CONTROL0_MISCr_reg); 3963 TX_X4_MISCr_T_PMA_BTMX_MODEf_SET(TX_X4_CONTROL0_MISCr_reg, or_value); 3964 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_MISCr(pc, TX_X4_CONTROL0_MISCr_reg)); 3965 /*Set the override enable*/ 3966 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 3967 SC_X4_FLD_OVRR_EN0_TYPEr_T_PMA_BTMX_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 1); 3968 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 3969 3970 break; 3971 case OVERRIDE_T_PMA_BTMX_MODE_OEN_DIS: 3972 /*Set the override enable*/ 3973 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 3974 SC_X4_FLD_OVRR_EN0_TYPEr_T_PMA_BTMX_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 0); 3975 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 3976 /* No missing break. Intentional fall through case */ 3977 /* coverity[unterminated_case] */ 3978 case OVERRIDE_SCR_MODE: 3979 3980 TX_X4_MISCr_CLR(TX_X4_CONTROL0_MISCr_reg); 3981 TX_X4_MISCr_SCR_MODEf_SET(TX_X4_CONTROL0_MISCr_reg, or_value); 3982 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_MISCr(pc, TX_X4_CONTROL0_MISCr_reg)); 3983 3984 /*Set the override enable*/ 3985 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 3986 SC_X4_FLD_OVRR_EN0_TYPEr_SCR_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 1); 3987 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 3988 3989 case OVERRIDE_SCR_MODE_DIS: 3990 /*Set the override enable*/ 3991 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 3992 SC_X4_FLD_OVRR_EN0_TYPEr_SCR_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 0); 3993 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 3994 break; 3995 case OVERRIDE_DESCR_MODE_OEN: 3996 3997 RX_X4_PCS_CTL0r_CLR(RX_X4_CONTROL0_PCS_CONTROL_0r_reg); 3998 RX_X4_PCS_CTL0r_DESCR_MODEf_SET(RX_X4_CONTROL0_PCS_CONTROL_0r_reg, or_value); 3999 PHYMOD_IF_ERR_RETURN(MODIFY_RX_X4_PCS_CTL0r(pc, RX_X4_CONTROL0_PCS_CONTROL_0r_reg)); 4000 4001 /*Set the override enable*/ 4002 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 4003 SC_X4_FLD_OVRR_EN0_TYPEr_DESCR_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 1); 4004 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 4005 break; 4006 case OVERRIDE_DESCR_MODE_OEN_DIS: 4007 /*Set the override enable*/ 4008 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 4009 SC_X4_FLD_OVRR_EN0_TYPEr_DESCR_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 0); 4010 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 4011 4012 break; 4013 case OVERRIDE_DEC_TL_MODE: 4014 4015 RX_X4_PCS_CTL0r_CLR(RX_X4_CONTROL0_PCS_CONTROL_0r_reg); 4016 RX_X4_PCS_CTL0r_DEC_TL_MODEf_SET(RX_X4_CONTROL0_PCS_CONTROL_0r_reg, or_value); 4017 PHYMOD_IF_ERR_RETURN(MODIFY_RX_X4_PCS_CTL0r(pc, RX_X4_CONTROL0_PCS_CONTROL_0r_reg)); 4018 4019 /*Set the override enable*/ 4020 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 4021 SC_X4_FLD_OVRR_EN0_TYPEr_DEC_TL_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 1); 4022 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 4023 break; 4024 case OVERRIDE_DEC_TL_MODE_DIS: 4025 /*Set the override enable*/ 4026 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 4027 SC_X4_FLD_OVRR_EN0_TYPEr_DEC_TL_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 0); 4028 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 4029 4030 break; 4031 case OVERRIDE_DESKEW_MODE: 4032 4033 RX_X4_PCS_CTL0r_CLR(RX_X4_CONTROL0_PCS_CONTROL_0r_reg); 4034 RX_X4_PCS_CTL0r_DESKEW_MODEf_SET(RX_X4_CONTROL0_PCS_CONTROL_0r_reg, or_value); 4035 PHYMOD_IF_ERR_RETURN(MODIFY_RX_X4_PCS_CTL0r(pc, RX_X4_CONTROL0_PCS_CONTROL_0r_reg)); 4036 4037 /*Set the override enable*/ 4038 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 4039 SC_X4_FLD_OVRR_EN0_TYPEr_DESKEW_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 1); 4040 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 4041 break; 4042 case OVERRIDE_DESKEW_MODE_DIS: 4043 /*Set the override enable*/ 4044 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 4045 SC_X4_FLD_OVRR_EN0_TYPEr_DESKEW_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 0); 4046 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 4047 4048 break; 4049 case OVERRIDE_DEC_FSM_MODE: 4050 4051 RX_X4_PCS_CTL0r_CLR(RX_X4_CONTROL0_PCS_CONTROL_0r_reg); 4052 RX_X4_PCS_CTL0r_DEC_FSM_MODEf_SET(RX_X4_CONTROL0_PCS_CONTROL_0r_reg, or_value); 4053 PHYMOD_IF_ERR_RETURN(MODIFY_RX_X4_PCS_CTL0r(pc, RX_X4_CONTROL0_PCS_CONTROL_0r_reg)); 4054 4055 /*Set the override enable*/ 4056 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 4057 SC_X4_FLD_OVRR_EN0_TYPEr_DEC_FSM_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 1); 4058 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 4059 break; 4060 case OVERRIDE_DEC_FSM_MODE_DIS: 4061 /*Set the override enable*/ 4062 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 4063 SC_X4_FLD_OVRR_EN0_TYPEr_DEC_FSM_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 0); 4064 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 4065 break; 4066 default: 4067 break; 4068 } 4069 return PHYMOD_E_NONE; 4070 } /* OVERRIDE_SET */ 4071 4072 /*! 4073 @brief TBD 4074 @param pc handle to current TSCF context (#PHYMOD_ST) 4075 @param per_lane_control 4076 @param per_field_override_en 4077 @returns PHYMOD_E_NONE if no errors. PHYMOD_EERROR else. 4078 @details 4079 TBD 4080 */ 4081 int tefmod_set_override_1(PHYMOD_ST* pc, int per_lane_control, uint32_t per_field_override_en) /* OVERRIDE_SET */ 4082 { 4083 int or_value; 4084 override_type_t or_en; 4085 MAIN0_SETUPr_t MAIN0_SETUPr_reg; 4086 RX_X4_BLKSYNC_CFGr_t RX_X4_CONTROL0_BLKSYNC_CONFIGr_reg; 4087 TX_X4_MISCr_t TX_X4_CONTROL0_MISCr_reg; 4088 TX_X4_CRED0r_t TX_X4_CREDIT0_CREDIT0r_reg; 4089 TX_X4_CRED1r_t TX_X4_CREDIT0_CREDIT1r_reg; 4090 TX_X4_LOOPCNTr_t TX_X4_CREDIT0_LOOPCNTr_reg; 4091 TX_X4_MAC_CREDGENCNTr_t TX_X4_CREDIT0_MAC_CREDITGENCNTr_reg; 4092 SC_X4_FLD_OVRR_EN0_TYPEr_t SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg; 4093 SC_X4_FLD_OVRR_EN1_TYPEr_t SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg; 4094 4095 TEFMOD_DBG_IN_FUNC_INFO(pc); 4096 or_en = (override_type_t) (per_field_override_en >> 16); 4097 4098 or_value = per_field_override_en & 0x0000ffff; 4099 4100 4101 switch(or_en) { 4102 case OVERRIDE_R_HG2_ENABLE: 4103 4104 TX_X4_MISCr_CLR(TX_X4_CONTROL0_MISCr_reg); 4105 TX_X4_MISCr_SET(TX_X4_CONTROL0_MISCr_reg, or_value); 4106 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_MISCr(pc, TX_X4_CONTROL0_MISCr_reg)); 4107 /*Set the override enable*/ 4108 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg); 4109 SC_X4_FLD_OVRR_EN1_TYPEr_R_HG2_ENABLE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg, 1); 4110 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg)); 4111 break; 4112 case OVERRIDE_R_HG2_ENABLE_DIS: 4113 /*Set the override enable*/ 4114 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg); 4115 SC_X4_FLD_OVRR_EN1_TYPEr_R_HG2_ENABLE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg, 0); 4116 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg)); 4117 4118 break; 4119 case OVERRIDE_BS_SM_SYNC_MODE_OEN: 4120 4121 RX_X4_BLKSYNC_CFGr_CLR(RX_X4_CONTROL0_BLKSYNC_CONFIGr_reg); 4122 RX_X4_BLKSYNC_CFGr_BS_SM_SYNC_MODEf_SET(RX_X4_CONTROL0_BLKSYNC_CONFIGr_reg, or_value); 4123 PHYMOD_IF_ERR_RETURN(MODIFY_RX_X4_BLKSYNC_CFGr(pc, RX_X4_CONTROL0_BLKSYNC_CONFIGr_reg)); 4124 4125 /*Set the override enable*/ 4126 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg); 4127 SC_X4_FLD_OVRR_EN1_TYPEr_BS_SM_SYNC_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg, 1); 4128 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg)); 4129 break; 4130 case OVERRIDE_BS_SM_SYNC_MODE_OEN_DIS: 4131 /*Set the override enable*/ 4132 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg); 4133 SC_X4_FLD_OVRR_EN1_TYPEr_BS_SM_SYNC_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg, 0); 4134 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg)); 4135 4136 break; 4137 case OVERRIDE_BS_SYNC_EN_OEN: 4138 4139 RX_X4_BLKSYNC_CFGr_CLR(RX_X4_CONTROL0_BLKSYNC_CONFIGr_reg); 4140 RX_X4_BLKSYNC_CFGr_BS_SYNC_ENf_SET(RX_X4_CONTROL0_BLKSYNC_CONFIGr_reg, or_value); 4141 PHYMOD_IF_ERR_RETURN(MODIFY_RX_X4_BLKSYNC_CFGr(pc, RX_X4_CONTROL0_BLKSYNC_CONFIGr_reg)); 4142 4143 /*Set the override enable*/ 4144 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg); 4145 SC_X4_FLD_OVRR_EN1_TYPEr_BS_SYNC_EN_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg, 1); 4146 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg)); 4147 break; 4148 case OVERRIDE_BS_SYNC_EN_OEN_DIS: 4149 /*Set the override enable*/ 4150 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg); 4151 SC_X4_FLD_OVRR_EN1_TYPEr_BS_SYNC_EN_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg, 0); 4152 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg)); 4153 4154 4155 break; 4156 case OVERRIDE_BS_DIST_MODE_OEN: 4157 RX_X4_BLKSYNC_CFGr_CLR(RX_X4_CONTROL0_BLKSYNC_CONFIGr_reg); 4158 RX_X4_BLKSYNC_CFGr_BS_DIST_MODEf_SET(RX_X4_CONTROL0_BLKSYNC_CONFIGr_reg, or_value); 4159 PHYMOD_IF_ERR_RETURN(MODIFY_RX_X4_BLKSYNC_CFGr(pc, RX_X4_CONTROL0_BLKSYNC_CONFIGr_reg)); 4160 4161 /*Set the override enable*/ 4162 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg); 4163 SC_X4_FLD_OVRR_EN1_TYPEr_BS_DIST_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg, 1); 4164 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg)); 4165 break; 4166 case OVERRIDE_BS_DIST_MODE_OEN_DIS: 4167 /*Set the override enable*/ 4168 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg); 4169 SC_X4_FLD_OVRR_EN1_TYPEr_BS_DIST_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg, 0); 4170 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg)); 4171 4172 break; 4173 case OVERRIDE_BS_BTMX_MODE_OEN: 4174 RX_X4_BLKSYNC_CFGr_CLR(RX_X4_CONTROL0_BLKSYNC_CONFIGr_reg); 4175 RX_X4_BLKSYNC_CFGr_BS_BTMX_MODEf_SET(RX_X4_CONTROL0_BLKSYNC_CONFIGr_reg, or_value); 4176 PHYMOD_IF_ERR_RETURN(MODIFY_RX_X4_BLKSYNC_CFGr(pc, RX_X4_CONTROL0_BLKSYNC_CONFIGr_reg)); 4177 4178 /*Set the override enable*/ 4179 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg); 4180 SC_X4_FLD_OVRR_EN1_TYPEr_BS_BTMX_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg, 1); 4181 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg)); 4182 break; 4183 case OVERRIDE_BS_BTMX_MODE_OEN_DIS: 4184 /*Set the override enable*/ 4185 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg); 4186 SC_X4_FLD_OVRR_EN1_TYPEr_BS_BTMX_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg, 0); 4187 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg)); 4188 4189 break; 4190 case OVERRIDE_CL72_EN: 4191 MAIN0_SETUPr_CLR(MAIN0_SETUPr_reg); 4192 MAIN0_SETUPr_CL72_ENf_SET(MAIN0_SETUPr_reg, or_value); 4193 PHYMOD_IF_ERR_RETURN(MODIFY_MAIN0_SETUPr(pc, MAIN0_SETUPr_reg)); 4194 4195 /*Set the override enable*/ 4196 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 4197 SC_X4_FLD_OVRR_EN0_TYPEr_CL72_EN_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 1); 4198 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 4199 break; 4200 case OVERRIDE_CL72_EN_DIS: 4201 /*Set the override enable*/ 4202 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 4203 SC_X4_FLD_OVRR_EN0_TYPEr_CL72_EN_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 0); 4204 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 4205 4206 break; 4207 case OVERRIDE_CLOCKCNT0: 4208 4209 TX_X4_CRED0r_CLR(TX_X4_CREDIT0_CREDIT0r_reg); 4210 TX_X4_CRED0r_CLOCKCNT0f_SET(TX_X4_CREDIT0_CREDIT0r_reg, or_value); 4211 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_CRED0r(pc, TX_X4_CREDIT0_CREDIT0r_reg)); 4212 4213 /*Set the override enable*/ 4214 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg); 4215 SC_X4_FLD_OVRR_EN1_TYPEr_CLOCKCNT0_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg, 1); 4216 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg)); 4217 break; 4218 case OVERRIDE_CLOCKCNT0_DIS: 4219 /*Set the override enable*/ 4220 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg); 4221 SC_X4_FLD_OVRR_EN1_TYPEr_CLOCKCNT0_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg, 0); 4222 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg)); 4223 4224 break; 4225 case OVERRIDE_CLOCKCNT1: 4226 TX_X4_CRED1r_CLR(TX_X4_CREDIT0_CREDIT1r_reg); 4227 TX_X4_CRED1r_CLOCKCNT1f_SET(TX_X4_CREDIT0_CREDIT1r_reg, or_value); 4228 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_CRED1r(pc, TX_X4_CREDIT0_CREDIT1r_reg)); 4229 4230 /*Set the override enable*/ 4231 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg); 4232 SC_X4_FLD_OVRR_EN1_TYPEr_CLOCKCNT1_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg, 1); 4233 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg)); 4234 break; 4235 case OVERRIDE_CLOCKCNT1_DIS: 4236 /*Set the override enable*/ 4237 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg); 4238 SC_X4_FLD_OVRR_EN1_TYPEr_CLOCKCNT1_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg, 0); 4239 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg)); 4240 4241 break; 4242 case OVERRIDE_LOOPCNT0: 4243 TX_X4_LOOPCNTr_CLR(TX_X4_CREDIT0_LOOPCNTr_reg); 4244 TX_X4_LOOPCNTr_LOOPCNT0f_SET(TX_X4_CREDIT0_LOOPCNTr_reg, or_value); 4245 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_LOOPCNTr(pc, TX_X4_CREDIT0_LOOPCNTr_reg)); 4246 4247 /*Set the override enable*/ 4248 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg); 4249 SC_X4_FLD_OVRR_EN1_TYPEr_LOOPCNT0_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg, 1); 4250 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg)); 4251 break; 4252 case OVERRIDE_LOOPCNT0_DIS: 4253 /*Set the override enable*/ 4254 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg); 4255 SC_X4_FLD_OVRR_EN1_TYPEr_LOOPCNT0_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg, 0); 4256 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg)); 4257 4258 break; 4259 case OVERRIDE_LOOPCNT1: 4260 TX_X4_LOOPCNTr_CLR(TX_X4_CREDIT0_LOOPCNTr_reg); 4261 TX_X4_LOOPCNTr_LOOPCNT1f_SET(TX_X4_CREDIT0_LOOPCNTr_reg, or_value); 4262 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_LOOPCNTr(pc, TX_X4_CREDIT0_LOOPCNTr_reg)); 4263 4264 /*Set the override enable*/ 4265 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg); 4266 SC_X4_FLD_OVRR_EN1_TYPEr_LOOPCNT1_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg, 1); 4267 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg)); 4268 break; 4269 case OVERRIDE_LOOPCNT1_DIS: 4270 /*Set the override enable*/ 4271 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg); 4272 SC_X4_FLD_OVRR_EN1_TYPEr_LOOPCNT1_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg, 0); 4273 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg)); 4274 4275 break; 4276 case OVERRIDE_MAC_CREDITGENCNT: 4277 TX_X4_MAC_CREDGENCNTr_CLR(TX_X4_CREDIT0_MAC_CREDITGENCNTr_reg); 4278 TX_X4_MAC_CREDGENCNTr_MAC_CREDITGENCNTf_SET(TX_X4_CREDIT0_MAC_CREDITGENCNTr_reg, or_value); 4279 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_MAC_CREDGENCNTr(pc, TX_X4_CREDIT0_MAC_CREDITGENCNTr_reg)); 4280 4281 /*Set the override enable*/ 4282 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg); 4283 SC_X4_FLD_OVRR_EN1_TYPEr_MAC_CREDITGENCNT_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg, 1); 4284 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg)); 4285 break; 4286 case OVERRIDE_MAC_CREDITGENCNT_DIS: 4287 /*Set the override enable*/ 4288 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg); 4289 SC_X4_FLD_OVRR_EN1_TYPEr_MAC_CREDITGENCNT_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg, 0); 4290 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg)); 4291 default: 4292 break; 4293 } 4294 return PHYMOD_E_NONE; 4295 } /* OVERRIDE_SET */ 4296 4297 /*! 4298 @brief Enable / Disable credits for any particular lane 4299 @param pc handle to current TSCF context (#PHYMOD_ST) 4300 @param per_lane_control Control to enable or disable credits 4301 @returns The value PHYMOD_E_NONE upon successful completion. 4302 @details 4303 This function is used to enable or disable the credit generation. 4304 4305 \li set to 0x1 to enable credit 4306 \li Set to 0x0 disable credit for selected lane. 4307 4308 This function reads/modifies the following registers: 4309 4310 \li enable credits: clockcnt0 (0xC100[14]) 4311 */ 4312 int tefmod_credit_control(PHYMOD_ST* pc, int per_lane_control) /* CREDIT_CONTROL */ 4313 { 4314 int cntl; 4315 TX_X4_CRED0r_t TX_X4_CREDIT0_CREDIT0r_reg; 4316 cntl = per_lane_control; 4317 4318 TEFMOD_DBG_IN_FUNC_INFO(pc); 4319 TX_X4_CRED0r_CLR(TX_X4_CREDIT0_CREDIT0r_reg); 4320 if (cntl) { /* enable credits */ 4321 TX_X4_CRED0r_CREDITENABLEf_SET(TX_X4_CREDIT0_CREDIT0r_reg, 1); 4322 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_CRED0r(pc, TX_X4_CREDIT0_CREDIT0r_reg)); 4323 } else { /* disable credits */ 4324 TX_X4_CRED0r_CREDITENABLEf_SET(TX_X4_CREDIT0_CREDIT0r_reg, 0); 4325 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_CRED0r(pc, TX_X4_CREDIT0_CREDIT0r_reg)); 4326 } 4327 return PHYMOD_E_NONE; 4328 } 4329 4330 /*! 4331 @brief tx lane reset and enable of any particular lane 4332 @param pc handle to current TSCF context (#PHYMOD_ST) 4333 @param tx_dis_type tx property to control, see enum #tefmod_tx_disable_enum_t 4334 @returns The value PHYMOD_E_NONE upon successful completion. 4335 @details 4336 This function is used to reset tx lane and enable/disable tx lane of any 4337 transmit lane. Set bit 0 of per_lane_control to enable the TX_LANE 4338 (1) or disable the TX lane (0). 4339 When diable TX lane, two types of operations are inovked independently. 4340 If per_lane_control bit [7:4] = 1, only traffic is disabled. 4341 (TEFMOD_TX_LANE_TRAFFIC =0x10) 4342 If bit [7:4] = 2, only reset function is invoked. 4343 (TEFMOD_TX_LANE_RESET = 0x20) 4344 4345 This function reads/modifies the following registers: 4346 4347 \li rstb_tx_lane : 0xc113[1] 4348 \li enable_tx_lane: 0xc113[0] 4349 */ 4350 4351 int tefmod_tx_lane_control_set(PHYMOD_ST* pc, tefmod_tx_disable_enum_t tx_dis_type) /* TX_LANE_CONTROL */ 4352 { 4353 TX_X4_MISCr_t TX_X4_CONTROL0_MISCr_reg; 4354 4355 TEFMOD_DBG_IN_FUNC_INFO(pc); 4356 TX_X4_MISCr_CLR(TX_X4_CONTROL0_MISCr_reg); 4357 4358 switch(tx_dis_type) { 4359 case TEFMOD_TX_LANE_RESET: 4360 TX_X4_MISCr_RSTB_TX_LANEf_SET(TX_X4_CONTROL0_MISCr_reg, 0); 4361 PHYMOD_IF_ERR_RETURN (MODIFY_TX_X4_MISCr(pc, TX_X4_CONTROL0_MISCr_reg)); 4362 TX_X4_MISCr_CLR(TX_X4_CONTROL0_MISCr_reg); 4363 TX_X4_MISCr_RSTB_TX_LANEf_SET(TX_X4_CONTROL0_MISCr_reg, 1); 4364 PHYMOD_IF_ERR_RETURN (MODIFY_TX_X4_MISCr(pc, TX_X4_CONTROL0_MISCr_reg)); 4365 break; 4366 case TEFMOD_TX_LANE_TRAFFIC_ENABLE: 4367 TX_X4_MISCr_ENABLE_TX_LANEf_SET(TX_X4_CONTROL0_MISCr_reg, 1); 4368 PHYMOD_IF_ERR_RETURN (MODIFY_TX_X4_MISCr(pc, TX_X4_CONTROL0_MISCr_reg)); 4369 break; 4370 case TEFMOD_TX_LANE_TRAFFIC_DISABLE: 4371 TX_X4_MISCr_ENABLE_TX_LANEf_SET(TX_X4_CONTROL0_MISCr_reg, 0); 4372 PHYMOD_IF_ERR_RETURN (MODIFY_TX_X4_MISCr(pc, TX_X4_CONTROL0_MISCr_reg)); 4373 break; 4374 case TEFMOD_TX_LANE_RESET_TRAFFIC_ENABLE: 4375 TX_X4_MISCr_RSTB_TX_LANEf_SET(TX_X4_CONTROL0_MISCr_reg, 1); 4376 PHYMOD_IF_ERR_RETURN (MODIFY_TX_X4_MISCr(pc, TX_X4_CONTROL0_MISCr_reg)); 4377 TX_X4_MISCr_CLR(TX_X4_CONTROL0_MISCr_reg); 4378 TX_X4_MISCr_ENABLE_TX_LANEf_SET(TX_X4_CONTROL0_MISCr_reg, 1); 4379 PHYMOD_IF_ERR_RETURN (MODIFY_TX_X4_MISCr(pc, TX_X4_CONTROL0_MISCr_reg)); 4380 break; 4381 case TEFMOD_TX_LANE_RESET_TRAFFIC_DISABLE: 4382 TX_X4_MISCr_RSTB_TX_LANEf_SET(TX_X4_CONTROL0_MISCr_reg, 0); 4383 PHYMOD_IF_ERR_RETURN (MODIFY_TX_X4_MISCr(pc, TX_X4_CONTROL0_MISCr_reg)); 4384 TX_X4_MISCr_CLR(TX_X4_CONTROL0_MISCr_reg); 4385 TX_X4_MISCr_ENABLE_TX_LANEf_SET(TX_X4_CONTROL0_MISCr_reg, 0); 4386 PHYMOD_IF_ERR_RETURN (MODIFY_TX_X4_MISCr(pc, TX_X4_CONTROL0_MISCr_reg)); 4387 break; 4388 default: 4389 break; 4390 } 4391 4392 return PHYMOD_E_NONE; 4393 } 4394 4395 /*! 4396 @brief tx lane reset and enable of any particular lane 4397 @param pc handle to current TSCF context (#PHYMOD_ST) 4398 @param reset gets the configured tx rstb 4399 @param enable gets the configured tx enable 4400 @returns The value PHYMOD_E_NONE upon successful completion. 4401 @details 4402 This function reads the following registers: 4403 4404 \li rstb_tx_lane : 0xc113[1] 4405 \li enable_tx_lane: 0xc113[0] 4406 */ 4407 int tefmod_tx_lane_control_get(PHYMOD_ST* pc, int *reset, int *enable) /* TX_LANE_CONTROL */ 4408 { 4409 TX_X4_MISCr_t TX_X4_CONTROL0_MISCr_reg; 4410 4411 TEFMOD_DBG_IN_FUNC_INFO(pc); 4412 TX_X4_MISCr_CLR(TX_X4_CONTROL0_MISCr_reg); 4413 4414 PHYMOD_IF_ERR_RETURN (READ_TX_X4_MISCr(pc, &TX_X4_CONTROL0_MISCr_reg)); 4415 4416 *reset = TX_X4_MISCr_RSTB_TX_LANEf_GET(TX_X4_CONTROL0_MISCr_reg); 4417 *enable = TX_X4_MISCr_ENABLE_TX_LANEf_GET(TX_X4_CONTROL0_MISCr_reg); 4418 4419 return PHYMOD_E_NONE; 4420 } 4421 4422 4423 /*! 4424 @brief rx lane reset and enable of any particular lane 4425 @param pc handle to current TSCF context (#PHYMOD_ST) 4426 @param accData TBD 4427 @param per_lane_control TBD 4428 @returns The value PHYMOD_E_NONE upon successful completion. 4429 @details 4430 This function enables/disables rx lane (RSTB_LANE) or read back control bit for 4431 that based on per_lane_control being 1 or 0. If per_lane_control is 0xa, only 4432 read back RSTB_LANE. 4433 \li select encodeMode 4434 This function reads/modifies the following registers: 4435 \li rstb_rx_lane : 0xc137[0] 4436 */ 4437 /* coverity[param_set_but_not_used] */ 4438 int tefmod_rx_lane_control(PHYMOD_ST* pc, int accData, int per_lane_control) /* RX_LANE_CONTROL */ 4439 { 4440 int cntl; 4441 RX_X4_PMA_CTL0r_t RX_X4_CONTROL0_PMA_CONTROL_0r_reg; 4442 /* coverity */ 4443 accData = accData; 4444 4445 TEFMOD_DBG_IN_FUNC_INFO(pc); 4446 cntl = per_lane_control; 4447 4448 #ifdef _DV_TB_ 4449 PHYMOD_DEBUG_ERROR(("%-22s u=%0d p=%0d sel=%x ln=%0d dxgxs=%0d cntl=%x\n", __func__, 4450 pc->unit, pc->port, pc->lane_select, pc->this_lane, pc->dxgxs, cntl)); 4451 #endif 4452 RX_X4_PMA_CTL0r_CLR(RX_X4_CONTROL0_PMA_CONTROL_0r_reg); 4453 if (cntl==0xa) { 4454 /* set encoder */ 4455 PHYMOD_IF_ERR_RETURN(READ_RX_X4_PMA_CTL0r(pc, &RX_X4_CONTROL0_PMA_CONTROL_0r_reg)); 4456 if(RX_X4_PMA_CTL0r_RSTB_LANEf_GET(RX_X4_CONTROL0_PMA_CONTROL_0r_reg)) 4457 accData =1; 4458 else 4459 accData =0; 4460 } else if (cntl) { 4461 /* set encoder */ 4462 RX_X4_PMA_CTL0r_RSTB_LANEf_SET(RX_X4_CONTROL0_PMA_CONTROL_0r_reg, 1); 4463 PHYMOD_IF_ERR_RETURN(MODIFY_RX_X4_PMA_CTL0r(pc, RX_X4_CONTROL0_PMA_CONTROL_0r_reg)); 4464 } else { 4465 /* bit set to 0 for disabling RXP */ 4466 RX_X4_PMA_CTL0r_RSTB_LANEf_SET(RX_X4_CONTROL0_PMA_CONTROL_0r_reg, 0); 4467 PHYMOD_IF_ERR_RETURN(MODIFY_RX_X4_PMA_CTL0r(pc, RX_X4_CONTROL0_PMA_CONTROL_0r_reg)); 4468 } 4469 return PHYMOD_E_NONE; 4470 } 4471 4472 #ifdef _DV_TB_ 4473 /*! 4474 @brief set broadcast enable and broadcast address 4475 4476 @param pc handle to current TSCF context (#PHYMOD_ST) 4477 4478 @returns The value PHYMOD_E_NONE upon successful completion. 4479 */ 4480 4481 int tefmod_bypass_sc(PHYMOD_ST* pc) /* BYPASS_SC */ 4482 { 4483 uint16_t bypass_en, fild_override_enable0, fild_override_enable1; 4484 SC_X4_BYPASSr_t SC_X4_CONTROL_BYPASSr_reg; 4485 SC_X4_FLD_OVRR_EN0_TYPEr_t SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg; 4486 SC_X4_FLD_OVRR_EN1_TYPEr_t SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg; 4487 4488 TEFMOD_DBG_IN_FUNC_INFO(pc); 4489 bypass_en = 0xf; 4490 fild_override_enable0 = 0xffff; 4491 fild_override_enable1 = 0xfff0; 4492 4493 SC_X4_BYPASSr_CLR(SC_X4_CONTROL_BYPASSr_reg); 4494 SC_X4_BYPASSr_SC_BYPASSf_SET(SC_X4_CONTROL_BYPASSr_reg, bypass_en); 4495 4496 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_BYPASSr(pc, SC_X4_CONTROL_BYPASSr_reg)); 4497 4498 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 4499 SC_X4_FLD_OVRR_EN0_TYPEr_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, fild_override_enable0); 4500 PHYMOD_IF_ERR_RETURN 4501 (MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 4502 4503 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg); 4504 SC_X4_FLD_OVRR_EN1_TYPEr_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg, fild_override_enable1); 4505 PHYMOD_IF_ERR_RETURN 4506 (MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg)); 4507 return PHYMOD_E_NONE; 4508 } 4509 #endif /* _DV_TB_ */ 4510 4511 /*! 4512 @brief Read the 16 bit rev. id value etc. 4513 @param pc handle to current TSCF context (#PHYMOD_ST) 4514 @param revIdV receives the revid 4515 @returns The value of the revid. 4516 @details 4517 This fucntion reads the revid register that contains core number, revision 4518 number and returns it. 4519 */ 4520 int tefmod_revid_read(PHYMOD_ST* pc, uint32_t *revIdV) /* REVID_READ */ 4521 { 4522 #ifdef _DV_TB_ 4523 int laneselect; 4524 #endif 4525 TEFMOD_DBG_IN_FUNC_INFO(pc); 4526 #ifdef _DV_TB_ 4527 laneselect = pc->lane_select; 4528 pc->lane_select=TEFMOD_LANE_0_0_0_1; 4529 4530 PHYMOD_DEBUG_ERROR(("%-22s u=%0d p=%0d sel=%x ln=%0d dxgxs=%0d\n", __func__, 4531 pc->unit, pc->port, pc->lane_select, pc->this_lane, pc->dxgxs)); 4532 #endif 4533 *revIdV=_tefmod_getRevDetails(pc); 4534 #ifdef _DV_TB_ 4535 pc->lane_select=laneselect; 4536 #endif 4537 return PHYMOD_E_NONE; 4538 } 4539 4540 #ifdef _DV_TB_ 4541 /*! 4542 @brief Control per lane clause 72 auto tuning function (training patterns) 4543 @param pc handle to current TSCF context (#PHYMOD_ST) 4544 @returns The value PHYMOD_E_NONE upon successful completion 4545 @details 4546 4547 This function enables/disables clause-72 auto-tuning per lane. It is used 4548 in 40G_KR4, 40G_CR4, 10G_KR modes etc. 4549 Lane is selected via #PHYMOD_ST::lane_select. 4550 This Function is controlled by #PHYMOD_ST::per_lane_control as follows. 4551 4552 \li 0Xxxxxxxx3 (b11): Enable CL72 hardware block 4553 \li 0Xxxxxxxx2 (b01): Disable CL72 hardware block 4554 \li 0Xxxxxxxx0 (b00): no changed. 4555 \li 0Xxxxxxx3- (b011----): Forced enable CL72 under AN. 4556 \li 0Xxxxxxx7- (b111----): Forced disable CL72 under AN. 4557 \li 0Xxxxxxx1- (b001----): Default CL72 under AN. 4558 \li 0Xxxxxxx0- (b000----): no changed 4559 \li 0Xxxxxx100 : read back CL72 HW en bit and put in accData. 4560 4561 This function modifies the following registers: 4562 4563 \li DEV1_IEEE9_PMD_10GBASE_KR_PMD_CONTROL_REGISTER_150 (0x0800_0096) 4564 \li CL72_MISC1_CONTROL (0xc253) 4565 4566 */ 4567 4568 /* XX int tefmod_clause72_control(PHYMOD_ST* pc) { only for DV ? CHECK Lpti*/ 4569 int tefmod_clause72_control(PHYMOD_ST* pc, int cl72en) /* CLAUSE_72_CONTROL */ 4570 { 4571 int cntl; 4572 #ifdef _DV_TB_ 4573 int tmp_port_type; 4574 #endif 4575 int cl72_restart, cl72_enable; 4576 CL93N72_IT_BASE_R_PMD_CTLr_t CL93N72_IEEE_TX_CL93N72IT_BASE_R_PMD_CONTROLr_reg; 4577 SC_X4_CTLr_t SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg; 4578 CL93N72_UR_CTL0r_t CL93N72_USER_RX_CL93N72UR_CONTROL0r_reg; 4579 4580 TEFMOD_DBG_IN_FUNC_INFO(pc); 4581 cntl = cl72en; 4582 cl72_restart = cntl & 0x1; 4583 cl72_enable = (cntl & 0x2) ? 1 : 0; 4584 4585 #ifdef _DV_TB_ 4586 if(pc->verbosity) 4587 PHYMOD_DEBUG_ERROR(("%-22s: port %0d cl72_restart %0d cl72_en %0d\n", __func__, pc->this_lane, cl72_restart, cl72_enable)); 4588 #endif 4589 CL93N72_IT_BASE_R_PMD_CTLr_CLR(CL93N72_IEEE_TX_CL93N72IT_BASE_R_PMD_CONTROLr_reg); 4590 4591 CL93N72_IT_BASE_R_PMD_CTLr_CL93N72_IEEE_RESTART_TRAININGf_SET(CL93N72_IEEE_TX_CL93N72IT_BASE_R_PMD_CONTROLr_reg, cl72_restart); 4592 CL93N72_IT_BASE_R_PMD_CTLr_CL93N72_IEEE_TRAINING_ENABLEf_SET(CL93N72_IEEE_TX_CL93N72IT_BASE_R_PMD_CONTROLr_reg, cl72_enable); 4593 4594 PHYMOD_IF_ERR_RETURN(MODIFY_CL93N72_IT_BASE_R_PMD_CTLr(pc, CL93N72_IEEE_TX_CL93N72IT_BASE_R_PMD_CONTROLr_reg)); 4595 4596 4597 CL93N72_UR_CTL0r_CLR(CL93N72_USER_RX_CL93N72UR_CONTROL0r_reg); 4598 PHYMOD_IF_ERR_RETURN(READ_CL93N72_UR_CTL0r(pc, &CL93N72_USER_RX_CL93N72UR_CONTROL0r_reg)); 4599 4600 4601 CL93N72_UR_CTL0r_CL93N72_RX_TRAINING_ENf_SET(CL93N72_USER_RX_CL93N72UR_CONTROL0r_reg, 1); 4602 PHYMOD_IF_ERR_RETURN(WRITE_CL93N72_UR_CTL0r(pc, CL93N72_USER_RX_CL93N72UR_CONTROL0r_reg)); 4603 4604 if(cl72_restart) { 4605 #ifdef _DV_TB_ 4606 tmp_port_type = port_type; 4607 port_type = TEFMOD_MULTI_PORT; 4608 #endif 4609 4610 SC_X4_CTLr_CLR(SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg); 4611 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg, 0); 4612 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_CTLr(pc, SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg)); 4613 4614 SC_X4_CTLr_CLR(SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg); 4615 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg, 1); 4616 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_CTLr(pc, SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg)); 4617 4618 #ifdef _DV_TB_ 4619 port_type = tmp_port_type; 4620 #endif 4621 } 4622 return PHYMOD_E_NONE; 4623 } /* CLAUSE_72_CONTROL */ 4624 #endif /* _DV_TB_ */ 4625 4626 #ifdef _SDK_TEFMOD_ 4627 int tefmod_clause72_control(PHYMOD_ST* pc, int cl72en) /* CLAUSE_72_CONTROL */ 4628 { 4629 int cl72_enable; 4630 SC_X4_CTLr_t SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg; 4631 CL93N72_IT_BASE_R_PMD_CTLr_t CL93N72_IEEE_TX_CL93N72IT_BASE_R_PMD_CONTROLr_reg; 4632 4633 4634 int start_lane = 0, num_lane = 0 , i=0; 4635 uint32_t enable = 0; 4636 phymod_access_t pa_copy; 4637 4638 TEFMOD_DBG_IN_FUNC_INFO(pc); 4639 cl72_enable = cl72en & 0x1; 4640 4641 /* need to figure out what's the starting lane */ 4642 PHYMOD_MEMCPY(&pa_copy, pc, sizeof(pa_copy)); 4643 PHYMOD_IF_ERR_RETURN 4644 (phymod_util_lane_config_get(pc, &start_lane, &num_lane)); 4645 pa_copy.lane_mask = 0x1 << start_lane; 4646 4647 4648 CL93N72_IT_BASE_R_PMD_CTLr_CLR(CL93N72_IEEE_TX_CL93N72IT_BASE_R_PMD_CONTROLr_reg); 4649 PHYMOD_IF_ERR_RETURN(READ_CL93N72_IT_BASE_R_PMD_CTLr(&pa_copy, &CL93N72_IEEE_TX_CL93N72IT_BASE_R_PMD_CONTROLr_reg)); 4650 4651 if(CL93N72_IT_BASE_R_PMD_CTLr_CL93N72_IEEE_TRAINING_ENABLEf_GET(CL93N72_IEEE_TX_CL93N72IT_BASE_R_PMD_CONTROLr_reg) != (uint32_t)cl72_enable) { 4652 4653 for (i = (num_lane-1); i >= 0; i--) { 4654 pa_copy.lane_mask = 0x1 << (i + start_lane); 4655 CL93N72_IT_BASE_R_PMD_CTLr_CLR(CL93N72_IEEE_TX_CL93N72IT_BASE_R_PMD_CONTROLr_reg); 4656 PHYMOD_IF_ERR_RETURN(READ_CL93N72_IT_BASE_R_PMD_CTLr(&pa_copy, &CL93N72_IEEE_TX_CL93N72IT_BASE_R_PMD_CONTROLr_reg)); 4657 CL93N72_IT_BASE_R_PMD_CTLr_CL93N72_IEEE_TRAINING_ENABLEf_SET(CL93N72_IEEE_TX_CL93N72IT_BASE_R_PMD_CONTROLr_reg, cl72_enable); 4658 4659 PHYMOD_IF_ERR_RETURN(MODIFY_CL93N72_IT_BASE_R_PMD_CTLr(&pa_copy, CL93N72_IEEE_TX_CL93N72IT_BASE_R_PMD_CONTROLr_reg)); 4660 } 4661 4662 pa_copy.lane_mask = 0x1 << start_lane; 4663 tefmod_disable_get(&pa_copy,&enable); 4664 if(enable == 0x1) { 4665 SC_X4_CTLr_CLR(SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg); 4666 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg, 0); 4667 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_CTLr(pc, SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg)); 4668 4669 SC_X4_CTLr_CLR(SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg); 4670 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg, 1); 4671 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_CTLr(&pa_copy, SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg)); 4672 } 4673 } 4674 4675 return PHYMOD_E_NONE; 4676 } /* CLAUSE_72_CONTROL */ 4677 #endif /* _SDK_TEFMOD_ */ 4678 4679 #ifdef _DV_TB_ 4680 /*! 4681 @brief Check PRBS sync status 4682 @param pc handle to current TSCF context (#PHYMOD_ST) 4683 @returns PHYMOD_E_NONE if prbs lock with no errors; 4684 PHYMOD_ETIMEOUT for a timeout, 4685 @details 4686 This function reads from one of PATGEN0_PRBSSTAT0 register within 4 lanes. 4687 Retunr value reads 0x8000, meaning that prbs has locked and there are no 4688 prbs errors, OR no lock (bit[15]=0) or errors (bit[14:0]!=0) 4689 4690 The errors are stored in #PHYMOD_ST::accData, as -2 if lost lock, -1 if no lock, 4691 0 is locked and error free. 1-n means erros found. 4692 4693 \li PATGEN0_PRBSSTAT0 (0xC032) 4694 \li PATGEN0_PRBSSTAT1 (0xC033) 4695 \li PATGEN0_TESTMISCSTATUSr (0xC034) 4696 */ 4697 int tefmod_prbs_check(PHYMOD_ST* pc, int accData) 4698 { 4699 uint16_t dataL, dataH; 4700 int lock, lock_lost, err; 4701 TLB_RX_PRBS_CHK_LOCK_STSr_t TLB_RX_PRBS_CHK_LOCK_STATUSr_reg; 4702 TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr_t TLB_RX_PRBS_CHK_ERR_CNT_MSB_STATUSr_reg; 4703 TLB_RX_PRBS_CHK_ERR_CNT_LSB_STSr_t TLB_RX_PRBS_CHK_ERR_CNT_LSB_STATUSr_reg; 4704 4705 TEFMOD_DBG_IN_FUNC_INFO(pc); 4706 TLB_RX_PRBS_CHK_LOCK_STSr_CLR(TLB_RX_PRBS_CHK_LOCK_STATUSr_reg); 4707 TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr_CLR(TLB_RX_PRBS_CHK_ERR_CNT_MSB_STATUSr_reg); 4708 TLB_RX_PRBS_CHK_ERR_CNT_LSB_STSr_CLR(TLB_RX_PRBS_CHK_ERR_CNT_LSB_STATUSr_reg); 4709 4710 PHYMOD_IF_ERR_RETURN 4711 (READ_TLB_RX_PRBS_CHK_LOCK_STSr(pc, &TLB_RX_PRBS_CHK_LOCK_STATUSr_reg)); 4712 PHYMOD_IF_ERR_RETURN 4713 (READ_TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr(pc, &TLB_RX_PRBS_CHK_ERR_CNT_MSB_STATUSr_reg)); 4714 PHYMOD_IF_ERR_RETURN 4715 (READ_TLB_RX_PRBS_CHK_ERR_CNT_LSB_STSr(pc, &TLB_RX_PRBS_CHK_ERR_CNT_LSB_STATUSr_reg)); 4716 4717 dataH = TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr_GET(TLB_RX_PRBS_CHK_ERR_CNT_MSB_STATUSr_reg); 4718 dataL = TLB_RX_PRBS_CHK_ERR_CNT_LSB_STSr_GET(TLB_RX_PRBS_CHK_ERR_CNT_LSB_STATUSr_reg); 4719 4720 lock = (TLB_RX_PRBS_CHK_LOCK_STSr_PRBS_CHK_LOCKf_GET(TLB_RX_PRBS_CHK_LOCK_STATUSr_reg)) ? 1 : 0; 4721 lock_lost = (TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr_PRBS_CHK_LOCK_LOST_LHf_GET(TLB_RX_PRBS_CHK_ERR_CNT_MSB_STATUSr_reg)) ? 1 : 0; 4722 4723 err = TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr_PRBS_CHK_ERR_CNT_MSBf_GET(TLB_RX_PRBS_CHK_ERR_CNT_MSB_STATUSr_reg); 4724 4725 err = (err << 16) | TLB_RX_PRBS_CHK_ERR_CNT_LSB_STSr_GET(TLB_RX_PRBS_CHK_ERR_CNT_LSB_STATUSr_reg); 4726 4727 if (TLB_RX_PRBS_CHK_LOCK_STSr_PRBS_CHK_LOCKf_GET(TLB_RX_PRBS_CHK_LOCK_STATUSr_reg)) { 4728 if (TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr_PRBS_CHK_LOCK_LOST_LHf_GET(TLB_RX_PRBS_CHK_ERR_CNT_MSB_STATUSr_reg)) { 4729 /* locked now but lost before */ 4730 accData = TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr_PRBS_CHK_ERR_CNT_MSBf_GET(TLB_RX_PRBS_CHK_ERR_CNT_MSB_STATUSr_reg); 4731 accData = (accData << 16) | dataL | 1 ; /* locked once, so one error at least */ 4732 } else { 4733 accData = dataH; 4734 accData = (accData << 16)| dataL; 4735 } 4736 } else { 4737 if (TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr_PRBS_CHK_LOCK_LOST_LHf_GET(TLB_RX_PRBS_CHK_ERR_CNT_MSB_STATUSr_reg)) { 4738 accData = -2; /* locked before but lost now */ 4739 } else { 4740 accData = -1; /* never locked */ 4741 } 4742 } 4743 return PHYMOD_E_NONE; 4744 } 4745 #endif /* _DV_TB_ */ 4746 4747 #ifdef _DV_TB_ 4748 /*! 4749 @brief program the prbs settings 4750 @param pc handle to current TSCF context (#PHYMOD_ST) 4751 @returns The vluae PHYMOD_E_NONE upon successful completion 4752 @details 4753 The 1st byte of #PHYMOD_ST::per_lane_control is for TX and 3rd byte is 4754 for RX. The bits of each byte control their 4755 lanes as follows. 4756 4757 \li 3:3 invert_data 4758 \li 2:0 polynomial mode (prbs7, prbs9, prbs11, prbs15, prbs23, prbs31, prbs58). 4759 */ 4760 int tefmod_prbs_mode(PHYMOD_ST* pc, int per_lane_control) /* PRBS_MODE */ 4761 { 4762 int prbs_check_mode; 4763 int prbs_sel_tx, prbs_inv_tx; 4764 int prbs_sel_rx, prbs_inv_rx; 4765 TLB_RX_PRBS_CHK_CFGr_t TLB_RX_PRBS_CHK_CONFIGr_reg; 4766 TLB_TX_PRBS_GEN_CFGr_t TLB_TX_PRBS_GEN_CONFIGr_reg; 4767 4768 TEFMOD_DBG_IN_FUNC_INFO(pc); 4769 prbs_check_mode = (per_lane_control & 0x70000) >> 16; 4770 prbs_sel_rx = (per_lane_control & 0x700) >> 8; 4771 prbs_inv_rx = (per_lane_control & 0x800) >> 8; 4772 prbs_sel_tx = per_lane_control & 0x7; 4773 prbs_inv_tx = per_lane_control & 0x8; 4774 4775 TLB_TX_PRBS_GEN_CFGr_CLR(TLB_TX_PRBS_GEN_CONFIGr_reg); 4776 TLB_TX_PRBS_GEN_CFGr_PRBS_GEN_INVf_SET(TLB_TX_PRBS_GEN_CONFIGr_reg, prbs_inv_tx); 4777 TLB_TX_PRBS_GEN_CFGr_PRBS_GEN_MODE_SELf_SET(TLB_TX_PRBS_GEN_CONFIGr_reg, prbs_sel_tx); 4778 4779 PHYMOD_IF_ERR_RETURN(MODIFY_TLB_TX_PRBS_GEN_CFGr(pc, TLB_TX_PRBS_GEN_CONFIGr_reg)); 4780 4781 4782 TLB_RX_PRBS_CHK_CFGr_CLR(TLB_RX_PRBS_CHK_CONFIGr_reg); 4783 4784 TLB_RX_PRBS_CHK_CFGr_PRBS_CHK_MODEf_SET(TLB_RX_PRBS_CHK_CONFIGr_reg, prbs_check_mode); 4785 TLB_RX_PRBS_CHK_CFGr_PRBS_CHK_MODE_SELf_SET(TLB_RX_PRBS_CHK_CONFIGr_reg, prbs_sel_rx); 4786 TLB_RX_PRBS_CHK_CFGr_PRBS_CHK_INVf_SET(TLB_RX_PRBS_CHK_CONFIGr_reg, prbs_inv_rx); 4787 4788 PHYMOD_IF_ERR_RETURN(MODIFY_TLB_RX_PRBS_CHK_CFGr(pc, TLB_RX_PRBS_CHK_CONFIGr_reg)); 4789 4790 return PHYMOD_E_NONE; 4791 } /* PRBS_MODE */ 4792 #endif /* _DV_TB_ */ 4793 4794 #ifdef _DV_TB_ 4795 /*! 4796 @brief program the prbs settings 4797 @param pc handle to current TSCF context (#PHYMOD_ST) 4798 @returns The vluae PHYMOD_E_NONE upon successful completion 4799 @details 4800 Some side effects of this are. 4801 4802 <ol> 4803 <li> the first byte [3:0] (0x-f) is for TX enable 4804 <li> the first byte [7:4] (0xf-) is for TX enable mask; 4805 <li> the second byte [3:0] is for RX enable 4806 <li> the second byte [7:4] is for RX enable mask; 4807 </ol> 4808 4809 The 1st (TX), 2nd(RX) byte of #PHYMOD_ST::per_lane_control is associated 4810 with TX and RX respectively. The bits of each byte control their 4811 lanes as follows. 4812 4813 \li 0: this_lane 4814 4815 Port mode should become multiple lane. Flex port suport is TBD. 4816 4817 The bus witdh selection(testgen_bus_width) is based on prior speed mode's 4818 code block. Thus the credit parameters doesn't require re-calculation. 4819 */ 4820 int tefmod_prbs_control(PHYMOD_ST* pc, int per_lane_control) /* PRBS_CONTROL */ 4821 { 4822 int prbs_rx_en, prbs_tx_en; 4823 TLB_TX_PRBS_GEN_CFGr_t TLB_TX_PRBS_GEN_CONFIGr_reg; 4824 TLB_RX_PRBS_CHK_CFGr_t TLB_RX_PRBS_CHK_CONFIGr_reg; 4825 4826 TEFMOD_DBG_IN_FUNC_INFO(pc); 4827 prbs_rx_en = ((per_lane_control & 0xf00) >> 8) ? 1: 0; 4828 prbs_tx_en = (per_lane_control & 0xf) ? 1 : 0; 4829 4830 TLB_TX_PRBS_GEN_CFGr_CLR(TLB_TX_PRBS_GEN_CONFIGr_reg); 4831 TLB_TX_PRBS_GEN_CFGr_PRBS_GEN_ENf_SET(TLB_TX_PRBS_GEN_CONFIGr_reg,prbs_tx_en); 4832 4833 PHYMOD_IF_ERR_RETURN(MODIFY_TLB_TX_PRBS_GEN_CFGr(pc, TLB_TX_PRBS_GEN_CONFIGr_reg)); 4834 4835 TLB_RX_PRBS_CHK_CFGr_CLR(TLB_RX_PRBS_CHK_CONFIGr_reg); 4836 TLB_RX_PRBS_CHK_CFGr_PRBS_CHK_ENf_SET(TLB_RX_PRBS_CHK_CONFIGr_reg,prbs_rx_en); 4837 4838 PHYMOD_IF_ERR_RETURN(MODIFY_TLB_RX_PRBS_CHK_CFGr(pc, TLB_RX_PRBS_CHK_CONFIGr_reg)); 4839 4840 return PHYMOD_E_NONE; 4841 } /* PRBS_CONTROL */ 4842 #endif /* _DV_TB_ */ 4843 4844 /*! 4845 @brief Sets CJPAT/CRPAT parameters for a particular port 4846 @param pc handle to current TSCF context (#PHYMOD_ST) 4847 @returns The value PHYMOD_E_NONE upon successful completion 4848 @details 4849 This function enables either a CJPAT or CRPAT for a particular port. 4850 */ 4851 4852 int tefmod_cjpat_crpat_control(PHYMOD_ST* pc) /* CJPAT_CRPAT_CONTROL */ 4853 { 4854 TEFMOD_DBG_IN_FUNC_INFO(pc); 4855 /* needed only for TSCF-B0 */ 4856 return PHYMOD_E_NONE; 4857 } 4858 4859 /*! 4860 @brief Checks CJPAT/CRPAT parameters for a particular port 4861 @param pc handle to current TSCF context (#PHYMOD_ST) 4862 @returns The value PHYMOD_E_NONE upon successful completion 4863 @details 4864 This function checks for CJPAT or CRPAT for a particular port. 4865 */ 4866 4867 int tefmod_cjpat_crpat_check(PHYMOD_ST* pc) /* CJPAT_CRPAT_CHECK */ 4868 { 4869 TEFMOD_DBG_IN_FUNC_INFO(pc); 4870 /* needed only for TSCF-B0 */ 4871 return PHYMOD_E_NONE; 4872 } 4873 /*! 4874 @brief Enables or disables the bit error rate testing for a particular lane. 4875 @param pc handle to current TSCF context (#PHYMOD_ST) 4876 @returns The value PHYMOD_E_NONE upon successful completion. 4877 @details 4878 4879 This function enables or disables bit-error-rate testing (BERT) 4880 4881 TBD 4882 */ 4883 int tefmod_tx_bert_control(PHYMOD_ST* pc) /* TX_BERT_CONTROL */ 4884 { 4885 TEFMOD_DBG_IN_FUNC_INFO(pc); 4886 /* needed only for TSCF-B0 */ 4887 return PHYMOD_E_NONE; 4888 } 4889 4890 /* ! 4891 @brief Allows user to set fec_override bit for disabling FEC in 100G AN 4892 @param pc handle to current TSCF context (#PHYMOD_ST) 4893 @param enable bit to enable (1) or disable (0) fec override bit 4894 4895 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_ERROR else 4896 4897 @details 4898 CL91 is ON in 100G AN mode by default.To disable cl91 in 100G the fec 4899 override bit need to be set to 1 by user before turning on AN 4900 4901 @Note 4902 In Gen 2: This bit must be set to 0 by default and a value of 0x1 is set 4903 to override FEC in 100G noFEC AN mode. 4904 4905 In TSCF Gen1 switch: This bit is set to 0x2 by default and a value of 0x0 4906 is set to override FEC in 100G noFEC AN mode. 4907 */ 4908 4909 int tefmod_fec_override_set(PHYMOD_ST* pc, uint32_t enable) 4910 { 4911 MAIN0_SERDESIDr_t serdesid; 4912 uint32_t model; 4913 MAIN0_LN_SWPr_t MAIN0_LANE_SWAPr_reg; 4914 SC_X4_SC_X4_OVRR_GEN2r_t sc_x4_sc_x4_overr_reg; 4915 4916 /* next check serdes ID to see if gen2 or not */ 4917 READ_MAIN0_SERDESIDr(pc, &serdesid); 4918 model = MAIN0_SERDESIDr_MODEL_NUMBERf_GET(serdesid); 4919 4920 if (model == TSCF_GEN2) { 4921 SC_X4_SC_X4_OVRR_GEN2r_CLR(sc_x4_sc_x4_overr_reg); 4922 SC_X4_SC_X4_OVRR_GEN2r_AN_FEC_SEL_OVERRIDEf_SET(sc_x4_sc_x4_overr_reg, enable); 4923 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_SC_X4_OVRR_GEN2r(pc, sc_x4_sc_x4_overr_reg)); 4924 } else { /* for TSCF Gen 1 switches*/ 4925 MAIN0_LN_SWPr_CLR(MAIN0_LANE_SWAPr_reg); 4926 if (enable) { 4927 MAIN0_LN_SWPr_SPEED_100G_FEC_SELf_SET(MAIN0_LANE_SWAPr_reg, 0x0); 4928 } else { 4929 MAIN0_LN_SWPr_SPEED_100G_FEC_SELf_SET(MAIN0_LANE_SWAPr_reg, 0x2); 4930 } 4931 PHYMOD_IF_ERR_RETURN(MODIFY_MAIN0_LN_SWPr(pc, MAIN0_LANE_SWAPr_reg)); 4932 } 4933 return PHYMOD_E_NONE; 4934 } 4935 4936 4937 int tefmod_fec_override_get(PHYMOD_ST* pc, uint32_t *enable) 4938 { 4939 MAIN0_SERDESIDr_t serdesid; 4940 uint32_t model, value; 4941 MAIN0_LN_SWPr_t MAIN0_LANE_SWAPr_reg; 4942 SC_X4_SC_X4_OVRR_GEN2r_t sc_x4_sc_x4_overr_reg; 4943 4944 /* next check serdes ID to see if gen2 or not */ 4945 READ_MAIN0_SERDESIDr(pc, &serdesid); 4946 model = MAIN0_SERDESIDr_MODEL_NUMBERf_GET(serdesid); 4947 4948 if (model == TSCF_GEN2) { 4949 PHYMOD_IF_ERR_RETURN(READ_SC_X4_SC_X4_OVRR_GEN2r(pc, &sc_x4_sc_x4_overr_reg)); 4950 *enable = SC_X4_SC_X4_OVRR_GEN2r_AN_FEC_SEL_OVERRIDEf_GET(sc_x4_sc_x4_overr_reg); 4951 } else { 4952 PHYMOD_IF_ERR_RETURN(READ_MAIN0_LN_SWPr(pc, &MAIN0_LANE_SWAPr_reg)); 4953 value = MAIN0_LN_SWPr_SPEED_100G_FEC_SELf_GET(MAIN0_LANE_SWAPr_reg); 4954 if (value == 0x0) { 4955 *enable = 1; 4956 } else if (value == 0x2 ) { 4957 *enable = 0; 4958 } 4959 } 4960 return PHYMOD_E_NONE; 4961 4962 } 4963 4964 /*! 4965 @brief enables/disables FEC function. 4966 @brief Controls PMD reset pins irrespective of PCS is in Speed Control mode or not 4967 @param pc handle to current TSCF context (#PHYMOD_ST) 4968 @param fec_en Bit encoded enable for various fec feature 4969 TEFMOD_CL91_TX_EN_DIS Enable CL91 TX 4970 TEFMOD_CL91_RX_EN_DIS Enable CL91 RX 4971 TEFMOD_CL91_IND_ONLY_EN_DIS Enable CL91 indication only 4972 TEFMOD_CL91_COR_ONLY_EN_DIS Enable CL91 correction only 4973 TEFMOD_CL74_TX_EN_DIS Enable CL74 TX 4974 TEFMOD_CL74_RX_EN_DIS Enable CL74 RX 4975 4976 @param fec_dis Bit encoded disable for various fec feature 4977 TEFMOD_CL91_TX_EN_DIS Disable CL91 TX 4978 TEFMOD_CL91_RX_EN_DIS Disable CL91 RX 4979 TEFMOD_CL91_IND_ONLY_EN_DIS Disable CL91 indication only 4980 TEFMOD_CL91_COR_ONLY_EN_DIS Disable CL91 correction only 4981 TEFMOD_CL74_TX_EN_DIS Disable CL74 TX 4982 TEFMOD_CL74_RX_EN_DIS Disable CL74 RX 4983 4984 @param cl74or91 make 100G speed use cl74 after autoneg 4985 bit 1-0 cl74or91 value 4986 4987 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_ERROR else. 4988 4989 @details 4990 To use cl91 in forced speed mode (in 100G only) Tx only fec_en=TEFMOD_CL91_TX_EN_DIS 4991 To use cl91 in forced speed mode (in 100G only) Rx only fec_en=TEFMOD_CL91_RX_EN_DIS 4992 To use cl91 in forced speed mode (in 100G only) Tx Rx fec_en=(TEFMOD_CL91_TX_EN_DIS|TEFMOD_CL91_RX_EN_DIS) 4993 4994 To enable cl74 Tx only fec_en = TEFMOD_CL74_TX_EN_DIS 4995 To disable cl74 Tx Rx fec_dis =(TEFMOD_CL74_TX_EN_DIS|TEFMOD_CL74_RX_EN_DIS) 4996 4997 Note: cl74 will be enabled per port. 4998 cl91 is used only in 100G (so all 4 lanes make a port) 4999 5000 cl74or91 is only used in autoneg. And other parm used in forced speed. 5001 */ 5002 5003 5004 int tefmod_FEC_control(PHYMOD_ST* pc, tefmod_fec_type_t fec_type, int enable, int cl74or91) 5005 { 5006 phymod_access_t pa_copy; 5007 int start_lane = 0, num_lane = 0 ; 5008 uint32_t local_enable = 0; 5009 MAIN0_SERDESIDr_t serdesid; 5010 uint32_t model; 5011 5012 TX_X1_T_CL91_FECr_t TX_X1_CONTROL0_T_CL91_FECr_reg; 5013 RX_X1_CL91_CFGr_t RX_X1_CONTROL0_CL91_CONFIGr_reg; 5014 5015 TX_X4_MISCr_t TX_X4_CONTROL0_MISCr_reg; 5016 RX_X4_PCS_CTL0r_t RX_X4_CONTROL0_PCS_CONTROL_0r_reg; 5017 SC_X4_CTLr_t SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg; 5018 5019 TEFMOD_DBG_IN_FUNC_INFO(pc); 5020 PHYMOD_MEMCPY(&pa_copy, pc, sizeof(pa_copy)); 5021 PHYMOD_IF_ERR_RETURN 5022 (phymod_util_lane_config_get(pc, &start_lane, &num_lane)); 5023 pa_copy.lane_mask = 0x1 << start_lane; 5024 5025 /* next check serdes ID to see if gen2 or not */ 5026 READ_MAIN0_SERDESIDr(pc, &serdesid); 5027 model = MAIN0_SERDESIDr_MODEL_NUMBERf_GET(serdesid); 5028 5029 if(enable < TEFMOD_PHY_CONTROL_FEC_AUTO) { 5030 if (fec_type == TEFMOD_CL91) { 5031 /* TSCF GEN1 doesn't support CL91 25G/50G*/ 5032 if ((model == TSCF_GEN1) && ((num_lane == 1) || (num_lane == 2))) { 5033 return PHYMOD_E_UNAVAIL; 5034 } 5035 5036 /* check if tscf_gen2 version */ 5037 if (model == TSCF_GEN2) { 5038 uint32_t fec_mode, current_fec_mode; 5039 int speed_id; 5040 TX_X4_TX_CTL0_GEN2r_t tx_x4_tx_ctrl_reg; 5041 RX_X4_PCS_CTL_0_GEN2r_t rx_x4_pcs_crtl_reg; 5042 SC_X4_CTLr_t sc_x4_ctl_reg; 5043 5044 READ_TX_X4_TX_CTL0_GEN2r(pc, &tx_x4_tx_ctrl_reg); 5045 READ_RX_X4_PCS_CTL_0_GEN2r(pc, &rx_x4_pcs_crtl_reg); 5046 5047 current_fec_mode = TX_X4_TX_CTL0_GEN2r_CL91_FEC_MODEf_GET(tx_x4_tx_ctrl_reg); 5048 5049 if (enable) { 5050 switch (num_lane) { 5051 case 1: 5052 fec_mode = TEFMOD_CL91_SINGLE_LANE_BRCM_PROP; 5053 break; 5054 case 2: 5055 fec_mode = TEFMOD_CL91_DUAL_LANE_BRCM_PROP; 5056 break; 5057 case 4: 5058 fec_mode = TEFMOD_CL91_QUAD_LANE; 5059 break; 5060 default: 5061 fec_mode = TEFMOD_CL91_SINGLE_LANE_BRCM_PROP; 5062 break; 5063 } 5064 } else { 5065 if (current_fec_mode == TEFMOD_IEEE_25G_CL91_SINGLE_LANE) { 5066 return PHYMOD_E_INTERNAL; 5067 } else { 5068 fec_mode = TEFMOD_NO_CL91_FEC; 5069 } 5070 } 5071 5072 if (num_lane == 1) { 5073 if ((fec_mode == TEFMOD_NO_CL91_FEC) 5074 || (fec_mode == TEFMOD_CL91_SINGLE_LANE_BRCM_PROP)) { 5075 tefmod_speed_id_get(pc, &speed_id); 5076 /*If current speed id is IEEE 25G, it need to be recoverd to Broadcom 25G*/ 5077 if (speed_id == sc_x4_control_sc_S_25G_KR_IEEE) { 5078 speed_id = sc_x4_control_sc_S_25G_X1; 5079 SC_X4_CTLr_CLR(sc_x4_ctl_reg); 5080 SC_X4_CTLr_SPEEDf_SET(sc_x4_ctl_reg, speed_id); 5081 MODIFY_SC_X4_CTLr(pc, sc_x4_ctl_reg); 5082 } 5083 } 5084 } 5085 5086 TX_X4_TX_CTL0_GEN2r_CL91_FEC_MODEf_SET(tx_x4_tx_ctrl_reg, fec_mode); 5087 RX_X4_PCS_CTL_0_GEN2r_CL91_FEC_MODEf_SET(rx_x4_pcs_crtl_reg, fec_mode); 5088 MODIFY_TX_X4_TX_CTL0_GEN2r(pc, tx_x4_tx_ctrl_reg); 5089 MODIFY_RX_X4_PCS_CTL_0_GEN2r(pc, rx_x4_pcs_crtl_reg); 5090 } else { 5091 /* this is the gen1 FEC cl91 */ 5092 TX_X1_T_CL91_FECr_CLR(TX_X1_CONTROL0_T_CL91_FECr_reg); 5093 READ_TX_X1_T_CL91_FECr(pc, &TX_X1_CONTROL0_T_CL91_FECr_reg); 5094 RX_X1_CL91_CFGr_CLR(RX_X1_CONTROL0_CL91_CONFIGr_reg); 5095 READ_RX_X1_CL91_CFGr(pc, &RX_X1_CONTROL0_CL91_CONFIGr_reg); 5096 5097 if (enable) { 5098 TX_X1_T_CL91_FECr_TX_CL91_FEC_ENf_SET(TX_X1_CONTROL0_T_CL91_FECr_reg, 1); 5099 5100 RX_X1_CL91_CFGr_RX_CL91_FEC_ENf_SET(RX_X1_CONTROL0_CL91_CONFIGr_reg, 1); 5101 /* for now leave the indication and correction disabled */ 5102 /* 5103 RX_X1_CL91_CFGr_FEC_BYP_IND_ENf_SET(RX_X1_CONTROL0_CL91_CONFIGr_reg, 1); 5104 RX_X1_CL91_CFGr_FEC_BYP_CORR_ENf_SET(RX_X1_CONTROL0_CL91_CONFIGr_reg, 1); 5105 */ 5106 } else { 5107 5108 TX_X1_T_CL91_FECr_TX_CL91_FEC_ENf_SET(TX_X1_CONTROL0_T_CL91_FECr_reg, 0); 5109 5110 RX_X1_CL91_CFGr_RX_CL91_FEC_ENf_SET(RX_X1_CONTROL0_CL91_CONFIGr_reg, 0); 5111 /* for now leave the indication and correction disabled */ 5112 /* 5113 RX_X1_CL91_CFGr_FEC_BYP_IND_ENf_SET(RX_X1_CONTROL0_CL91_CONFIGr_reg, 0); 5114 RX_X1_CL91_CFGr_FEC_BYP_CORR_ENf_SET(RX_X1_CONTROL0_CL91_CONFIGr_reg, 0); 5115 */ 5116 } 5117 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X1_T_CL91_FECr(pc, TX_X1_CONTROL0_T_CL91_FECr_reg)); 5118 PHYMOD_IF_ERR_RETURN(MODIFY_RX_X1_CL91_CFGr(pc, RX_X1_CONTROL0_CL91_CONFIGr_reg)); 5119 } 5120 }else if (fec_type == TEFMOD_CL108) { 5121 /* TSCF GEN1 doesn't support CL108 25G*/ 5122 if (model == TSCF_GEN1){ 5123 return PHYMOD_E_UNAVAIL; 5124 } 5125 5126 /*CL108 is only for 25G single lane*/ 5127 if (num_lane != 1) { 5128 return PHYMOD_E_UNAVAIL; 5129 } 5130 5131 if (model == TSCF_GEN2) { 5132 uint32_t fec_mode, current_fec_mode; 5133 TX_X4_TX_CTL0_GEN2r_t tx_x4_tx_ctrl_reg; 5134 RX_X4_PCS_CTL_0_GEN2r_t rx_x4_pcs_crtl_reg; 5135 SC_X4_CTLr_t sc_x4_ctl_reg; 5136 int speed_id; 5137 int current_speed_id; 5138 5139 READ_TX_X4_TX_CTL0_GEN2r(pc, &tx_x4_tx_ctrl_reg); 5140 READ_RX_X4_PCS_CTL_0_GEN2r(pc, &rx_x4_pcs_crtl_reg); 5141 SC_X4_CTLr_CLR(sc_x4_ctl_reg); 5142 5143 current_fec_mode = TX_X4_TX_CTL0_GEN2r_CL91_FEC_MODEf_GET(tx_x4_tx_ctrl_reg); 5144 5145 if (enable) { 5146 fec_mode = TEFMOD_IEEE_25G_CL91_SINGLE_LANE; 5147 } else { 5148 if (current_fec_mode != TEFMOD_IEEE_25G_CL91_SINGLE_LANE) { 5149 return PHYMOD_E_INTERNAL; 5150 } else { 5151 fec_mode = TEFMOD_NO_CL91_FEC; 5152 } 5153 } 5154 5155 tefmod_speed_id_get(pc, ¤t_speed_id); 5156 speed_id = current_speed_id; 5157 5158 if ((current_speed_id == sc_x4_control_sc_S_25G_KR_IEEE) 5159 || (current_speed_id == sc_x4_control_sc_S_25G_X1)) { 5160 if (fec_mode == TEFMOD_NO_CL91_FEC) { 5161 speed_id = sc_x4_control_sc_S_25G_X1; 5162 } else if (fec_mode == TEFMOD_IEEE_25G_CL91_SINGLE_LANE) { 5163 speed_id = sc_x4_control_sc_S_25G_KR_IEEE; 5164 } 5165 5166 if (current_speed_id != speed_id) { 5167 SC_X4_CTLr_SPEEDf_SET(sc_x4_ctl_reg, speed_id); 5168 MODIFY_SC_X4_CTLr(pc, sc_x4_ctl_reg); 5169 } 5170 } 5171 5172 TX_X4_TX_CTL0_GEN2r_CL91_FEC_MODEf_SET(tx_x4_tx_ctrl_reg, fec_mode); 5173 RX_X4_PCS_CTL_0_GEN2r_CL91_FEC_MODEf_SET(rx_x4_pcs_crtl_reg, fec_mode); 5174 MODIFY_TX_X4_TX_CTL0_GEN2r(pc, tx_x4_tx_ctrl_reg); 5175 MODIFY_RX_X4_PCS_CTL_0_GEN2r(pc, rx_x4_pcs_crtl_reg); 5176 } 5177 } else /* cl74 */ { 5178 READ_TX_X4_MISCr(pc, &TX_X4_CONTROL0_MISCr_reg); 5179 READ_RX_X4_PCS_CTL0r(pc, &RX_X4_CONTROL0_PCS_CONTROL_0r_reg); 5180 if (enable) { 5181 TX_X4_MISCr_FEC_ENABLEf_SET(TX_X4_CONTROL0_MISCr_reg, 1); 5182 RX_X4_PCS_CTL0r_FEC_ENABLEf_SET(RX_X4_CONTROL0_PCS_CONTROL_0r_reg, 1); 5183 } else { 5184 TX_X4_MISCr_FEC_ENABLEf_SET(TX_X4_CONTROL0_MISCr_reg, 0); 5185 RX_X4_PCS_CTL0r_FEC_ENABLEf_SET(RX_X4_CONTROL0_PCS_CONTROL_0r_reg, 0); 5186 } 5187 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_MISCr(pc, TX_X4_CONTROL0_MISCr_reg)); 5188 PHYMOD_IF_ERR_RETURN(MODIFY_RX_X4_PCS_CTL0r(pc, RX_X4_CONTROL0_PCS_CONTROL_0r_reg)); 5189 } 5190 } 5191 5192 tefmod_disable_get(&pa_copy,&local_enable); 5193 if (local_enable) { 5194 SC_X4_CTLr_CLR(SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg); 5195 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg, 0); 5196 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_CTLr(&pa_copy, SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg)); 5197 5198 SC_X4_CTLr_CLR(SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg); 5199 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg, 1); 5200 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_CTLr(&pa_copy, SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg)); 5201 } 5202 5203 return PHYMOD_E_NONE; 5204 } 5205 5206 5207 int tefmod_FEC_get(PHYMOD_ST* pc, tefmod_fec_type_t fec_type, int *fec_en) 5208 { 5209 SC_X4_FEC_STSr_t SC_X4_FINAL_CONFIG_STATUS_FEC_STATUSr_reg; 5210 SC_X4_FEC_STS_GEN2r_t SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_GEN2r_reg; 5211 MAIN0_SERDESIDr_t serdesid; 5212 uint32_t model, rev_letter; 5213 5214 *fec_en = 0; 5215 /* next check serdes ID to see if gen2 or not */ 5216 READ_MAIN0_SERDESIDr(pc, &serdesid); 5217 model = MAIN0_SERDESIDr_MODEL_NUMBERf_GET(serdesid); 5218 rev_letter = MAIN0_SERDESIDr_REV_LETTERf_GET(serdesid); 5219 5220 if (fec_type == TEFMOD_CL91 || fec_type == TEFMOD_CL108) { 5221 /* if the tscf model is gen2 */ 5222 if (model == TSCF_GEN2) { 5223 uint32_t fec_mode; 5224 int speed_id; 5225 SC_X4_FEC_STS_GEN2r_CLR(SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_GEN2r_reg); 5226 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FEC_STS_GEN2r(pc, &SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_GEN2r_reg)); 5227 fec_mode = SC_X4_FEC_STS_GEN2r_T_CL91_FEC_MODEf_GET(SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_GEN2r_reg); 5228 5229 switch (fec_mode) { 5230 case TEFMOD_NO_CL91_FEC: 5231 *fec_en = 0; 5232 break; 5233 case TEFMOD_CL91_SINGLE_LANE_BRCM_PROP: 5234 /* Gen 2 28nm revision D can't distinguish CL91 and CL108 FEC, so check speed ID */ 5235 if (rev_letter == REV_D) { 5236 PHYMOD_IF_ERR_RETURN(tefmod_speed_id_get(pc, &speed_id)); 5237 if (speed_id == sc_x4_control_sc_S_25G_KR_IEEE || speed_id == sc_x4_control_sc_S_25G_CR_IEEE) { 5238 *fec_en = (fec_type == TEFMOD_CL108 ? 1 : 0); 5239 } else { 5240 *fec_en = (fec_type == TEFMOD_CL91 ? 1 : 0); 5241 } 5242 } else { 5243 *fec_en = (fec_type == TEFMOD_CL91 ? 1 : 0); 5244 } 5245 break; 5246 case TEFMOD_CL91_SINGLE_LANE_FC: 5247 case TEFMOD_CL91_DUAL_LANE_BRCM_PROP: 5248 case TEFMOD_CL91_QUAD_LANE: 5249 *fec_en = (fec_type == TEFMOD_CL91 ? 1 : 0); 5250 break; 5251 case TEFMOD_IEEE_25G_CL91_SINGLE_LANE: 5252 *fec_en = (fec_type == TEFMOD_CL108 ? 1 : 0); 5253 break; 5254 default: 5255 break; 5256 } 5257 } else { 5258 if (fec_type == TEFMOD_CL91) { 5259 /* for gen1 fec cl91 */ 5260 SC_X4_FEC_STSr_CLR(SC_X4_FINAL_CONFIG_STATUS_FEC_STATUSr_reg); 5261 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FEC_STSr(pc, &SC_X4_FINAL_CONFIG_STATUS_FEC_STATUSr_reg)); 5262 *fec_en = SC_X4_FEC_STSr_T_CL91_FEC_ENABLEf_GET(SC_X4_FINAL_CONFIG_STATUS_FEC_STATUSr_reg); 5263 } else { 5264 return PHYMOD_E_UNAVAIL; 5265 } 5266 } 5267 } else { 5268 if (model == TSCF_GEN2) { 5269 SC_X4_FEC_STS_GEN2r_CLR(SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_GEN2r_reg); 5270 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FEC_STS_GEN2r(pc, &SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_GEN2r_reg)); 5271 *fec_en = SC_X4_FEC_STS_GEN2r_T_FEC_ENABLEf_GET(SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_GEN2r_reg); 5272 } else { 5273 SC_X4_FEC_STSr_CLR(SC_X4_FINAL_CONFIG_STATUS_FEC_STATUSr_reg); 5274 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FEC_STSr(pc, &SC_X4_FINAL_CONFIG_STATUS_FEC_STATUSr_reg)); 5275 *fec_en = SC_X4_FEC_STSr_T_FEC_ENABLEf_GET(SC_X4_FINAL_CONFIG_STATUS_FEC_STATUSr_reg); 5276 } 5277 } 5278 5279 #if 0 5280 PHYMOD_IF_ERR_RETURN(READ_TX_X1_T_CL91_FECr(pc, &TX_X1_CONTROL0_T_CL91_FECr_reg)); 5281 PHYMOD_IF_ERR_RETURN(READ_RX_X1_CL91_CFGr(pc, &RX_X1_CONTROL0_CL91_CONFIGr_reg)); 5282 5283 PHYMOD_IF_ERR_RETURN(READ_TX_X4_MISCr(pc, &TX_X4_CONTROL0_MISCr_reg)); 5284 PHYMOD_IF_ERR_RETURN(READ_RX_X4_PCS_CTL0r(pc, &RX_X4_CONTROL0_PCS_CONTROL_0r_reg)); 5285 5286 /* PHYMOD_IF_ERR_RETURN(READ_MAIN0_LN_SWPr(pc, &MAIN0_LANE_SWAPr_reg)); */ 5287 5288 5289 if (fec_type == TEFMOD_CL91) { 5290 *fec_en = TX_X1_T_CL91_FECr_TX_CL91_FEC_ENf_GET(TX_X1_CONTROL0_T_CL91_FECr_reg); 5291 } else { 5292 *fec_en = TX_X4_MISCr_FEC_ENABLEf_GET(TX_X4_CONTROL0_MISCr_reg); 5293 } 5294 #endif 5295 5296 return PHYMOD_E_NONE; 5297 } 5298 5299 /*! 5300 @brief Power down transmitter or receiver per lane basis. 5301 @param pc handle to current TSCF context (a.k.a #PHYMOD_ST) 5302 @param tx control for power of TX path 5303 @param rx control for power of RX path 5304 @returns PHYMOD_E_NONE if no errors. PHYMOD_EERROR else. 5305 @details 5306 Indi 5307 */ 5308 int tefmod_power_control(PHYMOD_ST* pc, int tx, int rx) 5309 { 5310 PMD_X4_CTLr_t PMD_X4_PMD_X4_CONTROLr_reg; 5311 5312 TEFMOD_DBG_IN_FUNC_INFO(pc); 5313 PMD_X4_CTLr_CLR(PMD_X4_PMD_X4_CONTROLr_reg); 5314 5315 PMD_X4_CTLr_LN_RX_H_PWRDNf_SET(PMD_X4_PMD_X4_CONTROLr_reg, rx); 5316 PMD_X4_CTLr_LN_TX_H_PWRDNf_SET(PMD_X4_PMD_X4_CONTROLr_reg, tx); 5317 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X4_CTLr(pc, PMD_X4_PMD_X4_CONTROLr_reg)); 5318 return PHYMOD_E_NONE; 5319 } 5320 5321 /*! 5322 @brief sets the lanes in Full Duplex/ half duplex mode. 5323 @param pc handle to current TSCF context (a.k.a tefmod struct) 5324 @returns PHYMOD_E_NONE if no errors. PHYMOD_EERROR else. 5325 @details 5326 This is bit encoded function. Bit 3 to 0 is for lane 3 to 0. High sets full 5327 duplex. Low is for half duplex. 5328 5329 <B>Currently, this function is not implemented</B> 5330 */ 5331 int tefmod_duplex_control(PHYMOD_ST* pc) 5332 { 5333 TEFMOD_DBG_IN_FUNC_INFO(pc); 5334 /* needed for B0 */ 5335 return PHYMOD_E_NONE; 5336 } 5337 5338 /*! 5339 @brief Set reference clock 5340 @param pc handle to current TSCF context (a.k.a tefmod struct) 5341 @param ref_clk The reference clock to set the PHY to. 5342 @returns PHYMOD_E_NONE if no errors. PHYMOD_EERROR else. 5343 @details 5344 The reference clock is set to inform the micro. The value written into the 5345 register is interpreted by the micro as thus. 5346 5347 refclk = regVal * 2 + 100; 5348 5349 Since the refclk field is 7 bits, the range is 100 - 228 5350 5351 */ 5352 5353 int tefmod_refclk_get(PHYMOD_ST* pc, phymod_ref_clk_t* ref_clk) 5354 { 5355 MAIN0_SETUPr_t MAIN0_SETUPr_reg; 5356 5357 TEFMOD_DBG_IN_FUNC_INFO(pc); 5358 MAIN0_SETUPr_CLR(MAIN0_SETUPr_reg); 5359 READ_MAIN0_SETUPr(pc, &MAIN0_SETUPr_reg); 5360 *ref_clk = MAIN0_SETUPr_REFCLK_SELf_GET(MAIN0_SETUPr_reg); 5361 5362 return PHYMOD_E_NONE; 5363 } 5364 5365 /*! 5366 @brief disables the PCS by clearing the writing to Speed control reg 5367 @param pc handle to current TSCF context (#PHYMOD_ST) 5368 @returns The value PHYMOD_E_NONE upon successful completion. 5369 @details 5370 TBD 5371 */ 5372 5373 #ifdef _DV_TB_ 5374 int tefmod_disable_pcs_falcon(PHYMOD_ST* pc) 5375 { 5376 SC_X4_CTLr_t SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg; 5377 5378 TEFMOD_DBG_IN_FUNC_INFO(pc); 5379 SC_X4_CTLr_CLR(SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg); 5380 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg, 0); 5381 5382 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_CTLr(pc, SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg)); 5383 5384 return PHYMOD_E_NONE; 5385 } 5386 #endif /* _DV_TB_*/ 5387 5388 /*! 5389 @brief sets PMD TX lane swap values for all lanes simultaneously. 5390 @param pc handle to current TSCF context (#PHYMOD_ST) 5391 @param per_lane_control controls the lane feature 5392 @returns The value PHYMOD_E_NONE upon successful completion 5393 @details 5394 This function sets the TX lane swap values for all lanes simultaneously. 5395 5396 The TSCF has several two sets of lane swap registers per lane. This function 5397 uses the lane swap registers closest to the pads. For TX, the lane swap occurs 5398 after all other analog/digital functionality. For RX, the lane swap occurs 5399 prior to all other analog/digital functionality. 5400 5401 Swap must be the first thing to do after reset/PLL configuration. 5402 5403 How the swap is done is indicated in the per_lane_control argument. 5404 bits 0 through 15 represent the swap settings for RX while bits 16 5405 through 31 represent the swap settings for TX. 5406 5407 Each 4 bit chunk within both the RX and TX sections represent the swap settings 5408 for a particular lane as follows: 5409 5410 Bits lane assignment 5411 5412 \li 15:12 TX lane 3 5413 \li 11:8 TX lane 2 5414 \li 7:4 TX lane 1 5415 \li 3:0 TX lane 0 5416 5417 Each 4-bit value may be either 0, 1, 2 or 3, with the value indicating the lane 5418 mapping. By default, the equivalent per_lane_control settings are 0x3210_3210, 5419 indicating that there is no re-routing of traffic. As an example, to swap lanes 5420 0 and 1 for both RX and TX, the per_lane_control should be set to 0x3201_3201. 5421 To swap lanes 0 and 1, and also lanes 2 and 3 for both RX and TX, the 5422 per_lane_control should be set to 0x2301_2301. 5423 5424 This function modifies the following registers: 5425 5426 \li MAIN0_LN_SWP (0x9003) 5427 */ 5428 int tefmod_pmd_addr_lane_swap(PHYMOD_ST *pc, int per_lane_control) 5429 { 5430 unsigned int map; 5431 unsigned int lane_addr_0, lane_addr_1, lane_addr_2, lane_addr_3; 5432 DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r_t DIG_COM_TX_LANE_MAP_3_N_LANE_ADDR_0_1r_reg; 5433 DIG_LN_ADDR_2_3r_t DIG_COM_LANE_ADDR_2_3r_reg; 5434 5435 TEFMOD_DBG_IN_FUNC_INFO(pc); 5436 map = (unsigned int)per_lane_control; 5437 5438 #ifdef _DV_TB_ 5439 lane_addr_0 = (map >> 16) & 0xf; 5440 lane_addr_1 = (map >> 20) & 0xf; 5441 lane_addr_2 = (map >> 24) & 0xf; 5442 lane_addr_3 = (map >> 28) & 0xf; 5443 #else 5444 lane_addr_0 = (map >> 0) & 0xf; 5445 lane_addr_1 = (map >> 4) & 0xf; 5446 lane_addr_2 = (map >> 8) & 0xf; 5447 lane_addr_3 = (map >> 12) & 0xf; 5448 #endif 5449 5450 #ifdef _DV_TB_ 5451 pc->adjust_port_mode = 1; 5452 #endif 5453 DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r_CLR(DIG_COM_TX_LANE_MAP_3_N_LANE_ADDR_0_1r_reg); 5454 5455 DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r_LANE_ADDR_1f_SET(DIG_COM_TX_LANE_MAP_3_N_LANE_ADDR_0_1r_reg, lane_addr_1); 5456 DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r_LANE_ADDR_0f_SET(DIG_COM_TX_LANE_MAP_3_N_LANE_ADDR_0_1r_reg, lane_addr_0); 5457 PHYMOD_IF_ERR_RETURN(MODIFY_DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r(pc, DIG_COM_TX_LANE_MAP_3_N_LANE_ADDR_0_1r_reg)); 5458 5459 DIG_LN_ADDR_2_3r_CLR(DIG_COM_LANE_ADDR_2_3r_reg); 5460 5461 DIG_LN_ADDR_2_3r_LANE_ADDR_3f_SET(DIG_COM_LANE_ADDR_2_3r_reg, lane_addr_3); 5462 DIG_LN_ADDR_2_3r_LANE_ADDR_2f_SET(DIG_COM_LANE_ADDR_2_3r_reg, lane_addr_2); 5463 5464 PHYMOD_IF_ERR_RETURN(WRITE_DIG_LN_ADDR_2_3r(pc, DIG_COM_LANE_ADDR_2_3r_reg)); 5465 #ifdef _DV_TB_ 5466 pc->adjust_port_mode = 0; 5467 #endif 5468 5469 return PHYMOD_E_NONE; 5470 } 5471 5472 /*! 5473 @brief sets PMD TX lane swap values for all lanes simultaneously. 5474 @param pc handle to current TSCF context (#PHYMOD_ST) 5475 @param per_lane_control controls the lane swap 5476 @returns The value PHYMOD_E_NONE upon successful completion 5477 @details 5478 This function sets the TX lane swap values for all lanes simultaneously. 5479 5480 The TSCF has several two sets of lane swap registers per lane. This function 5481 uses the lane swap registers closest to the pads. For TX, the lane swap occurs 5482 after all other analog/digital functionality. For RX, the lane swap occurs 5483 prior to all other analog/digital functionality. 5484 5485 It is not allowed to swap lanes without going through reset. 5486 5487 How the swap is done is indicated in the per_lane_control field; 5488 bits 0 through 15 represent the swap settings for RX while bits 16 5489 through 31 represent the swap settings for TX. 5490 5491 Each 4 bit chunk within both the RX and TX sections represent the swap settings 5492 for a particular lane as follows: 5493 5494 Bits lane assignment 5495 5496 \li 15:12 TX lane 3 5497 \li 11:8 TX lane 2 5498 \li 7:4 TX lane 1 5499 \li 3:0 TX lane 0 5500 5501 Each 4-bit value may be either 0, 1, 2 or 3, with the value indicating the lane 5502 mapping. By default, the equivalent per_lane_control settings are 0x3210_3210, 5503 indicating that there is no re-routing of traffic. As an example, to swap lanes 5504 0 and 1 for both RX and TX, the per_lane_control should be set to 0x3201_3201. 5505 To swap lanes 0 and 1, and also lanes 2 and 3 for both RX and TX, the 5506 per_lane_control should be set to 0x2301_2301. 5507 5508 This function modifies the following registers: 5509 5510 \li MAIN0_LN_SWP (0x9003) 5511 */ 5512 int tefmod_pmd_lane_swap_tx(PHYMOD_ST *pc, int per_lane_control) 5513 { 5514 unsigned int map; 5515 unsigned int tx_lane_map_0, tx_lane_map_1, tx_lane_map_2, tx_lane_map_3; 5516 DIG_TX_LN_MAP_0_1_2r_t DIG_COM_TX_LANE_MAP_0_1_2r_reg; 5517 DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r_t DIG_COM_TX_LANE_MAP_3_N_LANE_ADDR_0_1r_reg; 5518 5519 TEFMOD_DBG_IN_FUNC_INFO(pc); 5520 map = (unsigned int)per_lane_control; 5521 tx_lane_map_0 = (map >> 0) & 0xf; 5522 tx_lane_map_1 = (map >> 4) & 0xf; 5523 tx_lane_map_2 = (map >> 8) & 0xf; 5524 tx_lane_map_3 = (map >> 12)& 0xf; 5525 5526 #ifdef _DV_TB_ 5527 pc->adjust_port_mode = 1; 5528 #endif 5529 DIG_TX_LN_MAP_0_1_2r_CLR(DIG_COM_TX_LANE_MAP_0_1_2r_reg); 5530 5531 DIG_TX_LN_MAP_0_1_2r_TX_LANE_MAP_2f_SET(DIG_COM_TX_LANE_MAP_0_1_2r_reg, tx_lane_map_2); 5532 DIG_TX_LN_MAP_0_1_2r_TX_LANE_MAP_1f_SET(DIG_COM_TX_LANE_MAP_0_1_2r_reg, tx_lane_map_1); 5533 DIG_TX_LN_MAP_0_1_2r_TX_LANE_MAP_0f_SET(DIG_COM_TX_LANE_MAP_0_1_2r_reg, tx_lane_map_0); 5534 PHYMOD_IF_ERR_RETURN(MODIFY_DIG_TX_LN_MAP_0_1_2r(pc, DIG_COM_TX_LANE_MAP_0_1_2r_reg)); 5535 5536 DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r_CLR(DIG_COM_TX_LANE_MAP_3_N_LANE_ADDR_0_1r_reg); 5537 DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r_TX_LANE_MAP_3f_SET(DIG_COM_TX_LANE_MAP_3_N_LANE_ADDR_0_1r_reg, tx_lane_map_3); 5538 PHYMOD_IF_ERR_RETURN(MODIFY_DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r(pc, DIG_COM_TX_LANE_MAP_3_N_LANE_ADDR_0_1r_reg)); 5539 5540 #ifdef _DV_TB_ 5541 pc->adjust_port_mode = 0; 5542 #endif 5543 5544 return PHYMOD_E_NONE; 5545 } 5546 #ifdef _DV_TB_ 5547 #endif 5548 5549 #ifdef _DV_TB_ 5550 /*! 5551 @brief removes resets from all the PMD lanes 5552 @param pc handle to current TSCF context (#PHYMOD_ST) 5553 @returns The value PHYMOD_E_NONE upon successful completion 5554 @details 5555 Removes resets 5556 */ 5557 5558 int tefmod_pmd_reset_remove(PHYMOD_ST *pc, int pmd_touched) 5559 { 5560 uint16_t data; 5561 PMD_X1_CTLr_t PMD_X1_PMD_X1_CONTROLr_reg; 5562 PMD_X4_CTLr_t PMD_X4_PMD_X4_CONTROLr_reg; 5563 5564 TEFMOD_DBG_IN_FUNC_INFO(pc); 5565 data = 0; 5566 5567 if(pmd_touched == 0) { 5568 PMD_X1_CTLr_CLR(PMD_X1_PMD_X1_CONTROLr_reg); 5569 /* setup the PMD reset */ 5570 PMD_X1_CTLr_POR_H_RSTBf_SET(PMD_X1_PMD_X1_CONTROLr_reg, 1); 5571 PMD_X1_CTLr_CORE_DP_H_RSTBf_SET(PMD_X1_PMD_X1_CONTROLr_reg, 1); 5572 5573 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X1_CTLr(pc, PMD_X1_PMD_X1_CONTROLr_reg)); 5574 } 5575 5576 data = 0; 5577 5578 PMD_X4_CTLr_CLR(PMD_X4_PMD_X4_CONTROLr_reg); 5579 PMD_X4_CTLr_LN_RX_H_PWRDNf_SET(PMD_X4_PMD_X4_CONTROLr_reg, 0); 5580 PMD_X4_CTLr_LN_TX_H_PWRDNf_SET(PMD_X4_PMD_X4_CONTROLr_reg, 0); 5581 5582 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X4_CTLr(pc, PMD_X4_PMD_X4_CONTROLr_reg)); 5583 5584 PMD_X4_CTLr_CLR(PMD_X4_PMD_X4_CONTROLr_reg); 5585 PMD_X4_CTLr_LN_H_RSTBf_SET(PMD_X4_PMD_X4_CONTROLr_reg, 1); 5586 PMD_X4_CTLr_LN_DP_H_RSTBf_SET(PMD_X4_PMD_X4_CONTROLr_reg, 1); 5587 5588 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X4_CTLr(pc, PMD_X4_PMD_X4_CONTROLr_reg)); 5589 5590 return PHYMOD_E_NONE; 5591 } 5592 #endif 5593 5594 /*! 5595 @brief sets both the RX and TX lane swap values for all lanes simultaneously. 5596 @param pc handle to current TSCF context (#PHYMOD_ST) 5597 @param per_lane_control TBD 5598 @returns The value PHYMOD_E_NONE upon successful completion 5599 @details 5600 This function sets the TX lane swap values for all lanes simultaneously. 5601 5602 The TSCF has several two sets of lane swap registers per lane. This function 5603 uses the lane swap registers closest to the pads. For TX, the lane swap occurs 5604 after all other analog/digital functionality. For RX, the lane swap occurs 5605 prior to all other analog/digital functionality. 5606 5607 It is not advisable to swap lanes without going through reset. 5608 5609 How the swap is done is indicated in the per_lane_control field; bits 0 through 5610 15 represent the swap settings for RX while bits 16 through 31 represent the 5611 swap settings for TX. 5612 5613 Each 4 bit chunk within both the RX and TX sections represent the swap settings 5614 for a particular lane as follows: 5615 5616 Bits lane assignment 5617 5618 \li 15:12 TX lane 3 5619 \li 11:8 TX lane 2 5620 \li 7:4 TX lane 1 5621 \li 3:0 TX lane 0 5622 5623 Each 4-bit value may be either 0, 1, 2 or 3, with the value indicating the lane 5624 mapping. By default, the equivalent per_lane_control settings are 0x3210_3210, 5625 indicating that there is no re-routing of traffic. As an example, to swap lanes 5626 0 and 1 for both RX and TX, the per_lane_control should be set to 0x3201_3201. 5627 To swap lanes 0 and 1, and also lanes 2 and 3 for both RX and TX, the 5628 per_lane_control should be set to 0x2301_2301. 5629 5630 This function modifies the following registers: 5631 5632 \li MAIN0_LN_SWP (0x9003) 5633 */ 5634 int tefmod_pcs_lane_swap(PHYMOD_ST *pc, int per_lane_control) 5635 { 5636 unsigned int map; 5637 MAIN0_LN_SWPr_t MAIN0_LANE_SWAPr_reg; 5638 TX_X1_TX_LN_SWP_GEN2r_t tx_lane_map_r; 5639 RX_X1_RX_LN_SWP_GEN2r_t rx_lane_map_r; 5640 MAIN0_SERDESIDr_t serdesid; 5641 uint32_t model; 5642 5643 5644 5645 TEFMOD_DBG_IN_FUNC_INFO(pc); 5646 map = (unsigned int)per_lane_control; 5647 #ifdef _DV_TB_ 5648 map = map >> 16; 5649 #endif 5650 5651 5652 READ_MAIN0_SERDESIDr(pc, &serdesid); 5653 model = MAIN0_SERDESIDr_MODEL_NUMBERf_GET(serdesid); 5654 5655 /* check if tscf_gen2 version */ 5656 if (model == TSCF_GEN2) { 5657 /* program both tx and rx lane map the same */ 5658 TX_X1_TX_LN_SWP_GEN2r_CLR(tx_lane_map_r); 5659 RX_X1_RX_LN_SWP_GEN2r_CLR(rx_lane_map_r); 5660 TX_X1_TX_LN_SWP_GEN2r_LOGICAL3_TO_PHY_SELf_SET(tx_lane_map_r, ((map >> 12) & 0x3)); 5661 TX_X1_TX_LN_SWP_GEN2r_LOGICAL2_TO_PHY_SELf_SET(tx_lane_map_r, ((map >> 8) & 0x3)); 5662 TX_X1_TX_LN_SWP_GEN2r_LOGICAL1_TO_PHY_SELf_SET(tx_lane_map_r, ((map >> 4) & 0x3)); 5663 TX_X1_TX_LN_SWP_GEN2r_LOGICAL0_TO_PHY_SELf_SET(tx_lane_map_r, ((map >> 0) & 0x3)); 5664 RX_X1_RX_LN_SWP_GEN2r_LOGICAL3_TO_PHY_SELf_SET(rx_lane_map_r, ((map >> 12) & 0x3)); 5665 RX_X1_RX_LN_SWP_GEN2r_LOGICAL2_TO_PHY_SELf_SET(rx_lane_map_r, ((map >> 8) & 0x3)); 5666 RX_X1_RX_LN_SWP_GEN2r_LOGICAL1_TO_PHY_SELf_SET(rx_lane_map_r, ((map >> 4) & 0x3)); 5667 RX_X1_RX_LN_SWP_GEN2r_LOGICAL0_TO_PHY_SELf_SET(rx_lane_map_r, ((map >> 0) & 0x3)); 5668 MODIFY_TX_X1_TX_LN_SWP_GEN2r(pc, tx_lane_map_r); 5669 MODIFY_RX_X1_RX_LN_SWP_GEN2r(pc, rx_lane_map_r); 5670 5671 } else { 5672 5673 MAIN0_LN_SWPr_CLR(MAIN0_LANE_SWAPr_reg); 5674 MAIN0_LN_SWPr_LOGICAL3_TO_PHY_SELf_SET(MAIN0_LANE_SWAPr_reg, ((map >> 12) & 0x3)); 5675 MAIN0_LN_SWPr_LOGICAL2_TO_PHY_SELf_SET(MAIN0_LANE_SWAPr_reg, ((map >> 8) & 0x3)); 5676 MAIN0_LN_SWPr_LOGICAL1_TO_PHY_SELf_SET(MAIN0_LANE_SWAPr_reg, ((map >> 4) & 0x3)); 5677 MAIN0_LN_SWPr_LOGICAL0_TO_PHY_SELf_SET(MAIN0_LANE_SWAPr_reg, ((map >> 0) & 0x3)); 5678 5679 PHYMOD_IF_ERR_RETURN(MODIFY_MAIN0_LN_SWPr(pc, MAIN0_LANE_SWAPr_reg)); 5680 } 5681 5682 return PHYMOD_E_NONE; 5683 } 5684 5685 #ifdef _DV_TB_ 5686 /*! 5687 @brief configure soft table entry 5688 @param pc handle to current TSCF context (#PHYMOD_ST) 5689 @returns The value PHYMOD_E_NONE upon successful completion 5690 @details 5691 5692 This is a tier2 function, whenever something from Hard table needs to be overwritten 5693 using soft table, this function is called. 5694 There are 4 sets of regs to override. These regs are global sc_x1_speed_override0 .. override3 5695 */ 5696 int configure_st_entry(int st_entry_num, int st_entry_speed, PHYMOD_ST* pc) 5697 { 5698 SC_X1_SPD_OVRR0_SPDr_t SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEEDr_reg; 5699 SC_X1_SPD_OVRR1_SPDr_t SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEEDr_reg; 5700 SC_X1_SPD_OVRR2_SPDr_t SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEEDr_reg; 5701 SC_X1_SPD_OVRR3_SPDr_t SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEEDr_reg; 5702 5703 SC_X1_SPD_OVRR0_0r_t SC_X1_SPEED_OVERRIDE0_OVERRIDE_0r_reg; 5704 SC_X1_SPD_OVRR1_0r_t SC_X1_SPEED_OVERRIDE1_OVERRIDE_0r_reg; 5705 SC_X1_SPD_OVRR2_0r_t SC_X1_SPEED_OVERRIDE2_OVERRIDE_0r_reg; 5706 SC_X1_SPD_OVRR3_0r_t SC_X1_SPEED_OVERRIDE3_OVERRIDE_0r_reg; 5707 5708 SC_X1_SPD_OVRR0_1r_t SC_X1_SPEED_OVERRIDE0_OVERRIDE_1r_reg; 5709 SC_X1_SPD_OVRR1_1r_t SC_X1_SPEED_OVERRIDE1_OVERRIDE_1r_reg; 5710 SC_X1_SPD_OVRR2_1r_t SC_X1_SPEED_OVERRIDE2_OVERRIDE_1r_reg; 5711 SC_X1_SPD_OVRR3_1r_t SC_X1_SPEED_OVERRIDE3_OVERRIDE_1r_reg; 5712 5713 SC_X1_SPD_OVRR0_2r_t SC_X1_SPEED_OVERRIDE0_OVERRIDE_2r_reg; 5714 SC_X1_SPD_OVRR1_2r_t SC_X1_SPEED_OVERRIDE1_OVERRIDE_2r_reg; 5715 SC_X1_SPD_OVRR2_2r_t SC_X1_SPEED_OVERRIDE2_OVERRIDE_2r_reg; 5716 SC_X1_SPD_OVRR3_2r_t SC_X1_SPEED_OVERRIDE3_OVERRIDE_2r_reg; 5717 5718 SC_X1_SPD_OVRR0_3r_t SC_X1_SPEED_OVERRIDE0_OVERRIDE_3r_reg; 5719 SC_X1_SPD_OVRR1_3r_t SC_X1_SPEED_OVERRIDE1_OVERRIDE_3r_reg; 5720 SC_X1_SPD_OVRR2_3r_t SC_X1_SPEED_OVERRIDE2_OVERRIDE_3r_reg; 5721 SC_X1_SPD_OVRR3_3r_t SC_X1_SPEED_OVERRIDE3_OVERRIDE_3r_reg; 5722 5723 SC_X1_SPD_OVRR0_4r_t SC_X1_SPEED_OVERRIDE0_OVERRIDE_4r_reg; 5724 SC_X1_SPD_OVRR1_4r_t SC_X1_SPEED_OVERRIDE1_OVERRIDE_4r_reg; 5725 SC_X1_SPD_OVRR2_4r_t SC_X1_SPEED_OVERRIDE2_OVERRIDE_4r_reg; 5726 SC_X1_SPD_OVRR3_4r_t SC_X1_SPEED_OVERRIDE3_OVERRIDE_4r_reg; 5727 5728 SC_X1_SPD_OVRR0_5r_t SC_X1_SPEED_OVERRIDE0_OVERRIDE_5r_reg; 5729 SC_X1_SPD_OVRR1_5r_t SC_X1_SPEED_OVERRIDE1_OVERRIDE_5r_reg; 5730 SC_X1_SPD_OVRR2_5r_t SC_X1_SPEED_OVERRIDE2_OVERRIDE_5r_reg; 5731 SC_X1_SPD_OVRR3_5r_t SC_X1_SPEED_OVERRIDE3_OVERRIDE_5r_reg; 5732 5733 pc->speed = st_entry_speed; 5734 /* st_entry_num can be 0, 1, 2, or 3 */ 5735 if (pc->verbosity) 5736 PHYMOD_DEBUG_ERROR(("Using speed_id: %x and st_entry_num: %x", st_entry_speed, st_entry_num)); 5737 5738 if (st_entry_num == 0) { 5739 SC_X1_SPD_OVRR0_SPDr_CLR(SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEEDr_reg); 5740 SC_X1_SPD_OVRR0_SPDr_SPEEDf_SET(SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEEDr_reg, st_entry_speed); 5741 5742 SC_X1_SPD_OVRR0_SPDr_NUM_LANESf_SET(SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEEDr_reg, (pc->num_lanes)); 5743 5744 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR0_SPDr(pc, SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEEDr_reg)); 5745 5746 5747 SC_X1_SPD_OVRR0_0r_CLR(SC_X1_SPEED_OVERRIDE0_OVERRIDE_0r_reg); 5748 SC_X1_SPD_OVRR0_0r_OS_MODEf_SET(SC_X1_SPEED_OVERRIDE0_OVERRIDE_0r_reg, (pc->os_mode)); 5749 5750 SC_X1_SPD_OVRR0_0r_SCR_MODEf_SET(SC_X1_SPEED_OVERRIDE0_OVERRIDE_0r_reg, (pc->scr_mode)); 5751 5752 SC_X1_SPD_OVRR0_0r_T_ENC_MODEf_SET(SC_X1_SPEED_OVERRIDE0_OVERRIDE_0r_reg, (pc->t_enc_mode)); 5753 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR0_0r(pc, SC_X1_SPEED_OVERRIDE0_OVERRIDE_0r_reg)); 5754 5755 SC_X1_SPD_OVRR0_1r_CLR(SC_X1_SPEED_OVERRIDE0_OVERRIDE_1r_reg); 5756 SC_X1_SPD_OVRR0_1r_DESCR_MODEf_SET(SC_X1_SPEED_OVERRIDE0_OVERRIDE_1r_reg, (pc->descr_mode)); 5757 5758 SC_X1_SPD_OVRR0_1r_DEC_TL_MODEf_SET(SC_X1_SPEED_OVERRIDE0_OVERRIDE_1r_reg, (pc->dec_tl_mode)); 5759 5760 SC_X1_SPD_OVRR0_1r_DESKEW_MODEf_SET(SC_X1_SPEED_OVERRIDE0_OVERRIDE_1r_reg, (pc->deskew_mode)); 5761 5762 SC_X1_SPD_OVRR0_1r_DEC_FSM_MODEf_SET(SC_X1_SPEED_OVERRIDE0_OVERRIDE_1r_reg, (pc->dec_fsm_mode)); 5763 5764 SC_X1_SPD_OVRR0_1r_R_HG2_ENABLEf_SET(SC_X1_SPEED_OVERRIDE0_OVERRIDE_1r_reg, (pc->r_HG2_ENABLE)); 5765 5766 SC_X1_SPD_OVRR0_1r_BS_SM_SYNC_MODEf_SET(SC_X1_SPEED_OVERRIDE0_OVERRIDE_1r_reg, (pc->bs_sm_sync_mode)); 5767 5768 SC_X1_SPD_OVRR0_1r_BS_SYNC_ENf_SET(SC_X1_SPEED_OVERRIDE0_OVERRIDE_1r_reg, (pc->bs_sync_en)); 5769 5770 SC_X1_SPD_OVRR0_1r_BS_DIST_MODEf_SET(SC_X1_SPEED_OVERRIDE0_OVERRIDE_1r_reg, (pc->bs_dist_mode)); 5771 5772 SC_X1_SPD_OVRR0_1r_BS_BTMX_MODEf_SET(SC_X1_SPEED_OVERRIDE0_OVERRIDE_1r_reg, (pc->bs_btmx_mode)); 5773 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR0_1r(pc, SC_X1_SPEED_OVERRIDE0_OVERRIDE_1r_reg)); 5774 5775 SC_X1_SPD_OVRR0_2r_CLR(SC_X1_SPEED_OVERRIDE0_OVERRIDE_2r_reg); 5776 SC_X1_SPD_OVRR0_2r_CLOCKCNT0f_SET(SC_X1_SPEED_OVERRIDE0_OVERRIDE_2r_reg, (pc->clkcnt0)); 5777 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR0_2r(pc, SC_X1_SPEED_OVERRIDE0_OVERRIDE_2r_reg)); 5778 5779 SC_X1_SPD_OVRR0_3r_CLR(SC_X1_SPEED_OVERRIDE0_OVERRIDE_3r_reg); 5780 SC_X1_SPD_OVRR0_3r_CLOCKCNT1f_SET(SC_X1_SPEED_OVERRIDE0_OVERRIDE_3r_reg, (pc->clkcnt1)); 5781 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR0_3r(pc, SC_X1_SPEED_OVERRIDE0_OVERRIDE_3r_reg)); 5782 5783 SC_X1_SPD_OVRR0_4r_CLR(SC_X1_SPEED_OVERRIDE0_OVERRIDE_4r_reg); 5784 SC_X1_SPD_OVRR0_4r_LOOPCNT0f_SET(SC_X1_SPEED_OVERRIDE0_OVERRIDE_4r_reg, (pc->lpcnt0)); 5785 5786 SC_X1_SPD_OVRR0_4r_LOOPCNT1f_SET(SC_X1_SPEED_OVERRIDE0_OVERRIDE_4r_reg, (pc->lpcnt1)); 5787 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR0_4r(pc, SC_X1_SPEED_OVERRIDE0_OVERRIDE_4r_reg)); 5788 5789 SC_X1_SPD_OVRR0_5r_CLR(SC_X1_SPEED_OVERRIDE0_OVERRIDE_5r_reg); 5790 SC_X1_SPD_OVRR0_5r_MAC_CREDITGENCNTf_SET(SC_X1_SPEED_OVERRIDE0_OVERRIDE_5r_reg, (pc->cgc)); 5791 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR0_5r(pc, SC_X1_SPEED_OVERRIDE0_OVERRIDE_5r_reg)); 5792 } 5793 if (st_entry_num == 1) { 5794 SC_X1_SPD_OVRR1_SPDr_CLR(SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEEDr_reg); 5795 SC_X1_SPD_OVRR1_SPDr_SPEEDf_SET(SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEEDr_reg, st_entry_speed); 5796 5797 SC_X1_SPD_OVRR1_SPDr_NUM_LANESf_SET(SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEEDr_reg, (pc->num_lanes)); 5798 5799 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR1_SPDr(pc, SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEEDr_reg)); 5800 5801 5802 SC_X1_SPD_OVRR1_0r_CLR(SC_X1_SPEED_OVERRIDE1_OVERRIDE_0r_reg); 5803 SC_X1_SPD_OVRR1_0r_OS_MODEf_SET(SC_X1_SPEED_OVERRIDE1_OVERRIDE_0r_reg, (pc->os_mode)); 5804 5805 SC_X1_SPD_OVRR1_0r_SCR_MODEf_SET(SC_X1_SPEED_OVERRIDE1_OVERRIDE_0r_reg, (pc->scr_mode)); 5806 5807 SC_X1_SPD_OVRR1_0r_T_ENC_MODEf_SET(SC_X1_SPEED_OVERRIDE1_OVERRIDE_0r_reg, (pc->t_enc_mode)); 5808 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR1_0r(pc, SC_X1_SPEED_OVERRIDE1_OVERRIDE_0r_reg)); 5809 5810 SC_X1_SPD_OVRR1_1r_CLR(SC_X1_SPEED_OVERRIDE1_OVERRIDE_1r_reg); 5811 SC_X1_SPD_OVRR1_1r_DESCR_MODEf_SET(SC_X1_SPEED_OVERRIDE1_OVERRIDE_1r_reg, (pc->descr_mode)); 5812 5813 SC_X1_SPD_OVRR1_1r_DEC_TL_MODEf_SET(SC_X1_SPEED_OVERRIDE1_OVERRIDE_1r_reg, (pc->dec_tl_mode)); 5814 5815 SC_X1_SPD_OVRR1_1r_DESKEW_MODEf_SET(SC_X1_SPEED_OVERRIDE1_OVERRIDE_1r_reg, (pc->deskew_mode)); 5816 5817 SC_X1_SPD_OVRR1_1r_DEC_FSM_MODEf_SET(SC_X1_SPEED_OVERRIDE1_OVERRIDE_1r_reg, (pc->dec_fsm_mode)); 5818 5819 SC_X1_SPD_OVRR1_1r_R_HG2_ENABLEf_SET(SC_X1_SPEED_OVERRIDE1_OVERRIDE_1r_reg, (pc->r_HG2_ENABLE)); 5820 5821 SC_X1_SPD_OVRR1_1r_BS_SM_SYNC_MODEf_SET(SC_X1_SPEED_OVERRIDE1_OVERRIDE_1r_reg, (pc->bs_sm_sync_mode)); 5822 5823 SC_X1_SPD_OVRR1_1r_BS_SYNC_ENf_SET(SC_X1_SPEED_OVERRIDE1_OVERRIDE_1r_reg, (pc->bs_sync_en)); 5824 5825 SC_X1_SPD_OVRR1_1r_BS_DIST_MODEf_SET(SC_X1_SPEED_OVERRIDE1_OVERRIDE_1r_reg, (pc->bs_dist_mode)); 5826 5827 SC_X1_SPD_OVRR1_1r_BS_BTMX_MODEf_SET(SC_X1_SPEED_OVERRIDE1_OVERRIDE_1r_reg, (pc->bs_btmx_mode)); 5828 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR1_1r(pc, SC_X1_SPEED_OVERRIDE1_OVERRIDE_1r_reg)); 5829 5830 SC_X1_SPD_OVRR1_2r_CLR(SC_X1_SPEED_OVERRIDE1_OVERRIDE_2r_reg); 5831 SC_X1_SPD_OVRR1_2r_CLOCKCNT0f_SET(SC_X1_SPEED_OVERRIDE1_OVERRIDE_2r_reg, (pc->clkcnt0)); 5832 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR1_2r(pc, SC_X1_SPEED_OVERRIDE1_OVERRIDE_2r_reg)); 5833 5834 SC_X1_SPD_OVRR1_3r_CLR(SC_X1_SPEED_OVERRIDE1_OVERRIDE_3r_reg); 5835 SC_X1_SPD_OVRR1_3r_CLOCKCNT1f_SET(SC_X1_SPEED_OVERRIDE1_OVERRIDE_3r_reg, (pc->clkcnt1)); 5836 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR1_3r(pc, SC_X1_SPEED_OVERRIDE1_OVERRIDE_3r_reg)); 5837 5838 SC_X1_SPD_OVRR1_4r_CLR(SC_X1_SPEED_OVERRIDE1_OVERRIDE_4r_reg); 5839 SC_X1_SPD_OVRR1_4r_LOOPCNT0f_SET(SC_X1_SPEED_OVERRIDE1_OVERRIDE_4r_reg, (pc->lpcnt0)); 5840 5841 SC_X1_SPD_OVRR1_4r_LOOPCNT1f_SET(SC_X1_SPEED_OVERRIDE1_OVERRIDE_4r_reg, (pc->lpcnt1)); 5842 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR1_4r(pc, SC_X1_SPEED_OVERRIDE1_OVERRIDE_4r_reg)); 5843 5844 SC_X1_SPD_OVRR1_5r_CLR(SC_X1_SPEED_OVERRIDE1_OVERRIDE_5r_reg); 5845 SC_X1_SPD_OVRR1_5r_MAC_CREDITGENCNTf_SET(SC_X1_SPEED_OVERRIDE1_OVERRIDE_5r_reg, (pc->cgc)); 5846 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR1_5r(pc, SC_X1_SPEED_OVERRIDE1_OVERRIDE_5r_reg)); 5847 } 5848 if (st_entry_num == 2) { 5849 SC_X1_SPD_OVRR2_SPDr_CLR(SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEEDr_reg); 5850 SC_X1_SPD_OVRR2_SPDr_SPEEDf_SET(SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEEDr_reg, st_entry_speed); 5851 5852 SC_X1_SPD_OVRR2_SPDr_NUM_LANESf_SET(SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEEDr_reg, (pc->num_lanes)); 5853 5854 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR2_SPDr(pc, SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEEDr_reg)); 5855 5856 5857 SC_X1_SPD_OVRR2_0r_CLR(SC_X1_SPEED_OVERRIDE2_OVERRIDE_0r_reg); 5858 SC_X1_SPD_OVRR2_0r_OS_MODEf_SET(SC_X1_SPEED_OVERRIDE2_OVERRIDE_0r_reg, (pc->os_mode)); 5859 5860 SC_X1_SPD_OVRR2_0r_SCR_MODEf_SET(SC_X1_SPEED_OVERRIDE2_OVERRIDE_0r_reg, (pc->scr_mode)); 5861 5862 SC_X1_SPD_OVRR2_0r_T_ENC_MODEf_SET(SC_X1_SPEED_OVERRIDE2_OVERRIDE_0r_reg, (pc->t_enc_mode)); 5863 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR2_0r(pc, SC_X1_SPEED_OVERRIDE2_OVERRIDE_0r_reg)); 5864 5865 SC_X1_SPD_OVRR2_1r_CLR(SC_X1_SPEED_OVERRIDE2_OVERRIDE_1r_reg); 5866 SC_X1_SPD_OVRR2_1r_DESCR_MODEf_SET(SC_X1_SPEED_OVERRIDE2_OVERRIDE_1r_reg, (pc->descr_mode)); 5867 5868 SC_X1_SPD_OVRR2_1r_DEC_TL_MODEf_SET(SC_X1_SPEED_OVERRIDE2_OVERRIDE_1r_reg, (pc->dec_tl_mode)); 5869 5870 SC_X1_SPD_OVRR2_1r_DESKEW_MODEf_SET(SC_X1_SPEED_OVERRIDE2_OVERRIDE_1r_reg, (pc->deskew_mode)); 5871 5872 SC_X1_SPD_OVRR2_1r_DEC_FSM_MODEf_SET(SC_X1_SPEED_OVERRIDE2_OVERRIDE_1r_reg, (pc->dec_fsm_mode)); 5873 5874 SC_X1_SPD_OVRR2_1r_R_HG2_ENABLEf_SET(SC_X1_SPEED_OVERRIDE2_OVERRIDE_1r_reg, (pc->r_HG2_ENABLE)); 5875 5876 SC_X1_SPD_OVRR2_1r_BS_SM_SYNC_MODEf_SET(SC_X1_SPEED_OVERRIDE2_OVERRIDE_1r_reg, (pc->bs_sm_sync_mode)); 5877 5878 SC_X1_SPD_OVRR2_1r_BS_SYNC_ENf_SET(SC_X1_SPEED_OVERRIDE2_OVERRIDE_1r_reg, (pc->bs_sync_en)); 5879 5880 SC_X1_SPD_OVRR2_1r_BS_DIST_MODEf_SET(SC_X1_SPEED_OVERRIDE2_OVERRIDE_1r_reg, (pc->bs_dist_mode)); 5881 5882 SC_X1_SPD_OVRR2_1r_BS_BTMX_MODEf_SET(SC_X1_SPEED_OVERRIDE2_OVERRIDE_1r_reg, (pc->bs_btmx_mode)); 5883 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR2_1r(pc, SC_X1_SPEED_OVERRIDE2_OVERRIDE_1r_reg)); 5884 5885 SC_X1_SPD_OVRR2_2r_CLR(SC_X1_SPEED_OVERRIDE2_OVERRIDE_2r_reg); 5886 SC_X1_SPD_OVRR2_2r_CLOCKCNT0f_SET(SC_X1_SPEED_OVERRIDE2_OVERRIDE_2r_reg, (pc->clkcnt0)); 5887 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR2_2r(pc, SC_X1_SPEED_OVERRIDE2_OVERRIDE_2r_reg)); 5888 5889 SC_X1_SPD_OVRR2_3r_CLR(SC_X1_SPEED_OVERRIDE2_OVERRIDE_3r_reg); 5890 SC_X1_SPD_OVRR2_3r_CLOCKCNT1f_SET(SC_X1_SPEED_OVERRIDE2_OVERRIDE_3r_reg, (pc->clkcnt1)); 5891 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR2_3r(pc, SC_X1_SPEED_OVERRIDE2_OVERRIDE_3r_reg)); 5892 5893 SC_X1_SPD_OVRR2_4r_CLR(SC_X1_SPEED_OVERRIDE2_OVERRIDE_4r_reg); 5894 SC_X1_SPD_OVRR2_4r_LOOPCNT0f_SET(SC_X1_SPEED_OVERRIDE2_OVERRIDE_4r_reg, (pc->lpcnt0)); 5895 5896 SC_X1_SPD_OVRR2_4r_LOOPCNT1f_SET(SC_X1_SPEED_OVERRIDE2_OVERRIDE_4r_reg, (pc->lpcnt1)); 5897 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR2_4r(pc, SC_X1_SPEED_OVERRIDE2_OVERRIDE_4r_reg)); 5898 5899 SC_X1_SPD_OVRR2_5r_CLR(SC_X1_SPEED_OVERRIDE2_OVERRIDE_5r_reg); 5900 SC_X1_SPD_OVRR2_5r_MAC_CREDITGENCNTf_SET(SC_X1_SPEED_OVERRIDE2_OVERRIDE_5r_reg, (pc->cgc)); 5901 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR2_5r(pc, SC_X1_SPEED_OVERRIDE2_OVERRIDE_5r_reg)); 5902 } 5903 if (st_entry_num == 3) { 5904 SC_X1_SPD_OVRR3_SPDr_CLR(SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEEDr_reg); 5905 SC_X1_SPD_OVRR3_SPDr_SPEEDf_SET(SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEEDr_reg, st_entry_speed); 5906 5907 SC_X1_SPD_OVRR3_SPDr_NUM_LANESf_SET(SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEEDr_reg, (pc->num_lanes)); 5908 5909 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR3_SPDr(pc, SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEEDr_reg)); 5910 5911 5912 SC_X1_SPD_OVRR3_0r_CLR(SC_X1_SPEED_OVERRIDE3_OVERRIDE_0r_reg); 5913 SC_X1_SPD_OVRR3_0r_OS_MODEf_SET(SC_X1_SPEED_OVERRIDE3_OVERRIDE_0r_reg, (pc->os_mode)); 5914 5915 SC_X1_SPD_OVRR3_0r_SCR_MODEf_SET(SC_X1_SPEED_OVERRIDE3_OVERRIDE_0r_reg, (pc->scr_mode)); 5916 5917 SC_X1_SPD_OVRR3_0r_T_ENC_MODEf_SET(SC_X1_SPEED_OVERRIDE3_OVERRIDE_0r_reg, (pc->t_enc_mode)); 5918 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR3_0r(pc, SC_X1_SPEED_OVERRIDE3_OVERRIDE_0r_reg)); 5919 5920 SC_X1_SPD_OVRR3_1r_CLR(SC_X1_SPEED_OVERRIDE3_OVERRIDE_1r_reg); 5921 SC_X1_SPD_OVRR3_1r_DESCR_MODEf_SET(SC_X1_SPEED_OVERRIDE3_OVERRIDE_1r_reg, (pc->descr_mode)); 5922 5923 SC_X1_SPD_OVRR3_1r_DEC_TL_MODEf_SET(SC_X1_SPEED_OVERRIDE3_OVERRIDE_1r_reg, (pc->dec_tl_mode)); 5924 5925 SC_X1_SPD_OVRR3_1r_DESKEW_MODEf_SET(SC_X1_SPEED_OVERRIDE3_OVERRIDE_1r_reg, (pc->deskew_mode)); 5926 5927 SC_X1_SPD_OVRR3_1r_DEC_FSM_MODEf_SET(SC_X1_SPEED_OVERRIDE3_OVERRIDE_1r_reg, (pc->dec_fsm_mode)); 5928 5929 SC_X1_SPD_OVRR3_1r_R_HG2_ENABLEf_SET(SC_X1_SPEED_OVERRIDE3_OVERRIDE_1r_reg, (pc->r_HG2_ENABLE)); 5930 5931 SC_X1_SPD_OVRR3_1r_BS_SM_SYNC_MODEf_SET(SC_X1_SPEED_OVERRIDE3_OVERRIDE_1r_reg, (pc->bs_sm_sync_mode)); 5932 5933 SC_X1_SPD_OVRR3_1r_BS_SYNC_ENf_SET(SC_X1_SPEED_OVERRIDE3_OVERRIDE_1r_reg, (pc->bs_sync_en)); 5934 5935 SC_X1_SPD_OVRR3_1r_BS_DIST_MODEf_SET(SC_X1_SPEED_OVERRIDE3_OVERRIDE_1r_reg, (pc->bs_dist_mode)); 5936 5937 SC_X1_SPD_OVRR3_1r_BS_BTMX_MODEf_SET(SC_X1_SPEED_OVERRIDE3_OVERRIDE_1r_reg, (pc->bs_btmx_mode)); 5938 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR3_1r(pc, SC_X1_SPEED_OVERRIDE3_OVERRIDE_1r_reg)); 5939 5940 SC_X1_SPD_OVRR3_2r_CLR(SC_X1_SPEED_OVERRIDE3_OVERRIDE_2r_reg); 5941 SC_X1_SPD_OVRR3_2r_CLOCKCNT0f_SET(SC_X1_SPEED_OVERRIDE3_OVERRIDE_2r_reg, (pc->clkcnt0)); 5942 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR3_2r(pc, SC_X1_SPEED_OVERRIDE3_OVERRIDE_2r_reg)); 5943 5944 SC_X1_SPD_OVRR3_3r_CLR(SC_X1_SPEED_OVERRIDE3_OVERRIDE_3r_reg); 5945 SC_X1_SPD_OVRR3_3r_CLOCKCNT1f_SET(SC_X1_SPEED_OVERRIDE3_OVERRIDE_3r_reg, (pc->clkcnt1)); 5946 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR3_3r(pc, SC_X1_SPEED_OVERRIDE3_OVERRIDE_3r_reg)); 5947 5948 SC_X1_SPD_OVRR3_4r_CLR(SC_X1_SPEED_OVERRIDE3_OVERRIDE_4r_reg); 5949 SC_X1_SPD_OVRR3_4r_LOOPCNT0f_SET(SC_X1_SPEED_OVERRIDE3_OVERRIDE_4r_reg, (pc->lpcnt0)); 5950 5951 SC_X1_SPD_OVRR3_4r_LOOPCNT1f_SET(SC_X1_SPEED_OVERRIDE3_OVERRIDE_4r_reg, (pc->lpcnt1)); 5952 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR3_4r(pc, SC_X1_SPEED_OVERRIDE3_OVERRIDE_4r_reg)); 5953 5954 SC_X1_SPD_OVRR3_5r_CLR(SC_X1_SPEED_OVERRIDE3_OVERRIDE_5r_reg); 5955 SC_X1_SPD_OVRR3_5r_MAC_CREDITGENCNTf_SET(SC_X1_SPEED_OVERRIDE3_OVERRIDE_5r_reg, (pc->cgc)); 5956 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X1_SPD_OVRR3_5r(pc, SC_X1_SPEED_OVERRIDE3_OVERRIDE_5r_reg)); 5957 } 5958 return PHYMOD_E_NONE; 5959 } 5960 #endif 5961 5962 #ifdef _DV_TB_ 5963 /*! 5964 @brief override soft table entry speed in AN mode 5965 @param pc handle to current TSCF context (#PHYMOD_ST) 5966 @returns The value PHYMOD_E_NONE upon successful completion. 5967 @details 5968 This is a tier2 function, it is called from init_pcs_an 5969 For instance, if a speed is resolved to 10G, but using Softtable entry 5970 if user likes to override to 20G XFI, the individual fields below are 5971 updated in pc for comparison and the configure_st_entry is called 5972 configure_st_entry func does the actual overriding 5973 returns The value PHYMOD_E_NONE upon successful completion. 5974 */ 5975 5976 int tefmod_set_an_override(PHYMOD_ST* pc) 5977 { 5978 TEFMOD_DBG_IN_FUNC_INFO(pc); 5979 pc->num_lanes = 0; 5980 pc->os_mode = 0; 5981 pc->t_fifo_mode=0; 5982 pc->t_enc_mode=1; 5983 pc->t_HG2_ENABLE=0; 5984 pc->t_pma_btmx_mode=0; 5985 pc->scr_mode=1; 5986 pc->descr_mode=1; 5987 pc->dec_tl_mode=1; 5988 pc->deskew_mode=5; 5989 pc->dec_fsm_mode=1; 5990 pc->r_HG2_ENABLE=0; 5991 pc->bs_sm_sync_mode=1; 5992 pc->bs_sync_en=1; 5993 pc->bs_dist_mode=0; 5994 pc->bs_btmx_mode=0; 5995 pc->cl72_en=1; 5996 5997 pc->clkcnt0 = 9; 5998 pc->clkcnt1 = 5; 5999 pc->lpcnt0 = 1; 6000 pc->lpcnt1 = 18; 6001 pc->cgc = 4; 6002 6003 /*override from 10G XFI to 20G XFI */ 6004 configure_st_entry(pc->this_lane, 0x1, pc); 6005 pc->speed=1; 6006 6007 return PHYMOD_E_NONE; 6008 } 6009 #endif 6010 6011 6012 #ifdef _DV_TB_ 6013 /*! 6014 @brief tefmod_init_pcs_an , program PCS for AN 6015 @returns The value PHYMOD_E_NONE upon successful completion. 6016 @details 6017 If any override option switch is selected, it will call tier2 tefmod_set_an_override 6018 This is a tier2 function, whenever something from Hard table needs to be overwritten 6019 calls the other autoneg routines to perform AN. 6020 Sets AN port mode 6021 Controls the setting/resetting of autoneg advertisement registers. 6022 tefmod_autoneg_control starts the AN 6023 */ 6024 int tefmod_init_pcs_an(PHYMOD_ST* pc) 6025 { 6026 TEFMOD_DBG_IN_FUNC_INFO(pc); 6027 if(pc->sc_mode == TEFMOD_SC_MODE_AN_CL73) { 6028 tefmod_set_an_override(pc); 6029 } 6030 tefmod_set_an_port_mode(pc); 6031 tefmod_autoneg_set(pc); 6032 tefmod_autoneg_control(pc); 6033 return PHYMOD_E_NONE; 6034 } 6035 #endif 6036 6037 #ifdef _DV_TB_ 6038 /*! 6039 @brief tefmod_set_sc_speed , sets the required speed , 6040 @returns The value PHYMOD_E_NONE upon successful completion. 6041 @details 6042 After the resets, speed_ctrl regs are programmed(as per Ankits new init seq), fills up the lookup table by 6043 Updating the expected value 6044 */ 6045 int tefmod_set_sc_speed(PHYMOD_ST* pc) /* SET_SC_SPEED */ 6046 { 6047 int mapped_speed; 6048 SC_X4_CTLr_t SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg; 6049 6050 6051 TEFMOD_DBG_IN_FUNC_INFO(pc); 6052 /* write 0 to the speed change */ 6053 SC_X4_CTLr_CLR(SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg); 6054 PHYMOD_IF_ERR_RETURN(READ_SC_X4_CTLr(pc, &SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg)); 6055 6056 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg, 0); 6057 PHYMOD_IF_ERR_RETURN(WRITE_SC_X4_CTLr(pc, SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg)); 6058 6059 /* Set speed and write 1 */ 6060 SC_X4_CTLr_CLR(SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg); 6061 6062 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg, 1); 6063 tefmod_get_mapped_speed(pc->spd_intf, &mapped_speed); 6064 if(pc->sc_mode == TEFMOD_SC_MODE_HT_OVERRIDE || pc->sc_mode == TEFMOD_SC_MODE_ST_OVERRIDE) { mapped_speed = 2; 6065 } 6066 SC_X4_CTLr_SPEEDf_SET(SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg, mapped_speed); 6067 PHYMOD_IF_ERR_RETURN(WRITE_SC_X4_CTLr(pc, SC_X4_CONTROL_SC_X4_CONTROL_CONTROLr_reg)); 6068 6069 /* Update the speed */ 6070 pc->speed= mapped_speed; 6071 6072 /* Do lookup here */ 6073 tefmod_fill_lkup_exp(pc); 6074 6075 return PHYMOD_E_NONE; 6076 } 6077 #endif 6078 6079 #ifdef _DV_TB_ 6080 /*! 6081 @brief tefmod_init_pcs_fs , program PCS for Forced speed mode 6082 @returns The value PHYMOD_E_NONE upon successful completion. 6083 @details 6084 If any SW override option switch is selected, it will call tier2 which for eg will convert from 10G to 20G XFI 6085 Using HT, we do overrides of HT entries for eg will convert from 10G to 40G MLD 6086 If none of the override options are selected, we just program the SC table 6087 */ 6088 6089 int tefmod_init_pcs_fs(PHYMOD_ST* pc) 6090 { 6091 int or_value; 6092 int st_entry; 6093 int speed_entry; 6094 SC_X4_FLD_OVRR_EN0_TYPEr_t SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg; 6095 SC_X4_FLD_OVRR_EN1_TYPEr_t SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg; 6096 SC_X4_LN_NUM_OVRRr_t SC_X4_CONTROL_LANE_NUM_OVERRIDEr_reg; 6097 TX_X2_CL82_0r_t TX_X2_CONTROL0_CL82_0r_reg; 6098 TX_X4_ENC0r_t TX_X4_CONTROL0_ENCODE_0r_reg; 6099 TX_X4_MISCr_t TX_X4_CONTROL0_MISCr_reg; 6100 RX_X4_PCS_CTL0r_t RX_X4_CONTROL0_PCS_CONTROL_0r_reg; 6101 RX_X4_BLKSYNC_CFGr_t RX_X4_CONTROL0_BLKSYNC_CONFIGr_reg; 6102 TX_X4_LOOPCNTr_t TX_X4_CREDIT0_LOOPCNTr_reg; 6103 TX_X4_CRED1r_t TX_X4_CREDIT0_CREDIT1r_reg; 6104 TX_X4_MAC_CREDGENCNTr_t TX_X4_CREDIT0_MAC_CREDITGENCNTr_reg; 6105 6106 TEFMOD_DBG_IN_FUNC_INFO(pc); 6107 if(pc->sc_mode == TEFMOD_SC_MODE_ST_OVERRIDE) { 6108 6109 /*Set the override enable*/ 6110 /*override from 10G XFI to 20G XFI */ 6111 configure_st_entry(pc->sw_table_entry, pc->speed, pc); 6112 } 6113 6114 if(pc->sc_mode == TEFMOD_SC_MODE_HT_OVERRIDE) { 6115 6116 /*override from 10G XFI to 40G MLD */ 6117 6118 SC_X4_LN_NUM_OVRRr_CLR(SC_X4_CONTROL_LANE_NUM_OVERRIDEr_reg); 6119 SC_X4_LN_NUM_OVRRr_NUM_LANES_OVERRIDE_VALUEf_SET(SC_X4_CONTROL_LANE_NUM_OVERRIDEr_reg, 4); 6120 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_LN_NUM_OVRRr(pc, SC_X4_CONTROL_LANE_NUM_OVERRIDEr_reg)); 6121 6122 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 6123 SC_X4_FLD_OVRR_EN0_TYPEr_NUM_LANES_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 1); 6124 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 6125 6126 /*write t_fifo_mode */ 6127 or_value = 1; 6128 6129 TX_X2_CL82_0r_CLR(TX_X2_CONTROL0_CL82_0r_reg); 6130 TX_X2_CL82_0r_T_FIFO_MODEf_SET(TX_X2_CONTROL0_CL82_0r_reg, or_value); 6131 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X2_CL82_0r(pc, TX_X2_CONTROL0_CL82_0r_reg)); 6132 6133 /*Set the override enable*/ 6134 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 6135 SC_X4_FLD_OVRR_EN0_TYPEr_T_FIFO_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 1); 6136 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 6137 6138 /*write t_enc_mode */ 6139 or_value = 2; 6140 TX_X4_ENC0r_CLR(TX_X4_CONTROL0_ENCODE_0r_reg); 6141 TX_X4_ENC0r_T_ENC_MODEf_SET(TX_X4_CONTROL0_ENCODE_0r_reg, or_value); 6142 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_ENC0r(pc, TX_X4_CONTROL0_ENCODE_0r_reg)); 6143 6144 /*Set the override enable*/ 6145 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 6146 SC_X4_FLD_OVRR_EN0_TYPEr_T_ENC_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 1); 6147 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 6148 6149 6150 /* scrambler mode*/ 6151 or_value = 5; 6152 TX_X4_MISCr_CLR(TX_X4_CONTROL0_MISCr_reg); 6153 TX_X4_MISCr_SCR_MODEf_SET(TX_X4_CONTROL0_MISCr_reg, or_value); 6154 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_MISCr(pc, TX_X4_CONTROL0_MISCr_reg)); 6155 6156 /*Set the override enable*/ 6157 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 6158 SC_X4_FLD_OVRR_EN0_TYPEr_SCR_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 1); 6159 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 6160 6161 /*descrambler mode*/ 6162 or_value = 2; 6163 RX_X4_PCS_CTL0r_CLR(RX_X4_CONTROL0_PCS_CONTROL_0r_reg); 6164 RX_X4_PCS_CTL0r_DESCR_MODEf_SET(RX_X4_CONTROL0_PCS_CONTROL_0r_reg, or_value); 6165 PHYMOD_IF_ERR_RETURN(MODIFY_RX_X4_PCS_CTL0r(pc, RX_X4_CONTROL0_PCS_CONTROL_0r_reg)); 6166 6167 /*Set the override enable*/ 6168 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 6169 SC_X4_FLD_OVRR_EN0_TYPEr_DESCR_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 1); 6170 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 6171 6172 /*dec_tl_mode*/ 6173 or_value = 2; 6174 RX_X4_PCS_CTL0r_CLR(RX_X4_CONTROL0_PCS_CONTROL_0r_reg); 6175 RX_X4_PCS_CTL0r_DEC_TL_MODEf_SET(RX_X4_CONTROL0_PCS_CONTROL_0r_reg, or_value); 6176 PHYMOD_IF_ERR_RETURN(MODIFY_RX_X4_PCS_CTL0r(pc, RX_X4_CONTROL0_PCS_CONTROL_0r_reg)); 6177 6178 /*Set the override enable*/ 6179 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 6180 SC_X4_FLD_OVRR_EN0_TYPEr_DEC_TL_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 1); 6181 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 6182 6183 /*desjkew_mode*/ 6184 or_value = 2; 6185 RX_X4_PCS_CTL0r_CLR(RX_X4_CONTROL0_PCS_CONTROL_0r_reg); 6186 RX_X4_PCS_CTL0r_DESKEW_MODEf_SET(RX_X4_CONTROL0_PCS_CONTROL_0r_reg, or_value); 6187 PHYMOD_IF_ERR_RETURN(MODIFY_RX_X4_PCS_CTL0r(pc, RX_X4_CONTROL0_PCS_CONTROL_0r_reg)); 6188 /*Set the override enable*/ 6189 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 6190 SC_X4_FLD_OVRR_EN0_TYPEr_DESKEW_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 1); 6191 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 6192 6193 /*dec_fsm_mode*/ 6194 /*Set the override enable*/ 6195 or_value = 2; 6196 RX_X4_PCS_CTL0r_CLR(RX_X4_CONTROL0_PCS_CONTROL_0r_reg); 6197 RX_X4_PCS_CTL0r_DEC_FSM_MODEf_SET(RX_X4_CONTROL0_PCS_CONTROL_0r_reg, or_value); 6198 PHYMOD_IF_ERR_RETURN(MODIFY_RX_X4_PCS_CTL0r(pc, RX_X4_CONTROL0_PCS_CONTROL_0r_reg)); 6199 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 6200 SC_X4_FLD_OVRR_EN0_TYPEr_DEC_FSM_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 1); 6201 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 6202 6203 /*bs_sm_sync_mode*/ 6204 /*Set the override enable*/ 6205 or_value = 0; 6206 RX_X4_BLKSYNC_CFGr_CLR(RX_X4_CONTROL0_BLKSYNC_CONFIGr_reg); 6207 RX_X4_BLKSYNC_CFGr_BS_SM_SYNC_MODEf_SET(RX_X4_CONTROL0_BLKSYNC_CONFIGr_reg, or_value); 6208 PHYMOD_IF_ERR_RETURN(MODIFY_RX_X4_BLKSYNC_CFGr(pc, RX_X4_CONTROL0_BLKSYNC_CONFIGr_reg)); 6209 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg); 6210 SC_X4_FLD_OVRR_EN1_TYPEr_BS_SM_SYNC_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg, 1); 6211 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg)); 6212 6213 /*bs_dist_mode*/ 6214 /*Set the override enable*/ 6215 or_value = 2; 6216 RX_X4_BLKSYNC_CFGr_CLR(RX_X4_CONTROL0_BLKSYNC_CONFIGr_reg); 6217 RX_X4_BLKSYNC_CFGr_BS_DIST_MODEf_SET(RX_X4_CONTROL0_BLKSYNC_CONFIGr_reg, or_value); 6218 PHYMOD_IF_ERR_RETURN(MODIFY_RX_X4_BLKSYNC_CFGr(pc, RX_X4_CONTROL0_BLKSYNC_CONFIGr_reg)); 6219 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg); 6220 SC_X4_FLD_OVRR_EN1_TYPEr_BS_DIST_MODE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg, 1); 6221 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg)); 6222 6223 /* Program resets and credits */ 6224 /*Set the override enable*/ 6225 or_value = 18; 6226 TX_X4_LOOPCNTr_CLR(TX_X4_CREDIT0_LOOPCNTr_reg); 6227 TX_X4_LOOPCNTr_LOOPCNT1f_SET(TX_X4_CREDIT0_LOOPCNTr_reg, or_value); 6228 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_LOOPCNTr(pc, TX_X4_CREDIT0_LOOPCNTr_reg)); 6229 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg); 6230 SC_X4_FLD_OVRR_EN1_TYPEr_LOOPCNT1_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg, 1); 6231 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg)); 6232 6233 or_value = 5; 6234 TX_X4_CRED1r_CLR(TX_X4_CREDIT0_CREDIT1r_reg); 6235 TX_X4_CRED1r_CLOCKCNT1f_SET(TX_X4_CREDIT0_CREDIT1r_reg, or_value); 6236 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_CRED1r(pc, TX_X4_CREDIT0_CREDIT1r_reg)); 6237 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg); 6238 SC_X4_FLD_OVRR_EN1_TYPEr_CLOCKCNT1_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg, 1); 6239 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg)); 6240 6241 or_value = 2; 6242 TX_X4_MAC_CREDGENCNTr_CLR(TX_X4_CREDIT0_MAC_CREDITGENCNTr_reg); 6243 TX_X4_MAC_CREDGENCNTr_MAC_CREDITGENCNTf_SET(TX_X4_CREDIT0_MAC_CREDITGENCNTr_reg, or_value); 6244 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_MAC_CREDGENCNTr(pc, TX_X4_CREDIT0_MAC_CREDITGENCNTr_reg)); 6245 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg); 6246 SC_X4_FLD_OVRR_EN1_TYPEr_MAC_CREDITGENCNT_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg, 1); 6247 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg)); 6248 6249 } 6250 6251 if(pc->sc_mode == TEFMOD_SC_MODE_ST) { 6252 st_entry = pc->sw_table_entry & 0xff; 6253 speed_entry = (pc->sw_table_entry & 0xff00) >> 8; 6254 configure_st_entry(st_entry, speed_entry, pc); 6255 } 6256 #ifdef _DV_TB_ 6257 pc->adjust_port_mode = 1; 6258 #endif 6259 tefmod_set_sc_speed(pc); 6260 #ifdef _DV_TB_ 6261 pc->adjust_port_mode = 0; 6262 #endif 6263 return PHYMOD_E_NONE; 6264 } 6265 #endif 6266 6267 6268 /*! 6269 @brief tefmod_init_pcs_falcon , initializes PCS to the required speed , 6270 @returns The value PHYMOD_E_NONE upon successful completion. 6271 @details 6272 if gloop and rloops are set, calls the corresponding routines 6273 Sets watermark regs, AM timer regs, Higig en/dis controls 6274 calls init_pcs FS or AN, 6275 */ 6276 #ifdef _DV_TB_ 6277 int tefmod_init_pcs_falcon(PHYMOD_ST* pc) 6278 { 6279 /* Set_port_mode is common to both Autoneg and Forced_speed mode */ 6280 uint16_t data, mask; 6281 int bypass_int_cor; 6282 PMD_X4_CTLr_t PMD_X4_PMD_X4_CONTROLr_reg; 6283 TX_X1_T_PMA_WTRMKr_t TX_X1_CONTROL0_T_PMA_WATERMARKr_reg; 6284 RX_X1_CL91_CFGr_t RX_X1_CONTROL0_CL91_CONFIGr_reg; 6285 RX_X4_DEC_CTL0r_t RX_X4_CONTROL0_DECODE_CONTROL_0r_reg; 6286 TX_X4_ENC0r_t TX_X4_CONTROL0_ENCODE_0r_reg; 6287 SC_X4_FLD_OVRR_EN0_TYPEr_t SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg; 6288 SC_X4_FLD_OVRR_EN1_TYPEr_t SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg; 6289 CL82_RX_AM_TMRr_t CL82_SHARED_CL82_RX_AM_TIMERr_reg; 6290 TX_X2_MLD_SWP_CNTr_t TX_X2_CONTROL0_MLD_SWAP_COUNTr_reg; 6291 6292 TEFMOD_DBG_IN_FUNC_INFO(pc); 6293 if(pc->pcs_gloop_en != 0) { 6294 tefmod_tx_loopback_control(pc, pc->pcs_gloop_en, pc->this_lane); 6295 } 6296 if(pc->pcs_rloop_en != 0) { 6297 tefmod_rx_loopback_control(pc, pc->pcs_rloop_en); 6298 } 6299 if(pc->pmd_rloop_en != 0) { 6300 tefmod_rx_pmd_loopback_control(pc, pc->pcs_rloop_en, pc->pmd_rloop_en, pc->this_lane); 6301 } 6302 tefmod_update_port_mode_select(pc, pc->port_type, pc->this_lane, pc->tsc_clk_freq_pll_by_48, pc->pll_reset_en); 6303 pc->per_lane_control = 3; 6304 6305 data = 0; 6306 PMD_X4_CTLr_CLR(PMD_X4_PMD_X4_CONTROLr_reg); 6307 6308 PMD_X4_CTLr_LN_RX_H_PWRDNf_SET(PMD_X4_PMD_X4_CONTROLr_reg, 0); 6309 PMD_X4_CTLr_LN_TX_H_PWRDNf_SET(PMD_X4_PMD_X4_CONTROLr_reg, 0); 6310 6311 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X4_CTLr(pc, PMD_X4_PMD_X4_CONTROLr_reg)); 6312 6313 PMD_X4_CTLr_CLR(PMD_X4_PMD_X4_CONTROLr_reg); 6314 PMD_X4_CTLr_LN_H_RSTBf_SET(PMD_X4_PMD_X4_CONTROLr_reg, 1); 6315 PMD_X4_CTLr_LN_DP_H_RSTBf_SET(PMD_X4_PMD_X4_CONTROLr_reg, 1); 6316 6317 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X4_CTLr(pc, PMD_X4_PMD_X4_CONTROLr_reg)); 6318 6319 TX_X1_T_PMA_WTRMKr_CLR(TX_X1_CONTROL0_T_PMA_WATERMARKr_reg); 6320 TX_X1_T_PMA_WTRMKr_FIVE_LANE_BITMUX_WATERMARKf_SET(TX_X1_CONTROL0_T_PMA_WATERMARKr_reg, 7); 6321 TX_X1_T_PMA_WTRMKr_TWO_LANE_BITMUX_WATERMARKf_SET(TX_X1_CONTROL0_T_PMA_WATERMARKr_reg, 5); 6322 TX_X1_T_PMA_WTRMKr_SINGLE_LANE_BITMUX_WATERMARKf_SET(TX_X1_CONTROL0_T_PMA_WATERMARKr_reg, 4); 6323 6324 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X1_T_PMA_WTRMKr(pc, TX_X1_CONTROL0_T_PMA_WATERMARKr_reg)); 6325 6326 if(pc->cl91_en != 0 && pc->an_en != 1) { 6327 bypass_int_cor = 0; 6328 if(pc->cl91_bypass_indication) { 6329 bypass_int_cor |= TEFMOD_CL91_IND_ONLY_EN_DIS; 6330 } 6331 if(pc->cl91_bypass_correction) { 6332 bypass_int_cor |= TEFMOD_CL91_COR_ONLY_EN_DIS; 6333 } 6334 tefmod_FEC_control(pc, (TEFMOD_CL91_TX_EN_DIS|TEFMOD_CL91_RX_EN_DIS|bypass_int_cor), 0, 0); 6335 } else if(pc->cl91_en == 0 && pc->an_en != 1) { 6336 tefmod_FEC_control(pc, 0, (TEFMOD_CL91_TX_EN_DIS|TEFMOD_CL91_RX_EN_DIS), 0); 6337 } 6338 6339 if(pc->cl91_nofec == 1) { 6340 tefmod_FEC_control(pc, TEFMOD_CL74_CL91_EN_DIS, 0, 0); 6341 } 6342 if(pc->cl91_cl74 == 1) { 6343 tefmod_FEC_control(pc, TEFMOD_CL74_CL91_EN_DIS, 0, 1); 6344 } 6345 6346 tefmod_tx_lane_control_set(pc, TEFMOD_TX_LANE_RESET_TRAFFIC_ENABLE); 6347 tefmod_rx_lane_control(pc, pc->accData, pc->per_lane_control); 6348 6349 data = 0; 6350 mask = 0; 6351 6352 if(pc->rx_am_timer_init_val == 0x3ff) { 6353 RX_X1_CL91_CFGr_CLR(RX_X1_CONTROL0_CL91_CONFIGr_reg); 6354 RX_X1_CL91_CFGr_CL91_AM_SPACING_1024f_SET(RX_X1_CONTROL0_CL91_CONFIGr_reg, 1); 6355 PHYMOD_IF_ERR_RETURN(MODIFY_RX_X1_CL91_CFGr(pc, RX_X1_CONTROL0_CL91_CONFIGr_reg)); 6356 } 6357 6358 data = 0xffc; 6359 mask = 0xfff; 6360 6361 /* cfg_rx_am_timer_init_val=3ff cfg_tx_am_timer_init_val=ffc */ 6362 CL82_RX_AM_TMRr_CLR(CL82_SHARED_CL82_RX_AM_TIMERr_reg); 6363 TX_X2_MLD_SWP_CNTr_CLR(TX_X2_CONTROL0_MLD_SWAP_COUNTr_reg); 6364 6365 if(pc->rx_am_timer_init_val != 0x3fff) { 6366 CL82_RX_AM_TMRr_SET(CL82_SHARED_CL82_RX_AM_TIMERr_reg, pc->rx_am_timer_init_val); 6367 PHYMOD_IF_ERR_RETURN(WRITE_CL82_RX_AM_TMRr(pc, CL82_SHARED_CL82_RX_AM_TIMERr_reg)); 6368 } 6369 if(pc->tx_am_timer_init_val != 0xffff) { 6370 TX_X2_MLD_SWP_CNTr_SET(TX_X2_CONTROL0_MLD_SWAP_COUNTr_reg, pc->tx_am_timer_init_val); 6371 PHYMOD_IF_ERR_RETURN(WRITE_TX_X2_MLD_SWP_CNTr(pc, TX_X2_CONTROL0_MLD_SWAP_COUNTr_reg)); 6372 } 6373 6374 /* +cfg_rx_higig2_oen +cfg_tx_higig2_oen */ 6375 if(pc->tx_higig2_oen == 0x1) { 6376 /* Set t_HG2_ENABLE_oen bit 10 in 0xc060 */ 6377 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg); 6378 SC_X4_FLD_OVRR_EN0_TYPEr_T_HG2_ENABLE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg, 1); 6379 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPEr_reg)); 6380 6381 /* Clr/Set HG2_ENABLE bit 10 in 0xc111 */ 6382 TX_X4_ENC0r_CLR(TX_X4_CONTROL0_ENCODE_0r_reg); 6383 TX_X4_ENC0r_HG2_ENABLEf_SET(TX_X4_CONTROL0_ENCODE_0r_reg, pc->tx_higig2_en); 6384 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_ENC0r(pc,TX_X4_CONTROL0_ENCODE_0r_reg)); 6385 } 6386 6387 /* +cfg_tefmod_use_higig2_knobs +cfg_tx_higig2_codec */ 6388 if(pc->tefmod_use_higig2_knobs == 0x1) { 6389 TX_X4_ENC0r_CLR(TX_X4_CONTROL0_ENCODE_0r_reg); 6390 TX_X4_ENC0r_HG2_CODECf_SET(TX_X4_CONTROL0_ENCODE_0r_reg, pc->tx_higig2_codec); 6391 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_ENC0r(pc,TX_X4_CONTROL0_ENCODE_0r_reg)); 6392 } 6393 if(pc->rx_higig2_oen == 0x1) { 6394 /* Set r_HG2_ENABLE_oen bit 15 in 0xc061 */ 6395 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg); 6396 SC_X4_FLD_OVRR_EN1_TYPEr_R_HG2_ENABLE_OENf_SET(SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg, 1); 6397 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPEr_reg)); 6398 6399 /* Clr/Set HG2_ENABLE bit 12 in 0xc134 */ 6400 RX_X4_DEC_CTL0r_CLR(RX_X4_CONTROL0_DECODE_CONTROL_0r_reg); 6401 RX_X4_DEC_CTL0r_HG2_ENABLEf_SET(RX_X4_CONTROL0_DECODE_CONTROL_0r_reg, pc->rx_higig2_en); 6402 PHYMOD_IF_ERR_RETURN(MODIFY_RX_X4_DEC_CTL0r(pc, RX_X4_CONTROL0_DECODE_CONTROL_0r_reg)); 6403 } 6404 /* +cfg_tefmod_use_higig2_knobs +cfg_rx_higig2_codec */ 6405 if(pc->tefmod_use_higig2_knobs == 0x1) { 6406 RX_X4_DEC_CTL0r_CLR(RX_X4_CONTROL0_DECODE_CONTROL_0r_reg); 6407 RX_X4_DEC_CTL0r_HG2_CODECf_SET(RX_X4_CONTROL0_DECODE_CONTROL_0r_reg, pc->rx_higig2_codec); 6408 PHYMOD_IF_ERR_RETURN(MODIFY_RX_X4_DEC_CTL0r(pc, RX_X4_CONTROL0_DECODE_CONTROL_0r_reg)); 6409 } 6410 /*if FEC enabled */ 6411 if(pc->t_fec_enable) { 6412 tefmod_FEC_control(pc, (TEFMOD_CL74_TX_EN_DIS|TEFMOD_CL74_RX_EN_DIS), 0, 0); 6413 } 6414 /* call FS or AN mode */ 6415 if(pc->an_en) { 6416 tefmod_init_pcs_an(pc); 6417 } else { 6418 tefmod_init_pcs_fs(pc); 6419 } 6420 if(pc->pmd_gloop_en != 0) { 6421 tefmod_tx_pmd_loopback_control(pc, pc->pmd_gloop_en); 6422 } 6423 6424 if ((pc->pmd_reset_control) != 0) { 6425 tefmod_pmd_reset_bypass(pc, pc->pmd_reset_control); 6426 } 6427 if(pc->cl72_training_restart || pc->cl72_training_enabled) { 6428 pc->per_lane_control = pc->cl72_training_restart | (pc->cl72_training_enabled<<1); 6429 tefmod_clause72_control(pc, pc->per_lane_control); 6430 } 6431 return PHYMOD_E_NONE; 6432 } 6433 #endif 6434 6435 /*! 6436 @brief tefmod_init_pmd_falcon , initializes PMD the required speed , 6437 @returns The value PHYMOD_E_NONE upon successful completion. 6438 @details 6439 Sets up PMD resets, 6440 Speeds up DSC and VGA funnctions for simulation purpose only 6441 */ 6442 6443 #ifdef _DV_TB_ 6444 int tefmod_init_pmd_falcon(PHYMOD_ST* pc) 6445 { 6446 uint16_t os_mode; 6447 CKRST_LN_CLK_RST_N_PWRDWN_CTLr_t CKRST_CTRL_PMD_LANE_CLK_RESET_N_POWERDOWN_CONTROLr_reg; 6448 CKRST_OSR_MODE_CTLr_t CKRST_CTRL_PMD_OSR_MODE_CONTROLr_reg; 6449 6450 TEFMOD_DBG_IN_FUNC_INFO(pc); 6451 /* setup the PMD reset */ 6452 CKRST_LN_CLK_RST_N_PWRDWN_CTLr_CLR(CKRST_CTRL_PMD_LANE_CLK_RESET_N_POWERDOWN_CONTROLr_reg); 6453 CKRST_LN_CLK_RST_N_PWRDWN_CTLr_LN_DP_S_RSTBf_SET(CKRST_CTRL_PMD_LANE_CLK_RESET_N_POWERDOWN_CONTROLr_reg, 1); 6454 6455 PHYMOD_IF_ERR_RETURN(MODIFY_CKRST_LN_CLK_RST_N_PWRDWN_CTLr(pc, CKRST_CTRL_PMD_LANE_CLK_RESET_N_POWERDOWN_CONTROLr_reg)); 6456 6457 CKRST_LN_CLK_RST_N_PWRDWN_CTLr_CLR(CKRST_CTRL_PMD_LANE_CLK_RESET_N_POWERDOWN_CONTROLr_reg); 6458 CKRST_LN_CLK_RST_N_PWRDWN_CTLr_LN_DP_S_RSTBf_SET(CKRST_CTRL_PMD_LANE_CLK_RESET_N_POWERDOWN_CONTROLr_reg, 1); 6459 PHYMOD_IF_ERR_RETURN(MODIFY_CKRST_LN_CLK_RST_N_PWRDWN_CTLr(pc, CKRST_CTRL_PMD_LANE_CLK_RESET_N_POWERDOWN_CONTROLr_reg)); 6460 6461 tefmod_afe_speed_up_dsc_vga(pc); 6462 6463 if(pc->uc_active == 0){ 6464 os_mode = 0; 6465 if((pc->spd_intf == TEFMOD_SPD_10000_XFI) || 6466 (pc->spd_intf == TEFMOD_SPD_10600_XFI_HG) || 6467 (pc->spd_intf == TEFMOD_SPD_20G_MLD_X2) || 6468 (pc->spd_intf == TEFMOD_SPD_21G_MLD_HG_X2)|| 6469 (pc->spd_intf == TEFMOD_SPD_50G_MLD_X4) || 6470 (pc->spd_intf == TEFMOD_SPD_53G_MLD_HG_X4)|| 6471 (pc->spd_intf == TEFMOD_SPD_40G_MLD_X4) || 6472 (pc->spd_intf == TEFMOD_SPD_42G_MLD_HG_X4)) { 6473 os_mode = 1; 6474 } else if(pc->spd_intf == TEFMOD_SPD_1G_20G) { 6475 os_mode = 8; 6476 } else if(pc->spd_intf == TEFMOD_SPD_1G_25G) { 6477 os_mode = 12; 6478 } else { 6479 os_mode = 0; 6480 } 6481 6482 CKRST_OSR_MODE_CTLr_CLR(CKRST_CTRL_PMD_OSR_MODE_CONTROLr_reg); 6483 CKRST_OSR_MODE_CTLr_OSR_MODE_FRC_VALf_SET(CKRST_CTRL_PMD_OSR_MODE_CONTROLr_reg, os_mode); 6484 6485 PHYMOD_IF_ERR_RETURN(MODIFY_CKRST_OSR_MODE_CTLr(pc, CKRST_CTRL_PMD_OSR_MODE_CONTROLr_reg)); 6486 6487 } 6488 /* might be used later */ 6489 return PHYMOD_E_NONE; 6490 } 6491 #endif 6492 6493 /*! 6494 @brief tefmod_poll_for_sc_done , polls for the sc_done bit , 6495 @returns The value PHYMOD_E_NONE upon successful completion. 6496 @details 6497 Reads the SC_X4_COntrol_status reg and polls it to see if sc_done bit is set 6498 Sets the sc_done flag=1/0, if speed control is done, after resolving to the correct speed 6499 */ 6500 int tefmod_poll_for_sc_done(PHYMOD_ST* pc, int mapped_speed) 6501 { 6502 int done; 6503 int spd_match, sc_done; 6504 int cnt; 6505 uint16_t data; 6506 SC_X4_STSr_t SC_X4_CONTROL_SC_X4_CONTROL_STATUSr_reg; 6507 SC_X4_RSLVD_SPDr_t SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEEDr_reg; 6508 6509 TEFMOD_DBG_IN_FUNC_INFO(pc); 6510 cnt=0; 6511 sc_done = 0; 6512 spd_match = 0; 6513 6514 SC_X4_STSr_CLR(SC_X4_CONTROL_SC_X4_CONTROL_STATUSr_reg); 6515 while (cnt <=2000) { 6516 PHYMOD_IF_ERR_RETURN(READ_SC_X4_STSr(pc, &SC_X4_CONTROL_SC_X4_CONTROL_STATUSr_reg)); 6517 cnt = cnt + 1; 6518 if(SC_X4_STSr_SW_SPEED_CHANGE_DONEf_GET(SC_X4_CONTROL_SC_X4_CONTROL_STATUSr_reg)) { 6519 sc_done = 1; 6520 break; 6521 } else { 6522 if(cnt == 2000) { 6523 sc_done = 0; 6524 break; 6525 } 6526 } 6527 } 6528 6529 cnt=0; 6530 while (cnt <=400) { 6531 SC_X4_RSLVD_SPDr_CLR(SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEEDr_reg); 6532 PHYMOD_IF_ERR_RETURN(READ_SC_X4_RSLVD_SPDr(pc, &SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEEDr_reg)); 6533 data = SC_X4_RSLVD_SPDr_SPEEDf_GET(SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEEDr_reg); 6534 #ifdef _DV_TB_ 6535 if(pc->verbosity) 6536 PHYMOD_DEBUG_ERROR(("Resolved speed is %x :: need %x :: uint :: %d :: lane :: %d\n", data, mapped_speed, pc->unit, pc->this_lane)); 6537 #endif 6538 cnt = cnt + 1; 6539 if(data == mapped_speed) { 6540 spd_match = 1; 6541 break; 6542 } else { 6543 if(cnt == 400) { 6544 spd_match = 0; 6545 break; 6546 } 6547 } 6548 } 6549 if(sc_done && spd_match) { 6550 done = 1; 6551 } else { 6552 done = 0; 6553 } 6554 return done; 6555 } 6556 6557 /*! 6558 @brief tefmod_check_status , checks the statistics port_mode, 6559 @returns The value PHYMOD_E_NONE upon successful completion. 6560 @details 6561 Populates the HT entries, based on the speed 6562 In this routine, the following regs are read:RESOLVED_0r_STATUS to RESOLVED_5r_STATUS 6563 The read value from these are what is the actual (RTL sends this)and whatever was stored in lookup is what DV expects 6564 Sets the sc_done flag=1, if there are no mismatches 6565 */ 6566 6567 #ifdef _DV_TB_ 6568 int tefmod_check_status(PHYMOD_ST* pc) 6569 { 6570 uint16_t fail; 6571 int actual_speed; 6572 int spd_change_done; 6573 PHYMOD_ST sc_stats_actual; 6574 PHYMOD_ST* sc_stats_print_actual; 6575 SC_X4_RSLVD_SPDr_t SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEEDr_reg; 6576 SC_X4_RSLVD0r_t SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0r_reg; 6577 SC_X4_RSLVD1r_t SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1r_reg; 6578 SC_X4_RSLVD2r_t SC_X4_FINAL_CONFIG_STATUS_RESOLVED_2r_reg; 6579 SC_X4_RSLVD3r_t SC_X4_FINAL_CONFIG_STATUS_RESOLVED_3r_reg; 6580 SC_X4_RSLVD4r_t SC_X4_FINAL_CONFIG_STATUS_RESOLVED_4r_reg; 6581 SC_X4_RSLVD5r_t SC_X4_FINAL_CONFIG_STATUS_RESOLVED_5r_reg; 6582 SC_X4_FEC_STSr_t SC_X4_FINAL_CONFIG_STATUS_FEC_STATUSr_reg; 6583 6584 TEFMOD_DBG_IN_FUNC_INFO(pc); 6585 spd_change_done = 0; 6586 if(!pc->an_en) { 6587 spd_change_done = tefmod_poll_for_sc_done(pc, pc->speed); 6588 } 6589 6590 tefmod_get_ht_entries(pc); 6591 6592 if(pc->sc_mode == TEFMOD_SC_MODE_ST_OVERRIDE) { 6593 pc->os_mode=0; 6594 pc->clkcnt1 = 0x5; 6595 pc->lpcnt0 = 0x1; 6596 pc->lpcnt1 = 0x12; 6597 pc->cgc = 0x4; 6598 pc->cl72_en = 0; 6599 } 6600 6601 if(pc->sc_mode == TEFMOD_SC_MODE_AN_CL73) { 6602 pc->speed = 0; 6603 pc->cl72_en = 0; 6604 } 6605 6606 if(pc->an_fec || pc->t_fec_enable) { 6607 pc->bs_sync_en = 0; 6608 } 6609 if(pc->cl91_en != 0) { 6610 pc->t_pma_btmx_mode = 0; 6611 } 6612 if(pc->cl91_nofec != 0 || pc->cl91_cl74) { 6613 pc->t_pma_btmx_mode = 2; 6614 pc->deskew_mode = 4; 6615 pc->bs_sync_en = 1; 6616 pc->bs_dist_mode = 3; 6617 pc->bs_btmx_mode = 2; 6618 } 6619 if(pc->cl91_cl74 != 0) { 6620 pc->bs_sync_en = 0; 6621 } 6622 /* Read resolved speed */ 6623 6624 SC_X4_RSLVD_SPDr_CLR(SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEEDr_reg); 6625 PHYMOD_IF_ERR_RETURN(READ_SC_X4_RSLVD_SPDr(pc, &SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEEDr_reg)); 6626 6627 sc_stats_actual.num_lanes = SC_X4_RSLVD_SPDr_NUM_LANESf_GET(SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEEDr_reg); 6628 6629 actual_speed = SC_X4_RSLVD_SPDr_SPEEDf_GET(SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEEDr_reg); 6630 6631 6632 /* RESOLVED 0 */ 6633 /* cl72_en, scr_mode, os_mode, enc_mode, fifo_mode, HG2_en, t_pma_btmx_mode */ 6634 6635 PHYMOD_IF_ERR_RETURN(READ_SC_X4_RSLVD0r(pc, &SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0r_reg)); 6636 6637 sc_stats_actual.cl72_en = SC_X4_RSLVD0r_CL72_ENf_GET(SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0r_reg); 6638 sc_stats_actual.os_mode = SC_X4_RSLVD0r_OS_MODEf_GET(SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0r_reg); 6639 sc_stats_actual.t_fifo_mode = SC_X4_RSLVD0r_T_FIFO_MODEf_GET(SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0r_reg); 6640 sc_stats_actual.t_enc_mode = SC_X4_RSLVD0r_T_ENC_MODEf_GET(SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0r_reg); 6641 sc_stats_actual.t_HG2_ENABLE = SC_X4_RSLVD0r_T_HG2_ENABLEf_GET(SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0r_reg); 6642 sc_stats_actual.t_pma_btmx_mode = SC_X4_RSLVD0r_T_PMA_BTMX_MODEf_GET(SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0r_reg); 6643 sc_stats_actual.scr_mode = SC_X4_RSLVD0r_SCR_MODEf_GET(SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0r_reg); 6644 6645 /* RESOLVED 1 */ 6646 PHYMOD_IF_ERR_RETURN(READ_SC_X4_RSLVD1r(pc, &SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1r_reg)); 6647 sc_stats_actual.descr_mode = SC_X4_RSLVD1r_DESCR_MODEf_GET(SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1r_reg); 6648 sc_stats_actual.dec_tl_mode = SC_X4_RSLVD1r_DEC_TL_MODEf_GET(SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1r_reg); 6649 sc_stats_actual.deskew_mode = SC_X4_RSLVD1r_DESKEW_MODEf_GET(SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1r_reg); 6650 sc_stats_actual.dec_fsm_mode = SC_X4_RSLVD1r_DEC_FSM_MODEf_GET(SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1r_reg); 6651 sc_stats_actual.r_HG2_ENABLE = SC_X4_RSLVD1r_R_HG2_ENABLEf_GET(SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1r_reg); 6652 sc_stats_actual.bs_sm_sync_mode = SC_X4_RSLVD1r_BS_SM_SYNC_MODEf_GET(SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1r_reg); 6653 sc_stats_actual.bs_sync_en = SC_X4_RSLVD1r_BS_SYNC_ENf_GET(SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1r_reg); 6654 sc_stats_actual.bs_dist_mode = SC_X4_RSLVD1r_BS_DIST_MODEf_GET(SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1r_reg); 6655 sc_stats_actual.bs_btmx_mode = SC_X4_RSLVD1r_BS_BTMX_MODEf_GET(SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1r_reg); 6656 6657 6658 /*RESOLVED 2 */ 6659 PHYMOD_IF_ERR_RETURN(READ_SC_X4_RSLVD2r(pc, &SC_X4_FINAL_CONFIG_STATUS_RESOLVED_2r_reg)); 6660 sc_stats_actual.clkcnt0 = SC_X4_RSLVD2r_CLOCKCNT0f_GET(SC_X4_FINAL_CONFIG_STATUS_RESOLVED_2r_reg); 6661 /*RESOLVED 3 */ 6662 PHYMOD_IF_ERR_RETURN(READ_SC_X4_RSLVD3r(pc, &SC_X4_FINAL_CONFIG_STATUS_RESOLVED_3r_reg)); 6663 sc_stats_actual.clkcnt1 = SC_X4_RSLVD3r_CLOCKCNT1f_GET(SC_X4_FINAL_CONFIG_STATUS_RESOLVED_3r_reg); 6664 /*RESOLVED 4 */ 6665 PHYMOD_IF_ERR_RETURN(READ_SC_X4_RSLVD4r(pc, &SC_X4_FINAL_CONFIG_STATUS_RESOLVED_4r_reg)); 6666 sc_stats_actual.lpcnt0 = SC_X4_RSLVD4r_LOOPCNT0f_GET(SC_X4_FINAL_CONFIG_STATUS_RESOLVED_4r_reg); 6667 sc_stats_actual.lpcnt1 = SC_X4_RSLVD4r_LOOPCNT1f_GET(SC_X4_FINAL_CONFIG_STATUS_RESOLVED_4r_reg); 6668 /*RESOLVED 5 */ 6669 PHYMOD_IF_ERR_RETURN(READ_SC_X4_RSLVD5r(pc, &SC_X4_FINAL_CONFIG_STATUS_RESOLVED_5r_reg)); 6670 sc_stats_actual.cgc = SC_X4_RSLVD5r_MAC_CREDITGENCNTf_GET(SC_X4_FINAL_CONFIG_STATUS_RESOLVED_5r_reg); 6671 6672 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FEC_STSr(pc, &SC_X4_FINAL_CONFIG_STATUS_FEC_STATUSr_reg)); 6673 if(pc->an_fec || pc->t_fec_enable) { 6674 /* if(data != 3) {} */ 6675 if((SC_X4_FEC_STSr_T_FEC_ENABLEf_GET(SC_X4_FINAL_CONFIG_STATUS_FEC_STATUSr_reg) & 6676 SC_X4_FEC_STSr_R_FEC_ENABLEf_GET(SC_X4_FINAL_CONFIG_STATUS_FEC_STATUSr_reg)) != 1) { 6677 fail=1; 6678 } 6679 } 6680 6681 if(pc->cl91_en) { 6682 /* if(data != 0xc) {} */ 6683 if((SC_X4_FEC_STSr_T_CL91_FEC_ENABLEf_GET(SC_X4_FINAL_CONFIG_STATUS_FEC_STATUSr_reg) & 6684 SC_X4_FEC_STSr_R_CL91_FEC_ENABLEf_GET(SC_X4_FINAL_CONFIG_STATUS_FEC_STATUSr_reg)) != 1) { 6685 fail=1; 6686 } 6687 } 6688 6689 6690 /* NICK +cfg_rx_higig2_oen +cfg_tx_higig2_oen */ 6691 6692 if(pc->tx_higig2_oen == 0x1) { pc->t_HG2_ENABLE = pc->tx_higig2_en; } 6693 if(pc->rx_higig2_oen == 0x1) { pc->r_HG2_ENABLE = pc->rx_higig2_en; } 6694 6695 /* Compare actual vs expected stats */ 6696 fail = 0; 6697 6698 if(actual_speed != pc->speed) { 6699 if(pc->verbosity) 6700 #ifdef _DV_TB_ 6701 PHYMOD_DEBUG_ERROR(("Act speed is %d and exp_speed is %d\n", actual_speed, pc->speed)); 6702 #endif 6703 fail=1; 6704 } else { 6705 #ifdef _DV_TB_ 6706 if(pc->verbosity) 6707 PHYMOD_DEBUG_ERROR(("speed %d executed correctly \n", actual_speed)); 6708 #endif 6709 } 6710 6711 /*Resolved 0 comparison */ 6712 if(sc_stats_actual.cl72_en != pc->cl72_en) fail=1; 6713 if(sc_stats_actual.os_mode != pc->os_mode) fail=1; 6714 if(sc_stats_actual.t_fifo_mode != pc->t_fifo_mode) fail=1; 6715 if(sc_stats_actual.t_enc_mode != pc->t_enc_mode) fail=1; 6716 if(sc_stats_actual.t_HG2_ENABLE != pc->t_HG2_ENABLE) fail=1; 6717 if(sc_stats_actual.t_pma_btmx_mode != pc->t_pma_btmx_mode) fail=1; 6718 if(sc_stats_actual.scr_mode != pc->scr_mode) fail=1; 6719 6720 /*Resolved 1 comparison */ 6721 if(sc_stats_actual.descr_mode != pc->descr_mode) fail=1; 6722 if(sc_stats_actual.dec_tl_mode != pc->dec_tl_mode) fail=1; 6723 if(sc_stats_actual.deskew_mode != pc->deskew_mode) fail=1; 6724 if(sc_stats_actual.dec_fsm_mode != pc->dec_fsm_mode) fail=1; 6725 if(sc_stats_actual.r_HG2_ENABLE != pc->r_HG2_ENABLE) fail=1; 6726 if(sc_stats_actual.bs_sm_sync_mode != pc->bs_sm_sync_mode) fail=1; 6727 if(sc_stats_actual.bs_sync_en != pc->bs_sync_en) fail=1; 6728 if(sc_stats_actual.bs_dist_mode != pc->bs_dist_mode) fail=1; 6729 if(sc_stats_actual.bs_btmx_mode != pc->bs_btmx_mode) fail=1; 6730 6731 6732 /*Resolved 2 comparison */ 6733 if(sc_stats_actual.clkcnt0 != pc->clkcnt0) fail=1; 6734 6735 /*Resolved 3 comparison */ 6736 if(sc_stats_actual.clkcnt1 != pc->clkcnt1) fail=1; 6737 6738 /*Resolved 4 comparison */ 6739 if(sc_stats_actual.lpcnt0 != pc->lpcnt0) fail=1; 6740 if(sc_stats_actual.lpcnt1 != pc->lpcnt1) fail=1; 6741 6742 /*Resolved 5 comparison */ 6743 if(sc_stats_actual.cgc != pc->cgc) fail=1; 6744 6745 /* pc-> = fail; */ 6746 if(fail == 1) { 6747 #ifdef _DV_TB_ 6748 PHYMOD_DEBUG_ERROR(("Actual stats\n")); 6749 sc_stats_print_actual = &sc_stats_actual; 6750 print_tefmod_sc_lkup_table(sc_stats_print_actual); 6751 PHYMOD_DEBUG_ERROR(("Expected stats\n")); 6752 print_tefmod_sc_lkup_table(pc); 6753 return PHYMOD_E_FAIL; 6754 #endif 6755 pc->sc_done = 0; 6756 } else { 6757 pc->sc_done=1; 6758 #ifdef _DV_TB_ 6759 PHYMOD_DEBUG_ERROR(("SC_DONE set\n")); 6760 return PHYMOD_E_NONE; 6761 #endif 6762 } 6763 } 6764 #endif 6765 6766 /*! 6767 @brief tefmod_set_port_mode_sel , selects the port_mode, 6768 @returns The value PHYMOD_E_NONE upon successful completion. 6769 @details 6770 This is used when we are not using any speed control logic, but instead when bypassing this entire SC logic, this has to be programmed 6771 */ 6772 int tefmod_set_port_mode_sel(PHYMOD_ST* pc, int tsc_touched, tefmod_port_type_t port_type) 6773 { 6774 int port_mode_sel; 6775 uint16_t single_port_mode; 6776 MAIN0_SETUPr_t MAIN0_SETUPr_reg; 6777 6778 TEFMOD_DBG_IN_FUNC_INFO(pc); 6779 port_mode_sel = 0; 6780 if(tsc_touched == 1) 6781 single_port_mode = 0; 6782 else 6783 single_port_mode = 1; 6784 6785 switch(port_type) { 6786 case TEFMOD_MULTI_PORT: port_mode_sel = 0; break; 6787 case TEFMOD_TRI1_PORT: port_mode_sel = 2; break; 6788 case TEFMOD_TRI2_PORT: port_mode_sel = 1; break; 6789 case TEFMOD_DXGXS: port_mode_sel = 3; break; 6790 case TEFMOD_SINGLE_PORT: port_mode_sel = 4; break; 6791 default: break; 6792 } 6793 6794 MAIN0_SETUPr_CLR(MAIN0_SETUPr_reg); 6795 MAIN0_SETUPr_PORT_MODE_SELf_SET(MAIN0_SETUPr_reg, port_mode_sel); 6796 MAIN0_SETUPr_SINGLE_PORT_MODEf_SET(MAIN0_SETUPr_reg, single_port_mode); 6797 PHYMOD_IF_ERR_RETURN(MODIFY_MAIN0_SETUPr(pc, MAIN0_SETUPr_reg)); 6798 6799 return PHYMOD_E_NONE; 6800 } 6801 6802 /*! 6803 @brief firmware load request 6804 @param pc handle to current TSCF context (#PHYMOD_ST) 6805 @returns The value PHYMOD_E_NONE upon successful completion. 6806 @details 6807 */ 6808 int tefmod_firmware_set(PHYMOD_ST* pc) 6809 { 6810 TEFMOD_DBG_IN_FUNC_INFO(pc); 6811 return PHYMOD_E_NONE; 6812 } 6813 6814 #ifdef _SDK_TEFMOD_ 6815 /*! 6816 @brief Controls the init setting/resetting of autoneg registers. 6817 @param pc handle to current TSCF context (#PHYMOD_ST) 6818 @param an_init_st structure tefmod_an_init_t with all the one time autoneg init cfg. 6819 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 6820 @details Get aneg features via #tefmod_an_init_t. 6821 This does not start the autoneg. That is done in tefmod_autoneg_control 6822 */ 6823 int tefmod_autoneg_set_init(PHYMOD_ST* pc, tefmod_an_init_t *an_init_st) /* AUTONEG_SET */ 6824 { 6825 AN_X4_CL73_CTLSr_t AN_X4_CL73_CTLSr_reg; 6826 AN_X4_LD_BASE_ABIL1r_t AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg; 6827 AN_X4_LD_BASE_ABIL0r_t AN_X4_ABILITIES_LD_BASE_ABILITIES_0r_reg; 6828 AN_X4_CL73_CFGr_t AN_X4_CL73_CFGr_t_reg; 6829 6830 TEFMOD_DBG_IN_FUNC_INFO(pc); 6831 AN_X4_CL73_CTLSr_CLR(AN_X4_CL73_CTLSr_reg); 6832 AN_X4_CL73_CTLSr_AN_GOOD_TRAPf_SET(AN_X4_CL73_CTLSr_reg, an_init_st->an_good_trap); 6833 AN_X4_CL73_CTLSr_AN_GOOD_CHECK_TRAPf_SET(AN_X4_CL73_CTLSr_reg, an_init_st->an_good_check_trap); 6834 AN_X4_CL73_CTLSr_LINKFAILTIMER_DISf_SET(AN_X4_CL73_CTLSr_reg, an_init_st->linkfailtimer_dis); 6835 AN_X4_CL73_CTLSr_LINKFAILTIMERQUAL_ENf_SET(AN_X4_CL73_CTLSr_reg, an_init_st->linkfailtimerqua_en); 6836 AN_X4_CL73_CTLSr_AN_FAIL_COUNT_LIMITf_SET(AN_X4_CL73_CTLSr_reg, an_init_st->an_fail_cnt); 6837 AN_X4_CL73_CTLSr_AN_OUI_OVERRIDE_BAM73_ADVf_SET(AN_X4_CL73_CTLSr_reg, an_init_st->bam73_adv_oui); 6838 AN_X4_CL73_CTLSr_AN_OUI_OVERRIDE_BAM73_DETf_SET(AN_X4_CL73_CTLSr_reg, an_init_st->bam73_det_oui); 6839 AN_X4_CL73_CTLSr_AN_OUI_OVERRIDE_HPAM_ADVf_SET(AN_X4_CL73_CTLSr_reg, an_init_st->hpam_adv_oui); 6840 AN_X4_CL73_CTLSr_AN_OUI_OVERRIDE_HPAM_DETf_SET(AN_X4_CL73_CTLSr_reg, an_init_st->hpam_det_oui); 6841 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_CL73_CTLSr(pc, AN_X4_CL73_CTLSr_reg)); 6842 6843 AN_X4_LD_BASE_ABIL1r_CLR(AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg); 6844 if(an_init_st->disable_rf_report == 1) { 6845 AN_X4_LD_BASE_ABIL1r_CL73_REMOTE_FAULTf_SET(AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg, 1); 6846 } 6847 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_LD_BASE_ABIL1r(pc, AN_X4_ABILITIES_LD_BASE_ABILITIES_1r_reg)); 6848 6849 AN_X4_LD_BASE_ABIL0r_CLR(AN_X4_ABILITIES_LD_BASE_ABILITIES_0r_reg); 6850 AN_X4_LD_BASE_ABIL0r_TX_NONCEf_SET(AN_X4_ABILITIES_LD_BASE_ABILITIES_0r_reg, (an_init_st->cl73_transmit_nonce) & 0x1f); 6851 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_LD_BASE_ABIL0r(pc, AN_X4_ABILITIES_LD_BASE_ABILITIES_0r_reg)); 6852 6853 AN_X4_CL73_CFGr_CLR(AN_X4_CL73_CFGr_t_reg); 6854 AN_X4_CL73_CFGr_CL73_NONCE_MATCH_OVERf_SET(AN_X4_CL73_CFGr_t_reg, an_init_st->cl73_nonce_match_over); 6855 AN_X4_CL73_CFGr_CL73_NONCE_MATCH_VALf_SET(AN_X4_CL73_CFGr_t_reg, an_init_st->cl73_nonce_match_val); 6856 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_CL73_CFGr(pc, AN_X4_CL73_CFGr_t_reg)); 6857 6858 return PHYMOD_E_NONE; 6859 } 6860 #endif /* _SDK_TEFMOD_ */ 6861 6862 #ifdef _SDK_TEFMOD_ 6863 /*! 6864 @brief Controls the setting/resetting of autoneg timers. 6865 @param pc handle to current TSCF context (#PHYMOD_ST) 6866 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 6867 @details 6868 6869 */ 6870 int tefmod_autoneg_timer_init(PHYMOD_ST* pc) /* AUTONEG timer set*/ 6871 { 6872 6873 AN_X1_IGNORE_LNK_TMRr_t AN_X1_IGNORE_LNK_TMRr_reg; 6874 AN_X1_CL73_DME_LOCKr_t AN_X1_TIMERS_CL73_DME_LOCKr_reg; 6875 AN_X1_PD_SD_TMRr_t AN_X1_TIMERS_PD_SD_TIMERr_reg; 6876 AN_X1_CL73_BRK_LNKr_t AN_X1_TIMERS_CL73_BREAK_LINKr_reg; 6877 AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72r_t AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_NOT_CL72r_reg; 6878 AN_X1_LNK_FAIL_INHBT_TMR_CL72r_t AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_CL72r_reg; 6879 6880 AN_X1_IGNORE_LNK_TMRr_SET(AN_X1_IGNORE_LNK_TMRr_reg, 0x29a ); 6881 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_IGNORE_LNK_TMRr(pc,AN_X1_IGNORE_LNK_TMRr_reg)); 6882 6883 AN_X1_CL73_DME_LOCKr_SET(AN_X1_TIMERS_CL73_DME_LOCKr_reg, 0x14d4); 6884 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_CL73_DME_LOCKr(pc, AN_X1_TIMERS_CL73_DME_LOCKr_reg)); 6885 6886 AN_X1_PD_SD_TMRr_SET(AN_X1_TIMERS_PD_SD_TIMERr_reg, 0xa6a); 6887 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_PD_SD_TMRr(pc, AN_X1_TIMERS_PD_SD_TIMERr_reg)); 6888 6889 AN_X1_CL73_BRK_LNKr_SET(AN_X1_TIMERS_CL73_BREAK_LINKr_reg, 0x10ed); 6890 PHYMOD_IF_ERR_RETURN (WRITE_AN_X1_CL73_BRK_LNKr(pc, AN_X1_TIMERS_CL73_BREAK_LINKr_reg)); 6891 6892 /* AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72r_SET(AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_NOT_CL72r_reg, 0xbb8); */ 6893 /* Change based on finding in eagle */ 6894 AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72r_SET(AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_NOT_CL72r_reg, 0x3080); 6895 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72r(pc, AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_NOT_CL72r_reg)); 6896 6897 AN_X1_LNK_FAIL_INHBT_TMR_CL72r_SET(AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_CL72r_reg, 0x8382); 6898 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_LNK_FAIL_INHBT_TMR_CL72r(pc, AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_CL72r_reg)); 6899 6900 return PHYMOD_E_NONE; 6901 } 6902 6903 /* change the credit default for gen2 */ 6904 int tefmod_default_init(PHYMOD_ST* pc) /* default set*/ 6905 { 6906 MAIN0_SPD_CTL_GEN2r_t main_spd_ctl_gen2r; 6907 MAIN0_SPD_CTL_GEN2r_CLR(main_spd_ctl_gen2r); 6908 MAIN0_SPD_CTL_GEN2r_TSC_CREDIT_SELf_SET(main_spd_ctl_gen2r, 1); 6909 PHYMOD_IF_ERR_RETURN(MODIFY_MAIN0_SPD_CTL_GEN2r(pc, main_spd_ctl_gen2r)); 6910 6911 return PHYMOD_E_NONE; 6912 6913 } 6914 6915 #endif /* _SDK_TEFMOD_ */ 6916 6917 int tefmod_toggle_sw_speed_change(PHYMOD_ST* pc) 6918 { 6919 int cnt; 6920 int sw_sp_cfg_vld; 6921 SC_X4_CTLr_t SC_X4_CTLr_reg; 6922 SC_X4_STSr_t SC_X4_STSr_reg; 6923 6924 cnt=0; 6925 sw_sp_cfg_vld = 0; 6926 6927 #ifdef _DV_TB_ 6928 printf("Inside toggle_sw_speed_change"); 6929 #endif 6930 6931 SC_X4_CTLr_CLR(SC_X4_CTLr_reg); 6932 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(SC_X4_CTLr_reg, 0); 6933 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_CTLr(pc, SC_X4_CTLr_reg)); 6934 6935 SC_X4_CTLr_CLR(SC_X4_CTLr_reg); 6936 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(SC_X4_CTLr_reg, 1); 6937 SC_X4_CTLr_SPEEDf_SET(SC_X4_CTLr_reg, 0); 6938 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_CTLr(pc, SC_X4_CTLr_reg)); 6939 6940 while (cnt <=2000) { 6941 SC_X4_STSr_CLR(SC_X4_STSr_reg); 6942 PHYMOD_IF_ERR_RETURN(READ_SC_X4_STSr(pc, &SC_X4_STSr_reg)); 6943 cnt = cnt + 1; 6944 if(SC_X4_STSr_SW_SPEED_CONFIG_VLDf_GET(SC_X4_STSr_reg)) { 6945 sw_sp_cfg_vld = 1; 6946 #ifdef _DV_TB_ 6947 printf("sw_speed_cfg_vld set uint :: %d :: lane :: %d\n",pc->unit, pc->this_lane); 6948 #endif 6949 break; 6950 } 6951 } 6952 6953 SC_X4_CTLr_CLR(SC_X4_CTLr_reg); 6954 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(SC_X4_CTLr_reg, 0); 6955 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_CTLr(pc, SC_X4_CTLr_reg)); 6956 6957 if(!sw_sp_cfg_vld) { 6958 return PHYMOD_E_FAIL; 6959 } 6960 return PHYMOD_E_NONE; 6961 } 6962 6963 #ifdef _SDK_TEFMOD_ 6964 /** 6965 @brief To get autoneg control registers. 6966 @param pc handle to current TSCF context (#PHYMOD_ST) 6967 @param an_control reference to struct with autoneg parms #tefmod_an_control_t 6968 @param an_complete status of AN completion 6969 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 6970 @details Upper layer software calls this function to get autoneg 6971 info. 6972 */ 6973 int tefmod_autoneg_control_get(PHYMOD_ST* pc, tefmod_an_control_t *an_control, int *an_complete) 6974 { 6975 AN_X4_CL73_CFGr_t AN_X4_CL73_CFGr_reg; 6976 AN_X4_CL73_CTLSr_t AN_X4_CL73_CTLSr_reg; 6977 AN_X4_AN_MISC_STSr_t AN_X4_AN_MISC_STSr_reg; 6978 uint32_t model, msa_mode, base_ability,base_ability1; 6979 AN_X4_LD_BASE_ABIL_3_GEN2r_t AN_X4_LD_BASE_ABIL_3_GEN2r_reg; 6980 AN_X4_LD_BASE_ABIL_4_GEN2r_t AN_X4_LD_BASE_ABIL_4_GEN2r_reg; 6981 MAIN0_SERDESIDr_t serdesid; 6982 6983 TEFMOD_DBG_IN_FUNC_INFO(pc); 6984 READ_MAIN0_SERDESIDr(pc, &serdesid); 6985 model = MAIN0_SERDESIDr_MODEL_NUMBERf_GET(serdesid); 6986 6987 PHYMOD_IF_ERR_RETURN(READ_AN_X4_CL73_CTLSr(pc, &AN_X4_CL73_CTLSr_reg)); 6988 an_control->pd_kx_en = AN_X4_CL73_CTLSr_PD_KX_ENf_GET(AN_X4_CL73_CTLSr_reg); 6989 /* no pd_kx4_en */ 6990 6991 /*Setting X4 abilities*/ 6992 PHYMOD_IF_ERR_RETURN(READ_AN_X4_CL73_CFGr(pc, &AN_X4_CL73_CFGr_reg)); 6993 6994 if (AN_X4_CL73_CFGr_CL73_BAM_ENABLEf_GET(AN_X4_CL73_CFGr_reg) == 1) { 6995 if (model == TSCF_GEN2) { 6996 6997 PHYMOD_IF_ERR_RETURN(tefmod_an_msa_mode_get(pc, &msa_mode)); 6998 6999 if (msa_mode) { 7000 /* 7001 * Read the msa_mode value. 7002 * If it is 1, it is a MSA/IEEE_MSA AN mode. 7003 * Read the base page values (abil_3 & abil4). 7004 * If it is set, then set AN mode to IEEE_MSA, else set it to MSA mode. 7005 */ 7006 7007 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LD_BASE_ABIL_3_GEN2r(pc, &AN_X4_LD_BASE_ABIL_3_GEN2r_reg)); 7008 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LD_BASE_ABIL_4_GEN2r(pc, &AN_X4_LD_BASE_ABIL_4_GEN2r_reg)); 7009 base_ability = AN_X4_LD_BASE_ABIL_3_GEN2r_GET(AN_X4_LD_BASE_ABIL_3_GEN2r_reg) & 0x0fff; 7010 base_ability1 = AN_X4_LD_BASE_ABIL_4_GEN2r_GET(AN_X4_LD_BASE_ABIL_4_GEN2r_reg) & 0x0fff; 7011 7012 if (!(base_ability) && !(base_ability1)) { 7013 an_control->an_type = TEFMOD_AN_MODE_MSA; 7014 an_control->enable = 1; 7015 } else { 7016 an_control->an_type = TEFMOD_AN_MODE_CL73_MSA; 7017 an_control->enable = 1; 7018 } 7019 } else { 7020 an_control->an_type = TEFMOD_AN_MODE_CL73BAM; 7021 an_control->enable = 1; 7022 } 7023 7024 } else { 7025 an_control->an_type = TEFMOD_AN_MODE_CL73BAM; 7026 an_control->enable = 1; 7027 } 7028 } else if (AN_X4_CL73_CFGr_CL73_HPAM_ENABLEf_GET(AN_X4_CL73_CFGr_reg) == 1) { 7029 an_control->an_type = TEFMOD_AN_MODE_HPAM; 7030 an_control->enable = 1; 7031 } else if (AN_X4_CL73_CFGr_CL73_ENABLEf_GET(AN_X4_CL73_CFGr_reg) == 1) { 7032 an_control->an_type = TEFMOD_AN_MODE_CL73; 7033 an_control->enable = 1; 7034 } else { 7035 an_control->an_type = TEFMOD_AN_MODE_NONE; 7036 an_control->enable = 0; 7037 } 7038 7039 if(AN_X4_CL73_CFGr_AD_TO_CL73_ENf_GET(AN_X4_CL73_CFGr_reg) == 1) { 7040 an_control->an_property_type = TEFMOD_AN_PROPERTY_ENABLE_HPAM_TO_CL73_AUTO; 7041 } else if(AN_X4_CL73_CFGr_BAM_TO_HPAM_AD_ENf_GET(AN_X4_CL73_CFGr_reg) == 1) { 7042 an_control->an_property_type = TEFMOD_AN_PROPERTY_ENABLE_CL73_BAM_TO_HPAM_AUTO; 7043 } 7044 7045 an_control->num_lane_adv = AN_X4_CL73_CFGr_NUM_ADVERTISED_LANESf_GET(AN_X4_CL73_CFGr_reg); 7046 7047 /* an_complete status */ 7048 AN_X4_AN_MISC_STSr_CLR(AN_X4_AN_MISC_STSr_reg); 7049 PHYMOD_IF_ERR_RETURN (READ_AN_X4_AN_MISC_STSr(pc, &AN_X4_AN_MISC_STSr_reg)); 7050 *an_complete = AN_X4_AN_MISC_STSr_AN_COMPLETEf_GET(AN_X4_AN_MISC_STSr_reg); 7051 7052 return PHYMOD_E_NONE; 7053 } 7054 #endif /* _SDK_TEFMOD_ */ 7055 7056 #ifdef _SDK_TEFMOD_ 7057 /** 7058 @brief To get local autoneg advertisement registers. 7059 @param pc handle to current TSCF context (#PHYMOD_ST) 7060 @param an_ability_st receives autoneg info. #tefmod_an_adv_ability_t) 7061 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 7062 @details Upper layer software calls this function to get local autoneg 7063 info. This function is currently not implemented 7064 */ 7065 7066 int tefmod_autoneg_ability_get(PHYMOD_ST* pc, tefmod_an_adv_ability_t *an_ability_st) 7067 { 7068 AN_X4_LD_BASE_ABIL1r_t AN_X4_LD_BASE_ABIL1r_reg; 7069 AN_X4_LD_UP1_ABIL0r_t AN_X4_LD_UP1_ABIL0r_reg; 7070 AN_X4_LD_UP1_ABIL1r_t AN_X4_LD_UP1_ABIL1r_reg; 7071 MAIN0_SERDESIDr_t serdesid; 7072 AN_X4_LD_BASE_ABIL_3_GEN2r_t AN_X4_LD_BASE_ABIL_3_GEN2r_reg; 7073 AN_X4_LD_BASE_ABIL_4_GEN2r_t AN_X4_LD_BASE_ABIL_4_GEN2r_reg; 7074 AN_X4_LD_FEC_BASEPAGE_ABIL_GEN2r_t AN_X4_LD_FEC_BASEPAGE_ABIL_GEN2r_reg; 7075 uint32_t model; 7076 int an_fec = 0; 7077 7078 TEFMOD_DBG_IN_FUNC_INFO(pc); 7079 READ_MAIN0_SERDESIDr(pc, &serdesid); 7080 model = MAIN0_SERDESIDr_MODEL_NUMBERf_GET(serdesid); 7081 7082 READ_AN_X4_LD_UP1_ABIL0r(pc, &AN_X4_LD_UP1_ABIL0r_reg); 7083 an_ability_st->an_bam_speed = AN_X4_LD_UP1_ABIL0r_GET(AN_X4_LD_UP1_ABIL0r_reg) & 0x3ff; 7084 7085 READ_AN_X4_LD_UP1_ABIL1r(pc, &AN_X4_LD_UP1_ABIL1r_reg); 7086 an_ability_st->an_bam_speed1 = AN_X4_LD_UP1_ABIL1r_GET(AN_X4_LD_UP1_ABIL1r_reg) & 0x1f; 7087 7088 READ_AN_X4_LD_BASE_ABIL1r(pc, &AN_X4_LD_BASE_ABIL1r_reg); 7089 an_ability_st->an_base_speed = AN_X4_LD_BASE_ABIL1r_GET(AN_X4_LD_BASE_ABIL1r_reg) & 0x3f; 7090 7091 an_ability_st->an_pause = AN_X4_LD_BASE_ABIL1r_CL73_PAUSEf_GET(AN_X4_LD_BASE_ABIL1r_reg); 7092 7093 an_fec = AN_X4_LD_BASE_ABIL1r_FEC_REQf_GET(AN_X4_LD_BASE_ABIL1r_reg); 7094 if (an_fec == 0x3) { 7095 if (AN_X4_LD_BASE_ABIL1r_BASE_100G_CR4f_GET(AN_X4_LD_BASE_ABIL1r_reg) || 7096 AN_X4_LD_BASE_ABIL1r_BASE_100G_KR4f_GET(AN_X4_LD_BASE_ABIL1r_reg) ) { 7097 an_ability_st->an_fec = TEFMOD_FEC_CL91_SUPRTD_REQSTD; 7098 } else { 7099 an_ability_st->an_fec = TEFMOD_FEC_CL74_SUPRTD_REQSTD; 7100 } 7101 } else { 7102 an_ability_st->an_fec = (an_fec==0x1) ? TEFMOD_FEC_SUPRTD_NOT_REQSTD : TEFMOD_FEC_NOT_SUPRTD; 7103 } 7104 7105 an_fec = 0; 7106 if (model == TSCF_GEN2) { 7107 AN_X4_LD_BASE_ABIL_3_GEN2r_CLR(AN_X4_LD_BASE_ABIL_3_GEN2r_reg); 7108 AN_X4_LD_BASE_ABIL_4_GEN2r_CLR(AN_X4_LD_BASE_ABIL_4_GEN2r_reg); 7109 AN_X4_LD_FEC_BASEPAGE_ABIL_GEN2r_CLR(AN_X4_LD_FEC_BASEPAGE_ABIL_GEN2r_reg); 7110 7111 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LD_BASE_ABIL_3_GEN2r(pc, &AN_X4_LD_BASE_ABIL_3_GEN2r_reg)); 7112 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LD_BASE_ABIL_4_GEN2r(pc, &AN_X4_LD_BASE_ABIL_4_GEN2r_reg)); 7113 7114 if (AN_X4_LD_BASE_ABIL_3_GEN2r_BASE_25G_KR1_ENf_GET(AN_X4_LD_BASE_ABIL_3_GEN2r_reg)) { 7115 an_ability_st->an_base_speed |= (1<<TEFMOD_CL73_25GBASE_KR1); 7116 } 7117 if (AN_X4_LD_BASE_ABIL_3_GEN2r_BASE_25G_CR1_ENf_GET(AN_X4_LD_BASE_ABIL_3_GEN2r_reg)) { 7118 an_ability_st->an_base_speed |= (1<<TEFMOD_CL73_25GBASE_CR1); 7119 } 7120 if (AN_X4_LD_BASE_ABIL_4_GEN2r_BASE_25G_KRS1_ENf_GET(AN_X4_LD_BASE_ABIL_4_GEN2r_reg)) { 7121 an_ability_st->an_base_speed |= (1<<TEFMOD_CL73_25GBASE_KRS1); 7122 } 7123 if (AN_X4_LD_BASE_ABIL_4_GEN2r_BASE_25G_CRS1_ENf_GET(AN_X4_LD_BASE_ABIL_4_GEN2r_reg)) { 7124 an_ability_st->an_base_speed |= (1<<TEFMOD_CL73_25GBASE_CRS1); 7125 } 7126 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LD_FEC_BASEPAGE_ABIL_GEN2r(pc, &AN_X4_LD_FEC_BASEPAGE_ABIL_GEN2r_reg)); 7127 if (AN_X4_LD_FEC_BASEPAGE_ABIL_GEN2r_BASE_R_FEC_REQ_ENf_GET(AN_X4_LD_FEC_BASEPAGE_ABIL_GEN2r_reg)) { 7128 an_fec |= 0x1; 7129 } 7130 if (AN_X4_LD_FEC_BASEPAGE_ABIL_GEN2r_RS_FEC_REQ_ENf_GET(AN_X4_LD_FEC_BASEPAGE_ABIL_GEN2r_reg)) { 7131 an_fec |= 0x2; 7132 } 7133 if ((an_ability_st->an_fec == TEFMOD_FEC_SUPRTD_NOT_REQSTD) || 7134 (an_ability_st->an_fec == TEFMOD_FEC_NOT_SUPRTD)) { 7135 if (an_fec) { 7136 an_ability_st->an_fec = 0; 7137 if (an_fec & 0x1) { 7138 an_ability_st->an_fec |= TEFMOD_FEC_CL74_SUPRTD_REQSTD; 7139 } 7140 if (an_fec & 0x2) { 7141 an_ability_st->an_fec |= TEFMOD_FEC_CL91_SUPRTD_REQSTD; 7142 } 7143 } 7144 } else { 7145 if (an_fec & 0x1) { 7146 an_ability_st->an_fec |= TEFMOD_FEC_CL74_SUPRTD_REQSTD; 7147 } 7148 if (an_fec & 0x2) { 7149 an_ability_st->an_fec |= TEFMOD_FEC_CL91_SUPRTD_REQSTD; 7150 } 7151 } 7152 } 7153 7154 return PHYMOD_E_NONE; 7155 } 7156 #endif /* _SDK_TEFMOD_ */ 7157 7158 /** 7159 @brief Controls port RX squelch 7160 @param pc handle to current TSCE context (#PHYMOD_ST) 7161 @param enable is the control to RX squelch 7162 @returns The value PHYMOD_E_NONE upon successful completion. 7163 @details Controls port RX squelch 7164 */ 7165 int tefmod_rx_squelch_set(PHYMOD_ST *pc, int enable) 7166 { 7167 SIGDET_CTL1r_t sigdet_ctl; 7168 7169 SIGDET_CTL1r_CLR(sigdet_ctl); 7170 READ_SIGDET_CTL1r(pc, &sigdet_ctl); 7171 7172 if(enable){ 7173 SIGDET_CTL1r_SIGNAL_DETECT_FRCf_SET(sigdet_ctl, 1); 7174 SIGDET_CTL1r_SIGNAL_DETECT_FRC_VALf_SET(sigdet_ctl, 0); 7175 } else { 7176 SIGDET_CTL1r_SIGNAL_DETECT_FRCf_SET(sigdet_ctl, 0); 7177 SIGDET_CTL1r_SIGNAL_DETECT_FRC_VALf_SET(sigdet_ctl, 0); 7178 } 7179 PHYMOD_IF_ERR_RETURN(MODIFY_SIGDET_CTL1r(pc, sigdet_ctl)); 7180 7181 return PHYMOD_E_NONE; 7182 } 7183 7184 /** 7185 @brief Controls port TX squelch 7186 @param pc handle to current TSCE context (#PHYMOD_ST) 7187 @param enable is the control to TX squelch 7188 @returns The value PHYMOD_E_NONE upon successful completion. 7189 @details Controls port TX squelch 7190 */ 7191 int tefmod_tx_squelch_set(PHYMOD_ST *pc, int enable) 7192 { 7193 TXFIR_MISC_CTL1r_t tx_misc_ctl; 7194 phymod_access_t pa_copy; 7195 int i, start_lane = 0, num_lane = 0; 7196 7197 PHYMOD_MEMCPY(&pa_copy, pc, sizeof(pa_copy)); 7198 PHYMOD_IF_ERR_RETURN 7199 (phymod_util_lane_config_get(pc, &start_lane, &num_lane)); 7200 7201 TXFIR_MISC_CTL1r_CLR(tx_misc_ctl); 7202 pa_copy.lane_mask = 0x1 << start_lane; 7203 7204 PHYMOD_IF_ERR_RETURN(READ_TXFIR_MISC_CTL1r(&pa_copy, &tx_misc_ctl)); 7205 7206 TXFIR_MISC_CTL1r_SDK_TX_DISABLEf_SET(tx_misc_ctl, enable); 7207 7208 for (i = 0; i < num_lane; i++) { 7209 if (!PHYMOD_LANEPBMP_MEMBER(pc->lane_mask, start_lane + i)) { 7210 continue; 7211 } 7212 pa_copy.lane_mask = 0x1 << (i + start_lane); 7213 PHYMOD_IF_ERR_RETURN(MODIFY_TXFIR_MISC_CTL1r(&pa_copy, tx_misc_ctl)); 7214 } 7215 return PHYMOD_E_NONE; 7216 } 7217 7218 7219 /** 7220 @brief Controls port TX/RX squelch 7221 @param pc handle to current TSCE context (#PHYMOD_ST) 7222 @param enable is the control to TX/RX squelch. Enable=1 means enable the port,no squelch 7223 @returns The value PHYMOD_E_NONE upon successful completion. 7224 @details Controls port TX/RX squelch 7225 */ 7226 int tefmod_port_enable_set(PHYMOD_ST *pc, int enable) 7227 { 7228 if (enable) { 7229 tefmod_rx_squelch_set(pc, 0); 7230 tefmod_tx_squelch_set(pc, 0); 7231 } else { 7232 tefmod_rx_squelch_set(pc, 1); 7233 tefmod_tx_squelch_set(pc, 1); 7234 } 7235 7236 return PHYMOD_E_NONE; 7237 } 7238 7239 /** 7240 @brief Get port TX squelch control settings 7241 @param pc handle to current TSCE context (#PHYMOD_ST) 7242 @param val Receiver for status of TX squelch 7243 @returns The value PHYMOD_E_NONE upon successful completion. 7244 @details Get port TX squelch control settings 7245 */ 7246 int tefmod_tx_squelch_get(PHYMOD_ST *pc, int *val) 7247 { 7248 TXFIR_MISC_CTL1r_t tx_misc_ctl; 7249 7250 TXFIR_MISC_CTL1r_CLR(tx_misc_ctl); 7251 7252 PHYMOD_IF_ERR_RETURN(READ_TXFIR_MISC_CTL1r(pc, &tx_misc_ctl)); 7253 *val = TXFIR_MISC_CTL1r_SDK_TX_DISABLEf_GET(tx_misc_ctl); 7254 7255 return PHYMOD_E_NONE; 7256 } 7257 7258 /** 7259 @brief Gets port RX squelch settings 7260 @param pc handle to current TSCE context (#PHYMOD_ST) 7261 @param val Receiver for status of RX squelch 7262 @returns The value PHYMOD_E_NONE upon successful completion. 7263 @details Gets port RX squelch settings 7264 */ 7265 int tefmod_rx_squelch_get(PHYMOD_ST *pc, int *val) 7266 { 7267 SIGDET_CTL1r_t sigdet_ctl; 7268 7269 SIGDET_CTL1r_CLR(sigdet_ctl); 7270 7271 PHYMOD_IF_ERR_RETURN(READ_SIGDET_CTL1r(pc, &sigdet_ctl)); 7272 *val = SIGDET_CTL1r_SIGNAL_DETECT_FRCf_GET(sigdet_ctl); 7273 7274 return PHYMOD_E_NONE; 7275 } 7276 7277 /** 7278 @brief Get port TX/RX squelch Settings 7279 @param pc handle to current TSCE context (#PHYMOD_ST) 7280 @param tx_enable - get the TX squelch settings 7281 @param rx_enable - get the RX squelch settings 7282 @returns The value PHYMOD_E_NONE upon successful completion. 7283 @details Controls port TX/RX squelch 7284 */ 7285 int tefmod_port_enable_get(PHYMOD_ST *pc, int *tx_enable, int *rx_enable) 7286 { 7287 7288 tefmod_rx_squelch_get(pc, rx_enable); 7289 tefmod_tx_squelch_get(pc, tx_enable); 7290 7291 return PHYMOD_E_NONE; 7292 } 7293 7294 #ifdef _SDK_TEFMOD_ 7295 /** 7296 @brief To get remote autoneg advertisement registers. 7297 @param pc handle to current TSCF context (#PHYMOD_ST) 7298 @param an_ability_st receives autoneg info. #tefmod_an_adv_ability_t) 7299 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 7300 @details Upper layer software calls this function to get autoneg 7301 info. This function is not currently implemented. 7302 */ 7303 int tefmod_autoneg_remote_ability_get(PHYMOD_ST* pc, tefmod_an_adv_ability_t *an_ability_st) 7304 { 7305 7306 uint32_t data; 7307 uint32_t user_code; 7308 AN_X4_LP_BASE1r_t AN_X4_LP_BASE1r_reg; 7309 AN_X4_LP_BASE3r_t AN_X4_LP_BASE3r_reg; 7310 7311 AN_X4_LP_OUI_UP3r_t AN_X4_LP_OUI_UP3r_reg; 7312 AN_X4_LP_OUI_UP4r_t AN_X4_LP_OUI_UP4r_reg; 7313 7314 TEFMOD_DBG_IN_FUNC_INFO(pc); 7315 7316 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LP_BASE1r(pc, &AN_X4_LP_BASE1r_reg)); 7317 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LP_BASE3r(pc, &AN_X4_LP_BASE3r_reg)); 7318 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LP_OUI_UP3r(pc, &AN_X4_LP_OUI_UP3r_reg)); 7319 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LP_OUI_UP4r(pc, &AN_X4_LP_OUI_UP4r_reg)); 7320 7321 7322 /*an_ability_st->cl73_adv.an_bam_speed = 0xdead;*/ 7323 an_ability_st->an_bam_speed = 0x0; 7324 7325 user_code = AN_X4_LP_OUI_UP3r_BAM_CODEf_GET(AN_X4_LP_OUI_UP3r_reg) << 11 ; 7326 data = AN_X4_LP_OUI_UP4r_USER_DEFINED_DATAf_GET(AN_X4_LP_OUI_UP4r_reg); 7327 7328 if(data&(1<<1)) { 7329 an_ability_st->an_bam_speed |=(1<<0) ; 7330 } else { 7331 user_code |= data ; 7332 if(user_code == 0xabe20) 7333 an_ability_st->an_bam_speed |=(1<<0) ; 7334 } 7335 if(data&(1<<0)) an_ability_st->an_bam_speed |=(1<<1) ; 7336 7337 an_ability_st->an_pause = (AN_X4_LP_BASE1r_reg.v[0] >> 10 ) & 0x3;; 7338 an_ability_st->an_fec = (AN_X4_LP_BASE3r_reg.v[0] >> 14) & 0x3; 7339 7340 if (AN_X4_LP_BASE1r_SYMMETRIC_PAUSEf_GET(AN_X4_LP_BASE1r_reg)) { 7341 an_ability_st->an_pause |= TEFMOD_SYMM_PAUSE; 7342 } 7343 if (AN_X4_LP_BASE1r_ASYMMETRIC_PAUSEf_GET(AN_X4_LP_BASE1r_reg)) { 7344 an_ability_st->an_pause |= TEFMOD_ASYM_PAUSE; 7345 } 7346 7347 if(AN_X4_LP_BASE3r_FEC_REQUESTEDf_GET(AN_X4_LP_BASE3r_reg)) { 7348 an_ability_st->an_fec = (1 << 1); 7349 } 7350 if(AN_X4_LP_BASE3r_FEC_ABILITYf_GET(AN_X4_LP_BASE3r_reg)) { 7351 an_ability_st->an_fec |= 1 ; 7352 } 7353 7354 7355 return PHYMOD_E_NONE; 7356 } 7357 7358 /** 7359 @brief Sets the field of the Soft Table 7360 @param pc handle to current TSCE context (#PHYMOD_ST) 7361 @param st_entry_no: The ST to write to(0..3) 7362 @param st_control_field,: The ST field to write to 7363 @param st_field_value: The ST value to write to the field 7364 returns The value PHYMOD_E_NONE upon successful completion. 7365 @details Sets the field of the Soft Table 7366 */ 7367 int tefmod_st_control_field_set (PHYMOD_ST* pc,uint16_t st_entry_no, override_type_t st_control_field, uint16_t st_field_value) 7368 { 7369 SC_X1_SPD_OVRR0_SPDr_t SC_X1_SPD_OVRR0_SPDr_reg; 7370 SC_X1_SPD_OVRR1_SPDr_t SC_X1_SPD_OVRR1_SPDr_reg; 7371 SC_X1_SPD_OVRR2_SPDr_t SC_X1_SPD_OVRR2_SPDr_reg; 7372 SC_X1_SPD_OVRR3_SPDr_t SC_X1_SPD_OVRR3_SPDr_reg; 7373 7374 SC_X1_SPD_OVRR0_0r_t SC_X1_SPD_OVRR0_0r_reg; 7375 SC_X1_SPD_OVRR1_0r_t SC_X1_SPD_OVRR1_0r_reg; 7376 SC_X1_SPD_OVRR2_0r_t SC_X1_SPD_OVRR2_0r_reg; 7377 SC_X1_SPD_OVRR3_0r_t SC_X1_SPD_OVRR3_0r_reg; 7378 7379 SC_X1_SPD_OVRR0_1r_t SC_X1_SPD_OVRR0_1r_reg; 7380 SC_X1_SPD_OVRR1_1r_t SC_X1_SPD_OVRR1_1r_reg; 7381 SC_X1_SPD_OVRR2_1r_t SC_X1_SPD_OVRR2_1r_reg; 7382 SC_X1_SPD_OVRR3_1r_t SC_X1_SPD_OVRR3_1r_reg; 7383 7384 SC_X1_SPD_OVRR0_2r_t SC_X1_SPD_OVRR0_2r_reg; 7385 SC_X1_SPD_OVRR1_2r_t SC_X1_SPD_OVRR1_2r_reg; 7386 SC_X1_SPD_OVRR2_2r_t SC_X1_SPD_OVRR2_2r_reg; 7387 SC_X1_SPD_OVRR3_2r_t SC_X1_SPD_OVRR3_2r_reg; 7388 7389 SC_X1_SPD_OVRR0_3r_t SC_X1_SPD_OVRR0_3r_reg; 7390 SC_X1_SPD_OVRR1_3r_t SC_X1_SPD_OVRR1_3r_reg; 7391 SC_X1_SPD_OVRR2_3r_t SC_X1_SPD_OVRR2_3r_reg; 7392 SC_X1_SPD_OVRR3_3r_t SC_X1_SPD_OVRR3_3r_reg; 7393 7394 SC_X1_SPD_OVRR0_4r_t SC_X1_SPD_OVRR0_4r_reg; 7395 SC_X1_SPD_OVRR1_4r_t SC_X1_SPD_OVRR1_4r_reg; 7396 SC_X1_SPD_OVRR2_4r_t SC_X1_SPD_OVRR2_4r_reg; 7397 SC_X1_SPD_OVRR3_4r_t SC_X1_SPD_OVRR3_4r_reg; 7398 7399 SC_X1_SPD_OVRR0_5r_t SC_X1_SPD_OVRR0_5r_reg; 7400 SC_X1_SPD_OVRR1_5r_t SC_X1_SPD_OVRR1_5r_reg; 7401 SC_X1_SPD_OVRR2_5r_t SC_X1_SPD_OVRR2_5r_reg; 7402 SC_X1_SPD_OVRR3_5r_t SC_X1_SPD_OVRR3_5r_reg; 7403 7404 TEFMOD_DBG_IN_FUNC_INFO(pc); 7405 7406 switch (st_entry_no){ 7407 case 0: 7408 SC_X1_SPD_OVRR0_SPDr_CLR(SC_X1_SPD_OVRR0_SPDr_reg); 7409 SC_X1_SPD_OVRR0_0r_CLR(SC_X1_SPD_OVRR0_0r_reg); 7410 SC_X1_SPD_OVRR0_1r_CLR(SC_X1_SPD_OVRR0_1r_reg); 7411 SC_X1_SPD_OVRR0_2r_CLR(SC_X1_SPD_OVRR0_2r_reg); 7412 SC_X1_SPD_OVRR0_3r_CLR(SC_X1_SPD_OVRR0_3r_reg); 7413 SC_X1_SPD_OVRR0_4r_CLR(SC_X1_SPD_OVRR0_4r_reg); 7414 SC_X1_SPD_OVRR0_5r_CLR(SC_X1_SPD_OVRR0_5r_reg); 7415 break; 7416 case 1: 7417 SC_X1_SPD_OVRR1_SPDr_CLR(SC_X1_SPD_OVRR1_SPDr_reg); 7418 SC_X1_SPD_OVRR1_0r_CLR(SC_X1_SPD_OVRR1_0r_reg); 7419 SC_X1_SPD_OVRR1_1r_CLR(SC_X1_SPD_OVRR1_1r_reg); 7420 SC_X1_SPD_OVRR1_2r_CLR(SC_X1_SPD_OVRR1_2r_reg); 7421 SC_X1_SPD_OVRR1_3r_CLR(SC_X1_SPD_OVRR1_3r_reg); 7422 SC_X1_SPD_OVRR1_4r_CLR(SC_X1_SPD_OVRR1_4r_reg); 7423 SC_X1_SPD_OVRR1_5r_CLR(SC_X1_SPD_OVRR1_5r_reg); 7424 break; 7425 case 2: 7426 SC_X1_SPD_OVRR2_SPDr_CLR(SC_X1_SPD_OVRR2_SPDr_reg); 7427 SC_X1_SPD_OVRR2_0r_CLR(SC_X1_SPD_OVRR2_0r_reg); 7428 SC_X1_SPD_OVRR2_1r_CLR(SC_X1_SPD_OVRR2_1r_reg); 7429 SC_X1_SPD_OVRR2_2r_CLR(SC_X1_SPD_OVRR2_2r_reg); 7430 SC_X1_SPD_OVRR2_3r_CLR(SC_X1_SPD_OVRR2_3r_reg); 7431 SC_X1_SPD_OVRR2_4r_CLR(SC_X1_SPD_OVRR2_4r_reg); 7432 SC_X1_SPD_OVRR2_5r_CLR(SC_X1_SPD_OVRR2_5r_reg); 7433 break; 7434 case 3: 7435 SC_X1_SPD_OVRR3_SPDr_CLR(SC_X1_SPD_OVRR3_SPDr_reg); 7436 SC_X1_SPD_OVRR3_0r_CLR(SC_X1_SPD_OVRR3_0r_reg); 7437 SC_X1_SPD_OVRR3_1r_CLR(SC_X1_SPD_OVRR3_1r_reg); 7438 SC_X1_SPD_OVRR3_2r_CLR(SC_X1_SPD_OVRR3_2r_reg); 7439 SC_X1_SPD_OVRR3_3r_CLR(SC_X1_SPD_OVRR3_3r_reg); 7440 SC_X1_SPD_OVRR3_4r_CLR(SC_X1_SPD_OVRR3_4r_reg); 7441 SC_X1_SPD_OVRR3_5r_CLR(SC_X1_SPD_OVRR3_5r_reg); 7442 break; 7443 } 7444 switch (st_entry_no){ 7445 case 0: 7446 switch (st_control_field){ 7447 case OVERRIDE_NUM_LANES: 7448 SC_X1_SPD_OVRR0_SPDr_NUM_LANESf_SET(SC_X1_SPD_OVRR0_SPDr_reg, st_field_value); 7449 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_SPDr(pc, SC_X1_SPD_OVRR0_SPDr_reg)); 7450 break; 7451 case OVERRIDE_OS_MODE: 7452 SC_X1_SPD_OVRR0_0r_OS_MODEf_SET(SC_X1_SPD_OVRR0_0r_reg, st_field_value); 7453 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_0r(pc, SC_X1_SPD_OVRR0_0r_reg)); 7454 break; 7455 case OVERRIDE_T_FIFO_MODE: 7456 SC_X1_SPD_OVRR0_0r_T_FIFO_MODEf_SET(SC_X1_SPD_OVRR0_0r_reg, st_field_value); 7457 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_0r(pc, SC_X1_SPD_OVRR0_0r_reg)); 7458 break; 7459 case OVERRIDE_T_ENC_MODE: 7460 SC_X1_SPD_OVRR0_0r_T_ENC_MODEf_SET(SC_X1_SPD_OVRR0_0r_reg, st_field_value); 7461 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_0r(pc, SC_X1_SPD_OVRR0_0r_reg)); 7462 break; 7463 case OVERRIDE_T_HG2_ENABLE: 7464 SC_X1_SPD_OVRR0_0r_T_HG2_ENABLEf_SET(SC_X1_SPD_OVRR0_0r_reg, st_field_value); 7465 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_0r(pc, SC_X1_SPD_OVRR0_0r_reg)); 7466 break; 7467 case OVERRIDE_SCR_MODE: 7468 SC_X1_SPD_OVRR0_0r_SCR_MODEf_SET(SC_X1_SPD_OVRR0_0r_reg, st_field_value); 7469 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_0r(pc, SC_X1_SPD_OVRR0_0r_reg)); 7470 break; 7471 case OVERRIDE_DESCR_MODE_OEN: 7472 SC_X1_SPD_OVRR0_1r_DESCR_MODEf_SET(SC_X1_SPD_OVRR0_1r_reg, st_field_value); 7473 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_1r(pc, SC_X1_SPD_OVRR0_1r_reg)); 7474 break; 7475 case OVERRIDE_DEC_TL_MODE: 7476 SC_X1_SPD_OVRR0_1r_DEC_TL_MODEf_SET(SC_X1_SPD_OVRR0_1r_reg, st_field_value); 7477 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_1r(pc, SC_X1_SPD_OVRR0_1r_reg)); 7478 break; 7479 case OVERRIDE_DESKEW_MODE: 7480 SC_X1_SPD_OVRR0_1r_DESKEW_MODEf_SET(SC_X1_SPD_OVRR0_1r_reg, st_field_value); 7481 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_1r(pc, SC_X1_SPD_OVRR0_1r_reg)); 7482 break; 7483 case OVERRIDE_DEC_FSM_MODE: 7484 SC_X1_SPD_OVRR0_1r_DEC_FSM_MODEf_SET(SC_X1_SPD_OVRR0_1r_reg, st_field_value); 7485 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_1r(pc, SC_X1_SPD_OVRR0_1r_reg)); 7486 break; 7487 case OVERRIDE_R_HG2_ENABLE: 7488 SC_X1_SPD_OVRR0_1r_R_HG2_ENABLEf_SET(SC_X1_SPD_OVRR0_1r_reg, st_field_value); 7489 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_1r(pc, SC_X1_SPD_OVRR0_1r_reg)); 7490 break; 7491 case OVERRIDE_CL72_EN: 7492 SC_X1_SPD_OVRR0_0r_CL72_ENf_SET(SC_X1_SPD_OVRR0_0r_reg, st_field_value); 7493 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_0r(pc, SC_X1_SPD_OVRR0_0r_reg)); 7494 break; 7495 case OVERRIDE_CLOCKCNT0: 7496 SC_X1_SPD_OVRR0_2r_CLOCKCNT0f_SET(SC_X1_SPD_OVRR0_2r_reg, st_field_value); 7497 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_2r(pc, SC_X1_SPD_OVRR0_2r_reg)); 7498 break; 7499 case OVERRIDE_CLOCKCNT1: 7500 SC_X1_SPD_OVRR0_3r_CLOCKCNT1f_SET(SC_X1_SPD_OVRR0_3r_reg, st_field_value); 7501 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_3r(pc, SC_X1_SPD_OVRR0_3r_reg)); 7502 break; 7503 case OVERRIDE_LOOPCNT0: 7504 SC_X1_SPD_OVRR0_4r_LOOPCNT0f_SET(SC_X1_SPD_OVRR0_4r_reg, st_field_value); 7505 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_4r(pc, SC_X1_SPD_OVRR0_4r_reg)); 7506 break; 7507 case OVERRIDE_LOOPCNT1: 7508 SC_X1_SPD_OVRR0_4r_LOOPCNT1f_SET(SC_X1_SPD_OVRR0_4r_reg, st_field_value); 7509 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_4r(pc, SC_X1_SPD_OVRR0_4r_reg)); 7510 break; 7511 case OVERRIDE_MAC_CREDITGENCNT: 7512 SC_X1_SPD_OVRR0_5r_MAC_CREDITGENCNTf_SET(SC_X1_SPD_OVRR0_5r_reg, st_field_value); 7513 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_5r(pc, SC_X1_SPD_OVRR0_5r_reg)); 7514 break; 7515 default: 7516 return PHYMOD_E_FAIL; 7517 break; 7518 } 7519 break; 7520 case 1: 7521 switch (st_control_field){ 7522 case OVERRIDE_NUM_LANES: 7523 SC_X1_SPD_OVRR1_SPDr_NUM_LANESf_SET(SC_X1_SPD_OVRR1_SPDr_reg, st_field_value); 7524 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_SPDr(pc, SC_X1_SPD_OVRR1_SPDr_reg)); 7525 break; 7526 case OVERRIDE_OS_MODE: 7527 SC_X1_SPD_OVRR1_0r_OS_MODEf_SET(SC_X1_SPD_OVRR1_0r_reg, st_field_value); 7528 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_0r(pc, SC_X1_SPD_OVRR1_0r_reg)); 7529 break; 7530 case OVERRIDE_T_FIFO_MODE: 7531 SC_X1_SPD_OVRR1_0r_T_FIFO_MODEf_SET(SC_X1_SPD_OVRR1_0r_reg, st_field_value); 7532 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_0r(pc, SC_X1_SPD_OVRR1_0r_reg)); 7533 break; 7534 case OVERRIDE_T_ENC_MODE: 7535 SC_X1_SPD_OVRR1_0r_T_ENC_MODEf_SET(SC_X1_SPD_OVRR1_0r_reg, st_field_value); 7536 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_0r(pc, SC_X1_SPD_OVRR1_0r_reg)); 7537 break; 7538 case OVERRIDE_T_HG2_ENABLE: 7539 SC_X1_SPD_OVRR1_0r_T_HG2_ENABLEf_SET(SC_X1_SPD_OVRR1_0r_reg, st_field_value); 7540 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_0r(pc, SC_X1_SPD_OVRR1_0r_reg)); 7541 break; 7542 case OVERRIDE_SCR_MODE: 7543 SC_X1_SPD_OVRR1_0r_SCR_MODEf_SET(SC_X1_SPD_OVRR1_0r_reg, st_field_value); 7544 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_0r(pc, SC_X1_SPD_OVRR1_0r_reg)); 7545 break; 7546 case OVERRIDE_DESCR_MODE_OEN: 7547 SC_X1_SPD_OVRR1_1r_DESCR_MODEf_SET(SC_X1_SPD_OVRR1_1r_reg, st_field_value); 7548 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_1r(pc, SC_X1_SPD_OVRR1_1r_reg)); 7549 break; 7550 case OVERRIDE_DEC_TL_MODE: 7551 SC_X1_SPD_OVRR1_1r_DEC_TL_MODEf_SET(SC_X1_SPD_OVRR1_1r_reg, st_field_value); 7552 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_1r(pc, SC_X1_SPD_OVRR1_1r_reg)); 7553 break; 7554 case OVERRIDE_DESKEW_MODE: 7555 SC_X1_SPD_OVRR1_1r_DESKEW_MODEf_SET(SC_X1_SPD_OVRR1_1r_reg, st_field_value); 7556 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_1r(pc, SC_X1_SPD_OVRR1_1r_reg)); 7557 break; 7558 case OVERRIDE_DEC_FSM_MODE: 7559 SC_X1_SPD_OVRR1_1r_DEC_FSM_MODEf_SET(SC_X1_SPD_OVRR1_1r_reg, st_field_value); 7560 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_1r(pc, SC_X1_SPD_OVRR1_1r_reg)); 7561 break; 7562 case OVERRIDE_R_HG2_ENABLE: 7563 SC_X1_SPD_OVRR1_1r_R_HG2_ENABLEf_SET(SC_X1_SPD_OVRR1_1r_reg, st_field_value); 7564 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_1r(pc, SC_X1_SPD_OVRR1_1r_reg)); 7565 break; 7566 case OVERRIDE_CL72_EN: 7567 SC_X1_SPD_OVRR1_0r_CL72_ENf_SET(SC_X1_SPD_OVRR1_0r_reg, st_field_value); 7568 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_0r(pc, SC_X1_SPD_OVRR1_0r_reg)); 7569 break; 7570 case OVERRIDE_CLOCKCNT0: 7571 SC_X1_SPD_OVRR1_2r_CLOCKCNT0f_SET(SC_X1_SPD_OVRR1_2r_reg, st_field_value); 7572 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_2r(pc, SC_X1_SPD_OVRR1_2r_reg)); 7573 break; 7574 case OVERRIDE_CLOCKCNT1: 7575 SC_X1_SPD_OVRR1_3r_CLOCKCNT1f_SET(SC_X1_SPD_OVRR1_3r_reg, st_field_value); 7576 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_3r(pc, SC_X1_SPD_OVRR1_3r_reg)); 7577 break; 7578 case OVERRIDE_LOOPCNT0: 7579 SC_X1_SPD_OVRR1_4r_LOOPCNT0f_SET(SC_X1_SPD_OVRR1_4r_reg, st_field_value); 7580 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_4r(pc, SC_X1_SPD_OVRR1_4r_reg)); 7581 break; 7582 case OVERRIDE_LOOPCNT1: 7583 SC_X1_SPD_OVRR1_4r_LOOPCNT1f_SET(SC_X1_SPD_OVRR1_4r_reg, st_field_value); 7584 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_4r(pc, SC_X1_SPD_OVRR1_4r_reg)); 7585 break; 7586 case OVERRIDE_MAC_CREDITGENCNT: 7587 SC_X1_SPD_OVRR1_5r_MAC_CREDITGENCNTf_SET(SC_X1_SPD_OVRR1_5r_reg, st_field_value); 7588 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_5r(pc, SC_X1_SPD_OVRR1_5r_reg)); 7589 break; 7590 default: 7591 return PHYMOD_E_FAIL; 7592 break; 7593 } 7594 break; 7595 case 2: 7596 switch (st_control_field){ 7597 case OVERRIDE_NUM_LANES: 7598 SC_X1_SPD_OVRR2_SPDr_NUM_LANESf_SET(SC_X1_SPD_OVRR2_SPDr_reg, st_field_value); 7599 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_SPDr(pc, SC_X1_SPD_OVRR2_SPDr_reg)); 7600 break; 7601 case OVERRIDE_OS_MODE: 7602 SC_X1_SPD_OVRR2_0r_OS_MODEf_SET(SC_X1_SPD_OVRR2_0r_reg, st_field_value); 7603 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_0r(pc, SC_X1_SPD_OVRR2_0r_reg)); 7604 break; 7605 case OVERRIDE_T_FIFO_MODE: 7606 SC_X1_SPD_OVRR2_0r_T_FIFO_MODEf_SET(SC_X1_SPD_OVRR2_0r_reg, st_field_value); 7607 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_0r(pc, SC_X1_SPD_OVRR2_0r_reg)); 7608 break; 7609 case OVERRIDE_T_ENC_MODE: 7610 SC_X1_SPD_OVRR2_0r_T_ENC_MODEf_SET(SC_X1_SPD_OVRR2_0r_reg, st_field_value); 7611 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_0r(pc, SC_X1_SPD_OVRR2_0r_reg)); 7612 break; 7613 case OVERRIDE_T_HG2_ENABLE: 7614 SC_X1_SPD_OVRR2_0r_T_HG2_ENABLEf_SET(SC_X1_SPD_OVRR2_0r_reg, st_field_value); 7615 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_0r(pc, SC_X1_SPD_OVRR2_0r_reg)); 7616 break; 7617 case OVERRIDE_SCR_MODE: 7618 SC_X1_SPD_OVRR2_0r_SCR_MODEf_SET(SC_X1_SPD_OVRR2_0r_reg, st_field_value); 7619 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_0r(pc, SC_X1_SPD_OVRR2_0r_reg)); 7620 break; 7621 case OVERRIDE_DESCR_MODE_OEN: 7622 SC_X1_SPD_OVRR2_1r_DESCR_MODEf_SET(SC_X1_SPD_OVRR2_1r_reg, st_field_value); 7623 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_1r(pc, SC_X1_SPD_OVRR2_1r_reg)); 7624 break; 7625 case OVERRIDE_DEC_TL_MODE: 7626 SC_X1_SPD_OVRR2_1r_DEC_TL_MODEf_SET(SC_X1_SPD_OVRR2_1r_reg, st_field_value); 7627 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_1r(pc, SC_X1_SPD_OVRR2_1r_reg)); 7628 break; 7629 case OVERRIDE_DESKEW_MODE: 7630 SC_X1_SPD_OVRR2_1r_DESKEW_MODEf_SET(SC_X1_SPD_OVRR2_1r_reg, st_field_value); 7631 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_1r(pc, SC_X1_SPD_OVRR2_1r_reg)); 7632 break; 7633 case OVERRIDE_DEC_FSM_MODE: 7634 SC_X1_SPD_OVRR2_1r_DEC_FSM_MODEf_SET(SC_X1_SPD_OVRR2_1r_reg, st_field_value); 7635 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_1r(pc, SC_X1_SPD_OVRR2_1r_reg)); 7636 break; 7637 case OVERRIDE_R_HG2_ENABLE: 7638 SC_X1_SPD_OVRR2_1r_R_HG2_ENABLEf_SET(SC_X1_SPD_OVRR2_1r_reg, st_field_value); 7639 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_1r(pc, SC_X1_SPD_OVRR2_1r_reg)); 7640 break; 7641 case OVERRIDE_CL72_EN: 7642 SC_X1_SPD_OVRR2_0r_CL72_ENf_SET(SC_X1_SPD_OVRR2_0r_reg, st_field_value); 7643 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_0r(pc, SC_X1_SPD_OVRR2_0r_reg)); 7644 break; 7645 case OVERRIDE_CLOCKCNT0: 7646 SC_X1_SPD_OVRR2_2r_CLOCKCNT0f_SET(SC_X1_SPD_OVRR2_2r_reg, st_field_value); 7647 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_2r(pc, SC_X1_SPD_OVRR2_2r_reg)); 7648 break; 7649 case OVERRIDE_CLOCKCNT1: 7650 SC_X1_SPD_OVRR2_3r_CLOCKCNT1f_SET(SC_X1_SPD_OVRR2_3r_reg, st_field_value); 7651 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_3r(pc, SC_X1_SPD_OVRR2_3r_reg)); 7652 break; 7653 case OVERRIDE_LOOPCNT0: 7654 SC_X1_SPD_OVRR2_4r_LOOPCNT0f_SET(SC_X1_SPD_OVRR2_4r_reg, st_field_value); 7655 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_4r(pc, SC_X1_SPD_OVRR2_4r_reg)); 7656 break; 7657 case OVERRIDE_LOOPCNT1: 7658 SC_X1_SPD_OVRR2_4r_LOOPCNT1f_SET(SC_X1_SPD_OVRR2_4r_reg, st_field_value); 7659 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_4r(pc, SC_X1_SPD_OVRR2_4r_reg)); 7660 break; 7661 case OVERRIDE_MAC_CREDITGENCNT: 7662 SC_X1_SPD_OVRR2_5r_MAC_CREDITGENCNTf_SET(SC_X1_SPD_OVRR2_5r_reg, st_field_value); 7663 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_5r(pc, SC_X1_SPD_OVRR2_5r_reg)); 7664 break; 7665 default: 7666 return PHYMOD_E_FAIL; 7667 break; 7668 } 7669 break; 7670 case 3: 7671 switch (st_control_field){ 7672 case OVERRIDE_NUM_LANES: 7673 SC_X1_SPD_OVRR3_SPDr_NUM_LANESf_SET(SC_X1_SPD_OVRR3_SPDr_reg, st_field_value); 7674 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_SPDr(pc, SC_X1_SPD_OVRR3_SPDr_reg)); 7675 break; 7676 case OVERRIDE_OS_MODE: 7677 SC_X1_SPD_OVRR3_0r_OS_MODEf_SET(SC_X1_SPD_OVRR3_0r_reg, st_field_value); 7678 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_0r(pc, SC_X1_SPD_OVRR3_0r_reg)); 7679 break; 7680 case OVERRIDE_T_FIFO_MODE: 7681 SC_X1_SPD_OVRR3_0r_T_FIFO_MODEf_SET(SC_X1_SPD_OVRR3_0r_reg, st_field_value); 7682 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_0r(pc, SC_X1_SPD_OVRR3_0r_reg)); 7683 break; 7684 case OVERRIDE_T_ENC_MODE: 7685 SC_X1_SPD_OVRR3_0r_T_ENC_MODEf_SET(SC_X1_SPD_OVRR3_0r_reg, st_field_value); 7686 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_0r(pc, SC_X1_SPD_OVRR3_0r_reg)); 7687 break; 7688 case OVERRIDE_T_HG2_ENABLE: 7689 SC_X1_SPD_OVRR3_0r_T_HG2_ENABLEf_SET(SC_X1_SPD_OVRR3_0r_reg, st_field_value); 7690 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_0r(pc, SC_X1_SPD_OVRR3_0r_reg)); 7691 break; 7692 case OVERRIDE_SCR_MODE: 7693 SC_X1_SPD_OVRR3_0r_SCR_MODEf_SET(SC_X1_SPD_OVRR3_0r_reg, st_field_value); 7694 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_0r(pc, SC_X1_SPD_OVRR3_0r_reg)); 7695 break; 7696 case OVERRIDE_DESCR_MODE_OEN: 7697 SC_X1_SPD_OVRR3_1r_DESCR_MODEf_SET(SC_X1_SPD_OVRR3_1r_reg, st_field_value); 7698 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_1r(pc, SC_X1_SPD_OVRR3_1r_reg)); 7699 break; 7700 case OVERRIDE_DEC_TL_MODE: 7701 SC_X1_SPD_OVRR3_1r_DEC_TL_MODEf_SET(SC_X1_SPD_OVRR3_1r_reg, st_field_value); 7702 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_1r(pc, SC_X1_SPD_OVRR3_1r_reg)); 7703 break; 7704 case OVERRIDE_DESKEW_MODE: 7705 SC_X1_SPD_OVRR3_1r_DESKEW_MODEf_SET(SC_X1_SPD_OVRR3_1r_reg, st_field_value); 7706 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_1r(pc, SC_X1_SPD_OVRR3_1r_reg)); 7707 break; 7708 case OVERRIDE_DEC_FSM_MODE: 7709 SC_X1_SPD_OVRR3_1r_DEC_FSM_MODEf_SET(SC_X1_SPD_OVRR3_1r_reg, st_field_value); 7710 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_1r(pc, SC_X1_SPD_OVRR3_1r_reg)); 7711 break; 7712 case OVERRIDE_R_HG2_ENABLE: 7713 SC_X1_SPD_OVRR3_1r_R_HG2_ENABLEf_SET(SC_X1_SPD_OVRR3_1r_reg, st_field_value); 7714 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_1r(pc, SC_X1_SPD_OVRR3_1r_reg)); 7715 break; 7716 case OVERRIDE_CL72_EN: 7717 SC_X1_SPD_OVRR3_0r_CL72_ENf_SET(SC_X1_SPD_OVRR3_0r_reg, st_field_value); 7718 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_0r(pc, SC_X1_SPD_OVRR3_0r_reg)); 7719 break; 7720 case OVERRIDE_CLOCKCNT0: 7721 SC_X1_SPD_OVRR3_2r_CLOCKCNT0f_SET(SC_X1_SPD_OVRR3_2r_reg, st_field_value); 7722 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_2r(pc, SC_X1_SPD_OVRR3_2r_reg)); 7723 break; 7724 case OVERRIDE_CLOCKCNT1: 7725 SC_X1_SPD_OVRR3_3r_CLOCKCNT1f_SET(SC_X1_SPD_OVRR3_3r_reg, st_field_value); 7726 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_3r(pc, SC_X1_SPD_OVRR3_3r_reg)); 7727 break; 7728 case OVERRIDE_LOOPCNT0: 7729 SC_X1_SPD_OVRR3_4r_LOOPCNT0f_SET(SC_X1_SPD_OVRR3_4r_reg, st_field_value); 7730 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_4r(pc, SC_X1_SPD_OVRR3_4r_reg)); 7731 break; 7732 case OVERRIDE_LOOPCNT1: 7733 SC_X1_SPD_OVRR3_4r_LOOPCNT1f_SET(SC_X1_SPD_OVRR3_4r_reg, st_field_value); 7734 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_4r(pc, SC_X1_SPD_OVRR3_4r_reg)); 7735 break; 7736 case OVERRIDE_MAC_CREDITGENCNT: 7737 SC_X1_SPD_OVRR3_5r_MAC_CREDITGENCNTf_SET(SC_X1_SPD_OVRR3_5r_reg, st_field_value); 7738 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_5r(pc, SC_X1_SPD_OVRR3_5r_reg)); 7739 break; 7740 default: 7741 return PHYMOD_E_FAIL; 7742 break; 7743 } 7744 break; 7745 } 7746 return PHYMOD_E_NONE; 7747 } 7748 7749 /** 7750 @brief EEE Control Set 7751 @param pc handle to current TSCF context (#PHYMOD_ST) 7752 @param enable EEE control(enable/disable) 7753 @returns The value PHYMOD_E_NONE upon successful completion 7754 @details EEE Control 7755 enable =1 : Allow LPI pass through. i.e. dont convert LPI. 7756 enable =0 : Convert LPI to idle. So MAC will not see it. 7757 7758 */ 7759 int tefmod_eee_control_set(PHYMOD_ST* pc, uint32_t enable) 7760 { 7761 RX_X4_PCS_CTL0r_t reg_pcs_ctrl0; 7762 7763 TEFMOD_DBG_IN_FUNC_INFO(pc); 7764 RX_X4_PCS_CTL0r_CLR(reg_pcs_ctrl0); 7765 READ_RX_X4_PCS_CTL0r(pc, ®_pcs_ctrl0); 7766 7767 RX_X4_PCS_CTL0r_LPI_ENABLEf_SET(reg_pcs_ctrl0, enable & 0x1); 7768 PHYMOD_IF_ERR_RETURN (MODIFY_RX_X4_PCS_CTL0r(pc, reg_pcs_ctrl0)); 7769 return PHYMOD_E_NONE; 7770 } 7771 7772 /** 7773 @brief EEE Control Get 7774 @param pc handle to current TSCF context (#PHYMOD_ST) 7775 @param enable handle to receive EEE control 7776 @returns The value PHYMOD_E_NONE upon successful completion 7777 @details EEE Control 7778 enable =1 : Allow LPI pass through. i.e. dont convert LPI. 7779 enable =0 : Convert LPI to idle. So MAC will not see it. 7780 7781 */ 7782 int tefmod_eee_control_get(PHYMOD_ST* pc, uint32_t *enable) 7783 { 7784 RX_X4_PCS_CTL0r_t reg_pcs_ctrl0; 7785 7786 TEFMOD_DBG_IN_FUNC_INFO(pc); 7787 RX_X4_PCS_CTL0r_CLR(reg_pcs_ctrl0); 7788 7789 PHYMOD_IF_ERR_RETURN (READ_RX_X4_PCS_CTL0r(pc, ®_pcs_ctrl0)); 7790 *enable = RX_X4_PCS_CTL0r_LPI_ENABLEf_GET(reg_pcs_ctrl0); 7791 return PHYMOD_E_NONE; 7792 } 7793 7794 7795 /** 7796 @brief Setup the default for cl74 to ieee compliance 7797 @param pc handle to current TSCE context (#PHYMOD_ST) 7798 @returns The value PHYMOD_E_NONE upon successful completion 7799 @details cl74 control set to ieee compliance 7800 */ 7801 int tefmod_cl74_chng_default (PHYMOD_ST* pc) 7802 { 7803 RX_X4_FEC1r_t RX_X4_FEC1reg; 7804 phymod_access_t pa_copy; 7805 int i; 7806 7807 TEFMOD_DBG_IN_FUNC_INFO(pc); 7808 7809 PHYMOD_MEMCPY(&pa_copy, pc, sizeof(pa_copy)); 7810 RX_X4_FEC1r_CLR(RX_X4_FEC1reg); 7811 7812 for (i = 0; i <4; i++) { 7813 pa_copy.lane_mask = 0x1 << i; 7814 PHYMOD_IF_ERR_RETURN(WRITE_RX_X4_FEC1r(&pa_copy, RX_X4_FEC1reg)); 7815 } 7816 return PHYMOD_E_NONE; 7817 } 7818 7819 int tefmod_cl91_ecc_clear(PHYMOD_ST* pc, uint32_t model) 7820 { 7821 RX_X1_ECC_STS_FEC_MEM_0_GEN2r_t RX_X1_ECC_STS_FEC_MEM_0_GEN2r_reg; 7822 RX_X1_ECC_STS_FEC_MEM_1_GEN2r_t RX_X1_ECC_STS_FEC_MEM_1_GEN2r_reg; 7823 RX_X1_ECC_STS_FEC_MEM_2_GEN2r_t RX_X1_ECC_STS_FEC_MEM_2_GEN2r_reg; 7824 RX_X1_ECC_STS_FEC_MEM_3_GEN2r_t RX_X1_ECC_STS_FEC_MEM_3_GEN2r_reg; 7825 RX_X1_ECC_INTR_STS_1BIT_GEN2r_t RX_X1_ECC_INTR_STS_1BIT_GEN2r_reg; 7826 RX_X1_ECC_INTR_STS_2BIT_GEN2r_t RX_X1_ECC_INTR_STS_2BIT_GEN2r_reg; 7827 7828 RX_X4_ECC_STS_CL91_BUFFER_BLK_0_GEN2r_t RX_X4_ECC_STS_CL91_BUFFER_BLK_0_GEN2r_reg; 7829 RX_X4_ECC_STS_CL91_BUFFER_BLK_1_GEN2r_t RX_X4_ECC_STS_CL91_BUFFER_BLK_1_GEN2r_reg; 7830 RX_X4_ECC_STS_CL91_BUFFER_BLK_2_GEN2r_t RX_X4_ECC_STS_CL91_BUFFER_BLK_2_GEN2r_reg; 7831 RX_X4_ECC_STS_DESKEW_MEM_0_GEN2r_t RX_X4_ECC_STS_DESKEW_MEM_0_GEN2r_reg; 7832 RX_X4_ECC_STS_DESKEW_MEM_1_GEN2r_t RX_X4_ECC_STS_DESKEW_MEM_1_GEN2r_reg; 7833 RX_X4_ECC_STS_DESKEW_MEM_2_GEN2r_t RX_X4_ECC_STS_DESKEW_MEM_2_GEN2r_reg; 7834 RX_X4_ECC_INTR_STS_1BIT_GEN2r_t RX_X4_ECC_INTR_STS_1BIT_GEN2r_reg; 7835 RX_X4_ECC_INTR_STS_2BIT_GEN2r_t RX_X4_ECC_INTR_STS_2BIT_GEN2r_reg; 7836 phymod_access_t pa_copy; 7837 int i; 7838 7839 TEFMOD_DBG_IN_FUNC_INFO(pc); 7840 7841 PHYMOD_MEMCPY(&pa_copy, pc, sizeof(pa_copy)); 7842 RX_X1_ECC_STS_FEC_MEM_0_GEN2r_CLR(RX_X1_ECC_STS_FEC_MEM_0_GEN2r_reg); 7843 RX_X1_ECC_STS_FEC_MEM_1_GEN2r_CLR(RX_X1_ECC_STS_FEC_MEM_1_GEN2r_reg); 7844 RX_X1_ECC_STS_FEC_MEM_2_GEN2r_CLR(RX_X1_ECC_STS_FEC_MEM_2_GEN2r_reg); 7845 RX_X1_ECC_STS_FEC_MEM_3_GEN2r_CLR(RX_X1_ECC_STS_FEC_MEM_3_GEN2r_reg); 7846 RX_X1_ECC_INTR_STS_1BIT_GEN2r_CLR(RX_X1_ECC_INTR_STS_1BIT_GEN2r_reg); 7847 RX_X1_ECC_INTR_STS_2BIT_GEN2r_CLR(RX_X1_ECC_INTR_STS_2BIT_GEN2r_reg); 7848 7849 RX_X4_ECC_STS_CL91_BUFFER_BLK_0_GEN2r_CLR(RX_X4_ECC_STS_CL91_BUFFER_BLK_0_GEN2r_reg); 7850 RX_X4_ECC_STS_CL91_BUFFER_BLK_1_GEN2r_CLR(RX_X4_ECC_STS_CL91_BUFFER_BLK_1_GEN2r_reg); 7851 RX_X4_ECC_STS_CL91_BUFFER_BLK_2_GEN2r_CLR(RX_X4_ECC_STS_CL91_BUFFER_BLK_2_GEN2r_reg); 7852 RX_X4_ECC_STS_DESKEW_MEM_0_GEN2r_CLR(RX_X4_ECC_STS_DESKEW_MEM_0_GEN2r_reg); 7853 RX_X4_ECC_STS_DESKEW_MEM_1_GEN2r_CLR(RX_X4_ECC_STS_DESKEW_MEM_1_GEN2r_reg); 7854 RX_X4_ECC_STS_DESKEW_MEM_2_GEN2r_CLR(RX_X4_ECC_STS_DESKEW_MEM_2_GEN2r_reg); 7855 RX_X4_ECC_INTR_STS_1BIT_GEN2r_CLR(RX_X4_ECC_INTR_STS_1BIT_GEN2r_reg); 7856 RX_X4_ECC_INTR_STS_2BIT_GEN2r_CLR(RX_X4_ECC_INTR_STS_2BIT_GEN2r_reg); 7857 7858 if (model == TSCF_GEN2) { 7859 7860 /* Read Clear */ 7861 PHYMOD_IF_ERR_RETURN(READ_RX_X1_ECC_STS_FEC_MEM_0_GEN2r(&pa_copy, &RX_X1_ECC_STS_FEC_MEM_0_GEN2r_reg)); 7862 PHYMOD_IF_ERR_RETURN(READ_RX_X1_ECC_STS_FEC_MEM_1_GEN2r(&pa_copy, &RX_X1_ECC_STS_FEC_MEM_1_GEN2r_reg)); 7863 PHYMOD_IF_ERR_RETURN(READ_RX_X1_ECC_STS_FEC_MEM_2_GEN2r(&pa_copy, &RX_X1_ECC_STS_FEC_MEM_2_GEN2r_reg)); 7864 PHYMOD_IF_ERR_RETURN(READ_RX_X1_ECC_STS_FEC_MEM_3_GEN2r(&pa_copy, &RX_X1_ECC_STS_FEC_MEM_3_GEN2r_reg)); 7865 PHYMOD_IF_ERR_RETURN(READ_RX_X1_ECC_INTR_STS_1BIT_GEN2r(&pa_copy, &RX_X1_ECC_INTR_STS_1BIT_GEN2r_reg)); 7866 PHYMOD_IF_ERR_RETURN(READ_RX_X1_ECC_INTR_STS_2BIT_GEN2r(&pa_copy, &RX_X1_ECC_INTR_STS_2BIT_GEN2r_reg)); 7867 7868 for (i = 0; i < 4; i++) { 7869 pa_copy.lane_mask = 0x1 << i; 7870 PHYMOD_IF_ERR_RETURN(READ_RX_X4_ECC_STS_CL91_BUFFER_BLK_0_GEN2r(&pa_copy, &RX_X4_ECC_STS_CL91_BUFFER_BLK_0_GEN2r_reg)); 7871 PHYMOD_IF_ERR_RETURN(READ_RX_X4_ECC_STS_CL91_BUFFER_BLK_1_GEN2r(&pa_copy, &RX_X4_ECC_STS_CL91_BUFFER_BLK_1_GEN2r_reg)); 7872 PHYMOD_IF_ERR_RETURN(READ_RX_X4_ECC_STS_CL91_BUFFER_BLK_2_GEN2r(&pa_copy, &RX_X4_ECC_STS_CL91_BUFFER_BLK_2_GEN2r_reg)); 7873 PHYMOD_IF_ERR_RETURN(READ_RX_X4_ECC_STS_DESKEW_MEM_0_GEN2r(&pa_copy, &RX_X4_ECC_STS_DESKEW_MEM_0_GEN2r_reg)); 7874 PHYMOD_IF_ERR_RETURN(READ_RX_X4_ECC_STS_DESKEW_MEM_1_GEN2r(&pa_copy, &RX_X4_ECC_STS_DESKEW_MEM_1_GEN2r_reg)); 7875 PHYMOD_IF_ERR_RETURN(READ_RX_X4_ECC_STS_DESKEW_MEM_2_GEN2r(&pa_copy, &RX_X4_ECC_STS_DESKEW_MEM_2_GEN2r_reg)); 7876 PHYMOD_IF_ERR_RETURN(READ_RX_X4_ECC_INTR_STS_1BIT_GEN2r(&pa_copy, &RX_X4_ECC_INTR_STS_1BIT_GEN2r_reg)); 7877 PHYMOD_IF_ERR_RETURN(READ_RX_X4_ECC_INTR_STS_2BIT_GEN2r(&pa_copy, &RX_X4_ECC_INTR_STS_2BIT_GEN2r_reg)); 7878 } 7879 } 7880 7881 return PHYMOD_E_NONE; 7882 } 7883 7884 int tefmod_an_msa_mode_set(PHYMOD_ST* pc, uint32_t val) 7885 { 7886 uint32_t model; 7887 MAIN0_SERDESIDr_t serdesid; 7888 7889 TEFMOD_DBG_IN_FUNC_INFO(pc); 7890 READ_MAIN0_SERDESIDr(pc, &serdesid); 7891 model = MAIN0_SERDESIDr_MODEL_NUMBERf_GET(serdesid); 7892 7893 if (model == TSCF_GEN2) { 7894 AN_X4_LD_PAGE_0_GEN2r_t AN_X4_LD_PAGE_0_GEN2r_reg; 7895 AN_X4_LD_PAGE_0_GEN2r_CLR(AN_X4_LD_PAGE_0_GEN2r_reg); 7896 AN_X4_LD_PAGE_0_GEN2r_SET(AN_X4_LD_PAGE_0_GEN2r_reg, val & 0x1); 7897 7898 /********Setting AN_X4_LD_PAGE_0_GEN2r_t 0xc1e2*****/ 7899 PHYMOD_IF_ERR_RETURN(WRITE_AN_X4_LD_PAGE_0_GEN2r(pc, AN_X4_LD_PAGE_0_GEN2r_reg)); 7900 } 7901 7902 return PHYMOD_E_NONE; 7903 } 7904 7905 int tefmod_an_msa_mode_get(PHYMOD_ST* pc, uint32_t* val) 7906 { 7907 uint32_t model; 7908 MAIN0_SERDESIDr_t serdesid; 7909 7910 TEFMOD_DBG_IN_FUNC_INFO(pc); 7911 READ_MAIN0_SERDESIDr(pc, &serdesid); 7912 model = MAIN0_SERDESIDr_MODEL_NUMBERf_GET(serdesid); 7913 if (model == TSCF_GEN2) { 7914 AN_X4_LD_PAGE_0_GEN2r_t AN_X4_LD_PAGE_0_GEN2r_reg; 7915 AN_X4_LD_PAGE_0_GEN2r_CLR(AN_X4_LD_PAGE_0_GEN2r_reg); 7916 /********Getting AN_X4_LD_PAGE_0_GEN2r_t 0xc1e2*****/ 7917 PHYMOD_IF_ERR_RETURN (READ_AN_X4_LD_PAGE_0_GEN2r(pc, &AN_X4_LD_PAGE_0_GEN2r_reg)); 7918 *val = AN_X4_LD_PAGE_0_GEN2r_LD_PAGE_0f_GET(AN_X4_LD_PAGE_0_GEN2r_reg); 7919 } 7920 return PHYMOD_E_NONE; 7921 } 7922 7923 7924 int tefmod_an_oui_set(PHYMOD_ST* pc, tefmod_an_oui_t oui) 7925 { 7926 AN_X1_OUI_LWRr_t AN_X1_CONTROL_OUI_LOWERr_reg; 7927 AN_X1_OUI_UPRr_t AN_X1_CONTROL_OUI_UPPERr_reg; 7928 AN_X4_CL73_CTLSr_t AN_X4_CL73_CTLSr_reg; 7929 7930 TEFMOD_DBG_IN_FUNC_INFO(pc); 7931 7932 AN_X1_OUI_LWRr_CLR(AN_X1_CONTROL_OUI_LOWERr_reg); 7933 AN_X1_OUI_LWRr_SET(AN_X1_CONTROL_OUI_LOWERr_reg, oui.oui & 0xffff); 7934 /********Setting AN_X1_OUI_LWR 0x9241*****/ 7935 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_OUI_LWRr(pc, AN_X1_CONTROL_OUI_LOWERr_reg)); 7936 AN_X1_OUI_UPRr_CLR(AN_X1_CONTROL_OUI_UPPERr_reg); 7937 AN_X1_OUI_UPRr_SET(AN_X1_CONTROL_OUI_UPPERr_reg, (oui.oui >> 16) & 0xff); 7938 7939 /********Setting AN_X1_OUI_UPR 0x9240*****/ 7940 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_OUI_UPRr(pc, AN_X1_CONTROL_OUI_UPPERr_reg)); 7941 7942 AN_X4_CL73_CTLSr_CLR(AN_X4_CL73_CTLSr_reg); 7943 AN_X4_CL73_CTLSr_AN_OUI_OVERRIDE_BAM73_ADVf_SET(AN_X4_CL73_CTLSr_reg, oui.oui_override_bam73_adv); 7944 AN_X4_CL73_CTLSr_AN_OUI_OVERRIDE_BAM73_DETf_SET(AN_X4_CL73_CTLSr_reg, oui.oui_override_bam73_det); 7945 AN_X4_CL73_CTLSr_AN_OUI_OVERRIDE_HPAM_ADVf_SET(AN_X4_CL73_CTLSr_reg, oui.oui_override_hpam_adv); 7946 AN_X4_CL73_CTLSr_AN_OUI_OVERRIDE_HPAM_DETf_SET(AN_X4_CL73_CTLSr_reg, oui.oui_override_hpam_det); 7947 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_CL73_CTLSr(pc, AN_X4_CL73_CTLSr_reg)); 7948 7949 return PHYMOD_E_NONE; 7950 } 7951 7952 int tefmod_an_oui_get(PHYMOD_ST* pc, tefmod_an_oui_t* oui) { 7953 7954 AN_X1_OUI_LWRr_t AN_X1_CONTROL_OUI_LOWERr_reg; 7955 AN_X1_OUI_UPRr_t AN_X1_CONTROL_OUI_UPPERr_reg; 7956 AN_X4_CL73_CTLSr_t AN_X4_CL73_CTLSr_reg; 7957 7958 TEFMOD_DBG_IN_FUNC_INFO(pc); 7959 7960 PHYMOD_IF_ERR_RETURN(READ_AN_X1_OUI_LWRr(pc, &AN_X1_CONTROL_OUI_LOWERr_reg)); 7961 PHYMOD_IF_ERR_RETURN(READ_AN_X1_OUI_UPRr(pc, &AN_X1_CONTROL_OUI_UPPERr_reg)); 7962 PHYMOD_IF_ERR_RETURN(READ_AN_X4_CL73_CTLSr(pc, &AN_X4_CL73_CTLSr_reg)); 7963 7964 oui->oui = AN_X1_OUI_LWRr_GET(AN_X1_CONTROL_OUI_LOWERr_reg); 7965 oui->oui |= ((AN_X1_OUI_UPRr_GET(AN_X1_CONTROL_OUI_UPPERr_reg)) << 16); 7966 7967 oui->oui_override_bam73_adv = AN_X4_CL73_CTLSr_AN_OUI_OVERRIDE_BAM73_ADVf_GET(AN_X4_CL73_CTLSr_reg); 7968 oui->oui_override_bam73_det = AN_X4_CL73_CTLSr_AN_OUI_OVERRIDE_BAM73_DETf_GET(AN_X4_CL73_CTLSr_reg); 7969 oui->oui_override_hpam_adv = AN_X4_CL73_CTLSr_AN_OUI_OVERRIDE_HPAM_ADVf_GET(AN_X4_CL73_CTLSr_reg); 7970 oui->oui_override_hpam_det = AN_X4_CL73_CTLSr_AN_OUI_OVERRIDE_HPAM_DETf_GET(AN_X4_CL73_CTLSr_reg); 7971 7972 7973 return PHYMOD_E_NONE; 7974 } 7975 7976 int tefmod_autoneg_status_get(PHYMOD_ST* pc, int *an_en, int *an_done) 7977 { 7978 AN_X4_CL73_CFGr_t AN_X4_CL73_CFGr_reg; 7979 AN_X4_AN_MISC_STSr_t AN_X4_AN_MISC_STSr_reg; 7980 7981 AN_X4_CL73_CFGr_CLR(AN_X4_CL73_CFGr_reg); 7982 AN_X4_AN_MISC_STSr_CLR(AN_X4_AN_MISC_STSr_reg); 7983 7984 PHYMOD_IF_ERR_RETURN (READ_AN_X4_CL73_CFGr(pc, &AN_X4_CL73_CFGr_reg)); 7985 PHYMOD_IF_ERR_RETURN (READ_AN_X4_AN_MISC_STSr(pc, &AN_X4_AN_MISC_STSr_reg)); 7986 7987 *an_en = AN_X4_CL73_CFGr_CL73_AN_RESTARTf_GET(AN_X4_CL73_CFGr_reg); 7988 *an_done = AN_X4_AN_MISC_STSr_AN_COMPLETEf_GET(AN_X4_AN_MISC_STSr_reg); 7989 7990 return PHYMOD_E_NONE; 7991 } 7992 7993 int tefmod_autoneg_lp_status_get(PHYMOD_ST* pc, uint16_t *baseP0, uint16_t *baseP1, uint16_t *baseP2, uint16_t *nextP3, uint16_t *nextP4) 7994 { 7995 AN_X4_LP_BASE1r_t AN_X4_LP_BASE1r_reg; 7996 AN_X4_LP_BASE2r_t AN_X4_LP_BASE2r_reg; 7997 AN_X4_LP_BASE3r_t AN_X4_LP_BASE3r_reg; 7998 AN_X4_LP_OUI_UP4r_t AN_X4_LP_OUI_UP4r_reg; 7999 AN_X4_LP_OUI_UP5r_t AN_X4_LP_OUI_UP5r_reg; 8000 8001 AN_X4_LP_BASE1r_CLR( AN_X4_LP_BASE1r_reg); 8002 AN_X4_LP_BASE2r_CLR( AN_X4_LP_BASE2r_reg); 8003 AN_X4_LP_BASE3r_CLR( AN_X4_LP_BASE3r_reg); 8004 AN_X4_LP_OUI_UP4r_CLR(AN_X4_LP_OUI_UP4r_reg); 8005 AN_X4_LP_OUI_UP5r_CLR(AN_X4_LP_OUI_UP5r_reg); 8006 8007 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LP_BASE1r(pc, &AN_X4_LP_BASE1r_reg)); 8008 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LP_BASE2r(pc, &AN_X4_LP_BASE2r_reg)); 8009 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LP_BASE3r(pc, &AN_X4_LP_BASE3r_reg)); 8010 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LP_OUI_UP4r(pc,&AN_X4_LP_OUI_UP4r_reg)); 8011 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LP_OUI_UP5r(pc,&AN_X4_LP_OUI_UP5r_reg)); 8012 8013 *baseP0 = AN_X4_LP_BASE1r_GET(AN_X4_LP_BASE1r_reg); 8014 *baseP1 = AN_X4_LP_BASE2r_GET(AN_X4_LP_BASE2r_reg); 8015 *baseP2 = AN_X4_LP_BASE3r_GET(AN_X4_LP_BASE3r_reg); 8016 *nextP3 = AN_X4_LP_OUI_UP4r_GET(AN_X4_LP_OUI_UP4r_reg); 8017 *nextP4 = AN_X4_LP_OUI_UP5r_GET(AN_X4_LP_OUI_UP5r_reg); 8018 8019 return PHYMOD_E_NONE; 8020 } 8021 8022 8023 int tefmod_hg2_codec_set(PHYMOD_ST* pc, tefmod_hg2_codec_t hg2_codec) 8024 { 8025 TX_X4_ENC0r_t TX_X4_ENC0_reg; 8026 RX_X4_DEC_CTL0r_t RX_X4_DEC_CTL0_reg; 8027 8028 READ_TX_X4_ENC0r(pc, &TX_X4_ENC0_reg); 8029 READ_RX_X4_DEC_CTL0r(pc, &RX_X4_DEC_CTL0_reg); 8030 switch (hg2_codec) { 8031 case TEFMOD_HG2_CODEC_OFF: 8032 TX_X4_ENC0r_HG2_ENABLEf_SET(TX_X4_ENC0_reg, 0); 8033 TX_X4_ENC0r_HG2_CODECf_SET(TX_X4_ENC0_reg, 1); 8034 TX_X4_ENC0r_HG2_MESSAGE_INVALID_CODE_ENABLEf_SET(TX_X4_ENC0_reg, 1); 8035 RX_X4_DEC_CTL0r_HG2_ENABLEf_SET(RX_X4_DEC_CTL0_reg, 0); 8036 RX_X4_DEC_CTL0r_HG2_CODECf_SET(RX_X4_DEC_CTL0_reg, 1); 8037 RX_X4_DEC_CTL0r_HG2_MESSAGE_INVALID_CODE_ENABLEf_SET(RX_X4_DEC_CTL0_reg, 1); 8038 break; 8039 case TEFMOD_HG2_CODEC_ON_8BYTE_IPG: 8040 TX_X4_ENC0r_HG2_ENABLEf_SET(TX_X4_ENC0_reg, 1); 8041 TX_X4_ENC0r_HG2_CODECf_SET(TX_X4_ENC0_reg, 1); 8042 TX_X4_ENC0r_HG2_MESSAGE_INVALID_CODE_ENABLEf_SET(TX_X4_ENC0_reg, 1); 8043 RX_X4_DEC_CTL0r_HG2_ENABLEf_SET(RX_X4_DEC_CTL0_reg, 1); 8044 RX_X4_DEC_CTL0r_HG2_CODECf_SET(RX_X4_DEC_CTL0_reg, 1); 8045 RX_X4_DEC_CTL0r_HG2_MESSAGE_INVALID_CODE_ENABLEf_SET(RX_X4_DEC_CTL0_reg, 1); 8046 break; 8047 case TEFMOD_HG2_CODEC_ON_9BYTE_IPG: 8048 TX_X4_ENC0r_HG2_ENABLEf_SET(TX_X4_ENC0_reg, 1); 8049 TX_X4_ENC0r_HG2_CODECf_SET(TX_X4_ENC0_reg, 0); 8050 TX_X4_ENC0r_HG2_MESSAGE_INVALID_CODE_ENABLEf_SET(TX_X4_ENC0_reg, 1); 8051 RX_X4_DEC_CTL0r_HG2_ENABLEf_SET(RX_X4_DEC_CTL0_reg, 1); 8052 RX_X4_DEC_CTL0r_HG2_CODECf_SET(RX_X4_DEC_CTL0_reg, 0); 8053 RX_X4_DEC_CTL0r_HG2_MESSAGE_INVALID_CODE_ENABLEf_SET(RX_X4_DEC_CTL0_reg, 1); 8054 break; 8055 default: 8056 TX_X4_ENC0r_HG2_ENABLEf_SET(TX_X4_ENC0_reg, 0); 8057 TX_X4_ENC0r_HG2_CODECf_SET(TX_X4_ENC0_reg, 1); 8058 TX_X4_ENC0r_HG2_MESSAGE_INVALID_CODE_ENABLEf_SET(TX_X4_ENC0_reg, 1); 8059 RX_X4_DEC_CTL0r_HG2_ENABLEf_SET(RX_X4_DEC_CTL0_reg, 0); 8060 RX_X4_DEC_CTL0r_HG2_CODECf_SET(RX_X4_DEC_CTL0_reg, 1); 8061 RX_X4_DEC_CTL0r_HG2_MESSAGE_INVALID_CODE_ENABLEf_SET(RX_X4_DEC_CTL0_reg, 1); 8062 break; 8063 } 8064 MODIFY_RX_X4_DEC_CTL0r(pc, RX_X4_DEC_CTL0_reg); 8065 MODIFY_TX_X4_ENC0r(pc,TX_X4_ENC0_reg); 8066 8067 return PHYMOD_E_NONE; 8068 } 8069 8070 int tefmod_hg2_codec_get(PHYMOD_ST* pc, tefmod_hg2_codec_t* hg2_codec) 8071 { 8072 TX_X4_ENC0r_t TX_X4_ENC0_reg; 8073 8074 READ_TX_X4_ENC0r(pc, &TX_X4_ENC0_reg); 8075 if (TX_X4_ENC0r_HG2_ENABLEf_GET(TX_X4_ENC0_reg)) { 8076 if (TX_X4_ENC0r_HG2_CODECf_GET(TX_X4_ENC0_reg)) { 8077 *hg2_codec = TEFMOD_HG2_CODEC_ON_8BYTE_IPG; 8078 } else { 8079 *hg2_codec = TEFMOD_HG2_CODEC_ON_9BYTE_IPG; 8080 } 8081 } else { 8082 *hg2_codec = TEFMOD_HG2_CODEC_OFF; 8083 8084 } 8085 return PHYMOD_E_NONE; 8086 } 8087 8088 int tefmod_encode_mode_get(PHYMOD_ST* pc, tefmod_encode_mode *mode) 8089 { 8090 SC_X4_RSLVD0r_t reg_resolved; 8091 8092 SC_X4_RSLVD0r_CLR(reg_resolved); 8093 8094 PHYMOD_IF_ERR_RETURN 8095 (READ_SC_X4_RSLVD0r(pc, ®_resolved)); 8096 *mode = SC_X4_RSLVD0r_T_ENC_MODEf_GET(reg_resolved); 8097 8098 return PHYMOD_E_NONE; 8099 } 8100 8101 int tefmod_fec_correctable_counter_get(PHYMOD_ST* pc, uint32_t* count) 8102 { 8103 RX_X4_FEC_CORRBLKSL0r_t countl_0; 8104 RX_X4_FEC_CORRBLKSL1r_t countl_1; 8105 RX_X4_FEC_CORRBLKSL2r_t countl_2; 8106 RX_X4_FEC_CORRBLKSL3r_t countl_3; 8107 RX_X4_FEC_CORRBLKSL4r_t countl_4; 8108 RX_X4_FEC_CORRBLKSH0r_t counth_0; 8109 RX_X4_FEC_CORRBLKSH1r_t counth_1; 8110 RX_X4_FEC_CORRBLKSH2r_t counth_2; 8111 RX_X4_FEC_CORRBLKSH3r_t counth_3; 8112 RX_X4_FEC_CORRBLKSH4r_t counth_4; 8113 uint32_t sum = 0, count_vl = 0; 8114 8115 /* Per lane based counter */ 8116 /* 1 physical lane can map to 5 virtual lane */ 8117 PHYMOD_IF_ERR_RETURN (READ_RX_X4_FEC_CORRBLKSL0r(pc, &countl_0)); 8118 PHYMOD_IF_ERR_RETURN (READ_RX_X4_FEC_CORRBLKSH0r(pc, &counth_0)); 8119 sum = (RX_X4_FEC_CORRBLKSH0r_GET(counth_0) << 16) | (RX_X4_FEC_CORRBLKSL0r_GET(countl_0) & 0xffff); 8120 PHYMOD_IF_ERR_RETURN (READ_RX_X4_FEC_CORRBLKSL1r(pc, &countl_1)); 8121 PHYMOD_IF_ERR_RETURN (READ_RX_X4_FEC_CORRBLKSH1r(pc, &counth_1)); 8122 count_vl = (RX_X4_FEC_CORRBLKSH1r_GET(counth_1) << 16) | (RX_X4_FEC_CORRBLKSL1r_GET(countl_1) & 0xffff); 8123 /* Check overflow */ 8124 /* If sum+count_vl > 0xffffffff, will cause overflow, set sum=0xffffffff */ 8125 if (count_vl > 0xffffffff - sum) { 8126 sum = 0xffffffff; 8127 } else { 8128 sum += count_vl; 8129 } 8130 PHYMOD_IF_ERR_RETURN (READ_RX_X4_FEC_CORRBLKSL2r(pc, &countl_2)); 8131 PHYMOD_IF_ERR_RETURN (READ_RX_X4_FEC_CORRBLKSH2r(pc, &counth_2)); 8132 count_vl = (RX_X4_FEC_CORRBLKSH2r_GET(counth_2) << 16) | (RX_X4_FEC_CORRBLKSL2r_GET(countl_2) & 0xffff); 8133 /* Check overflow */ 8134 if (count_vl > 0xffffffff - sum) { 8135 sum = 0xffffffff; 8136 } else { 8137 sum += count_vl; 8138 } 8139 PHYMOD_IF_ERR_RETURN (READ_RX_X4_FEC_CORRBLKSL3r(pc, &countl_3)); 8140 PHYMOD_IF_ERR_RETURN (READ_RX_X4_FEC_CORRBLKSH3r(pc, &counth_3)); 8141 count_vl = (RX_X4_FEC_CORRBLKSH3r_GET(counth_3) << 16) | (RX_X4_FEC_CORRBLKSL3r_GET(countl_3) & 0xffff); 8142 /* Check overflow */ 8143 if (count_vl > 0xffffffff - sum) { 8144 sum = 0xffffffff; 8145 } else { 8146 sum += count_vl; 8147 } 8148 PHYMOD_IF_ERR_RETURN (READ_RX_X4_FEC_CORRBLKSL4r(pc, &countl_4)); 8149 PHYMOD_IF_ERR_RETURN (READ_RX_X4_FEC_CORRBLKSH4r(pc, &counth_4)); 8150 count_vl = (RX_X4_FEC_CORRBLKSH4r_GET(counth_4) << 16) | (RX_X4_FEC_CORRBLKSL4r_GET(countl_4) & 0xffff); 8151 /* Check overflow */ 8152 if (count_vl > 0xffffffff - sum) { 8153 *count = 0xffffffff; 8154 } else { 8155 *count = sum + count_vl; 8156 } 8157 8158 return PHYMOD_E_NONE; 8159 } 8160 8161 int tefmod_fec_uncorrectable_counter_get(PHYMOD_ST* pc, uint32_t* count) 8162 { 8163 RX_X4_FEC_UNCORRBLKSL0r_t countl_0; 8164 RX_X4_FEC_UNCORRBLKSL1r_t countl_1; 8165 RX_X4_FEC_UNCORRBLKSL2r_t countl_2; 8166 RX_X4_FEC_UNCORRBLKSL3r_t countl_3; 8167 RX_X4_FEC_UNCORRBLKSL4r_t countl_4; 8168 RX_X4_FEC_UNCORRBLKSH0r_t counth_0; 8169 RX_X4_FEC_UNCORRBLKSH1r_t counth_1; 8170 RX_X4_FEC_UNCORRBLKSH2r_t counth_2; 8171 RX_X4_FEC_UNCORRBLKSH3r_t counth_3; 8172 RX_X4_FEC_UNCORRBLKSH4r_t counth_4; 8173 uint32_t sum = 0, count_vl = 0; 8174 8175 /* Per lane based counter */ 8176 /* 1 physical lane can map to 5 virtual lane */ 8177 PHYMOD_IF_ERR_RETURN (READ_RX_X4_FEC_UNCORRBLKSL0r(pc, &countl_0)); 8178 PHYMOD_IF_ERR_RETURN (READ_RX_X4_FEC_UNCORRBLKSH0r(pc, &counth_0)); 8179 sum = (RX_X4_FEC_UNCORRBLKSH0r_GET(counth_0) << 16) | (RX_X4_FEC_UNCORRBLKSL0r_GET(countl_0) & 0xffff); 8180 PHYMOD_IF_ERR_RETURN (READ_RX_X4_FEC_UNCORRBLKSL1r(pc, &countl_1)); 8181 PHYMOD_IF_ERR_RETURN (READ_RX_X4_FEC_UNCORRBLKSH1r(pc, &counth_1)); 8182 count_vl = (RX_X4_FEC_UNCORRBLKSH1r_GET(counth_1) << 16) | (RX_X4_FEC_UNCORRBLKSL1r_GET(countl_1) & 0xffff); 8183 /* Check overflow */ 8184 /* If sum+count_vl > 0xffffffff, will cause overflow, set sum=0xffffffff */ 8185 if (count_vl > 0xffffffff - sum) { 8186 sum = 0xffffffff; 8187 } else { 8188 sum += count_vl; 8189 } 8190 PHYMOD_IF_ERR_RETURN (READ_RX_X4_FEC_UNCORRBLKSL2r(pc, &countl_2)); 8191 PHYMOD_IF_ERR_RETURN (READ_RX_X4_FEC_UNCORRBLKSH2r(pc, &counth_2)); 8192 count_vl = (RX_X4_FEC_UNCORRBLKSH2r_GET(counth_2) << 16) | (RX_X4_FEC_UNCORRBLKSL2r_GET(countl_2) & 0xffff); 8193 /* Check overflow */ 8194 if (count_vl > 0xffffffff - sum) { 8195 sum = 0xffffffff; 8196 } else { 8197 sum += count_vl; 8198 } 8199 PHYMOD_IF_ERR_RETURN (READ_RX_X4_FEC_UNCORRBLKSL3r(pc, &countl_3)); 8200 PHYMOD_IF_ERR_RETURN (READ_RX_X4_FEC_UNCORRBLKSH3r(pc, &counth_3)); 8201 count_vl = (RX_X4_FEC_UNCORRBLKSH3r_GET(counth_3) << 16) | (RX_X4_FEC_UNCORRBLKSL3r_GET(countl_3) & 0xffff); 8202 /* Check overflow */ 8203 if (count_vl > 0xffffffff - sum) { 8204 sum = 0xffffffff; 8205 } else { 8206 sum += count_vl; 8207 } 8208 PHYMOD_IF_ERR_RETURN (READ_RX_X4_FEC_UNCORRBLKSL4r(pc, &countl_4)); 8209 PHYMOD_IF_ERR_RETURN (READ_RX_X4_FEC_UNCORRBLKSH4r(pc, &counth_4)); 8210 count_vl = (RX_X4_FEC_UNCORRBLKSH4r_GET(counth_4) << 16) | (RX_X4_FEC_UNCORRBLKSL4r_GET(countl_4) & 0xffff); 8211 /* Check overflow */ 8212 if (count_vl > 0xffffffff - sum) { 8213 *count = 0xffffffff; 8214 } else { 8215 *count = sum + count_vl; 8216 } 8217 8218 return PHYMOD_E_NONE; 8219 } 8220 8221 int tefmod_fec_cl91_correctable_counter_get(PHYMOD_ST* pc, uint32_t* count) 8222 { 8223 RX_X1_FEC_CORR_CTR0r_t count0; 8224 RX_X1_FEC_CORR_CTR1r_t count1; 8225 MAIN0_SERDESIDr_t serdesid; 8226 uint32_t model; 8227 8228 READ_MAIN0_SERDESIDr(pc, &serdesid); 8229 model = MAIN0_SERDESIDr_MODEL_NUMBERf_GET(serdesid); 8230 8231 /* check if tscf_gen2 version */ 8232 if (model == TSCF_GEN2) { 8233 RX_X4_FEC_CORR_CTR_0_GEN2r_t count0_gen2; 8234 RX_X4_FEC_CORR_CTR_1_GEN2r_t count1_gen2; 8235 8236 /* Per port based counter */ 8237 PHYMOD_IF_ERR_RETURN (READ_RX_X4_FEC_CORR_CTR_0_GEN2r(pc, &count0_gen2)); 8238 PHYMOD_IF_ERR_RETURN (READ_RX_X4_FEC_CORR_CTR_1_GEN2r(pc, &count1_gen2)); 8239 *count = (RX_X4_FEC_CORR_CTR_1_GEN2r_GET(count1_gen2) << 16) 8240 | (RX_X4_FEC_CORR_CTR_0_GEN2r_GET(count0_gen2) & 0xffff); 8241 } else { 8242 /* Per port based counter */ 8243 PHYMOD_IF_ERR_RETURN (READ_RX_X1_FEC_CORR_CTR0r(pc, &count0)); 8244 PHYMOD_IF_ERR_RETURN (READ_RX_X1_FEC_CORR_CTR1r(pc, &count1)); 8245 *count = (RX_X1_FEC_CORR_CTR1r_GET(count1) << 16) | (RX_X1_FEC_CORR_CTR0r_GET(count0) & 0xffff); 8246 } 8247 8248 return PHYMOD_E_NONE; 8249 } 8250 8251 int tefmod_fec_cl91_uncorrectable_counter_get(PHYMOD_ST* pc, uint32_t* count) 8252 { 8253 RX_X1_FEC_UNCORR_CTR0r_t count0; 8254 RX_X1_FEC_UNCORR_CTR1r_t count1; 8255 MAIN0_SERDESIDr_t serdesid; 8256 uint32_t model; 8257 8258 READ_MAIN0_SERDESIDr(pc, &serdesid); 8259 model = MAIN0_SERDESIDr_MODEL_NUMBERf_GET(serdesid); 8260 8261 /* check if tscf_gen2 version */ 8262 if (model == TSCF_GEN2) { 8263 RX_X4_FEC_UNCORR_CTR_0_GEN2r_t count0_gen2; 8264 RX_X4_FEC_UNCORR_CTR_1_GEN2r_t count1_gen2; 8265 8266 /* Per port based counter */ 8267 PHYMOD_IF_ERR_RETURN (READ_RX_X4_FEC_UNCORR_CTR_0_GEN2r(pc, &count0_gen2)); 8268 PHYMOD_IF_ERR_RETURN (READ_RX_X4_FEC_UNCORR_CTR_1_GEN2r(pc, &count1_gen2)); 8269 *count = (RX_X4_FEC_UNCORR_CTR_1_GEN2r_GET(count1_gen2) << 16) 8270 | (RX_X4_FEC_UNCORR_CTR_0_GEN2r_GET(count0_gen2) & 0xffff); 8271 } else { 8272 /* Per port based counter */ 8273 PHYMOD_IF_ERR_RETURN (READ_RX_X1_FEC_UNCORR_CTR0r(pc, &count0)); 8274 PHYMOD_IF_ERR_RETURN (READ_RX_X1_FEC_UNCORR_CTR1r(pc, &count1)); 8275 *count = (RX_X1_FEC_UNCORR_CTR1r_GET(count1) << 16) | (RX_X1_FEC_UNCORR_CTR0r_GET(count0) & 0xffff); 8276 } 8277 8278 return PHYMOD_E_NONE; 8279 } 8280 8281 /* The number of cl82 BIP error */ 8282 int tefmod_bip_error_counter_get(PHYMOD_ST* pc, uint32_t* count) 8283 { 8284 RX_X4_BIPCNT0r_t count0; 8285 RX_X4_BIPCNT1r_t count1; 8286 RX_X4_BIPCNT2r_t count2; 8287 8288 PHYMOD_IF_ERR_RETURN (READ_RX_X4_BIPCNT0r(pc, &count0)); 8289 PHYMOD_IF_ERR_RETURN (READ_RX_X4_BIPCNT1r(pc, &count1)); 8290 PHYMOD_IF_ERR_RETURN (READ_RX_X4_BIPCNT2r(pc, &count2)); 8291 *count = RX_X4_BIPCNT0r_BIP_ERROR_COUNT_0f_GET(count0) + RX_X4_BIPCNT0r_BIP_ERROR_COUNT_1f_GET(count0); 8292 *count += RX_X4_BIPCNT1r_BIP_ERROR_COUNT_2f_GET(count1) + RX_X4_BIPCNT1r_BIP_ERROR_COUNT_3f_GET(count1); 8293 *count += RX_X4_BIPCNT2r_BIP_ERROR_COUNT_4f_GET(count2); 8294 8295 return PHYMOD_E_NONE; 8296 } 8297 8298 /* The number of times BER_BAD_SH state is entered for cl49. */ 8299 int tefmod_cl49_ber_counter_get(PHYMOD_ST* pc, uint32_t* count) 8300 { 8301 RX_X4_DEC_STS3r_t dec_sts; 8302 8303 PHYMOD_IF_ERR_RETURN (READ_RX_X4_DEC_STS3r(pc, &dec_sts)); 8304 *count = RX_X4_DEC_STS3r_CL49_BER_COUNTf_GET(dec_sts); 8305 8306 return PHYMOD_E_NONE; 8307 } 8308 8309 /* The number of times BER_BAD_SH state is entered for cl82. */ 8310 int tefmod_cl82_ber_counter_get(PHYMOD_ST* pc, uint32_t* count) 8311 { 8312 CL82_BER_HOr_t count_ho; 8313 CL82_BER_LOr_t count_lo; 8314 8315 PHYMOD_IF_ERR_RETURN (READ_CL82_BER_HOr(pc, &count_ho)); 8316 PHYMOD_IF_ERR_RETURN (READ_CL82_BER_LOr(pc, &count_lo)); 8317 *count = (CL82_BER_HOr_BER_HOf_GET(count_ho) << 8) | (CL82_BER_LOr_BER_LOf_GET(count_lo)); 8318 8319 return PHYMOD_E_NONE; 8320 } 8321 8322 int tefmod_setup_for_sw_an(PHYMOD_ST* pc, int num_lanes) 8323 { 8324 AN_X4_LD_CTL_GEN2r_t AN_X4_LD_CTLr_reg; 8325 AN_X4_CL73_CFG_GEN2r_t AN_X4_ABILITIES_CL73_CFGr_reg; 8326 AN_X4_WAIT_ACK_COMPLETE_GEN2r_t AN_X4_WAIT_ACK_COMPLETE_reg; 8327 AN_X1_CL73_ERR_GEN2r_t AN_X1_CL73_ERR_reg; 8328 MAIN0_SETUP_GEN2r_t MAIN0_SETUP_reg; 8329 uint32_t plldiv_r_val; 8330 int num_lane_adv; 8331 8332 8333 /* Set cl73 err timer to 0 */ 8334 AN_X1_CL73_ERR_GEN2r_CLR(AN_X1_CL73_ERR_reg); 8335 AN_X1_CL73_ERR_GEN2r_SET(AN_X1_CL73_ERR_reg, 0); 8336 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_CL73_ERR_GEN2r(pc, AN_X1_CL73_ERR_reg)); 8337 8338 /* disable tscf */ 8339 tefmod_disable_set(pc); 8340 8341 /* set the cl73 vc0 mode 1 */ 8342 PHYMOD_IF_ERR_RETURN(tefmod_get_plldiv(pc, &plldiv_r_val)); 8343 MAIN0_SETUP_GEN2r_CLR(MAIN0_SETUP_reg); 8344 PHYMOD_IF_ERR_RETURN(READ_MAIN0_SETUP_GEN2r(pc, &MAIN0_SETUP_reg)); 8345 8346 if (plldiv_r_val<=4) { /* pll_div <= 132; for 156MHz only */ 8347 /* for 25G VCO set the cl73 VCO bit to1 otherwise 0*/ 8348 MAIN0_SETUP_GEN2r_CL73_VCOf_SET(MAIN0_SETUP_reg, 0); 8349 } else { 8350 MAIN0_SETUP_GEN2r_CL73_VCOf_SET(MAIN0_SETUP_reg, 1); 8351 } 8352 PHYMOD_IF_ERR_RETURN(WRITE_MAIN0_SETUP_GEN2r(pc, MAIN0_SETUP_reg)); 8353 8354 /* clear the SW AN and cl73 an enable to 0 */ 8355 AN_X4_LD_CTL_GEN2r_CLR(AN_X4_LD_CTLr_reg); 8356 AN_X4_LD_CTL_GEN2r_AN_TYPE_SWf_SET(AN_X4_LD_CTLr_reg, 0); 8357 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_LD_CTL_GEN2r(pc, AN_X4_LD_CTLr_reg)); 8358 8359 8360 switch(num_lanes) { 8361 case 1: 8362 num_lane_adv = 0; 8363 break; 8364 case 2: 8365 num_lane_adv = 1; 8366 break; 8367 case 4: 8368 num_lane_adv = 2; 8369 break; 8370 default: 8371 return PHYMOD_E_PARAM; 8372 } 8373 8374 AN_X4_CL73_CFG_GEN2r_CLR(AN_X4_ABILITIES_CL73_CFGr_reg); 8375 AN_X4_CL73_CFG_GEN2r_CL73_BAM_ENABLEf_SET(AN_X4_ABILITIES_CL73_CFGr_reg, 0); 8376 AN_X4_CL73_CFG_GEN2r_CL73_ENABLEf_SET(AN_X4_ABILITIES_CL73_CFGr_reg, 0); 8377 AN_X4_CL73_CFG_GEN2r_NUM_ADVERTISED_LANESf_SET(AN_X4_ABILITIES_CL73_CFGr_reg, num_lane_adv); 8378 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_CL73_CFG_GEN2r(pc, AN_X4_ABILITIES_CL73_CFGr_reg)); 8379 8380 /* set the wait for ack FSM to 1 */ 8381 AN_X4_WAIT_ACK_COMPLETE_GEN2r_CLR(AN_X4_WAIT_ACK_COMPLETE_reg); 8382 PHYMOD_IF_ERR_RETURN(READ_AN_X4_WAIT_ACK_COMPLETE_GEN2r(pc, &AN_X4_WAIT_ACK_COMPLETE_reg)); 8383 AN_X4_WAIT_ACK_COMPLETE_GEN2r_WAIT_FOR_ACK_ENf_SET(AN_X4_WAIT_ACK_COMPLETE_reg, 1); 8384 PHYMOD_IF_ERR_RETURN(WRITE_AN_X4_WAIT_ACK_COMPLETE_GEN2r(pc, AN_X4_WAIT_ACK_COMPLETE_reg)); 8385 8386 return PHYMOD_E_NONE; 8387 } 8388 8389 int tefmod_sw_an_control(PHYMOD_ST* pc, int enable) 8390 { 8391 AN_X4_LD_CTL_GEN2r_t AN_X4_LD_CTLr_reg; 8392 AN_X4_CL73_CFG_GEN2r_t AN_X4_ABILITIES_CL73_CFGr_reg; 8393 8394 8395 /* Enabling SW AN if sw_an is set */ 8396 AN_X4_LD_CTL_GEN2r_CLR(AN_X4_LD_CTLr_reg); 8397 AN_X4_LD_CTL_GEN2r_AN_TYPE_SWf_SET(AN_X4_LD_CTLr_reg, enable); 8398 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_LD_CTL_GEN2r(pc, AN_X4_LD_CTLr_reg)); 8399 8400 AN_X4_CL73_CFG_GEN2r_CLR(AN_X4_ABILITIES_CL73_CFGr_reg); 8401 AN_X4_CL73_CFG_GEN2r_CL73_ENABLEf_SET(AN_X4_ABILITIES_CL73_CFGr_reg, enable); 8402 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_CL73_CFG_GEN2r(pc, AN_X4_ABILITIES_CL73_CFGr_reg)); 8403 8404 return PHYMOD_E_NONE; 8405 } 8406 8407 /*! 8408 @brief Programs the SW AN local device pages 8409 @param pc handle to current TSCF context (#PHYMOD_ST) 8410 @returns PHYMOD_E_NONE if no errors. PHYMOD_EERROR else. 8411 8412 @details 8413 This function programs SW AN local device pages. 8414 per_lane_control bits [17:16] indicate 8415 the page its trying to write, per_lane_control bits [15:0] 8416 has the actual page contents 8417 */ 8418 int tefmod_sw_an_ld_page_load(PHYMOD_ST* pc, phymod_an_page_t *pages, int is_base_page) 8419 { 8420 AN_X4_LD_PAGE_0_GEN2r_t AN_X4_LD_PAGE0r_reg; 8421 AN_X4_LD_PAGE_1_GEN2r_t AN_X4_LD_PAGE1r_reg; 8422 AN_X4_LD_PAGE_2_GEN2r_t AN_X4_LD_PAGE2r_reg; 8423 8424 AN_X4_SW_AN_BASE_PAGE_0_GEN2r_t AN_X4_SW_AN_BASE_PAGE0r_reg; 8425 AN_X4_SW_AN_BASE_PAGE_1_GEN2r_t AN_X4_SW_AN_BASE_PAGE1r_reg; 8426 AN_X4_SW_AN_BASE_PAGE_2_GEN2r_t AN_X4_SW_AN_BASE_PAGE2r_reg; 8427 8428 8429 if (is_base_page) { 8430 8431 AN_X4_SW_AN_BASE_PAGE_2_GEN2r_CLR(AN_X4_SW_AN_BASE_PAGE2r_reg); 8432 AN_X4_SW_AN_BASE_PAGE_2_GEN2r_SET(AN_X4_SW_AN_BASE_PAGE2r_reg, pages->page_2); 8433 PHYMOD_IF_ERR_RETURN(WRITE_AN_X4_SW_AN_BASE_PAGE_2_GEN2r(pc, AN_X4_SW_AN_BASE_PAGE2r_reg)); 8434 8435 AN_X4_SW_AN_BASE_PAGE_1_GEN2r_CLR(AN_X4_SW_AN_BASE_PAGE1r_reg); 8436 AN_X4_SW_AN_BASE_PAGE_1_GEN2r_SET(AN_X4_SW_AN_BASE_PAGE1r_reg, pages->page_1); 8437 PHYMOD_IF_ERR_RETURN(WRITE_AN_X4_SW_AN_BASE_PAGE_1_GEN2r(pc, AN_X4_SW_AN_BASE_PAGE1r_reg)); 8438 8439 AN_X4_SW_AN_BASE_PAGE_0_GEN2r_CLR(AN_X4_SW_AN_BASE_PAGE0r_reg); 8440 AN_X4_SW_AN_BASE_PAGE_0_GEN2r_SET(AN_X4_SW_AN_BASE_PAGE0r_reg, pages->page_0); 8441 PHYMOD_IF_ERR_RETURN(WRITE_AN_X4_SW_AN_BASE_PAGE_0_GEN2r(pc, AN_X4_SW_AN_BASE_PAGE0r_reg)); 8442 8443 } else { 8444 8445 AN_X4_LD_PAGE_2_GEN2r_CLR(AN_X4_LD_PAGE2r_reg); 8446 AN_X4_LD_PAGE_2_GEN2r_LD_PAGE_2f_SET(AN_X4_LD_PAGE2r_reg, pages->page_2); 8447 PHYMOD_IF_ERR_RETURN(WRITE_AN_X4_LD_PAGE_2_GEN2r(pc, AN_X4_LD_PAGE2r_reg)); 8448 8449 AN_X4_LD_PAGE_1_GEN2r_CLR(AN_X4_LD_PAGE1r_reg); 8450 AN_X4_LD_PAGE_1_GEN2r_LD_PAGE_1f_SET(AN_X4_LD_PAGE1r_reg, pages->page_1); 8451 PHYMOD_IF_ERR_RETURN(WRITE_AN_X4_LD_PAGE_1_GEN2r(pc, AN_X4_LD_PAGE1r_reg)); 8452 8453 AN_X4_LD_PAGE_0_GEN2r_CLR(AN_X4_LD_PAGE0r_reg); 8454 AN_X4_LD_PAGE_0_GEN2r_LD_PAGE_0f_SET(AN_X4_LD_PAGE0r_reg, pages->page_0); 8455 PHYMOD_IF_ERR_RETURN(WRITE_AN_X4_LD_PAGE_0_GEN2r(pc, AN_X4_LD_PAGE0r_reg)); 8456 8457 } 8458 return PHYMOD_E_NONE; 8459 } 8460 8461 /*! 8462 @brief Reads the SW AN link partner pages 8463 @param pc handle to current TSCF context (#PHYMOD_ST) 8464 @returns PHYMOD_E_NONE if no errors. PHYMOD_EERROR else. 8465 8466 @details 8467 This function reads SW AN link partner pages. The HW 8468 requires you to read page0 register last. 8469 8470 */ 8471 int tefmod_sw_an_lp_page_read(PHYMOD_ST* pc, phymod_an_page_t *pages) 8472 { 8473 AN_X4_LP_PAGE_0_GEN2r_t AN_X4_LP_PAGE0r_reg; 8474 AN_X4_LP_PAGE_1_GEN2r_t AN_X4_LP_PAGE1r_reg; 8475 AN_X4_LP_PAGE_2_GEN2r_t AN_X4_LP_PAGE2r_reg; 8476 8477 AN_X4_LP_PAGE_2_GEN2r_CLR(AN_X4_LP_PAGE2r_reg); 8478 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LP_PAGE_2_GEN2r(pc, &AN_X4_LP_PAGE2r_reg)); 8479 pages->page_2 = AN_X4_LP_PAGE_2_GEN2r_LP_PAGE_2f_GET(AN_X4_LP_PAGE2r_reg); 8480 8481 AN_X4_LP_PAGE_1_GEN2r_CLR(AN_X4_LP_PAGE1r_reg); 8482 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LP_PAGE_1_GEN2r(pc, &AN_X4_LP_PAGE1r_reg)); 8483 pages->page_1 = AN_X4_LP_PAGE_1_GEN2r_LP_PAGE_1f_GET(AN_X4_LP_PAGE1r_reg); 8484 8485 AN_X4_LP_PAGE_0_GEN2r_CLR(AN_X4_LP_PAGE0r_reg); 8486 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LP_PAGE_0_GEN2r(pc, &AN_X4_LP_PAGE0r_reg)); 8487 pages->page_0 = AN_X4_LP_PAGE_0_GEN2r_LP_PAGE_0f_GET(AN_X4_LP_PAGE0r_reg); 8488 8489 return PHYMOD_E_NONE; 8490 8491 } 8492 8493 8494 int tefmod_sw_an_ctl_sts_get(PHYMOD_ST* pc, phymod_sw_an_ctrl_status_t *an_ctrl_status) 8495 { 8496 AN_X4_SW_CTL_STS_GEN2r_t AN_X4_SW_CTL_STSr_reg; 8497 8498 AN_X4_SW_CTL_STS_GEN2r_CLR(AN_X4_SW_CTL_STSr_reg); 8499 PHYMOD_IF_ERR_RETURN (READ_AN_X4_SW_CTL_STS_GEN2r(pc, &AN_X4_SW_CTL_STSr_reg)); 8500 8501 an_ctrl_status->seq_restart = AN_X4_SW_CTL_STS_GEN2r_LD_SEQ_RESTARTf_GET(AN_X4_SW_CTL_STSr_reg); 8502 an_ctrl_status->lp_page_rdy = AN_X4_SW_CTL_STS_GEN2r_LP_PAGE_RDYf_GET(AN_X4_SW_CTL_STSr_reg); 8503 an_ctrl_status->page_req = AN_X4_SW_CTL_STS_GEN2r_LD_PAGE_REQf_GET(AN_X4_SW_CTL_STSr_reg); 8504 an_ctrl_status->an_completed = AN_X4_SW_CTL_STS_GEN2r_AN_COMPLETEDf_GET(AN_X4_SW_CTL_STSr_reg); 8505 8506 8507 if (!an_ctrl_status->an_completed) { 8508 PHYMOD_IF_ERR_RETURN 8509 (tefmod_pxgng_status_an_good_chk_get(pc, &an_ctrl_status->an_completed)); 8510 } 8511 8512 return PHYMOD_E_NONE; 8513 } 8514 8515 int tefmod_sw_an_set_ack(PHYMOD_ST* pc) 8516 { 8517 AN_X4_WAIT_ACK_COMPLETE_GEN2r_t AN_X4_WAIT_ACK_COMPLETEr_reg; 8518 8519 AN_X4_WAIT_ACK_COMPLETE_GEN2r_CLR(AN_X4_WAIT_ACK_COMPLETEr_reg); 8520 AN_X4_WAIT_ACK_COMPLETE_GEN2r_SEND_ACKf_SET(AN_X4_WAIT_ACK_COMPLETEr_reg, 1); 8521 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_WAIT_ACK_COMPLETE_GEN2r(pc, AN_X4_WAIT_ACK_COMPLETEr_reg)); 8522 8523 return PHYMOD_E_NONE; 8524 } 8525 8526 int tefmod_set_speed_id(PHYMOD_ST *pc, int speed_id) 8527 { 8528 SC_X4_CTLr_t xgxs_x4_ctrl; 8529 phymod_access_t pa_copy; 8530 int start_lane = 0, num_lane = 0; 8531 8532 8533 /* need to figure out what's the starting lane */ 8534 PHYMOD_MEMCPY(&pa_copy, pc, sizeof(pa_copy)); 8535 PHYMOD_IF_ERR_RETURN 8536 (phymod_util_lane_config_get(pc, &start_lane, &num_lane)); 8537 pa_copy.lane_mask = 0x1 << start_lane; 8538 8539 /* write the speed_id into the speed_change register */ 8540 SC_X4_CTLr_CLR(xgxs_x4_ctrl); 8541 SC_X4_CTLr_SPEEDf_SET(xgxs_x4_ctrl, speed_id); 8542 MODIFY_SC_X4_CTLr(pc, xgxs_x4_ctrl); 8543 8544 return PHYMOD_E_NONE; 8545 } 8546 8547 8548 8549 int tefmod_pxgng_status_an_ack_complete_get(PHYMOD_ST *pc, int *ack_complte) 8550 { 8551 8552 AN_X4_PXNG_STS_GEN2r_t an_pxng_status_reg; 8553 8554 AN_X4_PXNG_STS_GEN2r_CLR(an_pxng_status_reg); 8555 PHYMOD_IF_ERR_RETURN 8556 (READ_AN_X4_PXNG_STS_GEN2r(pc, &an_pxng_status_reg)); 8557 PHYMOD_IF_ERR_RETURN 8558 (READ_AN_X4_PXNG_STS_GEN2r(pc, &an_pxng_status_reg)); 8559 8560 *ack_complte = AN_X4_PXNG_STS_GEN2r_COMPLETE_ACKf_GET(an_pxng_status_reg); 8561 8562 return PHYMOD_E_NONE; 8563 } 8564 8565 int tefmod_pxgng_status_an_good_chk_get(PHYMOD_ST *pc, uint8_t *an_good_chk) 8566 { 8567 8568 AN_X4_PXNG_STS_GEN2r_t an_pxng_status_reg; 8569 8570 AN_X4_PXNG_STS_GEN2r_CLR(an_pxng_status_reg); 8571 PHYMOD_IF_ERR_RETURN 8572 (READ_AN_X4_PXNG_STS_GEN2r(pc, &an_pxng_status_reg)); 8573 PHYMOD_IF_ERR_RETURN 8574 (READ_AN_X4_PXNG_STS_GEN2r(pc, &an_pxng_status_reg)); 8575 8576 *an_good_chk = AN_X4_PXNG_STS_GEN2r_AN_GOOD_CHECKf_GET(an_pxng_status_reg); 8577 8578 return PHYMOD_E_NONE; 8579 8580 } 8581 8582 8583 int tefmod_sw_an_fec_override(PHYMOD_ST *pc, tefmod_fec_type_t fec_type, int enable) 8584 { 8585 SC_X4_SC_X4_OVRR_GEN2r_t SC_X4_SC_X4_OVRR_reg; 8586 int fec_value = 0; 8587 8588 if (enable) { 8589 if (fec_type == TEFMOD_CL91) { 8590 fec_value = 0x3; 8591 } else if (fec_type == TEFMOD_CL74) { 8592 fec_value = 0x2; 8593 } else { 8594 /* NO FEC */ 8595 fec_value = 0x1; 8596 } 8597 } else { 8598 fec_value = 0x0; 8599 } 8600 8601 SC_X4_SC_X4_OVRR_GEN2r_CLR(SC_X4_SC_X4_OVRR_reg); 8602 SC_X4_SC_X4_OVRR_GEN2r_AN_FEC_SEL_OVERRIDEf_SET(SC_X4_SC_X4_OVRR_reg, fec_value); 8603 PHYMOD_IF_ERR_RETURN 8604 (MODIFY_SC_X4_SC_X4_OVRR_GEN2r(pc, SC_X4_SC_X4_OVRR_reg)); 8605 8606 return PHYMOD_E_NONE; 8607 } 8608 8609 8610 int tefmod_sw_an_advert_set(PHYMOD_ST* pc, tefmod_an_adv_ability_t *cl73_adv, phymod_sw_an_ctxt_t *an_ctxt) 8611 { 8612 uint8_t pause_cap = 0; 8613 /* Initialize the base page */ 8614 an_ctxt->tx_pages.base_page.page_0 = 0; 8615 an_ctxt->tx_pages.base_page.page_1 = 0; 8616 an_ctxt->tx_pages.base_page.page_2 = 0; 8617 8618 8619 an_ctxt->no_pages_to_be_txed = 1; 8620 8621 an_ctxt->tx_pages.base_page.page_0 |= ((AN_BASE0_PAGE_IEEE_SEL_MASK & IEEE_SEL_802P3) << 8622 AN_BASE0_PAGE_IEEE_SEL_OFFSET); 8623 8624 an_ctxt->tx_pages.base_page.page_0 &= ~(AN_BASE0_PAGE_CL73_NOUNCE_MASK << 8625 AN_BASE0_PAGE_CL73_NOUNCE_OFFSET); /* HW will set this bit */ 8626 8627 if (cl73_adv->an_pause == TEFMOD_NO_PAUSE) { 8628 pause_cap = 0; 8629 } else if (cl73_adv->an_pause == TEFMOD_SYMM_PAUSE) { 8630 pause_cap = 1; 8631 } else if (cl73_adv->an_pause == TEFMOD_ASYM_PAUSE) { 8632 pause_cap = 2; 8633 } else if (cl73_adv->an_pause == TEFMOD_ASYM_SYMM_PAUSE) { 8634 pause_cap = 3; 8635 } else { 8636 /* default to no pause ability */ 8637 pause_cap = 0; 8638 } 8639 an_ctxt->tx_pages.base_page.page_0 |= ((AN_BASE0_PAGE_CAP_MASK & pause_cap) << 8640 AN_BASE0_PAGE_CAP_OFFSET); 8641 8642 an_ctxt->tx_pages.base_page.page_0 &= ~(AN_BASE0_PAGE_REMOTE_FAULT_MASK << 8643 AN_BASE0_PAGE_REMOTE_FAULT_OFFSET); /* Need more clarity */ 8644 8645 an_ctxt->tx_pages.base_page.page_0 &= ~(AN_BASE0_PAGE_ACK_MASK << 8646 AN_BASE0_PAGE_ACK_OFFSET); /* Set by HW */ 8647 8648 /* set tech Next page to 0*/ 8649 an_ctxt->tx_pages.base_page.page_0 &= ~(AN_BASE0_PAGE_NP_MASK << 8650 AN_BASE0_PAGE_NP_OFFSET); 8651 PHYMOD_SRAND(PHYMOD_TIME_USECS()); 8652 /* need to generate a 5 bit random number for Tx nounce for now set to 1 */ 8653 an_ctxt->tx_pages.base_page.page_1 |= ((AN_BASE1_PAGE_TX_NOUNCE_MASK & (PHYMOD_RAND())) << 8654 AN_BASE1_PAGE_TX_NOUNCE_OFFSET); 8655 8656 if (an_ctxt->an_mode == phymod_AN_MODE_MSA) { 8657 cl73_adv->an_base_speed = 0; 8658 } 8659 8660 if (cl73_adv->an_base_speed) { 8661 /* populate the IEE base ability */ 8662 if (((cl73_adv->an_base_speed >> TEFMOD_CL73_25GBASE_KR1 ) & 1) || 8663 ((cl73_adv->an_base_speed >> TEFMOD_CL73_25GBASE_CR1 ) & 1)) { 8664 an_ctxt->tx_pages.base_page.page_1 |= (AN_BASE_TECH_ABILITY_25GKR_MASK << 8665 AN_BASE_TECH_ABILITY_25GKR_OFFSET); 8666 } 8667 if (((cl73_adv->an_base_speed >> TEFMOD_CL73_25GBASE_KRS1 ) & 1) || 8668 ((cl73_adv->an_base_speed >> TEFMOD_CL73_25GBASE_CRS1 ) & 1)) { 8669 an_ctxt->tx_pages.base_page.page_1 |= (AN_BASE_TECH_ABILITY_25GKRS_MASK << 8670 AN_BASE_TECH_ABILITY_25GKRS_OFFSET); 8671 } 8672 8673 /* Set cl91/74 supported to 1 */ 8674 an_ctxt->tx_pages.base_page.page_2 |= (AN_BASE_CL74_ABILITY_SUP_MASK << 8675 AN_BASE_CL74_ABILITY_SUP_OFFSET); 8676 8677 if (cl73_adv->an_fec == TEFMOD_FEC_SUPRTD_NOT_REQSTD) { 8678 an_ctxt->tx_pages.base_page.page_2 &= ~(AN_BASE_CL74_ABILITY_REQ_MASK << 8679 AN_BASE_CL74_ABILITY_REQ_OFFSET); 8680 an_ctxt->tx_pages.base_page.page_2 &= ~(AN_BASE_CL91_ABILITY_REQ_MASK << 8681 AN_BASE_CL91_ABILITY_REQ_OFFSET); 8682 an_ctxt->tx_pages.base_page.page_2 &= ~(AN_BASE_CL74_25GKRS_REQ_MASK << 8683 AN_BASE_CL74_25GKRS_REQ_OFFSET); 8684 } else { 8685 if (cl73_adv->an_fec & TEFMOD_FEC_CL74_SUPRTD_REQSTD) { 8686 an_ctxt->tx_pages.base_page.page_2 |= (AN_BASE_CL74_ABILITY_REQ_MASK << 8687 AN_BASE_CL74_ABILITY_REQ_OFFSET); 8688 an_ctxt->tx_pages.base_page.page_2 |= (AN_BASE_CL74_25GKRS_REQ_MASK << 8689 AN_BASE_CL74_25GKRS_REQ_OFFSET); 8690 } 8691 if (cl73_adv->an_fec & TEFMOD_FEC_CL91_SUPRTD_REQSTD) { 8692 an_ctxt->tx_pages.base_page.page_2 |= (AN_BASE_CL91_ABILITY_REQ_MASK << 8693 AN_BASE_CL91_ABILITY_REQ_OFFSET); 8694 } 8695 } 8696 } 8697 8698 8699 8700 if (cl73_adv->an_bam_speed || cl73_adv->an_bam_speed1) { 8701 8702 /* If BAM speed is enabled set the NP bit in base page to 1*/ 8703 an_ctxt->tx_pages.base_page.page_0 |= (AN_BASE0_PAGE_NP_MASK << AN_BASE0_PAGE_NP_OFFSET); 8704 8705 an_ctxt->tx_pages.msg_page.page_0 = 0; 8706 an_ctxt->tx_pages.msg_page.page_1 = 0; 8707 an_ctxt->tx_pages.msg_page.page_2 = 0; 8708 8709 /* populate the Message page with Consortium information */ 8710 8711 /* Populate page0 with 8712 * 1. Msg code 8713 * 2. Toggle bit ==> set to 0 (will be handled by HW) 8714 * 3. ACK2 ==> Set to 0 (will be handled buy HW) 8715 * 4. set MP bit to 1 8716 * 5. Set NP bit to 1 8717 */ 8718 an_ctxt->tx_pages.msg_page.page_0 |= ((AN_MSG_PAGE0_MSG_CODE_MASK & MSA_MSG_CODE) << AN_MSG_PAGE0_MSG_CODE_OFFSET); 8719 an_ctxt->tx_pages.msg_page.page_0 |= (AN_MSG_PAGE0_MSG_PAGE_MASK << AN_MSG_PAGE0_MSG_PAGE_OFFSET); 8720 an_ctxt->tx_pages.msg_page.page_0 |= (AN_MSG_PAGE0_NP_MASK << AN_MSG_PAGE0_NP_OFFSET); 8721 8722 /* populate msg page 1 & 2 with consortium information 8723 * OUI 13:23 8724 * OUI 2:12 8725 */ 8726 an_ctxt->tx_pages.msg_page.page_1 |= ((AN_MSG_PAGE1_OUI_13to23_MASK & MSA_OUI_13to23) << 8727 AN_MSG_PAGE1_OUI_13to23_OFFSET); 8728 an_ctxt->tx_pages.msg_page.page_2 |= ((AN_MSG_PAGE2_OUI_2to12_MASK & MSA_OUT_2to12) << 8729 AN_MSG_PAGE2_OUI_2to12_OFFSET); 8730 8731 an_ctxt->tx_pages.ufmt_page.page_0 = 0; 8732 an_ctxt->tx_pages.ufmt_page.page_1 = 0; 8733 an_ctxt->tx_pages.ufmt_page.page_2 = 0; 8734 8735 /* Populate UFMT page */ 8736 8737 an_ctxt->tx_pages.ufmt_page.page_0 |= ((AN_UF_PAGE0_EXT_TECH_ABILITY_MASK & EXT_TECH_ABILITY_CODE) << 8738 AN_UF_PAGE0_EXT_TECH_ABILITY_OFFSET); 8739 an_ctxt->tx_pages.ufmt_page.page_0 |= ((AN_UF_PAGE0_OUI_MASK & MSA_OUI_0to1) << 8740 AN_UF_PAGE0_OUI_OFFSET); 8741 8742 if ((cl73_adv->an_bam_speed1 >> TEFMOD_CL73_BAM_25GBASE_KR1) & 0x1) { 8743 an_ctxt->tx_pages.ufmt_page.page_1 |= (AN_UF_PAGE1_25G_KR1_ABILITY_MASK << 8744 AN_UF_PAGE1_25G_KR1_ABILITY_OFFSET); 8745 } 8746 if ((cl73_adv->an_bam_speed1 >> TEFMOD_CL73_BAM_25GBASE_CR1) & 0x1) { 8747 an_ctxt->tx_pages.ufmt_page.page_1 |= (AN_UF_PAGE1_25G_CR1_ABILITY_MASK << 8748 AN_UF_PAGE1_25G_CR1_ABILITY_OFFSET); 8749 } 8750 if ((cl73_adv->an_bam_speed >> TEFMOD_CL73_BAM_50GBASE_KR2) & 0x1) { 8751 an_ctxt->tx_pages.ufmt_page.page_1 |= (AN_UF_PAGE1_50G_KR2_ABILITY_MASK << 8752 AN_UF_PAGE1_50G_KR2_ABILITY_OFFSET); 8753 } 8754 if ((cl73_adv->an_bam_speed >> TEFMOD_CL73_BAM_50GBASE_CR2) & 0x1) { 8755 an_ctxt->tx_pages.ufmt_page.page_1 |= (AN_UF_PAGE1_50G_CR2_ABILITY_MASK << 8756 AN_UF_PAGE1_50G_CR2_ABILITY_OFFSET); 8757 } 8758 8759 /* Update FEC Information */ 8760 an_ctxt->tx_pages.ufmt_page.page_2 |= (AN_UF_PAGE2_CL91_SUPPORT_MASK << 8761 AN_UF_PAGE2_CL91_SUPPORT_OFFSET); 8762 an_ctxt->tx_pages.ufmt_page.page_2 |= (AN_UF_PAGE2_CL74_SUPPORT_MASK << 8763 AN_UF_PAGE2_CL74_SUPPORT_OFFSET); 8764 8765 if (cl73_adv->an_fec & TEFMOD_FEC_CL74_SUPRTD_REQSTD) { 8766 an_ctxt->tx_pages.ufmt_page.page_2 |= (AN_UF_PAGE2_CL74_REQ_MASK << 8767 AN_UF_PAGE2_CL74_REQ_OFFSET); 8768 } 8769 if (cl73_adv->an_fec & TEFMOD_FEC_CL91_SUPRTD_REQSTD) { 8770 an_ctxt->tx_pages.ufmt_page.page_2 |= (AN_UF_PAGE2_CL91_REQ_MASK << 8771 AN_UF_PAGE2_CL91_REQ_OFFSET); 8772 } 8773 } 8774 8775 /* Populate the null page */ 8776 an_ctxt->tx_pages.null_page.page_2 = 0; 8777 an_ctxt->tx_pages.null_page.page_1 = 0; 8778 an_ctxt->tx_pages.null_page.page_0 = 1; 8779 8780 return PHYMOD_E_NONE; 8781 8782 } 8783 8784 int 8785 tefmod_serdes_model_get(PHYMOD_ST *pc, uint32_t *model) 8786 { 8787 MAIN0_SERDESIDr_t serdesid; 8788 8789 MAIN0_SERDESIDr_CLR(serdesid); 8790 PHYMOD_IF_ERR_RETURN 8791 (READ_MAIN0_SERDESIDr(pc, &serdesid)); 8792 *model = MAIN0_SERDESIDr_MODEL_NUMBERf_GET(serdesid); 8793 8794 return PHYMOD_E_NONE; 8795 } 8796 8797 int tefmod_25g_rsfec_am_init(PHYMOD_ST *pc) 8798 { 8799 SC_X4_IEEE_25G_CTL_GEN2r_t ieee_25G_am_reg; 8800 RX_X4_IEEE_25G_PARLLEL_DET_CTR_GEN2r_t ieee_25g_parallel_det_reg; 8801 SC_X4_MSA_25G_50G_CTL_GEN2r_t msa_25g_50g_am_reg; 8802 8803 SC_X4_IEEE_25G_CTL_GEN2r_CLR(ieee_25G_am_reg); 8804 RX_X4_IEEE_25G_PARLLEL_DET_CTR_GEN2r_CLR(ieee_25g_parallel_det_reg); 8805 SC_X4_MSA_25G_50G_CTL_GEN2r_CLR(msa_25g_50g_am_reg); 8806 8807 /* Program AM0 value to use 100G AM AM123 should use 40G AM 8808 * which is a default 8809 */ 8810 PHYMOD_IF_ERR_RETURN( 8811 READ_SC_X4_IEEE_25G_CTL_GEN2r(pc, &ieee_25G_am_reg)); 8812 SC_X4_IEEE_25G_CTL_GEN2r_IEEE_25G_AM0_FORMATf_SET(ieee_25G_am_reg, 1); 8813 PHYMOD_IF_ERR_RETURN( 8814 WRITE_SC_X4_IEEE_25G_CTL_GEN2r(pc, ieee_25G_am_reg)); 8815 8816 /* MSA Mode Program 25G AM0 value to use 100G AM AM123 should use 40G AM 8817 * The rest AM should use 40G AM, which is a default 8818 */ 8819 PHYMOD_IF_ERR_RETURN( 8820 READ_SC_X4_MSA_25G_50G_CTL_GEN2r(pc, &msa_25g_50g_am_reg)); 8821 SC_X4_MSA_25G_50G_CTL_GEN2r_MSA_25G_AM0_FORMATf_SET(msa_25g_50g_am_reg, 1); 8822 PHYMOD_IF_ERR_RETURN( 8823 WRITE_SC_X4_MSA_25G_50G_CTL_GEN2r(pc, msa_25g_50g_am_reg)); 8824 8825 /* Enable AM parallel detect for incase if the legacy devices use 40G AM */ 8826 PHYMOD_IF_ERR_RETURN( 8827 READ_RX_X4_IEEE_25G_PARLLEL_DET_CTR_GEN2r(pc, &ieee_25g_parallel_det_reg)); 8828 RX_X4_IEEE_25G_PARLLEL_DET_CTR_GEN2r_SET(ieee_25g_parallel_det_reg, 1); 8829 PHYMOD_IF_ERR_RETURN( 8830 WRITE_RX_X4_IEEE_25G_PARLLEL_DET_CTR_GEN2r(pc, ieee_25g_parallel_det_reg)); 8831 8832 return PHYMOD_E_NONE; 8833 8834 } 8835 8836 STATIC 8837 int _tefmod_rx_phy_lane_get(PHYMOD_ST *pc, int rx_logical_lane, 8838 int* rx_phy_lane) 8839 { 8840 MAIN0_LN_SWPr_t reg_lane_swap; 8841 RX_X1_RX_LN_SWP_GEN2r_t rx_lane_map_r; 8842 MAIN0_SERDESIDr_t serdesid; 8843 phymod_access_t pa_copy; 8844 uint32_t model; 8845 8846 PHYMOD_MEMCPY(&pa_copy, pc, sizeof(pa_copy)); 8847 8848 /*always use lane 0 copy since register is single copy */ 8849 pa_copy.lane_mask = 0x1; 8850 8851 READ_MAIN0_SERDESIDr(pc, &serdesid); 8852 model = MAIN0_SERDESIDr_MODEL_NUMBERf_GET(serdesid); 8853 8854 if (model == TSCF_GEN2) { 8855 PHYMOD_IF_ERR_RETURN(READ_RX_X1_RX_LN_SWP_GEN2r(&pa_copy, &rx_lane_map_r)); 8856 8857 switch (rx_logical_lane) { 8858 case 0: 8859 *rx_phy_lane = BCMI_TSCF_XGXS_RX_X1_RX_LN_SWP_GEN2r_LOGICAL0_TO_PHY_SELf_GET(rx_lane_map_r); 8860 break; 8861 case 1: 8862 *rx_phy_lane = BCMI_TSCF_XGXS_RX_X1_RX_LN_SWP_GEN2r_LOGICAL1_TO_PHY_SELf_GET(rx_lane_map_r); 8863 break; 8864 case 2: 8865 *rx_phy_lane = BCMI_TSCF_XGXS_RX_X1_RX_LN_SWP_GEN2r_LOGICAL2_TO_PHY_SELf_GET(rx_lane_map_r); 8866 break; 8867 case 3: 8868 *rx_phy_lane = BCMI_TSCF_XGXS_RX_X1_RX_LN_SWP_GEN2r_LOGICAL3_TO_PHY_SELf_GET(rx_lane_map_r); 8869 break; 8870 default: 8871 return PHYMOD_E_PARAM; 8872 } 8873 } else { 8874 PHYMOD_IF_ERR_RETURN(READ_MAIN0_LN_SWPr(&pa_copy, ®_lane_swap)); 8875 8876 switch (rx_logical_lane) { 8877 case 0: 8878 *rx_phy_lane = MAIN0_LN_SWPr_LOGICAL0_TO_PHY_SELf_GET(reg_lane_swap); 8879 break; 8880 case 1: 8881 *rx_phy_lane = MAIN0_LN_SWPr_LOGICAL1_TO_PHY_SELf_GET(reg_lane_swap); 8882 break; 8883 case 2: 8884 *rx_phy_lane = MAIN0_LN_SWPr_LOGICAL2_TO_PHY_SELf_GET(reg_lane_swap); 8885 break; 8886 case 3: 8887 *rx_phy_lane = MAIN0_LN_SWPr_LOGICAL3_TO_PHY_SELf_GET(reg_lane_swap); 8888 break; 8889 default: 8890 return PHYMOD_E_PARAM; 8891 } 8892 } 8893 8894 return PHYMOD_E_NONE; 8895 } 8896 8897 int tefmod_synce_stg0_mode_set(PHYMOD_ST *pc, int mode) 8898 { 8899 int start_lane = 0, num_lane = 0, phy_lane = 0; 8900 MAIN0_SYNCE_CTL_STAGE0r_t MAIN0_SYNCE_CTL_STAGE0r_reg; 8901 8902 PHYMOD_IF_ERR_RETURN 8903 (phymod_util_lane_config_get(pc, &start_lane, &num_lane)); 8904 8905 MAIN0_SYNCE_CTL_STAGE0r_CLR(MAIN0_SYNCE_CTL_STAGE0r_reg); 8906 8907 PHYMOD_IF_ERR_RETURN 8908 (_tefmod_rx_phy_lane_get(pc, start_lane, &phy_lane)); 8909 8910 PHYMOD_IF_ERR_RETURN(READ_MAIN0_SYNCE_CTL_STAGE0r(pc, 8911 &MAIN0_SYNCE_CTL_STAGE0r_reg)); 8912 8913 switch(phy_lane) { 8914 case 0: 8915 MAIN0_SYNCE_CTL_STAGE0r_SYNCE_STAGE0_MODE_PHY_LANE0f_SET( 8916 MAIN0_SYNCE_CTL_STAGE0r_reg, mode); 8917 break; 8918 case 1: 8919 MAIN0_SYNCE_CTL_STAGE0r_SYNCE_STAGE0_MODE_PHY_LANE1f_SET( 8920 MAIN0_SYNCE_CTL_STAGE0r_reg, mode); 8921 break; 8922 case 2: 8923 MAIN0_SYNCE_CTL_STAGE0r_SYNCE_STAGE0_MODE_PHY_LANE2f_SET( 8924 MAIN0_SYNCE_CTL_STAGE0r_reg, mode); 8925 break; 8926 case 3: 8927 MAIN0_SYNCE_CTL_STAGE0r_SYNCE_STAGE0_MODE_PHY_LANE3f_SET( 8928 MAIN0_SYNCE_CTL_STAGE0r_reg, mode); 8929 break; 8930 default: 8931 return PHYMOD_E_PARAM; 8932 } 8933 8934 PHYMOD_IF_ERR_RETURN(MODIFY_MAIN0_SYNCE_CTL_STAGE0r(pc, 8935 MAIN0_SYNCE_CTL_STAGE0r_reg)); 8936 8937 return PHYMOD_E_NONE; 8938 } 8939 8940 int tefmod_synce_stg1_mode_set(PHYMOD_ST *pc, int mode) 8941 { 8942 int start_lane = 0, num_lane = 0, phy_lane = 0; 8943 MAIN0_SYNCE_CTLr_t MAIN0_SYNCE_CTLr_reg; 8944 8945 PHYMOD_IF_ERR_RETURN 8946 (phymod_util_lane_config_get(pc, &start_lane, &num_lane)); 8947 8948 MAIN0_SYNCE_CTLr_CLR(MAIN0_SYNCE_CTLr_reg); 8949 8950 PHYMOD_IF_ERR_RETURN 8951 (_tefmod_rx_phy_lane_get(pc, start_lane, &phy_lane)); 8952 8953 PHYMOD_IF_ERR_RETURN(READ_MAIN0_SYNCE_CTLr(pc, &MAIN0_SYNCE_CTLr_reg)); 8954 8955 switch(phy_lane) { 8956 case 0: 8957 MAIN0_SYNCE_CTLr_SYNCE_MODE_PHY_LANE0f_SET( 8958 MAIN0_SYNCE_CTLr_reg, mode); 8959 break; 8960 case 1: 8961 MAIN0_SYNCE_CTLr_SYNCE_MODE_PHY_LANE1f_SET( 8962 MAIN0_SYNCE_CTLr_reg, mode); 8963 break; 8964 case 2: 8965 MAIN0_SYNCE_CTLr_SYNCE_MODE_PHY_LANE2f_SET( 8966 MAIN0_SYNCE_CTLr_reg, mode); 8967 break; 8968 case 3: 8969 MAIN0_SYNCE_CTLr_SYNCE_MODE_PHY_LANE3f_SET( 8970 MAIN0_SYNCE_CTLr_reg, mode); 8971 break; 8972 default: 8973 return PHYMOD_E_PARAM; 8974 } 8975 8976 PHYMOD_IF_ERR_RETURN(MODIFY_MAIN0_SYNCE_CTLr(pc, MAIN0_SYNCE_CTLr_reg)); 8977 8978 return PHYMOD_E_NONE; 8979 } 8980 8981 int tefmod_synce_clk_ctrl_set(PHYMOD_ST *pc, uint32_t val) 8982 { 8983 int start_lane = 0, num_lane = 0, phy_lane = 0; 8984 phymod_access_t pa_copy; 8985 RX_X4_SYNCE_FRACTIONAL_DIVr_t RX_X4_SYNCE_FRACTIONAL_DIVr_reg; 8986 8987 PHYMOD_IF_ERR_RETURN 8988 (phymod_util_lane_config_get(pc, &start_lane, &num_lane)); 8989 8990 PHYMOD_IF_ERR_RETURN 8991 (_tefmod_rx_phy_lane_get(pc, start_lane, &phy_lane)); 8992 8993 PHYMOD_MEMCPY(&pa_copy, pc, sizeof(pa_copy)); 8994 pa_copy.lane_mask = 0x1 << phy_lane; 8995 8996 RX_X4_SYNCE_FRACTIONAL_DIVr_CLR(RX_X4_SYNCE_FRACTIONAL_DIVr_reg); 8997 RX_X4_SYNCE_FRACTIONAL_DIVr_SET(RX_X4_SYNCE_FRACTIONAL_DIVr_reg, val); 8998 PHYMOD_IF_ERR_RETURN(MODIFY_RX_X4_SYNCE_FRACTIONAL_DIVr(&pa_copy, 8999 RX_X4_SYNCE_FRACTIONAL_DIVr_reg)); 9000 9001 return PHYMOD_E_NONE; 9002 } 9003 9004 int tefmod_synce_stg0_mode_get(PHYMOD_ST *pc, int *mode) 9005 { 9006 int start_lane = 0, num_lane = 0, phy_lane = 0; 9007 MAIN0_SYNCE_CTL_STAGE0r_t MAIN0_SYNCE_CTL_STAGE0r_reg; 9008 9009 PHYMOD_IF_ERR_RETURN 9010 (phymod_util_lane_config_get(pc, &start_lane, &num_lane)); 9011 9012 MAIN0_SYNCE_CTL_STAGE0r_CLR(MAIN0_SYNCE_CTL_STAGE0r_reg); 9013 9014 PHYMOD_IF_ERR_RETURN 9015 (_tefmod_rx_phy_lane_get(pc, start_lane, &phy_lane)); 9016 9017 PHYMOD_IF_ERR_RETURN(READ_MAIN0_SYNCE_CTL_STAGE0r(pc, 9018 &MAIN0_SYNCE_CTL_STAGE0r_reg)); 9019 9020 switch(phy_lane) { 9021 case 0: 9022 *mode = MAIN0_SYNCE_CTL_STAGE0r_SYNCE_STAGE0_MODE_PHY_LANE0f_GET( 9023 MAIN0_SYNCE_CTL_STAGE0r_reg); 9024 break; 9025 case 1: 9026 *mode = MAIN0_SYNCE_CTL_STAGE0r_SYNCE_STAGE0_MODE_PHY_LANE1f_GET( 9027 MAIN0_SYNCE_CTL_STAGE0r_reg); 9028 break; 9029 case 2: 9030 *mode = MAIN0_SYNCE_CTL_STAGE0r_SYNCE_STAGE0_MODE_PHY_LANE2f_GET( 9031 MAIN0_SYNCE_CTL_STAGE0r_reg); 9032 break; 9033 case 3: 9034 *mode = MAIN0_SYNCE_CTL_STAGE0r_SYNCE_STAGE0_MODE_PHY_LANE3f_GET( 9035 MAIN0_SYNCE_CTL_STAGE0r_reg); 9036 break; 9037 default: 9038 return PHYMOD_E_PARAM; 9039 } 9040 9041 return PHYMOD_E_NONE; 9042 } 9043 9044 int tefmod_synce_stg1_mode_get(PHYMOD_ST *pc, int *mode) 9045 { 9046 int start_lane = 0, num_lane = 0, phy_lane = 0; 9047 MAIN0_SYNCE_CTLr_t MAIN0_SYNCE_CTLr_reg; 9048 9049 PHYMOD_IF_ERR_RETURN 9050 (phymod_util_lane_config_get(pc, &start_lane, &num_lane)); 9051 9052 MAIN0_SYNCE_CTLr_CLR(MAIN0_SYNCE_CTLr_reg); 9053 9054 PHYMOD_IF_ERR_RETURN 9055 (_tefmod_rx_phy_lane_get(pc, start_lane, &phy_lane)); 9056 9057 PHYMOD_IF_ERR_RETURN(READ_MAIN0_SYNCE_CTLr(pc, &MAIN0_SYNCE_CTLr_reg)); 9058 9059 switch(phy_lane) { 9060 case 0: 9061 *mode = MAIN0_SYNCE_CTLr_SYNCE_MODE_PHY_LANE0f_GET( 9062 MAIN0_SYNCE_CTLr_reg); 9063 break; 9064 case 1: 9065 *mode = MAIN0_SYNCE_CTLr_SYNCE_MODE_PHY_LANE1f_GET( 9066 MAIN0_SYNCE_CTLr_reg); 9067 break; 9068 case 2: 9069 *mode = MAIN0_SYNCE_CTLr_SYNCE_MODE_PHY_LANE2f_GET( 9070 MAIN0_SYNCE_CTLr_reg); 9071 break; 9072 case 3: 9073 *mode = MAIN0_SYNCE_CTLr_SYNCE_MODE_PHY_LANE3f_GET( 9074 MAIN0_SYNCE_CTLr_reg); 9075 break; 9076 default: 9077 return PHYMOD_E_PARAM; 9078 } 9079 return PHYMOD_E_NONE; 9080 } 9081 9082 int tefmod_synce_clk_ctrl_get(PHYMOD_ST *pc, uint32_t *val) 9083 { 9084 int start_lane = 0, num_lane = 0, phy_lane = 0; 9085 phymod_access_t pa_copy; 9086 RX_X4_SYNCE_FRACTIONAL_DIVr_t RX_X4_SYNCE_FRACTIONAL_DIVr_reg; 9087 9088 PHYMOD_IF_ERR_RETURN 9089 (phymod_util_lane_config_get(pc, &start_lane, &num_lane)); 9090 9091 PHYMOD_IF_ERR_RETURN 9092 (_tefmod_rx_phy_lane_get(pc, start_lane, &phy_lane)); 9093 9094 PHYMOD_MEMCPY(&pa_copy, pc, sizeof(pa_copy)); 9095 pa_copy.lane_mask = 0x1 << phy_lane; 9096 9097 RX_X4_SYNCE_FRACTIONAL_DIVr_CLR(RX_X4_SYNCE_FRACTIONAL_DIVr_reg); 9098 9099 PHYMOD_IF_ERR_RETURN(READ_RX_X4_SYNCE_FRACTIONAL_DIVr(&pa_copy, 9100 &RX_X4_SYNCE_FRACTIONAL_DIVr_reg)); 9101 9102 *val = RX_X4_SYNCE_FRACTIONAL_DIVr_GET(RX_X4_SYNCE_FRACTIONAL_DIVr_reg); 9103 9104 return PHYMOD_E_NONE; 9105 } 9106 9107 #endif /* _SDK_TEFMOD_ */