tefmod.h (25327B)
1 /*---------------------------------------------------------------------- 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * $Copyright: (c) 2014 Broadcom Corporation All Rights Reserved.$ 8 * Broadcom Corporation 9 * Proprietary and Confidential information 10 * All rights reserved 11 * This source file is the property of Broadcom Corporation, and 12 * may not be copied or distributed in any isomorphic form without the 13 * prior written consent of Broadcom Corporation. 14 *---------------------------------------------------------------------- 15 * Description: define enumerators 16 *----------------------------------------------------------------------*/ 17 /* 18 * 19 * $Copyright: 20 * All Rights Reserved.$ 21 */ 22 23 #ifndef _tefmod_H_ 24 #define _tefmod_H_ 25 26 #ifndef _DV_TB_ 27 #define _SDK_TEFMOD_ 1 28 #endif 29 30 #ifdef _DV_TB_ 31 #ifdef LINUX 32 #include <stdint.h> 33 #endif 34 #include <stdio.h> 35 #include <string.h> 36 #include <stdlib.h> 37 #include "errno.h" 38 #endif 39 40 #ifdef _SDK_TEFMOD_ 41 #include <phymod/phymod.h> 42 #include <phymod/phymod_debug.h> 43 #include "tefmod_enum_defines.h" 44 #endif 45 46 #ifdef _SDK_TEFMOD_ 47 #define PHYMOD_ST const phymod_access_t 48 #else 49 #define PHYMOD_ST tefmod_st 50 #endif 51 52 #define TEFMOD_FEC_NOT_SUPRTD 0 53 #define TEFMOD_FEC_SUPRTD_NOT_REQSTD 1 54 #define TEFMOD_FEC_CL74_SUPRTD_REQSTD 4 55 #define TEFMOD_FEC_CL91_SUPRTD_REQSTD 8 56 57 /* matching SOC_PHY_CONTROL_FEC_OFF 58 * SOC_PHY_CONTROL_FEC_ON 59 * SOC_PHY_CONTROL_FEC_AUTO 60 */ 61 #define TEFMOD_PHY_CONTROL_FEC_OFF 0 62 #define TEFMOD_PHY_CONTROL_FEC_ON 1 63 #define TEFMOD_PHY_CONTROL_FEC_AUTO 2 64 65 66 /* So far 4 bits debug mask are used by TEFMOD */ 67 #define TEFMOD_DBG_MEM (1L << 4) /* allocation/object */ 68 #define TEFMOD_DBG_REGACC (1L << 3) /* Print all register accesses */ 69 #define TEFMOD_DBG_FUNCVALOUT (1L << 2) /* All values returned by Tier1*/ 70 #define TEFMOD_DBG_FUNCVALIN (1L << 1) /* All values pumped into Tier1*/ 71 #define TEFMOD_DBG_FUNC (1L << 0) /* Every time we enter a Tier1*/ 72 73 typedef enum { 74 TEFMOD_AN_MODE_CL73 = 0, 75 TEFMOD_AN_MODE_CL73BAM, 76 TEFMOD_AN_MODE_HPAM, 77 TEFMOD_AN_MODE_NONE, 78 TEFMOD_AN_MODE_CL73_MSA, 79 TEFMOD_AN_MODE_MSA, 80 TEFMOD_AN_MODE_TYPE_COUNT 81 }tefmod_an_mode_type_t; 82 83 84 85 typedef enum { 86 TEFMOD_AN_SET_RF_DISABLE = 0, 87 TEFMOD_AN_SET_SGMII_SPEED, 88 TEFMOD_AN_SET_SGMII_MASTER, 89 TEFMOD_AN_SET_HG_MODE, 90 TEFMOD_AN_SET_FEC_MODE, 91 TEFMOD_AN_SET_CL72_MODE, 92 TEFMOD_AN_SET_CL37_ATTR, 93 TEFMOD_AN_SET_CL48_SYNC, 94 TEFMOD_AN_SET_LK_FAIL_INHIBIT_TIMER_NO_CL72, 95 TEFMOD_AN_SET_CL73_FEC_OFF, 96 TEFMOD_AN_SET_CL73_FEC_ON, 97 TEFMOD_AN_SET_SPEED_PAUSE, 98 TEFMOD_AN_SET_TYPE_COUNT 99 }tefmod_an_set_type_t; 100 101 typedef union { 102 int tefmod_an_set_rf_disable; 103 int tefmod_an_set_sgmii_speed; 104 int tefmod_an_set_sgmii_master; 105 tefmod_an_set_type_t tefmod_an_set_cl37_attr; 106 }tefmod_an_set_value_t; 107 108 typedef enum { 109 TEFMOD_CL73_10GBASE_KR1 = 0, 110 TEFMOD_CL73_40GBASE_KR4, 111 TEFMOD_CL73_40GBASE_CR4, 112 TEFMOD_CL73_100GBASE_KR4, 113 TEFMOD_CL73_100GBASE_CR4, 114 TEFMOD_CL73_1GBASE_KX, 115 TEFMOD_CL73_25GBASE_KR1, 116 TEFMOD_CL73_25GBASE_CR1, 117 TEFMOD_CL73_25GBASE_KRS1, 118 TEFMOD_CL73_25GBASE_CRS1, 119 TEFMOD_CL73_SPEED_COUNT 120 }tefmod_cl73_speed_t; 121 122 typedef enum { 123 TEFMOD_CL73_BAM_20GBASE_KR2 = 0, 124 TEFMOD_CL73_BAM_20GBASE_CR2, 125 TEFMOD_CL73_BAM_40GBASE_KR2, 126 TEFMOD_CL73_BAM_40GBASE_CR2, 127 TEFMOD_CL73_BAM_RESERVED_1, 128 TEFMOD_CL73_BAM_RESERVED_2, 129 TEFMOD_CL73_BAM_50GBASE_KR2, 130 TEFMOD_CL73_BAM_50GBASE_CR2, 131 TEFMOD_CL73_BAM_50GBASE_KR4, 132 TEFMOD_CL73_BAM_50GBASE_CR4, 133 TEFMOD_CL73_BAM_SPEED_COUNT 134 }tefmod_cl73_bam_speed_t; 135 136 typedef enum { 137 TEFMOD_CL73_BAM_20GBASE_KR1 = 1, 138 TEFMOD_CL73_BAM_20GBASE_CR1, 139 TEFMOD_CL73_BAM_25GBASE_KR1, 140 TEFMOD_CL73_BAM_25GBASE_CR1, 141 TEFMOD_CL73_BAM_SPEED1_COUNT 142 }tefmod_cl73_bam_speed1_t; 143 144 typedef enum { 145 TEFMOD_NO_PAUSE = 0, 146 TEFMOD_SYMM_PAUSE, 147 TEFMOD_ASYM_PAUSE, 148 TEFMOD_ASYM_SYMM_PAUSE, 149 TEFMOD_AN_PAUSE_COUNT 150 }tefmod_an_pause_t; 151 152 typedef enum { 153 OVERRIDE_CLEAR = 0x0000, 154 OVERRIDE_NUM_LANES = 0x0001, 155 OVERRIDE_OS_MODE = 0x0002, 156 OVERRIDE_T_FIFO_MODE = 0x0004, 157 OVERRIDE_T_ENC_MODE = 0x0008, 158 OVERRIDE_T_HG2_ENABLE = 0x0010, 159 OVERRIDE_T_PMA_BTMX_MODE_OEN = 0x0020, 160 OVERRIDE_SCR_MODE = 0x0040, 161 OVERRIDE_DESCR_MODE_OEN = 0x0100, 162 OVERRIDE_DEC_TL_MODE = 0x0200, 163 OVERRIDE_DESKEW_MODE = 0x0400, 164 OVERRIDE_DEC_FSM_MODE = 0x0800, 165 OVERRIDE_R_HG2_ENABLE = 0x8001, 166 OVERRIDE_BS_SM_SYNC_MODE_OEN = 0x8002, 167 OVERRIDE_BS_SYNC_EN_OEN = 0x8004, 168 OVERRIDE_BS_DIST_MODE_OEN = 0x8008, 169 OVERRIDE_BS_BTMX_MODE_OEN = 0x8010, 170 OVERRIDE_CL72_EN = 0x8020, 171 OVERRIDE_CLOCKCNT0 = 0xf040, 172 OVERRIDE_CLOCKCNT1 = 0x8080, 173 OVERRIDE_LOOPCNT0 = 0x8100, 174 OVERRIDE_LOOPCNT1 = 0x8200, 175 OVERRIDE_MAC_CREDITGENCNT = 0x8400, 176 OVERRIDE_NUM_LANES_DIS = 0xff01, 177 OVERRIDE_OS_MODE_DIS = 0xff02, 178 OVERRIDE_T_FIFO_MODE_DIS = 0xff03, 179 OVERRIDE_T_ENC_MODE_DIS = 0xff04, 180 OVERRIDE_T_HG2_ENABLE_DIS = 0xff05, 181 OVERRIDE_T_PMA_BTMX_MODE_OEN_DIS= 0xff06, 182 OVERRIDE_SCR_MODE_DIS = 0xff07, 183 OVERRIDE_DESCR_MODE_OEN_DIS = 0xff08, 184 OVERRIDE_DEC_TL_MODE_DIS = 0xff09, 185 OVERRIDE_DESKEW_MODE_DIS = 0xff0a, 186 OVERRIDE_DEC_FSM_MODE_DIS = 0xff0b, 187 OVERRIDE_R_HG2_ENABLE_DIS = 0xff0c, 188 OVERRIDE_BS_SM_SYNC_MODE_OEN_DIS= 0xff0d, 189 OVERRIDE_BS_SYNC_EN_OEN_DIS = 0xff0e, 190 OVERRIDE_BS_DIST_MODE_OEN_DIS = 0xff0f, 191 OVERRIDE_BS_BTMX_MODE_OEN_DIS = 0xff10, 192 OVERRIDE_CL72_EN_DIS = 0xff11, 193 OVERRIDE_CLOCKCNT0_DIS = 0xff12, 194 OVERRIDE_CLOCKCNT1_DIS = 0xff13, 195 OVERRIDE_LOOPCNT0_DIS = 0xff14, 196 OVERRIDE_LOOPCNT1_DIS = 0xff15, 197 OVERRIDE_MAC_CREDITGENCNT_DIS = 0xff16 198 } override_type_t; 199 200 typedef enum { 201 TEFMOD_HG2_CODEC_OFF = 0, 202 TEFMOD_HG2_CODEC_ON_8BYTE_IPG, 203 TEFMOD_HG2_CODEC_ON_9BYTE_IPG, 204 TEFMOD_HG2_CODEC_COUNT 205 }tefmod_hg2_codec_t; 206 207 typedef enum { 208 TEFMOD_NO_CL91_FEC = 0, 209 TEFMOD_CL91_SINGLE_LANE_FC, 210 TEFMOD_CL91_SINGLE_LANE_BRCM_PROP, 211 TEFMOD_CL91_DUAL_LANE_BRCM_PROP, 212 TEFMOD_CL91_QUAD_LANE, 213 TEFMOD_IEEE_25G_CL91_SINGLE_LANE, 214 TEFMOD_CL91_COUNT 215 }tefmod_cl91_fec_mode_t; 216 217 /** 218 \struct tefmod_an_adv_ability_s 219 TBD 220 */ 221 222 typedef struct tefmod_an_adv_ability_s{ 223 tefmod_cl73_speed_t an_base_speed; 224 tefmod_cl73_bam_speed_t an_bam_speed; 225 tefmod_cl73_bam_speed1_t an_bam_speed1; 226 uint16_t an_nxt_page; 227 tefmod_an_pause_t an_pause; 228 uint16_t an_fec; 229 uint16_t an_cl72; 230 uint16_t an_hg2; 231 }tefmod_an_adv_ability_t; 232 233 typedef struct tefmod_an_ability_s{ 234 tefmod_an_adv_ability_t cl73_adv; /*includes cl73 and cl73-bam related */ 235 }tefmod_an_ability_t; 236 237 /** 238 \struct tefmod_an_oui_s 239 oui : New oui 240 override_bam73_adv : Adv new OUI for BAM73 241 override_bam73_det : Detect new OUI for BAM73 242 override_hpam_adv : Adv new OUI for HPAM 243 override_hpam_det : Detect new OUI for HPAM 244 */ 245 typedef struct tefmod_an_oui_s { 246 uint32_t oui; 247 uint16_t oui_override_bam73_adv; 248 uint16_t oui_override_bam73_det; 249 uint16_t oui_override_hpam_adv; 250 uint16_t oui_override_hpam_det; 251 } tefmod_an_oui_t; 252 253 typedef struct tefmod_an_control_s { 254 tefmod_an_type_t an_type; 255 uint16_t num_lane_adv; 256 uint16_t enable; 257 uint16_t pd_kx_en; 258 an_property_enable an_property_type; 259 uint16_t cl72_config_allowed; 260 } tefmod_an_control_t; 261 262 /** 263 \struct tefmod_an_init_s 264 265 This embodies all parameters required to program autonegotiation features in the 266 PHY for both CL37 and CL73 type autonegotiation and the BAM variants. 267 For details of individual fields, please refer to microarchitectural doc. 268 */ 269 typedef struct tefmod_an_init_s{ 270 uint16_t an_fail_cnt; 271 uint16_t linkfailtimer_dis; 272 uint16_t linkfailtimerqua_en; 273 uint16_t an_good_check_trap; 274 uint16_t an_good_trap; 275 uint16_t bam73_adv_oui; 276 uint16_t bam73_det_oui; 277 uint16_t hpam_adv_oui; 278 uint16_t hpam_det_oui; 279 uint16_t disable_rf_report; 280 uint16_t cl73_remote_fault; 281 uint16_t cl73_nonce_match_over; 282 uint16_t cl73_nonce_match_val; 283 uint16_t cl73_transmit_nonce; 284 uint16_t base_selector; 285 } tefmod_an_init_t; 286 287 288 /** 289 \struct tefmod_an_timers_s 290 TBD 291 */ 292 typedef struct tefmod_an_timers_s{ 293 uint16_t value; 294 } tefmod_an_timers_t; 295 296 /* definitions for SW AN PAGE */ 297 #define BRCM_OUI 0xAF7 298 #define BRCM_BAM_CODE 0x3 299 #define HP_OUI 0x643150 300 #define HP_USR_DEF_FIELD 0xABE20 301 #define MSA_OUI 0x6A737D /* OUI defined for consortium 25G */ 302 #define MSA_OUI_13to23 0x353 303 #define MSA_OUT_2to12 0x4DF 304 #define MSA_OUI_0to1 0x1 305 #define EXT_TECH_ABILITY_CODE 0x3 306 #define MSA_MSG_CODE 0x5 307 308 309 /* Below macros are defined based on IEEE and MSA 25G spec 310 * for detailed information Please refer to the 311 * IEEE 802.3by section 73.6 Link codeword encoding 312 * MSA Spec section 3.2.5 Auto-negotiation Figure 10 313 */ 314 315 #define AN_BASE0_PAGE_IEEE_SEL_MASK 0x1F 316 #define AN_BASE0_PAGE_IEEE_SEL_OFFSET 0x0 317 318 #define AN_BASE0_PAGE_CL73_NOUNCE_MASK 0x1F 319 #define AN_BASE0_PAGE_CL73_NOUNCE_OFFSET 0x5 320 321 /* pause capability not related to PHY */ 322 #define AN_BASE0_PAGE_CAP_MASK 0x3 323 #define AN_BASE0_PAGE_CAP_OFFSET 0xA 324 325 #define AN_BASE0_PAGE_REMOTE_FAULT_MASK 0x1 326 #define AN_BASE0_PAGE_REMOTE_FAULT_OFFSET 0xD 327 328 /* acknowledgement bit postion */ 329 #define AN_BASE0_PAGE_ACK_MASK 0x1 330 #define AN_BASE0_PAGE_ACK_OFFSET 0xE 331 332 /* Next Page bit postion */ 333 #define AN_BASE0_PAGE_NP_MASK 0x1 334 #define AN_BASE0_PAGE_NP_OFFSET 0xF 335 336 337 #define AN_BASE1_PAGE_TX_NOUNCE_MASK 0x1F 338 #define AN_BASE1_PAGE_TX_NOUNCE_OFFSET 0x0 339 340 #define AN_BASE1_PAGE_ABILITY_MASK 0x7FF 341 #define AN_BASE1_PAGE_ABILITY_OFFSET 0x5 342 343 #define AN_BASE_TECH_ABILITY_1000KX_MASK 0x1 344 #define AN_BASE_TECH_ABILITY_1000KX_OFFSET 0x5 345 346 #define AN_BASE_TECH_ABILITY_10GKX4_MASK 0x1 347 #define AN_BASE_TECH_ABILITY_10GKX4_OFFSET 0x6 348 349 #define AN_BASE_TECH_ABILITY_10GKR_MASK 0x1 350 #define AN_BASE_TECH_ABILITY_10GKR_OFFSET 0x7 351 352 #define AN_BASE_TECH_ABILITY_40GKR4_MASK 0x1 353 #define AN_BASE_TECH_ABILITY_40GKR4_OFFSET 0x8 354 355 #define AN_BASE_TECH_ABILITY_40GCR4_MASK 0x1 356 #define AN_BASE_TECH_ABILITY_40GCR4_OFFSET 0x9 357 358 #define AN_BASE_TECH_ABILITY_100GCR10_MASK 0x1 359 #define AN_BASE_TECH_ABILITY_100GCR10_OFFSET 0xA 360 361 #define AN_BASE_TECH_ABILITY_100GKP4_MASK 0x1 362 #define AN_BASE_TECH_ABILITY_100GKP4_OFFSET 0xB 363 364 #define AN_BASE_TECH_ABILITY_100GKR4_MASK 0x1 365 #define AN_BASE_TECH_ABILITY_100GKR4_OFFSET 0xC 366 367 #define AN_BASE_TECH_ABILITY_100GCR4_MASK 0x1 368 #define AN_BASE_TECH_ABILITY_100GCR4_OFFSET 0xD 369 370 #define AN_BASE_TECH_ABILITY_25GKRS_MASK 0x1 371 #define AN_BASE_TECH_ABILITY_25GKRS_OFFSET 0xE 372 373 #define AN_BASE_TECH_ABILITY_25GKR_MASK 0x1 374 #define AN_BASE_TECH_ABILITY_25GKR_OFFSET 0xF 375 376 #define AN_BASE2_PAGE_ABILITY_RSVD_MASK 0xFF7 377 #define AN_BASE2_PAGE_ABILITY_RSVD_OFFSET 0x0 378 379 #define AN_BASE2_PAGE_FEC_ABILITY_MASK 0xF 380 #define AN_BASE2_PAGE_FEC_ABILITY_OFFSET 0xC 381 382 #define AN_BASE_CL74_ABILITY_SUP_MASK 0x1 383 #define AN_BASE_CL74_ABILITY_SUP_OFFSET 0xE 384 385 #define AN_BASE_CL74_ABILITY_REQ_MASK 0x1 386 #define AN_BASE_CL74_ABILITY_REQ_OFFSET 0xF 387 388 #define AN_BASE_CL91_ABILITY_REQ_MASK 0x1 389 #define AN_BASE_CL91_ABILITY_REQ_OFFSET 0xC 390 391 #define AN_BASE_CL74_25GKRS_REQ_MASK 0x1 392 #define AN_BASE_CL74_25GKRS_REQ_OFFSET 0xD 393 394 /* Message Page definitions */ 395 396 #define AN_MSG_PAGE0_MSG_CODE_MASK 0x3FF 397 #define AN_MSG_PAGE0_MSG_CODE_OFFSET 0x0 398 399 #define AN_MSG_PAGE0_TOGGLE_MASK 0x1 400 #define AN_MSG_PAGE0_TOGGLE_OFFSET 0xB 401 402 #define AN_MSG_PAGE0_ACK2_MASK 0x1 403 #define AN_MSG_PAGE0_ACK2_OFFSET 0xC 404 405 #define AN_MSG_PAGE0_MSG_PAGE_MASK 0x1 406 #define AN_MSG_PAGE0_MSG_PAGE_OFFSET 0xD 407 408 #define AN_MSG_PAGE0_ACK_MASK 0x1 409 #define AN_MSG_PAGE0_ACK_OFFSET 0xE 410 411 #define AN_MSG_PAGE0_NP_MASK 0x1 412 #define AN_MSG_PAGE0_NP_OFFSET 0xF 413 414 #define AN_MSG_PAGE1_OUI_13to23_MASK 0x7FF 415 #define AN_MSG_PAGE1_OUI_13to23_OFFSET 0x0 416 417 #define AN_MSG_PAGE2_OUI_2to12_MASK 0x7FF 418 #define AN_MSG_PAGE2_OUI_2to12_OFFSET 0x0 419 420 /* Unformatted Page for MSA */ 421 422 #define AN_UF_PAGE0_EXT_TECH_ABILITY_MASK 0xFF 423 #define AN_UF_PAGE0_EXT_TECH_ABILITY_OFFSET 0x0 424 425 #define AN_UF_PAGE0_OUI_MASK 0x3 426 #define AN_UF_PAGE0_OUI_OFFSET 0x9 427 428 #define AN_UF_PAGE0_TOGGLE_MASK 0x1 429 #define AN_UF_PAGE0_TOGGLE_OFFSET 0xB 430 431 #define AN_UF_PAGE0_ACK_MASK 0x1 432 #define AN_UF_PAGE0_ACK_OFFSET 0xE 433 434 #define AN_UF_PAGE0_NP_MASK 0x1 435 #define AN_UF_PAGE0_NP_OFFSET 0xF 436 437 #define AN_UF_PAGE1_25G_KR1_ABILITY_MASK 0x1 438 #define AN_UF_PAGE1_25G_KR1_ABILITY_OFFSET 0x4 439 440 #define AN_UF_PAGE1_25G_CR1_ABILITY_MASK 0x1 441 #define AN_UF_PAGE1_25G_CR1_ABILITY_OFFSET 0x5 442 443 #define AN_UF_PAGE1_50G_KR2_ABILITY_MASK 0x1 444 #define AN_UF_PAGE1_50G_KR2_ABILITY_OFFSET 0x8 445 446 #define AN_UF_PAGE1_50G_CR2_ABILITY_MASK 0x1 447 #define AN_UF_PAGE1_50G_CR2_ABILITY_OFFSET 0x9 448 449 #define AN_UF_PAGE2_CL91_SUPPORT_MASK 0x1 450 #define AN_UF_PAGE2_CL91_SUPPORT_OFFSET 0x8 451 452 #define AN_UF_PAGE2_CL74_SUPPORT_MASK 0x1 453 #define AN_UF_PAGE2_CL74_SUPPORT_OFFSET 0x9 454 455 #define AN_UF_PAGE2_CL91_REQ_MASK 0x1 456 #define AN_UF_PAGE2_CL91_REQ_OFFSET 0xA 457 458 #define AN_UF_PAGE2_CL74_REQ_MASK 0x1 459 #define AN_UF_PAGE2_CL74_REQ_OFFSET 0xB 460 461 #define TEFMOD_25G_KR_SPD_IF 0x11 462 #define TEFMOD_25G_CR_SPD_IF 0x10 463 464 #define TEFMOD_50G_KR2_SPD_IF 0x31 465 #define TEFMOD_50G_CR2_SPD_IF 0x30 466 467 #define TEFMOD_100G_KR4_SPD_IF 0x41 468 #define TEFMOD_100G_CR4_SPD_IF 0x40 469 470 #define HCD_SPEED_ID_UNDEFINED 0xFF 471 472 typedef enum ieee_sel_e { 473 IEEE_SEL_RSVD = 0, 474 IEEE_SEL_802P3, 475 IEEE_SEL_802P9, 476 IEEE_SEL_802P5, 477 IEEE_SEL_1394 478 } ieee_sel_t; 479 480 typedef enum an_page_id_e { 481 TEFMOD_AN_PAGE_ID_NONE = 0, 482 TEFMOD_AN_PAGE_ID_BASE_PAGE, 483 TEFMOD_AN_PAGE_ID_MSG_PAGE, 484 TEFMOD_AN_PAGE_ID_UP_PAGE, 485 TEFMOD_AN_PAGE_ID_NULL_PAGE, 486 TEFMOD_AN_PAGE_ID_MAX 487 } an_page_id_t; 488 489 490 #ifdef CHECKIFNEEDED 491 492 extern int get_mapped_speed(tefmod_spd_intfc_type spd_intf, int *speed); 493 extern int get_actual_speed(int speed_id, int *speed); 494 495 #endif 496 extern int phymod_debug_check(uint32_t flags, PHYMOD_ST *pc); 497 498 extern int configure_st_entry(int st_entry_num, int st_entry_speed, PHYMOD_ST* pc); 499 500 extern int tefmod_pmd_osmode_set(PHYMOD_ST* pc, tefmod_spd_intfc_type_t spd_intf, phymod_ref_clk_t refclk, int os_mode); 501 extern int tefmod_pmd_x4_reset(PHYMOD_ST* pc); 502 extern int tefmod_tx_loopback_get(PHYMOD_ST* pc, uint32_t *enable); 503 extern int tefmod_firmware_set(PHYMOD_ST* pc); 504 extern int tefmod_tx_lane_disable (PHYMOD_ST* pc, int tx); 505 extern int tefmod_init_pcs_ilkn(PHYMOD_ST* pc); 506 extern int tefmod_pcs_ilkn_chk(PHYMOD_ST* pc, int *ilkn_set); 507 extern int tefmod_pmd_reset_bypass (PHYMOD_ST* pc, int pmd_reset_control); 508 extern int tefmod_afe_speed_up_dsc_vga(PHYMOD_ST* pc); 509 extern int tefmod_get_plldiv(PHYMOD_ST* pc, uint32_t *plldiv_r_val); 510 extern int tefmod_update_port_mode_select(PHYMOD_ST* pc, tefmod_port_type_t port_type, int master_port, int tsc_clk_freq_pll_by_48, int pll_reset_en); 511 extern int tefmod_set_port_mode(PHYMOD_ST* pc, int refclk, int plldiv, tefmod_port_type_t port_type, int master_port, int tsc_clk_freq_pll_by_48, int pll_reset_en); 512 extern int tefmod_tx_loopback_control(PHYMOD_ST* pc, int pcs_gloop_en, int starting_lane, int num_lanes); 513 extern int tefmod_tx_pmd_loopback_control(PHYMOD_ST* pc, int pmd_gloop_en); 514 extern int tefmod_rx_loopback_control(PHYMOD_ST* pc, int pcs_rloop_en); 515 extern int tefmod_rx_pmd_loopback_control(PHYMOD_ST* pc, int pcs_rloop_en, int pmd_rloop_en, int lane); 516 extern int tefmod_credit_set(PHYMOD_ST* pc); 517 extern int tefmod_encode_set(PHYMOD_ST* pc, int per_lane_control, tefmod_spd_intfc_type_t spd_intf, int tx_am_timer_init_val); 518 extern int tefmod_lf_rf_control(PHYMOD_ST* pc); 519 extern int tefmod_decode_set(PHYMOD_ST* pc); 520 extern int tefmod_trigger_speed_change(PHYMOD_ST* pc); 521 extern int tefmod_set_override_0(PHYMOD_ST* pc, int per_field_override_en); 522 extern int tefmod_set_override_1(PHYMOD_ST* pc, int per_lane_control, uint32_t per_field_override_en); 523 extern int tefmod_credit_control(PHYMOD_ST* pc, int per_lane_control); 524 extern int tefmod_tx_lane_control_set(PHYMOD_ST* pc, tefmod_tx_disable_enum_t dis); 525 extern int tefmod_tx_lane_control_get(PHYMOD_ST* pc, int *reset, int *enable); 526 extern int tefmod_rx_lane_control(PHYMOD_ST* pc, int accData, int per_lane_control); 527 extern int tefmod_bypass_sc(PHYMOD_ST* pc); 528 extern int tefmod_revid_read(PHYMOD_ST* pc, uint32_t *revIdV); 529 extern int tefmod_clause72_control(PHYMOD_ST* pc, int per_lane_control); 530 extern int tefmod_prbs_check(PHYMOD_ST* pc, int accData); 531 extern int tefmod_prbs_mode(PHYMOD_ST* pc, int per_lane_control); 532 extern int tefmod_prbs_control(PHYMOD_ST* pc, int per_lane_control); 533 extern int tefmod_cjpat_crpat_control(PHYMOD_ST* pc); 534 extern int tefmod_cjpat_crpat_check(PHYMOD_ST* pc); 535 extern int tefmod_tx_bert_control(PHYMOD_ST* pc); 536 extern int tefmod_FEC_control(PHYMOD_ST* pc, tefmod_fec_type_t fec_type, int enable, int cl74or91); 537 extern int tefmod_FEC_get(PHYMOD_ST* pc, tefmod_fec_type_t fec_type, int *fec_en); 538 extern int tefmod_power_control(PHYMOD_ST* pc, int tx, int rx); 539 extern int tefmod_duplex_control(PHYMOD_ST* pc); 540 extern int tefmod_disable_pcs_falcon(PHYMOD_ST* pc); 541 extern int tefmod_pmd_addr_lane_swap(PHYMOD_ST *pc, int per_lane_control); 542 extern int tefmod_pmd_lane_swap_tx(PHYMOD_ST *pc, int per_lane_control); 543 extern int tefmod_pmd_reset_remove(PHYMOD_ST *pc, int pmd_touched); 544 extern int tefmod_pcs_lane_swap(PHYMOD_ST *pc, int per_lane_control); 545 extern int tefmod_init_pcs_falcon(PHYMOD_ST* pc); 546 extern int tefmod_init_pmd_falcon(PHYMOD_ST* pc); 547 extern int tefmod_set_sc_speed(PHYMOD_ST* pc); 548 extern int tefmod_poll_for_sc_done(PHYMOD_ST* pc, int mapped_speed); 549 extern int tefmod_check_status(PHYMOD_ST* pc); 550 extern int tefmod_set_port_mode_sel(PHYMOD_ST* pc, int tsc_touched, tefmod_port_type_t port_type); 551 extern int tefmod_init_pcs_fs(PHYMOD_ST* pc); 552 extern int tefmod_init_pcs_an(PHYMOD_ST* pc); 553 extern int tefmod_set_an_override(PHYMOD_ST* pc); 554 extern int tefmod_tx_squelch_get(PHYMOD_ST *pc, int *val); 555 extern int tefmod_refclk_get(PHYMOD_ST* pc, phymod_ref_clk_t* ref_clk); 556 extern int tefmod_refclk_set(PHYMOD_ST* pc, phymod_ref_clk_t ref_clock); 557 558 extern int tefmod_get_mapped_speed(tefmod_spd_intfc_type_t spd_intf, int *speed); 559 extern int tefmod_toggle_sw_speed_change(PHYMOD_ST* pc); 560 561 extern int tefmod_autoneg_get(PHYMOD_ST* pc); 562 #ifdef _DV_TB_ 563 extern int tefmod_autoneg_set(PHYMOD_ST* pc); 564 extern int tefmod_autoneg_control(PHYMOD_ST* pc); 565 extern int tefmod_set_spd_intf(PHYMOD_ST* pc); 566 extern int tefmod_set_an_port_mode(PHYMOD_ST* pc); 567 #endif /* _DV_TB_ */ 568 #ifdef _SDK_TEFMOD_ 569 int tefmod_set_an_port_mode(PHYMOD_ST* pc, int num_of_lanes, int starting_lane); 570 extern int tefmod_set_an_single_port_mode(PHYMOD_ST* pc, int an_enable); 571 extern int tefmod_set_spd_intf(PHYMOD_ST *pc, tefmod_spd_intfc_type_t spd_intf); 572 extern int tefmod_autoneg_set_init(PHYMOD_ST* pc, tefmod_an_init_t *an_init_st); 573 extern int tefmod_autoneg_timer_init(PHYMOD_ST* pc); 574 extern int tefmod_autoneg_control(PHYMOD_ST* pc, tefmod_an_control_t *an_control); 575 extern int tefmod_autoneg_ability_set(PHYMOD_ST* pc, tefmod_an_adv_ability_t *an_ability_st); 576 extern int tefmod_diag(PHYMOD_ST *ws, tefmod_diag_type_t diag_type); 577 extern int tefmod_diag_disp(PHYMOD_ST *ws, const char* arg); 578 extern int tefmod_autoneg_control_get(PHYMOD_ST* pc, tefmod_an_control_t *an_control, int *an_complete); 579 extern int tefmod_autoneg_ability_get(PHYMOD_ST* pc, tefmod_an_adv_ability_t *an_ability_st); 580 extern int tefmod_autoneg_remote_ability_get(PHYMOD_ST* pc, tefmod_an_adv_ability_t *an_ability_st); 581 extern int tefmod_st_control_field_set (PHYMOD_ST* pc,uint16_t st_entry_no, override_type_t st_control_field, uint16_t st_field_value); 582 extern int tefmod_port_enable_set(PHYMOD_ST *pc, int enable); 583 extern int tefmod_tx_squelch_set(PHYMOD_ST *pc, int enable); 584 extern int tefmod_rx_squelch_set(PHYMOD_ST *pc, int enable); 585 extern int tefmod_rx_squelch_get(PHYMOD_ST *pc, int *enable); 586 extern int tefmod_default_init(PHYMOD_ST* pc); 587 extern int tefmod_pmd_x4_reset_get(PHYMOD_ST *pc, int *is_in_reset); 588 #endif /* _SDK_TEFMOD_ */ 589 590 extern int tefmod_port_enable_get(PHYMOD_ST *pc, int *tx_enable, int *rx_enable); 591 extern int tefmod_pll_lock_get(PHYMOD_ST* pc, int* lockStatus); 592 extern int tefmod_pmd_lock_get(PHYMOD_ST* pc, uint32_t* lockStatus); 593 extern int tefmod_set_pll_mode(PHYMOD_ST* pc, int pmd_touched, tefmod_spd_intfc_type_t spd_intf, int pll_mode); /* SET_PLL_MODE */ 594 extern int tefmod_speed_id_get(PHYMOD_ST* pc, int *speed_id); 595 extern int tefmod_pmd_reset_seq(PHYMOD_ST* pc, int pmd_touched); /* PMD_RESET_SEQ */ 596 extern int tefmod_master_port_num_set( PHYMOD_ST *pc, int port_num); 597 extern int tefmod_update_port_mode( PHYMOD_ST *pa, int *pll_restart); 598 extern int tefmod_pll_reset_enable_set (PHYMOD_ST *pa , int enable); 599 extern int tefmod_get_pcs_link_status(PHYMOD_ST* pc, uint32_t *link); 600 extern int tefmod_get_pcs_latched_link_status(PHYMOD_ST* pc, uint32_t *link); 601 extern int tefmod_disable_get(PHYMOD_ST* pc, uint32_t* enable); 602 extern int tefmod_disable_set(PHYMOD_ST* pc); 603 extern int tefmod_enable_set(PHYMOD_ST* pc); 604 extern int tefmod_plldiv_lkup_get(PHYMOD_ST* pc, tefmod_spd_intfc_type_t spd_intf, phymod_ref_clk_t refclk, uint32_t *plldiv); 605 extern int tefmod_osmode_lkup_get(PHYMOD_ST* pc, tefmod_spd_intfc_type_t spd_intf, uint32_t *osmode); 606 extern int tefmod_pcs_lane_swap_get ( PHYMOD_ST *pc, uint32_t *tx_rx_swap); 607 extern int tefmod_pmd_lane_swap_tx_get ( PHYMOD_ST *pc, uint32_t *tx_lane_map); 608 extern int tefmod_rx_lane_control_set(PHYMOD_ST* pc, int enable); /* RX_LANE_CONTROL */ 609 extern int tefmod_rx_lane_control_get(PHYMOD_ST* pc, int *enable); 610 extern int tefmod_tx_rx_polarity_get ( PHYMOD_ST *pc, uint32_t* tx_polarity, uint32_t* rx_polarity); 611 extern int tefmod_tx_rx_polarity_set ( PHYMOD_ST *pc, uint32_t tx_polarity, uint32_t rx_polarity); 612 613 int tefmod_eee_control_set(PHYMOD_ST* pc, uint32_t enable); 614 int tefmod_eee_control_get(PHYMOD_ST* pc, uint32_t* enable); 615 int tefmod_cl74_chng_default (PHYMOD_ST* pc); 616 int tefmod_cl91_ecc_clear(PHYMOD_ST* pc, uint32_t model); 617 618 extern int tefmod_an_msa_mode_set(PHYMOD_ST* pc, uint32_t val); 619 extern int tefmod_an_msa_mode_get(PHYMOD_ST* pc, uint32_t* val); 620 extern int tefmod_an_oui_set(PHYMOD_ST* pc, tefmod_an_oui_t oui); 621 extern int tefmod_an_oui_get(PHYMOD_ST* pc, tefmod_an_oui_t *oui); 622 extern int tefmod_autoneg_status_get(PHYMOD_ST* pc, int *an_en, int *an_done); 623 extern int tefmod_autoneg_lp_status_get(PHYMOD_ST* pc, uint16_t *baseP0, uint16_t *baseP1, uint16_t *baseP2, uint16_t *nextP3, uint16_t *nextP4); 624 extern int tefmod_hg2_codec_set(PHYMOD_ST* pc, tefmod_hg2_codec_t hg2_codec); 625 extern int tefmod_hg2_codec_get(PHYMOD_ST* pc, tefmod_hg2_codec_t* hg2_codec); 626 627 extern int tefmod_fec_correctable_counter_get(PHYMOD_ST* pc, uint32_t* count); 628 extern int tefmod_fec_uncorrectable_counter_get(PHYMOD_ST* pc, uint32_t* count); 629 extern int tefmod_fec_cl91_correctable_counter_get(PHYMOD_ST* pc, uint32_t* count); 630 extern int tefmod_fec_cl91_uncorrectable_counter_get(PHYMOD_ST* pc, uint32_t* count); 631 extern int tefmod_pcs_ilkn_mode_set(PHYMOD_ST* pc); /* INIT_PCS_ILKN */ 632 633 extern int tefmod_sw_an_control(PHYMOD_ST* pc, int enable); 634 extern int tefmod_sw_an_ld_page_load(PHYMOD_ST* pc, phymod_an_page_t *pages, int is_base_page); 635 extern int tefmod_sw_an_lp_page_read(PHYMOD_ST* pc, phymod_an_page_t *pages); 636 extern int tefmod_sw_an_ctl_sts_get(PHYMOD_ST* pc, phymod_sw_an_ctrl_status_t *an_ctrl_status); 637 extern int tefmod_sw_an_set_ack(PHYMOD_ST* pc); 638 extern int tefmod_set_speed_id(PHYMOD_ST *pc, int speed_id); 639 extern int tefmod_setup_for_sw_an(PHYMOD_ST* pc, int num_lanes); 640 extern int tefmod_pxgng_status_an_ack_complete_get(PHYMOD_ST *pc, int *ack_complte); 641 extern int tefmod_pxgng_status_an_good_chk_get(PHYMOD_ST *pc, uint8_t *an_good_chk); 642 extern int tefmod_sw_an_control(PHYMOD_ST *pc, int enable); 643 extern int tefmod_sw_an_advert_set(PHYMOD_ST* pc, tefmod_an_adv_ability_t *cl73_adv, phymod_sw_an_ctxt_t *an_ctxt); 644 extern int tefmod_sw_an_fec_override(PHYMOD_ST *pc, tefmod_fec_type_t fec_type, int enable); 645 extern int tefmod_serdes_model_get(PHYMOD_ST *pc, uint32_t *model); 646 extern int tefmod_25g_rsfec_am_init(PHYMOD_ST *pc); 647 648 extern int tefmod_encode_mode_get(PHYMOD_ST* pc, tefmod_encode_mode *mode); 649 extern int tefmod_bip_error_counter_get(PHYMOD_ST* pc, uint32_t* count); 650 extern int tefmod_cl49_ber_counter_get(PHYMOD_ST* pc, uint32_t* count); 651 extern int tefmod_cl82_ber_counter_get(PHYMOD_ST* pc, uint32_t* count); 652 extern int tefmod_fec_override_set(PHYMOD_ST *pc, uint32_t enable); 653 extern int tefmod_fec_override_get(PHYMOD_ST *pc, uint32_t *enable); 654 655 extern int tefmod_synce_stg0_mode_set(PHYMOD_ST *pc, int mode); 656 extern int tefmod_synce_stg0_mode_get(PHYMOD_ST *pc, int *mode); 657 extern int tefmod_synce_stg1_mode_set(PHYMOD_ST *pc, int mode); 658 extern int tefmod_synce_stg1_mode_get(PHYMOD_ST *pc, int *mode); 659 extern int tefmod_synce_clk_ctrl_set(PHYMOD_ST *pc, uint32_t val); 660 extern int tefmod_synce_clk_ctrl_get(PHYMOD_ST *pc, uint32_t *val); 661 #endif /* _tefmod_H_ */ 662