tsce_dpll.c (145403B)
1 /* 2 * 3 * 4 * 5 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 6 * 7 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 8 */ 9 10 #include <phymod/phymod.h> 11 #include <phymod/phymod_system.h> 12 #include <phymod/phymod_dispatch.h> 13 #include <phymod/phymod_debug.h> 14 #include <phymod/phymod_util.h> 15 #include <phymod/chip/bcmi_tsce_dpll_xgxs_defs.h> 16 #include <phymod/chip/tsce_dpll.h> 17 #include "../../tsce_dpll/tier1/temod_dpll_enum_defines.h" 18 #include "../../tsce_dpll/tier1/temod_dpll.h" 19 #include "../../tsce_dpll/tier1/temod_dpll_device.h" 20 #include "../../tsce_dpll/tier1/temod_dpll_sc_lkup_table.h" 21 #include "../../tsce_dpll/tier1/tedpll_PCSRegEnums.h" 22 #include "../../eagle_dpll/tier1/eagle2_cfg_seq.h" 23 #include "../../eagle_dpll/tier1/eagle2_tsc2pll_common.h" 24 #include "../../eagle_dpll/tier1/eagle2_tsc2pll_interface.h" 25 #include "../../eagle_dpll/tier1/eagle2_tsc2pll_debug_functions.h" 26 #include "../../eagle_dpll/tier1/eagle2_tsc2pll_dependencies.h" 27 28 #define TSCE_DPLL_PHY_ACCESS_PLLIDX_SET(_phy_access) \ 29 do{\ 30 (_phy_access)->access.pll_idx = 0;\ 31 (_phy_access)->access.pll_idx = temod2pll_pll_index_get(&((_phy_access)->access));\ 32 }while(0) 33 #define TSCE_DPLL_ID0 0x600d 34 #define TSCE_DPLL_ID1 0x8770 35 #define TSCE_DPLL_REV_MASK 0x0 36 37 #define TSCE_DPLL_MODEL 0x23 38 #define TSCE_DPLL_REV_NUM 0x0 39 #define TSCE_DPLL_TECH 0x3 40 #define EAGLE_DPLL_MODEL 0x1a 41 42 #define TSCE_DPLL_NOF_DFES (5) 43 #define TSCE_DPLL_NOF_LANES_IN_CORE (4) 44 #define TSCE_DPLL_LANE_SWAP_LANE_MASK (0x3) 45 #define TSCE_DPLL_PHY_ALL_LANES (0xf) 46 #define TSCE_DPLL_CORE_TO_PHY_ACCESS(_phy_access, _core_access) \ 47 do{\ 48 PHYMOD_MEMCPY(&(_phy_access)->access, &(_core_access)->access, sizeof((_phy_access)->access));\ 49 (_phy_access)->type = (_core_access)->type; \ 50 (_phy_access)->port_loc = (_core_access)->port_loc; \ 51 (_phy_access)->device_op_mode = (_core_access)->device_op_mode; \ 52 (_phy_access)->access.lane_mask = TSCE_DPLL_PHY_ALL_LANES; \ 53 }while(0) 54 55 #define TSCE_DPLL_MAX_FIRMWARES (5) 56 57 #define TSCE_DPLL_USERSPEED_SELECT(_phy, _config, _type) \ 58 ((_config)->mode==phymodPcsUserSpeedModeST) ? \ 59 temod2pll_st_control_field_set(&(_phy)->access, (_config)->current_entry, _type, (_config)->value) : \ 60 temod2pll_override_set(&(_phy)->access, _type, (_config)->value) 61 62 #define TSCE_DPLL_USERSPEED_CREDIT_SELECT(_phy, _config, _type) \ 63 ((_config)->mode==phymodPcsUserSpeedModeST) ? \ 64 temod2pll_st_credit_field_set(&(_phy)->access, (_config)->current_entry, _type, (_config)->value) : \ 65 temod2pll_credit_override_set(&(_phy)->access, _type, (_config)->value) 66 #define TSCE_PLL_NUM 2 67 #define TSCE_DPLL_PMD_VERIFY_UCODE_LOAD 1 68 69 /*need to update after FW release*/ 70 #if 1 71 /* uController's firmware */ 72 extern unsigned char eagle2_tsc2pll_ucode[]; 73 extern unsigned short eagle2_tsc2pll_ucode_ver; 74 extern unsigned short eagle2_tsc2pll_ucode_crc; 75 extern unsigned short eagle2_tsc2pll_ucode_len; 76 #endif 77 78 typedef int (*sequncer_control_f)(const phymod_access_t* core, uint32_t enable); 79 typedef int (*rx_DFE_tap_control_set_f)(const phymod_access_t* phy, uint32_t val); 80 STATIC 81 int _tsce_dpll_phy_firmware_lane_config_set(const phymod_phy_access_t* phy, phymod_firmware_lane_config_t fw_config) 82 { 83 struct eagle2_tsc2pll_uc_lane_config_st serdes_firmware_config; 84 phymod_phy_access_t phy_copy; 85 int start_lane, num_lane, i; 86 /* uint32_t rst_status; */ 87 uint32_t is_warm_boot; 88 89 PHYMOD_MEMSET(&serdes_firmware_config, 0x0, sizeof(serdes_firmware_config)); 90 PHYMOD_IF_ERR_RETURN 91 (phymod_util_lane_config_get(&phy->access, &start_lane, &num_lane)); 92 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 93 TSCE_DPLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 94 95 for (i = 0; i < num_lane; i++) { 96 if (!PHYMOD_LANEPBMP_MEMBER(phy->access.lane_mask, start_lane + i)) { 97 continue; 98 } 99 phy_copy.access.lane_mask = 1 << (start_lane + i); 100 serdes_firmware_config.field.lane_cfg_from_pcs = fw_config.LaneConfigFromPCS; 101 serdes_firmware_config.field.an_enabled = fw_config.AnEnabled; 102 serdes_firmware_config.field.dfe_on = fw_config.DfeOn; 103 serdes_firmware_config.field.force_brdfe_on = fw_config.ForceBrDfe; 104 /* serdes_firmware_config.field.cl72_emulation_en = fw_config.Cl72Enable; */ 105 serdes_firmware_config.field.scrambling_dis = fw_config.ScramblingDisable; 106 serdes_firmware_config.field.unreliable_los = fw_config.UnreliableLos; 107 serdes_firmware_config.field.media_type = fw_config.MediaType; 108 serdes_firmware_config.field.cl72_auto_polarity_en = fw_config.Cl72AutoPolEn; 109 serdes_firmware_config.field.cl72_restart_timeout_en = fw_config.Cl72RestTO; 110 111 PHYMOD_IF_ERR_RETURN(PHYMOD_IS_WRITE_DISABLED(&phy_copy.access, &is_warm_boot)); 112 113 114 if(!is_warm_boot) { 115 /* PHYMOD_IF_ERR_RETURN(eagle_lane_soft_reset_read(&phy_copy.access, &rst_status)); */ 116 /* if(rst_status) */ PHYMOD_IF_ERR_RETURN (eagle2_tsc2pll_lane_soft_reset_release(&phy_copy.access, 0)); 117 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_set_uc_lane_cfg(&phy_copy.access, serdes_firmware_config)); 118 /* if(rst_status) */ PHYMOD_IF_ERR_RETURN (eagle2_tsc2pll_lane_soft_reset_release(&phy_copy.access, 1)); 119 } 120 } 121 return PHYMOD_E_NONE; 122 } 123 int tsce_dpll_core_identify(const phymod_core_access_t* core, uint32_t core_id, uint32_t* is_identified) 124 { 125 int ioerr = 0; 126 const phymod_access_t *pm_acc = &core->access; 127 PHYID2r_t id2; 128 PHYID3r_t id3; 129 MAIN0_SERDESIDr_t serdesid; 130 /* DIG_REVID0r_t revid; */ 131 uint32_t model, rev_num, tech_proc; 132 int rv ; 133 *is_identified = 0; 134 135 if(core_id == 0){ 136 ioerr += READ_PHYID2r(pm_acc, &id2); 137 ioerr += READ_PHYID3r(pm_acc, &id3); 138 } 139 else{ 140 PHYID2r_SET(id2, ((core_id >> 16) & 0xffff)); 141 PHYID3r_SET(id3, core_id & 0xffff); 142 } 143 144 if (PHYID2r_GET(id2) == TSCE_DPLL_ID0 && 145 (PHYID3r_GET(id3) &= ~TSCE_DPLL_REV_MASK) == TSCE_DPLL_ID1) { 146 /* PHY IDs match - now check PCS model */ 147 ioerr += READ_MAIN0_SERDESIDr(pm_acc, &serdesid); 148 model = MAIN0_SERDESIDr_MODEL_NUMBERf_GET(serdesid); 149 rev_num = MAIN0_SERDESIDr_REV_NUMBERf_GET(serdesid); 150 tech_proc = MAIN0_SERDESIDr_TECH_PROCf_GET(serdesid); 151 if ((model == TSCE_DPLL_MODEL) && (rev_num == TSCE_DPLL_REV_NUM) && 152 (tech_proc == TSCE_DPLL_TECH)) { 153 /* PCS model matches - now check PMD model */ 154 /* for now Bypass the pmd register rev check */ 155 /* ioerr += READ_DIG_REVID0r(pm_acc, &revid); 156 if (DIG_REVID0r_REVID_MODELf_GET(revid) == EAGLE_DPLL_MODEL) */ { 157 *is_identified = 1; 158 } 159 } 160 } 161 rv = ioerr ? PHYMOD_E_IO : PHYMOD_E_NONE; 162 return rv ; 163 } 164 165 166 int tsce_dpll_core_info_get(const phymod_core_access_t* core, phymod_core_info_t* info) 167 { 168 uint32_t serdes_id; 169 char core_name[15] = "TsceGen3"; 170 PHYID2r_t id2; 171 PHYID3r_t id3; 172 const phymod_access_t *pm_acc = &core->access; 173 174 PHYMOD_IF_ERR_RETURN 175 (temod2pll_revid_read(&core->access, &serdes_id)); 176 PHYMOD_IF_ERR_RETURN 177 (phymod_core_name_get(core, serdes_id, core_name, info)); 178 179 info->serdes_id = serdes_id; 180 info->core_version = phymodCoreVersionTsceDpll; 181 182 PHYMOD_IF_ERR_RETURN(READ_PHYID2r(pm_acc, &id2)); 183 PHYMOD_IF_ERR_RETURN(READ_PHYID3r(pm_acc, &id3)); 184 185 info->phy_id0 = (uint16_t) id2.v[0]; 186 info->phy_id1 = (uint16_t) id3.v[0]; 187 return PHYMOD_E_NONE; 188 189 } 190 191 192 int tsce_dpll_core_lane_map_set(const phymod_core_access_t* core, const phymod_lane_map_t* lane_map) 193 { 194 uint32_t pcs_swap = 0 , pmd_swap = 0, lane; 195 uint32_t addr_index_swap = 0, pmd_tx_map =0; 196 197 if (lane_map->num_of_lanes != TSCE_DPLL_NOF_LANES_IN_CORE) { 198 return PHYMOD_E_CONFIG; 199 } 200 for (lane = 0 ; lane < TSCE_DPLL_NOF_LANES_IN_CORE ; lane++) { 201 if (lane_map->lane_map_rx[lane] >= TSCE_DPLL_NOF_LANES_IN_CORE) { 202 return PHYMOD_E_CONFIG; 203 } 204 /* encode each lane as four bits */ 205 /* pcs_map[lane] = rx_map[lane] */ 206 pcs_swap += lane_map->lane_map_rx[lane]<<(lane*4); 207 } 208 209 for( lane = 0 ; lane < TSCE_DPLL_NOF_LANES_IN_CORE ; lane++){ 210 if(lane_map->lane_map_tx[lane] >= TSCE_DPLL_NOF_LANES_IN_CORE){ 211 return PHYMOD_E_CONFIG; 212 } 213 /* encode each lane as four bits. pmd_swap is logic base */ 214 /* considering the pcs lane swap: pmd_map[pcs_map[lane]] = tx_map[lane] */ 215 pmd_swap += lane_map->lane_map_tx[lane]<<(lane_map->lane_map_rx[lane]*4); 216 } 217 218 for( lane = 0 ; lane < TSCE_DPLL_NOF_LANES_IN_CORE ; lane++){ 219 addr_index_swap |= (lane << 4*((pcs_swap >> lane*4) & 0xf)) ; 220 pmd_tx_map |= (lane << 4*((pmd_swap >> lane*4) & 0xf)) ; 221 } 222 if (!PHYMOD_DEVICE_OP_MODE_PCS_BYPASS_GET(core->device_op_mode)) { 223 224 PHYMOD_IF_ERR_RETURN 225 (temod2pll_pcs_rx_lane_swap(&core->access, pcs_swap)); 226 PHYMOD_IF_ERR_RETURN 227 (temod2pll_pcs_tx_lane_swap(&core->access, pcs_swap)); 228 PHYMOD_IF_ERR_RETURN 229 (temod2pll_pmd_addr_lane_swap(&core->access, addr_index_swap)); 230 } 231 PHYMOD_IF_ERR_RETURN 232 (temod2pll_pmd_lane_swap_tx(&core->access, pmd_tx_map)); 233 return PHYMOD_E_NONE; 234 235 } 236 237 int tsce_dpll_core_lane_map_get(const phymod_core_access_t* core, phymod_lane_map_t* lane_map) 238 { 239 uint32_t pmd_swap = 0 , pcs_swap = 0, lane; 240 PHYMOD_IF_ERR_RETURN(temod2pll_pcs_rx_lane_swap_get(&core->access, &pcs_swap)); 241 PHYMOD_IF_ERR_RETURN(temod2pll_pmd_lane_swap_tx_get(&core->access, &pmd_swap)); 242 for( lane = 0 ; lane < TSCE_DPLL_NOF_LANES_IN_CORE ; lane++){ 243 /* deccode each lane from four bits */ 244 lane_map->lane_map_rx[lane] = (pcs_swap>>(lane*4)) & TSCE_DPLL_LANE_SWAP_LANE_MASK; 245 /* considering the pcs lane swap: tx_map[lane] = pmd_map[pcs_map[lane]] */ 246 lane_map->lane_map_tx[lane] = (pmd_swap>>(lane_map->lane_map_rx[lane]*4)) & TSCE_DPLL_LANE_SWAP_LANE_MASK; 247 } 248 lane_map->num_of_lanes = TSCE_DPLL_NOF_LANES_IN_CORE; 249 return PHYMOD_E_NONE; 250 251 } 252 253 254 int tsce_dpll_core_reset_set(const phymod_core_access_t* core, phymod_reset_mode_t reset_mode, phymod_reset_direction_t direction) 255 { 256 257 258 /* Place your code here */ 259 260 261 return PHYMOD_E_NONE; 262 263 } 264 265 int tsce_dpll_core_reset_get(const phymod_core_access_t* core, phymod_reset_mode_t reset_mode, phymod_reset_direction_t* direction) 266 { 267 268 269 /* Place your code here */ 270 271 272 return PHYMOD_E_NONE; 273 274 } 275 276 277 int tsce_dpll_core_firmware_info_get(const phymod_core_access_t* core, phymod_core_firmware_info_t* fw_info) 278 { 279 280 /* 281 * It's O.K to use this code as is since the firmware CRC is already checked at 282 * at the time we load it. 283 */ 284 fw_info->fw_crc = eagle2_tsc2pll_ucode_crc; 285 fw_info->fw_version = eagle2_tsc2pll_ucode_ver; 286 return PHYMOD_E_NONE; 287 288 } 289 290 /* load tsce fw. the fw_loader parameter is valid just for external fw load */ 291 STATIC 292 int _tsce_dpll_core_firmware_load(const phymod_core_access_t* core, phymod_firmware_load_method_t load_method, phymod_firmware_loader_f fw_loader) 293 { 294 #ifndef TSCE_DPLL_PMD_VERIFY_UCODE_LOAD 295 phymod_core_firmware_info_t actual_fw; 296 #endif 297 298 299 switch(load_method){ 300 case phymodFirmwareLoadMethodInternal: 301 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_ucode_mdio_load(&core->access, eagle2_tsc2pll_ucode, eagle2_tsc2pll_ucode_len)); 302 break; 303 case phymodFirmwareLoadMethodExternal: 304 PHYMOD_NULL_CHECK(fw_loader); 305 306 eagle2_tsc2pll_pram_flop_set(&core->access, 0x0); 307 308 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_ucode_init(&core->access)); 309 310 PHYMOD_IF_ERR_RETURN 311 (temod2pll_pram_abl_enable_set(&core->access,1)); 312 PHYMOD_IF_ERR_RETURN 313 (eagle2_tsc2pll_pram_firmware_enable(&core->access, 1)); 314 315 PHYMOD_IF_ERR_RETURN(fw_loader(core, eagle2_tsc2pll_ucode_len, eagle2_tsc2pll_ucode)); 316 317 PHYMOD_IF_ERR_RETURN 318 (eagle2_tsc2pll_pram_firmware_enable(&core->access, 0)); 319 PHYMOD_IF_ERR_RETURN 320 (temod2pll_pram_abl_enable_set(&core->access,0)); 321 break; 322 case phymodFirmwareLoadMethodNone: 323 break; 324 default: 325 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_CONFIG, (_PHYMOD_MSG("illegal fw load method %u"), load_method)); 326 } 327 return PHYMOD_E_NONE; 328 } 329 int tsce_dpll_phy_firmware_core_config_set(const phymod_phy_access_t* phy, phymod_firmware_core_config_t fw_core_config) 330 { 331 struct eagle2_tsc2pll_uc_core_config_st serdes_firmware_core_config; 332 PHYMOD_MEMSET(&serdes_firmware_core_config, 0, sizeof(serdes_firmware_core_config)); 333 serdes_firmware_core_config.field.core_cfg_from_pcs = fw_core_config.CoreConfigFromPCS; 334 serdes_firmware_core_config.field.vco_rate = fw_core_config.VcoRate; 335 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_set_uc_core_config(&phy->access, serdes_firmware_core_config)); 336 return PHYMOD_E_NONE; 337 338 } 339 340 int tsce_dpll_phy_firmware_core_config_get(const phymod_phy_access_t* phy, phymod_firmware_core_config_t* fw_core_config) 341 { 342 struct eagle2_tsc2pll_uc_core_config_st serdes_firmware_core_config; 343 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_get_uc_core_config(&phy->access, &serdes_firmware_core_config)); 344 PHYMOD_MEMSET(fw_core_config, 0, sizeof(*fw_core_config)); 345 fw_core_config->CoreConfigFromPCS = serdes_firmware_core_config.field.core_cfg_from_pcs; 346 fw_core_config->VcoRate = serdes_firmware_core_config.field.vco_rate; 347 return PHYMOD_E_NONE; 348 349 } 350 351 352 int tsce_dpll_phy_firmware_lane_config_set(const phymod_phy_access_t* phy, phymod_firmware_lane_config_t fw_lane_config) 353 { 354 phymod_phy_access_t phy_copy; 355 int start_lane, num_lane, i; 356 357 PHYMOD_IF_ERR_RETURN 358 (phymod_util_lane_config_get(&phy->access, &start_lane, &num_lane)); 359 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 360 TSCE_DPLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 361 362 /*Hold the per lne soft reset bit*/ 363 for (i = 0; i < num_lane; i++) { 364 if (!PHYMOD_LANEPBMP_MEMBER(phy->access.lane_mask, start_lane + i)) { 365 continue; 366 } 367 phy_copy.access.lane_mask = 1 << (start_lane + i); 368 PHYMOD_IF_ERR_RETURN 369 (eagle2_tsc2pll_lane_soft_reset_release(&phy_copy.access, 0)); 370 } 371 372 PHYMOD_IF_ERR_RETURN 373 (_tsce_dpll_phy_firmware_lane_config_set(phy, fw_lane_config)); 374 /*Hold the per lne soft reset bit*/ 375 for (i = 0; i < num_lane; i++) { 376 if (!PHYMOD_LANEPBMP_MEMBER(phy->access.lane_mask, start_lane + i)) { 377 continue; 378 } 379 phy_copy.access.lane_mask = 1 << (start_lane + i); 380 PHYMOD_IF_ERR_RETURN 381 (eagle2_tsc2pll_lane_soft_reset_release(&phy_copy.access, 1)); 382 } 383 384 PHYMOD_IF_ERR_RETURN 385 (temod2pll_trigger_speed_change(&phy->access)); 386 return PHYMOD_E_NONE; 387 388 } 389 390 int tsce_dpll_phy_firmware_lane_config_get(const phymod_phy_access_t* phy, phymod_firmware_lane_config_t* fw_lane_config) 391 { 392 struct eagle2_tsc2pll_uc_lane_config_st serdes_firmware_config; 393 phymod_phy_access_t phy_copy; 394 PHYMOD_MEMSET(&serdes_firmware_config, 0x0, sizeof(serdes_firmware_config)); 395 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 396 TSCE_DPLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 397 398 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_get_uc_lane_cfg(&phy_copy.access, &serdes_firmware_config)); 399 PHYMOD_MEMSET(fw_lane_config, 0, sizeof(*fw_lane_config)); 400 fw_lane_config->LaneConfigFromPCS = serdes_firmware_config.field.lane_cfg_from_pcs; 401 fw_lane_config->AnEnabled = serdes_firmware_config.field.an_enabled; 402 fw_lane_config->DfeOn = serdes_firmware_config.field.dfe_on; 403 fw_lane_config->ForceBrDfe = serdes_firmware_config.field.force_brdfe_on; 404 fw_lane_config->Cl72AutoPolEn = serdes_firmware_config.field.cl72_auto_polarity_en; 405 fw_lane_config->Cl72RestTO = serdes_firmware_config.field.cl72_restart_timeout_en; 406 fw_lane_config->ScramblingDisable = serdes_firmware_config.field.scrambling_dis; 407 fw_lane_config->UnreliableLos = serdes_firmware_config.field.unreliable_los; 408 fw_lane_config->MediaType = serdes_firmware_config.field.media_type; 409 fw_lane_config->Cl72AutoPolEn = serdes_firmware_config.field.cl72_auto_polarity_en; 410 fw_lane_config->Cl72RestTO = serdes_firmware_config.field.cl72_restart_timeout_en; 411 412 return PHYMOD_E_NONE; 413 414 } 415 416 417 int tsce_dpll_core_pll_sequencer_restart(const phymod_core_access_t* core, uint32_t flags, phymod_sequencer_operation_t operation) 418 { 419 switch (operation) { 420 case phymodSeqOpStop: 421 PHYMOD_IF_ERR_RETURN 422 (temod2pll_pll_sequencer_control(&core->access, 0)); 423 break; 424 case phymodSeqOpStart: 425 PHYMOD_IF_ERR_RETURN 426 (temod2pll_pll_sequencer_control(&core->access, 1)); 427 428 /* PHYMOD_IF_ERR_RETURN 429 (temod2pll_pll_lock_wait(&core->access, 250000)); */ 430 break; 431 case phymodSeqOpRestart: 432 PHYMOD_IF_ERR_RETURN 433 (temod2pll_pll_sequencer_control(&core->access, 0)); 434 435 PHYMOD_IF_ERR_RETURN 436 (temod2pll_pll_sequencer_control(&core->access, 1)); 437 438 /* PHYMOD_IF_ERR_RETURN 439 (temod2pll_pll_lock_wait(&core->access, 250000)); */ 440 break; 441 default: 442 return PHYMOD_E_UNAVAIL; 443 break; 444 } 445 return PHYMOD_E_NONE; 446 447 } 448 449 450 int tsce_dpll_core_wait_event(const phymod_core_access_t* core, phymod_core_event_t event, uint32_t timeout) 451 { 452 switch(event){ 453 case phymodCoreEventPllLock: 454 /* PHYMOD_IF_ERR_RETURN(temod2pll_pll_lock_wait(&core->access, timeout)); */ 455 break; 456 default: 457 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_CONFIG, (_PHYMOD_MSG("illegal wait event %u"), event)); 458 } 459 return PHYMOD_E_NONE; 460 461 } 462 463 464 int tsce_dpll_phy_rx_restart(const phymod_phy_access_t* phy) 465 { 466 phymod_phy_access_t phy_copy; 467 468 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 469 TSCE_DPLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 470 471 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_rx_restart(&phy_copy.access, 1)); 472 return PHYMOD_E_NONE; 473 } 474 475 476 int tsce_dpll_phy_polarity_set(const phymod_phy_access_t* phy, const phymod_polarity_t* polarity) 477 { 478 phymod_phy_access_t phy_copy; 479 480 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 481 TSCE_DPLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 482 483 PHYMOD_IF_ERR_RETURN 484 (temod2pll_tx_rx_polarity_set(&phy_copy.access, polarity->tx_polarity, polarity->rx_polarity)); 485 return PHYMOD_E_NONE; 486 } 487 488 int tsce_dpll_phy_polarity_get(const phymod_phy_access_t* phy, phymod_polarity_t* polarity) 489 { 490 phymod_phy_access_t phy_copy; 491 492 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 493 TSCE_DPLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 494 495 PHYMOD_IF_ERR_RETURN 496 (temod2pll_tx_rx_polarity_get(&phy_copy.access, &polarity->tx_polarity, &polarity->rx_polarity)); 497 return PHYMOD_E_NONE; 498 } 499 500 501 int tsce_dpll_phy_tx_set(const phymod_phy_access_t* phy, const phymod_tx_t* tx) 502 { 503 phymod_phy_access_t phy_copy; 504 505 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 506 TSCE_DPLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 507 508 509 PHYMOD_IF_ERR_RETURN 510 (eagle2_tsc2pll_write_tx_afe(&phy_copy.access, TX_AFE_PRE, (int8_t)tx->pre)); 511 PHYMOD_IF_ERR_RETURN 512 (eagle2_tsc2pll_write_tx_afe(&phy_copy.access, TX_AFE_MAIN, (int8_t)tx->main)); 513 PHYMOD_IF_ERR_RETURN 514 (eagle2_tsc2pll_write_tx_afe(&phy_copy.access, TX_AFE_POST1, (int8_t)tx->post)); 515 PHYMOD_IF_ERR_RETURN 516 (eagle2_tsc2pll_write_tx_afe(&phy_copy.access, TX_AFE_POST2, (int8_t)tx->post2)); 517 PHYMOD_IF_ERR_RETURN 518 (eagle2_tsc2pll_write_tx_afe(&phy_copy.access, TX_AFE_POST3, (int8_t)tx->post3)); 519 PHYMOD_IF_ERR_RETURN 520 (eagle2_tsc2pll_write_tx_afe(&phy_copy.access, TX_AFE_AMP, (int8_t)tx->amp)); 521 522 return PHYMOD_E_NONE; 523 524 } 525 526 int tsce_dpll_phy_tx_get(const phymod_phy_access_t* phy, phymod_tx_t* tx) 527 { 528 phymod_phy_access_t phy_copy; 529 int8_t value = 0; 530 531 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 532 TSCE_DPLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 533 534 PHYMOD_IF_ERR_RETURN 535 (eagle2_tsc2pll_read_tx_afe(&phy_copy.access, TX_AFE_PRE, &value)); 536 tx->pre = value; 537 PHYMOD_IF_ERR_RETURN 538 (eagle2_tsc2pll_read_tx_afe(&phy_copy.access, TX_AFE_MAIN, &value)); 539 tx->main = value; 540 PHYMOD_IF_ERR_RETURN 541 (eagle2_tsc2pll_read_tx_afe(&phy_copy.access, TX_AFE_POST1, &value)); 542 tx->post = value; 543 PHYMOD_IF_ERR_RETURN 544 (eagle2_tsc2pll_read_tx_afe(&phy_copy.access, TX_AFE_POST2, &value)); 545 tx->post2 = value; 546 PHYMOD_IF_ERR_RETURN 547 (eagle2_tsc2pll_read_tx_afe(&phy_copy.access, TX_AFE_POST3, &value)); 548 tx->post3 = value; 549 PHYMOD_IF_ERR_RETURN 550 (eagle2_tsc2pll_read_tx_afe(&phy_copy.access, TX_AFE_AMP, &value)); 551 tx->amp = value; 552 553 return PHYMOD_E_NONE; 554 555 } 556 557 558 int tsce_dpll_phy_tx_override_set(const phymod_phy_access_t* phy, const phymod_tx_override_t* tx_override) 559 { 560 phymod_phy_access_t phy_copy; 561 562 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 563 TSCE_DPLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 564 565 PHYMOD_IF_ERR_RETURN 566 (eagle2_tsc2pll_tx_pi_freq_override(&phy_copy.access, 567 tx_override->phase_interpolator.enable, 568 tx_override->phase_interpolator.value)); 569 return PHYMOD_E_NONE; 570 571 } 572 573 int tsce_dpll_phy_tx_override_get(const phymod_phy_access_t* phy, phymod_tx_override_t* tx_override) 574 { 575 int16_t pi_value; 576 phymod_phy_access_t phy_copy; 577 578 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 579 TSCE_DPLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 580 581 PHYMOD_IF_ERR_RETURN 582 (eagle2_tsc2pll_tx_pi_control_get(&phy_copy.access, &pi_value)); 583 584 tx_override->phase_interpolator.value = (int32_t) pi_value; 585 586 return PHYMOD_E_NONE; 587 } 588 589 int tsce_dpll_phy_txpi_config_set(const phymod_phy_access_t* phy, const phymod_txpi_config_t* config) 590 { 591 phymod_phy_access_t phy_copy; 592 593 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 594 TSCE_DPLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 595 596 PHYMOD_IF_ERR_RETURN 597 (eagle2_tsc2pll_tx_pi_enable_set(&phy_copy.access, config->enable)); 598 599 PHYMOD_IF_ERR_RETURN 600 (eagle2_tsc2pll_tx_pi_ext_pd_select_set(&phy_copy.access, config->mode == PHYMOD_TXPI_EXT_PD_MODE ? 1 : 0)); 601 602 return PHYMOD_E_NONE; 603 } 604 605 int tsce_dpll_phy_txpi_config_get(const phymod_phy_access_t* phy, phymod_txpi_config_t* config) 606 { 607 phymod_phy_access_t phy_copy; 608 uint32_t ext_pd; 609 610 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 611 TSCE_DPLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 612 613 PHYMOD_IF_ERR_RETURN 614 (eagle2_tsc2pll_tx_pi_enable_get(&phy_copy.access, &config->enable)); 615 616 PHYMOD_IF_ERR_RETURN 617 (eagle2_tsc2pll_tx_pi_ext_pd_select_get(&phy_copy.access, &ext_pd)); 618 619 config->mode = ext_pd ? PHYMOD_TXPI_EXT_PD_MODE : PHYMOD_TXPI_NORMAL_MODE; 620 621 return PHYMOD_E_NONE; 622 } 623 624 int tsce_dpll_phy_rx_set(const phymod_phy_access_t* phy, const phymod_rx_t* rx) 625 { 626 uint32_t i; 627 uint8_t uc_lane_stopped; 628 phymod_phy_access_t pm_phy_copy; 629 int start_lane, num_lane, k; 630 631 PHYMOD_MEMCPY(&pm_phy_copy, phy, sizeof(pm_phy_copy)); 632 TSCE_DPLL_PHY_ACCESS_PLLIDX_SET(&pm_phy_copy); 633 /* next program the tx fir taps and driver current based on the input */ 634 PHYMOD_IF_ERR_RETURN 635 (phymod_util_lane_config_get(&phy->access, &start_lane, &num_lane)); 636 637 /* params check */ 638 if((rx->num_of_dfe_taps == 0) || (rx->num_of_dfe_taps > TSCE_DPLL_NOF_DFES)){ 639 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_CONFIG, (_PHYMOD_MSG("illegal number of DFEs to set %u"), (unsigned int)rx->num_of_dfe_taps)); 640 } 641 642 for (k = 0; k < num_lane; k++) { 643 if (!PHYMOD_LANEPBMP_MEMBER(phy->access.lane_mask, start_lane + k)) { 644 continue; 645 } 646 pm_phy_copy.access.lane_mask = 1 << (start_lane + k); 647 648 /*vga set*/ 649 /* first check if uc lane is stopped already */ 650 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_stop_uc_lane_status(&pm_phy_copy.access, (uint8_t *) &uc_lane_stopped)); 651 if (!uc_lane_stopped) { 652 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_stop_rx_adaptation(&pm_phy_copy.access, 1)); 653 } 654 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_stop_rx_adaptation(&pm_phy_copy.access, 1)); 655 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_write_rx_afe(&pm_phy_copy.access, RX_AFE_VGA, rx->vga.value)); 656 /* dfe set */ 657 for (i = 0 ; i < rx->num_of_dfe_taps ; i++){ 658 switch (i) { 659 case 0: 660 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_write_rx_afe(&pm_phy_copy.access, RX_AFE_DFE1, rx->dfe[i].value)); 661 break; 662 case 1: 663 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_write_rx_afe(&pm_phy_copy.access, RX_AFE_DFE2, rx->dfe[i].value)); 664 break; 665 case 2: 666 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_write_rx_afe(&pm_phy_copy.access, RX_AFE_DFE3, rx->dfe[i].value)); 667 break; 668 case 3: 669 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_write_rx_afe(&pm_phy_copy.access, RX_AFE_DFE4, rx->dfe[i].value)); 670 break; 671 case 4: 672 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_write_rx_afe(&pm_phy_copy.access, RX_AFE_DFE5, rx->dfe[i].value)); 673 break; 674 default: 675 return PHYMOD_E_PARAM; 676 } 677 } 678 /*peaking filter set*/ 679 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_write_rx_afe(&pm_phy_copy.access, RX_AFE_PF, rx->peaking_filter.value)); 680 681 /* low freq peak filter */ 682 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_write_rx_afe(&pm_phy_copy.access, RX_AFE_PF2, (int8_t)rx->low_freq_peaking_filter.value)); 683 684 } 685 return PHYMOD_E_NONE; 686 } 687 688 int tsce_dpll_phy_rx_get(const phymod_phy_access_t* phy, phymod_rx_t* rx) 689 { 690 int8_t tmpData; 691 phymod_phy_access_t phy_copy; 692 693 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 694 TSCE_DPLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 695 696 PHYMOD_IF_ERR_RETURN 697 (eagle2_tsc2pll_read_rx_afe(&phy_copy.access, RX_AFE_PF, &tmpData)); 698 rx->peaking_filter.value = tmpData; 699 PHYMOD_IF_ERR_RETURN 700 (eagle2_tsc2pll_read_rx_afe(&phy_copy.access, RX_AFE_PF2, &tmpData)); 701 rx->low_freq_peaking_filter.value = tmpData; 702 PHYMOD_IF_ERR_RETURN 703 (eagle2_tsc2pll_read_rx_afe(&phy_copy.access, RX_AFE_VGA,&tmpData)); 704 rx->vga.value = tmpData; 705 PHYMOD_IF_ERR_RETURN 706 (eagle2_tsc2pll_read_rx_afe(&phy_copy.access, RX_AFE_DFE1,&tmpData)); 707 rx->dfe[0].value = tmpData; 708 PHYMOD_IF_ERR_RETURN 709 (eagle2_tsc2pll_read_rx_afe(&phy_copy.access, RX_AFE_DFE2,&tmpData)); 710 rx->dfe[1].value = tmpData; 711 PHYMOD_IF_ERR_RETURN 712 (eagle2_tsc2pll_read_rx_afe(&phy_copy.access, RX_AFE_DFE3, &tmpData)); 713 rx->dfe[2].value = tmpData; 714 PHYMOD_IF_ERR_RETURN 715 (eagle2_tsc2pll_read_rx_afe(&phy_copy.access, RX_AFE_DFE4,&tmpData)); 716 rx->dfe[3].value = tmpData; 717 PHYMOD_IF_ERR_RETURN 718 (eagle2_tsc2pll_read_rx_afe(&phy_copy.access, RX_AFE_DFE5,&tmpData)); 719 rx->dfe[4].value = tmpData; 720 721 rx->num_of_dfe_taps = 5; 722 rx->dfe[0].enable = 1; 723 rx->dfe[1].enable = 1; 724 rx->dfe[2].enable = 1; 725 rx->dfe[3].enable = 1; 726 rx->dfe[4].enable = 1; 727 rx->vga.enable = 1; 728 rx->low_freq_peaking_filter.enable = 1; 729 rx->peaking_filter.enable = 1; 730 731 return PHYMOD_E_NONE; 732 } 733 734 735 int tsce_dpll_phy_rx_adaptation_resume(const phymod_phy_access_t* phy) 736 { 737 738 739 /* Place your code here */ 740 741 742 return PHYMOD_E_NONE; 743 744 } 745 746 747 int tsce_dpll_phy_reset_set(const phymod_phy_access_t* phy, const phymod_phy_reset_t* reset) 748 { 749 750 751 /* Place your code here */ 752 753 754 return PHYMOD_E_NONE; 755 756 } 757 758 int tsce_dpll_phy_reset_get(const phymod_phy_access_t* phy, phymod_phy_reset_t* reset) 759 { 760 761 762 /* Place your code here */ 763 764 765 return PHYMOD_E_NONE; 766 767 } 768 769 770 int tsce_dpll_phy_power_set(const phymod_phy_access_t* phy, const phymod_phy_power_t* power) 771 { 772 phymod_phy_access_t pm_phy_copy; 773 int start_lane, num_lane, i; 774 775 PHYMOD_MEMCPY(&pm_phy_copy, phy, sizeof(pm_phy_copy)); 776 TSCE_DPLL_PHY_ACCESS_PLLIDX_SET(&pm_phy_copy); 777 /* next program the tx fir taps and driver current based on the input */ 778 PHYMOD_IF_ERR_RETURN 779 (phymod_util_lane_config_get(&phy->access, &start_lane, &num_lane)); 780 781 if ((power->tx == phymodPowerOff) && (power->rx == phymodPowerOff)) { 782 for (i = 0; i < num_lane; i++) { 783 if (!PHYMOD_LANEPBMP_MEMBER(phy->access.lane_mask, start_lane + i)) { 784 continue; 785 } 786 pm_phy_copy.access.lane_mask = 1 << (start_lane + i); 787 PHYMOD_IF_ERR_RETURN(temod2pll_port_enable_set(&pm_phy_copy.access, 0)); 788 } 789 } 790 if ((power->tx == phymodPowerOn) && (power->rx == phymodPowerOn)) { 791 for (i = 0; i < num_lane; i++) { 792 if (!PHYMOD_LANEPBMP_MEMBER(phy->access.lane_mask, start_lane + i)) { 793 continue; 794 } 795 pm_phy_copy.access.lane_mask = 1 << (start_lane + i); 796 PHYMOD_IF_ERR_RETURN(temod2pll_port_enable_set(&pm_phy_copy.access, 1)); 797 } 798 } 799 if ((power->tx == phymodPowerOff) && (power->rx == phymodPowerNoChange)) { 800 /* disable tx on the PMD side */ 801 for (i = 0; i < num_lane; i++) { 802 if (!PHYMOD_LANEPBMP_MEMBER(phy->access.lane_mask, start_lane + i)) { 803 continue; 804 } 805 pm_phy_copy.access.lane_mask = 1 << (start_lane + i); 806 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_tx_disable(&pm_phy_copy.access, 1)); 807 } 808 } 809 if ((power->tx == phymodPowerOn) && (power->rx == phymodPowerNoChange)) { 810 /* enable tx on the PMD side */ 811 for (i = 0; i < num_lane; i++) { 812 if (!PHYMOD_LANEPBMP_MEMBER(phy->access.lane_mask, start_lane + i)) { 813 continue; 814 } 815 pm_phy_copy.access.lane_mask = 1 << (start_lane + i); 816 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_tx_disable(&pm_phy_copy.access, 0)); 817 } 818 } 819 if ((power->tx == phymodPowerNoChange) && (power->rx == phymodPowerOff)) { 820 /* disable rx on the PMD side */ 821 for (i = 0; i < num_lane; i++) { 822 if (!PHYMOD_LANEPBMP_MEMBER(phy->access.lane_mask, start_lane + i)) { 823 continue; 824 } 825 pm_phy_copy.access.lane_mask = 1 << (start_lane + i); 826 PHYMOD_IF_ERR_RETURN(temod2pll_rx_squelch_set(&pm_phy_copy.access, 1)); 827 } 828 } 829 if ((power->tx == phymodPowerNoChange) && (power->rx == phymodPowerOn)) { 830 /* enable rx on the PMD side */ 831 for (i = 0; i < num_lane; i++) { 832 if (!PHYMOD_LANEPBMP_MEMBER(phy->access.lane_mask, start_lane + i)) { 833 continue; 834 } 835 pm_phy_copy.access.lane_mask = 1 << (start_lane + i); 836 PHYMOD_IF_ERR_RETURN(temod2pll_rx_squelch_set(&pm_phy_copy.access, 0)); 837 } 838 } 839 return PHYMOD_E_NONE; 840 } 841 842 int tsce_dpll_phy_power_get(const phymod_phy_access_t* phy, phymod_phy_power_t* power) 843 { 844 int enable; 845 uint32_t lb_enable; 846 phymod_phy_access_t pm_phy_copy; 847 int start_lane, num_lane; 848 849 PHYMOD_MEMCPY(&pm_phy_copy, phy, sizeof(pm_phy_copy)); 850 TSCE_DPLL_PHY_ACCESS_PLLIDX_SET(&pm_phy_copy); 851 /* next program the tx fir taps and driver current based on the input */ 852 PHYMOD_IF_ERR_RETURN 853 (phymod_util_lane_config_get(&phy->access, &start_lane, &num_lane)); 854 855 pm_phy_copy.access.lane_mask = 0x1 << start_lane; 856 857 PHYMOD_IF_ERR_RETURN(temod2pll_rx_squelch_get(&pm_phy_copy.access, &enable)); 858 859 /* next check if PMD loopback is on */ 860 if (enable) { 861 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_pmd_loopback_get(&pm_phy_copy.access, &lb_enable)); 862 if (lb_enable) enable = 0; 863 } 864 865 power->rx = (enable == 1)? phymodPowerOff: phymodPowerOn; 866 /* Commented the following line. Because if in PMD loopback mode, we squelch the 867 xmit, and we should still see the correct port status */ 868 /* PHYMOD_IF_ERR_RETURN(temod2pll_tx_squelch_get(&pm_phy_copy.access, &enable)); */ 869 power->tx = (enable == 1)? phymodPowerOff: phymodPowerOn; 870 return PHYMOD_E_NONE; 871 } 872 873 874 int tsce_dpll_phy_tx_lane_control_set(const phymod_phy_access_t* phy, phymod_phy_tx_lane_control_t tx_control) 875 { 876 phymod_phy_access_t pm_phy_copy; 877 PHYMOD_MEMCPY(&pm_phy_copy, phy, sizeof(pm_phy_copy)); 878 TSCE_DPLL_PHY_ACCESS_PLLIDX_SET(&pm_phy_copy); 879 880 switch (tx_control) { 881 case phymodTxTrafficDisable: 882 PHYMOD_IF_ERR_RETURN(temod2pll_tx_lane_control_set(&pm_phy_copy.access, TEMOD2PLL_TX_LANE_TRAFFIC_DISABLE)); 883 break; 884 case phymodTxTrafficEnable: 885 PHYMOD_IF_ERR_RETURN(temod2pll_tx_lane_control_set(&pm_phy_copy.access, TEMOD2PLL_TX_LANE_TRAFFIC_ENABLE)); 886 break; 887 case phymodTxReset: 888 PHYMOD_IF_ERR_RETURN(temod2pll_tx_lane_control_set(&pm_phy_copy.access, TEMOD2PLL_TX_LANE_RESET)); 889 break; 890 case phymodTxSquelchOn: 891 PHYMOD_IF_ERR_RETURN(temod2pll_tx_squelch_set(&pm_phy_copy.access, 1)); 892 break; 893 case phymodTxSquelchOff: 894 PHYMOD_IF_ERR_RETURN(temod2pll_tx_squelch_set(&pm_phy_copy.access, 0)); 895 break; 896 default: 897 break; 898 } 899 return PHYMOD_E_NONE; 900 } 901 902 int tsce_dpll_phy_tx_lane_control_get(const phymod_phy_access_t* phy, phymod_phy_tx_lane_control_t* tx_control) 903 { 904 int enable, reset, tx_lane; 905 uint32_t lb_enable; 906 phymod_phy_access_t pm_phy_copy; 907 int start_lane, num_lane; 908 909 PHYMOD_MEMCPY(&pm_phy_copy, phy, sizeof(pm_phy_copy)); 910 TSCE_DPLL_PHY_ACCESS_PLLIDX_SET(&pm_phy_copy); 911 /* next program the tx fir taps and driver current based on the input */ 912 PHYMOD_IF_ERR_RETURN 913 (phymod_util_lane_config_get(&phy->access, &start_lane, &num_lane)); 914 915 pm_phy_copy.access.lane_mask = 0x1 << start_lane; 916 917 PHYMOD_IF_ERR_RETURN(temod2pll_tx_squelch_get(&pm_phy_copy.access, &enable)); 918 919 /* next check if PMD loopback is on */ 920 if (enable) { 921 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_pmd_loopback_get(&pm_phy_copy.access, &lb_enable)); 922 if (lb_enable) enable = 0; 923 } 924 925 if(enable) { 926 *tx_control = phymodTxSquelchOn; 927 } else { 928 PHYMOD_IF_ERR_RETURN(temod2pll_tx_lane_control_get(&pm_phy_copy.access, &reset, &tx_lane)); 929 if (!reset) { 930 *tx_control = phymodTxReset; 931 } else if (!tx_lane) { 932 *tx_control = phymodTxTrafficDisable; 933 } else { 934 *tx_control = phymodTxTrafficEnable; 935 } 936 } 937 return PHYMOD_E_NONE; 938 } 939 940 941 int tsce_dpll_phy_rx_lane_control_set(const phymod_phy_access_t* phy, phymod_phy_rx_lane_control_t rx_control) 942 { 943 phymod_phy_access_t pm_phy_copy; 944 int start_lane, num_lane, i; 945 946 PHYMOD_MEMCPY(&pm_phy_copy, phy, sizeof(pm_phy_copy)); 947 TSCE_DPLL_PHY_ACCESS_PLLIDX_SET(&pm_phy_copy); 948 /* next program the tx fir taps and driver current based on the input */ 949 PHYMOD_IF_ERR_RETURN 950 (phymod_util_lane_config_get(&phy->access, &start_lane, &num_lane)); 951 952 pm_phy_copy.access.lane_mask = 0x1 << start_lane; 953 954 switch (rx_control) { 955 case phymodRxReset: 956 PHYMOD_IF_ERR_RETURN(temod2pll_rx_lane_control_set(&phy->access, 1)); 957 break; 958 case phymodRxSquelchOn: 959 for (i = 0; i < num_lane; i++) { 960 if (!PHYMOD_LANEPBMP_MEMBER(phy->access.lane_mask, start_lane + i)) { 961 continue; 962 } 963 pm_phy_copy.access.lane_mask = 1 << (start_lane + i); 964 PHYMOD_IF_ERR_RETURN(temod2pll_rx_squelch_set(&pm_phy_copy.access, 1)); 965 } 966 break; 967 case phymodRxSquelchOff: 968 for (i = 0; i < num_lane; i++) { 969 if (!PHYMOD_LANEPBMP_MEMBER(phy->access.lane_mask, start_lane + i)) { 970 continue; 971 } 972 pm_phy_copy.access.lane_mask = 1 << (start_lane + i); 973 PHYMOD_IF_ERR_RETURN(temod2pll_rx_squelch_set(&pm_phy_copy.access, 0)); 974 } 975 break; 976 default: 977 break; 978 } 979 return PHYMOD_E_NONE; 980 } 981 982 int tsce_dpll_phy_rx_lane_control_get(const phymod_phy_access_t* phy, phymod_phy_rx_lane_control_t* rx_control) 983 { 984 int enable, reset; 985 uint32_t lb_enable; 986 phymod_phy_access_t pm_phy_copy; 987 int start_lane, num_lane; 988 989 PHYMOD_MEMCPY(&pm_phy_copy, phy, sizeof(pm_phy_copy)); 990 TSCE_DPLL_PHY_ACCESS_PLLIDX_SET(&pm_phy_copy); 991 /* next program the tx fir taps and driver current based on the input */ 992 PHYMOD_IF_ERR_RETURN 993 (phymod_util_lane_config_get(&phy->access, &start_lane, &num_lane)); 994 995 pm_phy_copy.access.lane_mask = 0x1 << start_lane; 996 997 PHYMOD_IF_ERR_RETURN(temod2pll_rx_squelch_get(&pm_phy_copy.access, &enable)); 998 /* next check if PMD loopback is on */ 999 if (enable) { 1000 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_pmd_loopback_get(&pm_phy_copy.access, &lb_enable)); 1001 if (lb_enable) enable = 0; 1002 } 1003 if(enable) { 1004 *rx_control = phymodRxSquelchOn; 1005 } else { 1006 PHYMOD_IF_ERR_RETURN(temod2pll_rx_lane_control_get(&pm_phy_copy.access, &reset)); 1007 if (reset == 0) { 1008 *rx_control = phymodRxReset; 1009 } else { 1010 *rx_control = phymodRxSquelchOff; 1011 } 1012 } 1013 return PHYMOD_E_NONE; 1014 } 1015 1016 1017 int tsce_dpll_phy_fec_enable_set(const phymod_phy_access_t* phy, uint32_t enable) 1018 { 1019 int i, start_lane, num_lane; 1020 phymod_phy_access_t phy_copy; 1021 if ((phy->access.lane_mask == 0xf) || 1022 (phy->access.lane_mask == 0xc) || 1023 (phy->access.lane_mask == 0x3)) { 1024 PHYMOD_IF_ERR_RETURN(temod2pll_fecmode_set(&phy->access, enable)); 1025 } else { 1026 PHYMOD_IF_ERR_RETURN 1027 (phymod_util_lane_config_get(&phy->access, &start_lane, &num_lane)); 1028 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 1029 TSCE_DPLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 1030 1031 for (i = 0; i < num_lane; i++) { 1032 if (!PHYMOD_LANEPBMP_MEMBER(phy->access.lane_mask, start_lane + i)) { 1033 continue; 1034 } 1035 phy_copy.access.lane_mask = 1 << (start_lane + i); 1036 PHYMOD_IF_ERR_RETURN(temod2pll_fecmode_set(&phy_copy.access, enable)); 1037 } 1038 } 1039 return PHYMOD_E_NONE; 1040 1041 } 1042 1043 int tsce_dpll_phy_fec_enable_get(const phymod_phy_access_t* phy, uint32_t* enable) 1044 { 1045 PHYMOD_IF_ERR_RETURN(temod2pll_fecmode_get(&phy->access, enable)); 1046 return PHYMOD_E_NONE; 1047 1048 } 1049 1050 STATIC 1051 int _tsce_dpll_pll_multiplier_get(uint32_t pll_div, uint32_t *pll_multiplier) 1052 { 1053 switch (pll_div) { 1054 case 0x0: 1055 *pll_multiplier = 46; 1056 break; 1057 case 0x1: 1058 *pll_multiplier = 72; 1059 break; 1060 case TEMOD2PLL_PLL_MODE_DIV_40: 1061 *pll_multiplier = 40; 1062 break; 1063 case TEMOD2PLL_PLL_MODE_DIV_42: 1064 *pll_multiplier = 42; 1065 break; 1066 case TEMOD2PLL_PLL_MODE_DIV_48: 1067 *pll_multiplier = 48; 1068 break; 1069 case 0x5: 1070 *pll_multiplier = 50; 1071 break; 1072 case TEMOD2PLL_PLL_MODE_DIV_52: 1073 *pll_multiplier = 52; 1074 break; 1075 case TEMOD2PLL_PLL_MODE_DIV_54: 1076 *pll_multiplier = 54; 1077 break; 1078 case TEMOD2PLL_PLL_MODE_DIV_60: 1079 *pll_multiplier = 60; 1080 break; 1081 case TEMOD2PLL_PLL_MODE_DIV_64: 1082 *pll_multiplier = 64; 1083 break; 1084 case TEMOD2PLL_PLL_MODE_DIV_66: 1085 *pll_multiplier = 66; 1086 break; 1087 case 0xb: 1088 *pll_multiplier = 68; 1089 break; 1090 case TEMOD2PLL_PLL_MODE_DIV_70: 1091 *pll_multiplier = 70; 1092 break; 1093 case TEMOD2PLL_PLL_MODE_DIV_80: 1094 *pll_multiplier = 80; 1095 break; 1096 case TEMOD2PLL_PLL_MODE_DIV_92: 1097 *pll_multiplier = 92; 1098 break; 1099 case 0xf: 1100 *pll_multiplier = 100; 1101 break; 1102 case TEMOD2PLL_PLL_MODE_DIV_82P5: 1103 *pll_multiplier = 82; 1104 break; 1105 case TEMOD2PLL_PLL_MODE_DIV_87P5: 1106 *pll_multiplier = 87; 1107 break; 1108 default: 1109 *pll_multiplier = 66; 1110 break; 1111 } 1112 return PHYMOD_E_NONE; 1113 } 1114 int tsce_dpll_phy_autoneg_oui_set(const phymod_phy_access_t* phy, phymod_autoneg_oui_t an_oui) 1115 { 1116 temod2pll_an_oui_t oui; 1117 1118 oui.oui = an_oui.oui; 1119 oui.oui_override_hpam_adv = an_oui.oui_override_hpam_adv; 1120 oui.oui_override_hpam_det = an_oui.oui_override_hpam_det; 1121 oui.oui_override_bam73_adv = an_oui.oui_override_bam73_adv; 1122 oui.oui_override_bam73_det = an_oui.oui_override_bam73_det; 1123 oui.oui_override_bam37_adv = an_oui.oui_override_bam37_adv; 1124 oui.oui_override_bam37_det = an_oui.oui_override_bam37_det; 1125 1126 PHYMOD_IF_ERR_RETURN(temod2pll_an_oui_set(&phy->access, oui)); 1127 1128 return PHYMOD_E_NONE; 1129 } 1130 1131 int tsce_dpll_phy_autoneg_oui_get(const phymod_phy_access_t* phy, phymod_autoneg_oui_t* an_oui) 1132 { 1133 temod2pll_an_oui_t oui; 1134 1135 PHYMOD_IF_ERR_RETURN(temod2pll_an_oui_get(&phy->access, &oui)); 1136 1137 an_oui->oui_override_hpam_adv = oui.oui_override_hpam_adv; 1138 an_oui->oui_override_hpam_det = oui.oui_override_hpam_det; 1139 an_oui->oui_override_bam73_adv = oui.oui_override_bam73_adv; 1140 an_oui->oui_override_bam73_det = oui.oui_override_bam73_det; 1141 an_oui->oui_override_bam37_adv = oui.oui_override_bam37_adv; 1142 an_oui->oui_override_bam37_det = oui.oui_override_bam37_det; 1143 1144 return PHYMOD_E_NONE; 1145 } 1146 1147 1148 int tsce_dpll_phy_eee_set(const phymod_phy_access_t* phy, uint32_t enable) 1149 { 1150 uint32_t lpi_bypass; 1151 int rv = PHYMOD_E_NONE ; 1152 lpi_bypass = PHYMOD_LPI_BYPASS_GET(enable); 1153 enable &= 0x1; 1154 if (lpi_bypass) { 1155 rv = temod2pll_eee_control_set(&phy->access,enable); 1156 } else { 1157 return PHYMOD_E_UNAVAIL; 1158 } 1159 return rv; 1160 } 1161 1162 int tsce_dpll_phy_eee_get(const phymod_phy_access_t* phy, uint32_t* enable) 1163 { 1164 if (PHYMOD_LPI_BYPASS_GET(*enable)) { 1165 PHYMOD_IF_ERR_RETURN(temod2pll_eee_control_get(&phy->access, enable)); 1166 PHYMOD_LPI_BYPASS_SET(*enable); 1167 } else { 1168 return PHYMOD_E_UNAVAIL; 1169 } 1170 return PHYMOD_E_NONE; 1171 } 1172 1173 STATIC 1174 int _tsce_dpll_pll_to_vco_rate(uint32_t pll_div, phymod_ref_clk_t ref_clk, uint32_t *vco_rate) 1175 { 1176 uint32_t pll_multiplier; 1177 1178 PHYMOD_IF_ERR_RETURN 1179 (_tsce_dpll_pll_multiplier_get(pll_div, &pll_multiplier)); 1180 /* update the VCO rate properly */ 1181 switch (ref_clk) { 1182 case phymodRefClk156Mhz: 1183 *vco_rate = pll_multiplier * 156 + pll_multiplier * 25 / 100; 1184 break; 1185 case phymodRefClk125Mhz: 1186 *vco_rate = pll_multiplier * 125; 1187 if ((pll_multiplier == 82) || (pll_multiplier == 87)) { 1188 *vco_rate = pll_multiplier * 125 + 62; 1189 } 1190 break; 1191 default: 1192 *vco_rate = pll_multiplier * 156 + pll_multiplier * 25 / 100; 1193 break; 1194 } 1195 1196 return PHYMOD_E_NONE; 1197 } 1198 1199 int _tsce_dpll_phy_pll_config(const phymod_phy_access_t* phy, uint32_t new_pll_div, phymod_ref_clk_t ref_clk, uint8_t pll_index) 1200 { 1201 phymod_phy_access_t pm_phy_copy; 1202 phymod_firmware_core_config_t firmware_core_config; 1203 uint32_t vco_rate; 1204 int start_lane =0, num_lane; 1205 PHYMOD_MEMSET(&firmware_core_config, 0x0, sizeof(firmware_core_config)); 1206 1207 PHYMOD_MEMCPY(&pm_phy_copy, phy, sizeof(pm_phy_copy)); 1208 pm_phy_copy.access.pll_idx = pll_index; 1209 1210 PHYMOD_IF_ERR_RETURN 1211 (phymod_util_lane_config_get(&phy->access, &start_lane, &num_lane)); 1212 1213 firmware_core_config.CoreConfigFromPCS = 0; 1214 1215 /* Change in PLL, so reset all the ports first. Check for TSC12 */ 1216 temod2pll_disable_set(&pm_phy_copy.access); 1217 1218 PHYMOD_IF_ERR_RETURN 1219 (eagle2_tsc2pll_core_soft_reset_release(&pm_phy_copy.access, 0)); 1220 1221 /* release the uc reset */ 1222 PHYMOD_IF_ERR_RETURN 1223 (eagle2_uc_reset(&pm_phy_copy.access ,1)); 1224 1225 /* set the PLL divider */ 1226 PHYMOD_IF_ERR_RETURN 1227 (temod2pll_pll_config_set(&pm_phy_copy.access, new_pll_div, ref_clk)); 1228 1229 PHYMOD_IF_ERR_RETURN 1230 (_tsce_dpll_pll_to_vco_rate(new_pll_div, ref_clk, &vco_rate)); 1231 1232 firmware_core_config.VcoRate = (vco_rate - 5750) / 250 + 1; 1233 1234 /* change the master port num to the current caller port */ 1235 PHYMOD_IF_ERR_RETURN 1236 (temod2pll_master_port_num_set(&pm_phy_copy.access, start_lane)); 1237 1238 PHYMOD_IF_ERR_RETURN 1239 (temod2pll_pll_reset_enable_set(&pm_phy_copy.access, 1)); 1240 1241 /* update the firmware config properly */ 1242 PHYMOD_IF_ERR_RETURN 1243 (tsce_dpll_phy_firmware_core_config_set(&pm_phy_copy, firmware_core_config)); 1244 PHYMOD_IF_ERR_RETURN 1245 (eagle2_tsc2pll_core_soft_reset_release(&pm_phy_copy.access, 1)); 1246 1247 return PHYMOD_E_NONE; 1248 } 1249 1250 int _tsce_dpll_phy_pll_select(const phymod_phy_access_t *phy, uint8_t pll_select) 1251 { 1252 int i, start_lane=0, num_lane; 1253 phymod_phy_access_t pm_phy_copy; 1254 1255 PHYMOD_MEMCPY(&pm_phy_copy, phy, sizeof(pm_phy_copy)); 1256 PHYMOD_IF_ERR_RETURN 1257 (phymod_util_lane_config_get(&phy->access, &start_lane, &num_lane)); 1258 1259 for (i = 0; i < num_lane; i++) { 1260 if (!PHYMOD_LANEPBMP_MEMBER(phy->access.lane_mask, start_lane + i)) { 1261 continue; 1262 } 1263 PHYMOD_IF_ERR_RETURN 1264 (temod2pll_pll_select(&pm_phy_copy.access, pll_select)); 1265 } 1266 1267 return PHYMOD_E_NONE; 1268 } 1269 int _tsce_dpll_phy_pll_set(const phymod_phy_access_t* phy, uint32_t new_div, phymod_ref_clk_t ref_clk, uint8_t* pll_select) 1270 { 1271 uint32_t current_div0, current_div1,new_pll_multiplier, pll_multiplier_0, pll_multiplier_1; 1272 int start_lane=0, num_lane; 1273 phymod_phy_access_t pm_phy_copy; 1274 uint8_t pll_index_temp = 0; 1275 temod2pll_pll_mode_type pll_mode; 1276 1277 PHYMOD_MEMCPY(&pm_phy_copy, phy, sizeof(pm_phy_copy)); 1278 TSCE_DPLL_PHY_ACCESS_PLLIDX_SET(&pm_phy_copy); 1279 PHYMOD_IF_ERR_RETURN 1280 (phymod_util_lane_config_get(&phy->access, &start_lane, &num_lane)); 1281 PHYMOD_IF_ERR_RETURN 1282 (_tsce_dpll_pll_multiplier_get(new_div, &new_pll_multiplier)); 1283 1284 /* get the current PLL0 and PLL1 setting */ 1285 pll_index_temp = pm_phy_copy.access.pll_idx; 1286 pm_phy_copy.access.lane_mask = 1 << start_lane; 1287 pm_phy_copy.access.pll_idx = 0; 1288 PHYMOD_IF_ERR_RETURN 1289 (temod2pll_pll_config_get(&pm_phy_copy.access, &pll_mode)); 1290 current_div0 = (uint32_t) pll_mode; 1291 pm_phy_copy.access.pll_idx = 1; 1292 PHYMOD_IF_ERR_RETURN 1293 (temod2pll_pll_config_get(&pm_phy_copy.access, &pll_mode)); 1294 current_div1 = (uint32_t) pll_mode; 1295 pm_phy_copy.access.pll_idx = pll_index_temp; 1296 1297 PHYMOD_IF_ERR_RETURN 1298 (_tsce_dpll_pll_multiplier_get(current_div0, &pll_multiplier_0)); 1299 PHYMOD_IF_ERR_RETURN 1300 (_tsce_dpll_pll_multiplier_get(current_div1, &pll_multiplier_1)); 1301 /* 1302 a)PLL0 is always programmed with the highest VCO frequency vs. PLL1. 1303 b)PLL1 only can be configured to 6.25G 1304 c) No flexing of PLL VCO frequency will be supported. If one of the 2 PLLs needs to be reconfigured, all 4 ports need to be brought down. 1305 d) The lane has to be in reset before the field can be reconfigured to select a different PLL. 1306 */ 1307 /*Compare the new div with the current divs , if new div equal to any one of the dual pll 1308 then select the pll for the lane 1309 */ 1310 if (new_div == current_div0 || new_div == current_div1) { 1311 if((new_div == current_div0) && (pm_phy_copy.access.pll_idx != 0)){ 1312 /*select pll0*/ 1313 PHYMOD_IF_ERR_RETURN 1314 (_tsce_dpll_phy_pll_select(phy, 0)); 1315 *pll_select = 0; 1316 } 1317 if((new_div == current_div1) && pm_phy_copy.access.pll_idx != 1) { 1318 /*select pll1*/ 1319 PHYMOD_IF_ERR_RETURN 1320 (_tsce_dpll_phy_pll_select(phy, 1)); 1321 *pll_select = 1; 1322 } 1323 return PHYMOD_E_NONE; 1324 } 1325 /*Else need to compare the current pll with pll1*/ 1326 /*PLL1 must be configured to 6.25G , and pll0 must higher than pll1. If new pll lower than pll1, it`s a illegal div*/ 1327 if (new_pll_multiplier < pll_multiplier_1) { 1328 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_CONFIG, 1329 (_PHYMOD_MSG("this div %d is not supported at this ref clock %d"), 1330 new_pll_multiplier, ref_clk)); 1331 /*IF the new pll higher than pll1, then select pll0 and re-configure pll0*/ 1332 } else { 1333 /*select pll0 then configure pll0*/ 1334 PHYMOD_IF_ERR_RETURN 1335 (_tsce_dpll_phy_pll_select(phy, 0)); 1336 *pll_select = 0; 1337 /*reconfig pll0 with new_div*/ 1338 PHYMOD_IF_ERR_RETURN 1339 (_tsce_dpll_phy_pll_config(phy, new_div, ref_clk, 0)); 1340 } 1341 1342 return PHYMOD_E_NONE; 1343 } 1344 int tsce_dpll_phy_interface_config_set(const phymod_phy_access_t* phy, uint32_t flags, const phymod_phy_inf_config_t* config) 1345 { 1346 uint32_t new_pll_div=0; 1347 uint16_t new_speed_vec=0; 1348 int16_t new_os_mode =-1; 1349 temod2pll_spd_intfc_type spd_intf = TEMOD2PLL_SPD_ILLEGAL; 1350 phymod_phy_access_t pm_phy_copy; 1351 int start_lane=0, num_lane, i; 1352 uint32_t os_dfeon=0; 1353 uint32_t scrambling_dis=0; 1354 uint32_t u_os_mode = 0; 1355 int dfe_adjust = -1 ; 1356 uint32_t vco_rate; 1357 uint32_t new_pll_div_enum; 1358 int cl72_allowed=0, cl72_req=0, high_vco_1G = 1; 1359 phymod_phy_inf_config_t temp_config; 1360 uint8_t pll_select; 1361 1362 /* sc_table_entry exp_entry; RAVI */ 1363 phymod_firmware_lane_config_t firmware_lane_config; 1364 phymod_firmware_core_config_t firmware_core_config; 1365 1366 PHYMOD_MEMCPY(&pm_phy_copy, phy, sizeof(pm_phy_copy)); 1367 TSCE_DPLL_PHY_ACCESS_PLLIDX_SET(&pm_phy_copy); 1368 PHYMOD_MEMSET(&firmware_lane_config, 0x0, sizeof(firmware_lane_config)); 1369 PHYMOD_MEMSET(&firmware_core_config, 0x0, sizeof(firmware_core_config)); 1370 PHYMOD_MEMSET(&temp_config, 0x0, sizeof(temp_config)); 1371 1372 firmware_lane_config.MediaType = 0; 1373 1374 /* next program the tx fir taps and driver current based on the input */ 1375 PHYMOD_IF_ERR_RETURN 1376 (phymod_util_lane_config_get(&phy->access, &start_lane, &num_lane)); 1377 1378 /* reset pcs */ 1379 temod2pll_disable_set(&phy->access); 1380 1381 /* Hold the per lne soft reset bit */ 1382 for (i = 0; i < num_lane; i++) { 1383 if (!PHYMOD_LANEPBMP_MEMBER(phy->access.lane_mask, start_lane + i)) { 1384 continue; 1385 } 1386 pm_phy_copy.access.lane_mask = 1 << (start_lane + i); 1387 PHYMOD_IF_ERR_RETURN 1388 (eagle2_tsc2pll_lane_soft_reset_release(&pm_phy_copy.access, 0)); 1389 } 1390 /* deassert pmd_tx_disable_pin_dis if it is set by ILKn */ 1391 /* remove pmd_tx_disable_pin_dis it may be asserted because of ILKn */ 1392 if(config->interface_type != phymodInterfaceBypass) { 1393 for (i = 0; i < num_lane; i++) { 1394 if (!PHYMOD_LANEPBMP_MEMBER(phy->access.lane_mask, start_lane + i)) { 1395 continue; 1396 } 1397 pm_phy_copy.access.lane_mask = 1 << (start_lane + i); 1398 PHYMOD_IF_ERR_RETURN 1399 (eagle2_tsc2pll_pmd_tx_disable_pin_dis_set(&phy->access, 0)); 1400 } 1401 } 1402 /* disable CL72 */ 1403 for (i = 0; i < num_lane; i++) { 1404 if (!PHYMOD_LANEPBMP_MEMBER(phy->access.lane_mask, start_lane + i)) { 1405 continue; 1406 } 1407 pm_phy_copy.access.lane_mask = 1 << (start_lane + i); 1408 PHYMOD_IF_ERR_RETURN 1409 (temod2pll_clause72_control(&pm_phy_copy.access, 0|TEMOD2PLL_CL72_CONTROL_NO_TRIGER)) ; 1410 } 1411 1412 pm_phy_copy.access.lane_mask = 0x1 << start_lane; 1413 PHYMOD_IF_ERR_RETURN 1414 (tsce_dpll_phy_firmware_lane_config_get(&pm_phy_copy, &firmware_lane_config)); 1415 1416 /* make sure that an and config from pcs is off */ 1417 firmware_core_config.CoreConfigFromPCS = 0; 1418 firmware_lane_config.AnEnabled = 0; 1419 firmware_lane_config.LaneConfigFromPCS = 0; 1420 1421 /* and also make sure the cl72 restart timeout is enabled */ 1422 firmware_lane_config.Cl72RestTO = 1; 1423 firmware_lane_config.Cl72AutoPolEn = 0; 1424 if (PHYMOD_INTF_MODES_FIBER_GET(config)) { 1425 firmware_lane_config.MediaType = phymodFirmwareMediaTypeOptics; 1426 } else if (PHYMOD_INTF_MODES_COPPER_GET(config)) { 1427 firmware_lane_config.MediaType = phymodFirmwareMediaTypeCopperCable; 1428 } else { 1429 firmware_lane_config.MediaType = phymodFirmwareMediaTypePcbTraceBackPlane; 1430 } 1431 1432 PHYMOD_IF_ERR_RETURN 1433 (temod2pll_update_port_mode(&phy->access)); 1434 1435 spd_intf = TEMOD2PLL_SPD_10_X1_SGMII; /* to prevent undefinded TEMOD2PLL_SPD_ILLEGAL accessing tables */ 1436 1437 /* find the speed */ 1438 if (config->interface_type == phymodInterfaceXFI) { 1439 firmware_lane_config.MediaType = phymodFirmwareMediaTypePcbTraceBackPlane; 1440 } else if(config->interface_type == phymodInterfaceSFI) { 1441 firmware_lane_config.MediaType = phymodFirmwareMediaTypeOptics; 1442 } else if(config->interface_type == phymodInterfaceSFPDAC) { 1443 firmware_lane_config.MediaType = phymodFirmwareMediaTypeCopperCable; 1444 } else if(config->interface_type == phymodInterface1000X) { 1445 firmware_lane_config.MediaType = phymodFirmwareMediaTypeOptics; 1446 } else if(config->interface_type == phymodInterfaceSGMII) { 1447 firmware_lane_config.MediaType = phymodFirmwareMediaTypePcbTraceBackPlane; 1448 } else if(config->interface_type == phymodInterfaceLR) { 1449 firmware_lane_config.MediaType = phymodFirmwareMediaTypeOptics; 1450 } else if(config->interface_type == phymodInterfaceSR) { 1451 firmware_lane_config.MediaType = phymodFirmwareMediaTypeOptics; 1452 } 1453 1454 cl72_req = (flags & (PHYMOD_INTF_F_CL72_REQUESTED_BY_CNFG|PHYMOD_INTF_F_CL72_REQUESTED_BY_API))?1:0; 1455 switch(config->data_rate) { 1456 case 10: 1457 if(config->pll_divider_req==40) { 1458 spd_intf = TEMOD2PLL_SPD_10_SGMII; 1459 high_vco_1G = 0; 1460 } else { 1461 spd_intf = TEMOD2PLL_SPD_10_X1_SGMII; 1462 } 1463 break; 1464 case 100: 1465 if(config->pll_divider_req==40) { 1466 spd_intf = TEMOD2PLL_SPD_100_SGMII; 1467 high_vco_1G = 0; 1468 } else { 1469 spd_intf = TEMOD2PLL_SPD_100_X1_SGMII; 1470 } 1471 break; 1472 case 1000: 1473 if(config->pll_divider_req==40) { 1474 spd_intf = TEMOD2PLL_SPD_1000_SGMII; 1475 high_vco_1G = 0; 1476 } else { 1477 spd_intf = TEMOD2PLL_SPD_1000_X1_SGMII; 1478 } 1479 break; 1480 case 2500: 1481 spd_intf = TEMOD2PLL_SPD_2500; 1482 high_vco_1G = 0; 1483 break; 1484 case 5000: 1485 if (config->interface_type == phymodInterfaceRXAUI) { 1486 temod2pll_credit_override_set(&phy->access, TEMOD2PLL_CREDIT_MAC, 0x4); 1487 new_os_mode = TEMOD2PLL_PMA_OS_MODE_2; 1488 if (PHYMOD_INTF_MODES_SCR_GET(config)) { 1489 spd_intf = TEMOD2PLL_SPD_10000_DXGXS_SCR; 1490 } else { 1491 spd_intf = TEMOD2PLL_SPD_10000_DXGXS; 1492 } 1493 } else if (PHYMOD_INTF_MODES_HIGIG_GET(config)) { 1494 if(config->pll_divider_req==40) { 1495 spd_intf = TEMOD2PLL_SPD_5000; 1496 } else { 1497 spd_intf = TEMOD2PLL_SPD_5000_XFI; 1498 } 1499 } else { 1500 if(config->pll_divider_req==40) { 1501 spd_intf = TEMOD2PLL_SPD_5000; 1502 } else { 1503 spd_intf = TEMOD2PLL_SPD_5000_XFI; 1504 } 1505 } 1506 break; 1507 case 10000: 1508 if (config->interface_type == phymodInterfaceXAUI) { 1509 spd_intf = TEMOD2PLL_SPD_10000; 1510 firmware_lane_config.MediaType = phymodFirmwareMediaTypePcbTraceBackPlane; 1511 } else if (config->interface_type == phymodInterfaceRXAUI) { 1512 if (PHYMOD_INTF_MODES_HIGIG_GET(config)) { 1513 if (PHYMOD_INTF_MODES_SCR_GET(config)) { 1514 spd_intf = TEMOD2PLL_SPD_10000_HI_DXGXS_SCR; 1515 } else { 1516 spd_intf = TEMOD2PLL_SPD_10000_HI_DXGXS; 1517 } 1518 } else { 1519 if (PHYMOD_INTF_MODES_SCR_GET(config)) { 1520 spd_intf = TEMOD2PLL_SPD_10000_DXGXS_SCR; 1521 } else { 1522 spd_intf = TEMOD2PLL_SPD_10000_DXGXS; 1523 } 1524 } 1525 firmware_lane_config.MediaType = phymodFirmwareMediaTypePcbTraceBackPlane; 1526 } else if(config->interface_type == phymodInterfaceX2) { 1527 spd_intf = TEMOD2PLL_SPD_10000_X2; 1528 } else { 1529 cl72_allowed = 1 ; 1530 if (config->interface_type == phymodInterfaceSFI) { 1531 spd_intf = TEMOD2PLL_SPD_10000_XFI; 1532 dfe_adjust = 0 ; 1533 } else if(config->interface_type == phymodInterfaceXFI) { 1534 spd_intf = TEMOD2PLL_SPD_10000_XFI; 1535 dfe_adjust = 0 ; 1536 } else if(config->interface_type == phymodInterfaceXGMII) { 1537 spd_intf = TEMOD2PLL_SPD_10000; 1538 } else { 1539 spd_intf = TEMOD2PLL_SPD_10000_XFI; 1540 if (PHYMOD_INTF_MODES_FIBER_GET(config)) { 1541 dfe_adjust = 0 ; 1542 } 1543 } 1544 } 1545 break; 1546 case 10500: 1547 /* TEMOD2PLL_SPD_10500_HI is 4-lane port */ 1548 spd_intf = TEMOD2PLL_SPD_10500_HI; 1549 break; 1550 case 11000: 1551 cl72_allowed = 1 ; 1552 if (PHYMOD_INTF_MODES_HIGIG_GET(config)) { 1553 spd_intf = TEMOD2PLL_SPD_10600_XFI_HG; 1554 } else { 1555 spd_intf = TEMOD2PLL_SPD_10000_XFI; 1556 } 1557 break; 1558 case 12000: 1559 cl72_allowed = 1 ; 1560 spd_intf = TEMOD2PLL_SPD_12P12_XFI; 1561 break; 1562 case 20000: 1563 if(config->interface_type == phymodInterfaceKR2) { 1564 firmware_lane_config.MediaType = phymodFirmwareMediaTypePcbTraceBackPlane; 1565 cl72_allowed = 1 ; 1566 spd_intf = TEMOD2PLL_SPD_20G_MLD_DXGXS ; 1567 } else if(config->interface_type == phymodInterfaceCR2) { 1568 firmware_lane_config.MediaType = phymodFirmwareMediaTypeCopperCable; 1569 cl72_allowed = 1 ; 1570 spd_intf = TEMOD2PLL_SPD_20G_MLD_DXGXS ; 1571 } else if(config->interface_type == phymodInterfaceRXAUI) { 1572 cl72_allowed = 1 ; 1573 spd_intf = TEMOD2PLL_SPD_20G_DXGXS; 1574 } else { 1575 if (PHYMOD_INTF_MODES_SCR_GET(config)) { 1576 spd_intf = TEMOD2PLL_SPD_20000_SCR; 1577 } else { 1578 spd_intf = TEMOD2PLL_SPD_20000; 1579 } 1580 } 1581 break; 1582 case 21000: 1583 if(config->interface_type == phymodInterfaceRXAUI) { 1584 cl72_allowed = 1 ; 1585 spd_intf = TEMOD2PLL_SPD_21P21G_HG_DXGXS; 1586 } else if(config->interface_type == phymodInterfaceKR2 || 1587 config->interface_type == phymodInterfaceCR2) { 1588 spd_intf = TEMOD2PLL_SPD_21G_HI_MLD_DXGXS; 1589 } else { 1590 spd_intf = TEMOD2PLL_SPD_21000; 1591 } 1592 break; 1593 case 24000: 1594 cl72_allowed = 1; 1595 spd_intf = TEMOD2PLL_SPD_24P24_MLD_DXGXS; 1596 break; 1597 case 25000: 1598 if (num_lane == 2) { 1599 cl72_allowed = 1 ; 1600 spd_intf = TEMOD2PLL_SPD_20G_MLD_DXGXS ; 1601 } else { 1602 spd_intf = TEMOD2PLL_SPD_25455 ; 1603 } 1604 break; 1605 case 25450: 1606 spd_intf = TEMOD2PLL_SPD_25455 ; 1607 break; 1608 case 30000: 1609 case 32000: 1610 spd_intf = TEMOD2PLL_SPD_31500; 1611 break; 1612 case 40000: 1613 cl72_allowed = 1 ; 1614 spd_intf = TEMOD2PLL_SPD_40G_XLAUI; 1615 if (config->interface_type == phymodInterfaceXLAUI) { 1616 firmware_lane_config.MediaType = phymodFirmwareMediaTypePcbTraceBackPlane; 1617 dfe_adjust = 0 ; 1618 } else if(config->interface_type == phymodInterfaceSR4) { 1619 firmware_lane_config.MediaType = phymodFirmwareMediaTypeOptics ; 1620 dfe_adjust = 0 ; 1621 } else if(config->interface_type == phymodInterfaceCR4) { 1622 firmware_lane_config.MediaType = phymodFirmwareMediaTypeCopperCable ; 1623 } else if (config->interface_type == phymodInterfaceKR4) { 1624 firmware_lane_config.MediaType = phymodFirmwareMediaTypePcbTraceBackPlane; 1625 } else if((config->interface_type == phymodInterfaceXGMII) || PHYMOD_INTF_MODES_HIGIG_GET(config)) { 1626 spd_intf = TEMOD2PLL_SPD_40G_X4; 1627 } else { 1628 firmware_lane_config.MediaType = phymodFirmwareMediaTypePcbTraceBackPlane ; 1629 } 1630 break; 1631 case 42000: 1632 cl72_allowed = 1 ; 1633 if ((config->interface_type == phymodInterfaceKR4) && 1634 PHYMOD_INTF_MODES_HIGIG_GET(config)) { 1635 spd_intf = TEMOD2PLL_SPD_42G_XLAUI; 1636 }else if((config->interface_type == phymodInterfaceCR4) && 1637 PHYMOD_INTF_MODES_HIGIG_GET(config)) { 1638 spd_intf = TEMOD2PLL_SPD_42G_XLAUI; 1639 firmware_lane_config.MediaType = phymodFirmwareMediaTypeCopperCable; 1640 }else if((config->interface_type == phymodInterfaceXGMII) || PHYMOD_INTF_MODES_HIGIG_GET(config)) { 1641 spd_intf = TEMOD2PLL_SPD_42P42G_HG2; 1642 dfe_adjust = 1; 1643 } else { 1644 spd_intf = TEMOD2PLL_SPD_42G_XLAUI; 1645 } 1646 break; 1647 case 48000: 1648 cl72_allowed = 1 ; 1649 spd_intf = TEMOD2PLL_SPD_48P48_MLD; 1650 firmware_lane_config.MediaType = phymodFirmwareMediaTypePcbTraceBackPlane; 1651 dfe_adjust = 0 ; 1652 break; 1653 default: 1654 break; 1655 } 1656 1657 /* need to decide if we need to set low VCO for 2.5G,1G or below */ 1658 if (!high_vco_1G) { 1659 PHYMOD_IF_ERR_RETURN 1660 (temod2pll_cl37_high_vco_set(&pm_phy_copy.access, high_vco_1G)); 1661 } 1662 1663 if(PHYMOD_INTF_MODES_HIGIG_GET(config)) { 1664 PHYMOD_IF_ERR_RETURN 1665 (temod2pll_encode_set(&phy->access, spd_intf, 1)); 1666 PHYMOD_IF_ERR_RETURN 1667 (temod2pll_decode_set(&phy->access, spd_intf, 1)); 1668 } else { 1669 PHYMOD_IF_ERR_RETURN 1670 (temod2pll_encode_set(&phy->access, spd_intf, 0)); 1671 PHYMOD_IF_ERR_RETURN 1672 (temod2pll_decode_set(&phy->access, spd_intf, 0)); 1673 } 1674 1675 if(config->data_rate==10||config->data_rate==100|| 1676 config->data_rate==1000) { 1677 if (config->interface_type == phymodInterfaceSGMII) { 1678 firmware_lane_config.MediaType = phymodFirmwareMediaTypePcbTraceBackPlane; 1679 } 1680 if (config->interface_type == phymodInterface1000X) { 1681 firmware_lane_config.MediaType = phymodFirmwareMediaTypeOptics; 1682 } 1683 } 1684 1685 /*new pll_div getting*/ 1686 if(config->interface_type == phymodInterfaceBypass) { 1687 1688 PHYMOD_IF_ERR_RETURN 1689 (eagle2_tsc2pll_get_vco(config, &vco_rate, &new_pll_div_enum, &new_os_mode)); 1690 1691 PHYMOD_IF_ERR_RETURN 1692 (eagle2_tsc2pll_get_pll_div_from_enum(new_pll_div_enum, &new_pll_div)); 1693 1694 } else { 1695 1696 PHYMOD_IF_ERR_RETURN 1697 (temod2pll_plldiv_lkup_get(&phy->access, spd_intf, config->ref_clock, &new_pll_div, &new_speed_vec)); 1698 1699 /* For 12.12G, data rate specified is 12000, and pll_div is set pll_mode_div_80 */ 1700 if (config->ref_clock == phymodRefClk156Mhz) { 1701 switch(config->data_rate) { 1702 case 11000: new_pll_div = TEMOD2PLL_PLL_MODE_DIV_70; break ; 1703 case 12000: new_pll_div = TEMOD2PLL_PLL_MODE_DIV_80; break ; 1704 case 21000: 1705 if (num_lane == 2) { 1706 new_pll_div = TEMOD2PLL_PLL_MODE_DIV_70; 1707 } 1708 break ; 1709 case 25000: 1710 if (num_lane == 2) { 1711 new_pll_div = TEMOD2PLL_PLL_MODE_DIV_80; 1712 } 1713 break ; 1714 case 42000: new_pll_div = TEMOD2PLL_PLL_MODE_DIV_70; break ; 1715 case 48000: new_pll_div = TEMOD2PLL_PLL_MODE_DIV_80; break ; 1716 default: break ; 1717 } 1718 } 1719 } 1720 1721 if(new_os_mode>=0) { 1722 u_os_mode = new_os_mode | TEMOD2PLL_OVERRIDE_CFG ; 1723 } else { 1724 u_os_mode = 0 ; 1725 } 1726 1727 /* if pll change is enabled. new_pll_div is the reg vector value */ 1728 if(PHYMOD_INTF_F_DONT_TURN_OFF_PLL & flags){ 1729 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_CONFIG, 1730 (_PHYMOD_MSG("pll has to change for speed_set from %u but DONT_TURN_OFF_PLL flag is enabled"), 1731 (unsigned int)new_pll_div)); 1732 } 1733 1734 /* the speed is not supported */ 1735 if (new_pll_div == TEMOD2PLL_PLL_MODE_DIV_ILLEGAL) { 1736 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_CONFIG, 1737 (_PHYMOD_MSG("this speed %d is not supported at this ref clock %d"), 1738 config->data_rate, config->ref_clock)); 1739 } 1740 1741 /* pll switch is required and expected */ 1742 PHYMOD_IF_ERR_RETURN 1743 (_tsce_dpll_phy_pll_set(phy, new_pll_div, config->ref_clock, &pll_select)); 1744 pm_phy_copy.access.pll_idx = pll_select; 1745 pm_phy_copy.access.lane_mask = phy->access.lane_mask; 1746 1747 1748 PHYMOD_IF_ERR_RETURN 1749 (temod2pll_pmd_osmode_set(&pm_phy_copy.access, spd_intf, u_os_mode)); 1750 PHYMOD_IF_ERR_RETURN(temod2pll_osdfe_on_lkup_get(&phy->access, spd_intf, &os_dfeon)); 1751 PHYMOD_IF_ERR_RETURN(temod2pll_scrambling_dis_lkup_get(&phy->access, spd_intf, &scrambling_dis)); 1752 firmware_lane_config.DfeOn = 0; 1753 firmware_lane_config.ScramblingDisable = scrambling_dis; 1754 if(os_dfeon == 0x1) 1755 firmware_lane_config.DfeOn = 1; 1756 1757 if(dfe_adjust >=0) 1758 firmware_lane_config.DfeOn = dfe_adjust ; 1759 if(cl72_req&cl72_allowed){ 1760 for (i = 0; i < num_lane; i++) { 1761 if (!PHYMOD_LANEPBMP_MEMBER(phy->access.lane_mask, start_lane + i)) { 1762 continue; 1763 } 1764 pm_phy_copy.access.lane_mask = 1 << (start_lane + i); 1765 PHYMOD_IF_ERR_RETURN 1766 (temod2pll_clause72_control(&pm_phy_copy.access, 1|TEMOD2PLL_CL72_CONTROL_NO_TRIGER)) ; 1767 } 1768 } 1769 1770 if(config->interface_type != phymodInterfaceBypass) { 1771 if(flags & PHYMOD_INTF_F_SET_SPD_NO_TRIGGER) { 1772 (temod2pll_set_spd_intf(&phy->access, spd_intf, 1)); 1773 } else { 1774 PHYMOD_IF_ERR_RETURN 1775 (temod2pll_set_spd_intf(&phy->access, spd_intf, 0)); 1776 } 1777 } 1778 1779 /* TX Params are set outside this func */ 1780 /* change TX parameters if enabled */ 1781 /* if((PHYMOD_IF_F_DONT_OVERIDE_TX_PARAMS & flags) == 0) 1782 PHYMOD_IF_ERR_RETURN 1783 (tsce_phy_media_type_tx_get(phy, phymodMediaTypeMid, &tx_params)); 1784 PHYMOD_IF_ERR_RETURN 1785 (tsce_phy_tx_set(phy, &tx_params)); 1786 */ 1787 1788 for (i = 0; i < num_lane; i++) { 1789 if (!PHYMOD_LANEPBMP_MEMBER(phy->access.lane_mask, start_lane + i)) { 1790 continue; 1791 } 1792 pm_phy_copy.access.lane_mask = 0x1 << (start_lane + i); 1793 PHYMOD_IF_ERR_RETURN 1794 (_tsce_dpll_phy_firmware_lane_config_set(&pm_phy_copy, firmware_lane_config)); 1795 } 1796 1797 /* release the per lne soft reset bit */ 1798 for (i = 0; i < num_lane; i++) { 1799 if (!PHYMOD_LANEPBMP_MEMBER(phy->access.lane_mask, start_lane + i)) { 1800 continue; 1801 } 1802 pm_phy_copy.access.lane_mask = 1 << (start_lane + i); 1803 PHYMOD_IF_ERR_RETURN 1804 (eagle2_tsc2pll_lane_soft_reset_release(&pm_phy_copy.access, 1)); 1805 } 1806 return PHYMOD_E_NONE; 1807 } 1808 1809 STATIC 1810 int _tsce_dpll_speed_id_interface_config_get(const phymod_phy_access_t* phy, int speed_id, 1811 phymod_phy_inf_config_t* config, uint16_t an_enable, 1812 phymod_firmware_lane_config_t *lane_config) 1813 { 1814 int ilkn_set; 1815 int osr_mode; 1816 int hg_enable = 0; 1817 uint32_t vco_rate; 1818 uint32_t pll_multiplier; 1819 uint32_t current_pll_div=0; 1820 int u_os_mode = 0xff; 1821 uint32_t actual_osr, actual_osr_rem; 1822 phymod_osr_mode_t osr_mode_enum; 1823 temod2pll_pll_mode_type pll_mode; 1824 phymod_phy_access_t pm_phy_copy; 1825 PHYMOD_MEMCPY(&pm_phy_copy, phy, sizeof(pm_phy_copy)); 1826 TSCE_DPLL_PHY_ACCESS_PLLIDX_SET(&pm_phy_copy); 1827 1828 if (config->ref_clock == phymodRefClk125Mhz) { 1829 PHYMOD_IF_ERR_RETURN 1830 (temod2pll_pll_config_get(&pm_phy_copy.access, &pll_mode)); 1831 current_pll_div = (uint32_t) pll_mode; 1832 } else { 1833 PHYMOD_IF_ERR_RETURN 1834 (temod2pll_get_plldiv(&pm_phy_copy.access, ¤t_pll_div)); 1835 } 1836 1837 PHYMOD_IF_ERR_RETURN 1838 (temod2pll_hg_enable_get(&phy->access, &hg_enable)); 1839 1840 PHYMOD_IF_ERR_RETURN(temod2pll_pcs_ilkn_chk(&phy->access, &ilkn_set)); 1841 if(ilkn_set) { 1842 config->interface_type = phymodInterfaceBypass; 1843 PHYMOD_IF_ERR_RETURN 1844 (_tsce_dpll_pll_multiplier_get(current_pll_div, &pll_multiplier)); 1845 PHYMOD_IF_ERR_RETURN 1846 (eagle2_tsc2pll_osr_mode_get(&pm_phy_copy.access, &osr_mode)); 1847 1848 switch (config->ref_clock) { 1849 case phymodRefClk156Mhz: 1850 vco_rate = pll_multiplier * 156 + pll_multiplier * 25 / 100; 1851 break; 1852 case phymodRefClk125Mhz: 1853 vco_rate = pll_multiplier * 125; 1854 break; 1855 default: 1856 vco_rate = pll_multiplier * 156 + pll_multiplier * 25 / 100; 1857 break; 1858 } 1859 1860 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_osr_mode_to_enum(osr_mode, &osr_mode_enum)); 1861 PHYMOD_IF_ERR_RETURN(phymod_osr_mode_to_actual_os(osr_mode_enum, &actual_osr, &actual_osr_rem)); 1862 config->data_rate = vco_rate/actual_osr; 1863 } else { 1864 1865 switch (speed_id) { 1866 case 0x1: 1867 config->data_rate = 10; 1868 config->interface_type = phymodInterfaceSGMII; 1869 break; 1870 case 0x2: 1871 config->data_rate = 100; 1872 config->interface_type = phymodInterfaceSGMII; 1873 break; 1874 case 0x3: 1875 { 1876 if (lane_config->MediaType == phymodFirmwareMediaTypeOptics) { 1877 config->interface_type = phymodInterface1000X; 1878 } else { 1879 config->interface_type = phymodInterfaceSGMII; 1880 } 1881 config->data_rate = 1000; 1882 break; 1883 } 1884 case 0x4: 1885 config->data_rate = 1000; 1886 config->interface_type = phymodInterfaceCX; 1887 break; 1888 case 0x5: 1889 config->data_rate = 1000; 1890 config->interface_type = phymodInterfaceKX; 1891 break; 1892 case 0x6: 1893 { 1894 if (an_enable) { 1895 config->interface_type = phymodInterfaceKX; 1896 } else { 1897 if (lane_config->MediaType == phymodFirmwareMediaTypeOptics) { 1898 config->interface_type = phymodInterface1000X; 1899 } else { 1900 config->interface_type = phymodInterfaceSGMII; 1901 } 1902 } 1903 config->data_rate = 2500; 1904 break; 1905 } 1906 break; 1907 case 0x7: 1908 config->data_rate = 5000; 1909 config->interface_type = phymodInterface1000X; 1910 break; 1911 case 0x8: 1912 config->data_rate = 10000; 1913 config->interface_type = phymodInterfaceCX4; 1914 break; 1915 case 0x9: 1916 config->data_rate = 10000; 1917 config->interface_type = phymodInterfaceKX4; 1918 break; 1919 case 0xa: 1920 config->data_rate = 10000; 1921 config->interface_type = phymodInterfaceXGMII; 1922 break; 1923 case 0xb: 1924 config->data_rate = 13000; 1925 config->interface_type = phymodInterfaceXGMII; 1926 break; 1927 case 0xc: 1928 config->data_rate = 15000; 1929 config->interface_type = phymodInterfaceXGMII; 1930 break; 1931 case 0xd: 1932 config->data_rate = 16000; 1933 config->interface_type = phymodInterfaceXGMII; 1934 break; 1935 case 0xe: 1936 config->data_rate = 20000; 1937 config->interface_type = phymodInterfaceCX4; 1938 break; 1939 case 0xf: 1940 PHYMOD_IF_ERR_RETURN 1941 (temod2pll_pmd_osmode_get(&pm_phy_copy.access, &u_os_mode)); 1942 if(u_os_mode == TEMOD2PLL_PMA_OS_MODE_2) { 1943 config->data_rate = 5000; 1944 config->interface_type = phymodInterfaceRXAUI; 1945 } else { 1946 config->data_rate = 10000; 1947 config->interface_type = phymodInterfaceRXAUI; 1948 } 1949 break; 1950 case 0x10: 1951 PHYMOD_IF_ERR_RETURN 1952 (temod2pll_pmd_osmode_get(&pm_phy_copy.access, &u_os_mode)); 1953 if(u_os_mode == TEMOD2PLL_PMA_OS_MODE_2) { 1954 config->data_rate = 5000; 1955 config->interface_type = phymodInterfaceRXAUI; 1956 } else { 1957 config->data_rate = 10000; 1958 config->interface_type = phymodInterfaceX2; 1959 } 1960 break; 1961 case 0x11: 1962 config->data_rate = 20000; 1963 config->interface_type = phymodInterfaceXGMII; 1964 break; 1965 case 0x12: 1966 config->data_rate = 10500; 1967 config->interface_type = phymodInterfaceX2; 1968 break; 1969 case 0x13: 1970 config->data_rate = 21000; 1971 config->interface_type = phymodInterfaceCX4; 1972 break; 1973 case 0x14: 1974 config->data_rate = 13000; /* round up from 12700 */ 1975 config->interface_type = phymodInterfaceX2; 1976 break; 1977 case 0x15: 1978 config->data_rate = 25450; 1979 config->interface_type = phymodInterfaceKR4; 1980 break; 1981 case 0x16: 1982 config->data_rate = 15750; 1983 config->interface_type = phymodInterfaceX2; 1984 break; 1985 case 0x17: 1986 config->data_rate = 31500; 1987 config->interface_type = phymodInterfaceXGMII; 1988 break; 1989 case 0x18: 1990 config->data_rate = 31500; 1991 config->interface_type = phymodInterfaceKR4; 1992 break; 1993 case 0x19: 1994 config->data_rate = 20000; 1995 config->interface_type = phymodInterfaceCX2; 1996 break; 1997 case 0x1a: 1998 if (config->ref_clock == phymodRefClk125Mhz) { 1999 if(current_pll_div==TEMOD2PLL_PLL_MODE_DIV_87P5) { 2000 config->data_rate = 21000; 2001 } else { 2002 config->data_rate = 20000; 2003 } 2004 } else { 2005 if(current_pll_div==TEMOD2PLL_PLL_MODE_DIV_70) { 2006 config->data_rate = 21000; 2007 } else { 2008 config->data_rate = 20000; 2009 } 2010 } 2011 config->interface_type = phymodInterfaceX2; 2012 break; 2013 case 0x1b: /* digital_operationSpeeds_SPEED_40G_X4; BRCM */ 2014 if (config->ref_clock == phymodRefClk125Mhz) { 2015 if(current_pll_div==TEMOD2PLL_PLL_MODE_DIV_87P5) { 2016 config->data_rate = 42000; 2017 } else { 2018 config->data_rate = 40000; 2019 } 2020 } else { 2021 if(current_pll_div==TEMOD2PLL_PLL_MODE_DIV_70) { 2022 config->data_rate = 42000; 2023 } else { 2024 config->data_rate = 40000; 2025 } 2026 } 2027 config->interface_type = phymodInterfaceXGMII; 2028 break; 2029 case 0x1c: 2030 if (config->ref_clock == phymodRefClk125Mhz) { 2031 if(current_pll_div==TEMOD2PLL_PLL_MODE_DIV_100) { 2032 config->data_rate = 12000; 2033 } else if(current_pll_div==TEMOD2PLL_PLL_MODE_DIV_87P5) { 2034 config->data_rate = 11000; 2035 } else { 2036 config->data_rate = 10000; 2037 } 2038 } else { 2039 if(current_pll_div==TEMOD2PLL_PLL_MODE_DIV_80) { 2040 config->data_rate = 12000; 2041 } else if(current_pll_div==TEMOD2PLL_PLL_MODE_DIV_70) { 2042 config->data_rate = 11000; 2043 } else { 2044 config->data_rate = 10000; 2045 } 2046 } 2047 config->interface_type = phymodInterfaceKR; 2048 if(!an_enable) { 2049 if (lane_config->MediaType == phymodFirmwareMediaTypeOptics) { 2050 config->interface_type = phymodInterfaceSFI ; 2051 } else if (lane_config->MediaType == phymodFirmwareMediaTypeCopperCable) { 2052 config->interface_type = phymodInterfaceCR ; 2053 } else { 2054 config->interface_type = phymodInterfaceXFI ; 2055 } 2056 } 2057 break; 2058 case 0x1d: 2059 config->data_rate = 11000; 2060 if (lane_config->MediaType == phymodFirmwareMediaTypeOptics) { 2061 if(config->interface_type == phymodInterfaceSR) { 2062 config->interface_type = phymodInterfaceSR ; 2063 } else { 2064 config->interface_type = phymodInterfaceSFI ; 2065 } 2066 } else { 2067 config->interface_type = phymodInterfaceXFI ; 2068 } 2069 break; 2070 case 0x1e: 2071 if (config->ref_clock == phymodRefClk125Mhz) { 2072 if(current_pll_div == TEMOD2PLL_PLL_MODE_DIV_100) { 2073 config->data_rate = 25000; 2074 } else if(current_pll_div == TEMOD2PLL_PLL_MODE_DIV_87P5) { 2075 config->data_rate = 21000; 2076 } else { 2077 config->data_rate = 20000; 2078 } 2079 } else { 2080 if(current_pll_div == TEMOD2PLL_PLL_MODE_DIV_80) { 2081 config->data_rate = 25000; 2082 } else if(current_pll_div == TEMOD2PLL_PLL_MODE_DIV_70) { 2083 config->data_rate = 21000; 2084 } else { 2085 config->data_rate = 20000; 2086 } 2087 } 2088 if (lane_config->MediaType == phymodFirmwareMediaTypeCopperCable) { 2089 config->interface_type = phymodInterfaceCR2; 2090 } else { 2091 config->interface_type = phymodInterfaceKR2; 2092 } 2093 break; 2094 case 0x1f: 2095 if (config->ref_clock == phymodRefClk125Mhz) { 2096 if(current_pll_div == TEMOD2PLL_PLL_MODE_DIV_100) { 2097 config->data_rate = 25000; 2098 } else if(current_pll_div == TEMOD2PLL_PLL_MODE_DIV_87P5) { 2099 config->data_rate = 21000; 2100 } else { 2101 config->data_rate = 20000; 2102 } 2103 } else { 2104 if(current_pll_div == TEMOD2PLL_PLL_MODE_DIV_80) { 2105 config->data_rate = 25000; 2106 } else if(current_pll_div == TEMOD2PLL_PLL_MODE_DIV_70) { 2107 config->data_rate = 21000; 2108 } else { 2109 config->data_rate = 20000; 2110 } 2111 } 2112 config->interface_type = phymodInterfaceCR2; 2113 break; 2114 case 0x20: 2115 config->data_rate = 21000; 2116 config->interface_type = phymodInterfaceKR2; 2117 break; 2118 case 0x21: /* digital_operationSpeeds_SPEED_40G_KR4 */ 2119 { 2120 if (config->ref_clock == phymodRefClk125Mhz) { 2121 if (current_pll_div == TEMOD2PLL_PLL_MODE_DIV_100) { 2122 config->data_rate = 48000; 2123 } else if (current_pll_div == TEMOD2PLL_PLL_MODE_DIV_87P5) { 2124 config->data_rate = 42000; 2125 } else { 2126 config->data_rate = 40000; 2127 } 2128 2129 } else { 2130 if (current_pll_div == TEMOD2PLL_PLL_MODE_DIV_80) { 2131 config->data_rate = 48000; 2132 } else if (current_pll_div == TEMOD2PLL_PLL_MODE_DIV_70) { 2133 config->data_rate = 42000; 2134 } else { 2135 config->data_rate = 40000; 2136 } 2137 } 2138 if (lane_config->MediaType == phymodFirmwareMediaTypeOptics) { 2139 config->interface_type = phymodInterfaceSR4; 2140 } else if (lane_config->MediaType == phymodFirmwareMediaTypeCopperCable) { 2141 config->interface_type = phymodInterfaceCR4; 2142 } else if ((lane_config->MediaType == phymodFirmwareMediaTypePcbTraceBackPlane) && hg_enable) { 2143 config->interface_type = phymodInterfaceKR4; 2144 } else if(lane_config->DfeOn) { 2145 config->interface_type = phymodInterfaceKR4; 2146 } else { 2147 config->interface_type = phymodInterfaceXLAUI; 2148 } 2149 break; 2150 } 2151 case 0x22: 2152 config->data_rate = 40000; 2153 config->interface_type = phymodInterfaceCR4; 2154 break; 2155 case 0x23: /* digital_operationSpeeds_SPEED_42G_X4; atcually MLD */ 2156 { 2157 config->data_rate = 42000; 2158 if(lane_config->MediaType == phymodFirmwareMediaTypeCopperCable){ 2159 config->interface_type = phymodInterfaceCR4; 2160 }else if(lane_config->DfeOn) { 2161 config->interface_type = phymodInterfaceKR4; 2162 } else { 2163 config->interface_type = phymodInterfaceXLAUI; 2164 } 2165 break; 2166 } 2167 case 0x2b: 2168 config->data_rate = 21000; 2169 config->interface_type = phymodInterfaceRXAUI; 2170 break; 2171 case 0x2c: 2172 config->data_rate = 42000; 2173 config->interface_type = phymodInterfaceXGMII; 2174 break; 2175 case 0x31: 2176 config->data_rate = 5000; 2177 config->interface_type = phymodInterfaceKR; 2178 break; 2179 case 0x32: 2180 config->data_rate = 10500; 2181 config->interface_type = phymodInterfaceXGMII; 2182 break; 2183 case 0x35: 2184 config->data_rate = 10; 2185 config->interface_type = phymodInterfaceSGMII; 2186 break; 2187 case 0x36: 2188 config->data_rate = 100; 2189 config->interface_type = phymodInterfaceSGMII; 2190 break; 2191 case 0x37: 2192 { 2193 if (lane_config->MediaType == phymodFirmwareMediaTypeOptics) { 2194 config->interface_type = phymodInterface1000X; 2195 } else { 2196 config->interface_type = phymodInterfaceSGMII; 2197 } 2198 config->data_rate = 1000; 2199 break; 2200 } 2201 case 0x38: 2202 { 2203 if (lane_config->MediaType == phymodFirmwareMediaTypeOptics) { 2204 config->interface_type = phymodInterfaceSR; 2205 } else { 2206 config->interface_type = phymodInterfaceSGMII; 2207 } 2208 config->data_rate = 2500; 2209 break; 2210 } 2211 default: 2212 config->data_rate = 0; 2213 config->interface_type = phymodInterfaceSGMII; 2214 break; 2215 } 2216 } 2217 return PHYMOD_E_NONE; 2218 } 2219 2220 int tsce_dpll_phy_interface_config_get(const phymod_phy_access_t* phy, uint32_t flags, phymod_ref_clk_t ref_clock, phymod_phy_inf_config_t* config) 2221 { 2222 int speed_id; 2223 phymod_firmware_lane_config_t firmware_lane_config; 2224 phymod_phy_access_t pm_phy_copy; 2225 int start_lane, num_lane; 2226 temod2pll_an_control_t an_control; 2227 int an_complete = 0; 2228 2229 config->ref_clock = ref_clock; 2230 PHYMOD_MEMCPY(&pm_phy_copy, phy, sizeof(pm_phy_copy)); 2231 TSCE_DPLL_PHY_ACCESS_PLLIDX_SET(&pm_phy_copy); 2232 PHYMOD_IF_ERR_RETURN 2233 (phymod_util_lane_config_get(&phy->access, &start_lane, &num_lane)); 2234 2235 PHYMOD_IF_ERR_RETURN 2236 (temod2pll_speed_id_get(&phy->access, &speed_id)); 2237 2238 pm_phy_copy.access.lane_mask = 0x1 << start_lane; 2239 2240 PHYMOD_MEMSET(&an_control, 0x0, sizeof(temod2pll_an_control_t)); 2241 PHYMOD_IF_ERR_RETURN 2242 (temod2pll_autoneg_control_get(&pm_phy_copy.access, &an_control, &an_complete)); 2243 2244 PHYMOD_IF_ERR_RETURN 2245 (tsce_dpll_phy_firmware_lane_config_get(&pm_phy_copy, &firmware_lane_config)); 2246 2247 PHYMOD_IF_ERR_RETURN 2248 (_tsce_dpll_speed_id_interface_config_get(phy, speed_id, config, an_control.enable, &firmware_lane_config)); 2249 2250 if (firmware_lane_config.MediaType == phymodFirmwareMediaTypeOptics) { 2251 PHYMOD_INTF_MODES_FIBER_SET(config); 2252 } else if (firmware_lane_config.MediaType == phymodFirmwareMediaTypeCopperCable) { 2253 PHYMOD_INTF_MODES_FIBER_CLR(config); 2254 PHYMOD_INTF_MODES_COPPER_SET(config); 2255 } else { 2256 PHYMOD_INTF_MODES_FIBER_CLR(config); 2257 PHYMOD_INTF_MODES_BACKPLANE_SET(config); 2258 } 2259 2260 switch (config->interface_type) { 2261 case phymodInterfaceSGMII: 2262 { 2263 if(config->data_rate == 1000) { 2264 if (!PHYMOD_INTF_MODES_FIBER_GET(config)) { 2265 config->interface_type = phymodInterfaceSGMII; 2266 } else { 2267 config->interface_type = phymodInterface1000X; 2268 } 2269 } else { 2270 config->interface_type = phymodInterfaceSGMII; 2271 } 2272 break; 2273 } 2274 case phymodInterfaceKR: 2275 { 2276 if (!an_control.enable) { 2277 if(config->data_rate == 10000) { 2278 if (!PHYMOD_INTF_MODES_FIBER_GET(config)) { 2279 config->interface_type = phymodInterfaceXFI; 2280 } else { 2281 config->interface_type = phymodInterfaceSFI; 2282 } 2283 } else { 2284 if (PHYMOD_INTF_MODES_FIBER_GET(config)) { 2285 config->interface_type = phymodInterfaceSR; 2286 } else { 2287 config->interface_type = phymodInterfaceKR; 2288 } 2289 } 2290 } else { 2291 config->interface_type = phymodInterfaceKR; 2292 } 2293 break; 2294 } 2295 default: 2296 break; 2297 } 2298 2299 return PHYMOD_E_NONE; 2300 2301 } 2302 2303 2304 int tsce_dpll_phy_cl72_set(const phymod_phy_access_t* phy, uint32_t cl72_en) 2305 { 2306 struct eagle2_tsc2pll_uc_lane_config_st serdes_firmware_config; 2307 phymod_phy_access_t pm_phy_copy; 2308 2309 PHYMOD_MEMCPY(&pm_phy_copy, phy, sizeof(pm_phy_copy)); 2310 TSCE_DPLL_PHY_ACCESS_PLLIDX_SET(&pm_phy_copy); 2311 2312 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_get_uc_lane_cfg(&pm_phy_copy.access, &serdes_firmware_config)); 2313 2314 if(serdes_firmware_config.field.dfe_on == 0) { 2315 PHYMOD_DEBUG_ERROR(("ERROR :: DFE is off : Can not start CL72 with no DFE\n")); 2316 return PHYMOD_E_CONFIG; 2317 } 2318 2319 PHYMOD_IF_ERR_RETURN 2320 (temod2pll_clause72_control(&pm_phy_copy.access, cl72_en)); 2321 return PHYMOD_E_NONE; 2322 2323 } 2324 2325 int tsce_dpll_phy_cl72_get(const phymod_phy_access_t* phy, uint32_t* cl72_en) 2326 { 2327 uint32_t local_en; 2328 phymod_phy_access_t pm_phy_copy; 2329 2330 PHYMOD_MEMCPY(&pm_phy_copy, phy, sizeof(pm_phy_copy)); 2331 TSCE_DPLL_PHY_ACCESS_PLLIDX_SET(&pm_phy_copy); 2332 PHYMOD_IF_ERR_RETURN 2333 (eagle2_tsc2pll_pmd_cl72_enable_get(&pm_phy_copy.access, &local_en)); 2334 *cl72_en = local_en; 2335 return PHYMOD_E_NONE; 2336 } 2337 2338 2339 int tsce_dpll_phy_cl72_status_get(const phymod_phy_access_t* phy, phymod_cl72_status_t* status) 2340 { 2341 uint32_t local_status; 2342 phymod_phy_access_t pm_phy_copy; 2343 2344 PHYMOD_MEMCPY(&pm_phy_copy, phy, sizeof(pm_phy_copy)); 2345 TSCE_DPLL_PHY_ACCESS_PLLIDX_SET(&pm_phy_copy); 2346 PHYMOD_IF_ERR_RETURN 2347 (eagle2_tsc2pll_pmd_cl72_receiver_status(&pm_phy_copy.access, &local_status)); 2348 status->locked = local_status; 2349 return PHYMOD_E_NONE; 2350 2351 } 2352 2353 2354 int tsce_dpll_phy_autoneg_ability_set(const phymod_phy_access_t* phy, const phymod_autoneg_ability_t* an_ability) 2355 { 2356 temod2pll_an_ability_t value; 2357 int start_lane, num_lane; 2358 phymod_phy_access_t phy_copy; 2359 /* next program the tx fir taps and driver current based on the input */ 2360 PHYMOD_IF_ERR_RETURN 2361 (phymod_util_lane_config_get(&phy->access, &start_lane, &num_lane)); 2362 2363 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 2364 TSCE_DPLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 2365 phy_copy.access.lane_mask = 0x1 << start_lane; 2366 2367 PHYMOD_MEMSET(&value, 0x0, sizeof(value)); 2368 2369 value.cl37_adv.an_cl72 = an_ability->an_cl72; 2370 value.cl73_adv.an_cl72 = an_ability->an_cl72; 2371 value.cl37_adv.an_hg2 = an_ability->an_hg2; 2372 if (PHYMOD_AN_FEC_CL74_GET(an_ability->an_fec)) { 2373 value.cl37_adv.an_fec = TEMOD2PLL_FEC_CL74_SUPRTD_REQSTD; 2374 value.cl73_adv.an_fec = TEMOD2PLL_FEC_CL74_SUPRTD_REQSTD; 2375 } else if (PHYMOD_AN_FEC_OFF_GET(an_ability->an_fec)) { 2376 value.cl37_adv.an_fec = TEMOD2PLL_FEC_SUPRTD_NOT_REQSTD; 2377 value.cl73_adv.an_fec = TEMOD2PLL_FEC_SUPRTD_NOT_REQSTD; 2378 } 2379 2380 /* check if sgmii or not */ 2381 if (PHYMOD_AN_CAP_SGMII_GET(an_ability)) { 2382 switch (an_ability->sgmii_speed) { 2383 case phymod_CL37_SGMII_10M: 2384 value.cl37_adv.cl37_sgmii_speed = TEMOD2PLL_CL37_SGMII_10M; 2385 break; 2386 case phymod_CL37_SGMII_100M: 2387 value.cl37_adv.cl37_sgmii_speed = TEMOD2PLL_CL37_SGMII_100M; 2388 break; 2389 case phymod_CL37_SGMII_1000M: 2390 value.cl37_adv.cl37_sgmii_speed = TEMOD2PLL_CL37_SGMII_1000M; 2391 break; 2392 default: 2393 value.cl37_adv.cl37_sgmii_speed = TEMOD2PLL_CL37_SGMII_1000M; 2394 break; 2395 } 2396 } 2397 /* next check pause */ 2398 if (PHYMOD_AN_CAP_SYMM_PAUSE_GET(an_ability) && !PHYMOD_AN_CAP_ASYM_PAUSE_GET(an_ability)) { 2399 value.cl37_adv.an_pause = TEMOD2PLL_SYMM_PAUSE; 2400 value.cl73_adv.an_pause = TEMOD2PLL_SYMM_PAUSE; 2401 } 2402 if (PHYMOD_AN_CAP_ASYM_PAUSE_GET(an_ability) && !PHYMOD_AN_CAP_SYMM_PAUSE_GET(an_ability)) { 2403 value.cl37_adv.an_pause = TEMOD2PLL_ASYM_PAUSE; 2404 value.cl73_adv.an_pause = TEMOD2PLL_ASYM_PAUSE; 2405 } 2406 if (PHYMOD_AN_CAP_ASYM_PAUSE_GET(an_ability) && PHYMOD_AN_CAP_SYMM_PAUSE_GET(an_ability)) { 2407 value.cl37_adv.an_pause = TEMOD2PLL_ASYM_SYMM_PAUSE; 2408 value.cl73_adv.an_pause = TEMOD2PLL_ASYM_SYMM_PAUSE; 2409 } 2410 2411 /* check cl73 and cl73 bam ability */ 2412 if (PHYMOD_AN_CAP_1G_KX_GET(an_ability->an_cap)) 2413 value.cl73_adv.an_base_speed |= 1 << TEMOD2PLL_CL73_1000BASE_KX; 2414 if (PHYMOD_AN_CAP_10G_KX4_GET(an_ability->an_cap)) 2415 value.cl73_adv.an_base_speed |= 1 << TEMOD2PLL_CL73_10GBASE_KX4; 2416 if (PHYMOD_AN_CAP_10G_KR_GET(an_ability->an_cap)) 2417 value.cl73_adv.an_base_speed |= 1 << TEMOD2PLL_CL73_10GBASE_KR; 2418 if (PHYMOD_AN_CAP_40G_KR4_GET(an_ability->an_cap)) 2419 value.cl73_adv.an_base_speed |= 1 << TEMOD2PLL_CL73_40GBASE_KR4; 2420 if (PHYMOD_AN_CAP_40G_CR4_GET(an_ability->an_cap)) 2421 value.cl73_adv.an_base_speed |= 1 << TEMOD2PLL_CL73_40GBASE_CR4; 2422 if (PHYMOD_AN_CAP_100G_CR10_GET(an_ability->an_cap)) 2423 value.cl73_adv.an_base_speed |= 1 << TEMOD2PLL_CL73_100GBASE_CR10; 2424 if (PHYMOD_AN_CAP_2P5G_X_GET(an_ability->an_cap)) 2425 value.cl73_adv.an_base_speed |= 1 << TEMOD2PLL_CL73_2p5GBASE_X; 2426 if (PHYMOD_AN_CAP_5G_KR1_GET(an_ability->an_cap)) 2427 value.cl73_adv.an_base_speed |= 1 << TEMOD2PLL_CL73_5GBASE_KR1; 2428 2429 /* next check cl73 bam ability */ 2430 if (PHYMOD_BAM_CL73_CAP_20G_KR2_GET(an_ability->cl73bam_cap)) 2431 value.cl73_adv.an_bam_speed |= 1 << TEMOD2PLL_CL73_BAM_20GBASE_KR2; 2432 if (PHYMOD_BAM_CL73_CAP_20G_CR2_GET(an_ability->cl73bam_cap)) 2433 value.cl73_adv.an_bam_speed |= 1 << TEMOD2PLL_CL73_BAM_20GBASE_CR2; 2434 2435 /* check cl37 and cl37 bam ability */ 2436 if (PHYMOD_BAM_CL37_CAP_2P5G_GET(an_ability->cl37bam_cap)) 2437 value.cl37_adv.an_bam_speed |= 1 << TEMOD2PLL_CL37_BAM_2p5GBASE_X; 2438 if (PHYMOD_BAM_CL37_CAP_5G_X4_GET(an_ability->cl37bam_cap)) 2439 value.cl37_adv.an_bam_speed |= 1 << TEMOD2PLL_CL37_BAM_5GBASE_X4; 2440 if (PHYMOD_BAM_CL37_CAP_6G_X4_GET(an_ability->cl37bam_cap)) 2441 value.cl37_adv.an_bam_speed |= 1 << TEMOD2PLL_CL37_BAM_6GBASE_X4; 2442 if (PHYMOD_BAM_CL37_CAP_10G_HIGIG_GET(an_ability->cl37bam_cap)) 2443 value.cl37_adv.an_bam_speed |= 1 << TEMOD2PLL_CL37_BAM_10GBASE_X4; 2444 if (PHYMOD_BAM_CL37_CAP_10G_CX4_GET(an_ability->cl37bam_cap)) 2445 value.cl37_adv.an_bam_speed |= 1 << TEMOD2PLL_CL37_BAM_10GBASE_X4_CX4; 2446 if (PHYMOD_BAM_CL37_CAP_12G_X4_GET(an_ability->cl37bam_cap)) 2447 value.cl37_adv.an_bam_speed |= 1 << TEMOD2PLL_CL37_BAM_12GBASE_X4; 2448 if (PHYMOD_BAM_CL37_CAP_12P5_X4_GET(an_ability->cl37bam_cap)) 2449 value.cl37_adv.an_bam_speed |= 1 << TEMOD2PLL_CL37_BAM_12p5GBASE_X4; 2450 if (PHYMOD_BAM_CL37_CAP_10G_X2_CX4_GET(an_ability->cl37bam_cap)) 2451 value.cl37_adv.an_bam_speed |= 1 << TEMOD2PLL_CL37_BAM_10GBASE_X2_CX4; 2452 if (PHYMOD_BAM_CL37_CAP_10G_DXGXS_GET(an_ability->cl37bam_cap)) 2453 value.cl37_adv.an_bam_speed |= 1 << TEMOD2PLL_CL37_BAM_10GBASE_X2; 2454 if (PHYMOD_BAM_CL37_CAP_10P5G_DXGXS_GET(an_ability->cl37bam_cap)) 2455 value.cl37_adv.an_bam_speed |= 1 << TEMOD2PLL_CL37_BAM_BAM_10p5GBASE_X2; 2456 if (PHYMOD_BAM_CL37_CAP_12P7_DXGXS_GET(an_ability->cl37bam_cap)) 2457 value.cl37_adv.an_bam_speed |= 1 << TEMOD2PLL_CL37_BAM_12p7GBASE_X2; 2458 if (PHYMOD_BAM_CL37_CAP_20G_X2_CX4_GET(an_ability->cl37bam_cap)) 2459 value.cl37_adv.an_bam_speed1 |= 1 << TEMOD2PLL_CL37_BAM_20GBASE_X2_CX4; 2460 if (PHYMOD_BAM_CL37_CAP_20G_X2_GET(an_ability->cl37bam_cap)) 2461 value.cl37_adv.an_bam_speed1 |= 1 << TEMOD2PLL_CL37_BAM_20GBASE_X2; 2462 if (PHYMOD_BAM_CL37_CAP_13G_X4_GET(an_ability->cl37bam_cap)) 2463 value.cl37_adv.an_bam_speed1 |= 1 << TEMOD2PLL_CL37_BAM_13GBASE_X4; 2464 if (PHYMOD_BAM_CL37_CAP_15G_X4_GET(an_ability->cl37bam_cap)) 2465 value.cl37_adv.an_bam_speed1 |= 1 << TEMOD2PLL_CL37_BAM_15GBASE_X4; 2466 if (PHYMOD_BAM_CL37_CAP_16G_X4_GET(an_ability->cl37bam_cap)) 2467 value.cl37_adv.an_bam_speed1 |= 1 << TEMOD2PLL_CL37_BAM_16GBASE_X4; 2468 if (PHYMOD_BAM_CL37_CAP_20G_X4_CX4_GET(an_ability->cl37bam_cap)) 2469 value.cl37_adv.an_bam_speed1 |= 1 << TEMOD2PLL_CL37_BAM_20GBASE_X4_CX4; 2470 if (PHYMOD_BAM_CL37_CAP_20G_X4_GET(an_ability->cl37bam_cap)) 2471 value.cl37_adv.an_bam_speed1 |= 1 << TEMOD2PLL_CL37_BAM_20GBASE_X4; 2472 if (PHYMOD_BAM_CL37_CAP_21G_X4_GET(an_ability->cl37bam_cap)) 2473 value.cl37_adv.an_bam_speed1 |= 1 << TEMOD2PLL_CL37_BAM_21GBASE_X4; 2474 if (PHYMOD_BAM_CL37_CAP_25P455G_GET(an_ability->cl37bam_cap)) 2475 value.cl37_adv.an_bam_speed1 |= 1 << TEMOD2PLL_CL37_BAM_25p455GBASE_X4; 2476 if (PHYMOD_BAM_CL37_CAP_31P5G_GET(an_ability->cl37bam_cap)) 2477 value.cl37_adv.an_bam_speed1 |= 1 << TEMOD2PLL_CL37_BAM_31p5GBASE_X4; 2478 if (PHYMOD_BAM_CL37_CAP_32P7G_GET(an_ability->cl37bam_cap)) 2479 value.cl37_adv.an_bam_speed1 |= 1 << TEMOD2PLL_CL37_BAM_32p7GBASE_X4; 2480 if (PHYMOD_BAM_CL37_CAP_40G_GET(an_ability->cl37bam_cap)) 2481 value.cl37_adv.an_bam_speed1 |= 1 << TEMOD2PLL_CL37_BAM_40GBASE_X4; 2482 2483 PHYMOD_IF_ERR_RETURN 2484 (temod2pll_autoneg_set(&phy_copy.access, &value)); 2485 return PHYMOD_E_NONE; 2486 2487 } 2488 2489 int tsce_dpll_phy_autoneg_ability_get(const phymod_phy_access_t* phy, phymod_autoneg_ability_t* an_ability_get_type) 2490 { 2491 temod2pll_an_ability_t value; 2492 phymod_phy_access_t phy_copy; 2493 int start_lane, num_lane; 2494 temod2pll_an_control_t an_control; 2495 int an_complete = 0; 2496 int an_fec = 0; 2497 2498 2499 PHYMOD_IF_ERR_RETURN 2500 (phymod_util_lane_config_get(&phy->access, &start_lane, &num_lane)); 2501 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 2502 TSCE_DPLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 2503 phy_copy.access.lane_mask = 0x1 << start_lane; 2504 PHYMOD_MEMSET(&value, 0x0, sizeof(value)); 2505 2506 PHYMOD_IF_ERR_RETURN 2507 (temod2pll_autoneg_local_ability_get(&phy_copy.access, &value)); 2508 PHYMOD_IF_ERR_RETURN 2509 (temod2pll_autoneg_control_get(&phy_copy.access, &an_control, &an_complete)); 2510 an_ability_get_type->an_cl72 = value.cl37_adv.an_cl72 | value.cl73_adv.an_cl72; 2511 an_ability_get_type->an_hg2 = value.cl37_adv.an_hg2; 2512 an_fec = value.cl37_adv.an_fec | value.cl73_adv.an_fec; 2513 an_ability_get_type->an_fec = 0; 2514 if (an_fec & TEMOD2PLL_FEC_CL74_SUPRTD_REQSTD) { 2515 PHYMOD_AN_FEC_CL74_SET(an_ability_get_type->an_fec); 2516 } else { 2517 PHYMOD_AN_FEC_OFF_SET(an_ability_get_type->an_fec); 2518 } 2519 2520 if ((value.cl37_adv.an_pause == TEMOD2PLL_ASYM_PAUSE)||(value.cl73_adv.an_pause == TEMOD2PLL_ASYM_PAUSE)) { 2521 PHYMOD_AN_CAP_ASYM_PAUSE_SET(an_ability_get_type); 2522 } else if ((value.cl37_adv.an_pause == TEMOD2PLL_SYMM_PAUSE)||(value.cl73_adv.an_pause == TEMOD2PLL_SYMM_PAUSE)) { 2523 PHYMOD_AN_CAP_SYMM_PAUSE_SET(an_ability_get_type); 2524 } else if ((value.cl37_adv.an_pause == TEMOD2PLL_ASYM_SYMM_PAUSE)||(value.cl73_adv.an_pause == TEMOD2PLL_ASYM_SYMM_PAUSE)) { 2525 PHYMOD_AN_CAP_ASYM_PAUSE_SET(an_ability_get_type); 2526 PHYMOD_AN_CAP_SYMM_PAUSE_SET(an_ability_get_type); 2527 } 2528 2529 /* get AN Clause */ 2530 switch (an_control.an_type) { 2531 case TEMOD2PLL_AN_MODE_CL73: 2532 PHYMOD_AN_CAP_CL73_SET(an_ability_get_type); 2533 break; 2534 case TEMOD2PLL_AN_MODE_CL37: 2535 PHYMOD_AN_CAP_CL37_SET(an_ability_get_type); 2536 break; 2537 case TEMOD2PLL_AN_MODE_CL73BAM: 2538 PHYMOD_AN_CAP_CL73BAM_SET(an_ability_get_type); 2539 break; 2540 case TEMOD2PLL_AN_MODE_CL37BAM: 2541 PHYMOD_AN_CAP_CL37BAM_SET(an_ability_get_type); 2542 break; 2543 case TEMOD2PLL_AN_MODE_HPAM: 2544 PHYMOD_AN_CAP_HPAM_SET(an_ability_get_type); 2545 break; 2546 case TEMOD2PLL_AN_MODE_SGMII: 2547 PHYMOD_AN_CAP_SGMII_SET(an_ability_get_type); 2548 break; 2549 case TEMOD2PLL_AN_MODE_CL37_SGMII: 2550 PHYMOD_AN_CAP_SGMII_SET(an_ability_get_type); 2551 break; 2552 default: 2553 break; 2554 } 2555 2556 /* get the cl37 sgmii speed */ 2557 switch (value.cl37_adv.cl37_sgmii_speed) { 2558 case TEMOD2PLL_CL37_SGMII_10M: 2559 an_ability_get_type->sgmii_speed = phymod_CL37_SGMII_10M; 2560 break; 2561 case TEMOD2PLL_CL37_SGMII_100M: 2562 an_ability_get_type->sgmii_speed = phymod_CL37_SGMII_100M; 2563 break; 2564 case TEMOD2PLL_CL37_SGMII_1000M: 2565 an_ability_get_type->sgmii_speed = phymod_CL37_SGMII_1000M; 2566 break; 2567 default: 2568 break; 2569 } 2570 /* first check cl73 ability */ 2571 if (value.cl73_adv.an_base_speed & 1 << TEMOD2PLL_CL73_100GBASE_CR10) 2572 PHYMOD_AN_CAP_100G_CR10_SET(an_ability_get_type->an_cap); 2573 if (value.cl73_adv.an_base_speed & 1 << TEMOD2PLL_CL73_40GBASE_CR4) 2574 PHYMOD_AN_CAP_40G_CR4_SET(an_ability_get_type->an_cap); 2575 if (value.cl73_adv.an_base_speed & 1 << TEMOD2PLL_CL73_40GBASE_KR4) 2576 PHYMOD_AN_CAP_40G_KR4_SET(an_ability_get_type->an_cap); 2577 if (value.cl73_adv.an_base_speed & 1 << TEMOD2PLL_CL73_10GBASE_KR) 2578 PHYMOD_AN_CAP_10G_KR_SET(an_ability_get_type->an_cap); 2579 if (value.cl73_adv.an_base_speed & 1 << TEMOD2PLL_CL73_10GBASE_KX4) 2580 PHYMOD_AN_CAP_10G_KX4_SET(an_ability_get_type->an_cap); 2581 if (value.cl73_adv.an_base_speed & 1 << TEMOD2PLL_CL73_1000BASE_KX) 2582 PHYMOD_AN_CAP_1G_KX_SET(an_ability_get_type->an_cap); 2583 if (value.cl73_adv.an_base_speed & 1<< TEMOD2PLL_CL73_2p5GBASE_X) 2584 PHYMOD_AN_CAP_2P5G_X_SET(an_ability_get_type->an_cap); 2585 if (value.cl73_adv.an_base_speed & 1<< TEMOD2PLL_CL73_5GBASE_KR1) 2586 PHYMOD_AN_CAP_5G_KR1_SET(an_ability_get_type->an_cap); 2587 2588 /* next check cl73 bam ability */ 2589 if (value.cl73_adv.an_bam_speed & 1 << TEMOD2PLL_CL73_BAM_20GBASE_KR2) 2590 PHYMOD_BAM_CL73_CAP_20G_KR2_SET(an_ability_get_type->cl73bam_cap); 2591 if (value.cl73_adv.an_bam_speed & 1 << TEMOD2PLL_CL73_BAM_20GBASE_CR2) 2592 PHYMOD_BAM_CL73_CAP_20G_CR2_SET(an_ability_get_type->cl73bam_cap); 2593 2594 /* check cl37 bam ability */ 2595 if (value.cl37_adv.an_bam_speed & 1 << TEMOD2PLL_CL37_BAM_2p5GBASE_X) 2596 PHYMOD_BAM_CL37_CAP_2P5G_SET(an_ability_get_type->cl37bam_cap); 2597 if (value.cl37_adv.an_bam_speed & 1 << TEMOD2PLL_CL37_BAM_5GBASE_X4) 2598 PHYMOD_BAM_CL37_CAP_5G_X4_SET(an_ability_get_type->cl37bam_cap); 2599 if (value.cl37_adv.an_bam_speed & 1 << TEMOD2PLL_CL37_BAM_6GBASE_X4) 2600 PHYMOD_BAM_CL37_CAP_6G_X4_SET(an_ability_get_type->cl37bam_cap); 2601 if (value.cl37_adv.an_bam_speed & 1 << TEMOD2PLL_CL37_BAM_10GBASE_X4) 2602 PHYMOD_BAM_CL37_CAP_10G_HIGIG_SET(an_ability_get_type->cl37bam_cap); 2603 if (value.cl37_adv.an_bam_speed & 1 << TEMOD2PLL_CL37_BAM_10GBASE_X4_CX4) 2604 PHYMOD_BAM_CL37_CAP_10G_CX4_SET(an_ability_get_type->cl37bam_cap); 2605 if (value.cl37_adv.an_bam_speed & 1 << TEMOD2PLL_CL37_BAM_10GBASE_X2) 2606 PHYMOD_BAM_CL37_CAP_10G_DXGXS_SET(an_ability_get_type->cl37bam_cap); 2607 if (value.cl37_adv.an_bam_speed & 1 << TEMOD2PLL_CL37_BAM_10GBASE_X2_CX4) 2608 PHYMOD_BAM_CL37_CAP_10G_X2_CX4_SET(an_ability_get_type->cl37bam_cap); 2609 if (value.cl37_adv.an_bam_speed & 1 << TEMOD2PLL_CL37_BAM_BAM_10p5GBASE_X2) 2610 PHYMOD_BAM_CL37_CAP_10P5G_DXGXS_SET(an_ability_get_type->cl37bam_cap); 2611 if (value.cl37_adv.an_bam_speed & 1 << TEMOD2PLL_CL37_BAM_12GBASE_X4) 2612 PHYMOD_BAM_CL37_CAP_12G_X4_SET(an_ability_get_type->cl37bam_cap); 2613 if (value.cl37_adv.an_bam_speed & 1 << TEMOD2PLL_CL37_BAM_12p5GBASE_X4) 2614 PHYMOD_BAM_CL37_CAP_12P5_X4_SET(an_ability_get_type->cl37bam_cap); 2615 if (value.cl37_adv.an_bam_speed & 1 << TEMOD2PLL_CL37_BAM_12p7GBASE_X2) 2616 PHYMOD_BAM_CL37_CAP_12P7_DXGXS_SET(an_ability_get_type->cl37bam_cap); 2617 2618 if (value.cl37_adv.an_bam_speed1 & 1 << TEMOD2PLL_CL37_BAM_13GBASE_X4) 2619 PHYMOD_BAM_CL37_CAP_13G_X4_SET(an_ability_get_type->cl37bam_cap); 2620 if (value.cl37_adv.an_bam_speed1 & 1 << TEMOD2PLL_CL37_BAM_15GBASE_X4) 2621 PHYMOD_BAM_CL37_CAP_15G_X4_SET(an_ability_get_type->cl37bam_cap); 2622 if (value.cl37_adv.an_bam_speed1 & 1 << TEMOD2PLL_CL37_BAM_15p75GBASE_X2) 2623 PHYMOD_BAM_CL37_CAP_12P7_DXGXS_SET(an_ability_get_type->cl37bam_cap); 2624 if (value.cl37_adv.an_bam_speed1 & 1 << TEMOD2PLL_CL37_BAM_16GBASE_X4) 2625 PHYMOD_BAM_CL37_CAP_16G_X4_SET(an_ability_get_type->cl37bam_cap); 2626 if (value.cl37_adv.an_bam_speed1 & 1 << TEMOD2PLL_CL37_BAM_20GBASE_X4_CX4) 2627 PHYMOD_BAM_CL37_CAP_20G_X4_CX4_SET(an_ability_get_type->cl37bam_cap); 2628 if (value.cl37_adv.an_bam_speed1 & 1 << TEMOD2PLL_CL37_BAM_20GBASE_X4) 2629 PHYMOD_BAM_CL37_CAP_20G_X4_SET(an_ability_get_type->cl37bam_cap); 2630 if (value.cl37_adv.an_bam_speed1 & 1 << TEMOD2PLL_CL37_BAM_20GBASE_X2) 2631 PHYMOD_BAM_CL37_CAP_20G_X2_SET(an_ability_get_type->cl37bam_cap); 2632 if (value.cl37_adv.an_bam_speed1 & 1 << TEMOD2PLL_CL37_BAM_20GBASE_X2_CX4) 2633 PHYMOD_BAM_CL37_CAP_20G_X2_CX4_SET(an_ability_get_type->cl37bam_cap); 2634 if (value.cl37_adv.an_bam_speed1 & 1 << TEMOD2PLL_CL37_BAM_21GBASE_X4) 2635 PHYMOD_BAM_CL37_CAP_21G_X4_SET(an_ability_get_type->cl37bam_cap); 2636 if (value.cl37_adv.an_bam_speed1 & 1 << TEMOD2PLL_CL37_BAM_25p455GBASE_X4) 2637 PHYMOD_BAM_CL37_CAP_25P455G_SET(an_ability_get_type->cl37bam_cap); 2638 if (value.cl37_adv.an_bam_speed1 & 1 << TEMOD2PLL_CL37_BAM_31p5GBASE_X4) 2639 PHYMOD_BAM_CL37_CAP_31P5G_SET(an_ability_get_type->cl37bam_cap); 2640 if (value.cl37_adv.an_bam_speed1 & 1 << TEMOD2PLL_CL37_BAM_32p7GBASE_X4) 2641 PHYMOD_BAM_CL37_CAP_32P7G_SET(an_ability_get_type->cl37bam_cap); 2642 if (value.cl37_adv.an_bam_speed1 & 1 << TEMOD2PLL_CL37_BAM_40GBASE_X4) 2643 PHYMOD_BAM_CL37_CAP_40G_SET(an_ability_get_type->cl37bam_cap); 2644 2645 return PHYMOD_E_NONE; 2646 } 2647 2648 2649 int tsce_dpll_phy_autoneg_remote_ability_get(const phymod_phy_access_t* phy, phymod_autoneg_ability_t* an_ability_get_type) 2650 { 2651 2652 temod2pll_an_ability_t value; 2653 temod2pll_an_control_t an_control; 2654 phymod_phy_access_t phy_copy; 2655 int an_complete = 0; 2656 int start_lane, num_lane; 2657 int an_fec; 2658 2659 PHYMOD_IF_ERR_RETURN 2660 (phymod_util_lane_config_get(&phy->access, &start_lane, &num_lane)); 2661 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 2662 TSCE_DPLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 2663 phy_copy.access.lane_mask = 0x1 << start_lane; 2664 PHYMOD_MEMSET(&value, 0x0, sizeof(value)); 2665 PHYMOD_MEMSET(&an_control, 0x0, sizeof(an_control)); 2666 2667 PHYMOD_IF_ERR_RETURN 2668 (temod2pll_autoneg_remote_ability_get(&phy_copy.access, &value)); 2669 an_ability_get_type->an_cl72 = value.cl37_adv.an_cl72 | value.cl73_adv.an_cl72; 2670 an_ability_get_type->an_hg2 = value.cl37_adv.an_hg2; 2671 an_fec = value.cl37_adv.an_fec | value.cl73_adv.an_fec; 2672 if (an_fec == TEMOD2PLL_FEC_CL74_SUPRTD_REQSTD) { 2673 PHYMOD_AN_FEC_CL74_SET(an_ability_get_type->an_fec); 2674 } else { 2675 PHYMOD_AN_FEC_OFF_SET(an_ability_get_type->an_fec); 2676 } 2677 PHYMOD_IF_ERR_RETURN 2678 (temod2pll_autoneg_control_get(&phy_copy.access, &an_control, &an_complete)); 2679 2680 if (an_control.an_type == TEMOD2PLL_AN_MODE_CL73 || an_control.an_type == TEMOD2PLL_AN_MODE_CL73BAM) { 2681 if (value.cl73_adv.an_pause == TEMOD2PLL_ASYM_PAUSE) { 2682 PHYMOD_AN_CAP_ASYM_PAUSE_SET(an_ability_get_type); 2683 } else if (value.cl73_adv.an_pause == TEMOD2PLL_SYMM_PAUSE) { 2684 PHYMOD_AN_CAP_SYMM_PAUSE_SET(an_ability_get_type); 2685 } else if (value.cl73_adv.an_pause == TEMOD2PLL_ASYM_SYMM_PAUSE) { 2686 PHYMOD_AN_CAP_ASYM_PAUSE_SET(an_ability_get_type); 2687 PHYMOD_AN_CAP_SYMM_PAUSE_SET(an_ability_get_type); 2688 } 2689 } else { 2690 if (value.cl37_adv.an_pause == TEMOD2PLL_ASYM_PAUSE) { 2691 PHYMOD_AN_CAP_ASYM_PAUSE_SET(an_ability_get_type); 2692 } else if (value.cl37_adv.an_pause == TEMOD2PLL_SYMM_PAUSE) { 2693 PHYMOD_AN_CAP_SYMM_PAUSE_SET(an_ability_get_type); 2694 } else if (value.cl37_adv.an_pause == TEMOD2PLL_ASYM_SYMM_PAUSE) { 2695 PHYMOD_AN_CAP_ASYM_PAUSE_SET(an_ability_get_type); 2696 PHYMOD_AN_CAP_SYMM_PAUSE_SET(an_ability_get_type); 2697 } 2698 } 2699 2700 /* get AN Clause */ 2701 switch (an_control.an_type) { 2702 case TEMOD2PLL_AN_MODE_CL73: 2703 PHYMOD_AN_CAP_CL73_SET(an_ability_get_type); 2704 break; 2705 case TEMOD2PLL_AN_MODE_CL37: 2706 PHYMOD_AN_CAP_CL37_SET(an_ability_get_type); 2707 break; 2708 case TEMOD2PLL_AN_MODE_CL73BAM: 2709 PHYMOD_AN_CAP_CL73BAM_SET(an_ability_get_type); 2710 break; 2711 case TEMOD2PLL_AN_MODE_CL37BAM: 2712 PHYMOD_AN_CAP_CL37BAM_SET(an_ability_get_type); 2713 break; 2714 case TEMOD2PLL_AN_MODE_HPAM: 2715 PHYMOD_AN_CAP_HPAM_SET(an_ability_get_type); 2716 break; 2717 case TEMOD2PLL_AN_MODE_SGMII: 2718 PHYMOD_AN_CAP_SGMII_SET(an_ability_get_type); 2719 break; 2720 case TEMOD2PLL_AN_MODE_CL37_SGMII: 2721 PHYMOD_AN_CAP_SGMII_SET(an_ability_get_type); 2722 break; 2723 default: 2724 break; 2725 } 2726 2727 /* get the cl37 sgmii speed */ 2728 switch (value.cl37_adv.cl37_sgmii_speed) { 2729 case TEMOD2PLL_CL37_SGMII_10M: 2730 an_ability_get_type->sgmii_speed = phymod_CL37_SGMII_10M; 2731 break; 2732 case TEMOD2PLL_CL37_SGMII_100M: 2733 an_ability_get_type->sgmii_speed = phymod_CL37_SGMII_100M; 2734 break; 2735 case TEMOD2PLL_CL37_SGMII_1000M: 2736 an_ability_get_type->sgmii_speed = phymod_CL37_SGMII_1000M; 2737 break; 2738 default: 2739 break; 2740 } 2741 2742 /* first check cl73 ability */ 2743 if (value.cl73_adv.an_base_speed & 1 << TEMOD2PLL_CL73_100GBASE_CR10) 2744 PHYMOD_AN_CAP_100G_CR10_SET(an_ability_get_type->an_cap); 2745 if (value.cl73_adv.an_base_speed & 1 << TEMOD2PLL_CL73_40GBASE_CR4) 2746 PHYMOD_AN_CAP_40G_CR4_SET(an_ability_get_type->an_cap); 2747 if (value.cl73_adv.an_base_speed & 1 << TEMOD2PLL_CL73_40GBASE_KR4) 2748 PHYMOD_AN_CAP_40G_KR4_SET(an_ability_get_type->an_cap); 2749 if (value.cl73_adv.an_base_speed & 1 << TEMOD2PLL_CL73_10GBASE_KR) 2750 PHYMOD_AN_CAP_10G_KR_SET(an_ability_get_type->an_cap); 2751 if (value.cl73_adv.an_base_speed & 1 << TEMOD2PLL_CL73_10GBASE_KX4) 2752 PHYMOD_AN_CAP_10G_KX4_SET(an_ability_get_type->an_cap); 2753 if (value.cl73_adv.an_base_speed & 1 << TEMOD2PLL_CL73_1000BASE_KX) 2754 PHYMOD_AN_CAP_1G_KX_SET(an_ability_get_type->an_cap); 2755 if (value.cl73_adv.an_base_speed & 1 << TEMOD2PLL_CL73_2p5GBASE_X) 2756 PHYMOD_AN_CAP_2P5G_X_SET(an_ability_get_type->an_cap); 2757 if (value.cl73_adv.an_base_speed & 1 << TEMOD2PLL_CL73_5GBASE_KR1) 2758 PHYMOD_AN_CAP_5G_KR1_SET(an_ability_get_type->an_cap); 2759 2760 /* next check cl73 bam ability */ 2761 /*UD0 in UP4 indicates Over 1G ability when an mode is cl37 bam*/ 2762 if (PHYMOD_AN_CAP_CL73BAM_GET(an_ability_get_type)) { 2763 if (value.cl73_adv.an_bam_speed & 1 << TEMOD2PLL_CL73_BAM_20GBASE_KR2) 2764 PHYMOD_BAM_CL73_CAP_20G_KR2_SET(an_ability_get_type->cl73bam_cap); 2765 if (value.cl73_adv.an_bam_speed & 1 << TEMOD2PLL_CL73_BAM_20GBASE_CR2) 2766 PHYMOD_BAM_CL73_CAP_20G_CR2_SET(an_ability_get_type->cl73bam_cap); 2767 } 2768 2769 /* check cl37 bam ability */ 2770 if (value.cl37_adv.an_bam_speed & 1 << TEMOD2PLL_CL37_BAM_2p5GBASE_X) 2771 PHYMOD_BAM_CL37_CAP_2P5G_SET(an_ability_get_type->cl37bam_cap); 2772 if (value.cl37_adv.an_bam_speed & 1 << TEMOD2PLL_CL37_BAM_5GBASE_X4) 2773 PHYMOD_BAM_CL37_CAP_5G_X4_SET(an_ability_get_type->cl37bam_cap); 2774 if (value.cl37_adv.an_bam_speed & 1 << TEMOD2PLL_CL37_BAM_6GBASE_X4) 2775 PHYMOD_BAM_CL37_CAP_6G_X4_SET(an_ability_get_type->cl37bam_cap); 2776 if (value.cl37_adv.an_bam_speed & 1 << TEMOD2PLL_CL37_BAM_10GBASE_X4) 2777 PHYMOD_BAM_CL37_CAP_10G_HIGIG_SET(an_ability_get_type->cl37bam_cap); 2778 if (value.cl37_adv.an_bam_speed & 1 << TEMOD2PLL_CL37_BAM_10GBASE_X4_CX4) 2779 PHYMOD_BAM_CL37_CAP_10G_CX4_SET(an_ability_get_type->cl37bam_cap); 2780 if (value.cl37_adv.an_bam_speed & 1 << TEMOD2PLL_CL37_BAM_10GBASE_X2) 2781 PHYMOD_BAM_CL37_CAP_10G_DXGXS_SET(an_ability_get_type->cl37bam_cap); 2782 if (value.cl37_adv.an_bam_speed & 1 << TEMOD2PLL_CL37_BAM_10GBASE_X2_CX4) 2783 PHYMOD_BAM_CL37_CAP_10G_X2_CX4_SET(an_ability_get_type->cl37bam_cap); 2784 if (value.cl37_adv.an_bam_speed & 1 << TEMOD2PLL_CL37_BAM_BAM_10p5GBASE_X2) 2785 PHYMOD_BAM_CL37_CAP_10P5G_DXGXS_SET(an_ability_get_type->cl37bam_cap); 2786 if (value.cl37_adv.an_bam_speed & 1 << TEMOD2PLL_CL37_BAM_12GBASE_X4) 2787 PHYMOD_BAM_CL37_CAP_12G_X4_SET(an_ability_get_type->cl37bam_cap); 2788 if (value.cl37_adv.an_bam_speed & 1 << TEMOD2PLL_CL37_BAM_12p5GBASE_X4) 2789 PHYMOD_BAM_CL37_CAP_12P5_X4_SET(an_ability_get_type->cl37bam_cap); 2790 if (value.cl37_adv.an_bam_speed & 1 << TEMOD2PLL_CL37_BAM_12p7GBASE_X2) 2791 PHYMOD_BAM_CL37_CAP_12P7_DXGXS_SET(an_ability_get_type->cl37bam_cap); 2792 2793 if (value.cl37_adv.an_bam_speed1 & 1 << TEMOD2PLL_CL37_BAM_13GBASE_X4) 2794 PHYMOD_BAM_CL37_CAP_13G_X4_SET(an_ability_get_type->cl37bam_cap); 2795 if (value.cl37_adv.an_bam_speed1 & 1 << TEMOD2PLL_CL37_BAM_15GBASE_X4) 2796 PHYMOD_BAM_CL37_CAP_15G_X4_SET(an_ability_get_type->cl37bam_cap); 2797 if (value.cl37_adv.an_bam_speed1 & 1 << TEMOD2PLL_CL37_BAM_15p75GBASE_X2) 2798 PHYMOD_BAM_CL37_CAP_12P7_DXGXS_SET(an_ability_get_type->cl37bam_cap); 2799 if (value.cl37_adv.an_bam_speed1 & 1 << TEMOD2PLL_CL37_BAM_16GBASE_X4) 2800 PHYMOD_BAM_CL37_CAP_16G_X4_SET(an_ability_get_type->cl37bam_cap); 2801 if (value.cl37_adv.an_bam_speed1 & 1 << TEMOD2PLL_CL37_BAM_20GBASE_X4_CX4) 2802 PHYMOD_BAM_CL37_CAP_20G_X4_CX4_SET(an_ability_get_type->cl37bam_cap); 2803 if (value.cl37_adv.an_bam_speed1 & 1 << TEMOD2PLL_CL37_BAM_20GBASE_X4) 2804 PHYMOD_BAM_CL37_CAP_20G_X4_SET(an_ability_get_type->cl37bam_cap); 2805 if (value.cl37_adv.an_bam_speed1 & 1 << TEMOD2PLL_CL37_BAM_20GBASE_X2) 2806 PHYMOD_BAM_CL37_CAP_20G_X2_SET(an_ability_get_type->cl37bam_cap); 2807 if (value.cl37_adv.an_bam_speed1 & 1 << TEMOD2PLL_CL37_BAM_20GBASE_X2_CX4) 2808 PHYMOD_BAM_CL37_CAP_20G_X2_CX4_SET(an_ability_get_type->cl37bam_cap); 2809 if (value.cl37_adv.an_bam_speed1 & 1 << TEMOD2PLL_CL37_BAM_21GBASE_X4) 2810 PHYMOD_BAM_CL37_CAP_21G_X4_SET(an_ability_get_type->cl37bam_cap); 2811 if (value.cl37_adv.an_bam_speed1 & 1 << TEMOD2PLL_CL37_BAM_25p455GBASE_X4) 2812 PHYMOD_BAM_CL37_CAP_25P455G_SET(an_ability_get_type->cl37bam_cap); 2813 if (value.cl37_adv.an_bam_speed1 & 1 << TEMOD2PLL_CL37_BAM_31p5GBASE_X4) 2814 PHYMOD_BAM_CL37_CAP_31P5G_SET(an_ability_get_type->cl37bam_cap); 2815 if (value.cl37_adv.an_bam_speed1 & 1 << TEMOD2PLL_CL37_BAM_32p7GBASE_X4) 2816 PHYMOD_BAM_CL37_CAP_32P7G_SET(an_ability_get_type->cl37bam_cap); 2817 if (value.cl37_adv.an_bam_speed1 & 1 << TEMOD2PLL_CL37_BAM_40GBASE_X4) 2818 PHYMOD_BAM_CL37_CAP_40G_SET(an_ability_get_type->cl37bam_cap); 2819 2820 return PHYMOD_E_NONE; 2821 } 2822 2823 2824 int tsce_dpll_phy_autoneg_set(const phymod_phy_access_t* phy, const phymod_autoneg_control_t* an) 2825 { 2826 int num_lane_adv_encoded; 2827 phymod_firmware_lane_config_t firmware_lane_config; 2828 phymod_firmware_core_config_t firmware_core_config_tmp; 2829 int start_lane, num_lane, i ; 2830 phymod_phy_access_t phy_copy; 2831 temod2pll_an_control_t an_control; 2832 int ctrl_port = 0 ; 2833 int pll_change = 0; 2834 uint32_t current_pll_div0 = 0; 2835 uint8_t current_pll_index = 0; 2836 temod2pll_pll_mode_type pll_mode; 2837 uint32_t new_pll_div = 0; 2838 2839 /* next program the tx fir taps and driver current based on the input */ 2840 PHYMOD_IF_ERR_RETURN 2841 (phymod_util_lane_config_get(&phy->access, &start_lane, &num_lane)); 2842 2843 PHYMOD_MEMSET(&firmware_lane_config, 0x0, sizeof(firmware_lane_config)); 2844 PHYMOD_MEMSET(&firmware_core_config_tmp, 0x0, sizeof(firmware_core_config_tmp)); 2845 2846 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 2847 TSCE_DPLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 2848 phy_copy.access.lane_mask = 0x1 << start_lane; 2849 2850 if((an->flags & PHYMOD_AN_F_SET_PRIOR_ENABLE)&& an->enable) { 2851 PHYMOD_IF_ERR_RETURN 2852 (temod2pll_tsc12_control(&phy_copy.access, 0, -1)); 2853 return PHYMOD_E_NONE ; 2854 } 2855 2856 /* get the current PLL0 */ 2857 current_pll_index = phy_copy.access.pll_idx; 2858 phy_copy.access.lane_mask = 1 << start_lane; 2859 phy_copy.access.pll_idx = 0; 2860 PHYMOD_IF_ERR_RETURN 2861 (temod2pll_pll_config_get(&phy_copy.access, &pll_mode)); 2862 current_pll_div0 = (uint32_t) pll_mode; 2863 phy_copy.access.pll_idx = current_pll_index; 2864 2865 /* make sure the firmware config is set to an eenabled */ 2866 PHYMOD_IF_ERR_RETURN 2867 (tsce_dpll_phy_firmware_core_config_get(&phy_copy, &firmware_core_config_tmp)); 2868 2869 2870 switch (an->num_lane_adv) { 2871 case 1: 2872 num_lane_adv_encoded = 0; 2873 break; 2874 case 2: 2875 num_lane_adv_encoded = 1; 2876 break; 2877 case 4: 2878 num_lane_adv_encoded = 2; 2879 break; 2880 case 10: 2881 num_lane_adv_encoded = 3; 2882 break; 2883 default: 2884 return PHYMOD_E_PARAM; 2885 } 2886 2887 /*KX pd is not supported*/ 2888 an_control.pd_kx_en = 0; 2889 if (PHYMOD_AN_F_SET_CL73_PDET_KX4_ENABLE_GET(an)) { 2890 an_control.pd_kx4_en = 1; 2891 } else { 2892 an_control.pd_kx4_en = 0; 2893 } 2894 an_control.pd_2p5g_en = 0; /*for now disable*/ 2895 an_control.num_lane_adv = num_lane_adv_encoded; 2896 an_control.enable = an->enable; 2897 an_control.an_property_type = 0x0; /* for now disable */ 2898 switch (an->an_mode) { 2899 case phymod_AN_MODE_CL73: 2900 an_control.an_type = TEMOD2PLL_AN_MODE_CL73; 2901 break; 2902 case phymod_AN_MODE_CL37: 2903 an_control.an_type = TEMOD2PLL_AN_MODE_CL37; 2904 break; 2905 case phymod_AN_MODE_CL73BAM: 2906 an_control.an_type = TEMOD2PLL_AN_MODE_CL73BAM; 2907 break; 2908 case phymod_AN_MODE_CL37BAM: 2909 an_control.an_type = TEMOD2PLL_AN_MODE_CL37BAM; 2910 break; 2911 case phymod_AN_MODE_HPAM: 2912 an_control.an_type = TEMOD2PLL_AN_MODE_HPAM; 2913 break; 2914 case phymod_AN_MODE_SGMII: 2915 an_control.an_type = TEMOD2PLL_AN_MODE_SGMII; 2916 break; 2917 case phymod_AN_MODE_CL37BAM_10P9375G_VCO: 2918 an_control.an_type = TEMOD2PLL_AN_MODE_CL37BAM; 2919 break; 2920 default: 2921 if(an->an_mode ==(phymod_AN_MODE_CL37_SGMII)) { 2922 an_control.an_type = TEMOD2PLL_AN_MODE_CL37_SGMII ; 2923 } else { 2924 an_control.an_type = TEMOD2PLL_AN_MODE_CL73; 2925 } 2926 break; 2927 } 2928 2929 /* make sure the firmware config is set to an eenabled */ 2930 PHYMOD_IF_ERR_RETURN 2931 (tsce_dpll_phy_firmware_core_config_get(&phy_copy, &firmware_core_config_tmp)); 2932 2933 /* If an_mode is not CL37BAM_10P9375G_VCO, the VCO will be changed to 10G 2934 * only when the current VCO is 11G. 2935 */ 2936 if (an->an_mode != phymod_AN_MODE_CL37BAM_10P9375G_VCO) { 2937 if (current_pll_div0 == TEMOD2PLL_PLL_MODE_DIV_70) { 2938 /*recofig pll0*/ 2939 pll_change = 1; 2940 new_pll_div = TEMOD2PLL_PLL_MODE_DIV_66; 2941 } 2942 } else { 2943 if (current_pll_div0 != TEMOD2PLL_PLL_MODE_DIV_70) { 2944 pll_change = 1; 2945 new_pll_div = TEMOD2PLL_PLL_MODE_DIV_70; 2946 } 2947 } 2948 2949 /* Hold core soft reset */ 2950 if ((an->num_lane_adv == 4) && !pll_change) { 2951 PHYMOD_IF_ERR_RETURN 2952 (eagle2_tsc2pll_core_soft_reset_release(&phy_copy.access, 0)); 2953 } 2954 2955 temod2pll_disable_set(&phy->access); 2956 2957 for (i = 0; i < num_lane; i++) { 2958 if (!PHYMOD_LANEPBMP_MEMBER(phy->access.lane_mask, start_lane + i)) { 2959 continue; 2960 } 2961 phy_copy.access.lane_mask = 0x1 << (i + start_lane); 2962 PHYMOD_IF_ERR_RETURN 2963 (eagle2_tsc2pll_lane_soft_reset_release(&phy_copy.access, 0)); 2964 } 2965 2966 /*re-configure PLL if need*/ 2967 if (pll_change) { 2968 2969 2970 phy_copy.access.pll_idx = 0; 2971 temod2pll_disable_set(&phy->access); 2972 PHYMOD_IF_ERR_RETURN 2973 (eagle2_tsc2pll_core_soft_reset_release(&phy_copy.access, 0)); 2974 PHYMOD_USLEEP(500); 2975 /* set the PLL divider */ 2976 PHYMOD_IF_ERR_RETURN 2977 (eagle2_tsc2pll_pll_mode_set(&phy_copy.access, new_pll_div)); 2978 2979 PHYMOD_IF_ERR_RETURN 2980 (temod2pll_pll_reset_enable_set(&phy_copy.access, 1)); 2981 2982 PHYMOD_IF_ERR_RETURN 2983 (eagle2_tsc2pll_core_soft_reset_release(&phy_copy.access, 1)); 2984 PHYMOD_USLEEP(500); 2985 PHYMOD_IF_ERR_RETURN 2986 (temod2pll_trigger_speed_change(&phy->access)); 2987 } 2988 phy_copy.access.pll_idx = current_pll_index; 2989 2990 /* make sure the firmware config is set to an eenabled */ 2991 PHYMOD_IF_ERR_RETURN 2992 (tsce_dpll_phy_firmware_lane_config_get(&phy_copy, &firmware_lane_config)); 2993 2994 /* now based on the medium type, either sgmii or cl37 will be adjusted*/ 2995 if (!PHYMOD_AN_F_IGNORE_MEDIUM_CHECK_GET(an)) { 2996 if ((firmware_lane_config.MediaType == phymodFirmwareMediaTypePcbTraceBackPlane) && 2997 an_control.an_type == TEMOD2PLL_AN_MODE_CL37) { 2998 an_control.an_type = TEMOD2PLL_AN_MODE_SGMII; 2999 } 3000 3001 3002 if ((firmware_lane_config.MediaType == phymodFirmwareMediaTypeOptics) && 3003 an_control.an_type == TEMOD2PLL_AN_MODE_SGMII) { 3004 an_control.an_type = TEMOD2PLL_AN_MODE_CL37; 3005 } 3006 3007 } 3008 3009 if (an->enable) { 3010 firmware_lane_config.AnEnabled = 1; 3011 firmware_lane_config.LaneConfigFromPCS = 1; 3012 firmware_core_config_tmp.CoreConfigFromPCS = 1; 3013 firmware_lane_config.Cl72RestTO = 0; 3014 } else { 3015 firmware_lane_config.AnEnabled = 0; 3016 firmware_lane_config.LaneConfigFromPCS = 0; 3017 firmware_core_config_tmp.CoreConfigFromPCS = 0; 3018 firmware_lane_config.Cl72RestTO = 1; 3019 } 3020 3021 if ((an->num_lane_adv == 4) && !pll_change) { 3022 phy_copy.access.lane_mask = 0x1 << start_lane; 3023 PHYMOD_IF_ERR_RETURN 3024 (tsce_dpll_phy_firmware_core_config_set(&phy_copy, firmware_core_config_tmp)); 3025 } 3026 3027 for (i = 0; i < num_lane; i++) { 3028 if (!PHYMOD_LANEPBMP_MEMBER(phy->access.lane_mask, start_lane + i)) { 3029 continue; 3030 } 3031 phy_copy.access.lane_mask = 0x1 << (i + start_lane); 3032 PHYMOD_IF_ERR_RETURN 3033 (_tsce_dpll_phy_firmware_lane_config_set(&phy_copy, firmware_lane_config)); 3034 } 3035 /* Release core soft reset */ 3036 if ((an->num_lane_adv == 4) && !pll_change) { 3037 phy_copy.access.lane_mask = 0x1 << start_lane; 3038 PHYMOD_IF_ERR_RETURN 3039 (eagle2_tsc2pll_core_soft_reset_release(&phy_copy.access, 1)); 3040 } 3041 3042 for (i = 0; i < num_lane; i++) { 3043 if (!PHYMOD_LANEPBMP_MEMBER(phy->access.lane_mask, start_lane + i)) { 3044 continue; 3045 } 3046 phy_copy.access.lane_mask = 0x1 << (i + start_lane); 3047 PHYMOD_IF_ERR_RETURN 3048 (eagle2_tsc2pll_lane_soft_reset_release(&phy_copy.access, 1)); 3049 } 3050 3051 phy_copy.access.lane_mask = 0x1 << start_lane; 3052 PHYMOD_IF_ERR_RETURN 3053 (temod2pll_trigger_speed_change(&phy_copy.access)); 3054 3055 if (an->an_mode == phymod_AN_MODE_CL37BAM_10P9375G_VCO) { 3056 ctrl_port = 1; 3057 } else { 3058 if (an->enable) { 3059 if (an->num_lane_adv == 4) { 3060 ctrl_port = 1 ; 3061 } else { 3062 if (PHYMOD_AN_F_ALLOW_PLL_CHANGE_GET(an)) { 3063 ctrl_port = 1; 3064 } else { 3065 ctrl_port = 0 ; 3066 } 3067 } 3068 } else { 3069 ctrl_port = 0; 3070 } 3071 } 3072 3073 PHYMOD_IF_ERR_RETURN 3074 (temod2pll_set_an_port_mode(&phy_copy.access, an->enable, num_lane_adv_encoded, start_lane, ctrl_port)); 3075 3076 PHYMOD_IF_ERR_RETURN 3077 (temod2pll_autoneg_control(&phy_copy.access, &an_control)); 3078 3079 return PHYMOD_E_NONE; 3080 3081 } 3082 3083 int tsce_dpll_phy_autoneg_get(const phymod_phy_access_t* phy, phymod_autoneg_control_t* an, uint32_t* an_done) 3084 { 3085 temod2pll_an_control_t an_control; 3086 phymod_phy_access_t phy_copy; 3087 int start_lane, num_lane; 3088 int an_complete = 0; 3089 3090 /* next program the tx fir taps and driver current based on the input */ 3091 PHYMOD_IF_ERR_RETURN 3092 (phymod_util_lane_config_get(&phy->access, &start_lane, &num_lane)); 3093 3094 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 3095 TSCE_DPLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 3096 phy_copy.access.lane_mask = 0x1 << start_lane; 3097 3098 PHYMOD_MEMSET(&an_control, 0x0, sizeof(temod2pll_an_control_t)); 3099 PHYMOD_IF_ERR_RETURN 3100 (temod2pll_autoneg_control_get(&phy_copy.access, &an_control, &an_complete)); 3101 3102 if (an_control.enable) { 3103 an->enable = 1; 3104 *an_done = an_complete; 3105 } else { 3106 an->enable = 0; 3107 *an_done = 0; 3108 } 3109 switch (an_control.an_type) { 3110 case TEMOD2PLL_AN_MODE_CL73: 3111 an->an_mode = phymod_AN_MODE_CL73; 3112 break; 3113 case TEMOD2PLL_AN_MODE_CL37: 3114 an->an_mode = phymod_AN_MODE_CL37; 3115 break; 3116 case TEMOD2PLL_AN_MODE_CL73BAM: 3117 an->an_mode = phymod_AN_MODE_CL73BAM; 3118 break; 3119 case TEMOD2PLL_AN_MODE_CL37BAM: 3120 an->an_mode = phymod_AN_MODE_CL37BAM; 3121 break; 3122 case TEMOD2PLL_AN_MODE_HPAM: 3123 an->an_mode = phymod_AN_MODE_HPAM; 3124 break; 3125 case TEMOD2PLL_AN_MODE_SGMII: 3126 an->an_mode = phymod_AN_MODE_SGMII; 3127 break; 3128 default: 3129 if(an_control.an_type == TEMOD2PLL_AN_MODE_CL37_SGMII) { 3130 an->an_mode = phymod_AN_MODE_CL37_SGMII ; 3131 } else { 3132 an->an_mode = phymod_AN_MODE_NONE; 3133 } 3134 break; 3135 } 3136 3137 return PHYMOD_E_NONE; 3138 } 3139 3140 3141 int tsce_dpll_phy_autoneg_restart_set(const phymod_phy_access_t* phy, const phymod_autoneg_control_t* an) 3142 { 3143 int start_lane, num_lane ; 3144 phymod_phy_access_t phy_copy; 3145 temod2pll_an_control_t an_control; 3146 3147 PHYMOD_IF_ERR_RETURN 3148 (phymod_util_lane_config_get(&phy->access, &start_lane, &num_lane)); 3149 3150 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 3151 TSCE_DPLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 3152 phy_copy.access.lane_mask = 0x1 << start_lane; 3153 3154 if(an->an_mode == phymod_AN_MODE_CL37_SGMII) { 3155 an_control.enable = an->enable; 3156 an_control.an_type = TEMOD2PLL_AN_MODE_CL37_SGMII; 3157 PHYMOD_IF_ERR_RETURN 3158 (temod2pll_autoneg_restart(&phy_copy.access, &an_control)); 3159 } 3160 return PHYMOD_E_NONE; 3161 } 3162 3163 3164 int tsce_dpll_phy_autoneg_status_get(const phymod_phy_access_t* phy, phymod_autoneg_status_t* status) 3165 { 3166 3167 3168 /* Place your code here */ 3169 3170 3171 return PHYMOD_E_NONE; 3172 3173 } 3174 3175 3176 STATIC 3177 int _tsce_dpll_core_init_pass1(const phymod_core_access_t* core, 3178 const phymod_core_init_config_t* init_config, 3179 const phymod_core_status_t* core_status) 3180 { 3181 phymod_phy_access_t phy_access; 3182 phymod_core_access_t core_copy; 3183 uint32_t uc_active = 0 ; 3184 3185 TSCE_DPLL_CORE_TO_PHY_ACCESS(&phy_access, core); 3186 PHYMOD_MEMCPY(&core_copy, core, sizeof(core_copy)); 3187 core_copy.access.lane_mask = 0x1; 3188 3189 core_copy.access.pll_idx = 0; 3190 PHYMOD_IF_ERR_RETURN 3191 (temod2pll_pmd_reset_seq(&core_copy.access, core_status->pmd_active)); 3192 PHYMOD_IF_ERR_RETURN 3193 (temod2pll_pmd_reset_seq_dp(&core_copy.access, core_status->pmd_active)); 3194 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_uc_active_get(&core_copy.access, &uc_active)) ; 3195 if(uc_active) { 3196 return(PHYMOD_E_NONE); 3197 } 3198 3199 /* need to set the heart beat default is for 156.25M */ 3200 PHYMOD_IF_ERR_RETURN (temod2pll_refclk_set(&core_copy.access, 3201 init_config->interface.ref_clock)); 3202 3203 if (_tsce_dpll_core_firmware_load(&core_copy, init_config->firmware_load_method, init_config->firmware_loader)) { 3204 PHYMOD_DEBUG_ERROR(("devad 0x%"PRIx32" lane 0x%"PRIx32": UC firmware-load failed\n", core->access.addr, core->access.lane_mask)); 3205 PHYMOD_IF_ERR_RETURN (PHYMOD_E_INIT); 3206 } 3207 return (PHYMOD_E_NONE); 3208 } 3209 3210 STATIC 3211 int _tsce_dpll_core_init_pass2(const phymod_core_access_t* core, 3212 const phymod_core_init_config_t* init_config, 3213 const phymod_core_status_t* core_status) 3214 { 3215 phymod_phy_access_t phy_access, phy_access_copy; 3216 phymod_core_access_t core_copy; 3217 phymod_firmware_core_config_t firmware_core_config_tmp; 3218 uint32_t vco_rate; 3219 3220 TSCE_DPLL_CORE_TO_PHY_ACCESS(&phy_access, core); 3221 PHYMOD_MEMCPY(&core_copy, core, sizeof(core_copy)); 3222 core_copy.access.lane_mask = 0x1; 3223 3224 phy_access_copy = phy_access; 3225 phy_access_copy.access = core->access; 3226 phy_access_copy.access.lane_mask = 0x1; 3227 phy_access_copy.type = core->type; 3228 3229 #ifndef TSCE_DPLL_PMD_VERIFY_UCODE_LOAD 3230 /* next we need to check if the load is correct or not */ 3231 if (eagle2_tsc2pll_ucode_load_verify(&core_copy.access, (uint8_t *) &eagle2_tsc2pll_ucode, eagle2_tsc2pll_ucode_len)) { 3232 PHYMOD_DEBUG_ERROR(("devad 0x%x lane 0x%x: UC load-verify failed\n", core->access.addr, core->access.lane_mask)); 3233 PHYMOD_IF_ERR_RETURN (PHYMOD_E_INIT); 3234 } 3235 #endif /* TSCE_DPLL_PMD_VERIFY_UCODE_LOAD */ 3236 3237 PHYMOD_IF_ERR_RETURN 3238 (eagle2_tsc2pll_pmd_ln_h_rstb_pkill_override( &phy_access_copy.access, 0x1)); 3239 3240 /* next we need to set the uc active and release uc */ 3241 PHYMOD_IF_ERR_RETURN 3242 (eagle2_tsc2pll_uc_active_set(&core_copy.access ,1)); 3243 3244 /* release the uc reset */ 3245 PHYMOD_IF_ERR_RETURN 3246 (eagle2_uc_reset(&core_copy.access ,1)); 3247 /* we need to wait at least 10ms for the uc to settle */ 3248 /* PHYMOD_USLEEP(10000); */ 3249 3250 if(PHYMOD_CORE_INIT_F_FIRMWARE_LOAD_VERIFY_GET(init_config)) { 3251 #ifndef TSCE_DPLL_PMD_VERIFY_UCODE_LOAD 3252 /* poll the ready bit in 10 ms */ 3253 eagle2_tsc2pll_poll_uc_dsc_ready_for_cmd_equals_1(&phy_access_copy.access, 1); 3254 #else 3255 PHYMOD_IF_ERR_RETURN( 3256 eagle2_tsc2pll_ucode_crc_verify( &core_copy.access, eagle2_tsc2pll_ucode_len,eagle2_tsc2pll_ucode_crc)); 3257 #endif /* TSCE_DPLL_PMD_VERIFY_UCODE_LOAD */ 3258 } 3259 3260 PHYMOD_IF_ERR_RETURN( 3261 eagle2_tsc2pll_pmd_ln_h_rstb_pkill_override( &phy_access_copy.access, 0x0)); 3262 3263 3264 /* now config the lane mapping and polarity */ 3265 PHYMOD_IF_ERR_RETURN 3266 (tsce_dpll_core_lane_map_set(core, &init_config->lane_map)); 3267 3268 #if 0 3269 /* NEED TO REVISIT */ 3270 PHYMOD_IF_ERR_RETURN 3271 (temod2pll_autoneg_set_init(&core->access, &an)); 3272 #endif 3273 PHYMOD_IF_ERR_RETURN 3274 (temod2pll_autoneg_timer_init(&core->access)); 3275 3276 /* mld has 2 reg copies */ 3277 phy_access_copy.access.lane_mask = 0xf; 3278 PHYMOD_IF_ERR_RETURN 3279 (temod2pll_mld_am_timers_set(&phy_access_copy.access)); 3280 3281 phy_access_copy.access.lane_mask = 0x1; 3282 3283 PHYMOD_IF_ERR_RETURN 3284 (temod2pll_master_port_num_set(&core->access, 0)); 3285 PHYMOD_IF_ERR_RETURN 3286 (temod2pll_cl48_lfrfli_init(&core->access)); 3287 3288 core_copy.access.pll_idx = 0; 3289 PHYMOD_IF_ERR_RETURN 3290 (eagle2_tsc2pll_core_soft_reset_release(&core_copy.access, 0)); 3291 core_copy.access.pll_idx = 1; 3292 PHYMOD_IF_ERR_RETURN 3293 (eagle2_tsc2pll_core_soft_reset_release(&core_copy.access, 0)); 3294 3295 /* don't overide the fw that set in config set if not specified */ 3296 firmware_core_config_tmp = init_config->firmware_core_config; 3297 firmware_core_config_tmp.CoreConfigFromPCS = 0; 3298 /* CONFIG pll0*/ 3299 phy_access_copy.access.pll_idx = 0; 3300 PHYMOD_IF_ERR_RETURN 3301 (temod2pll_pll_config_set(&phy_access_copy.access, init_config->pll0_div_init_value, init_config->interface.ref_clock)); 3302 3303 PHYMOD_IF_ERR_RETURN 3304 (_tsce_dpll_pll_to_vco_rate(init_config->pll0_div_init_value, init_config->interface.ref_clock, &vco_rate)); 3305 firmware_core_config_tmp.VcoRate = MHZ_TO_VCO_RATE(vco_rate); 3306 PHYMOD_IF_ERR_RETURN 3307 (tsce_dpll_phy_firmware_core_config_set(&phy_access_copy, firmware_core_config_tmp)); 3308 3309 /* CONFIG pll1*/ 3310 phy_access_copy.access.pll_idx = 1; 3311 PHYMOD_IF_ERR_RETURN 3312 (temod2pll_pll_config_set(&phy_access_copy.access, init_config->pll1_div_init_value, init_config->interface.ref_clock)); 3313 3314 PHYMOD_IF_ERR_RETURN 3315 (_tsce_dpll_pll_to_vco_rate(init_config->pll1_div_init_value, init_config->interface.ref_clock, &vco_rate)); 3316 firmware_core_config_tmp.VcoRate = MHZ_TO_VCO_RATE(vco_rate); 3317 PHYMOD_IF_ERR_RETURN 3318 (tsce_dpll_phy_firmware_core_config_set(&phy_access_copy, firmware_core_config_tmp)); 3319 3320 3321 PHYMOD_IF_ERR_RETURN 3322 (temod2pll_cl74_chng_default (&core_copy.access)); 3323 3324 /* release core soft reset */ 3325 core_copy.access.pll_idx = 0; 3326 PHYMOD_IF_ERR_RETURN 3327 (eagle2_tsc2pll_core_soft_reset_release(&core_copy.access, 1)); 3328 core_copy.access.pll_idx = 1; 3329 PHYMOD_IF_ERR_RETURN 3330 (eagle2_tsc2pll_core_soft_reset_release(&core_copy.access, 1)); 3331 3332 return PHYMOD_E_NONE; 3333 } 3334 int tsce_dpll_core_init(const phymod_core_access_t* core, const phymod_core_init_config_t* init_config, const phymod_core_status_t* core_status) 3335 { 3336 if ( (!PHYMOD_CORE_INIT_F_EXECUTE_PASS1_GET(init_config) && 3337 !PHYMOD_CORE_INIT_F_EXECUTE_PASS2_GET(init_config)) || 3338 PHYMOD_CORE_INIT_F_EXECUTE_PASS1_GET(init_config)) { 3339 PHYMOD_IF_ERR_RETURN 3340 (_tsce_dpll_core_init_pass1(core, init_config, core_status)); 3341 3342 if (PHYMOD_CORE_INIT_F_EXECUTE_PASS1_GET(init_config)) { 3343 return PHYMOD_E_NONE; 3344 } 3345 } 3346 3347 if ( (!PHYMOD_CORE_INIT_F_EXECUTE_PASS1_GET(init_config) && 3348 !PHYMOD_CORE_INIT_F_EXECUTE_PASS2_GET(init_config)) || 3349 PHYMOD_CORE_INIT_F_EXECUTE_PASS2_GET(init_config)) { 3350 PHYMOD_IF_ERR_RETURN 3351 (_tsce_dpll_core_init_pass2(core, init_config, core_status)); 3352 } 3353 3354 return PHYMOD_E_NONE; 3355 3356 } 3357 3358 3359 int tsce_dpll_phy_pll_multiplier_get(const phymod_phy_access_t* phy, uint32_t* core_vco_pll_multiplier) 3360 { 3361 3362 3363 /* Place your code here */ 3364 3365 3366 return PHYMOD_E_NONE; 3367 3368 } 3369 3370 3371 int tsce_dpll_phy_init(const phymod_phy_access_t* phy, const phymod_phy_init_config_t* init_config) 3372 { 3373 const phymod_access_t *pm_acc = &phy->access; 3374 phymod_phy_access_t pm_phy_copy; 3375 int start_lane, num_lane, i; 3376 int lane_bkup; 3377 phymod_polarity_t tmp_pol; 3378 PHYMOD_MEMSET(&tmp_pol, 0x0, sizeof(tmp_pol)); 3379 PHYMOD_MEMCPY(&pm_phy_copy, phy, sizeof(pm_phy_copy)); 3380 TSCE_DPLL_PHY_ACCESS_PLLIDX_SET(&pm_phy_copy); 3381 3382 /* next program the tx fir taps and driver current based on the input */ 3383 PHYMOD_IF_ERR_RETURN 3384 (phymod_util_lane_config_get(pm_acc, &start_lane, &num_lane)); 3385 /* per lane based reset release */ 3386 PHYMOD_IF_ERR_RETURN 3387 (temod2pll_pmd_x4_reset(pm_acc)); 3388 3389 /* poll for per lane uc_dsc_ready */ 3390 lane_bkup = pm_phy_copy.access.lane_mask; 3391 for (i = 0; i < num_lane; i++) { 3392 if (!PHYMOD_LANEPBMP_MEMBER(phy->access.lane_mask, start_lane + i)) { 3393 continue; 3394 } 3395 pm_phy_copy.access.lane_mask = 1 << (start_lane + i); 3396 PHYMOD_IF_ERR_RETURN 3397 (eagle2_tsc2pll_lane_soft_reset_release(&pm_phy_copy.access, 1)); 3398 } 3399 pm_phy_copy.access.lane_mask = lane_bkup; 3400 3401 /* program the rx/tx polarity */ 3402 for (i = 0; i < num_lane; i++) { 3403 if (!PHYMOD_LANEPBMP_MEMBER(phy->access.lane_mask, start_lane + i)) { 3404 continue; 3405 } 3406 pm_phy_copy.access.lane_mask = 0x1 << (i + start_lane); 3407 tmp_pol.tx_polarity = (init_config->polarity.tx_polarity) >> i & 0x1; 3408 tmp_pol.rx_polarity = (init_config->polarity.rx_polarity) >> i & 0x1; 3409 PHYMOD_IF_ERR_RETURN 3410 (tsce_dpll_phy_polarity_set(&pm_phy_copy, &tmp_pol)); 3411 PHYMOD_IF_ERR_RETURN 3412 (tsce_dpll_phy_tx_set(&pm_phy_copy, &init_config->tx[i])); 3413 } 3414 3415 pm_phy_copy.access.lane_mask = 0x1; 3416 3417 PHYMOD_IF_ERR_RETURN 3418 (temod2pll_update_port_mode(pm_acc)); 3419 3420 PHYMOD_IF_ERR_RETURN 3421 (temod2pll_rx_lane_control_set(pm_acc, 1)); 3422 PHYMOD_IF_ERR_RETURN 3423 (temod2pll_tx_lane_control_set(pm_acc, TEMOD2PLL_TX_LANE_RESET_TRAFFIC_ENABLE)); /* TX_LANE_CONTROL */ 3424 3425 return PHYMOD_E_NONE; 3426 } 3427 3428 3429 int tsce_dpll_phy_loopback_set(const phymod_phy_access_t* phy, phymod_loopback_mode_t loopback, uint32_t enable) 3430 { 3431 int start_lane, num_lane; 3432 int rv = PHYMOD_E_NONE; 3433 int i = 0; 3434 uint32_t cl72_en; 3435 phymod_phy_access_t phy_copy; 3436 3437 const phymod_access_t *pm_acc; 3438 pm_acc = &phy->access; 3439 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 3440 TSCE_DPLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 3441 3442 /* next figure out the lane num and start_lane based on the input */ 3443 PHYMOD_IF_ERR_RETURN 3444 (phymod_util_lane_config_get(&phy->access, &start_lane, &num_lane)); 3445 3446 switch (loopback) { 3447 case phymodLoopbackGlobal : 3448 PHYMOD_IF_ERR_RETURN 3449 (tsce_dpll_phy_cl72_get(&phy_copy, &cl72_en)); 3450 if((cl72_en == 1) && (enable == 1)) { 3451 PHYMOD_DEBUG_ERROR(("adr=%0"PRIx32",lane 0x%x: Error! pcs gloop not supported with cl72 enabled\n", pm_acc->addr, start_lane)); 3452 break; 3453 } 3454 PHYMOD_IF_ERR_RETURN(temod2pll_tx_loopback_control(&phy_copy.access, enable, start_lane, num_lane)); 3455 break; 3456 case phymodLoopbackGlobalPMD : 3457 PHYMOD_IF_ERR_RETURN 3458 (tsce_dpll_phy_cl72_get(&phy_copy, &cl72_en)); 3459 if((cl72_en == 1) && (enable == 1)) { 3460 PHYMOD_DEBUG_ERROR(("adr=%0"PRIx32",lane 0x%x: Error! pmd gloop not supported with cl72 enabled\n", pm_acc->addr, start_lane)); 3461 break; 3462 } 3463 for (i = 0; i < num_lane; i++) { 3464 if (!PHYMOD_LANEPBMP_MEMBER(phy->access.lane_mask, start_lane + i)) { 3465 continue; 3466 } 3467 phy_copy.access.lane_mask = 0x1 << (i + start_lane); 3468 PHYMOD_IF_ERR_RETURN(temod2pll_tx_squelch_set(&phy_copy.access, enable)); 3469 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_dig_lpbk(&phy_copy.access, (uint8_t) enable)); 3470 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_pmd_force_signal_detect(&phy_copy.access, (int) enable)); 3471 PHYMOD_IF_ERR_RETURN(temod2pll_rx_lane_control_set(&phy_copy.access, 1)); 3472 } 3473 break; 3474 case phymodLoopbackRemotePMD : 3475 for (i = 0; i < num_lane; i++) { 3476 if (!PHYMOD_LANEPBMP_MEMBER(phy->access.lane_mask, start_lane + i)) { 3477 continue; 3478 } 3479 phy_copy.access.lane_mask = 0x1 << (i + start_lane); 3480 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_rmt_lpbk(&phy_copy.access, (uint8_t)enable)); 3481 } 3482 break; 3483 case phymodLoopbackRemotePCS : 3484 /* PHYMOD_IF_ERR_RETURN(temod2pll_rx_loopback_control(&phy->access, enable, enable, enable)); */ /* RAVI */ 3485 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_CONFIG, 3486 (_PHYMOD_MSG("PCS Remote LoopBack not supported"))); 3487 break; 3488 default : 3489 break; 3490 } 3491 return rv; 3492 } 3493 3494 int tsce_dpll_phy_loopback_get(const phymod_phy_access_t* phy, phymod_loopback_mode_t loopback, uint32_t* enable) 3495 { 3496 uint32_t enable_core; 3497 int start_lane, num_lane; 3498 phymod_phy_access_t phy_copy; 3499 3500 *enable = 0; 3501 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 3502 TSCE_DPLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 3503 3504 /* next figure out the lane num and start_lane based on the input */ 3505 PHYMOD_IF_ERR_RETURN 3506 (phymod_util_lane_config_get(&phy->access, &start_lane, &num_lane)); 3507 3508 switch (loopback) { 3509 case phymodLoopbackGlobal : 3510 PHYMOD_IF_ERR_RETURN(temod2pll_tx_loopback_get(&phy_copy.access, &enable_core)); 3511 *enable = (enable_core >> start_lane) & 0x1; 3512 break; 3513 case phymodLoopbackGlobalPMD : 3514 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_pmd_loopback_get(&phy_copy.access, enable)); 3515 break; 3516 case phymodLoopbackRemotePMD : 3517 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_rmt_lpbk_get(&phy_copy.access, enable)); 3518 break; 3519 case phymodLoopbackRemotePCS : 3520 /* PHYMOD_IF_ERR_RETURN(temod2pll_rx_loopback_control(&phy->access, enable, enable, enable)); */ /* RAVI */ 3521 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_CONFIG, 3522 (_PHYMOD_MSG("PCS Remote LoopBack not supported"))); 3523 break; 3524 default : 3525 break; 3526 } 3527 return PHYMOD_E_NONE; 3528 } 3529 3530 3531 int tsce_dpll_phy_rx_pmd_locked_get(const phymod_phy_access_t* phy, uint32_t* rx_pmd_locked) 3532 { 3533 phymod_phy_access_t phy_copy; 3534 3535 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 3536 TSCE_DPLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 3537 PHYMOD_IF_ERR_RETURN(temod2pll_pmd_lock_get(&phy_copy.access, rx_pmd_locked)); 3538 return PHYMOD_E_NONE; 3539 } 3540 3541 3542 int tsce_dpll_phy_rx_signal_detect_get(const phymod_phy_access_t* phy, uint32_t* rx_signal_detect) 3543 { 3544 uint32_t local_tx_signal_det; 3545 phymod_phy_access_t phy_copy; 3546 3547 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 3548 TSCE_DPLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 3549 PHYMOD_IF_ERR_RETURN 3550 (eagle2_tsc2pll_signal_detect(&phy_copy.access, &local_tx_signal_det)); 3551 *rx_signal_detect = local_tx_signal_det; 3552 return PHYMOD_E_NONE; 3553 } 3554 3555 3556 int tsce_dpll_phy_link_status_get(const phymod_phy_access_t* phy, uint32_t* link_status) 3557 { 3558 phymod_phy_access_t phy_copy; 3559 3560 3561 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 3562 TSCE_DPLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 3563 3564 PHYMOD_IF_ERR_RETURN(temod2pll_get_pcs_latched_link_status(&phy_copy.access, link_status)); 3565 return PHYMOD_E_NONE; 3566 } 3567 3568 /*PLL index should be assembled, when the function is invoked. 3569 Default PLL index is 0. 3570 */ 3571 int tsce_dpll_phy_reg_read(const phymod_phy_access_t* phy, uint32_t reg_addr, uint32_t* val) 3572 { 3573 phymod_phy_access_t phy_copy; 3574 3575 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 3576 3577 PHYMOD_IF_ERR_RETURN(phymod_tsc_iblk_read(&phy_copy.access, reg_addr, val)); 3578 return PHYMOD_E_NONE; 3579 3580 } 3581 3582 /*PLL index should be assembled, when the function is invoked. 3583 Default PLL index is 0. 3584 */ 3585 int tsce_dpll_phy_reg_write(const phymod_phy_access_t* phy, uint32_t reg_addr, uint32_t val) 3586 { 3587 phymod_phy_access_t phy_copy; 3588 3589 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 3590 3591 PHYMOD_IF_ERR_RETURN(phymod_tsc_iblk_write(&phy_copy.access, reg_addr, val)); 3592 return PHYMOD_E_NONE; 3593 } 3594 3595 3596 int tsce_dpll_phy_eye_margin_est_get(const phymod_phy_access_t* phy, phymod_eye_margin_mode_t eye_margin_mode, uint32_t* value) 3597 { 3598 int start_lane, num_lane; 3599 phymod_phy_access_t phy_copy; 3600 int hz_l, hz_r, vt_u, vt_d; 3601 3602 3603 /* first get the start_lane */ 3604 PHYMOD_IF_ERR_RETURN 3605 (phymod_util_lane_config_get(&phy->access, &start_lane, &num_lane)); 3606 3607 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 3608 TSCE_DPLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 3609 phy_copy.access.lane_mask = 0x1 << start_lane; 3610 3611 PHYMOD_IF_ERR_RETURN 3612 (eagle2_tsc2pll_get_eye_margin_est(&phy_copy.access, &hz_l, &hz_r, &vt_u, &vt_d)); 3613 3614 switch (eye_margin_mode) { 3615 case phymod_eye_marign_HZ_L: 3616 *value = hz_l; 3617 break; 3618 case phymod_eye_marign_HZ_R: 3619 *value = hz_r; 3620 break; 3621 case phymod_eye_marign_VT_U: 3622 *value = vt_u; 3623 break; 3624 case phymod_eye_marign_VT_D: 3625 *value = vt_d; 3626 break; 3627 default: 3628 *value = 0; 3629 break; 3630 } 3631 3632 return PHYMOD_E_NONE; 3633 } 3634 int tsce_dpll_timesync_enable_set(const phymod_phy_access_t* phy, uint32_t flags, uint32_t enable) 3635 { 3636 phymod_phy_access_t phy_copy; 3637 3638 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 3639 TSCE_DPLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 3640 PHYMOD_IF_ERR_RETURN 3641 (temod2pll_1588_ts_enable_set(&phy_copy.access, enable)); 3642 return PHYMOD_E_NONE; 3643 } 3644 int tsce_dpll_timesync_enable_get(const phymod_phy_access_t* phy, uint32_t flags, uint32_t* enable) 3645 { 3646 phymod_phy_access_t phy_copy; 3647 3648 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 3649 TSCE_DPLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 3650 PHYMOD_IF_ERR_RETURN 3651 (temod2pll_1588_ts_enable_get(&phy_copy.access, enable)); 3652 3653 return PHYMOD_E_NONE; 3654 } 3655 3656 /*Set/Get timesync ts_offset*/ 3657 int tsce_dpll_timesync_offset_set(const phymod_core_access_t* core, uint32_t ts_offset) 3658 { 3659 phymod_core_access_t core_copy; 3660 3661 PHYMOD_MEMCPY(&core_copy, core, sizeof(core_copy)); 3662 TSCE_DPLL_PHY_ACCESS_PLLIDX_SET(&core_copy); 3663 PHYMOD_IF_ERR_RETURN 3664 (temod2pll_1588_ts_offset_set(&core_copy.access, ts_offset)); 3665 return PHYMOD_E_NONE; 3666 } 3667 3668 /*Set timesync adjust*/ 3669 int tsce_dpll_timesync_adjust_set(const phymod_phy_access_t* phy, phymod_timesync_compensation_mode_t timesync_am_norm_mode) 3670 { 3671 phymod_phy_access_t phy_copy; 3672 3673 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 3674 TSCE_DPLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 3675 3676 /*Set sfd_ts_en, crc_calc_mode, cl36_sop_adjust*/ 3677 PHYMOD_IF_ERR_RETURN 3678 (temod2pll_1588_pcs_control_set(&phy_copy.access)); 3679 /*set flck*/ 3680 PHYMOD_IF_ERR_RETURN 3681 (temod2pll_1588_fclk_set(&phy_copy.access)); 3682 /*set ui values*/ 3683 PHYMOD_IF_ERR_RETURN 3684 (temod2pll_1588_ui_values_set(&phy_copy.access)); 3685 /*Set RX/TX pmd fixed latency*/ 3686 PHYMOD_IF_ERR_RETURN 3687 (temod2pll_1588_txrx_fixed_latency_set(&phy_copy.access)); 3688 /*Program deskew adjustment for multi-lane ports */ 3689 if (timesync_am_norm_mode != phymodTimesyncCompensationModeNone) { 3690 PHYMOD_IF_ERR_RETURN 3691 (temod2pll_1588_rx_deskew_set(&phy_copy.access, timesync_am_norm_mode)); 3692 } 3693 return PHYMOD_E_NONE; 3694 } 3695 3696 int tsce_dpll_timesync_tx_info_get(const phymod_phy_access_t* phy, phymod_ts_fifo_status_t* ts_tx_info) 3697 { 3698 phymod_phy_access_t phy_copy; 3699 temod2pll_ts_tx_info_t local_ts_tx_info; 3700 3701 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 3702 TSCE_DPLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 3703 PHYMOD_MEMSET(&local_ts_tx_info, 0, sizeof(temod2pll_ts_tx_info_t)); 3704 3705 PHYMOD_IF_ERR_RETURN(temod2pll_1588_tx_info_get(&phy_copy.access, &local_ts_tx_info)); 3706 3707 ts_tx_info->ts_in_fifo_lo = ((uint32_t)(local_ts_tx_info.ts_val_hi << 16)) | ((uint32_t)local_ts_tx_info.ts_val_lo); 3708 ts_tx_info->ts_in_fifo_hi = 0; 3709 ts_tx_info->ts_seq_id = (uint32_t)local_ts_tx_info.ts_seq_id; 3710 ts_tx_info->ts_sub_nanosec = (uint32_t)local_ts_tx_info.ts_sub_nanosec; 3711 3712 return PHYMOD_E_NONE; 3713 } 3714 3715 int tsce_dpll_phy_bond_in_pwrdn_override(const phymod_phy_access_t* phy, uint32_t enable) 3716 { 3717 phymod_phy_access_t phy_copy; 3718 3719 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 3720 TSCE_DPLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 3721 3722 PHYMOD_IF_ERR_RETURN 3723 (temod2pll_bond_in_pwrdn_override(&phy_copy.access, enable)); 3724 return PHYMOD_E_NONE; 3725 } 3726 3727 int tsce_dpll_phy_hg2_codec_control_set(const phymod_phy_access_t* phy, 3728 phymod_phy_hg2_codec_t hg2_codec) 3729 { 3730 temod2pll_hg2_codec_t local_copy; 3731 switch (hg2_codec) { 3732 case phymodBcmHG2CodecOff: 3733 local_copy = TEMOD2PLL_HG2_CODEC_OFF; 3734 break; 3735 case phymodBcmHG2CodecOnWith8ByteIPG: 3736 local_copy = TEMOD2PLL_HG2_CODEC_ON_8BYTE_IPG; 3737 break; 3738 case phymodBcmHG2CodecOnWith9ByteIPG: 3739 local_copy = TEMOD2PLL_HG2_CODEC_ON_9BYTE_IPG; 3740 break; 3741 default: 3742 local_copy = TEMOD2PLL_HG2_CODEC_OFF; 3743 break; 3744 } 3745 PHYMOD_IF_ERR_RETURN(temod2pll_hg2_codec_set(&phy->access, local_copy)); 3746 return PHYMOD_E_NONE; 3747 } 3748 3749 int tsce_dpll_phy_hg2_codec_control_get(const phymod_phy_access_t* phy, 3750 phymod_phy_hg2_codec_t* hg2_codec) 3751 { 3752 temod2pll_hg2_codec_t local_copy; 3753 3754 PHYMOD_IF_ERR_RETURN(temod2pll_hg2_codec_get(&phy->access, &local_copy)); 3755 3756 switch (local_copy) { 3757 case TEMOD2PLL_HG2_CODEC_OFF: 3758 *hg2_codec = phymodBcmHG2CodecOff; 3759 break; 3760 case TEMOD2PLL_HG2_CODEC_ON_8BYTE_IPG: 3761 *hg2_codec = phymodBcmHG2CodecOnWith8ByteIPG; 3762 break; 3763 case TEMOD2PLL_HG2_CODEC_ON_9BYTE_IPG: 3764 *hg2_codec = phymodBcmHG2CodecOnWith9ByteIPG; 3765 break; 3766 default: 3767 *hg2_codec = phymodBcmHG2CodecOff; 3768 break; 3769 } 3770 return PHYMOD_E_NONE; 3771 } 3772 3773 int tsce_dpll_phy_rx_ppm_get(const phymod_phy_access_t* phy, int16_t* rx_ppm) 3774 { 3775 int start_lane, num_lane; 3776 phymod_phy_access_t pm_phy_copy; 3777 3778 PHYMOD_MEMCPY(&pm_phy_copy, phy, sizeof(pm_phy_copy)); 3779 3780 PHYMOD_IF_ERR_RETURN 3781 (phymod_util_lane_config_get(&phy->access, &start_lane, &num_lane)); 3782 3783 pm_phy_copy.access.lane_mask = 1 << start_lane; 3784 PHYMOD_IF_ERR_RETURN 3785 (eagle2_tsc2pll_rx_ppm(&pm_phy_copy.access, rx_ppm)); 3786 3787 return PHYMOD_E_NONE; 3788 } 3789 3790 int tsce_dpll_phy_synce_clk_ctrl_set(const phymod_phy_access_t* phy, 3791 phymod_synce_clk_ctrl_t cfg) 3792 { 3793 phymod_phy_access_t phy_copy; 3794 int start_lane, num_lane; 3795 3796 PHYMOD_IF_ERR_RETURN 3797 (phymod_util_lane_config_get(&phy->access, &start_lane, &num_lane)); 3798 3799 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 3800 phy_copy.access.lane_mask = 0x1 << start_lane; 3801 3802 PHYMOD_IF_ERR_RETURN 3803 (temod2pll_synce_stg0_mode_set(&phy_copy.access, cfg.stg0_mode)); 3804 3805 PHYMOD_IF_ERR_RETURN 3806 (temod2pll_synce_stg1_mode_set(&phy_copy.access, cfg.stg1_mode)); 3807 3808 PHYMOD_IF_ERR_RETURN 3809 (temod2pll_synce_clk_ctrl_set(&phy_copy.access, cfg.sdm_val)); 3810 3811 return PHYMOD_E_NONE; 3812 } 3813 3814 int tsce_dpll_phy_synce_clk_ctrl_get(const phymod_phy_access_t* phy, 3815 phymod_synce_clk_ctrl_t *cfg) 3816 { 3817 PHYMOD_IF_ERR_RETURN 3818 (temod2pll_synce_stg0_mode_get(&phy->access, &(cfg->stg0_mode))); 3819 3820 PHYMOD_IF_ERR_RETURN 3821 (temod2pll_synce_stg1_mode_get(&phy->access, &(cfg->stg1_mode))); 3822 3823 PHYMOD_IF_ERR_RETURN 3824 (temod2pll_synce_clk_ctrl_get(&phy->access, &(cfg->sdm_val))); 3825 3826 return PHYMOD_E_NONE; 3827 }