temod_dpll.h (19202B)
1 /*---------------------------------------------------------------------- 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * Broadcom Corporation 8 * Proprietary and Confidential information 9 * All rights reserved 10 * This source file is the property of Broadcom Corporation, and 11 * may not be copied or distributed in any isomorphic form without the 12 * prior written consent of Broadcom Corporation. 13 *---------------------------------------------------------------------- 14 * Description: define enumerators 15 *----------------------------------------------------------------------*/ 16 /* 17 * 18 * $Copyright: 19 * All Rights Reserved.$ 20 */ 21 #ifndef _TEMOD2PLL_H_ 22 #define _TEMOD2PLL_H_ 23 24 #ifndef _DV_TB_ 25 #define _SDK_TEMOD2PLL_ 1 26 #endif 27 28 #ifdef _SDK_TEMOD2PLL_ 29 #include <phymod/phymod.h> 30 #endif 31 32 #ifndef PHYMOD_ST 33 #ifdef _SDK_TEMOD2PLL_ 34 #define PHYMOD_ST const phymod_access_t 35 #else 36 #define PHYMOD_ST temod_st 37 #endif /* _SDK_TEMOD2PLL_ */ 38 #endif /* PHYMOD_ST */ 39 40 #ifdef _DV_TB_ 41 #include <stdint.h> 42 #include <stdio.h> 43 #include <string.h> 44 #include <stdlib.h> 45 #include "errno.h" 46 #endif 47 48 /* So far 4 bits debug mask are used by TMOD */ 49 /* Moved to temod_device.h chip specific debug. 50 #define TEMOD2PLL_DBG_REGACC (1L << 3) * Print all register accesses * 51 #define TEMOD2PLL_DBG_FUNCVALOUT (1L << 2) * All values returned by Tier1* 52 #define TEMOD2PLL_DBG_FUNCVALIN (1L << 1) * All values pumped into Tier1* 53 #define TEMOD2PLL_DBG_FUNC (1L << 0) * Every time we enter a Tier1* 54 */ 55 56 #define TEMOD2PLL_OVERRIDE_CFG 0x80000000 57 #define TEMOD2PLL_CL73_ABILITY_2P5G_POSITION (11) 58 #define TEMOD2PLL_CL73_ABILITY_5G_POSITION (12) 59 typedef enum { 60 TEMOD2PLL_AN_MODE_CL73 = 0, 61 TEMOD2PLL_AN_MODE_CL37, 62 TEMOD2PLL_AN_MODE_CL73BAM, 63 TEMOD2PLL_AN_MODE_CL37BAM, 64 TEMOD2PLL_AN_MODE_SGMII , 65 TEMOD2PLL_AN_MODE_HPAM , /* this macro needed to be identical to temod_an_type */ 66 TEMOD2PLL_AN_MODE_CL37_SGMII, 67 TEMOD2PLL_AN_MODE_NONE, 68 TEMOD2PLL_AN_MODE_TYPE_COUNT 69 }temod2pll_an_mode_type_t; 70 71 typedef enum { 72 TEMOD2PLL_TX_LANE_RESET = 0, 73 TEMOD2PLL_TX_LANE_TRAFFIC_ENABLE = 1, 74 TEMOD2PLL_TX_LANE_TRAFFIC_DISABLE = 2, 75 TEMOD2PLL_TX_LANE_RESET_TRAFFIC_ENABLE = 3, 76 TEMOD2PLL_TX_LANE_RESET_TRAFFIC_DISABLE = 4, 77 TEMOD2PLL_TX_LANE_TYPE_COUNT 78 }tx_lane_disable_type_t; 79 80 typedef struct temod2pll_an_control_s { 81 temod2pll_an_mode_type_t an_type; 82 uint16_t num_lane_adv; 83 uint16_t enable; 84 uint16_t pd_kx_en; 85 uint16_t pd_kx4_en; 86 uint16_t pd_2p5g_en; 87 an_property_enable an_property_type; 88 } temod2pll_an_control_t; 89 90 typedef enum { 91 TEMOD2PLL_CL73_100GBASE_CR10 = 0, 92 TEMOD2PLL_CL73_40GBASE_CR4, 93 TEMOD2PLL_CL73_40GBASE_KR4, 94 TEMOD2PLL_CL73_10GBASE_KR, 95 TEMOD2PLL_CL73_10GBASE_KX4, 96 TEMOD2PLL_CL73_1000BASE_KX, 97 TEMOD2PLL_CL73_2p5GBASE_X, 98 TEMOD2PLL_CL73_5GBASE_KR1, 99 TEMOD2PLL_CL73_SPEED_COUNT 100 }temod2pll_cl73_speed_t; 101 102 typedef enum { 103 TEMOD2PLL_CL73_BAM_20GBASE_KR2 = 0, 104 TEMOD2PLL_CL73_BAM_20GBASE_CR2, 105 TEMOD2PLL_CL73_BAM_SPEED_COUNT 106 }temod2pll_cl73_bam_speed_t; 107 108 typedef enum { 109 TEMOD2PLL_CL37_SGMII_10M = 0, 110 TEMOD2PLL_CL37_SGMII_100M, 111 TEMOD2PLL_CL37_SGMII_1000M, 112 TEMOD2PLL_CL37_SGMII_SPEED_COUNT 113 }temod2pll_cl37_sgmii_speed_t; 114 115 116 typedef enum { 117 TEMOD2PLL_CL37_BAM_13GBASE_X4 = 0, 118 TEMOD2PLL_CL37_BAM_15GBASE_X4, 119 TEMOD2PLL_CL37_BAM_15p75GBASE_X2, 120 TEMOD2PLL_CL37_BAM_16GBASE_X4, 121 TEMOD2PLL_CL37_BAM_20GBASE_X4_CX4, 122 TEMOD2PLL_CL37_BAM_20GBASE_X4, 123 TEMOD2PLL_CL37_BAM_20GBASE_X2, 124 TEMOD2PLL_CL37_BAM_20GBASE_X2_CX4, 125 TEMOD2PLL_CL37_BAM_21GBASE_X4, 126 TEMOD2PLL_CL37_BAM_25p455GBASE_X4, 127 TEMOD2PLL_CL37_BAM_31p5GBASE_X4, 128 TEMOD2PLL_CL37_BAM_32p7GBASE_X4, 129 TEMOD2PLL_CL37_BAM_40GBASE_X4, 130 TEMOD2PLL_CL37_BAM_SPEED1_COUNT 131 }temod2pll_cl37_bam_speed1_t; 132 133 typedef enum { 134 TEMOD2PLL_CL37_BAM_2p5GBASE_X = 0, 135 TEMOD2PLL_CL37_BAM_5GBASE_X4, 136 TEMOD2PLL_CL37_BAM_6GBASE_X4, 137 TEMOD2PLL_CL37_BAM_10GBASE_X4, 138 TEMOD2PLL_CL37_BAM_10GBASE_X4_CX4, 139 TEMOD2PLL_CL37_BAM_10GBASE_X2, 140 TEMOD2PLL_CL37_BAM_10GBASE_X2_CX4, 141 TEMOD2PLL_CL37_BAM_BAM_10p5GBASE_X2, 142 TEMOD2PLL_CL37_BAM_12GBASE_X4, 143 TEMOD2PLL_CL37_BAM_12p5GBASE_X4, 144 TEMOD2PLL_CL37_BAM_12p7GBASE_X2, 145 TEMOD2PLL_CL37_BAM_SPEED_COUNT 146 }temod2pll_cl37_bam_speed_t; 147 148 149 typedef enum { 150 TEMOD2PLL_NO_PAUSE = 0, 151 TEMOD2PLL_SYMM_PAUSE, 152 TEMOD2PLL_ASYM_PAUSE, 153 TEMOD2PLL_ASYM_SYMM_PAUSE, 154 TEMOD2PLL_AN_PAUSE_COUNT 155 }temod2pll_an_pause_t; 156 157 typedef enum { 158 TEMOD2PLL_HG2_CODEC_OFF = 0, 159 TEMOD2PLL_HG2_CODEC_ON_8BYTE_IPG, 160 TEMOD2PLL_HG2_CODEC_ON_9BYTE_IPG, 161 TEMOD2PLL_HG2_CODEC_COUNT 162 }temod2pll_hg2_codec_t; 163 164 #define TEMOD2PLL_FEC_NOT_SUPRTD 0 165 #define TEMOD2PLL_FEC_SUPRTD_NOT_REQSTD 1 166 #define TEMOD2PLL_FEC_CL74_SUPRTD_REQSTD 4 167 168 /** 169 \struct temod2pll_an_init_s 170 171 This embodies all parameters required to program autonegotiation features in the 172 PHY for both CL37 and CL73 type autonegotiation and the BAM variants. 173 For details of individual fields, please refer to microarchitectural doc. 174 */ 175 typedef struct temod2pll_an_init_s{ 176 uint16_t an_fail_cnt; 177 uint16_t an_oui_ctrl; 178 uint16_t linkfailtimer_dis; 179 uint16_t linkfailtimerqua_en; 180 uint16_t an_good_check_trap; 181 uint16_t an_good_trap; 182 uint16_t disable_rf_report; 183 uint16_t cl37_bam_ovr1g_pgcnt; 184 uint16_t cl73_remote_fault; 185 uint16_t cl73_nonce_match_over; 186 uint16_t cl73_nonce_match_val; 187 uint16_t cl73_transmit_nonce; 188 uint16_t base_selector; 189 } temod2pll_an_init_t; 190 191 192 /** 193 \struct temod2pll_an_timers_s 194 TBD 195 */ 196 typedef struct temod2pll_an_timers_s{ 197 uint16_t value; 198 } temod2pll_an_timers_t; 199 200 201 202 typedef struct temod2pll_an_adv_ability_s{ 203 temod2pll_cl73_speed_t an_base_speed; 204 temod2pll_cl37_bam_speed_t an_bam_speed; 205 temod2pll_cl37_bam_speed1_t an_bam_speed1; 206 temod2pll_an_pause_t an_pause; 207 uint16_t an_fec; 208 uint16_t an_cl72; 209 uint16_t an_hg2; 210 temod2pll_cl37_sgmii_speed_t cl37_sgmii_speed; 211 }temod2pll_an_adv_ability_t; 212 213 /** 214 \struct temod2pll_an_ability_s 215 216 TBD 217 218 */ 219 typedef struct temod2pll_an_ability_s { 220 temod2pll_an_adv_ability_t cl37_adv; /*includes cl37 and cl37-bam related (fec, cl72) */ 221 temod2pll_an_adv_ability_t cl73_adv; /*includes cl73 and cl73-bam related */ 222 } temod2pll_an_ability_t; 223 224 /** 225 \struct temod2pll_an_oui_s 226 oui : New oui 227 override_bam73_adv : Adv new OUI for BAM73 228 override_bam73_det : Detect new OUI for BAM73 229 override_hpam_adv : Adv new OUI for HPAM 230 override_hpam_det : Detect new OUI for HPAM 231 override_bam37_adv : Adv new OUI for BAM37 232 override_bam37_det : Detect new OUI for BAM37 233 */ 234 typedef struct temod2pll_an_oui_s { 235 uint32_t oui; 236 uint16_t oui_override_bam73_adv; 237 uint16_t oui_override_bam73_det; 238 uint16_t oui_override_hpam_adv; 239 uint16_t oui_override_hpam_det; 240 uint16_t oui_override_bam37_adv; 241 uint16_t oui_override_bam37_det; 242 } temod2pll_an_oui_t; 243 244 typedef struct temod2pll_ts_tx_info_s { 245 uint16_t ts_val_lo; 246 uint16_t ts_val_hi; 247 uint16_t ts_seq_id; 248 uint16_t ts_sub_nanosec; 249 } temod2pll_ts_tx_info_t; 250 251 extern int temod2pll_pll_reset_enable_set (PHYMOD_ST *pa , int enable); 252 extern int temod2pll_speed_id_get (PHYMOD_ST *pc, int *speed_id); 253 extern int temod2pll_update_port_mode( PHYMOD_ST *pa); 254 extern int temod2pll_get_plldiv (PHYMOD_ST *pa, uint32_t *pll_div); 255 extern int temod2pll_tx_rx_polarity_get (PHYMOD_ST *pc, uint32_t* txp, uint32_t* rxp); 256 extern int temod2pll_rx_lane_control_set(PHYMOD_ST* pc, int enable); 257 extern int temod2pll_rx_lane_control_get(PHYMOD_ST* pc, int *enable); 258 extern int temod2pll_tx_rx_polarity_set (PHYMOD_ST *pc, uint32_t txp, uint32_t rxp); 259 extern int temod2pll_pmd_lane_swap_tx_get (PHYMOD_ST *pc, uint32_t *tx_lane_map); 260 extern int temod2pll_pmd_addr_lane_swap (PHYMOD_ST *pc, uint32_t addr_lane_index); 261 extern int temod2pll_disable_get (PHYMOD_ST *pc, uint32_t* enable); 262 extern int temod2pll_pll_sequencer_control(PHYMOD_ST *pa, int enable); 263 extern int temod2pll_pcs_rx_lane_swap_get ( PHYMOD_ST *pc, uint32_t *rx_swap); 264 extern int temod2pll_pcs_tx_lane_swap_get ( PHYMOD_ST *pc, uint32_t *tx_swap); 265 extern int temod2pll_master_port_num_set(PHYMOD_ST *pa, int port_num); 266 extern int temod2pll_set_spd_intf(PHYMOD_ST *pc, temod2pll_spd_intfc_type spd_intf, int no_trig); 267 extern int temod2pll_pll_lock_wait(PHYMOD_ST* pc, int timeOutValue); 268 extern int temod2pll_credit_control(PHYMOD_ST* pc, int enable); 269 #ifdef _DV_TB_ 270 extern int temod2pll_tx_lane_control(PHYMOD_ST* pc, int enable, tx_lane_disable_type_t tx_dis_type); 271 #endif 272 #ifdef _SDK_TEMOD2PLL_ 273 extern int temod2pll_tx_lane_control_set(PHYMOD_ST* pc, tx_lane_disable_type_t tx_dis_type); 274 extern int temod2pll_tx_lane_control_get(PHYMOD_ST* pc, int *reset, int *enable); 275 #endif 276 extern int temod2pll_power_control(PHYMOD_ST* pc); 277 extern int temod2pll_override_set(PHYMOD_ST* pc, override_type_t or_type, uint16_t or_val); 278 extern int temod2pll_override_get(PHYMOD_ST* pc, override_type_t or_type, uint16_t *or_en, uint16_t *or_val); 279 extern int temod2pll_credit_set(PHYMOD_ST* pc, credit_type_t credit_type, int userCredit); 280 extern int temod2pll_rx_lane_control_set(PHYMOD_ST* pc, int enable); 281 extern int temod2pll_rx_lane_control_get(PHYMOD_ST* pc, int *enable); 282 #ifdef _DV_TB_ 283 extern int temod2pll_mld_am_timers_set(PHYMOD_ST* pc, int rx_am_timer_init,int tx_am_timer_init_val); 284 #endif 285 extern int temod2pll_init_pmd(PHYMOD_ST* pc, int pmd_touched, int uc_active); 286 extern int temod2pll_pmd_osmode_set(PHYMOD_ST* pc, temod2pll_spd_intfc_type spd_intf, int os_mode); 287 extern int temod2pll_pmd_osmode_get(PHYMOD_ST* pc, int *os_mode); 288 extern int temod2pll_pll_lock_get(PHYMOD_ST* pc, int* lockStatus); 289 extern int temod2pll_pmd_lock_get(PHYMOD_ST* pc, uint32_t* lockStatus); 290 extern int temod2pll_wait_pmd_lock(PHYMOD_ST* pc, int timeOutValue, int* lockStatus); 291 extern int temod2pll_pcs_bypass_ctl (PHYMOD_ST* pc, int cntl); 292 extern int temod2pll_pmd_reset_bypass (PHYMOD_ST* pc, int cntl); 293 extern int temod2pll_set_pll_mode(PHYMOD_ST* pc, int pmd_tched, temod2pll_spd_intfc_type sp, int pll_mode, int dual_pll); 294 extern int temod2pll_tick_override_set(PHYMOD_ST* pc, int tick_override, int numerator, int denominator); 295 extern int temod2pll_tx_loopback_control(PHYMOD_ST* pc, int enable, int starting_lane, int port_type); 296 extern int temod2pll_tx_pmd_loopback_control(PHYMOD_ST* pc, int cntl); 297 extern int temod2pll_rx_loopback_control(PHYMOD_ST* pc, int enable, int starting_lane, int port_type); 298 extern int temod2pll_encode_set(PHYMOD_ST* pc, temod2pll_spd_intfc_type spd_intf, uint16_t enable); 299 extern int temod2pll_decode_set(PHYMOD_ST* pc, temod2pll_spd_intfc_type spd_intf, uint16_t enable); 300 extern int temod2pll_hg_enable_get(PHYMOD_ST* pc, int *enable); 301 extern int temod2pll_spd_intf_get(PHYMOD_ST* pc, int *spd_intf); 302 extern int temod2pll_revid_read(PHYMOD_ST* pc, uint32_t *revid); 303 extern int temod2pll_init_pcs(PHYMOD_ST* pc); 304 extern int temod2pll_pmd_reset_seq_dp(PHYMOD_ST* pc, int pmd_touched); 305 extern int temod2pll_pmd_reset_seq(PHYMOD_ST* pc, int pmd_touched); 306 extern int temod2pll_pram_abl_enable_set(PHYMOD_ST* pc, int enable); 307 extern int temod2pll_wait_sc_done(PHYMOD_ST* pc, uint16_t *data); 308 extern int temod2pll_get_pcs_link_status(PHYMOD_ST* pc, uint32_t *link); 309 extern int temod2pll_get_pcs_latched_link_status(PHYMOD_ST* pc, uint32_t *link); 310 extern int temod2pll_disable_set(PHYMOD_ST* pc); 311 extern int temod2pll_init_pcs_ilkn(PHYMOD_ST* pc); 312 extern int temod2pll_pcs_ilkn_chk(PHYMOD_ST* pc, int *ilkn_set); 313 extern int temod2pll_pmd_x4_reset(PHYMOD_ST* pc); 314 extern int temod2pll_pmd_x4_reset_get(PHYMOD_ST* pc, int *is_in_reset); 315 extern int temod2pll_init_pmd_sw(PHYMOD_ST* pc, int pmd_touched, int uc_active, 316 temod2pll_spd_intfc_type spd_intf, int t_pma_os_mode); 317 extern int temod2pll_fecmode_set(PHYMOD_ST* pc, int fec_enable); 318 extern int temod2pll_fecmode_get(PHYMOD_ST* pc, uint32_t *fec_enable); 319 extern int temod2pll_credit_override_set(PHYMOD_ST* pc, credit_type_t credit_type, uint16_t userCredit); 320 extern int temod2pll_credit_override_get(PHYMOD_ST* pc, credit_type_t credit_type, uint16_t *userCredit_en, uint16_t *userCredit); 321 extern int temod2pll_cjpat_crpat_mode_set(PHYMOD_ST* pc, temod2pll_spd_intfc_type spd, int port, int pat, int pnum, int size, int ipgsz); 322 extern int temod2pll_cjpat_crpat_check(PHYMOD_ST* pc); 323 extern int temod2pll_cjpat_crpat_control(PHYMOD_ST* pc, int enable); 324 extern int temod2pll_pcs_rx_lane_swap(PHYMOD_ST *pc, int rx_lane_map); 325 extern int temod2pll_pcs_tx_lane_swap(PHYMOD_ST *pc, int tx_lane_map); 326 extern int temod2pll_trigger_speed_change(PHYMOD_ST* pc); 327 extern int temod2pll_init_pmd_qsgmii(PHYMOD_ST* pc, int pmd_touched, int uc_active); 328 extern int temod2pll_rx_lane_control_get(PHYMOD_ST* pc, int *value); 329 extern int temod2pll_pmd_override_control(PHYMOD_ST* pc, int cntl, int value); 330 extern int temod2pll_plldiv_lkup_get(PHYMOD_ST* pc, temod2pll_spd_intfc_type spd_intf, phymod_ref_clk_t ref_clk, uint32_t *plldiv, uint16_t *speed_vec); 331 extern int temod2pll_osmode_lkup_get(PHYMOD_ST* pc, temod2pll_spd_intfc_type spd_intf, uint32_t *osmode); 332 extern int temod2pll_osdfe_on_lkup_get(PHYMOD_ST* pc, temod2pll_spd_intfc_type spd_intf, uint32_t *osdfe_on); 333 extern int temod2pll_scrambling_dis_lkup_get(PHYMOD_ST* pc, temod2pll_spd_intfc_type spd_intf, uint32_t *scrambling_dis); 334 335 extern int temod2pll_port_enable_set(PHYMOD_ST *pc, int enable); 336 extern int temod2pll_tx_squelch_set(PHYMOD_ST *pc, int enable); 337 extern int temod2pll_rx_squelch_set(PHYMOD_ST *pc, int enable); 338 extern int temod2pll_port_enable_get(PHYMOD_ST *pc, int *tx_enable, int *rx_enable); 339 extern int temod2pll_tx_squelch_get(PHYMOD_ST *pc, int *enable); 340 extern int temod2pll_rx_squelch_get(PHYMOD_ST *pc, int *enable); 341 int temod2pll_eee_control_set(PHYMOD_ST* pc, uint32_t enable); 342 int temod2pll_eee_control_get(PHYMOD_ST* pc, uint32_t *enable); 343 extern int temod2pll_pll_config_get(const phymod_access_t *pa, temod2pll_pll_mode_type *pll_mode); 344 extern int temod2pll_pll_config_set(const phymod_access_t *pa, temod2pll_pll_mode_type pll_mode, phymod_ref_clk_t ref_clk); 345 #ifdef _SDK_TEMOD2PLL_ 346 extern int temod2pll_autoneg_set_init(PHYMOD_ST* pc, temod2pll_an_init_t *an_init_st); 347 extern int temod2pll_autoneg_control(PHYMOD_ST* pc, temod2pll_an_control_t *an_control); 348 extern int temod2pll_autoneg_restart(PHYMOD_ST* pc, temod2pll_an_control_t *an_control); 349 extern int temod2pll_autoneg_timer_init(PHYMOD_ST* pc); 350 extern int temod2pll_cl48_lfrfli_init(PHYMOD_ST* pc); 351 extern int temod2pll_autoneg_set(PHYMOD_ST* pc, temod2pll_an_ability_t *an_ability_st); 352 extern int temod2pll_set_an_port_mode(PHYMOD_ST* pc, int enable, int nl_encoded, int starting_lane, int single_port); 353 extern int temod2pll_refclk_set(PHYMOD_ST* pc, phymod_ref_clk_t ref_clock); 354 extern int temod2pll_pmd_lane_swap_tx(PHYMOD_ST *pc, uint32_t tx_lane_map); 355 extern int temod2pll_pmd_addr_lane_swap (PHYMOD_ST *pc, uint32_t addr_lane_index); 356 extern int temod2pll_tsc12_control(PHYMOD_ST* pc, int cl82_multi_pipe_mode, int cl82_mld_phys_map); 357 int temod2pll_tx_loopback_get(PHYMOD_ST* pc, uint32_t *enable); 358 extern int temod2pll_autoneg_local_ability_get(PHYMOD_ST* pc, temod2pll_an_ability_t *an_ability_st); 359 extern int temod2pll_autoneg_remote_ability_get(PHYMOD_ST* pc, temod2pll_an_ability_t *an_ability_st); 360 extern int temod2pll_autoneg_control_get(PHYMOD_ST* pc, temod2pll_an_control_t *an_control, int *an_complete); 361 extern int temod2pll_diag(PHYMOD_ST *pc, temod2pll_diag_type diag_type); 362 extern int temod2pll_diag_disp(PHYMOD_ST *pc, const char* mystr); 363 extern int temod2pll_clause72_control(PHYMOD_ST* pc, uint32_t cl_72_en); /* CLAUSE_72_CONTROL */ 364 365 extern int temod2pll_st_control_field_set (PHYMOD_ST* pc,uint16_t st_entry_no,override_type_t st_control_field,uint16_t st_field_value); 366 extern int temod2pll_st_control_field_get (PHYMOD_ST* pc,uint16_t st_entry_no, override_type_t st_control_field, uint16_t *st_field_value); 367 extern int temod2pll_st_credit_field_set (PHYMOD_ST* pc,uint16_t st_entry_no,credit_type_t credit_type,uint16_t st_field_value); 368 extern int temod2pll_st_credit_field_get (PHYMOD_ST* pc,uint16_t st_entry_no,credit_type_t credit_type,uint16_t* st_field_value); 369 extern int temod2pll_mld_am_timers_set(PHYMOD_ST* pc); 370 extern int temod2pll_an_ncl72_inhibit_timer_get(PHYMOD_ST* pc, uint16_t *value); 371 extern int temod2pll_an_ncl72_inhibit_timer_set(PHYMOD_ST* pc, uint16_t value); 372 extern int temod2pll_cl74_chng_default (PHYMOD_ST* pc); 373 374 extern int temod2pll_an_oui_set(PHYMOD_ST* pc, temod2pll_an_oui_t oui); 375 extern int temod2pll_an_oui_get(PHYMOD_ST* pc, temod2pll_an_oui_t *oui); 376 extern int temod2pll_cl37_high_vco_set(PHYMOD_ST* pc, int value); 377 extern int temod2pll_pcs_ilkn_mode_set(PHYMOD_ST* pc); /* INIT_PCS_ILKN */ 378 extern int temod2pll_pll_select(PHYMOD_ST* pc, int pll_select); 379 extern uint8_t temod2pll_pll_index_get(PHYMOD_ST* pc); 380 extern int temod2pll_1588_ts_enable_set(PHYMOD_ST* pc, uint32_t ts_enable); 381 extern int temod2pll_1588_ts_enable_get(PHYMOD_ST* pc, uint32_t *ts_enable); 382 extern int temod2pll_1588_ts_offset_set(PHYMOD_ST* pc, uint32_t ts_offset); 383 extern int temod2pll_1588_pcs_control_set(PHYMOD_ST* pc); 384 extern int temod2pll_1588_fclk_set(PHYMOD_ST* pc); 385 extern int temod2pll_1588_ui_values_set(PHYMOD_ST* pc); 386 extern int temod2pll_1588_txrx_fixed_latency_set(PHYMOD_ST* pc); 387 extern int temod2pll_1588_rx_deskew_set(PHYMOD_ST* pc, phymod_timesync_compensation_mode_t timesync_am_norm_mode); 388 extern int temod2pll_bond_in_pwrdn_override(PHYMOD_ST* pc, uint32_t enable); 389 extern int temod2pll_hg2_codec_set(PHYMOD_ST* pc, temod2pll_hg2_codec_t hg2_codec); 390 extern int temod2pll_hg2_codec_get(PHYMOD_ST* pc, temod2pll_hg2_codec_t* hg2_codec); 391 extern int temod2pll_1588_tx_info_get(PHYMOD_ST* pc, temod2pll_ts_tx_info_t* ts_tx_info); 392 #endif 393 394 #ifdef _DV_TB_ 395 extern int temod2pll_1588_set_rx_deskew(PHYMOD_ST* pc); 396 #endif 397 398 extern int temod2pll_pll_select(PHYMOD_ST* pc, int pll_select); 399 extern int temod2pll_fec_correctable_counter_get(PHYMOD_ST* pc, uint32_t* count); 400 extern int temod2pll_fec_uncorrectable_counter_get(PHYMOD_ST* pc, uint32_t* count); 401 int temod2pll_get_mapped_speed(temod2pll_spd_intfc_type spd_intf, int *speed); 402 extern int temod2pll_get_ui_values(int speed, uint16_t *ui_msb, uint16_t *ui_lsb); 403 extern int temod2pll_get_am_bits(int speed, long *am_bits); 404 extern int temod2pll_get_txrx_fixed_lat(int speed, uint16_t *tx_fixed_int, uint16_t *tx_fixed_frac, uint16_t *rx_fixed_int, uint16_t *rx_fixed_frac); 405 #ifdef GEN2_16NM_CODE 406 int temod2pll_get_pll_ndiv(int pll_mode, int *pll_ndiv); 407 #endif /*GEN2_16NM_CODE*/ 408 int temod2pll_get_actual_speed(int speed_id, int *speed); 409 410 extern int temod2pll_synce_stg0_mode_set(PHYMOD_ST *pc, int mode); 411 extern int temod2pll_synce_stg0_mode_get(PHYMOD_ST *pc, int *mode); 412 extern int temod2pll_synce_stg1_mode_set(PHYMOD_ST *pc, int mode); 413 extern int temod2pll_synce_stg1_mode_get(PHYMOD_ST *pc, int *mode); 414 extern int temod2pll_synce_clk_ctrl_set(PHYMOD_ST *pc, uint32_t val); 415 extern int temod2pll_synce_clk_ctrl_get(PHYMOD_ST *pc, uint32_t *val); 416 417 #endif /* _temod2pll_H_ */ 418