tedpll_PCSRegEnums.h (275384B)
1 /*************************************************************************** 2 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 3 * 4 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 5 * 6 * 7 * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE 8 * AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR 9 * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT. 10 * 11 * $brcm_Workfile: $ 12 * $brcm_Revision: $ 13 * $brcm_Date: $ 14 * 15 * Module Description: 16 * DO NOT EDIT THIS FILE DIRECTLY 17 * 18 * This module was generated magically with RDB from a source description 19 * file. You must edit the source file for changes to be made to this file. 20 * 21 * 22 * Date: Generated on Mon Dec 14 16:10:09 2015 23 * MD5 Checksum c90f927043e2811c767c86b727285e9c 24 * 25 * Compiled with: RDB Utility 5.0 26 * RDB Parser 3.0 27 * rdb2macro.pm 4.0 28 * Perl Interpreter 5.008008 29 * Operating System linux 30 * 31 * Spec Versions: an_x1_control 1 32 * an_x1_timers 1 33 * an_x4_abilities 1 34 * an_x4_hw_lp_pages 1 35 * an_x4_sw_management 1 36 * cl72_user 1 37 * cl82 1 38 * cl82_am 1 39 * cl82_am_tsc_12 1 40 * cl82_shared 1 41 * digital 1 42 * generic 1 43 * ieee0_cl22 1 44 * ilkn_control0 1 45 * ilkn_status0 1 46 * main0 1 47 * mem_dbg 1 48 * mem_ecc 1 49 * misc 1 50 * pmd_x1 1 51 * pmd_x4 1 52 * rx_x1_control0 1 53 * rx_x1_control1 1 54 * rx_x2_control0 1 55 * rx_x2_status0 1 56 * rx_x4_control0 1 57 * rx_x4_control0_tsc_121 58 * rx_x4_status0 1 59 * rx_x4_status0_tsc_12 1 60 * rx_x4_status1 1 61 * sc_x1_control 1 62 * sc_x1_speed_override01 63 * sc_x1_speed_override11 64 * sc_x1_speed_override21 65 * sc_x1_speed_override31 66 * sc_x4_control 1 67 * sc_x4_field_override_enable1 68 * sc_x4_final_config_status1 69 * test1 1 70 * testshared0 1 71 * testshared1 1 72 * tx_x1_control0 1 73 * tx_x1_status0 1 74 * tx_x2_control0 1 75 * tx_x2_status0 1 76 * tx_x4_control0 1 77 * tx_x4_credit_gen0 1 78 * tx_x4_status0 1 79 * 80 * RDB Files: /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/WC4_TSC_ALL.rdb 81 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/ieee0_cl22_regs.rdb 82 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/pmd_x1_regs.rdb 83 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/testshared0_regs.rdb 84 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/testshared1_regs.rdb 85 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/mem_ecc_regs.rdb 86 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/mem_dbg_regs.rdb 87 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/misc_regs.rdb 88 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/enum_inc.rdb 89 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/an_x1_timers_regs.rdb 90 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/cl82_shared_regs.rdb 91 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/cl82_am_regs.rdb 92 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/cl82_am_tsc_12_regs.rdb 93 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/cl82_regs.rdb 94 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/main0_regs.rdb 95 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/enum_inc.rdb 96 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/rx_x1_control0_regs.rdb 97 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/rx_x1_control1_regs.rdb 98 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/tx_x1_control0_regs.rdb 99 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/tx_x1_status0_regs.rdb 100 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/an_x1_control_regs.rdb 101 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/tx_x2_control0_regs.rdb 102 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/tx_x2_status0_regs.rdb 103 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/rx_x2_control0_regs.rdb 104 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/rx_x2_status0_regs.rdb 105 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/gen_per_lane_regs.rdb 106 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/enum_inc.rdb 107 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/pmd_x4_regs.rdb 108 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/test1_regs.rdb 109 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/tx_x4_credit_gen0_regs.rdb 110 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/enum_inc.rdb 111 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/tx_x4_control0_regs.rdb 112 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/tx_x4_status0_regs.rdb 113 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/rx_x4_control0_regs.rdb 114 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/rx_x4_status0_regs.rdb 115 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/rx_x4_status1_regs.rdb 116 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/rx_x4_control0_tsc_12_regs.rdb 117 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/rx_x4_status0_tsc_12_regs.rdb 118 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/an_x4_abilities_regs.rdb 119 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/an_x4_hw_lp_pages_regs.rdb 120 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/an_x4_sw_management_regs.rdb 121 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/enum_inc.rdb 122 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/digital_regs.rdb 123 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/enum_inc.rdb 124 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/cl72_user_regs.rdb 125 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/sc_x1_control_regs.rdb 126 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/sc_x4_control_regs.rdb 127 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/enum_inc.rdb 128 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/sc_x1_speed_override0_regs.rdb 129 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/sc_x1_speed_override_common.rdb 130 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/enum_inc.rdb 131 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/sc_x1_speed_override1_regs.rdb 132 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/sc_x1_speed_override_common.rdb 133 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/enum_inc.rdb 134 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/sc_x1_speed_override2_regs.rdb 135 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/sc_x1_speed_override_common.rdb 136 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/enum_inc.rdb 137 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/sc_x1_speed_override3_regs.rdb 138 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/sc_x1_speed_override_common.rdb 139 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/enum_inc.rdb 140 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/sc_x4_final_config_status_regs.rdb 141 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/sc_x1_speed_override_common.rdb 142 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/enum_inc.rdb 143 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/sc_x4_field_override_enable_regs.rdb 144 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/ilkn_control0_regs.rdb 145 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/ilkn_status0_regs.rdb 146 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/WC4_ieeeBlockCL22.rdb 147 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/WC4_userBlocks1.rdb 148 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/WC4_userBlocks2.rdb 149 * /projects/TSC_ext8/amarachi/tsceg3/tsce_g3/rtl/rdb/WC4_userBlocks4.rdb 150 * 151 * Revision History: 152 * 153 * $brcm_Log: $ 154 */ 155 156 #ifndef TEPCSREGENUMS_TMP__ 157 #define TEPCSREGENUMS_TMP__ 158 159 /**************************************************************************** 160 * Core Enums. 161 */ 162 /**************************************************************************** 163 * Enums: an_x4_sw_management_cl36TxEEEStates_l 164 */ 165 #define an_x4_sw_management_cl36TxEEEStates_l_TX_REFRESH 8 166 #define an_x4_sw_management_cl36TxEEEStates_l_TX_QUIET 4 167 #define an_x4_sw_management_cl36TxEEEStates_l_TX_SLEEP 2 168 #define an_x4_sw_management_cl36TxEEEStates_l_TX_ACTIVE 1 169 170 /**************************************************************************** 171 * Enums: an_x4_sw_management_cl36TxEEEStates_c 172 */ 173 #define an_x4_sw_management_cl36TxEEEStates_c_TX_REFRESH 3 174 #define an_x4_sw_management_cl36TxEEEStates_c_TX_QUIET 2 175 #define an_x4_sw_management_cl36TxEEEStates_c_TX_SLEEP 1 176 #define an_x4_sw_management_cl36TxEEEStates_c_TX_ACTIVE 0 177 178 /**************************************************************************** 179 * Enums: an_x4_sw_management_cl49TxEEEStates_l 180 */ 181 #define an_x4_sw_management_cl49TxEEEStates_l_SCR_RESET_2 64 182 #define an_x4_sw_management_cl49TxEEEStates_l_SCR_RESET_1 32 183 #define an_x4_sw_management_cl49TxEEEStates_l_TX_WAKE 16 184 #define an_x4_sw_management_cl49TxEEEStates_l_TX_REFRESH 8 185 #define an_x4_sw_management_cl49TxEEEStates_l_TX_QUIET 4 186 #define an_x4_sw_management_cl49TxEEEStates_l_TX_SLEEP 2 187 #define an_x4_sw_management_cl49TxEEEStates_l_TX_ACTIVE 1 188 189 /**************************************************************************** 190 * Enums: an_x4_sw_management_cl49TxEEEStates_c 191 */ 192 #define an_x4_sw_management_cl49TxEEEStates_c_SCR_RESET_2 6 193 #define an_x4_sw_management_cl49TxEEEStates_c_SCR_RESET_1 5 194 #define an_x4_sw_management_cl49TxEEEStates_c_TX_WAKE 4 195 #define an_x4_sw_management_cl49TxEEEStates_c_TX_REFRESH 3 196 #define an_x4_sw_management_cl49TxEEEStates_c_TX_QUIET 2 197 #define an_x4_sw_management_cl49TxEEEStates_c_TX_SLEEP 1 198 #define an_x4_sw_management_cl49TxEEEStates_c_TX_ACTIVE 0 199 200 /**************************************************************************** 201 * Enums: an_x4_sw_management_cl36RxEEEStates_l 202 */ 203 #define an_x4_sw_management_cl36RxEEEStates_l_RX_LINK_FAIL 32 204 #define an_x4_sw_management_cl36RxEEEStates_l_RX_WTF 16 205 #define an_x4_sw_management_cl36RxEEEStates_l_RX_WAKE 8 206 #define an_x4_sw_management_cl36RxEEEStates_l_RX_QUIET 4 207 #define an_x4_sw_management_cl36RxEEEStates_l_RX_SLEEP 2 208 #define an_x4_sw_management_cl36RxEEEStates_l_RX_ACTIVE 1 209 210 /**************************************************************************** 211 * Enums: an_x4_sw_management_cl36RxEEEStates_c 212 */ 213 #define an_x4_sw_management_cl36RxEEEStates_c_RX_LINK_FAIL 5 214 #define an_x4_sw_management_cl36RxEEEStates_c_RX_WTF 4 215 #define an_x4_sw_management_cl36RxEEEStates_c_RX_WAKE 3 216 #define an_x4_sw_management_cl36RxEEEStates_c_RX_QUIET 2 217 #define an_x4_sw_management_cl36RxEEEStates_c_RX_SLEEP 1 218 #define an_x4_sw_management_cl36RxEEEStates_c_RX_ACTIVE 0 219 220 /**************************************************************************** 221 * Enums: an_x4_sw_management_cl49RxEEEStates_l 222 */ 223 #define an_x4_sw_management_cl49RxEEEStates_l_RX_LINK_FAIL 32 224 #define an_x4_sw_management_cl49RxEEEStates_l_RX_WTF 16 225 #define an_x4_sw_management_cl49RxEEEStates_l_RX_WAKE 8 226 #define an_x4_sw_management_cl49RxEEEStates_l_RX_QUIET 4 227 #define an_x4_sw_management_cl49RxEEEStates_l_RX_SLEEP 2 228 #define an_x4_sw_management_cl49RxEEEStates_l_RX_ACTIVE 1 229 230 /**************************************************************************** 231 * Enums: an_x4_sw_management_cl49RxEEEStates_c 232 */ 233 #define an_x4_sw_management_cl49RxEEEStates_c_RX_LINK_FAIL 5 234 #define an_x4_sw_management_cl49RxEEEStates_c_RX_WTF 4 235 #define an_x4_sw_management_cl49RxEEEStates_c_RX_WAKE 3 236 #define an_x4_sw_management_cl49RxEEEStates_c_RX_QUIET 2 237 #define an_x4_sw_management_cl49RxEEEStates_c_RX_SLEEP 1 238 #define an_x4_sw_management_cl49RxEEEStates_c_RX_ACTIVE 0 239 240 /**************************************************************************** 241 * Enums: an_x4_sw_management_cl48TxEEEStates_l 242 */ 243 #define an_x4_sw_management_cl48TxEEEStates_l_TX_REFRESH 8 244 #define an_x4_sw_management_cl48TxEEEStates_l_TX_QUIET 4 245 #define an_x4_sw_management_cl48TxEEEStates_l_TX_SLEEP 2 246 #define an_x4_sw_management_cl48TxEEEStates_l_TX_ACTIVE 1 247 248 /**************************************************************************** 249 * Enums: an_x4_sw_management_cl48TxEEEStates_c 250 */ 251 #define an_x4_sw_management_cl48TxEEEStates_c_TX_REFRESH 3 252 #define an_x4_sw_management_cl48TxEEEStates_c_TX_QUIET 2 253 #define an_x4_sw_management_cl48TxEEEStates_c_TX_SLEEP 1 254 #define an_x4_sw_management_cl48TxEEEStates_c_TX_ACTIVE 0 255 256 /**************************************************************************** 257 * Enums: an_x4_sw_management_cl48RxEEEStates_l 258 */ 259 #define an_x4_sw_management_cl48RxEEEStates_l_RX_LINK_FAIL 32 260 #define an_x4_sw_management_cl48RxEEEStates_l_RX_WAKE 16 261 #define an_x4_sw_management_cl48RxEEEStates_l_RX_QUIET 8 262 #define an_x4_sw_management_cl48RxEEEStates_l_RX_DEACT 4 263 #define an_x4_sw_management_cl48RxEEEStates_l_RX_SLEEP 2 264 #define an_x4_sw_management_cl48RxEEEStates_l_RX_ACTIVE 1 265 266 /**************************************************************************** 267 * Enums: an_x4_sw_management_cl48RxEEEStates_c 268 */ 269 #define an_x4_sw_management_cl48RxEEEStates_c_RX_LINK_FAIL 5 270 #define an_x4_sw_management_cl48RxEEEStates_c_RX_WAKE 4 271 #define an_x4_sw_management_cl48RxEEEStates_c_RX_QUIET 3 272 #define an_x4_sw_management_cl48RxEEEStates_c_RX_DEACT 2 273 #define an_x4_sw_management_cl48RxEEEStates_c_RX_SLEEP 1 274 #define an_x4_sw_management_cl48RxEEEStates_c_RX_ACTIVE 0 275 276 /**************************************************************************** 277 * Enums: an_x4_sw_management_IQP_Options 278 */ 279 #define an_x4_sw_management_IQP_Options_i50uA 0 280 #define an_x4_sw_management_IQP_Options_i100uA 1 281 #define an_x4_sw_management_IQP_Options_i150uA 2 282 #define an_x4_sw_management_IQP_Options_i200uA 3 283 #define an_x4_sw_management_IQP_Options_i250uA 4 284 #define an_x4_sw_management_IQP_Options_i300uA 5 285 #define an_x4_sw_management_IQP_Options_i350uA 6 286 #define an_x4_sw_management_IQP_Options_i400uA 7 287 #define an_x4_sw_management_IQP_Options_i450uA 8 288 #define an_x4_sw_management_IQP_Options_i500uA 9 289 #define an_x4_sw_management_IQP_Options_i550uA 10 290 #define an_x4_sw_management_IQP_Options_i600uA 11 291 #define an_x4_sw_management_IQP_Options_i650uA 12 292 #define an_x4_sw_management_IQP_Options_i700uA 13 293 #define an_x4_sw_management_IQP_Options_i750uA 14 294 #define an_x4_sw_management_IQP_Options_i800uA 15 295 296 /**************************************************************************** 297 * Enums: an_x4_sw_management_IDriver_Options 298 */ 299 #define an_x4_sw_management_IDriver_Options_v680mV 0 300 #define an_x4_sw_management_IDriver_Options_v730mV 1 301 #define an_x4_sw_management_IDriver_Options_v780mV 2 302 #define an_x4_sw_management_IDriver_Options_v830mV 3 303 #define an_x4_sw_management_IDriver_Options_v880mV 4 304 #define an_x4_sw_management_IDriver_Options_v930mV 5 305 #define an_x4_sw_management_IDriver_Options_v980mV 6 306 #define an_x4_sw_management_IDriver_Options_v1010mV 7 307 #define an_x4_sw_management_IDriver_Options_v1040mV 8 308 #define an_x4_sw_management_IDriver_Options_v1060mV 9 309 #define an_x4_sw_management_IDriver_Options_v1070mV 10 310 #define an_x4_sw_management_IDriver_Options_v1080mV 11 311 #define an_x4_sw_management_IDriver_Options_v1085mV 12 312 #define an_x4_sw_management_IDriver_Options_v1090mV 13 313 #define an_x4_sw_management_IDriver_Options_v1095mV 14 314 #define an_x4_sw_management_IDriver_Options_v1100mV 15 315 316 /**************************************************************************** 317 * Enums: an_x4_sw_management_operationModes 318 */ 319 #define an_x4_sw_management_operationModes_XGXS 0 320 #define an_x4_sw_management_operationModes_XGXG_nCC 1 321 #define an_x4_sw_management_operationModes_Indlane_OS8 4 322 #define an_x4_sw_management_operationModes_IndLane_OS5 5 323 #define an_x4_sw_management_operationModes_PCI 7 324 #define an_x4_sw_management_operationModes_XGXS_nLQ 8 325 #define an_x4_sw_management_operationModes_XGXS_nLQnCC 9 326 #define an_x4_sw_management_operationModes_PBypass 10 327 #define an_x4_sw_management_operationModes_PBypass_nDSK 11 328 #define an_x4_sw_management_operationModes_ComboCoreMode 12 329 #define an_x4_sw_management_operationModes_Clocks_off 15 330 331 /**************************************************************************** 332 * Enums: an_x4_sw_management_synce_enum 333 */ 334 #define an_x4_sw_management_synce_enum_SYNCE_NO_DIV 0 335 #define an_x4_sw_management_synce_enum_SYNCE_DIV_7 1 336 #define an_x4_sw_management_synce_enum_SYNCE_DIV_11 2 337 #define an_x4_sw_management_synce_enum_SYNCE_DIV_10 3 338 339 /**************************************************************************** 340 * Enums: an_x4_sw_management_synce_enum_stage0 341 */ 342 #define an_x4_sw_management_synce_enum_stage0_SYNCE_NO_DIV 0 343 #define an_x4_sw_management_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 344 #define an_x4_sw_management_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 345 346 /**************************************************************************** 347 * Enums: an_x4_sw_management_operationSpeeds 348 */ 349 #define an_x4_sw_management_operationSpeeds_SPEED_10G_X4_10p3125 59 350 #define an_x4_sw_management_operationSpeeds_SPEED_10G_CX4_10p3125 58 351 #define an_x4_sw_management_operationSpeeds_SPEED_10G_KX4_10p3125 57 352 #define an_x4_sw_management_operationSpeeds_SPEED_2p5G_X1_10p3125 56 353 #define an_x4_sw_management_operationSpeeds_SPEED_1000M_10p3125 55 354 #define an_x4_sw_management_operationSpeeds_SPEED_100M_10p3125 54 355 #define an_x4_sw_management_operationSpeeds_SPEED_10M_10p3125 53 356 #define an_x4_sw_management_operationSpeeds_SPEED_10p5G_X4 50 357 #define an_x4_sw_management_operationSpeeds_SPEED_5G_KR1 49 358 #define an_x4_sw_management_operationSpeeds_SPEED_42p42G_X4 44 359 #define an_x4_sw_management_operationSpeeds_SPEED_21p21G_X2 43 360 #define an_x4_sw_management_operationSpeeds_SPEED_48p48G_X4 42 361 #define an_x4_sw_management_operationSpeeds_SPEED_24p24G_X2 41 362 #define an_x4_sw_management_operationSpeeds_SPEED_12p12G_X1 40 363 #define an_x4_sw_management_operationSpeeds_SPEED_127G_X12 39 364 #define an_x4_sw_management_operationSpeeds_SPEED_120G_X12 38 365 #define an_x4_sw_management_operationSpeeds_SPEED_107G_X10 37 366 #define an_x4_sw_management_operationSpeeds_SPEED_100G_CR10 36 367 #define an_x4_sw_management_operationSpeeds_SPEED_42G_X4 35 368 #define an_x4_sw_management_operationSpeeds_SPEED_40G_CR4 34 369 #define an_x4_sw_management_operationSpeeds_SPEED_40G_KR4 33 370 #define an_x4_sw_management_operationSpeeds_SPEED_21G_X2 32 371 #define an_x4_sw_management_operationSpeeds_SPEED_20G_CR2 31 372 #define an_x4_sw_management_operationSpeeds_SPEED_20G_KR2 30 373 #define an_x4_sw_management_operationSpeeds_SPEED_10p6_X1 29 374 #define an_x4_sw_management_operationSpeeds_SPEED_10G_KR1 28 375 #define an_x4_sw_management_operationSpeeds_SPEED_40G_X4 27 376 #define an_x4_sw_management_operationSpeeds_SPEED_20G_X2 26 377 #define an_x4_sw_management_operationSpeeds_SPEED_20G_CX2 25 378 #define an_x4_sw_management_operationSpeeds_SPEED_31p5G_KR4 24 379 #define an_x4_sw_management_operationSpeeds_SPEED_31p5G_X4 23 380 #define an_x4_sw_management_operationSpeeds_SPEED_15p75G_X2 22 381 #define an_x4_sw_management_operationSpeeds_SPEED_25p45G_X4 21 382 #define an_x4_sw_management_operationSpeeds_SPEED_12p7G_X2 20 383 #define an_x4_sw_management_operationSpeeds_SPEED_21G_X4 19 384 #define an_x4_sw_management_operationSpeeds_SPEED_10p5G_X2 18 385 #define an_x4_sw_management_operationSpeeds_SPEED_20G_X4 17 386 #define an_x4_sw_management_operationSpeeds_SPEED_10G_X2 16 387 #define an_x4_sw_management_operationSpeeds_SPEED_10G_CX2 15 388 #define an_x4_sw_management_operationSpeeds_SPEED_20G_CX4 14 389 #define an_x4_sw_management_operationSpeeds_SPEED_16G_X4 13 390 #define an_x4_sw_management_operationSpeeds_SPEED_15G_X4 12 391 #define an_x4_sw_management_operationSpeeds_SPEED_13G_X4 11 392 #define an_x4_sw_management_operationSpeeds_SPEED_10G_X4 10 393 #define an_x4_sw_management_operationSpeeds_SPEED_10G_KX4 9 394 #define an_x4_sw_management_operationSpeeds_SPEED_10G_CX4 8 395 #define an_x4_sw_management_operationSpeeds_SPEED_5G_X1 7 396 #define an_x4_sw_management_operationSpeeds_SPEED_2p5G_X1 6 397 #define an_x4_sw_management_operationSpeeds_SPEED_1G_KX1 5 398 #define an_x4_sw_management_operationSpeeds_SPEED_1G_CX1 4 399 #define an_x4_sw_management_operationSpeeds_SPEED_1000M 3 400 #define an_x4_sw_management_operationSpeeds_SPEED_100M 2 401 #define an_x4_sw_management_operationSpeeds_SPEED_10M 1 402 403 /**************************************************************************** 404 * Enums: an_x4_sw_management_actualSpeeds 405 */ 406 #define an_x4_sw_management_actualSpeeds_dr_10M 0 407 #define an_x4_sw_management_actualSpeeds_dr_100M 1 408 #define an_x4_sw_management_actualSpeeds_dr_1G 2 409 #define an_x4_sw_management_actualSpeeds_dr_2p5G 3 410 #define an_x4_sw_management_actualSpeeds_dr_5G_X4 4 411 #define an_x4_sw_management_actualSpeeds_dr_6G_X4 5 412 #define an_x4_sw_management_actualSpeeds_dr_10G_HiG 6 413 #define an_x4_sw_management_actualSpeeds_dr_10G_CX4 7 414 #define an_x4_sw_management_actualSpeeds_dr_12G_HiG 8 415 #define an_x4_sw_management_actualSpeeds_dr_12p5G_X4 9 416 #define an_x4_sw_management_actualSpeeds_dr_13G_X4 10 417 #define an_x4_sw_management_actualSpeeds_dr_15G_X4 11 418 #define an_x4_sw_management_actualSpeeds_dr_16G_X4 12 419 #define an_x4_sw_management_actualSpeeds_dr_1G_KX 13 420 #define an_x4_sw_management_actualSpeeds_dr_10G_KX4 14 421 #define an_x4_sw_management_actualSpeeds_dr_10G_KR 15 422 #define an_x4_sw_management_actualSpeeds_dr_5G 16 423 #define an_x4_sw_management_actualSpeeds_dr_6p4G 17 424 #define an_x4_sw_management_actualSpeeds_dr_20G_X4 18 425 #define an_x4_sw_management_actualSpeeds_dr_21G_X4 19 426 #define an_x4_sw_management_actualSpeeds_dr_25G_X4 20 427 #define an_x4_sw_management_actualSpeeds_dr_10G_HiG_DXGXS 21 428 #define an_x4_sw_management_actualSpeeds_dr_10G_DXGXS 22 429 #define an_x4_sw_management_actualSpeeds_dr_10p5G_HiG_DXGXS 23 430 #define an_x4_sw_management_actualSpeeds_dr_10p5G_DXGXS 24 431 #define an_x4_sw_management_actualSpeeds_dr_12p773G_HiG_DXGXS 25 432 #define an_x4_sw_management_actualSpeeds_dr_12p773G_DXGXS 26 433 #define an_x4_sw_management_actualSpeeds_dr_10G_XFI 27 434 #define an_x4_sw_management_actualSpeeds_dr_40G 28 435 #define an_x4_sw_management_actualSpeeds_dr_20G_HiG_DXGXS 29 436 #define an_x4_sw_management_actualSpeeds_dr_20G_DXGXS 30 437 #define an_x4_sw_management_actualSpeeds_dr_10G_SFI 31 438 #define an_x4_sw_management_actualSpeeds_dr_31p5G 32 439 #define an_x4_sw_management_actualSpeeds_dr_32p7G 33 440 #define an_x4_sw_management_actualSpeeds_dr_20G_SCR 34 441 #define an_x4_sw_management_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 442 #define an_x4_sw_management_actualSpeeds_dr_10G_DXGXS_SCR 36 443 #define an_x4_sw_management_actualSpeeds_dr_12G_R2 37 444 #define an_x4_sw_management_actualSpeeds_dr_10G_X2 38 445 #define an_x4_sw_management_actualSpeeds_dr_40G_KR4 39 446 #define an_x4_sw_management_actualSpeeds_dr_40G_CR4 40 447 #define an_x4_sw_management_actualSpeeds_dr_100G_CR10 41 448 #define an_x4_sw_management_actualSpeeds_dr_15p75G_DXGXS 44 449 #define an_x4_sw_management_actualSpeeds_dr_20G_KR2 57 450 #define an_x4_sw_management_actualSpeeds_dr_20G_CR2 58 451 452 /**************************************************************************** 453 * Enums: an_x4_sw_management_actualSpeedsMisc1 454 */ 455 #define an_x4_sw_management_actualSpeedsMisc1_dr_2500BRCM_X1 16 456 #define an_x4_sw_management_actualSpeedsMisc1_dr_5000BRCM_X4 17 457 #define an_x4_sw_management_actualSpeedsMisc1_dr_6000BRCM_X4 18 458 #define an_x4_sw_management_actualSpeedsMisc1_dr_10GHiGig_X4 19 459 #define an_x4_sw_management_actualSpeedsMisc1_dr_10GBASE_CX4 20 460 #define an_x4_sw_management_actualSpeedsMisc1_dr_12GHiGig_X4 21 461 #define an_x4_sw_management_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 462 #define an_x4_sw_management_actualSpeedsMisc1_dr_13GHiGig_X4 23 463 #define an_x4_sw_management_actualSpeedsMisc1_dr_15GHiGig_X4 24 464 #define an_x4_sw_management_actualSpeedsMisc1_dr_16GHiGig_X4 25 465 #define an_x4_sw_management_actualSpeedsMisc1_dr_5000BRCM_X1 26 466 #define an_x4_sw_management_actualSpeedsMisc1_dr_6363BRCM_X1 27 467 #define an_x4_sw_management_actualSpeedsMisc1_dr_20GHiGig_X4 28 468 #define an_x4_sw_management_actualSpeedsMisc1_dr_21GHiGig_X4 29 469 #define an_x4_sw_management_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 470 #define an_x4_sw_management_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 471 472 /**************************************************************************** 473 * Enums: an_x4_sw_management_IndLaneModes 474 */ 475 #define an_x4_sw_management_IndLaneModes_SWSDR_div2 0 476 #define an_x4_sw_management_IndLaneModes_SWSDR_div1 1 477 #define an_x4_sw_management_IndLaneModes_DWSDR_div2 2 478 #define an_x4_sw_management_IndLaneModes_DWSDR_div1 3 479 480 /**************************************************************************** 481 * Enums: an_x4_sw_management_prbsSelect 482 */ 483 #define an_x4_sw_management_prbsSelect_prbs7 0 484 #define an_x4_sw_management_prbsSelect_prbs15 1 485 #define an_x4_sw_management_prbsSelect_prbs23 2 486 #define an_x4_sw_management_prbsSelect_prbs31 3 487 488 /**************************************************************************** 489 * Enums: an_x4_sw_management_vcoDivider 490 */ 491 #define an_x4_sw_management_vcoDivider_div32 0 492 #define an_x4_sw_management_vcoDivider_div36 1 493 #define an_x4_sw_management_vcoDivider_div40 2 494 #define an_x4_sw_management_vcoDivider_div42 3 495 #define an_x4_sw_management_vcoDivider_div48 4 496 #define an_x4_sw_management_vcoDivider_div50 5 497 #define an_x4_sw_management_vcoDivider_div52 6 498 #define an_x4_sw_management_vcoDivider_div54 7 499 #define an_x4_sw_management_vcoDivider_div60 8 500 #define an_x4_sw_management_vcoDivider_div64 9 501 #define an_x4_sw_management_vcoDivider_div66 10 502 #define an_x4_sw_management_vcoDivider_div68 11 503 #define an_x4_sw_management_vcoDivider_div70 12 504 #define an_x4_sw_management_vcoDivider_div80 13 505 #define an_x4_sw_management_vcoDivider_div92 14 506 #define an_x4_sw_management_vcoDivider_div100 15 507 508 /**************************************************************************** 509 * Enums: an_x4_sw_management_refClkSelect 510 */ 511 #define an_x4_sw_management_refClkSelect_clk_25MHz 0 512 #define an_x4_sw_management_refClkSelect_clk_100MHz 1 513 #define an_x4_sw_management_refClkSelect_clk_125MHz 2 514 #define an_x4_sw_management_refClkSelect_clk_156p25MHz 3 515 #define an_x4_sw_management_refClkSelect_clk_187p5MHz 4 516 #define an_x4_sw_management_refClkSelect_clk_161p25Mhz 5 517 #define an_x4_sw_management_refClkSelect_clk_50Mhz 6 518 #define an_x4_sw_management_refClkSelect_clk_106p25Mhz 7 519 520 /**************************************************************************** 521 * Enums: an_x4_sw_management_aerMMDdevTypeSelect 522 */ 523 #define an_x4_sw_management_aerMMDdevTypeSelect_combo_core 0 524 #define an_x4_sw_management_aerMMDdevTypeSelect_PMA_PMD 1 525 #define an_x4_sw_management_aerMMDdevTypeSelect_PCS 3 526 #define an_x4_sw_management_aerMMDdevTypeSelect_PHY 4 527 #define an_x4_sw_management_aerMMDdevTypeSelect_DTE 5 528 #define an_x4_sw_management_aerMMDdevTypeSelect_CL73_AN 7 529 530 /**************************************************************************** 531 * Enums: an_x4_sw_management_aerMMDportSelect 532 */ 533 #define an_x4_sw_management_aerMMDportSelect_ln0 0 534 #define an_x4_sw_management_aerMMDportSelect_ln1 1 535 #define an_x4_sw_management_aerMMDportSelect_ln2 2 536 #define an_x4_sw_management_aerMMDportSelect_ln3 3 537 #define an_x4_sw_management_aerMMDportSelect_BCST_ln0_1_2_3 511 538 #define an_x4_sw_management_aerMMDportSelect_BCST_ln0_1 512 539 #define an_x4_sw_management_aerMMDportSelect_BCST_ln2_3 513 540 541 /**************************************************************************** 542 * Enums: an_x4_sw_management_firmwareModeSelect 543 */ 544 #define an_x4_sw_management_firmwareModeSelect_DEFAULT 0 545 #define an_x4_sw_management_firmwareModeSelect_SFP_OPT_LR 1 546 #define an_x4_sw_management_firmwareModeSelect_SFP_DAC 2 547 #define an_x4_sw_management_firmwareModeSelect_XLAUI 3 548 #define an_x4_sw_management_firmwareModeSelect_LONG_CH_6G 4 549 550 /**************************************************************************** 551 * Enums: an_x4_sw_management_tempIdxSelect 552 */ 553 #define an_x4_sw_management_tempIdxSelect_LTE__22p9C 15 554 #define an_x4_sw_management_tempIdxSelect_LTE__12p6C 14 555 #define an_x4_sw_management_tempIdxSelect_LTE__3p0C 13 556 #define an_x4_sw_management_tempIdxSelect_LTE_6p7C 12 557 #define an_x4_sw_management_tempIdxSelect_LTE_16p4C 11 558 #define an_x4_sw_management_tempIdxSelect_LTE_26p6C 10 559 #define an_x4_sw_management_tempIdxSelect_LTE_36p3C 9 560 #define an_x4_sw_management_tempIdxSelect_LTE_46p0C 8 561 #define an_x4_sw_management_tempIdxSelect_LTE_56p2C 7 562 #define an_x4_sw_management_tempIdxSelect_LTE_65p9C 6 563 #define an_x4_sw_management_tempIdxSelect_LTE_75p6C 5 564 #define an_x4_sw_management_tempIdxSelect_LTE_85p3C 4 565 #define an_x4_sw_management_tempIdxSelect_LTE_95p5C 3 566 #define an_x4_sw_management_tempIdxSelect_LTE_105p2C 2 567 #define an_x4_sw_management_tempIdxSelect_LTE_114p9C 1 568 #define an_x4_sw_management_tempIdxSelect_LTE_125p1C 0 569 570 /**************************************************************************** 571 * Enums: an_x4_sw_management_tla_ln_seq_status 572 */ 573 #define an_x4_sw_management_tla_ln_seq_status_INIT 1 574 #define an_x4_sw_management_tla_ln_seq_status_SET_AN_SPEED 2 575 #define an_x4_sw_management_tla_ln_seq_status_WAIT_AN_SPEED 4 576 #define an_x4_sw_management_tla_ln_seq_status_WAIT_AN_DONE 8 577 #define an_x4_sw_management_tla_ln_seq_status_SET_RS_SPEED 16 578 #define an_x4_sw_management_tla_ln_seq_status_WAIT_RS_CL72EN 32 579 #define an_x4_sw_management_tla_ln_seq_status_WAIT_RS_SPEED 64 580 #define an_x4_sw_management_tla_ln_seq_status_AN_IGNORE_LINK 128 581 #define an_x4_sw_management_tla_ln_seq_status_AN_GOOD_CHECK 256 582 #define an_x4_sw_management_tla_ln_seq_status_AN_GOOD 512 583 #define an_x4_sw_management_tla_ln_seq_status_AN_FAIL 1024 584 #define an_x4_sw_management_tla_ln_seq_status_AN_DEAD 2048 585 #define an_x4_sw_management_tla_ln_seq_status_SET_PD_SPEED 4096 586 #define an_x4_sw_management_tla_ln_seq_status_WAIT_PD_SPEED 8192 587 #define an_x4_sw_management_tla_ln_seq_status_PD_IGNORE_LINK 16384 588 #define an_x4_sw_management_tla_ln_seq_status_PD_GOOD_CHECK 32768 589 590 /**************************************************************************** 591 * Enums: an_x4_sw_management_tla_ln_seq_status1 592 */ 593 #define an_x4_sw_management_tla_ln_seq_status1_SW_SPEED_CHANGE 64 594 #define an_x4_sw_management_tla_ln_seq_status1_RELEASE_SW 32 595 #define an_x4_sw_management_tla_ln_seq_status1_RELEASE_DISABLE 16 596 #define an_x4_sw_management_tla_ln_seq_status1_PD_WAIT_LINK 8 597 #define an_x4_sw_management_tla_ln_seq_status1_PD_START_CL37_AN 4 598 #define an_x4_sw_management_tla_ln_seq_status1_PD_WAIT_CL37_AN_DONE 2 599 #define an_x4_sw_management_tla_ln_seq_status1_PD_DONE_CL37 1 600 601 /**************************************************************************** 602 * Enums: digital_cl36TxEEEStates_l 603 */ 604 #define digital_cl36TxEEEStates_l_TX_REFRESH 8 605 #define digital_cl36TxEEEStates_l_TX_QUIET 4 606 #define digital_cl36TxEEEStates_l_TX_SLEEP 2 607 #define digital_cl36TxEEEStates_l_TX_ACTIVE 1 608 609 /**************************************************************************** 610 * Enums: digital_cl36TxEEEStates_c 611 */ 612 #define digital_cl36TxEEEStates_c_TX_REFRESH 3 613 #define digital_cl36TxEEEStates_c_TX_QUIET 2 614 #define digital_cl36TxEEEStates_c_TX_SLEEP 1 615 #define digital_cl36TxEEEStates_c_TX_ACTIVE 0 616 617 /**************************************************************************** 618 * Enums: digital_cl49TxEEEStates_l 619 */ 620 #define digital_cl49TxEEEStates_l_SCR_RESET_2 64 621 #define digital_cl49TxEEEStates_l_SCR_RESET_1 32 622 #define digital_cl49TxEEEStates_l_TX_WAKE 16 623 #define digital_cl49TxEEEStates_l_TX_REFRESH 8 624 #define digital_cl49TxEEEStates_l_TX_QUIET 4 625 #define digital_cl49TxEEEStates_l_TX_SLEEP 2 626 #define digital_cl49TxEEEStates_l_TX_ACTIVE 1 627 628 /**************************************************************************** 629 * Enums: digital_cl49TxEEEStates_c 630 */ 631 #define digital_cl49TxEEEStates_c_SCR_RESET_2 6 632 #define digital_cl49TxEEEStates_c_SCR_RESET_1 5 633 #define digital_cl49TxEEEStates_c_TX_WAKE 4 634 #define digital_cl49TxEEEStates_c_TX_REFRESH 3 635 #define digital_cl49TxEEEStates_c_TX_QUIET 2 636 #define digital_cl49TxEEEStates_c_TX_SLEEP 1 637 #define digital_cl49TxEEEStates_c_TX_ACTIVE 0 638 639 /**************************************************************************** 640 * Enums: digital_cl36RxEEEStates_l 641 */ 642 #define digital_cl36RxEEEStates_l_RX_LINK_FAIL 32 643 #define digital_cl36RxEEEStates_l_RX_WTF 16 644 #define digital_cl36RxEEEStates_l_RX_WAKE 8 645 #define digital_cl36RxEEEStates_l_RX_QUIET 4 646 #define digital_cl36RxEEEStates_l_RX_SLEEP 2 647 #define digital_cl36RxEEEStates_l_RX_ACTIVE 1 648 649 /**************************************************************************** 650 * Enums: digital_cl36RxEEEStates_c 651 */ 652 #define digital_cl36RxEEEStates_c_RX_LINK_FAIL 5 653 #define digital_cl36RxEEEStates_c_RX_WTF 4 654 #define digital_cl36RxEEEStates_c_RX_WAKE 3 655 #define digital_cl36RxEEEStates_c_RX_QUIET 2 656 #define digital_cl36RxEEEStates_c_RX_SLEEP 1 657 #define digital_cl36RxEEEStates_c_RX_ACTIVE 0 658 659 /**************************************************************************** 660 * Enums: digital_cl49RxEEEStates_l 661 */ 662 #define digital_cl49RxEEEStates_l_RX_LINK_FAIL 32 663 #define digital_cl49RxEEEStates_l_RX_WTF 16 664 #define digital_cl49RxEEEStates_l_RX_WAKE 8 665 #define digital_cl49RxEEEStates_l_RX_QUIET 4 666 #define digital_cl49RxEEEStates_l_RX_SLEEP 2 667 #define digital_cl49RxEEEStates_l_RX_ACTIVE 1 668 669 /**************************************************************************** 670 * Enums: digital_cl49RxEEEStates_c 671 */ 672 #define digital_cl49RxEEEStates_c_RX_LINK_FAIL 5 673 #define digital_cl49RxEEEStates_c_RX_WTF 4 674 #define digital_cl49RxEEEStates_c_RX_WAKE 3 675 #define digital_cl49RxEEEStates_c_RX_QUIET 2 676 #define digital_cl49RxEEEStates_c_RX_SLEEP 1 677 #define digital_cl49RxEEEStates_c_RX_ACTIVE 0 678 679 /**************************************************************************** 680 * Enums: digital_cl48TxEEEStates_l 681 */ 682 #define digital_cl48TxEEEStates_l_TX_REFRESH 8 683 #define digital_cl48TxEEEStates_l_TX_QUIET 4 684 #define digital_cl48TxEEEStates_l_TX_SLEEP 2 685 #define digital_cl48TxEEEStates_l_TX_ACTIVE 1 686 687 /**************************************************************************** 688 * Enums: digital_cl48TxEEEStates_c 689 */ 690 #define digital_cl48TxEEEStates_c_TX_REFRESH 3 691 #define digital_cl48TxEEEStates_c_TX_QUIET 2 692 #define digital_cl48TxEEEStates_c_TX_SLEEP 1 693 #define digital_cl48TxEEEStates_c_TX_ACTIVE 0 694 695 /**************************************************************************** 696 * Enums: digital_cl48RxEEEStates_l 697 */ 698 #define digital_cl48RxEEEStates_l_RX_LINK_FAIL 32 699 #define digital_cl48RxEEEStates_l_RX_WAKE 16 700 #define digital_cl48RxEEEStates_l_RX_QUIET 8 701 #define digital_cl48RxEEEStates_l_RX_DEACT 4 702 #define digital_cl48RxEEEStates_l_RX_SLEEP 2 703 #define digital_cl48RxEEEStates_l_RX_ACTIVE 1 704 705 /**************************************************************************** 706 * Enums: digital_cl48RxEEEStates_c 707 */ 708 #define digital_cl48RxEEEStates_c_RX_LINK_FAIL 5 709 #define digital_cl48RxEEEStates_c_RX_WAKE 4 710 #define digital_cl48RxEEEStates_c_RX_QUIET 3 711 #define digital_cl48RxEEEStates_c_RX_DEACT 2 712 #define digital_cl48RxEEEStates_c_RX_SLEEP 1 713 #define digital_cl48RxEEEStates_c_RX_ACTIVE 0 714 715 /**************************************************************************** 716 * Enums: digital_IQP_Options 717 */ 718 #define digital_IQP_Options_i50uA 0 719 #define digital_IQP_Options_i100uA 1 720 #define digital_IQP_Options_i150uA 2 721 #define digital_IQP_Options_i200uA 3 722 #define digital_IQP_Options_i250uA 4 723 #define digital_IQP_Options_i300uA 5 724 #define digital_IQP_Options_i350uA 6 725 #define digital_IQP_Options_i400uA 7 726 #define digital_IQP_Options_i450uA 8 727 #define digital_IQP_Options_i500uA 9 728 #define digital_IQP_Options_i550uA 10 729 #define digital_IQP_Options_i600uA 11 730 #define digital_IQP_Options_i650uA 12 731 #define digital_IQP_Options_i700uA 13 732 #define digital_IQP_Options_i750uA 14 733 #define digital_IQP_Options_i800uA 15 734 735 /**************************************************************************** 736 * Enums: digital_IDriver_Options 737 */ 738 #define digital_IDriver_Options_v680mV 0 739 #define digital_IDriver_Options_v730mV 1 740 #define digital_IDriver_Options_v780mV 2 741 #define digital_IDriver_Options_v830mV 3 742 #define digital_IDriver_Options_v880mV 4 743 #define digital_IDriver_Options_v930mV 5 744 #define digital_IDriver_Options_v980mV 6 745 #define digital_IDriver_Options_v1010mV 7 746 #define digital_IDriver_Options_v1040mV 8 747 #define digital_IDriver_Options_v1060mV 9 748 #define digital_IDriver_Options_v1070mV 10 749 #define digital_IDriver_Options_v1080mV 11 750 #define digital_IDriver_Options_v1085mV 12 751 #define digital_IDriver_Options_v1090mV 13 752 #define digital_IDriver_Options_v1095mV 14 753 #define digital_IDriver_Options_v1100mV 15 754 755 /**************************************************************************** 756 * Enums: digital_operationModes 757 */ 758 #define digital_operationModes_XGXS 0 759 #define digital_operationModes_XGXG_nCC 1 760 #define digital_operationModes_Indlane_OS8 4 761 #define digital_operationModes_IndLane_OS5 5 762 #define digital_operationModes_PCI 7 763 #define digital_operationModes_XGXS_nLQ 8 764 #define digital_operationModes_XGXS_nLQnCC 9 765 #define digital_operationModes_PBypass 10 766 #define digital_operationModes_PBypass_nDSK 11 767 #define digital_operationModes_ComboCoreMode 12 768 #define digital_operationModes_Clocks_off 15 769 770 /**************************************************************************** 771 * Enums: digital_synce_enum 772 */ 773 #define digital_synce_enum_SYNCE_NO_DIV 0 774 #define digital_synce_enum_SYNCE_DIV_7 1 775 #define digital_synce_enum_SYNCE_DIV_11 2 776 #define digital_synce_enum_SYNCE_DIV_10 3 777 778 /**************************************************************************** 779 * Enums: digital_synce_enum_stage0 780 */ 781 #define digital_synce_enum_stage0_SYNCE_NO_DIV 0 782 #define digital_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 783 #define digital_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 784 785 /**************************************************************************** 786 * Enums: digital_operationSpeeds 787 */ 788 #define digital_operationSpeeds_SPEED_10G_X4_10p3125 59 789 #define digital_operationSpeeds_SPEED_10G_CX4_10p3125 58 790 #define digital_operationSpeeds_SPEED_10G_KX4_10p3125 57 791 #define digital_operationSpeeds_SPEED_2p5G_X1_10p3125 56 792 #define digital_operationSpeeds_SPEED_1000M_10p3125 55 793 #define digital_operationSpeeds_SPEED_100M_10p3125 54 794 #define digital_operationSpeeds_SPEED_10M_10p3125 53 795 #define digital_operationSpeeds_SPEED_10p5G_X4 50 796 #define digital_operationSpeeds_SPEED_5G_KR1 49 797 #define digital_operationSpeeds_SPEED_42p42G_X4 44 798 #define digital_operationSpeeds_SPEED_21p21G_X2 43 799 #define digital_operationSpeeds_SPEED_48p48G_X4 42 800 #define digital_operationSpeeds_SPEED_24p24G_X2 41 801 #define digital_operationSpeeds_SPEED_12p12G_X1 40 802 #define digital_operationSpeeds_SPEED_127G_X12 39 803 #define digital_operationSpeeds_SPEED_120G_X12 38 804 #define digital_operationSpeeds_SPEED_107G_X10 37 805 #define digital_operationSpeeds_SPEED_100G_CR10 36 806 #define digital_operationSpeeds_SPEED_42G_X4 35 807 #define digital_operationSpeeds_SPEED_40G_CR4 34 808 #define digital_operationSpeeds_SPEED_40G_KR4 33 809 #define digital_operationSpeeds_SPEED_21G_X2 32 810 #define digital_operationSpeeds_SPEED_20G_CR2 31 811 #define digital_operationSpeeds_SPEED_20G_KR2 30 812 #define digital_operationSpeeds_SPEED_10p6_X1 29 813 #define digital_operationSpeeds_SPEED_10G_KR1 28 814 #define digital_operationSpeeds_SPEED_40G_X4 27 815 #define digital_operationSpeeds_SPEED_20G_X2 26 816 #define digital_operationSpeeds_SPEED_20G_CX2 25 817 #define digital_operationSpeeds_SPEED_31p5G_KR4 24 818 #define digital_operationSpeeds_SPEED_31p5G_X4 23 819 #define digital_operationSpeeds_SPEED_15p75G_X2 22 820 #define digital_operationSpeeds_SPEED_25p45G_X4 21 821 #define digital_operationSpeeds_SPEED_12p7G_X2 20 822 #define digital_operationSpeeds_SPEED_21G_X4 19 823 #define digital_operationSpeeds_SPEED_10p5G_X2 18 824 #define digital_operationSpeeds_SPEED_20G_X4 17 825 #define digital_operationSpeeds_SPEED_10G_X2 16 826 #define digital_operationSpeeds_SPEED_10G_CX2 15 827 #define digital_operationSpeeds_SPEED_20G_CX4 14 828 #define digital_operationSpeeds_SPEED_16G_X4 13 829 #define digital_operationSpeeds_SPEED_15G_X4 12 830 #define digital_operationSpeeds_SPEED_13G_X4 11 831 #define digital_operationSpeeds_SPEED_10G_X4 10 832 #define digital_operationSpeeds_SPEED_10G_KX4 9 833 #define digital_operationSpeeds_SPEED_10G_CX4 8 834 #define digital_operationSpeeds_SPEED_5G_X1 7 835 #define digital_operationSpeeds_SPEED_2p5G_X1 6 836 #define digital_operationSpeeds_SPEED_1G_KX1 5 837 #define digital_operationSpeeds_SPEED_1G_CX1 4 838 #define digital_operationSpeeds_SPEED_1000M 3 839 #define digital_operationSpeeds_SPEED_100M 2 840 #define digital_operationSpeeds_SPEED_10M 1 841 842 /**************************************************************************** 843 * Enums: digital_actualSpeeds 844 */ 845 #define digital_actualSpeeds_dr_10M 0 846 #define digital_actualSpeeds_dr_100M 1 847 #define digital_actualSpeeds_dr_1G 2 848 #define digital_actualSpeeds_dr_2p5G 3 849 #define digital_actualSpeeds_dr_5G_X4 4 850 #define digital_actualSpeeds_dr_6G_X4 5 851 #define digital_actualSpeeds_dr_10G_HiG 6 852 #define digital_actualSpeeds_dr_10G_CX4 7 853 #define digital_actualSpeeds_dr_12G_HiG 8 854 #define digital_actualSpeeds_dr_12p5G_X4 9 855 #define digital_actualSpeeds_dr_13G_X4 10 856 #define digital_actualSpeeds_dr_15G_X4 11 857 #define digital_actualSpeeds_dr_16G_X4 12 858 #define digital_actualSpeeds_dr_1G_KX 13 859 #define digital_actualSpeeds_dr_10G_KX4 14 860 #define digital_actualSpeeds_dr_10G_KR 15 861 #define digital_actualSpeeds_dr_5G 16 862 #define digital_actualSpeeds_dr_6p4G 17 863 #define digital_actualSpeeds_dr_20G_X4 18 864 #define digital_actualSpeeds_dr_21G_X4 19 865 #define digital_actualSpeeds_dr_25G_X4 20 866 #define digital_actualSpeeds_dr_10G_HiG_DXGXS 21 867 #define digital_actualSpeeds_dr_10G_DXGXS 22 868 #define digital_actualSpeeds_dr_10p5G_HiG_DXGXS 23 869 #define digital_actualSpeeds_dr_10p5G_DXGXS 24 870 #define digital_actualSpeeds_dr_12p773G_HiG_DXGXS 25 871 #define digital_actualSpeeds_dr_12p773G_DXGXS 26 872 #define digital_actualSpeeds_dr_10G_XFI 27 873 #define digital_actualSpeeds_dr_40G 28 874 #define digital_actualSpeeds_dr_20G_HiG_DXGXS 29 875 #define digital_actualSpeeds_dr_20G_DXGXS 30 876 #define digital_actualSpeeds_dr_10G_SFI 31 877 #define digital_actualSpeeds_dr_31p5G 32 878 #define digital_actualSpeeds_dr_32p7G 33 879 #define digital_actualSpeeds_dr_20G_SCR 34 880 #define digital_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 881 #define digital_actualSpeeds_dr_10G_DXGXS_SCR 36 882 #define digital_actualSpeeds_dr_12G_R2 37 883 #define digital_actualSpeeds_dr_10G_X2 38 884 #define digital_actualSpeeds_dr_40G_KR4 39 885 #define digital_actualSpeeds_dr_40G_CR4 40 886 #define digital_actualSpeeds_dr_100G_CR10 41 887 #define digital_actualSpeeds_dr_15p75G_DXGXS 44 888 #define digital_actualSpeeds_dr_20G_KR2 57 889 #define digital_actualSpeeds_dr_20G_CR2 58 890 891 /**************************************************************************** 892 * Enums: digital_actualSpeedsMisc1 893 */ 894 #define digital_actualSpeedsMisc1_dr_2500BRCM_X1 16 895 #define digital_actualSpeedsMisc1_dr_5000BRCM_X4 17 896 #define digital_actualSpeedsMisc1_dr_6000BRCM_X4 18 897 #define digital_actualSpeedsMisc1_dr_10GHiGig_X4 19 898 #define digital_actualSpeedsMisc1_dr_10GBASE_CX4 20 899 #define digital_actualSpeedsMisc1_dr_12GHiGig_X4 21 900 #define digital_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 901 #define digital_actualSpeedsMisc1_dr_13GHiGig_X4 23 902 #define digital_actualSpeedsMisc1_dr_15GHiGig_X4 24 903 #define digital_actualSpeedsMisc1_dr_16GHiGig_X4 25 904 #define digital_actualSpeedsMisc1_dr_5000BRCM_X1 26 905 #define digital_actualSpeedsMisc1_dr_6363BRCM_X1 27 906 #define digital_actualSpeedsMisc1_dr_20GHiGig_X4 28 907 #define digital_actualSpeedsMisc1_dr_21GHiGig_X4 29 908 #define digital_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 909 #define digital_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 910 911 /**************************************************************************** 912 * Enums: digital_IndLaneModes 913 */ 914 #define digital_IndLaneModes_SWSDR_div2 0 915 #define digital_IndLaneModes_SWSDR_div1 1 916 #define digital_IndLaneModes_DWSDR_div2 2 917 #define digital_IndLaneModes_DWSDR_div1 3 918 919 /**************************************************************************** 920 * Enums: digital_prbsSelect 921 */ 922 #define digital_prbsSelect_prbs7 0 923 #define digital_prbsSelect_prbs15 1 924 #define digital_prbsSelect_prbs23 2 925 #define digital_prbsSelect_prbs31 3 926 927 /**************************************************************************** 928 * Enums: digital_vcoDivider 929 */ 930 #define digital_vcoDivider_div32 0 931 #define digital_vcoDivider_div36 1 932 #define digital_vcoDivider_div40 2 933 #define digital_vcoDivider_div42 3 934 #define digital_vcoDivider_div48 4 935 #define digital_vcoDivider_div50 5 936 #define digital_vcoDivider_div52 6 937 #define digital_vcoDivider_div54 7 938 #define digital_vcoDivider_div60 8 939 #define digital_vcoDivider_div64 9 940 #define digital_vcoDivider_div66 10 941 #define digital_vcoDivider_div68 11 942 #define digital_vcoDivider_div70 12 943 #define digital_vcoDivider_div80 13 944 #define digital_vcoDivider_div92 14 945 #define digital_vcoDivider_div100 15 946 947 /**************************************************************************** 948 * Enums: digital_refClkSelect 949 */ 950 #define digital_refClkSelect_clk_25MHz 0 951 #define digital_refClkSelect_clk_100MHz 1 952 #define digital_refClkSelect_clk_125MHz 2 953 #define digital_refClkSelect_clk_156p25MHz 3 954 #define digital_refClkSelect_clk_187p5MHz 4 955 #define digital_refClkSelect_clk_161p25Mhz 5 956 #define digital_refClkSelect_clk_50Mhz 6 957 #define digital_refClkSelect_clk_106p25Mhz 7 958 959 /**************************************************************************** 960 * Enums: digital_aerMMDdevTypeSelect 961 */ 962 #define digital_aerMMDdevTypeSelect_combo_core 0 963 #define digital_aerMMDdevTypeSelect_PMA_PMD 1 964 #define digital_aerMMDdevTypeSelect_PCS 3 965 #define digital_aerMMDdevTypeSelect_PHY 4 966 #define digital_aerMMDdevTypeSelect_DTE 5 967 #define digital_aerMMDdevTypeSelect_CL73_AN 7 968 969 /**************************************************************************** 970 * Enums: digital_aerMMDportSelect 971 */ 972 #define digital_aerMMDportSelect_ln0 0 973 #define digital_aerMMDportSelect_ln1 1 974 #define digital_aerMMDportSelect_ln2 2 975 #define digital_aerMMDportSelect_ln3 3 976 #define digital_aerMMDportSelect_BCST_ln0_1_2_3 511 977 #define digital_aerMMDportSelect_BCST_ln0_1 512 978 #define digital_aerMMDportSelect_BCST_ln2_3 513 979 980 /**************************************************************************** 981 * Enums: digital_firmwareModeSelect 982 */ 983 #define digital_firmwareModeSelect_DEFAULT 0 984 #define digital_firmwareModeSelect_SFP_OPT_LR 1 985 #define digital_firmwareModeSelect_SFP_DAC 2 986 #define digital_firmwareModeSelect_XLAUI 3 987 #define digital_firmwareModeSelect_LONG_CH_6G 4 988 989 /**************************************************************************** 990 * Enums: digital_tempIdxSelect 991 */ 992 #define digital_tempIdxSelect_LTE__22p9C 15 993 #define digital_tempIdxSelect_LTE__12p6C 14 994 #define digital_tempIdxSelect_LTE__3p0C 13 995 #define digital_tempIdxSelect_LTE_6p7C 12 996 #define digital_tempIdxSelect_LTE_16p4C 11 997 #define digital_tempIdxSelect_LTE_26p6C 10 998 #define digital_tempIdxSelect_LTE_36p3C 9 999 #define digital_tempIdxSelect_LTE_46p0C 8 1000 #define digital_tempIdxSelect_LTE_56p2C 7 1001 #define digital_tempIdxSelect_LTE_65p9C 6 1002 #define digital_tempIdxSelect_LTE_75p6C 5 1003 #define digital_tempIdxSelect_LTE_85p3C 4 1004 #define digital_tempIdxSelect_LTE_95p5C 3 1005 #define digital_tempIdxSelect_LTE_105p2C 2 1006 #define digital_tempIdxSelect_LTE_114p9C 1 1007 #define digital_tempIdxSelect_LTE_125p1C 0 1008 1009 /**************************************************************************** 1010 * Enums: generic_cl36TxEEEStates_l 1011 */ 1012 #define generic_cl36TxEEEStates_l_TX_REFRESH 8 1013 #define generic_cl36TxEEEStates_l_TX_QUIET 4 1014 #define generic_cl36TxEEEStates_l_TX_SLEEP 2 1015 #define generic_cl36TxEEEStates_l_TX_ACTIVE 1 1016 1017 /**************************************************************************** 1018 * Enums: generic_cl36TxEEEStates_c 1019 */ 1020 #define generic_cl36TxEEEStates_c_TX_REFRESH 3 1021 #define generic_cl36TxEEEStates_c_TX_QUIET 2 1022 #define generic_cl36TxEEEStates_c_TX_SLEEP 1 1023 #define generic_cl36TxEEEStates_c_TX_ACTIVE 0 1024 1025 /**************************************************************************** 1026 * Enums: generic_cl49TxEEEStates_l 1027 */ 1028 #define generic_cl49TxEEEStates_l_SCR_RESET_2 64 1029 #define generic_cl49TxEEEStates_l_SCR_RESET_1 32 1030 #define generic_cl49TxEEEStates_l_TX_WAKE 16 1031 #define generic_cl49TxEEEStates_l_TX_REFRESH 8 1032 #define generic_cl49TxEEEStates_l_TX_QUIET 4 1033 #define generic_cl49TxEEEStates_l_TX_SLEEP 2 1034 #define generic_cl49TxEEEStates_l_TX_ACTIVE 1 1035 1036 /**************************************************************************** 1037 * Enums: generic_cl49TxEEEStates_c 1038 */ 1039 #define generic_cl49TxEEEStates_c_SCR_RESET_2 6 1040 #define generic_cl49TxEEEStates_c_SCR_RESET_1 5 1041 #define generic_cl49TxEEEStates_c_TX_WAKE 4 1042 #define generic_cl49TxEEEStates_c_TX_REFRESH 3 1043 #define generic_cl49TxEEEStates_c_TX_QUIET 2 1044 #define generic_cl49TxEEEStates_c_TX_SLEEP 1 1045 #define generic_cl49TxEEEStates_c_TX_ACTIVE 0 1046 1047 /**************************************************************************** 1048 * Enums: generic_cl36RxEEEStates_l 1049 */ 1050 #define generic_cl36RxEEEStates_l_RX_LINK_FAIL 32 1051 #define generic_cl36RxEEEStates_l_RX_WTF 16 1052 #define generic_cl36RxEEEStates_l_RX_WAKE 8 1053 #define generic_cl36RxEEEStates_l_RX_QUIET 4 1054 #define generic_cl36RxEEEStates_l_RX_SLEEP 2 1055 #define generic_cl36RxEEEStates_l_RX_ACTIVE 1 1056 1057 /**************************************************************************** 1058 * Enums: generic_cl36RxEEEStates_c 1059 */ 1060 #define generic_cl36RxEEEStates_c_RX_LINK_FAIL 5 1061 #define generic_cl36RxEEEStates_c_RX_WTF 4 1062 #define generic_cl36RxEEEStates_c_RX_WAKE 3 1063 #define generic_cl36RxEEEStates_c_RX_QUIET 2 1064 #define generic_cl36RxEEEStates_c_RX_SLEEP 1 1065 #define generic_cl36RxEEEStates_c_RX_ACTIVE 0 1066 1067 /**************************************************************************** 1068 * Enums: generic_cl49RxEEEStates_l 1069 */ 1070 #define generic_cl49RxEEEStates_l_RX_LINK_FAIL 32 1071 #define generic_cl49RxEEEStates_l_RX_WTF 16 1072 #define generic_cl49RxEEEStates_l_RX_WAKE 8 1073 #define generic_cl49RxEEEStates_l_RX_QUIET 4 1074 #define generic_cl49RxEEEStates_l_RX_SLEEP 2 1075 #define generic_cl49RxEEEStates_l_RX_ACTIVE 1 1076 1077 /**************************************************************************** 1078 * Enums: generic_cl49RxEEEStates_c 1079 */ 1080 #define generic_cl49RxEEEStates_c_RX_LINK_FAIL 5 1081 #define generic_cl49RxEEEStates_c_RX_WTF 4 1082 #define generic_cl49RxEEEStates_c_RX_WAKE 3 1083 #define generic_cl49RxEEEStates_c_RX_QUIET 2 1084 #define generic_cl49RxEEEStates_c_RX_SLEEP 1 1085 #define generic_cl49RxEEEStates_c_RX_ACTIVE 0 1086 1087 /**************************************************************************** 1088 * Enums: generic_cl48TxEEEStates_l 1089 */ 1090 #define generic_cl48TxEEEStates_l_TX_REFRESH 8 1091 #define generic_cl48TxEEEStates_l_TX_QUIET 4 1092 #define generic_cl48TxEEEStates_l_TX_SLEEP 2 1093 #define generic_cl48TxEEEStates_l_TX_ACTIVE 1 1094 1095 /**************************************************************************** 1096 * Enums: generic_cl48TxEEEStates_c 1097 */ 1098 #define generic_cl48TxEEEStates_c_TX_REFRESH 3 1099 #define generic_cl48TxEEEStates_c_TX_QUIET 2 1100 #define generic_cl48TxEEEStates_c_TX_SLEEP 1 1101 #define generic_cl48TxEEEStates_c_TX_ACTIVE 0 1102 1103 /**************************************************************************** 1104 * Enums: generic_cl48RxEEEStates_l 1105 */ 1106 #define generic_cl48RxEEEStates_l_RX_LINK_FAIL 32 1107 #define generic_cl48RxEEEStates_l_RX_WAKE 16 1108 #define generic_cl48RxEEEStates_l_RX_QUIET 8 1109 #define generic_cl48RxEEEStates_l_RX_DEACT 4 1110 #define generic_cl48RxEEEStates_l_RX_SLEEP 2 1111 #define generic_cl48RxEEEStates_l_RX_ACTIVE 1 1112 1113 /**************************************************************************** 1114 * Enums: generic_cl48RxEEEStates_c 1115 */ 1116 #define generic_cl48RxEEEStates_c_RX_LINK_FAIL 5 1117 #define generic_cl48RxEEEStates_c_RX_WAKE 4 1118 #define generic_cl48RxEEEStates_c_RX_QUIET 3 1119 #define generic_cl48RxEEEStates_c_RX_DEACT 2 1120 #define generic_cl48RxEEEStates_c_RX_SLEEP 1 1121 #define generic_cl48RxEEEStates_c_RX_ACTIVE 0 1122 1123 /**************************************************************************** 1124 * Enums: generic_IQP_Options 1125 */ 1126 #define generic_IQP_Options_i50uA 0 1127 #define generic_IQP_Options_i100uA 1 1128 #define generic_IQP_Options_i150uA 2 1129 #define generic_IQP_Options_i200uA 3 1130 #define generic_IQP_Options_i250uA 4 1131 #define generic_IQP_Options_i300uA 5 1132 #define generic_IQP_Options_i350uA 6 1133 #define generic_IQP_Options_i400uA 7 1134 #define generic_IQP_Options_i450uA 8 1135 #define generic_IQP_Options_i500uA 9 1136 #define generic_IQP_Options_i550uA 10 1137 #define generic_IQP_Options_i600uA 11 1138 #define generic_IQP_Options_i650uA 12 1139 #define generic_IQP_Options_i700uA 13 1140 #define generic_IQP_Options_i750uA 14 1141 #define generic_IQP_Options_i800uA 15 1142 1143 /**************************************************************************** 1144 * Enums: generic_IDriver_Options 1145 */ 1146 #define generic_IDriver_Options_v680mV 0 1147 #define generic_IDriver_Options_v730mV 1 1148 #define generic_IDriver_Options_v780mV 2 1149 #define generic_IDriver_Options_v830mV 3 1150 #define generic_IDriver_Options_v880mV 4 1151 #define generic_IDriver_Options_v930mV 5 1152 #define generic_IDriver_Options_v980mV 6 1153 #define generic_IDriver_Options_v1010mV 7 1154 #define generic_IDriver_Options_v1040mV 8 1155 #define generic_IDriver_Options_v1060mV 9 1156 #define generic_IDriver_Options_v1070mV 10 1157 #define generic_IDriver_Options_v1080mV 11 1158 #define generic_IDriver_Options_v1085mV 12 1159 #define generic_IDriver_Options_v1090mV 13 1160 #define generic_IDriver_Options_v1095mV 14 1161 #define generic_IDriver_Options_v1100mV 15 1162 1163 /**************************************************************************** 1164 * Enums: generic_operationModes 1165 */ 1166 #define generic_operationModes_XGXS 0 1167 #define generic_operationModes_XGXG_nCC 1 1168 #define generic_operationModes_Indlane_OS8 4 1169 #define generic_operationModes_IndLane_OS5 5 1170 #define generic_operationModes_PCI 7 1171 #define generic_operationModes_XGXS_nLQ 8 1172 #define generic_operationModes_XGXS_nLQnCC 9 1173 #define generic_operationModes_PBypass 10 1174 #define generic_operationModes_PBypass_nDSK 11 1175 #define generic_operationModes_ComboCoreMode 12 1176 #define generic_operationModes_Clocks_off 15 1177 1178 /**************************************************************************** 1179 * Enums: generic_synce_enum 1180 */ 1181 #define generic_synce_enum_SYNCE_NO_DIV 0 1182 #define generic_synce_enum_SYNCE_DIV_7 1 1183 #define generic_synce_enum_SYNCE_DIV_11 2 1184 #define generic_synce_enum_SYNCE_DIV_10 3 1185 1186 /**************************************************************************** 1187 * Enums: generic_synce_enum_stage0 1188 */ 1189 #define generic_synce_enum_stage0_SYNCE_NO_DIV 0 1190 #define generic_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 1191 #define generic_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 1192 1193 /**************************************************************************** 1194 * Enums: generic_operationSpeeds 1195 */ 1196 #define generic_operationSpeeds_SPEED_10G_X4_10p3125 59 1197 #define generic_operationSpeeds_SPEED_10G_CX4_10p3125 58 1198 #define generic_operationSpeeds_SPEED_10G_KX4_10p3125 57 1199 #define generic_operationSpeeds_SPEED_2p5G_X1_10p3125 56 1200 #define generic_operationSpeeds_SPEED_1000M_10p3125 55 1201 #define generic_operationSpeeds_SPEED_100M_10p3125 54 1202 #define generic_operationSpeeds_SPEED_10M_10p3125 53 1203 #define generic_operationSpeeds_SPEED_10p5G_X4 50 1204 #define generic_operationSpeeds_SPEED_5G_KR1 49 1205 #define generic_operationSpeeds_SPEED_42p42G_X4 44 1206 #define generic_operationSpeeds_SPEED_21p21G_X2 43 1207 #define generic_operationSpeeds_SPEED_48p48G_X4 42 1208 #define generic_operationSpeeds_SPEED_24p24G_X2 41 1209 #define generic_operationSpeeds_SPEED_12p12G_X1 40 1210 #define generic_operationSpeeds_SPEED_127G_X12 39 1211 #define generic_operationSpeeds_SPEED_120G_X12 38 1212 #define generic_operationSpeeds_SPEED_107G_X10 37 1213 #define generic_operationSpeeds_SPEED_100G_CR10 36 1214 #define generic_operationSpeeds_SPEED_42G_X4 35 1215 #define generic_operationSpeeds_SPEED_40G_CR4 34 1216 #define generic_operationSpeeds_SPEED_40G_KR4 33 1217 #define generic_operationSpeeds_SPEED_21G_X2 32 1218 #define generic_operationSpeeds_SPEED_20G_CR2 31 1219 #define generic_operationSpeeds_SPEED_20G_KR2 30 1220 #define generic_operationSpeeds_SPEED_10p6_X1 29 1221 #define generic_operationSpeeds_SPEED_10G_KR1 28 1222 #define generic_operationSpeeds_SPEED_40G_X4 27 1223 #define generic_operationSpeeds_SPEED_20G_X2 26 1224 #define generic_operationSpeeds_SPEED_20G_CX2 25 1225 #define generic_operationSpeeds_SPEED_31p5G_KR4 24 1226 #define generic_operationSpeeds_SPEED_31p5G_X4 23 1227 #define generic_operationSpeeds_SPEED_15p75G_X2 22 1228 #define generic_operationSpeeds_SPEED_25p45G_X4 21 1229 #define generic_operationSpeeds_SPEED_12p7G_X2 20 1230 #define generic_operationSpeeds_SPEED_21G_X4 19 1231 #define generic_operationSpeeds_SPEED_10p5G_X2 18 1232 #define generic_operationSpeeds_SPEED_20G_X4 17 1233 #define generic_operationSpeeds_SPEED_10G_X2 16 1234 #define generic_operationSpeeds_SPEED_10G_CX2 15 1235 #define generic_operationSpeeds_SPEED_20G_CX4 14 1236 #define generic_operationSpeeds_SPEED_16G_X4 13 1237 #define generic_operationSpeeds_SPEED_15G_X4 12 1238 #define generic_operationSpeeds_SPEED_13G_X4 11 1239 #define generic_operationSpeeds_SPEED_10G_X4 10 1240 #define generic_operationSpeeds_SPEED_10G_KX4 9 1241 #define generic_operationSpeeds_SPEED_10G_CX4 8 1242 #define generic_operationSpeeds_SPEED_5G_X1 7 1243 #define generic_operationSpeeds_SPEED_2p5G_X1 6 1244 #define generic_operationSpeeds_SPEED_1G_KX1 5 1245 #define generic_operationSpeeds_SPEED_1G_CX1 4 1246 #define generic_operationSpeeds_SPEED_1000M 3 1247 #define generic_operationSpeeds_SPEED_100M 2 1248 #define generic_operationSpeeds_SPEED_10M 1 1249 1250 /**************************************************************************** 1251 * Enums: generic_actualSpeeds 1252 */ 1253 #define generic_actualSpeeds_dr_10M 0 1254 #define generic_actualSpeeds_dr_100M 1 1255 #define generic_actualSpeeds_dr_1G 2 1256 #define generic_actualSpeeds_dr_2p5G 3 1257 #define generic_actualSpeeds_dr_5G_X4 4 1258 #define generic_actualSpeeds_dr_6G_X4 5 1259 #define generic_actualSpeeds_dr_10G_HiG 6 1260 #define generic_actualSpeeds_dr_10G_CX4 7 1261 #define generic_actualSpeeds_dr_12G_HiG 8 1262 #define generic_actualSpeeds_dr_12p5G_X4 9 1263 #define generic_actualSpeeds_dr_13G_X4 10 1264 #define generic_actualSpeeds_dr_15G_X4 11 1265 #define generic_actualSpeeds_dr_16G_X4 12 1266 #define generic_actualSpeeds_dr_1G_KX 13 1267 #define generic_actualSpeeds_dr_10G_KX4 14 1268 #define generic_actualSpeeds_dr_10G_KR 15 1269 #define generic_actualSpeeds_dr_5G 16 1270 #define generic_actualSpeeds_dr_6p4G 17 1271 #define generic_actualSpeeds_dr_20G_X4 18 1272 #define generic_actualSpeeds_dr_21G_X4 19 1273 #define generic_actualSpeeds_dr_25G_X4 20 1274 #define generic_actualSpeeds_dr_10G_HiG_DXGXS 21 1275 #define generic_actualSpeeds_dr_10G_DXGXS 22 1276 #define generic_actualSpeeds_dr_10p5G_HiG_DXGXS 23 1277 #define generic_actualSpeeds_dr_10p5G_DXGXS 24 1278 #define generic_actualSpeeds_dr_12p773G_HiG_DXGXS 25 1279 #define generic_actualSpeeds_dr_12p773G_DXGXS 26 1280 #define generic_actualSpeeds_dr_10G_XFI 27 1281 #define generic_actualSpeeds_dr_40G 28 1282 #define generic_actualSpeeds_dr_20G_HiG_DXGXS 29 1283 #define generic_actualSpeeds_dr_20G_DXGXS 30 1284 #define generic_actualSpeeds_dr_10G_SFI 31 1285 #define generic_actualSpeeds_dr_31p5G 32 1286 #define generic_actualSpeeds_dr_32p7G 33 1287 #define generic_actualSpeeds_dr_20G_SCR 34 1288 #define generic_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 1289 #define generic_actualSpeeds_dr_10G_DXGXS_SCR 36 1290 #define generic_actualSpeeds_dr_12G_R2 37 1291 #define generic_actualSpeeds_dr_10G_X2 38 1292 #define generic_actualSpeeds_dr_40G_KR4 39 1293 #define generic_actualSpeeds_dr_40G_CR4 40 1294 #define generic_actualSpeeds_dr_100G_CR10 41 1295 #define generic_actualSpeeds_dr_15p75G_DXGXS 44 1296 #define generic_actualSpeeds_dr_20G_KR2 57 1297 #define generic_actualSpeeds_dr_20G_CR2 58 1298 1299 /**************************************************************************** 1300 * Enums: generic_actualSpeedsMisc1 1301 */ 1302 #define generic_actualSpeedsMisc1_dr_2500BRCM_X1 16 1303 #define generic_actualSpeedsMisc1_dr_5000BRCM_X4 17 1304 #define generic_actualSpeedsMisc1_dr_6000BRCM_X4 18 1305 #define generic_actualSpeedsMisc1_dr_10GHiGig_X4 19 1306 #define generic_actualSpeedsMisc1_dr_10GBASE_CX4 20 1307 #define generic_actualSpeedsMisc1_dr_12GHiGig_X4 21 1308 #define generic_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 1309 #define generic_actualSpeedsMisc1_dr_13GHiGig_X4 23 1310 #define generic_actualSpeedsMisc1_dr_15GHiGig_X4 24 1311 #define generic_actualSpeedsMisc1_dr_16GHiGig_X4 25 1312 #define generic_actualSpeedsMisc1_dr_5000BRCM_X1 26 1313 #define generic_actualSpeedsMisc1_dr_6363BRCM_X1 27 1314 #define generic_actualSpeedsMisc1_dr_20GHiGig_X4 28 1315 #define generic_actualSpeedsMisc1_dr_21GHiGig_X4 29 1316 #define generic_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 1317 #define generic_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 1318 1319 /**************************************************************************** 1320 * Enums: generic_IndLaneModes 1321 */ 1322 #define generic_IndLaneModes_SWSDR_div2 0 1323 #define generic_IndLaneModes_SWSDR_div1 1 1324 #define generic_IndLaneModes_DWSDR_div2 2 1325 #define generic_IndLaneModes_DWSDR_div1 3 1326 1327 /**************************************************************************** 1328 * Enums: generic_prbsSelect 1329 */ 1330 #define generic_prbsSelect_prbs7 0 1331 #define generic_prbsSelect_prbs15 1 1332 #define generic_prbsSelect_prbs23 2 1333 #define generic_prbsSelect_prbs31 3 1334 1335 /**************************************************************************** 1336 * Enums: generic_vcoDivider 1337 */ 1338 #define generic_vcoDivider_div32 0 1339 #define generic_vcoDivider_div36 1 1340 #define generic_vcoDivider_div40 2 1341 #define generic_vcoDivider_div42 3 1342 #define generic_vcoDivider_div48 4 1343 #define generic_vcoDivider_div50 5 1344 #define generic_vcoDivider_div52 6 1345 #define generic_vcoDivider_div54 7 1346 #define generic_vcoDivider_div60 8 1347 #define generic_vcoDivider_div64 9 1348 #define generic_vcoDivider_div66 10 1349 #define generic_vcoDivider_div68 11 1350 #define generic_vcoDivider_div70 12 1351 #define generic_vcoDivider_div80 13 1352 #define generic_vcoDivider_div92 14 1353 #define generic_vcoDivider_div100 15 1354 1355 /**************************************************************************** 1356 * Enums: generic_refClkSelect 1357 */ 1358 #define generic_refClkSelect_clk_25MHz 0 1359 #define generic_refClkSelect_clk_100MHz 1 1360 #define generic_refClkSelect_clk_125MHz 2 1361 #define generic_refClkSelect_clk_156p25MHz 3 1362 #define generic_refClkSelect_clk_187p5MHz 4 1363 #define generic_refClkSelect_clk_161p25Mhz 5 1364 #define generic_refClkSelect_clk_50Mhz 6 1365 #define generic_refClkSelect_clk_106p25Mhz 7 1366 1367 /**************************************************************************** 1368 * Enums: generic_aerMMDdevTypeSelect 1369 */ 1370 #define generic_aerMMDdevTypeSelect_combo_core 0 1371 #define generic_aerMMDdevTypeSelect_PMA_PMD 1 1372 #define generic_aerMMDdevTypeSelect_PCS 3 1373 #define generic_aerMMDdevTypeSelect_PHY 4 1374 #define generic_aerMMDdevTypeSelect_DTE 5 1375 #define generic_aerMMDdevTypeSelect_CL73_AN 7 1376 1377 /**************************************************************************** 1378 * Enums: generic_aerMMDportSelect 1379 */ 1380 #define generic_aerMMDportSelect_ln0 0 1381 #define generic_aerMMDportSelect_ln1 1 1382 #define generic_aerMMDportSelect_ln2 2 1383 #define generic_aerMMDportSelect_ln3 3 1384 #define generic_aerMMDportSelect_BCST_ln0_1_2_3 511 1385 #define generic_aerMMDportSelect_BCST_ln0_1 512 1386 #define generic_aerMMDportSelect_BCST_ln2_3 513 1387 1388 /**************************************************************************** 1389 * Enums: generic_firmwareModeSelect 1390 */ 1391 #define generic_firmwareModeSelect_DEFAULT 0 1392 #define generic_firmwareModeSelect_SFP_OPT_LR 1 1393 #define generic_firmwareModeSelect_SFP_DAC 2 1394 #define generic_firmwareModeSelect_XLAUI 3 1395 #define generic_firmwareModeSelect_LONG_CH_6G 4 1396 1397 /**************************************************************************** 1398 * Enums: generic_tempIdxSelect 1399 */ 1400 #define generic_tempIdxSelect_LTE__22p9C 15 1401 #define generic_tempIdxSelect_LTE__12p6C 14 1402 #define generic_tempIdxSelect_LTE__3p0C 13 1403 #define generic_tempIdxSelect_LTE_6p7C 12 1404 #define generic_tempIdxSelect_LTE_16p4C 11 1405 #define generic_tempIdxSelect_LTE_26p6C 10 1406 #define generic_tempIdxSelect_LTE_36p3C 9 1407 #define generic_tempIdxSelect_LTE_46p0C 8 1408 #define generic_tempIdxSelect_LTE_56p2C 7 1409 #define generic_tempIdxSelect_LTE_65p9C 6 1410 #define generic_tempIdxSelect_LTE_75p6C 5 1411 #define generic_tempIdxSelect_LTE_85p3C 4 1412 #define generic_tempIdxSelect_LTE_95p5C 3 1413 #define generic_tempIdxSelect_LTE_105p2C 2 1414 #define generic_tempIdxSelect_LTE_114p9C 1 1415 #define generic_tempIdxSelect_LTE_125p1C 0 1416 1417 /**************************************************************************** 1418 * Enums: main0_cl36TxEEEStates_l 1419 */ 1420 #define main0_cl36TxEEEStates_l_TX_REFRESH 8 1421 #define main0_cl36TxEEEStates_l_TX_QUIET 4 1422 #define main0_cl36TxEEEStates_l_TX_SLEEP 2 1423 #define main0_cl36TxEEEStates_l_TX_ACTIVE 1 1424 1425 /**************************************************************************** 1426 * Enums: main0_cl36TxEEEStates_c 1427 */ 1428 #define main0_cl36TxEEEStates_c_TX_REFRESH 3 1429 #define main0_cl36TxEEEStates_c_TX_QUIET 2 1430 #define main0_cl36TxEEEStates_c_TX_SLEEP 1 1431 #define main0_cl36TxEEEStates_c_TX_ACTIVE 0 1432 1433 /**************************************************************************** 1434 * Enums: main0_cl49TxEEEStates_l 1435 */ 1436 #define main0_cl49TxEEEStates_l_SCR_RESET_2 64 1437 #define main0_cl49TxEEEStates_l_SCR_RESET_1 32 1438 #define main0_cl49TxEEEStates_l_TX_WAKE 16 1439 #define main0_cl49TxEEEStates_l_TX_REFRESH 8 1440 #define main0_cl49TxEEEStates_l_TX_QUIET 4 1441 #define main0_cl49TxEEEStates_l_TX_SLEEP 2 1442 #define main0_cl49TxEEEStates_l_TX_ACTIVE 1 1443 1444 /**************************************************************************** 1445 * Enums: main0_cl49TxEEEStates_c 1446 */ 1447 #define main0_cl49TxEEEStates_c_SCR_RESET_2 6 1448 #define main0_cl49TxEEEStates_c_SCR_RESET_1 5 1449 #define main0_cl49TxEEEStates_c_TX_WAKE 4 1450 #define main0_cl49TxEEEStates_c_TX_REFRESH 3 1451 #define main0_cl49TxEEEStates_c_TX_QUIET 2 1452 #define main0_cl49TxEEEStates_c_TX_SLEEP 1 1453 #define main0_cl49TxEEEStates_c_TX_ACTIVE 0 1454 1455 /**************************************************************************** 1456 * Enums: main0_cl36RxEEEStates_l 1457 */ 1458 #define main0_cl36RxEEEStates_l_RX_LINK_FAIL 32 1459 #define main0_cl36RxEEEStates_l_RX_WTF 16 1460 #define main0_cl36RxEEEStates_l_RX_WAKE 8 1461 #define main0_cl36RxEEEStates_l_RX_QUIET 4 1462 #define main0_cl36RxEEEStates_l_RX_SLEEP 2 1463 #define main0_cl36RxEEEStates_l_RX_ACTIVE 1 1464 1465 /**************************************************************************** 1466 * Enums: main0_cl36RxEEEStates_c 1467 */ 1468 #define main0_cl36RxEEEStates_c_RX_LINK_FAIL 5 1469 #define main0_cl36RxEEEStates_c_RX_WTF 4 1470 #define main0_cl36RxEEEStates_c_RX_WAKE 3 1471 #define main0_cl36RxEEEStates_c_RX_QUIET 2 1472 #define main0_cl36RxEEEStates_c_RX_SLEEP 1 1473 #define main0_cl36RxEEEStates_c_RX_ACTIVE 0 1474 1475 /**************************************************************************** 1476 * Enums: main0_cl49RxEEEStates_l 1477 */ 1478 #define main0_cl49RxEEEStates_l_RX_LINK_FAIL 32 1479 #define main0_cl49RxEEEStates_l_RX_WTF 16 1480 #define main0_cl49RxEEEStates_l_RX_WAKE 8 1481 #define main0_cl49RxEEEStates_l_RX_QUIET 4 1482 #define main0_cl49RxEEEStates_l_RX_SLEEP 2 1483 #define main0_cl49RxEEEStates_l_RX_ACTIVE 1 1484 1485 /**************************************************************************** 1486 * Enums: main0_cl49RxEEEStates_c 1487 */ 1488 #define main0_cl49RxEEEStates_c_RX_LINK_FAIL 5 1489 #define main0_cl49RxEEEStates_c_RX_WTF 4 1490 #define main0_cl49RxEEEStates_c_RX_WAKE 3 1491 #define main0_cl49RxEEEStates_c_RX_QUIET 2 1492 #define main0_cl49RxEEEStates_c_RX_SLEEP 1 1493 #define main0_cl49RxEEEStates_c_RX_ACTIVE 0 1494 1495 /**************************************************************************** 1496 * Enums: main0_cl48TxEEEStates_l 1497 */ 1498 #define main0_cl48TxEEEStates_l_TX_REFRESH 8 1499 #define main0_cl48TxEEEStates_l_TX_QUIET 4 1500 #define main0_cl48TxEEEStates_l_TX_SLEEP 2 1501 #define main0_cl48TxEEEStates_l_TX_ACTIVE 1 1502 1503 /**************************************************************************** 1504 * Enums: main0_cl48TxEEEStates_c 1505 */ 1506 #define main0_cl48TxEEEStates_c_TX_REFRESH 3 1507 #define main0_cl48TxEEEStates_c_TX_QUIET 2 1508 #define main0_cl48TxEEEStates_c_TX_SLEEP 1 1509 #define main0_cl48TxEEEStates_c_TX_ACTIVE 0 1510 1511 /**************************************************************************** 1512 * Enums: main0_cl48RxEEEStates_l 1513 */ 1514 #define main0_cl48RxEEEStates_l_RX_LINK_FAIL 32 1515 #define main0_cl48RxEEEStates_l_RX_WAKE 16 1516 #define main0_cl48RxEEEStates_l_RX_QUIET 8 1517 #define main0_cl48RxEEEStates_l_RX_DEACT 4 1518 #define main0_cl48RxEEEStates_l_RX_SLEEP 2 1519 #define main0_cl48RxEEEStates_l_RX_ACTIVE 1 1520 1521 /**************************************************************************** 1522 * Enums: main0_cl48RxEEEStates_c 1523 */ 1524 #define main0_cl48RxEEEStates_c_RX_LINK_FAIL 5 1525 #define main0_cl48RxEEEStates_c_RX_WAKE 4 1526 #define main0_cl48RxEEEStates_c_RX_QUIET 3 1527 #define main0_cl48RxEEEStates_c_RX_DEACT 2 1528 #define main0_cl48RxEEEStates_c_RX_SLEEP 1 1529 #define main0_cl48RxEEEStates_c_RX_ACTIVE 0 1530 1531 /**************************************************************************** 1532 * Enums: main0_IQP_Options 1533 */ 1534 #define main0_IQP_Options_i50uA 0 1535 #define main0_IQP_Options_i100uA 1 1536 #define main0_IQP_Options_i150uA 2 1537 #define main0_IQP_Options_i200uA 3 1538 #define main0_IQP_Options_i250uA 4 1539 #define main0_IQP_Options_i300uA 5 1540 #define main0_IQP_Options_i350uA 6 1541 #define main0_IQP_Options_i400uA 7 1542 #define main0_IQP_Options_i450uA 8 1543 #define main0_IQP_Options_i500uA 9 1544 #define main0_IQP_Options_i550uA 10 1545 #define main0_IQP_Options_i600uA 11 1546 #define main0_IQP_Options_i650uA 12 1547 #define main0_IQP_Options_i700uA 13 1548 #define main0_IQP_Options_i750uA 14 1549 #define main0_IQP_Options_i800uA 15 1550 1551 /**************************************************************************** 1552 * Enums: main0_IDriver_Options 1553 */ 1554 #define main0_IDriver_Options_v680mV 0 1555 #define main0_IDriver_Options_v730mV 1 1556 #define main0_IDriver_Options_v780mV 2 1557 #define main0_IDriver_Options_v830mV 3 1558 #define main0_IDriver_Options_v880mV 4 1559 #define main0_IDriver_Options_v930mV 5 1560 #define main0_IDriver_Options_v980mV 6 1561 #define main0_IDriver_Options_v1010mV 7 1562 #define main0_IDriver_Options_v1040mV 8 1563 #define main0_IDriver_Options_v1060mV 9 1564 #define main0_IDriver_Options_v1070mV 10 1565 #define main0_IDriver_Options_v1080mV 11 1566 #define main0_IDriver_Options_v1085mV 12 1567 #define main0_IDriver_Options_v1090mV 13 1568 #define main0_IDriver_Options_v1095mV 14 1569 #define main0_IDriver_Options_v1100mV 15 1570 1571 /**************************************************************************** 1572 * Enums: main0_operationModes 1573 */ 1574 #define main0_operationModes_XGXS 0 1575 #define main0_operationModes_XGXG_nCC 1 1576 #define main0_operationModes_Indlane_OS8 4 1577 #define main0_operationModes_IndLane_OS5 5 1578 #define main0_operationModes_PCI 7 1579 #define main0_operationModes_XGXS_nLQ 8 1580 #define main0_operationModes_XGXS_nLQnCC 9 1581 #define main0_operationModes_PBypass 10 1582 #define main0_operationModes_PBypass_nDSK 11 1583 #define main0_operationModes_ComboCoreMode 12 1584 #define main0_operationModes_Clocks_off 15 1585 1586 /**************************************************************************** 1587 * Enums: main0_synce_enum 1588 */ 1589 #define main0_synce_enum_SYNCE_NO_DIV 0 1590 #define main0_synce_enum_SYNCE_DIV_7 1 1591 #define main0_synce_enum_SYNCE_DIV_11 2 1592 #define main0_synce_enum_SYNCE_DIV_10 3 1593 1594 /**************************************************************************** 1595 * Enums: main0_synce_enum_stage0 1596 */ 1597 #define main0_synce_enum_stage0_SYNCE_NO_DIV 0 1598 #define main0_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 1599 #define main0_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 1600 1601 /**************************************************************************** 1602 * Enums: main0_operationSpeeds 1603 */ 1604 #define main0_operationSpeeds_SPEED_10G_X4_10p3125 59 1605 #define main0_operationSpeeds_SPEED_10G_CX4_10p3125 58 1606 #define main0_operationSpeeds_SPEED_10G_KX4_10p3125 57 1607 #define main0_operationSpeeds_SPEED_2p5G_X1_10p3125 56 1608 #define main0_operationSpeeds_SPEED_1000M_10p3125 55 1609 #define main0_operationSpeeds_SPEED_100M_10p3125 54 1610 #define main0_operationSpeeds_SPEED_10M_10p3125 53 1611 #define main0_operationSpeeds_SPEED_10p5G_X4 50 1612 #define main0_operationSpeeds_SPEED_5G_KR1 49 1613 #define main0_operationSpeeds_SPEED_42p42G_X4 44 1614 #define main0_operationSpeeds_SPEED_21p21G_X2 43 1615 #define main0_operationSpeeds_SPEED_48p48G_X4 42 1616 #define main0_operationSpeeds_SPEED_24p24G_X2 41 1617 #define main0_operationSpeeds_SPEED_12p12G_X1 40 1618 #define main0_operationSpeeds_SPEED_127G_X12 39 1619 #define main0_operationSpeeds_SPEED_120G_X12 38 1620 #define main0_operationSpeeds_SPEED_107G_X10 37 1621 #define main0_operationSpeeds_SPEED_100G_CR10 36 1622 #define main0_operationSpeeds_SPEED_42G_X4 35 1623 #define main0_operationSpeeds_SPEED_40G_CR4 34 1624 #define main0_operationSpeeds_SPEED_40G_KR4 33 1625 #define main0_operationSpeeds_SPEED_21G_X2 32 1626 #define main0_operationSpeeds_SPEED_20G_CR2 31 1627 #define main0_operationSpeeds_SPEED_20G_KR2 30 1628 #define main0_operationSpeeds_SPEED_10p6_X1 29 1629 #define main0_operationSpeeds_SPEED_10G_KR1 28 1630 #define main0_operationSpeeds_SPEED_40G_X4 27 1631 #define main0_operationSpeeds_SPEED_20G_X2 26 1632 #define main0_operationSpeeds_SPEED_20G_CX2 25 1633 #define main0_operationSpeeds_SPEED_31p5G_KR4 24 1634 #define main0_operationSpeeds_SPEED_31p5G_X4 23 1635 #define main0_operationSpeeds_SPEED_15p75G_X2 22 1636 #define main0_operationSpeeds_SPEED_25p45G_X4 21 1637 #define main0_operationSpeeds_SPEED_12p7G_X2 20 1638 #define main0_operationSpeeds_SPEED_21G_X4 19 1639 #define main0_operationSpeeds_SPEED_10p5G_X2 18 1640 #define main0_operationSpeeds_SPEED_20G_X4 17 1641 #define main0_operationSpeeds_SPEED_10G_X2 16 1642 #define main0_operationSpeeds_SPEED_10G_CX2 15 1643 #define main0_operationSpeeds_SPEED_20G_CX4 14 1644 #define main0_operationSpeeds_SPEED_16G_X4 13 1645 #define main0_operationSpeeds_SPEED_15G_X4 12 1646 #define main0_operationSpeeds_SPEED_13G_X4 11 1647 #define main0_operationSpeeds_SPEED_10G_X4 10 1648 #define main0_operationSpeeds_SPEED_10G_KX4 9 1649 #define main0_operationSpeeds_SPEED_10G_CX4 8 1650 #define main0_operationSpeeds_SPEED_5G_X1 7 1651 #define main0_operationSpeeds_SPEED_2p5G_X1 6 1652 #define main0_operationSpeeds_SPEED_1G_KX1 5 1653 #define main0_operationSpeeds_SPEED_1G_CX1 4 1654 #define main0_operationSpeeds_SPEED_1000M 3 1655 #define main0_operationSpeeds_SPEED_100M 2 1656 #define main0_operationSpeeds_SPEED_10M 1 1657 1658 /**************************************************************************** 1659 * Enums: main0_actualSpeeds 1660 */ 1661 #define main0_actualSpeeds_dr_10M 0 1662 #define main0_actualSpeeds_dr_100M 1 1663 #define main0_actualSpeeds_dr_1G 2 1664 #define main0_actualSpeeds_dr_2p5G 3 1665 #define main0_actualSpeeds_dr_5G_X4 4 1666 #define main0_actualSpeeds_dr_6G_X4 5 1667 #define main0_actualSpeeds_dr_10G_HiG 6 1668 #define main0_actualSpeeds_dr_10G_CX4 7 1669 #define main0_actualSpeeds_dr_12G_HiG 8 1670 #define main0_actualSpeeds_dr_12p5G_X4 9 1671 #define main0_actualSpeeds_dr_13G_X4 10 1672 #define main0_actualSpeeds_dr_15G_X4 11 1673 #define main0_actualSpeeds_dr_16G_X4 12 1674 #define main0_actualSpeeds_dr_1G_KX 13 1675 #define main0_actualSpeeds_dr_10G_KX4 14 1676 #define main0_actualSpeeds_dr_10G_KR 15 1677 #define main0_actualSpeeds_dr_5G 16 1678 #define main0_actualSpeeds_dr_6p4G 17 1679 #define main0_actualSpeeds_dr_20G_X4 18 1680 #define main0_actualSpeeds_dr_21G_X4 19 1681 #define main0_actualSpeeds_dr_25G_X4 20 1682 #define main0_actualSpeeds_dr_10G_HiG_DXGXS 21 1683 #define main0_actualSpeeds_dr_10G_DXGXS 22 1684 #define main0_actualSpeeds_dr_10p5G_HiG_DXGXS 23 1685 #define main0_actualSpeeds_dr_10p5G_DXGXS 24 1686 #define main0_actualSpeeds_dr_12p773G_HiG_DXGXS 25 1687 #define main0_actualSpeeds_dr_12p773G_DXGXS 26 1688 #define main0_actualSpeeds_dr_10G_XFI 27 1689 #define main0_actualSpeeds_dr_40G 28 1690 #define main0_actualSpeeds_dr_20G_HiG_DXGXS 29 1691 #define main0_actualSpeeds_dr_20G_DXGXS 30 1692 #define main0_actualSpeeds_dr_10G_SFI 31 1693 #define main0_actualSpeeds_dr_31p5G 32 1694 #define main0_actualSpeeds_dr_32p7G 33 1695 #define main0_actualSpeeds_dr_20G_SCR 34 1696 #define main0_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 1697 #define main0_actualSpeeds_dr_10G_DXGXS_SCR 36 1698 #define main0_actualSpeeds_dr_12G_R2 37 1699 #define main0_actualSpeeds_dr_10G_X2 38 1700 #define main0_actualSpeeds_dr_40G_KR4 39 1701 #define main0_actualSpeeds_dr_40G_CR4 40 1702 #define main0_actualSpeeds_dr_100G_CR10 41 1703 #define main0_actualSpeeds_dr_15p75G_DXGXS 44 1704 #define main0_actualSpeeds_dr_20G_KR2 57 1705 #define main0_actualSpeeds_dr_20G_CR2 58 1706 1707 /**************************************************************************** 1708 * Enums: main0_actualSpeedsMisc1 1709 */ 1710 #define main0_actualSpeedsMisc1_dr_2500BRCM_X1 16 1711 #define main0_actualSpeedsMisc1_dr_5000BRCM_X4 17 1712 #define main0_actualSpeedsMisc1_dr_6000BRCM_X4 18 1713 #define main0_actualSpeedsMisc1_dr_10GHiGig_X4 19 1714 #define main0_actualSpeedsMisc1_dr_10GBASE_CX4 20 1715 #define main0_actualSpeedsMisc1_dr_12GHiGig_X4 21 1716 #define main0_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 1717 #define main0_actualSpeedsMisc1_dr_13GHiGig_X4 23 1718 #define main0_actualSpeedsMisc1_dr_15GHiGig_X4 24 1719 #define main0_actualSpeedsMisc1_dr_16GHiGig_X4 25 1720 #define main0_actualSpeedsMisc1_dr_5000BRCM_X1 26 1721 #define main0_actualSpeedsMisc1_dr_6363BRCM_X1 27 1722 #define main0_actualSpeedsMisc1_dr_20GHiGig_X4 28 1723 #define main0_actualSpeedsMisc1_dr_21GHiGig_X4 29 1724 #define main0_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 1725 #define main0_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 1726 1727 /**************************************************************************** 1728 * Enums: main0_IndLaneModes 1729 */ 1730 #define main0_IndLaneModes_SWSDR_div2 0 1731 #define main0_IndLaneModes_SWSDR_div1 1 1732 #define main0_IndLaneModes_DWSDR_div2 2 1733 #define main0_IndLaneModes_DWSDR_div1 3 1734 1735 /**************************************************************************** 1736 * Enums: main0_prbsSelect 1737 */ 1738 #define main0_prbsSelect_prbs7 0 1739 #define main0_prbsSelect_prbs15 1 1740 #define main0_prbsSelect_prbs23 2 1741 #define main0_prbsSelect_prbs31 3 1742 1743 /**************************************************************************** 1744 * Enums: main0_vcoDivider 1745 */ 1746 #define main0_vcoDivider_div32 0 1747 #define main0_vcoDivider_div36 1 1748 #define main0_vcoDivider_div40 2 1749 #define main0_vcoDivider_div42 3 1750 #define main0_vcoDivider_div48 4 1751 #define main0_vcoDivider_div50 5 1752 #define main0_vcoDivider_div52 6 1753 #define main0_vcoDivider_div54 7 1754 #define main0_vcoDivider_div60 8 1755 #define main0_vcoDivider_div64 9 1756 #define main0_vcoDivider_div66 10 1757 #define main0_vcoDivider_div68 11 1758 #define main0_vcoDivider_div70 12 1759 #define main0_vcoDivider_div80 13 1760 #define main0_vcoDivider_div92 14 1761 #define main0_vcoDivider_div100 15 1762 1763 /**************************************************************************** 1764 * Enums: main0_refClkSelect 1765 */ 1766 #define main0_refClkSelect_clk_25MHz 0 1767 #define main0_refClkSelect_clk_100MHz 1 1768 #define main0_refClkSelect_clk_125MHz 2 1769 #define main0_refClkSelect_clk_156p25MHz 3 1770 #define main0_refClkSelect_clk_187p5MHz 4 1771 #define main0_refClkSelect_clk_161p25Mhz 5 1772 #define main0_refClkSelect_clk_50Mhz 6 1773 #define main0_refClkSelect_clk_106p25Mhz 7 1774 1775 /**************************************************************************** 1776 * Enums: main0_aerMMDdevTypeSelect 1777 */ 1778 #define main0_aerMMDdevTypeSelect_combo_core 0 1779 #define main0_aerMMDdevTypeSelect_PMA_PMD 1 1780 #define main0_aerMMDdevTypeSelect_PCS 3 1781 #define main0_aerMMDdevTypeSelect_PHY 4 1782 #define main0_aerMMDdevTypeSelect_DTE 5 1783 #define main0_aerMMDdevTypeSelect_CL73_AN 7 1784 1785 /**************************************************************************** 1786 * Enums: main0_aerMMDportSelect 1787 */ 1788 #define main0_aerMMDportSelect_ln0 0 1789 #define main0_aerMMDportSelect_ln1 1 1790 #define main0_aerMMDportSelect_ln2 2 1791 #define main0_aerMMDportSelect_ln3 3 1792 #define main0_aerMMDportSelect_BCST_ln0_1_2_3 511 1793 #define main0_aerMMDportSelect_BCST_ln0_1 512 1794 #define main0_aerMMDportSelect_BCST_ln2_3 513 1795 1796 /**************************************************************************** 1797 * Enums: main0_firmwareModeSelect 1798 */ 1799 #define main0_firmwareModeSelect_DEFAULT 0 1800 #define main0_firmwareModeSelect_SFP_OPT_LR 1 1801 #define main0_firmwareModeSelect_SFP_DAC 2 1802 #define main0_firmwareModeSelect_XLAUI 3 1803 #define main0_firmwareModeSelect_LONG_CH_6G 4 1804 1805 /**************************************************************************** 1806 * Enums: main0_tempIdxSelect 1807 */ 1808 #define main0_tempIdxSelect_LTE__22p9C 15 1809 #define main0_tempIdxSelect_LTE__12p6C 14 1810 #define main0_tempIdxSelect_LTE__3p0C 13 1811 #define main0_tempIdxSelect_LTE_6p7C 12 1812 #define main0_tempIdxSelect_LTE_16p4C 11 1813 #define main0_tempIdxSelect_LTE_26p6C 10 1814 #define main0_tempIdxSelect_LTE_36p3C 9 1815 #define main0_tempIdxSelect_LTE_46p0C 8 1816 #define main0_tempIdxSelect_LTE_56p2C 7 1817 #define main0_tempIdxSelect_LTE_65p9C 6 1818 #define main0_tempIdxSelect_LTE_75p6C 5 1819 #define main0_tempIdxSelect_LTE_85p3C 4 1820 #define main0_tempIdxSelect_LTE_95p5C 3 1821 #define main0_tempIdxSelect_LTE_105p2C 2 1822 #define main0_tempIdxSelect_LTE_114p9C 1 1823 #define main0_tempIdxSelect_LTE_125p1C 0 1824 1825 /**************************************************************************** 1826 * Enums: misc_cl36TxEEEStates_l 1827 */ 1828 #define misc_cl36TxEEEStates_l_TX_REFRESH 8 1829 #define misc_cl36TxEEEStates_l_TX_QUIET 4 1830 #define misc_cl36TxEEEStates_l_TX_SLEEP 2 1831 #define misc_cl36TxEEEStates_l_TX_ACTIVE 1 1832 1833 /**************************************************************************** 1834 * Enums: misc_cl36TxEEEStates_c 1835 */ 1836 #define misc_cl36TxEEEStates_c_TX_REFRESH 3 1837 #define misc_cl36TxEEEStates_c_TX_QUIET 2 1838 #define misc_cl36TxEEEStates_c_TX_SLEEP 1 1839 #define misc_cl36TxEEEStates_c_TX_ACTIVE 0 1840 1841 /**************************************************************************** 1842 * Enums: misc_cl49TxEEEStates_l 1843 */ 1844 #define misc_cl49TxEEEStates_l_SCR_RESET_2 64 1845 #define misc_cl49TxEEEStates_l_SCR_RESET_1 32 1846 #define misc_cl49TxEEEStates_l_TX_WAKE 16 1847 #define misc_cl49TxEEEStates_l_TX_REFRESH 8 1848 #define misc_cl49TxEEEStates_l_TX_QUIET 4 1849 #define misc_cl49TxEEEStates_l_TX_SLEEP 2 1850 #define misc_cl49TxEEEStates_l_TX_ACTIVE 1 1851 1852 /**************************************************************************** 1853 * Enums: misc_cl49TxEEEStates_c 1854 */ 1855 #define misc_cl49TxEEEStates_c_SCR_RESET_2 6 1856 #define misc_cl49TxEEEStates_c_SCR_RESET_1 5 1857 #define misc_cl49TxEEEStates_c_TX_WAKE 4 1858 #define misc_cl49TxEEEStates_c_TX_REFRESH 3 1859 #define misc_cl49TxEEEStates_c_TX_QUIET 2 1860 #define misc_cl49TxEEEStates_c_TX_SLEEP 1 1861 #define misc_cl49TxEEEStates_c_TX_ACTIVE 0 1862 1863 /**************************************************************************** 1864 * Enums: misc_cl36RxEEEStates_l 1865 */ 1866 #define misc_cl36RxEEEStates_l_RX_LINK_FAIL 32 1867 #define misc_cl36RxEEEStates_l_RX_WTF 16 1868 #define misc_cl36RxEEEStates_l_RX_WAKE 8 1869 #define misc_cl36RxEEEStates_l_RX_QUIET 4 1870 #define misc_cl36RxEEEStates_l_RX_SLEEP 2 1871 #define misc_cl36RxEEEStates_l_RX_ACTIVE 1 1872 1873 /**************************************************************************** 1874 * Enums: misc_cl36RxEEEStates_c 1875 */ 1876 #define misc_cl36RxEEEStates_c_RX_LINK_FAIL 5 1877 #define misc_cl36RxEEEStates_c_RX_WTF 4 1878 #define misc_cl36RxEEEStates_c_RX_WAKE 3 1879 #define misc_cl36RxEEEStates_c_RX_QUIET 2 1880 #define misc_cl36RxEEEStates_c_RX_SLEEP 1 1881 #define misc_cl36RxEEEStates_c_RX_ACTIVE 0 1882 1883 /**************************************************************************** 1884 * Enums: misc_cl49RxEEEStates_l 1885 */ 1886 #define misc_cl49RxEEEStates_l_RX_LINK_FAIL 32 1887 #define misc_cl49RxEEEStates_l_RX_WTF 16 1888 #define misc_cl49RxEEEStates_l_RX_WAKE 8 1889 #define misc_cl49RxEEEStates_l_RX_QUIET 4 1890 #define misc_cl49RxEEEStates_l_RX_SLEEP 2 1891 #define misc_cl49RxEEEStates_l_RX_ACTIVE 1 1892 1893 /**************************************************************************** 1894 * Enums: misc_cl49RxEEEStates_c 1895 */ 1896 #define misc_cl49RxEEEStates_c_RX_LINK_FAIL 5 1897 #define misc_cl49RxEEEStates_c_RX_WTF 4 1898 #define misc_cl49RxEEEStates_c_RX_WAKE 3 1899 #define misc_cl49RxEEEStates_c_RX_QUIET 2 1900 #define misc_cl49RxEEEStates_c_RX_SLEEP 1 1901 #define misc_cl49RxEEEStates_c_RX_ACTIVE 0 1902 1903 /**************************************************************************** 1904 * Enums: misc_cl48TxEEEStates_l 1905 */ 1906 #define misc_cl48TxEEEStates_l_TX_REFRESH 8 1907 #define misc_cl48TxEEEStates_l_TX_QUIET 4 1908 #define misc_cl48TxEEEStates_l_TX_SLEEP 2 1909 #define misc_cl48TxEEEStates_l_TX_ACTIVE 1 1910 1911 /**************************************************************************** 1912 * Enums: misc_cl48TxEEEStates_c 1913 */ 1914 #define misc_cl48TxEEEStates_c_TX_REFRESH 3 1915 #define misc_cl48TxEEEStates_c_TX_QUIET 2 1916 #define misc_cl48TxEEEStates_c_TX_SLEEP 1 1917 #define misc_cl48TxEEEStates_c_TX_ACTIVE 0 1918 1919 /**************************************************************************** 1920 * Enums: misc_cl48RxEEEStates_l 1921 */ 1922 #define misc_cl48RxEEEStates_l_RX_LINK_FAIL 32 1923 #define misc_cl48RxEEEStates_l_RX_WAKE 16 1924 #define misc_cl48RxEEEStates_l_RX_QUIET 8 1925 #define misc_cl48RxEEEStates_l_RX_DEACT 4 1926 #define misc_cl48RxEEEStates_l_RX_SLEEP 2 1927 #define misc_cl48RxEEEStates_l_RX_ACTIVE 1 1928 1929 /**************************************************************************** 1930 * Enums: misc_cl48RxEEEStates_c 1931 */ 1932 #define misc_cl48RxEEEStates_c_RX_LINK_FAIL 5 1933 #define misc_cl48RxEEEStates_c_RX_WAKE 4 1934 #define misc_cl48RxEEEStates_c_RX_QUIET 3 1935 #define misc_cl48RxEEEStates_c_RX_DEACT 2 1936 #define misc_cl48RxEEEStates_c_RX_SLEEP 1 1937 #define misc_cl48RxEEEStates_c_RX_ACTIVE 0 1938 1939 /**************************************************************************** 1940 * Enums: misc_IQP_Options 1941 */ 1942 #define misc_IQP_Options_i50uA 0 1943 #define misc_IQP_Options_i100uA 1 1944 #define misc_IQP_Options_i150uA 2 1945 #define misc_IQP_Options_i200uA 3 1946 #define misc_IQP_Options_i250uA 4 1947 #define misc_IQP_Options_i300uA 5 1948 #define misc_IQP_Options_i350uA 6 1949 #define misc_IQP_Options_i400uA 7 1950 #define misc_IQP_Options_i450uA 8 1951 #define misc_IQP_Options_i500uA 9 1952 #define misc_IQP_Options_i550uA 10 1953 #define misc_IQP_Options_i600uA 11 1954 #define misc_IQP_Options_i650uA 12 1955 #define misc_IQP_Options_i700uA 13 1956 #define misc_IQP_Options_i750uA 14 1957 #define misc_IQP_Options_i800uA 15 1958 1959 /**************************************************************************** 1960 * Enums: misc_IDriver_Options 1961 */ 1962 #define misc_IDriver_Options_v680mV 0 1963 #define misc_IDriver_Options_v730mV 1 1964 #define misc_IDriver_Options_v780mV 2 1965 #define misc_IDriver_Options_v830mV 3 1966 #define misc_IDriver_Options_v880mV 4 1967 #define misc_IDriver_Options_v930mV 5 1968 #define misc_IDriver_Options_v980mV 6 1969 #define misc_IDriver_Options_v1010mV 7 1970 #define misc_IDriver_Options_v1040mV 8 1971 #define misc_IDriver_Options_v1060mV 9 1972 #define misc_IDriver_Options_v1070mV 10 1973 #define misc_IDriver_Options_v1080mV 11 1974 #define misc_IDriver_Options_v1085mV 12 1975 #define misc_IDriver_Options_v1090mV 13 1976 #define misc_IDriver_Options_v1095mV 14 1977 #define misc_IDriver_Options_v1100mV 15 1978 1979 /**************************************************************************** 1980 * Enums: misc_operationModes 1981 */ 1982 #define misc_operationModes_XGXS 0 1983 #define misc_operationModes_XGXG_nCC 1 1984 #define misc_operationModes_Indlane_OS8 4 1985 #define misc_operationModes_IndLane_OS5 5 1986 #define misc_operationModes_PCI 7 1987 #define misc_operationModes_XGXS_nLQ 8 1988 #define misc_operationModes_XGXS_nLQnCC 9 1989 #define misc_operationModes_PBypass 10 1990 #define misc_operationModes_PBypass_nDSK 11 1991 #define misc_operationModes_ComboCoreMode 12 1992 #define misc_operationModes_Clocks_off 15 1993 1994 /**************************************************************************** 1995 * Enums: misc_synce_enum 1996 */ 1997 #define misc_synce_enum_SYNCE_NO_DIV 0 1998 #define misc_synce_enum_SYNCE_DIV_7 1 1999 #define misc_synce_enum_SYNCE_DIV_11 2 2000 #define misc_synce_enum_SYNCE_DIV_10 3 2001 2002 /**************************************************************************** 2003 * Enums: misc_synce_enum_stage0 2004 */ 2005 #define misc_synce_enum_stage0_SYNCE_NO_DIV 0 2006 #define misc_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 2007 #define misc_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 2008 2009 /**************************************************************************** 2010 * Enums: misc_operationSpeeds 2011 */ 2012 #define misc_operationSpeeds_SPEED_10G_X4_10p3125 59 2013 #define misc_operationSpeeds_SPEED_10G_CX4_10p3125 58 2014 #define misc_operationSpeeds_SPEED_10G_KX4_10p3125 57 2015 #define misc_operationSpeeds_SPEED_2p5G_X1_10p3125 56 2016 #define misc_operationSpeeds_SPEED_1000M_10p3125 55 2017 #define misc_operationSpeeds_SPEED_100M_10p3125 54 2018 #define misc_operationSpeeds_SPEED_10M_10p3125 53 2019 #define misc_operationSpeeds_SPEED_10p5G_X4 50 2020 #define misc_operationSpeeds_SPEED_5G_KR1 49 2021 #define misc_operationSpeeds_SPEED_42p42G_X4 44 2022 #define misc_operationSpeeds_SPEED_21p21G_X2 43 2023 #define misc_operationSpeeds_SPEED_48p48G_X4 42 2024 #define misc_operationSpeeds_SPEED_24p24G_X2 41 2025 #define misc_operationSpeeds_SPEED_12p12G_X1 40 2026 #define misc_operationSpeeds_SPEED_127G_X12 39 2027 #define misc_operationSpeeds_SPEED_120G_X12 38 2028 #define misc_operationSpeeds_SPEED_107G_X10 37 2029 #define misc_operationSpeeds_SPEED_100G_CR10 36 2030 #define misc_operationSpeeds_SPEED_42G_X4 35 2031 #define misc_operationSpeeds_SPEED_40G_CR4 34 2032 #define misc_operationSpeeds_SPEED_40G_KR4 33 2033 #define misc_operationSpeeds_SPEED_21G_X2 32 2034 #define misc_operationSpeeds_SPEED_20G_CR2 31 2035 #define misc_operationSpeeds_SPEED_20G_KR2 30 2036 #define misc_operationSpeeds_SPEED_10p6_X1 29 2037 #define misc_operationSpeeds_SPEED_10G_KR1 28 2038 #define misc_operationSpeeds_SPEED_40G_X4 27 2039 #define misc_operationSpeeds_SPEED_20G_X2 26 2040 #define misc_operationSpeeds_SPEED_20G_CX2 25 2041 #define misc_operationSpeeds_SPEED_31p5G_KR4 24 2042 #define misc_operationSpeeds_SPEED_31p5G_X4 23 2043 #define misc_operationSpeeds_SPEED_15p75G_X2 22 2044 #define misc_operationSpeeds_SPEED_25p45G_X4 21 2045 #define misc_operationSpeeds_SPEED_12p7G_X2 20 2046 #define misc_operationSpeeds_SPEED_21G_X4 19 2047 #define misc_operationSpeeds_SPEED_10p5G_X2 18 2048 #define misc_operationSpeeds_SPEED_20G_X4 17 2049 #define misc_operationSpeeds_SPEED_10G_X2 16 2050 #define misc_operationSpeeds_SPEED_10G_CX2 15 2051 #define misc_operationSpeeds_SPEED_20G_CX4 14 2052 #define misc_operationSpeeds_SPEED_16G_X4 13 2053 #define misc_operationSpeeds_SPEED_15G_X4 12 2054 #define misc_operationSpeeds_SPEED_13G_X4 11 2055 #define misc_operationSpeeds_SPEED_10G_X4 10 2056 #define misc_operationSpeeds_SPEED_10G_KX4 9 2057 #define misc_operationSpeeds_SPEED_10G_CX4 8 2058 #define misc_operationSpeeds_SPEED_5G_X1 7 2059 #define misc_operationSpeeds_SPEED_2p5G_X1 6 2060 #define misc_operationSpeeds_SPEED_1G_KX1 5 2061 #define misc_operationSpeeds_SPEED_1G_CX1 4 2062 #define misc_operationSpeeds_SPEED_1000M 3 2063 #define misc_operationSpeeds_SPEED_100M 2 2064 #define misc_operationSpeeds_SPEED_10M 1 2065 2066 /**************************************************************************** 2067 * Enums: misc_actualSpeeds 2068 */ 2069 #define misc_actualSpeeds_dr_10M 0 2070 #define misc_actualSpeeds_dr_100M 1 2071 #define misc_actualSpeeds_dr_1G 2 2072 #define misc_actualSpeeds_dr_2p5G 3 2073 #define misc_actualSpeeds_dr_5G_X4 4 2074 #define misc_actualSpeeds_dr_6G_X4 5 2075 #define misc_actualSpeeds_dr_10G_HiG 6 2076 #define misc_actualSpeeds_dr_10G_CX4 7 2077 #define misc_actualSpeeds_dr_12G_HiG 8 2078 #define misc_actualSpeeds_dr_12p5G_X4 9 2079 #define misc_actualSpeeds_dr_13G_X4 10 2080 #define misc_actualSpeeds_dr_15G_X4 11 2081 #define misc_actualSpeeds_dr_16G_X4 12 2082 #define misc_actualSpeeds_dr_1G_KX 13 2083 #define misc_actualSpeeds_dr_10G_KX4 14 2084 #define misc_actualSpeeds_dr_10G_KR 15 2085 #define misc_actualSpeeds_dr_5G 16 2086 #define misc_actualSpeeds_dr_6p4G 17 2087 #define misc_actualSpeeds_dr_20G_X4 18 2088 #define misc_actualSpeeds_dr_21G_X4 19 2089 #define misc_actualSpeeds_dr_25G_X4 20 2090 #define misc_actualSpeeds_dr_10G_HiG_DXGXS 21 2091 #define misc_actualSpeeds_dr_10G_DXGXS 22 2092 #define misc_actualSpeeds_dr_10p5G_HiG_DXGXS 23 2093 #define misc_actualSpeeds_dr_10p5G_DXGXS 24 2094 #define misc_actualSpeeds_dr_12p773G_HiG_DXGXS 25 2095 #define misc_actualSpeeds_dr_12p773G_DXGXS 26 2096 #define misc_actualSpeeds_dr_10G_XFI 27 2097 #define misc_actualSpeeds_dr_40G 28 2098 #define misc_actualSpeeds_dr_20G_HiG_DXGXS 29 2099 #define misc_actualSpeeds_dr_20G_DXGXS 30 2100 #define misc_actualSpeeds_dr_10G_SFI 31 2101 #define misc_actualSpeeds_dr_31p5G 32 2102 #define misc_actualSpeeds_dr_32p7G 33 2103 #define misc_actualSpeeds_dr_20G_SCR 34 2104 #define misc_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 2105 #define misc_actualSpeeds_dr_10G_DXGXS_SCR 36 2106 #define misc_actualSpeeds_dr_12G_R2 37 2107 #define misc_actualSpeeds_dr_10G_X2 38 2108 #define misc_actualSpeeds_dr_40G_KR4 39 2109 #define misc_actualSpeeds_dr_40G_CR4 40 2110 #define misc_actualSpeeds_dr_100G_CR10 41 2111 #define misc_actualSpeeds_dr_15p75G_DXGXS 44 2112 #define misc_actualSpeeds_dr_20G_KR2 57 2113 #define misc_actualSpeeds_dr_20G_CR2 58 2114 2115 /**************************************************************************** 2116 * Enums: misc_actualSpeedsMisc1 2117 */ 2118 #define misc_actualSpeedsMisc1_dr_2500BRCM_X1 16 2119 #define misc_actualSpeedsMisc1_dr_5000BRCM_X4 17 2120 #define misc_actualSpeedsMisc1_dr_6000BRCM_X4 18 2121 #define misc_actualSpeedsMisc1_dr_10GHiGig_X4 19 2122 #define misc_actualSpeedsMisc1_dr_10GBASE_CX4 20 2123 #define misc_actualSpeedsMisc1_dr_12GHiGig_X4 21 2124 #define misc_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 2125 #define misc_actualSpeedsMisc1_dr_13GHiGig_X4 23 2126 #define misc_actualSpeedsMisc1_dr_15GHiGig_X4 24 2127 #define misc_actualSpeedsMisc1_dr_16GHiGig_X4 25 2128 #define misc_actualSpeedsMisc1_dr_5000BRCM_X1 26 2129 #define misc_actualSpeedsMisc1_dr_6363BRCM_X1 27 2130 #define misc_actualSpeedsMisc1_dr_20GHiGig_X4 28 2131 #define misc_actualSpeedsMisc1_dr_21GHiGig_X4 29 2132 #define misc_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 2133 #define misc_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 2134 2135 /**************************************************************************** 2136 * Enums: misc_IndLaneModes 2137 */ 2138 #define misc_IndLaneModes_SWSDR_div2 0 2139 #define misc_IndLaneModes_SWSDR_div1 1 2140 #define misc_IndLaneModes_DWSDR_div2 2 2141 #define misc_IndLaneModes_DWSDR_div1 3 2142 2143 /**************************************************************************** 2144 * Enums: misc_prbsSelect 2145 */ 2146 #define misc_prbsSelect_prbs7 0 2147 #define misc_prbsSelect_prbs15 1 2148 #define misc_prbsSelect_prbs23 2 2149 #define misc_prbsSelect_prbs31 3 2150 2151 /**************************************************************************** 2152 * Enums: misc_vcoDivider 2153 */ 2154 #define misc_vcoDivider_div32 0 2155 #define misc_vcoDivider_div36 1 2156 #define misc_vcoDivider_div40 2 2157 #define misc_vcoDivider_div42 3 2158 #define misc_vcoDivider_div48 4 2159 #define misc_vcoDivider_div50 5 2160 #define misc_vcoDivider_div52 6 2161 #define misc_vcoDivider_div54 7 2162 #define misc_vcoDivider_div60 8 2163 #define misc_vcoDivider_div64 9 2164 #define misc_vcoDivider_div66 10 2165 #define misc_vcoDivider_div68 11 2166 #define misc_vcoDivider_div70 12 2167 #define misc_vcoDivider_div80 13 2168 #define misc_vcoDivider_div92 14 2169 #define misc_vcoDivider_div100 15 2170 2171 /**************************************************************************** 2172 * Enums: misc_refClkSelect 2173 */ 2174 #define misc_refClkSelect_clk_25MHz 0 2175 #define misc_refClkSelect_clk_100MHz 1 2176 #define misc_refClkSelect_clk_125MHz 2 2177 #define misc_refClkSelect_clk_156p25MHz 3 2178 #define misc_refClkSelect_clk_187p5MHz 4 2179 #define misc_refClkSelect_clk_161p25Mhz 5 2180 #define misc_refClkSelect_clk_50Mhz 6 2181 #define misc_refClkSelect_clk_106p25Mhz 7 2182 2183 /**************************************************************************** 2184 * Enums: misc_aerMMDdevTypeSelect 2185 */ 2186 #define misc_aerMMDdevTypeSelect_combo_core 0 2187 #define misc_aerMMDdevTypeSelect_PMA_PMD 1 2188 #define misc_aerMMDdevTypeSelect_PCS 3 2189 #define misc_aerMMDdevTypeSelect_PHY 4 2190 #define misc_aerMMDdevTypeSelect_DTE 5 2191 #define misc_aerMMDdevTypeSelect_CL73_AN 7 2192 2193 /**************************************************************************** 2194 * Enums: misc_aerMMDportSelect 2195 */ 2196 #define misc_aerMMDportSelect_ln0 0 2197 #define misc_aerMMDportSelect_ln1 1 2198 #define misc_aerMMDportSelect_ln2 2 2199 #define misc_aerMMDportSelect_ln3 3 2200 #define misc_aerMMDportSelect_BCST_ln0_1_2_3 511 2201 #define misc_aerMMDportSelect_BCST_ln0_1 512 2202 #define misc_aerMMDportSelect_BCST_ln2_3 513 2203 2204 /**************************************************************************** 2205 * Enums: misc_firmwareModeSelect 2206 */ 2207 #define misc_firmwareModeSelect_DEFAULT 0 2208 #define misc_firmwareModeSelect_SFP_OPT_LR 1 2209 #define misc_firmwareModeSelect_SFP_DAC 2 2210 #define misc_firmwareModeSelect_XLAUI 3 2211 #define misc_firmwareModeSelect_LONG_CH_6G 4 2212 2213 /**************************************************************************** 2214 * Enums: misc_tempIdxSelect 2215 */ 2216 #define misc_tempIdxSelect_LTE__22p9C 15 2217 #define misc_tempIdxSelect_LTE__12p6C 14 2218 #define misc_tempIdxSelect_LTE__3p0C 13 2219 #define misc_tempIdxSelect_LTE_6p7C 12 2220 #define misc_tempIdxSelect_LTE_16p4C 11 2221 #define misc_tempIdxSelect_LTE_26p6C 10 2222 #define misc_tempIdxSelect_LTE_36p3C 9 2223 #define misc_tempIdxSelect_LTE_46p0C 8 2224 #define misc_tempIdxSelect_LTE_56p2C 7 2225 #define misc_tempIdxSelect_LTE_65p9C 6 2226 #define misc_tempIdxSelect_LTE_75p6C 5 2227 #define misc_tempIdxSelect_LTE_85p3C 4 2228 #define misc_tempIdxSelect_LTE_95p5C 3 2229 #define misc_tempIdxSelect_LTE_105p2C 2 2230 #define misc_tempIdxSelect_LTE_114p9C 1 2231 #define misc_tempIdxSelect_LTE_125p1C 0 2232 2233 /**************************************************************************** 2234 * Enums: sc_x1_speed_override0_cl36TxEEEStates_l 2235 */ 2236 #define sc_x1_speed_override0_cl36TxEEEStates_l_TX_REFRESH 8 2237 #define sc_x1_speed_override0_cl36TxEEEStates_l_TX_QUIET 4 2238 #define sc_x1_speed_override0_cl36TxEEEStates_l_TX_SLEEP 2 2239 #define sc_x1_speed_override0_cl36TxEEEStates_l_TX_ACTIVE 1 2240 2241 /**************************************************************************** 2242 * Enums: sc_x1_speed_override0_cl36TxEEEStates_c 2243 */ 2244 #define sc_x1_speed_override0_cl36TxEEEStates_c_TX_REFRESH 3 2245 #define sc_x1_speed_override0_cl36TxEEEStates_c_TX_QUIET 2 2246 #define sc_x1_speed_override0_cl36TxEEEStates_c_TX_SLEEP 1 2247 #define sc_x1_speed_override0_cl36TxEEEStates_c_TX_ACTIVE 0 2248 2249 /**************************************************************************** 2250 * Enums: sc_x1_speed_override0_cl49TxEEEStates_l 2251 */ 2252 #define sc_x1_speed_override0_cl49TxEEEStates_l_SCR_RESET_2 64 2253 #define sc_x1_speed_override0_cl49TxEEEStates_l_SCR_RESET_1 32 2254 #define sc_x1_speed_override0_cl49TxEEEStates_l_TX_WAKE 16 2255 #define sc_x1_speed_override0_cl49TxEEEStates_l_TX_REFRESH 8 2256 #define sc_x1_speed_override0_cl49TxEEEStates_l_TX_QUIET 4 2257 #define sc_x1_speed_override0_cl49TxEEEStates_l_TX_SLEEP 2 2258 #define sc_x1_speed_override0_cl49TxEEEStates_l_TX_ACTIVE 1 2259 2260 /**************************************************************************** 2261 * Enums: sc_x1_speed_override0_cl49TxEEEStates_c 2262 */ 2263 #define sc_x1_speed_override0_cl49TxEEEStates_c_SCR_RESET_2 6 2264 #define sc_x1_speed_override0_cl49TxEEEStates_c_SCR_RESET_1 5 2265 #define sc_x1_speed_override0_cl49TxEEEStates_c_TX_WAKE 4 2266 #define sc_x1_speed_override0_cl49TxEEEStates_c_TX_REFRESH 3 2267 #define sc_x1_speed_override0_cl49TxEEEStates_c_TX_QUIET 2 2268 #define sc_x1_speed_override0_cl49TxEEEStates_c_TX_SLEEP 1 2269 #define sc_x1_speed_override0_cl49TxEEEStates_c_TX_ACTIVE 0 2270 2271 /**************************************************************************** 2272 * Enums: sc_x1_speed_override0_cl36RxEEEStates_l 2273 */ 2274 #define sc_x1_speed_override0_cl36RxEEEStates_l_RX_LINK_FAIL 32 2275 #define sc_x1_speed_override0_cl36RxEEEStates_l_RX_WTF 16 2276 #define sc_x1_speed_override0_cl36RxEEEStates_l_RX_WAKE 8 2277 #define sc_x1_speed_override0_cl36RxEEEStates_l_RX_QUIET 4 2278 #define sc_x1_speed_override0_cl36RxEEEStates_l_RX_SLEEP 2 2279 #define sc_x1_speed_override0_cl36RxEEEStates_l_RX_ACTIVE 1 2280 2281 /**************************************************************************** 2282 * Enums: sc_x1_speed_override0_cl36RxEEEStates_c 2283 */ 2284 #define sc_x1_speed_override0_cl36RxEEEStates_c_RX_LINK_FAIL 5 2285 #define sc_x1_speed_override0_cl36RxEEEStates_c_RX_WTF 4 2286 #define sc_x1_speed_override0_cl36RxEEEStates_c_RX_WAKE 3 2287 #define sc_x1_speed_override0_cl36RxEEEStates_c_RX_QUIET 2 2288 #define sc_x1_speed_override0_cl36RxEEEStates_c_RX_SLEEP 1 2289 #define sc_x1_speed_override0_cl36RxEEEStates_c_RX_ACTIVE 0 2290 2291 /**************************************************************************** 2292 * Enums: sc_x1_speed_override0_cl49RxEEEStates_l 2293 */ 2294 #define sc_x1_speed_override0_cl49RxEEEStates_l_RX_LINK_FAIL 32 2295 #define sc_x1_speed_override0_cl49RxEEEStates_l_RX_WTF 16 2296 #define sc_x1_speed_override0_cl49RxEEEStates_l_RX_WAKE 8 2297 #define sc_x1_speed_override0_cl49RxEEEStates_l_RX_QUIET 4 2298 #define sc_x1_speed_override0_cl49RxEEEStates_l_RX_SLEEP 2 2299 #define sc_x1_speed_override0_cl49RxEEEStates_l_RX_ACTIVE 1 2300 2301 /**************************************************************************** 2302 * Enums: sc_x1_speed_override0_cl49RxEEEStates_c 2303 */ 2304 #define sc_x1_speed_override0_cl49RxEEEStates_c_RX_LINK_FAIL 5 2305 #define sc_x1_speed_override0_cl49RxEEEStates_c_RX_WTF 4 2306 #define sc_x1_speed_override0_cl49RxEEEStates_c_RX_WAKE 3 2307 #define sc_x1_speed_override0_cl49RxEEEStates_c_RX_QUIET 2 2308 #define sc_x1_speed_override0_cl49RxEEEStates_c_RX_SLEEP 1 2309 #define sc_x1_speed_override0_cl49RxEEEStates_c_RX_ACTIVE 0 2310 2311 /**************************************************************************** 2312 * Enums: sc_x1_speed_override0_cl48TxEEEStates_l 2313 */ 2314 #define sc_x1_speed_override0_cl48TxEEEStates_l_TX_REFRESH 8 2315 #define sc_x1_speed_override0_cl48TxEEEStates_l_TX_QUIET 4 2316 #define sc_x1_speed_override0_cl48TxEEEStates_l_TX_SLEEP 2 2317 #define sc_x1_speed_override0_cl48TxEEEStates_l_TX_ACTIVE 1 2318 2319 /**************************************************************************** 2320 * Enums: sc_x1_speed_override0_cl48TxEEEStates_c 2321 */ 2322 #define sc_x1_speed_override0_cl48TxEEEStates_c_TX_REFRESH 3 2323 #define sc_x1_speed_override0_cl48TxEEEStates_c_TX_QUIET 2 2324 #define sc_x1_speed_override0_cl48TxEEEStates_c_TX_SLEEP 1 2325 #define sc_x1_speed_override0_cl48TxEEEStates_c_TX_ACTIVE 0 2326 2327 /**************************************************************************** 2328 * Enums: sc_x1_speed_override0_cl48RxEEEStates_l 2329 */ 2330 #define sc_x1_speed_override0_cl48RxEEEStates_l_RX_LINK_FAIL 32 2331 #define sc_x1_speed_override0_cl48RxEEEStates_l_RX_WAKE 16 2332 #define sc_x1_speed_override0_cl48RxEEEStates_l_RX_QUIET 8 2333 #define sc_x1_speed_override0_cl48RxEEEStates_l_RX_DEACT 4 2334 #define sc_x1_speed_override0_cl48RxEEEStates_l_RX_SLEEP 2 2335 #define sc_x1_speed_override0_cl48RxEEEStates_l_RX_ACTIVE 1 2336 2337 /**************************************************************************** 2338 * Enums: sc_x1_speed_override0_cl48RxEEEStates_c 2339 */ 2340 #define sc_x1_speed_override0_cl48RxEEEStates_c_RX_LINK_FAIL 5 2341 #define sc_x1_speed_override0_cl48RxEEEStates_c_RX_WAKE 4 2342 #define sc_x1_speed_override0_cl48RxEEEStates_c_RX_QUIET 3 2343 #define sc_x1_speed_override0_cl48RxEEEStates_c_RX_DEACT 2 2344 #define sc_x1_speed_override0_cl48RxEEEStates_c_RX_SLEEP 1 2345 #define sc_x1_speed_override0_cl48RxEEEStates_c_RX_ACTIVE 0 2346 2347 /**************************************************************************** 2348 * Enums: sc_x1_speed_override0_IQP_Options 2349 */ 2350 #define sc_x1_speed_override0_IQP_Options_i50uA 0 2351 #define sc_x1_speed_override0_IQP_Options_i100uA 1 2352 #define sc_x1_speed_override0_IQP_Options_i150uA 2 2353 #define sc_x1_speed_override0_IQP_Options_i200uA 3 2354 #define sc_x1_speed_override0_IQP_Options_i250uA 4 2355 #define sc_x1_speed_override0_IQP_Options_i300uA 5 2356 #define sc_x1_speed_override0_IQP_Options_i350uA 6 2357 #define sc_x1_speed_override0_IQP_Options_i400uA 7 2358 #define sc_x1_speed_override0_IQP_Options_i450uA 8 2359 #define sc_x1_speed_override0_IQP_Options_i500uA 9 2360 #define sc_x1_speed_override0_IQP_Options_i550uA 10 2361 #define sc_x1_speed_override0_IQP_Options_i600uA 11 2362 #define sc_x1_speed_override0_IQP_Options_i650uA 12 2363 #define sc_x1_speed_override0_IQP_Options_i700uA 13 2364 #define sc_x1_speed_override0_IQP_Options_i750uA 14 2365 #define sc_x1_speed_override0_IQP_Options_i800uA 15 2366 2367 /**************************************************************************** 2368 * Enums: sc_x1_speed_override0_IDriver_Options 2369 */ 2370 #define sc_x1_speed_override0_IDriver_Options_v680mV 0 2371 #define sc_x1_speed_override0_IDriver_Options_v730mV 1 2372 #define sc_x1_speed_override0_IDriver_Options_v780mV 2 2373 #define sc_x1_speed_override0_IDriver_Options_v830mV 3 2374 #define sc_x1_speed_override0_IDriver_Options_v880mV 4 2375 #define sc_x1_speed_override0_IDriver_Options_v930mV 5 2376 #define sc_x1_speed_override0_IDriver_Options_v980mV 6 2377 #define sc_x1_speed_override0_IDriver_Options_v1010mV 7 2378 #define sc_x1_speed_override0_IDriver_Options_v1040mV 8 2379 #define sc_x1_speed_override0_IDriver_Options_v1060mV 9 2380 #define sc_x1_speed_override0_IDriver_Options_v1070mV 10 2381 #define sc_x1_speed_override0_IDriver_Options_v1080mV 11 2382 #define sc_x1_speed_override0_IDriver_Options_v1085mV 12 2383 #define sc_x1_speed_override0_IDriver_Options_v1090mV 13 2384 #define sc_x1_speed_override0_IDriver_Options_v1095mV 14 2385 #define sc_x1_speed_override0_IDriver_Options_v1100mV 15 2386 2387 /**************************************************************************** 2388 * Enums: sc_x1_speed_override0_operationModes 2389 */ 2390 #define sc_x1_speed_override0_operationModes_XGXS 0 2391 #define sc_x1_speed_override0_operationModes_XGXG_nCC 1 2392 #define sc_x1_speed_override0_operationModes_Indlane_OS8 4 2393 #define sc_x1_speed_override0_operationModes_IndLane_OS5 5 2394 #define sc_x1_speed_override0_operationModes_PCI 7 2395 #define sc_x1_speed_override0_operationModes_XGXS_nLQ 8 2396 #define sc_x1_speed_override0_operationModes_XGXS_nLQnCC 9 2397 #define sc_x1_speed_override0_operationModes_PBypass 10 2398 #define sc_x1_speed_override0_operationModes_PBypass_nDSK 11 2399 #define sc_x1_speed_override0_operationModes_ComboCoreMode 12 2400 #define sc_x1_speed_override0_operationModes_Clocks_off 15 2401 2402 /**************************************************************************** 2403 * Enums: sc_x1_speed_override0_synce_enum 2404 */ 2405 #define sc_x1_speed_override0_synce_enum_SYNCE_NO_DIV 0 2406 #define sc_x1_speed_override0_synce_enum_SYNCE_DIV_7 1 2407 #define sc_x1_speed_override0_synce_enum_SYNCE_DIV_11 2 2408 #define sc_x1_speed_override0_synce_enum_SYNCE_DIV_10 3 2409 2410 /**************************************************************************** 2411 * Enums: sc_x1_speed_override0_synce_enum_stage0 2412 */ 2413 #define sc_x1_speed_override0_synce_enum_stage0_SYNCE_NO_DIV 0 2414 #define sc_x1_speed_override0_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 2415 #define sc_x1_speed_override0_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 2416 2417 /**************************************************************************** 2418 * Enums: sc_x1_speed_override0_operationSpeeds 2419 */ 2420 #define sc_x1_speed_override0_operationSpeeds_SPEED_10G_X4_10p3125 59 2421 #define sc_x1_speed_override0_operationSpeeds_SPEED_10G_CX4_10p3125 58 2422 #define sc_x1_speed_override0_operationSpeeds_SPEED_10G_KX4_10p3125 57 2423 #define sc_x1_speed_override0_operationSpeeds_SPEED_2p5G_X1_10p3125 56 2424 #define sc_x1_speed_override0_operationSpeeds_SPEED_1000M_10p3125 55 2425 #define sc_x1_speed_override0_operationSpeeds_SPEED_100M_10p3125 54 2426 #define sc_x1_speed_override0_operationSpeeds_SPEED_10M_10p3125 53 2427 #define sc_x1_speed_override0_operationSpeeds_SPEED_10p5G_X4 50 2428 #define sc_x1_speed_override0_operationSpeeds_SPEED_5G_KR1 49 2429 #define sc_x1_speed_override0_operationSpeeds_SPEED_42p42G_X4 44 2430 #define sc_x1_speed_override0_operationSpeeds_SPEED_21p21G_X2 43 2431 #define sc_x1_speed_override0_operationSpeeds_SPEED_48p48G_X4 42 2432 #define sc_x1_speed_override0_operationSpeeds_SPEED_24p24G_X2 41 2433 #define sc_x1_speed_override0_operationSpeeds_SPEED_12p12G_X1 40 2434 #define sc_x1_speed_override0_operationSpeeds_SPEED_127G_X12 39 2435 #define sc_x1_speed_override0_operationSpeeds_SPEED_120G_X12 38 2436 #define sc_x1_speed_override0_operationSpeeds_SPEED_107G_X10 37 2437 #define sc_x1_speed_override0_operationSpeeds_SPEED_100G_CR10 36 2438 #define sc_x1_speed_override0_operationSpeeds_SPEED_42G_X4 35 2439 #define sc_x1_speed_override0_operationSpeeds_SPEED_40G_CR4 34 2440 #define sc_x1_speed_override0_operationSpeeds_SPEED_40G_KR4 33 2441 #define sc_x1_speed_override0_operationSpeeds_SPEED_21G_X2 32 2442 #define sc_x1_speed_override0_operationSpeeds_SPEED_20G_CR2 31 2443 #define sc_x1_speed_override0_operationSpeeds_SPEED_20G_KR2 30 2444 #define sc_x1_speed_override0_operationSpeeds_SPEED_10p6_X1 29 2445 #define sc_x1_speed_override0_operationSpeeds_SPEED_10G_KR1 28 2446 #define sc_x1_speed_override0_operationSpeeds_SPEED_40G_X4 27 2447 #define sc_x1_speed_override0_operationSpeeds_SPEED_20G_X2 26 2448 #define sc_x1_speed_override0_operationSpeeds_SPEED_20G_CX2 25 2449 #define sc_x1_speed_override0_operationSpeeds_SPEED_31p5G_KR4 24 2450 #define sc_x1_speed_override0_operationSpeeds_SPEED_31p5G_X4 23 2451 #define sc_x1_speed_override0_operationSpeeds_SPEED_15p75G_X2 22 2452 #define sc_x1_speed_override0_operationSpeeds_SPEED_25p45G_X4 21 2453 #define sc_x1_speed_override0_operationSpeeds_SPEED_12p7G_X2 20 2454 #define sc_x1_speed_override0_operationSpeeds_SPEED_21G_X4 19 2455 #define sc_x1_speed_override0_operationSpeeds_SPEED_10p5G_X2 18 2456 #define sc_x1_speed_override0_operationSpeeds_SPEED_20G_X4 17 2457 #define sc_x1_speed_override0_operationSpeeds_SPEED_10G_X2 16 2458 #define sc_x1_speed_override0_operationSpeeds_SPEED_10G_CX2 15 2459 #define sc_x1_speed_override0_operationSpeeds_SPEED_20G_CX4 14 2460 #define sc_x1_speed_override0_operationSpeeds_SPEED_16G_X4 13 2461 #define sc_x1_speed_override0_operationSpeeds_SPEED_15G_X4 12 2462 #define sc_x1_speed_override0_operationSpeeds_SPEED_13G_X4 11 2463 #define sc_x1_speed_override0_operationSpeeds_SPEED_10G_X4 10 2464 #define sc_x1_speed_override0_operationSpeeds_SPEED_10G_KX4 9 2465 #define sc_x1_speed_override0_operationSpeeds_SPEED_10G_CX4 8 2466 #define sc_x1_speed_override0_operationSpeeds_SPEED_5G_X1 7 2467 #define sc_x1_speed_override0_operationSpeeds_SPEED_2p5G_X1 6 2468 #define sc_x1_speed_override0_operationSpeeds_SPEED_1G_KX1 5 2469 #define sc_x1_speed_override0_operationSpeeds_SPEED_1G_CX1 4 2470 #define sc_x1_speed_override0_operationSpeeds_SPEED_1000M 3 2471 #define sc_x1_speed_override0_operationSpeeds_SPEED_100M 2 2472 #define sc_x1_speed_override0_operationSpeeds_SPEED_10M 1 2473 2474 /**************************************************************************** 2475 * Enums: sc_x1_speed_override0_actualSpeeds 2476 */ 2477 #define sc_x1_speed_override0_actualSpeeds_dr_10M 0 2478 #define sc_x1_speed_override0_actualSpeeds_dr_100M 1 2479 #define sc_x1_speed_override0_actualSpeeds_dr_1G 2 2480 #define sc_x1_speed_override0_actualSpeeds_dr_2p5G 3 2481 #define sc_x1_speed_override0_actualSpeeds_dr_5G_X4 4 2482 #define sc_x1_speed_override0_actualSpeeds_dr_6G_X4 5 2483 #define sc_x1_speed_override0_actualSpeeds_dr_10G_HiG 6 2484 #define sc_x1_speed_override0_actualSpeeds_dr_10G_CX4 7 2485 #define sc_x1_speed_override0_actualSpeeds_dr_12G_HiG 8 2486 #define sc_x1_speed_override0_actualSpeeds_dr_12p5G_X4 9 2487 #define sc_x1_speed_override0_actualSpeeds_dr_13G_X4 10 2488 #define sc_x1_speed_override0_actualSpeeds_dr_15G_X4 11 2489 #define sc_x1_speed_override0_actualSpeeds_dr_16G_X4 12 2490 #define sc_x1_speed_override0_actualSpeeds_dr_1G_KX 13 2491 #define sc_x1_speed_override0_actualSpeeds_dr_10G_KX4 14 2492 #define sc_x1_speed_override0_actualSpeeds_dr_10G_KR 15 2493 #define sc_x1_speed_override0_actualSpeeds_dr_5G 16 2494 #define sc_x1_speed_override0_actualSpeeds_dr_6p4G 17 2495 #define sc_x1_speed_override0_actualSpeeds_dr_20G_X4 18 2496 #define sc_x1_speed_override0_actualSpeeds_dr_21G_X4 19 2497 #define sc_x1_speed_override0_actualSpeeds_dr_25G_X4 20 2498 #define sc_x1_speed_override0_actualSpeeds_dr_10G_HiG_DXGXS 21 2499 #define sc_x1_speed_override0_actualSpeeds_dr_10G_DXGXS 22 2500 #define sc_x1_speed_override0_actualSpeeds_dr_10p5G_HiG_DXGXS 23 2501 #define sc_x1_speed_override0_actualSpeeds_dr_10p5G_DXGXS 24 2502 #define sc_x1_speed_override0_actualSpeeds_dr_12p773G_HiG_DXGXS 25 2503 #define sc_x1_speed_override0_actualSpeeds_dr_12p773G_DXGXS 26 2504 #define sc_x1_speed_override0_actualSpeeds_dr_10G_XFI 27 2505 #define sc_x1_speed_override0_actualSpeeds_dr_40G 28 2506 #define sc_x1_speed_override0_actualSpeeds_dr_20G_HiG_DXGXS 29 2507 #define sc_x1_speed_override0_actualSpeeds_dr_20G_DXGXS 30 2508 #define sc_x1_speed_override0_actualSpeeds_dr_10G_SFI 31 2509 #define sc_x1_speed_override0_actualSpeeds_dr_31p5G 32 2510 #define sc_x1_speed_override0_actualSpeeds_dr_32p7G 33 2511 #define sc_x1_speed_override0_actualSpeeds_dr_20G_SCR 34 2512 #define sc_x1_speed_override0_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 2513 #define sc_x1_speed_override0_actualSpeeds_dr_10G_DXGXS_SCR 36 2514 #define sc_x1_speed_override0_actualSpeeds_dr_12G_R2 37 2515 #define sc_x1_speed_override0_actualSpeeds_dr_10G_X2 38 2516 #define sc_x1_speed_override0_actualSpeeds_dr_40G_KR4 39 2517 #define sc_x1_speed_override0_actualSpeeds_dr_40G_CR4 40 2518 #define sc_x1_speed_override0_actualSpeeds_dr_100G_CR10 41 2519 #define sc_x1_speed_override0_actualSpeeds_dr_15p75G_DXGXS 44 2520 #define sc_x1_speed_override0_actualSpeeds_dr_20G_KR2 57 2521 #define sc_x1_speed_override0_actualSpeeds_dr_20G_CR2 58 2522 2523 /**************************************************************************** 2524 * Enums: sc_x1_speed_override0_actualSpeedsMisc1 2525 */ 2526 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_2500BRCM_X1 16 2527 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_5000BRCM_X4 17 2528 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_6000BRCM_X4 18 2529 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_10GHiGig_X4 19 2530 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_10GBASE_CX4 20 2531 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_12GHiGig_X4 21 2532 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 2533 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_13GHiGig_X4 23 2534 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_15GHiGig_X4 24 2535 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_16GHiGig_X4 25 2536 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_5000BRCM_X1 26 2537 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_6363BRCM_X1 27 2538 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_20GHiGig_X4 28 2539 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_21GHiGig_X4 29 2540 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 2541 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 2542 2543 /**************************************************************************** 2544 * Enums: sc_x1_speed_override0_IndLaneModes 2545 */ 2546 #define sc_x1_speed_override0_IndLaneModes_SWSDR_div2 0 2547 #define sc_x1_speed_override0_IndLaneModes_SWSDR_div1 1 2548 #define sc_x1_speed_override0_IndLaneModes_DWSDR_div2 2 2549 #define sc_x1_speed_override0_IndLaneModes_DWSDR_div1 3 2550 2551 /**************************************************************************** 2552 * Enums: sc_x1_speed_override0_prbsSelect 2553 */ 2554 #define sc_x1_speed_override0_prbsSelect_prbs7 0 2555 #define sc_x1_speed_override0_prbsSelect_prbs15 1 2556 #define sc_x1_speed_override0_prbsSelect_prbs23 2 2557 #define sc_x1_speed_override0_prbsSelect_prbs31 3 2558 2559 /**************************************************************************** 2560 * Enums: sc_x1_speed_override0_vcoDivider 2561 */ 2562 #define sc_x1_speed_override0_vcoDivider_div32 0 2563 #define sc_x1_speed_override0_vcoDivider_div36 1 2564 #define sc_x1_speed_override0_vcoDivider_div40 2 2565 #define sc_x1_speed_override0_vcoDivider_div42 3 2566 #define sc_x1_speed_override0_vcoDivider_div48 4 2567 #define sc_x1_speed_override0_vcoDivider_div50 5 2568 #define sc_x1_speed_override0_vcoDivider_div52 6 2569 #define sc_x1_speed_override0_vcoDivider_div54 7 2570 #define sc_x1_speed_override0_vcoDivider_div60 8 2571 #define sc_x1_speed_override0_vcoDivider_div64 9 2572 #define sc_x1_speed_override0_vcoDivider_div66 10 2573 #define sc_x1_speed_override0_vcoDivider_div68 11 2574 #define sc_x1_speed_override0_vcoDivider_div70 12 2575 #define sc_x1_speed_override0_vcoDivider_div80 13 2576 #define sc_x1_speed_override0_vcoDivider_div92 14 2577 #define sc_x1_speed_override0_vcoDivider_div100 15 2578 2579 /**************************************************************************** 2580 * Enums: sc_x1_speed_override0_refClkSelect 2581 */ 2582 #define sc_x1_speed_override0_refClkSelect_clk_25MHz 0 2583 #define sc_x1_speed_override0_refClkSelect_clk_100MHz 1 2584 #define sc_x1_speed_override0_refClkSelect_clk_125MHz 2 2585 #define sc_x1_speed_override0_refClkSelect_clk_156p25MHz 3 2586 #define sc_x1_speed_override0_refClkSelect_clk_187p5MHz 4 2587 #define sc_x1_speed_override0_refClkSelect_clk_161p25Mhz 5 2588 #define sc_x1_speed_override0_refClkSelect_clk_50Mhz 6 2589 #define sc_x1_speed_override0_refClkSelect_clk_106p25Mhz 7 2590 2591 /**************************************************************************** 2592 * Enums: sc_x1_speed_override0_aerMMDdevTypeSelect 2593 */ 2594 #define sc_x1_speed_override0_aerMMDdevTypeSelect_combo_core 0 2595 #define sc_x1_speed_override0_aerMMDdevTypeSelect_PMA_PMD 1 2596 #define sc_x1_speed_override0_aerMMDdevTypeSelect_PCS 3 2597 #define sc_x1_speed_override0_aerMMDdevTypeSelect_PHY 4 2598 #define sc_x1_speed_override0_aerMMDdevTypeSelect_DTE 5 2599 #define sc_x1_speed_override0_aerMMDdevTypeSelect_CL73_AN 7 2600 2601 /**************************************************************************** 2602 * Enums: sc_x1_speed_override0_aerMMDportSelect 2603 */ 2604 #define sc_x1_speed_override0_aerMMDportSelect_ln0 0 2605 #define sc_x1_speed_override0_aerMMDportSelect_ln1 1 2606 #define sc_x1_speed_override0_aerMMDportSelect_ln2 2 2607 #define sc_x1_speed_override0_aerMMDportSelect_ln3 3 2608 #define sc_x1_speed_override0_aerMMDportSelect_BCST_ln0_1_2_3 511 2609 #define sc_x1_speed_override0_aerMMDportSelect_BCST_ln0_1 512 2610 #define sc_x1_speed_override0_aerMMDportSelect_BCST_ln2_3 513 2611 2612 /**************************************************************************** 2613 * Enums: sc_x1_speed_override0_firmwareModeSelect 2614 */ 2615 #define sc_x1_speed_override0_firmwareModeSelect_DEFAULT 0 2616 #define sc_x1_speed_override0_firmwareModeSelect_SFP_OPT_LR 1 2617 #define sc_x1_speed_override0_firmwareModeSelect_SFP_DAC 2 2618 #define sc_x1_speed_override0_firmwareModeSelect_XLAUI 3 2619 #define sc_x1_speed_override0_firmwareModeSelect_LONG_CH_6G 4 2620 2621 /**************************************************************************** 2622 * Enums: sc_x1_speed_override0_tempIdxSelect 2623 */ 2624 #define sc_x1_speed_override0_tempIdxSelect_LTE__22p9C 15 2625 #define sc_x1_speed_override0_tempIdxSelect_LTE__12p6C 14 2626 #define sc_x1_speed_override0_tempIdxSelect_LTE__3p0C 13 2627 #define sc_x1_speed_override0_tempIdxSelect_LTE_6p7C 12 2628 #define sc_x1_speed_override0_tempIdxSelect_LTE_16p4C 11 2629 #define sc_x1_speed_override0_tempIdxSelect_LTE_26p6C 10 2630 #define sc_x1_speed_override0_tempIdxSelect_LTE_36p3C 9 2631 #define sc_x1_speed_override0_tempIdxSelect_LTE_46p0C 8 2632 #define sc_x1_speed_override0_tempIdxSelect_LTE_56p2C 7 2633 #define sc_x1_speed_override0_tempIdxSelect_LTE_65p9C 6 2634 #define sc_x1_speed_override0_tempIdxSelect_LTE_75p6C 5 2635 #define sc_x1_speed_override0_tempIdxSelect_LTE_85p3C 4 2636 #define sc_x1_speed_override0_tempIdxSelect_LTE_95p5C 3 2637 #define sc_x1_speed_override0_tempIdxSelect_LTE_105p2C 2 2638 #define sc_x1_speed_override0_tempIdxSelect_LTE_114p9C 1 2639 #define sc_x1_speed_override0_tempIdxSelect_LTE_125p1C 0 2640 2641 /**************************************************************************** 2642 * Enums: sc_x1_speed_override1_cl36TxEEEStates_l 2643 */ 2644 #define sc_x1_speed_override1_cl36TxEEEStates_l_TX_REFRESH 8 2645 #define sc_x1_speed_override1_cl36TxEEEStates_l_TX_QUIET 4 2646 #define sc_x1_speed_override1_cl36TxEEEStates_l_TX_SLEEP 2 2647 #define sc_x1_speed_override1_cl36TxEEEStates_l_TX_ACTIVE 1 2648 2649 /**************************************************************************** 2650 * Enums: sc_x1_speed_override1_cl36TxEEEStates_c 2651 */ 2652 #define sc_x1_speed_override1_cl36TxEEEStates_c_TX_REFRESH 3 2653 #define sc_x1_speed_override1_cl36TxEEEStates_c_TX_QUIET 2 2654 #define sc_x1_speed_override1_cl36TxEEEStates_c_TX_SLEEP 1 2655 #define sc_x1_speed_override1_cl36TxEEEStates_c_TX_ACTIVE 0 2656 2657 /**************************************************************************** 2658 * Enums: sc_x1_speed_override1_cl49TxEEEStates_l 2659 */ 2660 #define sc_x1_speed_override1_cl49TxEEEStates_l_SCR_RESET_2 64 2661 #define sc_x1_speed_override1_cl49TxEEEStates_l_SCR_RESET_1 32 2662 #define sc_x1_speed_override1_cl49TxEEEStates_l_TX_WAKE 16 2663 #define sc_x1_speed_override1_cl49TxEEEStates_l_TX_REFRESH 8 2664 #define sc_x1_speed_override1_cl49TxEEEStates_l_TX_QUIET 4 2665 #define sc_x1_speed_override1_cl49TxEEEStates_l_TX_SLEEP 2 2666 #define sc_x1_speed_override1_cl49TxEEEStates_l_TX_ACTIVE 1 2667 2668 /**************************************************************************** 2669 * Enums: sc_x1_speed_override1_cl49TxEEEStates_c 2670 */ 2671 #define sc_x1_speed_override1_cl49TxEEEStates_c_SCR_RESET_2 6 2672 #define sc_x1_speed_override1_cl49TxEEEStates_c_SCR_RESET_1 5 2673 #define sc_x1_speed_override1_cl49TxEEEStates_c_TX_WAKE 4 2674 #define sc_x1_speed_override1_cl49TxEEEStates_c_TX_REFRESH 3 2675 #define sc_x1_speed_override1_cl49TxEEEStates_c_TX_QUIET 2 2676 #define sc_x1_speed_override1_cl49TxEEEStates_c_TX_SLEEP 1 2677 #define sc_x1_speed_override1_cl49TxEEEStates_c_TX_ACTIVE 0 2678 2679 /**************************************************************************** 2680 * Enums: sc_x1_speed_override1_cl36RxEEEStates_l 2681 */ 2682 #define sc_x1_speed_override1_cl36RxEEEStates_l_RX_LINK_FAIL 32 2683 #define sc_x1_speed_override1_cl36RxEEEStates_l_RX_WTF 16 2684 #define sc_x1_speed_override1_cl36RxEEEStates_l_RX_WAKE 8 2685 #define sc_x1_speed_override1_cl36RxEEEStates_l_RX_QUIET 4 2686 #define sc_x1_speed_override1_cl36RxEEEStates_l_RX_SLEEP 2 2687 #define sc_x1_speed_override1_cl36RxEEEStates_l_RX_ACTIVE 1 2688 2689 /**************************************************************************** 2690 * Enums: sc_x1_speed_override1_cl36RxEEEStates_c 2691 */ 2692 #define sc_x1_speed_override1_cl36RxEEEStates_c_RX_LINK_FAIL 5 2693 #define sc_x1_speed_override1_cl36RxEEEStates_c_RX_WTF 4 2694 #define sc_x1_speed_override1_cl36RxEEEStates_c_RX_WAKE 3 2695 #define sc_x1_speed_override1_cl36RxEEEStates_c_RX_QUIET 2 2696 #define sc_x1_speed_override1_cl36RxEEEStates_c_RX_SLEEP 1 2697 #define sc_x1_speed_override1_cl36RxEEEStates_c_RX_ACTIVE 0 2698 2699 /**************************************************************************** 2700 * Enums: sc_x1_speed_override1_cl49RxEEEStates_l 2701 */ 2702 #define sc_x1_speed_override1_cl49RxEEEStates_l_RX_LINK_FAIL 32 2703 #define sc_x1_speed_override1_cl49RxEEEStates_l_RX_WTF 16 2704 #define sc_x1_speed_override1_cl49RxEEEStates_l_RX_WAKE 8 2705 #define sc_x1_speed_override1_cl49RxEEEStates_l_RX_QUIET 4 2706 #define sc_x1_speed_override1_cl49RxEEEStates_l_RX_SLEEP 2 2707 #define sc_x1_speed_override1_cl49RxEEEStates_l_RX_ACTIVE 1 2708 2709 /**************************************************************************** 2710 * Enums: sc_x1_speed_override1_cl49RxEEEStates_c 2711 */ 2712 #define sc_x1_speed_override1_cl49RxEEEStates_c_RX_LINK_FAIL 5 2713 #define sc_x1_speed_override1_cl49RxEEEStates_c_RX_WTF 4 2714 #define sc_x1_speed_override1_cl49RxEEEStates_c_RX_WAKE 3 2715 #define sc_x1_speed_override1_cl49RxEEEStates_c_RX_QUIET 2 2716 #define sc_x1_speed_override1_cl49RxEEEStates_c_RX_SLEEP 1 2717 #define sc_x1_speed_override1_cl49RxEEEStates_c_RX_ACTIVE 0 2718 2719 /**************************************************************************** 2720 * Enums: sc_x1_speed_override1_cl48TxEEEStates_l 2721 */ 2722 #define sc_x1_speed_override1_cl48TxEEEStates_l_TX_REFRESH 8 2723 #define sc_x1_speed_override1_cl48TxEEEStates_l_TX_QUIET 4 2724 #define sc_x1_speed_override1_cl48TxEEEStates_l_TX_SLEEP 2 2725 #define sc_x1_speed_override1_cl48TxEEEStates_l_TX_ACTIVE 1 2726 2727 /**************************************************************************** 2728 * Enums: sc_x1_speed_override1_cl48TxEEEStates_c 2729 */ 2730 #define sc_x1_speed_override1_cl48TxEEEStates_c_TX_REFRESH 3 2731 #define sc_x1_speed_override1_cl48TxEEEStates_c_TX_QUIET 2 2732 #define sc_x1_speed_override1_cl48TxEEEStates_c_TX_SLEEP 1 2733 #define sc_x1_speed_override1_cl48TxEEEStates_c_TX_ACTIVE 0 2734 2735 /**************************************************************************** 2736 * Enums: sc_x1_speed_override1_cl48RxEEEStates_l 2737 */ 2738 #define sc_x1_speed_override1_cl48RxEEEStates_l_RX_LINK_FAIL 32 2739 #define sc_x1_speed_override1_cl48RxEEEStates_l_RX_WAKE 16 2740 #define sc_x1_speed_override1_cl48RxEEEStates_l_RX_QUIET 8 2741 #define sc_x1_speed_override1_cl48RxEEEStates_l_RX_DEACT 4 2742 #define sc_x1_speed_override1_cl48RxEEEStates_l_RX_SLEEP 2 2743 #define sc_x1_speed_override1_cl48RxEEEStates_l_RX_ACTIVE 1 2744 2745 /**************************************************************************** 2746 * Enums: sc_x1_speed_override1_cl48RxEEEStates_c 2747 */ 2748 #define sc_x1_speed_override1_cl48RxEEEStates_c_RX_LINK_FAIL 5 2749 #define sc_x1_speed_override1_cl48RxEEEStates_c_RX_WAKE 4 2750 #define sc_x1_speed_override1_cl48RxEEEStates_c_RX_QUIET 3 2751 #define sc_x1_speed_override1_cl48RxEEEStates_c_RX_DEACT 2 2752 #define sc_x1_speed_override1_cl48RxEEEStates_c_RX_SLEEP 1 2753 #define sc_x1_speed_override1_cl48RxEEEStates_c_RX_ACTIVE 0 2754 2755 /**************************************************************************** 2756 * Enums: sc_x1_speed_override1_IQP_Options 2757 */ 2758 #define sc_x1_speed_override1_IQP_Options_i50uA 0 2759 #define sc_x1_speed_override1_IQP_Options_i100uA 1 2760 #define sc_x1_speed_override1_IQP_Options_i150uA 2 2761 #define sc_x1_speed_override1_IQP_Options_i200uA 3 2762 #define sc_x1_speed_override1_IQP_Options_i250uA 4 2763 #define sc_x1_speed_override1_IQP_Options_i300uA 5 2764 #define sc_x1_speed_override1_IQP_Options_i350uA 6 2765 #define sc_x1_speed_override1_IQP_Options_i400uA 7 2766 #define sc_x1_speed_override1_IQP_Options_i450uA 8 2767 #define sc_x1_speed_override1_IQP_Options_i500uA 9 2768 #define sc_x1_speed_override1_IQP_Options_i550uA 10 2769 #define sc_x1_speed_override1_IQP_Options_i600uA 11 2770 #define sc_x1_speed_override1_IQP_Options_i650uA 12 2771 #define sc_x1_speed_override1_IQP_Options_i700uA 13 2772 #define sc_x1_speed_override1_IQP_Options_i750uA 14 2773 #define sc_x1_speed_override1_IQP_Options_i800uA 15 2774 2775 /**************************************************************************** 2776 * Enums: sc_x1_speed_override1_IDriver_Options 2777 */ 2778 #define sc_x1_speed_override1_IDriver_Options_v680mV 0 2779 #define sc_x1_speed_override1_IDriver_Options_v730mV 1 2780 #define sc_x1_speed_override1_IDriver_Options_v780mV 2 2781 #define sc_x1_speed_override1_IDriver_Options_v830mV 3 2782 #define sc_x1_speed_override1_IDriver_Options_v880mV 4 2783 #define sc_x1_speed_override1_IDriver_Options_v930mV 5 2784 #define sc_x1_speed_override1_IDriver_Options_v980mV 6 2785 #define sc_x1_speed_override1_IDriver_Options_v1010mV 7 2786 #define sc_x1_speed_override1_IDriver_Options_v1040mV 8 2787 #define sc_x1_speed_override1_IDriver_Options_v1060mV 9 2788 #define sc_x1_speed_override1_IDriver_Options_v1070mV 10 2789 #define sc_x1_speed_override1_IDriver_Options_v1080mV 11 2790 #define sc_x1_speed_override1_IDriver_Options_v1085mV 12 2791 #define sc_x1_speed_override1_IDriver_Options_v1090mV 13 2792 #define sc_x1_speed_override1_IDriver_Options_v1095mV 14 2793 #define sc_x1_speed_override1_IDriver_Options_v1100mV 15 2794 2795 /**************************************************************************** 2796 * Enums: sc_x1_speed_override1_operationModes 2797 */ 2798 #define sc_x1_speed_override1_operationModes_XGXS 0 2799 #define sc_x1_speed_override1_operationModes_XGXG_nCC 1 2800 #define sc_x1_speed_override1_operationModes_Indlane_OS8 4 2801 #define sc_x1_speed_override1_operationModes_IndLane_OS5 5 2802 #define sc_x1_speed_override1_operationModes_PCI 7 2803 #define sc_x1_speed_override1_operationModes_XGXS_nLQ 8 2804 #define sc_x1_speed_override1_operationModes_XGXS_nLQnCC 9 2805 #define sc_x1_speed_override1_operationModes_PBypass 10 2806 #define sc_x1_speed_override1_operationModes_PBypass_nDSK 11 2807 #define sc_x1_speed_override1_operationModes_ComboCoreMode 12 2808 #define sc_x1_speed_override1_operationModes_Clocks_off 15 2809 2810 /**************************************************************************** 2811 * Enums: sc_x1_speed_override1_synce_enum 2812 */ 2813 #define sc_x1_speed_override1_synce_enum_SYNCE_NO_DIV 0 2814 #define sc_x1_speed_override1_synce_enum_SYNCE_DIV_7 1 2815 #define sc_x1_speed_override1_synce_enum_SYNCE_DIV_11 2 2816 #define sc_x1_speed_override1_synce_enum_SYNCE_DIV_10 3 2817 2818 /**************************************************************************** 2819 * Enums: sc_x1_speed_override1_synce_enum_stage0 2820 */ 2821 #define sc_x1_speed_override1_synce_enum_stage0_SYNCE_NO_DIV 0 2822 #define sc_x1_speed_override1_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 2823 #define sc_x1_speed_override1_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 2824 2825 /**************************************************************************** 2826 * Enums: sc_x1_speed_override1_operationSpeeds 2827 */ 2828 #define sc_x1_speed_override1_operationSpeeds_SPEED_10G_X4_10p3125 59 2829 #define sc_x1_speed_override1_operationSpeeds_SPEED_10G_CX4_10p3125 58 2830 #define sc_x1_speed_override1_operationSpeeds_SPEED_10G_KX4_10p3125 57 2831 #define sc_x1_speed_override1_operationSpeeds_SPEED_2p5G_X1_10p3125 56 2832 #define sc_x1_speed_override1_operationSpeeds_SPEED_1000M_10p3125 55 2833 #define sc_x1_speed_override1_operationSpeeds_SPEED_100M_10p3125 54 2834 #define sc_x1_speed_override1_operationSpeeds_SPEED_10M_10p3125 53 2835 #define sc_x1_speed_override1_operationSpeeds_SPEED_10p5G_X4 50 2836 #define sc_x1_speed_override1_operationSpeeds_SPEED_5G_KR1 49 2837 #define sc_x1_speed_override1_operationSpeeds_SPEED_42p42G_X4 44 2838 #define sc_x1_speed_override1_operationSpeeds_SPEED_21p21G_X2 43 2839 #define sc_x1_speed_override1_operationSpeeds_SPEED_48p48G_X4 42 2840 #define sc_x1_speed_override1_operationSpeeds_SPEED_24p24G_X2 41 2841 #define sc_x1_speed_override1_operationSpeeds_SPEED_12p12G_X1 40 2842 #define sc_x1_speed_override1_operationSpeeds_SPEED_127G_X12 39 2843 #define sc_x1_speed_override1_operationSpeeds_SPEED_120G_X12 38 2844 #define sc_x1_speed_override1_operationSpeeds_SPEED_107G_X10 37 2845 #define sc_x1_speed_override1_operationSpeeds_SPEED_100G_CR10 36 2846 #define sc_x1_speed_override1_operationSpeeds_SPEED_42G_X4 35 2847 #define sc_x1_speed_override1_operationSpeeds_SPEED_40G_CR4 34 2848 #define sc_x1_speed_override1_operationSpeeds_SPEED_40G_KR4 33 2849 #define sc_x1_speed_override1_operationSpeeds_SPEED_21G_X2 32 2850 #define sc_x1_speed_override1_operationSpeeds_SPEED_20G_CR2 31 2851 #define sc_x1_speed_override1_operationSpeeds_SPEED_20G_KR2 30 2852 #define sc_x1_speed_override1_operationSpeeds_SPEED_10p6_X1 29 2853 #define sc_x1_speed_override1_operationSpeeds_SPEED_10G_KR1 28 2854 #define sc_x1_speed_override1_operationSpeeds_SPEED_40G_X4 27 2855 #define sc_x1_speed_override1_operationSpeeds_SPEED_20G_X2 26 2856 #define sc_x1_speed_override1_operationSpeeds_SPEED_20G_CX2 25 2857 #define sc_x1_speed_override1_operationSpeeds_SPEED_31p5G_KR4 24 2858 #define sc_x1_speed_override1_operationSpeeds_SPEED_31p5G_X4 23 2859 #define sc_x1_speed_override1_operationSpeeds_SPEED_15p75G_X2 22 2860 #define sc_x1_speed_override1_operationSpeeds_SPEED_25p45G_X4 21 2861 #define sc_x1_speed_override1_operationSpeeds_SPEED_12p7G_X2 20 2862 #define sc_x1_speed_override1_operationSpeeds_SPEED_21G_X4 19 2863 #define sc_x1_speed_override1_operationSpeeds_SPEED_10p5G_X2 18 2864 #define sc_x1_speed_override1_operationSpeeds_SPEED_20G_X4 17 2865 #define sc_x1_speed_override1_operationSpeeds_SPEED_10G_X2 16 2866 #define sc_x1_speed_override1_operationSpeeds_SPEED_10G_CX2 15 2867 #define sc_x1_speed_override1_operationSpeeds_SPEED_20G_CX4 14 2868 #define sc_x1_speed_override1_operationSpeeds_SPEED_16G_X4 13 2869 #define sc_x1_speed_override1_operationSpeeds_SPEED_15G_X4 12 2870 #define sc_x1_speed_override1_operationSpeeds_SPEED_13G_X4 11 2871 #define sc_x1_speed_override1_operationSpeeds_SPEED_10G_X4 10 2872 #define sc_x1_speed_override1_operationSpeeds_SPEED_10G_KX4 9 2873 #define sc_x1_speed_override1_operationSpeeds_SPEED_10G_CX4 8 2874 #define sc_x1_speed_override1_operationSpeeds_SPEED_5G_X1 7 2875 #define sc_x1_speed_override1_operationSpeeds_SPEED_2p5G_X1 6 2876 #define sc_x1_speed_override1_operationSpeeds_SPEED_1G_KX1 5 2877 #define sc_x1_speed_override1_operationSpeeds_SPEED_1G_CX1 4 2878 #define sc_x1_speed_override1_operationSpeeds_SPEED_1000M 3 2879 #define sc_x1_speed_override1_operationSpeeds_SPEED_100M 2 2880 #define sc_x1_speed_override1_operationSpeeds_SPEED_10M 1 2881 2882 /**************************************************************************** 2883 * Enums: sc_x1_speed_override1_actualSpeeds 2884 */ 2885 #define sc_x1_speed_override1_actualSpeeds_dr_10M 0 2886 #define sc_x1_speed_override1_actualSpeeds_dr_100M 1 2887 #define sc_x1_speed_override1_actualSpeeds_dr_1G 2 2888 #define sc_x1_speed_override1_actualSpeeds_dr_2p5G 3 2889 #define sc_x1_speed_override1_actualSpeeds_dr_5G_X4 4 2890 #define sc_x1_speed_override1_actualSpeeds_dr_6G_X4 5 2891 #define sc_x1_speed_override1_actualSpeeds_dr_10G_HiG 6 2892 #define sc_x1_speed_override1_actualSpeeds_dr_10G_CX4 7 2893 #define sc_x1_speed_override1_actualSpeeds_dr_12G_HiG 8 2894 #define sc_x1_speed_override1_actualSpeeds_dr_12p5G_X4 9 2895 #define sc_x1_speed_override1_actualSpeeds_dr_13G_X4 10 2896 #define sc_x1_speed_override1_actualSpeeds_dr_15G_X4 11 2897 #define sc_x1_speed_override1_actualSpeeds_dr_16G_X4 12 2898 #define sc_x1_speed_override1_actualSpeeds_dr_1G_KX 13 2899 #define sc_x1_speed_override1_actualSpeeds_dr_10G_KX4 14 2900 #define sc_x1_speed_override1_actualSpeeds_dr_10G_KR 15 2901 #define sc_x1_speed_override1_actualSpeeds_dr_5G 16 2902 #define sc_x1_speed_override1_actualSpeeds_dr_6p4G 17 2903 #define sc_x1_speed_override1_actualSpeeds_dr_20G_X4 18 2904 #define sc_x1_speed_override1_actualSpeeds_dr_21G_X4 19 2905 #define sc_x1_speed_override1_actualSpeeds_dr_25G_X4 20 2906 #define sc_x1_speed_override1_actualSpeeds_dr_10G_HiG_DXGXS 21 2907 #define sc_x1_speed_override1_actualSpeeds_dr_10G_DXGXS 22 2908 #define sc_x1_speed_override1_actualSpeeds_dr_10p5G_HiG_DXGXS 23 2909 #define sc_x1_speed_override1_actualSpeeds_dr_10p5G_DXGXS 24 2910 #define sc_x1_speed_override1_actualSpeeds_dr_12p773G_HiG_DXGXS 25 2911 #define sc_x1_speed_override1_actualSpeeds_dr_12p773G_DXGXS 26 2912 #define sc_x1_speed_override1_actualSpeeds_dr_10G_XFI 27 2913 #define sc_x1_speed_override1_actualSpeeds_dr_40G 28 2914 #define sc_x1_speed_override1_actualSpeeds_dr_20G_HiG_DXGXS 29 2915 #define sc_x1_speed_override1_actualSpeeds_dr_20G_DXGXS 30 2916 #define sc_x1_speed_override1_actualSpeeds_dr_10G_SFI 31 2917 #define sc_x1_speed_override1_actualSpeeds_dr_31p5G 32 2918 #define sc_x1_speed_override1_actualSpeeds_dr_32p7G 33 2919 #define sc_x1_speed_override1_actualSpeeds_dr_20G_SCR 34 2920 #define sc_x1_speed_override1_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 2921 #define sc_x1_speed_override1_actualSpeeds_dr_10G_DXGXS_SCR 36 2922 #define sc_x1_speed_override1_actualSpeeds_dr_12G_R2 37 2923 #define sc_x1_speed_override1_actualSpeeds_dr_10G_X2 38 2924 #define sc_x1_speed_override1_actualSpeeds_dr_40G_KR4 39 2925 #define sc_x1_speed_override1_actualSpeeds_dr_40G_CR4 40 2926 #define sc_x1_speed_override1_actualSpeeds_dr_100G_CR10 41 2927 #define sc_x1_speed_override1_actualSpeeds_dr_15p75G_DXGXS 44 2928 #define sc_x1_speed_override1_actualSpeeds_dr_20G_KR2 57 2929 #define sc_x1_speed_override1_actualSpeeds_dr_20G_CR2 58 2930 2931 /**************************************************************************** 2932 * Enums: sc_x1_speed_override1_actualSpeedsMisc1 2933 */ 2934 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_2500BRCM_X1 16 2935 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_5000BRCM_X4 17 2936 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_6000BRCM_X4 18 2937 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_10GHiGig_X4 19 2938 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_10GBASE_CX4 20 2939 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_12GHiGig_X4 21 2940 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 2941 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_13GHiGig_X4 23 2942 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_15GHiGig_X4 24 2943 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_16GHiGig_X4 25 2944 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_5000BRCM_X1 26 2945 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_6363BRCM_X1 27 2946 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_20GHiGig_X4 28 2947 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_21GHiGig_X4 29 2948 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 2949 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 2950 2951 /**************************************************************************** 2952 * Enums: sc_x1_speed_override1_IndLaneModes 2953 */ 2954 #define sc_x1_speed_override1_IndLaneModes_SWSDR_div2 0 2955 #define sc_x1_speed_override1_IndLaneModes_SWSDR_div1 1 2956 #define sc_x1_speed_override1_IndLaneModes_DWSDR_div2 2 2957 #define sc_x1_speed_override1_IndLaneModes_DWSDR_div1 3 2958 2959 /**************************************************************************** 2960 * Enums: sc_x1_speed_override1_prbsSelect 2961 */ 2962 #define sc_x1_speed_override1_prbsSelect_prbs7 0 2963 #define sc_x1_speed_override1_prbsSelect_prbs15 1 2964 #define sc_x1_speed_override1_prbsSelect_prbs23 2 2965 #define sc_x1_speed_override1_prbsSelect_prbs31 3 2966 2967 /**************************************************************************** 2968 * Enums: sc_x1_speed_override1_vcoDivider 2969 */ 2970 #define sc_x1_speed_override1_vcoDivider_div32 0 2971 #define sc_x1_speed_override1_vcoDivider_div36 1 2972 #define sc_x1_speed_override1_vcoDivider_div40 2 2973 #define sc_x1_speed_override1_vcoDivider_div42 3 2974 #define sc_x1_speed_override1_vcoDivider_div48 4 2975 #define sc_x1_speed_override1_vcoDivider_div50 5 2976 #define sc_x1_speed_override1_vcoDivider_div52 6 2977 #define sc_x1_speed_override1_vcoDivider_div54 7 2978 #define sc_x1_speed_override1_vcoDivider_div60 8 2979 #define sc_x1_speed_override1_vcoDivider_div64 9 2980 #define sc_x1_speed_override1_vcoDivider_div66 10 2981 #define sc_x1_speed_override1_vcoDivider_div68 11 2982 #define sc_x1_speed_override1_vcoDivider_div70 12 2983 #define sc_x1_speed_override1_vcoDivider_div80 13 2984 #define sc_x1_speed_override1_vcoDivider_div92 14 2985 #define sc_x1_speed_override1_vcoDivider_div100 15 2986 2987 /**************************************************************************** 2988 * Enums: sc_x1_speed_override1_refClkSelect 2989 */ 2990 #define sc_x1_speed_override1_refClkSelect_clk_25MHz 0 2991 #define sc_x1_speed_override1_refClkSelect_clk_100MHz 1 2992 #define sc_x1_speed_override1_refClkSelect_clk_125MHz 2 2993 #define sc_x1_speed_override1_refClkSelect_clk_156p25MHz 3 2994 #define sc_x1_speed_override1_refClkSelect_clk_187p5MHz 4 2995 #define sc_x1_speed_override1_refClkSelect_clk_161p25Mhz 5 2996 #define sc_x1_speed_override1_refClkSelect_clk_50Mhz 6 2997 #define sc_x1_speed_override1_refClkSelect_clk_106p25Mhz 7 2998 2999 /**************************************************************************** 3000 * Enums: sc_x1_speed_override1_aerMMDdevTypeSelect 3001 */ 3002 #define sc_x1_speed_override1_aerMMDdevTypeSelect_combo_core 0 3003 #define sc_x1_speed_override1_aerMMDdevTypeSelect_PMA_PMD 1 3004 #define sc_x1_speed_override1_aerMMDdevTypeSelect_PCS 3 3005 #define sc_x1_speed_override1_aerMMDdevTypeSelect_PHY 4 3006 #define sc_x1_speed_override1_aerMMDdevTypeSelect_DTE 5 3007 #define sc_x1_speed_override1_aerMMDdevTypeSelect_CL73_AN 7 3008 3009 /**************************************************************************** 3010 * Enums: sc_x1_speed_override1_aerMMDportSelect 3011 */ 3012 #define sc_x1_speed_override1_aerMMDportSelect_ln0 0 3013 #define sc_x1_speed_override1_aerMMDportSelect_ln1 1 3014 #define sc_x1_speed_override1_aerMMDportSelect_ln2 2 3015 #define sc_x1_speed_override1_aerMMDportSelect_ln3 3 3016 #define sc_x1_speed_override1_aerMMDportSelect_BCST_ln0_1_2_3 511 3017 #define sc_x1_speed_override1_aerMMDportSelect_BCST_ln0_1 512 3018 #define sc_x1_speed_override1_aerMMDportSelect_BCST_ln2_3 513 3019 3020 /**************************************************************************** 3021 * Enums: sc_x1_speed_override1_firmwareModeSelect 3022 */ 3023 #define sc_x1_speed_override1_firmwareModeSelect_DEFAULT 0 3024 #define sc_x1_speed_override1_firmwareModeSelect_SFP_OPT_LR 1 3025 #define sc_x1_speed_override1_firmwareModeSelect_SFP_DAC 2 3026 #define sc_x1_speed_override1_firmwareModeSelect_XLAUI 3 3027 #define sc_x1_speed_override1_firmwareModeSelect_LONG_CH_6G 4 3028 3029 /**************************************************************************** 3030 * Enums: sc_x1_speed_override1_tempIdxSelect 3031 */ 3032 #define sc_x1_speed_override1_tempIdxSelect_LTE__22p9C 15 3033 #define sc_x1_speed_override1_tempIdxSelect_LTE__12p6C 14 3034 #define sc_x1_speed_override1_tempIdxSelect_LTE__3p0C 13 3035 #define sc_x1_speed_override1_tempIdxSelect_LTE_6p7C 12 3036 #define sc_x1_speed_override1_tempIdxSelect_LTE_16p4C 11 3037 #define sc_x1_speed_override1_tempIdxSelect_LTE_26p6C 10 3038 #define sc_x1_speed_override1_tempIdxSelect_LTE_36p3C 9 3039 #define sc_x1_speed_override1_tempIdxSelect_LTE_46p0C 8 3040 #define sc_x1_speed_override1_tempIdxSelect_LTE_56p2C 7 3041 #define sc_x1_speed_override1_tempIdxSelect_LTE_65p9C 6 3042 #define sc_x1_speed_override1_tempIdxSelect_LTE_75p6C 5 3043 #define sc_x1_speed_override1_tempIdxSelect_LTE_85p3C 4 3044 #define sc_x1_speed_override1_tempIdxSelect_LTE_95p5C 3 3045 #define sc_x1_speed_override1_tempIdxSelect_LTE_105p2C 2 3046 #define sc_x1_speed_override1_tempIdxSelect_LTE_114p9C 1 3047 #define sc_x1_speed_override1_tempIdxSelect_LTE_125p1C 0 3048 3049 /**************************************************************************** 3050 * Enums: sc_x1_speed_override2_cl36TxEEEStates_l 3051 */ 3052 #define sc_x1_speed_override2_cl36TxEEEStates_l_TX_REFRESH 8 3053 #define sc_x1_speed_override2_cl36TxEEEStates_l_TX_QUIET 4 3054 #define sc_x1_speed_override2_cl36TxEEEStates_l_TX_SLEEP 2 3055 #define sc_x1_speed_override2_cl36TxEEEStates_l_TX_ACTIVE 1 3056 3057 /**************************************************************************** 3058 * Enums: sc_x1_speed_override2_cl36TxEEEStates_c 3059 */ 3060 #define sc_x1_speed_override2_cl36TxEEEStates_c_TX_REFRESH 3 3061 #define sc_x1_speed_override2_cl36TxEEEStates_c_TX_QUIET 2 3062 #define sc_x1_speed_override2_cl36TxEEEStates_c_TX_SLEEP 1 3063 #define sc_x1_speed_override2_cl36TxEEEStates_c_TX_ACTIVE 0 3064 3065 /**************************************************************************** 3066 * Enums: sc_x1_speed_override2_cl49TxEEEStates_l 3067 */ 3068 #define sc_x1_speed_override2_cl49TxEEEStates_l_SCR_RESET_2 64 3069 #define sc_x1_speed_override2_cl49TxEEEStates_l_SCR_RESET_1 32 3070 #define sc_x1_speed_override2_cl49TxEEEStates_l_TX_WAKE 16 3071 #define sc_x1_speed_override2_cl49TxEEEStates_l_TX_REFRESH 8 3072 #define sc_x1_speed_override2_cl49TxEEEStates_l_TX_QUIET 4 3073 #define sc_x1_speed_override2_cl49TxEEEStates_l_TX_SLEEP 2 3074 #define sc_x1_speed_override2_cl49TxEEEStates_l_TX_ACTIVE 1 3075 3076 /**************************************************************************** 3077 * Enums: sc_x1_speed_override2_cl49TxEEEStates_c 3078 */ 3079 #define sc_x1_speed_override2_cl49TxEEEStates_c_SCR_RESET_2 6 3080 #define sc_x1_speed_override2_cl49TxEEEStates_c_SCR_RESET_1 5 3081 #define sc_x1_speed_override2_cl49TxEEEStates_c_TX_WAKE 4 3082 #define sc_x1_speed_override2_cl49TxEEEStates_c_TX_REFRESH 3 3083 #define sc_x1_speed_override2_cl49TxEEEStates_c_TX_QUIET 2 3084 #define sc_x1_speed_override2_cl49TxEEEStates_c_TX_SLEEP 1 3085 #define sc_x1_speed_override2_cl49TxEEEStates_c_TX_ACTIVE 0 3086 3087 /**************************************************************************** 3088 * Enums: sc_x1_speed_override2_cl36RxEEEStates_l 3089 */ 3090 #define sc_x1_speed_override2_cl36RxEEEStates_l_RX_LINK_FAIL 32 3091 #define sc_x1_speed_override2_cl36RxEEEStates_l_RX_WTF 16 3092 #define sc_x1_speed_override2_cl36RxEEEStates_l_RX_WAKE 8 3093 #define sc_x1_speed_override2_cl36RxEEEStates_l_RX_QUIET 4 3094 #define sc_x1_speed_override2_cl36RxEEEStates_l_RX_SLEEP 2 3095 #define sc_x1_speed_override2_cl36RxEEEStates_l_RX_ACTIVE 1 3096 3097 /**************************************************************************** 3098 * Enums: sc_x1_speed_override2_cl36RxEEEStates_c 3099 */ 3100 #define sc_x1_speed_override2_cl36RxEEEStates_c_RX_LINK_FAIL 5 3101 #define sc_x1_speed_override2_cl36RxEEEStates_c_RX_WTF 4 3102 #define sc_x1_speed_override2_cl36RxEEEStates_c_RX_WAKE 3 3103 #define sc_x1_speed_override2_cl36RxEEEStates_c_RX_QUIET 2 3104 #define sc_x1_speed_override2_cl36RxEEEStates_c_RX_SLEEP 1 3105 #define sc_x1_speed_override2_cl36RxEEEStates_c_RX_ACTIVE 0 3106 3107 /**************************************************************************** 3108 * Enums: sc_x1_speed_override2_cl49RxEEEStates_l 3109 */ 3110 #define sc_x1_speed_override2_cl49RxEEEStates_l_RX_LINK_FAIL 32 3111 #define sc_x1_speed_override2_cl49RxEEEStates_l_RX_WTF 16 3112 #define sc_x1_speed_override2_cl49RxEEEStates_l_RX_WAKE 8 3113 #define sc_x1_speed_override2_cl49RxEEEStates_l_RX_QUIET 4 3114 #define sc_x1_speed_override2_cl49RxEEEStates_l_RX_SLEEP 2 3115 #define sc_x1_speed_override2_cl49RxEEEStates_l_RX_ACTIVE 1 3116 3117 /**************************************************************************** 3118 * Enums: sc_x1_speed_override2_cl49RxEEEStates_c 3119 */ 3120 #define sc_x1_speed_override2_cl49RxEEEStates_c_RX_LINK_FAIL 5 3121 #define sc_x1_speed_override2_cl49RxEEEStates_c_RX_WTF 4 3122 #define sc_x1_speed_override2_cl49RxEEEStates_c_RX_WAKE 3 3123 #define sc_x1_speed_override2_cl49RxEEEStates_c_RX_QUIET 2 3124 #define sc_x1_speed_override2_cl49RxEEEStates_c_RX_SLEEP 1 3125 #define sc_x1_speed_override2_cl49RxEEEStates_c_RX_ACTIVE 0 3126 3127 /**************************************************************************** 3128 * Enums: sc_x1_speed_override2_cl48TxEEEStates_l 3129 */ 3130 #define sc_x1_speed_override2_cl48TxEEEStates_l_TX_REFRESH 8 3131 #define sc_x1_speed_override2_cl48TxEEEStates_l_TX_QUIET 4 3132 #define sc_x1_speed_override2_cl48TxEEEStates_l_TX_SLEEP 2 3133 #define sc_x1_speed_override2_cl48TxEEEStates_l_TX_ACTIVE 1 3134 3135 /**************************************************************************** 3136 * Enums: sc_x1_speed_override2_cl48TxEEEStates_c 3137 */ 3138 #define sc_x1_speed_override2_cl48TxEEEStates_c_TX_REFRESH 3 3139 #define sc_x1_speed_override2_cl48TxEEEStates_c_TX_QUIET 2 3140 #define sc_x1_speed_override2_cl48TxEEEStates_c_TX_SLEEP 1 3141 #define sc_x1_speed_override2_cl48TxEEEStates_c_TX_ACTIVE 0 3142 3143 /**************************************************************************** 3144 * Enums: sc_x1_speed_override2_cl48RxEEEStates_l 3145 */ 3146 #define sc_x1_speed_override2_cl48RxEEEStates_l_RX_LINK_FAIL 32 3147 #define sc_x1_speed_override2_cl48RxEEEStates_l_RX_WAKE 16 3148 #define sc_x1_speed_override2_cl48RxEEEStates_l_RX_QUIET 8 3149 #define sc_x1_speed_override2_cl48RxEEEStates_l_RX_DEACT 4 3150 #define sc_x1_speed_override2_cl48RxEEEStates_l_RX_SLEEP 2 3151 #define sc_x1_speed_override2_cl48RxEEEStates_l_RX_ACTIVE 1 3152 3153 /**************************************************************************** 3154 * Enums: sc_x1_speed_override2_cl48RxEEEStates_c 3155 */ 3156 #define sc_x1_speed_override2_cl48RxEEEStates_c_RX_LINK_FAIL 5 3157 #define sc_x1_speed_override2_cl48RxEEEStates_c_RX_WAKE 4 3158 #define sc_x1_speed_override2_cl48RxEEEStates_c_RX_QUIET 3 3159 #define sc_x1_speed_override2_cl48RxEEEStates_c_RX_DEACT 2 3160 #define sc_x1_speed_override2_cl48RxEEEStates_c_RX_SLEEP 1 3161 #define sc_x1_speed_override2_cl48RxEEEStates_c_RX_ACTIVE 0 3162 3163 /**************************************************************************** 3164 * Enums: sc_x1_speed_override2_IQP_Options 3165 */ 3166 #define sc_x1_speed_override2_IQP_Options_i50uA 0 3167 #define sc_x1_speed_override2_IQP_Options_i100uA 1 3168 #define sc_x1_speed_override2_IQP_Options_i150uA 2 3169 #define sc_x1_speed_override2_IQP_Options_i200uA 3 3170 #define sc_x1_speed_override2_IQP_Options_i250uA 4 3171 #define sc_x1_speed_override2_IQP_Options_i300uA 5 3172 #define sc_x1_speed_override2_IQP_Options_i350uA 6 3173 #define sc_x1_speed_override2_IQP_Options_i400uA 7 3174 #define sc_x1_speed_override2_IQP_Options_i450uA 8 3175 #define sc_x1_speed_override2_IQP_Options_i500uA 9 3176 #define sc_x1_speed_override2_IQP_Options_i550uA 10 3177 #define sc_x1_speed_override2_IQP_Options_i600uA 11 3178 #define sc_x1_speed_override2_IQP_Options_i650uA 12 3179 #define sc_x1_speed_override2_IQP_Options_i700uA 13 3180 #define sc_x1_speed_override2_IQP_Options_i750uA 14 3181 #define sc_x1_speed_override2_IQP_Options_i800uA 15 3182 3183 /**************************************************************************** 3184 * Enums: sc_x1_speed_override2_IDriver_Options 3185 */ 3186 #define sc_x1_speed_override2_IDriver_Options_v680mV 0 3187 #define sc_x1_speed_override2_IDriver_Options_v730mV 1 3188 #define sc_x1_speed_override2_IDriver_Options_v780mV 2 3189 #define sc_x1_speed_override2_IDriver_Options_v830mV 3 3190 #define sc_x1_speed_override2_IDriver_Options_v880mV 4 3191 #define sc_x1_speed_override2_IDriver_Options_v930mV 5 3192 #define sc_x1_speed_override2_IDriver_Options_v980mV 6 3193 #define sc_x1_speed_override2_IDriver_Options_v1010mV 7 3194 #define sc_x1_speed_override2_IDriver_Options_v1040mV 8 3195 #define sc_x1_speed_override2_IDriver_Options_v1060mV 9 3196 #define sc_x1_speed_override2_IDriver_Options_v1070mV 10 3197 #define sc_x1_speed_override2_IDriver_Options_v1080mV 11 3198 #define sc_x1_speed_override2_IDriver_Options_v1085mV 12 3199 #define sc_x1_speed_override2_IDriver_Options_v1090mV 13 3200 #define sc_x1_speed_override2_IDriver_Options_v1095mV 14 3201 #define sc_x1_speed_override2_IDriver_Options_v1100mV 15 3202 3203 /**************************************************************************** 3204 * Enums: sc_x1_speed_override2_operationModes 3205 */ 3206 #define sc_x1_speed_override2_operationModes_XGXS 0 3207 #define sc_x1_speed_override2_operationModes_XGXG_nCC 1 3208 #define sc_x1_speed_override2_operationModes_Indlane_OS8 4 3209 #define sc_x1_speed_override2_operationModes_IndLane_OS5 5 3210 #define sc_x1_speed_override2_operationModes_PCI 7 3211 #define sc_x1_speed_override2_operationModes_XGXS_nLQ 8 3212 #define sc_x1_speed_override2_operationModes_XGXS_nLQnCC 9 3213 #define sc_x1_speed_override2_operationModes_PBypass 10 3214 #define sc_x1_speed_override2_operationModes_PBypass_nDSK 11 3215 #define sc_x1_speed_override2_operationModes_ComboCoreMode 12 3216 #define sc_x1_speed_override2_operationModes_Clocks_off 15 3217 3218 /**************************************************************************** 3219 * Enums: sc_x1_speed_override2_synce_enum 3220 */ 3221 #define sc_x1_speed_override2_synce_enum_SYNCE_NO_DIV 0 3222 #define sc_x1_speed_override2_synce_enum_SYNCE_DIV_7 1 3223 #define sc_x1_speed_override2_synce_enum_SYNCE_DIV_11 2 3224 #define sc_x1_speed_override2_synce_enum_SYNCE_DIV_10 3 3225 3226 /**************************************************************************** 3227 * Enums: sc_x1_speed_override2_synce_enum_stage0 3228 */ 3229 #define sc_x1_speed_override2_synce_enum_stage0_SYNCE_NO_DIV 0 3230 #define sc_x1_speed_override2_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 3231 #define sc_x1_speed_override2_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 3232 3233 /**************************************************************************** 3234 * Enums: sc_x1_speed_override2_operationSpeeds 3235 */ 3236 #define sc_x1_speed_override2_operationSpeeds_SPEED_10G_X4_10p3125 59 3237 #define sc_x1_speed_override2_operationSpeeds_SPEED_10G_CX4_10p3125 58 3238 #define sc_x1_speed_override2_operationSpeeds_SPEED_10G_KX4_10p3125 57 3239 #define sc_x1_speed_override2_operationSpeeds_SPEED_2p5G_X1_10p3125 56 3240 #define sc_x1_speed_override2_operationSpeeds_SPEED_1000M_10p3125 55 3241 #define sc_x1_speed_override2_operationSpeeds_SPEED_100M_10p3125 54 3242 #define sc_x1_speed_override2_operationSpeeds_SPEED_10M_10p3125 53 3243 #define sc_x1_speed_override2_operationSpeeds_SPEED_10p5G_X4 50 3244 #define sc_x1_speed_override2_operationSpeeds_SPEED_5G_KR1 49 3245 #define sc_x1_speed_override2_operationSpeeds_SPEED_42p42G_X4 44 3246 #define sc_x1_speed_override2_operationSpeeds_SPEED_21p21G_X2 43 3247 #define sc_x1_speed_override2_operationSpeeds_SPEED_48p48G_X4 42 3248 #define sc_x1_speed_override2_operationSpeeds_SPEED_24p24G_X2 41 3249 #define sc_x1_speed_override2_operationSpeeds_SPEED_12p12G_X1 40 3250 #define sc_x1_speed_override2_operationSpeeds_SPEED_127G_X12 39 3251 #define sc_x1_speed_override2_operationSpeeds_SPEED_120G_X12 38 3252 #define sc_x1_speed_override2_operationSpeeds_SPEED_107G_X10 37 3253 #define sc_x1_speed_override2_operationSpeeds_SPEED_100G_CR10 36 3254 #define sc_x1_speed_override2_operationSpeeds_SPEED_42G_X4 35 3255 #define sc_x1_speed_override2_operationSpeeds_SPEED_40G_CR4 34 3256 #define sc_x1_speed_override2_operationSpeeds_SPEED_40G_KR4 33 3257 #define sc_x1_speed_override2_operationSpeeds_SPEED_21G_X2 32 3258 #define sc_x1_speed_override2_operationSpeeds_SPEED_20G_CR2 31 3259 #define sc_x1_speed_override2_operationSpeeds_SPEED_20G_KR2 30 3260 #define sc_x1_speed_override2_operationSpeeds_SPEED_10p6_X1 29 3261 #define sc_x1_speed_override2_operationSpeeds_SPEED_10G_KR1 28 3262 #define sc_x1_speed_override2_operationSpeeds_SPEED_40G_X4 27 3263 #define sc_x1_speed_override2_operationSpeeds_SPEED_20G_X2 26 3264 #define sc_x1_speed_override2_operationSpeeds_SPEED_20G_CX2 25 3265 #define sc_x1_speed_override2_operationSpeeds_SPEED_31p5G_KR4 24 3266 #define sc_x1_speed_override2_operationSpeeds_SPEED_31p5G_X4 23 3267 #define sc_x1_speed_override2_operationSpeeds_SPEED_15p75G_X2 22 3268 #define sc_x1_speed_override2_operationSpeeds_SPEED_25p45G_X4 21 3269 #define sc_x1_speed_override2_operationSpeeds_SPEED_12p7G_X2 20 3270 #define sc_x1_speed_override2_operationSpeeds_SPEED_21G_X4 19 3271 #define sc_x1_speed_override2_operationSpeeds_SPEED_10p5G_X2 18 3272 #define sc_x1_speed_override2_operationSpeeds_SPEED_20G_X4 17 3273 #define sc_x1_speed_override2_operationSpeeds_SPEED_10G_X2 16 3274 #define sc_x1_speed_override2_operationSpeeds_SPEED_10G_CX2 15 3275 #define sc_x1_speed_override2_operationSpeeds_SPEED_20G_CX4 14 3276 #define sc_x1_speed_override2_operationSpeeds_SPEED_16G_X4 13 3277 #define sc_x1_speed_override2_operationSpeeds_SPEED_15G_X4 12 3278 #define sc_x1_speed_override2_operationSpeeds_SPEED_13G_X4 11 3279 #define sc_x1_speed_override2_operationSpeeds_SPEED_10G_X4 10 3280 #define sc_x1_speed_override2_operationSpeeds_SPEED_10G_KX4 9 3281 #define sc_x1_speed_override2_operationSpeeds_SPEED_10G_CX4 8 3282 #define sc_x1_speed_override2_operationSpeeds_SPEED_5G_X1 7 3283 #define sc_x1_speed_override2_operationSpeeds_SPEED_2p5G_X1 6 3284 #define sc_x1_speed_override2_operationSpeeds_SPEED_1G_KX1 5 3285 #define sc_x1_speed_override2_operationSpeeds_SPEED_1G_CX1 4 3286 #define sc_x1_speed_override2_operationSpeeds_SPEED_1000M 3 3287 #define sc_x1_speed_override2_operationSpeeds_SPEED_100M 2 3288 #define sc_x1_speed_override2_operationSpeeds_SPEED_10M 1 3289 3290 /**************************************************************************** 3291 * Enums: sc_x1_speed_override2_actualSpeeds 3292 */ 3293 #define sc_x1_speed_override2_actualSpeeds_dr_10M 0 3294 #define sc_x1_speed_override2_actualSpeeds_dr_100M 1 3295 #define sc_x1_speed_override2_actualSpeeds_dr_1G 2 3296 #define sc_x1_speed_override2_actualSpeeds_dr_2p5G 3 3297 #define sc_x1_speed_override2_actualSpeeds_dr_5G_X4 4 3298 #define sc_x1_speed_override2_actualSpeeds_dr_6G_X4 5 3299 #define sc_x1_speed_override2_actualSpeeds_dr_10G_HiG 6 3300 #define sc_x1_speed_override2_actualSpeeds_dr_10G_CX4 7 3301 #define sc_x1_speed_override2_actualSpeeds_dr_12G_HiG 8 3302 #define sc_x1_speed_override2_actualSpeeds_dr_12p5G_X4 9 3303 #define sc_x1_speed_override2_actualSpeeds_dr_13G_X4 10 3304 #define sc_x1_speed_override2_actualSpeeds_dr_15G_X4 11 3305 #define sc_x1_speed_override2_actualSpeeds_dr_16G_X4 12 3306 #define sc_x1_speed_override2_actualSpeeds_dr_1G_KX 13 3307 #define sc_x1_speed_override2_actualSpeeds_dr_10G_KX4 14 3308 #define sc_x1_speed_override2_actualSpeeds_dr_10G_KR 15 3309 #define sc_x1_speed_override2_actualSpeeds_dr_5G 16 3310 #define sc_x1_speed_override2_actualSpeeds_dr_6p4G 17 3311 #define sc_x1_speed_override2_actualSpeeds_dr_20G_X4 18 3312 #define sc_x1_speed_override2_actualSpeeds_dr_21G_X4 19 3313 #define sc_x1_speed_override2_actualSpeeds_dr_25G_X4 20 3314 #define sc_x1_speed_override2_actualSpeeds_dr_10G_HiG_DXGXS 21 3315 #define sc_x1_speed_override2_actualSpeeds_dr_10G_DXGXS 22 3316 #define sc_x1_speed_override2_actualSpeeds_dr_10p5G_HiG_DXGXS 23 3317 #define sc_x1_speed_override2_actualSpeeds_dr_10p5G_DXGXS 24 3318 #define sc_x1_speed_override2_actualSpeeds_dr_12p773G_HiG_DXGXS 25 3319 #define sc_x1_speed_override2_actualSpeeds_dr_12p773G_DXGXS 26 3320 #define sc_x1_speed_override2_actualSpeeds_dr_10G_XFI 27 3321 #define sc_x1_speed_override2_actualSpeeds_dr_40G 28 3322 #define sc_x1_speed_override2_actualSpeeds_dr_20G_HiG_DXGXS 29 3323 #define sc_x1_speed_override2_actualSpeeds_dr_20G_DXGXS 30 3324 #define sc_x1_speed_override2_actualSpeeds_dr_10G_SFI 31 3325 #define sc_x1_speed_override2_actualSpeeds_dr_31p5G 32 3326 #define sc_x1_speed_override2_actualSpeeds_dr_32p7G 33 3327 #define sc_x1_speed_override2_actualSpeeds_dr_20G_SCR 34 3328 #define sc_x1_speed_override2_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 3329 #define sc_x1_speed_override2_actualSpeeds_dr_10G_DXGXS_SCR 36 3330 #define sc_x1_speed_override2_actualSpeeds_dr_12G_R2 37 3331 #define sc_x1_speed_override2_actualSpeeds_dr_10G_X2 38 3332 #define sc_x1_speed_override2_actualSpeeds_dr_40G_KR4 39 3333 #define sc_x1_speed_override2_actualSpeeds_dr_40G_CR4 40 3334 #define sc_x1_speed_override2_actualSpeeds_dr_100G_CR10 41 3335 #define sc_x1_speed_override2_actualSpeeds_dr_15p75G_DXGXS 44 3336 #define sc_x1_speed_override2_actualSpeeds_dr_20G_KR2 57 3337 #define sc_x1_speed_override2_actualSpeeds_dr_20G_CR2 58 3338 3339 /**************************************************************************** 3340 * Enums: sc_x1_speed_override2_actualSpeedsMisc1 3341 */ 3342 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_2500BRCM_X1 16 3343 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_5000BRCM_X4 17 3344 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_6000BRCM_X4 18 3345 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_10GHiGig_X4 19 3346 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_10GBASE_CX4 20 3347 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_12GHiGig_X4 21 3348 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 3349 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_13GHiGig_X4 23 3350 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_15GHiGig_X4 24 3351 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_16GHiGig_X4 25 3352 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_5000BRCM_X1 26 3353 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_6363BRCM_X1 27 3354 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_20GHiGig_X4 28 3355 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_21GHiGig_X4 29 3356 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 3357 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 3358 3359 /**************************************************************************** 3360 * Enums: sc_x1_speed_override2_IndLaneModes 3361 */ 3362 #define sc_x1_speed_override2_IndLaneModes_SWSDR_div2 0 3363 #define sc_x1_speed_override2_IndLaneModes_SWSDR_div1 1 3364 #define sc_x1_speed_override2_IndLaneModes_DWSDR_div2 2 3365 #define sc_x1_speed_override2_IndLaneModes_DWSDR_div1 3 3366 3367 /**************************************************************************** 3368 * Enums: sc_x1_speed_override2_prbsSelect 3369 */ 3370 #define sc_x1_speed_override2_prbsSelect_prbs7 0 3371 #define sc_x1_speed_override2_prbsSelect_prbs15 1 3372 #define sc_x1_speed_override2_prbsSelect_prbs23 2 3373 #define sc_x1_speed_override2_prbsSelect_prbs31 3 3374 3375 /**************************************************************************** 3376 * Enums: sc_x1_speed_override2_vcoDivider 3377 */ 3378 #define sc_x1_speed_override2_vcoDivider_div32 0 3379 #define sc_x1_speed_override2_vcoDivider_div36 1 3380 #define sc_x1_speed_override2_vcoDivider_div40 2 3381 #define sc_x1_speed_override2_vcoDivider_div42 3 3382 #define sc_x1_speed_override2_vcoDivider_div48 4 3383 #define sc_x1_speed_override2_vcoDivider_div50 5 3384 #define sc_x1_speed_override2_vcoDivider_div52 6 3385 #define sc_x1_speed_override2_vcoDivider_div54 7 3386 #define sc_x1_speed_override2_vcoDivider_div60 8 3387 #define sc_x1_speed_override2_vcoDivider_div64 9 3388 #define sc_x1_speed_override2_vcoDivider_div66 10 3389 #define sc_x1_speed_override2_vcoDivider_div68 11 3390 #define sc_x1_speed_override2_vcoDivider_div70 12 3391 #define sc_x1_speed_override2_vcoDivider_div80 13 3392 #define sc_x1_speed_override2_vcoDivider_div92 14 3393 #define sc_x1_speed_override2_vcoDivider_div100 15 3394 3395 /**************************************************************************** 3396 * Enums: sc_x1_speed_override2_refClkSelect 3397 */ 3398 #define sc_x1_speed_override2_refClkSelect_clk_25MHz 0 3399 #define sc_x1_speed_override2_refClkSelect_clk_100MHz 1 3400 #define sc_x1_speed_override2_refClkSelect_clk_125MHz 2 3401 #define sc_x1_speed_override2_refClkSelect_clk_156p25MHz 3 3402 #define sc_x1_speed_override2_refClkSelect_clk_187p5MHz 4 3403 #define sc_x1_speed_override2_refClkSelect_clk_161p25Mhz 5 3404 #define sc_x1_speed_override2_refClkSelect_clk_50Mhz 6 3405 #define sc_x1_speed_override2_refClkSelect_clk_106p25Mhz 7 3406 3407 /**************************************************************************** 3408 * Enums: sc_x1_speed_override2_aerMMDdevTypeSelect 3409 */ 3410 #define sc_x1_speed_override2_aerMMDdevTypeSelect_combo_core 0 3411 #define sc_x1_speed_override2_aerMMDdevTypeSelect_PMA_PMD 1 3412 #define sc_x1_speed_override2_aerMMDdevTypeSelect_PCS 3 3413 #define sc_x1_speed_override2_aerMMDdevTypeSelect_PHY 4 3414 #define sc_x1_speed_override2_aerMMDdevTypeSelect_DTE 5 3415 #define sc_x1_speed_override2_aerMMDdevTypeSelect_CL73_AN 7 3416 3417 /**************************************************************************** 3418 * Enums: sc_x1_speed_override2_aerMMDportSelect 3419 */ 3420 #define sc_x1_speed_override2_aerMMDportSelect_ln0 0 3421 #define sc_x1_speed_override2_aerMMDportSelect_ln1 1 3422 #define sc_x1_speed_override2_aerMMDportSelect_ln2 2 3423 #define sc_x1_speed_override2_aerMMDportSelect_ln3 3 3424 #define sc_x1_speed_override2_aerMMDportSelect_BCST_ln0_1_2_3 511 3425 #define sc_x1_speed_override2_aerMMDportSelect_BCST_ln0_1 512 3426 #define sc_x1_speed_override2_aerMMDportSelect_BCST_ln2_3 513 3427 3428 /**************************************************************************** 3429 * Enums: sc_x1_speed_override2_firmwareModeSelect 3430 */ 3431 #define sc_x1_speed_override2_firmwareModeSelect_DEFAULT 0 3432 #define sc_x1_speed_override2_firmwareModeSelect_SFP_OPT_LR 1 3433 #define sc_x1_speed_override2_firmwareModeSelect_SFP_DAC 2 3434 #define sc_x1_speed_override2_firmwareModeSelect_XLAUI 3 3435 #define sc_x1_speed_override2_firmwareModeSelect_LONG_CH_6G 4 3436 3437 /**************************************************************************** 3438 * Enums: sc_x1_speed_override2_tempIdxSelect 3439 */ 3440 #define sc_x1_speed_override2_tempIdxSelect_LTE__22p9C 15 3441 #define sc_x1_speed_override2_tempIdxSelect_LTE__12p6C 14 3442 #define sc_x1_speed_override2_tempIdxSelect_LTE__3p0C 13 3443 #define sc_x1_speed_override2_tempIdxSelect_LTE_6p7C 12 3444 #define sc_x1_speed_override2_tempIdxSelect_LTE_16p4C 11 3445 #define sc_x1_speed_override2_tempIdxSelect_LTE_26p6C 10 3446 #define sc_x1_speed_override2_tempIdxSelect_LTE_36p3C 9 3447 #define sc_x1_speed_override2_tempIdxSelect_LTE_46p0C 8 3448 #define sc_x1_speed_override2_tempIdxSelect_LTE_56p2C 7 3449 #define sc_x1_speed_override2_tempIdxSelect_LTE_65p9C 6 3450 #define sc_x1_speed_override2_tempIdxSelect_LTE_75p6C 5 3451 #define sc_x1_speed_override2_tempIdxSelect_LTE_85p3C 4 3452 #define sc_x1_speed_override2_tempIdxSelect_LTE_95p5C 3 3453 #define sc_x1_speed_override2_tempIdxSelect_LTE_105p2C 2 3454 #define sc_x1_speed_override2_tempIdxSelect_LTE_114p9C 1 3455 #define sc_x1_speed_override2_tempIdxSelect_LTE_125p1C 0 3456 3457 /**************************************************************************** 3458 * Enums: sc_x1_speed_override3_cl36TxEEEStates_l 3459 */ 3460 #define sc_x1_speed_override3_cl36TxEEEStates_l_TX_REFRESH 8 3461 #define sc_x1_speed_override3_cl36TxEEEStates_l_TX_QUIET 4 3462 #define sc_x1_speed_override3_cl36TxEEEStates_l_TX_SLEEP 2 3463 #define sc_x1_speed_override3_cl36TxEEEStates_l_TX_ACTIVE 1 3464 3465 /**************************************************************************** 3466 * Enums: sc_x1_speed_override3_cl36TxEEEStates_c 3467 */ 3468 #define sc_x1_speed_override3_cl36TxEEEStates_c_TX_REFRESH 3 3469 #define sc_x1_speed_override3_cl36TxEEEStates_c_TX_QUIET 2 3470 #define sc_x1_speed_override3_cl36TxEEEStates_c_TX_SLEEP 1 3471 #define sc_x1_speed_override3_cl36TxEEEStates_c_TX_ACTIVE 0 3472 3473 /**************************************************************************** 3474 * Enums: sc_x1_speed_override3_cl49TxEEEStates_l 3475 */ 3476 #define sc_x1_speed_override3_cl49TxEEEStates_l_SCR_RESET_2 64 3477 #define sc_x1_speed_override3_cl49TxEEEStates_l_SCR_RESET_1 32 3478 #define sc_x1_speed_override3_cl49TxEEEStates_l_TX_WAKE 16 3479 #define sc_x1_speed_override3_cl49TxEEEStates_l_TX_REFRESH 8 3480 #define sc_x1_speed_override3_cl49TxEEEStates_l_TX_QUIET 4 3481 #define sc_x1_speed_override3_cl49TxEEEStates_l_TX_SLEEP 2 3482 #define sc_x1_speed_override3_cl49TxEEEStates_l_TX_ACTIVE 1 3483 3484 /**************************************************************************** 3485 * Enums: sc_x1_speed_override3_cl49TxEEEStates_c 3486 */ 3487 #define sc_x1_speed_override3_cl49TxEEEStates_c_SCR_RESET_2 6 3488 #define sc_x1_speed_override3_cl49TxEEEStates_c_SCR_RESET_1 5 3489 #define sc_x1_speed_override3_cl49TxEEEStates_c_TX_WAKE 4 3490 #define sc_x1_speed_override3_cl49TxEEEStates_c_TX_REFRESH 3 3491 #define sc_x1_speed_override3_cl49TxEEEStates_c_TX_QUIET 2 3492 #define sc_x1_speed_override3_cl49TxEEEStates_c_TX_SLEEP 1 3493 #define sc_x1_speed_override3_cl49TxEEEStates_c_TX_ACTIVE 0 3494 3495 /**************************************************************************** 3496 * Enums: sc_x1_speed_override3_cl36RxEEEStates_l 3497 */ 3498 #define sc_x1_speed_override3_cl36RxEEEStates_l_RX_LINK_FAIL 32 3499 #define sc_x1_speed_override3_cl36RxEEEStates_l_RX_WTF 16 3500 #define sc_x1_speed_override3_cl36RxEEEStates_l_RX_WAKE 8 3501 #define sc_x1_speed_override3_cl36RxEEEStates_l_RX_QUIET 4 3502 #define sc_x1_speed_override3_cl36RxEEEStates_l_RX_SLEEP 2 3503 #define sc_x1_speed_override3_cl36RxEEEStates_l_RX_ACTIVE 1 3504 3505 /**************************************************************************** 3506 * Enums: sc_x1_speed_override3_cl36RxEEEStates_c 3507 */ 3508 #define sc_x1_speed_override3_cl36RxEEEStates_c_RX_LINK_FAIL 5 3509 #define sc_x1_speed_override3_cl36RxEEEStates_c_RX_WTF 4 3510 #define sc_x1_speed_override3_cl36RxEEEStates_c_RX_WAKE 3 3511 #define sc_x1_speed_override3_cl36RxEEEStates_c_RX_QUIET 2 3512 #define sc_x1_speed_override3_cl36RxEEEStates_c_RX_SLEEP 1 3513 #define sc_x1_speed_override3_cl36RxEEEStates_c_RX_ACTIVE 0 3514 3515 /**************************************************************************** 3516 * Enums: sc_x1_speed_override3_cl49RxEEEStates_l 3517 */ 3518 #define sc_x1_speed_override3_cl49RxEEEStates_l_RX_LINK_FAIL 32 3519 #define sc_x1_speed_override3_cl49RxEEEStates_l_RX_WTF 16 3520 #define sc_x1_speed_override3_cl49RxEEEStates_l_RX_WAKE 8 3521 #define sc_x1_speed_override3_cl49RxEEEStates_l_RX_QUIET 4 3522 #define sc_x1_speed_override3_cl49RxEEEStates_l_RX_SLEEP 2 3523 #define sc_x1_speed_override3_cl49RxEEEStates_l_RX_ACTIVE 1 3524 3525 /**************************************************************************** 3526 * Enums: sc_x1_speed_override3_cl49RxEEEStates_c 3527 */ 3528 #define sc_x1_speed_override3_cl49RxEEEStates_c_RX_LINK_FAIL 5 3529 #define sc_x1_speed_override3_cl49RxEEEStates_c_RX_WTF 4 3530 #define sc_x1_speed_override3_cl49RxEEEStates_c_RX_WAKE 3 3531 #define sc_x1_speed_override3_cl49RxEEEStates_c_RX_QUIET 2 3532 #define sc_x1_speed_override3_cl49RxEEEStates_c_RX_SLEEP 1 3533 #define sc_x1_speed_override3_cl49RxEEEStates_c_RX_ACTIVE 0 3534 3535 /**************************************************************************** 3536 * Enums: sc_x1_speed_override3_cl48TxEEEStates_l 3537 */ 3538 #define sc_x1_speed_override3_cl48TxEEEStates_l_TX_REFRESH 8 3539 #define sc_x1_speed_override3_cl48TxEEEStates_l_TX_QUIET 4 3540 #define sc_x1_speed_override3_cl48TxEEEStates_l_TX_SLEEP 2 3541 #define sc_x1_speed_override3_cl48TxEEEStates_l_TX_ACTIVE 1 3542 3543 /**************************************************************************** 3544 * Enums: sc_x1_speed_override3_cl48TxEEEStates_c 3545 */ 3546 #define sc_x1_speed_override3_cl48TxEEEStates_c_TX_REFRESH 3 3547 #define sc_x1_speed_override3_cl48TxEEEStates_c_TX_QUIET 2 3548 #define sc_x1_speed_override3_cl48TxEEEStates_c_TX_SLEEP 1 3549 #define sc_x1_speed_override3_cl48TxEEEStates_c_TX_ACTIVE 0 3550 3551 /**************************************************************************** 3552 * Enums: sc_x1_speed_override3_cl48RxEEEStates_l 3553 */ 3554 #define sc_x1_speed_override3_cl48RxEEEStates_l_RX_LINK_FAIL 32 3555 #define sc_x1_speed_override3_cl48RxEEEStates_l_RX_WAKE 16 3556 #define sc_x1_speed_override3_cl48RxEEEStates_l_RX_QUIET 8 3557 #define sc_x1_speed_override3_cl48RxEEEStates_l_RX_DEACT 4 3558 #define sc_x1_speed_override3_cl48RxEEEStates_l_RX_SLEEP 2 3559 #define sc_x1_speed_override3_cl48RxEEEStates_l_RX_ACTIVE 1 3560 3561 /**************************************************************************** 3562 * Enums: sc_x1_speed_override3_cl48RxEEEStates_c 3563 */ 3564 #define sc_x1_speed_override3_cl48RxEEEStates_c_RX_LINK_FAIL 5 3565 #define sc_x1_speed_override3_cl48RxEEEStates_c_RX_WAKE 4 3566 #define sc_x1_speed_override3_cl48RxEEEStates_c_RX_QUIET 3 3567 #define sc_x1_speed_override3_cl48RxEEEStates_c_RX_DEACT 2 3568 #define sc_x1_speed_override3_cl48RxEEEStates_c_RX_SLEEP 1 3569 #define sc_x1_speed_override3_cl48RxEEEStates_c_RX_ACTIVE 0 3570 3571 /**************************************************************************** 3572 * Enums: sc_x1_speed_override3_IQP_Options 3573 */ 3574 #define sc_x1_speed_override3_IQP_Options_i50uA 0 3575 #define sc_x1_speed_override3_IQP_Options_i100uA 1 3576 #define sc_x1_speed_override3_IQP_Options_i150uA 2 3577 #define sc_x1_speed_override3_IQP_Options_i200uA 3 3578 #define sc_x1_speed_override3_IQP_Options_i250uA 4 3579 #define sc_x1_speed_override3_IQP_Options_i300uA 5 3580 #define sc_x1_speed_override3_IQP_Options_i350uA 6 3581 #define sc_x1_speed_override3_IQP_Options_i400uA 7 3582 #define sc_x1_speed_override3_IQP_Options_i450uA 8 3583 #define sc_x1_speed_override3_IQP_Options_i500uA 9 3584 #define sc_x1_speed_override3_IQP_Options_i550uA 10 3585 #define sc_x1_speed_override3_IQP_Options_i600uA 11 3586 #define sc_x1_speed_override3_IQP_Options_i650uA 12 3587 #define sc_x1_speed_override3_IQP_Options_i700uA 13 3588 #define sc_x1_speed_override3_IQP_Options_i750uA 14 3589 #define sc_x1_speed_override3_IQP_Options_i800uA 15 3590 3591 /**************************************************************************** 3592 * Enums: sc_x1_speed_override3_IDriver_Options 3593 */ 3594 #define sc_x1_speed_override3_IDriver_Options_v680mV 0 3595 #define sc_x1_speed_override3_IDriver_Options_v730mV 1 3596 #define sc_x1_speed_override3_IDriver_Options_v780mV 2 3597 #define sc_x1_speed_override3_IDriver_Options_v830mV 3 3598 #define sc_x1_speed_override3_IDriver_Options_v880mV 4 3599 #define sc_x1_speed_override3_IDriver_Options_v930mV 5 3600 #define sc_x1_speed_override3_IDriver_Options_v980mV 6 3601 #define sc_x1_speed_override3_IDriver_Options_v1010mV 7 3602 #define sc_x1_speed_override3_IDriver_Options_v1040mV 8 3603 #define sc_x1_speed_override3_IDriver_Options_v1060mV 9 3604 #define sc_x1_speed_override3_IDriver_Options_v1070mV 10 3605 #define sc_x1_speed_override3_IDriver_Options_v1080mV 11 3606 #define sc_x1_speed_override3_IDriver_Options_v1085mV 12 3607 #define sc_x1_speed_override3_IDriver_Options_v1090mV 13 3608 #define sc_x1_speed_override3_IDriver_Options_v1095mV 14 3609 #define sc_x1_speed_override3_IDriver_Options_v1100mV 15 3610 3611 /**************************************************************************** 3612 * Enums: sc_x1_speed_override3_operationModes 3613 */ 3614 #define sc_x1_speed_override3_operationModes_XGXS 0 3615 #define sc_x1_speed_override3_operationModes_XGXG_nCC 1 3616 #define sc_x1_speed_override3_operationModes_Indlane_OS8 4 3617 #define sc_x1_speed_override3_operationModes_IndLane_OS5 5 3618 #define sc_x1_speed_override3_operationModes_PCI 7 3619 #define sc_x1_speed_override3_operationModes_XGXS_nLQ 8 3620 #define sc_x1_speed_override3_operationModes_XGXS_nLQnCC 9 3621 #define sc_x1_speed_override3_operationModes_PBypass 10 3622 #define sc_x1_speed_override3_operationModes_PBypass_nDSK 11 3623 #define sc_x1_speed_override3_operationModes_ComboCoreMode 12 3624 #define sc_x1_speed_override3_operationModes_Clocks_off 15 3625 3626 /**************************************************************************** 3627 * Enums: sc_x1_speed_override3_synce_enum 3628 */ 3629 #define sc_x1_speed_override3_synce_enum_SYNCE_NO_DIV 0 3630 #define sc_x1_speed_override3_synce_enum_SYNCE_DIV_7 1 3631 #define sc_x1_speed_override3_synce_enum_SYNCE_DIV_11 2 3632 #define sc_x1_speed_override3_synce_enum_SYNCE_DIV_10 3 3633 3634 /**************************************************************************** 3635 * Enums: sc_x1_speed_override3_synce_enum_stage0 3636 */ 3637 #define sc_x1_speed_override3_synce_enum_stage0_SYNCE_NO_DIV 0 3638 #define sc_x1_speed_override3_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 3639 #define sc_x1_speed_override3_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 3640 3641 /**************************************************************************** 3642 * Enums: sc_x1_speed_override3_operationSpeeds 3643 */ 3644 #define sc_x1_speed_override3_operationSpeeds_SPEED_10G_X4_10p3125 59 3645 #define sc_x1_speed_override3_operationSpeeds_SPEED_10G_CX4_10p3125 58 3646 #define sc_x1_speed_override3_operationSpeeds_SPEED_10G_KX4_10p3125 57 3647 #define sc_x1_speed_override3_operationSpeeds_SPEED_2p5G_X1_10p3125 56 3648 #define sc_x1_speed_override3_operationSpeeds_SPEED_1000M_10p3125 55 3649 #define sc_x1_speed_override3_operationSpeeds_SPEED_100M_10p3125 54 3650 #define sc_x1_speed_override3_operationSpeeds_SPEED_10M_10p3125 53 3651 #define sc_x1_speed_override3_operationSpeeds_SPEED_10p5G_X4 50 3652 #define sc_x1_speed_override3_operationSpeeds_SPEED_5G_KR1 49 3653 #define sc_x1_speed_override3_operationSpeeds_SPEED_42p42G_X4 44 3654 #define sc_x1_speed_override3_operationSpeeds_SPEED_21p21G_X2 43 3655 #define sc_x1_speed_override3_operationSpeeds_SPEED_48p48G_X4 42 3656 #define sc_x1_speed_override3_operationSpeeds_SPEED_24p24G_X2 41 3657 #define sc_x1_speed_override3_operationSpeeds_SPEED_12p12G_X1 40 3658 #define sc_x1_speed_override3_operationSpeeds_SPEED_127G_X12 39 3659 #define sc_x1_speed_override3_operationSpeeds_SPEED_120G_X12 38 3660 #define sc_x1_speed_override3_operationSpeeds_SPEED_107G_X10 37 3661 #define sc_x1_speed_override3_operationSpeeds_SPEED_100G_CR10 36 3662 #define sc_x1_speed_override3_operationSpeeds_SPEED_42G_X4 35 3663 #define sc_x1_speed_override3_operationSpeeds_SPEED_40G_CR4 34 3664 #define sc_x1_speed_override3_operationSpeeds_SPEED_40G_KR4 33 3665 #define sc_x1_speed_override3_operationSpeeds_SPEED_21G_X2 32 3666 #define sc_x1_speed_override3_operationSpeeds_SPEED_20G_CR2 31 3667 #define sc_x1_speed_override3_operationSpeeds_SPEED_20G_KR2 30 3668 #define sc_x1_speed_override3_operationSpeeds_SPEED_10p6_X1 29 3669 #define sc_x1_speed_override3_operationSpeeds_SPEED_10G_KR1 28 3670 #define sc_x1_speed_override3_operationSpeeds_SPEED_40G_X4 27 3671 #define sc_x1_speed_override3_operationSpeeds_SPEED_20G_X2 26 3672 #define sc_x1_speed_override3_operationSpeeds_SPEED_20G_CX2 25 3673 #define sc_x1_speed_override3_operationSpeeds_SPEED_31p5G_KR4 24 3674 #define sc_x1_speed_override3_operationSpeeds_SPEED_31p5G_X4 23 3675 #define sc_x1_speed_override3_operationSpeeds_SPEED_15p75G_X2 22 3676 #define sc_x1_speed_override3_operationSpeeds_SPEED_25p45G_X4 21 3677 #define sc_x1_speed_override3_operationSpeeds_SPEED_12p7G_X2 20 3678 #define sc_x1_speed_override3_operationSpeeds_SPEED_21G_X4 19 3679 #define sc_x1_speed_override3_operationSpeeds_SPEED_10p5G_X2 18 3680 #define sc_x1_speed_override3_operationSpeeds_SPEED_20G_X4 17 3681 #define sc_x1_speed_override3_operationSpeeds_SPEED_10G_X2 16 3682 #define sc_x1_speed_override3_operationSpeeds_SPEED_10G_CX2 15 3683 #define sc_x1_speed_override3_operationSpeeds_SPEED_20G_CX4 14 3684 #define sc_x1_speed_override3_operationSpeeds_SPEED_16G_X4 13 3685 #define sc_x1_speed_override3_operationSpeeds_SPEED_15G_X4 12 3686 #define sc_x1_speed_override3_operationSpeeds_SPEED_13G_X4 11 3687 #define sc_x1_speed_override3_operationSpeeds_SPEED_10G_X4 10 3688 #define sc_x1_speed_override3_operationSpeeds_SPEED_10G_KX4 9 3689 #define sc_x1_speed_override3_operationSpeeds_SPEED_10G_CX4 8 3690 #define sc_x1_speed_override3_operationSpeeds_SPEED_5G_X1 7 3691 #define sc_x1_speed_override3_operationSpeeds_SPEED_2p5G_X1 6 3692 #define sc_x1_speed_override3_operationSpeeds_SPEED_1G_KX1 5 3693 #define sc_x1_speed_override3_operationSpeeds_SPEED_1G_CX1 4 3694 #define sc_x1_speed_override3_operationSpeeds_SPEED_1000M 3 3695 #define sc_x1_speed_override3_operationSpeeds_SPEED_100M 2 3696 #define sc_x1_speed_override3_operationSpeeds_SPEED_10M 1 3697 3698 /**************************************************************************** 3699 * Enums: sc_x1_speed_override3_actualSpeeds 3700 */ 3701 #define sc_x1_speed_override3_actualSpeeds_dr_10M 0 3702 #define sc_x1_speed_override3_actualSpeeds_dr_100M 1 3703 #define sc_x1_speed_override3_actualSpeeds_dr_1G 2 3704 #define sc_x1_speed_override3_actualSpeeds_dr_2p5G 3 3705 #define sc_x1_speed_override3_actualSpeeds_dr_5G_X4 4 3706 #define sc_x1_speed_override3_actualSpeeds_dr_6G_X4 5 3707 #define sc_x1_speed_override3_actualSpeeds_dr_10G_HiG 6 3708 #define sc_x1_speed_override3_actualSpeeds_dr_10G_CX4 7 3709 #define sc_x1_speed_override3_actualSpeeds_dr_12G_HiG 8 3710 #define sc_x1_speed_override3_actualSpeeds_dr_12p5G_X4 9 3711 #define sc_x1_speed_override3_actualSpeeds_dr_13G_X4 10 3712 #define sc_x1_speed_override3_actualSpeeds_dr_15G_X4 11 3713 #define sc_x1_speed_override3_actualSpeeds_dr_16G_X4 12 3714 #define sc_x1_speed_override3_actualSpeeds_dr_1G_KX 13 3715 #define sc_x1_speed_override3_actualSpeeds_dr_10G_KX4 14 3716 #define sc_x1_speed_override3_actualSpeeds_dr_10G_KR 15 3717 #define sc_x1_speed_override3_actualSpeeds_dr_5G 16 3718 #define sc_x1_speed_override3_actualSpeeds_dr_6p4G 17 3719 #define sc_x1_speed_override3_actualSpeeds_dr_20G_X4 18 3720 #define sc_x1_speed_override3_actualSpeeds_dr_21G_X4 19 3721 #define sc_x1_speed_override3_actualSpeeds_dr_25G_X4 20 3722 #define sc_x1_speed_override3_actualSpeeds_dr_10G_HiG_DXGXS 21 3723 #define sc_x1_speed_override3_actualSpeeds_dr_10G_DXGXS 22 3724 #define sc_x1_speed_override3_actualSpeeds_dr_10p5G_HiG_DXGXS 23 3725 #define sc_x1_speed_override3_actualSpeeds_dr_10p5G_DXGXS 24 3726 #define sc_x1_speed_override3_actualSpeeds_dr_12p773G_HiG_DXGXS 25 3727 #define sc_x1_speed_override3_actualSpeeds_dr_12p773G_DXGXS 26 3728 #define sc_x1_speed_override3_actualSpeeds_dr_10G_XFI 27 3729 #define sc_x1_speed_override3_actualSpeeds_dr_40G 28 3730 #define sc_x1_speed_override3_actualSpeeds_dr_20G_HiG_DXGXS 29 3731 #define sc_x1_speed_override3_actualSpeeds_dr_20G_DXGXS 30 3732 #define sc_x1_speed_override3_actualSpeeds_dr_10G_SFI 31 3733 #define sc_x1_speed_override3_actualSpeeds_dr_31p5G 32 3734 #define sc_x1_speed_override3_actualSpeeds_dr_32p7G 33 3735 #define sc_x1_speed_override3_actualSpeeds_dr_20G_SCR 34 3736 #define sc_x1_speed_override3_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 3737 #define sc_x1_speed_override3_actualSpeeds_dr_10G_DXGXS_SCR 36 3738 #define sc_x1_speed_override3_actualSpeeds_dr_12G_R2 37 3739 #define sc_x1_speed_override3_actualSpeeds_dr_10G_X2 38 3740 #define sc_x1_speed_override3_actualSpeeds_dr_40G_KR4 39 3741 #define sc_x1_speed_override3_actualSpeeds_dr_40G_CR4 40 3742 #define sc_x1_speed_override3_actualSpeeds_dr_100G_CR10 41 3743 #define sc_x1_speed_override3_actualSpeeds_dr_15p75G_DXGXS 44 3744 #define sc_x1_speed_override3_actualSpeeds_dr_20G_KR2 57 3745 #define sc_x1_speed_override3_actualSpeeds_dr_20G_CR2 58 3746 3747 /**************************************************************************** 3748 * Enums: sc_x1_speed_override3_actualSpeedsMisc1 3749 */ 3750 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_2500BRCM_X1 16 3751 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_5000BRCM_X4 17 3752 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_6000BRCM_X4 18 3753 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_10GHiGig_X4 19 3754 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_10GBASE_CX4 20 3755 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_12GHiGig_X4 21 3756 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 3757 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_13GHiGig_X4 23 3758 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_15GHiGig_X4 24 3759 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_16GHiGig_X4 25 3760 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_5000BRCM_X1 26 3761 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_6363BRCM_X1 27 3762 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_20GHiGig_X4 28 3763 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_21GHiGig_X4 29 3764 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 3765 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 3766 3767 /**************************************************************************** 3768 * Enums: sc_x1_speed_override3_IndLaneModes 3769 */ 3770 #define sc_x1_speed_override3_IndLaneModes_SWSDR_div2 0 3771 #define sc_x1_speed_override3_IndLaneModes_SWSDR_div1 1 3772 #define sc_x1_speed_override3_IndLaneModes_DWSDR_div2 2 3773 #define sc_x1_speed_override3_IndLaneModes_DWSDR_div1 3 3774 3775 /**************************************************************************** 3776 * Enums: sc_x1_speed_override3_prbsSelect 3777 */ 3778 #define sc_x1_speed_override3_prbsSelect_prbs7 0 3779 #define sc_x1_speed_override3_prbsSelect_prbs15 1 3780 #define sc_x1_speed_override3_prbsSelect_prbs23 2 3781 #define sc_x1_speed_override3_prbsSelect_prbs31 3 3782 3783 /**************************************************************************** 3784 * Enums: sc_x1_speed_override3_vcoDivider 3785 */ 3786 #define sc_x1_speed_override3_vcoDivider_div32 0 3787 #define sc_x1_speed_override3_vcoDivider_div36 1 3788 #define sc_x1_speed_override3_vcoDivider_div40 2 3789 #define sc_x1_speed_override3_vcoDivider_div42 3 3790 #define sc_x1_speed_override3_vcoDivider_div48 4 3791 #define sc_x1_speed_override3_vcoDivider_div50 5 3792 #define sc_x1_speed_override3_vcoDivider_div52 6 3793 #define sc_x1_speed_override3_vcoDivider_div54 7 3794 #define sc_x1_speed_override3_vcoDivider_div60 8 3795 #define sc_x1_speed_override3_vcoDivider_div64 9 3796 #define sc_x1_speed_override3_vcoDivider_div66 10 3797 #define sc_x1_speed_override3_vcoDivider_div68 11 3798 #define sc_x1_speed_override3_vcoDivider_div70 12 3799 #define sc_x1_speed_override3_vcoDivider_div80 13 3800 #define sc_x1_speed_override3_vcoDivider_div92 14 3801 #define sc_x1_speed_override3_vcoDivider_div100 15 3802 3803 /**************************************************************************** 3804 * Enums: sc_x1_speed_override3_refClkSelect 3805 */ 3806 #define sc_x1_speed_override3_refClkSelect_clk_25MHz 0 3807 #define sc_x1_speed_override3_refClkSelect_clk_100MHz 1 3808 #define sc_x1_speed_override3_refClkSelect_clk_125MHz 2 3809 #define sc_x1_speed_override3_refClkSelect_clk_156p25MHz 3 3810 #define sc_x1_speed_override3_refClkSelect_clk_187p5MHz 4 3811 #define sc_x1_speed_override3_refClkSelect_clk_161p25Mhz 5 3812 #define sc_x1_speed_override3_refClkSelect_clk_50Mhz 6 3813 #define sc_x1_speed_override3_refClkSelect_clk_106p25Mhz 7 3814 3815 /**************************************************************************** 3816 * Enums: sc_x1_speed_override3_aerMMDdevTypeSelect 3817 */ 3818 #define sc_x1_speed_override3_aerMMDdevTypeSelect_combo_core 0 3819 #define sc_x1_speed_override3_aerMMDdevTypeSelect_PMA_PMD 1 3820 #define sc_x1_speed_override3_aerMMDdevTypeSelect_PCS 3 3821 #define sc_x1_speed_override3_aerMMDdevTypeSelect_PHY 4 3822 #define sc_x1_speed_override3_aerMMDdevTypeSelect_DTE 5 3823 #define sc_x1_speed_override3_aerMMDdevTypeSelect_CL73_AN 7 3824 3825 /**************************************************************************** 3826 * Enums: sc_x1_speed_override3_aerMMDportSelect 3827 */ 3828 #define sc_x1_speed_override3_aerMMDportSelect_ln0 0 3829 #define sc_x1_speed_override3_aerMMDportSelect_ln1 1 3830 #define sc_x1_speed_override3_aerMMDportSelect_ln2 2 3831 #define sc_x1_speed_override3_aerMMDportSelect_ln3 3 3832 #define sc_x1_speed_override3_aerMMDportSelect_BCST_ln0_1_2_3 511 3833 #define sc_x1_speed_override3_aerMMDportSelect_BCST_ln0_1 512 3834 #define sc_x1_speed_override3_aerMMDportSelect_BCST_ln2_3 513 3835 3836 /**************************************************************************** 3837 * Enums: sc_x1_speed_override3_firmwareModeSelect 3838 */ 3839 #define sc_x1_speed_override3_firmwareModeSelect_DEFAULT 0 3840 #define sc_x1_speed_override3_firmwareModeSelect_SFP_OPT_LR 1 3841 #define sc_x1_speed_override3_firmwareModeSelect_SFP_DAC 2 3842 #define sc_x1_speed_override3_firmwareModeSelect_XLAUI 3 3843 #define sc_x1_speed_override3_firmwareModeSelect_LONG_CH_6G 4 3844 3845 /**************************************************************************** 3846 * Enums: sc_x1_speed_override3_tempIdxSelect 3847 */ 3848 #define sc_x1_speed_override3_tempIdxSelect_LTE__22p9C 15 3849 #define sc_x1_speed_override3_tempIdxSelect_LTE__12p6C 14 3850 #define sc_x1_speed_override3_tempIdxSelect_LTE__3p0C 13 3851 #define sc_x1_speed_override3_tempIdxSelect_LTE_6p7C 12 3852 #define sc_x1_speed_override3_tempIdxSelect_LTE_16p4C 11 3853 #define sc_x1_speed_override3_tempIdxSelect_LTE_26p6C 10 3854 #define sc_x1_speed_override3_tempIdxSelect_LTE_36p3C 9 3855 #define sc_x1_speed_override3_tempIdxSelect_LTE_46p0C 8 3856 #define sc_x1_speed_override3_tempIdxSelect_LTE_56p2C 7 3857 #define sc_x1_speed_override3_tempIdxSelect_LTE_65p9C 6 3858 #define sc_x1_speed_override3_tempIdxSelect_LTE_75p6C 5 3859 #define sc_x1_speed_override3_tempIdxSelect_LTE_85p3C 4 3860 #define sc_x1_speed_override3_tempIdxSelect_LTE_95p5C 3 3861 #define sc_x1_speed_override3_tempIdxSelect_LTE_105p2C 2 3862 #define sc_x1_speed_override3_tempIdxSelect_LTE_114p9C 1 3863 #define sc_x1_speed_override3_tempIdxSelect_LTE_125p1C 0 3864 3865 /**************************************************************************** 3866 * Enums: sc_x4_control_cl36TxEEEStates_l 3867 */ 3868 #define sc_x4_control_cl36TxEEEStates_l_TX_REFRESH 8 3869 #define sc_x4_control_cl36TxEEEStates_l_TX_QUIET 4 3870 #define sc_x4_control_cl36TxEEEStates_l_TX_SLEEP 2 3871 #define sc_x4_control_cl36TxEEEStates_l_TX_ACTIVE 1 3872 3873 /**************************************************************************** 3874 * Enums: sc_x4_control_cl36TxEEEStates_c 3875 */ 3876 #define sc_x4_control_cl36TxEEEStates_c_TX_REFRESH 3 3877 #define sc_x4_control_cl36TxEEEStates_c_TX_QUIET 2 3878 #define sc_x4_control_cl36TxEEEStates_c_TX_SLEEP 1 3879 #define sc_x4_control_cl36TxEEEStates_c_TX_ACTIVE 0 3880 3881 /**************************************************************************** 3882 * Enums: sc_x4_control_cl49TxEEEStates_l 3883 */ 3884 #define sc_x4_control_cl49TxEEEStates_l_SCR_RESET_2 64 3885 #define sc_x4_control_cl49TxEEEStates_l_SCR_RESET_1 32 3886 #define sc_x4_control_cl49TxEEEStates_l_TX_WAKE 16 3887 #define sc_x4_control_cl49TxEEEStates_l_TX_REFRESH 8 3888 #define sc_x4_control_cl49TxEEEStates_l_TX_QUIET 4 3889 #define sc_x4_control_cl49TxEEEStates_l_TX_SLEEP 2 3890 #define sc_x4_control_cl49TxEEEStates_l_TX_ACTIVE 1 3891 3892 /**************************************************************************** 3893 * Enums: sc_x4_control_cl49TxEEEStates_c 3894 */ 3895 #define sc_x4_control_cl49TxEEEStates_c_SCR_RESET_2 6 3896 #define sc_x4_control_cl49TxEEEStates_c_SCR_RESET_1 5 3897 #define sc_x4_control_cl49TxEEEStates_c_TX_WAKE 4 3898 #define sc_x4_control_cl49TxEEEStates_c_TX_REFRESH 3 3899 #define sc_x4_control_cl49TxEEEStates_c_TX_QUIET 2 3900 #define sc_x4_control_cl49TxEEEStates_c_TX_SLEEP 1 3901 #define sc_x4_control_cl49TxEEEStates_c_TX_ACTIVE 0 3902 3903 /**************************************************************************** 3904 * Enums: sc_x4_control_cl36RxEEEStates_l 3905 */ 3906 #define sc_x4_control_cl36RxEEEStates_l_RX_LINK_FAIL 32 3907 #define sc_x4_control_cl36RxEEEStates_l_RX_WTF 16 3908 #define sc_x4_control_cl36RxEEEStates_l_RX_WAKE 8 3909 #define sc_x4_control_cl36RxEEEStates_l_RX_QUIET 4 3910 #define sc_x4_control_cl36RxEEEStates_l_RX_SLEEP 2 3911 #define sc_x4_control_cl36RxEEEStates_l_RX_ACTIVE 1 3912 3913 /**************************************************************************** 3914 * Enums: sc_x4_control_cl36RxEEEStates_c 3915 */ 3916 #define sc_x4_control_cl36RxEEEStates_c_RX_LINK_FAIL 5 3917 #define sc_x4_control_cl36RxEEEStates_c_RX_WTF 4 3918 #define sc_x4_control_cl36RxEEEStates_c_RX_WAKE 3 3919 #define sc_x4_control_cl36RxEEEStates_c_RX_QUIET 2 3920 #define sc_x4_control_cl36RxEEEStates_c_RX_SLEEP 1 3921 #define sc_x4_control_cl36RxEEEStates_c_RX_ACTIVE 0 3922 3923 /**************************************************************************** 3924 * Enums: sc_x4_control_cl49RxEEEStates_l 3925 */ 3926 #define sc_x4_control_cl49RxEEEStates_l_RX_LINK_FAIL 32 3927 #define sc_x4_control_cl49RxEEEStates_l_RX_WTF 16 3928 #define sc_x4_control_cl49RxEEEStates_l_RX_WAKE 8 3929 #define sc_x4_control_cl49RxEEEStates_l_RX_QUIET 4 3930 #define sc_x4_control_cl49RxEEEStates_l_RX_SLEEP 2 3931 #define sc_x4_control_cl49RxEEEStates_l_RX_ACTIVE 1 3932 3933 /**************************************************************************** 3934 * Enums: sc_x4_control_cl49RxEEEStates_c 3935 */ 3936 #define sc_x4_control_cl49RxEEEStates_c_RX_LINK_FAIL 5 3937 #define sc_x4_control_cl49RxEEEStates_c_RX_WTF 4 3938 #define sc_x4_control_cl49RxEEEStates_c_RX_WAKE 3 3939 #define sc_x4_control_cl49RxEEEStates_c_RX_QUIET 2 3940 #define sc_x4_control_cl49RxEEEStates_c_RX_SLEEP 1 3941 #define sc_x4_control_cl49RxEEEStates_c_RX_ACTIVE 0 3942 3943 /**************************************************************************** 3944 * Enums: sc_x4_control_cl48TxEEEStates_l 3945 */ 3946 #define sc_x4_control_cl48TxEEEStates_l_TX_REFRESH 8 3947 #define sc_x4_control_cl48TxEEEStates_l_TX_QUIET 4 3948 #define sc_x4_control_cl48TxEEEStates_l_TX_SLEEP 2 3949 #define sc_x4_control_cl48TxEEEStates_l_TX_ACTIVE 1 3950 3951 /**************************************************************************** 3952 * Enums: sc_x4_control_cl48TxEEEStates_c 3953 */ 3954 #define sc_x4_control_cl48TxEEEStates_c_TX_REFRESH 3 3955 #define sc_x4_control_cl48TxEEEStates_c_TX_QUIET 2 3956 #define sc_x4_control_cl48TxEEEStates_c_TX_SLEEP 1 3957 #define sc_x4_control_cl48TxEEEStates_c_TX_ACTIVE 0 3958 3959 /**************************************************************************** 3960 * Enums: sc_x4_control_cl48RxEEEStates_l 3961 */ 3962 #define sc_x4_control_cl48RxEEEStates_l_RX_LINK_FAIL 32 3963 #define sc_x4_control_cl48RxEEEStates_l_RX_WAKE 16 3964 #define sc_x4_control_cl48RxEEEStates_l_RX_QUIET 8 3965 #define sc_x4_control_cl48RxEEEStates_l_RX_DEACT 4 3966 #define sc_x4_control_cl48RxEEEStates_l_RX_SLEEP 2 3967 #define sc_x4_control_cl48RxEEEStates_l_RX_ACTIVE 1 3968 3969 /**************************************************************************** 3970 * Enums: sc_x4_control_cl48RxEEEStates_c 3971 */ 3972 #define sc_x4_control_cl48RxEEEStates_c_RX_LINK_FAIL 5 3973 #define sc_x4_control_cl48RxEEEStates_c_RX_WAKE 4 3974 #define sc_x4_control_cl48RxEEEStates_c_RX_QUIET 3 3975 #define sc_x4_control_cl48RxEEEStates_c_RX_DEACT 2 3976 #define sc_x4_control_cl48RxEEEStates_c_RX_SLEEP 1 3977 #define sc_x4_control_cl48RxEEEStates_c_RX_ACTIVE 0 3978 3979 /**************************************************************************** 3980 * Enums: sc_x4_control_IQP_Options 3981 */ 3982 #define sc_x4_control_IQP_Options_i50uA 0 3983 #define sc_x4_control_IQP_Options_i100uA 1 3984 #define sc_x4_control_IQP_Options_i150uA 2 3985 #define sc_x4_control_IQP_Options_i200uA 3 3986 #define sc_x4_control_IQP_Options_i250uA 4 3987 #define sc_x4_control_IQP_Options_i300uA 5 3988 #define sc_x4_control_IQP_Options_i350uA 6 3989 #define sc_x4_control_IQP_Options_i400uA 7 3990 #define sc_x4_control_IQP_Options_i450uA 8 3991 #define sc_x4_control_IQP_Options_i500uA 9 3992 #define sc_x4_control_IQP_Options_i550uA 10 3993 #define sc_x4_control_IQP_Options_i600uA 11 3994 #define sc_x4_control_IQP_Options_i650uA 12 3995 #define sc_x4_control_IQP_Options_i700uA 13 3996 #define sc_x4_control_IQP_Options_i750uA 14 3997 #define sc_x4_control_IQP_Options_i800uA 15 3998 3999 /**************************************************************************** 4000 * Enums: sc_x4_control_IDriver_Options 4001 */ 4002 #define sc_x4_control_IDriver_Options_v680mV 0 4003 #define sc_x4_control_IDriver_Options_v730mV 1 4004 #define sc_x4_control_IDriver_Options_v780mV 2 4005 #define sc_x4_control_IDriver_Options_v830mV 3 4006 #define sc_x4_control_IDriver_Options_v880mV 4 4007 #define sc_x4_control_IDriver_Options_v930mV 5 4008 #define sc_x4_control_IDriver_Options_v980mV 6 4009 #define sc_x4_control_IDriver_Options_v1010mV 7 4010 #define sc_x4_control_IDriver_Options_v1040mV 8 4011 #define sc_x4_control_IDriver_Options_v1060mV 9 4012 #define sc_x4_control_IDriver_Options_v1070mV 10 4013 #define sc_x4_control_IDriver_Options_v1080mV 11 4014 #define sc_x4_control_IDriver_Options_v1085mV 12 4015 #define sc_x4_control_IDriver_Options_v1090mV 13 4016 #define sc_x4_control_IDriver_Options_v1095mV 14 4017 #define sc_x4_control_IDriver_Options_v1100mV 15 4018 4019 /**************************************************************************** 4020 * Enums: sc_x4_control_operationModes 4021 */ 4022 #define sc_x4_control_operationModes_XGXS 0 4023 #define sc_x4_control_operationModes_XGXG_nCC 1 4024 #define sc_x4_control_operationModes_Indlane_OS8 4 4025 #define sc_x4_control_operationModes_IndLane_OS5 5 4026 #define sc_x4_control_operationModes_PCI 7 4027 #define sc_x4_control_operationModes_XGXS_nLQ 8 4028 #define sc_x4_control_operationModes_XGXS_nLQnCC 9 4029 #define sc_x4_control_operationModes_PBypass 10 4030 #define sc_x4_control_operationModes_PBypass_nDSK 11 4031 #define sc_x4_control_operationModes_ComboCoreMode 12 4032 #define sc_x4_control_operationModes_Clocks_off 15 4033 4034 /**************************************************************************** 4035 * Enums: sc_x4_control_synce_enum 4036 */ 4037 #define sc_x4_control_synce_enum_SYNCE_NO_DIV 0 4038 #define sc_x4_control_synce_enum_SYNCE_DIV_7 1 4039 #define sc_x4_control_synce_enum_SYNCE_DIV_11 2 4040 #define sc_x4_control_synce_enum_SYNCE_DIV_10 3 4041 4042 /**************************************************************************** 4043 * Enums: sc_x4_control_synce_enum_stage0 4044 */ 4045 #define sc_x4_control_synce_enum_stage0_SYNCE_NO_DIV 0 4046 #define sc_x4_control_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 4047 #define sc_x4_control_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 4048 4049 /**************************************************************************** 4050 * Enums: sc_x4_control_operationSpeeds 4051 */ 4052 #define sc_x4_control_operationSpeeds_SPEED_10G_X4_10p3125 59 4053 #define sc_x4_control_operationSpeeds_SPEED_10G_CX4_10p3125 58 4054 #define sc_x4_control_operationSpeeds_SPEED_10G_KX4_10p3125 57 4055 #define sc_x4_control_operationSpeeds_SPEED_2p5G_X1_10p3125 56 4056 #define sc_x4_control_operationSpeeds_SPEED_1000M_10p3125 55 4057 #define sc_x4_control_operationSpeeds_SPEED_100M_10p3125 54 4058 #define sc_x4_control_operationSpeeds_SPEED_10M_10p3125 53 4059 #define sc_x4_control_operationSpeeds_SPEED_10p5G_X4 50 4060 #define sc_x4_control_operationSpeeds_SPEED_5G_KR1 49 4061 #define sc_x4_control_operationSpeeds_SPEED_42p42G_X4 44 4062 #define sc_x4_control_operationSpeeds_SPEED_21p21G_X2 43 4063 #define sc_x4_control_operationSpeeds_SPEED_48p48G_X4 42 4064 #define sc_x4_control_operationSpeeds_SPEED_24p24G_X2 41 4065 #define sc_x4_control_operationSpeeds_SPEED_12p12G_X1 40 4066 #define sc_x4_control_operationSpeeds_SPEED_127G_X12 39 4067 #define sc_x4_control_operationSpeeds_SPEED_120G_X12 38 4068 #define sc_x4_control_operationSpeeds_SPEED_107G_X10 37 4069 #define sc_x4_control_operationSpeeds_SPEED_100G_CR10 36 4070 #define sc_x4_control_operationSpeeds_SPEED_42G_X4 35 4071 #define sc_x4_control_operationSpeeds_SPEED_40G_CR4 34 4072 #define sc_x4_control_operationSpeeds_SPEED_40G_KR4 33 4073 #define sc_x4_control_operationSpeeds_SPEED_21G_X2 32 4074 #define sc_x4_control_operationSpeeds_SPEED_20G_CR2 31 4075 #define sc_x4_control_operationSpeeds_SPEED_20G_KR2 30 4076 #define sc_x4_control_operationSpeeds_SPEED_10p6_X1 29 4077 #define sc_x4_control_operationSpeeds_SPEED_10G_KR1 28 4078 #define sc_x4_control_operationSpeeds_SPEED_40G_X4 27 4079 #define sc_x4_control_operationSpeeds_SPEED_20G_X2 26 4080 #define sc_x4_control_operationSpeeds_SPEED_20G_CX2 25 4081 #define sc_x4_control_operationSpeeds_SPEED_31p5G_KR4 24 4082 #define sc_x4_control_operationSpeeds_SPEED_31p5G_X4 23 4083 #define sc_x4_control_operationSpeeds_SPEED_15p75G_X2 22 4084 #define sc_x4_control_operationSpeeds_SPEED_25p45G_X4 21 4085 #define sc_x4_control_operationSpeeds_SPEED_12p7G_X2 20 4086 #define sc_x4_control_operationSpeeds_SPEED_21G_X4 19 4087 #define sc_x4_control_operationSpeeds_SPEED_10p5G_X2 18 4088 #define sc_x4_control_operationSpeeds_SPEED_20G_X4 17 4089 #define sc_x4_control_operationSpeeds_SPEED_10G_X2 16 4090 #define sc_x4_control_operationSpeeds_SPEED_10G_CX2 15 4091 #define sc_x4_control_operationSpeeds_SPEED_20G_CX4 14 4092 #define sc_x4_control_operationSpeeds_SPEED_16G_X4 13 4093 #define sc_x4_control_operationSpeeds_SPEED_15G_X4 12 4094 #define sc_x4_control_operationSpeeds_SPEED_13G_X4 11 4095 #define sc_x4_control_operationSpeeds_SPEED_10G_X4 10 4096 #define sc_x4_control_operationSpeeds_SPEED_10G_KX4 9 4097 #define sc_x4_control_operationSpeeds_SPEED_10G_CX4 8 4098 #define sc_x4_control_operationSpeeds_SPEED_5G_X1 7 4099 #define sc_x4_control_operationSpeeds_SPEED_2p5G_X1 6 4100 #define sc_x4_control_operationSpeeds_SPEED_1G_KX1 5 4101 #define sc_x4_control_operationSpeeds_SPEED_1G_CX1 4 4102 #define sc_x4_control_operationSpeeds_SPEED_1000M 3 4103 #define sc_x4_control_operationSpeeds_SPEED_100M 2 4104 #define sc_x4_control_operationSpeeds_SPEED_10M 1 4105 4106 /**************************************************************************** 4107 * Enums: sc_x4_control_actualSpeeds 4108 */ 4109 #define sc_x4_control_actualSpeeds_dr_10M 0 4110 #define sc_x4_control_actualSpeeds_dr_100M 1 4111 #define sc_x4_control_actualSpeeds_dr_1G 2 4112 #define sc_x4_control_actualSpeeds_dr_2p5G 3 4113 #define sc_x4_control_actualSpeeds_dr_5G_X4 4 4114 #define sc_x4_control_actualSpeeds_dr_6G_X4 5 4115 #define sc_x4_control_actualSpeeds_dr_10G_HiG 6 4116 #define sc_x4_control_actualSpeeds_dr_10G_CX4 7 4117 #define sc_x4_control_actualSpeeds_dr_12G_HiG 8 4118 #define sc_x4_control_actualSpeeds_dr_12p5G_X4 9 4119 #define sc_x4_control_actualSpeeds_dr_13G_X4 10 4120 #define sc_x4_control_actualSpeeds_dr_15G_X4 11 4121 #define sc_x4_control_actualSpeeds_dr_16G_X4 12 4122 #define sc_x4_control_actualSpeeds_dr_1G_KX 13 4123 #define sc_x4_control_actualSpeeds_dr_10G_KX4 14 4124 #define sc_x4_control_actualSpeeds_dr_10G_KR 15 4125 #define sc_x4_control_actualSpeeds_dr_5G 16 4126 #define sc_x4_control_actualSpeeds_dr_6p4G 17 4127 #define sc_x4_control_actualSpeeds_dr_20G_X4 18 4128 #define sc_x4_control_actualSpeeds_dr_21G_X4 19 4129 #define sc_x4_control_actualSpeeds_dr_25G_X4 20 4130 #define sc_x4_control_actualSpeeds_dr_10G_HiG_DXGXS 21 4131 #define sc_x4_control_actualSpeeds_dr_10G_DXGXS 22 4132 #define sc_x4_control_actualSpeeds_dr_10p5G_HiG_DXGXS 23 4133 #define sc_x4_control_actualSpeeds_dr_10p5G_DXGXS 24 4134 #define sc_x4_control_actualSpeeds_dr_12p773G_HiG_DXGXS 25 4135 #define sc_x4_control_actualSpeeds_dr_12p773G_DXGXS 26 4136 #define sc_x4_control_actualSpeeds_dr_10G_XFI 27 4137 #define sc_x4_control_actualSpeeds_dr_40G 28 4138 #define sc_x4_control_actualSpeeds_dr_20G_HiG_DXGXS 29 4139 #define sc_x4_control_actualSpeeds_dr_20G_DXGXS 30 4140 #define sc_x4_control_actualSpeeds_dr_10G_SFI 31 4141 #define sc_x4_control_actualSpeeds_dr_31p5G 32 4142 #define sc_x4_control_actualSpeeds_dr_32p7G 33 4143 #define sc_x4_control_actualSpeeds_dr_20G_SCR 34 4144 #define sc_x4_control_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 4145 #define sc_x4_control_actualSpeeds_dr_10G_DXGXS_SCR 36 4146 #define sc_x4_control_actualSpeeds_dr_12G_R2 37 4147 #define sc_x4_control_actualSpeeds_dr_10G_X2 38 4148 #define sc_x4_control_actualSpeeds_dr_40G_KR4 39 4149 #define sc_x4_control_actualSpeeds_dr_40G_CR4 40 4150 #define sc_x4_control_actualSpeeds_dr_100G_CR10 41 4151 #define sc_x4_control_actualSpeeds_dr_15p75G_DXGXS 44 4152 #define sc_x4_control_actualSpeeds_dr_20G_KR2 57 4153 #define sc_x4_control_actualSpeeds_dr_20G_CR2 58 4154 4155 /**************************************************************************** 4156 * Enums: sc_x4_control_actualSpeedsMisc1 4157 */ 4158 #define sc_x4_control_actualSpeedsMisc1_dr_2500BRCM_X1 16 4159 #define sc_x4_control_actualSpeedsMisc1_dr_5000BRCM_X4 17 4160 #define sc_x4_control_actualSpeedsMisc1_dr_6000BRCM_X4 18 4161 #define sc_x4_control_actualSpeedsMisc1_dr_10GHiGig_X4 19 4162 #define sc_x4_control_actualSpeedsMisc1_dr_10GBASE_CX4 20 4163 #define sc_x4_control_actualSpeedsMisc1_dr_12GHiGig_X4 21 4164 #define sc_x4_control_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 4165 #define sc_x4_control_actualSpeedsMisc1_dr_13GHiGig_X4 23 4166 #define sc_x4_control_actualSpeedsMisc1_dr_15GHiGig_X4 24 4167 #define sc_x4_control_actualSpeedsMisc1_dr_16GHiGig_X4 25 4168 #define sc_x4_control_actualSpeedsMisc1_dr_5000BRCM_X1 26 4169 #define sc_x4_control_actualSpeedsMisc1_dr_6363BRCM_X1 27 4170 #define sc_x4_control_actualSpeedsMisc1_dr_20GHiGig_X4 28 4171 #define sc_x4_control_actualSpeedsMisc1_dr_21GHiGig_X4 29 4172 #define sc_x4_control_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 4173 #define sc_x4_control_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 4174 4175 /**************************************************************************** 4176 * Enums: sc_x4_control_IndLaneModes 4177 */ 4178 #define sc_x4_control_IndLaneModes_SWSDR_div2 0 4179 #define sc_x4_control_IndLaneModes_SWSDR_div1 1 4180 #define sc_x4_control_IndLaneModes_DWSDR_div2 2 4181 #define sc_x4_control_IndLaneModes_DWSDR_div1 3 4182 4183 /**************************************************************************** 4184 * Enums: sc_x4_control_prbsSelect 4185 */ 4186 #define sc_x4_control_prbsSelect_prbs7 0 4187 #define sc_x4_control_prbsSelect_prbs15 1 4188 #define sc_x4_control_prbsSelect_prbs23 2 4189 #define sc_x4_control_prbsSelect_prbs31 3 4190 4191 /**************************************************************************** 4192 * Enums: sc_x4_control_vcoDivider 4193 */ 4194 #define sc_x4_control_vcoDivider_div32 0 4195 #define sc_x4_control_vcoDivider_div36 1 4196 #define sc_x4_control_vcoDivider_div40 2 4197 #define sc_x4_control_vcoDivider_div42 3 4198 #define sc_x4_control_vcoDivider_div48 4 4199 #define sc_x4_control_vcoDivider_div50 5 4200 #define sc_x4_control_vcoDivider_div52 6 4201 #define sc_x4_control_vcoDivider_div54 7 4202 #define sc_x4_control_vcoDivider_div60 8 4203 #define sc_x4_control_vcoDivider_div64 9 4204 #define sc_x4_control_vcoDivider_div66 10 4205 #define sc_x4_control_vcoDivider_div68 11 4206 #define sc_x4_control_vcoDivider_div70 12 4207 #define sc_x4_control_vcoDivider_div80 13 4208 #define sc_x4_control_vcoDivider_div92 14 4209 #define sc_x4_control_vcoDivider_div100 15 4210 4211 /**************************************************************************** 4212 * Enums: sc_x4_control_refClkSelect 4213 */ 4214 #define sc_x4_control_refClkSelect_clk_25MHz 0 4215 #define sc_x4_control_refClkSelect_clk_100MHz 1 4216 #define sc_x4_control_refClkSelect_clk_125MHz 2 4217 #define sc_x4_control_refClkSelect_clk_156p25MHz 3 4218 #define sc_x4_control_refClkSelect_clk_187p5MHz 4 4219 #define sc_x4_control_refClkSelect_clk_161p25Mhz 5 4220 #define sc_x4_control_refClkSelect_clk_50Mhz 6 4221 #define sc_x4_control_refClkSelect_clk_106p25Mhz 7 4222 4223 /**************************************************************************** 4224 * Enums: sc_x4_control_aerMMDdevTypeSelect 4225 */ 4226 #define sc_x4_control_aerMMDdevTypeSelect_combo_core 0 4227 #define sc_x4_control_aerMMDdevTypeSelect_PMA_PMD 1 4228 #define sc_x4_control_aerMMDdevTypeSelect_PCS 3 4229 #define sc_x4_control_aerMMDdevTypeSelect_PHY 4 4230 #define sc_x4_control_aerMMDdevTypeSelect_DTE 5 4231 #define sc_x4_control_aerMMDdevTypeSelect_CL73_AN 7 4232 4233 /**************************************************************************** 4234 * Enums: sc_x4_control_aerMMDportSelect 4235 */ 4236 #define sc_x4_control_aerMMDportSelect_ln0 0 4237 #define sc_x4_control_aerMMDportSelect_ln1 1 4238 #define sc_x4_control_aerMMDportSelect_ln2 2 4239 #define sc_x4_control_aerMMDportSelect_ln3 3 4240 #define sc_x4_control_aerMMDportSelect_BCST_ln0_1_2_3 511 4241 #define sc_x4_control_aerMMDportSelect_BCST_ln0_1 512 4242 #define sc_x4_control_aerMMDportSelect_BCST_ln2_3 513 4243 4244 /**************************************************************************** 4245 * Enums: sc_x4_control_firmwareModeSelect 4246 */ 4247 #define sc_x4_control_firmwareModeSelect_DEFAULT 0 4248 #define sc_x4_control_firmwareModeSelect_SFP_OPT_LR 1 4249 #define sc_x4_control_firmwareModeSelect_SFP_DAC 2 4250 #define sc_x4_control_firmwareModeSelect_XLAUI 3 4251 #define sc_x4_control_firmwareModeSelect_LONG_CH_6G 4 4252 4253 /**************************************************************************** 4254 * Enums: sc_x4_control_tempIdxSelect 4255 */ 4256 #define sc_x4_control_tempIdxSelect_LTE__22p9C 15 4257 #define sc_x4_control_tempIdxSelect_LTE__12p6C 14 4258 #define sc_x4_control_tempIdxSelect_LTE__3p0C 13 4259 #define sc_x4_control_tempIdxSelect_LTE_6p7C 12 4260 #define sc_x4_control_tempIdxSelect_LTE_16p4C 11 4261 #define sc_x4_control_tempIdxSelect_LTE_26p6C 10 4262 #define sc_x4_control_tempIdxSelect_LTE_36p3C 9 4263 #define sc_x4_control_tempIdxSelect_LTE_46p0C 8 4264 #define sc_x4_control_tempIdxSelect_LTE_56p2C 7 4265 #define sc_x4_control_tempIdxSelect_LTE_65p9C 6 4266 #define sc_x4_control_tempIdxSelect_LTE_75p6C 5 4267 #define sc_x4_control_tempIdxSelect_LTE_85p3C 4 4268 #define sc_x4_control_tempIdxSelect_LTE_95p5C 3 4269 #define sc_x4_control_tempIdxSelect_LTE_105p2C 2 4270 #define sc_x4_control_tempIdxSelect_LTE_114p9C 1 4271 #define sc_x4_control_tempIdxSelect_LTE_125p1C 0 4272 4273 /**************************************************************************** 4274 * Enums: sc_x4_control_sc_seq_status 4275 */ 4276 #define sc_x4_control_sc_seq_status_START 32768 4277 #define sc_x4_control_sc_seq_status_RESET_PCS 16384 4278 #define sc_x4_control_sc_seq_status_RESET_PMD_LANE 8192 4279 #define sc_x4_control_sc_seq_status_RESET_PMD_PLL 4096 4280 #define sc_x4_control_sc_seq_status_APPLY_SPEED_CFG 2048 4281 #define sc_x4_control_sc_seq_status_WAIT_CFG_DONE 1024 4282 #define sc_x4_control_sc_seq_status_ACTIVATE_PMD 512 4283 #define sc_x4_control_sc_seq_status_WAIT_PLL_RESET 256 4284 #define sc_x4_control_sc_seq_status_PLL_LOCK_FAIL 128 4285 #define sc_x4_control_sc_seq_status_ACTIVATE_TX 64 4286 #define sc_x4_control_sc_seq_status_WAIT_PMD_LOCK 32 4287 #define sc_x4_control_sc_seq_status_ACTIVATE_RX 16 4288 #define sc_x4_control_sc_seq_status_PMD_LOCK_FAIL 8 4289 #define sc_x4_control_sc_seq_status_DONE 4 4290 #define sc_x4_control_sc_seq_status_STOP 2 4291 #define sc_x4_control_sc_seq_status_BYPASS 1 4292 4293 /**************************************************************************** 4294 * Enums: sc_x4_final_config_status_cl36TxEEEStates_l 4295 */ 4296 #define sc_x4_final_config_status_cl36TxEEEStates_l_TX_REFRESH 8 4297 #define sc_x4_final_config_status_cl36TxEEEStates_l_TX_QUIET 4 4298 #define sc_x4_final_config_status_cl36TxEEEStates_l_TX_SLEEP 2 4299 #define sc_x4_final_config_status_cl36TxEEEStates_l_TX_ACTIVE 1 4300 4301 /**************************************************************************** 4302 * Enums: sc_x4_final_config_status_cl36TxEEEStates_c 4303 */ 4304 #define sc_x4_final_config_status_cl36TxEEEStates_c_TX_REFRESH 3 4305 #define sc_x4_final_config_status_cl36TxEEEStates_c_TX_QUIET 2 4306 #define sc_x4_final_config_status_cl36TxEEEStates_c_TX_SLEEP 1 4307 #define sc_x4_final_config_status_cl36TxEEEStates_c_TX_ACTIVE 0 4308 4309 /**************************************************************************** 4310 * Enums: sc_x4_final_config_status_cl49TxEEEStates_l 4311 */ 4312 #define sc_x4_final_config_status_cl49TxEEEStates_l_SCR_RESET_2 64 4313 #define sc_x4_final_config_status_cl49TxEEEStates_l_SCR_RESET_1 32 4314 #define sc_x4_final_config_status_cl49TxEEEStates_l_TX_WAKE 16 4315 #define sc_x4_final_config_status_cl49TxEEEStates_l_TX_REFRESH 8 4316 #define sc_x4_final_config_status_cl49TxEEEStates_l_TX_QUIET 4 4317 #define sc_x4_final_config_status_cl49TxEEEStates_l_TX_SLEEP 2 4318 #define sc_x4_final_config_status_cl49TxEEEStates_l_TX_ACTIVE 1 4319 4320 /**************************************************************************** 4321 * Enums: sc_x4_final_config_status_cl49TxEEEStates_c 4322 */ 4323 #define sc_x4_final_config_status_cl49TxEEEStates_c_SCR_RESET_2 6 4324 #define sc_x4_final_config_status_cl49TxEEEStates_c_SCR_RESET_1 5 4325 #define sc_x4_final_config_status_cl49TxEEEStates_c_TX_WAKE 4 4326 #define sc_x4_final_config_status_cl49TxEEEStates_c_TX_REFRESH 3 4327 #define sc_x4_final_config_status_cl49TxEEEStates_c_TX_QUIET 2 4328 #define sc_x4_final_config_status_cl49TxEEEStates_c_TX_SLEEP 1 4329 #define sc_x4_final_config_status_cl49TxEEEStates_c_TX_ACTIVE 0 4330 4331 /**************************************************************************** 4332 * Enums: sc_x4_final_config_status_cl36RxEEEStates_l 4333 */ 4334 #define sc_x4_final_config_status_cl36RxEEEStates_l_RX_LINK_FAIL 32 4335 #define sc_x4_final_config_status_cl36RxEEEStates_l_RX_WTF 16 4336 #define sc_x4_final_config_status_cl36RxEEEStates_l_RX_WAKE 8 4337 #define sc_x4_final_config_status_cl36RxEEEStates_l_RX_QUIET 4 4338 #define sc_x4_final_config_status_cl36RxEEEStates_l_RX_SLEEP 2 4339 #define sc_x4_final_config_status_cl36RxEEEStates_l_RX_ACTIVE 1 4340 4341 /**************************************************************************** 4342 * Enums: sc_x4_final_config_status_cl36RxEEEStates_c 4343 */ 4344 #define sc_x4_final_config_status_cl36RxEEEStates_c_RX_LINK_FAIL 5 4345 #define sc_x4_final_config_status_cl36RxEEEStates_c_RX_WTF 4 4346 #define sc_x4_final_config_status_cl36RxEEEStates_c_RX_WAKE 3 4347 #define sc_x4_final_config_status_cl36RxEEEStates_c_RX_QUIET 2 4348 #define sc_x4_final_config_status_cl36RxEEEStates_c_RX_SLEEP 1 4349 #define sc_x4_final_config_status_cl36RxEEEStates_c_RX_ACTIVE 0 4350 4351 /**************************************************************************** 4352 * Enums: sc_x4_final_config_status_cl49RxEEEStates_l 4353 */ 4354 #define sc_x4_final_config_status_cl49RxEEEStates_l_RX_LINK_FAIL 32 4355 #define sc_x4_final_config_status_cl49RxEEEStates_l_RX_WTF 16 4356 #define sc_x4_final_config_status_cl49RxEEEStates_l_RX_WAKE 8 4357 #define sc_x4_final_config_status_cl49RxEEEStates_l_RX_QUIET 4 4358 #define sc_x4_final_config_status_cl49RxEEEStates_l_RX_SLEEP 2 4359 #define sc_x4_final_config_status_cl49RxEEEStates_l_RX_ACTIVE 1 4360 4361 /**************************************************************************** 4362 * Enums: sc_x4_final_config_status_cl49RxEEEStates_c 4363 */ 4364 #define sc_x4_final_config_status_cl49RxEEEStates_c_RX_LINK_FAIL 5 4365 #define sc_x4_final_config_status_cl49RxEEEStates_c_RX_WTF 4 4366 #define sc_x4_final_config_status_cl49RxEEEStates_c_RX_WAKE 3 4367 #define sc_x4_final_config_status_cl49RxEEEStates_c_RX_QUIET 2 4368 #define sc_x4_final_config_status_cl49RxEEEStates_c_RX_SLEEP 1 4369 #define sc_x4_final_config_status_cl49RxEEEStates_c_RX_ACTIVE 0 4370 4371 /**************************************************************************** 4372 * Enums: sc_x4_final_config_status_cl48TxEEEStates_l 4373 */ 4374 #define sc_x4_final_config_status_cl48TxEEEStates_l_TX_REFRESH 8 4375 #define sc_x4_final_config_status_cl48TxEEEStates_l_TX_QUIET 4 4376 #define sc_x4_final_config_status_cl48TxEEEStates_l_TX_SLEEP 2 4377 #define sc_x4_final_config_status_cl48TxEEEStates_l_TX_ACTIVE 1 4378 4379 /**************************************************************************** 4380 * Enums: sc_x4_final_config_status_cl48TxEEEStates_c 4381 */ 4382 #define sc_x4_final_config_status_cl48TxEEEStates_c_TX_REFRESH 3 4383 #define sc_x4_final_config_status_cl48TxEEEStates_c_TX_QUIET 2 4384 #define sc_x4_final_config_status_cl48TxEEEStates_c_TX_SLEEP 1 4385 #define sc_x4_final_config_status_cl48TxEEEStates_c_TX_ACTIVE 0 4386 4387 /**************************************************************************** 4388 * Enums: sc_x4_final_config_status_cl48RxEEEStates_l 4389 */ 4390 #define sc_x4_final_config_status_cl48RxEEEStates_l_RX_LINK_FAIL 32 4391 #define sc_x4_final_config_status_cl48RxEEEStates_l_RX_WAKE 16 4392 #define sc_x4_final_config_status_cl48RxEEEStates_l_RX_QUIET 8 4393 #define sc_x4_final_config_status_cl48RxEEEStates_l_RX_DEACT 4 4394 #define sc_x4_final_config_status_cl48RxEEEStates_l_RX_SLEEP 2 4395 #define sc_x4_final_config_status_cl48RxEEEStates_l_RX_ACTIVE 1 4396 4397 /**************************************************************************** 4398 * Enums: sc_x4_final_config_status_cl48RxEEEStates_c 4399 */ 4400 #define sc_x4_final_config_status_cl48RxEEEStates_c_RX_LINK_FAIL 5 4401 #define sc_x4_final_config_status_cl48RxEEEStates_c_RX_WAKE 4 4402 #define sc_x4_final_config_status_cl48RxEEEStates_c_RX_QUIET 3 4403 #define sc_x4_final_config_status_cl48RxEEEStates_c_RX_DEACT 2 4404 #define sc_x4_final_config_status_cl48RxEEEStates_c_RX_SLEEP 1 4405 #define sc_x4_final_config_status_cl48RxEEEStates_c_RX_ACTIVE 0 4406 4407 /**************************************************************************** 4408 * Enums: sc_x4_final_config_status_IQP_Options 4409 */ 4410 #define sc_x4_final_config_status_IQP_Options_i50uA 0 4411 #define sc_x4_final_config_status_IQP_Options_i100uA 1 4412 #define sc_x4_final_config_status_IQP_Options_i150uA 2 4413 #define sc_x4_final_config_status_IQP_Options_i200uA 3 4414 #define sc_x4_final_config_status_IQP_Options_i250uA 4 4415 #define sc_x4_final_config_status_IQP_Options_i300uA 5 4416 #define sc_x4_final_config_status_IQP_Options_i350uA 6 4417 #define sc_x4_final_config_status_IQP_Options_i400uA 7 4418 #define sc_x4_final_config_status_IQP_Options_i450uA 8 4419 #define sc_x4_final_config_status_IQP_Options_i500uA 9 4420 #define sc_x4_final_config_status_IQP_Options_i550uA 10 4421 #define sc_x4_final_config_status_IQP_Options_i600uA 11 4422 #define sc_x4_final_config_status_IQP_Options_i650uA 12 4423 #define sc_x4_final_config_status_IQP_Options_i700uA 13 4424 #define sc_x4_final_config_status_IQP_Options_i750uA 14 4425 #define sc_x4_final_config_status_IQP_Options_i800uA 15 4426 4427 /**************************************************************************** 4428 * Enums: sc_x4_final_config_status_IDriver_Options 4429 */ 4430 #define sc_x4_final_config_status_IDriver_Options_v680mV 0 4431 #define sc_x4_final_config_status_IDriver_Options_v730mV 1 4432 #define sc_x4_final_config_status_IDriver_Options_v780mV 2 4433 #define sc_x4_final_config_status_IDriver_Options_v830mV 3 4434 #define sc_x4_final_config_status_IDriver_Options_v880mV 4 4435 #define sc_x4_final_config_status_IDriver_Options_v930mV 5 4436 #define sc_x4_final_config_status_IDriver_Options_v980mV 6 4437 #define sc_x4_final_config_status_IDriver_Options_v1010mV 7 4438 #define sc_x4_final_config_status_IDriver_Options_v1040mV 8 4439 #define sc_x4_final_config_status_IDriver_Options_v1060mV 9 4440 #define sc_x4_final_config_status_IDriver_Options_v1070mV 10 4441 #define sc_x4_final_config_status_IDriver_Options_v1080mV 11 4442 #define sc_x4_final_config_status_IDriver_Options_v1085mV 12 4443 #define sc_x4_final_config_status_IDriver_Options_v1090mV 13 4444 #define sc_x4_final_config_status_IDriver_Options_v1095mV 14 4445 #define sc_x4_final_config_status_IDriver_Options_v1100mV 15 4446 4447 /**************************************************************************** 4448 * Enums: sc_x4_final_config_status_operationModes 4449 */ 4450 #define sc_x4_final_config_status_operationModes_XGXS 0 4451 #define sc_x4_final_config_status_operationModes_XGXG_nCC 1 4452 #define sc_x4_final_config_status_operationModes_Indlane_OS8 4 4453 #define sc_x4_final_config_status_operationModes_IndLane_OS5 5 4454 #define sc_x4_final_config_status_operationModes_PCI 7 4455 #define sc_x4_final_config_status_operationModes_XGXS_nLQ 8 4456 #define sc_x4_final_config_status_operationModes_XGXS_nLQnCC 9 4457 #define sc_x4_final_config_status_operationModes_PBypass 10 4458 #define sc_x4_final_config_status_operationModes_PBypass_nDSK 11 4459 #define sc_x4_final_config_status_operationModes_ComboCoreMode 12 4460 #define sc_x4_final_config_status_operationModes_Clocks_off 15 4461 4462 /**************************************************************************** 4463 * Enums: sc_x4_final_config_status_synce_enum 4464 */ 4465 #define sc_x4_final_config_status_synce_enum_SYNCE_NO_DIV 0 4466 #define sc_x4_final_config_status_synce_enum_SYNCE_DIV_7 1 4467 #define sc_x4_final_config_status_synce_enum_SYNCE_DIV_11 2 4468 #define sc_x4_final_config_status_synce_enum_SYNCE_DIV_10 3 4469 4470 /**************************************************************************** 4471 * Enums: sc_x4_final_config_status_synce_enum_stage0 4472 */ 4473 #define sc_x4_final_config_status_synce_enum_stage0_SYNCE_NO_DIV 0 4474 #define sc_x4_final_config_status_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 4475 #define sc_x4_final_config_status_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 4476 4477 /**************************************************************************** 4478 * Enums: sc_x4_final_config_status_operationSpeeds 4479 */ 4480 #define sc_x4_final_config_status_operationSpeeds_SPEED_10G_X4_10p3125 59 4481 #define sc_x4_final_config_status_operationSpeeds_SPEED_10G_CX4_10p3125 58 4482 #define sc_x4_final_config_status_operationSpeeds_SPEED_10G_KX4_10p3125 57 4483 #define sc_x4_final_config_status_operationSpeeds_SPEED_2p5G_X1_10p3125 56 4484 #define sc_x4_final_config_status_operationSpeeds_SPEED_1000M_10p3125 55 4485 #define sc_x4_final_config_status_operationSpeeds_SPEED_100M_10p3125 54 4486 #define sc_x4_final_config_status_operationSpeeds_SPEED_10M_10p3125 53 4487 #define sc_x4_final_config_status_operationSpeeds_SPEED_10p5G_X4 50 4488 #define sc_x4_final_config_status_operationSpeeds_SPEED_5G_KR1 49 4489 #define sc_x4_final_config_status_operationSpeeds_SPEED_42p42G_X4 44 4490 #define sc_x4_final_config_status_operationSpeeds_SPEED_21p21G_X2 43 4491 #define sc_x4_final_config_status_operationSpeeds_SPEED_48p48G_X4 42 4492 #define sc_x4_final_config_status_operationSpeeds_SPEED_24p24G_X2 41 4493 #define sc_x4_final_config_status_operationSpeeds_SPEED_12p12G_X1 40 4494 #define sc_x4_final_config_status_operationSpeeds_SPEED_127G_X12 39 4495 #define sc_x4_final_config_status_operationSpeeds_SPEED_120G_X12 38 4496 #define sc_x4_final_config_status_operationSpeeds_SPEED_107G_X10 37 4497 #define sc_x4_final_config_status_operationSpeeds_SPEED_100G_CR10 36 4498 #define sc_x4_final_config_status_operationSpeeds_SPEED_42G_X4 35 4499 #define sc_x4_final_config_status_operationSpeeds_SPEED_40G_CR4 34 4500 #define sc_x4_final_config_status_operationSpeeds_SPEED_40G_KR4 33 4501 #define sc_x4_final_config_status_operationSpeeds_SPEED_21G_X2 32 4502 #define sc_x4_final_config_status_operationSpeeds_SPEED_20G_CR2 31 4503 #define sc_x4_final_config_status_operationSpeeds_SPEED_20G_KR2 30 4504 #define sc_x4_final_config_status_operationSpeeds_SPEED_10p6_X1 29 4505 #define sc_x4_final_config_status_operationSpeeds_SPEED_10G_KR1 28 4506 #define sc_x4_final_config_status_operationSpeeds_SPEED_40G_X4 27 4507 #define sc_x4_final_config_status_operationSpeeds_SPEED_20G_X2 26 4508 #define sc_x4_final_config_status_operationSpeeds_SPEED_20G_CX2 25 4509 #define sc_x4_final_config_status_operationSpeeds_SPEED_31p5G_KR4 24 4510 #define sc_x4_final_config_status_operationSpeeds_SPEED_31p5G_X4 23 4511 #define sc_x4_final_config_status_operationSpeeds_SPEED_15p75G_X2 22 4512 #define sc_x4_final_config_status_operationSpeeds_SPEED_25p45G_X4 21 4513 #define sc_x4_final_config_status_operationSpeeds_SPEED_12p7G_X2 20 4514 #define sc_x4_final_config_status_operationSpeeds_SPEED_21G_X4 19 4515 #define sc_x4_final_config_status_operationSpeeds_SPEED_10p5G_X2 18 4516 #define sc_x4_final_config_status_operationSpeeds_SPEED_20G_X4 17 4517 #define sc_x4_final_config_status_operationSpeeds_SPEED_10G_X2 16 4518 #define sc_x4_final_config_status_operationSpeeds_SPEED_10G_CX2 15 4519 #define sc_x4_final_config_status_operationSpeeds_SPEED_20G_CX4 14 4520 #define sc_x4_final_config_status_operationSpeeds_SPEED_16G_X4 13 4521 #define sc_x4_final_config_status_operationSpeeds_SPEED_15G_X4 12 4522 #define sc_x4_final_config_status_operationSpeeds_SPEED_13G_X4 11 4523 #define sc_x4_final_config_status_operationSpeeds_SPEED_10G_X4 10 4524 #define sc_x4_final_config_status_operationSpeeds_SPEED_10G_KX4 9 4525 #define sc_x4_final_config_status_operationSpeeds_SPEED_10G_CX4 8 4526 #define sc_x4_final_config_status_operationSpeeds_SPEED_5G_X1 7 4527 #define sc_x4_final_config_status_operationSpeeds_SPEED_2p5G_X1 6 4528 #define sc_x4_final_config_status_operationSpeeds_SPEED_1G_KX1 5 4529 #define sc_x4_final_config_status_operationSpeeds_SPEED_1G_CX1 4 4530 #define sc_x4_final_config_status_operationSpeeds_SPEED_1000M 3 4531 #define sc_x4_final_config_status_operationSpeeds_SPEED_100M 2 4532 #define sc_x4_final_config_status_operationSpeeds_SPEED_10M 1 4533 4534 /**************************************************************************** 4535 * Enums: sc_x4_final_config_status_actualSpeeds 4536 */ 4537 #define sc_x4_final_config_status_actualSpeeds_dr_10M 0 4538 #define sc_x4_final_config_status_actualSpeeds_dr_100M 1 4539 #define sc_x4_final_config_status_actualSpeeds_dr_1G 2 4540 #define sc_x4_final_config_status_actualSpeeds_dr_2p5G 3 4541 #define sc_x4_final_config_status_actualSpeeds_dr_5G_X4 4 4542 #define sc_x4_final_config_status_actualSpeeds_dr_6G_X4 5 4543 #define sc_x4_final_config_status_actualSpeeds_dr_10G_HiG 6 4544 #define sc_x4_final_config_status_actualSpeeds_dr_10G_CX4 7 4545 #define sc_x4_final_config_status_actualSpeeds_dr_12G_HiG 8 4546 #define sc_x4_final_config_status_actualSpeeds_dr_12p5G_X4 9 4547 #define sc_x4_final_config_status_actualSpeeds_dr_13G_X4 10 4548 #define sc_x4_final_config_status_actualSpeeds_dr_15G_X4 11 4549 #define sc_x4_final_config_status_actualSpeeds_dr_16G_X4 12 4550 #define sc_x4_final_config_status_actualSpeeds_dr_1G_KX 13 4551 #define sc_x4_final_config_status_actualSpeeds_dr_10G_KX4 14 4552 #define sc_x4_final_config_status_actualSpeeds_dr_10G_KR 15 4553 #define sc_x4_final_config_status_actualSpeeds_dr_5G 16 4554 #define sc_x4_final_config_status_actualSpeeds_dr_6p4G 17 4555 #define sc_x4_final_config_status_actualSpeeds_dr_20G_X4 18 4556 #define sc_x4_final_config_status_actualSpeeds_dr_21G_X4 19 4557 #define sc_x4_final_config_status_actualSpeeds_dr_25G_X4 20 4558 #define sc_x4_final_config_status_actualSpeeds_dr_10G_HiG_DXGXS 21 4559 #define sc_x4_final_config_status_actualSpeeds_dr_10G_DXGXS 22 4560 #define sc_x4_final_config_status_actualSpeeds_dr_10p5G_HiG_DXGXS 23 4561 #define sc_x4_final_config_status_actualSpeeds_dr_10p5G_DXGXS 24 4562 #define sc_x4_final_config_status_actualSpeeds_dr_12p773G_HiG_DXGXS 25 4563 #define sc_x4_final_config_status_actualSpeeds_dr_12p773G_DXGXS 26 4564 #define sc_x4_final_config_status_actualSpeeds_dr_10G_XFI 27 4565 #define sc_x4_final_config_status_actualSpeeds_dr_40G 28 4566 #define sc_x4_final_config_status_actualSpeeds_dr_20G_HiG_DXGXS 29 4567 #define sc_x4_final_config_status_actualSpeeds_dr_20G_DXGXS 30 4568 #define sc_x4_final_config_status_actualSpeeds_dr_10G_SFI 31 4569 #define sc_x4_final_config_status_actualSpeeds_dr_31p5G 32 4570 #define sc_x4_final_config_status_actualSpeeds_dr_32p7G 33 4571 #define sc_x4_final_config_status_actualSpeeds_dr_20G_SCR 34 4572 #define sc_x4_final_config_status_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 4573 #define sc_x4_final_config_status_actualSpeeds_dr_10G_DXGXS_SCR 36 4574 #define sc_x4_final_config_status_actualSpeeds_dr_12G_R2 37 4575 #define sc_x4_final_config_status_actualSpeeds_dr_10G_X2 38 4576 #define sc_x4_final_config_status_actualSpeeds_dr_40G_KR4 39 4577 #define sc_x4_final_config_status_actualSpeeds_dr_40G_CR4 40 4578 #define sc_x4_final_config_status_actualSpeeds_dr_100G_CR10 41 4579 #define sc_x4_final_config_status_actualSpeeds_dr_15p75G_DXGXS 44 4580 #define sc_x4_final_config_status_actualSpeeds_dr_20G_KR2 57 4581 #define sc_x4_final_config_status_actualSpeeds_dr_20G_CR2 58 4582 4583 /**************************************************************************** 4584 * Enums: sc_x4_final_config_status_actualSpeedsMisc1 4585 */ 4586 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_2500BRCM_X1 16 4587 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_5000BRCM_X4 17 4588 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_6000BRCM_X4 18 4589 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_10GHiGig_X4 19 4590 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_10GBASE_CX4 20 4591 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_12GHiGig_X4 21 4592 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 4593 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_13GHiGig_X4 23 4594 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_15GHiGig_X4 24 4595 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_16GHiGig_X4 25 4596 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_5000BRCM_X1 26 4597 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_6363BRCM_X1 27 4598 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_20GHiGig_X4 28 4599 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_21GHiGig_X4 29 4600 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 4601 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 4602 4603 /**************************************************************************** 4604 * Enums: sc_x4_final_config_status_IndLaneModes 4605 */ 4606 #define sc_x4_final_config_status_IndLaneModes_SWSDR_div2 0 4607 #define sc_x4_final_config_status_IndLaneModes_SWSDR_div1 1 4608 #define sc_x4_final_config_status_IndLaneModes_DWSDR_div2 2 4609 #define sc_x4_final_config_status_IndLaneModes_DWSDR_div1 3 4610 4611 /**************************************************************************** 4612 * Enums: sc_x4_final_config_status_prbsSelect 4613 */ 4614 #define sc_x4_final_config_status_prbsSelect_prbs7 0 4615 #define sc_x4_final_config_status_prbsSelect_prbs15 1 4616 #define sc_x4_final_config_status_prbsSelect_prbs23 2 4617 #define sc_x4_final_config_status_prbsSelect_prbs31 3 4618 4619 /**************************************************************************** 4620 * Enums: sc_x4_final_config_status_vcoDivider 4621 */ 4622 #define sc_x4_final_config_status_vcoDivider_div32 0 4623 #define sc_x4_final_config_status_vcoDivider_div36 1 4624 #define sc_x4_final_config_status_vcoDivider_div40 2 4625 #define sc_x4_final_config_status_vcoDivider_div42 3 4626 #define sc_x4_final_config_status_vcoDivider_div48 4 4627 #define sc_x4_final_config_status_vcoDivider_div50 5 4628 #define sc_x4_final_config_status_vcoDivider_div52 6 4629 #define sc_x4_final_config_status_vcoDivider_div54 7 4630 #define sc_x4_final_config_status_vcoDivider_div60 8 4631 #define sc_x4_final_config_status_vcoDivider_div64 9 4632 #define sc_x4_final_config_status_vcoDivider_div66 10 4633 #define sc_x4_final_config_status_vcoDivider_div68 11 4634 #define sc_x4_final_config_status_vcoDivider_div70 12 4635 #define sc_x4_final_config_status_vcoDivider_div80 13 4636 #define sc_x4_final_config_status_vcoDivider_div92 14 4637 #define sc_x4_final_config_status_vcoDivider_div100 15 4638 4639 /**************************************************************************** 4640 * Enums: sc_x4_final_config_status_refClkSelect 4641 */ 4642 #define sc_x4_final_config_status_refClkSelect_clk_25MHz 0 4643 #define sc_x4_final_config_status_refClkSelect_clk_100MHz 1 4644 #define sc_x4_final_config_status_refClkSelect_clk_125MHz 2 4645 #define sc_x4_final_config_status_refClkSelect_clk_156p25MHz 3 4646 #define sc_x4_final_config_status_refClkSelect_clk_187p5MHz 4 4647 #define sc_x4_final_config_status_refClkSelect_clk_161p25Mhz 5 4648 #define sc_x4_final_config_status_refClkSelect_clk_50Mhz 6 4649 #define sc_x4_final_config_status_refClkSelect_clk_106p25Mhz 7 4650 4651 /**************************************************************************** 4652 * Enums: sc_x4_final_config_status_aerMMDdevTypeSelect 4653 */ 4654 #define sc_x4_final_config_status_aerMMDdevTypeSelect_combo_core 0 4655 #define sc_x4_final_config_status_aerMMDdevTypeSelect_PMA_PMD 1 4656 #define sc_x4_final_config_status_aerMMDdevTypeSelect_PCS 3 4657 #define sc_x4_final_config_status_aerMMDdevTypeSelect_PHY 4 4658 #define sc_x4_final_config_status_aerMMDdevTypeSelect_DTE 5 4659 #define sc_x4_final_config_status_aerMMDdevTypeSelect_CL73_AN 7 4660 4661 /**************************************************************************** 4662 * Enums: sc_x4_final_config_status_aerMMDportSelect 4663 */ 4664 #define sc_x4_final_config_status_aerMMDportSelect_ln0 0 4665 #define sc_x4_final_config_status_aerMMDportSelect_ln1 1 4666 #define sc_x4_final_config_status_aerMMDportSelect_ln2 2 4667 #define sc_x4_final_config_status_aerMMDportSelect_ln3 3 4668 #define sc_x4_final_config_status_aerMMDportSelect_BCST_ln0_1_2_3 511 4669 #define sc_x4_final_config_status_aerMMDportSelect_BCST_ln0_1 512 4670 #define sc_x4_final_config_status_aerMMDportSelect_BCST_ln2_3 513 4671 4672 /**************************************************************************** 4673 * Enums: sc_x4_final_config_status_firmwareModeSelect 4674 */ 4675 #define sc_x4_final_config_status_firmwareModeSelect_DEFAULT 0 4676 #define sc_x4_final_config_status_firmwareModeSelect_SFP_OPT_LR 1 4677 #define sc_x4_final_config_status_firmwareModeSelect_SFP_DAC 2 4678 #define sc_x4_final_config_status_firmwareModeSelect_XLAUI 3 4679 #define sc_x4_final_config_status_firmwareModeSelect_LONG_CH_6G 4 4680 4681 /**************************************************************************** 4682 * Enums: sc_x4_final_config_status_tempIdxSelect 4683 */ 4684 #define sc_x4_final_config_status_tempIdxSelect_LTE__22p9C 15 4685 #define sc_x4_final_config_status_tempIdxSelect_LTE__12p6C 14 4686 #define sc_x4_final_config_status_tempIdxSelect_LTE__3p0C 13 4687 #define sc_x4_final_config_status_tempIdxSelect_LTE_6p7C 12 4688 #define sc_x4_final_config_status_tempIdxSelect_LTE_16p4C 11 4689 #define sc_x4_final_config_status_tempIdxSelect_LTE_26p6C 10 4690 #define sc_x4_final_config_status_tempIdxSelect_LTE_36p3C 9 4691 #define sc_x4_final_config_status_tempIdxSelect_LTE_46p0C 8 4692 #define sc_x4_final_config_status_tempIdxSelect_LTE_56p2C 7 4693 #define sc_x4_final_config_status_tempIdxSelect_LTE_65p9C 6 4694 #define sc_x4_final_config_status_tempIdxSelect_LTE_75p6C 5 4695 #define sc_x4_final_config_status_tempIdxSelect_LTE_85p3C 4 4696 #define sc_x4_final_config_status_tempIdxSelect_LTE_95p5C 3 4697 #define sc_x4_final_config_status_tempIdxSelect_LTE_105p2C 2 4698 #define sc_x4_final_config_status_tempIdxSelect_LTE_114p9C 1 4699 #define sc_x4_final_config_status_tempIdxSelect_LTE_125p1C 0 4700 4701 /**************************************************************************** 4702 * Enums: tx_x1_status0_tla_pll_status 4703 */ 4704 #define tx_x1_status0_tla_pll_status_INIT 1 4705 #define tx_x1_status0_tla_pll_status_PLL_LOCKED 2 4706 #define tx_x1_status0_tla_pll_status_RESET_PLL 4 4707 #define tx_x1_status0_tla_pll_status_CHANGE_PLL_MODE 8 4708 #define tx_x1_status0_tla_pll_status_PLL_SWITCH 16 4709 4710 /**************************************************************************** 4711 * Enums: tx_x4_credit_gen0_cl36TxEEEStates_l 4712 */ 4713 #define tx_x4_credit_gen0_cl36TxEEEStates_l_TX_REFRESH 8 4714 #define tx_x4_credit_gen0_cl36TxEEEStates_l_TX_QUIET 4 4715 #define tx_x4_credit_gen0_cl36TxEEEStates_l_TX_SLEEP 2 4716 #define tx_x4_credit_gen0_cl36TxEEEStates_l_TX_ACTIVE 1 4717 4718 /**************************************************************************** 4719 * Enums: tx_x4_credit_gen0_cl36TxEEEStates_c 4720 */ 4721 #define tx_x4_credit_gen0_cl36TxEEEStates_c_TX_REFRESH 3 4722 #define tx_x4_credit_gen0_cl36TxEEEStates_c_TX_QUIET 2 4723 #define tx_x4_credit_gen0_cl36TxEEEStates_c_TX_SLEEP 1 4724 #define tx_x4_credit_gen0_cl36TxEEEStates_c_TX_ACTIVE 0 4725 4726 /**************************************************************************** 4727 * Enums: tx_x4_credit_gen0_cl49TxEEEStates_l 4728 */ 4729 #define tx_x4_credit_gen0_cl49TxEEEStates_l_SCR_RESET_2 64 4730 #define tx_x4_credit_gen0_cl49TxEEEStates_l_SCR_RESET_1 32 4731 #define tx_x4_credit_gen0_cl49TxEEEStates_l_TX_WAKE 16 4732 #define tx_x4_credit_gen0_cl49TxEEEStates_l_TX_REFRESH 8 4733 #define tx_x4_credit_gen0_cl49TxEEEStates_l_TX_QUIET 4 4734 #define tx_x4_credit_gen0_cl49TxEEEStates_l_TX_SLEEP 2 4735 #define tx_x4_credit_gen0_cl49TxEEEStates_l_TX_ACTIVE 1 4736 4737 /**************************************************************************** 4738 * Enums: tx_x4_credit_gen0_cl49TxEEEStates_c 4739 */ 4740 #define tx_x4_credit_gen0_cl49TxEEEStates_c_SCR_RESET_2 6 4741 #define tx_x4_credit_gen0_cl49TxEEEStates_c_SCR_RESET_1 5 4742 #define tx_x4_credit_gen0_cl49TxEEEStates_c_TX_WAKE 4 4743 #define tx_x4_credit_gen0_cl49TxEEEStates_c_TX_REFRESH 3 4744 #define tx_x4_credit_gen0_cl49TxEEEStates_c_TX_QUIET 2 4745 #define tx_x4_credit_gen0_cl49TxEEEStates_c_TX_SLEEP 1 4746 #define tx_x4_credit_gen0_cl49TxEEEStates_c_TX_ACTIVE 0 4747 4748 /**************************************************************************** 4749 * Enums: tx_x4_credit_gen0_cl36RxEEEStates_l 4750 */ 4751 #define tx_x4_credit_gen0_cl36RxEEEStates_l_RX_LINK_FAIL 32 4752 #define tx_x4_credit_gen0_cl36RxEEEStates_l_RX_WTF 16 4753 #define tx_x4_credit_gen0_cl36RxEEEStates_l_RX_WAKE 8 4754 #define tx_x4_credit_gen0_cl36RxEEEStates_l_RX_QUIET 4 4755 #define tx_x4_credit_gen0_cl36RxEEEStates_l_RX_SLEEP 2 4756 #define tx_x4_credit_gen0_cl36RxEEEStates_l_RX_ACTIVE 1 4757 4758 /**************************************************************************** 4759 * Enums: tx_x4_credit_gen0_cl36RxEEEStates_c 4760 */ 4761 #define tx_x4_credit_gen0_cl36RxEEEStates_c_RX_LINK_FAIL 5 4762 #define tx_x4_credit_gen0_cl36RxEEEStates_c_RX_WTF 4 4763 #define tx_x4_credit_gen0_cl36RxEEEStates_c_RX_WAKE 3 4764 #define tx_x4_credit_gen0_cl36RxEEEStates_c_RX_QUIET 2 4765 #define tx_x4_credit_gen0_cl36RxEEEStates_c_RX_SLEEP 1 4766 #define tx_x4_credit_gen0_cl36RxEEEStates_c_RX_ACTIVE 0 4767 4768 /**************************************************************************** 4769 * Enums: tx_x4_credit_gen0_cl49RxEEEStates_l 4770 */ 4771 #define tx_x4_credit_gen0_cl49RxEEEStates_l_RX_LINK_FAIL 32 4772 #define tx_x4_credit_gen0_cl49RxEEEStates_l_RX_WTF 16 4773 #define tx_x4_credit_gen0_cl49RxEEEStates_l_RX_WAKE 8 4774 #define tx_x4_credit_gen0_cl49RxEEEStates_l_RX_QUIET 4 4775 #define tx_x4_credit_gen0_cl49RxEEEStates_l_RX_SLEEP 2 4776 #define tx_x4_credit_gen0_cl49RxEEEStates_l_RX_ACTIVE 1 4777 4778 /**************************************************************************** 4779 * Enums: tx_x4_credit_gen0_cl49RxEEEStates_c 4780 */ 4781 #define tx_x4_credit_gen0_cl49RxEEEStates_c_RX_LINK_FAIL 5 4782 #define tx_x4_credit_gen0_cl49RxEEEStates_c_RX_WTF 4 4783 #define tx_x4_credit_gen0_cl49RxEEEStates_c_RX_WAKE 3 4784 #define tx_x4_credit_gen0_cl49RxEEEStates_c_RX_QUIET 2 4785 #define tx_x4_credit_gen0_cl49RxEEEStates_c_RX_SLEEP 1 4786 #define tx_x4_credit_gen0_cl49RxEEEStates_c_RX_ACTIVE 0 4787 4788 /**************************************************************************** 4789 * Enums: tx_x4_credit_gen0_cl48TxEEEStates_l 4790 */ 4791 #define tx_x4_credit_gen0_cl48TxEEEStates_l_TX_REFRESH 8 4792 #define tx_x4_credit_gen0_cl48TxEEEStates_l_TX_QUIET 4 4793 #define tx_x4_credit_gen0_cl48TxEEEStates_l_TX_SLEEP 2 4794 #define tx_x4_credit_gen0_cl48TxEEEStates_l_TX_ACTIVE 1 4795 4796 /**************************************************************************** 4797 * Enums: tx_x4_credit_gen0_cl48TxEEEStates_c 4798 */ 4799 #define tx_x4_credit_gen0_cl48TxEEEStates_c_TX_REFRESH 3 4800 #define tx_x4_credit_gen0_cl48TxEEEStates_c_TX_QUIET 2 4801 #define tx_x4_credit_gen0_cl48TxEEEStates_c_TX_SLEEP 1 4802 #define tx_x4_credit_gen0_cl48TxEEEStates_c_TX_ACTIVE 0 4803 4804 /**************************************************************************** 4805 * Enums: tx_x4_credit_gen0_cl48RxEEEStates_l 4806 */ 4807 #define tx_x4_credit_gen0_cl48RxEEEStates_l_RX_LINK_FAIL 32 4808 #define tx_x4_credit_gen0_cl48RxEEEStates_l_RX_WAKE 16 4809 #define tx_x4_credit_gen0_cl48RxEEEStates_l_RX_QUIET 8 4810 #define tx_x4_credit_gen0_cl48RxEEEStates_l_RX_DEACT 4 4811 #define tx_x4_credit_gen0_cl48RxEEEStates_l_RX_SLEEP 2 4812 #define tx_x4_credit_gen0_cl48RxEEEStates_l_RX_ACTIVE 1 4813 4814 /**************************************************************************** 4815 * Enums: tx_x4_credit_gen0_cl48RxEEEStates_c 4816 */ 4817 #define tx_x4_credit_gen0_cl48RxEEEStates_c_RX_LINK_FAIL 5 4818 #define tx_x4_credit_gen0_cl48RxEEEStates_c_RX_WAKE 4 4819 #define tx_x4_credit_gen0_cl48RxEEEStates_c_RX_QUIET 3 4820 #define tx_x4_credit_gen0_cl48RxEEEStates_c_RX_DEACT 2 4821 #define tx_x4_credit_gen0_cl48RxEEEStates_c_RX_SLEEP 1 4822 #define tx_x4_credit_gen0_cl48RxEEEStates_c_RX_ACTIVE 0 4823 4824 /**************************************************************************** 4825 * Enums: tx_x4_credit_gen0_IQP_Options 4826 */ 4827 #define tx_x4_credit_gen0_IQP_Options_i50uA 0 4828 #define tx_x4_credit_gen0_IQP_Options_i100uA 1 4829 #define tx_x4_credit_gen0_IQP_Options_i150uA 2 4830 #define tx_x4_credit_gen0_IQP_Options_i200uA 3 4831 #define tx_x4_credit_gen0_IQP_Options_i250uA 4 4832 #define tx_x4_credit_gen0_IQP_Options_i300uA 5 4833 #define tx_x4_credit_gen0_IQP_Options_i350uA 6 4834 #define tx_x4_credit_gen0_IQP_Options_i400uA 7 4835 #define tx_x4_credit_gen0_IQP_Options_i450uA 8 4836 #define tx_x4_credit_gen0_IQP_Options_i500uA 9 4837 #define tx_x4_credit_gen0_IQP_Options_i550uA 10 4838 #define tx_x4_credit_gen0_IQP_Options_i600uA 11 4839 #define tx_x4_credit_gen0_IQP_Options_i650uA 12 4840 #define tx_x4_credit_gen0_IQP_Options_i700uA 13 4841 #define tx_x4_credit_gen0_IQP_Options_i750uA 14 4842 #define tx_x4_credit_gen0_IQP_Options_i800uA 15 4843 4844 /**************************************************************************** 4845 * Enums: tx_x4_credit_gen0_IDriver_Options 4846 */ 4847 #define tx_x4_credit_gen0_IDriver_Options_v680mV 0 4848 #define tx_x4_credit_gen0_IDriver_Options_v730mV 1 4849 #define tx_x4_credit_gen0_IDriver_Options_v780mV 2 4850 #define tx_x4_credit_gen0_IDriver_Options_v830mV 3 4851 #define tx_x4_credit_gen0_IDriver_Options_v880mV 4 4852 #define tx_x4_credit_gen0_IDriver_Options_v930mV 5 4853 #define tx_x4_credit_gen0_IDriver_Options_v980mV 6 4854 #define tx_x4_credit_gen0_IDriver_Options_v1010mV 7 4855 #define tx_x4_credit_gen0_IDriver_Options_v1040mV 8 4856 #define tx_x4_credit_gen0_IDriver_Options_v1060mV 9 4857 #define tx_x4_credit_gen0_IDriver_Options_v1070mV 10 4858 #define tx_x4_credit_gen0_IDriver_Options_v1080mV 11 4859 #define tx_x4_credit_gen0_IDriver_Options_v1085mV 12 4860 #define tx_x4_credit_gen0_IDriver_Options_v1090mV 13 4861 #define tx_x4_credit_gen0_IDriver_Options_v1095mV 14 4862 #define tx_x4_credit_gen0_IDriver_Options_v1100mV 15 4863 4864 /**************************************************************************** 4865 * Enums: tx_x4_credit_gen0_operationModes 4866 */ 4867 #define tx_x4_credit_gen0_operationModes_XGXS 0 4868 #define tx_x4_credit_gen0_operationModes_XGXG_nCC 1 4869 #define tx_x4_credit_gen0_operationModes_Indlane_OS8 4 4870 #define tx_x4_credit_gen0_operationModes_IndLane_OS5 5 4871 #define tx_x4_credit_gen0_operationModes_PCI 7 4872 #define tx_x4_credit_gen0_operationModes_XGXS_nLQ 8 4873 #define tx_x4_credit_gen0_operationModes_XGXS_nLQnCC 9 4874 #define tx_x4_credit_gen0_operationModes_PBypass 10 4875 #define tx_x4_credit_gen0_operationModes_PBypass_nDSK 11 4876 #define tx_x4_credit_gen0_operationModes_ComboCoreMode 12 4877 #define tx_x4_credit_gen0_operationModes_Clocks_off 15 4878 4879 /**************************************************************************** 4880 * Enums: tx_x4_credit_gen0_synce_enum 4881 */ 4882 #define tx_x4_credit_gen0_synce_enum_SYNCE_NO_DIV 0 4883 #define tx_x4_credit_gen0_synce_enum_SYNCE_DIV_7 1 4884 #define tx_x4_credit_gen0_synce_enum_SYNCE_DIV_11 2 4885 #define tx_x4_credit_gen0_synce_enum_SYNCE_DIV_10 3 4886 4887 /**************************************************************************** 4888 * Enums: tx_x4_credit_gen0_synce_enum_stage0 4889 */ 4890 #define tx_x4_credit_gen0_synce_enum_stage0_SYNCE_NO_DIV 0 4891 #define tx_x4_credit_gen0_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 4892 #define tx_x4_credit_gen0_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 4893 4894 /**************************************************************************** 4895 * Enums: tx_x4_credit_gen0_operationSpeeds 4896 */ 4897 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10G_X4_10p3125 59 4898 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10G_CX4_10p3125 58 4899 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10G_KX4_10p3125 57 4900 #define tx_x4_credit_gen0_operationSpeeds_SPEED_2p5G_X1_10p3125 56 4901 #define tx_x4_credit_gen0_operationSpeeds_SPEED_1000M_10p3125 55 4902 #define tx_x4_credit_gen0_operationSpeeds_SPEED_100M_10p3125 54 4903 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10M_10p3125 53 4904 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10p5G_X4 50 4905 #define tx_x4_credit_gen0_operationSpeeds_SPEED_5G_KR1 49 4906 #define tx_x4_credit_gen0_operationSpeeds_SPEED_42p42G_X4 44 4907 #define tx_x4_credit_gen0_operationSpeeds_SPEED_21p21G_X2 43 4908 #define tx_x4_credit_gen0_operationSpeeds_SPEED_48p48G_X4 42 4909 #define tx_x4_credit_gen0_operationSpeeds_SPEED_24p24G_X2 41 4910 #define tx_x4_credit_gen0_operationSpeeds_SPEED_12p12G_X1 40 4911 #define tx_x4_credit_gen0_operationSpeeds_SPEED_127G_X12 39 4912 #define tx_x4_credit_gen0_operationSpeeds_SPEED_120G_X12 38 4913 #define tx_x4_credit_gen0_operationSpeeds_SPEED_107G_X10 37 4914 #define tx_x4_credit_gen0_operationSpeeds_SPEED_100G_CR10 36 4915 #define tx_x4_credit_gen0_operationSpeeds_SPEED_42G_X4 35 4916 #define tx_x4_credit_gen0_operationSpeeds_SPEED_40G_CR4 34 4917 #define tx_x4_credit_gen0_operationSpeeds_SPEED_40G_KR4 33 4918 #define tx_x4_credit_gen0_operationSpeeds_SPEED_21G_X2 32 4919 #define tx_x4_credit_gen0_operationSpeeds_SPEED_20G_CR2 31 4920 #define tx_x4_credit_gen0_operationSpeeds_SPEED_20G_KR2 30 4921 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10p6_X1 29 4922 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10G_KR1 28 4923 #define tx_x4_credit_gen0_operationSpeeds_SPEED_40G_X4 27 4924 #define tx_x4_credit_gen0_operationSpeeds_SPEED_20G_X2 26 4925 #define tx_x4_credit_gen0_operationSpeeds_SPEED_20G_CX2 25 4926 #define tx_x4_credit_gen0_operationSpeeds_SPEED_31p5G_KR4 24 4927 #define tx_x4_credit_gen0_operationSpeeds_SPEED_31p5G_X4 23 4928 #define tx_x4_credit_gen0_operationSpeeds_SPEED_15p75G_X2 22 4929 #define tx_x4_credit_gen0_operationSpeeds_SPEED_25p45G_X4 21 4930 #define tx_x4_credit_gen0_operationSpeeds_SPEED_12p7G_X2 20 4931 #define tx_x4_credit_gen0_operationSpeeds_SPEED_21G_X4 19 4932 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10p5G_X2 18 4933 #define tx_x4_credit_gen0_operationSpeeds_SPEED_20G_X4 17 4934 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10G_X2 16 4935 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10G_CX2 15 4936 #define tx_x4_credit_gen0_operationSpeeds_SPEED_20G_CX4 14 4937 #define tx_x4_credit_gen0_operationSpeeds_SPEED_16G_X4 13 4938 #define tx_x4_credit_gen0_operationSpeeds_SPEED_15G_X4 12 4939 #define tx_x4_credit_gen0_operationSpeeds_SPEED_13G_X4 11 4940 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10G_X4 10 4941 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10G_KX4 9 4942 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10G_CX4 8 4943 #define tx_x4_credit_gen0_operationSpeeds_SPEED_5G_X1 7 4944 #define tx_x4_credit_gen0_operationSpeeds_SPEED_2p5G_X1 6 4945 #define tx_x4_credit_gen0_operationSpeeds_SPEED_1G_KX1 5 4946 #define tx_x4_credit_gen0_operationSpeeds_SPEED_1G_CX1 4 4947 #define tx_x4_credit_gen0_operationSpeeds_SPEED_1000M 3 4948 #define tx_x4_credit_gen0_operationSpeeds_SPEED_100M 2 4949 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10M 1 4950 4951 /**************************************************************************** 4952 * Enums: tx_x4_credit_gen0_actualSpeeds 4953 */ 4954 #define tx_x4_credit_gen0_actualSpeeds_dr_10M 0 4955 #define tx_x4_credit_gen0_actualSpeeds_dr_100M 1 4956 #define tx_x4_credit_gen0_actualSpeeds_dr_1G 2 4957 #define tx_x4_credit_gen0_actualSpeeds_dr_2p5G 3 4958 #define tx_x4_credit_gen0_actualSpeeds_dr_5G_X4 4 4959 #define tx_x4_credit_gen0_actualSpeeds_dr_6G_X4 5 4960 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_HiG 6 4961 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_CX4 7 4962 #define tx_x4_credit_gen0_actualSpeeds_dr_12G_HiG 8 4963 #define tx_x4_credit_gen0_actualSpeeds_dr_12p5G_X4 9 4964 #define tx_x4_credit_gen0_actualSpeeds_dr_13G_X4 10 4965 #define tx_x4_credit_gen0_actualSpeeds_dr_15G_X4 11 4966 #define tx_x4_credit_gen0_actualSpeeds_dr_16G_X4 12 4967 #define tx_x4_credit_gen0_actualSpeeds_dr_1G_KX 13 4968 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_KX4 14 4969 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_KR 15 4970 #define tx_x4_credit_gen0_actualSpeeds_dr_5G 16 4971 #define tx_x4_credit_gen0_actualSpeeds_dr_6p4G 17 4972 #define tx_x4_credit_gen0_actualSpeeds_dr_20G_X4 18 4973 #define tx_x4_credit_gen0_actualSpeeds_dr_21G_X4 19 4974 #define tx_x4_credit_gen0_actualSpeeds_dr_25G_X4 20 4975 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_HiG_DXGXS 21 4976 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_DXGXS 22 4977 #define tx_x4_credit_gen0_actualSpeeds_dr_10p5G_HiG_DXGXS 23 4978 #define tx_x4_credit_gen0_actualSpeeds_dr_10p5G_DXGXS 24 4979 #define tx_x4_credit_gen0_actualSpeeds_dr_12p773G_HiG_DXGXS 25 4980 #define tx_x4_credit_gen0_actualSpeeds_dr_12p773G_DXGXS 26 4981 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_XFI 27 4982 #define tx_x4_credit_gen0_actualSpeeds_dr_40G 28 4983 #define tx_x4_credit_gen0_actualSpeeds_dr_20G_HiG_DXGXS 29 4984 #define tx_x4_credit_gen0_actualSpeeds_dr_20G_DXGXS 30 4985 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_SFI 31 4986 #define tx_x4_credit_gen0_actualSpeeds_dr_31p5G 32 4987 #define tx_x4_credit_gen0_actualSpeeds_dr_32p7G 33 4988 #define tx_x4_credit_gen0_actualSpeeds_dr_20G_SCR 34 4989 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 4990 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_DXGXS_SCR 36 4991 #define tx_x4_credit_gen0_actualSpeeds_dr_12G_R2 37 4992 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_X2 38 4993 #define tx_x4_credit_gen0_actualSpeeds_dr_40G_KR4 39 4994 #define tx_x4_credit_gen0_actualSpeeds_dr_40G_CR4 40 4995 #define tx_x4_credit_gen0_actualSpeeds_dr_100G_CR10 41 4996 #define tx_x4_credit_gen0_actualSpeeds_dr_15p75G_DXGXS 44 4997 #define tx_x4_credit_gen0_actualSpeeds_dr_20G_KR2 57 4998 #define tx_x4_credit_gen0_actualSpeeds_dr_20G_CR2 58 4999 5000 /**************************************************************************** 5001 * Enums: tx_x4_credit_gen0_actualSpeedsMisc1 5002 */ 5003 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_2500BRCM_X1 16 5004 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_5000BRCM_X4 17 5005 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_6000BRCM_X4 18 5006 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_10GHiGig_X4 19 5007 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_10GBASE_CX4 20 5008 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_12GHiGig_X4 21 5009 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 5010 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_13GHiGig_X4 23 5011 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_15GHiGig_X4 24 5012 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_16GHiGig_X4 25 5013 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_5000BRCM_X1 26 5014 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_6363BRCM_X1 27 5015 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_20GHiGig_X4 28 5016 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_21GHiGig_X4 29 5017 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 5018 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 5019 5020 /**************************************************************************** 5021 * Enums: tx_x4_credit_gen0_IndLaneModes 5022 */ 5023 #define tx_x4_credit_gen0_IndLaneModes_SWSDR_div2 0 5024 #define tx_x4_credit_gen0_IndLaneModes_SWSDR_div1 1 5025 #define tx_x4_credit_gen0_IndLaneModes_DWSDR_div2 2 5026 #define tx_x4_credit_gen0_IndLaneModes_DWSDR_div1 3 5027 5028 /**************************************************************************** 5029 * Enums: tx_x4_credit_gen0_prbsSelect 5030 */ 5031 #define tx_x4_credit_gen0_prbsSelect_prbs7 0 5032 #define tx_x4_credit_gen0_prbsSelect_prbs15 1 5033 #define tx_x4_credit_gen0_prbsSelect_prbs23 2 5034 #define tx_x4_credit_gen0_prbsSelect_prbs31 3 5035 5036 /**************************************************************************** 5037 * Enums: tx_x4_credit_gen0_vcoDivider 5038 */ 5039 #define tx_x4_credit_gen0_vcoDivider_div32 0 5040 #define tx_x4_credit_gen0_vcoDivider_div36 1 5041 #define tx_x4_credit_gen0_vcoDivider_div40 2 5042 #define tx_x4_credit_gen0_vcoDivider_div42 3 5043 #define tx_x4_credit_gen0_vcoDivider_div48 4 5044 #define tx_x4_credit_gen0_vcoDivider_div50 5 5045 #define tx_x4_credit_gen0_vcoDivider_div52 6 5046 #define tx_x4_credit_gen0_vcoDivider_div54 7 5047 #define tx_x4_credit_gen0_vcoDivider_div60 8 5048 #define tx_x4_credit_gen0_vcoDivider_div64 9 5049 #define tx_x4_credit_gen0_vcoDivider_div66 10 5050 #define tx_x4_credit_gen0_vcoDivider_div68 11 5051 #define tx_x4_credit_gen0_vcoDivider_div70 12 5052 #define tx_x4_credit_gen0_vcoDivider_div80 13 5053 #define tx_x4_credit_gen0_vcoDivider_div92 14 5054 #define tx_x4_credit_gen0_vcoDivider_div100 15 5055 5056 /**************************************************************************** 5057 * Enums: tx_x4_credit_gen0_refClkSelect 5058 */ 5059 #define tx_x4_credit_gen0_refClkSelect_clk_25MHz 0 5060 #define tx_x4_credit_gen0_refClkSelect_clk_100MHz 1 5061 #define tx_x4_credit_gen0_refClkSelect_clk_125MHz 2 5062 #define tx_x4_credit_gen0_refClkSelect_clk_156p25MHz 3 5063 #define tx_x4_credit_gen0_refClkSelect_clk_187p5MHz 4 5064 #define tx_x4_credit_gen0_refClkSelect_clk_161p25Mhz 5 5065 #define tx_x4_credit_gen0_refClkSelect_clk_50Mhz 6 5066 #define tx_x4_credit_gen0_refClkSelect_clk_106p25Mhz 7 5067 5068 /**************************************************************************** 5069 * Enums: tx_x4_credit_gen0_aerMMDdevTypeSelect 5070 */ 5071 #define tx_x4_credit_gen0_aerMMDdevTypeSelect_combo_core 0 5072 #define tx_x4_credit_gen0_aerMMDdevTypeSelect_PMA_PMD 1 5073 #define tx_x4_credit_gen0_aerMMDdevTypeSelect_PCS 3 5074 #define tx_x4_credit_gen0_aerMMDdevTypeSelect_PHY 4 5075 #define tx_x4_credit_gen0_aerMMDdevTypeSelect_DTE 5 5076 #define tx_x4_credit_gen0_aerMMDdevTypeSelect_CL73_AN 7 5077 5078 /**************************************************************************** 5079 * Enums: tx_x4_credit_gen0_aerMMDportSelect 5080 */ 5081 #define tx_x4_credit_gen0_aerMMDportSelect_ln0 0 5082 #define tx_x4_credit_gen0_aerMMDportSelect_ln1 1 5083 #define tx_x4_credit_gen0_aerMMDportSelect_ln2 2 5084 #define tx_x4_credit_gen0_aerMMDportSelect_ln3 3 5085 #define tx_x4_credit_gen0_aerMMDportSelect_BCST_ln0_1_2_3 511 5086 #define tx_x4_credit_gen0_aerMMDportSelect_BCST_ln0_1 512 5087 #define tx_x4_credit_gen0_aerMMDportSelect_BCST_ln2_3 513 5088 5089 /**************************************************************************** 5090 * Enums: tx_x4_credit_gen0_firmwareModeSelect 5091 */ 5092 #define tx_x4_credit_gen0_firmwareModeSelect_DEFAULT 0 5093 #define tx_x4_credit_gen0_firmwareModeSelect_SFP_OPT_LR 1 5094 #define tx_x4_credit_gen0_firmwareModeSelect_SFP_DAC 2 5095 #define tx_x4_credit_gen0_firmwareModeSelect_XLAUI 3 5096 #define tx_x4_credit_gen0_firmwareModeSelect_LONG_CH_6G 4 5097 5098 /**************************************************************************** 5099 * Enums: tx_x4_credit_gen0_tempIdxSelect 5100 */ 5101 #define tx_x4_credit_gen0_tempIdxSelect_LTE__22p9C 15 5102 #define tx_x4_credit_gen0_tempIdxSelect_LTE__12p6C 14 5103 #define tx_x4_credit_gen0_tempIdxSelect_LTE__3p0C 13 5104 #define tx_x4_credit_gen0_tempIdxSelect_LTE_6p7C 12 5105 #define tx_x4_credit_gen0_tempIdxSelect_LTE_16p4C 11 5106 #define tx_x4_credit_gen0_tempIdxSelect_LTE_26p6C 10 5107 #define tx_x4_credit_gen0_tempIdxSelect_LTE_36p3C 9 5108 #define tx_x4_credit_gen0_tempIdxSelect_LTE_46p0C 8 5109 #define tx_x4_credit_gen0_tempIdxSelect_LTE_56p2C 7 5110 #define tx_x4_credit_gen0_tempIdxSelect_LTE_65p9C 6 5111 #define tx_x4_credit_gen0_tempIdxSelect_LTE_75p6C 5 5112 #define tx_x4_credit_gen0_tempIdxSelect_LTE_85p3C 4 5113 #define tx_x4_credit_gen0_tempIdxSelect_LTE_95p5C 3 5114 #define tx_x4_credit_gen0_tempIdxSelect_LTE_105p2C 2 5115 #define tx_x4_credit_gen0_tempIdxSelect_LTE_114p9C 1 5116 #define tx_x4_credit_gen0_tempIdxSelect_LTE_125p1C 0 5117 5118 5119 /**************************************************************************** 5120 * Datatype Definitions. 5121 */ 5122 #endif /* #ifndef TEPCSREGENUMS_TMP__ */ 5123 5124 /* End of File */ 5125