temod16_diagnostics.c (18970B)
1 /* 2 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 3 * 4 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 5 */ 6 7 #include <phymod/phymod.h> 8 #include <phymod/phymod_util.h> 9 #include <phymod/phymod_debug.h> 10 #include <phymod/chip/bcmi_tsce16_xgxs_defs.h> 11 #include "temod16_enum_defines.h" 12 #include "temod16.h" 13 14 #define PHYMOD_ST const phymod_access_t 15 #define _TRG_OPN(a) _TRGO_(a->addr, a->lane_mask) 16 #define _TRG_CLS(a) _TRGC_(a->addr, a->lane_mask) 17 #define _TRG_LANE(a) (a->lane_mask) 18 19 20 int temod16_diag_link(PHYMOD_ST *pc) 21 { 22 PMD_X1_STSr_t pmd_live_status; 23 PMD_X4_STSr_t pmd_lane_live_status; 24 PMD_X4_LATCH_STSr_t pmd_lane_latched_status[4]; 25 RX_X4_PCS_LIVE_STSr_t pcs_live_status; 26 RX_X4_PCS_LATCH_STS0r_t pcs_latched_status; 27 phymod_access_t *lpc = (phymod_access_t*)pc; 28 29 int i,rx_lock_sts[4],sig_det_sts[4], this_lane; 30 31 /*1. pmd_live_status */ 32 READ_PMD_X1_STSr(pc, &pmd_live_status); 33 34 /*2a. pmd_lane_live_status */ 35 /*2b. pmd_lane_latched_status */ 36 37 this_lane = _TRG_LANE(lpc); 38 for(i=0; i < 4; i++) { 39 _TRG_LANE(lpc) = 1<<i; 40 READ_PMD_X4_STSr(lpc, &pmd_lane_live_status); 41 sig_det_sts[i] = PMD_X4_STSr_SIGNAL_DETECT_STSf_GET(pmd_lane_live_status); 42 rx_lock_sts[i] = PMD_X4_STSr_RX_LOCK_STSf_GET(pmd_lane_live_status); 43 44 PMD_X4_LATCH_STSr_CLR(pmd_lane_latched_status[i]); 45 READ_PMD_X4_LATCH_STSr(pc, &pmd_lane_latched_status[i]); 46 } 47 _TRG_LANE(lpc) = this_lane; 48 49 /*3a. pcs_live_status */ 50 /*3b. pcs_latched_status */ 51 READ_RX_X4_PCS_LIVE_STSr(pc, &pcs_live_status); 52 READ_RX_X4_PCS_LATCH_STS0r(pc, &pcs_latched_status); 53 54 /* Print the information here */ 55 PHYMOD_DEBUG_ERROR(("+-----------------------+-------------------+---------------+---------+--------+\n")); 56 PHYMOD_DEBUG_ERROR(("| TRG ADR : %06d LANE: %02d LINK STATE | LH | LL |\n", pc->addr, pc->lane_mask)); 57 PHYMOD_DEBUG_ERROR(("+-----------------------+-------------------+---------------+---------+--------+\n")); 58 PHYMOD_DEBUG_ERROR(("| PMD PLL LOCK : %c | PCS SYNC : %c | PCS SYNC STAT : %04d : %04d |\n", 59 (PMD_X1_STSr_PLL_LOCK_STSf_GET(pmd_live_status) == 1) ? 'Y' : 'N', 60 (RX_X4_PCS_LIVE_STSr_SYNC_STATUSf_GET(pcs_live_status) == 1) ? 'Y' : 'N', 61 RX_X4_PCS_LATCH_STS0r_SYNC_STATUS_LHf_GET(pcs_latched_status), 62 RX_X4_PCS_LATCH_STS0r_SYNC_STATUS_LLf_GET(pcs_latched_status))); 63 64 PHYMOD_DEBUG_ERROR(("| PMD SIG DETECT : %c%c%c%c | PCS LINK : %c | PCS LINK STAT : %04d : %04d |\n", 65 (sig_det_sts[3] == 1)? 'Y':'N', 66 (sig_det_sts[2] == 1)? 'Y':'N', 67 (sig_det_sts[1] == 1)? 'Y':'N', 68 (sig_det_sts[0] == 1)? 'Y':'N', 69 (RX_X4_PCS_LIVE_STSr_LINK_STATUSf_GET(pcs_live_status) == 1) ? 'Y' : 'N', 70 RX_X4_PCS_LATCH_STS0r_LINK_STATUS_LHf_GET(pcs_latched_status), 71 RX_X4_PCS_LATCH_STS0r_LINK_STATUS_LLf_GET(pcs_latched_status))); 72 73 PHYMOD_DEBUG_ERROR(("| PMD LOCKED : %c%c%c%c | PCS HI BER : %04d | PCS HIGH BER : %04d : %04d |\n", 74 (rx_lock_sts[3] == 1)? 'Y':'N', 75 (rx_lock_sts[2] == 1)? 'Y':'N', 76 (rx_lock_sts[1] == 1)? 'Y':'N', 77 (rx_lock_sts[0] == 1)? 'Y':'N', 78 RX_X4_PCS_LIVE_STSr_HI_BERf_GET(pcs_live_status), 79 RX_X4_PCS_LATCH_STS0r_HI_BER_LLf_GET(pcs_latched_status), 80 RX_X4_PCS_LATCH_STS0r_HI_BER_LHf_GET(pcs_latched_status))); 81 82 PHYMOD_DEBUG_ERROR(("| PMD LATCH HI : %d%d%d%d | PCS DESKEW : %04d | PCS DESKEW : %04d : %04d |\n", 83 PMD_X4_LATCH_STSr_SIGNAL_DETECT_LHf_GET(pmd_lane_latched_status[3]), 84 PMD_X4_LATCH_STSr_SIGNAL_DETECT_LHf_GET(pmd_lane_latched_status[2]), 85 PMD_X4_LATCH_STSr_SIGNAL_DETECT_LHf_GET(pmd_lane_latched_status[1]), 86 PMD_X4_LATCH_STSr_SIGNAL_DETECT_LHf_GET(pmd_lane_latched_status[0]), 87 RX_X4_PCS_LIVE_STSr_DESKEW_STATUSf_GET(pcs_live_status), 88 RX_X4_PCS_LATCH_STS0r_DESKEW_STATUS_LLf_GET(pcs_latched_status), 89 RX_X4_PCS_LATCH_STS0r_DESKEW_STATUS_LHf_GET(pcs_latched_status))); 90 91 PHYMOD_DEBUG_ERROR(("| PMD LATCH LO : %d%d%d%d | PCS AMLOCK : %04d | PCS AM LOCK : %04d : %04d |\n", 92 PMD_X4_LATCH_STSr_SIGNAL_DETECT_LLf_GET(pmd_lane_latched_status[3]), 93 PMD_X4_LATCH_STSr_SIGNAL_DETECT_LLf_GET(pmd_lane_latched_status[2]), 94 PMD_X4_LATCH_STSr_SIGNAL_DETECT_LLf_GET(pmd_lane_latched_status[1]), 95 PMD_X4_LATCH_STSr_SIGNAL_DETECT_LLf_GET(pmd_lane_latched_status[0]), 96 RX_X4_PCS_LIVE_STSr_AM_LOCKf_GET(pcs_live_status), 97 RX_X4_PCS_LATCH_STS0r_AM_LOCK_LLf_GET(pcs_latched_status), 98 RX_X4_PCS_LATCH_STS0r_AM_LOCK_LHf_GET(pcs_latched_status))); 99 100 PHYMOD_DEBUG_ERROR(("| RXLOCK LATCH HI: %d%d%d%d | | |\n", 101 PMD_X4_LATCH_STSr_RX_LOCK_LHf_GET(pmd_lane_latched_status[3]), 102 PMD_X4_LATCH_STSr_RX_LOCK_LHf_GET(pmd_lane_latched_status[2]), 103 PMD_X4_LATCH_STSr_RX_LOCK_LHf_GET(pmd_lane_latched_status[1]), 104 PMD_X4_LATCH_STSr_RX_LOCK_LHf_GET(pmd_lane_latched_status[0]))); 105 106 PHYMOD_DEBUG_ERROR(("| RXLOCK LATCH LO: %d%d%d%d | | |\n", 107 PMD_X4_LATCH_STSr_RX_LOCK_LLf_GET(pmd_lane_latched_status[3]), 108 PMD_X4_LATCH_STSr_RX_LOCK_LLf_GET(pmd_lane_latched_status[2]), 109 PMD_X4_LATCH_STSr_RX_LOCK_LLf_GET(pmd_lane_latched_status[1]), 110 PMD_X4_LATCH_STSr_RX_LOCK_LLf_GET(pmd_lane_latched_status[0]))); 111 112 PHYMOD_DEBUG_ERROR(("+-----------------------+-------------------+----------------------------------+\n")); 113 114 return PHYMOD_E_NONE; 115 } 116 117 int temod16_diag_autoneg_abilities(PHYMOD_ST *pc) 118 { 119 AN_X4_ENSr_t an_ena; 120 AN_X4_LOC_DEV_CL37_BASE_ABILr_t cl37_base; 121 AN_X4_LOC_DEV_CL37_BAM_ABILr_t cl37_bam; 122 AN_X4_LOC_DEV_OVER1G_ABIL0r_t over1g; 123 AN_X4_LOC_DEV_OVER1G_ABIL1r_t over1g1; 124 AN_X4_LOC_DEV_CL73_BAM_ABILr_t cl73_bam; 125 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_t cl73_base_0; 126 AN_X4_LOC_DEV_CL73_BASE_ABIL1r_t cl73_base_1; 127 AN_X4_CTLSr_t an_ctrl; 128 uint16_t sgmii_spd, lanes, base_sel; 129 130 READ_AN_X4_ENSr (pc, &an_ena); 131 READ_AN_X4_LOC_DEV_CL37_BASE_ABILr (pc, &cl37_base); 132 READ_AN_X4_LOC_DEV_CL37_BAM_ABILr (pc, &cl37_bam); 133 READ_AN_X4_LOC_DEV_OVER1G_ABIL0r (pc, &over1g); 134 READ_AN_X4_LOC_DEV_OVER1G_ABIL1r (pc, &over1g1); 135 READ_AN_X4_LOC_DEV_CL73_BAM_ABILr (pc, &cl73_bam); 136 READ_AN_X4_LOC_DEV_CL73_BASE_ABIL0r (pc, &cl73_base_0); 137 READ_AN_X4_LOC_DEV_CL73_BASE_ABIL1r (pc, &cl73_base_1); 138 READ_AN_X4_CTLSr (pc, &an_ctrl); 139 140 PHYMOD_DEBUG_ERROR(("+-------------------+-------+------+-----------------------+-------------------+\n")); 141 PHYMOD_DEBUG_ERROR(("| ANX4 CTRL: 0x%04X | ENS : 0x%04X | CL37 BAM:0x%04X BASE :0x%04X |\n", 142 AN_X4_CTLSr_GET(an_ctrl), AN_X4_ENSr_GET(an_ena), 143 AN_X4_LOC_DEV_CL37_BAM_ABILr_GET(cl37_bam), AN_X4_LOC_DEV_CL37_BASE_ABILr_GET(cl37_base))); 144 145 PHYMOD_DEBUG_ERROR(("| ANX4 OVR0: 0x%04X | OVR1: 0x%04X | CL73 BAM:0x%04X BASE1:0x%04X BASE0:0x%04X |\n", 146 AN_X4_LOC_DEV_OVER1G_ABIL0r_GET(over1g), AN_X4_LOC_DEV_OVER1G_ABIL1r_GET(over1g1), 147 AN_X4_LOC_DEV_CL73_BAM_ABILr_GET(cl73_bam), AN_X4_LOC_DEV_CL73_BASE_ABIL0r_GET(cl73_base_0), 148 AN_X4_LOC_DEV_CL73_BASE_ABIL1r_GET(cl73_base_1))); 149 150 lanes = AN_X4_ENSr_NUM_ADVERTISED_LANESf_GET(an_ena); 151 PHYMOD_DEBUG_ERROR(("+-------------------+--------------+----+--------------------------------------+\n")); 152 PHYMOD_DEBUG_ERROR(("| CLAUSE 37 | CLAUSE 73 | |\n")); 153 PHYMOD_DEBUG_ERROR(("+-------------------+-------------------+--------------------------------------+\n")); 154 PHYMOD_DEBUG_ERROR(("| BAM ENA : %d | BAM ENA : %d | NUM ADV LANES : %d |\n", 155 AN_X4_ENSr_CL37_BAM_ENABLEf_GET(an_ena), 156 AN_X4_ENSr_CL73_BAM_ENABLEf_GET(an_ena), 157 (lanes == 0? 1 : (lanes == 1? 2 : (lanes == 3? 10 : 1))))); 158 159 PHYMOD_DEBUG_ERROR(("| AN ENA : %d | AN ENA : %d | FAIL COUNT LIM: %d |\n", 160 AN_X4_ENSr_CL37_ENABLEf_GET(an_ena), 161 AN_X4_ENSr_CL73_ENABLEf_GET(an_ena), 162 AN_X4_CTLSr_AN_FAIL_COUNT_LIMITf_GET(an_ctrl))); 163 164 PHYMOD_DEBUG_ERROR(("| SGMII ENA : %d | HPAM ENA : %d | |\n", 165 AN_X4_ENSr_CL37_SGMII_ENABLEf_GET(an_ena), 166 AN_X4_ENSr_CL73_HPAM_ENABLEf_GET(an_ena))); 167 168 PHYMOD_DEBUG_ERROR(("| BAM2SGMII ENA : %d | BAM3HPAM ENA : %d | |\n", 169 AN_X4_ENSr_CL37_BAM_TO_SGMII_AUTO_ENABLEf_GET(an_ena), 170 AN_X4_ENSr_CL73_BAM_TO_HPAM_AUTO_ENABLEf_GET(an_ena))); 171 172 PHYMOD_DEBUG_ERROR(("| SGMII2CL37 ENA: %d | HPAM2CL73 ENA: %d | |\n", 173 AN_X4_ENSr_SGMII_TO_CL37_AUTO_ENABLEf_GET(an_ena), 174 AN_X4_ENSr_HPAM_TO_CL73_AUTO_ENABLEf_GET(an_ena))); 175 176 PHYMOD_DEBUG_ERROR(("| AN RESTART : %d | AN RESTART : %d | |\n", 177 AN_X4_ENSr_CL37_AN_RESTARTf_GET(an_ena), 178 AN_X4_ENSr_CL73_AN_RESTARTf_GET(an_ena))); 179 180 sgmii_spd = AN_X4_LOC_DEV_CL37_BASE_ABILr_SGMII_SPEEDf_GET(cl37_base); 181 base_sel = AN_X4_LOC_DEV_CL73_BASE_ABIL1r_BASE_SELECTORf_GET(cl73_base_1); 182 183 PHYMOD_DEBUG_ERROR(("+-------------------+-------------------+--------------------------------------+\n")); 184 PHYMOD_DEBUG_ERROR(("| CL37 ABILITIES | CL73 ABILITIES |\n")); 185 PHYMOD_DEBUG_ERROR(("+---------------+-----------------------+-----------------+--------------------+\n")); 186 PHYMOD_DEBUG_ERROR(("| SWRST DIS : %d | ANRST DIS :%d | NONCE OVR : %d | NONCE VAL: %d |\n", 187 AN_X4_LOC_DEV_CL37_BASE_ABILr_CL37_SW_RESTART_RESET_DISABLEf_GET(cl37_base), 188 AN_X4_LOC_DEV_CL37_BASE_ABILr_CL37_AN_RESTART_RESET_DISABLEf_GET(cl37_base), 189 AN_X4_LOC_DEV_CL73_BASE_ABIL1r_CL73_NONCE_MATCH_OVERf_GET(cl73_base_1), 190 AN_X4_LOC_DEV_CL73_BASE_ABIL1r_CL73_NONCE_MATCH_VALf_GET(cl73_base_1))); 191 192 PHYMOD_DEBUG_ERROR(("| PD 2 CL37 : %d | NEXT PAGE :%d | TX NONCE : 0x%X| BASE SEL : %-7s |\n", 193 AN_X4_LOC_DEV_CL37_BASE_ABILr_AN_PD_TO_CL37_ENABLEf_GET(cl37_base), 194 AN_X4_LOC_DEV_CL37_BASE_ABILr_CL37_NEXT_PAGEf_GET(cl37_base), 195 AN_X4_LOC_DEV_CL73_BASE_ABIL1r_TRANSMIT_NONCEf_GET(cl73_base_1), 196 (base_sel == 0? "Rsvd" : 197 (base_sel == 1? "802.3" : 198 (base_sel == 2? "802.9" : 199 (base_sel == 3? "802.5": 200 (base_sel == 4? "1394": "UNKNOWN"))))) )); 201 202 PHYMOD_DEBUG_ERROR(("| HALF DUPLX: %d | FULL DUPLEX :%d | NEXT PAGE : %d | FEC : %d |\n", 203 AN_X4_LOC_DEV_CL37_BASE_ABILr_CL37_FULL_DUPLEXf_GET(cl37_base), 204 AN_X4_LOC_DEV_CL37_BASE_ABILr_CL37_HALF_DUPLEXf_GET(cl37_base), 205 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_NEXT_PAGEf_GET(cl73_base_0), 206 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_FECf_GET(cl73_base_0))); 207 208 PHYMOD_DEBUG_ERROR(("| PAUSE : %d | SGMII MASTER :%d | REMOTE FLT : %d | PAUSE : %d |\n", 209 AN_X4_LOC_DEV_CL37_BASE_ABILr_CL37_PAUSEf_GET(cl37_base), 210 AN_X4_LOC_DEV_CL37_BASE_ABILr_SGMII_MASTER_MODEf_GET(cl37_base), 211 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_CL73_REMOTE_FAULTf_GET(cl73_base_0), 212 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_CL73_PAUSEf_GET(cl73_base_0))); 213 214 PHYMOD_DEBUG_ERROR(("| SGMII FDUP: %d | SGMII SPD :%-7s |-----------------+--------------------|\n", 215 AN_X4_LOC_DEV_CL37_BASE_ABILr_SGMII_FULL_DUPLEXf_GET(cl37_base), 216 (sgmii_spd == 0? "10Mb/s" : 217 (sgmii_spd == 1? "100Mb/s": 218 (sgmii_spd == 2? "1Gb/s" : "Rsvd"))) )); 219 220 PHYMOD_DEBUG_ERROR(("| OVR1G ABIL: %d | OVR1G PAGECNT:%d | 1000BASE KX : %d | 10GBASE KX4 :%d |\n", 221 AN_X4_LOC_DEV_CL37_BAM_ABILr_OVER1G_ABILITYf_GET(cl37_bam), 222 AN_X4_LOC_DEV_CL37_BAM_ABILr_OVER1G_PAGE_COUNTf_GET(cl37_bam), 223 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_BASE_1000BASE_KXf_GET(cl73_base_0), 224 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_BASE_10GBASE_KX4f_GET(cl73_base_0))); 225 226 PHYMOD_DEBUG_ERROR(("| BAM CODE : 0x%04X | 10GBASE KR : %d | 10GBASE KR4 :%d |\n", 227 AN_X4_LOC_DEV_CL37_BAM_ABILr_CL37_BAM_CODEf_GET(cl37_bam), 228 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_BASE_10GBASE_KRf_GET(cl73_base_0), 229 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_BASE_40GBASE_KR4f_GET(cl73_base_0))); 230 231 PHYMOD_DEBUG_ERROR(("|---------------+-----------------------| 40GBASE CR4 : %d | 100GBASE CR1:%d |\n", 232 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_BASE_40GBASE_CR4f_GET(cl73_base_0), 233 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_BASE_100GBASE_CR10f_GET(cl73_base_0))); 234 235 PHYMOD_DEBUG_ERROR(("| | HPAM_20GKR2 : %d | BAM CODE :0x%04X|\n", 236 AN_X4_LOC_DEV_CL73_BAM_ABILr_HPAM_20GKR2f_GET(cl73_bam), 237 AN_X4_LOC_DEV_CL73_BAM_ABILr_CL73_BAM_CODEf_GET(cl73_bam))); 238 239 PHYMOD_DEBUG_ERROR(("| | 20GBASE CR2 : %d | 20GBASE KR2 : %d |\n", 240 AN_X4_LOC_DEV_CL73_BAM_ABILr_BAM_20GBASE_CR2f_GET(cl73_bam), 241 AN_X4_LOC_DEV_CL73_BAM_ABILr_BAM_20GBASE_KR2f_GET(cl73_bam))); 242 243 PHYMOD_DEBUG_ERROR(("+---------------------------------------+--------------------------------------+\n")); 244 PHYMOD_DEBUG_ERROR(("| OVER1G ABILITIES |\n")); 245 PHYMOD_DEBUG_ERROR(("+-------------------+--------------------+-----------------+-------------------+\n")); 246 PHYMOD_DEBUG_ERROR(("| HG2 : %d | FEC : %d | CL72 : %d| |\n", 247 AN_X4_LOC_DEV_OVER1G_ABIL1r_HG2f_GET(over1g1), 248 AN_X4_LOC_DEV_OVER1G_ABIL1r_FECf_GET(over1g1), 249 AN_X4_LOC_DEV_OVER1G_ABIL1r_CL72f_GET(over1g1))); 250 251 PHYMOD_DEBUG_ERROR(("| 40GBASE X4 : %d | 32P7GBASE X4 : %d | 31P5GBASE X4 : %d| 25P455GBASE X4: %d |\n", 252 AN_X4_LOC_DEV_OVER1G_ABIL1r_BAM_40GBASE_X4f_GET(over1g1), 253 AN_X4_LOC_DEV_OVER1G_ABIL1r_BAM_32P7GBASE_X4f_GET(over1g1), 254 AN_X4_LOC_DEV_OVER1G_ABIL1r_BAM_31P5GBASE_X4f_GET(over1g1), 255 AN_X4_LOC_DEV_OVER1G_ABIL1r_BAM_25P455GBASE_X4f_GET(over1g1))); 256 257 PHYMOD_DEBUG_ERROR(("| 21GBASE X4 : %d | 20GBASEX2 CX4: %d | 20GBASE X2 : %d| 20GBASE X4 : %d |\n", 258 AN_X4_LOC_DEV_OVER1G_ABIL1r_BAM_21GBASE_X4f_GET(over1g1), 259 AN_X4_LOC_DEV_OVER1G_ABIL1r_BAM_20GBASE_X2_CX4f_GET(over1g1), 260 AN_X4_LOC_DEV_OVER1G_ABIL1r_BAM_20GBASE_X2f_GET(over1g1), 261 AN_X4_LOC_DEV_OVER1G_ABIL1r_BAM_20GBASE_X4f_GET(over1g1))); 262 263 PHYMOD_DEBUG_ERROR(("| 16GBASE X4 : %d | 15P75GBASE X2: %d | 15GBASE X4 : %d| 13GBASE X4 : %d |\n", 264 AN_X4_LOC_DEV_OVER1G_ABIL1r_BAM_16GBASE_X4f_GET(over1g1), 265 AN_X4_LOC_DEV_OVER1G_ABIL1r_BAM_15P75GBASE_X2f_GET(over1g1), 266 AN_X4_LOC_DEV_OVER1G_ABIL1r_BAM_15GBASE_X4f_GET(over1g1), 267 AN_X4_LOC_DEV_OVER1G_ABIL1r_BAM_13GBASE_X4f_GET(over1g1))); 268 269 return PHYMOD_E_NONE; 270 } 271 272 int tempd16_an_hcd_spd_get (uint16_t spd, char *mystr, int len) 273 { 274 char *an_spd = "UNDEF"; 275 276 if (spd == 1) an_spd ="10M"; 277 if (spd == 2) an_spd ="100M"; 278 if (spd == 3) an_spd ="1000M"; 279 if (spd == 4) an_spd ="1G_CX1"; 280 if (spd == 5) an_spd ="1G_KX1"; 281 if (spd == 6) an_spd ="2p5G_X1"; 282 if (spd == 7) an_spd ="5G_X1"; 283 if (spd == 8) an_spd ="10G_CX4"; 284 if (spd == 9) an_spd ="10G_KX4"; 285 if (spd == 0xa) an_spd ="10G_X4"; 286 if (spd == 0xb) an_spd ="13G_X4"; 287 if (spd == 0xc) an_spd ="15G_X4"; 288 if (spd == 0xd) an_spd ="16G_X4"; 289 if (spd == 0xe) an_spd ="20G_CX4"; 290 if (spd == 0xf) an_spd ="10G_CX2"; 291 if (spd == 0x10) an_spd ="10G_X2"; 292 if (spd == 0x11) an_spd ="20G_X4"; 293 if (spd == 0x12) an_spd ="10p5G_X2"; 294 if (spd == 0x13) an_spd ="21G_X4"; 295 if (spd == 0x14) an_spd ="12p7G_X2"; 296 if (spd == 0x15) an_spd ="25p45G_X4"; 297 if (spd == 0x16) an_spd ="15p75G_X2"; 298 if (spd == 0x17) an_spd ="31P5G_X4"; 299 if (spd == 0x18) an_spd ="31p5G_KR4"; 300 if (spd == 0x19) an_spd ="20G_CX2"; 301 if (spd == 0x1a) an_spd ="20G_X2"; 302 if (spd == 0x1b) an_spd ="40G_X4"; 303 if (spd == 0x1c) an_spd ="10G_KR1"; 304 if (spd == 0x1d) an_spd ="10p6_X1"; 305 if (spd == 0x1e) an_spd ="20G_KR2"; 306 if (spd == 0x1f) an_spd ="20G_CR2"; 307 if (spd == 0x20) an_spd ="21G_X2"; 308 if (spd == 0x21) an_spd ="40G_KR4"; 309 if (spd == 0x22) an_spd ="40G_CR4"; 310 if (spd == 0x23) an_spd ="42G_X4"; 311 if (spd == 0x24) an_spd ="100G_CR10"; 312 if (spd == 0x25) an_spd ="107G_X10"; 313 if (spd == 0x26) an_spd ="120G_X12"; 314 if (spd == 0x27) an_spd ="127G_X12"; 315 if (spd == 0x31) an_spd ="5G_KR1"; 316 if (spd == 0x32) an_spd ="10p5G_X4"; 317 if (spd == 0x35) an_spd ="10M_10p3125"; 318 if (spd == 0x36) an_spd ="100M_10p3125"; 319 if (spd == 0x37) an_spd ="1000M_10p3125"; 320 if (spd == 0x38) an_spd ="2p5G_X1_10p3125"; 321 if (spd == 0x39) an_spd ="10G_KX4_10p3125"; 322 if (spd == 0x3a) an_spd ="10G_CX4_10p3125"; 323 if (spd == 0x3b) an_spd ="10G_X4_10p3125"; 324 325 PHYMOD_STRNCPY(mystr, an_spd, len); 326 327 return PHYMOD_E_NONE; 328 } 329 330 int temod16_diag_autoneg(PHYMOD_ST *pc) 331 { 332 AN_X4_AN_PAGE_SEQUENCER_STSr_t an_page_seq_status; 333 AN_X4_AN_ABIL_RESOLUTION_STSr_t an_hcd_status; 334 AN_X4_AN_MISC_STSr_t an_misc_status; 335 char an_spd[16]; 336 337 READ_AN_X4_AN_PAGE_SEQUENCER_STSr(pc,&an_page_seq_status); 338 READ_AN_X4_AN_ABIL_RESOLUTION_STSr(pc,&an_hcd_status); 339 READ_AN_X4_AN_MISC_STSr(pc,&an_misc_status); 340 tempd16_an_hcd_spd_get (AN_X4_AN_ABIL_RESOLUTION_STSr_AN_HCD_SPEEDf_GET(an_hcd_status), an_spd, sizeof(an_spd)); 341 342 PHYMOD_DEBUG_ERROR(("| TRG ADR : %06d LANE: %02d AUTONEG |\n", 343 pc->addr, pc->lane_mask)); 344 PHYMOD_DEBUG_ERROR(("+-------------+-------------+------------------------------+-------------------+\n")); 345 PHYMOD_DEBUG_ERROR(("| AN37: %c | AN73 : %c | AN HCD SPD : %-16s| AN LINK : %s |\n", 346 (AN_X4_AN_PAGE_SEQUENCER_STSr_AN_ST_CL37_COMPLETEf_GET(an_page_seq_status) == 1) ? 'Y' : 'N', 347 (AN_X4_AN_PAGE_SEQUENCER_STSr_AN_ST_CL73_COMPLETEf_GET(an_page_seq_status) == 1) ? 'Y' : 'N', an_spd, 348 (((AN_X4_AN_PAGE_SEQUENCER_STSr_AN_ST_CL73_COMPLETEf_GET(an_page_seq_status) == 1) || 349 (AN_X4_AN_PAGE_SEQUENCER_STSr_AN_ST_CL37_COMPLETEf_GET(an_page_seq_status) == 1)) && 350 (AN_X4_AN_MISC_STSr_AN_COMPLETEf_GET(an_misc_status) == 1))? "UP":"DN")); 351 352 temod16_diag_autoneg_abilities(pc); 353 PHYMOD_DEBUG_ERROR(("+-------------------+--------------------+-----------------+-------------------+\n")); 354 355 return PHYMOD_E_NONE; 356 } 357 358 int temod16_diag_disp(PHYMOD_ST *pc, const char* cmd_str) 359 { 360 temod16_diag_link(pc); 361 temod16_diag_autoneg(pc); 362 return PHYMOD_E_NONE; 363 }