temod16_defines.h (9212B)
1 /*---------------------------------------------------------------------- 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * Broadcom Corporation 8 * Proprietary and Confidential information 9 * All rights reserved 10 * This source file is the property of Broadcom Corporation, and 11 * may not be copied or distributed in any isomorphic form without the 12 * prior written consent of Broadcom Corporation. 13 *---------------------------------------------------------------------- 14 * Description: define enumerators and temod16_st 15 *----------------------------------------------------------------------*/ 16 17 #ifndef _temod16_DEFINES_H_ 18 #define _temod16_DEFINES_H_ 19 20 #include "temod16_enum_defines.h" 21 22 /*! \struct temod16_st 23 24 This is the central TSCE context storing information of a single TE. 25 It has multiple sections, each with a set of elementtsc 26 27 \li Address Context: Elements to uniquely access a TSCE 28 29 */ 30 31 typedef struct { 32 #if defined (_DV_TB_) 33 /* ===== BEGIN ===== TSCE port address section */ 34 /*! chip number of the chip where the TSCE resides, defined by MDK/SDK 35 * platforms. It is not user in verilog and customer software platforms. */ 36 int unit; 37 /*! Port no. defined in MDK/SDK platforms. It is not used in verilog and 38 * customer software platforms. */ 39 int port; 40 /*! Port address strap value. Used only in TSCE verif. env. to identify 41 * the TSCE to the station manager */ 42 int prt_ad; 43 #endif 44 /*! lanes to access. Can simultaneously select multiple lanes. */ 45 temod16_lane_select lane_select; 46 /*! Current lane being processed can be 0, 1, 2 or 3. */ 47 int this_lane; 48 /*! May not need this. Legacy. Ignore lane number implications*/ 49 int adjust_port_mode; 50 /*! Tier1 Features are controlled by adding values to this var. Currently we 51 * manage with 32 bits (int type). If more bits are needed to specify a 52 * feature,more feature control variables will be added or this will be 53 * turned into an array. In general we try to use at most 8 bits per lane. */ 54 int per_lane_control; 55 56 int pcs_gloop; 57 int pmd_gloop; 58 int pcs_rloop; 59 60 int pmd_reset_control; 61 62 int pkt_number; 63 int pkt_size; 64 int ipg_size; 65 66 /*! see doc. on temod16_spd_intfc_type */ 67 temod16_spd_intfc_type spd_intf; 68 /*! Serial Bus protocol or PCB */ 69 temod16_regacc_type regacc_type; 70 /*! combo or independent */ 71 temod16_port_type port_type; 72 /*! Single copy registers cannot be modified repeatedly. Tier1 init function 73 * access these registers has to do this only once between resets in 74 * independent mode when the same Tier1 is called for multiple lanes. This 75 * sticky bit, remembers if the single copy regs. were already modified. */ 76 int tsc_touched; 77 int pcs_lane_swap_touched; 78 int pmd_touched; 79 int uc_touched; 80 81 int master_portnum; 82 /*! Lane swap contl variable. The positional values of the 8 nibbles indicate 83 * location of the logical lanes, like so. rx3_rx2_rx1_rx0_tx3_tx2_tx1_tx0. 84 * Default value 0x32103210 indicates no lanes swapped. */ 85 int lane_swap; 86 /*! Address of reg. to access */ 87 int accAddr; 88 /*! Data context. Contains data to write or data that is just read. Also 89 * contains revid after read_revid. */ 90 int accData; 91 /*! Various status of the link. Note check status of one link at a time. */ 92 int diag_type; 93 /*! Autoneg types. */ 94 temod16_an_type an_type; 95 /*! Autoneg parameter RF */ 96 int an_rf; 97 /*! Autoneg parameter pause */ 98 int an_pause; 99 /*! Autoneg parameter various speeds (bit encoded) */ 100 int an_tech_ability; 101 int an_bam37_ability; 102 /*! Autoneg parameter enable FEC */ 103 int an_fec; 104 int an_higig2; 105 int an_cl72; 106 /*! Control information the driver prints. If set to zero, only warnings and 107 * errors will be printed. If set to 1, msgs (developers discretion will be 108 * printed) but not register transactions. If set to 2 transactions will be 109 * printed (plus everything else). 110 */ 111 int verbosity; 112 /* last 4 bits are for TSCE state information */ 113 int ctrl_type; 114 /*! for when user wants to provide custom refclk. Will also work for 115 * standard values. The 10ths value of the frequency need not be entered. So 156.1 116 * becomes 156 117 */ 118 int refclk; 119 /*! pll div value is auto computed. But override is provided. */ 120 int plldiv; 121 122 int vga_frzval; 123 int vga_frcfrz; 124 int dfe_frzval; 125 int dfe_frcfrz; 126 int linkup_bert_cnt[4] ; 127 int firmware_mode ; 128 int an_ctl ; 129 int pattern_enable ; 130 int pattern_type ; 131 132 int prbs_inv; 133 int prbs_enable; 134 int prbs_check_mode; 135 int real_check; 136 137 /*! set multipipe_mode to select 100G/120G speeds */ 138 int cl82_multi_pipe_mode; 139 140 /*! set cl82_mld_phys_map to set the mode for 100G speeds */ 141 int cl82_mld_phys_map; 142 143 144 int tx_am_timer_init_val; 145 int rx_am_timer_init_val; 146 147 /* SC Table Entry */ 148 int sc_mode; /* choose the override modes to pick the 149 speed fields */ 150 int speed; /* Speed */ 151 int num_lanes; /* Number of lanes */ 152 153 int pll_mode; /* PLL mode */ 154 155 int t_pma_os_mode; /* T_PMA over-sampling mode */ 156 int t_scr_mode; /* T_SCR Scrambler mode */ 157 int cl72_en; /* T_CL&@ enable */ 158 int fec_en; /* T_FEC enable */ 159 int t_encode_mode; /* TX Encode mode */ 160 161 int r_descr1_mode; /* R_DESC1 Descrambler mode */ 162 int r_dec1_mode; /* R_DEC1 Decode mode */ 163 int r_deskew_mode; /* R_DESKEW mode */ 164 int r_desc2_mode; /* R_DESC2 mode */ 165 int r_desc2_byte_deletion; /* R_DESC2 byte-deletion mode */ 166 int r_dec1_brcm64b66_descr; /* R_DEC1 Descramble mode */ 167 168 int cl48_check_end; /* CL48 link check end */ 169 int sigdet_filter; /* Signal detect mode */ 170 int blk_sync_mode; /* Block Sync Mode */ 171 int r_reorder_mode; /* R_REORDER mode */ 172 int cl36_en; /* CL36_EN mode */ 173 174 int sgmii; 175 int clkcnt0; 176 int clkcnt1; 177 int lpcnt0; 178 int lpcnt1; 179 int mac_cgc; 180 int pcs_repcnt; 181 int pcs_crdten; 182 int pcs_clkcnt; 183 int pcs_cgc; 184 int uc_active; 185 /*CL37 capabilities*/ 186 int cl37_an_pause; 187 int cl37_an_hd; 188 int cl37_an_fd; 189 int cl37_an_np; 190 int an_tick_override; 191 int an_tick_denominator; 192 int an_tick_numerator; 193 int an_fail_cnt; 194 int an_oui_ctrl; 195 int cl37_sgmii_speed; 196 int cl37_sgmii_duplex; 197 int cl37_sgmii_master_mode; 198 int cl37_bam_code; 199 int cl37_bam_ovr1g_en; 200 int cl37_bam_ovr1g_pgcnt; 201 int cl37_bam_speed; 202 int an_abilities_CL72; 203 int cl37_bam_fec; 204 int cl37_bam_hg2; 205 int cl37_bam_to_sgmii_auto_enable; 206 int sgmii_to_cl37_auto_enable; 207 int cl37_bam_en; 208 int cl37_sgmii_en; 209 int cl37_an_en; 210 int cl37_an_restart; 211 int cl73_an_en; 212 int cl73_bam_en; 213 int cl73_hpam_en; 214 int cl73_an_restart; 215 int cl73_bam_to_hpam_auto_enable; 216 int hpam_to_cl73_auto_enable; 217 int cl73_bam_speed; 218 int cl73_bam_code; 219 int cl73_speed; 220 int cl73_nxt_page; 221 int cl73_fec; 222 int cl73_pause; 223 int cl73_remote_fault; 224 int transmit_nonce; 225 int base_selector; 226 int cl73_nonce_match_over; 227 int cl73_nonce_match_val; 228 int oui_upper_data; 229 int oui_lower_data; 230 int cl37_restart_timer_period; 231 int cl37_ack_timer_period; 232 int cl37_error_timer_period; 233 int cl73_break_link_timer_period; 234 int cl73_error_timer_period; 235 int link_fail_inhibit_timer_cl72_period; 236 int link_fail_inhibit_timer_not_cl72_period; 237 int pd_sd_timer_period; 238 int cl72_max_wait_timer; 239 int cl72_wait_timer; 240 int an_ignore_link_timer; 241 int bam_spd_pri_5_0; 242 int bam_spd_pri_11_6; 243 int bam_spd_pri_17_12; 244 int bam_spd_pri_23_18; 245 int bam_spd_pri_29_24; 246 int bam_spd_pri_35_30; 247 int no_of_lanes; 248 int pd_kx_en; 249 int pd_kx4_en; 250 int an_pd_to_cl37_enable; 251 int cl37_high_vco; 252 int cl73_low_vco; 253 int single_port_mode; 254 int pd_to_cl37_retry_cnt; 255 int pd_to_cl37_wait_timer; 256 int disable_rf_report; 257 int bit_rep_native_mode; 258 int temod16_use_higig2_knobs ; 259 int tx_higig2_en; 260 int tx_higig2_codec; 261 int rx_higig2_en; 262 int rx_higig2_codec; 263 int linkfailtimer_dis; 264 int linkfailtimerqua_en; 265 int an_good_check_trap; 266 int an_good_trap; 267 int tx_reset_count; 268 int credit_sel; 269 int scramble_idle_tx_en; 270 int scramble_idle_rx_en; 271 } temod16_st; 272 273 /* function table */ 274 typedef int (*tier1FuncTable)(temod16_st* c); 275 276 #endif /* _temod16_DEFINES_H_ */