temod16_cfg_seq.c (232421B)
1 /*---------------------------------------------------------------------- 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * Broadcom Corporation 8 * Proprietary and Confidential information 9 * All rights reserved 10 * This source file is the property of Broadcom Corporation, and 11 * may not be copied or distributed in any isomorphic form without the 12 * prior written consent of Broadcom Corporation. 13 *--------------------------------------------------------------------- 14 * File : temod16_cfg_seq.c 15 * Description: c functions implementing Tier1s for TEMod Serdes Driver 16 *---------------------------------------------------------------------*/ 17 18 #ifndef _DV_TB_ 19 #define _SDK_TEMOD16_ 1 20 #endif 21 22 #ifdef _DV_TB_ 23 #include <stdint.h> 24 #include "temod16_main.h" 25 #include "temod16_defines.h" 26 #include "te16PCSRegEnums.h" 27 #include "te16PMDRegEnums.h" 28 #include "phy_tsc_iblk.h" 29 #include "bcmi_tsce_xgxs_defs.h" 30 #endif /* _DV_TB_ */ 31 32 33 #ifdef _SDK_TEMOD16_ 34 #include <phymod/phymod.h> 35 #include <phymod/phymod_system.h> 36 #include <phymod/phymod_util.h> 37 #include <phymod/phymod_debug.h> 38 #include <phymod/chip/bcmi_tsce16_xgxs_defs.h> 39 #include "temod16_enum_defines.h" 40 #include "temod16.h" 41 #include "temod16_sc_lkup_table.h" 42 #include "te16PCSRegEnums.h" 43 #include "../../merlin16/tier1/merlin16_internal.h" 44 #include "../../merlin16/tier1/merlin16_interface.h" 45 46 #endif /* _SDK_TEMOD16_ */ 47 48 #ifndef PHYMOD_ST 49 #ifdef _SDK_TEMOD16_ 50 #define PHYMOD_ST const phymod_access_t 51 #else 52 #define PHYMOD_ST temod16_st 53 #endif /* _SDK_TEMOD16_ */ 54 #endif /* PHYMOD_ST */ 55 56 57 #ifdef _SDK_TEMOD16_ 58 #define TEMOD16_DBG_FUNC (1L << 0) 59 #define TMOD_DBG_IN_FUNC_INFO(pc) \ 60 PHYMOD_VDBG(TEMOD16_DBG_FUNC,pc,("%-22s: Adr:%08x Ln:%02d\n", __func__, (unsigned int)pc->addr, (int)pc->lane_mask)) 61 #endif 62 63 #ifdef _DV_TB_ 64 #define TMOD_DBG_IN_FUNC_INFO(pc) \ 65 PHYMOD_VDBG(TEMOD16_DBG_FUNC, pc, \ 66 ("TEMOD16 IN Function : %s Port Add : %d Lane No: %d\n", \ 67 __func__, pc->prt_ad, pc->this_lane)) 68 #define TEFMOD_DBG_OUT_FUNC_INFO(pc) \ 69 PHYMOD_VDBG(TEMOD16_DBG_FUNC, pc, \ 70 ("TEMOD16 OUT of Function : %s Port Add : %d Lane No: %d\n", \ 71 __func__, pc->prt_ad, pc->this_lane)) 72 int phymod_debug_check(uint32_t flags, PHYMOD_ST *pc); 73 #endif 74 75 #ifdef _SDK_TEMOD16_ 76 static merlin16_sc_pmd_entry_st merlin16_sc_pmd_entry[] = { 77 78 /*SPEED_10M : 0*/ { 1, TEMOD16_PMA_OS_MODE_10, TEMOD16_PLL_MODE_DIV_80, 0, 0, 1}, 79 /*SPEED_10M : 1*/ { 1, TEMOD16_PMA_OS_MODE_10, TEMOD16_PLL_MODE_DIV_80, 0, 0, 1}, 80 /*SPEED_100M : 2*/ { 1, TEMOD16_PMA_OS_MODE_10, TEMOD16_PLL_MODE_DIV_80, 0, 0, 1}, 81 /*SPEED_1000M : 3*/ { 1, TEMOD16_PMA_OS_MODE_10, TEMOD16_PLL_MODE_DIV_80, 0, 0, 1}, 82 /*SPEED_1G_CX1 :TBD 4*/ { 1, TEMOD16_PMA_OS_MODE_10, TEMOD16_PLL_MODE_DIV_80, 0, 0, 1}, 83 /*SPEED_1G_KX1 : 5*/ { 1, TEMOD16_PMA_OS_MODE_8_25, TEMOD16_PLL_MODE_DIV_66, 0, 0, 1}, 84 /*SPEED_2p5G : 6*/ { 1, TEMOD16_PMA_OS_MODE_4, TEMOD16_PLL_MODE_DIV_80, 0, 0, 1}, 85 /*SPEED_5G_X1 : 7*/ { 1, TEMOD16_PMA_OS_MODE_2, TEMOD16_PLL_MODE_DIV_80, 1, 0, 0}, 86 /*SPEED_10G_CX4 : 8*/ { 4, TEMOD16_PMA_OS_MODE_4, TEMOD16_PLL_MODE_DIV_80, 0, 0, 0}, 87 /*SPEED_10G_KX4: 9*/ { 4, TEMOD16_PMA_OS_MODE_4, TEMOD16_PLL_MODE_DIV_80, 0, 0, 0}, 88 /*SPEED_10G_X4: TBD 10/0xa*/ { 4, TEMOD16_PMA_OS_MODE_4, TEMOD16_PLL_MODE_DIV_80, 0, 0, 1}, 89 /*SPEED_13G_X4 :NA 11/0xb*/ { 4, TEMOD16_PMA_OS_MODE_2, TEMOD16_PLL_MODE_DIV_52, 0, 0, 1}, 90 /*SPEED_15G_X4 : 12/0xc*/ { 4, TEMOD16_PMA_OS_MODE_2, TEMOD16_PLL_MODE_DIV_60, 0, 0, 1}, 91 /*SPEED_16G_X4 : 13/0xd*/ { 4, TEMOD16_PMA_OS_MODE_2, TEMOD16_PLL_MODE_DIV_64, 0, 0, 1}, 92 /*SPEED_20G_CX4: 14/0xe*/ { 4, TEMOD16_PMA_OS_MODE_1, TEMOD16_PLL_MODE_DIV_80, 0, 0, 1}, 93 /*SPEED_10G_CX2 : TBD 15/0xf*/ { 2, TEMOD16_PMA_OS_MODE_2, TEMOD16_PLL_MODE_DIV_80, 0, 0, 1}, 94 /*SPEED_10G_X2 : 16/0x10*/ { 2, TEMOD16_PMA_OS_MODE_2, TEMOD16_PLL_MODE_DIV_80, 1, 0, 1}, 95 /*SPEED_20G_X4: TBD 17/0x11*/ { 4, TEMOD16_PMA_OS_MODE_2, TEMOD16_PLL_MODE_DIV_80, 1, 0, 1}, 96 /*SPEED_10p5G_X2:NA 18/0x12*/ { 2, TEMOD16_PMA_OS_MODE_1, TEMOD16_PLL_MODE_DIV_42, 1, 0, 0}, 97 /*SPEED_21G_X4:NA 19/0x13*/ { 4, TEMOD16_PMA_OS_MODE_1, TEMOD16_PLL_MODE_DIV_42, 1, 0, 0}, 98 /*SPEED_12p7G_X2 :NA 20/0x14*/ { 2, TEMOD16_PMA_OS_MODE_1, TEMOD16_PLL_MODE_DIV_42, 1, 0, 0}, 99 /*SPEED_25p45G_X4:NA 21/0x15*/ { 4, TEMOD16_PMA_OS_MODE_1, TEMOD16_PLL_MODE_DIV_42, 1, 0, 0}, 100 /*SPEED_15p75G_X2:NA 22/0x16*/ { 2, TEMOD16_PMA_OS_MODE_1, TEMOD16_PLL_MODE_DIV_52, 1, 0, 0}, 101 /*SPEED_31p5G_X4:NA 23/0x17*/ { 4, TEMOD16_PMA_OS_MODE_1, TEMOD16_PLL_MODE_DIV_52, 1, 0, 0}, 102 /*SPEED_31p5G_KR4:NA 24/0x18*/ { 4, TEMOD16_PMA_OS_MODE_1, TEMOD16_PLL_MODE_DIV_52, 1, 0, 0}, 103 /*SPEED_20G_CX2: 25/0x19*/ { 2, TEMOD16_PMA_OS_MODE_1, TEMOD16_PLL_MODE_DIV_66, 1, 0, 0}, 104 /*SPEED_20G_X2: 26/0x1a*/ { 2, TEMOD16_PMA_OS_MODE_1, TEMOD16_PLL_MODE_DIV_66, 1, 0, 0}, 105 /*SPEED_40G_X4: 27/0x1b*/ { 2, TEMOD16_PMA_OS_MODE_1, TEMOD16_PLL_MODE_DIV_66, 1, 0, 0}, 106 /*SPEED_10G_KR1: 28/0x1c*/ { 0, TEMOD16_PMA_OS_MODE_1, TEMOD16_PLL_MODE_DIV_66, 1, 0, 0}, 107 /*SPEED_10p6_X1: 29/0x1d*/ { 0, TEMOD16_PMA_OS_MODE_1, TEMOD16_PLL_MODE_DIV_70, 1, 0, 0}, 108 /*SPEED_20G_KR2 30/0x1e*/ { 2, TEMOD16_PMA_OS_MODE_1, TEMOD16_PLL_MODE_DIV_66, 1, 0, 0}, 109 /*SPEED_20G_CR2 31/0x1f*/ { 2, TEMOD16_PMA_OS_MODE_1, TEMOD16_PLL_MODE_DIV_66, 1, 0, 0}, 110 /*SPEED_21G_X2 TBD 32/0x20*/ { 2, TEMOD16_PMA_OS_MODE_1, TEMOD16_PLL_MODE_DIV_70, 1, 0, 0}, 111 /*SPEED_40G_KR4 33/0x21*/ { 4, TEMOD16_PMA_OS_MODE_1, TEMOD16_PLL_MODE_DIV_66, 1, 0, 0}, 112 /*SPEED_40G_CR4 34/0x22*/ { 4, TEMOD16_PMA_OS_MODE_1, TEMOD16_PLL_MODE_DIV_66, 1, 0, 0}, 113 /*SPEED_42G_X4 35/0x23*/ { 4, TEMOD16_PMA_OS_MODE_1, TEMOD16_PLL_MODE_DIV_70, 1, 0, 0}, 114 /*SPEED_100G_CR10 TBD 36/0x24*/ {10, TEMOD16_PMA_OS_MODE_1, TEMOD16_PLL_MODE_DIV_66, 1, 0, 0}, 115 /*SPEED_107G_CR10 TBD 37/0x25*/ {10, TEMOD16_PMA_OS_MODE_1, TEMOD16_PLL_MODE_DIV_70, 1, 0, 0}, 116 /*SPEED_120G_X12 TBD 38/0x26*/ {12, TEMOD16_PMA_OS_MODE_1, TEMOD16_PLL_MODE_DIV_66, 1, 0, 0}, 117 /*SPEED_127G_X12 TBD 39/0x27*/ {12, TEMOD16_PMA_OS_MODE_1, TEMOD16_PLL_MODE_DIV_70, 1, 0, 0}, 118 /*SPEED_12.12G_KR1: 40/0x28*/ { 0, TEMOD16_PMA_OS_MODE_1, TEMOD16_PLL_MODE_DIV_80, 1, 0, 0}, 119 /*SPEED_24.24G_KR2 41/0x29*/ { 2, TEMOD16_PMA_OS_MODE_1, TEMOD16_PLL_MODE_DIV_80, 1, 0, 0}, 120 /*SPEED_48.48G_KR4 42/0x2a*/ { 4, TEMOD16_PMA_OS_MODE_1, TEMOD16_PLL_MODE_DIV_80, 1, 0, 0}, 121 /*SPEED_ILLEGAL 43/0x2b*/ { 0, TEMOD16_PMA_OS_MODE_5, TEMOD16_PLL_MODE_DIV_40, 0, 0, 0}, 122 /*SPEED_ILLEGAL 44/0x2c*/ { 0, TEMOD16_PMA_OS_MODE_5, TEMOD16_PLL_MODE_DIV_40, 0, 0, 0}, 123 /*SPEED_ILLEGAL 45/0x2d*/ { 0, TEMOD16_PMA_OS_MODE_5, TEMOD16_PLL_MODE_DIV_40, 0, 0, 0}, 124 /*SPEED_ILLEGAL 46/0x2e*/ { 0, TEMOD16_PMA_OS_MODE_5, TEMOD16_PLL_MODE_DIV_40, 0, 0, 0}, 125 /*SPEED_ILLEGAL 47/0x2f*/ { 0, TEMOD16_PMA_OS_MODE_5, TEMOD16_PLL_MODE_DIV_40, 0, 0, 0}, 126 /*SPEED_ILLEGAL 48/0x30*/ { 0, TEMOD16_PMA_OS_MODE_5, TEMOD16_PLL_MODE_DIV_40, 0, 0, 0}, 127 /*SPEED_5G_KR1 49/0x31*/ { 1, TEMOD16_PMA_OS_MODE_2, TEMOD16_PLL_MODE_DIV_66, 0, 0, 0}, 128 /*SPEED_10p5G_X4 50/0x32*/ { 2, TEMOD16_PMA_OS_MODE_2, TEMOD16_PLL_MODE_DIV_42, 0, 0, 0}, 129 /*SPEED_ILLEGAL 51/0x33*/ { 0, TEMOD16_PMA_OS_MODE_5, TEMOD16_PLL_MODE_DIV_40, 0, 0, 0}, 130 /*SPEED_ILLEGAL 52/0x33*/ { 0, TEMOD16_PMA_OS_MODE_5, TEMOD16_PLL_MODE_DIV_40, 0, 0, 0}, 131 /*SPEED_10M_10p3125 53/0x35*/ { 1, TEMOD16_PMA_OS_MODE_8_25, TEMOD16_PLL_MODE_DIV_66, 0, 0, 0}, 132 /*SPEED_100M_10p3125 54/0x36*/ { 1, TEMOD16_PMA_OS_MODE_8_25, TEMOD16_PLL_MODE_DIV_66, 0, 0, 0}, 133 /*SPEED_1000M_10p3125 55/0x37*/ { 1, TEMOD16_PMA_OS_MODE_8_25, TEMOD16_PLL_MODE_DIV_66, 0, 0, 0}, 134 /*SPEED_2p5G_X1_10p3125 56/0x38*/ { 1, TEMOD16_PMA_OS_MODE_3_3, TEMOD16_PLL_MODE_DIV_66, 0, 0, 0}, 135 /*SPEED_10G_KX4_10p3125: 57/0x39*/ { 4, TEMOD16_PMA_OS_MODE_3_3, TEMOD16_PLL_MODE_DIV_66, 0, 0, 0}, 136 /*SPEED_10G_CX4_10p3125: 58/0x3a*/ { 4, TEMOD16_PMA_OS_MODE_3_3, TEMOD16_PLL_MODE_DIV_66, 0, 0, 0}, 137 /*SPEED_10G_X4_10p3125: 59/0x3b*/ { 4, TEMOD16_PMA_OS_MODE_3_3, TEMOD16_PLL_MODE_DIV_66, 0, 0, 0}, 138 /*SPEED_ILLEGAL 60/0x3c*/ { 0, TEMOD16_PMA_OS_MODE_5, TEMOD16_PLL_MODE_DIV_40, 0, 0, 0} 139 140 }; 141 #endif 142 143 int _temod16_set_port_mode_select(PHYMOD_ST *pc); 144 int _configure_sc_speed_configuration(PHYMOD_ST* pc); 145 int _init_pcs_fs(PHYMOD_ST* pc); 146 int _init_pcs_an(PHYMOD_ST* pc); 147 int _temod16_wait_sc_stats_set(PHYMOD_ST* pc); 148 int _configure_st_entry(int st_entry_num, int st_entry_speed, PHYMOD_ST* pc); 149 150 #ifdef _DV_TB_ 151 int temod16_set_an_port_mode(PHYMOD_ST* pc); 152 int temod16_autoneg_set(PHYMOD_ST* pc); 153 int temod16_autoneg_control(PHYMOD_ST* pc); 154 int temod16_clause72_control(PHYMOD_ST* pc, cl72_type_t cl_72_type); 155 int temod16_prbs_check(PHYMOD_ST* pc, int real_check, int *prbs_status); 156 int temod16_prbs_mode(PHYMOD_ST* pc, int port, int prbs_inv, int pat, int check_mode); 157 int temod16_prbs_control(PHYMOD_ST* pc, int prbs_enable); 158 int temod16_prbs_rx_enable_set(PHYMOD_ST* pc, int enable); 159 int temod16_prbs_tx_enable_set(PHYMOD_ST* pc, int enable); 160 int temod16_prbs_rx_invert_data_set(PHYMOD_ST* pc, int invert_data); 161 int temod16_prbs_rx_check_mode_set(PHYMOD_ST* pc, int check_mode); 162 int temod16_prbs_tx_invert_data_set(PHYMOD_ST* pc, int invert_data); 163 int temod16_prbs_tx_polynomial_set(PHYMOD_ST* pc, prbs_polynomial_type_t prbs_polynomial); 164 int temod16_prbs_rx_polynomial_set(PHYMOD_ST* pc, prbs_polynomial_type_t prbs_polynomial); 165 int temod16_pmd_lane_swap(PHYMOD_ST *pc); 166 int temod16_check_sc_stats(PHYMOD_ST* pc); 167 int temod16_pmd_native_mode_set(PHYMOD_ST* pc, temod16_spd_intfc_type spd_intf); 168 #endif /* _DV_TB_ */ 169 170 /*! 171 @brief This function reads TX-PLL PLL_LOCK bit. 172 @param pc handle to current TSCE context (#PHYMOD_ST) 173 @param lockStatus reference which is updated with lock status. 174 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 175 @details Read PLL lock status. Returns 1 or 0 (locked/not) 176 */ 177 178 int temod16_pll_lock_get(PHYMOD_ST* pc, int* lockStatus) 179 { 180 PMD_X1_STSr_t reg_pmd_x1_sts; 181 TMOD_DBG_IN_FUNC_INFO(pc); 182 READ_PMD_X1_STSr(pc, ®_pmd_x1_sts); 183 184 *lockStatus = PMD_X1_STSr_PLL_LOCK_STSf_GET(reg_pmd_x1_sts); 185 return PHYMOD_E_NONE; 186 } 187 188 /** 189 @brief This function reads TX-PMD PMD_LOCK bit. 190 @param pc handle to current TSCE context (#PHYMOD_ST) 191 @param lockStatus reference which is updated with pmd_lock status 192 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 193 @details Read PMD lock status Returns 1 or 0 (locked/not) 194 */ 195 196 int temod16_pmd_lock_get(PHYMOD_ST* pc, uint32_t* lockStatus) 197 { 198 PMD_X4_STSr_t reg_pmd_x4_sts; 199 int i = 0, start_lane = 0, num_lane = 0; 200 phymod_access_t pa_copy; 201 202 TMOD_DBG_IN_FUNC_INFO(pc); 203 *lockStatus = 1; 204 PHYMOD_MEMCPY(&pa_copy, pc, sizeof(pa_copy)); 205 206 PHYMOD_IF_ERR_RETURN 207 (phymod_util_lane_config_get(pc, &start_lane, &num_lane)); 208 209 for(i=0; i<num_lane; i++) { 210 if(((pc->lane_mask >> (start_lane + i)) & 0x1) == 1) { 211 pa_copy.lane_mask |= 0x1 << (start_lane + i); 212 READ_PMD_X4_STSr(&pa_copy, ®_pmd_x4_sts); 213 *lockStatus = *lockStatus & PMD_X4_STSr_RX_LOCK_STSf_GET(reg_pmd_x4_sts); 214 } 215 } 216 217 return PHYMOD_E_NONE; 218 } 219 220 #ifdef _DV_TB_ 221 /* 222 @brief This function waits for TX-PLL PLL_LOCK bit. The register is one copy 223 @param pc handle to current TSCE context (#PHYMOD_ST) 224 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 225 @details Wait for PLL to lock. Cannot be used in SDK. 226 */ 227 228 int temod16_pll_lock_wait(PHYMOD_ST* pc, int timeOutValue) 229 { 230 int rv; 231 TMOD_DBG_IN_FUNC_INFO(pc); 232 233 rv = temod16_regbit_set_wait_check(pc, 234 0x9012, 235 1, 1, timeOutValue); 236 /* TBD PMD_X1_STATUS_PLL_LOCK_STS_MASK, 1, timeOutValue); */ 237 if (rv == SOC_E_TIMEOUT) { 238 PHYMOD_DEBUG_ERROR(("%-22s ERROR: p=%0d Timeout PLL lock:\n", __func__, pc->port)); 239 return (SOC_E_TIMEOUT); 240 } 241 return PHYMOD_E_NONE; 242 } 243 #endif 244 245 #ifdef _DV_TB_ 246 /* 247 @brief This function waits for the the RX-PMD to lock. 248 @param pc handle to current TSCE context (#PHYMOD_ST) 249 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 250 @details This function has a time out limit (TE_PLL_WAIT*50) micro-second in driver. 251 or TE_PLL_WAIT/20 pulling count in simualtion, if per_lane_control is set. Otherwise, 252 if per_lane_control==0, it reads back PMD_LIVE_STATUS and put it on accData. 253 */ 254 int temod16_wait_pmd_lock(PHYMOD_ST* pc, int timeOutValue, int* lockStatus) 255 { 256 int rv; 257 PMD_X4_STSr_t reg_pmd_x4_stats; 258 TMOD_DBG_IN_FUNC_INFO(pc); 259 260 PMD_X4_STSr_CLR(reg_pmd_x4_stats); 261 262 if (pc->per_lane_control) { 263 rv = temod16_regbit_set_wait_check(pc, 0xc012, 1,1,timeOutValue); 264 /* TBD PMD_X4_STATUS_RX_LOCK_STS_MASK,1,timeOutValue); */ 265 266 if (rv == SOC_E_TIMEOUT) { 267 PHYMOD_DEBUG_ERROR(("%-22s ERROR: P=%0d Timeout RX PMD lock:\n", __func__, pc->port)); 268 pc->accData = 0; 269 *lockStatus = 0; 270 return rv; 271 } else { 272 pc->accData = 1; 273 *lockStatus = 1; 274 } 275 } else { 276 READ_PMD_X4_STSr(pc, ®_pmd_x4_stats); 277 if (PMD_X4_STSr_RX_LOCK_STSf_GET(reg_pmd_x4_stats)) { 278 pc->accData = 1; 279 *lockStatus = 1; 280 } else { 281 pc->accData = 0; 282 *lockStatus = 0; 283 } 284 } 285 return (PHYMOD_E_NONE); 286 } 287 #endif 288 289 /** 290 @brief controls PCS Bypass Control function. 291 @param pc handle to current TSCE context (#PHYMOD_ST) 292 @param cntl Control value (bypass, un-bypass) 293 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 294 @details Set cntl <B>0 to disable</B> PCS and <B>1 to enable</B> PCS 295 When bypassed, PCS relinquishes control of PMD resets and PCS logic programming. 296 TEMod can take complete control of PMD programming. Bypass is also used in ILKN 297 mode where the PCS is not used. 298 299 */ 300 int temod16_pcs_bypass_ctl (PHYMOD_ST* pc, int cntl) 301 { 302 SC_X4_BYPASSr_t reg_sc_bypass; 303 304 TMOD_DBG_IN_FUNC_INFO(pc); 305 SC_X4_BYPASSr_CLR(reg_sc_bypass); 306 307 if (cntl==TEMOD16_SC_MODE_BYPASS) { 308 SC_X4_BYPASSr_SC_BYPASSf_SET(reg_sc_bypass, 1); 309 } else { 310 SC_X4_BYPASSr_SC_BYPASSf_SET(reg_sc_bypass, 0); 311 } 312 313 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X4_BYPASSr( pc, reg_sc_bypass)); 314 315 return PHYMOD_E_NONE; 316 } 317 318 #ifdef _DV_TB_ 319 /** 320 @brief Controls PMD datapath resets. 321 @param pc handle to current TSCE context (#PHYMOD_ST) 322 @param cntl Controls if PMD should be reset or unset 323 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 324 @details Set cntl arg <B>0</B>:disable <B>1</B>: enable 325 The PMD datapath is reset even if PCS is actively controlling PMD resets. 326 There are two types of control. One per lane and one per Core. 327 */ 328 int temod16_pmd_reset_bypass (PHYMOD_ST* pc, int cntl) /* PMD_RESET_BYPASS */ 329 { 330 int lnCntl, coreCntl; 331 lnCntl = cntl & 0x10 ; 332 coreCntl = cntl & 0x1 ; 333 PMD_X4_OVRRr_t reg_pmd_x4_or; 334 PMD_X4_CTLr_t reg_pmd_x4_ctrl; 335 PMD_X1_OVRRr_t reg_pmd_x1_or; 336 PMD_X1_CTLr_t reg_pmd_x1_ctrl; 337 SC_X4_CTLr_t reg_sc_ctrl; 338 339 TMOD_DBG_IN_FUNC_INFO(pc); 340 PMD_X4_OVRRr_CLR(reg_pmd_x4_or); 341 PMD_X4_CTLr_CLR(reg_pmd_x4_ctrl); 342 PMD_X1_OVRRr_CLR(reg_pmd_x1_or); 343 PMD_X1_CTLr_CLR(reg_pmd_x1_ctrl); 344 SC_X4_CTLr_CLR(reg_sc_ctrl); 345 346 if (lnCntl) { 347 PMD_X4_OVRRr_LN_RX_DP_H_RSTB_OENf_SET(reg_pmd_x4_or, 1); 348 PMD_X4_OVRRr_LN_TX_DP_H_RSTB_OENf_SET(reg_pmd_x4_or, 1); 349 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X4_OVRRr(pc, reg_pmd_x4_or)); 350 351 PMD_X4_CTLr_LN_RX_DP_H_RSTBf_SET(reg_pmd_x4_ctrl, 0); 352 PMD_X4_CTLr_LN_TX_DP_H_RSTBf_SET(reg_pmd_x4_ctrl, 0); 353 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X4_CTLr(pc, reg_pmd_x4_ctrl)); 354 355 /* toggle added */ 356 PMD_X4_OVRRr_CLR(reg_pmd_x4_or); 357 PMD_X4_CTLr_CLR(reg_pmd_x4_ctrl); 358 359 PMD_X4_CTLr_LN_RX_DP_H_RSTBf_SET(reg_pmd_x4_ctrl, 1); 360 PMD_X4_CTLr_LN_TX_DP_H_RSTBf_SET(reg_pmd_x4_ctrl, 1); 361 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X4_CTLr(pc, reg_pmd_x4_ctrl)); 362 363 PMD_X4_OVRRr_LN_RX_DP_H_RSTB_OENf_SET(reg_pmd_x4_or, 0); 364 PMD_X4_OVRRr_LN_TX_DP_H_RSTB_OENf_SET(reg_pmd_x4_or, 0); 365 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X4_OVRRr(pc, reg_pmd_x4_or)); 366 367 } else { 368 PMD_X4_OVRRr_LN_RX_DP_H_RSTB_OENf_SET(reg_pmd_x4_or, 0); 369 PMD_X4_OVRRr_LN_TX_DP_H_RSTB_OENf_SET(reg_pmd_x4_or, 0); 370 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X4_OVRRr(pc, reg_pmd_x4_or)); 371 372 PMD_X4_CTLr_LN_RX_DP_H_RSTBf_SET(reg_pmd_x4_ctrl, 1); 373 PMD_X4_CTLr_LN_TX_DP_H_RSTBf_SET(reg_pmd_x4_ctrl, 1); 374 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X4_CTLr(pc, reg_pmd_x4_ctrl)); 375 } 376 377 if (coreCntl) { 378 PMD_X1_OVRRr_CORE_DP_H_RSTB_OENf_SET(reg_pmd_x1_or, 1); 379 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X1_OVRRr(pc, reg_pmd_x1_or)); 380 381 PMD_X1_CTLr_CORE_DP_H_RSTBf_SET(reg_pmd_x1_ctrl, 0); 382 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X1_CTLr(pc, reg_pmd_x1_ctrl)); 383 384 /* toggle added */ 385 PMD_X1_OVRRr_CLR(reg_pmd_x1_or); 386 PMD_X1_CTLr_CLR(reg_pmd_x1_ctrl); 387 PMD_X1_CTLr_CORE_DP_H_RSTBf_SET(reg_pmd_x1_ctrl, 1); 388 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X1_CTLr(pc, reg_pmd_x1_ctrl)); 389 390 PMD_X1_OVRRr_CORE_DP_H_RSTB_OENf_SET(reg_pmd_x1_or, 0); 391 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X1_OVRRr(pc, reg_pmd_x1_or)); 392 393 } else { 394 PMD_X1_OVRRr_CORE_DP_H_RSTB_OENf_SET(reg_pmd_x1_or, 0); 395 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X1_OVRRr(pc, reg_pmd_x1_or)); 396 397 PMD_X1_CTLr_CORE_DP_H_RSTBf_SET(reg_pmd_x1_ctrl, 1); 398 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X1_CTLr(pc, reg_pmd_x1_ctrl)); 399 } 400 401 /* sw_speed_change toggled */ 402 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(reg_sc_ctrl, 0); 403 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_CTLr(pc, reg_sc_ctrl)); 404 405 SC_X4_CTLr_CLR(reg_sc_ctrl); 406 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(reg_sc_ctrl, 1); 407 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_CTLr(pc, reg_sc_ctrl)); 408 409 return PHYMOD_E_NONE; 410 411 } /* PMD_RESET_BYPASS */ 412 #endif 413 414 #ifdef _SDK_TEMOD16_ 415 /*! 416 \brief Controls the init setting/resetting of autoneg registers. 417 \param pc handle to current TSCE context (#PHYMOD_ST) 418 \param temod16_an_init_t structure with all the onr time autoneg init cfg. 419 \returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 420 \details Get aneg features via #temod16_an_init_t. 421 This does not start the autoneg. That is done in temod16_autoneg_control 422 423 */ 424 int temod16_autoneg_set_init(PHYMOD_ST* pc, temod16_an_init_t *an_init_st) /* AUTONEG_SET */ 425 { 426 AN_X4_CTLSr_t reg_an_ctrl; 427 DIGITAL_CTL1000X2r_t reg_ctrl1000x2; 428 AN_X4_LOC_DEV_CL73_BASE_ABIL1r_t reg_an_cl73_abl_1; 429 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_t reg_cl73_abiilities; 430 431 TMOD_DBG_IN_FUNC_INFO(pc); 432 AN_X4_CTLSr_CLR(reg_an_ctrl); 433 AN_X4_CTLSr_AN_FAIL_COUNT_LIMITf_SET(reg_an_ctrl, an_init_st->an_fail_cnt); 434 AN_X4_CTLSr_OUI_CONTROLf_SET(reg_an_ctrl, an_init_st->an_oui_ctrl); 435 AN_X4_CTLSr_LINKFAILTIMER_DISf_SET(reg_an_ctrl, an_init_st->linkfailtimer_dis); 436 AN_X4_CTLSr_LINKFAILTIMERQUAL_ENf_SET(reg_an_ctrl, an_init_st->linkfailtimerqua_en); 437 AN_X4_CTLSr_AN_GOOD_CHECK_TRAPf_SET(reg_an_ctrl, an_init_st->an_good_check_trap); 438 AN_X4_CTLSr_AN_GOOD_TRAPf_SET(reg_an_ctrl, an_init_st->an_good_trap); 439 PHYMOD_IF_ERR_RETURN(WRITE_AN_X4_CTLSr(pc, reg_an_ctrl)); 440 441 DIGITAL_CTL1000X2r_CLR(reg_ctrl1000x2); 442 DIGITAL_CTL1000X2r_DISABLE_REMOTE_FAULT_REPORTINGf_SET(reg_ctrl1000x2, an_init_st->disable_rf_report); 443 PHYMOD_IF_ERR_RETURN(MODIFY_DIGITAL_CTL1000X2r(pc, reg_ctrl1000x2)); 444 445 AN_X4_LOC_DEV_CL73_BASE_ABIL1r_CLR(reg_an_cl73_abl_1); 446 AN_X4_LOC_DEV_CL73_BASE_ABIL1r_CL73_NONCE_MATCH_OVERf_SET(reg_an_cl73_abl_1, an_init_st->cl73_nonce_match_over); 447 AN_X4_LOC_DEV_CL73_BASE_ABIL1r_CL73_NONCE_MATCH_VALf_SET(reg_an_cl73_abl_1, an_init_st->cl73_nonce_match_val); 448 AN_X4_LOC_DEV_CL73_BASE_ABIL1r_BASE_SELECTORf_SET(reg_an_cl73_abl_1, an_init_st->base_selector); 449 AN_X4_LOC_DEV_CL73_BASE_ABIL1r_TRANSMIT_NONCEf_SET(reg_an_cl73_abl_1, ( an_init_st->cl73_transmit_nonce & 0x1f)); 450 PHYMOD_IF_ERR_RETURN ( MODIFY_AN_X4_LOC_DEV_CL73_BASE_ABIL1r(pc, reg_an_cl73_abl_1)); 451 452 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_CLR(reg_cl73_abiilities); 453 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_CL73_REMOTE_FAULTf_SET(reg_cl73_abiilities, ( an_init_st->cl73_remote_fault & 1)); 454 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_LOC_DEV_CL73_BASE_ABIL0r(pc, reg_cl73_abiilities)); 455 456 return PHYMOD_E_NONE; 457 } 458 #endif 459 460 #ifdef _SDK_TEMOD16_ 461 /*! 462 \brief Controls the setting/resetting of autoneg timers. 463 \param pc handle to current TSCE context (#PHYMOD_ST) 464 \returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 465 \details 466 Get aneg features via #PHYMOD_ST->an_tech_ability and write the pages 467 This does not start the autoneg. That is done in temod16_autoneg_control 468 469 */ 470 int temod16_autoneg_timer_init(PHYMOD_ST* pc) /* AUTONEG timer set*/ 471 { 472 473 AN_X1_CL37_RESTARTr_t reg_cl37_restart; 474 AN_X1_CL37_ACKr_t reg_cl37_ack; 475 AN_X1_CL73_BRK_LNKr_t reg_cl73_break_link; 476 AN_X1_CL73_DME_LOCKr_t reg_cl73_dme_lock; 477 AN_X1_LNK_UPr_t reg_link_up; 478 AN_X1_LNK_FAIL_INHBT_TMR_CL72r_t reg_inhibit_timer; 479 AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72r_t reg_inhibit_not_timer; 480 AN_X1_PD_SD_TMRr_t reg_pd_sd_timer; 481 AN_X1_CL37_SYNC_STS_FILTER_TMRr_t reg_sync_status_filter_timer; 482 AN_X1_PD_TO_CL37_LNK_WAIT_TMRr_t reg_link_wait_timer; 483 AN_X1_IGNORE_LNK_TMRr_t reg_ignore_link_timer; 484 AN_X1_DME_PAGE_TMRr_t reg_dme_page_timer; 485 AN_X1_SGMII_CL73_TMR_TYPEr_t reg_sgmii_cl73_timer; 486 487 TMOD_DBG_IN_FUNC_INFO(pc); 488 /*0x9250 AN_X1_TIMERS_cl37_restart */ 489 AN_X1_CL37_RESTARTr_CLR(reg_cl37_restart); 490 AN_X1_CL37_RESTARTr_SET(reg_cl37_restart, 0x29a ); 491 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_CL37_RESTARTr(pc, reg_cl37_restart)); 492 493 /*0x9251 AN_X1_TIMERS_cl37_ack */ 494 AN_X1_CL37_ACKr_CLR(reg_cl37_ack); 495 AN_X1_CL37_ACKr_SET(reg_cl37_ack, 0x29a); 496 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_CL37_ACKr(pc, reg_cl37_ack)); 497 498 /*0x9253 AN_X1_TIMERS_cl73_break_link */ 499 AN_X1_CL73_BRK_LNKr_CLR(reg_cl73_break_link); 500 AN_X1_CL73_BRK_LNKr_SET(reg_cl73_break_link, 0x10ed); 501 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_CL73_BRK_LNKr(pc, reg_cl73_break_link)); 502 503 /*TBD::0x9255 AN_X1_TIMERS_cl73_dme_lock*/ 504 AN_X1_CL73_DME_LOCKr_CLR(reg_cl73_dme_lock); 505 AN_X1_CL73_DME_LOCKr_SET(reg_cl73_dme_lock, 0x14d4); 506 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_CL73_DME_LOCKr(pc, reg_cl73_dme_lock)); 507 508 /*TBD::0x9256 AN_X1_TIMERS_link_up*/ 509 AN_X1_LNK_UPr_CLR(reg_link_up); 510 AN_X1_LNK_UPr_SET(reg_link_up, 0x29a); 511 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_LNK_UPr(pc, reg_link_up)); 512 513 /*0x9257 AN_X1_TIMERS_link_fail_inhibit_timer_cl72*/ 514 AN_X1_LNK_FAIL_INHBT_TMR_CL72r_CLR(reg_inhibit_timer); 515 AN_X1_LNK_FAIL_INHBT_TMR_CL72r_SET(reg_inhibit_timer, 0x8382); 516 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_LNK_FAIL_INHBT_TMR_CL72r(pc, reg_inhibit_timer)); 517 518 /*0x9258 AN_X1_TIMERS_link_fail_inhibit_timer_not_cl72*/ 519 AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72r_CLR(reg_inhibit_not_timer); 520 AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72r_SET(reg_inhibit_not_timer, 0x1ee0); 521 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72r(pc, reg_inhibit_not_timer)); 522 523 /*0x9259 AN_X1_TIMERS_pd_sd_timer*/ 524 AN_X1_PD_SD_TMRr_CLR(reg_pd_sd_timer); 525 AN_X1_PD_SD_TMRr_SET(reg_pd_sd_timer, 0xa6a); 526 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_PD_SD_TMRr(pc, reg_pd_sd_timer)); 527 528 /*0x925a AN_X1_TIMERS_cl72_max_wait_timer*/ 529 AN_X1_CL37_SYNC_STS_FILTER_TMRr_CLR(reg_sync_status_filter_timer); 530 AN_X1_CL37_SYNC_STS_FILTER_TMRr_SET(reg_sync_status_filter_timer, 0x29a); 531 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_CL37_SYNC_STS_FILTER_TMRr(pc, reg_sync_status_filter_timer)); 532 533 /*0x925b AN_X1_TIMERS_PD_TO_CL37_LINK_WAIT_TIMER*/ 534 AN_X1_PD_TO_CL37_LNK_WAIT_TMRr_CLR(reg_link_wait_timer); 535 AN_X1_PD_TO_CL37_LNK_WAIT_TMRr_SET(reg_link_wait_timer, 0xa6a); 536 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_PD_TO_CL37_LNK_WAIT_TMRr(pc, reg_link_wait_timer)); 537 538 /*0x925c AN_X1_TIMERS_ignore_link_timer*/ 539 AN_X1_IGNORE_LNK_TMRr_CLR(reg_ignore_link_timer); 540 AN_X1_IGNORE_LNK_TMRr_SET(reg_ignore_link_timer, 0x29a); 541 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_IGNORE_LNK_TMRr(pc, reg_ignore_link_timer)); 542 543 /*0x925d AN_X1_TIMERS_dme_page_timer*/ 544 AN_X1_DME_PAGE_TMRr_CLR(reg_dme_page_timer); 545 AN_X1_DME_PAGE_TMRr_SET(reg_dme_page_timer, 0x3b5f); 546 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_DME_PAGE_TMRr(pc, reg_dme_page_timer)); 547 548 /*0x925e AN_X1_TIMERS_sgmii_cl73_timer_type*/ 549 AN_X1_SGMII_CL73_TMR_TYPEr_CLR(reg_sgmii_cl73_timer); 550 AN_X1_SGMII_CL73_TMR_TYPEr_SET(reg_sgmii_cl73_timer, 0x6b); 551 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_SGMII_CL73_TMR_TYPEr(pc, reg_sgmii_cl73_timer)); 552 return PHYMOD_E_NONE; 553 } 554 #endif 555 556 #ifdef _DV_TB_ 557 /** 558 @brief Controls the setting/resetting of autoneg advertisement registers. 559 @param pc handle to current TSCE context (#PHYMOD_ST) 560 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 561 @details 562 Get aneg features via #PHYMOD_ST->an_tech_ability and write the pages 563 This does not start the autoneg. That is done in temod16_autoneg_control 564 565 */ 566 int temod16_autoneg_set(PHYMOD_ST* pc) /* AUTONEG_SET */ 567 { 568 569 AN_X4_CTLSr_t reg_an_ctrl; 570 DIGITAL_CTL1000X2r_t reg_ctrl1000x2; 571 AN_X4_LOC_DEV_CL37_BASE_ABILr_t reg_cl37_base_abilities; 572 AN_X4_LOC_DEV_CL37_BAM_ABILr_t reg_cl37_bam_abilities; 573 AN_X4_LOC_DEV_OVER1G_ABIL0r_t reg_over1g_abilities; 574 AN_X4_LOC_DEV_OVER1G_ABIL1r_t reg_over1g_abilities1; 575 AN_X4_LOC_DEV_CL73_BAM_ABILr_t reg_cl73_bam_abilities; 576 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_t reg_cl73_base_abilities; 577 578 TMOD_DBG_IN_FUNC_INFO(pc); 579 AN_X4_CTLSr_CLR(reg_an_ctrl); 580 581 AN_X4_CTLSr_AN_FAIL_COUNT_LIMITf_SET(reg_an_ctrl, pc->an_fail_cnt); 582 AN_X4_CTLSr_OUI_CONTROLf_SET(reg_an_ctrl, pc->an_oui_ctrl); 583 AN_X4_CTLSr_PD_KX_ENf_SET(reg_an_ctrl, pc->pd_kx_en); 584 AN_X4_CTLSr_PD_KX4_ENf_SET(reg_an_ctrl, pc->pd_kx4_en); 585 AN_X4_CTLSr_LINKFAILTIMER_DISf_SET(reg_an_ctrl, pc->linkfailtimer_dis); 586 AN_X4_CTLSr_LINKFAILTIMERQUAL_ENf_SET(reg_an_ctrl, pc->linkfailtimerqua_en); 587 AN_X4_CTLSr_AN_GOOD_CHECK_TRAPf_SET(reg_an_ctrl, pc->an_good_check_trap); 588 AN_X4_CTLSr_AN_GOOD_TRAPf_SET(reg_an_ctrl, pc->an_good_trap); 589 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_CTLSr(pc, reg_an_ctrl)); 590 591 592 DIGITAL_CTL1000X2r_CLR(reg_ctrl1000x2); 593 DIGITAL_CTL1000X2r_DISABLE_REMOTE_FAULT_REPORTINGf_SET(reg_ctrl1000x2, pc->disable_rf_report); 594 PHYMOD_IF_ERR_RETURN(MODIFY_DIGITAL_CTL1000X2r(pc, reg_ctrl1000x2)); 595 596 if (pc->sc_mode == TEMOD16_SC_MODE_AN_CL37) { 597 /* an37 */ 598 if (!(pc->cl37_bam_en)) { 599 AN_X4_LOC_DEV_CL37_BASE_ABILr_CLR(reg_cl37_base_abilities); 600 AN_X4_LOC_DEV_CL37_BASE_ABILr_CL37_AN_RESTART_RESET_DISABLEf_SET(reg_cl37_base_abilities, 1); 601 AN_X4_LOC_DEV_CL37_BASE_ABILr_CL37_SW_RESTART_RESET_DISABLEf_SET (reg_cl37_base_abilities, 1); 602 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_LOC_DEV_CL37_BASE_ABILr(pc, reg_cl37_base_abilities)); 603 } 604 605 /*Local device cl37 base abilities setting*/ 606 /******* Pause Settings ********/ 607 AN_X4_LOC_DEV_CL37_BASE_ABILr_CLR(reg_cl37_base_abilities); 608 if (pc->cl37_an_pause) { 609 AN_X4_LOC_DEV_CL37_BASE_ABILr_CL37_PAUSEf_SET(reg_cl37_base_abilities, (pc->cl37_an_pause & 3)); 610 } 611 /******* Half duplex Settings ********/ 612 if (pc->cl37_an_hd) { 613 AN_X4_LOC_DEV_CL37_BASE_ABILr_CL37_HALF_DUPLEXf_SET(reg_cl37_base_abilities, (pc->cl37_an_hd & 1)); 614 } 615 /******* SGMII Master mode Settings ********/ 616 if (pc->cl37_sgmii_master_mode) { 617 AN_X4_LOC_DEV_CL37_BASE_ABILr_SGMII_MASTER_MODEf_SET(reg_cl37_base_abilities, (pc->cl37_sgmii_master_mode & 1)); 618 } 619 /******* SGMII Speed Settings ********/ 620 /*if (pc->cl37_sgmii_speed) { */ 621 AN_X4_LOC_DEV_CL37_BASE_ABILr_SGMII_SPEEDf_SET(reg_cl37_base_abilities, (pc->cl37_sgmii_speed & 3)); 622 /*}*/ 623 /******* CL37 Next page setting ********/ 624 if (pc->cl37_an_np) { 625 AN_X4_LOC_DEV_CL37_BASE_ABILr_CL37_NEXT_PAGEf_SET(reg_cl37_base_abilities, (pc->cl37_an_np & 1)); 626 } 627 /******* CL37 full duplex ********/ 628 if (pc->cl37_an_fd) { 629 AN_X4_LOC_DEV_CL37_BASE_ABILr_CL37_FULL_DUPLEXf_SET(reg_cl37_base_abilities, (pc->cl37_an_fd & 1)); 630 } 631 /******* SGMII duplex Settings ********/ 632 if (pc->cl37_sgmii_duplex) { 633 AN_X4_LOC_DEV_CL37_BASE_ABILr_SGMII_FULL_DUPLEXf_SET(reg_cl37_base_abilities, (pc->cl37_sgmii_duplex & 1)); 634 } 635 636 637 /***** Setting AN_X4_ABILITIES_ld_base_abilities_1 0xC181 *******/ 638 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_LOC_DEV_CL37_BASE_ABILr(pc, reg_cl37_base_abilities)); 639 640 /*Local device cl37 bam abilities setting*/ 641 642 /******* CL37 Bam AN_X4_ABILITIES_local_device_over1g_abilities_0 setting********/ 643 /* cl37 bam abilities 0xc182 */ 644 AN_X4_LOC_DEV_CL37_BAM_ABILr_CLR(reg_cl37_bam_abilities); 645 AN_X4_LOC_DEV_CL37_BAM_ABILr_CL37_BAM_CODEf_SET(reg_cl37_bam_abilities, (pc->cl37_bam_code & 0x1ff)); 646 AN_X4_LOC_DEV_CL37_BAM_ABILr_OVER1G_ABILITYf_SET(reg_cl37_bam_abilities, (pc->cl37_bam_ovr1g_en & 1)); 647 AN_X4_LOC_DEV_CL37_BAM_ABILr_OVER1G_PAGE_COUNTf_SET(reg_cl37_bam_abilities, (pc->cl37_bam_ovr1g_pgcnt & 3)); 648 649 PHYMOD_IF_ERR_RETURN 650 (MODIFY_AN_X4_LOC_DEV_CL37_BAM_ABILr(pc, reg_cl37_bam_abilities)); 651 652 653 AN_X4_LOC_DEV_OVER1G_ABIL0r_CLR(reg_over1g_abilities); 654 if (pc->cl37_bam_speed) 655 AN_X4_LOC_DEV_OVER1G_ABIL0r_SET(reg_over1g_abilities, (pc->cl37_bam_speed & 0x7ff)); 656 /***** Setting AN_X4_ABILITIES_local_device_over1g_abilities_0 0xC184 *******/ 657 PHYMOD_IF_ERR_RETURN(WRITE_AN_X4_LOC_DEV_OVER1G_ABIL0r(pc, reg_over1g_abilities)); 658 659 /******* CL37 Bam AN_X4_ABILITIES_local_device_over1g_abilities_1 setting********/ 660 AN_X4_LOC_DEV_OVER1G_ABIL1r_CLR(reg_over1g_abilities1); 661 if (pc->cl37_bam_speed) 662 AN_X4_LOC_DEV_OVER1G_ABIL1r_SET(reg_over1g_abilities1,pc->cl37_bam_speed >> 11); 663 /* AN_LOCAL_DEVICE_OVER1G_ABILITIES_1r_BAM_13GBASE_X4f_SET(reg_over1g_abilities1, (pc->cl37_bam_speed >> 11)); */ 664 if (pc->cl37_bam_fec) 665 AN_X4_LOC_DEV_OVER1G_ABIL1r_FECf_SET(reg_over1g_abilities1, (pc->cl37_bam_fec & 1)); 666 if (pc->cl37_bam_hg2) 667 AN_X4_LOC_DEV_OVER1G_ABIL1r_HG2f_SET(reg_over1g_abilities1, (pc->cl37_bam_hg2 & 1)); 668 if (pc->an_abilities_CL72) 669 AN_X4_LOC_DEV_OVER1G_ABIL1r_CL72f_SET(reg_over1g_abilities1, (pc->an_abilities_CL72 & 1)); 670 /***** Setting AN_X4_ABILITIES_local_device_over1g_abilities_0 0xC183 *******/ 671 PHYMOD_IF_ERR_RETURN(WRITE_AN_X4_LOC_DEV_OVER1G_ABIL1r(pc, reg_over1g_abilities1)); 672 673 }/*Completion of CL37 abilities*/ 674 /*CL73 abilities*/ 675 else if (pc->sc_mode == TEMOD16_SC_MODE_AN_CL73) { 676 /*PD to CL37 Enable*/ 677 if (pc->an_pd_to_cl37_enable) { 678 AN_X4_LOC_DEV_CL37_BASE_ABILr_CLR(reg_cl37_base_abilities); 679 AN_X4_LOC_DEV_CL37_BASE_ABILr_AN_PD_TO_CL37_ENABLEf_SET(reg_cl37_base_abilities, 0x1); 680 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_LOC_DEV_CL37_BASE_ABILr(pc, reg_cl37_base_abilities)); 681 AN_X4_LOC_DEV_CL37_BASE_ABILr_CLR(reg_cl37_base_abilities); 682 if (pc->cl37_an_pause) { 683 AN_X4_LOC_DEV_CL37_BASE_ABILr_CL37_PAUSEf_SET(reg_cl37_base_abilities, (pc->cl37_an_pause & 3)); 684 } 685 /******* Half duplex Settings ********/ 686 if (pc->cl37_an_hd) { 687 AN_X4_LOC_DEV_CL37_BASE_ABILr_CL37_HALF_DUPLEXf_SET(reg_cl37_base_abilities, (pc->cl37_an_hd & 1)); 688 } 689 /******* SGMII Master mode Settings ********/ 690 if (pc->cl37_sgmii_master_mode) { 691 AN_X4_LOC_DEV_CL37_BASE_ABILr_SGMII_MASTER_MODEf_SET(reg_cl37_base_abilities, (pc->cl37_sgmii_master_mode & 1)); 692 } 693 /******* SGMII Speed Settings ********/ 694 if (pc->cl37_sgmii_speed) { 695 AN_X4_LOC_DEV_CL37_BASE_ABILr_SGMII_SPEEDf_SET(reg_cl37_base_abilities, (pc->cl37_sgmii_speed & 3)); 696 } 697 /******* CL37 Next page setting ********/ 698 if (pc->cl37_an_np) { 699 AN_X4_LOC_DEV_CL37_BASE_ABILr_CL37_NEXT_PAGEf_SET(reg_cl37_base_abilities, (pc->cl37_an_np & 1)); 700 } 701 /******* CL37 full duplex ********/ 702 if (pc->cl37_an_fd) { 703 AN_X4_LOC_DEV_CL37_BASE_ABILr_CL37_FULL_DUPLEXf_SET(reg_cl37_base_abilities, (pc->cl37_an_fd & 1)); 704 } 705 /******* SGMII duplex Settings ********/ 706 if (pc->cl37_sgmii_duplex) { 707 AN_X4_LOC_DEV_CL37_BASE_ABILr_SGMII_FULL_DUPLEXf_SET(reg_cl37_base_abilities, (pc->cl37_sgmii_duplex & 1)); 708 } 709 710 /***** Setting AN_X4_ABILITIES_ld_base_abilities_1 0xC181 *******/ 711 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_LOC_DEV_CL37_BASE_ABILr(pc, reg_cl37_base_abilities)); 712 } 713 /*CL73 bam abilities setting*/ 714 AN_X4_LOC_DEV_CL73_BAM_ABILr_CLR(reg_cl73_bam_abilities); 715 AN_X4_LOC_DEV_CL73_BAM_ABILr_BAM_20GBASE_KR2f_SET(reg_cl73_bam_abilities,( pc->cl73_bam_speed & 1)); 716 AN_X4_LOC_DEV_CL73_BAM_ABILr_BAM_20GBASE_CR2f_SET(reg_cl73_bam_abilities,((pc->cl73_bam_speed >> 1) & 0x1)); 717 AN_X4_LOC_DEV_CL73_BAM_ABILr_HPAM_20GKR2f_SET(reg_cl73_bam_abilities, ((pc->cl73_bam_speed & 4) >> 2)); 718 AN_X4_LOC_DEV_CL73_BAM_ABILr_CL73_BAM_CODEf_SET(reg_cl73_bam_abilities, (pc->cl73_bam_code & 0x1ff)); 719 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_LOC_DEV_CL73_BAM_ABILr(pc, reg_cl73_bam_abilities)); 720 /*CL73 base abilities_0 setting*/ 721 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_CLR(reg_cl73_base_abilities); 722 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_NEXT_PAGEf_SET(reg_cl73_base_abilities, (pc->cl73_nxt_page & 1)); 723 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_BASE_100GBASE_CR10f_SET(reg_cl73_base_abilities, ((pc->cl73_speed >> 0)& 0x1)); 724 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_BASE_40GBASE_CR4f_SET(reg_cl73_base_abilities, ((pc->cl73_speed >> 1)& 0x1)); 725 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_BASE_40GBASE_KR4f_SET(reg_cl73_base_abilities, ((pc->cl73_speed >> 2)& 0x1)); 726 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_BASE_10GBASE_KRf_SET(reg_cl73_base_abilities, ((pc->cl73_speed >> 3)& 0x1)); 727 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_BASE_10GBASE_KX4f_SET(reg_cl73_base_abilities, ((pc->cl73_speed >> 4)& 0x1)); 728 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_BASE_1000BASE_KXf_SET(reg_cl73_base_abilities, ((pc->cl73_speed >> 5)& 0x1)); 729 730 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_CL73_PAUSEf_SET(reg_cl73_base_abilities, ( pc->cl73_pause & 3)); 731 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_FECf_SET(reg_cl73_base_abilities, ( pc->cl73_fec & 3)); 732 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_CL73_REMOTE_FAULTf_SET(reg_cl73_base_abilities, ( pc->cl73_remote_fault & 1)); 733 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_LOC_DEV_CL73_BASE_ABIL0r(pc, reg_cl73_base_abilities)); 734 } 735 736 return PHYMOD_E_NONE; 737 738 } 739 #endif 740 #ifdef _SDK_TEMOD16_ 741 int temod16_autoneg_set(PHYMOD_ST* pc, 742 temod16_an_ability_t *an_ability_st) /* AUTONEG_SET */ 743 { 744 745 AN_X4_LOC_DEV_CL37_BASE_ABILr_t reg_cl37_base_abilities; 746 AN_X4_LOC_DEV_CL37_BAM_ABILr_t reg_cl37_bam_abilities; 747 AN_X4_LOC_DEV_OVER1G_ABIL0r_t reg_over1g_abilities; 748 AN_X4_LOC_DEV_OVER1G_ABIL1r_t reg_over1g_abilities1; 749 AN_X4_LOC_DEV_CL73_BAM_ABILr_t reg_cl73_bam_abilities; 750 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_t reg_cl73_base_abilities; 751 AN_X4_LOC_DEV_CL73_BASE_ABIL1r_t reg_an_cl73_abl_1; 752 753 TMOD_DBG_IN_FUNC_INFO(pc); 754 755 /* an37 */ 756 AN_X4_LOC_DEV_CL37_BASE_ABILr_CLR(reg_cl37_base_abilities); 757 AN_X4_LOC_DEV_CL37_BASE_ABILr_CL37_AN_RESTART_RESET_DISABLEf_SET(reg_cl37_base_abilities, 1); 758 if((an_ability_st->cl37_adv.an_bam_speed) || (an_ability_st->cl37_adv.an_bam_speed1)) { 759 AN_X4_LOC_DEV_CL37_BASE_ABILr_CL37_AN_RESTART_RESET_DISABLEf_SET(reg_cl37_base_abilities, 0); 760 } 761 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_LOC_DEV_CL37_BASE_ABILr(pc, reg_cl37_base_abilities)); 762 763 /*Local device cl37 base abilities setting*/ 764 AN_X4_LOC_DEV_CL37_BASE_ABILr_CLR(reg_cl37_base_abilities); 765 AN_X4_LOC_DEV_CL37_BASE_ABILr_CL37_PAUSEf_SET(reg_cl37_base_abilities, (an_ability_st->cl37_adv.an_pause & 3)); 766 AN_X4_LOC_DEV_CL37_BASE_ABILr_SGMII_SPEEDf_SET(reg_cl37_base_abilities, (an_ability_st->cl37_adv.cl37_sgmii_speed & 3)); 767 768 AN_X4_LOC_DEV_CL37_BASE_ABILr_CL37_FULL_DUPLEXf_SET(reg_cl37_base_abilities, 1); 769 AN_X4_LOC_DEV_CL37_BASE_ABILr_SGMII_FULL_DUPLEXf_SET(reg_cl37_base_abilities, 1); 770 771 /***** Setting AN_X4_ABILITIES_ld_base_abilities_1 0xC181 *******/ 772 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_LOC_DEV_CL37_BASE_ABILr(pc, reg_cl37_base_abilities)); 773 774 /*Local device cl37 bam abilities setting*/ 775 /******* CL37 Bam AN_X4_ABILITIES_local_device_over1g_abilities_0 setting********/ 776 /* cl37 bam abilities 0xc182 */ 777 /* Once we put this code in init, can remove teh over1g* cfg from here */ 778 AN_X4_LOC_DEV_CL37_BAM_ABILr_CLR(reg_cl37_bam_abilities); 779 AN_X4_LOC_DEV_CL37_BAM_ABILr_CL37_BAM_CODEf_SET(reg_cl37_bam_abilities, 0x2); 780 AN_X4_LOC_DEV_CL37_BAM_ABILr_OVER1G_ABILITYf_SET(reg_cl37_bam_abilities, 0x1); 781 AN_X4_LOC_DEV_CL37_BAM_ABILr_OVER1G_PAGE_COUNTf_SET(reg_cl37_bam_abilities, 0x5); 782 783 PHYMOD_IF_ERR_RETURN 784 (MODIFY_AN_X4_LOC_DEV_CL37_BAM_ABILr(pc, reg_cl37_bam_abilities)); 785 786 AN_X4_LOC_DEV_OVER1G_ABIL0r_CLR(reg_over1g_abilities); 787 AN_X4_LOC_DEV_OVER1G_ABIL1r_CLR(reg_over1g_abilities1); 788 789 if (an_ability_st->cl37_adv.an_bam_speed) 790 AN_X4_LOC_DEV_OVER1G_ABIL0r_SET(reg_over1g_abilities, (an_ability_st->cl37_adv.an_bam_speed & 0x7ff)); 791 if (an_ability_st->cl37_adv.an_bam_speed1) 792 AN_X4_LOC_DEV_OVER1G_ABIL1r_SET(reg_over1g_abilities1, (an_ability_st->cl37_adv.an_bam_speed1 & 0x1fff )); 793 794 795 /******* CL37 Bam AN_X4_ABILITIES_local_device_over1g_abilities_1 setting********/ 796 if (an_ability_st->cl37_adv.an_fec == TEMOD16_FEC_CL74_SUPRTD_REQSTD) 797 AN_X4_LOC_DEV_OVER1G_ABIL1r_FECf_SET(reg_over1g_abilities1, (an_ability_st->cl37_adv.an_fec & 1)); 798 if (an_ability_st->cl37_adv.an_hg2) 799 AN_X4_LOC_DEV_OVER1G_ABIL1r_HG2f_SET(reg_over1g_abilities1, (an_ability_st->cl37_adv.an_hg2 & 1)); 800 if (an_ability_st->cl37_adv.an_cl72) 801 AN_X4_LOC_DEV_OVER1G_ABIL1r_CL72f_SET(reg_over1g_abilities1, (an_ability_st->cl37_adv.an_cl72 & 1)); 802 /***** Setting AN_X4_ABILITIES_local_device_over1g_abilities_0 0xC183 *******/ 803 PHYMOD_IF_ERR_RETURN(WRITE_AN_X4_LOC_DEV_OVER1G_ABIL0r(pc, reg_over1g_abilities)); 804 PHYMOD_IF_ERR_RETURN(WRITE_AN_X4_LOC_DEV_OVER1G_ABIL1r(pc, reg_over1g_abilities1)); 805 /*Completion of CL37 abilities*/ 806 807 /*CL73 abilities*/ 808 /*CL73 bam abilities setting*/ 809 AN_X4_LOC_DEV_CL73_BAM_ABILr_CLR(reg_cl73_bam_abilities); 810 AN_X4_LOC_DEV_CL73_BAM_ABILr_BAM_20GBASE_KR2f_SET(reg_cl73_bam_abilities,( an_ability_st->cl73_adv.an_bam_speed & 1)); 811 AN_X4_LOC_DEV_CL73_BAM_ABILr_BAM_20GBASE_CR2f_SET(reg_cl73_bam_abilities,((an_ability_st->cl73_adv.an_bam_speed >> 1) & 0x1)); 812 AN_X4_LOC_DEV_CL73_BAM_ABILr_HPAM_20GKR2f_SET(reg_cl73_bam_abilities, ((an_ability_st->cl73_adv.an_bam_speed & 4) >> 2)); 813 AN_X4_LOC_DEV_CL73_BAM_ABILr_CL73_BAM_CODEf_SET(reg_cl73_bam_abilities, 0x4); 814 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_LOC_DEV_CL73_BAM_ABILr(pc, reg_cl73_bam_abilities)); 815 /*CL73 base abilities_0 setting*/ 816 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_CLR(reg_cl73_base_abilities); 817 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_BASE_100GBASE_CR10f_SET(reg_cl73_base_abilities, ((an_ability_st->cl73_adv.an_base_speed >> 0)& 0x1)); 818 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_BASE_40GBASE_CR4f_SET(reg_cl73_base_abilities, ((an_ability_st->cl73_adv.an_base_speed >> 1)& 0x1)); 819 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_BASE_40GBASE_KR4f_SET(reg_cl73_base_abilities, ((an_ability_st->cl73_adv.an_base_speed >> 2)& 0x1)); 820 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_BASE_10GBASE_KRf_SET(reg_cl73_base_abilities, ((an_ability_st->cl73_adv.an_base_speed >> 3)& 0x1)); 821 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_BASE_10GBASE_KX4f_SET(reg_cl73_base_abilities, ((an_ability_st->cl73_adv.an_base_speed >> 4)& 0x1)); 822 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_BASE_1000BASE_KXf_SET(reg_cl73_base_abilities, ((an_ability_st->cl73_adv.an_base_speed >> 5)& 0x1)); 823 824 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_CL73_PAUSEf_SET(reg_cl73_base_abilities, ( an_ability_st->cl73_adv.an_pause & 3)); 825 826 if (an_ability_st->cl73_adv.an_fec == TEMOD16_FEC_CL74_SUPRTD_REQSTD) { 827 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_FECf_SET(reg_cl73_base_abilities, 0x3); 828 } else if (an_ability_st->cl73_adv.an_fec == TEMOD16_FEC_SUPRTD_NOT_REQSTD) { 829 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_FECf_SET(reg_cl73_base_abilities, 0x1); 830 } else { 831 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_FECf_SET(reg_cl73_base_abilities, 0x0); 832 } 833 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_LOC_DEV_CL73_BASE_ABIL0r(pc, reg_cl73_base_abilities)); 834 835 /* set cl73 nonce set 0xc340 */ 836 AN_X4_LOC_DEV_CL73_BASE_ABIL1r_CLR(reg_an_cl73_abl_1); 837 AN_X4_LOC_DEV_CL73_BASE_ABIL1r_BASE_SELECTORf_SET(reg_an_cl73_abl_1, 0x1); 838 PHYMOD_IF_ERR_RETURN ( MODIFY_AN_X4_LOC_DEV_CL73_BASE_ABIL1r(pc, reg_an_cl73_abl_1)); 839 840 /* CL72 Enable logic 841 if cl72_en = 1, use the default HT settings, no overrides. 842 If cl72_en=0, then override to disable cl72. 843 */ 844 if((an_ability_st->cl73_adv.an_cl72 & 0x1) == 1) { 845 temod16_override_set(pc, TEMOD16_OVERRIDE_CL72, 0x1); 846 } else { 847 temod16_override_set(pc, TEMOD16_OVERRIDE_CL72, 0x0); 848 } 849 850 return PHYMOD_E_NONE; 851 } 852 #endif /* _SDK_TEMOD16_*/ 853 854 855 /** 856 @brief To get autoneg control registers. 857 @param pc handle to current TSCE context (#PHYMOD_ST) 858 @param an_control details 859 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 860 @details Upper layer software calls this function to get autoneg 861 info. 862 863 <B>How to call:</B><br> 864 <p>Call directly </p> 865 */ 866 int temod16_autoneg_control_get(PHYMOD_ST* pc, temod16_an_control_t *an_control, int *an_complete) 867 { 868 AN_X4_LOC_DEV_CL37_BASE_ABILr_t reg_an_cl37_abl; 869 AN_X4_ENSr_t reg_an_enb; 870 AN_X4_CTLSr_t an_x4_abl_ctrl; 871 AN_X4_AN_MISC_STSr_t an_misc_sts; 872 873 TMOD_DBG_IN_FUNC_INFO(pc); 874 READ_AN_X4_LOC_DEV_CL37_BASE_ABILr(pc, ®_an_cl37_abl); 875 876 if (AN_X4_LOC_DEV_CL37_BASE_ABILr_SGMII_MASTER_MODEf_GET(reg_an_cl37_abl) == 1) { 877 an_control->an_property_type = TEMOD16_AN_PROPERTY_ENABLE_SGMII_MASTER_MODE; 878 } 879 880 READ_AN_X4_CTLSr(pc, &an_x4_abl_ctrl); 881 an_control->pd_kx_en = AN_X4_CTLSr_PD_KX_ENf_GET(an_x4_abl_ctrl); 882 an_control->pd_kx4_en = AN_X4_CTLSr_PD_KX4_ENf_GET(an_x4_abl_ctrl); 883 884 /*Setting X4 abilities*/ 885 READ_AN_X4_ENSr(pc, ®_an_enb); 886 if (AN_X4_ENSr_CL37_BAM_ENABLEf_GET(reg_an_enb) == 1) { 887 an_control->an_type = TEMOD16_AN_MODE_CL37BAM; 888 an_control->enable = 1; 889 } else if (AN_X4_ENSr_CL73_BAM_ENABLEf_GET(reg_an_enb) == 1) { 890 an_control->an_type = TEMOD16_AN_MODE_CL73BAM; 891 an_control->enable = 1; 892 } else if (AN_X4_ENSr_CL73_HPAM_ENABLEf_GET(reg_an_enb) == 1) { 893 an_control->an_type = TEMOD16_AN_MODE_HPAM; 894 an_control->enable = 1; 895 } else if ( AN_X4_ENSr_CL73_ENABLEf_GET(reg_an_enb) == 1) { 896 an_control->an_type = TEMOD16_AN_MODE_CL73; 897 an_control->enable = 1; 898 } else if ( AN_X4_ENSr_CL37_SGMII_ENABLEf_GET(reg_an_enb) == 1) { 899 an_control->an_type = TEMOD16_AN_MODE_SGMII; 900 an_control->enable = 1; 901 } else if ( AN_X4_ENSr_CL37_ENABLEf_GET(reg_an_enb) == 1) { 902 an_control->an_type = TEMOD16_AN_MODE_CL37;; 903 an_control->enable = 1; 904 } else { 905 an_control->an_type = TEMOD16_AN_MODE_NONE; 906 an_control->enable = 0; 907 } 908 909 if (AN_X4_ENSr_HPAM_TO_CL73_AUTO_ENABLEf_GET(reg_an_enb) == 1) { 910 an_control->an_property_type = TEMOD16_AN_PROPERTY_ENABLE_HPAM_TO_CL73_AUTO; 911 } else if (AN_X4_ENSr_CL73_BAM_TO_HPAM_AUTO_ENABLEf_GET(reg_an_enb) == 1) { 912 an_control->an_property_type = TEMOD16_AN_PROPERTY_ENABLE_CL73_BAM_TO_HPAM_AUTO; 913 } else if (AN_X4_ENSr_SGMII_TO_CL37_AUTO_ENABLEf_GET(reg_an_enb) == 1) { 914 an_control->an_property_type = TEMOD16_AN_PROPERTY_ENABLE_SGMII_TO_CL37_AUTO; 915 } else if (AN_X4_ENSr_CL37_BAM_TO_SGMII_AUTO_ENABLEf_GET(reg_an_enb) == 1) { 916 an_control->an_property_type = TEMOD16_AN_PROPERTY_ENABLE_CL37_BAM_to_SGMII_AUTO; 917 } 918 919 an_control->num_lane_adv = AN_X4_ENSr_NUM_ADVERTISED_LANESf_GET(reg_an_enb); 920 921 /* an_complete status */ 922 AN_X4_AN_MISC_STSr_CLR(an_misc_sts); 923 READ_AN_X4_AN_MISC_STSr(pc, &an_misc_sts); 924 *an_complete = AN_X4_AN_MISC_STSr_AN_COMPLETEf_GET(an_misc_sts); 925 926 return PHYMOD_E_NONE; 927 } 928 929 930 /** 931 @brief To get autoneg advertisement registers. 932 @param pc handle to current TSCE context (#PHYMOD_ST) 933 @param an_ability_st, with the local abilities 934 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 935 @details Upper layer software calls this function to get local autoneg 936 info. 937 938 <B>How to call:</B><br> 939 <p>Call directly </p> 940 */ 941 942 int temod16_autoneg_local_ability_get(PHYMOD_ST* pc, temod16_an_ability_t *an_ability_st) 943 { 944 945 AN_X4_LOC_DEV_CL37_BASE_ABILr_t reg_cl37_base_abilities; 946 AN_X4_LOC_DEV_OVER1G_ABIL0r_t reg_over1g_abilities; 947 AN_X4_LOC_DEV_OVER1G_ABIL1r_t reg_over1g_abilities1; 948 AN_X4_LOC_DEV_CL73_BAM_ABILr_t reg_cl73_bam_abilities; 949 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_t reg_cl73_base_abilities; 950 int an_fec; 951 952 TMOD_DBG_IN_FUNC_INFO(pc); 953 READ_AN_X4_LOC_DEV_CL37_BASE_ABILr(pc, ®_cl37_base_abilities); 954 an_ability_st->cl37_adv.an_pause = AN_X4_LOC_DEV_CL37_BASE_ABILr_CL37_PAUSEf_GET(reg_cl37_base_abilities); 955 an_ability_st->cl37_adv.cl37_sgmii_speed = AN_X4_LOC_DEV_CL37_BASE_ABILr_SGMII_SPEEDf_GET(reg_cl37_base_abilities); 956 957 READ_AN_X4_LOC_DEV_OVER1G_ABIL0r(pc, ®_over1g_abilities); 958 an_ability_st->cl37_adv.an_bam_speed = AN_X4_LOC_DEV_OVER1G_ABIL0r_GET(reg_over1g_abilities) & 0x7ff; 959 960 READ_AN_X4_LOC_DEV_OVER1G_ABIL1r(pc, ®_over1g_abilities1); 961 an_ability_st->cl37_adv.an_bam_speed1 = AN_X4_LOC_DEV_OVER1G_ABIL1r_GET(reg_over1g_abilities1) & 0xfff; 962 963 if (AN_X4_LOC_DEV_OVER1G_ABIL1r_FECf_GET(reg_over1g_abilities1)) { 964 an_ability_st->cl37_adv.an_fec = TEMOD16_FEC_CL74_SUPRTD_REQSTD; 965 } else { 966 an_ability_st->cl37_adv.an_fec = TEMOD16_FEC_SUPRTD_NOT_REQSTD; 967 } 968 an_ability_st->cl37_adv.an_cl72 = AN_X4_LOC_DEV_OVER1G_ABIL1r_CL72f_GET(reg_over1g_abilities1); 969 an_ability_st->cl37_adv.an_hg2 = AN_X4_LOC_DEV_OVER1G_ABIL1r_HG2f_GET(reg_over1g_abilities1); 970 971 READ_AN_X4_LOC_DEV_CL73_BAM_ABILr(pc, ®_cl73_bam_abilities); 972 an_ability_st->cl73_adv.an_bam_speed = AN_X4_LOC_DEV_CL73_BAM_ABILr_GET(reg_cl73_bam_abilities) & 0x7; 973 READ_AN_X4_LOC_DEV_CL73_BASE_ABIL0r(pc, ®_cl73_base_abilities); 974 an_ability_st->cl73_adv.an_base_speed = AN_X4_LOC_DEV_CL73_BASE_ABIL0r_GET(reg_cl73_base_abilities) & 0x3f; 975 976 an_ability_st->cl73_adv.an_pause = AN_X4_LOC_DEV_CL73_BASE_ABIL0r_CL73_PAUSEf_GET(reg_cl73_base_abilities); 977 an_fec = AN_X4_LOC_DEV_CL73_BASE_ABIL0r_FECf_GET(reg_cl73_base_abilities); 978 if (an_fec == 0x3) { 979 an_ability_st->cl73_adv.an_fec = TEMOD16_FEC_CL74_SUPRTD_REQSTD; 980 } else if (an_fec == 0x1) { 981 an_ability_st->cl73_adv.an_fec = TEMOD16_FEC_SUPRTD_NOT_REQSTD; 982 } else { 983 an_ability_st->cl73_adv.an_fec = TEMOD16_FEC_NOT_SUPRTD; 984 } 985 986 return PHYMOD_E_NONE; 987 } 988 989 /** 990 @brief To get autoneg advertisement registers. 991 @param pc handle to current TSCE context (#PHYMOD_ST) 992 @param an_ability_st, with the remote abilities 993 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 994 @details Upper layer software calls this function to get autoneg 995 info. 996 */ 997 998 #define AN_X4_LP_MP1024_UP1r_SPEED_ABILITY_20G_CX4f_GET(r) ((((r).an_x4_lp_mp1024_up1[0]) >> 10) & 0x1) 999 #define AN_X4_LP_MP1024_UP1r_SPEED_ABILITY_16G_X4f_GET(r) ((((r).an_x4_lp_mp1024_up1[0]) >> 9) & 0x1) 1000 #define AN_X4_LP_MP1024_UP1r_SPEED_ABILITY_15G_X4f_GET(r) ((((r).an_x4_lp_mp1024_up1[0]) >> 8) & 0x1) 1001 #define AN_X4_LP_MP1024_UP1r_SPEED_ABILITY_13G_X4f_GET(r) ((((r).an_x4_lp_mp1024_up1[0]) >> 7) & 0x1) 1002 #define AN_X4_LP_MP1024_UP1r_SPEED_ABILITY_12P5G_X4f_GET(r) ((((r).an_x4_lp_mp1024_up1[0]) >> 6) & 0x1) 1003 #define AN_X4_LP_MP1024_UP1r_SPEED_ABILITY_12G_X4f_GET(r) ((((r).an_x4_lp_mp1024_up1[0]) >> 5) & 0x1) 1004 #define AN_X4_LP_MP1024_UP1r_SPEED_ABILITY_10G_CX4f_GET(r) ((((r).an_x4_lp_mp1024_up1[0]) >> 4) & 0x1) 1005 #define AN_X4_LP_MP1024_UP1r_SPEED_ABILITY_10G_X4f_GET(r) ((((r).an_x4_lp_mp1024_up1[0]) >> 3) & 0x1) 1006 #define AN_X4_LP_MP1024_UP1r_SPEED_ABILITY_6G_X4f_GET(r) ((((r).an_x4_lp_mp1024_up1[0]) >> 2) & 0x1) 1007 #define AN_X4_LP_MP1024_UP1r_SPEED_ABILITY_5G_X4f_GET(r) ((((r).an_x4_lp_mp1024_up1[0]) >> 1) & 0x1) 1008 #define AN_X4_LP_MP1024_UP1r_SPEED_ABILITY_2P5G_X1f_GET(r) (((r).an_x4_lp_mp1024_up1[0]) & 0x1) 1009 1010 #define AN_X4_LP_BASE_PAGE2r_SPEED_100G_CR10f_GET(r) ((((r).an_x4_lp_base_page2[0]) >> 10) & 0x1) 1011 #define AN_X4_LP_BASE_PAGE2r_SPEED_40G_CR4f_GET(r) ((((r).an_x4_lp_base_page2[0]) >> 9) & 0x1) 1012 #define AN_X4_LP_BASE_PAGE2r_SPEED_40G_KR4f_GET(r) ((((r).an_x4_lp_base_page2[0]) >> 8) & 0x1) 1013 #define AN_X4_LP_BASE_PAGE2r_SPEED_10G_KR_ABILITYf_GET(r) ((((r).an_x4_lp_base_page2[0]) >> 7) & 0x1) 1014 #define AN_X4_LP_BASE_PAGE2r_SPEED_10G_KX4_ABILITYf_GET(r) ((((r).an_x4_lp_base_page2[0]) >> 6) & 0x1) 1015 #define AN_X4_LP_BASE_PAGE2r_SPEED_1G_KX_ABILITYf_GET(r) ((((r).an_x4_lp_base_page2[0]) >> 5) & 0x1) 1016 1017 #define AN_X4_LP_MP1024_UP3r_SPEED_ABILITY_21G_X4f_GET(r) ((((r).an_x4_lp_mp1024_up3[0]) >> 9) & 0x1) 1018 #define AN_X4_LP_MP1024_UP3r_SPEED_ABILITY_25P45G_X4f_GET(r) ((((r).an_x4_lp_mp1024_up3[0]) >> 8) & 0x1) 1019 #define AN_X4_LP_MP1024_UP3r_SPEED_ABILITY_31P5G_X4f_GET(r) ((((r).an_x4_lp_mp1024_up3[0]) >> 7) & 0x1) 1020 #define AN_X4_LP_MP1024_UP3r_SPEED_ABILITY_32P7Gf_GET(r) ((((r).an_x4_lp_mp1024_up3[0]) >> 6) & 0x1) 1021 #define AN_X4_LP_MP1024_UP3r_SPEED_ABILITY_40G_X4f_GET(r) ((((r).an_x4_lp_mp1024_up3[0]) >> 5) & 0x1) 1022 1023 #define AN_X4_LP_MP1024_UP4r_SPEED_ABILITY_1G_CX1f_GET(r) ((((r).an_x4_lp_mp1024_up4[0]) >> 9) & 0x1) 1024 #define AN_X4_LP_MP1024_UP4r_SPEED_ABILITY_10G_CX1f_GET(r) ((((r).an_x4_lp_mp1024_up4[0]) >> 8) & 0x1) 1025 #define AN_X4_LP_MP1024_UP4r_SPEED_ABILITY_15P75G_X2f_GET(r) ((((r).an_x4_lp_mp1024_up4[0]) >> 7) & 0x1) 1026 #define AN_X4_LP_MP1024_UP4r_SPEED_ABILITY_20G_CX2f_GET(r) ((((r).an_x4_lp_mp1024_up4[0]) >> 6) & 0x1) 1027 #define AN_X4_LP_MP1024_UP4r_SPEED_ABILITY_20G_X2f_GET(r) ((((r).an_x4_lp_mp1024_up4[0]) >> 5) & 0x1) 1028 #define AN_X4_LP_MP1024_UP4r_SPEED_ABILITY_12P7G_X2f_GET(r) ((((r).an_x4_lp_mp1024_up4[0]) >> 4) & 0x1) 1029 #define AN_X4_LP_MP1024_UP4r_SPEED_ABILITY_10P5G_X2f_GET(r) ((((r).an_x4_lp_mp1024_up4[0]) >> 3) & 0x1) 1030 #define AN_X4_LP_MP1024_UP4r_SPEED_ABILITY_10G_CX2f_GET(r) ((((r).an_x4_lp_mp1024_up4[0]) >> 2) & 0x1) 1031 #define AN_X4_LP_MP1024_UP4r_SPEED_ABILITY_10G_X2f_GET(r) ((((r).an_x4_lp_mp1024_up4[0]) >> 1) & 0x1) 1032 #define AN_X4_LP_MP1024_UP4r_SPEED_ABILITY_20G_X4f_GET(r) (((r).an_x4_lp_mp1024_up4[0]) & 0x1) 1033 1034 #define AN_X4_LP_MP5_UP3r_USER_DEFINED_CODE_19_11f_GET(r) (((r).an_x4_lp_mp5_up3[0]) & 0x1ff) 1035 #define AN_X4_LP_MP5_UP4r_USER_DEFINED_CODE_10_0f_GET(r) (((r).an_x4_lp_mp5_up4[0]) & 0x7ff) 1036 #define AN_X4_LP_MP1024_UP3r_HIGIG_II_ABILITYf_GET(r) (((r).an_x4_lp_mp1024_up3[0]) & 0x1) 1037 #define AN_X4_LP_MP1024_UP3r_CL74_FEC_ABILITYf_GET(r) ((((r).an_x4_lp_mp1024_up3[0]) >> 1) & 0x1) 1038 #define AN_X4_LP_MP1024_UP3r_CL72_TRAINING_ABILITYf_GET(r) ((((r).an_x4_lp_mp1024_up3[0]) >> 2) & 0x1) 1039 1040 int temod16_autoneg_remote_ability_get(PHYMOD_ST* pc, temod16_an_ability_t *an_ability_st) 1041 { 1042 AN_X4_LP_MP1024_UP1r_t an_x4_up1; 1043 AN_X4_LP_MP1024_UP3r_t an_x4_up3; 1044 AN_X4_LP_MP1024_UP4r_t an_x4_up4; 1045 AN_X4_LP_BASE_PAGE1r_t an_x4_pg1; 1046 AN_X4_LP_BASE_PAGE2r_t an_x4_pg2; 1047 AN_X4_LP_BASE_PAGE3r_t an_x4_pg3; 1048 AN_X4_LP_MP5_UP3r_t an_x4_mp5_up3; 1049 AN_X4_LP_MP5_UP4r_t an_x4_mp5_up4; 1050 1051 uint32_t data; 1052 uint32_t user_code; 1053 1054 TMOD_DBG_IN_FUNC_INFO(pc); 1055 1056 AN_X4_LP_MP1024_UP1r_CLR(an_x4_up1); 1057 AN_X4_LP_MP1024_UP3r_CLR(an_x4_up3); 1058 AN_X4_LP_MP1024_UP4r_CLR(an_x4_up4); 1059 AN_X4_LP_BASE_PAGE1r_CLR(an_x4_pg1); 1060 AN_X4_LP_BASE_PAGE2r_CLR(an_x4_pg2); 1061 AN_X4_LP_BASE_PAGE3r_CLR(an_x4_pg3); 1062 AN_X4_LP_MP5_UP3r_CLR(an_x4_mp5_up3); 1063 AN_X4_LP_MP5_UP4r_CLR(an_x4_mp5_up4); 1064 1065 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LP_MP1024_UP1r(pc, &an_x4_up1)); 1066 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LP_MP1024_UP3r(pc, &an_x4_up3)); 1067 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LP_MP1024_UP4r(pc, &an_x4_up4)); 1068 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LP_BASE_PAGE1r(pc, &an_x4_pg1)); 1069 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LP_BASE_PAGE2r(pc, &an_x4_pg2)); 1070 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LP_BASE_PAGE3r(pc, &an_x4_pg3)); 1071 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LP_MP5_UP3r(pc, &an_x4_mp5_up3)); 1072 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LP_MP5_UP4r(pc, &an_x4_mp5_up4)); 1073 1074 /* data: get the BAM_12GBASE_X4 and BAM_12p5GBASE_X4 */ 1075 data = AN_X4_LP_MP1024_UP1r_SPEED_ABILITY_12G_X4f_GET(an_x4_up1); 1076 data <<= TEMOD16_CL37_BAM_12GBASE_X4; 1077 data |= (AN_X4_LP_MP1024_UP1r_SPEED_ABILITY_12P5G_X4f_GET(an_x4_up1) << TEMOD16_CL37_BAM_12p5GBASE_X4); 1078 1079 /* data: get BAM_10GBASE_X2_CX4, BAM_10GBASE_X2_CX4 and BAM_10p5GBASE_X2 */ 1080 data |= (AN_X4_LP_MP1024_UP4r_SPEED_ABILITY_10P5G_X2f_GET(an_x4_up4) << TEMOD16_CL37_BAM_BAM_10p5GBASE_X2); 1081 data |= (AN_X4_LP_MP1024_UP4r_SPEED_ABILITY_10G_CX2f_GET(an_x4_up4) << TEMOD16_CL37_BAM_10GBASE_X2_CX4); 1082 data |= (AN_X4_LP_MP1024_UP4r_SPEED_ABILITY_10G_X2f_GET(an_x4_up4) << TEMOD16_CL37_BAM_10GBASE_X2); 1083 1084 /* data: get BAM_12p7GBASE_X2 */ 1085 data |= (AN_X4_LP_MP1024_UP4r_SPEED_ABILITY_12P7G_X2f_GET(an_x4_up4) << TEMOD16_CL37_BAM_12p7GBASE_X2); 1086 1087 /* data: get BAM_10GBASE_X4_CX4,BAM_10GBASE_X4,BAM_6GBASE_X4,BAM_5GBASE_X4 and BAM_2P5GBASE_X1 */ 1088 data |= AN_X4_LP_MP1024_UP1r_SPEED_ABILITY_2P5G_X1f_GET(an_x4_up1) << TEMOD16_CL37_BAM_2p5GBASE_X; 1089 data |= AN_X4_LP_MP1024_UP1r_SPEED_ABILITY_5G_X4f_GET(an_x4_up1) << TEMOD16_CL37_BAM_5GBASE_X4; 1090 data |= AN_X4_LP_MP1024_UP1r_SPEED_ABILITY_6G_X4f_GET(an_x4_up1) << TEMOD16_CL37_BAM_6GBASE_X4; 1091 data |= AN_X4_LP_MP1024_UP1r_SPEED_ABILITY_10G_X4f_GET(an_x4_up1) << TEMOD16_CL37_BAM_10GBASE_X4; 1092 data |= AN_X4_LP_MP1024_UP1r_SPEED_ABILITY_10G_CX4f_GET(an_x4_up1) << TEMOD16_CL37_BAM_10GBASE_X4_CX4; 1093 an_ability_st->cl37_adv.an_bam_speed = data; 1094 1095 /* data - get BAM_13GBASE_X4, BAM_15GBASE_X4, BAM_16GBASE_X4 and BAM_20GBASE_CX4 */ 1096 data = AN_X4_LP_MP1024_UP1r_SPEED_ABILITY_13G_X4f_GET(an_x4_up1) << TEMOD16_CL37_BAM_13GBASE_X4; 1097 data |= (AN_X4_LP_MP1024_UP1r_SPEED_ABILITY_15G_X4f_GET(an_x4_up1) << TEMOD16_CL37_BAM_15GBASE_X4); 1098 data |= (AN_X4_LP_MP1024_UP1r_SPEED_ABILITY_16G_X4f_GET(an_x4_up1) << TEMOD16_CL37_BAM_16GBASE_X4); 1099 data |= (AN_X4_LP_MP1024_UP1r_SPEED_ABILITY_20G_CX4f_GET(an_x4_up1) << TEMOD16_CL37_BAM_20GBASE_X4_CX4); 1100 an_ability_st->cl37_adv.an_bam_speed1 = data; 1101 1102 /* data - BAM_15p75GBASE_X2 , BAM_20GBASE_X2*/ 1103 data = AN_X4_LP_MP1024_UP4r_SPEED_ABILITY_15P75G_X2f_GET(an_x4_up4) << TEMOD16_CL37_BAM_15p75GBASE_X2; 1104 data |= (AN_X4_LP_MP1024_UP4r_SPEED_ABILITY_20G_CX2f_GET(an_x4_up4) << TEMOD16_CL37_BAM_20GBASE_X2); 1105 an_ability_st->cl37_adv.an_bam_speed1 |= data; 1106 1107 /* data - - 21G-X4 , 25.45G-X4, 31.5G-X4, 32.7G, 40G-X4 */ 1108 data = AN_X4_LP_MP1024_UP3r_SPEED_ABILITY_21G_X4f_GET(an_x4_up3) << TEMOD16_CL37_BAM_21GBASE_X4; 1109 data |= (AN_X4_LP_MP1024_UP3r_SPEED_ABILITY_25P45G_X4f_GET(an_x4_up3) << TEMOD16_CL37_BAM_25p455GBASE_X4); 1110 data |= (AN_X4_LP_MP1024_UP3r_SPEED_ABILITY_31P5G_X4f_GET(an_x4_up3) << TEMOD16_CL37_BAM_31p5GBASE_X4); 1111 data |= (AN_X4_LP_MP1024_UP3r_SPEED_ABILITY_32P7Gf_GET(an_x4_up3) << TEMOD16_CL37_BAM_32p7GBASE_X4); 1112 data |= (AN_X4_LP_MP1024_UP3r_SPEED_ABILITY_40G_X4f_GET(an_x4_up3) << TEMOD16_CL37_BAM_40GBASE_X4); 1113 an_ability_st->cl37_adv.an_bam_speed1 |= data; 1114 1115 1116 /*an_ability_st->cl73_adv.an_bam_speed = 0xdead;*/ 1117 an_ability_st->cl73_adv.an_bam_speed = 0x0; 1118 1119 /* User-Defined Code[19:11] contains BAM code */ 1120 user_code = AN_X4_LP_MP5_UP3r_USER_DEFINED_CODE_19_11f_GET(an_x4_mp5_up3) << 11; 1121 /* User-Defined Code[10:0] contains BAM abilities */ 1122 data = AN_X4_LP_MP5_UP4r_USER_DEFINED_CODE_10_0f_GET(an_x4_mp5_up4); 1123 1124 if (data & (1<<1)) { 1125 an_ability_st->cl73_adv.an_bam_speed |= (1 << TEMOD16_CL73_BAM_20GBASE_KR2); 1126 } else { 1127 user_code |= data; 1128 if(user_code == 0xabe20){ 1129 an_ability_st->cl73_adv.an_bam_speed |= (1 << TEMOD16_CL73_BAM_20GBASE_KR2); 1130 } 1131 } 1132 if (data & (1<<0)){ 1133 an_ability_st->cl73_adv.an_bam_speed |= (1<< TEMOD16_CL73_BAM_20GBASE_CR2); 1134 } 1135 1136 data = AN_X4_LP_BASE_PAGE2r_SPEED_100G_CR10f_GET(an_x4_pg2) << TEMOD16_CL73_100GBASE_CR10; 1137 data |= AN_X4_LP_BASE_PAGE2r_SPEED_40G_CR4f_GET(an_x4_pg2) << TEMOD16_CL73_40GBASE_CR4; 1138 data |= AN_X4_LP_BASE_PAGE2r_SPEED_40G_KR4f_GET(an_x4_pg2) << TEMOD16_CL73_40GBASE_KR4; 1139 data |= AN_X4_LP_BASE_PAGE2r_SPEED_10G_KR_ABILITYf_GET(an_x4_pg2) << TEMOD16_CL73_10GBASE_KR; 1140 data |= AN_X4_LP_BASE_PAGE2r_SPEED_10G_KX4_ABILITYf_GET(an_x4_pg2) << TEMOD16_CL73_10GBASE_KX4; 1141 data |= AN_X4_LP_BASE_PAGE2r_SPEED_1G_KX_ABILITYf_GET(an_x4_pg2) << TEMOD16_CL73_1000BASE_KX; 1142 an_ability_st->cl73_adv.an_base_speed |= data; 1143 1144 /* check the speed ability and pass it as well */ 1145 an_ability_st->cl37_adv.cl37_sgmii_speed = (AN_X4_LP_BASE_PAGE1r_LP_BASE_PAGE1_PAGE_DATAf_GET(an_x4_pg1) >> 10) & 0x3; 1146 an_ability_st->cl37_adv.an_pause = (AN_X4_LP_BASE_PAGE1r_LP_BASE_PAGE1_PAGE_DATAf_GET(an_x4_pg1) >> 7) & 0x3; 1147 an_ability_st->cl37_adv.an_hg2 = AN_X4_LP_MP1024_UP3r_HIGIG_II_ABILITYf_GET(an_x4_up3); 1148 an_ability_st->cl37_adv.an_fec = AN_X4_LP_MP1024_UP3r_CL74_FEC_ABILITYf_GET(an_x4_up3); 1149 an_ability_st->cl37_adv.an_cl72 = AN_X4_LP_MP1024_UP3r_CL72_TRAINING_ABILITYf_GET(an_x4_up3); 1150 1151 an_ability_st->cl73_adv.an_pause = (AN_X4_LP_BASE_PAGE1r_LP_BASE_PAGE1_PAGE_DATAf_GET(an_x4_pg1) >> 10) & 0x3; 1152 an_ability_st->cl73_adv.an_fec = (AN_X4_LP_BASE_PAGE3r_LP_BASE_PAGE3_PAGE_DATAf_GET(an_x4_pg3) >> 14) & 0x3; 1153 1154 return PHYMOD_E_NONE; 1155 } 1156 1157 1158 1159 /** 1160 @brief Controls setting/resetting of autoneg ability and enabling/disabling 1161 @param pc handle to current TSCE context (#PHYMOD_ST) 1162 @param an_control structure with AN controls 1163 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 1164 1165 This function programs auto-negotiation (AN) modes for the TSCE. It can 1166 enable/disable clause37/clause73/BAM autonegotiation capabilities. Call this 1167 function once for combo mode and once per lane in independent lane mode. 1168 1169 The autonegotiation mode is controlled by setting specific bits of 1170 #PHYMOD_ST::an_type. 1171 1172 The autonegotiation mode is indicated by setting an_type with 1173 1174 \li TEMOD16_AN_NONE (disable AN) 1175 \li TEMOD16_CL73 1176 \li TEMOD16_CL73_BAM 1177 \li TEMOD16_HPAM 1178 */ 1179 1180 #ifdef _DV_TB_ 1181 int temod16_autoneg_control(PHYMOD_ST* pc) 1182 { 1183 uint16_t data ; 1184 uint16_t an_setup_enable, num_advertised_lanes, cl37_bam_enable, cl73_bam_enable ; 1185 uint16_t cl73_hpam_enable, cl73_enable, cl37_sgmii_enable, cl37_enable; 1186 uint16_t cl73_nonce_match_over, cl73_nonce_match_val ,cl73_transmit_nonce; 1187 uint16_t base_selector, cl73_bam_code ; 1188 uint16_t hppam_20gkr2, next_page ; 1189 uint16_t cl37_next_page, cl37_full_duplex; 1190 uint16_t sgmii_full_duplex ; 1191 uint16_t cl37_bam_code, over1g_ability, over1g_page_count; 1192 uint16_t cl37_restart, cl73_restart ; 1193 int no_an ; 1194 AN_X4_LOC_DEV_CL37_BAM_ABILr_t reg_an_cl37_bam_abilities; 1195 /*AN_X4_LOC_DEV_CL73_BASE_ABIL0r_t reg_an_cl73_abl_0; */ 1196 AN_X4_LOC_DEV_CL73_BASE_ABIL1r_t reg_an_cl73_abl_1; 1197 /* AN_X4_LOC_DEV_CL73_BAM_ABILr_t reg_an_cl73_abl; */ 1198 /* UC_COMMAND3r_t reg_com3; */ 1199 AN_X4_ENSr_t reg_an_enb; 1200 TMOD_DBG_IN_FUNC_INFO(pc); 1201 1202 /* TSCE_COMMANDr_t reg_com; 1203 */ 1204 1205 no_an = 0 ; 1206 1207 an_setup_enable = 0x1; 1208 num_advertised_lanes = 0x2; 1209 cl37_bam_enable = 0x0; 1210 cl73_bam_enable = 0x0; 1211 cl73_hpam_enable = 0x0; 1212 cl73_enable = 0x0; 1213 cl37_sgmii_enable = 0x0; 1214 cl37_enable = 0x0; 1215 cl73_nonce_match_over = 0x1; 1216 cl73_transmit_nonce = 0x0; 1217 cl73_nonce_match_val = 0x0; 1218 base_selector = 0x1; 1219 cl73_bam_code = 0x0; 1220 hppam_20gkr2 = 0x0; 1221 next_page = 0x0; 1222 cl37_next_page = 0x0; 1223 cl37_full_duplex = 0x1; 1224 sgmii_full_duplex = 0x1; 1225 cl37_bam_code = 0x0; 1226 over1g_ability = 0x0; 1227 over1g_page_count = 0x0; 1228 cl37_restart = 0x0; 1229 cl73_restart = 0x0; 1230 1231 num_advertised_lanes = pc->no_of_lanes; 1232 1233 /*if (pc-> an_type == TSCMOD_CL73) { 1234 cl73_restart = 0x1; 1235 cl73_enable = 0x1; 1236 cl73_nonce_match_over = 0x1; 1237 cl73_nonce_match_val = 0x0; 1238 base_selector = 0x1; 1239 } else if (pc-> an_type == TSCMOD_CL37) { 1240 cl37_restart = 0x1; 1241 cl37_enable = 0x1; 1242 cl37_bam_code = 0x0; 1243 over1g_ability = 0x0; 1244 over1g_page_count = 0x0; 1245 sgmii_full_duplex = 0x0; 1246 } else if (pc-> an_type == TSCMOD_CL37_BAM) { 1247 cl37_restart = 0x1; 1248 cl37_enable = 0x1; 1249 cl37_bam_enable = 0x1; 1250 cl37_bam_code = 0x1; 1251 over1g_ability = 0x1; 1252 over1g_page_count = 0x1; */ /* PHY-863: =1: 5 pages; =0: 3 pages; WC uses 3 pages */ 1253 /*sgmii_full_duplex = 0x0; 1254 cl37_next_page = 0x1; 1255 } else if (pc-> an_type == TSCMOD_CL37_SGMII) { 1256 cl37_restart = 0x1; 1257 cl37_sgmii_enable = 0x1; 1258 cl37_enable = 0x1; 1259 cl37_bam_code = 0x0; 1260 over1g_ability = 0x0; 1261 over1g_page_count = 0x0; 1262 } else if (pc-> an_type == TSCMOD_CL73_BAM) { 1263 cl73_restart = 0x1; 1264 cl73_enable = 0x1; 1265 cl73_bam_enable = 0x1; 1266 cl73_bam_code = 0x3; 1267 next_page = 0x1; 1268 cl73_nonce_match_over = 0x1; 1269 cl73_nonce_match_val = 0x0; 1270 base_selector = 0x1; 1271 } else if (pc-> an_type == TSCMOD_HPAM) { 1272 cl73_restart = 0x1; 1273 cl73_enable = 0x1; 1274 cl73_hpam_enable = 0x1; 1275 cl73_bam_code = 0x3; 1276 hppam_20gkr2 = 0x1; 1277 next_page = 0x1; 1278 cl73_nonce_match_over = 0x1; 1279 cl73_nonce_match_val = 0x0; 1280 base_selector = 0x1; 1281 } else { 1282 no_an = 1 ; 1283 printf("%-22s ERROR: u=%0d p=%0d Autoneg mode not defined\n", __func__, pc->unit, pc->port); 1284 }*/ 1285 #if defined (_DV_TB_) 1286 if (pc->sc_mode == TEMOD16_SC_MODE_AN_CL37) { 1287 cl37_restart = 0x0; 1288 cl37_enable = pc->cl37_an_en; 1289 cl37_bam_enable = pc->cl37_bam_en; 1290 cl37_sgmii_enable = pc->cl37_sgmii_en; 1291 cl37_bam_code = pc->cl37_bam_code & 0x1ff; 1292 over1g_ability = pc->cl37_bam_ovr1g_en & 1; 1293 over1g_page_count = pc->cl37_bam_ovr1g_pgcnt & 3; /* PHY-863: =1: 5 pages; =0: 3 pages; WC uses 3 pages */ 1294 sgmii_full_duplex = pc->cl37_sgmii_duplex & 1; 1295 cl37_next_page = pc->cl37_an_np & 1; 1296 } else if (pc->sc_mode == TEMOD16_SC_MODE_AN_CL73) { 1297 cl73_restart = 0x0; 1298 cl73_enable = pc->cl73_an_en; 1299 cl73_bam_enable = pc->cl73_bam_en; 1300 cl73_hpam_enable = pc->cl73_hpam_en; 1301 cl73_bam_code = pc->cl73_bam_code & 0x1ff; 1302 next_page = pc->cl73_nxt_page & 1; 1303 cl73_nonce_match_over = pc->cl73_nonce_match_over & 1; 1304 cl73_transmit_nonce = pc->transmit_nonce; 1305 cl73_nonce_match_val = pc->cl73_nonce_match_val & 1; 1306 base_selector = pc->base_selector & 0x1f; 1307 } else { 1308 no_an = 1 ; 1309 printf("%-22s ERROR: u=%0d p=%0d Autoneg mode not defined\n", __func__, pc->unit, pc->port); 1310 return PHYMOD_E_FAIL; 1311 } 1312 #endif /*_DV_TB_*/ 1313 1314 1315 /* cl37 bam abilities 0xc182 */ 1316 AN_X4_LOC_DEV_CL37_BAM_ABILr_CLR(reg_an_cl37_bam_abilities); 1317 AN_X4_LOC_DEV_CL37_BAM_ABILr_CL37_BAM_CODEf_SET(reg_an_cl37_bam_abilities, cl37_bam_code); 1318 AN_X4_LOC_DEV_CL37_BAM_ABILr_OVER1G_ABILITYf_SET(reg_an_cl37_bam_abilities, over1g_ability); 1319 AN_X4_LOC_DEV_CL37_BAM_ABILr_OVER1G_PAGE_COUNTf_SET(reg_an_cl37_bam_abilities, over1g_page_count); 1320 1321 PHYMOD_IF_ERR_RETURN 1322 (MODIFY_AN_X4_LOC_DEV_CL37_BAM_ABILr(pc, reg_an_cl37_bam_abilities)); 1323 1324 /* set next page bit set 0xc186 */ 1325 /* 1326 TSCE_READ_AN_LOCAL_DEVICE_CL73_BASE_ABILITIES_0r(pc, ®_an_cl73_abl_0); 1327 TSCE_AN_LOCAL_DEVICE_CL73_BASE_ABILITIES_0r_NEXT_PAGEf_SET(reg_an_cl73_abl_0, next_page); 1328 PHYMOD_IF_ERR_RETURN ( TSCE_WRITE_AN_LOCAL_DEVICE_CL73_BASE_ABILITIES_0r(pc, reg_an_cl73_abl_0)); 1329 */ 1330 1331 /* set cl73_bam_code set 0xc187 */ 1332 /* 1333 1334 TSCE_READ_AN_LOCAL_DEVICE_CL73_BAM_ABILITIESr(pc, ®_an_cl73_abl); 1335 TSCE_AN_LOCAL_DEVICE_CL73_BAM_ABILITIESr_CL73_BAM_CODEf_SET(reg_an_cl73_abl, cl73_bam_code); 1336 PHYMOD_IF_ERR_RETURN ( TSCE_WRITE_AN_LOCAL_DEVICE_CL73_BAM_ABILITIESr(pc, reg_an_cl73_abl)); 1337 */ 1338 /* disable ecc of uC 0xffcc */ 1339 /* 1340 TSCE_COMMAND3r_SET(reg_com3, 0x0c04); 1341 PHYMOD_IF_ERR_RETURN (TSCE_WRITE_COMMAND3r(pc, reg_com3)); 1342 */ 1343 1344 /* enable micro_controller 0xffc2 */ 1345 /* 1346 TSCE_READ_COMMANDr(pc, ®_com); 1347 TSCE_COMMANDr_MICRO_MDIO_DW8051_RESET_Nf_SET(reg_com,1); 1348 UC_COMMAND_MDIO_UC_RESET_N_MASK)); 1349 */ 1350 /* set cl73 nonce set 0xc340 */ 1351 AN_X4_LOC_DEV_CL73_BASE_ABIL1r_CLR(reg_an_cl73_abl_1); 1352 AN_X4_LOC_DEV_CL73_BASE_ABIL1r_CL73_NONCE_MATCH_OVERf_SET(reg_an_cl73_abl_1, cl73_nonce_match_over); 1353 AN_X4_LOC_DEV_CL73_BASE_ABIL1r_CL73_NONCE_MATCH_VALf_SET(reg_an_cl73_abl_1, cl73_nonce_match_val); 1354 PHYMOD_IF_ERR_RETURN ( MODIFY_AN_X4_LOC_DEV_CL73_BASE_ABIL1r(pc, reg_an_cl73_abl_1)); 1355 1356 /* set cl73 base_selector to 802.3 set 0xc185 */ 1357 AN_X4_LOC_DEV_CL73_BASE_ABIL1r_CLR(reg_an_cl73_abl_1); 1358 AN_X4_LOC_DEV_CL73_BASE_ABIL1r_BASE_SELECTORf_SET(reg_an_cl73_abl_1, base_selector); 1359 PHYMOD_IF_ERR_RETURN ( MODIFY_AN_X4_LOC_DEV_CL73_BASE_ABIL1r(pc, reg_an_cl73_abl_1)); 1360 1361 AN_X4_LOC_DEV_CL73_BASE_ABIL1r_CLR(reg_an_cl73_abl_1); 1362 AN_X4_LOC_DEV_CL73_BASE_ABIL1r_TRANSMIT_NONCEf_SET(reg_an_cl73_abl_1, ( cl73_transmit_nonce & 0x1f)); 1363 PHYMOD_IF_ERR_RETURN ( MODIFY_AN_X4_LOC_DEV_CL73_BASE_ABIL1r(pc, reg_an_cl73_abl_1)); 1364 1365 /* 0x924a for PHY_892 TBD*/ 1366 /*if ((no_an==0)&&(pc->port_type==TSCMOD_SINGLE_PORT)) {*/ 1367 data = 0x1a0a ; /* 100ms TX_RESET_TIMER_PERIOD */ 1368 data = 0xd05 ; /* 50ms */ 1369 /*} else { 1370 data = 0x5 ; 1371 } 1372 PHYMOD_IF_ERR_RETURN 1373 TSC_REG_WRITE(pc->unit, pc, 0x00, 0x0000924a, data)) ;*/ 1374 1375 /*Disabling AN if already enabled required for dynamic speed change tests*/ 1376 1377 AN_X4_ENSr_CLR(reg_an_enb); 1378 1379 AN_X4_ENSr_CL37_ENABLEf_SET(reg_an_enb,0); 1380 AN_X4_ENSr_CL73_ENABLEf_SET(reg_an_enb,0); 1381 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_ENSr(pc, reg_an_enb)); 1382 1383 /*Setting X4 abilities*/ 1384 AN_X4_ENSr_CLR(reg_an_enb); 1385 AN_X4_ENSr_CL37_BAM_ENABLEf_SET(reg_an_enb,cl37_bam_enable); 1386 AN_X4_ENSr_CL73_BAM_ENABLEf_SET(reg_an_enb,cl73_bam_enable); 1387 AN_X4_ENSr_CL73_HPAM_ENABLEf_SET(reg_an_enb,cl73_hpam_enable); 1388 AN_X4_ENSr_CL73_ENABLEf_SET(reg_an_enb,cl73_enable); 1389 AN_X4_ENSr_CL37_SGMII_ENABLEf_SET(reg_an_enb,cl37_sgmii_enable); 1390 AN_X4_ENSr_CL37_ENABLEf_SET(reg_an_enb,cl37_enable); 1391 AN_X4_ENSr_CL37_AN_RESTARTf_SET(reg_an_enb,cl37_restart); 1392 AN_X4_ENSr_CL73_AN_RESTARTf_SET(reg_an_enb,cl73_restart); 1393 AN_X4_ENSr_HPAM_TO_CL73_AUTO_ENABLEf_SET(reg_an_enb,pc->hpam_to_cl73_auto_enable); 1394 AN_X4_ENSr_CL73_BAM_TO_HPAM_AUTO_ENABLEf_SET(reg_an_enb,pc->cl73_bam_to_hpam_auto_enable); 1395 AN_X4_ENSr_SGMII_TO_CL37_AUTO_ENABLEf_SET(reg_an_enb,pc->sgmii_to_cl37_auto_enable); 1396 AN_X4_ENSr_CL37_BAM_TO_SGMII_AUTO_ENABLEf_SET(reg_an_enb,pc->cl37_bam_to_sgmii_auto_enable); 1397 AN_X4_ENSr_NUM_ADVERTISED_LANESf_SET(reg_an_enb,num_advertised_lanes); 1398 1399 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_ENSr(pc, reg_an_enb)); 1400 1401 return PHYMOD_E_NONE; 1402 } /* temod16_autoneg_control */ 1403 #endif 1404 #ifdef _SDK_TEMOD16_ 1405 int temod16_autoneg_control(PHYMOD_ST* pc, temod16_an_control_t *an_control) 1406 { 1407 uint16_t num_advertised_lanes, cl37_bam_enable, cl73_bam_enable ; 1408 uint16_t cl73_hpam_enable, cl73_enable, cl37_sgmii_enable, cl37_enable; 1409 uint16_t cl73_bam_code; 1410 uint16_t cl73_next_page; 1411 uint16_t cl37_next_page; 1412 uint16_t cl37_bam_code; 1413 uint16_t cl37_restart, cl73_restart ; 1414 phymod_access_t pa_copy; 1415 int i=0, start_lane=0, num_lane=0, sgmii_to_cl37=0 ; 1416 uint32_t enable=0; 1417 1418 AN_X4_LOC_DEV_CL37_BASE_ABILr_t reg_an_cl37_abl; 1419 AN_X4_LOC_DEV_CL37_BAM_ABILr_t reg_an_cl37_bam_abilities; 1420 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_t reg_an_cl73_abl_0; 1421 AN_X4_ENSr_t reg_an_enb; 1422 AN_X4_CTLSr_t an_x4_abl_ctrl; 1423 1424 AN_X1_CL37_ERRr_t reg_cl37_err; 1425 AN_X1_CL73_ERRr_t reg_cl73_err; 1426 AN_X4_LOC_DEV_CL73_BAM_ABILr_t reg_cl73_bam_abilities; 1427 TMOD_DBG_IN_FUNC_INFO(pc); 1428 1429 PHYMOD_MEMCPY(&pa_copy, pc, sizeof(pa_copy)); 1430 PHYMOD_IF_ERR_RETURN 1431 (phymod_util_lane_config_get(pc, &start_lane, &num_lane)); 1432 pa_copy.lane_mask = 0; 1433 num_advertised_lanes = an_control->num_lane_adv; 1434 1435 switch (num_advertised_lanes) { 1436 case 3: num_lane = 4; break; 1437 case 2: num_lane = 4; break; 1438 case 1: num_lane = 2; break; 1439 case 0: num_lane = 1; break; 1440 default: num_lane = 1; 1441 } 1442 for (i=0; i<num_lane; i++) { 1443 pa_copy.lane_mask = pa_copy.lane_mask | 0x1 << (start_lane+i); 1444 } 1445 1446 cl37_bam_enable = 0x0; 1447 cl73_bam_enable = 0x0; 1448 cl73_hpam_enable = 0x0; 1449 cl73_enable = 0x0; 1450 cl37_sgmii_enable = 0x0; 1451 cl37_enable = 0x0; 1452 cl73_next_page = 0x0; 1453 cl37_next_page = 0x0; 1454 cl37_bam_code = 0x0; 1455 cl37_restart = 0x0; 1456 cl73_restart = 0x0; 1457 cl73_bam_code = 0x0; 1458 1459 switch (an_control->an_type) { 1460 case TEMOD16_CL73: 1461 { 1462 cl73_restart = an_control->enable; 1463 cl73_enable = an_control->enable; 1464 break; 1465 } 1466 case TEMOD16_CL37: 1467 cl37_restart = an_control->enable; 1468 cl37_enable = an_control->enable; 1469 cl37_bam_code = 0x0; 1470 break; 1471 case TEMOD16_CL37_BAM: 1472 cl37_restart = an_control->enable; 1473 cl37_enable = an_control->enable; 1474 cl37_bam_enable = an_control->enable; 1475 cl37_bam_code = 0x1; 1476 cl37_next_page = 0x1; 1477 break; 1478 case TEMOD16_CL37_SGMII: 1479 cl37_restart = an_control->enable; 1480 cl37_sgmii_enable = an_control->enable; 1481 cl37_enable = an_control->enable; 1482 cl37_bam_code = 0x0; 1483 break; 1484 case TEMOD16_CL73_BAM: 1485 cl73_restart = an_control->enable; 1486 cl73_enable = an_control->enable; 1487 cl73_bam_enable = an_control->enable; 1488 cl73_next_page = 0x1; 1489 cl73_bam_code = 0x3; 1490 break; 1491 case TEMOD16_HPAM: 1492 cl73_restart = an_control->enable; 1493 cl73_enable = an_control->enable; 1494 cl73_hpam_enable = an_control->enable; 1495 cl73_next_page = 0x1; 1496 break; 1497 case TEMOD16_AN_MODE_CL37_SGMII: 1498 cl37_restart = an_control->enable; 1499 cl37_sgmii_enable = an_control->enable; 1500 cl37_enable = an_control->enable; 1501 if(cl37_enable) { 1502 sgmii_to_cl37 = 1; 1503 } 1504 cl37_bam_code = 0x0; 1505 break; 1506 default: 1507 return PHYMOD_E_FAIL; 1508 break; 1509 } 1510 1511 /* RESET Speed Change bit */ 1512 if(an_control->enable){ 1513 temod16_disable_set(pc); 1514 } 1515 1516 /* AN TIMERS */ 1517 /*0x9252 AN_X1_TIMERS_cl37_error */ 1518 AN_X1_CL37_ERRr_CLR(reg_cl37_err); 1519 if (an_control->an_type == TEMOD16_AN_MODE_CL37) { 1520 AN_X1_CL37_ERRr_SET(reg_cl37_err, 0); 1521 } else if (an_control->an_type == TEMOD16_AN_MODE_CL37BAM) { 1522 AN_X1_CL37_ERRr_SET(reg_cl37_err, 0x55d); 1523 } 1524 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_CL37_ERRr(pc, reg_cl37_err)); 1525 1526 /*0x9254 AN_X1_TIMERS_cl73_error*/ 1527 AN_X1_CL73_ERRr_CLR(reg_cl73_err); 1528 if (an_control->an_type == TEMOD16_AN_MODE_CL73) { 1529 AN_X1_CL73_ERRr_SET(reg_cl73_err, 0); 1530 } else if (an_control->an_type == TEMOD16_AN_MODE_HPAM) { 1531 AN_X1_CL73_ERRr_SET(reg_cl73_err, 0xfff0); 1532 } else if (an_control->an_type == TEMOD16_AN_MODE_CL73BAM) { 1533 AN_X1_CL73_ERRr_SET(reg_cl73_err, 0x1a10); 1534 } 1535 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_CL73_ERRr(pc, reg_cl73_err)); 1536 1537 1538 /* an37 an-restart_reset_disable setting */ 1539 /* DOne in autoneg_set, so commenting here */ 1540 /* 1541 AN_X4_LOC_DEV_CL37_BASE_ABILr_CLR(reg_an_cl37_abl); 1542 AN_X4_LOC_DEV_CL37_BASE_ABILr_CL37_AN_RESTART_RESET_DISABLEf_SET(reg_an_cl37_abl, cl37_an_restart_reset_disable); 1543 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_LOC_DEV_CL37_BASE_ABILr(pc, reg_an_cl37_abl)); 1544 */ 1545 1546 /* cl37 bam abilities 0xc182 */ 1547 AN_X4_LOC_DEV_CL37_BAM_ABILr_CLR(reg_an_cl37_bam_abilities); 1548 AN_X4_LOC_DEV_CL37_BAM_ABILr_CL37_BAM_CODEf_SET(reg_an_cl37_bam_abilities, cl37_bam_code); 1549 PHYMOD_IF_ERR_RETURN 1550 (MODIFY_AN_X4_LOC_DEV_CL37_BAM_ABILr(pc, reg_an_cl37_bam_abilities)); 1551 1552 /*need to set the next page for cl37bam */ 1553 AN_X4_LOC_DEV_CL37_BASE_ABILr_CLR(reg_an_cl37_abl); 1554 if (an_control->an_property_type & TEMOD16_AN_PROPERTY_ENABLE_SGMII_MASTER_MODE ) 1555 AN_X4_LOC_DEV_CL37_BASE_ABILr_SGMII_MASTER_MODEf_SET(reg_an_cl37_abl, 0x1); 1556 else 1557 AN_X4_LOC_DEV_CL37_BASE_ABILr_SGMII_MASTER_MODEf_SET(reg_an_cl37_abl, 0x0); 1558 AN_X4_LOC_DEV_CL37_BASE_ABILr_CL37_NEXT_PAGEf_SET(reg_an_cl37_abl, cl37_next_page); 1559 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_LOC_DEV_CL37_BASE_ABILr(pc, reg_an_cl37_abl)); 1560 1561 /*need to set cl73 BAM next page probably*/ 1562 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_CLR(reg_an_cl73_abl_0); 1563 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_NEXT_PAGEf_SET(reg_an_cl73_abl_0, cl73_next_page & 1); 1564 PHYMOD_IF_ERR_RETURN ( MODIFY_AN_X4_LOC_DEV_CL73_BASE_ABIL0r(pc, reg_an_cl73_abl_0)); 1565 PHYMOD_IF_ERR_RETURN( READ_AN_X4_LOC_DEV_CL73_BAM_ABILr(pc, ®_cl73_bam_abilities)); 1566 AN_X4_LOC_DEV_CL73_BAM_ABILr_CL73_BAM_CODEf_SET(reg_cl73_bam_abilities, (cl73_bam_code & 0x1ff)); 1567 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_LOC_DEV_CL73_BAM_ABILr(pc, reg_cl73_bam_abilities)); 1568 1569 1570 AN_X4_CTLSr_CLR(an_x4_abl_ctrl); 1571 AN_X4_CTLSr_PD_KX_ENf_SET(an_x4_abl_ctrl, an_control->pd_kx_en & 0x1); 1572 AN_X4_CTLSr_PD_KX4_ENf_SET(an_x4_abl_ctrl, an_control->pd_kx4_en & 0x1); 1573 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_CTLSr(pc, an_x4_abl_ctrl)); 1574 1575 AN_X4_ENSr_CLR(reg_an_enb); 1576 1577 AN_X4_ENSr_CL37_ENABLEf_SET(reg_an_enb,0); 1578 AN_X4_ENSr_CL73_ENABLEf_SET(reg_an_enb,0); 1579 AN_X4_ENSr_CL37_AN_RESTARTf_SET(reg_an_enb,0); 1580 AN_X4_ENSr_CL73_AN_RESTARTf_SET(reg_an_enb,0); 1581 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_ENSr(pc, reg_an_enb)); 1582 1583 /*Setting X4 abilities*/ 1584 AN_X4_ENSr_CLR(reg_an_enb); 1585 AN_X4_ENSr_CL37_BAM_ENABLEf_SET(reg_an_enb,cl37_bam_enable); 1586 AN_X4_ENSr_CL73_BAM_ENABLEf_SET(reg_an_enb,cl73_bam_enable); 1587 AN_X4_ENSr_CL73_HPAM_ENABLEf_SET(reg_an_enb,cl73_hpam_enable); 1588 AN_X4_ENSr_CL73_ENABLEf_SET(reg_an_enb,cl73_enable); 1589 AN_X4_ENSr_CL37_SGMII_ENABLEf_SET(reg_an_enb,cl37_sgmii_enable); 1590 AN_X4_ENSr_CL37_ENABLEf_SET(reg_an_enb,cl37_enable); 1591 AN_X4_ENSr_CL37_AN_RESTARTf_SET(reg_an_enb,cl37_restart); 1592 AN_X4_ENSr_CL73_AN_RESTARTf_SET(reg_an_enb,cl73_restart); 1593 if (an_control->an_property_type & TEMOD16_AN_PROPERTY_ENABLE_HPAM_TO_CL73_AUTO ) 1594 AN_X4_ENSr_HPAM_TO_CL73_AUTO_ENABLEf_SET(reg_an_enb,0x1); 1595 else 1596 AN_X4_ENSr_HPAM_TO_CL73_AUTO_ENABLEf_SET(reg_an_enb,0x0); 1597 if (an_control->an_property_type & TEMOD16_AN_PROPERTY_ENABLE_CL73_BAM_TO_HPAM_AUTO ) 1598 AN_X4_ENSr_CL73_BAM_TO_HPAM_AUTO_ENABLEf_SET(reg_an_enb,0x1); 1599 else 1600 AN_X4_ENSr_CL73_BAM_TO_HPAM_AUTO_ENABLEf_SET(reg_an_enb,0x0); 1601 if ((an_control->an_property_type & TEMOD16_AN_PROPERTY_ENABLE_SGMII_TO_CL37_AUTO) || sgmii_to_cl37) 1602 AN_X4_ENSr_SGMII_TO_CL37_AUTO_ENABLEf_SET(reg_an_enb,0x1); 1603 else 1604 AN_X4_ENSr_SGMII_TO_CL37_AUTO_ENABLEf_SET(reg_an_enb,0x0); 1605 if (an_control->an_property_type & TEMOD16_AN_PROPERTY_ENABLE_CL37_BAM_to_SGMII_AUTO ) 1606 AN_X4_ENSr_CL37_BAM_TO_SGMII_AUTO_ENABLEf_SET(reg_an_enb,0x1); 1607 else 1608 AN_X4_ENSr_CL37_BAM_TO_SGMII_AUTO_ENABLEf_SET(reg_an_enb,0x0); 1609 AN_X4_ENSr_NUM_ADVERTISED_LANESf_SET(reg_an_enb,num_advertised_lanes); 1610 1611 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_ENSr(pc, reg_an_enb)); 1612 1613 /*next check if an enabled, restart bit needs to be cleared */ 1614 if (an_control->enable) { 1615 AN_X4_ENSr_CLR(reg_an_enb); 1616 AN_X4_ENSr_CL37_AN_RESTARTf_SET(reg_an_enb,0); 1617 AN_X4_ENSr_CL73_AN_RESTARTf_SET(reg_an_enb,0); 1618 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_ENSr(pc, reg_an_enb)); 1619 } 1620 1621 /* need to clean up the FIFO */ 1622 if (an_control->enable == 0) { 1623 pa_copy.lane_mask = 1 << start_lane ; 1624 temod16_disable_get(&pa_copy,&enable); 1625 if (enable == 0x1) { 1626 PHYMOD_IF_ERR_RETURN (temod16_trigger_speed_change(&pa_copy)); 1627 } 1628 } 1629 return PHYMOD_E_NONE; 1630 } /* temod16_autoneg_control */ 1631 #endif /* _SDK_TEMOD16_*/ 1632 1633 #ifdef _DV_TB_ 1634 /* 1635 @brief Speeds up DSC and VGA functions for simulation purpose only 1636 @param pc handle to current TSCE context (#PHYMOD_ST) 1637 @returns The value PHYMOD_E_NONE upon successful completion. 1638 @details 1639 1640 This function speeds up PLL, DSC and VGA functions for any speed mode. Please don't 1641 call this function in normal operation. 1642 Set #PHYMOD_ST::per_lane_control to 1 for speed up. 1643 1644 This function is controlled by the following register bit: 1645 1646 \li acq2_timeout, acq1_timeout, acqcdr_timeout (0xc210) -> 0x0421 1647 \li acqvga_timeout (0xc211) -> 0x0800 1648 1649 */ 1650 int temod16_afe_speed_up_dsc_vga(PHYMOD_ST* pc, int pmd_touched) /* AFE_SPEED_UP_DSC_VGA */ 1651 { 1652 PLL_CALCTL0r_t reg_pll_calctl0; 1653 PLL_CALCTL1r_t reg_pll_calctl1; 1654 PLL_CALCTL2r_t reg_pll_calctl2; 1655 UC_CTL0r_t reg_uc_ctl0; 1656 /* 1657 PLL_CAL_CTL0r_t reg_ctrl0; 1658 PLL_CAL_CTL1r_t reg_ctrl1; 1659 PLL_CAL_CTL2r_t reg_ctrl2; 1660 PLL_CAL_CTL5r_t reg_ctrl5; 1661 PLL_CAL_CTL6r_t reg_ctrl6; 1662 */ 1663 DSC_SM_CTL4r_t reg_ctrl4; 1664 1665 TMOD_DBG_IN_FUNC_INFO(pc); 1666 1667 PLL_CALCTL0r_CLR(reg_pll_calctl0); 1668 PLL_CALCTL1r_CLR(reg_pll_calctl1); 1669 PLL_CALCTL2r_CLR(reg_pll_calctl2); 1670 UC_CTL0r_CLR(reg_uc_ctl0); 1671 /* 1672 PLL_CAL_CTL5r_CLR(reg_ctrl5); 1673 PLL_CAL_CTL6r_CLR(reg_ctrl6); 1674 PLL_CAL_CTL0r_CLR(reg_ctrl0); 1675 PLL_CAL_CTL1r_CLR(reg_ctrl1); 1676 PLL_CAL_CTL2r_CLR(reg_ctrl2); 1677 */ 1678 DSC_SM_CTL4r_CLR(reg_ctrl4); 1679 1680 if (pmd_touched == 0) { 1681 /* PLL speed_up begin */ 1682 /* write ( "calib_step_time", 0x52);*/ 1683 PLL_CALCTL0r_CALIB_STEP_TIMEf_SET(reg_pll_calctl0, 0x52); 1684 PHYMOD_IF_ERR_RETURN (MODIFY_PLL_CALCTL0r(pc, reg_pll_calctl0)); 1685 1686 /* write ( "freqdet_time", 0x28F);*/ 1687 PLL_CALCTL1r_FREQDET_TIMEf_SET(reg_pll_calctl1, 0x28f); 1688 PHYMOD_IF_ERR_RETURN (MODIFY_PLL_CALCTL1r(pc, reg_pll_calctl1)); 1689 1690 /* write ( "calib_cap_charge_time", 0x28);*/ 1691 PLL_CALCTL2r_CALIB_CAP_CHARGE_TIMEf_SET(reg_pll_calctl2, 0x28); 1692 PHYMOD_IF_ERR_RETURN (MODIFY_PLL_CALCTL2r(pc, reg_pll_calctl2)); 1693 } 1694 /* PLL speed_up end */ 1695 1696 /* write ( "tx_disable_timer_ctrl", 0);*/ 1697 UC_CTL0r_TX_DISABLE_TIMER_CTRLf_SET(reg_uc_ctl0, 0x0); 1698 PHYMOD_IF_ERR_RETURN (MODIFY_UC_CTL0r(pc, reg_uc_ctl0)); 1699 1700 /* DSC speed_up begin */ 1701 1702 DSC_SM_CTL4r_HW_TUNE_TIMEOUTf_SET(reg_ctrl4, 0x1); 1703 DSC_SM_CTL4r_CDR_SETTLE_TIMEOUTf_SET(reg_ctrl4, 0x1); 1704 DSC_SM_CTL4r_ACQ_CDR_TIMEOUTf_SET(reg_ctrl4, 0x4); 1705 1706 PHYMOD_IF_ERR_RETURN (MODIFY_DSC_SM_CTL4r(pc, reg_ctrl4)); 1707 1708 /* DSC speed_up end */ 1709 return PHYMOD_E_NONE; 1710 } 1711 #endif /* _DV_TB_ */ 1712 1713 static int _temod16_getRevDetails(PHYMOD_ST* pc) 1714 { 1715 MAIN0_SERDESIDr_t reg_serdesid; 1716 1717 MAIN0_SERDESIDr_CLR(reg_serdesid); 1718 PHYMOD_IF_ERR_RETURN(READ_MAIN0_SERDESIDr(pc,®_serdesid)); 1719 return (MAIN0_SERDESIDr_GET(reg_serdesid)); 1720 } 1721 1722 /** 1723 @brief Init routine sets various operating modes of TSCE. 1724 @param pc handle to current TSCE context (#PHYMOD_ST) 1725 @param pmd_touched 1726 @param spd_intf #temod16_spd_intfc_type 1727 @param pll_mode # to override the pll div 1728 @returns PHYMOD_E_NONE if successful. PHYMOD_E_FAIL else. 1729 @details 1730 1731 This function is called once per TSCE. It cannot be called multiple times 1732 and should be called immediately after reset. Elements of #PHYMOD_ST should be 1733 initialized to required values prior to calling this function. The following 1734 sub-configurations are performed here. 1735 1736 \li Set pll divider for VCO setting in PMD. pll divider is calculated from max_speed. 1737 */ 1738 1739 int temod16_set_pll_mode(PHYMOD_ST* pc, int pmd_touched, temod16_spd_intfc_type spd_intf, int pll_mode) /* SET_PLL_MODE */ 1740 { 1741 PLL_CTL8r_t reg_ctl8; 1742 PLL_CTL9r_t reg_ctl9; 1743 int speed; 1744 int pll_ndiv; 1745 int pll_mode_lcl; 1746 1747 TMOD_DBG_IN_FUNC_INFO(pc); 1748 PLL_CTL8r_CLR(reg_ctl8); 1749 PLL_CTL9r_CLR(reg_ctl9); 1750 1751 if (pmd_touched == 0) { 1752 temod16_get_mapped_speed(spd_intf, &speed); 1753 /*Support Override PLL DIV */ 1754 if (pll_mode & 0x80000000) { 1755 pll_mode_lcl = pll_mode & 0x3ff; 1756 temod16_get_pll_ndiv(pll_mode_lcl, &pll_ndiv); 1757 PLL_CTL8r_I_NDIV_INTf_SET(reg_ctl8, (pll_ndiv) & 0x0000ffff); 1758 } else { 1759 temod16_get_pll_ndiv(merlin16_sc_pmd_entry[speed].pll_mode, &pll_ndiv); 1760 PLL_CTL8r_I_NDIV_INTf_SET(reg_ctl8, pll_ndiv); 1761 } 1762 1763 #ifdef _DV_TB_ 1764 if ( pc->verbosity) { 1765 printf("%-22s: plldiv:%d data:%x\n", __func__, pc->plldiv, PLL_CTL8r_I_NDIV_INTf_GET(reg_ctl8)); 1766 printf("%-22s: main0_setup=%x\n", __func__, PLL_CTL8r_I_NDIV_INTf_GET(reg_ctl8)); 1767 } 1768 #endif 1769 1770 PHYMOD_IF_ERR_RETURN (MODIFY_PLL_CTL8r(pc, reg_ctl8)); 1771 1772 /* write ( "mmd_resetb" 0); */ 1773 PLL_CTL9r_MMD_RESETBf_SET(reg_ctl9, 0); 1774 1775 /* dummy read to kill some time* */ 1776 PHYMOD_IF_ERR_RETURN (READ_PLL_CTL8r(pc, ®_ctl8)); 1777 1778 /* write ( "mmd_resetb" 1); */ 1779 /* mmd_resetb should be asserted and deasserted every time a different divider value is programmed. */ 1780 PLL_CTL9r_MMD_RESETBf_SET(reg_ctl9, 1); 1781 1782 } 1783 1784 return PHYMOD_E_NONE; 1785 1786 } /* temod16_set_pll_mode(PHYMOD_ST* pc) */ 1787 1788 #ifdef _DV_TB_ 1789 /** 1790 @brief set the AN tick overrides 1791 @param pc handle to current TSCE context (#PHYMOD_ST) 1792 @param tick_override 1793 @param numerator 1794 @param denominator 1795 @returns PHYMOD_E_NONE if successful. 1796 @details 1797 */ 1798 int temod16_tick_override_set(PHYMOD_ST* pc, int tick_override, int numerator, int denominator) 1799 { 1800 MAIN0_TICK_CTL1r_t reg_ctrl1; 1801 MAIN0_TICK_CTL0r_t reg_ctrl0; 1802 1803 TMOD_DBG_IN_FUNC_INFO(pc); 1804 MAIN0_TICK_CTL1r_CLR(reg_ctrl1); 1805 MAIN0_TICK_CTL0r_CLR(reg_ctrl0); 1806 1807 /*Tick over_write enable*/ 1808 MAIN0_TICK_CTL1r_TICK_OVERRIDEf_SET(reg_ctrl1, tick_override); 1809 MAIN0_TICK_CTL1r_TICK_NUMERATOR_UPPERf_SET(reg_ctrl1, (numerator & 0x7fff0)); 1810 PHYMOD_IF_ERR_RETURN(WRITE_MAIN0_TICK_CTL1r(pc, reg_ctrl1)); 1811 1812 MAIN0_TICK_CTL0r_TICK_DENOMINATORf_SET(reg_ctrl0, (denominator & 0x3ff) ); 1813 MAIN0_TICK_CTL0r_TICK_NUMERATOR_LOWERf_SET(reg_ctrl0, (numerator & 0xf)); 1814 PHYMOD_IF_ERR_RETURN(WRITE_MAIN0_TICK_CTL0r(pc, reg_ctrl0)); 1815 1816 return PHYMOD_E_NONE; 1817 1818 } 1819 #endif /* _DV_TB_ */ 1820 1821 /** 1822 @brief Set the AN Portmode and Single Port for AN of TSCE. 1823 @param pc handle to current TSCE context (#PHYMOD_ST) 1824 @param number_of_lanes 1825 @param starting lane #port no. 1826 @param single_port 1827 @returns PHYMOD_E_NONE if successful. PHYMOD_E_FAIL else. 1828 @details 1829 1830 This function can be called multiple times.Elements of #PHYMOD_ST should be 1831 initialized to required values prior to calling this function. The following 1832 sub-configurations are performed here. 1833 1834 \li Set pll divider for VCO setting (0x9000[12, 11:8]). pll divider is calculated from max_speed. 1835 1836 */ 1837 #ifdef _DV_TB_ 1838 int temod16_set_an_port_mode(PHYMOD_ST* pc) /* SET_AN_PORT_MODE */ 1839 { 1840 uint16_t data, mask,rdata; 1841 PHYMOD_ST pc_10G_X1; 1842 PHYMOD_ST* pc_10G_X1_tmp; 1843 PHYMOD_ST pc_40G_X4; 1844 PHYMOD_ST* pc_40G_X4_tmp; 1845 PHYMOD_ST pc_100G_X4; 1846 PHYMOD_ST* pc_100G_X4_tmp; 1847 1848 MAIN0_SETUPr_t reg_main0_setup; 1849 AN_X1_CL37_RESTARTr_t reg_cl37_restart_timers; 1850 AN_X1_CL37_ACKr_t reg_cl37_ack_timers; 1851 AN_X1_CL37_ERRr_t reg_cl37_err_timers; 1852 AN_X1_CL73_BRK_LNKr_t reg_cl73_brk_lnk_timers; 1853 AN_X1_CL73_ERRr_t reg_cl73_err_timers; 1854 MAIN0_TICK_CTL1r_t reg_tick_ctrl; 1855 MAIN0_TICK_CTL0r_t reg_tick_ctrl0; 1856 1857 AN_X1_CFG_CTLr_t reg_an_retry_cnt; 1858 AN_X1_BAM_SPD_PRI_35_30r_t reg_pri35_30; 1859 AN_X1_BAM_SPD_PRI_29_24r_t reg_pri29_24; 1860 AN_X1_BAM_SPD_PRI_23_18r_t reg_pri23_18; 1861 AN_X1_BAM_SPD_PRI_17_12r_t reg_pri17_12; 1862 AN_X1_BAM_SPD_PRI_11_6r_t reg_pri11_6; 1863 AN_X1_BAM_SPD_PRI_5_0r_t reg_bam_pri5; 1864 AN_X1_OUI_LWRr_t reg_an_oui_lower; 1865 AN_X1_OUI_UPRr_t reg_an_oui_upper; 1866 SC_X1_TX_RST_CNTr_t reg_sc_rst_cnt; 1867 AN_X1_SGMII_CL73_TMR_TYPEr_t reg_an_cl73_sgmii_tmr; 1868 AN_X1_IGNORE_LNK_TMRr_t reg_an_ig_link_tmr; 1869 AN_X1_PD_TO_CL37_LNK_WAIT_TMRr_t reg_an_pd_to_cl37; 1870 AN_X1_CL37_SYNC_STS_FILTER_TMRr_t reg_an_sync_stat_fil_timer; 1871 AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72r_t reg_lk_fail_not72; 1872 AN_X1_CL73_DME_LOCKr_t reg_cl73_dme; 1873 AN_X1_LNK_UPr_t reg_an_lp; 1874 AN_X1_LNK_FAIL_INHBT_TMR_CL72r_t reg_lk_fail; 1875 AN_X1_PD_SD_TMRr_t reg_an_pd_sd_tmr; 1876 1877 TMOD_DBG_IN_FUNC_INFO(pc); 1878 MAIN0_SETUPr_CLR(reg_main0_setup); 1879 1880 data=0; 1881 mask=0; 1882 /*Ref clock selection*/ 1883 data = main0_refClkSelect_clk_156p25MHz; 1884 /*Selectng div 40 for CL37*/ 1885 /*if (pc->sc_mode == TEMOD16_SC_MODE_AN_CL37) 1886 data = data | (MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_div40 << 1887 MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_SHIFT); */ 1888 /*Selectng div 66 for CL77*/ 1889 /*if (pc->sc_mode == TEMOD16_SC_MODE_AN_CL73) 1890 data = data | (MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_div66 << 1891 MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_SHIFT);*/ 1892 1893 /*For AN port mode should be always QUAD*/ 1894 1895 PHYMOD_IF_ERR_RETURN (READ_MAIN0_SETUPr(pc, ®_main0_setup)); 1896 rdata = MAIN0_SETUPr_PORT_MODE_SELf_GET(reg_main0_setup); 1897 1898 MAIN0_SETUPr_REFCLK_SELf_SET(reg_main0_setup, data); 1899 data = 0; 1900 if ((pc->no_of_lanes == 2) || (pc->no_of_lanes == 3)) { 1901 MAIN0_SETUPr_PORT_MODE_SELf_SET(reg_main0_setup, 0); 1902 } else { 1903 if (pc->this_lane == 0 || pc->this_lane == 1 || pc->this_lane == 4 || pc->this_lane == 5 || pc->this_lane == 8 || pc->this_lane == 9) { 1904 if (rdata == 0x1 || rdata == 0x3) { 1905 data = data | 0x1; 1906 } 1907 if (rdata == 0x4 || rdata == 0x2) { 1908 data = data | 0x0; 1909 } 1910 } 1911 if (pc->this_lane == 2 || pc->this_lane == 3 || pc->this_lane == 6 || pc->this_lane == 7 || pc->this_lane == 10 || pc->this_lane == 11) { 1912 if (rdata == 0x2 || rdata == 0x3) { 1913 data = data | 0x2 ; 1914 } 1915 if (rdata == 0x1 || rdata == 0x4) { 1916 data = data | 0x0 ; 1917 } 1918 } 1919 MAIN0_SETUPr_PORT_MODE_SELf_SET(reg_main0_setup, data); 1920 } 1921 1922 PHYMOD_IF_ERR_RETURN(MODIFY_MAIN0_SETUPr(pc,reg_main0_setup)); 1923 1924 /*Tick over_write enable*/ 1925 MAIN0_TICK_CTL1r_CLR(reg_tick_ctrl); 1926 MAIN0_TICK_CTL0r_CLR(reg_tick_ctrl0); 1927 1928 MAIN0_TICK_CTL1r_TICK_OVERRIDEf_SET(reg_tick_ctrl, pc->an_tick_override); 1929 MAIN0_TICK_CTL1r_TICK_NUMERATOR_UPPERf_SET(reg_tick_ctrl, (pc->an_tick_numerator & 0x7fff0) >> 4); 1930 PHYMOD_IF_ERR_RETURN(WRITE_MAIN0_TICK_CTL1r(pc, reg_tick_ctrl)); 1931 1932 data=0; 1933 if ((pc->sc_mode == TEMOD16_SC_MODE_AN_CL37)) 1934 { 1935 /*Setting numerator to 0x10 and denominator to 0x1 for CL37*/ 1936 MAIN0_TICK_CTL0r_TICK_DENOMINATORf_SET(reg_tick_ctrl0,(pc->an_tick_denominator & 0x3ff)); 1937 MAIN0_TICK_CTL0r_TICK_NUMERATOR_LOWERf_SET(reg_tick_ctrl0,(pc->an_tick_numerator & 0xf)); 1938 PHYMOD_IF_ERR_RETURN(WRITE_MAIN0_TICK_CTL0r(pc, reg_tick_ctrl0)); 1939 } 1940 if ((pc->sc_mode == TEMOD16_SC_MODE_AN_CL73)) 1941 { 1942 /*Setting numerator to 0x80 and denominator to 0x1 for CL37*/ 1943 MAIN0_TICK_CTL0r_TICK_DENOMINATORf_SET(reg_tick_ctrl0,(pc->an_tick_denominator & 0x3ff)); 1944 MAIN0_TICK_CTL0r_TICK_NUMERATOR_LOWERf_SET(reg_tick_ctrl0,(pc->an_tick_numerator & 0xf)); 1945 PHYMOD_IF_ERR_RETURN(WRITE_MAIN0_TICK_CTL0r(pc, reg_tick_ctrl0)); 1946 } 1947 1948 1949 #if defined (_DV_TB_) 1950 /*AN from ST */ 1951 if (pc->per_lane_control & 0x4) { 1952 pc_10G_X1 = *pc; 1953 pc_10G_X1.speed = digital_operationSpeeds_SPEED_10G_KR1; 1954 pc_10G_X1_tmp = &pc_10G_X1; 1955 get_ht_entries(pc_10G_X1_tmp); 1956 if (pc->cl72_en & 0x80000000) 1957 pc_10G_X1_tmp->cl72_en = 0x0; 1958 else 1959 pc_10G_X1_tmp->cl72_en = 0x1; 1960 pc_10G_X1_tmp->cl72_en = pc_10G_X1_tmp->cl72_en | 0x40000000; 1961 _configure_st_entry(1, digital_operationSpeeds_SPEED_40G_KR4, pc_10G_X1_tmp); 1962 } 1963 else if (pc->per_lane_control & 0x8) { 1964 pc_40G_X4 = *pc; 1965 pc_40G_X4.speed = digital_operationSpeeds_SPEED_40G_KR4; 1966 pc_40G_X4_tmp = &pc_40G_X4; 1967 get_ht_entries(pc_40G_X4_tmp); 1968 if (pc->cl72_en & 0x80000000) 1969 pc_40G_X4_tmp->cl72_en = 0x0; 1970 else 1971 pc_40G_X4_tmp->cl72_en = 0x1; 1972 pc_40G_X4_tmp->cl72_en = pc_40G_X4_tmp->cl72_en | 0x40000000; 1973 _configure_st_entry(1, digital_operationSpeeds_SPEED_10G_KR1, pc_40G_X4_tmp); 1974 } 1975 else if (pc->per_lane_control & 0x20) { 1976 pc_100G_X4 = *pc; 1977 pc_100G_X4.speed = digital_operationSpeeds_SPEED_100M; 1978 pc_100G_X4_tmp = &pc_100G_X4; 1979 get_ht_entries(pc_100G_X4_tmp); 1980 pc_100G_X4_tmp->cl72_en = pc_100G_X4_tmp->cl72_en | 0x40000000; 1981 pc_100G_X4_tmp->this_lane = 0; 1982 pc_100G_X4_tmp->prt_ad = 1; 1983 _configure_st_entry(1, digital_operationSpeeds_SPEED_100G_CR10, pc_100G_X4_tmp); 1984 pc_100G_X4_tmp->this_lane = 4; 1985 pc_100G_X4_tmp->prt_ad = 5; 1986 _configure_st_entry(1, digital_operationSpeeds_SPEED_100G_CR10, pc_100G_X4_tmp); 1987 pc_100G_X4_tmp->this_lane = 8; 1988 pc_100G_X4_tmp->prt_ad = 9; 1989 _configure_st_entry(1, digital_operationSpeeds_SPEED_100G_CR10, pc_100G_X4_tmp); 1990 } 1991 #endif 1992 1993 1994 /*0x9250 AN_X1_TIMERS_cl37_restart */ 1995 AN_X1_CL37_RESTARTr_CLR(reg_cl37_restart_timers); 1996 data = pc->cl37_restart_timer_period; 1997 if (data == 0) 1998 data = 0x1f; 1999 AN_X1_CL37_RESTARTr_CL37_RESTART_TIMER_PERIODf_SET(reg_cl37_restart_timers, data); 2000 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_CL37_RESTARTr(pc, reg_cl37_restart_timers)); 2001 /*0x9251 AN_X1_TIMERS_cl37_ack */ 2002 AN_X1_CL37_ACKr_CLR(reg_cl37_ack_timers); 2003 data = pc->cl37_ack_timer_period; 2004 if (data == 0) 2005 data = 0x1f; 2006 AN_X1_CL37_ACKr_CL37_ACK_TIMER_PERIODf_SET(reg_cl37_ack_timers, data); 2007 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_CL37_ACKr(pc, reg_cl37_ack_timers)); 2008 /*0x9252 AN_X1_TIMERS_cl37_error */ 2009 AN_X1_CL37_ERRr_CLR(reg_cl37_err_timers); 2010 data = pc->cl37_error_timer_period; 2011 AN_X1_CL37_ERRr_CL37_ERROR_TIMER_PERIODf_SET(reg_cl37_err_timers, data); 2012 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_CL37_ERRr(pc, reg_cl37_err_timers)); 2013 /*0x9253 AN_X1_TIMERS_cl73_break_link */ 2014 AN_X1_CL73_BRK_LNKr_CLR(reg_cl73_brk_lnk_timers); 2015 data = pc->cl73_break_link_timer_period; 2016 AN_X1_CL73_BRK_LNKr_TX_DISABLE_TIMER_PERIODf_SET(reg_cl73_brk_lnk_timers, data); 2017 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_CL73_BRK_LNKr(pc, reg_cl73_brk_lnk_timers)); 2018 /*0x9254 AN_X1_TIMERS_cl73_error*/ 2019 AN_X1_CL73_ERRr_CLR(reg_cl73_err_timers); 2020 data = pc->cl73_error_timer_period; 2021 AN_X1_CL73_ERRr_CL73_ERROR_TIMER_PERIODf_SET(reg_cl73_err_timers, data); 2022 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_CL73_ERRr(pc, reg_cl73_err_timers)); 2023 /*TBD::0x9255 AN_X1_TIMERS_cl73_dme_lock*/ 2024 data = 100; 2025 AN_X1_CL73_DME_LOCKr_CLR(reg_cl73_dme); 2026 AN_X1_CL73_DME_LOCKr_PD_DME_LOCK_TIMER_PERIODf_SET(reg_cl73_dme, data); 2027 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_CL73_DME_LOCKr(pc, reg_cl73_dme)); 2028 /*TBD::0x9256 AN_X1_TIMERS_link_up*/ 2029 data = 32; 2030 AN_X1_LNK_UPr_CLR(reg_an_lp); 2031 AN_X1_LNK_UPr_CL73_LINK_UP_TIMER_PERIODf_SET(reg_an_lp, data); 2032 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_LNK_UPr(pc, reg_an_lp)); 2033 /*0x9257 AN_X1_TIMERS_link_fail_inhibit_timer_cl72*/ 2034 data = pc->link_fail_inhibit_timer_cl72_period; 2035 AN_X1_LNK_FAIL_INHBT_TMR_CL72r_CLR(reg_lk_fail); 2036 AN_X1_LNK_FAIL_INHBT_TMR_CL72r_LINK_FAIL_INHIBIT_TIMER_CL72_PERIODf_SET(reg_lk_fail, data); 2037 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_LNK_FAIL_INHBT_TMR_CL72r(pc, reg_lk_fail)); 2038 /*0x9258 AN_X1_TIMERS_link_fail_inhibit_timer_not_cl72*/ 2039 data = pc->link_fail_inhibit_timer_not_cl72_period; 2040 AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72r_CLR(reg_lk_fail_not72); 2041 AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72r_LINK_FAIL_INHIBIT_TIMER_NCL72_PERIODf_SET(reg_lk_fail_not72, data); 2042 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72r(pc, reg_lk_fail_not72)); 2043 /*0x9259 AN_X1_TIMERS_pd_sd_timer*/ 2044 data = pc->pd_sd_timer_period; 2045 AN_X1_PD_SD_TMRr_CLR(reg_an_pd_sd_tmr); 2046 AN_X1_PD_SD_TMRr_PD_SD_TIMER_PERIODf_SET(reg_an_pd_sd_tmr, data); 2047 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_PD_SD_TMRr(pc, reg_an_pd_sd_tmr)); 2048 /*0x925a AN_X1_TIMERS_cl72_max_wait_timer*/ 2049 data = pc->cl72_max_wait_timer; 2050 AN_X1_CL37_SYNC_STS_FILTER_TMRr_CLR(reg_an_sync_stat_fil_timer); 2051 AN_X1_CL37_SYNC_STS_FILTER_TMRr_CL37_SYNC_STATUS_FILTER_TIMER_PERIODf_SET(reg_an_sync_stat_fil_timer, data); 2052 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_CL37_SYNC_STS_FILTER_TMRr(pc, reg_an_sync_stat_fil_timer)); 2053 /*0x925b AN_X1_TIMERS_PD_TO_CL37_LINK_WAIT_TIMER*/ 2054 data = pc->pd_to_cl37_wait_timer; 2055 AN_X1_PD_TO_CL37_LNK_WAIT_TMRr_CLR(reg_an_pd_to_cl37); 2056 AN_X1_PD_TO_CL37_LNK_WAIT_TMRr_PD_TO_CL37_LINK_WAIT_TIMERf_SET(reg_an_pd_to_cl37, data); 2057 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_PD_TO_CL37_LNK_WAIT_TMRr(pc, reg_an_pd_to_cl37)); 2058 /*0x925c AN_X1_TIMERS_ignore_link_timer*/ 2059 data = pc->an_ignore_link_timer; 2060 AN_X1_IGNORE_LNK_TMRr_CLR(reg_an_ig_link_tmr); 2061 AN_X1_IGNORE_LNK_TMRr_IGNORE_LINK_TIMER_PERIODf_SET(reg_an_ig_link_tmr, data); 2062 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_IGNORE_LNK_TMRr(pc, reg_an_ig_link_tmr)); 2063 /*TBD::0x925d AN_X1_TIMERS_dme_page_timer*/ 2064 /* data = 100; 2065 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_TIMERS_DME_PAGE_TIMERr(pc->unit, pc, data)); 2066 */ 2067 /*TBD::0x925e AN_X1_TIMERS_sgmii_cl73_timer_type*/ 2068 data = 100; 2069 AN_X1_SGMII_CL73_TMR_TYPEr_CLR(reg_an_cl73_sgmii_tmr); 2070 AN_X1_SGMII_CL73_TMR_TYPEr_SGMII_TIMERf_SET(reg_an_cl73_sgmii_tmr, data); 2071 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_SGMII_CL73_TMR_TYPEr(pc, reg_an_cl73_sgmii_tmr)); 2072 /*TBD::0x9263 AN_X1_TIMERS_sgmii_cl73_timer_type*/ 2073 data = pc->tx_reset_count; 2074 SC_X1_TX_RST_CNTr_CLR(reg_sc_rst_cnt); 2075 SC_X1_TX_RST_CNTr_TX_RESET_COUNTf_SET(reg_sc_rst_cnt, data); 2076 PHYMOD_IF_ERR_RETURN(WRITE_SC_X1_TX_RST_CNTr(pc, reg_sc_rst_cnt)); 2077 /*TBD::0x924a AN_X1_CONTROL_tx_reset_timer_period*/ 2078 /*data = 20; 2079 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_CONTROL_TX_RESET_TIMER_PERIODr(pc->unit, pc, 2080 data)); */ 2081 /*TBD::0x924a AN_X1_CONTROL_pll_reset_timer */ 2082 /* data = 20; 2083 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_CONTROL_TX_RESET_TIMER_PERIODr(pc->unit, pc, 2084 data)); */ 2085 /*0x9240 AN_X1_CONTROL_oui_upper */ 2086 data = (pc->oui_upper_data & 0xff); 2087 AN_X1_OUI_UPRr_CLR(reg_an_oui_upper); 2088 AN_X1_OUI_UPRr_OUI_UPPER_DATAf_SET(reg_an_oui_upper, data); 2089 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_OUI_UPRr(pc, reg_an_oui_upper)); 2090 /*0x9241 AN_X1_CONTROL_oui_lower */ 2091 data = ((pc->oui_lower_data)); 2092 AN_X1_OUI_LWRr_CLR(reg_an_oui_lower); 2093 AN_X1_OUI_LWRr_OUI_LOWER_DATAf_SET(reg_an_oui_lower, data); 2094 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_OUI_LWRr(pc, reg_an_oui_lower)); 2095 /*0x9242 AN_X1_CONTROL_BAM_SPEED_PRI_5_0 */ 2096 data = ((pc->bam_spd_pri_5_0)); 2097 AN_X1_BAM_SPD_PRI_5_0r_CLR(reg_bam_pri5); 2098 AN_X1_BAM_SPD_PRI_5_0r_SET(reg_bam_pri5, data); 2099 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_BAM_SPD_PRI_5_0r(pc, reg_bam_pri5)); 2100 /*0x9243 AN_X1_CONTROL_BAM_SPEED_PRI_11_6 */ 2101 data = ((pc->bam_spd_pri_11_6)); 2102 AN_X1_BAM_SPD_PRI_11_6r_CLR(reg_pri11_6); 2103 AN_X1_BAM_SPD_PRI_11_6r_SET(reg_pri11_6, data); 2104 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_BAM_SPD_PRI_11_6r(pc, reg_pri11_6)); 2105 /*0x9244 AN_X1_CONTROL_BAM_SPEED_PRI_17_12 */ 2106 data = ((pc->bam_spd_pri_17_12)); 2107 AN_X1_BAM_SPD_PRI_17_12r_CLR(reg_pri17_12); 2108 AN_X1_BAM_SPD_PRI_17_12r_SET(reg_pri17_12, data); 2109 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_BAM_SPD_PRI_17_12r(pc, reg_pri17_12)); 2110 /*0x9245 AN_X1_CONTROL_BAM_SPEED_PRI_23_18 */ 2111 data = ((pc->bam_spd_pri_23_18) ); 2112 AN_X1_BAM_SPD_PRI_23_18r_CLR(reg_pri23_18); 2113 AN_X1_BAM_SPD_PRI_23_18r_SET(reg_pri23_18, data); 2114 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_BAM_SPD_PRI_23_18r(pc, reg_pri23_18)); 2115 /*0x9246 AN_X1_CONTROL_BAM_SPEED_PRI_29_24 */ 2116 data = ((pc->bam_spd_pri_29_24)); 2117 AN_X1_BAM_SPD_PRI_29_24r_CLR(reg_pri29_24); 2118 AN_X1_BAM_SPD_PRI_29_24r_SET(reg_pri29_24, data); 2119 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_BAM_SPD_PRI_29_24r(pc, reg_pri29_24)); 2120 /*0x9247 AN_X1_CONTROL_BAM_SPEED_PRI_35_30 */ 2121 data = ((pc->bam_spd_pri_35_30)); 2122 AN_X1_BAM_SPD_PRI_35_30r_CLR(reg_pri35_30); 2123 AN_X1_BAM_SPD_PRI_35_30r_SET(reg_pri35_30, data); 2124 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_BAM_SPD_PRI_35_30r(pc, reg_pri35_30)); 2125 /*0x9248 AN_X1_CONTROL_CONFIG_CONTROL */ 2126 data = pc->pd_to_cl37_retry_cnt; 2127 AN_X1_CFG_CTLr_CLR(reg_an_retry_cnt); 2128 AN_X1_CFG_CTLr_SET(reg_an_retry_cnt, data); 2129 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_CFG_CTLr(pc, reg_an_retry_cnt)); 2130 return PHYMOD_E_NONE; 2131 } /* temod16_set_an_port_mode(PHYMOD_ST* pc) */ 2132 #endif 2133 #ifdef _SDK_TEMOD16_ 2134 int temod16_set_an_port_mode(PHYMOD_ST* pc, int enable, int nl_encoded, int starting_lane, int single_port) /* SET_AN_PORT_MODE */ 2135 { 2136 uint16_t rdata; 2137 MAIN0_SETUPr_t reg_setup; 2138 int new_portmode = -1; 2139 temod16_pll_mode_type current_pll = TEMOD16_PLL_MODE_DIV_ZERO; 2140 2141 TMOD_DBG_IN_FUNC_INFO(pc); 2142 MAIN0_SETUPr_CLR(reg_setup); 2143 PHYMOD_IF_ERR_RETURN (READ_MAIN0_SETUPr(pc, ®_setup)); 2144 2145 /*Ref clock selection tied to 156.25MHz */ 2146 MAIN0_SETUPr_REFCLK_SELf_SET(reg_setup, 0x3); 2147 2148 rdata = MAIN0_SETUPr_PORT_MODE_SELf_GET(reg_setup); 2149 2150 /* nl_encoded: encoded num of lanes adv: say 0->KR, 1->KR2, 2->KR4, 3->CR10*/ 2151 if((nl_encoded == 2) || (nl_encoded == 3)) { 2152 MAIN0_SETUPr_PORT_MODE_SELf_SET(reg_setup, 0); 2153 } else { 2154 if(starting_lane == 0 || starting_lane == 1){ 2155 switch(rdata) { 2156 case 0x2: new_portmode = 0; break ; 2157 case 0x3: new_portmode = 1; break ; 2158 case 0x4: new_portmode = 1; break ; 2159 default: break ; 2160 } 2161 } 2162 if(starting_lane == 2 || starting_lane == 3){ 2163 switch(rdata) { 2164 case 0x1: new_portmode = 0; break ; 2165 case 0x3: new_portmode = 2; break ; 2166 case 0x4: new_portmode = 2; break ; 2167 default: break ; 2168 } 2169 } 2170 if((enable>0) && (new_portmode>=0)) { /* only AN enable to change this field */ 2171 MAIN0_SETUPr_PORT_MODE_SELf_SET(reg_setup, new_portmode); 2172 } 2173 } 2174 2175 /*Setting single port mode*/ 2176 MAIN0_SETUPr_SINGLE_PORT_MODEf_SET(reg_setup, single_port); 2177 2178 PHYMOD_IF_ERR_RETURN(temod16_pll_config_get(pc, ¤t_pll)); 2179 if (current_pll == TEMOD16_PLL_MODE_DIV_80) { 2180 MAIN0_SETUPr_CL37_HIGH_VCOf_SET(reg_setup, 1); 2181 } else { 2182 MAIN0_SETUPr_CL37_HIGH_VCOf_SET(reg_setup, 0); 2183 } 2184 2185 PHYMOD_IF_ERR_RETURN(MODIFY_MAIN0_SETUPr(pc,reg_setup)); 2186 2187 return PHYMOD_E_NONE; 2188 } /* temod16_set_an_port_mode(PHYMOD_ST* pc, int num_of_lanes, int starting_lane, int single_port) */ 2189 #endif /* _SDK_TEMOD16_ */ 2190 2191 /** 2192 @brief Sets loopback mode at PCS/PMD parallel interface. (PCS gloop). 2193 @param pc handle to current TSCE context (#PHYMOD_ST) 2194 @param enable loopbacks. 2195 @returns The value PHYMOD_E_NONE upon successful completion 2196 2197 This function sets the TX-to-RX digital loopback mode at the PCS/PMD parallel interface, which is set 2198 based on port_type. 2199 2200 \li 0:1 : Enable TX->RX loopback 2201 \li 0:0 : Disable TX->RX loopback 2202 2203 Note that this function can program <B>multiple lanes simultaneously</B>. 2204 2205 */ 2206 int temod16_tx_loopback_control(PHYMOD_ST* pc, int enable, int starting_lane, int num_lanes) /* TX_LOOPBACK_CONTROL */ 2207 { 2208 MAIN0_LPBK_CTLr_t reg_lb_ctrl; 2209 PMD_X4_OVRRr_t reg_pmd_ovr; 2210 PMD_X4_CTLr_t reg_pmd_ctrl; 2211 uint16_t lane_mask, data, i, data_temp; 2212 2213 TMOD_DBG_IN_FUNC_INFO(pc); 2214 data = 0; 2215 lane_mask = 0; 2216 data_temp = 0; 2217 MAIN0_LPBK_CTLr_CLR(reg_lb_ctrl); 2218 PMD_X4_OVRRr_CLR(reg_pmd_ovr); 2219 PMD_X4_CTLr_CLR(reg_pmd_ctrl); 2220 2221 for (i = 0; i < num_lanes; i++) { 2222 if (!PHYMOD_LANEPBMP_MEMBER(pc->lane_mask, starting_lane + i)) { 2223 continue; 2224 } 2225 lane_mask |= 1 << (starting_lane + i); 2226 data |= enable << (starting_lane + i); 2227 } 2228 2229 PHYMOD_IF_ERR_RETURN 2230 (READ_MAIN0_LPBK_CTLr(pc, ®_lb_ctrl)); 2231 2232 data_temp = MAIN0_LPBK_CTLr_LOCAL_PCS_LOOPBACK_ENABLEf_GET(reg_lb_ctrl); 2233 data_temp &= ~lane_mask; 2234 data |= data_temp; 2235 2236 MAIN0_LPBK_CTLr_LOCAL_PCS_LOOPBACK_ENABLEf_SET(reg_lb_ctrl, data); 2237 PHYMOD_IF_ERR_RETURN 2238 (MODIFY_MAIN0_LPBK_CTLr(pc, reg_lb_ctrl)); 2239 2240 /* signal_detect and rx_lock */ 2241 if (enable) { 2242 PMD_X4_OVRRr_RX_LOCK_OVRDf_SET(reg_pmd_ovr, 1); 2243 PMD_X4_OVRRr_SIGNAL_DETECT_OVRDf_SET(reg_pmd_ovr, 1); 2244 PMD_X4_OVRRr_TX_DISABLE_OENf_SET(reg_pmd_ovr, 1); 2245 } else { 2246 PMD_X4_OVRRr_RX_LOCK_OVRDf_SET(reg_pmd_ovr, 0); 2247 PMD_X4_OVRRr_SIGNAL_DETECT_OVRDf_SET(reg_pmd_ovr, 0); 2248 PMD_X4_OVRRr_TX_DISABLE_OENf_SET(reg_pmd_ovr, 0); 2249 } 2250 2251 PHYMOD_IF_ERR_RETURN 2252 (MODIFY_PMD_X4_OVRRr(pc, reg_pmd_ovr)); 2253 2254 /* set tx_disable */ 2255 if (enable) { 2256 PMD_X4_CTLr_TX_DISABLEf_SET(reg_pmd_ctrl, 1); 2257 } else { 2258 PMD_X4_CTLr_TX_DISABLEf_SET(reg_pmd_ctrl, 0); 2259 } 2260 PHYMOD_IF_ERR_RETURN 2261 (MODIFY_PMD_X4_CTLr(pc, reg_pmd_ctrl)); 2262 2263 return PHYMOD_E_NONE; 2264 2265 } 2266 2267 #ifdef _DV_TB_ 2268 /*! 2269 @brief Sets loopback mode at PMD serial interface. (gloop(PCS) + PMD) 2270 @param pc handle to current TSCE context (#PHYMOD_ST) 2271 @param cntl select tx/rx loopback 2272 @returns The value PHYMOD_E_NONE upon successful completion 2273 2274 This function sets the PMD TX-to-RX digital loopback mode. 2275 2276 \li 0:1 : Enable TX->RX loopback 2277 \li 0:0 : Disable TX->RX loopback 2278 2279 Note that this function can program <B>multiple lanes simultaneously</B>. 2280 As an example, to enable gloop on all lanes, 2281 set #PHYMOD_ST::per_lane_control to 0x01010101 2282 2283 */ 2284 int temod16_tx_pmd_loopback_control(PHYMOD_ST* pc, int cntl) /* TX_PMD_LOOPBACK_CONTROL */ 2285 { 2286 2287 TLB_RX_DIG_LPBK_CFGr_t reg_lpbk_cfg; 2288 2289 TMOD_DBG_IN_FUNC_INFO(pc); 2290 TLB_RX_DIG_LPBK_CFGr_CLR(reg_lpbk_cfg); 2291 READ_TLB_RX_DIG_LPBK_CFGr(pc, ®_lpbk_cfg); 2292 2293 /*cntl = (pc-> pmd_gloop);*/ 2294 if (cntl) { 2295 TLB_RX_DIG_LPBK_CFGr_DIG_LPBK_ENf_SET(reg_lpbk_cfg, 1); 2296 } else { 2297 TLB_RX_DIG_LPBK_CFGr_DIG_LPBK_ENf_SET(reg_lpbk_cfg, 0); 2298 } 2299 PHYMOD_IF_ERR_RETURN 2300 (WRITE_TLB_RX_DIG_LPBK_CFGr(pc, reg_lpbk_cfg)); 2301 2302 return PHYMOD_E_NONE; 2303 2304 } 2305 #endif 2306 2307 /** 2308 @brief pcs -> rloop 2309 @param pc handle to current TSCE context (#PHYMOD_ST) 2310 @returns The value PHYMOD_E_NONE upon successful completion 2311 2312 This function sets the RX-to-TX(PCS) Remote loopback mode, based on port_type. 2313 2314 \li 0:1 : Enable RX->TX loopback 2315 \li 0:0 : Disable RX->TX loopback 2316 2317 Note that this function can program <B>multiple lanes simultaneously</B>. 2318 As an example, to enable gloop on all lanes, 2319 set #PHYMOD_ST::per_lane_control to 0x01010101 2320 2321 */ 2322 int temod16_rx_loopback_control(PHYMOD_ST* pc, int enable, int starting_lane, int port_type) /* RX_LOOPBACK_CONTROL */ 2323 { 2324 MAIN0_LPBK_CTLr_t reg_lb_ctrl; 2325 TX_PI_CTL5r_t reg_tx_pi_ctl5; 2326 2327 /*TLB_TX_TX_PI_LOOP_TIMING_CFGr_t reg_lb_timing;*/ 2328 TX_PI_CTL0r_t reg_com_ctrl; 2329 2330 uint16_t lane_mask, data, data_temp; 2331 2332 TMOD_DBG_IN_FUNC_INFO(pc); 2333 MAIN0_LPBK_CTLr_CLR(reg_lb_ctrl); 2334 TX_PI_CTL5r_CLR(reg_tx_pi_ctl5); 2335 2336 /*TLB_TX_TX_PI_LOOP_TIMING_CFGr_CLR(reg_lb_timing);*/ 2337 TX_PI_CTL0r_CLR(reg_com_ctrl); 2338 2339 lane_mask = 0; 2340 switch (port_type) { 2341 case TEMOD16_MULTI_PORT: lane_mask = (1 << (starting_lane%4)); break; 2342 case TEMOD16_TRI1_PORT: lane_mask = ((starting_lane%4)==2)?0xc : (1 << (starting_lane%4)); break; 2343 case TEMOD16_TRI2_PORT: lane_mask = ((starting_lane%4)==0)?0x3 : (1 << (starting_lane%4)); break; 2344 case TEMOD16_DXGXS: lane_mask = ((starting_lane%4)==0)?0x3 : 0xc; break; 2345 case TEMOD16_SINGLE_PORT: lane_mask = 0xf; break; 2346 default: break ; 2347 } 2348 data = enable ? lane_mask : 0; 2349 2350 PHYMOD_IF_ERR_RETURN 2351 (READ_MAIN0_LPBK_CTLr(pc, ®_lb_ctrl)); 2352 2353 data_temp = MAIN0_LPBK_CTLr_REMOTE_PCS_LOOPBACK_ENABLEf_GET(reg_lb_ctrl); 2354 data_temp = data_temp & ~lane_mask; 2355 data = data | data_temp; 2356 2357 2358 TX_PI_CTL5r_TX_PI_REPEATER_MODE_ENf_SET(reg_tx_pi_ctl5, 0); 2359 PHYMOD_IF_ERR_RETURN 2360 (MODIFY_TX_PI_CTL5r(pc, reg_tx_pi_ctl5)); 2361 2362 /* set Tx_PI */ 2363 /* TLB_TX_TX_PI_LOOP_TIMING_CFGr_TX_PI_LOOP_TIMING_SRC_SELf_SET(reg_lb_timing, 1);*/ 2364 2365 /* PHYMOD_IF_ERR_RETURN 2366 (MODIFY_TLB_TX_TX_PI_LOOP_TIMING_CFGr(pc, reg_lb_timing));*/ 2367 2368 TX_PI_CTL0r_TX_PI_ENf_SET(reg_com_ctrl, 1); 2369 TX_PI_CTL0r_TX_PI_JITTER_FILTER_ENf_SET(reg_com_ctrl, 1); 2370 PHYMOD_IF_ERR_RETURN 2371 (MODIFY_TX_PI_CTL0r(pc, reg_com_ctrl)); 2372 2373 /* wait for 25 us here*/ 2374 2375 TX_PI_CTL0r_CLR(reg_com_ctrl); 2376 TX_PI_CTL0r_TX_PI_EXT_CTRL_ENf_SET(reg_com_ctrl, 1); 2377 PHYMOD_IF_ERR_RETURN 2378 (MODIFY_TX_PI_CTL0r(pc, reg_com_ctrl)); 2379 2380 MAIN0_LPBK_CTLr_REMOTE_PCS_LOOPBACK_ENABLEf_SET(reg_lb_ctrl, data ); 2381 PHYMOD_IF_ERR_RETURN 2382 (MODIFY_MAIN0_LPBK_CTLr(pc, reg_lb_ctrl)); 2383 2384 return PHYMOD_E_NONE; 2385 } 2386 2387 /** 2388 @brief set tx encoder of any particular lane 2389 @param pc handle to current TSCE context (#PHYMOD_ST) 2390 @returns The value PHYMOD_E_NONE upon successful completion. 2391 2392 This function is used to select encoder of any transmit lane. 2393 2394 \li select encodeMode 2395 2396 */ 2397 #ifdef _DV_TB_ 2398 int temod16_encode_set(PHYMOD_ST* pc, temod16_spd_intfc_type spd_intf) /* ENCODE_SET */ 2399 { 2400 uint16_t hg2_message_invalid_code_enable, hg2_codec, hg2_en ; 2401 TX_X4_ENC0r_t reg_encode; 2402 int cntl; 2403 2404 TMOD_DBG_IN_FUNC_INFO(pc); 2405 TX_X4_ENC0r_CLR(reg_encode); 2406 2407 printf("HiGig_Info : %-22s : pc->per_lane_control %08x : tx_higig2_en %08x : tx_higig2_codec %08x\n", __func__, pc->per_lane_control, pc->tx_higig2_en, pc->tx_higig2_codec) ; 2408 2409 cntl = pc->per_lane_control; 2410 2411 hg2_message_invalid_code_enable = 1 ; 2412 hg2_en = 0 ; /* 001 cl48 8b10b 2413 010 cl48 8b10b rxaui 2414 011 cl36 8b10b 2415 100 cl82 64b66b 2416 101 cl49 64b66b 2417 110 brcm 64b66b */ 2418 hg2_codec = 0 ; 2419 2420 if ((spd_intf == TEMOD16_SPD_10_SGMII) | 2421 (spd_intf == TEMOD16_SPD_100_SGMII) | 2422 (spd_intf == TEMOD16_SPD_1000_SGMII) | 2423 (spd_intf == TEMOD16_SPD_2500)) { 2424 hg2_message_invalid_code_enable = 0x0 ; 2425 } else if ((spd_intf == TEMOD16_SPD_10000_XFI)|| 2426 (spd_intf == TEMOD16_SPD_10600_XFI_HG)|| 2427 (spd_intf == TEMOD16_SPD_5000)) { 2428 hg2_message_invalid_code_enable = 1 ; 2429 } else if (spd_intf == TEMOD16_SPD_10000 ) { /* 10G XAUI */ 2430 hg2_message_invalid_code_enable = 0 ; 2431 } else if (spd_intf == TEMOD16_SPD_10000_HI ) { /* 10.6G HI XAUI */ 2432 hg2_message_invalid_code_enable = 0 ; 2433 } else if (spd_intf == TEMOD16_SPD_20G_MLD_DXGXS ) { 2434 hg2_message_invalid_code_enable = 1 ; 2435 } else if ((spd_intf ==TEMOD16_SPD_21G_HI_MLD_DXGXS)|| 2436 (spd_intf ==TEMOD16_SPD_12773_HI_DXGXS)) { 2437 hg2_message_invalid_code_enable = 1 ; 2438 hg2_en = 1 ; 2439 hg2_codec = 1 ; 2440 } else if ((spd_intf == TEMOD16_SPD_20G_DXGXS)|| 2441 (spd_intf == TEMOD16_SPD_21G_HI_DXGXS)) { 2442 hg2_message_invalid_code_enable = 0 ; 2443 } else if ((spd_intf == TEMOD16_SPD_42G_X4)|| 2444 (spd_intf == TEMOD16_SPD_40G_X4)|| 2445 (spd_intf == TEMOD16_SPD_25455) || 2446 (spd_intf == TEMOD16_SPD_12773_DXGXS)) { 2447 hg2_message_invalid_code_enable = 0 ; 2448 } else if (spd_intf == TEMOD16_SPD_40G_XLAUI ) { 2449 hg2_message_invalid_code_enable = 1 ; 2450 } else if (spd_intf == TEMOD16_SPD_42G_XLAUI ) { 2451 hg2_message_invalid_code_enable = 1 ; 2452 hg2_en = 1 ; 2453 hg2_codec = 1 ; 2454 } else if (spd_intf == TEMOD16_SPD_127G_HG_CR12) { 2455 hg2_message_invalid_code_enable = 1 ; 2456 hg2_en = 1 ; 2457 hg2_codec = 1 ; 2458 } else if (spd_intf == TEMOD16_SPD_107G_HG_CR10) { 2459 hg2_message_invalid_code_enable = 1 ; 2460 hg2_en = 1 ; 2461 hg2_codec = 1 ; 2462 } 2463 2464 /* NICK */ 2465 if (cntl & 0x80000000) { 2466 READ_TX_X4_ENC0r(pc, ®_encode); 2467 printf("HiGig_Info : %-22s : pc->per_lane_control %08x : TX_X4_CONTROL0_ENCODE_0 0x%04x : tx_higig2_en %01x : tx_higig2_codec %01x\n", __func__, pc->per_lane_control, 2468 reg_encode, (TX_X4_ENC0r_HG2_ENABLEf_GET(reg_encode)) & 0x1, (TX_X4_ENC0r_HG2_CODECf_GET(reg_encode)) & 0x1) ; 2469 hg2_en = pc->tx_higig2_en ; 2470 hg2_codec = pc->tx_higig2_codec ; 2471 } 2472 /* set encoder 0xc111 */ 2473 TX_X4_ENC0r_HG2_MESSAGE_INVALID_CODE_ENABLEf_SET(reg_encode, hg2_message_invalid_code_enable); 2474 TX_X4_ENC0r_HG2_CODECf_SET(reg_encode, hg2_codec); 2475 TX_X4_ENC0r_HG2_ENABLEf_SET(reg_encode, hg2_en); 2476 2477 if (pc->scramble_idle_tx_en) { 2478 TX_X4_ENC0r_T_TEST_MODE_CFGf_SET(reg_encode,pc->scramble_idle_tx_en); 2479 /* TX_X4_ENC0r_CL49_TX_TL_MODEf_SET(reg_encode,2); */ 2480 } 2481 PHYMOD_IF_ERR_RETURN (MODIFY_TX_X4_ENC0r(pc, reg_encode)); 2482 2483 return PHYMOD_E_NONE; 2484 } 2485 #endif /* _DV_TB_ */ 2486 2487 #ifdef _SDK_TEMOD16_ 2488 2489 int temod16_encode_set(PHYMOD_ST* pc, temod16_spd_intfc_type spd_intf, uint16_t enable) /* ENCODE_SET */ 2490 { 2491 uint16_t hg2_message_invalid_code_enable, hg2_codec, hg2_en ; 2492 TX_X4_ENC0r_t reg_encode; 2493 2494 TMOD_DBG_IN_FUNC_INFO(pc); 2495 TX_X4_ENC0r_CLR(reg_encode); 2496 2497 hg2_message_invalid_code_enable = 0; 2498 hg2_en = 0 ; 2499 hg2_codec = 0 ; 2500 2501 if(enable == 1) { 2502 hg2_message_invalid_code_enable = 1; 2503 hg2_en = 1; 2504 hg2_codec = 1; 2505 } 2506 2507 /* set encoder 0xc111 */ 2508 TX_X4_ENC0r_HG2_MESSAGE_INVALID_CODE_ENABLEf_SET(reg_encode, hg2_message_invalid_code_enable); 2509 TX_X4_ENC0r_HG2_CODECf_SET(reg_encode, hg2_codec); 2510 TX_X4_ENC0r_HG2_ENABLEf_SET(reg_encode, hg2_en); 2511 2512 PHYMOD_IF_ERR_RETURN 2513 (MODIFY_TX_X4_ENC0r(pc, reg_encode)); 2514 2515 return PHYMOD_E_NONE; 2516 2517 } 2518 2519 #endif /* _SDK_TEMOD16_ */ 2520 2521 /** 2522 @brief set rx decoder of any particular lane 2523 @param pc handle to current TSCE context (#PHYMOD_ST) 2524 @returns The value PHYMOD_E_NONE upon successful completion. 2525 @details This function is used to select decoder of any receive lane. 2526 2527 \li select decodeMode 2528 2529 */ 2530 2531 #ifdef _DV_TB_ 2532 int temod16_decode_set(PHYMOD_ST* pc, temod16_spd_intfc_type spd_intf) /* DECODE_SET */ 2533 { 2534 2535 uint16_t hg2_message_ivalid_code_enable, hg2_en, hg2_codec; 2536 RX_X4_DEC_CTL0r_t reg_decode_ctrl; 2537 int cntl; 2538 2539 TMOD_DBG_IN_FUNC_INFO(pc); 2540 RX_X4_DEC_CTL0r_CLR(reg_decode_ctrl); 2541 2542 /* NICK */ 2543 printf("HiGig_Info : %-22s : pc->per_lane_control %08x : rx_higig2_en %08x : rx_higig2_codec %08x\n", __func__, pc->per_lane_control, pc->rx_higig2_en, pc->rx_higig2_codec); 2544 2545 /* NICK */ 2546 cntl = pc->per_lane_control | 0x1 ; 2547 /* cntl = 1; */ 2548 2549 hg2_message_ivalid_code_enable = 0x1 ; 2550 hg2_en = 0 ; 2551 hg2_codec = 0 ; 2552 if (cntl) { /* set decoder */ 2553 2554 2555 if (spd_intf == TEMOD16_SPD_10_SGMII) { 2556 hg2_message_ivalid_code_enable = 0x0 ; 2557 } else if (spd_intf == TEMOD16_SPD_100_SGMII) { 2558 hg2_message_ivalid_code_enable = 0x0 ; 2559 } else if (spd_intf == TEMOD16_SPD_1000_SGMII) { 2560 hg2_message_ivalid_code_enable = 0x0 ; 2561 } else if (spd_intf == TEMOD16_SPD_2500) { 2562 hg2_message_ivalid_code_enable = 0x0 ; 2563 } else if ((spd_intf == TEMOD16_SPD_10000_XFI)|| 2564 (spd_intf == TEMOD16_SPD_10600_XFI_HG)|| 2565 (spd_intf == TEMOD16_SPD_5000)) { 2566 hg2_message_ivalid_code_enable = 0x1 ; 2567 } else if ( spd_intf == TEMOD16_SPD_10000 ) { /* 10G XAUI */ 2568 hg2_message_ivalid_code_enable = 0x0 ; 2569 } else if ( spd_intf == TEMOD16_SPD_10000_HI ) { /* 10G XAUI */ 2570 hg2_message_ivalid_code_enable = 0x0 ; 2571 } else if ( spd_intf == TEMOD16_SPD_20G_MLD_DXGXS ) { 2572 hg2_message_ivalid_code_enable = 0x1 ; 2573 } else if ((spd_intf ==TEMOD16_SPD_21G_HI_MLD_DXGXS)|| 2574 (spd_intf ==TEMOD16_SPD_12773_HI_DXGXS)) { 2575 hg2_message_ivalid_code_enable = 0x1 ; 2576 hg2_en = 1 ; 2577 hg2_codec = 1 ; 2578 } else if ((spd_intf == TEMOD16_SPD_20G_DXGXS)|| 2579 (spd_intf == TEMOD16_SPD_21G_HI_DXGXS)) { 2580 hg2_message_ivalid_code_enable = 0x0 ; 2581 } else if ((spd_intf == TEMOD16_SPD_42G_X4) || 2582 (spd_intf == TEMOD16_SPD_40G_X4) || 2583 (spd_intf == TEMOD16_SPD_25455) || 2584 (spd_intf == TEMOD16_SPD_12773_DXGXS)) { 2585 hg2_message_ivalid_code_enable = 0x1 ; 2586 } else if ( spd_intf == TEMOD16_SPD_40G_XLAUI ) { 2587 hg2_message_ivalid_code_enable = 0x1 ; 2588 } else if ( spd_intf == TEMOD16_SPD_42G_XLAUI ) { /* 40 MLD Hig2 */ 2589 hg2_message_ivalid_code_enable = 0x1 ; 2590 hg2_en = 1 ; 2591 hg2_codec = 1 ; 2592 } else if ( spd_intf == TEMOD16_SPD_127G_HG_CR12 ) { 2593 hg2_message_ivalid_code_enable = 0x1 ; 2594 hg2_en = 1 ; 2595 hg2_codec = 1 ; 2596 } else if ( spd_intf == TEMOD16_SPD_107G_HG_CR10 ) { 2597 hg2_message_ivalid_code_enable = 0x1 ; 2598 hg2_en = 1 ; 2599 hg2_codec = 1 ; 2600 } else { 2601 printf("%-22s ERROR: p=%0d undefined spd_intf=%0d(%s)\n", __func__, pc->port, spd_intf, 2602 e2s_temod16_spd_intfc_type[spd_intf]) ; 2603 } 2604 /* HG setting */ 2605 if ((pc->ctrl_type & TEMOD16_CTRL_TYPE_HG)) { 2606 /* not CL48 */ 2607 hg2_en = 1 ; 2608 hg2_codec = 1 ; 2609 } 2610 2611 /* NICK */ 2612 if (cntl & 0x80000000) { 2613 READ_RX_X4_DEC_CTL0r(pc, ®_decode_ctrl); 2614 #ifdef _DV_TB_ 2615 printf("HiGig_Info : %-22s : pc->per_lane_control %08x : RX_X4_CONTROL0_DECODE_CONTROL_0 0x%04x : rx_higig2_en %01x : rx_higig2_codec %01x\n", __func__, pc->per_lane_control, reg_decode_ctrl, 2616 (RX_X4_DEC_CTL0r_HG2_ENABLEf_GET(reg_decode_ctrl)) & 0x1, (RX_X4_DEC_CTL0r_HG2_CODECf_GET(reg_decode_ctrl)) & 0x1) ; 2617 #endif 2618 2619 hg2_en = pc->rx_higig2_en ; 2620 hg2_codec = pc->rx_higig2_codec ; 2621 } 2622 2623 2624 if (pc->sc_mode != TEMOD16_SC_MODE_AN_CL37 && pc->sc_mode !=TEMOD16_SC_MODE_AN_CL73) { 2625 2626 RX_X4_DEC_CTL0r_HG2_MESSAGE_INVALID_CODE_ENABLEf_SET(reg_decode_ctrl, hg2_message_ivalid_code_enable); 2627 RX_X4_DEC_CTL0r_HG2_ENABLEf_SET(reg_decode_ctrl, hg2_en); 2628 RX_X4_DEC_CTL0r_HG2_CODECf_SET(reg_decode_ctrl, hg2_codec); 2629 PHYMOD_IF_ERR_RETURN 2630 (MODIFY_RX_X4_DEC_CTL0r(pc, reg_decode_ctrl)); 2631 } 2632 } else { /* if ~cntl */ 2633 /* no op */ 2634 return PHYMOD_E_NONE; 2635 } 2636 2637 if (pc->scramble_idle_rx_en) { 2638 RX_X4_DEC_CTL0r_R_TEST_MODE_CFGf_SET(reg_decode_ctrl,pc->scramble_idle_rx_en); 2639 } 2640 if ((pc->pmd_reset_control) != 0) { 2641 temod16_pmd_reset_bypass(pc, 1); 2642 } 2643 2644 return PHYMOD_E_NONE; 2645 } /* DECODE_SET */ 2646 #endif 2647 2648 #ifdef _SDK_TEMOD16_ 2649 int temod16_decode_set(PHYMOD_ST* pc, temod16_spd_intfc_type spd_intf, uint16_t enable) /* DECODE_SET */ 2650 { 2651 2652 uint16_t hg2_message_ivalid_code_enable, hg2_en, hg2_codec; 2653 RX_X4_DEC_CTL0r_t reg_decode_ctrl; 2654 2655 TMOD_DBG_IN_FUNC_INFO(pc); 2656 RX_X4_DEC_CTL0r_CLR(reg_decode_ctrl); 2657 2658 hg2_message_ivalid_code_enable = 0x0; 2659 hg2_en = 0 ; 2660 hg2_codec = 0 ; 2661 if(enable == 1) { 2662 hg2_message_ivalid_code_enable = 1; 2663 hg2_en = 1; 2664 hg2_codec = 1; 2665 } 2666 2667 2668 RX_X4_DEC_CTL0r_HG2_MESSAGE_INVALID_CODE_ENABLEf_SET(reg_decode_ctrl, hg2_message_ivalid_code_enable); 2669 RX_X4_DEC_CTL0r_HG2_ENABLEf_SET(reg_decode_ctrl, hg2_en); 2670 RX_X4_DEC_CTL0r_HG2_CODECf_SET(reg_decode_ctrl, hg2_codec); 2671 PHYMOD_IF_ERR_RETURN 2672 (MODIFY_RX_X4_DEC_CTL0r(pc, reg_decode_ctrl)); 2673 return PHYMOD_E_NONE; 2674 } /* DECODE_SET */ 2675 2676 #endif /* SDK_TEMOD16_ */ 2677 2678 /*! 2679 @brief get port speed configured 2680 @param pc handle to current TSCE context (#PHYMOD_ST) 2681 @param get the resolved speed cfg in the spd_intf 2682 @returns The value PHYMOD_E_NONE upon successful completion. 2683 @details get port speed configured 2684 */ 2685 int temod16_spd_intf_get(PHYMOD_ST* pc, int *spd_intf) /* SET_SPD_INTF */ 2686 { 2687 SC_X4_RSLVD_SPDr_t sc_final_resolved_speed; 2688 2689 TMOD_DBG_IN_FUNC_INFO(pc); 2690 SC_X4_RSLVD_SPDr_CLR(sc_final_resolved_speed); 2691 READ_SC_X4_RSLVD_SPDr(pc,&sc_final_resolved_speed); 2692 temod16_get_actual_speed(SC_X4_RSLVD_SPDr_SPEEDf_GET(sc_final_resolved_speed), spd_intf); 2693 return PHYMOD_E_NONE; 2694 } 2695 2696 /** 2697 @brief Read the 16 bit rev. id value etc. 2698 @param pc handle to current TSCE context (#PHYMOD_ST) 2699 @param *revid int ref. to return revision id to calling function. 2700 @returns The value PHYMOD_E_NONE upon successful completion. 2701 @details 2702 This fucntion reads the revid register that contains core number, revision 2703 number and stores the 16-bit value in the field #PHYMOD_ST::accData. 2704 2705 */ 2706 int temod16_revid_read(PHYMOD_ST* pc, uint32_t *revid) 2707 { 2708 /* 2709 int laneselect; 2710 laneselect = pc->lane_select; 2711 pc->lane_select=TEMOD16_LANE_0_0_0_1; 2712 */ 2713 TMOD_DBG_IN_FUNC_INFO(pc); 2714 *revid=_temod16_getRevDetails(pc); 2715 /* 2716 pc->lane_select=laneselect; 2717 */ 2718 2719 return PHYMOD_E_NONE; 2720 } 2721 2722 #ifdef _DV_TB_ 2723 /** 2724 @brief Read the 16 bit rev. id value etc. 2725 @param pc handle to current TSCE context (#PHYMOD_ST) 2726 @returns The value PHYMOD_E_NONE upon successful completion 2727 @details Per Port PCS Init 2728 2729 */ 2730 int temod16_init_pcs(PHYMOD_ST* pc) /* INIT_PCS */ 2731 { 2732 TMOD_DBG_IN_FUNC_INFO(pc); 2733 _temod16_set_port_mode_select(pc); 2734 temod16_set_bit_repli(pc,pc->spd_intf); 2735 2736 temod16_rx_lane_control_set(pc, 1); 2737 temod16_tx_lane_control_set(pc, 1, 0); /* TX_LANE_CONTROL */ 2738 2739 /*Re-Visit, Assuming the value is non xero in case mld only */ 2740 temod16_mld_am_timers_set(pc, pc->rx_am_timer_init_val, pc->tx_am_timer_init_val); 2741 2742 if ((pc->sc_mode == TEMOD16_SC_MODE_AN_CL37) || (pc->sc_mode == TEMOD16_SC_MODE_AN_CL73)) 2743 _init_pcs_an(pc); 2744 else /* Forced Speed */ 2745 _init_pcs_fs(pc); 2746 2747 return PHYMOD_E_NONE; 2748 } 2749 #endif 2750 2751 /** 2752 @brief Init the PMD 2753 @param pc handle to current TSCE context (#PHYMOD_ST) 2754 @param pmd_touched If the PMD is already initialized 2755 @returns The value PHYMOD_E_NONE upon successful completion 2756 @details Per core PMD resets (both datapath and entire core) 2757 We only intend to use this function if the PMD has never been initialized. 2758 */ 2759 int temod16_pmd_reset_seq(PHYMOD_ST* pc, int pmd_touched) /* PMD_RESET_SEQ */ 2760 { 2761 PMD_X1_CTLr_t reg_pmd_x1_ctrl; 2762 #ifdef KEEP_THIS 2763 SC_X4_BYPASSr_t reg_bypass; 2764 SC_X4_BYPASSr_CLR(reg_bypass); 2765 #endif 2766 TMOD_DBG_IN_FUNC_INFO(pc); 2767 PMD_X1_CTLr_CLR(reg_pmd_x1_ctrl); 2768 2769 if (pmd_touched == 0) { 2770 PMD_X1_CTLr_POR_H_RSTBf_SET(reg_pmd_x1_ctrl,1); 2771 PMD_X1_CTLr_CORE_DP_H_RSTBf_SET(reg_pmd_x1_ctrl,1); 2772 PHYMOD_IF_ERR_RETURN(WRITE_PMD_X1_CTLr(pc,reg_pmd_x1_ctrl)); 2773 } 2774 2775 #ifdef KEEP_THIS 2776 SC_X4_BYPASSr_SC_BYPASSf_SET(reg_bypass, 1); 2777 PHYMOD_IF_ERR_RETURN(WRITE_SC_X4_BYPASSr(pc,reg_bypass)); 2778 #endif 2779 2780 return PHYMOD_E_NONE; 2781 } 2782 2783 /** 2784 @brief Wait for SC done bit set. 2785 @param pc handle to current TSCE context (#PHYMOD_ST) 2786 @param data handle to return SC_X4_CONTROL_STATUS reg. 2787 @returns The value PHYMOD_E_NONE upon successful completion 2788 @details Wait for SC done bit set. This is a very short wait Hence we allow a 2789 loop here. We never allow looping in tier1 as a rule. All looping should be done 2790 in tier2 and above. 2791 2792 */ 2793 int temod16_wait_sc_done(PHYMOD_ST* pc, uint16_t *data) 2794 { 2795 static int timeOut = 15; 2796 int localTimeOut = timeOut; 2797 SC_X4_STSr_t reg_sc_ctrl_sts; 2798 2799 TMOD_DBG_IN_FUNC_INFO(pc); 2800 SC_X4_STSr_CLR(reg_sc_ctrl_sts); 2801 2802 while(1) { 2803 localTimeOut--; 2804 PHYMOD_IF_ERR_RETURN(READ_SC_X4_STSr(pc, ®_sc_ctrl_sts)); 2805 if ((SC_X4_STSr_SW_SPEED_CHANGE_DONEf_GET(reg_sc_ctrl_sts) == 1) || localTimeOut < 1) 2806 break; 2807 } 2808 return PHYMOD_E_NONE; 2809 } 2810 2811 /** 2812 @brief Read the 16 bit rev. id value etc. 2813 @param pc handle to current TSCE context (#PHYMOD_ST) 2814 @returns The value PHYMOD_E_NONE upon successful completion 2815 @details Per Port PCS Init 2816 */ 2817 int _temod16_wait_sc_stats_set(PHYMOD_ST* pc) 2818 { 2819 uint16_t data; 2820 SC_X4_STSr_t reg_sc_ctrl_sts; 2821 2822 SC_X4_STSr_CLR(reg_sc_ctrl_sts); 2823 2824 while(1) { 2825 PHYMOD_IF_ERR_RETURN(READ_SC_X4_STSr(pc, ®_sc_ctrl_sts)); 2826 data = SC_X4_STSr_SW_SPEED_CONFIG_VLDf_GET(reg_sc_ctrl_sts); 2827 if (data == 1) 2828 break; 2829 } 2830 return PHYMOD_E_NONE; 2831 } 2832 2833 /** 2834 @brief Read PCS Link status 2835 @param pc handle to current TSCE context (#PHYMOD_ST) 2836 @param *link Reference for Status of PCS Link 2837 @returns The value PHYMOD_E_NONE upon successful completion 2838 @details Per Port PCS Init 2839 2840 */ 2841 int temod16_get_pcs_link_status(PHYMOD_ST* pc, uint32_t *link) 2842 { 2843 RX_X4_PCS_LIVE_STSr_t reg_pcs_live_sts; 2844 2845 TMOD_DBG_IN_FUNC_INFO(pc); 2846 RX_X4_PCS_LIVE_STSr_CLR(reg_pcs_live_sts); 2847 PHYMOD_IF_ERR_RETURN (READ_RX_X4_PCS_LIVE_STSr(pc, ®_pcs_live_sts)); 2848 *link = RX_X4_PCS_LIVE_STSr_LINK_STATUSf_GET(reg_pcs_live_sts); 2849 return PHYMOD_E_NONE; 2850 } 2851 2852 #ifdef _DV_TB_ 2853 /** 2854 @brief Read the 16 bit rev. id value etc. 2855 @param pc handle to current TSCE context (#PHYMOD_ST) 2856 @returns The value PHYMOD_E_NONE upon successful completion 2857 @details Per Port PCS Init 2858 2859 */ 2860 int temod16_mld_am_timers_set(PHYMOD_ST* pc, int rx_am_timer_init_val, int tx_am_timer_init_val) /*MLD_AM_TIMERS_SET */ 2861 { 2862 CL82_RX_AM_TMRr_t reg_rx_am_timer; 2863 TX_X2_MLD_SWP_CNTr_t reg_mld_swap_cnt; 2864 2865 TMOD_DBG_IN_FUNC_INFO(pc); 2866 CL82_RX_AM_TMRr_CLR(reg_rx_am_timer); 2867 TX_X2_MLD_SWP_CNTr_CLR(reg_mld_swap_cnt); 2868 2869 if (rx_am_timer_init_val != 0) { 2870 CL82_RX_AM_TMRr_SET(reg_rx_am_timer, rx_am_timer_init_val); 2871 PHYMOD_IF_ERR_RETURN (WRITE_CL82_RX_AM_TMRr(pc, reg_rx_am_timer)); 2872 } 2873 if (tx_am_timer_init_val != 0) { 2874 TX_X2_MLD_SWP_CNTr_SET(reg_mld_swap_cnt, tx_am_timer_init_val); 2875 PHYMOD_IF_ERR_RETURN (WRITE_TX_X2_MLD_SWP_CNTr(pc, reg_mld_swap_cnt)); 2876 } 2877 return PHYMOD_E_NONE; 2878 } 2879 #endif 2880 2881 /** 2882 @brief Disable teh Port(Forced Speed Mode) 2883 @param pc handle to current TSCE context (#PHYMOD_ST) 2884 @returns The value PHYMOD_E_NONE upon successful completion 2885 @details Per Port PCS Init 2886 2887 */ 2888 int temod16_disable_set(PHYMOD_ST* pc) /* INIT_PCS */ 2889 { 2890 SC_X4_CTLr_t reg_sc_ctrl; 2891 2892 TMOD_DBG_IN_FUNC_INFO(pc); 2893 SC_X4_CTLr_CLR(reg_sc_ctrl); 2894 2895 /* write 0 to the speed change */ 2896 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(reg_sc_ctrl, 0); 2897 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_CTLr(pc,reg_sc_ctrl)); 2898 2899 return PHYMOD_E_NONE; 2900 } 2901 2902 /** 2903 @brief Select the ILKN path and bypass TSCE PCS 2904 @param pc handle to current TSCE context (#PHYMOD_ST) 2905 @returns The value PHYMOD_E_NONE upon successful completion 2906 @details This will enable ILKN path. PCS is set to bypass to relinquish PMD 2907 control. Expect PMD to be programmed elsewhere. If we need the QSGMII PCS expect 2908 the QSGMII to be already programmed at the port layer. If not, we will feed 2909 garbage to the ILKN path. 2910 2911 */ 2912 int temod16_init_pcs_ilkn(PHYMOD_ST* pc) /* INIT_PCS */ 2913 { 2914 SC_X4_BYPASSr_t reg_sc_bypass; 2915 ILKN_CTL0r_t reg_ilkn_ctrl0; 2916 2917 TMOD_DBG_IN_FUNC_INFO(pc); 2918 SC_X4_BYPASSr_CLR(reg_sc_bypass); 2919 ILKN_CTL0r_CLR(reg_ilkn_ctrl0); 2920 2921 SC_X4_BYPASSr_SC_BYPASSf_SET(reg_sc_bypass, 1); 2922 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_BYPASSr(pc,reg_sc_bypass)); 2923 2924 ILKN_CTL0r_ILKN_SELf_SET(reg_ilkn_ctrl0, 1); 2925 ILKN_CTL0r_CREDIT_ENf_SET(reg_ilkn_ctrl0, 1); 2926 PHYMOD_IF_ERR_RETURN(MODIFY_ILKN_CTL0r(pc, reg_ilkn_ctrl0)); 2927 2928 return PHYMOD_E_NONE; 2929 } 2930 2931 /** 2932 @brief PMD per lane reset 2933 @param pc handle to current TSCE context (#PHYMOD_ST) 2934 @returns The value PHYMOD_E_NONE upon successful completion 2935 @details Per lane PMD ln_rst and ln_dp_rst by writing to PMD_X4_CONTROL in pcs space 2936 2937 */ 2938 int temod16_pmd_x4_reset(PHYMOD_ST* pc) /* PMD_X4_RESET */ 2939 { 2940 PMD_X4_CTLr_t reg_pmd_x4_ctrl; 2941 2942 TMOD_DBG_IN_FUNC_INFO(pc); 2943 PMD_X4_CTLr_CLR(reg_pmd_x4_ctrl); 2944 PMD_X4_CTLr_LN_RX_H_RSTBf_SET(reg_pmd_x4_ctrl,0); 2945 PMD_X4_CTLr_LN_TX_H_RSTBf_SET(reg_pmd_x4_ctrl,0); 2946 PMD_X4_CTLr_LN_RX_DP_H_RSTBf_SET(reg_pmd_x4_ctrl,0); 2947 PMD_X4_CTLr_LN_TX_DP_H_RSTBf_SET(reg_pmd_x4_ctrl,0); 2948 PHYMOD_IF_ERR_RETURN (MODIFY_PMD_X4_CTLr(pc, reg_pmd_x4_ctrl)); 2949 2950 PMD_X4_CTLr_CLR(reg_pmd_x4_ctrl); 2951 PMD_X4_CTLr_LN_RX_H_RSTBf_SET(reg_pmd_x4_ctrl,1); 2952 PMD_X4_CTLr_LN_TX_H_RSTBf_SET(reg_pmd_x4_ctrl,1); 2953 PMD_X4_CTLr_LN_RX_DP_H_RSTBf_SET(reg_pmd_x4_ctrl,1); 2954 PMD_X4_CTLr_LN_TX_DP_H_RSTBf_SET(reg_pmd_x4_ctrl,1); 2955 PHYMOD_IF_ERR_RETURN (MODIFY_PMD_X4_CTLr(pc, reg_pmd_x4_ctrl)); 2956 2957 return PHYMOD_E_NONE; 2958 } 2959 2960 /** 2961 @brief Initialize the PMD in independent mode. (No PCS involved) 2962 @param pc handle to current TSCE context (#PHYMOD_ST) 2963 @param pmd_touched 2964 @param uc_active 2965 @param spd_intf #temod16_spd_intfc_type 2966 @param t_pma_os_mode per lane OS Mode in PMD 2967 @returns The value PHYMOD_E_NONE upon successful completion 2968 @details Per Port PMD Init done by software 2969 2970 */ 2971 int temod16_init_pmd_sw(PHYMOD_ST* pc, int pmd_touched, int uc_active, 2972 temod16_spd_intfc_type spd_intf, int t_pma_os_mode) /* INIT_PMD_SW */ 2973 { 2974 TMOD_DBG_IN_FUNC_INFO(pc); 2975 temod16_init_pmd(pc, pmd_touched, uc_active); 2976 2977 #ifdef _DV_TB_ 2978 temod16_pmd_native_mode_set(pc, spd_intf); 2979 #endif 2980 2981 temod16_pmd_osmode_set(pc, spd_intf, t_pma_os_mode); 2982 2983 return PHYMOD_E_NONE; 2984 } 2985 2986 /** 2987 @brief Initialize PMD. for both PCS and independent modes. 2988 @param pc handle to current TSCE context (#PHYMOD_ST) 2989 @param pmd_touched Indicates this PMD was previously initialized for another 2990 port in the same core. 2991 @param uc_active Actually means PMD config. will come from PCS and not TMod 2992 @returns PHYMOD_E_NONE upon success, PHYMOD_E_FAIL else. 2993 @details Per Port PMD Init 2994 2995 */ 2996 int temod16_init_pmd(PHYMOD_ST* pc, int pmd_touched, int uc_active) /* INIT_PMD */ 2997 { 2998 /* TXFIR_MISC_CTL1r_t reg_misc1_ctrl; */ 2999 RXTXCOM_LN_CLK_RST_N_PWRDWN_CTLr_t reg_pwrdwn_ctrl; 3000 TOP_USER_CTL0r_t reg_usr_ctrl; 3001 3002 TMOD_DBG_IN_FUNC_INFO(pc); 3003 RXTXCOM_LN_CLK_RST_N_PWRDWN_CTLr_CLR(reg_pwrdwn_ctrl); 3004 TOP_USER_CTL0r_CLR(reg_usr_ctrl); 3005 3006 /* REMOVED NOT NEEDED 3007 TXFIR_MISC_CTL1r_CLR(reg_misc1_ctrl); 3008 TXFIR_MISC_CTL1r_DP_RESET_TX_DISABLE_DISf_SET(reg_misc1_ctrl, 1); 3009 PHYMOD_IF_ERR_RETURN(MODIFY_TXFIR_MISC_CTL1r(pc,reg_misc1_ctrl)); 3010 */ 3011 3012 RXTXCOM_LN_CLK_RST_N_PWRDWN_CTLr_LN_DP_S_RSTBf_SET(reg_pwrdwn_ctrl, 1); 3013 PHYMOD_IF_ERR_RETURN(MODIFY_RXTXCOM_LN_CLK_RST_N_PWRDWN_CTLr(pc, reg_pwrdwn_ctrl)); 3014 3015 if (pmd_touched == 0) { 3016 if (uc_active == 1) { 3017 TOP_USER_CTL0r_UC_ACTIVEf_SET(reg_usr_ctrl, 1); 3018 TOP_USER_CTL0r_CORE_DP_S_RSTBf_SET(reg_usr_ctrl, 1); 3019 /* release reset to pll data path. TBD need for all lanes and uc_active set */ 3020 PHYMOD_IF_ERR_RETURN (MODIFY_TOP_USER_CTL0r(pc, reg_usr_ctrl)); 3021 } else{ 3022 TOP_USER_CTL0r_CORE_DP_S_RSTBf_SET(reg_usr_ctrl, 1); 3023 PHYMOD_IF_ERR_RETURN (MODIFY_TOP_USER_CTL0r(pc, reg_usr_ctrl)); 3024 } 3025 } 3026 return PHYMOD_E_NONE; 3027 } 3028 3029 /** 3030 @brief Set Per lane OS mode set in PMD 3031 @param pc handle to current TSCE context (#PHYMOD_ST) 3032 @param spd_intf speed type #temod16_spd_intfc_type 3033 @param os_mode over sample rate. 3034 @returns The value PHYMOD_E_NONE upon successful completion 3035 @details Per Port PMD Init 3036 3037 */ 3038 int temod16_pmd_osmode_set(PHYMOD_ST* pc, temod16_spd_intfc_type spd_intf, int os_mode) /* INIT_PMD */ 3039 { 3040 RXTXCOM_OSR_MODE_CTLr_t reg_osr_mode; 3041 int speed; 3042 3043 TMOD_DBG_IN_FUNC_INFO(pc); 3044 RXTXCOM_OSR_MODE_CTLr_CLR(reg_osr_mode); 3045 temod16_get_mapped_speed(spd_intf, &speed); 3046 3047 /*os_mode = 0x0; */ /* 0= OS MODE 1; 1= OS MODE 2; 2=OS MODE 3; 3048 3=OS MODE 3.3; 4=OS MODE 4; 5=OS MODE 5; 3049 6=OS MODE 8; 7=OS MODE 8.25; 8: OS MODE 10*/ 3050 if (os_mode & 0x80000000) { 3051 os_mode = (os_mode) & 0x0000ffff; 3052 } 3053 else { 3054 os_mode = merlin16_sc_pmd_entry[speed].t_pma_os_mode; 3055 } 3056 3057 RXTXCOM_OSR_MODE_CTLr_OSR_MODE_FRCf_SET(reg_osr_mode, 1); 3058 RXTXCOM_OSR_MODE_CTLr_OSR_MODE_FRC_VALf_SET(reg_osr_mode, os_mode); 3059 3060 PHYMOD_IF_ERR_RETURN 3061 (MODIFY_RXTXCOM_OSR_MODE_CTLr(pc, reg_osr_mode)); 3062 3063 return PHYMOD_E_NONE; 3064 } 3065 3066 /** 3067 @brief Get Per lane OS mode set in PMD 3068 @param pc handle to current TSCE context (#PHYMOD_ST) 3069 @param os_mode over sample rate. 3070 @returns The value PHYMOD_E_NONE upon successful completion 3071 @details Per Port PMD Init 3072 3073 */ 3074 int temod16_pmd_osmode_get(PHYMOD_ST* pc, int *os_mode) /* INIT_PMD */ 3075 { 3076 RXTXCOM_OSR_MODE_CTLr_t reg_osr_mode; 3077 3078 TMOD_DBG_IN_FUNC_INFO(pc); 3079 RXTXCOM_OSR_MODE_CTLr_CLR(reg_osr_mode); 3080 3081 PHYMOD_IF_ERR_RETURN 3082 (READ_RXTXCOM_OSR_MODE_CTLr(pc, ®_osr_mode)); 3083 3084 if(RXTXCOM_OSR_MODE_CTLr_OSR_MODE_FRCf_GET(reg_osr_mode) == 1) 3085 *os_mode = RXTXCOM_OSR_MODE_CTLr_OSR_MODE_FRC_VALf_GET(reg_osr_mode); 3086 else 3087 *os_mode = 0xff; 3088 3089 return PHYMOD_E_NONE; 3090 } 3091 3092 #ifdef _DV_TB_ 3093 int temod16_pmd_native_mode_set(PHYMOD_ST* pc, temod16_spd_intfc_type spd_intf) 3094 { 3095 TLB_TX_TLB_TX_MISC_CFGr_t reg_tx_misc; 3096 3097 TMOD_DBG_IN_FUNC_INFO(pc); 3098 TLB_TX_TLB_TX_MISC_CFGr_CLR(reg_tx_misc); 3099 3100 if ( 3101 spd_intf == TEMOD16_SPD_10000 || 3102 spd_intf == TEMOD16_SPD_15000 || 3103 spd_intf == TEMOD16_SPD_16000 || 3104 spd_intf == TEMOD16_SPD_10000_DXGXS || 3105 spd_intf == TEMOD16_SPD_20000 3106 ) { 3107 TLB_TX_TLB_TX_MISC_CFGr_TX_PCS_NATIVE_ANA_FRMT_ENf_SET(reg_tx_misc,pc->bit_rep_native_mode); 3108 } 3109 3110 PHYMOD_IF_ERR_RETURN (MODIFY_TLB_TX_TLB_TX_MISC_CFGr(pc, reg_tx_misc)); 3111 3112 return PHYMOD_E_NONE; 3113 } 3114 #endif 3115 /** 3116 @brief Enable FEC for forced Speeds. Will be rewritten in FEC_control 3117 @param pc handle to current TSCE context (#PHYMOD_ST) 3118 @returns The value PHYMOD_E_NONE upon successful completion 3119 @details Enable FEC for forced speeds. 3120 3121 */ 3122 int temod16_fecmode_set(PHYMOD_ST* pc, int fec_enable) /* FECMODE_SET */ 3123 { 3124 TX_X4_MISCr_t reg_misc; 3125 RX_X4_DEC_CTL0r_t reg_decode; 3126 SC_X4_CTLr_t reg; 3127 phymod_access_t pa_copy; 3128 int start_lane = 0, num_lane = 0; 3129 3130 3131 TMOD_DBG_IN_FUNC_INFO(pc); 3132 TX_X4_MISCr_CLR(reg_misc); 3133 RX_X4_DEC_CTL0r_CLR(reg_decode); 3134 SC_X4_CTLr_CLR(reg); 3135 3136 PHYMOD_MEMCPY(&pa_copy, pc, sizeof(pa_copy)); 3137 PHYMOD_IF_ERR_RETURN 3138 (phymod_util_lane_config_get(pc, &start_lane, &num_lane)); 3139 pa_copy.lane_mask = 0x1 << start_lane; 3140 3141 TX_X4_MISCr_FEC_ENABLEf_SET(reg_misc, fec_enable); 3142 PHYMOD_IF_ERR_RETURN (MODIFY_TX_X4_MISCr(pc, reg_misc)); 3143 3144 RX_X4_DEC_CTL0r_BLOCK_SYNC_MODEf_SET(reg_decode, (fec_enable << 2)); 3145 PHYMOD_IF_ERR_RETURN (MODIFY_RX_X4_DEC_CTL0r(pc, reg_decode)); 3146 3147 3148 PHYMOD_IF_ERR_RETURN(READ_SC_X4_CTLr(&pa_copy, ®)); 3149 if (SC_X4_CTLr_SW_SPEED_CHANGEf_GET(reg) == 1) { 3150 PHYMOD_IF_ERR_RETURN (temod16_trigger_speed_change(&pa_copy)); 3151 } 3152 3153 return PHYMOD_E_NONE; 3154 } 3155 3156 int temod16_fecmode_get(PHYMOD_ST* pc, uint32_t *fec_enable) 3157 { 3158 TX_X4_MISCr_t reg_misc; 3159 SC_X4_CTLr_t reg; 3160 AN_X4_ENSr_t reg_an_enb; 3161 AN_X4_AN_ABIL_RESOLUTION_STSr_t an_hcd_status; 3162 3163 TMOD_DBG_IN_FUNC_INFO(pc); 3164 TX_X4_MISCr_CLR(reg_misc); 3165 SC_X4_CTLr_CLR(reg); 3166 AN_X4_ENSr_CLR(reg_an_enb); 3167 3168 PHYMOD_IF_ERR_RETURN(READ_SC_X4_CTLr(pc, ®)); 3169 PHYMOD_IF_ERR_RETURN (READ_AN_X4_ENSr(pc, ®_an_enb)); 3170 3171 *fec_enable = 0; 3172 if(AN_X4_ENSr_CL73_ENABLEf_GET(reg_an_enb) == 1){ 3173 READ_AN_X4_AN_ABIL_RESOLUTION_STSr(pc,&an_hcd_status); 3174 *fec_enable = AN_X4_AN_ABIL_RESOLUTION_STSr_AN_HCD_FECf_GET(an_hcd_status); 3175 } else if(SC_X4_CTLr_SW_SPEED_CHANGEf_GET(reg) == 1) { 3176 PHYMOD_IF_ERR_RETURN (READ_TX_X4_MISCr(pc, ®_misc)); 3177 *fec_enable = TX_X4_MISCr_FEC_ENABLEf_GET(reg_misc); 3178 } 3179 3180 return PHYMOD_E_NONE; 3181 } 3182 3183 /** 3184 @brief Generic Override mechanism. Any PCS parameter can be overriden. 3185 @param pc handle to current TSCE context (#PHYMOD_ST) 3186 param cntl bit mask of parameters to override. 3187 @returns The value PHYMOD_E_NONE upon successful completion 3188 @details The cntl encoding is as follows. 3189 3190 NUM_LANES_OEN | 3191 OS_MODE_OEN | 3192 FEC_ENABLE_OEN | 3193 DESKEWMODE_OEN | 3194 DESC2_MODE_OEN | 3195 CL36BYTEDELETEMOD16E_OEN | 3196 BRCM64B66_DESCRAMBLER_ENABLE_OEN | 3197 CHK_END_EN_OEN | 3198 BLOCK_SYNC_MODE_OEN | 3199 DECODERMODE_OEN | 3200 ENCODEMODE_OEN | 3201 DESCRAMBLERMODE_OEN | 3202 SCR_MODE_OEN 3203 3204 */ 3205 int temod16_override_set(PHYMOD_ST* pc, override_type_t or_type, uint16_t or_val) /* OVERRIDE_SET */ 3206 { 3207 int or_value; 3208 SC_X4_FLD_OVRR_EN0_TYPEr_t reg_or_en0; 3209 SC_X4_FLD_OVRR_EN1_TYPEr_t reg_or_en1; 3210 LNK_CTLr_t reg_cl72_link_ctrl; 3211 SC_X4_LN_NUM_OVRRr_t reg_ln_num_or_val; 3212 RX_X4_PMA_CTL0r_t reg_os_mode_or_val; 3213 TX_X4_MISCr_t reg_misc_or_val; 3214 RX_X4_PCS_CTL0r_t reg_pcs_or_val; 3215 RX_X2_MISC0r_t reg_misc0_or_val; 3216 RX_X4_DEC_CTL0r_t reg_dec_or_val; 3217 RX_X4_CL36_RX0r_t reg_cl36_or_val; 3218 TX_X4_ENC0r_t reg_encode_or_val; 3219 3220 TMOD_DBG_IN_FUNC_INFO(pc); 3221 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(reg_or_en0); 3222 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(reg_or_en1); 3223 3224 or_value = or_val & 0x0000ffff; 3225 switch (or_type) { 3226 case TEMOD16_OVERRIDE_RESET : 3227 /* reset credits */ 3228 WRITE_SC_X4_FLD_OVRR_EN0_TYPEr(pc,reg_or_en0); 3229 3230 SC_X4_FLD_OVRR_EN1_TYPEr_CL72_EN_OENf_SET(reg_or_en1, 0); 3231 SC_X4_FLD_OVRR_EN1_TYPEr_REORDER_EN_OENf_SET(reg_or_en1, 0); 3232 SC_X4_FLD_OVRR_EN1_TYPEr_CL36_EN_OENf_SET(reg_or_en1, 0); 3233 MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc,reg_or_en1); 3234 break; 3235 case TEMOD16_OVERRIDE_ALL : 3236 /* get info. from table and apply it to all credit regs. */ 3237 break; 3238 case TEMOD16_OVERRIDE_CL72 : 3239 LNK_CTLr_CLR(reg_cl72_link_ctrl); 3240 LNK_CTLr_LINK_CONTROL_FORCEVALf_SET(reg_cl72_link_ctrl, or_value); 3241 MODIFY_LNK_CTLr(pc,reg_cl72_link_ctrl); 3242 /*Set the override enable*/ 3243 if (or_value == 0) { 3244 SC_X4_FLD_OVRR_EN1_TYPEr_CL72_EN_OENf_SET(reg_or_en1, 1); 3245 } else { 3246 SC_X4_FLD_OVRR_EN1_TYPEr_CL72_EN_OENf_SET(reg_or_en1, 0); 3247 } 3248 MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc,reg_or_en1); 3249 break; 3250 case TEMOD16_OVERRIDE_NUM_LANES : 3251 SC_X4_LN_NUM_OVRRr_CLR(reg_ln_num_or_val); 3252 SC_X4_LN_NUM_OVRRr_NUM_LANES_OVERRIDE_VALUEf_SET(reg_ln_num_or_val,or_value); 3253 MODIFY_SC_X4_LN_NUM_OVRRr(pc,reg_ln_num_or_val); 3254 /*Set the override enable*/ 3255 SC_X4_FLD_OVRR_EN0_TYPEr_NUM_LANES_OENf_SET(reg_or_en0,1); 3256 MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc,reg_or_en0); 3257 break; 3258 case TEMOD16_OVERRIDE_OS_MODE: 3259 RX_X4_PMA_CTL0r_CLR(reg_os_mode_or_val); 3260 RX_X4_PMA_CTL0r_OS_MODEf_SET(reg_os_mode_or_val,or_value); 3261 MODIFY_RX_X4_PMA_CTL0r(pc,reg_os_mode_or_val); 3262 /*Set the override enable*/ 3263 SC_X4_FLD_OVRR_EN0_TYPEr_OS_MODE_OENf_SET(reg_or_en0,1); 3264 MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc,reg_or_en0); 3265 break; 3266 case TEMOD16_OVERRIDE_FEC_EN : 3267 TX_X4_MISCr_CLR(reg_misc_or_val); 3268 TX_X4_MISCr_FEC_ENABLEf_SET(reg_misc_or_val,or_value); 3269 MODIFY_TX_X4_MISCr(pc,reg_misc_or_val); 3270 /*Set the override enable*/ 3271 SC_X4_FLD_OVRR_EN0_TYPEr_FEC_ENABLE_OENf_SET(reg_or_en0,1); 3272 MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc,reg_or_en0); 3273 break; 3274 case TEMOD16_OVERRIDE_DESKEW_MODE: 3275 RX_X4_PCS_CTL0r_CLR(reg_pcs_or_val); 3276 RX_X4_PCS_CTL0r_DESKEWMODEf_SET(reg_pcs_or_val,or_value); 3277 MODIFY_RX_X4_PCS_CTL0r(pc,reg_pcs_or_val); 3278 /*Set the override enable*/ 3279 SC_X4_FLD_OVRR_EN0_TYPEr_DESKEWMODE_OENf_SET(reg_or_en0,1); 3280 MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc,reg_or_en0); 3281 break; 3282 case TEMOD16_OVERRIDE_DESC2_MODE : 3283 RX_X4_PCS_CTL0r_CLR(reg_pcs_or_val); 3284 RX_X4_PCS_CTL0r_DESC2_MODEf_SET(reg_pcs_or_val,or_value); 3285 MODIFY_RX_X4_PCS_CTL0r(pc,reg_pcs_or_val); 3286 /*Set the override enable*/ 3287 SC_X4_FLD_OVRR_EN0_TYPEr_DESC2_MODE_OENf_SET(reg_or_en0,1); 3288 MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc,reg_or_en0); 3289 break; 3290 case TEMOD16_OVERRIDE_CL36BYTEDEL_MODE: 3291 RX_X4_PCS_CTL0r_CLR(reg_pcs_or_val); 3292 RX_X4_PCS_CTL0r_CL36BYTEDELETEMODEf_SET(reg_pcs_or_val,or_value); 3293 MODIFY_RX_X4_PCS_CTL0r(pc,reg_pcs_or_val); 3294 /*Set the override enable*/ 3295 SC_X4_FLD_OVRR_EN0_TYPEr_CL36BYTEDELETEMODE_OENf_SET(reg_or_en0,1); 3296 MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc,reg_or_en0); 3297 break; 3298 case TEMOD16_OVERRIDE_BRCM64B66_DESCR_MODE: 3299 RX_X4_PCS_CTL0r_CLR(reg_pcs_or_val); 3300 RX_X4_PCS_CTL0r_BRCM64B66_DESCRAMBLER_ENABLEf_SET(reg_pcs_or_val,or_value); 3301 MODIFY_RX_X4_PCS_CTL0r(pc,reg_pcs_or_val); 3302 /*Set the override enable*/ 3303 SC_X4_FLD_OVRR_EN0_TYPEr_BRCM64B66_DESCRAMBLER_ENABLE_OENf_SET(reg_or_en0,1); 3304 MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc,reg_or_en0); 3305 break; 3306 case TEMOD16_OVERRIDE_CHKEND_EN: 3307 RX_X2_MISC0r_CLR(reg_misc0_or_val); 3308 RX_X2_MISC0r_CHK_END_ENf_SET(reg_misc0_or_val, or_value); 3309 MODIFY_RX_X2_MISC0r(pc,reg_misc0_or_val); 3310 /*Set the override enable*/ 3311 SC_X4_FLD_OVRR_EN0_TYPEr_CHK_END_EN_OENf_SET(reg_or_en0,1); 3312 MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc,reg_or_en0); 3313 break; 3314 case TEMOD16_OVERRIDE_BLKSYNC_MODE: 3315 RX_X4_DEC_CTL0r_CLR(reg_dec_or_val); 3316 RX_X4_DEC_CTL0r_BLOCK_SYNC_MODEf_SET(reg_dec_or_val,or_value); 3317 MODIFY_RX_X4_DEC_CTL0r(pc, reg_dec_or_val); 3318 /*Set the override enable*/ 3319 SC_X4_FLD_OVRR_EN0_TYPEr_BLOCK_SYNC_MODE_OENf_SET(reg_or_en0,1); 3320 MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc,reg_or_en0); 3321 break; 3322 case TEMOD16_OVERRIDE_REORDER_EN : 3323 RX_X4_CL36_RX0r_CLR(reg_cl36_or_val); 3324 RX_X4_CL36_RX0r_REORDER_ENf_SET(reg_cl36_or_val, or_value); 3325 MODIFY_RX_X4_CL36_RX0r(pc,reg_cl36_or_val); 3326 /*Set the override enable*/ 3327 SC_X4_FLD_OVRR_EN1_TYPEr_REORDER_EN_OENf_SET(reg_or_en1, 1); 3328 MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc,reg_or_en1); 3329 break; 3330 case TEMOD16_OVERRIDE_CL36_EN: 3331 RX_X4_CL36_RX0r_CLR(reg_cl36_or_val); 3332 RX_X4_CL36_RX0r_CL36_ENf_SET(reg_cl36_or_val, or_value); 3333 MODIFY_RX_X4_CL36_RX0r(pc,reg_cl36_or_val); 3334 /*Set the override enable*/ 3335 SC_X4_FLD_OVRR_EN1_TYPEr_CL36_EN_OENf_SET(reg_or_en1, 1); 3336 MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc,reg_or_en1); 3337 break; 3338 case TEMOD16_OVERRIDE_SCR_MODE: 3339 TX_X4_MISCr_CLR(reg_misc_or_val); 3340 TX_X4_MISCr_SCR_MODEf_SET(reg_misc_or_val,or_value); 3341 MODIFY_TX_X4_MISCr(pc,reg_misc_or_val); 3342 /*Set the override enable*/ 3343 SC_X4_FLD_OVRR_EN0_TYPEr_SCR_MODE_OENf_SET(reg_or_en0,1); 3344 MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc,reg_or_en0); 3345 break; 3346 case TEMOD16_OVERRIDE_DESCR_MODE: 3347 RX_X4_PCS_CTL0r_CLR(reg_pcs_or_val); 3348 RX_X4_PCS_CTL0r_DESCRAMBLERMODEf_SET(reg_pcs_or_val,or_value); 3349 MODIFY_RX_X4_PCS_CTL0r(pc,reg_pcs_or_val); 3350 /*Set the override enable*/ 3351 SC_X4_FLD_OVRR_EN0_TYPEr_DESCRAMBLERMODE_OENf_SET(reg_or_en0,1); 3352 MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc,reg_or_en0); 3353 break; 3354 case TEMOD16_OVERRIDE_ENCODE_MODE: 3355 TX_X4_ENC0r_CLR(reg_encode_or_val); 3356 TX_X4_ENC0r_ENCODEMODEf_SET(reg_encode_or_val, or_value); 3357 MODIFY_TX_X4_ENC0r(pc,reg_encode_or_val); 3358 /*Set the override enable*/ 3359 SC_X4_FLD_OVRR_EN0_TYPEr_ENCODEMODE_OENf_SET(reg_or_en0,1); 3360 MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc,reg_or_en0); 3361 break; 3362 case TEMOD16_OVERRIDE_DECODE_MODE: 3363 RX_X4_PCS_CTL0r_CLR(reg_pcs_or_val); 3364 RX_X4_PCS_CTL0r_DECODERMODEf_SET(reg_pcs_or_val,or_value); 3365 MODIFY_RX_X4_PCS_CTL0r(pc,reg_pcs_or_val); 3366 /*Set the override enable*/ 3367 SC_X4_FLD_OVRR_EN0_TYPEr_DECODERMODE_OENf_SET(reg_or_en0,1); 3368 MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc,reg_or_en0); 3369 break; 3370 case TEMOD16_OVERRIDE_SPDID : 3371 /* get info. from table and apply it to all credit regs. */ 3372 break; 3373 } 3374 return PHYMOD_E_NONE; 3375 3376 } 3377 3378 /** 3379 @brief Override the credits. 3380 @param pc handle to current TSCE context (#PHYMOD_ST) 3381 @param credit_type type of credit to override #credit_type_t 3382 @param userCredit User override value 3383 @returns The value PHYMOD_E_NONE upon successful completion 3384 @details Credit override mechanism is a seperate function. However it is similar 3385 to other override mechanisms. 3386 3387 */ 3388 int temod16_credit_override_set(PHYMOD_ST* pc, credit_type_t credit_type, int userCredit) /* CREDIT_OVERRIDE_SET */ 3389 { 3390 SC_X4_FLD_OVRR_EN1_TYPEr_t reg_enable_type; 3391 TX_X4_CRED0r_t reg_credit0; 3392 TX_X4_CRED1r_t reg_credit1; 3393 TX_X4_LOOPCNTr_t reg_loopcnt; 3394 TX_X4_MAC_CREDGENCNTr_t reg_maccreditgen; 3395 TX_X4_PCS_CLKCNT0r_t reg_pcs_clk_cnt; 3396 TX_X4_PCS_CREDGENCNTr_t reg_pcs_creditgen; 3397 3398 TMOD_DBG_IN_FUNC_INFO(pc); 3399 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(reg_enable_type); 3400 TX_X4_CRED0r_CLR(reg_credit0); 3401 TX_X4_CRED1r_CLR(reg_credit1); 3402 TX_X4_LOOPCNTr_CLR(reg_loopcnt); 3403 TX_X4_MAC_CREDGENCNTr_CLR(reg_maccreditgen); 3404 TX_X4_PCS_CLKCNT0r_CLR(reg_pcs_clk_cnt); 3405 TX_X4_PCS_CREDGENCNTr_CLR(reg_pcs_creditgen); 3406 3407 switch ( credit_type ) { 3408 case TEMOD16_CREDIT_RESET: 3409 /* reset credits */ 3410 SC_X4_FLD_OVRR_EN1_TYPEr_CLOCKCNT0_OENf_SET(reg_enable_type, 0); 3411 SC_X4_FLD_OVRR_EN1_TYPEr_CLOCKCNT1_OENf_SET(reg_enable_type, 0); 3412 SC_X4_FLD_OVRR_EN1_TYPEr_LOOPCNT0_OENf_SET(reg_enable_type, 0); 3413 SC_X4_FLD_OVRR_EN1_TYPEr_LOOPCNT1_OENf_SET(reg_enable_type, 0); 3414 SC_X4_FLD_OVRR_EN1_TYPEr_REPLICATION_CNT_OENf_SET(reg_enable_type, 0); 3415 SC_X4_FLD_OVRR_EN1_TYPEr_MAC_CREDITGENCNT_OENf_SET(reg_enable_type, 0); 3416 SC_X4_FLD_OVRR_EN1_TYPEr_PCS_CREDITENABLE_OENf_SET(reg_enable_type, 0); 3417 SC_X4_FLD_OVRR_EN1_TYPEr_PCS_CLOCKCNT0_OENf_SET(reg_enable_type, 0); 3418 SC_X4_FLD_OVRR_EN1_TYPEr_PCS_CREDITGENCNT_OENf_SET(reg_enable_type, 0); 3419 SC_X4_FLD_OVRR_EN1_TYPEr_SGMII_SPD_SWITCH_OENf_SET(reg_enable_type, 0); 3420 3421 PHYMOD_IF_ERR_RETURN(WRITE_SC_X4_FLD_OVRR_EN1_TYPEr(pc, reg_enable_type)); 3422 break; 3423 case TEMOD16_CREDIT_TABLE: 3424 /* get info. from table and apply it to all credit regs. */ 3425 break; 3426 case TEMOD16_CREDIT_CLOCK_COUNT_0: 3427 /* write to clockcnt0 */ 3428 TX_X4_CRED0r_CLOCKCNT0f_SET(reg_credit0, userCredit); 3429 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_CRED0r(pc, reg_credit0)); 3430 /*Set the override enable*/ 3431 SC_X4_FLD_OVRR_EN1_TYPEr_CLOCKCNT0_OENf_SET(reg_enable_type, 1); 3432 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, reg_enable_type)); 3433 break; 3434 case TEMOD16_CREDIT_CLOCK_COUNT_1: /* (cntl & 0x00020000) */ 3435 /* write to clockcnt1 */ 3436 TX_X4_CRED1r_CLOCKCNT1f_SET(reg_credit1, userCredit); 3437 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_CRED1r(pc, reg_credit1)); 3438 /*Set the override enable*/ 3439 SC_X4_FLD_OVRR_EN1_TYPEr_CLOCKCNT1_OENf_SET(reg_enable_type, 1); 3440 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, reg_enable_type)); 3441 break; 3442 case TEMOD16_CREDIT_LOOP_COUNT_0: 3443 /* write to loopcnt0 */ 3444 TX_X4_LOOPCNTr_LOOPCNT0f_SET(reg_loopcnt, userCredit); 3445 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_LOOPCNTr(pc, reg_loopcnt)); 3446 /*Set the override enable*/ 3447 SC_X4_FLD_OVRR_EN1_TYPEr_LOOPCNT0_OENf_SET(reg_enable_type, 1); 3448 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, reg_enable_type)); 3449 break; 3450 case TEMOD16_CREDIT_LOOP_COUNT_1: /* (cntl & 0x00080000) */ 3451 /* write to pcs_clockcnt0 */ 3452 TX_X4_LOOPCNTr_LOOPCNT1f_SET(reg_loopcnt, userCredit); 3453 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_LOOPCNTr(pc, reg_loopcnt)); 3454 /*Set the override enable*/ 3455 SC_X4_FLD_OVRR_EN1_TYPEr_LOOPCNT1_OENf_SET(reg_enable_type, 1); 3456 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, reg_enable_type)); 3457 break; 3458 case TEMOD16_CREDIT_MAC: /* (cntl & 0x00100000) */ 3459 /* write to mac_creditgencnt */ 3460 TX_X4_MAC_CREDGENCNTr_MAC_CREDITGENCNTf_SET(reg_maccreditgen, userCredit); 3461 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_MAC_CREDGENCNTr(pc, reg_maccreditgen)); 3462 /*Set the override enable*/ 3463 SC_X4_FLD_OVRR_EN1_TYPEr_MAC_CREDITGENCNT_OENf_SET(reg_enable_type, 1); 3464 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, reg_enable_type)); 3465 break; 3466 case TEMOD16_CREDIT_PCS_CLOCK_COUNT_0: /* (cntl & 0x00200000) */ 3467 /* write to pcs_clockcnt0 */ 3468 TX_X4_PCS_CLKCNT0r_PCS_CLOCKCNT0f_SET(reg_pcs_clk_cnt, userCredit); 3469 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_PCS_CLKCNT0r(pc, reg_pcs_clk_cnt)); 3470 /*Set the override enable*/ 3471 SC_X4_FLD_OVRR_EN1_TYPEr_PCS_CLOCKCNT0_OENf_SET(reg_enable_type, 1); 3472 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, reg_enable_type)); 3473 break; 3474 case TEMOD16_CREDIT_PCS_GEN_COUNT: /* (cntl & 0x00400000) */ 3475 /* write to pcs_creditgencnt */ 3476 TX_X4_PCS_CREDGENCNTr_PCS_CREDITGENCNTf_SET(reg_pcs_creditgen, userCredit) ; 3477 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_PCS_CREDGENCNTr(pc, reg_pcs_creditgen)); 3478 /*Set the override enable*/ 3479 SC_X4_FLD_OVRR_EN1_TYPEr_PCS_CREDITGENCNT_OENf_SET(reg_enable_type, 1); 3480 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, reg_enable_type)); 3481 break; 3482 case TEMOD16_CREDIT_EN: /* (cntl & 0x00800000) */ 3483 /* write to pcs_crden */ 3484 TX_X4_PCS_CLKCNT0r_PCS_CREDITENABLEf_SET(reg_pcs_clk_cnt, userCredit); 3485 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_PCS_CLKCNT0r(pc, reg_pcs_clk_cnt)); 3486 /*Set the override enable*/ 3487 SC_X4_FLD_OVRR_EN1_TYPEr_PCS_CREDITENABLE_OENf_SET(reg_enable_type, 1); 3488 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, reg_enable_type)); 3489 break; 3490 case TEMOD16_CREDIT_PCS_REPCNT: /* (cntl & 0x01000000) */ 3491 /* write to pcs_repcnt */ 3492 TX_X4_PCS_CLKCNT0r_REPLICATION_CNTf_SET(reg_pcs_clk_cnt, userCredit); 3493 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_PCS_CLKCNT0r(pc, reg_pcs_clk_cnt)); 3494 /*Set the override enable*/ 3495 SC_X4_FLD_OVRR_EN1_TYPEr_REPLICATION_CNT_OENf_SET(reg_enable_type, 1); 3496 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, reg_enable_type)); 3497 break; 3498 case TEMOD16_CREDIT_SGMII_SPD: /* (cntl & 0x02000000) */ 3499 /* write to sgmii */ 3500 TX_X4_CRED0r_SGMII_SPD_SWITCHf_SET(reg_credit0, userCredit); 3501 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_CRED0r(pc, reg_credit0)); 3502 /*Set the override enable*/ 3503 SC_X4_FLD_OVRR_EN1_TYPEr_SGMII_SPD_SWITCH_OENf_SET(reg_enable_type, 1); 3504 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, reg_enable_type)); 3505 break; 3506 default: 3507 return PHYMOD_E_FAIL; 3508 break; 3509 } 3510 return PHYMOD_E_NONE; 3511 } /* CREDIT_SET */ 3512 3513 /** 3514 @brief Read the 16 bit rev. id value etc. 3515 @param pc handle to current TSCE context (#PHYMOD_ST) 3516 @returns The value PHYMOD_E_NONE upon successful completion 3517 @details 3518 3519 */ 3520 int temod16_pmd_lane_reset(PHYMOD_ST* pc) /* PMD_LANE_RESET */ 3521 { 3522 TMOD_DBG_IN_FUNC_INFO(pc); 3523 return PHYMOD_E_NONE; 3524 } 3525 3526 #ifdef _DV_TB_ 3527 /** 3528 @brief Control per lane clause 72 auto tuning function (training patterns) 3529 @param pc handle to current TSCE context (#PHYMOD_ST) 3530 @param cl_72_type #cl72_type_t 3531 @returns The value PHYMOD_E_NONE upon successful completion 3532 @details 3533 This function enables/disables clause-72 auto-tuning per lane. It is used 3534 in 40G_KR4, 40G_CR4, 10G_KR modes etc. 3535 Lane is selected via #PHYMOD_ST::lane_select. 3536 This Function is controlled by #PHYMOD_ST::per_lane_control as follows. 3537 3538 \li 0Xxxxxxxx3 (b11): Enable CL72 hardware block 3539 \li 0Xxxxxxxx2 (b01): Disable CL72 hardware block 3540 \li 0Xxxxxxxx0 (b00): no changed. 3541 \li 0Xxxxxxx3- (b011----): Forced enable CL72 under AN. 3542 \li 0Xxxxxxx7- (b111----): Forced disable CL72 under AN. 3543 \li 0Xxxxxxx1- (b001----): Default CL72 under AN. 3544 \li 0Xxxxxxx0- (b000----): no changed 3545 \li 0Xxxxxx100 : read back CL72 HW en bit and put in accData. 3546 3547 */ 3548 int temod16_clause72_control(PHYMOD_ST* pc, cl72_type_t cl_72_type) /* CLAUSE_72_CONTROL */ 3549 { 3550 return PHYMOD_E_NONE; 3551 } /* clause72_control */ 3552 #endif /* _DV_TB_ */ 3553 3554 #ifdef _DV_TB_ 3555 3556 int temod16_prbs_check(PHYMOD_ST* pc, int real_check, int *prbs_status) 3557 { 3558 TLB_RX_PRBS_CHK_LOCK_STSr_t reg_prbs_chk_lock; 3559 TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr_t reg_prbs_err_cnt_msb; 3560 TLB_RX_PRBS_CHK_ERR_CNT_LSB_STSr_t reg_prbs_err_cnt_lsb; 3561 int lock, lock_lost, err ; 3562 3563 TMOD_DBG_IN_FUNC_INFO(pc); 3564 pc->accData = 0 ; 3565 3566 TLB_RX_PRBS_CHK_LOCK_STSr_CLR(reg_prbs_chk_lock); 3567 TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr_CLR(reg_prbs_err_cnt_msb); 3568 TLB_RX_PRBS_CHK_ERR_CNT_LSB_STSr_CLR(reg_prbs_err_cnt_lsb); 3569 3570 PHYMOD_IF_ERR_RETURN 3571 ( READ_TLB_RX_PRBS_CHK_LOCK_STSr(pc, ®_prbs_chk_lock)); 3572 PHYMOD_IF_ERR_RETURN 3573 (READ_TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr(pc, ®_prbs_err_cnt_msb)); 3574 PHYMOD_IF_ERR_RETURN 3575 (READ_TLB_RX_PRBS_CHK_ERR_CNT_LSB_STSr(pc, ®_prbs_err_cnt_lsb)); 3576 3577 lock = TLB_RX_PRBS_CHK_LOCK_STSr_PRBS_CHK_LOCKf_GET(reg_prbs_chk_lock) ? 1 : 0 ; 3578 lock_lost = TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr_PRBS_CHK_LOCK_LOST_LHf_GET(reg_prbs_err_cnt_msb) ? 1 : 0 ; 3579 err = TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr_PRBS_CHK_ERR_CNT_MSBf_GET(reg_prbs_err_cnt_msb) ; 3580 err = (err << 16) | TLB_RX_PRBS_CHK_ERR_CNT_LSB_STSr_PRBS_CHK_ERR_CNT_LSBf_GET(reg_prbs_err_cnt_lsb) ; 3581 3582 #ifdef _DV_TB_ 3583 printf("prbs_check u=%0d p=%0d ln=%0d lck=%0d lost=%0d err=%0d(H%x L%x)\n", 3584 pc->unit, pc->port, pc->this_lane, lock, lock_lost, err, reg_prbs_err_cnt_msb, reg_prbs_err_cnt_lsb); 3585 #endif 3586 3587 if (TLB_RX_PRBS_CHK_LOCK_STSr_PRBS_CHK_LOCKf_GET(reg_prbs_chk_lock)) { 3588 if (TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr_PRBS_CHK_LOCK_LOST_LHf_GET(reg_prbs_err_cnt_msb)) { 3589 /* locked now but lost before */ 3590 *prbs_status = TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr_PRBS_CHK_ERR_CNT_MSBf_GET(reg_prbs_err_cnt_msb); 3591 *prbs_status = (*prbs_status << 16) | TLB_RX_PRBS_CHK_ERR_CNT_LSB_STSr_PRBS_CHK_ERR_CNT_LSBf_GET(reg_prbs_err_cnt_lsb) | 1 ; /* locked once, so one error at least */ 3592 pc->accData = real_check ? 1 : 0 ; 3593 return PHYMOD_E_FAIL; 3594 } else { 3595 *prbs_status = TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr_PRBS_CHK_ERR_CNT_MSBf_GET(reg_prbs_err_cnt_msb) ; 3596 *prbs_status = (*prbs_status << 16)| TLB_RX_PRBS_CHK_ERR_CNT_LSB_STSr_PRBS_CHK_ERR_CNT_LSBf_GET(reg_prbs_err_cnt_lsb) ; 3597 if (err) { 3598 pc->accData = real_check ? 1 : 0 ; 3599 return PHYMOD_E_FAIL; 3600 } 3601 } 3602 } else { 3603 if (TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr_PRBS_CHK_LOCK_LOST_LHf_GET(reg_prbs_err_cnt_msb)) { 3604 *prbs_status = -2 ; /* locked before but lost now */ 3605 pc->accData = real_check ? 1 : 0 ; 3606 return PHYMOD_E_FAIL; 3607 } else { 3608 *prbs_status = -1 ; /* never locked */ 3609 pc->accData = real_check ? 1 : 0 ; 3610 return PHYMOD_E_FAIL; 3611 } 3612 } 3613 return PHYMOD_E_NONE ; 3614 } 3615 #endif /* _DV_TB_ */ 3616 3617 #ifdef _DV_TB_ 3618 3619 int temod16_prbs_mode(PHYMOD_ST* pc, int port, int prbs_inv, int pattern_type, int prbs_check_mode) /* PRBS_MODE */ 3620 { 3621 TLB_TX_PRBS_GEN_CFGr_t reg_prbs_gen_cfg; 3622 TLB_RX_PRBS_CHK_CFGr_t reg_prbs_chk_cfg; 3623 /* SC_X4_BYPASSr_t reg_bypass; */ 3624 3625 /*int prbs_check_mode ; */ 3626 int prbs_sel_tx, prbs_inv_tx ; 3627 int prbs_sel_rx, prbs_inv_rx ; 3628 3629 3630 TMOD_DBG_IN_FUNC_INFO(pc); 3631 TLB_TX_PRBS_GEN_CFGr_CLR(reg_prbs_gen_cfg); 3632 TLB_RX_PRBS_CHK_CFGr_CLR(reg_prbs_chk_cfg); 3633 3634 prbs_sel_tx = pattern_type; 3635 prbs_sel_rx = pattern_type; 3636 prbs_inv_tx = prbs_inv; 3637 prbs_inv_rx = prbs_inv; 3638 3639 TLB_TX_PRBS_GEN_CFGr_PRBS_GEN_MODE_SELf_SET(reg_prbs_gen_cfg, prbs_sel_tx); 3640 TLB_TX_PRBS_GEN_CFGr_PRBS_GEN_INVf_SET(reg_prbs_gen_cfg, prbs_inv_tx); 3641 3642 PHYMOD_IF_ERR_RETURN (MODIFY_TLB_TX_PRBS_GEN_CFGr(pc, reg_prbs_gen_cfg)); 3643 3644 TLB_RX_PRBS_CHK_CFGr_PRBS_CHK_MODEf_SET(reg_prbs_chk_cfg, prbs_check_mode); 3645 TLB_RX_PRBS_CHK_CFGr_PRBS_CHK_MODE_SELf_SET(reg_prbs_chk_cfg, prbs_sel_rx); 3646 TLB_RX_PRBS_CHK_CFGr_PRBS_CHK_INVf_SET(reg_prbs_chk_cfg, prbs_inv_rx); 3647 3648 PHYMOD_IF_ERR_RETURN (MODIFY_TLB_RX_PRBS_CHK_CFGr(pc, reg_prbs_chk_cfg)); 3649 3650 return PHYMOD_E_NONE; 3651 3652 } /* PRBS_MODE */ 3653 #endif /* _DV_TB_ */ 3654 3655 #ifdef _DV_TB_ 3656 3657 int temod16_prbs_control(PHYMOD_ST* pc, int prbs_enable) /* PRBS_CONTROL */ 3658 { 3659 TLB_TX_PRBS_GEN_CFGr_t reg_prbs_gen_cfg; 3660 TLB_RX_PRBS_CHK_CFGr_t reg_prbs_chk_cfg; 3661 int prbs_rx_en, prbs_tx_en ; 3662 3663 TMOD_DBG_IN_FUNC_INFO(pc); 3664 TLB_TX_PRBS_GEN_CFGr_CLR(reg_prbs_gen_cfg); 3665 TLB_RX_PRBS_CHK_CFGr_CLR(reg_prbs_chk_cfg); 3666 3667 prbs_tx_en = prbs_enable; 3668 prbs_rx_en = prbs_enable; 3669 3670 TLB_TX_PRBS_GEN_CFGr_PRBS_GEN_ENf_SET(reg_prbs_gen_cfg, prbs_tx_en); 3671 PHYMOD_IF_ERR_RETURN (MODIFY_TLB_TX_PRBS_GEN_CFGr(pc, reg_prbs_gen_cfg)); 3672 3673 TLB_RX_PRBS_CHK_CFGr_PRBS_CHK_ENf_SET(reg_prbs_chk_cfg, prbs_rx_en); 3674 PHYMOD_IF_ERR_RETURN (MODIFY_TLB_RX_PRBS_CHK_CFGr(pc, reg_prbs_chk_cfg)); 3675 3676 return PHYMOD_E_NONE; 3677 3678 } /* PRBS_CONTROL */ 3679 #endif /* _DV_TB_ */ 3680 3681 /** 3682 @brief Sets CJPAT/CRPAT parameters for a particular port 3683 @param pc handle to current TSCE context (#PHYMOD_ST) 3684 @param port handle to current TSCE context (#PHYMOD_ST) 3685 @param pattern_type type of CJPat 3686 @param pkt_number number of packets 3687 @param pkt_size size of packets 3688 @param ipg_size IPG between packets 3689 @returns The value PHYMOD_E_NONE upon successful completion 3690 3691 This function enables either a CJPAT or CRPAT for a particular port. 3692 The speed mode of the lane must be chosen from the enumerated type 3693 #temod16_spd_intfc_type and set in the 3694 #PHYMOD_ST::spd_intf field. To enable CJPAT, set #PHYMOD_ST::per_lane_control to 3695 the value #USE_CJPAT; to enable CRPAT, set #PHYMOD_ST::per_lane_control to the 3696 value #USE_CRPAT. This function is used in tandem with temod16_cjpat_crpat_check(). 3697 3698 */ 3699 3700 int temod16_cjpat_crpat_mode_set(PHYMOD_ST* pc, temod16_spd_intfc_type spd_intf, int port, int pattern_type, int pkt_number, int pkt_size, int ipg_size) /* CJPAT_CRPAT_MODE_SET */ 3701 { 3702 int number_pkt, crc_check, intf_type, rx_port_sel, tx_port_sel, pkt_or_prtp ; 3703 int pkt_size_int, ipg_size_int, payload_type, prtp_data_pattern_sel, rx_prtp_en ; 3704 int tx_prtp_en; 3705 uint16_t data16 ; 3706 3707 int rand_num; 3708 3709 PKTGEN_CTL1r_t reg_pktctrl1; 3710 PKTGEN_CTL2r_t reg_pktctrl2; 3711 PKTGEN_PRTPCTLr_t reg_prtpctrl; 3712 PKTGEN_PCS_SEEDA0r_t reg_seeda0; 3713 PKTGEN_PCS_SEEDA1r_t reg_seeda1; 3714 PKTGEN_PCS_SEEDA2r_t reg_seeda2; 3715 PKTGEN_PCS_SEEDA3r_t reg_seeda3; 3716 PKTGEN_PCS_SEEDB0r_t reg_seedb0; 3717 PKTGEN_PCS_SEEDB1r_t reg_seedb1; 3718 PKTGEN_PCS_SEEDB2r_t reg_seedb2; 3719 PKTGEN_PCS_SEEDB3r_t reg_seedb3; 3720 PKTGEN_PAYLOADBYTESr_t reg_payload_b; 3721 3722 TMOD_DBG_IN_FUNC_INFO(pc); 3723 PKTGEN_CTL1r_CLR(reg_pktctrl1); 3724 PKTGEN_CTL2r_CLR(reg_pktctrl2); 3725 PKTGEN_PRTPCTLr_CLR(reg_prtpctrl); 3726 PKTGEN_PCS_SEEDA0r_CLR(reg_seeda0); 3727 PKTGEN_PCS_SEEDA1r_CLR(reg_seeda1); 3728 PKTGEN_PCS_SEEDA2r_CLR(reg_seeda2); 3729 PKTGEN_PCS_SEEDA3r_CLR(reg_seeda3); 3730 PKTGEN_PCS_SEEDB0r_CLR(reg_seedb0); 3731 PKTGEN_PCS_SEEDB1r_CLR(reg_seedb1); 3732 PKTGEN_PCS_SEEDB2r_CLR(reg_seedb2); 3733 PKTGEN_PCS_SEEDB3r_CLR(reg_seedb3); 3734 PKTGEN_PAYLOADBYTESr_CLR(reg_payload_b); 3735 3736 number_pkt = pkt_number ; /* 2: unlimited, 0: idles, 1: single pkt */ 3737 crc_check = 1 ; 3738 rx_port_sel= port ; 3739 tx_port_sel= port ; 3740 pkt_or_prtp = 0 ; /* 0: pakcet generator; 1: PRTP(pseudo random test pattern) */ 3741 rx_prtp_en = 0; 3742 tx_prtp_en = 0; 3743 if ((pattern_type == 0x9) | (pattern_type == 0xA)) { 3744 pkt_or_prtp = 1; 3745 rx_prtp_en = 1; 3746 tx_prtp_en = 1; 3747 } 3748 3749 if (pattern_type == 0xA) { 3750 prtp_data_pattern_sel = 1; 3751 } else { 3752 prtp_data_pattern_sel = 0; 3753 } 3754 3755 /* pkt_size_int = pkt_size ; */ 3756 pkt_size_int = 1; 3757 ipg_size_int = 8 ; 3758 /* ipg_size_int = ipg_size ; */ 3759 3760 /* need to check the interface type */ 3761 if ((pattern_type == 0x9) | (pattern_type == 0xA)) { 3762 payload_type = 0; 3763 } else { 3764 payload_type = pattern_type; 3765 } 3766 3767 3768 /* intf_type 0: XLGMII/XGMII; 1: MIII/GMII */ 3769 3770 intf_type = ((spd_intf == TEMOD16_SPD_10_X1_SGMII) | 3771 (spd_intf == TEMOD16_SPD_100_X1_SGMII) | 3772 (spd_intf == TEMOD16_SPD_1000_X1_SGMII) | 3773 (spd_intf == TEMOD16_SPD_10_SGMII) | 3774 (spd_intf == TEMOD16_SPD_100_SGMII) | 3775 (spd_intf == TEMOD16_SPD_1000_SGMII) | 3776 (spd_intf == TEMOD16_SPD_2500) | 3777 (spd_intf == TEMOD16_SPD_2500_X1)) ? 1 : 0; 3778 3779 /* if payload type is Repeat 2 Bytes in 0x9040*/ 3780 3781 if (payload_type == 0) { 3782 data16 = 0x2323; 3783 PKTGEN_PAYLOADBYTESr_BYTE1f_SET(reg_payload_b, ((data16 >> 8) & 0xff)); 3784 PKTGEN_PAYLOADBYTESr_BYTE0f_SET(reg_payload_b, (data16 & 0xff)); 3785 WRITE_PKTGEN_PAYLOADBYTESr(pc, reg_payload_b); 3786 } 3787 3788 /* 0x9030 */ 3789 PKTGEN_CTL1r_PKT_OR_PRTPf_SET(reg_pktctrl1, pkt_or_prtp); 3790 PKTGEN_CTL1r_TX_TEST_PORT_SELf_SET(reg_pktctrl1, tx_port_sel); 3791 PKTGEN_CTL1r_RX_PORT_SELf_SET(reg_pktctrl1, rx_port_sel); 3792 PKTGEN_CTL1r_RX_PKT_CHECK_ENf_SET(reg_pktctrl1, crc_check); 3793 PKTGEN_CTL1r_RX_MSBUS_TYPEf_SET(reg_pktctrl1, intf_type); 3794 PKTGEN_CTL1r_NUMBER_PKTf_SET(reg_pktctrl1, number_pkt); 3795 PKTGEN_CTL1r_TX_PRTP_ENf_SET(reg_pktctrl1, tx_prtp_en); 3796 PKTGEN_CTL1r_PRTP_DATA_PATTERN_SELf_SET(reg_pktctrl1, prtp_data_pattern_sel); 3797 3798 PHYMOD_IF_ERR_RETURN 3799 (WRITE_PKTGEN_CTL1r(pc, reg_pktctrl1)); 3800 3801 /* 0x9031 */ 3802 PKTGEN_CTL2r_IPG_SIZEf_SET(reg_pktctrl2, ipg_size_int); 3803 PKTGEN_CTL2r_PKT_SIZEf_SET(reg_pktctrl2, pkt_size_int); 3804 PKTGEN_CTL2r_PAYLOAD_TYPEf_SET(reg_pktctrl2, payload_type); 3805 PKTGEN_CTL2r_TX_MSBUS_TYPEf_SET(reg_pktctrl2, intf_type); 3806 3807 PHYMOD_IF_ERR_RETURN 3808 (WRITE_PKTGEN_CTL2r(pc, reg_pktctrl2)); 3809 3810 /* 0x9032 */ 3811 PKTGEN_PRTPCTLr_RX_PRTP_ENf_SET(reg_prtpctrl,rx_prtp_en); 3812 PHYMOD_IF_ERR_RETURN 3813 (WRITE_PKTGEN_PRTPCTLr(pc, reg_prtpctrl)); 3814 3815 /* program seeds if necessary */ 3816 rand_num = 1234; 3817 #ifdef _DV_TB_ 3818 rand_num = rand (); 3819 #endif 3820 3821 data16 = rand_num & 0xFFFF; 3822 if ((pattern_type == 0x9) | (pattern_type == 0xA)) { 3823 PKTGEN_PCS_SEEDA0r_SEEDA0f_SET(reg_seeda0, data16); 3824 PHYMOD_IF_ERR_RETURN 3825 (WRITE_PKTGEN_PCS_SEEDA0r(pc, reg_seeda0)); 3826 data16 = data16 + 1; 3827 PKTGEN_PCS_SEEDA1r_SEEDA1f_SET(reg_seeda1, data16); 3828 PHYMOD_IF_ERR_RETURN 3829 (WRITE_PKTGEN_PCS_SEEDA1r(pc, reg_seeda1)); 3830 data16 = data16 + 1; 3831 PKTGEN_PCS_SEEDA2r_SEEDA2f_SET(reg_seeda2, data16); 3832 PHYMOD_IF_ERR_RETURN 3833 (WRITE_PKTGEN_PCS_SEEDA2r( pc, reg_seeda2)); 3834 data16 = data16 + 1; 3835 PKTGEN_PCS_SEEDA3r_SEEDA3f_SET(reg_seeda3, data16); 3836 PHYMOD_IF_ERR_RETURN 3837 (WRITE_PKTGEN_PCS_SEEDA3r(pc, reg_seeda3)); 3838 data16 = data16 + 1; 3839 PKTGEN_PCS_SEEDB0r_SEEDB0f_SET(reg_seedb0, data16); 3840 PHYMOD_IF_ERR_RETURN 3841 (WRITE_PKTGEN_PCS_SEEDB0r( pc, reg_seedb0)); 3842 data16 = data16 + 1; 3843 PKTGEN_PCS_SEEDB1r_SEEDB1f_SET(reg_seedb1, data16); 3844 PHYMOD_IF_ERR_RETURN 3845 (WRITE_PKTGEN_PCS_SEEDB1r( pc, reg_seedb1)); 3846 data16 = data16 + 1; 3847 PKTGEN_PCS_SEEDB2r_SEEDB2f_SET(reg_seedb2, data16); 3848 PHYMOD_IF_ERR_RETURN 3849 (WRITE_PKTGEN_PCS_SEEDB2r(pc, reg_seedb2)); 3850 data16 = data16 + 1; 3851 PKTGEN_PCS_SEEDB3r_SEEDB3f_SET(reg_seedb3, data16); 3852 PHYMOD_IF_ERR_RETURN 3853 (WRITE_PKTGEN_PCS_SEEDB3r( pc, reg_seedb3)); 3854 } 3855 return PHYMOD_E_NONE; 3856 } /* int temod16_cjpat_crpat_mode_set */ 3857 3858 /** 3859 @brief Checks CJPAT/CRPAT parameters for a particular port 3860 @param pc handle to current TSCE context (#PHYMOD_ST) 3861 @returns The value PHYMOD_E_NONE upon successful completion 3862 3863 This function checks for CJPAT or CRPAT for a particular port. The speed mode 3864 of the lane must be chosen from the enumerated type #temod16_spd_intfc_type and 3865 set in the #PHYMOD_ST::spd_intf field. CJPAT/CRPAT must first enabled using 3866 #temod16_cjpat_crpat_control(). The duration of packet transmission is controlled 3867 externally and is the time duration between the two function calls above. 3868 3869 This function compares the CJPAT/CRPAT TX and RX counters and prints the 3870 results. Currently only packet count is supported. 3871 3872 This function reads the following registers: 3873 3874 \li PATGEN1_TXPKTCNT_U (0xC040) Upper 16b of count of Transmitted packets 3875 \li PATGEN1_TXPKTCNT_L (0xC041) Lower 16b of count of Transmitted packets 3876 \li PATGEN1_RXPKTCNT_U (0xC042) Upper 16b of count of Recieved packets 3877 \li PATGEN1_RXPKTCNT_L (0xC043) Lower 16b of count of Recieved packets 3878 \li PKTGEN0_CRCERRORCOUNT (0x9033) CRC error conunt 3879 3880 */ 3881 3882 int temod16_cjpat_crpat_check(PHYMOD_ST* pc) /* CJPAT_CRPAT_CHECK */ 3883 { 3884 uint32_t tx_cnt, rx_cnt ; 3885 3886 TXPKTCNT_Ur_t reg_tx_u; 3887 TXPKTCNT_Lr_t reg_tx_l; 3888 RXPKTCNT_Ur_t reg_rx_u; 3889 RXPKTCNT_Lr_t reg_rx_l; 3890 PKTGEN_CRCERRCNTr_t reg_crc_cnt; 3891 3892 TMOD_DBG_IN_FUNC_INFO(pc); 3893 TXPKTCNT_Ur_CLR(reg_tx_u); 3894 READ_TXPKTCNT_Ur(pc, ®_tx_u); 3895 TXPKTCNT_Lr_CLR(reg_tx_l); 3896 READ_TXPKTCNT_Lr(pc, ®_tx_l); 3897 RXPKTCNT_Ur_CLR(reg_rx_u); 3898 READ_RXPKTCNT_Ur(pc, ®_rx_u); 3899 RXPKTCNT_Lr_CLR(reg_rx_l); 3900 READ_RXPKTCNT_Lr(pc, ®_rx_l); 3901 PKTGEN_CRCERRCNTr_CLR(reg_crc_cnt); 3902 READ_PKTGEN_CRCERRCNTr(pc, ®_crc_cnt); 3903 3904 tx_cnt = TXPKTCNT_Ur_GET(reg_tx_u) <<16; 3905 tx_cnt |= TXPKTCNT_Lr_GET(reg_tx_l); 3906 3907 rx_cnt = RXPKTCNT_Ur_GET(reg_rx_u) <<16; 3908 rx_cnt |= RXPKTCNT_Lr_GET(reg_rx_l); 3909 3910 #ifdef _DV_TB_ 3911 pc->accData = 1 ; 3912 #endif /* _DV_TB_ */ 3913 if ( (tx_cnt != rx_cnt) ||(tx_cnt==0) ) { 3914 #ifdef _DV_TB_ 3915 3916 PHYMOD_DEBUG_ERROR(("%-22s ERROR: u=%0d p=%0d tx_cnt=%0d rx_cnt=%0d mismatch\n", __func__, pc->unit, pc->port, tx_cnt, rx_cnt)); 3917 pc->accData = 0; 3918 #endif /* _DV_TB_ */ 3919 return PHYMOD_E_FAIL; 3920 } 3921 3922 if (reg_crc_cnt.pktgen_crcerrcnt[0]) { 3923 #ifdef _DV_TB_ 3924 3925 PHYMOD_DEBUG_ERROR(("%-22s ERROR: u=%0d p=%0d crc error=%0d\n", __func__, pc->unit, pc->port, reg_crc_cnt.pktgen_crcerrcnt[0])); 3926 pc->accData = 0; 3927 #endif /* _DV_TB_ */ 3928 3929 return PHYMOD_E_FAIL; 3930 } 3931 return PHYMOD_E_NONE; 3932 } 3933 3934 3935 int temod16_cjpat_crpat_control(PHYMOD_ST* pc, int enable) /* CJPAT_CRPAT_CONTROL */ 3936 { 3937 PKTGEN_CTL2r_t reg; 3938 3939 TMOD_DBG_IN_FUNC_INFO(pc); 3940 PKTGEN_CTL2r_CLR(reg); 3941 /* 0x9031 */ 3942 PHYMOD_IF_ERR_RETURN 3943 (READ_PKTGEN_CTL2r(pc, ®)); 3944 3945 if (enable) { 3946 PKTGEN_CTL2r_PKTGEN_ENf_SET(reg, 1); 3947 } else { 3948 PKTGEN_CTL2r_PKTGEN_ENf_SET(reg, 0); 3949 } 3950 PHYMOD_IF_ERR_RETURN 3951 (WRITE_PKTGEN_CTL2r(pc, reg)); 3952 3953 return PHYMOD_E_NONE; 3954 } 3955 3956 3957 int temod16_pcs_lane_swap(PHYMOD_ST *pc, int lane_map) 3958 { 3959 unsigned int tx_lane_map_0, tx_lane_map_1, tx_lane_map_2, tx_lane_map_3; 3960 unsigned int rx_lane_map_0, rx_lane_map_1, rx_lane_map_2, rx_lane_map_3; 3961 MAIN0_LN_SWPr_t reg; 3962 TMOD_DBG_IN_FUNC_INFO(pc); 3963 /* lane_map = lane_map >> 16;*/ 3964 3965 MAIN0_LN_SWPr_CLR(reg); 3966 3967 tx_lane_map_0 = (((lane_map >> 0) & 0x3) ); 3968 tx_lane_map_1 = (((lane_map >> 4) & 0x3) ); 3969 tx_lane_map_2 = (((lane_map >> 8) & 0x3) ); 3970 tx_lane_map_3 = (((lane_map >> 12) & 0x3) ); 3971 3972 rx_lane_map_0 = (((lane_map >> 16) & 0x3) ); 3973 rx_lane_map_1 = (((lane_map >> 20) & 0x3) ); 3974 rx_lane_map_2 = (((lane_map >> 24) & 0x3) ); 3975 rx_lane_map_3 = (((lane_map >> 28) & 0x3) ); 3976 3977 MAIN0_LN_SWPr_LOG0_TO_PHY_TX_LNSWAP_SELf_SET(reg, tx_lane_map_0); 3978 MAIN0_LN_SWPr_LOG1_TO_PHY_TX_LNSWAP_SELf_SET(reg, tx_lane_map_1); 3979 MAIN0_LN_SWPr_LOG2_TO_PHY_TX_LNSWAP_SELf_SET(reg, tx_lane_map_2); 3980 MAIN0_LN_SWPr_LOG3_TO_PHY_TX_LNSWAP_SELf_SET(reg, tx_lane_map_3); 3981 3982 MAIN0_LN_SWPr_LOG0_TO_PHY_RX_LNSWAP_SELf_SET(reg, rx_lane_map_0); 3983 MAIN0_LN_SWPr_LOG1_TO_PHY_RX_LNSWAP_SELf_SET(reg, rx_lane_map_1); 3984 MAIN0_LN_SWPr_LOG2_TO_PHY_RX_LNSWAP_SELf_SET(reg, rx_lane_map_2); 3985 MAIN0_LN_SWPr_LOG3_TO_PHY_RX_LNSWAP_SELf_SET(reg, rx_lane_map_3); 3986 3987 PHYMOD_IF_ERR_RETURN 3988 (WRITE_MAIN0_LN_SWPr(pc, reg)) ; 3989 3990 return PHYMOD_E_NONE ; 3991 } 3992 3993 #ifdef _DV_TB_ 3994 /** 3995 @brief sets PMD TX lane swap values for all lanes simultaneously. 3996 @param pc handle to current TSCE context (#PHYMOD_ST) 3997 @returns The value PHYMOD_E_NONE upon successful completion 3998 3999 This function sets the TX lane swap values for all lanes simultaneously. 4000 4001 The TSCE has several two sets of lane swap registers per lane. This function 4002 uses the lane swap registers closest to the pads. For TX, the lane swap occurs 4003 after all other analog/digital functionality. For RX, the lane swap occurs 4004 prior to all other analog/digital functionality. 4005 4006 It is not advisable to swap lanes without going through reset. 4007 4008 How the swap is done is indicated in the #PHYMOD_ST::per_lane_control field; 4009 bits 0 through 15 represent the swap settings for RX while bits 16 4010 through 31 represent the swap settings for TX. 4011 4012 Each 4 bit chunk within both the RX and TX sections represent the swap settings 4013 for a particular lane as follows: 4014 4015 Bits lane assignment 4016 4017 \li 15:12 TX lane 3 4018 \li 11:8 TX lane 2 4019 \li 7:4 TX lane 1 4020 \li 3:0 TX lane 0 4021 4022 Each 4-bit value may be either 0, 1, 2 or 3, with the value indicating the lane 4023 mapping. By default, the equivalent per_lane_control settings are 0x3210_3210, 4024 indicating that there is no re-routing of traffic. As an example, to swap lanes 4025 0 and 1 for both RX and TX, the per_lane_control should be set to 0x3201_3201. 4026 To swap lanes 0 and 1, and also lanes 2 and 3 for both RX and TX, the 4027 per_lane_control should be set to 0x2301_2301. 4028 4029 */ 4030 int temod16_pmd_lane_swap(PHYMOD_ST *pc) 4031 { 4032 LN_ADDR0r_t reg_adr0; 4033 LN_ADDR1r_t reg_adr1; 4034 LN_ADDR2r_t reg_adr2; 4035 LN_ADDR3r_t reg_adr3; 4036 4037 unsigned int map; 4038 unsigned int rx_lane_addr_0, rx_lane_addr_1, rx_lane_addr_2, rx_lane_addr_3; 4039 unsigned int tx_lane_addr_0, tx_lane_addr_1, tx_lane_addr_2, tx_lane_addr_3; 4040 4041 TMOD_DBG_IN_FUNC_INFO(pc); 4042 LN_ADDR0r_CLR(reg_adr0); 4043 LN_ADDR1r_CLR(reg_adr1); 4044 LN_ADDR2r_CLR(reg_adr2); 4045 LN_ADDR3r_CLR(reg_adr3); 4046 4047 map = (unsigned int)pc->per_lane_control; 4048 4049 tx_lane_addr_0 = (map >> 0) & 0xf; 4050 tx_lane_addr_1 = (map >> 4) & 0xf; 4051 tx_lane_addr_2 = (map >> 8) & 0xf; 4052 tx_lane_addr_3 = (map >> 12) & 0xf; 4053 rx_lane_addr_0 = (map >> 16) & 0xf; 4054 rx_lane_addr_1 = (map >> 20) & 0xf; 4055 rx_lane_addr_2 = (map >> 24) & 0xf; 4056 rx_lane_addr_3 = (map >> 28) & 0xf; 4057 4058 #ifdef _DV_TB_ 4059 pc->adjust_port_mode = 1; 4060 #endif 4061 #ifdef _SDK_TEMOD16_ 4062 4063 #endif 4064 4065 LN_ADDR0r_TX_LANE_ADDR_0f_SET(reg_adr0, tx_lane_addr_0); 4066 LN_ADDR0r_RX_LANE_ADDR_0f_SET(reg_adr0, rx_lane_addr_0); 4067 PHYMOD_IF_ERR_RETURN 4068 (MODIFY_LN_ADDR0r(pc, reg_adr0)); 4069 4070 LN_ADDR1r_TX_LANE_ADDR_1f_SET(reg_adr1, tx_lane_addr_1); 4071 LN_ADDR1r_RX_LANE_ADDR_1f_SET(reg_adr1, rx_lane_addr_1); 4072 PHYMOD_IF_ERR_RETURN 4073 (MODIFY_LN_ADDR1r(pc, reg_adr1)); 4074 4075 LN_ADDR2r_TX_LANE_ADDR_2f_SET(reg_adr2, tx_lane_addr_2); 4076 LN_ADDR2r_RX_LANE_ADDR_2f_SET(reg_adr2, rx_lane_addr_2); 4077 PHYMOD_IF_ERR_RETURN 4078 (MODIFY_LN_ADDR2r(pc, reg_adr2)); 4079 4080 LN_ADDR3r_TX_LANE_ADDR_3f_SET(reg_adr3, tx_lane_addr_3); 4081 LN_ADDR3r_RX_LANE_ADDR_3f_SET(reg_adr3, rx_lane_addr_3); 4082 PHYMOD_IF_ERR_RETURN 4083 (MODIFY_LN_ADDR3r(pc, reg_adr3)); 4084 4085 4086 #ifdef _DV_TB_ 4087 pc->adjust_port_mode = 0; 4088 #endif 4089 #ifdef _SDK_TEMOD16_ 4090 4091 #endif 4092 4093 return PHYMOD_E_NONE ; 4094 } 4095 #endif /* _DV_TB_ */ 4096 4097 /** 4098 @brief sets PMD TX lane swap values for all lanes simultaneously. 4099 @param pc handle to current TSCE context (#PHYMOD_ST) 4100 @returns The value PHYMOD_E_NONE upon successful completion 4101 4102 This function sets the TX lane swap values for all lanes simultaneously. 4103 4104 The TSCE has several two sets of lane swap registers per lane. This function uses the 4105 lane swap registers closest to the pads. For TX, the lane swap occurs after all other 4106 analog/digital functionality. For RX, the lane swap occurs prior to all other 4107 analog/digital functionality. 4108 4109 It is not advisable to swap lanes without going through reset. 4110 4111 How the swap is done is indicated in the #PHYMOD_ST::per_lane_control field; 4112 bits 0 through 15 represent the swap settings for RX while bits 16 4113 through 31 represent the swap settings for TX. 4114 4115 Each 4 bit chunk within both the RX and TX sections represent the swap settings 4116 for a particular lane as follows: 4117 4118 Bits lane assignment 4119 4120 \li 15:12 TX lane 3 4121 \li 11:8 TX lane 2 4122 \li 7:4 TX lane 1 4123 \li 3:0 TX lane 0 4124 4125 Each 4-bit value may be either 0, 1, 2 or 3, with the value indicating the lane 4126 mapping. By default, the equivalent per_lane_control settings are 0x3210_3210, 4127 indicating that there is no re-routing of traffic. As an example, to swap lanes 4128 0 and 1 for both RX and TX, the per_lane_control should be set to 0x3201_3201. 4129 To swap lanes 0 and 1, and also lanes 2 and 3 for both RX and TX, the 4130 per_lane_control should be set to 0x2301_2301. 4131 4132 */ 4133 int temod16_pmd_lane_swap_tx(PHYMOD_ST *pc, uint32_t tx_lane_map_0, uint32_t tx_lane_map_1, uint32_t tx_lane_map_2, uint32_t tx_lane_map_3) 4134 { 4135 return PHYMOD_E_NONE ; 4136 } 4137 4138 /** 4139 @brief is used to power down transmitter or receiver per lane basis. 4140 @param pc handle to current TSCE context (a.k.a #PHYMOD_ST) 4141 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 4142 @details 4143 4144 This function is used to power on/off the TX and RX lanes in one swoop. To 4145 change the power down state for TX or RX, bit-wise OR one of the following 4146 4147 \li CHANGE_TX0_PWRED_STATE 0x10 4148 \li CHANGE_TX1_PWRED_STATE 0x20 4149 \li CHANGE_TX2_PWRED_STATE 0x40 4150 \li CHANGE_TX3_PWRED_STATE 0x80 4151 4152 <br> 4153 4154 \li CHANGE_RX0_PWRED_STATE 0x1000 4155 \li CHANGE_RX1_PWRED_STATE 0x2000 4156 \li CHANGE_RX2_PWRED_STATE 0x4000 4157 \li CHANGE_RX3_PWRED_STATE 0x8000 4158 4159 into #PHYMOD_ST::per_lane_control. These values serve as masks for whether the 4160 power on/off for a particular lane should be changed. 4161 4162 To turn off the power for the selected TX/RX lane, bit-wise OR one of these 4163 4164 \li PWR_DOWN_TX0 0x1 4165 \li PWR_DOWN_TX1 0x2 4166 \li PWR_DOWN_TX2 0x4 4167 \li PWR_DOWN_TX3 0x8 4168 4169 <br> 4170 4171 \li PWR_DOWN_RX0 0x100 4172 \li PWR_DOWN_RX1 0x200 4173 \li PWR_DOWN_RX2 0x400 4174 \li PWR_DOWN_RX3 0x800 4175 4176 into #PHYMOD_ST::per_lane_control. 4177 4178 As an example, to turn off the TX power on lane 0, turn on the TX power on lane1, 4179 leave the RX power states along with the TX power on lanes 2 and 3 unaffected, set 4180 4181 #PHYMOD_ST::per_lane_control = CHANGE_TX0_PWRED_STATE | 4182 PWR_DOWN_TX0 | 4183 CHANGE_TX1_PWRED_STATE; 4184 */ 4185 int temod16_power_control(PHYMOD_ST* pc) 4186 { 4187 TMOD_DBG_IN_FUNC_INFO(pc); 4188 /* To be implemented */ 4189 return PHYMOD_E_NONE; 4190 } 4191 4192 #ifdef _DV_TB_ 4193 /** 4194 @brief Read the 16 bit rev. id value etc. 4195 @param pc handle to current TSCE context (#PHYMOD_ST) 4196 @returns The value PHYMOD_E_NONE upon successful 4197 @details PCS Init calls this Per Port PCS Init routine 4198 */ 4199 int _temod16_set_port_mode_select(PHYMOD_ST* pc) 4200 { 4201 4202 int port_mode_sel ; 4203 uint16_t single_port_mode; 4204 MAIN0_SETUPr_t reg ; 4205 4206 MAIN0_SETUPr_CLR(reg); 4207 port_mode_sel = 0 ; 4208 if (pc->tsc_touched == 1) { 4209 single_port_mode = 0 ; 4210 MAIN0_SETUPr_CLR(reg); 4211 } else { 4212 MAIN0_SETUPr_MASTER_PORT_NUMf_SET(reg, pc->master_portnum); 4213 MAIN0_SETUPr_PLL_RESET_ENf_SET(reg, 1); 4214 } 4215 4216 switch (pc->port_type) { 4217 case TEMOD16_MULTI_PORT: port_mode_sel = 0; break ; 4218 case TEMOD16_TRI1_PORT: port_mode_sel = 1; break ; 4219 case TEMOD16_TRI2_PORT: port_mode_sel = 2; break ; 4220 case TEMOD16_DXGXS: port_mode_sel = 3; break ; 4221 case TEMOD16_SINGLE_PORT: port_mode_sel = 4; break ; 4222 default: break ; 4223 } 4224 4225 if ((pc->sc_mode == TEMOD16_SC_MODE_AN_CL37) || (pc->sc_mode == TEMOD16_SC_MODE_AN_CL73)) { 4226 /*data = port_mode_sel << MAIN0_SETUP_PORT_MODE_SEL_SHIFT |*/ 4227 MAIN0_SETUPr_SINGLE_PORT_MODEf_SET(reg, pc->single_port_mode); 4228 MAIN0_SETUPr_AN_HIGH_VCOf_SET(reg, pc->cl37_high_vco); 4229 MAIN0_SETUPr_CL73_LOW_VCOf_SET(reg, pc->cl73_low_vco); 4230 MAIN0_SETUPr_REFCLK_SELf_SET(reg, pc->refclk); 4231 4232 PHYMOD_IF_ERR_RETURN (MODIFY_MAIN0_SETUPr(pc, reg)); 4233 } else { 4234 MAIN0_SETUPr_SINGLE_PORT_MODEf_SET(reg, pc->single_port_mode); 4235 MAIN0_SETUPr_AN_HIGH_VCOf_SET(reg, pc->cl37_high_vco); 4236 MAIN0_SETUPr_CL73_LOW_VCOf_SET(reg, pc->cl73_low_vco); 4237 MAIN0_SETUPr_REFCLK_SELf_SET(reg, pc->refclk); 4238 MAIN0_SETUPr_PORT_MODE_SELf_SET(reg, port_mode_sel); 4239 4240 PHYMOD_IF_ERR_RETURN (MODIFY_MAIN0_SETUPr(pc, reg)); 4241 } 4242 return PHYMOD_E_NONE; 4243 } 4244 #endif 4245 4246 #ifdef _DV_TB_ 4247 /** 4248 @brief Read the 16 bit rev. id value etc. 4249 @param pc handle to current TSCE context (#PHYMOD_ST) 4250 @returns The value PHYMOD_E_NONE upon successful completion 4251 @details Per Port PCS Init 4252 4253 */ 4254 /* TBD PARAMETERIZE CODE for SDK*/ 4255 int _configure_st_entry(int st_entry_num, int st_entry_speed, PHYMOD_ST* pc) 4256 { 4257 SC_X1_SPD_OVRR0_SPDr_t reg0_ovr_spd; 4258 SC_X1_SPD_OVRR0_0r_t reg0_ovr; 4259 SC_X1_SPD_OVRR0_1r_t reg0_ovr1; 4260 SC_X1_SPD_OVRR0_2r_t reg0_ovr2; 4261 SC_X1_SPD_OVRR0_3r_t reg0_ovr3; 4262 SC_X1_SPD_OVRR0_4r_t reg0_ovr4; 4263 SC_X1_SPD_OVRR0_5r_t reg0_ovr5; 4264 SC_X1_SPD_OVRR0_6r_t reg0_ovr6; 4265 SC_X1_SPD_OVRR0_7r_t reg0_ovr7; 4266 SC_X1_SPD_OVRR0_8r_t reg0_ovr8; 4267 4268 SC_X1_SPD_OVRR1_SPDr_t reg1_ovr_spd; 4269 SC_X1_SPD_OVRR1_0r_t reg1_ovr; 4270 SC_X1_SPD_OVRR1_1r_t reg1_ovr1; 4271 SC_X1_SPD_OVRR1_2r_t reg1_ovr2; 4272 SC_X1_SPD_OVRR1_3r_t reg1_ovr3; 4273 SC_X1_SPD_OVRR1_4r_t reg1_ovr4; 4274 SC_X1_SPD_OVRR1_5r_t reg1_ovr5; 4275 SC_X1_SPD_OVRR1_6r_t reg1_ovr6; 4276 SC_X1_SPD_OVRR1_7r_t reg1_ovr7; 4277 SC_X1_SPD_OVRR1_8r_t reg1_ovr8; 4278 4279 SC_X1_SPD_OVRR2_SPDr_t reg2_ovr_spd; 4280 SC_X1_SPD_OVRR2_0r_t reg2_ovr; 4281 SC_X1_SPD_OVRR2_1r_t reg2_ovr1; 4282 SC_X1_SPD_OVRR2_2r_t reg2_ovr2; 4283 SC_X1_SPD_OVRR2_3r_t reg2_ovr3; 4284 SC_X1_SPD_OVRR2_4r_t reg2_ovr4; 4285 SC_X1_SPD_OVRR2_5r_t reg2_ovr5; 4286 SC_X1_SPD_OVRR2_6r_t reg2_ovr6; 4287 SC_X1_SPD_OVRR2_7r_t reg2_ovr7; 4288 SC_X1_SPD_OVRR2_8r_t reg2_ovr8; 4289 4290 SC_X1_SPD_OVRR3_SPDr_t reg3_ovr_spd; 4291 SC_X1_SPD_OVRR3_0r_t reg3_ovr; 4292 SC_X1_SPD_OVRR3_1r_t reg3_ovr1; 4293 SC_X1_SPD_OVRR3_2r_t reg3_ovr2; 4294 SC_X1_SPD_OVRR3_3r_t reg3_ovr3; 4295 SC_X1_SPD_OVRR3_4r_t reg3_ovr4; 4296 SC_X1_SPD_OVRR3_5r_t reg3_ovr5; 4297 SC_X1_SPD_OVRR3_6r_t reg3_ovr6; 4298 SC_X1_SPD_OVRR3_7r_t reg3_ovr7; 4299 SC_X1_SPD_OVRR3_8r_t reg3_ovr8; 4300 4301 if (st_entry_num == 0) { 4302 4303 SC_X1_SPD_OVRR0_SPDr_CLR(reg0_ovr_spd); 4304 SC_X1_SPD_OVRR0_SPDr_NUM_LANESf_SET(reg0_ovr_spd, pc->num_lanes); 4305 SC_X1_SPD_OVRR0_SPDr_SPEEDf_SET(reg0_ovr_spd, st_entry_speed); 4306 4307 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_SPDr(pc, reg0_ovr_spd)); 4308 4309 SC_X1_SPD_OVRR0_0r_CLR(reg0_ovr); 4310 SC_X1_SPD_OVRR0_1r_CLR(reg0_ovr1); 4311 SC_X1_SPD_OVRR0_2r_CLR(reg0_ovr2); 4312 SC_X1_SPD_OVRR0_3r_CLR(reg0_ovr3); 4313 SC_X1_SPD_OVRR0_4r_CLR(reg0_ovr4); 4314 SC_X1_SPD_OVRR0_5r_CLR(reg0_ovr5); 4315 SC_X1_SPD_OVRR0_6r_CLR(reg0_ovr6); 4316 SC_X1_SPD_OVRR0_7r_CLR(reg0_ovr7); 4317 SC_X1_SPD_OVRR0_8r_CLR(reg0_ovr8); 4318 4319 SC_X1_SPD_OVRR0_0r_ENCODEMODEf_SET(reg0_ovr, pc->t_encode_mode); 4320 SC_X1_SPD_OVRR0_0r_SCR_MODEf_SET(reg0_ovr, pc->t_scr_mode); 4321 SC_X1_SPD_OVRR0_0r_OS_MODEf_SET(reg0_ovr, pc->t_pma_os_mode); 4322 4323 4324 if (pc->cl72_en & 0x40000000) 4325 SC_X1_SPD_OVRR0_0r_CL72_ENABLEf_SET(reg0_ovr, pc->cl72_en) ; 4326 4327 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_0r(pc, reg0_ovr)); 4328 4329 SC_X1_SPD_OVRR0_1r_BRCM64B66_DESCRAMBLER_ENABLEf_SET(reg0_ovr1, pc->r_dec1_brcm64b66_descr); 4330 SC_X1_SPD_OVRR0_1r_CL36BYTEDELETEMOD16Ef_SET(reg0_ovr1, pc->r_desc2_byte_deletion); 4331 SC_X1_SPD_OVRR0_1r_DESC2_MODEf_SET(reg0_ovr1, pc->r_desc2_mode); 4332 SC_X1_SPD_OVRR0_1r_DESKEWMODEf_SET(reg0_ovr1, pc->r_deskew_mode); 4333 SC_X1_SPD_OVRR0_1r_DECODERMODEf_SET(reg0_ovr1, pc->r_dec1_mode); 4334 SC_X1_SPD_OVRR0_1r_DESCRAMBLERMODEf_SET(reg0_ovr1, pc->r_descr1_mode); 4335 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_1r(pc, reg0_ovr1)); 4336 4337 SC_X1_SPD_OVRR0_2r_CL36_ENf_SET(reg0_ovr2, pc->cl36_en); 4338 SC_X1_SPD_OVRR0_2r_REORDER_ENf_SET(reg0_ovr2, pc->r_reorder_mode); 4339 SC_X1_SPD_OVRR0_2r_BLOCK_SYNC_MODEf_SET(reg0_ovr2, pc->blk_sync_mode); 4340 SC_X1_SPD_OVRR0_2r_CHK_END_ENf_SET(reg0_ovr2, pc->cl48_check_end); 4341 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_2r(pc, reg0_ovr2)); 4342 4343 SC_X1_SPD_OVRR0_3r_CLOCKCNT0f_SET(reg0_ovr3, pc->clkcnt0); 4344 SC_X1_SPD_OVRR0_3r_SGMII_SPD_SWITCHf_SET(reg0_ovr3, pc->sgmii); 4345 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_3r(pc, reg0_ovr3)); 4346 4347 SC_X1_SPD_OVRR0_4r_CLOCKCNT1f_SET(reg0_ovr4, pc->clkcnt1); 4348 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_4r(pc, reg0_ovr4)); 4349 4350 SC_X1_SPD_OVRR0_5r_LOOPCNT1f_SET(reg0_ovr5, pc->lpcnt1); 4351 SC_X1_SPD_OVRR0_5r_LOOPCNT0f_SET(reg0_ovr5, pc->lpcnt0); 4352 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_5r(pc, reg0_ovr5)); 4353 4354 SC_X1_SPD_OVRR0_6r_MAC_CREDITGENCNTf_SET(reg0_ovr6, pc->mac_cgc); 4355 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_6r(pc, reg0_ovr6)); 4356 SC_X1_SPD_OVRR0_7r_PCS_CLOCKCNT0f_SET(reg0_ovr7, pc->pcs_clkcnt); 4357 SC_X1_SPD_OVRR0_7r_PCS_CREDITENABLEf_SET(reg0_ovr7, pc->pcs_crdten); 4358 SC_X1_SPD_OVRR0_7r_REPLICATION_CNTf_SET(reg0_ovr7, pc->pcs_repcnt); 4359 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_7r(pc, reg0_ovr7)); 4360 4361 SC_X1_SPD_OVRR0_8r_PCS_CREDITGENCNTf_SET(reg0_ovr8, pc->pcs_cgc); 4362 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_8r(pc, reg0_ovr8)); 4363 } /* (st_entry_num == 0) */ 4364 4365 else if (st_entry_num == 1) { 4366 4367 4368 SC_X1_SPD_OVRR1_SPDr_CLR(reg1_ovr_spd); 4369 SC_X1_SPD_OVRR1_SPDr_NUM_LANESf_SET(reg1_ovr_spd, pc->num_lanes); 4370 SC_X1_SPD_OVRR1_SPDr_SPEEDf_SET(reg1_ovr_spd, st_entry_speed); 4371 4372 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_SPDr(pc, reg1_ovr_spd)); 4373 4374 SC_X1_SPD_OVRR1_0r_CLR(reg1_ovr); 4375 SC_X1_SPD_OVRR1_1r_CLR(reg1_ovr1); 4376 SC_X1_SPD_OVRR1_2r_CLR(reg1_ovr2); 4377 SC_X1_SPD_OVRR1_3r_CLR(reg1_ovr3); 4378 SC_X1_SPD_OVRR1_4r_CLR(reg1_ovr4); 4379 SC_X1_SPD_OVRR1_5r_CLR(reg1_ovr5); 4380 SC_X1_SPD_OVRR1_6r_CLR(reg1_ovr6); 4381 SC_X1_SPD_OVRR1_7r_CLR(reg1_ovr7); 4382 SC_X1_SPD_OVRR1_8r_CLR(reg1_ovr8); 4383 4384 SC_X1_SPD_OVRR1_0r_ENCODEMODEf_SET(reg1_ovr, pc->t_encode_mode); 4385 SC_X1_SPD_OVRR1_0r_SCR_MODEf_SET(reg1_ovr, pc->t_scr_mode); 4386 SC_X1_SPD_OVRR1_0r_OS_MODEf_SET(reg1_ovr, pc->t_pma_os_mode); 4387 4388 4389 if (pc->cl72_en & 0x40000000) 4390 SC_X1_SPD_OVRR1_0r_CL72_ENABLEf_SET(reg1_ovr, pc->cl72_en) ; 4391 4392 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_0r(pc, reg1_ovr)); 4393 4394 SC_X1_SPD_OVRR1_1r_BRCM64B66_DESCRAMBLER_ENABLEf_SET(reg1_ovr1, pc->r_dec1_brcm64b66_descr); 4395 SC_X1_SPD_OVRR1_1r_CL36BYTEDELETEMOD16Ef_SET(reg1_ovr1, pc->r_desc2_byte_deletion); 4396 SC_X1_SPD_OVRR1_1r_DESC2_MODEf_SET(reg1_ovr1, pc->r_desc2_mode); 4397 SC_X1_SPD_OVRR1_1r_DESKEWMODEf_SET(reg1_ovr1, pc->r_deskew_mode); 4398 SC_X1_SPD_OVRR1_1r_DECODERMODEf_SET(reg1_ovr1, pc->r_dec1_mode); 4399 SC_X1_SPD_OVRR1_1r_DESCRAMBLERMODEf_SET(reg1_ovr1, pc->r_descr1_mode); 4400 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_1r(pc, reg1_ovr1)); 4401 4402 SC_X1_SPD_OVRR1_2r_CL36_ENf_SET(reg1_ovr2, pc->cl36_en); 4403 SC_X1_SPD_OVRR1_2r_REORDER_ENf_SET(reg1_ovr2, pc->r_reorder_mode); 4404 SC_X1_SPD_OVRR1_2r_BLOCK_SYNC_MODEf_SET(reg1_ovr2, pc->blk_sync_mode); 4405 SC_X1_SPD_OVRR1_2r_CHK_END_ENf_SET(reg1_ovr2, pc->cl48_check_end); 4406 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_2r(pc, reg1_ovr2)); 4407 4408 SC_X1_SPD_OVRR1_3r_CLOCKCNT0f_SET(reg1_ovr3, pc->clkcnt0); 4409 SC_X1_SPD_OVRR1_3r_SGMII_SPD_SWITCHf_SET(reg1_ovr3, pc->sgmii); 4410 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_3r(pc, reg1_ovr3)); 4411 4412 SC_X1_SPD_OVRR1_4r_CLOCKCNT1f_SET(reg1_ovr4, pc->clkcnt1); 4413 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_4r(pc, reg1_ovr4)); 4414 4415 SC_X1_SPD_OVRR1_5r_LOOPCNT1f_SET(reg1_ovr5, pc->lpcnt1); 4416 SC_X1_SPD_OVRR1_5r_LOOPCNT0f_SET(reg1_ovr5, pc->lpcnt0); 4417 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_5r(pc, reg1_ovr5)); 4418 4419 SC_X1_SPD_OVRR1_6r_MAC_CREDITGENCNTf_SET(reg1_ovr6, pc->mac_cgc); 4420 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_6r(pc, reg1_ovr6)); 4421 SC_X1_SPD_OVRR1_7r_PCS_CLOCKCNT0f_SET(reg1_ovr7, pc->pcs_clkcnt); 4422 SC_X1_SPD_OVRR1_7r_PCS_CREDITENABLEf_SET(reg1_ovr7, pc->pcs_crdten); 4423 SC_X1_SPD_OVRR1_7r_REPLICATION_CNTf_SET(reg1_ovr7, pc->pcs_repcnt); 4424 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_7r(pc, reg1_ovr7)); 4425 4426 SC_X1_SPD_OVRR1_8r_PCS_CREDITGENCNTf_SET(reg1_ovr8, pc->pcs_cgc); 4427 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_8r(pc, reg1_ovr8)); 4428 4429 4430 4431 } /* (st_entry_num == 1) */ 4432 4433 else if (st_entry_num == 2) { 4434 4435 SC_X1_SPD_OVRR2_SPDr_CLR(reg2_ovr_spd); 4436 SC_X1_SPD_OVRR2_SPDr_NUM_LANESf_SET(reg2_ovr_spd, pc->num_lanes); 4437 SC_X1_SPD_OVRR2_SPDr_SPEEDf_SET(reg2_ovr_spd, st_entry_speed); 4438 4439 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_SPDr(pc, reg2_ovr_spd)); 4440 4441 SC_X1_SPD_OVRR2_0r_CLR(reg2_ovr); 4442 SC_X1_SPD_OVRR2_1r_CLR(reg2_ovr1); 4443 SC_X1_SPD_OVRR2_2r_CLR(reg2_ovr2); 4444 SC_X1_SPD_OVRR2_3r_CLR(reg2_ovr3); 4445 SC_X1_SPD_OVRR2_4r_CLR(reg2_ovr4); 4446 SC_X1_SPD_OVRR2_5r_CLR(reg2_ovr5); 4447 SC_X1_SPD_OVRR2_6r_CLR(reg2_ovr6); 4448 SC_X1_SPD_OVRR2_7r_CLR(reg2_ovr7); 4449 SC_X1_SPD_OVRR2_8r_CLR(reg2_ovr8); 4450 4451 SC_X1_SPD_OVRR2_0r_ENCODEMODEf_SET(reg2_ovr, pc->t_encode_mode); 4452 SC_X1_SPD_OVRR2_0r_SCR_MODEf_SET(reg2_ovr, pc->t_scr_mode); 4453 SC_X1_SPD_OVRR2_0r_OS_MODEf_SET(reg2_ovr, pc->t_pma_os_mode); 4454 4455 4456 if (pc->cl72_en & 0x40000000) 4457 SC_X1_SPD_OVRR2_0r_CL72_ENABLEf_SET(reg2_ovr, pc->cl72_en) ; 4458 4459 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_0r(pc, reg2_ovr)); 4460 4461 SC_X1_SPD_OVRR2_1r_BRCM64B66_DESCRAMBLER_ENABLEf_SET(reg2_ovr1, pc->r_dec1_brcm64b66_descr); 4462 SC_X1_SPD_OVRR2_1r_CL36BYTEDELETEMOD16Ef_SET(reg2_ovr1, pc->r_desc2_byte_deletion); 4463 SC_X1_SPD_OVRR2_1r_DESC2_MODEf_SET(reg2_ovr1, pc->r_desc2_mode); 4464 SC_X1_SPD_OVRR2_1r_DESKEWMODEf_SET(reg2_ovr1, pc->r_deskew_mode); 4465 SC_X1_SPD_OVRR2_1r_DECODERMODEf_SET(reg2_ovr1, pc->r_dec1_mode); 4466 SC_X1_SPD_OVRR2_1r_DESCRAMBLERMODEf_SET(reg2_ovr1, pc->r_descr1_mode); 4467 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_1r(pc, reg2_ovr1)); 4468 4469 SC_X1_SPD_OVRR2_2r_CL36_ENf_SET(reg2_ovr2, pc->cl36_en); 4470 SC_X1_SPD_OVRR2_2r_REORDER_ENf_SET(reg2_ovr2, pc->r_reorder_mode); 4471 SC_X1_SPD_OVRR2_2r_BLOCK_SYNC_MODEf_SET(reg2_ovr2, pc->blk_sync_mode); 4472 SC_X1_SPD_OVRR2_2r_CHK_END_ENf_SET(reg2_ovr2, pc->cl48_check_end); 4473 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_2r(pc, reg2_ovr2)); 4474 4475 SC_X1_SPD_OVRR2_3r_CLOCKCNT0f_SET(reg2_ovr3, pc->clkcnt0); 4476 SC_X1_SPD_OVRR2_3r_SGMII_SPD_SWITCHf_SET(reg2_ovr3, pc->sgmii); 4477 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_3r(pc, reg2_ovr3)); 4478 4479 SC_X1_SPD_OVRR2_4r_CLOCKCNT1f_SET(reg2_ovr4, pc->clkcnt1); 4480 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_4r(pc, reg2_ovr4)); 4481 4482 SC_X1_SPD_OVRR2_5r_LOOPCNT1f_SET(reg2_ovr5, pc->lpcnt1); 4483 SC_X1_SPD_OVRR2_5r_LOOPCNT0f_SET(reg2_ovr5, pc->lpcnt0); 4484 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_5r(pc, reg2_ovr5)); 4485 4486 SC_X1_SPD_OVRR2_6r_MAC_CREDITGENCNTf_SET(reg2_ovr6, pc->mac_cgc); 4487 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_6r(pc, reg2_ovr6)); 4488 SC_X1_SPD_OVRR2_7r_PCS_CLOCKCNT0f_SET(reg2_ovr7, pc->pcs_clkcnt); 4489 SC_X1_SPD_OVRR2_7r_PCS_CREDITENABLEf_SET(reg2_ovr7, pc->pcs_crdten); 4490 SC_X1_SPD_OVRR2_7r_REPLICATION_CNTf_SET(reg2_ovr7, pc->pcs_repcnt); 4491 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_7r(pc, reg2_ovr7)); 4492 4493 SC_X1_SPD_OVRR2_8r_PCS_CREDITGENCNTf_SET(reg2_ovr8, pc->pcs_cgc); 4494 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_8r(pc, reg2_ovr8)); 4495 } /* (st_entry_num == 2) */ 4496 4497 else /*(st_entry_num == 3) */ { 4498 4499 SC_X1_SPD_OVRR3_SPDr_CLR(reg3_ovr_spd); 4500 SC_X1_SPD_OVRR3_SPDr_NUM_LANESf_SET(reg3_ovr_spd, pc->num_lanes); 4501 SC_X1_SPD_OVRR3_SPDr_SPEEDf_SET(reg3_ovr_spd, st_entry_speed); 4502 4503 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_SPDr(pc, reg3_ovr_spd)); 4504 4505 SC_X1_SPD_OVRR3_0r_CLR(reg3_ovr); 4506 SC_X1_SPD_OVRR3_1r_CLR(reg3_ovr1); 4507 SC_X1_SPD_OVRR3_2r_CLR(reg3_ovr2); 4508 SC_X1_SPD_OVRR3_3r_CLR(reg3_ovr3); 4509 SC_X1_SPD_OVRR3_4r_CLR(reg3_ovr4); 4510 SC_X1_SPD_OVRR3_5r_CLR(reg3_ovr5); 4511 SC_X1_SPD_OVRR3_6r_CLR(reg3_ovr6); 4512 SC_X1_SPD_OVRR3_7r_CLR(reg3_ovr7); 4513 SC_X1_SPD_OVRR3_8r_CLR(reg3_ovr8); 4514 4515 SC_X1_SPD_OVRR3_0r_ENCODEMODEf_SET(reg3_ovr, pc->t_encode_mode); 4516 SC_X1_SPD_OVRR3_0r_SCR_MODEf_SET(reg3_ovr, pc->t_scr_mode); 4517 SC_X1_SPD_OVRR3_0r_OS_MODEf_SET(reg3_ovr, pc->t_pma_os_mode); 4518 4519 4520 if (pc->cl72_en & 0x40000000) 4521 SC_X1_SPD_OVRR3_0r_CL72_ENABLEf_SET(reg3_ovr, pc->cl72_en) ; 4522 4523 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_0r(pc, reg3_ovr)); 4524 4525 SC_X1_SPD_OVRR3_1r_BRCM64B66_DESCRAMBLER_ENABLEf_SET(reg3_ovr1, pc->r_dec1_brcm64b66_descr); 4526 SC_X1_SPD_OVRR3_1r_CL36BYTEDELETEMOD16Ef_SET(reg3_ovr1, pc->r_desc2_byte_deletion); 4527 SC_X1_SPD_OVRR3_1r_DESC2_MODEf_SET(reg3_ovr1, pc->r_desc2_mode); 4528 SC_X1_SPD_OVRR3_1r_DESKEWMODEf_SET(reg3_ovr1, pc->r_deskew_mode); 4529 SC_X1_SPD_OVRR3_1r_DECODERMODEf_SET(reg3_ovr1, pc->r_dec1_mode); 4530 SC_X1_SPD_OVRR3_1r_DESCRAMBLERMODEf_SET(reg3_ovr1, pc->r_descr1_mode); 4531 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_1r(pc, reg3_ovr1)); 4532 4533 SC_X1_SPD_OVRR3_2r_CL36_ENf_SET(reg3_ovr2, pc->cl36_en); 4534 SC_X1_SPD_OVRR3_2r_REORDER_ENf_SET(reg3_ovr2, pc->r_reorder_mode); 4535 SC_X1_SPD_OVRR3_2r_BLOCK_SYNC_MODEf_SET(reg3_ovr2, pc->blk_sync_mode); 4536 SC_X1_SPD_OVRR3_2r_CHK_END_ENf_SET(reg3_ovr2, pc->cl48_check_end); 4537 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_2r(pc, reg3_ovr2)); 4538 4539 SC_X1_SPD_OVRR3_3r_CLOCKCNT0f_SET(reg3_ovr3, pc->clkcnt0); 4540 SC_X1_SPD_OVRR3_3r_SGMII_SPD_SWITCHf_SET(reg3_ovr3, pc->sgmii); 4541 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_3r(pc, reg3_ovr3)); 4542 4543 SC_X1_SPD_OVRR3_4r_CLOCKCNT1f_SET(reg3_ovr4, pc->clkcnt1); 4544 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_4r(pc, reg3_ovr4)); 4545 4546 SC_X1_SPD_OVRR3_5r_LOOPCNT1f_SET(reg3_ovr5, pc->lpcnt1); 4547 SC_X1_SPD_OVRR3_5r_LOOPCNT0f_SET(reg3_ovr5, pc->lpcnt0); 4548 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_5r(pc, reg3_ovr5)); 4549 4550 SC_X1_SPD_OVRR3_6r_MAC_CREDITGENCNTf_SET(reg3_ovr6, pc->mac_cgc); 4551 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_6r(pc, reg3_ovr6)); 4552 SC_X1_SPD_OVRR3_7r_PCS_CLOCKCNT0f_SET(reg3_ovr7, pc->pcs_clkcnt); 4553 SC_X1_SPD_OVRR3_7r_PCS_CREDITENABLEf_SET(reg3_ovr7, pc->pcs_crdten); 4554 SC_X1_SPD_OVRR3_7r_REPLICATION_CNTf_SET(reg3_ovr7, pc->pcs_repcnt); 4555 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_7r(pc, reg3_ovr7)); 4556 4557 SC_X1_SPD_OVRR3_8r_PCS_CREDITGENCNTf_SET(reg3_ovr8, pc->pcs_cgc); 4558 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_8r(pc, reg3_ovr8)); 4559 } /* (st_entry_num == 3) */ 4560 4561 return PHYMOD_E_NONE; 4562 } 4563 #endif 4564 4565 #ifdef _DV_TB_ 4566 /** 4567 @brief Read the 16 bit rev. id value etc. 4568 @param pc handle to current TSCE context (#PHYMOD_ST) 4569 @returns The value PHYMOD_E_NONE upon successful completion 4570 @details Per Port PCS Init 4571 */ 4572 int _configure_sc_speed_configuration(PHYMOD_ST* pc) 4573 { 4574 int data =0; 4575 int mask =0; 4576 int st_entry =0; 4577 int speed_entry = 0; 4578 PHYMOD_ST pc_st_tmp; 4579 PHYMOD_ST* pc_st; 4580 4581 if (pc->sc_mode == TEMOD16_SC_MODE_HT_WITH_BASIC_OVERRIDE) { 4582 /* Configure the ffec_eb regsiter */ 4583 data |= (1 << 10); 4584 mask |= 0x0400; 4585 4586 } 4587 else if (pc->sc_mode == TEMOD16_SC_MODE_ST_OVERRIDE) { 4588 } 4589 else if (pc->sc_mode == TEMOD16_SC_MODE_ST) { 4590 st_entry = pc->per_lane_control & 0xff; 4591 speed_entry = (pc->per_lane_control & 0xff00) >> 8; 4592 4593 /* 4594 A pc_st_tmp is created so the overriden expected values passed from SV are not 4595 loaded in ST, and teh ST has the same HT values 4596 */ 4597 init_temod16_st(&pc_st_tmp); 4598 pc_st_tmp.spd_intf = pc->spd_intf; 4599 pc_st_tmp.prt_ad = pc->prt_ad; 4600 pc_st_tmp.unit = pc->unit; 4601 pc_st_tmp.port_type = pc->port_type; 4602 pc_st_tmp.this_lane = pc->this_lane; 4603 pc_st_tmp.sc_mode = pc->sc_mode; 4604 pc_st_tmp.cl72_en = pc->cl72_en; 4605 pc_st = &pc_st_tmp; 4606 temod16_sc_lkup_table(pc_st); 4607 /*configure the ST regsiters */ 4608 _configure_st_entry(st_entry, speed_entry, pc_st); 4609 4610 } 4611 return PHYMOD_E_NONE; 4612 } 4613 #endif 4614 4615 #ifdef _DV_TB_ 4616 /** 4617 @brief Read the 16 bit rev. id value etc. 4618 @param pc handle to current TSCE context (#PHYMOD_ST) 4619 @returns The value PHYMOD_E_NONE upon successful completion 4620 @details Per Port PCS Init 4621 */ 4622 int _init_pcs_an(PHYMOD_ST* pc) 4623 { 4624 UC_CLK_CTL0r_t reg_ctrl0; 4625 UC_RST_CTL0r_t reg_rst_ctrl0; 4626 4627 UC_CLK_CTL0r_CLR(reg_ctrl0); 4628 UC_RST_CTL0r_CLR(reg_rst_ctrl0); 4629 4630 UC_CLK_CTL0r_MICRO_MASTER_CLK_ENf_SET(reg_ctrl0, 1); 4631 PHYMOD_IF_ERR_RETURN(MODIFY_UC_CLK_CTL0r(pc, reg_ctrl0)); 4632 4633 UC_RST_CTL0r_MICRO_MASTER_RSTBf_SET(reg_rst_ctrl0, 1); 4634 PHYMOD_IF_ERR_RETURN(MODIFY_UC_RST_CTL0r(pc, reg_rst_ctrl0)); 4635 4636 temod16_set_an_port_mode(pc); 4637 pc->port_type=TEMOD16_MULTI_PORT; 4638 temod16_autoneg_set(pc); 4639 temod16_autoneg_control(pc); 4640 4641 return PHYMOD_E_NONE; 4642 } 4643 #endif /* _DV_TB_ */ 4644 #ifdef _SDK_TEMOD16_TEMP_ 4645 4646 int _init_pcs_an(PHYMOD_ST* pc) 4647 { 4648 temod16_an_set_type_t ata_type; 4649 temod16_tech_ability an_tech_ability = 0; 4650 temod16_cl37bam_ability an_cl37bam_ability = 0; 4651 temod16_an_mode_type_t an_mode = 0; 4652 int data; 4653 4654 /* temod16_autoneg_init(pc); */ 4655 temod16_autoneg_timer_init(pc); 4656 /* temod16_tick_override_set(pc, pc->an_tick_override, pc->an_tick_numerator, pc->an_tick_denominator); */ 4657 temod16_set_an_port_mode(pc, 1, pc->no_of_lanes, pc->this_lane, pc->single_port); 4658 4659 /* TBD: add locgic to port the info from pc to an_ability_st and an_control */ 4660 temod16_autoneg_set( pc, an_ability_st); 4661 temod16_autoneg_control(pc, an_control) 4662 4663 return PHYMOD_E_NONE; 4664 } 4665 #endif /* _SDK_TEMOD16_TEMP_ */ 4666 4667 /** 4668 @brief Read the 16 bit rev. id value etc. 4669 @param pc handle to current TSCE context (#PHYMOD_ST) 4670 @returns The value PHYMOD_E_NONE upon successful completion 4671 @details Per Port PCS Init 4672 */ 4673 4674 int temod16_trigger_speed_change(PHYMOD_ST* pc) 4675 { 4676 SC_X4_CTLr_t reg; 4677 4678 TMOD_DBG_IN_FUNC_INFO(pc); 4679 #ifdef _DV_TB_ 4680 pc->adjust_port_mode = 1; 4681 #endif /* _DV_TB_ */ 4682 #ifdef _SDK_TEMOD16_ 4683 4684 #endif 4685 4686 /* write 0 to the speed change */ 4687 SC_X4_CTLr_CLR(reg); 4688 PHYMOD_IF_ERR_RETURN(READ_SC_X4_CTLr(pc, ®)); 4689 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(reg, 0); 4690 PHYMOD_IF_ERR_RETURN(WRITE_SC_X4_CTLr(pc, reg)); 4691 4692 /* write 1 to the speed change. No need to read again before write*/ 4693 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(reg, 1); 4694 PHYMOD_IF_ERR_RETURN(WRITE_SC_X4_CTLr(pc, reg)); 4695 4696 #ifdef _DV_TB_ 4697 pc->adjust_port_mode = 0; 4698 #endif /* _DV_TB_ */ 4699 #ifdef _SDK_TEMOD16_ 4700 4701 #endif 4702 4703 return PHYMOD_E_NONE; 4704 } 4705 4706 #ifdef _DV_TB_ 4707 /** 4708 @brief Read the 16 bit rev. id value etc. 4709 @param pc handle to current TSCE context (#PHYMOD_ST) 4710 @returns The value PHYMOD_E_NONE upon successful completion 4711 @details Per Port PCS Init 4712 */ 4713 int _read_and_compare_final_status(PHYMOD_ST* pc) 4714 { 4715 uint16_t fail; 4716 int actual_speed; 4717 PHYMOD_ST sc_final_stats_actual; 4718 PHYMOD_ST* sc_final_stats_actual_tmp; 4719 SC_X4_RSLVD_SPDr_t reg_resolved_spd; 4720 SC_X4_RSLVD0r_t reg_resolved_0; 4721 SC_X4_RSLVD1r_t reg_resolved_1; 4722 SC_X4_RSLVD2r_t reg_resolved_2; 4723 SC_X4_RSLVD3r_t reg_resolved_3; 4724 SC_X4_RSLVD4r_t reg_resolved_4; 4725 SC_X4_RSLVD5r_t reg_resolved_5; 4726 SC_X4_RSLVD6r_t reg_resolved_6; 4727 SC_X4_RSLVD7r_t reg_resolved_7; 4728 SC_X4_RSLVD8r_t reg_resolved_8; 4729 4730 SC_X4_RSLVD_SPDr_CLR(reg_resolved_spd); 4731 PHYMOD_IF_ERR_RETURN(READ_SC_X4_RSLVD_SPDr(pc, ®_resolved_spd)); 4732 sc_final_stats_actual.num_lanes = SC_X4_RSLVD_SPDr_NUM_LANESf_GET(reg_resolved_spd); 4733 actual_speed = SC_X4_RSLVD_SPDr_SPEEDf_GET(reg_resolved_spd); 4734 sc_final_stats_actual.speed = actual_speed; 4735 4736 SC_X4_RSLVD0r_CLR(reg_resolved_0); 4737 PHYMOD_IF_ERR_RETURN(READ_SC_X4_RSLVD0r(pc, ®_resolved_0)); 4738 sc_final_stats_actual.t_encode_mode = SC_X4_RSLVD0r_ENCODEMODEf_GET(reg_resolved_0); 4739 sc_final_stats_actual.cl72_en = SC_X4_RSLVD0r_CL72_ENABLEf_GET(reg_resolved_0); 4740 sc_final_stats_actual.fec_en = SC_X4_RSLVD0r_FEC_ENABLEf_GET(reg_resolved_0); 4741 sc_final_stats_actual.t_scr_mode = SC_X4_RSLVD0r_SCR_MODEf_GET(reg_resolved_0); 4742 sc_final_stats_actual.t_pma_os_mode = SC_X4_RSLVD0r_OS_MODEf_GET(reg_resolved_0); 4743 4744 SC_X4_RSLVD1r_CLR(reg_resolved_1); 4745 PHYMOD_IF_ERR_RETURN(READ_SC_X4_RSLVD1r(pc, ®_resolved_1)); 4746 sc_final_stats_actual.r_dec1_brcm64b66_descr = SC_X4_RSLVD1r_BRCM64B66_DESCRAMBLER_ENABLEf_GET(reg_resolved_1); 4747 sc_final_stats_actual.r_desc2_byte_deletion = SC_X4_RSLVD1r_CL36BYTEDELETEMOD16Ef_GET(reg_resolved_1); 4748 sc_final_stats_actual.r_desc2_mode = SC_X4_RSLVD1r_DESC2_MODEf_GET(reg_resolved_1); 4749 sc_final_stats_actual.r_deskew_mode = SC_X4_RSLVD1r_DESKEWMODEf_GET(reg_resolved_1); 4750 sc_final_stats_actual.r_dec1_mode = SC_X4_RSLVD1r_DECODERMODEf_GET(reg_resolved_1); 4751 sc_final_stats_actual.r_descr1_mode = SC_X4_RSLVD1r_DESCRAMBLERMODEf_GET(reg_resolved_1); 4752 4753 SC_X4_RSLVD2r_CLR(reg_resolved_2); 4754 PHYMOD_IF_ERR_RETURN(READ_SC_X4_RSLVD2r(pc, ®_resolved_2)); 4755 sc_final_stats_actual.cl36_en = SC_X4_RSLVD2r_CL36_ENf_GET(reg_resolved_2); 4756 sc_final_stats_actual.r_reorder_mode = SC_X4_RSLVD2r_REORDER_ENf_GET(reg_resolved_2); 4757 sc_final_stats_actual.blk_sync_mode = SC_X4_RSLVD2r_BLOCK_SYNC_MODEf_GET(reg_resolved_2); 4758 sc_final_stats_actual.cl48_check_end = SC_X4_RSLVD2r_CHK_END_ENf_GET(reg_resolved_2); 4759 4760 SC_X4_RSLVD3r_CLR(reg_resolved_3); 4761 PHYMOD_IF_ERR_RETURN(READ_SC_X4_RSLVD3r(pc, ®_resolved_3)); 4762 sc_final_stats_actual.clkcnt0 = SC_X4_RSLVD3r_CLOCKCNT0f_GET(reg_resolved_3); 4763 sc_final_stats_actual.sgmii = SC_X4_RSLVD3r_SGMII_SPD_SWITCHf_GET(reg_resolved_3); 4764 4765 SC_X4_RSLVD4r_CLR(reg_resolved_4); 4766 PHYMOD_IF_ERR_RETURN(READ_SC_X4_RSLVD4r(pc, ®_resolved_4)); 4767 sc_final_stats_actual.clkcnt1 = SC_X4_RSLVD4r_CLOCKCNT1f_GET(reg_resolved_4); 4768 4769 SC_X4_RSLVD5r_CLR(reg_resolved_5); 4770 PHYMOD_IF_ERR_RETURN(READ_SC_X4_RSLVD5r(pc, ®_resolved_5)); 4771 sc_final_stats_actual.lpcnt1 = SC_X4_RSLVD5r_LOOPCNT1f_GET(reg_resolved_5); 4772 sc_final_stats_actual.lpcnt0 = SC_X4_RSLVD5r_LOOPCNT0f_GET(reg_resolved_5); 4773 4774 SC_X4_RSLVD6r_CLR(reg_resolved_6); 4775 PHYMOD_IF_ERR_RETURN(READ_SC_X4_RSLVD6r(pc, ®_resolved_6)); 4776 sc_final_stats_actual.mac_cgc = SC_X4_RSLVD6r_MAC_CREDITGENCNTf_GET(reg_resolved_6); 4777 4778 SC_X4_RSLVD7r_CLR(reg_resolved_7); 4779 PHYMOD_IF_ERR_RETURN(READ_SC_X4_RSLVD7r(pc, ®_resolved_7)); 4780 sc_final_stats_actual.pcs_clkcnt = SC_X4_RSLVD7r_PCS_CLOCKCNT0f_GET(reg_resolved_7); 4781 sc_final_stats_actual.pcs_crdten = SC_X4_RSLVD7r_PCS_CREDITENABLEf_GET(reg_resolved_7); 4782 sc_final_stats_actual.pcs_repcnt = SC_X4_RSLVD7r_REPLICATION_CNTf_GET(reg_resolved_7); 4783 4784 SC_X4_RSLVD8r_CLR(reg_resolved_8); 4785 PHYMOD_IF_ERR_RETURN(READ_SC_X4_RSLVD8r(pc, ®_resolved_8)); 4786 sc_final_stats_actual.pcs_cgc = SC_X4_RSLVD8r_PCS_CREDITGENCNTf_GET(reg_resolved_8); 4787 4788 /* Compare the actual and expected stats */ 4789 fail = 0; 4790 4791 4792 if (pc->sc_mode == TEMOD16_SC_MODE_ST) { 4793 if (actual_speed != (pc->per_lane_control >> 8)) 4794 fail = 1; 4795 } else if ((pc->per_lane_control & 0xffff) == (0x004 | (TEMOD16_SPD_10000_XFI << 8))) { /* DV Verification Only */ 4796 if (actual_speed != digital_operationSpeeds_SPEED_10G_KR1) 4797 fail = 1; 4798 } else if ((pc->per_lane_control & 0xffff) == (0x004 | (TEMOD16_SPD_10_SGMII << 8))) { /* DV Verification Only */ 4799 if (actual_speed != digital_operationSpeeds_SPEED_10M) 4800 fail = 1; 4801 } else if ((pc->per_lane_control & 0xffff) == (0x004 | (TEMOD16_SPD_5000_XFI << 8))) { /* DV Verification Only */ 4802 if (actual_speed != digital_operationSpeeds_SPEED_5G_KR1) 4803 fail = 1; 4804 } else { 4805 if (actual_speed != pc->speed) 4806 fail = 1; 4807 } 4808 4809 if (sc_final_stats_actual.num_lanes != pc->num_lanes) 4810 fail = 1; 4811 if (sc_final_stats_actual.t_pma_os_mode != pc->t_pma_os_mode) 4812 fail = 1; 4813 if (sc_final_stats_actual.t_scr_mode != pc->t_scr_mode) 4814 fail = 1; 4815 if (sc_final_stats_actual.fec_en != pc->fec_en) 4816 fail = 1; 4817 if (sc_final_stats_actual.t_encode_mode != pc->t_encode_mode) 4818 fail = 1; 4819 4820 4821 if (pc->cl72_en & 0x08000000) { 4822 if (sc_final_stats_actual.cl72_en != (pc->cl72_en & 0xffff)) 4823 fail = 1; 4824 } 4825 4826 if (sc_final_stats_actual.r_descr1_mode != pc->r_descr1_mode) 4827 fail = 1; 4828 if (sc_final_stats_actual.r_dec1_mode != pc->r_dec1_mode) 4829 fail = 1; 4830 if (sc_final_stats_actual.r_deskew_mode != pc->r_deskew_mode) 4831 fail = 1; 4832 if (sc_final_stats_actual.r_desc2_mode != pc->r_desc2_mode) 4833 fail = 1; 4834 if (sc_final_stats_actual.r_desc2_byte_deletion != pc->r_desc2_byte_deletion) 4835 fail = 1; 4836 if (sc_final_stats_actual.r_dec1_brcm64b66_descr != pc->r_dec1_brcm64b66_descr) 4837 fail = 1; 4838 4839 if (sc_final_stats_actual.cl48_check_end != pc->cl48_check_end) 4840 fail = 1; 4841 if (sc_final_stats_actual.blk_sync_mode != pc->blk_sync_mode) 4842 fail = 1; 4843 if (sc_final_stats_actual.r_reorder_mode != pc->r_reorder_mode) 4844 fail = 1; 4845 if (sc_final_stats_actual.cl36_en != pc->cl36_en) 4846 fail = 1; 4847 4848 if (sc_final_stats_actual.sgmii != pc->sgmii) 4849 fail = 1; 4850 if (sc_final_stats_actual.clkcnt0 != pc->clkcnt0) 4851 fail = 1; 4852 if (sc_final_stats_actual.clkcnt1 != pc->clkcnt1) 4853 fail = 1; 4854 if (sc_final_stats_actual.lpcnt0 != pc->lpcnt0) 4855 fail = 1; 4856 if (sc_final_stats_actual.lpcnt1 != pc->lpcnt1) 4857 fail = 1; 4858 if (sc_final_stats_actual.mac_cgc != pc->mac_cgc) 4859 fail = 1; 4860 if (sc_final_stats_actual.pcs_repcnt != pc->pcs_repcnt) 4861 fail = 1; 4862 if (sc_final_stats_actual.pcs_crdten != pc->pcs_crdten) 4863 fail = 1; 4864 if (sc_final_stats_actual.pcs_clkcnt != pc->pcs_clkcnt) 4865 fail = 1; 4866 if (sc_final_stats_actual.pcs_cgc != pc->pcs_cgc) 4867 fail = 1; 4868 4869 pc->accData = fail; 4870 if (fail == 1) { 4871 #ifdef _DV_TB_ 4872 printf("Actual stats:\n"); 4873 sc_final_stats_actual_tmp = &sc_final_stats_actual; 4874 print_temod16_sc_lkup_table(sc_final_stats_actual_tmp); 4875 printf("Expected stats:\n"); 4876 print_temod16_sc_lkup_table(pc); 4877 #endif 4878 return PHYMOD_E_FAIL; 4879 } 4880 return PHYMOD_E_NONE; 4881 } 4882 #endif 4883 4884 #ifdef _DV_TB_ 4885 /** 4886 @brief Read the 16 bit rev. id value etc. 4887 @param pc handle to current TSCE context (#PHYMOD_ST) 4888 @returns The value PHYMOD_E_NONE upon successful completion 4889 @details Per Port PCS Init for forced speeds 4890 4891 */ 4892 int _init_pcs_fs(PHYMOD_ST* pc) 4893 { 4894 uint16_t data; 4895 SC_X4_CTLr_t reg_swmode; 4896 4897 _get_sc_speed_configuration(pc); 4898 _configure_sc_speed_configuration(pc); 4899 4900 /* Set speed */ 4901 if (pc->sc_mode == TEMOD16_SC_MODE_ST) 4902 data = (pc->per_lane_control & 0xff00) >> 8; 4903 else if ((pc->per_lane_control & 0xffff) == (0x004 | (TEMOD16_SPD_10000_XFI << 8))) /* DV Verification Only */ 4904 data = digital_operationSpeeds_SPEED_10G_KR1; 4905 else if ((pc->per_lane_control & 0xffff) == (0x004 | (TEMOD16_SPD_10_SGMII << 8))) /* DV Verification Only */ 4906 data = digital_operationSpeeds_SPEED_10M; 4907 else if ((pc->per_lane_control & 0xffff) == (0x004 | (TEMOD16_SPD_5000_XFI << 8))) /* DV Verification Only */ 4908 data = digital_operationSpeeds_SPEED_5G_KR1; 4909 else 4910 data = pc->speed; 4911 4912 SC_X4_CTLr_CLR(reg_swmode); 4913 SC_X4_CTLr_SW_SPEEDf_SET(reg_swmode, data); 4914 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_CTLr(pc, reg_swmode)); 4915 4916 temod16_trigger_speed_change(pc); 4917 _temod16_wait_sc_stats_set(pc); 4918 4919 return PHYMOD_E_NONE; 4920 } 4921 #endif 4922 4923 /** 4924 @brief Initialize the PMD for QSGMII PCS. (different from TSCE PCS) 4925 @param pc handle to current TSCE context (#PHYMOD_ST) 4926 @returns The value PHYMOD_E_NONE upon successful completion 4927 @details Details pending. 4928 */ 4929 int temod16_init_pmd_qsgmii(PHYMOD_ST* pc, int pmd_touched, int uc_active) /* INIT_PMD_SGMII */ 4930 { 4931 return PHYMOD_E_NONE; 4932 } 4933 4934 /** 4935 @brief TSC12 DV stuff. Incomplete 4936 @param pc handle to current TSCE context (#PHYMOD_ST) 4937 @returns The value PHYMOD_E_NONE upon successful completion. 4938 @details Called to Configure tsc12 for 100G+ speeds 4939 4940 */ 4941 4942 int temod16_tsc12_control(PHYMOD_ST* pc, int cl82_multi_pipe_mode, int cl82_mld_phys_map) /* TSC12_CONTROL */ 4943 { 4944 MAIN0_MISCr_t reg_misc; 4945 TMOD_DBG_IN_FUNC_INFO(pc); 4946 MAIN0_MISCr_CLR(reg_misc); 4947 4948 MAIN0_MISCr_CL82_MULTI_PIPE_MODEf_SET(reg_misc, (cl82_multi_pipe_mode & 0x3)); 4949 MAIN0_MISCr_CL82_MLD_PHYS_MAPf_SET(reg_misc, (cl82_mld_phys_map & 0x3)); 4950 4951 PHYMOD_IF_ERR_RETURN (MODIFY_MAIN0_MISCr(pc, reg_misc)); 4952 return PHYMOD_E_NONE; 4953 } 4954 4955 /* 4956 int temod16_set_bit_repli(PHYMOD_ST* pc, temod16_spd_intfc_type spd_intf ) 4957 { 4958 MAIN0_MISCr_t reg_misc; 4959 TMOD_DBG_IN_FUNC_INFO(pc); 4960 MAIN0_MISCr_CLR(reg_misc); 4961 4962 MAIN0_MISCr_TX_PCS_BIT_REPL_ENf_SET(reg_misc, pc->bit_rep_native_mode); 4963 PHYMOD_IF_ERR_RETURN (MODIFY_MAIN0_MISCr(pc, reg_misc)); 4964 4965 return PHYMOD_E_NONE; 4966 } 4967 */ 4968 4969 #ifdef _DV_TB_ 4970 /** 4971 @brief Checks to ensure SC has programmed the PCS as expected 4972 @param pc handle to current TSCE context (#PHYMOD_ST) 4973 @returns The value PHYMOD_E_NONE upon successful completion. 4974 @details Called to Configure tsc12 for 100G+ speeds 4975 4976 */ 4977 4978 int temod16_check_sc_stats(PHYMOD_ST* pc) /* CHECK_SC_STATS */ 4979 { 4980 uint16_t data ; 4981 4982 TMOD_DBG_IN_FUNC_INFO(pc); 4983 data = _read_and_compare_final_status(pc); 4984 return PHYMOD_E_NONE; 4985 } 4986 #endif /* _DV_TB_ */ 4987 4988 4989 /** 4990 @brief get the rx lane reset staus for any lane 4991 @param pc handle to current TSCE context (#PHYMOD_ST) 4992 @param get the status as *value 4993 @returns The value PHYMOD_E_NONE upon successful completion. 4994 4995 This function enables/disables rx lane (RSTB_LANE) or read back control bit for 4996 that based on per_lane_control being 1 or 0. If per_lane_control is 0xa, only 4997 read back RSTB_LANE. 4998 4999 */ 5000 int temod16_rx_lane_control_get(PHYMOD_ST* pc, int *value) /* RX_LANE_CONTROL */ 5001 { 5002 RX_X4_PMA_CTL0r_t reg_pma_ctrl; 5003 5004 TMOD_DBG_IN_FUNC_INFO(pc); 5005 RX_X4_PMA_CTL0r_CLR(reg_pma_ctrl); 5006 5007 PHYMOD_IF_ERR_RETURN (READ_RX_X4_PMA_CTL0r(pc, ®_pma_ctrl)); 5008 if ( RX_X4_PMA_CTL0r_RSTB_LANEf_GET(reg_pma_ctrl) ) 5009 *value = 1; 5010 else 5011 *value = 0; 5012 5013 return PHYMOD_E_NONE; 5014 } 5015 5016 /** 5017 @brief rx lane reset and enable of any particular lane 5018 @param pc handle to current TSCE context (#PHYMOD_ST) 5019 @param enable to reset the lane. 5020 @returns The value PHYMOD_E_NONE upon successful completion. 5021 5022 This function enables/disables rx lane (RSTB_LANE) or read back control bit for 5023 that based on per_lane_control being 1 or 0. If per_lane_control is 0xa, only 5024 read back RSTB_LANE. 5025 5026 */ 5027 int temod16_rx_lane_control_set(PHYMOD_ST* pc, int enable) /* RX_LANE_CONTROL */ 5028 { 5029 RX_X4_PMA_CTL0r_t reg_pma_ctrl; 5030 5031 TMOD_DBG_IN_FUNC_INFO(pc); 5032 RX_X4_PMA_CTL0r_CLR(reg_pma_ctrl); 5033 if (enable) { 5034 RX_X4_PMA_CTL0r_RSTB_LANEf_SET(reg_pma_ctrl, 1); 5035 PHYMOD_IF_ERR_RETURN (MODIFY_RX_X4_PMA_CTL0r(pc, reg_pma_ctrl)); 5036 } else { 5037 /* bit set to 0 for disabling RXP */ 5038 RX_X4_PMA_CTL0r_RSTB_LANEf_SET( reg_pma_ctrl, 0); 5039 PHYMOD_IF_ERR_RETURN (MODIFY_RX_X4_PMA_CTL0r(pc, reg_pma_ctrl)); 5040 } 5041 return PHYMOD_E_NONE; 5042 } 5043 5044 #ifdef _DV_TB_ 5045 int temod16_prbs_rx_enable_set(PHYMOD_ST* pc, int enable) 5046 { 5047 TLB_RX_PRBS_CHK_CFGr_t reg_prbs_chk_cfg; 5048 5049 TMOD_DBG_IN_FUNC_INFO(pc); 5050 TLB_RX_PRBS_CHK_CFGr_CLR(reg_prbs_chk_cfg); 5051 5052 TLB_RX_PRBS_CHK_CFGr_PRBS_CHK_ENf_SET(reg_prbs_chk_cfg, enable); 5053 PHYMOD_IF_ERR_RETURN (MODIFY_TLB_RX_PRBS_CHK_CFGr(pc, reg_prbs_chk_cfg)); 5054 5055 return PHYMOD_E_NONE; 5056 } 5057 #endif 5058 5059 #ifdef _DV_TB_ 5060 int temod16_prbs_tx_enable_set(PHYMOD_ST* pc, int enable) /* PRBS_MODE */ 5061 { 5062 TLB_TX_PRBS_GEN_CFGr_t reg_prbs_gen_cfg; 5063 5064 TMOD_DBG_IN_FUNC_INFO(pc); 5065 TLB_TX_PRBS_GEN_CFGr_CLR(reg_prbs_gen_cfg); 5066 5067 TLB_TX_PRBS_GEN_CFGr_PRBS_GEN_ENf_SET(reg_prbs_gen_cfg, enable); 5068 PHYMOD_IF_ERR_RETURN (MODIFY_TLB_TX_PRBS_GEN_CFGr(pc, reg_prbs_gen_cfg)); 5069 5070 return PHYMOD_E_NONE; 5071 5072 } /* PRBS_MODE */ 5073 #endif 5074 5075 #ifdef _DV_TB_ 5076 int temod16_prbs_rx_invert_data_set(PHYMOD_ST* pc, int invert_data) /* PRBS_MODE */ 5077 { 5078 TLB_RX_PRBS_CHK_CFGr_t reg_prbs_chk_cfg; 5079 5080 TMOD_DBG_IN_FUNC_INFO(pc); 5081 TLB_RX_PRBS_CHK_CFGr_CLR(reg_prbs_chk_cfg); 5082 5083 TLB_RX_PRBS_CHK_CFGr_PRBS_CHK_INVf_SET(reg_prbs_chk_cfg, invert_data) ; 5084 PHYMOD_IF_ERR_RETURN (MODIFY_TLB_RX_PRBS_CHK_CFGr(pc, reg_prbs_chk_cfg)); 5085 5086 return PHYMOD_E_NONE; 5087 5088 } /* PRBS_MODE */ 5089 #endif 5090 5091 #ifdef _DV_TB_ 5092 int temod16_prbs_rx_check_mode_set(PHYMOD_ST* pc, int check_mode) /* PRBS_MODE */ 5093 { 5094 TLB_RX_PRBS_CHK_CFGr_t reg_prbs_chk_cfg; 5095 5096 TMOD_DBG_IN_FUNC_INFO(pc); 5097 TLB_RX_PRBS_CHK_CFGr_CLR(reg_prbs_chk_cfg); 5098 5099 TLB_RX_PRBS_CHK_CFGr_PRBS_CHK_MODEf_SET(reg_prbs_chk_cfg, check_mode); 5100 PHYMOD_IF_ERR_RETURN (MODIFY_TLB_RX_PRBS_CHK_CFGr(pc, reg_prbs_chk_cfg)); 5101 5102 return PHYMOD_E_NONE; 5103 5104 } /* PRBS_MODE */ 5105 #endif 5106 5107 #ifdef _DV_TB_ 5108 int temod16_prbs_tx_invert_data_set(PHYMOD_ST* pc, int invert_data) /* PRBS_MODE */ 5109 { 5110 TLB_TX_PRBS_GEN_CFGr_t reg_prbs_gen_cfg; 5111 5112 TMOD_DBG_IN_FUNC_INFO(pc); 5113 TLB_TX_PRBS_GEN_CFGr_CLR(reg_prbs_gen_cfg); 5114 5115 TLB_TX_PRBS_GEN_CFGr_PRBS_GEN_INVf_SET(reg_prbs_gen_cfg, invert_data); 5116 PHYMOD_IF_ERR_RETURN(MODIFY_TLB_TX_PRBS_GEN_CFGr(pc, reg_prbs_gen_cfg)); 5117 5118 return PHYMOD_E_NONE; 5119 5120 } /* PRBS_MODE */ 5121 #endif 5122 5123 #ifdef _DV_TB_ 5124 int temod16_prbs_tx_polynomial_set(PHYMOD_ST* pc, prbs_polynomial_type_t prbs_polynomial) /* PRBS_MODE */ 5125 { 5126 TLB_TX_PRBS_GEN_CFGr_t reg_prbs_gen_cfg; 5127 5128 TMOD_DBG_IN_FUNC_INFO(pc); 5129 TLB_TX_PRBS_GEN_CFGr_CLR(reg_prbs_gen_cfg); 5130 5131 TLB_TX_PRBS_GEN_CFGr_PRBS_GEN_MODE_SELf_SET(reg_prbs_gen_cfg, prbs_polynomial); 5132 PHYMOD_IF_ERR_RETURN (MODIFY_TLB_TX_PRBS_GEN_CFGr(pc, reg_prbs_gen_cfg)); 5133 5134 return PHYMOD_E_NONE; 5135 5136 } /* PRBS_MODE */ 5137 #endif 5138 5139 #ifdef _DV_TB_ 5140 int temod16_prbs_rx_polynomial_set(PHYMOD_ST* pc, prbs_polynomial_type_t prbs_polynomial) /* PRBS_MODE */ 5141 { 5142 TLB_RX_PRBS_CHK_CFGr_t reg_prbs_chk_cfg; 5143 5144 TMOD_DBG_IN_FUNC_INFO(pc); 5145 TLB_RX_PRBS_CHK_CFGr_CLR(reg_prbs_chk_cfg); 5146 5147 TLB_RX_PRBS_CHK_CFGr_PRBS_CHK_MODE_SELf_SET(reg_prbs_chk_cfg, prbs_polynomial); 5148 PHYMOD_IF_ERR_RETURN (MODIFY_TLB_RX_PRBS_CHK_CFGr(pc, reg_prbs_chk_cfg)); 5149 5150 return PHYMOD_E_NONE; 5151 5152 } /* PRBS_MODE */ 5153 #endif 5154 5155 5156 int temod16_tx_loopback_get(PHYMOD_ST *pc, uint32_t *enable) /* TX_LOOPBACK_get */ 5157 { 5158 MAIN0_LPBK_CTLr_t loopReg; 5159 TMOD_DBG_IN_FUNC_INFO(pc); 5160 5161 PHYMOD_IF_ERR_RETURN(READ_MAIN0_LPBK_CTLr(pc, &loopReg)); 5162 *enable = MAIN0_LPBK_CTLr_LOCAL_PCS_LOOPBACK_ENABLEf_GET(loopReg); 5163 5164 return PHYMOD_E_NONE; 5165 } 5166 5167 int temod16_update_port_mode(PHYMOD_ST *pc, int *pll_restart) 5168 { 5169 MAIN0_SETUPr_t mode_reg; 5170 int port_mode_sel, port_mode_sel_reg, temp_pll_restart; 5171 uint32_t single_port_mode; 5172 uint32_t first_couple_mode = 0, second_couple_mode = 0; 5173 TMOD_DBG_IN_FUNC_INFO(pc); 5174 5175 port_mode_sel = 0 ; 5176 single_port_mode = 0 ; 5177 temp_pll_restart = 0; 5178 5179 PHYMOD_IF_ERR_RETURN(READ_MAIN0_SETUPr(pc, &mode_reg)); 5180 port_mode_sel_reg = MAIN0_SETUPr_PORT_MODE_SELf_GET(mode_reg); 5181 5182 if (pc->lane_mask == 0xf) { 5183 port_mode_sel = 4; 5184 if ( port_mode_sel_reg != 4) { 5185 temp_pll_restart = 1; 5186 } 5187 } else { 5188 first_couple_mode = ((port_mode_sel_reg == 2) || (port_mode_sel_reg == 3) || (port_mode_sel_reg == 4)); 5189 second_couple_mode = ((port_mode_sel_reg == 1) || (port_mode_sel_reg == 3) || (port_mode_sel_reg == 4)); 5190 switch (pc->lane_mask) { 5191 case 1: 5192 case 2: 5193 first_couple_mode = 0; 5194 break; 5195 case 4: 5196 case 8: 5197 second_couple_mode = 0; 5198 break; 5199 case 3: 5200 first_couple_mode = 1; 5201 break; 5202 case 0xc: 5203 second_couple_mode = 1; 5204 break; 5205 default: 5206 /* dprintf("%-22s: ERROR port_mode_sel=%0d undefined\n", 5207 __func__, port_mode_sel_reg); */ 5208 break ; 5209 } 5210 5211 if (first_couple_mode) { 5212 port_mode_sel =(second_couple_mode)? 3: 2; 5213 } 5214 else if (second_couple_mode) { 5215 port_mode_sel = 1; 5216 } 5217 else{ 5218 port_mode_sel = 0 ; 5219 } 5220 } 5221 5222 *pll_restart = temp_pll_restart; 5223 5224 MAIN0_SETUPr_SINGLE_PORT_MODEf_SET(mode_reg, single_port_mode); 5225 MAIN0_SETUPr_PORT_MODE_SELf_SET(mode_reg, port_mode_sel); 5226 PHYMOD_IF_ERR_RETURN(MODIFY_MAIN0_SETUPr(pc, mode_reg)); 5227 return PHYMOD_E_NONE ; 5228 } 5229 5230 int temod16_tx_lane_control_set(PHYMOD_ST* pc, tx_lane_disable_type_t tx_dis_type) /* TX_LANE_CONTROL */ 5231 { 5232 TX_X4_MISCr_t reg_misc_ctrl; 5233 TMOD_DBG_IN_FUNC_INFO(pc); 5234 5235 TX_X4_MISCr_CLR(reg_misc_ctrl); 5236 5237 switch (tx_dis_type) { 5238 case TEMOD16_TX_LANE_RESET: 5239 TX_X4_MISCr_RSTB_TX_LANEf_SET(reg_misc_ctrl, 0); 5240 PHYMOD_IF_ERR_RETURN (MODIFY_TX_X4_MISCr(pc, reg_misc_ctrl)); 5241 TX_X4_MISCr_CLR(reg_misc_ctrl); 5242 TX_X4_MISCr_RSTB_TX_LANEf_SET(reg_misc_ctrl, 1); 5243 PHYMOD_IF_ERR_RETURN (MODIFY_TX_X4_MISCr(pc, reg_misc_ctrl)); 5244 break; 5245 case TEMOD16_TX_LANE_TRAFFIC_ENABLE: 5246 TX_X4_MISCr_ENABLE_TX_LANEf_SET(reg_misc_ctrl, 1); 5247 PHYMOD_IF_ERR_RETURN (MODIFY_TX_X4_MISCr(pc, reg_misc_ctrl)); 5248 break; 5249 case TEMOD16_TX_LANE_TRAFFIC_DISABLE: 5250 TX_X4_MISCr_ENABLE_TX_LANEf_SET(reg_misc_ctrl, 0); 5251 PHYMOD_IF_ERR_RETURN (MODIFY_TX_X4_MISCr(pc, reg_misc_ctrl)); 5252 break; 5253 case TEMOD16_TX_LANE_RESET_TRAFFIC_ENABLE: 5254 TX_X4_MISCr_RSTB_TX_LANEf_SET(reg_misc_ctrl, 1); 5255 PHYMOD_IF_ERR_RETURN (MODIFY_TX_X4_MISCr(pc, reg_misc_ctrl)); 5256 TX_X4_MISCr_CLR(reg_misc_ctrl); 5257 TX_X4_MISCr_ENABLE_TX_LANEf_SET(reg_misc_ctrl, 1); 5258 PHYMOD_IF_ERR_RETURN (MODIFY_TX_X4_MISCr(pc, reg_misc_ctrl)); 5259 break; 5260 case TEMOD16_TX_LANE_RESET_TRAFFIC_DISABLE: 5261 TX_X4_MISCr_RSTB_TX_LANEf_SET(reg_misc_ctrl, 0); 5262 PHYMOD_IF_ERR_RETURN (MODIFY_TX_X4_MISCr(pc, reg_misc_ctrl)); 5263 TX_X4_MISCr_CLR(reg_misc_ctrl); 5264 TX_X4_MISCr_ENABLE_TX_LANEf_SET(reg_misc_ctrl, 0); 5265 PHYMOD_IF_ERR_RETURN (MODIFY_TX_X4_MISCr(pc, reg_misc_ctrl)); 5266 break; 5267 default: 5268 break; 5269 } 5270 return PHYMOD_E_NONE; 5271 } 5272 5273 int temod16_refclk_set(PHYMOD_ST* pc, phymod_ref_clk_t ref_clock) 5274 { 5275 MAIN0_SETUPr_t reg_setup; 5276 TOP_USER_CTL0r_t dig_top_user_reg; 5277 TMOD_DBG_IN_FUNC_INFO(pc); 5278 5279 MAIN0_SETUPr_CLR(reg_setup); 5280 PHYMOD_IF_ERR_RETURN(READ_MAIN0_SETUPr(pc, ®_setup)); 5281 PHYMOD_IF_ERR_RETURN(READ_TOP_USER_CTL0r(pc, &dig_top_user_reg)); 5282 5283 if (ref_clock == phymodRefClk125Mhz) { 5284 MAIN0_SETUPr_REFCLK_SELf_SET(reg_setup, main0_refClkSelect_clk_125MHz); 5285 TOP_USER_CTL0r_HEARTBEAT_COUNT_1USf_SET(dig_top_user_reg, 0x1f4); 5286 } else { 5287 MAIN0_SETUPr_REFCLK_SELf_SET(reg_setup, main0_refClkSelect_clk_156p25MHz); 5288 TOP_USER_CTL0r_HEARTBEAT_COUNT_1USf_SET(dig_top_user_reg, 0x271); 5289 } 5290 5291 PHYMOD_IF_ERR_RETURN(MODIFY_MAIN0_SETUPr(pc,reg_setup)); 5292 PHYMOD_IF_ERR_RETURN(MODIFY_TOP_USER_CTL0r(pc, dig_top_user_reg)); 5293 5294 return PHYMOD_E_NONE; 5295 } 5296 5297 int temod16_pcs_ilkn_mode_set(PHYMOD_ST* pc) /* INIT_PCS_ILKN */ 5298 { 5299 SC_X4_BYPASSr_t reg_sc_bypass; 5300 5301 TMOD_DBG_IN_FUNC_INFO(pc); 5302 SC_X4_BYPASSr_CLR(reg_sc_bypass); 5303 SC_X4_BYPASSr_SC_BYPASSf_SET(reg_sc_bypass, 1); 5304 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_BYPASSr(pc,reg_sc_bypass)); 5305 5306 return PHYMOD_E_NONE; 5307 } 5308 5309 int temod16_master_port_num_set( PHYMOD_ST *pc, int port_num) 5310 { 5311 MAIN0_SETUPr_t main_reg; 5312 TMOD_DBG_IN_FUNC_INFO(pc); 5313 5314 MAIN0_SETUPr_CLR(main_reg); 5315 MAIN0_SETUPr_MASTER_PORT_NUMf_SET(main_reg, port_num); 5316 PHYMOD_IF_ERR_RETURN(MODIFY_MAIN0_SETUPr(pc, main_reg)); 5317 5318 return PHYMOD_E_NONE; 5319 } 5320 5321 int temod16_cl48_lfrfli_init(PHYMOD_ST* pc) /* AUTONEG timer set*/ 5322 { 5323 TX_X2_CL48_0r_t reg_cl48_ctl ; 5324 TMOD_DBG_IN_FUNC_INFO(pc); 5325 5326 TX_X2_CL48_0r_CLR(reg_cl48_ctl) ; 5327 TX_X2_CL48_0r_CL48_TX_LI_ENABLEf_SET(reg_cl48_ctl,1) ; 5328 TX_X2_CL48_0r_CL48_TX_LF_ENABLEf_SET(reg_cl48_ctl,1) ; 5329 TX_X2_CL48_0r_CL48_TX_RF_ENABLEf_SET(reg_cl48_ctl,1) ; 5330 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X2_CL48_0r(pc, reg_cl48_ctl)); 5331 5332 return PHYMOD_E_NONE; 5333 } 5334 5335 int temod16_mld_am_timers_set(PHYMOD_ST* pc) /*MLD_AM_TIMERS_SET */ 5336 { 5337 TX_X2_MLD_SWP_CNTr_t reg_mld_swap_cnt; 5338 TMOD_DBG_IN_FUNC_INFO(pc); 5339 5340 TX_X2_MLD_SWP_CNTr_CLR(reg_mld_swap_cnt); 5341 5342 TX_X2_MLD_SWP_CNTr_SET(reg_mld_swap_cnt, 0xfffc); 5343 PHYMOD_IF_ERR_RETURN (WRITE_TX_X2_MLD_SWP_CNTr(pc, reg_mld_swap_cnt)); 5344 return PHYMOD_E_NONE; 5345 } 5346 5347 int temod16_cl74_chng_default(PHYMOD_ST* pc) 5348 { 5349 RX_X4_FEC2r_t RX_X4_FEC2reg; 5350 phymod_access_t pa_copy; 5351 int i; 5352 TMOD_DBG_IN_FUNC_INFO(pc); 5353 5354 PHYMOD_MEMCPY(&pa_copy, pc, sizeof(pa_copy)); 5355 RX_X4_FEC2r_CLR(RX_X4_FEC2reg); 5356 5357 for (i = 0; i <4; i++) { 5358 pa_copy.lane_mask = 0x1 << i; 5359 PHYMOD_IF_ERR_RETURN(WRITE_RX_X4_FEC2r(&pa_copy, RX_X4_FEC2reg)); 5360 } 5361 return PHYMOD_E_NONE; 5362 } 5363 5364 int temod16_speed_id_get(PHYMOD_ST* pc, int *speed_id) 5365 { 5366 SC_X4_RSLVD_SPDr_t sc_final_resolved_speed; 5367 TMOD_DBG_IN_FUNC_INFO(pc); 5368 5369 SC_X4_RSLVD_SPDr_CLR(sc_final_resolved_speed); 5370 PHYMOD_IF_ERR_RETURN(READ_SC_X4_RSLVD_SPDr(pc,&sc_final_resolved_speed)); 5371 *speed_id = SC_X4_RSLVD_SPDr_SPEEDf_GET(sc_final_resolved_speed); 5372 5373 return PHYMOD_E_NONE; 5374 } 5375 5376 int temod16_hg_enable_get(PHYMOD_ST* pc, int *enable) 5377 { 5378 TX_X4_ENC0r_t reg_encode; 5379 TMOD_DBG_IN_FUNC_INFO(pc); 5380 5381 TX_X4_ENC0r_CLR(reg_encode); 5382 5383 PHYMOD_IF_ERR_RETURN 5384 (READ_TX_X4_ENC0r(pc, ®_encode)); 5385 *enable = TX_X4_ENC0r_HG2_ENABLEf_GET(reg_encode); 5386 5387 return PHYMOD_E_NONE; 5388 } 5389 5390 int temod16_pll_config_set(const phymod_access_t *pa, temod16_pll_mode_type pll_mode, phymod_ref_clk_t ref_clk) 5391 { 5392 enum merlin16_pll_refclk_enum refclk; 5393 enum merlin16_pll_div_enum pll_cfg; 5394 5395 switch (pll_mode) { 5396 5397 case TEMOD16_PLL_MODE_DIV_54: 5398 pll_cfg = MERLIN16_PLL_DIV_54P4; 5399 break; 5400 case TEMOD16_PLL_MODE_DIV_60: 5401 pll_cfg = MERLIN16_PLL_DIV_60; 5402 break; 5403 case TEMOD16_PLL_MODE_DIV_64: 5404 pll_cfg = MERLIN16_PLL_DIV_64; 5405 break; 5406 case TEMOD16_PLL_MODE_DIV_66: 5407 pll_cfg = MERLIN16_PLL_DIV_66; 5408 break; 5409 case TEMOD16_PLL_MODE_DIV_70: 5410 pll_cfg = MERLIN16_PLL_DIV_70; 5411 break; 5412 case TEMOD16_PLL_MODE_DIV_80: 5413 pll_cfg = MERLIN16_PLL_DIV_80; 5414 break; 5415 case TEMOD16_PLL_MODE_DIV_92: 5416 pll_cfg = MERLIN16_PLL_DIV_92; 5417 break; 5418 default: 5419 pll_cfg = MERLIN16_PLL_DIV_66; 5420 break; 5421 } 5422 5423 switch (ref_clk) { 5424 case phymodRefClk156Mhz: 5425 refclk = MERLIN16_PLL_REFCLK_156P25MHZ; 5426 break; 5427 default: 5428 refclk = MERLIN16_PLL_REFCLK_156P25MHZ; 5429 break; 5430 } 5431 5432 return merlin16_configure_pll_refclk_div(pa, refclk, pll_cfg); 5433 } 5434 5435 int temod16_pll_config_get(const phymod_access_t *pa, temod16_pll_mode_type *pll_mode) 5436 { 5437 uint32_t pll_div; 5438 5439 PHYMOD_IF_ERR_RETURN 5440 (merlin16_INTERNAL_read_pll_div(pa, &pll_div)); 5441 5442 /* merlin16_INTERNAL_read_pll_div() puts one of merlin16_pll_div_enum 5443 * as the returned value in pll_div 5444 */ 5445 switch (pll_div) { 5446 case MERLIN16_PLL_DIV_70: *pll_mode = TEMOD16_PLL_MODE_DIV_70; 5447 break; 5448 case MERLIN16_PLL_DIV_66: *pll_mode = TEMOD16_PLL_MODE_DIV_66; 5449 break; 5450 case MERLIN16_PLL_DIV_64: *pll_mode = TEMOD16_PLL_MODE_DIV_64; 5451 break; 5452 case MERLIN16_PLL_DIV_60: *pll_mode = TEMOD16_PLL_MODE_DIV_60; 5453 break; 5454 case MERLIN16_PLL_DIV_92: *pll_mode = TEMOD16_PLL_MODE_DIV_92; 5455 break; 5456 case MERLIN16_PLL_DIV_80: *pll_mode = TEMOD16_PLL_MODE_DIV_80; 5457 break; 5458 case MERLIN16_PLL_DIV_54P4: *pll_mode = TEMOD16_PLL_MODE_DIV_54; 5459 break; 5460 default: return PHYMOD_E_NONE; 5461 break; 5462 } 5463 5464 return PHYMOD_E_NONE; 5465 } 5466 5467 int temod16_pcs_ilkn_chk(PHYMOD_ST* pc, int *ilkn_set) /* INIT_PCS_ILKN */ 5468 { 5469 ILKN_CTL0r_t ILKN_CONTROL0r_reg; 5470 TMOD_DBG_IN_FUNC_INFO(pc); 5471 5472 PHYMOD_IF_ERR_RETURN(READ_ILKN_CTL0r(pc, &ILKN_CONTROL0r_reg)); 5473 5474 *ilkn_set = ILKN_CTL0r_ILKN_SELf_GET(ILKN_CONTROL0r_reg); 5475 5476 return PHYMOD_E_NONE; 5477 } 5478 5479 int temod16_clause72_control(PHYMOD_ST* sa__, int cl72_en) /* CLAUSE_72_CONTROL */ 5480 { 5481 err_code_t __err; 5482 phymod_access_t pa_copy; 5483 int start_lane = 0, num_lane = 0; 5484 uint32_t enable=0; 5485 5486 PHYMOD_MEMCPY(&pa_copy, sa__, sizeof(pa_copy)); 5487 PHYMOD_IF_ERR_RETURN 5488 (phymod_util_lane_config_get(sa__, &start_lane, &num_lane)); 5489 pa_copy.lane_mask = 0x1 << start_lane; 5490 5491 __err=wr_cl72_ieee_training_enable(cl72_en); if (__err) return(__err); 5492 __err=wr_cl72_ieee_restart_training(cl72_en); if (__err) return(__err); 5493 5494 pa_copy.lane_mask = 0x1 << start_lane; 5495 temod16_disable_get(&pa_copy, &enable); 5496 if (cl72_en & TEMOD16_CL72_CONTROL_NO_TRIGER) { 5497 5498 } else { 5499 if (enable == 0x1) { 5500 PHYMOD_IF_ERR_RETURN (temod16_trigger_speed_change(&pa_copy)); 5501 } 5502 } 5503 5504 return PHYMOD_E_NONE; 5505 } 5506 5507 int temod16_cl37_high_vco_set(PHYMOD_ST* pc, int value) 5508 { 5509 MAIN0_SETUPr_t reg_setup; 5510 5511 MAIN0_SETUPr_CLR(reg_setup); 5512 MAIN0_SETUPr_CL37_HIGH_VCOf_SET(reg_setup, value); 5513 PHYMOD_IF_ERR_RETURN(MODIFY_MAIN0_SETUPr(pc,reg_setup)); 5514 5515 return PHYMOD_E_NONE; 5516 } 5517 5518 int temod16_osdfe_on_lkup_get(PHYMOD_ST* pc, temod16_spd_intfc_type spd_intf, uint32_t* osdfe_on) 5519 { 5520 int speed_id; 5521 5522 temod16_get_mapped_speed(spd_intf, &speed_id); 5523 *osdfe_on = merlin16_sc_pmd_entry[speed_id].osdfe_on; 5524 5525 return PHYMOD_E_NONE; 5526 } 5527 5528 int temod16_scrambling_dis_lkup_get(PHYMOD_ST* pc, temod16_spd_intfc_type spd_intf, uint32_t* scrambling_dis) 5529 { 5530 int speed_id; 5531 5532 temod16_get_mapped_speed(spd_intf, &speed_id); 5533 *scrambling_dis = merlin16_sc_pmd_entry[speed_id].scrambling_dis; 5534 5535 return PHYMOD_E_NONE; 5536 } 5537 5538 int temod16_override_clear(PHYMOD_ST* pc, override_type_t or_type) 5539 { 5540 SC_X4_FLD_OVRR_EN0_TYPEr_t reg_or_en0; 5541 TMOD_DBG_IN_FUNC_INFO(pc); 5542 5543 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(reg_or_en0); 5544 switch (or_type) { 5545 case TEMOD16_OVERRIDE_SCR_MODE: 5546 /*Set the override disable*/ 5547 SC_X4_FLD_OVRR_EN0_TYPEr_SCR_MODE_OENf_SET(reg_or_en0,0); 5548 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc,reg_or_en0)); 5549 break; 5550 case TEMOD16_OVERRIDE_DESCR_MODE: 5551 /*Set the override disable*/ 5552 SC_X4_FLD_OVRR_EN0_TYPEr_DESCRAMBLERMODE_OENf_SET(reg_or_en0,0); 5553 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc,reg_or_en0)); 5554 break; 5555 default: 5556 return PHYMOD_E_UNAVAIL; 5557 } 5558 return PHYMOD_E_NONE; 5559 } 5560 5561 int temod16_set_spd_intf(PHYMOD_ST *pc, temod16_spd_intfc_type spd_intf, int no_trig) 5562 { 5563 SC_X4_CTLr_t xgxs_x4_ctrl; 5564 phymod_access_t pa_copy; 5565 int speed_id = 0, start_lane = 0, num_lane = 0; 5566 TMOD_DBG_IN_FUNC_INFO(pc); 5567 5568 /* need to figure out what's the starting lane */ 5569 PHYMOD_MEMCPY(&pa_copy, pc, sizeof(pa_copy)); 5570 PHYMOD_IF_ERR_RETURN 5571 (phymod_util_lane_config_get(pc, &start_lane, &num_lane)); 5572 pa_copy.lane_mask = 0x1 << start_lane; 5573 5574 PHYMOD_IF_ERR_RETURN(temod16_get_mapped_speed(spd_intf, &speed_id)); 5575 /* write the speed_id into the speed_change register */ 5576 SC_X4_CTLr_CLR(xgxs_x4_ctrl); 5577 SC_X4_CTLr_SW_SPEEDf_SET(xgxs_x4_ctrl, speed_id); 5578 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_CTLr(pc, xgxs_x4_ctrl)); 5579 /*next call the speed_change routine */ 5580 if (no_trig) { 5581 } else { 5582 PHYMOD_IF_ERR_RETURN (temod16_trigger_speed_change(&pa_copy)); 5583 /*check the speed_change_done nit*/ 5584 PHYMOD_IF_ERR_RETURN (_temod16_wait_sc_stats_set(pc)); 5585 } 5586 5587 return PHYMOD_E_NONE; 5588 } 5589 5590 int temod16_rx_squelch_set(PHYMOD_ST *pc, int enable) 5591 { 5592 SIGDET_CTL1r_t sigdet_ctl; 5593 5594 SIGDET_CTL1r_CLR(sigdet_ctl); 5595 PHYMOD_IF_ERR_RETURN(READ_SIGDET_CTL1r(pc, &sigdet_ctl)); 5596 if (enable) { 5597 SIGDET_CTL1r_SIGNAL_DETECT_FRCf_SET(sigdet_ctl, 1); 5598 SIGDET_CTL1r_SIGNAL_DETECT_FRC_VALf_SET(sigdet_ctl, 0); 5599 } else { 5600 SIGDET_CTL1r_SIGNAL_DETECT_FRCf_SET(sigdet_ctl, 0); 5601 SIGDET_CTL1r_SIGNAL_DETECT_FRC_VALf_SET(sigdet_ctl, 0); 5602 } 5603 PHYMOD_IF_ERR_RETURN(MODIFY_SIGDET_CTL1r(pc, sigdet_ctl)); 5604 5605 return PHYMOD_E_NONE; 5606 } 5607 5608 int temod16_rx_squelch_get(PHYMOD_ST *pc, int *val) 5609 { 5610 SIGDET_CTL1r_t sigdet_ctl; 5611 5612 SIGDET_CTL1r_CLR(sigdet_ctl); 5613 PHYMOD_IF_ERR_RETURN(READ_SIGDET_CTL1r(pc, &sigdet_ctl)); 5614 *val = SIGDET_CTL1r_SIGNAL_DETECT_FRCf_GET(sigdet_ctl); 5615 5616 return PHYMOD_E_NONE; 5617 } 5618 5619 int temod16_port_enable_set(PHYMOD_ST *pc, int enable) 5620 { 5621 if (enable) { 5622 PHYMOD_IF_ERR_RETURN(temod16_rx_squelch_set(pc, 0)); 5623 PHYMOD_IF_ERR_RETURN(temod16_tx_squelch_set(pc, 0)); 5624 } else { 5625 PHYMOD_IF_ERR_RETURN(temod16_rx_squelch_set(pc, 1)); 5626 PHYMOD_IF_ERR_RETURN(temod16_tx_squelch_set(pc, 1)); 5627 } 5628 5629 return PHYMOD_E_NONE; 5630 } 5631 5632 int temod16_tx_squelch_set(PHYMOD_ST *pc, int enable) 5633 { 5634 MISC_CTL0r_t tx_misc_ctl; 5635 5636 MISC_CTL0r_CLR(tx_misc_ctl); 5637 PHYMOD_IF_ERR_RETURN(READ_MISC_CTL0r(pc, &tx_misc_ctl)); 5638 MISC_CTL0r_SDK_TX_DISABLEf_SET(tx_misc_ctl, enable); 5639 PHYMOD_IF_ERR_RETURN(MODIFY_MISC_CTL0r(pc, tx_misc_ctl)); 5640 5641 return PHYMOD_E_NONE; 5642 } 5643 5644 int temod16_tx_squelch_get(PHYMOD_ST *pc, int *val) 5645 { 5646 MISC_CTL0r_t tx_misc_ctl; 5647 5648 MISC_CTL0r_CLR(tx_misc_ctl); 5649 PHYMOD_IF_ERR_RETURN(READ_MISC_CTL0r(pc, &tx_misc_ctl)); 5650 *val = MISC_CTL0r_SDK_TX_DISABLEf_GET(tx_misc_ctl); 5651 5652 return PHYMOD_E_NONE; 5653 } 5654 5655 int temod16_tx_lane_control_get(PHYMOD_ST* pc, int *reset, int *enable) /* TX_LANE_CONTROL_GET */ 5656 { 5657 TX_X4_MISCr_t reg_misc_ctrl; 5658 5659 TMOD_DBG_IN_FUNC_INFO(pc); 5660 TX_X4_MISCr_CLR(reg_misc_ctrl); 5661 5662 PHYMOD_IF_ERR_RETURN (READ_TX_X4_MISCr(pc, ®_misc_ctrl)); 5663 *reset = TX_X4_MISCr_RSTB_TX_LANEf_GET(reg_misc_ctrl); 5664 *enable = TX_X4_MISCr_ENABLE_TX_LANEf_GET(reg_misc_ctrl); 5665 5666 return PHYMOD_E_NONE; 5667 } 5668 5669 int temod16_get_pcs_latched_link_status(PHYMOD_ST* pc, uint32_t *link) 5670 { 5671 RX_X4_PCS_LIVE_STSr_t reg_pcs_live_sts; 5672 RX_X4_PCS_LATCH_STS0r_t latched_sts ; 5673 int latched_val ; 5674 5675 TMOD_DBG_IN_FUNC_INFO(pc); 5676 RX_X4_PCS_LIVE_STSr_CLR(reg_pcs_live_sts); 5677 RX_X4_PCS_LATCH_STS0r_CLR(latched_sts) ; 5678 5679 PHYMOD_IF_ERR_RETURN (READ_RX_X4_PCS_LIVE_STSr(pc, ®_pcs_live_sts)); 5680 PHYMOD_IF_ERR_RETURN (READ_RX_X4_PCS_LATCH_STS0r(pc, &latched_sts)) ; 5681 latched_val = RX_X4_PCS_LATCH_STS0r_LINK_STATUS_LLf_GET(latched_sts) ; 5682 if (latched_val) { 5683 *link = 0 ; 5684 } else { 5685 *link = RX_X4_PCS_LIVE_STSr_LINK_STATUSf_GET(reg_pcs_live_sts); 5686 } 5687 5688 return PHYMOD_E_NONE; 5689 } 5690 5691 /* PMD per lane reset get */ 5692 int temod16_pmd_x4_reset_get(PHYMOD_ST* pc, int *is_in_reset) 5693 { 5694 PMD_X4_CTLr_t reg_pmd_x4_ctrl; 5695 5696 TMOD_DBG_IN_FUNC_INFO(pc); 5697 PMD_X4_CTLr_CLR(reg_pmd_x4_ctrl); 5698 PHYMOD_IF_ERR_RETURN(READ_PMD_X4_CTLr(pc, ®_pmd_x4_ctrl)); 5699 5700 if (PMD_X4_CTLr_LN_TX_H_RSTBf_GET(reg_pmd_x4_ctrl) && 5701 PMD_X4_CTLr_LN_RX_H_RSTBf_GET(reg_pmd_x4_ctrl) && 5702 PMD_X4_CTLr_LN_TX_DP_H_RSTBf_GET(reg_pmd_x4_ctrl) && 5703 PMD_X4_CTLr_LN_RX_DP_H_RSTBf_GET(reg_pmd_x4_ctrl)) { 5704 *is_in_reset = 0 ; 5705 } else { 5706 *is_in_reset = 1 ; 5707 } 5708 5709 return PHYMOD_E_NONE; 5710 } 5711 /** 5712 @brief Get the plldiv from lookup table 5713 @param pc handle to current TSCE context (#PHYMOD_ST) 5714 @param spd_intf speed as specified by enum #temod_spd_intfc_type 5715 @param plldiv Receives the pll divider value 5716 @param speed_vec Receives the speed id. 5717 @returns The value PHYMOD_E_NONE upon successful completion 5718 @details Get the plldiv from lookup table 5719 */ 5720 int temod16_plldiv_lkup_get(PHYMOD_ST* pc, temod16_spd_intfc_type spd_intf, phymod_ref_clk_t ref_clk, uint32_t *plldiv, uint16_t *speed_vec) 5721 { 5722 int speed_id; 5723 5724 temod16_get_mapped_speed(spd_intf, &speed_id); 5725 if (ref_clk == phymodRefClk156Mhz) { 5726 *plldiv = merlin16_sc_pmd_entry[speed_id].pll_mode; 5727 } 5728 *speed_vec = speed_id ; 5729 5730 return PHYMOD_E_NONE; 5731 } 5732 5733 int temod16_pll_reset_enable_set(PHYMOD_ST *pa , int enable) 5734 { 5735 MAIN0_SETUPr_t main_reg; 5736 5737 MAIN0_SETUPr_CLR(main_reg); 5738 MAIN0_SETUPr_PLL_RESET_ENf_SET(main_reg, enable); 5739 MODIFY_MAIN0_SETUPr(pa, main_reg); 5740 return PHYMOD_E_NONE; 5741 } 5742 5743 int temod16_disable_get(PHYMOD_ST *pa, uint32_t *enable ) 5744 { 5745 SC_X4_CTLr_t reg_sc_ctrl; 5746 5747 TMOD_DBG_IN_FUNC_INFO(pa); 5748 SC_X4_CTLr_CLR(reg_sc_ctrl); 5749 5750 PHYMOD_IF_ERR_RETURN(READ_SC_X4_CTLr(pa,®_sc_ctrl)); 5751 *enable = SC_X4_CTLr_SW_SPEED_CHANGEf_GET(reg_sc_ctrl); 5752 5753 return PHYMOD_E_NONE; 5754 } 5755 5756 /** 5757 @brief EEE Control Set 5758 @param pc handle to current TSCE context (#PHYMOD_ST) 5759 @param enable enable or disable EEE control 5760 @returns The value PHYMOD_E_NONE upon successful completion 5761 @details EEE Control 5762 enable =1 : Allow LPI pass through. i.e. dont convert LPI. 5763 enable =0 : Convert LPI to idle. So MAC will not see it. 5764 5765 */ 5766 int temod16_eee_control_set(PHYMOD_ST* pc, uint32_t enable) 5767 { 5768 RX_X4_PCS_CTL0r_t reg_pcs_ctrl0; 5769 5770 TMOD_DBG_IN_FUNC_INFO(pc); 5771 RX_X4_PCS_CTL0r_CLR(reg_pcs_ctrl0); 5772 READ_RX_X4_PCS_CTL0r(pc, ®_pcs_ctrl0); 5773 5774 RX_X4_PCS_CTL0r_LPI_ENABLEf_SET(reg_pcs_ctrl0, enable & 0x1); 5775 PHYMOD_IF_ERR_RETURN (MODIFY_RX_X4_PCS_CTL0r(pc, reg_pcs_ctrl0)); 5776 return PHYMOD_E_NONE; 5777 } 5778 5779 /** 5780 @brief EEE Control Get 5781 @param pc handle to current TSCE context (#PHYMOD_ST) 5782 @param enable handle to pass back EEE control 5783 @returns The value PHYMOD_E_NONE upon successful completion 5784 @details EEE Control 5785 enable =1 : Allow LPI pass through. i.e. dont convert LPI. 5786 enable =0 : Convert LPI to idle. So MAC will not see it. 5787 5788 */ 5789 int temod16_eee_control_get(PHYMOD_ST* pc, uint32_t *enable) 5790 { 5791 RX_X4_PCS_CTL0r_t reg_pcs_ctrl0; 5792 5793 TMOD_DBG_IN_FUNC_INFO(pc); 5794 RX_X4_PCS_CTL0r_CLR(reg_pcs_ctrl0); 5795 5796 PHYMOD_IF_ERR_RETURN (READ_RX_X4_PCS_CTL0r(pc, ®_pcs_ctrl0)); 5797 *enable = RX_X4_PCS_CTL0r_LPI_ENABLEf_GET(reg_pcs_ctrl0); 5798 return PHYMOD_E_NONE; 5799 } 5800 5801 STATIC 5802 int _temod16_rx_phy_lane_get(PHYMOD_ST *pc, int rx_logical_lane, int* rx_phy_lane) 5803 { 5804 MAIN0_LN_SWPr_t reg_lane_swap; 5805 phymod_access_t pa_copy; 5806 5807 PHYMOD_MEMCPY(&pa_copy, pc, sizeof(pa_copy)); 5808 5809 /*always use lane 0 copy since register is single copy */ 5810 pa_copy.lane_mask = 0x1; 5811 5812 PHYMOD_IF_ERR_RETURN 5813 (READ_MAIN0_LN_SWPr(&pa_copy, ®_lane_swap)); 5814 5815 switch (rx_logical_lane) { 5816 case 0: 5817 *rx_phy_lane = MAIN0_LN_SWPr_LOG0_TO_PHY_RX_LNSWAP_SELf_GET(reg_lane_swap); 5818 break; 5819 case 1: 5820 *rx_phy_lane = MAIN0_LN_SWPr_LOG1_TO_PHY_RX_LNSWAP_SELf_GET(reg_lane_swap); 5821 break; 5822 case 2: 5823 *rx_phy_lane = MAIN0_LN_SWPr_LOG2_TO_PHY_RX_LNSWAP_SELf_GET(reg_lane_swap); 5824 break; 5825 case 3: 5826 *rx_phy_lane = MAIN0_LN_SWPr_LOG3_TO_PHY_RX_LNSWAP_SELf_GET(reg_lane_swap); 5827 break; 5828 default: 5829 return PHYMOD_E_PARAM; 5830 } 5831 5832 return PHYMOD_E_NONE; 5833 } 5834 5835 int temod16_synce_stg0_mode_set(PHYMOD_ST *pc, int mode) 5836 { 5837 int start_lane = 0, num_lane = 0, phy_lane = 0; 5838 MAIN0_SYNCE_CTL_STAGE0r_t reg_main0_synce_ctl_stage0; 5839 5840 PHYMOD_IF_ERR_RETURN 5841 (phymod_util_lane_config_get(pc, &start_lane, &num_lane)); 5842 5843 PHYMOD_IF_ERR_RETURN 5844 (_temod16_rx_phy_lane_get(pc, start_lane, &phy_lane)); 5845 5846 MAIN0_SYNCE_CTL_STAGE0r_CLR(reg_main0_synce_ctl_stage0); 5847 PHYMOD_IF_ERR_RETURN(READ_MAIN0_SYNCE_CTL_STAGE0r(pc, ®_main0_synce_ctl_stage0)); 5848 5849 switch(phy_lane) { 5850 case 0: 5851 MAIN0_SYNCE_CTL_STAGE0r_SYNCE_STAGE0_MODE_PHY_LN0f_SET( 5852 reg_main0_synce_ctl_stage0, mode); 5853 break; 5854 case 1: 5855 MAIN0_SYNCE_CTL_STAGE0r_SYNCE_STAGE0_MODE_PHY_LN1f_SET( 5856 reg_main0_synce_ctl_stage0, mode); 5857 break; 5858 case 2: 5859 MAIN0_SYNCE_CTL_STAGE0r_SYNCE_STAGE0_MODE_PHY_LN2f_SET( 5860 reg_main0_synce_ctl_stage0, mode); 5861 break; 5862 case 3: 5863 MAIN0_SYNCE_CTL_STAGE0r_SYNCE_STAGE0_MODE_PHY_LN3f_SET( 5864 reg_main0_synce_ctl_stage0, mode); 5865 break; 5866 default: 5867 return PHYMOD_E_PARAM; 5868 } 5869 5870 PHYMOD_IF_ERR_RETURN(MODIFY_MAIN0_SYNCE_CTL_STAGE0r(pc, reg_main0_synce_ctl_stage0)); 5871 5872 return PHYMOD_E_NONE; 5873 } 5874 5875 int temod16_synce_stg1_mode_set(PHYMOD_ST *pc, int mode) 5876 { 5877 int start_lane = 0, num_lane = 0, phy_lane = 0; 5878 MAIN0_SYNCE_CTLr_t reg_main0_synce_ctl; 5879 5880 PHYMOD_IF_ERR_RETURN 5881 (phymod_util_lane_config_get(pc, &start_lane, &num_lane)); 5882 5883 PHYMOD_IF_ERR_RETURN 5884 (_temod16_rx_phy_lane_get(pc, start_lane, &phy_lane)); 5885 5886 MAIN0_SYNCE_CTLr_CLR(reg_main0_synce_ctl); 5887 PHYMOD_IF_ERR_RETURN(READ_MAIN0_SYNCE_CTLr(pc, ®_main0_synce_ctl)); 5888 5889 switch(phy_lane) { 5890 case 0: 5891 MAIN0_SYNCE_CTLr_SYNCE_MODE_PHY_LN0f_SET(reg_main0_synce_ctl, mode); 5892 break; 5893 case 1: 5894 MAIN0_SYNCE_CTLr_SYNCE_MODE_PHY_LN1f_SET(reg_main0_synce_ctl, mode); 5895 break; 5896 case 2: 5897 MAIN0_SYNCE_CTLr_SYNCE_MODE_PHY_LN2f_SET(reg_main0_synce_ctl, mode); 5898 break; 5899 case 3: 5900 MAIN0_SYNCE_CTLr_SYNCE_MODE_PHY_LN3f_SET(reg_main0_synce_ctl, mode); 5901 break; 5902 default: 5903 return PHYMOD_E_PARAM; 5904 } 5905 5906 PHYMOD_IF_ERR_RETURN(MODIFY_MAIN0_SYNCE_CTLr(pc, reg_main0_synce_ctl)); 5907 5908 return PHYMOD_E_NONE; 5909 } 5910 5911 int temod16_synce_clk_ctrl_set(PHYMOD_ST *pc, uint32_t val) 5912 { 5913 int start_lane = 0, num_lane = 0, phy_lane = 0; 5914 phymod_access_t pa_copy; 5915 RX_X4_SYNCE_CTLr_t reg_rx_x4_synce_ctl; 5916 5917 PHYMOD_IF_ERR_RETURN 5918 (phymod_util_lane_config_get(pc, &start_lane, &num_lane)); 5919 5920 PHYMOD_IF_ERR_RETURN 5921 (_temod16_rx_phy_lane_get(pc, start_lane, &phy_lane)); 5922 5923 PHYMOD_MEMCPY(&pa_copy, pc, sizeof(pa_copy)); 5924 pa_copy.lane_mask = 0x1 << phy_lane; 5925 5926 RX_X4_SYNCE_CTLr_CLR(reg_rx_x4_synce_ctl); 5927 RX_X4_SYNCE_CTLr_SET(reg_rx_x4_synce_ctl, val); 5928 PHYMOD_IF_ERR_RETURN(WRITE_RX_X4_SYNCE_CTLr(&pa_copy, reg_rx_x4_synce_ctl)); 5929 5930 return PHYMOD_E_NONE; 5931 } 5932 5933 int temod16_synce_stg0_mode_get(PHYMOD_ST *pc, int *mode) 5934 { 5935 int start_lane = 0, num_lane = 0, phy_lane = 0; 5936 MAIN0_SYNCE_CTL_STAGE0r_t reg_main0_synce_ctl_stage0; 5937 5938 PHYMOD_IF_ERR_RETURN 5939 (phymod_util_lane_config_get(pc, &start_lane, &num_lane)); 5940 5941 PHYMOD_IF_ERR_RETURN 5942 (_temod16_rx_phy_lane_get(pc, start_lane, &phy_lane)); 5943 5944 MAIN0_SYNCE_CTL_STAGE0r_CLR(reg_main0_synce_ctl_stage0); 5945 PHYMOD_IF_ERR_RETURN(READ_MAIN0_SYNCE_CTL_STAGE0r(pc, ®_main0_synce_ctl_stage0)); 5946 5947 switch(phy_lane) { 5948 case 0: 5949 *mode = MAIN0_SYNCE_CTL_STAGE0r_SYNCE_STAGE0_MODE_PHY_LN0f_GET( 5950 reg_main0_synce_ctl_stage0); 5951 break; 5952 case 1: 5953 *mode = MAIN0_SYNCE_CTL_STAGE0r_SYNCE_STAGE0_MODE_PHY_LN1f_GET( 5954 reg_main0_synce_ctl_stage0); 5955 break; 5956 case 2: 5957 *mode = MAIN0_SYNCE_CTL_STAGE0r_SYNCE_STAGE0_MODE_PHY_LN2f_GET( 5958 reg_main0_synce_ctl_stage0); 5959 break; 5960 case 3: 5961 *mode = MAIN0_SYNCE_CTL_STAGE0r_SYNCE_STAGE0_MODE_PHY_LN3f_GET( 5962 reg_main0_synce_ctl_stage0); 5963 break; 5964 default: 5965 return PHYMOD_E_PARAM; 5966 } 5967 5968 return PHYMOD_E_NONE; 5969 } 5970 5971 int temod16_synce_stg1_mode_get(PHYMOD_ST *pc, int *mode) 5972 { 5973 int start_lane = 0, num_lane = 0, phy_lane = 0; 5974 MAIN0_SYNCE_CTLr_t reg_main0_synce_ctl; 5975 5976 PHYMOD_IF_ERR_RETURN 5977 (phymod_util_lane_config_get(pc, &start_lane, &num_lane)); 5978 5979 PHYMOD_IF_ERR_RETURN 5980 (_temod16_rx_phy_lane_get(pc, start_lane, &phy_lane)); 5981 5982 MAIN0_SYNCE_CTLr_CLR(reg_main0_synce_ctl); 5983 PHYMOD_IF_ERR_RETURN(READ_MAIN0_SYNCE_CTLr(pc, ®_main0_synce_ctl)); 5984 5985 switch(phy_lane) { 5986 case 0: 5987 *mode = MAIN0_SYNCE_CTLr_SYNCE_MODE_PHY_LN0f_GET(reg_main0_synce_ctl); 5988 break; 5989 case 1: 5990 *mode = MAIN0_SYNCE_CTLr_SYNCE_MODE_PHY_LN1f_GET(reg_main0_synce_ctl); 5991 break; 5992 case 2: 5993 *mode = MAIN0_SYNCE_CTLr_SYNCE_MODE_PHY_LN2f_GET(reg_main0_synce_ctl); 5994 break; 5995 case 3: 5996 *mode = MAIN0_SYNCE_CTLr_SYNCE_MODE_PHY_LN3f_GET(reg_main0_synce_ctl); 5997 break; 5998 default: 5999 return PHYMOD_E_PARAM; 6000 } 6001 6002 return PHYMOD_E_NONE; 6003 } 6004 6005 int temod16_synce_clk_ctrl_get(PHYMOD_ST *pc, uint32_t *val) 6006 { 6007 int start_lane = 0, num_lane = 0, phy_lane = 0; 6008 phymod_access_t pa_copy; 6009 RX_X4_SYNCE_CTLr_t reg_rx_x4_synce_ctl; 6010 6011 PHYMOD_IF_ERR_RETURN 6012 (phymod_util_lane_config_get(pc, &start_lane, &num_lane)); 6013 6014 PHYMOD_IF_ERR_RETURN 6015 (_temod16_rx_phy_lane_get(pc, start_lane, &phy_lane)); 6016 6017 PHYMOD_MEMCPY(&pa_copy, pc, sizeof(pa_copy)); 6018 pa_copy.lane_mask = 0x1 << phy_lane; 6019 6020 RX_X4_SYNCE_CTLr_CLR(reg_rx_x4_synce_ctl); 6021 PHYMOD_IF_ERR_RETURN(READ_RX_X4_SYNCE_CTLr(&pa_copy, ®_rx_x4_synce_ctl)); 6022 6023 *val = RX_X4_SYNCE_CTLr_GET(reg_rx_x4_synce_ctl); 6024 6025 return PHYMOD_E_NONE; 6026 } 6027 6028 #ifdef _SDK_TEMOD16_ 6029 int temod16_pll_sequencer_control(PHYMOD_ST *pa, int enable) { return 0; } 6030 int temod16_firmware_load(PHYMOD_ST *pa) { return 0; } 6031 /* int temod16_get_ht_entries ( PHYMOD_ST *pa,, sc_table_entry_t *exp_entry) { return 0; } */ 6032 int temod16_osmode_set(PHYMOD_ST *pa, int pmd_os_mode, int override_enable) { return 0; } 6033 int temod16_pcs_lane_swap_get(PHYMOD_ST *pa, uint32_t *tx_rx_swap) { return 0; } 6034 int temod16_pll_lock_wait(PHYMOD_ST *pc, int timeOutValue) { return 0; } 6035 int temod16_pll_mode_set(PHYMOD_ST *pa, int pll_mode) { return 0; } 6036 int temod16_pmd_lane_swap_tx_get(PHYMOD_ST *pa, uint32_t *tx_swap) { return 0; } 6037 int temod16_rx_lane_control(PHYMOD_ST *pa, int enable) { return 0; } 6038 int temod16_tx_lane_disable_get(PHYMOD_ST *pa, uint32_t *enable) { return 0; } 6039 int temod16_tx_lane_disable_set(PHYMOD_ST *pa, uint32_t *enable) { return 0; } 6040 int temod16_tx_pi_control_get(PHYMOD_ST *pa, uint32_t *value) { return 0; } 6041 int temod16_update_port_mode_select(PHYMOD_ST *pa, int *pll_restart) { return 0; } 6042 int _temod16_trigger_speed_change(PHYMOD_ST *pa) { return 0 ; } 6043 int temod16_get_ht_entries(int speed, sc_table_entry_t *exp_entry) { return 0; } 6044 #endif 6045 6046 int temod16_autoneg_get(PHYMOD_ST* pc, int* an_enabled, int* an_complete) { return 0; } 6047 6048