te16PMDRegEnums.h (380281B)
1 /*************************************************************************** 2 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 3 * 4 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 5 * 6 * 7 * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE 8 * AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR 9 * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT. 10 * 11 * $brcm_Workfile: $ 12 * $brcm_Revision: $ 13 * $brcm_Date: $ 14 * 15 * Module Description: 16 * DO NOT EDIT THIS FILE DIRECTLY 17 * 18 * This module was generated magically with RDB from a source description 19 * file. You must edit the source file for changes to be made to this file. 20 * 21 * 22 * Date: Generated on Thu Feb 13 19:01:25 2014 23 * MD5 Checksum 3ce209c9ee2a4cae2cd897291b668394 24 * 25 * Compiled with: RDB Utility 5.0 26 * RDB Parser 3.0 27 * rdb2macro.pm 4.0 28 * Perl Interpreter 5.008008 29 * Operating System linux 30 * 31 * Spec Versions: ams_com 1 32 * ams_rx 1 33 * ams_tx 1 34 * ckrst_ctrl 1 35 * cl72_ieee_rx 1 36 * cl72_ieee_tx 1 37 * cl72_user_rx 1 38 * cl72_user_tx_pmd 1 39 * dig_com_tsc 1 40 * dsc_a 1 41 * dsc_b 1 42 * dsc_c 1 43 * dsc_d 1 44 * dsc_e 1 45 * mdio_blk_addr 1 46 * mdio_cl22_ieee_com 1 47 * mdio_mmdsel_aer_com 1 48 * micro_a 1 49 * micro_b 1 50 * patt_gen 1 51 * pll_cal_com 1 52 * sigdet 1 53 * tlb_rx 1 54 * tlb_tx 1 55 * tx_fed_pmd 1 56 * tx_pi 1 57 * txcom_pmd 1 58 * 59 * RDB Files: /projects/TSC_ext6/udayc/EA_Mar_26/tsce/dv/common/temod16/Eagle_rdb/eagle_top_tsc.rdb 60 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/dv/common/temod16/Eagle_rdb/tx_pi.rdb 61 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/dv/common/temod16/Eagle_rdb/dig_com_tsc.rdb 62 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/dv/common/temod16/Eagle_rdb/tlb_tx.rdb 63 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/dv/common/temod16/Eagle_rdb/tlb_rx.rdb 64 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/dv/common/temod16/Eagle_rdb/patt_gen.rdb 65 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/dv/common/temod16/Eagle_rdb/cl72_user_rx_regs.rdb 66 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/dv/common/temod16/Eagle_rdb/cl72_user_tx_regs_pmd.rdb 67 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/dv/common/temod16/Eagle_rdb/cl72_ieee_tx_regs.rdb 68 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/dv/common/temod16/Eagle_rdb/cl72_ieee_rx_regs.rdb 69 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/dv/common/temod16/Eagle_rdb/txcom_regs_pmd.rdb 70 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/dv/common/temod16/Eagle_rdb/ams_com.rdb 71 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/dv/common/temod16/Eagle_rdb/pll_cal_com.rdb 72 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/dv/common/temod16/Eagle_rdb/ams_tx.rdb 73 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/dv/common/temod16/Eagle_rdb/tx_fed_regs_pmd.rdb 74 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/dv/common/temod16/Eagle_rdb/ams_rx.rdb 75 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/dv/common/temod16/Eagle_rdb/sigdet.rdb 76 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/dv/common/temod16/Eagle_rdb/dsc_a.rdb 77 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/dv/common/temod16/Eagle_rdb/dsc_b.rdb 78 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/dv/common/temod16/Eagle_rdb/dsc_c.rdb 79 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/dv/common/temod16/Eagle_rdb/dsc_d.rdb 80 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/dv/common/temod16/Eagle_rdb/dsc_e.rdb 81 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/dv/common/temod16/Eagle_rdb/ckrst_ctrl.rdb 82 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/dv/common/temod16/Eagle_rdb/mdio_mmdsel_aer_com.rdb 83 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/dv/common/temod16/Eagle_rdb/mdio_blk_addr.rdb 84 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/dv/common/temod16/Eagle_rdb/mdio_cl22_ieee_com_html.rdb 85 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/dv/common/temod16/Eagle_rdb/micro_a_regs.rdb 86 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/dv/common/temod16/Eagle_rdb/micro_b_regs.rdb 87 * 88 * Revision History: 89 * 90 * $brcm_Log: $ 91 */ 92 93 #ifndef TEPMDREGENUMS_TMP__ 94 #define TEPMDREGENUMS_TMP__ 95 96 /** 97 * m = memory, c = core, r = register, f = field, d = data. 98 */ 99 #if !defined(GET_FIELD) && !defined(SET_FIELD) 100 #define BRCM_ALIGN(c,r,f) c##_##r##_##f##_ALIGN 101 #define BRCM_BITS(c,r,f) c##_##r##_##f##_BITS 102 #define BRCM_MASK(c,r,f) c##_##r##_##f##_MASK 103 #define BRCM_SHIFT(c,r,f) c##_##r##_##f##_SHIFT 104 105 #define GET_FIELD(m,c,r,f) \ 106 ((((m) & BRCM_MASK(c,r,f)) >> BRCM_SHIFT(c,r,f)) << BRCM_ALIGN(c,r,f)) 107 108 #define SET_FIELD(m,c,r,f,d) \ 109 ((m) = (((m) & ~BRCM_MASK(c,r,f)) | ((((d) >> BRCM_ALIGN(c,r,f)) << \ 110 BRCM_SHIFT(c,r,f)) & BRCM_MASK(c,r,f))) \ 111 ) 112 113 #define SET_TYPE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##d) 114 #define SET_NAME_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##r##_##f##_##d) 115 #define SET_VALUE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,d) 116 117 #endif /* GET & SET */ 118 119 /**************************************************************************** 120 * Core Enums. 121 */ 122 /**************************************************************************** 123 * eagle_tsc_mdio_ieee_MDIO_CL22_IEEE_COM 124 */ 125 126 127 /**************************************************************************** 128 * eagle_tsc_mdio_ieee_MDIO_CL22_IEEE_COM 129 */ 130 /**************************************************************************** 131 * MDIO_CL22_IEEE_COM :: ACC_CTRL 132 */ 133 /* MDIO_CL22_IEEE_COM :: ACC_CTRL :: mdio_function [15:14] */ 134 #define MDIO_CL22_IEEE_COM_ACC_CTRL_MDIO_FUNCTION_MASK 0xc000 135 #define MDIO_CL22_IEEE_COM_ACC_CTRL_MDIO_FUNCTION_ALIGN 0 136 #define MDIO_CL22_IEEE_COM_ACC_CTRL_MDIO_FUNCTION_BITS 2 137 #define MDIO_CL22_IEEE_COM_ACC_CTRL_MDIO_FUNCTION_SHIFT 14 138 139 /* MDIO_CL22_IEEE_COM :: ACC_CTRL :: reserved0 [13:05] */ 140 #define MDIO_CL22_IEEE_COM_ACC_CTRL_RESERVED0_MASK 0x3fe0 141 #define MDIO_CL22_IEEE_COM_ACC_CTRL_RESERVED0_ALIGN 0 142 #define MDIO_CL22_IEEE_COM_ACC_CTRL_RESERVED0_BITS 9 143 #define MDIO_CL22_IEEE_COM_ACC_CTRL_RESERVED0_SHIFT 5 144 145 /* MDIO_CL22_IEEE_COM :: ACC_CTRL :: mdio_devad [04:00] */ 146 #define MDIO_CL22_IEEE_COM_ACC_CTRL_MDIO_DEVAD_MASK 0x001f 147 #define MDIO_CL22_IEEE_COM_ACC_CTRL_MDIO_DEVAD_ALIGN 0 148 #define MDIO_CL22_IEEE_COM_ACC_CTRL_MDIO_DEVAD_BITS 5 149 #define MDIO_CL22_IEEE_COM_ACC_CTRL_MDIO_DEVAD_SHIFT 0 150 151 152 /**************************************************************************** 153 * MDIO_CL22_IEEE_COM :: ACC_ADDR_DATA 154 */ 155 /* MDIO_CL22_IEEE_COM :: ACC_ADDR_DATA :: mdio_addr_data [15:00] */ 156 #define MDIO_CL22_IEEE_COM_ACC_ADDR_DATA_MDIO_ADDR_DATA_MASK 0xffff 157 #define MDIO_CL22_IEEE_COM_ACC_ADDR_DATA_MDIO_ADDR_DATA_ALIGN 0 158 #define MDIO_CL22_IEEE_COM_ACC_ADDR_DATA_MDIO_ADDR_DATA_BITS 16 159 #define MDIO_CL22_IEEE_COM_ACC_ADDR_DATA_MDIO_ADDR_DATA_SHIFT 0 160 161 162 /**************************************************************************** 163 * eagle_tsc_cl72b_ieee_blk_CL72_IEEE_TX 164 */ 165 /**************************************************************************** 166 * CL72_IEEE_TX :: BASE_R_PMD_CONTROL_REGISTER_150 167 */ 168 /* CL72_IEEE_TX :: BASE_R_PMD_CONTROL_REGISTER_150 :: reserved0 [15:02] */ 169 #define CL72_IEEE_TX_BASE_R_PMD_CONTROL_REGISTER_150_RESERVED0_MASK 0xfffc 170 #define CL72_IEEE_TX_BASE_R_PMD_CONTROL_REGISTER_150_RESERVED0_ALIGN 0 171 #define CL72_IEEE_TX_BASE_R_PMD_CONTROL_REGISTER_150_RESERVED0_BITS 14 172 #define CL72_IEEE_TX_BASE_R_PMD_CONTROL_REGISTER_150_RESERVED0_SHIFT 2 173 174 /* CL72_IEEE_TX :: BASE_R_PMD_CONTROL_REGISTER_150 :: cl72_ieee_training_enable [01:01] */ 175 #define CL72_IEEE_TX_BASE_R_PMD_CONTROL_REGISTER_150_CL72_IEEE_TRAINING_ENABLE_MASK 0x0002 176 #define CL72_IEEE_TX_BASE_R_PMD_CONTROL_REGISTER_150_CL72_IEEE_TRAINING_ENABLE_ALIGN 0 177 #define CL72_IEEE_TX_BASE_R_PMD_CONTROL_REGISTER_150_CL72_IEEE_TRAINING_ENABLE_BITS 1 178 #define CL72_IEEE_TX_BASE_R_PMD_CONTROL_REGISTER_150_CL72_IEEE_TRAINING_ENABLE_SHIFT 1 179 180 /* CL72_IEEE_TX :: BASE_R_PMD_CONTROL_REGISTER_150 :: cl72_ieee_restart_training [00:00] */ 181 #define CL72_IEEE_TX_BASE_R_PMD_CONTROL_REGISTER_150_CL72_IEEE_RESTART_TRAINING_MASK 0x0001 182 #define CL72_IEEE_TX_BASE_R_PMD_CONTROL_REGISTER_150_CL72_IEEE_RESTART_TRAINING_ALIGN 0 183 #define CL72_IEEE_TX_BASE_R_PMD_CONTROL_REGISTER_150_CL72_IEEE_RESTART_TRAINING_BITS 1 184 #define CL72_IEEE_TX_BASE_R_PMD_CONTROL_REGISTER_150_CL72_IEEE_RESTART_TRAINING_SHIFT 0 185 186 187 /**************************************************************************** 188 * CL72_IEEE_TX :: BASE_R_PMD_STATUS_REGISTER_151 189 */ 190 /* CL72_IEEE_TX :: BASE_R_PMD_STATUS_REGISTER_151 :: reserved0 [15:04] */ 191 #define CL72_IEEE_TX_BASE_R_PMD_STATUS_REGISTER_151_RESERVED0_MASK 0xfff0 192 #define CL72_IEEE_TX_BASE_R_PMD_STATUS_REGISTER_151_RESERVED0_ALIGN 0 193 #define CL72_IEEE_TX_BASE_R_PMD_STATUS_REGISTER_151_RESERVED0_BITS 12 194 #define CL72_IEEE_TX_BASE_R_PMD_STATUS_REGISTER_151_RESERVED0_SHIFT 4 195 196 /* CL72_IEEE_TX :: BASE_R_PMD_STATUS_REGISTER_151 :: cl72_ieee_training_failure [03:03] */ 197 #define CL72_IEEE_TX_BASE_R_PMD_STATUS_REGISTER_151_CL72_IEEE_TRAINING_FAILURE_MASK 0x0008 198 #define CL72_IEEE_TX_BASE_R_PMD_STATUS_REGISTER_151_CL72_IEEE_TRAINING_FAILURE_ALIGN 0 199 #define CL72_IEEE_TX_BASE_R_PMD_STATUS_REGISTER_151_CL72_IEEE_TRAINING_FAILURE_BITS 1 200 #define CL72_IEEE_TX_BASE_R_PMD_STATUS_REGISTER_151_CL72_IEEE_TRAINING_FAILURE_SHIFT 3 201 202 /* CL72_IEEE_TX :: BASE_R_PMD_STATUS_REGISTER_151 :: cl72_ieee_training_status [02:02] */ 203 #define CL72_IEEE_TX_BASE_R_PMD_STATUS_REGISTER_151_CL72_IEEE_TRAINING_STATUS_MASK 0x0004 204 #define CL72_IEEE_TX_BASE_R_PMD_STATUS_REGISTER_151_CL72_IEEE_TRAINING_STATUS_ALIGN 0 205 #define CL72_IEEE_TX_BASE_R_PMD_STATUS_REGISTER_151_CL72_IEEE_TRAINING_STATUS_BITS 1 206 #define CL72_IEEE_TX_BASE_R_PMD_STATUS_REGISTER_151_CL72_IEEE_TRAINING_STATUS_SHIFT 2 207 208 /* CL72_IEEE_TX :: BASE_R_PMD_STATUS_REGISTER_151 :: cl72_ieee_frame_lock [01:01] */ 209 #define CL72_IEEE_TX_BASE_R_PMD_STATUS_REGISTER_151_CL72_IEEE_FRAME_LOCK_MASK 0x0002 210 #define CL72_IEEE_TX_BASE_R_PMD_STATUS_REGISTER_151_CL72_IEEE_FRAME_LOCK_ALIGN 0 211 #define CL72_IEEE_TX_BASE_R_PMD_STATUS_REGISTER_151_CL72_IEEE_FRAME_LOCK_BITS 1 212 #define CL72_IEEE_TX_BASE_R_PMD_STATUS_REGISTER_151_CL72_IEEE_FRAME_LOCK_SHIFT 1 213 214 /* CL72_IEEE_TX :: BASE_R_PMD_STATUS_REGISTER_151 :: cl72_ieee_receiver_status [00:00] */ 215 #define CL72_IEEE_TX_BASE_R_PMD_STATUS_REGISTER_151_CL72_IEEE_RECEIVER_STATUS_MASK 0x0001 216 #define CL72_IEEE_TX_BASE_R_PMD_STATUS_REGISTER_151_CL72_IEEE_RECEIVER_STATUS_ALIGN 0 217 #define CL72_IEEE_TX_BASE_R_PMD_STATUS_REGISTER_151_CL72_IEEE_RECEIVER_STATUS_BITS 1 218 #define CL72_IEEE_TX_BASE_R_PMD_STATUS_REGISTER_151_CL72_IEEE_RECEIVER_STATUS_SHIFT 0 219 220 221 /**************************************************************************** 222 * CL72_IEEE_TX :: BASE_R_LP_COEFF_UPDATE_REGISTER_152 223 */ 224 /* CL72_IEEE_TX :: BASE_R_LP_COEFF_UPDATE_REGISTER_152 :: cl72_ieee_lp_coeff_update [15:00] */ 225 #define CL72_IEEE_TX_BASE_R_LP_COEFF_UPDATE_REGISTER_152_CL72_IEEE_LP_COEFF_UPDATE_MASK 0xffff 226 #define CL72_IEEE_TX_BASE_R_LP_COEFF_UPDATE_REGISTER_152_CL72_IEEE_LP_COEFF_UPDATE_ALIGN 0 227 #define CL72_IEEE_TX_BASE_R_LP_COEFF_UPDATE_REGISTER_152_CL72_IEEE_LP_COEFF_UPDATE_BITS 16 228 #define CL72_IEEE_TX_BASE_R_LP_COEFF_UPDATE_REGISTER_152_CL72_IEEE_LP_COEFF_UPDATE_SHIFT 0 229 230 231 /**************************************************************************** 232 * CL72_IEEE_TX :: BASE_R_LD_COEFF_UPDATE_REGISTER_154 233 */ 234 /* CL72_IEEE_TX :: BASE_R_LD_COEFF_UPDATE_REGISTER_154 :: cl72_ieee_ld_coeff_update [15:00] */ 235 #define CL72_IEEE_TX_BASE_R_LD_COEFF_UPDATE_REGISTER_154_CL72_IEEE_LD_COEFF_UPDATE_MASK 0xffff 236 #define CL72_IEEE_TX_BASE_R_LD_COEFF_UPDATE_REGISTER_154_CL72_IEEE_LD_COEFF_UPDATE_ALIGN 0 237 #define CL72_IEEE_TX_BASE_R_LD_COEFF_UPDATE_REGISTER_154_CL72_IEEE_LD_COEFF_UPDATE_BITS 16 238 #define CL72_IEEE_TX_BASE_R_LD_COEFF_UPDATE_REGISTER_154_CL72_IEEE_LD_COEFF_UPDATE_SHIFT 0 239 240 241 /**************************************************************************** 242 * CL72_IEEE_TX :: BASE_R_LD_STATUS_REPORT_REGISTER_155 243 */ 244 /* CL72_IEEE_TX :: BASE_R_LD_STATUS_REPORT_REGISTER_155 :: cl72_ieee_ld_status_report [15:00] */ 245 #define CL72_IEEE_TX_BASE_R_LD_STATUS_REPORT_REGISTER_155_CL72_IEEE_LD_STATUS_REPORT_MASK 0xffff 246 #define CL72_IEEE_TX_BASE_R_LD_STATUS_REPORT_REGISTER_155_CL72_IEEE_LD_STATUS_REPORT_ALIGN 0 247 #define CL72_IEEE_TX_BASE_R_LD_STATUS_REPORT_REGISTER_155_CL72_IEEE_LD_STATUS_REPORT_BITS 16 248 #define CL72_IEEE_TX_BASE_R_LD_STATUS_REPORT_REGISTER_155_CL72_IEEE_LD_STATUS_REPORT_SHIFT 0 249 250 251 /**************************************************************************** 252 * eagle_tsc_cl72b_ieee_blk_CL72_IEEE_RX 253 */ 254 /**************************************************************************** 255 * CL72_IEEE_RX :: BASE_R_LD_STATUS_REPORT_REGISTER_153 256 */ 257 /* CL72_IEEE_RX :: BASE_R_LD_STATUS_REPORT_REGISTER_153 :: cl72_ieee_lp_status_report [15:00] */ 258 #define CL72_IEEE_RX_BASE_R_LD_STATUS_REPORT_REGISTER_153_CL72_IEEE_LP_STATUS_REPORT_MASK 0xffff 259 #define CL72_IEEE_RX_BASE_R_LD_STATUS_REPORT_REGISTER_153_CL72_IEEE_LP_STATUS_REPORT_ALIGN 0 260 #define CL72_IEEE_RX_BASE_R_LD_STATUS_REPORT_REGISTER_153_CL72_IEEE_LP_STATUS_REPORT_BITS 16 261 #define CL72_IEEE_RX_BASE_R_LD_STATUS_REPORT_REGISTER_153_CL72_IEEE_LP_STATUS_REPORT_SHIFT 0 262 263 264 /**************************************************************************** 265 * eagle_tsc_dsc_blk_DSC_A 266 */ 267 /**************************************************************************** 268 * DSC_A :: CDR_CONTROL_0 269 */ 270 /* DSC_A :: CDR_CONTROL_0 :: reserved0 [15:11] */ 271 #define DSC_A_CDR_CONTROL_0_RESERVED0_MASK 0xf800 272 #define DSC_A_CDR_CONTROL_0_RESERVED0_ALIGN 0 273 #define DSC_A_CDR_CONTROL_0_RESERVED0_BITS 5 274 #define DSC_A_CDR_CONTROL_0_RESERVED0_SHIFT 11 275 276 /* DSC_A :: CDR_CONTROL_0 :: cdr_lm_thr_sel [10:08] */ 277 #define DSC_A_CDR_CONTROL_0_CDR_LM_THR_SEL_MASK 0x0700 278 #define DSC_A_CDR_CONTROL_0_CDR_LM_THR_SEL_ALIGN 0 279 #define DSC_A_CDR_CONTROL_0_CDR_LM_THR_SEL_BITS 3 280 #define DSC_A_CDR_CONTROL_0_CDR_LM_THR_SEL_SHIFT 8 281 282 /* DSC_A :: CDR_CONTROL_0 :: cdr_freq_override_en [07:07] */ 283 #define DSC_A_CDR_CONTROL_0_CDR_FREQ_OVERRIDE_EN_MASK 0x0080 284 #define DSC_A_CDR_CONTROL_0_CDR_FREQ_OVERRIDE_EN_ALIGN 0 285 #define DSC_A_CDR_CONTROL_0_CDR_FREQ_OVERRIDE_EN_BITS 1 286 #define DSC_A_CDR_CONTROL_0_CDR_FREQ_OVERRIDE_EN_SHIFT 7 287 288 /* DSC_A :: CDR_CONTROL_0 :: cdr_integ_sat_sel [06:06] */ 289 #define DSC_A_CDR_CONTROL_0_CDR_INTEG_SAT_SEL_MASK 0x0040 290 #define DSC_A_CDR_CONTROL_0_CDR_INTEG_SAT_SEL_ALIGN 0 291 #define DSC_A_CDR_CONTROL_0_CDR_INTEG_SAT_SEL_BITS 1 292 #define DSC_A_CDR_CONTROL_0_CDR_INTEG_SAT_SEL_SHIFT 6 293 294 /* DSC_A :: CDR_CONTROL_0 :: cdr_phase_err_frz [05:05] */ 295 #define DSC_A_CDR_CONTROL_0_CDR_PHASE_ERR_FRZ_MASK 0x0020 296 #define DSC_A_CDR_CONTROL_0_CDR_PHASE_ERR_FRZ_ALIGN 0 297 #define DSC_A_CDR_CONTROL_0_CDR_PHASE_ERR_FRZ_BITS 1 298 #define DSC_A_CDR_CONTROL_0_CDR_PHASE_ERR_FRZ_SHIFT 5 299 300 /* DSC_A :: CDR_CONTROL_0 :: cdr_integ_reg_clr [04:04] */ 301 #define DSC_A_CDR_CONTROL_0_CDR_INTEG_REG_CLR_MASK 0x0010 302 #define DSC_A_CDR_CONTROL_0_CDR_INTEG_REG_CLR_ALIGN 0 303 #define DSC_A_CDR_CONTROL_0_CDR_INTEG_REG_CLR_BITS 1 304 #define DSC_A_CDR_CONTROL_0_CDR_INTEG_REG_CLR_SHIFT 4 305 306 /* DSC_A :: CDR_CONTROL_0 :: reserved1 [03:03] */ 307 #define DSC_A_CDR_CONTROL_0_RESERVED1_MASK 0x0008 308 #define DSC_A_CDR_CONTROL_0_RESERVED1_ALIGN 0 309 #define DSC_A_CDR_CONTROL_0_RESERVED1_BITS 1 310 #define DSC_A_CDR_CONTROL_0_RESERVED1_SHIFT 3 311 312 /* DSC_A :: CDR_CONTROL_0 :: cdr_freq_en [02:02] */ 313 #define DSC_A_CDR_CONTROL_0_CDR_FREQ_EN_MASK 0x0004 314 #define DSC_A_CDR_CONTROL_0_CDR_FREQ_EN_ALIGN 0 315 #define DSC_A_CDR_CONTROL_0_CDR_FREQ_EN_BITS 1 316 #define DSC_A_CDR_CONTROL_0_CDR_FREQ_EN_SHIFT 2 317 318 /* DSC_A :: CDR_CONTROL_0 :: br_pd_en [01:01] */ 319 #define DSC_A_CDR_CONTROL_0_BR_PD_EN_MASK 0x0002 320 #define DSC_A_CDR_CONTROL_0_BR_PD_EN_ALIGN 0 321 #define DSC_A_CDR_CONTROL_0_BR_PD_EN_BITS 1 322 #define DSC_A_CDR_CONTROL_0_BR_PD_EN_SHIFT 1 323 324 /* DSC_A :: CDR_CONTROL_0 :: cdr_phase_sat_ctrl [00:00] */ 325 #define DSC_A_CDR_CONTROL_0_CDR_PHASE_SAT_CTRL_MASK 0x0001 326 #define DSC_A_CDR_CONTROL_0_CDR_PHASE_SAT_CTRL_ALIGN 0 327 #define DSC_A_CDR_CONTROL_0_CDR_PHASE_SAT_CTRL_BITS 1 328 #define DSC_A_CDR_CONTROL_0_CDR_PHASE_SAT_CTRL_SHIFT 0 329 330 331 /**************************************************************************** 332 * DSC_A :: CDR_CONTROL_1 333 */ 334 /* DSC_A :: CDR_CONTROL_1 :: cdr_freq_override_val [15:00] */ 335 #define DSC_A_CDR_CONTROL_1_CDR_FREQ_OVERRIDE_VAL_MASK 0xffff 336 #define DSC_A_CDR_CONTROL_1_CDR_FREQ_OVERRIDE_VAL_ALIGN 0 337 #define DSC_A_CDR_CONTROL_1_CDR_FREQ_OVERRIDE_VAL_BITS 16 338 #define DSC_A_CDR_CONTROL_1_CDR_FREQ_OVERRIDE_VAL_SHIFT 0 339 340 341 /**************************************************************************** 342 * DSC_A :: CDR_CONTROL_2 343 */ 344 /* DSC_A :: CDR_CONTROL_2 :: reserved0 [15:10] */ 345 #define DSC_A_CDR_CONTROL_2_RESERVED0_MASK 0xfc00 346 #define DSC_A_CDR_CONTROL_2_RESERVED0_ALIGN 0 347 #define DSC_A_CDR_CONTROL_2_RESERVED0_BITS 6 348 #define DSC_A_CDR_CONTROL_2_RESERVED0_SHIFT 10 349 350 /* DSC_A :: CDR_CONTROL_2 :: osx2p_pherr_gain [09:08] */ 351 #define DSC_A_CDR_CONTROL_2_OSX2P_PHERR_GAIN_MASK 0x0300 352 #define DSC_A_CDR_CONTROL_2_OSX2P_PHERR_GAIN_ALIGN 0 353 #define DSC_A_CDR_CONTROL_2_OSX2P_PHERR_GAIN_BITS 2 354 #define DSC_A_CDR_CONTROL_2_OSX2P_PHERR_GAIN_SHIFT 8 355 356 /* DSC_A :: CDR_CONTROL_2 :: pattern_sel [07:04] */ 357 #define DSC_A_CDR_CONTROL_2_PATTERN_SEL_MASK 0x00f0 358 #define DSC_A_CDR_CONTROL_2_PATTERN_SEL_ALIGN 0 359 #define DSC_A_CDR_CONTROL_2_PATTERN_SEL_BITS 4 360 #define DSC_A_CDR_CONTROL_2_PATTERN_SEL_SHIFT 4 361 362 /* DSC_A :: CDR_CONTROL_2 :: reserved1 [03:02] */ 363 #define DSC_A_CDR_CONTROL_2_RESERVED1_MASK 0x000c 364 #define DSC_A_CDR_CONTROL_2_RESERVED1_ALIGN 0 365 #define DSC_A_CDR_CONTROL_2_RESERVED1_BITS 2 366 #define DSC_A_CDR_CONTROL_2_RESERVED1_SHIFT 2 367 368 /* DSC_A :: CDR_CONTROL_2 :: phase_err_offset_mult_2 [01:01] */ 369 #define DSC_A_CDR_CONTROL_2_PHASE_ERR_OFFSET_MULT_2_MASK 0x0002 370 #define DSC_A_CDR_CONTROL_2_PHASE_ERR_OFFSET_MULT_2_ALIGN 0 371 #define DSC_A_CDR_CONTROL_2_PHASE_ERR_OFFSET_MULT_2_BITS 1 372 #define DSC_A_CDR_CONTROL_2_PHASE_ERR_OFFSET_MULT_2_SHIFT 1 373 374 /* DSC_A :: CDR_CONTROL_2 :: cdr_zero_polarity [00:00] */ 375 #define DSC_A_CDR_CONTROL_2_CDR_ZERO_POLARITY_MASK 0x0001 376 #define DSC_A_CDR_CONTROL_2_CDR_ZERO_POLARITY_ALIGN 0 377 #define DSC_A_CDR_CONTROL_2_CDR_ZERO_POLARITY_BITS 1 378 #define DSC_A_CDR_CONTROL_2_CDR_ZERO_POLARITY_SHIFT 0 379 380 381 /**************************************************************************** 382 * DSC_A :: RX_PI_CONTROL 383 */ 384 /* DSC_A :: RX_PI_CONTROL :: rx_pi_manual_reset [15:15] */ 385 #define DSC_A_RX_PI_CONTROL_RX_PI_MANUAL_RESET_MASK 0x8000 386 #define DSC_A_RX_PI_CONTROL_RX_PI_MANUAL_RESET_ALIGN 0 387 #define DSC_A_RX_PI_CONTROL_RX_PI_MANUAL_RESET_BITS 1 388 #define DSC_A_RX_PI_CONTROL_RX_PI_MANUAL_RESET_SHIFT 15 389 390 /* DSC_A :: RX_PI_CONTROL :: rx_pi_slicers_en [14:12] */ 391 #define DSC_A_RX_PI_CONTROL_RX_PI_SLICERS_EN_MASK 0x7000 392 #define DSC_A_RX_PI_CONTROL_RX_PI_SLICERS_EN_ALIGN 0 393 #define DSC_A_RX_PI_CONTROL_RX_PI_SLICERS_EN_BITS 3 394 #define DSC_A_RX_PI_CONTROL_RX_PI_SLICERS_EN_SHIFT 12 395 396 /* DSC_A :: RX_PI_CONTROL :: rx_pi_manual_mode [11:11] */ 397 #define DSC_A_RX_PI_CONTROL_RX_PI_MANUAL_MODE_MASK 0x0800 398 #define DSC_A_RX_PI_CONTROL_RX_PI_MANUAL_MODE_ALIGN 0 399 #define DSC_A_RX_PI_CONTROL_RX_PI_MANUAL_MODE_BITS 1 400 #define DSC_A_RX_PI_CONTROL_RX_PI_MANUAL_MODE_SHIFT 11 401 402 /* DSC_A :: RX_PI_CONTROL :: rx_pi_phase_step_dir [10:10] */ 403 #define DSC_A_RX_PI_CONTROL_RX_PI_PHASE_STEP_DIR_MASK 0x0400 404 #define DSC_A_RX_PI_CONTROL_RX_PI_PHASE_STEP_DIR_ALIGN 0 405 #define DSC_A_RX_PI_CONTROL_RX_PI_PHASE_STEP_DIR_BITS 1 406 #define DSC_A_RX_PI_CONTROL_RX_PI_PHASE_STEP_DIR_SHIFT 10 407 408 /* DSC_A :: RX_PI_CONTROL :: rx_pi_manual_strobe [09:09] */ 409 #define DSC_A_RX_PI_CONTROL_RX_PI_MANUAL_STROBE_MASK 0x0200 410 #define DSC_A_RX_PI_CONTROL_RX_PI_MANUAL_STROBE_ALIGN 0 411 #define DSC_A_RX_PI_CONTROL_RX_PI_MANUAL_STROBE_BITS 1 412 #define DSC_A_RX_PI_CONTROL_RX_PI_MANUAL_STROBE_SHIFT 9 413 414 /* DSC_A :: RX_PI_CONTROL :: reserved0 [08:07] */ 415 #define DSC_A_RX_PI_CONTROL_RESERVED0_MASK 0x0180 416 #define DSC_A_RX_PI_CONTROL_RESERVED0_ALIGN 0 417 #define DSC_A_RX_PI_CONTROL_RESERVED0_BITS 2 418 #define DSC_A_RX_PI_CONTROL_RESERVED0_SHIFT 7 419 420 /* DSC_A :: RX_PI_CONTROL :: rx_pi_phase_step_cnt [06:00] */ 421 #define DSC_A_RX_PI_CONTROL_RX_PI_PHASE_STEP_CNT_MASK 0x007f 422 #define DSC_A_RX_PI_CONTROL_RX_PI_PHASE_STEP_CNT_ALIGN 0 423 #define DSC_A_RX_PI_CONTROL_RX_PI_PHASE_STEP_CNT_BITS 7 424 #define DSC_A_RX_PI_CONTROL_RX_PI_PHASE_STEP_CNT_SHIFT 0 425 426 427 /**************************************************************************** 428 * DSC_A :: CDR_STATUS_INTEG_REG 429 */ 430 /* DSC_A :: CDR_STATUS_INTEG_REG :: cdr_integ_reg [15:00] */ 431 #define DSC_A_CDR_STATUS_INTEG_REG_CDR_INTEG_REG_MASK 0xffff 432 #define DSC_A_CDR_STATUS_INTEG_REG_CDR_INTEG_REG_ALIGN 0 433 #define DSC_A_CDR_STATUS_INTEG_REG_CDR_INTEG_REG_BITS 16 434 #define DSC_A_CDR_STATUS_INTEG_REG_CDR_INTEG_REG_SHIFT 0 435 436 437 /**************************************************************************** 438 * DSC_A :: CDR_STATUS_PHASE_ERROR 439 */ 440 /* DSC_A :: CDR_STATUS_PHASE_ERROR :: reserved0 [15:09] */ 441 #define DSC_A_CDR_STATUS_PHASE_ERROR_RESERVED0_MASK 0xfe00 442 #define DSC_A_CDR_STATUS_PHASE_ERROR_RESERVED0_ALIGN 0 443 #define DSC_A_CDR_STATUS_PHASE_ERROR_RESERVED0_BITS 7 444 #define DSC_A_CDR_STATUS_PHASE_ERROR_RESERVED0_SHIFT 9 445 446 /* DSC_A :: CDR_STATUS_PHASE_ERROR :: cdr_lm_outoflock [08:08] */ 447 #define DSC_A_CDR_STATUS_PHASE_ERROR_CDR_LM_OUTOFLOCK_MASK 0x0100 448 #define DSC_A_CDR_STATUS_PHASE_ERROR_CDR_LM_OUTOFLOCK_ALIGN 0 449 #define DSC_A_CDR_STATUS_PHASE_ERROR_CDR_LM_OUTOFLOCK_BITS 1 450 #define DSC_A_CDR_STATUS_PHASE_ERROR_CDR_LM_OUTOFLOCK_SHIFT 8 451 452 /* DSC_A :: CDR_STATUS_PHASE_ERROR :: reserved1 [07:05] */ 453 #define DSC_A_CDR_STATUS_PHASE_ERROR_RESERVED1_MASK 0x00e0 454 #define DSC_A_CDR_STATUS_PHASE_ERROR_RESERVED1_ALIGN 0 455 #define DSC_A_CDR_STATUS_PHASE_ERROR_RESERVED1_BITS 3 456 #define DSC_A_CDR_STATUS_PHASE_ERROR_RESERVED1_SHIFT 5 457 458 /* DSC_A :: CDR_STATUS_PHASE_ERROR :: cdr_phase_err [04:00] */ 459 #define DSC_A_CDR_STATUS_PHASE_ERROR_CDR_PHASE_ERR_MASK 0x001f 460 #define DSC_A_CDR_STATUS_PHASE_ERROR_CDR_PHASE_ERR_ALIGN 0 461 #define DSC_A_CDR_STATUS_PHASE_ERROR_CDR_PHASE_ERR_BITS 5 462 #define DSC_A_CDR_STATUS_PHASE_ERROR_CDR_PHASE_ERR_SHIFT 0 463 464 465 /**************************************************************************** 466 * DSC_A :: RX_PI_CNT_BIN_D 467 */ 468 /* DSC_A :: RX_PI_CNT_BIN_D :: reserved0 [15:15] */ 469 #define DSC_A_RX_PI_CNT_BIN_D_RESERVED0_MASK 0x8000 470 #define DSC_A_RX_PI_CNT_BIN_D_RESERVED0_ALIGN 0 471 #define DSC_A_RX_PI_CNT_BIN_D_RESERVED0_BITS 1 472 #define DSC_A_RX_PI_CNT_BIN_D_RESERVED0_SHIFT 15 473 474 /* DSC_A :: RX_PI_CNT_BIN_D :: cnt_bin_p1_dreg [14:08] */ 475 #define DSC_A_RX_PI_CNT_BIN_D_CNT_BIN_P1_DREG_MASK 0x7f00 476 #define DSC_A_RX_PI_CNT_BIN_D_CNT_BIN_P1_DREG_ALIGN 0 477 #define DSC_A_RX_PI_CNT_BIN_D_CNT_BIN_P1_DREG_BITS 7 478 #define DSC_A_RX_PI_CNT_BIN_D_CNT_BIN_P1_DREG_SHIFT 8 479 480 /* DSC_A :: RX_PI_CNT_BIN_D :: reserved1 [07:07] */ 481 #define DSC_A_RX_PI_CNT_BIN_D_RESERVED1_MASK 0x0080 482 #define DSC_A_RX_PI_CNT_BIN_D_RESERVED1_ALIGN 0 483 #define DSC_A_RX_PI_CNT_BIN_D_RESERVED1_BITS 1 484 #define DSC_A_RX_PI_CNT_BIN_D_RESERVED1_SHIFT 7 485 486 /* DSC_A :: RX_PI_CNT_BIN_D :: cnt_bin_d_dreg [06:00] */ 487 #define DSC_A_RX_PI_CNT_BIN_D_CNT_BIN_D_DREG_MASK 0x007f 488 #define DSC_A_RX_PI_CNT_BIN_D_CNT_BIN_D_DREG_ALIGN 0 489 #define DSC_A_RX_PI_CNT_BIN_D_CNT_BIN_D_DREG_BITS 7 490 #define DSC_A_RX_PI_CNT_BIN_D_CNT_BIN_D_DREG_SHIFT 0 491 492 493 /**************************************************************************** 494 * DSC_A :: RX_PI_CNT_BIN_P 495 */ 496 /* DSC_A :: RX_PI_CNT_BIN_P :: reserved0 [15:15] */ 497 #define DSC_A_RX_PI_CNT_BIN_P_RESERVED0_MASK 0x8000 498 #define DSC_A_RX_PI_CNT_BIN_P_RESERVED0_ALIGN 0 499 #define DSC_A_RX_PI_CNT_BIN_P_RESERVED0_BITS 1 500 #define DSC_A_RX_PI_CNT_BIN_P_RESERVED0_SHIFT 15 501 502 /* DSC_A :: RX_PI_CNT_BIN_P :: cnt_bin_m1_preg [14:08] */ 503 #define DSC_A_RX_PI_CNT_BIN_P_CNT_BIN_M1_PREG_MASK 0x7f00 504 #define DSC_A_RX_PI_CNT_BIN_P_CNT_BIN_M1_PREG_ALIGN 0 505 #define DSC_A_RX_PI_CNT_BIN_P_CNT_BIN_M1_PREG_BITS 7 506 #define DSC_A_RX_PI_CNT_BIN_P_CNT_BIN_M1_PREG_SHIFT 8 507 508 /* DSC_A :: RX_PI_CNT_BIN_P :: reserved1 [07:07] */ 509 #define DSC_A_RX_PI_CNT_BIN_P_RESERVED1_MASK 0x0080 510 #define DSC_A_RX_PI_CNT_BIN_P_RESERVED1_ALIGN 0 511 #define DSC_A_RX_PI_CNT_BIN_P_RESERVED1_BITS 1 512 #define DSC_A_RX_PI_CNT_BIN_P_RESERVED1_SHIFT 7 513 514 /* DSC_A :: RX_PI_CNT_BIN_P :: cnt_bin_p1_preg [06:00] */ 515 #define DSC_A_RX_PI_CNT_BIN_P_CNT_BIN_P1_PREG_MASK 0x007f 516 #define DSC_A_RX_PI_CNT_BIN_P_CNT_BIN_P1_PREG_ALIGN 0 517 #define DSC_A_RX_PI_CNT_BIN_P_CNT_BIN_P1_PREG_BITS 7 518 #define DSC_A_RX_PI_CNT_BIN_P_CNT_BIN_P1_PREG_SHIFT 0 519 520 521 /**************************************************************************** 522 * DSC_A :: RX_PI_CNT_BIN_M 523 */ 524 /* DSC_A :: RX_PI_CNT_BIN_M :: reserved0 [15:15] */ 525 #define DSC_A_RX_PI_CNT_BIN_M_RESERVED0_MASK 0x8000 526 #define DSC_A_RX_PI_CNT_BIN_M_RESERVED0_ALIGN 0 527 #define DSC_A_RX_PI_CNT_BIN_M_RESERVED0_BITS 1 528 #define DSC_A_RX_PI_CNT_BIN_M_RESERVED0_SHIFT 15 529 530 /* DSC_A :: RX_PI_CNT_BIN_M :: cnt_bin_d_mreg [14:08] */ 531 #define DSC_A_RX_PI_CNT_BIN_M_CNT_BIN_D_MREG_MASK 0x7f00 532 #define DSC_A_RX_PI_CNT_BIN_M_CNT_BIN_D_MREG_ALIGN 0 533 #define DSC_A_RX_PI_CNT_BIN_M_CNT_BIN_D_MREG_BITS 7 534 #define DSC_A_RX_PI_CNT_BIN_M_CNT_BIN_D_MREG_SHIFT 8 535 536 /* DSC_A :: RX_PI_CNT_BIN_M :: reserved1 [07:07] */ 537 #define DSC_A_RX_PI_CNT_BIN_M_RESERVED1_MASK 0x0080 538 #define DSC_A_RX_PI_CNT_BIN_M_RESERVED1_ALIGN 0 539 #define DSC_A_RX_PI_CNT_BIN_M_RESERVED1_BITS 1 540 #define DSC_A_RX_PI_CNT_BIN_M_RESERVED1_SHIFT 7 541 542 /* DSC_A :: RX_PI_CNT_BIN_M :: cnt_bin_m1_mreg [06:00] */ 543 #define DSC_A_RX_PI_CNT_BIN_M_CNT_BIN_M1_MREG_MASK 0x007f 544 #define DSC_A_RX_PI_CNT_BIN_M_CNT_BIN_M1_MREG_ALIGN 0 545 #define DSC_A_RX_PI_CNT_BIN_M_CNT_BIN_M1_MREG_BITS 7 546 #define DSC_A_RX_PI_CNT_BIN_M_CNT_BIN_M1_MREG_SHIFT 0 547 548 549 /**************************************************************************** 550 * DSC_A :: RX_PI_DIFF_BIN 551 */ 552 /* DSC_A :: RX_PI_DIFF_BIN :: cnt_d_minus_p1 [15:08] */ 553 #define DSC_A_RX_PI_DIFF_BIN_CNT_D_MINUS_P1_MASK 0xff00 554 #define DSC_A_RX_PI_DIFF_BIN_CNT_D_MINUS_P1_ALIGN 0 555 #define DSC_A_RX_PI_DIFF_BIN_CNT_D_MINUS_P1_BITS 8 556 #define DSC_A_RX_PI_DIFF_BIN_CNT_D_MINUS_P1_SHIFT 8 557 558 /* DSC_A :: RX_PI_DIFF_BIN :: cnt_d_minus_m1 [07:00] */ 559 #define DSC_A_RX_PI_DIFF_BIN_CNT_D_MINUS_M1_MASK 0x00ff 560 #define DSC_A_RX_PI_DIFF_BIN_CNT_D_MINUS_M1_ALIGN 0 561 #define DSC_A_RX_PI_DIFF_BIN_CNT_D_MINUS_M1_BITS 8 562 #define DSC_A_RX_PI_DIFF_BIN_CNT_D_MINUS_M1_SHIFT 0 563 564 565 /**************************************************************************** 566 * DSC_A :: TRNSUM_CNTL_5 567 */ 568 /* DSC_A :: TRNSUM_CNTL_5 :: reserved0 [15:15] */ 569 #define DSC_A_TRNSUM_CNTL_5_RESERVED0_MASK 0x8000 570 #define DSC_A_TRNSUM_CNTL_5_RESERVED0_ALIGN 0 571 #define DSC_A_TRNSUM_CNTL_5_RESERVED0_BITS 1 572 #define DSC_A_TRNSUM_CNTL_5_RESERVED0_SHIFT 15 573 574 /* DSC_A :: TRNSUM_CNTL_5 :: send_lms_to_pcs [14:14] */ 575 #define DSC_A_TRNSUM_CNTL_5_SEND_LMS_TO_PCS_MASK 0x4000 576 #define DSC_A_TRNSUM_CNTL_5_SEND_LMS_TO_PCS_ALIGN 0 577 #define DSC_A_TRNSUM_CNTL_5_SEND_LMS_TO_PCS_BITS 1 578 #define DSC_A_TRNSUM_CNTL_5_SEND_LMS_TO_PCS_SHIFT 14 579 580 /* DSC_A :: TRNSUM_CNTL_5 :: reserved1 [13:00] */ 581 #define DSC_A_TRNSUM_CNTL_5_RESERVED1_MASK 0x3fff 582 #define DSC_A_TRNSUM_CNTL_5_RESERVED1_ALIGN 0 583 #define DSC_A_TRNSUM_CNTL_5_RESERVED1_BITS 14 584 #define DSC_A_TRNSUM_CNTL_5_RESERVED1_SHIFT 0 585 586 587 /**************************************************************************** 588 * DSC_A :: DSC_UC_CTRL 589 */ 590 /* DSC_A :: DSC_UC_CTRL :: uc_dsc_supp_info [15:08] */ 591 #define DSC_A_DSC_UC_CTRL_UC_DSC_SUPP_INFO_MASK 0xff00 592 #define DSC_A_DSC_UC_CTRL_UC_DSC_SUPP_INFO_ALIGN 0 593 #define DSC_A_DSC_UC_CTRL_UC_DSC_SUPP_INFO_BITS 8 594 #define DSC_A_DSC_UC_CTRL_UC_DSC_SUPP_INFO_SHIFT 8 595 596 /* DSC_A :: DSC_UC_CTRL :: uc_dsc_ready_for_cmd [07:07] */ 597 #define DSC_A_DSC_UC_CTRL_UC_DSC_READY_FOR_CMD_MASK 0x0080 598 #define DSC_A_DSC_UC_CTRL_UC_DSC_READY_FOR_CMD_ALIGN 0 599 #define DSC_A_DSC_UC_CTRL_UC_DSC_READY_FOR_CMD_BITS 1 600 #define DSC_A_DSC_UC_CTRL_UC_DSC_READY_FOR_CMD_SHIFT 7 601 602 /* DSC_A :: DSC_UC_CTRL :: uc_dsc_error_found [06:06] */ 603 #define DSC_A_DSC_UC_CTRL_UC_DSC_ERROR_FOUND_MASK 0x0040 604 #define DSC_A_DSC_UC_CTRL_UC_DSC_ERROR_FOUND_ALIGN 0 605 #define DSC_A_DSC_UC_CTRL_UC_DSC_ERROR_FOUND_BITS 1 606 #define DSC_A_DSC_UC_CTRL_UC_DSC_ERROR_FOUND_SHIFT 6 607 608 /* DSC_A :: DSC_UC_CTRL :: uc_dsc_gp_uc_req [05:00] */ 609 #define DSC_A_DSC_UC_CTRL_UC_DSC_GP_UC_REQ_MASK 0x003f 610 #define DSC_A_DSC_UC_CTRL_UC_DSC_GP_UC_REQ_ALIGN 0 611 #define DSC_A_DSC_UC_CTRL_UC_DSC_GP_UC_REQ_BITS 6 612 #define DSC_A_DSC_UC_CTRL_UC_DSC_GP_UC_REQ_SHIFT 0 613 614 615 /**************************************************************************** 616 * DSC_A :: DSC_SCRATCH 617 */ 618 /* DSC_A :: DSC_SCRATCH :: uc_dsc_scratch [15:00] */ 619 #define DSC_A_DSC_SCRATCH_UC_DSC_SCRATCH_MASK 0xffff 620 #define DSC_A_DSC_SCRATCH_UC_DSC_SCRATCH_ALIGN 0 621 #define DSC_A_DSC_SCRATCH_UC_DSC_SCRATCH_BITS 16 622 #define DSC_A_DSC_SCRATCH_UC_DSC_SCRATCH_SHIFT 0 623 624 625 /**************************************************************************** 626 * eagle_tsc_dsc_blk_DSC_B 627 */ 628 /**************************************************************************** 629 * DSC_B :: DSC_SM_CTRL_0 630 */ 631 /* DSC_B :: DSC_SM_CTRL_0 :: set_meas_incomplete [15:15] */ 632 #define DSC_B_DSC_SM_CTRL_0_SET_MEAS_INCOMPLETE_MASK 0x8000 633 #define DSC_B_DSC_SM_CTRL_0_SET_MEAS_INCOMPLETE_ALIGN 0 634 #define DSC_B_DSC_SM_CTRL_0_SET_MEAS_INCOMPLETE_BITS 1 635 #define DSC_B_DSC_SM_CTRL_0_SET_MEAS_INCOMPLETE_SHIFT 15 636 637 /* DSC_B :: DSC_SM_CTRL_0 :: uc_ack_dsc_config [14:14] */ 638 #define DSC_B_DSC_SM_CTRL_0_UC_ACK_DSC_CONFIG_MASK 0x4000 639 #define DSC_B_DSC_SM_CTRL_0_UC_ACK_DSC_CONFIG_ALIGN 0 640 #define DSC_B_DSC_SM_CTRL_0_UC_ACK_DSC_CONFIG_BITS 1 641 #define DSC_B_DSC_SM_CTRL_0_UC_ACK_DSC_CONFIG_SHIFT 14 642 643 /* DSC_B :: DSC_SM_CTRL_0 :: uc_ack_dsc_restart [13:13] */ 644 #define DSC_B_DSC_SM_CTRL_0_UC_ACK_DSC_RESTART_MASK 0x2000 645 #define DSC_B_DSC_SM_CTRL_0_UC_ACK_DSC_RESTART_ALIGN 0 646 #define DSC_B_DSC_SM_CTRL_0_UC_ACK_DSC_RESTART_BITS 1 647 #define DSC_B_DSC_SM_CTRL_0_UC_ACK_DSC_RESTART_SHIFT 13 648 649 /* DSC_B :: DSC_SM_CTRL_0 :: uc_ack_dsc_reset [12:12] */ 650 #define DSC_B_DSC_SM_CTRL_0_UC_ACK_DSC_RESET_MASK 0x1000 651 #define DSC_B_DSC_SM_CTRL_0_UC_ACK_DSC_RESET_ALIGN 0 652 #define DSC_B_DSC_SM_CTRL_0_UC_ACK_DSC_RESET_BITS 1 653 #define DSC_B_DSC_SM_CTRL_0_UC_ACK_DSC_RESET_SHIFT 12 654 655 /* DSC_B :: DSC_SM_CTRL_0 :: uc_ack_dsc_eee_done [11:11] */ 656 #define DSC_B_DSC_SM_CTRL_0_UC_ACK_DSC_EEE_DONE_MASK 0x0800 657 #define DSC_B_DSC_SM_CTRL_0_UC_ACK_DSC_EEE_DONE_ALIGN 0 658 #define DSC_B_DSC_SM_CTRL_0_UC_ACK_DSC_EEE_DONE_BITS 1 659 #define DSC_B_DSC_SM_CTRL_0_UC_ACK_DSC_EEE_DONE_SHIFT 11 660 661 /* DSC_B :: DSC_SM_CTRL_0 :: reserved0 [10:09] */ 662 #define DSC_B_DSC_SM_CTRL_0_RESERVED0_MASK 0x0600 663 #define DSC_B_DSC_SM_CTRL_0_RESERVED0_ALIGN 0 664 #define DSC_B_DSC_SM_CTRL_0_RESERVED0_BITS 2 665 #define DSC_B_DSC_SM_CTRL_0_RESERVED0_SHIFT 9 666 667 /* DSC_B :: DSC_SM_CTRL_0 :: eee_measure_en [08:08] */ 668 #define DSC_B_DSC_SM_CTRL_0_EEE_MEASURE_EN_MASK 0x0100 669 #define DSC_B_DSC_SM_CTRL_0_EEE_MEASURE_EN_ALIGN 0 670 #define DSC_B_DSC_SM_CTRL_0_EEE_MEASURE_EN_BITS 1 671 #define DSC_B_DSC_SM_CTRL_0_EEE_MEASURE_EN_SHIFT 8 672 673 /* DSC_B :: DSC_SM_CTRL_0 :: uc_trnsum_en [07:07] */ 674 #define DSC_B_DSC_SM_CTRL_0_UC_TRNSUM_EN_MASK 0x0080 675 #define DSC_B_DSC_SM_CTRL_0_UC_TRNSUM_EN_ALIGN 0 676 #define DSC_B_DSC_SM_CTRL_0_UC_TRNSUM_EN_BITS 1 677 #define DSC_B_DSC_SM_CTRL_0_UC_TRNSUM_EN_SHIFT 7 678 679 /* DSC_B :: DSC_SM_CTRL_0 :: hw_tune_en [06:06] */ 680 #define DSC_B_DSC_SM_CTRL_0_HW_TUNE_EN_MASK 0x0040 681 #define DSC_B_DSC_SM_CTRL_0_HW_TUNE_EN_ALIGN 0 682 #define DSC_B_DSC_SM_CTRL_0_HW_TUNE_EN_BITS 1 683 #define DSC_B_DSC_SM_CTRL_0_HW_TUNE_EN_SHIFT 6 684 685 /* DSC_B :: DSC_SM_CTRL_0 :: uc_tune_en [05:05] */ 686 #define DSC_B_DSC_SM_CTRL_0_UC_TUNE_EN_MASK 0x0020 687 #define DSC_B_DSC_SM_CTRL_0_UC_TUNE_EN_ALIGN 0 688 #define DSC_B_DSC_SM_CTRL_0_UC_TUNE_EN_BITS 1 689 #define DSC_B_DSC_SM_CTRL_0_UC_TUNE_EN_SHIFT 5 690 691 /* DSC_B :: DSC_SM_CTRL_0 :: cl72_timer_en [04:04] */ 692 #define DSC_B_DSC_SM_CTRL_0_CL72_TIMER_EN_MASK 0x0010 693 #define DSC_B_DSC_SM_CTRL_0_CL72_TIMER_EN_ALIGN 0 694 #define DSC_B_DSC_SM_CTRL_0_CL72_TIMER_EN_BITS 1 695 #define DSC_B_DSC_SM_CTRL_0_CL72_TIMER_EN_SHIFT 4 696 697 /* DSC_B :: DSC_SM_CTRL_0 :: ignore_rx_mode [03:03] */ 698 #define DSC_B_DSC_SM_CTRL_0_IGNORE_RX_MODE_MASK 0x0008 699 #define DSC_B_DSC_SM_CTRL_0_IGNORE_RX_MODE_ALIGN 0 700 #define DSC_B_DSC_SM_CTRL_0_IGNORE_RX_MODE_BITS 1 701 #define DSC_B_DSC_SM_CTRL_0_IGNORE_RX_MODE_SHIFT 3 702 703 /* DSC_B :: DSC_SM_CTRL_0 :: eee_quiet_rx_afe_pwrdwn_val [02:02] */ 704 #define DSC_B_DSC_SM_CTRL_0_EEE_QUIET_RX_AFE_PWRDWN_VAL_MASK 0x0004 705 #define DSC_B_DSC_SM_CTRL_0_EEE_QUIET_RX_AFE_PWRDWN_VAL_ALIGN 0 706 #define DSC_B_DSC_SM_CTRL_0_EEE_QUIET_RX_AFE_PWRDWN_VAL_BITS 1 707 #define DSC_B_DSC_SM_CTRL_0_EEE_QUIET_RX_AFE_PWRDWN_VAL_SHIFT 2 708 709 /* DSC_B :: DSC_SM_CTRL_0 :: eee_mode_en [01:01] */ 710 #define DSC_B_DSC_SM_CTRL_0_EEE_MODE_EN_MASK 0x0002 711 #define DSC_B_DSC_SM_CTRL_0_EEE_MODE_EN_ALIGN 0 712 #define DSC_B_DSC_SM_CTRL_0_EEE_MODE_EN_BITS 1 713 #define DSC_B_DSC_SM_CTRL_0_EEE_MODE_EN_SHIFT 1 714 715 /* DSC_B :: DSC_SM_CTRL_0 :: reserved1 [00:00] */ 716 #define DSC_B_DSC_SM_CTRL_0_RESERVED1_MASK 0x0001 717 #define DSC_B_DSC_SM_CTRL_0_RESERVED1_ALIGN 0 718 #define DSC_B_DSC_SM_CTRL_0_RESERVED1_BITS 1 719 #define DSC_B_DSC_SM_CTRL_0_RESERVED1_SHIFT 0 720 721 722 /**************************************************************************** 723 * DSC_B :: DSC_SM_CTRL_1 724 */ 725 /* DSC_B :: DSC_SM_CTRL_1 :: reserved0 [15:14] */ 726 #define DSC_B_DSC_SM_CTRL_1_RESERVED0_MASK 0xc000 727 #define DSC_B_DSC_SM_CTRL_1_RESERVED0_ALIGN 0 728 #define DSC_B_DSC_SM_CTRL_1_RESERVED0_BITS 2 729 #define DSC_B_DSC_SM_CTRL_1_RESERVED0_SHIFT 14 730 731 /* DSC_B :: DSC_SM_CTRL_1 :: trnsum_clr_frc_val [13:13] */ 732 #define DSC_B_DSC_SM_CTRL_1_TRNSUM_CLR_FRC_VAL_MASK 0x2000 733 #define DSC_B_DSC_SM_CTRL_1_TRNSUM_CLR_FRC_VAL_ALIGN 0 734 #define DSC_B_DSC_SM_CTRL_1_TRNSUM_CLR_FRC_VAL_BITS 1 735 #define DSC_B_DSC_SM_CTRL_1_TRNSUM_CLR_FRC_VAL_SHIFT 13 736 737 /* DSC_B :: DSC_SM_CTRL_1 :: trnsum_clr_frc [12:12] */ 738 #define DSC_B_DSC_SM_CTRL_1_TRNSUM_CLR_FRC_MASK 0x1000 739 #define DSC_B_DSC_SM_CTRL_1_TRNSUM_CLR_FRC_ALIGN 0 740 #define DSC_B_DSC_SM_CTRL_1_TRNSUM_CLR_FRC_BITS 1 741 #define DSC_B_DSC_SM_CTRL_1_TRNSUM_CLR_FRC_SHIFT 12 742 743 /* DSC_B :: DSC_SM_CTRL_1 :: cdr_frz_frc_val [11:11] */ 744 #define DSC_B_DSC_SM_CTRL_1_CDR_FRZ_FRC_VAL_MASK 0x0800 745 #define DSC_B_DSC_SM_CTRL_1_CDR_FRZ_FRC_VAL_ALIGN 0 746 #define DSC_B_DSC_SM_CTRL_1_CDR_FRZ_FRC_VAL_BITS 1 747 #define DSC_B_DSC_SM_CTRL_1_CDR_FRZ_FRC_VAL_SHIFT 11 748 749 /* DSC_B :: DSC_SM_CTRL_1 :: cdr_frz_frc [10:10] */ 750 #define DSC_B_DSC_SM_CTRL_1_CDR_FRZ_FRC_MASK 0x0400 751 #define DSC_B_DSC_SM_CTRL_1_CDR_FRZ_FRC_ALIGN 0 752 #define DSC_B_DSC_SM_CTRL_1_CDR_FRZ_FRC_BITS 1 753 #define DSC_B_DSC_SM_CTRL_1_CDR_FRZ_FRC_SHIFT 10 754 755 /* DSC_B :: DSC_SM_CTRL_1 :: freq_upd_en_frc_val [09:09] */ 756 #define DSC_B_DSC_SM_CTRL_1_FREQ_UPD_EN_FRC_VAL_MASK 0x0200 757 #define DSC_B_DSC_SM_CTRL_1_FREQ_UPD_EN_FRC_VAL_ALIGN 0 758 #define DSC_B_DSC_SM_CTRL_1_FREQ_UPD_EN_FRC_VAL_BITS 1 759 #define DSC_B_DSC_SM_CTRL_1_FREQ_UPD_EN_FRC_VAL_SHIFT 9 760 761 /* DSC_B :: DSC_SM_CTRL_1 :: freq_upd_en_frc [08:08] */ 762 #define DSC_B_DSC_SM_CTRL_1_FREQ_UPD_EN_FRC_MASK 0x0100 763 #define DSC_B_DSC_SM_CTRL_1_FREQ_UPD_EN_FRC_ALIGN 0 764 #define DSC_B_DSC_SM_CTRL_1_FREQ_UPD_EN_FRC_BITS 1 765 #define DSC_B_DSC_SM_CTRL_1_FREQ_UPD_EN_FRC_SHIFT 8 766 767 /* DSC_B :: DSC_SM_CTRL_1 :: timer_done_frc_val [07:07] */ 768 #define DSC_B_DSC_SM_CTRL_1_TIMER_DONE_FRC_VAL_MASK 0x0080 769 #define DSC_B_DSC_SM_CTRL_1_TIMER_DONE_FRC_VAL_ALIGN 0 770 #define DSC_B_DSC_SM_CTRL_1_TIMER_DONE_FRC_VAL_BITS 1 771 #define DSC_B_DSC_SM_CTRL_1_TIMER_DONE_FRC_VAL_SHIFT 7 772 773 /* DSC_B :: DSC_SM_CTRL_1 :: timer_done_frc [06:06] */ 774 #define DSC_B_DSC_SM_CTRL_1_TIMER_DONE_FRC_MASK 0x0040 775 #define DSC_B_DSC_SM_CTRL_1_TIMER_DONE_FRC_ALIGN 0 776 #define DSC_B_DSC_SM_CTRL_1_TIMER_DONE_FRC_BITS 1 777 #define DSC_B_DSC_SM_CTRL_1_TIMER_DONE_FRC_SHIFT 6 778 779 /* DSC_B :: DSC_SM_CTRL_1 :: trnsum_frz_frc_val [05:05] */ 780 #define DSC_B_DSC_SM_CTRL_1_TRNSUM_FRZ_FRC_VAL_MASK 0x0020 781 #define DSC_B_DSC_SM_CTRL_1_TRNSUM_FRZ_FRC_VAL_ALIGN 0 782 #define DSC_B_DSC_SM_CTRL_1_TRNSUM_FRZ_FRC_VAL_BITS 1 783 #define DSC_B_DSC_SM_CTRL_1_TRNSUM_FRZ_FRC_VAL_SHIFT 5 784 785 /* DSC_B :: DSC_SM_CTRL_1 :: trnsum_frz_frc [04:04] */ 786 #define DSC_B_DSC_SM_CTRL_1_TRNSUM_FRZ_FRC_MASK 0x0010 787 #define DSC_B_DSC_SM_CTRL_1_TRNSUM_FRZ_FRC_ALIGN 0 788 #define DSC_B_DSC_SM_CTRL_1_TRNSUM_FRZ_FRC_BITS 1 789 #define DSC_B_DSC_SM_CTRL_1_TRNSUM_FRZ_FRC_SHIFT 4 790 791 /* DSC_B :: DSC_SM_CTRL_1 :: dsc_clr_frc_val [03:03] */ 792 #define DSC_B_DSC_SM_CTRL_1_DSC_CLR_FRC_VAL_MASK 0x0008 793 #define DSC_B_DSC_SM_CTRL_1_DSC_CLR_FRC_VAL_ALIGN 0 794 #define DSC_B_DSC_SM_CTRL_1_DSC_CLR_FRC_VAL_BITS 1 795 #define DSC_B_DSC_SM_CTRL_1_DSC_CLR_FRC_VAL_SHIFT 3 796 797 /* DSC_B :: DSC_SM_CTRL_1 :: dsc_clr_frc [02:02] */ 798 #define DSC_B_DSC_SM_CTRL_1_DSC_CLR_FRC_MASK 0x0004 799 #define DSC_B_DSC_SM_CTRL_1_DSC_CLR_FRC_ALIGN 0 800 #define DSC_B_DSC_SM_CTRL_1_DSC_CLR_FRC_BITS 1 801 #define DSC_B_DSC_SM_CTRL_1_DSC_CLR_FRC_SHIFT 2 802 803 /* DSC_B :: DSC_SM_CTRL_1 :: rx_dsc_lock_frc_val [01:01] */ 804 #define DSC_B_DSC_SM_CTRL_1_RX_DSC_LOCK_FRC_VAL_MASK 0x0002 805 #define DSC_B_DSC_SM_CTRL_1_RX_DSC_LOCK_FRC_VAL_ALIGN 0 806 #define DSC_B_DSC_SM_CTRL_1_RX_DSC_LOCK_FRC_VAL_BITS 1 807 #define DSC_B_DSC_SM_CTRL_1_RX_DSC_LOCK_FRC_VAL_SHIFT 1 808 809 /* DSC_B :: DSC_SM_CTRL_1 :: rx_dsc_lock_frc [00:00] */ 810 #define DSC_B_DSC_SM_CTRL_1_RX_DSC_LOCK_FRC_MASK 0x0001 811 #define DSC_B_DSC_SM_CTRL_1_RX_DSC_LOCK_FRC_ALIGN 0 812 #define DSC_B_DSC_SM_CTRL_1_RX_DSC_LOCK_FRC_BITS 1 813 #define DSC_B_DSC_SM_CTRL_1_RX_DSC_LOCK_FRC_SHIFT 0 814 815 816 /**************************************************************************** 817 * DSC_B :: DSC_SM_CTRL_2 818 */ 819 /* DSC_B :: DSC_SM_CTRL_2 :: reserved0 [15:13] */ 820 #define DSC_B_DSC_SM_CTRL_2_RESERVED0_MASK 0xe000 821 #define DSC_B_DSC_SM_CTRL_2_RESERVED0_ALIGN 0 822 #define DSC_B_DSC_SM_CTRL_2_RESERVED0_BITS 3 823 #define DSC_B_DSC_SM_CTRL_2_RESERVED0_SHIFT 13 824 825 /* DSC_B :: DSC_SM_CTRL_2 :: eee_lfsr_cnt [12:00] */ 826 #define DSC_B_DSC_SM_CTRL_2_EEE_LFSR_CNT_MASK 0x1fff 827 #define DSC_B_DSC_SM_CTRL_2_EEE_LFSR_CNT_ALIGN 0 828 #define DSC_B_DSC_SM_CTRL_2_EEE_LFSR_CNT_BITS 13 829 #define DSC_B_DSC_SM_CTRL_2_EEE_LFSR_CNT_SHIFT 0 830 831 832 /**************************************************************************** 833 * DSC_B :: DSC_SM_CTRL_3 834 */ 835 /* DSC_B :: DSC_SM_CTRL_3 :: reserved0 [15:13] */ 836 #define DSC_B_DSC_SM_CTRL_3_RESERVED0_MASK 0xe000 837 #define DSC_B_DSC_SM_CTRL_3_RESERVED0_ALIGN 0 838 #define DSC_B_DSC_SM_CTRL_3_RESERVED0_BITS 3 839 #define DSC_B_DSC_SM_CTRL_3_RESERVED0_SHIFT 13 840 841 /* DSC_B :: DSC_SM_CTRL_3 :: measure_lfsr_cnt [12:00] */ 842 #define DSC_B_DSC_SM_CTRL_3_MEASURE_LFSR_CNT_MASK 0x1fff 843 #define DSC_B_DSC_SM_CTRL_3_MEASURE_LFSR_CNT_ALIGN 0 844 #define DSC_B_DSC_SM_CTRL_3_MEASURE_LFSR_CNT_BITS 13 845 #define DSC_B_DSC_SM_CTRL_3_MEASURE_LFSR_CNT_SHIFT 0 846 847 848 /**************************************************************************** 849 * DSC_B :: DSC_SM_CTRL_4 850 */ 851 /* DSC_B :: DSC_SM_CTRL_4 :: reserved0 [15:15] */ 852 #define DSC_B_DSC_SM_CTRL_4_RESERVED0_MASK 0x8000 853 #define DSC_B_DSC_SM_CTRL_4_RESERVED0_ALIGN 0 854 #define DSC_B_DSC_SM_CTRL_4_RESERVED0_BITS 1 855 #define DSC_B_DSC_SM_CTRL_4_RESERVED0_SHIFT 15 856 857 /* DSC_B :: DSC_SM_CTRL_4 :: hw_tune_timeout [14:10] */ 858 #define DSC_B_DSC_SM_CTRL_4_HW_TUNE_TIMEOUT_MASK 0x7c00 859 #define DSC_B_DSC_SM_CTRL_4_HW_TUNE_TIMEOUT_ALIGN 0 860 #define DSC_B_DSC_SM_CTRL_4_HW_TUNE_TIMEOUT_BITS 5 861 #define DSC_B_DSC_SM_CTRL_4_HW_TUNE_TIMEOUT_SHIFT 10 862 863 /* DSC_B :: DSC_SM_CTRL_4 :: cdr_settle_timeout [09:05] */ 864 #define DSC_B_DSC_SM_CTRL_4_CDR_SETTLE_TIMEOUT_MASK 0x03e0 865 #define DSC_B_DSC_SM_CTRL_4_CDR_SETTLE_TIMEOUT_ALIGN 0 866 #define DSC_B_DSC_SM_CTRL_4_CDR_SETTLE_TIMEOUT_BITS 5 867 #define DSC_B_DSC_SM_CTRL_4_CDR_SETTLE_TIMEOUT_SHIFT 5 868 869 /* DSC_B :: DSC_SM_CTRL_4 :: acq_cdr_timeout [04:00] */ 870 #define DSC_B_DSC_SM_CTRL_4_ACQ_CDR_TIMEOUT_MASK 0x001f 871 #define DSC_B_DSC_SM_CTRL_4_ACQ_CDR_TIMEOUT_ALIGN 0 872 #define DSC_B_DSC_SM_CTRL_4_ACQ_CDR_TIMEOUT_BITS 5 873 #define DSC_B_DSC_SM_CTRL_4_ACQ_CDR_TIMEOUT_SHIFT 0 874 875 876 /**************************************************************************** 877 * DSC_B :: DSC_SM_CTRL_5 878 */ 879 /* DSC_B :: DSC_SM_CTRL_5 :: reserved0 [15:15] */ 880 #define DSC_B_DSC_SM_CTRL_5_RESERVED0_MASK 0x8000 881 #define DSC_B_DSC_SM_CTRL_5_RESERVED0_ALIGN 0 882 #define DSC_B_DSC_SM_CTRL_5_RESERVED0_BITS 1 883 #define DSC_B_DSC_SM_CTRL_5_RESERVED0_SHIFT 15 884 885 /* DSC_B :: DSC_SM_CTRL_5 :: eee_cdr_settle_timeout [14:10] */ 886 #define DSC_B_DSC_SM_CTRL_5_EEE_CDR_SETTLE_TIMEOUT_MASK 0x7c00 887 #define DSC_B_DSC_SM_CTRL_5_EEE_CDR_SETTLE_TIMEOUT_ALIGN 0 888 #define DSC_B_DSC_SM_CTRL_5_EEE_CDR_SETTLE_TIMEOUT_BITS 5 889 #define DSC_B_DSC_SM_CTRL_5_EEE_CDR_SETTLE_TIMEOUT_SHIFT 10 890 891 /* DSC_B :: DSC_SM_CTRL_5 :: eee_acq_cdr_timeout [09:05] */ 892 #define DSC_B_DSC_SM_CTRL_5_EEE_ACQ_CDR_TIMEOUT_MASK 0x03e0 893 #define DSC_B_DSC_SM_CTRL_5_EEE_ACQ_CDR_TIMEOUT_ALIGN 0 894 #define DSC_B_DSC_SM_CTRL_5_EEE_ACQ_CDR_TIMEOUT_BITS 5 895 #define DSC_B_DSC_SM_CTRL_5_EEE_ACQ_CDR_TIMEOUT_SHIFT 5 896 897 /* DSC_B :: DSC_SM_CTRL_5 :: measure_timeout [04:00] */ 898 #define DSC_B_DSC_SM_CTRL_5_MEASURE_TIMEOUT_MASK 0x001f 899 #define DSC_B_DSC_SM_CTRL_5_MEASURE_TIMEOUT_ALIGN 0 900 #define DSC_B_DSC_SM_CTRL_5_MEASURE_TIMEOUT_BITS 5 901 #define DSC_B_DSC_SM_CTRL_5_MEASURE_TIMEOUT_SHIFT 0 902 903 904 /**************************************************************************** 905 * DSC_B :: DSC_SM_CTRL_6 906 */ 907 /* DSC_B :: DSC_SM_CTRL_6 :: reserved0 [15:15] */ 908 #define DSC_B_DSC_SM_CTRL_6_RESERVED0_MASK 0x8000 909 #define DSC_B_DSC_SM_CTRL_6_RESERVED0_ALIGN 0 910 #define DSC_B_DSC_SM_CTRL_6_RESERVED0_BITS 1 911 #define DSC_B_DSC_SM_CTRL_6_RESERVED0_SHIFT 15 912 913 /* DSC_B :: DSC_SM_CTRL_6 :: eee_ana_pwr_timeout [14:10] */ 914 #define DSC_B_DSC_SM_CTRL_6_EEE_ANA_PWR_TIMEOUT_MASK 0x7c00 915 #define DSC_B_DSC_SM_CTRL_6_EEE_ANA_PWR_TIMEOUT_ALIGN 0 916 #define DSC_B_DSC_SM_CTRL_6_EEE_ANA_PWR_TIMEOUT_BITS 5 917 #define DSC_B_DSC_SM_CTRL_6_EEE_ANA_PWR_TIMEOUT_SHIFT 10 918 919 /* DSC_B :: DSC_SM_CTRL_6 :: reserved1 [09:05] */ 920 #define DSC_B_DSC_SM_CTRL_6_RESERVED1_MASK 0x03e0 921 #define DSC_B_DSC_SM_CTRL_6_RESERVED1_ALIGN 0 922 #define DSC_B_DSC_SM_CTRL_6_RESERVED1_BITS 5 923 #define DSC_B_DSC_SM_CTRL_6_RESERVED1_SHIFT 5 924 925 /* DSC_B :: DSC_SM_CTRL_6 :: eee_hw_tune_timeout [04:00] */ 926 #define DSC_B_DSC_SM_CTRL_6_EEE_HW_TUNE_TIMEOUT_MASK 0x001f 927 #define DSC_B_DSC_SM_CTRL_6_EEE_HW_TUNE_TIMEOUT_ALIGN 0 928 #define DSC_B_DSC_SM_CTRL_6_EEE_HW_TUNE_TIMEOUT_BITS 5 929 #define DSC_B_DSC_SM_CTRL_6_EEE_HW_TUNE_TIMEOUT_SHIFT 0 930 931 932 /**************************************************************************** 933 * DSC_B :: DSC_SM_CTRL_7 934 */ 935 /* DSC_B :: DSC_SM_CTRL_7 :: cdr_bwsel_prop_norm [15:14] */ 936 #define DSC_B_DSC_SM_CTRL_7_CDR_BWSEL_PROP_NORM_MASK 0xc000 937 #define DSC_B_DSC_SM_CTRL_7_CDR_BWSEL_PROP_NORM_ALIGN 0 938 #define DSC_B_DSC_SM_CTRL_7_CDR_BWSEL_PROP_NORM_BITS 2 939 #define DSC_B_DSC_SM_CTRL_7_CDR_BWSEL_PROP_NORM_SHIFT 14 940 941 /* DSC_B :: DSC_SM_CTRL_7 :: cdr_bwsel_prop_acqcdr [13:12] */ 942 #define DSC_B_DSC_SM_CTRL_7_CDR_BWSEL_PROP_ACQCDR_MASK 0x3000 943 #define DSC_B_DSC_SM_CTRL_7_CDR_BWSEL_PROP_ACQCDR_ALIGN 0 944 #define DSC_B_DSC_SM_CTRL_7_CDR_BWSEL_PROP_ACQCDR_BITS 2 945 #define DSC_B_DSC_SM_CTRL_7_CDR_BWSEL_PROP_ACQCDR_SHIFT 12 946 947 /* DSC_B :: DSC_SM_CTRL_7 :: cdr_bwsel_integ_norm [11:08] */ 948 #define DSC_B_DSC_SM_CTRL_7_CDR_BWSEL_INTEG_NORM_MASK 0x0f00 949 #define DSC_B_DSC_SM_CTRL_7_CDR_BWSEL_INTEG_NORM_ALIGN 0 950 #define DSC_B_DSC_SM_CTRL_7_CDR_BWSEL_INTEG_NORM_BITS 4 951 #define DSC_B_DSC_SM_CTRL_7_CDR_BWSEL_INTEG_NORM_SHIFT 8 952 953 /* DSC_B :: DSC_SM_CTRL_7 :: cdr_bwsel_integ_eee_acqcdr [07:04] */ 954 #define DSC_B_DSC_SM_CTRL_7_CDR_BWSEL_INTEG_EEE_ACQCDR_MASK 0x00f0 955 #define DSC_B_DSC_SM_CTRL_7_CDR_BWSEL_INTEG_EEE_ACQCDR_ALIGN 0 956 #define DSC_B_DSC_SM_CTRL_7_CDR_BWSEL_INTEG_EEE_ACQCDR_BITS 4 957 #define DSC_B_DSC_SM_CTRL_7_CDR_BWSEL_INTEG_EEE_ACQCDR_SHIFT 4 958 959 /* DSC_B :: DSC_SM_CTRL_7 :: cdr_bwsel_integ_acqcdr [03:00] */ 960 #define DSC_B_DSC_SM_CTRL_7_CDR_BWSEL_INTEG_ACQCDR_MASK 0x000f 961 #define DSC_B_DSC_SM_CTRL_7_CDR_BWSEL_INTEG_ACQCDR_ALIGN 0 962 #define DSC_B_DSC_SM_CTRL_7_CDR_BWSEL_INTEG_ACQCDR_BITS 4 963 #define DSC_B_DSC_SM_CTRL_7_CDR_BWSEL_INTEG_ACQCDR_SHIFT 0 964 965 966 /**************************************************************************** 967 * DSC_B :: DSC_SM_CTRL_8 968 */ 969 /* DSC_B :: DSC_SM_CTRL_8 :: cdr_bwsel_prop_eee_acqcdr [15:14] */ 970 #define DSC_B_DSC_SM_CTRL_8_CDR_BWSEL_PROP_EEE_ACQCDR_MASK 0xc000 971 #define DSC_B_DSC_SM_CTRL_8_CDR_BWSEL_PROP_EEE_ACQCDR_ALIGN 0 972 #define DSC_B_DSC_SM_CTRL_8_CDR_BWSEL_PROP_EEE_ACQCDR_BITS 2 973 #define DSC_B_DSC_SM_CTRL_8_CDR_BWSEL_PROP_EEE_ACQCDR_SHIFT 14 974 975 /* DSC_B :: DSC_SM_CTRL_8 :: reserved0 [13:12] */ 976 #define DSC_B_DSC_SM_CTRL_8_RESERVED0_MASK 0x3000 977 #define DSC_B_DSC_SM_CTRL_8_RESERVED0_ALIGN 0 978 #define DSC_B_DSC_SM_CTRL_8_RESERVED0_BITS 2 979 #define DSC_B_DSC_SM_CTRL_8_RESERVED0_SHIFT 12 980 981 /* DSC_B :: DSC_SM_CTRL_8 :: eee_phase_err_offset_en [11:10] */ 982 #define DSC_B_DSC_SM_CTRL_8_EEE_PHASE_ERR_OFFSET_EN_MASK 0x0c00 983 #define DSC_B_DSC_SM_CTRL_8_EEE_PHASE_ERR_OFFSET_EN_ALIGN 0 984 #define DSC_B_DSC_SM_CTRL_8_EEE_PHASE_ERR_OFFSET_EN_BITS 2 985 #define DSC_B_DSC_SM_CTRL_8_EEE_PHASE_ERR_OFFSET_EN_SHIFT 10 986 987 /* DSC_B :: DSC_SM_CTRL_8 :: phase_err_offset_en [09:08] */ 988 #define DSC_B_DSC_SM_CTRL_8_PHASE_ERR_OFFSET_EN_MASK 0x0300 989 #define DSC_B_DSC_SM_CTRL_8_PHASE_ERR_OFFSET_EN_ALIGN 0 990 #define DSC_B_DSC_SM_CTRL_8_PHASE_ERR_OFFSET_EN_BITS 2 991 #define DSC_B_DSC_SM_CTRL_8_PHASE_ERR_OFFSET_EN_SHIFT 8 992 993 /* DSC_B :: DSC_SM_CTRL_8 :: eee_phase_err_offset [07:04] */ 994 #define DSC_B_DSC_SM_CTRL_8_EEE_PHASE_ERR_OFFSET_MASK 0x00f0 995 #define DSC_B_DSC_SM_CTRL_8_EEE_PHASE_ERR_OFFSET_ALIGN 0 996 #define DSC_B_DSC_SM_CTRL_8_EEE_PHASE_ERR_OFFSET_BITS 4 997 #define DSC_B_DSC_SM_CTRL_8_EEE_PHASE_ERR_OFFSET_SHIFT 4 998 999 /* DSC_B :: DSC_SM_CTRL_8 :: phase_err_offset [03:00] */ 1000 #define DSC_B_DSC_SM_CTRL_8_PHASE_ERR_OFFSET_MASK 0x000f 1001 #define DSC_B_DSC_SM_CTRL_8_PHASE_ERR_OFFSET_ALIGN 0 1002 #define DSC_B_DSC_SM_CTRL_8_PHASE_ERR_OFFSET_BITS 4 1003 #define DSC_B_DSC_SM_CTRL_8_PHASE_ERR_OFFSET_SHIFT 0 1004 1005 1006 /**************************************************************************** 1007 * DSC_B :: DSC_SM_CTRL_9 1008 */ 1009 /* DSC_B :: DSC_SM_CTRL_9 :: reserved0 [15:02] */ 1010 #define DSC_B_DSC_SM_CTRL_9_RESERVED0_MASK 0xfffc 1011 #define DSC_B_DSC_SM_CTRL_9_RESERVED0_ALIGN 0 1012 #define DSC_B_DSC_SM_CTRL_9_RESERVED0_BITS 14 1013 #define DSC_B_DSC_SM_CTRL_9_RESERVED0_SHIFT 2 1014 1015 /* DSC_B :: DSC_SM_CTRL_9 :: rx_restart_pmd_hold [01:01] */ 1016 #define DSC_B_DSC_SM_CTRL_9_RX_RESTART_PMD_HOLD_MASK 0x0002 1017 #define DSC_B_DSC_SM_CTRL_9_RX_RESTART_PMD_HOLD_ALIGN 0 1018 #define DSC_B_DSC_SM_CTRL_9_RX_RESTART_PMD_HOLD_BITS 1 1019 #define DSC_B_DSC_SM_CTRL_9_RX_RESTART_PMD_HOLD_SHIFT 1 1020 1021 /* DSC_B :: DSC_SM_CTRL_9 :: rx_restart_pmd [00:00] */ 1022 #define DSC_B_DSC_SM_CTRL_9_RX_RESTART_PMD_MASK 0x0001 1023 #define DSC_B_DSC_SM_CTRL_9_RX_RESTART_PMD_ALIGN 0 1024 #define DSC_B_DSC_SM_CTRL_9_RX_RESTART_PMD_BITS 1 1025 #define DSC_B_DSC_SM_CTRL_9_RX_RESTART_PMD_SHIFT 0 1026 1027 1028 /**************************************************************************** 1029 * DSC_B :: DSC_SM_STATUS_DSC_LOCK 1030 */ 1031 /* DSC_B :: DSC_SM_STATUS_DSC_LOCK :: eee_measure_cnt [15:07] */ 1032 #define DSC_B_DSC_SM_STATUS_DSC_LOCK_EEE_MEASURE_CNT_MASK 0xff80 1033 #define DSC_B_DSC_SM_STATUS_DSC_LOCK_EEE_MEASURE_CNT_ALIGN 0 1034 #define DSC_B_DSC_SM_STATUS_DSC_LOCK_EEE_MEASURE_CNT_BITS 9 1035 #define DSC_B_DSC_SM_STATUS_DSC_LOCK_EEE_MEASURE_CNT_SHIFT 7 1036 1037 /* DSC_B :: DSC_SM_STATUS_DSC_LOCK :: reserved0 [06:02] */ 1038 #define DSC_B_DSC_SM_STATUS_DSC_LOCK_RESERVED0_MASK 0x007c 1039 #define DSC_B_DSC_SM_STATUS_DSC_LOCK_RESERVED0_ALIGN 0 1040 #define DSC_B_DSC_SM_STATUS_DSC_LOCK_RESERVED0_BITS 5 1041 #define DSC_B_DSC_SM_STATUS_DSC_LOCK_RESERVED0_SHIFT 2 1042 1043 /* DSC_B :: DSC_SM_STATUS_DSC_LOCK :: meas_incomplete [01:01] */ 1044 #define DSC_B_DSC_SM_STATUS_DSC_LOCK_MEAS_INCOMPLETE_MASK 0x0002 1045 #define DSC_B_DSC_SM_STATUS_DSC_LOCK_MEAS_INCOMPLETE_ALIGN 0 1046 #define DSC_B_DSC_SM_STATUS_DSC_LOCK_MEAS_INCOMPLETE_BITS 1 1047 #define DSC_B_DSC_SM_STATUS_DSC_LOCK_MEAS_INCOMPLETE_SHIFT 1 1048 1049 /* DSC_B :: DSC_SM_STATUS_DSC_LOCK :: rx_dsc_lock [00:00] */ 1050 #define DSC_B_DSC_SM_STATUS_DSC_LOCK_RX_DSC_LOCK_MASK 0x0001 1051 #define DSC_B_DSC_SM_STATUS_DSC_LOCK_RX_DSC_LOCK_ALIGN 0 1052 #define DSC_B_DSC_SM_STATUS_DSC_LOCK_RX_DSC_LOCK_BITS 1 1053 #define DSC_B_DSC_SM_STATUS_DSC_LOCK_RX_DSC_LOCK_SHIFT 0 1054 1055 1056 /**************************************************************************** 1057 * DSC_B :: DSC_SM_STATUS_DSC_STATE_ONE_HOT 1058 */ 1059 /* DSC_B :: DSC_SM_STATUS_DSC_STATE_ONE_HOT :: reserved0 [15:10] */ 1060 #define DSC_B_DSC_SM_STATUS_DSC_STATE_ONE_HOT_RESERVED0_MASK 0xfc00 1061 #define DSC_B_DSC_SM_STATUS_DSC_STATE_ONE_HOT_RESERVED0_ALIGN 0 1062 #define DSC_B_DSC_SM_STATUS_DSC_STATE_ONE_HOT_RESERVED0_BITS 6 1063 #define DSC_B_DSC_SM_STATUS_DSC_STATE_ONE_HOT_RESERVED0_SHIFT 10 1064 1065 /* DSC_B :: DSC_SM_STATUS_DSC_STATE_ONE_HOT :: dsc_state_one_hot [09:00] */ 1066 #define DSC_B_DSC_SM_STATUS_DSC_STATE_ONE_HOT_DSC_STATE_ONE_HOT_MASK 0x03ff 1067 #define DSC_B_DSC_SM_STATUS_DSC_STATE_ONE_HOT_DSC_STATE_ONE_HOT_ALIGN 0 1068 #define DSC_B_DSC_SM_STATUS_DSC_STATE_ONE_HOT_DSC_STATE_ONE_HOT_BITS 10 1069 #define DSC_B_DSC_SM_STATUS_DSC_STATE_ONE_HOT_DSC_STATE_ONE_HOT_SHIFT 0 1070 1071 1072 /**************************************************************************** 1073 * DSC_B :: DSC_SM_STATUS_DSC_STATE_EEE_ONE_HOT 1074 */ 1075 /* DSC_B :: DSC_SM_STATUS_DSC_STATE_EEE_ONE_HOT :: reserved0 [15:07] */ 1076 #define DSC_B_DSC_SM_STATUS_DSC_STATE_EEE_ONE_HOT_RESERVED0_MASK 0xff80 1077 #define DSC_B_DSC_SM_STATUS_DSC_STATE_EEE_ONE_HOT_RESERVED0_ALIGN 0 1078 #define DSC_B_DSC_SM_STATUS_DSC_STATE_EEE_ONE_HOT_RESERVED0_BITS 9 1079 #define DSC_B_DSC_SM_STATUS_DSC_STATE_EEE_ONE_HOT_RESERVED0_SHIFT 7 1080 1081 /* DSC_B :: DSC_SM_STATUS_DSC_STATE_EEE_ONE_HOT :: dsc_state_eee_one_hot [06:00] */ 1082 #define DSC_B_DSC_SM_STATUS_DSC_STATE_EEE_ONE_HOT_DSC_STATE_EEE_ONE_HOT_MASK 0x007f 1083 #define DSC_B_DSC_SM_STATUS_DSC_STATE_EEE_ONE_HOT_DSC_STATE_EEE_ONE_HOT_ALIGN 0 1084 #define DSC_B_DSC_SM_STATUS_DSC_STATE_EEE_ONE_HOT_DSC_STATE_EEE_ONE_HOT_BITS 7 1085 #define DSC_B_DSC_SM_STATUS_DSC_STATE_EEE_ONE_HOT_DSC_STATE_EEE_ONE_HOT_SHIFT 0 1086 1087 1088 /**************************************************************************** 1089 * DSC_B :: DSC_SM_STATUS_RESTART 1090 */ 1091 /* DSC_B :: DSC_SM_STATUS_RESTART :: reserved0 [15:04] */ 1092 #define DSC_B_DSC_SM_STATUS_RESTART_RESERVED0_MASK 0xfff0 1093 #define DSC_B_DSC_SM_STATUS_RESTART_RESERVED0_ALIGN 0 1094 #define DSC_B_DSC_SM_STATUS_RESTART_RESERVED0_BITS 12 1095 #define DSC_B_DSC_SM_STATUS_RESTART_RESERVED0_SHIFT 4 1096 1097 /* DSC_B :: DSC_SM_STATUS_RESTART :: eee_quiet_from_eee_states [03:03] */ 1098 #define DSC_B_DSC_SM_STATUS_RESTART_EEE_QUIET_FROM_EEE_STATES_MASK 0x0008 1099 #define DSC_B_DSC_SM_STATUS_RESTART_EEE_QUIET_FROM_EEE_STATES_ALIGN 0 1100 #define DSC_B_DSC_SM_STATUS_RESTART_EEE_QUIET_FROM_EEE_STATES_BITS 1 1101 #define DSC_B_DSC_SM_STATUS_RESTART_EEE_QUIET_FROM_EEE_STATES_SHIFT 3 1102 1103 /* DSC_B :: DSC_SM_STATUS_RESTART :: restart_pmd_restart [02:02] */ 1104 #define DSC_B_DSC_SM_STATUS_RESTART_RESTART_PMD_RESTART_MASK 0x0004 1105 #define DSC_B_DSC_SM_STATUS_RESTART_RESTART_PMD_RESTART_ALIGN 0 1106 #define DSC_B_DSC_SM_STATUS_RESTART_RESTART_PMD_RESTART_BITS 1 1107 #define DSC_B_DSC_SM_STATUS_RESTART_RESTART_PMD_RESTART_SHIFT 2 1108 1109 /* DSC_B :: DSC_SM_STATUS_RESTART :: restart_sigdet [01:01] */ 1110 #define DSC_B_DSC_SM_STATUS_RESTART_RESTART_SIGDET_MASK 0x0002 1111 #define DSC_B_DSC_SM_STATUS_RESTART_RESTART_SIGDET_ALIGN 0 1112 #define DSC_B_DSC_SM_STATUS_RESTART_RESTART_SIGDET_BITS 1 1113 #define DSC_B_DSC_SM_STATUS_RESTART_RESTART_SIGDET_SHIFT 1 1114 1115 /* DSC_B :: DSC_SM_STATUS_RESTART :: restart_pi_ext_mode [00:00] */ 1116 #define DSC_B_DSC_SM_STATUS_RESTART_RESTART_PI_EXT_MODE_MASK 0x0001 1117 #define DSC_B_DSC_SM_STATUS_RESTART_RESTART_PI_EXT_MODE_ALIGN 0 1118 #define DSC_B_DSC_SM_STATUS_RESTART_RESTART_PI_EXT_MODE_BITS 1 1119 #define DSC_B_DSC_SM_STATUS_RESTART_RESTART_PI_EXT_MODE_SHIFT 0 1120 1121 1122 /**************************************************************************** 1123 * DSC_B :: DSC_SM_STATUS_DSC_STATE 1124 */ 1125 /* DSC_B :: DSC_SM_STATUS_DSC_STATE :: dsc_state [15:11] */ 1126 #define DSC_B_DSC_SM_STATUS_DSC_STATE_DSC_STATE_MASK 0xf800 1127 #define DSC_B_DSC_SM_STATUS_DSC_STATE_DSC_STATE_ALIGN 0 1128 #define DSC_B_DSC_SM_STATUS_DSC_STATE_DSC_STATE_BITS 5 1129 #define DSC_B_DSC_SM_STATUS_DSC_STATE_DSC_STATE_SHIFT 11 1130 1131 /* DSC_B :: DSC_SM_STATUS_DSC_STATE :: dsc_sm_gp_uc_req [10:05] */ 1132 #define DSC_B_DSC_SM_STATUS_DSC_STATE_DSC_SM_GP_UC_REQ_MASK 0x07e0 1133 #define DSC_B_DSC_SM_STATUS_DSC_STATE_DSC_SM_GP_UC_REQ_ALIGN 0 1134 #define DSC_B_DSC_SM_STATUS_DSC_STATE_DSC_SM_GP_UC_REQ_BITS 6 1135 #define DSC_B_DSC_SM_STATUS_DSC_STATE_DSC_SM_GP_UC_REQ_SHIFT 5 1136 1137 /* DSC_B :: DSC_SM_STATUS_DSC_STATE :: dsc_sm_ready_for_cmd [04:04] */ 1138 #define DSC_B_DSC_SM_STATUS_DSC_STATE_DSC_SM_READY_FOR_CMD_MASK 0x0010 1139 #define DSC_B_DSC_SM_STATUS_DSC_STATE_DSC_SM_READY_FOR_CMD_ALIGN 0 1140 #define DSC_B_DSC_SM_STATUS_DSC_STATE_DSC_SM_READY_FOR_CMD_BITS 1 1141 #define DSC_B_DSC_SM_STATUS_DSC_STATE_DSC_SM_READY_FOR_CMD_SHIFT 4 1142 1143 /* DSC_B :: DSC_SM_STATUS_DSC_STATE :: dsc_sm_scratch [03:00] */ 1144 #define DSC_B_DSC_SM_STATUS_DSC_STATE_DSC_SM_SCRATCH_MASK 0x000f 1145 #define DSC_B_DSC_SM_STATUS_DSC_STATE_DSC_SM_SCRATCH_ALIGN 0 1146 #define DSC_B_DSC_SM_STATUS_DSC_STATE_DSC_SM_SCRATCH_BITS 4 1147 #define DSC_B_DSC_SM_STATUS_DSC_STATE_DSC_SM_SCRATCH_SHIFT 0 1148 1149 1150 /**************************************************************************** 1151 * eagle_tsc_dsc_blk_DSC_C 1152 */ 1153 /**************************************************************************** 1154 * DSC_C :: DFE_COMMON_CTL 1155 */ 1156 /* DSC_C :: DFE_COMMON_CTL :: dfe_acc_hys_en [15:15] */ 1157 #define DSC_C_DFE_COMMON_CTL_DFE_ACC_HYS_EN_MASK 0x8000 1158 #define DSC_C_DFE_COMMON_CTL_DFE_ACC_HYS_EN_ALIGN 0 1159 #define DSC_C_DFE_COMMON_CTL_DFE_ACC_HYS_EN_BITS 1 1160 #define DSC_C_DFE_COMMON_CTL_DFE_ACC_HYS_EN_SHIFT 15 1161 1162 /* DSC_C :: DFE_COMMON_CTL :: dfe_allow_simult [14:14] */ 1163 #define DSC_C_DFE_COMMON_CTL_DFE_ALLOW_SIMULT_MASK 0x4000 1164 #define DSC_C_DFE_COMMON_CTL_DFE_ALLOW_SIMULT_ALIGN 0 1165 #define DSC_C_DFE_COMMON_CTL_DFE_ALLOW_SIMULT_BITS 1 1166 #define DSC_C_DFE_COMMON_CTL_DFE_ALLOW_SIMULT_SHIFT 14 1167 1168 /* DSC_C :: DFE_COMMON_CTL :: dfe_update_gain [13:13] */ 1169 #define DSC_C_DFE_COMMON_CTL_DFE_UPDATE_GAIN_MASK 0x2000 1170 #define DSC_C_DFE_COMMON_CTL_DFE_UPDATE_GAIN_ALIGN 0 1171 #define DSC_C_DFE_COMMON_CTL_DFE_UPDATE_GAIN_BITS 1 1172 #define DSC_C_DFE_COMMON_CTL_DFE_UPDATE_GAIN_SHIFT 13 1173 1174 /* DSC_C :: DFE_COMMON_CTL :: reserved0 [12:00] */ 1175 #define DSC_C_DFE_COMMON_CTL_RESERVED0_MASK 0x1fff 1176 #define DSC_C_DFE_COMMON_CTL_RESERVED0_ALIGN 0 1177 #define DSC_C_DFE_COMMON_CTL_RESERVED0_BITS 13 1178 #define DSC_C_DFE_COMMON_CTL_RESERVED0_SHIFT 0 1179 1180 1181 /**************************************************************************** 1182 * DSC_C :: DFE_1_CTL 1183 */ 1184 /* DSC_C :: DFE_1_CTL :: dfe_1_en [15:15] */ 1185 #define DSC_C_DFE_1_CTL_DFE_1_EN_MASK 0x8000 1186 #define DSC_C_DFE_1_CTL_DFE_1_EN_ALIGN 0 1187 #define DSC_C_DFE_1_CTL_DFE_1_EN_BITS 1 1188 #define DSC_C_DFE_1_CTL_DFE_1_EN_SHIFT 15 1189 1190 /* DSC_C :: DFE_1_CTL :: dfe_1_err_sel [14:13] */ 1191 #define DSC_C_DFE_1_CTL_DFE_1_ERR_SEL_MASK 0x6000 1192 #define DSC_C_DFE_1_CTL_DFE_1_ERR_SEL_ALIGN 0 1193 #define DSC_C_DFE_1_CTL_DFE_1_ERR_SEL_BITS 2 1194 #define DSC_C_DFE_1_CTL_DFE_1_ERR_SEL_SHIFT 13 1195 1196 /* DSC_C :: DFE_1_CTL :: dfe_1_gradient_invert [12:12] */ 1197 #define DSC_C_DFE_1_CTL_DFE_1_GRADIENT_INVERT_MASK 0x1000 1198 #define DSC_C_DFE_1_CTL_DFE_1_GRADIENT_INVERT_ALIGN 0 1199 #define DSC_C_DFE_1_CTL_DFE_1_GRADIENT_INVERT_BITS 1 1200 #define DSC_C_DFE_1_CTL_DFE_1_GRADIENT_INVERT_SHIFT 12 1201 1202 /* DSC_C :: DFE_1_CTL :: dfe_1_err_gain [11:10] */ 1203 #define DSC_C_DFE_1_CTL_DFE_1_ERR_GAIN_MASK 0x0c00 1204 #define DSC_C_DFE_1_CTL_DFE_1_ERR_GAIN_ALIGN 0 1205 #define DSC_C_DFE_1_CTL_DFE_1_ERR_GAIN_BITS 2 1206 #define DSC_C_DFE_1_CTL_DFE_1_ERR_GAIN_SHIFT 10 1207 1208 /* DSC_C :: DFE_1_CTL :: dfe_1_inv_m1 [09:09] */ 1209 #define DSC_C_DFE_1_CTL_DFE_1_INV_M1_MASK 0x0200 1210 #define DSC_C_DFE_1_CTL_DFE_1_INV_M1_ALIGN 0 1211 #define DSC_C_DFE_1_CTL_DFE_1_INV_M1_BITS 1 1212 #define DSC_C_DFE_1_CTL_DFE_1_INV_M1_SHIFT 9 1213 1214 /* DSC_C :: DFE_1_CTL :: dfe_1_inv_p1 [08:08] */ 1215 #define DSC_C_DFE_1_CTL_DFE_1_INV_P1_MASK 0x0100 1216 #define DSC_C_DFE_1_CTL_DFE_1_INV_P1_ALIGN 0 1217 #define DSC_C_DFE_1_CTL_DFE_1_INV_P1_BITS 1 1218 #define DSC_C_DFE_1_CTL_DFE_1_INV_P1_SHIFT 8 1219 1220 /* DSC_C :: DFE_1_CTL :: reserved0 [07:02] */ 1221 #define DSC_C_DFE_1_CTL_RESERVED0_MASK 0x00fc 1222 #define DSC_C_DFE_1_CTL_RESERVED0_ALIGN 0 1223 #define DSC_C_DFE_1_CTL_RESERVED0_BITS 6 1224 #define DSC_C_DFE_1_CTL_RESERVED0_SHIFT 2 1225 1226 /* DSC_C :: DFE_1_CTL :: dfe_1_cmn_only [01:01] */ 1227 #define DSC_C_DFE_1_CTL_DFE_1_CMN_ONLY_MASK 0x0002 1228 #define DSC_C_DFE_1_CTL_DFE_1_CMN_ONLY_ALIGN 0 1229 #define DSC_C_DFE_1_CTL_DFE_1_CMN_ONLY_BITS 1 1230 #define DSC_C_DFE_1_CTL_DFE_1_CMN_ONLY_SHIFT 1 1231 1232 /* DSC_C :: DFE_1_CTL :: dfe_1_acc_clr [00:00] */ 1233 #define DSC_C_DFE_1_CTL_DFE_1_ACC_CLR_MASK 0x0001 1234 #define DSC_C_DFE_1_CTL_DFE_1_ACC_CLR_ALIGN 0 1235 #define DSC_C_DFE_1_CTL_DFE_1_ACC_CLR_BITS 1 1236 #define DSC_C_DFE_1_CTL_DFE_1_ACC_CLR_SHIFT 0 1237 1238 1239 /**************************************************************************** 1240 * DSC_C :: DFE_1_PAT_CTL 1241 */ 1242 /* DSC_C :: DFE_1_PAT_CTL :: reserved0 [15:14] */ 1243 #define DSC_C_DFE_1_PAT_CTL_RESERVED0_MASK 0xc000 1244 #define DSC_C_DFE_1_PAT_CTL_RESERVED0_ALIGN 0 1245 #define DSC_C_DFE_1_PAT_CTL_RESERVED0_BITS 2 1246 #define DSC_C_DFE_1_PAT_CTL_RESERVED0_SHIFT 14 1247 1248 /* DSC_C :: DFE_1_PAT_CTL :: dfe_1_pattern_bit_en [13:08] */ 1249 #define DSC_C_DFE_1_PAT_CTL_DFE_1_PATTERN_BIT_EN_MASK 0x3f00 1250 #define DSC_C_DFE_1_PAT_CTL_DFE_1_PATTERN_BIT_EN_ALIGN 0 1251 #define DSC_C_DFE_1_PAT_CTL_DFE_1_PATTERN_BIT_EN_BITS 6 1252 #define DSC_C_DFE_1_PAT_CTL_DFE_1_PATTERN_BIT_EN_SHIFT 8 1253 1254 /* DSC_C :: DFE_1_PAT_CTL :: reserved1 [07:06] */ 1255 #define DSC_C_DFE_1_PAT_CTL_RESERVED1_MASK 0x00c0 1256 #define DSC_C_DFE_1_PAT_CTL_RESERVED1_ALIGN 0 1257 #define DSC_C_DFE_1_PAT_CTL_RESERVED1_BITS 2 1258 #define DSC_C_DFE_1_PAT_CTL_RESERVED1_SHIFT 6 1259 1260 /* DSC_C :: DFE_1_PAT_CTL :: dfe_1_pattern [05:00] */ 1261 #define DSC_C_DFE_1_PAT_CTL_DFE_1_PATTERN_MASK 0x003f 1262 #define DSC_C_DFE_1_PAT_CTL_DFE_1_PATTERN_ALIGN 0 1263 #define DSC_C_DFE_1_PAT_CTL_DFE_1_PATTERN_BITS 6 1264 #define DSC_C_DFE_1_PAT_CTL_DFE_1_PATTERN_SHIFT 0 1265 1266 1267 /**************************************************************************** 1268 * DSC_C :: DFE_2_CTL 1269 */ 1270 /* DSC_C :: DFE_2_CTL :: dfe_2_en [15:15] */ 1271 #define DSC_C_DFE_2_CTL_DFE_2_EN_MASK 0x8000 1272 #define DSC_C_DFE_2_CTL_DFE_2_EN_ALIGN 0 1273 #define DSC_C_DFE_2_CTL_DFE_2_EN_BITS 1 1274 #define DSC_C_DFE_2_CTL_DFE_2_EN_SHIFT 15 1275 1276 /* DSC_C :: DFE_2_CTL :: dfe_2_err_sel [14:13] */ 1277 #define DSC_C_DFE_2_CTL_DFE_2_ERR_SEL_MASK 0x6000 1278 #define DSC_C_DFE_2_CTL_DFE_2_ERR_SEL_ALIGN 0 1279 #define DSC_C_DFE_2_CTL_DFE_2_ERR_SEL_BITS 2 1280 #define DSC_C_DFE_2_CTL_DFE_2_ERR_SEL_SHIFT 13 1281 1282 /* DSC_C :: DFE_2_CTL :: dfe_2_gradient_invert [12:12] */ 1283 #define DSC_C_DFE_2_CTL_DFE_2_GRADIENT_INVERT_MASK 0x1000 1284 #define DSC_C_DFE_2_CTL_DFE_2_GRADIENT_INVERT_ALIGN 0 1285 #define DSC_C_DFE_2_CTL_DFE_2_GRADIENT_INVERT_BITS 1 1286 #define DSC_C_DFE_2_CTL_DFE_2_GRADIENT_INVERT_SHIFT 12 1287 1288 /* DSC_C :: DFE_2_CTL :: dfe_2_err_gain [11:10] */ 1289 #define DSC_C_DFE_2_CTL_DFE_2_ERR_GAIN_MASK 0x0c00 1290 #define DSC_C_DFE_2_CTL_DFE_2_ERR_GAIN_ALIGN 0 1291 #define DSC_C_DFE_2_CTL_DFE_2_ERR_GAIN_BITS 2 1292 #define DSC_C_DFE_2_CTL_DFE_2_ERR_GAIN_SHIFT 10 1293 1294 /* DSC_C :: DFE_2_CTL :: dfe_2_inv_m1 [09:09] */ 1295 #define DSC_C_DFE_2_CTL_DFE_2_INV_M1_MASK 0x0200 1296 #define DSC_C_DFE_2_CTL_DFE_2_INV_M1_ALIGN 0 1297 #define DSC_C_DFE_2_CTL_DFE_2_INV_M1_BITS 1 1298 #define DSC_C_DFE_2_CTL_DFE_2_INV_M1_SHIFT 9 1299 1300 /* DSC_C :: DFE_2_CTL :: dfe_2_inv_p1 [08:08] */ 1301 #define DSC_C_DFE_2_CTL_DFE_2_INV_P1_MASK 0x0100 1302 #define DSC_C_DFE_2_CTL_DFE_2_INV_P1_ALIGN 0 1303 #define DSC_C_DFE_2_CTL_DFE_2_INV_P1_BITS 1 1304 #define DSC_C_DFE_2_CTL_DFE_2_INV_P1_SHIFT 8 1305 1306 /* DSC_C :: DFE_2_CTL :: reserved0 [07:02] */ 1307 #define DSC_C_DFE_2_CTL_RESERVED0_MASK 0x00fc 1308 #define DSC_C_DFE_2_CTL_RESERVED0_ALIGN 0 1309 #define DSC_C_DFE_2_CTL_RESERVED0_BITS 6 1310 #define DSC_C_DFE_2_CTL_RESERVED0_SHIFT 2 1311 1312 /* DSC_C :: DFE_2_CTL :: dfe_2_cmn_only [01:01] */ 1313 #define DSC_C_DFE_2_CTL_DFE_2_CMN_ONLY_MASK 0x0002 1314 #define DSC_C_DFE_2_CTL_DFE_2_CMN_ONLY_ALIGN 0 1315 #define DSC_C_DFE_2_CTL_DFE_2_CMN_ONLY_BITS 1 1316 #define DSC_C_DFE_2_CTL_DFE_2_CMN_ONLY_SHIFT 1 1317 1318 /* DSC_C :: DFE_2_CTL :: dfe_2_acc_clr [00:00] */ 1319 #define DSC_C_DFE_2_CTL_DFE_2_ACC_CLR_MASK 0x0001 1320 #define DSC_C_DFE_2_CTL_DFE_2_ACC_CLR_ALIGN 0 1321 #define DSC_C_DFE_2_CTL_DFE_2_ACC_CLR_BITS 1 1322 #define DSC_C_DFE_2_CTL_DFE_2_ACC_CLR_SHIFT 0 1323 1324 1325 /**************************************************************************** 1326 * DSC_C :: DFE_2_PAT_CTL 1327 */ 1328 /* DSC_C :: DFE_2_PAT_CTL :: reserved0 [15:14] */ 1329 #define DSC_C_DFE_2_PAT_CTL_RESERVED0_MASK 0xc000 1330 #define DSC_C_DFE_2_PAT_CTL_RESERVED0_ALIGN 0 1331 #define DSC_C_DFE_2_PAT_CTL_RESERVED0_BITS 2 1332 #define DSC_C_DFE_2_PAT_CTL_RESERVED0_SHIFT 14 1333 1334 /* DSC_C :: DFE_2_PAT_CTL :: dfe_2_pattern_bit_en [13:08] */ 1335 #define DSC_C_DFE_2_PAT_CTL_DFE_2_PATTERN_BIT_EN_MASK 0x3f00 1336 #define DSC_C_DFE_2_PAT_CTL_DFE_2_PATTERN_BIT_EN_ALIGN 0 1337 #define DSC_C_DFE_2_PAT_CTL_DFE_2_PATTERN_BIT_EN_BITS 6 1338 #define DSC_C_DFE_2_PAT_CTL_DFE_2_PATTERN_BIT_EN_SHIFT 8 1339 1340 /* DSC_C :: DFE_2_PAT_CTL :: reserved1 [07:06] */ 1341 #define DSC_C_DFE_2_PAT_CTL_RESERVED1_MASK 0x00c0 1342 #define DSC_C_DFE_2_PAT_CTL_RESERVED1_ALIGN 0 1343 #define DSC_C_DFE_2_PAT_CTL_RESERVED1_BITS 2 1344 #define DSC_C_DFE_2_PAT_CTL_RESERVED1_SHIFT 6 1345 1346 /* DSC_C :: DFE_2_PAT_CTL :: dfe_2_pattern [05:00] */ 1347 #define DSC_C_DFE_2_PAT_CTL_DFE_2_PATTERN_MASK 0x003f 1348 #define DSC_C_DFE_2_PAT_CTL_DFE_2_PATTERN_ALIGN 0 1349 #define DSC_C_DFE_2_PAT_CTL_DFE_2_PATTERN_BITS 6 1350 #define DSC_C_DFE_2_PAT_CTL_DFE_2_PATTERN_SHIFT 0 1351 1352 1353 /**************************************************************************** 1354 * DSC_C :: DFE_3_CTL 1355 */ 1356 /* DSC_C :: DFE_3_CTL :: dfe_3_en [15:15] */ 1357 #define DSC_C_DFE_3_CTL_DFE_3_EN_MASK 0x8000 1358 #define DSC_C_DFE_3_CTL_DFE_3_EN_ALIGN 0 1359 #define DSC_C_DFE_3_CTL_DFE_3_EN_BITS 1 1360 #define DSC_C_DFE_3_CTL_DFE_3_EN_SHIFT 15 1361 1362 /* DSC_C :: DFE_3_CTL :: dfe_3_err_sel [14:13] */ 1363 #define DSC_C_DFE_3_CTL_DFE_3_ERR_SEL_MASK 0x6000 1364 #define DSC_C_DFE_3_CTL_DFE_3_ERR_SEL_ALIGN 0 1365 #define DSC_C_DFE_3_CTL_DFE_3_ERR_SEL_BITS 2 1366 #define DSC_C_DFE_3_CTL_DFE_3_ERR_SEL_SHIFT 13 1367 1368 /* DSC_C :: DFE_3_CTL :: dfe_3_gradient_invert [12:12] */ 1369 #define DSC_C_DFE_3_CTL_DFE_3_GRADIENT_INVERT_MASK 0x1000 1370 #define DSC_C_DFE_3_CTL_DFE_3_GRADIENT_INVERT_ALIGN 0 1371 #define DSC_C_DFE_3_CTL_DFE_3_GRADIENT_INVERT_BITS 1 1372 #define DSC_C_DFE_3_CTL_DFE_3_GRADIENT_INVERT_SHIFT 12 1373 1374 /* DSC_C :: DFE_3_CTL :: dfe_3_err_gain [11:10] */ 1375 #define DSC_C_DFE_3_CTL_DFE_3_ERR_GAIN_MASK 0x0c00 1376 #define DSC_C_DFE_3_CTL_DFE_3_ERR_GAIN_ALIGN 0 1377 #define DSC_C_DFE_3_CTL_DFE_3_ERR_GAIN_BITS 2 1378 #define DSC_C_DFE_3_CTL_DFE_3_ERR_GAIN_SHIFT 10 1379 1380 /* DSC_C :: DFE_3_CTL :: dfe_3_inv_m1 [09:09] */ 1381 #define DSC_C_DFE_3_CTL_DFE_3_INV_M1_MASK 0x0200 1382 #define DSC_C_DFE_3_CTL_DFE_3_INV_M1_ALIGN 0 1383 #define DSC_C_DFE_3_CTL_DFE_3_INV_M1_BITS 1 1384 #define DSC_C_DFE_3_CTL_DFE_3_INV_M1_SHIFT 9 1385 1386 /* DSC_C :: DFE_3_CTL :: dfe_3_inv_p1 [08:08] */ 1387 #define DSC_C_DFE_3_CTL_DFE_3_INV_P1_MASK 0x0100 1388 #define DSC_C_DFE_3_CTL_DFE_3_INV_P1_ALIGN 0 1389 #define DSC_C_DFE_3_CTL_DFE_3_INV_P1_BITS 1 1390 #define DSC_C_DFE_3_CTL_DFE_3_INV_P1_SHIFT 8 1391 1392 /* DSC_C :: DFE_3_CTL :: reserved0 [07:01] */ 1393 #define DSC_C_DFE_3_CTL_RESERVED0_MASK 0x00fe 1394 #define DSC_C_DFE_3_CTL_RESERVED0_ALIGN 0 1395 #define DSC_C_DFE_3_CTL_RESERVED0_BITS 7 1396 #define DSC_C_DFE_3_CTL_RESERVED0_SHIFT 1 1397 1398 /* DSC_C :: DFE_3_CTL :: dfe_3_acc_clr [00:00] */ 1399 #define DSC_C_DFE_3_CTL_DFE_3_ACC_CLR_MASK 0x0001 1400 #define DSC_C_DFE_3_CTL_DFE_3_ACC_CLR_ALIGN 0 1401 #define DSC_C_DFE_3_CTL_DFE_3_ACC_CLR_BITS 1 1402 #define DSC_C_DFE_3_CTL_DFE_3_ACC_CLR_SHIFT 0 1403 1404 1405 /**************************************************************************** 1406 * DSC_C :: DFE_3_PAT_CTL 1407 */ 1408 /* DSC_C :: DFE_3_PAT_CTL :: reserved0 [15:14] */ 1409 #define DSC_C_DFE_3_PAT_CTL_RESERVED0_MASK 0xc000 1410 #define DSC_C_DFE_3_PAT_CTL_RESERVED0_ALIGN 0 1411 #define DSC_C_DFE_3_PAT_CTL_RESERVED0_BITS 2 1412 #define DSC_C_DFE_3_PAT_CTL_RESERVED0_SHIFT 14 1413 1414 /* DSC_C :: DFE_3_PAT_CTL :: dfe_3_pattern_bit_en [13:08] */ 1415 #define DSC_C_DFE_3_PAT_CTL_DFE_3_PATTERN_BIT_EN_MASK 0x3f00 1416 #define DSC_C_DFE_3_PAT_CTL_DFE_3_PATTERN_BIT_EN_ALIGN 0 1417 #define DSC_C_DFE_3_PAT_CTL_DFE_3_PATTERN_BIT_EN_BITS 6 1418 #define DSC_C_DFE_3_PAT_CTL_DFE_3_PATTERN_BIT_EN_SHIFT 8 1419 1420 /* DSC_C :: DFE_3_PAT_CTL :: reserved1 [07:06] */ 1421 #define DSC_C_DFE_3_PAT_CTL_RESERVED1_MASK 0x00c0 1422 #define DSC_C_DFE_3_PAT_CTL_RESERVED1_ALIGN 0 1423 #define DSC_C_DFE_3_PAT_CTL_RESERVED1_BITS 2 1424 #define DSC_C_DFE_3_PAT_CTL_RESERVED1_SHIFT 6 1425 1426 /* DSC_C :: DFE_3_PAT_CTL :: dfe_3_pattern [05:00] */ 1427 #define DSC_C_DFE_3_PAT_CTL_DFE_3_PATTERN_MASK 0x003f 1428 #define DSC_C_DFE_3_PAT_CTL_DFE_3_PATTERN_ALIGN 0 1429 #define DSC_C_DFE_3_PAT_CTL_DFE_3_PATTERN_BITS 6 1430 #define DSC_C_DFE_3_PAT_CTL_DFE_3_PATTERN_SHIFT 0 1431 1432 1433 /**************************************************************************** 1434 * DSC_C :: DFE_4_CTL 1435 */ 1436 /* DSC_C :: DFE_4_CTL :: dfe_4_en [15:15] */ 1437 #define DSC_C_DFE_4_CTL_DFE_4_EN_MASK 0x8000 1438 #define DSC_C_DFE_4_CTL_DFE_4_EN_ALIGN 0 1439 #define DSC_C_DFE_4_CTL_DFE_4_EN_BITS 1 1440 #define DSC_C_DFE_4_CTL_DFE_4_EN_SHIFT 15 1441 1442 /* DSC_C :: DFE_4_CTL :: dfe_4_err_sel [14:13] */ 1443 #define DSC_C_DFE_4_CTL_DFE_4_ERR_SEL_MASK 0x6000 1444 #define DSC_C_DFE_4_CTL_DFE_4_ERR_SEL_ALIGN 0 1445 #define DSC_C_DFE_4_CTL_DFE_4_ERR_SEL_BITS 2 1446 #define DSC_C_DFE_4_CTL_DFE_4_ERR_SEL_SHIFT 13 1447 1448 /* DSC_C :: DFE_4_CTL :: dfe_4_gradient_invert [12:12] */ 1449 #define DSC_C_DFE_4_CTL_DFE_4_GRADIENT_INVERT_MASK 0x1000 1450 #define DSC_C_DFE_4_CTL_DFE_4_GRADIENT_INVERT_ALIGN 0 1451 #define DSC_C_DFE_4_CTL_DFE_4_GRADIENT_INVERT_BITS 1 1452 #define DSC_C_DFE_4_CTL_DFE_4_GRADIENT_INVERT_SHIFT 12 1453 1454 /* DSC_C :: DFE_4_CTL :: dfe_4_err_gain [11:10] */ 1455 #define DSC_C_DFE_4_CTL_DFE_4_ERR_GAIN_MASK 0x0c00 1456 #define DSC_C_DFE_4_CTL_DFE_4_ERR_GAIN_ALIGN 0 1457 #define DSC_C_DFE_4_CTL_DFE_4_ERR_GAIN_BITS 2 1458 #define DSC_C_DFE_4_CTL_DFE_4_ERR_GAIN_SHIFT 10 1459 1460 /* DSC_C :: DFE_4_CTL :: dfe_4_inv_m1 [09:09] */ 1461 #define DSC_C_DFE_4_CTL_DFE_4_INV_M1_MASK 0x0200 1462 #define DSC_C_DFE_4_CTL_DFE_4_INV_M1_ALIGN 0 1463 #define DSC_C_DFE_4_CTL_DFE_4_INV_M1_BITS 1 1464 #define DSC_C_DFE_4_CTL_DFE_4_INV_M1_SHIFT 9 1465 1466 /* DSC_C :: DFE_4_CTL :: dfe_4_inv_p1 [08:08] */ 1467 #define DSC_C_DFE_4_CTL_DFE_4_INV_P1_MASK 0x0100 1468 #define DSC_C_DFE_4_CTL_DFE_4_INV_P1_ALIGN 0 1469 #define DSC_C_DFE_4_CTL_DFE_4_INV_P1_BITS 1 1470 #define DSC_C_DFE_4_CTL_DFE_4_INV_P1_SHIFT 8 1471 1472 /* DSC_C :: DFE_4_CTL :: reserved0 [07:01] */ 1473 #define DSC_C_DFE_4_CTL_RESERVED0_MASK 0x00fe 1474 #define DSC_C_DFE_4_CTL_RESERVED0_ALIGN 0 1475 #define DSC_C_DFE_4_CTL_RESERVED0_BITS 7 1476 #define DSC_C_DFE_4_CTL_RESERVED0_SHIFT 1 1477 1478 /* DSC_C :: DFE_4_CTL :: dfe_4_acc_clr [00:00] */ 1479 #define DSC_C_DFE_4_CTL_DFE_4_ACC_CLR_MASK 0x0001 1480 #define DSC_C_DFE_4_CTL_DFE_4_ACC_CLR_ALIGN 0 1481 #define DSC_C_DFE_4_CTL_DFE_4_ACC_CLR_BITS 1 1482 #define DSC_C_DFE_4_CTL_DFE_4_ACC_CLR_SHIFT 0 1483 1484 1485 /**************************************************************************** 1486 * DSC_C :: DFE_4_PAT_CTL 1487 */ 1488 /* DSC_C :: DFE_4_PAT_CTL :: reserved0 [15:14] */ 1489 #define DSC_C_DFE_4_PAT_CTL_RESERVED0_MASK 0xc000 1490 #define DSC_C_DFE_4_PAT_CTL_RESERVED0_ALIGN 0 1491 #define DSC_C_DFE_4_PAT_CTL_RESERVED0_BITS 2 1492 #define DSC_C_DFE_4_PAT_CTL_RESERVED0_SHIFT 14 1493 1494 /* DSC_C :: DFE_4_PAT_CTL :: dfe_4_pattern_bit_en [13:08] */ 1495 #define DSC_C_DFE_4_PAT_CTL_DFE_4_PATTERN_BIT_EN_MASK 0x3f00 1496 #define DSC_C_DFE_4_PAT_CTL_DFE_4_PATTERN_BIT_EN_ALIGN 0 1497 #define DSC_C_DFE_4_PAT_CTL_DFE_4_PATTERN_BIT_EN_BITS 6 1498 #define DSC_C_DFE_4_PAT_CTL_DFE_4_PATTERN_BIT_EN_SHIFT 8 1499 1500 /* DSC_C :: DFE_4_PAT_CTL :: reserved1 [07:06] */ 1501 #define DSC_C_DFE_4_PAT_CTL_RESERVED1_MASK 0x00c0 1502 #define DSC_C_DFE_4_PAT_CTL_RESERVED1_ALIGN 0 1503 #define DSC_C_DFE_4_PAT_CTL_RESERVED1_BITS 2 1504 #define DSC_C_DFE_4_PAT_CTL_RESERVED1_SHIFT 6 1505 1506 /* DSC_C :: DFE_4_PAT_CTL :: dfe_4_pattern [05:00] */ 1507 #define DSC_C_DFE_4_PAT_CTL_DFE_4_PATTERN_MASK 0x003f 1508 #define DSC_C_DFE_4_PAT_CTL_DFE_4_PATTERN_ALIGN 0 1509 #define DSC_C_DFE_4_PAT_CTL_DFE_4_PATTERN_BITS 6 1510 #define DSC_C_DFE_4_PAT_CTL_DFE_4_PATTERN_SHIFT 0 1511 1512 1513 /**************************************************************************** 1514 * DSC_C :: DFE_5_CTL 1515 */ 1516 /* DSC_C :: DFE_5_CTL :: dfe_5_en [15:15] */ 1517 #define DSC_C_DFE_5_CTL_DFE_5_EN_MASK 0x8000 1518 #define DSC_C_DFE_5_CTL_DFE_5_EN_ALIGN 0 1519 #define DSC_C_DFE_5_CTL_DFE_5_EN_BITS 1 1520 #define DSC_C_DFE_5_CTL_DFE_5_EN_SHIFT 15 1521 1522 /* DSC_C :: DFE_5_CTL :: dfe_5_err_sel [14:13] */ 1523 #define DSC_C_DFE_5_CTL_DFE_5_ERR_SEL_MASK 0x6000 1524 #define DSC_C_DFE_5_CTL_DFE_5_ERR_SEL_ALIGN 0 1525 #define DSC_C_DFE_5_CTL_DFE_5_ERR_SEL_BITS 2 1526 #define DSC_C_DFE_5_CTL_DFE_5_ERR_SEL_SHIFT 13 1527 1528 /* DSC_C :: DFE_5_CTL :: dfe_5_gradient_invert [12:12] */ 1529 #define DSC_C_DFE_5_CTL_DFE_5_GRADIENT_INVERT_MASK 0x1000 1530 #define DSC_C_DFE_5_CTL_DFE_5_GRADIENT_INVERT_ALIGN 0 1531 #define DSC_C_DFE_5_CTL_DFE_5_GRADIENT_INVERT_BITS 1 1532 #define DSC_C_DFE_5_CTL_DFE_5_GRADIENT_INVERT_SHIFT 12 1533 1534 /* DSC_C :: DFE_5_CTL :: dfe_5_err_gain [11:10] */ 1535 #define DSC_C_DFE_5_CTL_DFE_5_ERR_GAIN_MASK 0x0c00 1536 #define DSC_C_DFE_5_CTL_DFE_5_ERR_GAIN_ALIGN 0 1537 #define DSC_C_DFE_5_CTL_DFE_5_ERR_GAIN_BITS 2 1538 #define DSC_C_DFE_5_CTL_DFE_5_ERR_GAIN_SHIFT 10 1539 1540 /* DSC_C :: DFE_5_CTL :: dfe_5_inv_m1 [09:09] */ 1541 #define DSC_C_DFE_5_CTL_DFE_5_INV_M1_MASK 0x0200 1542 #define DSC_C_DFE_5_CTL_DFE_5_INV_M1_ALIGN 0 1543 #define DSC_C_DFE_5_CTL_DFE_5_INV_M1_BITS 1 1544 #define DSC_C_DFE_5_CTL_DFE_5_INV_M1_SHIFT 9 1545 1546 /* DSC_C :: DFE_5_CTL :: dfe_5_inv_p1 [08:08] */ 1547 #define DSC_C_DFE_5_CTL_DFE_5_INV_P1_MASK 0x0100 1548 #define DSC_C_DFE_5_CTL_DFE_5_INV_P1_ALIGN 0 1549 #define DSC_C_DFE_5_CTL_DFE_5_INV_P1_BITS 1 1550 #define DSC_C_DFE_5_CTL_DFE_5_INV_P1_SHIFT 8 1551 1552 /* DSC_C :: DFE_5_CTL :: reserved0 [07:01] */ 1553 #define DSC_C_DFE_5_CTL_RESERVED0_MASK 0x00fe 1554 #define DSC_C_DFE_5_CTL_RESERVED0_ALIGN 0 1555 #define DSC_C_DFE_5_CTL_RESERVED0_BITS 7 1556 #define DSC_C_DFE_5_CTL_RESERVED0_SHIFT 1 1557 1558 /* DSC_C :: DFE_5_CTL :: dfe_5_acc_clr [00:00] */ 1559 #define DSC_C_DFE_5_CTL_DFE_5_ACC_CLR_MASK 0x0001 1560 #define DSC_C_DFE_5_CTL_DFE_5_ACC_CLR_ALIGN 0 1561 #define DSC_C_DFE_5_CTL_DFE_5_ACC_CLR_BITS 1 1562 #define DSC_C_DFE_5_CTL_DFE_5_ACC_CLR_SHIFT 0 1563 1564 1565 /**************************************************************************** 1566 * DSC_C :: DFE_5_PAT_CTL 1567 */ 1568 /* DSC_C :: DFE_5_PAT_CTL :: reserved0 [15:14] */ 1569 #define DSC_C_DFE_5_PAT_CTL_RESERVED0_MASK 0xc000 1570 #define DSC_C_DFE_5_PAT_CTL_RESERVED0_ALIGN 0 1571 #define DSC_C_DFE_5_PAT_CTL_RESERVED0_BITS 2 1572 #define DSC_C_DFE_5_PAT_CTL_RESERVED0_SHIFT 14 1573 1574 /* DSC_C :: DFE_5_PAT_CTL :: dfe_5_pattern_bit_en [13:08] */ 1575 #define DSC_C_DFE_5_PAT_CTL_DFE_5_PATTERN_BIT_EN_MASK 0x3f00 1576 #define DSC_C_DFE_5_PAT_CTL_DFE_5_PATTERN_BIT_EN_ALIGN 0 1577 #define DSC_C_DFE_5_PAT_CTL_DFE_5_PATTERN_BIT_EN_BITS 6 1578 #define DSC_C_DFE_5_PAT_CTL_DFE_5_PATTERN_BIT_EN_SHIFT 8 1579 1580 /* DSC_C :: DFE_5_PAT_CTL :: reserved1 [07:06] */ 1581 #define DSC_C_DFE_5_PAT_CTL_RESERVED1_MASK 0x00c0 1582 #define DSC_C_DFE_5_PAT_CTL_RESERVED1_ALIGN 0 1583 #define DSC_C_DFE_5_PAT_CTL_RESERVED1_BITS 2 1584 #define DSC_C_DFE_5_PAT_CTL_RESERVED1_SHIFT 6 1585 1586 /* DSC_C :: DFE_5_PAT_CTL :: dfe_5_pattern [05:00] */ 1587 #define DSC_C_DFE_5_PAT_CTL_DFE_5_PATTERN_MASK 0x003f 1588 #define DSC_C_DFE_5_PAT_CTL_DFE_5_PATTERN_ALIGN 0 1589 #define DSC_C_DFE_5_PAT_CTL_DFE_5_PATTERN_BITS 6 1590 #define DSC_C_DFE_5_PAT_CTL_DFE_5_PATTERN_SHIFT 0 1591 1592 1593 /**************************************************************************** 1594 * DSC_C :: DFE_VGA_OVERRIDE 1595 */ 1596 /* DSC_C :: DFE_VGA_OVERRIDE :: dfe_vga_write_en [15:15] */ 1597 #define DSC_C_DFE_VGA_OVERRIDE_DFE_VGA_WRITE_EN_MASK 0x8000 1598 #define DSC_C_DFE_VGA_OVERRIDE_DFE_VGA_WRITE_EN_ALIGN 0 1599 #define DSC_C_DFE_VGA_OVERRIDE_DFE_VGA_WRITE_EN_BITS 1 1600 #define DSC_C_DFE_VGA_OVERRIDE_DFE_VGA_WRITE_EN_SHIFT 15 1601 1602 /* DSC_C :: DFE_VGA_OVERRIDE :: reserved0 [14:14] */ 1603 #define DSC_C_DFE_VGA_OVERRIDE_RESERVED0_MASK 0x4000 1604 #define DSC_C_DFE_VGA_OVERRIDE_RESERVED0_ALIGN 0 1605 #define DSC_C_DFE_VGA_OVERRIDE_RESERVED0_BITS 1 1606 #define DSC_C_DFE_VGA_OVERRIDE_RESERVED0_SHIFT 14 1607 1608 /* DSC_C :: DFE_VGA_OVERRIDE :: dfe_vga_write_tapsel [13:09] */ 1609 #define DSC_C_DFE_VGA_OVERRIDE_DFE_VGA_WRITE_TAPSEL_MASK 0x3e00 1610 #define DSC_C_DFE_VGA_OVERRIDE_DFE_VGA_WRITE_TAPSEL_ALIGN 0 1611 #define DSC_C_DFE_VGA_OVERRIDE_DFE_VGA_WRITE_TAPSEL_BITS 5 1612 #define DSC_C_DFE_VGA_OVERRIDE_DFE_VGA_WRITE_TAPSEL_SHIFT 9 1613 1614 /* DSC_C :: DFE_VGA_OVERRIDE :: dfe_vga_write_val [08:00] */ 1615 #define DSC_C_DFE_VGA_OVERRIDE_DFE_VGA_WRITE_VAL_MASK 0x01ff 1616 #define DSC_C_DFE_VGA_OVERRIDE_DFE_VGA_WRITE_VAL_ALIGN 0 1617 #define DSC_C_DFE_VGA_OVERRIDE_DFE_VGA_WRITE_VAL_BITS 9 1618 #define DSC_C_DFE_VGA_OVERRIDE_DFE_VGA_WRITE_VAL_SHIFT 0 1619 1620 1621 /**************************************************************************** 1622 * DSC_C :: VGA_CTL 1623 */ 1624 /* DSC_C :: VGA_CTL :: vga_en [15:15] */ 1625 #define DSC_C_VGA_CTL_VGA_EN_MASK 0x8000 1626 #define DSC_C_VGA_CTL_VGA_EN_ALIGN 0 1627 #define DSC_C_VGA_CTL_VGA_EN_BITS 1 1628 #define DSC_C_VGA_CTL_VGA_EN_SHIFT 15 1629 1630 /* DSC_C :: VGA_CTL :: vga_err_sel [14:13] */ 1631 #define DSC_C_VGA_CTL_VGA_ERR_SEL_MASK 0x6000 1632 #define DSC_C_VGA_CTL_VGA_ERR_SEL_ALIGN 0 1633 #define DSC_C_VGA_CTL_VGA_ERR_SEL_BITS 2 1634 #define DSC_C_VGA_CTL_VGA_ERR_SEL_SHIFT 13 1635 1636 /* DSC_C :: VGA_CTL :: vga_p1_gradient_invert [12:12] */ 1637 #define DSC_C_VGA_CTL_VGA_P1_GRADIENT_INVERT_MASK 0x1000 1638 #define DSC_C_VGA_CTL_VGA_P1_GRADIENT_INVERT_ALIGN 0 1639 #define DSC_C_VGA_CTL_VGA_P1_GRADIENT_INVERT_BITS 1 1640 #define DSC_C_VGA_CTL_VGA_P1_GRADIENT_INVERT_SHIFT 12 1641 1642 /* DSC_C :: VGA_CTL :: vga_err_gain [11:10] */ 1643 #define DSC_C_VGA_CTL_VGA_ERR_GAIN_MASK 0x0c00 1644 #define DSC_C_VGA_CTL_VGA_ERR_GAIN_ALIGN 0 1645 #define DSC_C_VGA_CTL_VGA_ERR_GAIN_BITS 2 1646 #define DSC_C_VGA_CTL_VGA_ERR_GAIN_SHIFT 10 1647 1648 /* DSC_C :: VGA_CTL :: vga_inv_m1 [09:09] */ 1649 #define DSC_C_VGA_CTL_VGA_INV_M1_MASK 0x0200 1650 #define DSC_C_VGA_CTL_VGA_INV_M1_ALIGN 0 1651 #define DSC_C_VGA_CTL_VGA_INV_M1_BITS 1 1652 #define DSC_C_VGA_CTL_VGA_INV_M1_SHIFT 9 1653 1654 /* DSC_C :: VGA_CTL :: vga_inv_p1 [08:08] */ 1655 #define DSC_C_VGA_CTL_VGA_INV_P1_MASK 0x0100 1656 #define DSC_C_VGA_CTL_VGA_INV_P1_ALIGN 0 1657 #define DSC_C_VGA_CTL_VGA_INV_P1_BITS 1 1658 #define DSC_C_VGA_CTL_VGA_INV_P1_SHIFT 8 1659 1660 /* DSC_C :: VGA_CTL :: vga_update_gain [07:06] */ 1661 #define DSC_C_VGA_CTL_VGA_UPDATE_GAIN_MASK 0x00c0 1662 #define DSC_C_VGA_CTL_VGA_UPDATE_GAIN_ALIGN 0 1663 #define DSC_C_VGA_CTL_VGA_UPDATE_GAIN_BITS 2 1664 #define DSC_C_VGA_CTL_VGA_UPDATE_GAIN_SHIFT 6 1665 1666 /* DSC_C :: VGA_CTL :: reserved0 [05:03] */ 1667 #define DSC_C_VGA_CTL_RESERVED0_MASK 0x0038 1668 #define DSC_C_VGA_CTL_RESERVED0_ALIGN 0 1669 #define DSC_C_VGA_CTL_RESERVED0_BITS 3 1670 #define DSC_C_VGA_CTL_RESERVED0_SHIFT 3 1671 1672 /* DSC_C :: VGA_CTL :: vga_tablemap_disable [02:02] */ 1673 #define DSC_C_VGA_CTL_VGA_TABLEMAP_DISABLE_MASK 0x0004 1674 #define DSC_C_VGA_CTL_VGA_TABLEMAP_DISABLE_ALIGN 0 1675 #define DSC_C_VGA_CTL_VGA_TABLEMAP_DISABLE_BITS 1 1676 #define DSC_C_VGA_CTL_VGA_TABLEMAP_DISABLE_SHIFT 2 1677 1678 /* DSC_C :: VGA_CTL :: vga_acc_hys_en [01:01] */ 1679 #define DSC_C_VGA_CTL_VGA_ACC_HYS_EN_MASK 0x0002 1680 #define DSC_C_VGA_CTL_VGA_ACC_HYS_EN_ALIGN 0 1681 #define DSC_C_VGA_CTL_VGA_ACC_HYS_EN_BITS 1 1682 #define DSC_C_VGA_CTL_VGA_ACC_HYS_EN_SHIFT 1 1683 1684 /* DSC_C :: VGA_CTL :: vga_p1_acc_clr [00:00] */ 1685 #define DSC_C_VGA_CTL_VGA_P1_ACC_CLR_MASK 0x0001 1686 #define DSC_C_VGA_CTL_VGA_P1_ACC_CLR_ALIGN 0 1687 #define DSC_C_VGA_CTL_VGA_P1_ACC_CLR_BITS 1 1688 #define DSC_C_VGA_CTL_VGA_P1_ACC_CLR_SHIFT 0 1689 1690 1691 /**************************************************************************** 1692 * DSC_C :: VGA_PAT_EYEDIAG_CTL 1693 */ 1694 /* DSC_C :: VGA_PAT_EYEDIAG_CTL :: p1_eyediag_en [15:15] */ 1695 #define DSC_C_VGA_PAT_EYEDIAG_CTL_P1_EYEDIAG_EN_MASK 0x8000 1696 #define DSC_C_VGA_PAT_EYEDIAG_CTL_P1_EYEDIAG_EN_ALIGN 0 1697 #define DSC_C_VGA_PAT_EYEDIAG_CTL_P1_EYEDIAG_EN_BITS 1 1698 #define DSC_C_VGA_PAT_EYEDIAG_CTL_P1_EYEDIAG_EN_SHIFT 15 1699 1700 /* DSC_C :: VGA_PAT_EYEDIAG_CTL :: reserved0 [14:08] */ 1701 #define DSC_C_VGA_PAT_EYEDIAG_CTL_RESERVED0_MASK 0x7f00 1702 #define DSC_C_VGA_PAT_EYEDIAG_CTL_RESERVED0_ALIGN 0 1703 #define DSC_C_VGA_PAT_EYEDIAG_CTL_RESERVED0_BITS 7 1704 #define DSC_C_VGA_PAT_EYEDIAG_CTL_RESERVED0_SHIFT 8 1705 1706 /* DSC_C :: VGA_PAT_EYEDIAG_CTL :: vga_pattern_bit_en [07:04] */ 1707 #define DSC_C_VGA_PAT_EYEDIAG_CTL_VGA_PATTERN_BIT_EN_MASK 0x00f0 1708 #define DSC_C_VGA_PAT_EYEDIAG_CTL_VGA_PATTERN_BIT_EN_ALIGN 0 1709 #define DSC_C_VGA_PAT_EYEDIAG_CTL_VGA_PATTERN_BIT_EN_BITS 4 1710 #define DSC_C_VGA_PAT_EYEDIAG_CTL_VGA_PATTERN_BIT_EN_SHIFT 4 1711 1712 /* DSC_C :: VGA_PAT_EYEDIAG_CTL :: vga_pattern [03:00] */ 1713 #define DSC_C_VGA_PAT_EYEDIAG_CTL_VGA_PATTERN_MASK 0x000f 1714 #define DSC_C_VGA_PAT_EYEDIAG_CTL_VGA_PATTERN_ALIGN 0 1715 #define DSC_C_VGA_PAT_EYEDIAG_CTL_VGA_PATTERN_BITS 4 1716 #define DSC_C_VGA_PAT_EYEDIAG_CTL_VGA_PATTERN_SHIFT 0 1717 1718 1719 /**************************************************************************** 1720 * DSC_C :: P1_FRAC_OFFS_CTL 1721 */ 1722 /* DSC_C :: P1_FRAC_OFFS_CTL :: reserved0 [15:09] */ 1723 #define DSC_C_P1_FRAC_OFFS_CTL_RESERVED0_MASK 0xfe00 1724 #define DSC_C_P1_FRAC_OFFS_CTL_RESERVED0_ALIGN 0 1725 #define DSC_C_P1_FRAC_OFFS_CTL_RESERVED0_BITS 7 1726 #define DSC_C_P1_FRAC_OFFS_CTL_RESERVED0_SHIFT 9 1727 1728 /* DSC_C :: P1_FRAC_OFFS_CTL :: p1_off_3levelq_en [08:08] */ 1729 #define DSC_C_P1_FRAC_OFFS_CTL_P1_OFF_3LEVELQ_EN_MASK 0x0100 1730 #define DSC_C_P1_FRAC_OFFS_CTL_P1_OFF_3LEVELQ_EN_ALIGN 0 1731 #define DSC_C_P1_FRAC_OFFS_CTL_P1_OFF_3LEVELQ_EN_BITS 1 1732 #define DSC_C_P1_FRAC_OFFS_CTL_P1_OFF_3LEVELQ_EN_SHIFT 8 1733 1734 /* DSC_C :: P1_FRAC_OFFS_CTL :: p1_offset_en [07:07] */ 1735 #define DSC_C_P1_FRAC_OFFS_CTL_P1_OFFSET_EN_MASK 0x0080 1736 #define DSC_C_P1_FRAC_OFFS_CTL_P1_OFFSET_EN_ALIGN 0 1737 #define DSC_C_P1_FRAC_OFFS_CTL_P1_OFFSET_EN_BITS 1 1738 #define DSC_C_P1_FRAC_OFFS_CTL_P1_OFFSET_EN_SHIFT 7 1739 1740 /* DSC_C :: P1_FRAC_OFFS_CTL :: p1_offset [06:00] */ 1741 #define DSC_C_P1_FRAC_OFFS_CTL_P1_OFFSET_MASK 0x007f 1742 #define DSC_C_P1_FRAC_OFFS_CTL_P1_OFFSET_ALIGN 0 1743 #define DSC_C_P1_FRAC_OFFS_CTL_P1_OFFSET_BITS 7 1744 #define DSC_C_P1_FRAC_OFFS_CTL_P1_OFFSET_SHIFT 0 1745 1746 1747 /**************************************************************************** 1748 * eagle_tsc_dsc_blk_DSC_D 1749 */ 1750 /**************************************************************************** 1751 * DSC_D :: TRNSUM_CTL_1 1752 */ 1753 /* DSC_D :: TRNSUM_CTL_1 :: trnsum_en [15:15] */ 1754 #define DSC_D_TRNSUM_CTL_1_TRNSUM_EN_MASK 0x8000 1755 #define DSC_D_TRNSUM_CTL_1_TRNSUM_EN_ALIGN 0 1756 #define DSC_D_TRNSUM_CTL_1_TRNSUM_EN_BITS 1 1757 #define DSC_D_TRNSUM_CTL_1_TRNSUM_EN_SHIFT 15 1758 1759 /* DSC_D :: TRNSUM_CTL_1 :: trnsum_err_sel [14:12] */ 1760 #define DSC_D_TRNSUM_CTL_1_TRNSUM_ERR_SEL_MASK 0x7000 1761 #define DSC_D_TRNSUM_CTL_1_TRNSUM_ERR_SEL_ALIGN 0 1762 #define DSC_D_TRNSUM_CTL_1_TRNSUM_ERR_SEL_BITS 3 1763 #define DSC_D_TRNSUM_CTL_1_TRNSUM_ERR_SEL_SHIFT 12 1764 1765 /* DSC_D :: TRNSUM_CTL_1 :: trnsum_random_tapsel_disable [11:11] */ 1766 #define DSC_D_TRNSUM_CTL_1_TRNSUM_RANDOM_TAPSEL_DISABLE_MASK 0x0800 1767 #define DSC_D_TRNSUM_CTL_1_TRNSUM_RANDOM_TAPSEL_DISABLE_ALIGN 0 1768 #define DSC_D_TRNSUM_CTL_1_TRNSUM_RANDOM_TAPSEL_DISABLE_BITS 1 1769 #define DSC_D_TRNSUM_CTL_1_TRNSUM_RANDOM_TAPSEL_DISABLE_SHIFT 11 1770 1771 /* DSC_D :: TRNSUM_CTL_1 :: trnsum_inv_pattern_en [10:10] */ 1772 #define DSC_D_TRNSUM_CTL_1_TRNSUM_INV_PATTERN_EN_MASK 0x0400 1773 #define DSC_D_TRNSUM_CTL_1_TRNSUM_INV_PATTERN_EN_ALIGN 0 1774 #define DSC_D_TRNSUM_CTL_1_TRNSUM_INV_PATTERN_EN_BITS 1 1775 #define DSC_D_TRNSUM_CTL_1_TRNSUM_INV_PATTERN_EN_SHIFT 10 1776 1777 /* DSC_D :: TRNSUM_CTL_1 :: trnsum_pattern_full_check_off [09:09] */ 1778 #define DSC_D_TRNSUM_CTL_1_TRNSUM_PATTERN_FULL_CHECK_OFF_MASK 0x0200 1779 #define DSC_D_TRNSUM_CTL_1_TRNSUM_PATTERN_FULL_CHECK_OFF_ALIGN 0 1780 #define DSC_D_TRNSUM_CTL_1_TRNSUM_PATTERN_FULL_CHECK_OFF_BITS 1 1781 #define DSC_D_TRNSUM_CTL_1_TRNSUM_PATTERN_FULL_CHECK_OFF_SHIFT 9 1782 1783 /* DSC_D :: TRNSUM_CTL_1 :: reserved0 [08:08] */ 1784 #define DSC_D_TRNSUM_CTL_1_RESERVED0_MASK 0x0100 1785 #define DSC_D_TRNSUM_CTL_1_RESERVED0_ALIGN 0 1786 #define DSC_D_TRNSUM_CTL_1_RESERVED0_BITS 1 1787 #define DSC_D_TRNSUM_CTL_1_RESERVED0_SHIFT 8 1788 1789 /* DSC_D :: TRNSUM_CTL_1 :: trnsum_gain [07:06] */ 1790 #define DSC_D_TRNSUM_CTL_1_TRNSUM_GAIN_MASK 0x00c0 1791 #define DSC_D_TRNSUM_CTL_1_TRNSUM_GAIN_ALIGN 0 1792 #define DSC_D_TRNSUM_CTL_1_TRNSUM_GAIN_BITS 2 1793 #define DSC_D_TRNSUM_CTL_1_TRNSUM_GAIN_SHIFT 6 1794 1795 /* DSC_D :: TRNSUM_CTL_1 :: trnsum_eye_closure_en [05:05] */ 1796 #define DSC_D_TRNSUM_CTL_1_TRNSUM_EYE_CLOSURE_EN_MASK 0x0020 1797 #define DSC_D_TRNSUM_CTL_1_TRNSUM_EYE_CLOSURE_EN_ALIGN 0 1798 #define DSC_D_TRNSUM_CTL_1_TRNSUM_EYE_CLOSURE_EN_BITS 1 1799 #define DSC_D_TRNSUM_CTL_1_TRNSUM_EYE_CLOSURE_EN_SHIFT 5 1800 1801 /* DSC_D :: TRNSUM_CTL_1 :: cdr_qphase_mult_en [04:04] */ 1802 #define DSC_D_TRNSUM_CTL_1_CDR_QPHASE_MULT_EN_MASK 0x0010 1803 #define DSC_D_TRNSUM_CTL_1_CDR_QPHASE_MULT_EN_ALIGN 0 1804 #define DSC_D_TRNSUM_CTL_1_CDR_QPHASE_MULT_EN_BITS 1 1805 #define DSC_D_TRNSUM_CTL_1_CDR_QPHASE_MULT_EN_SHIFT 4 1806 1807 /* DSC_D :: TRNSUM_CTL_1 :: trnsum_tap_range_sel [03:02] */ 1808 #define DSC_D_TRNSUM_CTL_1_TRNSUM_TAP_RANGE_SEL_MASK 0x000c 1809 #define DSC_D_TRNSUM_CTL_1_TRNSUM_TAP_RANGE_SEL_ALIGN 0 1810 #define DSC_D_TRNSUM_CTL_1_TRNSUM_TAP_RANGE_SEL_BITS 2 1811 #define DSC_D_TRNSUM_CTL_1_TRNSUM_TAP_RANGE_SEL_SHIFT 2 1812 1813 /* DSC_D :: TRNSUM_CTL_1 :: reserved1 [01:00] */ 1814 #define DSC_D_TRNSUM_CTL_1_RESERVED1_MASK 0x0003 1815 #define DSC_D_TRNSUM_CTL_1_RESERVED1_ALIGN 0 1816 #define DSC_D_TRNSUM_CTL_1_RESERVED1_BITS 2 1817 #define DSC_D_TRNSUM_CTL_1_RESERVED1_SHIFT 0 1818 1819 1820 /**************************************************************************** 1821 * DSC_D :: TRNSUM_CTL_2 1822 */ 1823 /* DSC_D :: TRNSUM_CTL_2 :: trnsum_pattern [15:08] */ 1824 #define DSC_D_TRNSUM_CTL_2_TRNSUM_PATTERN_MASK 0xff00 1825 #define DSC_D_TRNSUM_CTL_2_TRNSUM_PATTERN_ALIGN 0 1826 #define DSC_D_TRNSUM_CTL_2_TRNSUM_PATTERN_BITS 8 1827 #define DSC_D_TRNSUM_CTL_2_TRNSUM_PATTERN_SHIFT 8 1828 1829 /* DSC_D :: TRNSUM_CTL_2 :: trnsum_pattern_bit_en [07:00] */ 1830 #define DSC_D_TRNSUM_CTL_2_TRNSUM_PATTERN_BIT_EN_MASK 0x00ff 1831 #define DSC_D_TRNSUM_CTL_2_TRNSUM_PATTERN_BIT_EN_ALIGN 0 1832 #define DSC_D_TRNSUM_CTL_2_TRNSUM_PATTERN_BIT_EN_BITS 8 1833 #define DSC_D_TRNSUM_CTL_2_TRNSUM_PATTERN_BIT_EN_SHIFT 0 1834 1835 1836 /**************************************************************************** 1837 * DSC_D :: TRNSUM_CTL_3 1838 */ 1839 /* DSC_D :: TRNSUM_CTL_3 :: trnsum_tap_en [15:08] */ 1840 #define DSC_D_TRNSUM_CTL_3_TRNSUM_TAP_EN_MASK 0xff00 1841 #define DSC_D_TRNSUM_CTL_3_TRNSUM_TAP_EN_ALIGN 0 1842 #define DSC_D_TRNSUM_CTL_3_TRNSUM_TAP_EN_BITS 8 1843 #define DSC_D_TRNSUM_CTL_3_TRNSUM_TAP_EN_SHIFT 8 1844 1845 /* DSC_D :: TRNSUM_CTL_3 :: trnsum_tap_sign [07:00] */ 1846 #define DSC_D_TRNSUM_CTL_3_TRNSUM_TAP_SIGN_MASK 0x00ff 1847 #define DSC_D_TRNSUM_CTL_3_TRNSUM_TAP_SIGN_ALIGN 0 1848 #define DSC_D_TRNSUM_CTL_3_TRNSUM_TAP_SIGN_BITS 8 1849 #define DSC_D_TRNSUM_CTL_3_TRNSUM_TAP_SIGN_SHIFT 0 1850 1851 1852 /**************************************************************************** 1853 * DSC_D :: TRNSUM_CTL_4 1854 */ 1855 /* DSC_D :: TRNSUM_CTL_4 :: tdr_cycle_bin [15:12] */ 1856 #define DSC_D_TRNSUM_CTL_4_TDR_CYCLE_BIN_MASK 0xf000 1857 #define DSC_D_TRNSUM_CTL_4_TDR_CYCLE_BIN_ALIGN 0 1858 #define DSC_D_TRNSUM_CTL_4_TDR_CYCLE_BIN_BITS 4 1859 #define DSC_D_TRNSUM_CTL_4_TDR_CYCLE_BIN_SHIFT 12 1860 1861 /* DSC_D :: TRNSUM_CTL_4 :: tdr_cycle_sel [11:08] */ 1862 #define DSC_D_TRNSUM_CTL_4_TDR_CYCLE_SEL_MASK 0x0f00 1863 #define DSC_D_TRNSUM_CTL_4_TDR_CYCLE_SEL_ALIGN 0 1864 #define DSC_D_TRNSUM_CTL_4_TDR_CYCLE_SEL_BITS 4 1865 #define DSC_D_TRNSUM_CTL_4_TDR_CYCLE_SEL_SHIFT 8 1866 1867 /* DSC_D :: TRNSUM_CTL_4 :: tdr_trnsum_en [07:07] */ 1868 #define DSC_D_TRNSUM_CTL_4_TDR_TRNSUM_EN_MASK 0x0080 1869 #define DSC_D_TRNSUM_CTL_4_TDR_TRNSUM_EN_ALIGN 0 1870 #define DSC_D_TRNSUM_CTL_4_TDR_TRNSUM_EN_BITS 1 1871 #define DSC_D_TRNSUM_CTL_4_TDR_TRNSUM_EN_SHIFT 7 1872 1873 /* DSC_D :: TRNSUM_CTL_4 :: tdr_bit_sel [06:02] */ 1874 #define DSC_D_TRNSUM_CTL_4_TDR_BIT_SEL_MASK 0x007c 1875 #define DSC_D_TRNSUM_CTL_4_TDR_BIT_SEL_ALIGN 0 1876 #define DSC_D_TRNSUM_CTL_4_TDR_BIT_SEL_BITS 5 1877 #define DSC_D_TRNSUM_CTL_4_TDR_BIT_SEL_SHIFT 2 1878 1879 /* DSC_D :: TRNSUM_CTL_4 :: trnsum_unsigned_flip [01:01] */ 1880 #define DSC_D_TRNSUM_CTL_4_TRNSUM_UNSIGNED_FLIP_MASK 0x0002 1881 #define DSC_D_TRNSUM_CTL_4_TRNSUM_UNSIGNED_FLIP_ALIGN 0 1882 #define DSC_D_TRNSUM_CTL_4_TRNSUM_UNSIGNED_FLIP_BITS 1 1883 #define DSC_D_TRNSUM_CTL_4_TRNSUM_UNSIGNED_FLIP_SHIFT 1 1884 1885 /* DSC_D :: TRNSUM_CTL_4 :: trnsum_unsigned_corr [00:00] */ 1886 #define DSC_D_TRNSUM_CTL_4_TRNSUM_UNSIGNED_CORR_MASK 0x0001 1887 #define DSC_D_TRNSUM_CTL_4_TRNSUM_UNSIGNED_CORR_ALIGN 0 1888 #define DSC_D_TRNSUM_CTL_4_TRNSUM_UNSIGNED_CORR_BITS 1 1889 #define DSC_D_TRNSUM_CTL_4_TRNSUM_UNSIGNED_CORR_SHIFT 0 1890 1891 1892 /**************************************************************************** 1893 * DSC_D :: TRNSUM_STS_1 1894 */ 1895 /* DSC_D :: TRNSUM_STS_1 :: trnsum_e_high [15:00] */ 1896 #define DSC_D_TRNSUM_STS_1_TRNSUM_E_HIGH_MASK 0xffff 1897 #define DSC_D_TRNSUM_STS_1_TRNSUM_E_HIGH_ALIGN 0 1898 #define DSC_D_TRNSUM_STS_1_TRNSUM_E_HIGH_BITS 16 1899 #define DSC_D_TRNSUM_STS_1_TRNSUM_E_HIGH_SHIFT 0 1900 1901 1902 /**************************************************************************** 1903 * DSC_D :: TRNSUM_STS_2 1904 */ 1905 /* DSC_D :: TRNSUM_STS_2 :: reserved0 [15:08] */ 1906 #define DSC_D_TRNSUM_STS_2_RESERVED0_MASK 0xff00 1907 #define DSC_D_TRNSUM_STS_2_RESERVED0_ALIGN 0 1908 #define DSC_D_TRNSUM_STS_2_RESERVED0_BITS 8 1909 #define DSC_D_TRNSUM_STS_2_RESERVED0_SHIFT 8 1910 1911 /* DSC_D :: TRNSUM_STS_2 :: trnsum_e_low [07:00] */ 1912 #define DSC_D_TRNSUM_STS_2_TRNSUM_E_LOW_MASK 0x00ff 1913 #define DSC_D_TRNSUM_STS_2_TRNSUM_E_LOW_ALIGN 0 1914 #define DSC_D_TRNSUM_STS_2_TRNSUM_E_LOW_BITS 8 1915 #define DSC_D_TRNSUM_STS_2_TRNSUM_E_LOW_SHIFT 0 1916 1917 1918 /**************************************************************************** 1919 * DSC_D :: TRNSUM_STS_3 1920 */ 1921 /* DSC_D :: TRNSUM_STS_3 :: trnsum_o_high [15:00] */ 1922 #define DSC_D_TRNSUM_STS_3_TRNSUM_O_HIGH_MASK 0xffff 1923 #define DSC_D_TRNSUM_STS_3_TRNSUM_O_HIGH_ALIGN 0 1924 #define DSC_D_TRNSUM_STS_3_TRNSUM_O_HIGH_BITS 16 1925 #define DSC_D_TRNSUM_STS_3_TRNSUM_O_HIGH_SHIFT 0 1926 1927 1928 /**************************************************************************** 1929 * DSC_D :: TRNSUM_STS_4 1930 */ 1931 /* DSC_D :: TRNSUM_STS_4 :: reserved0 [15:08] */ 1932 #define DSC_D_TRNSUM_STS_4_RESERVED0_MASK 0xff00 1933 #define DSC_D_TRNSUM_STS_4_RESERVED0_ALIGN 0 1934 #define DSC_D_TRNSUM_STS_4_RESERVED0_BITS 8 1935 #define DSC_D_TRNSUM_STS_4_RESERVED0_SHIFT 8 1936 1937 /* DSC_D :: TRNSUM_STS_4 :: trnsum_o_low [07:00] */ 1938 #define DSC_D_TRNSUM_STS_4_TRNSUM_O_LOW_MASK 0x00ff 1939 #define DSC_D_TRNSUM_STS_4_TRNSUM_O_LOW_ALIGN 0 1940 #define DSC_D_TRNSUM_STS_4_TRNSUM_O_LOW_BITS 8 1941 #define DSC_D_TRNSUM_STS_4_TRNSUM_O_LOW_SHIFT 0 1942 1943 1944 /**************************************************************************** 1945 * DSC_D :: TRNSUM_STS_5 1946 */ 1947 /* DSC_D :: TRNSUM_STS_5 :: trnsum_high [15:00] */ 1948 #define DSC_D_TRNSUM_STS_5_TRNSUM_HIGH_MASK 0xffff 1949 #define DSC_D_TRNSUM_STS_5_TRNSUM_HIGH_ALIGN 0 1950 #define DSC_D_TRNSUM_STS_5_TRNSUM_HIGH_BITS 16 1951 #define DSC_D_TRNSUM_STS_5_TRNSUM_HIGH_SHIFT 0 1952 1953 1954 /**************************************************************************** 1955 * DSC_D :: TRNSUM_STS_6 1956 */ 1957 /* DSC_D :: TRNSUM_STS_6 :: reserved0 [15:10] */ 1958 #define DSC_D_TRNSUM_STS_6_RESERVED0_MASK 0xfc00 1959 #define DSC_D_TRNSUM_STS_6_RESERVED0_ALIGN 0 1960 #define DSC_D_TRNSUM_STS_6_RESERVED0_BITS 6 1961 #define DSC_D_TRNSUM_STS_6_RESERVED0_SHIFT 10 1962 1963 /* DSC_D :: TRNSUM_STS_6 :: trnsum_low [09:00] */ 1964 #define DSC_D_TRNSUM_STS_6_TRNSUM_LOW_MASK 0x03ff 1965 #define DSC_D_TRNSUM_STS_6_TRNSUM_LOW_ALIGN 0 1966 #define DSC_D_TRNSUM_STS_6_TRNSUM_LOW_BITS 10 1967 #define DSC_D_TRNSUM_STS_6_TRNSUM_LOW_SHIFT 0 1968 1969 1970 /**************************************************************************** 1971 * DSC_D :: VGA_P1EYEDIAG_STS 1972 */ 1973 /* DSC_D :: VGA_P1EYEDIAG_STS :: reserved0 [15:14] */ 1974 #define DSC_D_VGA_P1EYEDIAG_STS_RESERVED0_MASK 0xc000 1975 #define DSC_D_VGA_P1EYEDIAG_STS_RESERVED0_ALIGN 0 1976 #define DSC_D_VGA_P1EYEDIAG_STS_RESERVED0_BITS 2 1977 #define DSC_D_VGA_P1EYEDIAG_STS_RESERVED0_SHIFT 14 1978 1979 /* DSC_D :: VGA_P1EYEDIAG_STS :: p1_eyediag_bin [13:08] */ 1980 #define DSC_D_VGA_P1EYEDIAG_STS_P1_EYEDIAG_BIN_MASK 0x3f00 1981 #define DSC_D_VGA_P1EYEDIAG_STS_P1_EYEDIAG_BIN_ALIGN 0 1982 #define DSC_D_VGA_P1EYEDIAG_STS_P1_EYEDIAG_BIN_BITS 6 1983 #define DSC_D_VGA_P1EYEDIAG_STS_P1_EYEDIAG_BIN_SHIFT 8 1984 1985 /* DSC_D :: VGA_P1EYEDIAG_STS :: reserved1 [07:06] */ 1986 #define DSC_D_VGA_P1EYEDIAG_STS_RESERVED1_MASK 0x00c0 1987 #define DSC_D_VGA_P1EYEDIAG_STS_RESERVED1_ALIGN 0 1988 #define DSC_D_VGA_P1EYEDIAG_STS_RESERVED1_BITS 2 1989 #define DSC_D_VGA_P1EYEDIAG_STS_RESERVED1_SHIFT 6 1990 1991 /* DSC_D :: VGA_P1EYEDIAG_STS :: vga_bin [05:00] */ 1992 #define DSC_D_VGA_P1EYEDIAG_STS_VGA_BIN_MASK 0x003f 1993 #define DSC_D_VGA_P1EYEDIAG_STS_VGA_BIN_ALIGN 0 1994 #define DSC_D_VGA_P1EYEDIAG_STS_VGA_BIN_BITS 6 1995 #define DSC_D_VGA_P1EYEDIAG_STS_VGA_BIN_SHIFT 0 1996 1997 1998 /**************************************************************************** 1999 * DSC_D :: DFE_1_STS 2000 */ 2001 /* DSC_D :: DFE_1_STS :: dfe_1_wants_negative [15:15] */ 2002 #define DSC_D_DFE_1_STS_DFE_1_WANTS_NEGATIVE_MASK 0x8000 2003 #define DSC_D_DFE_1_STS_DFE_1_WANTS_NEGATIVE_ALIGN 0 2004 #define DSC_D_DFE_1_STS_DFE_1_WANTS_NEGATIVE_BITS 1 2005 #define DSC_D_DFE_1_STS_DFE_1_WANTS_NEGATIVE_SHIFT 15 2006 2007 /* DSC_D :: DFE_1_STS :: reserved0 [14:14] */ 2008 #define DSC_D_DFE_1_STS_RESERVED0_MASK 0x4000 2009 #define DSC_D_DFE_1_STS_RESERVED0_ALIGN 0 2010 #define DSC_D_DFE_1_STS_RESERVED0_BITS 1 2011 #define DSC_D_DFE_1_STS_RESERVED0_SHIFT 14 2012 2013 /* DSC_D :: DFE_1_STS :: dfe_1_e [13:11] */ 2014 #define DSC_D_DFE_1_STS_DFE_1_E_MASK 0x3800 2015 #define DSC_D_DFE_1_STS_DFE_1_E_ALIGN 0 2016 #define DSC_D_DFE_1_STS_DFE_1_E_BITS 3 2017 #define DSC_D_DFE_1_STS_DFE_1_E_SHIFT 11 2018 2019 /* DSC_D :: DFE_1_STS :: dfe_1_o [10:08] */ 2020 #define DSC_D_DFE_1_STS_DFE_1_O_MASK 0x0700 2021 #define DSC_D_DFE_1_STS_DFE_1_O_ALIGN 0 2022 #define DSC_D_DFE_1_STS_DFE_1_O_BITS 3 2023 #define DSC_D_DFE_1_STS_DFE_1_O_SHIFT 8 2024 2025 /* DSC_D :: DFE_1_STS :: reserved1 [07:06] */ 2026 #define DSC_D_DFE_1_STS_RESERVED1_MASK 0x00c0 2027 #define DSC_D_DFE_1_STS_RESERVED1_ALIGN 0 2028 #define DSC_D_DFE_1_STS_RESERVED1_BITS 2 2029 #define DSC_D_DFE_1_STS_RESERVED1_SHIFT 6 2030 2031 /* DSC_D :: DFE_1_STS :: dfe_1_cmn [05:00] */ 2032 #define DSC_D_DFE_1_STS_DFE_1_CMN_MASK 0x003f 2033 #define DSC_D_DFE_1_STS_DFE_1_CMN_ALIGN 0 2034 #define DSC_D_DFE_1_STS_DFE_1_CMN_BITS 6 2035 #define DSC_D_DFE_1_STS_DFE_1_CMN_SHIFT 0 2036 2037 2038 /**************************************************************************** 2039 * DSC_D :: DFE_2_STS 2040 */ 2041 /* DSC_D :: DFE_2_STS :: reserved0 [15:14] */ 2042 #define DSC_D_DFE_2_STS_RESERVED0_MASK 0xc000 2043 #define DSC_D_DFE_2_STS_RESERVED0_ALIGN 0 2044 #define DSC_D_DFE_2_STS_RESERVED0_BITS 2 2045 #define DSC_D_DFE_2_STS_RESERVED0_SHIFT 14 2046 2047 /* DSC_D :: DFE_2_STS :: dfe_2_e [13:11] */ 2048 #define DSC_D_DFE_2_STS_DFE_2_E_MASK 0x3800 2049 #define DSC_D_DFE_2_STS_DFE_2_E_ALIGN 0 2050 #define DSC_D_DFE_2_STS_DFE_2_E_BITS 3 2051 #define DSC_D_DFE_2_STS_DFE_2_E_SHIFT 11 2052 2053 /* DSC_D :: DFE_2_STS :: dfe_2_o [10:08] */ 2054 #define DSC_D_DFE_2_STS_DFE_2_O_MASK 0x0700 2055 #define DSC_D_DFE_2_STS_DFE_2_O_ALIGN 0 2056 #define DSC_D_DFE_2_STS_DFE_2_O_BITS 3 2057 #define DSC_D_DFE_2_STS_DFE_2_O_SHIFT 8 2058 2059 /* DSC_D :: DFE_2_STS :: reserved1 [07:07] */ 2060 #define DSC_D_DFE_2_STS_RESERVED1_MASK 0x0080 2061 #define DSC_D_DFE_2_STS_RESERVED1_ALIGN 0 2062 #define DSC_D_DFE_2_STS_RESERVED1_BITS 1 2063 #define DSC_D_DFE_2_STS_RESERVED1_SHIFT 7 2064 2065 /* DSC_D :: DFE_2_STS :: dfe_2_se [06:06] */ 2066 #define DSC_D_DFE_2_STS_DFE_2_SE_MASK 0x0040 2067 #define DSC_D_DFE_2_STS_DFE_2_SE_ALIGN 0 2068 #define DSC_D_DFE_2_STS_DFE_2_SE_BITS 1 2069 #define DSC_D_DFE_2_STS_DFE_2_SE_SHIFT 6 2070 2071 /* DSC_D :: DFE_2_STS :: dfe_2_so [05:05] */ 2072 #define DSC_D_DFE_2_STS_DFE_2_SO_MASK 0x0020 2073 #define DSC_D_DFE_2_STS_DFE_2_SO_ALIGN 0 2074 #define DSC_D_DFE_2_STS_DFE_2_SO_BITS 1 2075 #define DSC_D_DFE_2_STS_DFE_2_SO_SHIFT 5 2076 2077 /* DSC_D :: DFE_2_STS :: dfe_2_cmn [04:00] */ 2078 #define DSC_D_DFE_2_STS_DFE_2_CMN_MASK 0x001f 2079 #define DSC_D_DFE_2_STS_DFE_2_CMN_ALIGN 0 2080 #define DSC_D_DFE_2_STS_DFE_2_CMN_BITS 5 2081 #define DSC_D_DFE_2_STS_DFE_2_CMN_SHIFT 0 2082 2083 2084 /**************************************************************************** 2085 * DSC_D :: DFE_3_4_5_STS 2086 */ 2087 /* DSC_D :: DFE_3_4_5_STS :: dfe_5_cmn [15:11] */ 2088 #define DSC_D_DFE_3_4_5_STS_DFE_5_CMN_MASK 0xf800 2089 #define DSC_D_DFE_3_4_5_STS_DFE_5_CMN_ALIGN 0 2090 #define DSC_D_DFE_3_4_5_STS_DFE_5_CMN_BITS 5 2091 #define DSC_D_DFE_3_4_5_STS_DFE_5_CMN_SHIFT 11 2092 2093 /* DSC_D :: DFE_3_4_5_STS :: dfe_4_cmn [10:06] */ 2094 #define DSC_D_DFE_3_4_5_STS_DFE_4_CMN_MASK 0x07c0 2095 #define DSC_D_DFE_3_4_5_STS_DFE_4_CMN_ALIGN 0 2096 #define DSC_D_DFE_3_4_5_STS_DFE_4_CMN_BITS 5 2097 #define DSC_D_DFE_3_4_5_STS_DFE_4_CMN_SHIFT 6 2098 2099 /* DSC_D :: DFE_3_4_5_STS :: dfe_3_cmn [05:00] */ 2100 #define DSC_D_DFE_3_4_5_STS_DFE_3_CMN_MASK 0x003f 2101 #define DSC_D_DFE_3_4_5_STS_DFE_3_CMN_ALIGN 0 2102 #define DSC_D_DFE_3_4_5_STS_DFE_3_CMN_BITS 6 2103 #define DSC_D_DFE_3_4_5_STS_DFE_3_CMN_SHIFT 0 2104 2105 2106 /**************************************************************************** 2107 * DSC_D :: VGA_TAP_BIN 2108 */ 2109 /* DSC_D :: VGA_TAP_BIN :: reserved0 [15:12] */ 2110 #define DSC_D_VGA_TAP_BIN_RESERVED0_MASK 0xf000 2111 #define DSC_D_VGA_TAP_BIN_RESERVED0_ALIGN 0 2112 #define DSC_D_VGA_TAP_BIN_RESERVED0_BITS 4 2113 #define DSC_D_VGA_TAP_BIN_RESERVED0_SHIFT 12 2114 2115 /* DSC_D :: VGA_TAP_BIN :: vga3_ctrl_bin [11:08] */ 2116 #define DSC_D_VGA_TAP_BIN_VGA3_CTRL_BIN_MASK 0x0f00 2117 #define DSC_D_VGA_TAP_BIN_VGA3_CTRL_BIN_ALIGN 0 2118 #define DSC_D_VGA_TAP_BIN_VGA3_CTRL_BIN_BITS 4 2119 #define DSC_D_VGA_TAP_BIN_VGA3_CTRL_BIN_SHIFT 8 2120 2121 /* DSC_D :: VGA_TAP_BIN :: reserved1 [07:05] */ 2122 #define DSC_D_VGA_TAP_BIN_RESERVED1_MASK 0x00e0 2123 #define DSC_D_VGA_TAP_BIN_RESERVED1_ALIGN 0 2124 #define DSC_D_VGA_TAP_BIN_RESERVED1_BITS 3 2125 #define DSC_D_VGA_TAP_BIN_RESERVED1_SHIFT 5 2126 2127 /* DSC_D :: VGA_TAP_BIN :: vga_ctrl_bin [04:00] */ 2128 #define DSC_D_VGA_TAP_BIN_VGA_CTRL_BIN_MASK 0x001f 2129 #define DSC_D_VGA_TAP_BIN_VGA_CTRL_BIN_ALIGN 0 2130 #define DSC_D_VGA_TAP_BIN_VGA_CTRL_BIN_BITS 5 2131 #define DSC_D_VGA_TAP_BIN_VGA_CTRL_BIN_SHIFT 0 2132 2133 2134 /**************************************************************************** 2135 * eagle_tsc_dsc_blk_DSC_E 2136 */ 2137 /**************************************************************************** 2138 * DSC_E :: CTRL 2139 */ 2140 /* DSC_E :: CTRL :: reserved0 [15:10] */ 2141 #define DSC_E_CTRL_RESERVED0_MASK 0xfc00 2142 #define DSC_E_CTRL_RESERVED0_ALIGN 0 2143 #define DSC_E_CTRL_RESERVED0_BITS 6 2144 #define DSC_E_CTRL_RESERVED0_SHIFT 10 2145 2146 /* DSC_E :: CTRL :: offset_fastacq [09:09] */ 2147 #define DSC_E_CTRL_OFFSET_FASTACQ_MASK 0x0200 2148 #define DSC_E_CTRL_OFFSET_FASTACQ_ALIGN 0 2149 #define DSC_E_CTRL_OFFSET_FASTACQ_BITS 1 2150 #define DSC_E_CTRL_OFFSET_FASTACQ_SHIFT 9 2151 2152 /* DSC_E :: CTRL :: en_dfe_clk [08:08] */ 2153 #define DSC_E_CTRL_EN_DFE_CLK_MASK 0x0100 2154 #define DSC_E_CTRL_EN_DFE_CLK_ALIGN 0 2155 #define DSC_E_CTRL_EN_DFE_CLK_BITS 1 2156 #define DSC_E_CTRL_EN_DFE_CLK_SHIFT 8 2157 2158 /* DSC_E :: CTRL :: pf_hiz [07:07] */ 2159 #define DSC_E_CTRL_PF_HIZ_MASK 0x0080 2160 #define DSC_E_CTRL_PF_HIZ_ALIGN 0 2161 #define DSC_E_CTRL_PF_HIZ_BITS 1 2162 #define DSC_E_CTRL_PF_HIZ_SHIFT 7 2163 2164 /* DSC_E :: CTRL :: m1_thresh_sel [06:05] */ 2165 #define DSC_E_CTRL_M1_THRESH_SEL_MASK 0x0060 2166 #define DSC_E_CTRL_M1_THRESH_SEL_ALIGN 0 2167 #define DSC_E_CTRL_M1_THRESH_SEL_BITS 2 2168 #define DSC_E_CTRL_M1_THRESH_SEL_SHIFT 5 2169 2170 /* DSC_E :: CTRL :: m1_thresh_zero [04:04] */ 2171 #define DSC_E_CTRL_M1_THRESH_ZERO_MASK 0x0010 2172 #define DSC_E_CTRL_M1_THRESH_ZERO_ALIGN 0 2173 #define DSC_E_CTRL_M1_THRESH_ZERO_BITS 1 2174 #define DSC_E_CTRL_M1_THRESH_ZERO_SHIFT 4 2175 2176 /* DSC_E :: CTRL :: p1_thresh_sel [03:03] */ 2177 #define DSC_E_CTRL_P1_THRESH_SEL_MASK 0x0008 2178 #define DSC_E_CTRL_P1_THRESH_SEL_ALIGN 0 2179 #define DSC_E_CTRL_P1_THRESH_SEL_BITS 1 2180 #define DSC_E_CTRL_P1_THRESH_SEL_SHIFT 3 2181 2182 /* DSC_E :: CTRL :: en_hgain [02:02] */ 2183 #define DSC_E_CTRL_EN_HGAIN_MASK 0x0004 2184 #define DSC_E_CTRL_EN_HGAIN_ALIGN 0 2185 #define DSC_E_CTRL_EN_HGAIN_BITS 1 2186 #define DSC_E_CTRL_EN_HGAIN_SHIFT 2 2187 2188 /* DSC_E :: CTRL :: offset_pd [01:01] */ 2189 #define DSC_E_CTRL_OFFSET_PD_MASK 0x0002 2190 #define DSC_E_CTRL_OFFSET_PD_ALIGN 0 2191 #define DSC_E_CTRL_OFFSET_PD_BITS 1 2192 #define DSC_E_CTRL_OFFSET_PD_SHIFT 1 2193 2194 /* DSC_E :: CTRL :: pd_ch_p1 [00:00] */ 2195 #define DSC_E_CTRL_PD_CH_P1_MASK 0x0001 2196 #define DSC_E_CTRL_PD_CH_P1_ALIGN 0 2197 #define DSC_E_CTRL_PD_CH_P1_BITS 1 2198 #define DSC_E_CTRL_PD_CH_P1_SHIFT 0 2199 2200 2201 /**************************************************************************** 2202 * DSC_E :: PF_CTRL 2203 */ 2204 /* DSC_E :: PF_CTRL :: reserved0 [15:04] */ 2205 #define DSC_E_PF_CTRL_RESERVED0_MASK 0xfff0 2206 #define DSC_E_PF_CTRL_RESERVED0_ALIGN 0 2207 #define DSC_E_PF_CTRL_RESERVED0_BITS 12 2208 #define DSC_E_PF_CTRL_RESERVED0_SHIFT 4 2209 2210 /* DSC_E :: PF_CTRL :: pf_ctrl [03:00] */ 2211 #define DSC_E_PF_CTRL_PF_CTRL_MASK 0x000f 2212 #define DSC_E_PF_CTRL_PF_CTRL_ALIGN 0 2213 #define DSC_E_PF_CTRL_PF_CTRL_BITS 4 2214 #define DSC_E_PF_CTRL_PF_CTRL_SHIFT 0 2215 2216 2217 /**************************************************************************** 2218 * DSC_E :: PF2_LOWP_CTRL 2219 */ 2220 /* DSC_E :: PF2_LOWP_CTRL :: reserved0 [15:03] */ 2221 #define DSC_E_PF2_LOWP_CTRL_RESERVED0_MASK 0xfff8 2222 #define DSC_E_PF2_LOWP_CTRL_RESERVED0_ALIGN 0 2223 #define DSC_E_PF2_LOWP_CTRL_RESERVED0_BITS 13 2224 #define DSC_E_PF2_LOWP_CTRL_RESERVED0_SHIFT 3 2225 2226 /* DSC_E :: PF2_LOWP_CTRL :: pf2_lowp_ctrl [02:00] */ 2227 #define DSC_E_PF2_LOWP_CTRL_PF2_LOWP_CTRL_MASK 0x0007 2228 #define DSC_E_PF2_LOWP_CTRL_PF2_LOWP_CTRL_ALIGN 0 2229 #define DSC_E_PF2_LOWP_CTRL_PF2_LOWP_CTRL_BITS 3 2230 #define DSC_E_PF2_LOWP_CTRL_PF2_LOWP_CTRL_SHIFT 0 2231 2232 2233 /**************************************************************************** 2234 * DSC_E :: OFFSET_ADJ_DATA_ODD 2235 */ 2236 /* DSC_E :: OFFSET_ADJ_DATA_ODD :: reserved0 [15:06] */ 2237 #define DSC_E_OFFSET_ADJ_DATA_ODD_RESERVED0_MASK 0xffc0 2238 #define DSC_E_OFFSET_ADJ_DATA_ODD_RESERVED0_ALIGN 0 2239 #define DSC_E_OFFSET_ADJ_DATA_ODD_RESERVED0_BITS 10 2240 #define DSC_E_OFFSET_ADJ_DATA_ODD_RESERVED0_SHIFT 6 2241 2242 /* DSC_E :: OFFSET_ADJ_DATA_ODD :: dfe_offset_adj_data_odd [05:00] */ 2243 #define DSC_E_OFFSET_ADJ_DATA_ODD_DFE_OFFSET_ADJ_DATA_ODD_MASK 0x003f 2244 #define DSC_E_OFFSET_ADJ_DATA_ODD_DFE_OFFSET_ADJ_DATA_ODD_ALIGN 0 2245 #define DSC_E_OFFSET_ADJ_DATA_ODD_DFE_OFFSET_ADJ_DATA_ODD_BITS 6 2246 #define DSC_E_OFFSET_ADJ_DATA_ODD_DFE_OFFSET_ADJ_DATA_ODD_SHIFT 0 2247 2248 2249 /**************************************************************************** 2250 * DSC_E :: OFFSET_ADJ_DATA_EVEN 2251 */ 2252 /* DSC_E :: OFFSET_ADJ_DATA_EVEN :: reserved0 [15:06] */ 2253 #define DSC_E_OFFSET_ADJ_DATA_EVEN_RESERVED0_MASK 0xffc0 2254 #define DSC_E_OFFSET_ADJ_DATA_EVEN_RESERVED0_ALIGN 0 2255 #define DSC_E_OFFSET_ADJ_DATA_EVEN_RESERVED0_BITS 10 2256 #define DSC_E_OFFSET_ADJ_DATA_EVEN_RESERVED0_SHIFT 6 2257 2258 /* DSC_E :: OFFSET_ADJ_DATA_EVEN :: dfe_offset_adj_data_even [05:00] */ 2259 #define DSC_E_OFFSET_ADJ_DATA_EVEN_DFE_OFFSET_ADJ_DATA_EVEN_MASK 0x003f 2260 #define DSC_E_OFFSET_ADJ_DATA_EVEN_DFE_OFFSET_ADJ_DATA_EVEN_ALIGN 0 2261 #define DSC_E_OFFSET_ADJ_DATA_EVEN_DFE_OFFSET_ADJ_DATA_EVEN_BITS 6 2262 #define DSC_E_OFFSET_ADJ_DATA_EVEN_DFE_OFFSET_ADJ_DATA_EVEN_SHIFT 0 2263 2264 2265 /**************************************************************************** 2266 * DSC_E :: OFFSET_ADJ_P1_ODD 2267 */ 2268 /* DSC_E :: OFFSET_ADJ_P1_ODD :: reserved0 [15:06] */ 2269 #define DSC_E_OFFSET_ADJ_P1_ODD_RESERVED0_MASK 0xffc0 2270 #define DSC_E_OFFSET_ADJ_P1_ODD_RESERVED0_ALIGN 0 2271 #define DSC_E_OFFSET_ADJ_P1_ODD_RESERVED0_BITS 10 2272 #define DSC_E_OFFSET_ADJ_P1_ODD_RESERVED0_SHIFT 6 2273 2274 /* DSC_E :: OFFSET_ADJ_P1_ODD :: dfe_offset_adj_p1_odd [05:00] */ 2275 #define DSC_E_OFFSET_ADJ_P1_ODD_DFE_OFFSET_ADJ_P1_ODD_MASK 0x003f 2276 #define DSC_E_OFFSET_ADJ_P1_ODD_DFE_OFFSET_ADJ_P1_ODD_ALIGN 0 2277 #define DSC_E_OFFSET_ADJ_P1_ODD_DFE_OFFSET_ADJ_P1_ODD_BITS 6 2278 #define DSC_E_OFFSET_ADJ_P1_ODD_DFE_OFFSET_ADJ_P1_ODD_SHIFT 0 2279 2280 2281 /**************************************************************************** 2282 * DSC_E :: OFFSET_ADJ_P1_EVEN 2283 */ 2284 /* DSC_E :: OFFSET_ADJ_P1_EVEN :: reserved0 [15:06] */ 2285 #define DSC_E_OFFSET_ADJ_P1_EVEN_RESERVED0_MASK 0xffc0 2286 #define DSC_E_OFFSET_ADJ_P1_EVEN_RESERVED0_ALIGN 0 2287 #define DSC_E_OFFSET_ADJ_P1_EVEN_RESERVED0_BITS 10 2288 #define DSC_E_OFFSET_ADJ_P1_EVEN_RESERVED0_SHIFT 6 2289 2290 /* DSC_E :: OFFSET_ADJ_P1_EVEN :: dfe_offset_adj_p1_even [05:00] */ 2291 #define DSC_E_OFFSET_ADJ_P1_EVEN_DFE_OFFSET_ADJ_P1_EVEN_MASK 0x003f 2292 #define DSC_E_OFFSET_ADJ_P1_EVEN_DFE_OFFSET_ADJ_P1_EVEN_ALIGN 0 2293 #define DSC_E_OFFSET_ADJ_P1_EVEN_DFE_OFFSET_ADJ_P1_EVEN_BITS 6 2294 #define DSC_E_OFFSET_ADJ_P1_EVEN_DFE_OFFSET_ADJ_P1_EVEN_SHIFT 0 2295 2296 2297 /**************************************************************************** 2298 * DSC_E :: OFFSET_ADJ_M1_ODD 2299 */ 2300 /* DSC_E :: OFFSET_ADJ_M1_ODD :: reserved0 [15:06] */ 2301 #define DSC_E_OFFSET_ADJ_M1_ODD_RESERVED0_MASK 0xffc0 2302 #define DSC_E_OFFSET_ADJ_M1_ODD_RESERVED0_ALIGN 0 2303 #define DSC_E_OFFSET_ADJ_M1_ODD_RESERVED0_BITS 10 2304 #define DSC_E_OFFSET_ADJ_M1_ODD_RESERVED0_SHIFT 6 2305 2306 /* DSC_E :: OFFSET_ADJ_M1_ODD :: dfe_offset_adj_m1_odd [05:00] */ 2307 #define DSC_E_OFFSET_ADJ_M1_ODD_DFE_OFFSET_ADJ_M1_ODD_MASK 0x003f 2308 #define DSC_E_OFFSET_ADJ_M1_ODD_DFE_OFFSET_ADJ_M1_ODD_ALIGN 0 2309 #define DSC_E_OFFSET_ADJ_M1_ODD_DFE_OFFSET_ADJ_M1_ODD_BITS 6 2310 #define DSC_E_OFFSET_ADJ_M1_ODD_DFE_OFFSET_ADJ_M1_ODD_SHIFT 0 2311 2312 2313 /**************************************************************************** 2314 * DSC_E :: OFFSET_ADJ_M1_EVEN 2315 */ 2316 /* DSC_E :: OFFSET_ADJ_M1_EVEN :: reserved0 [15:06] */ 2317 #define DSC_E_OFFSET_ADJ_M1_EVEN_RESERVED0_MASK 0xffc0 2318 #define DSC_E_OFFSET_ADJ_M1_EVEN_RESERVED0_ALIGN 0 2319 #define DSC_E_OFFSET_ADJ_M1_EVEN_RESERVED0_BITS 10 2320 #define DSC_E_OFFSET_ADJ_M1_EVEN_RESERVED0_SHIFT 6 2321 2322 /* DSC_E :: OFFSET_ADJ_M1_EVEN :: dfe_offset_adj_m1_even [05:00] */ 2323 #define DSC_E_OFFSET_ADJ_M1_EVEN_DFE_OFFSET_ADJ_M1_EVEN_MASK 0x003f 2324 #define DSC_E_OFFSET_ADJ_M1_EVEN_DFE_OFFSET_ADJ_M1_EVEN_ALIGN 0 2325 #define DSC_E_OFFSET_ADJ_M1_EVEN_DFE_OFFSET_ADJ_M1_EVEN_BITS 6 2326 #define DSC_E_OFFSET_ADJ_M1_EVEN_DFE_OFFSET_ADJ_M1_EVEN_SHIFT 0 2327 2328 2329 /**************************************************************************** 2330 * DSC_E :: DC_OFFSET 2331 */ 2332 /* DSC_E :: DC_OFFSET :: reserved0 [15:07] */ 2333 #define DSC_E_DC_OFFSET_RESERVED0_MASK 0xff80 2334 #define DSC_E_DC_OFFSET_RESERVED0_ALIGN 0 2335 #define DSC_E_DC_OFFSET_RESERVED0_BITS 9 2336 #define DSC_E_DC_OFFSET_RESERVED0_SHIFT 7 2337 2338 /* DSC_E :: DC_OFFSET :: dc_offset [06:00] */ 2339 #define DSC_E_DC_OFFSET_DC_OFFSET_MASK 0x007f 2340 #define DSC_E_DC_OFFSET_DC_OFFSET_ALIGN 0 2341 #define DSC_E_DC_OFFSET_DC_OFFSET_BITS 7 2342 #define DSC_E_DC_OFFSET_DC_OFFSET_SHIFT 0 2343 2344 2345 /**************************************************************************** 2346 * eagle_tsc_cl72_user_blk_CL72_USER_RX 2347 */ 2348 /**************************************************************************** 2349 * CL72_USER_RX :: RCVD_STATUS_REGISTER 2350 */ 2351 /* CL72_USER_RX :: RCVD_STATUS_REGISTER :: cl72_rcvd_status_page [15:00] */ 2352 #define CL72_USER_RX_RCVD_STATUS_REGISTER_CL72_RCVD_STATUS_PAGE_MASK 0xffff 2353 #define CL72_USER_RX_RCVD_STATUS_REGISTER_CL72_RCVD_STATUS_PAGE_ALIGN 0 2354 #define CL72_USER_RX_RCVD_STATUS_REGISTER_CL72_RCVD_STATUS_PAGE_BITS 16 2355 #define CL72_USER_RX_RCVD_STATUS_REGISTER_CL72_RCVD_STATUS_PAGE_SHIFT 0 2356 2357 2358 /**************************************************************************** 2359 * CL72_USER_RX :: MISC1_CONTROL 2360 */ 2361 /* CL72_USER_RX :: MISC1_CONTROL :: reserved0 [15:03] */ 2362 #define CL72_USER_RX_MISC1_CONTROL_RESERVED0_MASK 0xfff8 2363 #define CL72_USER_RX_MISC1_CONTROL_RESERVED0_ALIGN 0 2364 #define CL72_USER_RX_MISC1_CONTROL_RESERVED0_BITS 13 2365 #define CL72_USER_RX_MISC1_CONTROL_RESERVED0_SHIFT 3 2366 2367 /* CL72_USER_RX :: MISC1_CONTROL :: cl72_rx_dp_ln_clk_en [02:02] */ 2368 #define CL72_USER_RX_MISC1_CONTROL_CL72_RX_DP_LN_CLK_EN_MASK 0x0004 2369 #define CL72_USER_RX_MISC1_CONTROL_CL72_RX_DP_LN_CLK_EN_ALIGN 0 2370 #define CL72_USER_RX_MISC1_CONTROL_CL72_RX_DP_LN_CLK_EN_BITS 1 2371 #define CL72_USER_RX_MISC1_CONTROL_CL72_RX_DP_LN_CLK_EN_SHIFT 2 2372 2373 /* CL72_USER_RX :: MISC1_CONTROL :: cl72_tr_coarse_lock [01:01] */ 2374 #define CL72_USER_RX_MISC1_CONTROL_CL72_TR_COARSE_LOCK_MASK 0x0002 2375 #define CL72_USER_RX_MISC1_CONTROL_CL72_TR_COARSE_LOCK_ALIGN 0 2376 #define CL72_USER_RX_MISC1_CONTROL_CL72_TR_COARSE_LOCK_BITS 1 2377 #define CL72_USER_RX_MISC1_CONTROL_CL72_TR_COARSE_LOCK_SHIFT 1 2378 2379 /* CL72_USER_RX :: MISC1_CONTROL :: reserved1 [00:00] */ 2380 #define CL72_USER_RX_MISC1_CONTROL_RESERVED1_MASK 0x0001 2381 #define CL72_USER_RX_MISC1_CONTROL_RESERVED1_ALIGN 0 2382 #define CL72_USER_RX_MISC1_CONTROL_RESERVED1_BITS 1 2383 #define CL72_USER_RX_MISC1_CONTROL_RESERVED1_SHIFT 0 2384 2385 2386 /**************************************************************************** 2387 * CL72_USER_RX :: DEBUG_2_REGISTER 2388 */ 2389 /* CL72_USER_RX :: DEBUG_2_REGISTER :: reserved0 [15:15] */ 2390 #define CL72_USER_RX_DEBUG_2_REGISTER_RESERVED0_MASK 0x8000 2391 #define CL72_USER_RX_DEBUG_2_REGISTER_RESERVED0_ALIGN 0 2392 #define CL72_USER_RX_DEBUG_2_REGISTER_RESERVED0_BITS 1 2393 #define CL72_USER_RX_DEBUG_2_REGISTER_RESERVED0_SHIFT 15 2394 2395 /* CL72_USER_RX :: DEBUG_2_REGISTER :: cl72_ppm_offset_en [14:14] */ 2396 #define CL72_USER_RX_DEBUG_2_REGISTER_CL72_PPM_OFFSET_EN_MASK 0x4000 2397 #define CL72_USER_RX_DEBUG_2_REGISTER_CL72_PPM_OFFSET_EN_ALIGN 0 2398 #define CL72_USER_RX_DEBUG_2_REGISTER_CL72_PPM_OFFSET_EN_BITS 1 2399 #define CL72_USER_RX_DEBUG_2_REGISTER_CL72_PPM_OFFSET_EN_SHIFT 14 2400 2401 /* CL72_USER_RX :: DEBUG_2_REGISTER :: cl72_strict_marker_chk [13:13] */ 2402 #define CL72_USER_RX_DEBUG_2_REGISTER_CL72_STRICT_MARKER_CHK_MASK 0x2000 2403 #define CL72_USER_RX_DEBUG_2_REGISTER_CL72_STRICT_MARKER_CHK_ALIGN 0 2404 #define CL72_USER_RX_DEBUG_2_REGISTER_CL72_STRICT_MARKER_CHK_BITS 1 2405 #define CL72_USER_RX_DEBUG_2_REGISTER_CL72_STRICT_MARKER_CHK_SHIFT 13 2406 2407 /* CL72_USER_RX :: DEBUG_2_REGISTER :: cl72_strict_dme_chk [12:12] */ 2408 #define CL72_USER_RX_DEBUG_2_REGISTER_CL72_STRICT_DME_CHK_MASK 0x1000 2409 #define CL72_USER_RX_DEBUG_2_REGISTER_CL72_STRICT_DME_CHK_ALIGN 0 2410 #define CL72_USER_RX_DEBUG_2_REGISTER_CL72_STRICT_DME_CHK_BITS 1 2411 #define CL72_USER_RX_DEBUG_2_REGISTER_CL72_STRICT_DME_CHK_SHIFT 12 2412 2413 /* CL72_USER_RX :: DEBUG_2_REGISTER :: cl72_ctrl_frame_dly [11:08] */ 2414 #define CL72_USER_RX_DEBUG_2_REGISTER_CL72_CTRL_FRAME_DLY_MASK 0x0f00 2415 #define CL72_USER_RX_DEBUG_2_REGISTER_CL72_CTRL_FRAME_DLY_ALIGN 0 2416 #define CL72_USER_RX_DEBUG_2_REGISTER_CL72_CTRL_FRAME_DLY_BITS 4 2417 #define CL72_USER_RX_DEBUG_2_REGISTER_CL72_CTRL_FRAME_DLY_SHIFT 8 2418 2419 /* CL72_USER_RX :: DEBUG_2_REGISTER :: cl72_dme_cell_boundary_chk [07:07] */ 2420 #define CL72_USER_RX_DEBUG_2_REGISTER_CL72_DME_CELL_BOUNDARY_CHK_MASK 0x0080 2421 #define CL72_USER_RX_DEBUG_2_REGISTER_CL72_DME_CELL_BOUNDARY_CHK_ALIGN 0 2422 #define CL72_USER_RX_DEBUG_2_REGISTER_CL72_DME_CELL_BOUNDARY_CHK_BITS 1 2423 #define CL72_USER_RX_DEBUG_2_REGISTER_CL72_DME_CELL_BOUNDARY_CHK_SHIFT 7 2424 2425 /* CL72_USER_RX :: DEBUG_2_REGISTER :: reserved1 [06:05] */ 2426 #define CL72_USER_RX_DEBUG_2_REGISTER_RESERVED1_MASK 0x0060 2427 #define CL72_USER_RX_DEBUG_2_REGISTER_RESERVED1_ALIGN 0 2428 #define CL72_USER_RX_DEBUG_2_REGISTER_RESERVED1_BITS 2 2429 #define CL72_USER_RX_DEBUG_2_REGISTER_RESERVED1_SHIFT 5 2430 2431 /* CL72_USER_RX :: DEBUG_2_REGISTER :: cl72_bad_marker_cnt [04:02] */ 2432 #define CL72_USER_RX_DEBUG_2_REGISTER_CL72_BAD_MARKER_CNT_MASK 0x001c 2433 #define CL72_USER_RX_DEBUG_2_REGISTER_CL72_BAD_MARKER_CNT_ALIGN 0 2434 #define CL72_USER_RX_DEBUG_2_REGISTER_CL72_BAD_MARKER_CNT_BITS 3 2435 #define CL72_USER_RX_DEBUG_2_REGISTER_CL72_BAD_MARKER_CNT_SHIFT 2 2436 2437 /* CL72_USER_RX :: DEBUG_2_REGISTER :: cl72_good_marker_cnt [01:00] */ 2438 #define CL72_USER_RX_DEBUG_2_REGISTER_CL72_GOOD_MARKER_CNT_MASK 0x0003 2439 #define CL72_USER_RX_DEBUG_2_REGISTER_CL72_GOOD_MARKER_CNT_ALIGN 0 2440 #define CL72_USER_RX_DEBUG_2_REGISTER_CL72_GOOD_MARKER_CNT_BITS 2 2441 #define CL72_USER_RX_DEBUG_2_REGISTER_CL72_GOOD_MARKER_CNT_SHIFT 0 2442 2443 2444 /**************************************************************************** 2445 * CL72_USER_RX :: CL72_LP_CONTROL_PAGE 2446 */ 2447 /* CL72_USER_RX :: CL72_LP_CONTROL_PAGE :: cl72_lp_control_page [15:00] */ 2448 #define CL72_USER_RX_CL72_LP_CONTROL_PAGE_CL72_LP_CONTROL_PAGE_MASK 0xffff 2449 #define CL72_USER_RX_CL72_LP_CONTROL_PAGE_CL72_LP_CONTROL_PAGE_ALIGN 0 2450 #define CL72_USER_RX_CL72_LP_CONTROL_PAGE_CL72_LP_CONTROL_PAGE_BITS 16 2451 #define CL72_USER_RX_CL72_LP_CONTROL_PAGE_CL72_LP_CONTROL_PAGE_SHIFT 0 2452 2453 2454 /**************************************************************************** 2455 * CL72_USER_RX :: CL72_STATUS1_REGISTER 2456 */ 2457 /* CL72_USER_RX :: CL72_STATUS1_REGISTER :: reserved0 [15:01] */ 2458 #define CL72_USER_RX_CL72_STATUS1_REGISTER_RESERVED0_MASK 0xfffe 2459 #define CL72_USER_RX_CL72_STATUS1_REGISTER_RESERVED0_ALIGN 0 2460 #define CL72_USER_RX_CL72_STATUS1_REGISTER_RESERVED0_BITS 15 2461 #define CL72_USER_RX_CL72_STATUS1_REGISTER_RESERVED0_SHIFT 1 2462 2463 /* CL72_USER_RX :: CL72_STATUS1_REGISTER :: cl72_signal_detect [00:00] */ 2464 #define CL72_USER_RX_CL72_STATUS1_REGISTER_CL72_SIGNAL_DETECT_MASK 0x0001 2465 #define CL72_USER_RX_CL72_STATUS1_REGISTER_CL72_SIGNAL_DETECT_ALIGN 0 2466 #define CL72_USER_RX_CL72_STATUS1_REGISTER_CL72_SIGNAL_DETECT_BITS 1 2467 #define CL72_USER_RX_CL72_STATUS1_REGISTER_CL72_SIGNAL_DETECT_SHIFT 0 2468 2469 2470 /**************************************************************************** 2471 * eagle_tsc_cl72_user_blk_CL72_USER_TX 2472 */ 2473 /**************************************************************************** 2474 * CL72_USER_TX :: XMT_UPDATE_REGISTER 2475 */ 2476 /* CL72_USER_TX :: XMT_UPDATE_REGISTER :: cl72_xmt_update_page [15:00] */ 2477 #define CL72_USER_TX_XMT_UPDATE_REGISTER_CL72_XMT_UPDATE_PAGE_MASK 0xffff 2478 #define CL72_USER_TX_XMT_UPDATE_REGISTER_CL72_XMT_UPDATE_PAGE_ALIGN 0 2479 #define CL72_USER_TX_XMT_UPDATE_REGISTER_CL72_XMT_UPDATE_PAGE_BITS 16 2480 #define CL72_USER_TX_XMT_UPDATE_REGISTER_CL72_XMT_UPDATE_PAGE_SHIFT 0 2481 2482 2483 /**************************************************************************** 2484 * CL72_USER_TX :: MISC2_CONTROL 2485 */ 2486 /* CL72_USER_TX :: MISC2_CONTROL :: reserved0 [15:03] */ 2487 #define CL72_USER_TX_MISC2_CONTROL_RESERVED0_MASK 0xfff8 2488 #define CL72_USER_TX_MISC2_CONTROL_RESERVED0_ALIGN 0 2489 #define CL72_USER_TX_MISC2_CONTROL_RESERVED0_BITS 13 2490 #define CL72_USER_TX_MISC2_CONTROL_RESERVED0_SHIFT 3 2491 2492 /* CL72_USER_TX :: MISC2_CONTROL :: cl72_tx_dp_ln_clk_en [02:02] */ 2493 #define CL72_USER_TX_MISC2_CONTROL_CL72_TX_DP_LN_CLK_EN_MASK 0x0004 2494 #define CL72_USER_TX_MISC2_CONTROL_CL72_TX_DP_LN_CLK_EN_ALIGN 0 2495 #define CL72_USER_TX_MISC2_CONTROL_CL72_TX_DP_LN_CLK_EN_BITS 1 2496 #define CL72_USER_TX_MISC2_CONTROL_CL72_TX_DP_LN_CLK_EN_SHIFT 2 2497 2498 /* CL72_USER_TX :: MISC2_CONTROL :: cl72_signal_det_frc [01:01] */ 2499 #define CL72_USER_TX_MISC2_CONTROL_CL72_SIGNAL_DET_FRC_MASK 0x0002 2500 #define CL72_USER_TX_MISC2_CONTROL_CL72_SIGNAL_DET_FRC_ALIGN 0 2501 #define CL72_USER_TX_MISC2_CONTROL_CL72_SIGNAL_DET_FRC_BITS 1 2502 #define CL72_USER_TX_MISC2_CONTROL_CL72_SIGNAL_DET_FRC_SHIFT 1 2503 2504 /* CL72_USER_TX :: MISC2_CONTROL :: cl72_rx_trained [00:00] */ 2505 #define CL72_USER_TX_MISC2_CONTROL_CL72_RX_TRAINED_MASK 0x0001 2506 #define CL72_USER_TX_MISC2_CONTROL_CL72_RX_TRAINED_ALIGN 0 2507 #define CL72_USER_TX_MISC2_CONTROL_CL72_RX_TRAINED_BITS 1 2508 #define CL72_USER_TX_MISC2_CONTROL_CL72_RX_TRAINED_SHIFT 0 2509 2510 2511 /**************************************************************************** 2512 * CL72_USER_TX :: DEBUG_3_REGISTER 2513 */ 2514 /* CL72_USER_TX :: DEBUG_3_REGISTER :: reserved0 [15:02] */ 2515 #define CL72_USER_TX_DEBUG_3_REGISTER_RESERVED0_MASK 0xfffc 2516 #define CL72_USER_TX_DEBUG_3_REGISTER_RESERVED0_ALIGN 0 2517 #define CL72_USER_TX_DEBUG_3_REGISTER_RESERVED0_BITS 14 2518 #define CL72_USER_TX_DEBUG_3_REGISTER_RESERVED0_SHIFT 2 2519 2520 /* CL72_USER_TX :: DEBUG_3_REGISTER :: cl72_frame_lock_rdy_for_cmd_en [01:01] */ 2521 #define CL72_USER_TX_DEBUG_3_REGISTER_CL72_FRAME_LOCK_RDY_FOR_CMD_EN_MASK 0x0002 2522 #define CL72_USER_TX_DEBUG_3_REGISTER_CL72_FRAME_LOCK_RDY_FOR_CMD_EN_ALIGN 0 2523 #define CL72_USER_TX_DEBUG_3_REGISTER_CL72_FRAME_LOCK_RDY_FOR_CMD_EN_BITS 1 2524 #define CL72_USER_TX_DEBUG_3_REGISTER_CL72_FRAME_LOCK_RDY_FOR_CMD_EN_SHIFT 1 2525 2526 /* CL72_USER_TX :: DEBUG_3_REGISTER :: cl72_brk_ring_osc [00:00] */ 2527 #define CL72_USER_TX_DEBUG_3_REGISTER_CL72_BRK_RING_OSC_MASK 0x0001 2528 #define CL72_USER_TX_DEBUG_3_REGISTER_CL72_BRK_RING_OSC_ALIGN 0 2529 #define CL72_USER_TX_DEBUG_3_REGISTER_CL72_BRK_RING_OSC_BITS 1 2530 #define CL72_USER_TX_DEBUG_3_REGISTER_CL72_BRK_RING_OSC_SHIFT 0 2531 2532 2533 /**************************************************************************** 2534 * CL72_USER_TX :: PCS_INTERFACE_CONTROL_REGISTER 2535 */ 2536 /* CL72_USER_TX :: PCS_INTERFACE_CONTROL_REGISTER :: reserved0 [15:01] */ 2537 #define CL72_USER_TX_PCS_INTERFACE_CONTROL_REGISTER_RESERVED0_MASK 0xfffe 2538 #define CL72_USER_TX_PCS_INTERFACE_CONTROL_REGISTER_RESERVED0_ALIGN 0 2539 #define CL72_USER_TX_PCS_INTERFACE_CONTROL_REGISTER_RESERVED0_BITS 15 2540 #define CL72_USER_TX_PCS_INTERFACE_CONTROL_REGISTER_RESERVED0_SHIFT 1 2541 2542 /* CL72_USER_TX :: PCS_INTERFACE_CONTROL_REGISTER :: cl72_dis_max_wait_timer [00:00] */ 2543 #define CL72_USER_TX_PCS_INTERFACE_CONTROL_REGISTER_CL72_DIS_MAX_WAIT_TIMER_MASK 0x0001 2544 #define CL72_USER_TX_PCS_INTERFACE_CONTROL_REGISTER_CL72_DIS_MAX_WAIT_TIMER_ALIGN 0 2545 #define CL72_USER_TX_PCS_INTERFACE_CONTROL_REGISTER_CL72_DIS_MAX_WAIT_TIMER_BITS 1 2546 #define CL72_USER_TX_PCS_INTERFACE_CONTROL_REGISTER_CL72_DIS_MAX_WAIT_TIMER_SHIFT 0 2547 2548 2549 /**************************************************************************** 2550 * CL72_USER_TX :: CL72_LD_STATUS_PAGE 2551 */ 2552 /* CL72_USER_TX :: CL72_LD_STATUS_PAGE :: cl72_ld_status_page [15:00] */ 2553 #define CL72_USER_TX_CL72_LD_STATUS_PAGE_CL72_LD_STATUS_PAGE_MASK 0xffff 2554 #define CL72_USER_TX_CL72_LD_STATUS_PAGE_CL72_LD_STATUS_PAGE_ALIGN 0 2555 #define CL72_USER_TX_CL72_LD_STATUS_PAGE_CL72_LD_STATUS_PAGE_BITS 16 2556 #define CL72_USER_TX_CL72_LD_STATUS_PAGE_CL72_LD_STATUS_PAGE_SHIFT 0 2557 2558 2559 /**************************************************************************** 2560 * CL72_USER_TX :: CL72_READY_FOR_CMD_REGISTER 2561 */ 2562 /* CL72_USER_TX :: CL72_READY_FOR_CMD_REGISTER :: reserved0 [15:01] */ 2563 #define CL72_USER_TX_CL72_READY_FOR_CMD_REGISTER_RESERVED0_MASK 0xfffe 2564 #define CL72_USER_TX_CL72_READY_FOR_CMD_REGISTER_RESERVED0_ALIGN 0 2565 #define CL72_USER_TX_CL72_READY_FOR_CMD_REGISTER_RESERVED0_BITS 15 2566 #define CL72_USER_TX_CL72_READY_FOR_CMD_REGISTER_RESERVED0_SHIFT 1 2567 2568 /* CL72_USER_TX :: CL72_READY_FOR_CMD_REGISTER :: cl72_ready_for_cmd [00:00] */ 2569 #define CL72_USER_TX_CL72_READY_FOR_CMD_REGISTER_CL72_READY_FOR_CMD_MASK 0x0001 2570 #define CL72_USER_TX_CL72_READY_FOR_CMD_REGISTER_CL72_READY_FOR_CMD_ALIGN 0 2571 #define CL72_USER_TX_CL72_READY_FOR_CMD_REGISTER_CL72_READY_FOR_CMD_BITS 1 2572 #define CL72_USER_TX_CL72_READY_FOR_CMD_REGISTER_CL72_READY_FOR_CMD_SHIFT 0 2573 2574 2575 /**************************************************************************** 2576 * CL72_USER_TX :: KR_DEFAULT_CONTROL1 2577 */ 2578 /* CL72_USER_TX :: KR_DEFAULT_CONTROL1 :: reserved0 [15:11] */ 2579 #define CL72_USER_TX_KR_DEFAULT_CONTROL1_RESERVED0_MASK 0xf800 2580 #define CL72_USER_TX_KR_DEFAULT_CONTROL1_RESERVED0_ALIGN 0 2581 #define CL72_USER_TX_KR_DEFAULT_CONTROL1_RESERVED0_BITS 5 2582 #define CL72_USER_TX_KR_DEFAULT_CONTROL1_RESERVED0_SHIFT 11 2583 2584 /* CL72_USER_TX :: KR_DEFAULT_CONTROL1 :: cl72_tx_fir_tap_post_kr_init_val [10:05] */ 2585 #define CL72_USER_TX_KR_DEFAULT_CONTROL1_CL72_TX_FIR_TAP_POST_KR_INIT_VAL_MASK 0x07e0 2586 #define CL72_USER_TX_KR_DEFAULT_CONTROL1_CL72_TX_FIR_TAP_POST_KR_INIT_VAL_ALIGN 0 2587 #define CL72_USER_TX_KR_DEFAULT_CONTROL1_CL72_TX_FIR_TAP_POST_KR_INIT_VAL_BITS 6 2588 #define CL72_USER_TX_KR_DEFAULT_CONTROL1_CL72_TX_FIR_TAP_POST_KR_INIT_VAL_SHIFT 5 2589 2590 /* CL72_USER_TX :: KR_DEFAULT_CONTROL1 :: cl72_tx_fir_tap_pre_kr_init_val [04:00] */ 2591 #define CL72_USER_TX_KR_DEFAULT_CONTROL1_CL72_TX_FIR_TAP_PRE_KR_INIT_VAL_MASK 0x001f 2592 #define CL72_USER_TX_KR_DEFAULT_CONTROL1_CL72_TX_FIR_TAP_PRE_KR_INIT_VAL_ALIGN 0 2593 #define CL72_USER_TX_KR_DEFAULT_CONTROL1_CL72_TX_FIR_TAP_PRE_KR_INIT_VAL_BITS 5 2594 #define CL72_USER_TX_KR_DEFAULT_CONTROL1_CL72_TX_FIR_TAP_PRE_KR_INIT_VAL_SHIFT 0 2595 2596 2597 /**************************************************************************** 2598 * CL72_USER_TX :: KR_DEFAULT_CONTROL2 2599 */ 2600 /* CL72_USER_TX :: KR_DEFAULT_CONTROL2 :: reserved0 [15:07] */ 2601 #define CL72_USER_TX_KR_DEFAULT_CONTROL2_RESERVED0_MASK 0xff80 2602 #define CL72_USER_TX_KR_DEFAULT_CONTROL2_RESERVED0_ALIGN 0 2603 #define CL72_USER_TX_KR_DEFAULT_CONTROL2_RESERVED0_BITS 9 2604 #define CL72_USER_TX_KR_DEFAULT_CONTROL2_RESERVED0_SHIFT 7 2605 2606 /* CL72_USER_TX :: KR_DEFAULT_CONTROL2 :: cl72_tx_fir_tap_main_kr_init_val [06:00] */ 2607 #define CL72_USER_TX_KR_DEFAULT_CONTROL2_CL72_TX_FIR_TAP_MAIN_KR_INIT_VAL_MASK 0x007f 2608 #define CL72_USER_TX_KR_DEFAULT_CONTROL2_CL72_TX_FIR_TAP_MAIN_KR_INIT_VAL_ALIGN 0 2609 #define CL72_USER_TX_KR_DEFAULT_CONTROL2_CL72_TX_FIR_TAP_MAIN_KR_INIT_VAL_BITS 7 2610 #define CL72_USER_TX_KR_DEFAULT_CONTROL2_CL72_TX_FIR_TAP_MAIN_KR_INIT_VAL_SHIFT 0 2611 2612 2613 /**************************************************************************** 2614 * CL72_USER_TX :: MISC_COEFF_CONTROL 2615 */ 2616 /* CL72_USER_TX :: MISC_COEFF_CONTROL :: reserved0 [15:13] */ 2617 #define CL72_USER_TX_MISC_COEFF_CONTROL_RESERVED0_MASK 0xe000 2618 #define CL72_USER_TX_MISC_COEFF_CONTROL_RESERVED0_ALIGN 0 2619 #define CL72_USER_TX_MISC_COEFF_CONTROL_RESERVED0_BITS 3 2620 #define CL72_USER_TX_MISC_COEFF_CONTROL_RESERVED0_SHIFT 13 2621 2622 /* CL72_USER_TX :: MISC_COEFF_CONTROL :: cl72_double_cmd_en [12:12] */ 2623 #define CL72_USER_TX_MISC_COEFF_CONTROL_CL72_DOUBLE_CMD_EN_MASK 0x1000 2624 #define CL72_USER_TX_MISC_COEFF_CONTROL_CL72_DOUBLE_CMD_EN_ALIGN 0 2625 #define CL72_USER_TX_MISC_COEFF_CONTROL_CL72_DOUBLE_CMD_EN_BITS 1 2626 #define CL72_USER_TX_MISC_COEFF_CONTROL_CL72_DOUBLE_CMD_EN_SHIFT 12 2627 2628 /* CL72_USER_TX :: MISC_COEFF_CONTROL :: cl72_dis_lp_coeff_updates_to_ld [11:11] */ 2629 #define CL72_USER_TX_MISC_COEFF_CONTROL_CL72_DIS_LP_COEFF_UPDATES_TO_LD_MASK 0x0800 2630 #define CL72_USER_TX_MISC_COEFF_CONTROL_CL72_DIS_LP_COEFF_UPDATES_TO_LD_ALIGN 0 2631 #define CL72_USER_TX_MISC_COEFF_CONTROL_CL72_DIS_LP_COEFF_UPDATES_TO_LD_BITS 1 2632 #define CL72_USER_TX_MISC_COEFF_CONTROL_CL72_DIS_LP_COEFF_UPDATES_TO_LD_SHIFT 11 2633 2634 /* CL72_USER_TX :: MISC_COEFF_CONTROL :: cl72_ld_xmt_status_override [10:10] */ 2635 #define CL72_USER_TX_MISC_COEFF_CONTROL_CL72_LD_XMT_STATUS_OVERRIDE_MASK 0x0400 2636 #define CL72_USER_TX_MISC_COEFF_CONTROL_CL72_LD_XMT_STATUS_OVERRIDE_ALIGN 0 2637 #define CL72_USER_TX_MISC_COEFF_CONTROL_CL72_LD_XMT_STATUS_OVERRIDE_BITS 1 2638 #define CL72_USER_TX_MISC_COEFF_CONTROL_CL72_LD_XMT_STATUS_OVERRIDE_SHIFT 10 2639 2640 /* CL72_USER_TX :: MISC_COEFF_CONTROL :: cl72_ld_xmt_status_load [09:09] */ 2641 #define CL72_USER_TX_MISC_COEFF_CONTROL_CL72_LD_XMT_STATUS_LOAD_MASK 0x0200 2642 #define CL72_USER_TX_MISC_COEFF_CONTROL_CL72_LD_XMT_STATUS_LOAD_ALIGN 0 2643 #define CL72_USER_TX_MISC_COEFF_CONTROL_CL72_LD_XMT_STATUS_LOAD_BITS 1 2644 #define CL72_USER_TX_MISC_COEFF_CONTROL_CL72_LD_XMT_STATUS_LOAD_SHIFT 9 2645 2646 /* CL72_USER_TX :: MISC_COEFF_CONTROL :: cl72_v2_constraint_dis [08:08] */ 2647 #define CL72_USER_TX_MISC_COEFF_CONTROL_CL72_V2_CONSTRAINT_DIS_MASK 0x0100 2648 #define CL72_USER_TX_MISC_COEFF_CONTROL_CL72_V2_CONSTRAINT_DIS_ALIGN 0 2649 #define CL72_USER_TX_MISC_COEFF_CONTROL_CL72_V2_CONSTRAINT_DIS_BITS 1 2650 #define CL72_USER_TX_MISC_COEFF_CONTROL_CL72_V2_CONSTRAINT_DIS_SHIFT 8 2651 2652 /* CL72_USER_TX :: MISC_COEFF_CONTROL :: cl72_tap_v2_val [07:02] */ 2653 #define CL72_USER_TX_MISC_COEFF_CONTROL_CL72_TAP_V2_VAL_MASK 0x00fc 2654 #define CL72_USER_TX_MISC_COEFF_CONTROL_CL72_TAP_V2_VAL_ALIGN 0 2655 #define CL72_USER_TX_MISC_COEFF_CONTROL_CL72_TAP_V2_VAL_BITS 6 2656 #define CL72_USER_TX_MISC_COEFF_CONTROL_CL72_TAP_V2_VAL_SHIFT 2 2657 2658 /* CL72_USER_TX :: MISC_COEFF_CONTROL :: cl72_inc_dec_val_sel [01:00] */ 2659 #define CL72_USER_TX_MISC_COEFF_CONTROL_CL72_INC_DEC_VAL_SEL_MASK 0x0003 2660 #define CL72_USER_TX_MISC_COEFF_CONTROL_CL72_INC_DEC_VAL_SEL_ALIGN 0 2661 #define CL72_USER_TX_MISC_COEFF_CONTROL_CL72_INC_DEC_VAL_SEL_BITS 2 2662 #define CL72_USER_TX_MISC_COEFF_CONTROL_CL72_INC_DEC_VAL_SEL_SHIFT 0 2663 2664 2665 /**************************************************************************** 2666 * CL72_USER_TX :: CL72_LD_XMT_STATUS_PAGE_OVERRIDE 2667 */ 2668 /* CL72_USER_TX :: CL72_LD_XMT_STATUS_PAGE_OVERRIDE :: cl72_override_ld_status_page [15:00] */ 2669 #define CL72_USER_TX_CL72_LD_XMT_STATUS_PAGE_OVERRIDE_CL72_OVERRIDE_LD_STATUS_PAGE_MASK 0xffff 2670 #define CL72_USER_TX_CL72_LD_XMT_STATUS_PAGE_OVERRIDE_CL72_OVERRIDE_LD_STATUS_PAGE_ALIGN 0 2671 #define CL72_USER_TX_CL72_LD_XMT_STATUS_PAGE_OVERRIDE_CL72_OVERRIDE_LD_STATUS_PAGE_BITS 16 2672 #define CL72_USER_TX_CL72_LD_XMT_STATUS_PAGE_OVERRIDE_CL72_OVERRIDE_LD_STATUS_PAGE_SHIFT 0 2673 2674 2675 /**************************************************************************** 2676 * CL72_USER_TX :: CL72_TX_DEBUG_STATUS 2677 */ 2678 /* CL72_USER_TX :: CL72_TX_DEBUG_STATUS :: reserved0 [15:12] */ 2679 #define CL72_USER_TX_CL72_TX_DEBUG_STATUS_RESERVED0_MASK 0xf000 2680 #define CL72_USER_TX_CL72_TX_DEBUG_STATUS_RESERVED0_ALIGN 0 2681 #define CL72_USER_TX_CL72_TX_DEBUG_STATUS_RESERVED0_BITS 4 2682 #define CL72_USER_TX_CL72_TX_DEBUG_STATUS_RESERVED0_SHIFT 12 2683 2684 /* CL72_USER_TX :: CL72_TX_DEBUG_STATUS :: cl72_frame_lock_lh [11:11] */ 2685 #define CL72_USER_TX_CL72_TX_DEBUG_STATUS_CL72_FRAME_LOCK_LH_MASK 0x0800 2686 #define CL72_USER_TX_CL72_TX_DEBUG_STATUS_CL72_FRAME_LOCK_LH_ALIGN 0 2687 #define CL72_USER_TX_CL72_TX_DEBUG_STATUS_CL72_FRAME_LOCK_LH_BITS 1 2688 #define CL72_USER_TX_CL72_TX_DEBUG_STATUS_CL72_FRAME_LOCK_LH_SHIFT 11 2689 2690 /* CL72_USER_TX :: CL72_TX_DEBUG_STATUS :: cl72_ld_coeff_cmd_hist [10:00] */ 2691 #define CL72_USER_TX_CL72_TX_DEBUG_STATUS_CL72_LD_COEFF_CMD_HIST_MASK 0x07ff 2692 #define CL72_USER_TX_CL72_TX_DEBUG_STATUS_CL72_LD_COEFF_CMD_HIST_ALIGN 0 2693 #define CL72_USER_TX_CL72_TX_DEBUG_STATUS_CL72_LD_COEFF_CMD_HIST_BITS 11 2694 #define CL72_USER_TX_CL72_TX_DEBUG_STATUS_CL72_LD_COEFF_CMD_HIST_SHIFT 0 2695 2696 2697 /**************************************************************************** 2698 * eagle_tsc_tx_pi_blk_TX_PI_COM 2699 */ 2700 /**************************************************************************** 2701 * TX_PI_COM :: CONTROL_0 2702 */ 2703 /* TX_PI_COM :: CONTROL_0 :: reserved0 [15:15] */ 2704 #define TX_PI_COM_CONTROL_0_RESERVED0_MASK 0x8000 2705 #define TX_PI_COM_CONTROL_0_RESERVED0_ALIGN 0 2706 #define TX_PI_COM_CONTROL_0_RESERVED0_BITS 1 2707 #define TX_PI_COM_CONTROL_0_RESERVED0_SHIFT 15 2708 2709 /* TX_PI_COM :: CONTROL_0 :: tx_pi_ext_phase_bwsel_integ [14:12] */ 2710 #define TX_PI_COM_CONTROL_0_TX_PI_EXT_PHASE_BWSEL_INTEG_MASK 0x7000 2711 #define TX_PI_COM_CONTROL_0_TX_PI_EXT_PHASE_BWSEL_INTEG_ALIGN 0 2712 #define TX_PI_COM_CONTROL_0_TX_PI_EXT_PHASE_BWSEL_INTEG_BITS 3 2713 #define TX_PI_COM_CONTROL_0_TX_PI_EXT_PHASE_BWSEL_INTEG_SHIFT 12 2714 2715 /* TX_PI_COM :: CONTROL_0 :: tx_pi_second_order_bwsel_integ [11:10] */ 2716 #define TX_PI_COM_CONTROL_0_TX_PI_SECOND_ORDER_BWSEL_INTEG_MASK 0x0c00 2717 #define TX_PI_COM_CONTROL_0_TX_PI_SECOND_ORDER_BWSEL_INTEG_ALIGN 0 2718 #define TX_PI_COM_CONTROL_0_TX_PI_SECOND_ORDER_BWSEL_INTEG_BITS 2 2719 #define TX_PI_COM_CONTROL_0_TX_PI_SECOND_ORDER_BWSEL_INTEG_SHIFT 10 2720 2721 /* TX_PI_COM :: CONTROL_0 :: tx_pi_first_order_bwsel_integ [09:08] */ 2722 #define TX_PI_COM_CONTROL_0_TX_PI_FIRST_ORDER_BWSEL_INTEG_MASK 0x0300 2723 #define TX_PI_COM_CONTROL_0_TX_PI_FIRST_ORDER_BWSEL_INTEG_ALIGN 0 2724 #define TX_PI_COM_CONTROL_0_TX_PI_FIRST_ORDER_BWSEL_INTEG_BITS 2 2725 #define TX_PI_COM_CONTROL_0_TX_PI_FIRST_ORDER_BWSEL_INTEG_SHIFT 8 2726 2727 /* TX_PI_COM :: CONTROL_0 :: tx_pi_second_order_loop_en [07:07] */ 2728 #define TX_PI_COM_CONTROL_0_TX_PI_SECOND_ORDER_LOOP_EN_MASK 0x0080 2729 #define TX_PI_COM_CONTROL_0_TX_PI_SECOND_ORDER_LOOP_EN_ALIGN 0 2730 #define TX_PI_COM_CONTROL_0_TX_PI_SECOND_ORDER_LOOP_EN_BITS 1 2731 #define TX_PI_COM_CONTROL_0_TX_PI_SECOND_ORDER_LOOP_EN_SHIFT 7 2732 2733 /* TX_PI_COM :: CONTROL_0 :: tx_pi_jit_ssc_freq_mode [06:06] */ 2734 #define TX_PI_COM_CONTROL_0_TX_PI_JIT_SSC_FREQ_MODE_MASK 0x0040 2735 #define TX_PI_COM_CONTROL_0_TX_PI_JIT_SSC_FREQ_MODE_ALIGN 0 2736 #define TX_PI_COM_CONTROL_0_TX_PI_JIT_SSC_FREQ_MODE_BITS 1 2737 #define TX_PI_COM_CONTROL_0_TX_PI_JIT_SSC_FREQ_MODE_SHIFT 6 2738 2739 /* TX_PI_COM :: CONTROL_0 :: tx_pi_ssc_gen_en [05:05] */ 2740 #define TX_PI_COM_CONTROL_0_TX_PI_SSC_GEN_EN_MASK 0x0020 2741 #define TX_PI_COM_CONTROL_0_TX_PI_SSC_GEN_EN_ALIGN 0 2742 #define TX_PI_COM_CONTROL_0_TX_PI_SSC_GEN_EN_BITS 1 2743 #define TX_PI_COM_CONTROL_0_TX_PI_SSC_GEN_EN_SHIFT 5 2744 2745 /* TX_PI_COM :: CONTROL_0 :: tx_pi_sj_gen_en [04:04] */ 2746 #define TX_PI_COM_CONTROL_0_TX_PI_SJ_GEN_EN_MASK 0x0010 2747 #define TX_PI_COM_CONTROL_0_TX_PI_SJ_GEN_EN_ALIGN 0 2748 #define TX_PI_COM_CONTROL_0_TX_PI_SJ_GEN_EN_BITS 1 2749 #define TX_PI_COM_CONTROL_0_TX_PI_SJ_GEN_EN_SHIFT 4 2750 2751 /* TX_PI_COM :: CONTROL_0 :: tx_pi_freq_override_en [03:03] */ 2752 #define TX_PI_COM_CONTROL_0_TX_PI_FREQ_OVERRIDE_EN_MASK 0x0008 2753 #define TX_PI_COM_CONTROL_0_TX_PI_FREQ_OVERRIDE_EN_ALIGN 0 2754 #define TX_PI_COM_CONTROL_0_TX_PI_FREQ_OVERRIDE_EN_BITS 1 2755 #define TX_PI_COM_CONTROL_0_TX_PI_FREQ_OVERRIDE_EN_SHIFT 3 2756 2757 /* TX_PI_COM :: CONTROL_0 :: tx_pi_ext_ctrl_en [02:02] */ 2758 #define TX_PI_COM_CONTROL_0_TX_PI_EXT_CTRL_EN_MASK 0x0004 2759 #define TX_PI_COM_CONTROL_0_TX_PI_EXT_CTRL_EN_ALIGN 0 2760 #define TX_PI_COM_CONTROL_0_TX_PI_EXT_CTRL_EN_BITS 1 2761 #define TX_PI_COM_CONTROL_0_TX_PI_EXT_CTRL_EN_SHIFT 2 2762 2763 /* TX_PI_COM :: CONTROL_0 :: tx_pi_jitter_filter_en [01:01] */ 2764 #define TX_PI_COM_CONTROL_0_TX_PI_JITTER_FILTER_EN_MASK 0x0002 2765 #define TX_PI_COM_CONTROL_0_TX_PI_JITTER_FILTER_EN_ALIGN 0 2766 #define TX_PI_COM_CONTROL_0_TX_PI_JITTER_FILTER_EN_BITS 1 2767 #define TX_PI_COM_CONTROL_0_TX_PI_JITTER_FILTER_EN_SHIFT 1 2768 2769 /* TX_PI_COM :: CONTROL_0 :: tx_pi_en [00:00] */ 2770 #define TX_PI_COM_CONTROL_0_TX_PI_EN_MASK 0x0001 2771 #define TX_PI_COM_CONTROL_0_TX_PI_EN_ALIGN 0 2772 #define TX_PI_COM_CONTROL_0_TX_PI_EN_BITS 1 2773 #define TX_PI_COM_CONTROL_0_TX_PI_EN_SHIFT 0 2774 2775 2776 /**************************************************************************** 2777 * TX_PI_COM :: CONTROL_1 2778 */ 2779 /* TX_PI_COM :: CONTROL_1 :: reserved0 [15:15] */ 2780 #define TX_PI_COM_CONTROL_1_RESERVED0_MASK 0x8000 2781 #define TX_PI_COM_CONTROL_1_RESERVED0_ALIGN 0 2782 #define TX_PI_COM_CONTROL_1_RESERVED0_BITS 1 2783 #define TX_PI_COM_CONTROL_1_RESERVED0_SHIFT 15 2784 2785 /* TX_PI_COM :: CONTROL_1 :: tx_pi_freq_override_val [14:00] */ 2786 #define TX_PI_COM_CONTROL_1_TX_PI_FREQ_OVERRIDE_VAL_MASK 0x7fff 2787 #define TX_PI_COM_CONTROL_1_TX_PI_FREQ_OVERRIDE_VAL_ALIGN 0 2788 #define TX_PI_COM_CONTROL_1_TX_PI_FREQ_OVERRIDE_VAL_BITS 15 2789 #define TX_PI_COM_CONTROL_1_TX_PI_FREQ_OVERRIDE_VAL_SHIFT 0 2790 2791 2792 /**************************************************************************** 2793 * TX_PI_COM :: CONTROL_2 2794 */ 2795 /* TX_PI_COM :: CONTROL_2 :: reserved0 [15:14] */ 2796 #define TX_PI_COM_CONTROL_2_RESERVED0_MASK 0xc000 2797 #define TX_PI_COM_CONTROL_2_RESERVED0_ALIGN 0 2798 #define TX_PI_COM_CONTROL_2_RESERVED0_BITS 2 2799 #define TX_PI_COM_CONTROL_2_RESERVED0_SHIFT 14 2800 2801 /* TX_PI_COM :: CONTROL_2 :: tx_pi_jit_amp [13:08] */ 2802 #define TX_PI_COM_CONTROL_2_TX_PI_JIT_AMP_MASK 0x3f00 2803 #define TX_PI_COM_CONTROL_2_TX_PI_JIT_AMP_ALIGN 0 2804 #define TX_PI_COM_CONTROL_2_TX_PI_JIT_AMP_BITS 6 2805 #define TX_PI_COM_CONTROL_2_TX_PI_JIT_AMP_SHIFT 8 2806 2807 /* TX_PI_COM :: CONTROL_2 :: reserved1 [07:06] */ 2808 #define TX_PI_COM_CONTROL_2_RESERVED1_MASK 0x00c0 2809 #define TX_PI_COM_CONTROL_2_RESERVED1_ALIGN 0 2810 #define TX_PI_COM_CONTROL_2_RESERVED1_BITS 2 2811 #define TX_PI_COM_CONTROL_2_RESERVED1_SHIFT 6 2812 2813 /* TX_PI_COM :: CONTROL_2 :: tx_pi_jit_freq_idx [05:00] */ 2814 #define TX_PI_COM_CONTROL_2_TX_PI_JIT_FREQ_IDX_MASK 0x003f 2815 #define TX_PI_COM_CONTROL_2_TX_PI_JIT_FREQ_IDX_ALIGN 0 2816 #define TX_PI_COM_CONTROL_2_TX_PI_JIT_FREQ_IDX_BITS 6 2817 #define TX_PI_COM_CONTROL_2_TX_PI_JIT_FREQ_IDX_SHIFT 0 2818 2819 2820 /**************************************************************************** 2821 * TX_PI_COM :: CONTROL_3 2822 */ 2823 /* TX_PI_COM :: CONTROL_3 :: reserved0 [15:12] */ 2824 #define TX_PI_COM_CONTROL_3_RESERVED0_MASK 0xf000 2825 #define TX_PI_COM_CONTROL_3_RESERVED0_ALIGN 0 2826 #define TX_PI_COM_CONTROL_3_RESERVED0_BITS 4 2827 #define TX_PI_COM_CONTROL_3_RESERVED0_SHIFT 12 2828 2829 /* TX_PI_COM :: CONTROL_3 :: tx_pi_phase_step_num [11:08] */ 2830 #define TX_PI_COM_CONTROL_3_TX_PI_PHASE_STEP_NUM_MASK 0x0f00 2831 #define TX_PI_COM_CONTROL_3_TX_PI_PHASE_STEP_NUM_ALIGN 0 2832 #define TX_PI_COM_CONTROL_3_TX_PI_PHASE_STEP_NUM_BITS 4 2833 #define TX_PI_COM_CONTROL_3_TX_PI_PHASE_STEP_NUM_SHIFT 8 2834 2835 /* TX_PI_COM :: CONTROL_3 :: reserved1 [07:05] */ 2836 #define TX_PI_COM_CONTROL_3_RESERVED1_MASK 0x00e0 2837 #define TX_PI_COM_CONTROL_3_RESERVED1_ALIGN 0 2838 #define TX_PI_COM_CONTROL_3_RESERVED1_BITS 3 2839 #define TX_PI_COM_CONTROL_3_RESERVED1_SHIFT 5 2840 2841 /* TX_PI_COM :: CONTROL_3 :: tx_pi_phase_invert [04:04] */ 2842 #define TX_PI_COM_CONTROL_3_TX_PI_PHASE_INVERT_MASK 0x0010 2843 #define TX_PI_COM_CONTROL_3_TX_PI_PHASE_INVERT_ALIGN 0 2844 #define TX_PI_COM_CONTROL_3_TX_PI_PHASE_INVERT_BITS 1 2845 #define TX_PI_COM_CONTROL_3_TX_PI_PHASE_INVERT_SHIFT 4 2846 2847 /* TX_PI_COM :: CONTROL_3 :: reserved2 [03:03] */ 2848 #define TX_PI_COM_CONTROL_3_RESERVED2_MASK 0x0008 2849 #define TX_PI_COM_CONTROL_3_RESERVED2_ALIGN 0 2850 #define TX_PI_COM_CONTROL_3_RESERVED2_BITS 1 2851 #define TX_PI_COM_CONTROL_3_RESERVED2_SHIFT 3 2852 2853 /* TX_PI_COM :: CONTROL_3 :: tx_pi_phase_step_dir [02:02] */ 2854 #define TX_PI_COM_CONTROL_3_TX_PI_PHASE_STEP_DIR_MASK 0x0004 2855 #define TX_PI_COM_CONTROL_3_TX_PI_PHASE_STEP_DIR_ALIGN 0 2856 #define TX_PI_COM_CONTROL_3_TX_PI_PHASE_STEP_DIR_BITS 1 2857 #define TX_PI_COM_CONTROL_3_TX_PI_PHASE_STEP_DIR_SHIFT 2 2858 2859 /* TX_PI_COM :: CONTROL_3 :: tx_pi_phase_strobe [01:01] */ 2860 #define TX_PI_COM_CONTROL_3_TX_PI_PHASE_STROBE_MASK 0x0002 2861 #define TX_PI_COM_CONTROL_3_TX_PI_PHASE_STROBE_ALIGN 0 2862 #define TX_PI_COM_CONTROL_3_TX_PI_PHASE_STROBE_BITS 1 2863 #define TX_PI_COM_CONTROL_3_TX_PI_PHASE_STROBE_SHIFT 1 2864 2865 /* TX_PI_COM :: CONTROL_3 :: tx_pi_phase_override [00:00] */ 2866 #define TX_PI_COM_CONTROL_3_TX_PI_PHASE_OVERRIDE_MASK 0x0001 2867 #define TX_PI_COM_CONTROL_3_TX_PI_PHASE_OVERRIDE_ALIGN 0 2868 #define TX_PI_COM_CONTROL_3_TX_PI_PHASE_OVERRIDE_BITS 1 2869 #define TX_PI_COM_CONTROL_3_TX_PI_PHASE_OVERRIDE_SHIFT 0 2870 2871 2872 /**************************************************************************** 2873 * TX_PI_COM :: CONTROL_4 2874 */ 2875 /* TX_PI_COM :: CONTROL_4 :: reserved0 [15:06] */ 2876 #define TX_PI_COM_CONTROL_4_RESERVED0_MASK 0xffc0 2877 #define TX_PI_COM_CONTROL_4_RESERVED0_ALIGN 0 2878 #define TX_PI_COM_CONTROL_4_RESERVED0_BITS 10 2879 #define TX_PI_COM_CONTROL_4_RESERVED0_SHIFT 6 2880 2881 /* TX_PI_COM :: CONTROL_4 :: tx_pi_frc_phase_step_mux_sel [05:05] */ 2882 #define TX_PI_COM_CONTROL_4_TX_PI_FRC_PHASE_STEP_MUX_SEL_MASK 0x0020 2883 #define TX_PI_COM_CONTROL_4_TX_PI_FRC_PHASE_STEP_MUX_SEL_ALIGN 0 2884 #define TX_PI_COM_CONTROL_4_TX_PI_FRC_PHASE_STEP_MUX_SEL_BITS 1 2885 #define TX_PI_COM_CONTROL_4_TX_PI_FRC_PHASE_STEP_MUX_SEL_SHIFT 5 2886 2887 /* TX_PI_COM :: CONTROL_4 :: tx_pi_rmt_lpbk_bypass_flt [04:04] */ 2888 #define TX_PI_COM_CONTROL_4_TX_PI_RMT_LPBK_BYPASS_FLT_MASK 0x0010 2889 #define TX_PI_COM_CONTROL_4_TX_PI_RMT_LPBK_BYPASS_FLT_ALIGN 0 2890 #define TX_PI_COM_CONTROL_4_TX_PI_RMT_LPBK_BYPASS_FLT_BITS 1 2891 #define TX_PI_COM_CONTROL_4_TX_PI_RMT_LPBK_BYPASS_FLT_SHIFT 4 2892 2893 /* TX_PI_COM :: CONTROL_4 :: tx_pi_reset_code_dbg [03:03] */ 2894 #define TX_PI_COM_CONTROL_4_TX_PI_RESET_CODE_DBG_MASK 0x0008 2895 #define TX_PI_COM_CONTROL_4_TX_PI_RESET_CODE_DBG_ALIGN 0 2896 #define TX_PI_COM_CONTROL_4_TX_PI_RESET_CODE_DBG_BITS 1 2897 #define TX_PI_COM_CONTROL_4_TX_PI_RESET_CODE_DBG_SHIFT 3 2898 2899 /* TX_PI_COM :: CONTROL_4 :: tx_pi_frz_mode [02:02] */ 2900 #define TX_PI_COM_CONTROL_4_TX_PI_FRZ_MODE_MASK 0x0004 2901 #define TX_PI_COM_CONTROL_4_TX_PI_FRZ_MODE_ALIGN 0 2902 #define TX_PI_COM_CONTROL_4_TX_PI_FRZ_MODE_BITS 1 2903 #define TX_PI_COM_CONTROL_4_TX_PI_FRZ_MODE_SHIFT 2 2904 2905 /* TX_PI_COM :: CONTROL_4 :: tx_pi_frz_frc_val [01:01] */ 2906 #define TX_PI_COM_CONTROL_4_TX_PI_FRZ_FRC_VAL_MASK 0x0002 2907 #define TX_PI_COM_CONTROL_4_TX_PI_FRZ_FRC_VAL_ALIGN 0 2908 #define TX_PI_COM_CONTROL_4_TX_PI_FRZ_FRC_VAL_BITS 1 2909 #define TX_PI_COM_CONTROL_4_TX_PI_FRZ_FRC_VAL_SHIFT 1 2910 2911 /* TX_PI_COM :: CONTROL_4 :: tx_pi_frz_frc [00:00] */ 2912 #define TX_PI_COM_CONTROL_4_TX_PI_FRZ_FRC_MASK 0x0001 2913 #define TX_PI_COM_CONTROL_4_TX_PI_FRZ_FRC_ALIGN 0 2914 #define TX_PI_COM_CONTROL_4_TX_PI_FRZ_FRC_BITS 1 2915 #define TX_PI_COM_CONTROL_4_TX_PI_FRZ_FRC_SHIFT 0 2916 2917 2918 /**************************************************************************** 2919 * TX_PI_COM :: CONTROL_6 2920 */ 2921 /* TX_PI_COM :: CONTROL_6 :: reserved0 [15:09] */ 2922 #define TX_PI_COM_CONTROL_6_RESERVED0_MASK 0xfe00 2923 #define TX_PI_COM_CONTROL_6_RESERVED0_ALIGN 0 2924 #define TX_PI_COM_CONTROL_6_RESERVED0_BITS 7 2925 #define TX_PI_COM_CONTROL_6_RESERVED0_SHIFT 9 2926 2927 /* TX_PI_COM :: CONTROL_6 :: tx_pi_lane_sel_frc [08:08] */ 2928 #define TX_PI_COM_CONTROL_6_TX_PI_LANE_SEL_FRC_MASK 0x0100 2929 #define TX_PI_COM_CONTROL_6_TX_PI_LANE_SEL_FRC_ALIGN 0 2930 #define TX_PI_COM_CONTROL_6_TX_PI_LANE_SEL_FRC_BITS 1 2931 #define TX_PI_COM_CONTROL_6_TX_PI_LANE_SEL_FRC_SHIFT 8 2932 2933 /* TX_PI_COM :: CONTROL_6 :: reserved1 [07:05] */ 2934 #define TX_PI_COM_CONTROL_6_RESERVED1_MASK 0x00e0 2935 #define TX_PI_COM_CONTROL_6_RESERVED1_ALIGN 0 2936 #define TX_PI_COM_CONTROL_6_RESERVED1_BITS 3 2937 #define TX_PI_COM_CONTROL_6_RESERVED1_SHIFT 5 2938 2939 /* TX_PI_COM :: CONTROL_6 :: tx_pi_lane_sel_frc_val [04:00] */ 2940 #define TX_PI_COM_CONTROL_6_TX_PI_LANE_SEL_FRC_VAL_MASK 0x001f 2941 #define TX_PI_COM_CONTROL_6_TX_PI_LANE_SEL_FRC_VAL_ALIGN 0 2942 #define TX_PI_COM_CONTROL_6_TX_PI_LANE_SEL_FRC_VAL_BITS 5 2943 #define TX_PI_COM_CONTROL_6_TX_PI_LANE_SEL_FRC_VAL_SHIFT 0 2944 2945 2946 /**************************************************************************** 2947 * TX_PI_COM :: STATUS_0 2948 */ 2949 /* TX_PI_COM :: STATUS_0 :: reserved0 [15:07] */ 2950 #define TX_PI_COM_STATUS_0_RESERVED0_MASK 0xff80 2951 #define TX_PI_COM_STATUS_0_RESERVED0_ALIGN 0 2952 #define TX_PI_COM_STATUS_0_RESERVED0_BITS 9 2953 #define TX_PI_COM_STATUS_0_RESERVED0_SHIFT 7 2954 2955 /* TX_PI_COM :: STATUS_0 :: tx_pi_phase_cntr [06:00] */ 2956 #define TX_PI_COM_STATUS_0_TX_PI_PHASE_CNTR_MASK 0x007f 2957 #define TX_PI_COM_STATUS_0_TX_PI_PHASE_CNTR_ALIGN 0 2958 #define TX_PI_COM_STATUS_0_TX_PI_PHASE_CNTR_BITS 7 2959 #define TX_PI_COM_STATUS_0_TX_PI_PHASE_CNTR_SHIFT 0 2960 2961 2962 /**************************************************************************** 2963 * TX_PI_COM :: STATUS_1 2964 */ 2965 /* TX_PI_COM :: STATUS_1 :: reserved0 [15:14] */ 2966 #define TX_PI_COM_STATUS_1_RESERVED0_MASK 0xc000 2967 #define TX_PI_COM_STATUS_1_RESERVED0_ALIGN 0 2968 #define TX_PI_COM_STATUS_1_RESERVED0_BITS 2 2969 #define TX_PI_COM_STATUS_1_RESERVED0_SHIFT 14 2970 2971 /* TX_PI_COM :: STATUS_1 :: tx_pi_integ1_reg [13:00] */ 2972 #define TX_PI_COM_STATUS_1_TX_PI_INTEG1_REG_MASK 0x3fff 2973 #define TX_PI_COM_STATUS_1_TX_PI_INTEG1_REG_ALIGN 0 2974 #define TX_PI_COM_STATUS_1_TX_PI_INTEG1_REG_BITS 14 2975 #define TX_PI_COM_STATUS_1_TX_PI_INTEG1_REG_SHIFT 0 2976 2977 2978 /**************************************************************************** 2979 * TX_PI_COM :: STATUS_2 2980 */ 2981 /* TX_PI_COM :: STATUS_2 :: reserved0 [15:15] */ 2982 #define TX_PI_COM_STATUS_2_RESERVED0_MASK 0x8000 2983 #define TX_PI_COM_STATUS_2_RESERVED0_ALIGN 0 2984 #define TX_PI_COM_STATUS_2_RESERVED0_BITS 1 2985 #define TX_PI_COM_STATUS_2_RESERVED0_SHIFT 15 2986 2987 /* TX_PI_COM :: STATUS_2 :: tx_pi_integ2_reg [14:00] */ 2988 #define TX_PI_COM_STATUS_2_TX_PI_INTEG2_REG_MASK 0x7fff 2989 #define TX_PI_COM_STATUS_2_TX_PI_INTEG2_REG_ALIGN 0 2990 #define TX_PI_COM_STATUS_2_TX_PI_INTEG2_REG_BITS 15 2991 #define TX_PI_COM_STATUS_2_TX_PI_INTEG2_REG_SHIFT 0 2992 2993 2994 /**************************************************************************** 2995 * TX_PI_COM :: STATUS_3 2996 */ 2997 /* TX_PI_COM :: STATUS_3 :: reserved0 [15:06] */ 2998 #define TX_PI_COM_STATUS_3_RESERVED0_MASK 0xffc0 2999 #define TX_PI_COM_STATUS_3_RESERVED0_ALIGN 0 3000 #define TX_PI_COM_STATUS_3_RESERVED0_BITS 10 3001 #define TX_PI_COM_STATUS_3_RESERVED0_SHIFT 6 3002 3003 /* TX_PI_COM :: STATUS_3 :: tx_pi_phase_err [05:00] */ 3004 #define TX_PI_COM_STATUS_3_TX_PI_PHASE_ERR_MASK 0x003f 3005 #define TX_PI_COM_STATUS_3_TX_PI_PHASE_ERR_ALIGN 0 3006 #define TX_PI_COM_STATUS_3_TX_PI_PHASE_ERR_BITS 6 3007 #define TX_PI_COM_STATUS_3_TX_PI_PHASE_ERR_SHIFT 0 3008 3009 3010 /**************************************************************************** 3011 * eagle_tsc_ckrst_ctrl_blk_CKRST_CTRL 3012 */ 3013 /**************************************************************************** 3014 * CKRST_CTRL :: OSR_MODE_CONTROL 3015 */ 3016 /* CKRST_CTRL :: OSR_MODE_CONTROL :: osr_mode_frc [15:15] */ 3017 #define CKRST_CTRL_OSR_MODE_CONTROL_OSR_MODE_FRC_MASK 0x8000 3018 #define CKRST_CTRL_OSR_MODE_CONTROL_OSR_MODE_FRC_ALIGN 0 3019 #define CKRST_CTRL_OSR_MODE_CONTROL_OSR_MODE_FRC_BITS 1 3020 #define CKRST_CTRL_OSR_MODE_CONTROL_OSR_MODE_FRC_SHIFT 15 3021 3022 /* CKRST_CTRL :: OSR_MODE_CONTROL :: reserved0 [14:04] */ 3023 #define CKRST_CTRL_OSR_MODE_CONTROL_RESERVED0_MASK 0x7ff0 3024 #define CKRST_CTRL_OSR_MODE_CONTROL_RESERVED0_ALIGN 0 3025 #define CKRST_CTRL_OSR_MODE_CONTROL_RESERVED0_BITS 11 3026 #define CKRST_CTRL_OSR_MODE_CONTROL_RESERVED0_SHIFT 4 3027 3028 /* CKRST_CTRL :: OSR_MODE_CONTROL :: osr_mode_frc_val [03:00] */ 3029 #define CKRST_CTRL_OSR_MODE_CONTROL_OSR_MODE_FRC_VAL_MASK 0x000f 3030 #define CKRST_CTRL_OSR_MODE_CONTROL_OSR_MODE_FRC_VAL_ALIGN 0 3031 #define CKRST_CTRL_OSR_MODE_CONTROL_OSR_MODE_FRC_VAL_BITS 4 3032 #define CKRST_CTRL_OSR_MODE_CONTROL_OSR_MODE_FRC_VAL_SHIFT 0 3033 3034 3035 /**************************************************************************** 3036 * CKRST_CTRL :: LANE_CLK_RESET_N_POWERDOWN_CONTROL 3037 */ 3038 /* CKRST_CTRL :: LANE_CLK_RESET_N_POWERDOWN_CONTROL :: reserved0 [15:05] */ 3039 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_RESERVED0_MASK 0xffe0 3040 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_RESERVED0_ALIGN 0 3041 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_RESERVED0_BITS 11 3042 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_RESERVED0_SHIFT 5 3043 3044 /* CKRST_CTRL :: LANE_CLK_RESET_N_POWERDOWN_CONTROL :: afe_sigdet_pwrdn [04:04] */ 3045 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_AFE_SIGDET_PWRDN_MASK 0x0010 3046 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_AFE_SIGDET_PWRDN_ALIGN 0 3047 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_AFE_SIGDET_PWRDN_BITS 1 3048 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_AFE_SIGDET_PWRDN_SHIFT 4 3049 3050 /* CKRST_CTRL :: LANE_CLK_RESET_N_POWERDOWN_CONTROL :: ln_tx_s_pwrdn [03:03] */ 3051 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_LN_TX_S_PWRDN_MASK 0x0008 3052 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_LN_TX_S_PWRDN_ALIGN 0 3053 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_LN_TX_S_PWRDN_BITS 1 3054 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_LN_TX_S_PWRDN_SHIFT 3 3055 3056 /* CKRST_CTRL :: LANE_CLK_RESET_N_POWERDOWN_CONTROL :: ln_rx_s_pwrdn [02:02] */ 3057 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_LN_RX_S_PWRDN_MASK 0x0004 3058 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_LN_RX_S_PWRDN_ALIGN 0 3059 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_LN_RX_S_PWRDN_BITS 1 3060 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_LN_RX_S_PWRDN_SHIFT 2 3061 3062 /* CKRST_CTRL :: LANE_CLK_RESET_N_POWERDOWN_CONTROL :: ln_dp_s_rstb [01:01] */ 3063 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_LN_DP_S_RSTB_MASK 0x0002 3064 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_LN_DP_S_RSTB_ALIGN 0 3065 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_LN_DP_S_RSTB_BITS 1 3066 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_LN_DP_S_RSTB_SHIFT 1 3067 3068 /* CKRST_CTRL :: LANE_CLK_RESET_N_POWERDOWN_CONTROL :: reserved1 [00:00] */ 3069 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_RESERVED1_MASK 0x0001 3070 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_RESERVED1_ALIGN 0 3071 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_RESERVED1_BITS 1 3072 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_RESERVED1_SHIFT 0 3073 3074 3075 /**************************************************************************** 3076 * CKRST_CTRL :: LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL 3077 */ 3078 /* CKRST_CTRL :: LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL :: reserved0 [15:08] */ 3079 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_RESERVED0_MASK 0xff00 3080 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_RESERVED0_ALIGN 0 3081 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_RESERVED0_BITS 8 3082 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_RESERVED0_SHIFT 8 3083 3084 /* CKRST_CTRL :: LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL :: afe_tx_reset_frc_val [07:07] */ 3085 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_TX_RESET_FRC_VAL_MASK 0x0080 3086 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_TX_RESET_FRC_VAL_ALIGN 0 3087 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_TX_RESET_FRC_VAL_BITS 1 3088 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_TX_RESET_FRC_VAL_SHIFT 7 3089 3090 /* CKRST_CTRL :: LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL :: afe_tx_reset_frc [06:06] */ 3091 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_TX_RESET_FRC_MASK 0x0040 3092 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_TX_RESET_FRC_ALIGN 0 3093 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_TX_RESET_FRC_BITS 1 3094 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_TX_RESET_FRC_SHIFT 6 3095 3096 /* CKRST_CTRL :: LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL :: afe_tx_pwrdn_frc_val [05:05] */ 3097 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_TX_PWRDN_FRC_VAL_MASK 0x0020 3098 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_TX_PWRDN_FRC_VAL_ALIGN 0 3099 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_TX_PWRDN_FRC_VAL_BITS 1 3100 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_TX_PWRDN_FRC_VAL_SHIFT 5 3101 3102 /* CKRST_CTRL :: LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL :: afe_tx_pwrdn_frc [04:04] */ 3103 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_TX_PWRDN_FRC_MASK 0x0010 3104 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_TX_PWRDN_FRC_ALIGN 0 3105 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_TX_PWRDN_FRC_BITS 1 3106 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_TX_PWRDN_FRC_SHIFT 4 3107 3108 /* CKRST_CTRL :: LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL :: afe_rx_reset_frc_val [03:03] */ 3109 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_RX_RESET_FRC_VAL_MASK 0x0008 3110 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_RX_RESET_FRC_VAL_ALIGN 0 3111 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_RX_RESET_FRC_VAL_BITS 1 3112 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_RX_RESET_FRC_VAL_SHIFT 3 3113 3114 /* CKRST_CTRL :: LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL :: afe_rx_reset_frc [02:02] */ 3115 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_RX_RESET_FRC_MASK 0x0004 3116 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_RX_RESET_FRC_ALIGN 0 3117 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_RX_RESET_FRC_BITS 1 3118 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_RX_RESET_FRC_SHIFT 2 3119 3120 /* CKRST_CTRL :: LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL :: afe_rx_pwrdn_frc_val [01:01] */ 3121 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_RX_PWRDN_FRC_VAL_MASK 0x0002 3122 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_RX_PWRDN_FRC_VAL_ALIGN 0 3123 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_RX_PWRDN_FRC_VAL_BITS 1 3124 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_RX_PWRDN_FRC_VAL_SHIFT 1 3125 3126 /* CKRST_CTRL :: LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL :: afe_rx_pwrdn_frc [00:00] */ 3127 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_RX_PWRDN_FRC_MASK 0x0001 3128 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_RX_PWRDN_FRC_ALIGN 0 3129 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_RX_PWRDN_FRC_BITS 1 3130 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_RX_PWRDN_FRC_SHIFT 0 3131 3132 3133 /**************************************************************************** 3134 * CKRST_CTRL :: LANE_RESET_N_PWRDN_PIN_KILL_CONTROL 3135 */ 3136 /* CKRST_CTRL :: LANE_RESET_N_PWRDN_PIN_KILL_CONTROL :: reserved0 [15:04] */ 3137 #define CKRST_CTRL_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL_RESERVED0_MASK 0xfff0 3138 #define CKRST_CTRL_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL_RESERVED0_ALIGN 0 3139 #define CKRST_CTRL_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL_RESERVED0_BITS 12 3140 #define CKRST_CTRL_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL_RESERVED0_SHIFT 4 3141 3142 /* CKRST_CTRL :: LANE_RESET_N_PWRDN_PIN_KILL_CONTROL :: pmd_ln_tx_h_pwrdn_pkill [03:03] */ 3143 #define CKRST_CTRL_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL_PMD_LN_TX_H_PWRDN_PKILL_MASK 0x0008 3144 #define CKRST_CTRL_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL_PMD_LN_TX_H_PWRDN_PKILL_ALIGN 0 3145 #define CKRST_CTRL_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL_PMD_LN_TX_H_PWRDN_PKILL_BITS 1 3146 #define CKRST_CTRL_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL_PMD_LN_TX_H_PWRDN_PKILL_SHIFT 3 3147 3148 /* CKRST_CTRL :: LANE_RESET_N_PWRDN_PIN_KILL_CONTROL :: pmd_ln_rx_h_pwrdn_pkill [02:02] */ 3149 #define CKRST_CTRL_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL_PMD_LN_RX_H_PWRDN_PKILL_MASK 0x0004 3150 #define CKRST_CTRL_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL_PMD_LN_RX_H_PWRDN_PKILL_ALIGN 0 3151 #define CKRST_CTRL_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL_PMD_LN_RX_H_PWRDN_PKILL_BITS 1 3152 #define CKRST_CTRL_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL_PMD_LN_RX_H_PWRDN_PKILL_SHIFT 2 3153 3154 /* CKRST_CTRL :: LANE_RESET_N_PWRDN_PIN_KILL_CONTROL :: pmd_ln_dp_h_rstb_pkill [01:01] */ 3155 #define CKRST_CTRL_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL_PMD_LN_DP_H_RSTB_PKILL_MASK 0x0002 3156 #define CKRST_CTRL_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL_PMD_LN_DP_H_RSTB_PKILL_ALIGN 0 3157 #define CKRST_CTRL_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL_PMD_LN_DP_H_RSTB_PKILL_BITS 1 3158 #define CKRST_CTRL_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL_PMD_LN_DP_H_RSTB_PKILL_SHIFT 1 3159 3160 /* CKRST_CTRL :: LANE_RESET_N_PWRDN_PIN_KILL_CONTROL :: pmd_ln_h_rstb_pkill [00:00] */ 3161 #define CKRST_CTRL_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL_PMD_LN_H_RSTB_PKILL_MASK 0x0001 3162 #define CKRST_CTRL_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL_PMD_LN_H_RSTB_PKILL_ALIGN 0 3163 #define CKRST_CTRL_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL_PMD_LN_H_RSTB_PKILL_BITS 1 3164 #define CKRST_CTRL_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL_PMD_LN_H_RSTB_PKILL_SHIFT 0 3165 3166 3167 /**************************************************************************** 3168 * CKRST_CTRL :: LANE_DEBUG_RESET_CONTROL 3169 */ 3170 /* CKRST_CTRL :: LANE_DEBUG_RESET_CONTROL :: reserved0 [15:10] */ 3171 #define CKRST_CTRL_LANE_DEBUG_RESET_CONTROL_RESERVED0_MASK 0xfc00 3172 #define CKRST_CTRL_LANE_DEBUG_RESET_CONTROL_RESERVED0_ALIGN 0 3173 #define CKRST_CTRL_LANE_DEBUG_RESET_CONTROL_RESERVED0_BITS 6 3174 #define CKRST_CTRL_LANE_DEBUG_RESET_CONTROL_RESERVED0_SHIFT 10 3175 3176 /* CKRST_CTRL :: LANE_DEBUG_RESET_CONTROL :: ln_tx_dp_s_rstb [09:09] */ 3177 #define CKRST_CTRL_LANE_DEBUG_RESET_CONTROL_LN_TX_DP_S_RSTB_MASK 0x0200 3178 #define CKRST_CTRL_LANE_DEBUG_RESET_CONTROL_LN_TX_DP_S_RSTB_ALIGN 0 3179 #define CKRST_CTRL_LANE_DEBUG_RESET_CONTROL_LN_TX_DP_S_RSTB_BITS 1 3180 #define CKRST_CTRL_LANE_DEBUG_RESET_CONTROL_LN_TX_DP_S_RSTB_SHIFT 9 3181 3182 /* CKRST_CTRL :: LANE_DEBUG_RESET_CONTROL :: ln_tx_s_rstb [08:08] */ 3183 #define CKRST_CTRL_LANE_DEBUG_RESET_CONTROL_LN_TX_S_RSTB_MASK 0x0100 3184 #define CKRST_CTRL_LANE_DEBUG_RESET_CONTROL_LN_TX_S_RSTB_ALIGN 0 3185 #define CKRST_CTRL_LANE_DEBUG_RESET_CONTROL_LN_TX_S_RSTB_BITS 1 3186 #define CKRST_CTRL_LANE_DEBUG_RESET_CONTROL_LN_TX_S_RSTB_SHIFT 8 3187 3188 /* CKRST_CTRL :: LANE_DEBUG_RESET_CONTROL :: reserved1 [07:03] */ 3189 #define CKRST_CTRL_LANE_DEBUG_RESET_CONTROL_RESERVED1_MASK 0x00f8 3190 #define CKRST_CTRL_LANE_DEBUG_RESET_CONTROL_RESERVED1_ALIGN 0 3191 #define CKRST_CTRL_LANE_DEBUG_RESET_CONTROL_RESERVED1_BITS 5 3192 #define CKRST_CTRL_LANE_DEBUG_RESET_CONTROL_RESERVED1_SHIFT 3 3193 3194 /* CKRST_CTRL :: LANE_DEBUG_RESET_CONTROL :: sigdet_dp_rstb_en [02:02] */ 3195 #define CKRST_CTRL_LANE_DEBUG_RESET_CONTROL_SIGDET_DP_RSTB_EN_MASK 0x0004 3196 #define CKRST_CTRL_LANE_DEBUG_RESET_CONTROL_SIGDET_DP_RSTB_EN_ALIGN 0 3197 #define CKRST_CTRL_LANE_DEBUG_RESET_CONTROL_SIGDET_DP_RSTB_EN_BITS 1 3198 #define CKRST_CTRL_LANE_DEBUG_RESET_CONTROL_SIGDET_DP_RSTB_EN_SHIFT 2 3199 3200 /* CKRST_CTRL :: LANE_DEBUG_RESET_CONTROL :: ln_rx_dp_s_rstb [01:01] */ 3201 #define CKRST_CTRL_LANE_DEBUG_RESET_CONTROL_LN_RX_DP_S_RSTB_MASK 0x0002 3202 #define CKRST_CTRL_LANE_DEBUG_RESET_CONTROL_LN_RX_DP_S_RSTB_ALIGN 0 3203 #define CKRST_CTRL_LANE_DEBUG_RESET_CONTROL_LN_RX_DP_S_RSTB_BITS 1 3204 #define CKRST_CTRL_LANE_DEBUG_RESET_CONTROL_LN_RX_DP_S_RSTB_SHIFT 1 3205 3206 /* CKRST_CTRL :: LANE_DEBUG_RESET_CONTROL :: ln_rx_s_rstb [00:00] */ 3207 #define CKRST_CTRL_LANE_DEBUG_RESET_CONTROL_LN_RX_S_RSTB_MASK 0x0001 3208 #define CKRST_CTRL_LANE_DEBUG_RESET_CONTROL_LN_RX_S_RSTB_ALIGN 0 3209 #define CKRST_CTRL_LANE_DEBUG_RESET_CONTROL_LN_RX_S_RSTB_BITS 1 3210 #define CKRST_CTRL_LANE_DEBUG_RESET_CONTROL_LN_RX_S_RSTB_SHIFT 0 3211 3212 3213 /**************************************************************************** 3214 * CKRST_CTRL :: UC_ACK_LANE_CONTROL 3215 */ 3216 /* CKRST_CTRL :: UC_ACK_LANE_CONTROL :: reserved0 [15:02] */ 3217 #define CKRST_CTRL_UC_ACK_LANE_CONTROL_RESERVED0_MASK 0xfffc 3218 #define CKRST_CTRL_UC_ACK_LANE_CONTROL_RESERVED0_ALIGN 0 3219 #define CKRST_CTRL_UC_ACK_LANE_CONTROL_RESERVED0_BITS 14 3220 #define CKRST_CTRL_UC_ACK_LANE_CONTROL_RESERVED0_SHIFT 2 3221 3222 /* CKRST_CTRL :: UC_ACK_LANE_CONTROL :: uc_ack_lane_dp_reset [01:01] */ 3223 #define CKRST_CTRL_UC_ACK_LANE_CONTROL_UC_ACK_LANE_DP_RESET_MASK 0x0002 3224 #define CKRST_CTRL_UC_ACK_LANE_CONTROL_UC_ACK_LANE_DP_RESET_ALIGN 0 3225 #define CKRST_CTRL_UC_ACK_LANE_CONTROL_UC_ACK_LANE_DP_RESET_BITS 1 3226 #define CKRST_CTRL_UC_ACK_LANE_CONTROL_UC_ACK_LANE_DP_RESET_SHIFT 1 3227 3228 /* CKRST_CTRL :: UC_ACK_LANE_CONTROL :: uc_ack_lane_cfg_done [00:00] */ 3229 #define CKRST_CTRL_UC_ACK_LANE_CONTROL_UC_ACK_LANE_CFG_DONE_MASK 0x0001 3230 #define CKRST_CTRL_UC_ACK_LANE_CONTROL_UC_ACK_LANE_CFG_DONE_ALIGN 0 3231 #define CKRST_CTRL_UC_ACK_LANE_CONTROL_UC_ACK_LANE_CFG_DONE_BITS 1 3232 #define CKRST_CTRL_UC_ACK_LANE_CONTROL_UC_ACK_LANE_CFG_DONE_SHIFT 0 3233 3234 3235 /**************************************************************************** 3236 * CKRST_CTRL :: LANE_REG_RESET_OCCURRED_CONTROL 3237 */ 3238 /* CKRST_CTRL :: LANE_REG_RESET_OCCURRED_CONTROL :: reserved0 [15:01] */ 3239 #define CKRST_CTRL_LANE_REG_RESET_OCCURRED_CONTROL_RESERVED0_MASK 0xfffe 3240 #define CKRST_CTRL_LANE_REG_RESET_OCCURRED_CONTROL_RESERVED0_ALIGN 0 3241 #define CKRST_CTRL_LANE_REG_RESET_OCCURRED_CONTROL_RESERVED0_BITS 15 3242 #define CKRST_CTRL_LANE_REG_RESET_OCCURRED_CONTROL_RESERVED0_SHIFT 1 3243 3244 /* CKRST_CTRL :: LANE_REG_RESET_OCCURRED_CONTROL :: lane_reg_reset_occurred [00:00] */ 3245 #define CKRST_CTRL_LANE_REG_RESET_OCCURRED_CONTROL_LANE_REG_RESET_OCCURRED_MASK 0x0001 3246 #define CKRST_CTRL_LANE_REG_RESET_OCCURRED_CONTROL_LANE_REG_RESET_OCCURRED_ALIGN 0 3247 #define CKRST_CTRL_LANE_REG_RESET_OCCURRED_CONTROL_LANE_REG_RESET_OCCURRED_BITS 1 3248 #define CKRST_CTRL_LANE_REG_RESET_OCCURRED_CONTROL_LANE_REG_RESET_OCCURRED_SHIFT 0 3249 3250 3251 /**************************************************************************** 3252 * CKRST_CTRL :: CLOCK_N_RESET_DEBUG_CONTROL 3253 */ 3254 /* CKRST_CTRL :: CLOCK_N_RESET_DEBUG_CONTROL :: reserved0 [15:05] */ 3255 #define CKRST_CTRL_CLOCK_N_RESET_DEBUG_CONTROL_RESERVED0_MASK 0xffe0 3256 #define CKRST_CTRL_CLOCK_N_RESET_DEBUG_CONTROL_RESERVED0_ALIGN 0 3257 #define CKRST_CTRL_CLOCK_N_RESET_DEBUG_CONTROL_RESERVED0_BITS 11 3258 #define CKRST_CTRL_CLOCK_N_RESET_DEBUG_CONTROL_RESERVED0_SHIFT 5 3259 3260 /* CKRST_CTRL :: CLOCK_N_RESET_DEBUG_CONTROL :: pmd_rx_clk_vld_frc_val [04:04] */ 3261 #define CKRST_CTRL_CLOCK_N_RESET_DEBUG_CONTROL_PMD_RX_CLK_VLD_FRC_VAL_MASK 0x0010 3262 #define CKRST_CTRL_CLOCK_N_RESET_DEBUG_CONTROL_PMD_RX_CLK_VLD_FRC_VAL_ALIGN 0 3263 #define CKRST_CTRL_CLOCK_N_RESET_DEBUG_CONTROL_PMD_RX_CLK_VLD_FRC_VAL_BITS 1 3264 #define CKRST_CTRL_CLOCK_N_RESET_DEBUG_CONTROL_PMD_RX_CLK_VLD_FRC_VAL_SHIFT 4 3265 3266 /* CKRST_CTRL :: CLOCK_N_RESET_DEBUG_CONTROL :: pmd_rx_clk_vld_frc [03:03] */ 3267 #define CKRST_CTRL_CLOCK_N_RESET_DEBUG_CONTROL_PMD_RX_CLK_VLD_FRC_MASK 0x0008 3268 #define CKRST_CTRL_CLOCK_N_RESET_DEBUG_CONTROL_PMD_RX_CLK_VLD_FRC_ALIGN 0 3269 #define CKRST_CTRL_CLOCK_N_RESET_DEBUG_CONTROL_PMD_RX_CLK_VLD_FRC_BITS 1 3270 #define CKRST_CTRL_CLOCK_N_RESET_DEBUG_CONTROL_PMD_RX_CLK_VLD_FRC_SHIFT 3 3271 3272 /* CKRST_CTRL :: CLOCK_N_RESET_DEBUG_CONTROL :: ln_rx_s_comclk_frc_on [02:02] */ 3273 #define CKRST_CTRL_CLOCK_N_RESET_DEBUG_CONTROL_LN_RX_S_COMCLK_FRC_ON_MASK 0x0004 3274 #define CKRST_CTRL_CLOCK_N_RESET_DEBUG_CONTROL_LN_RX_S_COMCLK_FRC_ON_ALIGN 0 3275 #define CKRST_CTRL_CLOCK_N_RESET_DEBUG_CONTROL_LN_RX_S_COMCLK_FRC_ON_BITS 1 3276 #define CKRST_CTRL_CLOCK_N_RESET_DEBUG_CONTROL_LN_RX_S_COMCLK_FRC_ON_SHIFT 2 3277 3278 /* CKRST_CTRL :: CLOCK_N_RESET_DEBUG_CONTROL :: ln_rx_s_comclk_sel [01:01] */ 3279 #define CKRST_CTRL_CLOCK_N_RESET_DEBUG_CONTROL_LN_RX_S_COMCLK_SEL_MASK 0x0002 3280 #define CKRST_CTRL_CLOCK_N_RESET_DEBUG_CONTROL_LN_RX_S_COMCLK_SEL_ALIGN 0 3281 #define CKRST_CTRL_CLOCK_N_RESET_DEBUG_CONTROL_LN_RX_S_COMCLK_SEL_BITS 1 3282 #define CKRST_CTRL_CLOCK_N_RESET_DEBUG_CONTROL_LN_RX_S_COMCLK_SEL_SHIFT 1 3283 3284 /* CKRST_CTRL :: CLOCK_N_RESET_DEBUG_CONTROL :: ln_rx_s_clkgate_frc_on [00:00] */ 3285 #define CKRST_CTRL_CLOCK_N_RESET_DEBUG_CONTROL_LN_RX_S_CLKGATE_FRC_ON_MASK 0x0001 3286 #define CKRST_CTRL_CLOCK_N_RESET_DEBUG_CONTROL_LN_RX_S_CLKGATE_FRC_ON_ALIGN 0 3287 #define CKRST_CTRL_CLOCK_N_RESET_DEBUG_CONTROL_LN_RX_S_CLKGATE_FRC_ON_BITS 1 3288 #define CKRST_CTRL_CLOCK_N_RESET_DEBUG_CONTROL_LN_RX_S_CLKGATE_FRC_ON_SHIFT 0 3289 3290 3291 /**************************************************************************** 3292 * CKRST_CTRL :: PMD_LANE_MODE_STATUS 3293 */ 3294 /* CKRST_CTRL :: PMD_LANE_MODE_STATUS :: pmd_lane_mode [15:00] */ 3295 #define CKRST_CTRL_PMD_LANE_MODE_STATUS_PMD_LANE_MODE_MASK 0xffff 3296 #define CKRST_CTRL_PMD_LANE_MODE_STATUS_PMD_LANE_MODE_ALIGN 0 3297 #define CKRST_CTRL_PMD_LANE_MODE_STATUS_PMD_LANE_MODE_BITS 16 3298 #define CKRST_CTRL_PMD_LANE_MODE_STATUS_PMD_LANE_MODE_SHIFT 0 3299 3300 3301 /**************************************************************************** 3302 * CKRST_CTRL :: LANE_DP_RESET_STATE_STATUS 3303 */ 3304 /* CKRST_CTRL :: LANE_DP_RESET_STATE_STATUS :: reserved0 [15:03] */ 3305 #define CKRST_CTRL_LANE_DP_RESET_STATE_STATUS_RESERVED0_MASK 0xfff8 3306 #define CKRST_CTRL_LANE_DP_RESET_STATE_STATUS_RESERVED0_ALIGN 0 3307 #define CKRST_CTRL_LANE_DP_RESET_STATE_STATUS_RESERVED0_BITS 13 3308 #define CKRST_CTRL_LANE_DP_RESET_STATE_STATUS_RESERVED0_SHIFT 3 3309 3310 /* CKRST_CTRL :: LANE_DP_RESET_STATE_STATUS :: lane_dp_reset_state [02:00] */ 3311 #define CKRST_CTRL_LANE_DP_RESET_STATE_STATUS_LANE_DP_RESET_STATE_MASK 0x0007 3312 #define CKRST_CTRL_LANE_DP_RESET_STATE_STATUS_LANE_DP_RESET_STATE_ALIGN 0 3313 #define CKRST_CTRL_LANE_DP_RESET_STATE_STATUS_LANE_DP_RESET_STATE_BITS 3 3314 #define CKRST_CTRL_LANE_DP_RESET_STATE_STATUS_LANE_DP_RESET_STATE_SHIFT 0 3315 3316 3317 /**************************************************************************** 3318 * CKRST_CTRL :: LANE_MULTICAST_MASK_CONTROL 3319 */ 3320 /* CKRST_CTRL :: LANE_MULTICAST_MASK_CONTROL :: reserved0 [15:01] */ 3321 #define CKRST_CTRL_LANE_MULTICAST_MASK_CONTROL_RESERVED0_MASK 0xfffe 3322 #define CKRST_CTRL_LANE_MULTICAST_MASK_CONTROL_RESERVED0_ALIGN 0 3323 #define CKRST_CTRL_LANE_MULTICAST_MASK_CONTROL_RESERVED0_BITS 15 3324 #define CKRST_CTRL_LANE_MULTICAST_MASK_CONTROL_RESERVED0_SHIFT 1 3325 3326 /* CKRST_CTRL :: LANE_MULTICAST_MASK_CONTROL :: lane_multicast_mask_control [00:00] */ 3327 #define CKRST_CTRL_LANE_MULTICAST_MASK_CONTROL_LANE_MULTICAST_MASK_CONTROL_MASK 0x0001 3328 #define CKRST_CTRL_LANE_MULTICAST_MASK_CONTROL_LANE_MULTICAST_MASK_CONTROL_ALIGN 0 3329 #define CKRST_CTRL_LANE_MULTICAST_MASK_CONTROL_LANE_MULTICAST_MASK_CONTROL_BITS 1 3330 #define CKRST_CTRL_LANE_MULTICAST_MASK_CONTROL_LANE_MULTICAST_MASK_CONTROL_SHIFT 0 3331 3332 3333 /**************************************************************************** 3334 * CKRST_CTRL :: OSR_MODE_STATUS 3335 */ 3336 /* CKRST_CTRL :: OSR_MODE_STATUS :: reserved0 [15:04] */ 3337 #define CKRST_CTRL_OSR_MODE_STATUS_RESERVED0_MASK 0xfff0 3338 #define CKRST_CTRL_OSR_MODE_STATUS_RESERVED0_ALIGN 0 3339 #define CKRST_CTRL_OSR_MODE_STATUS_RESERVED0_BITS 12 3340 #define CKRST_CTRL_OSR_MODE_STATUS_RESERVED0_SHIFT 4 3341 3342 /* CKRST_CTRL :: OSR_MODE_STATUS :: osr_mode [03:00] */ 3343 #define CKRST_CTRL_OSR_MODE_STATUS_OSR_MODE_MASK 0x000f 3344 #define CKRST_CTRL_OSR_MODE_STATUS_OSR_MODE_ALIGN 0 3345 #define CKRST_CTRL_OSR_MODE_STATUS_OSR_MODE_BITS 4 3346 #define CKRST_CTRL_OSR_MODE_STATUS_OSR_MODE_SHIFT 0 3347 3348 3349 /**************************************************************************** 3350 * CKRST_CTRL :: OSR_MODE_PIN_STATUS 3351 */ 3352 /* CKRST_CTRL :: OSR_MODE_PIN_STATUS :: reserved0 [15:04] */ 3353 #define CKRST_CTRL_OSR_MODE_PIN_STATUS_RESERVED0_MASK 0xfff0 3354 #define CKRST_CTRL_OSR_MODE_PIN_STATUS_RESERVED0_ALIGN 0 3355 #define CKRST_CTRL_OSR_MODE_PIN_STATUS_RESERVED0_BITS 12 3356 #define CKRST_CTRL_OSR_MODE_PIN_STATUS_RESERVED0_SHIFT 4 3357 3358 /* CKRST_CTRL :: OSR_MODE_PIN_STATUS :: osr_mode_pin [03:00] */ 3359 #define CKRST_CTRL_OSR_MODE_PIN_STATUS_OSR_MODE_PIN_MASK 0x000f 3360 #define CKRST_CTRL_OSR_MODE_PIN_STATUS_OSR_MODE_PIN_ALIGN 0 3361 #define CKRST_CTRL_OSR_MODE_PIN_STATUS_OSR_MODE_PIN_BITS 4 3362 #define CKRST_CTRL_OSR_MODE_PIN_STATUS_OSR_MODE_PIN_SHIFT 0 3363 3364 3365 /**************************************************************************** 3366 * CKRST_CTRL :: LN_S_RSTB_CONTROL 3367 */ 3368 /* CKRST_CTRL :: LN_S_RSTB_CONTROL :: reserved0 [15:01] */ 3369 #define CKRST_CTRL_LN_S_RSTB_CONTROL_RESERVED0_MASK 0xfffe 3370 #define CKRST_CTRL_LN_S_RSTB_CONTROL_RESERVED0_ALIGN 0 3371 #define CKRST_CTRL_LN_S_RSTB_CONTROL_RESERVED0_BITS 15 3372 #define CKRST_CTRL_LN_S_RSTB_CONTROL_RESERVED0_SHIFT 1 3373 3374 /* CKRST_CTRL :: LN_S_RSTB_CONTROL :: ln_s_rstb [00:00] */ 3375 #define CKRST_CTRL_LN_S_RSTB_CONTROL_LN_S_RSTB_MASK 0x0001 3376 #define CKRST_CTRL_LN_S_RSTB_CONTROL_LN_S_RSTB_ALIGN 0 3377 #define CKRST_CTRL_LN_S_RSTB_CONTROL_LN_S_RSTB_BITS 1 3378 #define CKRST_CTRL_LN_S_RSTB_CONTROL_LN_S_RSTB_SHIFT 0 3379 3380 3381 /**************************************************************************** 3382 * eagle_tsc_ams_blk_AMS_RX 3383 */ 3384 /**************************************************************************** 3385 * AMS_RX :: CONTROL_0 3386 */ 3387 /* AMS_RX :: CONTROL_0 :: ams_rx_imod_commonmode [15:15] */ 3388 #define AMS_RX_CONTROL_0_AMS_RX_IMOD_COMMONMODE_MASK 0x8000 3389 #define AMS_RX_CONTROL_0_AMS_RX_IMOD_COMMONMODE_ALIGN 0 3390 #define AMS_RX_CONTROL_0_AMS_RX_IMOD_COMMONMODE_BITS 1 3391 #define AMS_RX_CONTROL_0_AMS_RX_IMOD_COMMONMODE_SHIFT 15 3392 3393 /* AMS_RX :: CONTROL_0 :: ams_rx_imin_commonmode [14:14] */ 3394 #define AMS_RX_CONTROL_0_AMS_RX_IMIN_COMMONMODE_MASK 0x4000 3395 #define AMS_RX_CONTROL_0_AMS_RX_IMIN_COMMONMODE_ALIGN 0 3396 #define AMS_RX_CONTROL_0_AMS_RX_IMIN_COMMONMODE_BITS 1 3397 #define AMS_RX_CONTROL_0_AMS_RX_IMIN_COMMONMODE_SHIFT 14 3398 3399 /* AMS_RX :: CONTROL_0 :: ams_rx_en_10gmode [13:13] */ 3400 #define AMS_RX_CONTROL_0_AMS_RX_EN_10GMODE_MASK 0x2000 3401 #define AMS_RX_CONTROL_0_AMS_RX_EN_10GMODE_ALIGN 0 3402 #define AMS_RX_CONTROL_0_AMS_RX_EN_10GMODE_BITS 1 3403 #define AMS_RX_CONTROL_0_AMS_RX_EN_10GMODE_SHIFT 13 3404 3405 /* AMS_RX :: CONTROL_0 :: ams_rx_dc_couple [12:12] */ 3406 #define AMS_RX_CONTROL_0_AMS_RX_DC_COUPLE_MASK 0x1000 3407 #define AMS_RX_CONTROL_0_AMS_RX_DC_COUPLE_ALIGN 0 3408 #define AMS_RX_CONTROL_0_AMS_RX_DC_COUPLE_BITS 1 3409 #define AMS_RX_CONTROL_0_AMS_RX_DC_COUPLE_SHIFT 12 3410 3411 /* AMS_RX :: CONTROL_0 :: ams_rx_vga_bw_extension [11:11] */ 3412 #define AMS_RX_CONTROL_0_AMS_RX_VGA_BW_EXTENSION_MASK 0x0800 3413 #define AMS_RX_CONTROL_0_AMS_RX_VGA_BW_EXTENSION_ALIGN 0 3414 #define AMS_RX_CONTROL_0_AMS_RX_VGA_BW_EXTENSION_BITS 1 3415 #define AMS_RX_CONTROL_0_AMS_RX_VGA_BW_EXTENSION_SHIFT 11 3416 3417 /* AMS_RX :: CONTROL_0 :: ams_rx_sigdet_low_power [10:10] */ 3418 #define AMS_RX_CONTROL_0_AMS_RX_SIGDET_LOW_POWER_MASK 0x0400 3419 #define AMS_RX_CONTROL_0_AMS_RX_SIGDET_LOW_POWER_ALIGN 0 3420 #define AMS_RX_CONTROL_0_AMS_RX_SIGDET_LOW_POWER_BITS 1 3421 #define AMS_RX_CONTROL_0_AMS_RX_SIGDET_LOW_POWER_SHIFT 10 3422 3423 /* AMS_RX :: CONTROL_0 :: ams_rx_sigdet_bypass [09:09] */ 3424 #define AMS_RX_CONTROL_0_AMS_RX_SIGDET_BYPASS_MASK 0x0200 3425 #define AMS_RX_CONTROL_0_AMS_RX_SIGDET_BYPASS_ALIGN 0 3426 #define AMS_RX_CONTROL_0_AMS_RX_SIGDET_BYPASS_BITS 1 3427 #define AMS_RX_CONTROL_0_AMS_RX_SIGDET_BYPASS_SHIFT 9 3428 3429 /* AMS_RX :: CONTROL_0 :: ams_rx_tport_en [08:08] */ 3430 #define AMS_RX_CONTROL_0_AMS_RX_TPORT_EN_MASK 0x0100 3431 #define AMS_RX_CONTROL_0_AMS_RX_TPORT_EN_ALIGN 0 3432 #define AMS_RX_CONTROL_0_AMS_RX_TPORT_EN_BITS 1 3433 #define AMS_RX_CONTROL_0_AMS_RX_TPORT_EN_SHIFT 8 3434 3435 /* AMS_RX :: CONTROL_0 :: ams_rx_vga_output_idle [07:07] */ 3436 #define AMS_RX_CONTROL_0_AMS_RX_VGA_OUTPUT_IDLE_MASK 0x0080 3437 #define AMS_RX_CONTROL_0_AMS_RX_VGA_OUTPUT_IDLE_ALIGN 0 3438 #define AMS_RX_CONTROL_0_AMS_RX_VGA_OUTPUT_IDLE_BITS 1 3439 #define AMS_RX_CONTROL_0_AMS_RX_VGA_OUTPUT_IDLE_SHIFT 7 3440 3441 /* AMS_RX :: CONTROL_0 :: ams_rx_sig_pwrdn [06:06] */ 3442 #define AMS_RX_CONTROL_0_AMS_RX_SIG_PWRDN_MASK 0x0040 3443 #define AMS_RX_CONTROL_0_AMS_RX_SIG_PWRDN_ALIGN 0 3444 #define AMS_RX_CONTROL_0_AMS_RX_SIG_PWRDN_BITS 1 3445 #define AMS_RX_CONTROL_0_AMS_RX_SIG_PWRDN_SHIFT 6 3446 3447 /* AMS_RX :: CONTROL_0 :: ams_rx_sigdet_threshold [05:03] */ 3448 #define AMS_RX_CONTROL_0_AMS_RX_SIGDET_THRESHOLD_MASK 0x0038 3449 #define AMS_RX_CONTROL_0_AMS_RX_SIGDET_THRESHOLD_ALIGN 0 3450 #define AMS_RX_CONTROL_0_AMS_RX_SIGDET_THRESHOLD_BITS 3 3451 #define AMS_RX_CONTROL_0_AMS_RX_SIGDET_THRESHOLD_SHIFT 3 3452 3453 /* AMS_RX :: CONTROL_0 :: ams_rx_phase_int_ampl_ctrl [02:02] */ 3454 #define AMS_RX_CONTROL_0_AMS_RX_PHASE_INT_AMPL_CTRL_MASK 0x0004 3455 #define AMS_RX_CONTROL_0_AMS_RX_PHASE_INT_AMPL_CTRL_ALIGN 0 3456 #define AMS_RX_CONTROL_0_AMS_RX_PHASE_INT_AMPL_CTRL_BITS 1 3457 #define AMS_RX_CONTROL_0_AMS_RX_PHASE_INT_AMPL_CTRL_SHIFT 2 3458 3459 /* AMS_RX :: CONTROL_0 :: ams_rx_sel_dfeckdelay [01:00] */ 3460 #define AMS_RX_CONTROL_0_AMS_RX_SEL_DFECKDELAY_MASK 0x0003 3461 #define AMS_RX_CONTROL_0_AMS_RX_SEL_DFECKDELAY_ALIGN 0 3462 #define AMS_RX_CONTROL_0_AMS_RX_SEL_DFECKDELAY_BITS 2 3463 #define AMS_RX_CONTROL_0_AMS_RX_SEL_DFECKDELAY_SHIFT 0 3464 3465 3466 /**************************************************************************** 3467 * AMS_RX :: CONTROL_1 3468 */ 3469 /* AMS_RX :: CONTROL_1 :: ams_rx_imax_ctat [15:15] */ 3470 #define AMS_RX_CONTROL_1_AMS_RX_IMAX_CTAT_MASK 0x8000 3471 #define AMS_RX_CONTROL_1_AMS_RX_IMAX_CTAT_ALIGN 0 3472 #define AMS_RX_CONTROL_1_AMS_RX_IMAX_CTAT_BITS 1 3473 #define AMS_RX_CONTROL_1_AMS_RX_IMAX_CTAT_SHIFT 15 3474 3475 /* AMS_RX :: CONTROL_1 :: ams_rx_imode_ctat [14:14] */ 3476 #define AMS_RX_CONTROL_1_AMS_RX_IMODE_CTAT_MASK 0x4000 3477 #define AMS_RX_CONTROL_1_AMS_RX_IMODE_CTAT_ALIGN 0 3478 #define AMS_RX_CONTROL_1_AMS_RX_IMODE_CTAT_BITS 1 3479 #define AMS_RX_CONTROL_1_AMS_RX_IMODE_CTAT_SHIFT 14 3480 3481 /* AMS_RX :: CONTROL_1 :: ams_rx_imin_ctat [13:13] */ 3482 #define AMS_RX_CONTROL_1_AMS_RX_IMIN_CTAT_MASK 0x2000 3483 #define AMS_RX_CONTROL_1_AMS_RX_IMIN_CTAT_ALIGN 0 3484 #define AMS_RX_CONTROL_1_AMS_RX_IMIN_CTAT_BITS 1 3485 #define AMS_RX_CONTROL_1_AMS_RX_IMIN_CTAT_SHIFT 13 3486 3487 /* AMS_RX :: CONTROL_1 :: ams_rx_imax_pf [12:12] */ 3488 #define AMS_RX_CONTROL_1_AMS_RX_IMAX_PF_MASK 0x1000 3489 #define AMS_RX_CONTROL_1_AMS_RX_IMAX_PF_ALIGN 0 3490 #define AMS_RX_CONTROL_1_AMS_RX_IMAX_PF_BITS 1 3491 #define AMS_RX_CONTROL_1_AMS_RX_IMAX_PF_SHIFT 12 3492 3493 /* AMS_RX :: CONTROL_1 :: ams_rx_imode_pf [11:11] */ 3494 #define AMS_RX_CONTROL_1_AMS_RX_IMODE_PF_MASK 0x0800 3495 #define AMS_RX_CONTROL_1_AMS_RX_IMODE_PF_ALIGN 0 3496 #define AMS_RX_CONTROL_1_AMS_RX_IMODE_PF_BITS 1 3497 #define AMS_RX_CONTROL_1_AMS_RX_IMODE_PF_SHIFT 11 3498 3499 /* AMS_RX :: CONTROL_1 :: ams_rx_imin_pf [10:10] */ 3500 #define AMS_RX_CONTROL_1_AMS_RX_IMIN_PF_MASK 0x0400 3501 #define AMS_RX_CONTROL_1_AMS_RX_IMIN_PF_ALIGN 0 3502 #define AMS_RX_CONTROL_1_AMS_RX_IMIN_PF_BITS 1 3503 #define AMS_RX_CONTROL_1_AMS_RX_IMIN_PF_SHIFT 10 3504 3505 /* AMS_RX :: CONTROL_1 :: ams_rx_imax_dfe_summer [09:09] */ 3506 #define AMS_RX_CONTROL_1_AMS_RX_IMAX_DFE_SUMMER_MASK 0x0200 3507 #define AMS_RX_CONTROL_1_AMS_RX_IMAX_DFE_SUMMER_ALIGN 0 3508 #define AMS_RX_CONTROL_1_AMS_RX_IMAX_DFE_SUMMER_BITS 1 3509 #define AMS_RX_CONTROL_1_AMS_RX_IMAX_DFE_SUMMER_SHIFT 9 3510 3511 /* AMS_RX :: CONTROL_1 :: ams_rx_imode_dfe_summer [08:08] */ 3512 #define AMS_RX_CONTROL_1_AMS_RX_IMODE_DFE_SUMMER_MASK 0x0100 3513 #define AMS_RX_CONTROL_1_AMS_RX_IMODE_DFE_SUMMER_ALIGN 0 3514 #define AMS_RX_CONTROL_1_AMS_RX_IMODE_DFE_SUMMER_BITS 1 3515 #define AMS_RX_CONTROL_1_AMS_RX_IMODE_DFE_SUMMER_SHIFT 8 3516 3517 /* AMS_RX :: CONTROL_1 :: ams_rx_imin_dfe_summer [07:07] */ 3518 #define AMS_RX_CONTROL_1_AMS_RX_IMIN_DFE_SUMMER_MASK 0x0080 3519 #define AMS_RX_CONTROL_1_AMS_RX_IMIN_DFE_SUMMER_ALIGN 0 3520 #define AMS_RX_CONTROL_1_AMS_RX_IMIN_DFE_SUMMER_BITS 1 3521 #define AMS_RX_CONTROL_1_AMS_RX_IMIN_DFE_SUMMER_SHIFT 7 3522 3523 /* AMS_RX :: CONTROL_1 :: ams_rx_imax_vga [06:06] */ 3524 #define AMS_RX_CONTROL_1_AMS_RX_IMAX_VGA_MASK 0x0040 3525 #define AMS_RX_CONTROL_1_AMS_RX_IMAX_VGA_ALIGN 0 3526 #define AMS_RX_CONTROL_1_AMS_RX_IMAX_VGA_BITS 1 3527 #define AMS_RX_CONTROL_1_AMS_RX_IMAX_VGA_SHIFT 6 3528 3529 /* AMS_RX :: CONTROL_1 :: ams_rx_imode_vga [05:05] */ 3530 #define AMS_RX_CONTROL_1_AMS_RX_IMODE_VGA_MASK 0x0020 3531 #define AMS_RX_CONTROL_1_AMS_RX_IMODE_VGA_ALIGN 0 3532 #define AMS_RX_CONTROL_1_AMS_RX_IMODE_VGA_BITS 1 3533 #define AMS_RX_CONTROL_1_AMS_RX_IMODE_VGA_SHIFT 5 3534 3535 /* AMS_RX :: CONTROL_1 :: ams_rx_imin_vga [04:04] */ 3536 #define AMS_RX_CONTROL_1_AMS_RX_IMIN_VGA_MASK 0x0010 3537 #define AMS_RX_CONTROL_1_AMS_RX_IMIN_VGA_ALIGN 0 3538 #define AMS_RX_CONTROL_1_AMS_RX_IMIN_VGA_BITS 1 3539 #define AMS_RX_CONTROL_1_AMS_RX_IMIN_VGA_SHIFT 4 3540 3541 /* AMS_RX :: CONTROL_1 :: ams_rx_imax_phase_int [03:03] */ 3542 #define AMS_RX_CONTROL_1_AMS_RX_IMAX_PHASE_INT_MASK 0x0008 3543 #define AMS_RX_CONTROL_1_AMS_RX_IMAX_PHASE_INT_ALIGN 0 3544 #define AMS_RX_CONTROL_1_AMS_RX_IMAX_PHASE_INT_BITS 1 3545 #define AMS_RX_CONTROL_1_AMS_RX_IMAX_PHASE_INT_SHIFT 3 3546 3547 /* AMS_RX :: CONTROL_1 :: ams_rx_imode_phase_int [02:02] */ 3548 #define AMS_RX_CONTROL_1_AMS_RX_IMODE_PHASE_INT_MASK 0x0004 3549 #define AMS_RX_CONTROL_1_AMS_RX_IMODE_PHASE_INT_ALIGN 0 3550 #define AMS_RX_CONTROL_1_AMS_RX_IMODE_PHASE_INT_BITS 1 3551 #define AMS_RX_CONTROL_1_AMS_RX_IMODE_PHASE_INT_SHIFT 2 3552 3553 /* AMS_RX :: CONTROL_1 :: ams_rx_imin_phase_int [01:01] */ 3554 #define AMS_RX_CONTROL_1_AMS_RX_IMIN_PHASE_INT_MASK 0x0002 3555 #define AMS_RX_CONTROL_1_AMS_RX_IMIN_PHASE_INT_ALIGN 0 3556 #define AMS_RX_CONTROL_1_AMS_RX_IMIN_PHASE_INT_BITS 1 3557 #define AMS_RX_CONTROL_1_AMS_RX_IMIN_PHASE_INT_SHIFT 1 3558 3559 /* AMS_RX :: CONTROL_1 :: ams_rx_imax_commonmode [00:00] */ 3560 #define AMS_RX_CONTROL_1_AMS_RX_IMAX_COMMONMODE_MASK 0x0001 3561 #define AMS_RX_CONTROL_1_AMS_RX_IMAX_COMMONMODE_ALIGN 0 3562 #define AMS_RX_CONTROL_1_AMS_RX_IMAX_COMMONMODE_BITS 1 3563 #define AMS_RX_CONTROL_1_AMS_RX_IMAX_COMMONMODE_SHIFT 0 3564 3565 3566 /**************************************************************************** 3567 * AMS_RX :: CONTROL_2 3568 */ 3569 /* AMS_RX :: CONTROL_2 :: ams_rx_spare_47 [15:15] */ 3570 #define AMS_RX_CONTROL_2_AMS_RX_SPARE_47_MASK 0x8000 3571 #define AMS_RX_CONTROL_2_AMS_RX_SPARE_47_ALIGN 0 3572 #define AMS_RX_CONTROL_2_AMS_RX_SPARE_47_BITS 1 3573 #define AMS_RX_CONTROL_2_AMS_RX_SPARE_47_SHIFT 15 3574 3575 /* AMS_RX :: CONTROL_2 :: ams_rx_spare_46 [14:14] */ 3576 #define AMS_RX_CONTROL_2_AMS_RX_SPARE_46_MASK 0x4000 3577 #define AMS_RX_CONTROL_2_AMS_RX_SPARE_46_ALIGN 0 3578 #define AMS_RX_CONTROL_2_AMS_RX_SPARE_46_BITS 1 3579 #define AMS_RX_CONTROL_2_AMS_RX_SPARE_46_SHIFT 14 3580 3581 /* AMS_RX :: CONTROL_2 :: ams_rx_en_vcctrl [13:13] */ 3582 #define AMS_RX_CONTROL_2_AMS_RX_EN_VCCTRL_MASK 0x2000 3583 #define AMS_RX_CONTROL_2_AMS_RX_EN_VCCTRL_ALIGN 0 3584 #define AMS_RX_CONTROL_2_AMS_RX_EN_VCCTRL_BITS 1 3585 #define AMS_RX_CONTROL_2_AMS_RX_EN_VCCTRL_SHIFT 13 3586 3587 /* AMS_RX :: CONTROL_2 :: ams_rx_sel_th4dfe [12:11] */ 3588 #define AMS_RX_CONTROL_2_AMS_RX_SEL_TH4DFE_MASK 0x1800 3589 #define AMS_RX_CONTROL_2_AMS_RX_SEL_TH4DFE_ALIGN 0 3590 #define AMS_RX_CONTROL_2_AMS_RX_SEL_TH4DFE_BITS 2 3591 #define AMS_RX_CONTROL_2_AMS_RX_SEL_TH4DFE_SHIFT 11 3592 3593 /* AMS_RX :: CONTROL_2 :: ams_rx_sel_ugbw [10:09] */ 3594 #define AMS_RX_CONTROL_2_AMS_RX_SEL_UGBW_MASK 0x0600 3595 #define AMS_RX_CONTROL_2_AMS_RX_SEL_UGBW_ALIGN 0 3596 #define AMS_RX_CONTROL_2_AMS_RX_SEL_UGBW_BITS 2 3597 #define AMS_RX_CONTROL_2_AMS_RX_SEL_UGBW_SHIFT 9 3598 3599 /* AMS_RX :: CONTROL_2 :: ams_rx_imax_dfe_tap_weight [08:08] */ 3600 #define AMS_RX_CONTROL_2_AMS_RX_IMAX_DFE_TAP_WEIGHT_MASK 0x0100 3601 #define AMS_RX_CONTROL_2_AMS_RX_IMAX_DFE_TAP_WEIGHT_ALIGN 0 3602 #define AMS_RX_CONTROL_2_AMS_RX_IMAX_DFE_TAP_WEIGHT_BITS 1 3603 #define AMS_RX_CONTROL_2_AMS_RX_IMAX_DFE_TAP_WEIGHT_SHIFT 8 3604 3605 /* AMS_RX :: CONTROL_2 :: ams_rx_imode_dfe_tap_weight [07:07] */ 3606 #define AMS_RX_CONTROL_2_AMS_RX_IMODE_DFE_TAP_WEIGHT_MASK 0x0080 3607 #define AMS_RX_CONTROL_2_AMS_RX_IMODE_DFE_TAP_WEIGHT_ALIGN 0 3608 #define AMS_RX_CONTROL_2_AMS_RX_IMODE_DFE_TAP_WEIGHT_BITS 1 3609 #define AMS_RX_CONTROL_2_AMS_RX_IMODE_DFE_TAP_WEIGHT_SHIFT 7 3610 3611 /* AMS_RX :: CONTROL_2 :: ams_rx_imin_dfe_tap_weight [06:06] */ 3612 #define AMS_RX_CONTROL_2_AMS_RX_IMIN_DFE_TAP_WEIGHT_MASK 0x0040 3613 #define AMS_RX_CONTROL_2_AMS_RX_IMIN_DFE_TAP_WEIGHT_ALIGN 0 3614 #define AMS_RX_CONTROL_2_AMS_RX_IMIN_DFE_TAP_WEIGHT_BITS 1 3615 #define AMS_RX_CONTROL_2_AMS_RX_IMIN_DFE_TAP_WEIGHT_SHIFT 6 3616 3617 /* AMS_RX :: CONTROL_2 :: ams_rx_imax_slicer [05:05] */ 3618 #define AMS_RX_CONTROL_2_AMS_RX_IMAX_SLICER_MASK 0x0020 3619 #define AMS_RX_CONTROL_2_AMS_RX_IMAX_SLICER_ALIGN 0 3620 #define AMS_RX_CONTROL_2_AMS_RX_IMAX_SLICER_BITS 1 3621 #define AMS_RX_CONTROL_2_AMS_RX_IMAX_SLICER_SHIFT 5 3622 3623 /* AMS_RX :: CONTROL_2 :: ams_rx_imode_slicer [04:04] */ 3624 #define AMS_RX_CONTROL_2_AMS_RX_IMODE_SLICER_MASK 0x0010 3625 #define AMS_RX_CONTROL_2_AMS_RX_IMODE_SLICER_ALIGN 0 3626 #define AMS_RX_CONTROL_2_AMS_RX_IMODE_SLICER_BITS 1 3627 #define AMS_RX_CONTROL_2_AMS_RX_IMODE_SLICER_SHIFT 4 3628 3629 /* AMS_RX :: CONTROL_2 :: ams_rx_imin_slicer [03:03] */ 3630 #define AMS_RX_CONTROL_2_AMS_RX_IMIN_SLICER_MASK 0x0008 3631 #define AMS_RX_CONTROL_2_AMS_RX_IMIN_SLICER_ALIGN 0 3632 #define AMS_RX_CONTROL_2_AMS_RX_IMIN_SLICER_BITS 1 3633 #define AMS_RX_CONTROL_2_AMS_RX_IMIN_SLICER_SHIFT 3 3634 3635 /* AMS_RX :: CONTROL_2 :: ams_rx_spare_34 [02:02] */ 3636 #define AMS_RX_CONTROL_2_AMS_RX_SPARE_34_MASK 0x0004 3637 #define AMS_RX_CONTROL_2_AMS_RX_SPARE_34_ALIGN 0 3638 #define AMS_RX_CONTROL_2_AMS_RX_SPARE_34_BITS 1 3639 #define AMS_RX_CONTROL_2_AMS_RX_SPARE_34_SHIFT 2 3640 3641 /* AMS_RX :: CONTROL_2 :: ams_rx_spare_33 [01:01] */ 3642 #define AMS_RX_CONTROL_2_AMS_RX_SPARE_33_MASK 0x0002 3643 #define AMS_RX_CONTROL_2_AMS_RX_SPARE_33_ALIGN 0 3644 #define AMS_RX_CONTROL_2_AMS_RX_SPARE_33_BITS 1 3645 #define AMS_RX_CONTROL_2_AMS_RX_SPARE_33_SHIFT 1 3646 3647 /* AMS_RX :: CONTROL_2 :: ams_rx_spare_32 [00:00] */ 3648 #define AMS_RX_CONTROL_2_AMS_RX_SPARE_32_MASK 0x0001 3649 #define AMS_RX_CONTROL_2_AMS_RX_SPARE_32_ALIGN 0 3650 #define AMS_RX_CONTROL_2_AMS_RX_SPARE_32_BITS 1 3651 #define AMS_RX_CONTROL_2_AMS_RX_SPARE_32_SHIFT 0 3652 3653 3654 /**************************************************************************** 3655 * AMS_RX :: CONTROL_3 3656 */ 3657 /* AMS_RX :: CONTROL_3 :: ams_rx_spare_63 [15:15] */ 3658 #define AMS_RX_CONTROL_3_AMS_RX_SPARE_63_MASK 0x8000 3659 #define AMS_RX_CONTROL_3_AMS_RX_SPARE_63_ALIGN 0 3660 #define AMS_RX_CONTROL_3_AMS_RX_SPARE_63_BITS 1 3661 #define AMS_RX_CONTROL_3_AMS_RX_SPARE_63_SHIFT 15 3662 3663 /* AMS_RX :: CONTROL_3 :: ams_rx_spare_62 [14:14] */ 3664 #define AMS_RX_CONTROL_3_AMS_RX_SPARE_62_MASK 0x4000 3665 #define AMS_RX_CONTROL_3_AMS_RX_SPARE_62_ALIGN 0 3666 #define AMS_RX_CONTROL_3_AMS_RX_SPARE_62_BITS 1 3667 #define AMS_RX_CONTROL_3_AMS_RX_SPARE_62_SHIFT 14 3668 3669 /* AMS_RX :: CONTROL_3 :: ams_rx_i1p25dfe [13:13] */ 3670 #define AMS_RX_CONTROL_3_AMS_RX_I1P25DFE_MASK 0x2000 3671 #define AMS_RX_CONTROL_3_AMS_RX_I1P25DFE_ALIGN 0 3672 #define AMS_RX_CONTROL_3_AMS_RX_I1P25DFE_BITS 1 3673 #define AMS_RX_CONTROL_3_AMS_RX_I1P25DFE_SHIFT 13 3674 3675 /* AMS_RX :: CONTROL_3 :: ams_rx_i4deadzone [12:12] */ 3676 #define AMS_RX_CONTROL_3_AMS_RX_I4DEADZONE_MASK 0x1000 3677 #define AMS_RX_CONTROL_3_AMS_RX_I4DEADZONE_ALIGN 0 3678 #define AMS_RX_CONTROL_3_AMS_RX_I4DEADZONE_BITS 1 3679 #define AMS_RX_CONTROL_3_AMS_RX_I4DEADZONE_SHIFT 12 3680 3681 /* AMS_RX :: CONTROL_3 :: ams_rx_imax_signal_detect [11:11] */ 3682 #define AMS_RX_CONTROL_3_AMS_RX_IMAX_SIGNAL_DETECT_MASK 0x0800 3683 #define AMS_RX_CONTROL_3_AMS_RX_IMAX_SIGNAL_DETECT_ALIGN 0 3684 #define AMS_RX_CONTROL_3_AMS_RX_IMAX_SIGNAL_DETECT_BITS 1 3685 #define AMS_RX_CONTROL_3_AMS_RX_IMAX_SIGNAL_DETECT_SHIFT 11 3686 3687 /* AMS_RX :: CONTROL_3 :: ams_rx_imode_signal_detect [10:10] */ 3688 #define AMS_RX_CONTROL_3_AMS_RX_IMODE_SIGNAL_DETECT_MASK 0x0400 3689 #define AMS_RX_CONTROL_3_AMS_RX_IMODE_SIGNAL_DETECT_ALIGN 0 3690 #define AMS_RX_CONTROL_3_AMS_RX_IMODE_SIGNAL_DETECT_BITS 1 3691 #define AMS_RX_CONTROL_3_AMS_RX_IMODE_SIGNAL_DETECT_SHIFT 10 3692 3693 /* AMS_RX :: CONTROL_3 :: ams_rx_imin_signal_detect [09:09] */ 3694 #define AMS_RX_CONTROL_3_AMS_RX_IMIN_SIGNAL_DETECT_MASK 0x0200 3695 #define AMS_RX_CONTROL_3_AMS_RX_IMIN_SIGNAL_DETECT_ALIGN 0 3696 #define AMS_RX_CONTROL_3_AMS_RX_IMIN_SIGNAL_DETECT_BITS 1 3697 #define AMS_RX_CONTROL_3_AMS_RX_IMIN_SIGNAL_DETECT_SHIFT 9 3698 3699 /* AMS_RX :: CONTROL_3 :: ams_rx_imax_metres_eyediag [08:08] */ 3700 #define AMS_RX_CONTROL_3_AMS_RX_IMAX_METRES_EYEDIAG_MASK 0x0100 3701 #define AMS_RX_CONTROL_3_AMS_RX_IMAX_METRES_EYEDIAG_ALIGN 0 3702 #define AMS_RX_CONTROL_3_AMS_RX_IMAX_METRES_EYEDIAG_BITS 1 3703 #define AMS_RX_CONTROL_3_AMS_RX_IMAX_METRES_EYEDIAG_SHIFT 8 3704 3705 /* AMS_RX :: CONTROL_3 :: ams_rx_imode_metres_eyediag [07:07] */ 3706 #define AMS_RX_CONTROL_3_AMS_RX_IMODE_METRES_EYEDIAG_MASK 0x0080 3707 #define AMS_RX_CONTROL_3_AMS_RX_IMODE_METRES_EYEDIAG_ALIGN 0 3708 #define AMS_RX_CONTROL_3_AMS_RX_IMODE_METRES_EYEDIAG_BITS 1 3709 #define AMS_RX_CONTROL_3_AMS_RX_IMODE_METRES_EYEDIAG_SHIFT 7 3710 3711 /* AMS_RX :: CONTROL_3 :: ams_rx_imin_metres_eyediag [06:06] */ 3712 #define AMS_RX_CONTROL_3_AMS_RX_IMIN_METRES_EYEDIAG_MASK 0x0040 3713 #define AMS_RX_CONTROL_3_AMS_RX_IMIN_METRES_EYEDIAG_ALIGN 0 3714 #define AMS_RX_CONTROL_3_AMS_RX_IMIN_METRES_EYEDIAG_BITS 1 3715 #define AMS_RX_CONTROL_3_AMS_RX_IMIN_METRES_EYEDIAG_SHIFT 6 3716 3717 /* AMS_RX :: CONTROL_3 :: ams_rx_imax_phase_int_p1 [05:05] */ 3718 #define AMS_RX_CONTROL_3_AMS_RX_IMAX_PHASE_INT_P1_MASK 0x0020 3719 #define AMS_RX_CONTROL_3_AMS_RX_IMAX_PHASE_INT_P1_ALIGN 0 3720 #define AMS_RX_CONTROL_3_AMS_RX_IMAX_PHASE_INT_P1_BITS 1 3721 #define AMS_RX_CONTROL_3_AMS_RX_IMAX_PHASE_INT_P1_SHIFT 5 3722 3723 /* AMS_RX :: CONTROL_3 :: ams_rx_imode_phase_int_p1 [04:04] */ 3724 #define AMS_RX_CONTROL_3_AMS_RX_IMODE_PHASE_INT_P1_MASK 0x0010 3725 #define AMS_RX_CONTROL_3_AMS_RX_IMODE_PHASE_INT_P1_ALIGN 0 3726 #define AMS_RX_CONTROL_3_AMS_RX_IMODE_PHASE_INT_P1_BITS 1 3727 #define AMS_RX_CONTROL_3_AMS_RX_IMODE_PHASE_INT_P1_SHIFT 4 3728 3729 /* AMS_RX :: CONTROL_3 :: ams_rx_imin_phase_int_p1 [03:03] */ 3730 #define AMS_RX_CONTROL_3_AMS_RX_IMIN_PHASE_INT_P1_MASK 0x0008 3731 #define AMS_RX_CONTROL_3_AMS_RX_IMIN_PHASE_INT_P1_ALIGN 0 3732 #define AMS_RX_CONTROL_3_AMS_RX_IMIN_PHASE_INT_P1_BITS 1 3733 #define AMS_RX_CONTROL_3_AMS_RX_IMIN_PHASE_INT_P1_SHIFT 3 3734 3735 /* AMS_RX :: CONTROL_3 :: ams_rx_imax_dc_offset_dac [02:02] */ 3736 #define AMS_RX_CONTROL_3_AMS_RX_IMAX_DC_OFFSET_DAC_MASK 0x0004 3737 #define AMS_RX_CONTROL_3_AMS_RX_IMAX_DC_OFFSET_DAC_ALIGN 0 3738 #define AMS_RX_CONTROL_3_AMS_RX_IMAX_DC_OFFSET_DAC_BITS 1 3739 #define AMS_RX_CONTROL_3_AMS_RX_IMAX_DC_OFFSET_DAC_SHIFT 2 3740 3741 /* AMS_RX :: CONTROL_3 :: ams_rx_imode_dc_offset_dac [01:01] */ 3742 #define AMS_RX_CONTROL_3_AMS_RX_IMODE_DC_OFFSET_DAC_MASK 0x0002 3743 #define AMS_RX_CONTROL_3_AMS_RX_IMODE_DC_OFFSET_DAC_ALIGN 0 3744 #define AMS_RX_CONTROL_3_AMS_RX_IMODE_DC_OFFSET_DAC_BITS 1 3745 #define AMS_RX_CONTROL_3_AMS_RX_IMODE_DC_OFFSET_DAC_SHIFT 1 3746 3747 /* AMS_RX :: CONTROL_3 :: ams_rx_imin_dc_offset_dac [00:00] */ 3748 #define AMS_RX_CONTROL_3_AMS_RX_IMIN_DC_OFFSET_DAC_MASK 0x0001 3749 #define AMS_RX_CONTROL_3_AMS_RX_IMIN_DC_OFFSET_DAC_ALIGN 0 3750 #define AMS_RX_CONTROL_3_AMS_RX_IMIN_DC_OFFSET_DAC_BITS 1 3751 #define AMS_RX_CONTROL_3_AMS_RX_IMIN_DC_OFFSET_DAC_SHIFT 0 3752 3753 3754 /**************************************************************************** 3755 * AMS_RX :: CONTROL_4 3756 */ 3757 /* AMS_RX :: CONTROL_4 :: ams_rx_phs_interp_rescal_mux [15:12] */ 3758 #define AMS_RX_CONTROL_4_AMS_RX_PHS_INTERP_RESCAL_MUX_MASK 0xf000 3759 #define AMS_RX_CONTROL_4_AMS_RX_PHS_INTERP_RESCAL_MUX_ALIGN 0 3760 #define AMS_RX_CONTROL_4_AMS_RX_PHS_INTERP_RESCAL_MUX_BITS 4 3761 #define AMS_RX_CONTROL_4_AMS_RX_PHS_INTERP_RESCAL_MUX_SHIFT 12 3762 3763 /* AMS_RX :: CONTROL_4 :: ams_rx_vga_rescal_mux [11:09] */ 3764 #define AMS_RX_CONTROL_4_AMS_RX_VGA_RESCAL_MUX_MASK 0x0e00 3765 #define AMS_RX_CONTROL_4_AMS_RX_VGA_RESCAL_MUX_ALIGN 0 3766 #define AMS_RX_CONTROL_4_AMS_RX_VGA_RESCAL_MUX_BITS 3 3767 #define AMS_RX_CONTROL_4_AMS_RX_VGA_RESCAL_MUX_SHIFT 9 3768 3769 /* AMS_RX :: CONTROL_4 :: ams_rx_dc_offset_range [08:08] */ 3770 #define AMS_RX_CONTROL_4_AMS_RX_DC_OFFSET_RANGE_MASK 0x0100 3771 #define AMS_RX_CONTROL_4_AMS_RX_DC_OFFSET_RANGE_ALIGN 0 3772 #define AMS_RX_CONTROL_4_AMS_RX_DC_OFFSET_RANGE_BITS 1 3773 #define AMS_RX_CONTROL_4_AMS_RX_DC_OFFSET_RANGE_SHIFT 8 3774 3775 /* AMS_RX :: CONTROL_4 :: ams_rx_force_dc_offset [07:07] */ 3776 #define AMS_RX_CONTROL_4_AMS_RX_FORCE_DC_OFFSET_MASK 0x0080 3777 #define AMS_RX_CONTROL_4_AMS_RX_FORCE_DC_OFFSET_ALIGN 0 3778 #define AMS_RX_CONTROL_4_AMS_RX_FORCE_DC_OFFSET_BITS 1 3779 #define AMS_RX_CONTROL_4_AMS_RX_FORCE_DC_OFFSET_SHIFT 7 3780 3781 /* AMS_RX :: CONTROL_4 :: ams_rx_dc_offset [06:00] */ 3782 #define AMS_RX_CONTROL_4_AMS_RX_DC_OFFSET_MASK 0x007f 3783 #define AMS_RX_CONTROL_4_AMS_RX_DC_OFFSET_ALIGN 0 3784 #define AMS_RX_CONTROL_4_AMS_RX_DC_OFFSET_BITS 7 3785 #define AMS_RX_CONTROL_4_AMS_RX_DC_OFFSET_SHIFT 0 3786 3787 3788 /**************************************************************************** 3789 * AMS_RX :: INTCTRL 3790 */ 3791 /* AMS_RX :: INTCTRL :: reserved0 [15:01] */ 3792 #define AMS_RX_INTCTRL_RESERVED0_MASK 0xfffe 3793 #define AMS_RX_INTCTRL_RESERVED0_ALIGN 0 3794 #define AMS_RX_INTCTRL_RESERVED0_BITS 15 3795 #define AMS_RX_INTCTRL_RESERVED0_SHIFT 1 3796 3797 /* AMS_RX :: INTCTRL :: ams_rx_dfe_os2x_mode [00:00] */ 3798 #define AMS_RX_INTCTRL_AMS_RX_DFE_OS2X_MODE_MASK 0x0001 3799 #define AMS_RX_INTCTRL_AMS_RX_DFE_OS2X_MODE_ALIGN 0 3800 #define AMS_RX_INTCTRL_AMS_RX_DFE_OS2X_MODE_BITS 1 3801 #define AMS_RX_INTCTRL_AMS_RX_DFE_OS2X_MODE_SHIFT 0 3802 3803 3804 /**************************************************************************** 3805 * AMS_RX :: STATUS 3806 */ 3807 /* AMS_RX :: STATUS :: ams_rx_sts [15:00] */ 3808 #define AMS_RX_STATUS_AMS_RX_STS_MASK 0xffff 3809 #define AMS_RX_STATUS_AMS_RX_STS_ALIGN 0 3810 #define AMS_RX_STATUS_AMS_RX_STS_BITS 16 3811 #define AMS_RX_STATUS_AMS_RX_STS_SHIFT 0 3812 3813 3814 /**************************************************************************** 3815 * eagle_tsc_ams_blk_AMS_TX 3816 */ 3817 /**************************************************************************** 3818 * AMS_TX :: CONTROL_0 3819 */ 3820 /* AMS_TX :: CONTROL_0 :: ams_tx_cal_aux [15:12] */ 3821 #define AMS_TX_CONTROL_0_AMS_TX_CAL_AUX_MASK 0xf000 3822 #define AMS_TX_CONTROL_0_AMS_TX_CAL_AUX_ALIGN 0 3823 #define AMS_TX_CONTROL_0_AMS_TX_CAL_AUX_BITS 4 3824 #define AMS_TX_CONTROL_0_AMS_TX_CAL_AUX_SHIFT 12 3825 3826 /* AMS_TX :: CONTROL_0 :: ams_tx_cal_off [11:11] */ 3827 #define AMS_TX_CONTROL_0_AMS_TX_CAL_OFF_MASK 0x0800 3828 #define AMS_TX_CONTROL_0_AMS_TX_CAL_OFF_ALIGN 0 3829 #define AMS_TX_CONTROL_0_AMS_TX_CAL_OFF_BITS 1 3830 #define AMS_TX_CONTROL_0_AMS_TX_CAL_OFF_SHIFT 11 3831 3832 /* AMS_TX :: CONTROL_0 :: ams_tx_dcc_dis [10:10] */ 3833 #define AMS_TX_CONTROL_0_AMS_TX_DCC_DIS_MASK 0x0400 3834 #define AMS_TX_CONTROL_0_AMS_TX_DCC_DIS_ALIGN 0 3835 #define AMS_TX_CONTROL_0_AMS_TX_DCC_DIS_BITS 1 3836 #define AMS_TX_CONTROL_0_AMS_TX_DCC_DIS_SHIFT 10 3837 3838 /* AMS_TX :: CONTROL_0 :: ams_tx_dcc_sel [09:09] */ 3839 #define AMS_TX_CONTROL_0_AMS_TX_DCC_SEL_MASK 0x0200 3840 #define AMS_TX_CONTROL_0_AMS_TX_DCC_SEL_ALIGN 0 3841 #define AMS_TX_CONTROL_0_AMS_TX_DCC_SEL_BITS 1 3842 #define AMS_TX_CONTROL_0_AMS_TX_DCC_SEL_SHIFT 9 3843 3844 /* AMS_TX :: CONTROL_0 :: ams_tx_kr_test_mode [08:08] */ 3845 #define AMS_TX_CONTROL_0_AMS_TX_KR_TEST_MODE_MASK 0x0100 3846 #define AMS_TX_CONTROL_0_AMS_TX_KR_TEST_MODE_ALIGN 0 3847 #define AMS_TX_CONTROL_0_AMS_TX_KR_TEST_MODE_BITS 1 3848 #define AMS_TX_CONTROL_0_AMS_TX_KR_TEST_MODE_SHIFT 8 3849 3850 /* AMS_TX :: CONTROL_0 :: ams_tx_ticksel [07:06] */ 3851 #define AMS_TX_CONTROL_0_AMS_TX_TICKSEL_MASK 0x00c0 3852 #define AMS_TX_CONTROL_0_AMS_TX_TICKSEL_ALIGN 0 3853 #define AMS_TX_CONTROL_0_AMS_TX_TICKSEL_BITS 2 3854 #define AMS_TX_CONTROL_0_AMS_TX_TICKSEL_SHIFT 6 3855 3856 /* AMS_TX :: CONTROL_0 :: ams_tx_test_data [05:04] */ 3857 #define AMS_TX_CONTROL_0_AMS_TX_TEST_DATA_MASK 0x0030 3858 #define AMS_TX_CONTROL_0_AMS_TX_TEST_DATA_ALIGN 0 3859 #define AMS_TX_CONTROL_0_AMS_TX_TEST_DATA_BITS 2 3860 #define AMS_TX_CONTROL_0_AMS_TX_TEST_DATA_SHIFT 4 3861 3862 /* AMS_TX :: CONTROL_0 :: ams_tx_spare_3 [03:03] */ 3863 #define AMS_TX_CONTROL_0_AMS_TX_SPARE_3_MASK 0x0008 3864 #define AMS_TX_CONTROL_0_AMS_TX_SPARE_3_ALIGN 0 3865 #define AMS_TX_CONTROL_0_AMS_TX_SPARE_3_BITS 1 3866 #define AMS_TX_CONTROL_0_AMS_TX_SPARE_3_SHIFT 3 3867 3868 /* AMS_TX :: CONTROL_0 :: ams_tx_spare_2 [02:02] */ 3869 #define AMS_TX_CONTROL_0_AMS_TX_SPARE_2_MASK 0x0004 3870 #define AMS_TX_CONTROL_0_AMS_TX_SPARE_2_ALIGN 0 3871 #define AMS_TX_CONTROL_0_AMS_TX_SPARE_2_BITS 1 3872 #define AMS_TX_CONTROL_0_AMS_TX_SPARE_2_SHIFT 2 3873 3874 /* AMS_TX :: CONTROL_0 :: ams_tx_spare_1 [01:01] */ 3875 #define AMS_TX_CONTROL_0_AMS_TX_SPARE_1_MASK 0x0002 3876 #define AMS_TX_CONTROL_0_AMS_TX_SPARE_1_ALIGN 0 3877 #define AMS_TX_CONTROL_0_AMS_TX_SPARE_1_BITS 1 3878 #define AMS_TX_CONTROL_0_AMS_TX_SPARE_1_SHIFT 1 3879 3880 /* AMS_TX :: CONTROL_0 :: ams_tx_osr4 [00:00] */ 3881 #define AMS_TX_CONTROL_0_AMS_TX_OSR4_MASK 0x0001 3882 #define AMS_TX_CONTROL_0_AMS_TX_OSR4_ALIGN 0 3883 #define AMS_TX_CONTROL_0_AMS_TX_OSR4_BITS 1 3884 #define AMS_TX_CONTROL_0_AMS_TX_OSR4_SHIFT 0 3885 3886 3887 /**************************************************************************** 3888 * AMS_TX :: CONTROL_1 3889 */ 3890 /* AMS_TX :: CONTROL_1 :: ams_tx_lp_ovrd [15:15] */ 3891 #define AMS_TX_CONTROL_1_AMS_TX_LP_OVRD_MASK 0x8000 3892 #define AMS_TX_CONTROL_1_AMS_TX_LP_OVRD_ALIGN 0 3893 #define AMS_TX_CONTROL_1_AMS_TX_LP_OVRD_BITS 1 3894 #define AMS_TX_CONTROL_1_AMS_TX_LP_OVRD_SHIFT 15 3895 3896 /* AMS_TX :: CONTROL_1 :: ams_tx_spare_30_25 [14:09] */ 3897 #define AMS_TX_CONTROL_1_AMS_TX_SPARE_30_25_MASK 0x7e00 3898 #define AMS_TX_CONTROL_1_AMS_TX_SPARE_30_25_ALIGN 0 3899 #define AMS_TX_CONTROL_1_AMS_TX_SPARE_30_25_BITS 6 3900 #define AMS_TX_CONTROL_1_AMS_TX_SPARE_30_25_SHIFT 9 3901 3902 /* AMS_TX :: CONTROL_1 :: ams_tx_icml [08:06] */ 3903 #define AMS_TX_CONTROL_1_AMS_TX_ICML_MASK 0x01c0 3904 #define AMS_TX_CONTROL_1_AMS_TX_ICML_ALIGN 0 3905 #define AMS_TX_CONTROL_1_AMS_TX_ICML_BITS 3 3906 #define AMS_TX_CONTROL_1_AMS_TX_ICML_SHIFT 6 3907 3908 /* AMS_TX :: CONTROL_1 :: ams_tx_idcc [05:03] */ 3909 #define AMS_TX_CONTROL_1_AMS_TX_IDCC_MASK 0x0038 3910 #define AMS_TX_CONTROL_1_AMS_TX_IDCC_ALIGN 0 3911 #define AMS_TX_CONTROL_1_AMS_TX_IDCC_BITS 3 3912 #define AMS_TX_CONTROL_1_AMS_TX_IDCC_SHIFT 3 3913 3914 /* AMS_TX :: CONTROL_1 :: ams_tx_ibias [02:00] */ 3915 #define AMS_TX_CONTROL_1_AMS_TX_IBIAS_MASK 0x0007 3916 #define AMS_TX_CONTROL_1_AMS_TX_IBIAS_ALIGN 0 3917 #define AMS_TX_CONTROL_1_AMS_TX_IBIAS_BITS 3 3918 #define AMS_TX_CONTROL_1_AMS_TX_IBIAS_SHIFT 0 3919 3920 3921 /**************************************************************************** 3922 * AMS_TX :: CONTROL_2 3923 */ 3924 /* AMS_TX :: CONTROL_2 :: ams_tx_elec_idle_aux [15:15] */ 3925 #define AMS_TX_CONTROL_2_AMS_TX_ELEC_IDLE_AUX_MASK 0x8000 3926 #define AMS_TX_CONTROL_2_AMS_TX_ELEC_IDLE_AUX_ALIGN 0 3927 #define AMS_TX_CONTROL_2_AMS_TX_ELEC_IDLE_AUX_BITS 1 3928 #define AMS_TX_CONTROL_2_AMS_TX_ELEC_IDLE_AUX_SHIFT 15 3929 3930 /* AMS_TX :: CONTROL_2 :: ams_tx_drivermode [14:13] */ 3931 #define AMS_TX_CONTROL_2_AMS_TX_DRIVERMODE_MASK 0x6000 3932 #define AMS_TX_CONTROL_2_AMS_TX_DRIVERMODE_ALIGN 0 3933 #define AMS_TX_CONTROL_2_AMS_TX_DRIVERMODE_BITS 2 3934 #define AMS_TX_CONTROL_2_AMS_TX_DRIVERMODE_SHIFT 13 3935 3936 /* AMS_TX :: CONTROL_2 :: ams_tx_sign_post2 [12:12] */ 3937 #define AMS_TX_CONTROL_2_AMS_TX_SIGN_POST2_MASK 0x1000 3938 #define AMS_TX_CONTROL_2_AMS_TX_SIGN_POST2_ALIGN 0 3939 #define AMS_TX_CONTROL_2_AMS_TX_SIGN_POST2_BITS 1 3940 #define AMS_TX_CONTROL_2_AMS_TX_SIGN_POST2_SHIFT 12 3941 3942 /* AMS_TX :: CONTROL_2 :: ams_tx_post2_coef [11:08] */ 3943 #define AMS_TX_CONTROL_2_AMS_TX_POST2_COEF_MASK 0x0f00 3944 #define AMS_TX_CONTROL_2_AMS_TX_POST2_COEF_ALIGN 0 3945 #define AMS_TX_CONTROL_2_AMS_TX_POST2_COEF_BITS 4 3946 #define AMS_TX_CONTROL_2_AMS_TX_POST2_COEF_SHIFT 8 3947 3948 /* AMS_TX :: CONTROL_2 :: ams_tx_sign_post3 [07:07] */ 3949 #define AMS_TX_CONTROL_2_AMS_TX_SIGN_POST3_MASK 0x0080 3950 #define AMS_TX_CONTROL_2_AMS_TX_SIGN_POST3_ALIGN 0 3951 #define AMS_TX_CONTROL_2_AMS_TX_SIGN_POST3_BITS 1 3952 #define AMS_TX_CONTROL_2_AMS_TX_SIGN_POST3_SHIFT 7 3953 3954 /* AMS_TX :: CONTROL_2 :: ams_tx_post3_coef [06:04] */ 3955 #define AMS_TX_CONTROL_2_AMS_TX_POST3_COEF_MASK 0x0070 3956 #define AMS_TX_CONTROL_2_AMS_TX_POST3_COEF_ALIGN 0 3957 #define AMS_TX_CONTROL_2_AMS_TX_POST3_COEF_BITS 3 3958 #define AMS_TX_CONTROL_2_AMS_TX_POST3_COEF_SHIFT 4 3959 3960 /* AMS_TX :: CONTROL_2 :: ams_tx_amp_ctl [03:00] */ 3961 #define AMS_TX_CONTROL_2_AMS_TX_AMP_CTL_MASK 0x000f 3962 #define AMS_TX_CONTROL_2_AMS_TX_AMP_CTL_ALIGN 0 3963 #define AMS_TX_CONTROL_2_AMS_TX_AMP_CTL_BITS 4 3964 #define AMS_TX_CONTROL_2_AMS_TX_AMP_CTL_SHIFT 0 3965 3966 3967 /**************************************************************************** 3968 * AMS_TX :: INTCTRL 3969 */ 3970 /* AMS_TX :: INTCTRL :: reserved0 [15:01] */ 3971 #define AMS_TX_INTCTRL_RESERVED0_MASK 0xfffe 3972 #define AMS_TX_INTCTRL_RESERVED0_ALIGN 0 3973 #define AMS_TX_INTCTRL_RESERVED0_BITS 15 3974 #define AMS_TX_INTCTRL_RESERVED0_SHIFT 1 3975 3976 /* AMS_TX :: INTCTRL :: ams_tx_sel_halfrate [00:00] */ 3977 #define AMS_TX_INTCTRL_AMS_TX_SEL_HALFRATE_MASK 0x0001 3978 #define AMS_TX_INTCTRL_AMS_TX_SEL_HALFRATE_ALIGN 0 3979 #define AMS_TX_INTCTRL_AMS_TX_SEL_HALFRATE_BITS 1 3980 #define AMS_TX_INTCTRL_AMS_TX_SEL_HALFRATE_SHIFT 0 3981 3982 3983 /**************************************************************************** 3984 * AMS_TX :: STATUS 3985 */ 3986 /* AMS_TX :: STATUS :: ams_tx_sts [15:00] */ 3987 #define AMS_TX_STATUS_AMS_TX_STS_MASK 0xffff 3988 #define AMS_TX_STATUS_AMS_TX_STS_ALIGN 0 3989 #define AMS_TX_STATUS_AMS_TX_STS_BITS 16 3990 #define AMS_TX_STATUS_AMS_TX_STS_SHIFT 0 3991 3992 3993 /**************************************************************************** 3994 * eagle_tsc_ams_blk_AMS_COM 3995 */ 3996 /**************************************************************************** 3997 * AMS_COM :: CONTROL_0 3998 */ 3999 /* AMS_COM :: CONTROL_0 :: ams_pll_cal_aux [15:12] */ 4000 #define AMS_COM_CONTROL_0_AMS_PLL_CAL_AUX_MASK 0xf000 4001 #define AMS_COM_CONTROL_0_AMS_PLL_CAL_AUX_ALIGN 0 4002 #define AMS_COM_CONTROL_0_AMS_PLL_CAL_AUX_BITS 4 4003 #define AMS_COM_CONTROL_0_AMS_PLL_CAL_AUX_SHIFT 12 4004 4005 /* AMS_COM :: CONTROL_0 :: ams_pll_cal_off [11:11] */ 4006 #define AMS_COM_CONTROL_0_AMS_PLL_CAL_OFF_MASK 0x0800 4007 #define AMS_COM_CONTROL_0_AMS_PLL_CAL_OFF_ALIGN 0 4008 #define AMS_COM_CONTROL_0_AMS_PLL_CAL_OFF_BITS 1 4009 #define AMS_COM_CONTROL_0_AMS_PLL_CAL_OFF_SHIFT 11 4010 4011 /* AMS_COM :: CONTROL_0 :: ams_pll_imode_iclkidrv1 [10:10] */ 4012 #define AMS_COM_CONTROL_0_AMS_PLL_IMODE_ICLKIDRV1_MASK 0x0400 4013 #define AMS_COM_CONTROL_0_AMS_PLL_IMODE_ICLKIDRV1_ALIGN 0 4014 #define AMS_COM_CONTROL_0_AMS_PLL_IMODE_ICLKIDRV1_BITS 1 4015 #define AMS_COM_CONTROL_0_AMS_PLL_IMODE_ICLKIDRV1_SHIFT 10 4016 4017 /* AMS_COM :: CONTROL_0 :: ams_pll_imax_iclkidrv1 [09:09] */ 4018 #define AMS_COM_CONTROL_0_AMS_PLL_IMAX_ICLKIDRV1_MASK 0x0200 4019 #define AMS_COM_CONTROL_0_AMS_PLL_IMAX_ICLKIDRV1_ALIGN 0 4020 #define AMS_COM_CONTROL_0_AMS_PLL_IMAX_ICLKIDRV1_BITS 1 4021 #define AMS_COM_CONTROL_0_AMS_PLL_IMAX_ICLKIDRV1_SHIFT 9 4022 4023 /* AMS_COM :: CONTROL_0 :: ams_pll_imin_iclkidrv1 [08:08] */ 4024 #define AMS_COM_CONTROL_0_AMS_PLL_IMIN_ICLKIDRV1_MASK 0x0100 4025 #define AMS_COM_CONTROL_0_AMS_PLL_IMIN_ICLKIDRV1_ALIGN 0 4026 #define AMS_COM_CONTROL_0_AMS_PLL_IMIN_ICLKIDRV1_BITS 1 4027 #define AMS_COM_CONTROL_0_AMS_PLL_IMIN_ICLKIDRV1_SHIFT 8 4028 4029 /* AMS_COM :: CONTROL_0 :: ams_pll_imode_ickgen [07:07] */ 4030 #define AMS_COM_CONTROL_0_AMS_PLL_IMODE_ICKGEN_MASK 0x0080 4031 #define AMS_COM_CONTROL_0_AMS_PLL_IMODE_ICKGEN_ALIGN 0 4032 #define AMS_COM_CONTROL_0_AMS_PLL_IMODE_ICKGEN_BITS 1 4033 #define AMS_COM_CONTROL_0_AMS_PLL_IMODE_ICKGEN_SHIFT 7 4034 4035 /* AMS_COM :: CONTROL_0 :: ams_pll_imax_ickgen [06:06] */ 4036 #define AMS_COM_CONTROL_0_AMS_PLL_IMAX_ICKGEN_MASK 0x0040 4037 #define AMS_COM_CONTROL_0_AMS_PLL_IMAX_ICKGEN_ALIGN 0 4038 #define AMS_COM_CONTROL_0_AMS_PLL_IMAX_ICKGEN_BITS 1 4039 #define AMS_COM_CONTROL_0_AMS_PLL_IMAX_ICKGEN_SHIFT 6 4040 4041 /* AMS_COM :: CONTROL_0 :: ams_pll_imin_ickgen [05:05] */ 4042 #define AMS_COM_CONTROL_0_AMS_PLL_IMIN_ICKGEN_MASK 0x0020 4043 #define AMS_COM_CONTROL_0_AMS_PLL_IMIN_ICKGEN_ALIGN 0 4044 #define AMS_COM_CONTROL_0_AMS_PLL_IMIN_ICKGEN_BITS 1 4045 #define AMS_COM_CONTROL_0_AMS_PLL_IMIN_ICKGEN_SHIFT 5 4046 4047 /* AMS_COM :: CONTROL_0 :: ams_pll_imode_iclkint [04:04] */ 4048 #define AMS_COM_CONTROL_0_AMS_PLL_IMODE_ICLKINT_MASK 0x0010 4049 #define AMS_COM_CONTROL_0_AMS_PLL_IMODE_ICLKINT_ALIGN 0 4050 #define AMS_COM_CONTROL_0_AMS_PLL_IMODE_ICLKINT_BITS 1 4051 #define AMS_COM_CONTROL_0_AMS_PLL_IMODE_ICLKINT_SHIFT 4 4052 4053 /* AMS_COM :: CONTROL_0 :: ams_pll_imax_iclkint [03:03] */ 4054 #define AMS_COM_CONTROL_0_AMS_PLL_IMAX_ICLKINT_MASK 0x0008 4055 #define AMS_COM_CONTROL_0_AMS_PLL_IMAX_ICLKINT_ALIGN 0 4056 #define AMS_COM_CONTROL_0_AMS_PLL_IMAX_ICLKINT_BITS 1 4057 #define AMS_COM_CONTROL_0_AMS_PLL_IMAX_ICLKINT_SHIFT 3 4058 4059 /* AMS_COM :: CONTROL_0 :: ams_pll_imin_iclkint [02:02] */ 4060 #define AMS_COM_CONTROL_0_AMS_PLL_IMIN_ICLKINT_MASK 0x0004 4061 #define AMS_COM_CONTROL_0_AMS_PLL_IMIN_ICLKINT_ALIGN 0 4062 #define AMS_COM_CONTROL_0_AMS_PLL_IMIN_ICLKINT_BITS 1 4063 #define AMS_COM_CONTROL_0_AMS_PLL_IMIN_ICLKINT_SHIFT 2 4064 4065 /* AMS_COM :: CONTROL_0 :: ams_pll_txcg_vddr_bgb [01:01] */ 4066 #define AMS_COM_CONTROL_0_AMS_PLL_TXCG_VDDR_BGB_MASK 0x0002 4067 #define AMS_COM_CONTROL_0_AMS_PLL_TXCG_VDDR_BGB_ALIGN 0 4068 #define AMS_COM_CONTROL_0_AMS_PLL_TXCG_VDDR_BGB_BITS 1 4069 #define AMS_COM_CONTROL_0_AMS_PLL_TXCG_VDDR_BGB_SHIFT 1 4070 4071 /* AMS_COM :: CONTROL_0 :: ams_pll_lowpwr_6g [00:00] */ 4072 #define AMS_COM_CONTROL_0_AMS_PLL_LOWPWR_6G_MASK 0x0001 4073 #define AMS_COM_CONTROL_0_AMS_PLL_LOWPWR_6G_ALIGN 0 4074 #define AMS_COM_CONTROL_0_AMS_PLL_LOWPWR_6G_BITS 1 4075 #define AMS_COM_CONTROL_0_AMS_PLL_LOWPWR_6G_SHIFT 0 4076 4077 4078 /**************************************************************************** 4079 * AMS_COM :: CONTROL_1 4080 */ 4081 /* AMS_COM :: CONTROL_1 :: ams_pll_enable_ftune [15:15] */ 4082 #define AMS_COM_CONTROL_1_AMS_PLL_ENABLE_FTUNE_MASK 0x8000 4083 #define AMS_COM_CONTROL_1_AMS_PLL_ENABLE_FTUNE_ALIGN 0 4084 #define AMS_COM_CONTROL_1_AMS_PLL_ENABLE_FTUNE_BITS 1 4085 #define AMS_COM_CONTROL_1_AMS_PLL_ENABLE_FTUNE_SHIFT 15 4086 4087 /* AMS_COM :: CONTROL_1 :: ams_pll_reset [14:14] */ 4088 #define AMS_COM_CONTROL_1_AMS_PLL_RESET_MASK 0x4000 4089 #define AMS_COM_CONTROL_1_AMS_PLL_RESET_ALIGN 0 4090 #define AMS_COM_CONTROL_1_AMS_PLL_RESET_BITS 1 4091 #define AMS_COM_CONTROL_1_AMS_PLL_RESET_SHIFT 14 4092 4093 /* AMS_COM :: CONTROL_1 :: ams_pll_ivco [13:11] */ 4094 #define AMS_COM_CONTROL_1_AMS_PLL_IVCO_MASK 0x3800 4095 #define AMS_COM_CONTROL_1_AMS_PLL_IVCO_ALIGN 0 4096 #define AMS_COM_CONTROL_1_AMS_PLL_IVCO_BITS 3 4097 #define AMS_COM_CONTROL_1_AMS_PLL_IVCO_SHIFT 11 4098 4099 /* AMS_COM :: CONTROL_1 :: ams_pll_vco_imax [10:10] */ 4100 #define AMS_COM_CONTROL_1_AMS_PLL_VCO_IMAX_MASK 0x0400 4101 #define AMS_COM_CONTROL_1_AMS_PLL_VCO_IMAX_ALIGN 0 4102 #define AMS_COM_CONTROL_1_AMS_PLL_VCO_IMAX_BITS 1 4103 #define AMS_COM_CONTROL_1_AMS_PLL_VCO_IMAX_SHIFT 10 4104 4105 /* AMS_COM :: CONTROL_1 :: ams_pll_vcoictrl [09:08] */ 4106 #define AMS_COM_CONTROL_1_AMS_PLL_VCOICTRL_MASK 0x0300 4107 #define AMS_COM_CONTROL_1_AMS_PLL_VCOICTRL_ALIGN 0 4108 #define AMS_COM_CONTROL_1_AMS_PLL_VCOICTRL_BITS 2 4109 #define AMS_COM_CONTROL_1_AMS_PLL_VCOICTRL_SHIFT 8 4110 4111 /* AMS_COM :: CONTROL_1 :: ams_pll_vco_div4 [07:07] */ 4112 #define AMS_COM_CONTROL_1_AMS_PLL_VCO_DIV4_MASK 0x0080 4113 #define AMS_COM_CONTROL_1_AMS_PLL_VCO_DIV4_ALIGN 0 4114 #define AMS_COM_CONTROL_1_AMS_PLL_VCO_DIV4_BITS 1 4115 #define AMS_COM_CONTROL_1_AMS_PLL_VCO_DIV4_SHIFT 7 4116 4117 /* AMS_COM :: CONTROL_1 :: ams_pll_vco_div2 [06:06] */ 4118 #define AMS_COM_CONTROL_1_AMS_PLL_VCO_DIV2_MASK 0x0040 4119 #define AMS_COM_CONTROL_1_AMS_PLL_VCO_DIV2_ALIGN 0 4120 #define AMS_COM_CONTROL_1_AMS_PLL_VCO_DIV2_BITS 1 4121 #define AMS_COM_CONTROL_1_AMS_PLL_VCO_DIV2_SHIFT 6 4122 4123 /* AMS_COM :: CONTROL_1 :: ams_pll_fp3_ctrl [05:04] */ 4124 #define AMS_COM_CONTROL_1_AMS_PLL_FP3_CTRL_MASK 0x0030 4125 #define AMS_COM_CONTROL_1_AMS_PLL_FP3_CTRL_ALIGN 0 4126 #define AMS_COM_CONTROL_1_AMS_PLL_FP3_CTRL_BITS 2 4127 #define AMS_COM_CONTROL_1_AMS_PLL_FP3_CTRL_SHIFT 4 4128 4129 /* AMS_COM :: CONTROL_1 :: ams_pll_fp3_rh [03:03] */ 4130 #define AMS_COM_CONTROL_1_AMS_PLL_FP3_RH_MASK 0x0008 4131 #define AMS_COM_CONTROL_1_AMS_PLL_FP3_RH_ALIGN 0 4132 #define AMS_COM_CONTROL_1_AMS_PLL_FP3_RH_BITS 1 4133 #define AMS_COM_CONTROL_1_AMS_PLL_FP3_RH_SHIFT 3 4134 4135 /* AMS_COM :: CONTROL_1 :: ams_pll_spare_18 [02:02] */ 4136 #define AMS_COM_CONTROL_1_AMS_PLL_SPARE_18_MASK 0x0004 4137 #define AMS_COM_CONTROL_1_AMS_PLL_SPARE_18_ALIGN 0 4138 #define AMS_COM_CONTROL_1_AMS_PLL_SPARE_18_BITS 1 4139 #define AMS_COM_CONTROL_1_AMS_PLL_SPARE_18_SHIFT 2 4140 4141 /* AMS_COM :: CONTROL_1 :: ams_pll_dblr_ctrl [01:00] */ 4142 #define AMS_COM_CONTROL_1_AMS_PLL_DBLR_CTRL_MASK 0x0003 4143 #define AMS_COM_CONTROL_1_AMS_PLL_DBLR_CTRL_ALIGN 0 4144 #define AMS_COM_CONTROL_1_AMS_PLL_DBLR_CTRL_BITS 2 4145 #define AMS_COM_CONTROL_1_AMS_PLL_DBLR_CTRL_SHIFT 0 4146 4147 4148 /**************************************************************************** 4149 * AMS_COM :: CONTROL_2 4150 */ 4151 /* AMS_COM :: CONTROL_2 :: ams_pll_imax_ick [15:15] */ 4152 #define AMS_COM_CONTROL_2_AMS_PLL_IMAX_ICK_MASK 0x8000 4153 #define AMS_COM_CONTROL_2_AMS_PLL_IMAX_ICK_ALIGN 0 4154 #define AMS_COM_CONTROL_2_AMS_PLL_IMAX_ICK_BITS 1 4155 #define AMS_COM_CONTROL_2_AMS_PLL_IMAX_ICK_SHIFT 15 4156 4157 /* AMS_COM :: CONTROL_2 :: ams_pll_imode_ick [14:14] */ 4158 #define AMS_COM_CONTROL_2_AMS_PLL_IMODE_ICK_MASK 0x4000 4159 #define AMS_COM_CONTROL_2_AMS_PLL_IMODE_ICK_ALIGN 0 4160 #define AMS_COM_CONTROL_2_AMS_PLL_IMODE_ICK_BITS 1 4161 #define AMS_COM_CONTROL_2_AMS_PLL_IMODE_ICK_SHIFT 14 4162 4163 /* AMS_COM :: CONTROL_2 :: ams_pll_imin_ick [13:13] */ 4164 #define AMS_COM_CONTROL_2_AMS_PLL_IMIN_ICK_MASK 0x2000 4165 #define AMS_COM_CONTROL_2_AMS_PLL_IMIN_ICK_ALIGN 0 4166 #define AMS_COM_CONTROL_2_AMS_PLL_IMIN_ICK_BITS 1 4167 #define AMS_COM_CONTROL_2_AMS_PLL_IMIN_ICK_SHIFT 13 4168 4169 /* AMS_COM :: CONTROL_2 :: ams_pll_imax_icp [12:12] */ 4170 #define AMS_COM_CONTROL_2_AMS_PLL_IMAX_ICP_MASK 0x1000 4171 #define AMS_COM_CONTROL_2_AMS_PLL_IMAX_ICP_ALIGN 0 4172 #define AMS_COM_CONTROL_2_AMS_PLL_IMAX_ICP_BITS 1 4173 #define AMS_COM_CONTROL_2_AMS_PLL_IMAX_ICP_SHIFT 12 4174 4175 /* AMS_COM :: CONTROL_2 :: ams_pll_imode_icp [11:11] */ 4176 #define AMS_COM_CONTROL_2_AMS_PLL_IMODE_ICP_MASK 0x0800 4177 #define AMS_COM_CONTROL_2_AMS_PLL_IMODE_ICP_ALIGN 0 4178 #define AMS_COM_CONTROL_2_AMS_PLL_IMODE_ICP_BITS 1 4179 #define AMS_COM_CONTROL_2_AMS_PLL_IMODE_ICP_SHIFT 11 4180 4181 /* AMS_COM :: CONTROL_2 :: ams_pll_imin_icp [10:10] */ 4182 #define AMS_COM_CONTROL_2_AMS_PLL_IMIN_ICP_MASK 0x0400 4183 #define AMS_COM_CONTROL_2_AMS_PLL_IMIN_ICP_ALIGN 0 4184 #define AMS_COM_CONTROL_2_AMS_PLL_IMIN_ICP_BITS 1 4185 #define AMS_COM_CONTROL_2_AMS_PLL_IMIN_ICP_SHIFT 10 4186 4187 /* AMS_COM :: CONTROL_2 :: ams_pll_imax_ibias [09:09] */ 4188 #define AMS_COM_CONTROL_2_AMS_PLL_IMAX_IBIAS_MASK 0x0200 4189 #define AMS_COM_CONTROL_2_AMS_PLL_IMAX_IBIAS_ALIGN 0 4190 #define AMS_COM_CONTROL_2_AMS_PLL_IMAX_IBIAS_BITS 1 4191 #define AMS_COM_CONTROL_2_AMS_PLL_IMAX_IBIAS_SHIFT 9 4192 4193 /* AMS_COM :: CONTROL_2 :: ams_pll_imode_ibias [08:08] */ 4194 #define AMS_COM_CONTROL_2_AMS_PLL_IMODE_IBIAS_MASK 0x0100 4195 #define AMS_COM_CONTROL_2_AMS_PLL_IMODE_IBIAS_ALIGN 0 4196 #define AMS_COM_CONTROL_2_AMS_PLL_IMODE_IBIAS_BITS 1 4197 #define AMS_COM_CONTROL_2_AMS_PLL_IMODE_IBIAS_SHIFT 8 4198 4199 /* AMS_COM :: CONTROL_2 :: ams_pll_imin_ibias [07:07] */ 4200 #define AMS_COM_CONTROL_2_AMS_PLL_IMIN_IBIAS_MASK 0x0080 4201 #define AMS_COM_CONTROL_2_AMS_PLL_IMIN_IBIAS_ALIGN 0 4202 #define AMS_COM_CONTROL_2_AMS_PLL_IMIN_IBIAS_BITS 1 4203 #define AMS_COM_CONTROL_2_AMS_PLL_IMIN_IBIAS_SHIFT 7 4204 4205 /* AMS_COM :: CONTROL_2 :: ams_pll_refh_pll [06:06] */ 4206 #define AMS_COM_CONTROL_2_AMS_PLL_REFH_PLL_MASK 0x0040 4207 #define AMS_COM_CONTROL_2_AMS_PLL_REFH_PLL_ALIGN 0 4208 #define AMS_COM_CONTROL_2_AMS_PLL_REFH_PLL_BITS 1 4209 #define AMS_COM_CONTROL_2_AMS_PLL_REFH_PLL_SHIFT 6 4210 4211 /* AMS_COM :: CONTROL_2 :: ams_pll_refl_pll [05:05] */ 4212 #define AMS_COM_CONTROL_2_AMS_PLL_REFL_PLL_MASK 0x0020 4213 #define AMS_COM_CONTROL_2_AMS_PLL_REFL_PLL_ALIGN 0 4214 #define AMS_COM_CONTROL_2_AMS_PLL_REFL_PLL_BITS 1 4215 #define AMS_COM_CONTROL_2_AMS_PLL_REFL_PLL_SHIFT 5 4216 4217 /* AMS_COM :: CONTROL_2 :: ams_pll_iqp [04:01] */ 4218 #define AMS_COM_CONTROL_2_AMS_PLL_IQP_MASK 0x001e 4219 #define AMS_COM_CONTROL_2_AMS_PLL_IQP_ALIGN 0 4220 #define AMS_COM_CONTROL_2_AMS_PLL_IQP_BITS 4 4221 #define AMS_COM_CONTROL_2_AMS_PLL_IQP_SHIFT 1 4222 4223 /* AMS_COM :: CONTROL_2 :: ams_pll_en_hrz [00:00] */ 4224 #define AMS_COM_CONTROL_2_AMS_PLL_EN_HRZ_MASK 0x0001 4225 #define AMS_COM_CONTROL_2_AMS_PLL_EN_HRZ_ALIGN 0 4226 #define AMS_COM_CONTROL_2_AMS_PLL_EN_HRZ_BITS 1 4227 #define AMS_COM_CONTROL_2_AMS_PLL_EN_HRZ_SHIFT 0 4228 4229 4230 /**************************************************************************** 4231 * AMS_COM :: CONTROL_3 4232 */ 4233 /* AMS_COM :: CONTROL_3 :: ams_pll_test_rx [15:15] */ 4234 #define AMS_COM_CONTROL_3_AMS_PLL_TEST_RX_MASK 0x8000 4235 #define AMS_COM_CONTROL_3_AMS_PLL_TEST_RX_ALIGN 0 4236 #define AMS_COM_CONTROL_3_AMS_PLL_TEST_RX_BITS 1 4237 #define AMS_COM_CONTROL_3_AMS_PLL_TEST_RX_SHIFT 15 4238 4239 /* AMS_COM :: CONTROL_3 :: ams_pll_test_pll [14:14] */ 4240 #define AMS_COM_CONTROL_3_AMS_PLL_TEST_PLL_MASK 0x4000 4241 #define AMS_COM_CONTROL_3_AMS_PLL_TEST_PLL_ALIGN 0 4242 #define AMS_COM_CONTROL_3_AMS_PLL_TEST_PLL_BITS 1 4243 #define AMS_COM_CONTROL_3_AMS_PLL_TEST_PLL_SHIFT 14 4244 4245 /* AMS_COM :: CONTROL_3 :: ams_pll_test_vc [13:13] */ 4246 #define AMS_COM_CONTROL_3_AMS_PLL_TEST_VC_MASK 0x2000 4247 #define AMS_COM_CONTROL_3_AMS_PLL_TEST_VC_ALIGN 0 4248 #define AMS_COM_CONTROL_3_AMS_PLL_TEST_VC_BITS 1 4249 #define AMS_COM_CONTROL_3_AMS_PLL_TEST_VC_SHIFT 13 4250 4251 /* AMS_COM :: CONTROL_3 :: ams_pll_test_vref [12:12] */ 4252 #define AMS_COM_CONTROL_3_AMS_PLL_TEST_VREF_MASK 0x1000 4253 #define AMS_COM_CONTROL_3_AMS_PLL_TEST_VREF_ALIGN 0 4254 #define AMS_COM_CONTROL_3_AMS_PLL_TEST_VREF_BITS 1 4255 #define AMS_COM_CONTROL_3_AMS_PLL_TEST_VREF_SHIFT 12 4256 4257 /* AMS_COM :: CONTROL_3 :: ams_pll_imax_iop [11:11] */ 4258 #define AMS_COM_CONTROL_3_AMS_PLL_IMAX_IOP_MASK 0x0800 4259 #define AMS_COM_CONTROL_3_AMS_PLL_IMAX_IOP_ALIGN 0 4260 #define AMS_COM_CONTROL_3_AMS_PLL_IMAX_IOP_BITS 1 4261 #define AMS_COM_CONTROL_3_AMS_PLL_IMAX_IOP_SHIFT 11 4262 4263 /* AMS_COM :: CONTROL_3 :: ams_pll_imode_iop [10:10] */ 4264 #define AMS_COM_CONTROL_3_AMS_PLL_IMODE_IOP_MASK 0x0400 4265 #define AMS_COM_CONTROL_3_AMS_PLL_IMODE_IOP_ALIGN 0 4266 #define AMS_COM_CONTROL_3_AMS_PLL_IMODE_IOP_BITS 1 4267 #define AMS_COM_CONTROL_3_AMS_PLL_IMODE_IOP_SHIFT 10 4268 4269 /* AMS_COM :: CONTROL_3 :: ams_pll_imin_iop [09:09] */ 4270 #define AMS_COM_CONTROL_3_AMS_PLL_IMIN_IOP_MASK 0x0200 4271 #define AMS_COM_CONTROL_3_AMS_PLL_IMIN_IOP_ALIGN 0 4272 #define AMS_COM_CONTROL_3_AMS_PLL_IMIN_IOP_BITS 1 4273 #define AMS_COM_CONTROL_3_AMS_PLL_IMIN_IOP_SHIFT 9 4274 4275 /* AMS_COM :: CONTROL_3 :: ams_pll_imax_icomp [08:08] */ 4276 #define AMS_COM_CONTROL_3_AMS_PLL_IMAX_ICOMP_MASK 0x0100 4277 #define AMS_COM_CONTROL_3_AMS_PLL_IMAX_ICOMP_ALIGN 0 4278 #define AMS_COM_CONTROL_3_AMS_PLL_IMAX_ICOMP_BITS 1 4279 #define AMS_COM_CONTROL_3_AMS_PLL_IMAX_ICOMP_SHIFT 8 4280 4281 /* AMS_COM :: CONTROL_3 :: ams_pll_imode_icomp [07:07] */ 4282 #define AMS_COM_CONTROL_3_AMS_PLL_IMODE_ICOMP_MASK 0x0080 4283 #define AMS_COM_CONTROL_3_AMS_PLL_IMODE_ICOMP_ALIGN 0 4284 #define AMS_COM_CONTROL_3_AMS_PLL_IMODE_ICOMP_BITS 1 4285 #define AMS_COM_CONTROL_3_AMS_PLL_IMODE_ICOMP_SHIFT 7 4286 4287 /* AMS_COM :: CONTROL_3 :: ams_pll_imin_icomp [06:06] */ 4288 #define AMS_COM_CONTROL_3_AMS_PLL_IMIN_ICOMP_MASK 0x0040 4289 #define AMS_COM_CONTROL_3_AMS_PLL_IMIN_ICOMP_ALIGN 0 4290 #define AMS_COM_CONTROL_3_AMS_PLL_IMIN_ICOMP_BITS 1 4291 #define AMS_COM_CONTROL_3_AMS_PLL_IMIN_ICOMP_SHIFT 6 4292 4293 /* AMS_COM :: CONTROL_3 :: ams_pll_imax_icml [05:05] */ 4294 #define AMS_COM_CONTROL_3_AMS_PLL_IMAX_ICML_MASK 0x0020 4295 #define AMS_COM_CONTROL_3_AMS_PLL_IMAX_ICML_ALIGN 0 4296 #define AMS_COM_CONTROL_3_AMS_PLL_IMAX_ICML_BITS 1 4297 #define AMS_COM_CONTROL_3_AMS_PLL_IMAX_ICML_SHIFT 5 4298 4299 /* AMS_COM :: CONTROL_3 :: ams_pll_imode_icml [04:04] */ 4300 #define AMS_COM_CONTROL_3_AMS_PLL_IMODE_ICML_MASK 0x0010 4301 #define AMS_COM_CONTROL_3_AMS_PLL_IMODE_ICML_ALIGN 0 4302 #define AMS_COM_CONTROL_3_AMS_PLL_IMODE_ICML_BITS 1 4303 #define AMS_COM_CONTROL_3_AMS_PLL_IMODE_ICML_SHIFT 4 4304 4305 /* AMS_COM :: CONTROL_3 :: ams_pll_imin_icml [03:03] */ 4306 #define AMS_COM_CONTROL_3_AMS_PLL_IMIN_ICML_MASK 0x0008 4307 #define AMS_COM_CONTROL_3_AMS_PLL_IMIN_ICML_ALIGN 0 4308 #define AMS_COM_CONTROL_3_AMS_PLL_IMIN_ICML_BITS 1 4309 #define AMS_COM_CONTROL_3_AMS_PLL_IMIN_ICML_SHIFT 3 4310 4311 /* AMS_COM :: CONTROL_3 :: ams_pll_imax_i10gbuf [02:02] */ 4312 #define AMS_COM_CONTROL_3_AMS_PLL_IMAX_I10GBUF_MASK 0x0004 4313 #define AMS_COM_CONTROL_3_AMS_PLL_IMAX_I10GBUF_ALIGN 0 4314 #define AMS_COM_CONTROL_3_AMS_PLL_IMAX_I10GBUF_BITS 1 4315 #define AMS_COM_CONTROL_3_AMS_PLL_IMAX_I10GBUF_SHIFT 2 4316 4317 /* AMS_COM :: CONTROL_3 :: ams_pll_imode_i10gbuf [01:01] */ 4318 #define AMS_COM_CONTROL_3_AMS_PLL_IMODE_I10GBUF_MASK 0x0002 4319 #define AMS_COM_CONTROL_3_AMS_PLL_IMODE_I10GBUF_ALIGN 0 4320 #define AMS_COM_CONTROL_3_AMS_PLL_IMODE_I10GBUF_BITS 1 4321 #define AMS_COM_CONTROL_3_AMS_PLL_IMODE_I10GBUF_SHIFT 1 4322 4323 /* AMS_COM :: CONTROL_3 :: ams_pll_imin_i10gbuf [00:00] */ 4324 #define AMS_COM_CONTROL_3_AMS_PLL_IMIN_I10GBUF_MASK 0x0001 4325 #define AMS_COM_CONTROL_3_AMS_PLL_IMIN_I10GBUF_ALIGN 0 4326 #define AMS_COM_CONTROL_3_AMS_PLL_IMIN_I10GBUF_BITS 1 4327 #define AMS_COM_CONTROL_3_AMS_PLL_IMIN_I10GBUF_SHIFT 0 4328 4329 4330 /**************************************************************************** 4331 * AMS_COM :: CONTROL_4 4332 */ 4333 /* AMS_COM :: CONTROL_4 :: ams_pll_force_rescal [15:15] */ 4334 #define AMS_COM_CONTROL_4_AMS_PLL_FORCE_RESCAL_MASK 0x8000 4335 #define AMS_COM_CONTROL_4_AMS_PLL_FORCE_RESCAL_ALIGN 0 4336 #define AMS_COM_CONTROL_4_AMS_PLL_FORCE_RESCAL_BITS 1 4337 #define AMS_COM_CONTROL_4_AMS_PLL_FORCE_RESCAL_SHIFT 15 4338 4339 /* AMS_COM :: CONTROL_4 :: ams_pll_force_kvh_bw [14:14] */ 4340 #define AMS_COM_CONTROL_4_AMS_PLL_FORCE_KVH_BW_MASK 0x4000 4341 #define AMS_COM_CONTROL_4_AMS_PLL_FORCE_KVH_BW_ALIGN 0 4342 #define AMS_COM_CONTROL_4_AMS_PLL_FORCE_KVH_BW_BITS 1 4343 #define AMS_COM_CONTROL_4_AMS_PLL_FORCE_KVH_BW_SHIFT 14 4344 4345 /* AMS_COM :: CONTROL_4 :: ams_pll_kvh_force [13:12] */ 4346 #define AMS_COM_CONTROL_4_AMS_PLL_KVH_FORCE_MASK 0x3000 4347 #define AMS_COM_CONTROL_4_AMS_PLL_KVH_FORCE_ALIGN 0 4348 #define AMS_COM_CONTROL_4_AMS_PLL_KVH_FORCE_BITS 2 4349 #define AMS_COM_CONTROL_4_AMS_PLL_KVH_FORCE_SHIFT 12 4350 4351 /* AMS_COM :: CONTROL_4 :: ams_pll_vddr_bgb [11:11] */ 4352 #define AMS_COM_CONTROL_4_AMS_PLL_VDDR_BGB_MASK 0x0800 4353 #define AMS_COM_CONTROL_4_AMS_PLL_VDDR_BGB_ALIGN 0 4354 #define AMS_COM_CONTROL_4_AMS_PLL_VDDR_BGB_BITS 1 4355 #define AMS_COM_CONTROL_4_AMS_PLL_VDDR_BGB_SHIFT 11 4356 4357 /* AMS_COM :: CONTROL_4 :: ams_pll_comp_vth [10:10] */ 4358 #define AMS_COM_CONTROL_4_AMS_PLL_COMP_VTH_MASK 0x0400 4359 #define AMS_COM_CONTROL_4_AMS_PLL_COMP_VTH_ALIGN 0 4360 #define AMS_COM_CONTROL_4_AMS_PLL_COMP_VTH_BITS 1 4361 #define AMS_COM_CONTROL_4_AMS_PLL_COMP_VTH_SHIFT 10 4362 4363 /* AMS_COM :: CONTROL_4 :: ams_pll_2rx_clkbw [09:08] */ 4364 #define AMS_COM_CONTROL_4_AMS_PLL_2RX_CLKBW_MASK 0x0300 4365 #define AMS_COM_CONTROL_4_AMS_PLL_2RX_CLKBW_ALIGN 0 4366 #define AMS_COM_CONTROL_4_AMS_PLL_2RX_CLKBW_BITS 2 4367 #define AMS_COM_CONTROL_4_AMS_PLL_2RX_CLKBW_SHIFT 8 4368 4369 /* AMS_COM :: CONTROL_4 :: ams_pll_bgr_ctatadj [07:04] */ 4370 #define AMS_COM_CONTROL_4_AMS_PLL_BGR_CTATADJ_MASK 0x00f0 4371 #define AMS_COM_CONTROL_4_AMS_PLL_BGR_CTATADJ_ALIGN 0 4372 #define AMS_COM_CONTROL_4_AMS_PLL_BGR_CTATADJ_BITS 4 4373 #define AMS_COM_CONTROL_4_AMS_PLL_BGR_CTATADJ_SHIFT 4 4374 4375 /* AMS_COM :: CONTROL_4 :: ams_pll_bgr_ptatadj [03:00] */ 4376 #define AMS_COM_CONTROL_4_AMS_PLL_BGR_PTATADJ_MASK 0x000f 4377 #define AMS_COM_CONTROL_4_AMS_PLL_BGR_PTATADJ_ALIGN 0 4378 #define AMS_COM_CONTROL_4_AMS_PLL_BGR_PTATADJ_BITS 4 4379 #define AMS_COM_CONTROL_4_AMS_PLL_BGR_PTATADJ_SHIFT 0 4380 4381 4382 /**************************************************************************** 4383 * AMS_COM :: CONTROL_5 4384 */ 4385 /* AMS_COM :: CONTROL_5 :: ams_pll_bgcalr_ptatadj [15:11] */ 4386 #define AMS_COM_CONTROL_5_AMS_PLL_BGCALR_PTATADJ_MASK 0xf800 4387 #define AMS_COM_CONTROL_5_AMS_PLL_BGCALR_PTATADJ_ALIGN 0 4388 #define AMS_COM_CONTROL_5_AMS_PLL_BGCALR_PTATADJ_BITS 5 4389 #define AMS_COM_CONTROL_5_AMS_PLL_BGCALR_PTATADJ_SHIFT 11 4390 4391 /* AMS_COM :: CONTROL_5 :: ams_pll_bgcalr_ctatadj [10:06] */ 4392 #define AMS_COM_CONTROL_5_AMS_PLL_BGCALR_CTATADJ_MASK 0x07c0 4393 #define AMS_COM_CONTROL_5_AMS_PLL_BGCALR_CTATADJ_ALIGN 0 4394 #define AMS_COM_CONTROL_5_AMS_PLL_BGCALR_CTATADJ_BITS 5 4395 #define AMS_COM_CONTROL_5_AMS_PLL_BGCALR_CTATADJ_SHIFT 6 4396 4397 /* AMS_COM :: CONTROL_5 :: ams_pll_test_pnp [05:04] */ 4398 #define AMS_COM_CONTROL_5_AMS_PLL_TEST_PNP_MASK 0x0030 4399 #define AMS_COM_CONTROL_5_AMS_PLL_TEST_PNP_ALIGN 0 4400 #define AMS_COM_CONTROL_5_AMS_PLL_TEST_PNP_BITS 2 4401 #define AMS_COM_CONTROL_5_AMS_PLL_TEST_PNP_SHIFT 4 4402 4403 /* AMS_COM :: CONTROL_5 :: ams_pll_vbypass [03:03] */ 4404 #define AMS_COM_CONTROL_5_AMS_PLL_VBYPASS_MASK 0x0008 4405 #define AMS_COM_CONTROL_5_AMS_PLL_VBYPASS_ALIGN 0 4406 #define AMS_COM_CONTROL_5_AMS_PLL_VBYPASS_BITS 1 4407 #define AMS_COM_CONTROL_5_AMS_PLL_VBYPASS_SHIFT 3 4408 4409 /* AMS_COM :: CONTROL_5 :: ams_pll_bgint [02:02] */ 4410 #define AMS_COM_CONTROL_5_AMS_PLL_BGINT_MASK 0x0004 4411 #define AMS_COM_CONTROL_5_AMS_PLL_BGINT_ALIGN 0 4412 #define AMS_COM_CONTROL_5_AMS_PLL_BGINT_BITS 1 4413 #define AMS_COM_CONTROL_5_AMS_PLL_BGINT_SHIFT 2 4414 4415 /* AMS_COM :: CONTROL_5 :: ams_pll_bgip [01:01] */ 4416 #define AMS_COM_CONTROL_5_AMS_PLL_BGIP_MASK 0x0002 4417 #define AMS_COM_CONTROL_5_AMS_PLL_BGIP_ALIGN 0 4418 #define AMS_COM_CONTROL_5_AMS_PLL_BGIP_BITS 1 4419 #define AMS_COM_CONTROL_5_AMS_PLL_BGIP_SHIFT 1 4420 4421 /* AMS_COM :: CONTROL_5 :: ams_pll_max_test_port_ampl [00:00] */ 4422 #define AMS_COM_CONTROL_5_AMS_PLL_MAX_TEST_PORT_AMPL_MASK 0x0001 4423 #define AMS_COM_CONTROL_5_AMS_PLL_MAX_TEST_PORT_AMPL_ALIGN 0 4424 #define AMS_COM_CONTROL_5_AMS_PLL_MAX_TEST_PORT_AMPL_BITS 1 4425 #define AMS_COM_CONTROL_5_AMS_PLL_MAX_TEST_PORT_AMPL_SHIFT 0 4426 4427 4428 /**************************************************************************** 4429 * AMS_COM :: CONTROL_6 4430 */ 4431 /* AMS_COM :: CONTROL_6 :: ams_pll_mix2p1cr_ptatadj [15:11] */ 4432 #define AMS_COM_CONTROL_6_AMS_PLL_MIX2P1CR_PTATADJ_MASK 0xf800 4433 #define AMS_COM_CONTROL_6_AMS_PLL_MIX2P1CR_PTATADJ_ALIGN 0 4434 #define AMS_COM_CONTROL_6_AMS_PLL_MIX2P1CR_PTATADJ_BITS 5 4435 #define AMS_COM_CONTROL_6_AMS_PLL_MIX2P1CR_PTATADJ_SHIFT 11 4436 4437 /* AMS_COM :: CONTROL_6 :: ams_pll_mix2p1cr_ctatadj [10:06] */ 4438 #define AMS_COM_CONTROL_6_AMS_PLL_MIX2P1CR_CTATADJ_MASK 0x07c0 4439 #define AMS_COM_CONTROL_6_AMS_PLL_MIX2P1CR_CTATADJ_ALIGN 0 4440 #define AMS_COM_CONTROL_6_AMS_PLL_MIX2P1CR_CTATADJ_BITS 5 4441 #define AMS_COM_CONTROL_6_AMS_PLL_MIX2P1CR_CTATADJ_SHIFT 6 4442 4443 /* AMS_COM :: CONTROL_6 :: ams_pll_refclk_doubler [05:05] */ 4444 #define AMS_COM_CONTROL_6_AMS_PLL_REFCLK_DOUBLER_MASK 0x0020 4445 #define AMS_COM_CONTROL_6_AMS_PLL_REFCLK_DOUBLER_ALIGN 0 4446 #define AMS_COM_CONTROL_6_AMS_PLL_REFCLK_DOUBLER_BITS 1 4447 #define AMS_COM_CONTROL_6_AMS_PLL_REFCLK_DOUBLER_SHIFT 5 4448 4449 /* AMS_COM :: CONTROL_6 :: ams_pll_spare_100 [04:04] */ 4450 #define AMS_COM_CONTROL_6_AMS_PLL_SPARE_100_MASK 0x0010 4451 #define AMS_COM_CONTROL_6_AMS_PLL_SPARE_100_ALIGN 0 4452 #define AMS_COM_CONTROL_6_AMS_PLL_SPARE_100_BITS 1 4453 #define AMS_COM_CONTROL_6_AMS_PLL_SPARE_100_SHIFT 4 4454 4455 /* AMS_COM :: CONTROL_6 :: ams_pll_pdf_ref_skew [03:03] */ 4456 #define AMS_COM_CONTROL_6_AMS_PLL_PDF_REF_SKEW_MASK 0x0008 4457 #define AMS_COM_CONTROL_6_AMS_PLL_PDF_REF_SKEW_ALIGN 0 4458 #define AMS_COM_CONTROL_6_AMS_PLL_PDF_REF_SKEW_BITS 1 4459 #define AMS_COM_CONTROL_6_AMS_PLL_PDF_REF_SKEW_SHIFT 3 4460 4461 /* AMS_COM :: CONTROL_6 :: ams_pll_pdf_fd_skew [02:02] */ 4462 #define AMS_COM_CONTROL_6_AMS_PLL_PDF_FD_SKEW_MASK 0x0004 4463 #define AMS_COM_CONTROL_6_AMS_PLL_PDF_FD_SKEW_ALIGN 0 4464 #define AMS_COM_CONTROL_6_AMS_PLL_PDF_FD_SKEW_BITS 1 4465 #define AMS_COM_CONTROL_6_AMS_PLL_PDF_FD_SKEW_SHIFT 2 4466 4467 /* AMS_COM :: CONTROL_6 :: ams_pll_pdf_skew_enlarge [01:01] */ 4468 #define AMS_COM_CONTROL_6_AMS_PLL_PDF_SKEW_ENLARGE_MASK 0x0002 4469 #define AMS_COM_CONTROL_6_AMS_PLL_PDF_SKEW_ENLARGE_ALIGN 0 4470 #define AMS_COM_CONTROL_6_AMS_PLL_PDF_SKEW_ENLARGE_BITS 1 4471 #define AMS_COM_CONTROL_6_AMS_PLL_PDF_SKEW_ENLARGE_SHIFT 1 4472 4473 /* AMS_COM :: CONTROL_6 :: ams_pll_test_fracn_en [00:00] */ 4474 #define AMS_COM_CONTROL_6_AMS_PLL_TEST_FRACN_EN_MASK 0x0001 4475 #define AMS_COM_CONTROL_6_AMS_PLL_TEST_FRACN_EN_ALIGN 0 4476 #define AMS_COM_CONTROL_6_AMS_PLL_TEST_FRACN_EN_BITS 1 4477 #define AMS_COM_CONTROL_6_AMS_PLL_TEST_FRACN_EN_SHIFT 0 4478 4479 4480 /**************************************************************************** 4481 * AMS_COM :: CONTROL_7 4482 */ 4483 /* AMS_COM :: CONTROL_7 :: ams_pll_fracn_div_l [15:00] */ 4484 #define AMS_COM_CONTROL_7_AMS_PLL_FRACN_DIV_L_MASK 0xffff 4485 #define AMS_COM_CONTROL_7_AMS_PLL_FRACN_DIV_L_ALIGN 0 4486 #define AMS_COM_CONTROL_7_AMS_PLL_FRACN_DIV_L_BITS 16 4487 #define AMS_COM_CONTROL_7_AMS_PLL_FRACN_DIV_L_SHIFT 0 4488 4489 4490 /**************************************************************************** 4491 * AMS_COM :: CONTROL_8 4492 */ 4493 /* AMS_COM :: CONTROL_8 :: ams_pll_fracn_sel [15:15] */ 4494 #define AMS_COM_CONTROL_8_AMS_PLL_FRACN_SEL_MASK 0x8000 4495 #define AMS_COM_CONTROL_8_AMS_PLL_FRACN_SEL_ALIGN 0 4496 #define AMS_COM_CONTROL_8_AMS_PLL_FRACN_SEL_BITS 1 4497 #define AMS_COM_CONTROL_8_AMS_PLL_FRACN_SEL_SHIFT 15 4498 4499 /* AMS_COM :: CONTROL_8 :: ams_pll_ditheren [14:14] */ 4500 #define AMS_COM_CONTROL_8_AMS_PLL_DITHEREN_MASK 0x4000 4501 #define AMS_COM_CONTROL_8_AMS_PLL_DITHEREN_ALIGN 0 4502 #define AMS_COM_CONTROL_8_AMS_PLL_DITHEREN_BITS 1 4503 #define AMS_COM_CONTROL_8_AMS_PLL_DITHEREN_SHIFT 14 4504 4505 /* AMS_COM :: CONTROL_8 :: ams_pll_fracn_ndiv_int [13:04] */ 4506 #define AMS_COM_CONTROL_8_AMS_PLL_FRACN_NDIV_INT_MASK 0x3ff0 4507 #define AMS_COM_CONTROL_8_AMS_PLL_FRACN_NDIV_INT_ALIGN 0 4508 #define AMS_COM_CONTROL_8_AMS_PLL_FRACN_NDIV_INT_BITS 10 4509 #define AMS_COM_CONTROL_8_AMS_PLL_FRACN_NDIV_INT_SHIFT 4 4510 4511 /* AMS_COM :: CONTROL_8 :: ams_pll_fracn_bypass [03:03] */ 4512 #define AMS_COM_CONTROL_8_AMS_PLL_FRACN_BYPASS_MASK 0x0008 4513 #define AMS_COM_CONTROL_8_AMS_PLL_FRACN_BYPASS_ALIGN 0 4514 #define AMS_COM_CONTROL_8_AMS_PLL_FRACN_BYPASS_BITS 1 4515 #define AMS_COM_CONTROL_8_AMS_PLL_FRACN_BYPASS_SHIFT 3 4516 4517 /* AMS_COM :: CONTROL_8 :: ams_pll_fracn_divrange [02:02] */ 4518 #define AMS_COM_CONTROL_8_AMS_PLL_FRACN_DIVRANGE_MASK 0x0004 4519 #define AMS_COM_CONTROL_8_AMS_PLL_FRACN_DIVRANGE_ALIGN 0 4520 #define AMS_COM_CONTROL_8_AMS_PLL_FRACN_DIVRANGE_BITS 1 4521 #define AMS_COM_CONTROL_8_AMS_PLL_FRACN_DIVRANGE_SHIFT 2 4522 4523 /* AMS_COM :: CONTROL_8 :: ams_pll_fracn_div_h [01:00] */ 4524 #define AMS_COM_CONTROL_8_AMS_PLL_FRACN_DIV_H_MASK 0x0003 4525 #define AMS_COM_CONTROL_8_AMS_PLL_FRACN_DIV_H_ALIGN 0 4526 #define AMS_COM_CONTROL_8_AMS_PLL_FRACN_DIV_H_BITS 2 4527 #define AMS_COM_CONTROL_8_AMS_PLL_FRACN_DIV_H_SHIFT 0 4528 4529 4530 /**************************************************************************** 4531 * AMS_COM :: INTCTRL 4532 */ 4533 /* AMS_COM :: INTCTRL :: reserved0 [15:01] */ 4534 #define AMS_COM_INTCTRL_RESERVED0_MASK 0xfffe 4535 #define AMS_COM_INTCTRL_RESERVED0_ALIGN 0 4536 #define AMS_COM_INTCTRL_RESERVED0_BITS 15 4537 #define AMS_COM_INTCTRL_RESERVED0_SHIFT 1 4538 4539 /* AMS_COM :: INTCTRL :: ams_pll_tx_lowpwr_6g [00:00] */ 4540 #define AMS_COM_INTCTRL_AMS_PLL_TX_LOWPWR_6G_MASK 0x0001 4541 #define AMS_COM_INTCTRL_AMS_PLL_TX_LOWPWR_6G_ALIGN 0 4542 #define AMS_COM_INTCTRL_AMS_PLL_TX_LOWPWR_6G_BITS 1 4543 #define AMS_COM_INTCTRL_AMS_PLL_TX_LOWPWR_6G_SHIFT 0 4544 4545 4546 /**************************************************************************** 4547 * AMS_COM :: STATUS 4548 */ 4549 /* AMS_COM :: STATUS :: ams_pll_sts [15:00] */ 4550 #define AMS_COM_STATUS_AMS_PLL_STS_MASK 0xffff 4551 #define AMS_COM_STATUS_AMS_PLL_STS_ALIGN 0 4552 #define AMS_COM_STATUS_AMS_PLL_STS_BITS 16 4553 #define AMS_COM_STATUS_AMS_PLL_STS_SHIFT 0 4554 4555 4556 /**************************************************************************** 4557 * eagle_tsc_sigdet_blk_SIGDET 4558 */ 4559 /**************************************************************************** 4560 * SIGDET :: CTRL_0 4561 */ 4562 /* SIGDET :: CTRL_0 :: reserved0 [15:13] */ 4563 #define SIGDET_CTRL_0_RESERVED0_MASK 0xe000 4564 #define SIGDET_CTRL_0_RESERVED0_ALIGN 0 4565 #define SIGDET_CTRL_0_RESERVED0_BITS 3 4566 #define SIGDET_CTRL_0_RESERVED0_SHIFT 13 4567 4568 /* SIGDET :: CTRL_0 :: los_filter_count [12:08] */ 4569 #define SIGDET_CTRL_0_LOS_FILTER_COUNT_MASK 0x1f00 4570 #define SIGDET_CTRL_0_LOS_FILTER_COUNT_ALIGN 0 4571 #define SIGDET_CTRL_0_LOS_FILTER_COUNT_BITS 5 4572 #define SIGDET_CTRL_0_LOS_FILTER_COUNT_SHIFT 8 4573 4574 /* SIGDET :: CTRL_0 :: reserved1 [07:05] */ 4575 #define SIGDET_CTRL_0_RESERVED1_MASK 0x00e0 4576 #define SIGDET_CTRL_0_RESERVED1_ALIGN 0 4577 #define SIGDET_CTRL_0_RESERVED1_BITS 3 4578 #define SIGDET_CTRL_0_RESERVED1_SHIFT 5 4579 4580 /* SIGDET :: CTRL_0 :: signal_detect_filter_count [04:00] */ 4581 #define SIGDET_CTRL_0_SIGNAL_DETECT_FILTER_COUNT_MASK 0x001f 4582 #define SIGDET_CTRL_0_SIGNAL_DETECT_FILTER_COUNT_ALIGN 0 4583 #define SIGDET_CTRL_0_SIGNAL_DETECT_FILTER_COUNT_BITS 5 4584 #define SIGDET_CTRL_0_SIGNAL_DETECT_FILTER_COUNT_SHIFT 0 4585 4586 4587 /**************************************************************************** 4588 * SIGDET :: CTRL_1 4589 */ 4590 /* SIGDET :: CTRL_1 :: energy_detect_mask_count [15:11] */ 4591 #define SIGDET_CTRL_1_ENERGY_DETECT_MASK_COUNT_MASK 0xf800 4592 #define SIGDET_CTRL_1_ENERGY_DETECT_MASK_COUNT_ALIGN 0 4593 #define SIGDET_CTRL_1_ENERGY_DETECT_MASK_COUNT_BITS 5 4594 #define SIGDET_CTRL_1_ENERGY_DETECT_MASK_COUNT_SHIFT 11 4595 4596 /* SIGDET :: CTRL_1 :: reserved0 [10:09] */ 4597 #define SIGDET_CTRL_1_RESERVED0_MASK 0x0600 4598 #define SIGDET_CTRL_1_RESERVED0_ALIGN 0 4599 #define SIGDET_CTRL_1_RESERVED0_BITS 2 4600 #define SIGDET_CTRL_1_RESERVED0_SHIFT 9 4601 4602 /* SIGDET :: CTRL_1 :: signal_detect_frc_val [08:08] */ 4603 #define SIGDET_CTRL_1_SIGNAL_DETECT_FRC_VAL_MASK 0x0100 4604 #define SIGDET_CTRL_1_SIGNAL_DETECT_FRC_VAL_ALIGN 0 4605 #define SIGDET_CTRL_1_SIGNAL_DETECT_FRC_VAL_BITS 1 4606 #define SIGDET_CTRL_1_SIGNAL_DETECT_FRC_VAL_SHIFT 8 4607 4608 /* SIGDET :: CTRL_1 :: signal_detect_frc [07:07] */ 4609 #define SIGDET_CTRL_1_SIGNAL_DETECT_FRC_MASK 0x0080 4610 #define SIGDET_CTRL_1_SIGNAL_DETECT_FRC_ALIGN 0 4611 #define SIGDET_CTRL_1_SIGNAL_DETECT_FRC_BITS 1 4612 #define SIGDET_CTRL_1_SIGNAL_DETECT_FRC_SHIFT 7 4613 4614 /* SIGDET :: CTRL_1 :: energy_detect_frc_val [06:06] */ 4615 #define SIGDET_CTRL_1_ENERGY_DETECT_FRC_VAL_MASK 0x0040 4616 #define SIGDET_CTRL_1_ENERGY_DETECT_FRC_VAL_ALIGN 0 4617 #define SIGDET_CTRL_1_ENERGY_DETECT_FRC_VAL_BITS 1 4618 #define SIGDET_CTRL_1_ENERGY_DETECT_FRC_VAL_SHIFT 6 4619 4620 /* SIGDET :: CTRL_1 :: energy_detect_frc [05:05] */ 4621 #define SIGDET_CTRL_1_ENERGY_DETECT_FRC_MASK 0x0020 4622 #define SIGDET_CTRL_1_ENERGY_DETECT_FRC_ALIGN 0 4623 #define SIGDET_CTRL_1_ENERGY_DETECT_FRC_BITS 1 4624 #define SIGDET_CTRL_1_ENERGY_DETECT_FRC_SHIFT 5 4625 4626 /* SIGDET :: CTRL_1 :: signal_detect_filter_1us [04:04] */ 4627 #define SIGDET_CTRL_1_SIGNAL_DETECT_FILTER_1US_MASK 0x0010 4628 #define SIGDET_CTRL_1_SIGNAL_DETECT_FILTER_1US_ALIGN 0 4629 #define SIGDET_CTRL_1_SIGNAL_DETECT_FILTER_1US_BITS 1 4630 #define SIGDET_CTRL_1_SIGNAL_DETECT_FILTER_1US_SHIFT 4 4631 4632 /* SIGDET :: CTRL_1 :: ignore_lp_mode [03:03] */ 4633 #define SIGDET_CTRL_1_IGNORE_LP_MODE_MASK 0x0008 4634 #define SIGDET_CTRL_1_IGNORE_LP_MODE_ALIGN 0 4635 #define SIGDET_CTRL_1_IGNORE_LP_MODE_BITS 1 4636 #define SIGDET_CTRL_1_IGNORE_LP_MODE_SHIFT 3 4637 4638 /* SIGDET :: CTRL_1 :: ext_los_inv [02:02] */ 4639 #define SIGDET_CTRL_1_EXT_LOS_INV_MASK 0x0004 4640 #define SIGDET_CTRL_1_EXT_LOS_INV_ALIGN 0 4641 #define SIGDET_CTRL_1_EXT_LOS_INV_BITS 1 4642 #define SIGDET_CTRL_1_EXT_LOS_INV_SHIFT 2 4643 4644 /* SIGDET :: CTRL_1 :: ext_los_en [01:01] */ 4645 #define SIGDET_CTRL_1_EXT_LOS_EN_MASK 0x0002 4646 #define SIGDET_CTRL_1_EXT_LOS_EN_ALIGN 0 4647 #define SIGDET_CTRL_1_EXT_LOS_EN_BITS 1 4648 #define SIGDET_CTRL_1_EXT_LOS_EN_SHIFT 1 4649 4650 /* SIGDET :: CTRL_1 :: afe_signal_detect_dis [00:00] */ 4651 #define SIGDET_CTRL_1_AFE_SIGNAL_DETECT_DIS_MASK 0x0001 4652 #define SIGDET_CTRL_1_AFE_SIGNAL_DETECT_DIS_ALIGN 0 4653 #define SIGDET_CTRL_1_AFE_SIGNAL_DETECT_DIS_BITS 1 4654 #define SIGDET_CTRL_1_AFE_SIGNAL_DETECT_DIS_SHIFT 0 4655 4656 4657 /**************************************************************************** 4658 * SIGDET :: CTRL_2 4659 */ 4660 /* SIGDET :: CTRL_2 :: reserved0 [15:14] */ 4661 #define SIGDET_CTRL_2_RESERVED0_MASK 0xc000 4662 #define SIGDET_CTRL_2_RESERVED0_ALIGN 0 4663 #define SIGDET_CTRL_2_RESERVED0_BITS 2 4664 #define SIGDET_CTRL_2_RESERVED0_SHIFT 14 4665 4666 /* SIGDET :: CTRL_2 :: hold_sd_count [13:11] */ 4667 #define SIGDET_CTRL_2_HOLD_SD_COUNT_MASK 0x3800 4668 #define SIGDET_CTRL_2_HOLD_SD_COUNT_ALIGN 0 4669 #define SIGDET_CTRL_2_HOLD_SD_COUNT_BITS 3 4670 #define SIGDET_CTRL_2_HOLD_SD_COUNT_SHIFT 11 4671 4672 /* SIGDET :: CTRL_2 :: hold_los_count [10:08] */ 4673 #define SIGDET_CTRL_2_HOLD_LOS_COUNT_MASK 0x0700 4674 #define SIGDET_CTRL_2_HOLD_LOS_COUNT_ALIGN 0 4675 #define SIGDET_CTRL_2_HOLD_LOS_COUNT_BITS 3 4676 #define SIGDET_CTRL_2_HOLD_LOS_COUNT_SHIFT 8 4677 4678 /* SIGDET :: CTRL_2 :: reserved1 [07:07] */ 4679 #define SIGDET_CTRL_2_RESERVED1_MASK 0x0080 4680 #define SIGDET_CTRL_2_RESERVED1_ALIGN 0 4681 #define SIGDET_CTRL_2_RESERVED1_BITS 1 4682 #define SIGDET_CTRL_2_RESERVED1_SHIFT 7 4683 4684 /* SIGDET :: CTRL_2 :: signal_detect_thresh [06:04] */ 4685 #define SIGDET_CTRL_2_SIGNAL_DETECT_THRESH_MASK 0x0070 4686 #define SIGDET_CTRL_2_SIGNAL_DETECT_THRESH_ALIGN 0 4687 #define SIGDET_CTRL_2_SIGNAL_DETECT_THRESH_BITS 3 4688 #define SIGDET_CTRL_2_SIGNAL_DETECT_THRESH_SHIFT 4 4689 4690 /* SIGDET :: CTRL_2 :: reserved2 [03:03] */ 4691 #define SIGDET_CTRL_2_RESERVED2_MASK 0x0008 4692 #define SIGDET_CTRL_2_RESERVED2_ALIGN 0 4693 #define SIGDET_CTRL_2_RESERVED2_BITS 1 4694 #define SIGDET_CTRL_2_RESERVED2_SHIFT 3 4695 4696 /* SIGDET :: CTRL_2 :: los_thresh [02:00] */ 4697 #define SIGDET_CTRL_2_LOS_THRESH_MASK 0x0007 4698 #define SIGDET_CTRL_2_LOS_THRESH_ALIGN 0 4699 #define SIGDET_CTRL_2_LOS_THRESH_BITS 3 4700 #define SIGDET_CTRL_2_LOS_THRESH_SHIFT 0 4701 4702 4703 /**************************************************************************** 4704 * SIGDET :: STATUS_0 4705 */ 4706 /* SIGDET :: STATUS_0 :: reserved0 [15:11] */ 4707 #define SIGDET_STATUS_0_RESERVED0_MASK 0xf800 4708 #define SIGDET_STATUS_0_RESERVED0_ALIGN 0 4709 #define SIGDET_STATUS_0_RESERVED0_BITS 5 4710 #define SIGDET_STATUS_0_RESERVED0_SHIFT 11 4711 4712 /* SIGDET :: STATUS_0 :: afe_sigdet_thresh [10:08] */ 4713 #define SIGDET_STATUS_0_AFE_SIGDET_THRESH_MASK 0x0700 4714 #define SIGDET_STATUS_0_AFE_SIGDET_THRESH_ALIGN 0 4715 #define SIGDET_STATUS_0_AFE_SIGDET_THRESH_BITS 3 4716 #define SIGDET_STATUS_0_AFE_SIGDET_THRESH_SHIFT 8 4717 4718 /* SIGDET :: STATUS_0 :: reserved1 [07:06] */ 4719 #define SIGDET_STATUS_0_RESERVED1_MASK 0x00c0 4720 #define SIGDET_STATUS_0_RESERVED1_ALIGN 0 4721 #define SIGDET_STATUS_0_RESERVED1_BITS 2 4722 #define SIGDET_STATUS_0_RESERVED1_SHIFT 6 4723 4724 /* SIGDET :: STATUS_0 :: signal_detect_raw_change [05:05] */ 4725 #define SIGDET_STATUS_0_SIGNAL_DETECT_RAW_CHANGE_MASK 0x0020 4726 #define SIGDET_STATUS_0_SIGNAL_DETECT_RAW_CHANGE_ALIGN 0 4727 #define SIGDET_STATUS_0_SIGNAL_DETECT_RAW_CHANGE_BITS 1 4728 #define SIGDET_STATUS_0_SIGNAL_DETECT_RAW_CHANGE_SHIFT 5 4729 4730 /* SIGDET :: STATUS_0 :: signal_detect_raw [04:04] */ 4731 #define SIGDET_STATUS_0_SIGNAL_DETECT_RAW_MASK 0x0010 4732 #define SIGDET_STATUS_0_SIGNAL_DETECT_RAW_ALIGN 0 4733 #define SIGDET_STATUS_0_SIGNAL_DETECT_RAW_BITS 1 4734 #define SIGDET_STATUS_0_SIGNAL_DETECT_RAW_SHIFT 4 4735 4736 /* SIGDET :: STATUS_0 :: energy_detect_change [03:03] */ 4737 #define SIGDET_STATUS_0_ENERGY_DETECT_CHANGE_MASK 0x0008 4738 #define SIGDET_STATUS_0_ENERGY_DETECT_CHANGE_ALIGN 0 4739 #define SIGDET_STATUS_0_ENERGY_DETECT_CHANGE_BITS 1 4740 #define SIGDET_STATUS_0_ENERGY_DETECT_CHANGE_SHIFT 3 4741 4742 /* SIGDET :: STATUS_0 :: energy_detect [02:02] */ 4743 #define SIGDET_STATUS_0_ENERGY_DETECT_MASK 0x0004 4744 #define SIGDET_STATUS_0_ENERGY_DETECT_ALIGN 0 4745 #define SIGDET_STATUS_0_ENERGY_DETECT_BITS 1 4746 #define SIGDET_STATUS_0_ENERGY_DETECT_SHIFT 2 4747 4748 /* SIGDET :: STATUS_0 :: signal_detect_change [01:01] */ 4749 #define SIGDET_STATUS_0_SIGNAL_DETECT_CHANGE_MASK 0x0002 4750 #define SIGDET_STATUS_0_SIGNAL_DETECT_CHANGE_ALIGN 0 4751 #define SIGDET_STATUS_0_SIGNAL_DETECT_CHANGE_BITS 1 4752 #define SIGDET_STATUS_0_SIGNAL_DETECT_CHANGE_SHIFT 1 4753 4754 /* SIGDET :: STATUS_0 :: signal_detect [00:00] */ 4755 #define SIGDET_STATUS_0_SIGNAL_DETECT_MASK 0x0001 4756 #define SIGDET_STATUS_0_SIGNAL_DETECT_ALIGN 0 4757 #define SIGDET_STATUS_0_SIGNAL_DETECT_BITS 1 4758 #define SIGDET_STATUS_0_SIGNAL_DETECT_SHIFT 0 4759 4760 4761 /**************************************************************************** 4762 * eagle_tsc_tlb_blk_TLB_RX 4763 */ 4764 /**************************************************************************** 4765 * TLB_RX :: PRBS_CHK_CNT_CONFIG 4766 */ 4767 /* TLB_RX :: PRBS_CHK_CNT_CONFIG :: reserved0 [15:13] */ 4768 #define TLB_RX_PRBS_CHK_CNT_CONFIG_RESERVED0_MASK 0xe000 4769 #define TLB_RX_PRBS_CHK_CNT_CONFIG_RESERVED0_ALIGN 0 4770 #define TLB_RX_PRBS_CHK_CNT_CONFIG_RESERVED0_BITS 3 4771 #define TLB_RX_PRBS_CHK_CNT_CONFIG_RESERVED0_SHIFT 13 4772 4773 /* TLB_RX :: PRBS_CHK_CNT_CONFIG :: prbs_chk_ool_cnt [12:08] */ 4774 #define TLB_RX_PRBS_CHK_CNT_CONFIG_PRBS_CHK_OOL_CNT_MASK 0x1f00 4775 #define TLB_RX_PRBS_CHK_CNT_CONFIG_PRBS_CHK_OOL_CNT_ALIGN 0 4776 #define TLB_RX_PRBS_CHK_CNT_CONFIG_PRBS_CHK_OOL_CNT_BITS 5 4777 #define TLB_RX_PRBS_CHK_CNT_CONFIG_PRBS_CHK_OOL_CNT_SHIFT 8 4778 4779 /* TLB_RX :: PRBS_CHK_CNT_CONFIG :: reserved1 [07:05] */ 4780 #define TLB_RX_PRBS_CHK_CNT_CONFIG_RESERVED1_MASK 0x00e0 4781 #define TLB_RX_PRBS_CHK_CNT_CONFIG_RESERVED1_ALIGN 0 4782 #define TLB_RX_PRBS_CHK_CNT_CONFIG_RESERVED1_BITS 3 4783 #define TLB_RX_PRBS_CHK_CNT_CONFIG_RESERVED1_SHIFT 5 4784 4785 /* TLB_RX :: PRBS_CHK_CNT_CONFIG :: prbs_chk_lock_cnt [04:00] */ 4786 #define TLB_RX_PRBS_CHK_CNT_CONFIG_PRBS_CHK_LOCK_CNT_MASK 0x001f 4787 #define TLB_RX_PRBS_CHK_CNT_CONFIG_PRBS_CHK_LOCK_CNT_ALIGN 0 4788 #define TLB_RX_PRBS_CHK_CNT_CONFIG_PRBS_CHK_LOCK_CNT_BITS 5 4789 #define TLB_RX_PRBS_CHK_CNT_CONFIG_PRBS_CHK_LOCK_CNT_SHIFT 0 4790 4791 4792 /**************************************************************************** 4793 * TLB_RX :: PRBS_CHK_CONFIG 4794 */ 4795 /* TLB_RX :: PRBS_CHK_CONFIG :: reserved0 [15:12] */ 4796 #define TLB_RX_PRBS_CHK_CONFIG_RESERVED0_MASK 0xf000 4797 #define TLB_RX_PRBS_CHK_CONFIG_RESERVED0_ALIGN 0 4798 #define TLB_RX_PRBS_CHK_CONFIG_RESERVED0_BITS 4 4799 #define TLB_RX_PRBS_CHK_CONFIG_RESERVED0_SHIFT 12 4800 4801 /* TLB_RX :: PRBS_CHK_CONFIG :: prbs_chk_clk_en_frc_on [11:11] */ 4802 #define TLB_RX_PRBS_CHK_CONFIG_PRBS_CHK_CLK_EN_FRC_ON_MASK 0x0800 4803 #define TLB_RX_PRBS_CHK_CONFIG_PRBS_CHK_CLK_EN_FRC_ON_ALIGN 0 4804 #define TLB_RX_PRBS_CHK_CONFIG_PRBS_CHK_CLK_EN_FRC_ON_BITS 1 4805 #define TLB_RX_PRBS_CHK_CONFIG_PRBS_CHK_CLK_EN_FRC_ON_SHIFT 11 4806 4807 /* TLB_RX :: PRBS_CHK_CONFIG :: trnsum_error_count_en [10:10] */ 4808 #define TLB_RX_PRBS_CHK_CONFIG_TRNSUM_ERROR_COUNT_EN_MASK 0x0400 4809 #define TLB_RX_PRBS_CHK_CONFIG_TRNSUM_ERROR_COUNT_EN_ALIGN 0 4810 #define TLB_RX_PRBS_CHK_CONFIG_TRNSUM_ERROR_COUNT_EN_BITS 1 4811 #define TLB_RX_PRBS_CHK_CONFIG_TRNSUM_ERROR_COUNT_EN_SHIFT 10 4812 4813 /* TLB_RX :: PRBS_CHK_CONFIG :: prbs_chk_err_cnt_burst_mode [09:09] */ 4814 #define TLB_RX_PRBS_CHK_CONFIG_PRBS_CHK_ERR_CNT_BURST_MODE_MASK 0x0200 4815 #define TLB_RX_PRBS_CHK_CONFIG_PRBS_CHK_ERR_CNT_BURST_MODE_ALIGN 0 4816 #define TLB_RX_PRBS_CHK_CONFIG_PRBS_CHK_ERR_CNT_BURST_MODE_BITS 1 4817 #define TLB_RX_PRBS_CHK_CONFIG_PRBS_CHK_ERR_CNT_BURST_MODE_SHIFT 9 4818 4819 /* TLB_RX :: PRBS_CHK_CONFIG :: reserved1 [08:08] */ 4820 #define TLB_RX_PRBS_CHK_CONFIG_RESERVED1_MASK 0x0100 4821 #define TLB_RX_PRBS_CHK_CONFIG_RESERVED1_ALIGN 0 4822 #define TLB_RX_PRBS_CHK_CONFIG_RESERVED1_BITS 1 4823 #define TLB_RX_PRBS_CHK_CONFIG_RESERVED1_SHIFT 8 4824 4825 /* TLB_RX :: PRBS_CHK_CONFIG :: prbs_chk_en_auto_mode [07:07] */ 4826 #define TLB_RX_PRBS_CHK_CONFIG_PRBS_CHK_EN_AUTO_MODE_MASK 0x0080 4827 #define TLB_RX_PRBS_CHK_CONFIG_PRBS_CHK_EN_AUTO_MODE_ALIGN 0 4828 #define TLB_RX_PRBS_CHK_CONFIG_PRBS_CHK_EN_AUTO_MODE_BITS 1 4829 #define TLB_RX_PRBS_CHK_CONFIG_PRBS_CHK_EN_AUTO_MODE_SHIFT 7 4830 4831 /* TLB_RX :: PRBS_CHK_CONFIG :: prbs_chk_mode [06:05] */ 4832 #define TLB_RX_PRBS_CHK_CONFIG_PRBS_CHK_MODE_MASK 0x0060 4833 #define TLB_RX_PRBS_CHK_CONFIG_PRBS_CHK_MODE_ALIGN 0 4834 #define TLB_RX_PRBS_CHK_CONFIG_PRBS_CHK_MODE_BITS 2 4835 #define TLB_RX_PRBS_CHK_CONFIG_PRBS_CHK_MODE_SHIFT 5 4836 4837 /* TLB_RX :: PRBS_CHK_CONFIG :: prbs_chk_inv [04:04] */ 4838 #define TLB_RX_PRBS_CHK_CONFIG_PRBS_CHK_INV_MASK 0x0010 4839 #define TLB_RX_PRBS_CHK_CONFIG_PRBS_CHK_INV_ALIGN 0 4840 #define TLB_RX_PRBS_CHK_CONFIG_PRBS_CHK_INV_BITS 1 4841 #define TLB_RX_PRBS_CHK_CONFIG_PRBS_CHK_INV_SHIFT 4 4842 4843 /* TLB_RX :: PRBS_CHK_CONFIG :: prbs_chk_mode_sel [03:01] */ 4844 #define TLB_RX_PRBS_CHK_CONFIG_PRBS_CHK_MODE_SEL_MASK 0x000e 4845 #define TLB_RX_PRBS_CHK_CONFIG_PRBS_CHK_MODE_SEL_ALIGN 0 4846 #define TLB_RX_PRBS_CHK_CONFIG_PRBS_CHK_MODE_SEL_BITS 3 4847 #define TLB_RX_PRBS_CHK_CONFIG_PRBS_CHK_MODE_SEL_SHIFT 1 4848 4849 /* TLB_RX :: PRBS_CHK_CONFIG :: prbs_chk_en [00:00] */ 4850 #define TLB_RX_PRBS_CHK_CONFIG_PRBS_CHK_EN_MASK 0x0001 4851 #define TLB_RX_PRBS_CHK_CONFIG_PRBS_CHK_EN_ALIGN 0 4852 #define TLB_RX_PRBS_CHK_CONFIG_PRBS_CHK_EN_BITS 1 4853 #define TLB_RX_PRBS_CHK_CONFIG_PRBS_CHK_EN_SHIFT 0 4854 4855 4856 /**************************************************************************** 4857 * TLB_RX :: DIG_LPBK_CONFIG 4858 */ 4859 /* TLB_RX :: DIG_LPBK_CONFIG :: reserved0 [15:03] */ 4860 #define TLB_RX_DIG_LPBK_CONFIG_RESERVED0_MASK 0xfff8 4861 #define TLB_RX_DIG_LPBK_CONFIG_RESERVED0_ALIGN 0 4862 #define TLB_RX_DIG_LPBK_CONFIG_RESERVED0_BITS 13 4863 #define TLB_RX_DIG_LPBK_CONFIG_RESERVED0_SHIFT 3 4864 4865 /* TLB_RX :: DIG_LPBK_CONFIG :: dig_lpbk_pd_flt_bypass [02:02] */ 4866 #define TLB_RX_DIG_LPBK_CONFIG_DIG_LPBK_PD_FLT_BYPASS_MASK 0x0004 4867 #define TLB_RX_DIG_LPBK_CONFIG_DIG_LPBK_PD_FLT_BYPASS_ALIGN 0 4868 #define TLB_RX_DIG_LPBK_CONFIG_DIG_LPBK_PD_FLT_BYPASS_BITS 1 4869 #define TLB_RX_DIG_LPBK_CONFIG_DIG_LPBK_PD_FLT_BYPASS_SHIFT 2 4870 4871 /* TLB_RX :: DIG_LPBK_CONFIG :: dig_lpbk_pd_mode [01:01] */ 4872 #define TLB_RX_DIG_LPBK_CONFIG_DIG_LPBK_PD_MODE_MASK 0x0002 4873 #define TLB_RX_DIG_LPBK_CONFIG_DIG_LPBK_PD_MODE_ALIGN 0 4874 #define TLB_RX_DIG_LPBK_CONFIG_DIG_LPBK_PD_MODE_BITS 1 4875 #define TLB_RX_DIG_LPBK_CONFIG_DIG_LPBK_PD_MODE_SHIFT 1 4876 4877 /* TLB_RX :: DIG_LPBK_CONFIG :: dig_lpbk_en [00:00] */ 4878 #define TLB_RX_DIG_LPBK_CONFIG_DIG_LPBK_EN_MASK 0x0001 4879 #define TLB_RX_DIG_LPBK_CONFIG_DIG_LPBK_EN_ALIGN 0 4880 #define TLB_RX_DIG_LPBK_CONFIG_DIG_LPBK_EN_BITS 1 4881 #define TLB_RX_DIG_LPBK_CONFIG_DIG_LPBK_EN_SHIFT 0 4882 4883 4884 /**************************************************************************** 4885 * TLB_RX :: TLB_RX_MISC_CONFIG 4886 */ 4887 /* TLB_RX :: TLB_RX_MISC_CONFIG :: reserved0 [15:03] */ 4888 #define TLB_RX_TLB_RX_MISC_CONFIG_RESERVED0_MASK 0xfff8 4889 #define TLB_RX_TLB_RX_MISC_CONFIG_RESERVED0_ALIGN 0 4890 #define TLB_RX_TLB_RX_MISC_CONFIG_RESERVED0_BITS 13 4891 #define TLB_RX_TLB_RX_MISC_CONFIG_RESERVED0_SHIFT 3 4892 4893 /* TLB_RX :: TLB_RX_MISC_CONFIG :: dbg_mask_dig_lpbk_en [02:02] */ 4894 #define TLB_RX_TLB_RX_MISC_CONFIG_DBG_MASK_DIG_LPBK_EN_MASK 0x0004 4895 #define TLB_RX_TLB_RX_MISC_CONFIG_DBG_MASK_DIG_LPBK_EN_ALIGN 0 4896 #define TLB_RX_TLB_RX_MISC_CONFIG_DBG_MASK_DIG_LPBK_EN_BITS 1 4897 #define TLB_RX_TLB_RX_MISC_CONFIG_DBG_MASK_DIG_LPBK_EN_SHIFT 2 4898 4899 /* TLB_RX :: TLB_RX_MISC_CONFIG :: rx_aggregator_bypass_en [01:01] */ 4900 #define TLB_RX_TLB_RX_MISC_CONFIG_RX_AGGREGATOR_BYPASS_EN_MASK 0x0002 4901 #define TLB_RX_TLB_RX_MISC_CONFIG_RX_AGGREGATOR_BYPASS_EN_ALIGN 0 4902 #define TLB_RX_TLB_RX_MISC_CONFIG_RX_AGGREGATOR_BYPASS_EN_BITS 1 4903 #define TLB_RX_TLB_RX_MISC_CONFIG_RX_AGGREGATOR_BYPASS_EN_SHIFT 1 4904 4905 /* TLB_RX :: TLB_RX_MISC_CONFIG :: rx_pmd_dp_invert [00:00] */ 4906 #define TLB_RX_TLB_RX_MISC_CONFIG_RX_PMD_DP_INVERT_MASK 0x0001 4907 #define TLB_RX_TLB_RX_MISC_CONFIG_RX_PMD_DP_INVERT_ALIGN 0 4908 #define TLB_RX_TLB_RX_MISC_CONFIG_RX_PMD_DP_INVERT_BITS 1 4909 #define TLB_RX_TLB_RX_MISC_CONFIG_RX_PMD_DP_INVERT_SHIFT 0 4910 4911 4912 /**************************************************************************** 4913 * TLB_RX :: PRBS_CHK_EN_TIMER_CONTROL 4914 */ 4915 /* TLB_RX :: PRBS_CHK_EN_TIMER_CONTROL :: reserved0 [15:13] */ 4916 #define TLB_RX_PRBS_CHK_EN_TIMER_CONTROL_RESERVED0_MASK 0xe000 4917 #define TLB_RX_PRBS_CHK_EN_TIMER_CONTROL_RESERVED0_ALIGN 0 4918 #define TLB_RX_PRBS_CHK_EN_TIMER_CONTROL_RESERVED0_BITS 3 4919 #define TLB_RX_PRBS_CHK_EN_TIMER_CONTROL_RESERVED0_SHIFT 13 4920 4921 /* TLB_RX :: PRBS_CHK_EN_TIMER_CONTROL :: prbs_chk_en_timeout [12:08] */ 4922 #define TLB_RX_PRBS_CHK_EN_TIMER_CONTROL_PRBS_CHK_EN_TIMEOUT_MASK 0x1f00 4923 #define TLB_RX_PRBS_CHK_EN_TIMER_CONTROL_PRBS_CHK_EN_TIMEOUT_ALIGN 0 4924 #define TLB_RX_PRBS_CHK_EN_TIMER_CONTROL_PRBS_CHK_EN_TIMEOUT_BITS 5 4925 #define TLB_RX_PRBS_CHK_EN_TIMER_CONTROL_PRBS_CHK_EN_TIMEOUT_SHIFT 8 4926 4927 /* TLB_RX :: PRBS_CHK_EN_TIMER_CONTROL :: reserved1 [07:02] */ 4928 #define TLB_RX_PRBS_CHK_EN_TIMER_CONTROL_RESERVED1_MASK 0x00fc 4929 #define TLB_RX_PRBS_CHK_EN_TIMER_CONTROL_RESERVED1_ALIGN 0 4930 #define TLB_RX_PRBS_CHK_EN_TIMER_CONTROL_RESERVED1_BITS 6 4931 #define TLB_RX_PRBS_CHK_EN_TIMER_CONTROL_RESERVED1_SHIFT 2 4932 4933 /* TLB_RX :: PRBS_CHK_EN_TIMER_CONTROL :: prbs_chk_en_timer_mode [01:00] */ 4934 #define TLB_RX_PRBS_CHK_EN_TIMER_CONTROL_PRBS_CHK_EN_TIMER_MODE_MASK 0x0003 4935 #define TLB_RX_PRBS_CHK_EN_TIMER_CONTROL_PRBS_CHK_EN_TIMER_MODE_ALIGN 0 4936 #define TLB_RX_PRBS_CHK_EN_TIMER_CONTROL_PRBS_CHK_EN_TIMER_MODE_BITS 2 4937 #define TLB_RX_PRBS_CHK_EN_TIMER_CONTROL_PRBS_CHK_EN_TIMER_MODE_SHIFT 0 4938 4939 4940 /**************************************************************************** 4941 * TLB_RX :: DIG_LPBK_PD_STATUS 4942 */ 4943 /* TLB_RX :: DIG_LPBK_PD_STATUS :: reserved0 [15:02] */ 4944 #define TLB_RX_DIG_LPBK_PD_STATUS_RESERVED0_MASK 0xfffc 4945 #define TLB_RX_DIG_LPBK_PD_STATUS_RESERVED0_ALIGN 0 4946 #define TLB_RX_DIG_LPBK_PD_STATUS_RESERVED0_BITS 14 4947 #define TLB_RX_DIG_LPBK_PD_STATUS_RESERVED0_SHIFT 2 4948 4949 /* TLB_RX :: DIG_LPBK_PD_STATUS :: dig_lpbk_pd_early_ind [01:01] */ 4950 #define TLB_RX_DIG_LPBK_PD_STATUS_DIG_LPBK_PD_EARLY_IND_MASK 0x0002 4951 #define TLB_RX_DIG_LPBK_PD_STATUS_DIG_LPBK_PD_EARLY_IND_ALIGN 0 4952 #define TLB_RX_DIG_LPBK_PD_STATUS_DIG_LPBK_PD_EARLY_IND_BITS 1 4953 #define TLB_RX_DIG_LPBK_PD_STATUS_DIG_LPBK_PD_EARLY_IND_SHIFT 1 4954 4955 /* TLB_RX :: DIG_LPBK_PD_STATUS :: dig_lpbk_pd_late_ind [00:00] */ 4956 #define TLB_RX_DIG_LPBK_PD_STATUS_DIG_LPBK_PD_LATE_IND_MASK 0x0001 4957 #define TLB_RX_DIG_LPBK_PD_STATUS_DIG_LPBK_PD_LATE_IND_ALIGN 0 4958 #define TLB_RX_DIG_LPBK_PD_STATUS_DIG_LPBK_PD_LATE_IND_BITS 1 4959 #define TLB_RX_DIG_LPBK_PD_STATUS_DIG_LPBK_PD_LATE_IND_SHIFT 0 4960 4961 4962 /**************************************************************************** 4963 * TLB_RX :: PRBS_CHK_LOCK_STATUS 4964 */ 4965 /* TLB_RX :: PRBS_CHK_LOCK_STATUS :: reserved0 [15:01] */ 4966 #define TLB_RX_PRBS_CHK_LOCK_STATUS_RESERVED0_MASK 0xfffe 4967 #define TLB_RX_PRBS_CHK_LOCK_STATUS_RESERVED0_ALIGN 0 4968 #define TLB_RX_PRBS_CHK_LOCK_STATUS_RESERVED0_BITS 15 4969 #define TLB_RX_PRBS_CHK_LOCK_STATUS_RESERVED0_SHIFT 1 4970 4971 /* TLB_RX :: PRBS_CHK_LOCK_STATUS :: prbs_chk_lock [00:00] */ 4972 #define TLB_RX_PRBS_CHK_LOCK_STATUS_PRBS_CHK_LOCK_MASK 0x0001 4973 #define TLB_RX_PRBS_CHK_LOCK_STATUS_PRBS_CHK_LOCK_ALIGN 0 4974 #define TLB_RX_PRBS_CHK_LOCK_STATUS_PRBS_CHK_LOCK_BITS 1 4975 #define TLB_RX_PRBS_CHK_LOCK_STATUS_PRBS_CHK_LOCK_SHIFT 0 4976 4977 4978 /**************************************************************************** 4979 * TLB_RX :: PRBS_CHK_ERR_CNT_MSB_STATUS 4980 */ 4981 /* TLB_RX :: PRBS_CHK_ERR_CNT_MSB_STATUS :: prbs_chk_lock_lost_lh [15:15] */ 4982 #define TLB_RX_PRBS_CHK_ERR_CNT_MSB_STATUS_PRBS_CHK_LOCK_LOST_LH_MASK 0x8000 4983 #define TLB_RX_PRBS_CHK_ERR_CNT_MSB_STATUS_PRBS_CHK_LOCK_LOST_LH_ALIGN 0 4984 #define TLB_RX_PRBS_CHK_ERR_CNT_MSB_STATUS_PRBS_CHK_LOCK_LOST_LH_BITS 1 4985 #define TLB_RX_PRBS_CHK_ERR_CNT_MSB_STATUS_PRBS_CHK_LOCK_LOST_LH_SHIFT 15 4986 4987 /* TLB_RX :: PRBS_CHK_ERR_CNT_MSB_STATUS :: prbs_chk_err_cnt_msb [14:00] */ 4988 #define TLB_RX_PRBS_CHK_ERR_CNT_MSB_STATUS_PRBS_CHK_ERR_CNT_MSB_MASK 0x7fff 4989 #define TLB_RX_PRBS_CHK_ERR_CNT_MSB_STATUS_PRBS_CHK_ERR_CNT_MSB_ALIGN 0 4990 #define TLB_RX_PRBS_CHK_ERR_CNT_MSB_STATUS_PRBS_CHK_ERR_CNT_MSB_BITS 15 4991 #define TLB_RX_PRBS_CHK_ERR_CNT_MSB_STATUS_PRBS_CHK_ERR_CNT_MSB_SHIFT 0 4992 4993 4994 /**************************************************************************** 4995 * TLB_RX :: PRBS_CHK_ERR_CNT_LSB_STATUS 4996 */ 4997 /* TLB_RX :: PRBS_CHK_ERR_CNT_LSB_STATUS :: prbs_chk_err_cnt_lsb [15:00] */ 4998 #define TLB_RX_PRBS_CHK_ERR_CNT_LSB_STATUS_PRBS_CHK_ERR_CNT_LSB_MASK 0xffff 4999 #define TLB_RX_PRBS_CHK_ERR_CNT_LSB_STATUS_PRBS_CHK_ERR_CNT_LSB_ALIGN 0 5000 #define TLB_RX_PRBS_CHK_ERR_CNT_LSB_STATUS_PRBS_CHK_ERR_CNT_LSB_BITS 16 5001 #define TLB_RX_PRBS_CHK_ERR_CNT_LSB_STATUS_PRBS_CHK_ERR_CNT_LSB_SHIFT 0 5002 5003 5004 /**************************************************************************** 5005 * TLB_RX :: PMD_RX_LOCK_STATUS 5006 */ 5007 /* TLB_RX :: PMD_RX_LOCK_STATUS :: reserved0 [15:02] */ 5008 #define TLB_RX_PMD_RX_LOCK_STATUS_RESERVED0_MASK 0xfffc 5009 #define TLB_RX_PMD_RX_LOCK_STATUS_RESERVED0_ALIGN 0 5010 #define TLB_RX_PMD_RX_LOCK_STATUS_RESERVED0_BITS 14 5011 #define TLB_RX_PMD_RX_LOCK_STATUS_RESERVED0_SHIFT 2 5012 5013 /* TLB_RX :: PMD_RX_LOCK_STATUS :: pmd_rx_lock_change [01:01] */ 5014 #define TLB_RX_PMD_RX_LOCK_STATUS_PMD_RX_LOCK_CHANGE_MASK 0x0002 5015 #define TLB_RX_PMD_RX_LOCK_STATUS_PMD_RX_LOCK_CHANGE_ALIGN 0 5016 #define TLB_RX_PMD_RX_LOCK_STATUS_PMD_RX_LOCK_CHANGE_BITS 1 5017 #define TLB_RX_PMD_RX_LOCK_STATUS_PMD_RX_LOCK_CHANGE_SHIFT 1 5018 5019 /* TLB_RX :: PMD_RX_LOCK_STATUS :: pmd_rx_lock [00:00] */ 5020 #define TLB_RX_PMD_RX_LOCK_STATUS_PMD_RX_LOCK_MASK 0x0001 5021 #define TLB_RX_PMD_RX_LOCK_STATUS_PMD_RX_LOCK_ALIGN 0 5022 #define TLB_RX_PMD_RX_LOCK_STATUS_PMD_RX_LOCK_BITS 1 5023 #define TLB_RX_PMD_RX_LOCK_STATUS_PMD_RX_LOCK_SHIFT 0 5024 5025 5026 /**************************************************************************** 5027 * eagle_tsc_tlb_blk_TLB_TX 5028 */ 5029 /**************************************************************************** 5030 * TLB_TX :: PATT_GEN_CONFIG 5031 */ 5032 /* TLB_TX :: PATT_GEN_CONFIG :: patt_gen_start_pos [15:12] */ 5033 #define TLB_TX_PATT_GEN_CONFIG_PATT_GEN_START_POS_MASK 0xf000 5034 #define TLB_TX_PATT_GEN_CONFIG_PATT_GEN_START_POS_ALIGN 0 5035 #define TLB_TX_PATT_GEN_CONFIG_PATT_GEN_START_POS_BITS 4 5036 #define TLB_TX_PATT_GEN_CONFIG_PATT_GEN_START_POS_SHIFT 12 5037 5038 /* TLB_TX :: PATT_GEN_CONFIG :: patt_gen_stop_pos [11:08] */ 5039 #define TLB_TX_PATT_GEN_CONFIG_PATT_GEN_STOP_POS_MASK 0x0f00 5040 #define TLB_TX_PATT_GEN_CONFIG_PATT_GEN_STOP_POS_ALIGN 0 5041 #define TLB_TX_PATT_GEN_CONFIG_PATT_GEN_STOP_POS_BITS 4 5042 #define TLB_TX_PATT_GEN_CONFIG_PATT_GEN_STOP_POS_SHIFT 8 5043 5044 /* TLB_TX :: PATT_GEN_CONFIG :: reserved0 [07:01] */ 5045 #define TLB_TX_PATT_GEN_CONFIG_RESERVED0_MASK 0x00fe 5046 #define TLB_TX_PATT_GEN_CONFIG_RESERVED0_ALIGN 0 5047 #define TLB_TX_PATT_GEN_CONFIG_RESERVED0_BITS 7 5048 #define TLB_TX_PATT_GEN_CONFIG_RESERVED0_SHIFT 1 5049 5050 /* TLB_TX :: PATT_GEN_CONFIG :: patt_gen_en [00:00] */ 5051 #define TLB_TX_PATT_GEN_CONFIG_PATT_GEN_EN_MASK 0x0001 5052 #define TLB_TX_PATT_GEN_CONFIG_PATT_GEN_EN_ALIGN 0 5053 #define TLB_TX_PATT_GEN_CONFIG_PATT_GEN_EN_BITS 1 5054 #define TLB_TX_PATT_GEN_CONFIG_PATT_GEN_EN_SHIFT 0 5055 5056 5057 /**************************************************************************** 5058 * TLB_TX :: PRBS_GEN_CONFIG 5059 */ 5060 /* TLB_TX :: PRBS_GEN_CONFIG :: reserved0 [15:06] */ 5061 #define TLB_TX_PRBS_GEN_CONFIG_RESERVED0_MASK 0xffc0 5062 #define TLB_TX_PRBS_GEN_CONFIG_RESERVED0_ALIGN 0 5063 #define TLB_TX_PRBS_GEN_CONFIG_RESERVED0_BITS 10 5064 #define TLB_TX_PRBS_GEN_CONFIG_RESERVED0_SHIFT 6 5065 5066 /* TLB_TX :: PRBS_GEN_CONFIG :: prbs_gen_err_ins [05:05] */ 5067 #define TLB_TX_PRBS_GEN_CONFIG_PRBS_GEN_ERR_INS_MASK 0x0020 5068 #define TLB_TX_PRBS_GEN_CONFIG_PRBS_GEN_ERR_INS_ALIGN 0 5069 #define TLB_TX_PRBS_GEN_CONFIG_PRBS_GEN_ERR_INS_BITS 1 5070 #define TLB_TX_PRBS_GEN_CONFIG_PRBS_GEN_ERR_INS_SHIFT 5 5071 5072 /* TLB_TX :: PRBS_GEN_CONFIG :: prbs_gen_inv [04:04] */ 5073 #define TLB_TX_PRBS_GEN_CONFIG_PRBS_GEN_INV_MASK 0x0010 5074 #define TLB_TX_PRBS_GEN_CONFIG_PRBS_GEN_INV_ALIGN 0 5075 #define TLB_TX_PRBS_GEN_CONFIG_PRBS_GEN_INV_BITS 1 5076 #define TLB_TX_PRBS_GEN_CONFIG_PRBS_GEN_INV_SHIFT 4 5077 5078 /* TLB_TX :: PRBS_GEN_CONFIG :: prbs_gen_mode_sel [03:01] */ 5079 #define TLB_TX_PRBS_GEN_CONFIG_PRBS_GEN_MODE_SEL_MASK 0x000e 5080 #define TLB_TX_PRBS_GEN_CONFIG_PRBS_GEN_MODE_SEL_ALIGN 0 5081 #define TLB_TX_PRBS_GEN_CONFIG_PRBS_GEN_MODE_SEL_BITS 3 5082 #define TLB_TX_PRBS_GEN_CONFIG_PRBS_GEN_MODE_SEL_SHIFT 1 5083 5084 /* TLB_TX :: PRBS_GEN_CONFIG :: prbs_gen_en [00:00] */ 5085 #define TLB_TX_PRBS_GEN_CONFIG_PRBS_GEN_EN_MASK 0x0001 5086 #define TLB_TX_PRBS_GEN_CONFIG_PRBS_GEN_EN_ALIGN 0 5087 #define TLB_TX_PRBS_GEN_CONFIG_PRBS_GEN_EN_BITS 1 5088 #define TLB_TX_PRBS_GEN_CONFIG_PRBS_GEN_EN_SHIFT 0 5089 5090 5091 /**************************************************************************** 5092 * TLB_TX :: RMT_LPBK_CONFIG 5093 */ 5094 /* TLB_TX :: RMT_LPBK_CONFIG :: reserved0 [15:03] */ 5095 #define TLB_TX_RMT_LPBK_CONFIG_RESERVED0_MASK 0xfff8 5096 #define TLB_TX_RMT_LPBK_CONFIG_RESERVED0_ALIGN 0 5097 #define TLB_TX_RMT_LPBK_CONFIG_RESERVED0_BITS 13 5098 #define TLB_TX_RMT_LPBK_CONFIG_RESERVED0_SHIFT 3 5099 5100 /* TLB_TX :: RMT_LPBK_CONFIG :: rmt_lpbk_pd_frc_on [02:02] */ 5101 #define TLB_TX_RMT_LPBK_CONFIG_RMT_LPBK_PD_FRC_ON_MASK 0x0004 5102 #define TLB_TX_RMT_LPBK_CONFIG_RMT_LPBK_PD_FRC_ON_ALIGN 0 5103 #define TLB_TX_RMT_LPBK_CONFIG_RMT_LPBK_PD_FRC_ON_BITS 1 5104 #define TLB_TX_RMT_LPBK_CONFIG_RMT_LPBK_PD_FRC_ON_SHIFT 2 5105 5106 /* TLB_TX :: RMT_LPBK_CONFIG :: rmt_lpbk_pd_mode [01:01] */ 5107 #define TLB_TX_RMT_LPBK_CONFIG_RMT_LPBK_PD_MODE_MASK 0x0002 5108 #define TLB_TX_RMT_LPBK_CONFIG_RMT_LPBK_PD_MODE_ALIGN 0 5109 #define TLB_TX_RMT_LPBK_CONFIG_RMT_LPBK_PD_MODE_BITS 1 5110 #define TLB_TX_RMT_LPBK_CONFIG_RMT_LPBK_PD_MODE_SHIFT 1 5111 5112 /* TLB_TX :: RMT_LPBK_CONFIG :: rmt_lpbk_en [00:00] */ 5113 #define TLB_TX_RMT_LPBK_CONFIG_RMT_LPBK_EN_MASK 0x0001 5114 #define TLB_TX_RMT_LPBK_CONFIG_RMT_LPBK_EN_ALIGN 0 5115 #define TLB_TX_RMT_LPBK_CONFIG_RMT_LPBK_EN_BITS 1 5116 #define TLB_TX_RMT_LPBK_CONFIG_RMT_LPBK_EN_SHIFT 0 5117 5118 5119 /**************************************************************************** 5120 * TLB_TX :: TLB_TX_MISC_CONFIG 5121 */ 5122 /* TLB_TX :: TLB_TX_MISC_CONFIG :: reserved0 [15:03] */ 5123 #define TLB_TX_TLB_TX_MISC_CONFIG_RESERVED0_MASK 0xfff8 5124 #define TLB_TX_TLB_TX_MISC_CONFIG_RESERVED0_ALIGN 0 5125 #define TLB_TX_TLB_TX_MISC_CONFIG_RESERVED0_BITS 13 5126 #define TLB_TX_TLB_TX_MISC_CONFIG_RESERVED0_SHIFT 3 5127 5128 /* TLB_TX :: TLB_TX_MISC_CONFIG :: tx_mux_sel_order [02:02] */ 5129 #define TLB_TX_TLB_TX_MISC_CONFIG_TX_MUX_SEL_ORDER_MASK 0x0004 5130 #define TLB_TX_TLB_TX_MISC_CONFIG_TX_MUX_SEL_ORDER_ALIGN 0 5131 #define TLB_TX_TLB_TX_MISC_CONFIG_TX_MUX_SEL_ORDER_BITS 1 5132 #define TLB_TX_TLB_TX_MISC_CONFIG_TX_MUX_SEL_ORDER_SHIFT 2 5133 5134 /* TLB_TX :: TLB_TX_MISC_CONFIG :: tx_pcs_native_ana_frmt_en [01:01] */ 5135 #define TLB_TX_TLB_TX_MISC_CONFIG_TX_PCS_NATIVE_ANA_FRMT_EN_MASK 0x0002 5136 #define TLB_TX_TLB_TX_MISC_CONFIG_TX_PCS_NATIVE_ANA_FRMT_EN_ALIGN 0 5137 #define TLB_TX_TLB_TX_MISC_CONFIG_TX_PCS_NATIVE_ANA_FRMT_EN_BITS 1 5138 #define TLB_TX_TLB_TX_MISC_CONFIG_TX_PCS_NATIVE_ANA_FRMT_EN_SHIFT 1 5139 5140 /* TLB_TX :: TLB_TX_MISC_CONFIG :: tx_pmd_dp_invert [00:00] */ 5141 #define TLB_TX_TLB_TX_MISC_CONFIG_TX_PMD_DP_INVERT_MASK 0x0001 5142 #define TLB_TX_TLB_TX_MISC_CONFIG_TX_PMD_DP_INVERT_ALIGN 0 5143 #define TLB_TX_TLB_TX_MISC_CONFIG_TX_PMD_DP_INVERT_BITS 1 5144 #define TLB_TX_TLB_TX_MISC_CONFIG_TX_PMD_DP_INVERT_SHIFT 0 5145 5146 5147 /**************************************************************************** 5148 * TLB_TX :: TX_PI_LOOP_TIMING_CONFIG 5149 */ 5150 /* TLB_TX :: TX_PI_LOOP_TIMING_CONFIG :: reserved0 [15:01] */ 5151 #define TLB_TX_TX_PI_LOOP_TIMING_CONFIG_RESERVED0_MASK 0xfffe 5152 #define TLB_TX_TX_PI_LOOP_TIMING_CONFIG_RESERVED0_ALIGN 0 5153 #define TLB_TX_TX_PI_LOOP_TIMING_CONFIG_RESERVED0_BITS 15 5154 #define TLB_TX_TX_PI_LOOP_TIMING_CONFIG_RESERVED0_SHIFT 1 5155 5156 /* TLB_TX :: TX_PI_LOOP_TIMING_CONFIG :: tx_pi_loop_timing_src_sel [00:00] */ 5157 #define TLB_TX_TX_PI_LOOP_TIMING_CONFIG_TX_PI_LOOP_TIMING_SRC_SEL_MASK 0x0001 5158 #define TLB_TX_TX_PI_LOOP_TIMING_CONFIG_TX_PI_LOOP_TIMING_SRC_SEL_ALIGN 0 5159 #define TLB_TX_TX_PI_LOOP_TIMING_CONFIG_TX_PI_LOOP_TIMING_SRC_SEL_BITS 1 5160 #define TLB_TX_TX_PI_LOOP_TIMING_CONFIG_TX_PI_LOOP_TIMING_SRC_SEL_SHIFT 0 5161 5162 5163 /**************************************************************************** 5164 * TLB_TX :: RMT_LPBK_PD_STATUS 5165 */ 5166 /* TLB_TX :: RMT_LPBK_PD_STATUS :: reserved0 [15:02] */ 5167 #define TLB_TX_RMT_LPBK_PD_STATUS_RESERVED0_MASK 0xfffc 5168 #define TLB_TX_RMT_LPBK_PD_STATUS_RESERVED0_ALIGN 0 5169 #define TLB_TX_RMT_LPBK_PD_STATUS_RESERVED0_BITS 14 5170 #define TLB_TX_RMT_LPBK_PD_STATUS_RESERVED0_SHIFT 2 5171 5172 /* TLB_TX :: RMT_LPBK_PD_STATUS :: rmt_lpbk_pd_early_ind [01:01] */ 5173 #define TLB_TX_RMT_LPBK_PD_STATUS_RMT_LPBK_PD_EARLY_IND_MASK 0x0002 5174 #define TLB_TX_RMT_LPBK_PD_STATUS_RMT_LPBK_PD_EARLY_IND_ALIGN 0 5175 #define TLB_TX_RMT_LPBK_PD_STATUS_RMT_LPBK_PD_EARLY_IND_BITS 1 5176 #define TLB_TX_RMT_LPBK_PD_STATUS_RMT_LPBK_PD_EARLY_IND_SHIFT 1 5177 5178 /* TLB_TX :: RMT_LPBK_PD_STATUS :: rmt_lpbk_pd_late_ind [00:00] */ 5179 #define TLB_TX_RMT_LPBK_PD_STATUS_RMT_LPBK_PD_LATE_IND_MASK 0x0001 5180 #define TLB_TX_RMT_LPBK_PD_STATUS_RMT_LPBK_PD_LATE_IND_ALIGN 0 5181 #define TLB_TX_RMT_LPBK_PD_STATUS_RMT_LPBK_PD_LATE_IND_BITS 1 5182 #define TLB_TX_RMT_LPBK_PD_STATUS_RMT_LPBK_PD_LATE_IND_SHIFT 0 5183 5184 5185 /**************************************************************************** 5186 * eagle_tsc_dig_com_blk_DIG_COM 5187 */ 5188 /**************************************************************************** 5189 * DIG_COM :: REVID0 5190 */ 5191 /* DIG_COM :: REVID0 :: revid_rev_letter [15:14] */ 5192 #define DIG_COM_REVID0_REVID_REV_LETTER_MASK 0xc000 5193 #define DIG_COM_REVID0_REVID_REV_LETTER_ALIGN 0 5194 #define DIG_COM_REVID0_REVID_REV_LETTER_BITS 2 5195 #define DIG_COM_REVID0_REVID_REV_LETTER_SHIFT 14 5196 5197 /* DIG_COM :: REVID0 :: revid_rev_number [13:11] */ 5198 #define DIG_COM_REVID0_REVID_REV_NUMBER_MASK 0x3800 5199 #define DIG_COM_REVID0_REVID_REV_NUMBER_ALIGN 0 5200 #define DIG_COM_REVID0_REVID_REV_NUMBER_BITS 3 5201 #define DIG_COM_REVID0_REVID_REV_NUMBER_SHIFT 11 5202 5203 /* DIG_COM :: REVID0 :: revid_bonding [10:09] */ 5204 #define DIG_COM_REVID0_REVID_BONDING_MASK 0x0600 5205 #define DIG_COM_REVID0_REVID_BONDING_ALIGN 0 5206 #define DIG_COM_REVID0_REVID_BONDING_BITS 2 5207 #define DIG_COM_REVID0_REVID_BONDING_SHIFT 9 5208 5209 /* DIG_COM :: REVID0 :: revid_process [08:06] */ 5210 #define DIG_COM_REVID0_REVID_PROCESS_MASK 0x01c0 5211 #define DIG_COM_REVID0_REVID_PROCESS_ALIGN 0 5212 #define DIG_COM_REVID0_REVID_PROCESS_BITS 3 5213 #define DIG_COM_REVID0_REVID_PROCESS_SHIFT 6 5214 5215 /* DIG_COM :: REVID0 :: revid_model [05:00] */ 5216 #define DIG_COM_REVID0_REVID_MODEL_MASK 0x003f 5217 #define DIG_COM_REVID0_REVID_MODEL_ALIGN 0 5218 #define DIG_COM_REVID0_REVID_MODEL_BITS 6 5219 #define DIG_COM_REVID0_REVID_MODEL_SHIFT 0 5220 5221 5222 /**************************************************************************** 5223 * DIG_COM :: RESET_CONTROL_PMD 5224 */ 5225 /* DIG_COM :: RESET_CONTROL_PMD :: reserved0 [15:01] */ 5226 #define DIG_COM_RESET_CONTROL_PMD_RESERVED0_MASK 0xfffe 5227 #define DIG_COM_RESET_CONTROL_PMD_RESERVED0_ALIGN 0 5228 #define DIG_COM_RESET_CONTROL_PMD_RESERVED0_BITS 15 5229 #define DIG_COM_RESET_CONTROL_PMD_RESERVED0_SHIFT 1 5230 5231 /* DIG_COM :: RESET_CONTROL_PMD :: core_s_rstb [00:00] */ 5232 #define DIG_COM_RESET_CONTROL_PMD_CORE_S_RSTB_MASK 0x0001 5233 #define DIG_COM_RESET_CONTROL_PMD_CORE_S_RSTB_ALIGN 0 5234 #define DIG_COM_RESET_CONTROL_PMD_CORE_S_RSTB_BITS 1 5235 #define DIG_COM_RESET_CONTROL_PMD_CORE_S_RSTB_SHIFT 0 5236 5237 5238 /**************************************************************************** 5239 * DIG_COM :: RESET_CONTROL_CORE_DP 5240 */ 5241 /* DIG_COM :: RESET_CONTROL_CORE_DP :: reserved0 [15:15] */ 5242 #define DIG_COM_RESET_CONTROL_CORE_DP_RESERVED0_MASK 0x8000 5243 #define DIG_COM_RESET_CONTROL_CORE_DP_RESERVED0_ALIGN 0 5244 #define DIG_COM_RESET_CONTROL_CORE_DP_RESERVED0_BITS 1 5245 #define DIG_COM_RESET_CONTROL_CORE_DP_RESERVED0_SHIFT 15 5246 5247 /* DIG_COM :: RESET_CONTROL_CORE_DP :: tx_pi_loop_filter_stable [14:14] */ 5248 #define DIG_COM_RESET_CONTROL_CORE_DP_TX_PI_LOOP_FILTER_STABLE_MASK 0x4000 5249 #define DIG_COM_RESET_CONTROL_CORE_DP_TX_PI_LOOP_FILTER_STABLE_ALIGN 0 5250 #define DIG_COM_RESET_CONTROL_CORE_DP_TX_PI_LOOP_FILTER_STABLE_BITS 1 5251 #define DIG_COM_RESET_CONTROL_CORE_DP_TX_PI_LOOP_FILTER_STABLE_SHIFT 14 5252 5253 /* DIG_COM :: RESET_CONTROL_CORE_DP :: afe_s_pll_reset_frc [13:13] */ 5254 #define DIG_COM_RESET_CONTROL_CORE_DP_AFE_S_PLL_RESET_FRC_MASK 0x2000 5255 #define DIG_COM_RESET_CONTROL_CORE_DP_AFE_S_PLL_RESET_FRC_ALIGN 0 5256 #define DIG_COM_RESET_CONTROL_CORE_DP_AFE_S_PLL_RESET_FRC_BITS 1 5257 #define DIG_COM_RESET_CONTROL_CORE_DP_AFE_S_PLL_RESET_FRC_SHIFT 13 5258 5259 /* DIG_COM :: RESET_CONTROL_CORE_DP :: afe_s_pll_reset_frc_val [12:12] */ 5260 #define DIG_COM_RESET_CONTROL_CORE_DP_AFE_S_PLL_RESET_FRC_VAL_MASK 0x1000 5261 #define DIG_COM_RESET_CONTROL_CORE_DP_AFE_S_PLL_RESET_FRC_VAL_ALIGN 0 5262 #define DIG_COM_RESET_CONTROL_CORE_DP_AFE_S_PLL_RESET_FRC_VAL_BITS 1 5263 #define DIG_COM_RESET_CONTROL_CORE_DP_AFE_S_PLL_RESET_FRC_VAL_SHIFT 12 5264 5265 /* DIG_COM :: RESET_CONTROL_CORE_DP :: tx_s_clkgate_frc_on [11:11] */ 5266 #define DIG_COM_RESET_CONTROL_CORE_DP_TX_S_CLKGATE_FRC_ON_MASK 0x0800 5267 #define DIG_COM_RESET_CONTROL_CORE_DP_TX_S_CLKGATE_FRC_ON_ALIGN 0 5268 #define DIG_COM_RESET_CONTROL_CORE_DP_TX_S_CLKGATE_FRC_ON_BITS 1 5269 #define DIG_COM_RESET_CONTROL_CORE_DP_TX_S_CLKGATE_FRC_ON_SHIFT 11 5270 5271 /* DIG_COM :: RESET_CONTROL_CORE_DP :: tx_s_comclk_frc_on [10:10] */ 5272 #define DIG_COM_RESET_CONTROL_CORE_DP_TX_S_COMCLK_FRC_ON_MASK 0x0400 5273 #define DIG_COM_RESET_CONTROL_CORE_DP_TX_S_COMCLK_FRC_ON_ALIGN 0 5274 #define DIG_COM_RESET_CONTROL_CORE_DP_TX_S_COMCLK_FRC_ON_BITS 1 5275 #define DIG_COM_RESET_CONTROL_CORE_DP_TX_S_COMCLK_FRC_ON_SHIFT 10 5276 5277 /* DIG_COM :: RESET_CONTROL_CORE_DP :: tx_s_comclk_sel [09:09] */ 5278 #define DIG_COM_RESET_CONTROL_CORE_DP_TX_S_COMCLK_SEL_MASK 0x0200 5279 #define DIG_COM_RESET_CONTROL_CORE_DP_TX_S_COMCLK_SEL_ALIGN 0 5280 #define DIG_COM_RESET_CONTROL_CORE_DP_TX_S_COMCLK_SEL_BITS 1 5281 #define DIG_COM_RESET_CONTROL_CORE_DP_TX_S_COMCLK_SEL_SHIFT 9 5282 5283 /* DIG_COM :: RESET_CONTROL_CORE_DP :: pmd_tx_clk_vld_frc_val [08:08] */ 5284 #define DIG_COM_RESET_CONTROL_CORE_DP_PMD_TX_CLK_VLD_FRC_VAL_MASK 0x0100 5285 #define DIG_COM_RESET_CONTROL_CORE_DP_PMD_TX_CLK_VLD_FRC_VAL_ALIGN 0 5286 #define DIG_COM_RESET_CONTROL_CORE_DP_PMD_TX_CLK_VLD_FRC_VAL_BITS 1 5287 #define DIG_COM_RESET_CONTROL_CORE_DP_PMD_TX_CLK_VLD_FRC_VAL_SHIFT 8 5288 5289 /* DIG_COM :: RESET_CONTROL_CORE_DP :: pmd_tx_clk_vld_frc [07:07] */ 5290 #define DIG_COM_RESET_CONTROL_CORE_DP_PMD_TX_CLK_VLD_FRC_MASK 0x0080 5291 #define DIG_COM_RESET_CONTROL_CORE_DP_PMD_TX_CLK_VLD_FRC_ALIGN 0 5292 #define DIG_COM_RESET_CONTROL_CORE_DP_PMD_TX_CLK_VLD_FRC_BITS 1 5293 #define DIG_COM_RESET_CONTROL_CORE_DP_PMD_TX_CLK_VLD_FRC_SHIFT 7 5294 5295 /* DIG_COM :: RESET_CONTROL_CORE_DP :: reserved1 [06:06] */ 5296 #define DIG_COM_RESET_CONTROL_CORE_DP_RESERVED1_MASK 0x0040 5297 #define DIG_COM_RESET_CONTROL_CORE_DP_RESERVED1_ALIGN 0 5298 #define DIG_COM_RESET_CONTROL_CORE_DP_RESERVED1_BITS 1 5299 #define DIG_COM_RESET_CONTROL_CORE_DP_RESERVED1_SHIFT 6 5300 5301 /* DIG_COM :: RESET_CONTROL_CORE_DP :: pmd_mdio_trans_pkill [05:05] */ 5302 #define DIG_COM_RESET_CONTROL_CORE_DP_PMD_MDIO_TRANS_PKILL_MASK 0x0020 5303 #define DIG_COM_RESET_CONTROL_CORE_DP_PMD_MDIO_TRANS_PKILL_ALIGN 0 5304 #define DIG_COM_RESET_CONTROL_CORE_DP_PMD_MDIO_TRANS_PKILL_BITS 1 5305 #define DIG_COM_RESET_CONTROL_CORE_DP_PMD_MDIO_TRANS_PKILL_SHIFT 5 5306 5307 /* DIG_COM :: RESET_CONTROL_CORE_DP :: sup_rst_seq_frc [04:04] */ 5308 #define DIG_COM_RESET_CONTROL_CORE_DP_SUP_RST_SEQ_FRC_MASK 0x0010 5309 #define DIG_COM_RESET_CONTROL_CORE_DP_SUP_RST_SEQ_FRC_ALIGN 0 5310 #define DIG_COM_RESET_CONTROL_CORE_DP_SUP_RST_SEQ_FRC_BITS 1 5311 #define DIG_COM_RESET_CONTROL_CORE_DP_SUP_RST_SEQ_FRC_SHIFT 4 5312 5313 /* DIG_COM :: RESET_CONTROL_CORE_DP :: sup_rst_seq_frc_val [03:03] */ 5314 #define DIG_COM_RESET_CONTROL_CORE_DP_SUP_RST_SEQ_FRC_VAL_MASK 0x0008 5315 #define DIG_COM_RESET_CONTROL_CORE_DP_SUP_RST_SEQ_FRC_VAL_ALIGN 0 5316 #define DIG_COM_RESET_CONTROL_CORE_DP_SUP_RST_SEQ_FRC_VAL_BITS 1 5317 #define DIG_COM_RESET_CONTROL_CORE_DP_SUP_RST_SEQ_FRC_VAL_SHIFT 3 5318 5319 /* DIG_COM :: RESET_CONTROL_CORE_DP :: reserved2 [02:02] */ 5320 #define DIG_COM_RESET_CONTROL_CORE_DP_RESERVED2_MASK 0x0004 5321 #define DIG_COM_RESET_CONTROL_CORE_DP_RESERVED2_ALIGN 0 5322 #define DIG_COM_RESET_CONTROL_CORE_DP_RESERVED2_BITS 1 5323 #define DIG_COM_RESET_CONTROL_CORE_DP_RESERVED2_SHIFT 2 5324 5325 /* DIG_COM :: RESET_CONTROL_CORE_DP :: pmd_core_dp_h_rstb_pkill [01:01] */ 5326 #define DIG_COM_RESET_CONTROL_CORE_DP_PMD_CORE_DP_H_RSTB_PKILL_MASK 0x0002 5327 #define DIG_COM_RESET_CONTROL_CORE_DP_PMD_CORE_DP_H_RSTB_PKILL_ALIGN 0 5328 #define DIG_COM_RESET_CONTROL_CORE_DP_PMD_CORE_DP_H_RSTB_PKILL_BITS 1 5329 #define DIG_COM_RESET_CONTROL_CORE_DP_PMD_CORE_DP_H_RSTB_PKILL_SHIFT 1 5330 5331 /* DIG_COM :: RESET_CONTROL_CORE_DP :: reserved3 [00:00] */ 5332 #define DIG_COM_RESET_CONTROL_CORE_DP_RESERVED3_MASK 0x0001 5333 #define DIG_COM_RESET_CONTROL_CORE_DP_RESERVED3_ALIGN 0 5334 #define DIG_COM_RESET_CONTROL_CORE_DP_RESERVED3_BITS 1 5335 #define DIG_COM_RESET_CONTROL_CORE_DP_RESERVED3_SHIFT 0 5336 5337 5338 /**************************************************************************** 5339 * DIG_COM :: CORE_MULTICAST_MASK_CONRTOL 5340 */ 5341 /* DIG_COM :: CORE_MULTICAST_MASK_CONRTOL :: reserved0 [15:04] */ 5342 #define DIG_COM_CORE_MULTICAST_MASK_CONRTOL_RESERVED0_MASK 0xfff0 5343 #define DIG_COM_CORE_MULTICAST_MASK_CONRTOL_RESERVED0_ALIGN 0 5344 #define DIG_COM_CORE_MULTICAST_MASK_CONRTOL_RESERVED0_BITS 12 5345 #define DIG_COM_CORE_MULTICAST_MASK_CONRTOL_RESERVED0_SHIFT 4 5346 5347 /* DIG_COM :: CORE_MULTICAST_MASK_CONRTOL :: core_multicast_mask_control [03:00] */ 5348 #define DIG_COM_CORE_MULTICAST_MASK_CONRTOL_CORE_MULTICAST_MASK_CONTROL_MASK 0x000f 5349 #define DIG_COM_CORE_MULTICAST_MASK_CONRTOL_CORE_MULTICAST_MASK_CONTROL_ALIGN 0 5350 #define DIG_COM_CORE_MULTICAST_MASK_CONRTOL_CORE_MULTICAST_MASK_CONTROL_BITS 4 5351 #define DIG_COM_CORE_MULTICAST_MASK_CONRTOL_CORE_MULTICAST_MASK_CONTROL_SHIFT 0 5352 5353 5354 /**************************************************************************** 5355 * DIG_COM :: TOP_USER_CONTROL_0 5356 */ 5357 /* DIG_COM :: TOP_USER_CONTROL_0 :: uc_active [15:15] */ 5358 #define DIG_COM_TOP_USER_CONTROL_0_UC_ACTIVE_MASK 0x8000 5359 #define DIG_COM_TOP_USER_CONTROL_0_UC_ACTIVE_ALIGN 0 5360 #define DIG_COM_TOP_USER_CONTROL_0_UC_ACTIVE_BITS 1 5361 #define DIG_COM_TOP_USER_CONTROL_0_UC_ACTIVE_SHIFT 15 5362 5363 /* DIG_COM :: TOP_USER_CONTROL_0 :: afe_s_pll_pwrdn [14:14] */ 5364 #define DIG_COM_TOP_USER_CONTROL_0_AFE_S_PLL_PWRDN_MASK 0x4000 5365 #define DIG_COM_TOP_USER_CONTROL_0_AFE_S_PLL_PWRDN_ALIGN 0 5366 #define DIG_COM_TOP_USER_CONTROL_0_AFE_S_PLL_PWRDN_BITS 1 5367 #define DIG_COM_TOP_USER_CONTROL_0_AFE_S_PLL_PWRDN_SHIFT 14 5368 5369 /* DIG_COM :: TOP_USER_CONTROL_0 :: core_dp_s_rstb [13:13] */ 5370 #define DIG_COM_TOP_USER_CONTROL_0_CORE_DP_S_RSTB_MASK 0x2000 5371 #define DIG_COM_TOP_USER_CONTROL_0_CORE_DP_S_RSTB_ALIGN 0 5372 #define DIG_COM_TOP_USER_CONTROL_0_CORE_DP_S_RSTB_BITS 1 5373 #define DIG_COM_TOP_USER_CONTROL_0_CORE_DP_S_RSTB_SHIFT 13 5374 5375 /* DIG_COM :: TOP_USER_CONTROL_0 :: reserved0 [12:10] */ 5376 #define DIG_COM_TOP_USER_CONTROL_0_RESERVED0_MASK 0x1c00 5377 #define DIG_COM_TOP_USER_CONTROL_0_RESERVED0_ALIGN 0 5378 #define DIG_COM_TOP_USER_CONTROL_0_RESERVED0_BITS 3 5379 #define DIG_COM_TOP_USER_CONTROL_0_RESERVED0_SHIFT 10 5380 5381 /* DIG_COM :: TOP_USER_CONTROL_0 :: heartbeat_count_1us [09:00] */ 5382 #define DIG_COM_TOP_USER_CONTROL_0_HEARTBEAT_COUNT_1US_MASK 0x03ff 5383 #define DIG_COM_TOP_USER_CONTROL_0_HEARTBEAT_COUNT_1US_ALIGN 0 5384 #define DIG_COM_TOP_USER_CONTROL_0_HEARTBEAT_COUNT_1US_BITS 10 5385 #define DIG_COM_TOP_USER_CONTROL_0_HEARTBEAT_COUNT_1US_SHIFT 0 5386 5387 5388 /**************************************************************************** 5389 * DIG_COM :: UC_ACK_CORE_CONTROL 5390 */ 5391 /* DIG_COM :: UC_ACK_CORE_CONTROL :: reserved0 [15:02] */ 5392 #define DIG_COM_UC_ACK_CORE_CONTROL_RESERVED0_MASK 0xfffc 5393 #define DIG_COM_UC_ACK_CORE_CONTROL_RESERVED0_ALIGN 0 5394 #define DIG_COM_UC_ACK_CORE_CONTROL_RESERVED0_BITS 14 5395 #define DIG_COM_UC_ACK_CORE_CONTROL_RESERVED0_SHIFT 2 5396 5397 /* DIG_COM :: UC_ACK_CORE_CONTROL :: uc_ack_core_dp_reset [01:01] */ 5398 #define DIG_COM_UC_ACK_CORE_CONTROL_UC_ACK_CORE_DP_RESET_MASK 0x0002 5399 #define DIG_COM_UC_ACK_CORE_CONTROL_UC_ACK_CORE_DP_RESET_ALIGN 0 5400 #define DIG_COM_UC_ACK_CORE_CONTROL_UC_ACK_CORE_DP_RESET_BITS 1 5401 #define DIG_COM_UC_ACK_CORE_CONTROL_UC_ACK_CORE_DP_RESET_SHIFT 1 5402 5403 /* DIG_COM :: UC_ACK_CORE_CONTROL :: uc_ack_core_cfg_done [00:00] */ 5404 #define DIG_COM_UC_ACK_CORE_CONTROL_UC_ACK_CORE_CFG_DONE_MASK 0x0001 5405 #define DIG_COM_UC_ACK_CORE_CONTROL_UC_ACK_CORE_CFG_DONE_ALIGN 0 5406 #define DIG_COM_UC_ACK_CORE_CONTROL_UC_ACK_CORE_CFG_DONE_BITS 1 5407 #define DIG_COM_UC_ACK_CORE_CONTROL_UC_ACK_CORE_CFG_DONE_SHIFT 0 5408 5409 5410 /**************************************************************************** 5411 * DIG_COM :: CORE_REG_RESET_OCCURRED_CONTROL 5412 */ 5413 /* DIG_COM :: CORE_REG_RESET_OCCURRED_CONTROL :: reserved0 [15:01] */ 5414 #define DIG_COM_CORE_REG_RESET_OCCURRED_CONTROL_RESERVED0_MASK 0xfffe 5415 #define DIG_COM_CORE_REG_RESET_OCCURRED_CONTROL_RESERVED0_ALIGN 0 5416 #define DIG_COM_CORE_REG_RESET_OCCURRED_CONTROL_RESERVED0_BITS 15 5417 #define DIG_COM_CORE_REG_RESET_OCCURRED_CONTROL_RESERVED0_SHIFT 1 5418 5419 /* DIG_COM :: CORE_REG_RESET_OCCURRED_CONTROL :: core_reg_reset_occurred [00:00] */ 5420 #define DIG_COM_CORE_REG_RESET_OCCURRED_CONTROL_CORE_REG_RESET_OCCURRED_MASK 0x0001 5421 #define DIG_COM_CORE_REG_RESET_OCCURRED_CONTROL_CORE_REG_RESET_OCCURRED_ALIGN 0 5422 #define DIG_COM_CORE_REG_RESET_OCCURRED_CONTROL_CORE_REG_RESET_OCCURRED_BITS 1 5423 #define DIG_COM_CORE_REG_RESET_OCCURRED_CONTROL_CORE_REG_RESET_OCCURRED_SHIFT 0 5424 5425 5426 /**************************************************************************** 5427 * DIG_COM :: RST_SEQ_TIMER_CONTROL 5428 */ 5429 /* DIG_COM :: RST_SEQ_TIMER_CONTROL :: rst_seq_dis_flt_mode [15:14] */ 5430 #define DIG_COM_RST_SEQ_TIMER_CONTROL_RST_SEQ_DIS_FLT_MODE_MASK 0xc000 5431 #define DIG_COM_RST_SEQ_TIMER_CONTROL_RST_SEQ_DIS_FLT_MODE_ALIGN 0 5432 #define DIG_COM_RST_SEQ_TIMER_CONTROL_RST_SEQ_DIS_FLT_MODE_BITS 2 5433 #define DIG_COM_RST_SEQ_TIMER_CONTROL_RST_SEQ_DIS_FLT_MODE_SHIFT 14 5434 5435 /* DIG_COM :: RST_SEQ_TIMER_CONTROL :: reserved0 [13:11] */ 5436 #define DIG_COM_RST_SEQ_TIMER_CONTROL_RESERVED0_MASK 0x3800 5437 #define DIG_COM_RST_SEQ_TIMER_CONTROL_RESERVED0_ALIGN 0 5438 #define DIG_COM_RST_SEQ_TIMER_CONTROL_RESERVED0_BITS 3 5439 #define DIG_COM_RST_SEQ_TIMER_CONTROL_RESERVED0_SHIFT 11 5440 5441 /* DIG_COM :: RST_SEQ_TIMER_CONTROL :: pwrdn_seq_timer [10:08] */ 5442 #define DIG_COM_RST_SEQ_TIMER_CONTROL_PWRDN_SEQ_TIMER_MASK 0x0700 5443 #define DIG_COM_RST_SEQ_TIMER_CONTROL_PWRDN_SEQ_TIMER_ALIGN 0 5444 #define DIG_COM_RST_SEQ_TIMER_CONTROL_PWRDN_SEQ_TIMER_BITS 3 5445 #define DIG_COM_RST_SEQ_TIMER_CONTROL_PWRDN_SEQ_TIMER_SHIFT 8 5446 5447 /* DIG_COM :: RST_SEQ_TIMER_CONTROL :: reserved1 [07:03] */ 5448 #define DIG_COM_RST_SEQ_TIMER_CONTROL_RESERVED1_MASK 0x00f8 5449 #define DIG_COM_RST_SEQ_TIMER_CONTROL_RESERVED1_ALIGN 0 5450 #define DIG_COM_RST_SEQ_TIMER_CONTROL_RESERVED1_BITS 5 5451 #define DIG_COM_RST_SEQ_TIMER_CONTROL_RESERVED1_SHIFT 3 5452 5453 /* DIG_COM :: RST_SEQ_TIMER_CONTROL :: rst_seq_timer [02:00] */ 5454 #define DIG_COM_RST_SEQ_TIMER_CONTROL_RST_SEQ_TIMER_MASK 0x0007 5455 #define DIG_COM_RST_SEQ_TIMER_CONTROL_RST_SEQ_TIMER_ALIGN 0 5456 #define DIG_COM_RST_SEQ_TIMER_CONTROL_RST_SEQ_TIMER_BITS 3 5457 #define DIG_COM_RST_SEQ_TIMER_CONTROL_RST_SEQ_TIMER_SHIFT 0 5458 5459 5460 /**************************************************************************** 5461 * DIG_COM :: CORE_DP_RESET_STATE_STATUS 5462 */ 5463 /* DIG_COM :: CORE_DP_RESET_STATE_STATUS :: reserved0 [15:15] */ 5464 #define DIG_COM_CORE_DP_RESET_STATE_STATUS_RESERVED0_MASK 0x8000 5465 #define DIG_COM_CORE_DP_RESET_STATE_STATUS_RESERVED0_ALIGN 0 5466 #define DIG_COM_CORE_DP_RESET_STATE_STATUS_RESERVED0_BITS 1 5467 #define DIG_COM_CORE_DP_RESET_STATE_STATUS_RESERVED0_SHIFT 15 5468 5469 /* DIG_COM :: CORE_DP_RESET_STATE_STATUS :: lane_reset_released [14:14] */ 5470 #define DIG_COM_CORE_DP_RESET_STATE_STATUS_LANE_RESET_RELEASED_MASK 0x4000 5471 #define DIG_COM_CORE_DP_RESET_STATE_STATUS_LANE_RESET_RELEASED_ALIGN 0 5472 #define DIG_COM_CORE_DP_RESET_STATE_STATUS_LANE_RESET_RELEASED_BITS 1 5473 #define DIG_COM_CORE_DP_RESET_STATE_STATUS_LANE_RESET_RELEASED_SHIFT 14 5474 5475 /* DIG_COM :: CORE_DP_RESET_STATE_STATUS :: reserved1 [13:13] */ 5476 #define DIG_COM_CORE_DP_RESET_STATE_STATUS_RESERVED1_MASK 0x2000 5477 #define DIG_COM_CORE_DP_RESET_STATE_STATUS_RESERVED1_ALIGN 0 5478 #define DIG_COM_CORE_DP_RESET_STATE_STATUS_RESERVED1_BITS 1 5479 #define DIG_COM_CORE_DP_RESET_STATE_STATUS_RESERVED1_SHIFT 13 5480 5481 /* DIG_COM :: CORE_DP_RESET_STATE_STATUS :: lane_reset_released_index [12:08] */ 5482 #define DIG_COM_CORE_DP_RESET_STATE_STATUS_LANE_RESET_RELEASED_INDEX_MASK 0x1f00 5483 #define DIG_COM_CORE_DP_RESET_STATE_STATUS_LANE_RESET_RELEASED_INDEX_ALIGN 0 5484 #define DIG_COM_CORE_DP_RESET_STATE_STATUS_LANE_RESET_RELEASED_INDEX_BITS 5 5485 #define DIG_COM_CORE_DP_RESET_STATE_STATUS_LANE_RESET_RELEASED_INDEX_SHIFT 8 5486 5487 /* DIG_COM :: CORE_DP_RESET_STATE_STATUS :: reserved2 [07:03] */ 5488 #define DIG_COM_CORE_DP_RESET_STATE_STATUS_RESERVED2_MASK 0x00f8 5489 #define DIG_COM_CORE_DP_RESET_STATE_STATUS_RESERVED2_ALIGN 0 5490 #define DIG_COM_CORE_DP_RESET_STATE_STATUS_RESERVED2_BITS 5 5491 #define DIG_COM_CORE_DP_RESET_STATE_STATUS_RESERVED2_SHIFT 3 5492 5493 /* DIG_COM :: CORE_DP_RESET_STATE_STATUS :: core_dp_reset_state [02:00] */ 5494 #define DIG_COM_CORE_DP_RESET_STATE_STATUS_CORE_DP_RESET_STATE_MASK 0x0007 5495 #define DIG_COM_CORE_DP_RESET_STATE_STATUS_CORE_DP_RESET_STATE_ALIGN 0 5496 #define DIG_COM_CORE_DP_RESET_STATE_STATUS_CORE_DP_RESET_STATE_BITS 3 5497 #define DIG_COM_CORE_DP_RESET_STATE_STATUS_CORE_DP_RESET_STATE_SHIFT 0 5498 5499 5500 /**************************************************************************** 5501 * DIG_COM :: PMD_CORE_MODE_STATUS 5502 */ 5503 /* DIG_COM :: PMD_CORE_MODE_STATUS :: pmd_core_mode [15:00] */ 5504 #define DIG_COM_PMD_CORE_MODE_STATUS_PMD_CORE_MODE_MASK 0xffff 5505 #define DIG_COM_PMD_CORE_MODE_STATUS_PMD_CORE_MODE_ALIGN 0 5506 #define DIG_COM_PMD_CORE_MODE_STATUS_PMD_CORE_MODE_BITS 16 5507 #define DIG_COM_PMD_CORE_MODE_STATUS_PMD_CORE_MODE_SHIFT 0 5508 5509 5510 /**************************************************************************** 5511 * DIG_COM :: REVID1 5512 */ 5513 /* DIG_COM :: REVID1 :: revid_multiplicity [15:12] */ 5514 #define DIG_COM_REVID1_REVID_MULTIPLICITY_MASK 0xf000 5515 #define DIG_COM_REVID1_REVID_MULTIPLICITY_ALIGN 0 5516 #define DIG_COM_REVID1_REVID_MULTIPLICITY_BITS 4 5517 #define DIG_COM_REVID1_REVID_MULTIPLICITY_SHIFT 12 5518 5519 /* DIG_COM :: REVID1 :: reserved0 [11:06] */ 5520 #define DIG_COM_REVID1_RESERVED0_MASK 0x0fc0 5521 #define DIG_COM_REVID1_RESERVED0_ALIGN 0 5522 #define DIG_COM_REVID1_RESERVED0_BITS 6 5523 #define DIG_COM_REVID1_RESERVED0_SHIFT 6 5524 5525 /* DIG_COM :: REVID1 :: revid_mdio [05:05] */ 5526 #define DIG_COM_REVID1_REVID_MDIO_MASK 0x0020 5527 #define DIG_COM_REVID1_REVID_MDIO_ALIGN 0 5528 #define DIG_COM_REVID1_REVID_MDIO_BITS 1 5529 #define DIG_COM_REVID1_REVID_MDIO_SHIFT 5 5530 5531 /* DIG_COM :: REVID1 :: revid_micro [04:04] */ 5532 #define DIG_COM_REVID1_REVID_MICRO_MASK 0x0010 5533 #define DIG_COM_REVID1_REVID_MICRO_ALIGN 0 5534 #define DIG_COM_REVID1_REVID_MICRO_BITS 1 5535 #define DIG_COM_REVID1_REVID_MICRO_SHIFT 4 5536 5537 /* DIG_COM :: REVID1 :: revid_cl72 [03:03] */ 5538 #define DIG_COM_REVID1_REVID_CL72_MASK 0x0008 5539 #define DIG_COM_REVID1_REVID_CL72_ALIGN 0 5540 #define DIG_COM_REVID1_REVID_CL72_BITS 1 5541 #define DIG_COM_REVID1_REVID_CL72_SHIFT 3 5542 5543 /* DIG_COM :: REVID1 :: revid_pir [02:02] */ 5544 #define DIG_COM_REVID1_REVID_PIR_MASK 0x0004 5545 #define DIG_COM_REVID1_REVID_PIR_ALIGN 0 5546 #define DIG_COM_REVID1_REVID_PIR_BITS 1 5547 #define DIG_COM_REVID1_REVID_PIR_SHIFT 2 5548 5549 /* DIG_COM :: REVID1 :: revid_llp [01:01] */ 5550 #define DIG_COM_REVID1_REVID_LLP_MASK 0x0002 5551 #define DIG_COM_REVID1_REVID_LLP_ALIGN 0 5552 #define DIG_COM_REVID1_REVID_LLP_BITS 1 5553 #define DIG_COM_REVID1_REVID_LLP_SHIFT 1 5554 5555 /* DIG_COM :: REVID1 :: revid_eee [00:00] */ 5556 #define DIG_COM_REVID1_REVID_EEE_MASK 0x0001 5557 #define DIG_COM_REVID1_REVID_EEE_ALIGN 0 5558 #define DIG_COM_REVID1_REVID_EEE_BITS 1 5559 #define DIG_COM_REVID1_REVID_EEE_SHIFT 0 5560 5561 5562 /**************************************************************************** 5563 * DIG_COM :: TX_LANE_MAP_0_1_2 5564 */ 5565 /* DIG_COM :: TX_LANE_MAP_0_1_2 :: reserved0 [15:15] */ 5566 #define DIG_COM_TX_LANE_MAP_0_1_2_RESERVED0_MASK 0x8000 5567 #define DIG_COM_TX_LANE_MAP_0_1_2_RESERVED0_ALIGN 0 5568 #define DIG_COM_TX_LANE_MAP_0_1_2_RESERVED0_BITS 1 5569 #define DIG_COM_TX_LANE_MAP_0_1_2_RESERVED0_SHIFT 15 5570 5571 /* DIG_COM :: TX_LANE_MAP_0_1_2 :: tx_lane_map_2 [14:10] */ 5572 #define DIG_COM_TX_LANE_MAP_0_1_2_TX_LANE_MAP_2_MASK 0x7c00 5573 #define DIG_COM_TX_LANE_MAP_0_1_2_TX_LANE_MAP_2_ALIGN 0 5574 #define DIG_COM_TX_LANE_MAP_0_1_2_TX_LANE_MAP_2_BITS 5 5575 #define DIG_COM_TX_LANE_MAP_0_1_2_TX_LANE_MAP_2_SHIFT 10 5576 5577 /* DIG_COM :: TX_LANE_MAP_0_1_2 :: tx_lane_map_1 [09:05] */ 5578 #define DIG_COM_TX_LANE_MAP_0_1_2_TX_LANE_MAP_1_MASK 0x03e0 5579 #define DIG_COM_TX_LANE_MAP_0_1_2_TX_LANE_MAP_1_ALIGN 0 5580 #define DIG_COM_TX_LANE_MAP_0_1_2_TX_LANE_MAP_1_BITS 5 5581 #define DIG_COM_TX_LANE_MAP_0_1_2_TX_LANE_MAP_1_SHIFT 5 5582 5583 /* DIG_COM :: TX_LANE_MAP_0_1_2 :: tx_lane_map_0 [04:00] */ 5584 #define DIG_COM_TX_LANE_MAP_0_1_2_TX_LANE_MAP_0_MASK 0x001f 5585 #define DIG_COM_TX_LANE_MAP_0_1_2_TX_LANE_MAP_0_ALIGN 0 5586 #define DIG_COM_TX_LANE_MAP_0_1_2_TX_LANE_MAP_0_BITS 5 5587 #define DIG_COM_TX_LANE_MAP_0_1_2_TX_LANE_MAP_0_SHIFT 0 5588 5589 5590 /**************************************************************************** 5591 * DIG_COM :: TX_LANE_MAP_3_N_LANE_ADDR_0_1 5592 */ 5593 /* DIG_COM :: TX_LANE_MAP_3_N_LANE_ADDR_0_1 :: reserved0 [15:15] */ 5594 #define DIG_COM_TX_LANE_MAP_3_N_LANE_ADDR_0_1_RESERVED0_MASK 0x8000 5595 #define DIG_COM_TX_LANE_MAP_3_N_LANE_ADDR_0_1_RESERVED0_ALIGN 0 5596 #define DIG_COM_TX_LANE_MAP_3_N_LANE_ADDR_0_1_RESERVED0_BITS 1 5597 #define DIG_COM_TX_LANE_MAP_3_N_LANE_ADDR_0_1_RESERVED0_SHIFT 15 5598 5599 /* DIG_COM :: TX_LANE_MAP_3_N_LANE_ADDR_0_1 :: lane_addr_1 [14:10] */ 5600 #define DIG_COM_TX_LANE_MAP_3_N_LANE_ADDR_0_1_LANE_ADDR_1_MASK 0x7c00 5601 #define DIG_COM_TX_LANE_MAP_3_N_LANE_ADDR_0_1_LANE_ADDR_1_ALIGN 0 5602 #define DIG_COM_TX_LANE_MAP_3_N_LANE_ADDR_0_1_LANE_ADDR_1_BITS 5 5603 #define DIG_COM_TX_LANE_MAP_3_N_LANE_ADDR_0_1_LANE_ADDR_1_SHIFT 10 5604 5605 /* DIG_COM :: TX_LANE_MAP_3_N_LANE_ADDR_0_1 :: lane_addr_0 [09:05] */ 5606 #define DIG_COM_TX_LANE_MAP_3_N_LANE_ADDR_0_1_LANE_ADDR_0_MASK 0x03e0 5607 #define DIG_COM_TX_LANE_MAP_3_N_LANE_ADDR_0_1_LANE_ADDR_0_ALIGN 0 5608 #define DIG_COM_TX_LANE_MAP_3_N_LANE_ADDR_0_1_LANE_ADDR_0_BITS 5 5609 #define DIG_COM_TX_LANE_MAP_3_N_LANE_ADDR_0_1_LANE_ADDR_0_SHIFT 5 5610 5611 /* DIG_COM :: TX_LANE_MAP_3_N_LANE_ADDR_0_1 :: tx_lane_map_3 [04:00] */ 5612 #define DIG_COM_TX_LANE_MAP_3_N_LANE_ADDR_0_1_TX_LANE_MAP_3_MASK 0x001f 5613 #define DIG_COM_TX_LANE_MAP_3_N_LANE_ADDR_0_1_TX_LANE_MAP_3_ALIGN 0 5614 #define DIG_COM_TX_LANE_MAP_3_N_LANE_ADDR_0_1_TX_LANE_MAP_3_BITS 5 5615 #define DIG_COM_TX_LANE_MAP_3_N_LANE_ADDR_0_1_TX_LANE_MAP_3_SHIFT 0 5616 5617 5618 /**************************************************************************** 5619 * DIG_COM :: LANE_ADDR_2_3 5620 */ 5621 /* DIG_COM :: LANE_ADDR_2_3 :: reserved0 [15:13] */ 5622 #define DIG_COM_LANE_ADDR_2_3_RESERVED0_MASK 0xe000 5623 #define DIG_COM_LANE_ADDR_2_3_RESERVED0_ALIGN 0 5624 #define DIG_COM_LANE_ADDR_2_3_RESERVED0_BITS 3 5625 #define DIG_COM_LANE_ADDR_2_3_RESERVED0_SHIFT 13 5626 5627 /* DIG_COM :: LANE_ADDR_2_3 :: lane_addr_3 [12:08] */ 5628 #define DIG_COM_LANE_ADDR_2_3_LANE_ADDR_3_MASK 0x1f00 5629 #define DIG_COM_LANE_ADDR_2_3_LANE_ADDR_3_ALIGN 0 5630 #define DIG_COM_LANE_ADDR_2_3_LANE_ADDR_3_BITS 5 5631 #define DIG_COM_LANE_ADDR_2_3_LANE_ADDR_3_SHIFT 8 5632 5633 /* DIG_COM :: LANE_ADDR_2_3 :: reserved1 [07:05] */ 5634 #define DIG_COM_LANE_ADDR_2_3_RESERVED1_MASK 0x00e0 5635 #define DIG_COM_LANE_ADDR_2_3_RESERVED1_ALIGN 0 5636 #define DIG_COM_LANE_ADDR_2_3_RESERVED1_BITS 3 5637 #define DIG_COM_LANE_ADDR_2_3_RESERVED1_SHIFT 5 5638 5639 /* DIG_COM :: LANE_ADDR_2_3 :: lane_addr_2 [04:00] */ 5640 #define DIG_COM_LANE_ADDR_2_3_LANE_ADDR_2_MASK 0x001f 5641 #define DIG_COM_LANE_ADDR_2_3_LANE_ADDR_2_ALIGN 0 5642 #define DIG_COM_LANE_ADDR_2_3_LANE_ADDR_2_BITS 5 5643 #define DIG_COM_LANE_ADDR_2_3_LANE_ADDR_2_SHIFT 0 5644 5645 5646 /**************************************************************************** 5647 * DIG_COM :: REVID2 5648 */ 5649 /* DIG_COM :: REVID2 :: reserved0 [15:04] */ 5650 #define DIG_COM_REVID2_RESERVED0_MASK 0xfff0 5651 #define DIG_COM_REVID2_RESERVED0_ALIGN 0 5652 #define DIG_COM_REVID2_RESERVED0_BITS 12 5653 #define DIG_COM_REVID2_RESERVED0_SHIFT 4 5654 5655 /* DIG_COM :: REVID2 :: revid2 [03:00] */ 5656 #define DIG_COM_REVID2_REVID2_MASK 0x000f 5657 #define DIG_COM_REVID2_REVID2_ALIGN 0 5658 #define DIG_COM_REVID2_REVID2_BITS 4 5659 #define DIG_COM_REVID2_REVID2_SHIFT 0 5660 5661 5662 /**************************************************************************** 5663 * eagle_tsc_patt_gen_blk_PATT_GEN_COM 5664 */ 5665 /**************************************************************************** 5666 * PATT_GEN_COM :: SEQ_0 5667 */ 5668 /* PATT_GEN_COM :: SEQ_0 :: patt_gen_seq_0 [15:00] */ 5669 #define PATT_GEN_COM_SEQ_0_PATT_GEN_SEQ_0_MASK 0xffff 5670 #define PATT_GEN_COM_SEQ_0_PATT_GEN_SEQ_0_ALIGN 0 5671 #define PATT_GEN_COM_SEQ_0_PATT_GEN_SEQ_0_BITS 16 5672 #define PATT_GEN_COM_SEQ_0_PATT_GEN_SEQ_0_SHIFT 0 5673 5674 5675 /**************************************************************************** 5676 * PATT_GEN_COM :: SEQ_1 5677 */ 5678 /* PATT_GEN_COM :: SEQ_1 :: patt_gen_seq_1 [15:00] */ 5679 #define PATT_GEN_COM_SEQ_1_PATT_GEN_SEQ_1_MASK 0xffff 5680 #define PATT_GEN_COM_SEQ_1_PATT_GEN_SEQ_1_ALIGN 0 5681 #define PATT_GEN_COM_SEQ_1_PATT_GEN_SEQ_1_BITS 16 5682 #define PATT_GEN_COM_SEQ_1_PATT_GEN_SEQ_1_SHIFT 0 5683 5684 5685 /**************************************************************************** 5686 * PATT_GEN_COM :: SEQ_2 5687 */ 5688 /* PATT_GEN_COM :: SEQ_2 :: patt_gen_seq_2 [15:00] */ 5689 #define PATT_GEN_COM_SEQ_2_PATT_GEN_SEQ_2_MASK 0xffff 5690 #define PATT_GEN_COM_SEQ_2_PATT_GEN_SEQ_2_ALIGN 0 5691 #define PATT_GEN_COM_SEQ_2_PATT_GEN_SEQ_2_BITS 16 5692 #define PATT_GEN_COM_SEQ_2_PATT_GEN_SEQ_2_SHIFT 0 5693 5694 5695 /**************************************************************************** 5696 * PATT_GEN_COM :: SEQ_3 5697 */ 5698 /* PATT_GEN_COM :: SEQ_3 :: patt_gen_seq_3 [15:00] */ 5699 #define PATT_GEN_COM_SEQ_3_PATT_GEN_SEQ_3_MASK 0xffff 5700 #define PATT_GEN_COM_SEQ_3_PATT_GEN_SEQ_3_ALIGN 0 5701 #define PATT_GEN_COM_SEQ_3_PATT_GEN_SEQ_3_BITS 16 5702 #define PATT_GEN_COM_SEQ_3_PATT_GEN_SEQ_3_SHIFT 0 5703 5704 5705 /**************************************************************************** 5706 * PATT_GEN_COM :: SEQ_4 5707 */ 5708 /* PATT_GEN_COM :: SEQ_4 :: patt_gen_seq_4 [15:00] */ 5709 #define PATT_GEN_COM_SEQ_4_PATT_GEN_SEQ_4_MASK 0xffff 5710 #define PATT_GEN_COM_SEQ_4_PATT_GEN_SEQ_4_ALIGN 0 5711 #define PATT_GEN_COM_SEQ_4_PATT_GEN_SEQ_4_BITS 16 5712 #define PATT_GEN_COM_SEQ_4_PATT_GEN_SEQ_4_SHIFT 0 5713 5714 5715 /**************************************************************************** 5716 * PATT_GEN_COM :: SEQ_5 5717 */ 5718 /* PATT_GEN_COM :: SEQ_5 :: patt_gen_seq_5 [15:00] */ 5719 #define PATT_GEN_COM_SEQ_5_PATT_GEN_SEQ_5_MASK 0xffff 5720 #define PATT_GEN_COM_SEQ_5_PATT_GEN_SEQ_5_ALIGN 0 5721 #define PATT_GEN_COM_SEQ_5_PATT_GEN_SEQ_5_BITS 16 5722 #define PATT_GEN_COM_SEQ_5_PATT_GEN_SEQ_5_SHIFT 0 5723 5724 5725 /**************************************************************************** 5726 * PATT_GEN_COM :: SEQ_6 5727 */ 5728 /* PATT_GEN_COM :: SEQ_6 :: patt_gen_seq_6 [15:00] */ 5729 #define PATT_GEN_COM_SEQ_6_PATT_GEN_SEQ_6_MASK 0xffff 5730 #define PATT_GEN_COM_SEQ_6_PATT_GEN_SEQ_6_ALIGN 0 5731 #define PATT_GEN_COM_SEQ_6_PATT_GEN_SEQ_6_BITS 16 5732 #define PATT_GEN_COM_SEQ_6_PATT_GEN_SEQ_6_SHIFT 0 5733 5734 5735 /**************************************************************************** 5736 * PATT_GEN_COM :: SEQ_7 5737 */ 5738 /* PATT_GEN_COM :: SEQ_7 :: patt_gen_seq_7 [15:00] */ 5739 #define PATT_GEN_COM_SEQ_7_PATT_GEN_SEQ_7_MASK 0xffff 5740 #define PATT_GEN_COM_SEQ_7_PATT_GEN_SEQ_7_ALIGN 0 5741 #define PATT_GEN_COM_SEQ_7_PATT_GEN_SEQ_7_BITS 16 5742 #define PATT_GEN_COM_SEQ_7_PATT_GEN_SEQ_7_SHIFT 0 5743 5744 5745 /**************************************************************************** 5746 * PATT_GEN_COM :: SEQ_8 5747 */ 5748 /* PATT_GEN_COM :: SEQ_8 :: patt_gen_seq_8 [15:00] */ 5749 #define PATT_GEN_COM_SEQ_8_PATT_GEN_SEQ_8_MASK 0xffff 5750 #define PATT_GEN_COM_SEQ_8_PATT_GEN_SEQ_8_ALIGN 0 5751 #define PATT_GEN_COM_SEQ_8_PATT_GEN_SEQ_8_BITS 16 5752 #define PATT_GEN_COM_SEQ_8_PATT_GEN_SEQ_8_SHIFT 0 5753 5754 5755 /**************************************************************************** 5756 * PATT_GEN_COM :: SEQ_9 5757 */ 5758 /* PATT_GEN_COM :: SEQ_9 :: patt_gen_seq_9 [15:00] */ 5759 #define PATT_GEN_COM_SEQ_9_PATT_GEN_SEQ_9_MASK 0xffff 5760 #define PATT_GEN_COM_SEQ_9_PATT_GEN_SEQ_9_ALIGN 0 5761 #define PATT_GEN_COM_SEQ_9_PATT_GEN_SEQ_9_BITS 16 5762 #define PATT_GEN_COM_SEQ_9_PATT_GEN_SEQ_9_SHIFT 0 5763 5764 5765 /**************************************************************************** 5766 * PATT_GEN_COM :: SEQ_10 5767 */ 5768 /* PATT_GEN_COM :: SEQ_10 :: patt_gen_seq_10 [15:00] */ 5769 #define PATT_GEN_COM_SEQ_10_PATT_GEN_SEQ_10_MASK 0xffff 5770 #define PATT_GEN_COM_SEQ_10_PATT_GEN_SEQ_10_ALIGN 0 5771 #define PATT_GEN_COM_SEQ_10_PATT_GEN_SEQ_10_BITS 16 5772 #define PATT_GEN_COM_SEQ_10_PATT_GEN_SEQ_10_SHIFT 0 5773 5774 5775 /**************************************************************************** 5776 * PATT_GEN_COM :: SEQ_11 5777 */ 5778 /* PATT_GEN_COM :: SEQ_11 :: patt_gen_seq_11 [15:00] */ 5779 #define PATT_GEN_COM_SEQ_11_PATT_GEN_SEQ_11_MASK 0xffff 5780 #define PATT_GEN_COM_SEQ_11_PATT_GEN_SEQ_11_ALIGN 0 5781 #define PATT_GEN_COM_SEQ_11_PATT_GEN_SEQ_11_BITS 16 5782 #define PATT_GEN_COM_SEQ_11_PATT_GEN_SEQ_11_SHIFT 0 5783 5784 5785 /**************************************************************************** 5786 * PATT_GEN_COM :: SEQ_12 5787 */ 5788 /* PATT_GEN_COM :: SEQ_12 :: patt_gen_seq_12 [15:00] */ 5789 #define PATT_GEN_COM_SEQ_12_PATT_GEN_SEQ_12_MASK 0xffff 5790 #define PATT_GEN_COM_SEQ_12_PATT_GEN_SEQ_12_ALIGN 0 5791 #define PATT_GEN_COM_SEQ_12_PATT_GEN_SEQ_12_BITS 16 5792 #define PATT_GEN_COM_SEQ_12_PATT_GEN_SEQ_12_SHIFT 0 5793 5794 5795 /**************************************************************************** 5796 * PATT_GEN_COM :: SEQ_13 5797 */ 5798 /* PATT_GEN_COM :: SEQ_13 :: patt_gen_seq_13 [15:00] */ 5799 #define PATT_GEN_COM_SEQ_13_PATT_GEN_SEQ_13_MASK 0xffff 5800 #define PATT_GEN_COM_SEQ_13_PATT_GEN_SEQ_13_ALIGN 0 5801 #define PATT_GEN_COM_SEQ_13_PATT_GEN_SEQ_13_BITS 16 5802 #define PATT_GEN_COM_SEQ_13_PATT_GEN_SEQ_13_SHIFT 0 5803 5804 5805 /**************************************************************************** 5806 * PATT_GEN_COM :: SEQ_14 5807 */ 5808 /* PATT_GEN_COM :: SEQ_14 :: patt_gen_seq_14 [15:00] */ 5809 #define PATT_GEN_COM_SEQ_14_PATT_GEN_SEQ_14_MASK 0xffff 5810 #define PATT_GEN_COM_SEQ_14_PATT_GEN_SEQ_14_ALIGN 0 5811 #define PATT_GEN_COM_SEQ_14_PATT_GEN_SEQ_14_BITS 16 5812 #define PATT_GEN_COM_SEQ_14_PATT_GEN_SEQ_14_SHIFT 0 5813 5814 5815 /**************************************************************************** 5816 * eagle_tsc_tx_fed_blk_TX_FED 5817 */ 5818 /**************************************************************************** 5819 * TX_FED :: TXFIR_CONTROL1 5820 */ 5821 /* TX_FED :: TXFIR_CONTROL1 :: reserved0 [15:11] */ 5822 #define TX_FED_TXFIR_CONTROL1_RESERVED0_MASK 0xf800 5823 #define TX_FED_TXFIR_CONTROL1_RESERVED0_ALIGN 0 5824 #define TX_FED_TXFIR_CONTROL1_RESERVED0_BITS 5 5825 #define TX_FED_TXFIR_CONTROL1_RESERVED0_SHIFT 11 5826 5827 /* TX_FED :: TXFIR_CONTROL1 :: txfir_post_override [10:05] */ 5828 #define TX_FED_TXFIR_CONTROL1_TXFIR_POST_OVERRIDE_MASK 0x07e0 5829 #define TX_FED_TXFIR_CONTROL1_TXFIR_POST_OVERRIDE_ALIGN 0 5830 #define TX_FED_TXFIR_CONTROL1_TXFIR_POST_OVERRIDE_BITS 6 5831 #define TX_FED_TXFIR_CONTROL1_TXFIR_POST_OVERRIDE_SHIFT 5 5832 5833 /* TX_FED :: TXFIR_CONTROL1 :: txfir_pre_override [04:00] */ 5834 #define TX_FED_TXFIR_CONTROL1_TXFIR_PRE_OVERRIDE_MASK 0x001f 5835 #define TX_FED_TXFIR_CONTROL1_TXFIR_PRE_OVERRIDE_ALIGN 0 5836 #define TX_FED_TXFIR_CONTROL1_TXFIR_PRE_OVERRIDE_BITS 5 5837 #define TX_FED_TXFIR_CONTROL1_TXFIR_PRE_OVERRIDE_SHIFT 0 5838 5839 5840 /**************************************************************************** 5841 * TX_FED :: TXFIR_CONTROL2 5842 */ 5843 /* TX_FED :: TXFIR_CONTROL2 :: txfir_override_en [15:15] */ 5844 #define TX_FED_TXFIR_CONTROL2_TXFIR_OVERRIDE_EN_MASK 0x8000 5845 #define TX_FED_TXFIR_CONTROL2_TXFIR_OVERRIDE_EN_ALIGN 0 5846 #define TX_FED_TXFIR_CONTROL2_TXFIR_OVERRIDE_EN_BITS 1 5847 #define TX_FED_TXFIR_CONTROL2_TXFIR_OVERRIDE_EN_SHIFT 15 5848 5849 /* TX_FED :: TXFIR_CONTROL2 :: reserved0 [14:12] */ 5850 #define TX_FED_TXFIR_CONTROL2_RESERVED0_MASK 0x7000 5851 #define TX_FED_TXFIR_CONTROL2_RESERVED0_ALIGN 0 5852 #define TX_FED_TXFIR_CONTROL2_RESERVED0_BITS 3 5853 #define TX_FED_TXFIR_CONTROL2_RESERVED0_SHIFT 12 5854 5855 /* TX_FED :: TXFIR_CONTROL2 :: txfir_post2 [11:07] */ 5856 #define TX_FED_TXFIR_CONTROL2_TXFIR_POST2_MASK 0x0f80 5857 #define TX_FED_TXFIR_CONTROL2_TXFIR_POST2_ALIGN 0 5858 #define TX_FED_TXFIR_CONTROL2_TXFIR_POST2_BITS 5 5859 #define TX_FED_TXFIR_CONTROL2_TXFIR_POST2_SHIFT 7 5860 5861 /* TX_FED :: TXFIR_CONTROL2 :: txfir_main_override [06:00] */ 5862 #define TX_FED_TXFIR_CONTROL2_TXFIR_MAIN_OVERRIDE_MASK 0x007f 5863 #define TX_FED_TXFIR_CONTROL2_TXFIR_MAIN_OVERRIDE_ALIGN 0 5864 #define TX_FED_TXFIR_CONTROL2_TXFIR_MAIN_OVERRIDE_BITS 7 5865 #define TX_FED_TXFIR_CONTROL2_TXFIR_MAIN_OVERRIDE_SHIFT 0 5866 5867 5868 /**************************************************************************** 5869 * TX_FED :: TXFIR_CONTROL3 5870 */ 5871 /* TX_FED :: TXFIR_CONTROL3 :: txfir_post2_offset [15:12] */ 5872 #define TX_FED_TXFIR_CONTROL3_TXFIR_POST2_OFFSET_MASK 0xf000 5873 #define TX_FED_TXFIR_CONTROL3_TXFIR_POST2_OFFSET_ALIGN 0 5874 #define TX_FED_TXFIR_CONTROL3_TXFIR_POST2_OFFSET_BITS 4 5875 #define TX_FED_TXFIR_CONTROL3_TXFIR_POST2_OFFSET_SHIFT 12 5876 5877 /* TX_FED :: TXFIR_CONTROL3 :: txfir_post_offset [11:08] */ 5878 #define TX_FED_TXFIR_CONTROL3_TXFIR_POST_OFFSET_MASK 0x0f00 5879 #define TX_FED_TXFIR_CONTROL3_TXFIR_POST_OFFSET_ALIGN 0 5880 #define TX_FED_TXFIR_CONTROL3_TXFIR_POST_OFFSET_BITS 4 5881 #define TX_FED_TXFIR_CONTROL3_TXFIR_POST_OFFSET_SHIFT 8 5882 5883 /* TX_FED :: TXFIR_CONTROL3 :: txfir_main_offset [07:04] */ 5884 #define TX_FED_TXFIR_CONTROL3_TXFIR_MAIN_OFFSET_MASK 0x00f0 5885 #define TX_FED_TXFIR_CONTROL3_TXFIR_MAIN_OFFSET_ALIGN 0 5886 #define TX_FED_TXFIR_CONTROL3_TXFIR_MAIN_OFFSET_BITS 4 5887 #define TX_FED_TXFIR_CONTROL3_TXFIR_MAIN_OFFSET_SHIFT 4 5888 5889 /* TX_FED :: TXFIR_CONTROL3 :: txfir_pre_offset [03:00] */ 5890 #define TX_FED_TXFIR_CONTROL3_TXFIR_PRE_OFFSET_MASK 0x000f 5891 #define TX_FED_TXFIR_CONTROL3_TXFIR_PRE_OFFSET_ALIGN 0 5892 #define TX_FED_TXFIR_CONTROL3_TXFIR_PRE_OFFSET_BITS 4 5893 #define TX_FED_TXFIR_CONTROL3_TXFIR_PRE_OFFSET_SHIFT 0 5894 5895 5896 /**************************************************************************** 5897 * TX_FED :: TXFIR_STATUS1 5898 */ 5899 /* TX_FED :: TXFIR_STATUS1 :: reserved0 [15:11] */ 5900 #define TX_FED_TXFIR_STATUS1_RESERVED0_MASK 0xf800 5901 #define TX_FED_TXFIR_STATUS1_RESERVED0_ALIGN 0 5902 #define TX_FED_TXFIR_STATUS1_RESERVED0_BITS 5 5903 #define TX_FED_TXFIR_STATUS1_RESERVED0_SHIFT 11 5904 5905 /* TX_FED :: TXFIR_STATUS1 :: txfir_post_after_ovr [10:05] */ 5906 #define TX_FED_TXFIR_STATUS1_TXFIR_POST_AFTER_OVR_MASK 0x07e0 5907 #define TX_FED_TXFIR_STATUS1_TXFIR_POST_AFTER_OVR_ALIGN 0 5908 #define TX_FED_TXFIR_STATUS1_TXFIR_POST_AFTER_OVR_BITS 6 5909 #define TX_FED_TXFIR_STATUS1_TXFIR_POST_AFTER_OVR_SHIFT 5 5910 5911 /* TX_FED :: TXFIR_STATUS1 :: txfir_pre_after_ovr [04:00] */ 5912 #define TX_FED_TXFIR_STATUS1_TXFIR_PRE_AFTER_OVR_MASK 0x001f 5913 #define TX_FED_TXFIR_STATUS1_TXFIR_PRE_AFTER_OVR_ALIGN 0 5914 #define TX_FED_TXFIR_STATUS1_TXFIR_PRE_AFTER_OVR_BITS 5 5915 #define TX_FED_TXFIR_STATUS1_TXFIR_PRE_AFTER_OVR_SHIFT 0 5916 5917 5918 /**************************************************************************** 5919 * TX_FED :: TXFIR_STATUS2 5920 */ 5921 /* TX_FED :: TXFIR_STATUS2 :: reserved0 [15:07] */ 5922 #define TX_FED_TXFIR_STATUS2_RESERVED0_MASK 0xff80 5923 #define TX_FED_TXFIR_STATUS2_RESERVED0_ALIGN 0 5924 #define TX_FED_TXFIR_STATUS2_RESERVED0_BITS 9 5925 #define TX_FED_TXFIR_STATUS2_RESERVED0_SHIFT 7 5926 5927 /* TX_FED :: TXFIR_STATUS2 :: txfir_main_after_ovr [06:00] */ 5928 #define TX_FED_TXFIR_STATUS2_TXFIR_MAIN_AFTER_OVR_MASK 0x007f 5929 #define TX_FED_TXFIR_STATUS2_TXFIR_MAIN_AFTER_OVR_ALIGN 0 5930 #define TX_FED_TXFIR_STATUS2_TXFIR_MAIN_AFTER_OVR_BITS 7 5931 #define TX_FED_TXFIR_STATUS2_TXFIR_MAIN_AFTER_OVR_SHIFT 0 5932 5933 5934 /**************************************************************************** 5935 * TX_FED :: TXFIR_STATUS3 5936 */ 5937 /* TX_FED :: TXFIR_STATUS3 :: reserved0 [15:11] */ 5938 #define TX_FED_TXFIR_STATUS3_RESERVED0_MASK 0xf800 5939 #define TX_FED_TXFIR_STATUS3_RESERVED0_ALIGN 0 5940 #define TX_FED_TXFIR_STATUS3_RESERVED0_BITS 5 5941 #define TX_FED_TXFIR_STATUS3_RESERVED0_SHIFT 11 5942 5943 /* TX_FED :: TXFIR_STATUS3 :: txfir_post_adjusted [10:05] */ 5944 #define TX_FED_TXFIR_STATUS3_TXFIR_POST_ADJUSTED_MASK 0x07e0 5945 #define TX_FED_TXFIR_STATUS3_TXFIR_POST_ADJUSTED_ALIGN 0 5946 #define TX_FED_TXFIR_STATUS3_TXFIR_POST_ADJUSTED_BITS 6 5947 #define TX_FED_TXFIR_STATUS3_TXFIR_POST_ADJUSTED_SHIFT 5 5948 5949 /* TX_FED :: TXFIR_STATUS3 :: txfir_pre_adjusted [04:00] */ 5950 #define TX_FED_TXFIR_STATUS3_TXFIR_PRE_ADJUSTED_MASK 0x001f 5951 #define TX_FED_TXFIR_STATUS3_TXFIR_PRE_ADJUSTED_ALIGN 0 5952 #define TX_FED_TXFIR_STATUS3_TXFIR_PRE_ADJUSTED_BITS 5 5953 #define TX_FED_TXFIR_STATUS3_TXFIR_PRE_ADJUSTED_SHIFT 0 5954 5955 5956 /**************************************************************************** 5957 * TX_FED :: TXFIR_STATUS4 5958 */ 5959 /* TX_FED :: TXFIR_STATUS4 :: txfir_post3_adjusted [15:12] */ 5960 #define TX_FED_TXFIR_STATUS4_TXFIR_POST3_ADJUSTED_MASK 0xf000 5961 #define TX_FED_TXFIR_STATUS4_TXFIR_POST3_ADJUSTED_ALIGN 0 5962 #define TX_FED_TXFIR_STATUS4_TXFIR_POST3_ADJUSTED_BITS 4 5963 #define TX_FED_TXFIR_STATUS4_TXFIR_POST3_ADJUSTED_SHIFT 12 5964 5965 /* TX_FED :: TXFIR_STATUS4 :: txfir_post2_adjusted [11:07] */ 5966 #define TX_FED_TXFIR_STATUS4_TXFIR_POST2_ADJUSTED_MASK 0x0f80 5967 #define TX_FED_TXFIR_STATUS4_TXFIR_POST2_ADJUSTED_ALIGN 0 5968 #define TX_FED_TXFIR_STATUS4_TXFIR_POST2_ADJUSTED_BITS 5 5969 #define TX_FED_TXFIR_STATUS4_TXFIR_POST2_ADJUSTED_SHIFT 7 5970 5971 /* TX_FED :: TXFIR_STATUS4 :: txfir_main_adjusted [06:00] */ 5972 #define TX_FED_TXFIR_STATUS4_TXFIR_MAIN_ADJUSTED_MASK 0x007f 5973 #define TX_FED_TXFIR_STATUS4_TXFIR_MAIN_ADJUSTED_ALIGN 0 5974 #define TX_FED_TXFIR_STATUS4_TXFIR_MAIN_ADJUSTED_BITS 7 5975 #define TX_FED_TXFIR_STATUS4_TXFIR_MAIN_ADJUSTED_SHIFT 0 5976 5977 5978 /**************************************************************************** 5979 * TX_FED :: MICRO_CONTROL 5980 */ 5981 /* TX_FED :: MICRO_CONTROL :: reserved0 [15:01] */ 5982 #define TX_FED_MICRO_CONTROL_RESERVED0_MASK 0xfffe 5983 #define TX_FED_MICRO_CONTROL_RESERVED0_ALIGN 0 5984 #define TX_FED_MICRO_CONTROL_RESERVED0_BITS 15 5985 #define TX_FED_MICRO_CONTROL_RESERVED0_SHIFT 1 5986 5987 /* TX_FED :: MICRO_CONTROL :: micro_tx_disable [00:00] */ 5988 #define TX_FED_MICRO_CONTROL_MICRO_TX_DISABLE_MASK 0x0001 5989 #define TX_FED_MICRO_CONTROL_MICRO_TX_DISABLE_ALIGN 0 5990 #define TX_FED_MICRO_CONTROL_MICRO_TX_DISABLE_BITS 1 5991 #define TX_FED_MICRO_CONTROL_MICRO_TX_DISABLE_SHIFT 0 5992 5993 5994 /**************************************************************************** 5995 * TX_FED :: MISC_CONTROL1 5996 */ 5997 /* TX_FED :: MISC_CONTROL1 :: reserved0 [15:13] */ 5998 #define TX_FED_MISC_CONTROL1_RESERVED0_MASK 0xe000 5999 #define TX_FED_MISC_CONTROL1_RESERVED0_ALIGN 0 6000 #define TX_FED_MISC_CONTROL1_RESERVED0_BITS 3 6001 #define TX_FED_MISC_CONTROL1_RESERVED0_SHIFT 13 6002 6003 /* TX_FED :: MISC_CONTROL1 :: dp_reset_tx_disable_dis [12:12] */ 6004 #define TX_FED_MISC_CONTROL1_DP_RESET_TX_DISABLE_DIS_MASK 0x1000 6005 #define TX_FED_MISC_CONTROL1_DP_RESET_TX_DISABLE_DIS_ALIGN 0 6006 #define TX_FED_MISC_CONTROL1_DP_RESET_TX_DISABLE_DIS_BITS 1 6007 #define TX_FED_MISC_CONTROL1_DP_RESET_TX_DISABLE_DIS_SHIFT 12 6008 6009 /* TX_FED :: MISC_CONTROL1 :: tx_disable_output_sel [11:10] */ 6010 #define TX_FED_MISC_CONTROL1_TX_DISABLE_OUTPUT_SEL_MASK 0x0c00 6011 #define TX_FED_MISC_CONTROL1_TX_DISABLE_OUTPUT_SEL_ALIGN 0 6012 #define TX_FED_MISC_CONTROL1_TX_DISABLE_OUTPUT_SEL_BITS 2 6013 #define TX_FED_MISC_CONTROL1_TX_DISABLE_OUTPUT_SEL_SHIFT 10 6014 6015 /* TX_FED :: MISC_CONTROL1 :: tx_eee_alert_en [09:09] */ 6016 #define TX_FED_MISC_CONTROL1_TX_EEE_ALERT_EN_MASK 0x0200 6017 #define TX_FED_MISC_CONTROL1_TX_EEE_ALERT_EN_ALIGN 0 6018 #define TX_FED_MISC_CONTROL1_TX_EEE_ALERT_EN_BITS 1 6019 #define TX_FED_MISC_CONTROL1_TX_EEE_ALERT_EN_SHIFT 9 6020 6021 /* TX_FED :: MISC_CONTROL1 :: tx_eee_quiet_en [08:08] */ 6022 #define TX_FED_MISC_CONTROL1_TX_EEE_QUIET_EN_MASK 0x0100 6023 #define TX_FED_MISC_CONTROL1_TX_EEE_QUIET_EN_ALIGN 0 6024 #define TX_FED_MISC_CONTROL1_TX_EEE_QUIET_EN_BITS 1 6025 #define TX_FED_MISC_CONTROL1_TX_EEE_QUIET_EN_SHIFT 8 6026 6027 /* TX_FED :: MISC_CONTROL1 :: tx_disable_timer_ctrl [07:02] */ 6028 #define TX_FED_MISC_CONTROL1_TX_DISABLE_TIMER_CTRL_MASK 0x00fc 6029 #define TX_FED_MISC_CONTROL1_TX_DISABLE_TIMER_CTRL_ALIGN 0 6030 #define TX_FED_MISC_CONTROL1_TX_DISABLE_TIMER_CTRL_BITS 6 6031 #define TX_FED_MISC_CONTROL1_TX_DISABLE_TIMER_CTRL_SHIFT 2 6032 6033 /* TX_FED :: MISC_CONTROL1 :: pmd_tx_disable_pin_dis [01:01] */ 6034 #define TX_FED_MISC_CONTROL1_PMD_TX_DISABLE_PIN_DIS_MASK 0x0002 6035 #define TX_FED_MISC_CONTROL1_PMD_TX_DISABLE_PIN_DIS_ALIGN 0 6036 #define TX_FED_MISC_CONTROL1_PMD_TX_DISABLE_PIN_DIS_BITS 1 6037 #define TX_FED_MISC_CONTROL1_PMD_TX_DISABLE_PIN_DIS_SHIFT 1 6038 6039 /* TX_FED :: MISC_CONTROL1 :: sdk_tx_disable [00:00] */ 6040 #define TX_FED_MISC_CONTROL1_SDK_TX_DISABLE_MASK 0x0001 6041 #define TX_FED_MISC_CONTROL1_SDK_TX_DISABLE_ALIGN 0 6042 #define TX_FED_MISC_CONTROL1_SDK_TX_DISABLE_BITS 1 6043 #define TX_FED_MISC_CONTROL1_SDK_TX_DISABLE_SHIFT 0 6044 6045 6046 /**************************************************************************** 6047 * TX_FED :: TXFIR_CONTROL4 6048 */ 6049 /* TX_FED :: TXFIR_CONTROL4 :: reserved0 [15:12] */ 6050 #define TX_FED_TXFIR_CONTROL4_RESERVED0_MASK 0xf000 6051 #define TX_FED_TXFIR_CONTROL4_RESERVED0_ALIGN 0 6052 #define TX_FED_TXFIR_CONTROL4_RESERVED0_BITS 4 6053 #define TX_FED_TXFIR_CONTROL4_RESERVED0_SHIFT 12 6054 6055 /* TX_FED :: TXFIR_CONTROL4 :: txfir_post3_offset [11:08] */ 6056 #define TX_FED_TXFIR_CONTROL4_TXFIR_POST3_OFFSET_MASK 0x0f00 6057 #define TX_FED_TXFIR_CONTROL4_TXFIR_POST3_OFFSET_ALIGN 0 6058 #define TX_FED_TXFIR_CONTROL4_TXFIR_POST3_OFFSET_BITS 4 6059 #define TX_FED_TXFIR_CONTROL4_TXFIR_POST3_OFFSET_SHIFT 8 6060 6061 /* TX_FED :: TXFIR_CONTROL4 :: reserved1 [07:04] */ 6062 #define TX_FED_TXFIR_CONTROL4_RESERVED1_MASK 0x00f0 6063 #define TX_FED_TXFIR_CONTROL4_RESERVED1_ALIGN 0 6064 #define TX_FED_TXFIR_CONTROL4_RESERVED1_BITS 4 6065 #define TX_FED_TXFIR_CONTROL4_RESERVED1_SHIFT 4 6066 6067 /* TX_FED :: TXFIR_CONTROL4 :: txfir_post3 [03:00] */ 6068 #define TX_FED_TXFIR_CONTROL4_TXFIR_POST3_MASK 0x000f 6069 #define TX_FED_TXFIR_CONTROL4_TXFIR_POST3_ALIGN 0 6070 #define TX_FED_TXFIR_CONTROL4_TXFIR_POST3_BITS 4 6071 #define TX_FED_TXFIR_CONTROL4_TXFIR_POST3_SHIFT 0 6072 6073 6074 /**************************************************************************** 6075 * eagle_tsc_pll_cal_com_blk_PLL_CAL_COM 6076 */ 6077 /**************************************************************************** 6078 * PLL_CAL_COM :: CTL_0 6079 */ 6080 /* PLL_CAL_COM :: CTL_0 :: vco_start_time [15:08] */ 6081 #define PLL_CAL_COM_CTL_0_VCO_START_TIME_MASK 0xff00 6082 #define PLL_CAL_COM_CTL_0_VCO_START_TIME_ALIGN 0 6083 #define PLL_CAL_COM_CTL_0_VCO_START_TIME_BITS 8 6084 #define PLL_CAL_COM_CTL_0_VCO_START_TIME_SHIFT 8 6085 6086 /* PLL_CAL_COM :: CTL_0 :: vco_step_time [07:00] */ 6087 #define PLL_CAL_COM_CTL_0_VCO_STEP_TIME_MASK 0x00ff 6088 #define PLL_CAL_COM_CTL_0_VCO_STEP_TIME_ALIGN 0 6089 #define PLL_CAL_COM_CTL_0_VCO_STEP_TIME_BITS 8 6090 #define PLL_CAL_COM_CTL_0_VCO_STEP_TIME_SHIFT 0 6091 6092 6093 /**************************************************************************** 6094 * PLL_CAL_COM :: CTL_1 6095 */ 6096 /* PLL_CAL_COM :: CTL_1 :: pre_freq_det_time [15:08] */ 6097 #define PLL_CAL_COM_CTL_1_PRE_FREQ_DET_TIME_MASK 0xff00 6098 #define PLL_CAL_COM_CTL_1_PRE_FREQ_DET_TIME_ALIGN 0 6099 #define PLL_CAL_COM_CTL_1_PRE_FREQ_DET_TIME_BITS 8 6100 #define PLL_CAL_COM_CTL_1_PRE_FREQ_DET_TIME_SHIFT 8 6101 6102 /* PLL_CAL_COM :: CTL_1 :: retry_time [07:00] */ 6103 #define PLL_CAL_COM_CTL_1_RETRY_TIME_MASK 0x00ff 6104 #define PLL_CAL_COM_CTL_1_RETRY_TIME_ALIGN 0 6105 #define PLL_CAL_COM_CTL_1_RETRY_TIME_BITS 8 6106 #define PLL_CAL_COM_CTL_1_RETRY_TIME_SHIFT 0 6107 6108 6109 /**************************************************************************** 6110 * PLL_CAL_COM :: CTL_2 6111 */ 6112 /* PLL_CAL_COM :: CTL_2 :: res_cal_cntr [15:08] */ 6113 #define PLL_CAL_COM_CTL_2_RES_CAL_CNTR_MASK 0xff00 6114 #define PLL_CAL_COM_CTL_2_RES_CAL_CNTR_ALIGN 0 6115 #define PLL_CAL_COM_CTL_2_RES_CAL_CNTR_BITS 8 6116 #define PLL_CAL_COM_CTL_2_RES_CAL_CNTR_SHIFT 8 6117 6118 /* PLL_CAL_COM :: CTL_2 :: win_cal_cntr [07:00] */ 6119 #define PLL_CAL_COM_CTL_2_WIN_CAL_CNTR_MASK 0x00ff 6120 #define PLL_CAL_COM_CTL_2_WIN_CAL_CNTR_ALIGN 0 6121 #define PLL_CAL_COM_CTL_2_WIN_CAL_CNTR_BITS 8 6122 #define PLL_CAL_COM_CTL_2_WIN_CAL_CNTR_SHIFT 0 6123 6124 6125 /**************************************************************************** 6126 * PLL_CAL_COM :: CTL_3 6127 */ 6128 /* PLL_CAL_COM :: CTL_3 :: cap_select_m [15:08] */ 6129 #define PLL_CAL_COM_CTL_3_CAP_SELECT_M_MASK 0xff00 6130 #define PLL_CAL_COM_CTL_3_CAP_SELECT_M_ALIGN 0 6131 #define PLL_CAL_COM_CTL_3_CAP_SELECT_M_BITS 8 6132 #define PLL_CAL_COM_CTL_3_CAP_SELECT_M_SHIFT 8 6133 6134 /* PLL_CAL_COM :: CTL_3 :: cap_select_m_en [07:07] */ 6135 #define PLL_CAL_COM_CTL_3_CAP_SELECT_M_EN_MASK 0x0080 6136 #define PLL_CAL_COM_CTL_3_CAP_SELECT_M_EN_ALIGN 0 6137 #define PLL_CAL_COM_CTL_3_CAP_SELECT_M_EN_BITS 1 6138 #define PLL_CAL_COM_CTL_3_CAP_SELECT_M_EN_SHIFT 7 6139 6140 /* PLL_CAL_COM :: CTL_3 :: cap_force_slowdown_en [06:06] */ 6141 #define PLL_CAL_COM_CTL_3_CAP_FORCE_SLOWDOWN_EN_MASK 0x0040 6142 #define PLL_CAL_COM_CTL_3_CAP_FORCE_SLOWDOWN_EN_ALIGN 0 6143 #define PLL_CAL_COM_CTL_3_CAP_FORCE_SLOWDOWN_EN_BITS 1 6144 #define PLL_CAL_COM_CTL_3_CAP_FORCE_SLOWDOWN_EN_SHIFT 6 6145 6146 /* PLL_CAL_COM :: CTL_3 :: cap_force_slowdown [05:05] */ 6147 #define PLL_CAL_COM_CTL_3_CAP_FORCE_SLOWDOWN_MASK 0x0020 6148 #define PLL_CAL_COM_CTL_3_CAP_FORCE_SLOWDOWN_ALIGN 0 6149 #define PLL_CAL_COM_CTL_3_CAP_FORCE_SLOWDOWN_BITS 1 6150 #define PLL_CAL_COM_CTL_3_CAP_FORCE_SLOWDOWN_SHIFT 5 6151 6152 /* PLL_CAL_COM :: CTL_3 :: cap_retry_en [04:04] */ 6153 #define PLL_CAL_COM_CTL_3_CAP_RETRY_EN_MASK 0x0010 6154 #define PLL_CAL_COM_CTL_3_CAP_RETRY_EN_ALIGN 0 6155 #define PLL_CAL_COM_CTL_3_CAP_RETRY_EN_BITS 1 6156 #define PLL_CAL_COM_CTL_3_CAP_RETRY_EN_SHIFT 4 6157 6158 /* PLL_CAL_COM :: CTL_3 :: cap_restart [03:03] */ 6159 #define PLL_CAL_COM_CTL_3_CAP_RESTART_MASK 0x0008 6160 #define PLL_CAL_COM_CTL_3_CAP_RESTART_ALIGN 0 6161 #define PLL_CAL_COM_CTL_3_CAP_RESTART_BITS 1 6162 #define PLL_CAL_COM_CTL_3_CAP_RESTART_SHIFT 3 6163 6164 /* PLL_CAL_COM :: CTL_3 :: cap_seq_cya [02:02] */ 6165 #define PLL_CAL_COM_CTL_3_CAP_SEQ_CYA_MASK 0x0004 6166 #define PLL_CAL_COM_CTL_3_CAP_SEQ_CYA_ALIGN 0 6167 #define PLL_CAL_COM_CTL_3_CAP_SEQ_CYA_BITS 1 6168 #define PLL_CAL_COM_CTL_3_CAP_SEQ_CYA_SHIFT 2 6169 6170 /* PLL_CAL_COM :: CTL_3 :: cap_cnt_mask_en [01:01] */ 6171 #define PLL_CAL_COM_CTL_3_CAP_CNT_MASK_EN_MASK 0x0002 6172 #define PLL_CAL_COM_CTL_3_CAP_CNT_MASK_EN_ALIGN 0 6173 #define PLL_CAL_COM_CTL_3_CAP_CNT_MASK_EN_BITS 1 6174 #define PLL_CAL_COM_CTL_3_CAP_CNT_MASK_EN_SHIFT 1 6175 6176 /* PLL_CAL_COM :: CTL_3 :: fast_search_mode [00:00] */ 6177 #define PLL_CAL_COM_CTL_3_FAST_SEARCH_MODE_MASK 0x0001 6178 #define PLL_CAL_COM_CTL_3_FAST_SEARCH_MODE_ALIGN 0 6179 #define PLL_CAL_COM_CTL_3_FAST_SEARCH_MODE_BITS 1 6180 #define PLL_CAL_COM_CTL_3_FAST_SEARCH_MODE_SHIFT 0 6181 6182 6183 /**************************************************************************** 6184 * PLL_CAL_COM :: CTL_4 6185 */ 6186 /* PLL_CAL_COM :: CTL_4 :: pll_seq_start [15:15] */ 6187 #define PLL_CAL_COM_CTL_4_PLL_SEQ_START_MASK 0x8000 6188 #define PLL_CAL_COM_CTL_4_PLL_SEQ_START_ALIGN 0 6189 #define PLL_CAL_COM_CTL_4_PLL_SEQ_START_BITS 1 6190 #define PLL_CAL_COM_CTL_4_PLL_SEQ_START_SHIFT 15 6191 6192 /* PLL_CAL_COM :: CTL_4 :: vco_done_en [14:14] */ 6193 #define PLL_CAL_COM_CTL_4_VCO_DONE_EN_MASK 0x4000 6194 #define PLL_CAL_COM_CTL_4_VCO_DONE_EN_ALIGN 0 6195 #define PLL_CAL_COM_CTL_4_VCO_DONE_EN_BITS 1 6196 #define PLL_CAL_COM_CTL_4_VCO_DONE_EN_SHIFT 14 6197 6198 /* PLL_CAL_COM :: CTL_4 :: freq_det_retry_en [13:13] */ 6199 #define PLL_CAL_COM_CTL_4_FREQ_DET_RETRY_EN_MASK 0x2000 6200 #define PLL_CAL_COM_CTL_4_FREQ_DET_RETRY_EN_ALIGN 0 6201 #define PLL_CAL_COM_CTL_4_FREQ_DET_RETRY_EN_BITS 1 6202 #define PLL_CAL_COM_CTL_4_FREQ_DET_RETRY_EN_SHIFT 13 6203 6204 /* PLL_CAL_COM :: CTL_4 :: freq_det_restart_en [12:12] */ 6205 #define PLL_CAL_COM_CTL_4_FREQ_DET_RESTART_EN_MASK 0x1000 6206 #define PLL_CAL_COM_CTL_4_FREQ_DET_RESTART_EN_ALIGN 0 6207 #define PLL_CAL_COM_CTL_4_FREQ_DET_RESTART_EN_BITS 1 6208 #define PLL_CAL_COM_CTL_4_FREQ_DET_RESTART_EN_SHIFT 12 6209 6210 /* PLL_CAL_COM :: CTL_4 :: freq_monitor_en [11:11] */ 6211 #define PLL_CAL_COM_CTL_4_FREQ_MONITOR_EN_MASK 0x0800 6212 #define PLL_CAL_COM_CTL_4_FREQ_MONITOR_EN_ALIGN 0 6213 #define PLL_CAL_COM_CTL_4_FREQ_MONITOR_EN_BITS 1 6214 #define PLL_CAL_COM_CTL_4_FREQ_MONITOR_EN_SHIFT 11 6215 6216 /* PLL_CAL_COM :: CTL_4 :: slowdn_xor [10:10] */ 6217 #define PLL_CAL_COM_CTL_4_SLOWDN_XOR_MASK 0x0400 6218 #define PLL_CAL_COM_CTL_4_SLOWDN_XOR_ALIGN 0 6219 #define PLL_CAL_COM_CTL_4_SLOWDN_XOR_BITS 1 6220 #define PLL_CAL_COM_CTL_4_SLOWDN_XOR_SHIFT 10 6221 6222 /* PLL_CAL_COM :: CTL_4 :: vco_rst_en [09:09] */ 6223 #define PLL_CAL_COM_CTL_4_VCO_RST_EN_MASK 0x0200 6224 #define PLL_CAL_COM_CTL_4_VCO_RST_EN_ALIGN 0 6225 #define PLL_CAL_COM_CTL_4_VCO_RST_EN_BITS 1 6226 #define PLL_CAL_COM_CTL_4_VCO_RST_EN_SHIFT 9 6227 6228 /* PLL_CAL_COM :: CTL_4 :: pll_force_fdone_en [08:08] */ 6229 #define PLL_CAL_COM_CTL_4_PLL_FORCE_FDONE_EN_MASK 0x0100 6230 #define PLL_CAL_COM_CTL_4_PLL_FORCE_FDONE_EN_ALIGN 0 6231 #define PLL_CAL_COM_CTL_4_PLL_FORCE_FDONE_EN_BITS 1 6232 #define PLL_CAL_COM_CTL_4_PLL_FORCE_FDONE_EN_SHIFT 8 6233 6234 /* PLL_CAL_COM :: CTL_4 :: pll_force_fdone [07:07] */ 6235 #define PLL_CAL_COM_CTL_4_PLL_FORCE_FDONE_MASK 0x0080 6236 #define PLL_CAL_COM_CTL_4_PLL_FORCE_FDONE_ALIGN 0 6237 #define PLL_CAL_COM_CTL_4_PLL_FORCE_FDONE_BITS 1 6238 #define PLL_CAL_COM_CTL_4_PLL_FORCE_FDONE_SHIFT 7 6239 6240 /* PLL_CAL_COM :: CTL_4 :: pll_force_fpass [06:06] */ 6241 #define PLL_CAL_COM_CTL_4_PLL_FORCE_FPASS_MASK 0x0040 6242 #define PLL_CAL_COM_CTL_4_PLL_FORCE_FPASS_ALIGN 0 6243 #define PLL_CAL_COM_CTL_4_PLL_FORCE_FPASS_BITS 1 6244 #define PLL_CAL_COM_CTL_4_PLL_FORCE_FPASS_SHIFT 6 6245 6246 /* PLL_CAL_COM :: CTL_4 :: pll_force_cap_done_en [05:05] */ 6247 #define PLL_CAL_COM_CTL_4_PLL_FORCE_CAP_DONE_EN_MASK 0x0020 6248 #define PLL_CAL_COM_CTL_4_PLL_FORCE_CAP_DONE_EN_ALIGN 0 6249 #define PLL_CAL_COM_CTL_4_PLL_FORCE_CAP_DONE_EN_BITS 1 6250 #define PLL_CAL_COM_CTL_4_PLL_FORCE_CAP_DONE_EN_SHIFT 5 6251 6252 /* PLL_CAL_COM :: CTL_4 :: pll_force_cap_done [04:04] */ 6253 #define PLL_CAL_COM_CTL_4_PLL_FORCE_CAP_DONE_MASK 0x0010 6254 #define PLL_CAL_COM_CTL_4_PLL_FORCE_CAP_DONE_ALIGN 0 6255 #define PLL_CAL_COM_CTL_4_PLL_FORCE_CAP_DONE_BITS 1 6256 #define PLL_CAL_COM_CTL_4_PLL_FORCE_CAP_DONE_SHIFT 4 6257 6258 /* PLL_CAL_COM :: CTL_4 :: pll_force_cap_pass_en [03:03] */ 6259 #define PLL_CAL_COM_CTL_4_PLL_FORCE_CAP_PASS_EN_MASK 0x0008 6260 #define PLL_CAL_COM_CTL_4_PLL_FORCE_CAP_PASS_EN_ALIGN 0 6261 #define PLL_CAL_COM_CTL_4_PLL_FORCE_CAP_PASS_EN_BITS 1 6262 #define PLL_CAL_COM_CTL_4_PLL_FORCE_CAP_PASS_EN_SHIFT 3 6263 6264 /* PLL_CAL_COM :: CTL_4 :: pll_force_cap_pass [02:02] */ 6265 #define PLL_CAL_COM_CTL_4_PLL_FORCE_CAP_PASS_MASK 0x0004 6266 #define PLL_CAL_COM_CTL_4_PLL_FORCE_CAP_PASS_ALIGN 0 6267 #define PLL_CAL_COM_CTL_4_PLL_FORCE_CAP_PASS_BITS 1 6268 #define PLL_CAL_COM_CTL_4_PLL_FORCE_CAP_PASS_SHIFT 2 6269 6270 /* PLL_CAL_COM :: CTL_4 :: pll_lock_frc [01:01] */ 6271 #define PLL_CAL_COM_CTL_4_PLL_LOCK_FRC_MASK 0x0002 6272 #define PLL_CAL_COM_CTL_4_PLL_LOCK_FRC_ALIGN 0 6273 #define PLL_CAL_COM_CTL_4_PLL_LOCK_FRC_BITS 1 6274 #define PLL_CAL_COM_CTL_4_PLL_LOCK_FRC_SHIFT 1 6275 6276 /* PLL_CAL_COM :: CTL_4 :: pll_lock_frc_val [00:00] */ 6277 #define PLL_CAL_COM_CTL_4_PLL_LOCK_FRC_VAL_MASK 0x0001 6278 #define PLL_CAL_COM_CTL_4_PLL_LOCK_FRC_VAL_ALIGN 0 6279 #define PLL_CAL_COM_CTL_4_PLL_LOCK_FRC_VAL_BITS 1 6280 #define PLL_CAL_COM_CTL_4_PLL_LOCK_FRC_VAL_SHIFT 0 6281 6282 6283 /**************************************************************************** 6284 * PLL_CAL_COM :: CTL_5 6285 */ 6286 /* PLL_CAL_COM :: CTL_5 :: reserved0 [15:14] */ 6287 #define PLL_CAL_COM_CTL_5_RESERVED0_MASK 0xc000 6288 #define PLL_CAL_COM_CTL_5_RESERVED0_ALIGN 0 6289 #define PLL_CAL_COM_CTL_5_RESERVED0_BITS 2 6290 #define PLL_CAL_COM_CTL_5_RESERVED0_SHIFT 14 6291 6292 /* PLL_CAL_COM :: CTL_5 :: refclk_divcnt [13:00] */ 6293 #define PLL_CAL_COM_CTL_5_REFCLK_DIVCNT_MASK 0x3fff 6294 #define PLL_CAL_COM_CTL_5_REFCLK_DIVCNT_ALIGN 0 6295 #define PLL_CAL_COM_CTL_5_REFCLK_DIVCNT_BITS 14 6296 #define PLL_CAL_COM_CTL_5_REFCLK_DIVCNT_SHIFT 0 6297 6298 6299 /**************************************************************************** 6300 * PLL_CAL_COM :: CTL_6 6301 */ 6302 /* PLL_CAL_COM :: CTL_6 :: reserved0 [15:03] */ 6303 #define PLL_CAL_COM_CTL_6_RESERVED0_MASK 0xfff8 6304 #define PLL_CAL_COM_CTL_6_RESERVED0_ALIGN 0 6305 #define PLL_CAL_COM_CTL_6_RESERVED0_BITS 13 6306 #define PLL_CAL_COM_CTL_6_RESERVED0_SHIFT 3 6307 6308 /* PLL_CAL_COM :: CTL_6 :: refclk_divcnt_sel [02:00] */ 6309 #define PLL_CAL_COM_CTL_6_REFCLK_DIVCNT_SEL_MASK 0x0007 6310 #define PLL_CAL_COM_CTL_6_REFCLK_DIVCNT_SEL_ALIGN 0 6311 #define PLL_CAL_COM_CTL_6_REFCLK_DIVCNT_SEL_BITS 3 6312 #define PLL_CAL_COM_CTL_6_REFCLK_DIVCNT_SEL_SHIFT 0 6313 6314 6315 /**************************************************************************** 6316 * PLL_CAL_COM :: CTL_7 6317 */ 6318 /* PLL_CAL_COM :: CTL_7 :: reserved0 [15:09] */ 6319 #define PLL_CAL_COM_CTL_7_RESERVED0_MASK 0xfe00 6320 #define PLL_CAL_COM_CTL_7_RESERVED0_ALIGN 0 6321 #define PLL_CAL_COM_CTL_7_RESERVED0_BITS 7 6322 #define PLL_CAL_COM_CTL_7_RESERVED0_SHIFT 9 6323 6324 /* PLL_CAL_COM :: CTL_7 :: rescal_frc [08:08] */ 6325 #define PLL_CAL_COM_CTL_7_RESCAL_FRC_MASK 0x0100 6326 #define PLL_CAL_COM_CTL_7_RESCAL_FRC_ALIGN 0 6327 #define PLL_CAL_COM_CTL_7_RESCAL_FRC_BITS 1 6328 #define PLL_CAL_COM_CTL_7_RESCAL_FRC_SHIFT 8 6329 6330 /* PLL_CAL_COM :: CTL_7 :: rescal_frc_val [07:04] */ 6331 #define PLL_CAL_COM_CTL_7_RESCAL_FRC_VAL_MASK 0x00f0 6332 #define PLL_CAL_COM_CTL_7_RESCAL_FRC_VAL_ALIGN 0 6333 #define PLL_CAL_COM_CTL_7_RESCAL_FRC_VAL_BITS 4 6334 #define PLL_CAL_COM_CTL_7_RESCAL_FRC_VAL_SHIFT 4 6335 6336 /* PLL_CAL_COM :: CTL_7 :: pll_mode [03:00] */ 6337 #define PLL_CAL_COM_CTL_7_PLL_MODE_MASK 0x000f 6338 #define PLL_CAL_COM_CTL_7_PLL_MODE_ALIGN 0 6339 #define PLL_CAL_COM_CTL_7_PLL_MODE_BITS 4 6340 #define PLL_CAL_COM_CTL_7_PLL_MODE_SHIFT 0 6341 6342 6343 /**************************************************************************** 6344 * PLL_CAL_COM :: CTL_STATUS_0 6345 */ 6346 /* PLL_CAL_COM :: CTL_STATUS_0 :: lost_pll_lock_sm [15:15] */ 6347 #define PLL_CAL_COM_CTL_STATUS_0_LOST_PLL_LOCK_SM_MASK 0x8000 6348 #define PLL_CAL_COM_CTL_STATUS_0_LOST_PLL_LOCK_SM_ALIGN 0 6349 #define PLL_CAL_COM_CTL_STATUS_0_LOST_PLL_LOCK_SM_BITS 1 6350 #define PLL_CAL_COM_CTL_STATUS_0_LOST_PLL_LOCK_SM_SHIFT 15 6351 6352 /* PLL_CAL_COM :: CTL_STATUS_0 :: cap_done [14:14] */ 6353 #define PLL_CAL_COM_CTL_STATUS_0_CAP_DONE_MASK 0x4000 6354 #define PLL_CAL_COM_CTL_STATUS_0_CAP_DONE_ALIGN 0 6355 #define PLL_CAL_COM_CTL_STATUS_0_CAP_DONE_BITS 1 6356 #define PLL_CAL_COM_CTL_STATUS_0_CAP_DONE_SHIFT 14 6357 6358 /* PLL_CAL_COM :: CTL_STATUS_0 :: cap_pass [13:13] */ 6359 #define PLL_CAL_COM_CTL_STATUS_0_CAP_PASS_MASK 0x2000 6360 #define PLL_CAL_COM_CTL_STATUS_0_CAP_PASS_ALIGN 0 6361 #define PLL_CAL_COM_CTL_STATUS_0_CAP_PASS_BITS 1 6362 #define PLL_CAL_COM_CTL_STATUS_0_CAP_PASS_SHIFT 13 6363 6364 /* PLL_CAL_COM :: CTL_STATUS_0 :: freq_done_sm [12:12] */ 6365 #define PLL_CAL_COM_CTL_STATUS_0_FREQ_DONE_SM_MASK 0x1000 6366 #define PLL_CAL_COM_CTL_STATUS_0_FREQ_DONE_SM_ALIGN 0 6367 #define PLL_CAL_COM_CTL_STATUS_0_FREQ_DONE_SM_BITS 1 6368 #define PLL_CAL_COM_CTL_STATUS_0_FREQ_DONE_SM_SHIFT 12 6369 6370 /* PLL_CAL_COM :: CTL_STATUS_0 :: freq_pass_sm [11:11] */ 6371 #define PLL_CAL_COM_CTL_STATUS_0_FREQ_PASS_SM_MASK 0x0800 6372 #define PLL_CAL_COM_CTL_STATUS_0_FREQ_PASS_SM_ALIGN 0 6373 #define PLL_CAL_COM_CTL_STATUS_0_FREQ_PASS_SM_BITS 1 6374 #define PLL_CAL_COM_CTL_STATUS_0_FREQ_PASS_SM_SHIFT 11 6375 6376 /* PLL_CAL_COM :: CTL_STATUS_0 :: pll_seq_done [10:10] */ 6377 #define PLL_CAL_COM_CTL_STATUS_0_PLL_SEQ_DONE_MASK 0x0400 6378 #define PLL_CAL_COM_CTL_STATUS_0_PLL_SEQ_DONE_ALIGN 0 6379 #define PLL_CAL_COM_CTL_STATUS_0_PLL_SEQ_DONE_BITS 1 6380 #define PLL_CAL_COM_CTL_STATUS_0_PLL_SEQ_DONE_SHIFT 10 6381 6382 /* PLL_CAL_COM :: CTL_STATUS_0 :: pll_seq_pass [09:09] */ 6383 #define PLL_CAL_COM_CTL_STATUS_0_PLL_SEQ_PASS_MASK 0x0200 6384 #define PLL_CAL_COM_CTL_STATUS_0_PLL_SEQ_PASS_ALIGN 0 6385 #define PLL_CAL_COM_CTL_STATUS_0_PLL_SEQ_PASS_BITS 1 6386 #define PLL_CAL_COM_CTL_STATUS_0_PLL_SEQ_PASS_SHIFT 9 6387 6388 /* PLL_CAL_COM :: CTL_STATUS_0 :: pll_lock [08:08] */ 6389 #define PLL_CAL_COM_CTL_STATUS_0_PLL_LOCK_MASK 0x0100 6390 #define PLL_CAL_COM_CTL_STATUS_0_PLL_LOCK_ALIGN 0 6391 #define PLL_CAL_COM_CTL_STATUS_0_PLL_LOCK_BITS 1 6392 #define PLL_CAL_COM_CTL_STATUS_0_PLL_LOCK_SHIFT 8 6393 6394 /* PLL_CAL_COM :: CTL_STATUS_0 :: reserved0 [07:07] */ 6395 #define PLL_CAL_COM_CTL_STATUS_0_RESERVED0_MASK 0x0080 6396 #define PLL_CAL_COM_CTL_STATUS_0_RESERVED0_ALIGN 0 6397 #define PLL_CAL_COM_CTL_STATUS_0_RESERVED0_BITS 1 6398 #define PLL_CAL_COM_CTL_STATUS_0_RESERVED0_SHIFT 7 6399 6400 /* PLL_CAL_COM :: CTL_STATUS_0 :: cap_done_lh_ll [06:06] */ 6401 #define PLL_CAL_COM_CTL_STATUS_0_CAP_DONE_LH_LL_MASK 0x0040 6402 #define PLL_CAL_COM_CTL_STATUS_0_CAP_DONE_LH_LL_ALIGN 0 6403 #define PLL_CAL_COM_CTL_STATUS_0_CAP_DONE_LH_LL_BITS 1 6404 #define PLL_CAL_COM_CTL_STATUS_0_CAP_DONE_LH_LL_SHIFT 6 6405 6406 /* PLL_CAL_COM :: CTL_STATUS_0 :: cap_pass_lh_ll [05:05] */ 6407 #define PLL_CAL_COM_CTL_STATUS_0_CAP_PASS_LH_LL_MASK 0x0020 6408 #define PLL_CAL_COM_CTL_STATUS_0_CAP_PASS_LH_LL_ALIGN 0 6409 #define PLL_CAL_COM_CTL_STATUS_0_CAP_PASS_LH_LL_BITS 1 6410 #define PLL_CAL_COM_CTL_STATUS_0_CAP_PASS_LH_LL_SHIFT 5 6411 6412 /* PLL_CAL_COM :: CTL_STATUS_0 :: freq_done_sm_lh_ll [04:04] */ 6413 #define PLL_CAL_COM_CTL_STATUS_0_FREQ_DONE_SM_LH_LL_MASK 0x0010 6414 #define PLL_CAL_COM_CTL_STATUS_0_FREQ_DONE_SM_LH_LL_ALIGN 0 6415 #define PLL_CAL_COM_CTL_STATUS_0_FREQ_DONE_SM_LH_LL_BITS 1 6416 #define PLL_CAL_COM_CTL_STATUS_0_FREQ_DONE_SM_LH_LL_SHIFT 4 6417 6418 /* PLL_CAL_COM :: CTL_STATUS_0 :: freq_pass_sm_lh_ll [03:03] */ 6419 #define PLL_CAL_COM_CTL_STATUS_0_FREQ_PASS_SM_LH_LL_MASK 0x0008 6420 #define PLL_CAL_COM_CTL_STATUS_0_FREQ_PASS_SM_LH_LL_ALIGN 0 6421 #define PLL_CAL_COM_CTL_STATUS_0_FREQ_PASS_SM_LH_LL_BITS 1 6422 #define PLL_CAL_COM_CTL_STATUS_0_FREQ_PASS_SM_LH_LL_SHIFT 3 6423 6424 /* PLL_CAL_COM :: CTL_STATUS_0 :: pll_seq_done_lh_ll [02:02] */ 6425 #define PLL_CAL_COM_CTL_STATUS_0_PLL_SEQ_DONE_LH_LL_MASK 0x0004 6426 #define PLL_CAL_COM_CTL_STATUS_0_PLL_SEQ_DONE_LH_LL_ALIGN 0 6427 #define PLL_CAL_COM_CTL_STATUS_0_PLL_SEQ_DONE_LH_LL_BITS 1 6428 #define PLL_CAL_COM_CTL_STATUS_0_PLL_SEQ_DONE_LH_LL_SHIFT 2 6429 6430 /* PLL_CAL_COM :: CTL_STATUS_0 :: pll_seq_pass_lh_ll [01:01] */ 6431 #define PLL_CAL_COM_CTL_STATUS_0_PLL_SEQ_PASS_LH_LL_MASK 0x0002 6432 #define PLL_CAL_COM_CTL_STATUS_0_PLL_SEQ_PASS_LH_LL_ALIGN 0 6433 #define PLL_CAL_COM_CTL_STATUS_0_PLL_SEQ_PASS_LH_LL_BITS 1 6434 #define PLL_CAL_COM_CTL_STATUS_0_PLL_SEQ_PASS_LH_LL_SHIFT 1 6435 6436 /* PLL_CAL_COM :: CTL_STATUS_0 :: pll_lock_lh_ll [00:00] */ 6437 #define PLL_CAL_COM_CTL_STATUS_0_PLL_LOCK_LH_LL_MASK 0x0001 6438 #define PLL_CAL_COM_CTL_STATUS_0_PLL_LOCK_LH_LL_ALIGN 0 6439 #define PLL_CAL_COM_CTL_STATUS_0_PLL_LOCK_LH_LL_BITS 1 6440 #define PLL_CAL_COM_CTL_STATUS_0_PLL_LOCK_LH_LL_SHIFT 0 6441 6442 6443 /**************************************************************************** 6444 * PLL_CAL_COM :: CTL_STATUS_1 6445 */ 6446 /* PLL_CAL_COM :: CTL_STATUS_1 :: reserved0 [15:12] */ 6447 #define PLL_CAL_COM_CTL_STATUS_1_RESERVED0_MASK 0xf000 6448 #define PLL_CAL_COM_CTL_STATUS_1_RESERVED0_ALIGN 0 6449 #define PLL_CAL_COM_CTL_STATUS_1_RESERVED0_BITS 4 6450 #define PLL_CAL_COM_CTL_STATUS_1_RESERVED0_SHIFT 12 6451 6452 /* PLL_CAL_COM :: CTL_STATUS_1 :: rescal_in [11:08] */ 6453 #define PLL_CAL_COM_CTL_STATUS_1_RESCAL_IN_MASK 0x0f00 6454 #define PLL_CAL_COM_CTL_STATUS_1_RESCAL_IN_ALIGN 0 6455 #define PLL_CAL_COM_CTL_STATUS_1_RESCAL_IN_BITS 4 6456 #define PLL_CAL_COM_CTL_STATUS_1_RESCAL_IN_SHIFT 8 6457 6458 /* PLL_CAL_COM :: CTL_STATUS_1 :: cap_select [07:00] */ 6459 #define PLL_CAL_COM_CTL_STATUS_1_CAP_SELECT_MASK 0x00ff 6460 #define PLL_CAL_COM_CTL_STATUS_1_CAP_SELECT_ALIGN 0 6461 #define PLL_CAL_COM_CTL_STATUS_1_CAP_SELECT_BITS 8 6462 #define PLL_CAL_COM_CTL_STATUS_1_CAP_SELECT_SHIFT 0 6463 6464 6465 /**************************************************************************** 6466 * PLL_CAL_COM :: CTL_STATUS_DBG 6467 */ 6468 /* PLL_CAL_COM :: CTL_STATUS_DBG :: dbg_pll_state_one_hot [15:08] */ 6469 #define PLL_CAL_COM_CTL_STATUS_DBG_DBG_PLL_STATE_ONE_HOT_MASK 0xff00 6470 #define PLL_CAL_COM_CTL_STATUS_DBG_DBG_PLL_STATE_ONE_HOT_ALIGN 0 6471 #define PLL_CAL_COM_CTL_STATUS_DBG_DBG_PLL_STATE_ONE_HOT_BITS 8 6472 #define PLL_CAL_COM_CTL_STATUS_DBG_DBG_PLL_STATE_ONE_HOT_SHIFT 8 6473 6474 /* PLL_CAL_COM :: CTL_STATUS_DBG :: dbg_cap_state_one_hot [07:03] */ 6475 #define PLL_CAL_COM_CTL_STATUS_DBG_DBG_CAP_STATE_ONE_HOT_MASK 0x00f8 6476 #define PLL_CAL_COM_CTL_STATUS_DBG_DBG_CAP_STATE_ONE_HOT_ALIGN 0 6477 #define PLL_CAL_COM_CTL_STATUS_DBG_DBG_CAP_STATE_ONE_HOT_BITS 5 6478 #define PLL_CAL_COM_CTL_STATUS_DBG_DBG_CAP_STATE_ONE_HOT_SHIFT 3 6479 6480 /* PLL_CAL_COM :: CTL_STATUS_DBG :: dbg_fdbck [02:02] */ 6481 #define PLL_CAL_COM_CTL_STATUS_DBG_DBG_FDBCK_MASK 0x0004 6482 #define PLL_CAL_COM_CTL_STATUS_DBG_DBG_FDBCK_ALIGN 0 6483 #define PLL_CAL_COM_CTL_STATUS_DBG_DBG_FDBCK_BITS 1 6484 #define PLL_CAL_COM_CTL_STATUS_DBG_DBG_FDBCK_SHIFT 2 6485 6486 /* PLL_CAL_COM :: CTL_STATUS_DBG :: dbg_slowdn_change [01:01] */ 6487 #define PLL_CAL_COM_CTL_STATUS_DBG_DBG_SLOWDN_CHANGE_MASK 0x0002 6488 #define PLL_CAL_COM_CTL_STATUS_DBG_DBG_SLOWDN_CHANGE_ALIGN 0 6489 #define PLL_CAL_COM_CTL_STATUS_DBG_DBG_SLOWDN_CHANGE_BITS 1 6490 #define PLL_CAL_COM_CTL_STATUS_DBG_DBG_SLOWDN_CHANGE_SHIFT 1 6491 6492 /* PLL_CAL_COM :: CTL_STATUS_DBG :: dbg_slowdn [00:00] */ 6493 #define PLL_CAL_COM_CTL_STATUS_DBG_DBG_SLOWDN_MASK 0x0001 6494 #define PLL_CAL_COM_CTL_STATUS_DBG_DBG_SLOWDN_ALIGN 0 6495 #define PLL_CAL_COM_CTL_STATUS_DBG_DBG_SLOWDN_BITS 1 6496 #define PLL_CAL_COM_CTL_STATUS_DBG_DBG_SLOWDN_SHIFT 0 6497 6498 6499 /**************************************************************************** 6500 * eagle_tsc_txcom_blk_TX_COM 6501 */ 6502 /**************************************************************************** 6503 * TX_COM :: CL72_TAP_LIMIT_CONTROL1 6504 */ 6505 /* TX_COM :: CL72_TAP_LIMIT_CONTROL1 :: reserved0 [15:11] */ 6506 #define TX_COM_CL72_TAP_LIMIT_CONTROL1_RESERVED0_MASK 0xf800 6507 #define TX_COM_CL72_TAP_LIMIT_CONTROL1_RESERVED0_ALIGN 0 6508 #define TX_COM_CL72_TAP_LIMIT_CONTROL1_RESERVED0_BITS 5 6509 #define TX_COM_CL72_TAP_LIMIT_CONTROL1_RESERVED0_SHIFT 11 6510 6511 /* TX_COM :: CL72_TAP_LIMIT_CONTROL1 :: post_tap_limit [10:05] */ 6512 #define TX_COM_CL72_TAP_LIMIT_CONTROL1_POST_TAP_LIMIT_MASK 0x07e0 6513 #define TX_COM_CL72_TAP_LIMIT_CONTROL1_POST_TAP_LIMIT_ALIGN 0 6514 #define TX_COM_CL72_TAP_LIMIT_CONTROL1_POST_TAP_LIMIT_BITS 6 6515 #define TX_COM_CL72_TAP_LIMIT_CONTROL1_POST_TAP_LIMIT_SHIFT 5 6516 6517 /* TX_COM :: CL72_TAP_LIMIT_CONTROL1 :: pre_tap_limit [04:00] */ 6518 #define TX_COM_CL72_TAP_LIMIT_CONTROL1_PRE_TAP_LIMIT_MASK 0x001f 6519 #define TX_COM_CL72_TAP_LIMIT_CONTROL1_PRE_TAP_LIMIT_ALIGN 0 6520 #define TX_COM_CL72_TAP_LIMIT_CONTROL1_PRE_TAP_LIMIT_BITS 5 6521 #define TX_COM_CL72_TAP_LIMIT_CONTROL1_PRE_TAP_LIMIT_SHIFT 0 6522 6523 6524 /**************************************************************************** 6525 * TX_COM :: CL72_TAP_LIMIT_CONTROL2 6526 */ 6527 /* TX_COM :: CL72_TAP_LIMIT_CONTROL2 :: reserved0 [15:07] */ 6528 #define TX_COM_CL72_TAP_LIMIT_CONTROL2_RESERVED0_MASK 0xff80 6529 #define TX_COM_CL72_TAP_LIMIT_CONTROL2_RESERVED0_ALIGN 0 6530 #define TX_COM_CL72_TAP_LIMIT_CONTROL2_RESERVED0_BITS 9 6531 #define TX_COM_CL72_TAP_LIMIT_CONTROL2_RESERVED0_SHIFT 7 6532 6533 /* TX_COM :: CL72_TAP_LIMIT_CONTROL2 :: main_tap_limit [06:00] */ 6534 #define TX_COM_CL72_TAP_LIMIT_CONTROL2_MAIN_TAP_LIMIT_MASK 0x007f 6535 #define TX_COM_CL72_TAP_LIMIT_CONTROL2_MAIN_TAP_LIMIT_ALIGN 0 6536 #define TX_COM_CL72_TAP_LIMIT_CONTROL2_MAIN_TAP_LIMIT_BITS 7 6537 #define TX_COM_CL72_TAP_LIMIT_CONTROL2_MAIN_TAP_LIMIT_SHIFT 0 6538 6539 6540 /**************************************************************************** 6541 * TX_COM :: CL72_TAP_PRESET_CONTROL 6542 */ 6543 /* TX_COM :: CL72_TAP_PRESET_CONTROL :: reserved0 [15:11] */ 6544 #define TX_COM_CL72_TAP_PRESET_CONTROL_RESERVED0_MASK 0xf800 6545 #define TX_COM_CL72_TAP_PRESET_CONTROL_RESERVED0_ALIGN 0 6546 #define TX_COM_CL72_TAP_PRESET_CONTROL_RESERVED0_BITS 5 6547 #define TX_COM_CL72_TAP_PRESET_CONTROL_RESERVED0_SHIFT 11 6548 6549 /* TX_COM :: CL72_TAP_PRESET_CONTROL :: pre_tap_preset_val [10:06] */ 6550 #define TX_COM_CL72_TAP_PRESET_CONTROL_PRE_TAP_PRESET_VAL_MASK 0x07c0 6551 #define TX_COM_CL72_TAP_PRESET_CONTROL_PRE_TAP_PRESET_VAL_ALIGN 0 6552 #define TX_COM_CL72_TAP_PRESET_CONTROL_PRE_TAP_PRESET_VAL_BITS 5 6553 #define TX_COM_CL72_TAP_PRESET_CONTROL_PRE_TAP_PRESET_VAL_SHIFT 6 6554 6555 /* TX_COM :: CL72_TAP_PRESET_CONTROL :: post_tap_preset_val [05:00] */ 6556 #define TX_COM_CL72_TAP_PRESET_CONTROL_POST_TAP_PRESET_VAL_MASK 0x003f 6557 #define TX_COM_CL72_TAP_PRESET_CONTROL_POST_TAP_PRESET_VAL_ALIGN 0 6558 #define TX_COM_CL72_TAP_PRESET_CONTROL_POST_TAP_PRESET_VAL_BITS 6 6559 #define TX_COM_CL72_TAP_PRESET_CONTROL_POST_TAP_PRESET_VAL_SHIFT 0 6560 6561 6562 /**************************************************************************** 6563 * TX_COM :: CL72_DEBUG_1_REGISTER 6564 */ 6565 /* TX_COM :: CL72_DEBUG_1_REGISTER :: reserved0 [15:15] */ 6566 #define TX_COM_CL72_DEBUG_1_REGISTER_RESERVED0_MASK 0x8000 6567 #define TX_COM_CL72_DEBUG_1_REGISTER_RESERVED0_ALIGN 0 6568 #define TX_COM_CL72_DEBUG_1_REGISTER_RESERVED0_BITS 1 6569 #define TX_COM_CL72_DEBUG_1_REGISTER_RESERVED0_SHIFT 15 6570 6571 /* TX_COM :: CL72_DEBUG_1_REGISTER :: tap_sum_max_val [14:07] */ 6572 #define TX_COM_CL72_DEBUG_1_REGISTER_TAP_SUM_MAX_VAL_MASK 0x7f80 6573 #define TX_COM_CL72_DEBUG_1_REGISTER_TAP_SUM_MAX_VAL_ALIGN 0 6574 #define TX_COM_CL72_DEBUG_1_REGISTER_TAP_SUM_MAX_VAL_BITS 8 6575 #define TX_COM_CL72_DEBUG_1_REGISTER_TAP_SUM_MAX_VAL_SHIFT 7 6576 6577 /* TX_COM :: CL72_DEBUG_1_REGISTER :: main_tap_min_val [06:00] */ 6578 #define TX_COM_CL72_DEBUG_1_REGISTER_MAIN_TAP_MIN_VAL_MASK 0x007f 6579 #define TX_COM_CL72_DEBUG_1_REGISTER_MAIN_TAP_MIN_VAL_ALIGN 0 6580 #define TX_COM_CL72_DEBUG_1_REGISTER_MAIN_TAP_MIN_VAL_BITS 7 6581 #define TX_COM_CL72_DEBUG_1_REGISTER_MAIN_TAP_MIN_VAL_SHIFT 0 6582 6583 6584 /**************************************************************************** 6585 * TX_COM :: CL72_MAX_WAIT_TIMER_REGISTER 6586 */ 6587 /* TX_COM :: CL72_MAX_WAIT_TIMER_REGISTER :: max_wait_timer_period [15:00] */ 6588 #define TX_COM_CL72_MAX_WAIT_TIMER_REGISTER_MAX_WAIT_TIMER_PERIOD_MASK 0xffff 6589 #define TX_COM_CL72_MAX_WAIT_TIMER_REGISTER_MAX_WAIT_TIMER_PERIOD_ALIGN 0 6590 #define TX_COM_CL72_MAX_WAIT_TIMER_REGISTER_MAX_WAIT_TIMER_PERIOD_BITS 16 6591 #define TX_COM_CL72_MAX_WAIT_TIMER_REGISTER_MAX_WAIT_TIMER_PERIOD_SHIFT 0 6592 6593 6594 /**************************************************************************** 6595 * TX_COM :: CL72_WAIT_TIMER_REGISTER 6596 */ 6597 /* TX_COM :: CL72_WAIT_TIMER_REGISTER :: reserved0 [15:09] */ 6598 #define TX_COM_CL72_WAIT_TIMER_REGISTER_RESERVED0_MASK 0xfe00 6599 #define TX_COM_CL72_WAIT_TIMER_REGISTER_RESERVED0_ALIGN 0 6600 #define TX_COM_CL72_WAIT_TIMER_REGISTER_RESERVED0_BITS 7 6601 #define TX_COM_CL72_WAIT_TIMER_REGISTER_RESERVED0_SHIFT 9 6602 6603 /* TX_COM :: CL72_WAIT_TIMER_REGISTER :: wait_cntr_limit [08:00] */ 6604 #define TX_COM_CL72_WAIT_TIMER_REGISTER_WAIT_CNTR_LIMIT_MASK 0x01ff 6605 #define TX_COM_CL72_WAIT_TIMER_REGISTER_WAIT_CNTR_LIMIT_ALIGN 0 6606 #define TX_COM_CL72_WAIT_TIMER_REGISTER_WAIT_CNTR_LIMIT_BITS 9 6607 #define TX_COM_CL72_WAIT_TIMER_REGISTER_WAIT_CNTR_LIMIT_SHIFT 0 6608 6609 6610 /**************************************************************************** 6611 * eagle_tsc_micro_blk_MICRO_A_COM 6612 */ 6613 /**************************************************************************** 6614 * MICRO_A_COM :: RAMWORD 6615 */ 6616 /* MICRO_A_COM :: RAMWORD :: micro_ram_count [15:00] */ 6617 #define MICRO_A_COM_RAMWORD_MICRO_RAM_COUNT_MASK 0xffff 6618 #define MICRO_A_COM_RAMWORD_MICRO_RAM_COUNT_ALIGN 0 6619 #define MICRO_A_COM_RAMWORD_MICRO_RAM_COUNT_BITS 16 6620 #define MICRO_A_COM_RAMWORD_MICRO_RAM_COUNT_SHIFT 0 6621 6622 6623 /**************************************************************************** 6624 * MICRO_A_COM :: ADDRESS 6625 */ 6626 /* MICRO_A_COM :: ADDRESS :: micro_ram_address [15:00] */ 6627 #define MICRO_A_COM_ADDRESS_MICRO_RAM_ADDRESS_MASK 0xffff 6628 #define MICRO_A_COM_ADDRESS_MICRO_RAM_ADDRESS_ALIGN 0 6629 #define MICRO_A_COM_ADDRESS_MICRO_RAM_ADDRESS_BITS 16 6630 #define MICRO_A_COM_ADDRESS_MICRO_RAM_ADDRESS_SHIFT 0 6631 6632 6633 /**************************************************************************** 6634 * MICRO_A_COM :: COMMAND 6635 */ 6636 /* MICRO_A_COM :: COMMAND :: micro_init_cmd [15:15] */ 6637 #define MICRO_A_COM_COMMAND_MICRO_INIT_CMD_MASK 0x8000 6638 #define MICRO_A_COM_COMMAND_MICRO_INIT_CMD_ALIGN 0 6639 #define MICRO_A_COM_COMMAND_MICRO_INIT_CMD_BITS 1 6640 #define MICRO_A_COM_COMMAND_MICRO_INIT_CMD_SHIFT 15 6641 6642 /* MICRO_A_COM :: COMMAND :: micro_pmi_hp_ack_frc_val [14:14] */ 6643 #define MICRO_A_COM_COMMAND_MICRO_PMI_HP_ACK_FRC_VAL_MASK 0x4000 6644 #define MICRO_A_COM_COMMAND_MICRO_PMI_HP_ACK_FRC_VAL_ALIGN 0 6645 #define MICRO_A_COM_COMMAND_MICRO_PMI_HP_ACK_FRC_VAL_BITS 1 6646 #define MICRO_A_COM_COMMAND_MICRO_PMI_HP_ACK_FRC_VAL_SHIFT 14 6647 6648 /* MICRO_A_COM :: COMMAND :: micro_pmi_hp_ack_frc [13:13] */ 6649 #define MICRO_A_COM_COMMAND_MICRO_PMI_HP_ACK_FRC_MASK 0x2000 6650 #define MICRO_A_COM_COMMAND_MICRO_PMI_HP_ACK_FRC_ALIGN 0 6651 #define MICRO_A_COM_COMMAND_MICRO_PMI_HP_ACK_FRC_BITS 1 6652 #define MICRO_A_COM_COMMAND_MICRO_PMI_HP_ACK_FRC_SHIFT 13 6653 6654 /* MICRO_A_COM :: COMMAND :: micro_mdio_prog_ram_cs_frc_val [12:12] */ 6655 #define MICRO_A_COM_COMMAND_MICRO_MDIO_PROG_RAM_CS_FRC_VAL_MASK 0x1000 6656 #define MICRO_A_COM_COMMAND_MICRO_MDIO_PROG_RAM_CS_FRC_VAL_ALIGN 0 6657 #define MICRO_A_COM_COMMAND_MICRO_MDIO_PROG_RAM_CS_FRC_VAL_BITS 1 6658 #define MICRO_A_COM_COMMAND_MICRO_MDIO_PROG_RAM_CS_FRC_VAL_SHIFT 12 6659 6660 /* MICRO_A_COM :: COMMAND :: micro_mdio_prog_ram_cs_frc [11:11] */ 6661 #define MICRO_A_COM_COMMAND_MICRO_MDIO_PROG_RAM_CS_FRC_MASK 0x0800 6662 #define MICRO_A_COM_COMMAND_MICRO_MDIO_PROG_RAM_CS_FRC_ALIGN 0 6663 #define MICRO_A_COM_COMMAND_MICRO_MDIO_PROG_RAM_CS_FRC_BITS 1 6664 #define MICRO_A_COM_COMMAND_MICRO_MDIO_PROG_RAM_CS_FRC_SHIFT 11 6665 6666 /* MICRO_A_COM :: COMMAND :: micro_mdio_autowakeup [10:10] */ 6667 #define MICRO_A_COM_COMMAND_MICRO_MDIO_AUTOWAKEUP_MASK 0x0400 6668 #define MICRO_A_COM_COMMAND_MICRO_MDIO_AUTOWAKEUP_ALIGN 0 6669 #define MICRO_A_COM_COMMAND_MICRO_MDIO_AUTOWAKEUP_BITS 1 6670 #define MICRO_A_COM_COMMAND_MICRO_MDIO_AUTOWAKEUP_SHIFT 10 6671 6672 /* MICRO_A_COM :: COMMAND :: micro_byte_mode [09:09] */ 6673 #define MICRO_A_COM_COMMAND_MICRO_BYTE_MODE_MASK 0x0200 6674 #define MICRO_A_COM_COMMAND_MICRO_BYTE_MODE_ALIGN 0 6675 #define MICRO_A_COM_COMMAND_MICRO_BYTE_MODE_BITS 1 6676 #define MICRO_A_COM_COMMAND_MICRO_BYTE_MODE_SHIFT 9 6677 6678 /* MICRO_A_COM :: COMMAND :: micro_mdio_ram_access_mode [08:07] */ 6679 #define MICRO_A_COM_COMMAND_MICRO_MDIO_RAM_ACCESS_MODE_MASK 0x0180 6680 #define MICRO_A_COM_COMMAND_MICRO_MDIO_RAM_ACCESS_MODE_ALIGN 0 6681 #define MICRO_A_COM_COMMAND_MICRO_MDIO_RAM_ACCESS_MODE_BITS 2 6682 #define MICRO_A_COM_COMMAND_MICRO_MDIO_RAM_ACCESS_MODE_SHIFT 7 6683 6684 /* MICRO_A_COM :: COMMAND :: micro_mdio_ram_read_autoinc_en [06:06] */ 6685 #define MICRO_A_COM_COMMAND_MICRO_MDIO_RAM_READ_AUTOINC_EN_MASK 0x0040 6686 #define MICRO_A_COM_COMMAND_MICRO_MDIO_RAM_READ_AUTOINC_EN_ALIGN 0 6687 #define MICRO_A_COM_COMMAND_MICRO_MDIO_RAM_READ_AUTOINC_EN_BITS 1 6688 #define MICRO_A_COM_COMMAND_MICRO_MDIO_RAM_READ_AUTOINC_EN_SHIFT 6 6689 6690 /* MICRO_A_COM :: COMMAND :: reserved0 [05:05] */ 6691 #define MICRO_A_COM_COMMAND_RESERVED0_MASK 0x0020 6692 #define MICRO_A_COM_COMMAND_RESERVED0_ALIGN 0 6693 #define MICRO_A_COM_COMMAND_RESERVED0_BITS 1 6694 #define MICRO_A_COM_COMMAND_RESERVED0_SHIFT 5 6695 6696 /* MICRO_A_COM :: COMMAND :: micro_mdio_dw8051_reset_n [04:04] */ 6697 #define MICRO_A_COM_COMMAND_MICRO_MDIO_DW8051_RESET_N_MASK 0x0010 6698 #define MICRO_A_COM_COMMAND_MICRO_MDIO_DW8051_RESET_N_ALIGN 0 6699 #define MICRO_A_COM_COMMAND_MICRO_MDIO_DW8051_RESET_N_BITS 1 6700 #define MICRO_A_COM_COMMAND_MICRO_MDIO_DW8051_RESET_N_SHIFT 4 6701 6702 /* MICRO_A_COM :: COMMAND :: micro_write [03:03] */ 6703 #define MICRO_A_COM_COMMAND_MICRO_WRITE_MASK 0x0008 6704 #define MICRO_A_COM_COMMAND_MICRO_WRITE_ALIGN 0 6705 #define MICRO_A_COM_COMMAND_MICRO_WRITE_BITS 1 6706 #define MICRO_A_COM_COMMAND_MICRO_WRITE_SHIFT 3 6707 6708 /* MICRO_A_COM :: COMMAND :: micro_read [02:02] */ 6709 #define MICRO_A_COM_COMMAND_MICRO_READ_MASK 0x0004 6710 #define MICRO_A_COM_COMMAND_MICRO_READ_ALIGN 0 6711 #define MICRO_A_COM_COMMAND_MICRO_READ_BITS 1 6712 #define MICRO_A_COM_COMMAND_MICRO_READ_SHIFT 2 6713 6714 /* MICRO_A_COM :: COMMAND :: micro_stop [01:01] */ 6715 #define MICRO_A_COM_COMMAND_MICRO_STOP_MASK 0x0002 6716 #define MICRO_A_COM_COMMAND_MICRO_STOP_ALIGN 0 6717 #define MICRO_A_COM_COMMAND_MICRO_STOP_BITS 1 6718 #define MICRO_A_COM_COMMAND_MICRO_STOP_SHIFT 1 6719 6720 /* MICRO_A_COM :: COMMAND :: micro_run [00:00] */ 6721 #define MICRO_A_COM_COMMAND_MICRO_RUN_MASK 0x0001 6722 #define MICRO_A_COM_COMMAND_MICRO_RUN_ALIGN 0 6723 #define MICRO_A_COM_COMMAND_MICRO_RUN_BITS 1 6724 #define MICRO_A_COM_COMMAND_MICRO_RUN_SHIFT 0 6725 6726 6727 /**************************************************************************** 6728 * MICRO_A_COM :: RAM_WRDATA 6729 */ 6730 /* MICRO_A_COM :: RAM_WRDATA :: micro_ram_wrdata [15:00] */ 6731 #define MICRO_A_COM_RAM_WRDATA_MICRO_RAM_WRDATA_MASK 0xffff 6732 #define MICRO_A_COM_RAM_WRDATA_MICRO_RAM_WRDATA_ALIGN 0 6733 #define MICRO_A_COM_RAM_WRDATA_MICRO_RAM_WRDATA_BITS 16 6734 #define MICRO_A_COM_RAM_WRDATA_MICRO_RAM_WRDATA_SHIFT 0 6735 6736 6737 /**************************************************************************** 6738 * MICRO_A_COM :: RAM_RDDATA 6739 */ 6740 /* MICRO_A_COM :: RAM_RDDATA :: micro_ram_rddata [15:00] */ 6741 #define MICRO_A_COM_RAM_RDDATA_MICRO_RAM_RDDATA_MASK 0xffff 6742 #define MICRO_A_COM_RAM_RDDATA_MICRO_RAM_RDDATA_ALIGN 0 6743 #define MICRO_A_COM_RAM_RDDATA_MICRO_RAM_RDDATA_BITS 16 6744 #define MICRO_A_COM_RAM_RDDATA_MICRO_RAM_RDDATA_SHIFT 0 6745 6746 6747 /**************************************************************************** 6748 * MICRO_A_COM :: DOWNLOAD_STATUS 6749 */ 6750 /* MICRO_A_COM :: DOWNLOAD_STATUS :: micro_init_done [15:15] */ 6751 #define MICRO_A_COM_DOWNLOAD_STATUS_MICRO_INIT_DONE_MASK 0x8000 6752 #define MICRO_A_COM_DOWNLOAD_STATUS_MICRO_INIT_DONE_ALIGN 0 6753 #define MICRO_A_COM_DOWNLOAD_STATUS_MICRO_INIT_DONE_BITS 1 6754 #define MICRO_A_COM_DOWNLOAD_STATUS_MICRO_INIT_DONE_SHIFT 15 6755 6756 /* MICRO_A_COM :: DOWNLOAD_STATUS :: reserved0 [14:06] */ 6757 #define MICRO_A_COM_DOWNLOAD_STATUS_RESERVED0_MASK 0x7fc0 6758 #define MICRO_A_COM_DOWNLOAD_STATUS_RESERVED0_ALIGN 0 6759 #define MICRO_A_COM_DOWNLOAD_STATUS_RESERVED0_BITS 9 6760 #define MICRO_A_COM_DOWNLOAD_STATUS_RESERVED0_SHIFT 6 6761 6762 /* MICRO_A_COM :: DOWNLOAD_STATUS :: micro_fsm [05:02] */ 6763 #define MICRO_A_COM_DOWNLOAD_STATUS_MICRO_FSM_MASK 0x003c 6764 #define MICRO_A_COM_DOWNLOAD_STATUS_MICRO_FSM_ALIGN 0 6765 #define MICRO_A_COM_DOWNLOAD_STATUS_MICRO_FSM_BITS 4 6766 #define MICRO_A_COM_DOWNLOAD_STATUS_MICRO_FSM_SHIFT 2 6767 6768 /* MICRO_A_COM :: DOWNLOAD_STATUS :: micro_err1 [01:01] */ 6769 #define MICRO_A_COM_DOWNLOAD_STATUS_MICRO_ERR1_MASK 0x0002 6770 #define MICRO_A_COM_DOWNLOAD_STATUS_MICRO_ERR1_ALIGN 0 6771 #define MICRO_A_COM_DOWNLOAD_STATUS_MICRO_ERR1_BITS 1 6772 #define MICRO_A_COM_DOWNLOAD_STATUS_MICRO_ERR1_SHIFT 1 6773 6774 /* MICRO_A_COM :: DOWNLOAD_STATUS :: micro_err0 [00:00] */ 6775 #define MICRO_A_COM_DOWNLOAD_STATUS_MICRO_ERR0_MASK 0x0001 6776 #define MICRO_A_COM_DOWNLOAD_STATUS_MICRO_ERR0_ALIGN 0 6777 #define MICRO_A_COM_DOWNLOAD_STATUS_MICRO_ERR0_BITS 1 6778 #define MICRO_A_COM_DOWNLOAD_STATUS_MICRO_ERR0_SHIFT 0 6779 6780 6781 /**************************************************************************** 6782 * MICRO_A_COM :: SFR_STATUS 6783 */ 6784 /* MICRO_A_COM :: SFR_STATUS :: micro_status_muxed [15:00] */ 6785 #define MICRO_A_COM_SFR_STATUS_MICRO_STATUS_MUXED_MASK 0xffff 6786 #define MICRO_A_COM_SFR_STATUS_MICRO_STATUS_MUXED_ALIGN 0 6787 #define MICRO_A_COM_SFR_STATUS_MICRO_STATUS_MUXED_BITS 16 6788 #define MICRO_A_COM_SFR_STATUS_MICRO_STATUS_MUXED_SHIFT 0 6789 6790 6791 /**************************************************************************** 6792 * MICRO_A_COM :: MDIO_UC_MAILBOX_MSW 6793 */ 6794 /* MICRO_A_COM :: MDIO_UC_MAILBOX_MSW :: micro_mdio_uc_mailbox_msw [15:00] */ 6795 #define MICRO_A_COM_MDIO_UC_MAILBOX_MSW_MICRO_MDIO_UC_MAILBOX_MSW_MASK 0xffff 6796 #define MICRO_A_COM_MDIO_UC_MAILBOX_MSW_MICRO_MDIO_UC_MAILBOX_MSW_ALIGN 0 6797 #define MICRO_A_COM_MDIO_UC_MAILBOX_MSW_MICRO_MDIO_UC_MAILBOX_MSW_BITS 16 6798 #define MICRO_A_COM_MDIO_UC_MAILBOX_MSW_MICRO_MDIO_UC_MAILBOX_MSW_SHIFT 0 6799 6800 6801 /**************************************************************************** 6802 * MICRO_A_COM :: MDIO_UC_MAILBOX_LSW 6803 */ 6804 /* MICRO_A_COM :: MDIO_UC_MAILBOX_LSW :: micro_mdio_uc_mailbox_lsw [15:00] */ 6805 #define MICRO_A_COM_MDIO_UC_MAILBOX_LSW_MICRO_MDIO_UC_MAILBOX_LSW_MASK 0xffff 6806 #define MICRO_A_COM_MDIO_UC_MAILBOX_LSW_MICRO_MDIO_UC_MAILBOX_LSW_ALIGN 0 6807 #define MICRO_A_COM_MDIO_UC_MAILBOX_LSW_MICRO_MDIO_UC_MAILBOX_LSW_BITS 16 6808 #define MICRO_A_COM_MDIO_UC_MAILBOX_LSW_MICRO_MDIO_UC_MAILBOX_LSW_SHIFT 0 6809 6810 6811 /**************************************************************************** 6812 * MICRO_A_COM :: UC_MDIO_MAILBOX_LSW 6813 */ 6814 /* MICRO_A_COM :: UC_MDIO_MAILBOX_LSW :: micro_uc_mdio_mailbox_lsw [15:00] */ 6815 #define MICRO_A_COM_UC_MDIO_MAILBOX_LSW_MICRO_UC_MDIO_MAILBOX_LSW_MASK 0xffff 6816 #define MICRO_A_COM_UC_MDIO_MAILBOX_LSW_MICRO_UC_MDIO_MAILBOX_LSW_ALIGN 0 6817 #define MICRO_A_COM_UC_MDIO_MAILBOX_LSW_MICRO_UC_MDIO_MAILBOX_LSW_BITS 16 6818 #define MICRO_A_COM_UC_MDIO_MAILBOX_LSW_MICRO_UC_MDIO_MAILBOX_LSW_SHIFT 0 6819 6820 6821 /**************************************************************************** 6822 * MICRO_A_COM :: COMMAND2 6823 */ 6824 /* MICRO_A_COM :: COMMAND2 :: micro_srst_dw8051_to_pmi [15:15] */ 6825 #define MICRO_A_COM_COMMAND2_MICRO_SRST_DW8051_TO_PMI_MASK 0x8000 6826 #define MICRO_A_COM_COMMAND2_MICRO_SRST_DW8051_TO_PMI_ALIGN 0 6827 #define MICRO_A_COM_COMMAND2_MICRO_SRST_DW8051_TO_PMI_BITS 1 6828 #define MICRO_A_COM_COMMAND2_MICRO_SRST_DW8051_TO_PMI_SHIFT 15 6829 6830 /* MICRO_A_COM :: COMMAND2 :: micro_srst_mdio_program_access [14:14] */ 6831 #define MICRO_A_COM_COMMAND2_MICRO_SRST_MDIO_PROGRAM_ACCESS_MASK 0x4000 6832 #define MICRO_A_COM_COMMAND2_MICRO_SRST_MDIO_PROGRAM_ACCESS_ALIGN 0 6833 #define MICRO_A_COM_COMMAND2_MICRO_SRST_MDIO_PROGRAM_ACCESS_BITS 1 6834 #define MICRO_A_COM_COMMAND2_MICRO_SRST_MDIO_PROGRAM_ACCESS_SHIFT 14 6835 6836 /* MICRO_A_COM :: COMMAND2 :: micro_srst_mdio_load_program_ram [13:13] */ 6837 #define MICRO_A_COM_COMMAND2_MICRO_SRST_MDIO_LOAD_PROGRAM_RAM_MASK 0x2000 6838 #define MICRO_A_COM_COMMAND2_MICRO_SRST_MDIO_LOAD_PROGRAM_RAM_ALIGN 0 6839 #define MICRO_A_COM_COMMAND2_MICRO_SRST_MDIO_LOAD_PROGRAM_RAM_BITS 1 6840 #define MICRO_A_COM_COMMAND2_MICRO_SRST_MDIO_LOAD_PROGRAM_RAM_SHIFT 13 6841 6842 /* MICRO_A_COM :: COMMAND2 :: micro_zero_rom_dataout [12:12] */ 6843 #define MICRO_A_COM_COMMAND2_MICRO_ZERO_ROM_DATAOUT_MASK 0x1000 6844 #define MICRO_A_COM_COMMAND2_MICRO_ZERO_ROM_DATAOUT_ALIGN 0 6845 #define MICRO_A_COM_COMMAND2_MICRO_ZERO_ROM_DATAOUT_BITS 1 6846 #define MICRO_A_COM_COMMAND2_MICRO_ZERO_ROM_DATAOUT_SHIFT 12 6847 6848 /* MICRO_A_COM :: COMMAND2 :: micro_ram_clk_invert [11:11] */ 6849 #define MICRO_A_COM_COMMAND2_MICRO_RAM_CLK_INVERT_MASK 0x0800 6850 #define MICRO_A_COM_COMMAND2_MICRO_RAM_CLK_INVERT_ALIGN 0 6851 #define MICRO_A_COM_COMMAND2_MICRO_RAM_CLK_INVERT_BITS 1 6852 #define MICRO_A_COM_COMMAND2_MICRO_RAM_CLK_INVERT_SHIFT 11 6853 6854 /* MICRO_A_COM :: COMMAND2 :: micro_srst_mdio_dataram_access [10:10] */ 6855 #define MICRO_A_COM_COMMAND2_MICRO_SRST_MDIO_DATARAM_ACCESS_MASK 0x0400 6856 #define MICRO_A_COM_COMMAND2_MICRO_SRST_MDIO_DATARAM_ACCESS_ALIGN 0 6857 #define MICRO_A_COM_COMMAND2_MICRO_SRST_MDIO_DATARAM_ACCESS_BITS 1 6858 #define MICRO_A_COM_COMMAND2_MICRO_SRST_MDIO_DATARAM_ACCESS_SHIFT 10 6859 6860 /* MICRO_A_COM :: COMMAND2 :: reserved0 [09:04] */ 6861 #define MICRO_A_COM_COMMAND2_RESERVED0_MASK 0x03f0 6862 #define MICRO_A_COM_COMMAND2_RESERVED0_ALIGN 0 6863 #define MICRO_A_COM_COMMAND2_RESERVED0_BITS 6 6864 #define MICRO_A_COM_COMMAND2_RESERVED0_SHIFT 4 6865 6866 /* MICRO_A_COM :: COMMAND2 :: micro_pmi_ack_timeout_val [03:00] */ 6867 #define MICRO_A_COM_COMMAND2_MICRO_PMI_ACK_TIMEOUT_VAL_MASK 0x000f 6868 #define MICRO_A_COM_COMMAND2_MICRO_PMI_ACK_TIMEOUT_VAL_ALIGN 0 6869 #define MICRO_A_COM_COMMAND2_MICRO_PMI_ACK_TIMEOUT_VAL_BITS 4 6870 #define MICRO_A_COM_COMMAND2_MICRO_PMI_ACK_TIMEOUT_VAL_SHIFT 0 6871 6872 6873 /**************************************************************************** 6874 * MICRO_A_COM :: UC_MDIO_MAILBOX_MSW 6875 */ 6876 /* MICRO_A_COM :: UC_MDIO_MAILBOX_MSW :: micro_uc_mdio_mailbox_msw [15:00] */ 6877 #define MICRO_A_COM_UC_MDIO_MAILBOX_MSW_MICRO_UC_MDIO_MAILBOX_MSW_MASK 0xffff 6878 #define MICRO_A_COM_UC_MDIO_MAILBOX_MSW_MICRO_UC_MDIO_MAILBOX_MSW_ALIGN 0 6879 #define MICRO_A_COM_UC_MDIO_MAILBOX_MSW_MICRO_UC_MDIO_MAILBOX_MSW_BITS 16 6880 #define MICRO_A_COM_UC_MDIO_MAILBOX_MSW_MICRO_UC_MDIO_MAILBOX_MSW_SHIFT 0 6881 6882 6883 /**************************************************************************** 6884 * MICRO_A_COM :: COMMAND3 6885 */ 6886 /* MICRO_A_COM :: COMMAND3 :: micro_gen_status_sel [15:13] */ 6887 #define MICRO_A_COM_COMMAND3_MICRO_GEN_STATUS_SEL_MASK 0xe000 6888 #define MICRO_A_COM_COMMAND3_MICRO_GEN_STATUS_SEL_ALIGN 0 6889 #define MICRO_A_COM_COMMAND3_MICRO_GEN_STATUS_SEL_BITS 3 6890 #define MICRO_A_COM_COMMAND3_MICRO_GEN_STATUS_SEL_SHIFT 13 6891 #define MICRO_A_COM_COMMAND3_MICRO_GEN_STATUS_SEL_ecc_error_counters 0 6892 #define MICRO_A_COM_COMMAND3_MICRO_GEN_STATUS_SEL_program_ram_load_status 1 6893 #define MICRO_A_COM_COMMAND3_MICRO_GEN_STATUS_SEL_program_ram_mdio_status 2 6894 #define MICRO_A_COM_COMMAND3_MICRO_GEN_STATUS_SEL_dataram_mdio_status 3 6895 #define MICRO_A_COM_COMMAND3_MICRO_GEN_STATUS_SEL_pmi_status 4 6896 6897 /* MICRO_A_COM :: COMMAND3 :: micro_disable_ecc [12:12] */ 6898 #define MICRO_A_COM_COMMAND3_MICRO_DISABLE_ECC_MASK 0x1000 6899 #define MICRO_A_COM_COMMAND3_MICRO_DISABLE_ECC_ALIGN 0 6900 #define MICRO_A_COM_COMMAND3_MICRO_DISABLE_ECC_BITS 1 6901 #define MICRO_A_COM_COMMAND3_MICRO_DISABLE_ECC_SHIFT 12 6902 6903 /* MICRO_A_COM :: COMMAND3 :: micro_inrush_current_frc_val [11:11] */ 6904 #define MICRO_A_COM_COMMAND3_MICRO_INRUSH_CURRENT_FRC_VAL_MASK 0x0800 6905 #define MICRO_A_COM_COMMAND3_MICRO_INRUSH_CURRENT_FRC_VAL_ALIGN 0 6906 #define MICRO_A_COM_COMMAND3_MICRO_INRUSH_CURRENT_FRC_VAL_BITS 1 6907 #define MICRO_A_COM_COMMAND3_MICRO_INRUSH_CURRENT_FRC_VAL_SHIFT 11 6908 6909 /* MICRO_A_COM :: COMMAND3 :: micro_inrush_current_frc [10:10] */ 6910 #define MICRO_A_COM_COMMAND3_MICRO_INRUSH_CURRENT_FRC_MASK 0x0400 6911 #define MICRO_A_COM_COMMAND3_MICRO_INRUSH_CURRENT_FRC_ALIGN 0 6912 #define MICRO_A_COM_COMMAND3_MICRO_INRUSH_CURRENT_FRC_BITS 1 6913 #define MICRO_A_COM_COMMAND3_MICRO_INRUSH_CURRENT_FRC_SHIFT 10 6914 6915 /* MICRO_A_COM :: COMMAND3 :: reserved0 [09:03] */ 6916 #define MICRO_A_COM_COMMAND3_RESERVED0_MASK 0x03f8 6917 #define MICRO_A_COM_COMMAND3_RESERVED0_ALIGN 0 6918 #define MICRO_A_COM_COMMAND3_RESERVED0_BITS 7 6919 #define MICRO_A_COM_COMMAND3_RESERVED0_SHIFT 3 6920 6921 /* MICRO_A_COM :: COMMAND3 :: micro_pram_if_rstb [02:02] */ 6922 #define MICRO_A_COM_COMMAND3_MICRO_PRAM_IF_RSTB_MASK 0x0004 6923 #define MICRO_A_COM_COMMAND3_MICRO_PRAM_IF_RSTB_ALIGN 0 6924 #define MICRO_A_COM_COMMAND3_MICRO_PRAM_IF_RSTB_BITS 1 6925 #define MICRO_A_COM_COMMAND3_MICRO_PRAM_IF_RSTB_SHIFT 2 6926 6927 /* MICRO_A_COM :: COMMAND3 :: micro_pram_if_flop_bypass [01:01] */ 6928 #define MICRO_A_COM_COMMAND3_MICRO_PRAM_IF_FLOP_BYPASS_MASK 0x0002 6929 #define MICRO_A_COM_COMMAND3_MICRO_PRAM_IF_FLOP_BYPASS_ALIGN 0 6930 #define MICRO_A_COM_COMMAND3_MICRO_PRAM_IF_FLOP_BYPASS_BITS 1 6931 #define MICRO_A_COM_COMMAND3_MICRO_PRAM_IF_FLOP_BYPASS_SHIFT 1 6932 6933 /* MICRO_A_COM :: COMMAND3 :: micro_pram_if_en [00:00] */ 6934 #define MICRO_A_COM_COMMAND3_MICRO_PRAM_IF_EN_MASK 0x0001 6935 #define MICRO_A_COM_COMMAND3_MICRO_PRAM_IF_EN_ALIGN 0 6936 #define MICRO_A_COM_COMMAND3_MICRO_PRAM_IF_EN_BITS 1 6937 #define MICRO_A_COM_COMMAND3_MICRO_PRAM_IF_EN_SHIFT 0 6938 6939 6940 /**************************************************************************** 6941 * MICRO_A_COM :: COMMAND4 6942 */ 6943 /* MICRO_A_COM :: COMMAND4 :: reserved0 [15:02] */ 6944 #define MICRO_A_COM_COMMAND4_RESERVED0_MASK 0xfffc 6945 #define MICRO_A_COM_COMMAND4_RESERVED0_ALIGN 0 6946 #define MICRO_A_COM_COMMAND4_RESERVED0_BITS 14 6947 #define MICRO_A_COM_COMMAND4_RESERVED0_SHIFT 2 6948 6949 /* MICRO_A_COM :: COMMAND4 :: micro_system_reset_n [01:01] */ 6950 #define MICRO_A_COM_COMMAND4_MICRO_SYSTEM_RESET_N_MASK 0x0002 6951 #define MICRO_A_COM_COMMAND4_MICRO_SYSTEM_RESET_N_ALIGN 0 6952 #define MICRO_A_COM_COMMAND4_MICRO_SYSTEM_RESET_N_BITS 1 6953 #define MICRO_A_COM_COMMAND4_MICRO_SYSTEM_RESET_N_SHIFT 1 6954 6955 /* MICRO_A_COM :: COMMAND4 :: micro_system_clk_en [00:00] */ 6956 #define MICRO_A_COM_COMMAND4_MICRO_SYSTEM_CLK_EN_MASK 0x0001 6957 #define MICRO_A_COM_COMMAND4_MICRO_SYSTEM_CLK_EN_ALIGN 0 6958 #define MICRO_A_COM_COMMAND4_MICRO_SYSTEM_CLK_EN_BITS 1 6959 #define MICRO_A_COM_COMMAND4_MICRO_SYSTEM_CLK_EN_SHIFT 0 6960 6961 6962 /**************************************************************************** 6963 * MICRO_A_COM :: TEMPERATURE_STATUS 6964 */ 6965 /* MICRO_A_COM :: TEMPERATURE_STATUS :: micro_tempature_data [15:00] */ 6966 #define MICRO_A_COM_TEMPERATURE_STATUS_MICRO_TEMPATURE_DATA_MASK 0xffff 6967 #define MICRO_A_COM_TEMPERATURE_STATUS_MICRO_TEMPATURE_DATA_ALIGN 0 6968 #define MICRO_A_COM_TEMPERATURE_STATUS_MICRO_TEMPATURE_DATA_BITS 16 6969 #define MICRO_A_COM_TEMPERATURE_STATUS_MICRO_TEMPATURE_DATA_SHIFT 0 6970 6971 6972 /**************************************************************************** 6973 * eagle_tsc_micro_blk_MICRO_B_COM 6974 */ 6975 /**************************************************************************** 6976 * MICRO_B_COM :: PROGRAM_RAM_CONTROL1 6977 */ 6978 /* MICRO_B_COM :: PROGRAM_RAM_CONTROL1 :: reserved0 [15:14] */ 6979 #define MICRO_B_COM_PROGRAM_RAM_CONTROL1_RESERVED0_MASK 0xc000 6980 #define MICRO_B_COM_PROGRAM_RAM_CONTROL1_RESERVED0_ALIGN 0 6981 #define MICRO_B_COM_PROGRAM_RAM_CONTROL1_RESERVED0_BITS 2 6982 #define MICRO_B_COM_PROGRAM_RAM_CONTROL1_RESERVED0_SHIFT 14 6983 6984 /* MICRO_B_COM :: PROGRAM_RAM_CONTROL1 :: micro_program_ram_tm [13:00] */ 6985 #define MICRO_B_COM_PROGRAM_RAM_CONTROL1_MICRO_PROGRAM_RAM_TM_MASK 0x3fff 6986 #define MICRO_B_COM_PROGRAM_RAM_CONTROL1_MICRO_PROGRAM_RAM_TM_ALIGN 0 6987 #define MICRO_B_COM_PROGRAM_RAM_CONTROL1_MICRO_PROGRAM_RAM_TM_BITS 14 6988 #define MICRO_B_COM_PROGRAM_RAM_CONTROL1_MICRO_PROGRAM_RAM_TM_SHIFT 0 6989 6990 6991 /**************************************************************************** 6992 * MICRO_B_COM :: DATARAM_CONTROL1 6993 */ 6994 /* MICRO_B_COM :: DATARAM_CONTROL1 :: reserved0 [15:10] */ 6995 #define MICRO_B_COM_DATARAM_CONTROL1_RESERVED0_MASK 0xfc00 6996 #define MICRO_B_COM_DATARAM_CONTROL1_RESERVED0_ALIGN 0 6997 #define MICRO_B_COM_DATARAM_CONTROL1_RESERVED0_BITS 6 6998 #define MICRO_B_COM_DATARAM_CONTROL1_RESERVED0_SHIFT 10 6999 7000 /* MICRO_B_COM :: DATARAM_CONTROL1 :: micro_dataram_tm [09:00] */ 7001 #define MICRO_B_COM_DATARAM_CONTROL1_MICRO_DATARAM_TM_MASK 0x03ff 7002 #define MICRO_B_COM_DATARAM_CONTROL1_MICRO_DATARAM_TM_ALIGN 0 7003 #define MICRO_B_COM_DATARAM_CONTROL1_MICRO_DATARAM_TM_BITS 10 7004 #define MICRO_B_COM_DATARAM_CONTROL1_MICRO_DATARAM_TM_SHIFT 0 7005 7006 7007 /**************************************************************************** 7008 * MICRO_B_COM :: IRAM_CONTROL1 7009 */ 7010 /* MICRO_B_COM :: IRAM_CONTROL1 :: reserved0 [15:10] */ 7011 #define MICRO_B_COM_IRAM_CONTROL1_RESERVED0_MASK 0xfc00 7012 #define MICRO_B_COM_IRAM_CONTROL1_RESERVED0_ALIGN 0 7013 #define MICRO_B_COM_IRAM_CONTROL1_RESERVED0_BITS 6 7014 #define MICRO_B_COM_IRAM_CONTROL1_RESERVED0_SHIFT 10 7015 7016 /* MICRO_B_COM :: IRAM_CONTROL1 :: micro_iram_tm [09:00] */ 7017 #define MICRO_B_COM_IRAM_CONTROL1_MICRO_IRAM_TM_MASK 0x03ff 7018 #define MICRO_B_COM_IRAM_CONTROL1_MICRO_IRAM_TM_ALIGN 0 7019 #define MICRO_B_COM_IRAM_CONTROL1_MICRO_IRAM_TM_BITS 10 7020 #define MICRO_B_COM_IRAM_CONTROL1_MICRO_IRAM_TM_SHIFT 0 7021 7022 7023 /**************************************************************************** 7024 * eagle_tsc_mdio_MDIO_MMDSEL_AER_COM 7025 */ 7026 /**************************************************************************** 7027 * MDIO_MMDSEL_AER_COM :: MDIO_MASKDATA 7028 */ 7029 /* MDIO_MMDSEL_AER_COM :: MDIO_MASKDATA :: mdio_maskdata [15:00] */ 7030 #define MDIO_MMDSEL_AER_COM_MDIO_MASKDATA_MDIO_MASKDATA_MASK 0xffff 7031 #define MDIO_MMDSEL_AER_COM_MDIO_MASKDATA_MDIO_MASKDATA_ALIGN 0 7032 #define MDIO_MMDSEL_AER_COM_MDIO_MASKDATA_MDIO_MASKDATA_BITS 16 7033 #define MDIO_MMDSEL_AER_COM_MDIO_MASKDATA_MDIO_MASKDATA_SHIFT 0 7034 7035 7036 /**************************************************************************** 7037 * MDIO_MMDSEL_AER_COM :: MDIO_BRCST_PORT_ADDR 7038 */ 7039 /* MDIO_MMDSEL_AER_COM :: MDIO_BRCST_PORT_ADDR :: reserved0 [15:05] */ 7040 #define MDIO_MMDSEL_AER_COM_MDIO_BRCST_PORT_ADDR_RESERVED0_MASK 0xffe0 7041 #define MDIO_MMDSEL_AER_COM_MDIO_BRCST_PORT_ADDR_RESERVED0_ALIGN 0 7042 #define MDIO_MMDSEL_AER_COM_MDIO_BRCST_PORT_ADDR_RESERVED0_BITS 11 7043 #define MDIO_MMDSEL_AER_COM_MDIO_BRCST_PORT_ADDR_RESERVED0_SHIFT 5 7044 7045 /* MDIO_MMDSEL_AER_COM :: MDIO_BRCST_PORT_ADDR :: mdio_brcst_port_addr [04:00] */ 7046 #define MDIO_MMDSEL_AER_COM_MDIO_BRCST_PORT_ADDR_MDIO_BRCST_PORT_ADDR_MASK 0x001f 7047 #define MDIO_MMDSEL_AER_COM_MDIO_BRCST_PORT_ADDR_MDIO_BRCST_PORT_ADDR_ALIGN 0 7048 #define MDIO_MMDSEL_AER_COM_MDIO_BRCST_PORT_ADDR_MDIO_BRCST_PORT_ADDR_BITS 5 7049 #define MDIO_MMDSEL_AER_COM_MDIO_BRCST_PORT_ADDR_MDIO_BRCST_PORT_ADDR_SHIFT 0 7050 7051 7052 /**************************************************************************** 7053 * MDIO_MMDSEL_AER_COM :: MDIO_MMD_SELECT 7054 */ 7055 /* MDIO_MMDSEL_AER_COM :: MDIO_MMD_SELECT :: mdio_multi_prts_en [15:15] */ 7056 #define MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT_MDIO_MULTI_PRTS_EN_MASK 0x8000 7057 #define MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT_MDIO_MULTI_PRTS_EN_ALIGN 0 7058 #define MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT_MDIO_MULTI_PRTS_EN_BITS 1 7059 #define MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT_MDIO_MULTI_PRTS_EN_SHIFT 15 7060 7061 /* MDIO_MMDSEL_AER_COM :: MDIO_MMD_SELECT :: mdio_multi_mmds_en [14:14] */ 7062 #define MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT_MDIO_MULTI_MMDS_EN_MASK 0x4000 7063 #define MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT_MDIO_MULTI_MMDS_EN_ALIGN 0 7064 #define MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT_MDIO_MULTI_MMDS_EN_BITS 1 7065 #define MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT_MDIO_MULTI_MMDS_EN_SHIFT 14 7066 7067 /* MDIO_MMDSEL_AER_COM :: MDIO_MMD_SELECT :: reserved0 [13:07] */ 7068 #define MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT_RESERVED0_MASK 0x3f80 7069 #define MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT_RESERVED0_ALIGN 0 7070 #define MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT_RESERVED0_BITS 7 7071 #define MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT_RESERVED0_SHIFT 7 7072 7073 /* MDIO_MMDSEL_AER_COM :: MDIO_MMD_SELECT :: mdio_dev_pcs_en [06:06] */ 7074 #define MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT_MDIO_DEV_PCS_EN_MASK 0x0040 7075 #define MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT_MDIO_DEV_PCS_EN_ALIGN 0 7076 #define MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT_MDIO_DEV_PCS_EN_BITS 1 7077 #define MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT_MDIO_DEV_PCS_EN_SHIFT 6 7078 7079 /* MDIO_MMDSEL_AER_COM :: MDIO_MMD_SELECT :: mdio_dev_dte_en [05:05] */ 7080 #define MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT_MDIO_DEV_DTE_EN_MASK 0x0020 7081 #define MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT_MDIO_DEV_DTE_EN_ALIGN 0 7082 #define MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT_MDIO_DEV_DTE_EN_BITS 1 7083 #define MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT_MDIO_DEV_DTE_EN_SHIFT 5 7084 7085 /* MDIO_MMDSEL_AER_COM :: MDIO_MMD_SELECT :: mdio_dev_phy_en [04:04] */ 7086 #define MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT_MDIO_DEV_PHY_EN_MASK 0x0010 7087 #define MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT_MDIO_DEV_PHY_EN_ALIGN 0 7088 #define MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT_MDIO_DEV_PHY_EN_BITS 1 7089 #define MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT_MDIO_DEV_PHY_EN_SHIFT 4 7090 7091 /* MDIO_MMDSEL_AER_COM :: MDIO_MMD_SELECT :: mdio_dev_an_en [03:03] */ 7092 #define MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT_MDIO_DEV_AN_EN_MASK 0x0008 7093 #define MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT_MDIO_DEV_AN_EN_ALIGN 0 7094 #define MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT_MDIO_DEV_AN_EN_BITS 1 7095 #define MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT_MDIO_DEV_AN_EN_SHIFT 3 7096 7097 /* MDIO_MMDSEL_AER_COM :: MDIO_MMD_SELECT :: mdio_dev_pmd_en [02:02] */ 7098 #define MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT_MDIO_DEV_PMD_EN_MASK 0x0004 7099 #define MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT_MDIO_DEV_PMD_EN_ALIGN 0 7100 #define MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT_MDIO_DEV_PMD_EN_BITS 1 7101 #define MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT_MDIO_DEV_PMD_EN_SHIFT 2 7102 7103 /* MDIO_MMDSEL_AER_COM :: MDIO_MMD_SELECT :: reserved1 [01:01] */ 7104 #define MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT_RESERVED1_MASK 0x0002 7105 #define MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT_RESERVED1_ALIGN 0 7106 #define MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT_RESERVED1_BITS 1 7107 #define MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT_RESERVED1_SHIFT 1 7108 7109 /* MDIO_MMDSEL_AER_COM :: MDIO_MMD_SELECT :: mdio_dev_cl22_en [00:00] */ 7110 #define MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT_MDIO_DEV_CL22_EN_MASK 0x0001 7111 #define MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT_MDIO_DEV_CL22_EN_ALIGN 0 7112 #define MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT_MDIO_DEV_CL22_EN_BITS 1 7113 #define MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT_MDIO_DEV_CL22_EN_SHIFT 0 7114 7115 7116 /**************************************************************************** 7117 * MDIO_MMDSEL_AER_COM :: MDIO_AER 7118 */ 7119 /* MDIO_MMDSEL_AER_COM :: MDIO_AER :: mdio_aer [15:00] */ 7120 #define MDIO_MMDSEL_AER_COM_MDIO_AER_MDIO_AER_MASK 0xffff 7121 #define MDIO_MMDSEL_AER_COM_MDIO_AER_MDIO_AER_ALIGN 0 7122 #define MDIO_MMDSEL_AER_COM_MDIO_AER_MDIO_AER_BITS 16 7123 #define MDIO_MMDSEL_AER_COM_MDIO_AER_MDIO_AER_SHIFT 0 7124 7125 7126 /**************************************************************************** 7127 * eagle_tsc_mdio_MDIO_BLK_ADDR_COM 7128 */ 7129 /**************************************************************************** 7130 * MDIO_BLK_ADDR_COM :: BLK_ADDR 7131 */ 7132 /* MDIO_BLK_ADDR_COM :: BLK_ADDR :: reserved0 [15:15] */ 7133 #define MDIO_BLK_ADDR_COM_BLK_ADDR_RESERVED0_MASK 0x8000 7134 #define MDIO_BLK_ADDR_COM_BLK_ADDR_RESERVED0_ALIGN 0 7135 #define MDIO_BLK_ADDR_COM_BLK_ADDR_RESERVED0_BITS 1 7136 #define MDIO_BLK_ADDR_COM_BLK_ADDR_RESERVED0_SHIFT 15 7137 7138 /* MDIO_BLK_ADDR_COM :: BLK_ADDR :: mdio_blk_addr [14:04] */ 7139 #define MDIO_BLK_ADDR_COM_BLK_ADDR_MDIO_BLK_ADDR_MASK 0x7ff0 7140 #define MDIO_BLK_ADDR_COM_BLK_ADDR_MDIO_BLK_ADDR_ALIGN 0 7141 #define MDIO_BLK_ADDR_COM_BLK_ADDR_MDIO_BLK_ADDR_BITS 11 7142 #define MDIO_BLK_ADDR_COM_BLK_ADDR_MDIO_BLK_ADDR_SHIFT 4 7143 7144 /* MDIO_BLK_ADDR_COM :: BLK_ADDR :: reserved1 [03:00] */ 7145 #define MDIO_BLK_ADDR_COM_BLK_ADDR_RESERVED1_MASK 0x000f 7146 #define MDIO_BLK_ADDR_COM_BLK_ADDR_RESERVED1_ALIGN 0 7147 #define MDIO_BLK_ADDR_COM_BLK_ADDR_RESERVED1_BITS 4 7148 #define MDIO_BLK_ADDR_COM_BLK_ADDR_RESERVED1_SHIFT 0 7149 7150 7151 /**************************************************************************** 7152 * Datatype Definitions. 7153 */ 7154 #endif /* #ifndef TEPMDREGENUMS_TMP__ */ 7155 7156 /* End of File */ 7157