te16PCSRegEnums.h (708857B)
1 /*************************************************************************** 2 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 3 * 4 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 5 * 6 * 7 * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE 8 * AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR 9 * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT. 10 * 11 * $brcm_Workfile: $ 12 * $brcm_Revision: $ 13 * $brcm_Date: $ 14 * 15 * Module Description: 16 * DO NOT EDIT THIS FILE DIRECTLY 17 * 18 * This module was generated magically with RDB from a source description 19 * file. You must edit the source file for changes to be made to this file. 20 * 21 * 22 * Date: Generated on Thu Feb 13 19:01:21 2014 23 * MD5 Checksum 80c9b488d015cbc31e3f4b0aa72c338d 24 * 25 * Compiled with: RDB Utility 5.0 26 * RDB Parser 3.0 27 * rdb2macro.pm 4.0 28 * Perl Interpreter 5.008008 29 * Operating System linux 30 * 31 * Spec Versions: an_x1_control 1 32 * an_x1_timers 1 33 * an_x4_abilities 1 34 * an_x4_hw_lp_pages 1 35 * an_x4_sw_management 1 36 * cl72_user 1 37 * cl82 1 38 * cl82_am 1 39 * cl82_am_tsc_12 1 40 * cl82_shared 1 41 * digital 1 42 * generic 1 43 * ieee0_cl22 1 44 * ilkn_control0 1 45 * ilkn_status0 1 46 * main0 1 47 * mem_dbg 1 48 * mem_ecc 1 49 * misc 1 50 * pmd_x1 1 51 * pmd_x4 1 52 * rx_x1_control0 1 53 * rx_x1_control1 1 54 * rx_x2_control0 1 55 * rx_x2_status0 1 56 * rx_x4_control0 1 57 * rx_x4_control0_tsc_121 58 * rx_x4_status0 1 59 * rx_x4_status0_tsc_12 1 60 * rx_x4_status1 1 61 * sc_x1_control 1 62 * sc_x1_speed_override01 63 * sc_x1_speed_override11 64 * sc_x1_speed_override21 65 * sc_x1_speed_override31 66 * sc_x4_control 1 67 * sc_x4_field_override_enable1 68 * sc_x4_final_config_status1 69 * test1 1 70 * testshared0 1 71 * testshared1 1 72 * tx_x1_control0 1 73 * tx_x1_status0 1 74 * tx_x2_control0 1 75 * tx_x2_status0 1 76 * tx_x4_control0 1 77 * tx_x4_credit_gen0 1 78 * tx_x4_status0 1 79 * 80 * RDB Files: /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/WC4_TSC_ALL.rdb 81 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/ieee0_cl22_regs.rdb 82 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/pmd_x1_regs.rdb 83 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/testshared0_regs.rdb 84 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/testshared1_regs.rdb 85 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/mem_ecc_regs.rdb 86 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/mem_dbg_regs.rdb 87 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/misc_regs.rdb 88 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/enum_inc.rdb 89 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/an_x1_timers_regs.rdb 90 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/cl82_shared_regs.rdb 91 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/cl82_am_regs.rdb 92 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/cl82_am_tsc_12_regs.rdb 93 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/cl82_regs.rdb 94 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/main0_regs.rdb 95 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/enum_inc.rdb 96 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/rx_x1_control0_regs.rdb 97 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/rx_x1_control1_regs.rdb 98 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/tx_x1_control0_regs.rdb 99 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/tx_x1_status0_regs.rdb 100 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/an_x1_control_regs.rdb 101 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/tx_x2_control0_regs.rdb 102 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/tx_x2_status0_regs.rdb 103 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/rx_x2_control0_regs.rdb 104 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/rx_x2_status0_regs.rdb 105 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/gen_per_lane_regs.rdb 106 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/enum_inc.rdb 107 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/pmd_x4_regs.rdb 108 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/test1_regs.rdb 109 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/tx_x4_credit_gen0_regs.rdb 110 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/enum_inc.rdb 111 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/tx_x4_control0_regs.rdb 112 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/tx_x4_status0_regs.rdb 113 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/rx_x4_control0_regs.rdb 114 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/rx_x4_status0_regs.rdb 115 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/rx_x4_status1_regs.rdb 116 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/rx_x4_control0_tsc_12_regs.rdb 117 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/rx_x4_status0_tsc_12_regs.rdb 118 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/an_x4_abilities_regs.rdb 119 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/an_x4_hw_lp_pages_regs.rdb 120 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/an_x4_sw_management_regs.rdb 121 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/enum_inc.rdb 122 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/digital_regs.rdb 123 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/enum_inc.rdb 124 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/cl72_user_regs.rdb 125 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/sc_x1_control_regs.rdb 126 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/sc_x4_control_regs.rdb 127 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/enum_inc.rdb 128 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/sc_x1_speed_override0_regs.rdb 129 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/sc_x1_speed_override_common.rdb 130 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/enum_inc.rdb 131 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/sc_x1_speed_override1_regs.rdb 132 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/sc_x1_speed_override_common.rdb 133 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/enum_inc.rdb 134 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/sc_x1_speed_override2_regs.rdb 135 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/sc_x1_speed_override_common.rdb 136 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/enum_inc.rdb 137 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/sc_x1_speed_override3_regs.rdb 138 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/sc_x1_speed_override_common.rdb 139 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/enum_inc.rdb 140 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/sc_x4_final_config_status_regs.rdb 141 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/sc_x1_speed_override_common.rdb 142 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/enum_inc.rdb 143 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/sc_x4_field_override_enable_regs.rdb 144 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/ilkn_control0_regs.rdb 145 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/ilkn_status0_regs.rdb 146 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/WC4_ieeeBlockCL22.rdb 147 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/WC4_userBlocks1.rdb 148 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/WC4_userBlocks2.rdb 149 * /projects/TSC_ext6/udayc/EA_Mar_26/tsce/rtl/rdb/WC4_userBlocks4.rdb 150 * 151 * Revision History: 152 * 153 * $brcm_Log: $ 154 */ 155 156 #ifndef TEPCSREGENUMS_TMP__ 157 #define TEPCSREGENUMS_TMP__ 158 159 /** 160 * m = memory, c = core, r = register, f = field, d = data. 161 */ 162 #if !defined(GET_FIELD) && !defined(SET_FIELD) 163 #define BRCM_ALIGN(c,r,f) c##_##r##_##f##_ALIGN 164 #define BRCM_BITS(c,r,f) c##_##r##_##f##_BITS 165 #define BRCM_MASK(c,r,f) c##_##r##_##f##_MASK 166 #define BRCM_SHIFT(c,r,f) c##_##r##_##f##_SHIFT 167 168 #define GET_FIELD(m,c,r,f) \ 169 ((((m) & BRCM_MASK(c,r,f)) >> BRCM_SHIFT(c,r,f)) << BRCM_ALIGN(c,r,f)) 170 171 #define SET_FIELD(m,c,r,f,d) \ 172 ((m) = (((m) & ~BRCM_MASK(c,r,f)) | ((((d) >> BRCM_ALIGN(c,r,f)) << \ 173 BRCM_SHIFT(c,r,f)) & BRCM_MASK(c,r,f))) \ 174 ) 175 176 #define SET_TYPE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##d) 177 #define SET_NAME_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##r##_##f##_##d) 178 #define SET_VALUE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,d) 179 180 #endif /* GET & SET */ 181 182 /**************************************************************************** 183 * Core Enums. 184 */ 185 /**************************************************************************** 186 * Enums: an_x4_sw_management_cl36TxEEEStates_l 187 */ 188 #define an_x4_sw_management_cl36TxEEEStates_l_TX_REFRESH 8 189 #define an_x4_sw_management_cl36TxEEEStates_l_TX_QUIET 4 190 #define an_x4_sw_management_cl36TxEEEStates_l_TX_SLEEP 2 191 #define an_x4_sw_management_cl36TxEEEStates_l_TX_ACTIVE 1 192 193 /**************************************************************************** 194 * Enums: an_x4_sw_management_cl36TxEEEStates_c 195 */ 196 #define an_x4_sw_management_cl36TxEEEStates_c_TX_REFRESH 3 197 #define an_x4_sw_management_cl36TxEEEStates_c_TX_QUIET 2 198 #define an_x4_sw_management_cl36TxEEEStates_c_TX_SLEEP 1 199 #define an_x4_sw_management_cl36TxEEEStates_c_TX_ACTIVE 0 200 201 /**************************************************************************** 202 * Enums: an_x4_sw_management_cl49TxEEEStates_l 203 */ 204 #define an_x4_sw_management_cl49TxEEEStates_l_SCR_RESET_2 64 205 #define an_x4_sw_management_cl49TxEEEStates_l_SCR_RESET_1 32 206 #define an_x4_sw_management_cl49TxEEEStates_l_TX_WAKE 16 207 #define an_x4_sw_management_cl49TxEEEStates_l_TX_REFRESH 8 208 #define an_x4_sw_management_cl49TxEEEStates_l_TX_QUIET 4 209 #define an_x4_sw_management_cl49TxEEEStates_l_TX_SLEEP 2 210 #define an_x4_sw_management_cl49TxEEEStates_l_TX_ACTIVE 1 211 212 /**************************************************************************** 213 * Enums: an_x4_sw_management_cl49TxEEEStates_c 214 */ 215 #define an_x4_sw_management_cl49TxEEEStates_c_SCR_RESET_2 6 216 #define an_x4_sw_management_cl49TxEEEStates_c_SCR_RESET_1 5 217 #define an_x4_sw_management_cl49TxEEEStates_c_TX_WAKE 4 218 #define an_x4_sw_management_cl49TxEEEStates_c_TX_REFRESH 3 219 #define an_x4_sw_management_cl49TxEEEStates_c_TX_QUIET 2 220 #define an_x4_sw_management_cl49TxEEEStates_c_TX_SLEEP 1 221 #define an_x4_sw_management_cl49TxEEEStates_c_TX_ACTIVE 0 222 223 /**************************************************************************** 224 * Enums: an_x4_sw_management_cl36RxEEEStates_l 225 */ 226 #define an_x4_sw_management_cl36RxEEEStates_l_RX_LINK_FAIL 32 227 #define an_x4_sw_management_cl36RxEEEStates_l_RX_WTF 16 228 #define an_x4_sw_management_cl36RxEEEStates_l_RX_WAKE 8 229 #define an_x4_sw_management_cl36RxEEEStates_l_RX_QUIET 4 230 #define an_x4_sw_management_cl36RxEEEStates_l_RX_SLEEP 2 231 #define an_x4_sw_management_cl36RxEEEStates_l_RX_ACTIVE 1 232 233 /**************************************************************************** 234 * Enums: an_x4_sw_management_cl36RxEEEStates_c 235 */ 236 #define an_x4_sw_management_cl36RxEEEStates_c_RX_LINK_FAIL 5 237 #define an_x4_sw_management_cl36RxEEEStates_c_RX_WTF 4 238 #define an_x4_sw_management_cl36RxEEEStates_c_RX_WAKE 3 239 #define an_x4_sw_management_cl36RxEEEStates_c_RX_QUIET 2 240 #define an_x4_sw_management_cl36RxEEEStates_c_RX_SLEEP 1 241 #define an_x4_sw_management_cl36RxEEEStates_c_RX_ACTIVE 0 242 243 /**************************************************************************** 244 * Enums: an_x4_sw_management_cl49RxEEEStates_l 245 */ 246 #define an_x4_sw_management_cl49RxEEEStates_l_RX_LINK_FAIL 32 247 #define an_x4_sw_management_cl49RxEEEStates_l_RX_WTF 16 248 #define an_x4_sw_management_cl49RxEEEStates_l_RX_WAKE 8 249 #define an_x4_sw_management_cl49RxEEEStates_l_RX_QUIET 4 250 #define an_x4_sw_management_cl49RxEEEStates_l_RX_SLEEP 2 251 #define an_x4_sw_management_cl49RxEEEStates_l_RX_ACTIVE 1 252 253 /**************************************************************************** 254 * Enums: an_x4_sw_management_cl49RxEEEStates_c 255 */ 256 #define an_x4_sw_management_cl49RxEEEStates_c_RX_LINK_FAIL 5 257 #define an_x4_sw_management_cl49RxEEEStates_c_RX_WTF 4 258 #define an_x4_sw_management_cl49RxEEEStates_c_RX_WAKE 3 259 #define an_x4_sw_management_cl49RxEEEStates_c_RX_QUIET 2 260 #define an_x4_sw_management_cl49RxEEEStates_c_RX_SLEEP 1 261 #define an_x4_sw_management_cl49RxEEEStates_c_RX_ACTIVE 0 262 263 /**************************************************************************** 264 * Enums: an_x4_sw_management_cl48TxEEEStates_l 265 */ 266 #define an_x4_sw_management_cl48TxEEEStates_l_TX_REFRESH 8 267 #define an_x4_sw_management_cl48TxEEEStates_l_TX_QUIET 4 268 #define an_x4_sw_management_cl48TxEEEStates_l_TX_SLEEP 2 269 #define an_x4_sw_management_cl48TxEEEStates_l_TX_ACTIVE 1 270 271 /**************************************************************************** 272 * Enums: an_x4_sw_management_cl48TxEEEStates_c 273 */ 274 #define an_x4_sw_management_cl48TxEEEStates_c_TX_REFRESH 3 275 #define an_x4_sw_management_cl48TxEEEStates_c_TX_QUIET 2 276 #define an_x4_sw_management_cl48TxEEEStates_c_TX_SLEEP 1 277 #define an_x4_sw_management_cl48TxEEEStates_c_TX_ACTIVE 0 278 279 /**************************************************************************** 280 * Enums: an_x4_sw_management_cl48RxEEEStates_l 281 */ 282 #define an_x4_sw_management_cl48RxEEEStates_l_RX_LINK_FAIL 32 283 #define an_x4_sw_management_cl48RxEEEStates_l_RX_WAKE 16 284 #define an_x4_sw_management_cl48RxEEEStates_l_RX_QUIET 8 285 #define an_x4_sw_management_cl48RxEEEStates_l_RX_DEACT 4 286 #define an_x4_sw_management_cl48RxEEEStates_l_RX_SLEEP 2 287 #define an_x4_sw_management_cl48RxEEEStates_l_RX_ACTIVE 1 288 289 /**************************************************************************** 290 * Enums: an_x4_sw_management_cl48RxEEEStates_c 291 */ 292 #define an_x4_sw_management_cl48RxEEEStates_c_RX_LINK_FAIL 5 293 #define an_x4_sw_management_cl48RxEEEStates_c_RX_WAKE 4 294 #define an_x4_sw_management_cl48RxEEEStates_c_RX_QUIET 3 295 #define an_x4_sw_management_cl48RxEEEStates_c_RX_DEACT 2 296 #define an_x4_sw_management_cl48RxEEEStates_c_RX_SLEEP 1 297 #define an_x4_sw_management_cl48RxEEEStates_c_RX_ACTIVE 0 298 299 /**************************************************************************** 300 * Enums: an_x4_sw_management_IQP_Options 301 */ 302 #define an_x4_sw_management_IQP_Options_i50uA 0 303 #define an_x4_sw_management_IQP_Options_i100uA 1 304 #define an_x4_sw_management_IQP_Options_i150uA 2 305 #define an_x4_sw_management_IQP_Options_i200uA 3 306 #define an_x4_sw_management_IQP_Options_i250uA 4 307 #define an_x4_sw_management_IQP_Options_i300uA 5 308 #define an_x4_sw_management_IQP_Options_i350uA 6 309 #define an_x4_sw_management_IQP_Options_i400uA 7 310 #define an_x4_sw_management_IQP_Options_i450uA 8 311 #define an_x4_sw_management_IQP_Options_i500uA 9 312 #define an_x4_sw_management_IQP_Options_i550uA 10 313 #define an_x4_sw_management_IQP_Options_i600uA 11 314 #define an_x4_sw_management_IQP_Options_i650uA 12 315 #define an_x4_sw_management_IQP_Options_i700uA 13 316 #define an_x4_sw_management_IQP_Options_i750uA 14 317 #define an_x4_sw_management_IQP_Options_i800uA 15 318 319 /**************************************************************************** 320 * Enums: an_x4_sw_management_IDriver_Options 321 */ 322 #define an_x4_sw_management_IDriver_Options_v680mV 0 323 #define an_x4_sw_management_IDriver_Options_v730mV 1 324 #define an_x4_sw_management_IDriver_Options_v780mV 2 325 #define an_x4_sw_management_IDriver_Options_v830mV 3 326 #define an_x4_sw_management_IDriver_Options_v880mV 4 327 #define an_x4_sw_management_IDriver_Options_v930mV 5 328 #define an_x4_sw_management_IDriver_Options_v980mV 6 329 #define an_x4_sw_management_IDriver_Options_v1010mV 7 330 #define an_x4_sw_management_IDriver_Options_v1040mV 8 331 #define an_x4_sw_management_IDriver_Options_v1060mV 9 332 #define an_x4_sw_management_IDriver_Options_v1070mV 10 333 #define an_x4_sw_management_IDriver_Options_v1080mV 11 334 #define an_x4_sw_management_IDriver_Options_v1085mV 12 335 #define an_x4_sw_management_IDriver_Options_v1090mV 13 336 #define an_x4_sw_management_IDriver_Options_v1095mV 14 337 #define an_x4_sw_management_IDriver_Options_v1100mV 15 338 339 /**************************************************************************** 340 * Enums: an_x4_sw_management_operationModes 341 */ 342 #define an_x4_sw_management_operationModes_XGXS 0 343 #define an_x4_sw_management_operationModes_XGXG_nCC 1 344 #define an_x4_sw_management_operationModes_Indlane_OS8 4 345 #define an_x4_sw_management_operationModes_IndLane_OS5 5 346 #define an_x4_sw_management_operationModes_PCI 7 347 #define an_x4_sw_management_operationModes_XGXS_nLQ 8 348 #define an_x4_sw_management_operationModes_XGXS_nLQnCC 9 349 #define an_x4_sw_management_operationModes_PBypass 10 350 #define an_x4_sw_management_operationModes_PBypass_nDSK 11 351 #define an_x4_sw_management_operationModes_ComboCoreMode 12 352 #define an_x4_sw_management_operationModes_Clocks_off 15 353 354 /**************************************************************************** 355 * Enums: an_x4_sw_management_synce_enum 356 */ 357 #define an_x4_sw_management_synce_enum_SYNCE_NO_DIV 0 358 #define an_x4_sw_management_synce_enum_SYNCE_DIV_7 1 359 #define an_x4_sw_management_synce_enum_SYNCE_DIV_11 2 360 361 /**************************************************************************** 362 * Enums: an_x4_sw_management_operationSpeeds 363 */ 364 #define an_x4_sw_management_operationSpeeds_SPEED_2p5G_X1_10p3125 56 365 #define an_x4_sw_management_operationSpeeds_SPEED_1000M_10p3125 55 366 #define an_x4_sw_management_operationSpeeds_SPEED_100M_10p3125 54 367 #define an_x4_sw_management_operationSpeeds_SPEED_10M_10p3125 53 368 #define an_x4_sw_management_operationSpeeds_SPEED_10p5G_X4 50 369 #define an_x4_sw_management_operationSpeeds_SPEED_5G_KR1 49 370 #define an_x4_sw_management_operationSpeeds_SPEED_127G_X12 39 371 #define an_x4_sw_management_operationSpeeds_SPEED_120G_X12 38 372 #define an_x4_sw_management_operationSpeeds_SPEED_107G_X10 37 373 #define an_x4_sw_management_operationSpeeds_SPEED_100G_CR10 36 374 #define an_x4_sw_management_operationSpeeds_SPEED_42G_X4 35 375 #define an_x4_sw_management_operationSpeeds_SPEED_40G_CR4 34 376 #define an_x4_sw_management_operationSpeeds_SPEED_40G_KR4 33 377 #define an_x4_sw_management_operationSpeeds_SPEED_21G_X2 32 378 #define an_x4_sw_management_operationSpeeds_SPEED_20G_CR2 31 379 #define an_x4_sw_management_operationSpeeds_SPEED_20G_KR2 30 380 #define an_x4_sw_management_operationSpeeds_SPEED_10p6_X1 29 381 #define an_x4_sw_management_operationSpeeds_SPEED_10G_KR1 28 382 #define an_x4_sw_management_operationSpeeds_SPEED_40G_X4 27 383 #define an_x4_sw_management_operationSpeeds_SPEED_20G_X2 26 384 #define an_x4_sw_management_operationSpeeds_SPEED_20G_CX2 25 385 #define an_x4_sw_management_operationSpeeds_SPEED_31p5G_KR4 24 386 #define an_x4_sw_management_operationSpeeds_SPEED_31p5G_X4 23 387 #define an_x4_sw_management_operationSpeeds_SPEED_15p75G_X2 22 388 #define an_x4_sw_management_operationSpeeds_SPEED_25p45G_X4 21 389 #define an_x4_sw_management_operationSpeeds_SPEED_12p7G_X2 20 390 #define an_x4_sw_management_operationSpeeds_SPEED_21G_X4 19 391 #define an_x4_sw_management_operationSpeeds_SPEED_10p5G_X2 18 392 #define an_x4_sw_management_operationSpeeds_SPEED_20G_X4 17 393 #define an_x4_sw_management_operationSpeeds_SPEED_10G_X2 16 394 #define an_x4_sw_management_operationSpeeds_SPEED_10G_CX2 15 395 #define an_x4_sw_management_operationSpeeds_SPEED_20G_CX4 14 396 #define an_x4_sw_management_operationSpeeds_SPEED_16G_X4 13 397 #define an_x4_sw_management_operationSpeeds_SPEED_15G_X4 12 398 #define an_x4_sw_management_operationSpeeds_SPEED_13G_X4 11 399 #define an_x4_sw_management_operationSpeeds_SPEED_10G_X4 10 400 #define an_x4_sw_management_operationSpeeds_SPEED_10G_KX4 9 401 #define an_x4_sw_management_operationSpeeds_SPEED_10G_CX4 8 402 #define an_x4_sw_management_operationSpeeds_SPEED_5G_X1 7 403 #define an_x4_sw_management_operationSpeeds_SPEED_2p5G_X1 6 404 #define an_x4_sw_management_operationSpeeds_SPEED_1G_KX1 5 405 #define an_x4_sw_management_operationSpeeds_SPEED_1G_CX1 4 406 #define an_x4_sw_management_operationSpeeds_SPEED_1000M 3 407 #define an_x4_sw_management_operationSpeeds_SPEED_100M 2 408 #define an_x4_sw_management_operationSpeeds_SPEED_10M 1 409 410 /**************************************************************************** 411 * Enums: an_x4_sw_management_actualSpeeds 412 */ 413 #define an_x4_sw_management_actualSpeeds_dr_10M 0 414 #define an_x4_sw_management_actualSpeeds_dr_100M 1 415 #define an_x4_sw_management_actualSpeeds_dr_1G 2 416 #define an_x4_sw_management_actualSpeeds_dr_2p5G 3 417 #define an_x4_sw_management_actualSpeeds_dr_5G_X4 4 418 #define an_x4_sw_management_actualSpeeds_dr_6G_X4 5 419 #define an_x4_sw_management_actualSpeeds_dr_10G_HiG 6 420 #define an_x4_sw_management_actualSpeeds_dr_10G_CX4 7 421 #define an_x4_sw_management_actualSpeeds_dr_12G_HiG 8 422 #define an_x4_sw_management_actualSpeeds_dr_12p5G_X4 9 423 #define an_x4_sw_management_actualSpeeds_dr_13G_X4 10 424 #define an_x4_sw_management_actualSpeeds_dr_15G_X4 11 425 #define an_x4_sw_management_actualSpeeds_dr_16G_X4 12 426 #define an_x4_sw_management_actualSpeeds_dr_1G_KX 13 427 #define an_x4_sw_management_actualSpeeds_dr_10G_KX4 14 428 #define an_x4_sw_management_actualSpeeds_dr_10G_KR 15 429 #define an_x4_sw_management_actualSpeeds_dr_5G 16 430 #define an_x4_sw_management_actualSpeeds_dr_6p4G 17 431 #define an_x4_sw_management_actualSpeeds_dr_20G_X4 18 432 #define an_x4_sw_management_actualSpeeds_dr_21G_X4 19 433 #define an_x4_sw_management_actualSpeeds_dr_25G_X4 20 434 #define an_x4_sw_management_actualSpeeds_dr_10G_HiG_DXGXS 21 435 #define an_x4_sw_management_actualSpeeds_dr_10G_DXGXS 22 436 #define an_x4_sw_management_actualSpeeds_dr_10p5G_HiG_DXGXS 23 437 #define an_x4_sw_management_actualSpeeds_dr_10p5G_DXGXS 24 438 #define an_x4_sw_management_actualSpeeds_dr_12p773G_HiG_DXGXS 25 439 #define an_x4_sw_management_actualSpeeds_dr_12p773G_DXGXS 26 440 #define an_x4_sw_management_actualSpeeds_dr_10G_XFI 27 441 #define an_x4_sw_management_actualSpeeds_dr_40G 28 442 #define an_x4_sw_management_actualSpeeds_dr_20G_HiG_DXGXS 29 443 #define an_x4_sw_management_actualSpeeds_dr_20G_DXGXS 30 444 #define an_x4_sw_management_actualSpeeds_dr_10G_SFI 31 445 #define an_x4_sw_management_actualSpeeds_dr_31p5G 32 446 #define an_x4_sw_management_actualSpeeds_dr_32p7G 33 447 #define an_x4_sw_management_actualSpeeds_dr_20G_SCR 34 448 #define an_x4_sw_management_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 449 #define an_x4_sw_management_actualSpeeds_dr_10G_DXGXS_SCR 36 450 #define an_x4_sw_management_actualSpeeds_dr_12G_R2 37 451 #define an_x4_sw_management_actualSpeeds_dr_10G_X2 38 452 #define an_x4_sw_management_actualSpeeds_dr_40G_KR4 39 453 #define an_x4_sw_management_actualSpeeds_dr_40G_CR4 40 454 #define an_x4_sw_management_actualSpeeds_dr_100G_CR10 41 455 #define an_x4_sw_management_actualSpeeds_dr_15p75G_DXGXS 44 456 #define an_x4_sw_management_actualSpeeds_dr_20G_KR2 57 457 #define an_x4_sw_management_actualSpeeds_dr_20G_CR2 58 458 459 /**************************************************************************** 460 * Enums: an_x4_sw_management_actualSpeedsMisc1 461 */ 462 #define an_x4_sw_management_actualSpeedsMisc1_dr_2500BRCM_X1 16 463 #define an_x4_sw_management_actualSpeedsMisc1_dr_5000BRCM_X4 17 464 #define an_x4_sw_management_actualSpeedsMisc1_dr_6000BRCM_X4 18 465 #define an_x4_sw_management_actualSpeedsMisc1_dr_10GHiGig_X4 19 466 #define an_x4_sw_management_actualSpeedsMisc1_dr_10GBASE_CX4 20 467 #define an_x4_sw_management_actualSpeedsMisc1_dr_12GHiGig_X4 21 468 #define an_x4_sw_management_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 469 #define an_x4_sw_management_actualSpeedsMisc1_dr_13GHiGig_X4 23 470 #define an_x4_sw_management_actualSpeedsMisc1_dr_15GHiGig_X4 24 471 #define an_x4_sw_management_actualSpeedsMisc1_dr_16GHiGig_X4 25 472 #define an_x4_sw_management_actualSpeedsMisc1_dr_5000BRCM_X1 26 473 #define an_x4_sw_management_actualSpeedsMisc1_dr_6363BRCM_X1 27 474 #define an_x4_sw_management_actualSpeedsMisc1_dr_20GHiGig_X4 28 475 #define an_x4_sw_management_actualSpeedsMisc1_dr_21GHiGig_X4 29 476 #define an_x4_sw_management_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 477 #define an_x4_sw_management_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 478 479 /**************************************************************************** 480 * Enums: an_x4_sw_management_IndLaneModes 481 */ 482 #define an_x4_sw_management_IndLaneModes_SWSDR_div2 0 483 #define an_x4_sw_management_IndLaneModes_SWSDR_div1 1 484 #define an_x4_sw_management_IndLaneModes_DWSDR_div2 2 485 #define an_x4_sw_management_IndLaneModes_DWSDR_div1 3 486 487 /**************************************************************************** 488 * Enums: an_x4_sw_management_prbsSelect 489 */ 490 #define an_x4_sw_management_prbsSelect_prbs7 0 491 #define an_x4_sw_management_prbsSelect_prbs15 1 492 #define an_x4_sw_management_prbsSelect_prbs23 2 493 #define an_x4_sw_management_prbsSelect_prbs31 3 494 495 /**************************************************************************** 496 * Enums: an_x4_sw_management_vcoDivider 497 */ 498 #define an_x4_sw_management_vcoDivider_div32 0 499 #define an_x4_sw_management_vcoDivider_div36 1 500 #define an_x4_sw_management_vcoDivider_div40 2 501 #define an_x4_sw_management_vcoDivider_div42 3 502 #define an_x4_sw_management_vcoDivider_div48 4 503 #define an_x4_sw_management_vcoDivider_div50 5 504 #define an_x4_sw_management_vcoDivider_div52 6 505 #define an_x4_sw_management_vcoDivider_div54 7 506 #define an_x4_sw_management_vcoDivider_div60 8 507 #define an_x4_sw_management_vcoDivider_div64 9 508 #define an_x4_sw_management_vcoDivider_div66 10 509 #define an_x4_sw_management_vcoDivider_div68 11 510 #define an_x4_sw_management_vcoDivider_div70 12 511 #define an_x4_sw_management_vcoDivider_div80 13 512 #define an_x4_sw_management_vcoDivider_div92 14 513 #define an_x4_sw_management_vcoDivider_div100 15 514 515 /**************************************************************************** 516 * Enums: an_x4_sw_management_refClkSelect 517 */ 518 #define an_x4_sw_management_refClkSelect_clk_25MHz 0 519 #define an_x4_sw_management_refClkSelect_clk_100MHz 1 520 #define an_x4_sw_management_refClkSelect_clk_125MHz 2 521 #define an_x4_sw_management_refClkSelect_clk_156p25MHz 3 522 #define an_x4_sw_management_refClkSelect_clk_187p5MHz 4 523 #define an_x4_sw_management_refClkSelect_clk_161p25Mhz 5 524 #define an_x4_sw_management_refClkSelect_clk_50Mhz 6 525 #define an_x4_sw_management_refClkSelect_clk_106p25Mhz 7 526 527 /**************************************************************************** 528 * Enums: an_x4_sw_management_aerMMDdevTypeSelect 529 */ 530 #define an_x4_sw_management_aerMMDdevTypeSelect_combo_core 0 531 #define an_x4_sw_management_aerMMDdevTypeSelect_PMA_PMD 1 532 #define an_x4_sw_management_aerMMDdevTypeSelect_PCS 3 533 #define an_x4_sw_management_aerMMDdevTypeSelect_PHY 4 534 #define an_x4_sw_management_aerMMDdevTypeSelect_DTE 5 535 #define an_x4_sw_management_aerMMDdevTypeSelect_CL73_AN 7 536 537 /**************************************************************************** 538 * Enums: an_x4_sw_management_aerMMDportSelect 539 */ 540 #define an_x4_sw_management_aerMMDportSelect_ln0 0 541 #define an_x4_sw_management_aerMMDportSelect_ln1 1 542 #define an_x4_sw_management_aerMMDportSelect_ln2 2 543 #define an_x4_sw_management_aerMMDportSelect_ln3 3 544 #define an_x4_sw_management_aerMMDportSelect_BCST_ln0_1_2_3 511 545 #define an_x4_sw_management_aerMMDportSelect_BCST_ln0_1 512 546 #define an_x4_sw_management_aerMMDportSelect_BCST_ln2_3 513 547 548 /**************************************************************************** 549 * Enums: an_x4_sw_management_firmwareModeSelect 550 */ 551 #define an_x4_sw_management_firmwareModeSelect_DEFAULT 0 552 #define an_x4_sw_management_firmwareModeSelect_SFP_OPT_LR 1 553 #define an_x4_sw_management_firmwareModeSelect_SFP_DAC 2 554 #define an_x4_sw_management_firmwareModeSelect_XLAUI 3 555 #define an_x4_sw_management_firmwareModeSelect_LONG_CH_6G 4 556 557 /**************************************************************************** 558 * Enums: an_x4_sw_management_tempIdxSelect 559 */ 560 #define an_x4_sw_management_tempIdxSelect_LTE__22p9C 15 561 #define an_x4_sw_management_tempIdxSelect_LTE__12p6C 14 562 #define an_x4_sw_management_tempIdxSelect_LTE__3p0C 13 563 #define an_x4_sw_management_tempIdxSelect_LTE_6p7C 12 564 #define an_x4_sw_management_tempIdxSelect_LTE_16p4C 11 565 #define an_x4_sw_management_tempIdxSelect_LTE_26p6C 10 566 #define an_x4_sw_management_tempIdxSelect_LTE_36p3C 9 567 #define an_x4_sw_management_tempIdxSelect_LTE_46p0C 8 568 #define an_x4_sw_management_tempIdxSelect_LTE_56p2C 7 569 #define an_x4_sw_management_tempIdxSelect_LTE_65p9C 6 570 #define an_x4_sw_management_tempIdxSelect_LTE_75p6C 5 571 #define an_x4_sw_management_tempIdxSelect_LTE_85p3C 4 572 #define an_x4_sw_management_tempIdxSelect_LTE_95p5C 3 573 #define an_x4_sw_management_tempIdxSelect_LTE_105p2C 2 574 #define an_x4_sw_management_tempIdxSelect_LTE_114p9C 1 575 #define an_x4_sw_management_tempIdxSelect_LTE_125p1C 0 576 577 /**************************************************************************** 578 * Enums: an_x4_sw_management_tla_ln_seq_status 579 */ 580 #define an_x4_sw_management_tla_ln_seq_status_INIT 1 581 #define an_x4_sw_management_tla_ln_seq_status_SET_AN_SPEED 2 582 #define an_x4_sw_management_tla_ln_seq_status_WAIT_AN_SPEED 4 583 #define an_x4_sw_management_tla_ln_seq_status_WAIT_AN_DONE 8 584 #define an_x4_sw_management_tla_ln_seq_status_SET_RS_SPEED 16 585 #define an_x4_sw_management_tla_ln_seq_status_WAIT_RS_CL72EN 32 586 #define an_x4_sw_management_tla_ln_seq_status_WAIT_RS_SPEED 64 587 #define an_x4_sw_management_tla_ln_seq_status_AN_IGNORE_LINK 128 588 #define an_x4_sw_management_tla_ln_seq_status_AN_GOOD_CHECK 256 589 #define an_x4_sw_management_tla_ln_seq_status_AN_GOOD 512 590 #define an_x4_sw_management_tla_ln_seq_status_AN_FAIL 1024 591 #define an_x4_sw_management_tla_ln_seq_status_AN_DEAD 2048 592 #define an_x4_sw_management_tla_ln_seq_status_SET_PD_SPEED 4096 593 #define an_x4_sw_management_tla_ln_seq_status_WAIT_PD_SPEED 8192 594 #define an_x4_sw_management_tla_ln_seq_status_PD_IGNORE_LINK 16384 595 #define an_x4_sw_management_tla_ln_seq_status_PD_GOOD_CHECK 32768 596 597 /**************************************************************************** 598 * Enums: an_x4_sw_management_tla_ln_seq_status1 599 */ 600 #define an_x4_sw_management_tla_ln_seq_status1_SW_SPEED_CHANGE 64 601 #define an_x4_sw_management_tla_ln_seq_status1_RELEASE_SW 32 602 #define an_x4_sw_management_tla_ln_seq_status1_RELEASE_DISABLE 16 603 #define an_x4_sw_management_tla_ln_seq_status1_PD_WAIT_LINK 8 604 #define an_x4_sw_management_tla_ln_seq_status1_PD_START_CL37_AN 4 605 #define an_x4_sw_management_tla_ln_seq_status1_PD_WAIT_CL37_AN_DONE 2 606 #define an_x4_sw_management_tla_ln_seq_status1_PD_DONE_CL37 1 607 608 /**************************************************************************** 609 * Enums: digital_cl36TxEEEStates_l 610 */ 611 #define digital_cl36TxEEEStates_l_TX_REFRESH 8 612 #define digital_cl36TxEEEStates_l_TX_QUIET 4 613 #define digital_cl36TxEEEStates_l_TX_SLEEP 2 614 #define digital_cl36TxEEEStates_l_TX_ACTIVE 1 615 616 /**************************************************************************** 617 * Enums: digital_cl36TxEEEStates_c 618 */ 619 #define digital_cl36TxEEEStates_c_TX_REFRESH 3 620 #define digital_cl36TxEEEStates_c_TX_QUIET 2 621 #define digital_cl36TxEEEStates_c_TX_SLEEP 1 622 #define digital_cl36TxEEEStates_c_TX_ACTIVE 0 623 624 /**************************************************************************** 625 * Enums: digital_cl49TxEEEStates_l 626 */ 627 #define digital_cl49TxEEEStates_l_SCR_RESET_2 64 628 #define digital_cl49TxEEEStates_l_SCR_RESET_1 32 629 #define digital_cl49TxEEEStates_l_TX_WAKE 16 630 #define digital_cl49TxEEEStates_l_TX_REFRESH 8 631 #define digital_cl49TxEEEStates_l_TX_QUIET 4 632 #define digital_cl49TxEEEStates_l_TX_SLEEP 2 633 #define digital_cl49TxEEEStates_l_TX_ACTIVE 1 634 635 /**************************************************************************** 636 * Enums: digital_cl49TxEEEStates_c 637 */ 638 #define digital_cl49TxEEEStates_c_SCR_RESET_2 6 639 #define digital_cl49TxEEEStates_c_SCR_RESET_1 5 640 #define digital_cl49TxEEEStates_c_TX_WAKE 4 641 #define digital_cl49TxEEEStates_c_TX_REFRESH 3 642 #define digital_cl49TxEEEStates_c_TX_QUIET 2 643 #define digital_cl49TxEEEStates_c_TX_SLEEP 1 644 #define digital_cl49TxEEEStates_c_TX_ACTIVE 0 645 646 /**************************************************************************** 647 * Enums: digital_cl36RxEEEStates_l 648 */ 649 #define digital_cl36RxEEEStates_l_RX_LINK_FAIL 32 650 #define digital_cl36RxEEEStates_l_RX_WTF 16 651 #define digital_cl36RxEEEStates_l_RX_WAKE 8 652 #define digital_cl36RxEEEStates_l_RX_QUIET 4 653 #define digital_cl36RxEEEStates_l_RX_SLEEP 2 654 #define digital_cl36RxEEEStates_l_RX_ACTIVE 1 655 656 /**************************************************************************** 657 * Enums: digital_cl36RxEEEStates_c 658 */ 659 #define digital_cl36RxEEEStates_c_RX_LINK_FAIL 5 660 #define digital_cl36RxEEEStates_c_RX_WTF 4 661 #define digital_cl36RxEEEStates_c_RX_WAKE 3 662 #define digital_cl36RxEEEStates_c_RX_QUIET 2 663 #define digital_cl36RxEEEStates_c_RX_SLEEP 1 664 #define digital_cl36RxEEEStates_c_RX_ACTIVE 0 665 666 /**************************************************************************** 667 * Enums: digital_cl49RxEEEStates_l 668 */ 669 #define digital_cl49RxEEEStates_l_RX_LINK_FAIL 32 670 #define digital_cl49RxEEEStates_l_RX_WTF 16 671 #define digital_cl49RxEEEStates_l_RX_WAKE 8 672 #define digital_cl49RxEEEStates_l_RX_QUIET 4 673 #define digital_cl49RxEEEStates_l_RX_SLEEP 2 674 #define digital_cl49RxEEEStates_l_RX_ACTIVE 1 675 676 /**************************************************************************** 677 * Enums: digital_cl49RxEEEStates_c 678 */ 679 #define digital_cl49RxEEEStates_c_RX_LINK_FAIL 5 680 #define digital_cl49RxEEEStates_c_RX_WTF 4 681 #define digital_cl49RxEEEStates_c_RX_WAKE 3 682 #define digital_cl49RxEEEStates_c_RX_QUIET 2 683 #define digital_cl49RxEEEStates_c_RX_SLEEP 1 684 #define digital_cl49RxEEEStates_c_RX_ACTIVE 0 685 686 /**************************************************************************** 687 * Enums: digital_cl48TxEEEStates_l 688 */ 689 #define digital_cl48TxEEEStates_l_TX_REFRESH 8 690 #define digital_cl48TxEEEStates_l_TX_QUIET 4 691 #define digital_cl48TxEEEStates_l_TX_SLEEP 2 692 #define digital_cl48TxEEEStates_l_TX_ACTIVE 1 693 694 /**************************************************************************** 695 * Enums: digital_cl48TxEEEStates_c 696 */ 697 #define digital_cl48TxEEEStates_c_TX_REFRESH 3 698 #define digital_cl48TxEEEStates_c_TX_QUIET 2 699 #define digital_cl48TxEEEStates_c_TX_SLEEP 1 700 #define digital_cl48TxEEEStates_c_TX_ACTIVE 0 701 702 /**************************************************************************** 703 * Enums: digital_cl48RxEEEStates_l 704 */ 705 #define digital_cl48RxEEEStates_l_RX_LINK_FAIL 32 706 #define digital_cl48RxEEEStates_l_RX_WAKE 16 707 #define digital_cl48RxEEEStates_l_RX_QUIET 8 708 #define digital_cl48RxEEEStates_l_RX_DEACT 4 709 #define digital_cl48RxEEEStates_l_RX_SLEEP 2 710 #define digital_cl48RxEEEStates_l_RX_ACTIVE 1 711 712 /**************************************************************************** 713 * Enums: digital_cl48RxEEEStates_c 714 */ 715 #define digital_cl48RxEEEStates_c_RX_LINK_FAIL 5 716 #define digital_cl48RxEEEStates_c_RX_WAKE 4 717 #define digital_cl48RxEEEStates_c_RX_QUIET 3 718 #define digital_cl48RxEEEStates_c_RX_DEACT 2 719 #define digital_cl48RxEEEStates_c_RX_SLEEP 1 720 #define digital_cl48RxEEEStates_c_RX_ACTIVE 0 721 722 /**************************************************************************** 723 * Enums: digital_IQP_Options 724 */ 725 #define digital_IQP_Options_i50uA 0 726 #define digital_IQP_Options_i100uA 1 727 #define digital_IQP_Options_i150uA 2 728 #define digital_IQP_Options_i200uA 3 729 #define digital_IQP_Options_i250uA 4 730 #define digital_IQP_Options_i300uA 5 731 #define digital_IQP_Options_i350uA 6 732 #define digital_IQP_Options_i400uA 7 733 #define digital_IQP_Options_i450uA 8 734 #define digital_IQP_Options_i500uA 9 735 #define digital_IQP_Options_i550uA 10 736 #define digital_IQP_Options_i600uA 11 737 #define digital_IQP_Options_i650uA 12 738 #define digital_IQP_Options_i700uA 13 739 #define digital_IQP_Options_i750uA 14 740 #define digital_IQP_Options_i800uA 15 741 742 /**************************************************************************** 743 * Enums: digital_IDriver_Options 744 */ 745 #define digital_IDriver_Options_v680mV 0 746 #define digital_IDriver_Options_v730mV 1 747 #define digital_IDriver_Options_v780mV 2 748 #define digital_IDriver_Options_v830mV 3 749 #define digital_IDriver_Options_v880mV 4 750 #define digital_IDriver_Options_v930mV 5 751 #define digital_IDriver_Options_v980mV 6 752 #define digital_IDriver_Options_v1010mV 7 753 #define digital_IDriver_Options_v1040mV 8 754 #define digital_IDriver_Options_v1060mV 9 755 #define digital_IDriver_Options_v1070mV 10 756 #define digital_IDriver_Options_v1080mV 11 757 #define digital_IDriver_Options_v1085mV 12 758 #define digital_IDriver_Options_v1090mV 13 759 #define digital_IDriver_Options_v1095mV 14 760 #define digital_IDriver_Options_v1100mV 15 761 762 /**************************************************************************** 763 * Enums: digital_operationModes 764 */ 765 #define digital_operationModes_XGXS 0 766 #define digital_operationModes_XGXG_nCC 1 767 #define digital_operationModes_Indlane_OS8 4 768 #define digital_operationModes_IndLane_OS5 5 769 #define digital_operationModes_PCI 7 770 #define digital_operationModes_XGXS_nLQ 8 771 #define digital_operationModes_XGXS_nLQnCC 9 772 #define digital_operationModes_PBypass 10 773 #define digital_operationModes_PBypass_nDSK 11 774 #define digital_operationModes_ComboCoreMode 12 775 #define digital_operationModes_Clocks_off 15 776 777 /**************************************************************************** 778 * Enums: digital_synce_enum 779 */ 780 #define digital_synce_enum_SYNCE_NO_DIV 0 781 #define digital_synce_enum_SYNCE_DIV_7 1 782 #define digital_synce_enum_SYNCE_DIV_11 2 783 784 /**************************************************************************** 785 * Enums: digital_operationSpeeds 786 */ 787 #define digital_operationSpeeds_SPEED_10G_X4_10p3 59 788 #define digital_operationSpeeds_SPEED_10G_CX4_10p3 58 789 #define digital_operationSpeeds_SPEED_10G_KX4_10p3 57 790 #define digital_operationSpeeds_SPEED_2p5G_X1_10p3125 56 791 #define digital_operationSpeeds_SPEED_1000M_10p3125 55 792 #define digital_operationSpeeds_SPEED_100M_10p3125 54 793 #define digital_operationSpeeds_SPEED_10M_10p3125 53 794 #define digital_operationSpeeds_SPEED_10p5G_X4 50 795 #define digital_operationSpeeds_SPEED_5G_KR1 49 796 #define digital_operationSpeeds_SPEED_48p48G_MLD 42 797 #define digital_operationSpeeds_SPEED_24p24G_MLD 41 798 #define digital_operationSpeeds_SPEED_12p12G_KR1 40 799 #define digital_operationSpeeds_SPEED_48p48G_MLD 42 800 #define digital_operationSpeeds_SPEED_127G_X12 39 801 #define digital_operationSpeeds_SPEED_120G_X12 38 802 #define digital_operationSpeeds_SPEED_107G_X10 37 803 #define digital_operationSpeeds_SPEED_100G_CR10 36 804 #define digital_operationSpeeds_SPEED_42G_X4 35 805 #define digital_operationSpeeds_SPEED_40G_CR4 34 806 #define digital_operationSpeeds_SPEED_40G_KR4 33 807 #define digital_operationSpeeds_SPEED_21G_X2 32 808 #define digital_operationSpeeds_SPEED_20G_CR2 31 809 #define digital_operationSpeeds_SPEED_20G_KR2 30 810 #define digital_operationSpeeds_SPEED_10p6_X1 29 811 #define digital_operationSpeeds_SPEED_10G_KR1 28 812 #define digital_operationSpeeds_SPEED_40G_X4 27 813 #define digital_operationSpeeds_SPEED_20G_X2 26 814 #define digital_operationSpeeds_SPEED_20G_CX2 25 815 #define digital_operationSpeeds_SPEED_31p5G_KR4 24 816 #define digital_operationSpeeds_SPEED_31p5G_X4 23 817 #define digital_operationSpeeds_SPEED_15p75G_X2 22 818 #define digital_operationSpeeds_SPEED_25p45G_X4 21 819 #define digital_operationSpeeds_SPEED_12p7G_X2 20 820 #define digital_operationSpeeds_SPEED_21G_X4 19 821 #define digital_operationSpeeds_SPEED_10p5G_X2 18 822 #define digital_operationSpeeds_SPEED_20G_X4 17 823 #define digital_operationSpeeds_SPEED_10G_X2 16 824 #define digital_operationSpeeds_SPEED_10G_CX2 15 825 #define digital_operationSpeeds_SPEED_20G_CX4 14 826 #define digital_operationSpeeds_SPEED_16G_X4 13 827 #define digital_operationSpeeds_SPEED_15G_X4 12 828 #define digital_operationSpeeds_SPEED_13G_X4 11 829 #define digital_operationSpeeds_SPEED_10G_X4 10 830 #define digital_operationSpeeds_SPEED_10G_KX4 9 831 #define digital_operationSpeeds_SPEED_10G_CX4 8 832 #define digital_operationSpeeds_SPEED_5G_X1 7 833 #define digital_operationSpeeds_SPEED_2p5G_X1 6 834 #define digital_operationSpeeds_SPEED_1G_KX1 5 835 #define digital_operationSpeeds_SPEED_1G_CX1 4 836 #define digital_operationSpeeds_SPEED_1000M 3 837 #define digital_operationSpeeds_SPEED_100M 2 838 #define digital_operationSpeeds_SPEED_10M 1 839 840 /**************************************************************************** 841 * Enums: digital_actualSpeeds 842 */ 843 #define digital_actualSpeeds_dr_10M 0 844 #define digital_actualSpeeds_dr_100M 1 845 #define digital_actualSpeeds_dr_1G 2 846 #define digital_actualSpeeds_dr_2p5G 3 847 #define digital_actualSpeeds_dr_5G_X4 4 848 #define digital_actualSpeeds_dr_6G_X4 5 849 #define digital_actualSpeeds_dr_10G_HiG 6 850 #define digital_actualSpeeds_dr_10G_CX4 7 851 #define digital_actualSpeeds_dr_12G_HiG 8 852 #define digital_actualSpeeds_dr_12p5G_X4 9 853 #define digital_actualSpeeds_dr_13G_X4 10 854 #define digital_actualSpeeds_dr_15G_X4 11 855 #define digital_actualSpeeds_dr_16G_X4 12 856 #define digital_actualSpeeds_dr_1G_KX 13 857 #define digital_actualSpeeds_dr_10G_KX4 14 858 #define digital_actualSpeeds_dr_10G_KR 15 859 #define digital_actualSpeeds_dr_5G 16 860 #define digital_actualSpeeds_dr_6p4G 17 861 #define digital_actualSpeeds_dr_20G_X4 18 862 #define digital_actualSpeeds_dr_21G_X4 19 863 #define digital_actualSpeeds_dr_25G_X4 20 864 #define digital_actualSpeeds_dr_10G_HiG_DXGXS 21 865 #define digital_actualSpeeds_dr_10G_DXGXS 22 866 #define digital_actualSpeeds_dr_10p5G_HiG_DXGXS 23 867 #define digital_actualSpeeds_dr_10p5G_DXGXS 24 868 #define digital_actualSpeeds_dr_12p773G_HiG_DXGXS 25 869 #define digital_actualSpeeds_dr_12p773G_DXGXS 26 870 #define digital_actualSpeeds_dr_10G_XFI 27 871 #define digital_actualSpeeds_dr_40G 28 872 #define digital_actualSpeeds_dr_20G_HiG_DXGXS 29 873 #define digital_actualSpeeds_dr_20G_DXGXS 30 874 #define digital_actualSpeeds_dr_10G_SFI 31 875 #define digital_actualSpeeds_dr_31p5G 32 876 #define digital_actualSpeeds_dr_32p7G 33 877 #define digital_actualSpeeds_dr_20G_SCR 34 878 #define digital_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 879 #define digital_actualSpeeds_dr_10G_DXGXS_SCR 36 880 #define digital_actualSpeeds_dr_12G_R2 37 881 #define digital_actualSpeeds_dr_10G_X2 38 882 #define digital_actualSpeeds_dr_40G_KR4 39 883 #define digital_actualSpeeds_dr_40G_CR4 40 884 #define digital_actualSpeeds_dr_100G_CR10 41 885 #define digital_actualSpeeds_dr_15p75G_DXGXS 44 886 #define digital_actualSpeeds_dr_20G_KR2 57 887 #define digital_actualSpeeds_dr_20G_CR2 58 888 889 /**************************************************************************** 890 * Enums: digital_actualSpeedsMisc1 891 */ 892 #define digital_actualSpeedsMisc1_dr_2500BRCM_X1 16 893 #define digital_actualSpeedsMisc1_dr_5000BRCM_X4 17 894 #define digital_actualSpeedsMisc1_dr_6000BRCM_X4 18 895 #define digital_actualSpeedsMisc1_dr_10GHiGig_X4 19 896 #define digital_actualSpeedsMisc1_dr_10GBASE_CX4 20 897 #define digital_actualSpeedsMisc1_dr_12GHiGig_X4 21 898 #define digital_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 899 #define digital_actualSpeedsMisc1_dr_13GHiGig_X4 23 900 #define digital_actualSpeedsMisc1_dr_15GHiGig_X4 24 901 #define digital_actualSpeedsMisc1_dr_16GHiGig_X4 25 902 #define digital_actualSpeedsMisc1_dr_5000BRCM_X1 26 903 #define digital_actualSpeedsMisc1_dr_6363BRCM_X1 27 904 #define digital_actualSpeedsMisc1_dr_20GHiGig_X4 28 905 #define digital_actualSpeedsMisc1_dr_21GHiGig_X4 29 906 #define digital_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 907 #define digital_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 908 909 /**************************************************************************** 910 * Enums: digital_IndLaneModes 911 */ 912 #define digital_IndLaneModes_SWSDR_div2 0 913 #define digital_IndLaneModes_SWSDR_div1 1 914 #define digital_IndLaneModes_DWSDR_div2 2 915 #define digital_IndLaneModes_DWSDR_div1 3 916 917 /**************************************************************************** 918 * Enums: digital_prbsSelect 919 */ 920 #define digital_prbsSelect_prbs7 0 921 #define digital_prbsSelect_prbs15 1 922 #define digital_prbsSelect_prbs23 2 923 #define digital_prbsSelect_prbs31 3 924 925 /**************************************************************************** 926 * Enums: digital_vcoDivider 927 */ 928 #define digital_vcoDivider_div32 0 929 #define digital_vcoDivider_div36 1 930 #define digital_vcoDivider_div40 2 931 #define digital_vcoDivider_div42 3 932 #define digital_vcoDivider_div48 4 933 #define digital_vcoDivider_div50 5 934 #define digital_vcoDivider_div52 6 935 #define digital_vcoDivider_div54 7 936 #define digital_vcoDivider_div60 8 937 #define digital_vcoDivider_div64 9 938 #define digital_vcoDivider_div66 10 939 #define digital_vcoDivider_div68 11 940 #define digital_vcoDivider_div70 12 941 #define digital_vcoDivider_div80 13 942 #define digital_vcoDivider_div92 14 943 #define digital_vcoDivider_div100 15 944 945 /**************************************************************************** 946 * Enums: digital_refClkSelect 947 */ 948 #define digital_refClkSelect_clk_25MHz 0 949 #define digital_refClkSelect_clk_100MHz 1 950 #define digital_refClkSelect_clk_125MHz 2 951 #define digital_refClkSelect_clk_156p25MHz 3 952 #define digital_refClkSelect_clk_187p5MHz 4 953 #define digital_refClkSelect_clk_161p25Mhz 5 954 #define digital_refClkSelect_clk_50Mhz 6 955 #define digital_refClkSelect_clk_106p25Mhz 7 956 957 /**************************************************************************** 958 * Enums: digital_aerMMDdevTypeSelect 959 */ 960 #define digital_aerMMDdevTypeSelect_combo_core 0 961 #define digital_aerMMDdevTypeSelect_PMA_PMD 1 962 #define digital_aerMMDdevTypeSelect_PCS 3 963 #define digital_aerMMDdevTypeSelect_PHY 4 964 #define digital_aerMMDdevTypeSelect_DTE 5 965 #define digital_aerMMDdevTypeSelect_CL73_AN 7 966 967 /**************************************************************************** 968 * Enums: digital_aerMMDportSelect 969 */ 970 #define digital_aerMMDportSelect_ln0 0 971 #define digital_aerMMDportSelect_ln1 1 972 #define digital_aerMMDportSelect_ln2 2 973 #define digital_aerMMDportSelect_ln3 3 974 #define digital_aerMMDportSelect_BCST_ln0_1_2_3 511 975 #define digital_aerMMDportSelect_BCST_ln0_1 512 976 #define digital_aerMMDportSelect_BCST_ln2_3 513 977 978 /**************************************************************************** 979 * Enums: digital_firmwareModeSelect 980 */ 981 #define digital_firmwareModeSelect_DEFAULT 0 982 #define digital_firmwareModeSelect_SFP_OPT_LR 1 983 #define digital_firmwareModeSelect_SFP_DAC 2 984 #define digital_firmwareModeSelect_XLAUI 3 985 #define digital_firmwareModeSelect_LONG_CH_6G 4 986 987 /**************************************************************************** 988 * Enums: digital_tempIdxSelect 989 */ 990 #define digital_tempIdxSelect_LTE__22p9C 15 991 #define digital_tempIdxSelect_LTE__12p6C 14 992 #define digital_tempIdxSelect_LTE__3p0C 13 993 #define digital_tempIdxSelect_LTE_6p7C 12 994 #define digital_tempIdxSelect_LTE_16p4C 11 995 #define digital_tempIdxSelect_LTE_26p6C 10 996 #define digital_tempIdxSelect_LTE_36p3C 9 997 #define digital_tempIdxSelect_LTE_46p0C 8 998 #define digital_tempIdxSelect_LTE_56p2C 7 999 #define digital_tempIdxSelect_LTE_65p9C 6 1000 #define digital_tempIdxSelect_LTE_75p6C 5 1001 #define digital_tempIdxSelect_LTE_85p3C 4 1002 #define digital_tempIdxSelect_LTE_95p5C 3 1003 #define digital_tempIdxSelect_LTE_105p2C 2 1004 #define digital_tempIdxSelect_LTE_114p9C 1 1005 #define digital_tempIdxSelect_LTE_125p1C 0 1006 1007 /**************************************************************************** 1008 * Enums: generic_cl36TxEEEStates_l 1009 */ 1010 #define generic_cl36TxEEEStates_l_TX_REFRESH 8 1011 #define generic_cl36TxEEEStates_l_TX_QUIET 4 1012 #define generic_cl36TxEEEStates_l_TX_SLEEP 2 1013 #define generic_cl36TxEEEStates_l_TX_ACTIVE 1 1014 1015 /**************************************************************************** 1016 * Enums: generic_cl36TxEEEStates_c 1017 */ 1018 #define generic_cl36TxEEEStates_c_TX_REFRESH 3 1019 #define generic_cl36TxEEEStates_c_TX_QUIET 2 1020 #define generic_cl36TxEEEStates_c_TX_SLEEP 1 1021 #define generic_cl36TxEEEStates_c_TX_ACTIVE 0 1022 1023 /**************************************************************************** 1024 * Enums: generic_cl49TxEEEStates_l 1025 */ 1026 #define generic_cl49TxEEEStates_l_SCR_RESET_2 64 1027 #define generic_cl49TxEEEStates_l_SCR_RESET_1 32 1028 #define generic_cl49TxEEEStates_l_TX_WAKE 16 1029 #define generic_cl49TxEEEStates_l_TX_REFRESH 8 1030 #define generic_cl49TxEEEStates_l_TX_QUIET 4 1031 #define generic_cl49TxEEEStates_l_TX_SLEEP 2 1032 #define generic_cl49TxEEEStates_l_TX_ACTIVE 1 1033 1034 /**************************************************************************** 1035 * Enums: generic_cl49TxEEEStates_c 1036 */ 1037 #define generic_cl49TxEEEStates_c_SCR_RESET_2 6 1038 #define generic_cl49TxEEEStates_c_SCR_RESET_1 5 1039 #define generic_cl49TxEEEStates_c_TX_WAKE 4 1040 #define generic_cl49TxEEEStates_c_TX_REFRESH 3 1041 #define generic_cl49TxEEEStates_c_TX_QUIET 2 1042 #define generic_cl49TxEEEStates_c_TX_SLEEP 1 1043 #define generic_cl49TxEEEStates_c_TX_ACTIVE 0 1044 1045 /**************************************************************************** 1046 * Enums: generic_cl36RxEEEStates_l 1047 */ 1048 #define generic_cl36RxEEEStates_l_RX_LINK_FAIL 32 1049 #define generic_cl36RxEEEStates_l_RX_WTF 16 1050 #define generic_cl36RxEEEStates_l_RX_WAKE 8 1051 #define generic_cl36RxEEEStates_l_RX_QUIET 4 1052 #define generic_cl36RxEEEStates_l_RX_SLEEP 2 1053 #define generic_cl36RxEEEStates_l_RX_ACTIVE 1 1054 1055 /**************************************************************************** 1056 * Enums: generic_cl36RxEEEStates_c 1057 */ 1058 #define generic_cl36RxEEEStates_c_RX_LINK_FAIL 5 1059 #define generic_cl36RxEEEStates_c_RX_WTF 4 1060 #define generic_cl36RxEEEStates_c_RX_WAKE 3 1061 #define generic_cl36RxEEEStates_c_RX_QUIET 2 1062 #define generic_cl36RxEEEStates_c_RX_SLEEP 1 1063 #define generic_cl36RxEEEStates_c_RX_ACTIVE 0 1064 1065 /**************************************************************************** 1066 * Enums: generic_cl49RxEEEStates_l 1067 */ 1068 #define generic_cl49RxEEEStates_l_RX_LINK_FAIL 32 1069 #define generic_cl49RxEEEStates_l_RX_WTF 16 1070 #define generic_cl49RxEEEStates_l_RX_WAKE 8 1071 #define generic_cl49RxEEEStates_l_RX_QUIET 4 1072 #define generic_cl49RxEEEStates_l_RX_SLEEP 2 1073 #define generic_cl49RxEEEStates_l_RX_ACTIVE 1 1074 1075 /**************************************************************************** 1076 * Enums: generic_cl49RxEEEStates_c 1077 */ 1078 #define generic_cl49RxEEEStates_c_RX_LINK_FAIL 5 1079 #define generic_cl49RxEEEStates_c_RX_WTF 4 1080 #define generic_cl49RxEEEStates_c_RX_WAKE 3 1081 #define generic_cl49RxEEEStates_c_RX_QUIET 2 1082 #define generic_cl49RxEEEStates_c_RX_SLEEP 1 1083 #define generic_cl49RxEEEStates_c_RX_ACTIVE 0 1084 1085 /**************************************************************************** 1086 * Enums: generic_cl48TxEEEStates_l 1087 */ 1088 #define generic_cl48TxEEEStates_l_TX_REFRESH 8 1089 #define generic_cl48TxEEEStates_l_TX_QUIET 4 1090 #define generic_cl48TxEEEStates_l_TX_SLEEP 2 1091 #define generic_cl48TxEEEStates_l_TX_ACTIVE 1 1092 1093 /**************************************************************************** 1094 * Enums: generic_cl48TxEEEStates_c 1095 */ 1096 #define generic_cl48TxEEEStates_c_TX_REFRESH 3 1097 #define generic_cl48TxEEEStates_c_TX_QUIET 2 1098 #define generic_cl48TxEEEStates_c_TX_SLEEP 1 1099 #define generic_cl48TxEEEStates_c_TX_ACTIVE 0 1100 1101 /**************************************************************************** 1102 * Enums: generic_cl48RxEEEStates_l 1103 */ 1104 #define generic_cl48RxEEEStates_l_RX_LINK_FAIL 32 1105 #define generic_cl48RxEEEStates_l_RX_WAKE 16 1106 #define generic_cl48RxEEEStates_l_RX_QUIET 8 1107 #define generic_cl48RxEEEStates_l_RX_DEACT 4 1108 #define generic_cl48RxEEEStates_l_RX_SLEEP 2 1109 #define generic_cl48RxEEEStates_l_RX_ACTIVE 1 1110 1111 /**************************************************************************** 1112 * Enums: generic_cl48RxEEEStates_c 1113 */ 1114 #define generic_cl48RxEEEStates_c_RX_LINK_FAIL 5 1115 #define generic_cl48RxEEEStates_c_RX_WAKE 4 1116 #define generic_cl48RxEEEStates_c_RX_QUIET 3 1117 #define generic_cl48RxEEEStates_c_RX_DEACT 2 1118 #define generic_cl48RxEEEStates_c_RX_SLEEP 1 1119 #define generic_cl48RxEEEStates_c_RX_ACTIVE 0 1120 1121 /**************************************************************************** 1122 * Enums: generic_IQP_Options 1123 */ 1124 #define generic_IQP_Options_i50uA 0 1125 #define generic_IQP_Options_i100uA 1 1126 #define generic_IQP_Options_i150uA 2 1127 #define generic_IQP_Options_i200uA 3 1128 #define generic_IQP_Options_i250uA 4 1129 #define generic_IQP_Options_i300uA 5 1130 #define generic_IQP_Options_i350uA 6 1131 #define generic_IQP_Options_i400uA 7 1132 #define generic_IQP_Options_i450uA 8 1133 #define generic_IQP_Options_i500uA 9 1134 #define generic_IQP_Options_i550uA 10 1135 #define generic_IQP_Options_i600uA 11 1136 #define generic_IQP_Options_i650uA 12 1137 #define generic_IQP_Options_i700uA 13 1138 #define generic_IQP_Options_i750uA 14 1139 #define generic_IQP_Options_i800uA 15 1140 1141 /**************************************************************************** 1142 * Enums: generic_IDriver_Options 1143 */ 1144 #define generic_IDriver_Options_v680mV 0 1145 #define generic_IDriver_Options_v730mV 1 1146 #define generic_IDriver_Options_v780mV 2 1147 #define generic_IDriver_Options_v830mV 3 1148 #define generic_IDriver_Options_v880mV 4 1149 #define generic_IDriver_Options_v930mV 5 1150 #define generic_IDriver_Options_v980mV 6 1151 #define generic_IDriver_Options_v1010mV 7 1152 #define generic_IDriver_Options_v1040mV 8 1153 #define generic_IDriver_Options_v1060mV 9 1154 #define generic_IDriver_Options_v1070mV 10 1155 #define generic_IDriver_Options_v1080mV 11 1156 #define generic_IDriver_Options_v1085mV 12 1157 #define generic_IDriver_Options_v1090mV 13 1158 #define generic_IDriver_Options_v1095mV 14 1159 #define generic_IDriver_Options_v1100mV 15 1160 1161 /**************************************************************************** 1162 * Enums: generic_operationModes 1163 */ 1164 #define generic_operationModes_XGXS 0 1165 #define generic_operationModes_XGXG_nCC 1 1166 #define generic_operationModes_Indlane_OS8 4 1167 #define generic_operationModes_IndLane_OS5 5 1168 #define generic_operationModes_PCI 7 1169 #define generic_operationModes_XGXS_nLQ 8 1170 #define generic_operationModes_XGXS_nLQnCC 9 1171 #define generic_operationModes_PBypass 10 1172 #define generic_operationModes_PBypass_nDSK 11 1173 #define generic_operationModes_ComboCoreMode 12 1174 #define generic_operationModes_Clocks_off 15 1175 1176 /**************************************************************************** 1177 * Enums: generic_synce_enum 1178 */ 1179 #define generic_synce_enum_SYNCE_NO_DIV 0 1180 #define generic_synce_enum_SYNCE_DIV_7 1 1181 #define generic_synce_enum_SYNCE_DIV_11 2 1182 1183 /**************************************************************************** 1184 * Enums: generic_operationSpeeds 1185 */ 1186 #define generic_operationSpeeds_SPEED_2p5G_X1_10p3125 56 1187 #define generic_operationSpeeds_SPEED_1000M_10p3125 55 1188 #define generic_operationSpeeds_SPEED_100M_10p3125 54 1189 #define generic_operationSpeeds_SPEED_10M_10p3125 53 1190 #define generic_operationSpeeds_SPEED_10p5G_X4 50 1191 #define generic_operationSpeeds_SPEED_5G_KR1 49 1192 #define generic_operationSpeeds_SPEED_127G_X12 39 1193 #define generic_operationSpeeds_SPEED_120G_X12 38 1194 #define generic_operationSpeeds_SPEED_107G_X10 37 1195 #define generic_operationSpeeds_SPEED_100G_CR10 36 1196 #define generic_operationSpeeds_SPEED_42G_X4 35 1197 #define generic_operationSpeeds_SPEED_40G_CR4 34 1198 #define generic_operationSpeeds_SPEED_40G_KR4 33 1199 #define generic_operationSpeeds_SPEED_21G_X2 32 1200 #define generic_operationSpeeds_SPEED_20G_CR2 31 1201 #define generic_operationSpeeds_SPEED_20G_KR2 30 1202 #define generic_operationSpeeds_SPEED_10p6_X1 29 1203 #define generic_operationSpeeds_SPEED_10G_KR1 28 1204 #define generic_operationSpeeds_SPEED_40G_X4 27 1205 #define generic_operationSpeeds_SPEED_20G_X2 26 1206 #define generic_operationSpeeds_SPEED_20G_CX2 25 1207 #define generic_operationSpeeds_SPEED_31p5G_KR4 24 1208 #define generic_operationSpeeds_SPEED_31p5G_X4 23 1209 #define generic_operationSpeeds_SPEED_15p75G_X2 22 1210 #define generic_operationSpeeds_SPEED_25p45G_X4 21 1211 #define generic_operationSpeeds_SPEED_12p7G_X2 20 1212 #define generic_operationSpeeds_SPEED_21G_X4 19 1213 #define generic_operationSpeeds_SPEED_10p5G_X2 18 1214 #define generic_operationSpeeds_SPEED_20G_X4 17 1215 #define generic_operationSpeeds_SPEED_10G_X2 16 1216 #define generic_operationSpeeds_SPEED_10G_CX2 15 1217 #define generic_operationSpeeds_SPEED_20G_CX4 14 1218 #define generic_operationSpeeds_SPEED_16G_X4 13 1219 #define generic_operationSpeeds_SPEED_15G_X4 12 1220 #define generic_operationSpeeds_SPEED_13G_X4 11 1221 #define generic_operationSpeeds_SPEED_10G_X4 10 1222 #define generic_operationSpeeds_SPEED_10G_KX4 9 1223 #define generic_operationSpeeds_SPEED_10G_CX4 8 1224 #define generic_operationSpeeds_SPEED_5G_X1 7 1225 #define generic_operationSpeeds_SPEED_2p5G_X1 6 1226 #define generic_operationSpeeds_SPEED_1G_KX1 5 1227 #define generic_operationSpeeds_SPEED_1G_CX1 4 1228 #define generic_operationSpeeds_SPEED_1000M 3 1229 #define generic_operationSpeeds_SPEED_100M 2 1230 #define generic_operationSpeeds_SPEED_10M 1 1231 1232 /**************************************************************************** 1233 * Enums: generic_actualSpeeds 1234 */ 1235 #define generic_actualSpeeds_dr_10M 0 1236 #define generic_actualSpeeds_dr_100M 1 1237 #define generic_actualSpeeds_dr_1G 2 1238 #define generic_actualSpeeds_dr_2p5G 3 1239 #define generic_actualSpeeds_dr_5G_X4 4 1240 #define generic_actualSpeeds_dr_6G_X4 5 1241 #define generic_actualSpeeds_dr_10G_HiG 6 1242 #define generic_actualSpeeds_dr_10G_CX4 7 1243 #define generic_actualSpeeds_dr_12G_HiG 8 1244 #define generic_actualSpeeds_dr_12p5G_X4 9 1245 #define generic_actualSpeeds_dr_13G_X4 10 1246 #define generic_actualSpeeds_dr_15G_X4 11 1247 #define generic_actualSpeeds_dr_16G_X4 12 1248 #define generic_actualSpeeds_dr_1G_KX 13 1249 #define generic_actualSpeeds_dr_10G_KX4 14 1250 #define generic_actualSpeeds_dr_10G_KR 15 1251 #define generic_actualSpeeds_dr_5G 16 1252 #define generic_actualSpeeds_dr_6p4G 17 1253 #define generic_actualSpeeds_dr_20G_X4 18 1254 #define generic_actualSpeeds_dr_21G_X4 19 1255 #define generic_actualSpeeds_dr_25G_X4 20 1256 #define generic_actualSpeeds_dr_10G_HiG_DXGXS 21 1257 #define generic_actualSpeeds_dr_10G_DXGXS 22 1258 #define generic_actualSpeeds_dr_10p5G_HiG_DXGXS 23 1259 #define generic_actualSpeeds_dr_10p5G_DXGXS 24 1260 #define generic_actualSpeeds_dr_12p773G_HiG_DXGXS 25 1261 #define generic_actualSpeeds_dr_12p773G_DXGXS 26 1262 #define generic_actualSpeeds_dr_10G_XFI 27 1263 #define generic_actualSpeeds_dr_40G 28 1264 #define generic_actualSpeeds_dr_20G_HiG_DXGXS 29 1265 #define generic_actualSpeeds_dr_20G_DXGXS 30 1266 #define generic_actualSpeeds_dr_10G_SFI 31 1267 #define generic_actualSpeeds_dr_31p5G 32 1268 #define generic_actualSpeeds_dr_32p7G 33 1269 #define generic_actualSpeeds_dr_20G_SCR 34 1270 #define generic_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 1271 #define generic_actualSpeeds_dr_10G_DXGXS_SCR 36 1272 #define generic_actualSpeeds_dr_12G_R2 37 1273 #define generic_actualSpeeds_dr_10G_X2 38 1274 #define generic_actualSpeeds_dr_40G_KR4 39 1275 #define generic_actualSpeeds_dr_40G_CR4 40 1276 #define generic_actualSpeeds_dr_100G_CR10 41 1277 #define generic_actualSpeeds_dr_15p75G_DXGXS 44 1278 #define generic_actualSpeeds_dr_20G_KR2 57 1279 #define generic_actualSpeeds_dr_20G_CR2 58 1280 1281 /**************************************************************************** 1282 * Enums: generic_actualSpeedsMisc1 1283 */ 1284 #define generic_actualSpeedsMisc1_dr_2500BRCM_X1 16 1285 #define generic_actualSpeedsMisc1_dr_5000BRCM_X4 17 1286 #define generic_actualSpeedsMisc1_dr_6000BRCM_X4 18 1287 #define generic_actualSpeedsMisc1_dr_10GHiGig_X4 19 1288 #define generic_actualSpeedsMisc1_dr_10GBASE_CX4 20 1289 #define generic_actualSpeedsMisc1_dr_12GHiGig_X4 21 1290 #define generic_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 1291 #define generic_actualSpeedsMisc1_dr_13GHiGig_X4 23 1292 #define generic_actualSpeedsMisc1_dr_15GHiGig_X4 24 1293 #define generic_actualSpeedsMisc1_dr_16GHiGig_X4 25 1294 #define generic_actualSpeedsMisc1_dr_5000BRCM_X1 26 1295 #define generic_actualSpeedsMisc1_dr_6363BRCM_X1 27 1296 #define generic_actualSpeedsMisc1_dr_20GHiGig_X4 28 1297 #define generic_actualSpeedsMisc1_dr_21GHiGig_X4 29 1298 #define generic_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 1299 #define generic_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 1300 1301 /**************************************************************************** 1302 * Enums: generic_IndLaneModes 1303 */ 1304 #define generic_IndLaneModes_SWSDR_div2 0 1305 #define generic_IndLaneModes_SWSDR_div1 1 1306 #define generic_IndLaneModes_DWSDR_div2 2 1307 #define generic_IndLaneModes_DWSDR_div1 3 1308 1309 /**************************************************************************** 1310 * Enums: generic_prbsSelect 1311 */ 1312 #define generic_prbsSelect_prbs7 0 1313 #define generic_prbsSelect_prbs15 1 1314 #define generic_prbsSelect_prbs23 2 1315 #define generic_prbsSelect_prbs31 3 1316 1317 /**************************************************************************** 1318 * Enums: generic_vcoDivider 1319 */ 1320 #define generic_vcoDivider_div32 0 1321 #define generic_vcoDivider_div36 1 1322 #define generic_vcoDivider_div40 2 1323 #define generic_vcoDivider_div42 3 1324 #define generic_vcoDivider_div48 4 1325 #define generic_vcoDivider_div50 5 1326 #define generic_vcoDivider_div52 6 1327 #define generic_vcoDivider_div54 7 1328 #define generic_vcoDivider_div60 8 1329 #define generic_vcoDivider_div64 9 1330 #define generic_vcoDivider_div66 10 1331 #define generic_vcoDivider_div68 11 1332 #define generic_vcoDivider_div70 12 1333 #define generic_vcoDivider_div80 13 1334 #define generic_vcoDivider_div92 14 1335 #define generic_vcoDivider_div100 15 1336 1337 /**************************************************************************** 1338 * Enums: generic_refClkSelect 1339 */ 1340 #define generic_refClkSelect_clk_25MHz 0 1341 #define generic_refClkSelect_clk_100MHz 1 1342 #define generic_refClkSelect_clk_125MHz 2 1343 #define generic_refClkSelect_clk_156p25MHz 3 1344 #define generic_refClkSelect_clk_187p5MHz 4 1345 #define generic_refClkSelect_clk_161p25Mhz 5 1346 #define generic_refClkSelect_clk_50Mhz 6 1347 #define generic_refClkSelect_clk_106p25Mhz 7 1348 1349 /**************************************************************************** 1350 * Enums: generic_aerMMDdevTypeSelect 1351 */ 1352 #define generic_aerMMDdevTypeSelect_combo_core 0 1353 #define generic_aerMMDdevTypeSelect_PMA_PMD 1 1354 #define generic_aerMMDdevTypeSelect_PCS 3 1355 #define generic_aerMMDdevTypeSelect_PHY 4 1356 #define generic_aerMMDdevTypeSelect_DTE 5 1357 #define generic_aerMMDdevTypeSelect_CL73_AN 7 1358 1359 /**************************************************************************** 1360 * Enums: generic_aerMMDportSelect 1361 */ 1362 #define generic_aerMMDportSelect_ln0 0 1363 #define generic_aerMMDportSelect_ln1 1 1364 #define generic_aerMMDportSelect_ln2 2 1365 #define generic_aerMMDportSelect_ln3 3 1366 #define generic_aerMMDportSelect_BCST_ln0_1_2_3 511 1367 #define generic_aerMMDportSelect_BCST_ln0_1 512 1368 #define generic_aerMMDportSelect_BCST_ln2_3 513 1369 1370 /**************************************************************************** 1371 * Enums: generic_firmwareModeSelect 1372 */ 1373 #define generic_firmwareModeSelect_DEFAULT 0 1374 #define generic_firmwareModeSelect_SFP_OPT_LR 1 1375 #define generic_firmwareModeSelect_SFP_DAC 2 1376 #define generic_firmwareModeSelect_XLAUI 3 1377 #define generic_firmwareModeSelect_LONG_CH_6G 4 1378 1379 /**************************************************************************** 1380 * Enums: generic_tempIdxSelect 1381 */ 1382 #define generic_tempIdxSelect_LTE__22p9C 15 1383 #define generic_tempIdxSelect_LTE__12p6C 14 1384 #define generic_tempIdxSelect_LTE__3p0C 13 1385 #define generic_tempIdxSelect_LTE_6p7C 12 1386 #define generic_tempIdxSelect_LTE_16p4C 11 1387 #define generic_tempIdxSelect_LTE_26p6C 10 1388 #define generic_tempIdxSelect_LTE_36p3C 9 1389 #define generic_tempIdxSelect_LTE_46p0C 8 1390 #define generic_tempIdxSelect_LTE_56p2C 7 1391 #define generic_tempIdxSelect_LTE_65p9C 6 1392 #define generic_tempIdxSelect_LTE_75p6C 5 1393 #define generic_tempIdxSelect_LTE_85p3C 4 1394 #define generic_tempIdxSelect_LTE_95p5C 3 1395 #define generic_tempIdxSelect_LTE_105p2C 2 1396 #define generic_tempIdxSelect_LTE_114p9C 1 1397 #define generic_tempIdxSelect_LTE_125p1C 0 1398 1399 /**************************************************************************** 1400 * Enums: main0_cl36TxEEEStates_l 1401 */ 1402 #define main0_cl36TxEEEStates_l_TX_REFRESH 8 1403 #define main0_cl36TxEEEStates_l_TX_QUIET 4 1404 #define main0_cl36TxEEEStates_l_TX_SLEEP 2 1405 #define main0_cl36TxEEEStates_l_TX_ACTIVE 1 1406 1407 /**************************************************************************** 1408 * Enums: main0_cl36TxEEEStates_c 1409 */ 1410 #define main0_cl36TxEEEStates_c_TX_REFRESH 3 1411 #define main0_cl36TxEEEStates_c_TX_QUIET 2 1412 #define main0_cl36TxEEEStates_c_TX_SLEEP 1 1413 #define main0_cl36TxEEEStates_c_TX_ACTIVE 0 1414 1415 /**************************************************************************** 1416 * Enums: main0_cl49TxEEEStates_l 1417 */ 1418 #define main0_cl49TxEEEStates_l_SCR_RESET_2 64 1419 #define main0_cl49TxEEEStates_l_SCR_RESET_1 32 1420 #define main0_cl49TxEEEStates_l_TX_WAKE 16 1421 #define main0_cl49TxEEEStates_l_TX_REFRESH 8 1422 #define main0_cl49TxEEEStates_l_TX_QUIET 4 1423 #define main0_cl49TxEEEStates_l_TX_SLEEP 2 1424 #define main0_cl49TxEEEStates_l_TX_ACTIVE 1 1425 1426 /**************************************************************************** 1427 * Enums: main0_cl49TxEEEStates_c 1428 */ 1429 #define main0_cl49TxEEEStates_c_SCR_RESET_2 6 1430 #define main0_cl49TxEEEStates_c_SCR_RESET_1 5 1431 #define main0_cl49TxEEEStates_c_TX_WAKE 4 1432 #define main0_cl49TxEEEStates_c_TX_REFRESH 3 1433 #define main0_cl49TxEEEStates_c_TX_QUIET 2 1434 #define main0_cl49TxEEEStates_c_TX_SLEEP 1 1435 #define main0_cl49TxEEEStates_c_TX_ACTIVE 0 1436 1437 /**************************************************************************** 1438 * Enums: main0_cl36RxEEEStates_l 1439 */ 1440 #define main0_cl36RxEEEStates_l_RX_LINK_FAIL 32 1441 #define main0_cl36RxEEEStates_l_RX_WTF 16 1442 #define main0_cl36RxEEEStates_l_RX_WAKE 8 1443 #define main0_cl36RxEEEStates_l_RX_QUIET 4 1444 #define main0_cl36RxEEEStates_l_RX_SLEEP 2 1445 #define main0_cl36RxEEEStates_l_RX_ACTIVE 1 1446 1447 /**************************************************************************** 1448 * Enums: main0_cl36RxEEEStates_c 1449 */ 1450 #define main0_cl36RxEEEStates_c_RX_LINK_FAIL 5 1451 #define main0_cl36RxEEEStates_c_RX_WTF 4 1452 #define main0_cl36RxEEEStates_c_RX_WAKE 3 1453 #define main0_cl36RxEEEStates_c_RX_QUIET 2 1454 #define main0_cl36RxEEEStates_c_RX_SLEEP 1 1455 #define main0_cl36RxEEEStates_c_RX_ACTIVE 0 1456 1457 /**************************************************************************** 1458 * Enums: main0_cl49RxEEEStates_l 1459 */ 1460 #define main0_cl49RxEEEStates_l_RX_LINK_FAIL 32 1461 #define main0_cl49RxEEEStates_l_RX_WTF 16 1462 #define main0_cl49RxEEEStates_l_RX_WAKE 8 1463 #define main0_cl49RxEEEStates_l_RX_QUIET 4 1464 #define main0_cl49RxEEEStates_l_RX_SLEEP 2 1465 #define main0_cl49RxEEEStates_l_RX_ACTIVE 1 1466 1467 /**************************************************************************** 1468 * Enums: main0_cl49RxEEEStates_c 1469 */ 1470 #define main0_cl49RxEEEStates_c_RX_LINK_FAIL 5 1471 #define main0_cl49RxEEEStates_c_RX_WTF 4 1472 #define main0_cl49RxEEEStates_c_RX_WAKE 3 1473 #define main0_cl49RxEEEStates_c_RX_QUIET 2 1474 #define main0_cl49RxEEEStates_c_RX_SLEEP 1 1475 #define main0_cl49RxEEEStates_c_RX_ACTIVE 0 1476 1477 /**************************************************************************** 1478 * Enums: main0_cl48TxEEEStates_l 1479 */ 1480 #define main0_cl48TxEEEStates_l_TX_REFRESH 8 1481 #define main0_cl48TxEEEStates_l_TX_QUIET 4 1482 #define main0_cl48TxEEEStates_l_TX_SLEEP 2 1483 #define main0_cl48TxEEEStates_l_TX_ACTIVE 1 1484 1485 /**************************************************************************** 1486 * Enums: main0_cl48TxEEEStates_c 1487 */ 1488 #define main0_cl48TxEEEStates_c_TX_REFRESH 3 1489 #define main0_cl48TxEEEStates_c_TX_QUIET 2 1490 #define main0_cl48TxEEEStates_c_TX_SLEEP 1 1491 #define main0_cl48TxEEEStates_c_TX_ACTIVE 0 1492 1493 /**************************************************************************** 1494 * Enums: main0_cl48RxEEEStates_l 1495 */ 1496 #define main0_cl48RxEEEStates_l_RX_LINK_FAIL 32 1497 #define main0_cl48RxEEEStates_l_RX_WAKE 16 1498 #define main0_cl48RxEEEStates_l_RX_QUIET 8 1499 #define main0_cl48RxEEEStates_l_RX_DEACT 4 1500 #define main0_cl48RxEEEStates_l_RX_SLEEP 2 1501 #define main0_cl48RxEEEStates_l_RX_ACTIVE 1 1502 1503 /**************************************************************************** 1504 * Enums: main0_cl48RxEEEStates_c 1505 */ 1506 #define main0_cl48RxEEEStates_c_RX_LINK_FAIL 5 1507 #define main0_cl48RxEEEStates_c_RX_WAKE 4 1508 #define main0_cl48RxEEEStates_c_RX_QUIET 3 1509 #define main0_cl48RxEEEStates_c_RX_DEACT 2 1510 #define main0_cl48RxEEEStates_c_RX_SLEEP 1 1511 #define main0_cl48RxEEEStates_c_RX_ACTIVE 0 1512 1513 /**************************************************************************** 1514 * Enums: main0_IQP_Options 1515 */ 1516 #define main0_IQP_Options_i50uA 0 1517 #define main0_IQP_Options_i100uA 1 1518 #define main0_IQP_Options_i150uA 2 1519 #define main0_IQP_Options_i200uA 3 1520 #define main0_IQP_Options_i250uA 4 1521 #define main0_IQP_Options_i300uA 5 1522 #define main0_IQP_Options_i350uA 6 1523 #define main0_IQP_Options_i400uA 7 1524 #define main0_IQP_Options_i450uA 8 1525 #define main0_IQP_Options_i500uA 9 1526 #define main0_IQP_Options_i550uA 10 1527 #define main0_IQP_Options_i600uA 11 1528 #define main0_IQP_Options_i650uA 12 1529 #define main0_IQP_Options_i700uA 13 1530 #define main0_IQP_Options_i750uA 14 1531 #define main0_IQP_Options_i800uA 15 1532 1533 /**************************************************************************** 1534 * Enums: main0_IDriver_Options 1535 */ 1536 #define main0_IDriver_Options_v680mV 0 1537 #define main0_IDriver_Options_v730mV 1 1538 #define main0_IDriver_Options_v780mV 2 1539 #define main0_IDriver_Options_v830mV 3 1540 #define main0_IDriver_Options_v880mV 4 1541 #define main0_IDriver_Options_v930mV 5 1542 #define main0_IDriver_Options_v980mV 6 1543 #define main0_IDriver_Options_v1010mV 7 1544 #define main0_IDriver_Options_v1040mV 8 1545 #define main0_IDriver_Options_v1060mV 9 1546 #define main0_IDriver_Options_v1070mV 10 1547 #define main0_IDriver_Options_v1080mV 11 1548 #define main0_IDriver_Options_v1085mV 12 1549 #define main0_IDriver_Options_v1090mV 13 1550 #define main0_IDriver_Options_v1095mV 14 1551 #define main0_IDriver_Options_v1100mV 15 1552 1553 /**************************************************************************** 1554 * Enums: main0_operationModes 1555 */ 1556 #define main0_operationModes_XGXS 0 1557 #define main0_operationModes_XGXG_nCC 1 1558 #define main0_operationModes_Indlane_OS8 4 1559 #define main0_operationModes_IndLane_OS5 5 1560 #define main0_operationModes_PCI 7 1561 #define main0_operationModes_XGXS_nLQ 8 1562 #define main0_operationModes_XGXS_nLQnCC 9 1563 #define main0_operationModes_PBypass 10 1564 #define main0_operationModes_PBypass_nDSK 11 1565 #define main0_operationModes_ComboCoreMode 12 1566 #define main0_operationModes_Clocks_off 15 1567 1568 /**************************************************************************** 1569 * Enums: main0_synce_enum 1570 */ 1571 #define main0_synce_enum_SYNCE_NO_DIV 0 1572 #define main0_synce_enum_SYNCE_DIV_7 1 1573 #define main0_synce_enum_SYNCE_DIV_11 2 1574 1575 /**************************************************************************** 1576 * Enums: main0_operationSpeeds 1577 */ 1578 #define main0_operationSpeeds_SPEED_2p5G_X1_10p3125 56 1579 #define main0_operationSpeeds_SPEED_1000M_10p3125 55 1580 #define main0_operationSpeeds_SPEED_100M_10p3125 54 1581 #define main0_operationSpeeds_SPEED_10M_10p3125 53 1582 #define main0_operationSpeeds_SPEED_10p5G_X4 50 1583 #define main0_operationSpeeds_SPEED_5G_KR1 49 1584 #define main0_operationSpeeds_SPEED_127G_X12 39 1585 #define main0_operationSpeeds_SPEED_120G_X12 38 1586 #define main0_operationSpeeds_SPEED_107G_X10 37 1587 #define main0_operationSpeeds_SPEED_100G_CR10 36 1588 #define main0_operationSpeeds_SPEED_42G_X4 35 1589 #define main0_operationSpeeds_SPEED_40G_CR4 34 1590 #define main0_operationSpeeds_SPEED_40G_KR4 33 1591 #define main0_operationSpeeds_SPEED_21G_X2 32 1592 #define main0_operationSpeeds_SPEED_20G_CR2 31 1593 #define main0_operationSpeeds_SPEED_20G_KR2 30 1594 #define main0_operationSpeeds_SPEED_10p6_X1 29 1595 #define main0_operationSpeeds_SPEED_10G_KR1 28 1596 #define main0_operationSpeeds_SPEED_40G_X4 27 1597 #define main0_operationSpeeds_SPEED_20G_X2 26 1598 #define main0_operationSpeeds_SPEED_20G_CX2 25 1599 #define main0_operationSpeeds_SPEED_31p5G_KR4 24 1600 #define main0_operationSpeeds_SPEED_31p5G_X4 23 1601 #define main0_operationSpeeds_SPEED_15p75G_X2 22 1602 #define main0_operationSpeeds_SPEED_25p45G_X4 21 1603 #define main0_operationSpeeds_SPEED_12p7G_X2 20 1604 #define main0_operationSpeeds_SPEED_21G_X4 19 1605 #define main0_operationSpeeds_SPEED_10p5G_X2 18 1606 #define main0_operationSpeeds_SPEED_20G_X4 17 1607 #define main0_operationSpeeds_SPEED_10G_X2 16 1608 #define main0_operationSpeeds_SPEED_10G_CX2 15 1609 #define main0_operationSpeeds_SPEED_20G_CX4 14 1610 #define main0_operationSpeeds_SPEED_16G_X4 13 1611 #define main0_operationSpeeds_SPEED_15G_X4 12 1612 #define main0_operationSpeeds_SPEED_13G_X4 11 1613 #define main0_operationSpeeds_SPEED_10G_X4 10 1614 #define main0_operationSpeeds_SPEED_10G_KX4 9 1615 #define main0_operationSpeeds_SPEED_10G_CX4 8 1616 #define main0_operationSpeeds_SPEED_5G_X1 7 1617 #define main0_operationSpeeds_SPEED_2p5G_X1 6 1618 #define main0_operationSpeeds_SPEED_1G_KX1 5 1619 #define main0_operationSpeeds_SPEED_1G_CX1 4 1620 #define main0_operationSpeeds_SPEED_1000M 3 1621 #define main0_operationSpeeds_SPEED_100M 2 1622 #define main0_operationSpeeds_SPEED_10M 1 1623 1624 /**************************************************************************** 1625 * Enums: main0_actualSpeeds 1626 */ 1627 #define main0_actualSpeeds_dr_10M 0 1628 #define main0_actualSpeeds_dr_100M 1 1629 #define main0_actualSpeeds_dr_1G 2 1630 #define main0_actualSpeeds_dr_2p5G 3 1631 #define main0_actualSpeeds_dr_5G_X4 4 1632 #define main0_actualSpeeds_dr_6G_X4 5 1633 #define main0_actualSpeeds_dr_10G_HiG 6 1634 #define main0_actualSpeeds_dr_10G_CX4 7 1635 #define main0_actualSpeeds_dr_12G_HiG 8 1636 #define main0_actualSpeeds_dr_12p5G_X4 9 1637 #define main0_actualSpeeds_dr_13G_X4 10 1638 #define main0_actualSpeeds_dr_15G_X4 11 1639 #define main0_actualSpeeds_dr_16G_X4 12 1640 #define main0_actualSpeeds_dr_1G_KX 13 1641 #define main0_actualSpeeds_dr_10G_KX4 14 1642 #define main0_actualSpeeds_dr_10G_KR 15 1643 #define main0_actualSpeeds_dr_5G 16 1644 #define main0_actualSpeeds_dr_6p4G 17 1645 #define main0_actualSpeeds_dr_20G_X4 18 1646 #define main0_actualSpeeds_dr_21G_X4 19 1647 #define main0_actualSpeeds_dr_25G_X4 20 1648 #define main0_actualSpeeds_dr_10G_HiG_DXGXS 21 1649 #define main0_actualSpeeds_dr_10G_DXGXS 22 1650 #define main0_actualSpeeds_dr_10p5G_HiG_DXGXS 23 1651 #define main0_actualSpeeds_dr_10p5G_DXGXS 24 1652 #define main0_actualSpeeds_dr_12p773G_HiG_DXGXS 25 1653 #define main0_actualSpeeds_dr_12p773G_DXGXS 26 1654 #define main0_actualSpeeds_dr_10G_XFI 27 1655 #define main0_actualSpeeds_dr_40G 28 1656 #define main0_actualSpeeds_dr_20G_HiG_DXGXS 29 1657 #define main0_actualSpeeds_dr_20G_DXGXS 30 1658 #define main0_actualSpeeds_dr_10G_SFI 31 1659 #define main0_actualSpeeds_dr_31p5G 32 1660 #define main0_actualSpeeds_dr_32p7G 33 1661 #define main0_actualSpeeds_dr_20G_SCR 34 1662 #define main0_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 1663 #define main0_actualSpeeds_dr_10G_DXGXS_SCR 36 1664 #define main0_actualSpeeds_dr_12G_R2 37 1665 #define main0_actualSpeeds_dr_10G_X2 38 1666 #define main0_actualSpeeds_dr_40G_KR4 39 1667 #define main0_actualSpeeds_dr_40G_CR4 40 1668 #define main0_actualSpeeds_dr_100G_CR10 41 1669 #define main0_actualSpeeds_dr_15p75G_DXGXS 44 1670 #define main0_actualSpeeds_dr_20G_KR2 57 1671 #define main0_actualSpeeds_dr_20G_CR2 58 1672 1673 /**************************************************************************** 1674 * Enums: main0_actualSpeedsMisc1 1675 */ 1676 #define main0_actualSpeedsMisc1_dr_2500BRCM_X1 16 1677 #define main0_actualSpeedsMisc1_dr_5000BRCM_X4 17 1678 #define main0_actualSpeedsMisc1_dr_6000BRCM_X4 18 1679 #define main0_actualSpeedsMisc1_dr_10GHiGig_X4 19 1680 #define main0_actualSpeedsMisc1_dr_10GBASE_CX4 20 1681 #define main0_actualSpeedsMisc1_dr_12GHiGig_X4 21 1682 #define main0_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 1683 #define main0_actualSpeedsMisc1_dr_13GHiGig_X4 23 1684 #define main0_actualSpeedsMisc1_dr_15GHiGig_X4 24 1685 #define main0_actualSpeedsMisc1_dr_16GHiGig_X4 25 1686 #define main0_actualSpeedsMisc1_dr_5000BRCM_X1 26 1687 #define main0_actualSpeedsMisc1_dr_6363BRCM_X1 27 1688 #define main0_actualSpeedsMisc1_dr_20GHiGig_X4 28 1689 #define main0_actualSpeedsMisc1_dr_21GHiGig_X4 29 1690 #define main0_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 1691 #define main0_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 1692 1693 /**************************************************************************** 1694 * Enums: main0_IndLaneModes 1695 */ 1696 #define main0_IndLaneModes_SWSDR_div2 0 1697 #define main0_IndLaneModes_SWSDR_div1 1 1698 #define main0_IndLaneModes_DWSDR_div2 2 1699 #define main0_IndLaneModes_DWSDR_div1 3 1700 1701 /**************************************************************************** 1702 * Enums: main0_prbsSelect 1703 */ 1704 #define main0_prbsSelect_prbs7 0 1705 #define main0_prbsSelect_prbs15 1 1706 #define main0_prbsSelect_prbs23 2 1707 #define main0_prbsSelect_prbs31 3 1708 1709 /**************************************************************************** 1710 * Enums: main0_vcoDivider 1711 */ 1712 #define main0_vcoDivider_div32 0 1713 #define main0_vcoDivider_div36 1 1714 #define main0_vcoDivider_div40 2 1715 #define main0_vcoDivider_div42 3 1716 #define main0_vcoDivider_div48 4 1717 #define main0_vcoDivider_div50 5 1718 #define main0_vcoDivider_div52 6 1719 #define main0_vcoDivider_div54 7 1720 #define main0_vcoDivider_div60 8 1721 #define main0_vcoDivider_div64 9 1722 #define main0_vcoDivider_div66 10 1723 #define main0_vcoDivider_div68 11 1724 #define main0_vcoDivider_div70 12 1725 #define main0_vcoDivider_div80 13 1726 #define main0_vcoDivider_div92 14 1727 #define main0_vcoDivider_div100 15 1728 1729 /**************************************************************************** 1730 * Enums: main0_refClkSelect 1731 */ 1732 #define main0_refClkSelect_clk_25MHz 0 1733 #define main0_refClkSelect_clk_100MHz 1 1734 #define main0_refClkSelect_clk_125MHz 2 1735 #define main0_refClkSelect_clk_156p25MHz 3 1736 #define main0_refClkSelect_clk_187p5MHz 4 1737 #define main0_refClkSelect_clk_161p25Mhz 5 1738 #define main0_refClkSelect_clk_50Mhz 6 1739 #define main0_refClkSelect_clk_106p25Mhz 7 1740 1741 /**************************************************************************** 1742 * Enums: main0_aerMMDdevTypeSelect 1743 */ 1744 #define main0_aerMMDdevTypeSelect_combo_core 0 1745 #define main0_aerMMDdevTypeSelect_PMA_PMD 1 1746 #define main0_aerMMDdevTypeSelect_PCS 3 1747 #define main0_aerMMDdevTypeSelect_PHY 4 1748 #define main0_aerMMDdevTypeSelect_DTE 5 1749 #define main0_aerMMDdevTypeSelect_CL73_AN 7 1750 1751 /**************************************************************************** 1752 * Enums: main0_aerMMDportSelect 1753 */ 1754 #define main0_aerMMDportSelect_ln0 0 1755 #define main0_aerMMDportSelect_ln1 1 1756 #define main0_aerMMDportSelect_ln2 2 1757 #define main0_aerMMDportSelect_ln3 3 1758 #define main0_aerMMDportSelect_BCST_ln0_1_2_3 511 1759 #define main0_aerMMDportSelect_BCST_ln0_1 512 1760 #define main0_aerMMDportSelect_BCST_ln2_3 513 1761 1762 /**************************************************************************** 1763 * Enums: main0_firmwareModeSelect 1764 */ 1765 #define main0_firmwareModeSelect_DEFAULT 0 1766 #define main0_firmwareModeSelect_SFP_OPT_LR 1 1767 #define main0_firmwareModeSelect_SFP_DAC 2 1768 #define main0_firmwareModeSelect_XLAUI 3 1769 #define main0_firmwareModeSelect_LONG_CH_6G 4 1770 1771 /**************************************************************************** 1772 * Enums: main0_tempIdxSelect 1773 */ 1774 #define main0_tempIdxSelect_LTE__22p9C 15 1775 #define main0_tempIdxSelect_LTE__12p6C 14 1776 #define main0_tempIdxSelect_LTE__3p0C 13 1777 #define main0_tempIdxSelect_LTE_6p7C 12 1778 #define main0_tempIdxSelect_LTE_16p4C 11 1779 #define main0_tempIdxSelect_LTE_26p6C 10 1780 #define main0_tempIdxSelect_LTE_36p3C 9 1781 #define main0_tempIdxSelect_LTE_46p0C 8 1782 #define main0_tempIdxSelect_LTE_56p2C 7 1783 #define main0_tempIdxSelect_LTE_65p9C 6 1784 #define main0_tempIdxSelect_LTE_75p6C 5 1785 #define main0_tempIdxSelect_LTE_85p3C 4 1786 #define main0_tempIdxSelect_LTE_95p5C 3 1787 #define main0_tempIdxSelect_LTE_105p2C 2 1788 #define main0_tempIdxSelect_LTE_114p9C 1 1789 #define main0_tempIdxSelect_LTE_125p1C 0 1790 1791 /**************************************************************************** 1792 * Enums: misc_cl36TxEEEStates_l 1793 */ 1794 #define misc_cl36TxEEEStates_l_TX_REFRESH 8 1795 #define misc_cl36TxEEEStates_l_TX_QUIET 4 1796 #define misc_cl36TxEEEStates_l_TX_SLEEP 2 1797 #define misc_cl36TxEEEStates_l_TX_ACTIVE 1 1798 1799 /**************************************************************************** 1800 * Enums: misc_cl36TxEEEStates_c 1801 */ 1802 #define misc_cl36TxEEEStates_c_TX_REFRESH 3 1803 #define misc_cl36TxEEEStates_c_TX_QUIET 2 1804 #define misc_cl36TxEEEStates_c_TX_SLEEP 1 1805 #define misc_cl36TxEEEStates_c_TX_ACTIVE 0 1806 1807 /**************************************************************************** 1808 * Enums: misc_cl49TxEEEStates_l 1809 */ 1810 #define misc_cl49TxEEEStates_l_SCR_RESET_2 64 1811 #define misc_cl49TxEEEStates_l_SCR_RESET_1 32 1812 #define misc_cl49TxEEEStates_l_TX_WAKE 16 1813 #define misc_cl49TxEEEStates_l_TX_REFRESH 8 1814 #define misc_cl49TxEEEStates_l_TX_QUIET 4 1815 #define misc_cl49TxEEEStates_l_TX_SLEEP 2 1816 #define misc_cl49TxEEEStates_l_TX_ACTIVE 1 1817 1818 /**************************************************************************** 1819 * Enums: misc_cl49TxEEEStates_c 1820 */ 1821 #define misc_cl49TxEEEStates_c_SCR_RESET_2 6 1822 #define misc_cl49TxEEEStates_c_SCR_RESET_1 5 1823 #define misc_cl49TxEEEStates_c_TX_WAKE 4 1824 #define misc_cl49TxEEEStates_c_TX_REFRESH 3 1825 #define misc_cl49TxEEEStates_c_TX_QUIET 2 1826 #define misc_cl49TxEEEStates_c_TX_SLEEP 1 1827 #define misc_cl49TxEEEStates_c_TX_ACTIVE 0 1828 1829 /**************************************************************************** 1830 * Enums: misc_cl36RxEEEStates_l 1831 */ 1832 #define misc_cl36RxEEEStates_l_RX_LINK_FAIL 32 1833 #define misc_cl36RxEEEStates_l_RX_WTF 16 1834 #define misc_cl36RxEEEStates_l_RX_WAKE 8 1835 #define misc_cl36RxEEEStates_l_RX_QUIET 4 1836 #define misc_cl36RxEEEStates_l_RX_SLEEP 2 1837 #define misc_cl36RxEEEStates_l_RX_ACTIVE 1 1838 1839 /**************************************************************************** 1840 * Enums: misc_cl36RxEEEStates_c 1841 */ 1842 #define misc_cl36RxEEEStates_c_RX_LINK_FAIL 5 1843 #define misc_cl36RxEEEStates_c_RX_WTF 4 1844 #define misc_cl36RxEEEStates_c_RX_WAKE 3 1845 #define misc_cl36RxEEEStates_c_RX_QUIET 2 1846 #define misc_cl36RxEEEStates_c_RX_SLEEP 1 1847 #define misc_cl36RxEEEStates_c_RX_ACTIVE 0 1848 1849 /**************************************************************************** 1850 * Enums: misc_cl49RxEEEStates_l 1851 */ 1852 #define misc_cl49RxEEEStates_l_RX_LINK_FAIL 32 1853 #define misc_cl49RxEEEStates_l_RX_WTF 16 1854 #define misc_cl49RxEEEStates_l_RX_WAKE 8 1855 #define misc_cl49RxEEEStates_l_RX_QUIET 4 1856 #define misc_cl49RxEEEStates_l_RX_SLEEP 2 1857 #define misc_cl49RxEEEStates_l_RX_ACTIVE 1 1858 1859 /**************************************************************************** 1860 * Enums: misc_cl49RxEEEStates_c 1861 */ 1862 #define misc_cl49RxEEEStates_c_RX_LINK_FAIL 5 1863 #define misc_cl49RxEEEStates_c_RX_WTF 4 1864 #define misc_cl49RxEEEStates_c_RX_WAKE 3 1865 #define misc_cl49RxEEEStates_c_RX_QUIET 2 1866 #define misc_cl49RxEEEStates_c_RX_SLEEP 1 1867 #define misc_cl49RxEEEStates_c_RX_ACTIVE 0 1868 1869 /**************************************************************************** 1870 * Enums: misc_cl48TxEEEStates_l 1871 */ 1872 #define misc_cl48TxEEEStates_l_TX_REFRESH 8 1873 #define misc_cl48TxEEEStates_l_TX_QUIET 4 1874 #define misc_cl48TxEEEStates_l_TX_SLEEP 2 1875 #define misc_cl48TxEEEStates_l_TX_ACTIVE 1 1876 1877 /**************************************************************************** 1878 * Enums: misc_cl48TxEEEStates_c 1879 */ 1880 #define misc_cl48TxEEEStates_c_TX_REFRESH 3 1881 #define misc_cl48TxEEEStates_c_TX_QUIET 2 1882 #define misc_cl48TxEEEStates_c_TX_SLEEP 1 1883 #define misc_cl48TxEEEStates_c_TX_ACTIVE 0 1884 1885 /**************************************************************************** 1886 * Enums: misc_cl48RxEEEStates_l 1887 */ 1888 #define misc_cl48RxEEEStates_l_RX_LINK_FAIL 32 1889 #define misc_cl48RxEEEStates_l_RX_WAKE 16 1890 #define misc_cl48RxEEEStates_l_RX_QUIET 8 1891 #define misc_cl48RxEEEStates_l_RX_DEACT 4 1892 #define misc_cl48RxEEEStates_l_RX_SLEEP 2 1893 #define misc_cl48RxEEEStates_l_RX_ACTIVE 1 1894 1895 /**************************************************************************** 1896 * Enums: misc_cl48RxEEEStates_c 1897 */ 1898 #define misc_cl48RxEEEStates_c_RX_LINK_FAIL 5 1899 #define misc_cl48RxEEEStates_c_RX_WAKE 4 1900 #define misc_cl48RxEEEStates_c_RX_QUIET 3 1901 #define misc_cl48RxEEEStates_c_RX_DEACT 2 1902 #define misc_cl48RxEEEStates_c_RX_SLEEP 1 1903 #define misc_cl48RxEEEStates_c_RX_ACTIVE 0 1904 1905 /**************************************************************************** 1906 * Enums: misc_IQP_Options 1907 */ 1908 #define misc_IQP_Options_i50uA 0 1909 #define misc_IQP_Options_i100uA 1 1910 #define misc_IQP_Options_i150uA 2 1911 #define misc_IQP_Options_i200uA 3 1912 #define misc_IQP_Options_i250uA 4 1913 #define misc_IQP_Options_i300uA 5 1914 #define misc_IQP_Options_i350uA 6 1915 #define misc_IQP_Options_i400uA 7 1916 #define misc_IQP_Options_i450uA 8 1917 #define misc_IQP_Options_i500uA 9 1918 #define misc_IQP_Options_i550uA 10 1919 #define misc_IQP_Options_i600uA 11 1920 #define misc_IQP_Options_i650uA 12 1921 #define misc_IQP_Options_i700uA 13 1922 #define misc_IQP_Options_i750uA 14 1923 #define misc_IQP_Options_i800uA 15 1924 1925 /**************************************************************************** 1926 * Enums: misc_IDriver_Options 1927 */ 1928 #define misc_IDriver_Options_v680mV 0 1929 #define misc_IDriver_Options_v730mV 1 1930 #define misc_IDriver_Options_v780mV 2 1931 #define misc_IDriver_Options_v830mV 3 1932 #define misc_IDriver_Options_v880mV 4 1933 #define misc_IDriver_Options_v930mV 5 1934 #define misc_IDriver_Options_v980mV 6 1935 #define misc_IDriver_Options_v1010mV 7 1936 #define misc_IDriver_Options_v1040mV 8 1937 #define misc_IDriver_Options_v1060mV 9 1938 #define misc_IDriver_Options_v1070mV 10 1939 #define misc_IDriver_Options_v1080mV 11 1940 #define misc_IDriver_Options_v1085mV 12 1941 #define misc_IDriver_Options_v1090mV 13 1942 #define misc_IDriver_Options_v1095mV 14 1943 #define misc_IDriver_Options_v1100mV 15 1944 1945 /**************************************************************************** 1946 * Enums: misc_operationModes 1947 */ 1948 #define misc_operationModes_XGXS 0 1949 #define misc_operationModes_XGXG_nCC 1 1950 #define misc_operationModes_Indlane_OS8 4 1951 #define misc_operationModes_IndLane_OS5 5 1952 #define misc_operationModes_PCI 7 1953 #define misc_operationModes_XGXS_nLQ 8 1954 #define misc_operationModes_XGXS_nLQnCC 9 1955 #define misc_operationModes_PBypass 10 1956 #define misc_operationModes_PBypass_nDSK 11 1957 #define misc_operationModes_ComboCoreMode 12 1958 #define misc_operationModes_Clocks_off 15 1959 1960 /**************************************************************************** 1961 * Enums: misc_synce_enum 1962 */ 1963 #define misc_synce_enum_SYNCE_NO_DIV 0 1964 #define misc_synce_enum_SYNCE_DIV_7 1 1965 #define misc_synce_enum_SYNCE_DIV_11 2 1966 1967 /**************************************************************************** 1968 * Enums: misc_operationSpeeds 1969 */ 1970 #define misc_operationSpeeds_SPEED_2p5G_X1_10p3125 56 1971 #define misc_operationSpeeds_SPEED_1000M_10p3125 55 1972 #define misc_operationSpeeds_SPEED_100M_10p3125 54 1973 #define misc_operationSpeeds_SPEED_10M_10p3125 53 1974 #define misc_operationSpeeds_SPEED_10p5G_X4 50 1975 #define misc_operationSpeeds_SPEED_5G_KR1 49 1976 #define misc_operationSpeeds_SPEED_127G_X12 39 1977 #define misc_operationSpeeds_SPEED_120G_X12 38 1978 #define misc_operationSpeeds_SPEED_107G_X10 37 1979 #define misc_operationSpeeds_SPEED_100G_CR10 36 1980 #define misc_operationSpeeds_SPEED_42G_X4 35 1981 #define misc_operationSpeeds_SPEED_40G_CR4 34 1982 #define misc_operationSpeeds_SPEED_40G_KR4 33 1983 #define misc_operationSpeeds_SPEED_21G_X2 32 1984 #define misc_operationSpeeds_SPEED_20G_CR2 31 1985 #define misc_operationSpeeds_SPEED_20G_KR2 30 1986 #define misc_operationSpeeds_SPEED_10p6_X1 29 1987 #define misc_operationSpeeds_SPEED_10G_KR1 28 1988 #define misc_operationSpeeds_SPEED_40G_X4 27 1989 #define misc_operationSpeeds_SPEED_20G_X2 26 1990 #define misc_operationSpeeds_SPEED_20G_CX2 25 1991 #define misc_operationSpeeds_SPEED_31p5G_KR4 24 1992 #define misc_operationSpeeds_SPEED_31p5G_X4 23 1993 #define misc_operationSpeeds_SPEED_15p75G_X2 22 1994 #define misc_operationSpeeds_SPEED_25p45G_X4 21 1995 #define misc_operationSpeeds_SPEED_12p7G_X2 20 1996 #define misc_operationSpeeds_SPEED_21G_X4 19 1997 #define misc_operationSpeeds_SPEED_10p5G_X2 18 1998 #define misc_operationSpeeds_SPEED_20G_X4 17 1999 #define misc_operationSpeeds_SPEED_10G_X2 16 2000 #define misc_operationSpeeds_SPEED_10G_CX2 15 2001 #define misc_operationSpeeds_SPEED_20G_CX4 14 2002 #define misc_operationSpeeds_SPEED_16G_X4 13 2003 #define misc_operationSpeeds_SPEED_15G_X4 12 2004 #define misc_operationSpeeds_SPEED_13G_X4 11 2005 #define misc_operationSpeeds_SPEED_10G_X4 10 2006 #define misc_operationSpeeds_SPEED_10G_KX4 9 2007 #define misc_operationSpeeds_SPEED_10G_CX4 8 2008 #define misc_operationSpeeds_SPEED_5G_X1 7 2009 #define misc_operationSpeeds_SPEED_2p5G_X1 6 2010 #define misc_operationSpeeds_SPEED_1G_KX1 5 2011 #define misc_operationSpeeds_SPEED_1G_CX1 4 2012 #define misc_operationSpeeds_SPEED_1000M 3 2013 #define misc_operationSpeeds_SPEED_100M 2 2014 #define misc_operationSpeeds_SPEED_10M 1 2015 2016 /**************************************************************************** 2017 * Enums: misc_actualSpeeds 2018 */ 2019 #define misc_actualSpeeds_dr_10M 0 2020 #define misc_actualSpeeds_dr_100M 1 2021 #define misc_actualSpeeds_dr_1G 2 2022 #define misc_actualSpeeds_dr_2p5G 3 2023 #define misc_actualSpeeds_dr_5G_X4 4 2024 #define misc_actualSpeeds_dr_6G_X4 5 2025 #define misc_actualSpeeds_dr_10G_HiG 6 2026 #define misc_actualSpeeds_dr_10G_CX4 7 2027 #define misc_actualSpeeds_dr_12G_HiG 8 2028 #define misc_actualSpeeds_dr_12p5G_X4 9 2029 #define misc_actualSpeeds_dr_13G_X4 10 2030 #define misc_actualSpeeds_dr_15G_X4 11 2031 #define misc_actualSpeeds_dr_16G_X4 12 2032 #define misc_actualSpeeds_dr_1G_KX 13 2033 #define misc_actualSpeeds_dr_10G_KX4 14 2034 #define misc_actualSpeeds_dr_10G_KR 15 2035 #define misc_actualSpeeds_dr_5G 16 2036 #define misc_actualSpeeds_dr_6p4G 17 2037 #define misc_actualSpeeds_dr_20G_X4 18 2038 #define misc_actualSpeeds_dr_21G_X4 19 2039 #define misc_actualSpeeds_dr_25G_X4 20 2040 #define misc_actualSpeeds_dr_10G_HiG_DXGXS 21 2041 #define misc_actualSpeeds_dr_10G_DXGXS 22 2042 #define misc_actualSpeeds_dr_10p5G_HiG_DXGXS 23 2043 #define misc_actualSpeeds_dr_10p5G_DXGXS 24 2044 #define misc_actualSpeeds_dr_12p773G_HiG_DXGXS 25 2045 #define misc_actualSpeeds_dr_12p773G_DXGXS 26 2046 #define misc_actualSpeeds_dr_10G_XFI 27 2047 #define misc_actualSpeeds_dr_40G 28 2048 #define misc_actualSpeeds_dr_20G_HiG_DXGXS 29 2049 #define misc_actualSpeeds_dr_20G_DXGXS 30 2050 #define misc_actualSpeeds_dr_10G_SFI 31 2051 #define misc_actualSpeeds_dr_31p5G 32 2052 #define misc_actualSpeeds_dr_32p7G 33 2053 #define misc_actualSpeeds_dr_20G_SCR 34 2054 #define misc_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 2055 #define misc_actualSpeeds_dr_10G_DXGXS_SCR 36 2056 #define misc_actualSpeeds_dr_12G_R2 37 2057 #define misc_actualSpeeds_dr_10G_X2 38 2058 #define misc_actualSpeeds_dr_40G_KR4 39 2059 #define misc_actualSpeeds_dr_40G_CR4 40 2060 #define misc_actualSpeeds_dr_100G_CR10 41 2061 #define misc_actualSpeeds_dr_15p75G_DXGXS 44 2062 #define misc_actualSpeeds_dr_20G_KR2 57 2063 #define misc_actualSpeeds_dr_20G_CR2 58 2064 2065 /**************************************************************************** 2066 * Enums: misc_actualSpeedsMisc1 2067 */ 2068 #define misc_actualSpeedsMisc1_dr_2500BRCM_X1 16 2069 #define misc_actualSpeedsMisc1_dr_5000BRCM_X4 17 2070 #define misc_actualSpeedsMisc1_dr_6000BRCM_X4 18 2071 #define misc_actualSpeedsMisc1_dr_10GHiGig_X4 19 2072 #define misc_actualSpeedsMisc1_dr_10GBASE_CX4 20 2073 #define misc_actualSpeedsMisc1_dr_12GHiGig_X4 21 2074 #define misc_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 2075 #define misc_actualSpeedsMisc1_dr_13GHiGig_X4 23 2076 #define misc_actualSpeedsMisc1_dr_15GHiGig_X4 24 2077 #define misc_actualSpeedsMisc1_dr_16GHiGig_X4 25 2078 #define misc_actualSpeedsMisc1_dr_5000BRCM_X1 26 2079 #define misc_actualSpeedsMisc1_dr_6363BRCM_X1 27 2080 #define misc_actualSpeedsMisc1_dr_20GHiGig_X4 28 2081 #define misc_actualSpeedsMisc1_dr_21GHiGig_X4 29 2082 #define misc_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 2083 #define misc_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 2084 2085 /**************************************************************************** 2086 * Enums: misc_IndLaneModes 2087 */ 2088 #define misc_IndLaneModes_SWSDR_div2 0 2089 #define misc_IndLaneModes_SWSDR_div1 1 2090 #define misc_IndLaneModes_DWSDR_div2 2 2091 #define misc_IndLaneModes_DWSDR_div1 3 2092 2093 /**************************************************************************** 2094 * Enums: misc_prbsSelect 2095 */ 2096 #define misc_prbsSelect_prbs7 0 2097 #define misc_prbsSelect_prbs15 1 2098 #define misc_prbsSelect_prbs23 2 2099 #define misc_prbsSelect_prbs31 3 2100 2101 /**************************************************************************** 2102 * Enums: misc_vcoDivider 2103 */ 2104 #define misc_vcoDivider_div32 0 2105 #define misc_vcoDivider_div36 1 2106 #define misc_vcoDivider_div40 2 2107 #define misc_vcoDivider_div42 3 2108 #define misc_vcoDivider_div48 4 2109 #define misc_vcoDivider_div50 5 2110 #define misc_vcoDivider_div52 6 2111 #define misc_vcoDivider_div54 7 2112 #define misc_vcoDivider_div60 8 2113 #define misc_vcoDivider_div64 9 2114 #define misc_vcoDivider_div66 10 2115 #define misc_vcoDivider_div68 11 2116 #define misc_vcoDivider_div70 12 2117 #define misc_vcoDivider_div80 13 2118 #define misc_vcoDivider_div92 14 2119 #define misc_vcoDivider_div100 15 2120 2121 /**************************************************************************** 2122 * Enums: misc_refClkSelect 2123 */ 2124 #define misc_refClkSelect_clk_25MHz 0 2125 #define misc_refClkSelect_clk_100MHz 1 2126 #define misc_refClkSelect_clk_125MHz 2 2127 #define misc_refClkSelect_clk_156p25MHz 3 2128 #define misc_refClkSelect_clk_187p5MHz 4 2129 #define misc_refClkSelect_clk_161p25Mhz 5 2130 #define misc_refClkSelect_clk_50Mhz 6 2131 #define misc_refClkSelect_clk_106p25Mhz 7 2132 2133 /**************************************************************************** 2134 * Enums: misc_aerMMDdevTypeSelect 2135 */ 2136 #define misc_aerMMDdevTypeSelect_combo_core 0 2137 #define misc_aerMMDdevTypeSelect_PMA_PMD 1 2138 #define misc_aerMMDdevTypeSelect_PCS 3 2139 #define misc_aerMMDdevTypeSelect_PHY 4 2140 #define misc_aerMMDdevTypeSelect_DTE 5 2141 #define misc_aerMMDdevTypeSelect_CL73_AN 7 2142 2143 /**************************************************************************** 2144 * Enums: misc_aerMMDportSelect 2145 */ 2146 #define misc_aerMMDportSelect_ln0 0 2147 #define misc_aerMMDportSelect_ln1 1 2148 #define misc_aerMMDportSelect_ln2 2 2149 #define misc_aerMMDportSelect_ln3 3 2150 #define misc_aerMMDportSelect_BCST_ln0_1_2_3 511 2151 #define misc_aerMMDportSelect_BCST_ln0_1 512 2152 #define misc_aerMMDportSelect_BCST_ln2_3 513 2153 2154 /**************************************************************************** 2155 * Enums: misc_firmwareModeSelect 2156 */ 2157 #define misc_firmwareModeSelect_DEFAULT 0 2158 #define misc_firmwareModeSelect_SFP_OPT_LR 1 2159 #define misc_firmwareModeSelect_SFP_DAC 2 2160 #define misc_firmwareModeSelect_XLAUI 3 2161 #define misc_firmwareModeSelect_LONG_CH_6G 4 2162 2163 /**************************************************************************** 2164 * Enums: misc_tempIdxSelect 2165 */ 2166 #define misc_tempIdxSelect_LTE__22p9C 15 2167 #define misc_tempIdxSelect_LTE__12p6C 14 2168 #define misc_tempIdxSelect_LTE__3p0C 13 2169 #define misc_tempIdxSelect_LTE_6p7C 12 2170 #define misc_tempIdxSelect_LTE_16p4C 11 2171 #define misc_tempIdxSelect_LTE_26p6C 10 2172 #define misc_tempIdxSelect_LTE_36p3C 9 2173 #define misc_tempIdxSelect_LTE_46p0C 8 2174 #define misc_tempIdxSelect_LTE_56p2C 7 2175 #define misc_tempIdxSelect_LTE_65p9C 6 2176 #define misc_tempIdxSelect_LTE_75p6C 5 2177 #define misc_tempIdxSelect_LTE_85p3C 4 2178 #define misc_tempIdxSelect_LTE_95p5C 3 2179 #define misc_tempIdxSelect_LTE_105p2C 2 2180 #define misc_tempIdxSelect_LTE_114p9C 1 2181 #define misc_tempIdxSelect_LTE_125p1C 0 2182 2183 /**************************************************************************** 2184 * Enums: sc_x1_speed_override0_cl36TxEEEStates_l 2185 */ 2186 #define sc_x1_speed_override0_cl36TxEEEStates_l_TX_REFRESH 8 2187 #define sc_x1_speed_override0_cl36TxEEEStates_l_TX_QUIET 4 2188 #define sc_x1_speed_override0_cl36TxEEEStates_l_TX_SLEEP 2 2189 #define sc_x1_speed_override0_cl36TxEEEStates_l_TX_ACTIVE 1 2190 2191 /**************************************************************************** 2192 * Enums: sc_x1_speed_override0_cl36TxEEEStates_c 2193 */ 2194 #define sc_x1_speed_override0_cl36TxEEEStates_c_TX_REFRESH 3 2195 #define sc_x1_speed_override0_cl36TxEEEStates_c_TX_QUIET 2 2196 #define sc_x1_speed_override0_cl36TxEEEStates_c_TX_SLEEP 1 2197 #define sc_x1_speed_override0_cl36TxEEEStates_c_TX_ACTIVE 0 2198 2199 /**************************************************************************** 2200 * Enums: sc_x1_speed_override0_cl49TxEEEStates_l 2201 */ 2202 #define sc_x1_speed_override0_cl49TxEEEStates_l_SCR_RESET_2 64 2203 #define sc_x1_speed_override0_cl49TxEEEStates_l_SCR_RESET_1 32 2204 #define sc_x1_speed_override0_cl49TxEEEStates_l_TX_WAKE 16 2205 #define sc_x1_speed_override0_cl49TxEEEStates_l_TX_REFRESH 8 2206 #define sc_x1_speed_override0_cl49TxEEEStates_l_TX_QUIET 4 2207 #define sc_x1_speed_override0_cl49TxEEEStates_l_TX_SLEEP 2 2208 #define sc_x1_speed_override0_cl49TxEEEStates_l_TX_ACTIVE 1 2209 2210 /**************************************************************************** 2211 * Enums: sc_x1_speed_override0_cl49TxEEEStates_c 2212 */ 2213 #define sc_x1_speed_override0_cl49TxEEEStates_c_SCR_RESET_2 6 2214 #define sc_x1_speed_override0_cl49TxEEEStates_c_SCR_RESET_1 5 2215 #define sc_x1_speed_override0_cl49TxEEEStates_c_TX_WAKE 4 2216 #define sc_x1_speed_override0_cl49TxEEEStates_c_TX_REFRESH 3 2217 #define sc_x1_speed_override0_cl49TxEEEStates_c_TX_QUIET 2 2218 #define sc_x1_speed_override0_cl49TxEEEStates_c_TX_SLEEP 1 2219 #define sc_x1_speed_override0_cl49TxEEEStates_c_TX_ACTIVE 0 2220 2221 /**************************************************************************** 2222 * Enums: sc_x1_speed_override0_cl36RxEEEStates_l 2223 */ 2224 #define sc_x1_speed_override0_cl36RxEEEStates_l_RX_LINK_FAIL 32 2225 #define sc_x1_speed_override0_cl36RxEEEStates_l_RX_WTF 16 2226 #define sc_x1_speed_override0_cl36RxEEEStates_l_RX_WAKE 8 2227 #define sc_x1_speed_override0_cl36RxEEEStates_l_RX_QUIET 4 2228 #define sc_x1_speed_override0_cl36RxEEEStates_l_RX_SLEEP 2 2229 #define sc_x1_speed_override0_cl36RxEEEStates_l_RX_ACTIVE 1 2230 2231 /**************************************************************************** 2232 * Enums: sc_x1_speed_override0_cl36RxEEEStates_c 2233 */ 2234 #define sc_x1_speed_override0_cl36RxEEEStates_c_RX_LINK_FAIL 5 2235 #define sc_x1_speed_override0_cl36RxEEEStates_c_RX_WTF 4 2236 #define sc_x1_speed_override0_cl36RxEEEStates_c_RX_WAKE 3 2237 #define sc_x1_speed_override0_cl36RxEEEStates_c_RX_QUIET 2 2238 #define sc_x1_speed_override0_cl36RxEEEStates_c_RX_SLEEP 1 2239 #define sc_x1_speed_override0_cl36RxEEEStates_c_RX_ACTIVE 0 2240 2241 /**************************************************************************** 2242 * Enums: sc_x1_speed_override0_cl49RxEEEStates_l 2243 */ 2244 #define sc_x1_speed_override0_cl49RxEEEStates_l_RX_LINK_FAIL 32 2245 #define sc_x1_speed_override0_cl49RxEEEStates_l_RX_WTF 16 2246 #define sc_x1_speed_override0_cl49RxEEEStates_l_RX_WAKE 8 2247 #define sc_x1_speed_override0_cl49RxEEEStates_l_RX_QUIET 4 2248 #define sc_x1_speed_override0_cl49RxEEEStates_l_RX_SLEEP 2 2249 #define sc_x1_speed_override0_cl49RxEEEStates_l_RX_ACTIVE 1 2250 2251 /**************************************************************************** 2252 * Enums: sc_x1_speed_override0_cl49RxEEEStates_c 2253 */ 2254 #define sc_x1_speed_override0_cl49RxEEEStates_c_RX_LINK_FAIL 5 2255 #define sc_x1_speed_override0_cl49RxEEEStates_c_RX_WTF 4 2256 #define sc_x1_speed_override0_cl49RxEEEStates_c_RX_WAKE 3 2257 #define sc_x1_speed_override0_cl49RxEEEStates_c_RX_QUIET 2 2258 #define sc_x1_speed_override0_cl49RxEEEStates_c_RX_SLEEP 1 2259 #define sc_x1_speed_override0_cl49RxEEEStates_c_RX_ACTIVE 0 2260 2261 /**************************************************************************** 2262 * Enums: sc_x1_speed_override0_cl48TxEEEStates_l 2263 */ 2264 #define sc_x1_speed_override0_cl48TxEEEStates_l_TX_REFRESH 8 2265 #define sc_x1_speed_override0_cl48TxEEEStates_l_TX_QUIET 4 2266 #define sc_x1_speed_override0_cl48TxEEEStates_l_TX_SLEEP 2 2267 #define sc_x1_speed_override0_cl48TxEEEStates_l_TX_ACTIVE 1 2268 2269 /**************************************************************************** 2270 * Enums: sc_x1_speed_override0_cl48TxEEEStates_c 2271 */ 2272 #define sc_x1_speed_override0_cl48TxEEEStates_c_TX_REFRESH 3 2273 #define sc_x1_speed_override0_cl48TxEEEStates_c_TX_QUIET 2 2274 #define sc_x1_speed_override0_cl48TxEEEStates_c_TX_SLEEP 1 2275 #define sc_x1_speed_override0_cl48TxEEEStates_c_TX_ACTIVE 0 2276 2277 /**************************************************************************** 2278 * Enums: sc_x1_speed_override0_cl48RxEEEStates_l 2279 */ 2280 #define sc_x1_speed_override0_cl48RxEEEStates_l_RX_LINK_FAIL 32 2281 #define sc_x1_speed_override0_cl48RxEEEStates_l_RX_WAKE 16 2282 #define sc_x1_speed_override0_cl48RxEEEStates_l_RX_QUIET 8 2283 #define sc_x1_speed_override0_cl48RxEEEStates_l_RX_DEACT 4 2284 #define sc_x1_speed_override0_cl48RxEEEStates_l_RX_SLEEP 2 2285 #define sc_x1_speed_override0_cl48RxEEEStates_l_RX_ACTIVE 1 2286 2287 /**************************************************************************** 2288 * Enums: sc_x1_speed_override0_cl48RxEEEStates_c 2289 */ 2290 #define sc_x1_speed_override0_cl48RxEEEStates_c_RX_LINK_FAIL 5 2291 #define sc_x1_speed_override0_cl48RxEEEStates_c_RX_WAKE 4 2292 #define sc_x1_speed_override0_cl48RxEEEStates_c_RX_QUIET 3 2293 #define sc_x1_speed_override0_cl48RxEEEStates_c_RX_DEACT 2 2294 #define sc_x1_speed_override0_cl48RxEEEStates_c_RX_SLEEP 1 2295 #define sc_x1_speed_override0_cl48RxEEEStates_c_RX_ACTIVE 0 2296 2297 /**************************************************************************** 2298 * Enums: sc_x1_speed_override0_IQP_Options 2299 */ 2300 #define sc_x1_speed_override0_IQP_Options_i50uA 0 2301 #define sc_x1_speed_override0_IQP_Options_i100uA 1 2302 #define sc_x1_speed_override0_IQP_Options_i150uA 2 2303 #define sc_x1_speed_override0_IQP_Options_i200uA 3 2304 #define sc_x1_speed_override0_IQP_Options_i250uA 4 2305 #define sc_x1_speed_override0_IQP_Options_i300uA 5 2306 #define sc_x1_speed_override0_IQP_Options_i350uA 6 2307 #define sc_x1_speed_override0_IQP_Options_i400uA 7 2308 #define sc_x1_speed_override0_IQP_Options_i450uA 8 2309 #define sc_x1_speed_override0_IQP_Options_i500uA 9 2310 #define sc_x1_speed_override0_IQP_Options_i550uA 10 2311 #define sc_x1_speed_override0_IQP_Options_i600uA 11 2312 #define sc_x1_speed_override0_IQP_Options_i650uA 12 2313 #define sc_x1_speed_override0_IQP_Options_i700uA 13 2314 #define sc_x1_speed_override0_IQP_Options_i750uA 14 2315 #define sc_x1_speed_override0_IQP_Options_i800uA 15 2316 2317 /**************************************************************************** 2318 * Enums: sc_x1_speed_override0_IDriver_Options 2319 */ 2320 #define sc_x1_speed_override0_IDriver_Options_v680mV 0 2321 #define sc_x1_speed_override0_IDriver_Options_v730mV 1 2322 #define sc_x1_speed_override0_IDriver_Options_v780mV 2 2323 #define sc_x1_speed_override0_IDriver_Options_v830mV 3 2324 #define sc_x1_speed_override0_IDriver_Options_v880mV 4 2325 #define sc_x1_speed_override0_IDriver_Options_v930mV 5 2326 #define sc_x1_speed_override0_IDriver_Options_v980mV 6 2327 #define sc_x1_speed_override0_IDriver_Options_v1010mV 7 2328 #define sc_x1_speed_override0_IDriver_Options_v1040mV 8 2329 #define sc_x1_speed_override0_IDriver_Options_v1060mV 9 2330 #define sc_x1_speed_override0_IDriver_Options_v1070mV 10 2331 #define sc_x1_speed_override0_IDriver_Options_v1080mV 11 2332 #define sc_x1_speed_override0_IDriver_Options_v1085mV 12 2333 #define sc_x1_speed_override0_IDriver_Options_v1090mV 13 2334 #define sc_x1_speed_override0_IDriver_Options_v1095mV 14 2335 #define sc_x1_speed_override0_IDriver_Options_v1100mV 15 2336 2337 /**************************************************************************** 2338 * Enums: sc_x1_speed_override0_operationModes 2339 */ 2340 #define sc_x1_speed_override0_operationModes_XGXS 0 2341 #define sc_x1_speed_override0_operationModes_XGXG_nCC 1 2342 #define sc_x1_speed_override0_operationModes_Indlane_OS8 4 2343 #define sc_x1_speed_override0_operationModes_IndLane_OS5 5 2344 #define sc_x1_speed_override0_operationModes_PCI 7 2345 #define sc_x1_speed_override0_operationModes_XGXS_nLQ 8 2346 #define sc_x1_speed_override0_operationModes_XGXS_nLQnCC 9 2347 #define sc_x1_speed_override0_operationModes_PBypass 10 2348 #define sc_x1_speed_override0_operationModes_PBypass_nDSK 11 2349 #define sc_x1_speed_override0_operationModes_ComboCoreMode 12 2350 #define sc_x1_speed_override0_operationModes_Clocks_off 15 2351 2352 /**************************************************************************** 2353 * Enums: sc_x1_speed_override0_synce_enum 2354 */ 2355 #define sc_x1_speed_override0_synce_enum_SYNCE_NO_DIV 0 2356 #define sc_x1_speed_override0_synce_enum_SYNCE_DIV_7 1 2357 #define sc_x1_speed_override0_synce_enum_SYNCE_DIV_11 2 2358 2359 /**************************************************************************** 2360 * Enums: sc_x1_speed_override0_operationSpeeds 2361 */ 2362 #define sc_x1_speed_override0_operationSpeeds_SPEED_2p5G_X1_10p3125 56 2363 #define sc_x1_speed_override0_operationSpeeds_SPEED_1000M_10p3125 55 2364 #define sc_x1_speed_override0_operationSpeeds_SPEED_100M_10p3125 54 2365 #define sc_x1_speed_override0_operationSpeeds_SPEED_10M_10p3125 53 2366 #define sc_x1_speed_override0_operationSpeeds_SPEED_10p5G_X4 50 2367 #define sc_x1_speed_override0_operationSpeeds_SPEED_5G_KR1 49 2368 #define sc_x1_speed_override0_operationSpeeds_SPEED_127G_X12 39 2369 #define sc_x1_speed_override0_operationSpeeds_SPEED_120G_X12 38 2370 #define sc_x1_speed_override0_operationSpeeds_SPEED_107G_X10 37 2371 #define sc_x1_speed_override0_operationSpeeds_SPEED_100G_CR10 36 2372 #define sc_x1_speed_override0_operationSpeeds_SPEED_42G_X4 35 2373 #define sc_x1_speed_override0_operationSpeeds_SPEED_40G_CR4 34 2374 #define sc_x1_speed_override0_operationSpeeds_SPEED_40G_KR4 33 2375 #define sc_x1_speed_override0_operationSpeeds_SPEED_21G_X2 32 2376 #define sc_x1_speed_override0_operationSpeeds_SPEED_20G_CR2 31 2377 #define sc_x1_speed_override0_operationSpeeds_SPEED_20G_KR2 30 2378 #define sc_x1_speed_override0_operationSpeeds_SPEED_10p6_X1 29 2379 #define sc_x1_speed_override0_operationSpeeds_SPEED_10G_KR1 28 2380 #define sc_x1_speed_override0_operationSpeeds_SPEED_40G_X4 27 2381 #define sc_x1_speed_override0_operationSpeeds_SPEED_20G_X2 26 2382 #define sc_x1_speed_override0_operationSpeeds_SPEED_20G_CX2 25 2383 #define sc_x1_speed_override0_operationSpeeds_SPEED_31p5G_KR4 24 2384 #define sc_x1_speed_override0_operationSpeeds_SPEED_31p5G_X4 23 2385 #define sc_x1_speed_override0_operationSpeeds_SPEED_15p75G_X2 22 2386 #define sc_x1_speed_override0_operationSpeeds_SPEED_25p45G_X4 21 2387 #define sc_x1_speed_override0_operationSpeeds_SPEED_12p7G_X2 20 2388 #define sc_x1_speed_override0_operationSpeeds_SPEED_21G_X4 19 2389 #define sc_x1_speed_override0_operationSpeeds_SPEED_10p5G_X2 18 2390 #define sc_x1_speed_override0_operationSpeeds_SPEED_20G_X4 17 2391 #define sc_x1_speed_override0_operationSpeeds_SPEED_10G_X2 16 2392 #define sc_x1_speed_override0_operationSpeeds_SPEED_10G_CX2 15 2393 #define sc_x1_speed_override0_operationSpeeds_SPEED_20G_CX4 14 2394 #define sc_x1_speed_override0_operationSpeeds_SPEED_16G_X4 13 2395 #define sc_x1_speed_override0_operationSpeeds_SPEED_15G_X4 12 2396 #define sc_x1_speed_override0_operationSpeeds_SPEED_13G_X4 11 2397 #define sc_x1_speed_override0_operationSpeeds_SPEED_10G_X4 10 2398 #define sc_x1_speed_override0_operationSpeeds_SPEED_10G_KX4 9 2399 #define sc_x1_speed_override0_operationSpeeds_SPEED_10G_CX4 8 2400 #define sc_x1_speed_override0_operationSpeeds_SPEED_5G_X1 7 2401 #define sc_x1_speed_override0_operationSpeeds_SPEED_2p5G_X1 6 2402 #define sc_x1_speed_override0_operationSpeeds_SPEED_1G_KX1 5 2403 #define sc_x1_speed_override0_operationSpeeds_SPEED_1G_CX1 4 2404 #define sc_x1_speed_override0_operationSpeeds_SPEED_1000M 3 2405 #define sc_x1_speed_override0_operationSpeeds_SPEED_100M 2 2406 #define sc_x1_speed_override0_operationSpeeds_SPEED_10M 1 2407 2408 /**************************************************************************** 2409 * Enums: sc_x1_speed_override0_actualSpeeds 2410 */ 2411 #define sc_x1_speed_override0_actualSpeeds_dr_10M 0 2412 #define sc_x1_speed_override0_actualSpeeds_dr_100M 1 2413 #define sc_x1_speed_override0_actualSpeeds_dr_1G 2 2414 #define sc_x1_speed_override0_actualSpeeds_dr_2p5G 3 2415 #define sc_x1_speed_override0_actualSpeeds_dr_5G_X4 4 2416 #define sc_x1_speed_override0_actualSpeeds_dr_6G_X4 5 2417 #define sc_x1_speed_override0_actualSpeeds_dr_10G_HiG 6 2418 #define sc_x1_speed_override0_actualSpeeds_dr_10G_CX4 7 2419 #define sc_x1_speed_override0_actualSpeeds_dr_12G_HiG 8 2420 #define sc_x1_speed_override0_actualSpeeds_dr_12p5G_X4 9 2421 #define sc_x1_speed_override0_actualSpeeds_dr_13G_X4 10 2422 #define sc_x1_speed_override0_actualSpeeds_dr_15G_X4 11 2423 #define sc_x1_speed_override0_actualSpeeds_dr_16G_X4 12 2424 #define sc_x1_speed_override0_actualSpeeds_dr_1G_KX 13 2425 #define sc_x1_speed_override0_actualSpeeds_dr_10G_KX4 14 2426 #define sc_x1_speed_override0_actualSpeeds_dr_10G_KR 15 2427 #define sc_x1_speed_override0_actualSpeeds_dr_5G 16 2428 #define sc_x1_speed_override0_actualSpeeds_dr_6p4G 17 2429 #define sc_x1_speed_override0_actualSpeeds_dr_20G_X4 18 2430 #define sc_x1_speed_override0_actualSpeeds_dr_21G_X4 19 2431 #define sc_x1_speed_override0_actualSpeeds_dr_25G_X4 20 2432 #define sc_x1_speed_override0_actualSpeeds_dr_10G_HiG_DXGXS 21 2433 #define sc_x1_speed_override0_actualSpeeds_dr_10G_DXGXS 22 2434 #define sc_x1_speed_override0_actualSpeeds_dr_10p5G_HiG_DXGXS 23 2435 #define sc_x1_speed_override0_actualSpeeds_dr_10p5G_DXGXS 24 2436 #define sc_x1_speed_override0_actualSpeeds_dr_12p773G_HiG_DXGXS 25 2437 #define sc_x1_speed_override0_actualSpeeds_dr_12p773G_DXGXS 26 2438 #define sc_x1_speed_override0_actualSpeeds_dr_10G_XFI 27 2439 #define sc_x1_speed_override0_actualSpeeds_dr_40G 28 2440 #define sc_x1_speed_override0_actualSpeeds_dr_20G_HiG_DXGXS 29 2441 #define sc_x1_speed_override0_actualSpeeds_dr_20G_DXGXS 30 2442 #define sc_x1_speed_override0_actualSpeeds_dr_10G_SFI 31 2443 #define sc_x1_speed_override0_actualSpeeds_dr_31p5G 32 2444 #define sc_x1_speed_override0_actualSpeeds_dr_32p7G 33 2445 #define sc_x1_speed_override0_actualSpeeds_dr_20G_SCR 34 2446 #define sc_x1_speed_override0_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 2447 #define sc_x1_speed_override0_actualSpeeds_dr_10G_DXGXS_SCR 36 2448 #define sc_x1_speed_override0_actualSpeeds_dr_12G_R2 37 2449 #define sc_x1_speed_override0_actualSpeeds_dr_10G_X2 38 2450 #define sc_x1_speed_override0_actualSpeeds_dr_40G_KR4 39 2451 #define sc_x1_speed_override0_actualSpeeds_dr_40G_CR4 40 2452 #define sc_x1_speed_override0_actualSpeeds_dr_100G_CR10 41 2453 #define sc_x1_speed_override0_actualSpeeds_dr_15p75G_DXGXS 44 2454 #define sc_x1_speed_override0_actualSpeeds_dr_20G_KR2 57 2455 #define sc_x1_speed_override0_actualSpeeds_dr_20G_CR2 58 2456 2457 /**************************************************************************** 2458 * Enums: sc_x1_speed_override0_actualSpeedsMisc1 2459 */ 2460 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_2500BRCM_X1 16 2461 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_5000BRCM_X4 17 2462 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_6000BRCM_X4 18 2463 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_10GHiGig_X4 19 2464 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_10GBASE_CX4 20 2465 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_12GHiGig_X4 21 2466 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 2467 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_13GHiGig_X4 23 2468 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_15GHiGig_X4 24 2469 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_16GHiGig_X4 25 2470 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_5000BRCM_X1 26 2471 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_6363BRCM_X1 27 2472 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_20GHiGig_X4 28 2473 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_21GHiGig_X4 29 2474 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 2475 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 2476 2477 /**************************************************************************** 2478 * Enums: sc_x1_speed_override0_IndLaneModes 2479 */ 2480 #define sc_x1_speed_override0_IndLaneModes_SWSDR_div2 0 2481 #define sc_x1_speed_override0_IndLaneModes_SWSDR_div1 1 2482 #define sc_x1_speed_override0_IndLaneModes_DWSDR_div2 2 2483 #define sc_x1_speed_override0_IndLaneModes_DWSDR_div1 3 2484 2485 /**************************************************************************** 2486 * Enums: sc_x1_speed_override0_prbsSelect 2487 */ 2488 #define sc_x1_speed_override0_prbsSelect_prbs7 0 2489 #define sc_x1_speed_override0_prbsSelect_prbs15 1 2490 #define sc_x1_speed_override0_prbsSelect_prbs23 2 2491 #define sc_x1_speed_override0_prbsSelect_prbs31 3 2492 2493 /**************************************************************************** 2494 * Enums: sc_x1_speed_override0_vcoDivider 2495 */ 2496 #define sc_x1_speed_override0_vcoDivider_div32 0 2497 #define sc_x1_speed_override0_vcoDivider_div36 1 2498 #define sc_x1_speed_override0_vcoDivider_div40 2 2499 #define sc_x1_speed_override0_vcoDivider_div42 3 2500 #define sc_x1_speed_override0_vcoDivider_div48 4 2501 #define sc_x1_speed_override0_vcoDivider_div50 5 2502 #define sc_x1_speed_override0_vcoDivider_div52 6 2503 #define sc_x1_speed_override0_vcoDivider_div54 7 2504 #define sc_x1_speed_override0_vcoDivider_div60 8 2505 #define sc_x1_speed_override0_vcoDivider_div64 9 2506 #define sc_x1_speed_override0_vcoDivider_div66 10 2507 #define sc_x1_speed_override0_vcoDivider_div68 11 2508 #define sc_x1_speed_override0_vcoDivider_div70 12 2509 #define sc_x1_speed_override0_vcoDivider_div80 13 2510 #define sc_x1_speed_override0_vcoDivider_div92 14 2511 #define sc_x1_speed_override0_vcoDivider_div100 15 2512 2513 /**************************************************************************** 2514 * Enums: sc_x1_speed_override0_refClkSelect 2515 */ 2516 #define sc_x1_speed_override0_refClkSelect_clk_25MHz 0 2517 #define sc_x1_speed_override0_refClkSelect_clk_100MHz 1 2518 #define sc_x1_speed_override0_refClkSelect_clk_125MHz 2 2519 #define sc_x1_speed_override0_refClkSelect_clk_156p25MHz 3 2520 #define sc_x1_speed_override0_refClkSelect_clk_187p5MHz 4 2521 #define sc_x1_speed_override0_refClkSelect_clk_161p25Mhz 5 2522 #define sc_x1_speed_override0_refClkSelect_clk_50Mhz 6 2523 #define sc_x1_speed_override0_refClkSelect_clk_106p25Mhz 7 2524 2525 /**************************************************************************** 2526 * Enums: sc_x1_speed_override0_aerMMDdevTypeSelect 2527 */ 2528 #define sc_x1_speed_override0_aerMMDdevTypeSelect_combo_core 0 2529 #define sc_x1_speed_override0_aerMMDdevTypeSelect_PMA_PMD 1 2530 #define sc_x1_speed_override0_aerMMDdevTypeSelect_PCS 3 2531 #define sc_x1_speed_override0_aerMMDdevTypeSelect_PHY 4 2532 #define sc_x1_speed_override0_aerMMDdevTypeSelect_DTE 5 2533 #define sc_x1_speed_override0_aerMMDdevTypeSelect_CL73_AN 7 2534 2535 /**************************************************************************** 2536 * Enums: sc_x1_speed_override0_aerMMDportSelect 2537 */ 2538 #define sc_x1_speed_override0_aerMMDportSelect_ln0 0 2539 #define sc_x1_speed_override0_aerMMDportSelect_ln1 1 2540 #define sc_x1_speed_override0_aerMMDportSelect_ln2 2 2541 #define sc_x1_speed_override0_aerMMDportSelect_ln3 3 2542 #define sc_x1_speed_override0_aerMMDportSelect_BCST_ln0_1_2_3 511 2543 #define sc_x1_speed_override0_aerMMDportSelect_BCST_ln0_1 512 2544 #define sc_x1_speed_override0_aerMMDportSelect_BCST_ln2_3 513 2545 2546 /**************************************************************************** 2547 * Enums: sc_x1_speed_override0_firmwareModeSelect 2548 */ 2549 #define sc_x1_speed_override0_firmwareModeSelect_DEFAULT 0 2550 #define sc_x1_speed_override0_firmwareModeSelect_SFP_OPT_LR 1 2551 #define sc_x1_speed_override0_firmwareModeSelect_SFP_DAC 2 2552 #define sc_x1_speed_override0_firmwareModeSelect_XLAUI 3 2553 #define sc_x1_speed_override0_firmwareModeSelect_LONG_CH_6G 4 2554 2555 /**************************************************************************** 2556 * Enums: sc_x1_speed_override0_tempIdxSelect 2557 */ 2558 #define sc_x1_speed_override0_tempIdxSelect_LTE__22p9C 15 2559 #define sc_x1_speed_override0_tempIdxSelect_LTE__12p6C 14 2560 #define sc_x1_speed_override0_tempIdxSelect_LTE__3p0C 13 2561 #define sc_x1_speed_override0_tempIdxSelect_LTE_6p7C 12 2562 #define sc_x1_speed_override0_tempIdxSelect_LTE_16p4C 11 2563 #define sc_x1_speed_override0_tempIdxSelect_LTE_26p6C 10 2564 #define sc_x1_speed_override0_tempIdxSelect_LTE_36p3C 9 2565 #define sc_x1_speed_override0_tempIdxSelect_LTE_46p0C 8 2566 #define sc_x1_speed_override0_tempIdxSelect_LTE_56p2C 7 2567 #define sc_x1_speed_override0_tempIdxSelect_LTE_65p9C 6 2568 #define sc_x1_speed_override0_tempIdxSelect_LTE_75p6C 5 2569 #define sc_x1_speed_override0_tempIdxSelect_LTE_85p3C 4 2570 #define sc_x1_speed_override0_tempIdxSelect_LTE_95p5C 3 2571 #define sc_x1_speed_override0_tempIdxSelect_LTE_105p2C 2 2572 #define sc_x1_speed_override0_tempIdxSelect_LTE_114p9C 1 2573 #define sc_x1_speed_override0_tempIdxSelect_LTE_125p1C 0 2574 2575 /**************************************************************************** 2576 * Enums: sc_x1_speed_override1_cl36TxEEEStates_l 2577 */ 2578 #define sc_x1_speed_override1_cl36TxEEEStates_l_TX_REFRESH 8 2579 #define sc_x1_speed_override1_cl36TxEEEStates_l_TX_QUIET 4 2580 #define sc_x1_speed_override1_cl36TxEEEStates_l_TX_SLEEP 2 2581 #define sc_x1_speed_override1_cl36TxEEEStates_l_TX_ACTIVE 1 2582 2583 /**************************************************************************** 2584 * Enums: sc_x1_speed_override1_cl36TxEEEStates_c 2585 */ 2586 #define sc_x1_speed_override1_cl36TxEEEStates_c_TX_REFRESH 3 2587 #define sc_x1_speed_override1_cl36TxEEEStates_c_TX_QUIET 2 2588 #define sc_x1_speed_override1_cl36TxEEEStates_c_TX_SLEEP 1 2589 #define sc_x1_speed_override1_cl36TxEEEStates_c_TX_ACTIVE 0 2590 2591 /**************************************************************************** 2592 * Enums: sc_x1_speed_override1_cl49TxEEEStates_l 2593 */ 2594 #define sc_x1_speed_override1_cl49TxEEEStates_l_SCR_RESET_2 64 2595 #define sc_x1_speed_override1_cl49TxEEEStates_l_SCR_RESET_1 32 2596 #define sc_x1_speed_override1_cl49TxEEEStates_l_TX_WAKE 16 2597 #define sc_x1_speed_override1_cl49TxEEEStates_l_TX_REFRESH 8 2598 #define sc_x1_speed_override1_cl49TxEEEStates_l_TX_QUIET 4 2599 #define sc_x1_speed_override1_cl49TxEEEStates_l_TX_SLEEP 2 2600 #define sc_x1_speed_override1_cl49TxEEEStates_l_TX_ACTIVE 1 2601 2602 /**************************************************************************** 2603 * Enums: sc_x1_speed_override1_cl49TxEEEStates_c 2604 */ 2605 #define sc_x1_speed_override1_cl49TxEEEStates_c_SCR_RESET_2 6 2606 #define sc_x1_speed_override1_cl49TxEEEStates_c_SCR_RESET_1 5 2607 #define sc_x1_speed_override1_cl49TxEEEStates_c_TX_WAKE 4 2608 #define sc_x1_speed_override1_cl49TxEEEStates_c_TX_REFRESH 3 2609 #define sc_x1_speed_override1_cl49TxEEEStates_c_TX_QUIET 2 2610 #define sc_x1_speed_override1_cl49TxEEEStates_c_TX_SLEEP 1 2611 #define sc_x1_speed_override1_cl49TxEEEStates_c_TX_ACTIVE 0 2612 2613 /**************************************************************************** 2614 * Enums: sc_x1_speed_override1_cl36RxEEEStates_l 2615 */ 2616 #define sc_x1_speed_override1_cl36RxEEEStates_l_RX_LINK_FAIL 32 2617 #define sc_x1_speed_override1_cl36RxEEEStates_l_RX_WTF 16 2618 #define sc_x1_speed_override1_cl36RxEEEStates_l_RX_WAKE 8 2619 #define sc_x1_speed_override1_cl36RxEEEStates_l_RX_QUIET 4 2620 #define sc_x1_speed_override1_cl36RxEEEStates_l_RX_SLEEP 2 2621 #define sc_x1_speed_override1_cl36RxEEEStates_l_RX_ACTIVE 1 2622 2623 /**************************************************************************** 2624 * Enums: sc_x1_speed_override1_cl36RxEEEStates_c 2625 */ 2626 #define sc_x1_speed_override1_cl36RxEEEStates_c_RX_LINK_FAIL 5 2627 #define sc_x1_speed_override1_cl36RxEEEStates_c_RX_WTF 4 2628 #define sc_x1_speed_override1_cl36RxEEEStates_c_RX_WAKE 3 2629 #define sc_x1_speed_override1_cl36RxEEEStates_c_RX_QUIET 2 2630 #define sc_x1_speed_override1_cl36RxEEEStates_c_RX_SLEEP 1 2631 #define sc_x1_speed_override1_cl36RxEEEStates_c_RX_ACTIVE 0 2632 2633 /**************************************************************************** 2634 * Enums: sc_x1_speed_override1_cl49RxEEEStates_l 2635 */ 2636 #define sc_x1_speed_override1_cl49RxEEEStates_l_RX_LINK_FAIL 32 2637 #define sc_x1_speed_override1_cl49RxEEEStates_l_RX_WTF 16 2638 #define sc_x1_speed_override1_cl49RxEEEStates_l_RX_WAKE 8 2639 #define sc_x1_speed_override1_cl49RxEEEStates_l_RX_QUIET 4 2640 #define sc_x1_speed_override1_cl49RxEEEStates_l_RX_SLEEP 2 2641 #define sc_x1_speed_override1_cl49RxEEEStates_l_RX_ACTIVE 1 2642 2643 /**************************************************************************** 2644 * Enums: sc_x1_speed_override1_cl49RxEEEStates_c 2645 */ 2646 #define sc_x1_speed_override1_cl49RxEEEStates_c_RX_LINK_FAIL 5 2647 #define sc_x1_speed_override1_cl49RxEEEStates_c_RX_WTF 4 2648 #define sc_x1_speed_override1_cl49RxEEEStates_c_RX_WAKE 3 2649 #define sc_x1_speed_override1_cl49RxEEEStates_c_RX_QUIET 2 2650 #define sc_x1_speed_override1_cl49RxEEEStates_c_RX_SLEEP 1 2651 #define sc_x1_speed_override1_cl49RxEEEStates_c_RX_ACTIVE 0 2652 2653 /**************************************************************************** 2654 * Enums: sc_x1_speed_override1_cl48TxEEEStates_l 2655 */ 2656 #define sc_x1_speed_override1_cl48TxEEEStates_l_TX_REFRESH 8 2657 #define sc_x1_speed_override1_cl48TxEEEStates_l_TX_QUIET 4 2658 #define sc_x1_speed_override1_cl48TxEEEStates_l_TX_SLEEP 2 2659 #define sc_x1_speed_override1_cl48TxEEEStates_l_TX_ACTIVE 1 2660 2661 /**************************************************************************** 2662 * Enums: sc_x1_speed_override1_cl48TxEEEStates_c 2663 */ 2664 #define sc_x1_speed_override1_cl48TxEEEStates_c_TX_REFRESH 3 2665 #define sc_x1_speed_override1_cl48TxEEEStates_c_TX_QUIET 2 2666 #define sc_x1_speed_override1_cl48TxEEEStates_c_TX_SLEEP 1 2667 #define sc_x1_speed_override1_cl48TxEEEStates_c_TX_ACTIVE 0 2668 2669 /**************************************************************************** 2670 * Enums: sc_x1_speed_override1_cl48RxEEEStates_l 2671 */ 2672 #define sc_x1_speed_override1_cl48RxEEEStates_l_RX_LINK_FAIL 32 2673 #define sc_x1_speed_override1_cl48RxEEEStates_l_RX_WAKE 16 2674 #define sc_x1_speed_override1_cl48RxEEEStates_l_RX_QUIET 8 2675 #define sc_x1_speed_override1_cl48RxEEEStates_l_RX_DEACT 4 2676 #define sc_x1_speed_override1_cl48RxEEEStates_l_RX_SLEEP 2 2677 #define sc_x1_speed_override1_cl48RxEEEStates_l_RX_ACTIVE 1 2678 2679 /**************************************************************************** 2680 * Enums: sc_x1_speed_override1_cl48RxEEEStates_c 2681 */ 2682 #define sc_x1_speed_override1_cl48RxEEEStates_c_RX_LINK_FAIL 5 2683 #define sc_x1_speed_override1_cl48RxEEEStates_c_RX_WAKE 4 2684 #define sc_x1_speed_override1_cl48RxEEEStates_c_RX_QUIET 3 2685 #define sc_x1_speed_override1_cl48RxEEEStates_c_RX_DEACT 2 2686 #define sc_x1_speed_override1_cl48RxEEEStates_c_RX_SLEEP 1 2687 #define sc_x1_speed_override1_cl48RxEEEStates_c_RX_ACTIVE 0 2688 2689 /**************************************************************************** 2690 * Enums: sc_x1_speed_override1_IQP_Options 2691 */ 2692 #define sc_x1_speed_override1_IQP_Options_i50uA 0 2693 #define sc_x1_speed_override1_IQP_Options_i100uA 1 2694 #define sc_x1_speed_override1_IQP_Options_i150uA 2 2695 #define sc_x1_speed_override1_IQP_Options_i200uA 3 2696 #define sc_x1_speed_override1_IQP_Options_i250uA 4 2697 #define sc_x1_speed_override1_IQP_Options_i300uA 5 2698 #define sc_x1_speed_override1_IQP_Options_i350uA 6 2699 #define sc_x1_speed_override1_IQP_Options_i400uA 7 2700 #define sc_x1_speed_override1_IQP_Options_i450uA 8 2701 #define sc_x1_speed_override1_IQP_Options_i500uA 9 2702 #define sc_x1_speed_override1_IQP_Options_i550uA 10 2703 #define sc_x1_speed_override1_IQP_Options_i600uA 11 2704 #define sc_x1_speed_override1_IQP_Options_i650uA 12 2705 #define sc_x1_speed_override1_IQP_Options_i700uA 13 2706 #define sc_x1_speed_override1_IQP_Options_i750uA 14 2707 #define sc_x1_speed_override1_IQP_Options_i800uA 15 2708 2709 /**************************************************************************** 2710 * Enums: sc_x1_speed_override1_IDriver_Options 2711 */ 2712 #define sc_x1_speed_override1_IDriver_Options_v680mV 0 2713 #define sc_x1_speed_override1_IDriver_Options_v730mV 1 2714 #define sc_x1_speed_override1_IDriver_Options_v780mV 2 2715 #define sc_x1_speed_override1_IDriver_Options_v830mV 3 2716 #define sc_x1_speed_override1_IDriver_Options_v880mV 4 2717 #define sc_x1_speed_override1_IDriver_Options_v930mV 5 2718 #define sc_x1_speed_override1_IDriver_Options_v980mV 6 2719 #define sc_x1_speed_override1_IDriver_Options_v1010mV 7 2720 #define sc_x1_speed_override1_IDriver_Options_v1040mV 8 2721 #define sc_x1_speed_override1_IDriver_Options_v1060mV 9 2722 #define sc_x1_speed_override1_IDriver_Options_v1070mV 10 2723 #define sc_x1_speed_override1_IDriver_Options_v1080mV 11 2724 #define sc_x1_speed_override1_IDriver_Options_v1085mV 12 2725 #define sc_x1_speed_override1_IDriver_Options_v1090mV 13 2726 #define sc_x1_speed_override1_IDriver_Options_v1095mV 14 2727 #define sc_x1_speed_override1_IDriver_Options_v1100mV 15 2728 2729 /**************************************************************************** 2730 * Enums: sc_x1_speed_override1_operationModes 2731 */ 2732 #define sc_x1_speed_override1_operationModes_XGXS 0 2733 #define sc_x1_speed_override1_operationModes_XGXG_nCC 1 2734 #define sc_x1_speed_override1_operationModes_Indlane_OS8 4 2735 #define sc_x1_speed_override1_operationModes_IndLane_OS5 5 2736 #define sc_x1_speed_override1_operationModes_PCI 7 2737 #define sc_x1_speed_override1_operationModes_XGXS_nLQ 8 2738 #define sc_x1_speed_override1_operationModes_XGXS_nLQnCC 9 2739 #define sc_x1_speed_override1_operationModes_PBypass 10 2740 #define sc_x1_speed_override1_operationModes_PBypass_nDSK 11 2741 #define sc_x1_speed_override1_operationModes_ComboCoreMode 12 2742 #define sc_x1_speed_override1_operationModes_Clocks_off 15 2743 2744 /**************************************************************************** 2745 * Enums: sc_x1_speed_override1_synce_enum 2746 */ 2747 #define sc_x1_speed_override1_synce_enum_SYNCE_NO_DIV 0 2748 #define sc_x1_speed_override1_synce_enum_SYNCE_DIV_7 1 2749 #define sc_x1_speed_override1_synce_enum_SYNCE_DIV_11 2 2750 2751 /**************************************************************************** 2752 * Enums: sc_x1_speed_override1_operationSpeeds 2753 */ 2754 #define sc_x1_speed_override1_operationSpeeds_SPEED_2p5G_X1_10p3125 56 2755 #define sc_x1_speed_override1_operationSpeeds_SPEED_1000M_10p3125 55 2756 #define sc_x1_speed_override1_operationSpeeds_SPEED_100M_10p3125 54 2757 #define sc_x1_speed_override1_operationSpeeds_SPEED_10M_10p3125 53 2758 #define sc_x1_speed_override1_operationSpeeds_SPEED_10p5G_X4 50 2759 #define sc_x1_speed_override1_operationSpeeds_SPEED_5G_KR1 49 2760 #define sc_x1_speed_override1_operationSpeeds_SPEED_127G_X12 39 2761 #define sc_x1_speed_override1_operationSpeeds_SPEED_120G_X12 38 2762 #define sc_x1_speed_override1_operationSpeeds_SPEED_107G_X10 37 2763 #define sc_x1_speed_override1_operationSpeeds_SPEED_100G_CR10 36 2764 #define sc_x1_speed_override1_operationSpeeds_SPEED_42G_X4 35 2765 #define sc_x1_speed_override1_operationSpeeds_SPEED_40G_CR4 34 2766 #define sc_x1_speed_override1_operationSpeeds_SPEED_40G_KR4 33 2767 #define sc_x1_speed_override1_operationSpeeds_SPEED_21G_X2 32 2768 #define sc_x1_speed_override1_operationSpeeds_SPEED_20G_CR2 31 2769 #define sc_x1_speed_override1_operationSpeeds_SPEED_20G_KR2 30 2770 #define sc_x1_speed_override1_operationSpeeds_SPEED_10p6_X1 29 2771 #define sc_x1_speed_override1_operationSpeeds_SPEED_10G_KR1 28 2772 #define sc_x1_speed_override1_operationSpeeds_SPEED_40G_X4 27 2773 #define sc_x1_speed_override1_operationSpeeds_SPEED_20G_X2 26 2774 #define sc_x1_speed_override1_operationSpeeds_SPEED_20G_CX2 25 2775 #define sc_x1_speed_override1_operationSpeeds_SPEED_31p5G_KR4 24 2776 #define sc_x1_speed_override1_operationSpeeds_SPEED_31p5G_X4 23 2777 #define sc_x1_speed_override1_operationSpeeds_SPEED_15p75G_X2 22 2778 #define sc_x1_speed_override1_operationSpeeds_SPEED_25p45G_X4 21 2779 #define sc_x1_speed_override1_operationSpeeds_SPEED_12p7G_X2 20 2780 #define sc_x1_speed_override1_operationSpeeds_SPEED_21G_X4 19 2781 #define sc_x1_speed_override1_operationSpeeds_SPEED_10p5G_X2 18 2782 #define sc_x1_speed_override1_operationSpeeds_SPEED_20G_X4 17 2783 #define sc_x1_speed_override1_operationSpeeds_SPEED_10G_X2 16 2784 #define sc_x1_speed_override1_operationSpeeds_SPEED_10G_CX2 15 2785 #define sc_x1_speed_override1_operationSpeeds_SPEED_20G_CX4 14 2786 #define sc_x1_speed_override1_operationSpeeds_SPEED_16G_X4 13 2787 #define sc_x1_speed_override1_operationSpeeds_SPEED_15G_X4 12 2788 #define sc_x1_speed_override1_operationSpeeds_SPEED_13G_X4 11 2789 #define sc_x1_speed_override1_operationSpeeds_SPEED_10G_X4 10 2790 #define sc_x1_speed_override1_operationSpeeds_SPEED_10G_KX4 9 2791 #define sc_x1_speed_override1_operationSpeeds_SPEED_10G_CX4 8 2792 #define sc_x1_speed_override1_operationSpeeds_SPEED_5G_X1 7 2793 #define sc_x1_speed_override1_operationSpeeds_SPEED_2p5G_X1 6 2794 #define sc_x1_speed_override1_operationSpeeds_SPEED_1G_KX1 5 2795 #define sc_x1_speed_override1_operationSpeeds_SPEED_1G_CX1 4 2796 #define sc_x1_speed_override1_operationSpeeds_SPEED_1000M 3 2797 #define sc_x1_speed_override1_operationSpeeds_SPEED_100M 2 2798 #define sc_x1_speed_override1_operationSpeeds_SPEED_10M 1 2799 2800 /**************************************************************************** 2801 * Enums: sc_x1_speed_override1_actualSpeeds 2802 */ 2803 #define sc_x1_speed_override1_actualSpeeds_dr_10M 0 2804 #define sc_x1_speed_override1_actualSpeeds_dr_100M 1 2805 #define sc_x1_speed_override1_actualSpeeds_dr_1G 2 2806 #define sc_x1_speed_override1_actualSpeeds_dr_2p5G 3 2807 #define sc_x1_speed_override1_actualSpeeds_dr_5G_X4 4 2808 #define sc_x1_speed_override1_actualSpeeds_dr_6G_X4 5 2809 #define sc_x1_speed_override1_actualSpeeds_dr_10G_HiG 6 2810 #define sc_x1_speed_override1_actualSpeeds_dr_10G_CX4 7 2811 #define sc_x1_speed_override1_actualSpeeds_dr_12G_HiG 8 2812 #define sc_x1_speed_override1_actualSpeeds_dr_12p5G_X4 9 2813 #define sc_x1_speed_override1_actualSpeeds_dr_13G_X4 10 2814 #define sc_x1_speed_override1_actualSpeeds_dr_15G_X4 11 2815 #define sc_x1_speed_override1_actualSpeeds_dr_16G_X4 12 2816 #define sc_x1_speed_override1_actualSpeeds_dr_1G_KX 13 2817 #define sc_x1_speed_override1_actualSpeeds_dr_10G_KX4 14 2818 #define sc_x1_speed_override1_actualSpeeds_dr_10G_KR 15 2819 #define sc_x1_speed_override1_actualSpeeds_dr_5G 16 2820 #define sc_x1_speed_override1_actualSpeeds_dr_6p4G 17 2821 #define sc_x1_speed_override1_actualSpeeds_dr_20G_X4 18 2822 #define sc_x1_speed_override1_actualSpeeds_dr_21G_X4 19 2823 #define sc_x1_speed_override1_actualSpeeds_dr_25G_X4 20 2824 #define sc_x1_speed_override1_actualSpeeds_dr_10G_HiG_DXGXS 21 2825 #define sc_x1_speed_override1_actualSpeeds_dr_10G_DXGXS 22 2826 #define sc_x1_speed_override1_actualSpeeds_dr_10p5G_HiG_DXGXS 23 2827 #define sc_x1_speed_override1_actualSpeeds_dr_10p5G_DXGXS 24 2828 #define sc_x1_speed_override1_actualSpeeds_dr_12p773G_HiG_DXGXS 25 2829 #define sc_x1_speed_override1_actualSpeeds_dr_12p773G_DXGXS 26 2830 #define sc_x1_speed_override1_actualSpeeds_dr_10G_XFI 27 2831 #define sc_x1_speed_override1_actualSpeeds_dr_40G 28 2832 #define sc_x1_speed_override1_actualSpeeds_dr_20G_HiG_DXGXS 29 2833 #define sc_x1_speed_override1_actualSpeeds_dr_20G_DXGXS 30 2834 #define sc_x1_speed_override1_actualSpeeds_dr_10G_SFI 31 2835 #define sc_x1_speed_override1_actualSpeeds_dr_31p5G 32 2836 #define sc_x1_speed_override1_actualSpeeds_dr_32p7G 33 2837 #define sc_x1_speed_override1_actualSpeeds_dr_20G_SCR 34 2838 #define sc_x1_speed_override1_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 2839 #define sc_x1_speed_override1_actualSpeeds_dr_10G_DXGXS_SCR 36 2840 #define sc_x1_speed_override1_actualSpeeds_dr_12G_R2 37 2841 #define sc_x1_speed_override1_actualSpeeds_dr_10G_X2 38 2842 #define sc_x1_speed_override1_actualSpeeds_dr_40G_KR4 39 2843 #define sc_x1_speed_override1_actualSpeeds_dr_40G_CR4 40 2844 #define sc_x1_speed_override1_actualSpeeds_dr_100G_CR10 41 2845 #define sc_x1_speed_override1_actualSpeeds_dr_15p75G_DXGXS 44 2846 #define sc_x1_speed_override1_actualSpeeds_dr_20G_KR2 57 2847 #define sc_x1_speed_override1_actualSpeeds_dr_20G_CR2 58 2848 2849 /**************************************************************************** 2850 * Enums: sc_x1_speed_override1_actualSpeedsMisc1 2851 */ 2852 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_2500BRCM_X1 16 2853 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_5000BRCM_X4 17 2854 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_6000BRCM_X4 18 2855 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_10GHiGig_X4 19 2856 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_10GBASE_CX4 20 2857 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_12GHiGig_X4 21 2858 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 2859 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_13GHiGig_X4 23 2860 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_15GHiGig_X4 24 2861 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_16GHiGig_X4 25 2862 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_5000BRCM_X1 26 2863 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_6363BRCM_X1 27 2864 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_20GHiGig_X4 28 2865 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_21GHiGig_X4 29 2866 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 2867 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 2868 2869 /**************************************************************************** 2870 * Enums: sc_x1_speed_override1_IndLaneModes 2871 */ 2872 #define sc_x1_speed_override1_IndLaneModes_SWSDR_div2 0 2873 #define sc_x1_speed_override1_IndLaneModes_SWSDR_div1 1 2874 #define sc_x1_speed_override1_IndLaneModes_DWSDR_div2 2 2875 #define sc_x1_speed_override1_IndLaneModes_DWSDR_div1 3 2876 2877 /**************************************************************************** 2878 * Enums: sc_x1_speed_override1_prbsSelect 2879 */ 2880 #define sc_x1_speed_override1_prbsSelect_prbs7 0 2881 #define sc_x1_speed_override1_prbsSelect_prbs15 1 2882 #define sc_x1_speed_override1_prbsSelect_prbs23 2 2883 #define sc_x1_speed_override1_prbsSelect_prbs31 3 2884 2885 /**************************************************************************** 2886 * Enums: sc_x1_speed_override1_vcoDivider 2887 */ 2888 #define sc_x1_speed_override1_vcoDivider_div32 0 2889 #define sc_x1_speed_override1_vcoDivider_div36 1 2890 #define sc_x1_speed_override1_vcoDivider_div40 2 2891 #define sc_x1_speed_override1_vcoDivider_div42 3 2892 #define sc_x1_speed_override1_vcoDivider_div48 4 2893 #define sc_x1_speed_override1_vcoDivider_div50 5 2894 #define sc_x1_speed_override1_vcoDivider_div52 6 2895 #define sc_x1_speed_override1_vcoDivider_div54 7 2896 #define sc_x1_speed_override1_vcoDivider_div60 8 2897 #define sc_x1_speed_override1_vcoDivider_div64 9 2898 #define sc_x1_speed_override1_vcoDivider_div66 10 2899 #define sc_x1_speed_override1_vcoDivider_div68 11 2900 #define sc_x1_speed_override1_vcoDivider_div70 12 2901 #define sc_x1_speed_override1_vcoDivider_div80 13 2902 #define sc_x1_speed_override1_vcoDivider_div92 14 2903 #define sc_x1_speed_override1_vcoDivider_div100 15 2904 2905 /**************************************************************************** 2906 * Enums: sc_x1_speed_override1_refClkSelect 2907 */ 2908 #define sc_x1_speed_override1_refClkSelect_clk_25MHz 0 2909 #define sc_x1_speed_override1_refClkSelect_clk_100MHz 1 2910 #define sc_x1_speed_override1_refClkSelect_clk_125MHz 2 2911 #define sc_x1_speed_override1_refClkSelect_clk_156p25MHz 3 2912 #define sc_x1_speed_override1_refClkSelect_clk_187p5MHz 4 2913 #define sc_x1_speed_override1_refClkSelect_clk_161p25Mhz 5 2914 #define sc_x1_speed_override1_refClkSelect_clk_50Mhz 6 2915 #define sc_x1_speed_override1_refClkSelect_clk_106p25Mhz 7 2916 2917 /**************************************************************************** 2918 * Enums: sc_x1_speed_override1_aerMMDdevTypeSelect 2919 */ 2920 #define sc_x1_speed_override1_aerMMDdevTypeSelect_combo_core 0 2921 #define sc_x1_speed_override1_aerMMDdevTypeSelect_PMA_PMD 1 2922 #define sc_x1_speed_override1_aerMMDdevTypeSelect_PCS 3 2923 #define sc_x1_speed_override1_aerMMDdevTypeSelect_PHY 4 2924 #define sc_x1_speed_override1_aerMMDdevTypeSelect_DTE 5 2925 #define sc_x1_speed_override1_aerMMDdevTypeSelect_CL73_AN 7 2926 2927 /**************************************************************************** 2928 * Enums: sc_x1_speed_override1_aerMMDportSelect 2929 */ 2930 #define sc_x1_speed_override1_aerMMDportSelect_ln0 0 2931 #define sc_x1_speed_override1_aerMMDportSelect_ln1 1 2932 #define sc_x1_speed_override1_aerMMDportSelect_ln2 2 2933 #define sc_x1_speed_override1_aerMMDportSelect_ln3 3 2934 #define sc_x1_speed_override1_aerMMDportSelect_BCST_ln0_1_2_3 511 2935 #define sc_x1_speed_override1_aerMMDportSelect_BCST_ln0_1 512 2936 #define sc_x1_speed_override1_aerMMDportSelect_BCST_ln2_3 513 2937 2938 /**************************************************************************** 2939 * Enums: sc_x1_speed_override1_firmwareModeSelect 2940 */ 2941 #define sc_x1_speed_override1_firmwareModeSelect_DEFAULT 0 2942 #define sc_x1_speed_override1_firmwareModeSelect_SFP_OPT_LR 1 2943 #define sc_x1_speed_override1_firmwareModeSelect_SFP_DAC 2 2944 #define sc_x1_speed_override1_firmwareModeSelect_XLAUI 3 2945 #define sc_x1_speed_override1_firmwareModeSelect_LONG_CH_6G 4 2946 2947 /**************************************************************************** 2948 * Enums: sc_x1_speed_override1_tempIdxSelect 2949 */ 2950 #define sc_x1_speed_override1_tempIdxSelect_LTE__22p9C 15 2951 #define sc_x1_speed_override1_tempIdxSelect_LTE__12p6C 14 2952 #define sc_x1_speed_override1_tempIdxSelect_LTE__3p0C 13 2953 #define sc_x1_speed_override1_tempIdxSelect_LTE_6p7C 12 2954 #define sc_x1_speed_override1_tempIdxSelect_LTE_16p4C 11 2955 #define sc_x1_speed_override1_tempIdxSelect_LTE_26p6C 10 2956 #define sc_x1_speed_override1_tempIdxSelect_LTE_36p3C 9 2957 #define sc_x1_speed_override1_tempIdxSelect_LTE_46p0C 8 2958 #define sc_x1_speed_override1_tempIdxSelect_LTE_56p2C 7 2959 #define sc_x1_speed_override1_tempIdxSelect_LTE_65p9C 6 2960 #define sc_x1_speed_override1_tempIdxSelect_LTE_75p6C 5 2961 #define sc_x1_speed_override1_tempIdxSelect_LTE_85p3C 4 2962 #define sc_x1_speed_override1_tempIdxSelect_LTE_95p5C 3 2963 #define sc_x1_speed_override1_tempIdxSelect_LTE_105p2C 2 2964 #define sc_x1_speed_override1_tempIdxSelect_LTE_114p9C 1 2965 #define sc_x1_speed_override1_tempIdxSelect_LTE_125p1C 0 2966 2967 /**************************************************************************** 2968 * Enums: sc_x1_speed_override2_cl36TxEEEStates_l 2969 */ 2970 #define sc_x1_speed_override2_cl36TxEEEStates_l_TX_REFRESH 8 2971 #define sc_x1_speed_override2_cl36TxEEEStates_l_TX_QUIET 4 2972 #define sc_x1_speed_override2_cl36TxEEEStates_l_TX_SLEEP 2 2973 #define sc_x1_speed_override2_cl36TxEEEStates_l_TX_ACTIVE 1 2974 2975 /**************************************************************************** 2976 * Enums: sc_x1_speed_override2_cl36TxEEEStates_c 2977 */ 2978 #define sc_x1_speed_override2_cl36TxEEEStates_c_TX_REFRESH 3 2979 #define sc_x1_speed_override2_cl36TxEEEStates_c_TX_QUIET 2 2980 #define sc_x1_speed_override2_cl36TxEEEStates_c_TX_SLEEP 1 2981 #define sc_x1_speed_override2_cl36TxEEEStates_c_TX_ACTIVE 0 2982 2983 /**************************************************************************** 2984 * Enums: sc_x1_speed_override2_cl49TxEEEStates_l 2985 */ 2986 #define sc_x1_speed_override2_cl49TxEEEStates_l_SCR_RESET_2 64 2987 #define sc_x1_speed_override2_cl49TxEEEStates_l_SCR_RESET_1 32 2988 #define sc_x1_speed_override2_cl49TxEEEStates_l_TX_WAKE 16 2989 #define sc_x1_speed_override2_cl49TxEEEStates_l_TX_REFRESH 8 2990 #define sc_x1_speed_override2_cl49TxEEEStates_l_TX_QUIET 4 2991 #define sc_x1_speed_override2_cl49TxEEEStates_l_TX_SLEEP 2 2992 #define sc_x1_speed_override2_cl49TxEEEStates_l_TX_ACTIVE 1 2993 2994 /**************************************************************************** 2995 * Enums: sc_x1_speed_override2_cl49TxEEEStates_c 2996 */ 2997 #define sc_x1_speed_override2_cl49TxEEEStates_c_SCR_RESET_2 6 2998 #define sc_x1_speed_override2_cl49TxEEEStates_c_SCR_RESET_1 5 2999 #define sc_x1_speed_override2_cl49TxEEEStates_c_TX_WAKE 4 3000 #define sc_x1_speed_override2_cl49TxEEEStates_c_TX_REFRESH 3 3001 #define sc_x1_speed_override2_cl49TxEEEStates_c_TX_QUIET 2 3002 #define sc_x1_speed_override2_cl49TxEEEStates_c_TX_SLEEP 1 3003 #define sc_x1_speed_override2_cl49TxEEEStates_c_TX_ACTIVE 0 3004 3005 /**************************************************************************** 3006 * Enums: sc_x1_speed_override2_cl36RxEEEStates_l 3007 */ 3008 #define sc_x1_speed_override2_cl36RxEEEStates_l_RX_LINK_FAIL 32 3009 #define sc_x1_speed_override2_cl36RxEEEStates_l_RX_WTF 16 3010 #define sc_x1_speed_override2_cl36RxEEEStates_l_RX_WAKE 8 3011 #define sc_x1_speed_override2_cl36RxEEEStates_l_RX_QUIET 4 3012 #define sc_x1_speed_override2_cl36RxEEEStates_l_RX_SLEEP 2 3013 #define sc_x1_speed_override2_cl36RxEEEStates_l_RX_ACTIVE 1 3014 3015 /**************************************************************************** 3016 * Enums: sc_x1_speed_override2_cl36RxEEEStates_c 3017 */ 3018 #define sc_x1_speed_override2_cl36RxEEEStates_c_RX_LINK_FAIL 5 3019 #define sc_x1_speed_override2_cl36RxEEEStates_c_RX_WTF 4 3020 #define sc_x1_speed_override2_cl36RxEEEStates_c_RX_WAKE 3 3021 #define sc_x1_speed_override2_cl36RxEEEStates_c_RX_QUIET 2 3022 #define sc_x1_speed_override2_cl36RxEEEStates_c_RX_SLEEP 1 3023 #define sc_x1_speed_override2_cl36RxEEEStates_c_RX_ACTIVE 0 3024 3025 /**************************************************************************** 3026 * Enums: sc_x1_speed_override2_cl49RxEEEStates_l 3027 */ 3028 #define sc_x1_speed_override2_cl49RxEEEStates_l_RX_LINK_FAIL 32 3029 #define sc_x1_speed_override2_cl49RxEEEStates_l_RX_WTF 16 3030 #define sc_x1_speed_override2_cl49RxEEEStates_l_RX_WAKE 8 3031 #define sc_x1_speed_override2_cl49RxEEEStates_l_RX_QUIET 4 3032 #define sc_x1_speed_override2_cl49RxEEEStates_l_RX_SLEEP 2 3033 #define sc_x1_speed_override2_cl49RxEEEStates_l_RX_ACTIVE 1 3034 3035 /**************************************************************************** 3036 * Enums: sc_x1_speed_override2_cl49RxEEEStates_c 3037 */ 3038 #define sc_x1_speed_override2_cl49RxEEEStates_c_RX_LINK_FAIL 5 3039 #define sc_x1_speed_override2_cl49RxEEEStates_c_RX_WTF 4 3040 #define sc_x1_speed_override2_cl49RxEEEStates_c_RX_WAKE 3 3041 #define sc_x1_speed_override2_cl49RxEEEStates_c_RX_QUIET 2 3042 #define sc_x1_speed_override2_cl49RxEEEStates_c_RX_SLEEP 1 3043 #define sc_x1_speed_override2_cl49RxEEEStates_c_RX_ACTIVE 0 3044 3045 /**************************************************************************** 3046 * Enums: sc_x1_speed_override2_cl48TxEEEStates_l 3047 */ 3048 #define sc_x1_speed_override2_cl48TxEEEStates_l_TX_REFRESH 8 3049 #define sc_x1_speed_override2_cl48TxEEEStates_l_TX_QUIET 4 3050 #define sc_x1_speed_override2_cl48TxEEEStates_l_TX_SLEEP 2 3051 #define sc_x1_speed_override2_cl48TxEEEStates_l_TX_ACTIVE 1 3052 3053 /**************************************************************************** 3054 * Enums: sc_x1_speed_override2_cl48TxEEEStates_c 3055 */ 3056 #define sc_x1_speed_override2_cl48TxEEEStates_c_TX_REFRESH 3 3057 #define sc_x1_speed_override2_cl48TxEEEStates_c_TX_QUIET 2 3058 #define sc_x1_speed_override2_cl48TxEEEStates_c_TX_SLEEP 1 3059 #define sc_x1_speed_override2_cl48TxEEEStates_c_TX_ACTIVE 0 3060 3061 /**************************************************************************** 3062 * Enums: sc_x1_speed_override2_cl48RxEEEStates_l 3063 */ 3064 #define sc_x1_speed_override2_cl48RxEEEStates_l_RX_LINK_FAIL 32 3065 #define sc_x1_speed_override2_cl48RxEEEStates_l_RX_WAKE 16 3066 #define sc_x1_speed_override2_cl48RxEEEStates_l_RX_QUIET 8 3067 #define sc_x1_speed_override2_cl48RxEEEStates_l_RX_DEACT 4 3068 #define sc_x1_speed_override2_cl48RxEEEStates_l_RX_SLEEP 2 3069 #define sc_x1_speed_override2_cl48RxEEEStates_l_RX_ACTIVE 1 3070 3071 /**************************************************************************** 3072 * Enums: sc_x1_speed_override2_cl48RxEEEStates_c 3073 */ 3074 #define sc_x1_speed_override2_cl48RxEEEStates_c_RX_LINK_FAIL 5 3075 #define sc_x1_speed_override2_cl48RxEEEStates_c_RX_WAKE 4 3076 #define sc_x1_speed_override2_cl48RxEEEStates_c_RX_QUIET 3 3077 #define sc_x1_speed_override2_cl48RxEEEStates_c_RX_DEACT 2 3078 #define sc_x1_speed_override2_cl48RxEEEStates_c_RX_SLEEP 1 3079 #define sc_x1_speed_override2_cl48RxEEEStates_c_RX_ACTIVE 0 3080 3081 /**************************************************************************** 3082 * Enums: sc_x1_speed_override2_IQP_Options 3083 */ 3084 #define sc_x1_speed_override2_IQP_Options_i50uA 0 3085 #define sc_x1_speed_override2_IQP_Options_i100uA 1 3086 #define sc_x1_speed_override2_IQP_Options_i150uA 2 3087 #define sc_x1_speed_override2_IQP_Options_i200uA 3 3088 #define sc_x1_speed_override2_IQP_Options_i250uA 4 3089 #define sc_x1_speed_override2_IQP_Options_i300uA 5 3090 #define sc_x1_speed_override2_IQP_Options_i350uA 6 3091 #define sc_x1_speed_override2_IQP_Options_i400uA 7 3092 #define sc_x1_speed_override2_IQP_Options_i450uA 8 3093 #define sc_x1_speed_override2_IQP_Options_i500uA 9 3094 #define sc_x1_speed_override2_IQP_Options_i550uA 10 3095 #define sc_x1_speed_override2_IQP_Options_i600uA 11 3096 #define sc_x1_speed_override2_IQP_Options_i650uA 12 3097 #define sc_x1_speed_override2_IQP_Options_i700uA 13 3098 #define sc_x1_speed_override2_IQP_Options_i750uA 14 3099 #define sc_x1_speed_override2_IQP_Options_i800uA 15 3100 3101 /**************************************************************************** 3102 * Enums: sc_x1_speed_override2_IDriver_Options 3103 */ 3104 #define sc_x1_speed_override2_IDriver_Options_v680mV 0 3105 #define sc_x1_speed_override2_IDriver_Options_v730mV 1 3106 #define sc_x1_speed_override2_IDriver_Options_v780mV 2 3107 #define sc_x1_speed_override2_IDriver_Options_v830mV 3 3108 #define sc_x1_speed_override2_IDriver_Options_v880mV 4 3109 #define sc_x1_speed_override2_IDriver_Options_v930mV 5 3110 #define sc_x1_speed_override2_IDriver_Options_v980mV 6 3111 #define sc_x1_speed_override2_IDriver_Options_v1010mV 7 3112 #define sc_x1_speed_override2_IDriver_Options_v1040mV 8 3113 #define sc_x1_speed_override2_IDriver_Options_v1060mV 9 3114 #define sc_x1_speed_override2_IDriver_Options_v1070mV 10 3115 #define sc_x1_speed_override2_IDriver_Options_v1080mV 11 3116 #define sc_x1_speed_override2_IDriver_Options_v1085mV 12 3117 #define sc_x1_speed_override2_IDriver_Options_v1090mV 13 3118 #define sc_x1_speed_override2_IDriver_Options_v1095mV 14 3119 #define sc_x1_speed_override2_IDriver_Options_v1100mV 15 3120 3121 /**************************************************************************** 3122 * Enums: sc_x1_speed_override2_operationModes 3123 */ 3124 #define sc_x1_speed_override2_operationModes_XGXS 0 3125 #define sc_x1_speed_override2_operationModes_XGXG_nCC 1 3126 #define sc_x1_speed_override2_operationModes_Indlane_OS8 4 3127 #define sc_x1_speed_override2_operationModes_IndLane_OS5 5 3128 #define sc_x1_speed_override2_operationModes_PCI 7 3129 #define sc_x1_speed_override2_operationModes_XGXS_nLQ 8 3130 #define sc_x1_speed_override2_operationModes_XGXS_nLQnCC 9 3131 #define sc_x1_speed_override2_operationModes_PBypass 10 3132 #define sc_x1_speed_override2_operationModes_PBypass_nDSK 11 3133 #define sc_x1_speed_override2_operationModes_ComboCoreMode 12 3134 #define sc_x1_speed_override2_operationModes_Clocks_off 15 3135 3136 /**************************************************************************** 3137 * Enums: sc_x1_speed_override2_synce_enum 3138 */ 3139 #define sc_x1_speed_override2_synce_enum_SYNCE_NO_DIV 0 3140 #define sc_x1_speed_override2_synce_enum_SYNCE_DIV_7 1 3141 #define sc_x1_speed_override2_synce_enum_SYNCE_DIV_11 2 3142 3143 /**************************************************************************** 3144 * Enums: sc_x1_speed_override2_operationSpeeds 3145 */ 3146 #define sc_x1_speed_override2_operationSpeeds_SPEED_2p5G_X1_10p3125 56 3147 #define sc_x1_speed_override2_operationSpeeds_SPEED_1000M_10p3125 55 3148 #define sc_x1_speed_override2_operationSpeeds_SPEED_100M_10p3125 54 3149 #define sc_x1_speed_override2_operationSpeeds_SPEED_10M_10p3125 53 3150 #define sc_x1_speed_override2_operationSpeeds_SPEED_10p5G_X4 50 3151 #define sc_x1_speed_override2_operationSpeeds_SPEED_5G_KR1 49 3152 #define sc_x1_speed_override2_operationSpeeds_SPEED_127G_X12 39 3153 #define sc_x1_speed_override2_operationSpeeds_SPEED_120G_X12 38 3154 #define sc_x1_speed_override2_operationSpeeds_SPEED_107G_X10 37 3155 #define sc_x1_speed_override2_operationSpeeds_SPEED_100G_CR10 36 3156 #define sc_x1_speed_override2_operationSpeeds_SPEED_42G_X4 35 3157 #define sc_x1_speed_override2_operationSpeeds_SPEED_40G_CR4 34 3158 #define sc_x1_speed_override2_operationSpeeds_SPEED_40G_KR4 33 3159 #define sc_x1_speed_override2_operationSpeeds_SPEED_21G_X2 32 3160 #define sc_x1_speed_override2_operationSpeeds_SPEED_20G_CR2 31 3161 #define sc_x1_speed_override2_operationSpeeds_SPEED_20G_KR2 30 3162 #define sc_x1_speed_override2_operationSpeeds_SPEED_10p6_X1 29 3163 #define sc_x1_speed_override2_operationSpeeds_SPEED_10G_KR1 28 3164 #define sc_x1_speed_override2_operationSpeeds_SPEED_40G_X4 27 3165 #define sc_x1_speed_override2_operationSpeeds_SPEED_20G_X2 26 3166 #define sc_x1_speed_override2_operationSpeeds_SPEED_20G_CX2 25 3167 #define sc_x1_speed_override2_operationSpeeds_SPEED_31p5G_KR4 24 3168 #define sc_x1_speed_override2_operationSpeeds_SPEED_31p5G_X4 23 3169 #define sc_x1_speed_override2_operationSpeeds_SPEED_15p75G_X2 22 3170 #define sc_x1_speed_override2_operationSpeeds_SPEED_25p45G_X4 21 3171 #define sc_x1_speed_override2_operationSpeeds_SPEED_12p7G_X2 20 3172 #define sc_x1_speed_override2_operationSpeeds_SPEED_21G_X4 19 3173 #define sc_x1_speed_override2_operationSpeeds_SPEED_10p5G_X2 18 3174 #define sc_x1_speed_override2_operationSpeeds_SPEED_20G_X4 17 3175 #define sc_x1_speed_override2_operationSpeeds_SPEED_10G_X2 16 3176 #define sc_x1_speed_override2_operationSpeeds_SPEED_10G_CX2 15 3177 #define sc_x1_speed_override2_operationSpeeds_SPEED_20G_CX4 14 3178 #define sc_x1_speed_override2_operationSpeeds_SPEED_16G_X4 13 3179 #define sc_x1_speed_override2_operationSpeeds_SPEED_15G_X4 12 3180 #define sc_x1_speed_override2_operationSpeeds_SPEED_13G_X4 11 3181 #define sc_x1_speed_override2_operationSpeeds_SPEED_10G_X4 10 3182 #define sc_x1_speed_override2_operationSpeeds_SPEED_10G_KX4 9 3183 #define sc_x1_speed_override2_operationSpeeds_SPEED_10G_CX4 8 3184 #define sc_x1_speed_override2_operationSpeeds_SPEED_5G_X1 7 3185 #define sc_x1_speed_override2_operationSpeeds_SPEED_2p5G_X1 6 3186 #define sc_x1_speed_override2_operationSpeeds_SPEED_1G_KX1 5 3187 #define sc_x1_speed_override2_operationSpeeds_SPEED_1G_CX1 4 3188 #define sc_x1_speed_override2_operationSpeeds_SPEED_1000M 3 3189 #define sc_x1_speed_override2_operationSpeeds_SPEED_100M 2 3190 #define sc_x1_speed_override2_operationSpeeds_SPEED_10M 1 3191 3192 /**************************************************************************** 3193 * Enums: sc_x1_speed_override2_actualSpeeds 3194 */ 3195 #define sc_x1_speed_override2_actualSpeeds_dr_10M 0 3196 #define sc_x1_speed_override2_actualSpeeds_dr_100M 1 3197 #define sc_x1_speed_override2_actualSpeeds_dr_1G 2 3198 #define sc_x1_speed_override2_actualSpeeds_dr_2p5G 3 3199 #define sc_x1_speed_override2_actualSpeeds_dr_5G_X4 4 3200 #define sc_x1_speed_override2_actualSpeeds_dr_6G_X4 5 3201 #define sc_x1_speed_override2_actualSpeeds_dr_10G_HiG 6 3202 #define sc_x1_speed_override2_actualSpeeds_dr_10G_CX4 7 3203 #define sc_x1_speed_override2_actualSpeeds_dr_12G_HiG 8 3204 #define sc_x1_speed_override2_actualSpeeds_dr_12p5G_X4 9 3205 #define sc_x1_speed_override2_actualSpeeds_dr_13G_X4 10 3206 #define sc_x1_speed_override2_actualSpeeds_dr_15G_X4 11 3207 #define sc_x1_speed_override2_actualSpeeds_dr_16G_X4 12 3208 #define sc_x1_speed_override2_actualSpeeds_dr_1G_KX 13 3209 #define sc_x1_speed_override2_actualSpeeds_dr_10G_KX4 14 3210 #define sc_x1_speed_override2_actualSpeeds_dr_10G_KR 15 3211 #define sc_x1_speed_override2_actualSpeeds_dr_5G 16 3212 #define sc_x1_speed_override2_actualSpeeds_dr_6p4G 17 3213 #define sc_x1_speed_override2_actualSpeeds_dr_20G_X4 18 3214 #define sc_x1_speed_override2_actualSpeeds_dr_21G_X4 19 3215 #define sc_x1_speed_override2_actualSpeeds_dr_25G_X4 20 3216 #define sc_x1_speed_override2_actualSpeeds_dr_10G_HiG_DXGXS 21 3217 #define sc_x1_speed_override2_actualSpeeds_dr_10G_DXGXS 22 3218 #define sc_x1_speed_override2_actualSpeeds_dr_10p5G_HiG_DXGXS 23 3219 #define sc_x1_speed_override2_actualSpeeds_dr_10p5G_DXGXS 24 3220 #define sc_x1_speed_override2_actualSpeeds_dr_12p773G_HiG_DXGXS 25 3221 #define sc_x1_speed_override2_actualSpeeds_dr_12p773G_DXGXS 26 3222 #define sc_x1_speed_override2_actualSpeeds_dr_10G_XFI 27 3223 #define sc_x1_speed_override2_actualSpeeds_dr_40G 28 3224 #define sc_x1_speed_override2_actualSpeeds_dr_20G_HiG_DXGXS 29 3225 #define sc_x1_speed_override2_actualSpeeds_dr_20G_DXGXS 30 3226 #define sc_x1_speed_override2_actualSpeeds_dr_10G_SFI 31 3227 #define sc_x1_speed_override2_actualSpeeds_dr_31p5G 32 3228 #define sc_x1_speed_override2_actualSpeeds_dr_32p7G 33 3229 #define sc_x1_speed_override2_actualSpeeds_dr_20G_SCR 34 3230 #define sc_x1_speed_override2_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 3231 #define sc_x1_speed_override2_actualSpeeds_dr_10G_DXGXS_SCR 36 3232 #define sc_x1_speed_override2_actualSpeeds_dr_12G_R2 37 3233 #define sc_x1_speed_override2_actualSpeeds_dr_10G_X2 38 3234 #define sc_x1_speed_override2_actualSpeeds_dr_40G_KR4 39 3235 #define sc_x1_speed_override2_actualSpeeds_dr_40G_CR4 40 3236 #define sc_x1_speed_override2_actualSpeeds_dr_100G_CR10 41 3237 #define sc_x1_speed_override2_actualSpeeds_dr_15p75G_DXGXS 44 3238 #define sc_x1_speed_override2_actualSpeeds_dr_20G_KR2 57 3239 #define sc_x1_speed_override2_actualSpeeds_dr_20G_CR2 58 3240 3241 /**************************************************************************** 3242 * Enums: sc_x1_speed_override2_actualSpeedsMisc1 3243 */ 3244 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_2500BRCM_X1 16 3245 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_5000BRCM_X4 17 3246 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_6000BRCM_X4 18 3247 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_10GHiGig_X4 19 3248 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_10GBASE_CX4 20 3249 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_12GHiGig_X4 21 3250 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 3251 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_13GHiGig_X4 23 3252 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_15GHiGig_X4 24 3253 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_16GHiGig_X4 25 3254 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_5000BRCM_X1 26 3255 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_6363BRCM_X1 27 3256 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_20GHiGig_X4 28 3257 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_21GHiGig_X4 29 3258 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 3259 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 3260 3261 /**************************************************************************** 3262 * Enums: sc_x1_speed_override2_IndLaneModes 3263 */ 3264 #define sc_x1_speed_override2_IndLaneModes_SWSDR_div2 0 3265 #define sc_x1_speed_override2_IndLaneModes_SWSDR_div1 1 3266 #define sc_x1_speed_override2_IndLaneModes_DWSDR_div2 2 3267 #define sc_x1_speed_override2_IndLaneModes_DWSDR_div1 3 3268 3269 /**************************************************************************** 3270 * Enums: sc_x1_speed_override2_prbsSelect 3271 */ 3272 #define sc_x1_speed_override2_prbsSelect_prbs7 0 3273 #define sc_x1_speed_override2_prbsSelect_prbs15 1 3274 #define sc_x1_speed_override2_prbsSelect_prbs23 2 3275 #define sc_x1_speed_override2_prbsSelect_prbs31 3 3276 3277 /**************************************************************************** 3278 * Enums: sc_x1_speed_override2_vcoDivider 3279 */ 3280 #define sc_x1_speed_override2_vcoDivider_div32 0 3281 #define sc_x1_speed_override2_vcoDivider_div36 1 3282 #define sc_x1_speed_override2_vcoDivider_div40 2 3283 #define sc_x1_speed_override2_vcoDivider_div42 3 3284 #define sc_x1_speed_override2_vcoDivider_div48 4 3285 #define sc_x1_speed_override2_vcoDivider_div50 5 3286 #define sc_x1_speed_override2_vcoDivider_div52 6 3287 #define sc_x1_speed_override2_vcoDivider_div54 7 3288 #define sc_x1_speed_override2_vcoDivider_div60 8 3289 #define sc_x1_speed_override2_vcoDivider_div64 9 3290 #define sc_x1_speed_override2_vcoDivider_div66 10 3291 #define sc_x1_speed_override2_vcoDivider_div68 11 3292 #define sc_x1_speed_override2_vcoDivider_div70 12 3293 #define sc_x1_speed_override2_vcoDivider_div80 13 3294 #define sc_x1_speed_override2_vcoDivider_div92 14 3295 #define sc_x1_speed_override2_vcoDivider_div100 15 3296 3297 /**************************************************************************** 3298 * Enums: sc_x1_speed_override2_refClkSelect 3299 */ 3300 #define sc_x1_speed_override2_refClkSelect_clk_25MHz 0 3301 #define sc_x1_speed_override2_refClkSelect_clk_100MHz 1 3302 #define sc_x1_speed_override2_refClkSelect_clk_125MHz 2 3303 #define sc_x1_speed_override2_refClkSelect_clk_156p25MHz 3 3304 #define sc_x1_speed_override2_refClkSelect_clk_187p5MHz 4 3305 #define sc_x1_speed_override2_refClkSelect_clk_161p25Mhz 5 3306 #define sc_x1_speed_override2_refClkSelect_clk_50Mhz 6 3307 #define sc_x1_speed_override2_refClkSelect_clk_106p25Mhz 7 3308 3309 /**************************************************************************** 3310 * Enums: sc_x1_speed_override2_aerMMDdevTypeSelect 3311 */ 3312 #define sc_x1_speed_override2_aerMMDdevTypeSelect_combo_core 0 3313 #define sc_x1_speed_override2_aerMMDdevTypeSelect_PMA_PMD 1 3314 #define sc_x1_speed_override2_aerMMDdevTypeSelect_PCS 3 3315 #define sc_x1_speed_override2_aerMMDdevTypeSelect_PHY 4 3316 #define sc_x1_speed_override2_aerMMDdevTypeSelect_DTE 5 3317 #define sc_x1_speed_override2_aerMMDdevTypeSelect_CL73_AN 7 3318 3319 /**************************************************************************** 3320 * Enums: sc_x1_speed_override2_aerMMDportSelect 3321 */ 3322 #define sc_x1_speed_override2_aerMMDportSelect_ln0 0 3323 #define sc_x1_speed_override2_aerMMDportSelect_ln1 1 3324 #define sc_x1_speed_override2_aerMMDportSelect_ln2 2 3325 #define sc_x1_speed_override2_aerMMDportSelect_ln3 3 3326 #define sc_x1_speed_override2_aerMMDportSelect_BCST_ln0_1_2_3 511 3327 #define sc_x1_speed_override2_aerMMDportSelect_BCST_ln0_1 512 3328 #define sc_x1_speed_override2_aerMMDportSelect_BCST_ln2_3 513 3329 3330 /**************************************************************************** 3331 * Enums: sc_x1_speed_override2_firmwareModeSelect 3332 */ 3333 #define sc_x1_speed_override2_firmwareModeSelect_DEFAULT 0 3334 #define sc_x1_speed_override2_firmwareModeSelect_SFP_OPT_LR 1 3335 #define sc_x1_speed_override2_firmwareModeSelect_SFP_DAC 2 3336 #define sc_x1_speed_override2_firmwareModeSelect_XLAUI 3 3337 #define sc_x1_speed_override2_firmwareModeSelect_LONG_CH_6G 4 3338 3339 /**************************************************************************** 3340 * Enums: sc_x1_speed_override2_tempIdxSelect 3341 */ 3342 #define sc_x1_speed_override2_tempIdxSelect_LTE__22p9C 15 3343 #define sc_x1_speed_override2_tempIdxSelect_LTE__12p6C 14 3344 #define sc_x1_speed_override2_tempIdxSelect_LTE__3p0C 13 3345 #define sc_x1_speed_override2_tempIdxSelect_LTE_6p7C 12 3346 #define sc_x1_speed_override2_tempIdxSelect_LTE_16p4C 11 3347 #define sc_x1_speed_override2_tempIdxSelect_LTE_26p6C 10 3348 #define sc_x1_speed_override2_tempIdxSelect_LTE_36p3C 9 3349 #define sc_x1_speed_override2_tempIdxSelect_LTE_46p0C 8 3350 #define sc_x1_speed_override2_tempIdxSelect_LTE_56p2C 7 3351 #define sc_x1_speed_override2_tempIdxSelect_LTE_65p9C 6 3352 #define sc_x1_speed_override2_tempIdxSelect_LTE_75p6C 5 3353 #define sc_x1_speed_override2_tempIdxSelect_LTE_85p3C 4 3354 #define sc_x1_speed_override2_tempIdxSelect_LTE_95p5C 3 3355 #define sc_x1_speed_override2_tempIdxSelect_LTE_105p2C 2 3356 #define sc_x1_speed_override2_tempIdxSelect_LTE_114p9C 1 3357 #define sc_x1_speed_override2_tempIdxSelect_LTE_125p1C 0 3358 3359 /**************************************************************************** 3360 * Enums: sc_x1_speed_override3_cl36TxEEEStates_l 3361 */ 3362 #define sc_x1_speed_override3_cl36TxEEEStates_l_TX_REFRESH 8 3363 #define sc_x1_speed_override3_cl36TxEEEStates_l_TX_QUIET 4 3364 #define sc_x1_speed_override3_cl36TxEEEStates_l_TX_SLEEP 2 3365 #define sc_x1_speed_override3_cl36TxEEEStates_l_TX_ACTIVE 1 3366 3367 /**************************************************************************** 3368 * Enums: sc_x1_speed_override3_cl36TxEEEStates_c 3369 */ 3370 #define sc_x1_speed_override3_cl36TxEEEStates_c_TX_REFRESH 3 3371 #define sc_x1_speed_override3_cl36TxEEEStates_c_TX_QUIET 2 3372 #define sc_x1_speed_override3_cl36TxEEEStates_c_TX_SLEEP 1 3373 #define sc_x1_speed_override3_cl36TxEEEStates_c_TX_ACTIVE 0 3374 3375 /**************************************************************************** 3376 * Enums: sc_x1_speed_override3_cl49TxEEEStates_l 3377 */ 3378 #define sc_x1_speed_override3_cl49TxEEEStates_l_SCR_RESET_2 64 3379 #define sc_x1_speed_override3_cl49TxEEEStates_l_SCR_RESET_1 32 3380 #define sc_x1_speed_override3_cl49TxEEEStates_l_TX_WAKE 16 3381 #define sc_x1_speed_override3_cl49TxEEEStates_l_TX_REFRESH 8 3382 #define sc_x1_speed_override3_cl49TxEEEStates_l_TX_QUIET 4 3383 #define sc_x1_speed_override3_cl49TxEEEStates_l_TX_SLEEP 2 3384 #define sc_x1_speed_override3_cl49TxEEEStates_l_TX_ACTIVE 1 3385 3386 /**************************************************************************** 3387 * Enums: sc_x1_speed_override3_cl49TxEEEStates_c 3388 */ 3389 #define sc_x1_speed_override3_cl49TxEEEStates_c_SCR_RESET_2 6 3390 #define sc_x1_speed_override3_cl49TxEEEStates_c_SCR_RESET_1 5 3391 #define sc_x1_speed_override3_cl49TxEEEStates_c_TX_WAKE 4 3392 #define sc_x1_speed_override3_cl49TxEEEStates_c_TX_REFRESH 3 3393 #define sc_x1_speed_override3_cl49TxEEEStates_c_TX_QUIET 2 3394 #define sc_x1_speed_override3_cl49TxEEEStates_c_TX_SLEEP 1 3395 #define sc_x1_speed_override3_cl49TxEEEStates_c_TX_ACTIVE 0 3396 3397 /**************************************************************************** 3398 * Enums: sc_x1_speed_override3_cl36RxEEEStates_l 3399 */ 3400 #define sc_x1_speed_override3_cl36RxEEEStates_l_RX_LINK_FAIL 32 3401 #define sc_x1_speed_override3_cl36RxEEEStates_l_RX_WTF 16 3402 #define sc_x1_speed_override3_cl36RxEEEStates_l_RX_WAKE 8 3403 #define sc_x1_speed_override3_cl36RxEEEStates_l_RX_QUIET 4 3404 #define sc_x1_speed_override3_cl36RxEEEStates_l_RX_SLEEP 2 3405 #define sc_x1_speed_override3_cl36RxEEEStates_l_RX_ACTIVE 1 3406 3407 /**************************************************************************** 3408 * Enums: sc_x1_speed_override3_cl36RxEEEStates_c 3409 */ 3410 #define sc_x1_speed_override3_cl36RxEEEStates_c_RX_LINK_FAIL 5 3411 #define sc_x1_speed_override3_cl36RxEEEStates_c_RX_WTF 4 3412 #define sc_x1_speed_override3_cl36RxEEEStates_c_RX_WAKE 3 3413 #define sc_x1_speed_override3_cl36RxEEEStates_c_RX_QUIET 2 3414 #define sc_x1_speed_override3_cl36RxEEEStates_c_RX_SLEEP 1 3415 #define sc_x1_speed_override3_cl36RxEEEStates_c_RX_ACTIVE 0 3416 3417 /**************************************************************************** 3418 * Enums: sc_x1_speed_override3_cl49RxEEEStates_l 3419 */ 3420 #define sc_x1_speed_override3_cl49RxEEEStates_l_RX_LINK_FAIL 32 3421 #define sc_x1_speed_override3_cl49RxEEEStates_l_RX_WTF 16 3422 #define sc_x1_speed_override3_cl49RxEEEStates_l_RX_WAKE 8 3423 #define sc_x1_speed_override3_cl49RxEEEStates_l_RX_QUIET 4 3424 #define sc_x1_speed_override3_cl49RxEEEStates_l_RX_SLEEP 2 3425 #define sc_x1_speed_override3_cl49RxEEEStates_l_RX_ACTIVE 1 3426 3427 /**************************************************************************** 3428 * Enums: sc_x1_speed_override3_cl49RxEEEStates_c 3429 */ 3430 #define sc_x1_speed_override3_cl49RxEEEStates_c_RX_LINK_FAIL 5 3431 #define sc_x1_speed_override3_cl49RxEEEStates_c_RX_WTF 4 3432 #define sc_x1_speed_override3_cl49RxEEEStates_c_RX_WAKE 3 3433 #define sc_x1_speed_override3_cl49RxEEEStates_c_RX_QUIET 2 3434 #define sc_x1_speed_override3_cl49RxEEEStates_c_RX_SLEEP 1 3435 #define sc_x1_speed_override3_cl49RxEEEStates_c_RX_ACTIVE 0 3436 3437 /**************************************************************************** 3438 * Enums: sc_x1_speed_override3_cl48TxEEEStates_l 3439 */ 3440 #define sc_x1_speed_override3_cl48TxEEEStates_l_TX_REFRESH 8 3441 #define sc_x1_speed_override3_cl48TxEEEStates_l_TX_QUIET 4 3442 #define sc_x1_speed_override3_cl48TxEEEStates_l_TX_SLEEP 2 3443 #define sc_x1_speed_override3_cl48TxEEEStates_l_TX_ACTIVE 1 3444 3445 /**************************************************************************** 3446 * Enums: sc_x1_speed_override3_cl48TxEEEStates_c 3447 */ 3448 #define sc_x1_speed_override3_cl48TxEEEStates_c_TX_REFRESH 3 3449 #define sc_x1_speed_override3_cl48TxEEEStates_c_TX_QUIET 2 3450 #define sc_x1_speed_override3_cl48TxEEEStates_c_TX_SLEEP 1 3451 #define sc_x1_speed_override3_cl48TxEEEStates_c_TX_ACTIVE 0 3452 3453 /**************************************************************************** 3454 * Enums: sc_x1_speed_override3_cl48RxEEEStates_l 3455 */ 3456 #define sc_x1_speed_override3_cl48RxEEEStates_l_RX_LINK_FAIL 32 3457 #define sc_x1_speed_override3_cl48RxEEEStates_l_RX_WAKE 16 3458 #define sc_x1_speed_override3_cl48RxEEEStates_l_RX_QUIET 8 3459 #define sc_x1_speed_override3_cl48RxEEEStates_l_RX_DEACT 4 3460 #define sc_x1_speed_override3_cl48RxEEEStates_l_RX_SLEEP 2 3461 #define sc_x1_speed_override3_cl48RxEEEStates_l_RX_ACTIVE 1 3462 3463 /**************************************************************************** 3464 * Enums: sc_x1_speed_override3_cl48RxEEEStates_c 3465 */ 3466 #define sc_x1_speed_override3_cl48RxEEEStates_c_RX_LINK_FAIL 5 3467 #define sc_x1_speed_override3_cl48RxEEEStates_c_RX_WAKE 4 3468 #define sc_x1_speed_override3_cl48RxEEEStates_c_RX_QUIET 3 3469 #define sc_x1_speed_override3_cl48RxEEEStates_c_RX_DEACT 2 3470 #define sc_x1_speed_override3_cl48RxEEEStates_c_RX_SLEEP 1 3471 #define sc_x1_speed_override3_cl48RxEEEStates_c_RX_ACTIVE 0 3472 3473 /**************************************************************************** 3474 * Enums: sc_x1_speed_override3_IQP_Options 3475 */ 3476 #define sc_x1_speed_override3_IQP_Options_i50uA 0 3477 #define sc_x1_speed_override3_IQP_Options_i100uA 1 3478 #define sc_x1_speed_override3_IQP_Options_i150uA 2 3479 #define sc_x1_speed_override3_IQP_Options_i200uA 3 3480 #define sc_x1_speed_override3_IQP_Options_i250uA 4 3481 #define sc_x1_speed_override3_IQP_Options_i300uA 5 3482 #define sc_x1_speed_override3_IQP_Options_i350uA 6 3483 #define sc_x1_speed_override3_IQP_Options_i400uA 7 3484 #define sc_x1_speed_override3_IQP_Options_i450uA 8 3485 #define sc_x1_speed_override3_IQP_Options_i500uA 9 3486 #define sc_x1_speed_override3_IQP_Options_i550uA 10 3487 #define sc_x1_speed_override3_IQP_Options_i600uA 11 3488 #define sc_x1_speed_override3_IQP_Options_i650uA 12 3489 #define sc_x1_speed_override3_IQP_Options_i700uA 13 3490 #define sc_x1_speed_override3_IQP_Options_i750uA 14 3491 #define sc_x1_speed_override3_IQP_Options_i800uA 15 3492 3493 /**************************************************************************** 3494 * Enums: sc_x1_speed_override3_IDriver_Options 3495 */ 3496 #define sc_x1_speed_override3_IDriver_Options_v680mV 0 3497 #define sc_x1_speed_override3_IDriver_Options_v730mV 1 3498 #define sc_x1_speed_override3_IDriver_Options_v780mV 2 3499 #define sc_x1_speed_override3_IDriver_Options_v830mV 3 3500 #define sc_x1_speed_override3_IDriver_Options_v880mV 4 3501 #define sc_x1_speed_override3_IDriver_Options_v930mV 5 3502 #define sc_x1_speed_override3_IDriver_Options_v980mV 6 3503 #define sc_x1_speed_override3_IDriver_Options_v1010mV 7 3504 #define sc_x1_speed_override3_IDriver_Options_v1040mV 8 3505 #define sc_x1_speed_override3_IDriver_Options_v1060mV 9 3506 #define sc_x1_speed_override3_IDriver_Options_v1070mV 10 3507 #define sc_x1_speed_override3_IDriver_Options_v1080mV 11 3508 #define sc_x1_speed_override3_IDriver_Options_v1085mV 12 3509 #define sc_x1_speed_override3_IDriver_Options_v1090mV 13 3510 #define sc_x1_speed_override3_IDriver_Options_v1095mV 14 3511 #define sc_x1_speed_override3_IDriver_Options_v1100mV 15 3512 3513 /**************************************************************************** 3514 * Enums: sc_x1_speed_override3_operationModes 3515 */ 3516 #define sc_x1_speed_override3_operationModes_XGXS 0 3517 #define sc_x1_speed_override3_operationModes_XGXG_nCC 1 3518 #define sc_x1_speed_override3_operationModes_Indlane_OS8 4 3519 #define sc_x1_speed_override3_operationModes_IndLane_OS5 5 3520 #define sc_x1_speed_override3_operationModes_PCI 7 3521 #define sc_x1_speed_override3_operationModes_XGXS_nLQ 8 3522 #define sc_x1_speed_override3_operationModes_XGXS_nLQnCC 9 3523 #define sc_x1_speed_override3_operationModes_PBypass 10 3524 #define sc_x1_speed_override3_operationModes_PBypass_nDSK 11 3525 #define sc_x1_speed_override3_operationModes_ComboCoreMode 12 3526 #define sc_x1_speed_override3_operationModes_Clocks_off 15 3527 3528 /**************************************************************************** 3529 * Enums: sc_x1_speed_override3_synce_enum 3530 */ 3531 #define sc_x1_speed_override3_synce_enum_SYNCE_NO_DIV 0 3532 #define sc_x1_speed_override3_synce_enum_SYNCE_DIV_7 1 3533 #define sc_x1_speed_override3_synce_enum_SYNCE_DIV_11 2 3534 3535 /**************************************************************************** 3536 * Enums: sc_x1_speed_override3_operationSpeeds 3537 */ 3538 #define sc_x1_speed_override3_operationSpeeds_SPEED_2p5G_X1_10p3125 56 3539 #define sc_x1_speed_override3_operationSpeeds_SPEED_1000M_10p3125 55 3540 #define sc_x1_speed_override3_operationSpeeds_SPEED_100M_10p3125 54 3541 #define sc_x1_speed_override3_operationSpeeds_SPEED_10M_10p3125 53 3542 #define sc_x1_speed_override3_operationSpeeds_SPEED_10p5G_X4 50 3543 #define sc_x1_speed_override3_operationSpeeds_SPEED_5G_KR1 49 3544 #define sc_x1_speed_override3_operationSpeeds_SPEED_127G_X12 39 3545 #define sc_x1_speed_override3_operationSpeeds_SPEED_120G_X12 38 3546 #define sc_x1_speed_override3_operationSpeeds_SPEED_107G_X10 37 3547 #define sc_x1_speed_override3_operationSpeeds_SPEED_100G_CR10 36 3548 #define sc_x1_speed_override3_operationSpeeds_SPEED_42G_X4 35 3549 #define sc_x1_speed_override3_operationSpeeds_SPEED_40G_CR4 34 3550 #define sc_x1_speed_override3_operationSpeeds_SPEED_40G_KR4 33 3551 #define sc_x1_speed_override3_operationSpeeds_SPEED_21G_X2 32 3552 #define sc_x1_speed_override3_operationSpeeds_SPEED_20G_CR2 31 3553 #define sc_x1_speed_override3_operationSpeeds_SPEED_20G_KR2 30 3554 #define sc_x1_speed_override3_operationSpeeds_SPEED_10p6_X1 29 3555 #define sc_x1_speed_override3_operationSpeeds_SPEED_10G_KR1 28 3556 #define sc_x1_speed_override3_operationSpeeds_SPEED_40G_X4 27 3557 #define sc_x1_speed_override3_operationSpeeds_SPEED_20G_X2 26 3558 #define sc_x1_speed_override3_operationSpeeds_SPEED_20G_CX2 25 3559 #define sc_x1_speed_override3_operationSpeeds_SPEED_31p5G_KR4 24 3560 #define sc_x1_speed_override3_operationSpeeds_SPEED_31p5G_X4 23 3561 #define sc_x1_speed_override3_operationSpeeds_SPEED_15p75G_X2 22 3562 #define sc_x1_speed_override3_operationSpeeds_SPEED_25p45G_X4 21 3563 #define sc_x1_speed_override3_operationSpeeds_SPEED_12p7G_X2 20 3564 #define sc_x1_speed_override3_operationSpeeds_SPEED_21G_X4 19 3565 #define sc_x1_speed_override3_operationSpeeds_SPEED_10p5G_X2 18 3566 #define sc_x1_speed_override3_operationSpeeds_SPEED_20G_X4 17 3567 #define sc_x1_speed_override3_operationSpeeds_SPEED_10G_X2 16 3568 #define sc_x1_speed_override3_operationSpeeds_SPEED_10G_CX2 15 3569 #define sc_x1_speed_override3_operationSpeeds_SPEED_20G_CX4 14 3570 #define sc_x1_speed_override3_operationSpeeds_SPEED_16G_X4 13 3571 #define sc_x1_speed_override3_operationSpeeds_SPEED_15G_X4 12 3572 #define sc_x1_speed_override3_operationSpeeds_SPEED_13G_X4 11 3573 #define sc_x1_speed_override3_operationSpeeds_SPEED_10G_X4 10 3574 #define sc_x1_speed_override3_operationSpeeds_SPEED_10G_KX4 9 3575 #define sc_x1_speed_override3_operationSpeeds_SPEED_10G_CX4 8 3576 #define sc_x1_speed_override3_operationSpeeds_SPEED_5G_X1 7 3577 #define sc_x1_speed_override3_operationSpeeds_SPEED_2p5G_X1 6 3578 #define sc_x1_speed_override3_operationSpeeds_SPEED_1G_KX1 5 3579 #define sc_x1_speed_override3_operationSpeeds_SPEED_1G_CX1 4 3580 #define sc_x1_speed_override3_operationSpeeds_SPEED_1000M 3 3581 #define sc_x1_speed_override3_operationSpeeds_SPEED_100M 2 3582 #define sc_x1_speed_override3_operationSpeeds_SPEED_10M 1 3583 3584 /**************************************************************************** 3585 * Enums: sc_x1_speed_override3_actualSpeeds 3586 */ 3587 #define sc_x1_speed_override3_actualSpeeds_dr_10M 0 3588 #define sc_x1_speed_override3_actualSpeeds_dr_100M 1 3589 #define sc_x1_speed_override3_actualSpeeds_dr_1G 2 3590 #define sc_x1_speed_override3_actualSpeeds_dr_2p5G 3 3591 #define sc_x1_speed_override3_actualSpeeds_dr_5G_X4 4 3592 #define sc_x1_speed_override3_actualSpeeds_dr_6G_X4 5 3593 #define sc_x1_speed_override3_actualSpeeds_dr_10G_HiG 6 3594 #define sc_x1_speed_override3_actualSpeeds_dr_10G_CX4 7 3595 #define sc_x1_speed_override3_actualSpeeds_dr_12G_HiG 8 3596 #define sc_x1_speed_override3_actualSpeeds_dr_12p5G_X4 9 3597 #define sc_x1_speed_override3_actualSpeeds_dr_13G_X4 10 3598 #define sc_x1_speed_override3_actualSpeeds_dr_15G_X4 11 3599 #define sc_x1_speed_override3_actualSpeeds_dr_16G_X4 12 3600 #define sc_x1_speed_override3_actualSpeeds_dr_1G_KX 13 3601 #define sc_x1_speed_override3_actualSpeeds_dr_10G_KX4 14 3602 #define sc_x1_speed_override3_actualSpeeds_dr_10G_KR 15 3603 #define sc_x1_speed_override3_actualSpeeds_dr_5G 16 3604 #define sc_x1_speed_override3_actualSpeeds_dr_6p4G 17 3605 #define sc_x1_speed_override3_actualSpeeds_dr_20G_X4 18 3606 #define sc_x1_speed_override3_actualSpeeds_dr_21G_X4 19 3607 #define sc_x1_speed_override3_actualSpeeds_dr_25G_X4 20 3608 #define sc_x1_speed_override3_actualSpeeds_dr_10G_HiG_DXGXS 21 3609 #define sc_x1_speed_override3_actualSpeeds_dr_10G_DXGXS 22 3610 #define sc_x1_speed_override3_actualSpeeds_dr_10p5G_HiG_DXGXS 23 3611 #define sc_x1_speed_override3_actualSpeeds_dr_10p5G_DXGXS 24 3612 #define sc_x1_speed_override3_actualSpeeds_dr_12p773G_HiG_DXGXS 25 3613 #define sc_x1_speed_override3_actualSpeeds_dr_12p773G_DXGXS 26 3614 #define sc_x1_speed_override3_actualSpeeds_dr_10G_XFI 27 3615 #define sc_x1_speed_override3_actualSpeeds_dr_40G 28 3616 #define sc_x1_speed_override3_actualSpeeds_dr_20G_HiG_DXGXS 29 3617 #define sc_x1_speed_override3_actualSpeeds_dr_20G_DXGXS 30 3618 #define sc_x1_speed_override3_actualSpeeds_dr_10G_SFI 31 3619 #define sc_x1_speed_override3_actualSpeeds_dr_31p5G 32 3620 #define sc_x1_speed_override3_actualSpeeds_dr_32p7G 33 3621 #define sc_x1_speed_override3_actualSpeeds_dr_20G_SCR 34 3622 #define sc_x1_speed_override3_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 3623 #define sc_x1_speed_override3_actualSpeeds_dr_10G_DXGXS_SCR 36 3624 #define sc_x1_speed_override3_actualSpeeds_dr_12G_R2 37 3625 #define sc_x1_speed_override3_actualSpeeds_dr_10G_X2 38 3626 #define sc_x1_speed_override3_actualSpeeds_dr_40G_KR4 39 3627 #define sc_x1_speed_override3_actualSpeeds_dr_40G_CR4 40 3628 #define sc_x1_speed_override3_actualSpeeds_dr_100G_CR10 41 3629 #define sc_x1_speed_override3_actualSpeeds_dr_15p75G_DXGXS 44 3630 #define sc_x1_speed_override3_actualSpeeds_dr_20G_KR2 57 3631 #define sc_x1_speed_override3_actualSpeeds_dr_20G_CR2 58 3632 3633 /**************************************************************************** 3634 * Enums: sc_x1_speed_override3_actualSpeedsMisc1 3635 */ 3636 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_2500BRCM_X1 16 3637 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_5000BRCM_X4 17 3638 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_6000BRCM_X4 18 3639 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_10GHiGig_X4 19 3640 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_10GBASE_CX4 20 3641 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_12GHiGig_X4 21 3642 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 3643 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_13GHiGig_X4 23 3644 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_15GHiGig_X4 24 3645 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_16GHiGig_X4 25 3646 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_5000BRCM_X1 26 3647 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_6363BRCM_X1 27 3648 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_20GHiGig_X4 28 3649 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_21GHiGig_X4 29 3650 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 3651 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 3652 3653 /**************************************************************************** 3654 * Enums: sc_x1_speed_override3_IndLaneModes 3655 */ 3656 #define sc_x1_speed_override3_IndLaneModes_SWSDR_div2 0 3657 #define sc_x1_speed_override3_IndLaneModes_SWSDR_div1 1 3658 #define sc_x1_speed_override3_IndLaneModes_DWSDR_div2 2 3659 #define sc_x1_speed_override3_IndLaneModes_DWSDR_div1 3 3660 3661 /**************************************************************************** 3662 * Enums: sc_x1_speed_override3_prbsSelect 3663 */ 3664 #define sc_x1_speed_override3_prbsSelect_prbs7 0 3665 #define sc_x1_speed_override3_prbsSelect_prbs15 1 3666 #define sc_x1_speed_override3_prbsSelect_prbs23 2 3667 #define sc_x1_speed_override3_prbsSelect_prbs31 3 3668 3669 /**************************************************************************** 3670 * Enums: sc_x1_speed_override3_vcoDivider 3671 */ 3672 #define sc_x1_speed_override3_vcoDivider_div32 0 3673 #define sc_x1_speed_override3_vcoDivider_div36 1 3674 #define sc_x1_speed_override3_vcoDivider_div40 2 3675 #define sc_x1_speed_override3_vcoDivider_div42 3 3676 #define sc_x1_speed_override3_vcoDivider_div48 4 3677 #define sc_x1_speed_override3_vcoDivider_div50 5 3678 #define sc_x1_speed_override3_vcoDivider_div52 6 3679 #define sc_x1_speed_override3_vcoDivider_div54 7 3680 #define sc_x1_speed_override3_vcoDivider_div60 8 3681 #define sc_x1_speed_override3_vcoDivider_div64 9 3682 #define sc_x1_speed_override3_vcoDivider_div66 10 3683 #define sc_x1_speed_override3_vcoDivider_div68 11 3684 #define sc_x1_speed_override3_vcoDivider_div70 12 3685 #define sc_x1_speed_override3_vcoDivider_div80 13 3686 #define sc_x1_speed_override3_vcoDivider_div92 14 3687 #define sc_x1_speed_override3_vcoDivider_div100 15 3688 3689 /**************************************************************************** 3690 * Enums: sc_x1_speed_override3_refClkSelect 3691 */ 3692 #define sc_x1_speed_override3_refClkSelect_clk_25MHz 0 3693 #define sc_x1_speed_override3_refClkSelect_clk_100MHz 1 3694 #define sc_x1_speed_override3_refClkSelect_clk_125MHz 2 3695 #define sc_x1_speed_override3_refClkSelect_clk_156p25MHz 3 3696 #define sc_x1_speed_override3_refClkSelect_clk_187p5MHz 4 3697 #define sc_x1_speed_override3_refClkSelect_clk_161p25Mhz 5 3698 #define sc_x1_speed_override3_refClkSelect_clk_50Mhz 6 3699 #define sc_x1_speed_override3_refClkSelect_clk_106p25Mhz 7 3700 3701 /**************************************************************************** 3702 * Enums: sc_x1_speed_override3_aerMMDdevTypeSelect 3703 */ 3704 #define sc_x1_speed_override3_aerMMDdevTypeSelect_combo_core 0 3705 #define sc_x1_speed_override3_aerMMDdevTypeSelect_PMA_PMD 1 3706 #define sc_x1_speed_override3_aerMMDdevTypeSelect_PCS 3 3707 #define sc_x1_speed_override3_aerMMDdevTypeSelect_PHY 4 3708 #define sc_x1_speed_override3_aerMMDdevTypeSelect_DTE 5 3709 #define sc_x1_speed_override3_aerMMDdevTypeSelect_CL73_AN 7 3710 3711 /**************************************************************************** 3712 * Enums: sc_x1_speed_override3_aerMMDportSelect 3713 */ 3714 #define sc_x1_speed_override3_aerMMDportSelect_ln0 0 3715 #define sc_x1_speed_override3_aerMMDportSelect_ln1 1 3716 #define sc_x1_speed_override3_aerMMDportSelect_ln2 2 3717 #define sc_x1_speed_override3_aerMMDportSelect_ln3 3 3718 #define sc_x1_speed_override3_aerMMDportSelect_BCST_ln0_1_2_3 511 3719 #define sc_x1_speed_override3_aerMMDportSelect_BCST_ln0_1 512 3720 #define sc_x1_speed_override3_aerMMDportSelect_BCST_ln2_3 513 3721 3722 /**************************************************************************** 3723 * Enums: sc_x1_speed_override3_firmwareModeSelect 3724 */ 3725 #define sc_x1_speed_override3_firmwareModeSelect_DEFAULT 0 3726 #define sc_x1_speed_override3_firmwareModeSelect_SFP_OPT_LR 1 3727 #define sc_x1_speed_override3_firmwareModeSelect_SFP_DAC 2 3728 #define sc_x1_speed_override3_firmwareModeSelect_XLAUI 3 3729 #define sc_x1_speed_override3_firmwareModeSelect_LONG_CH_6G 4 3730 3731 /**************************************************************************** 3732 * Enums: sc_x1_speed_override3_tempIdxSelect 3733 */ 3734 #define sc_x1_speed_override3_tempIdxSelect_LTE__22p9C 15 3735 #define sc_x1_speed_override3_tempIdxSelect_LTE__12p6C 14 3736 #define sc_x1_speed_override3_tempIdxSelect_LTE__3p0C 13 3737 #define sc_x1_speed_override3_tempIdxSelect_LTE_6p7C 12 3738 #define sc_x1_speed_override3_tempIdxSelect_LTE_16p4C 11 3739 #define sc_x1_speed_override3_tempIdxSelect_LTE_26p6C 10 3740 #define sc_x1_speed_override3_tempIdxSelect_LTE_36p3C 9 3741 #define sc_x1_speed_override3_tempIdxSelect_LTE_46p0C 8 3742 #define sc_x1_speed_override3_tempIdxSelect_LTE_56p2C 7 3743 #define sc_x1_speed_override3_tempIdxSelect_LTE_65p9C 6 3744 #define sc_x1_speed_override3_tempIdxSelect_LTE_75p6C 5 3745 #define sc_x1_speed_override3_tempIdxSelect_LTE_85p3C 4 3746 #define sc_x1_speed_override3_tempIdxSelect_LTE_95p5C 3 3747 #define sc_x1_speed_override3_tempIdxSelect_LTE_105p2C 2 3748 #define sc_x1_speed_override3_tempIdxSelect_LTE_114p9C 1 3749 #define sc_x1_speed_override3_tempIdxSelect_LTE_125p1C 0 3750 3751 /**************************************************************************** 3752 * Enums: sc_x4_control_cl36TxEEEStates_l 3753 */ 3754 #define sc_x4_control_cl36TxEEEStates_l_TX_REFRESH 8 3755 #define sc_x4_control_cl36TxEEEStates_l_TX_QUIET 4 3756 #define sc_x4_control_cl36TxEEEStates_l_TX_SLEEP 2 3757 #define sc_x4_control_cl36TxEEEStates_l_TX_ACTIVE 1 3758 3759 /**************************************************************************** 3760 * Enums: sc_x4_control_cl36TxEEEStates_c 3761 */ 3762 #define sc_x4_control_cl36TxEEEStates_c_TX_REFRESH 3 3763 #define sc_x4_control_cl36TxEEEStates_c_TX_QUIET 2 3764 #define sc_x4_control_cl36TxEEEStates_c_TX_SLEEP 1 3765 #define sc_x4_control_cl36TxEEEStates_c_TX_ACTIVE 0 3766 3767 /**************************************************************************** 3768 * Enums: sc_x4_control_cl49TxEEEStates_l 3769 */ 3770 #define sc_x4_control_cl49TxEEEStates_l_SCR_RESET_2 64 3771 #define sc_x4_control_cl49TxEEEStates_l_SCR_RESET_1 32 3772 #define sc_x4_control_cl49TxEEEStates_l_TX_WAKE 16 3773 #define sc_x4_control_cl49TxEEEStates_l_TX_REFRESH 8 3774 #define sc_x4_control_cl49TxEEEStates_l_TX_QUIET 4 3775 #define sc_x4_control_cl49TxEEEStates_l_TX_SLEEP 2 3776 #define sc_x4_control_cl49TxEEEStates_l_TX_ACTIVE 1 3777 3778 /**************************************************************************** 3779 * Enums: sc_x4_control_cl49TxEEEStates_c 3780 */ 3781 #define sc_x4_control_cl49TxEEEStates_c_SCR_RESET_2 6 3782 #define sc_x4_control_cl49TxEEEStates_c_SCR_RESET_1 5 3783 #define sc_x4_control_cl49TxEEEStates_c_TX_WAKE 4 3784 #define sc_x4_control_cl49TxEEEStates_c_TX_REFRESH 3 3785 #define sc_x4_control_cl49TxEEEStates_c_TX_QUIET 2 3786 #define sc_x4_control_cl49TxEEEStates_c_TX_SLEEP 1 3787 #define sc_x4_control_cl49TxEEEStates_c_TX_ACTIVE 0 3788 3789 /**************************************************************************** 3790 * Enums: sc_x4_control_cl36RxEEEStates_l 3791 */ 3792 #define sc_x4_control_cl36RxEEEStates_l_RX_LINK_FAIL 32 3793 #define sc_x4_control_cl36RxEEEStates_l_RX_WTF 16 3794 #define sc_x4_control_cl36RxEEEStates_l_RX_WAKE 8 3795 #define sc_x4_control_cl36RxEEEStates_l_RX_QUIET 4 3796 #define sc_x4_control_cl36RxEEEStates_l_RX_SLEEP 2 3797 #define sc_x4_control_cl36RxEEEStates_l_RX_ACTIVE 1 3798 3799 /**************************************************************************** 3800 * Enums: sc_x4_control_cl36RxEEEStates_c 3801 */ 3802 #define sc_x4_control_cl36RxEEEStates_c_RX_LINK_FAIL 5 3803 #define sc_x4_control_cl36RxEEEStates_c_RX_WTF 4 3804 #define sc_x4_control_cl36RxEEEStates_c_RX_WAKE 3 3805 #define sc_x4_control_cl36RxEEEStates_c_RX_QUIET 2 3806 #define sc_x4_control_cl36RxEEEStates_c_RX_SLEEP 1 3807 #define sc_x4_control_cl36RxEEEStates_c_RX_ACTIVE 0 3808 3809 /**************************************************************************** 3810 * Enums: sc_x4_control_cl49RxEEEStates_l 3811 */ 3812 #define sc_x4_control_cl49RxEEEStates_l_RX_LINK_FAIL 32 3813 #define sc_x4_control_cl49RxEEEStates_l_RX_WTF 16 3814 #define sc_x4_control_cl49RxEEEStates_l_RX_WAKE 8 3815 #define sc_x4_control_cl49RxEEEStates_l_RX_QUIET 4 3816 #define sc_x4_control_cl49RxEEEStates_l_RX_SLEEP 2 3817 #define sc_x4_control_cl49RxEEEStates_l_RX_ACTIVE 1 3818 3819 /**************************************************************************** 3820 * Enums: sc_x4_control_cl49RxEEEStates_c 3821 */ 3822 #define sc_x4_control_cl49RxEEEStates_c_RX_LINK_FAIL 5 3823 #define sc_x4_control_cl49RxEEEStates_c_RX_WTF 4 3824 #define sc_x4_control_cl49RxEEEStates_c_RX_WAKE 3 3825 #define sc_x4_control_cl49RxEEEStates_c_RX_QUIET 2 3826 #define sc_x4_control_cl49RxEEEStates_c_RX_SLEEP 1 3827 #define sc_x4_control_cl49RxEEEStates_c_RX_ACTIVE 0 3828 3829 /**************************************************************************** 3830 * Enums: sc_x4_control_cl48TxEEEStates_l 3831 */ 3832 #define sc_x4_control_cl48TxEEEStates_l_TX_REFRESH 8 3833 #define sc_x4_control_cl48TxEEEStates_l_TX_QUIET 4 3834 #define sc_x4_control_cl48TxEEEStates_l_TX_SLEEP 2 3835 #define sc_x4_control_cl48TxEEEStates_l_TX_ACTIVE 1 3836 3837 /**************************************************************************** 3838 * Enums: sc_x4_control_cl48TxEEEStates_c 3839 */ 3840 #define sc_x4_control_cl48TxEEEStates_c_TX_REFRESH 3 3841 #define sc_x4_control_cl48TxEEEStates_c_TX_QUIET 2 3842 #define sc_x4_control_cl48TxEEEStates_c_TX_SLEEP 1 3843 #define sc_x4_control_cl48TxEEEStates_c_TX_ACTIVE 0 3844 3845 /**************************************************************************** 3846 * Enums: sc_x4_control_cl48RxEEEStates_l 3847 */ 3848 #define sc_x4_control_cl48RxEEEStates_l_RX_LINK_FAIL 32 3849 #define sc_x4_control_cl48RxEEEStates_l_RX_WAKE 16 3850 #define sc_x4_control_cl48RxEEEStates_l_RX_QUIET 8 3851 #define sc_x4_control_cl48RxEEEStates_l_RX_DEACT 4 3852 #define sc_x4_control_cl48RxEEEStates_l_RX_SLEEP 2 3853 #define sc_x4_control_cl48RxEEEStates_l_RX_ACTIVE 1 3854 3855 /**************************************************************************** 3856 * Enums: sc_x4_control_cl48RxEEEStates_c 3857 */ 3858 #define sc_x4_control_cl48RxEEEStates_c_RX_LINK_FAIL 5 3859 #define sc_x4_control_cl48RxEEEStates_c_RX_WAKE 4 3860 #define sc_x4_control_cl48RxEEEStates_c_RX_QUIET 3 3861 #define sc_x4_control_cl48RxEEEStates_c_RX_DEACT 2 3862 #define sc_x4_control_cl48RxEEEStates_c_RX_SLEEP 1 3863 #define sc_x4_control_cl48RxEEEStates_c_RX_ACTIVE 0 3864 3865 /**************************************************************************** 3866 * Enums: sc_x4_control_IQP_Options 3867 */ 3868 #define sc_x4_control_IQP_Options_i50uA 0 3869 #define sc_x4_control_IQP_Options_i100uA 1 3870 #define sc_x4_control_IQP_Options_i150uA 2 3871 #define sc_x4_control_IQP_Options_i200uA 3 3872 #define sc_x4_control_IQP_Options_i250uA 4 3873 #define sc_x4_control_IQP_Options_i300uA 5 3874 #define sc_x4_control_IQP_Options_i350uA 6 3875 #define sc_x4_control_IQP_Options_i400uA 7 3876 #define sc_x4_control_IQP_Options_i450uA 8 3877 #define sc_x4_control_IQP_Options_i500uA 9 3878 #define sc_x4_control_IQP_Options_i550uA 10 3879 #define sc_x4_control_IQP_Options_i600uA 11 3880 #define sc_x4_control_IQP_Options_i650uA 12 3881 #define sc_x4_control_IQP_Options_i700uA 13 3882 #define sc_x4_control_IQP_Options_i750uA 14 3883 #define sc_x4_control_IQP_Options_i800uA 15 3884 3885 /**************************************************************************** 3886 * Enums: sc_x4_control_IDriver_Options 3887 */ 3888 #define sc_x4_control_IDriver_Options_v680mV 0 3889 #define sc_x4_control_IDriver_Options_v730mV 1 3890 #define sc_x4_control_IDriver_Options_v780mV 2 3891 #define sc_x4_control_IDriver_Options_v830mV 3 3892 #define sc_x4_control_IDriver_Options_v880mV 4 3893 #define sc_x4_control_IDriver_Options_v930mV 5 3894 #define sc_x4_control_IDriver_Options_v980mV 6 3895 #define sc_x4_control_IDriver_Options_v1010mV 7 3896 #define sc_x4_control_IDriver_Options_v1040mV 8 3897 #define sc_x4_control_IDriver_Options_v1060mV 9 3898 #define sc_x4_control_IDriver_Options_v1070mV 10 3899 #define sc_x4_control_IDriver_Options_v1080mV 11 3900 #define sc_x4_control_IDriver_Options_v1085mV 12 3901 #define sc_x4_control_IDriver_Options_v1090mV 13 3902 #define sc_x4_control_IDriver_Options_v1095mV 14 3903 #define sc_x4_control_IDriver_Options_v1100mV 15 3904 3905 /**************************************************************************** 3906 * Enums: sc_x4_control_operationModes 3907 */ 3908 #define sc_x4_control_operationModes_XGXS 0 3909 #define sc_x4_control_operationModes_XGXG_nCC 1 3910 #define sc_x4_control_operationModes_Indlane_OS8 4 3911 #define sc_x4_control_operationModes_IndLane_OS5 5 3912 #define sc_x4_control_operationModes_PCI 7 3913 #define sc_x4_control_operationModes_XGXS_nLQ 8 3914 #define sc_x4_control_operationModes_XGXS_nLQnCC 9 3915 #define sc_x4_control_operationModes_PBypass 10 3916 #define sc_x4_control_operationModes_PBypass_nDSK 11 3917 #define sc_x4_control_operationModes_ComboCoreMode 12 3918 #define sc_x4_control_operationModes_Clocks_off 15 3919 3920 /**************************************************************************** 3921 * Enums: sc_x4_control_synce_enum 3922 */ 3923 #define sc_x4_control_synce_enum_SYNCE_NO_DIV 0 3924 #define sc_x4_control_synce_enum_SYNCE_DIV_7 1 3925 #define sc_x4_control_synce_enum_SYNCE_DIV_11 2 3926 3927 /**************************************************************************** 3928 * Enums: sc_x4_control_operationSpeeds 3929 */ 3930 #define sc_x4_control_operationSpeeds_SPEED_2p5G_X1_10p3125 56 3931 #define sc_x4_control_operationSpeeds_SPEED_1000M_10p3125 55 3932 #define sc_x4_control_operationSpeeds_SPEED_100M_10p3125 54 3933 #define sc_x4_control_operationSpeeds_SPEED_10M_10p3125 53 3934 #define sc_x4_control_operationSpeeds_SPEED_10p5G_X4 50 3935 #define sc_x4_control_operationSpeeds_SPEED_5G_KR1 49 3936 #define sc_x4_control_operationSpeeds_SPEED_127G_X12 39 3937 #define sc_x4_control_operationSpeeds_SPEED_120G_X12 38 3938 #define sc_x4_control_operationSpeeds_SPEED_107G_X10 37 3939 #define sc_x4_control_operationSpeeds_SPEED_100G_CR10 36 3940 #define sc_x4_control_operationSpeeds_SPEED_42G_X4 35 3941 #define sc_x4_control_operationSpeeds_SPEED_40G_CR4 34 3942 #define sc_x4_control_operationSpeeds_SPEED_40G_KR4 33 3943 #define sc_x4_control_operationSpeeds_SPEED_21G_X2 32 3944 #define sc_x4_control_operationSpeeds_SPEED_20G_CR2 31 3945 #define sc_x4_control_operationSpeeds_SPEED_20G_KR2 30 3946 #define sc_x4_control_operationSpeeds_SPEED_10p6_X1 29 3947 #define sc_x4_control_operationSpeeds_SPEED_10G_KR1 28 3948 #define sc_x4_control_operationSpeeds_SPEED_40G_X4 27 3949 #define sc_x4_control_operationSpeeds_SPEED_20G_X2 26 3950 #define sc_x4_control_operationSpeeds_SPEED_20G_CX2 25 3951 #define sc_x4_control_operationSpeeds_SPEED_31p5G_KR4 24 3952 #define sc_x4_control_operationSpeeds_SPEED_31p5G_X4 23 3953 #define sc_x4_control_operationSpeeds_SPEED_15p75G_X2 22 3954 #define sc_x4_control_operationSpeeds_SPEED_25p45G_X4 21 3955 #define sc_x4_control_operationSpeeds_SPEED_12p7G_X2 20 3956 #define sc_x4_control_operationSpeeds_SPEED_21G_X4 19 3957 #define sc_x4_control_operationSpeeds_SPEED_10p5G_X2 18 3958 #define sc_x4_control_operationSpeeds_SPEED_20G_X4 17 3959 #define sc_x4_control_operationSpeeds_SPEED_10G_X2 16 3960 #define sc_x4_control_operationSpeeds_SPEED_10G_CX2 15 3961 #define sc_x4_control_operationSpeeds_SPEED_20G_CX4 14 3962 #define sc_x4_control_operationSpeeds_SPEED_16G_X4 13 3963 #define sc_x4_control_operationSpeeds_SPEED_15G_X4 12 3964 #define sc_x4_control_operationSpeeds_SPEED_13G_X4 11 3965 #define sc_x4_control_operationSpeeds_SPEED_10G_X4 10 3966 #define sc_x4_control_operationSpeeds_SPEED_10G_KX4 9 3967 #define sc_x4_control_operationSpeeds_SPEED_10G_CX4 8 3968 #define sc_x4_control_operationSpeeds_SPEED_5G_X1 7 3969 #define sc_x4_control_operationSpeeds_SPEED_2p5G_X1 6 3970 #define sc_x4_control_operationSpeeds_SPEED_1G_KX1 5 3971 #define sc_x4_control_operationSpeeds_SPEED_1G_CX1 4 3972 #define sc_x4_control_operationSpeeds_SPEED_1000M 3 3973 #define sc_x4_control_operationSpeeds_SPEED_100M 2 3974 #define sc_x4_control_operationSpeeds_SPEED_10M 1 3975 3976 /**************************************************************************** 3977 * Enums: sc_x4_control_actualSpeeds 3978 */ 3979 #define sc_x4_control_actualSpeeds_dr_10M 0 3980 #define sc_x4_control_actualSpeeds_dr_100M 1 3981 #define sc_x4_control_actualSpeeds_dr_1G 2 3982 #define sc_x4_control_actualSpeeds_dr_2p5G 3 3983 #define sc_x4_control_actualSpeeds_dr_5G_X4 4 3984 #define sc_x4_control_actualSpeeds_dr_6G_X4 5 3985 #define sc_x4_control_actualSpeeds_dr_10G_HiG 6 3986 #define sc_x4_control_actualSpeeds_dr_10G_CX4 7 3987 #define sc_x4_control_actualSpeeds_dr_12G_HiG 8 3988 #define sc_x4_control_actualSpeeds_dr_12p5G_X4 9 3989 #define sc_x4_control_actualSpeeds_dr_13G_X4 10 3990 #define sc_x4_control_actualSpeeds_dr_15G_X4 11 3991 #define sc_x4_control_actualSpeeds_dr_16G_X4 12 3992 #define sc_x4_control_actualSpeeds_dr_1G_KX 13 3993 #define sc_x4_control_actualSpeeds_dr_10G_KX4 14 3994 #define sc_x4_control_actualSpeeds_dr_10G_KR 15 3995 #define sc_x4_control_actualSpeeds_dr_5G 16 3996 #define sc_x4_control_actualSpeeds_dr_6p4G 17 3997 #define sc_x4_control_actualSpeeds_dr_20G_X4 18 3998 #define sc_x4_control_actualSpeeds_dr_21G_X4 19 3999 #define sc_x4_control_actualSpeeds_dr_25G_X4 20 4000 #define sc_x4_control_actualSpeeds_dr_10G_HiG_DXGXS 21 4001 #define sc_x4_control_actualSpeeds_dr_10G_DXGXS 22 4002 #define sc_x4_control_actualSpeeds_dr_10p5G_HiG_DXGXS 23 4003 #define sc_x4_control_actualSpeeds_dr_10p5G_DXGXS 24 4004 #define sc_x4_control_actualSpeeds_dr_12p773G_HiG_DXGXS 25 4005 #define sc_x4_control_actualSpeeds_dr_12p773G_DXGXS 26 4006 #define sc_x4_control_actualSpeeds_dr_10G_XFI 27 4007 #define sc_x4_control_actualSpeeds_dr_40G 28 4008 #define sc_x4_control_actualSpeeds_dr_20G_HiG_DXGXS 29 4009 #define sc_x4_control_actualSpeeds_dr_20G_DXGXS 30 4010 #define sc_x4_control_actualSpeeds_dr_10G_SFI 31 4011 #define sc_x4_control_actualSpeeds_dr_31p5G 32 4012 #define sc_x4_control_actualSpeeds_dr_32p7G 33 4013 #define sc_x4_control_actualSpeeds_dr_20G_SCR 34 4014 #define sc_x4_control_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 4015 #define sc_x4_control_actualSpeeds_dr_10G_DXGXS_SCR 36 4016 #define sc_x4_control_actualSpeeds_dr_12G_R2 37 4017 #define sc_x4_control_actualSpeeds_dr_10G_X2 38 4018 #define sc_x4_control_actualSpeeds_dr_40G_KR4 39 4019 #define sc_x4_control_actualSpeeds_dr_40G_CR4 40 4020 #define sc_x4_control_actualSpeeds_dr_100G_CR10 41 4021 #define sc_x4_control_actualSpeeds_dr_15p75G_DXGXS 44 4022 #define sc_x4_control_actualSpeeds_dr_20G_KR2 57 4023 #define sc_x4_control_actualSpeeds_dr_20G_CR2 58 4024 4025 /**************************************************************************** 4026 * Enums: sc_x4_control_actualSpeedsMisc1 4027 */ 4028 #define sc_x4_control_actualSpeedsMisc1_dr_2500BRCM_X1 16 4029 #define sc_x4_control_actualSpeedsMisc1_dr_5000BRCM_X4 17 4030 #define sc_x4_control_actualSpeedsMisc1_dr_6000BRCM_X4 18 4031 #define sc_x4_control_actualSpeedsMisc1_dr_10GHiGig_X4 19 4032 #define sc_x4_control_actualSpeedsMisc1_dr_10GBASE_CX4 20 4033 #define sc_x4_control_actualSpeedsMisc1_dr_12GHiGig_X4 21 4034 #define sc_x4_control_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 4035 #define sc_x4_control_actualSpeedsMisc1_dr_13GHiGig_X4 23 4036 #define sc_x4_control_actualSpeedsMisc1_dr_15GHiGig_X4 24 4037 #define sc_x4_control_actualSpeedsMisc1_dr_16GHiGig_X4 25 4038 #define sc_x4_control_actualSpeedsMisc1_dr_5000BRCM_X1 26 4039 #define sc_x4_control_actualSpeedsMisc1_dr_6363BRCM_X1 27 4040 #define sc_x4_control_actualSpeedsMisc1_dr_20GHiGig_X4 28 4041 #define sc_x4_control_actualSpeedsMisc1_dr_21GHiGig_X4 29 4042 #define sc_x4_control_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 4043 #define sc_x4_control_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 4044 4045 /**************************************************************************** 4046 * Enums: sc_x4_control_IndLaneModes 4047 */ 4048 #define sc_x4_control_IndLaneModes_SWSDR_div2 0 4049 #define sc_x4_control_IndLaneModes_SWSDR_div1 1 4050 #define sc_x4_control_IndLaneModes_DWSDR_div2 2 4051 #define sc_x4_control_IndLaneModes_DWSDR_div1 3 4052 4053 /**************************************************************************** 4054 * Enums: sc_x4_control_prbsSelect 4055 */ 4056 #define sc_x4_control_prbsSelect_prbs7 0 4057 #define sc_x4_control_prbsSelect_prbs15 1 4058 #define sc_x4_control_prbsSelect_prbs23 2 4059 #define sc_x4_control_prbsSelect_prbs31 3 4060 4061 /**************************************************************************** 4062 * Enums: sc_x4_control_vcoDivider 4063 */ 4064 #define sc_x4_control_vcoDivider_div32 0 4065 #define sc_x4_control_vcoDivider_div36 1 4066 #define sc_x4_control_vcoDivider_div40 2 4067 #define sc_x4_control_vcoDivider_div42 3 4068 #define sc_x4_control_vcoDivider_div48 4 4069 #define sc_x4_control_vcoDivider_div50 5 4070 #define sc_x4_control_vcoDivider_div52 6 4071 #define sc_x4_control_vcoDivider_div54 7 4072 #define sc_x4_control_vcoDivider_div60 8 4073 #define sc_x4_control_vcoDivider_div64 9 4074 #define sc_x4_control_vcoDivider_div66 10 4075 #define sc_x4_control_vcoDivider_div68 11 4076 #define sc_x4_control_vcoDivider_div70 12 4077 #define sc_x4_control_vcoDivider_div80 13 4078 #define sc_x4_control_vcoDivider_div92 14 4079 #define sc_x4_control_vcoDivider_div100 15 4080 4081 /**************************************************************************** 4082 * Enums: sc_x4_control_refClkSelect 4083 */ 4084 #define sc_x4_control_refClkSelect_clk_25MHz 0 4085 #define sc_x4_control_refClkSelect_clk_100MHz 1 4086 #define sc_x4_control_refClkSelect_clk_125MHz 2 4087 #define sc_x4_control_refClkSelect_clk_156p25MHz 3 4088 #define sc_x4_control_refClkSelect_clk_187p5MHz 4 4089 #define sc_x4_control_refClkSelect_clk_161p25Mhz 5 4090 #define sc_x4_control_refClkSelect_clk_50Mhz 6 4091 #define sc_x4_control_refClkSelect_clk_106p25Mhz 7 4092 4093 /**************************************************************************** 4094 * Enums: sc_x4_control_aerMMDdevTypeSelect 4095 */ 4096 #define sc_x4_control_aerMMDdevTypeSelect_combo_core 0 4097 #define sc_x4_control_aerMMDdevTypeSelect_PMA_PMD 1 4098 #define sc_x4_control_aerMMDdevTypeSelect_PCS 3 4099 #define sc_x4_control_aerMMDdevTypeSelect_PHY 4 4100 #define sc_x4_control_aerMMDdevTypeSelect_DTE 5 4101 #define sc_x4_control_aerMMDdevTypeSelect_CL73_AN 7 4102 4103 /**************************************************************************** 4104 * Enums: sc_x4_control_aerMMDportSelect 4105 */ 4106 #define sc_x4_control_aerMMDportSelect_ln0 0 4107 #define sc_x4_control_aerMMDportSelect_ln1 1 4108 #define sc_x4_control_aerMMDportSelect_ln2 2 4109 #define sc_x4_control_aerMMDportSelect_ln3 3 4110 #define sc_x4_control_aerMMDportSelect_BCST_ln0_1_2_3 511 4111 #define sc_x4_control_aerMMDportSelect_BCST_ln0_1 512 4112 #define sc_x4_control_aerMMDportSelect_BCST_ln2_3 513 4113 4114 /**************************************************************************** 4115 * Enums: sc_x4_control_firmwareModeSelect 4116 */ 4117 #define sc_x4_control_firmwareModeSelect_DEFAULT 0 4118 #define sc_x4_control_firmwareModeSelect_SFP_OPT_LR 1 4119 #define sc_x4_control_firmwareModeSelect_SFP_DAC 2 4120 #define sc_x4_control_firmwareModeSelect_XLAUI 3 4121 #define sc_x4_control_firmwareModeSelect_LONG_CH_6G 4 4122 4123 /**************************************************************************** 4124 * Enums: sc_x4_control_tempIdxSelect 4125 */ 4126 #define sc_x4_control_tempIdxSelect_LTE__22p9C 15 4127 #define sc_x4_control_tempIdxSelect_LTE__12p6C 14 4128 #define sc_x4_control_tempIdxSelect_LTE__3p0C 13 4129 #define sc_x4_control_tempIdxSelect_LTE_6p7C 12 4130 #define sc_x4_control_tempIdxSelect_LTE_16p4C 11 4131 #define sc_x4_control_tempIdxSelect_LTE_26p6C 10 4132 #define sc_x4_control_tempIdxSelect_LTE_36p3C 9 4133 #define sc_x4_control_tempIdxSelect_LTE_46p0C 8 4134 #define sc_x4_control_tempIdxSelect_LTE_56p2C 7 4135 #define sc_x4_control_tempIdxSelect_LTE_65p9C 6 4136 #define sc_x4_control_tempIdxSelect_LTE_75p6C 5 4137 #define sc_x4_control_tempIdxSelect_LTE_85p3C 4 4138 #define sc_x4_control_tempIdxSelect_LTE_95p5C 3 4139 #define sc_x4_control_tempIdxSelect_LTE_105p2C 2 4140 #define sc_x4_control_tempIdxSelect_LTE_114p9C 1 4141 #define sc_x4_control_tempIdxSelect_LTE_125p1C 0 4142 4143 /**************************************************************************** 4144 * Enums: sc_x4_control_sc_seq_status 4145 */ 4146 #define sc_x4_control_sc_seq_status_START 32768 4147 #define sc_x4_control_sc_seq_status_RESET_PCS 16384 4148 #define sc_x4_control_sc_seq_status_RESET_PMD_LANE 8192 4149 #define sc_x4_control_sc_seq_status_RESET_PMD_PLL 4096 4150 #define sc_x4_control_sc_seq_status_APPLY_SPEED_CFG 2048 4151 #define sc_x4_control_sc_seq_status_WAIT_CFG_DONE 1024 4152 #define sc_x4_control_sc_seq_status_ACTIVATE_PMD 512 4153 #define sc_x4_control_sc_seq_status_WAIT_PLL_RESET 256 4154 #define sc_x4_control_sc_seq_status_PLL_LOCK_FAIL 128 4155 #define sc_x4_control_sc_seq_status_ACTIVATE_TX 64 4156 #define sc_x4_control_sc_seq_status_WAIT_PMD_LOCK 32 4157 #define sc_x4_control_sc_seq_status_ACTIVATE_RX 16 4158 #define sc_x4_control_sc_seq_status_PMD_LOCK_FAIL 8 4159 #define sc_x4_control_sc_seq_status_DONE 4 4160 #define sc_x4_control_sc_seq_status_STOP 2 4161 #define sc_x4_control_sc_seq_status_BYPASS 1 4162 4163 /**************************************************************************** 4164 * Enums: sc_x4_final_config_status_cl36TxEEEStates_l 4165 */ 4166 #define sc_x4_final_config_status_cl36TxEEEStates_l_TX_REFRESH 8 4167 #define sc_x4_final_config_status_cl36TxEEEStates_l_TX_QUIET 4 4168 #define sc_x4_final_config_status_cl36TxEEEStates_l_TX_SLEEP 2 4169 #define sc_x4_final_config_status_cl36TxEEEStates_l_TX_ACTIVE 1 4170 4171 /**************************************************************************** 4172 * Enums: sc_x4_final_config_status_cl36TxEEEStates_c 4173 */ 4174 #define sc_x4_final_config_status_cl36TxEEEStates_c_TX_REFRESH 3 4175 #define sc_x4_final_config_status_cl36TxEEEStates_c_TX_QUIET 2 4176 #define sc_x4_final_config_status_cl36TxEEEStates_c_TX_SLEEP 1 4177 #define sc_x4_final_config_status_cl36TxEEEStates_c_TX_ACTIVE 0 4178 4179 /**************************************************************************** 4180 * Enums: sc_x4_final_config_status_cl49TxEEEStates_l 4181 */ 4182 #define sc_x4_final_config_status_cl49TxEEEStates_l_SCR_RESET_2 64 4183 #define sc_x4_final_config_status_cl49TxEEEStates_l_SCR_RESET_1 32 4184 #define sc_x4_final_config_status_cl49TxEEEStates_l_TX_WAKE 16 4185 #define sc_x4_final_config_status_cl49TxEEEStates_l_TX_REFRESH 8 4186 #define sc_x4_final_config_status_cl49TxEEEStates_l_TX_QUIET 4 4187 #define sc_x4_final_config_status_cl49TxEEEStates_l_TX_SLEEP 2 4188 #define sc_x4_final_config_status_cl49TxEEEStates_l_TX_ACTIVE 1 4189 4190 /**************************************************************************** 4191 * Enums: sc_x4_final_config_status_cl49TxEEEStates_c 4192 */ 4193 #define sc_x4_final_config_status_cl49TxEEEStates_c_SCR_RESET_2 6 4194 #define sc_x4_final_config_status_cl49TxEEEStates_c_SCR_RESET_1 5 4195 #define sc_x4_final_config_status_cl49TxEEEStates_c_TX_WAKE 4 4196 #define sc_x4_final_config_status_cl49TxEEEStates_c_TX_REFRESH 3 4197 #define sc_x4_final_config_status_cl49TxEEEStates_c_TX_QUIET 2 4198 #define sc_x4_final_config_status_cl49TxEEEStates_c_TX_SLEEP 1 4199 #define sc_x4_final_config_status_cl49TxEEEStates_c_TX_ACTIVE 0 4200 4201 /**************************************************************************** 4202 * Enums: sc_x4_final_config_status_cl36RxEEEStates_l 4203 */ 4204 #define sc_x4_final_config_status_cl36RxEEEStates_l_RX_LINK_FAIL 32 4205 #define sc_x4_final_config_status_cl36RxEEEStates_l_RX_WTF 16 4206 #define sc_x4_final_config_status_cl36RxEEEStates_l_RX_WAKE 8 4207 #define sc_x4_final_config_status_cl36RxEEEStates_l_RX_QUIET 4 4208 #define sc_x4_final_config_status_cl36RxEEEStates_l_RX_SLEEP 2 4209 #define sc_x4_final_config_status_cl36RxEEEStates_l_RX_ACTIVE 1 4210 4211 /**************************************************************************** 4212 * Enums: sc_x4_final_config_status_cl36RxEEEStates_c 4213 */ 4214 #define sc_x4_final_config_status_cl36RxEEEStates_c_RX_LINK_FAIL 5 4215 #define sc_x4_final_config_status_cl36RxEEEStates_c_RX_WTF 4 4216 #define sc_x4_final_config_status_cl36RxEEEStates_c_RX_WAKE 3 4217 #define sc_x4_final_config_status_cl36RxEEEStates_c_RX_QUIET 2 4218 #define sc_x4_final_config_status_cl36RxEEEStates_c_RX_SLEEP 1 4219 #define sc_x4_final_config_status_cl36RxEEEStates_c_RX_ACTIVE 0 4220 4221 /**************************************************************************** 4222 * Enums: sc_x4_final_config_status_cl49RxEEEStates_l 4223 */ 4224 #define sc_x4_final_config_status_cl49RxEEEStates_l_RX_LINK_FAIL 32 4225 #define sc_x4_final_config_status_cl49RxEEEStates_l_RX_WTF 16 4226 #define sc_x4_final_config_status_cl49RxEEEStates_l_RX_WAKE 8 4227 #define sc_x4_final_config_status_cl49RxEEEStates_l_RX_QUIET 4 4228 #define sc_x4_final_config_status_cl49RxEEEStates_l_RX_SLEEP 2 4229 #define sc_x4_final_config_status_cl49RxEEEStates_l_RX_ACTIVE 1 4230 4231 /**************************************************************************** 4232 * Enums: sc_x4_final_config_status_cl49RxEEEStates_c 4233 */ 4234 #define sc_x4_final_config_status_cl49RxEEEStates_c_RX_LINK_FAIL 5 4235 #define sc_x4_final_config_status_cl49RxEEEStates_c_RX_WTF 4 4236 #define sc_x4_final_config_status_cl49RxEEEStates_c_RX_WAKE 3 4237 #define sc_x4_final_config_status_cl49RxEEEStates_c_RX_QUIET 2 4238 #define sc_x4_final_config_status_cl49RxEEEStates_c_RX_SLEEP 1 4239 #define sc_x4_final_config_status_cl49RxEEEStates_c_RX_ACTIVE 0 4240 4241 /**************************************************************************** 4242 * Enums: sc_x4_final_config_status_cl48TxEEEStates_l 4243 */ 4244 #define sc_x4_final_config_status_cl48TxEEEStates_l_TX_REFRESH 8 4245 #define sc_x4_final_config_status_cl48TxEEEStates_l_TX_QUIET 4 4246 #define sc_x4_final_config_status_cl48TxEEEStates_l_TX_SLEEP 2 4247 #define sc_x4_final_config_status_cl48TxEEEStates_l_TX_ACTIVE 1 4248 4249 /**************************************************************************** 4250 * Enums: sc_x4_final_config_status_cl48TxEEEStates_c 4251 */ 4252 #define sc_x4_final_config_status_cl48TxEEEStates_c_TX_REFRESH 3 4253 #define sc_x4_final_config_status_cl48TxEEEStates_c_TX_QUIET 2 4254 #define sc_x4_final_config_status_cl48TxEEEStates_c_TX_SLEEP 1 4255 #define sc_x4_final_config_status_cl48TxEEEStates_c_TX_ACTIVE 0 4256 4257 /**************************************************************************** 4258 * Enums: sc_x4_final_config_status_cl48RxEEEStates_l 4259 */ 4260 #define sc_x4_final_config_status_cl48RxEEEStates_l_RX_LINK_FAIL 32 4261 #define sc_x4_final_config_status_cl48RxEEEStates_l_RX_WAKE 16 4262 #define sc_x4_final_config_status_cl48RxEEEStates_l_RX_QUIET 8 4263 #define sc_x4_final_config_status_cl48RxEEEStates_l_RX_DEACT 4 4264 #define sc_x4_final_config_status_cl48RxEEEStates_l_RX_SLEEP 2 4265 #define sc_x4_final_config_status_cl48RxEEEStates_l_RX_ACTIVE 1 4266 4267 /**************************************************************************** 4268 * Enums: sc_x4_final_config_status_cl48RxEEEStates_c 4269 */ 4270 #define sc_x4_final_config_status_cl48RxEEEStates_c_RX_LINK_FAIL 5 4271 #define sc_x4_final_config_status_cl48RxEEEStates_c_RX_WAKE 4 4272 #define sc_x4_final_config_status_cl48RxEEEStates_c_RX_QUIET 3 4273 #define sc_x4_final_config_status_cl48RxEEEStates_c_RX_DEACT 2 4274 #define sc_x4_final_config_status_cl48RxEEEStates_c_RX_SLEEP 1 4275 #define sc_x4_final_config_status_cl48RxEEEStates_c_RX_ACTIVE 0 4276 4277 /**************************************************************************** 4278 * Enums: sc_x4_final_config_status_IQP_Options 4279 */ 4280 #define sc_x4_final_config_status_IQP_Options_i50uA 0 4281 #define sc_x4_final_config_status_IQP_Options_i100uA 1 4282 #define sc_x4_final_config_status_IQP_Options_i150uA 2 4283 #define sc_x4_final_config_status_IQP_Options_i200uA 3 4284 #define sc_x4_final_config_status_IQP_Options_i250uA 4 4285 #define sc_x4_final_config_status_IQP_Options_i300uA 5 4286 #define sc_x4_final_config_status_IQP_Options_i350uA 6 4287 #define sc_x4_final_config_status_IQP_Options_i400uA 7 4288 #define sc_x4_final_config_status_IQP_Options_i450uA 8 4289 #define sc_x4_final_config_status_IQP_Options_i500uA 9 4290 #define sc_x4_final_config_status_IQP_Options_i550uA 10 4291 #define sc_x4_final_config_status_IQP_Options_i600uA 11 4292 #define sc_x4_final_config_status_IQP_Options_i650uA 12 4293 #define sc_x4_final_config_status_IQP_Options_i700uA 13 4294 #define sc_x4_final_config_status_IQP_Options_i750uA 14 4295 #define sc_x4_final_config_status_IQP_Options_i800uA 15 4296 4297 /**************************************************************************** 4298 * Enums: sc_x4_final_config_status_IDriver_Options 4299 */ 4300 #define sc_x4_final_config_status_IDriver_Options_v680mV 0 4301 #define sc_x4_final_config_status_IDriver_Options_v730mV 1 4302 #define sc_x4_final_config_status_IDriver_Options_v780mV 2 4303 #define sc_x4_final_config_status_IDriver_Options_v830mV 3 4304 #define sc_x4_final_config_status_IDriver_Options_v880mV 4 4305 #define sc_x4_final_config_status_IDriver_Options_v930mV 5 4306 #define sc_x4_final_config_status_IDriver_Options_v980mV 6 4307 #define sc_x4_final_config_status_IDriver_Options_v1010mV 7 4308 #define sc_x4_final_config_status_IDriver_Options_v1040mV 8 4309 #define sc_x4_final_config_status_IDriver_Options_v1060mV 9 4310 #define sc_x4_final_config_status_IDriver_Options_v1070mV 10 4311 #define sc_x4_final_config_status_IDriver_Options_v1080mV 11 4312 #define sc_x4_final_config_status_IDriver_Options_v1085mV 12 4313 #define sc_x4_final_config_status_IDriver_Options_v1090mV 13 4314 #define sc_x4_final_config_status_IDriver_Options_v1095mV 14 4315 #define sc_x4_final_config_status_IDriver_Options_v1100mV 15 4316 4317 /**************************************************************************** 4318 * Enums: sc_x4_final_config_status_operationModes 4319 */ 4320 #define sc_x4_final_config_status_operationModes_XGXS 0 4321 #define sc_x4_final_config_status_operationModes_XGXG_nCC 1 4322 #define sc_x4_final_config_status_operationModes_Indlane_OS8 4 4323 #define sc_x4_final_config_status_operationModes_IndLane_OS5 5 4324 #define sc_x4_final_config_status_operationModes_PCI 7 4325 #define sc_x4_final_config_status_operationModes_XGXS_nLQ 8 4326 #define sc_x4_final_config_status_operationModes_XGXS_nLQnCC 9 4327 #define sc_x4_final_config_status_operationModes_PBypass 10 4328 #define sc_x4_final_config_status_operationModes_PBypass_nDSK 11 4329 #define sc_x4_final_config_status_operationModes_ComboCoreMode 12 4330 #define sc_x4_final_config_status_operationModes_Clocks_off 15 4331 4332 /**************************************************************************** 4333 * Enums: sc_x4_final_config_status_synce_enum 4334 */ 4335 #define sc_x4_final_config_status_synce_enum_SYNCE_NO_DIV 0 4336 #define sc_x4_final_config_status_synce_enum_SYNCE_DIV_7 1 4337 #define sc_x4_final_config_status_synce_enum_SYNCE_DIV_11 2 4338 4339 /**************************************************************************** 4340 * Enums: sc_x4_final_config_status_operationSpeeds 4341 */ 4342 #define sc_x4_final_config_status_operationSpeeds_SPEED_2p5G_X1_10p3125 56 4343 #define sc_x4_final_config_status_operationSpeeds_SPEED_1000M_10p3125 55 4344 #define sc_x4_final_config_status_operationSpeeds_SPEED_100M_10p3125 54 4345 #define sc_x4_final_config_status_operationSpeeds_SPEED_10M_10p3125 53 4346 #define sc_x4_final_config_status_operationSpeeds_SPEED_10p5G_X4 50 4347 #define sc_x4_final_config_status_operationSpeeds_SPEED_5G_KR1 49 4348 #define sc_x4_final_config_status_operationSpeeds_SPEED_127G_X12 39 4349 #define sc_x4_final_config_status_operationSpeeds_SPEED_120G_X12 38 4350 #define sc_x4_final_config_status_operationSpeeds_SPEED_107G_X10 37 4351 #define sc_x4_final_config_status_operationSpeeds_SPEED_100G_CR10 36 4352 #define sc_x4_final_config_status_operationSpeeds_SPEED_42G_X4 35 4353 #define sc_x4_final_config_status_operationSpeeds_SPEED_40G_CR4 34 4354 #define sc_x4_final_config_status_operationSpeeds_SPEED_40G_KR4 33 4355 #define sc_x4_final_config_status_operationSpeeds_SPEED_21G_X2 32 4356 #define sc_x4_final_config_status_operationSpeeds_SPEED_20G_CR2 31 4357 #define sc_x4_final_config_status_operationSpeeds_SPEED_20G_KR2 30 4358 #define sc_x4_final_config_status_operationSpeeds_SPEED_10p6_X1 29 4359 #define sc_x4_final_config_status_operationSpeeds_SPEED_10G_KR1 28 4360 #define sc_x4_final_config_status_operationSpeeds_SPEED_40G_X4 27 4361 #define sc_x4_final_config_status_operationSpeeds_SPEED_20G_X2 26 4362 #define sc_x4_final_config_status_operationSpeeds_SPEED_20G_CX2 25 4363 #define sc_x4_final_config_status_operationSpeeds_SPEED_31p5G_KR4 24 4364 #define sc_x4_final_config_status_operationSpeeds_SPEED_31p5G_X4 23 4365 #define sc_x4_final_config_status_operationSpeeds_SPEED_15p75G_X2 22 4366 #define sc_x4_final_config_status_operationSpeeds_SPEED_25p45G_X4 21 4367 #define sc_x4_final_config_status_operationSpeeds_SPEED_12p7G_X2 20 4368 #define sc_x4_final_config_status_operationSpeeds_SPEED_21G_X4 19 4369 #define sc_x4_final_config_status_operationSpeeds_SPEED_10p5G_X2 18 4370 #define sc_x4_final_config_status_operationSpeeds_SPEED_20G_X4 17 4371 #define sc_x4_final_config_status_operationSpeeds_SPEED_10G_X2 16 4372 #define sc_x4_final_config_status_operationSpeeds_SPEED_10G_CX2 15 4373 #define sc_x4_final_config_status_operationSpeeds_SPEED_20G_CX4 14 4374 #define sc_x4_final_config_status_operationSpeeds_SPEED_16G_X4 13 4375 #define sc_x4_final_config_status_operationSpeeds_SPEED_15G_X4 12 4376 #define sc_x4_final_config_status_operationSpeeds_SPEED_13G_X4 11 4377 #define sc_x4_final_config_status_operationSpeeds_SPEED_10G_X4 10 4378 #define sc_x4_final_config_status_operationSpeeds_SPEED_10G_KX4 9 4379 #define sc_x4_final_config_status_operationSpeeds_SPEED_10G_CX4 8 4380 #define sc_x4_final_config_status_operationSpeeds_SPEED_5G_X1 7 4381 #define sc_x4_final_config_status_operationSpeeds_SPEED_2p5G_X1 6 4382 #define sc_x4_final_config_status_operationSpeeds_SPEED_1G_KX1 5 4383 #define sc_x4_final_config_status_operationSpeeds_SPEED_1G_CX1 4 4384 #define sc_x4_final_config_status_operationSpeeds_SPEED_1000M 3 4385 #define sc_x4_final_config_status_operationSpeeds_SPEED_100M 2 4386 #define sc_x4_final_config_status_operationSpeeds_SPEED_10M 1 4387 4388 /**************************************************************************** 4389 * Enums: sc_x4_final_config_status_actualSpeeds 4390 */ 4391 #define sc_x4_final_config_status_actualSpeeds_dr_10M 0 4392 #define sc_x4_final_config_status_actualSpeeds_dr_100M 1 4393 #define sc_x4_final_config_status_actualSpeeds_dr_1G 2 4394 #define sc_x4_final_config_status_actualSpeeds_dr_2p5G 3 4395 #define sc_x4_final_config_status_actualSpeeds_dr_5G_X4 4 4396 #define sc_x4_final_config_status_actualSpeeds_dr_6G_X4 5 4397 #define sc_x4_final_config_status_actualSpeeds_dr_10G_HiG 6 4398 #define sc_x4_final_config_status_actualSpeeds_dr_10G_CX4 7 4399 #define sc_x4_final_config_status_actualSpeeds_dr_12G_HiG 8 4400 #define sc_x4_final_config_status_actualSpeeds_dr_12p5G_X4 9 4401 #define sc_x4_final_config_status_actualSpeeds_dr_13G_X4 10 4402 #define sc_x4_final_config_status_actualSpeeds_dr_15G_X4 11 4403 #define sc_x4_final_config_status_actualSpeeds_dr_16G_X4 12 4404 #define sc_x4_final_config_status_actualSpeeds_dr_1G_KX 13 4405 #define sc_x4_final_config_status_actualSpeeds_dr_10G_KX4 14 4406 #define sc_x4_final_config_status_actualSpeeds_dr_10G_KR 15 4407 #define sc_x4_final_config_status_actualSpeeds_dr_5G 16 4408 #define sc_x4_final_config_status_actualSpeeds_dr_6p4G 17 4409 #define sc_x4_final_config_status_actualSpeeds_dr_20G_X4 18 4410 #define sc_x4_final_config_status_actualSpeeds_dr_21G_X4 19 4411 #define sc_x4_final_config_status_actualSpeeds_dr_25G_X4 20 4412 #define sc_x4_final_config_status_actualSpeeds_dr_10G_HiG_DXGXS 21 4413 #define sc_x4_final_config_status_actualSpeeds_dr_10G_DXGXS 22 4414 #define sc_x4_final_config_status_actualSpeeds_dr_10p5G_HiG_DXGXS 23 4415 #define sc_x4_final_config_status_actualSpeeds_dr_10p5G_DXGXS 24 4416 #define sc_x4_final_config_status_actualSpeeds_dr_12p773G_HiG_DXGXS 25 4417 #define sc_x4_final_config_status_actualSpeeds_dr_12p773G_DXGXS 26 4418 #define sc_x4_final_config_status_actualSpeeds_dr_10G_XFI 27 4419 #define sc_x4_final_config_status_actualSpeeds_dr_40G 28 4420 #define sc_x4_final_config_status_actualSpeeds_dr_20G_HiG_DXGXS 29 4421 #define sc_x4_final_config_status_actualSpeeds_dr_20G_DXGXS 30 4422 #define sc_x4_final_config_status_actualSpeeds_dr_10G_SFI 31 4423 #define sc_x4_final_config_status_actualSpeeds_dr_31p5G 32 4424 #define sc_x4_final_config_status_actualSpeeds_dr_32p7G 33 4425 #define sc_x4_final_config_status_actualSpeeds_dr_20G_SCR 34 4426 #define sc_x4_final_config_status_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 4427 #define sc_x4_final_config_status_actualSpeeds_dr_10G_DXGXS_SCR 36 4428 #define sc_x4_final_config_status_actualSpeeds_dr_12G_R2 37 4429 #define sc_x4_final_config_status_actualSpeeds_dr_10G_X2 38 4430 #define sc_x4_final_config_status_actualSpeeds_dr_40G_KR4 39 4431 #define sc_x4_final_config_status_actualSpeeds_dr_40G_CR4 40 4432 #define sc_x4_final_config_status_actualSpeeds_dr_100G_CR10 41 4433 #define sc_x4_final_config_status_actualSpeeds_dr_15p75G_DXGXS 44 4434 #define sc_x4_final_config_status_actualSpeeds_dr_20G_KR2 57 4435 #define sc_x4_final_config_status_actualSpeeds_dr_20G_CR2 58 4436 4437 /**************************************************************************** 4438 * Enums: sc_x4_final_config_status_actualSpeedsMisc1 4439 */ 4440 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_2500BRCM_X1 16 4441 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_5000BRCM_X4 17 4442 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_6000BRCM_X4 18 4443 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_10GHiGig_X4 19 4444 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_10GBASE_CX4 20 4445 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_12GHiGig_X4 21 4446 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 4447 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_13GHiGig_X4 23 4448 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_15GHiGig_X4 24 4449 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_16GHiGig_X4 25 4450 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_5000BRCM_X1 26 4451 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_6363BRCM_X1 27 4452 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_20GHiGig_X4 28 4453 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_21GHiGig_X4 29 4454 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 4455 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 4456 4457 /**************************************************************************** 4458 * Enums: sc_x4_final_config_status_IndLaneModes 4459 */ 4460 #define sc_x4_final_config_status_IndLaneModes_SWSDR_div2 0 4461 #define sc_x4_final_config_status_IndLaneModes_SWSDR_div1 1 4462 #define sc_x4_final_config_status_IndLaneModes_DWSDR_div2 2 4463 #define sc_x4_final_config_status_IndLaneModes_DWSDR_div1 3 4464 4465 /**************************************************************************** 4466 * Enums: sc_x4_final_config_status_prbsSelect 4467 */ 4468 #define sc_x4_final_config_status_prbsSelect_prbs7 0 4469 #define sc_x4_final_config_status_prbsSelect_prbs15 1 4470 #define sc_x4_final_config_status_prbsSelect_prbs23 2 4471 #define sc_x4_final_config_status_prbsSelect_prbs31 3 4472 4473 /**************************************************************************** 4474 * Enums: sc_x4_final_config_status_vcoDivider 4475 */ 4476 #define sc_x4_final_config_status_vcoDivider_div32 0 4477 #define sc_x4_final_config_status_vcoDivider_div36 1 4478 #define sc_x4_final_config_status_vcoDivider_div40 2 4479 #define sc_x4_final_config_status_vcoDivider_div42 3 4480 #define sc_x4_final_config_status_vcoDivider_div48 4 4481 #define sc_x4_final_config_status_vcoDivider_div50 5 4482 #define sc_x4_final_config_status_vcoDivider_div52 6 4483 #define sc_x4_final_config_status_vcoDivider_div54 7 4484 #define sc_x4_final_config_status_vcoDivider_div60 8 4485 #define sc_x4_final_config_status_vcoDivider_div64 9 4486 #define sc_x4_final_config_status_vcoDivider_div66 10 4487 #define sc_x4_final_config_status_vcoDivider_div68 11 4488 #define sc_x4_final_config_status_vcoDivider_div70 12 4489 #define sc_x4_final_config_status_vcoDivider_div80 13 4490 #define sc_x4_final_config_status_vcoDivider_div92 14 4491 #define sc_x4_final_config_status_vcoDivider_div100 15 4492 4493 /**************************************************************************** 4494 * Enums: sc_x4_final_config_status_refClkSelect 4495 */ 4496 #define sc_x4_final_config_status_refClkSelect_clk_25MHz 0 4497 #define sc_x4_final_config_status_refClkSelect_clk_100MHz 1 4498 #define sc_x4_final_config_status_refClkSelect_clk_125MHz 2 4499 #define sc_x4_final_config_status_refClkSelect_clk_156p25MHz 3 4500 #define sc_x4_final_config_status_refClkSelect_clk_187p5MHz 4 4501 #define sc_x4_final_config_status_refClkSelect_clk_161p25Mhz 5 4502 #define sc_x4_final_config_status_refClkSelect_clk_50Mhz 6 4503 #define sc_x4_final_config_status_refClkSelect_clk_106p25Mhz 7 4504 4505 /**************************************************************************** 4506 * Enums: sc_x4_final_config_status_aerMMDdevTypeSelect 4507 */ 4508 #define sc_x4_final_config_status_aerMMDdevTypeSelect_combo_core 0 4509 #define sc_x4_final_config_status_aerMMDdevTypeSelect_PMA_PMD 1 4510 #define sc_x4_final_config_status_aerMMDdevTypeSelect_PCS 3 4511 #define sc_x4_final_config_status_aerMMDdevTypeSelect_PHY 4 4512 #define sc_x4_final_config_status_aerMMDdevTypeSelect_DTE 5 4513 #define sc_x4_final_config_status_aerMMDdevTypeSelect_CL73_AN 7 4514 4515 /**************************************************************************** 4516 * Enums: sc_x4_final_config_status_aerMMDportSelect 4517 */ 4518 #define sc_x4_final_config_status_aerMMDportSelect_ln0 0 4519 #define sc_x4_final_config_status_aerMMDportSelect_ln1 1 4520 #define sc_x4_final_config_status_aerMMDportSelect_ln2 2 4521 #define sc_x4_final_config_status_aerMMDportSelect_ln3 3 4522 #define sc_x4_final_config_status_aerMMDportSelect_BCST_ln0_1_2_3 511 4523 #define sc_x4_final_config_status_aerMMDportSelect_BCST_ln0_1 512 4524 #define sc_x4_final_config_status_aerMMDportSelect_BCST_ln2_3 513 4525 4526 /**************************************************************************** 4527 * Enums: sc_x4_final_config_status_firmwareModeSelect 4528 */ 4529 #define sc_x4_final_config_status_firmwareModeSelect_DEFAULT 0 4530 #define sc_x4_final_config_status_firmwareModeSelect_SFP_OPT_LR 1 4531 #define sc_x4_final_config_status_firmwareModeSelect_SFP_DAC 2 4532 #define sc_x4_final_config_status_firmwareModeSelect_XLAUI 3 4533 #define sc_x4_final_config_status_firmwareModeSelect_LONG_CH_6G 4 4534 4535 /**************************************************************************** 4536 * Enums: sc_x4_final_config_status_tempIdxSelect 4537 */ 4538 #define sc_x4_final_config_status_tempIdxSelect_LTE__22p9C 15 4539 #define sc_x4_final_config_status_tempIdxSelect_LTE__12p6C 14 4540 #define sc_x4_final_config_status_tempIdxSelect_LTE__3p0C 13 4541 #define sc_x4_final_config_status_tempIdxSelect_LTE_6p7C 12 4542 #define sc_x4_final_config_status_tempIdxSelect_LTE_16p4C 11 4543 #define sc_x4_final_config_status_tempIdxSelect_LTE_26p6C 10 4544 #define sc_x4_final_config_status_tempIdxSelect_LTE_36p3C 9 4545 #define sc_x4_final_config_status_tempIdxSelect_LTE_46p0C 8 4546 #define sc_x4_final_config_status_tempIdxSelect_LTE_56p2C 7 4547 #define sc_x4_final_config_status_tempIdxSelect_LTE_65p9C 6 4548 #define sc_x4_final_config_status_tempIdxSelect_LTE_75p6C 5 4549 #define sc_x4_final_config_status_tempIdxSelect_LTE_85p3C 4 4550 #define sc_x4_final_config_status_tempIdxSelect_LTE_95p5C 3 4551 #define sc_x4_final_config_status_tempIdxSelect_LTE_105p2C 2 4552 #define sc_x4_final_config_status_tempIdxSelect_LTE_114p9C 1 4553 #define sc_x4_final_config_status_tempIdxSelect_LTE_125p1C 0 4554 4555 /**************************************************************************** 4556 * Enums: tx_x1_status0_tla_pll_status 4557 */ 4558 #define tx_x1_status0_tla_pll_status_INIT 1 4559 #define tx_x1_status0_tla_pll_status_PLL_LOCKED 2 4560 #define tx_x1_status0_tla_pll_status_RESET_PLL 4 4561 #define tx_x1_status0_tla_pll_status_CHANGE_PLL_MODE 8 4562 #define tx_x1_status0_tla_pll_status_PLL_SWITCH 16 4563 4564 /**************************************************************************** 4565 * Enums: tx_x4_credit_gen0_cl36TxEEEStates_l 4566 */ 4567 #define tx_x4_credit_gen0_cl36TxEEEStates_l_TX_REFRESH 8 4568 #define tx_x4_credit_gen0_cl36TxEEEStates_l_TX_QUIET 4 4569 #define tx_x4_credit_gen0_cl36TxEEEStates_l_TX_SLEEP 2 4570 #define tx_x4_credit_gen0_cl36TxEEEStates_l_TX_ACTIVE 1 4571 4572 /**************************************************************************** 4573 * Enums: tx_x4_credit_gen0_cl36TxEEEStates_c 4574 */ 4575 #define tx_x4_credit_gen0_cl36TxEEEStates_c_TX_REFRESH 3 4576 #define tx_x4_credit_gen0_cl36TxEEEStates_c_TX_QUIET 2 4577 #define tx_x4_credit_gen0_cl36TxEEEStates_c_TX_SLEEP 1 4578 #define tx_x4_credit_gen0_cl36TxEEEStates_c_TX_ACTIVE 0 4579 4580 /**************************************************************************** 4581 * Enums: tx_x4_credit_gen0_cl49TxEEEStates_l 4582 */ 4583 #define tx_x4_credit_gen0_cl49TxEEEStates_l_SCR_RESET_2 64 4584 #define tx_x4_credit_gen0_cl49TxEEEStates_l_SCR_RESET_1 32 4585 #define tx_x4_credit_gen0_cl49TxEEEStates_l_TX_WAKE 16 4586 #define tx_x4_credit_gen0_cl49TxEEEStates_l_TX_REFRESH 8 4587 #define tx_x4_credit_gen0_cl49TxEEEStates_l_TX_QUIET 4 4588 #define tx_x4_credit_gen0_cl49TxEEEStates_l_TX_SLEEP 2 4589 #define tx_x4_credit_gen0_cl49TxEEEStates_l_TX_ACTIVE 1 4590 4591 /**************************************************************************** 4592 * Enums: tx_x4_credit_gen0_cl49TxEEEStates_c 4593 */ 4594 #define tx_x4_credit_gen0_cl49TxEEEStates_c_SCR_RESET_2 6 4595 #define tx_x4_credit_gen0_cl49TxEEEStates_c_SCR_RESET_1 5 4596 #define tx_x4_credit_gen0_cl49TxEEEStates_c_TX_WAKE 4 4597 #define tx_x4_credit_gen0_cl49TxEEEStates_c_TX_REFRESH 3 4598 #define tx_x4_credit_gen0_cl49TxEEEStates_c_TX_QUIET 2 4599 #define tx_x4_credit_gen0_cl49TxEEEStates_c_TX_SLEEP 1 4600 #define tx_x4_credit_gen0_cl49TxEEEStates_c_TX_ACTIVE 0 4601 4602 /**************************************************************************** 4603 * Enums: tx_x4_credit_gen0_cl36RxEEEStates_l 4604 */ 4605 #define tx_x4_credit_gen0_cl36RxEEEStates_l_RX_LINK_FAIL 32 4606 #define tx_x4_credit_gen0_cl36RxEEEStates_l_RX_WTF 16 4607 #define tx_x4_credit_gen0_cl36RxEEEStates_l_RX_WAKE 8 4608 #define tx_x4_credit_gen0_cl36RxEEEStates_l_RX_QUIET 4 4609 #define tx_x4_credit_gen0_cl36RxEEEStates_l_RX_SLEEP 2 4610 #define tx_x4_credit_gen0_cl36RxEEEStates_l_RX_ACTIVE 1 4611 4612 /**************************************************************************** 4613 * Enums: tx_x4_credit_gen0_cl36RxEEEStates_c 4614 */ 4615 #define tx_x4_credit_gen0_cl36RxEEEStates_c_RX_LINK_FAIL 5 4616 #define tx_x4_credit_gen0_cl36RxEEEStates_c_RX_WTF 4 4617 #define tx_x4_credit_gen0_cl36RxEEEStates_c_RX_WAKE 3 4618 #define tx_x4_credit_gen0_cl36RxEEEStates_c_RX_QUIET 2 4619 #define tx_x4_credit_gen0_cl36RxEEEStates_c_RX_SLEEP 1 4620 #define tx_x4_credit_gen0_cl36RxEEEStates_c_RX_ACTIVE 0 4621 4622 /**************************************************************************** 4623 * Enums: tx_x4_credit_gen0_cl49RxEEEStates_l 4624 */ 4625 #define tx_x4_credit_gen0_cl49RxEEEStates_l_RX_LINK_FAIL 32 4626 #define tx_x4_credit_gen0_cl49RxEEEStates_l_RX_WTF 16 4627 #define tx_x4_credit_gen0_cl49RxEEEStates_l_RX_WAKE 8 4628 #define tx_x4_credit_gen0_cl49RxEEEStates_l_RX_QUIET 4 4629 #define tx_x4_credit_gen0_cl49RxEEEStates_l_RX_SLEEP 2 4630 #define tx_x4_credit_gen0_cl49RxEEEStates_l_RX_ACTIVE 1 4631 4632 /**************************************************************************** 4633 * Enums: tx_x4_credit_gen0_cl49RxEEEStates_c 4634 */ 4635 #define tx_x4_credit_gen0_cl49RxEEEStates_c_RX_LINK_FAIL 5 4636 #define tx_x4_credit_gen0_cl49RxEEEStates_c_RX_WTF 4 4637 #define tx_x4_credit_gen0_cl49RxEEEStates_c_RX_WAKE 3 4638 #define tx_x4_credit_gen0_cl49RxEEEStates_c_RX_QUIET 2 4639 #define tx_x4_credit_gen0_cl49RxEEEStates_c_RX_SLEEP 1 4640 #define tx_x4_credit_gen0_cl49RxEEEStates_c_RX_ACTIVE 0 4641 4642 /**************************************************************************** 4643 * Enums: tx_x4_credit_gen0_cl48TxEEEStates_l 4644 */ 4645 #define tx_x4_credit_gen0_cl48TxEEEStates_l_TX_REFRESH 8 4646 #define tx_x4_credit_gen0_cl48TxEEEStates_l_TX_QUIET 4 4647 #define tx_x4_credit_gen0_cl48TxEEEStates_l_TX_SLEEP 2 4648 #define tx_x4_credit_gen0_cl48TxEEEStates_l_TX_ACTIVE 1 4649 4650 /**************************************************************************** 4651 * Enums: tx_x4_credit_gen0_cl48TxEEEStates_c 4652 */ 4653 #define tx_x4_credit_gen0_cl48TxEEEStates_c_TX_REFRESH 3 4654 #define tx_x4_credit_gen0_cl48TxEEEStates_c_TX_QUIET 2 4655 #define tx_x4_credit_gen0_cl48TxEEEStates_c_TX_SLEEP 1 4656 #define tx_x4_credit_gen0_cl48TxEEEStates_c_TX_ACTIVE 0 4657 4658 /**************************************************************************** 4659 * Enums: tx_x4_credit_gen0_cl48RxEEEStates_l 4660 */ 4661 #define tx_x4_credit_gen0_cl48RxEEEStates_l_RX_LINK_FAIL 32 4662 #define tx_x4_credit_gen0_cl48RxEEEStates_l_RX_WAKE 16 4663 #define tx_x4_credit_gen0_cl48RxEEEStates_l_RX_QUIET 8 4664 #define tx_x4_credit_gen0_cl48RxEEEStates_l_RX_DEACT 4 4665 #define tx_x4_credit_gen0_cl48RxEEEStates_l_RX_SLEEP 2 4666 #define tx_x4_credit_gen0_cl48RxEEEStates_l_RX_ACTIVE 1 4667 4668 /**************************************************************************** 4669 * Enums: tx_x4_credit_gen0_cl48RxEEEStates_c 4670 */ 4671 #define tx_x4_credit_gen0_cl48RxEEEStates_c_RX_LINK_FAIL 5 4672 #define tx_x4_credit_gen0_cl48RxEEEStates_c_RX_WAKE 4 4673 #define tx_x4_credit_gen0_cl48RxEEEStates_c_RX_QUIET 3 4674 #define tx_x4_credit_gen0_cl48RxEEEStates_c_RX_DEACT 2 4675 #define tx_x4_credit_gen0_cl48RxEEEStates_c_RX_SLEEP 1 4676 #define tx_x4_credit_gen0_cl48RxEEEStates_c_RX_ACTIVE 0 4677 4678 /**************************************************************************** 4679 * Enums: tx_x4_credit_gen0_IQP_Options 4680 */ 4681 #define tx_x4_credit_gen0_IQP_Options_i50uA 0 4682 #define tx_x4_credit_gen0_IQP_Options_i100uA 1 4683 #define tx_x4_credit_gen0_IQP_Options_i150uA 2 4684 #define tx_x4_credit_gen0_IQP_Options_i200uA 3 4685 #define tx_x4_credit_gen0_IQP_Options_i250uA 4 4686 #define tx_x4_credit_gen0_IQP_Options_i300uA 5 4687 #define tx_x4_credit_gen0_IQP_Options_i350uA 6 4688 #define tx_x4_credit_gen0_IQP_Options_i400uA 7 4689 #define tx_x4_credit_gen0_IQP_Options_i450uA 8 4690 #define tx_x4_credit_gen0_IQP_Options_i500uA 9 4691 #define tx_x4_credit_gen0_IQP_Options_i550uA 10 4692 #define tx_x4_credit_gen0_IQP_Options_i600uA 11 4693 #define tx_x4_credit_gen0_IQP_Options_i650uA 12 4694 #define tx_x4_credit_gen0_IQP_Options_i700uA 13 4695 #define tx_x4_credit_gen0_IQP_Options_i750uA 14 4696 #define tx_x4_credit_gen0_IQP_Options_i800uA 15 4697 4698 /**************************************************************************** 4699 * Enums: tx_x4_credit_gen0_IDriver_Options 4700 */ 4701 #define tx_x4_credit_gen0_IDriver_Options_v680mV 0 4702 #define tx_x4_credit_gen0_IDriver_Options_v730mV 1 4703 #define tx_x4_credit_gen0_IDriver_Options_v780mV 2 4704 #define tx_x4_credit_gen0_IDriver_Options_v830mV 3 4705 #define tx_x4_credit_gen0_IDriver_Options_v880mV 4 4706 #define tx_x4_credit_gen0_IDriver_Options_v930mV 5 4707 #define tx_x4_credit_gen0_IDriver_Options_v980mV 6 4708 #define tx_x4_credit_gen0_IDriver_Options_v1010mV 7 4709 #define tx_x4_credit_gen0_IDriver_Options_v1040mV 8 4710 #define tx_x4_credit_gen0_IDriver_Options_v1060mV 9 4711 #define tx_x4_credit_gen0_IDriver_Options_v1070mV 10 4712 #define tx_x4_credit_gen0_IDriver_Options_v1080mV 11 4713 #define tx_x4_credit_gen0_IDriver_Options_v1085mV 12 4714 #define tx_x4_credit_gen0_IDriver_Options_v1090mV 13 4715 #define tx_x4_credit_gen0_IDriver_Options_v1095mV 14 4716 #define tx_x4_credit_gen0_IDriver_Options_v1100mV 15 4717 4718 /**************************************************************************** 4719 * Enums: tx_x4_credit_gen0_operationModes 4720 */ 4721 #define tx_x4_credit_gen0_operationModes_XGXS 0 4722 #define tx_x4_credit_gen0_operationModes_XGXG_nCC 1 4723 #define tx_x4_credit_gen0_operationModes_Indlane_OS8 4 4724 #define tx_x4_credit_gen0_operationModes_IndLane_OS5 5 4725 #define tx_x4_credit_gen0_operationModes_PCI 7 4726 #define tx_x4_credit_gen0_operationModes_XGXS_nLQ 8 4727 #define tx_x4_credit_gen0_operationModes_XGXS_nLQnCC 9 4728 #define tx_x4_credit_gen0_operationModes_PBypass 10 4729 #define tx_x4_credit_gen0_operationModes_PBypass_nDSK 11 4730 #define tx_x4_credit_gen0_operationModes_ComboCoreMode 12 4731 #define tx_x4_credit_gen0_operationModes_Clocks_off 15 4732 4733 /**************************************************************************** 4734 * Enums: tx_x4_credit_gen0_synce_enum 4735 */ 4736 #define tx_x4_credit_gen0_synce_enum_SYNCE_NO_DIV 0 4737 #define tx_x4_credit_gen0_synce_enum_SYNCE_DIV_7 1 4738 #define tx_x4_credit_gen0_synce_enum_SYNCE_DIV_11 2 4739 4740 /**************************************************************************** 4741 * Enums: tx_x4_credit_gen0_operationSpeeds 4742 */ 4743 #define tx_x4_credit_gen0_operationSpeeds_SPEED_2p5G_X1_10p3125 56 4744 #define tx_x4_credit_gen0_operationSpeeds_SPEED_1000M_10p3125 55 4745 #define tx_x4_credit_gen0_operationSpeeds_SPEED_100M_10p3125 54 4746 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10M_10p3125 53 4747 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10p5G_X4 50 4748 #define tx_x4_credit_gen0_operationSpeeds_SPEED_5G_KR1 49 4749 #define tx_x4_credit_gen0_operationSpeeds_SPEED_127G_X12 39 4750 #define tx_x4_credit_gen0_operationSpeeds_SPEED_120G_X12 38 4751 #define tx_x4_credit_gen0_operationSpeeds_SPEED_107G_X10 37 4752 #define tx_x4_credit_gen0_operationSpeeds_SPEED_100G_CR10 36 4753 #define tx_x4_credit_gen0_operationSpeeds_SPEED_42G_X4 35 4754 #define tx_x4_credit_gen0_operationSpeeds_SPEED_40G_CR4 34 4755 #define tx_x4_credit_gen0_operationSpeeds_SPEED_40G_KR4 33 4756 #define tx_x4_credit_gen0_operationSpeeds_SPEED_21G_X2 32 4757 #define tx_x4_credit_gen0_operationSpeeds_SPEED_20G_CR2 31 4758 #define tx_x4_credit_gen0_operationSpeeds_SPEED_20G_KR2 30 4759 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10p6_X1 29 4760 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10G_KR1 28 4761 #define tx_x4_credit_gen0_operationSpeeds_SPEED_40G_X4 27 4762 #define tx_x4_credit_gen0_operationSpeeds_SPEED_20G_X2 26 4763 #define tx_x4_credit_gen0_operationSpeeds_SPEED_20G_CX2 25 4764 #define tx_x4_credit_gen0_operationSpeeds_SPEED_31p5G_KR4 24 4765 #define tx_x4_credit_gen0_operationSpeeds_SPEED_31p5G_X4 23 4766 #define tx_x4_credit_gen0_operationSpeeds_SPEED_15p75G_X2 22 4767 #define tx_x4_credit_gen0_operationSpeeds_SPEED_25p45G_X4 21 4768 #define tx_x4_credit_gen0_operationSpeeds_SPEED_12p7G_X2 20 4769 #define tx_x4_credit_gen0_operationSpeeds_SPEED_21G_X4 19 4770 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10p5G_X2 18 4771 #define tx_x4_credit_gen0_operationSpeeds_SPEED_20G_X4 17 4772 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10G_X2 16 4773 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10G_CX2 15 4774 #define tx_x4_credit_gen0_operationSpeeds_SPEED_20G_CX4 14 4775 #define tx_x4_credit_gen0_operationSpeeds_SPEED_16G_X4 13 4776 #define tx_x4_credit_gen0_operationSpeeds_SPEED_15G_X4 12 4777 #define tx_x4_credit_gen0_operationSpeeds_SPEED_13G_X4 11 4778 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10G_X4 10 4779 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10G_KX4 9 4780 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10G_CX4 8 4781 #define tx_x4_credit_gen0_operationSpeeds_SPEED_5G_X1 7 4782 #define tx_x4_credit_gen0_operationSpeeds_SPEED_2p5G_X1 6 4783 #define tx_x4_credit_gen0_operationSpeeds_SPEED_1G_KX1 5 4784 #define tx_x4_credit_gen0_operationSpeeds_SPEED_1G_CX1 4 4785 #define tx_x4_credit_gen0_operationSpeeds_SPEED_1000M 3 4786 #define tx_x4_credit_gen0_operationSpeeds_SPEED_100M 2 4787 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10M 1 4788 4789 /**************************************************************************** 4790 * Enums: tx_x4_credit_gen0_actualSpeeds 4791 */ 4792 #define tx_x4_credit_gen0_actualSpeeds_dr_10M 0 4793 #define tx_x4_credit_gen0_actualSpeeds_dr_100M 1 4794 #define tx_x4_credit_gen0_actualSpeeds_dr_1G 2 4795 #define tx_x4_credit_gen0_actualSpeeds_dr_2p5G 3 4796 #define tx_x4_credit_gen0_actualSpeeds_dr_5G_X4 4 4797 #define tx_x4_credit_gen0_actualSpeeds_dr_6G_X4 5 4798 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_HiG 6 4799 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_CX4 7 4800 #define tx_x4_credit_gen0_actualSpeeds_dr_12G_HiG 8 4801 #define tx_x4_credit_gen0_actualSpeeds_dr_12p5G_X4 9 4802 #define tx_x4_credit_gen0_actualSpeeds_dr_13G_X4 10 4803 #define tx_x4_credit_gen0_actualSpeeds_dr_15G_X4 11 4804 #define tx_x4_credit_gen0_actualSpeeds_dr_16G_X4 12 4805 #define tx_x4_credit_gen0_actualSpeeds_dr_1G_KX 13 4806 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_KX4 14 4807 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_KR 15 4808 #define tx_x4_credit_gen0_actualSpeeds_dr_5G 16 4809 #define tx_x4_credit_gen0_actualSpeeds_dr_6p4G 17 4810 #define tx_x4_credit_gen0_actualSpeeds_dr_20G_X4 18 4811 #define tx_x4_credit_gen0_actualSpeeds_dr_21G_X4 19 4812 #define tx_x4_credit_gen0_actualSpeeds_dr_25G_X4 20 4813 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_HiG_DXGXS 21 4814 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_DXGXS 22 4815 #define tx_x4_credit_gen0_actualSpeeds_dr_10p5G_HiG_DXGXS 23 4816 #define tx_x4_credit_gen0_actualSpeeds_dr_10p5G_DXGXS 24 4817 #define tx_x4_credit_gen0_actualSpeeds_dr_12p773G_HiG_DXGXS 25 4818 #define tx_x4_credit_gen0_actualSpeeds_dr_12p773G_DXGXS 26 4819 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_XFI 27 4820 #define tx_x4_credit_gen0_actualSpeeds_dr_40G 28 4821 #define tx_x4_credit_gen0_actualSpeeds_dr_20G_HiG_DXGXS 29 4822 #define tx_x4_credit_gen0_actualSpeeds_dr_20G_DXGXS 30 4823 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_SFI 31 4824 #define tx_x4_credit_gen0_actualSpeeds_dr_31p5G 32 4825 #define tx_x4_credit_gen0_actualSpeeds_dr_32p7G 33 4826 #define tx_x4_credit_gen0_actualSpeeds_dr_20G_SCR 34 4827 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 4828 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_DXGXS_SCR 36 4829 #define tx_x4_credit_gen0_actualSpeeds_dr_12G_R2 37 4830 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_X2 38 4831 #define tx_x4_credit_gen0_actualSpeeds_dr_40G_KR4 39 4832 #define tx_x4_credit_gen0_actualSpeeds_dr_40G_CR4 40 4833 #define tx_x4_credit_gen0_actualSpeeds_dr_100G_CR10 41 4834 #define tx_x4_credit_gen0_actualSpeeds_dr_15p75G_DXGXS 44 4835 #define tx_x4_credit_gen0_actualSpeeds_dr_20G_KR2 57 4836 #define tx_x4_credit_gen0_actualSpeeds_dr_20G_CR2 58 4837 4838 /**************************************************************************** 4839 * Enums: tx_x4_credit_gen0_actualSpeedsMisc1 4840 */ 4841 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_2500BRCM_X1 16 4842 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_5000BRCM_X4 17 4843 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_6000BRCM_X4 18 4844 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_10GHiGig_X4 19 4845 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_10GBASE_CX4 20 4846 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_12GHiGig_X4 21 4847 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 4848 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_13GHiGig_X4 23 4849 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_15GHiGig_X4 24 4850 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_16GHiGig_X4 25 4851 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_5000BRCM_X1 26 4852 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_6363BRCM_X1 27 4853 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_20GHiGig_X4 28 4854 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_21GHiGig_X4 29 4855 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 4856 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 4857 4858 /**************************************************************************** 4859 * Enums: tx_x4_credit_gen0_IndLaneModes 4860 */ 4861 #define tx_x4_credit_gen0_IndLaneModes_SWSDR_div2 0 4862 #define tx_x4_credit_gen0_IndLaneModes_SWSDR_div1 1 4863 #define tx_x4_credit_gen0_IndLaneModes_DWSDR_div2 2 4864 #define tx_x4_credit_gen0_IndLaneModes_DWSDR_div1 3 4865 4866 /**************************************************************************** 4867 * Enums: tx_x4_credit_gen0_prbsSelect 4868 */ 4869 #define tx_x4_credit_gen0_prbsSelect_prbs7 0 4870 #define tx_x4_credit_gen0_prbsSelect_prbs15 1 4871 #define tx_x4_credit_gen0_prbsSelect_prbs23 2 4872 #define tx_x4_credit_gen0_prbsSelect_prbs31 3 4873 4874 /**************************************************************************** 4875 * Enums: tx_x4_credit_gen0_vcoDivider 4876 */ 4877 #define tx_x4_credit_gen0_vcoDivider_div32 0 4878 #define tx_x4_credit_gen0_vcoDivider_div36 1 4879 #define tx_x4_credit_gen0_vcoDivider_div40 2 4880 #define tx_x4_credit_gen0_vcoDivider_div42 3 4881 #define tx_x4_credit_gen0_vcoDivider_div48 4 4882 #define tx_x4_credit_gen0_vcoDivider_div50 5 4883 #define tx_x4_credit_gen0_vcoDivider_div52 6 4884 #define tx_x4_credit_gen0_vcoDivider_div54 7 4885 #define tx_x4_credit_gen0_vcoDivider_div60 8 4886 #define tx_x4_credit_gen0_vcoDivider_div64 9 4887 #define tx_x4_credit_gen0_vcoDivider_div66 10 4888 #define tx_x4_credit_gen0_vcoDivider_div68 11 4889 #define tx_x4_credit_gen0_vcoDivider_div70 12 4890 #define tx_x4_credit_gen0_vcoDivider_div80 13 4891 #define tx_x4_credit_gen0_vcoDivider_div92 14 4892 #define tx_x4_credit_gen0_vcoDivider_div100 15 4893 4894 /**************************************************************************** 4895 * Enums: tx_x4_credit_gen0_refClkSelect 4896 */ 4897 #define tx_x4_credit_gen0_refClkSelect_clk_25MHz 0 4898 #define tx_x4_credit_gen0_refClkSelect_clk_100MHz 1 4899 #define tx_x4_credit_gen0_refClkSelect_clk_125MHz 2 4900 #define tx_x4_credit_gen0_refClkSelect_clk_156p25MHz 3 4901 #define tx_x4_credit_gen0_refClkSelect_clk_187p5MHz 4 4902 #define tx_x4_credit_gen0_refClkSelect_clk_161p25Mhz 5 4903 #define tx_x4_credit_gen0_refClkSelect_clk_50Mhz 6 4904 #define tx_x4_credit_gen0_refClkSelect_clk_106p25Mhz 7 4905 4906 /**************************************************************************** 4907 * Enums: tx_x4_credit_gen0_aerMMDdevTypeSelect 4908 */ 4909 #define tx_x4_credit_gen0_aerMMDdevTypeSelect_combo_core 0 4910 #define tx_x4_credit_gen0_aerMMDdevTypeSelect_PMA_PMD 1 4911 #define tx_x4_credit_gen0_aerMMDdevTypeSelect_PCS 3 4912 #define tx_x4_credit_gen0_aerMMDdevTypeSelect_PHY 4 4913 #define tx_x4_credit_gen0_aerMMDdevTypeSelect_DTE 5 4914 #define tx_x4_credit_gen0_aerMMDdevTypeSelect_CL73_AN 7 4915 4916 /**************************************************************************** 4917 * Enums: tx_x4_credit_gen0_aerMMDportSelect 4918 */ 4919 #define tx_x4_credit_gen0_aerMMDportSelect_ln0 0 4920 #define tx_x4_credit_gen0_aerMMDportSelect_ln1 1 4921 #define tx_x4_credit_gen0_aerMMDportSelect_ln2 2 4922 #define tx_x4_credit_gen0_aerMMDportSelect_ln3 3 4923 #define tx_x4_credit_gen0_aerMMDportSelect_BCST_ln0_1_2_3 511 4924 #define tx_x4_credit_gen0_aerMMDportSelect_BCST_ln0_1 512 4925 #define tx_x4_credit_gen0_aerMMDportSelect_BCST_ln2_3 513 4926 4927 /**************************************************************************** 4928 * Enums: tx_x4_credit_gen0_firmwareModeSelect 4929 */ 4930 #define tx_x4_credit_gen0_firmwareModeSelect_DEFAULT 0 4931 #define tx_x4_credit_gen0_firmwareModeSelect_SFP_OPT_LR 1 4932 #define tx_x4_credit_gen0_firmwareModeSelect_SFP_DAC 2 4933 #define tx_x4_credit_gen0_firmwareModeSelect_XLAUI 3 4934 #define tx_x4_credit_gen0_firmwareModeSelect_LONG_CH_6G 4 4935 4936 /**************************************************************************** 4937 * Enums: tx_x4_credit_gen0_tempIdxSelect 4938 */ 4939 #define tx_x4_credit_gen0_tempIdxSelect_LTE__22p9C 15 4940 #define tx_x4_credit_gen0_tempIdxSelect_LTE__12p6C 14 4941 #define tx_x4_credit_gen0_tempIdxSelect_LTE__3p0C 13 4942 #define tx_x4_credit_gen0_tempIdxSelect_LTE_6p7C 12 4943 #define tx_x4_credit_gen0_tempIdxSelect_LTE_16p4C 11 4944 #define tx_x4_credit_gen0_tempIdxSelect_LTE_26p6C 10 4945 #define tx_x4_credit_gen0_tempIdxSelect_LTE_36p3C 9 4946 #define tx_x4_credit_gen0_tempIdxSelect_LTE_46p0C 8 4947 #define tx_x4_credit_gen0_tempIdxSelect_LTE_56p2C 7 4948 #define tx_x4_credit_gen0_tempIdxSelect_LTE_65p9C 6 4949 #define tx_x4_credit_gen0_tempIdxSelect_LTE_75p6C 5 4950 #define tx_x4_credit_gen0_tempIdxSelect_LTE_85p3C 4 4951 #define tx_x4_credit_gen0_tempIdxSelect_LTE_95p5C 3 4952 #define tx_x4_credit_gen0_tempIdxSelect_LTE_105p2C 2 4953 #define tx_x4_credit_gen0_tempIdxSelect_LTE_114p9C 1 4954 #define tx_x4_credit_gen0_tempIdxSelect_LTE_125p1C 0 4955 4956 /**************************************************************************** 4957 * TSCE_IEEE_CL22_CL22_B0 4958 */ 4959 /**************************************************************************** 4960 * CL22_B0 :: phyid2 4961 */ 4962 /* CL22_B0 :: phyid2 :: regid1 [15:00] */ 4963 #define CL22_B0_PHYID2_REGID1_MASK 0xffff 4964 #define CL22_B0_PHYID2_REGID1_ALIGN 0 4965 #define CL22_B0_PHYID2_REGID1_BITS 16 4966 #define CL22_B0_PHYID2_REGID1_SHIFT 0 4967 4968 4969 /**************************************************************************** 4970 * CL22_B0 :: phyid3 4971 */ 4972 /* CL22_B0 :: phyid3 :: regid2 [15:00] */ 4973 #define CL22_B0_PHYID3_REGID2_MASK 0xffff 4974 #define CL22_B0_PHYID3_REGID2_ALIGN 0 4975 #define CL22_B0_PHYID3_REGID2_BITS 16 4976 #define CL22_B0_PHYID3_REGID2_SHIFT 0 4977 4978 4979 /**************************************************************************** 4980 * TSCE_TSCE_USER1_Main0 4981 */ 4982 /**************************************************************************** 4983 * Main0 :: setup 4984 */ 4985 /* Main0 :: setup :: refclk_sel [15:13] */ 4986 #define MAIN0_SETUP_REFCLK_SEL_MASK 0xe000 4987 #define MAIN0_SETUP_REFCLK_SEL_ALIGN 0 4988 #define MAIN0_SETUP_REFCLK_SEL_BITS 3 4989 #define MAIN0_SETUP_REFCLK_SEL_SHIFT 13 4990 #define MAIN0_SETUP_REFCLK_SEL_clk_25MHz 0 4991 #define MAIN0_SETUP_REFCLK_SEL_clk_100MHz 1 4992 #define MAIN0_SETUP_REFCLK_SEL_clk_125MHz 2 4993 #define MAIN0_SETUP_REFCLK_SEL_clk_156p25MHz 3 4994 #define MAIN0_SETUP_REFCLK_SEL_clk_187p5MHz 4 4995 #define MAIN0_SETUP_REFCLK_SEL_clk_161p25Mhz 5 4996 #define MAIN0_SETUP_REFCLK_SEL_clk_50Mhz 6 4997 #define MAIN0_SETUP_REFCLK_SEL_clk_106p25Mhz 7 4998 4999 /* Main0 :: setup :: cl37_high_vco [12:12] */ 5000 #define MAIN0_SETUP_CL37_HIGH_VCO_MASK 0x1000 5001 #define MAIN0_SETUP_CL37_HIGH_VCO_ALIGN 0 5002 #define MAIN0_SETUP_CL37_HIGH_VCO_BITS 1 5003 #define MAIN0_SETUP_CL37_HIGH_VCO_SHIFT 12 5004 5005 /* Main0 :: setup :: cl73_low_vco [11:11] */ 5006 #define MAIN0_SETUP_CL73_LOW_VCO_MASK 0x0800 5007 #define MAIN0_SETUP_CL73_LOW_VCO_ALIGN 0 5008 #define MAIN0_SETUP_CL73_LOW_VCO_BITS 1 5009 #define MAIN0_SETUP_CL73_LOW_VCO_SHIFT 11 5010 5011 /* Main0 :: setup :: pll_reset_en [10:10] */ 5012 #define MAIN0_SETUP_PLL_RESET_EN_MASK 0x0400 5013 #define MAIN0_SETUP_PLL_RESET_EN_ALIGN 0 5014 #define MAIN0_SETUP_PLL_RESET_EN_BITS 1 5015 #define MAIN0_SETUP_PLL_RESET_EN_SHIFT 10 5016 5017 /* Main0 :: setup :: master_port_num [09:08] */ 5018 #define MAIN0_SETUP_MASTER_PORT_NUM_MASK 0x0300 5019 #define MAIN0_SETUP_MASTER_PORT_NUM_ALIGN 0 5020 #define MAIN0_SETUP_MASTER_PORT_NUM_BITS 2 5021 #define MAIN0_SETUP_MASTER_PORT_NUM_SHIFT 8 5022 5023 /* Main0 :: setup :: reserved0 [07:07] */ 5024 #define MAIN0_SETUP_RESERVED0_MASK 0x0080 5025 #define MAIN0_SETUP_RESERVED0_ALIGN 0 5026 #define MAIN0_SETUP_RESERVED0_BITS 1 5027 #define MAIN0_SETUP_RESERVED0_SHIFT 7 5028 5029 /* Main0 :: setup :: port_mode_sel [06:04] */ 5030 #define MAIN0_SETUP_PORT_MODE_SEL_MASK 0x0070 5031 #define MAIN0_SETUP_PORT_MODE_SEL_ALIGN 0 5032 #define MAIN0_SETUP_PORT_MODE_SEL_BITS 3 5033 #define MAIN0_SETUP_PORT_MODE_SEL_SHIFT 4 5034 5035 /* Main0 :: setup :: single_port_mode [03:03] */ 5036 #define MAIN0_SETUP_SINGLE_PORT_MODE_MASK 0x0008 5037 #define MAIN0_SETUP_SINGLE_PORT_MODE_ALIGN 0 5038 #define MAIN0_SETUP_SINGLE_PORT_MODE_BITS 1 5039 #define MAIN0_SETUP_SINGLE_PORT_MODE_SHIFT 3 5040 5041 /* Main0 :: setup :: stand_alone_mode [02:02] */ 5042 #define MAIN0_SETUP_STAND_ALONE_MODE_MASK 0x0004 5043 #define MAIN0_SETUP_STAND_ALONE_MODE_ALIGN 0 5044 #define MAIN0_SETUP_STAND_ALONE_MODE_BITS 1 5045 #define MAIN0_SETUP_STAND_ALONE_MODE_SHIFT 2 5046 5047 /* Main0 :: setup :: reserved1 [01:00] */ 5048 #define MAIN0_SETUP_RESERVED1_MASK 0x0003 5049 #define MAIN0_SETUP_RESERVED1_ALIGN 0 5050 #define MAIN0_SETUP_RESERVED1_BITS 2 5051 #define MAIN0_SETUP_RESERVED1_SHIFT 0 5052 5053 5054 /**************************************************************************** 5055 * Main0 :: synce_control 5056 */ 5057 /* Main0 :: synce_control :: reserved0 [15:08] */ 5058 #define MAIN0_SYNCE_CONTROL_RESERVED0_MASK 0xff00 5059 #define MAIN0_SYNCE_CONTROL_RESERVED0_ALIGN 0 5060 #define MAIN0_SYNCE_CONTROL_RESERVED0_BITS 8 5061 #define MAIN0_SYNCE_CONTROL_RESERVED0_SHIFT 8 5062 5063 /* Main0 :: synce_control :: synce_mode_phy_ln3 [07:06] */ 5064 #define MAIN0_SYNCE_CONTROL_SYNCE_MODE_PHY_LN3_MASK 0x00c0 5065 #define MAIN0_SYNCE_CONTROL_SYNCE_MODE_PHY_LN3_ALIGN 0 5066 #define MAIN0_SYNCE_CONTROL_SYNCE_MODE_PHY_LN3_BITS 2 5067 #define MAIN0_SYNCE_CONTROL_SYNCE_MODE_PHY_LN3_SHIFT 6 5068 #define MAIN0_SYNCE_CONTROL_SYNCE_MODE_PHY_LN3_SYNCE_NO_DIV 0 5069 #define MAIN0_SYNCE_CONTROL_SYNCE_MODE_PHY_LN3_SYNCE_DIV_7 1 5070 #define MAIN0_SYNCE_CONTROL_SYNCE_MODE_PHY_LN3_SYNCE_DIV_11 2 5071 5072 /* Main0 :: synce_control :: synce_mode_phy_ln2 [05:04] */ 5073 #define MAIN0_SYNCE_CONTROL_SYNCE_MODE_PHY_LN2_MASK 0x0030 5074 #define MAIN0_SYNCE_CONTROL_SYNCE_MODE_PHY_LN2_ALIGN 0 5075 #define MAIN0_SYNCE_CONTROL_SYNCE_MODE_PHY_LN2_BITS 2 5076 #define MAIN0_SYNCE_CONTROL_SYNCE_MODE_PHY_LN2_SHIFT 4 5077 #define MAIN0_SYNCE_CONTROL_SYNCE_MODE_PHY_LN2_SYNCE_NO_DIV 0 5078 #define MAIN0_SYNCE_CONTROL_SYNCE_MODE_PHY_LN2_SYNCE_DIV_7 1 5079 #define MAIN0_SYNCE_CONTROL_SYNCE_MODE_PHY_LN2_SYNCE_DIV_11 2 5080 5081 /* Main0 :: synce_control :: synce_mode_phy_ln1 [03:02] */ 5082 #define MAIN0_SYNCE_CONTROL_SYNCE_MODE_PHY_LN1_MASK 0x000c 5083 #define MAIN0_SYNCE_CONTROL_SYNCE_MODE_PHY_LN1_ALIGN 0 5084 #define MAIN0_SYNCE_CONTROL_SYNCE_MODE_PHY_LN1_BITS 2 5085 #define MAIN0_SYNCE_CONTROL_SYNCE_MODE_PHY_LN1_SHIFT 2 5086 #define MAIN0_SYNCE_CONTROL_SYNCE_MODE_PHY_LN1_SYNCE_NO_DIV 0 5087 #define MAIN0_SYNCE_CONTROL_SYNCE_MODE_PHY_LN1_SYNCE_DIV_7 1 5088 #define MAIN0_SYNCE_CONTROL_SYNCE_MODE_PHY_LN1_SYNCE_DIV_11 2 5089 5090 /* Main0 :: synce_control :: synce_mode_phy_ln0 [01:00] */ 5091 #define MAIN0_SYNCE_CONTROL_SYNCE_MODE_PHY_LN0_MASK 0x0003 5092 #define MAIN0_SYNCE_CONTROL_SYNCE_MODE_PHY_LN0_ALIGN 0 5093 #define MAIN0_SYNCE_CONTROL_SYNCE_MODE_PHY_LN0_BITS 2 5094 #define MAIN0_SYNCE_CONTROL_SYNCE_MODE_PHY_LN0_SHIFT 0 5095 #define MAIN0_SYNCE_CONTROL_SYNCE_MODE_PHY_LN0_SYNCE_NO_DIV 0 5096 #define MAIN0_SYNCE_CONTROL_SYNCE_MODE_PHY_LN0_SYNCE_DIV_7 1 5097 #define MAIN0_SYNCE_CONTROL_SYNCE_MODE_PHY_LN0_SYNCE_DIV_11 2 5098 5099 5100 /**************************************************************************** 5101 * Main0 :: lane_swap 5102 */ 5103 /* Main0 :: lane_swap :: reserved0 [15:08] */ 5104 #define MAIN0_LANE_SWAP_RESERVED0_MASK 0xff00 5105 #define MAIN0_LANE_SWAP_RESERVED0_ALIGN 0 5106 #define MAIN0_LANE_SWAP_RESERVED0_BITS 8 5107 #define MAIN0_LANE_SWAP_RESERVED0_SHIFT 8 5108 5109 /* Main0 :: lane_swap :: log3_to_phy_lnswap_sel [07:06] */ 5110 #define MAIN0_LANE_SWAP_LOG3_TO_PHY_LNSWAP_SEL_MASK 0x00c0 5111 #define MAIN0_LANE_SWAP_LOG3_TO_PHY_LNSWAP_SEL_ALIGN 0 5112 #define MAIN0_LANE_SWAP_LOG3_TO_PHY_LNSWAP_SEL_BITS 2 5113 #define MAIN0_LANE_SWAP_LOG3_TO_PHY_LNSWAP_SEL_SHIFT 6 5114 5115 /* Main0 :: lane_swap :: log2_to_phy_lnswap_sel [05:04] */ 5116 #define MAIN0_LANE_SWAP_LOG2_TO_PHY_LNSWAP_SEL_MASK 0x0030 5117 #define MAIN0_LANE_SWAP_LOG2_TO_PHY_LNSWAP_SEL_ALIGN 0 5118 #define MAIN0_LANE_SWAP_LOG2_TO_PHY_LNSWAP_SEL_BITS 2 5119 #define MAIN0_LANE_SWAP_LOG2_TO_PHY_LNSWAP_SEL_SHIFT 4 5120 5121 /* Main0 :: lane_swap :: log1_to_phy_lnswap_sel [03:02] */ 5122 #define MAIN0_LANE_SWAP_LOG1_TO_PHY_LNSWAP_SEL_MASK 0x000c 5123 #define MAIN0_LANE_SWAP_LOG1_TO_PHY_LNSWAP_SEL_ALIGN 0 5124 #define MAIN0_LANE_SWAP_LOG1_TO_PHY_LNSWAP_SEL_BITS 2 5125 #define MAIN0_LANE_SWAP_LOG1_TO_PHY_LNSWAP_SEL_SHIFT 2 5126 5127 /* Main0 :: lane_swap :: log0_to_phy_lnswap_sel [01:00] */ 5128 #define MAIN0_LANE_SWAP_LOG0_TO_PHY_LNSWAP_SEL_MASK 0x0003 5129 #define MAIN0_LANE_SWAP_LOG0_TO_PHY_LNSWAP_SEL_ALIGN 0 5130 #define MAIN0_LANE_SWAP_LOG0_TO_PHY_LNSWAP_SEL_BITS 2 5131 #define MAIN0_LANE_SWAP_LOG0_TO_PHY_LNSWAP_SEL_SHIFT 0 5132 5133 5134 /**************************************************************************** 5135 * Main0 :: deviceInPkg5 5136 */ 5137 /* Main0 :: deviceInPkg5 :: reserved0 [15:08] */ 5138 #define MAIN0_DEVICEINPKG5_RESERVED0_MASK 0xff00 5139 #define MAIN0_DEVICEINPKG5_RESERVED0_ALIGN 0 5140 #define MAIN0_DEVICEINPKG5_RESERVED0_BITS 8 5141 #define MAIN0_DEVICEINPKG5_RESERVED0_SHIFT 8 5142 5143 /* Main0 :: deviceInPkg5 :: AN [07:07] */ 5144 #define MAIN0_DEVICEINPKG5_AN_MASK 0x0080 5145 #define MAIN0_DEVICEINPKG5_AN_ALIGN 0 5146 #define MAIN0_DEVICEINPKG5_AN_BITS 1 5147 #define MAIN0_DEVICEINPKG5_AN_SHIFT 7 5148 5149 /* Main0 :: deviceInPkg5 :: TC [06:06] */ 5150 #define MAIN0_DEVICEINPKG5_TC_MASK 0x0040 5151 #define MAIN0_DEVICEINPKG5_TC_ALIGN 0 5152 #define MAIN0_DEVICEINPKG5_TC_BITS 1 5153 #define MAIN0_DEVICEINPKG5_TC_SHIFT 6 5154 5155 /* Main0 :: deviceInPkg5 :: DTE_XS [05:05] */ 5156 #define MAIN0_DEVICEINPKG5_DTE_XS_MASK 0x0020 5157 #define MAIN0_DEVICEINPKG5_DTE_XS_ALIGN 0 5158 #define MAIN0_DEVICEINPKG5_DTE_XS_BITS 1 5159 #define MAIN0_DEVICEINPKG5_DTE_XS_SHIFT 5 5160 5161 /* Main0 :: deviceInPkg5 :: PHY_XS [04:04] */ 5162 #define MAIN0_DEVICEINPKG5_PHY_XS_MASK 0x0010 5163 #define MAIN0_DEVICEINPKG5_PHY_XS_ALIGN 0 5164 #define MAIN0_DEVICEINPKG5_PHY_XS_BITS 1 5165 #define MAIN0_DEVICEINPKG5_PHY_XS_SHIFT 4 5166 5167 /* Main0 :: deviceInPkg5 :: PCS_XS [03:03] */ 5168 #define MAIN0_DEVICEINPKG5_PCS_XS_MASK 0x0008 5169 #define MAIN0_DEVICEINPKG5_PCS_XS_ALIGN 0 5170 #define MAIN0_DEVICEINPKG5_PCS_XS_BITS 1 5171 #define MAIN0_DEVICEINPKG5_PCS_XS_SHIFT 3 5172 5173 /* Main0 :: deviceInPkg5 :: WIS [02:02] */ 5174 #define MAIN0_DEVICEINPKG5_WIS_MASK 0x0004 5175 #define MAIN0_DEVICEINPKG5_WIS_ALIGN 0 5176 #define MAIN0_DEVICEINPKG5_WIS_BITS 1 5177 #define MAIN0_DEVICEINPKG5_WIS_SHIFT 2 5178 5179 /* Main0 :: deviceInPkg5 :: PMA_PMD [01:01] */ 5180 #define MAIN0_DEVICEINPKG5_PMA_PMD_MASK 0x0002 5181 #define MAIN0_DEVICEINPKG5_PMA_PMD_ALIGN 0 5182 #define MAIN0_DEVICEINPKG5_PMA_PMD_BITS 1 5183 #define MAIN0_DEVICEINPKG5_PMA_PMD_SHIFT 1 5184 5185 /* Main0 :: deviceInPkg5 :: Clause22 [00:00] */ 5186 #define MAIN0_DEVICEINPKG5_CLAUSE22_MASK 0x0001 5187 #define MAIN0_DEVICEINPKG5_CLAUSE22_ALIGN 0 5188 #define MAIN0_DEVICEINPKG5_CLAUSE22_BITS 1 5189 #define MAIN0_DEVICEINPKG5_CLAUSE22_SHIFT 0 5190 5191 5192 /**************************************************************************** 5193 * Main0 :: misc 5194 */ 5195 /* Main0 :: misc :: reserved0 [15:12] */ 5196 #define MAIN0_MISC_RESERVED0_MASK 0xf000 5197 #define MAIN0_MISC_RESERVED0_ALIGN 0 5198 #define MAIN0_MISC_RESERVED0_BITS 4 5199 #define MAIN0_MISC_RESERVED0_SHIFT 12 5200 5201 /* Main0 :: misc :: cl49_low_latency_en [11:11] */ 5202 #define MAIN0_MISC_CL49_LOW_LATENCY_EN_MASK 0x0800 5203 #define MAIN0_MISC_CL49_LOW_LATENCY_EN_ALIGN 0 5204 #define MAIN0_MISC_CL49_LOW_LATENCY_EN_BITS 1 5205 #define MAIN0_MISC_CL49_LOW_LATENCY_EN_SHIFT 11 5206 5207 /* Main0 :: misc :: cl82_multi_pipe_mode [10:09] */ 5208 #define MAIN0_MISC_CL82_MULTI_PIPE_MODE_MASK 0x0600 5209 #define MAIN0_MISC_CL82_MULTI_PIPE_MODE_ALIGN 0 5210 #define MAIN0_MISC_CL82_MULTI_PIPE_MODE_BITS 2 5211 #define MAIN0_MISC_CL82_MULTI_PIPE_MODE_SHIFT 9 5212 5213 /* Main0 :: misc :: cl82_mld_phys_map [08:07] */ 5214 #define MAIN0_MISC_CL82_MLD_PHYS_MAP_MASK 0x0180 5215 #define MAIN0_MISC_CL82_MLD_PHYS_MAP_ALIGN 0 5216 #define MAIN0_MISC_CL82_MLD_PHYS_MAP_BITS 2 5217 #define MAIN0_MISC_CL82_MLD_PHYS_MAP_SHIFT 7 5218 5219 /* Main0 :: misc :: reserved1 [06:00] */ 5220 #define MAIN0_MISC_RESERVED1_MASK 0x007f 5221 #define MAIN0_MISC_RESERVED1_ALIGN 0 5222 #define MAIN0_MISC_RESERVED1_BITS 7 5223 #define MAIN0_MISC_RESERVED1_SHIFT 0 5224 5225 5226 /**************************************************************************** 5227 * Main0 :: tick_control_1 5228 */ 5229 /* Main0 :: tick_control_1 :: tick_override [15:15] */ 5230 #define MAIN0_TICK_CONTROL_1_TICK_OVERRIDE_MASK 0x8000 5231 #define MAIN0_TICK_CONTROL_1_TICK_OVERRIDE_ALIGN 0 5232 #define MAIN0_TICK_CONTROL_1_TICK_OVERRIDE_BITS 1 5233 #define MAIN0_TICK_CONTROL_1_TICK_OVERRIDE_SHIFT 15 5234 5235 /* Main0 :: tick_control_1 :: tick_numerator_upper [14:00] */ 5236 #define MAIN0_TICK_CONTROL_1_TICK_NUMERATOR_UPPER_MASK 0x7fff 5237 #define MAIN0_TICK_CONTROL_1_TICK_NUMERATOR_UPPER_ALIGN 0 5238 #define MAIN0_TICK_CONTROL_1_TICK_NUMERATOR_UPPER_BITS 15 5239 #define MAIN0_TICK_CONTROL_1_TICK_NUMERATOR_UPPER_SHIFT 0 5240 5241 5242 /**************************************************************************** 5243 * Main0 :: tick_control_0 5244 */ 5245 /* Main0 :: tick_control_0 :: tick_numerator_lower [15:12] */ 5246 #define MAIN0_TICK_CONTROL_0_TICK_NUMERATOR_LOWER_MASK 0xf000 5247 #define MAIN0_TICK_CONTROL_0_TICK_NUMERATOR_LOWER_ALIGN 0 5248 #define MAIN0_TICK_CONTROL_0_TICK_NUMERATOR_LOWER_BITS 4 5249 #define MAIN0_TICK_CONTROL_0_TICK_NUMERATOR_LOWER_SHIFT 12 5250 5251 /* Main0 :: tick_control_0 :: tick_denominator [11:02] */ 5252 #define MAIN0_TICK_CONTROL_0_TICK_DENOMINATOR_MASK 0x0ffc 5253 #define MAIN0_TICK_CONTROL_0_TICK_DENOMINATOR_ALIGN 0 5254 #define MAIN0_TICK_CONTROL_0_TICK_DENOMINATOR_BITS 10 5255 #define MAIN0_TICK_CONTROL_0_TICK_DENOMINATOR_SHIFT 2 5256 5257 /* Main0 :: tick_control_0 :: reserved0 [01:00] */ 5258 #define MAIN0_TICK_CONTROL_0_RESERVED0_MASK 0x0003 5259 #define MAIN0_TICK_CONTROL_0_RESERVED0_ALIGN 0 5260 #define MAIN0_TICK_CONTROL_0_RESERVED0_BITS 2 5261 #define MAIN0_TICK_CONTROL_0_RESERVED0_SHIFT 0 5262 5263 5264 /**************************************************************************** 5265 * Main0 :: loopback_control 5266 */ 5267 /* Main0 :: loopback_control :: remote_pcs_loopback_enable [15:12] */ 5268 #define MAIN0_LOOPBACK_CONTROL_REMOTE_PCS_LOOPBACK_ENABLE_MASK 0xf000 5269 #define MAIN0_LOOPBACK_CONTROL_REMOTE_PCS_LOOPBACK_ENABLE_ALIGN 0 5270 #define MAIN0_LOOPBACK_CONTROL_REMOTE_PCS_LOOPBACK_ENABLE_BITS 4 5271 #define MAIN0_LOOPBACK_CONTROL_REMOTE_PCS_LOOPBACK_ENABLE_SHIFT 12 5272 5273 /* Main0 :: loopback_control :: remote_pmd_loopback_enable [11:08] */ 5274 #define MAIN0_LOOPBACK_CONTROL_REMOTE_PMD_LOOPBACK_ENABLE_MASK 0x0f00 5275 #define MAIN0_LOOPBACK_CONTROL_REMOTE_PMD_LOOPBACK_ENABLE_ALIGN 0 5276 #define MAIN0_LOOPBACK_CONTROL_REMOTE_PMD_LOOPBACK_ENABLE_BITS 4 5277 #define MAIN0_LOOPBACK_CONTROL_REMOTE_PMD_LOOPBACK_ENABLE_SHIFT 8 5278 5279 /* Main0 :: loopback_control :: local_pcs_loopback_enable [07:04] */ 5280 #define MAIN0_LOOPBACK_CONTROL_LOCAL_PCS_LOOPBACK_ENABLE_MASK 0x00f0 5281 #define MAIN0_LOOPBACK_CONTROL_LOCAL_PCS_LOOPBACK_ENABLE_ALIGN 0 5282 #define MAIN0_LOOPBACK_CONTROL_LOCAL_PCS_LOOPBACK_ENABLE_BITS 4 5283 #define MAIN0_LOOPBACK_CONTROL_LOCAL_PCS_LOOPBACK_ENABLE_SHIFT 4 5284 5285 /* Main0 :: loopback_control :: reserved0 [03:00] */ 5286 #define MAIN0_LOOPBACK_CONTROL_RESERVED0_MASK 0x000f 5287 #define MAIN0_LOOPBACK_CONTROL_RESERVED0_ALIGN 0 5288 #define MAIN0_LOOPBACK_CONTROL_RESERVED0_BITS 4 5289 #define MAIN0_LOOPBACK_CONTROL_RESERVED0_SHIFT 0 5290 5291 5292 /**************************************************************************** 5293 * Main0 :: mdio_broadcast 5294 */ 5295 /* Main0 :: mdio_broadcast :: prtad_bcst [15:11] */ 5296 #define MAIN0_MDIO_BROADCAST_PRTAD_BCST_MASK 0xf800 5297 #define MAIN0_MDIO_BROADCAST_PRTAD_BCST_ALIGN 0 5298 #define MAIN0_MDIO_BROADCAST_PRTAD_BCST_BITS 5 5299 #define MAIN0_MDIO_BROADCAST_PRTAD_BCST_SHIFT 11 5300 5301 /* Main0 :: mdio_broadcast :: multiPRTs_en [10:07] */ 5302 #define MAIN0_MDIO_BROADCAST_MULTIPRTS_EN_MASK 0x0780 5303 #define MAIN0_MDIO_BROADCAST_MULTIPRTS_EN_ALIGN 0 5304 #define MAIN0_MDIO_BROADCAST_MULTIPRTS_EN_BITS 4 5305 #define MAIN0_MDIO_BROADCAST_MULTIPRTS_EN_SHIFT 7 5306 5307 /* Main0 :: mdio_broadcast :: reserved0 [06:00] */ 5308 #define MAIN0_MDIO_BROADCAST_RESERVED0_MASK 0x007f 5309 #define MAIN0_MDIO_BROADCAST_RESERVED0_ALIGN 0 5310 #define MAIN0_MDIO_BROADCAST_RESERVED0_BITS 7 5311 #define MAIN0_MDIO_BROADCAST_RESERVED0_SHIFT 0 5312 5313 5314 /**************************************************************************** 5315 * Main0 :: serdesID 5316 */ 5317 /* Main0 :: serdesID :: rev_letter [15:14] */ 5318 #define MAIN0_SERDESID_REV_LETTER_MASK 0xc000 5319 #define MAIN0_SERDESID_REV_LETTER_ALIGN 0 5320 #define MAIN0_SERDESID_REV_LETTER_BITS 2 5321 #define MAIN0_SERDESID_REV_LETTER_SHIFT 14 5322 5323 /* Main0 :: serdesID :: rev_number [13:11] */ 5324 #define MAIN0_SERDESID_REV_NUMBER_MASK 0x3800 5325 #define MAIN0_SERDESID_REV_NUMBER_ALIGN 0 5326 #define MAIN0_SERDESID_REV_NUMBER_BITS 3 5327 #define MAIN0_SERDESID_REV_NUMBER_SHIFT 11 5328 5329 /* Main0 :: serdesID :: bonding [10:09] */ 5330 #define MAIN0_SERDESID_BONDING_MASK 0x0600 5331 #define MAIN0_SERDESID_BONDING_ALIGN 0 5332 #define MAIN0_SERDESID_BONDING_BITS 2 5333 #define MAIN0_SERDESID_BONDING_SHIFT 9 5334 5335 /* Main0 :: serdesID :: tech_proc [08:06] */ 5336 #define MAIN0_SERDESID_TECH_PROC_MASK 0x01c0 5337 #define MAIN0_SERDESID_TECH_PROC_ALIGN 0 5338 #define MAIN0_SERDESID_TECH_PROC_BITS 3 5339 #define MAIN0_SERDESID_TECH_PROC_SHIFT 6 5340 5341 /* Main0 :: serdesID :: model_number [05:00] */ 5342 #define MAIN0_SERDESID_MODEL_NUMBER_MASK 0x003f 5343 #define MAIN0_SERDESID_MODEL_NUMBER_ALIGN 0 5344 #define MAIN0_SERDESID_MODEL_NUMBER_BITS 6 5345 #define MAIN0_SERDESID_MODEL_NUMBER_SHIFT 0 5346 5347 5348 /**************************************************************************** 5349 * TSCE_TSCE_USER1_pmd_x1 5350 */ 5351 /**************************************************************************** 5352 * pmd_x1 :: control 5353 */ 5354 /* pmd_x1 :: control :: reserved0 [15:09] */ 5355 #define PMD_X1_CONTROL_RESERVED0_MASK 0xfe00 5356 #define PMD_X1_CONTROL_RESERVED0_ALIGN 0 5357 #define PMD_X1_CONTROL_RESERVED0_BITS 7 5358 #define PMD_X1_CONTROL_RESERVED0_SHIFT 9 5359 5360 /* pmd_x1 :: control :: pram_ability [08:08] */ 5361 #define PMD_X1_CONTROL_PRAM_ABILITY_MASK 0x0100 5362 #define PMD_X1_CONTROL_PRAM_ABILITY_ALIGN 0 5363 #define PMD_X1_CONTROL_PRAM_ABILITY_BITS 1 5364 #define PMD_X1_CONTROL_PRAM_ABILITY_SHIFT 8 5365 5366 /* pmd_x1 :: control :: reserved1 [07:02] */ 5367 #define PMD_X1_CONTROL_RESERVED1_MASK 0x00fc 5368 #define PMD_X1_CONTROL_RESERVED1_ALIGN 0 5369 #define PMD_X1_CONTROL_RESERVED1_BITS 6 5370 #define PMD_X1_CONTROL_RESERVED1_SHIFT 2 5371 5372 /* pmd_x1 :: control :: por_h_rstb [01:01] */ 5373 #define PMD_X1_CONTROL_POR_H_RSTB_MASK 0x0002 5374 #define PMD_X1_CONTROL_POR_H_RSTB_ALIGN 0 5375 #define PMD_X1_CONTROL_POR_H_RSTB_BITS 1 5376 #define PMD_X1_CONTROL_POR_H_RSTB_SHIFT 1 5377 5378 /* pmd_x1 :: control :: core_dp_h_rstb [00:00] */ 5379 #define PMD_X1_CONTROL_CORE_DP_H_RSTB_MASK 0x0001 5380 #define PMD_X1_CONTROL_CORE_DP_H_RSTB_ALIGN 0 5381 #define PMD_X1_CONTROL_CORE_DP_H_RSTB_BITS 1 5382 #define PMD_X1_CONTROL_CORE_DP_H_RSTB_SHIFT 0 5383 5384 5385 /**************************************************************************** 5386 * pmd_x1 :: mode 5387 */ 5388 /* pmd_x1 :: mode :: core_mode [15:00] */ 5389 #define PMD_X1_MODE_CORE_MODE_MASK 0xffff 5390 #define PMD_X1_MODE_CORE_MODE_ALIGN 0 5391 #define PMD_X1_MODE_CORE_MODE_BITS 16 5392 #define PMD_X1_MODE_CORE_MODE_SHIFT 0 5393 5394 5395 /**************************************************************************** 5396 * pmd_x1 :: status 5397 */ 5398 /* pmd_x1 :: status :: reserved0 [15:02] */ 5399 #define PMD_X1_STATUS_RESERVED0_MASK 0xfffc 5400 #define PMD_X1_STATUS_RESERVED0_ALIGN 0 5401 #define PMD_X1_STATUS_RESERVED0_BITS 14 5402 #define PMD_X1_STATUS_RESERVED0_SHIFT 2 5403 5404 /* pmd_x1 :: status :: tx_clk_vld_sts [01:01] */ 5405 #define PMD_X1_STATUS_TX_CLK_VLD_STS_MASK 0x0002 5406 #define PMD_X1_STATUS_TX_CLK_VLD_STS_ALIGN 0 5407 #define PMD_X1_STATUS_TX_CLK_VLD_STS_BITS 1 5408 #define PMD_X1_STATUS_TX_CLK_VLD_STS_SHIFT 1 5409 5410 /* pmd_x1 :: status :: pll_lock_sts [00:00] */ 5411 #define PMD_X1_STATUS_PLL_LOCK_STS_MASK 0x0001 5412 #define PMD_X1_STATUS_PLL_LOCK_STS_ALIGN 0 5413 #define PMD_X1_STATUS_PLL_LOCK_STS_BITS 1 5414 #define PMD_X1_STATUS_PLL_LOCK_STS_SHIFT 0 5415 5416 5417 /**************************************************************************** 5418 * pmd_x1 :: latch_status 5419 */ 5420 /* pmd_x1 :: latch_status :: reserved0 [15:04] */ 5421 #define PMD_X1_LATCH_STATUS_RESERVED0_MASK 0xfff0 5422 #define PMD_X1_LATCH_STATUS_RESERVED0_ALIGN 0 5423 #define PMD_X1_LATCH_STATUS_RESERVED0_BITS 12 5424 #define PMD_X1_LATCH_STATUS_RESERVED0_SHIFT 4 5425 5426 /* pmd_x1 :: latch_status :: tx_clk_vld_LH [03:03] */ 5427 #define PMD_X1_LATCH_STATUS_TX_CLK_VLD_LH_MASK 0x0008 5428 #define PMD_X1_LATCH_STATUS_TX_CLK_VLD_LH_ALIGN 0 5429 #define PMD_X1_LATCH_STATUS_TX_CLK_VLD_LH_BITS 1 5430 #define PMD_X1_LATCH_STATUS_TX_CLK_VLD_LH_SHIFT 3 5431 5432 /* pmd_x1 :: latch_status :: tx_clk_vld_LL [02:02] */ 5433 #define PMD_X1_LATCH_STATUS_TX_CLK_VLD_LL_MASK 0x0004 5434 #define PMD_X1_LATCH_STATUS_TX_CLK_VLD_LL_ALIGN 0 5435 #define PMD_X1_LATCH_STATUS_TX_CLK_VLD_LL_BITS 1 5436 #define PMD_X1_LATCH_STATUS_TX_CLK_VLD_LL_SHIFT 2 5437 5438 /* pmd_x1 :: latch_status :: pll_lock_LH [01:01] */ 5439 #define PMD_X1_LATCH_STATUS_PLL_LOCK_LH_MASK 0x0002 5440 #define PMD_X1_LATCH_STATUS_PLL_LOCK_LH_ALIGN 0 5441 #define PMD_X1_LATCH_STATUS_PLL_LOCK_LH_BITS 1 5442 #define PMD_X1_LATCH_STATUS_PLL_LOCK_LH_SHIFT 1 5443 5444 /* pmd_x1 :: latch_status :: pll_lock_LL [00:00] */ 5445 #define PMD_X1_LATCH_STATUS_PLL_LOCK_LL_MASK 0x0001 5446 #define PMD_X1_LATCH_STATUS_PLL_LOCK_LL_ALIGN 0 5447 #define PMD_X1_LATCH_STATUS_PLL_LOCK_LL_BITS 1 5448 #define PMD_X1_LATCH_STATUS_PLL_LOCK_LL_SHIFT 0 5449 5450 5451 /**************************************************************************** 5452 * pmd_x1 :: override 5453 */ 5454 /* pmd_x1 :: override :: reserved0 [15:04] */ 5455 #define PMD_X1_OVERRIDE_RESERVED0_MASK 0xfff0 5456 #define PMD_X1_OVERRIDE_RESERVED0_ALIGN 0 5457 #define PMD_X1_OVERRIDE_RESERVED0_BITS 12 5458 #define PMD_X1_OVERRIDE_RESERVED0_SHIFT 4 5459 5460 /* pmd_x1 :: override :: core_dp_h_rstb_oen [03:03] */ 5461 #define PMD_X1_OVERRIDE_CORE_DP_H_RSTB_OEN_MASK 0x0008 5462 #define PMD_X1_OVERRIDE_CORE_DP_H_RSTB_OEN_ALIGN 0 5463 #define PMD_X1_OVERRIDE_CORE_DP_H_RSTB_OEN_BITS 1 5464 #define PMD_X1_OVERRIDE_CORE_DP_H_RSTB_OEN_SHIFT 3 5465 5466 /* pmd_x1 :: override :: core_mode_oen [02:02] */ 5467 #define PMD_X1_OVERRIDE_CORE_MODE_OEN_MASK 0x0004 5468 #define PMD_X1_OVERRIDE_CORE_MODE_OEN_ALIGN 0 5469 #define PMD_X1_OVERRIDE_CORE_MODE_OEN_BITS 1 5470 #define PMD_X1_OVERRIDE_CORE_MODE_OEN_SHIFT 2 5471 5472 /* pmd_x1 :: override :: tx_clk_vld_ovrd [01:01] */ 5473 #define PMD_X1_OVERRIDE_TX_CLK_VLD_OVRD_MASK 0x0002 5474 #define PMD_X1_OVERRIDE_TX_CLK_VLD_OVRD_ALIGN 0 5475 #define PMD_X1_OVERRIDE_TX_CLK_VLD_OVRD_BITS 1 5476 #define PMD_X1_OVERRIDE_TX_CLK_VLD_OVRD_SHIFT 1 5477 5478 /* pmd_x1 :: override :: pll_lock_ovrd [00:00] */ 5479 #define PMD_X1_OVERRIDE_PLL_LOCK_OVRD_MASK 0x0001 5480 #define PMD_X1_OVERRIDE_PLL_LOCK_OVRD_ALIGN 0 5481 #define PMD_X1_OVERRIDE_PLL_LOCK_OVRD_BITS 1 5482 #define PMD_X1_OVERRIDE_PLL_LOCK_OVRD_SHIFT 0 5483 5484 5485 /**************************************************************************** 5486 * TSCE_TSCE_USER1_PktGen0 5487 */ 5488 /**************************************************************************** 5489 * PktGen0 :: PktGenCtrl1 5490 */ 5491 /* PktGen0 :: PktGenCtrl1 :: number_pkt [15:12] */ 5492 #define PKTGEN0_PKTGENCTRL1_NUMBER_PKT_MASK 0xf000 5493 #define PKTGEN0_PKTGENCTRL1_NUMBER_PKT_ALIGN 0 5494 #define PKTGEN0_PKTGENCTRL1_NUMBER_PKT_BITS 4 5495 #define PKTGEN0_PKTGENCTRL1_NUMBER_PKT_SHIFT 12 5496 5497 /* PktGen0 :: PktGenCtrl1 :: rx_pkt_check_en [11:11] */ 5498 #define PKTGEN0_PKTGENCTRL1_RX_PKT_CHECK_EN_MASK 0x0800 5499 #define PKTGEN0_PKTGENCTRL1_RX_PKT_CHECK_EN_ALIGN 0 5500 #define PKTGEN0_PKTGENCTRL1_RX_PKT_CHECK_EN_BITS 1 5501 #define PKTGEN0_PKTGENCTRL1_RX_PKT_CHECK_EN_SHIFT 11 5502 5503 /* PktGen0 :: PktGenCtrl1 :: rx_MSBUS_type [10:10] */ 5504 #define PKTGEN0_PKTGENCTRL1_RX_MSBUS_TYPE_MASK 0x0400 5505 #define PKTGEN0_PKTGENCTRL1_RX_MSBUS_TYPE_ALIGN 0 5506 #define PKTGEN0_PKTGENCTRL1_RX_MSBUS_TYPE_BITS 1 5507 #define PKTGEN0_PKTGENCTRL1_RX_MSBUS_TYPE_SHIFT 10 5508 5509 /* PktGen0 :: PktGenCtrl1 :: clr_crccnt [09:09] */ 5510 #define PKTGEN0_PKTGENCTRL1_CLR_CRCCNT_MASK 0x0200 5511 #define PKTGEN0_PKTGENCTRL1_CLR_CRCCNT_ALIGN 0 5512 #define PKTGEN0_PKTGENCTRL1_CLR_CRCCNT_BITS 1 5513 #define PKTGEN0_PKTGENCTRL1_CLR_CRCCNT_SHIFT 9 5514 5515 /* PktGen0 :: PktGenCtrl1 :: rx_port_sel [08:07] */ 5516 #define PKTGEN0_PKTGENCTRL1_RX_PORT_SEL_MASK 0x0180 5517 #define PKTGEN0_PKTGENCTRL1_RX_PORT_SEL_ALIGN 0 5518 #define PKTGEN0_PKTGENCTRL1_RX_PORT_SEL_BITS 2 5519 #define PKTGEN0_PKTGENCTRL1_RX_PORT_SEL_SHIFT 7 5520 5521 /* PktGen0 :: PktGenCtrl1 :: tx_prtp_en [06:06] */ 5522 #define PKTGEN0_PKTGENCTRL1_TX_PRTP_EN_MASK 0x0040 5523 #define PKTGEN0_PKTGENCTRL1_TX_PRTP_EN_ALIGN 0 5524 #define PKTGEN0_PKTGENCTRL1_TX_PRTP_EN_BITS 1 5525 #define PKTGEN0_PKTGENCTRL1_TX_PRTP_EN_SHIFT 6 5526 5527 /* PktGen0 :: PktGenCtrl1 :: prtp_data_pattern_sel [05:05] */ 5528 #define PKTGEN0_PKTGENCTRL1_PRTP_DATA_PATTERN_SEL_MASK 0x0020 5529 #define PKTGEN0_PKTGENCTRL1_PRTP_DATA_PATTERN_SEL_ALIGN 0 5530 #define PKTGEN0_PKTGENCTRL1_PRTP_DATA_PATTERN_SEL_BITS 1 5531 #define PKTGEN0_PKTGENCTRL1_PRTP_DATA_PATTERN_SEL_SHIFT 5 5532 5533 /* PktGen0 :: PktGenCtrl1 :: reserved0 [04:04] */ 5534 #define PKTGEN0_PKTGENCTRL1_RESERVED0_MASK 0x0010 5535 #define PKTGEN0_PKTGENCTRL1_RESERVED0_ALIGN 0 5536 #define PKTGEN0_PKTGENCTRL1_RESERVED0_BITS 1 5537 #define PKTGEN0_PKTGENCTRL1_RESERVED0_SHIFT 4 5538 5539 /* PktGen0 :: PktGenCtrl1 :: lpi_en [03:03] */ 5540 #define PKTGEN0_PKTGENCTRL1_LPI_EN_MASK 0x0008 5541 #define PKTGEN0_PKTGENCTRL1_LPI_EN_ALIGN 0 5542 #define PKTGEN0_PKTGENCTRL1_LPI_EN_BITS 1 5543 #define PKTGEN0_PKTGENCTRL1_LPI_EN_SHIFT 3 5544 5545 /* PktGen0 :: PktGenCtrl1 :: tx_test_port_sel [02:01] */ 5546 #define PKTGEN0_PKTGENCTRL1_TX_TEST_PORT_SEL_MASK 0x0006 5547 #define PKTGEN0_PKTGENCTRL1_TX_TEST_PORT_SEL_ALIGN 0 5548 #define PKTGEN0_PKTGENCTRL1_TX_TEST_PORT_SEL_BITS 2 5549 #define PKTGEN0_PKTGENCTRL1_TX_TEST_PORT_SEL_SHIFT 1 5550 5551 /* PktGen0 :: PktGenCtrl1 :: pkt_or_prtp [00:00] */ 5552 #define PKTGEN0_PKTGENCTRL1_PKT_OR_PRTP_MASK 0x0001 5553 #define PKTGEN0_PKTGENCTRL1_PKT_OR_PRTP_ALIGN 0 5554 #define PKTGEN0_PKTGENCTRL1_PKT_OR_PRTP_BITS 1 5555 #define PKTGEN0_PKTGENCTRL1_PKT_OR_PRTP_SHIFT 0 5556 5557 5558 /**************************************************************************** 5559 * PktGen0 :: PktGenCtrl2 5560 */ 5561 /* PktGen0 :: PktGenCtrl2 :: pktgen_en [15:15] */ 5562 #define PKTGEN0_PKTGENCTRL2_PKTGEN_EN_MASK 0x8000 5563 #define PKTGEN0_PKTGENCTRL2_PKTGEN_EN_ALIGN 0 5564 #define PKTGEN0_PKTGENCTRL2_PKTGEN_EN_BITS 1 5565 #define PKTGEN0_PKTGENCTRL2_PKTGEN_EN_SHIFT 15 5566 5567 /* PktGen0 :: PktGenCtrl2 :: tx_MSBUS_type [14:14] */ 5568 #define PKTGEN0_PKTGENCTRL2_TX_MSBUS_TYPE_MASK 0x4000 5569 #define PKTGEN0_PKTGENCTRL2_TX_MSBUS_TYPE_ALIGN 0 5570 #define PKTGEN0_PKTGENCTRL2_TX_MSBUS_TYPE_BITS 1 5571 #define PKTGEN0_PKTGENCTRL2_TX_MSBUS_TYPE_SHIFT 14 5572 5573 /* PktGen0 :: PktGenCtrl2 :: payload_type [13:11] */ 5574 #define PKTGEN0_PKTGENCTRL2_PAYLOAD_TYPE_MASK 0x3800 5575 #define PKTGEN0_PKTGENCTRL2_PAYLOAD_TYPE_ALIGN 0 5576 #define PKTGEN0_PKTGENCTRL2_PAYLOAD_TYPE_BITS 3 5577 #define PKTGEN0_PKTGENCTRL2_PAYLOAD_TYPE_SHIFT 11 5578 5579 /* PktGen0 :: PktGenCtrl2 :: pkt_size [10:05] */ 5580 #define PKTGEN0_PKTGENCTRL2_PKT_SIZE_MASK 0x07e0 5581 #define PKTGEN0_PKTGENCTRL2_PKT_SIZE_ALIGN 0 5582 #define PKTGEN0_PKTGENCTRL2_PKT_SIZE_BITS 6 5583 #define PKTGEN0_PKTGENCTRL2_PKT_SIZE_SHIFT 5 5584 5585 /* PktGen0 :: PktGenCtrl2 :: ipg_size [04:00] */ 5586 #define PKTGEN0_PKTGENCTRL2_IPG_SIZE_MASK 0x001f 5587 #define PKTGEN0_PKTGENCTRL2_IPG_SIZE_ALIGN 0 5588 #define PKTGEN0_PKTGENCTRL2_IPG_SIZE_BITS 5 5589 #define PKTGEN0_PKTGENCTRL2_IPG_SIZE_SHIFT 0 5590 5591 5592 /**************************************************************************** 5593 * PktGen0 :: PrtpControl 5594 */ 5595 /* PktGen0 :: PrtpControl :: reserved0 [15:09] */ 5596 #define PKTGEN0_PRTPCONTROL_RESERVED0_MASK 0xfe00 5597 #define PKTGEN0_PRTPCONTROL_RESERVED0_ALIGN 0 5598 #define PKTGEN0_PRTPCONTROL_RESERVED0_BITS 7 5599 #define PKTGEN0_PRTPCONTROL_RESERVED0_SHIFT 9 5600 5601 /* PktGen0 :: PrtpControl :: errgen_en [08:05] */ 5602 #define PKTGEN0_PRTPCONTROL_ERRGEN_EN_MASK 0x01e0 5603 #define PKTGEN0_PRTPCONTROL_ERRGEN_EN_ALIGN 0 5604 #define PKTGEN0_PRTPCONTROL_ERRGEN_EN_BITS 4 5605 #define PKTGEN0_PRTPCONTROL_ERRGEN_EN_SHIFT 5 5606 5607 /* PktGen0 :: PrtpControl :: rx_prtp_en [04:04] */ 5608 #define PKTGEN0_PRTPCONTROL_RX_PRTP_EN_MASK 0x0010 5609 #define PKTGEN0_PRTPCONTROL_RX_PRTP_EN_ALIGN 0 5610 #define PKTGEN0_PRTPCONTROL_RX_PRTP_EN_BITS 1 5611 #define PKTGEN0_PRTPCONTROL_RX_PRTP_EN_SHIFT 4 5612 5613 /* PktGen0 :: PrtpControl :: reserved1 [03:00] */ 5614 #define PKTGEN0_PRTPCONTROL_RESERVED1_MASK 0x000f 5615 #define PKTGEN0_PRTPCONTROL_RESERVED1_ALIGN 0 5616 #define PKTGEN0_PRTPCONTROL_RESERVED1_BITS 4 5617 #define PKTGEN0_PRTPCONTROL_RESERVED1_SHIFT 0 5618 5619 5620 /**************************************************************************** 5621 * PktGen0 :: CrcErrorCount 5622 */ 5623 /* PktGen0 :: CrcErrorCount :: crcerrcnt [15:00] */ 5624 #define PKTGEN0_CRCERRORCOUNT_CRCERRCNT_MASK 0xffff 5625 #define PKTGEN0_CRCERRORCOUNT_CRCERRCNT_ALIGN 0 5626 #define PKTGEN0_CRCERRORCOUNT_CRCERRCNT_BITS 16 5627 #define PKTGEN0_CRCERRORCOUNT_CRCERRCNT_SHIFT 0 5628 5629 5630 /**************************************************************************** 5631 * PktGen0 :: PrtpErrorCounter 5632 */ 5633 /* PktGen0 :: PrtpErrorCounter :: prtp_err_count [15:00] */ 5634 #define PKTGEN0_PRTPERRORCOUNTER_PRTP_ERR_COUNT_MASK 0xffff 5635 #define PKTGEN0_PRTPERRORCOUNTER_PRTP_ERR_COUNT_ALIGN 0 5636 #define PKTGEN0_PRTPERRORCOUNTER_PRTP_ERR_COUNT_BITS 16 5637 #define PKTGEN0_PRTPERRORCOUNTER_PRTP_ERR_COUNT_SHIFT 0 5638 5639 5640 /**************************************************************************** 5641 * PktGen0 :: PrtpLockStatus 5642 */ 5643 /* PktGen0 :: PrtpLockStatus :: reserved0 [15:01] */ 5644 #define PKTGEN0_PRTPLOCKSTATUS_RESERVED0_MASK 0xfffe 5645 #define PKTGEN0_PRTPLOCKSTATUS_RESERVED0_ALIGN 0 5646 #define PKTGEN0_PRTPLOCKSTATUS_RESERVED0_BITS 15 5647 #define PKTGEN0_PRTPLOCKSTATUS_RESERVED0_SHIFT 1 5648 5649 /* PktGen0 :: PrtpLockStatus :: prtp_lock [00:00] */ 5650 #define PKTGEN0_PRTPLOCKSTATUS_PRTP_LOCK_MASK 0x0001 5651 #define PKTGEN0_PRTPLOCKSTATUS_PRTP_LOCK_ALIGN 0 5652 #define PKTGEN0_PRTPLOCKSTATUS_PRTP_LOCK_BITS 1 5653 #define PKTGEN0_PRTPLOCKSTATUS_PRTP_LOCK_SHIFT 0 5654 5655 5656 /**************************************************************************** 5657 * PktGen0 :: PCS_seedA0 5658 */ 5659 /* PktGen0 :: PCS_seedA0 :: seedA0 [15:00] */ 5660 #define PKTGEN0_PCS_SEEDA0_SEEDA0_MASK 0xffff 5661 #define PKTGEN0_PCS_SEEDA0_SEEDA0_ALIGN 0 5662 #define PKTGEN0_PCS_SEEDA0_SEEDA0_BITS 16 5663 #define PKTGEN0_PCS_SEEDA0_SEEDA0_SHIFT 0 5664 5665 5666 /**************************************************************************** 5667 * PktGen0 :: PCS_seedA1 5668 */ 5669 /* PktGen0 :: PCS_seedA1 :: seedA1 [15:00] */ 5670 #define PKTGEN0_PCS_SEEDA1_SEEDA1_MASK 0xffff 5671 #define PKTGEN0_PCS_SEEDA1_SEEDA1_ALIGN 0 5672 #define PKTGEN0_PCS_SEEDA1_SEEDA1_BITS 16 5673 #define PKTGEN0_PCS_SEEDA1_SEEDA1_SHIFT 0 5674 5675 5676 /**************************************************************************** 5677 * PktGen0 :: PCS_seedA2 5678 */ 5679 /* PktGen0 :: PCS_seedA2 :: seedA2 [15:00] */ 5680 #define PKTGEN0_PCS_SEEDA2_SEEDA2_MASK 0xffff 5681 #define PKTGEN0_PCS_SEEDA2_SEEDA2_ALIGN 0 5682 #define PKTGEN0_PCS_SEEDA2_SEEDA2_BITS 16 5683 #define PKTGEN0_PCS_SEEDA2_SEEDA2_SHIFT 0 5684 5685 5686 /**************************************************************************** 5687 * PktGen0 :: PCS_seedA3 5688 */ 5689 /* PktGen0 :: PCS_seedA3 :: reserved0 [15:10] */ 5690 #define PKTGEN0_PCS_SEEDA3_RESERVED0_MASK 0xfc00 5691 #define PKTGEN0_PCS_SEEDA3_RESERVED0_ALIGN 0 5692 #define PKTGEN0_PCS_SEEDA3_RESERVED0_BITS 6 5693 #define PKTGEN0_PCS_SEEDA3_RESERVED0_SHIFT 10 5694 5695 /* PktGen0 :: PCS_seedA3 :: seedA3 [09:00] */ 5696 #define PKTGEN0_PCS_SEEDA3_SEEDA3_MASK 0x03ff 5697 #define PKTGEN0_PCS_SEEDA3_SEEDA3_ALIGN 0 5698 #define PKTGEN0_PCS_SEEDA3_SEEDA3_BITS 10 5699 #define PKTGEN0_PCS_SEEDA3_SEEDA3_SHIFT 0 5700 5701 5702 /**************************************************************************** 5703 * PktGen0 :: PCS_seedB0 5704 */ 5705 /* PktGen0 :: PCS_seedB0 :: seedB0 [15:00] */ 5706 #define PKTGEN0_PCS_SEEDB0_SEEDB0_MASK 0xffff 5707 #define PKTGEN0_PCS_SEEDB0_SEEDB0_ALIGN 0 5708 #define PKTGEN0_PCS_SEEDB0_SEEDB0_BITS 16 5709 #define PKTGEN0_PCS_SEEDB0_SEEDB0_SHIFT 0 5710 5711 5712 /**************************************************************************** 5713 * PktGen0 :: PCS_seedB1 5714 */ 5715 /* PktGen0 :: PCS_seedB1 :: seedB1 [15:00] */ 5716 #define PKTGEN0_PCS_SEEDB1_SEEDB1_MASK 0xffff 5717 #define PKTGEN0_PCS_SEEDB1_SEEDB1_ALIGN 0 5718 #define PKTGEN0_PCS_SEEDB1_SEEDB1_BITS 16 5719 #define PKTGEN0_PCS_SEEDB1_SEEDB1_SHIFT 0 5720 5721 5722 /**************************************************************************** 5723 * PktGen0 :: PCS_seedB2 5724 */ 5725 /* PktGen0 :: PCS_seedB2 :: seedB2 [15:00] */ 5726 #define PKTGEN0_PCS_SEEDB2_SEEDB2_MASK 0xffff 5727 #define PKTGEN0_PCS_SEEDB2_SEEDB2_ALIGN 0 5728 #define PKTGEN0_PCS_SEEDB2_SEEDB2_BITS 16 5729 #define PKTGEN0_PCS_SEEDB2_SEEDB2_SHIFT 0 5730 5731 5732 /**************************************************************************** 5733 * PktGen0 :: PCS_seedB3 5734 */ 5735 /* PktGen0 :: PCS_seedB3 :: reserved0 [15:10] */ 5736 #define PKTGEN0_PCS_SEEDB3_RESERVED0_MASK 0xfc00 5737 #define PKTGEN0_PCS_SEEDB3_RESERVED0_ALIGN 0 5738 #define PKTGEN0_PCS_SEEDB3_RESERVED0_BITS 6 5739 #define PKTGEN0_PCS_SEEDB3_RESERVED0_SHIFT 10 5740 5741 /* PktGen0 :: PCS_seedB3 :: seedB3 [09:00] */ 5742 #define PKTGEN0_PCS_SEEDB3_SEEDB3_MASK 0x03ff 5743 #define PKTGEN0_PCS_SEEDB3_SEEDB3_ALIGN 0 5744 #define PKTGEN0_PCS_SEEDB3_SEEDB3_BITS 10 5745 #define PKTGEN0_PCS_SEEDB3_SEEDB3_SHIFT 0 5746 5747 5748 /**************************************************************************** 5749 * TSCE_TSCE_USER1_PktGen1 5750 */ 5751 /**************************************************************************** 5752 * PktGen1 :: PayloadBytes 5753 */ 5754 /* PktGen1 :: PayloadBytes :: byte1 [15:08] */ 5755 #define PKTGEN1_PAYLOADBYTES_BYTE1_MASK 0xff00 5756 #define PKTGEN1_PAYLOADBYTES_BYTE1_ALIGN 0 5757 #define PKTGEN1_PAYLOADBYTES_BYTE1_BITS 8 5758 #define PKTGEN1_PAYLOADBYTES_BYTE1_SHIFT 8 5759 5760 /* PktGen1 :: PayloadBytes :: byte0 [07:00] */ 5761 #define PKTGEN1_PAYLOADBYTES_BYTE0_MASK 0x00ff 5762 #define PKTGEN1_PAYLOADBYTES_BYTE0_ALIGN 0 5763 #define PKTGEN1_PAYLOADBYTES_BYTE0_BITS 8 5764 #define PKTGEN1_PAYLOADBYTES_BYTE0_SHIFT 0 5765 5766 5767 /**************************************************************************** 5768 * PktGen1 :: ErrorMask4 5769 */ 5770 /* PktGen1 :: ErrorMask4 :: error_mask_79_64 [15:00] */ 5771 #define PKTGEN1_ERRORMASK4_ERROR_MASK_79_64_MASK 0xffff 5772 #define PKTGEN1_ERRORMASK4_ERROR_MASK_79_64_ALIGN 0 5773 #define PKTGEN1_ERRORMASK4_ERROR_MASK_79_64_BITS 16 5774 #define PKTGEN1_ERRORMASK4_ERROR_MASK_79_64_SHIFT 0 5775 5776 5777 /**************************************************************************** 5778 * PktGen1 :: ErrorMask3 5779 */ 5780 /* PktGen1 :: ErrorMask3 :: error_mask_63_48 [15:00] */ 5781 #define PKTGEN1_ERRORMASK3_ERROR_MASK_63_48_MASK 0xffff 5782 #define PKTGEN1_ERRORMASK3_ERROR_MASK_63_48_ALIGN 0 5783 #define PKTGEN1_ERRORMASK3_ERROR_MASK_63_48_BITS 16 5784 #define PKTGEN1_ERRORMASK3_ERROR_MASK_63_48_SHIFT 0 5785 5786 5787 /**************************************************************************** 5788 * PktGen1 :: ErrorMask2 5789 */ 5790 /* PktGen1 :: ErrorMask2 :: error_mask_47_32 [15:00] */ 5791 #define PKTGEN1_ERRORMASK2_ERROR_MASK_47_32_MASK 0xffff 5792 #define PKTGEN1_ERRORMASK2_ERROR_MASK_47_32_ALIGN 0 5793 #define PKTGEN1_ERRORMASK2_ERROR_MASK_47_32_BITS 16 5794 #define PKTGEN1_ERRORMASK2_ERROR_MASK_47_32_SHIFT 0 5795 5796 5797 /**************************************************************************** 5798 * PktGen1 :: ErrorMask1 5799 */ 5800 /* PktGen1 :: ErrorMask1 :: error_mask_31_16 [15:00] */ 5801 #define PKTGEN1_ERRORMASK1_ERROR_MASK_31_16_MASK 0xffff 5802 #define PKTGEN1_ERRORMASK1_ERROR_MASK_31_16_ALIGN 0 5803 #define PKTGEN1_ERRORMASK1_ERROR_MASK_31_16_BITS 16 5804 #define PKTGEN1_ERRORMASK1_ERROR_MASK_31_16_SHIFT 0 5805 5806 5807 /**************************************************************************** 5808 * PktGen1 :: ErrorMask0 5809 */ 5810 /* PktGen1 :: ErrorMask0 :: error_mask_15_0 [15:00] */ 5811 #define PKTGEN1_ERRORMASK0_ERROR_MASK_15_0_MASK 0xffff 5812 #define PKTGEN1_ERRORMASK0_ERROR_MASK_15_0_ALIGN 0 5813 #define PKTGEN1_ERRORMASK0_ERROR_MASK_15_0_BITS 16 5814 #define PKTGEN1_ERRORMASK0_ERROR_MASK_15_0_SHIFT 0 5815 5816 5817 /**************************************************************************** 5818 * TSCE_TSCE_USER1_mem_ecc 5819 */ 5820 /**************************************************************************** 5821 * mem_ecc :: ecc_int_1bit 5822 */ 5823 /* mem_ecc :: ecc_int_1bit :: reserved0 [15:04] */ 5824 #define MEM_ECC_ECC_INT_1BIT_RESERVED0_MASK 0xfff0 5825 #define MEM_ECC_ECC_INT_1BIT_RESERVED0_ALIGN 0 5826 #define MEM_ECC_ECC_INT_1BIT_RESERVED0_BITS 12 5827 #define MEM_ECC_ECC_INT_1BIT_RESERVED0_SHIFT 4 5828 5829 /* mem_ecc :: ecc_int_1bit :: int_1b [03:00] */ 5830 #define MEM_ECC_ECC_INT_1BIT_INT_1B_MASK 0x000f 5831 #define MEM_ECC_ECC_INT_1BIT_INT_1B_ALIGN 0 5832 #define MEM_ECC_ECC_INT_1BIT_INT_1B_BITS 4 5833 #define MEM_ECC_ECC_INT_1BIT_INT_1B_SHIFT 0 5834 5835 5836 /**************************************************************************** 5837 * mem_ecc :: ecc_int_2bit 5838 */ 5839 /* mem_ecc :: ecc_int_2bit :: reserved0 [15:04] */ 5840 #define MEM_ECC_ECC_INT_2BIT_RESERVED0_MASK 0xfff0 5841 #define MEM_ECC_ECC_INT_2BIT_RESERVED0_ALIGN 0 5842 #define MEM_ECC_ECC_INT_2BIT_RESERVED0_BITS 12 5843 #define MEM_ECC_ECC_INT_2BIT_RESERVED0_SHIFT 4 5844 5845 /* mem_ecc :: ecc_int_2bit :: int_2b [03:00] */ 5846 #define MEM_ECC_ECC_INT_2BIT_INT_2B_MASK 0x000f 5847 #define MEM_ECC_ECC_INT_2BIT_INT_2B_ALIGN 0 5848 #define MEM_ECC_ECC_INT_2BIT_INT_2B_BITS 4 5849 #define MEM_ECC_ECC_INT_2BIT_INT_2B_SHIFT 0 5850 5851 5852 /**************************************************************************** 5853 * mem_ecc :: ecc_msk_1bit 5854 */ 5855 /* mem_ecc :: ecc_msk_1bit :: reserved0 [15:04] */ 5856 #define MEM_ECC_ECC_MSK_1BIT_RESERVED0_MASK 0xfff0 5857 #define MEM_ECC_ECC_MSK_1BIT_RESERVED0_ALIGN 0 5858 #define MEM_ECC_ECC_MSK_1BIT_RESERVED0_BITS 12 5859 #define MEM_ECC_ECC_MSK_1BIT_RESERVED0_SHIFT 4 5860 5861 /* mem_ecc :: ecc_msk_1bit :: msk_1b [03:00] */ 5862 #define MEM_ECC_ECC_MSK_1BIT_MSK_1B_MASK 0x000f 5863 #define MEM_ECC_ECC_MSK_1BIT_MSK_1B_ALIGN 0 5864 #define MEM_ECC_ECC_MSK_1BIT_MSK_1B_BITS 4 5865 #define MEM_ECC_ECC_MSK_1BIT_MSK_1B_SHIFT 0 5866 5867 5868 /**************************************************************************** 5869 * mem_ecc :: ecc_msk_2bit 5870 */ 5871 /* mem_ecc :: ecc_msk_2bit :: reserved0 [15:04] */ 5872 #define MEM_ECC_ECC_MSK_2BIT_RESERVED0_MASK 0xfff0 5873 #define MEM_ECC_ECC_MSK_2BIT_RESERVED0_ALIGN 0 5874 #define MEM_ECC_ECC_MSK_2BIT_RESERVED0_BITS 12 5875 #define MEM_ECC_ECC_MSK_2BIT_RESERVED0_SHIFT 4 5876 5877 /* mem_ecc :: ecc_msk_2bit :: msk_2b [03:00] */ 5878 #define MEM_ECC_ECC_MSK_2BIT_MSK_2B_MASK 0x000f 5879 #define MEM_ECC_ECC_MSK_2BIT_MSK_2B_ALIGN 0 5880 #define MEM_ECC_ECC_MSK_2BIT_MSK_2B_BITS 4 5881 #define MEM_ECC_ECC_MSK_2BIT_MSK_2B_SHIFT 0 5882 5883 5884 /**************************************************************************** 5885 * mem_ecc :: ecc_disable 5886 */ 5887 /* mem_ecc :: ecc_disable :: reserved0 [15:03] */ 5888 #define MEM_ECC_ECC_DISABLE_RESERVED0_MASK 0xfff8 5889 #define MEM_ECC_ECC_DISABLE_RESERVED0_ALIGN 0 5890 #define MEM_ECC_ECC_DISABLE_RESERVED0_BITS 13 5891 #define MEM_ECC_ECC_DISABLE_RESERVED0_SHIFT 3 5892 5893 /* mem_ecc :: ecc_disable :: rfec1_disable_ecc [02:02] */ 5894 #define MEM_ECC_ECC_DISABLE_RFEC1_DISABLE_ECC_MASK 0x0004 5895 #define MEM_ECC_ECC_DISABLE_RFEC1_DISABLE_ECC_ALIGN 0 5896 #define MEM_ECC_ECC_DISABLE_RFEC1_DISABLE_ECC_BITS 1 5897 #define MEM_ECC_ECC_DISABLE_RFEC1_DISABLE_ECC_SHIFT 2 5898 5899 /* mem_ecc :: ecc_disable :: rfec0_disable_ecc [01:01] */ 5900 #define MEM_ECC_ECC_DISABLE_RFEC0_DISABLE_ECC_MASK 0x0002 5901 #define MEM_ECC_ECC_DISABLE_RFEC0_DISABLE_ECC_ALIGN 0 5902 #define MEM_ECC_ECC_DISABLE_RFEC0_DISABLE_ECC_BITS 1 5903 #define MEM_ECC_ECC_DISABLE_RFEC0_DISABLE_ECC_SHIFT 1 5904 5905 /* mem_ecc :: ecc_disable :: deskew_disable_ecc [00:00] */ 5906 #define MEM_ECC_ECC_DISABLE_DESKEW_DISABLE_ECC_MASK 0x0001 5907 #define MEM_ECC_ECC_DISABLE_DESKEW_DISABLE_ECC_ALIGN 0 5908 #define MEM_ECC_ECC_DISABLE_DESKEW_DISABLE_ECC_BITS 1 5909 #define MEM_ECC_ECC_DISABLE_DESKEW_DISABLE_ECC_SHIFT 0 5910 5911 5912 /**************************************************************************** 5913 * mem_ecc :: ecc_corrupt 5914 */ 5915 /* mem_ecc :: ecc_corrupt :: reserved0 [15:06] */ 5916 #define MEM_ECC_ECC_CORRUPT_RESERVED0_MASK 0xffc0 5917 #define MEM_ECC_ECC_CORRUPT_RESERVED0_ALIGN 0 5918 #define MEM_ECC_ECC_CORRUPT_RESERVED0_BITS 10 5919 #define MEM_ECC_ECC_CORRUPT_RESERVED0_SHIFT 6 5920 5921 /* mem_ecc :: ecc_corrupt :: rfec1_ecc_corrupt [05:04] */ 5922 #define MEM_ECC_ECC_CORRUPT_RFEC1_ECC_CORRUPT_MASK 0x0030 5923 #define MEM_ECC_ECC_CORRUPT_RFEC1_ECC_CORRUPT_ALIGN 0 5924 #define MEM_ECC_ECC_CORRUPT_RFEC1_ECC_CORRUPT_BITS 2 5925 #define MEM_ECC_ECC_CORRUPT_RFEC1_ECC_CORRUPT_SHIFT 4 5926 5927 /* mem_ecc :: ecc_corrupt :: rfec0_ecc_corrupt [03:02] */ 5928 #define MEM_ECC_ECC_CORRUPT_RFEC0_ECC_CORRUPT_MASK 0x000c 5929 #define MEM_ECC_ECC_CORRUPT_RFEC0_ECC_CORRUPT_ALIGN 0 5930 #define MEM_ECC_ECC_CORRUPT_RFEC0_ECC_CORRUPT_BITS 2 5931 #define MEM_ECC_ECC_CORRUPT_RFEC0_ECC_CORRUPT_SHIFT 2 5932 5933 /* mem_ecc :: ecc_corrupt :: deskew_ecc_corrupt [01:00] */ 5934 #define MEM_ECC_ECC_CORRUPT_DESKEW_ECC_CORRUPT_MASK 0x0003 5935 #define MEM_ECC_ECC_CORRUPT_DESKEW_ECC_CORRUPT_ALIGN 0 5936 #define MEM_ECC_ECC_CORRUPT_DESKEW_ECC_CORRUPT_BITS 2 5937 #define MEM_ECC_ECC_CORRUPT_DESKEW_ECC_CORRUPT_SHIFT 0 5938 5939 5940 /**************************************************************************** 5941 * mem_ecc :: ecc_deskew_status 5942 */ 5943 /* mem_ecc :: ecc_deskew_status :: deskew_1bit_error [15:15] */ 5944 #define MEM_ECC_ECC_DESKEW_STATUS_DESKEW_1BIT_ERROR_MASK 0x8000 5945 #define MEM_ECC_ECC_DESKEW_STATUS_DESKEW_1BIT_ERROR_ALIGN 0 5946 #define MEM_ECC_ECC_DESKEW_STATUS_DESKEW_1BIT_ERROR_BITS 1 5947 #define MEM_ECC_ECC_DESKEW_STATUS_DESKEW_1BIT_ERROR_SHIFT 15 5948 5949 /* mem_ecc :: ecc_deskew_status :: deskew_2bit_error [14:14] */ 5950 #define MEM_ECC_ECC_DESKEW_STATUS_DESKEW_2BIT_ERROR_MASK 0x4000 5951 #define MEM_ECC_ECC_DESKEW_STATUS_DESKEW_2BIT_ERROR_ALIGN 0 5952 #define MEM_ECC_ECC_DESKEW_STATUS_DESKEW_2BIT_ERROR_BITS 1 5953 #define MEM_ECC_ECC_DESKEW_STATUS_DESKEW_2BIT_ERROR_SHIFT 14 5954 5955 /* mem_ecc :: ecc_deskew_status :: reserved0 [13:07] */ 5956 #define MEM_ECC_ECC_DESKEW_STATUS_RESERVED0_MASK 0x3f80 5957 #define MEM_ECC_ECC_DESKEW_STATUS_RESERVED0_ALIGN 0 5958 #define MEM_ECC_ECC_DESKEW_STATUS_RESERVED0_BITS 7 5959 #define MEM_ECC_ECC_DESKEW_STATUS_RESERVED0_SHIFT 7 5960 5961 /* mem_ecc :: ecc_deskew_status :: deskew_address [06:00] */ 5962 #define MEM_ECC_ECC_DESKEW_STATUS_DESKEW_ADDRESS_MASK 0x007f 5963 #define MEM_ECC_ECC_DESKEW_STATUS_DESKEW_ADDRESS_ALIGN 0 5964 #define MEM_ECC_ECC_DESKEW_STATUS_DESKEW_ADDRESS_BITS 7 5965 #define MEM_ECC_ECC_DESKEW_STATUS_DESKEW_ADDRESS_SHIFT 0 5966 5967 5968 /**************************************************************************** 5969 * mem_ecc :: ecc_rfec0_status 5970 */ 5971 /* mem_ecc :: ecc_rfec0_status :: rfec0_1bit_error [15:15] */ 5972 #define MEM_ECC_ECC_RFEC0_STATUS_RFEC0_1BIT_ERROR_MASK 0x8000 5973 #define MEM_ECC_ECC_RFEC0_STATUS_RFEC0_1BIT_ERROR_ALIGN 0 5974 #define MEM_ECC_ECC_RFEC0_STATUS_RFEC0_1BIT_ERROR_BITS 1 5975 #define MEM_ECC_ECC_RFEC0_STATUS_RFEC0_1BIT_ERROR_SHIFT 15 5976 5977 /* mem_ecc :: ecc_rfec0_status :: rfec0_2bit_error [14:14] */ 5978 #define MEM_ECC_ECC_RFEC0_STATUS_RFEC0_2BIT_ERROR_MASK 0x4000 5979 #define MEM_ECC_ECC_RFEC0_STATUS_RFEC0_2BIT_ERROR_ALIGN 0 5980 #define MEM_ECC_ECC_RFEC0_STATUS_RFEC0_2BIT_ERROR_BITS 1 5981 #define MEM_ECC_ECC_RFEC0_STATUS_RFEC0_2BIT_ERROR_SHIFT 14 5982 5983 /* mem_ecc :: ecc_rfec0_status :: reserved0 [13:08] */ 5984 #define MEM_ECC_ECC_RFEC0_STATUS_RESERVED0_MASK 0x3f00 5985 #define MEM_ECC_ECC_RFEC0_STATUS_RESERVED0_ALIGN 0 5986 #define MEM_ECC_ECC_RFEC0_STATUS_RESERVED0_BITS 6 5987 #define MEM_ECC_ECC_RFEC0_STATUS_RESERVED0_SHIFT 8 5988 5989 /* mem_ecc :: ecc_rfec0_status :: rfec0_address [07:00] */ 5990 #define MEM_ECC_ECC_RFEC0_STATUS_RFEC0_ADDRESS_MASK 0x00ff 5991 #define MEM_ECC_ECC_RFEC0_STATUS_RFEC0_ADDRESS_ALIGN 0 5992 #define MEM_ECC_ECC_RFEC0_STATUS_RFEC0_ADDRESS_BITS 8 5993 #define MEM_ECC_ECC_RFEC0_STATUS_RFEC0_ADDRESS_SHIFT 0 5994 5995 5996 /**************************************************************************** 5997 * mem_ecc :: ecc_rfec1_status 5998 */ 5999 /* mem_ecc :: ecc_rfec1_status :: rfec1_1bit_error [15:15] */ 6000 #define MEM_ECC_ECC_RFEC1_STATUS_RFEC1_1BIT_ERROR_MASK 0x8000 6001 #define MEM_ECC_ECC_RFEC1_STATUS_RFEC1_1BIT_ERROR_ALIGN 0 6002 #define MEM_ECC_ECC_RFEC1_STATUS_RFEC1_1BIT_ERROR_BITS 1 6003 #define MEM_ECC_ECC_RFEC1_STATUS_RFEC1_1BIT_ERROR_SHIFT 15 6004 6005 /* mem_ecc :: ecc_rfec1_status :: rfec1_2bit_error [14:14] */ 6006 #define MEM_ECC_ECC_RFEC1_STATUS_RFEC1_2BIT_ERROR_MASK 0x4000 6007 #define MEM_ECC_ECC_RFEC1_STATUS_RFEC1_2BIT_ERROR_ALIGN 0 6008 #define MEM_ECC_ECC_RFEC1_STATUS_RFEC1_2BIT_ERROR_BITS 1 6009 #define MEM_ECC_ECC_RFEC1_STATUS_RFEC1_2BIT_ERROR_SHIFT 14 6010 6011 /* mem_ecc :: ecc_rfec1_status :: reserved0 [13:08] */ 6012 #define MEM_ECC_ECC_RFEC1_STATUS_RESERVED0_MASK 0x3f00 6013 #define MEM_ECC_ECC_RFEC1_STATUS_RESERVED0_ALIGN 0 6014 #define MEM_ECC_ECC_RFEC1_STATUS_RESERVED0_BITS 6 6015 #define MEM_ECC_ECC_RFEC1_STATUS_RESERVED0_SHIFT 8 6016 6017 /* mem_ecc :: ecc_rfec1_status :: rfec1_address [07:00] */ 6018 #define MEM_ECC_ECC_RFEC1_STATUS_RFEC1_ADDRESS_MASK 0x00ff 6019 #define MEM_ECC_ECC_RFEC1_STATUS_RFEC1_ADDRESS_ALIGN 0 6020 #define MEM_ECC_ECC_RFEC1_STATUS_RFEC1_ADDRESS_BITS 8 6021 #define MEM_ECC_ECC_RFEC1_STATUS_RFEC1_ADDRESS_SHIFT 0 6022 6023 6024 /**************************************************************************** 6025 * TSCE_TSCE_USER1_mem_dbg 6026 */ 6027 /**************************************************************************** 6028 * mem_dbg :: mem_tm_deskew 6029 */ 6030 /* mem_dbg :: mem_tm_deskew :: reserved0 [15:12] */ 6031 #define MEM_DBG_MEM_TM_DESKEW_RESERVED0_MASK 0xf000 6032 #define MEM_DBG_MEM_TM_DESKEW_RESERVED0_ALIGN 0 6033 #define MEM_DBG_MEM_TM_DESKEW_RESERVED0_BITS 4 6034 #define MEM_DBG_MEM_TM_DESKEW_RESERVED0_SHIFT 12 6035 6036 /* mem_dbg :: mem_tm_deskew :: deskew_tm [11:00] */ 6037 #define MEM_DBG_MEM_TM_DESKEW_DESKEW_TM_MASK 0x0fff 6038 #define MEM_DBG_MEM_TM_DESKEW_DESKEW_TM_ALIGN 0 6039 #define MEM_DBG_MEM_TM_DESKEW_DESKEW_TM_BITS 12 6040 #define MEM_DBG_MEM_TM_DESKEW_DESKEW_TM_SHIFT 0 6041 6042 6043 /**************************************************************************** 6044 * mem_dbg :: mem_tm_rfec0 6045 */ 6046 /* mem_dbg :: mem_tm_rfec0 :: reserved0 [15:12] */ 6047 #define MEM_DBG_MEM_TM_RFEC0_RESERVED0_MASK 0xf000 6048 #define MEM_DBG_MEM_TM_RFEC0_RESERVED0_ALIGN 0 6049 #define MEM_DBG_MEM_TM_RFEC0_RESERVED0_BITS 4 6050 #define MEM_DBG_MEM_TM_RFEC0_RESERVED0_SHIFT 12 6051 6052 /* mem_dbg :: mem_tm_rfec0 :: rfec0_tm [11:00] */ 6053 #define MEM_DBG_MEM_TM_RFEC0_RFEC0_TM_MASK 0x0fff 6054 #define MEM_DBG_MEM_TM_RFEC0_RFEC0_TM_ALIGN 0 6055 #define MEM_DBG_MEM_TM_RFEC0_RFEC0_TM_BITS 12 6056 #define MEM_DBG_MEM_TM_RFEC0_RFEC0_TM_SHIFT 0 6057 6058 6059 /**************************************************************************** 6060 * mem_dbg :: mem_tm_rfec1 6061 */ 6062 /* mem_dbg :: mem_tm_rfec1 :: reserved0 [15:12] */ 6063 #define MEM_DBG_MEM_TM_RFEC1_RESERVED0_MASK 0xf000 6064 #define MEM_DBG_MEM_TM_RFEC1_RESERVED0_ALIGN 0 6065 #define MEM_DBG_MEM_TM_RFEC1_RESERVED0_BITS 4 6066 #define MEM_DBG_MEM_TM_RFEC1_RESERVED0_SHIFT 12 6067 6068 /* mem_dbg :: mem_tm_rfec1 :: rfec1_tm [11:00] */ 6069 #define MEM_DBG_MEM_TM_RFEC1_RFEC1_TM_MASK 0x0fff 6070 #define MEM_DBG_MEM_TM_RFEC1_RFEC1_TM_ALIGN 0 6071 #define MEM_DBG_MEM_TM_RFEC1_RFEC1_TM_BITS 12 6072 #define MEM_DBG_MEM_TM_RFEC1_RFEC1_TM_SHIFT 0 6073 6074 6075 /**************************************************************************** 6076 * TSCE_TSCE_USER1_Misc 6077 */ 6078 /**************************************************************************** 6079 * Misc :: xgxsStatus0 6080 */ 6081 /* Misc :: xgxsStatus0 :: status_en [15:15] */ 6082 #define MISC_XGXSSTATUS0_STATUS_EN_MASK 0x8000 6083 #define MISC_XGXSSTATUS0_STATUS_EN_ALIGN 0 6084 #define MISC_XGXSSTATUS0_STATUS_EN_BITS 1 6085 #define MISC_XGXSSTATUS0_STATUS_EN_SHIFT 15 6086 6087 /* Misc :: xgxsStatus0 :: reserved0 [14:01] */ 6088 #define MISC_XGXSSTATUS0_RESERVED0_MASK 0x7ffe 6089 #define MISC_XGXSSTATUS0_RESERVED0_ALIGN 0 6090 #define MISC_XGXSSTATUS0_RESERVED0_BITS 14 6091 #define MISC_XGXSSTATUS0_RESERVED0_SHIFT 1 6092 6093 /* Misc :: xgxsStatus0 :: skew_status [00:00] */ 6094 #define MISC_XGXSSTATUS0_SKEW_STATUS_MASK 0x0001 6095 #define MISC_XGXSSTATUS0_SKEW_STATUS_ALIGN 0 6096 #define MISC_XGXSSTATUS0_SKEW_STATUS_BITS 1 6097 #define MISC_XGXSSTATUS0_SKEW_STATUS_SHIFT 0 6098 6099 6100 /**************************************************************************** 6101 * Misc :: tx_rate_mismatch 6102 */ 6103 /* Misc :: tx_rate_mismatch :: reserved0 [15:08] */ 6104 #define MISC_TX_RATE_MISMATCH_RESERVED0_MASK 0xff00 6105 #define MISC_TX_RATE_MISMATCH_RESERVED0_ALIGN 0 6106 #define MISC_TX_RATE_MISMATCH_RESERVED0_BITS 8 6107 #define MISC_TX_RATE_MISMATCH_RESERVED0_SHIFT 8 6108 6109 /* Misc :: tx_rate_mismatch :: tx_lane_rate_mismatch_vl1 [07:04] */ 6110 #define MISC_TX_RATE_MISMATCH_TX_LANE_RATE_MISMATCH_VL1_MASK 0x00f0 6111 #define MISC_TX_RATE_MISMATCH_TX_LANE_RATE_MISMATCH_VL1_ALIGN 0 6112 #define MISC_TX_RATE_MISMATCH_TX_LANE_RATE_MISMATCH_VL1_BITS 4 6113 #define MISC_TX_RATE_MISMATCH_TX_LANE_RATE_MISMATCH_VL1_SHIFT 4 6114 6115 /* Misc :: tx_rate_mismatch :: tx_lane_rate_mismatch [03:00] */ 6116 #define MISC_TX_RATE_MISMATCH_TX_LANE_RATE_MISMATCH_MASK 0x000f 6117 #define MISC_TX_RATE_MISMATCH_TX_LANE_RATE_MISMATCH_ALIGN 0 6118 #define MISC_TX_RATE_MISMATCH_TX_LANE_RATE_MISMATCH_BITS 4 6119 #define MISC_TX_RATE_MISMATCH_TX_LANE_RATE_MISMATCH_SHIFT 0 6120 6121 6122 /**************************************************************************** 6123 * Misc :: scrambler_control 6124 */ 6125 /* Misc :: scrambler_control :: reserved0 [15:05] */ 6126 #define MISC_SCRAMBLER_CONTROL_RESERVED0_MASK 0xffe0 6127 #define MISC_SCRAMBLER_CONTROL_RESERVED0_ALIGN 0 6128 #define MISC_SCRAMBLER_CONTROL_RESERVED0_BITS 11 6129 #define MISC_SCRAMBLER_CONTROL_RESERVED0_SHIFT 5 6130 6131 /* Misc :: scrambler_control :: scrambler_en_mask [04:00] */ 6132 #define MISC_SCRAMBLER_CONTROL_SCRAMBLER_EN_MASK_MASK 0x001f 6133 #define MISC_SCRAMBLER_CONTROL_SCRAMBLER_EN_MASK_ALIGN 0 6134 #define MISC_SCRAMBLER_CONTROL_SCRAMBLER_EN_MASK_BITS 5 6135 #define MISC_SCRAMBLER_CONTROL_SCRAMBLER_EN_MASK_SHIFT 0 6136 6137 6138 /**************************************************************************** 6139 * Misc :: cl72_enable_mask 6140 */ 6141 /* Misc :: cl72_enable_mask :: cl72_en_mask [15:00] */ 6142 #define MISC_CL72_ENABLE_MASK_CL72_EN_MASK_MASK 0xffff 6143 #define MISC_CL72_ENABLE_MASK_CL72_EN_MASK_ALIGN 0 6144 #define MISC_CL72_ENABLE_MASK_CL72_EN_MASK_BITS 16 6145 #define MISC_CL72_ENABLE_MASK_CL72_EN_MASK_SHIFT 0 6146 6147 6148 /**************************************************************************** 6149 * TSCE_TSCE_USER1_CL82_Shared 6150 */ 6151 /**************************************************************************** 6152 * CL82_Shared :: cl82_rx_am_timer 6153 */ 6154 /* CL82_Shared :: cl82_rx_am_timer :: AM_timer_init_rx_val [15:00] */ 6155 #define CL82_SHARED_CL82_RX_AM_TIMER_AM_TIMER_INIT_RX_VAL_MASK 0xffff 6156 #define CL82_SHARED_CL82_RX_AM_TIMER_AM_TIMER_INIT_RX_VAL_ALIGN 0 6157 #define CL82_SHARED_CL82_RX_AM_TIMER_AM_TIMER_INIT_RX_VAL_BITS 16 6158 #define CL82_SHARED_CL82_RX_AM_TIMER_AM_TIMER_INIT_RX_VAL_SHIFT 0 6159 6160 6161 /**************************************************************************** 6162 * TSCE_TSCE_USER1_CL82_AM_regs 6163 */ 6164 /**************************************************************************** 6165 * CL82_AM_regs :: lane_0_am_byte10 6166 */ 6167 /* CL82_AM_regs :: lane_0_am_byte10 :: LANE_0_AM_1_0 [15:00] */ 6168 #define CL82_AM_REGS_LANE_0_AM_BYTE10_LANE_0_AM_1_0_MASK 0xffff 6169 #define CL82_AM_REGS_LANE_0_AM_BYTE10_LANE_0_AM_1_0_ALIGN 0 6170 #define CL82_AM_REGS_LANE_0_AM_BYTE10_LANE_0_AM_1_0_BITS 16 6171 #define CL82_AM_REGS_LANE_0_AM_BYTE10_LANE_0_AM_1_0_SHIFT 0 6172 6173 6174 /**************************************************************************** 6175 * CL82_AM_regs :: lane_1_am_byte10 6176 */ 6177 /* CL82_AM_regs :: lane_1_am_byte10 :: LANE_1_AM_1_0 [15:00] */ 6178 #define CL82_AM_REGS_LANE_1_AM_BYTE10_LANE_1_AM_1_0_MASK 0xffff 6179 #define CL82_AM_REGS_LANE_1_AM_BYTE10_LANE_1_AM_1_0_ALIGN 0 6180 #define CL82_AM_REGS_LANE_1_AM_BYTE10_LANE_1_AM_1_0_BITS 16 6181 #define CL82_AM_REGS_LANE_1_AM_BYTE10_LANE_1_AM_1_0_SHIFT 0 6182 6183 6184 /**************************************************************************** 6185 * CL82_AM_regs :: lanes_1_0_am_byte2 6186 */ 6187 /* CL82_AM_regs :: lanes_1_0_am_byte2 :: LANE_1_AM_2 [15:08] */ 6188 #define CL82_AM_REGS_LANES_1_0_AM_BYTE2_LANE_1_AM_2_MASK 0xff00 6189 #define CL82_AM_REGS_LANES_1_0_AM_BYTE2_LANE_1_AM_2_ALIGN 0 6190 #define CL82_AM_REGS_LANES_1_0_AM_BYTE2_LANE_1_AM_2_BITS 8 6191 #define CL82_AM_REGS_LANES_1_0_AM_BYTE2_LANE_1_AM_2_SHIFT 8 6192 6193 /* CL82_AM_regs :: lanes_1_0_am_byte2 :: LANE_0_AM_2 [07:00] */ 6194 #define CL82_AM_REGS_LANES_1_0_AM_BYTE2_LANE_0_AM_2_MASK 0x00ff 6195 #define CL82_AM_REGS_LANES_1_0_AM_BYTE2_LANE_0_AM_2_ALIGN 0 6196 #define CL82_AM_REGS_LANES_1_0_AM_BYTE2_LANE_0_AM_2_BITS 8 6197 #define CL82_AM_REGS_LANES_1_0_AM_BYTE2_LANE_0_AM_2_SHIFT 0 6198 6199 6200 /**************************************************************************** 6201 * TSCE_TSCE_USER1_CL82_AM_regs_tsc_12 6202 */ 6203 /**************************************************************************** 6204 * CL82_AM_regs_tsc_12 :: lane_2_am_byte10 6205 */ 6206 /* CL82_AM_regs_tsc_12 :: lane_2_am_byte10 :: LANE_2_AM_1_0 [15:00] */ 6207 #define CL82_AM_REGS_TSC_12_LANE_2_AM_BYTE10_LANE_2_AM_1_0_MASK 0xffff 6208 #define CL82_AM_REGS_TSC_12_LANE_2_AM_BYTE10_LANE_2_AM_1_0_ALIGN 0 6209 #define CL82_AM_REGS_TSC_12_LANE_2_AM_BYTE10_LANE_2_AM_1_0_BITS 16 6210 #define CL82_AM_REGS_TSC_12_LANE_2_AM_BYTE10_LANE_2_AM_1_0_SHIFT 0 6211 6212 6213 /**************************************************************************** 6214 * CL82_AM_regs_tsc_12 :: lane_3_am_byte10 6215 */ 6216 /* CL82_AM_regs_tsc_12 :: lane_3_am_byte10 :: LANE_3_AM_1_0 [15:00] */ 6217 #define CL82_AM_REGS_TSC_12_LANE_3_AM_BYTE10_LANE_3_AM_1_0_MASK 0xffff 6218 #define CL82_AM_REGS_TSC_12_LANE_3_AM_BYTE10_LANE_3_AM_1_0_ALIGN 0 6219 #define CL82_AM_REGS_TSC_12_LANE_3_AM_BYTE10_LANE_3_AM_1_0_BITS 16 6220 #define CL82_AM_REGS_TSC_12_LANE_3_AM_BYTE10_LANE_3_AM_1_0_SHIFT 0 6221 6222 6223 /**************************************************************************** 6224 * CL82_AM_regs_tsc_12 :: lanes_3_2_am_byte2 6225 */ 6226 /* CL82_AM_regs_tsc_12 :: lanes_3_2_am_byte2 :: LANE_3_AM_2 [15:08] */ 6227 #define CL82_AM_REGS_TSC_12_LANES_3_2_AM_BYTE2_LANE_3_AM_2_MASK 0xff00 6228 #define CL82_AM_REGS_TSC_12_LANES_3_2_AM_BYTE2_LANE_3_AM_2_ALIGN 0 6229 #define CL82_AM_REGS_TSC_12_LANES_3_2_AM_BYTE2_LANE_3_AM_2_BITS 8 6230 #define CL82_AM_REGS_TSC_12_LANES_3_2_AM_BYTE2_LANE_3_AM_2_SHIFT 8 6231 6232 /* CL82_AM_regs_tsc_12 :: lanes_3_2_am_byte2 :: LANE_2_AM_2 [07:00] */ 6233 #define CL82_AM_REGS_TSC_12_LANES_3_2_AM_BYTE2_LANE_2_AM_2_MASK 0x00ff 6234 #define CL82_AM_REGS_TSC_12_LANES_3_2_AM_BYTE2_LANE_2_AM_2_ALIGN 0 6235 #define CL82_AM_REGS_TSC_12_LANES_3_2_AM_BYTE2_LANE_2_AM_2_BITS 8 6236 #define CL82_AM_REGS_TSC_12_LANES_3_2_AM_BYTE2_LANE_2_AM_2_SHIFT 0 6237 6238 6239 /**************************************************************************** 6240 * TSCE_TSCE_USER1_RX_X1_Control0 6241 */ 6242 /**************************************************************************** 6243 * RX_X1_Control0 :: decode_control_0 6244 */ 6245 /* RX_X1_Control0 :: decode_control_0 :: reserved0 [15:12] */ 6246 #define RX_X1_CONTROL0_DECODE_CONTROL_0_RESERVED0_MASK 0xf000 6247 #define RX_X1_CONTROL0_DECODE_CONTROL_0_RESERVED0_ALIGN 0 6248 #define RX_X1_CONTROL0_DECODE_CONTROL_0_RESERVED0_BITS 4 6249 #define RX_X1_CONTROL0_DECODE_CONTROL_0_RESERVED0_SHIFT 12 6250 6251 /* RX_X1_Control0 :: decode_control_0 :: scwCount [11:08] */ 6252 #define RX_X1_CONTROL0_DECODE_CONTROL_0_SCWCOUNT_MASK 0x0f00 6253 #define RX_X1_CONTROL0_DECODE_CONTROL_0_SCWCOUNT_ALIGN 0 6254 #define RX_X1_CONTROL0_DECODE_CONTROL_0_SCWCOUNT_BITS 4 6255 #define RX_X1_CONTROL0_DECODE_CONTROL_0_SCWCOUNT_SHIFT 8 6256 6257 /* RX_X1_Control0 :: decode_control_0 :: gcwCount [07:04] */ 6258 #define RX_X1_CONTROL0_DECODE_CONTROL_0_GCWCOUNT_MASK 0x00f0 6259 #define RX_X1_CONTROL0_DECODE_CONTROL_0_GCWCOUNT_ALIGN 0 6260 #define RX_X1_CONTROL0_DECODE_CONTROL_0_GCWCOUNT_BITS 4 6261 #define RX_X1_CONTROL0_DECODE_CONTROL_0_GCWCOUNT_SHIFT 4 6262 6263 /* RX_X1_Control0 :: decode_control_0 :: hystCount [03:00] */ 6264 #define RX_X1_CONTROL0_DECODE_CONTROL_0_HYSTCOUNT_MASK 0x000f 6265 #define RX_X1_CONTROL0_DECODE_CONTROL_0_HYSTCOUNT_ALIGN 0 6266 #define RX_X1_CONTROL0_DECODE_CONTROL_0_HYSTCOUNT_BITS 4 6267 #define RX_X1_CONTROL0_DECODE_CONTROL_0_HYSTCOUNT_SHIFT 0 6268 6269 6270 /**************************************************************************** 6271 * RX_X1_Control0 :: decode_control_1 6272 */ 6273 /* RX_X1_Control0 :: decode_control_1 :: SET_BER_WINDOW_512 [15:15] */ 6274 #define RX_X1_CONTROL0_DECODE_CONTROL_1_SET_BER_WINDOW_512_MASK 0x8000 6275 #define RX_X1_CONTROL0_DECODE_CONTROL_1_SET_BER_WINDOW_512_ALIGN 0 6276 #define RX_X1_CONTROL0_DECODE_CONTROL_1_SET_BER_WINDOW_512_BITS 1 6277 #define RX_X1_CONTROL0_DECODE_CONTROL_1_SET_BER_WINDOW_512_SHIFT 15 6278 6279 /* RX_X1_Control0 :: decode_control_1 :: CL82_BER_LIMIT [14:08] */ 6280 #define RX_X1_CONTROL0_DECODE_CONTROL_1_CL82_BER_LIMIT_MASK 0x7f00 6281 #define RX_X1_CONTROL0_DECODE_CONTROL_1_CL82_BER_LIMIT_ALIGN 0 6282 #define RX_X1_CONTROL0_DECODE_CONTROL_1_CL82_BER_LIMIT_BITS 7 6283 #define RX_X1_CONTROL0_DECODE_CONTROL_1_CL82_BER_LIMIT_SHIFT 8 6284 6285 /* RX_X1_Control0 :: decode_control_1 :: CL49_BER_LIMIT [07:02] */ 6286 #define RX_X1_CONTROL0_DECODE_CONTROL_1_CL49_BER_LIMIT_MASK 0x00fc 6287 #define RX_X1_CONTROL0_DECODE_CONTROL_1_CL49_BER_LIMIT_ALIGN 0 6288 #define RX_X1_CONTROL0_DECODE_CONTROL_1_CL49_BER_LIMIT_BITS 6 6289 #define RX_X1_CONTROL0_DECODE_CONTROL_1_CL49_BER_LIMIT_SHIFT 2 6290 6291 /* RX_X1_Control0 :: decode_control_1 :: reserved0 [01:00] */ 6292 #define RX_X1_CONTROL0_DECODE_CONTROL_1_RESERVED0_MASK 0x0003 6293 #define RX_X1_CONTROL0_DECODE_CONTROL_1_RESERVED0_ALIGN 0 6294 #define RX_X1_CONTROL0_DECODE_CONTROL_1_RESERVED0_BITS 2 6295 #define RX_X1_CONTROL0_DECODE_CONTROL_1_RESERVED0_SHIFT 0 6296 6297 6298 /**************************************************************************** 6299 * RX_X1_Control0 :: deskew_windows 6300 */ 6301 /* RX_X1_Control0 :: deskew_windows :: cl82_dswin_100g [15:12] */ 6302 #define RX_X1_CONTROL0_DESKEW_WINDOWS_CL82_DSWIN_100G_MASK 0xf000 6303 #define RX_X1_CONTROL0_DESKEW_WINDOWS_CL82_DSWIN_100G_ALIGN 0 6304 #define RX_X1_CONTROL0_DESKEW_WINDOWS_CL82_DSWIN_100G_BITS 4 6305 #define RX_X1_CONTROL0_DESKEW_WINDOWS_CL82_DSWIN_100G_SHIFT 12 6306 6307 /* RX_X1_Control0 :: deskew_windows :: cl82_dswin [11:07] */ 6308 #define RX_X1_CONTROL0_DESKEW_WINDOWS_CL82_DSWIN_MASK 0x0f80 6309 #define RX_X1_CONTROL0_DESKEW_WINDOWS_CL82_DSWIN_ALIGN 0 6310 #define RX_X1_CONTROL0_DESKEW_WINDOWS_CL82_DSWIN_BITS 5 6311 #define RX_X1_CONTROL0_DESKEW_WINDOWS_CL82_DSWIN_SHIFT 7 6312 6313 /* RX_X1_Control0 :: deskew_windows :: cl48_dswin64b66b [06:04] */ 6314 #define RX_X1_CONTROL0_DESKEW_WINDOWS_CL48_DSWIN64B66B_MASK 0x0070 6315 #define RX_X1_CONTROL0_DESKEW_WINDOWS_CL48_DSWIN64B66B_ALIGN 0 6316 #define RX_X1_CONTROL0_DESKEW_WINDOWS_CL48_DSWIN64B66B_BITS 3 6317 #define RX_X1_CONTROL0_DESKEW_WINDOWS_CL48_DSWIN64B66B_SHIFT 4 6318 6319 /* RX_X1_Control0 :: deskew_windows :: cl48_dswin8b10b [03:00] */ 6320 #define RX_X1_CONTROL0_DESKEW_WINDOWS_CL48_DSWIN8B10B_MASK 0x000f 6321 #define RX_X1_CONTROL0_DESKEW_WINDOWS_CL48_DSWIN8B10B_ALIGN 0 6322 #define RX_X1_CONTROL0_DESKEW_WINDOWS_CL48_DSWIN8B10B_BITS 4 6323 #define RX_X1_CONTROL0_DESKEW_WINDOWS_CL48_DSWIN8B10B_SHIFT 0 6324 6325 6326 /**************************************************************************** 6327 * TSCE_TSCE_USER1_RX_X1_Control1 6328 */ 6329 /**************************************************************************** 6330 * RX_X1_Control1 :: shcnt_cl49 6331 */ 6332 /* RX_X1_Control1 :: shcnt_cl49 :: cl49_valid_sh_cnt [15:08] */ 6333 #define RX_X1_CONTROL1_SHCNT_CL49_CL49_VALID_SH_CNT_MASK 0xff00 6334 #define RX_X1_CONTROL1_SHCNT_CL49_CL49_VALID_SH_CNT_ALIGN 0 6335 #define RX_X1_CONTROL1_SHCNT_CL49_CL49_VALID_SH_CNT_BITS 8 6336 #define RX_X1_CONTROL1_SHCNT_CL49_CL49_VALID_SH_CNT_SHIFT 8 6337 6338 /* RX_X1_Control1 :: shcnt_cl49 :: cl49_invalid_sh_cnt [07:00] */ 6339 #define RX_X1_CONTROL1_SHCNT_CL49_CL49_INVALID_SH_CNT_MASK 0x00ff 6340 #define RX_X1_CONTROL1_SHCNT_CL49_CL49_INVALID_SH_CNT_ALIGN 0 6341 #define RX_X1_CONTROL1_SHCNT_CL49_CL49_INVALID_SH_CNT_BITS 8 6342 #define RX_X1_CONTROL1_SHCNT_CL49_CL49_INVALID_SH_CNT_SHIFT 0 6343 6344 6345 /**************************************************************************** 6346 * RX_X1_Control1 :: valid_shcnt_cl82 6347 */ 6348 /* RX_X1_Control1 :: valid_shcnt_cl82 :: reserved0 [15:12] */ 6349 #define RX_X1_CONTROL1_VALID_SHCNT_CL82_RESERVED0_MASK 0xf000 6350 #define RX_X1_CONTROL1_VALID_SHCNT_CL82_RESERVED0_ALIGN 0 6351 #define RX_X1_CONTROL1_VALID_SHCNT_CL82_RESERVED0_BITS 4 6352 #define RX_X1_CONTROL1_VALID_SHCNT_CL82_RESERVED0_SHIFT 12 6353 6354 /* RX_X1_Control1 :: valid_shcnt_cl82 :: cl82_valid_sh_cnt [11:00] */ 6355 #define RX_X1_CONTROL1_VALID_SHCNT_CL82_CL82_VALID_SH_CNT_MASK 0x0fff 6356 #define RX_X1_CONTROL1_VALID_SHCNT_CL82_CL82_VALID_SH_CNT_ALIGN 0 6357 #define RX_X1_CONTROL1_VALID_SHCNT_CL82_CL82_VALID_SH_CNT_BITS 12 6358 #define RX_X1_CONTROL1_VALID_SHCNT_CL82_CL82_VALID_SH_CNT_SHIFT 0 6359 6360 6361 /**************************************************************************** 6362 * RX_X1_Control1 :: invalid_shcnt_cl82 6363 */ 6364 /* RX_X1_Control1 :: invalid_shcnt_cl82 :: reserved0 [15:12] */ 6365 #define RX_X1_CONTROL1_INVALID_SHCNT_CL82_RESERVED0_MASK 0xf000 6366 #define RX_X1_CONTROL1_INVALID_SHCNT_CL82_RESERVED0_ALIGN 0 6367 #define RX_X1_CONTROL1_INVALID_SHCNT_CL82_RESERVED0_BITS 4 6368 #define RX_X1_CONTROL1_INVALID_SHCNT_CL82_RESERVED0_SHIFT 12 6369 6370 /* RX_X1_Control1 :: invalid_shcnt_cl82 :: cl82_invalid_sh_cnt [11:00] */ 6371 #define RX_X1_CONTROL1_INVALID_SHCNT_CL82_CL82_INVALID_SH_CNT_MASK 0x0fff 6372 #define RX_X1_CONTROL1_INVALID_SHCNT_CL82_CL82_INVALID_SH_CNT_ALIGN 0 6373 #define RX_X1_CONTROL1_INVALID_SHCNT_CL82_CL82_INVALID_SH_CNT_BITS 12 6374 #define RX_X1_CONTROL1_INVALID_SHCNT_CL82_CL82_INVALID_SH_CNT_SHIFT 0 6375 6376 6377 /**************************************************************************** 6378 * RX_X1_Control1 :: scw0 6379 */ 6380 /* RX_X1_Control1 :: scw0 :: scw0 [15:00] */ 6381 #define RX_X1_CONTROL1_SCW0_SCW0_MASK 0xffff 6382 #define RX_X1_CONTROL1_SCW0_SCW0_ALIGN 0 6383 #define RX_X1_CONTROL1_SCW0_SCW0_BITS 16 6384 #define RX_X1_CONTROL1_SCW0_SCW0_SHIFT 0 6385 6386 6387 /**************************************************************************** 6388 * RX_X1_Control1 :: scw1 6389 */ 6390 /* RX_X1_Control1 :: scw1 :: scw1 [15:00] */ 6391 #define RX_X1_CONTROL1_SCW1_SCW1_MASK 0xffff 6392 #define RX_X1_CONTROL1_SCW1_SCW1_ALIGN 0 6393 #define RX_X1_CONTROL1_SCW1_SCW1_BITS 16 6394 #define RX_X1_CONTROL1_SCW1_SCW1_SHIFT 0 6395 6396 6397 /**************************************************************************** 6398 * RX_X1_Control1 :: scw2 6399 */ 6400 /* RX_X1_Control1 :: scw2 :: scw2 [15:00] */ 6401 #define RX_X1_CONTROL1_SCW2_SCW2_MASK 0xffff 6402 #define RX_X1_CONTROL1_SCW2_SCW2_ALIGN 0 6403 #define RX_X1_CONTROL1_SCW2_SCW2_BITS 16 6404 #define RX_X1_CONTROL1_SCW2_SCW2_SHIFT 0 6405 6406 6407 /**************************************************************************** 6408 * RX_X1_Control1 :: scw3 6409 */ 6410 /* RX_X1_Control1 :: scw3 :: scw3 [15:00] */ 6411 #define RX_X1_CONTROL1_SCW3_SCW3_MASK 0xffff 6412 #define RX_X1_CONTROL1_SCW3_SCW3_ALIGN 0 6413 #define RX_X1_CONTROL1_SCW3_SCW3_BITS 16 6414 #define RX_X1_CONTROL1_SCW3_SCW3_SHIFT 0 6415 6416 6417 /**************************************************************************** 6418 * RX_X1_Control1 :: scw4 6419 */ 6420 /* RX_X1_Control1 :: scw4 :: reserved0 [15:02] */ 6421 #define RX_X1_CONTROL1_SCW4_RESERVED0_MASK 0xfffc 6422 #define RX_X1_CONTROL1_SCW4_RESERVED0_ALIGN 0 6423 #define RX_X1_CONTROL1_SCW4_RESERVED0_BITS 14 6424 #define RX_X1_CONTROL1_SCW4_RESERVED0_SHIFT 2 6425 6426 /* RX_X1_Control1 :: scw4 :: scw4 [01:00] */ 6427 #define RX_X1_CONTROL1_SCW4_SCW4_MASK 0x0003 6428 #define RX_X1_CONTROL1_SCW4_SCW4_ALIGN 0 6429 #define RX_X1_CONTROL1_SCW4_SCW4_BITS 2 6430 #define RX_X1_CONTROL1_SCW4_SCW4_SHIFT 0 6431 6432 6433 /**************************************************************************** 6434 * RX_X1_Control1 :: scw0_mask 6435 */ 6436 /* RX_X1_Control1 :: scw0_mask :: scw0_mask [15:00] */ 6437 #define RX_X1_CONTROL1_SCW0_MASK_SCW0_MASK_MASK 0xffff 6438 #define RX_X1_CONTROL1_SCW0_MASK_SCW0_MASK_ALIGN 0 6439 #define RX_X1_CONTROL1_SCW0_MASK_SCW0_MASK_BITS 16 6440 #define RX_X1_CONTROL1_SCW0_MASK_SCW0_MASK_SHIFT 0 6441 6442 6443 /**************************************************************************** 6444 * RX_X1_Control1 :: scw1_mask 6445 */ 6446 /* RX_X1_Control1 :: scw1_mask :: scw1_mask [15:00] */ 6447 #define RX_X1_CONTROL1_SCW1_MASK_SCW1_MASK_MASK 0xffff 6448 #define RX_X1_CONTROL1_SCW1_MASK_SCW1_MASK_ALIGN 0 6449 #define RX_X1_CONTROL1_SCW1_MASK_SCW1_MASK_BITS 16 6450 #define RX_X1_CONTROL1_SCW1_MASK_SCW1_MASK_SHIFT 0 6451 6452 6453 /**************************************************************************** 6454 * RX_X1_Control1 :: scw2_mask 6455 */ 6456 /* RX_X1_Control1 :: scw2_mask :: scw2_mask [15:00] */ 6457 #define RX_X1_CONTROL1_SCW2_MASK_SCW2_MASK_MASK 0xffff 6458 #define RX_X1_CONTROL1_SCW2_MASK_SCW2_MASK_ALIGN 0 6459 #define RX_X1_CONTROL1_SCW2_MASK_SCW2_MASK_BITS 16 6460 #define RX_X1_CONTROL1_SCW2_MASK_SCW2_MASK_SHIFT 0 6461 6462 6463 /**************************************************************************** 6464 * RX_X1_Control1 :: scw3_mask 6465 */ 6466 /* RX_X1_Control1 :: scw3_mask :: scw3_mask [15:00] */ 6467 #define RX_X1_CONTROL1_SCW3_MASK_SCW3_MASK_MASK 0xffff 6468 #define RX_X1_CONTROL1_SCW3_MASK_SCW3_MASK_ALIGN 0 6469 #define RX_X1_CONTROL1_SCW3_MASK_SCW3_MASK_BITS 16 6470 #define RX_X1_CONTROL1_SCW3_MASK_SCW3_MASK_SHIFT 0 6471 6472 6473 /**************************************************************************** 6474 * RX_X1_Control1 :: scw4_mask 6475 */ 6476 /* RX_X1_Control1 :: scw4_mask :: reserved0 [15:02] */ 6477 #define RX_X1_CONTROL1_SCW4_MASK_RESERVED0_MASK 0xfffc 6478 #define RX_X1_CONTROL1_SCW4_MASK_RESERVED0_ALIGN 0 6479 #define RX_X1_CONTROL1_SCW4_MASK_RESERVED0_BITS 14 6480 #define RX_X1_CONTROL1_SCW4_MASK_RESERVED0_SHIFT 2 6481 6482 /* RX_X1_Control1 :: scw4_mask :: scw4_mask [01:00] */ 6483 #define RX_X1_CONTROL1_SCW4_MASK_SCW4_MASK_MASK 0x0003 6484 #define RX_X1_CONTROL1_SCW4_MASK_SCW4_MASK_ALIGN 0 6485 #define RX_X1_CONTROL1_SCW4_MASK_SCW4_MASK_BITS 2 6486 #define RX_X1_CONTROL1_SCW4_MASK_SCW4_MASK_SHIFT 0 6487 6488 6489 /**************************************************************************** 6490 * TSCE_TSCE_USER1_AN_X1_CONTROL 6491 */ 6492 /**************************************************************************** 6493 * AN_X1_CONTROL :: oui_upper 6494 */ 6495 /* AN_X1_CONTROL :: oui_upper :: reserved0 [15:08] */ 6496 #define AN_X1_CONTROL_OUI_UPPER_RESERVED0_MASK 0xff00 6497 #define AN_X1_CONTROL_OUI_UPPER_RESERVED0_ALIGN 0 6498 #define AN_X1_CONTROL_OUI_UPPER_RESERVED0_BITS 8 6499 #define AN_X1_CONTROL_OUI_UPPER_RESERVED0_SHIFT 8 6500 6501 /* AN_X1_CONTROL :: oui_upper :: oui_upper_data [07:00] */ 6502 #define AN_X1_CONTROL_OUI_UPPER_OUI_UPPER_DATA_MASK 0x00ff 6503 #define AN_X1_CONTROL_OUI_UPPER_OUI_UPPER_DATA_ALIGN 0 6504 #define AN_X1_CONTROL_OUI_UPPER_OUI_UPPER_DATA_BITS 8 6505 #define AN_X1_CONTROL_OUI_UPPER_OUI_UPPER_DATA_SHIFT 0 6506 6507 6508 /**************************************************************************** 6509 * AN_X1_CONTROL :: oui_lower 6510 */ 6511 /* AN_X1_CONTROL :: oui_lower :: oui_lower_data [15:00] */ 6512 #define AN_X1_CONTROL_OUI_LOWER_OUI_LOWER_DATA_MASK 0xffff 6513 #define AN_X1_CONTROL_OUI_LOWER_OUI_LOWER_DATA_ALIGN 0 6514 #define AN_X1_CONTROL_OUI_LOWER_OUI_LOWER_DATA_BITS 16 6515 #define AN_X1_CONTROL_OUI_LOWER_OUI_LOWER_DATA_SHIFT 0 6516 6517 6518 /**************************************************************************** 6519 * AN_X1_CONTROL :: bam_speed_pri_5_0 6520 */ 6521 /* AN_X1_CONTROL :: bam_speed_pri_5_0 :: reserved0 [15:12] */ 6522 #define AN_X1_CONTROL_BAM_SPEED_PRI_5_0_RESERVED0_MASK 0xf000 6523 #define AN_X1_CONTROL_BAM_SPEED_PRI_5_0_RESERVED0_ALIGN 0 6524 #define AN_X1_CONTROL_BAM_SPEED_PRI_5_0_RESERVED0_BITS 4 6525 #define AN_X1_CONTROL_BAM_SPEED_PRI_5_0_RESERVED0_SHIFT 12 6526 6527 /* AN_X1_CONTROL :: bam_speed_pri_5_0 :: an_priority_1GKX [11:10] */ 6528 #define AN_X1_CONTROL_BAM_SPEED_PRI_5_0_AN_PRIORITY_1GKX_MASK 0x0c00 6529 #define AN_X1_CONTROL_BAM_SPEED_PRI_5_0_AN_PRIORITY_1GKX_ALIGN 0 6530 #define AN_X1_CONTROL_BAM_SPEED_PRI_5_0_AN_PRIORITY_1GKX_BITS 2 6531 #define AN_X1_CONTROL_BAM_SPEED_PRI_5_0_AN_PRIORITY_1GKX_SHIFT 10 6532 6533 /* AN_X1_CONTROL :: bam_speed_pri_5_0 :: an_priority_2p5GX1 [09:08] */ 6534 #define AN_X1_CONTROL_BAM_SPEED_PRI_5_0_AN_PRIORITY_2P5GX1_MASK 0x0300 6535 #define AN_X1_CONTROL_BAM_SPEED_PRI_5_0_AN_PRIORITY_2P5GX1_ALIGN 0 6536 #define AN_X1_CONTROL_BAM_SPEED_PRI_5_0_AN_PRIORITY_2P5GX1_BITS 2 6537 #define AN_X1_CONTROL_BAM_SPEED_PRI_5_0_AN_PRIORITY_2P5GX1_SHIFT 8 6538 6539 /* AN_X1_CONTROL :: bam_speed_pri_5_0 :: an_priority_5GX4 [07:06] */ 6540 #define AN_X1_CONTROL_BAM_SPEED_PRI_5_0_AN_PRIORITY_5GX4_MASK 0x00c0 6541 #define AN_X1_CONTROL_BAM_SPEED_PRI_5_0_AN_PRIORITY_5GX4_ALIGN 0 6542 #define AN_X1_CONTROL_BAM_SPEED_PRI_5_0_AN_PRIORITY_5GX4_BITS 2 6543 #define AN_X1_CONTROL_BAM_SPEED_PRI_5_0_AN_PRIORITY_5GX4_SHIFT 6 6544 6545 /* AN_X1_CONTROL :: bam_speed_pri_5_0 :: an_priority_10M [05:04] */ 6546 #define AN_X1_CONTROL_BAM_SPEED_PRI_5_0_AN_PRIORITY_10M_MASK 0x0030 6547 #define AN_X1_CONTROL_BAM_SPEED_PRI_5_0_AN_PRIORITY_10M_ALIGN 0 6548 #define AN_X1_CONTROL_BAM_SPEED_PRI_5_0_AN_PRIORITY_10M_BITS 2 6549 #define AN_X1_CONTROL_BAM_SPEED_PRI_5_0_AN_PRIORITY_10M_SHIFT 4 6550 6551 /* AN_X1_CONTROL :: bam_speed_pri_5_0 :: an_priority_100M [03:02] */ 6552 #define AN_X1_CONTROL_BAM_SPEED_PRI_5_0_AN_PRIORITY_100M_MASK 0x000c 6553 #define AN_X1_CONTROL_BAM_SPEED_PRI_5_0_AN_PRIORITY_100M_ALIGN 0 6554 #define AN_X1_CONTROL_BAM_SPEED_PRI_5_0_AN_PRIORITY_100M_BITS 2 6555 #define AN_X1_CONTROL_BAM_SPEED_PRI_5_0_AN_PRIORITY_100M_SHIFT 2 6556 6557 /* AN_X1_CONTROL :: bam_speed_pri_5_0 :: an_priority_1000M [01:00] */ 6558 #define AN_X1_CONTROL_BAM_SPEED_PRI_5_0_AN_PRIORITY_1000M_MASK 0x0003 6559 #define AN_X1_CONTROL_BAM_SPEED_PRI_5_0_AN_PRIORITY_1000M_ALIGN 0 6560 #define AN_X1_CONTROL_BAM_SPEED_PRI_5_0_AN_PRIORITY_1000M_BITS 2 6561 #define AN_X1_CONTROL_BAM_SPEED_PRI_5_0_AN_PRIORITY_1000M_SHIFT 0 6562 6563 6564 /**************************************************************************** 6565 * AN_X1_CONTROL :: bam_speed_pri_11_6 6566 */ 6567 /* AN_X1_CONTROL :: bam_speed_pri_11_6 :: reserved0 [15:12] */ 6568 #define AN_X1_CONTROL_BAM_SPEED_PRI_11_6_RESERVED0_MASK 0xf000 6569 #define AN_X1_CONTROL_BAM_SPEED_PRI_11_6_RESERVED0_ALIGN 0 6570 #define AN_X1_CONTROL_BAM_SPEED_PRI_11_6_RESERVED0_BITS 4 6571 #define AN_X1_CONTROL_BAM_SPEED_PRI_11_6_RESERVED0_SHIFT 12 6572 6573 /* AN_X1_CONTROL :: bam_speed_pri_11_6 :: an_priority_10GKR [11:10] */ 6574 #define AN_X1_CONTROL_BAM_SPEED_PRI_11_6_AN_PRIORITY_10GKR_MASK 0x0c00 6575 #define AN_X1_CONTROL_BAM_SPEED_PRI_11_6_AN_PRIORITY_10GKR_ALIGN 0 6576 #define AN_X1_CONTROL_BAM_SPEED_PRI_11_6_AN_PRIORITY_10GKR_BITS 2 6577 #define AN_X1_CONTROL_BAM_SPEED_PRI_11_6_AN_PRIORITY_10GKR_SHIFT 10 6578 6579 /* AN_X1_CONTROL :: bam_speed_pri_11_6 :: an_priority_10GKX4 [09:08] */ 6580 #define AN_X1_CONTROL_BAM_SPEED_PRI_11_6_AN_PRIORITY_10GKX4_MASK 0x0300 6581 #define AN_X1_CONTROL_BAM_SPEED_PRI_11_6_AN_PRIORITY_10GKX4_ALIGN 0 6582 #define AN_X1_CONTROL_BAM_SPEED_PRI_11_6_AN_PRIORITY_10GKX4_BITS 2 6583 #define AN_X1_CONTROL_BAM_SPEED_PRI_11_6_AN_PRIORITY_10GKX4_SHIFT 8 6584 6585 /* AN_X1_CONTROL :: bam_speed_pri_11_6 :: an_priority_10GX4 [07:06] */ 6586 #define AN_X1_CONTROL_BAM_SPEED_PRI_11_6_AN_PRIORITY_10GX4_MASK 0x00c0 6587 #define AN_X1_CONTROL_BAM_SPEED_PRI_11_6_AN_PRIORITY_10GX4_ALIGN 0 6588 #define AN_X1_CONTROL_BAM_SPEED_PRI_11_6_AN_PRIORITY_10GX4_BITS 2 6589 #define AN_X1_CONTROL_BAM_SPEED_PRI_11_6_AN_PRIORITY_10GX4_SHIFT 6 6590 6591 /* AN_X1_CONTROL :: bam_speed_pri_11_6 :: an_priority_6GX4 [05:04] */ 6592 #define AN_X1_CONTROL_BAM_SPEED_PRI_11_6_AN_PRIORITY_6GX4_MASK 0x0030 6593 #define AN_X1_CONTROL_BAM_SPEED_PRI_11_6_AN_PRIORITY_6GX4_ALIGN 0 6594 #define AN_X1_CONTROL_BAM_SPEED_PRI_11_6_AN_PRIORITY_6GX4_BITS 2 6595 #define AN_X1_CONTROL_BAM_SPEED_PRI_11_6_AN_PRIORITY_6GX4_SHIFT 4 6596 6597 /* AN_X1_CONTROL :: bam_speed_pri_11_6 :: an_priority_10GCX1 [03:02] */ 6598 #define AN_X1_CONTROL_BAM_SPEED_PRI_11_6_AN_PRIORITY_10GCX1_MASK 0x000c 6599 #define AN_X1_CONTROL_BAM_SPEED_PRI_11_6_AN_PRIORITY_10GCX1_ALIGN 0 6600 #define AN_X1_CONTROL_BAM_SPEED_PRI_11_6_AN_PRIORITY_10GCX1_BITS 2 6601 #define AN_X1_CONTROL_BAM_SPEED_PRI_11_6_AN_PRIORITY_10GCX1_SHIFT 2 6602 6603 /* AN_X1_CONTROL :: bam_speed_pri_11_6 :: an_priority_10GCX4 [01:00] */ 6604 #define AN_X1_CONTROL_BAM_SPEED_PRI_11_6_AN_PRIORITY_10GCX4_MASK 0x0003 6605 #define AN_X1_CONTROL_BAM_SPEED_PRI_11_6_AN_PRIORITY_10GCX4_ALIGN 0 6606 #define AN_X1_CONTROL_BAM_SPEED_PRI_11_6_AN_PRIORITY_10GCX4_BITS 2 6607 #define AN_X1_CONTROL_BAM_SPEED_PRI_11_6_AN_PRIORITY_10GCX4_SHIFT 0 6608 6609 6610 /**************************************************************************** 6611 * AN_X1_CONTROL :: bam_speed_pri_17_12 6612 */ 6613 /* AN_X1_CONTROL :: bam_speed_pri_17_12 :: reserved0 [15:12] */ 6614 #define AN_X1_CONTROL_BAM_SPEED_PRI_17_12_RESERVED0_MASK 0xf000 6615 #define AN_X1_CONTROL_BAM_SPEED_PRI_17_12_RESERVED0_ALIGN 0 6616 #define AN_X1_CONTROL_BAM_SPEED_PRI_17_12_RESERVED0_BITS 4 6617 #define AN_X1_CONTROL_BAM_SPEED_PRI_17_12_RESERVED0_SHIFT 12 6618 6619 /* AN_X1_CONTROL :: bam_speed_pri_17_12 :: an_priority_12GX4 [11:10] */ 6620 #define AN_X1_CONTROL_BAM_SPEED_PRI_17_12_AN_PRIORITY_12GX4_MASK 0x0c00 6621 #define AN_X1_CONTROL_BAM_SPEED_PRI_17_12_AN_PRIORITY_12GX4_ALIGN 0 6622 #define AN_X1_CONTROL_BAM_SPEED_PRI_17_12_AN_PRIORITY_12GX4_BITS 2 6623 #define AN_X1_CONTROL_BAM_SPEED_PRI_17_12_AN_PRIORITY_12GX4_SHIFT 10 6624 6625 /* AN_X1_CONTROL :: bam_speed_pri_17_12 :: an_priority_12p5GX4 [09:08] */ 6626 #define AN_X1_CONTROL_BAM_SPEED_PRI_17_12_AN_PRIORITY_12P5GX4_MASK 0x0300 6627 #define AN_X1_CONTROL_BAM_SPEED_PRI_17_12_AN_PRIORITY_12P5GX4_ALIGN 0 6628 #define AN_X1_CONTROL_BAM_SPEED_PRI_17_12_AN_PRIORITY_12P5GX4_BITS 2 6629 #define AN_X1_CONTROL_BAM_SPEED_PRI_17_12_AN_PRIORITY_12P5GX4_SHIFT 8 6630 6631 /* AN_X1_CONTROL :: bam_speed_pri_17_12 :: an_priority_12p7GX2 [07:06] */ 6632 #define AN_X1_CONTROL_BAM_SPEED_PRI_17_12_AN_PRIORITY_12P7GX2_MASK 0x00c0 6633 #define AN_X1_CONTROL_BAM_SPEED_PRI_17_12_AN_PRIORITY_12P7GX2_ALIGN 0 6634 #define AN_X1_CONTROL_BAM_SPEED_PRI_17_12_AN_PRIORITY_12P7GX2_BITS 2 6635 #define AN_X1_CONTROL_BAM_SPEED_PRI_17_12_AN_PRIORITY_12P7GX2_SHIFT 6 6636 6637 /* AN_X1_CONTROL :: bam_speed_pri_17_12 :: an_priority_10GCX2 [05:04] */ 6638 #define AN_X1_CONTROL_BAM_SPEED_PRI_17_12_AN_PRIORITY_10GCX2_MASK 0x0030 6639 #define AN_X1_CONTROL_BAM_SPEED_PRI_17_12_AN_PRIORITY_10GCX2_ALIGN 0 6640 #define AN_X1_CONTROL_BAM_SPEED_PRI_17_12_AN_PRIORITY_10GCX2_BITS 2 6641 #define AN_X1_CONTROL_BAM_SPEED_PRI_17_12_AN_PRIORITY_10GCX2_SHIFT 4 6642 6643 /* AN_X1_CONTROL :: bam_speed_pri_17_12 :: an_priority_10GX2 [03:02] */ 6644 #define AN_X1_CONTROL_BAM_SPEED_PRI_17_12_AN_PRIORITY_10GX2_MASK 0x000c 6645 #define AN_X1_CONTROL_BAM_SPEED_PRI_17_12_AN_PRIORITY_10GX2_ALIGN 0 6646 #define AN_X1_CONTROL_BAM_SPEED_PRI_17_12_AN_PRIORITY_10GX2_BITS 2 6647 #define AN_X1_CONTROL_BAM_SPEED_PRI_17_12_AN_PRIORITY_10GX2_SHIFT 2 6648 6649 /* AN_X1_CONTROL :: bam_speed_pri_17_12 :: an_priority_10p5GX2 [01:00] */ 6650 #define AN_X1_CONTROL_BAM_SPEED_PRI_17_12_AN_PRIORITY_10P5GX2_MASK 0x0003 6651 #define AN_X1_CONTROL_BAM_SPEED_PRI_17_12_AN_PRIORITY_10P5GX2_ALIGN 0 6652 #define AN_X1_CONTROL_BAM_SPEED_PRI_17_12_AN_PRIORITY_10P5GX2_BITS 2 6653 #define AN_X1_CONTROL_BAM_SPEED_PRI_17_12_AN_PRIORITY_10P5GX2_SHIFT 0 6654 6655 6656 /**************************************************************************** 6657 * AN_X1_CONTROL :: bam_speed_pri_23_18 6658 */ 6659 /* AN_X1_CONTROL :: bam_speed_pri_23_18 :: reserved0 [15:12] */ 6660 #define AN_X1_CONTROL_BAM_SPEED_PRI_23_18_RESERVED0_MASK 0xf000 6661 #define AN_X1_CONTROL_BAM_SPEED_PRI_23_18_RESERVED0_ALIGN 0 6662 #define AN_X1_CONTROL_BAM_SPEED_PRI_23_18_RESERVED0_BITS 4 6663 #define AN_X1_CONTROL_BAM_SPEED_PRI_23_18_RESERVED0_SHIFT 12 6664 6665 /* AN_X1_CONTROL :: bam_speed_pri_23_18 :: an_priority_40GCR4 [11:10] */ 6666 #define AN_X1_CONTROL_BAM_SPEED_PRI_23_18_AN_PRIORITY_40GCR4_MASK 0x0c00 6667 #define AN_X1_CONTROL_BAM_SPEED_PRI_23_18_AN_PRIORITY_40GCR4_ALIGN 0 6668 #define AN_X1_CONTROL_BAM_SPEED_PRI_23_18_AN_PRIORITY_40GCR4_BITS 2 6669 #define AN_X1_CONTROL_BAM_SPEED_PRI_23_18_AN_PRIORITY_40GCR4_SHIFT 10 6670 6671 /* AN_X1_CONTROL :: bam_speed_pri_23_18 :: an_priority_40GKR4 [09:08] */ 6672 #define AN_X1_CONTROL_BAM_SPEED_PRI_23_18_AN_PRIORITY_40GKR4_MASK 0x0300 6673 #define AN_X1_CONTROL_BAM_SPEED_PRI_23_18_AN_PRIORITY_40GKR4_ALIGN 0 6674 #define AN_X1_CONTROL_BAM_SPEED_PRI_23_18_AN_PRIORITY_40GKR4_BITS 2 6675 #define AN_X1_CONTROL_BAM_SPEED_PRI_23_18_AN_PRIORITY_40GKR4_SHIFT 8 6676 6677 /* AN_X1_CONTROL :: bam_speed_pri_23_18 :: an_priority_100GCR10 [07:06] */ 6678 #define AN_X1_CONTROL_BAM_SPEED_PRI_23_18_AN_PRIORITY_100GCR10_MASK 0x00c0 6679 #define AN_X1_CONTROL_BAM_SPEED_PRI_23_18_AN_PRIORITY_100GCR10_ALIGN 0 6680 #define AN_X1_CONTROL_BAM_SPEED_PRI_23_18_AN_PRIORITY_100GCR10_BITS 2 6681 #define AN_X1_CONTROL_BAM_SPEED_PRI_23_18_AN_PRIORITY_100GCR10_SHIFT 6 6682 6683 /* AN_X1_CONTROL :: bam_speed_pri_23_18 :: an_priority_13GX4 [05:04] */ 6684 #define AN_X1_CONTROL_BAM_SPEED_PRI_23_18_AN_PRIORITY_13GX4_MASK 0x0030 6685 #define AN_X1_CONTROL_BAM_SPEED_PRI_23_18_AN_PRIORITY_13GX4_ALIGN 0 6686 #define AN_X1_CONTROL_BAM_SPEED_PRI_23_18_AN_PRIORITY_13GX4_BITS 2 6687 #define AN_X1_CONTROL_BAM_SPEED_PRI_23_18_AN_PRIORITY_13GX4_SHIFT 4 6688 6689 /* AN_X1_CONTROL :: bam_speed_pri_23_18 :: an_priority_15GX4 [03:02] */ 6690 #define AN_X1_CONTROL_BAM_SPEED_PRI_23_18_AN_PRIORITY_15GX4_MASK 0x000c 6691 #define AN_X1_CONTROL_BAM_SPEED_PRI_23_18_AN_PRIORITY_15GX4_ALIGN 0 6692 #define AN_X1_CONTROL_BAM_SPEED_PRI_23_18_AN_PRIORITY_15GX4_BITS 2 6693 #define AN_X1_CONTROL_BAM_SPEED_PRI_23_18_AN_PRIORITY_15GX4_SHIFT 2 6694 6695 /* AN_X1_CONTROL :: bam_speed_pri_23_18 :: an_priority_15p75GX2 [01:00] */ 6696 #define AN_X1_CONTROL_BAM_SPEED_PRI_23_18_AN_PRIORITY_15P75GX2_MASK 0x0003 6697 #define AN_X1_CONTROL_BAM_SPEED_PRI_23_18_AN_PRIORITY_15P75GX2_ALIGN 0 6698 #define AN_X1_CONTROL_BAM_SPEED_PRI_23_18_AN_PRIORITY_15P75GX2_BITS 2 6699 #define AN_X1_CONTROL_BAM_SPEED_PRI_23_18_AN_PRIORITY_15P75GX2_SHIFT 0 6700 6701 6702 /**************************************************************************** 6703 * AN_X1_CONTROL :: bam_speed_pri_29_24 6704 */ 6705 /* AN_X1_CONTROL :: bam_speed_pri_29_24 :: reserved0 [15:12] */ 6706 #define AN_X1_CONTROL_BAM_SPEED_PRI_29_24_RESERVED0_MASK 0xf000 6707 #define AN_X1_CONTROL_BAM_SPEED_PRI_29_24_RESERVED0_ALIGN 0 6708 #define AN_X1_CONTROL_BAM_SPEED_PRI_29_24_RESERVED0_BITS 4 6709 #define AN_X1_CONTROL_BAM_SPEED_PRI_29_24_RESERVED0_SHIFT 12 6710 6711 /* AN_X1_CONTROL :: bam_speed_pri_29_24 :: an_priority_20GKR2 [11:10] */ 6712 #define AN_X1_CONTROL_BAM_SPEED_PRI_29_24_AN_PRIORITY_20GKR2_MASK 0x0c00 6713 #define AN_X1_CONTROL_BAM_SPEED_PRI_29_24_AN_PRIORITY_20GKR2_ALIGN 0 6714 #define AN_X1_CONTROL_BAM_SPEED_PRI_29_24_AN_PRIORITY_20GKR2_BITS 2 6715 #define AN_X1_CONTROL_BAM_SPEED_PRI_29_24_AN_PRIORITY_20GKR2_SHIFT 10 6716 6717 /* AN_X1_CONTROL :: bam_speed_pri_29_24 :: an_priority_20GCX4 [09:08] */ 6718 #define AN_X1_CONTROL_BAM_SPEED_PRI_29_24_AN_PRIORITY_20GCX4_MASK 0x0300 6719 #define AN_X1_CONTROL_BAM_SPEED_PRI_29_24_AN_PRIORITY_20GCX4_ALIGN 0 6720 #define AN_X1_CONTROL_BAM_SPEED_PRI_29_24_AN_PRIORITY_20GCX4_BITS 2 6721 #define AN_X1_CONTROL_BAM_SPEED_PRI_29_24_AN_PRIORITY_20GCX4_SHIFT 8 6722 6723 /* AN_X1_CONTROL :: bam_speed_pri_29_24 :: an_priority_20GX2 [07:06] */ 6724 #define AN_X1_CONTROL_BAM_SPEED_PRI_29_24_AN_PRIORITY_20GX2_MASK 0x00c0 6725 #define AN_X1_CONTROL_BAM_SPEED_PRI_29_24_AN_PRIORITY_20GX2_ALIGN 0 6726 #define AN_X1_CONTROL_BAM_SPEED_PRI_29_24_AN_PRIORITY_20GX2_BITS 2 6727 #define AN_X1_CONTROL_BAM_SPEED_PRI_29_24_AN_PRIORITY_20GX2_SHIFT 6 6728 6729 /* AN_X1_CONTROL :: bam_speed_pri_29_24 :: an_priority_16GX4 [05:04] */ 6730 #define AN_X1_CONTROL_BAM_SPEED_PRI_29_24_AN_PRIORITY_16GX4_MASK 0x0030 6731 #define AN_X1_CONTROL_BAM_SPEED_PRI_29_24_AN_PRIORITY_16GX4_ALIGN 0 6732 #define AN_X1_CONTROL_BAM_SPEED_PRI_29_24_AN_PRIORITY_16GX4_BITS 2 6733 #define AN_X1_CONTROL_BAM_SPEED_PRI_29_24_AN_PRIORITY_16GX4_SHIFT 4 6734 6735 /* AN_X1_CONTROL :: bam_speed_pri_29_24 :: an_priority_20GCX2 [03:02] */ 6736 #define AN_X1_CONTROL_BAM_SPEED_PRI_29_24_AN_PRIORITY_20GCX2_MASK 0x000c 6737 #define AN_X1_CONTROL_BAM_SPEED_PRI_29_24_AN_PRIORITY_20GCX2_ALIGN 0 6738 #define AN_X1_CONTROL_BAM_SPEED_PRI_29_24_AN_PRIORITY_20GCX2_BITS 2 6739 #define AN_X1_CONTROL_BAM_SPEED_PRI_29_24_AN_PRIORITY_20GCX2_SHIFT 2 6740 6741 /* AN_X1_CONTROL :: bam_speed_pri_29_24 :: an_priority_20GCR2 [01:00] */ 6742 #define AN_X1_CONTROL_BAM_SPEED_PRI_29_24_AN_PRIORITY_20GCR2_MASK 0x0003 6743 #define AN_X1_CONTROL_BAM_SPEED_PRI_29_24_AN_PRIORITY_20GCR2_ALIGN 0 6744 #define AN_X1_CONTROL_BAM_SPEED_PRI_29_24_AN_PRIORITY_20GCR2_BITS 2 6745 #define AN_X1_CONTROL_BAM_SPEED_PRI_29_24_AN_PRIORITY_20GCR2_SHIFT 0 6746 6747 6748 /**************************************************************************** 6749 * AN_X1_CONTROL :: bam_speed_pri_35_30 6750 */ 6751 /* AN_X1_CONTROL :: bam_speed_pri_35_30 :: reserved0 [15:12] */ 6752 #define AN_X1_CONTROL_BAM_SPEED_PRI_35_30_RESERVED0_MASK 0xf000 6753 #define AN_X1_CONTROL_BAM_SPEED_PRI_35_30_RESERVED0_ALIGN 0 6754 #define AN_X1_CONTROL_BAM_SPEED_PRI_35_30_RESERVED0_BITS 4 6755 #define AN_X1_CONTROL_BAM_SPEED_PRI_35_30_RESERVED0_SHIFT 12 6756 6757 /* AN_X1_CONTROL :: bam_speed_pri_35_30 :: an_priority_31p5G [11:10] */ 6758 #define AN_X1_CONTROL_BAM_SPEED_PRI_35_30_AN_PRIORITY_31P5G_MASK 0x0c00 6759 #define AN_X1_CONTROL_BAM_SPEED_PRI_35_30_AN_PRIORITY_31P5G_ALIGN 0 6760 #define AN_X1_CONTROL_BAM_SPEED_PRI_35_30_AN_PRIORITY_31P5G_BITS 2 6761 #define AN_X1_CONTROL_BAM_SPEED_PRI_35_30_AN_PRIORITY_31P5G_SHIFT 10 6762 6763 /* AN_X1_CONTROL :: bam_speed_pri_35_30 :: an_priority_32p7G [09:08] */ 6764 #define AN_X1_CONTROL_BAM_SPEED_PRI_35_30_AN_PRIORITY_32P7G_MASK 0x0300 6765 #define AN_X1_CONTROL_BAM_SPEED_PRI_35_30_AN_PRIORITY_32P7G_ALIGN 0 6766 #define AN_X1_CONTROL_BAM_SPEED_PRI_35_30_AN_PRIORITY_32P7G_BITS 2 6767 #define AN_X1_CONTROL_BAM_SPEED_PRI_35_30_AN_PRIORITY_32P7G_SHIFT 8 6768 6769 /* AN_X1_CONTROL :: bam_speed_pri_35_30 :: an_priority_40GX4 [07:06] */ 6770 #define AN_X1_CONTROL_BAM_SPEED_PRI_35_30_AN_PRIORITY_40GX4_MASK 0x00c0 6771 #define AN_X1_CONTROL_BAM_SPEED_PRI_35_30_AN_PRIORITY_40GX4_ALIGN 0 6772 #define AN_X1_CONTROL_BAM_SPEED_PRI_35_30_AN_PRIORITY_40GX4_BITS 2 6773 #define AN_X1_CONTROL_BAM_SPEED_PRI_35_30_AN_PRIORITY_40GX4_SHIFT 6 6774 6775 /* AN_X1_CONTROL :: bam_speed_pri_35_30 :: an_priority_20GX4 [05:04] */ 6776 #define AN_X1_CONTROL_BAM_SPEED_PRI_35_30_AN_PRIORITY_20GX4_MASK 0x0030 6777 #define AN_X1_CONTROL_BAM_SPEED_PRI_35_30_AN_PRIORITY_20GX4_ALIGN 0 6778 #define AN_X1_CONTROL_BAM_SPEED_PRI_35_30_AN_PRIORITY_20GX4_BITS 2 6779 #define AN_X1_CONTROL_BAM_SPEED_PRI_35_30_AN_PRIORITY_20GX4_SHIFT 4 6780 6781 /* AN_X1_CONTROL :: bam_speed_pri_35_30 :: an_priority_21GX4 [03:02] */ 6782 #define AN_X1_CONTROL_BAM_SPEED_PRI_35_30_AN_PRIORITY_21GX4_MASK 0x000c 6783 #define AN_X1_CONTROL_BAM_SPEED_PRI_35_30_AN_PRIORITY_21GX4_ALIGN 0 6784 #define AN_X1_CONTROL_BAM_SPEED_PRI_35_30_AN_PRIORITY_21GX4_BITS 2 6785 #define AN_X1_CONTROL_BAM_SPEED_PRI_35_30_AN_PRIORITY_21GX4_SHIFT 2 6786 6787 /* AN_X1_CONTROL :: bam_speed_pri_35_30 :: an_priority_25p45GX4 [01:00] */ 6788 #define AN_X1_CONTROL_BAM_SPEED_PRI_35_30_AN_PRIORITY_25P45GX4_MASK 0x0003 6789 #define AN_X1_CONTROL_BAM_SPEED_PRI_35_30_AN_PRIORITY_25P45GX4_ALIGN 0 6790 #define AN_X1_CONTROL_BAM_SPEED_PRI_35_30_AN_PRIORITY_25P45GX4_BITS 2 6791 #define AN_X1_CONTROL_BAM_SPEED_PRI_35_30_AN_PRIORITY_25P45GX4_SHIFT 0 6792 6793 6794 /**************************************************************************** 6795 * AN_X1_CONTROL :: config_control 6796 */ 6797 /* AN_X1_CONTROL :: config_control :: reserved0 [15:08] */ 6798 #define AN_X1_CONTROL_CONFIG_CONTROL_RESERVED0_MASK 0xff00 6799 #define AN_X1_CONTROL_CONFIG_CONTROL_RESERVED0_ALIGN 0 6800 #define AN_X1_CONTROL_CONFIG_CONTROL_RESERVED0_BITS 8 6801 #define AN_X1_CONTROL_CONFIG_CONTROL_RESERVED0_SHIFT 8 6802 6803 /* AN_X1_CONTROL :: config_control :: an_pd_to_cl37_retry_count [07:00] */ 6804 #define AN_X1_CONTROL_CONFIG_CONTROL_AN_PD_TO_CL37_RETRY_COUNT_MASK 0x00ff 6805 #define AN_X1_CONTROL_CONFIG_CONTROL_AN_PD_TO_CL37_RETRY_COUNT_ALIGN 0 6806 #define AN_X1_CONTROL_CONFIG_CONTROL_AN_PD_TO_CL37_RETRY_COUNT_BITS 8 6807 #define AN_X1_CONTROL_CONFIG_CONTROL_AN_PD_TO_CL37_RETRY_COUNT_SHIFT 0 6808 6809 6810 /**************************************************************************** 6811 * TSCE_TSCE_USER1_AN_X1_TIMERS 6812 */ 6813 /**************************************************************************** 6814 * AN_X1_TIMERS :: cl37_restart 6815 */ 6816 /* AN_X1_TIMERS :: cl37_restart :: cl37_restart_timer_period [15:00] */ 6817 #define AN_X1_TIMERS_CL37_RESTART_CL37_RESTART_TIMER_PERIOD_MASK 0xffff 6818 #define AN_X1_TIMERS_CL37_RESTART_CL37_RESTART_TIMER_PERIOD_ALIGN 0 6819 #define AN_X1_TIMERS_CL37_RESTART_CL37_RESTART_TIMER_PERIOD_BITS 16 6820 #define AN_X1_TIMERS_CL37_RESTART_CL37_RESTART_TIMER_PERIOD_SHIFT 0 6821 6822 6823 /**************************************************************************** 6824 * AN_X1_TIMERS :: cl37_ack 6825 */ 6826 /* AN_X1_TIMERS :: cl37_ack :: cl37_ack_timer_period [15:00] */ 6827 #define AN_X1_TIMERS_CL37_ACK_CL37_ACK_TIMER_PERIOD_MASK 0xffff 6828 #define AN_X1_TIMERS_CL37_ACK_CL37_ACK_TIMER_PERIOD_ALIGN 0 6829 #define AN_X1_TIMERS_CL37_ACK_CL37_ACK_TIMER_PERIOD_BITS 16 6830 #define AN_X1_TIMERS_CL37_ACK_CL37_ACK_TIMER_PERIOD_SHIFT 0 6831 6832 6833 /**************************************************************************** 6834 * AN_X1_TIMERS :: cl37_error 6835 */ 6836 /* AN_X1_TIMERS :: cl37_error :: cl37_error_timer_period [15:00] */ 6837 #define AN_X1_TIMERS_CL37_ERROR_CL37_ERROR_TIMER_PERIOD_MASK 0xffff 6838 #define AN_X1_TIMERS_CL37_ERROR_CL37_ERROR_TIMER_PERIOD_ALIGN 0 6839 #define AN_X1_TIMERS_CL37_ERROR_CL37_ERROR_TIMER_PERIOD_BITS 16 6840 #define AN_X1_TIMERS_CL37_ERROR_CL37_ERROR_TIMER_PERIOD_SHIFT 0 6841 6842 6843 /**************************************************************************** 6844 * AN_X1_TIMERS :: cl73_break_link 6845 */ 6846 /* AN_X1_TIMERS :: cl73_break_link :: tx_disable_timer_period [15:00] */ 6847 #define AN_X1_TIMERS_CL73_BREAK_LINK_TX_DISABLE_TIMER_PERIOD_MASK 0xffff 6848 #define AN_X1_TIMERS_CL73_BREAK_LINK_TX_DISABLE_TIMER_PERIOD_ALIGN 0 6849 #define AN_X1_TIMERS_CL73_BREAK_LINK_TX_DISABLE_TIMER_PERIOD_BITS 16 6850 #define AN_X1_TIMERS_CL73_BREAK_LINK_TX_DISABLE_TIMER_PERIOD_SHIFT 0 6851 6852 6853 /**************************************************************************** 6854 * AN_X1_TIMERS :: cl73_error 6855 */ 6856 /* AN_X1_TIMERS :: cl73_error :: cl73_error_timer_period [15:00] */ 6857 #define AN_X1_TIMERS_CL73_ERROR_CL73_ERROR_TIMER_PERIOD_MASK 0xffff 6858 #define AN_X1_TIMERS_CL73_ERROR_CL73_ERROR_TIMER_PERIOD_ALIGN 0 6859 #define AN_X1_TIMERS_CL73_ERROR_CL73_ERROR_TIMER_PERIOD_BITS 16 6860 #define AN_X1_TIMERS_CL73_ERROR_CL73_ERROR_TIMER_PERIOD_SHIFT 0 6861 6862 6863 /**************************************************************************** 6864 * AN_X1_TIMERS :: cl73_dme_lock 6865 */ 6866 /* AN_X1_TIMERS :: cl73_dme_lock :: pd_dme_lock_timer_period [15:00] */ 6867 #define AN_X1_TIMERS_CL73_DME_LOCK_PD_DME_LOCK_TIMER_PERIOD_MASK 0xffff 6868 #define AN_X1_TIMERS_CL73_DME_LOCK_PD_DME_LOCK_TIMER_PERIOD_ALIGN 0 6869 #define AN_X1_TIMERS_CL73_DME_LOCK_PD_DME_LOCK_TIMER_PERIOD_BITS 16 6870 #define AN_X1_TIMERS_CL73_DME_LOCK_PD_DME_LOCK_TIMER_PERIOD_SHIFT 0 6871 6872 6873 /**************************************************************************** 6874 * AN_X1_TIMERS :: link_up 6875 */ 6876 /* AN_X1_TIMERS :: link_up :: cl73_link_up_timer_period [15:00] */ 6877 #define AN_X1_TIMERS_LINK_UP_CL73_LINK_UP_TIMER_PERIOD_MASK 0xffff 6878 #define AN_X1_TIMERS_LINK_UP_CL73_LINK_UP_TIMER_PERIOD_ALIGN 0 6879 #define AN_X1_TIMERS_LINK_UP_CL73_LINK_UP_TIMER_PERIOD_BITS 16 6880 #define AN_X1_TIMERS_LINK_UP_CL73_LINK_UP_TIMER_PERIOD_SHIFT 0 6881 6882 6883 /**************************************************************************** 6884 * AN_X1_TIMERS :: link_fail_inhibit_timer_cl72 6885 */ 6886 /* AN_X1_TIMERS :: link_fail_inhibit_timer_cl72 :: link_fail_inhibit_timer_cl72_period [15:00] */ 6887 #define AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_CL72_LINK_FAIL_INHIBIT_TIMER_CL72_PERIOD_MASK 0xffff 6888 #define AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_CL72_LINK_FAIL_INHIBIT_TIMER_CL72_PERIOD_ALIGN 0 6889 #define AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_CL72_LINK_FAIL_INHIBIT_TIMER_CL72_PERIOD_BITS 16 6890 #define AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_CL72_LINK_FAIL_INHIBIT_TIMER_CL72_PERIOD_SHIFT 0 6891 6892 6893 /**************************************************************************** 6894 * AN_X1_TIMERS :: link_fail_inhibit_timer_not_cl72 6895 */ 6896 /* AN_X1_TIMERS :: link_fail_inhibit_timer_not_cl72 :: link_fail_inhibit_timer_ncl72_period [15:00] */ 6897 #define AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_NOT_CL72_LINK_FAIL_INHIBIT_TIMER_NCL72_PERIOD_MASK 0xffff 6898 #define AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_NOT_CL72_LINK_FAIL_INHIBIT_TIMER_NCL72_PERIOD_ALIGN 0 6899 #define AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_NOT_CL72_LINK_FAIL_INHIBIT_TIMER_NCL72_PERIOD_BITS 16 6900 #define AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_NOT_CL72_LINK_FAIL_INHIBIT_TIMER_NCL72_PERIOD_SHIFT 0 6901 6902 6903 /**************************************************************************** 6904 * AN_X1_TIMERS :: pd_sd_timer 6905 */ 6906 /* AN_X1_TIMERS :: pd_sd_timer :: pd_sd_timer_period [15:00] */ 6907 #define AN_X1_TIMERS_PD_SD_TIMER_PD_SD_TIMER_PERIOD_MASK 0xffff 6908 #define AN_X1_TIMERS_PD_SD_TIMER_PD_SD_TIMER_PERIOD_ALIGN 0 6909 #define AN_X1_TIMERS_PD_SD_TIMER_PD_SD_TIMER_PERIOD_BITS 16 6910 #define AN_X1_TIMERS_PD_SD_TIMER_PD_SD_TIMER_PERIOD_SHIFT 0 6911 6912 6913 /**************************************************************************** 6914 * AN_X1_TIMERS :: cl37_sync_status_filter_timer 6915 */ 6916 /* AN_X1_TIMERS :: cl37_sync_status_filter_timer :: cl37_sync_status_filter_timer_period [15:00] */ 6917 #define AN_X1_TIMERS_CL37_SYNC_STATUS_FILTER_TIMER_CL37_SYNC_STATUS_FILTER_TIMER_PERIOD_MASK 0xffff 6918 #define AN_X1_TIMERS_CL37_SYNC_STATUS_FILTER_TIMER_CL37_SYNC_STATUS_FILTER_TIMER_PERIOD_ALIGN 0 6919 #define AN_X1_TIMERS_CL37_SYNC_STATUS_FILTER_TIMER_CL37_SYNC_STATUS_FILTER_TIMER_PERIOD_BITS 16 6920 #define AN_X1_TIMERS_CL37_SYNC_STATUS_FILTER_TIMER_CL37_SYNC_STATUS_FILTER_TIMER_PERIOD_SHIFT 0 6921 6922 6923 /**************************************************************************** 6924 * AN_X1_TIMERS :: pd_to_cl37_link_wait_timer 6925 */ 6926 /* AN_X1_TIMERS :: pd_to_cl37_link_wait_timer :: pd_to_cl37_link_wait_timer [15:00] */ 6927 #define AN_X1_TIMERS_PD_TO_CL37_LINK_WAIT_TIMER_PD_TO_CL37_LINK_WAIT_TIMER_MASK 0xffff 6928 #define AN_X1_TIMERS_PD_TO_CL37_LINK_WAIT_TIMER_PD_TO_CL37_LINK_WAIT_TIMER_ALIGN 0 6929 #define AN_X1_TIMERS_PD_TO_CL37_LINK_WAIT_TIMER_PD_TO_CL37_LINK_WAIT_TIMER_BITS 16 6930 #define AN_X1_TIMERS_PD_TO_CL37_LINK_WAIT_TIMER_PD_TO_CL37_LINK_WAIT_TIMER_SHIFT 0 6931 6932 6933 /**************************************************************************** 6934 * AN_X1_TIMERS :: ignore_link_timer 6935 */ 6936 /* AN_X1_TIMERS :: ignore_link_timer :: ignore_link_timer_period [15:00] */ 6937 #define AN_X1_TIMERS_IGNORE_LINK_TIMER_IGNORE_LINK_TIMER_PERIOD_MASK 0xffff 6938 #define AN_X1_TIMERS_IGNORE_LINK_TIMER_IGNORE_LINK_TIMER_PERIOD_ALIGN 0 6939 #define AN_X1_TIMERS_IGNORE_LINK_TIMER_IGNORE_LINK_TIMER_PERIOD_BITS 16 6940 #define AN_X1_TIMERS_IGNORE_LINK_TIMER_IGNORE_LINK_TIMER_PERIOD_SHIFT 0 6941 6942 6943 /**************************************************************************** 6944 * AN_X1_TIMERS :: dme_page_timer 6945 */ 6946 /* AN_X1_TIMERS :: dme_page_timer :: reserved0 [15:14] */ 6947 #define AN_X1_TIMERS_DME_PAGE_TIMER_RESERVED0_MASK 0xc000 6948 #define AN_X1_TIMERS_DME_PAGE_TIMER_RESERVED0_ALIGN 0 6949 #define AN_X1_TIMERS_DME_PAGE_TIMER_RESERVED0_BITS 2 6950 #define AN_X1_TIMERS_DME_PAGE_TIMER_RESERVED0_SHIFT 14 6951 6952 /* AN_X1_TIMERS :: dme_page_timer :: cl73_page_test_max_timer [13:07] */ 6953 #define AN_X1_TIMERS_DME_PAGE_TIMER_CL73_PAGE_TEST_MAX_TIMER_MASK 0x3f80 6954 #define AN_X1_TIMERS_DME_PAGE_TIMER_CL73_PAGE_TEST_MAX_TIMER_ALIGN 0 6955 #define AN_X1_TIMERS_DME_PAGE_TIMER_CL73_PAGE_TEST_MAX_TIMER_BITS 7 6956 #define AN_X1_TIMERS_DME_PAGE_TIMER_CL73_PAGE_TEST_MAX_TIMER_SHIFT 7 6957 6958 /* AN_X1_TIMERS :: dme_page_timer :: cl73_page_test_min_timer [06:00] */ 6959 #define AN_X1_TIMERS_DME_PAGE_TIMER_CL73_PAGE_TEST_MIN_TIMER_MASK 0x007f 6960 #define AN_X1_TIMERS_DME_PAGE_TIMER_CL73_PAGE_TEST_MIN_TIMER_ALIGN 0 6961 #define AN_X1_TIMERS_DME_PAGE_TIMER_CL73_PAGE_TEST_MIN_TIMER_BITS 7 6962 #define AN_X1_TIMERS_DME_PAGE_TIMER_CL73_PAGE_TEST_MIN_TIMER_SHIFT 0 6963 6964 6965 /**************************************************************************** 6966 * AN_X1_TIMERS :: sgmii_cl73_timer_type 6967 */ 6968 /* AN_X1_TIMERS :: sgmii_cl73_timer_type :: sgmii_timer [15:00] */ 6969 #define AN_X1_TIMERS_SGMII_CL73_TIMER_TYPE_SGMII_TIMER_MASK 0xffff 6970 #define AN_X1_TIMERS_SGMII_CL73_TIMER_TYPE_SGMII_TIMER_ALIGN 0 6971 #define AN_X1_TIMERS_SGMII_CL73_TIMER_TYPE_SGMII_TIMER_BITS 16 6972 #define AN_X1_TIMERS_SGMII_CL73_TIMER_TYPE_SGMII_TIMER_SHIFT 0 6973 6974 6975 /**************************************************************************** 6976 * TSCE_TSCE_USER1_sc_x1_control 6977 */ 6978 /**************************************************************************** 6979 * sc_x1_control :: pll_lock_timer 6980 */ 6981 /* sc_x1_control :: pll_lock_timer :: pll_lock_timer_period [15:00] */ 6982 #define SC_X1_CONTROL_PLL_LOCK_TIMER_PLL_LOCK_TIMER_PERIOD_MASK 0xffff 6983 #define SC_X1_CONTROL_PLL_LOCK_TIMER_PLL_LOCK_TIMER_PERIOD_ALIGN 0 6984 #define SC_X1_CONTROL_PLL_LOCK_TIMER_PLL_LOCK_TIMER_PERIOD_BITS 16 6985 #define SC_X1_CONTROL_PLL_LOCK_TIMER_PLL_LOCK_TIMER_PERIOD_SHIFT 0 6986 6987 6988 /**************************************************************************** 6989 * sc_x1_control :: pmd_lock_timer 6990 */ 6991 /* sc_x1_control :: pmd_lock_timer :: pmd_lock_timer_period [15:00] */ 6992 #define SC_X1_CONTROL_PMD_LOCK_TIMER_PMD_LOCK_TIMER_PERIOD_MASK 0xffff 6993 #define SC_X1_CONTROL_PMD_LOCK_TIMER_PMD_LOCK_TIMER_PERIOD_ALIGN 0 6994 #define SC_X1_CONTROL_PMD_LOCK_TIMER_PMD_LOCK_TIMER_PERIOD_BITS 16 6995 #define SC_X1_CONTROL_PMD_LOCK_TIMER_PMD_LOCK_TIMER_PERIOD_SHIFT 0 6996 6997 6998 /**************************************************************************** 6999 * sc_x1_control :: pipeline_reset_count 7000 */ 7001 /* sc_x1_control :: pipeline_reset_count :: pipeline_reset_count [15:00] */ 7002 #define SC_X1_CONTROL_PIPELINE_RESET_COUNT_PIPELINE_RESET_COUNT_MASK 0xffff 7003 #define SC_X1_CONTROL_PIPELINE_RESET_COUNT_PIPELINE_RESET_COUNT_ALIGN 0 7004 #define SC_X1_CONTROL_PIPELINE_RESET_COUNT_PIPELINE_RESET_COUNT_BITS 16 7005 #define SC_X1_CONTROL_PIPELINE_RESET_COUNT_PIPELINE_RESET_COUNT_SHIFT 0 7006 7007 7008 /**************************************************************************** 7009 * sc_x1_control :: tx_reset_count 7010 */ 7011 /* sc_x1_control :: tx_reset_count :: tx_reset_count [15:00] */ 7012 #define SC_X1_CONTROL_TX_RESET_COUNT_TX_RESET_COUNT_MASK 0xffff 7013 #define SC_X1_CONTROL_TX_RESET_COUNT_TX_RESET_COUNT_ALIGN 0 7014 #define SC_X1_CONTROL_TX_RESET_COUNT_TX_RESET_COUNT_BITS 16 7015 #define SC_X1_CONTROL_TX_RESET_COUNT_TX_RESET_COUNT_SHIFT 0 7016 7017 7018 /**************************************************************************** 7019 * sc_x1_control :: status 7020 */ 7021 /* sc_x1_control :: status :: reserved0 [15:03] */ 7022 #define SC_X1_CONTROL_STATUS_RESERVED0_MASK 0xfff8 7023 #define SC_X1_CONTROL_STATUS_RESERVED0_ALIGN 0 7024 #define SC_X1_CONTROL_STATUS_RESERVED0_BITS 13 7025 #define SC_X1_CONTROL_STATUS_RESERVED0_SHIFT 3 7026 7027 /* sc_x1_control :: status :: resolved_port_mode [02:00] */ 7028 #define SC_X1_CONTROL_STATUS_RESOLVED_PORT_MODE_MASK 0x0007 7029 #define SC_X1_CONTROL_STATUS_RESOLVED_PORT_MODE_ALIGN 0 7030 #define SC_X1_CONTROL_STATUS_RESOLVED_PORT_MODE_BITS 3 7031 #define SC_X1_CONTROL_STATUS_RESOLVED_PORT_MODE_SHIFT 0 7032 7033 7034 /**************************************************************************** 7035 * TSCE_TSCE_USER1_sc_x1_speed_override0 7036 */ 7037 /**************************************************************************** 7038 * sc_x1_speed_override0 :: override_speed 7039 */ 7040 /* sc_x1_speed_override0 :: override_speed :: speed [15:08] */ 7041 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_MASK 0xff00 7042 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_ALIGN 0 7043 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_BITS 8 7044 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_SHIFT 8 7045 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_SPEED_2p5G_X1_10p3125 56 7046 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_SPEED_1000M_10p3125 55 7047 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_SPEED_100M_10p3125 54 7048 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_SPEED_10M_10p3125 53 7049 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_SPEED_10p5G_X4 50 7050 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_SPEED_5G_KR1 49 7051 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_SPEED_127G_X12 39 7052 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_SPEED_120G_X12 38 7053 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_SPEED_107G_X10 37 7054 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_SPEED_100G_CR10 36 7055 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_SPEED_42G_X4 35 7056 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_SPEED_40G_CR4 34 7057 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_SPEED_40G_KR4 33 7058 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_SPEED_21G_X2 32 7059 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_SPEED_20G_CR2 31 7060 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_SPEED_20G_KR2 30 7061 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_SPEED_10p6_X1 29 7062 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_SPEED_10G_KR1 28 7063 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_SPEED_40G_X4 27 7064 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_SPEED_20G_X2 26 7065 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_SPEED_20G_CX2 25 7066 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_SPEED_31p5G_KR4 24 7067 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_SPEED_31p5G_X4 23 7068 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_SPEED_15p75G_X2 22 7069 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_SPEED_25p45G_X4 21 7070 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_SPEED_12p7G_X2 20 7071 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_SPEED_21G_X4 19 7072 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_SPEED_10p5G_X2 18 7073 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_SPEED_20G_X4 17 7074 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_SPEED_10G_X2 16 7075 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_SPEED_10G_CX2 15 7076 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_SPEED_20G_CX4 14 7077 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_SPEED_16G_X4 13 7078 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_SPEED_15G_X4 12 7079 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_SPEED_13G_X4 11 7080 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_SPEED_10G_X4 10 7081 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_SPEED_10G_KX4 9 7082 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_SPEED_10G_CX4 8 7083 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_SPEED_5G_X1 7 7084 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_SPEED_2p5G_X1 6 7085 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_SPEED_1G_KX1 5 7086 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_SPEED_1G_CX1 4 7087 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_SPEED_1000M 3 7088 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_SPEED_100M 2 7089 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_SPEED_SPEED_10M 1 7090 7091 /* sc_x1_speed_override0 :: override_speed :: reserved0 [07:03] */ 7092 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_RESERVED0_MASK 0x00f8 7093 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_RESERVED0_ALIGN 0 7094 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_RESERVED0_BITS 5 7095 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_RESERVED0_SHIFT 3 7096 7097 /* sc_x1_speed_override0 :: override_speed :: num_lanes [02:00] */ 7098 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_NUM_LANES_MASK 0x0007 7099 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_NUM_LANES_ALIGN 0 7100 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_NUM_LANES_BITS 3 7101 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED_NUM_LANES_SHIFT 0 7102 7103 7104 /**************************************************************************** 7105 * sc_x1_speed_override0 :: override_0 7106 */ 7107 /* sc_x1_speed_override0 :: override_0 :: os_mode [15:12] */ 7108 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_OS_MODE_MASK 0xf000 7109 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_OS_MODE_ALIGN 0 7110 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_OS_MODE_BITS 4 7111 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_OS_MODE_SHIFT 12 7112 7113 /* sc_x1_speed_override0 :: override_0 :: scr_mode [11:10] */ 7114 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_SCR_MODE_MASK 0x0c00 7115 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_SCR_MODE_ALIGN 0 7116 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_SCR_MODE_BITS 2 7117 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_SCR_MODE_SHIFT 10 7118 7119 /* sc_x1_speed_override0 :: override_0 :: cl72_enable [09:09] */ 7120 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_CL72_ENABLE_MASK 0x0200 7121 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_CL72_ENABLE_ALIGN 0 7122 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_CL72_ENABLE_BITS 1 7123 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_CL72_ENABLE_SHIFT 9 7124 7125 /* sc_x1_speed_override0 :: override_0 :: fec_enable [08:08] */ 7126 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_FEC_ENABLE_MASK 0x0100 7127 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_FEC_ENABLE_ALIGN 0 7128 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_FEC_ENABLE_BITS 1 7129 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_FEC_ENABLE_SHIFT 8 7130 7131 /* sc_x1_speed_override0 :: override_0 :: reserved0 [07:03] */ 7132 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_RESERVED0_MASK 0x00f8 7133 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_RESERVED0_ALIGN 0 7134 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_RESERVED0_BITS 5 7135 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_RESERVED0_SHIFT 3 7136 7137 /* sc_x1_speed_override0 :: override_0 :: encodeMode [02:00] */ 7138 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_ENCODEMODE_MASK 0x0007 7139 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_ENCODEMODE_ALIGN 0 7140 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_ENCODEMODE_BITS 3 7141 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_0_ENCODEMODE_SHIFT 0 7142 7143 7144 /**************************************************************************** 7145 * sc_x1_speed_override0 :: override_1 7146 */ 7147 /* sc_x1_speed_override0 :: override_1 :: descramblermode [15:14] */ 7148 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_DESCRAMBLERMODE_MASK 0xc000 7149 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_DESCRAMBLERMODE_ALIGN 0 7150 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_DESCRAMBLERMODE_BITS 2 7151 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_DESCRAMBLERMODE_SHIFT 14 7152 7153 /* sc_x1_speed_override0 :: override_1 :: decodermode [13:11] */ 7154 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_DECODERMODE_MASK 0x3800 7155 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_DECODERMODE_ALIGN 0 7156 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_DECODERMODE_BITS 3 7157 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_DECODERMODE_SHIFT 11 7158 7159 /* sc_x1_speed_override0 :: override_1 :: deskewmode [10:08] */ 7160 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_DESKEWMODE_MASK 0x0700 7161 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_DESKEWMODE_ALIGN 0 7162 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_DESKEWMODE_BITS 3 7163 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_DESKEWMODE_SHIFT 8 7164 7165 /* sc_x1_speed_override0 :: override_1 :: desc2_mode [07:05] */ 7166 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_DESC2_MODE_MASK 0x00e0 7167 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_DESC2_MODE_ALIGN 0 7168 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_DESC2_MODE_BITS 3 7169 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_DESC2_MODE_SHIFT 5 7170 7171 /* sc_x1_speed_override0 :: override_1 :: CL36ByteDeleteMode [04:03] */ 7172 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_CL36BYTEDELETEMOD16E_MASK 0x0018 7173 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_CL36BYTEDELETEMOD16E_ALIGN 0 7174 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_CL36BYTEDELETEMOD16E_BITS 2 7175 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_CL36BYTEDELETEMOD16E_SHIFT 3 7176 7177 /* sc_x1_speed_override0 :: override_1 :: reserved0 [02:02] */ 7178 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_RESERVED0_MASK 0x0004 7179 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_RESERVED0_ALIGN 0 7180 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_RESERVED0_BITS 1 7181 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_RESERVED0_SHIFT 2 7182 7183 /* sc_x1_speed_override0 :: override_1 :: brcm64b66_descrambler_enable [01:01] */ 7184 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_BRCM64B66_DESCRAMBLER_ENABLE_MASK 0x0002 7185 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_BRCM64B66_DESCRAMBLER_ENABLE_ALIGN 0 7186 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_BRCM64B66_DESCRAMBLER_ENABLE_BITS 1 7187 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_BRCM64B66_DESCRAMBLER_ENABLE_SHIFT 1 7188 7189 /* sc_x1_speed_override0 :: override_1 :: reserved1 [00:00] */ 7190 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_RESERVED1_MASK 0x0001 7191 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_RESERVED1_ALIGN 0 7192 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_RESERVED1_BITS 1 7193 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_1_RESERVED1_SHIFT 0 7194 7195 7196 /**************************************************************************** 7197 * sc_x1_speed_override0 :: override_2 7198 */ 7199 /* sc_x1_speed_override0 :: override_2 :: reserved0 [15:11] */ 7200 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_2_RESERVED0_MASK 0xf800 7201 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_2_RESERVED0_ALIGN 0 7202 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_2_RESERVED0_BITS 5 7203 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_2_RESERVED0_SHIFT 11 7204 7205 /* sc_x1_speed_override0 :: override_2 :: chk_end_en [10:10] */ 7206 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_2_CHK_END_EN_MASK 0x0400 7207 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_2_CHK_END_EN_ALIGN 0 7208 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_2_CHK_END_EN_BITS 1 7209 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_2_CHK_END_EN_SHIFT 10 7210 7211 /* sc_x1_speed_override0 :: override_2 :: reserved1 [09:07] */ 7212 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_2_RESERVED1_MASK 0x0380 7213 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_2_RESERVED1_ALIGN 0 7214 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_2_RESERVED1_BITS 3 7215 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_2_RESERVED1_SHIFT 7 7216 7217 /* sc_x1_speed_override0 :: override_2 :: block_sync_mode [06:04] */ 7218 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_2_BLOCK_SYNC_MODE_MASK 0x0070 7219 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_2_BLOCK_SYNC_MODE_ALIGN 0 7220 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_2_BLOCK_SYNC_MODE_BITS 3 7221 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_2_BLOCK_SYNC_MODE_SHIFT 4 7222 7223 /* sc_x1_speed_override0 :: override_2 :: reserved2 [03:02] */ 7224 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_2_RESERVED2_MASK 0x000c 7225 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_2_RESERVED2_ALIGN 0 7226 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_2_RESERVED2_BITS 2 7227 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_2_RESERVED2_SHIFT 2 7228 7229 /* sc_x1_speed_override0 :: override_2 :: reorder_en [01:01] */ 7230 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_2_REORDER_EN_MASK 0x0002 7231 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_2_REORDER_EN_ALIGN 0 7232 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_2_REORDER_EN_BITS 1 7233 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_2_REORDER_EN_SHIFT 1 7234 7235 /* sc_x1_speed_override0 :: override_2 :: cl36_en [00:00] */ 7236 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_2_CL36_EN_MASK 0x0001 7237 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_2_CL36_EN_ALIGN 0 7238 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_2_CL36_EN_BITS 1 7239 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_2_CL36_EN_SHIFT 0 7240 7241 7242 /**************************************************************************** 7243 * sc_x1_speed_override0 :: override_3 7244 */ 7245 /* sc_x1_speed_override0 :: override_3 :: sgmii_spd_switch [15:15] */ 7246 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_3_SGMII_SPD_SWITCH_MASK 0x8000 7247 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_3_SGMII_SPD_SWITCH_ALIGN 0 7248 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_3_SGMII_SPD_SWITCH_BITS 1 7249 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_3_SGMII_SPD_SWITCH_SHIFT 15 7250 7251 /* sc_x1_speed_override0 :: override_3 :: reserved0 [14:14] */ 7252 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_3_RESERVED0_MASK 0x4000 7253 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_3_RESERVED0_ALIGN 0 7254 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_3_RESERVED0_BITS 1 7255 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_3_RESERVED0_SHIFT 14 7256 7257 /* sc_x1_speed_override0 :: override_3 :: clockcnt0 [13:00] */ 7258 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_3_CLOCKCNT0_MASK 0x3fff 7259 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_3_CLOCKCNT0_ALIGN 0 7260 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_3_CLOCKCNT0_BITS 14 7261 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_3_CLOCKCNT0_SHIFT 0 7262 7263 7264 /**************************************************************************** 7265 * sc_x1_speed_override0 :: override_4 7266 */ 7267 /* sc_x1_speed_override0 :: override_4 :: reserved0 [15:08] */ 7268 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_4_RESERVED0_MASK 0xff00 7269 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_4_RESERVED0_ALIGN 0 7270 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_4_RESERVED0_BITS 8 7271 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_4_RESERVED0_SHIFT 8 7272 7273 /* sc_x1_speed_override0 :: override_4 :: clockcnt1 [07:00] */ 7274 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_4_CLOCKCNT1_MASK 0x00ff 7275 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_4_CLOCKCNT1_ALIGN 0 7276 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_4_CLOCKCNT1_BITS 8 7277 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_4_CLOCKCNT1_SHIFT 0 7278 7279 7280 /**************************************************************************** 7281 * sc_x1_speed_override0 :: override_5 7282 */ 7283 /* sc_x1_speed_override0 :: override_5 :: reserved0 [15:14] */ 7284 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_5_RESERVED0_MASK 0xc000 7285 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_5_RESERVED0_ALIGN 0 7286 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_5_RESERVED0_BITS 2 7287 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_5_RESERVED0_SHIFT 14 7288 7289 /* sc_x1_speed_override0 :: override_5 :: loopcnt0 [13:06] */ 7290 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_5_LOOPCNT0_MASK 0x3fc0 7291 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_5_LOOPCNT0_ALIGN 0 7292 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_5_LOOPCNT0_BITS 8 7293 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_5_LOOPCNT0_SHIFT 6 7294 7295 /* sc_x1_speed_override0 :: override_5 :: loopcnt1 [05:00] */ 7296 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_5_LOOPCNT1_MASK 0x003f 7297 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_5_LOOPCNT1_ALIGN 0 7298 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_5_LOOPCNT1_BITS 6 7299 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_5_LOOPCNT1_SHIFT 0 7300 7301 7302 /**************************************************************************** 7303 * sc_x1_speed_override0 :: override_6 7304 */ 7305 /* sc_x1_speed_override0 :: override_6 :: reserved0 [15:13] */ 7306 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_6_RESERVED0_MASK 0xe000 7307 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_6_RESERVED0_ALIGN 0 7308 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_6_RESERVED0_BITS 3 7309 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_6_RESERVED0_SHIFT 13 7310 7311 /* sc_x1_speed_override0 :: override_6 :: mac_creditgencnt [12:00] */ 7312 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_6_MAC_CREDITGENCNT_MASK 0x1fff 7313 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_6_MAC_CREDITGENCNT_ALIGN 0 7314 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_6_MAC_CREDITGENCNT_BITS 13 7315 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_6_MAC_CREDITGENCNT_SHIFT 0 7316 7317 7318 /**************************************************************************** 7319 * sc_x1_speed_override0 :: override_7 7320 */ 7321 /* sc_x1_speed_override0 :: override_7 :: replication_cnt [15:15] */ 7322 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_REPLICATION_CNT_MASK 0x8000 7323 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_REPLICATION_CNT_ALIGN 0 7324 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_REPLICATION_CNT_BITS 1 7325 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_REPLICATION_CNT_SHIFT 15 7326 7327 /* sc_x1_speed_override0 :: override_7 :: pcs_creditenable [14:14] */ 7328 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_PCS_CREDITENABLE_MASK 0x4000 7329 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_PCS_CREDITENABLE_ALIGN 0 7330 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_PCS_CREDITENABLE_BITS 1 7331 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_PCS_CREDITENABLE_SHIFT 14 7332 7333 /* sc_x1_speed_override0 :: override_7 :: pcs_clockcnt0 [13:00] */ 7334 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_PCS_CLOCKCNT0_MASK 0x3fff 7335 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_PCS_CLOCKCNT0_ALIGN 0 7336 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_PCS_CLOCKCNT0_BITS 14 7337 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_7_PCS_CLOCKCNT0_SHIFT 0 7338 7339 7340 /**************************************************************************** 7341 * sc_x1_speed_override0 :: override_8 7342 */ 7343 /* sc_x1_speed_override0 :: override_8 :: reserved0 [15:13] */ 7344 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_8_RESERVED0_MASK 0xe000 7345 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_8_RESERVED0_ALIGN 0 7346 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_8_RESERVED0_BITS 3 7347 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_8_RESERVED0_SHIFT 13 7348 7349 /* sc_x1_speed_override0 :: override_8 :: pcs_creditgencnt [12:00] */ 7350 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_8_PCS_CREDITGENCNT_MASK 0x1fff 7351 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_8_PCS_CREDITGENCNT_ALIGN 0 7352 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_8_PCS_CREDITGENCNT_BITS 13 7353 #define SC_X1_SPEED_OVERRIDE0_OVERRIDE_8_PCS_CREDITGENCNT_SHIFT 0 7354 7355 7356 /**************************************************************************** 7357 * TSCE_TSCE_USER1_sc_x1_speed_override1 7358 */ 7359 /**************************************************************************** 7360 * sc_x1_speed_override1 :: override_speed 7361 */ 7362 /* sc_x1_speed_override1 :: override_speed :: speed [15:08] */ 7363 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_MASK 0xff00 7364 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_ALIGN 0 7365 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_BITS 8 7366 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_SHIFT 8 7367 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_SPEED_2p5G_X1_10p3125 56 7368 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_SPEED_1000M_10p3125 55 7369 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_SPEED_100M_10p3125 54 7370 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_SPEED_10M_10p3125 53 7371 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_SPEED_10p5G_X4 50 7372 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_SPEED_5G_KR1 49 7373 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_SPEED_127G_X12 39 7374 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_SPEED_120G_X12 38 7375 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_SPEED_107G_X10 37 7376 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_SPEED_100G_CR10 36 7377 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_SPEED_42G_X4 35 7378 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_SPEED_40G_CR4 34 7379 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_SPEED_40G_KR4 33 7380 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_SPEED_21G_X2 32 7381 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_SPEED_20G_CR2 31 7382 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_SPEED_20G_KR2 30 7383 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_SPEED_10p6_X1 29 7384 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_SPEED_10G_KR1 28 7385 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_SPEED_40G_X4 27 7386 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_SPEED_20G_X2 26 7387 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_SPEED_20G_CX2 25 7388 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_SPEED_31p5G_KR4 24 7389 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_SPEED_31p5G_X4 23 7390 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_SPEED_15p75G_X2 22 7391 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_SPEED_25p45G_X4 21 7392 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_SPEED_12p7G_X2 20 7393 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_SPEED_21G_X4 19 7394 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_SPEED_10p5G_X2 18 7395 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_SPEED_20G_X4 17 7396 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_SPEED_10G_X2 16 7397 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_SPEED_10G_CX2 15 7398 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_SPEED_20G_CX4 14 7399 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_SPEED_16G_X4 13 7400 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_SPEED_15G_X4 12 7401 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_SPEED_13G_X4 11 7402 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_SPEED_10G_X4 10 7403 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_SPEED_10G_KX4 9 7404 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_SPEED_10G_CX4 8 7405 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_SPEED_5G_X1 7 7406 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_SPEED_2p5G_X1 6 7407 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_SPEED_1G_KX1 5 7408 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_SPEED_1G_CX1 4 7409 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_SPEED_1000M 3 7410 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_SPEED_100M 2 7411 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_SPEED_SPEED_10M 1 7412 7413 /* sc_x1_speed_override1 :: override_speed :: reserved0 [07:03] */ 7414 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_RESERVED0_MASK 0x00f8 7415 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_RESERVED0_ALIGN 0 7416 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_RESERVED0_BITS 5 7417 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_RESERVED0_SHIFT 3 7418 7419 /* sc_x1_speed_override1 :: override_speed :: num_lanes [02:00] */ 7420 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_NUM_LANES_MASK 0x0007 7421 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_NUM_LANES_ALIGN 0 7422 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_NUM_LANES_BITS 3 7423 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED_NUM_LANES_SHIFT 0 7424 7425 7426 /**************************************************************************** 7427 * sc_x1_speed_override1 :: override_0 7428 */ 7429 /* sc_x1_speed_override1 :: override_0 :: os_mode [15:12] */ 7430 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_OS_MODE_MASK 0xf000 7431 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_OS_MODE_ALIGN 0 7432 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_OS_MODE_BITS 4 7433 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_OS_MODE_SHIFT 12 7434 7435 /* sc_x1_speed_override1 :: override_0 :: scr_mode [11:10] */ 7436 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_SCR_MODE_MASK 0x0c00 7437 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_SCR_MODE_ALIGN 0 7438 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_SCR_MODE_BITS 2 7439 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_SCR_MODE_SHIFT 10 7440 7441 /* sc_x1_speed_override1 :: override_0 :: cl72_enable [09:09] */ 7442 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_CL72_ENABLE_MASK 0x0200 7443 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_CL72_ENABLE_ALIGN 0 7444 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_CL72_ENABLE_BITS 1 7445 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_CL72_ENABLE_SHIFT 9 7446 7447 /* sc_x1_speed_override1 :: override_0 :: fec_enable [08:08] */ 7448 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_FEC_ENABLE_MASK 0x0100 7449 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_FEC_ENABLE_ALIGN 0 7450 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_FEC_ENABLE_BITS 1 7451 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_FEC_ENABLE_SHIFT 8 7452 7453 /* sc_x1_speed_override1 :: override_0 :: reserved0 [07:03] */ 7454 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_RESERVED0_MASK 0x00f8 7455 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_RESERVED0_ALIGN 0 7456 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_RESERVED0_BITS 5 7457 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_RESERVED0_SHIFT 3 7458 7459 /* sc_x1_speed_override1 :: override_0 :: encodeMode [02:00] */ 7460 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_ENCODEMODE_MASK 0x0007 7461 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_ENCODEMODE_ALIGN 0 7462 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_ENCODEMODE_BITS 3 7463 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_0_ENCODEMODE_SHIFT 0 7464 7465 7466 /**************************************************************************** 7467 * sc_x1_speed_override1 :: override_1 7468 */ 7469 /* sc_x1_speed_override1 :: override_1 :: descramblermode [15:14] */ 7470 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_DESCRAMBLERMODE_MASK 0xc000 7471 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_DESCRAMBLERMODE_ALIGN 0 7472 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_DESCRAMBLERMODE_BITS 2 7473 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_DESCRAMBLERMODE_SHIFT 14 7474 7475 /* sc_x1_speed_override1 :: override_1 :: decodermode [13:11] */ 7476 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_DECODERMODE_MASK 0x3800 7477 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_DECODERMODE_ALIGN 0 7478 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_DECODERMODE_BITS 3 7479 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_DECODERMODE_SHIFT 11 7480 7481 /* sc_x1_speed_override1 :: override_1 :: deskewmode [10:08] */ 7482 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_DESKEWMODE_MASK 0x0700 7483 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_DESKEWMODE_ALIGN 0 7484 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_DESKEWMODE_BITS 3 7485 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_DESKEWMODE_SHIFT 8 7486 7487 /* sc_x1_speed_override1 :: override_1 :: desc2_mode [07:05] */ 7488 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_DESC2_MODE_MASK 0x00e0 7489 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_DESC2_MODE_ALIGN 0 7490 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_DESC2_MODE_BITS 3 7491 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_DESC2_MODE_SHIFT 5 7492 7493 /* sc_x1_speed_override1 :: override_1 :: CL36ByteDeleteMode [04:03] */ 7494 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_CL36BYTEDELETEMOD16E_MASK 0x0018 7495 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_CL36BYTEDELETEMOD16E_ALIGN 0 7496 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_CL36BYTEDELETEMOD16E_BITS 2 7497 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_CL36BYTEDELETEMOD16E_SHIFT 3 7498 7499 /* sc_x1_speed_override1 :: override_1 :: reserved0 [02:02] */ 7500 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_RESERVED0_MASK 0x0004 7501 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_RESERVED0_ALIGN 0 7502 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_RESERVED0_BITS 1 7503 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_RESERVED0_SHIFT 2 7504 7505 /* sc_x1_speed_override1 :: override_1 :: brcm64b66_descrambler_enable [01:01] */ 7506 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_BRCM64B66_DESCRAMBLER_ENABLE_MASK 0x0002 7507 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_BRCM64B66_DESCRAMBLER_ENABLE_ALIGN 0 7508 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_BRCM64B66_DESCRAMBLER_ENABLE_BITS 1 7509 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_BRCM64B66_DESCRAMBLER_ENABLE_SHIFT 1 7510 7511 /* sc_x1_speed_override1 :: override_1 :: reserved1 [00:00] */ 7512 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_RESERVED1_MASK 0x0001 7513 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_RESERVED1_ALIGN 0 7514 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_RESERVED1_BITS 1 7515 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_1_RESERVED1_SHIFT 0 7516 7517 7518 /**************************************************************************** 7519 * sc_x1_speed_override1 :: override_2 7520 */ 7521 /* sc_x1_speed_override1 :: override_2 :: reserved0 [15:11] */ 7522 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_2_RESERVED0_MASK 0xf800 7523 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_2_RESERVED0_ALIGN 0 7524 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_2_RESERVED0_BITS 5 7525 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_2_RESERVED0_SHIFT 11 7526 7527 /* sc_x1_speed_override1 :: override_2 :: chk_end_en [10:10] */ 7528 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_2_CHK_END_EN_MASK 0x0400 7529 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_2_CHK_END_EN_ALIGN 0 7530 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_2_CHK_END_EN_BITS 1 7531 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_2_CHK_END_EN_SHIFT 10 7532 7533 /* sc_x1_speed_override1 :: override_2 :: reserved1 [09:07] */ 7534 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_2_RESERVED1_MASK 0x0380 7535 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_2_RESERVED1_ALIGN 0 7536 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_2_RESERVED1_BITS 3 7537 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_2_RESERVED1_SHIFT 7 7538 7539 /* sc_x1_speed_override1 :: override_2 :: block_sync_mode [06:04] */ 7540 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_2_BLOCK_SYNC_MODE_MASK 0x0070 7541 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_2_BLOCK_SYNC_MODE_ALIGN 0 7542 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_2_BLOCK_SYNC_MODE_BITS 3 7543 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_2_BLOCK_SYNC_MODE_SHIFT 4 7544 7545 /* sc_x1_speed_override1 :: override_2 :: reserved2 [03:02] */ 7546 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_2_RESERVED2_MASK 0x000c 7547 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_2_RESERVED2_ALIGN 0 7548 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_2_RESERVED2_BITS 2 7549 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_2_RESERVED2_SHIFT 2 7550 7551 /* sc_x1_speed_override1 :: override_2 :: reorder_en [01:01] */ 7552 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_2_REORDER_EN_MASK 0x0002 7553 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_2_REORDER_EN_ALIGN 0 7554 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_2_REORDER_EN_BITS 1 7555 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_2_REORDER_EN_SHIFT 1 7556 7557 /* sc_x1_speed_override1 :: override_2 :: cl36_en [00:00] */ 7558 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_2_CL36_EN_MASK 0x0001 7559 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_2_CL36_EN_ALIGN 0 7560 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_2_CL36_EN_BITS 1 7561 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_2_CL36_EN_SHIFT 0 7562 7563 7564 /**************************************************************************** 7565 * sc_x1_speed_override1 :: override_3 7566 */ 7567 /* sc_x1_speed_override1 :: override_3 :: sgmii_spd_switch [15:15] */ 7568 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_3_SGMII_SPD_SWITCH_MASK 0x8000 7569 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_3_SGMII_SPD_SWITCH_ALIGN 0 7570 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_3_SGMII_SPD_SWITCH_BITS 1 7571 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_3_SGMII_SPD_SWITCH_SHIFT 15 7572 7573 /* sc_x1_speed_override1 :: override_3 :: reserved0 [14:14] */ 7574 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_3_RESERVED0_MASK 0x4000 7575 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_3_RESERVED0_ALIGN 0 7576 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_3_RESERVED0_BITS 1 7577 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_3_RESERVED0_SHIFT 14 7578 7579 /* sc_x1_speed_override1 :: override_3 :: clockcnt0 [13:00] */ 7580 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_3_CLOCKCNT0_MASK 0x3fff 7581 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_3_CLOCKCNT0_ALIGN 0 7582 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_3_CLOCKCNT0_BITS 14 7583 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_3_CLOCKCNT0_SHIFT 0 7584 7585 7586 /**************************************************************************** 7587 * sc_x1_speed_override1 :: override_4 7588 */ 7589 /* sc_x1_speed_override1 :: override_4 :: reserved0 [15:08] */ 7590 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_4_RESERVED0_MASK 0xff00 7591 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_4_RESERVED0_ALIGN 0 7592 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_4_RESERVED0_BITS 8 7593 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_4_RESERVED0_SHIFT 8 7594 7595 /* sc_x1_speed_override1 :: override_4 :: clockcnt1 [07:00] */ 7596 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_4_CLOCKCNT1_MASK 0x00ff 7597 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_4_CLOCKCNT1_ALIGN 0 7598 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_4_CLOCKCNT1_BITS 8 7599 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_4_CLOCKCNT1_SHIFT 0 7600 7601 7602 /**************************************************************************** 7603 * sc_x1_speed_override1 :: override_5 7604 */ 7605 /* sc_x1_speed_override1 :: override_5 :: reserved0 [15:14] */ 7606 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_5_RESERVED0_MASK 0xc000 7607 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_5_RESERVED0_ALIGN 0 7608 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_5_RESERVED0_BITS 2 7609 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_5_RESERVED0_SHIFT 14 7610 7611 /* sc_x1_speed_override1 :: override_5 :: loopcnt0 [13:06] */ 7612 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_5_LOOPCNT0_MASK 0x3fc0 7613 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_5_LOOPCNT0_ALIGN 0 7614 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_5_LOOPCNT0_BITS 8 7615 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_5_LOOPCNT0_SHIFT 6 7616 7617 /* sc_x1_speed_override1 :: override_5 :: loopcnt1 [05:00] */ 7618 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_5_LOOPCNT1_MASK 0x003f 7619 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_5_LOOPCNT1_ALIGN 0 7620 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_5_LOOPCNT1_BITS 6 7621 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_5_LOOPCNT1_SHIFT 0 7622 7623 7624 /**************************************************************************** 7625 * sc_x1_speed_override1 :: override_6 7626 */ 7627 /* sc_x1_speed_override1 :: override_6 :: reserved0 [15:13] */ 7628 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_6_RESERVED0_MASK 0xe000 7629 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_6_RESERVED0_ALIGN 0 7630 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_6_RESERVED0_BITS 3 7631 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_6_RESERVED0_SHIFT 13 7632 7633 /* sc_x1_speed_override1 :: override_6 :: mac_creditgencnt [12:00] */ 7634 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_6_MAC_CREDITGENCNT_MASK 0x1fff 7635 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_6_MAC_CREDITGENCNT_ALIGN 0 7636 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_6_MAC_CREDITGENCNT_BITS 13 7637 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_6_MAC_CREDITGENCNT_SHIFT 0 7638 7639 7640 /**************************************************************************** 7641 * sc_x1_speed_override1 :: override_7 7642 */ 7643 /* sc_x1_speed_override1 :: override_7 :: replication_cnt [15:15] */ 7644 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_REPLICATION_CNT_MASK 0x8000 7645 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_REPLICATION_CNT_ALIGN 0 7646 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_REPLICATION_CNT_BITS 1 7647 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_REPLICATION_CNT_SHIFT 15 7648 7649 /* sc_x1_speed_override1 :: override_7 :: pcs_creditenable [14:14] */ 7650 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_PCS_CREDITENABLE_MASK 0x4000 7651 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_PCS_CREDITENABLE_ALIGN 0 7652 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_PCS_CREDITENABLE_BITS 1 7653 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_PCS_CREDITENABLE_SHIFT 14 7654 7655 /* sc_x1_speed_override1 :: override_7 :: pcs_clockcnt0 [13:00] */ 7656 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_PCS_CLOCKCNT0_MASK 0x3fff 7657 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_PCS_CLOCKCNT0_ALIGN 0 7658 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_PCS_CLOCKCNT0_BITS 14 7659 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_7_PCS_CLOCKCNT0_SHIFT 0 7660 7661 7662 /**************************************************************************** 7663 * sc_x1_speed_override1 :: override_8 7664 */ 7665 /* sc_x1_speed_override1 :: override_8 :: reserved0 [15:13] */ 7666 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_8_RESERVED0_MASK 0xe000 7667 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_8_RESERVED0_ALIGN 0 7668 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_8_RESERVED0_BITS 3 7669 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_8_RESERVED0_SHIFT 13 7670 7671 /* sc_x1_speed_override1 :: override_8 :: pcs_creditgencnt [12:00] */ 7672 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_8_PCS_CREDITGENCNT_MASK 0x1fff 7673 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_8_PCS_CREDITGENCNT_ALIGN 0 7674 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_8_PCS_CREDITGENCNT_BITS 13 7675 #define SC_X1_SPEED_OVERRIDE1_OVERRIDE_8_PCS_CREDITGENCNT_SHIFT 0 7676 7677 7678 /**************************************************************************** 7679 * TSCE_TSCE_USER1_sc_x1_speed_override2 7680 */ 7681 /**************************************************************************** 7682 * sc_x1_speed_override2 :: override_speed 7683 */ 7684 /* sc_x1_speed_override2 :: override_speed :: speed [15:08] */ 7685 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_MASK 0xff00 7686 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_ALIGN 0 7687 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_BITS 8 7688 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_SHIFT 8 7689 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_SPEED_2p5G_X1_10p3125 56 7690 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_SPEED_1000M_10p3125 55 7691 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_SPEED_100M_10p3125 54 7692 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_SPEED_10M_10p3125 53 7693 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_SPEED_10p5G_X4 50 7694 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_SPEED_5G_KR1 49 7695 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_SPEED_127G_X12 39 7696 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_SPEED_120G_X12 38 7697 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_SPEED_107G_X10 37 7698 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_SPEED_100G_CR10 36 7699 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_SPEED_42G_X4 35 7700 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_SPEED_40G_CR4 34 7701 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_SPEED_40G_KR4 33 7702 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_SPEED_21G_X2 32 7703 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_SPEED_20G_CR2 31 7704 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_SPEED_20G_KR2 30 7705 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_SPEED_10p6_X1 29 7706 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_SPEED_10G_KR1 28 7707 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_SPEED_40G_X4 27 7708 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_SPEED_20G_X2 26 7709 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_SPEED_20G_CX2 25 7710 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_SPEED_31p5G_KR4 24 7711 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_SPEED_31p5G_X4 23 7712 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_SPEED_15p75G_X2 22 7713 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_SPEED_25p45G_X4 21 7714 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_SPEED_12p7G_X2 20 7715 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_SPEED_21G_X4 19 7716 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_SPEED_10p5G_X2 18 7717 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_SPEED_20G_X4 17 7718 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_SPEED_10G_X2 16 7719 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_SPEED_10G_CX2 15 7720 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_SPEED_20G_CX4 14 7721 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_SPEED_16G_X4 13 7722 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_SPEED_15G_X4 12 7723 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_SPEED_13G_X4 11 7724 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_SPEED_10G_X4 10 7725 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_SPEED_10G_KX4 9 7726 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_SPEED_10G_CX4 8 7727 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_SPEED_5G_X1 7 7728 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_SPEED_2p5G_X1 6 7729 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_SPEED_1G_KX1 5 7730 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_SPEED_1G_CX1 4 7731 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_SPEED_1000M 3 7732 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_SPEED_100M 2 7733 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_SPEED_SPEED_10M 1 7734 7735 /* sc_x1_speed_override2 :: override_speed :: reserved0 [07:03] */ 7736 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_RESERVED0_MASK 0x00f8 7737 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_RESERVED0_ALIGN 0 7738 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_RESERVED0_BITS 5 7739 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_RESERVED0_SHIFT 3 7740 7741 /* sc_x1_speed_override2 :: override_speed :: num_lanes [02:00] */ 7742 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_NUM_LANES_MASK 0x0007 7743 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_NUM_LANES_ALIGN 0 7744 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_NUM_LANES_BITS 3 7745 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED_NUM_LANES_SHIFT 0 7746 7747 7748 /**************************************************************************** 7749 * sc_x1_speed_override2 :: override_0 7750 */ 7751 /* sc_x1_speed_override2 :: override_0 :: os_mode [15:12] */ 7752 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_OS_MODE_MASK 0xf000 7753 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_OS_MODE_ALIGN 0 7754 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_OS_MODE_BITS 4 7755 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_OS_MODE_SHIFT 12 7756 7757 /* sc_x1_speed_override2 :: override_0 :: scr_mode [11:10] */ 7758 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_SCR_MODE_MASK 0x0c00 7759 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_SCR_MODE_ALIGN 0 7760 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_SCR_MODE_BITS 2 7761 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_SCR_MODE_SHIFT 10 7762 7763 /* sc_x1_speed_override2 :: override_0 :: cl72_enable [09:09] */ 7764 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_CL72_ENABLE_MASK 0x0200 7765 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_CL72_ENABLE_ALIGN 0 7766 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_CL72_ENABLE_BITS 1 7767 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_CL72_ENABLE_SHIFT 9 7768 7769 /* sc_x1_speed_override2 :: override_0 :: fec_enable [08:08] */ 7770 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_FEC_ENABLE_MASK 0x0100 7771 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_FEC_ENABLE_ALIGN 0 7772 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_FEC_ENABLE_BITS 1 7773 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_FEC_ENABLE_SHIFT 8 7774 7775 /* sc_x1_speed_override2 :: override_0 :: reserved0 [07:03] */ 7776 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_RESERVED0_MASK 0x00f8 7777 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_RESERVED0_ALIGN 0 7778 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_RESERVED0_BITS 5 7779 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_RESERVED0_SHIFT 3 7780 7781 /* sc_x1_speed_override2 :: override_0 :: encodeMode [02:00] */ 7782 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_ENCODEMODE_MASK 0x0007 7783 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_ENCODEMODE_ALIGN 0 7784 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_ENCODEMODE_BITS 3 7785 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_0_ENCODEMODE_SHIFT 0 7786 7787 7788 /**************************************************************************** 7789 * sc_x1_speed_override2 :: override_1 7790 */ 7791 /* sc_x1_speed_override2 :: override_1 :: descramblermode [15:14] */ 7792 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_DESCRAMBLERMODE_MASK 0xc000 7793 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_DESCRAMBLERMODE_ALIGN 0 7794 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_DESCRAMBLERMODE_BITS 2 7795 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_DESCRAMBLERMODE_SHIFT 14 7796 7797 /* sc_x1_speed_override2 :: override_1 :: decodermode [13:11] */ 7798 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_DECODERMODE_MASK 0x3800 7799 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_DECODERMODE_ALIGN 0 7800 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_DECODERMODE_BITS 3 7801 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_DECODERMODE_SHIFT 11 7802 7803 /* sc_x1_speed_override2 :: override_1 :: deskewmode [10:08] */ 7804 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_DESKEWMODE_MASK 0x0700 7805 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_DESKEWMODE_ALIGN 0 7806 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_DESKEWMODE_BITS 3 7807 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_DESKEWMODE_SHIFT 8 7808 7809 /* sc_x1_speed_override2 :: override_1 :: desc2_mode [07:05] */ 7810 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_DESC2_MODE_MASK 0x00e0 7811 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_DESC2_MODE_ALIGN 0 7812 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_DESC2_MODE_BITS 3 7813 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_DESC2_MODE_SHIFT 5 7814 7815 /* sc_x1_speed_override2 :: override_1 :: CL36ByteDeleteMode [04:03] */ 7816 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_CL36BYTEDELETEMOD16E_MASK 0x0018 7817 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_CL36BYTEDELETEMOD16E_ALIGN 0 7818 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_CL36BYTEDELETEMOD16E_BITS 2 7819 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_CL36BYTEDELETEMOD16E_SHIFT 3 7820 7821 /* sc_x1_speed_override2 :: override_1 :: reserved0 [02:02] */ 7822 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_RESERVED0_MASK 0x0004 7823 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_RESERVED0_ALIGN 0 7824 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_RESERVED0_BITS 1 7825 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_RESERVED0_SHIFT 2 7826 7827 /* sc_x1_speed_override2 :: override_1 :: brcm64b66_descrambler_enable [01:01] */ 7828 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_BRCM64B66_DESCRAMBLER_ENABLE_MASK 0x0002 7829 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_BRCM64B66_DESCRAMBLER_ENABLE_ALIGN 0 7830 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_BRCM64B66_DESCRAMBLER_ENABLE_BITS 1 7831 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_BRCM64B66_DESCRAMBLER_ENABLE_SHIFT 1 7832 7833 /* sc_x1_speed_override2 :: override_1 :: reserved1 [00:00] */ 7834 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_RESERVED1_MASK 0x0001 7835 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_RESERVED1_ALIGN 0 7836 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_RESERVED1_BITS 1 7837 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_1_RESERVED1_SHIFT 0 7838 7839 7840 /**************************************************************************** 7841 * sc_x1_speed_override2 :: override_2 7842 */ 7843 /* sc_x1_speed_override2 :: override_2 :: reserved0 [15:11] */ 7844 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_2_RESERVED0_MASK 0xf800 7845 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_2_RESERVED0_ALIGN 0 7846 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_2_RESERVED0_BITS 5 7847 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_2_RESERVED0_SHIFT 11 7848 7849 /* sc_x1_speed_override2 :: override_2 :: chk_end_en [10:10] */ 7850 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_2_CHK_END_EN_MASK 0x0400 7851 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_2_CHK_END_EN_ALIGN 0 7852 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_2_CHK_END_EN_BITS 1 7853 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_2_CHK_END_EN_SHIFT 10 7854 7855 /* sc_x1_speed_override2 :: override_2 :: reserved1 [09:07] */ 7856 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_2_RESERVED1_MASK 0x0380 7857 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_2_RESERVED1_ALIGN 0 7858 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_2_RESERVED1_BITS 3 7859 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_2_RESERVED1_SHIFT 7 7860 7861 /* sc_x1_speed_override2 :: override_2 :: block_sync_mode [06:04] */ 7862 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_2_BLOCK_SYNC_MODE_MASK 0x0070 7863 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_2_BLOCK_SYNC_MODE_ALIGN 0 7864 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_2_BLOCK_SYNC_MODE_BITS 3 7865 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_2_BLOCK_SYNC_MODE_SHIFT 4 7866 7867 /* sc_x1_speed_override2 :: override_2 :: reserved2 [03:02] */ 7868 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_2_RESERVED2_MASK 0x000c 7869 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_2_RESERVED2_ALIGN 0 7870 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_2_RESERVED2_BITS 2 7871 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_2_RESERVED2_SHIFT 2 7872 7873 /* sc_x1_speed_override2 :: override_2 :: reorder_en [01:01] */ 7874 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_2_REORDER_EN_MASK 0x0002 7875 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_2_REORDER_EN_ALIGN 0 7876 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_2_REORDER_EN_BITS 1 7877 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_2_REORDER_EN_SHIFT 1 7878 7879 /* sc_x1_speed_override2 :: override_2 :: cl36_en [00:00] */ 7880 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_2_CL36_EN_MASK 0x0001 7881 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_2_CL36_EN_ALIGN 0 7882 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_2_CL36_EN_BITS 1 7883 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_2_CL36_EN_SHIFT 0 7884 7885 7886 /**************************************************************************** 7887 * sc_x1_speed_override2 :: override_3 7888 */ 7889 /* sc_x1_speed_override2 :: override_3 :: sgmii_spd_switch [15:15] */ 7890 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_3_SGMII_SPD_SWITCH_MASK 0x8000 7891 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_3_SGMII_SPD_SWITCH_ALIGN 0 7892 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_3_SGMII_SPD_SWITCH_BITS 1 7893 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_3_SGMII_SPD_SWITCH_SHIFT 15 7894 7895 /* sc_x1_speed_override2 :: override_3 :: reserved0 [14:14] */ 7896 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_3_RESERVED0_MASK 0x4000 7897 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_3_RESERVED0_ALIGN 0 7898 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_3_RESERVED0_BITS 1 7899 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_3_RESERVED0_SHIFT 14 7900 7901 /* sc_x1_speed_override2 :: override_3 :: clockcnt0 [13:00] */ 7902 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_3_CLOCKCNT0_MASK 0x3fff 7903 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_3_CLOCKCNT0_ALIGN 0 7904 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_3_CLOCKCNT0_BITS 14 7905 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_3_CLOCKCNT0_SHIFT 0 7906 7907 7908 /**************************************************************************** 7909 * sc_x1_speed_override2 :: override_4 7910 */ 7911 /* sc_x1_speed_override2 :: override_4 :: reserved0 [15:08] */ 7912 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_4_RESERVED0_MASK 0xff00 7913 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_4_RESERVED0_ALIGN 0 7914 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_4_RESERVED0_BITS 8 7915 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_4_RESERVED0_SHIFT 8 7916 7917 /* sc_x1_speed_override2 :: override_4 :: clockcnt1 [07:00] */ 7918 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_4_CLOCKCNT1_MASK 0x00ff 7919 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_4_CLOCKCNT1_ALIGN 0 7920 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_4_CLOCKCNT1_BITS 8 7921 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_4_CLOCKCNT1_SHIFT 0 7922 7923 7924 /**************************************************************************** 7925 * sc_x1_speed_override2 :: override_5 7926 */ 7927 /* sc_x1_speed_override2 :: override_5 :: reserved0 [15:14] */ 7928 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_5_RESERVED0_MASK 0xc000 7929 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_5_RESERVED0_ALIGN 0 7930 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_5_RESERVED0_BITS 2 7931 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_5_RESERVED0_SHIFT 14 7932 7933 /* sc_x1_speed_override2 :: override_5 :: loopcnt0 [13:06] */ 7934 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_5_LOOPCNT0_MASK 0x3fc0 7935 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_5_LOOPCNT0_ALIGN 0 7936 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_5_LOOPCNT0_BITS 8 7937 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_5_LOOPCNT0_SHIFT 6 7938 7939 /* sc_x1_speed_override2 :: override_5 :: loopcnt1 [05:00] */ 7940 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_5_LOOPCNT1_MASK 0x003f 7941 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_5_LOOPCNT1_ALIGN 0 7942 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_5_LOOPCNT1_BITS 6 7943 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_5_LOOPCNT1_SHIFT 0 7944 7945 7946 /**************************************************************************** 7947 * sc_x1_speed_override2 :: override_6 7948 */ 7949 /* sc_x1_speed_override2 :: override_6 :: reserved0 [15:13] */ 7950 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_6_RESERVED0_MASK 0xe000 7951 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_6_RESERVED0_ALIGN 0 7952 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_6_RESERVED0_BITS 3 7953 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_6_RESERVED0_SHIFT 13 7954 7955 /* sc_x1_speed_override2 :: override_6 :: mac_creditgencnt [12:00] */ 7956 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_6_MAC_CREDITGENCNT_MASK 0x1fff 7957 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_6_MAC_CREDITGENCNT_ALIGN 0 7958 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_6_MAC_CREDITGENCNT_BITS 13 7959 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_6_MAC_CREDITGENCNT_SHIFT 0 7960 7961 7962 /**************************************************************************** 7963 * sc_x1_speed_override2 :: override_7 7964 */ 7965 /* sc_x1_speed_override2 :: override_7 :: replication_cnt [15:15] */ 7966 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_REPLICATION_CNT_MASK 0x8000 7967 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_REPLICATION_CNT_ALIGN 0 7968 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_REPLICATION_CNT_BITS 1 7969 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_REPLICATION_CNT_SHIFT 15 7970 7971 /* sc_x1_speed_override2 :: override_7 :: pcs_creditenable [14:14] */ 7972 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_PCS_CREDITENABLE_MASK 0x4000 7973 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_PCS_CREDITENABLE_ALIGN 0 7974 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_PCS_CREDITENABLE_BITS 1 7975 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_PCS_CREDITENABLE_SHIFT 14 7976 7977 /* sc_x1_speed_override2 :: override_7 :: pcs_clockcnt0 [13:00] */ 7978 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_PCS_CLOCKCNT0_MASK 0x3fff 7979 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_PCS_CLOCKCNT0_ALIGN 0 7980 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_PCS_CLOCKCNT0_BITS 14 7981 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_7_PCS_CLOCKCNT0_SHIFT 0 7982 7983 7984 /**************************************************************************** 7985 * sc_x1_speed_override2 :: override_8 7986 */ 7987 /* sc_x1_speed_override2 :: override_8 :: reserved0 [15:13] */ 7988 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_8_RESERVED0_MASK 0xe000 7989 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_8_RESERVED0_ALIGN 0 7990 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_8_RESERVED0_BITS 3 7991 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_8_RESERVED0_SHIFT 13 7992 7993 /* sc_x1_speed_override2 :: override_8 :: pcs_creditgencnt [12:00] */ 7994 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_8_PCS_CREDITGENCNT_MASK 0x1fff 7995 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_8_PCS_CREDITGENCNT_ALIGN 0 7996 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_8_PCS_CREDITGENCNT_BITS 13 7997 #define SC_X1_SPEED_OVERRIDE2_OVERRIDE_8_PCS_CREDITGENCNT_SHIFT 0 7998 7999 8000 /**************************************************************************** 8001 * TSCE_TSCE_USER1_sc_x1_speed_override3 8002 */ 8003 /**************************************************************************** 8004 * sc_x1_speed_override3 :: override_speed 8005 */ 8006 /* sc_x1_speed_override3 :: override_speed :: speed [15:08] */ 8007 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_MASK 0xff00 8008 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_ALIGN 0 8009 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_BITS 8 8010 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_SHIFT 8 8011 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_SPEED_2p5G_X1_10p3125 56 8012 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_SPEED_1000M_10p3125 55 8013 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_SPEED_100M_10p3125 54 8014 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_SPEED_10M_10p3125 53 8015 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_SPEED_10p5G_X4 50 8016 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_SPEED_5G_KR1 49 8017 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_SPEED_127G_X12 39 8018 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_SPEED_120G_X12 38 8019 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_SPEED_107G_X10 37 8020 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_SPEED_100G_CR10 36 8021 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_SPEED_42G_X4 35 8022 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_SPEED_40G_CR4 34 8023 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_SPEED_40G_KR4 33 8024 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_SPEED_21G_X2 32 8025 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_SPEED_20G_CR2 31 8026 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_SPEED_20G_KR2 30 8027 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_SPEED_10p6_X1 29 8028 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_SPEED_10G_KR1 28 8029 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_SPEED_40G_X4 27 8030 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_SPEED_20G_X2 26 8031 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_SPEED_20G_CX2 25 8032 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_SPEED_31p5G_KR4 24 8033 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_SPEED_31p5G_X4 23 8034 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_SPEED_15p75G_X2 22 8035 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_SPEED_25p45G_X4 21 8036 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_SPEED_12p7G_X2 20 8037 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_SPEED_21G_X4 19 8038 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_SPEED_10p5G_X2 18 8039 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_SPEED_20G_X4 17 8040 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_SPEED_10G_X2 16 8041 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_SPEED_10G_CX2 15 8042 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_SPEED_20G_CX4 14 8043 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_SPEED_16G_X4 13 8044 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_SPEED_15G_X4 12 8045 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_SPEED_13G_X4 11 8046 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_SPEED_10G_X4 10 8047 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_SPEED_10G_KX4 9 8048 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_SPEED_10G_CX4 8 8049 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_SPEED_5G_X1 7 8050 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_SPEED_2p5G_X1 6 8051 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_SPEED_1G_KX1 5 8052 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_SPEED_1G_CX1 4 8053 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_SPEED_1000M 3 8054 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_SPEED_100M 2 8055 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_SPEED_SPEED_10M 1 8056 8057 /* sc_x1_speed_override3 :: override_speed :: reserved0 [07:03] */ 8058 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_RESERVED0_MASK 0x00f8 8059 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_RESERVED0_ALIGN 0 8060 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_RESERVED0_BITS 5 8061 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_RESERVED0_SHIFT 3 8062 8063 /* sc_x1_speed_override3 :: override_speed :: num_lanes [02:00] */ 8064 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_NUM_LANES_MASK 0x0007 8065 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_NUM_LANES_ALIGN 0 8066 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_NUM_LANES_BITS 3 8067 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED_NUM_LANES_SHIFT 0 8068 8069 8070 /**************************************************************************** 8071 * sc_x1_speed_override3 :: override_0 8072 */ 8073 /* sc_x1_speed_override3 :: override_0 :: os_mode [15:12] */ 8074 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_OS_MODE_MASK 0xf000 8075 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_OS_MODE_ALIGN 0 8076 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_OS_MODE_BITS 4 8077 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_OS_MODE_SHIFT 12 8078 8079 /* sc_x1_speed_override3 :: override_0 :: scr_mode [11:10] */ 8080 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_SCR_MODE_MASK 0x0c00 8081 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_SCR_MODE_ALIGN 0 8082 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_SCR_MODE_BITS 2 8083 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_SCR_MODE_SHIFT 10 8084 8085 /* sc_x1_speed_override3 :: override_0 :: cl72_enable [09:09] */ 8086 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_CL72_ENABLE_MASK 0x0200 8087 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_CL72_ENABLE_ALIGN 0 8088 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_CL72_ENABLE_BITS 1 8089 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_CL72_ENABLE_SHIFT 9 8090 8091 /* sc_x1_speed_override3 :: override_0 :: fec_enable [08:08] */ 8092 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_FEC_ENABLE_MASK 0x0100 8093 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_FEC_ENABLE_ALIGN 0 8094 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_FEC_ENABLE_BITS 1 8095 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_FEC_ENABLE_SHIFT 8 8096 8097 /* sc_x1_speed_override3 :: override_0 :: reserved0 [07:03] */ 8098 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_RESERVED0_MASK 0x00f8 8099 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_RESERVED0_ALIGN 0 8100 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_RESERVED0_BITS 5 8101 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_RESERVED0_SHIFT 3 8102 8103 /* sc_x1_speed_override3 :: override_0 :: encodeMode [02:00] */ 8104 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_ENCODEMODE_MASK 0x0007 8105 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_ENCODEMODE_ALIGN 0 8106 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_ENCODEMODE_BITS 3 8107 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_0_ENCODEMODE_SHIFT 0 8108 8109 8110 /**************************************************************************** 8111 * sc_x1_speed_override3 :: override_1 8112 */ 8113 /* sc_x1_speed_override3 :: override_1 :: descramblermode [15:14] */ 8114 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_DESCRAMBLERMODE_MASK 0xc000 8115 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_DESCRAMBLERMODE_ALIGN 0 8116 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_DESCRAMBLERMODE_BITS 2 8117 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_DESCRAMBLERMODE_SHIFT 14 8118 8119 /* sc_x1_speed_override3 :: override_1 :: decodermode [13:11] */ 8120 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_DECODERMODE_MASK 0x3800 8121 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_DECODERMODE_ALIGN 0 8122 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_DECODERMODE_BITS 3 8123 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_DECODERMODE_SHIFT 11 8124 8125 /* sc_x1_speed_override3 :: override_1 :: deskewmode [10:08] */ 8126 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_DESKEWMODE_MASK 0x0700 8127 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_DESKEWMODE_ALIGN 0 8128 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_DESKEWMODE_BITS 3 8129 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_DESKEWMODE_SHIFT 8 8130 8131 /* sc_x1_speed_override3 :: override_1 :: desc2_mode [07:05] */ 8132 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_DESC2_MODE_MASK 0x00e0 8133 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_DESC2_MODE_ALIGN 0 8134 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_DESC2_MODE_BITS 3 8135 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_DESC2_MODE_SHIFT 5 8136 8137 /* sc_x1_speed_override3 :: override_1 :: CL36ByteDeleteMode [04:03] */ 8138 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_CL36BYTEDELETEMOD16E_MASK 0x0018 8139 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_CL36BYTEDELETEMOD16E_ALIGN 0 8140 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_CL36BYTEDELETEMOD16E_BITS 2 8141 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_CL36BYTEDELETEMOD16E_SHIFT 3 8142 8143 /* sc_x1_speed_override3 :: override_1 :: reserved0 [02:02] */ 8144 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_RESERVED0_MASK 0x0004 8145 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_RESERVED0_ALIGN 0 8146 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_RESERVED0_BITS 1 8147 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_RESERVED0_SHIFT 2 8148 8149 /* sc_x1_speed_override3 :: override_1 :: brcm64b66_descrambler_enable [01:01] */ 8150 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_BRCM64B66_DESCRAMBLER_ENABLE_MASK 0x0002 8151 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_BRCM64B66_DESCRAMBLER_ENABLE_ALIGN 0 8152 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_BRCM64B66_DESCRAMBLER_ENABLE_BITS 1 8153 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_BRCM64B66_DESCRAMBLER_ENABLE_SHIFT 1 8154 8155 /* sc_x1_speed_override3 :: override_1 :: reserved1 [00:00] */ 8156 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_RESERVED1_MASK 0x0001 8157 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_RESERVED1_ALIGN 0 8158 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_RESERVED1_BITS 1 8159 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_1_RESERVED1_SHIFT 0 8160 8161 8162 /**************************************************************************** 8163 * sc_x1_speed_override3 :: override_2 8164 */ 8165 /* sc_x1_speed_override3 :: override_2 :: reserved0 [15:11] */ 8166 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_2_RESERVED0_MASK 0xf800 8167 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_2_RESERVED0_ALIGN 0 8168 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_2_RESERVED0_BITS 5 8169 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_2_RESERVED0_SHIFT 11 8170 8171 /* sc_x1_speed_override3 :: override_2 :: chk_end_en [10:10] */ 8172 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_2_CHK_END_EN_MASK 0x0400 8173 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_2_CHK_END_EN_ALIGN 0 8174 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_2_CHK_END_EN_BITS 1 8175 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_2_CHK_END_EN_SHIFT 10 8176 8177 /* sc_x1_speed_override3 :: override_2 :: reserved1 [09:07] */ 8178 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_2_RESERVED1_MASK 0x0380 8179 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_2_RESERVED1_ALIGN 0 8180 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_2_RESERVED1_BITS 3 8181 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_2_RESERVED1_SHIFT 7 8182 8183 /* sc_x1_speed_override3 :: override_2 :: block_sync_mode [06:04] */ 8184 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_2_BLOCK_SYNC_MODE_MASK 0x0070 8185 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_2_BLOCK_SYNC_MODE_ALIGN 0 8186 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_2_BLOCK_SYNC_MODE_BITS 3 8187 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_2_BLOCK_SYNC_MODE_SHIFT 4 8188 8189 /* sc_x1_speed_override3 :: override_2 :: reserved2 [03:02] */ 8190 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_2_RESERVED2_MASK 0x000c 8191 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_2_RESERVED2_ALIGN 0 8192 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_2_RESERVED2_BITS 2 8193 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_2_RESERVED2_SHIFT 2 8194 8195 /* sc_x1_speed_override3 :: override_2 :: reorder_en [01:01] */ 8196 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_2_REORDER_EN_MASK 0x0002 8197 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_2_REORDER_EN_ALIGN 0 8198 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_2_REORDER_EN_BITS 1 8199 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_2_REORDER_EN_SHIFT 1 8200 8201 /* sc_x1_speed_override3 :: override_2 :: cl36_en [00:00] */ 8202 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_2_CL36_EN_MASK 0x0001 8203 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_2_CL36_EN_ALIGN 0 8204 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_2_CL36_EN_BITS 1 8205 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_2_CL36_EN_SHIFT 0 8206 8207 8208 /**************************************************************************** 8209 * sc_x1_speed_override3 :: override_3 8210 */ 8211 /* sc_x1_speed_override3 :: override_3 :: sgmii_spd_switch [15:15] */ 8212 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_3_SGMII_SPD_SWITCH_MASK 0x8000 8213 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_3_SGMII_SPD_SWITCH_ALIGN 0 8214 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_3_SGMII_SPD_SWITCH_BITS 1 8215 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_3_SGMII_SPD_SWITCH_SHIFT 15 8216 8217 /* sc_x1_speed_override3 :: override_3 :: reserved0 [14:14] */ 8218 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_3_RESERVED0_MASK 0x4000 8219 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_3_RESERVED0_ALIGN 0 8220 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_3_RESERVED0_BITS 1 8221 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_3_RESERVED0_SHIFT 14 8222 8223 /* sc_x1_speed_override3 :: override_3 :: clockcnt0 [13:00] */ 8224 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_3_CLOCKCNT0_MASK 0x3fff 8225 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_3_CLOCKCNT0_ALIGN 0 8226 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_3_CLOCKCNT0_BITS 14 8227 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_3_CLOCKCNT0_SHIFT 0 8228 8229 8230 /**************************************************************************** 8231 * sc_x1_speed_override3 :: override_4 8232 */ 8233 /* sc_x1_speed_override3 :: override_4 :: reserved0 [15:08] */ 8234 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_4_RESERVED0_MASK 0xff00 8235 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_4_RESERVED0_ALIGN 0 8236 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_4_RESERVED0_BITS 8 8237 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_4_RESERVED0_SHIFT 8 8238 8239 /* sc_x1_speed_override3 :: override_4 :: clockcnt1 [07:00] */ 8240 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_4_CLOCKCNT1_MASK 0x00ff 8241 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_4_CLOCKCNT1_ALIGN 0 8242 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_4_CLOCKCNT1_BITS 8 8243 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_4_CLOCKCNT1_SHIFT 0 8244 8245 8246 /**************************************************************************** 8247 * sc_x1_speed_override3 :: override_5 8248 */ 8249 /* sc_x1_speed_override3 :: override_5 :: reserved0 [15:14] */ 8250 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_5_RESERVED0_MASK 0xc000 8251 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_5_RESERVED0_ALIGN 0 8252 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_5_RESERVED0_BITS 2 8253 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_5_RESERVED0_SHIFT 14 8254 8255 /* sc_x1_speed_override3 :: override_5 :: loopcnt0 [13:06] */ 8256 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_5_LOOPCNT0_MASK 0x3fc0 8257 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_5_LOOPCNT0_ALIGN 0 8258 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_5_LOOPCNT0_BITS 8 8259 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_5_LOOPCNT0_SHIFT 6 8260 8261 /* sc_x1_speed_override3 :: override_5 :: loopcnt1 [05:00] */ 8262 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_5_LOOPCNT1_MASK 0x003f 8263 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_5_LOOPCNT1_ALIGN 0 8264 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_5_LOOPCNT1_BITS 6 8265 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_5_LOOPCNT1_SHIFT 0 8266 8267 8268 /**************************************************************************** 8269 * sc_x1_speed_override3 :: override_6 8270 */ 8271 /* sc_x1_speed_override3 :: override_6 :: reserved0 [15:13] */ 8272 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_6_RESERVED0_MASK 0xe000 8273 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_6_RESERVED0_ALIGN 0 8274 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_6_RESERVED0_BITS 3 8275 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_6_RESERVED0_SHIFT 13 8276 8277 /* sc_x1_speed_override3 :: override_6 :: mac_creditgencnt [12:00] */ 8278 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_6_MAC_CREDITGENCNT_MASK 0x1fff 8279 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_6_MAC_CREDITGENCNT_ALIGN 0 8280 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_6_MAC_CREDITGENCNT_BITS 13 8281 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_6_MAC_CREDITGENCNT_SHIFT 0 8282 8283 8284 /**************************************************************************** 8285 * sc_x1_speed_override3 :: override_7 8286 */ 8287 /* sc_x1_speed_override3 :: override_7 :: replication_cnt [15:15] */ 8288 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_REPLICATION_CNT_MASK 0x8000 8289 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_REPLICATION_CNT_ALIGN 0 8290 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_REPLICATION_CNT_BITS 1 8291 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_REPLICATION_CNT_SHIFT 15 8292 8293 /* sc_x1_speed_override3 :: override_7 :: pcs_creditenable [14:14] */ 8294 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_PCS_CREDITENABLE_MASK 0x4000 8295 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_PCS_CREDITENABLE_ALIGN 0 8296 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_PCS_CREDITENABLE_BITS 1 8297 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_PCS_CREDITENABLE_SHIFT 14 8298 8299 /* sc_x1_speed_override3 :: override_7 :: pcs_clockcnt0 [13:00] */ 8300 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_PCS_CLOCKCNT0_MASK 0x3fff 8301 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_PCS_CLOCKCNT0_ALIGN 0 8302 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_PCS_CLOCKCNT0_BITS 14 8303 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_7_PCS_CLOCKCNT0_SHIFT 0 8304 8305 8306 /**************************************************************************** 8307 * sc_x1_speed_override3 :: override_8 8308 */ 8309 /* sc_x1_speed_override3 :: override_8 :: reserved0 [15:13] */ 8310 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_8_RESERVED0_MASK 0xe000 8311 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_8_RESERVED0_ALIGN 0 8312 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_8_RESERVED0_BITS 3 8313 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_8_RESERVED0_SHIFT 13 8314 8315 /* sc_x1_speed_override3 :: override_8 :: pcs_creditgencnt [12:00] */ 8316 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_8_PCS_CREDITGENCNT_MASK 0x1fff 8317 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_8_PCS_CREDITGENCNT_ALIGN 0 8318 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_8_PCS_CREDITGENCNT_BITS 13 8319 #define SC_X1_SPEED_OVERRIDE3_OVERRIDE_8_PCS_CREDITGENCNT_SHIFT 0 8320 8321 8322 /**************************************************************************** 8323 * TSCE_TSCE_USER2_TX_X2_Control0 8324 */ 8325 /**************************************************************************** 8326 * TX_X2_Control0 :: MLD_swap_count 8327 */ 8328 /* TX_X2_Control0 :: MLD_swap_count :: MLD_swap_count [15:00] */ 8329 #define TX_X2_CONTROL0_MLD_SWAP_COUNT_MLD_SWAP_COUNT_MASK 0xffff 8330 #define TX_X2_CONTROL0_MLD_SWAP_COUNT_MLD_SWAP_COUNT_ALIGN 0 8331 #define TX_X2_CONTROL0_MLD_SWAP_COUNT_MLD_SWAP_COUNT_BITS 16 8332 #define TX_X2_CONTROL0_MLD_SWAP_COUNT_MLD_SWAP_COUNT_SHIFT 0 8333 8334 8335 /**************************************************************************** 8336 * TX_X2_Control0 :: cl48_0 8337 */ 8338 /* TX_X2_Control0 :: cl48_0 :: BRCM_MODE_USE_K20PT5 [15:15] */ 8339 #define TX_X2_CONTROL0_CL48_0_BRCM_MODE_USE_K20PT5_MASK 0x8000 8340 #define TX_X2_CONTROL0_CL48_0_BRCM_MODE_USE_K20PT5_ALIGN 0 8341 #define TX_X2_CONTROL0_CL48_0_BRCM_MODE_USE_K20PT5_BITS 1 8342 #define TX_X2_CONTROL0_CL48_0_BRCM_MODE_USE_K20PT5_SHIFT 15 8343 8344 /* TX_X2_Control0 :: cl48_0 :: reserved0 [14:07] */ 8345 #define TX_X2_CONTROL0_CL48_0_RESERVED0_MASK 0x7f80 8346 #define TX_X2_CONTROL0_CL48_0_RESERVED0_ALIGN 0 8347 #define TX_X2_CONTROL0_CL48_0_RESERVED0_BITS 8 8348 #define TX_X2_CONTROL0_CL48_0_RESERVED0_SHIFT 7 8349 8350 /* TX_X2_Control0 :: cl48_0 :: cl48_tx_li_enable [06:06] */ 8351 #define TX_X2_CONTROL0_CL48_0_CL48_TX_LI_ENABLE_MASK 0x0040 8352 #define TX_X2_CONTROL0_CL48_0_CL48_TX_LI_ENABLE_ALIGN 0 8353 #define TX_X2_CONTROL0_CL48_0_CL48_TX_LI_ENABLE_BITS 1 8354 #define TX_X2_CONTROL0_CL48_0_CL48_TX_LI_ENABLE_SHIFT 6 8355 8356 /* TX_X2_Control0 :: cl48_0 :: cl48_tx_lf_enable [05:05] */ 8357 #define TX_X2_CONTROL0_CL48_0_CL48_TX_LF_ENABLE_MASK 0x0020 8358 #define TX_X2_CONTROL0_CL48_0_CL48_TX_LF_ENABLE_ALIGN 0 8359 #define TX_X2_CONTROL0_CL48_0_CL48_TX_LF_ENABLE_BITS 1 8360 #define TX_X2_CONTROL0_CL48_0_CL48_TX_LF_ENABLE_SHIFT 5 8361 8362 /* TX_X2_Control0 :: cl48_0 :: cl48_tx_rf_enable [04:04] */ 8363 #define TX_X2_CONTROL0_CL48_0_CL48_TX_RF_ENABLE_MASK 0x0010 8364 #define TX_X2_CONTROL0_CL48_0_CL48_TX_RF_ENABLE_ALIGN 0 8365 #define TX_X2_CONTROL0_CL48_0_CL48_TX_RF_ENABLE_BITS 1 8366 #define TX_X2_CONTROL0_CL48_0_CL48_TX_RF_ENABLE_SHIFT 4 8367 8368 /* TX_X2_Control0 :: cl48_0 :: cl48_tx_QrsvdCtrl [03:00] */ 8369 #define TX_X2_CONTROL0_CL48_0_CL48_TX_QRSVDCTRL_MASK 0x000f 8370 #define TX_X2_CONTROL0_CL48_0_CL48_TX_QRSVDCTRL_ALIGN 0 8371 #define TX_X2_CONTROL0_CL48_0_CL48_TX_QRSVDCTRL_BITS 4 8372 #define TX_X2_CONTROL0_CL48_0_CL48_TX_QRSVDCTRL_SHIFT 0 8373 8374 8375 /**************************************************************************** 8376 * TX_X2_Control0 :: cl82_0 8377 */ 8378 /* TX_X2_Control0 :: cl82_0 :: reserved0 [15:11] */ 8379 #define TX_X2_CONTROL0_CL82_0_RESERVED0_MASK 0xf800 8380 #define TX_X2_CONTROL0_CL82_0_RESERVED0_ALIGN 0 8381 #define TX_X2_CONTROL0_CL82_0_RESERVED0_BITS 5 8382 #define TX_X2_CONTROL0_CL82_0_RESERVED0_SHIFT 11 8383 8384 /* TX_X2_Control0 :: cl82_0 :: cl82_bypass_txsm [10:10] */ 8385 #define TX_X2_CONTROL0_CL82_0_CL82_BYPASS_TXSM_MASK 0x0400 8386 #define TX_X2_CONTROL0_CL82_0_CL82_BYPASS_TXSM_ALIGN 0 8387 #define TX_X2_CONTROL0_CL82_0_CL82_BYPASS_TXSM_BITS 1 8388 #define TX_X2_CONTROL0_CL82_0_CL82_BYPASS_TXSM_SHIFT 10 8389 8390 /* TX_X2_Control0 :: cl82_0 :: reserved1 [09:07] */ 8391 #define TX_X2_CONTROL0_CL82_0_RESERVED1_MASK 0x0380 8392 #define TX_X2_CONTROL0_CL82_0_RESERVED1_ALIGN 0 8393 #define TX_X2_CONTROL0_CL82_0_RESERVED1_BITS 3 8394 #define TX_X2_CONTROL0_CL82_0_RESERVED1_SHIFT 7 8395 8396 /* TX_X2_Control0 :: cl82_0 :: cl82_tx_li_enable [06:06] */ 8397 #define TX_X2_CONTROL0_CL82_0_CL82_TX_LI_ENABLE_MASK 0x0040 8398 #define TX_X2_CONTROL0_CL82_0_CL82_TX_LI_ENABLE_ALIGN 0 8399 #define TX_X2_CONTROL0_CL82_0_CL82_TX_LI_ENABLE_BITS 1 8400 #define TX_X2_CONTROL0_CL82_0_CL82_TX_LI_ENABLE_SHIFT 6 8401 8402 /* TX_X2_Control0 :: cl82_0 :: cl82_tx_lf_enable [05:05] */ 8403 #define TX_X2_CONTROL0_CL82_0_CL82_TX_LF_ENABLE_MASK 0x0020 8404 #define TX_X2_CONTROL0_CL82_0_CL82_TX_LF_ENABLE_ALIGN 0 8405 #define TX_X2_CONTROL0_CL82_0_CL82_TX_LF_ENABLE_BITS 1 8406 #define TX_X2_CONTROL0_CL82_0_CL82_TX_LF_ENABLE_SHIFT 5 8407 8408 /* TX_X2_Control0 :: cl82_0 :: cl82_tx_rf_enable [04:04] */ 8409 #define TX_X2_CONTROL0_CL82_0_CL82_TX_RF_ENABLE_MASK 0x0010 8410 #define TX_X2_CONTROL0_CL82_0_CL82_TX_RF_ENABLE_ALIGN 0 8411 #define TX_X2_CONTROL0_CL82_0_CL82_TX_RF_ENABLE_BITS 1 8412 #define TX_X2_CONTROL0_CL82_0_CL82_TX_RF_ENABLE_SHIFT 4 8413 8414 /* TX_X2_Control0 :: cl82_0 :: reserved2 [03:00] */ 8415 #define TX_X2_CONTROL0_CL82_0_RESERVED2_MASK 0x000f 8416 #define TX_X2_CONTROL0_CL82_0_RESERVED2_ALIGN 0 8417 #define TX_X2_CONTROL0_CL82_0_RESERVED2_BITS 4 8418 #define TX_X2_CONTROL0_CL82_0_RESERVED2_SHIFT 0 8419 8420 8421 /**************************************************************************** 8422 * TX_X2_Control0 :: brcm_mode 8423 */ 8424 /* TX_X2_Control0 :: brcm_mode :: reserved0 [15:08] */ 8425 #define TX_X2_CONTROL0_BRCM_MODE_RESERVED0_MASK 0xff00 8426 #define TX_X2_CONTROL0_BRCM_MODE_RESERVED0_ALIGN 0 8427 #define TX_X2_CONTROL0_BRCM_MODE_RESERVED0_BITS 8 8428 #define TX_X2_CONTROL0_BRCM_MODE_RESERVED0_SHIFT 8 8429 8430 /* TX_X2_Control0 :: brcm_mode :: acol_swap_count64B66B [07:00] */ 8431 #define TX_X2_CONTROL0_BRCM_MODE_ACOL_SWAP_COUNT64B66B_MASK 0x00ff 8432 #define TX_X2_CONTROL0_BRCM_MODE_ACOL_SWAP_COUNT64B66B_ALIGN 0 8433 #define TX_X2_CONTROL0_BRCM_MODE_ACOL_SWAP_COUNT64B66B_BITS 8 8434 #define TX_X2_CONTROL0_BRCM_MODE_ACOL_SWAP_COUNT64B66B_SHIFT 0 8435 8436 8437 /**************************************************************************** 8438 * TSCE_TSCE_USER2_TX_X2_Status0 8439 */ 8440 /**************************************************************************** 8441 * TX_X2_Status0 :: cl82_tx_status_0 8442 */ 8443 /* TX_X2_Status0 :: cl82_tx_status_0 :: reserved0 [15:14] */ 8444 #define TX_X2_STATUS0_CL82_TX_STATUS_0_RESERVED0_MASK 0xc000 8445 #define TX_X2_STATUS0_CL82_TX_STATUS_0_RESERVED0_ALIGN 0 8446 #define TX_X2_STATUS0_CL82_TX_STATUS_0_RESERVED0_BITS 2 8447 #define TX_X2_STATUS0_CL82_TX_STATUS_0_RESERVED0_SHIFT 14 8448 8449 /* TX_X2_Status0 :: cl82_tx_status_0 :: cl82_idle_deletion_underflow [13:13] */ 8450 #define TX_X2_STATUS0_CL82_TX_STATUS_0_CL82_IDLE_DELETION_UNDERFLOW_MASK 0x2000 8451 #define TX_X2_STATUS0_CL82_TX_STATUS_0_CL82_IDLE_DELETION_UNDERFLOW_ALIGN 0 8452 #define TX_X2_STATUS0_CL82_TX_STATUS_0_CL82_IDLE_DELETION_UNDERFLOW_BITS 1 8453 #define TX_X2_STATUS0_CL82_TX_STATUS_0_CL82_IDLE_DELETION_UNDERFLOW_SHIFT 13 8454 8455 /* TX_X2_Status0 :: cl82_tx_status_0 :: t_type_coded [12:10] */ 8456 #define TX_X2_STATUS0_CL82_TX_STATUS_0_T_TYPE_CODED_MASK 0x1c00 8457 #define TX_X2_STATUS0_CL82_TX_STATUS_0_T_TYPE_CODED_ALIGN 0 8458 #define TX_X2_STATUS0_CL82_TX_STATUS_0_T_TYPE_CODED_BITS 3 8459 #define TX_X2_STATUS0_CL82_TX_STATUS_0_T_TYPE_CODED_SHIFT 10 8460 8461 /* TX_X2_Status0 :: cl82_tx_status_0 :: ltxsm_state [09:03] */ 8462 #define TX_X2_STATUS0_CL82_TX_STATUS_0_LTXSM_STATE_MASK 0x03f8 8463 #define TX_X2_STATUS0_CL82_TX_STATUS_0_LTXSM_STATE_ALIGN 0 8464 #define TX_X2_STATUS0_CL82_TX_STATUS_0_LTXSM_STATE_BITS 7 8465 #define TX_X2_STATUS0_CL82_TX_STATUS_0_LTXSM_STATE_SHIFT 3 8466 8467 /* TX_X2_Status0 :: cl82_tx_status_0 :: txsm_state [02:00] */ 8468 #define TX_X2_STATUS0_CL82_TX_STATUS_0_TXSM_STATE_MASK 0x0007 8469 #define TX_X2_STATUS0_CL82_TX_STATUS_0_TXSM_STATE_ALIGN 0 8470 #define TX_X2_STATUS0_CL82_TX_STATUS_0_TXSM_STATE_BITS 3 8471 #define TX_X2_STATUS0_CL82_TX_STATUS_0_TXSM_STATE_SHIFT 0 8472 8473 8474 /**************************************************************************** 8475 * TSCE_TSCE_USER2_RX_X2_Control0 8476 */ 8477 /**************************************************************************** 8478 * RX_X2_Control0 :: qrsvd_0 8479 */ 8480 /* RX_X2_Control0 :: qrsvd_0 :: reserved0 [15:15] */ 8481 #define RX_X2_CONTROL0_QRSVD_0_RESERVED0_MASK 0x8000 8482 #define RX_X2_CONTROL0_QRSVD_0_RESERVED0_ALIGN 0 8483 #define RX_X2_CONTROL0_QRSVD_0_RESERVED0_BITS 1 8484 #define RX_X2_CONTROL0_QRSVD_0_RESERVED0_SHIFT 15 8485 8486 /* RX_X2_Control0 :: qrsvd_0 :: QrsvdSwap [14:05] */ 8487 #define RX_X2_CONTROL0_QRSVD_0_QRSVDSWAP_MASK 0x7fe0 8488 #define RX_X2_CONTROL0_QRSVD_0_QRSVDSWAP_ALIGN 0 8489 #define RX_X2_CONTROL0_QRSVD_0_QRSVDSWAP_BITS 10 8490 #define RX_X2_CONTROL0_QRSVD_0_QRSVDSWAP_SHIFT 5 8491 8492 /* RX_X2_Control0 :: qrsvd_0 :: CL48_rx_QrsvdCtrl [04:01] */ 8493 #define RX_X2_CONTROL0_QRSVD_0_CL48_RX_QRSVDCTRL_MASK 0x001e 8494 #define RX_X2_CONTROL0_QRSVD_0_CL48_RX_QRSVDCTRL_ALIGN 0 8495 #define RX_X2_CONTROL0_QRSVD_0_CL48_RX_QRSVDCTRL_BITS 4 8496 #define RX_X2_CONTROL0_QRSVD_0_CL48_RX_QRSVDCTRL_SHIFT 1 8497 8498 /* RX_X2_Control0 :: qrsvd_0 :: reserved1 [00:00] */ 8499 #define RX_X2_CONTROL0_QRSVD_0_RESERVED1_MASK 0x0001 8500 #define RX_X2_CONTROL0_QRSVD_0_RESERVED1_ALIGN 0 8501 #define RX_X2_CONTROL0_QRSVD_0_RESERVED1_BITS 1 8502 #define RX_X2_CONTROL0_QRSVD_0_RESERVED1_SHIFT 0 8503 8504 8505 /**************************************************************************** 8506 * RX_X2_Control0 :: qrsvd_1 8507 */ 8508 /* RX_X2_Control0 :: qrsvd_1 :: Qrsvd1 [15:07] */ 8509 #define RX_X2_CONTROL0_QRSVD_1_QRSVD1_MASK 0xff80 8510 #define RX_X2_CONTROL0_QRSVD_1_QRSVD1_ALIGN 0 8511 #define RX_X2_CONTROL0_QRSVD_1_QRSVD1_BITS 9 8512 #define RX_X2_CONTROL0_QRSVD_1_QRSVD1_SHIFT 7 8513 8514 /* RX_X2_Control0 :: qrsvd_1 :: Qrsvd2_8_2 [06:00] */ 8515 #define RX_X2_CONTROL0_QRSVD_1_QRSVD2_8_2_MASK 0x007f 8516 #define RX_X2_CONTROL0_QRSVD_1_QRSVD2_8_2_ALIGN 0 8517 #define RX_X2_CONTROL0_QRSVD_1_QRSVD2_8_2_BITS 7 8518 #define RX_X2_CONTROL0_QRSVD_1_QRSVD2_8_2_SHIFT 0 8519 8520 8521 /**************************************************************************** 8522 * RX_X2_Control0 :: qrsvd_2 8523 */ 8524 /* RX_X2_Control0 :: qrsvd_2 :: Qrsvd2_1_0 [15:14] */ 8525 #define RX_X2_CONTROL0_QRSVD_2_QRSVD2_1_0_MASK 0xc000 8526 #define RX_X2_CONTROL0_QRSVD_2_QRSVD2_1_0_ALIGN 0 8527 #define RX_X2_CONTROL0_QRSVD_2_QRSVD2_1_0_BITS 2 8528 #define RX_X2_CONTROL0_QRSVD_2_QRSVD2_1_0_SHIFT 14 8529 8530 /* RX_X2_Control0 :: qrsvd_2 :: Qrsvd3 [13:05] */ 8531 #define RX_X2_CONTROL0_QRSVD_2_QRSVD3_MASK 0x3fe0 8532 #define RX_X2_CONTROL0_QRSVD_2_QRSVD3_ALIGN 0 8533 #define RX_X2_CONTROL0_QRSVD_2_QRSVD3_BITS 9 8534 #define RX_X2_CONTROL0_QRSVD_2_QRSVD3_SHIFT 5 8535 8536 /* RX_X2_Control0 :: qrsvd_2 :: reserved0 [04:00] */ 8537 #define RX_X2_CONTROL0_QRSVD_2_RESERVED0_MASK 0x001f 8538 #define RX_X2_CONTROL0_QRSVD_2_RESERVED0_ALIGN 0 8539 #define RX_X2_CONTROL0_QRSVD_2_RESERVED0_BITS 5 8540 #define RX_X2_CONTROL0_QRSVD_2_RESERVED0_SHIFT 0 8541 8542 8543 /**************************************************************************** 8544 * RX_X2_Control0 :: misc_0 8545 */ 8546 /* RX_X2_Control0 :: misc_0 :: reserved0 [15:13] */ 8547 #define RX_X2_CONTROL0_MISC_0_RESERVED0_MASK 0xe000 8548 #define RX_X2_CONTROL0_MISC_0_RESERVED0_ALIGN 0 8549 #define RX_X2_CONTROL0_MISC_0_RESERVED0_BITS 3 8550 #define RX_X2_CONTROL0_MISC_0_RESERVED0_SHIFT 13 8551 8552 /* RX_X2_Control0 :: misc_0 :: link_en [12:12] */ 8553 #define RX_X2_CONTROL0_MISC_0_LINK_EN_MASK 0x1000 8554 #define RX_X2_CONTROL0_MISC_0_LINK_EN_ALIGN 0 8555 #define RX_X2_CONTROL0_MISC_0_LINK_EN_BITS 1 8556 #define RX_X2_CONTROL0_MISC_0_LINK_EN_SHIFT 12 8557 8558 /* RX_X2_Control0 :: misc_0 :: reserved1 [11:11] */ 8559 #define RX_X2_CONTROL0_MISC_0_RESERVED1_MASK 0x0800 8560 #define RX_X2_CONTROL0_MISC_0_RESERVED1_ALIGN 0 8561 #define RX_X2_CONTROL0_MISC_0_RESERVED1_BITS 1 8562 #define RX_X2_CONTROL0_MISC_0_RESERVED1_SHIFT 11 8563 8564 /* RX_X2_Control0 :: misc_0 :: chk_end_en [10:10] */ 8565 #define RX_X2_CONTROL0_MISC_0_CHK_END_EN_MASK 0x0400 8566 #define RX_X2_CONTROL0_MISC_0_CHK_END_EN_ALIGN 0 8567 #define RX_X2_CONTROL0_MISC_0_CHK_END_EN_BITS 1 8568 #define RX_X2_CONTROL0_MISC_0_CHK_END_EN_SHIFT 10 8569 8570 /* RX_X2_Control0 :: misc_0 :: reserved2 [09:09] */ 8571 #define RX_X2_CONTROL0_MISC_0_RESERVED2_MASK 0x0200 8572 #define RX_X2_CONTROL0_MISC_0_RESERVED2_ALIGN 0 8573 #define RX_X2_CONTROL0_MISC_0_RESERVED2_BITS 1 8574 #define RX_X2_CONTROL0_MISC_0_RESERVED2_SHIFT 9 8575 8576 /* RX_X2_Control0 :: misc_0 :: brcm_mode_use_k20pt5 [08:08] */ 8577 #define RX_X2_CONTROL0_MISC_0_BRCM_MODE_USE_K20PT5_MASK 0x0100 8578 #define RX_X2_CONTROL0_MISC_0_BRCM_MODE_USE_K20PT5_ALIGN 0 8579 #define RX_X2_CONTROL0_MISC_0_BRCM_MODE_USE_K20PT5_BITS 1 8580 #define RX_X2_CONTROL0_MISC_0_BRCM_MODE_USE_K20PT5_SHIFT 8 8581 8582 /* RX_X2_Control0 :: misc_0 :: reserved3 [07:02] */ 8583 #define RX_X2_CONTROL0_MISC_0_RESERVED3_MASK 0x00fc 8584 #define RX_X2_CONTROL0_MISC_0_RESERVED3_ALIGN 0 8585 #define RX_X2_CONTROL0_MISC_0_RESERVED3_BITS 6 8586 #define RX_X2_CONTROL0_MISC_0_RESERVED3_SHIFT 2 8587 8588 /* RX_X2_Control0 :: misc_0 :: dis_cl82_bermon [01:01] */ 8589 #define RX_X2_CONTROL0_MISC_0_DIS_CL82_BERMON_MASK 0x0002 8590 #define RX_X2_CONTROL0_MISC_0_DIS_CL82_BERMON_ALIGN 0 8591 #define RX_X2_CONTROL0_MISC_0_DIS_CL82_BERMON_BITS 1 8592 #define RX_X2_CONTROL0_MISC_0_DIS_CL82_BERMON_SHIFT 1 8593 8594 /* RX_X2_Control0 :: misc_0 :: bypass_cl82rxsm [00:00] */ 8595 #define RX_X2_CONTROL0_MISC_0_BYPASS_CL82RXSM_MASK 0x0001 8596 #define RX_X2_CONTROL0_MISC_0_BYPASS_CL82RXSM_ALIGN 0 8597 #define RX_X2_CONTROL0_MISC_0_BYPASS_CL82RXSM_BITS 1 8598 #define RX_X2_CONTROL0_MISC_0_BYPASS_CL82RXSM_SHIFT 0 8599 8600 8601 /**************************************************************************** 8602 * RX_X2_Control0 :: misc_1 8603 */ 8604 /* RX_X2_Control0 :: misc_1 :: reserved0 [15:10] */ 8605 #define RX_X2_CONTROL0_MISC_1_RESERVED0_MASK 0xfc00 8606 #define RX_X2_CONTROL0_MISC_1_RESERVED0_ALIGN 0 8607 #define RX_X2_CONTROL0_MISC_1_RESERVED0_BITS 6 8608 #define RX_X2_CONTROL0_MISC_1_RESERVED0_SHIFT 10 8609 8610 /* RX_X2_Control0 :: misc_1 :: cl82_rx_li_enable [09:09] */ 8611 #define RX_X2_CONTROL0_MISC_1_CL82_RX_LI_ENABLE_MASK 0x0200 8612 #define RX_X2_CONTROL0_MISC_1_CL82_RX_LI_ENABLE_ALIGN 0 8613 #define RX_X2_CONTROL0_MISC_1_CL82_RX_LI_ENABLE_BITS 1 8614 #define RX_X2_CONTROL0_MISC_1_CL82_RX_LI_ENABLE_SHIFT 9 8615 8616 /* RX_X2_Control0 :: misc_1 :: cl48_rx_li_enable [08:08] */ 8617 #define RX_X2_CONTROL0_MISC_1_CL48_RX_LI_ENABLE_MASK 0x0100 8618 #define RX_X2_CONTROL0_MISC_1_CL48_RX_LI_ENABLE_ALIGN 0 8619 #define RX_X2_CONTROL0_MISC_1_CL48_RX_LI_ENABLE_BITS 1 8620 #define RX_X2_CONTROL0_MISC_1_CL48_RX_LI_ENABLE_SHIFT 8 8621 8622 /* RX_X2_Control0 :: misc_1 :: reserved1 [07:04] */ 8623 #define RX_X2_CONTROL0_MISC_1_RESERVED1_MASK 0x00f0 8624 #define RX_X2_CONTROL0_MISC_1_RESERVED1_ALIGN 0 8625 #define RX_X2_CONTROL0_MISC_1_RESERVED1_BITS 4 8626 #define RX_X2_CONTROL0_MISC_1_RESERVED1_SHIFT 4 8627 8628 /* RX_X2_Control0 :: misc_1 :: cl48_rx_lf_enable [03:03] */ 8629 #define RX_X2_CONTROL0_MISC_1_CL48_RX_LF_ENABLE_MASK 0x0008 8630 #define RX_X2_CONTROL0_MISC_1_CL48_RX_LF_ENABLE_ALIGN 0 8631 #define RX_X2_CONTROL0_MISC_1_CL48_RX_LF_ENABLE_BITS 1 8632 #define RX_X2_CONTROL0_MISC_1_CL48_RX_LF_ENABLE_SHIFT 3 8633 8634 /* RX_X2_Control0 :: misc_1 :: cl48_rx_rf_enable [02:02] */ 8635 #define RX_X2_CONTROL0_MISC_1_CL48_RX_RF_ENABLE_MASK 0x0004 8636 #define RX_X2_CONTROL0_MISC_1_CL48_RX_RF_ENABLE_ALIGN 0 8637 #define RX_X2_CONTROL0_MISC_1_CL48_RX_RF_ENABLE_BITS 1 8638 #define RX_X2_CONTROL0_MISC_1_CL48_RX_RF_ENABLE_SHIFT 2 8639 8640 /* RX_X2_Control0 :: misc_1 :: cl82_rx_lf_enable [01:01] */ 8641 #define RX_X2_CONTROL0_MISC_1_CL82_RX_LF_ENABLE_MASK 0x0002 8642 #define RX_X2_CONTROL0_MISC_1_CL82_RX_LF_ENABLE_ALIGN 0 8643 #define RX_X2_CONTROL0_MISC_1_CL82_RX_LF_ENABLE_BITS 1 8644 #define RX_X2_CONTROL0_MISC_1_CL82_RX_LF_ENABLE_SHIFT 1 8645 8646 /* RX_X2_Control0 :: misc_1 :: cl82_rx_rf_enable [00:00] */ 8647 #define RX_X2_CONTROL0_MISC_1_CL82_RX_RF_ENABLE_MASK 0x0001 8648 #define RX_X2_CONTROL0_MISC_1_CL82_RX_RF_ENABLE_ALIGN 0 8649 #define RX_X2_CONTROL0_MISC_1_CL82_RX_RF_ENABLE_BITS 1 8650 #define RX_X2_CONTROL0_MISC_1_CL82_RX_RF_ENABLE_SHIFT 0 8651 8652 8653 /**************************************************************************** 8654 * TSCE_TSCE_USER2_RX_X2_Status0 8655 */ 8656 /**************************************************************************** 8657 * RX_X2_Status0 :: skew_status_0 8658 */ 8659 /* RX_X2_Status0 :: skew_status_0 :: cl48_skew_status [15:15] */ 8660 #define RX_X2_STATUS0_SKEW_STATUS_0_CL48_SKEW_STATUS_MASK 0x8000 8661 #define RX_X2_STATUS0_SKEW_STATUS_0_CL48_SKEW_STATUS_ALIGN 0 8662 #define RX_X2_STATUS0_SKEW_STATUS_0_CL48_SKEW_STATUS_BITS 1 8663 #define RX_X2_STATUS0_SKEW_STATUS_0_CL48_SKEW_STATUS_SHIFT 15 8664 8665 /* RX_X2_Status0 :: skew_status_0 :: cl48_skewacq_state_d_0 [14:12] */ 8666 #define RX_X2_STATUS0_SKEW_STATUS_0_CL48_SKEWACQ_STATE_D_0_MASK 0x7000 8667 #define RX_X2_STATUS0_SKEW_STATUS_0_CL48_SKEWACQ_STATE_D_0_ALIGN 0 8668 #define RX_X2_STATUS0_SKEW_STATUS_0_CL48_SKEWACQ_STATE_D_0_BITS 3 8669 #define RX_X2_STATUS0_SKEW_STATUS_0_CL48_SKEWACQ_STATE_D_0_SHIFT 12 8670 8671 /* RX_X2_Status0 :: skew_status_0 :: cl48_skewacq_state_d_1 [11:09] */ 8672 #define RX_X2_STATUS0_SKEW_STATUS_0_CL48_SKEWACQ_STATE_D_1_MASK 0x0e00 8673 #define RX_X2_STATUS0_SKEW_STATUS_0_CL48_SKEWACQ_STATE_D_1_ALIGN 0 8674 #define RX_X2_STATUS0_SKEW_STATUS_0_CL48_SKEWACQ_STATE_D_1_BITS 3 8675 #define RX_X2_STATUS0_SKEW_STATUS_0_CL48_SKEWACQ_STATE_D_1_SHIFT 9 8676 8677 /* RX_X2_Status0 :: skew_status_0 :: cl48_skewacq_state_d_2 [08:06] */ 8678 #define RX_X2_STATUS0_SKEW_STATUS_0_CL48_SKEWACQ_STATE_D_2_MASK 0x01c0 8679 #define RX_X2_STATUS0_SKEW_STATUS_0_CL48_SKEWACQ_STATE_D_2_ALIGN 0 8680 #define RX_X2_STATUS0_SKEW_STATUS_0_CL48_SKEWACQ_STATE_D_2_BITS 3 8681 #define RX_X2_STATUS0_SKEW_STATUS_0_CL48_SKEWACQ_STATE_D_2_SHIFT 6 8682 8683 /* RX_X2_Status0 :: skew_status_0 :: cl48_skewacq_state_d_3 [05:03] */ 8684 #define RX_X2_STATUS0_SKEW_STATUS_0_CL48_SKEWACQ_STATE_D_3_MASK 0x0038 8685 #define RX_X2_STATUS0_SKEW_STATUS_0_CL48_SKEWACQ_STATE_D_3_ALIGN 0 8686 #define RX_X2_STATUS0_SKEW_STATUS_0_CL48_SKEWACQ_STATE_D_3_BITS 3 8687 #define RX_X2_STATUS0_SKEW_STATUS_0_CL48_SKEWACQ_STATE_D_3_SHIFT 3 8688 8689 /* RX_X2_Status0 :: skew_status_0 :: reserved0 [02:00] */ 8690 #define RX_X2_STATUS0_SKEW_STATUS_0_RESERVED0_MASK 0x0007 8691 #define RX_X2_STATUS0_SKEW_STATUS_0_RESERVED0_ALIGN 0 8692 #define RX_X2_STATUS0_SKEW_STATUS_0_RESERVED0_BITS 3 8693 #define RX_X2_STATUS0_SKEW_STATUS_0_RESERVED0_SHIFT 0 8694 8695 8696 /**************************************************************************** 8697 * RX_X2_Status0 :: skew_status_1 8698 */ 8699 /* RX_X2_Status0 :: skew_status_1 :: reserved0 [15:08] */ 8700 #define RX_X2_STATUS0_SKEW_STATUS_1_RESERVED0_MASK 0xff00 8701 #define RX_X2_STATUS0_SKEW_STATUS_1_RESERVED0_ALIGN 0 8702 #define RX_X2_STATUS0_SKEW_STATUS_1_RESERVED0_BITS 8 8703 #define RX_X2_STATUS0_SKEW_STATUS_1_RESERVED0_SHIFT 8 8704 8705 /* RX_X2_Status0 :: skew_status_1 :: cl48_skewacq_state_l [07:00] */ 8706 #define RX_X2_STATUS0_SKEW_STATUS_1_CL48_SKEWACQ_STATE_L_MASK 0x00ff 8707 #define RX_X2_STATUS0_SKEW_STATUS_1_CL48_SKEWACQ_STATE_L_ALIGN 0 8708 #define RX_X2_STATUS0_SKEW_STATUS_1_CL48_SKEWACQ_STATE_L_BITS 8 8709 #define RX_X2_STATUS0_SKEW_STATUS_1_CL48_SKEWACQ_STATE_L_SHIFT 0 8710 8711 8712 /**************************************************************************** 8713 * TSCE_TSCE_USER2_CL82 8714 */ 8715 /**************************************************************************** 8716 * CL82 :: rx_decoder_status 8717 */ 8718 /* CL82 :: rx_decoder_status :: reserved0 [15:13] */ 8719 #define CL82_RX_DECODER_STATUS_RESERVED0_MASK 0xe000 8720 #define CL82_RX_DECODER_STATUS_RESERVED0_ALIGN 0 8721 #define CL82_RX_DECODER_STATUS_RESERVED0_BITS 3 8722 #define CL82_RX_DECODER_STATUS_RESERVED0_SHIFT 13 8723 8724 /* CL82 :: rx_decoder_status :: r_type_coded [12:07] */ 8725 #define CL82_RX_DECODER_STATUS_R_TYPE_CODED_MASK 0x1f80 8726 #define CL82_RX_DECODER_STATUS_R_TYPE_CODED_ALIGN 0 8727 #define CL82_RX_DECODER_STATUS_R_TYPE_CODED_BITS 6 8728 #define CL82_RX_DECODER_STATUS_R_TYPE_CODED_SHIFT 7 8729 8730 /* CL82 :: rx_decoder_status :: rxsm_state [06:00] */ 8731 #define CL82_RX_DECODER_STATUS_RXSM_STATE_MASK 0x007f 8732 #define CL82_RX_DECODER_STATUS_RXSM_STATE_ALIGN 0 8733 #define CL82_RX_DECODER_STATUS_RXSM_STATE_BITS 7 8734 #define CL82_RX_DECODER_STATUS_RXSM_STATE_SHIFT 0 8735 8736 8737 /**************************************************************************** 8738 * CL82 :: rx_deskew_ber_status 8739 */ 8740 /* CL82 :: rx_deskew_ber_status :: deskew_state [15:14] */ 8741 #define CL82_RX_DESKEW_BER_STATUS_DESKEW_STATE_MASK 0xc000 8742 #define CL82_RX_DESKEW_BER_STATUS_DESKEW_STATE_ALIGN 0 8743 #define CL82_RX_DESKEW_BER_STATUS_DESKEW_STATE_BITS 2 8744 #define CL82_RX_DESKEW_BER_STATUS_DESKEW_STATE_SHIFT 14 8745 8746 /* CL82 :: rx_deskew_ber_status :: deskew_his_state [13:12] */ 8747 #define CL82_RX_DESKEW_BER_STATUS_DESKEW_HIS_STATE_MASK 0x3000 8748 #define CL82_RX_DESKEW_BER_STATUS_DESKEW_HIS_STATE_ALIGN 0 8749 #define CL82_RX_DESKEW_BER_STATUS_DESKEW_HIS_STATE_BITS 2 8750 #define CL82_RX_DESKEW_BER_STATUS_DESKEW_HIS_STATE_SHIFT 12 8751 8752 /* CL82 :: rx_deskew_ber_status :: reserved0 [11:11] */ 8753 #define CL82_RX_DESKEW_BER_STATUS_RESERVED0_MASK 0x0800 8754 #define CL82_RX_DESKEW_BER_STATUS_RESERVED0_ALIGN 0 8755 #define CL82_RX_DESKEW_BER_STATUS_RESERVED0_BITS 1 8756 #define CL82_RX_DESKEW_BER_STATUS_RESERVED0_SHIFT 11 8757 8758 /* CL82 :: rx_deskew_ber_status :: lbermon_state [10:06] */ 8759 #define CL82_RX_DESKEW_BER_STATUS_LBERMON_STATE_MASK 0x07c0 8760 #define CL82_RX_DESKEW_BER_STATUS_LBERMON_STATE_ALIGN 0 8761 #define CL82_RX_DESKEW_BER_STATUS_LBERMON_STATE_BITS 5 8762 #define CL82_RX_DESKEW_BER_STATUS_LBERMON_STATE_SHIFT 6 8763 8764 /* CL82 :: rx_deskew_ber_status :: reserved1 [05:05] */ 8765 #define CL82_RX_DESKEW_BER_STATUS_RESERVED1_MASK 0x0020 8766 #define CL82_RX_DESKEW_BER_STATUS_RESERVED1_ALIGN 0 8767 #define CL82_RX_DESKEW_BER_STATUS_RESERVED1_BITS 1 8768 #define CL82_RX_DESKEW_BER_STATUS_RESERVED1_SHIFT 5 8769 8770 /* CL82 :: rx_deskew_ber_status :: bermon_state [04:00] */ 8771 #define CL82_RX_DESKEW_BER_STATUS_BERMON_STATE_MASK 0x001f 8772 #define CL82_RX_DESKEW_BER_STATUS_BERMON_STATE_ALIGN 0 8773 #define CL82_RX_DESKEW_BER_STATUS_BERMON_STATE_BITS 5 8774 #define CL82_RX_DESKEW_BER_STATUS_BERMON_STATE_SHIFT 0 8775 8776 8777 /**************************************************************************** 8778 * CL82 :: ber_ho_status 8779 */ 8780 /* CL82 :: ber_ho_status :: ber_ho [15:00] */ 8781 #define CL82_BER_HO_STATUS_BER_HO_MASK 0xffff 8782 #define CL82_BER_HO_STATUS_BER_HO_ALIGN 0 8783 #define CL82_BER_HO_STATUS_BER_HO_BITS 16 8784 #define CL82_BER_HO_STATUS_BER_HO_SHIFT 0 8785 8786 8787 /**************************************************************************** 8788 * CL82 :: PCS_errored_blocks_ho 8789 */ 8790 /* CL82 :: PCS_errored_blocks_ho :: errored_blocks_ho_present [15:15] */ 8791 #define CL82_PCS_ERRORED_BLOCKS_HO_ERRORED_BLOCKS_HO_PRESENT_MASK 0x8000 8792 #define CL82_PCS_ERRORED_BLOCKS_HO_ERRORED_BLOCKS_HO_PRESENT_ALIGN 0 8793 #define CL82_PCS_ERRORED_BLOCKS_HO_ERRORED_BLOCKS_HO_PRESENT_BITS 1 8794 #define CL82_PCS_ERRORED_BLOCKS_HO_ERRORED_BLOCKS_HO_PRESENT_SHIFT 15 8795 8796 /* CL82 :: PCS_errored_blocks_ho :: reserved0 [14:14] */ 8797 #define CL82_PCS_ERRORED_BLOCKS_HO_RESERVED0_MASK 0x4000 8798 #define CL82_PCS_ERRORED_BLOCKS_HO_RESERVED0_ALIGN 0 8799 #define CL82_PCS_ERRORED_BLOCKS_HO_RESERVED0_BITS 1 8800 #define CL82_PCS_ERRORED_BLOCKS_HO_RESERVED0_SHIFT 14 8801 8802 /* CL82 :: PCS_errored_blocks_ho :: errored_blocks_ho [13:00] */ 8803 #define CL82_PCS_ERRORED_BLOCKS_HO_ERRORED_BLOCKS_HO_MASK 0x3fff 8804 #define CL82_PCS_ERRORED_BLOCKS_HO_ERRORED_BLOCKS_HO_ALIGN 0 8805 #define CL82_PCS_ERRORED_BLOCKS_HO_ERRORED_BLOCKS_HO_BITS 14 8806 #define CL82_PCS_ERRORED_BLOCKS_HO_ERRORED_BLOCKS_HO_SHIFT 0 8807 8808 8809 /**************************************************************************** 8810 * TSCE_TSCE_USER4_pmd_x4 8811 */ 8812 /**************************************************************************** 8813 * pmd_x4 :: control 8814 */ 8815 /* pmd_x4 :: control :: reserved0 [15:14] */ 8816 #define PMD_X4_CONTROL_RESERVED0_MASK 0xc000 8817 #define PMD_X4_CONTROL_RESERVED0_ALIGN 0 8818 #define PMD_X4_CONTROL_RESERVED0_BITS 2 8819 #define PMD_X4_CONTROL_RESERVED0_SHIFT 14 8820 8821 /* pmd_x4 :: control :: rx_dme_en [13:13] */ 8822 #define PMD_X4_CONTROL_RX_DME_EN_MASK 0x2000 8823 #define PMD_X4_CONTROL_RX_DME_EN_ALIGN 0 8824 #define PMD_X4_CONTROL_RX_DME_EN_BITS 1 8825 #define PMD_X4_CONTROL_RX_DME_EN_SHIFT 13 8826 8827 /* pmd_x4 :: control :: osr_mode [12:09] */ 8828 #define PMD_X4_CONTROL_OSR_MODE_MASK 0x1e00 8829 #define PMD_X4_CONTROL_OSR_MODE_ALIGN 0 8830 #define PMD_X4_CONTROL_OSR_MODE_BITS 4 8831 #define PMD_X4_CONTROL_OSR_MODE_SHIFT 9 8832 8833 /* pmd_x4 :: control :: tx_disable [08:08] */ 8834 #define PMD_X4_CONTROL_TX_DISABLE_MASK 0x0100 8835 #define PMD_X4_CONTROL_TX_DISABLE_ALIGN 0 8836 #define PMD_X4_CONTROL_TX_DISABLE_BITS 1 8837 #define PMD_X4_CONTROL_TX_DISABLE_SHIFT 8 8838 8839 /* pmd_x4 :: control :: reserved1 [07:04] */ 8840 #define PMD_X4_CONTROL_RESERVED1_MASK 0x00f0 8841 #define PMD_X4_CONTROL_RESERVED1_ALIGN 0 8842 #define PMD_X4_CONTROL_RESERVED1_BITS 4 8843 #define PMD_X4_CONTROL_RESERVED1_SHIFT 4 8844 8845 /* pmd_x4 :: control :: ln_rx_h_pwrdn [03:03] */ 8846 #define PMD_X4_CONTROL_LN_RX_H_PWRDN_MASK 0x0008 8847 #define PMD_X4_CONTROL_LN_RX_H_PWRDN_ALIGN 0 8848 #define PMD_X4_CONTROL_LN_RX_H_PWRDN_BITS 1 8849 #define PMD_X4_CONTROL_LN_RX_H_PWRDN_SHIFT 3 8850 8851 /* pmd_x4 :: control :: ln_tx_h_pwrdn [02:02] */ 8852 #define PMD_X4_CONTROL_LN_TX_H_PWRDN_MASK 0x0004 8853 #define PMD_X4_CONTROL_LN_TX_H_PWRDN_ALIGN 0 8854 #define PMD_X4_CONTROL_LN_TX_H_PWRDN_BITS 1 8855 #define PMD_X4_CONTROL_LN_TX_H_PWRDN_SHIFT 2 8856 8857 /* pmd_x4 :: control :: ln_h_rstb [01:01] */ 8858 #define PMD_X4_CONTROL_LN_H_RSTB_MASK 0x0002 8859 #define PMD_X4_CONTROL_LN_H_RSTB_ALIGN 0 8860 #define PMD_X4_CONTROL_LN_H_RSTB_BITS 1 8861 #define PMD_X4_CONTROL_LN_H_RSTB_SHIFT 1 8862 8863 /* pmd_x4 :: control :: ln_dp_h_rstb [00:00] */ 8864 #define PMD_X4_CONTROL_LN_DP_H_RSTB_MASK 0x0001 8865 #define PMD_X4_CONTROL_LN_DP_H_RSTB_ALIGN 0 8866 #define PMD_X4_CONTROL_LN_DP_H_RSTB_BITS 1 8867 #define PMD_X4_CONTROL_LN_DP_H_RSTB_SHIFT 0 8868 8869 8870 /**************************************************************************** 8871 * pmd_x4 :: mode 8872 */ 8873 /* pmd_x4 :: mode :: lane_mode [15:00] */ 8874 #define PMD_X4_MODE_LANE_MODE_MASK 0xffff 8875 #define PMD_X4_MODE_LANE_MODE_ALIGN 0 8876 #define PMD_X4_MODE_LANE_MODE_BITS 16 8877 #define PMD_X4_MODE_LANE_MODE_SHIFT 0 8878 8879 8880 /**************************************************************************** 8881 * pmd_x4 :: status 8882 */ 8883 /* pmd_x4 :: status :: reserved0 [15:03] */ 8884 #define PMD_X4_STATUS_RESERVED0_MASK 0xfff8 8885 #define PMD_X4_STATUS_RESERVED0_ALIGN 0 8886 #define PMD_X4_STATUS_RESERVED0_BITS 13 8887 #define PMD_X4_STATUS_RESERVED0_SHIFT 3 8888 8889 /* pmd_x4 :: status :: rx_clk_vld_sts [02:02] */ 8890 #define PMD_X4_STATUS_RX_CLK_VLD_STS_MASK 0x0004 8891 #define PMD_X4_STATUS_RX_CLK_VLD_STS_ALIGN 0 8892 #define PMD_X4_STATUS_RX_CLK_VLD_STS_BITS 1 8893 #define PMD_X4_STATUS_RX_CLK_VLD_STS_SHIFT 2 8894 8895 /* pmd_x4 :: status :: signal_detect_sts [01:01] */ 8896 #define PMD_X4_STATUS_SIGNAL_DETECT_STS_MASK 0x0002 8897 #define PMD_X4_STATUS_SIGNAL_DETECT_STS_ALIGN 0 8898 #define PMD_X4_STATUS_SIGNAL_DETECT_STS_BITS 1 8899 #define PMD_X4_STATUS_SIGNAL_DETECT_STS_SHIFT 1 8900 8901 /* pmd_x4 :: status :: rx_lock_sts [00:00] */ 8902 #define PMD_X4_STATUS_RX_LOCK_STS_MASK 0x0001 8903 #define PMD_X4_STATUS_RX_LOCK_STS_ALIGN 0 8904 #define PMD_X4_STATUS_RX_LOCK_STS_BITS 1 8905 #define PMD_X4_STATUS_RX_LOCK_STS_SHIFT 0 8906 8907 8908 /**************************************************************************** 8909 * pmd_x4 :: latch_status 8910 */ 8911 /* pmd_x4 :: latch_status :: reserved0 [15:06] */ 8912 #define PMD_X4_LATCH_STATUS_RESERVED0_MASK 0xffc0 8913 #define PMD_X4_LATCH_STATUS_RESERVED0_ALIGN 0 8914 #define PMD_X4_LATCH_STATUS_RESERVED0_BITS 10 8915 #define PMD_X4_LATCH_STATUS_RESERVED0_SHIFT 6 8916 8917 /* pmd_x4 :: latch_status :: rx_clk_vld_LH [05:05] */ 8918 #define PMD_X4_LATCH_STATUS_RX_CLK_VLD_LH_MASK 0x0020 8919 #define PMD_X4_LATCH_STATUS_RX_CLK_VLD_LH_ALIGN 0 8920 #define PMD_X4_LATCH_STATUS_RX_CLK_VLD_LH_BITS 1 8921 #define PMD_X4_LATCH_STATUS_RX_CLK_VLD_LH_SHIFT 5 8922 8923 /* pmd_x4 :: latch_status :: rx_clk_vld_LL [04:04] */ 8924 #define PMD_X4_LATCH_STATUS_RX_CLK_VLD_LL_MASK 0x0010 8925 #define PMD_X4_LATCH_STATUS_RX_CLK_VLD_LL_ALIGN 0 8926 #define PMD_X4_LATCH_STATUS_RX_CLK_VLD_LL_BITS 1 8927 #define PMD_X4_LATCH_STATUS_RX_CLK_VLD_LL_SHIFT 4 8928 8929 /* pmd_x4 :: latch_status :: signal_detect_LH [03:03] */ 8930 #define PMD_X4_LATCH_STATUS_SIGNAL_DETECT_LH_MASK 0x0008 8931 #define PMD_X4_LATCH_STATUS_SIGNAL_DETECT_LH_ALIGN 0 8932 #define PMD_X4_LATCH_STATUS_SIGNAL_DETECT_LH_BITS 1 8933 #define PMD_X4_LATCH_STATUS_SIGNAL_DETECT_LH_SHIFT 3 8934 8935 /* pmd_x4 :: latch_status :: signal_detect_LL [02:02] */ 8936 #define PMD_X4_LATCH_STATUS_SIGNAL_DETECT_LL_MASK 0x0004 8937 #define PMD_X4_LATCH_STATUS_SIGNAL_DETECT_LL_ALIGN 0 8938 #define PMD_X4_LATCH_STATUS_SIGNAL_DETECT_LL_BITS 1 8939 #define PMD_X4_LATCH_STATUS_SIGNAL_DETECT_LL_SHIFT 2 8940 8941 /* pmd_x4 :: latch_status :: rx_lock_LH [01:01] */ 8942 #define PMD_X4_LATCH_STATUS_RX_LOCK_LH_MASK 0x0002 8943 #define PMD_X4_LATCH_STATUS_RX_LOCK_LH_ALIGN 0 8944 #define PMD_X4_LATCH_STATUS_RX_LOCK_LH_BITS 1 8945 #define PMD_X4_LATCH_STATUS_RX_LOCK_LH_SHIFT 1 8946 8947 /* pmd_x4 :: latch_status :: rx_lock_LL [00:00] */ 8948 #define PMD_X4_LATCH_STATUS_RX_LOCK_LL_MASK 0x0001 8949 #define PMD_X4_LATCH_STATUS_RX_LOCK_LL_ALIGN 0 8950 #define PMD_X4_LATCH_STATUS_RX_LOCK_LL_BITS 1 8951 #define PMD_X4_LATCH_STATUS_RX_LOCK_LL_SHIFT 0 8952 8953 8954 /**************************************************************************** 8955 * pmd_x4 :: override 8956 */ 8957 /* pmd_x4 :: override :: reserved0 [15:08] */ 8958 #define PMD_X4_OVERRIDE_RESERVED0_MASK 0xff00 8959 #define PMD_X4_OVERRIDE_RESERVED0_ALIGN 0 8960 #define PMD_X4_OVERRIDE_RESERVED0_BITS 8 8961 #define PMD_X4_OVERRIDE_RESERVED0_SHIFT 8 8962 8963 /* pmd_x4 :: override :: ln_dp_h_rstb_oen [07:07] */ 8964 #define PMD_X4_OVERRIDE_LN_DP_H_RSTB_OEN_MASK 0x0080 8965 #define PMD_X4_OVERRIDE_LN_DP_H_RSTB_OEN_ALIGN 0 8966 #define PMD_X4_OVERRIDE_LN_DP_H_RSTB_OEN_BITS 1 8967 #define PMD_X4_OVERRIDE_LN_DP_H_RSTB_OEN_SHIFT 7 8968 8969 /* pmd_x4 :: override :: tx_disable_oen [06:06] */ 8970 #define PMD_X4_OVERRIDE_TX_DISABLE_OEN_MASK 0x0040 8971 #define PMD_X4_OVERRIDE_TX_DISABLE_OEN_ALIGN 0 8972 #define PMD_X4_OVERRIDE_TX_DISABLE_OEN_BITS 1 8973 #define PMD_X4_OVERRIDE_TX_DISABLE_OEN_SHIFT 6 8974 8975 /* pmd_x4 :: override :: rx_dme_en_oen [05:05] */ 8976 #define PMD_X4_OVERRIDE_RX_DME_EN_OEN_MASK 0x0020 8977 #define PMD_X4_OVERRIDE_RX_DME_EN_OEN_ALIGN 0 8978 #define PMD_X4_OVERRIDE_RX_DME_EN_OEN_BITS 1 8979 #define PMD_X4_OVERRIDE_RX_DME_EN_OEN_SHIFT 5 8980 8981 /* pmd_x4 :: override :: osr_mode_oen [04:04] */ 8982 #define PMD_X4_OVERRIDE_OSR_MODE_OEN_MASK 0x0010 8983 #define PMD_X4_OVERRIDE_OSR_MODE_OEN_ALIGN 0 8984 #define PMD_X4_OVERRIDE_OSR_MODE_OEN_BITS 1 8985 #define PMD_X4_OVERRIDE_OSR_MODE_OEN_SHIFT 4 8986 8987 /* pmd_x4 :: override :: lane_mode_oen [03:03] */ 8988 #define PMD_X4_OVERRIDE_LANE_MODE_OEN_MASK 0x0008 8989 #define PMD_X4_OVERRIDE_LANE_MODE_OEN_ALIGN 0 8990 #define PMD_X4_OVERRIDE_LANE_MODE_OEN_BITS 1 8991 #define PMD_X4_OVERRIDE_LANE_MODE_OEN_SHIFT 3 8992 8993 /* pmd_x4 :: override :: rx_clk_vld_ovrd [02:02] */ 8994 #define PMD_X4_OVERRIDE_RX_CLK_VLD_OVRD_MASK 0x0004 8995 #define PMD_X4_OVERRIDE_RX_CLK_VLD_OVRD_ALIGN 0 8996 #define PMD_X4_OVERRIDE_RX_CLK_VLD_OVRD_BITS 1 8997 #define PMD_X4_OVERRIDE_RX_CLK_VLD_OVRD_SHIFT 2 8998 8999 /* pmd_x4 :: override :: signal_detect_ovrd [01:01] */ 9000 #define PMD_X4_OVERRIDE_SIGNAL_DETECT_OVRD_MASK 0x0002 9001 #define PMD_X4_OVERRIDE_SIGNAL_DETECT_OVRD_ALIGN 0 9002 #define PMD_X4_OVERRIDE_SIGNAL_DETECT_OVRD_BITS 1 9003 #define PMD_X4_OVERRIDE_SIGNAL_DETECT_OVRD_SHIFT 1 9004 9005 /* pmd_x4 :: override :: rx_lock_ovrd [00:00] */ 9006 #define PMD_X4_OVERRIDE_RX_LOCK_OVRD_MASK 0x0001 9007 #define PMD_X4_OVERRIDE_RX_LOCK_OVRD_ALIGN 0 9008 #define PMD_X4_OVERRIDE_RX_LOCK_OVRD_BITS 1 9009 #define PMD_X4_OVERRIDE_RX_LOCK_OVRD_SHIFT 0 9010 9011 9012 /**************************************************************************** 9013 * pmd_x4 :: eee_control 9014 */ 9015 /* pmd_x4 :: eee_control :: reserved0 [15:03] */ 9016 #define PMD_X4_EEE_CONTROL_RESERVED0_MASK 0xfff8 9017 #define PMD_X4_EEE_CONTROL_RESERVED0_ALIGN 0 9018 #define PMD_X4_EEE_CONTROL_RESERVED0_BITS 13 9019 #define PMD_X4_EEE_CONTROL_RESERVED0_SHIFT 3 9020 9021 /* pmd_x4 :: eee_control :: rx_mode [02:02] */ 9022 #define PMD_X4_EEE_CONTROL_RX_MODE_MASK 0x0004 9023 #define PMD_X4_EEE_CONTROL_RX_MODE_ALIGN 0 9024 #define PMD_X4_EEE_CONTROL_RX_MODE_BITS 1 9025 #define PMD_X4_EEE_CONTROL_RX_MODE_SHIFT 2 9026 9027 /* pmd_x4 :: eee_control :: tx_mode [01:00] */ 9028 #define PMD_X4_EEE_CONTROL_TX_MODE_MASK 0x0003 9029 #define PMD_X4_EEE_CONTROL_TX_MODE_ALIGN 0 9030 #define PMD_X4_EEE_CONTROL_TX_MODE_BITS 2 9031 #define PMD_X4_EEE_CONTROL_TX_MODE_SHIFT 0 9032 9033 9034 /**************************************************************************** 9035 * pmd_x4 :: eee_status 9036 */ 9037 /* pmd_x4 :: eee_status :: reserved0 [15:01] */ 9038 #define PMD_X4_EEE_STATUS_RESERVED0_MASK 0xfffe 9039 #define PMD_X4_EEE_STATUS_RESERVED0_ALIGN 0 9040 #define PMD_X4_EEE_STATUS_RESERVED0_BITS 15 9041 #define PMD_X4_EEE_STATUS_RESERVED0_SHIFT 1 9042 9043 /* pmd_x4 :: eee_status :: energy_detect [00:00] */ 9044 #define PMD_X4_EEE_STATUS_ENERGY_DETECT_MASK 0x0001 9045 #define PMD_X4_EEE_STATUS_ENERGY_DETECT_ALIGN 0 9046 #define PMD_X4_EEE_STATUS_ENERGY_DETECT_BITS 1 9047 #define PMD_X4_EEE_STATUS_ENERGY_DETECT_SHIFT 0 9048 9049 9050 /**************************************************************************** 9051 * TSCE_TSCE_USER4_PatGen1 9052 */ 9053 /**************************************************************************** 9054 * PatGen1 :: txpktcnt_U 9055 */ 9056 /* PatGen1 :: txpktcnt_U :: txpktcnt_U [15:00] */ 9057 #define PATGEN1_TXPKTCNT_U_TXPKTCNT_U_MASK 0xffff 9058 #define PATGEN1_TXPKTCNT_U_TXPKTCNT_U_ALIGN 0 9059 #define PATGEN1_TXPKTCNT_U_TXPKTCNT_U_BITS 16 9060 #define PATGEN1_TXPKTCNT_U_TXPKTCNT_U_SHIFT 0 9061 9062 9063 /**************************************************************************** 9064 * PatGen1 :: txpktcnt_L 9065 */ 9066 /* PatGen1 :: txpktcnt_L :: txpktcnt_L [15:00] */ 9067 #define PATGEN1_TXPKTCNT_L_TXPKTCNT_L_MASK 0xffff 9068 #define PATGEN1_TXPKTCNT_L_TXPKTCNT_L_ALIGN 0 9069 #define PATGEN1_TXPKTCNT_L_TXPKTCNT_L_BITS 16 9070 #define PATGEN1_TXPKTCNT_L_TXPKTCNT_L_SHIFT 0 9071 9072 9073 /**************************************************************************** 9074 * PatGen1 :: rxpktcnt_U 9075 */ 9076 /* PatGen1 :: rxpktcnt_U :: rxpktcnt_U [15:00] */ 9077 #define PATGEN1_RXPKTCNT_U_RXPKTCNT_U_MASK 0xffff 9078 #define PATGEN1_RXPKTCNT_U_RXPKTCNT_U_ALIGN 0 9079 #define PATGEN1_RXPKTCNT_U_RXPKTCNT_U_BITS 16 9080 #define PATGEN1_RXPKTCNT_U_RXPKTCNT_U_SHIFT 0 9081 9082 9083 /**************************************************************************** 9084 * PatGen1 :: rxpktcnt_L 9085 */ 9086 /* PatGen1 :: rxpktcnt_L :: rxpktcnt_L [15:00] */ 9087 #define PATGEN1_RXPKTCNT_L_RXPKTCNT_L_MASK 0xffff 9088 #define PATGEN1_RXPKTCNT_L_RXPKTCNT_L_ALIGN 0 9089 #define PATGEN1_RXPKTCNT_L_RXPKTCNT_L_BITS 16 9090 #define PATGEN1_RXPKTCNT_L_RXPKTCNT_L_SHIFT 0 9091 9092 9093 /**************************************************************************** 9094 * TSCE_TSCE_USER4_sc_x4_control 9095 */ 9096 /**************************************************************************** 9097 * sc_x4_control :: control 9098 */ 9099 /* sc_x4_control :: control :: reserved0 [15:09] */ 9100 #define SC_X4_CONTROL_CONTROL_RESERVED0_MASK 0xfe00 9101 #define SC_X4_CONTROL_CONTROL_RESERVED0_ALIGN 0 9102 #define SC_X4_CONTROL_CONTROL_RESERVED0_BITS 7 9103 #define SC_X4_CONTROL_CONTROL_RESERVED0_SHIFT 9 9104 9105 /* sc_x4_control :: control :: sw_speed_change [08:08] */ 9106 #define SC_X4_CONTROL_CONTROL_SW_SPEED_CHANGE_MASK 0x0100 9107 #define SC_X4_CONTROL_CONTROL_SW_SPEED_CHANGE_ALIGN 0 9108 #define SC_X4_CONTROL_CONTROL_SW_SPEED_CHANGE_BITS 1 9109 #define SC_X4_CONTROL_CONTROL_SW_SPEED_CHANGE_SHIFT 8 9110 9111 /* sc_x4_control :: control :: sw_speed [07:00] */ 9112 #define SC_X4_CONTROL_CONTROL_SW_SPEED_MASK 0x00ff 9113 #define SC_X4_CONTROL_CONTROL_SW_SPEED_ALIGN 0 9114 #define SC_X4_CONTROL_CONTROL_SW_SPEED_BITS 8 9115 #define SC_X4_CONTROL_CONTROL_SW_SPEED_SHIFT 0 9116 #define SC_X4_CONTROL_CONTROL_SW_SPEED_SPEED_2p5G_X1_10p3125 56 9117 #define SC_X4_CONTROL_CONTROL_SW_SPEED_SPEED_1000M_10p3125 55 9118 #define SC_X4_CONTROL_CONTROL_SW_SPEED_SPEED_100M_10p3125 54 9119 #define SC_X4_CONTROL_CONTROL_SW_SPEED_SPEED_10M_10p3125 53 9120 #define SC_X4_CONTROL_CONTROL_SW_SPEED_SPEED_10p5G_X4 50 9121 #define SC_X4_CONTROL_CONTROL_SW_SPEED_SPEED_5G_KR1 49 9122 #define SC_X4_CONTROL_CONTROL_SW_SPEED_SPEED_127G_X12 39 9123 #define SC_X4_CONTROL_CONTROL_SW_SPEED_SPEED_120G_X12 38 9124 #define SC_X4_CONTROL_CONTROL_SW_SPEED_SPEED_107G_X10 37 9125 #define SC_X4_CONTROL_CONTROL_SW_SPEED_SPEED_100G_CR10 36 9126 #define SC_X4_CONTROL_CONTROL_SW_SPEED_SPEED_42G_X4 35 9127 #define SC_X4_CONTROL_CONTROL_SW_SPEED_SPEED_40G_CR4 34 9128 #define SC_X4_CONTROL_CONTROL_SW_SPEED_SPEED_40G_KR4 33 9129 #define SC_X4_CONTROL_CONTROL_SW_SPEED_SPEED_21G_X2 32 9130 #define SC_X4_CONTROL_CONTROL_SW_SPEED_SPEED_20G_CR2 31 9131 #define SC_X4_CONTROL_CONTROL_SW_SPEED_SPEED_20G_KR2 30 9132 #define SC_X4_CONTROL_CONTROL_SW_SPEED_SPEED_10p6_X1 29 9133 #define SC_X4_CONTROL_CONTROL_SW_SPEED_SPEED_10G_KR1 28 9134 #define SC_X4_CONTROL_CONTROL_SW_SPEED_SPEED_40G_X4 27 9135 #define SC_X4_CONTROL_CONTROL_SW_SPEED_SPEED_20G_X2 26 9136 #define SC_X4_CONTROL_CONTROL_SW_SPEED_SPEED_20G_CX2 25 9137 #define SC_X4_CONTROL_CONTROL_SW_SPEED_SPEED_31p5G_KR4 24 9138 #define SC_X4_CONTROL_CONTROL_SW_SPEED_SPEED_31p5G_X4 23 9139 #define SC_X4_CONTROL_CONTROL_SW_SPEED_SPEED_15p75G_X2 22 9140 #define SC_X4_CONTROL_CONTROL_SW_SPEED_SPEED_25p45G_X4 21 9141 #define SC_X4_CONTROL_CONTROL_SW_SPEED_SPEED_12p7G_X2 20 9142 #define SC_X4_CONTROL_CONTROL_SW_SPEED_SPEED_21G_X4 19 9143 #define SC_X4_CONTROL_CONTROL_SW_SPEED_SPEED_10p5G_X2 18 9144 #define SC_X4_CONTROL_CONTROL_SW_SPEED_SPEED_20G_X4 17 9145 #define SC_X4_CONTROL_CONTROL_SW_SPEED_SPEED_10G_X2 16 9146 #define SC_X4_CONTROL_CONTROL_SW_SPEED_SPEED_10G_CX2 15 9147 #define SC_X4_CONTROL_CONTROL_SW_SPEED_SPEED_20G_CX4 14 9148 #define SC_X4_CONTROL_CONTROL_SW_SPEED_SPEED_16G_X4 13 9149 #define SC_X4_CONTROL_CONTROL_SW_SPEED_SPEED_15G_X4 12 9150 #define SC_X4_CONTROL_CONTROL_SW_SPEED_SPEED_13G_X4 11 9151 #define SC_X4_CONTROL_CONTROL_SW_SPEED_SPEED_10G_X4 10 9152 #define SC_X4_CONTROL_CONTROL_SW_SPEED_SPEED_10G_KX4 9 9153 #define SC_X4_CONTROL_CONTROL_SW_SPEED_SPEED_10G_CX4 8 9154 #define SC_X4_CONTROL_CONTROL_SW_SPEED_SPEED_5G_X1 7 9155 #define SC_X4_CONTROL_CONTROL_SW_SPEED_SPEED_2p5G_X1 6 9156 #define SC_X4_CONTROL_CONTROL_SW_SPEED_SPEED_1G_KX1 5 9157 #define SC_X4_CONTROL_CONTROL_SW_SPEED_SPEED_1G_CX1 4 9158 #define SC_X4_CONTROL_CONTROL_SW_SPEED_SPEED_1000M 3 9159 #define SC_X4_CONTROL_CONTROL_SW_SPEED_SPEED_100M 2 9160 #define SC_X4_CONTROL_CONTROL_SW_SPEED_SPEED_10M 1 9161 9162 9163 /**************************************************************************** 9164 * sc_x4_control :: status 9165 */ 9166 /* sc_x4_control :: status :: reserved0 [15:02] */ 9167 #define SC_X4_CONTROL_STATUS_RESERVED0_MASK 0xfffc 9168 #define SC_X4_CONTROL_STATUS_RESERVED0_ALIGN 0 9169 #define SC_X4_CONTROL_STATUS_RESERVED0_BITS 14 9170 #define SC_X4_CONTROL_STATUS_RESERVED0_SHIFT 2 9171 9172 /* sc_x4_control :: status :: sw_speed_config_vld [01:01] */ 9173 #define SC_X4_CONTROL_STATUS_SW_SPEED_CONFIG_VLD_MASK 0x0002 9174 #define SC_X4_CONTROL_STATUS_SW_SPEED_CONFIG_VLD_ALIGN 0 9175 #define SC_X4_CONTROL_STATUS_SW_SPEED_CONFIG_VLD_BITS 1 9176 #define SC_X4_CONTROL_STATUS_SW_SPEED_CONFIG_VLD_SHIFT 1 9177 9178 /* sc_x4_control :: status :: sw_speed_change_done [00:00] */ 9179 #define SC_X4_CONTROL_STATUS_SW_SPEED_CHANGE_DONE_MASK 0x0001 9180 #define SC_X4_CONTROL_STATUS_SW_SPEED_CHANGE_DONE_ALIGN 0 9181 #define SC_X4_CONTROL_STATUS_SW_SPEED_CHANGE_DONE_BITS 1 9182 #define SC_X4_CONTROL_STATUS_SW_SPEED_CHANGE_DONE_SHIFT 0 9183 9184 9185 /**************************************************************************** 9186 * sc_x4_control :: error 9187 */ 9188 /* sc_x4_control :: error :: reserved0 [15:02] */ 9189 #define SC_X4_CONTROL_ERROR_RESERVED0_MASK 0xfffc 9190 #define SC_X4_CONTROL_ERROR_RESERVED0_ALIGN 0 9191 #define SC_X4_CONTROL_ERROR_RESERVED0_BITS 14 9192 #define SC_X4_CONTROL_ERROR_RESERVED0_SHIFT 2 9193 9194 /* sc_x4_control :: error :: pmd_lock_timed_out [01:01] */ 9195 #define SC_X4_CONTROL_ERROR_PMD_LOCK_TIMED_OUT_MASK 0x0002 9196 #define SC_X4_CONTROL_ERROR_PMD_LOCK_TIMED_OUT_ALIGN 0 9197 #define SC_X4_CONTROL_ERROR_PMD_LOCK_TIMED_OUT_BITS 1 9198 #define SC_X4_CONTROL_ERROR_PMD_LOCK_TIMED_OUT_SHIFT 1 9199 9200 /* sc_x4_control :: error :: pll_lock_timed_out [00:00] */ 9201 #define SC_X4_CONTROL_ERROR_PLL_LOCK_TIMED_OUT_MASK 0x0001 9202 #define SC_X4_CONTROL_ERROR_PLL_LOCK_TIMED_OUT_ALIGN 0 9203 #define SC_X4_CONTROL_ERROR_PLL_LOCK_TIMED_OUT_BITS 1 9204 #define SC_X4_CONTROL_ERROR_PLL_LOCK_TIMED_OUT_SHIFT 0 9205 9206 9207 /**************************************************************************** 9208 * sc_x4_control :: debug 9209 */ 9210 /* sc_x4_control :: debug :: sc_fsm_status [15:00] */ 9211 #define SC_X4_CONTROL_DEBUG_SC_FSM_STATUS_MASK 0xffff 9212 #define SC_X4_CONTROL_DEBUG_SC_FSM_STATUS_ALIGN 0 9213 #define SC_X4_CONTROL_DEBUG_SC_FSM_STATUS_BITS 16 9214 #define SC_X4_CONTROL_DEBUG_SC_FSM_STATUS_SHIFT 0 9215 #define SC_X4_CONTROL_DEBUG_SC_FSM_STATUS_START 32768 9216 #define SC_X4_CONTROL_DEBUG_SC_FSM_STATUS_RESET_PCS 16384 9217 #define SC_X4_CONTROL_DEBUG_SC_FSM_STATUS_RESET_PMD_LANE 8192 9218 #define SC_X4_CONTROL_DEBUG_SC_FSM_STATUS_RESET_PMD_PLL 4096 9219 #define SC_X4_CONTROL_DEBUG_SC_FSM_STATUS_APPLY_SPEED_CFG 2048 9220 #define SC_X4_CONTROL_DEBUG_SC_FSM_STATUS_WAIT_CFG_DONE 1024 9221 #define SC_X4_CONTROL_DEBUG_SC_FSM_STATUS_ACTIVATE_PMD 512 9222 #define SC_X4_CONTROL_DEBUG_SC_FSM_STATUS_WAIT_PLL_RESET 256 9223 #define SC_X4_CONTROL_DEBUG_SC_FSM_STATUS_PLL_LOCK_FAIL 128 9224 #define SC_X4_CONTROL_DEBUG_SC_FSM_STATUS_ACTIVATE_TX 64 9225 #define SC_X4_CONTROL_DEBUG_SC_FSM_STATUS_WAIT_PMD_LOCK 32 9226 #define SC_X4_CONTROL_DEBUG_SC_FSM_STATUS_ACTIVATE_RX 16 9227 #define SC_X4_CONTROL_DEBUG_SC_FSM_STATUS_PMD_LOCK_FAIL 8 9228 #define SC_X4_CONTROL_DEBUG_SC_FSM_STATUS_DONE 4 9229 #define SC_X4_CONTROL_DEBUG_SC_FSM_STATUS_STOP 2 9230 #define SC_X4_CONTROL_DEBUG_SC_FSM_STATUS_BYPASS 1 9231 9232 9233 /**************************************************************************** 9234 * sc_x4_control :: lane_num_override 9235 */ 9236 /* sc_x4_control :: lane_num_override :: reserved0 [15:03] */ 9237 #define SC_X4_CONTROL_LANE_NUM_OVERRIDE_RESERVED0_MASK 0xfff8 9238 #define SC_X4_CONTROL_LANE_NUM_OVERRIDE_RESERVED0_ALIGN 0 9239 #define SC_X4_CONTROL_LANE_NUM_OVERRIDE_RESERVED0_BITS 13 9240 #define SC_X4_CONTROL_LANE_NUM_OVERRIDE_RESERVED0_SHIFT 3 9241 9242 /* sc_x4_control :: lane_num_override :: num_lanes_override_value [02:00] */ 9243 #define SC_X4_CONTROL_LANE_NUM_OVERRIDE_NUM_LANES_OVERRIDE_VALUE_MASK 0x0007 9244 #define SC_X4_CONTROL_LANE_NUM_OVERRIDE_NUM_LANES_OVERRIDE_VALUE_ALIGN 0 9245 #define SC_X4_CONTROL_LANE_NUM_OVERRIDE_NUM_LANES_OVERRIDE_VALUE_BITS 3 9246 #define SC_X4_CONTROL_LANE_NUM_OVERRIDE_NUM_LANES_OVERRIDE_VALUE_SHIFT 0 9247 9248 9249 /**************************************************************************** 9250 * sc_x4_control :: bypass 9251 */ 9252 /* sc_x4_control :: bypass :: reserved0 [15:02] */ 9253 #define SC_X4_CONTROL_BYPASS_RESERVED0_MASK 0xfffc 9254 #define SC_X4_CONTROL_BYPASS_RESERVED0_ALIGN 0 9255 #define SC_X4_CONTROL_BYPASS_RESERVED0_BITS 14 9256 #define SC_X4_CONTROL_BYPASS_RESERVED0_SHIFT 2 9257 9258 /* sc_x4_control :: bypass :: sc_ignore_tx_data_vld [01:01] */ 9259 #define SC_X4_CONTROL_BYPASS_SC_IGNORE_TX_DATA_VLD_MASK 0x0002 9260 #define SC_X4_CONTROL_BYPASS_SC_IGNORE_TX_DATA_VLD_ALIGN 0 9261 #define SC_X4_CONTROL_BYPASS_SC_IGNORE_TX_DATA_VLD_BITS 1 9262 #define SC_X4_CONTROL_BYPASS_SC_IGNORE_TX_DATA_VLD_SHIFT 1 9263 9264 /* sc_x4_control :: bypass :: sc_bypass [00:00] */ 9265 #define SC_X4_CONTROL_BYPASS_SC_BYPASS_MASK 0x0001 9266 #define SC_X4_CONTROL_BYPASS_SC_BYPASS_ALIGN 0 9267 #define SC_X4_CONTROL_BYPASS_SC_BYPASS_BITS 1 9268 #define SC_X4_CONTROL_BYPASS_SC_BYPASS_SHIFT 0 9269 9270 9271 /**************************************************************************** 9272 * TSCE_TSCE_USER4_sc_x4_field_override_enable 9273 */ 9274 /**************************************************************************** 9275 * sc_x4_field_override_enable :: field_override_enable0_type 9276 */ 9277 /* sc_x4_field_override_enable :: field_override_enable0_type :: reserved0 [15:15] */ 9278 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_RESERVED0_MASK 0x8000 9279 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_RESERVED0_ALIGN 0 9280 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_RESERVED0_BITS 1 9281 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_RESERVED0_SHIFT 15 9282 9283 /* sc_x4_field_override_enable :: field_override_enable0_type :: num_lanes_oen [14:14] */ 9284 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_NUM_LANES_OEN_MASK 0x4000 9285 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_NUM_LANES_OEN_ALIGN 0 9286 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_NUM_LANES_OEN_BITS 1 9287 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_NUM_LANES_OEN_SHIFT 14 9288 9289 /* sc_x4_field_override_enable :: field_override_enable0_type :: reserved1 [13:13] */ 9290 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_RESERVED1_MASK 0x2000 9291 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_RESERVED1_ALIGN 0 9292 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_RESERVED1_BITS 1 9293 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_RESERVED1_SHIFT 13 9294 9295 /* sc_x4_field_override_enable :: field_override_enable0_type :: os_mode_oen [12:12] */ 9296 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_OS_MODE_OEN_MASK 0x1000 9297 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_OS_MODE_OEN_ALIGN 0 9298 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_OS_MODE_OEN_BITS 1 9299 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_OS_MODE_OEN_SHIFT 12 9300 9301 /* sc_x4_field_override_enable :: field_override_enable0_type :: scr_mode_oen [11:11] */ 9302 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_SCR_MODE_OEN_MASK 0x0800 9303 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_SCR_MODE_OEN_ALIGN 0 9304 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_SCR_MODE_OEN_BITS 1 9305 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_SCR_MODE_OEN_SHIFT 11 9306 9307 /* sc_x4_field_override_enable :: field_override_enable0_type :: fec_enable_oen [10:10] */ 9308 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_FEC_ENABLE_OEN_MASK 0x0400 9309 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_FEC_ENABLE_OEN_ALIGN 0 9310 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_FEC_ENABLE_OEN_BITS 1 9311 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_FEC_ENABLE_OEN_SHIFT 10 9312 9313 /* sc_x4_field_override_enable :: field_override_enable0_type :: encodeMode_oen [09:09] */ 9314 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_ENCODEMODE_OEN_MASK 0x0200 9315 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_ENCODEMODE_OEN_ALIGN 0 9316 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_ENCODEMODE_OEN_BITS 1 9317 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_ENCODEMODE_OEN_SHIFT 9 9318 9319 /* sc_x4_field_override_enable :: field_override_enable0_type :: descramblermode_oen [08:08] */ 9320 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_DESCRAMBLERMODE_OEN_MASK 0x0100 9321 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_DESCRAMBLERMODE_OEN_ALIGN 0 9322 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_DESCRAMBLERMODE_OEN_BITS 1 9323 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_DESCRAMBLERMODE_OEN_SHIFT 8 9324 9325 /* sc_x4_field_override_enable :: field_override_enable0_type :: decodermode_oen [07:07] */ 9326 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_DECODERMODE_OEN_MASK 0x0080 9327 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_DECODERMODE_OEN_ALIGN 0 9328 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_DECODERMODE_OEN_BITS 1 9329 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_DECODERMODE_OEN_SHIFT 7 9330 9331 /* sc_x4_field_override_enable :: field_override_enable0_type :: deskewmode_oen [06:06] */ 9332 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_DESKEWMODE_OEN_MASK 0x0040 9333 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_DESKEWMODE_OEN_ALIGN 0 9334 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_DESKEWMODE_OEN_BITS 1 9335 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_DESKEWMODE_OEN_SHIFT 6 9336 9337 /* sc_x4_field_override_enable :: field_override_enable0_type :: desc2_mode_oen [05:05] */ 9338 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_DESC2_MODE_OEN_MASK 0x0020 9339 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_DESC2_MODE_OEN_ALIGN 0 9340 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_DESC2_MODE_OEN_BITS 1 9341 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_DESC2_MODE_OEN_SHIFT 5 9342 9343 /* sc_x4_field_override_enable :: field_override_enable0_type :: CL36ByteDeleteMode_oen [04:04] */ 9344 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_CL36BYTEDELETEMOD16E_OEN_MASK 0x0010 9345 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_CL36BYTEDELETEMOD16E_OEN_ALIGN 0 9346 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_CL36BYTEDELETEMOD16E_OEN_BITS 1 9347 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_CL36BYTEDELETEMOD16E_OEN_SHIFT 4 9348 9349 /* sc_x4_field_override_enable :: field_override_enable0_type :: brcm64b66_descrambler_enable_oen [03:03] */ 9350 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_BRCM64B66_DESCRAMBLER_ENABLE_OEN_MASK 0x0008 9351 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_BRCM64B66_DESCRAMBLER_ENABLE_OEN_ALIGN 0 9352 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_BRCM64B66_DESCRAMBLER_ENABLE_OEN_BITS 1 9353 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_BRCM64B66_DESCRAMBLER_ENABLE_OEN_SHIFT 3 9354 9355 /* sc_x4_field_override_enable :: field_override_enable0_type :: chk_end_en_oen [02:02] */ 9356 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_CHK_END_EN_OEN_MASK 0x0004 9357 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_CHK_END_EN_OEN_ALIGN 0 9358 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_CHK_END_EN_OEN_BITS 1 9359 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_CHK_END_EN_OEN_SHIFT 2 9360 9361 /* sc_x4_field_override_enable :: field_override_enable0_type :: reserved2 [01:01] */ 9362 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_RESERVED2_MASK 0x0002 9363 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_RESERVED2_ALIGN 0 9364 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_RESERVED2_BITS 1 9365 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_RESERVED2_SHIFT 1 9366 9367 /* sc_x4_field_override_enable :: field_override_enable0_type :: block_sync_mode_oen [00:00] */ 9368 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_BLOCK_SYNC_MODE_OEN_MASK 0x0001 9369 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_BLOCK_SYNC_MODE_OEN_ALIGN 0 9370 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_BLOCK_SYNC_MODE_OEN_BITS 1 9371 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE_BLOCK_SYNC_MODE_OEN_SHIFT 0 9372 9373 9374 /**************************************************************************** 9375 * sc_x4_field_override_enable :: field_override_enable1_type 9376 */ 9377 /* sc_x4_field_override_enable :: field_override_enable1_type :: reserved0 [15:14] */ 9378 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_RESERVED0_MASK 0xc000 9379 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_RESERVED0_ALIGN 0 9380 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_RESERVED0_BITS 2 9381 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_RESERVED0_SHIFT 14 9382 9383 /* sc_x4_field_override_enable :: field_override_enable1_type :: cl72_en_oen [13:13] */ 9384 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_CL72_EN_OEN_MASK 0x2000 9385 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_CL72_EN_OEN_ALIGN 0 9386 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_CL72_EN_OEN_BITS 1 9387 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_CL72_EN_OEN_SHIFT 13 9388 9389 /* sc_x4_field_override_enable :: field_override_enable1_type :: reorder_en_oen [12:12] */ 9390 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_REORDER_EN_OEN_MASK 0x1000 9391 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_REORDER_EN_OEN_ALIGN 0 9392 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_REORDER_EN_OEN_BITS 1 9393 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_REORDER_EN_OEN_SHIFT 12 9394 9395 /* sc_x4_field_override_enable :: field_override_enable1_type :: cl36_en_oen [11:11] */ 9396 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_CL36_EN_OEN_MASK 0x0800 9397 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_CL36_EN_OEN_ALIGN 0 9398 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_CL36_EN_OEN_BITS 1 9399 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_CL36_EN_OEN_SHIFT 11 9400 9401 /* sc_x4_field_override_enable :: field_override_enable1_type :: sgmii_spd_switch_oen [10:10] */ 9402 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_SGMII_SPD_SWITCH_OEN_MASK 0x0400 9403 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_SGMII_SPD_SWITCH_OEN_ALIGN 0 9404 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_SGMII_SPD_SWITCH_OEN_BITS 1 9405 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_SGMII_SPD_SWITCH_OEN_SHIFT 10 9406 9407 /* sc_x4_field_override_enable :: field_override_enable1_type :: creditenable_oen [09:09] */ 9408 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_CREDITENABLE_OEN_MASK 0x0200 9409 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_CREDITENABLE_OEN_ALIGN 0 9410 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_CREDITENABLE_OEN_BITS 1 9411 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_CREDITENABLE_OEN_SHIFT 9 9412 9413 /* sc_x4_field_override_enable :: field_override_enable1_type :: clockcnt0_oen [08:08] */ 9414 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_CLOCKCNT0_OEN_MASK 0x0100 9415 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_CLOCKCNT0_OEN_ALIGN 0 9416 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_CLOCKCNT0_OEN_BITS 1 9417 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_CLOCKCNT0_OEN_SHIFT 8 9418 9419 /* sc_x4_field_override_enable :: field_override_enable1_type :: clockcnt1_oen [07:07] */ 9420 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_CLOCKCNT1_OEN_MASK 0x0080 9421 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_CLOCKCNT1_OEN_ALIGN 0 9422 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_CLOCKCNT1_OEN_BITS 1 9423 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_CLOCKCNT1_OEN_SHIFT 7 9424 9425 /* sc_x4_field_override_enable :: field_override_enable1_type :: loopcnt0_oen [06:06] */ 9426 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_LOOPCNT0_OEN_MASK 0x0040 9427 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_LOOPCNT0_OEN_ALIGN 0 9428 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_LOOPCNT0_OEN_BITS 1 9429 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_LOOPCNT0_OEN_SHIFT 6 9430 9431 /* sc_x4_field_override_enable :: field_override_enable1_type :: loopcnt1_oen [05:05] */ 9432 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_LOOPCNT1_OEN_MASK 0x0020 9433 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_LOOPCNT1_OEN_ALIGN 0 9434 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_LOOPCNT1_OEN_BITS 1 9435 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_LOOPCNT1_OEN_SHIFT 5 9436 9437 /* sc_x4_field_override_enable :: field_override_enable1_type :: mac_creditgencnt_oen [04:04] */ 9438 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_MAC_CREDITGENCNT_OEN_MASK 0x0010 9439 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_MAC_CREDITGENCNT_OEN_ALIGN 0 9440 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_MAC_CREDITGENCNT_OEN_BITS 1 9441 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_MAC_CREDITGENCNT_OEN_SHIFT 4 9442 9443 /* sc_x4_field_override_enable :: field_override_enable1_type :: replication_cnt_oen [03:03] */ 9444 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_REPLICATION_CNT_OEN_MASK 0x0008 9445 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_REPLICATION_CNT_OEN_ALIGN 0 9446 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_REPLICATION_CNT_OEN_BITS 1 9447 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_REPLICATION_CNT_OEN_SHIFT 3 9448 9449 /* sc_x4_field_override_enable :: field_override_enable1_type :: pcs_creditenable_oen [02:02] */ 9450 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_PCS_CREDITENABLE_OEN_MASK 0x0004 9451 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_PCS_CREDITENABLE_OEN_ALIGN 0 9452 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_PCS_CREDITENABLE_OEN_BITS 1 9453 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_PCS_CREDITENABLE_OEN_SHIFT 2 9454 9455 /* sc_x4_field_override_enable :: field_override_enable1_type :: pcs_clockcnt0_oen [01:01] */ 9456 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_PCS_CLOCKCNT0_OEN_MASK 0x0002 9457 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_PCS_CLOCKCNT0_OEN_ALIGN 0 9458 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_PCS_CLOCKCNT0_OEN_BITS 1 9459 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_PCS_CLOCKCNT0_OEN_SHIFT 1 9460 9461 /* sc_x4_field_override_enable :: field_override_enable1_type :: pcs_creditgencnt_oen [00:00] */ 9462 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_PCS_CREDITGENCNT_OEN_MASK 0x0001 9463 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_PCS_CREDITGENCNT_OEN_ALIGN 0 9464 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_PCS_CREDITGENCNT_OEN_BITS 1 9465 #define SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE_PCS_CREDITGENCNT_OEN_SHIFT 0 9466 9467 9468 /**************************************************************************** 9469 * TSCE_TSCE_USER4_sc_x4_final_config_status 9470 */ 9471 /**************************************************************************** 9472 * sc_x4_final_config_status :: resolved_speed 9473 */ 9474 /* sc_x4_final_config_status :: resolved_speed :: speed [15:08] */ 9475 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_MASK 0xff00 9476 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_ALIGN 0 9477 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_BITS 8 9478 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_SHIFT 8 9479 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_SPEED_2p5G_X1_10p3125 56 9480 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_SPEED_1000M_10p3125 55 9481 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_SPEED_100M_10p3125 54 9482 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_SPEED_10M_10p3125 53 9483 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_SPEED_10p5G_X4 50 9484 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_SPEED_5G_KR1 49 9485 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_SPEED_127G_X12 39 9486 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_SPEED_120G_X12 38 9487 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_SPEED_107G_X10 37 9488 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_SPEED_100G_CR10 36 9489 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_SPEED_42G_X4 35 9490 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_SPEED_40G_CR4 34 9491 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_SPEED_40G_KR4 33 9492 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_SPEED_21G_X2 32 9493 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_SPEED_20G_CR2 31 9494 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_SPEED_20G_KR2 30 9495 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_SPEED_10p6_X1 29 9496 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_SPEED_10G_KR1 28 9497 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_SPEED_40G_X4 27 9498 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_SPEED_20G_X2 26 9499 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_SPEED_20G_CX2 25 9500 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_SPEED_31p5G_KR4 24 9501 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_SPEED_31p5G_X4 23 9502 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_SPEED_15p75G_X2 22 9503 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_SPEED_25p45G_X4 21 9504 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_SPEED_12p7G_X2 20 9505 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_SPEED_21G_X4 19 9506 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_SPEED_10p5G_X2 18 9507 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_SPEED_20G_X4 17 9508 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_SPEED_10G_X2 16 9509 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_SPEED_10G_CX2 15 9510 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_SPEED_20G_CX4 14 9511 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_SPEED_16G_X4 13 9512 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_SPEED_15G_X4 12 9513 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_SPEED_13G_X4 11 9514 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_SPEED_10G_X4 10 9515 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_SPEED_10G_KX4 9 9516 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_SPEED_10G_CX4 8 9517 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_SPEED_5G_X1 7 9518 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_SPEED_2p5G_X1 6 9519 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_SPEED_1G_KX1 5 9520 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_SPEED_1G_CX1 4 9521 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_SPEED_1000M 3 9522 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_SPEED_100M 2 9523 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_SPEED_10M 1 9524 9525 /* sc_x4_final_config_status :: resolved_speed :: reserved0 [07:03] */ 9526 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_RESERVED0_MASK 0x00f8 9527 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_RESERVED0_ALIGN 0 9528 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_RESERVED0_BITS 5 9529 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_RESERVED0_SHIFT 3 9530 9531 /* sc_x4_final_config_status :: resolved_speed :: num_lanes [02:00] */ 9532 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_NUM_LANES_MASK 0x0007 9533 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_NUM_LANES_ALIGN 0 9534 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_NUM_LANES_BITS 3 9535 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_NUM_LANES_SHIFT 0 9536 9537 9538 /**************************************************************************** 9539 * sc_x4_final_config_status :: resolved_0 9540 */ 9541 /* sc_x4_final_config_status :: resolved_0 :: os_mode [15:12] */ 9542 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_OS_MODE_MASK 0xf000 9543 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_OS_MODE_ALIGN 0 9544 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_OS_MODE_BITS 4 9545 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_OS_MODE_SHIFT 12 9546 9547 /* sc_x4_final_config_status :: resolved_0 :: scr_mode [11:10] */ 9548 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_SCR_MODE_MASK 0x0c00 9549 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_SCR_MODE_ALIGN 0 9550 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_SCR_MODE_BITS 2 9551 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_SCR_MODE_SHIFT 10 9552 9553 /* sc_x4_final_config_status :: resolved_0 :: cl72_enable [09:09] */ 9554 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_CL72_ENABLE_MASK 0x0200 9555 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_CL72_ENABLE_ALIGN 0 9556 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_CL72_ENABLE_BITS 1 9557 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_CL72_ENABLE_SHIFT 9 9558 9559 /* sc_x4_final_config_status :: resolved_0 :: fec_enable [08:08] */ 9560 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_FEC_ENABLE_MASK 0x0100 9561 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_FEC_ENABLE_ALIGN 0 9562 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_FEC_ENABLE_BITS 1 9563 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_FEC_ENABLE_SHIFT 8 9564 9565 /* sc_x4_final_config_status :: resolved_0 :: reserved0 [07:03] */ 9566 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_RESERVED0_MASK 0x00f8 9567 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_RESERVED0_ALIGN 0 9568 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_RESERVED0_BITS 5 9569 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_RESERVED0_SHIFT 3 9570 9571 /* sc_x4_final_config_status :: resolved_0 :: encodeMode [02:00] */ 9572 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_ENCODEMODE_MASK 0x0007 9573 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_ENCODEMODE_ALIGN 0 9574 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_ENCODEMODE_BITS 3 9575 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0_ENCODEMODE_SHIFT 0 9576 9577 9578 /**************************************************************************** 9579 * sc_x4_final_config_status :: resolved_1 9580 */ 9581 /* sc_x4_final_config_status :: resolved_1 :: descramblermode [15:14] */ 9582 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_DESCRAMBLERMODE_MASK 0xc000 9583 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_DESCRAMBLERMODE_ALIGN 0 9584 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_DESCRAMBLERMODE_BITS 2 9585 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_DESCRAMBLERMODE_SHIFT 14 9586 9587 /* sc_x4_final_config_status :: resolved_1 :: decodermode [13:11] */ 9588 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_DECODERMODE_MASK 0x3800 9589 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_DECODERMODE_ALIGN 0 9590 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_DECODERMODE_BITS 3 9591 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_DECODERMODE_SHIFT 11 9592 9593 /* sc_x4_final_config_status :: resolved_1 :: deskewmode [10:08] */ 9594 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_DESKEWMODE_MASK 0x0700 9595 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_DESKEWMODE_ALIGN 0 9596 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_DESKEWMODE_BITS 3 9597 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_DESKEWMODE_SHIFT 8 9598 9599 /* sc_x4_final_config_status :: resolved_1 :: desc2_mode [07:05] */ 9600 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_DESC2_MODE_MASK 0x00e0 9601 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_DESC2_MODE_ALIGN 0 9602 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_DESC2_MODE_BITS 3 9603 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_DESC2_MODE_SHIFT 5 9604 9605 /* sc_x4_final_config_status :: resolved_1 :: CL36ByteDeleteMode [04:03] */ 9606 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_CL36BYTEDELETEMOD16E_MASK 0x0018 9607 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_CL36BYTEDELETEMOD16E_ALIGN 0 9608 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_CL36BYTEDELETEMOD16E_BITS 2 9609 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_CL36BYTEDELETEMOD16E_SHIFT 3 9610 9611 /* sc_x4_final_config_status :: resolved_1 :: reserved0 [02:02] */ 9612 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_RESERVED0_MASK 0x0004 9613 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_RESERVED0_ALIGN 0 9614 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_RESERVED0_BITS 1 9615 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_RESERVED0_SHIFT 2 9616 9617 /* sc_x4_final_config_status :: resolved_1 :: brcm64b66_descrambler_enable [01:01] */ 9618 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_BRCM64B66_DESCRAMBLER_ENABLE_MASK 0x0002 9619 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_BRCM64B66_DESCRAMBLER_ENABLE_ALIGN 0 9620 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_BRCM64B66_DESCRAMBLER_ENABLE_BITS 1 9621 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_BRCM64B66_DESCRAMBLER_ENABLE_SHIFT 1 9622 9623 /* sc_x4_final_config_status :: resolved_1 :: reserved1 [00:00] */ 9624 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_RESERVED1_MASK 0x0001 9625 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_RESERVED1_ALIGN 0 9626 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_RESERVED1_BITS 1 9627 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1_RESERVED1_SHIFT 0 9628 9629 9630 /**************************************************************************** 9631 * sc_x4_final_config_status :: resolved_2 9632 */ 9633 /* sc_x4_final_config_status :: resolved_2 :: reserved0 [15:11] */ 9634 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_2_RESERVED0_MASK 0xf800 9635 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_2_RESERVED0_ALIGN 0 9636 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_2_RESERVED0_BITS 5 9637 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_2_RESERVED0_SHIFT 11 9638 9639 /* sc_x4_final_config_status :: resolved_2 :: chk_end_en [10:10] */ 9640 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_2_CHK_END_EN_MASK 0x0400 9641 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_2_CHK_END_EN_ALIGN 0 9642 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_2_CHK_END_EN_BITS 1 9643 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_2_CHK_END_EN_SHIFT 10 9644 9645 /* sc_x4_final_config_status :: resolved_2 :: reserved1 [09:07] */ 9646 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_2_RESERVED1_MASK 0x0380 9647 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_2_RESERVED1_ALIGN 0 9648 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_2_RESERVED1_BITS 3 9649 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_2_RESERVED1_SHIFT 7 9650 9651 /* sc_x4_final_config_status :: resolved_2 :: block_sync_mode [06:04] */ 9652 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_2_BLOCK_SYNC_MODE_MASK 0x0070 9653 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_2_BLOCK_SYNC_MODE_ALIGN 0 9654 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_2_BLOCK_SYNC_MODE_BITS 3 9655 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_2_BLOCK_SYNC_MODE_SHIFT 4 9656 9657 /* sc_x4_final_config_status :: resolved_2 :: reserved2 [03:02] */ 9658 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_2_RESERVED2_MASK 0x000c 9659 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_2_RESERVED2_ALIGN 0 9660 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_2_RESERVED2_BITS 2 9661 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_2_RESERVED2_SHIFT 2 9662 9663 /* sc_x4_final_config_status :: resolved_2 :: reorder_en [01:01] */ 9664 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_2_REORDER_EN_MASK 0x0002 9665 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_2_REORDER_EN_ALIGN 0 9666 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_2_REORDER_EN_BITS 1 9667 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_2_REORDER_EN_SHIFT 1 9668 9669 /* sc_x4_final_config_status :: resolved_2 :: cl36_en [00:00] */ 9670 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_2_CL36_EN_MASK 0x0001 9671 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_2_CL36_EN_ALIGN 0 9672 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_2_CL36_EN_BITS 1 9673 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_2_CL36_EN_SHIFT 0 9674 9675 9676 /**************************************************************************** 9677 * sc_x4_final_config_status :: resolved_3 9678 */ 9679 /* sc_x4_final_config_status :: resolved_3 :: sgmii_spd_switch [15:15] */ 9680 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_3_SGMII_SPD_SWITCH_MASK 0x8000 9681 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_3_SGMII_SPD_SWITCH_ALIGN 0 9682 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_3_SGMII_SPD_SWITCH_BITS 1 9683 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_3_SGMII_SPD_SWITCH_SHIFT 15 9684 9685 /* sc_x4_final_config_status :: resolved_3 :: reserved0 [14:14] */ 9686 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_3_RESERVED0_MASK 0x4000 9687 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_3_RESERVED0_ALIGN 0 9688 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_3_RESERVED0_BITS 1 9689 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_3_RESERVED0_SHIFT 14 9690 9691 /* sc_x4_final_config_status :: resolved_3 :: clockcnt0 [13:00] */ 9692 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_3_CLOCKCNT0_MASK 0x3fff 9693 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_3_CLOCKCNT0_ALIGN 0 9694 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_3_CLOCKCNT0_BITS 14 9695 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_3_CLOCKCNT0_SHIFT 0 9696 9697 9698 /**************************************************************************** 9699 * sc_x4_final_config_status :: resolved_4 9700 */ 9701 /* sc_x4_final_config_status :: resolved_4 :: reserved0 [15:08] */ 9702 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_4_RESERVED0_MASK 0xff00 9703 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_4_RESERVED0_ALIGN 0 9704 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_4_RESERVED0_BITS 8 9705 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_4_RESERVED0_SHIFT 8 9706 9707 /* sc_x4_final_config_status :: resolved_4 :: clockcnt1 [07:00] */ 9708 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_4_CLOCKCNT1_MASK 0x00ff 9709 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_4_CLOCKCNT1_ALIGN 0 9710 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_4_CLOCKCNT1_BITS 8 9711 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_4_CLOCKCNT1_SHIFT 0 9712 9713 9714 /**************************************************************************** 9715 * sc_x4_final_config_status :: resolved_5 9716 */ 9717 /* sc_x4_final_config_status :: resolved_5 :: reserved0 [15:14] */ 9718 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_5_RESERVED0_MASK 0xc000 9719 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_5_RESERVED0_ALIGN 0 9720 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_5_RESERVED0_BITS 2 9721 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_5_RESERVED0_SHIFT 14 9722 9723 /* sc_x4_final_config_status :: resolved_5 :: loopcnt0 [13:06] */ 9724 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_5_LOOPCNT0_MASK 0x3fc0 9725 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_5_LOOPCNT0_ALIGN 0 9726 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_5_LOOPCNT0_BITS 8 9727 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_5_LOOPCNT0_SHIFT 6 9728 9729 /* sc_x4_final_config_status :: resolved_5 :: loopcnt1 [05:00] */ 9730 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_5_LOOPCNT1_MASK 0x003f 9731 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_5_LOOPCNT1_ALIGN 0 9732 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_5_LOOPCNT1_BITS 6 9733 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_5_LOOPCNT1_SHIFT 0 9734 9735 9736 /**************************************************************************** 9737 * sc_x4_final_config_status :: resolved_6 9738 */ 9739 /* sc_x4_final_config_status :: resolved_6 :: reserved0 [15:13] */ 9740 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_6_RESERVED0_MASK 0xe000 9741 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_6_RESERVED0_ALIGN 0 9742 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_6_RESERVED0_BITS 3 9743 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_6_RESERVED0_SHIFT 13 9744 9745 /* sc_x4_final_config_status :: resolved_6 :: mac_creditgencnt [12:00] */ 9746 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_6_MAC_CREDITGENCNT_MASK 0x1fff 9747 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_6_MAC_CREDITGENCNT_ALIGN 0 9748 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_6_MAC_CREDITGENCNT_BITS 13 9749 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_6_MAC_CREDITGENCNT_SHIFT 0 9750 9751 9752 /**************************************************************************** 9753 * sc_x4_final_config_status :: resolved_7 9754 */ 9755 /* sc_x4_final_config_status :: resolved_7 :: replication_cnt [15:15] */ 9756 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_REPLICATION_CNT_MASK 0x8000 9757 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_REPLICATION_CNT_ALIGN 0 9758 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_REPLICATION_CNT_BITS 1 9759 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_REPLICATION_CNT_SHIFT 15 9760 9761 /* sc_x4_final_config_status :: resolved_7 :: pcs_creditenable [14:14] */ 9762 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_PCS_CREDITENABLE_MASK 0x4000 9763 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_PCS_CREDITENABLE_ALIGN 0 9764 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_PCS_CREDITENABLE_BITS 1 9765 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_PCS_CREDITENABLE_SHIFT 14 9766 9767 /* sc_x4_final_config_status :: resolved_7 :: pcs_clockcnt0 [13:00] */ 9768 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_PCS_CLOCKCNT0_MASK 0x3fff 9769 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_PCS_CLOCKCNT0_ALIGN 0 9770 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_PCS_CLOCKCNT0_BITS 14 9771 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7_PCS_CLOCKCNT0_SHIFT 0 9772 9773 9774 /**************************************************************************** 9775 * sc_x4_final_config_status :: resolved_8 9776 */ 9777 /* sc_x4_final_config_status :: resolved_8 :: reserved0 [15:13] */ 9778 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_8_RESERVED0_MASK 0xe000 9779 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_8_RESERVED0_ALIGN 0 9780 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_8_RESERVED0_BITS 3 9781 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_8_RESERVED0_SHIFT 13 9782 9783 /* sc_x4_final_config_status :: resolved_8 :: pcs_creditgencnt [12:00] */ 9784 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_8_PCS_CREDITGENCNT_MASK 0x1fff 9785 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_8_PCS_CREDITGENCNT_ALIGN 0 9786 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_8_PCS_CREDITGENCNT_BITS 13 9787 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_8_PCS_CREDITGENCNT_SHIFT 0 9788 9789 9790 /**************************************************************************** 9791 * TSCE_TSCE_USER4_TX_X4_Credit0 9792 */ 9793 /**************************************************************************** 9794 * TX_X4_Credit0 :: credit0 9795 */ 9796 /* TX_X4_Credit0 :: credit0 :: sgmii_spd_switch [15:15] */ 9797 #define TX_X4_CREDIT0_CREDIT0_SGMII_SPD_SWITCH_MASK 0x8000 9798 #define TX_X4_CREDIT0_CREDIT0_SGMII_SPD_SWITCH_ALIGN 0 9799 #define TX_X4_CREDIT0_CREDIT0_SGMII_SPD_SWITCH_BITS 1 9800 #define TX_X4_CREDIT0_CREDIT0_SGMII_SPD_SWITCH_SHIFT 15 9801 9802 /* TX_X4_Credit0 :: credit0 :: creditenable [14:14] */ 9803 #define TX_X4_CREDIT0_CREDIT0_CREDITENABLE_MASK 0x4000 9804 #define TX_X4_CREDIT0_CREDIT0_CREDITENABLE_ALIGN 0 9805 #define TX_X4_CREDIT0_CREDIT0_CREDITENABLE_BITS 1 9806 #define TX_X4_CREDIT0_CREDIT0_CREDITENABLE_SHIFT 14 9807 9808 /* TX_X4_Credit0 :: credit0 :: clockcnt0 [13:00] */ 9809 #define TX_X4_CREDIT0_CREDIT0_CLOCKCNT0_MASK 0x3fff 9810 #define TX_X4_CREDIT0_CREDIT0_CLOCKCNT0_ALIGN 0 9811 #define TX_X4_CREDIT0_CREDIT0_CLOCKCNT0_BITS 14 9812 #define TX_X4_CREDIT0_CREDIT0_CLOCKCNT0_SHIFT 0 9813 9814 9815 /**************************************************************************** 9816 * TX_X4_Credit0 :: credit1 9817 */ 9818 /* TX_X4_Credit0 :: credit1 :: reserved0 [15:08] */ 9819 #define TX_X4_CREDIT0_CREDIT1_RESERVED0_MASK 0xff00 9820 #define TX_X4_CREDIT0_CREDIT1_RESERVED0_ALIGN 0 9821 #define TX_X4_CREDIT0_CREDIT1_RESERVED0_BITS 8 9822 #define TX_X4_CREDIT0_CREDIT1_RESERVED0_SHIFT 8 9823 9824 /* TX_X4_Credit0 :: credit1 :: clockcnt1 [07:00] */ 9825 #define TX_X4_CREDIT0_CREDIT1_CLOCKCNT1_MASK 0x00ff 9826 #define TX_X4_CREDIT0_CREDIT1_CLOCKCNT1_ALIGN 0 9827 #define TX_X4_CREDIT0_CREDIT1_CLOCKCNT1_BITS 8 9828 #define TX_X4_CREDIT0_CREDIT1_CLOCKCNT1_SHIFT 0 9829 9830 9831 /**************************************************************************** 9832 * TX_X4_Credit0 :: loopcnt 9833 */ 9834 /* TX_X4_Credit0 :: loopcnt :: reserved0 [15:14] */ 9835 #define TX_X4_CREDIT0_LOOPCNT_RESERVED0_MASK 0xc000 9836 #define TX_X4_CREDIT0_LOOPCNT_RESERVED0_ALIGN 0 9837 #define TX_X4_CREDIT0_LOOPCNT_RESERVED0_BITS 2 9838 #define TX_X4_CREDIT0_LOOPCNT_RESERVED0_SHIFT 14 9839 9840 /* TX_X4_Credit0 :: loopcnt :: loopcnt0 [13:06] */ 9841 #define TX_X4_CREDIT0_LOOPCNT_LOOPCNT0_MASK 0x3fc0 9842 #define TX_X4_CREDIT0_LOOPCNT_LOOPCNT0_ALIGN 0 9843 #define TX_X4_CREDIT0_LOOPCNT_LOOPCNT0_BITS 8 9844 #define TX_X4_CREDIT0_LOOPCNT_LOOPCNT0_SHIFT 6 9845 9846 /* TX_X4_Credit0 :: loopcnt :: loopcnt1 [05:00] */ 9847 #define TX_X4_CREDIT0_LOOPCNT_LOOPCNT1_MASK 0x003f 9848 #define TX_X4_CREDIT0_LOOPCNT_LOOPCNT1_ALIGN 0 9849 #define TX_X4_CREDIT0_LOOPCNT_LOOPCNT1_BITS 6 9850 #define TX_X4_CREDIT0_LOOPCNT_LOOPCNT1_SHIFT 0 9851 9852 9853 /**************************************************************************** 9854 * TX_X4_Credit0 :: mac_creditgencnt 9855 */ 9856 /* TX_X4_Credit0 :: mac_creditgencnt :: reserved0 [15:13] */ 9857 #define TX_X4_CREDIT0_MAC_CREDITGENCNT_RESERVED0_MASK 0xe000 9858 #define TX_X4_CREDIT0_MAC_CREDITGENCNT_RESERVED0_ALIGN 0 9859 #define TX_X4_CREDIT0_MAC_CREDITGENCNT_RESERVED0_BITS 3 9860 #define TX_X4_CREDIT0_MAC_CREDITGENCNT_RESERVED0_SHIFT 13 9861 9862 /* TX_X4_Credit0 :: mac_creditgencnt :: mac_creditgencnt [12:00] */ 9863 #define TX_X4_CREDIT0_MAC_CREDITGENCNT_MAC_CREDITGENCNT_MASK 0x1fff 9864 #define TX_X4_CREDIT0_MAC_CREDITGENCNT_MAC_CREDITGENCNT_ALIGN 0 9865 #define TX_X4_CREDIT0_MAC_CREDITGENCNT_MAC_CREDITGENCNT_BITS 13 9866 #define TX_X4_CREDIT0_MAC_CREDITGENCNT_MAC_CREDITGENCNT_SHIFT 0 9867 9868 9869 /**************************************************************************** 9870 * TX_X4_Credit0 :: pcs_clockcnt0 9871 */ 9872 /* TX_X4_Credit0 :: pcs_clockcnt0 :: replication_cnt [15:15] */ 9873 #define TX_X4_CREDIT0_PCS_CLOCKCNT0_REPLICATION_CNT_MASK 0x8000 9874 #define TX_X4_CREDIT0_PCS_CLOCKCNT0_REPLICATION_CNT_ALIGN 0 9875 #define TX_X4_CREDIT0_PCS_CLOCKCNT0_REPLICATION_CNT_BITS 1 9876 #define TX_X4_CREDIT0_PCS_CLOCKCNT0_REPLICATION_CNT_SHIFT 15 9877 9878 /* TX_X4_Credit0 :: pcs_clockcnt0 :: pcs_creditenable [14:14] */ 9879 #define TX_X4_CREDIT0_PCS_CLOCKCNT0_PCS_CREDITENABLE_MASK 0x4000 9880 #define TX_X4_CREDIT0_PCS_CLOCKCNT0_PCS_CREDITENABLE_ALIGN 0 9881 #define TX_X4_CREDIT0_PCS_CLOCKCNT0_PCS_CREDITENABLE_BITS 1 9882 #define TX_X4_CREDIT0_PCS_CLOCKCNT0_PCS_CREDITENABLE_SHIFT 14 9883 9884 /* TX_X4_Credit0 :: pcs_clockcnt0 :: pcs_clockcnt0 [13:00] */ 9885 #define TX_X4_CREDIT0_PCS_CLOCKCNT0_PCS_CLOCKCNT0_MASK 0x3fff 9886 #define TX_X4_CREDIT0_PCS_CLOCKCNT0_PCS_CLOCKCNT0_ALIGN 0 9887 #define TX_X4_CREDIT0_PCS_CLOCKCNT0_PCS_CLOCKCNT0_BITS 14 9888 #define TX_X4_CREDIT0_PCS_CLOCKCNT0_PCS_CLOCKCNT0_SHIFT 0 9889 9890 9891 /**************************************************************************** 9892 * TX_X4_Credit0 :: pcs_creditgencnt 9893 */ 9894 /* TX_X4_Credit0 :: pcs_creditgencnt :: reserved0 [15:13] */ 9895 #define TX_X4_CREDIT0_PCS_CREDITGENCNT_RESERVED0_MASK 0xe000 9896 #define TX_X4_CREDIT0_PCS_CREDITGENCNT_RESERVED0_ALIGN 0 9897 #define TX_X4_CREDIT0_PCS_CREDITGENCNT_RESERVED0_BITS 3 9898 #define TX_X4_CREDIT0_PCS_CREDITGENCNT_RESERVED0_SHIFT 13 9899 9900 /* TX_X4_Credit0 :: pcs_creditgencnt :: pcs_creditgencnt [12:00] */ 9901 #define TX_X4_CREDIT0_PCS_CREDITGENCNT_PCS_CREDITGENCNT_MASK 0x1fff 9902 #define TX_X4_CREDIT0_PCS_CREDITGENCNT_PCS_CREDITGENCNT_ALIGN 0 9903 #define TX_X4_CREDIT0_PCS_CREDITGENCNT_PCS_CREDITGENCNT_BITS 13 9904 #define TX_X4_CREDIT0_PCS_CREDITGENCNT_PCS_CREDITGENCNT_SHIFT 0 9905 9906 9907 /**************************************************************************** 9908 * TSCE_TSCE_USER4_TX_X4_Control0 9909 */ 9910 /**************************************************************************** 9911 * TX_X4_Control0 :: encode_0 9912 */ 9913 /* TX_X4_Control0 :: encode_0 :: reserved0 [15:13] */ 9914 #define TX_X4_CONTROL0_ENCODE_0_RESERVED0_MASK 0xe000 9915 #define TX_X4_CONTROL0_ENCODE_0_RESERVED0_ALIGN 0 9916 #define TX_X4_CONTROL0_ENCODE_0_RESERVED0_BITS 3 9917 #define TX_X4_CONTROL0_ENCODE_0_RESERVED0_SHIFT 13 9918 9919 /* TX_X4_Control0 :: encode_0 :: HG2_CODEC [12:12] */ 9920 #define TX_X4_CONTROL0_ENCODE_0_HG2_CODEC_MASK 0x1000 9921 #define TX_X4_CONTROL0_ENCODE_0_HG2_CODEC_ALIGN 0 9922 #define TX_X4_CONTROL0_ENCODE_0_HG2_CODEC_BITS 1 9923 #define TX_X4_CONTROL0_ENCODE_0_HG2_CODEC_SHIFT 12 9924 9925 /* TX_X4_Control0 :: encode_0 :: HG2_MESSAGE_INVALID_CODE_ENABLE [11:11] */ 9926 #define TX_X4_CONTROL0_ENCODE_0_HG2_MESSAGE_INVALID_CODE_ENABLE_MASK 0x0800 9927 #define TX_X4_CONTROL0_ENCODE_0_HG2_MESSAGE_INVALID_CODE_ENABLE_ALIGN 0 9928 #define TX_X4_CONTROL0_ENCODE_0_HG2_MESSAGE_INVALID_CODE_ENABLE_BITS 1 9929 #define TX_X4_CONTROL0_ENCODE_0_HG2_MESSAGE_INVALID_CODE_ENABLE_SHIFT 11 9930 9931 /* TX_X4_Control0 :: encode_0 :: HG2_ENABLE [10:10] */ 9932 #define TX_X4_CONTROL0_ENCODE_0_HG2_ENABLE_MASK 0x0400 9933 #define TX_X4_CONTROL0_ENCODE_0_HG2_ENABLE_ALIGN 0 9934 #define TX_X4_CONTROL0_ENCODE_0_HG2_ENABLE_BITS 1 9935 #define TX_X4_CONTROL0_ENCODE_0_HG2_ENABLE_SHIFT 10 9936 9937 /* TX_X4_Control0 :: encode_0 :: cl49_bypass_txsm [09:09] */ 9938 #define TX_X4_CONTROL0_ENCODE_0_CL49_BYPASS_TXSM_MASK 0x0200 9939 #define TX_X4_CONTROL0_ENCODE_0_CL49_BYPASS_TXSM_ALIGN 0 9940 #define TX_X4_CONTROL0_ENCODE_0_CL49_BYPASS_TXSM_BITS 1 9941 #define TX_X4_CONTROL0_ENCODE_0_CL49_BYPASS_TXSM_SHIFT 9 9942 9943 /* TX_X4_Control0 :: encode_0 :: reserved1 [08:07] */ 9944 #define TX_X4_CONTROL0_ENCODE_0_RESERVED1_MASK 0x0180 9945 #define TX_X4_CONTROL0_ENCODE_0_RESERVED1_ALIGN 0 9946 #define TX_X4_CONTROL0_ENCODE_0_RESERVED1_BITS 2 9947 #define TX_X4_CONTROL0_ENCODE_0_RESERVED1_SHIFT 7 9948 9949 /* TX_X4_Control0 :: encode_0 :: cl49_tx_tl_mode [06:05] */ 9950 #define TX_X4_CONTROL0_ENCODE_0_CL49_TX_TL_MODE_MASK 0x0060 9951 #define TX_X4_CONTROL0_ENCODE_0_CL49_TX_TL_MODE_ALIGN 0 9952 #define TX_X4_CONTROL0_ENCODE_0_CL49_TX_TL_MODE_BITS 2 9953 #define TX_X4_CONTROL0_ENCODE_0_CL49_TX_TL_MODE_SHIFT 5 9954 9955 /* TX_X4_Control0 :: encode_0 :: encodeMode [04:02] */ 9956 #define TX_X4_CONTROL0_ENCODE_0_ENCODEMODE_MASK 0x001c 9957 #define TX_X4_CONTROL0_ENCODE_0_ENCODEMODE_ALIGN 0 9958 #define TX_X4_CONTROL0_ENCODE_0_ENCODEMODE_BITS 3 9959 #define TX_X4_CONTROL0_ENCODE_0_ENCODEMODE_SHIFT 2 9960 9961 /* TX_X4_Control0 :: encode_0 :: reserved2 [01:00] */ 9962 #define TX_X4_CONTROL0_ENCODE_0_RESERVED2_MASK 0x0003 9963 #define TX_X4_CONTROL0_ENCODE_0_RESERVED2_ALIGN 0 9964 #define TX_X4_CONTROL0_ENCODE_0_RESERVED2_BITS 2 9965 #define TX_X4_CONTROL0_ENCODE_0_RESERVED2_SHIFT 0 9966 9967 9968 /**************************************************************************** 9969 * TX_X4_Control0 :: encode_1 9970 */ 9971 /* TX_X4_Control0 :: encode_1 :: reserved0 [15:10] */ 9972 #define TX_X4_CONTROL0_ENCODE_1_RESERVED0_MASK 0xfc00 9973 #define TX_X4_CONTROL0_ENCODE_1_RESERVED0_ALIGN 0 9974 #define TX_X4_CONTROL0_ENCODE_1_RESERVED0_BITS 6 9975 #define TX_X4_CONTROL0_ENCODE_1_RESERVED0_SHIFT 10 9976 9977 /* TX_X4_Control0 :: encode_1 :: catch_all_8b10b_dis [09:09] */ 9978 #define TX_X4_CONTROL0_ENCODE_1_CATCH_ALL_8B10B_DIS_MASK 0x0200 9979 #define TX_X4_CONTROL0_ENCODE_1_CATCH_ALL_8B10B_DIS_ALIGN 0 9980 #define TX_X4_CONTROL0_ENCODE_1_CATCH_ALL_8B10B_DIS_BITS 1 9981 #define TX_X4_CONTROL0_ENCODE_1_CATCH_ALL_8B10B_DIS_SHIFT 9 9982 9983 /* TX_X4_Control0 :: encode_1 :: prog_tl_en [08:08] */ 9984 #define TX_X4_CONTROL0_ENCODE_1_PROG_TL_EN_MASK 0x0100 9985 #define TX_X4_CONTROL0_ENCODE_1_PROG_TL_EN_ALIGN 0 9986 #define TX_X4_CONTROL0_ENCODE_1_PROG_TL_EN_BITS 1 9987 #define TX_X4_CONTROL0_ENCODE_1_PROG_TL_EN_SHIFT 8 9988 9989 /* TX_X4_Control0 :: encode_1 :: prog_tl_char [07:00] */ 9990 #define TX_X4_CONTROL0_ENCODE_1_PROG_TL_CHAR_MASK 0x00ff 9991 #define TX_X4_CONTROL0_ENCODE_1_PROG_TL_CHAR_ALIGN 0 9992 #define TX_X4_CONTROL0_ENCODE_1_PROG_TL_CHAR_BITS 8 9993 #define TX_X4_CONTROL0_ENCODE_1_PROG_TL_CHAR_SHIFT 0 9994 9995 9996 /**************************************************************************** 9997 * TX_X4_Control0 :: misc 9998 */ 9999 /* TX_X4_Control0 :: misc :: scr_mode [15:14] */ 10000 #define TX_X4_CONTROL0_MISC_SCR_MODE_MASK 0xc000 10001 #define TX_X4_CONTROL0_MISC_SCR_MODE_ALIGN 0 10002 #define TX_X4_CONTROL0_MISC_SCR_MODE_BITS 2 10003 #define TX_X4_CONTROL0_MISC_SCR_MODE_SHIFT 14 10004 10005 /* TX_X4_Control0 :: misc :: reserved0 [13:11] */ 10006 #define TX_X4_CONTROL0_MISC_RESERVED0_MASK 0x3800 10007 #define TX_X4_CONTROL0_MISC_RESERVED0_ALIGN 0 10008 #define TX_X4_CONTROL0_MISC_RESERVED0_BITS 3 10009 #define TX_X4_CONTROL0_MISC_RESERVED0_SHIFT 11 10010 10011 /* TX_X4_Control0 :: misc :: fec_enable [10:10] */ 10012 #define TX_X4_CONTROL0_MISC_FEC_ENABLE_MASK 0x0400 10013 #define TX_X4_CONTROL0_MISC_FEC_ENABLE_ALIGN 0 10014 #define TX_X4_CONTROL0_MISC_FEC_ENABLE_BITS 1 10015 #define TX_X4_CONTROL0_MISC_FEC_ENABLE_SHIFT 10 10016 10017 /* TX_X4_Control0 :: misc :: reserved1 [09:09] */ 10018 #define TX_X4_CONTROL0_MISC_RESERVED1_MASK 0x0200 10019 #define TX_X4_CONTROL0_MISC_RESERVED1_ALIGN 0 10020 #define TX_X4_CONTROL0_MISC_RESERVED1_BITS 1 10021 #define TX_X4_CONTROL0_MISC_RESERVED1_SHIFT 9 10022 10023 /* TX_X4_Control0 :: misc :: cl49_tx_li_enable [08:08] */ 10024 #define TX_X4_CONTROL0_MISC_CL49_TX_LI_ENABLE_MASK 0x0100 10025 #define TX_X4_CONTROL0_MISC_CL49_TX_LI_ENABLE_ALIGN 0 10026 #define TX_X4_CONTROL0_MISC_CL49_TX_LI_ENABLE_BITS 1 10027 #define TX_X4_CONTROL0_MISC_CL49_TX_LI_ENABLE_SHIFT 8 10028 10029 /* TX_X4_Control0 :: misc :: cl49_tx_lf_enable [07:07] */ 10030 #define TX_X4_CONTROL0_MISC_CL49_TX_LF_ENABLE_MASK 0x0080 10031 #define TX_X4_CONTROL0_MISC_CL49_TX_LF_ENABLE_ALIGN 0 10032 #define TX_X4_CONTROL0_MISC_CL49_TX_LF_ENABLE_BITS 1 10033 #define TX_X4_CONTROL0_MISC_CL49_TX_LF_ENABLE_SHIFT 7 10034 10035 /* TX_X4_Control0 :: misc :: cl49_tx_rf_enable [06:06] */ 10036 #define TX_X4_CONTROL0_MISC_CL49_TX_RF_ENABLE_MASK 0x0040 10037 #define TX_X4_CONTROL0_MISC_CL49_TX_RF_ENABLE_ALIGN 0 10038 #define TX_X4_CONTROL0_MISC_CL49_TX_RF_ENABLE_BITS 1 10039 #define TX_X4_CONTROL0_MISC_CL49_TX_RF_ENABLE_SHIFT 6 10040 10041 /* TX_X4_Control0 :: misc :: reserved2 [05:04] */ 10042 #define TX_X4_CONTROL0_MISC_RESERVED2_MASK 0x0030 10043 #define TX_X4_CONTROL0_MISC_RESERVED2_ALIGN 0 10044 #define TX_X4_CONTROL0_MISC_RESERVED2_BITS 2 10045 #define TX_X4_CONTROL0_MISC_RESERVED2_SHIFT 4 10046 10047 /* TX_X4_Control0 :: misc :: tx_fifo_watermark [03:02] */ 10048 #define TX_X4_CONTROL0_MISC_TX_FIFO_WATERMARK_MASK 0x000c 10049 #define TX_X4_CONTROL0_MISC_TX_FIFO_WATERMARK_ALIGN 0 10050 #define TX_X4_CONTROL0_MISC_TX_FIFO_WATERMARK_BITS 2 10051 #define TX_X4_CONTROL0_MISC_TX_FIFO_WATERMARK_SHIFT 2 10052 10053 /* TX_X4_Control0 :: misc :: rstb_tx_lane [01:01] */ 10054 #define TX_X4_CONTROL0_MISC_RSTB_TX_LANE_MASK 0x0002 10055 #define TX_X4_CONTROL0_MISC_RSTB_TX_LANE_ALIGN 0 10056 #define TX_X4_CONTROL0_MISC_RSTB_TX_LANE_BITS 1 10057 #define TX_X4_CONTROL0_MISC_RSTB_TX_LANE_SHIFT 1 10058 10059 /* TX_X4_Control0 :: misc :: enable_tx_lane [00:00] */ 10060 #define TX_X4_CONTROL0_MISC_ENABLE_TX_LANE_MASK 0x0001 10061 #define TX_X4_CONTROL0_MISC_ENABLE_TX_LANE_ALIGN 0 10062 #define TX_X4_CONTROL0_MISC_ENABLE_TX_LANE_BITS 1 10063 #define TX_X4_CONTROL0_MISC_ENABLE_TX_LANE_SHIFT 0 10064 10065 10066 /**************************************************************************** 10067 * TSCE_TSCE_USER4_TX_X4_Status0 10068 */ 10069 /**************************************************************************** 10070 * TX_X4_Status0 :: encode_status_0 10071 */ 10072 /* TX_X4_Status0 :: encode_status_0 :: cl49_t_type_coded [15:12] */ 10073 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_T_TYPE_CODED_MASK 0xf000 10074 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_T_TYPE_CODED_ALIGN 0 10075 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_T_TYPE_CODED_BITS 4 10076 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_T_TYPE_CODED_SHIFT 12 10077 10078 /* TX_X4_Status0 :: encode_status_0 :: cl49_tx_fault_det [11:11] */ 10079 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_TX_FAULT_DET_MASK 0x0800 10080 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_TX_FAULT_DET_ALIGN 0 10081 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_TX_FAULT_DET_BITS 1 10082 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_TX_FAULT_DET_SHIFT 11 10083 10084 /* TX_X4_Status0 :: encode_status_0 :: cl49_ltxsm_state [10:03] */ 10085 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_LTXSM_STATE_MASK 0x07f8 10086 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_LTXSM_STATE_ALIGN 0 10087 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_LTXSM_STATE_BITS 8 10088 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_LTXSM_STATE_SHIFT 3 10089 10090 /* TX_X4_Status0 :: encode_status_0 :: cl49_txsm_state [02:00] */ 10091 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_TXSM_STATE_MASK 0x0007 10092 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_TXSM_STATE_ALIGN 0 10093 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_TXSM_STATE_BITS 3 10094 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_TXSM_STATE_SHIFT 0 10095 10096 10097 /**************************************************************************** 10098 * TX_X4_Status0 :: pcs_status 10099 */ 10100 /* TX_X4_Status0 :: pcs_status :: reserved0 [15:09] */ 10101 #define TX_X4_STATUS0_PCS_STATUS_RESERVED0_MASK 0xfe00 10102 #define TX_X4_STATUS0_PCS_STATUS_RESERVED0_ALIGN 0 10103 #define TX_X4_STATUS0_PCS_STATUS_RESERVED0_BITS 7 10104 #define TX_X4_STATUS0_PCS_STATUS_RESERVED0_SHIFT 9 10105 10106 /* TX_X4_Status0 :: pcs_status :: tx_LOCAL_FAULT [08:08] */ 10107 #define TX_X4_STATUS0_PCS_STATUS_TX_LOCAL_FAULT_MASK 0x0100 10108 #define TX_X4_STATUS0_PCS_STATUS_TX_LOCAL_FAULT_ALIGN 0 10109 #define TX_X4_STATUS0_PCS_STATUS_TX_LOCAL_FAULT_BITS 1 10110 #define TX_X4_STATUS0_PCS_STATUS_TX_LOCAL_FAULT_SHIFT 8 10111 10112 /* TX_X4_Status0 :: pcs_status :: tx_REMOTE_FAULT [07:07] */ 10113 #define TX_X4_STATUS0_PCS_STATUS_TX_REMOTE_FAULT_MASK 0x0080 10114 #define TX_X4_STATUS0_PCS_STATUS_TX_REMOTE_FAULT_ALIGN 0 10115 #define TX_X4_STATUS0_PCS_STATUS_TX_REMOTE_FAULT_BITS 1 10116 #define TX_X4_STATUS0_PCS_STATUS_TX_REMOTE_FAULT_SHIFT 7 10117 10118 /* TX_X4_Status0 :: pcs_status :: tx_LINK_INTERRUPT [06:06] */ 10119 #define TX_X4_STATUS0_PCS_STATUS_TX_LINK_INTERRUPT_MASK 0x0040 10120 #define TX_X4_STATUS0_PCS_STATUS_TX_LINK_INTERRUPT_ALIGN 0 10121 #define TX_X4_STATUS0_PCS_STATUS_TX_LINK_INTERRUPT_BITS 1 10122 #define TX_X4_STATUS0_PCS_STATUS_TX_LINK_INTERRUPT_SHIFT 6 10123 10124 /* TX_X4_Status0 :: pcs_status :: tx_LPI_RECEIVED [05:05] */ 10125 #define TX_X4_STATUS0_PCS_STATUS_TX_LPI_RECEIVED_MASK 0x0020 10126 #define TX_X4_STATUS0_PCS_STATUS_TX_LPI_RECEIVED_ALIGN 0 10127 #define TX_X4_STATUS0_PCS_STATUS_TX_LPI_RECEIVED_BITS 1 10128 #define TX_X4_STATUS0_PCS_STATUS_TX_LPI_RECEIVED_SHIFT 5 10129 10130 /* TX_X4_Status0 :: pcs_status :: LINK_INTERRUPT_LH [04:04] */ 10131 #define TX_X4_STATUS0_PCS_STATUS_LINK_INTERRUPT_LH_MASK 0x0010 10132 #define TX_X4_STATUS0_PCS_STATUS_LINK_INTERRUPT_LH_ALIGN 0 10133 #define TX_X4_STATUS0_PCS_STATUS_LINK_INTERRUPT_LH_BITS 1 10134 #define TX_X4_STATUS0_PCS_STATUS_LINK_INTERRUPT_LH_SHIFT 4 10135 10136 /* TX_X4_Status0 :: pcs_status :: LOCAL_FAULT_LH [03:03] */ 10137 #define TX_X4_STATUS0_PCS_STATUS_LOCAL_FAULT_LH_MASK 0x0008 10138 #define TX_X4_STATUS0_PCS_STATUS_LOCAL_FAULT_LH_ALIGN 0 10139 #define TX_X4_STATUS0_PCS_STATUS_LOCAL_FAULT_LH_BITS 1 10140 #define TX_X4_STATUS0_PCS_STATUS_LOCAL_FAULT_LH_SHIFT 3 10141 10142 /* TX_X4_Status0 :: pcs_status :: REMOTE_FAULT_LH [02:02] */ 10143 #define TX_X4_STATUS0_PCS_STATUS_REMOTE_FAULT_LH_MASK 0x0004 10144 #define TX_X4_STATUS0_PCS_STATUS_REMOTE_FAULT_LH_ALIGN 0 10145 #define TX_X4_STATUS0_PCS_STATUS_REMOTE_FAULT_LH_BITS 1 10146 #define TX_X4_STATUS0_PCS_STATUS_REMOTE_FAULT_LH_SHIFT 2 10147 10148 /* TX_X4_Status0 :: pcs_status :: RESERVED_ORDERED_SET_LH [01:01] */ 10149 #define TX_X4_STATUS0_PCS_STATUS_RESERVED_ORDERED_SET_LH_MASK 0x0002 10150 #define TX_X4_STATUS0_PCS_STATUS_RESERVED_ORDERED_SET_LH_ALIGN 0 10151 #define TX_X4_STATUS0_PCS_STATUS_RESERVED_ORDERED_SET_LH_BITS 1 10152 #define TX_X4_STATUS0_PCS_STATUS_RESERVED_ORDERED_SET_LH_SHIFT 1 10153 10154 /* TX_X4_Status0 :: pcs_status :: LPI_RECEIVED_LH [00:00] */ 10155 #define TX_X4_STATUS0_PCS_STATUS_LPI_RECEIVED_LH_MASK 0x0001 10156 #define TX_X4_STATUS0_PCS_STATUS_LPI_RECEIVED_LH_ALIGN 0 10157 #define TX_X4_STATUS0_PCS_STATUS_LPI_RECEIVED_LH_BITS 1 10158 #define TX_X4_STATUS0_PCS_STATUS_LPI_RECEIVED_LH_SHIFT 0 10159 10160 10161 /**************************************************************************** 10162 * TSCE_TSCE_USER4_RX_X4_Control0 10163 */ 10164 /**************************************************************************** 10165 * RX_X4_Control0 :: pcs_control_0 10166 */ 10167 /* RX_X4_Control0 :: pcs_control_0 :: descramblermode [15:14] */ 10168 #define RX_X4_CONTROL0_PCS_CONTROL_0_DESCRAMBLERMODE_MASK 0xc000 10169 #define RX_X4_CONTROL0_PCS_CONTROL_0_DESCRAMBLERMODE_ALIGN 0 10170 #define RX_X4_CONTROL0_PCS_CONTROL_0_DESCRAMBLERMODE_BITS 2 10171 #define RX_X4_CONTROL0_PCS_CONTROL_0_DESCRAMBLERMODE_SHIFT 14 10172 10173 /* RX_X4_Control0 :: pcs_control_0 :: decodermode [13:11] */ 10174 #define RX_X4_CONTROL0_PCS_CONTROL_0_DECODERMODE_MASK 0x3800 10175 #define RX_X4_CONTROL0_PCS_CONTROL_0_DECODERMODE_ALIGN 0 10176 #define RX_X4_CONTROL0_PCS_CONTROL_0_DECODERMODE_BITS 3 10177 #define RX_X4_CONTROL0_PCS_CONTROL_0_DECODERMODE_SHIFT 11 10178 10179 /* RX_X4_Control0 :: pcs_control_0 :: deskewmode [10:08] */ 10180 #define RX_X4_CONTROL0_PCS_CONTROL_0_DESKEWMODE_MASK 0x0700 10181 #define RX_X4_CONTROL0_PCS_CONTROL_0_DESKEWMODE_ALIGN 0 10182 #define RX_X4_CONTROL0_PCS_CONTROL_0_DESKEWMODE_BITS 3 10183 #define RX_X4_CONTROL0_PCS_CONTROL_0_DESKEWMODE_SHIFT 8 10184 10185 /* RX_X4_Control0 :: pcs_control_0 :: desc2_mode [07:05] */ 10186 #define RX_X4_CONTROL0_PCS_CONTROL_0_DESC2_MODE_MASK 0x00e0 10187 #define RX_X4_CONTROL0_PCS_CONTROL_0_DESC2_MODE_ALIGN 0 10188 #define RX_X4_CONTROL0_PCS_CONTROL_0_DESC2_MODE_BITS 3 10189 #define RX_X4_CONTROL0_PCS_CONTROL_0_DESC2_MODE_SHIFT 5 10190 10191 /* RX_X4_Control0 :: pcs_control_0 :: CL36ByteDeleteMode [04:03] */ 10192 #define RX_X4_CONTROL0_PCS_CONTROL_0_CL36BYTEDELETEMOD16E_MASK 0x0018 10193 #define RX_X4_CONTROL0_PCS_CONTROL_0_CL36BYTEDELETEMOD16E_ALIGN 0 10194 #define RX_X4_CONTROL0_PCS_CONTROL_0_CL36BYTEDELETEMOD16E_BITS 2 10195 #define RX_X4_CONTROL0_PCS_CONTROL_0_CL36BYTEDELETEMOD16E_SHIFT 3 10196 10197 /* RX_X4_Control0 :: pcs_control_0 :: LPI_ENABLE [02:02] */ 10198 #define RX_X4_CONTROL0_PCS_CONTROL_0_LPI_ENABLE_MASK 0x0004 10199 #define RX_X4_CONTROL0_PCS_CONTROL_0_LPI_ENABLE_ALIGN 0 10200 #define RX_X4_CONTROL0_PCS_CONTROL_0_LPI_ENABLE_BITS 1 10201 #define RX_X4_CONTROL0_PCS_CONTROL_0_LPI_ENABLE_SHIFT 2 10202 10203 /* RX_X4_Control0 :: pcs_control_0 :: brcm64b66_descrambler_enable [01:01] */ 10204 #define RX_X4_CONTROL0_PCS_CONTROL_0_BRCM64B66_DESCRAMBLER_ENABLE_MASK 0x0002 10205 #define RX_X4_CONTROL0_PCS_CONTROL_0_BRCM64B66_DESCRAMBLER_ENABLE_ALIGN 0 10206 #define RX_X4_CONTROL0_PCS_CONTROL_0_BRCM64B66_DESCRAMBLER_ENABLE_BITS 1 10207 #define RX_X4_CONTROL0_PCS_CONTROL_0_BRCM64B66_DESCRAMBLER_ENABLE_SHIFT 1 10208 10209 /* RX_X4_Control0 :: pcs_control_0 :: reserved0 [00:00] */ 10210 #define RX_X4_CONTROL0_PCS_CONTROL_0_RESERVED0_MASK 0x0001 10211 #define RX_X4_CONTROL0_PCS_CONTROL_0_RESERVED0_ALIGN 0 10212 #define RX_X4_CONTROL0_PCS_CONTROL_0_RESERVED0_BITS 1 10213 #define RX_X4_CONTROL0_PCS_CONTROL_0_RESERVED0_SHIFT 0 10214 10215 10216 /**************************************************************************** 10217 * RX_X4_Control0 :: fec_0 10218 */ 10219 /* RX_X4_Control0 :: fec_0 :: reserved0 [15:14] */ 10220 #define RX_X4_CONTROL0_FEC_0_RESERVED0_MASK 0xc000 10221 #define RX_X4_CONTROL0_FEC_0_RESERVED0_ALIGN 0 10222 #define RX_X4_CONTROL0_FEC_0_RESERVED0_BITS 2 10223 #define RX_X4_CONTROL0_FEC_0_RESERVED0_SHIFT 14 10224 10225 /* RX_X4_Control0 :: fec_0 :: fec_err_enable [13:13] */ 10226 #define RX_X4_CONTROL0_FEC_0_FEC_ERR_ENABLE_MASK 0x2000 10227 #define RX_X4_CONTROL0_FEC_0_FEC_ERR_ENABLE_ALIGN 0 10228 #define RX_X4_CONTROL0_FEC_0_FEC_ERR_ENABLE_BITS 1 10229 #define RX_X4_CONTROL0_FEC_0_FEC_ERR_ENABLE_SHIFT 13 10230 10231 /* RX_X4_Control0 :: fec_0 :: error_en_ovr [12:12] */ 10232 #define RX_X4_CONTROL0_FEC_0_ERROR_EN_OVR_MASK 0x1000 10233 #define RX_X4_CONTROL0_FEC_0_ERROR_EN_OVR_ALIGN 0 10234 #define RX_X4_CONTROL0_FEC_0_ERROR_EN_OVR_BITS 1 10235 #define RX_X4_CONTROL0_FEC_0_ERROR_EN_OVR_SHIFT 12 10236 10237 /* RX_X4_Control0 :: fec_0 :: error_en_ovr_val [11:11] */ 10238 #define RX_X4_CONTROL0_FEC_0_ERROR_EN_OVR_VAL_MASK 0x0800 10239 #define RX_X4_CONTROL0_FEC_0_ERROR_EN_OVR_VAL_ALIGN 0 10240 #define RX_X4_CONTROL0_FEC_0_ERROR_EN_OVR_VAL_BITS 1 10241 #define RX_X4_CONTROL0_FEC_0_ERROR_EN_OVR_VAL_SHIFT 11 10242 10243 /* RX_X4_Control0 :: fec_0 :: dbg_enable [10:10] */ 10244 #define RX_X4_CONTROL0_FEC_0_DBG_ENABLE_MASK 0x0400 10245 #define RX_X4_CONTROL0_FEC_0_DBG_ENABLE_ALIGN 0 10246 #define RX_X4_CONTROL0_FEC_0_DBG_ENABLE_BITS 1 10247 #define RX_X4_CONTROL0_FEC_0_DBG_ENABLE_SHIFT 10 10248 10249 /* RX_X4_Control0 :: fec_0 :: fast_lock_en [09:09] */ 10250 #define RX_X4_CONTROL0_FEC_0_FAST_LOCK_EN_MASK 0x0200 10251 #define RX_X4_CONTROL0_FEC_0_FAST_LOCK_EN_ALIGN 0 10252 #define RX_X4_CONTROL0_FEC_0_FAST_LOCK_EN_BITS 1 10253 #define RX_X4_CONTROL0_FEC_0_FAST_LOCK_EN_SHIFT 9 10254 10255 /* RX_X4_Control0 :: fec_0 :: reserved1 [08:00] */ 10256 #define RX_X4_CONTROL0_FEC_0_RESERVED1_MASK 0x01ff 10257 #define RX_X4_CONTROL0_FEC_0_RESERVED1_ALIGN 0 10258 #define RX_X4_CONTROL0_FEC_0_RESERVED1_BITS 9 10259 #define RX_X4_CONTROL0_FEC_0_RESERVED1_SHIFT 0 10260 10261 10262 /**************************************************************************** 10263 * RX_X4_Control0 :: fec_1 10264 */ 10265 /* RX_X4_Control0 :: fec_1 :: fec_error_code_all [15:15] */ 10266 #define RX_X4_CONTROL0_FEC_1_FEC_ERROR_CODE_ALL_MASK 0x8000 10267 #define RX_X4_CONTROL0_FEC_1_FEC_ERROR_CODE_ALL_ALIGN 0 10268 #define RX_X4_CONTROL0_FEC_1_FEC_ERROR_CODE_ALL_BITS 1 10269 #define RX_X4_CONTROL0_FEC_1_FEC_ERROR_CODE_ALL_SHIFT 15 10270 10271 /* RX_X4_Control0 :: fec_1 :: good_parity_cnt [14:12] */ 10272 #define RX_X4_CONTROL0_FEC_1_GOOD_PARITY_CNT_MASK 0x7000 10273 #define RX_X4_CONTROL0_FEC_1_GOOD_PARITY_CNT_ALIGN 0 10274 #define RX_X4_CONTROL0_FEC_1_GOOD_PARITY_CNT_BITS 3 10275 #define RX_X4_CONTROL0_FEC_1_GOOD_PARITY_CNT_SHIFT 12 10276 10277 /* RX_X4_Control0 :: fec_1 :: invalid_parity_cnt [11:08] */ 10278 #define RX_X4_CONTROL0_FEC_1_INVALID_PARITY_CNT_MASK 0x0f00 10279 #define RX_X4_CONTROL0_FEC_1_INVALID_PARITY_CNT_ALIGN 0 10280 #define RX_X4_CONTROL0_FEC_1_INVALID_PARITY_CNT_BITS 4 10281 #define RX_X4_CONTROL0_FEC_1_INVALID_PARITY_CNT_SHIFT 8 10282 10283 /* RX_X4_Control0 :: fec_1 :: dec_max_pm [07:02] */ 10284 #define RX_X4_CONTROL0_FEC_1_DEC_MAX_PM_MASK 0x00fc 10285 #define RX_X4_CONTROL0_FEC_1_DEC_MAX_PM_ALIGN 0 10286 #define RX_X4_CONTROL0_FEC_1_DEC_MAX_PM_BITS 6 10287 #define RX_X4_CONTROL0_FEC_1_DEC_MAX_PM_SHIFT 2 10288 10289 /* RX_X4_Control0 :: fec_1 :: burst_err_status_mode [01:01] */ 10290 #define RX_X4_CONTROL0_FEC_1_BURST_ERR_STATUS_MODE_MASK 0x0002 10291 #define RX_X4_CONTROL0_FEC_1_BURST_ERR_STATUS_MODE_ALIGN 0 10292 #define RX_X4_CONTROL0_FEC_1_BURST_ERR_STATUS_MODE_BITS 1 10293 #define RX_X4_CONTROL0_FEC_1_BURST_ERR_STATUS_MODE_SHIFT 1 10294 10295 /* RX_X4_Control0 :: fec_1 :: dbg_err_mode [00:00] */ 10296 #define RX_X4_CONTROL0_FEC_1_DBG_ERR_MODE_MASK 0x0001 10297 #define RX_X4_CONTROL0_FEC_1_DBG_ERR_MODE_ALIGN 0 10298 #define RX_X4_CONTROL0_FEC_1_DBG_ERR_MODE_BITS 1 10299 #define RX_X4_CONTROL0_FEC_1_DBG_ERR_MODE_SHIFT 0 10300 10301 10302 /**************************************************************************** 10303 * RX_X4_Control0 :: fec_2 10304 */ 10305 /* RX_X4_Control0 :: fec_2 :: dec_pm_mode [15:11] */ 10306 #define RX_X4_CONTROL0_FEC_2_DEC_PM_MODE_MASK 0xf800 10307 #define RX_X4_CONTROL0_FEC_2_DEC_PM_MODE_ALIGN 0 10308 #define RX_X4_CONTROL0_FEC_2_DEC_PM_MODE_BITS 5 10309 #define RX_X4_CONTROL0_FEC_2_DEC_PM_MODE_SHIFT 11 10310 10311 /* RX_X4_Control0 :: fec_2 :: dec_19b_burst_gap_count [10:08] */ 10312 #define RX_X4_CONTROL0_FEC_2_DEC_19B_BURST_GAP_COUNT_MASK 0x0700 10313 #define RX_X4_CONTROL0_FEC_2_DEC_19B_BURST_GAP_COUNT_ALIGN 0 10314 #define RX_X4_CONTROL0_FEC_2_DEC_19B_BURST_GAP_COUNT_BITS 3 10315 #define RX_X4_CONTROL0_FEC_2_DEC_19B_BURST_GAP_COUNT_SHIFT 8 10316 10317 /* RX_X4_Control0 :: fec_2 :: dec_18b_burst_gap_count [07:05] */ 10318 #define RX_X4_CONTROL0_FEC_2_DEC_18B_BURST_GAP_COUNT_MASK 0x00e0 10319 #define RX_X4_CONTROL0_FEC_2_DEC_18B_BURST_GAP_COUNT_ALIGN 0 10320 #define RX_X4_CONTROL0_FEC_2_DEC_18B_BURST_GAP_COUNT_BITS 3 10321 #define RX_X4_CONTROL0_FEC_2_DEC_18B_BURST_GAP_COUNT_SHIFT 5 10322 10323 /* RX_X4_Control0 :: fec_2 :: dec_17b_burst_gap_count [04:02] */ 10324 #define RX_X4_CONTROL0_FEC_2_DEC_17B_BURST_GAP_COUNT_MASK 0x001c 10325 #define RX_X4_CONTROL0_FEC_2_DEC_17B_BURST_GAP_COUNT_ALIGN 0 10326 #define RX_X4_CONTROL0_FEC_2_DEC_17B_BURST_GAP_COUNT_BITS 3 10327 #define RX_X4_CONTROL0_FEC_2_DEC_17B_BURST_GAP_COUNT_SHIFT 2 10328 10329 /* RX_X4_Control0 :: fec_2 :: dec_gap_count_mode [01:01] */ 10330 #define RX_X4_CONTROL0_FEC_2_DEC_GAP_COUNT_MODE_MASK 0x0002 10331 #define RX_X4_CONTROL0_FEC_2_DEC_GAP_COUNT_MODE_ALIGN 0 10332 #define RX_X4_CONTROL0_FEC_2_DEC_GAP_COUNT_MODE_BITS 1 10333 #define RX_X4_CONTROL0_FEC_2_DEC_GAP_COUNT_MODE_SHIFT 1 10334 10335 /* RX_X4_Control0 :: fec_2 :: reserved0 [00:00] */ 10336 #define RX_X4_CONTROL0_FEC_2_RESERVED0_MASK 0x0001 10337 #define RX_X4_CONTROL0_FEC_2_RESERVED0_ALIGN 0 10338 #define RX_X4_CONTROL0_FEC_2_RESERVED0_BITS 1 10339 #define RX_X4_CONTROL0_FEC_2_RESERVED0_SHIFT 0 10340 10341 10342 /**************************************************************************** 10343 * RX_X4_Control0 :: decode_control_0 10344 */ 10345 /* RX_X4_Control0 :: decode_control_0 :: bypass_cl49rxsm [15:15] */ 10346 #define RX_X4_CONTROL0_DECODE_CONTROL_0_BYPASS_CL49RXSM_MASK 0x8000 10347 #define RX_X4_CONTROL0_DECODE_CONTROL_0_BYPASS_CL49RXSM_ALIGN 0 10348 #define RX_X4_CONTROL0_DECODE_CONTROL_0_BYPASS_CL49RXSM_BITS 1 10349 #define RX_X4_CONTROL0_DECODE_CONTROL_0_BYPASS_CL49RXSM_SHIFT 15 10350 10351 /* RX_X4_Control0 :: decode_control_0 :: r_test_mode_cfg [14:14] */ 10352 #define RX_X4_CONTROL0_DECODE_CONTROL_0_R_TEST_MODE_CFG_MASK 0x4000 10353 #define RX_X4_CONTROL0_DECODE_CONTROL_0_R_TEST_MODE_CFG_ALIGN 0 10354 #define RX_X4_CONTROL0_DECODE_CONTROL_0_R_TEST_MODE_CFG_BITS 1 10355 #define RX_X4_CONTROL0_DECODE_CONTROL_0_R_TEST_MODE_CFG_SHIFT 14 10356 10357 /* RX_X4_Control0 :: decode_control_0 :: HG2_MESSAGE_INVALID_CODE_ENABLE [13:13] */ 10358 #define RX_X4_CONTROL0_DECODE_CONTROL_0_HG2_MESSAGE_INVALID_CODE_ENABLE_MASK 0x2000 10359 #define RX_X4_CONTROL0_DECODE_CONTROL_0_HG2_MESSAGE_INVALID_CODE_ENABLE_ALIGN 0 10360 #define RX_X4_CONTROL0_DECODE_CONTROL_0_HG2_MESSAGE_INVALID_CODE_ENABLE_BITS 1 10361 #define RX_X4_CONTROL0_DECODE_CONTROL_0_HG2_MESSAGE_INVALID_CODE_ENABLE_SHIFT 13 10362 10363 /* RX_X4_Control0 :: decode_control_0 :: HG2_ENABLE [12:12] */ 10364 #define RX_X4_CONTROL0_DECODE_CONTROL_0_HG2_ENABLE_MASK 0x1000 10365 #define RX_X4_CONTROL0_DECODE_CONTROL_0_HG2_ENABLE_ALIGN 0 10366 #define RX_X4_CONTROL0_DECODE_CONTROL_0_HG2_ENABLE_BITS 1 10367 #define RX_X4_CONTROL0_DECODE_CONTROL_0_HG2_ENABLE_SHIFT 12 10368 10369 /* RX_X4_Control0 :: decode_control_0 :: cl48_syncacq_en [11:11] */ 10370 #define RX_X4_CONTROL0_DECODE_CONTROL_0_CL48_SYNCACQ_EN_MASK 0x0800 10371 #define RX_X4_CONTROL0_DECODE_CONTROL_0_CL48_SYNCACQ_EN_ALIGN 0 10372 #define RX_X4_CONTROL0_DECODE_CONTROL_0_CL48_SYNCACQ_EN_BITS 1 10373 #define RX_X4_CONTROL0_DECODE_CONTROL_0_CL48_SYNCACQ_EN_SHIFT 11 10374 10375 /* RX_X4_Control0 :: decode_control_0 :: cl48_cgbad_en [10:10] */ 10376 #define RX_X4_CONTROL0_DECODE_CONTROL_0_CL48_CGBAD_EN_MASK 0x0400 10377 #define RX_X4_CONTROL0_DECODE_CONTROL_0_CL48_CGBAD_EN_ALIGN 0 10378 #define RX_X4_CONTROL0_DECODE_CONTROL_0_CL48_CGBAD_EN_BITS 1 10379 #define RX_X4_CONTROL0_DECODE_CONTROL_0_CL48_CGBAD_EN_SHIFT 10 10380 10381 /* RX_X4_Control0 :: decode_control_0 :: HG2_CODEC [09:09] */ 10382 #define RX_X4_CONTROL0_DECODE_CONTROL_0_HG2_CODEC_MASK 0x0200 10383 #define RX_X4_CONTROL0_DECODE_CONTROL_0_HG2_CODEC_ALIGN 0 10384 #define RX_X4_CONTROL0_DECODE_CONTROL_0_HG2_CODEC_BITS 1 10385 #define RX_X4_CONTROL0_DECODE_CONTROL_0_HG2_CODEC_SHIFT 9 10386 10387 /* RX_X4_Control0 :: decode_control_0 :: disable_cl49_bermon [08:08] */ 10388 #define RX_X4_CONTROL0_DECODE_CONTROL_0_DISABLE_CL49_BERMON_MASK 0x0100 10389 #define RX_X4_CONTROL0_DECODE_CONTROL_0_DISABLE_CL49_BERMON_ALIGN 0 10390 #define RX_X4_CONTROL0_DECODE_CONTROL_0_DISABLE_CL49_BERMON_BITS 1 10391 #define RX_X4_CONTROL0_DECODE_CONTROL_0_DISABLE_CL49_BERMON_SHIFT 8 10392 10393 /* RX_X4_Control0 :: decode_control_0 :: reserved0 [07:07] */ 10394 #define RX_X4_CONTROL0_DECODE_CONTROL_0_RESERVED0_MASK 0x0080 10395 #define RX_X4_CONTROL0_DECODE_CONTROL_0_RESERVED0_ALIGN 0 10396 #define RX_X4_CONTROL0_DECODE_CONTROL_0_RESERVED0_BITS 1 10397 #define RX_X4_CONTROL0_DECODE_CONTROL_0_RESERVED0_SHIFT 7 10398 10399 /* RX_X4_Control0 :: decode_control_0 :: cl49_rx_li_enable [06:06] */ 10400 #define RX_X4_CONTROL0_DECODE_CONTROL_0_CL49_RX_LI_ENABLE_MASK 0x0040 10401 #define RX_X4_CONTROL0_DECODE_CONTROL_0_CL49_RX_LI_ENABLE_ALIGN 0 10402 #define RX_X4_CONTROL0_DECODE_CONTROL_0_CL49_RX_LI_ENABLE_BITS 1 10403 #define RX_X4_CONTROL0_DECODE_CONTROL_0_CL49_RX_LI_ENABLE_SHIFT 6 10404 10405 /* RX_X4_Control0 :: decode_control_0 :: cl49_rx_lf_enable [05:05] */ 10406 #define RX_X4_CONTROL0_DECODE_CONTROL_0_CL49_RX_LF_ENABLE_MASK 0x0020 10407 #define RX_X4_CONTROL0_DECODE_CONTROL_0_CL49_RX_LF_ENABLE_ALIGN 0 10408 #define RX_X4_CONTROL0_DECODE_CONTROL_0_CL49_RX_LF_ENABLE_BITS 1 10409 #define RX_X4_CONTROL0_DECODE_CONTROL_0_CL49_RX_LF_ENABLE_SHIFT 5 10410 10411 /* RX_X4_Control0 :: decode_control_0 :: cl49_rx_rf_enable [04:04] */ 10412 #define RX_X4_CONTROL0_DECODE_CONTROL_0_CL49_RX_RF_ENABLE_MASK 0x0010 10413 #define RX_X4_CONTROL0_DECODE_CONTROL_0_CL49_RX_RF_ENABLE_ALIGN 0 10414 #define RX_X4_CONTROL0_DECODE_CONTROL_0_CL49_RX_RF_ENABLE_BITS 1 10415 #define RX_X4_CONTROL0_DECODE_CONTROL_0_CL49_RX_RF_ENABLE_SHIFT 4 10416 10417 /* RX_X4_Control0 :: decode_control_0 :: reserved1 [03:03] */ 10418 #define RX_X4_CONTROL0_DECODE_CONTROL_0_RESERVED1_MASK 0x0008 10419 #define RX_X4_CONTROL0_DECODE_CONTROL_0_RESERVED1_ALIGN 0 10420 #define RX_X4_CONTROL0_DECODE_CONTROL_0_RESERVED1_BITS 1 10421 #define RX_X4_CONTROL0_DECODE_CONTROL_0_RESERVED1_SHIFT 3 10422 10423 /* RX_X4_Control0 :: decode_control_0 :: block_sync_mode [02:00] */ 10424 #define RX_X4_CONTROL0_DECODE_CONTROL_0_BLOCK_SYNC_MODE_MASK 0x0007 10425 #define RX_X4_CONTROL0_DECODE_CONTROL_0_BLOCK_SYNC_MODE_ALIGN 0 10426 #define RX_X4_CONTROL0_DECODE_CONTROL_0_BLOCK_SYNC_MODE_BITS 3 10427 #define RX_X4_CONTROL0_DECODE_CONTROL_0_BLOCK_SYNC_MODE_SHIFT 0 10428 10429 10430 /**************************************************************************** 10431 * RX_X4_Control0 :: decode_control_1 10432 */ 10433 /* RX_X4_Control0 :: decode_control_1 :: b66dec_dout_errors_if_bad_sync [15:15] */ 10434 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_DOUT_ERRORS_IF_BAD_SYNC_MASK 0x8000 10435 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_DOUT_ERRORS_IF_BAD_SYNC_ALIGN 0 10436 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_DOUT_ERRORS_IF_BAD_SYNC_BITS 1 10437 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_DOUT_ERRORS_IF_BAD_SYNC_SHIFT 15 10438 10439 /* RX_X4_Control0 :: decode_control_1 :: b66dec_noblocklock_dout_sel [14:13] */ 10440 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_NOBLOCKLOCK_DOUT_SEL_MASK 0x6000 10441 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_NOBLOCKLOCK_DOUT_SEL_ALIGN 0 10442 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_NOBLOCKLOCK_DOUT_SEL_BITS 2 10443 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_NOBLOCKLOCK_DOUT_SEL_SHIFT 13 10444 10445 /* RX_X4_Control0 :: decode_control_1 :: b66dec_prog_tl_en [12:12] */ 10446 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_PROG_TL_EN_MASK 0x1000 10447 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_PROG_TL_EN_ALIGN 0 10448 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_PROG_TL_EN_BITS 1 10449 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_PROG_TL_EN_SHIFT 12 10450 10451 /* RX_X4_Control0 :: decode_control_1 :: b66dec_prog_tl_char [11:04] */ 10452 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_PROG_TL_CHAR_MASK 0x0ff0 10453 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_PROG_TL_CHAR_ALIGN 0 10454 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_PROG_TL_CHAR_BITS 8 10455 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_PROG_TL_CHAR_SHIFT 4 10456 10457 /* RX_X4_Control0 :: decode_control_1 :: b66dec_fault_det_en [03:03] */ 10458 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_FAULT_DET_EN_MASK 0x0008 10459 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_FAULT_DET_EN_ALIGN 0 10460 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_FAULT_DET_EN_BITS 1 10461 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_FAULT_DET_EN_SHIFT 3 10462 10463 /* RX_X4_Control0 :: decode_control_1 :: b66dec_kcode66ErrCount_en [02:02] */ 10464 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_KCODE66ERRCOUNT_EN_MASK 0x0004 10465 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_KCODE66ERRCOUNT_EN_ALIGN 0 10466 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_KCODE66ERRCOUNT_EN_BITS 1 10467 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_KCODE66ERRCOUNT_EN_SHIFT 2 10468 10469 /* RX_X4_Control0 :: decode_control_1 :: b66dec_syncErrCount_en [01:01] */ 10470 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_SYNCERRCOUNT_EN_MASK 0x0002 10471 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_SYNCERRCOUNT_EN_ALIGN 0 10472 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_SYNCERRCOUNT_EN_BITS 1 10473 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_SYNCERRCOUNT_EN_SHIFT 1 10474 10475 /* RX_X4_Control0 :: decode_control_1 :: b66dec_cgbad_en [00:00] */ 10476 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_CGBAD_EN_MASK 0x0001 10477 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_CGBAD_EN_ALIGN 0 10478 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_CGBAD_EN_BITS 1 10479 #define RX_X4_CONTROL0_DECODE_CONTROL_1_B66DEC_CGBAD_EN_SHIFT 0 10480 10481 10482 /**************************************************************************** 10483 * RX_X4_Control0 :: cl36_rx_0 10484 */ 10485 /* RX_X4_Control0 :: cl36_rx_0 :: reserved0 [15:06] */ 10486 #define RX_X4_CONTROL0_CL36_RX_0_RESERVED0_MASK 0xffc0 10487 #define RX_X4_CONTROL0_CL36_RX_0_RESERVED0_ALIGN 0 10488 #define RX_X4_CONTROL0_CL36_RX_0_RESERVED0_BITS 10 10489 #define RX_X4_CONTROL0_CL36_RX_0_RESERVED0_SHIFT 6 10490 10491 /* RX_X4_Control0 :: cl36_rx_0 :: cl36_BER_en [05:05] */ 10492 #define RX_X4_CONTROL0_CL36_RX_0_CL36_BER_EN_MASK 0x0020 10493 #define RX_X4_CONTROL0_CL36_RX_0_CL36_BER_EN_ALIGN 0 10494 #define RX_X4_CONTROL0_CL36_RX_0_CL36_BER_EN_BITS 1 10495 #define RX_X4_CONTROL0_CL36_RX_0_CL36_BER_EN_SHIFT 5 10496 10497 /* RX_X4_Control0 :: cl36_rx_0 :: reserved1 [04:04] */ 10498 #define RX_X4_CONTROL0_CL36_RX_0_RESERVED1_MASK 0x0010 10499 #define RX_X4_CONTROL0_CL36_RX_0_RESERVED1_ALIGN 0 10500 #define RX_X4_CONTROL0_CL36_RX_0_RESERVED1_BITS 1 10501 #define RX_X4_CONTROL0_CL36_RX_0_RESERVED1_SHIFT 4 10502 10503 /* RX_X4_Control0 :: cl36_rx_0 :: cl36_force_comma_align_enable [03:03] */ 10504 #define RX_X4_CONTROL0_CL36_RX_0_CL36_FORCE_COMMA_ALIGN_ENABLE_MASK 0x0008 10505 #define RX_X4_CONTROL0_CL36_RX_0_CL36_FORCE_COMMA_ALIGN_ENABLE_ALIGN 0 10506 #define RX_X4_CONTROL0_CL36_RX_0_CL36_FORCE_COMMA_ALIGN_ENABLE_BITS 1 10507 #define RX_X4_CONTROL0_CL36_RX_0_CL36_FORCE_COMMA_ALIGN_ENABLE_SHIFT 3 10508 10509 /* RX_X4_Control0 :: cl36_rx_0 :: disable_carrier_extend [02:02] */ 10510 #define RX_X4_CONTROL0_CL36_RX_0_DISABLE_CARRIER_EXTEND_MASK 0x0004 10511 #define RX_X4_CONTROL0_CL36_RX_0_DISABLE_CARRIER_EXTEND_ALIGN 0 10512 #define RX_X4_CONTROL0_CL36_RX_0_DISABLE_CARRIER_EXTEND_BITS 1 10513 #define RX_X4_CONTROL0_CL36_RX_0_DISABLE_CARRIER_EXTEND_SHIFT 2 10514 10515 /* RX_X4_Control0 :: cl36_rx_0 :: reorder_en [01:01] */ 10516 #define RX_X4_CONTROL0_CL36_RX_0_REORDER_EN_MASK 0x0002 10517 #define RX_X4_CONTROL0_CL36_RX_0_REORDER_EN_ALIGN 0 10518 #define RX_X4_CONTROL0_CL36_RX_0_REORDER_EN_BITS 1 10519 #define RX_X4_CONTROL0_CL36_RX_0_REORDER_EN_SHIFT 1 10520 10521 /* RX_X4_Control0 :: cl36_rx_0 :: cl36_en [00:00] */ 10522 #define RX_X4_CONTROL0_CL36_RX_0_CL36_EN_MASK 0x0001 10523 #define RX_X4_CONTROL0_CL36_RX_0_CL36_EN_ALIGN 0 10524 #define RX_X4_CONTROL0_CL36_RX_0_CL36_EN_BITS 1 10525 #define RX_X4_CONTROL0_CL36_RX_0_CL36_EN_SHIFT 0 10526 10527 10528 /**************************************************************************** 10529 * RX_X4_Control0 :: pma_control_0 10530 */ 10531 /* RX_X4_Control0 :: pma_control_0 :: reserved0 [15:07] */ 10532 #define RX_X4_CONTROL0_PMA_CONTROL_0_RESERVED0_MASK 0xff80 10533 #define RX_X4_CONTROL0_PMA_CONTROL_0_RESERVED0_ALIGN 0 10534 #define RX_X4_CONTROL0_PMA_CONTROL_0_RESERVED0_BITS 9 10535 #define RX_X4_CONTROL0_PMA_CONTROL_0_RESERVED0_SHIFT 7 10536 10537 /* RX_X4_Control0 :: pma_control_0 :: os_mode [06:03] */ 10538 #define RX_X4_CONTROL0_PMA_CONTROL_0_OS_MODE_MASK 0x0078 10539 #define RX_X4_CONTROL0_PMA_CONTROL_0_OS_MODE_ALIGN 0 10540 #define RX_X4_CONTROL0_PMA_CONTROL_0_OS_MODE_BITS 4 10541 #define RX_X4_CONTROL0_PMA_CONTROL_0_OS_MODE_SHIFT 3 10542 10543 /* RX_X4_Control0 :: pma_control_0 :: reserved1 [02:02] */ 10544 #define RX_X4_CONTROL0_PMA_CONTROL_0_RESERVED1_MASK 0x0004 10545 #define RX_X4_CONTROL0_PMA_CONTROL_0_RESERVED1_ALIGN 0 10546 #define RX_X4_CONTROL0_PMA_CONTROL_0_RESERVED1_BITS 1 10547 #define RX_X4_CONTROL0_PMA_CONTROL_0_RESERVED1_SHIFT 2 10548 10549 /* RX_X4_Control0 :: pma_control_0 :: rx_gbox_afrst_en [01:01] */ 10550 #define RX_X4_CONTROL0_PMA_CONTROL_0_RX_GBOX_AFRST_EN_MASK 0x0002 10551 #define RX_X4_CONTROL0_PMA_CONTROL_0_RX_GBOX_AFRST_EN_ALIGN 0 10552 #define RX_X4_CONTROL0_PMA_CONTROL_0_RX_GBOX_AFRST_EN_BITS 1 10553 #define RX_X4_CONTROL0_PMA_CONTROL_0_RX_GBOX_AFRST_EN_SHIFT 1 10554 10555 /* RX_X4_Control0 :: pma_control_0 :: rstb_lane [00:00] */ 10556 #define RX_X4_CONTROL0_PMA_CONTROL_0_RSTB_LANE_MASK 0x0001 10557 #define RX_X4_CONTROL0_PMA_CONTROL_0_RSTB_LANE_ALIGN 0 10558 #define RX_X4_CONTROL0_PMA_CONTROL_0_RSTB_LANE_BITS 1 10559 #define RX_X4_CONTROL0_PMA_CONTROL_0_RSTB_LANE_SHIFT 0 10560 10561 10562 /**************************************************************************** 10563 * RX_X4_Control0 :: link_control 10564 */ 10565 /* RX_X4_Control0 :: link_control :: reserved0 [15:01] */ 10566 #define RX_X4_CONTROL0_LINK_CONTROL_RESERVED0_MASK 0xfffe 10567 #define RX_X4_CONTROL0_LINK_CONTROL_RESERVED0_ALIGN 0 10568 #define RX_X4_CONTROL0_LINK_CONTROL_RESERVED0_BITS 15 10569 #define RX_X4_CONTROL0_LINK_CONTROL_RESERVED0_SHIFT 1 10570 10571 /* RX_X4_Control0 :: link_control :: latch_linkdown_enable [00:00] */ 10572 #define RX_X4_CONTROL0_LINK_CONTROL_LATCH_LINKDOWN_ENABLE_MASK 0x0001 10573 #define RX_X4_CONTROL0_LINK_CONTROL_LATCH_LINKDOWN_ENABLE_ALIGN 0 10574 #define RX_X4_CONTROL0_LINK_CONTROL_LATCH_LINKDOWN_ENABLE_BITS 1 10575 #define RX_X4_CONTROL0_LINK_CONTROL_LATCH_LINKDOWN_ENABLE_SHIFT 0 10576 10577 10578 /**************************************************************************** 10579 * TSCE_TSCE_USER4_RX_X4_Status0 10580 */ 10581 /**************************************************************************** 10582 * RX_X4_Status0 :: fec_dbg_errL 10583 */ 10584 /* RX_X4_Status0 :: fec_dbg_errL :: dbg_errL [15:00] */ 10585 #define RX_X4_STATUS0_FEC_DBG_ERRL_DBG_ERRL_MASK 0xffff 10586 #define RX_X4_STATUS0_FEC_DBG_ERRL_DBG_ERRL_ALIGN 0 10587 #define RX_X4_STATUS0_FEC_DBG_ERRL_DBG_ERRL_BITS 16 10588 #define RX_X4_STATUS0_FEC_DBG_ERRL_DBG_ERRL_SHIFT 0 10589 10590 10591 /**************************************************************************** 10592 * RX_X4_Status0 :: fec_dbg_erraH 10593 */ 10594 /* RX_X4_Status0 :: fec_dbg_erraH :: dbg_errH [15:00] */ 10595 #define RX_X4_STATUS0_FEC_DBG_ERRAH_DBG_ERRH_MASK 0xffff 10596 #define RX_X4_STATUS0_FEC_DBG_ERRAH_DBG_ERRH_ALIGN 0 10597 #define RX_X4_STATUS0_FEC_DBG_ERRAH_DBG_ERRH_BITS 16 10598 #define RX_X4_STATUS0_FEC_DBG_ERRAH_DBG_ERRH_SHIFT 0 10599 10600 10601 /**************************************************************************** 10602 * RX_X4_Status0 :: fec_burst_err_statusL 10603 */ 10604 /* RX_X4_Status0 :: fec_burst_err_statusL :: burst_err_statusL [15:00] */ 10605 #define RX_X4_STATUS0_FEC_BURST_ERR_STATUSL_BURST_ERR_STATUSL_MASK 0xffff 10606 #define RX_X4_STATUS0_FEC_BURST_ERR_STATUSL_BURST_ERR_STATUSL_ALIGN 0 10607 #define RX_X4_STATUS0_FEC_BURST_ERR_STATUSL_BURST_ERR_STATUSL_BITS 16 10608 #define RX_X4_STATUS0_FEC_BURST_ERR_STATUSL_BURST_ERR_STATUSL_SHIFT 0 10609 10610 10611 /**************************************************************************** 10612 * RX_X4_Status0 :: fec_burst_err_statusH 10613 */ 10614 /* RX_X4_Status0 :: fec_burst_err_statusH :: burst_err_statusH [15:00] */ 10615 #define RX_X4_STATUS0_FEC_BURST_ERR_STATUSH_BURST_ERR_STATUSH_MASK 0xffff 10616 #define RX_X4_STATUS0_FEC_BURST_ERR_STATUSH_BURST_ERR_STATUSH_ALIGN 0 10617 #define RX_X4_STATUS0_FEC_BURST_ERR_STATUSH_BURST_ERR_STATUSH_BITS 16 10618 #define RX_X4_STATUS0_FEC_BURST_ERR_STATUSH_BURST_ERR_STATUSH_SHIFT 0 10619 10620 10621 /**************************************************************************** 10622 * RX_X4_Status0 :: barrel_shifter_state 10623 */ 10624 /* RX_X4_Status0 :: barrel_shifter_state :: reserved0 [15:08] */ 10625 #define RX_X4_STATUS0_BARREL_SHIFTER_STATE_RESERVED0_MASK 0xff00 10626 #define RX_X4_STATUS0_BARREL_SHIFTER_STATE_RESERVED0_ALIGN 0 10627 #define RX_X4_STATUS0_BARREL_SHIFTER_STATE_RESERVED0_BITS 8 10628 #define RX_X4_STATUS0_BARREL_SHIFTER_STATE_RESERVED0_SHIFT 8 10629 10630 /* RX_X4_Status0 :: barrel_shifter_state :: shift_ammount [07:00] */ 10631 #define RX_X4_STATUS0_BARREL_SHIFTER_STATE_SHIFT_AMMOUNT_MASK 0x00ff 10632 #define RX_X4_STATUS0_BARREL_SHIFTER_STATE_SHIFT_AMMOUNT_ALIGN 0 10633 #define RX_X4_STATUS0_BARREL_SHIFTER_STATE_SHIFT_AMMOUNT_BITS 8 10634 #define RX_X4_STATUS0_BARREL_SHIFTER_STATE_SHIFT_AMMOUNT_SHIFT 0 10635 10636 10637 /**************************************************************************** 10638 * RX_X4_Status0 :: cl49_lock_fsm_status 10639 */ 10640 /* RX_X4_Status0 :: cl49_lock_fsm_status :: reserved0 [15:05] */ 10641 #define RX_X4_STATUS0_CL49_LOCK_FSM_STATUS_RESERVED0_MASK 0xffe0 10642 #define RX_X4_STATUS0_CL49_LOCK_FSM_STATUS_RESERVED0_ALIGN 0 10643 #define RX_X4_STATUS0_CL49_LOCK_FSM_STATUS_RESERVED0_BITS 11 10644 #define RX_X4_STATUS0_CL49_LOCK_FSM_STATUS_RESERVED0_SHIFT 5 10645 10646 /* RX_X4_Status0 :: cl49_lock_fsm_status :: lsm_his_state [04:02] */ 10647 #define RX_X4_STATUS0_CL49_LOCK_FSM_STATUS_LSM_HIS_STATE_MASK 0x001c 10648 #define RX_X4_STATUS0_CL49_LOCK_FSM_STATUS_LSM_HIS_STATE_ALIGN 0 10649 #define RX_X4_STATUS0_CL49_LOCK_FSM_STATUS_LSM_HIS_STATE_BITS 3 10650 #define RX_X4_STATUS0_CL49_LOCK_FSM_STATUS_LSM_HIS_STATE_SHIFT 2 10651 10652 /* RX_X4_Status0 :: cl49_lock_fsm_status :: lsm_curr_state [01:00] */ 10653 #define RX_X4_STATUS0_CL49_LOCK_FSM_STATUS_LSM_CURR_STATE_MASK 0x0003 10654 #define RX_X4_STATUS0_CL49_LOCK_FSM_STATUS_LSM_CURR_STATE_ALIGN 0 10655 #define RX_X4_STATUS0_CL49_LOCK_FSM_STATUS_LSM_CURR_STATE_BITS 2 10656 #define RX_X4_STATUS0_CL49_LOCK_FSM_STATUS_LSM_CURR_STATE_SHIFT 0 10657 10658 10659 /**************************************************************************** 10660 * RX_X4_Status0 :: decode_status_0 10661 */ 10662 /* RX_X4_Status0 :: decode_status_0 :: cl49_r_type_coded [15:12] */ 10663 #define RX_X4_STATUS0_DECODE_STATUS_0_CL49_R_TYPE_CODED_MASK 0xf000 10664 #define RX_X4_STATUS0_DECODE_STATUS_0_CL49_R_TYPE_CODED_ALIGN 0 10665 #define RX_X4_STATUS0_DECODE_STATUS_0_CL49_R_TYPE_CODED_BITS 4 10666 #define RX_X4_STATUS0_DECODE_STATUS_0_CL49_R_TYPE_CODED_SHIFT 12 10667 10668 /* RX_X4_Status0 :: decode_status_0 :: reserved0 [11:11] */ 10669 #define RX_X4_STATUS0_DECODE_STATUS_0_RESERVED0_MASK 0x0800 10670 #define RX_X4_STATUS0_DECODE_STATUS_0_RESERVED0_ALIGN 0 10671 #define RX_X4_STATUS0_DECODE_STATUS_0_RESERVED0_BITS 1 10672 #define RX_X4_STATUS0_DECODE_STATUS_0_RESERVED0_SHIFT 11 10673 10674 /* RX_X4_Status0 :: decode_status_0 :: cl49_rxsm_history_state [10:03] */ 10675 #define RX_X4_STATUS0_DECODE_STATUS_0_CL49_RXSM_HISTORY_STATE_MASK 0x07f8 10676 #define RX_X4_STATUS0_DECODE_STATUS_0_CL49_RXSM_HISTORY_STATE_ALIGN 0 10677 #define RX_X4_STATUS0_DECODE_STATUS_0_CL49_RXSM_HISTORY_STATE_BITS 8 10678 #define RX_X4_STATUS0_DECODE_STATUS_0_CL49_RXSM_HISTORY_STATE_SHIFT 3 10679 10680 /* RX_X4_Status0 :: decode_status_0 :: cl49_rxsm_current_state [02:00] */ 10681 #define RX_X4_STATUS0_DECODE_STATUS_0_CL49_RXSM_CURRENT_STATE_MASK 0x0007 10682 #define RX_X4_STATUS0_DECODE_STATUS_0_CL49_RXSM_CURRENT_STATE_ALIGN 0 10683 #define RX_X4_STATUS0_DECODE_STATUS_0_CL49_RXSM_CURRENT_STATE_BITS 3 10684 #define RX_X4_STATUS0_DECODE_STATUS_0_CL49_RXSM_CURRENT_STATE_SHIFT 0 10685 10686 10687 /**************************************************************************** 10688 * RX_X4_Status0 :: decode_status_1 10689 */ 10690 /* RX_X4_Status0 :: decode_status_1 :: reserved0 [15:10] */ 10691 #define RX_X4_STATUS0_DECODE_STATUS_1_RESERVED0_MASK 0xfc00 10692 #define RX_X4_STATUS0_DECODE_STATUS_1_RESERVED0_ALIGN 0 10693 #define RX_X4_STATUS0_DECODE_STATUS_1_RESERVED0_BITS 6 10694 #define RX_X4_STATUS0_DECODE_STATUS_1_RESERVED0_SHIFT 10 10695 10696 /* RX_X4_Status0 :: decode_status_1 :: cl49_bermon_history_state [09:05] */ 10697 #define RX_X4_STATUS0_DECODE_STATUS_1_CL49_BERMON_HISTORY_STATE_MASK 0x03e0 10698 #define RX_X4_STATUS0_DECODE_STATUS_1_CL49_BERMON_HISTORY_STATE_ALIGN 0 10699 #define RX_X4_STATUS0_DECODE_STATUS_1_CL49_BERMON_HISTORY_STATE_BITS 5 10700 #define RX_X4_STATUS0_DECODE_STATUS_1_CL49_BERMON_HISTORY_STATE_SHIFT 5 10701 10702 /* RX_X4_Status0 :: decode_status_1 :: cl49_bermon_current_state [04:00] */ 10703 #define RX_X4_STATUS0_DECODE_STATUS_1_CL49_BERMON_CURRENT_STATE_MASK 0x001f 10704 #define RX_X4_STATUS0_DECODE_STATUS_1_CL49_BERMON_CURRENT_STATE_ALIGN 0 10705 #define RX_X4_STATUS0_DECODE_STATUS_1_CL49_BERMON_CURRENT_STATE_BITS 5 10706 #define RX_X4_STATUS0_DECODE_STATUS_1_CL49_BERMON_CURRENT_STATE_SHIFT 0 10707 10708 10709 /**************************************************************************** 10710 * RX_X4_Status0 :: decode_status_2 10711 */ 10712 /* RX_X4_Status0 :: decode_status_2 :: sync66ErrCount [15:08] */ 10713 #define RX_X4_STATUS0_DECODE_STATUS_2_SYNC66ERRCOUNT_MASK 0xff00 10714 #define RX_X4_STATUS0_DECODE_STATUS_2_SYNC66ERRCOUNT_ALIGN 0 10715 #define RX_X4_STATUS0_DECODE_STATUS_2_SYNC66ERRCOUNT_BITS 8 10716 #define RX_X4_STATUS0_DECODE_STATUS_2_SYNC66ERRCOUNT_SHIFT 8 10717 10718 /* RX_X4_Status0 :: decode_status_2 :: kcode66ErrCount [07:00] */ 10719 #define RX_X4_STATUS0_DECODE_STATUS_2_KCODE66ERRCOUNT_MASK 0x00ff 10720 #define RX_X4_STATUS0_DECODE_STATUS_2_KCODE66ERRCOUNT_ALIGN 0 10721 #define RX_X4_STATUS0_DECODE_STATUS_2_KCODE66ERRCOUNT_BITS 8 10722 #define RX_X4_STATUS0_DECODE_STATUS_2_KCODE66ERRCOUNT_SHIFT 0 10723 10724 10725 /**************************************************************************** 10726 * RX_X4_Status0 :: decode_status_3 10727 */ 10728 /* RX_X4_Status0 :: decode_status_3 :: reserved0 [15:10] */ 10729 #define RX_X4_STATUS0_DECODE_STATUS_3_RESERVED0_MASK 0xfc00 10730 #define RX_X4_STATUS0_DECODE_STATUS_3_RESERVED0_ALIGN 0 10731 #define RX_X4_STATUS0_DECODE_STATUS_3_RESERVED0_BITS 6 10732 #define RX_X4_STATUS0_DECODE_STATUS_3_RESERVED0_SHIFT 10 10733 10734 /* RX_X4_Status0 :: decode_status_3 :: cl49ieee_errored_blocks [09:02] */ 10735 #define RX_X4_STATUS0_DECODE_STATUS_3_CL49IEEE_ERRORED_BLOCKS_MASK 0x03fc 10736 #define RX_X4_STATUS0_DECODE_STATUS_3_CL49IEEE_ERRORED_BLOCKS_ALIGN 0 10737 #define RX_X4_STATUS0_DECODE_STATUS_3_CL49IEEE_ERRORED_BLOCKS_BITS 8 10738 #define RX_X4_STATUS0_DECODE_STATUS_3_CL49IEEE_ERRORED_BLOCKS_SHIFT 2 10739 10740 /* RX_X4_Status0 :: decode_status_3 :: reserved1 [01:00] */ 10741 #define RX_X4_STATUS0_DECODE_STATUS_3_RESERVED1_MASK 0x0003 10742 #define RX_X4_STATUS0_DECODE_STATUS_3_RESERVED1_ALIGN 0 10743 #define RX_X4_STATUS0_DECODE_STATUS_3_RESERVED1_BITS 2 10744 #define RX_X4_STATUS0_DECODE_STATUS_3_RESERVED1_SHIFT 0 10745 10746 10747 /**************************************************************************** 10748 * RX_X4_Status0 :: decode_status_4 10749 */ 10750 /* RX_X4_Status0 :: decode_status_4 :: b66dec_fault_det [15:15] */ 10751 #define RX_X4_STATUS0_DECODE_STATUS_4_B66DEC_FAULT_DET_MASK 0x8000 10752 #define RX_X4_STATUS0_DECODE_STATUS_4_B66DEC_FAULT_DET_ALIGN 0 10753 #define RX_X4_STATUS0_DECODE_STATUS_4_B66DEC_FAULT_DET_BITS 1 10754 #define RX_X4_STATUS0_DECODE_STATUS_4_B66DEC_FAULT_DET_SHIFT 15 10755 10756 /* RX_X4_Status0 :: decode_status_4 :: cl48_syncacq_state_l [14:04] */ 10757 #define RX_X4_STATUS0_DECODE_STATUS_4_CL48_SYNCACQ_STATE_L_MASK 0x7ff0 10758 #define RX_X4_STATUS0_DECODE_STATUS_4_CL48_SYNCACQ_STATE_L_ALIGN 0 10759 #define RX_X4_STATUS0_DECODE_STATUS_4_CL48_SYNCACQ_STATE_L_BITS 11 10760 #define RX_X4_STATUS0_DECODE_STATUS_4_CL48_SYNCACQ_STATE_L_SHIFT 4 10761 10762 /* RX_X4_Status0 :: decode_status_4 :: reserved0 [03:00] */ 10763 #define RX_X4_STATUS0_DECODE_STATUS_4_RESERVED0_MASK 0x000f 10764 #define RX_X4_STATUS0_DECODE_STATUS_4_RESERVED0_ALIGN 0 10765 #define RX_X4_STATUS0_DECODE_STATUS_4_RESERVED0_BITS 4 10766 #define RX_X4_STATUS0_DECODE_STATUS_4_RESERVED0_SHIFT 0 10767 10768 10769 /**************************************************************************** 10770 * RX_X4_Status0 :: decode_status_5 10771 */ 10772 /* RX_X4_Status0 :: decode_status_5 :: cl48_syncacq_state_d_0 [15:12] */ 10773 #define RX_X4_STATUS0_DECODE_STATUS_5_CL48_SYNCACQ_STATE_D_0_MASK 0xf000 10774 #define RX_X4_STATUS0_DECODE_STATUS_5_CL48_SYNCACQ_STATE_D_0_ALIGN 0 10775 #define RX_X4_STATUS0_DECODE_STATUS_5_CL48_SYNCACQ_STATE_D_0_BITS 4 10776 #define RX_X4_STATUS0_DECODE_STATUS_5_CL48_SYNCACQ_STATE_D_0_SHIFT 12 10777 10778 /* RX_X4_Status0 :: decode_status_5 :: cl48_syncacq_state_d_1 [11:08] */ 10779 #define RX_X4_STATUS0_DECODE_STATUS_5_CL48_SYNCACQ_STATE_D_1_MASK 0x0f00 10780 #define RX_X4_STATUS0_DECODE_STATUS_5_CL48_SYNCACQ_STATE_D_1_ALIGN 0 10781 #define RX_X4_STATUS0_DECODE_STATUS_5_CL48_SYNCACQ_STATE_D_1_BITS 4 10782 #define RX_X4_STATUS0_DECODE_STATUS_5_CL48_SYNCACQ_STATE_D_1_SHIFT 8 10783 10784 /* RX_X4_Status0 :: decode_status_5 :: cl48_syncacq_state_d_2 [07:04] */ 10785 #define RX_X4_STATUS0_DECODE_STATUS_5_CL48_SYNCACQ_STATE_D_2_MASK 0x00f0 10786 #define RX_X4_STATUS0_DECODE_STATUS_5_CL48_SYNCACQ_STATE_D_2_ALIGN 0 10787 #define RX_X4_STATUS0_DECODE_STATUS_5_CL48_SYNCACQ_STATE_D_2_BITS 4 10788 #define RX_X4_STATUS0_DECODE_STATUS_5_CL48_SYNCACQ_STATE_D_2_SHIFT 4 10789 10790 /* RX_X4_Status0 :: decode_status_5 :: cl48_syncacq_state_d_3 [03:00] */ 10791 #define RX_X4_STATUS0_DECODE_STATUS_5_CL48_SYNCACQ_STATE_D_3_MASK 0x000f 10792 #define RX_X4_STATUS0_DECODE_STATUS_5_CL48_SYNCACQ_STATE_D_3_ALIGN 0 10793 #define RX_X4_STATUS0_DECODE_STATUS_5_CL48_SYNCACQ_STATE_D_3_BITS 4 10794 #define RX_X4_STATUS0_DECODE_STATUS_5_CL48_SYNCACQ_STATE_D_3_SHIFT 0 10795 10796 10797 /**************************************************************************** 10798 * RX_X4_Status0 :: syncacq_status_0 10799 */ 10800 /* RX_X4_Status0 :: syncacq_status_0 :: reserved0 [15:04] */ 10801 #define RX_X4_STATUS0_SYNCACQ_STATUS_0_RESERVED0_MASK 0xfff0 10802 #define RX_X4_STATUS0_SYNCACQ_STATUS_0_RESERVED0_ALIGN 0 10803 #define RX_X4_STATUS0_SYNCACQ_STATUS_0_RESERVED0_BITS 12 10804 #define RX_X4_STATUS0_SYNCACQ_STATUS_0_RESERVED0_SHIFT 4 10805 10806 /* RX_X4_Status0 :: syncacq_status_0 :: cl36_syncacq_state_coded_per_ln [03:00] */ 10807 #define RX_X4_STATUS0_SYNCACQ_STATUS_0_CL36_SYNCACQ_STATE_CODED_PER_LN_MASK 0x000f 10808 #define RX_X4_STATUS0_SYNCACQ_STATUS_0_CL36_SYNCACQ_STATE_CODED_PER_LN_ALIGN 0 10809 #define RX_X4_STATUS0_SYNCACQ_STATUS_0_CL36_SYNCACQ_STATE_CODED_PER_LN_BITS 4 10810 #define RX_X4_STATUS0_SYNCACQ_STATUS_0_CL36_SYNCACQ_STATE_CODED_PER_LN_SHIFT 0 10811 10812 10813 /**************************************************************************** 10814 * RX_X4_Status0 :: syncacq_status_1 10815 */ 10816 /* RX_X4_Status0 :: syncacq_status_1 :: reserved0 [15:13] */ 10817 #define RX_X4_STATUS0_SYNCACQ_STATUS_1_RESERVED0_MASK 0xe000 10818 #define RX_X4_STATUS0_SYNCACQ_STATUS_1_RESERVED0_ALIGN 0 10819 #define RX_X4_STATUS0_SYNCACQ_STATUS_1_RESERVED0_BITS 3 10820 #define RX_X4_STATUS0_SYNCACQ_STATUS_1_RESERVED0_SHIFT 13 10821 10822 /* RX_X4_Status0 :: syncacq_status_1 :: cl36_syncacq_his_state_per_ln [12:00] */ 10823 #define RX_X4_STATUS0_SYNCACQ_STATUS_1_CL36_SYNCACQ_HIS_STATE_PER_LN_MASK 0x1fff 10824 #define RX_X4_STATUS0_SYNCACQ_STATUS_1_CL36_SYNCACQ_HIS_STATE_PER_LN_ALIGN 0 10825 #define RX_X4_STATUS0_SYNCACQ_STATUS_1_CL36_SYNCACQ_HIS_STATE_PER_LN_BITS 13 10826 #define RX_X4_STATUS0_SYNCACQ_STATUS_1_CL36_SYNCACQ_HIS_STATE_PER_LN_SHIFT 0 10827 10828 10829 /**************************************************************************** 10830 * RX_X4_Status0 :: bercount 10831 */ 10832 /* RX_X4_Status0 :: bercount :: BIP_ERROR_COUNT_PER_LANE [15:08] */ 10833 #define RX_X4_STATUS0_BERCOUNT_BIP_ERROR_COUNT_PER_LANE_MASK 0xff00 10834 #define RX_X4_STATUS0_BERCOUNT_BIP_ERROR_COUNT_PER_LANE_ALIGN 0 10835 #define RX_X4_STATUS0_BERCOUNT_BIP_ERROR_COUNT_PER_LANE_BITS 8 10836 #define RX_X4_STATUS0_BERCOUNT_BIP_ERROR_COUNT_PER_LANE_SHIFT 8 10837 10838 /* RX_X4_Status0 :: bercount :: BER_count_per_ln [07:00] */ 10839 #define RX_X4_STATUS0_BERCOUNT_BER_COUNT_PER_LN_MASK 0x00ff 10840 #define RX_X4_STATUS0_BERCOUNT_BER_COUNT_PER_LN_ALIGN 0 10841 #define RX_X4_STATUS0_BERCOUNT_BER_COUNT_PER_LN_BITS 8 10842 #define RX_X4_STATUS0_BERCOUNT_BER_COUNT_PER_LN_SHIFT 0 10843 10844 10845 /**************************************************************************** 10846 * TSCE_TSCE_USER4_RX_X4_Status1 10847 */ 10848 /**************************************************************************** 10849 * RX_X4_Status1 :: pcs_latched_status_1 10850 */ 10851 /* RX_X4_Status1 :: pcs_latched_status_1 :: LOCAL_FAULT_LH [15:15] */ 10852 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LOCAL_FAULT_LH_MASK 0x8000 10853 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LOCAL_FAULT_LH_ALIGN 0 10854 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LOCAL_FAULT_LH_BITS 1 10855 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LOCAL_FAULT_LH_SHIFT 15 10856 10857 /* RX_X4_Status1 :: pcs_latched_status_1 :: REMOTE_FAULT_LH [14:14] */ 10858 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_REMOTE_FAULT_LH_MASK 0x4000 10859 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_REMOTE_FAULT_LH_ALIGN 0 10860 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_REMOTE_FAULT_LH_BITS 1 10861 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_REMOTE_FAULT_LH_SHIFT 14 10862 10863 /* RX_X4_Status1 :: pcs_latched_status_1 :: LINK_INTERRUPT_LH [13:13] */ 10864 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LINK_INTERRUPT_LH_MASK 0x2000 10865 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LINK_INTERRUPT_LH_ALIGN 0 10866 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LINK_INTERRUPT_LH_BITS 1 10867 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LINK_INTERRUPT_LH_SHIFT 13 10868 10869 /* RX_X4_Status1 :: pcs_latched_status_1 :: RESERVED_ORDERED_SET_LH [12:12] */ 10870 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_RESERVED_ORDERED_SET_LH_MASK 0x1000 10871 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_RESERVED_ORDERED_SET_LH_ALIGN 0 10872 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_RESERVED_ORDERED_SET_LH_BITS 1 10873 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_RESERVED_ORDERED_SET_LH_SHIFT 12 10874 10875 /* RX_X4_Status1 :: pcs_latched_status_1 :: RESERVED_ORDERED_BYTE_3 [11:04] */ 10876 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_RESERVED_ORDERED_BYTE_3_MASK 0x0ff0 10877 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_RESERVED_ORDERED_BYTE_3_ALIGN 0 10878 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_RESERVED_ORDERED_BYTE_3_BITS 8 10879 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_RESERVED_ORDERED_BYTE_3_SHIFT 4 10880 10881 /* RX_X4_Status1 :: pcs_latched_status_1 :: LPI_RECEIVED_LH [03:03] */ 10882 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LPI_RECEIVED_LH_MASK 0x0008 10883 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LPI_RECEIVED_LH_ALIGN 0 10884 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LPI_RECEIVED_LH_BITS 1 10885 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LPI_RECEIVED_LH_SHIFT 3 10886 10887 /* RX_X4_Status1 :: pcs_latched_status_1 :: reserved0 [02:00] */ 10888 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_RESERVED0_MASK 0x0007 10889 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_RESERVED0_ALIGN 0 10890 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_RESERVED0_BITS 3 10891 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_RESERVED0_SHIFT 0 10892 10893 10894 /**************************************************************************** 10895 * RX_X4_Status1 :: pcs_latched_status_0 10896 */ 10897 /* RX_X4_Status1 :: pcs_latched_status_0 :: AM_LOCK_LH [15:15] */ 10898 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_AM_LOCK_LH_MASK 0x8000 10899 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_AM_LOCK_LH_ALIGN 0 10900 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_AM_LOCK_LH_BITS 1 10901 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_AM_LOCK_LH_SHIFT 15 10902 10903 /* RX_X4_Status1 :: pcs_latched_status_0 :: AM_LOCK_LL [14:14] */ 10904 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_AM_LOCK_LL_MASK 0x4000 10905 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_AM_LOCK_LL_ALIGN 0 10906 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_AM_LOCK_LL_BITS 1 10907 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_AM_LOCK_LL_SHIFT 14 10908 10909 /* RX_X4_Status1 :: pcs_latched_status_0 :: DESKEW_STATUS_LH [13:13] */ 10910 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_DESKEW_STATUS_LH_MASK 0x2000 10911 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_DESKEW_STATUS_LH_ALIGN 0 10912 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_DESKEW_STATUS_LH_BITS 1 10913 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_DESKEW_STATUS_LH_SHIFT 13 10914 10915 /* RX_X4_Status1 :: pcs_latched_status_0 :: DESKEW_STATUS_LL [12:12] */ 10916 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_DESKEW_STATUS_LL_MASK 0x1000 10917 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_DESKEW_STATUS_LL_ALIGN 0 10918 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_DESKEW_STATUS_LL_BITS 1 10919 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_DESKEW_STATUS_LL_SHIFT 12 10920 10921 /* RX_X4_Status1 :: pcs_latched_status_0 :: HI_BER_LH [11:11] */ 10922 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_HI_BER_LH_MASK 0x0800 10923 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_HI_BER_LH_ALIGN 0 10924 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_HI_BER_LH_BITS 1 10925 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_HI_BER_LH_SHIFT 11 10926 10927 /* RX_X4_Status1 :: pcs_latched_status_0 :: HI_BER_LL [10:10] */ 10928 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_HI_BER_LL_MASK 0x0400 10929 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_HI_BER_LL_ALIGN 0 10930 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_HI_BER_LL_BITS 1 10931 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_HI_BER_LL_SHIFT 10 10932 10933 /* RX_X4_Status1 :: pcs_latched_status_0 :: LINK_STATUS_LH [09:09] */ 10934 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_LINK_STATUS_LH_MASK 0x0200 10935 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_LINK_STATUS_LH_ALIGN 0 10936 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_LINK_STATUS_LH_BITS 1 10937 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_LINK_STATUS_LH_SHIFT 9 10938 10939 /* RX_X4_Status1 :: pcs_latched_status_0 :: LINK_STATUS_LL [08:08] */ 10940 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_LINK_STATUS_LL_MASK 0x0100 10941 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_LINK_STATUS_LL_ALIGN 0 10942 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_LINK_STATUS_LL_BITS 1 10943 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_LINK_STATUS_LL_SHIFT 8 10944 10945 /* RX_X4_Status1 :: pcs_latched_status_0 :: SYNC_STATUS_LH [07:07] */ 10946 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_SYNC_STATUS_LH_MASK 0x0080 10947 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_SYNC_STATUS_LH_ALIGN 0 10948 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_SYNC_STATUS_LH_BITS 1 10949 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_SYNC_STATUS_LH_SHIFT 7 10950 10951 /* RX_X4_Status1 :: pcs_latched_status_0 :: SYNC_STATUS_LL [06:06] */ 10952 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_SYNC_STATUS_LL_MASK 0x0040 10953 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_SYNC_STATUS_LL_ALIGN 0 10954 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_SYNC_STATUS_LL_BITS 1 10955 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_SYNC_STATUS_LL_SHIFT 6 10956 10957 /* RX_X4_Status1 :: pcs_latched_status_0 :: reserved0 [05:00] */ 10958 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_RESERVED0_MASK 0x003f 10959 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_RESERVED0_ALIGN 0 10960 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_RESERVED0_BITS 6 10961 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_0_RESERVED0_SHIFT 0 10962 10963 10964 /**************************************************************************** 10965 * RX_X4_Status1 :: pcs_live_status 10966 */ 10967 /* RX_X4_Status1 :: pcs_live_status :: reserved0 [15:09] */ 10968 #define RX_X4_STATUS1_PCS_LIVE_STATUS_RESERVED0_MASK 0xfe00 10969 #define RX_X4_STATUS1_PCS_LIVE_STATUS_RESERVED0_ALIGN 0 10970 #define RX_X4_STATUS1_PCS_LIVE_STATUS_RESERVED0_BITS 7 10971 #define RX_X4_STATUS1_PCS_LIVE_STATUS_RESERVED0_SHIFT 9 10972 10973 /* RX_X4_Status1 :: pcs_live_status :: LOCAL_FAULT [08:08] */ 10974 #define RX_X4_STATUS1_PCS_LIVE_STATUS_LOCAL_FAULT_MASK 0x0100 10975 #define RX_X4_STATUS1_PCS_LIVE_STATUS_LOCAL_FAULT_ALIGN 0 10976 #define RX_X4_STATUS1_PCS_LIVE_STATUS_LOCAL_FAULT_BITS 1 10977 #define RX_X4_STATUS1_PCS_LIVE_STATUS_LOCAL_FAULT_SHIFT 8 10978 10979 /* RX_X4_Status1 :: pcs_live_status :: REMOTE_FAULT [07:07] */ 10980 #define RX_X4_STATUS1_PCS_LIVE_STATUS_REMOTE_FAULT_MASK 0x0080 10981 #define RX_X4_STATUS1_PCS_LIVE_STATUS_REMOTE_FAULT_ALIGN 0 10982 #define RX_X4_STATUS1_PCS_LIVE_STATUS_REMOTE_FAULT_BITS 1 10983 #define RX_X4_STATUS1_PCS_LIVE_STATUS_REMOTE_FAULT_SHIFT 7 10984 10985 /* RX_X4_Status1 :: pcs_live_status :: LINK_INTERRUPT [06:06] */ 10986 #define RX_X4_STATUS1_PCS_LIVE_STATUS_LINK_INTERRUPT_MASK 0x0040 10987 #define RX_X4_STATUS1_PCS_LIVE_STATUS_LINK_INTERRUPT_ALIGN 0 10988 #define RX_X4_STATUS1_PCS_LIVE_STATUS_LINK_INTERRUPT_BITS 1 10989 #define RX_X4_STATUS1_PCS_LIVE_STATUS_LINK_INTERRUPT_SHIFT 6 10990 10991 /* RX_X4_Status1 :: pcs_live_status :: LPI_RECEIVED [05:05] */ 10992 #define RX_X4_STATUS1_PCS_LIVE_STATUS_LPI_RECEIVED_MASK 0x0020 10993 #define RX_X4_STATUS1_PCS_LIVE_STATUS_LPI_RECEIVED_ALIGN 0 10994 #define RX_X4_STATUS1_PCS_LIVE_STATUS_LPI_RECEIVED_BITS 1 10995 #define RX_X4_STATUS1_PCS_LIVE_STATUS_LPI_RECEIVED_SHIFT 5 10996 10997 /* RX_X4_Status1 :: pcs_live_status :: AM_LOCK [04:04] */ 10998 #define RX_X4_STATUS1_PCS_LIVE_STATUS_AM_LOCK_MASK 0x0010 10999 #define RX_X4_STATUS1_PCS_LIVE_STATUS_AM_LOCK_ALIGN 0 11000 #define RX_X4_STATUS1_PCS_LIVE_STATUS_AM_LOCK_BITS 1 11001 #define RX_X4_STATUS1_PCS_LIVE_STATUS_AM_LOCK_SHIFT 4 11002 11003 /* RX_X4_Status1 :: pcs_live_status :: DESKEW_STATUS [03:03] */ 11004 #define RX_X4_STATUS1_PCS_LIVE_STATUS_DESKEW_STATUS_MASK 0x0008 11005 #define RX_X4_STATUS1_PCS_LIVE_STATUS_DESKEW_STATUS_ALIGN 0 11006 #define RX_X4_STATUS1_PCS_LIVE_STATUS_DESKEW_STATUS_BITS 1 11007 #define RX_X4_STATUS1_PCS_LIVE_STATUS_DESKEW_STATUS_SHIFT 3 11008 11009 /* RX_X4_Status1 :: pcs_live_status :: HI_BER [02:02] */ 11010 #define RX_X4_STATUS1_PCS_LIVE_STATUS_HI_BER_MASK 0x0004 11011 #define RX_X4_STATUS1_PCS_LIVE_STATUS_HI_BER_ALIGN 0 11012 #define RX_X4_STATUS1_PCS_LIVE_STATUS_HI_BER_BITS 1 11013 #define RX_X4_STATUS1_PCS_LIVE_STATUS_HI_BER_SHIFT 2 11014 11015 /* RX_X4_Status1 :: pcs_live_status :: LINK_STATUS [01:01] */ 11016 #define RX_X4_STATUS1_PCS_LIVE_STATUS_LINK_STATUS_MASK 0x0002 11017 #define RX_X4_STATUS1_PCS_LIVE_STATUS_LINK_STATUS_ALIGN 0 11018 #define RX_X4_STATUS1_PCS_LIVE_STATUS_LINK_STATUS_BITS 1 11019 #define RX_X4_STATUS1_PCS_LIVE_STATUS_LINK_STATUS_SHIFT 1 11020 11021 /* RX_X4_Status1 :: pcs_live_status :: SYNC_STATUS [00:00] */ 11022 #define RX_X4_STATUS1_PCS_LIVE_STATUS_SYNC_STATUS_MASK 0x0001 11023 #define RX_X4_STATUS1_PCS_LIVE_STATUS_SYNC_STATUS_ALIGN 0 11024 #define RX_X4_STATUS1_PCS_LIVE_STATUS_SYNC_STATUS_BITS 1 11025 #define RX_X4_STATUS1_PCS_LIVE_STATUS_SYNC_STATUS_SHIFT 0 11026 11027 11028 /**************************************************************************** 11029 * RX_X4_Status1 :: cl82_rx_am_latched_status 11030 */ 11031 /* RX_X4_Status1 :: cl82_rx_am_latched_status :: reserved0 [15:11] */ 11032 #define RX_X4_STATUS1_CL82_RX_AM_LATCHED_STATUS_RESERVED0_MASK 0xf800 11033 #define RX_X4_STATUS1_CL82_RX_AM_LATCHED_STATUS_RESERVED0_ALIGN 0 11034 #define RX_X4_STATUS1_CL82_RX_AM_LATCHED_STATUS_RESERVED0_BITS 5 11035 #define RX_X4_STATUS1_CL82_RX_AM_LATCHED_STATUS_RESERVED0_SHIFT 11 11036 11037 /* RX_X4_Status1 :: cl82_rx_am_latched_status :: amrkr_spacing_err_latch_mux [10:10] */ 11038 #define RX_X4_STATUS1_CL82_RX_AM_LATCHED_STATUS_AMRKR_SPACING_ERR_LATCH_MUX_MASK 0x0400 11039 #define RX_X4_STATUS1_CL82_RX_AM_LATCHED_STATUS_AMRKR_SPACING_ERR_LATCH_MUX_ALIGN 0 11040 #define RX_X4_STATUS1_CL82_RX_AM_LATCHED_STATUS_AMRKR_SPACING_ERR_LATCH_MUX_BITS 1 11041 #define RX_X4_STATUS1_CL82_RX_AM_LATCHED_STATUS_AMRKR_SPACING_ERR_LATCH_MUX_SHIFT 10 11042 11043 /* RX_X4_Status1 :: cl82_rx_am_latched_status :: am_lock_his_state [09:00] */ 11044 #define RX_X4_STATUS1_CL82_RX_AM_LATCHED_STATUS_AM_LOCK_HIS_STATE_MASK 0x03ff 11045 #define RX_X4_STATUS1_CL82_RX_AM_LATCHED_STATUS_AM_LOCK_HIS_STATE_ALIGN 0 11046 #define RX_X4_STATUS1_CL82_RX_AM_LATCHED_STATUS_AM_LOCK_HIS_STATE_BITS 10 11047 #define RX_X4_STATUS1_CL82_RX_AM_LATCHED_STATUS_AM_LOCK_HIS_STATE_SHIFT 0 11048 11049 11050 /**************************************************************************** 11051 * RX_X4_Status1 :: cl82_rx_am_live_status 11052 */ 11053 /* RX_X4_Status1 :: cl82_rx_am_live_status :: reserved0 [15:10] */ 11054 #define RX_X4_STATUS1_CL82_RX_AM_LIVE_STATUS_RESERVED0_MASK 0xfc00 11055 #define RX_X4_STATUS1_CL82_RX_AM_LIVE_STATUS_RESERVED0_ALIGN 0 11056 #define RX_X4_STATUS1_CL82_RX_AM_LIVE_STATUS_RESERVED0_BITS 6 11057 #define RX_X4_STATUS1_CL82_RX_AM_LIVE_STATUS_RESERVED0_SHIFT 10 11058 11059 /* RX_X4_Status1 :: cl82_rx_am_live_status :: am_lock_state [09:00] */ 11060 #define RX_X4_STATUS1_CL82_RX_AM_LIVE_STATUS_AM_LOCK_STATE_MASK 0x03ff 11061 #define RX_X4_STATUS1_CL82_RX_AM_LIVE_STATUS_AM_LOCK_STATE_ALIGN 0 11062 #define RX_X4_STATUS1_CL82_RX_AM_LIVE_STATUS_AM_LOCK_STATE_BITS 10 11063 #define RX_X4_STATUS1_CL82_RX_AM_LIVE_STATUS_AM_LOCK_STATE_SHIFT 0 11064 11065 11066 /**************************************************************************** 11067 * RX_X4_Status1 :: fec_CorrectedBlksL 11068 */ 11069 /* RX_X4_Status1 :: fec_CorrectedBlksL :: corCountL [15:00] */ 11070 #define RX_X4_STATUS1_FEC_CORRECTEDBLKSL_CORCOUNTL_MASK 0xffff 11071 #define RX_X4_STATUS1_FEC_CORRECTEDBLKSL_CORCOUNTL_ALIGN 0 11072 #define RX_X4_STATUS1_FEC_CORRECTEDBLKSL_CORCOUNTL_BITS 16 11073 #define RX_X4_STATUS1_FEC_CORRECTEDBLKSL_CORCOUNTL_SHIFT 0 11074 11075 11076 /**************************************************************************** 11077 * RX_X4_Status1 :: fec_CorrectedBlksH 11078 */ 11079 /* RX_X4_Status1 :: fec_CorrectedBlksH :: corCountH [15:00] */ 11080 #define RX_X4_STATUS1_FEC_CORRECTEDBLKSH_CORCOUNTH_MASK 0xffff 11081 #define RX_X4_STATUS1_FEC_CORRECTEDBLKSH_CORCOUNTH_ALIGN 0 11082 #define RX_X4_STATUS1_FEC_CORRECTEDBLKSH_CORCOUNTH_BITS 16 11083 #define RX_X4_STATUS1_FEC_CORRECTEDBLKSH_CORCOUNTH_SHIFT 0 11084 11085 11086 /**************************************************************************** 11087 * RX_X4_Status1 :: fec_UncorrectedBlksL 11088 */ 11089 /* RX_X4_Status1 :: fec_UncorrectedBlksL :: uncorCountL [15:00] */ 11090 #define RX_X4_STATUS1_FEC_UNCORRECTEDBLKSL_UNCORCOUNTL_MASK 0xffff 11091 #define RX_X4_STATUS1_FEC_UNCORRECTEDBLKSL_UNCORCOUNTL_ALIGN 0 11092 #define RX_X4_STATUS1_FEC_UNCORRECTEDBLKSL_UNCORCOUNTL_BITS 16 11093 #define RX_X4_STATUS1_FEC_UNCORRECTEDBLKSL_UNCORCOUNTL_SHIFT 0 11094 11095 11096 /**************************************************************************** 11097 * RX_X4_Status1 :: fec_UncorrectedBlksH 11098 */ 11099 /* RX_X4_Status1 :: fec_UncorrectedBlksH :: uncorCountH [15:00] */ 11100 #define RX_X4_STATUS1_FEC_UNCORRECTEDBLKSH_UNCORCOUNTH_MASK 0xffff 11101 #define RX_X4_STATUS1_FEC_UNCORRECTEDBLKSH_UNCORCOUNTH_ALIGN 0 11102 #define RX_X4_STATUS1_FEC_UNCORRECTEDBLKSH_UNCORCOUNTH_BITS 16 11103 #define RX_X4_STATUS1_FEC_UNCORRECTEDBLKSH_UNCORCOUNTH_SHIFT 0 11104 11105 11106 /**************************************************************************** 11107 * RX_X4_Status1 :: gbox_status 11108 */ 11109 /* RX_X4_Status1 :: gbox_status :: reserved0 [15:02] */ 11110 #define RX_X4_STATUS1_GBOX_STATUS_RESERVED0_MASK 0xfffc 11111 #define RX_X4_STATUS1_GBOX_STATUS_RESERVED0_ALIGN 0 11112 #define RX_X4_STATUS1_GBOX_STATUS_RESERVED0_BITS 14 11113 #define RX_X4_STATUS1_GBOX_STATUS_RESERVED0_SHIFT 2 11114 11115 /* RX_X4_Status1 :: gbox_status :: gbox_overflow_err [01:01] */ 11116 #define RX_X4_STATUS1_GBOX_STATUS_GBOX_OVERFLOW_ERR_MASK 0x0002 11117 #define RX_X4_STATUS1_GBOX_STATUS_GBOX_OVERFLOW_ERR_ALIGN 0 11118 #define RX_X4_STATUS1_GBOX_STATUS_GBOX_OVERFLOW_ERR_BITS 1 11119 #define RX_X4_STATUS1_GBOX_STATUS_GBOX_OVERFLOW_ERR_SHIFT 1 11120 11121 /* RX_X4_Status1 :: gbox_status :: gbox_underflow_err [00:00] */ 11122 #define RX_X4_STATUS1_GBOX_STATUS_GBOX_UNDERFLOW_ERR_MASK 0x0001 11123 #define RX_X4_STATUS1_GBOX_STATUS_GBOX_UNDERFLOW_ERR_ALIGN 0 11124 #define RX_X4_STATUS1_GBOX_STATUS_GBOX_UNDERFLOW_ERR_BITS 1 11125 #define RX_X4_STATUS1_GBOX_STATUS_GBOX_UNDERFLOW_ERR_SHIFT 0 11126 11127 11128 /**************************************************************************** 11129 * TSCE_TSCE_USER4_RX_X4_Control0_tsc_12 11130 */ 11131 /**************************************************************************** 11132 * RX_X4_Control0_tsc_12 :: fec_0 11133 */ 11134 /* RX_X4_Control0_tsc_12 :: fec_0 :: reserved0 [15:14] */ 11135 #define RX_X4_CONTROL0_TSC_12_FEC_0_RESERVED0_MASK 0xc000 11136 #define RX_X4_CONTROL0_TSC_12_FEC_0_RESERVED0_ALIGN 0 11137 #define RX_X4_CONTROL0_TSC_12_FEC_0_RESERVED0_BITS 2 11138 #define RX_X4_CONTROL0_TSC_12_FEC_0_RESERVED0_SHIFT 14 11139 11140 /* RX_X4_Control0_tsc_12 :: fec_0 :: fec_err_enable [13:13] */ 11141 #define RX_X4_CONTROL0_TSC_12_FEC_0_FEC_ERR_ENABLE_MASK 0x2000 11142 #define RX_X4_CONTROL0_TSC_12_FEC_0_FEC_ERR_ENABLE_ALIGN 0 11143 #define RX_X4_CONTROL0_TSC_12_FEC_0_FEC_ERR_ENABLE_BITS 1 11144 #define RX_X4_CONTROL0_TSC_12_FEC_0_FEC_ERR_ENABLE_SHIFT 13 11145 11146 /* RX_X4_Control0_tsc_12 :: fec_0 :: error_en_ovr [12:12] */ 11147 #define RX_X4_CONTROL0_TSC_12_FEC_0_ERROR_EN_OVR_MASK 0x1000 11148 #define RX_X4_CONTROL0_TSC_12_FEC_0_ERROR_EN_OVR_ALIGN 0 11149 #define RX_X4_CONTROL0_TSC_12_FEC_0_ERROR_EN_OVR_BITS 1 11150 #define RX_X4_CONTROL0_TSC_12_FEC_0_ERROR_EN_OVR_SHIFT 12 11151 11152 /* RX_X4_Control0_tsc_12 :: fec_0 :: error_en_ovr_val [11:11] */ 11153 #define RX_X4_CONTROL0_TSC_12_FEC_0_ERROR_EN_OVR_VAL_MASK 0x0800 11154 #define RX_X4_CONTROL0_TSC_12_FEC_0_ERROR_EN_OVR_VAL_ALIGN 0 11155 #define RX_X4_CONTROL0_TSC_12_FEC_0_ERROR_EN_OVR_VAL_BITS 1 11156 #define RX_X4_CONTROL0_TSC_12_FEC_0_ERROR_EN_OVR_VAL_SHIFT 11 11157 11158 /* RX_X4_Control0_tsc_12 :: fec_0 :: dbg_enable [10:10] */ 11159 #define RX_X4_CONTROL0_TSC_12_FEC_0_DBG_ENABLE_MASK 0x0400 11160 #define RX_X4_CONTROL0_TSC_12_FEC_0_DBG_ENABLE_ALIGN 0 11161 #define RX_X4_CONTROL0_TSC_12_FEC_0_DBG_ENABLE_BITS 1 11162 #define RX_X4_CONTROL0_TSC_12_FEC_0_DBG_ENABLE_SHIFT 10 11163 11164 /* RX_X4_Control0_tsc_12 :: fec_0 :: fast_lock_en [09:09] */ 11165 #define RX_X4_CONTROL0_TSC_12_FEC_0_FAST_LOCK_EN_MASK 0x0200 11166 #define RX_X4_CONTROL0_TSC_12_FEC_0_FAST_LOCK_EN_ALIGN 0 11167 #define RX_X4_CONTROL0_TSC_12_FEC_0_FAST_LOCK_EN_BITS 1 11168 #define RX_X4_CONTROL0_TSC_12_FEC_0_FAST_LOCK_EN_SHIFT 9 11169 11170 /* RX_X4_Control0_tsc_12 :: fec_0 :: reserved1 [08:00] */ 11171 #define RX_X4_CONTROL0_TSC_12_FEC_0_RESERVED1_MASK 0x01ff 11172 #define RX_X4_CONTROL0_TSC_12_FEC_0_RESERVED1_ALIGN 0 11173 #define RX_X4_CONTROL0_TSC_12_FEC_0_RESERVED1_BITS 9 11174 #define RX_X4_CONTROL0_TSC_12_FEC_0_RESERVED1_SHIFT 0 11175 11176 11177 /**************************************************************************** 11178 * RX_X4_Control0_tsc_12 :: fec_1 11179 */ 11180 /* RX_X4_Control0_tsc_12 :: fec_1 :: fec_error_code_all [15:15] */ 11181 #define RX_X4_CONTROL0_TSC_12_FEC_1_FEC_ERROR_CODE_ALL_MASK 0x8000 11182 #define RX_X4_CONTROL0_TSC_12_FEC_1_FEC_ERROR_CODE_ALL_ALIGN 0 11183 #define RX_X4_CONTROL0_TSC_12_FEC_1_FEC_ERROR_CODE_ALL_BITS 1 11184 #define RX_X4_CONTROL0_TSC_12_FEC_1_FEC_ERROR_CODE_ALL_SHIFT 15 11185 11186 /* RX_X4_Control0_tsc_12 :: fec_1 :: good_parity_cnt [14:12] */ 11187 #define RX_X4_CONTROL0_TSC_12_FEC_1_GOOD_PARITY_CNT_MASK 0x7000 11188 #define RX_X4_CONTROL0_TSC_12_FEC_1_GOOD_PARITY_CNT_ALIGN 0 11189 #define RX_X4_CONTROL0_TSC_12_FEC_1_GOOD_PARITY_CNT_BITS 3 11190 #define RX_X4_CONTROL0_TSC_12_FEC_1_GOOD_PARITY_CNT_SHIFT 12 11191 11192 /* RX_X4_Control0_tsc_12 :: fec_1 :: invalid_parity_cnt [11:08] */ 11193 #define RX_X4_CONTROL0_TSC_12_FEC_1_INVALID_PARITY_CNT_MASK 0x0f00 11194 #define RX_X4_CONTROL0_TSC_12_FEC_1_INVALID_PARITY_CNT_ALIGN 0 11195 #define RX_X4_CONTROL0_TSC_12_FEC_1_INVALID_PARITY_CNT_BITS 4 11196 #define RX_X4_CONTROL0_TSC_12_FEC_1_INVALID_PARITY_CNT_SHIFT 8 11197 11198 /* RX_X4_Control0_tsc_12 :: fec_1 :: dec_max_pm [07:02] */ 11199 #define RX_X4_CONTROL0_TSC_12_FEC_1_DEC_MAX_PM_MASK 0x00fc 11200 #define RX_X4_CONTROL0_TSC_12_FEC_1_DEC_MAX_PM_ALIGN 0 11201 #define RX_X4_CONTROL0_TSC_12_FEC_1_DEC_MAX_PM_BITS 6 11202 #define RX_X4_CONTROL0_TSC_12_FEC_1_DEC_MAX_PM_SHIFT 2 11203 11204 /* RX_X4_Control0_tsc_12 :: fec_1 :: burst_err_status_mode [01:01] */ 11205 #define RX_X4_CONTROL0_TSC_12_FEC_1_BURST_ERR_STATUS_MODE_MASK 0x0002 11206 #define RX_X4_CONTROL0_TSC_12_FEC_1_BURST_ERR_STATUS_MODE_ALIGN 0 11207 #define RX_X4_CONTROL0_TSC_12_FEC_1_BURST_ERR_STATUS_MODE_BITS 1 11208 #define RX_X4_CONTROL0_TSC_12_FEC_1_BURST_ERR_STATUS_MODE_SHIFT 1 11209 11210 /* RX_X4_Control0_tsc_12 :: fec_1 :: dbg_err_mode [00:00] */ 11211 #define RX_X4_CONTROL0_TSC_12_FEC_1_DBG_ERR_MODE_MASK 0x0001 11212 #define RX_X4_CONTROL0_TSC_12_FEC_1_DBG_ERR_MODE_ALIGN 0 11213 #define RX_X4_CONTROL0_TSC_12_FEC_1_DBG_ERR_MODE_BITS 1 11214 #define RX_X4_CONTROL0_TSC_12_FEC_1_DBG_ERR_MODE_SHIFT 0 11215 11216 11217 /**************************************************************************** 11218 * RX_X4_Control0_tsc_12 :: fec_2 11219 */ 11220 /* RX_X4_Control0_tsc_12 :: fec_2 :: dec_pm_mode [15:11] */ 11221 #define RX_X4_CONTROL0_TSC_12_FEC_2_DEC_PM_MODE_MASK 0xf800 11222 #define RX_X4_CONTROL0_TSC_12_FEC_2_DEC_PM_MODE_ALIGN 0 11223 #define RX_X4_CONTROL0_TSC_12_FEC_2_DEC_PM_MODE_BITS 5 11224 #define RX_X4_CONTROL0_TSC_12_FEC_2_DEC_PM_MODE_SHIFT 11 11225 11226 /* RX_X4_Control0_tsc_12 :: fec_2 :: dec_19b_burst_gap_count [10:08] */ 11227 #define RX_X4_CONTROL0_TSC_12_FEC_2_DEC_19B_BURST_GAP_COUNT_MASK 0x0700 11228 #define RX_X4_CONTROL0_TSC_12_FEC_2_DEC_19B_BURST_GAP_COUNT_ALIGN 0 11229 #define RX_X4_CONTROL0_TSC_12_FEC_2_DEC_19B_BURST_GAP_COUNT_BITS 3 11230 #define RX_X4_CONTROL0_TSC_12_FEC_2_DEC_19B_BURST_GAP_COUNT_SHIFT 8 11231 11232 /* RX_X4_Control0_tsc_12 :: fec_2 :: dec_18b_burst_gap_count [07:05] */ 11233 #define RX_X4_CONTROL0_TSC_12_FEC_2_DEC_18B_BURST_GAP_COUNT_MASK 0x00e0 11234 #define RX_X4_CONTROL0_TSC_12_FEC_2_DEC_18B_BURST_GAP_COUNT_ALIGN 0 11235 #define RX_X4_CONTROL0_TSC_12_FEC_2_DEC_18B_BURST_GAP_COUNT_BITS 3 11236 #define RX_X4_CONTROL0_TSC_12_FEC_2_DEC_18B_BURST_GAP_COUNT_SHIFT 5 11237 11238 /* RX_X4_Control0_tsc_12 :: fec_2 :: dec_17b_burst_gap_count [04:02] */ 11239 #define RX_X4_CONTROL0_TSC_12_FEC_2_DEC_17B_BURST_GAP_COUNT_MASK 0x001c 11240 #define RX_X4_CONTROL0_TSC_12_FEC_2_DEC_17B_BURST_GAP_COUNT_ALIGN 0 11241 #define RX_X4_CONTROL0_TSC_12_FEC_2_DEC_17B_BURST_GAP_COUNT_BITS 3 11242 #define RX_X4_CONTROL0_TSC_12_FEC_2_DEC_17B_BURST_GAP_COUNT_SHIFT 2 11243 11244 /* RX_X4_Control0_tsc_12 :: fec_2 :: dec_gap_count_mode [01:01] */ 11245 #define RX_X4_CONTROL0_TSC_12_FEC_2_DEC_GAP_COUNT_MODE_MASK 0x0002 11246 #define RX_X4_CONTROL0_TSC_12_FEC_2_DEC_GAP_COUNT_MODE_ALIGN 0 11247 #define RX_X4_CONTROL0_TSC_12_FEC_2_DEC_GAP_COUNT_MODE_BITS 1 11248 #define RX_X4_CONTROL0_TSC_12_FEC_2_DEC_GAP_COUNT_MODE_SHIFT 1 11249 11250 /* RX_X4_Control0_tsc_12 :: fec_2 :: reserved0 [00:00] */ 11251 #define RX_X4_CONTROL0_TSC_12_FEC_2_RESERVED0_MASK 0x0001 11252 #define RX_X4_CONTROL0_TSC_12_FEC_2_RESERVED0_ALIGN 0 11253 #define RX_X4_CONTROL0_TSC_12_FEC_2_RESERVED0_BITS 1 11254 #define RX_X4_CONTROL0_TSC_12_FEC_2_RESERVED0_SHIFT 0 11255 11256 11257 /**************************************************************************** 11258 * TSCE_TSCE_USER4_RX_X4_Status0_tsc_12 11259 */ 11260 /**************************************************************************** 11261 * RX_X4_Status0_tsc_12 :: fec_dbg_errL 11262 */ 11263 /* RX_X4_Status0_tsc_12 :: fec_dbg_errL :: dbg_errL [15:00] */ 11264 #define RX_X4_STATUS0_TSC_12_FEC_DBG_ERRL_DBG_ERRL_MASK 0xffff 11265 #define RX_X4_STATUS0_TSC_12_FEC_DBG_ERRL_DBG_ERRL_ALIGN 0 11266 #define RX_X4_STATUS0_TSC_12_FEC_DBG_ERRL_DBG_ERRL_BITS 16 11267 #define RX_X4_STATUS0_TSC_12_FEC_DBG_ERRL_DBG_ERRL_SHIFT 0 11268 11269 11270 /**************************************************************************** 11271 * RX_X4_Status0_tsc_12 :: fec_dbg_erraH 11272 */ 11273 /* RX_X4_Status0_tsc_12 :: fec_dbg_erraH :: dbg_errH [15:00] */ 11274 #define RX_X4_STATUS0_TSC_12_FEC_DBG_ERRAH_DBG_ERRH_MASK 0xffff 11275 #define RX_X4_STATUS0_TSC_12_FEC_DBG_ERRAH_DBG_ERRH_ALIGN 0 11276 #define RX_X4_STATUS0_TSC_12_FEC_DBG_ERRAH_DBG_ERRH_BITS 16 11277 #define RX_X4_STATUS0_TSC_12_FEC_DBG_ERRAH_DBG_ERRH_SHIFT 0 11278 11279 11280 /**************************************************************************** 11281 * RX_X4_Status0_tsc_12 :: fec_burst_err_statusL 11282 */ 11283 /* RX_X4_Status0_tsc_12 :: fec_burst_err_statusL :: burst_err_statusL [15:00] */ 11284 #define RX_X4_STATUS0_TSC_12_FEC_BURST_ERR_STATUSL_BURST_ERR_STATUSL_MASK 0xffff 11285 #define RX_X4_STATUS0_TSC_12_FEC_BURST_ERR_STATUSL_BURST_ERR_STATUSL_ALIGN 0 11286 #define RX_X4_STATUS0_TSC_12_FEC_BURST_ERR_STATUSL_BURST_ERR_STATUSL_BITS 16 11287 #define RX_X4_STATUS0_TSC_12_FEC_BURST_ERR_STATUSL_BURST_ERR_STATUSL_SHIFT 0 11288 11289 11290 /**************************************************************************** 11291 * RX_X4_Status0_tsc_12 :: fec_burst_err_statusH 11292 */ 11293 /* RX_X4_Status0_tsc_12 :: fec_burst_err_statusH :: burst_err_statusH [15:00] */ 11294 #define RX_X4_STATUS0_TSC_12_FEC_BURST_ERR_STATUSH_BURST_ERR_STATUSH_MASK 0xffff 11295 #define RX_X4_STATUS0_TSC_12_FEC_BURST_ERR_STATUSH_BURST_ERR_STATUSH_ALIGN 0 11296 #define RX_X4_STATUS0_TSC_12_FEC_BURST_ERR_STATUSH_BURST_ERR_STATUSH_BITS 16 11297 #define RX_X4_STATUS0_TSC_12_FEC_BURST_ERR_STATUSH_BURST_ERR_STATUSH_SHIFT 0 11298 11299 11300 /**************************************************************************** 11301 * RX_X4_Status0_tsc_12 :: bercount 11302 */ 11303 /* RX_X4_Status0_tsc_12 :: bercount :: reserved0 [15:08] */ 11304 #define RX_X4_STATUS0_TSC_12_BERCOUNT_RESERVED0_MASK 0xff00 11305 #define RX_X4_STATUS0_TSC_12_BERCOUNT_RESERVED0_ALIGN 0 11306 #define RX_X4_STATUS0_TSC_12_BERCOUNT_RESERVED0_BITS 8 11307 #define RX_X4_STATUS0_TSC_12_BERCOUNT_RESERVED0_SHIFT 8 11308 11309 /* RX_X4_Status0_tsc_12 :: bercount :: BIP_ERROR_COUNT_PER_LANE [07:00] */ 11310 #define RX_X4_STATUS0_TSC_12_BERCOUNT_BIP_ERROR_COUNT_PER_LANE_MASK 0x00ff 11311 #define RX_X4_STATUS0_TSC_12_BERCOUNT_BIP_ERROR_COUNT_PER_LANE_ALIGN 0 11312 #define RX_X4_STATUS0_TSC_12_BERCOUNT_BIP_ERROR_COUNT_PER_LANE_BITS 8 11313 #define RX_X4_STATUS0_TSC_12_BERCOUNT_BIP_ERROR_COUNT_PER_LANE_SHIFT 0 11314 11315 11316 /**************************************************************************** 11317 * RX_X4_Status0_tsc_12 :: cl49_lock_fsm_status 11318 */ 11319 /* RX_X4_Status0_tsc_12 :: cl49_lock_fsm_status :: rmld_status [15:08] */ 11320 #define RX_X4_STATUS0_TSC_12_CL49_LOCK_FSM_STATUS_RMLD_STATUS_MASK 0xff00 11321 #define RX_X4_STATUS0_TSC_12_CL49_LOCK_FSM_STATUS_RMLD_STATUS_ALIGN 0 11322 #define RX_X4_STATUS0_TSC_12_CL49_LOCK_FSM_STATUS_RMLD_STATUS_BITS 8 11323 #define RX_X4_STATUS0_TSC_12_CL49_LOCK_FSM_STATUS_RMLD_STATUS_SHIFT 8 11324 11325 /* RX_X4_Status0_tsc_12 :: cl49_lock_fsm_status :: align_status_cl82 [07:07] */ 11326 #define RX_X4_STATUS0_TSC_12_CL49_LOCK_FSM_STATUS_ALIGN_STATUS_CL82_MASK 0x0080 11327 #define RX_X4_STATUS0_TSC_12_CL49_LOCK_FSM_STATUS_ALIGN_STATUS_CL82_ALIGN 0 11328 #define RX_X4_STATUS0_TSC_12_CL49_LOCK_FSM_STATUS_ALIGN_STATUS_CL82_BITS 1 11329 #define RX_X4_STATUS0_TSC_12_CL49_LOCK_FSM_STATUS_ALIGN_STATUS_CL82_SHIFT 7 11330 11331 /* RX_X4_Status0_tsc_12 :: cl49_lock_fsm_status :: reserved0 [06:05] */ 11332 #define RX_X4_STATUS0_TSC_12_CL49_LOCK_FSM_STATUS_RESERVED0_MASK 0x0060 11333 #define RX_X4_STATUS0_TSC_12_CL49_LOCK_FSM_STATUS_RESERVED0_ALIGN 0 11334 #define RX_X4_STATUS0_TSC_12_CL49_LOCK_FSM_STATUS_RESERVED0_BITS 2 11335 #define RX_X4_STATUS0_TSC_12_CL49_LOCK_FSM_STATUS_RESERVED0_SHIFT 5 11336 11337 /* RX_X4_Status0_tsc_12 :: cl49_lock_fsm_status :: lsm_his_state [04:02] */ 11338 #define RX_X4_STATUS0_TSC_12_CL49_LOCK_FSM_STATUS_LSM_HIS_STATE_MASK 0x001c 11339 #define RX_X4_STATUS0_TSC_12_CL49_LOCK_FSM_STATUS_LSM_HIS_STATE_ALIGN 0 11340 #define RX_X4_STATUS0_TSC_12_CL49_LOCK_FSM_STATUS_LSM_HIS_STATE_BITS 3 11341 #define RX_X4_STATUS0_TSC_12_CL49_LOCK_FSM_STATUS_LSM_HIS_STATE_SHIFT 2 11342 11343 /* RX_X4_Status0_tsc_12 :: cl49_lock_fsm_status :: lsm_curr_state [01:00] */ 11344 #define RX_X4_STATUS0_TSC_12_CL49_LOCK_FSM_STATUS_LSM_CURR_STATE_MASK 0x0003 11345 #define RX_X4_STATUS0_TSC_12_CL49_LOCK_FSM_STATUS_LSM_CURR_STATE_ALIGN 0 11346 #define RX_X4_STATUS0_TSC_12_CL49_LOCK_FSM_STATUS_LSM_CURR_STATE_BITS 2 11347 #define RX_X4_STATUS0_TSC_12_CL49_LOCK_FSM_STATUS_LSM_CURR_STATE_SHIFT 0 11348 11349 11350 /**************************************************************************** 11351 * RX_X4_Status0_tsc_12 :: mld_vl_info_0 11352 */ 11353 /* RX_X4_Status0_tsc_12 :: mld_vl_info_0 :: reserved0 [15:10] */ 11354 #define RX_X4_STATUS0_TSC_12_MLD_VL_INFO_0_RESERVED0_MASK 0xfc00 11355 #define RX_X4_STATUS0_TSC_12_MLD_VL_INFO_0_RESERVED0_ALIGN 0 11356 #define RX_X4_STATUS0_TSC_12_MLD_VL_INFO_0_RESERVED0_BITS 6 11357 #define RX_X4_STATUS0_TSC_12_MLD_VL_INFO_0_RESERVED0_SHIFT 10 11358 11359 /* RX_X4_Status0_tsc_12 :: mld_vl_info_0 :: VL_ON_LL_1 [09:05] */ 11360 #define RX_X4_STATUS0_TSC_12_MLD_VL_INFO_0_VL_ON_LL_1_MASK 0x03e0 11361 #define RX_X4_STATUS0_TSC_12_MLD_VL_INFO_0_VL_ON_LL_1_ALIGN 0 11362 #define RX_X4_STATUS0_TSC_12_MLD_VL_INFO_0_VL_ON_LL_1_BITS 5 11363 #define RX_X4_STATUS0_TSC_12_MLD_VL_INFO_0_VL_ON_LL_1_SHIFT 5 11364 11365 /* RX_X4_Status0_tsc_12 :: mld_vl_info_0 :: VL_ON_LL_0 [04:00] */ 11366 #define RX_X4_STATUS0_TSC_12_MLD_VL_INFO_0_VL_ON_LL_0_MASK 0x001f 11367 #define RX_X4_STATUS0_TSC_12_MLD_VL_INFO_0_VL_ON_LL_0_ALIGN 0 11368 #define RX_X4_STATUS0_TSC_12_MLD_VL_INFO_0_VL_ON_LL_0_BITS 5 11369 #define RX_X4_STATUS0_TSC_12_MLD_VL_INFO_0_VL_ON_LL_0_SHIFT 0 11370 11371 11372 /**************************************************************************** 11373 * RX_X4_Status0_tsc_12 :: barrel_shifter_state 11374 */ 11375 /* RX_X4_Status0_tsc_12 :: barrel_shifter_state :: reserved0 [15:08] */ 11376 #define RX_X4_STATUS0_TSC_12_BARREL_SHIFTER_STATE_RESERVED0_MASK 0xff00 11377 #define RX_X4_STATUS0_TSC_12_BARREL_SHIFTER_STATE_RESERVED0_ALIGN 0 11378 #define RX_X4_STATUS0_TSC_12_BARREL_SHIFTER_STATE_RESERVED0_BITS 8 11379 #define RX_X4_STATUS0_TSC_12_BARREL_SHIFTER_STATE_RESERVED0_SHIFT 8 11380 11381 /* RX_X4_Status0_tsc_12 :: barrel_shifter_state :: shift_ammount [07:00] */ 11382 #define RX_X4_STATUS0_TSC_12_BARREL_SHIFTER_STATE_SHIFT_AMMOUNT_MASK 0x00ff 11383 #define RX_X4_STATUS0_TSC_12_BARREL_SHIFTER_STATE_SHIFT_AMMOUNT_ALIGN 0 11384 #define RX_X4_STATUS0_TSC_12_BARREL_SHIFTER_STATE_SHIFT_AMMOUNT_BITS 8 11385 #define RX_X4_STATUS0_TSC_12_BARREL_SHIFTER_STATE_SHIFT_AMMOUNT_SHIFT 0 11386 11387 11388 /**************************************************************************** 11389 * RX_X4_Status0_tsc_12 :: fec_CorrectedBlksL 11390 */ 11391 /* RX_X4_Status0_tsc_12 :: fec_CorrectedBlksL :: corCountL [15:00] */ 11392 #define RX_X4_STATUS0_TSC_12_FEC_CORRECTEDBLKSL_CORCOUNTL_MASK 0xffff 11393 #define RX_X4_STATUS0_TSC_12_FEC_CORRECTEDBLKSL_CORCOUNTL_ALIGN 0 11394 #define RX_X4_STATUS0_TSC_12_FEC_CORRECTEDBLKSL_CORCOUNTL_BITS 16 11395 #define RX_X4_STATUS0_TSC_12_FEC_CORRECTEDBLKSL_CORCOUNTL_SHIFT 0 11396 11397 11398 /**************************************************************************** 11399 * RX_X4_Status0_tsc_12 :: fec_CorrectedBlksH 11400 */ 11401 /* RX_X4_Status0_tsc_12 :: fec_CorrectedBlksH :: corCountH [15:00] */ 11402 #define RX_X4_STATUS0_TSC_12_FEC_CORRECTEDBLKSH_CORCOUNTH_MASK 0xffff 11403 #define RX_X4_STATUS0_TSC_12_FEC_CORRECTEDBLKSH_CORCOUNTH_ALIGN 0 11404 #define RX_X4_STATUS0_TSC_12_FEC_CORRECTEDBLKSH_CORCOUNTH_BITS 16 11405 #define RX_X4_STATUS0_TSC_12_FEC_CORRECTEDBLKSH_CORCOUNTH_SHIFT 0 11406 11407 11408 /**************************************************************************** 11409 * RX_X4_Status0_tsc_12 :: fec_UncorrectedBlksL 11410 */ 11411 /* RX_X4_Status0_tsc_12 :: fec_UncorrectedBlksL :: uncorCountL [15:00] */ 11412 #define RX_X4_STATUS0_TSC_12_FEC_UNCORRECTEDBLKSL_UNCORCOUNTL_MASK 0xffff 11413 #define RX_X4_STATUS0_TSC_12_FEC_UNCORRECTEDBLKSL_UNCORCOUNTL_ALIGN 0 11414 #define RX_X4_STATUS0_TSC_12_FEC_UNCORRECTEDBLKSL_UNCORCOUNTL_BITS 16 11415 #define RX_X4_STATUS0_TSC_12_FEC_UNCORRECTEDBLKSL_UNCORCOUNTL_SHIFT 0 11416 11417 11418 /**************************************************************************** 11419 * RX_X4_Status0_tsc_12 :: fec_UncorrectedBlksH 11420 */ 11421 /* RX_X4_Status0_tsc_12 :: fec_UncorrectedBlksH :: uncorCountH [15:00] */ 11422 #define RX_X4_STATUS0_TSC_12_FEC_UNCORRECTEDBLKSH_UNCORCOUNTH_MASK 0xffff 11423 #define RX_X4_STATUS0_TSC_12_FEC_UNCORRECTEDBLKSH_UNCORCOUNTH_ALIGN 0 11424 #define RX_X4_STATUS0_TSC_12_FEC_UNCORRECTEDBLKSH_UNCORCOUNTH_BITS 16 11425 #define RX_X4_STATUS0_TSC_12_FEC_UNCORRECTEDBLKSH_UNCORCOUNTH_SHIFT 0 11426 11427 11428 /**************************************************************************** 11429 * RX_X4_Status0_tsc_12 :: cl82_pcs_latched_status 11430 */ 11431 /* RX_X4_Status0_tsc_12 :: cl82_pcs_latched_status :: AM_LOCK_LH [15:15] */ 11432 #define RX_X4_STATUS0_TSC_12_CL82_PCS_LATCHED_STATUS_AM_LOCK_LH_MASK 0x8000 11433 #define RX_X4_STATUS0_TSC_12_CL82_PCS_LATCHED_STATUS_AM_LOCK_LH_ALIGN 0 11434 #define RX_X4_STATUS0_TSC_12_CL82_PCS_LATCHED_STATUS_AM_LOCK_LH_BITS 1 11435 #define RX_X4_STATUS0_TSC_12_CL82_PCS_LATCHED_STATUS_AM_LOCK_LH_SHIFT 15 11436 11437 /* RX_X4_Status0_tsc_12 :: cl82_pcs_latched_status :: AM_LOCK_LL [14:14] */ 11438 #define RX_X4_STATUS0_TSC_12_CL82_PCS_LATCHED_STATUS_AM_LOCK_LL_MASK 0x4000 11439 #define RX_X4_STATUS0_TSC_12_CL82_PCS_LATCHED_STATUS_AM_LOCK_LL_ALIGN 0 11440 #define RX_X4_STATUS0_TSC_12_CL82_PCS_LATCHED_STATUS_AM_LOCK_LL_BITS 1 11441 #define RX_X4_STATUS0_TSC_12_CL82_PCS_LATCHED_STATUS_AM_LOCK_LL_SHIFT 14 11442 11443 /* RX_X4_Status0_tsc_12 :: cl82_pcs_latched_status :: SYNC_STATUS_LH [13:13] */ 11444 #define RX_X4_STATUS0_TSC_12_CL82_PCS_LATCHED_STATUS_SYNC_STATUS_LH_MASK 0x2000 11445 #define RX_X4_STATUS0_TSC_12_CL82_PCS_LATCHED_STATUS_SYNC_STATUS_LH_ALIGN 0 11446 #define RX_X4_STATUS0_TSC_12_CL82_PCS_LATCHED_STATUS_SYNC_STATUS_LH_BITS 1 11447 #define RX_X4_STATUS0_TSC_12_CL82_PCS_LATCHED_STATUS_SYNC_STATUS_LH_SHIFT 13 11448 11449 /* RX_X4_Status0_tsc_12 :: cl82_pcs_latched_status :: SYNC_STATUS_LL [12:12] */ 11450 #define RX_X4_STATUS0_TSC_12_CL82_PCS_LATCHED_STATUS_SYNC_STATUS_LL_MASK 0x1000 11451 #define RX_X4_STATUS0_TSC_12_CL82_PCS_LATCHED_STATUS_SYNC_STATUS_LL_ALIGN 0 11452 #define RX_X4_STATUS0_TSC_12_CL82_PCS_LATCHED_STATUS_SYNC_STATUS_LL_BITS 1 11453 #define RX_X4_STATUS0_TSC_12_CL82_PCS_LATCHED_STATUS_SYNC_STATUS_LL_SHIFT 12 11454 11455 /* RX_X4_Status0_tsc_12 :: cl82_pcs_latched_status :: reserved0 [11:11] */ 11456 #define RX_X4_STATUS0_TSC_12_CL82_PCS_LATCHED_STATUS_RESERVED0_MASK 0x0800 11457 #define RX_X4_STATUS0_TSC_12_CL82_PCS_LATCHED_STATUS_RESERVED0_ALIGN 0 11458 #define RX_X4_STATUS0_TSC_12_CL82_PCS_LATCHED_STATUS_RESERVED0_BITS 1 11459 #define RX_X4_STATUS0_TSC_12_CL82_PCS_LATCHED_STATUS_RESERVED0_SHIFT 11 11460 11461 /* RX_X4_Status0_tsc_12 :: cl82_pcs_latched_status :: amrkr_spacing_err_latch_mux [10:10] */ 11462 #define RX_X4_STATUS0_TSC_12_CL82_PCS_LATCHED_STATUS_AMRKR_SPACING_ERR_LATCH_MUX_MASK 0x0400 11463 #define RX_X4_STATUS0_TSC_12_CL82_PCS_LATCHED_STATUS_AMRKR_SPACING_ERR_LATCH_MUX_ALIGN 0 11464 #define RX_X4_STATUS0_TSC_12_CL82_PCS_LATCHED_STATUS_AMRKR_SPACING_ERR_LATCH_MUX_BITS 1 11465 #define RX_X4_STATUS0_TSC_12_CL82_PCS_LATCHED_STATUS_AMRKR_SPACING_ERR_LATCH_MUX_SHIFT 10 11466 11467 /* RX_X4_Status0_tsc_12 :: cl82_pcs_latched_status :: am_lock_his_state [09:00] */ 11468 #define RX_X4_STATUS0_TSC_12_CL82_PCS_LATCHED_STATUS_AM_LOCK_HIS_STATE_MASK 0x03ff 11469 #define RX_X4_STATUS0_TSC_12_CL82_PCS_LATCHED_STATUS_AM_LOCK_HIS_STATE_ALIGN 0 11470 #define RX_X4_STATUS0_TSC_12_CL82_PCS_LATCHED_STATUS_AM_LOCK_HIS_STATE_BITS 10 11471 #define RX_X4_STATUS0_TSC_12_CL82_PCS_LATCHED_STATUS_AM_LOCK_HIS_STATE_SHIFT 0 11472 11473 11474 /**************************************************************************** 11475 * RX_X4_Status0_tsc_12 :: cl82_pcs_live_status 11476 */ 11477 /* RX_X4_Status0_tsc_12 :: cl82_pcs_live_status :: AM_LOCK [15:15] */ 11478 #define RX_X4_STATUS0_TSC_12_CL82_PCS_LIVE_STATUS_AM_LOCK_MASK 0x8000 11479 #define RX_X4_STATUS0_TSC_12_CL82_PCS_LIVE_STATUS_AM_LOCK_ALIGN 0 11480 #define RX_X4_STATUS0_TSC_12_CL82_PCS_LIVE_STATUS_AM_LOCK_BITS 1 11481 #define RX_X4_STATUS0_TSC_12_CL82_PCS_LIVE_STATUS_AM_LOCK_SHIFT 15 11482 11483 /* RX_X4_Status0_tsc_12 :: cl82_pcs_live_status :: SYNC_STATUS [14:14] */ 11484 #define RX_X4_STATUS0_TSC_12_CL82_PCS_LIVE_STATUS_SYNC_STATUS_MASK 0x4000 11485 #define RX_X4_STATUS0_TSC_12_CL82_PCS_LIVE_STATUS_SYNC_STATUS_ALIGN 0 11486 #define RX_X4_STATUS0_TSC_12_CL82_PCS_LIVE_STATUS_SYNC_STATUS_BITS 1 11487 #define RX_X4_STATUS0_TSC_12_CL82_PCS_LIVE_STATUS_SYNC_STATUS_SHIFT 14 11488 11489 /* RX_X4_Status0_tsc_12 :: cl82_pcs_live_status :: reserved0 [13:10] */ 11490 #define RX_X4_STATUS0_TSC_12_CL82_PCS_LIVE_STATUS_RESERVED0_MASK 0x3c00 11491 #define RX_X4_STATUS0_TSC_12_CL82_PCS_LIVE_STATUS_RESERVED0_ALIGN 0 11492 #define RX_X4_STATUS0_TSC_12_CL82_PCS_LIVE_STATUS_RESERVED0_BITS 4 11493 #define RX_X4_STATUS0_TSC_12_CL82_PCS_LIVE_STATUS_RESERVED0_SHIFT 10 11494 11495 /* RX_X4_Status0_tsc_12 :: cl82_pcs_live_status :: am_lock_state [09:00] */ 11496 #define RX_X4_STATUS0_TSC_12_CL82_PCS_LIVE_STATUS_AM_LOCK_STATE_MASK 0x03ff 11497 #define RX_X4_STATUS0_TSC_12_CL82_PCS_LIVE_STATUS_AM_LOCK_STATE_ALIGN 0 11498 #define RX_X4_STATUS0_TSC_12_CL82_PCS_LIVE_STATUS_AM_LOCK_STATE_BITS 10 11499 #define RX_X4_STATUS0_TSC_12_CL82_PCS_LIVE_STATUS_AM_LOCK_STATE_SHIFT 0 11500 11501 11502 /**************************************************************************** 11503 * TSCE_TSCE_USER4_AN_X4_ABILITIES 11504 */ 11505 /**************************************************************************** 11506 * AN_X4_ABILITIES :: enables 11507 */ 11508 /* AN_X4_ABILITIES :: enables :: reserved0 [15:14] */ 11509 #define AN_X4_ABILITIES_ENABLES_RESERVED0_MASK 0xc000 11510 #define AN_X4_ABILITIES_ENABLES_RESERVED0_ALIGN 0 11511 #define AN_X4_ABILITIES_ENABLES_RESERVED0_BITS 2 11512 #define AN_X4_ABILITIES_ENABLES_RESERVED0_SHIFT 14 11513 11514 /* AN_X4_ABILITIES :: enables :: num_advertised_lanes [13:12] */ 11515 #define AN_X4_ABILITIES_ENABLES_NUM_ADVERTISED_LANES_MASK 0x3000 11516 #define AN_X4_ABILITIES_ENABLES_NUM_ADVERTISED_LANES_ALIGN 0 11517 #define AN_X4_ABILITIES_ENABLES_NUM_ADVERTISED_LANES_BITS 2 11518 #define AN_X4_ABILITIES_ENABLES_NUM_ADVERTISED_LANES_SHIFT 12 11519 11520 /* AN_X4_ABILITIES :: enables :: cl37_bam_enable [11:11] */ 11521 #define AN_X4_ABILITIES_ENABLES_CL37_BAM_ENABLE_MASK 0x0800 11522 #define AN_X4_ABILITIES_ENABLES_CL37_BAM_ENABLE_ALIGN 0 11523 #define AN_X4_ABILITIES_ENABLES_CL37_BAM_ENABLE_BITS 1 11524 #define AN_X4_ABILITIES_ENABLES_CL37_BAM_ENABLE_SHIFT 11 11525 11526 /* AN_X4_ABILITIES :: enables :: cl73_bam_enable [10:10] */ 11527 #define AN_X4_ABILITIES_ENABLES_CL73_BAM_ENABLE_MASK 0x0400 11528 #define AN_X4_ABILITIES_ENABLES_CL73_BAM_ENABLE_ALIGN 0 11529 #define AN_X4_ABILITIES_ENABLES_CL73_BAM_ENABLE_BITS 1 11530 #define AN_X4_ABILITIES_ENABLES_CL73_BAM_ENABLE_SHIFT 10 11531 11532 /* AN_X4_ABILITIES :: enables :: cl73_hpam_enable [09:09] */ 11533 #define AN_X4_ABILITIES_ENABLES_CL73_HPAM_ENABLE_MASK 0x0200 11534 #define AN_X4_ABILITIES_ENABLES_CL73_HPAM_ENABLE_ALIGN 0 11535 #define AN_X4_ABILITIES_ENABLES_CL73_HPAM_ENABLE_BITS 1 11536 #define AN_X4_ABILITIES_ENABLES_CL73_HPAM_ENABLE_SHIFT 9 11537 11538 /* AN_X4_ABILITIES :: enables :: cl73_enable [08:08] */ 11539 #define AN_X4_ABILITIES_ENABLES_CL73_ENABLE_MASK 0x0100 11540 #define AN_X4_ABILITIES_ENABLES_CL73_ENABLE_ALIGN 0 11541 #define AN_X4_ABILITIES_ENABLES_CL73_ENABLE_BITS 1 11542 #define AN_X4_ABILITIES_ENABLES_CL73_ENABLE_SHIFT 8 11543 11544 /* AN_X4_ABILITIES :: enables :: cl37_sgmii_enable [07:07] */ 11545 #define AN_X4_ABILITIES_ENABLES_CL37_SGMII_ENABLE_MASK 0x0080 11546 #define AN_X4_ABILITIES_ENABLES_CL37_SGMII_ENABLE_ALIGN 0 11547 #define AN_X4_ABILITIES_ENABLES_CL37_SGMII_ENABLE_BITS 1 11548 #define AN_X4_ABILITIES_ENABLES_CL37_SGMII_ENABLE_SHIFT 7 11549 11550 /* AN_X4_ABILITIES :: enables :: cl37_enable [06:06] */ 11551 #define AN_X4_ABILITIES_ENABLES_CL37_ENABLE_MASK 0x0040 11552 #define AN_X4_ABILITIES_ENABLES_CL37_ENABLE_ALIGN 0 11553 #define AN_X4_ABILITIES_ENABLES_CL37_ENABLE_BITS 1 11554 #define AN_X4_ABILITIES_ENABLES_CL37_ENABLE_SHIFT 6 11555 11556 /* AN_X4_ABILITIES :: enables :: cl37_bam_to_sgmii_auto_enable [05:05] */ 11557 #define AN_X4_ABILITIES_ENABLES_CL37_BAM_TO_SGMII_AUTO_ENABLE_MASK 0x0020 11558 #define AN_X4_ABILITIES_ENABLES_CL37_BAM_TO_SGMII_AUTO_ENABLE_ALIGN 0 11559 #define AN_X4_ABILITIES_ENABLES_CL37_BAM_TO_SGMII_AUTO_ENABLE_BITS 1 11560 #define AN_X4_ABILITIES_ENABLES_CL37_BAM_TO_SGMII_AUTO_ENABLE_SHIFT 5 11561 11562 /* AN_X4_ABILITIES :: enables :: sgmii_to_cl37_auto_enable [04:04] */ 11563 #define AN_X4_ABILITIES_ENABLES_SGMII_TO_CL37_AUTO_ENABLE_MASK 0x0010 11564 #define AN_X4_ABILITIES_ENABLES_SGMII_TO_CL37_AUTO_ENABLE_ALIGN 0 11565 #define AN_X4_ABILITIES_ENABLES_SGMII_TO_CL37_AUTO_ENABLE_BITS 1 11566 #define AN_X4_ABILITIES_ENABLES_SGMII_TO_CL37_AUTO_ENABLE_SHIFT 4 11567 11568 /* AN_X4_ABILITIES :: enables :: cl73_bam_to_hpam_auto_enable [03:03] */ 11569 #define AN_X4_ABILITIES_ENABLES_CL73_BAM_TO_HPAM_AUTO_ENABLE_MASK 0x0008 11570 #define AN_X4_ABILITIES_ENABLES_CL73_BAM_TO_HPAM_AUTO_ENABLE_ALIGN 0 11571 #define AN_X4_ABILITIES_ENABLES_CL73_BAM_TO_HPAM_AUTO_ENABLE_BITS 1 11572 #define AN_X4_ABILITIES_ENABLES_CL73_BAM_TO_HPAM_AUTO_ENABLE_SHIFT 3 11573 11574 /* AN_X4_ABILITIES :: enables :: hpam_to_cl73_auto_enable [02:02] */ 11575 #define AN_X4_ABILITIES_ENABLES_HPAM_TO_CL73_AUTO_ENABLE_MASK 0x0004 11576 #define AN_X4_ABILITIES_ENABLES_HPAM_TO_CL73_AUTO_ENABLE_ALIGN 0 11577 #define AN_X4_ABILITIES_ENABLES_HPAM_TO_CL73_AUTO_ENABLE_BITS 1 11578 #define AN_X4_ABILITIES_ENABLES_HPAM_TO_CL73_AUTO_ENABLE_SHIFT 2 11579 11580 /* AN_X4_ABILITIES :: enables :: cl37_an_restart [01:01] */ 11581 #define AN_X4_ABILITIES_ENABLES_CL37_AN_RESTART_MASK 0x0002 11582 #define AN_X4_ABILITIES_ENABLES_CL37_AN_RESTART_ALIGN 0 11583 #define AN_X4_ABILITIES_ENABLES_CL37_AN_RESTART_BITS 1 11584 #define AN_X4_ABILITIES_ENABLES_CL37_AN_RESTART_SHIFT 1 11585 11586 /* AN_X4_ABILITIES :: enables :: cl73_an_restart [00:00] */ 11587 #define AN_X4_ABILITIES_ENABLES_CL73_AN_RESTART_MASK 0x0001 11588 #define AN_X4_ABILITIES_ENABLES_CL73_AN_RESTART_ALIGN 0 11589 #define AN_X4_ABILITIES_ENABLES_CL73_AN_RESTART_BITS 1 11590 #define AN_X4_ABILITIES_ENABLES_CL73_AN_RESTART_SHIFT 0 11591 11592 11593 /**************************************************************************** 11594 * AN_X4_ABILITIES :: local_device_cl37_base_abilities 11595 */ 11596 /* AN_X4_ABILITIES :: local_device_cl37_base_abilities :: reserved0 [15:13] */ 11597 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_RESERVED0_MASK 0xe000 11598 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_RESERVED0_ALIGN 0 11599 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_RESERVED0_BITS 3 11600 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_RESERVED0_SHIFT 13 11601 11602 /* AN_X4_ABILITIES :: local_device_cl37_base_abilities :: cl37_sw_restart_reset_disable [12:12] */ 11603 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_CL37_SW_RESTART_RESET_DISABLE_MASK 0x1000 11604 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_CL37_SW_RESTART_RESET_DISABLE_ALIGN 0 11605 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_CL37_SW_RESTART_RESET_DISABLE_BITS 1 11606 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_CL37_SW_RESTART_RESET_DISABLE_SHIFT 12 11607 11608 /* AN_X4_ABILITIES :: local_device_cl37_base_abilities :: cl37_an_restart_reset_disable [11:11] */ 11609 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_CL37_AN_RESTART_RESET_DISABLE_MASK 0x0800 11610 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_CL37_AN_RESTART_RESET_DISABLE_ALIGN 0 11611 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_CL37_AN_RESTART_RESET_DISABLE_BITS 1 11612 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_CL37_AN_RESTART_RESET_DISABLE_SHIFT 11 11613 11614 /* AN_X4_ABILITIES :: local_device_cl37_base_abilities :: an_pd_to_cl37_enable [10:10] */ 11615 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_AN_PD_TO_CL37_ENABLE_MASK 0x0400 11616 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_AN_PD_TO_CL37_ENABLE_ALIGN 0 11617 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_AN_PD_TO_CL37_ENABLE_BITS 1 11618 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_AN_PD_TO_CL37_ENABLE_SHIFT 10 11619 11620 /* AN_X4_ABILITIES :: local_device_cl37_base_abilities :: sgmii_master_mode [09:09] */ 11621 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_SGMII_MASTER_MODE_MASK 0x0200 11622 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_SGMII_MASTER_MODE_ALIGN 0 11623 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_SGMII_MASTER_MODE_BITS 1 11624 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_SGMII_MASTER_MODE_SHIFT 9 11625 11626 /* AN_X4_ABILITIES :: local_device_cl37_base_abilities :: cl37_next_page [08:08] */ 11627 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_CL37_NEXT_PAGE_MASK 0x0100 11628 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_CL37_NEXT_PAGE_ALIGN 0 11629 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_CL37_NEXT_PAGE_BITS 1 11630 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_CL37_NEXT_PAGE_SHIFT 8 11631 11632 /* AN_X4_ABILITIES :: local_device_cl37_base_abilities :: cl37_pause [07:06] */ 11633 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_CL37_PAUSE_MASK 0x00c0 11634 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_CL37_PAUSE_ALIGN 0 11635 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_CL37_PAUSE_BITS 2 11636 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_CL37_PAUSE_SHIFT 6 11637 11638 /* AN_X4_ABILITIES :: local_device_cl37_base_abilities :: cl37_half_duplex [05:05] */ 11639 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_CL37_HALF_DUPLEX_MASK 0x0020 11640 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_CL37_HALF_DUPLEX_ALIGN 0 11641 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_CL37_HALF_DUPLEX_BITS 1 11642 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_CL37_HALF_DUPLEX_SHIFT 5 11643 11644 /* AN_X4_ABILITIES :: local_device_cl37_base_abilities :: cl37_full_duplex [04:04] */ 11645 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_CL37_FULL_DUPLEX_MASK 0x0010 11646 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_CL37_FULL_DUPLEX_ALIGN 0 11647 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_CL37_FULL_DUPLEX_BITS 1 11648 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_CL37_FULL_DUPLEX_SHIFT 4 11649 11650 /* AN_X4_ABILITIES :: local_device_cl37_base_abilities :: reserved1 [03:03] */ 11651 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_RESERVED1_MASK 0x0008 11652 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_RESERVED1_ALIGN 0 11653 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_RESERVED1_BITS 1 11654 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_RESERVED1_SHIFT 3 11655 11656 /* AN_X4_ABILITIES :: local_device_cl37_base_abilities :: sgmii_full_duplex [02:02] */ 11657 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_SGMII_FULL_DUPLEX_MASK 0x0004 11658 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_SGMII_FULL_DUPLEX_ALIGN 0 11659 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_SGMII_FULL_DUPLEX_BITS 1 11660 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_SGMII_FULL_DUPLEX_SHIFT 2 11661 11662 /* AN_X4_ABILITIES :: local_device_cl37_base_abilities :: sgmii_speed [01:00] */ 11663 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_SGMII_SPEED_MASK 0x0003 11664 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_SGMII_SPEED_ALIGN 0 11665 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_SGMII_SPEED_BITS 2 11666 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BASE_ABILITIES_SGMII_SPEED_SHIFT 0 11667 11668 11669 /**************************************************************************** 11670 * AN_X4_ABILITIES :: local_device_cl37_bam_abilities 11671 */ 11672 /* AN_X4_ABILITIES :: local_device_cl37_bam_abilities :: reserved0 [15:12] */ 11673 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BAM_ABILITIES_RESERVED0_MASK 0xf000 11674 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BAM_ABILITIES_RESERVED0_ALIGN 0 11675 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BAM_ABILITIES_RESERVED0_BITS 4 11676 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BAM_ABILITIES_RESERVED0_SHIFT 12 11677 11678 /* AN_X4_ABILITIES :: local_device_cl37_bam_abilities :: cl37_bam_code [11:03] */ 11679 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BAM_ABILITIES_CL37_BAM_CODE_MASK 0x0ff8 11680 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BAM_ABILITIES_CL37_BAM_CODE_ALIGN 0 11681 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BAM_ABILITIES_CL37_BAM_CODE_BITS 9 11682 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BAM_ABILITIES_CL37_BAM_CODE_SHIFT 3 11683 11684 /* AN_X4_ABILITIES :: local_device_cl37_bam_abilities :: over1g_ability [02:02] */ 11685 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BAM_ABILITIES_OVER1G_ABILITY_MASK 0x0004 11686 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BAM_ABILITIES_OVER1G_ABILITY_ALIGN 0 11687 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BAM_ABILITIES_OVER1G_ABILITY_BITS 1 11688 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BAM_ABILITIES_OVER1G_ABILITY_SHIFT 2 11689 11690 /* AN_X4_ABILITIES :: local_device_cl37_bam_abilities :: over1g_page_count [01:00] */ 11691 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BAM_ABILITIES_OVER1G_PAGE_COUNT_MASK 0x0003 11692 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BAM_ABILITIES_OVER1G_PAGE_COUNT_ALIGN 0 11693 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BAM_ABILITIES_OVER1G_PAGE_COUNT_BITS 2 11694 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL37_BAM_ABILITIES_OVER1G_PAGE_COUNT_SHIFT 0 11695 11696 11697 /**************************************************************************** 11698 * AN_X4_ABILITIES :: local_device_over1g_abilities_1 11699 */ 11700 /* AN_X4_ABILITIES :: local_device_over1g_abilities_1 :: HG2 [15:15] */ 11701 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_HG2_MASK 0x8000 11702 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_HG2_ALIGN 0 11703 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_HG2_BITS 1 11704 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_HG2_SHIFT 15 11705 11706 /* AN_X4_ABILITIES :: local_device_over1g_abilities_1 :: FEC [14:14] */ 11707 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_FEC_MASK 0x4000 11708 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_FEC_ALIGN 0 11709 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_FEC_BITS 1 11710 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_FEC_SHIFT 14 11711 11712 /* AN_X4_ABILITIES :: local_device_over1g_abilities_1 :: CL72 [13:13] */ 11713 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_CL72_MASK 0x2000 11714 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_CL72_ALIGN 0 11715 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_CL72_BITS 1 11716 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_CL72_SHIFT 13 11717 11718 /* AN_X4_ABILITIES :: local_device_over1g_abilities_1 :: BAM_40GBASE_X4 [12:12] */ 11719 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_40GBASE_X4_MASK 0x1000 11720 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_40GBASE_X4_ALIGN 0 11721 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_40GBASE_X4_BITS 1 11722 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_40GBASE_X4_SHIFT 12 11723 11724 /* AN_X4_ABILITIES :: local_device_over1g_abilities_1 :: BAM_32p7GBASE_X4 [11:11] */ 11725 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_32P7GBASE_X4_MASK 0x0800 11726 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_32P7GBASE_X4_ALIGN 0 11727 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_32P7GBASE_X4_BITS 1 11728 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_32P7GBASE_X4_SHIFT 11 11729 11730 /* AN_X4_ABILITIES :: local_device_over1g_abilities_1 :: BAM_31p5GBASE_X4 [10:10] */ 11731 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_31P5GBASE_X4_MASK 0x0400 11732 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_31P5GBASE_X4_ALIGN 0 11733 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_31P5GBASE_X4_BITS 1 11734 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_31P5GBASE_X4_SHIFT 10 11735 11736 /* AN_X4_ABILITIES :: local_device_over1g_abilities_1 :: BAM_25p455GBASE_X4 [09:09] */ 11737 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_25P455GBASE_X4_MASK 0x0200 11738 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_25P455GBASE_X4_ALIGN 0 11739 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_25P455GBASE_X4_BITS 1 11740 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_25P455GBASE_X4_SHIFT 9 11741 11742 /* AN_X4_ABILITIES :: local_device_over1g_abilities_1 :: BAM_21GBASE_X4 [08:08] */ 11743 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_21GBASE_X4_MASK 0x0100 11744 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_21GBASE_X4_ALIGN 0 11745 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_21GBASE_X4_BITS 1 11746 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_21GBASE_X4_SHIFT 8 11747 11748 /* AN_X4_ABILITIES :: local_device_over1g_abilities_1 :: BAM_20GBASE_X2_CX4 [07:07] */ 11749 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_20GBASE_X2_CX4_MASK 0x0080 11750 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_20GBASE_X2_CX4_ALIGN 0 11751 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_20GBASE_X2_CX4_BITS 1 11752 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_20GBASE_X2_CX4_SHIFT 7 11753 11754 /* AN_X4_ABILITIES :: local_device_over1g_abilities_1 :: BAM_20GBASE_X2 [06:06] */ 11755 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_20GBASE_X2_MASK 0x0040 11756 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_20GBASE_X2_ALIGN 0 11757 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_20GBASE_X2_BITS 1 11758 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_20GBASE_X2_SHIFT 6 11759 11760 /* AN_X4_ABILITIES :: local_device_over1g_abilities_1 :: BAM_20GBASE_X4 [05:05] */ 11761 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_20GBASE_X4_MASK 0x0020 11762 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_20GBASE_X4_ALIGN 0 11763 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_20GBASE_X4_BITS 1 11764 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_20GBASE_X4_SHIFT 5 11765 11766 /* AN_X4_ABILITIES :: local_device_over1g_abilities_1 :: BAM_20GBASE_X4_CX4 [04:04] */ 11767 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_20GBASE_X4_CX4_MASK 0x0010 11768 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_20GBASE_X4_CX4_ALIGN 0 11769 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_20GBASE_X4_CX4_BITS 1 11770 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_20GBASE_X4_CX4_SHIFT 4 11771 11772 /* AN_X4_ABILITIES :: local_device_over1g_abilities_1 :: BAM_16GBASE_X4 [03:03] */ 11773 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_16GBASE_X4_MASK 0x0008 11774 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_16GBASE_X4_ALIGN 0 11775 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_16GBASE_X4_BITS 1 11776 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_16GBASE_X4_SHIFT 3 11777 11778 /* AN_X4_ABILITIES :: local_device_over1g_abilities_1 :: BAM_15p75GBASE_X2 [02:02] */ 11779 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_15P75GBASE_X2_MASK 0x0004 11780 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_15P75GBASE_X2_ALIGN 0 11781 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_15P75GBASE_X2_BITS 1 11782 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_15P75GBASE_X2_SHIFT 2 11783 11784 /* AN_X4_ABILITIES :: local_device_over1g_abilities_1 :: BAM_15GBASE_X4 [01:01] */ 11785 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_15GBASE_X4_MASK 0x0002 11786 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_15GBASE_X4_ALIGN 0 11787 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_15GBASE_X4_BITS 1 11788 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_15GBASE_X4_SHIFT 1 11789 11790 /* AN_X4_ABILITIES :: local_device_over1g_abilities_1 :: BAM_13GBASE_X4 [00:00] */ 11791 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_13GBASE_X4_MASK 0x0001 11792 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_13GBASE_X4_ALIGN 0 11793 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_13GBASE_X4_BITS 1 11794 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_1_BAM_13GBASE_X4_SHIFT 0 11795 11796 11797 /**************************************************************************** 11798 * AN_X4_ABILITIES :: local_device_over1g_abilities_0 11799 */ 11800 /* AN_X4_ABILITIES :: local_device_over1g_abilities_0 :: reserved0 [15:11] */ 11801 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_RESERVED0_MASK 0xf800 11802 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_RESERVED0_ALIGN 0 11803 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_RESERVED0_BITS 5 11804 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_RESERVED0_SHIFT 11 11805 11806 /* AN_X4_ABILITIES :: local_device_over1g_abilities_0 :: BAM_12p7GBASE_X2 [10:10] */ 11807 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_12P7GBASE_X2_MASK 0x0400 11808 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_12P7GBASE_X2_ALIGN 0 11809 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_12P7GBASE_X2_BITS 1 11810 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_12P7GBASE_X2_SHIFT 10 11811 11812 /* AN_X4_ABILITIES :: local_device_over1g_abilities_0 :: BAM_12p5GBASE_X4 [09:09] */ 11813 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_12P5GBASE_X4_MASK 0x0200 11814 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_12P5GBASE_X4_ALIGN 0 11815 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_12P5GBASE_X4_BITS 1 11816 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_12P5GBASE_X4_SHIFT 9 11817 11818 /* AN_X4_ABILITIES :: local_device_over1g_abilities_0 :: BAM_12GBASE_X4 [08:08] */ 11819 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_12GBASE_X4_MASK 0x0100 11820 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_12GBASE_X4_ALIGN 0 11821 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_12GBASE_X4_BITS 1 11822 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_12GBASE_X4_SHIFT 8 11823 11824 /* AN_X4_ABILITIES :: local_device_over1g_abilities_0 :: BAM_10p5GBASE_X2 [07:07] */ 11825 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_10P5GBASE_X2_MASK 0x0080 11826 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_10P5GBASE_X2_ALIGN 0 11827 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_10P5GBASE_X2_BITS 1 11828 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_10P5GBASE_X2_SHIFT 7 11829 11830 /* AN_X4_ABILITIES :: local_device_over1g_abilities_0 :: BAM_10GBASE_X2_CX4 [06:06] */ 11831 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_10GBASE_X2_CX4_MASK 0x0040 11832 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_10GBASE_X2_CX4_ALIGN 0 11833 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_10GBASE_X2_CX4_BITS 1 11834 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_10GBASE_X2_CX4_SHIFT 6 11835 11836 /* AN_X4_ABILITIES :: local_device_over1g_abilities_0 :: BAM_10GBASE_X2 [05:05] */ 11837 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_10GBASE_X2_MASK 0x0020 11838 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_10GBASE_X2_ALIGN 0 11839 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_10GBASE_X2_BITS 1 11840 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_10GBASE_X2_SHIFT 5 11841 11842 /* AN_X4_ABILITIES :: local_device_over1g_abilities_0 :: BAM_10GBASE_X4_CX4 [04:04] */ 11843 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_10GBASE_X4_CX4_MASK 0x0010 11844 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_10GBASE_X4_CX4_ALIGN 0 11845 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_10GBASE_X4_CX4_BITS 1 11846 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_10GBASE_X4_CX4_SHIFT 4 11847 11848 /* AN_X4_ABILITIES :: local_device_over1g_abilities_0 :: BAM_10GBASE_X4 [03:03] */ 11849 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_10GBASE_X4_MASK 0x0008 11850 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_10GBASE_X4_ALIGN 0 11851 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_10GBASE_X4_BITS 1 11852 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_10GBASE_X4_SHIFT 3 11853 11854 /* AN_X4_ABILITIES :: local_device_over1g_abilities_0 :: BAM_6GBASE_X4 [02:02] */ 11855 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_6GBASE_X4_MASK 0x0004 11856 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_6GBASE_X4_ALIGN 0 11857 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_6GBASE_X4_BITS 1 11858 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_6GBASE_X4_SHIFT 2 11859 11860 /* AN_X4_ABILITIES :: local_device_over1g_abilities_0 :: BAM_5GBASE_X4 [01:01] */ 11861 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_5GBASE_X4_MASK 0x0002 11862 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_5GBASE_X4_ALIGN 0 11863 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_5GBASE_X4_BITS 1 11864 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_5GBASE_X4_SHIFT 1 11865 11866 /* AN_X4_ABILITIES :: local_device_over1g_abilities_0 :: BAM_2p5GBASE_X [00:00] */ 11867 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_2P5GBASE_X_MASK 0x0001 11868 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_2P5GBASE_X_ALIGN 0 11869 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_2P5GBASE_X_BITS 1 11870 #define AN_X4_ABILITIES_LOCAL_DEVICE_OVER1G_ABILITIES_0_BAM_2P5GBASE_X_SHIFT 0 11871 11872 11873 /**************************************************************************** 11874 * AN_X4_ABILITIES :: local_device_cl73_base_abilities_1 11875 */ 11876 /* AN_X4_ABILITIES :: local_device_cl73_base_abilities_1 :: reserved0 [15:12] */ 11877 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_1_RESERVED0_MASK 0xf000 11878 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_1_RESERVED0_ALIGN 0 11879 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_1_RESERVED0_BITS 4 11880 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_1_RESERVED0_SHIFT 12 11881 11882 /* AN_X4_ABILITIES :: local_device_cl73_base_abilities_1 :: cl73_nonce_match_over [11:11] */ 11883 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_1_CL73_NONCE_MATCH_OVER_MASK 0x0800 11884 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_1_CL73_NONCE_MATCH_OVER_ALIGN 0 11885 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_1_CL73_NONCE_MATCH_OVER_BITS 1 11886 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_1_CL73_NONCE_MATCH_OVER_SHIFT 11 11887 11888 /* AN_X4_ABILITIES :: local_device_cl73_base_abilities_1 :: cl73_nonce_match_val [10:10] */ 11889 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_1_CL73_NONCE_MATCH_VAL_MASK 0x0400 11890 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_1_CL73_NONCE_MATCH_VAL_ALIGN 0 11891 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_1_CL73_NONCE_MATCH_VAL_BITS 1 11892 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_1_CL73_NONCE_MATCH_VAL_SHIFT 10 11893 11894 /* AN_X4_ABILITIES :: local_device_cl73_base_abilities_1 :: transmit_nonce [09:05] */ 11895 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_1_TRANSMIT_NONCE_MASK 0x03e0 11896 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_1_TRANSMIT_NONCE_ALIGN 0 11897 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_1_TRANSMIT_NONCE_BITS 5 11898 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_1_TRANSMIT_NONCE_SHIFT 5 11899 11900 /* AN_X4_ABILITIES :: local_device_cl73_base_abilities_1 :: base_selector [04:00] */ 11901 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_1_BASE_SELECTOR_MASK 0x001f 11902 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_1_BASE_SELECTOR_ALIGN 0 11903 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_1_BASE_SELECTOR_BITS 5 11904 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_1_BASE_SELECTOR_SHIFT 0 11905 11906 11907 /**************************************************************************** 11908 * AN_X4_ABILITIES :: local_device_cl73_base_abilities_0 11909 */ 11910 /* AN_X4_ABILITIES :: local_device_cl73_base_abilities_0 :: reserved0 [15:12] */ 11911 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_RESERVED0_MASK 0xf000 11912 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_RESERVED0_ALIGN 0 11913 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_RESERVED0_BITS 4 11914 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_RESERVED0_SHIFT 12 11915 11916 /* AN_X4_ABILITIES :: local_device_cl73_base_abilities_0 :: cl73_remote_fault [11:11] */ 11917 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_CL73_REMOTE_FAULT_MASK 0x0800 11918 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_CL73_REMOTE_FAULT_ALIGN 0 11919 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_CL73_REMOTE_FAULT_BITS 1 11920 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_CL73_REMOTE_FAULT_SHIFT 11 11921 11922 /* AN_X4_ABILITIES :: local_device_cl73_base_abilities_0 :: next_page [10:10] */ 11923 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_NEXT_PAGE_MASK 0x0400 11924 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_NEXT_PAGE_ALIGN 0 11925 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_NEXT_PAGE_BITS 1 11926 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_NEXT_PAGE_SHIFT 10 11927 11928 /* AN_X4_ABILITIES :: local_device_cl73_base_abilities_0 :: fec [09:08] */ 11929 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_FEC_MASK 0x0300 11930 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_FEC_ALIGN 0 11931 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_FEC_BITS 2 11932 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_FEC_SHIFT 8 11933 11934 /* AN_X4_ABILITIES :: local_device_cl73_base_abilities_0 :: cl73_pause [07:06] */ 11935 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_CL73_PAUSE_MASK 0x00c0 11936 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_CL73_PAUSE_ALIGN 0 11937 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_CL73_PAUSE_BITS 2 11938 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_CL73_PAUSE_SHIFT 6 11939 11940 /* AN_X4_ABILITIES :: local_device_cl73_base_abilities_0 :: BASE_1000BASE_KX [05:05] */ 11941 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_BASE_1000BASE_KX_MASK 0x0020 11942 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_BASE_1000BASE_KX_ALIGN 0 11943 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_BASE_1000BASE_KX_BITS 1 11944 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_BASE_1000BASE_KX_SHIFT 5 11945 11946 /* AN_X4_ABILITIES :: local_device_cl73_base_abilities_0 :: BASE_10GBASE_KX4 [04:04] */ 11947 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_BASE_10GBASE_KX4_MASK 0x0010 11948 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_BASE_10GBASE_KX4_ALIGN 0 11949 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_BASE_10GBASE_KX4_BITS 1 11950 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_BASE_10GBASE_KX4_SHIFT 4 11951 11952 /* AN_X4_ABILITIES :: local_device_cl73_base_abilities_0 :: BASE_10GBASE_KR [03:03] */ 11953 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_BASE_10GBASE_KR_MASK 0x0008 11954 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_BASE_10GBASE_KR_ALIGN 0 11955 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_BASE_10GBASE_KR_BITS 1 11956 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_BASE_10GBASE_KR_SHIFT 3 11957 11958 /* AN_X4_ABILITIES :: local_device_cl73_base_abilities_0 :: BASE_40GBASE_KR4 [02:02] */ 11959 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_BASE_40GBASE_KR4_MASK 0x0004 11960 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_BASE_40GBASE_KR4_ALIGN 0 11961 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_BASE_40GBASE_KR4_BITS 1 11962 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_BASE_40GBASE_KR4_SHIFT 2 11963 11964 /* AN_X4_ABILITIES :: local_device_cl73_base_abilities_0 :: BASE_40GBASE_CR4 [01:01] */ 11965 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_BASE_40GBASE_CR4_MASK 0x0002 11966 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_BASE_40GBASE_CR4_ALIGN 0 11967 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_BASE_40GBASE_CR4_BITS 1 11968 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_BASE_40GBASE_CR4_SHIFT 1 11969 11970 /* AN_X4_ABILITIES :: local_device_cl73_base_abilities_0 :: BASE_100GBASE_CR10 [00:00] */ 11971 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_BASE_100GBASE_CR10_MASK 0x0001 11972 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_BASE_100GBASE_CR10_ALIGN 0 11973 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_BASE_100GBASE_CR10_BITS 1 11974 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BASE_ABILITIES_0_BASE_100GBASE_CR10_SHIFT 0 11975 11976 11977 /**************************************************************************** 11978 * AN_X4_ABILITIES :: local_device_cl73_bam_abilities 11979 */ 11980 /* AN_X4_ABILITIES :: local_device_cl73_bam_abilities :: reserved0 [15:12] */ 11981 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BAM_ABILITIES_RESERVED0_MASK 0xf000 11982 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BAM_ABILITIES_RESERVED0_ALIGN 0 11983 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BAM_ABILITIES_RESERVED0_BITS 4 11984 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BAM_ABILITIES_RESERVED0_SHIFT 12 11985 11986 /* AN_X4_ABILITIES :: local_device_cl73_bam_abilities :: HPAM_20GKR2 [11:11] */ 11987 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BAM_ABILITIES_HPAM_20GKR2_MASK 0x0800 11988 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BAM_ABILITIES_HPAM_20GKR2_ALIGN 0 11989 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BAM_ABILITIES_HPAM_20GKR2_BITS 1 11990 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BAM_ABILITIES_HPAM_20GKR2_SHIFT 11 11991 11992 /* AN_X4_ABILITIES :: local_device_cl73_bam_abilities :: cl73_bam_code [10:02] */ 11993 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BAM_ABILITIES_CL73_BAM_CODE_MASK 0x07fc 11994 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BAM_ABILITIES_CL73_BAM_CODE_ALIGN 0 11995 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BAM_ABILITIES_CL73_BAM_CODE_BITS 9 11996 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BAM_ABILITIES_CL73_BAM_CODE_SHIFT 2 11997 11998 /* AN_X4_ABILITIES :: local_device_cl73_bam_abilities :: BAM_20GBASE_CR2 [01:01] */ 11999 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BAM_ABILITIES_BAM_20GBASE_CR2_MASK 0x0002 12000 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BAM_ABILITIES_BAM_20GBASE_CR2_ALIGN 0 12001 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BAM_ABILITIES_BAM_20GBASE_CR2_BITS 1 12002 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BAM_ABILITIES_BAM_20GBASE_CR2_SHIFT 1 12003 12004 /* AN_X4_ABILITIES :: local_device_cl73_bam_abilities :: BAM_20GBASE_KR2 [00:00] */ 12005 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BAM_ABILITIES_BAM_20GBASE_KR2_MASK 0x0001 12006 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BAM_ABILITIES_BAM_20GBASE_KR2_ALIGN 0 12007 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BAM_ABILITIES_BAM_20GBASE_KR2_BITS 1 12008 #define AN_X4_ABILITIES_LOCAL_DEVICE_CL73_BAM_ABILITIES_BAM_20GBASE_KR2_SHIFT 0 12009 12010 12011 /**************************************************************************** 12012 * AN_X4_ABILITIES :: controls 12013 */ 12014 /* AN_X4_ABILITIES :: controls :: OUI_CONTROL [15:10] */ 12015 #define AN_X4_ABILITIES_CONTROLS_OUI_CONTROL_MASK 0xfc00 12016 #define AN_X4_ABILITIES_CONTROLS_OUI_CONTROL_ALIGN 0 12017 #define AN_X4_ABILITIES_CONTROLS_OUI_CONTROL_BITS 6 12018 #define AN_X4_ABILITIES_CONTROLS_OUI_CONTROL_SHIFT 10 12019 12020 /* AN_X4_ABILITIES :: controls :: an_fail_count_limit [09:06] */ 12021 #define AN_X4_ABILITIES_CONTROLS_AN_FAIL_COUNT_LIMIT_MASK 0x03c0 12022 #define AN_X4_ABILITIES_CONTROLS_AN_FAIL_COUNT_LIMIT_ALIGN 0 12023 #define AN_X4_ABILITIES_CONTROLS_AN_FAIL_COUNT_LIMIT_BITS 4 12024 #define AN_X4_ABILITIES_CONTROLS_AN_FAIL_COUNT_LIMIT_SHIFT 6 12025 12026 /* AN_X4_ABILITIES :: controls :: linkFailTimerQual_en [05:05] */ 12027 #define AN_X4_ABILITIES_CONTROLS_LINKFAILTIMERQUAL_EN_MASK 0x0020 12028 #define AN_X4_ABILITIES_CONTROLS_LINKFAILTIMERQUAL_EN_ALIGN 0 12029 #define AN_X4_ABILITIES_CONTROLS_LINKFAILTIMERQUAL_EN_BITS 1 12030 #define AN_X4_ABILITIES_CONTROLS_LINKFAILTIMERQUAL_EN_SHIFT 5 12031 12032 /* AN_X4_ABILITIES :: controls :: linkFailTimer_dis [04:04] */ 12033 #define AN_X4_ABILITIES_CONTROLS_LINKFAILTIMER_DIS_MASK 0x0010 12034 #define AN_X4_ABILITIES_CONTROLS_LINKFAILTIMER_DIS_ALIGN 0 12035 #define AN_X4_ABILITIES_CONTROLS_LINKFAILTIMER_DIS_BITS 1 12036 #define AN_X4_ABILITIES_CONTROLS_LINKFAILTIMER_DIS_SHIFT 4 12037 12038 /* AN_X4_ABILITIES :: controls :: an_good_check_trap [03:03] */ 12039 #define AN_X4_ABILITIES_CONTROLS_AN_GOOD_CHECK_TRAP_MASK 0x0008 12040 #define AN_X4_ABILITIES_CONTROLS_AN_GOOD_CHECK_TRAP_ALIGN 0 12041 #define AN_X4_ABILITIES_CONTROLS_AN_GOOD_CHECK_TRAP_BITS 1 12042 #define AN_X4_ABILITIES_CONTROLS_AN_GOOD_CHECK_TRAP_SHIFT 3 12043 12044 /* AN_X4_ABILITIES :: controls :: an_good_trap [02:02] */ 12045 #define AN_X4_ABILITIES_CONTROLS_AN_GOOD_TRAP_MASK 0x0004 12046 #define AN_X4_ABILITIES_CONTROLS_AN_GOOD_TRAP_ALIGN 0 12047 #define AN_X4_ABILITIES_CONTROLS_AN_GOOD_TRAP_BITS 1 12048 #define AN_X4_ABILITIES_CONTROLS_AN_GOOD_TRAP_SHIFT 2 12049 12050 /* AN_X4_ABILITIES :: controls :: pd_KX_en [01:01] */ 12051 #define AN_X4_ABILITIES_CONTROLS_PD_KX_EN_MASK 0x0002 12052 #define AN_X4_ABILITIES_CONTROLS_PD_KX_EN_ALIGN 0 12053 #define AN_X4_ABILITIES_CONTROLS_PD_KX_EN_BITS 1 12054 #define AN_X4_ABILITIES_CONTROLS_PD_KX_EN_SHIFT 1 12055 12056 /* AN_X4_ABILITIES :: controls :: pd_KX4_en [00:00] */ 12057 #define AN_X4_ABILITIES_CONTROLS_PD_KX4_EN_MASK 0x0001 12058 #define AN_X4_ABILITIES_CONTROLS_PD_KX4_EN_ALIGN 0 12059 #define AN_X4_ABILITIES_CONTROLS_PD_KX4_EN_BITS 1 12060 #define AN_X4_ABILITIES_CONTROLS_PD_KX4_EN_SHIFT 0 12061 12062 12063 /**************************************************************************** 12064 * TSCE_TSCE_USER4_AN_X4_HW_LP_PAGES 12065 */ 12066 /**************************************************************************** 12067 * AN_X4_HW_LP_PAGES :: lp_mp5_up1 12068 */ 12069 /* AN_X4_HW_LP_PAGES :: lp_mp5_up1 :: lp_mp5_up1_page_data [15:00] */ 12070 #define AN_X4_HW_LP_PAGES_LP_MP5_UP1_LP_MP5_UP1_PAGE_DATA_MASK 0xffff 12071 #define AN_X4_HW_LP_PAGES_LP_MP5_UP1_LP_MP5_UP1_PAGE_DATA_ALIGN 0 12072 #define AN_X4_HW_LP_PAGES_LP_MP5_UP1_LP_MP5_UP1_PAGE_DATA_BITS 16 12073 #define AN_X4_HW_LP_PAGES_LP_MP5_UP1_LP_MP5_UP1_PAGE_DATA_SHIFT 0 12074 12075 12076 /**************************************************************************** 12077 * AN_X4_HW_LP_PAGES :: lp_mp5_up2 12078 */ 12079 /* AN_X4_HW_LP_PAGES :: lp_mp5_up2 :: lp_mp5_up2_page_data [15:00] */ 12080 #define AN_X4_HW_LP_PAGES_LP_MP5_UP2_LP_MP5_UP2_PAGE_DATA_MASK 0xffff 12081 #define AN_X4_HW_LP_PAGES_LP_MP5_UP2_LP_MP5_UP2_PAGE_DATA_ALIGN 0 12082 #define AN_X4_HW_LP_PAGES_LP_MP5_UP2_LP_MP5_UP2_PAGE_DATA_BITS 16 12083 #define AN_X4_HW_LP_PAGES_LP_MP5_UP2_LP_MP5_UP2_PAGE_DATA_SHIFT 0 12084 12085 12086 /**************************************************************************** 12087 * AN_X4_HW_LP_PAGES :: lp_mp5_up3 12088 */ 12089 /* AN_X4_HW_LP_PAGES :: lp_mp5_up3 :: lp_mp5_up3_page_data [15:00] */ 12090 #define AN_X4_HW_LP_PAGES_LP_MP5_UP3_LP_MP5_UP3_PAGE_DATA_MASK 0xffff 12091 #define AN_X4_HW_LP_PAGES_LP_MP5_UP3_LP_MP5_UP3_PAGE_DATA_ALIGN 0 12092 #define AN_X4_HW_LP_PAGES_LP_MP5_UP3_LP_MP5_UP3_PAGE_DATA_BITS 16 12093 #define AN_X4_HW_LP_PAGES_LP_MP5_UP3_LP_MP5_UP3_PAGE_DATA_SHIFT 0 12094 12095 12096 /**************************************************************************** 12097 * AN_X4_HW_LP_PAGES :: lp_mp5_up4 12098 */ 12099 /* AN_X4_HW_LP_PAGES :: lp_mp5_up4 :: lp_mp5_up4_page_data [15:00] */ 12100 #define AN_X4_HW_LP_PAGES_LP_MP5_UP4_LP_MP5_UP4_PAGE_DATA_MASK 0xffff 12101 #define AN_X4_HW_LP_PAGES_LP_MP5_UP4_LP_MP5_UP4_PAGE_DATA_ALIGN 0 12102 #define AN_X4_HW_LP_PAGES_LP_MP5_UP4_LP_MP5_UP4_PAGE_DATA_BITS 16 12103 #define AN_X4_HW_LP_PAGES_LP_MP5_UP4_LP_MP5_UP4_PAGE_DATA_SHIFT 0 12104 12105 12106 /**************************************************************************** 12107 * AN_X4_HW_LP_PAGES :: lp_mp1024_up1 12108 */ 12109 /* AN_X4_HW_LP_PAGES :: lp_mp1024_up1 :: lp_mp1024_up1_page_data [15:00] */ 12110 #define AN_X4_HW_LP_PAGES_LP_MP1024_UP1_LP_MP1024_UP1_PAGE_DATA_MASK 0xffff 12111 #define AN_X4_HW_LP_PAGES_LP_MP1024_UP1_LP_MP1024_UP1_PAGE_DATA_ALIGN 0 12112 #define AN_X4_HW_LP_PAGES_LP_MP1024_UP1_LP_MP1024_UP1_PAGE_DATA_BITS 16 12113 #define AN_X4_HW_LP_PAGES_LP_MP1024_UP1_LP_MP1024_UP1_PAGE_DATA_SHIFT 0 12114 12115 12116 /**************************************************************************** 12117 * AN_X4_HW_LP_PAGES :: lp_mp1024_up2 12118 */ 12119 /* AN_X4_HW_LP_PAGES :: lp_mp1024_up2 :: lp_mp1024_up2_page_data [15:00] */ 12120 #define AN_X4_HW_LP_PAGES_LP_MP1024_UP2_LP_MP1024_UP2_PAGE_DATA_MASK 0xffff 12121 #define AN_X4_HW_LP_PAGES_LP_MP1024_UP2_LP_MP1024_UP2_PAGE_DATA_ALIGN 0 12122 #define AN_X4_HW_LP_PAGES_LP_MP1024_UP2_LP_MP1024_UP2_PAGE_DATA_BITS 16 12123 #define AN_X4_HW_LP_PAGES_LP_MP1024_UP2_LP_MP1024_UP2_PAGE_DATA_SHIFT 0 12124 12125 12126 /**************************************************************************** 12127 * AN_X4_HW_LP_PAGES :: lp_mp1024_up3 12128 */ 12129 /* AN_X4_HW_LP_PAGES :: lp_mp1024_up3 :: lp_mp1024_up3_page_data [15:00] */ 12130 #define AN_X4_HW_LP_PAGES_LP_MP1024_UP3_LP_MP1024_UP3_PAGE_DATA_MASK 0xffff 12131 #define AN_X4_HW_LP_PAGES_LP_MP1024_UP3_LP_MP1024_UP3_PAGE_DATA_ALIGN 0 12132 #define AN_X4_HW_LP_PAGES_LP_MP1024_UP3_LP_MP1024_UP3_PAGE_DATA_BITS 16 12133 #define AN_X4_HW_LP_PAGES_LP_MP1024_UP3_LP_MP1024_UP3_PAGE_DATA_SHIFT 0 12134 12135 12136 /**************************************************************************** 12137 * AN_X4_HW_LP_PAGES :: lp_mp1024_up4 12138 */ 12139 /* AN_X4_HW_LP_PAGES :: lp_mp1024_up4 :: lp_mp1024_up4_page_data [15:00] */ 12140 #define AN_X4_HW_LP_PAGES_LP_MP1024_UP4_LP_MP1024_UP4_PAGE_DATA_MASK 0xffff 12141 #define AN_X4_HW_LP_PAGES_LP_MP1024_UP4_LP_MP1024_UP4_PAGE_DATA_ALIGN 0 12142 #define AN_X4_HW_LP_PAGES_LP_MP1024_UP4_LP_MP1024_UP4_PAGE_DATA_BITS 16 12143 #define AN_X4_HW_LP_PAGES_LP_MP1024_UP4_LP_MP1024_UP4_PAGE_DATA_SHIFT 0 12144 12145 12146 /**************************************************************************** 12147 * AN_X4_HW_LP_PAGES :: lp_base_page1 12148 */ 12149 /* AN_X4_HW_LP_PAGES :: lp_base_page1 :: lp_base_page1_page_data [15:00] */ 12150 #define AN_X4_HW_LP_PAGES_LP_BASE_PAGE1_LP_BASE_PAGE1_PAGE_DATA_MASK 0xffff 12151 #define AN_X4_HW_LP_PAGES_LP_BASE_PAGE1_LP_BASE_PAGE1_PAGE_DATA_ALIGN 0 12152 #define AN_X4_HW_LP_PAGES_LP_BASE_PAGE1_LP_BASE_PAGE1_PAGE_DATA_BITS 16 12153 #define AN_X4_HW_LP_PAGES_LP_BASE_PAGE1_LP_BASE_PAGE1_PAGE_DATA_SHIFT 0 12154 12155 12156 /**************************************************************************** 12157 * AN_X4_HW_LP_PAGES :: lp_base_page2 12158 */ 12159 /* AN_X4_HW_LP_PAGES :: lp_base_page2 :: lp_base_page2_page_data [15:00] */ 12160 #define AN_X4_HW_LP_PAGES_LP_BASE_PAGE2_LP_BASE_PAGE2_PAGE_DATA_MASK 0xffff 12161 #define AN_X4_HW_LP_PAGES_LP_BASE_PAGE2_LP_BASE_PAGE2_PAGE_DATA_ALIGN 0 12162 #define AN_X4_HW_LP_PAGES_LP_BASE_PAGE2_LP_BASE_PAGE2_PAGE_DATA_BITS 16 12163 #define AN_X4_HW_LP_PAGES_LP_BASE_PAGE2_LP_BASE_PAGE2_PAGE_DATA_SHIFT 0 12164 12165 12166 /**************************************************************************** 12167 * AN_X4_HW_LP_PAGES :: lp_base_page3 12168 */ 12169 /* AN_X4_HW_LP_PAGES :: lp_base_page3 :: lp_base_page3_page_data [15:00] */ 12170 #define AN_X4_HW_LP_PAGES_LP_BASE_PAGE3_LP_BASE_PAGE3_PAGE_DATA_MASK 0xffff 12171 #define AN_X4_HW_LP_PAGES_LP_BASE_PAGE3_LP_BASE_PAGE3_PAGE_DATA_ALIGN 0 12172 #define AN_X4_HW_LP_PAGES_LP_BASE_PAGE3_LP_BASE_PAGE3_PAGE_DATA_BITS 16 12173 #define AN_X4_HW_LP_PAGES_LP_BASE_PAGE3_LP_BASE_PAGE3_PAGE_DATA_SHIFT 0 12174 12175 12176 /**************************************************************************** 12177 * TSCE_TSCE_USER4_AN_X4_SW_MANAGEMENT 12178 */ 12179 /**************************************************************************** 12180 * AN_X4_SW_MANAGEMENT :: ld_page_2 12181 */ 12182 /* AN_X4_SW_MANAGEMENT :: ld_page_2 :: ld_page_2_page_data [15:00] */ 12183 #define AN_X4_SW_MANAGEMENT_LD_PAGE_2_LD_PAGE_2_PAGE_DATA_MASK 0xffff 12184 #define AN_X4_SW_MANAGEMENT_LD_PAGE_2_LD_PAGE_2_PAGE_DATA_ALIGN 0 12185 #define AN_X4_SW_MANAGEMENT_LD_PAGE_2_LD_PAGE_2_PAGE_DATA_BITS 16 12186 #define AN_X4_SW_MANAGEMENT_LD_PAGE_2_LD_PAGE_2_PAGE_DATA_SHIFT 0 12187 12188 12189 /**************************************************************************** 12190 * AN_X4_SW_MANAGEMENT :: ld_page_1 12191 */ 12192 /* AN_X4_SW_MANAGEMENT :: ld_page_1 :: ld_page_1_page_data [15:00] */ 12193 #define AN_X4_SW_MANAGEMENT_LD_PAGE_1_LD_PAGE_1_PAGE_DATA_MASK 0xffff 12194 #define AN_X4_SW_MANAGEMENT_LD_PAGE_1_LD_PAGE_1_PAGE_DATA_ALIGN 0 12195 #define AN_X4_SW_MANAGEMENT_LD_PAGE_1_LD_PAGE_1_PAGE_DATA_BITS 16 12196 #define AN_X4_SW_MANAGEMENT_LD_PAGE_1_LD_PAGE_1_PAGE_DATA_SHIFT 0 12197 12198 12199 /**************************************************************************** 12200 * AN_X4_SW_MANAGEMENT :: ld_page_0 12201 */ 12202 /* AN_X4_SW_MANAGEMENT :: ld_page_0 :: ld_page_0_page_data [15:00] */ 12203 #define AN_X4_SW_MANAGEMENT_LD_PAGE_0_LD_PAGE_0_PAGE_DATA_MASK 0xffff 12204 #define AN_X4_SW_MANAGEMENT_LD_PAGE_0_LD_PAGE_0_PAGE_DATA_ALIGN 0 12205 #define AN_X4_SW_MANAGEMENT_LD_PAGE_0_LD_PAGE_0_PAGE_DATA_BITS 16 12206 #define AN_X4_SW_MANAGEMENT_LD_PAGE_0_LD_PAGE_0_PAGE_DATA_SHIFT 0 12207 12208 12209 /**************************************************************************** 12210 * AN_X4_SW_MANAGEMENT :: lp_page_2 12211 */ 12212 /* AN_X4_SW_MANAGEMENT :: lp_page_2 :: lp_page_2_page_data [15:00] */ 12213 #define AN_X4_SW_MANAGEMENT_LP_PAGE_2_LP_PAGE_2_PAGE_DATA_MASK 0xffff 12214 #define AN_X4_SW_MANAGEMENT_LP_PAGE_2_LP_PAGE_2_PAGE_DATA_ALIGN 0 12215 #define AN_X4_SW_MANAGEMENT_LP_PAGE_2_LP_PAGE_2_PAGE_DATA_BITS 16 12216 #define AN_X4_SW_MANAGEMENT_LP_PAGE_2_LP_PAGE_2_PAGE_DATA_SHIFT 0 12217 12218 12219 /**************************************************************************** 12220 * AN_X4_SW_MANAGEMENT :: lp_page_1 12221 */ 12222 /* AN_X4_SW_MANAGEMENT :: lp_page_1 :: lp_page_1_page_data [15:00] */ 12223 #define AN_X4_SW_MANAGEMENT_LP_PAGE_1_LP_PAGE_1_PAGE_DATA_MASK 0xffff 12224 #define AN_X4_SW_MANAGEMENT_LP_PAGE_1_LP_PAGE_1_PAGE_DATA_ALIGN 0 12225 #define AN_X4_SW_MANAGEMENT_LP_PAGE_1_LP_PAGE_1_PAGE_DATA_BITS 16 12226 #define AN_X4_SW_MANAGEMENT_LP_PAGE_1_LP_PAGE_1_PAGE_DATA_SHIFT 0 12227 12228 12229 /**************************************************************************** 12230 * AN_X4_SW_MANAGEMENT :: lp_page_0 12231 */ 12232 /* AN_X4_SW_MANAGEMENT :: lp_page_0 :: lp_page_0_page_data [15:00] */ 12233 #define AN_X4_SW_MANAGEMENT_LP_PAGE_0_LP_PAGE_0_PAGE_DATA_MASK 0xffff 12234 #define AN_X4_SW_MANAGEMENT_LP_PAGE_0_LP_PAGE_0_PAGE_DATA_ALIGN 0 12235 #define AN_X4_SW_MANAGEMENT_LP_PAGE_0_LP_PAGE_0_PAGE_DATA_BITS 16 12236 #define AN_X4_SW_MANAGEMENT_LP_PAGE_0_LP_PAGE_0_PAGE_DATA_SHIFT 0 12237 12238 12239 /**************************************************************************** 12240 * AN_X4_SW_MANAGEMENT :: sw_control_status 12241 */ 12242 /* AN_X4_SW_MANAGEMENT :: sw_control_status :: an_completed_sw [15:15] */ 12243 #define AN_X4_SW_MANAGEMENT_SW_CONTROL_STATUS_AN_COMPLETED_SW_MASK 0x8000 12244 #define AN_X4_SW_MANAGEMENT_SW_CONTROL_STATUS_AN_COMPLETED_SW_ALIGN 0 12245 #define AN_X4_SW_MANAGEMENT_SW_CONTROL_STATUS_AN_COMPLETED_SW_BITS 1 12246 #define AN_X4_SW_MANAGEMENT_SW_CONTROL_STATUS_AN_COMPLETED_SW_SHIFT 15 12247 12248 /* AN_X4_SW_MANAGEMENT :: sw_control_status :: ld_control_valid [14:14] */ 12249 #define AN_X4_SW_MANAGEMENT_SW_CONTROL_STATUS_LD_CONTROL_VALID_MASK 0x4000 12250 #define AN_X4_SW_MANAGEMENT_SW_CONTROL_STATUS_LD_CONTROL_VALID_ALIGN 0 12251 #define AN_X4_SW_MANAGEMENT_SW_CONTROL_STATUS_LD_CONTROL_VALID_BITS 1 12252 #define AN_X4_SW_MANAGEMENT_SW_CONTROL_STATUS_LD_CONTROL_VALID_SHIFT 14 12253 12254 /* AN_X4_SW_MANAGEMENT :: sw_control_status :: lp_status_valid [13:13] */ 12255 #define AN_X4_SW_MANAGEMENT_SW_CONTROL_STATUS_LP_STATUS_VALID_MASK 0x2000 12256 #define AN_X4_SW_MANAGEMENT_SW_CONTROL_STATUS_LP_STATUS_VALID_ALIGN 0 12257 #define AN_X4_SW_MANAGEMENT_SW_CONTROL_STATUS_LP_STATUS_VALID_BITS 1 12258 #define AN_X4_SW_MANAGEMENT_SW_CONTROL_STATUS_LP_STATUS_VALID_SHIFT 13 12259 12260 /* AN_X4_SW_MANAGEMENT :: sw_control_status :: reserved0 [12:09] */ 12261 #define AN_X4_SW_MANAGEMENT_SW_CONTROL_STATUS_RESERVED0_MASK 0x1e00 12262 #define AN_X4_SW_MANAGEMENT_SW_CONTROL_STATUS_RESERVED0_ALIGN 0 12263 #define AN_X4_SW_MANAGEMENT_SW_CONTROL_STATUS_RESERVED0_BITS 4 12264 #define AN_X4_SW_MANAGEMENT_SW_CONTROL_STATUS_RESERVED0_SHIFT 9 12265 12266 /* AN_X4_SW_MANAGEMENT :: sw_control_status :: pd_cl37_completed [08:08] */ 12267 #define AN_X4_SW_MANAGEMENT_SW_CONTROL_STATUS_PD_CL37_COMPLETED_MASK 0x0100 12268 #define AN_X4_SW_MANAGEMENT_SW_CONTROL_STATUS_PD_CL37_COMPLETED_ALIGN 0 12269 #define AN_X4_SW_MANAGEMENT_SW_CONTROL_STATUS_PD_CL37_COMPLETED_BITS 1 12270 #define AN_X4_SW_MANAGEMENT_SW_CONTROL_STATUS_PD_CL37_COMPLETED_SHIFT 8 12271 12272 /* AN_X4_SW_MANAGEMENT :: sw_control_status :: tla_ln_sequencer_fsm_status1 [07:00] */ 12273 #define AN_X4_SW_MANAGEMENT_SW_CONTROL_STATUS_TLA_LN_SEQUENCER_FSM_STATUS1_MASK 0x00ff 12274 #define AN_X4_SW_MANAGEMENT_SW_CONTROL_STATUS_TLA_LN_SEQUENCER_FSM_STATUS1_ALIGN 0 12275 #define AN_X4_SW_MANAGEMENT_SW_CONTROL_STATUS_TLA_LN_SEQUENCER_FSM_STATUS1_BITS 8 12276 #define AN_X4_SW_MANAGEMENT_SW_CONTROL_STATUS_TLA_LN_SEQUENCER_FSM_STATUS1_SHIFT 0 12277 #define AN_X4_SW_MANAGEMENT_SW_CONTROL_STATUS_TLA_LN_SEQUENCER_FSM_STATUS1_SW_SPEED_CHANGE 64 12278 #define AN_X4_SW_MANAGEMENT_SW_CONTROL_STATUS_TLA_LN_SEQUENCER_FSM_STATUS1_RELEASE_SW 32 12279 #define AN_X4_SW_MANAGEMENT_SW_CONTROL_STATUS_TLA_LN_SEQUENCER_FSM_STATUS1_RELEASE_DISABLE 16 12280 #define AN_X4_SW_MANAGEMENT_SW_CONTROL_STATUS_TLA_LN_SEQUENCER_FSM_STATUS1_PD_WAIT_LINK 8 12281 #define AN_X4_SW_MANAGEMENT_SW_CONTROL_STATUS_TLA_LN_SEQUENCER_FSM_STATUS1_PD_START_CL37_AN 4 12282 #define AN_X4_SW_MANAGEMENT_SW_CONTROL_STATUS_TLA_LN_SEQUENCER_FSM_STATUS1_PD_WAIT_CL37_AN_DONE 2 12283 #define AN_X4_SW_MANAGEMENT_SW_CONTROL_STATUS_TLA_LN_SEQUENCER_FSM_STATUS1_PD_DONE_CL37 1 12284 12285 12286 /**************************************************************************** 12287 * AN_X4_SW_MANAGEMENT :: ld_control 12288 */ 12289 /* AN_X4_SW_MANAGEMENT :: ld_control :: reserved0 [15:02] */ 12290 #define AN_X4_SW_MANAGEMENT_LD_CONTROL_RESERVED0_MASK 0xfffc 12291 #define AN_X4_SW_MANAGEMENT_LD_CONTROL_RESERVED0_ALIGN 0 12292 #define AN_X4_SW_MANAGEMENT_LD_CONTROL_RESERVED0_BITS 14 12293 #define AN_X4_SW_MANAGEMENT_LD_CONTROL_RESERVED0_SHIFT 2 12294 12295 /* AN_X4_SW_MANAGEMENT :: ld_control :: SW_AN [01:01] */ 12296 #define AN_X4_SW_MANAGEMENT_LD_CONTROL_SW_AN_MASK 0x0002 12297 #define AN_X4_SW_MANAGEMENT_LD_CONTROL_SW_AN_ALIGN 0 12298 #define AN_X4_SW_MANAGEMENT_LD_CONTROL_SW_AN_BITS 1 12299 #define AN_X4_SW_MANAGEMENT_LD_CONTROL_SW_AN_SHIFT 1 12300 12301 /* AN_X4_SW_MANAGEMENT :: ld_control :: SW_HCD [00:00] */ 12302 #define AN_X4_SW_MANAGEMENT_LD_CONTROL_SW_HCD_MASK 0x0001 12303 #define AN_X4_SW_MANAGEMENT_LD_CONTROL_SW_HCD_ALIGN 0 12304 #define AN_X4_SW_MANAGEMENT_LD_CONTROL_SW_HCD_BITS 1 12305 #define AN_X4_SW_MANAGEMENT_LD_CONTROL_SW_HCD_SHIFT 0 12306 12307 12308 /**************************************************************************** 12309 * AN_X4_SW_MANAGEMENT :: an_page_sequencer_status 12310 */ 12311 /* AN_X4_SW_MANAGEMENT :: an_page_sequencer_status :: an_st_sgmii_mode [15:15] */ 12312 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_SGMII_MODE_MASK 0x8000 12313 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_SGMII_MODE_ALIGN 0 12314 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_SGMII_MODE_BITS 1 12315 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_SGMII_MODE_SHIFT 15 12316 12317 /* AN_X4_SW_MANAGEMENT :: an_page_sequencer_status :: an_st_hp_mode [14:14] */ 12318 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_HP_MODE_MASK 0x4000 12319 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_HP_MODE_ALIGN 0 12320 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_HP_MODE_BITS 1 12321 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_HP_MODE_SHIFT 14 12322 12323 /* AN_X4_SW_MANAGEMENT :: an_page_sequencer_status :: an_st_rx_sgmii_mismatch [13:13] */ 12324 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_SGMII_MISMATCH_MASK 0x2000 12325 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_SGMII_MISMATCH_ALIGN 0 12326 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_SGMII_MISMATCH_BITS 1 12327 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_SGMII_MISMATCH_SHIFT 13 12328 12329 /* AN_X4_SW_MANAGEMENT :: an_page_sequencer_status :: an_st_rx_bp [12:12] */ 12330 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_BP_MASK 0x1000 12331 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_BP_ALIGN 0 12332 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_BP_BITS 1 12333 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_BP_SHIFT 12 12334 12335 /* AN_X4_SW_MANAGEMENT :: an_page_sequencer_status :: an_st_rx_np [11:11] */ 12336 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_NP_MASK 0x0800 12337 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_NP_ALIGN 0 12338 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_NP_BITS 1 12339 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_NP_SHIFT 11 12340 12341 /* AN_X4_SW_MANAGEMENT :: an_page_sequencer_status :: an_st_rx_mp_null [10:10] */ 12342 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_MP_NULL_MASK 0x0400 12343 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_MP_NULL_ALIGN 0 12344 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_MP_NULL_BITS 1 12345 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_MP_NULL_SHIFT 10 12346 12347 /* AN_X4_SW_MANAGEMENT :: an_page_sequencer_status :: an_st_rx_mp_oui [09:09] */ 12348 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_MP_OUI_MASK 0x0200 12349 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_MP_OUI_ALIGN 0 12350 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_MP_OUI_BITS 1 12351 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_MP_OUI_SHIFT 9 12352 12353 /* AN_X4_SW_MANAGEMENT :: an_page_sequencer_status :: an_st_rx_mp_over1g [08:08] */ 12354 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_MP_OVER1G_MASK 0x0100 12355 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_MP_OVER1G_ALIGN 0 12356 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_MP_OVER1G_BITS 1 12357 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_MP_OVER1G_SHIFT 8 12358 12359 /* AN_X4_SW_MANAGEMENT :: an_page_sequencer_status :: an_st_rx_mp_mismatch [07:07] */ 12360 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_MP_MISMATCH_MASK 0x0080 12361 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_MP_MISMATCH_ALIGN 0 12362 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_MP_MISMATCH_BITS 1 12363 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_MP_MISMATCH_SHIFT 7 12364 12365 /* AN_X4_SW_MANAGEMENT :: an_page_sequencer_status :: an_st_rx_up_3 [06:06] */ 12366 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_UP_3_MASK 0x0040 12367 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_UP_3_ALIGN 0 12368 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_UP_3_BITS 1 12369 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_UP_3_SHIFT 6 12370 12371 /* AN_X4_SW_MANAGEMENT :: an_page_sequencer_status :: an_st_rx_up_oui_mismatch [05:05] */ 12372 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_UP_OUI_MISMATCH_MASK 0x0020 12373 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_UP_OUI_MISMATCH_ALIGN 0 12374 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_UP_OUI_MISMATCH_BITS 1 12375 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_UP_OUI_MISMATCH_SHIFT 5 12376 12377 /* AN_X4_SW_MANAGEMENT :: an_page_sequencer_status :: an_st_rx_up_oui_match [04:04] */ 12378 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_UP_OUI_MATCH_MASK 0x0010 12379 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_UP_OUI_MATCH_ALIGN 0 12380 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_UP_OUI_MATCH_BITS 1 12381 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_UP_OUI_MATCH_SHIFT 4 12382 12383 /* AN_X4_SW_MANAGEMENT :: an_page_sequencer_status :: an_st_rx_invalid_seq [03:03] */ 12384 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_INVALID_SEQ_MASK 0x0008 12385 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_INVALID_SEQ_ALIGN 0 12386 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_INVALID_SEQ_BITS 1 12387 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_INVALID_SEQ_SHIFT 3 12388 12389 /* AN_X4_SW_MANAGEMENT :: an_page_sequencer_status :: an_st_rx_np_toggle_err [02:02] */ 12390 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_NP_TOGGLE_ERR_MASK 0x0004 12391 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_NP_TOGGLE_ERR_ALIGN 0 12392 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_NP_TOGGLE_ERR_BITS 1 12393 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_RX_NP_TOGGLE_ERR_SHIFT 2 12394 12395 /* AN_X4_SW_MANAGEMENT :: an_page_sequencer_status :: an_st_cl37_complete [01:01] */ 12396 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_CL37_COMPLETE_MASK 0x0002 12397 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_CL37_COMPLETE_ALIGN 0 12398 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_CL37_COMPLETE_BITS 1 12399 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_CL37_COMPLETE_SHIFT 1 12400 12401 /* AN_X4_SW_MANAGEMENT :: an_page_sequencer_status :: an_st_cl73_complete [00:00] */ 12402 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_CL73_COMPLETE_MASK 0x0001 12403 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_CL73_COMPLETE_ALIGN 0 12404 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_CL73_COMPLETE_BITS 1 12405 #define AN_X4_SW_MANAGEMENT_AN_PAGE_SEQUENCER_STATUS_AN_ST_CL73_COMPLETE_SHIFT 0 12406 12407 12408 /**************************************************************************** 12409 * AN_X4_SW_MANAGEMENT :: an_page_exchangeer_status 12410 */ 12411 /* AN_X4_SW_MANAGEMENT :: an_page_exchangeer_status :: reserved0 [15:14] */ 12412 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_RESERVED0_MASK 0xc000 12413 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_RESERVED0_ALIGN 0 12414 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_RESERVED0_BITS 2 12415 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_RESERVED0_SHIFT 14 12416 12417 /* AN_X4_SW_MANAGEMENT :: an_page_exchangeer_status :: an_st_next_page_wait [13:13] */ 12418 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_NEXT_PAGE_WAIT_MASK 0x2000 12419 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_NEXT_PAGE_WAIT_ALIGN 0 12420 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_NEXT_PAGE_WAIT_BITS 1 12421 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_NEXT_PAGE_WAIT_SHIFT 13 12422 12423 /* AN_X4_SW_MANAGEMENT :: an_page_exchangeer_status :: an_st_link_ok [12:12] */ 12424 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_LINK_OK_MASK 0x1000 12425 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_LINK_OK_ALIGN 0 12426 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_LINK_OK_BITS 1 12427 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_LINK_OK_SHIFT 12 12428 12429 /* AN_X4_SW_MANAGEMENT :: an_page_exchangeer_status :: an_st_an_good_check [11:11] */ 12430 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_AN_GOOD_CHECK_MASK 0x0800 12431 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_AN_GOOD_CHECK_ALIGN 0 12432 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_AN_GOOD_CHECK_BITS 1 12433 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_AN_GOOD_CHECK_SHIFT 11 12434 12435 /* AN_X4_SW_MANAGEMENT :: an_page_exchangeer_status :: an_st_restart [10:10] */ 12436 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_RESTART_MASK 0x0400 12437 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_RESTART_ALIGN 0 12438 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_RESTART_BITS 1 12439 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_RESTART_SHIFT 10 12440 12441 /* AN_X4_SW_MANAGEMENT :: an_page_exchangeer_status :: an_st_config_nonzero [09:09] */ 12442 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_CONFIG_NONZERO_MASK 0x0200 12443 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_CONFIG_NONZERO_ALIGN 0 12444 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_CONFIG_NONZERO_BITS 1 12445 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_CONFIG_NONZERO_SHIFT 9 12446 12447 /* AN_X4_SW_MANAGEMENT :: an_page_exchangeer_status :: an_st_consistency_mismatch [08:08] */ 12448 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_CONSISTENCY_MISMATCH_MASK 0x0100 12449 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_CONSISTENCY_MISMATCH_ALIGN 0 12450 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_CONSISTENCY_MISMATCH_BITS 1 12451 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_CONSISTENCY_MISMATCH_SHIFT 8 12452 12453 /* AN_X4_SW_MANAGEMENT :: an_page_exchangeer_status :: an_st_complete_ack [07:07] */ 12454 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_COMPLETE_ACK_MASK 0x0080 12455 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_COMPLETE_ACK_ALIGN 0 12456 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_COMPLETE_ACK_BITS 1 12457 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_COMPLETE_ACK_SHIFT 7 12458 12459 /* AN_X4_SW_MANAGEMENT :: an_page_exchangeer_status :: an_st_ack_detect [06:06] */ 12460 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_ACK_DETECT_MASK 0x0040 12461 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_ACK_DETECT_ALIGN 0 12462 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_ACK_DETECT_BITS 1 12463 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_ACK_DETECT_SHIFT 6 12464 12465 /* AN_X4_SW_MANAGEMENT :: an_page_exchangeer_status :: an_st_ability_detect [05:05] */ 12466 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_ABILITY_DETECT_MASK 0x0020 12467 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_ABILITY_DETECT_ALIGN 0 12468 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_ABILITY_DETECT_BITS 1 12469 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_ABILITY_DETECT_SHIFT 5 12470 12471 /* AN_X4_SW_MANAGEMENT :: an_page_exchangeer_status :: an_st_an_enable [04:04] */ 12472 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_AN_ENABLE_MASK 0x0010 12473 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_AN_ENABLE_ALIGN 0 12474 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_AN_ENABLE_BITS 1 12475 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_AN_ENABLE_SHIFT 4 12476 12477 /* AN_X4_SW_MANAGEMENT :: an_page_exchangeer_status :: an_st_error_state [03:03] */ 12478 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_ERROR_STATE_MASK 0x0008 12479 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_ERROR_STATE_ALIGN 0 12480 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_ERROR_STATE_BITS 1 12481 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_ERROR_STATE_SHIFT 3 12482 12483 /* AN_X4_SW_MANAGEMENT :: an_page_exchangeer_status :: an_st_disable_link [02:02] */ 12484 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_DISABLE_LINK_MASK 0x0004 12485 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_DISABLE_LINK_ALIGN 0 12486 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_DISABLE_LINK_BITS 1 12487 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_DISABLE_LINK_SHIFT 2 12488 12489 /* AN_X4_SW_MANAGEMENT :: an_page_exchangeer_status :: an_st_idle_detect [01:01] */ 12490 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_IDLE_DETECT_MASK 0x0002 12491 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_IDLE_DETECT_ALIGN 0 12492 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_IDLE_DETECT_BITS 1 12493 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_IDLE_DETECT_SHIFT 1 12494 12495 /* AN_X4_SW_MANAGEMENT :: an_page_exchangeer_status :: an_st_config_restart [00:00] */ 12496 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_CONFIG_RESTART_MASK 0x0001 12497 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_CONFIG_RESTART_ALIGN 0 12498 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_CONFIG_RESTART_BITS 1 12499 #define AN_X4_SW_MANAGEMENT_AN_PAGE_EXCHANGEER_STATUS_AN_ST_CONFIG_RESTART_SHIFT 0 12500 12501 12502 /**************************************************************************** 12503 * AN_X4_SW_MANAGEMENT :: an_page_decoder_status 12504 */ 12505 /* AN_X4_SW_MANAGEMENT :: an_page_decoder_status :: reserved0 [15:13] */ 12506 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_RESERVED0_MASK 0xe000 12507 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_RESERVED0_ALIGN 0 12508 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_RESERVED0_BITS 3 12509 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_RESERVED0_SHIFT 13 12510 12511 /* AN_X4_SW_MANAGEMENT :: an_page_decoder_status :: an_rx_st_pulse_too_moderate [12:12] */ 12512 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_PULSE_TOO_MODERATE_MASK 0x1000 12513 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_PULSE_TOO_MODERATE_ALIGN 0 12514 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_PULSE_TOO_MODERATE_BITS 1 12515 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_PULSE_TOO_MODERATE_SHIFT 12 12516 12517 /* AN_X4_SW_MANAGEMENT :: an_page_decoder_status :: an_rx_st_pulse_too_short [11:11] */ 12518 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_PULSE_TOO_SHORT_MASK 0x0800 12519 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_PULSE_TOO_SHORT_ALIGN 0 12520 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_PULSE_TOO_SHORT_BITS 1 12521 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_PULSE_TOO_SHORT_SHIFT 11 12522 12523 /* AN_X4_SW_MANAGEMENT :: an_page_decoder_status :: an_rx_st_pulse_too_long [10:10] */ 12524 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_PULSE_TOO_LONG_MASK 0x0400 12525 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_PULSE_TOO_LONG_ALIGN 0 12526 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_PULSE_TOO_LONG_BITS 1 12527 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_PULSE_TOO_LONG_SHIFT 10 12528 12529 /* AN_X4_SW_MANAGEMENT :: an_page_decoder_status :: an_rx_st_page_too_short [09:09] */ 12530 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_PAGE_TOO_SHORT_MASK 0x0200 12531 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_PAGE_TOO_SHORT_ALIGN 0 12532 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_PAGE_TOO_SHORT_BITS 1 12533 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_PAGE_TOO_SHORT_SHIFT 9 12534 12535 /* AN_X4_SW_MANAGEMENT :: an_page_decoder_status :: an_rx_st_page_too_long [08:08] */ 12536 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_PAGE_TOO_LONG_MASK 0x0100 12537 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_PAGE_TOO_LONG_ALIGN 0 12538 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_PAGE_TOO_LONG_BITS 1 12539 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_PAGE_TOO_LONG_SHIFT 8 12540 12541 /* AN_X4_SW_MANAGEMENT :: an_page_decoder_status :: an_rx_st_clk_trans_miss [07:07] */ 12542 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_CLK_TRANS_MISS_MASK 0x0080 12543 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_CLK_TRANS_MISS_ALIGN 0 12544 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_CLK_TRANS_MISS_BITS 1 12545 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_CLK_TRANS_MISS_SHIFT 7 12546 12547 /* AN_X4_SW_MANAGEMENT :: an_page_decoder_status :: an_rx_st_mv_pair [06:06] */ 12548 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_MV_PAIR_MASK 0x0040 12549 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_MV_PAIR_ALIGN 0 12550 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_MV_PAIR_BITS 1 12551 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_MV_PAIR_SHIFT 6 12552 12553 /* AN_X4_SW_MANAGEMENT :: an_page_decoder_status :: an_rx_st_page [05:05] */ 12554 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_PAGE_MASK 0x0020 12555 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_PAGE_ALIGN 0 12556 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_PAGE_BITS 1 12557 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_PAGE_SHIFT 5 12558 12559 /* AN_X4_SW_MANAGEMENT :: an_page_decoder_status :: an_rx_st_rudi_idle [04:04] */ 12560 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_RUDI_IDLE_MASK 0x0010 12561 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_RUDI_IDLE_ALIGN 0 12562 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_RUDI_IDLE_BITS 1 12563 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_RUDI_IDLE_SHIFT 4 12564 12565 /* AN_X4_SW_MANAGEMENT :: an_page_decoder_status :: an_rx_st_rudi_config [03:03] */ 12566 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_RUDI_CONFIG_MASK 0x0008 12567 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_RUDI_CONFIG_ALIGN 0 12568 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_RUDI_CONFIG_BITS 1 12569 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_RUDI_CONFIG_SHIFT 3 12570 12571 /* AN_X4_SW_MANAGEMENT :: an_page_decoder_status :: an_rx_st_rudi_invalid [02:02] */ 12572 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_RUDI_INVALID_MASK 0x0004 12573 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_RUDI_INVALID_ALIGN 0 12574 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_RUDI_INVALID_BITS 1 12575 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_RUDI_INVALID_SHIFT 2 12576 12577 /* AN_X4_SW_MANAGEMENT :: an_page_decoder_status :: an_rx_st_state [01:00] */ 12578 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_STATE_MASK 0x0003 12579 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_STATE_ALIGN 0 12580 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_STATE_BITS 2 12581 #define AN_X4_SW_MANAGEMENT_AN_PAGE_DECODER_STATUS_AN_RX_ST_STATE_SHIFT 0 12582 12583 12584 /**************************************************************************** 12585 * AN_X4_SW_MANAGEMENT :: an_ability_resolution_status 12586 */ 12587 /* AN_X4_SW_MANAGEMENT :: an_ability_resolution_status :: an_st_resolution_err [15:15] */ 12588 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_ST_RESOLUTION_ERR_MASK 0x8000 12589 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_ST_RESOLUTION_ERR_ALIGN 0 12590 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_ST_RESOLUTION_ERR_BITS 1 12591 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_ST_RESOLUTION_ERR_SHIFT 15 12592 12593 /* AN_X4_SW_MANAGEMENT :: an_ability_resolution_status :: an_hcd_duplex [14:14] */ 12594 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_DUPLEX_MASK 0x4000 12595 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_DUPLEX_ALIGN 0 12596 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_DUPLEX_BITS 1 12597 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_DUPLEX_SHIFT 14 12598 12599 /* AN_X4_SW_MANAGEMENT :: an_ability_resolution_status :: an_hcd_pause [13:12] */ 12600 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_PAUSE_MASK 0x3000 12601 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_PAUSE_ALIGN 0 12602 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_PAUSE_BITS 2 12603 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_PAUSE_SHIFT 12 12604 12605 /* AN_X4_SW_MANAGEMENT :: an_ability_resolution_status :: an_hcd_speed [11:04] */ 12606 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_MASK 0x0ff0 12607 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_ALIGN 0 12608 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_BITS 8 12609 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_SHIFT 4 12610 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_SPEED_2p5G_X1_10p3125 56 12611 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_SPEED_1000M_10p3125 55 12612 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_SPEED_100M_10p3125 54 12613 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_SPEED_10M_10p3125 53 12614 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_SPEED_10p5G_X4 50 12615 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_SPEED_5G_KR1 49 12616 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_SPEED_127G_X12 39 12617 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_SPEED_120G_X12 38 12618 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_SPEED_107G_X10 37 12619 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_SPEED_100G_CR10 36 12620 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_SPEED_42G_X4 35 12621 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_SPEED_40G_CR4 34 12622 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_SPEED_40G_KR4 33 12623 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_SPEED_21G_X2 32 12624 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_SPEED_20G_CR2 31 12625 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_SPEED_20G_KR2 30 12626 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_SPEED_10p6_X1 29 12627 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_SPEED_10G_KR1 28 12628 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_SPEED_40G_X4 27 12629 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_SPEED_20G_X2 26 12630 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_SPEED_20G_CX2 25 12631 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_SPEED_31p5G_KR4 24 12632 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_SPEED_31p5G_X4 23 12633 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_SPEED_15p75G_X2 22 12634 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_SPEED_25p45G_X4 21 12635 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_SPEED_12p7G_X2 20 12636 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_SPEED_21G_X4 19 12637 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_SPEED_10p5G_X2 18 12638 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_SPEED_20G_X4 17 12639 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_SPEED_10G_X2 16 12640 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_SPEED_10G_CX2 15 12641 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_SPEED_20G_CX4 14 12642 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_SPEED_16G_X4 13 12643 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_SPEED_15G_X4 12 12644 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_SPEED_13G_X4 11 12645 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_SPEED_10G_X4 10 12646 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_SPEED_10G_KX4 9 12647 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_SPEED_10G_CX4 8 12648 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_SPEED_5G_X1 7 12649 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_SPEED_2p5G_X1 6 12650 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_SPEED_1G_KX1 5 12651 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_SPEED_1G_CX1 4 12652 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_SPEED_1000M 3 12653 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_SPEED_100M 2 12654 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_SPEED_10M 1 12655 12656 /* AN_X4_SW_MANAGEMENT :: an_ability_resolution_status :: an_hcd_fec [03:03] */ 12657 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_FEC_MASK 0x0008 12658 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_FEC_ALIGN 0 12659 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_FEC_BITS 1 12660 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_FEC_SHIFT 3 12661 12662 /* AN_X4_SW_MANAGEMENT :: an_ability_resolution_status :: an_hcd_cl72 [02:02] */ 12663 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_CL72_MASK 0x0004 12664 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_CL72_ALIGN 0 12665 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_CL72_BITS 1 12666 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_CL72_SHIFT 2 12667 12668 /* AN_X4_SW_MANAGEMENT :: an_ability_resolution_status :: an_hcd_higig2 [01:01] */ 12669 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_HIGIG2_MASK 0x0002 12670 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_HIGIG2_ALIGN 0 12671 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_HIGIG2_BITS 1 12672 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_HIGIG2_SHIFT 1 12673 12674 /* AN_X4_SW_MANAGEMENT :: an_ability_resolution_status :: an_hcd_switch_to_cl37 [00:00] */ 12675 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SWITCH_TO_CL37_MASK 0x0001 12676 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SWITCH_TO_CL37_ALIGN 0 12677 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SWITCH_TO_CL37_BITS 1 12678 #define AN_X4_SW_MANAGEMENT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SWITCH_TO_CL37_SHIFT 0 12679 12680 12681 /**************************************************************************** 12682 * AN_X4_SW_MANAGEMENT :: an_misc_status 12683 */ 12684 /* AN_X4_SW_MANAGEMENT :: an_misc_status :: an_complete [15:15] */ 12685 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_AN_COMPLETE_MASK 0x8000 12686 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_AN_COMPLETE_ALIGN 0 12687 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_AN_COMPLETE_BITS 1 12688 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_AN_COMPLETE_SHIFT 15 12689 12690 /* AN_X4_SW_MANAGEMENT :: an_misc_status :: an_retry_count [14:09] */ 12691 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_AN_RETRY_COUNT_MASK 0x7e00 12692 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_AN_RETRY_COUNT_ALIGN 0 12693 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_AN_RETRY_COUNT_BITS 6 12694 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_AN_RETRY_COUNT_SHIFT 9 12695 12696 /* AN_X4_SW_MANAGEMENT :: an_misc_status :: remote_fault_in_base_page [08:08] */ 12697 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_REMOTE_FAULT_IN_BASE_PAGE_MASK 0x0100 12698 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_REMOTE_FAULT_IN_BASE_PAGE_ALIGN 0 12699 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_REMOTE_FAULT_IN_BASE_PAGE_BITS 1 12700 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_REMOTE_FAULT_IN_BASE_PAGE_SHIFT 8 12701 12702 /* AN_X4_SW_MANAGEMENT :: an_misc_status :: pd_completed [07:07] */ 12703 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_PD_COMPLETED_MASK 0x0080 12704 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_PD_COMPLETED_ALIGN 0 12705 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_PD_COMPLETED_BITS 1 12706 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_PD_COMPLETED_SHIFT 7 12707 12708 /* AN_X4_SW_MANAGEMENT :: an_misc_status :: an_active [06:06] */ 12709 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_AN_ACTIVE_MASK 0x0040 12710 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_AN_ACTIVE_ALIGN 0 12711 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_AN_ACTIVE_BITS 1 12712 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_AN_ACTIVE_SHIFT 6 12713 12714 /* AN_X4_SW_MANAGEMENT :: an_misc_status :: an_fail_count [05:02] */ 12715 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_AN_FAIL_COUNT_MASK 0x003c 12716 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_AN_FAIL_COUNT_ALIGN 0 12717 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_AN_FAIL_COUNT_BITS 4 12718 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_AN_FAIL_COUNT_SHIFT 2 12719 12720 /* AN_X4_SW_MANAGEMENT :: an_misc_status :: pd_in_progress [01:01] */ 12721 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_PD_IN_PROGRESS_MASK 0x0002 12722 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_PD_IN_PROGRESS_ALIGN 0 12723 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_PD_IN_PROGRESS_BITS 1 12724 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_PD_IN_PROGRESS_SHIFT 1 12725 12726 /* AN_X4_SW_MANAGEMENT :: an_misc_status :: pd_hcd_kx4_or_kx [00:00] */ 12727 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_PD_HCD_KX4_OR_KX_MASK 0x0001 12728 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_PD_HCD_KX4_OR_KX_ALIGN 0 12729 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_PD_HCD_KX4_OR_KX_BITS 1 12730 #define AN_X4_SW_MANAGEMENT_AN_MISC_STATUS_PD_HCD_KX4_OR_KX_SHIFT 0 12731 12732 12733 /**************************************************************************** 12734 * AN_X4_SW_MANAGEMENT :: tla_sequencer_status 12735 */ 12736 /* AN_X4_SW_MANAGEMENT :: tla_sequencer_status :: tla_ln_sequencer_fsm_status [15:00] */ 12737 #define AN_X4_SW_MANAGEMENT_TLA_SEQUENCER_STATUS_TLA_LN_SEQUENCER_FSM_STATUS_MASK 0xffff 12738 #define AN_X4_SW_MANAGEMENT_TLA_SEQUENCER_STATUS_TLA_LN_SEQUENCER_FSM_STATUS_ALIGN 0 12739 #define AN_X4_SW_MANAGEMENT_TLA_SEQUENCER_STATUS_TLA_LN_SEQUENCER_FSM_STATUS_BITS 16 12740 #define AN_X4_SW_MANAGEMENT_TLA_SEQUENCER_STATUS_TLA_LN_SEQUENCER_FSM_STATUS_SHIFT 0 12741 #define AN_X4_SW_MANAGEMENT_TLA_SEQUENCER_STATUS_TLA_LN_SEQUENCER_FSM_STATUS_INIT 1 12742 #define AN_X4_SW_MANAGEMENT_TLA_SEQUENCER_STATUS_TLA_LN_SEQUENCER_FSM_STATUS_SET_AN_SPEED 2 12743 #define AN_X4_SW_MANAGEMENT_TLA_SEQUENCER_STATUS_TLA_LN_SEQUENCER_FSM_STATUS_WAIT_AN_SPEED 4 12744 #define AN_X4_SW_MANAGEMENT_TLA_SEQUENCER_STATUS_TLA_LN_SEQUENCER_FSM_STATUS_WAIT_AN_DONE 8 12745 #define AN_X4_SW_MANAGEMENT_TLA_SEQUENCER_STATUS_TLA_LN_SEQUENCER_FSM_STATUS_SET_RS_SPEED 16 12746 #define AN_X4_SW_MANAGEMENT_TLA_SEQUENCER_STATUS_TLA_LN_SEQUENCER_FSM_STATUS_WAIT_RS_CL72EN 32 12747 #define AN_X4_SW_MANAGEMENT_TLA_SEQUENCER_STATUS_TLA_LN_SEQUENCER_FSM_STATUS_WAIT_RS_SPEED 64 12748 #define AN_X4_SW_MANAGEMENT_TLA_SEQUENCER_STATUS_TLA_LN_SEQUENCER_FSM_STATUS_AN_IGNORE_LINK 128 12749 #define AN_X4_SW_MANAGEMENT_TLA_SEQUENCER_STATUS_TLA_LN_SEQUENCER_FSM_STATUS_AN_GOOD_CHECK 256 12750 #define AN_X4_SW_MANAGEMENT_TLA_SEQUENCER_STATUS_TLA_LN_SEQUENCER_FSM_STATUS_AN_GOOD 512 12751 #define AN_X4_SW_MANAGEMENT_TLA_SEQUENCER_STATUS_TLA_LN_SEQUENCER_FSM_STATUS_AN_FAIL 1024 12752 #define AN_X4_SW_MANAGEMENT_TLA_SEQUENCER_STATUS_TLA_LN_SEQUENCER_FSM_STATUS_AN_DEAD 2048 12753 #define AN_X4_SW_MANAGEMENT_TLA_SEQUENCER_STATUS_TLA_LN_SEQUENCER_FSM_STATUS_SET_PD_SPEED 4096 12754 #define AN_X4_SW_MANAGEMENT_TLA_SEQUENCER_STATUS_TLA_LN_SEQUENCER_FSM_STATUS_WAIT_PD_SPEED 8192 12755 #define AN_X4_SW_MANAGEMENT_TLA_SEQUENCER_STATUS_TLA_LN_SEQUENCER_FSM_STATUS_PD_IGNORE_LINK 16384 12756 #define AN_X4_SW_MANAGEMENT_TLA_SEQUENCER_STATUS_TLA_LN_SEQUENCER_FSM_STATUS_PD_GOOD_CHECK 32768 12757 12758 12759 /**************************************************************************** 12760 * AN_X4_SW_MANAGEMENT :: an_seq_unexpected_page 12761 */ 12762 /* AN_X4_SW_MANAGEMENT :: an_seq_unexpected_page :: seq_unexpected_page [15:00] */ 12763 #define AN_X4_SW_MANAGEMENT_AN_SEQ_UNEXPECTED_PAGE_SEQ_UNEXPECTED_PAGE_MASK 0xffff 12764 #define AN_X4_SW_MANAGEMENT_AN_SEQ_UNEXPECTED_PAGE_SEQ_UNEXPECTED_PAGE_ALIGN 0 12765 #define AN_X4_SW_MANAGEMENT_AN_SEQ_UNEXPECTED_PAGE_SEQ_UNEXPECTED_PAGE_BITS 16 12766 #define AN_X4_SW_MANAGEMENT_AN_SEQ_UNEXPECTED_PAGE_SEQ_UNEXPECTED_PAGE_SHIFT 0 12767 12768 12769 /**************************************************************************** 12770 * TSCE_TSCE_USER4_CL72 12771 */ 12772 /**************************************************************************** 12773 * CL72 :: link_control 12774 */ 12775 /* CL72 :: link_control :: reserved0 [15:15] */ 12776 #define CL72_LINK_CONTROL_RESERVED0_MASK 0x8000 12777 #define CL72_LINK_CONTROL_RESERVED0_ALIGN 0 12778 #define CL72_LINK_CONTROL_RESERVED0_BITS 1 12779 #define CL72_LINK_CONTROL_RESERVED0_SHIFT 15 12780 12781 /* CL72 :: link_control :: link_control_forceval [14:14] */ 12782 #define CL72_LINK_CONTROL_LINK_CONTROL_FORCEVAL_MASK 0x4000 12783 #define CL72_LINK_CONTROL_LINK_CONTROL_FORCEVAL_ALIGN 0 12784 #define CL72_LINK_CONTROL_LINK_CONTROL_FORCEVAL_BITS 1 12785 #define CL72_LINK_CONTROL_LINK_CONTROL_FORCEVAL_SHIFT 14 12786 12787 /* CL72 :: link_control :: reserved1 [13:00] */ 12788 #define CL72_LINK_CONTROL_RESERVED1_MASK 0x3fff 12789 #define CL72_LINK_CONTROL_RESERVED1_ALIGN 0 12790 #define CL72_LINK_CONTROL_RESERVED1_BITS 14 12791 #define CL72_LINK_CONTROL_RESERVED1_SHIFT 0 12792 12793 12794 /**************************************************************************** 12795 * TSCE_TSCE_USER4_Digital 12796 */ 12797 /**************************************************************************** 12798 * Digital :: Control1000X2 12799 */ 12800 /* Digital :: Control1000X2 :: reserved0 [15:05] */ 12801 #define DIGITAL_CONTROL1000X2_RESERVED0_MASK 0xffe0 12802 #define DIGITAL_CONTROL1000X2_RESERVED0_ALIGN 0 12803 #define DIGITAL_CONTROL1000X2_RESERVED0_BITS 11 12804 #define DIGITAL_CONTROL1000X2_RESERVED0_SHIFT 5 12805 12806 /* Digital :: Control1000X2 :: disable_remote_fault_reporting [04:04] */ 12807 #define DIGITAL_CONTROL1000X2_DISABLE_REMOTE_FAULT_REPORTING_MASK 0x0010 12808 #define DIGITAL_CONTROL1000X2_DISABLE_REMOTE_FAULT_REPORTING_ALIGN 0 12809 #define DIGITAL_CONTROL1000X2_DISABLE_REMOTE_FAULT_REPORTING_BITS 1 12810 #define DIGITAL_CONTROL1000X2_DISABLE_REMOTE_FAULT_REPORTING_SHIFT 4 12811 12812 /* Digital :: Control1000X2 :: reserved1 [03:00] */ 12813 #define DIGITAL_CONTROL1000X2_RESERVED1_MASK 0x000f 12814 #define DIGITAL_CONTROL1000X2_RESERVED1_ALIGN 0 12815 #define DIGITAL_CONTROL1000X2_RESERVED1_BITS 4 12816 #define DIGITAL_CONTROL1000X2_RESERVED1_SHIFT 0 12817 12818 12819 /**************************************************************************** 12820 * Digital :: spare0 12821 */ 12822 /* Digital :: spare0 :: reserved0 [15:08] */ 12823 #define DIGITAL_SPARE0_RESERVED0_MASK 0xff00 12824 #define DIGITAL_SPARE0_RESERVED0_ALIGN 0 12825 #define DIGITAL_SPARE0_RESERVED0_BITS 8 12826 #define DIGITAL_SPARE0_RESERVED0_SHIFT 8 12827 12828 /* Digital :: spare0 :: spare0 [07:00] */ 12829 #define DIGITAL_SPARE0_SPARE0_MASK 0x00ff 12830 #define DIGITAL_SPARE0_SPARE0_ALIGN 0 12831 #define DIGITAL_SPARE0_SPARE0_BITS 8 12832 #define DIGITAL_SPARE0_SPARE0_SHIFT 0 12833 12834 12835 /**************************************************************************** 12836 * Digital :: spare1 12837 */ 12838 /* Digital :: spare1 :: reserved0 [15:08] */ 12839 #define DIGITAL_SPARE1_RESERVED0_MASK 0xff00 12840 #define DIGITAL_SPARE1_RESERVED0_ALIGN 0 12841 #define DIGITAL_SPARE1_RESERVED0_BITS 8 12842 #define DIGITAL_SPARE1_RESERVED0_SHIFT 8 12843 12844 /* Digital :: spare1 :: spare1 [07:00] */ 12845 #define DIGITAL_SPARE1_SPARE1_MASK 0x00ff 12846 #define DIGITAL_SPARE1_SPARE1_ALIGN 0 12847 #define DIGITAL_SPARE1_SPARE1_BITS 8 12848 #define DIGITAL_SPARE1_SPARE1_SHIFT 0 12849 12850 12851 /**************************************************************************** 12852 * TSCE_TSCE_USER4_ilkn_control0 12853 */ 12854 /**************************************************************************** 12855 * ilkn_control0 :: ilkn_control0 12856 */ 12857 /* ilkn_control0 :: ilkn_control0 :: credit_en [15:15] */ 12858 #define ILKN_CONTROL0_ILKN_CONTROL0_CREDIT_EN_MASK 0x8000 12859 #define ILKN_CONTROL0_ILKN_CONTROL0_CREDIT_EN_ALIGN 0 12860 #define ILKN_CONTROL0_ILKN_CONTROL0_CREDIT_EN_BITS 1 12861 #define ILKN_CONTROL0_ILKN_CONTROL0_CREDIT_EN_SHIFT 15 12862 12863 /* ilkn_control0 :: ilkn_control0 :: reserved0 [14:10] */ 12864 #define ILKN_CONTROL0_ILKN_CONTROL0_RESERVED0_MASK 0x7c00 12865 #define ILKN_CONTROL0_ILKN_CONTROL0_RESERVED0_ALIGN 0 12866 #define ILKN_CONTROL0_ILKN_CONTROL0_RESERVED0_BITS 5 12867 #define ILKN_CONTROL0_ILKN_CONTROL0_RESERVED0_SHIFT 10 12868 12869 /* ilkn_control0 :: ilkn_control0 :: soft_rst_rx [09:09] */ 12870 #define ILKN_CONTROL0_ILKN_CONTROL0_SOFT_RST_RX_MASK 0x0200 12871 #define ILKN_CONTROL0_ILKN_CONTROL0_SOFT_RST_RX_ALIGN 0 12872 #define ILKN_CONTROL0_ILKN_CONTROL0_SOFT_RST_RX_BITS 1 12873 #define ILKN_CONTROL0_ILKN_CONTROL0_SOFT_RST_RX_SHIFT 9 12874 12875 /* ilkn_control0 :: ilkn_control0 :: soft_rst_tx [08:08] */ 12876 #define ILKN_CONTROL0_ILKN_CONTROL0_SOFT_RST_TX_MASK 0x0100 12877 #define ILKN_CONTROL0_ILKN_CONTROL0_SOFT_RST_TX_ALIGN 0 12878 #define ILKN_CONTROL0_ILKN_CONTROL0_SOFT_RST_TX_BITS 1 12879 #define ILKN_CONTROL0_ILKN_CONTROL0_SOFT_RST_TX_SHIFT 8 12880 12881 /* ilkn_control0 :: ilkn_control0 :: inv_rx_order [07:07] */ 12882 #define ILKN_CONTROL0_ILKN_CONTROL0_INV_RX_ORDER_MASK 0x0080 12883 #define ILKN_CONTROL0_ILKN_CONTROL0_INV_RX_ORDER_ALIGN 0 12884 #define ILKN_CONTROL0_ILKN_CONTROL0_INV_RX_ORDER_BITS 1 12885 #define ILKN_CONTROL0_ILKN_CONTROL0_INV_RX_ORDER_SHIFT 7 12886 12887 /* ilkn_control0 :: ilkn_control0 :: inv_tx_order [06:06] */ 12888 #define ILKN_CONTROL0_ILKN_CONTROL0_INV_TX_ORDER_MASK 0x0040 12889 #define ILKN_CONTROL0_ILKN_CONTROL0_INV_TX_ORDER_ALIGN 0 12890 #define ILKN_CONTROL0_ILKN_CONTROL0_INV_TX_ORDER_BITS 1 12891 #define ILKN_CONTROL0_ILKN_CONTROL0_INV_TX_ORDER_SHIFT 6 12892 12893 /* ilkn_control0 :: ilkn_control0 :: reserved1 [05:04] */ 12894 #define ILKN_CONTROL0_ILKN_CONTROL0_RESERVED1_MASK 0x0030 12895 #define ILKN_CONTROL0_ILKN_CONTROL0_RESERVED1_ALIGN 0 12896 #define ILKN_CONTROL0_ILKN_CONTROL0_RESERVED1_BITS 2 12897 #define ILKN_CONTROL0_ILKN_CONTROL0_RESERVED1_SHIFT 4 12898 12899 /* ilkn_control0 :: ilkn_control0 :: ilkn_sel [03:03] */ 12900 #define ILKN_CONTROL0_ILKN_CONTROL0_ILKN_SEL_MASK 0x0008 12901 #define ILKN_CONTROL0_ILKN_CONTROL0_ILKN_SEL_ALIGN 0 12902 #define ILKN_CONTROL0_ILKN_CONTROL0_ILKN_SEL_BITS 1 12903 #define ILKN_CONTROL0_ILKN_CONTROL0_ILKN_SEL_SHIFT 3 12904 12905 /* ilkn_control0 :: ilkn_control0 :: wm [02:00] */ 12906 #define ILKN_CONTROL0_ILKN_CONTROL0_WM_MASK 0x0007 12907 #define ILKN_CONTROL0_ILKN_CONTROL0_WM_ALIGN 0 12908 #define ILKN_CONTROL0_ILKN_CONTROL0_WM_BITS 3 12909 #define ILKN_CONTROL0_ILKN_CONTROL0_WM_SHIFT 0 12910 12911 12912 /**************************************************************************** 12913 * TSCE_TSCE_USER4_ilkn_status0 12914 */ 12915 /**************************************************************************** 12916 * ilkn_status0 :: ilkn_status0 12917 */ 12918 /* ilkn_status0 :: ilkn_status0 :: reserved0 [15:08] */ 12919 #define ILKN_STATUS0_ILKN_STATUS0_RESERVED0_MASK 0xff00 12920 #define ILKN_STATUS0_ILKN_STATUS0_RESERVED0_ALIGN 0 12921 #define ILKN_STATUS0_ILKN_STATUS0_RESERVED0_BITS 8 12922 #define ILKN_STATUS0_ILKN_STATUS0_RESERVED0_SHIFT 8 12923 12924 /* ilkn_status0 :: ilkn_status0 :: txfifo_underrun [07:07] */ 12925 #define ILKN_STATUS0_ILKN_STATUS0_TXFIFO_UNDERRUN_MASK 0x0080 12926 #define ILKN_STATUS0_ILKN_STATUS0_TXFIFO_UNDERRUN_ALIGN 0 12927 #define ILKN_STATUS0_ILKN_STATUS0_TXFIFO_UNDERRUN_BITS 1 12928 #define ILKN_STATUS0_ILKN_STATUS0_TXFIFO_UNDERRUN_SHIFT 7 12929 12930 /* ilkn_status0 :: ilkn_status0 :: txfifo_overrun [06:06] */ 12931 #define ILKN_STATUS0_ILKN_STATUS0_TXFIFO_OVERRUN_MASK 0x0040 12932 #define ILKN_STATUS0_ILKN_STATUS0_TXFIFO_OVERRUN_ALIGN 0 12933 #define ILKN_STATUS0_ILKN_STATUS0_TXFIFO_OVERRUN_BITS 1 12934 #define ILKN_STATUS0_ILKN_STATUS0_TXFIFO_OVERRUN_SHIFT 6 12935 12936 /* ilkn_status0 :: ilkn_status0 :: txfifo_full [05:05] */ 12937 #define ILKN_STATUS0_ILKN_STATUS0_TXFIFO_FULL_MASK 0x0020 12938 #define ILKN_STATUS0_ILKN_STATUS0_TXFIFO_FULL_ALIGN 0 12939 #define ILKN_STATUS0_ILKN_STATUS0_TXFIFO_FULL_BITS 1 12940 #define ILKN_STATUS0_ILKN_STATUS0_TXFIFO_FULL_SHIFT 5 12941 12942 /* ilkn_status0 :: ilkn_status0 :: txfifo_empty [04:04] */ 12943 #define ILKN_STATUS0_ILKN_STATUS0_TXFIFO_EMPTY_MASK 0x0010 12944 #define ILKN_STATUS0_ILKN_STATUS0_TXFIFO_EMPTY_ALIGN 0 12945 #define ILKN_STATUS0_ILKN_STATUS0_TXFIFO_EMPTY_BITS 1 12946 #define ILKN_STATUS0_ILKN_STATUS0_TXFIFO_EMPTY_SHIFT 4 12947 12948 /* ilkn_status0 :: ilkn_status0 :: rxfifo_underrun [03:03] */ 12949 #define ILKN_STATUS0_ILKN_STATUS0_RXFIFO_UNDERRUN_MASK 0x0008 12950 #define ILKN_STATUS0_ILKN_STATUS0_RXFIFO_UNDERRUN_ALIGN 0 12951 #define ILKN_STATUS0_ILKN_STATUS0_RXFIFO_UNDERRUN_BITS 1 12952 #define ILKN_STATUS0_ILKN_STATUS0_RXFIFO_UNDERRUN_SHIFT 3 12953 12954 /* ilkn_status0 :: ilkn_status0 :: rxfifo_overrun [02:02] */ 12955 #define ILKN_STATUS0_ILKN_STATUS0_RXFIFO_OVERRUN_MASK 0x0004 12956 #define ILKN_STATUS0_ILKN_STATUS0_RXFIFO_OVERRUN_ALIGN 0 12957 #define ILKN_STATUS0_ILKN_STATUS0_RXFIFO_OVERRUN_BITS 1 12958 #define ILKN_STATUS0_ILKN_STATUS0_RXFIFO_OVERRUN_SHIFT 2 12959 12960 /* ilkn_status0 :: ilkn_status0 :: rxfifo_full [01:01] */ 12961 #define ILKN_STATUS0_ILKN_STATUS0_RXFIFO_FULL_MASK 0x0002 12962 #define ILKN_STATUS0_ILKN_STATUS0_RXFIFO_FULL_ALIGN 0 12963 #define ILKN_STATUS0_ILKN_STATUS0_RXFIFO_FULL_BITS 1 12964 #define ILKN_STATUS0_ILKN_STATUS0_RXFIFO_FULL_SHIFT 1 12965 12966 /* ilkn_status0 :: ilkn_status0 :: rxfifo_empty [00:00] */ 12967 #define ILKN_STATUS0_ILKN_STATUS0_RXFIFO_EMPTY_MASK 0x0001 12968 #define ILKN_STATUS0_ILKN_STATUS0_RXFIFO_EMPTY_ALIGN 0 12969 #define ILKN_STATUS0_ILKN_STATUS0_RXFIFO_EMPTY_BITS 1 12970 #define ILKN_STATUS0_ILKN_STATUS0_RXFIFO_EMPTY_SHIFT 0 12971 12972 12973 /**************************************************************************** 12974 * Datatype Definitions. 12975 */ 12976 #endif /* #ifndef TEPCSREGENUMS_TMP__ */ 12977 12978 /* End of File */ 12979