sc_field_defines.h (9195B)
1 /*---------------------------------------------------------------------- 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * Broadcom Corporation 8 * Proprietary and Confidential information 9 * All rights reserved 10 * This source file is the property of Broadcom Corporation, and 11 * may not be copied or distributed in any isomorphic form without the 12 * prior written consent of Broadcom Corporation. 13 *--------------------------------------------------------------------- 14 * File : sc_field_defines.h 15 * Description: 16 *---------------------------------------------------------------------*/ 17 18 /*############################################################################## 19 ############################################################################# */ 20 #define TEMOD16_PLL_MODE_DIV_40 2 21 #define TEMOD16_PLL_MODE_DIV_42 3 22 #define TEMOD16_PLL_MODE_DIV_48 4 23 #define TEMOD16_PLL_MODE_DIV_52 6 24 #define TEMOD16_PLL_MODE_DIV_54 7 25 #define TEMOD16_PLL_MODE_DIV_60 8 26 #define TEMOD16_PLL_MODE_DIV_64 9 27 #define TEMOD16_PLL_MODE_DIV_66 10 28 #define TEMOD16_PLL_MODE_DIV_70 12 29 #define TEMOD16_PLL_MODE_DIV_80 13 30 #define TEMOD16_PLL_MODE_DIV_92 14 31 #define TEMOD16_PLL_MODE_ILLEGAL 0 32 33 /*############################################################################# */ 34 #define TEMOD16_PMA_OS_MODE_1 0 35 #define TEMOD16_PMA_OS_MODE_2 1 36 #define TEMOD16_PMA_OS_MODE_3 2 37 #define TEMOD16_PMA_OS_MODE_3_3 3 38 #define TEMOD16_PMA_OS_MODE_4 4 39 #define TEMOD16_PMA_OS_MODE_5 5 40 #define TEMOD16_PMA_OS_MODE_7_5 6 41 #define TEMOD16_PMA_OS_MODE_8 7 42 #define TEMOD16_PMA_OS_MODE_8_25 8 43 #define TEMOD16_PMA_OS_MODE_10 9 44 #define TEMOD16_PMA_OS_MODE_ILLEGAL 15 45 46 /*############################################################################# */ 47 #define TEMOD16_SCR_MODE_BYPASS 0 48 #define TEMOD16_SCR_MODE_66B 1 49 #define TEMOD16_SCR_MODE_80B 2 50 #define TEMOD16_SCR_MODE_64B 3 51 52 /*############################################################################# */ 53 #define TEMOD16_ENCODE_MODE_NONE 0 54 #define TEMOD16_ENCODE_MODE_CL48 1 55 #define TEMOD16_ENCODE_MODE_CL48_2_LANE 2 56 #define TEMOD16_ENCODE_MODE_CL36 3 57 #define TEMOD16_ENCODE_MODE_CL82 4 58 #define TEMOD16_ENCODE_MODE_CL49 5 59 #define TEMOD16_ENCODE_MODE_BRCM 6 60 #define TEMOD16_ENCODE_MODE_ILLEGAL 7 61 62 63 /*############################################################################# */ 64 #define TEMOD16_CL48_CHECK_END_OFF 0 65 #define TEMOD16_CL48_CHECK_END_ON 1 66 67 /*############################################################################# */ 68 #define TEMOD16_SIGDET_FILTER_NONCX4 0 69 #define TEMOD16_SIGDET_FILTER_CX4 1 70 71 /*############################################################################# */ 72 #define TEMOD16_BLOCKSYNC_MODE_NONE 0 73 #define TEMOD16_BLOCKSYNC_MODE_CL49 1 74 #define TEMOD16_BLOCKSYNC_MODE_CL82 2 75 #define TEMOD16_BLOCKSYNC_MODE_8B10B 3 76 #define TEMOD16_BLOCKSYNC_MODE_FEC 4 77 #define TEMOD16_BLOCKSYNC_MODE_BRCM 5 78 #define TEMOD16_BLOCKSYNC_MODE_ILLEGAL 7 79 80 /*############################################################################# */ 81 #define TEMOD16_R_REORDER_MODE_NONE 0 82 #define TEMOD16_R_REORDER_MODE_CL48 1 83 #define TEMOD16_R_REORDER_MODE_CL36 2 84 #define TEMOD16_R_REORDER_MODE_CL36_CL48 3 85 86 /*############################################################################# */ 87 #define TEMOD16_CL36_DISABLE 0 88 #define TEMOD16_CL36_ENABLE 1 89 90 /*############################################################################# */ 91 #define TEMOD16_R_DESCR1_MODE_BYPASS 0 92 #define TEMOD16_R_DESCR1_MODE_66B 1 93 #define TEMOD16_R_DESCR1_MODE_10B 2 94 #define TEMOD16_R_DESCR1_MODE_ILLEGAL 3 95 96 97 /*############################################################################# */ 98 #define TEMOD16_DECODER_MODE_NONE 0 99 #define TEMOD16_DECODER_MODE_CL49 1 100 #define TEMOD16_DECODER_MODE_BRCM 2 101 #define TEMOD16_DECODER_MODE_ALU 3 102 #define TEMOD16_DECODER_MODE_CL48 4 103 #define TEMOD16_DECODER_MODE_CL36 5 104 #define TEMOD16_DECODER_MODE_CL82 6 105 #define TEMOD16_DECODER_MODE_ILLEGAL 7 106 107 /*############################################################################# */ 108 #define TEMOD16_R_DESKEW_MODE_BYPASS 0 109 #define TEMOD16_R_DESKEW_MODE_8B_10B 1 110 #define TEMOD16_R_DESKEW_MODE_BRCM_66B 2 111 #define TEMOD16_R_DESKEW_MODE_CL82_66B 3 112 #define TEMOD16_R_DESKEW_MODE_CL36_10B 4 113 #define TEMOD16_R_DESKEW_MODE_ILLEGAL 7 114 115 /*#############################################################################*/ 116 #define TEMOD16_DESC2_MODE_NONE 0 117 #define TEMOD16_DESC2_MODE_CL49 1 118 #define TEMOD16_DESC2_MODE_BRCM 2 119 #define TEMOD16_DESC2_MODE_ALU 3 120 #define TEMOD16_DESC2_MODE_CL48 4 121 #define TEMOD16_DESC2_MODE_CL36 5 122 #define TEMOD16_DESC2_MODE_CL82 6 123 #define TEMOD16_DESC2_MODE_ILLEGAL 7 124 125 126 /*#############################################################################*/ 127 128 #define TEMOD16_R_DESC2_BYTE_DELETION_100M 0 129 #define TEMOD16_R_DESC2_BYTE_DELETION_10M 1 130 #define TEMOD16_R_DESC2_BYTE_DELETION_NONE 2 131 132 /*############################################################################*/ 133 134 #define TEMOD16_R_DEC1_DESCR_MODE_NONE 0 135 #define TEMOD16_R_DEC1_DESCR_MODE_BRCM64B66B 1 136 137 /*#############################################################################*/ 138 139 #define RTL_SPEED_100G_CR10 0x29 140 #define RTL_SPEED_40G_CR4 0x28 141 #define RTL_SPEED_40G_KR4 0x27 142 #define RTL_SPEED_40G_X4 0x1C 143 #define RTL_SPEED_32p7G_X4 0x21 144 #define RTL_SPEED_31p5G_X4 0x20 145 #define RTL_SPEED_25p45G_X4 0x14 146 #define RTL_SPEED_21G_X4 0x13 147 #define RTL_SPEED_20G_CR2 0x3A 148 #define RTL_SPEED_20G_KR2 0x39 149 #define RTL_SPEED_20G_X2 0x1D 150 #define RTL_SPEED_20G_X4 0x22 151 #define RTL_SPEED_20G_CX2 0x1E 152 #define RTL_SPEED_20G_CX4 0x12 153 #define RTL_SPEED_16G_X4 0x0C 154 #define RTL_SPEED_15p75G_X2 0x2C 155 #define RTL_SPEED_15G_X4 0x0B 156 #define RTL_SPEED_13G_X4 0x0A 157 #define RTL_SPEED_12p7G_X2 0x19 158 #define RTL_SPEED_12p5G_X4 0x09 159 #define RTL_SPEED_12G_X4 0x08 160 #define RTL_SPEED_10p5G_X2 0x17 161 #define RTL_SPEED_10G_KR1 0x0F 162 #define RTL_SPEED_10G_CX2 0x24 163 #define RTL_SPEED_10G_X2 0x23 164 #define RTL_SPEED_10G_KX4 0x0E 165 #define RTL_SPEED_10G_CX4 0x07 166 #define RTL_SPEED_10G_X4 0x06 167 #define RTL_SPEED_10G_CX1 0x33 168 #define RTL_SPEED_6G_X4 0x05 169 #define RTL_SPEED_5G_X4 0x04 170 #define RTL_SPEED_5G_X2 0x2A 171 #define RTL_SPEED_2p5G_X1 0x03 172 #define RTL_SPEED_1G_KX1 0x0D 173 #define RTL_SPEED_1000M 0x02 174 #define RTL_SPEED_1G_CX1 0x34 175 #define RTL_SPEED_100M 0x01 176 #define RTL_SPEED_10M 0x00 177 #define RTL_SPEED_5G_X1 0x10 178 #define RTL_SPEED_6p36G_X1 0x11 179 #define RTL_SPEED_10G_X2_NOSCRAMBLE 0x15 180 #define RTL_SPEED_10G_CX2_NOSCRAMBLE 0x16 181 #define RTL_SPEED_10p5G_CX2_NOSCRAMBLE 0x18 182 #define RTL_SPEED_12p7G_CX2 0x1A 183 #define RTL_SPEED_10G_X1 0x1B 184 #define RTL_SPEED_10G_SFI 0x1F 185 #define RTL_SPEED_3p125G_IL 0x3C 186 #define RTL_SPEED_6p25_IL 0x3D 187 #define RTL_SPEED_10p31G_IL 0x3E 188 #define RTL_SPEED_10p96G_IL 0x3F 189 #define RTL_SPEED_12p5G_IL 0x40 190 #define RTL_SPEED_11p5G_IL 0x41 191 #define RTL_SPEED_1p25G_IL 0x42 192 #define RTL_SPEED_2G_FC 0x2E 193 #define RTL_SPEED_4G_FC 0x2F 194 #define RTL_SPEED_8G_FC 0x30 195 #define RTL_SPEED_1G_CL73 0x3B 196 #define RTL_SPEED_1000M_SGMII 0x2D 197 #define RTL_SPEED_NONE 0x2B 198 199 200 /*#############################################################################*/