temod_enum_defines.c (17521B)
1 /*---------------------------------------------------------------------- 2 * : temod_enum_defines.h, 3 * : n * 4 * Broadcom Corporation 5 * Proprietary and Confidential information 6 * All rights reserved 7 * This source file is the property of Broadcom Corporation, and 8 * may not be copied or distributed in any isomorphic form without the 9 * prior written consent of Broadcom Corporation. 10 *--------------------------------------------------------------------- 11 *--------------------------------------------------------------------- 12 ############### THIS FILE IS AUTOMATICALLY GENERATED. ############### 13 ############### DO !! NOT !! MANUALLY EDIT THIS FILE. ############### 14 *--------------------------------------------------------------------- 15 * Description: This file contains enums, elems, and doxygen comments 16 * needed for SerDes Configuration programs. 17 *--------------------------------------------------------------------- 18 * CVS INFORMATION: 19 * Please see inc/enum_desc.txt for CVS information. 20 *---------------------------------------------------------------------- 21 */ 22 /* 23 * 24 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 25 * 26 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 27 */ 28 /* This file is automatically generated. Do not modify it. Modify the 29 * inc/enum_desc.txt to change enums, elems, or comments. For issues about 30 * the process that creates this file contact the temod development team. 31 */ 32 33 #include "temod_enum_defines.h" 34 35 char* e2s_temod_core_select [CNT_temod_core_select] = { 36 "TEMOD_CORE_0_0_1" , 37 "TEMOD_CORE_0_1_0" , 38 "TEMOD_CORE_1_0_0" , 39 "TEMOD_CORE_0_1_1" , 40 "TEMOD_CORE_1_0_1" , 41 "TEMOD_CORE_1_1_1" , 42 "TEMOD_CORE_ILLEGAL" 43 }; /* e2s_temod_core_select */ 44 45 int e2n_temod_core_select [CNT_temod_core_select] = { 46 1 , 47 2 , 48 4 , 49 3 , 50 5 , 51 7 , 52 0 53 }; /* e2n_temod_core_select */ 54 55 char* e2s_temod_lane_select [CNT_temod_lane_select] = { 56 "TEMOD_LANE_0_0_0_1" , 57 "TEMOD_LANE_0_0_1_0" , 58 "TEMOD_LANE_0_0_1_1" , 59 "TEMOD_LANE_0_1_0_0" , 60 "TEMOD_LANE_0_1_0_1" , 61 "TEMOD_LANE_0_1_1_0" , 62 "TEMOD_LANE_0_1_1_1" , 63 "TEMOD_LANE_1_0_0_0" , 64 "TEMOD_LANE_1_0_0_1" , 65 "TEMOD_LANE_1_0_1_0" , 66 "TEMOD_LANE_1_0_1_1" , 67 "TEMOD_LANE_1_1_0_0" , 68 "TEMOD_LANE_1_1_0_1" , 69 "TEMOD_LANE_1_1_1_0" , 70 "TEMOD_LANE_1_1_1_1" , 71 "TEMOD_LANE_BCST" , 72 "TEMOD_LANE_ILLEGAL" 73 }; /* e2s_temod_lane_select */ 74 75 int e2n_temod_lane_select [CNT_temod_lane_select] = { 76 1 , 77 2 , 78 3 , 79 4 , 80 5 , 81 6 , 82 7 , 83 8 , 84 9 , 85 10 , 86 11 , 87 12 , 88 13 , 89 14 , 90 15 , 91 15 , 92 0 93 }; /* e2n_temod_lane_select */ 94 95 char* e2s_temod_spd_intfc_type [CNT_temod_spd_intfc_type] = { 96 "TEMOD_SPD_ZERO" , 97 "TEMOD_SPD_10_X1_SGMII" , 98 "TEMOD_SPD_100_X1_SGMII" , 99 "TEMOD_SPD_1000_X1_SGMII" , 100 "TEMOD_SPD_2500_X1" , 101 "TEMOD_SPD_10_SGMII" , 102 "TEMOD_SPD_100_SGMII" , 103 "TEMOD_SPD_1000_SGMII" , 104 "TEMOD_SPD_2500" , 105 "TEMOD_SPD_5000" , 106 "TEMOD_SPD_1000_XFI" , 107 "TEMOD_SPD_5000_XFI" , 108 "TEMOD_SPD_10000_XFI" , 109 "TEMOD_SPD_10600_XFI_HG" , 110 "TEMOD_SPD_10000_HI" , 111 "TEMOD_SPD_10000" , 112 "TEMOD_SPD_12000_HI" , 113 "TEMOD_SPD_13000" , 114 "TEMOD_SPD_15000" , 115 "TEMOD_SPD_16000" , 116 "TEMOD_SPD_20000" , 117 "TEMOD_SPD_20000_SCR" , 118 "TEMOD_SPD_21000" , 119 "TEMOD_SPD_25455" , 120 "TEMOD_SPD_31500" , 121 "TEMOD_SPD_31500_MLD" , 122 "TEMOD_SPD_40G_X4" , 123 "TEMOD_SPD_42G_X4" , 124 "TEMOD_SPD_40G_XLAUI" , 125 "TEMOD_SPD_42G_XLAUI" , 126 "TEMOD_SPD_10000_X2" , 127 "TEMOD_SPD_10000_HI_DXGXS" , 128 "TEMOD_SPD_10000_DXGXS" , 129 "TEMOD_SPD_10000_HI_DXGXS_SCR" , 130 "TEMOD_SPD_10000_DXGXS_SCR" , 131 "TEMOD_SPD_10500_HI" , 132 "TEMOD_SPD_10500_HI_DXGXS" , 133 "TEMOD_SPD_12773_HI_DXGXS" , 134 "TEMOD_SPD_12773_DXGXS" , 135 "TEMOD_SPD_15750_HI_DXGXS" , 136 "TEMOD_SPD_20G_MLD_DXGXS" , 137 "TEMOD_SPD_21G_HI_MLD_DXGXS" , 138 "TEMOD_SPD_20G_DXGXS" , 139 "TEMOD_SPD_21G_HI_DXGXS" , 140 "TEMOD_SPD_100G_CR10" , 141 "TEMOD_SPD_107G_HG_CR10" , 142 "TEMOD_SPD_120G_CR12" , 143 "TEMOD_SPD_127G_HG_CR12" , 144 "TEMOD_SPD_4000" , 145 "TEMOD_SPD_ILLEGAL" 146 }; /* e2s_temod_spd_intfc_type */ 147 148 int e2n_temod_spd_intfc_type [CNT_temod_spd_intfc_type] = { 149 0 , 150 10 , 151 100 , 152 1000 , 153 2500 , 154 10 , 155 100 , 156 1000 , 157 2500 , 158 5000 , 159 5000 , 160 5000 , 161 10000 , 162 10560 , 163 10000 , 164 10000 , 165 12000 , 166 13000 , 167 15000 , 168 16000 , 169 20000 , 170 20000 , 171 21000 , 172 25000 , 173 31500 , 174 31500 , 175 40000 , 176 40000 , 177 40000 , 178 42000 , 179 10000 , 180 10000 , 181 10000 , 182 10000 , 183 10000 , 184 10500 , 185 10500 , 186 12773 , 187 12773 , 188 15750 , 189 20000 , 190 20000 , 191 20000 , 192 21000 , 193 100000 , 194 107000 , 195 120000 , 196 127000 , 197 4000 , 198 0 199 }; /* e2n_temod_spd_intfc_type */ 200 201 char* e2s_temod_regacc_type [CNT_temod_regacc_type] = { 202 "TEMOD_REGACC_CL22" , 203 "TEMOD_REGACC_CL45" , 204 "TEMOD_REGACC_TOTSC" , 205 "TEMOD_REGACC_SBUS_FD" , 206 "TEMOD_REGACC_SBUS_BD" , 207 "TEMOD_REGACC_ILLEGAL" 208 }; /* e2s_temod_regacc_type */ 209 210 char* e2s_temod_port_type [CNT_temod_port_type] = { 211 "TEMOD_SINGLE_PORT" , 212 "TEMOD_MULTI_PORT" , 213 "TEMOD_DXGXS" , 214 "TEMOD_TRI1_PORT" , 215 "TEMOD_TRI2_PORT" , 216 "TEMOD_PORT_MODE_ILLEGAL" 217 }; /* e2s_temod_port_type */ 218 219 char* e2s_temod_diag_type [CNT_temod_diag_type] = { 220 "TEMOD_DIAG_GENERAL" , 221 "TEMOD_DIAG_TOPOLOGY" , 222 "TEMOD_DIAG_LINK" , 223 "TEMOD_DIAG_SPEED" , 224 "TEMOD_DIAG_ANEG" , 225 "TEMOD_DIAG_TFC" , 226 "TEMOD_DIAG_AN_TIMERS" , 227 "TEMOD_DIAG_STATE" , 228 "TEMOD_DIAG_DEBUG" , 229 "TEMOD_DIAG_IEEE" , 230 "TEMOD_DIAG_EEE" , 231 "TEMOD_DIAG_BER" , 232 "TEMOD_DIAG_CFG" , 233 "TEMOD_DIAG_CL72" , 234 "TEMOD_DIAG_DSC", 235 "TEMOD_SERDES_DIAG" , 236 "TEMOD_DIAG_ALL" , 237 "TEMOD_DIAG_ILLEGAL" 238 }; /* e2s_temod_diag_type */ 239 240 char* e2s_temod_pmd_diag_type [CNT_temod_pmd_diag_type] = { 241 "TEMOD_SERDES_DIAG_CORE_CONFIG" , 242 "TEMOD_SERDES_DIAG_CORE_STATE" , 243 "TEMOD_SERDES_DIAG_LANE_CONFIG" , 244 "TEMOD_SERDES_DIAG_LANE_DEBUG_STATUS" , 245 "TEMOD_SERDES_DIAG_LANE_STATE" , 246 "TEMOD_SERDES_DIAG_LANE_STATE_HDR" , 247 "TEMOD_SERDES_DIAG_LANE_STATE_LEGEND" , 248 "TEMOD_SERDES_DIAG_CL72_STATUS" , 249 "TEMOD_SERDES_DIAG_EYE_DENSITY" , 250 "TEMOD_SERDES_DIAG_EYE_SCAN" , 251 "TEMOD_SERDES_DIAG_MEAS_EYE_DENSITY_DATA" , 252 "TEMOD_SERDES_DIAG_MEAS_EYE_SCAN_DONE" , 253 "TEMOD_SERDES_DIAG_MEAS_LOWBER_EYE" , 254 "TEMOD_SERDES_DIAG_READ_EYE_SCAN_STRIPE" , 255 "TEMOD_SERDES_DIAG_EYE_DENSITY_DATA" , 256 "TEMOD_SERDES_DIAG_LOWBER_EYE" , 257 "TEMOD_SERDES_DIAG_EYE_SCAN_VERTICAL" , 258 "TEMOD_SERDES_DIAG_EYE_SCAN_STRIPE" , 259 "TEMOD_SERDES_DIAG_EYE_SCAN_HEADER" , 260 "TEMOD_SERDES_DIAG_EYE_SCAN_FOOTER" , 261 "TEMOD_SERDES_DIAG_BER_SCAN_TEST" , 262 "TEMOD_SERDES_DIAG_READ_BER_SCAN_DATA" , 263 "TEMOD_SERDES_DIAG_EYE_MARGIN_PROJ" , 264 "TEMOD_SERDES_DIAG_DIG_LPBK" , 265 "TEMOD_SERDES_DIAG_MEAS_EYE_SCAN_START" , 266 "TEMOD_SERDES_DIAG_ILLEGAL" 267 }; /* e2s_temod_pmd_diag_type */ 268 269 270 char* e2s_temod_eye_direction [CNT_temod_eye_direction] = { 271 "TEMOD_EYE_VU" , 272 "TEMOD_EYE_VD" , 273 "TEMOD_EYE_HL" , 274 "TEMOD_EYE_HR" , 275 "TEMOD_EYE_ILLEGAL" 276 }; /* e2s_temod_eye_direction */ 277 278 char* e2s_temod_tech_ability [CNT_temod_tech_ability] = { 279 "TEMOD_ABILITY_1G_KX" , 280 "TEMOD_ABILITY_10G_KX4" , 281 "TEMOD_ABILITY_10G_KR" , 282 "TEMOD_ABILITY_40G_KR4" , 283 "TEMOD_ABILITY_40G_CR4" , 284 "TEMOD_ABILITY_100G_CR10" , 285 "TEMOD_ABILITY_20G_KR2" , 286 "TEMOD_ABILITY_20G_CR2" , 287 "TEMOD_ABILITY_ILLEGAL" 288 }; /* e2s_temod_tech_ability */ 289 290 int e2n_temod_tech_ability [CNT_temod_tech_ability] = { 291 0x5 , 292 0x6 , 293 0x7 , 294 0x8 , 295 0x9 , 296 0xa , 297 0x100 , 298 0x101 , 299 0x102 300 }; /* e2n_temod_tech_ability */ 301 302 char* e2s_temod_cl37bam_ability [CNT_temod_cl37bam_ability] = { 303 "TEMOD_BAM37ABL_2P5G" , 304 "TEMOD_BAM37ABL_5G_X4" , 305 "TEMOD_BAM37ABL_6G_X4" , 306 "TEMOD_BAM37ABL_10G_HIGIG" , 307 "TEMOD_BAM37ABL_10G_CX4" , 308 "TEMOD_BAM37ABL_12G_X4" , 309 "TEMOD_BAM37ABL_12P5_X4" , 310 "TEMOD_BAM37ABL_13G_X4" , 311 "TEMOD_BAM37ABL_15G_X4" , 312 "TEMOD_BAM37ABL_16G_X4" , 313 "TEMOD_BAM37ABL_20G_X4_CX4" , 314 "TEMOD_BAM37ABL_20G_X4" , 315 "TEMOD_BAM37ABL_21G_X4" , 316 "TEMOD_BAM37ABL_25P455G" , 317 "TEMOD_BAM37ABL_31P5G" , 318 "TEMOD_BAM37ABL_32P7G" , 319 "TEMOD_BAM37ABL_40G" , 320 "TEMOD_BAM37ABL_10G_X2_CX4" , 321 "TEMOD_BAM37ABL_10G_DXGXS" , 322 "TEMOD_BAM37ABL_10P5G_DXGXS" , 323 "TEMOD_BAM37ABL_12P7_DXGXS" , 324 "TEMOD_BAM37ABL_15P75G_R2" , 325 "TEMOD_BAM37ABL_20G_X2_CX4" , 326 "TEMOD_BAM37ABL_20G_X2" , 327 "TEMOD_BAM37ABL_ILLEGAL" 328 }; /* e2s_temod_cl37bam_ability */ 329 330 char* e2s_temod_diag_an_type [CNT_temod_diag_an_type] = { 331 "TEMOD_DIAG_AN_DONE" , 332 "TEMOD_DIAG_AN_HCD" , 333 "TEMOD_DIAG_AN_TYPE_ILLEGAL" 334 }; /* e2s_temod_diag_an_type */ 335 336 char* e2s_temod_tier1_function_type [CNT_temod_tier1_function_type] = { 337 "PCS_BYPASS_CTL" , 338 "INIT_PCS" , 339 "INIT_PMD_SW" , 340 "INIT_PMD" , 341 "PMD_RESET_SEQ" , 342 "PMD_X4_RESET" , 343 "WAIT_SC_DONE" , 344 "ENABLE_SET" , 345 "FECMODE_SET" , 346 "GET_PCS_LINK_STATUS" , 347 "OVERRIDE_SET" , 348 "CREDIT_OVERRIDE_SET" , 349 "ENCODE_SET" , 350 "DECODE_SET" , 351 "CREDIT_CONTROL" , 352 "TX_LANE_CONTROL" , 353 "RX_LANE_CONTROL" , 354 "TX_LANE_DISABLE" , 355 "POWER_CONTROL" , 356 "AUTONEG_SET" , 357 "AUTONEG_GET" , 358 "AUTONEG_CONTROL" , 359 "TSC12_CONTROL" , 360 "CHECK_SC_STATS" , 361 "REG_READ" , 362 "REG_WRITE" , 363 "PRBS_CHECK" , 364 "CJPAT_CRPAT_MODE_SET" , 365 "CJPAT_CRPAT_CHECK" , 366 "TEMOD_DIAG" , 367 "PCS_LANE_SWAP" , 368 "PMD_LANE_SWAP" , 369 "PMD_LANE_SWAP_TX" , 370 "PARALLEL_DETECT_CONTROL" , 371 "REVID_READ" , 372 "SOFT_RESET" , 373 "SET_SPD_INTF" , 374 "SET_PORT_MODE" , 375 "EEE_PASSTHRU_SET" , 376 "EEE_PASSTHRU_GET" , 377 "FEC_CONTROL" , 378 "HIGIG2_CONTROL" , 379 "LF_RF_CONTROL" , 380 "RX_FAST_LOCK_CONTROL" , 381 "PMD_CORE_RESET" , 382 "PMD_LANE_RESET" , 383 "AFE_SPEED_UP_DSC_VGA" , 384 "CLAUSE_72_CONTROL" , 385 "PLL_SEQUENCER_CONTROL" , 386 "PLL_LOCK_WAIT" , 387 "PROG_DATA" , 388 "RX_SEQ_CONTROL" , 389 "SET_POLARITY" , 390 "PRBS_CONTROL" , 391 "PRBS_MODE" , 392 "RX_PF_CONTROL" , 393 "RX_VGA_CONTROL" , 394 "CJPAT_CRPAT_CONTROL" , 395 "TX_LOOPBACK_CONTROL" , 396 "TX_PMD_LOOPBACK_CONTROL" , 397 "RX_LOOPBACK_CONTROL" , 398 "RX_P1_SLICER_CONTROL" , 399 "RX_M1_SLICER_CONTROL" , 400 "RX_D_SLICER_CONTROL" , 401 "WAIT_PMD_LOCK" , 402 "FIRMWARE_SET" , 403 "INIT_PMD_QSGMII" , 404 "INIT_PCS_ILKN" , 405 "PMD_RESET_BYPASS" , 406 "PMD_OVERRIDE_CONTROL" , 407 "TIER1_FUNCTION_ILLEGAL" 408 }; /* e2s_temod_tier1_function_type */ 409 410 char* e2s_sc_mode_type [CNT_sc_mode_type] = { 411 "TEMOD_SC_MODE_HT_WITH_BASIC_OVERRIDE" , 412 "TEMOD_SC_MODE_HT_OVERRIDE" , 413 "TEMOD_SC_MODE_ST" , 414 "TEMOD_SC_MODE_ST_OVERRIDE" , 415 "TEMOD_SC_MODE_AN_CL37" , 416 "TEMOD_SC_MODE_AN_CL73" , 417 "TEMOD_SC_MODE_BYPASS" , 418 "TEMOD_SC_MODE_ILLEGAL" 419 }; /* e2s_sc_mode_type */ 420 421 int e2n_sc_mode_type [CNT_sc_mode_type] = { 422 0 , 423 1 , 424 2 , 425 3 , 426 4 , 427 5 , 428 6 , 429 7 430 }; /* e2n_sc_mode_type */ 431 432 char* e2s_temod_pll_mode_type [CNT_temod_pll_mode_type] = { 433 "TEMOD_PLL_MODE_DIV_ZERO" , 434 "TEMOD_PLL_MODE_DIV_72" , 435 "TEMOD_PLL_MODE_DIV_40" , 436 "TEMOD_PLL_MODE_DIV_42" , 437 "TEMOD_PLL_MODE_DIV_48" , 438 "TEMOD_PLL_MODE_DIV_50" , 439 "TEMOD_PLL_MODE_DIV_52" , 440 "TEMOD_PLL_MODE_DIV_54" , 441 "TEMOD_PLL_MODE_DIV_60" , 442 "TEMOD_PLL_MODE_DIV_64" , 443 "TEMOD_PLL_MODE_DIV_66" , 444 "TEMOD_PLL_MODE_DIV_68" , 445 "TEMOD_PLL_MODE_DIV_70" , 446 "TEMOD_PLL_MODE_DIV_80" , 447 "TEMOD_PLL_MODE_DIV_92" , 448 "TEMOD_PLL_MODE_DIV_100" , 449 "TEMOD_PLL_MODE_DIV_82P5" , 450 "TEMOD_PLL_MODE_DIV_87P5" , 451 "TEMOD_PLL_MODE_DIV_ILLEGAL" 452 }; /* e2s_temod_pll_mode_type */ 453 454 int e2n_temod_pll_mode_type [CNT_temod_pll_mode_type] = { 455 0 , 456 40 , 457 42 , 458 48 , 459 52 , 460 54 , 461 60 , 462 64 , 463 66 , 464 70 , 465 80 , 466 92 , 467 0 468 }; /* e2n_temod_pll_mode_type */ 469 470 char* e2s_temod_os_mode_type [CNT_temod_os_mode_type] = { 471 "TEMOD_PMA_OS_MODE_1" , 472 "TEMOD_PMA_OS_MODE_2" , 473 "TEMOD_PMA_OS_MODE_3" , 474 "TEMOD_PMA_OS_MODE_3_3" , 475 "TEMOD_PMA_OS_MODE_4" , 476 "TEMOD_PMA_OS_MODE_5" , 477 "TEMOD_PMA_OS_MODE_7_25" , 478 "TEMOD_PMA_OS_MODE_8" , 479 "TEMOD_PMA_OS_MODE_8_25" , 480 "TEMOD_PMA_OS_MODE_10" , 481 "TEMOD_PMA_OS_MODE_ILLEGAL" 482 }; /* e2s_temod_os_mode_type */ 483 484 int e2n_temod_os_mode_type [CNT_temod_os_mode_type] = { 485 1 , 486 2 , 487 3 , 488 33 , 489 4 , 490 5 , 491 725 , 492 8 , 493 825 , 494 9 , 495 0 496 }; /* e2n_temod_os_mode_type */ 497 498 char* e2s_temod_scr_mode [CNT_temod_scr_mode] = { 499 "TEMOD_SCR_MODE_BYPASS" , 500 "TEMOD_SCR_MODE_66B" , 501 "TEMOD_SCR_MODE_80B" , 502 "TEMOD_SCR_MODE_64B" 503 }; /* e2s_temod_scr_mode */ 504 505 int e2n_temod_scr_mode [CNT_temod_scr_mode] = { 506 0 , 507 1 , 508 2 , 509 3 510 }; /* e2n_temod_scr_mode */ 511 512 char* e2s_temod_encode_mode [CNT_temod_encode_mode] = { 513 "TEMOD_ENCODE_MODE_NONE" , 514 "TEMOD_ENCODE_MODE_CL48" , 515 "TEMOD_ENCODE_MODE_CL48_2_LANE" , 516 "TEMOD_ENCODE_MODE_CL36" , 517 "TEMOD_ENCODE_MODE_CL82" , 518 "TEMOD_ENCODE_MODE_CL49" , 519 "TEMOD_ENCODE_MODE_BRCM" , 520 "TEMOD_ENCODE_MODE_ILLEGAL" 521 }; /* e2s_temod_encode_mode */ 522 523 int e2n_temod_encode_mode [CNT_temod_encode_mode] = { 524 0 , 525 1 , 526 2 , 527 3 , 528 4 , 529 5 , 530 6 , 531 7 532 }; /* e2n_temod_encode_mode */ 533 534 char* e2s_temod_check_end_mode [CNT_temod_check_end_mode] = { 535 "TEMOD_CL48_CHECK_END_OFF" , 536 "TEMOD_CL48_CHECK_END_ON" 537 }; /* e2s_temod_check_end_mode */ 538 539 char* e2s_temod_sigdet_filter [CNT_temod_sigdet_filter] = { 540 "TEMOD_SIGDET_FILTER_NONCX4" , 541 "TEMOD_SIGDET_FILTER_CX4" 542 }; /* e2s_temod_sigdet_filter */ 543 544 char* e2s_temod_blocksync_mode [CNT_temod_blocksync_mode] = { 545 "TEMOD_BLOCKSYNC_MODE_NONE" , 546 "TEMOD_BLOCKSYNC_MODE_CL49" , 547 "TEMOD_BLOCKSYNC_MODE_CL82" , 548 "TEMOD_BLOCKSYNC_MODE_8B10B" , 549 "TEMOD_BLOCKSYNC_MODE_FEC" , 550 "TEMOD_BLOCKSYNC_MODE_BRCM" , 551 "TEMOD_BLOCKSYNC_MODE_ILLEGAL" 552 }; /* e2s_temod_blocksync_mode */ 553 554 char* e2s_temod_reorder_mode [CNT_temod_reorder_mode] = { 555 "TEMOD_R_REORDER_MODE_NONE" , 556 "TEMOD_R_REORDER_MODE_CL48" , 557 "TEMOD_R_REORDER_MODE_CL36" , 558 "TEMOD_R_REORDER_MODE_CL36_CL48" 559 }; /* e2s_temod_reorder_mode */ 560 561 char* e2s_temod_cl36_mode [CNT_temod_cl36_mode] = { 562 "TEMOD_CL36_DISABLE" , 563 "TEMOD_CL36_ENABLE" 564 }; /* e2s_temod_cl36_mode */ 565 566 char* e2s_temod_descrambler_mode [CNT_temod_descrambler_mode] = { 567 "TEMOD_R_DESCR1_MODE_BYPASS" , 568 "TEMOD_R_DESCR1_MODE_66B" , 569 "TEMOD_R_DESCR1_MODE_10B" , 570 "TEMOD_R_DESCR1_MODE_ILLEGAL" 571 }; /* e2s_temod_descrambler_mode */ 572 573 char* e2s_temod_decoder_mode [CNT_temod_decoder_mode] = { 574 "TEMOD_DECODER_MODE_NONE" , 575 "TEMOD_DECODER_MODE_CL49" , 576 "TEMOD_DECODER_MODE_BRCM" , 577 "TEMOD_DECODER_MODE_ALU" , 578 "TEMOD_DECODER_MODE_CL48" , 579 "TEMOD_DECODER_MODE_CL36" , 580 "TEMOD_DECODER_MODE_CL82" , 581 "TEMOD_DECODER_MODE_ILLEGAL" 582 }; /* e2s_temod_decoder_mode */ 583 584 char* e2s_temod_deskew_mode [CNT_temod_deskew_mode] = { 585 "TEMOD_R_DESKEW_MODE_BYPASS" , 586 "TEMOD_R_DESKEW_MODE_8B_10B" , 587 "TEMOD_R_DESKEW_MODE_BRCM_66B" , 588 "TEMOD_R_DESKEW_MODE_CL82_66B" , 589 "TEMOD_R_DESKEW_MODE_CL36_10B" , 590 "TEMOD_R_DESKEW_MODE_ILLEGAL" 591 }; /* e2s_temod_deskew_mode */ 592 593 char* e2s_temod_descrambler2_mode [CNT_temod_descrambler2_mode] = { 594 "TEMOD_DESC2_MODE_NONE" , 595 "TEMOD_DESC2_MODE_CL49" , 596 "TEMOD_DESC2_MODE_BRCM" , 597 "TEMOD_DESC2_MODE_ALU" , 598 "TEMOD_DESC2_MODE_CL48" , 599 "TEMOD_DESC2_MODE_CL36" , 600 "TEMOD_DESC2_MODE_CL82" , 601 "TEMOD_DESC2_MODE_ILLEGAL" 602 }; /* e2s_temod_descrambler2_mode */ 603 604 char* e2s_temod_byte_del_mode [CNT_temod_byte_del_mode] = { 605 "TEMOD_R_DESC2_BYTE_DELETION_100M" , 606 "TEMOD_R_DESC2_BYTE_DELETION_10M" , 607 "TEMOD_R_DESC2_BYTE_DELETION_NONE" 608 }; /* e2s_temod_byte_del_mode */ 609 610 char* e2s_temod_decode_descr_mode [CNT_temod_decode_descr_mode] = { 611 "TEMOD_R_DEC1_DESCR_MODE_NONE" , 612 "TEMOD_R_DEC1_DESCR_MODE_BRCM64B66B" 613 }; /* e2s_temod_decode_descr_mode */ 614 615 char* e2s_an_property_enable [CNT_an_property_enable] = { 616 "TEMOD_AN_PROPERTY_ENABLE_NONE" , 617 "TEMOD_AN_PROPERTY_ENABLE_SGMII_MASTER_MODE" , 618 "TEMOD_AN_PROPERTY_ENABLE_AN_PD_TO_CL37" , 619 "TEMOD_AN_PROPERTY_ENABLE_SGMII_TO_CL37_AUTO" , 620 "TEMOD_AN_PROPERTY_ENABLE_CL37_BAM_to_SGMII_AUTO" , 621 "TEMOD_AN_PROPERTY_ENABLE_HPAM_TO_CL73_AUTO" , 622 "TEMOD_AN_PROPERTY_ENABLE_CL73_BAM_TO_HPAM_AUTO" , 623 "TEMOD_AN_PROPERTY_ENABLE_ILLEGAL" 624 }; /* e2s_an_property_enable */ 625 626 char* e2s_credit_type_t [CNT_credit_type_t] = { 627 "TEMOD_CREDIT_RESET" , 628 "TEMOD_CREDIT_TABLE" , 629 "TEMOD_CREDIT_CLOCK_COUNT_0" , 630 "TEMOD_CREDIT_CLOCK_COUNT_1" , 631 "TEMOD_CREDIT_LOOP_COUNT_0" , 632 "TEMOD_CREDIT_LOOP_COUNT_1" , 633 "TEMOD_CREDIT_MAC" , 634 "TEMOD_CREDIT_PCS_CLOCK_COUNT_0" , 635 "TEMOD_CREDIT_PCS_GEN_COUNT" , 636 "TEMOD_CREDIT_EN" , 637 "TEMOD_CREDIT_PCS_REPCNT" , 638 "TEMOD_CREDIT_SGMII_SPD" , 639 "TEMOD_CREDIT_ILLEGAL" 640 }; /* e2s_credit_type_t */ 641 642 char* e2s_override_type_t [CNT_override_type_t] = { 643 "TEMOD_OVERRIDE_RESET" , 644 "TEMOD_OVERRIDE_CL72" , 645 "TEMOD_OVERRIDE_SPDID" , 646 "TEMOD_OVERRIDE_NUM_LANES" , 647 "TEMOD_OVERRIDE_OS_MODE" , 648 "TEMOD_OVERRIDE_FEC_EN" , 649 "TEMOD_OVERRIDE_DESKEW_MODE" , 650 "TEMOD_OVERRIDE_DESC2_MODE" , 651 "TEMOD_OVERRIDE_CL36BYTEDEL_MODE" , 652 "TEMOD_OVERRIDE_BRCM64B66_DESCR_MODE" , 653 "TEMOD_OVERRIDE_CHKEND_EN" , 654 "TEMOD_OVERRIDE_BLKSYNC_MODE" , 655 "TEMOD_OVERRIDE_DECODE_MODE" , 656 "TEMOD_OVERRIDE_REORDER_EN" , 657 "TEMOD_OVERRIDE_CL36_EN" , 658 "TEMOD_OVERRIDE_SCR_MODE" , 659 "TEMOD_OVERRIDE_DESCR_MODE" , 660 "TEMOD_OVERRIDE_ENCODE_MODE" , 661 "TEMOD_OVERRIDE_ALL" 662 }; /* e2s_override_type_t */ 663 664 char* e2s_temod_ref_clk_t [CNT_temod_ref_clk_t] = { 665 "TEMODREFCLK156MHZ" , 666 "TEMODREFCLK125MHZ" , 667 "TEMODREFCLKCOUNT" 668 }; /* e2s_temod_ref_clk_t */ 669