temod_diagnostics.c (56957B)
1 /*---------------------------------------------------------------------- 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * Broadcom Corporation 8 * Proprietary and Confidential information 9 * Copyright: (c) 2012 Broadcom Corp. 10 * All rights reserved 11 * This source file is the property of Broadcom Corporation, and 12 * may not be copied or distributed in any isomorphic form without the 13 * prior written consent of Broadcom Corporation. 14 *--------------------------------------------------------------------- 15 * File : temod_diagnostics.c 16 * Description: C sequences which utilize tier1s to build configurations 17 * which target only the diagnostic features of the Serdes 18 *-----------------------------------------------------------------------*/ 19 20 #ifndef _DV_TB_ 21 #define _SDK_TEMOD_ 1 22 #endif 23 24 #ifdef _DV_TB_ 25 #include "temod_phyreg.h" 26 #include <stdint.h> 27 #include "temod_main.h" 28 #include "temod_defines.h" 29 #include "temod_phyreg.h" 30 #include "tePCSRegEnums.h" 31 #include "tePMDRegEnums.h" 32 #include "phy_tsc_iblk.h" 33 #include "bcmi_tsce_xgxs_defs.h" 34 #endif 35 36 #ifdef _SDK_TEMOD_ 37 #include <phymod/phymod.h> 38 #include <phymod/phymod_system.h> 39 #include <phymod/phymod_config.h> 40 #include <phymod/phymod_debug.h> 41 #include <phymod/chip/bcmi_tsce_xgxs_defs.h> 42 #include "temod_enum_defines.h" 43 #include "temod.h" 44 #include "temod_sc_lkup_table.h" 45 #include "tePCSRegEnums.h" 46 #endif 47 48 #define _TRGO_(a,l) PHYMOD_DEBUG_ERROR(("<< PHY_TRG: Adr:%06d Ln:%02d\n",a,l)); 49 #define _TRGC_(a,l) PHYMOD_DEBUG_ERROR((">> PHY TRG: Adr:%06d Ln:%02d\n",a,l)); 50 #ifdef _SDK_TEMOD_ 51 #define PHYMOD_ST const phymod_access_t 52 #define _TRG_OPN(a) _TRGO_(a->addr, a->lane_mask) 53 #define _TRG_CLS(a) _TRGC_(a->addr, a->lane_mask) 54 #define _TRG_LANE(a) (a->lane_mask) 55 #endif 56 #ifdef _DV_TB_ 57 #define PHYMOD_ST temod_st 58 #define _TRG_OPN(a) _TRGO_(a->prt_ad, a->this_lane) 59 #define _TRG_CLS(a) _TRGC_(a->prt_ad, a->this_lane) 60 #define _TRG_LANE(a) (a->this_lane) 61 #endif 62 63 int temod_diag_link(PHYMOD_ST *pc); 64 int temod_diag_st(PHYMOD_ST *pc, int resolved_speed); 65 66 /** 67 @brief Field OVR diagnostic function 68 @param pc handle to current TSCE context (#PHYMOD_ST) 69 @returns PHYMOD_E_NONE 70 @details Field OVR Details 71 Check if the field OVR is set, and if OVR enabled, print the OVR value 72 */ 73 74 int temod_diag_field_or(PHYMOD_ST *pc) 75 { 76 SC_X4_FLD_OVRR_EN0_TYPEr_t field_or_0; 77 SC_X4_FLD_OVRR_EN1_TYPEr_t field_or_1; 78 SC_X4_LN_NUM_OVRRr_t num_lanes_or; 79 RX_X4_PMA_CTL0r_t os_or; 80 TX_X4_MISCr_t tx_misc_or; 81 TX_X4_ENC0r_t encode_or; 82 RX_X4_PCS_CTL0r_t rx_x4_pcs_ctrl_or; 83 RX_X2_MISC0r_t chk_end_or; 84 RX_X4_DEC_CTL0r_t blk_sync_or; 85 CL72_LNK_CTLr_t cl72_or; 86 RX_X4_CL36_RX0r_t cl36_or; 87 TX_X4_CRED0r_t crd_or; 88 TX_X4_CRED1r_t crd1_or; 89 TX_X4_LOOPCNTr_t loopcnt_or; 90 TX_X4_MAC_CREDGENCNTr_t mac_cgc_or; 91 TX_X4_PCS_CLKCNT0r_t pcs_crd_or; 92 TX_X4_PCS_CREDGENCNTr_t pcs_cgc_or; 93 94 READ_CL72_LNK_CTLr(pc,&cl72_or); 95 96 READ_SC_X4_FLD_OVRR_EN0_TYPEr(pc, &field_or_0); 97 READ_SC_X4_FLD_OVRR_EN1_TYPEr(pc, &field_or_1); 98 READ_SC_X4_LN_NUM_OVRRr(pc,&num_lanes_or); 99 100 READ_RX_X4_PMA_CTL0r(pc,&os_or); 101 READ_RX_X4_PCS_CTL0r(pc,&rx_x4_pcs_ctrl_or); 102 READ_RX_X2_MISC0r(pc,&chk_end_or); 103 READ_RX_X4_DEC_CTL0r(pc,&blk_sync_or); 104 READ_RX_X4_CL36_RX0r(pc,&cl36_or); 105 106 READ_TX_X4_MISCr(pc,&tx_misc_or); 107 READ_TX_X4_ENC0r(pc,&encode_or); 108 READ_TX_X4_CRED0r(pc,&crd_or); 109 READ_TX_X4_CRED1r(pc,&crd1_or); 110 READ_TX_X4_LOOPCNTr(pc,&loopcnt_or); 111 READ_TX_X4_MAC_CREDGENCNTr(pc,&mac_cgc_or); 112 READ_TX_X4_PCS_CLKCNT0r(pc,&pcs_crd_or); 113 READ_TX_X4_PCS_CREDGENCNTr(pc,&pcs_cgc_or); 114 115 PHYMOD_DEBUG_ERROR(("| OEN SET OVR VALUE |\n")); 116 PHYMOD_DEBUG_ERROR(("+----------------+----------------+--------------------------------------------+\n")); 117 PHYMOD_DEBUG_ERROR(("| NUM LANES: 0x%x | FEC ENA : 0x%X | |\n", 118 SC_X4_LN_NUM_OVRRr_NUM_LANES_OVERRIDE_VALUEf_GET(num_lanes_or), 119 TX_X4_MISCr_FEC_ENABLEf_GET(tx_misc_or))); 120 /* e2s_temod_os_mode_type[RX_X4_PMA_CTL0r_OS_MODEf_GET(os_or)]+6)); */ 121 122 PHYMOD_DEBUG_ERROR(("| 64B66DECR: 0x%x | CHKEND : 0x%X | %-43s|\n", 123 RX_X4_PCS_CTL0r_BRCM64B66_DESCRAMBLER_ENABLEf_GET(rx_x4_pcs_ctrl_or), 124 RX_X2_MISC0r_CHK_END_ENf_GET(chk_end_or), 125 e2s_temod_scr_mode[TX_X4_MISCr_SCR_MODEf_GET(tx_misc_or)]+6)); 126 127 PHYMOD_DEBUG_ERROR(("| FECENABL : 0x%x | REORDER : 0x%X | %-43s|\n", 128 CL72_LNK_CTLr_LINK_CONTROL_FORCEVALf_GET(cl72_or), 129 RX_X4_CL36_RX0r_REORDER_ENf_GET(cl36_or), 130 e2s_temod_encode_mode[TX_X4_ENC0r_ENCODEMODEf_GET(encode_or)]+6)); 131 132 PHYMOD_DEBUG_ERROR(("| CL36ENA : 0x%x | SGMIISPD : 0x%X | %-43s|\n", 133 RX_X4_CL36_RX0r_CL36_ENf_GET(cl36_or), 134 TX_X4_CRED0r_SGMII_SPD_SWITCHf_GET(crd_or), 135 e2s_temod_descrambler_mode[RX_X4_PCS_CTL0r_DESCRAMBLERMODEf_GET(rx_x4_pcs_ctrl_or)]+6)); 136 137 PHYMOD_DEBUG_ERROR(("| CLKCNT0 : 0x%x | CLKCNT1 : 0x%X | %-43s|\n", 138 TX_X4_CRED0r_CLOCKCNT0f_GET(crd_or), 139 TX_X4_CRED1r_CLOCKCNT1f_GET(crd1_or), 140 e2s_temod_decoder_mode[RX_X4_PCS_CTL0r_DECODERMODEf_GET(rx_x4_pcs_ctrl_or)]+6)); 141 142 PHYMOD_DEBUG_ERROR(("| LP CNT0 : 0x%x | LP CNT1 : 0x%X | %-43s|\n", 143 TX_X4_LOOPCNTr_LOOPCNT0f_GET(loopcnt_or), 144 TX_X4_LOOPCNTr_LOOPCNT1f_GET(loopcnt_or), 145 e2s_temod_deskew_mode[RX_X4_PCS_CTL0r_DESKEWMODEf_GET(rx_x4_pcs_ctrl_or)]+6)); 146 147 PHYMOD_DEBUG_ERROR(("| MACCRDGEN: 0x%x | REPLCNT : 0x%X | %-43s|\n", 148 TX_X4_MAC_CREDGENCNTr_MAC_CREDITGENCNTf_GET(mac_cgc_or), 149 TX_X4_PCS_CLKCNT0r_REPLICATION_CNTf_GET(pcs_crd_or), 150 e2s_temod_descrambler2_mode[RX_X4_PCS_CTL0r_DESC2_MODEf_GET(rx_x4_pcs_ctrl_or)]+6)); 151 152 PHYMOD_DEBUG_ERROR(("| PCSCRDENA: 0x%x | CLK CNT : 0x%X | %-43s|\n", 153 TX_X4_PCS_CLKCNT0r_PCS_CREDITENABLEf_GET(pcs_crd_or), 154 TX_X4_PCS_CLKCNT0r_PCS_CLOCKCNT0f_GET(pcs_crd_or), 155 e2s_temod_byte_del_mode[RX_X4_PCS_CTL0r_CL36BYTEDELETEMODEf_GET(rx_x4_pcs_ctrl_or)]+6)); 156 157 158 PHYMOD_DEBUG_ERROR(("| PCSCRDGEN: 0x%x | | %-43s|\n", 159 TX_X4_PCS_CREDGENCNTr_PCS_CREDITGENCNTf_GET(pcs_cgc_or), 160 e2s_temod_blocksync_mode[RX_X4_DEC_CTL0r_BLOCK_SYNC_MODEf_GET(blk_sync_or)]+6)); 161 162 /* 163 if(TSCE_FIELD_OVERRIDE_ENABLE1_TYPEr_CREDITENABLE_OENf_GET(field_or_1) == 1) { 164 PHYMOD_DEBUG_ERROR(("crediten_OEN set. ovr_value:0x%x\n", 165 TSCE_TX_X4_CREDIT0r_CREDITENABLEf_GET(crd_or))); 166 } 167 */ 168 169 PHYMOD_DEBUG_ERROR(("+----------------+--+-------------+------+------------------+------------------+\n")); 170 return PHYMOD_E_NONE; 171 } 172 173 /** 174 @brief pmd pcs lane cfg diagnostic function 175 @param pc handle to current TSCE context (#PHYMOD_ST) 176 @param lane The lane under consideration (TBD) 177 @returns PHYMOD_E_NONE 178 @details Get the uc controls for pmd lane cfg 179 Read the pcs_lane_cfg information from uc RAM. To check if the pmd is to be 180 programmed from pcs lane cfg. 181 */ 182 int temod_diag_pmd_pcs_lane_cfg(PHYMOD_ST *pc, int lane) 183 { 184 return PHYMOD_E_NONE; 185 } /* temod_diag_pmd_pcs_lane_cfg */ 186 187 /** 188 @brief Speed diagnostic function 189 @param pc handle to current TSCE context (#PHYMOD_ST) 190 @returns PHYMOD_E_NONE 191 @details Speed Details 192 1. Get the Speed set 193 2. Get the Speed valis and Speed Done Status 194 3. Get the final stats of the speed 195 */ 196 int temod_diag_speed(PHYMOD_ST *pc) 197 { 198 SC_X4_STSr_t sc_ctrl_status; 199 SC_X4_RSLVD_SPDr_t sc_final_resolved_speed; 200 SC_X4_RSLVD0r_t sc_final_resolved_0; 201 SC_X4_RSLVD1r_t sc_final_resolved_1; 202 SC_X4_RSLVD2r_t sc_final_resolved_2; 203 SC_X4_RSLVD3r_t sc_final_resolved_3; 204 SC_X4_RSLVD4r_t sc_final_resolved_4; 205 SC_X4_RSLVD5r_t sc_final_resolved_5; 206 SC_X4_RSLVD6r_t sc_final_resolved_6; 207 SC_X4_RSLVD7r_t sc_final_resolved_7; 208 SC_X4_RSLVD8r_t sc_final_resolved_8; 209 MAIN0_SETUPr_t setup_reg; 210 PLL_CAL_CTL7r_t pll_div_reg; 211 CKRST_OSR_MODE_CTLr_t reg_osr_mode; 212 213 PHYMOD_DEBUG_ERROR(("| TRG ADR : %06d LANE: %02d SPEED |\n", pc->addr, pc->lane_mask)); 214 PHYMOD_DEBUG_ERROR(("+---------------------+-----------------------------+-----------+--------------+\n")); 215 216 /*1. Get the Speed valid and Speed Done Status */ 217 READ_SC_X4_STSr(pc,&sc_ctrl_status); 218 219 /*2. Get the Speed set */ 220 /*2a PLLDIV and the refclk settings */ 221 READ_SC_X4_RSLVD_SPDr(pc,&sc_final_resolved_speed); 222 READ_MAIN0_SETUPr(pc,&setup_reg); 223 READ_PLL_CAL_CTL7r(pc,&pll_div_reg); 224 READ_CKRST_OSR_MODE_CTLr(pc, ®_osr_mode); 225 226 /*2b Check if the Speed id is existent in ST */ 227 temod_diag_st(pc, SC_X4_RSLVD_SPDr_SPEEDf_GET(sc_final_resolved_speed)); 228 temod_diag_field_or(pc); 229 230 /*3. Get the final stats for the speed */ 231 READ_SC_X4_RSLVD0r(pc,&sc_final_resolved_0); 232 READ_SC_X4_RSLVD2r(pc,&sc_final_resolved_2); 233 234 235 READ_SC_X4_RSLVD1r(pc,&sc_final_resolved_1); 236 237 READ_SC_X4_RSLVD3r(pc,&sc_final_resolved_3); 238 READ_SC_X4_RSLVD4r(pc,&sc_final_resolved_4); 239 READ_SC_X4_RSLVD5r(pc,&sc_final_resolved_5); 240 READ_SC_X4_RSLVD6r(pc,&sc_final_resolved_6); 241 READ_SC_X4_RSLVD7r(pc,&sc_final_resolved_7); 242 READ_SC_X4_RSLVD8r(pc,&sc_final_resolved_8); 243 244 245 PHYMOD_DEBUG_ERROR(("| SPEED | STATS0 | STATS1 | CREDIT STATS |\n")); 246 PHYMOD_DEBUG_ERROR(("+-------------------+--------------------+------------------+------------------+\n")); 247 PHYMOD_DEBUG_ERROR(("| SPD CHG VLD %d | OS MODE %-6s | DESCR MODE %-6s| SGMII SPD : %04d |\n", 248 SC_X4_STSr_SW_SPEED_CONFIG_VLDf_GET(sc_ctrl_status), 249 e2s_temod_os_mode_type[CKRST_OSR_MODE_CTLr_OSR_MODE_FRC_VALf_GET(reg_osr_mode)]+18, 250 e2s_temod_descrambler_mode[SC_X4_RSLVD1r_DESCRAMBLERMODEf_GET(sc_final_resolved_1)]+20, 251 SC_X4_RSLVD3r_SGMII_SPD_SWITCHf_GET(sc_final_resolved_3))); 252 253 PHYMOD_DEBUG_ERROR(("| SPD CHG DONE %d | SCR MODE %-6s |DECODE MODE %-6s| CLK CNT0 : %04d |\n", 254 SC_X4_STSr_SW_SPEED_CHANGE_DONEf_GET(sc_ctrl_status), 255 e2s_temod_scr_mode[SC_X4_RSLVD0r_SCR_MODEf_GET(sc_final_resolved_0)]+15, 256 e2s_temod_decoder_mode[SC_X4_RSLVD1r_DECODERMODEf_GET(sc_final_resolved_1)]+19, 257 SC_X4_RSLVD3r_CLOCKCNT0f_GET(sc_final_resolved_3))); 258 259 PHYMOD_DEBUG_ERROR(("| SPD RESOLVED %04d | ENC MODE %-6s |DESKEW MODE %-6s| CLK CNT1 : %04d |\n", 260 SC_X4_RSLVD_SPDr_SPEEDf_GET(sc_final_resolved_speed), 261 e2s_temod_encode_mode[SC_X4_RSLVD0r_ENCODEMODEf_GET(sc_final_resolved_0)]+18, 262 e2s_temod_deskew_mode[SC_X4_RSLVD1r_DESKEWMODEf_GET(sc_final_resolved_1)]+20, 263 SC_X4_RSLVD4r_CLOCKCNT1f_GET(sc_final_resolved_4))); 264 265 PHYMOD_DEBUG_ERROR(("| #LN RESOLVED %04d |BLKSYNC MODE %-6s |DESCR2 MODE %-6s| LP CNT0 : %04d |\n", 266 SC_X4_RSLVD_SPDr_NUM_LANESf_GET(sc_final_resolved_speed), 267 e2s_temod_blocksync_mode[SC_X4_RSLVD2r_BLOCK_SYNC_MODEf_GET(sc_final_resolved_2)]+21, 268 e2s_temod_descrambler2_mode[SC_X4_RSLVD1r_DESC2_MODEf_GET(sc_final_resolved_1)]+17, 269 SC_X4_RSLVD5r_LOOPCNT0f_GET(sc_final_resolved_5))); 270 271 PHYMOD_DEBUG_ERROR(("| PLL DIV %04d | CL72 ENA : %02d | BYTE DEL %-6s| LP CNT1 : %04d |\n", 272 PLL_CAL_CTL7r_PLL_MODEf_GET(pll_div_reg), 273 SC_X4_RSLVD0r_CL72_ENABLEf_GET(sc_final_resolved_0), 274 e2s_temod_byte_del_mode[SC_X4_RSLVD1r_CL36BYTEDELETEMODEf_GET(sc_final_resolved_1)]+28, 275 SC_X4_RSLVD5r_LOOPCNT1f_GET(sc_final_resolved_5))); 276 277 PHYMOD_DEBUG_ERROR(("| REF CLOCK %04d | CHKEND ENA : %02d |64b66DEC EN %d | MAC CGC : %04d |\n", 278 MAIN0_SETUPr_REFCLK_SELf_GET(setup_reg), 279 SC_X4_RSLVD2r_CHK_END_ENf_GET(sc_final_resolved_2), 280 SC_X4_RSLVD1r_BRCM64B66_DESCRAMBLER_ENABLEf_GET(sc_final_resolved_1), 281 SC_X4_RSLVD6r_MAC_CREDITGENCNTf_GET(sc_final_resolved_6))); 282 283 PHYMOD_DEBUG_ERROR(("| | FEC ENA : %02d | | REP CNT : %04d |\n", 284 SC_X4_RSLVD0r_FEC_ENABLEf_GET(sc_final_resolved_0), 285 SC_X4_RSLVD7r_REPLICATION_CNTf_GET(sc_final_resolved_7))); 286 287 PHYMOD_DEBUG_ERROR(("| |REORDER ENA : %02d | |PCS CRD EN : %04d |\n", 288 SC_X4_RSLVD2r_REORDER_ENf_GET(sc_final_resolved_2), 289 SC_X4_RSLVD7r_PCS_CREDITENABLEf_GET(sc_final_resolved_7))); 290 291 PHYMOD_DEBUG_ERROR(("| | CL36 ENA : %02d | |PCS CK CNT : %04d |\n", 292 SC_X4_RSLVD2r_CL36_ENf_GET(sc_final_resolved_2), 293 SC_X4_RSLVD7r_PCS_CLOCKCNT0f_GET(sc_final_resolved_7))); 294 295 PHYMOD_DEBUG_ERROR(("| | | |CRDGEN CNT : %04d |\n", 296 SC_X4_RSLVD8r_PCS_CREDITGENCNTf_GET(sc_final_resolved_8))); 297 298 299 PHYMOD_DEBUG_ERROR(("+-------------------+--------------------+------------------+------------------+\n")); 300 301 return PHYMOD_E_NONE; 302 } 303 304 /** 305 @brief Autoneg Ability diagnostic function 306 @param pc handle to current TSCE context (#PHYMOD_ST) 307 @returns PHYMOD_E_NONE 308 @details Autoneg diags 309 1. Get the AN Abilities for CL37 and CL73 310 */ 311 int temod_diag_autoneg_abilities(PHYMOD_ST *pc) 312 { 313 AN_X4_ENSr_t an_ena; 314 AN_X4_LOC_DEV_CL37_BASE_ABILr_t cl37_base; 315 AN_X4_LOC_DEV_CL37_BAM_ABILr_t cl37_bam; 316 AN_X4_LOC_DEV_OVER1G_ABIL0r_t over1g; 317 AN_X4_LOC_DEV_OVER1G_ABIL1r_t over1g1; 318 AN_X4_LOC_DEV_CL73_BAM_ABILr_t cl73_bam; 319 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_t cl73_base_0; 320 AN_X4_LOC_DEV_CL73_BASE_ABIL1r_t cl73_base_1; 321 AN_X4_CTLSr_t an_ctrl; 322 uint16_t sgmii_spd, lanes, base_sel; 323 324 READ_AN_X4_ENSr (pc, &an_ena); 325 READ_AN_X4_LOC_DEV_CL37_BASE_ABILr (pc, &cl37_base); 326 READ_AN_X4_LOC_DEV_CL37_BAM_ABILr (pc, &cl37_bam); 327 READ_AN_X4_LOC_DEV_OVER1G_ABIL0r (pc, &over1g); 328 READ_AN_X4_LOC_DEV_OVER1G_ABIL1r (pc, &over1g1); 329 READ_AN_X4_LOC_DEV_CL73_BAM_ABILr (pc, &cl73_bam); 330 READ_AN_X4_LOC_DEV_CL73_BASE_ABIL0r (pc, &cl73_base_0); 331 READ_AN_X4_LOC_DEV_CL73_BASE_ABIL1r (pc, &cl73_base_1); 332 READ_AN_X4_CTLSr (pc, &an_ctrl); 333 334 PHYMOD_DEBUG_ERROR(("+-------------------+-------+------+-----------------------+-------------------+\n")); 335 PHYMOD_DEBUG_ERROR(("| ANX4 CTRL: 0x%04X | ENS : 0x%04X | CL37 BAM:0x%04X BASE :0x%04X |\n", 336 AN_X4_CTLSr_GET(an_ctrl), AN_X4_ENSr_GET(an_ena), 337 AN_X4_LOC_DEV_CL37_BAM_ABILr_GET(cl37_bam), AN_X4_LOC_DEV_CL37_BASE_ABILr_GET(cl37_base))); 338 339 PHYMOD_DEBUG_ERROR(("| ANX4 OVR0: 0x%04X | OVR1: 0x%04X | CL73 BAM:0x%04X BASE1:0x%04X BASE0:0x%04X |\n", 340 AN_X4_LOC_DEV_OVER1G_ABIL0r_GET(over1g), AN_X4_LOC_DEV_OVER1G_ABIL1r_GET(over1g1), 341 AN_X4_LOC_DEV_CL73_BAM_ABILr_GET(cl73_bam), AN_X4_LOC_DEV_CL73_BASE_ABIL0r_GET(cl73_base_0), 342 AN_X4_LOC_DEV_CL73_BASE_ABIL1r_GET(cl73_base_1))); 343 344 lanes = AN_X4_ENSr_NUM_ADVERTISED_LANESf_GET(an_ena); 345 PHYMOD_DEBUG_ERROR(("+-------------------+--------------+----+--------------------------------------+\n")); 346 PHYMOD_DEBUG_ERROR(("| CLAUSE 37 | CLAUSE 73 | |\n")); 347 PHYMOD_DEBUG_ERROR(("+-------------------+-------------------+--------------------------------------+\n")); 348 PHYMOD_DEBUG_ERROR(("| BAM ENA : %d | BAM ENA : %d | NUM ADV LANES : %d |\n", 349 AN_X4_ENSr_CL37_BAM_ENABLEf_GET(an_ena), 350 AN_X4_ENSr_CL73_BAM_ENABLEf_GET(an_ena), 351 (lanes == 0? 1 : (lanes == 1? 2 : (lanes == 3? 10 : 1))))); 352 353 PHYMOD_DEBUG_ERROR(("| AN ENA : %d | AN ENA : %d | FAIL COUNT LIM: %d |\n", 354 AN_X4_ENSr_CL37_ENABLEf_GET(an_ena), 355 AN_X4_ENSr_CL73_ENABLEf_GET(an_ena), 356 AN_X4_CTLSr_AN_FAIL_COUNT_LIMITf_GET(an_ctrl))); 357 358 PHYMOD_DEBUG_ERROR(("| SGMII ENA : %d | HPAM ENA : %d | |\n", 359 AN_X4_ENSr_CL37_SGMII_ENABLEf_GET(an_ena), 360 AN_X4_ENSr_CL73_HPAM_ENABLEf_GET(an_ena))); 361 362 PHYMOD_DEBUG_ERROR(("| BAM2SGMII ENA : %d | BAM3HPAM ENA : %d | |\n", 363 AN_X4_ENSr_CL37_BAM_TO_SGMII_AUTO_ENABLEf_GET(an_ena), 364 AN_X4_ENSr_CL73_BAM_TO_HPAM_AUTO_ENABLEf_GET(an_ena))); 365 366 PHYMOD_DEBUG_ERROR(("| SGMII2CL37 ENA: %d | HPAM2CL73 ENA: %d | |\n", 367 AN_X4_ENSr_SGMII_TO_CL37_AUTO_ENABLEf_GET(an_ena), 368 AN_X4_ENSr_HPAM_TO_CL73_AUTO_ENABLEf_GET(an_ena))); 369 370 PHYMOD_DEBUG_ERROR(("| AN RESTART : %d | AN RESTART : %d | |\n", 371 AN_X4_ENSr_CL37_AN_RESTARTf_GET(an_ena), 372 AN_X4_ENSr_CL73_AN_RESTARTf_GET(an_ena))); 373 374 sgmii_spd = AN_X4_LOC_DEV_CL37_BASE_ABILr_SGMII_SPEEDf_GET(cl37_base); 375 base_sel = AN_X4_LOC_DEV_CL73_BASE_ABIL1r_BASE_SELECTORf_GET(cl73_base_1); 376 377 PHYMOD_DEBUG_ERROR(("+-------------------+-------------------+--------------------------------------+\n")); 378 PHYMOD_DEBUG_ERROR(("| CL37 ABILITIES | CL73 ABILITIES |\n")); 379 PHYMOD_DEBUG_ERROR(("+---------------+-----------------------+-----------------+--------------------+\n")); 380 PHYMOD_DEBUG_ERROR(("| SWRST DIS : %d | ANRST DIS :%d | NONCE OVR : %d | NONCE VAL: %d |\n", 381 AN_X4_LOC_DEV_CL37_BASE_ABILr_CL37_SW_RESTART_RESET_DISABLEf_GET(cl37_base), 382 AN_X4_LOC_DEV_CL37_BASE_ABILr_CL37_AN_RESTART_RESET_DISABLEf_GET(cl37_base), 383 AN_X4_LOC_DEV_CL73_BASE_ABIL1r_CL73_NONCE_MATCH_OVERf_GET(cl73_base_1), 384 AN_X4_LOC_DEV_CL73_BASE_ABIL1r_CL73_NONCE_MATCH_VALf_GET(cl73_base_1))); 385 386 PHYMOD_DEBUG_ERROR(("| PD 2 CL37 : %d | NEXT PAGE :%d | TX NONCE : 0x%X| BASE SEL : %-7s |\n", 387 AN_X4_LOC_DEV_CL37_BASE_ABILr_AN_PD_TO_CL37_ENABLEf_GET(cl37_base), 388 AN_X4_LOC_DEV_CL37_BASE_ABILr_CL37_NEXT_PAGEf_GET(cl37_base), 389 AN_X4_LOC_DEV_CL73_BASE_ABIL1r_TRANSMIT_NONCEf_GET(cl73_base_1), 390 (base_sel == 0? "Rsvd" : 391 (base_sel == 1? "802.3" : 392 (base_sel == 2? "802.9" : 393 (base_sel == 3? "802.5": 394 (base_sel == 4? "1394": "UNKNOWN"))))) )); 395 396 PHYMOD_DEBUG_ERROR(("| HALF DUPLX: %d | FULL DUPLEX :%d | NEXT PAGE : %d | FEC : %d |\n", 397 AN_X4_LOC_DEV_CL37_BASE_ABILr_CL37_FULL_DUPLEXf_GET(cl37_base), 398 AN_X4_LOC_DEV_CL37_BASE_ABILr_CL37_HALF_DUPLEXf_GET(cl37_base), 399 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_NEXT_PAGEf_GET(cl73_base_0), 400 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_FECf_GET(cl73_base_0))); 401 402 PHYMOD_DEBUG_ERROR(("| PAUSE : %d | SGMII MASTER :%d | REMOTE FLT : %d | PAUSE : %d |\n", 403 AN_X4_LOC_DEV_CL37_BASE_ABILr_CL37_PAUSEf_GET(cl37_base), 404 AN_X4_LOC_DEV_CL37_BASE_ABILr_SGMII_MASTER_MODEf_GET(cl37_base), 405 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_CL73_REMOTE_FAULTf_GET(cl73_base_0), 406 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_CL73_PAUSEf_GET(cl73_base_0))); 407 408 PHYMOD_DEBUG_ERROR(("| SGMII FDUP: %d | SGMII SPD :%-7s |-----------------+--------------------|\n", 409 AN_X4_LOC_DEV_CL37_BASE_ABILr_SGMII_FULL_DUPLEXf_GET(cl37_base), 410 (sgmii_spd == 0? "10Mb/s" : 411 (sgmii_spd == 1? "100Mb/s": 412 (sgmii_spd == 2? "1Gb/s" : "Rsvd"))) )); 413 414 PHYMOD_DEBUG_ERROR(("| OVR1G ABIL: %d | OVR1G PAGECNT:%d | 1000BASE KX : %d | 10GBASE KX4 :%d |\n", 415 AN_X4_LOC_DEV_CL37_BAM_ABILr_OVER1G_ABILITYf_GET(cl37_bam), 416 AN_X4_LOC_DEV_CL37_BAM_ABILr_OVER1G_PAGE_COUNTf_GET(cl37_bam), 417 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_BASE_1000BASE_KXf_GET(cl73_base_0), 418 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_BASE_10GBASE_KX4f_GET(cl73_base_0))); 419 420 PHYMOD_DEBUG_ERROR(("| BAM CODE : 0x%04X | 10GBASE KR : %d | 10GBASE KR4 :%d |\n", 421 AN_X4_LOC_DEV_CL37_BAM_ABILr_CL37_BAM_CODEf_GET(cl37_bam), 422 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_BASE_10GBASE_KRf_GET(cl73_base_0), 423 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_BASE_40GBASE_KR4f_GET(cl73_base_0))); 424 425 PHYMOD_DEBUG_ERROR(("|---------------+-----------------------| 40GBASE CR4 : %d | 100GBASE CR1:%d |\n", 426 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_BASE_40GBASE_CR4f_GET(cl73_base_0), 427 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_BASE_100GBASE_CR10f_GET(cl73_base_0))); 428 429 PHYMOD_DEBUG_ERROR(("| | HPAM_20GKR2 : %d | BAM CODE :0x%04X|\n", 430 AN_X4_LOC_DEV_CL73_BAM_ABILr_HPAM_20GKR2f_GET(cl73_bam), 431 AN_X4_LOC_DEV_CL73_BAM_ABILr_CL73_BAM_CODEf_GET(cl73_bam))); 432 433 PHYMOD_DEBUG_ERROR(("| | 20GBASE CR2 : %d | 20GBASE KR2 : %d |\n", 434 AN_X4_LOC_DEV_CL73_BAM_ABILr_BAM_20GBASE_CR2f_GET(cl73_bam), 435 AN_X4_LOC_DEV_CL73_BAM_ABILr_BAM_20GBASE_KR2f_GET(cl73_bam))); 436 437 PHYMOD_DEBUG_ERROR(("+---------------------------------------+--------------------------------------+\n")); 438 PHYMOD_DEBUG_ERROR(("| OVER1G ABILITIES |\n")); 439 PHYMOD_DEBUG_ERROR(("+-------------------+--------------------+-----------------+-------------------+\n")); 440 PHYMOD_DEBUG_ERROR(("| HG2 : %d | FEC : %d | CL72 : %d| |\n", 441 AN_X4_LOC_DEV_OVER1G_ABIL1r_HG2f_GET(over1g1), 442 AN_X4_LOC_DEV_OVER1G_ABIL1r_FECf_GET(over1g1), 443 AN_X4_LOC_DEV_OVER1G_ABIL1r_CL72f_GET(over1g1))); 444 445 PHYMOD_DEBUG_ERROR(("| 40GBASE X4 : %d | 32P7GBASE X4 : %d | 31P5GBASE X4 : %d| 25P455GBASE X4: %d |\n", 446 AN_X4_LOC_DEV_OVER1G_ABIL1r_BAM_40GBASE_X4f_GET(over1g1), 447 AN_X4_LOC_DEV_OVER1G_ABIL1r_BAM_32P7GBASE_X4f_GET(over1g1), 448 AN_X4_LOC_DEV_OVER1G_ABIL1r_BAM_31P5GBASE_X4f_GET(over1g1), 449 AN_X4_LOC_DEV_OVER1G_ABIL1r_BAM_25P455GBASE_X4f_GET(over1g1))); 450 451 PHYMOD_DEBUG_ERROR(("| 21GBASE X4 : %d | 20GBASEX2 CX4: %d | 20GBASE X2 : %d| 20GBASE X4 : %d |\n", 452 AN_X4_LOC_DEV_OVER1G_ABIL1r_BAM_21GBASE_X4f_GET(over1g1), 453 AN_X4_LOC_DEV_OVER1G_ABIL1r_BAM_20GBASE_X2_CX4f_GET(over1g1), 454 AN_X4_LOC_DEV_OVER1G_ABIL1r_BAM_20GBASE_X2f_GET(over1g1), 455 AN_X4_LOC_DEV_OVER1G_ABIL1r_BAM_20GBASE_X4f_GET(over1g1))); 456 457 PHYMOD_DEBUG_ERROR(("| 16GBASE X4 : %d | 15P75GBASE X2: %d | 15GBASE X4 : %d| 13GBASE X4 : %d |\n", 458 AN_X4_LOC_DEV_OVER1G_ABIL1r_BAM_16GBASE_X4f_GET(over1g1), 459 AN_X4_LOC_DEV_OVER1G_ABIL1r_BAM_15P75GBASE_X2f_GET(over1g1), 460 AN_X4_LOC_DEV_OVER1G_ABIL1r_BAM_15GBASE_X4f_GET(over1g1), 461 AN_X4_LOC_DEV_OVER1G_ABIL1r_BAM_13GBASE_X4f_GET(over1g1))); 462 463 return PHYMOD_E_NONE; 464 } 465 466 int tempd_an_hcd_spd_get (uint16_t spd, char *mystr, int len) 467 { 468 char *an_spd = "UNDEF"; 469 470 if (spd == 1) an_spd ="10M"; 471 if (spd == 2) an_spd ="100M"; 472 if (spd == 3) an_spd ="1000M"; 473 if (spd == 4) an_spd ="1G_CX1"; 474 if (spd == 5) an_spd ="1G_KX1"; 475 if (spd == 6) an_spd ="2p5G_X1"; 476 if (spd == 7) an_spd ="5G_X1"; 477 if (spd == 8) an_spd ="10G_CX4"; 478 if (spd == 9) an_spd ="10G_KX4"; 479 if (spd == 0xa) an_spd ="10G_X4"; 480 if (spd == 0xb) an_spd ="13G_X4"; 481 if (spd == 0xc) an_spd ="15G_X4"; 482 if (spd == 0xd) an_spd ="16G_X4"; 483 if (spd == 0xe) an_spd ="20G_CX4"; 484 if (spd == 0xf) an_spd ="10G_CX2"; 485 if (spd == 0x10) an_spd ="10G_X2"; 486 if (spd == 0x11) an_spd ="20G_X4"; 487 if (spd == 0x12) an_spd ="10p5G_X2"; 488 if (spd == 0x13) an_spd ="21G_X4"; 489 if (spd == 0x14) an_spd ="12p7G_X2"; 490 if (spd == 0x15) an_spd ="25p45G_X4"; 491 if (spd == 0x16) an_spd ="15p75G_X2"; 492 if (spd == 0x17) an_spd ="31P5G_X4"; 493 if (spd == 0x18) an_spd ="31p5G_KR4"; 494 if (spd == 0x19) an_spd ="20G_CX2"; 495 if (spd == 0x1a) an_spd ="20G_X2"; 496 if (spd == 0x1b) an_spd ="40G_X4"; 497 if (spd == 0x1c) an_spd ="10G_KR1"; 498 if (spd == 0x1d) an_spd ="10p6_X1"; 499 if (spd == 0x1e) an_spd ="20G_KR2"; 500 if (spd == 0x1f) an_spd ="20G_CR2"; 501 if (spd == 0x20) an_spd ="21G_X2"; 502 if (spd == 0x21) an_spd ="40G_KR4"; 503 if (spd == 0x22) an_spd ="40G_CR4"; 504 if (spd == 0x23) an_spd ="42G_X4"; 505 if (spd == 0x24) an_spd ="100G_CR10"; 506 if (spd == 0x25) an_spd ="107G_X10"; 507 if (spd == 0x26) an_spd ="120G_X12"; 508 if (spd == 0x27) an_spd ="127G_X12"; 509 if (spd == 0x31) an_spd ="5G_KR1"; 510 if (spd == 0x32) an_spd ="10p5G_X4"; 511 if (spd == 0x35) an_spd ="10M_10p3125"; 512 if (spd == 0x36) an_spd ="100M_10p3125"; 513 if (spd == 0x37) an_spd ="1000M_10p3125"; 514 if (spd == 0x38) an_spd ="2p5G_X1_10p3125"; 515 516 PHYMOD_STRNCPY(mystr, an_spd, len); 517 518 return PHYMOD_E_NONE; 519 } 520 /** 521 @brief Autoneg diagnostic function 522 @param pc handle to current TSCE context (#PHYMOD_ST) 523 @returns PHYMOD_E_NONE 524 @details Autoneg diags 525 1. Get the AN complete status for AN37/73 526 2. Get the resolved HCD 527 3. Get the link up status after AN 528 */ 529 int temod_diag_autoneg(PHYMOD_ST *pc) 530 { 531 AN_X4_AN_PAGE_SEQUENCER_STSr_t an_page_seq_status; 532 AN_X4_AN_ABIL_RESOLUTION_STSr_t an_hcd_status; 533 AN_X4_AN_MISC_STSr_t an_misc_status; 534 char an_spd[16]; 535 536 READ_AN_X4_AN_PAGE_SEQUENCER_STSr(pc,&an_page_seq_status); 537 READ_AN_X4_AN_ABIL_RESOLUTION_STSr(pc,&an_hcd_status); 538 READ_AN_X4_AN_MISC_STSr(pc,&an_misc_status); 539 tempd_an_hcd_spd_get (AN_X4_AN_ABIL_RESOLUTION_STSr_AN_HCD_SPEEDf_GET(an_hcd_status), an_spd, sizeof(an_spd)); 540 541 PHYMOD_DEBUG_ERROR(("| TRG ADR : %06d LANE: %02d AUTONEG |\n", 542 pc->addr, pc->lane_mask)); 543 PHYMOD_DEBUG_ERROR(("+-------------+-------------+------------------------------+-------------------+\n")); 544 PHYMOD_DEBUG_ERROR(("| AN37: %c | AN73 : %c | AN HCD SPD : %-16s| AN LINK : %s |\n", 545 (AN_X4_AN_PAGE_SEQUENCER_STSr_AN_ST_CL37_COMPLETEf_GET(an_page_seq_status) == 1) ? 'Y' : 'N', 546 (AN_X4_AN_PAGE_SEQUENCER_STSr_AN_ST_CL73_COMPLETEf_GET(an_page_seq_status) == 1) ? 'Y' : 'N', an_spd, 547 (((AN_X4_AN_PAGE_SEQUENCER_STSr_AN_ST_CL73_COMPLETEf_GET(an_page_seq_status) == 1) || 548 (AN_X4_AN_PAGE_SEQUENCER_STSr_AN_ST_CL37_COMPLETEf_GET(an_page_seq_status) == 1)) && 549 (AN_X4_AN_MISC_STSr_AN_COMPLETEf_GET(an_misc_status) == 1))? "UP":"DN")); 550 551 temod_diag_autoneg_abilities(pc); 552 PHYMOD_DEBUG_ERROR(("+-------------------+--------------------+-----------------+-------------------+\n")); 553 554 return PHYMOD_E_NONE; 555 } 556 557 /** 558 @brief Topology diagnostic function. 559 @param pc handle to current TSCE context (#PHYMOD_ST) 560 @returns PHYMOD_E_NONE 561 @details Get the topology details 562 1. LoopBack 563 a. Remote Loopback - RX loopback 564 i. PCS loopback 565 ii. PMD loopback //Not tested in TSCE 566 b. Local loopback/gloop - TX loopback 567 i. PCS loopback 568 ii. PMD loopback 569 2. LaneSwap 570 a. PCS LaneSwap(RX) 571 b. PMD LaneSwap(TX) 572 3. Polarity Inversion 573 a. tx 574 b. rx 575 4. Master PortNum, port mode and single port mode 576 */ 577 578 int temod_diag_topology(PHYMOD_ST *pc) 579 { 580 MAIN0_LPBK_CTLr_t pcs_loopback_ctrl; 581 TLB_RX_DIG_LPBK_CFGr_t pmd_loopback_dig; 582 TLB_TX_RMT_LPBK_CFGr_t pmd_loopback_remote; 583 MAIN0_LN_SWPr_t pcs_lane_swap; 584 DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r_t pmd_lane_addr_swap_1; 585 DIG_LN_ADDR_2_3r_t pmd_lane_addr_swap_2; 586 DIG_TX_LN_MAP_0_1_2r_t pmd_lane_addr_swap_3; 587 TLB_TX_TLB_TX_MISC_CFGr_t tx_pol_inv; 588 TLB_RX_TLB_RX_MISC_CFGr_t rx_pol_inv; 589 MAIN0_SETUPr_t reg_main0_setup; 590 591 /* Main0 Setup Register */ 592 /*1. Loopback */ 593 READ_MAIN0_LPBK_CTLr(pc, &pcs_loopback_ctrl); 594 READ_TLB_RX_DIG_LPBK_CFGr(pc, &pmd_loopback_dig); 595 READ_TLB_TX_RMT_LPBK_CFGr(pc, &pmd_loopback_remote); 596 597 /*2. LaneSwap */ 598 READ_MAIN0_LN_SWPr(pc, &pcs_lane_swap); 599 READ_DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r(pc, &pmd_lane_addr_swap_1); 600 READ_DIG_LN_ADDR_2_3r(pc, &pmd_lane_addr_swap_2); 601 READ_DIG_TX_LN_MAP_0_1_2r(pc, &pmd_lane_addr_swap_3); 602 603 /*3.Polarity Inversion */ 604 READ_TLB_TX_TLB_TX_MISC_CFGr(pc, &tx_pol_inv); 605 READ_TLB_RX_TLB_RX_MISC_CFGr(pc, &rx_pol_inv); 606 607 /* 4. Master PortNum, port mode abd single port mode */ 608 READ_MAIN0_SETUPr(pc, ®_main0_setup); 609 610 611 /* Print the information here */ 612 { 613 uint16_t pcs_lcl_lb, pcs_rmt_lb, pmd_dig_lb, pmd_rmt_lb; 614 pcs_lcl_lb = MAIN0_LPBK_CTLr_LOCAL_PCS_LOOPBACK_ENABLEf_GET(pcs_loopback_ctrl); 615 pcs_rmt_lb = MAIN0_LPBK_CTLr_REMOTE_PCS_LOOPBACK_ENABLEf_GET(pcs_loopback_ctrl); 616 pmd_dig_lb = TLB_RX_DIG_LPBK_CFGr_DIG_LPBK_ENf_GET(pmd_loopback_dig); 617 pmd_rmt_lb = TLB_TX_RMT_LPBK_CFGr_RMT_LPBK_ENf_GET(pmd_loopback_remote); 618 619 PHYMOD_DEBUG_ERROR(("\n")); 620 PHYMOD_DEBUG_ERROR(("+------------------------------------------------------------------------------+\n")); 621 PHYMOD_DEBUG_ERROR(("| TRG ADR : %06d LANE: %02d TOPOLOGY |\n", pc->addr, pc->lane_mask)); 622 PHYMOD_DEBUG_ERROR(("+-------------------+--------------------------+---------------+---------------+\n")); 623 PHYMOD_DEBUG_ERROR(("| PCSLCL LPBK: %c%c%c%c | PCS LANE SWAP L2P : %d%d%d%d | TX POLARITY : %d | PORT NUM : %d|\n", 624 (pcs_lcl_lb & 8) ? 'Y':'N', 625 (pcs_lcl_lb & 4) ? 'Y':'N', 626 (pcs_lcl_lb & 2) ? 'Y':'N', 627 (pcs_lcl_lb & 1) ? 'Y':'N', 628 MAIN0_LN_SWPr_LOG3_TO_PHY_LNSWAP_SELf_GET(pcs_lane_swap), 629 MAIN0_LN_SWPr_LOG2_TO_PHY_LNSWAP_SELf_GET(pcs_lane_swap), 630 MAIN0_LN_SWPr_LOG1_TO_PHY_LNSWAP_SELf_GET(pcs_lane_swap), 631 MAIN0_LN_SWPr_LOG0_TO_PHY_LNSWAP_SELf_GET(pcs_lane_swap), 632 TLB_TX_TLB_TX_MISC_CFGr_TX_PMD_DP_INVERTf_GET(tx_pol_inv), 633 MAIN0_SETUPr_MASTER_PORT_NUMf_GET(reg_main0_setup))); 634 635 PHYMOD_DEBUG_ERROR(("| PCSRMT LPBK: %c%c%c%c | PMD LANE ADDR IDX : %d%d%d%d | | SNGLMODE : %d|\n", 636 (pcs_rmt_lb & 8) ? 'Y':'N', 637 (pcs_rmt_lb & 4) ? 'Y':'N', 638 (pcs_rmt_lb & 2) ? 'Y':'N', 639 (pcs_rmt_lb & 1) ? 'Y':'N', 640 DIG_LN_ADDR_2_3r_LANE_ADDR_3f_GET(pmd_lane_addr_swap_2), 641 DIG_LN_ADDR_2_3r_LANE_ADDR_2f_GET(pmd_lane_addr_swap_2), 642 DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r_LANE_ADDR_1f_GET(pmd_lane_addr_swap_1), 643 DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r_LANE_ADDR_0f_GET(pmd_lane_addr_swap_1), 644 MAIN0_SETUPr_SINGLE_PORT_MODEf_GET(reg_main0_setup))); 645 646 PHYMOD_DEBUG_ERROR(("| PMDDIG LPBK: %c%c%c%c | PMD TO AFE : %d%d%d%d | RX POLARITY : %d | PORT MODE: %d|\n", 647 (pmd_dig_lb & 8) ? 'Y':'N', 648 (pmd_dig_lb & 4) ? 'Y':'N', 649 (pmd_dig_lb & 2) ? 'Y':'N', 650 (pmd_dig_lb & 1) ? 'Y':'N', 651 DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r_TX_LANE_MAP_3f_GET(pmd_lane_addr_swap_1), 652 DIG_TX_LN_MAP_0_1_2r_TX_LANE_MAP_2f_GET(pmd_lane_addr_swap_3), 653 DIG_TX_LN_MAP_0_1_2r_TX_LANE_MAP_1f_GET(pmd_lane_addr_swap_3), 654 DIG_TX_LN_MAP_0_1_2r_TX_LANE_MAP_0f_GET(pmd_lane_addr_swap_3), 655 TLB_RX_TLB_RX_MISC_CFGr_RX_PMD_DP_INVERTf_GET(rx_pol_inv), 656 MAIN0_SETUPr_PORT_MODE_SELf_GET(reg_main0_setup))); 657 658 PHYMOD_DEBUG_ERROR(("| PMDREM LPBK: %c%c%c%c | | |\n", 659 (pmd_rmt_lb & 8) ? 'Y':'N', 660 (pmd_rmt_lb & 4) ? 'Y':'N', 661 (pmd_rmt_lb & 2) ? 'Y':'N', 662 (pmd_rmt_lb & 1) ? 'Y':'N')); 663 PHYMOD_DEBUG_ERROR(("+-------------------+--------------------------+-------------------------------+\n")); 664 665 } 666 667 return PHYMOD_E_NONE; 668 } 669 670 /** 671 @brief Get the link status 672 @param pc handle to current TSCE context (#PHYMOD_ST) 673 @returns PHYMOD_E_NONE 674 @details Call all the Diags sequentially. 675 #temod_diag_topology 676 #temod_diag_link 677 #temod_diag_autoneg 678 #temod_diag_speed 679 */ 680 int temod_diag_general(PHYMOD_ST *pc) 681 { 682 temod_diag_topology(pc); 683 temod_diag_link(pc); 684 temod_diag_autoneg(pc); 685 temod_diag_speed(pc); 686 687 return (PHYMOD_E_NONE); 688 } 689 690 /** 691 @brief Get the link status 692 @param pc handle to current TSCE context (#PHYMOD_ST) 693 @returns PHYMOD_E_NONE 694 @details Print the link status. 695 - pmd_live_status 696 -# pll_lock_sts : PMD PLL lock indication 697 - pmd_lane_live_status 698 -# signal_detect_sts : The signal detected on the lane 699 -# rx_lock_sts : The recovery clock locked for the rx lane 700 - pmd_lane_latched_status 701 - pcs_live_status 702 -# Live per port sync status indicator: cl36/cl48/brcm mode/Comma detect/code sync 703 -# Live per lane Block Lock Status indicator: cl49/cl82/Sync bits locked, on the 2 sync bits of the 66 bits(of 64/66 encoding) 704 b. link_status : Link status for that port 705 - pcs_latched_status 706 */ 707 int temod_diag_link(PHYMOD_ST *pc) 708 { 709 PMD_X1_STSr_t pmd_live_status; 710 PMD_X4_STSr_t pmd_lane_live_status; 711 PMD_X4_LATCH_STSr_t pmd_lane_latched_status[4]; 712 RX_X4_PCS_LIVE_STSr_t pcs_live_status; 713 RX_X4_PCS_LATCH_STS0r_t pcs_latched_status; 714 phymod_access_t *lpc = (phymod_access_t*)pc; 715 716 int i,rx_lock_sts[4],sig_det_sts[4], this_lane; 717 718 719 /*1. pmd_live_status */ 720 READ_PMD_X1_STSr(pc, &pmd_live_status); 721 722 /*2a. pmd_lane_live_status */ 723 /*2b. pmd_lane_latched_status */ 724 725 this_lane = _TRG_LANE(lpc); 726 for(i=0; i < 4; i++) { 727 _TRG_LANE(lpc) = 1<<i; 728 READ_PMD_X4_STSr(lpc, &pmd_lane_live_status); 729 sig_det_sts[i] = PMD_X4_STSr_SIGNAL_DETECT_STSf_GET(pmd_lane_live_status); 730 rx_lock_sts[i] = PMD_X4_STSr_RX_LOCK_STSf_GET(pmd_lane_live_status); 731 732 PMD_X4_LATCH_STSr_CLR(pmd_lane_latched_status[i]); 733 READ_PMD_X4_LATCH_STSr(pc, &pmd_lane_latched_status[i]); 734 } 735 _TRG_LANE(lpc) = this_lane; 736 737 /*3a. pcs_live_status */ 738 /*3b. pcs_latched_status */ 739 READ_RX_X4_PCS_LIVE_STSr(pc, &pcs_live_status); 740 READ_RX_X4_PCS_LATCH_STS0r(pc, &pcs_latched_status); 741 742 /* Print the information here */ 743 PHYMOD_DEBUG_ERROR(("| TRG ADR : %06d LANE: %02d LINK STATE | LH | LL |\n", pc->addr, pc->lane_mask)); 744 PHYMOD_DEBUG_ERROR(("+-----------------------+-------------------+---------------+---------+--------+\n")); 745 PHYMOD_DEBUG_ERROR(("| PMD PLL LOCK : %c | PCS SYNC : %c | PCS SYNC STAT : %04d : %04d |\n", 746 (PMD_X1_STSr_PLL_LOCK_STSf_GET(pmd_live_status) == 1) ? 'Y' : 'N', 747 (RX_X4_PCS_LIVE_STSr_SYNC_STATUSf_GET(pcs_live_status) == 1) ? 'Y' : 'N', 748 RX_X4_PCS_LATCH_STS0r_SYNC_STATUS_LHf_GET(pcs_latched_status), 749 RX_X4_PCS_LATCH_STS0r_SYNC_STATUS_LLf_GET(pcs_latched_status))); 750 751 PHYMOD_DEBUG_ERROR(("| PMD SIG DETECT : %c%c%c%c | PCS LINK : %c | PCS LINK STAT : %04d : %04d |\n", 752 (sig_det_sts[3] == 1)? 'Y':'N', 753 (sig_det_sts[2] == 1)? 'Y':'N', 754 (sig_det_sts[1] == 1)? 'Y':'N', 755 (sig_det_sts[0] == 1)? 'Y':'N', 756 (RX_X4_PCS_LIVE_STSr_LINK_STATUSf_GET(pcs_live_status) == 1) ? 'Y' : 'N', 757 RX_X4_PCS_LATCH_STS0r_LINK_STATUS_LHf_GET(pcs_latched_status), 758 RX_X4_PCS_LATCH_STS0r_LINK_STATUS_LLf_GET(pcs_latched_status))); 759 760 PHYMOD_DEBUG_ERROR(("| PMD LOCKED : %c%c%c%c | PCS HI BER : %04d | PCS HIGH BER : %04d : %04d |\n", 761 (rx_lock_sts[3] == 1)? 'Y':'N', 762 (rx_lock_sts[2] == 1)? 'Y':'N', 763 (rx_lock_sts[1] == 1)? 'Y':'N', 764 (rx_lock_sts[0] == 1)? 'Y':'N', 765 RX_X4_PCS_LIVE_STSr_HI_BERf_GET(pcs_live_status), 766 RX_X4_PCS_LATCH_STS0r_HI_BER_LLf_GET(pcs_latched_status), 767 RX_X4_PCS_LATCH_STS0r_HI_BER_LHf_GET(pcs_latched_status))); 768 769 770 PHYMOD_DEBUG_ERROR(("| PMD LATCH HI : %d%d%d%d | PCS DESKEW : %04d | PCS DESKEW : %04d : %04d |\n", 771 PMD_X4_LATCH_STSr_SIGNAL_DETECT_LHf_GET(pmd_lane_latched_status[3]), 772 PMD_X4_LATCH_STSr_SIGNAL_DETECT_LHf_GET(pmd_lane_latched_status[2]), 773 PMD_X4_LATCH_STSr_SIGNAL_DETECT_LHf_GET(pmd_lane_latched_status[1]), 774 PMD_X4_LATCH_STSr_SIGNAL_DETECT_LHf_GET(pmd_lane_latched_status[0]), 775 RX_X4_PCS_LIVE_STSr_DESKEW_STATUSf_GET(pcs_live_status), 776 RX_X4_PCS_LATCH_STS0r_DESKEW_STATUS_LLf_GET(pcs_latched_status), 777 RX_X4_PCS_LATCH_STS0r_DESKEW_STATUS_LHf_GET(pcs_latched_status))); 778 779 PHYMOD_DEBUG_ERROR(("| PMD LATCH LO : %d%d%d%d | PCS AMLOCK : %04d | PCS AM LOCK : %04d : %04d |\n", 780 PMD_X4_LATCH_STSr_SIGNAL_DETECT_LLf_GET(pmd_lane_latched_status[3]), 781 PMD_X4_LATCH_STSr_SIGNAL_DETECT_LLf_GET(pmd_lane_latched_status[2]), 782 PMD_X4_LATCH_STSr_SIGNAL_DETECT_LLf_GET(pmd_lane_latched_status[1]), 783 PMD_X4_LATCH_STSr_SIGNAL_DETECT_LLf_GET(pmd_lane_latched_status[0]), 784 RX_X4_PCS_LIVE_STSr_AM_LOCKf_GET(pcs_live_status), 785 RX_X4_PCS_LATCH_STS0r_AM_LOCK_LLf_GET(pcs_latched_status), 786 RX_X4_PCS_LATCH_STS0r_AM_LOCK_LHf_GET(pcs_latched_status))); 787 788 PHYMOD_DEBUG_ERROR(("| RXLOCK LATCH HI: %d%d%d%d | | |\n", 789 PMD_X4_LATCH_STSr_RX_LOCK_LHf_GET(pmd_lane_latched_status[3]), 790 PMD_X4_LATCH_STSr_RX_LOCK_LHf_GET(pmd_lane_latched_status[2]), 791 PMD_X4_LATCH_STSr_RX_LOCK_LHf_GET(pmd_lane_latched_status[1]), 792 PMD_X4_LATCH_STSr_RX_LOCK_LHf_GET(pmd_lane_latched_status[0]))); 793 794 PHYMOD_DEBUG_ERROR(("| RXLOCK LATCH LO: %d%d%d%d | | |\n", 795 PMD_X4_LATCH_STSr_RX_LOCK_LLf_GET(pmd_lane_latched_status[3]), 796 PMD_X4_LATCH_STSr_RX_LOCK_LLf_GET(pmd_lane_latched_status[2]), 797 PMD_X4_LATCH_STSr_RX_LOCK_LLf_GET(pmd_lane_latched_status[1]), 798 PMD_X4_LATCH_STSr_RX_LOCK_LLf_GET(pmd_lane_latched_status[0]))); 799 800 PHYMOD_DEBUG_ERROR(("+-----------------------+-------------------+----------------------------------+\n")); 801 802 return PHYMOD_E_NONE; 803 } 804 805 /** 806 @brief Internal Tfc info (PRTP. vs. PktGen vs. MAC dataetc.). 807 @param pc handle to current TSCE context (#PHYMOD_ST) 808 @returns PHYMOD_E_NONE 809 @details Print the Internal Tfc types. 810 */ 811 int temod_diag_internal_tfc(PHYMOD_ST *pc) 812 { 813 PKTGEN_CTL1r_t reg_pktgen_ctl1; 814 PKTGEN_CTL2r_t reg_pktgen_ctl2; 815 PKTGEN_PRTPCTLr_t reg_prtp_ctl; 816 817 READ_PKTGEN_CTL1r(pc, ®_pktgen_ctl1); 818 READ_PKTGEN_CTL2r(pc, ®_pktgen_ctl2); 819 READ_PKTGEN_PRTPCTLr(pc, ®_prtp_ctl); 820 821 PHYMOD_DEBUG_ERROR(("| TRG ADR : %06d LANE: %02d INTERNAL TFC |\n", 822 pc->addr, pc->lane_mask)); 823 PHYMOD_DEBUG_ERROR(("+------------------------------------------+-----------------------------------+\n")); 824 825 if (PKTGEN_CTL1r_TX_PRTP_ENf_GET(reg_pktgen_ctl1) || 826 PKTGEN_PRTPCTLr_RX_PRTP_ENf_GET(reg_prtp_ctl)) { 827 828 PHYMOD_DEBUG_ERROR(("| TX/RX_PRT_EN %-8s (Tx = 0x%0x, Rx=0x%0X) | PKT_OR_PRTP %-8s |\n", 829 ((PKTGEN_CTL1r_TX_PRTP_ENf_GET(reg_pktgen_ctl1) == 0 ) || 830 (PKTGEN_PRTPCTLr_RX_PRTP_ENf_GET(reg_prtp_ctl) == 0)) ? "Not Set" : "Set", 831 PKTGEN_CTL1r_TX_PRTP_ENf_GET(reg_pktgen_ctl1), 832 PKTGEN_PRTPCTLr_RX_PRTP_ENf_GET(reg_prtp_ctl), 833 (PKTGEN_CTL1r_PKT_OR_PRTPf_GET(reg_pktgen_ctl1) == 1) ? "Set" : "Not Set")); 834 835 } else if(PKTGEN_CTL2r_PKTGEN_ENf_GET(reg_pktgen_ctl2)){ 836 PHYMOD_DEBUG_ERROR(("| Traffic_type: CJ/CRPAT | PKT_OR_PRTP : %-16s |\n", 837 (PKTGEN_CTL1r_PKT_OR_PRTPf_GET(reg_pktgen_ctl1) == 0)? "Set" : "Not Set")); 838 } else { 839 PHYMOD_DEBUG_ERROR(("| Traffic_type: MAC | |\n")); 840 } 841 842 PHYMOD_DEBUG_ERROR(("+------------------------------------------+-----------------------------------+\n")); 843 return PHYMOD_E_NONE; 844 } 845 846 #define _TRG_ST_PRINT(pc, st_num, ovr, sc_st) \ 847 { \ 848 SC_X1_SPD_##ovr##_SPDr_t sc_st##_speed; \ 849 SC_X1_SPD_##ovr##_0r_t sc_st##_0; \ 850 SC_X1_SPD_##ovr##_1r_t sc_st##_1; \ 851 SC_X1_SPD_##ovr##_2r_t sc_st##_2; \ 852 SC_X1_SPD_##ovr##_3r_t sc_st##_3; \ 853 SC_X1_SPD_##ovr##_4r_t sc_st##_4; \ 854 SC_X1_SPD_##ovr##_5r_t sc_st##_5; \ 855 SC_X1_SPD_##ovr##_6r_t sc_st##_6; \ 856 SC_X1_SPD_##ovr##_7r_t sc_st##_7; \ 857 SC_X1_SPD_##ovr##_8r_t sc_st##_8; \ 858 uint8_t x1_speed; \ 859 READ_SC_X1_SPD_##ovr##_SPDr(pc,&sc_st##_speed); \ 860 x1_speed = SC_X1_SPD_##ovr##_SPDr_SPEEDf_GET(sc_st##_speed); \ 861 if (x1_speed == 0xFF) { \ 862 PHYMOD_DEBUG_ERROR(("| ST [%d] | SPD_ILLEGAL | NUM LANES : %d |\n", \ 863 st_num, \ 864 SC_X1_SPD_##ovr##_SPDr_NUM_LANESf_GET(sc_st##_speed))); \ 865 } else { \ 866 PHYMOD_DEBUG_ERROR(("| ST [%d] | 0x%02X | NUM LANES : %d |\n", \ 867 st_num, x1_speed, \ 868 SC_X1_SPD_##ovr##_SPDr_NUM_LANESf_GET(sc_st##_speed))); \ 869 } \ 870 \ 871 if((resolved_speed == 0xff) || (resolved_speed==SC_X1_SPD_##ovr##_SPDr_SPEEDf_GET(sc_st##_speed))) { /* ST has Entry */ \ 872 READ_SC_X1_SPD_##ovr##_0r(pc,&sc_st##_0); \ 873 READ_SC_X1_SPD_##ovr##_1r(pc,&sc_st##_1); \ 874 READ_SC_X1_SPD_##ovr##_2r(pc,&sc_st##_2); \ 875 READ_SC_X1_SPD_##ovr##_3r(pc,&sc_st##_3); \ 876 READ_SC_X1_SPD_##ovr##_4r(pc,&sc_st##_4); \ 877 READ_SC_X1_SPD_##ovr##_5r(pc,&sc_st##_5); \ 878 READ_SC_X1_SPD_##ovr##_6r(pc,&sc_st##_6); \ 879 READ_SC_X1_SPD_##ovr##_7r(pc,&sc_st##_7); \ 880 READ_SC_X1_SPD_##ovr##_8r(pc,&sc_st##_8); \ 881 \ 882 PHYMOD_DEBUG_ERROR(("| %-20s | SGMII SPD : %04d | |\n", \ 883 e2s_temod_descrambler_mode[SC_X1_SPD_##ovr##_1r_DESCRAMBLERMODEf_GET(sc_st##_1)]+6, \ 884 SC_X1_SPD_##ovr##_3r_SGMII_SPD_SWITCHf_GET(sc_st##_3))); \ 885 \ 886 PHYMOD_DEBUG_ERROR(("| %-20s | %-28s| CLK CNT0 : %04d |\n", \ 887 e2s_temod_scr_mode[SC_X1_SPD_##ovr##_0r_SCR_MODEf_GET(sc_st##_0)]+6, \ 888 e2s_temod_decoder_mode[SC_X1_SPD_##ovr##_1r_DECODERMODEf_GET(sc_st##_1)]+6, \ 889 SC_X1_SPD_##ovr##_3r_CLOCKCNT0f_GET(sc_st##_3))); \ 890 \ 891 PHYMOD_DEBUG_ERROR(("| %-20s | %-28s| CLK CNT1 : %04d |\n", \ 892 e2s_temod_encode_mode[SC_X1_SPD_##ovr##_0r_ENCODEMODEf_GET(sc_st##_0)]+6, \ 893 e2s_temod_deskew_mode[SC_X1_SPD_##ovr##_1r_DESKEWMODEf_GET(sc_st##_1)]+6, \ 894 SC_X1_SPD_##ovr##_4r_CLOCKCNT1f_GET(sc_st##_4))); \ 895 \ 896 PHYMOD_DEBUG_ERROR(("| %-20s | %-28s| LP CNT0 : %04d |\n", \ 897 e2s_temod_blocksync_mode[SC_X1_SPD_##ovr##_2r_BLOCK_SYNC_MODEf_GET(sc_st##_2)]+6, \ 898 e2s_temod_descrambler2_mode[SC_X1_SPD_##ovr##_1r_DESC2_MODEf_GET(sc_st##_1)]+6, \ 899 SC_X1_SPD_##ovr##_5r_LOOPCNT0f_GET(sc_st##_5))); \ 900 \ 901 PHYMOD_DEBUG_ERROR(("| | |CRDGEN CNT : %04d |\n", \ 902 SC_X1_SPD_##ovr##_8r_PCS_CREDITGENCNTf_GET(sc_st##_8))); \ 903 \ 904 PHYMOD_DEBUG_ERROR(("| CL72 ENA : %02d | %-28s| LP CNT1 : %04d |\n", \ 905 SC_X1_SPD_##ovr##_0r_CL72_ENABLEf_GET(sc_st##_0), \ 906 e2s_temod_byte_del_mode[SC_X1_SPD_##ovr##_1r_CL36BYTEDELETEMODEf_GET(sc_st##_1)]+6, \ 907 SC_X1_SPD_##ovr##_5r_LOOPCNT1f_GET(sc_st##_5))); \ 908 \ 909 PHYMOD_DEBUG_ERROR(("| CHKEND ENA : %02d | 64b66DEC EN %d | MAC CGC : %04d |\n", \ 910 SC_X1_SPD_##ovr##_2r_CHK_END_ENf_GET(sc_st##_2), \ 911 SC_X1_SPD_##ovr##_1r_BRCM64B66_DESCRAMBLER_ENABLEf_GET(sc_st##_1), \ 912 SC_X1_SPD_##ovr##_6r_MAC_CREDITGENCNTf_GET(sc_st##_6))); \ 913 \ 914 PHYMOD_DEBUG_ERROR(("| FEC ENA : %02d | | REP CNT : %04d |\n", \ 915 SC_X1_SPD_##ovr##_0r_FEC_ENABLEf_GET(sc_st##_0), \ 916 SC_X1_SPD_##ovr##_7r_REPLICATION_CNTf_GET(sc_st##_7))); \ 917 \ 918 PHYMOD_DEBUG_ERROR(("| REORDER ENA : %02d | |PCS CRD EN : %04d |\n", \ 919 SC_X1_SPD_##ovr##_2r_REORDER_ENf_GET(sc_st##_2), \ 920 SC_X1_SPD_##ovr##_7r_PCS_CREDITENABLEf_GET(sc_st##_7))); \ 921 \ 922 PHYMOD_DEBUG_ERROR(("| CL36 ENA : %02d | |PCS CK CNT : %04d |\n", \ 923 SC_X1_SPD_##ovr##_2r_CL36_ENf_GET(sc_st##_2), \ 924 SC_X1_SPD_##ovr##_7r_PCS_CLOCKCNT0f_GET(sc_st##_7))); \ 925 \ 926 PHYMOD_DEBUG_ERROR(("+----------------------+-----------------------------+----------+--------------+\n")); \ 927 } \ 928 } 929 930 /** 931 @brief Soft Table diagnostic function 932 @param pc handle to current TSCE context (#PHYMOD_ST) 933 @param resolved_speed The speed to which AN is already resolved. 934 @returns PHYMOD_E_NONE 935 @details Soft Table diags 936 Print the soft table enteries 937 if the resolved_speed is not set, then all the table enteries are displayed 938 */ 939 int temod_diag_st(PHYMOD_ST *pc, int resolved_speed) 940 { 941 _TRG_ST_PRINT(pc, 0, OVRR0, sc_st0) 942 _TRG_ST_PRINT(pc, 1, OVRR1, sc_st1) 943 _TRG_ST_PRINT(pc, 2, OVRR2, sc_st2) 944 _TRG_ST_PRINT(pc, 3, OVRR2, sc_st3) 945 946 PHYMOD_DEBUG_ERROR(("+----------------------+------------------------------+---------+--------------+\n")); 947 948 return PHYMOD_E_NONE; 949 } /*temod_diag_st */ 950 951 /** 952 @brief AN Timers diagnostic function 953 @param pc handle to current TSCE context (#PHYMOD_ST) 954 @returns PHYMOD_E_NONE 955 @details Prints the AN timers for both CL37 and CL73 autonegotiations. 956 */ 957 int temod_diag_an_timers(PHYMOD_ST* pc) 958 { 959 AN_X1_CL37_RESTARTr_t reg_cl37_restart; 960 AN_X1_CL37_ACKr_t reg_cl37_ack; 961 AN_X1_CL37_ERRr_t reg_cl37_err; 962 AN_X1_CL73_BRK_LNKr_t reg_cl73_break_link; 963 AN_X1_CL73_ERRr_t reg_cl73_err; 964 AN_X1_CL73_DME_LOCKr_t reg_cl73_dme_lock; 965 AN_X1_LNK_UPr_t reg_link_up; 966 AN_X1_LNK_FAIL_INHBT_TMR_CL72r_t reg_inhibit_timer; 967 AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72r_t reg_inhibit_not_timer; 968 AN_X1_PD_SD_TMRr_t reg_pd_sd_timer; 969 AN_X1_CL37_SYNC_STS_FILTER_TMRr_t reg_sync_status_filter_timer; 970 AN_X1_PD_TO_CL37_LNK_WAIT_TMRr_t reg_link_wait_timer; 971 AN_X1_IGNORE_LNK_TMRr_t reg_ignore_link_timer; 972 AN_X1_DME_PAGE_TMRr_t reg_dme_page_timer; 973 AN_X1_SGMII_CL73_TMR_TYPEr_t reg_sgmii_cl73_timer; 974 975 READ_AN_X1_CL37_RESTARTr(pc, ®_cl37_restart); 976 READ_AN_X1_CL37_ACKr(pc, ®_cl37_ack); 977 READ_AN_X1_CL37_ERRr(pc, ®_cl37_err); 978 READ_AN_X1_CL73_BRK_LNKr(pc, ®_cl73_break_link); 979 READ_AN_X1_CL73_ERRr(pc, ®_cl73_err); 980 READ_AN_X1_CL73_DME_LOCKr(pc, ®_cl73_dme_lock); 981 READ_AN_X1_LNK_UPr(pc, ®_link_up); 982 READ_AN_X1_LNK_FAIL_INHBT_TMR_CL72r(pc, ®_inhibit_timer); 983 READ_AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72r(pc, ®_inhibit_not_timer); 984 READ_AN_X1_PD_SD_TMRr(pc, ®_pd_sd_timer); 985 READ_AN_X1_CL37_SYNC_STS_FILTER_TMRr(pc, ®_sync_status_filter_timer); 986 READ_AN_X1_PD_TO_CL37_LNK_WAIT_TMRr(pc, ®_link_wait_timer); 987 READ_AN_X1_IGNORE_LNK_TMRr(pc, ®_ignore_link_timer); 988 READ_AN_X1_DME_PAGE_TMRr(pc, ®_dme_page_timer); 989 READ_AN_X1_SGMII_CL73_TMR_TYPEr(pc, ®_sgmii_cl73_timer); 990 991 PHYMOD_DEBUG_ERROR(("| TRG ADR : %06d LANE: %02d AN TIMERS |\n", 992 pc->addr, pc->lane_mask)); 993 PHYMOD_DEBUG_ERROR(("+--------------------------------------+---------------------------------------+\n")); 994 PHYMOD_DEBUG_ERROR(("| CL37 RESTART : 0x%08X | CL37 ACK : 0x%08X |\n", 995 AN_X1_CL37_RESTARTr_CL37_RESTART_TIMER_PERIODf_GET(reg_cl37_restart), 996 AN_X1_CL37_ACKr_CL37_ACK_TIMER_PERIODf_GET(reg_cl37_ack))); 997 998 PHYMOD_DEBUG_ERROR(("| CL37 ERR : 0x%08X | CL37 LINK BREAK : 0x%08X |\n", 999 AN_X1_CL37_ERRr_CL37_ERROR_TIMER_PERIODf_GET(reg_cl37_err), 1000 AN_X1_CL73_BRK_LNKr_TX_DISABLE_TIMER_PERIODf_GET(reg_cl73_break_link))); 1001 1002 PHYMOD_DEBUG_ERROR(("| CL73 ERR : 0x%08X | CL73 DME LOCK : 0x%08X |\n", 1003 AN_X1_CL73_ERRr_CL73_ERROR_TIMER_PERIODf_GET(reg_cl73_err), 1004 AN_X1_CL73_DME_LOCKr_PD_DME_LOCK_TIMER_PERIODf_GET(reg_cl73_dme_lock))); 1005 1006 PHYMOD_DEBUG_ERROR(("| LINK_UP : 0x%08X | PS SD : 0x%08x |\n", 1007 AN_X1_LNK_UPr_CL73_LINK_UP_TIMER_PERIODf_GET(reg_link_up), 1008 AN_X1_PD_SD_TMRr_PD_SD_TIMER_PERIODf_GET(reg_pd_sd_timer))); 1009 1010 PHYMOD_DEBUG_ERROR(("| SYNC STATUS : 0x%08X | PD TO CL37 : 0x%08X |\n", 1011 AN_X1_CL37_SYNC_STS_FILTER_TMRr_CL37_SYNC_STATUS_FILTER_TIMER_PERIODf_GET(reg_sync_status_filter_timer), 1012 AN_X1_PD_TO_CL37_LNK_WAIT_TMRr_PD_TO_CL37_LINK_WAIT_TIMERf_GET(reg_link_wait_timer))); 1013 1014 PHYMOD_DEBUG_ERROR(("| IGNORE LINK : 0x%08X | SGMII : 0x%08X |\n", 1015 AN_X1_IGNORE_LNK_TMRr_IGNORE_LINK_TIMER_PERIODf_GET(reg_ignore_link_timer), 1016 AN_X1_SGMII_CL73_TMR_TYPEr_SGMII_TIMERf_GET(reg_sgmii_cl73_timer))); 1017 1018 PHYMOD_DEBUG_ERROR(("| DME PAGE MIN : 0x%08X | DME PAGE MAX : 0x%08X |\n", 1019 AN_X1_DME_PAGE_TMRr_CL73_PAGE_TEST_MIN_TIMERf_GET(reg_dme_page_timer), 1020 AN_X1_DME_PAGE_TMRr_CL73_PAGE_TEST_MAX_TIMERf_GET(reg_dme_page_timer))); 1021 1022 PHYMOD_DEBUG_ERROR(("| FAIL INHIBIT W/O CL72 : 0x%08X | FAIL INHIBIT WITH CL72 : 0x%08X |\n", 1023 AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72r_LINK_FAIL_INHIBIT_TIMER_NCL72_PERIODf_GET(reg_inhibit_not_timer), 1024 AN_X1_LNK_FAIL_INHBT_TMR_CL72r_LINK_FAIL_INHIBIT_TIMER_CL72_PERIODf_GET(reg_inhibit_timer))); 1025 1026 PHYMOD_DEBUG_ERROR(("+--------------------------------------+---------------------------------------+\n")); 1027 return PHYMOD_E_NONE; 1028 } 1029 1030 /** 1031 @brief Prints out the debug state register 1032 @param pc handle to current TSCE context (#PHYMOD_ST) 1033 @returns PHYMOD_E_NONE 1034 @details Prints the debug state regs. 1035 */ 1036 int temod_diag_state(PHYMOD_ST* pc) 1037 { 1038 SC_X4_DBGr_t reg_sc_dbg_st; 1039 AN_X4_TLA_SEQUENCER_STSr_t reg_an_tla_seq; 1040 1041 READ_SC_X4_DBGr(pc, ®_sc_dbg_st); 1042 READ_AN_X4_TLA_SEQUENCER_STSr(pc, ®_an_tla_seq); 1043 1044 PHYMOD_DEBUG_ERROR(("| DEBUG STATE |\n")); 1045 PHYMOD_DEBUG_ERROR(("+--------------------------------------+---------------------------------------+\n")); 1046 PHYMOD_DEBUG_ERROR(("| SC_DEBUG_STATE : 0x%08x | FSM_STATUS : 0x%08X |\n", 1047 SC_X4_DBGr_GET(reg_sc_dbg_st), SC_X4_DBGr_SC_FSM_STATUSf_GET(reg_sc_dbg_st))); 1048 1049 PHYMOD_DEBUG_ERROR(("| TLA_SEQUENCER STS : 0x%08x | |\n", 1050 AN_X4_TLA_SEQUENCER_STSr_GET(reg_an_tla_seq))); 1051 PHYMOD_DEBUG_ERROR(("+--------------------------------------+---------------------------------------+\n")); 1052 1053 return PHYMOD_E_NONE; 1054 } 1055 1056 /* 1057 @brief TBD 1058 @param pc handle to current TSCE context (#PHYMOD_ST) 1059 @returns PHYMOD_E_NONE 1060 @details Misc debug 1061 */ 1062 int temod_diag_debug(PHYMOD_ST* pc) 1063 { 1064 return PHYMOD_E_NONE; 1065 } 1066 1067 int temod_diag_g_rd_ram(PHYMOD_ST *pc, int mode, int lane) 1068 { 1069 return PHYMOD_E_NONE; 1070 } 1071 1072 int temod_diag_g_rd_uC(PHYMOD_ST *pc, int lane) 1073 { 1074 return PHYMOD_E_NONE; 1075 } 1076 1077 int temod_diag_g_info(PHYMOD_ST *pc) 1078 { 1079 return PHYMOD_E_NONE; 1080 } 1081 1082 int temod_diag_ieee(PHYMOD_ST *pc) 1083 { 1084 return PHYMOD_E_NONE; 1085 } 1086 1087 /*! 1088 1089 */ 1090 int temod_diag(PHYMOD_ST *pc, temod_diag_type diag_type) 1091 { 1092 int rv; 1093 rv = PHYMOD_E_NONE; 1094 1095 PHYMOD_DEBUG_ERROR(("+------------------------------------------------------------------------------+\n")); 1096 if(diag_type & TEMOD_DIAG_GENERAL) rv |= temod_diag_general(pc); 1097 if(diag_type & TEMOD_DIAG_TOPOLOGY) rv |= temod_diag_topology(pc); 1098 if(diag_type & TEMOD_DIAG_LINK) rv |= temod_diag_link(pc); 1099 if(diag_type & TEMOD_DIAG_SPEED) rv |= temod_diag_speed(pc); 1100 if(diag_type & TEMOD_DIAG_ANEG) rv |= temod_diag_autoneg(pc); 1101 if(diag_type & TEMOD_DIAG_TFC) rv |= temod_diag_internal_tfc(pc); 1102 if(diag_type & TEMOD_DIAG_AN_TIMERS) rv |= temod_diag_an_timers(pc); 1103 if(diag_type & TEMOD_DIAG_STATE) rv |= temod_diag_state(pc); 1104 if(diag_type & TEMOD_DIAG_DEBUG) rv |= temod_diag_debug(pc); 1105 return rv; 1106 } 1107 1108 /*! 1109 */ 1110 int temod_diag_disp(PHYMOD_ST *pc, const char* cmd_str) 1111 { 1112 temod_diag_type type; 1113 1114 if (!cmd_str) 1115 type = TEMOD_DIAG_GENERAL; 1116 else if (!PHYMOD_STRCMP(cmd_str, "topo")) 1117 type = TEMOD_DIAG_TOPOLOGY; 1118 else if (!PHYMOD_STRCMP(cmd_str, "link")) 1119 type = TEMOD_DIAG_LINK; 1120 else if (!PHYMOD_STRCMP(cmd_str, "speed")) 1121 type = TEMOD_DIAG_SPEED; 1122 else if (!PHYMOD_STRCMP(cmd_str, "aneg")) 1123 type = TEMOD_DIAG_ANEG; 1124 else if (!PHYMOD_STRCMP(cmd_str, "tfc")) 1125 type = TEMOD_DIAG_TFC; 1126 else if (!PHYMOD_STRCMP(cmd_str, "antimers")) 1127 type = TEMOD_DIAG_AN_TIMERS; 1128 else if (!PHYMOD_STRCMP(cmd_str, "state")) 1129 type = TEMOD_DIAG_STATE; 1130 else if (!PHYMOD_STRCMP(cmd_str, "debug")) 1131 type = TEMOD_DIAG_DEBUG; 1132 else 1133 type = TEMOD_DIAG_GENERAL; 1134 1135 return (temod_diag(pc, type)); 1136 } 1137