temod_cfg_seq.c (330812B)
1 /*---------------------------------------------------------------------- 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * Broadcom Corporation 8 * Proprietary and Confidential information 9 * All rights reserved 10 * This source file is the property of Broadcom Corporation, and 11 * may not be copied or distributed in any isomorphic form without the 12 * prior written consent of Broadcom Corporation. 13 *--------------------------------------------------------------------- 14 * File : temod_cfg_seq.c 15 * Description: c functions implementing Tier1s for TEMod Serdes Driver 16 *---------------------------------------------------------------------*/ 17 18 #ifndef _DV_TB_ 19 #define _SDK_TEMOD_ 1 20 #endif 21 22 #ifdef _DV_TB_ 23 #include <stdint.h> 24 #include "temod_main.h" 25 #include "temod_defines.h" 26 #include "tePCSRegEnums.h" 27 #include "tePMDRegEnums.h" 28 #include "phy_tsc_iblk.h" 29 #include "bcmi_tsce_xgxs_defs.h" 30 #endif /* _DV_TB_ */ 31 32 #ifdef _SDK_TEMOD_ 33 #include <phymod/phymod.h> 34 #include <phymod/phymod_system.h> 35 #include <phymod/phymod_util.h> 36 #include <phymod/phymod_debug.h> 37 #include <phymod/chip/bcmi_tsce_xgxs_defs.h> 38 #include "temod_enum_defines.h" 39 #include "temod.h" 40 #include "temod_device.h" 41 #include "temod_sc_lkup_table.h" 42 #include "tePCSRegEnums.h" 43 #include "../../eagle/tier1/eagle_tsc_common.h" 44 #include "../../eagle/tier1/eagle_tsc_interface.h" 45 #include "../../eagle/tier1/eagle_tsc_fields.h" 46 #include "../../eagle/tier1/eagle_tsc_dependencies.h" 47 #include "../../eagle/tier1/eagle_tsc_field_access.h" 48 49 #endif /* _SDK_TEMOD_ */ 50 51 #ifndef PHYMOD_ST 52 #ifdef _SDK_TEMOD_ 53 #define PHYMOD_ST const phymod_access_t 54 #else 55 #define PHYMOD_ST temod_st 56 #endif /* _SDK_TEMOD_ */ 57 #endif /* PHYMOD_ST */ 58 59 #ifdef _SDK_TEMOD_ 60 #define TEMOD_DBG_IN_FUNC_INFO(pc) \ 61 PHYMOD_VDBG(TEMOD_DBG_FUNC,pc,("%-22s: Adr:%08x Ln:%02d\n", __func__, (unsigned int)pc->addr, (int)pc->lane_mask)) 62 #define TEMOD_DBG_IN_FUNC_VIN_INFO(pc,_print_) \ 63 PHYMOD_VDBG(TEMOD_DBG_FUNCVALIN,pc,_print_) 64 #define TEMOD_DBG_IN_FUNC_VOUT_INFO(pc,_print_) \ 65 PHYMOD_VDBG(TEMOD_DBG_FUNCVALOUT,pc,_print_) 66 #endif 67 68 #ifdef _DV_TB_ 69 #define TEMOD_DBG_IN_FUNC_INFO(pc) \ 70 PHYMOD_VDBG(TEMOD_DBG_FUNC, pc, \ 71 ("TEMOD IN Function : %s Port Add : %d Lane No: %d\n", \ 72 __func__, pc->prt_ad, pc->this_lane)) 73 #define TEMOD_DBG_IN_FUNC_VIN_INFO(pc,_print_) \ 74 PHYMOD_VDBG(TEMOD_DBG_FUNCVALIN,pc,_print_) 75 #define TEMOD_DBG_IN_FUNC_VOUT_INFO(pc,_print_) \ 76 PHYMOD_VDBG(TEMOD_DBG_FUNCVALOUT,pc,_print_) 77 int phymod_debug_check(uint32_t flags, PHYMOD_ST *pc); 78 #endif 79 80 static eagle_sc_pmd_entry_st eagle_sc_pmd_entry[] = { 81 82 /*SPD_10M 0*/ { 1, TEMOD_PMA_OS_MODE_5, TEMOD_PLL_MODE_DIV_40, 0, 0, 1}, 83 /*SPD_10M 1*/ { 1, TEMOD_PMA_OS_MODE_5, TEMOD_PLL_MODE_DIV_40, 0, 0, 1}, 84 /*SPD_100M 2*/ { 1, TEMOD_PMA_OS_MODE_5, TEMOD_PLL_MODE_DIV_40, 0, 0, 1}, 85 /*SPD_1000M 3*/ { 1, TEMOD_PMA_OS_MODE_5, TEMOD_PLL_MODE_DIV_40, 0, 0, 1}, 86 /*SPD_1G_CX1 4*/ { 1, TEMOD_PMA_OS_MODE_5, TEMOD_PLL_MODE_DIV_40, 0, 0, 1}, 87 /*SPD_1G_KX1 5*/ { 1, TEMOD_PMA_OS_MODE_8_25, TEMOD_PLL_MODE_DIV_66, 0, 0, 1}, 88 /*SPD_2p5G 6*/ { 1, TEMOD_PMA_OS_MODE_2, TEMOD_PLL_MODE_DIV_40, 0, 0, 1}, 89 /*SPD_5G_X1 7*/ { 1, TEMOD_PMA_OS_MODE_1, TEMOD_PLL_MODE_DIV_40, 1, 0, 0}, 90 /*SPD_10G_CX4 8*/ { 4, TEMOD_PMA_OS_MODE_2, TEMOD_PLL_MODE_DIV_40, 0, 0, 0}, 91 /*SPD_10G_KX4 9*/ { 4, TEMOD_PMA_OS_MODE_2, TEMOD_PLL_MODE_DIV_40, 0, 0, 0}, 92 /*SPD_10G_X4 10*/ { 4, TEMOD_PMA_OS_MODE_2, TEMOD_PLL_MODE_DIV_40, 0, 0, 1}, 93 /*SPD_13G_X4 11*/ { 4, TEMOD_PMA_OS_MODE_2, TEMOD_PLL_MODE_DIV_52, 0, 0, 1}, 94 /*SPD_15G_X4 12*/ { 4, TEMOD_PMA_OS_MODE_2, TEMOD_PLL_MODE_DIV_60, 0, 0, 1}, 95 /*SPD_16G_X4 13*/ { 4, TEMOD_PMA_OS_MODE_2, TEMOD_PLL_MODE_DIV_64, 0, 0, 1}, 96 /*SPD_20G_CX4 14*/ { 4, TEMOD_PMA_OS_MODE_1, TEMOD_PLL_MODE_DIV_40, 0, 0, 1}, 97 /*SPD_10G_CX2 15*/ { 2, TEMOD_PMA_OS_MODE_1, TEMOD_PLL_MODE_DIV_40, 0, 0, 1}, 98 /*SPD_10G_X2 16*/ { 2, TEMOD_PMA_OS_MODE_1, TEMOD_PLL_MODE_DIV_40, 1, 0, 0}, 99 /*SPD_20G_X4 17*/ { 4, TEMOD_PMA_OS_MODE_1, TEMOD_PLL_MODE_DIV_40, 1, 0, 1}, 100 /*SPD_10p5G_X2 18*/ { 2, TEMOD_PMA_OS_MODE_1, TEMOD_PLL_MODE_DIV_42, 1, 0, 0}, 101 /*SPD_21G_X4 19*/ { 4, TEMOD_PMA_OS_MODE_1, TEMOD_PLL_MODE_DIV_42, 1, 0, 0}, 102 /*SPD_12p7G_X2 20*/ { 2, TEMOD_PMA_OS_MODE_1, TEMOD_PLL_MODE_DIV_42, 1, 0, 0}, 103 /*SPD_25p45G_X4 21*/ { 4, TEMOD_PMA_OS_MODE_1, TEMOD_PLL_MODE_DIV_42, 1, 0, 0}, 104 /*SPD_15p75G_X2 22*/ { 2, TEMOD_PMA_OS_MODE_1, TEMOD_PLL_MODE_DIV_52, 1, 0, 0}, 105 /*SPD_31p5G_X4 23*/ { 4, TEMOD_PMA_OS_MODE_1, TEMOD_PLL_MODE_DIV_52, 1, 0, 0}, 106 /*SPD_31p5G_KR4 24*/ { 4, TEMOD_PMA_OS_MODE_1, TEMOD_PLL_MODE_DIV_52, 1, 0, 0}, 107 /*SPD_20G_CX2 25*/ { 2, TEMOD_PMA_OS_MODE_1, TEMOD_PLL_MODE_DIV_66, 1, 0, 0}, 108 /*SPD_20G_X2 26*/ { 2, TEMOD_PMA_OS_MODE_1, TEMOD_PLL_MODE_DIV_66, 1, 0, 0}, 109 /*SPD_40G_X4 27*/ { 4, TEMOD_PMA_OS_MODE_1, TEMOD_PLL_MODE_DIV_66, 1, 0, 0}, 110 /*SPD_10G_KR1 28*/ { 0, TEMOD_PMA_OS_MODE_1, TEMOD_PLL_MODE_DIV_66, 1, 0, 0}, 111 /*SPD_10p6_X1 29*/ { 0, TEMOD_PMA_OS_MODE_1, TEMOD_PLL_MODE_DIV_70, 1, 0, 0}, 112 /*SPD_20G_KR2 30*/ { 2, TEMOD_PMA_OS_MODE_1, TEMOD_PLL_MODE_DIV_66, 1, 0, 0}, 113 /*SPD_20G_CR2 31*/ { 2, TEMOD_PMA_OS_MODE_1, TEMOD_PLL_MODE_DIV_66, 1, 0, 0}, 114 /*SPD_21G_X2 32*/ { 2, TEMOD_PMA_OS_MODE_1, TEMOD_PLL_MODE_DIV_70, 1, 0, 0}, 115 /*SPD_40G_KR4 33*/ { 4, TEMOD_PMA_OS_MODE_1, TEMOD_PLL_MODE_DIV_66, 1, 0, 0}, 116 /*SPD_40G_CR4 34*/ { 4, TEMOD_PMA_OS_MODE_1, TEMOD_PLL_MODE_DIV_66, 1, 0, 0}, 117 /*SPD_42G_X4 35*/ { 4, TEMOD_PMA_OS_MODE_1, TEMOD_PLL_MODE_DIV_70, 1, 0, 0}, 118 /*SPD_100G_CR10 36*/ {10, TEMOD_PMA_OS_MODE_1, TEMOD_PLL_MODE_DIV_66, 1, 0, 0}, 119 /*SPD_107G_CR10 37*/ {10, TEMOD_PMA_OS_MODE_1, TEMOD_PLL_MODE_DIV_70, 1, 0, 0}, 120 /*SPD_120G_X12 38*/ {12, TEMOD_PMA_OS_MODE_1, TEMOD_PLL_MODE_DIV_66, 1, 0, 0}, 121 /*SPD_127G_X12 39*/ {12, TEMOD_PMA_OS_MODE_1, TEMOD_PLL_MODE_DIV_70, 1, 0, 0}, 122 /*SPD_ILLEGAL 40*/ { 0, TEMOD_PMA_OS_MODE_5, TEMOD_PLL_MODE_DIV_40, 0, 0, 0}, 123 /*SPD_ILLEGAL 41*/ { 0, TEMOD_PMA_OS_MODE_5, TEMOD_PLL_MODE_DIV_40, 0, 0, 0}, 124 /*SPD_ILLEGAL 42*/ { 0, TEMOD_PMA_OS_MODE_5, TEMOD_PLL_MODE_DIV_40, 0, 0, 0}, 125 /*SPD_ILLEGAL 43*/ { 0, TEMOD_PMA_OS_MODE_5, TEMOD_PLL_MODE_DIV_40, 0, 0, 0}, 126 /*SPD_ILLEGAL 44*/ { 0, TEMOD_PMA_OS_MODE_5, TEMOD_PLL_MODE_DIV_40, 0, 0, 0}, 127 /*SPD_ILLEGAL 45*/ { 0, TEMOD_PMA_OS_MODE_5, TEMOD_PLL_MODE_DIV_40, 0, 0, 0}, 128 /*SPD_ILLEGAL 46*/ { 0, TEMOD_PMA_OS_MODE_5, TEMOD_PLL_MODE_DIV_40, 0, 0, 0}, 129 /*SPD_ILLEGAL 47*/ { 0, TEMOD_PMA_OS_MODE_5, TEMOD_PLL_MODE_DIV_40, 0, 0, 0}, 130 /*SPD_ILLEGAL 48*/ { 0, TEMOD_PMA_OS_MODE_5, TEMOD_PLL_MODE_DIV_40, 0, 0, 0}, 131 /*SPD_5G_KR1 49*/ { 0, TEMOD_PMA_OS_MODE_2, TEMOD_PLL_MODE_DIV_66, 0, 0, 0}, 132 /*SPD_10p5G_X4 50*/ { 4, TEMOD_PMA_OS_MODE_2, TEMOD_PLL_MODE_DIV_42, 0, 0, 0}, 133 /*SPD_ILLEGAL 51*/ { 0, TEMOD_PMA_OS_MODE_5, TEMOD_PLL_MODE_DIV_40, 0, 0, 0}, 134 /*SPD_ILLEGAL 52*/ { 0, TEMOD_PMA_OS_MODE_5, TEMOD_PLL_MODE_DIV_40, 0, 0, 0}, 135 /*SPD_10M_10p3125 53*/ { 1, TEMOD_PMA_OS_MODE_8_25, TEMOD_PLL_MODE_DIV_66, 0, 0, 0}, 136 /*SPD_100M_10p3125 54*/ { 1, TEMOD_PMA_OS_MODE_8_25, TEMOD_PLL_MODE_DIV_66, 0, 0, 0}, 137 /*SPD_1000M_10p3125 55*/ { 1, TEMOD_PMA_OS_MODE_8_25, TEMOD_PLL_MODE_DIV_66, 0, 0, 0}, 138 /*SPD_2p5G_X1_10p3125 56*/ { 1, TEMOD_PMA_OS_MODE_3_3,TEMOD_PLL_MODE_DIV_66, 0, 0, 0}, 139 /*SPD_ILLEGAL 57*/ { 0, TEMOD_PMA_OS_MODE_5, TEMOD_PLL_MODE_DIV_40, 0, 0, 0} 140 141 }; 142 143 static eagle_sc_pmd_entry_st eagle_sc_pmd_entry_125M_refclk[] = { 144 145 /*SPD_10M 0*/ { 1, TEMOD_PMA_OS_MODE_5, TEMOD_PLL_MODE_DIV_50, 0, 0, 1}, 146 /*SPD_10M 1*/ { 1, TEMOD_PMA_OS_MODE_5, TEMOD_PLL_MODE_DIV_50, 0, 0, 1}, 147 /*SPD_100M 2*/ { 1, TEMOD_PMA_OS_MODE_5, TEMOD_PLL_MODE_DIV_50, 0, 0, 1}, 148 /*SPD_1000M 3*/ { 1, TEMOD_PMA_OS_MODE_5, TEMOD_PLL_MODE_DIV_50, 0, 0, 1}, 149 /*SPD_1G_CX1 4*/ { 1, TEMOD_PMA_OS_MODE_5, TEMOD_PLL_MODE_DIV_50, 0, 0, 1}, 150 /*SPD_1G_KX1 5*/ { 1, TEMOD_PMA_OS_MODE_8_25, TEMOD_PLL_MODE_DIV_82P5, 0, 0, 1}, 151 /*SPD_2p5G 6*/ { 1, TEMOD_PMA_OS_MODE_2, TEMOD_PLL_MODE_DIV_50, 0, 0, 1}, 152 /*SPD_5G_X1 7*/ { 1, TEMOD_PMA_OS_MODE_1, TEMOD_PLL_MODE_DIV_50, 1, 0, 0}, 153 /*SPD_10G_CX4 8*/ { 4, TEMOD_PMA_OS_MODE_2, TEMOD_PLL_MODE_DIV_50, 0, 0, 0}, 154 /*SPD_10G_KX4 9*/ { 4, TEMOD_PMA_OS_MODE_2, TEMOD_PLL_MODE_DIV_50, 0, 0, 0}, 155 /*SPD_10G_X4 10*/ { 4, TEMOD_PMA_OS_MODE_2, TEMOD_PLL_MODE_DIV_50, 0, 0, 1}, 156 /*SPD_13G_X4 11*/ { 4, TEMOD_PMA_OS_MODE_2, TEMOD_PLL_MODE_DIV_ILLEGAL, 0, 0, 1}, 157 /*SPD_15G_X4 12*/ { 4, TEMOD_PMA_OS_MODE_2, TEMOD_PLL_MODE_DIV_ILLEGAL, 0, 0, 1}, 158 /*SPD_16G_X4 13*/ { 4, TEMOD_PMA_OS_MODE_2, TEMOD_PLL_MODE_DIV_80, 0, 0, 1}, 159 /*SPD_20G_CX4 14*/ { 4, TEMOD_PMA_OS_MODE_1, TEMOD_PLL_MODE_DIV_50, 0, 0, 1}, 160 /*SPD_10G_CX2 15*/ { 2, TEMOD_PMA_OS_MODE_1, TEMOD_PLL_MODE_DIV_50, 0, 0, 1}, 161 /*SPD_10G_X2 16*/ { 2, TEMOD_PMA_OS_MODE_1, TEMOD_PLL_MODE_DIV_50, 1, 0, 1}, 162 /*SPD_20G_X4 17*/ { 4, TEMOD_PMA_OS_MODE_1, TEMOD_PLL_MODE_DIV_50, 1, 0, 1}, 163 /*SPD_10p5G_X2 18*/ { 2, TEMOD_PMA_OS_MODE_1, TEMOD_PLL_MODE_DIV_ILLEGAL, 1, 0, 0}, 164 /*SPD_21G_X4 19*/ { 4, TEMOD_PMA_OS_MODE_1, TEMOD_PLL_MODE_DIV_ILLEGAL, 1, 0, 0}, 165 /*SPD_12p7G_X2 20*/ { 2, TEMOD_PMA_OS_MODE_1, TEMOD_PLL_MODE_DIV_ILLEGAL, 1, 0, 0}, 166 /*SPD_25p45G_X4 21*/ { 4, TEMOD_PMA_OS_MODE_1, TEMOD_PLL_MODE_DIV_ILLEGAL, 1, 0, 0}, 167 /*SPD_15p75G_X2 22*/ { 2, TEMOD_PMA_OS_MODE_1, TEMOD_PLL_MODE_DIV_ILLEGAL, 1, 0, 0}, 168 /*SPD_31p5G_X4 23*/ { 4, TEMOD_PMA_OS_MODE_1, TEMOD_PLL_MODE_DIV_ILLEGAL, 1, 0, 0}, 169 /*SPD_31p5G_KR4 24*/ { 4, TEMOD_PMA_OS_MODE_1, TEMOD_PLL_MODE_DIV_ILLEGAL, 1, 0, 0}, 170 /*SPD_20G_CX2 25*/ { 2, TEMOD_PMA_OS_MODE_1, TEMOD_PLL_MODE_DIV_82P5, 1, 0, 0}, 171 /*SPD_20G_X2 26*/ { 2, TEMOD_PMA_OS_MODE_1, TEMOD_PLL_MODE_DIV_82P5, 1, 0, 0}, 172 /*SPD_40G_X4 27*/ { 4, TEMOD_PMA_OS_MODE_1, TEMOD_PLL_MODE_DIV_82P5, 1, 0, 0}, 173 /*SPD_10G_KR1 28*/ { 0, TEMOD_PMA_OS_MODE_1, TEMOD_PLL_MODE_DIV_82P5, 1, 0, 0}, 174 /*SPD_10p6_X1 29*/ { 0, TEMOD_PMA_OS_MODE_1, TEMOD_PLL_MODE_DIV_87P5, 1, 0, 0}, 175 /*SPD_20G_KR2 30*/ { 2, TEMOD_PMA_OS_MODE_1, TEMOD_PLL_MODE_DIV_82P5, 1, 0, 0}, 176 /*SPD_20G_CR2 31*/ { 2, TEMOD_PMA_OS_MODE_1, TEMOD_PLL_MODE_DIV_82P5, 1, 0, 0}, 177 /*SPD_21G_X2 32*/ { 2, TEMOD_PMA_OS_MODE_1, TEMOD_PLL_MODE_DIV_87P5, 1, 0, 0}, 178 /*SPD_40G_KR4 33*/ { 4, TEMOD_PMA_OS_MODE_1, TEMOD_PLL_MODE_DIV_82P5, 1, 0, 0}, 179 /*SPD_40G_CR4 34*/ { 4, TEMOD_PMA_OS_MODE_1, TEMOD_PLL_MODE_DIV_82P5, 1, 0, 0}, 180 /*SPD_42G_X4 35*/ { 4, TEMOD_PMA_OS_MODE_1, TEMOD_PLL_MODE_DIV_87P5, 1, 0, 0}, 181 /*SPD_100G_CR10 36*/ {10, TEMOD_PMA_OS_MODE_1, TEMOD_PLL_MODE_DIV_82P5, 1, 0, 0}, 182 /*SPD_107G_CR10 37*/ {10, TEMOD_PMA_OS_MODE_1, TEMOD_PLL_MODE_DIV_87P5, 1, 0, 0}, 183 /*SPD_120G_X12 38*/ {12, TEMOD_PMA_OS_MODE_1, TEMOD_PLL_MODE_DIV_82P5, 1, 0, 0}, 184 /*SPD_127G_X12 39*/ {12, TEMOD_PMA_OS_MODE_1, TEMOD_PLL_MODE_DIV_87P5, 1, 0, 0}, 185 /*SPD_ILLEGAL 40*/ { 0, TEMOD_PMA_OS_MODE_5, TEMOD_PLL_MODE_DIV_40, 0, 0, 0}, 186 /*SPD_ILLEGAL 41*/ { 0, TEMOD_PMA_OS_MODE_5, TEMOD_PLL_MODE_DIV_40, 0, 0, 0}, 187 /*SPD_ILLEGAL 42*/ { 0, TEMOD_PMA_OS_MODE_5, TEMOD_PLL_MODE_DIV_40, 0, 0, 0}, 188 /*SPD_ILLEGAL 43*/ { 0, TEMOD_PMA_OS_MODE_5, TEMOD_PLL_MODE_DIV_40, 0, 0, 0}, 189 /*SPD_ILLEGAL 44*/ { 0, TEMOD_PMA_OS_MODE_5, TEMOD_PLL_MODE_DIV_40, 0, 0, 0}, 190 /*SPD_ILLEGAL 45*/ { 0, TEMOD_PMA_OS_MODE_5, TEMOD_PLL_MODE_DIV_40, 0, 0, 0}, 191 /*SPD_ILLEGAL 46*/ { 0, TEMOD_PMA_OS_MODE_5, TEMOD_PLL_MODE_DIV_40, 0, 0, 0}, 192 /*SPD_ILLEGAL 47*/ { 0, TEMOD_PMA_OS_MODE_5, TEMOD_PLL_MODE_DIV_40, 0, 0, 0}, 193 /*SPD_ILLEGAL 48*/ { 0, TEMOD_PMA_OS_MODE_5, TEMOD_PLL_MODE_DIV_40, 0, 0, 0}, 194 /*SPD_5G_KR1 49*/ { 0, TEMOD_PMA_OS_MODE_2, TEMOD_PLL_MODE_DIV_82P5, 0, 0, 0}, 195 /*SPD_10p5G_X4 50*/ { 4, TEMOD_PMA_OS_MODE_2, TEMOD_PLL_MODE_DIV_42, 0, 0, 0}, 196 /*SPD_ILLEGAL 51*/ { 0, TEMOD_PMA_OS_MODE_5, TEMOD_PLL_MODE_DIV_40, 0, 0, 0}, 197 /*SPD_ILLEGAL 52*/ { 0, TEMOD_PMA_OS_MODE_5, TEMOD_PLL_MODE_DIV_40, 0, 0, 0}, 198 /*SPD_10M_10p3125 53*/ { 1, TEMOD_PMA_OS_MODE_8_25, TEMOD_PLL_MODE_DIV_82P5, 0, 0, 0}, 199 /*SPD_100M_10p3125 54*/ { 1, TEMOD_PMA_OS_MODE_8_25, TEMOD_PLL_MODE_DIV_82P5, 0, 0, 0}, 200 /*SPD_1000M_10p3125 55*/ { 1, TEMOD_PMA_OS_MODE_8_25, TEMOD_PLL_MODE_DIV_82P5, 0, 0, 0}, 201 /*SPD_2p5G_X1_10p3125 56*/ { 1, TEMOD_PMA_OS_MODE_3_3,TEMOD_PLL_MODE_DIV_82P5, 0, 0, 0}, 202 /*SPD_ILLEGAL 57*/ { 0, TEMOD_PMA_OS_MODE_5, TEMOD_PLL_MODE_DIV_50, 0, 0, 0} 203 204 }; 205 206 207 int _temod_wait_sc_stats_set(PHYMOD_ST* pc); 208 209 #ifdef _DV_TB_ 210 int _configure_sc_speed_configuration(PHYMOD_ST* pc); 211 int _init_pcs_fs(PHYMOD_ST* pc); 212 int _init_pcs_an(PHYMOD_ST* pc); 213 int _configure_st_entry(int st_entry_num, int st_entry_speed, PHYMOD_ST* pc); 214 int temod_set_an_port_mode(PHYMOD_ST* pc); 215 int temod_autoneg_set(PHYMOD_ST* pc); 216 int temod_autoneg_control(PHYMOD_ST* pc); 217 int temod_clause72_control(PHYMOD_ST* pc, cl72_type_t cl_72_type); 218 int temod_prbs_check(PHYMOD_ST* pc, int real_check, int *prbs_status); 219 int temod_prbs_mode(PHYMOD_ST* pc, int port, int prbs_inv, int pat, int check_mode); 220 int temod_prbs_control(PHYMOD_ST* pc, int prbs_enable); 221 int temod_prbs_rx_enable_set(PHYMOD_ST* pc, int enable); 222 int temod_prbs_tx_enable_set(PHYMOD_ST* pc, int enable); 223 int temod_prbs_rx_invert_data_set(PHYMOD_ST* pc, int invert_data); 224 int temod_prbs_rx_check_mode_set(PHYMOD_ST* pc, int check_mode); 225 int temod_prbs_tx_invert_data_set(PHYMOD_ST* pc, int invert_data); 226 int temod_prbs_tx_polynomial_set(PHYMOD_ST* pc, eagle_prbs_polynomial_type_t prbs_polynomial); 227 int temod_prbs_rx_polynomial_set(PHYMOD_ST* pc, eagle_prbs_polynomial_type_t prbs_polynomial); 228 int temod_pmd_addr_lane_swap(PHYMOD_ST *pc, uint32_t addr_lane_index); 229 int temod_check_sc_stats(PHYMOD_ST* pc); 230 #endif /* _DV_TB_ */ 231 232 /*! 233 @brief This function returns lock status of PLL 234 @param pc handle to current TSCE context (#PHYMOD_ST) 235 @param lockStatus reference which is updated with lock status. 236 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 237 @details This function reads TX-PLL PLL_LOCK bit to get the PLL lock status. 238 Returns 1 or 0 (locked/not). 239 */ 240 241 int temod_pll_lock_get(PHYMOD_ST* pc, int* lockStatus) 242 { 243 PMD_X1_STSr_t reg_pmd_x1_sts; 244 TEMOD_DBG_IN_FUNC_INFO(pc); 245 READ_PMD_X1_STSr(pc, ®_pmd_x1_sts); 246 247 *lockStatus = PMD_X1_STSr_PLL_LOCK_STSf_GET(reg_pmd_x1_sts); 248 TEMOD_DBG_IN_FUNC_VOUT_INFO(pc,("PLL lockStatus: %d", *lockStatus)); 249 return PHYMOD_E_NONE; 250 } 251 252 /** 253 @brief This function returns the locked status of PMD. 254 @param pc handle to current TSCE context (#PHYMOD_ST) 255 @param lockStatus reference which is updated with pmd_lock status 256 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 257 @details This function reads RX-PMD PMD_LOCK bit to get the locked status of 258 PMD. PMD lock status also indicates CDR (clock recovered from data received). 259 Returns 1 or 0 (locked/not) 260 */ 261 #ifdef _DV_TB_ 262 int temod_pmd_lock_get(PHYMOD_ST* pc, uint32_t* lockStatus) 263 { 264 PMD_X4_STSr_t reg_pmd_x4_sts; 265 int i; 266 int lane_mask; 267 PHYMOD_ST* pc_copy; 268 TEMOD_DBG_IN_FUNC_INFO(pc); 269 270 pc_copy = pc; 271 pc_copy->port_type = TEMOD_MULTI_PORT; 272 lane_mask = 0; 273 switch(pc->port_type) { 274 case TEMOD_MULTI_PORT: lane_mask = 0x1 << pc->this_lane; break; 275 case TEMOD_TRI1_PORT: if(pc->this_lane == 3) lane_mask = 0xc; 276 else lane_mask = 0x1 << pc->this_lane; 277 break; 278 case TEMOD_TRI2_PORT: if(pc->this_lane == 0) lane_mask = 0x3; 279 else lane_mask = 0x1 << pc->this_lane; 280 break; 281 case TEMOD_DXGXS: if(pc->this_lane == 0) lane_mask = 0x3; 282 else lane_mask = 0xc; 283 break; 284 case TEMOD_SINGLE_PORT: lane_mask = 0xf; break; 285 default: break; 286 } 287 288 *lockStatus = 1; 289 for(i=0; i<4; i++) { 290 if(((lane_mask >> i) & 0x1) == 1) { 291 pc_copy.this_lane = i; 292 READ_PMD_X4_STSr(pc_copy, ®_pmd_x4_sts); 293 *lockStatus = *lockStatus & PMD_X4_STSr_RX_LOCK_STSf_GET(reg_pmd_x4_sts); 294 } 295 } 296 /* TEMOD_DBG_IN_FUNC_VOUT_INFO(pc,("PMD lockStatus: %d", *lockStatus)); */ 297 298 return PHYMOD_E_NONE; 299 } 300 301 #endif 302 303 #ifdef _SDK_TEMOD_ 304 int temod_pmd_lock_get(PHYMOD_ST* pc, uint32_t* lockStatus) 305 { 306 PMD_X4_STSr_t reg_pmd_x4_sts; 307 int i=0, start_lane=0, num_lane=0; 308 phymod_access_t pa_copy; 309 TEMOD_DBG_IN_FUNC_INFO(pc); 310 311 *lockStatus = 1; 312 PHYMOD_MEMCPY(&pa_copy, pc, sizeof(pa_copy)); 313 314 PHYMOD_IF_ERR_RETURN 315 (phymod_util_lane_config_get(pc, &start_lane, &num_lane)); 316 317 for(i=0; i<num_lane; i++) { 318 if(((pc->lane_mask >> (start_lane+i)) & 0x1) == 1) { 319 pa_copy.lane_mask |= 0x1 << (start_lane+i); 320 READ_PMD_X4_STSr(&pa_copy, ®_pmd_x4_sts); 321 *lockStatus = *lockStatus & PMD_X4_STSr_RX_LOCK_STSf_GET(reg_pmd_x4_sts); 322 } 323 } 324 325 /* TEMOD_DBG_IN_FUNC_VOUT_INFO(pc,("PMD lockStatus: %d", *lockStatus)); */ 326 327 return PHYMOD_E_NONE; 328 } 329 #endif 330 331 332 #ifdef _DV_TB_ 333 /* 334 @brief This function waits for TX-PLL PLL_LOCK bit. The register is one copy 335 @param pc handle to current TSCE context (#PHYMOD_ST) 336 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 337 @details Wait for PLL to lock. Cannot be used in SDK. 338 */ 339 340 int temod_pll_lock_wait(PHYMOD_ST* pc, int timeOutValue) 341 { 342 int rv; 343 TEMOD_DBG_IN_FUNC_INFO(pc); 344 TEMOD_DBG_IN_FUNC_VIN_INFO(pc,("pll_lock_wait timeOutValue: %d", timeOutValue)); 345 346 rv = temod_regbit_set_wait_check(pc, 347 0x9012, 348 1, 1, timeOutValue); 349 /* TBD PMD_X1_STATUS_PLL_LOCK_STS_MASK, 1, timeOutValue); */ 350 if (rv == SOC_E_TIMEOUT) { 351 PHYMOD_DEBUG_ERROR(("%-22s ERROR: p=%0d Timeout PLL lock:\n", __func__, pc->port)); 352 return (SOC_E_TIMEOUT); 353 } 354 return PHYMOD_E_NONE; 355 } 356 #endif 357 358 #ifdef _DV_TB_ 359 /* 360 @brief This function waits for the the RX-PMD to lock. 361 @param pc handle to current TSCE context (#PHYMOD_ST) 362 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 363 @details This function has a time out limit (TE_PLL_WAIT*50) micro-second in driver. 364 or TE_PLL_WAIT/20 pulling count in simualtion, if per_lane_control is set. Otherwise, 365 if per_lane_control==0, it reads back PMD_LIVE_STATUS and put it on accData. 366 */ 367 int temod_wait_pmd_lock(PHYMOD_ST* pc, int timeOutValue, int* lockStatus) 368 { 369 int rv; 370 PMD_X4_STSr_t reg_pmd_x4_stats; 371 TEMOD_DBG_IN_FUNC_INFO(pc); 372 TEMOD_DBG_IN_FUNC_VIN_INFO(pc,("pmd lock wait timeOutValue: %d", timeOutValue)); 373 374 PMD_X4_STSr_CLR(reg_pmd_x4_stats); 375 376 if(pc->per_lane_control) { 377 rv = temod_regbit_set_wait_check(pc, 0xc012, 1,1,timeOutValue); 378 /* TBD PMD_X4_STATUS_RX_LOCK_STS_MASK,1,timeOutValue); */ 379 380 if (rv == SOC_E_TIMEOUT) { 381 PHYMOD_DEBUG_ERROR(("%-22s ERROR: P=%0d Timeout RX PMD lock:\n", __func__, pc->port)); 382 pc->accData = 0; 383 *lockStatus = 0; 384 return rv; 385 } else { 386 pc->accData = 1; 387 *lockStatus = 1; 388 } 389 } else { 390 READ_PMD_X4_STSr(pc, ®_pmd_x4_stats); 391 if(PMD_X4_STSr_RX_LOCK_STSf_GET(reg_pmd_x4_stats)) { 392 pc->accData = 1; 393 *lockStatus = 1; 394 } else { 395 pc->accData = 0; 396 *lockStatus = 0; 397 } 398 } 399 TEMOD_DBG_IN_FUNC_VOUT_INFO(pc,("pmd lockStatus: %d", *lockStatus)); 400 401 return (PHYMOD_E_NONE); 402 } 403 #endif 404 405 #ifdef _DV_TB_ 406 /** 407 @brief controls PCS Bypass Control function. 408 @param pc handle to current TSCE context (#PHYMOD_ST) 409 @param cntl Control value (bypass, un-bypass) 410 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 411 @details Set cntl <B>0 to disable</B> PCS and <B>1 to enable</B> PCS When 412 bypassed, PCS relinquishes control of PMD resets. The PHY driver, TEMod can take 413 complete control of PMD programming. Bypass is also used in ILKN mode where the 414 PCS is not used. 415 */ 416 417 int temod_pcs_bypass_ctl (PHYMOD_ST* pc, int cntl) 418 { 419 SC_X4_BYPASSr_t reg_sc_bypass; 420 421 TEMOD_DBG_IN_FUNC_INFO(pc); 422 TEMOD_DBG_IN_FUNC_VIN_INFO(pc,("Cntl is:%d",cntl)); 423 424 SC_X4_BYPASSr_CLR(reg_sc_bypass); 425 426 if (cntl==TEMOD_SC_MODE_BYPASS) { 427 SC_X4_BYPASSr_SC_BYPASSf_SET(reg_sc_bypass, 1); 428 } else { 429 SC_X4_BYPASSr_SC_BYPASSf_SET(reg_sc_bypass, 0); 430 } 431 432 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X4_BYPASSr( pc, reg_sc_bypass)); 433 434 return PHYMOD_E_NONE; 435 } 436 #endif /* _DV_TB_ */ 437 438 439 #ifdef _DV_TB_ 440 /** 441 @brief Controls PMD datapath resets. 442 @param pc handle to current TSCE context (#PHYMOD_ST) 443 @param cntl Controls if PMD should be reset or unset 444 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 445 @details Set cntl arg <B>0</B>:disable <B>1</B>: enable 446 The PMD datapath is reset even if PCS is actively controlling PMD resets. 447 There are two types of control. One per lane and one per Core. 448 */ 449 int temod_pmd_reset_bypass (PHYMOD_ST* pc, int cntl) /* PMD_RESET_BYPASS */ 450 { 451 int lnCntl, coreCntl; 452 lnCntl = cntl & 0x10 ; 453 coreCntl = cntl & 0x1 ; 454 PMD_X4_OVRRr_t reg_pmd_x4_or; 455 PMD_X4_CTLr_t reg_pmd_x4_ctrl; 456 PMD_X1_OVRRr_t reg_pmd_x1_or; 457 PMD_X1_CTLr_t reg_pmd_x1_ctrl; 458 SC_X4_CTLr_t reg_sc_ctrl; 459 460 TEMOD_DBG_IN_FUNC_INFO(pc); 461 TEMOD_DBG_IN_FUNC_VIN_INFO(pc,("Cntl is:%d",cntl)); 462 463 PMD_X4_OVRRr_CLR(reg_pmd_x4_or); 464 PMD_X4_CTLr_CLR(reg_pmd_x4_ctrl); 465 PMD_X1_OVRRr_CLR(reg_pmd_x1_or); 466 PMD_X1_CTLr_CLR(reg_pmd_x1_ctrl); 467 SC_X4_CTLr_CLR(reg_sc_ctrl); 468 469 if (lnCntl) { 470 PMD_X4_OVRRr_LN_DP_H_RSTB_OENf_SET(reg_pmd_x4_or, 1); 471 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X4_OVRRr(pc, reg_pmd_x4_or)); 472 473 PMD_X4_CTLr_LN_DP_H_RSTBf_SET(reg_pmd_x4_ctrl, 0); 474 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X4_CTLr(pc, reg_pmd_x4_ctrl)); 475 476 /* toggle added */ 477 PMD_X4_OVRRr_CLR(reg_pmd_x4_or); 478 PMD_X4_CTLr_CLR(reg_pmd_x4_ctrl); 479 480 PMD_X4_CTLr_LN_DP_H_RSTBf_SET(reg_pmd_x4_ctrl, 1); 481 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X4_CTLr(pc, reg_pmd_x4_ctrl)); 482 483 PMD_X4_OVRRr_LN_DP_H_RSTB_OENf_SET(reg_pmd_x4_or, 0); 484 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X4_OVRRr(pc, reg_pmd_x4_or)); 485 486 } else { 487 PMD_X4_OVRRr_LN_DP_H_RSTB_OENf_SET(reg_pmd_x4_or, 0); 488 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X4_OVRRr(pc, reg_pmd_x4_or)); 489 490 PMD_X4_CTLr_LN_DP_H_RSTBf_SET(reg_pmd_x4_ctrl, 1); 491 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X4_CTLr(pc, reg_pmd_x4_ctrl)); 492 } 493 494 if (coreCntl) { 495 PMD_X1_OVRRr_CORE_DP_H_RSTB_OENf_SET(reg_pmd_x1_or, 1); 496 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X1_OVRRr(pc, reg_pmd_x1_or)); 497 498 PMD_X1_CTLr_CORE_DP_H_RSTBf_SET(reg_pmd_x1_ctrl, 0); 499 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X1_CTLr(pc, reg_pmd_x1_ctrl)); 500 501 /* toggle added */ 502 PMD_X1_OVRRr_CLR(reg_pmd_x1_or); 503 PMD_X1_CTLr_CLR(reg_pmd_x1_ctrl); 504 PMD_X1_CTLr_CORE_DP_H_RSTBf_SET(reg_pmd_x1_ctrl, 1); 505 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X1_CTLr(pc, reg_pmd_x1_ctrl)); 506 507 PMD_X1_OVRRr_CORE_DP_H_RSTB_OENf_SET(reg_pmd_x1_or, 0); 508 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X1_OVRRr(pc, reg_pmd_x1_or)); 509 510 } else { 511 PMD_X1_OVRRr_CORE_DP_H_RSTB_OENf_SET(reg_pmd_x1_or, 0); 512 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X1_OVRRr(pc, reg_pmd_x1_or)); 513 514 PMD_X1_CTLr_CORE_DP_H_RSTBf_SET(reg_pmd_x1_ctrl, 1); 515 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X1_CTLr(pc, reg_pmd_x1_ctrl)); 516 } 517 518 /* sw_speed_change toggled */ 519 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(reg_sc_ctrl, 0); 520 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_CTLr(pc, reg_sc_ctrl)); 521 522 SC_X4_CTLr_CLR(reg_sc_ctrl); 523 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(reg_sc_ctrl, 1); 524 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_CTLr(pc, reg_sc_ctrl)); 525 526 return PHYMOD_E_NONE; 527 528 } /* PMD_RESET_BYPASS */ 529 #endif 530 531 #ifdef _SDK_TEMOD_ 532 /*! 533 @brief Controls the initial setting/resetting of autoneg related registers. 534 @param pc handle to current TSCE context (#PHYMOD_ST) 535 @param an_init_st structure with all the onr time autoneg init cfg. 536 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 537 @details Get aneg features from upper software layers via #temod_an_init_t. 538 and prepare the PHY for autoneg by populating the advertisements 539 and autonegotiation modes. It does not start or control the autoneg process. That is done 540 in #temod_autoneg_control 541 */ 542 int temod_autoneg_set_init(PHYMOD_ST* pc, temod_an_init_t *an_init_st) /* AUTONEG_SET */ 543 { 544 AN_X4_CTLSr_t reg_an_ctrl; 545 DIG_CTL1000X2r_t reg_ctrl1000x2; 546 AN_X4_LOC_DEV_CL73_BASE_ABIL1r_t reg_an_cl73_abl_1; 547 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_t reg_cl73_abiilities; 548 549 TEMOD_DBG_IN_FUNC_INFO(pc); 550 AN_X4_CTLSr_CLR(reg_an_ctrl); 551 AN_X4_CTLSr_AN_FAIL_COUNT_LIMITf_SET(reg_an_ctrl, an_init_st->an_fail_cnt); 552 AN_X4_CTLSr_OUI_CONTROLf_SET(reg_an_ctrl, an_init_st->an_oui_ctrl); 553 AN_X4_CTLSr_LINKFAILTIMER_DISf_SET(reg_an_ctrl, an_init_st->linkfailtimer_dis); 554 AN_X4_CTLSr_LINKFAILTIMERQUAL_ENf_SET(reg_an_ctrl, an_init_st->linkfailtimerqua_en); 555 AN_X4_CTLSr_AN_GOOD_CHECK_TRAPf_SET(reg_an_ctrl, an_init_st->an_good_check_trap); 556 AN_X4_CTLSr_AN_GOOD_TRAPf_SET(reg_an_ctrl, an_init_st->an_good_trap); 557 PHYMOD_IF_ERR_RETURN(WRITE_AN_X4_CTLSr(pc, reg_an_ctrl)); 558 559 DIG_CTL1000X2r_CLR(reg_ctrl1000x2); 560 DIG_CTL1000X2r_DISABLE_REMOTE_FAULT_REPORTINGf_SET(reg_ctrl1000x2, an_init_st->disable_rf_report); 561 PHYMOD_IF_ERR_RETURN(MODIFY_DIG_CTL1000X2r(pc, reg_ctrl1000x2)); 562 563 AN_X4_LOC_DEV_CL73_BASE_ABIL1r_CLR(reg_an_cl73_abl_1); 564 AN_X4_LOC_DEV_CL73_BASE_ABIL1r_CL73_NONCE_MATCH_OVERf_SET(reg_an_cl73_abl_1, an_init_st->cl73_nonce_match_over); 565 AN_X4_LOC_DEV_CL73_BASE_ABIL1r_CL73_NONCE_MATCH_VALf_SET(reg_an_cl73_abl_1, an_init_st->cl73_nonce_match_val); 566 AN_X4_LOC_DEV_CL73_BASE_ABIL1r_BASE_SELECTORf_SET(reg_an_cl73_abl_1, an_init_st->base_selector); 567 AN_X4_LOC_DEV_CL73_BASE_ABIL1r_TRANSMIT_NONCEf_SET(reg_an_cl73_abl_1, ( an_init_st->cl73_transmit_nonce & 0x1f)); 568 PHYMOD_IF_ERR_RETURN ( MODIFY_AN_X4_LOC_DEV_CL73_BASE_ABIL1r(pc, reg_an_cl73_abl_1)); 569 570 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_CLR(reg_cl73_abiilities); 571 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_CL73_REMOTE_FAULTf_SET(reg_cl73_abiilities, ( an_init_st->cl73_remote_fault & 1)); 572 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_LOC_DEV_CL73_BASE_ABIL0r(pc, reg_cl73_abiilities)); 573 574 return PHYMOD_E_NONE; 575 } 576 #endif 577 578 #ifdef _SDK_TEMOD_ 579 /*! 580 @brief Controls the setting/resetting of autoneg timers. 581 @param pc handle to current TSCE context (#PHYMOD_ST) 582 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 583 @details This function gets specific aneg timer related information from upper 584 software layers via #PHYMOD_ST->an_tech_ability and updates the autoneg pages. 585 This does not start autonegotiation. That is done in #temod_autoneg_control 586 */ 587 588 int temod_autoneg_timer_init(PHYMOD_ST* pc) /* AUTONEG timer set*/ 589 { 590 AN_X1_CL37_RESTARTr_t reg_cl37_restart; 591 AN_X1_CL37_ACKr_t reg_cl37_ack; 592 AN_X1_CL73_BRK_LNKr_t reg_cl73_break_link; 593 AN_X1_CL73_DME_LOCKr_t reg_cl73_dme_lock; 594 AN_X1_LNK_UPr_t reg_link_up; 595 AN_X1_LNK_FAIL_INHBT_TMR_CL72r_t reg_inhibit_timer; 596 AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72r_t reg_inhibit_not_timer; 597 AN_X1_PD_SD_TMRr_t reg_pd_sd_timer; 598 AN_X1_CL37_SYNC_STS_FILTER_TMRr_t reg_sync_status_filter_timer; 599 AN_X1_PD_TO_CL37_LNK_WAIT_TMRr_t reg_link_wait_timer; 600 AN_X1_IGNORE_LNK_TMRr_t reg_ignore_link_timer; 601 AN_X1_DME_PAGE_TMRr_t reg_dme_page_timer; 602 AN_X1_SGMII_CL73_TMR_TYPEr_t reg_sgmii_cl73_timer; 603 604 TEMOD_DBG_IN_FUNC_INFO(pc); 605 /*0x9250 AN_X1_TIMERS_cl37_restart */ 606 AN_X1_CL37_RESTARTr_CLR(reg_cl37_restart); 607 AN_X1_CL37_RESTARTr_SET(reg_cl37_restart, 0x29a ); 608 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_CL37_RESTARTr(pc, reg_cl37_restart)); 609 610 /*0x9251 AN_X1_TIMERS_cl37_ack */ 611 AN_X1_CL37_ACKr_CLR(reg_cl37_ack); 612 AN_X1_CL37_ACKr_SET(reg_cl37_ack, 0x29a); 613 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_CL37_ACKr(pc, reg_cl37_ack)); 614 615 /*0x9253 AN_X1_TIMERS_cl73_break_link */ 616 AN_X1_CL73_BRK_LNKr_CLR(reg_cl73_break_link); 617 AN_X1_CL73_BRK_LNKr_SET(reg_cl73_break_link, 0x10ed); 618 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_CL73_BRK_LNKr(pc, reg_cl73_break_link)); 619 620 /*TBD::0x9255 AN_X1_TIMERS_cl73_dme_lock*/ 621 AN_X1_CL73_DME_LOCKr_CLR(reg_cl73_dme_lock); 622 AN_X1_CL73_DME_LOCKr_SET(reg_cl73_dme_lock, 0x14d4); 623 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_CL73_DME_LOCKr(pc, reg_cl73_dme_lock)); 624 625 /*TBD::0x9256 AN_X1_TIMERS_link_up*/ 626 AN_X1_LNK_UPr_CLR(reg_link_up); 627 AN_X1_LNK_UPr_SET(reg_link_up, 0x29a); 628 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_LNK_UPr(pc, reg_link_up)); 629 630 /*0x9257 AN_X1_TIMERS_link_fail_inhibit_timer_cl72*/ 631 AN_X1_LNK_FAIL_INHBT_TMR_CL72r_CLR(reg_inhibit_timer); 632 AN_X1_LNK_FAIL_INHBT_TMR_CL72r_SET(reg_inhibit_timer, 0x8382); 633 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_LNK_FAIL_INHBT_TMR_CL72r(pc, reg_inhibit_timer)); 634 635 /*0x9258 AN_X1_TIMERS_link_fail_inhibit_timer_not_cl72*/ 636 AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72r_CLR(reg_inhibit_not_timer); 637 /* AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72r_SET(reg_inhibit_not_timer, 0xbb8); */ 638 /* AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72r_SET(reg_inhibit_not_timer, 0x14d5); */ 639 AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72r_SET(reg_inhibit_not_timer, 0x8382); 640 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72r(pc, reg_inhibit_not_timer)); 641 642 /*0x9259 AN_X1_TIMERS_pd_sd_timer*/ 643 AN_X1_PD_SD_TMRr_CLR(reg_pd_sd_timer); 644 AN_X1_PD_SD_TMRr_SET(reg_pd_sd_timer, 0xa6a); 645 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_PD_SD_TMRr(pc, reg_pd_sd_timer)); 646 647 /*0x925a AN_X1_TIMERS_cl72_max_wait_timer*/ 648 AN_X1_CL37_SYNC_STS_FILTER_TMRr_CLR(reg_sync_status_filter_timer); 649 AN_X1_CL37_SYNC_STS_FILTER_TMRr_SET(reg_sync_status_filter_timer, 0x29a); 650 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_CL37_SYNC_STS_FILTER_TMRr(pc, reg_sync_status_filter_timer)); 651 652 /*0x925b AN_X1_TIMERS_PD_TO_CL37_LINK_WAIT_TIMER*/ 653 AN_X1_PD_TO_CL37_LNK_WAIT_TMRr_CLR(reg_link_wait_timer); 654 AN_X1_PD_TO_CL37_LNK_WAIT_TMRr_SET(reg_link_wait_timer, 0xa6a); 655 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_PD_TO_CL37_LNK_WAIT_TMRr(pc, reg_link_wait_timer)); 656 657 /*0x925c AN_X1_TIMERS_ignore_link_timer*/ 658 AN_X1_IGNORE_LNK_TMRr_CLR(reg_ignore_link_timer); 659 AN_X1_IGNORE_LNK_TMRr_SET(reg_ignore_link_timer, 0x29a); 660 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_IGNORE_LNK_TMRr(pc, reg_ignore_link_timer)); 661 662 /*0x925d AN_X1_TIMERS_dme_page_timer*/ 663 AN_X1_DME_PAGE_TMRr_CLR(reg_dme_page_timer); 664 AN_X1_DME_PAGE_TMRr_SET(reg_dme_page_timer, 0x3b5f); 665 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_DME_PAGE_TMRr(pc, reg_dme_page_timer)); 666 667 /*0x925e AN_X1_TIMERS_sgmii_cl73_timer_type*/ 668 AN_X1_SGMII_CL73_TMR_TYPEr_CLR(reg_sgmii_cl73_timer); 669 AN_X1_SGMII_CL73_TMR_TYPEr_SET(reg_sgmii_cl73_timer, 0x6b); 670 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_SGMII_CL73_TMR_TYPEr(pc, reg_sgmii_cl73_timer)); 671 return PHYMOD_E_NONE; 672 } 673 #endif 674 675 #ifdef _SDK_TEMOD_ 676 /*! 677 @brief Controls initializing CL48 lf/rf/li. 678 @param pc handle to current TSCE context (#PHYMOD_ST) 679 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 680 @details This function gets specific aneg timer related information from upper 681 software layers via #PHYMOD_ST->an_tech_ability and updates the autoneg pages. 682 This does not start autonegotiation. That is done in #temod_autoneg_control 683 */ 684 int temod_cl48_lfrfli_init(PHYMOD_ST* pc) /* AUTONEG timer set*/ 685 { 686 TX_X2_CL48_0r_t reg_cl48_ctl ; 687 688 TEMOD_DBG_IN_FUNC_INFO(pc); 689 TX_X2_CL48_0r_CLR(reg_cl48_ctl) ; 690 TX_X2_CL48_0r_CL48_TX_LI_ENABLEf_SET(reg_cl48_ctl,1) ; 691 TX_X2_CL48_0r_CL48_TX_LF_ENABLEf_SET(reg_cl48_ctl,1) ; 692 TX_X2_CL48_0r_CL48_TX_RF_ENABLEf_SET(reg_cl48_ctl,1) ; 693 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X2_CL48_0r(pc, reg_cl48_ctl)); 694 695 return PHYMOD_E_NONE; 696 } 697 #endif 698 699 /** 700 @brief Controls the setting/resetting of autoneg advertisement registers. 701 @param pc handle to current TSCE context (#PHYMOD_ST) 702 @param an_ability_st handle to current abilities struct #temod_an_ability_t 703 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 704 @details This function gets specific aneg related information from upper 705 software layers via #PHYMOD_ST->an_tech_ability and updates the autoneg pages. 706 This does not start autonegotiation. That is done in #temod_autoneg_control 707 */ 708 #ifdef _DV_TB_ 709 int temod_autoneg_set(PHYMOD_ST* pc) /* AUTONEG_SET */ 710 { 711 AN_X4_CTLSr_t reg_an_ctrl; 712 DIG_CTL1000X2r_t reg_ctrl1000x2; 713 AN_X4_LOC_DEV_CL37_BASE_ABILr_t reg_cl37_base_abilities; 714 AN_X4_LOC_DEV_CL37_BAM_ABILr_t reg_cl37_bam_abilities; 715 AN_X4_LOC_DEV_OVER1G_ABIL0r_t reg_over1g_abilities; 716 AN_X4_LOC_DEV_OVER1G_ABIL1r_t reg_over1g_abilities1; 717 AN_X4_LOC_DEV_CL73_BAM_ABILr_t reg_cl73_bam_abilities; 718 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_t reg_cl73_base_abilities; 719 720 TEMOD_DBG_IN_FUNC_INFO(pc); 721 AN_X4_CTLSr_CLR(reg_an_ctrl); 722 723 AN_X4_CTLSr_AN_FAIL_COUNT_LIMITf_SET(reg_an_ctrl, pc->an_fail_cnt); 724 AN_X4_CTLSr_OUI_CONTROLf_SET(reg_an_ctrl, pc->an_oui_ctrl); 725 AN_X4_CTLSr_PD_KX_ENf_SET(reg_an_ctrl, pc->pd_kx_en); 726 AN_X4_CTLSr_PD_KX4_ENf_SET(reg_an_ctrl, pc->pd_kx4_en); 727 AN_X4_CTLSr_LINKFAILTIMER_DISf_SET(reg_an_ctrl, pc->linkfailtimer_dis); 728 AN_X4_CTLSr_LINKFAILTIMERQUAL_ENf_SET(reg_an_ctrl, pc->linkfailtimerqua_en); 729 AN_X4_CTLSr_AN_GOOD_CHECK_TRAPf_SET(reg_an_ctrl, pc->an_good_check_trap); 730 AN_X4_CTLSr_AN_GOOD_TRAPf_SET(reg_an_ctrl, pc->an_good_trap); 731 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_CTLSr(pc, reg_an_ctrl)); 732 733 734 DIG_CTL1000X2r_CLR(reg_ctrl1000x2); 735 DIG_CTL1000X2r_DISABLE_REMOTE_FAULT_REPORTINGf_SET(reg_ctrl1000x2, pc->disable_rf_report); 736 PHYMOD_IF_ERR_RETURN(MODIFY_DIG_CTL1000X2r(pc, reg_ctrl1000x2)); 737 738 if(pc->sc_mode == TEMOD_SC_MODE_AN_CL37) { 739 /* an37 */ 740 if(!(pc->cl37_bam_en)){ 741 AN_X4_LOC_DEV_CL37_BASE_ABILr_CLR(reg_cl37_base_abilities); 742 AN_X4_LOC_DEV_CL37_BASE_ABILr_CL37_AN_RESTART_RESET_DISABLEf_SET(reg_cl37_base_abilities, 1); 743 AN_X4_LOC_DEV_CL37_BASE_ABILr_CL37_SW_RESTART_RESET_DISABLEf_SET (reg_cl37_base_abilities, 1); 744 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_LOC_DEV_CL37_BASE_ABILr(pc, reg_cl37_base_abilities)); 745 } 746 747 /*Local device cl37 base abilities setting*/ 748 /******* Pause Settings ********/ 749 AN_X4_LOC_DEV_CL37_BASE_ABILr_CLR(reg_cl37_base_abilities); 750 if(pc->cl37_an_pause){ 751 AN_X4_LOC_DEV_CL37_BASE_ABILr_CL37_PAUSEf_SET(reg_cl37_base_abilities, (pc->cl37_an_pause & 3)); 752 } 753 /******* Half duplex Settings ********/ 754 if(pc->cl37_an_hd){ 755 AN_X4_LOC_DEV_CL37_BASE_ABILr_CL37_HALF_DUPLEXf_SET(reg_cl37_base_abilities, (pc->cl37_an_hd & 1)); 756 } 757 /******* SGMII Master mode Settings ********/ 758 if(pc->cl37_sgmii_master_mode){ 759 AN_X4_LOC_DEV_CL37_BASE_ABILr_SGMII_MASTER_MODEf_SET(reg_cl37_base_abilities, (pc->cl37_sgmii_master_mode & 1)); 760 } 761 /******* SGMII Speed Settings ********/ 762 /*if(pc->cl37_sgmii_speed){ */ 763 AN_X4_LOC_DEV_CL37_BASE_ABILr_SGMII_SPEEDf_SET(reg_cl37_base_abilities, (pc->cl37_sgmii_speed & 3)); 764 /*}*/ 765 /******* CL37 Next page setting ********/ 766 if(pc->cl37_an_np){ 767 AN_X4_LOC_DEV_CL37_BASE_ABILr_CL37_NEXT_PAGEf_SET(reg_cl37_base_abilities, (pc->cl37_an_np & 1)); 768 } 769 /******* CL37 full duplex ********/ 770 if(pc->cl37_an_fd){ 771 AN_X4_LOC_DEV_CL37_BASE_ABILr_CL37_FULL_DUPLEXf_SET(reg_cl37_base_abilities, (pc->cl37_an_fd & 1)); 772 } 773 /******* SGMII duplex Settings ********/ 774 if(pc->cl37_sgmii_duplex){ 775 AN_X4_LOC_DEV_CL37_BASE_ABILr_SGMII_FULL_DUPLEXf_SET(reg_cl37_base_abilities, (pc->cl37_sgmii_duplex & 1)); 776 } 777 778 779 /***** Setting AN_X4_ABILITIES_ld_base_abilities_1 0xC181 *******/ 780 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_LOC_DEV_CL37_BASE_ABILr(pc, reg_cl37_base_abilities)); 781 782 /*Local device cl37 bam abilities setting*/ 783 784 /******* CL37 Bam AN_X4_ABILITIES_local_device_over1g_abilities_0 setting********/ 785 /* cl37 bam abilities 0xc182 */ 786 AN_X4_LOC_DEV_CL37_BAM_ABILr_CLR(reg_cl37_bam_abilities); 787 AN_X4_LOC_DEV_CL37_BAM_ABILr_CL37_BAM_CODEf_SET(reg_cl37_bam_abilities, (pc->cl37_bam_code & 0x1ff)); 788 AN_X4_LOC_DEV_CL37_BAM_ABILr_OVER1G_ABILITYf_SET(reg_cl37_bam_abilities, (pc->cl37_bam_ovr1g_en & 1)); 789 AN_X4_LOC_DEV_CL37_BAM_ABILr_OVER1G_PAGE_COUNTf_SET(reg_cl37_bam_abilities, (pc->cl37_bam_ovr1g_pgcnt & 3)); 790 791 PHYMOD_IF_ERR_RETURN 792 (MODIFY_AN_X4_LOC_DEV_CL37_BAM_ABILr(pc, reg_cl37_bam_abilities)); 793 794 795 AN_X4_LOC_DEV_OVER1G_ABIL0r_CLR(reg_over1g_abilities); 796 if(pc->cl37_bam_speed) 797 AN_X4_LOC_DEV_OVER1G_ABIL0r_SET(reg_over1g_abilities, (pc->cl37_bam_speed & 0x7ff)); 798 /***** Setting AN_X4_ABILITIES_local_device_over1g_abilities_0 0xC184 *******/ 799 PHYMOD_IF_ERR_RETURN(WRITE_AN_X4_LOC_DEV_OVER1G_ABIL0r(pc, reg_over1g_abilities)); 800 801 /******* CL37 Bam AN_X4_ABILITIES_local_device_over1g_abilities_1 setting********/ 802 AN_X4_LOC_DEV_OVER1G_ABIL1r_CLR(reg_over1g_abilities1); 803 if(pc->cl37_bam_speed) 804 AN_X4_LOC_DEV_OVER1G_ABIL1r_SET(reg_over1g_abilities1,pc->cl37_bam_speed >> 11); 805 /* AN_LOCAL_DEVICE_OVER1G_ABILITIES_1r_BAM_13GBASE_X4f_SET(reg_over1g_abilities1, (pc->cl37_bam_speed >> 11)); */ 806 if(pc->cl37_bam_fec) 807 AN_X4_LOC_DEV_OVER1G_ABIL1r_FECf_SET(reg_over1g_abilities1, (pc->cl37_bam_fec & 1)); 808 if(pc->cl37_bam_hg2) 809 AN_X4_LOC_DEV_OVER1G_ABIL1r_HG2f_SET(reg_over1g_abilities1, (pc->cl37_bam_hg2 & 1)); 810 if(pc->an_abilities_CL72) 811 AN_X4_LOC_DEV_OVER1G_ABIL1r_CL72f_SET(reg_over1g_abilities1, (pc->an_abilities_CL72 & 1)); 812 /***** Setting AN_X4_ABILITIES_local_device_over1g_abilities_0 0xC183 *******/ 813 PHYMOD_IF_ERR_RETURN(WRITE_AN_X4_LOC_DEV_OVER1G_ABIL1r(pc, reg_over1g_abilities1)); 814 } /*Completion of CL37 abilities*/ 815 /*CL73 abilities*/ 816 else if(pc->sc_mode == TEMOD_SC_MODE_AN_CL73) { 817 /*PD to CL37 Enable*/ 818 if(pc->an_pd_to_cl37_enable) { 819 AN_X4_LOC_DEV_CL37_BASE_ABILr_CLR(reg_cl37_base_abilities); 820 AN_X4_LOC_DEV_CL37_BASE_ABILr_AN_PD_TO_CL37_ENABLEf_SET(reg_cl37_base_abilities, 0x1); 821 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_LOC_DEV_CL37_BASE_ABILr(pc, reg_cl37_base_abilities)); 822 AN_X4_LOC_DEV_CL37_BASE_ABILr_CLR(reg_cl37_base_abilities); 823 if(pc->cl37_an_pause){ 824 AN_X4_LOC_DEV_CL37_BASE_ABILr_CL37_PAUSEf_SET(reg_cl37_base_abilities, (pc->cl37_an_pause & 3)); 825 } 826 /******* Half duplex Settings ********/ 827 if(pc->cl37_an_hd){ 828 AN_X4_LOC_DEV_CL37_BASE_ABILr_CL37_HALF_DUPLEXf_SET(reg_cl37_base_abilities, (pc->cl37_an_hd & 1)); 829 } 830 /******* SGMII Master mode Settings ********/ 831 if(pc->cl37_sgmii_master_mode){ 832 AN_X4_LOC_DEV_CL37_BASE_ABILr_SGMII_MASTER_MODEf_SET(reg_cl37_base_abilities, (pc->cl37_sgmii_master_mode & 1)); 833 } 834 /******* SGMII Speed Settings ********/ 835 if(pc->cl37_sgmii_speed){ 836 AN_X4_LOC_DEV_CL37_BASE_ABILr_SGMII_SPEEDf_SET(reg_cl37_base_abilities, (pc->cl37_sgmii_speed & 3)); 837 } 838 /******* CL37 Next page setting ********/ 839 if(pc->cl37_an_np){ 840 AN_X4_LOC_DEV_CL37_BASE_ABILr_CL37_NEXT_PAGEf_SET(reg_cl37_base_abilities, (pc->cl37_an_np & 1)); 841 } 842 /******* CL37 full duplex ********/ 843 if(pc->cl37_an_fd){ 844 AN_X4_LOC_DEV_CL37_BASE_ABILr_CL37_FULL_DUPLEXf_SET(reg_cl37_base_abilities, (pc->cl37_an_fd & 1)); 845 } 846 /******* SGMII duplex Settings ********/ 847 if(pc->cl37_sgmii_duplex){ 848 AN_X4_LOC_DEV_CL37_BASE_ABILr_SGMII_FULL_DUPLEXf_SET(reg_cl37_base_abilities, (pc->cl37_sgmii_duplex & 1)); 849 } 850 851 /***** Setting AN_X4_ABILITIES_ld_base_abilities_1 0xC181 *******/ 852 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_LOC_DEV_CL37_BASE_ABILr(pc, reg_cl37_base_abilities)); 853 } 854 /*CL73 bam abilities setting*/ 855 AN_X4_LOC_DEV_CL73_BAM_ABILr_CLR(reg_cl73_bam_abilities); 856 AN_X4_LOC_DEV_CL73_BAM_ABILr_BAM_20GBASE_KR2f_SET(reg_cl73_bam_abilities,( pc->cl73_bam_speed & 1)); 857 AN_X4_LOC_DEV_CL73_BAM_ABILr_BAM_20GBASE_CR2f_SET(reg_cl73_bam_abilities,((pc->cl73_bam_speed >> 1) & 0x1)); 858 AN_X4_LOC_DEV_CL73_BAM_ABILr_HPAM_20GKR2f_SET(reg_cl73_bam_abilities, ((pc->cl73_bam_speed & 4) >> 2)); 859 AN_X4_LOC_DEV_CL73_BAM_ABILr_CL73_BAM_CODEf_SET(reg_cl73_bam_abilities, (pc->cl73_bam_code & 0x1ff)); 860 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_LOC_DEV_CL73_BAM_ABILr(pc, reg_cl73_bam_abilities)); 861 /*CL73 base abilities_0 setting*/ 862 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_CLR(reg_cl73_base_abilities); 863 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_NEXT_PAGEf_SET(reg_cl73_base_abilities, (pc->cl73_nxt_page & 1)); 864 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_BASE_100GBASE_CR10f_SET(reg_cl73_base_abilities, ((pc->cl73_speed >> 0)& 0x1)); 865 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_BASE_40GBASE_CR4f_SET(reg_cl73_base_abilities, ((pc->cl73_speed >> 1)& 0x1)); 866 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_BASE_40GBASE_KR4f_SET(reg_cl73_base_abilities, ((pc->cl73_speed >> 2)& 0x1)); 867 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_BASE_10GBASE_KRf_SET(reg_cl73_base_abilities, ((pc->cl73_speed >> 3)& 0x1)); 868 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_BASE_10GBASE_KX4f_SET(reg_cl73_base_abilities, ((pc->cl73_speed >> 4)& 0x1)); 869 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_BASE_1000BASE_KXf_SET(reg_cl73_base_abilities, ((pc->cl73_speed >> 5)& 0x1)); 870 871 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_CL73_PAUSEf_SET(reg_cl73_base_abilities, ( pc->cl73_pause & 3)); 872 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_FECf_SET(reg_cl73_base_abilities, ( pc->cl73_fec & 3)); 873 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_CL73_REMOTE_FAULTf_SET(reg_cl73_base_abilities, ( pc->cl73_remote_fault & 1)); 874 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_LOC_DEV_CL73_BASE_ABIL0r(pc, reg_cl73_base_abilities)); 875 } 876 return PHYMOD_E_NONE; 877 } 878 #endif 879 880 #ifdef _SDK_TEMOD_ 881 int temod_autoneg_set(PHYMOD_ST* pc, 882 temod_an_ability_t *an_ability_st) /* AUTONEG_SET */ 883 { 884 AN_X4_LOC_DEV_CL37_BASE_ABILr_t reg_cl37_base_abilities; 885 AN_X4_LOC_DEV_CL37_BAM_ABILr_t reg_cl37_bam_abilities; 886 AN_X4_LOC_DEV_OVER1G_ABIL0r_t reg_over1g_abilities; 887 AN_X4_LOC_DEV_OVER1G_ABIL1r_t reg_over1g_abilities1; 888 AN_X4_LOC_DEV_CL73_BAM_ABILr_t reg_cl73_bam_abilities; 889 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_t reg_cl73_base_abilities; 890 AN_X4_LOC_DEV_CL73_BASE_ABIL1r_t reg_an_cl73_abl_1; 891 892 TEMOD_DBG_IN_FUNC_INFO(pc); 893 894 /* if((an_ability_st->cl37_adv.an_type == TEMOD_AN_MODE_CL37) || ( an_ability_st->cl37_adv.an_type == TEMOD_AN_MODE_CL37BAM) || 895 (an_ability_st->cl37_adv.an_type == TEMOD_AN_MODE_SGMII) ) */ { 896 897 /* an37 */ 898 /*if((an_ability_st->cl37_adv.an_type != TEMOD_AN_MODE_CL37BAM)) */{ 899 AN_X4_LOC_DEV_CL37_BASE_ABILr_CLR(reg_cl37_base_abilities); 900 AN_X4_LOC_DEV_CL37_BASE_ABILr_CL37_AN_RESTART_RESET_DISABLEf_SET(reg_cl37_base_abilities, 1); 901 AN_X4_LOC_DEV_CL37_BASE_ABILr_CL37_SW_RESTART_RESET_DISABLEf_SET (reg_cl37_base_abilities, 1); 902 if((an_ability_st->cl37_adv.an_bam_speed) || (an_ability_st->cl37_adv.an_bam_speed1)) { 903 AN_X4_LOC_DEV_CL37_BASE_ABILr_CL37_AN_RESTART_RESET_DISABLEf_SET(reg_cl37_base_abilities, 0); 904 AN_X4_LOC_DEV_CL37_BASE_ABILr_CL37_SW_RESTART_RESET_DISABLEf_SET (reg_cl37_base_abilities, 0); 905 } 906 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_LOC_DEV_CL37_BASE_ABILr(pc, reg_cl37_base_abilities)); 907 } 908 909 /*Local device cl37 base abilities setting*/ 910 AN_X4_LOC_DEV_CL37_BASE_ABILr_CLR(reg_cl37_base_abilities); 911 AN_X4_LOC_DEV_CL37_BASE_ABILr_CL37_PAUSEf_SET(reg_cl37_base_abilities, (an_ability_st->cl37_adv.an_pause & 3)); 912 AN_X4_LOC_DEV_CL37_BASE_ABILr_SGMII_SPEEDf_SET(reg_cl37_base_abilities, (an_ability_st->cl37_adv.cl37_sgmii_speed & 3)); 913 914 AN_X4_LOC_DEV_CL37_BASE_ABILr_CL37_FULL_DUPLEXf_SET(reg_cl37_base_abilities, 1); 915 AN_X4_LOC_DEV_CL37_BASE_ABILr_SGMII_FULL_DUPLEXf_SET(reg_cl37_base_abilities, 1); 916 917 AN_X4_LOC_DEV_CL37_BASE_ABILr_AN_PD_TO_CL37_ENABLEf_SET(reg_cl37_base_abilities, 1); 918 919 /***** Setting AN_X4_ABILITIES_ld_base_abilities_1 0xC181 *******/ 920 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_LOC_DEV_CL37_BASE_ABILr(pc, reg_cl37_base_abilities)); 921 922 /*Local device cl37 bam abilities setting*/ 923 /******* CL37 Bam AN_X4_ABILITIES_local_device_over1g_abilities_0 setting********/ 924 /* cl37 bam abilities 0xc182 */ 925 /* Once we put this code in init, can remove teh over1g* cfg from here */ 926 /*if((an_ability_st->cl37_adv.an_type == TEMOD_AN_MODE_CL37BAM)) */{ 927 AN_X4_LOC_DEV_CL37_BAM_ABILr_CLR(reg_cl37_bam_abilities); 928 AN_X4_LOC_DEV_CL37_BAM_ABILr_CL37_BAM_CODEf_SET(reg_cl37_bam_abilities, 0x2); 929 AN_X4_LOC_DEV_CL37_BAM_ABILr_OVER1G_ABILITYf_SET(reg_cl37_bam_abilities, 0x1); 930 AN_X4_LOC_DEV_CL37_BAM_ABILr_OVER1G_PAGE_COUNTf_SET(reg_cl37_bam_abilities, 0x5); 931 932 PHYMOD_IF_ERR_RETURN 933 (MODIFY_AN_X4_LOC_DEV_CL37_BAM_ABILr(pc, reg_cl37_bam_abilities)); 934 935 AN_X4_LOC_DEV_OVER1G_ABIL0r_CLR(reg_over1g_abilities); 936 AN_X4_LOC_DEV_OVER1G_ABIL1r_CLR(reg_over1g_abilities1); 937 938 if(an_ability_st->cl37_adv.an_bam_speed) 939 AN_X4_LOC_DEV_OVER1G_ABIL0r_SET(reg_over1g_abilities, (an_ability_st->cl37_adv.an_bam_speed & 0x7ff)); 940 if(an_ability_st->cl37_adv.an_bam_speed1) 941 AN_X4_LOC_DEV_OVER1G_ABIL1r_SET(reg_over1g_abilities1, (an_ability_st->cl37_adv.an_bam_speed1 & 0x1fff )); 942 943 944 /******* CL37 Bam AN_X4_ABILITIES_local_device_over1g_abilities_1 setting********/ 945 if(an_ability_st->cl37_adv.an_fec == TEMOD_FEC_CL74_SUPRTD_REQSTD) { 946 AN_X4_LOC_DEV_OVER1G_ABIL1r_FECf_SET(reg_over1g_abilities1, 1); 947 } else { 948 AN_X4_LOC_DEV_OVER1G_ABIL1r_FECf_SET(reg_over1g_abilities1, 0); 949 } 950 if(an_ability_st->cl37_adv.an_hg2) { 951 AN_X4_LOC_DEV_OVER1G_ABIL1r_HG2f_SET(reg_over1g_abilities1, (an_ability_st->cl37_adv.an_hg2 & 1)); 952 } 953 if(an_ability_st->cl37_adv.an_cl72) { 954 AN_X4_LOC_DEV_OVER1G_ABIL1r_CL72f_SET(reg_over1g_abilities1, (an_ability_st->cl37_adv.an_cl72 & 1)); 955 } 956 /***** Setting AN_X4_ABILITIES_local_device_over1g_abilities_0 0xC183 *******/ 957 PHYMOD_IF_ERR_RETURN(WRITE_AN_X4_LOC_DEV_OVER1G_ABIL0r(pc, reg_over1g_abilities)); 958 PHYMOD_IF_ERR_RETURN(WRITE_AN_X4_LOC_DEV_OVER1G_ABIL1r(pc, reg_over1g_abilities1)); 959 } /* TEMOD_AN_MODE_CL37BAM */ 960 961 }/*Completion of CL37 abilities*/ 962 /*CL73 abilities*/ 963 /*if((an_ability_st->cl73_adv.an_type == TEMOD_AN_MODE_CL73) || ( an_ability_st->cl73_adv.an_type == TEMOD_AN_MODE_CL73BAM)) */ { 964 /*CL73 bam abilities setting*/ 965 AN_X4_LOC_DEV_CL73_BAM_ABILr_CLR(reg_cl73_bam_abilities); 966 AN_X4_LOC_DEV_CL73_BAM_ABILr_BAM_20GBASE_KR2f_SET(reg_cl73_bam_abilities,( an_ability_st->cl73_adv.an_bam_speed & 1)); 967 AN_X4_LOC_DEV_CL73_BAM_ABILr_BAM_20GBASE_CR2f_SET(reg_cl73_bam_abilities,((an_ability_st->cl73_adv.an_bam_speed >> 1) & 0x1)); 968 969 /* 20G KR2 BAM and 20G HPAM advertised here, the setting of the cl73_hpam_enable or the cl73_bam_enable in the control, 970 decides the AN HPAM or AN BAM */ 971 AN_X4_LOC_DEV_CL73_BAM_ABILr_HPAM_20GKR2f_SET(reg_cl73_bam_abilities, (an_ability_st->cl73_adv.an_bam_speed & 1)); 972 /* AN_X4_LOC_DEV_CL73_BAM_ABILr_HPAM_20GKR2f_SET(reg_cl73_bam_abilities, ((an_ability_st->cl73_adv.an_bam_speed & 4) >> 2)); */ 973 974 AN_X4_LOC_DEV_CL73_BAM_ABILr_CL73_BAM_CODEf_SET(reg_cl73_bam_abilities, 0x4); 975 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_LOC_DEV_CL73_BAM_ABILr(pc, reg_cl73_bam_abilities)); 976 /*CL73 base abilities_0 setting*/ 977 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_CLR(reg_cl73_base_abilities); 978 979 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_SET(reg_cl73_base_abilities, an_ability_st->cl73_adv.an_base_speed & 0x3f); 980 981 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_CL73_PAUSEf_SET(reg_cl73_base_abilities, ( an_ability_st->cl73_adv.an_pause & 3)); 982 983 if (an_ability_st->cl73_adv.an_fec == TEMOD_FEC_CL74_SUPRTD_REQSTD) { 984 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_FECf_SET(reg_cl73_base_abilities, 0x3); 985 } else if (an_ability_st->cl73_adv.an_fec == TEMOD_FEC_SUPRTD_NOT_REQSTD) { 986 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_FECf_SET(reg_cl73_base_abilities, 0x1); 987 } else { 988 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_FECf_SET(reg_cl73_base_abilities, 0x0); 989 } 990 PHYMOD_IF_ERR_RETURN(WRITE_AN_X4_LOC_DEV_CL73_BASE_ABIL0r(pc, reg_cl73_base_abilities)); 991 992 /* set cl73 nonce set 0xc340 */ 993 AN_X4_LOC_DEV_CL73_BASE_ABIL1r_CLR(reg_an_cl73_abl_1); 994 AN_X4_LOC_DEV_CL73_BASE_ABIL1r_BASE_SELECTORf_SET(reg_an_cl73_abl_1, 0x1); 995 PHYMOD_IF_ERR_RETURN ( MODIFY_AN_X4_LOC_DEV_CL73_BASE_ABIL1r(pc, reg_an_cl73_abl_1)); 996 997 998 if((an_ability_st->cl73_adv.an_cl72 & 0x1) == 1) { 999 temod_override_set(pc, TEMOD_OVERRIDE_RESET, 0x0); 1000 } else { 1001 temod_override_set(pc, TEMOD_OVERRIDE_CL72, 0x0); 1002 } 1003 } 1004 return PHYMOD_E_NONE; 1005 } 1006 #endif /* _SDK_TEMOD_*/ 1007 1008 /** 1009 @brief To get autoneg control registers. 1010 @param pc handle to current TSCE context (#PHYMOD_ST) 1011 @param an_control reference of type #temod_an_control_t which is updated here 1012 @param an_complete reference which is updated with an_complete info 1013 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 1014 @details Upper software layers call this function to get the status of autoneg. 1015 This function does not return autoneg abilities, but only the status of 1016 completion. 1017 */ 1018 1019 int temod_autoneg_control_get(PHYMOD_ST* pc, temod_an_control_t *an_control, int *an_complete) 1020 { 1021 AN_X4_LOC_DEV_CL37_BASE_ABILr_t reg_an_cl37_abl; 1022 AN_X4_ENSr_t reg_an_enb; 1023 AN_X4_CTLSr_t an_x4_abl_ctrl; 1024 AN_X4_AN_MISC_STSr_t an_misc_sts; 1025 1026 TEMOD_DBG_IN_FUNC_INFO(pc); 1027 READ_AN_X4_LOC_DEV_CL37_BASE_ABILr(pc, ®_an_cl37_abl); 1028 1029 if(AN_X4_LOC_DEV_CL37_BASE_ABILr_SGMII_MASTER_MODEf_GET(reg_an_cl37_abl) == 1) { 1030 an_control->an_property_type = TEMOD_AN_PROPERTY_ENABLE_SGMII_MASTER_MODE; 1031 } 1032 1033 READ_AN_X4_CTLSr(pc, &an_x4_abl_ctrl); 1034 an_control->pd_kx_en = AN_X4_CTLSr_PD_KX_ENf_GET(an_x4_abl_ctrl); 1035 an_control->pd_kx4_en = AN_X4_CTLSr_PD_KX4_ENf_GET(an_x4_abl_ctrl); 1036 1037 /*Setting X4 abilities*/ 1038 READ_AN_X4_ENSr(pc, ®_an_enb); 1039 if(AN_X4_ENSr_CL37_BAM_ENABLEf_GET(reg_an_enb) == 1){ 1040 an_control->an_type = TEMOD_AN_MODE_CL37BAM; 1041 an_control->enable = 1; 1042 } else if (AN_X4_ENSr_CL73_BAM_ENABLEf_GET(reg_an_enb) == 1){ 1043 an_control->an_type = TEMOD_AN_MODE_CL73BAM; 1044 an_control->enable = 1; 1045 } else if (AN_X4_ENSr_CL73_HPAM_ENABLEf_GET(reg_an_enb) == 1) { 1046 an_control->an_type = TEMOD_AN_MODE_HPAM; 1047 an_control->enable = 1; 1048 } else if ( AN_X4_ENSr_CL73_ENABLEf_GET(reg_an_enb) == 1) { 1049 an_control->an_type = TEMOD_AN_MODE_CL73; 1050 an_control->enable = 1; 1051 } else if ( AN_X4_ENSr_CL37_SGMII_ENABLEf_GET(reg_an_enb) == 1) { 1052 an_control->an_type = TEMOD_AN_MODE_SGMII; 1053 if( AN_X4_ENSr_SGMII_TO_CL37_AUTO_ENABLEf_GET(reg_an_enb) == 1) { 1054 an_control->an_type = TEMOD_AN_MODE_CL37_SGMII; 1055 } 1056 an_control->enable = 1; 1057 } else if ( AN_X4_ENSr_CL37_ENABLEf_GET(reg_an_enb) == 1){ 1058 an_control->an_type = TEMOD_AN_MODE_CL37; 1059 an_control->enable = 1; 1060 } else { 1061 an_control->an_type = TEMOD_AN_MODE_NONE; 1062 an_control->enable = 0; 1063 } 1064 1065 if(AN_X4_ENSr_HPAM_TO_CL73_AUTO_ENABLEf_GET(reg_an_enb) == 1) { 1066 an_control->an_property_type = TEMOD_AN_PROPERTY_ENABLE_HPAM_TO_CL73_AUTO; 1067 } else if(AN_X4_ENSr_CL73_BAM_TO_HPAM_AUTO_ENABLEf_GET(reg_an_enb) == 1) { 1068 an_control->an_property_type = TEMOD_AN_PROPERTY_ENABLE_CL73_BAM_TO_HPAM_AUTO; 1069 } else if(AN_X4_ENSr_SGMII_TO_CL37_AUTO_ENABLEf_GET(reg_an_enb) == 1) { 1070 an_control->an_property_type = TEMOD_AN_PROPERTY_ENABLE_SGMII_TO_CL37_AUTO; 1071 } else if(AN_X4_ENSr_CL37_BAM_TO_SGMII_AUTO_ENABLEf_GET(reg_an_enb) == 1) { 1072 an_control->an_property_type = TEMOD_AN_PROPERTY_ENABLE_CL37_BAM_to_SGMII_AUTO; 1073 } 1074 1075 an_control->num_lane_adv = AN_X4_ENSr_NUM_ADVERTISED_LANESf_GET(reg_an_enb); 1076 1077 /* an_complete status */ 1078 AN_X4_AN_MISC_STSr_CLR(an_misc_sts); 1079 1080 READ_AN_X4_AN_MISC_STSr(pc, &an_misc_sts); 1081 1082 *an_complete = AN_X4_AN_MISC_STSr_AN_COMPLETEf_GET(an_misc_sts); 1083 1084 return PHYMOD_E_NONE; 1085 } 1086 1087 /** 1088 @brief To get local autoneg advertisement information. 1089 @param pc handle to current TSCE context (#PHYMOD_ST) 1090 @param an_ability_st reference of type #temod_an_ability_t updated by this function. 1091 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 1092 @details Upper software layers call this function to get local autoneg 1093 abilities info. This function must be called after advertisement is set. This 1094 function does not return the progress of autoneg. 1095 */ 1096 1097 int temod_autoneg_local_ability_get(PHYMOD_ST* pc, temod_an_ability_t *an_ability_st) 1098 { 1099 AN_X4_LOC_DEV_CL37_BASE_ABILr_t reg_cl37_base_abilities; 1100 AN_X4_LOC_DEV_OVER1G_ABIL0r_t reg_over1g_abilities; 1101 AN_X4_LOC_DEV_OVER1G_ABIL1r_t reg_over1g_abilities1; 1102 AN_X4_LOC_DEV_CL73_BAM_ABILr_t reg_cl73_bam_abilities; 1103 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_t reg_cl73_base_abilities; 1104 int an_fec; 1105 1106 TEMOD_DBG_IN_FUNC_INFO(pc); 1107 READ_AN_X4_LOC_DEV_CL37_BASE_ABILr(pc, ®_cl37_base_abilities); 1108 an_ability_st->cl37_adv.an_pause = AN_X4_LOC_DEV_CL37_BASE_ABILr_CL37_PAUSEf_GET(reg_cl37_base_abilities); 1109 an_ability_st->cl37_adv.cl37_sgmii_speed = AN_X4_LOC_DEV_CL37_BASE_ABILr_SGMII_SPEEDf_GET(reg_cl37_base_abilities); 1110 1111 READ_AN_X4_LOC_DEV_OVER1G_ABIL0r(pc, ®_over1g_abilities); 1112 an_ability_st->cl37_adv.an_bam_speed = AN_X4_LOC_DEV_OVER1G_ABIL0r_GET(reg_over1g_abilities) & 0x7ff; 1113 1114 READ_AN_X4_LOC_DEV_OVER1G_ABIL1r(pc, ®_over1g_abilities1); 1115 an_ability_st->cl37_adv.an_bam_speed1 = AN_X4_LOC_DEV_OVER1G_ABIL1r_GET(reg_over1g_abilities1) & 0x1fff; 1116 1117 if (AN_X4_LOC_DEV_OVER1G_ABIL1r_FECf_GET(reg_over1g_abilities1)) { 1118 an_ability_st->cl37_adv.an_fec = TEMOD_FEC_CL74_SUPRTD_REQSTD; 1119 } else { 1120 an_ability_st->cl37_adv.an_fec = TEMOD_FEC_SUPRTD_NOT_REQSTD; 1121 } 1122 an_ability_st->cl37_adv.an_cl72 = AN_X4_LOC_DEV_OVER1G_ABIL1r_CL72f_GET(reg_over1g_abilities1); 1123 an_ability_st->cl37_adv.an_hg2 = AN_X4_LOC_DEV_OVER1G_ABIL1r_HG2f_GET(reg_over1g_abilities1); 1124 1125 READ_AN_X4_LOC_DEV_CL73_BAM_ABILr(pc, ®_cl73_bam_abilities); 1126 an_ability_st->cl73_adv.an_bam_speed = AN_X4_LOC_DEV_CL73_BAM_ABILr_GET(reg_cl73_bam_abilities) & 0x7; 1127 READ_AN_X4_LOC_DEV_CL73_BASE_ABIL0r(pc, ®_cl73_base_abilities); 1128 an_ability_st->cl73_adv.an_base_speed = AN_X4_LOC_DEV_CL73_BASE_ABIL0r_GET(reg_cl73_base_abilities) & 0x3f; 1129 1130 an_ability_st->cl73_adv.an_pause = AN_X4_LOC_DEV_CL73_BASE_ABIL0r_CL73_PAUSEf_GET(reg_cl73_base_abilities); 1131 1132 an_fec = AN_X4_LOC_DEV_CL73_BASE_ABIL0r_FECf_GET(reg_cl73_base_abilities); 1133 if (an_fec == 0x3) { 1134 an_ability_st->cl73_adv.an_fec = TEMOD_FEC_CL74_SUPRTD_REQSTD; 1135 } else if (an_fec == 0x1) { 1136 an_ability_st->cl73_adv.an_fec = TEMOD_FEC_SUPRTD_NOT_REQSTD; 1137 } else { 1138 an_ability_st->cl73_adv.an_fec = TEMOD_FEC_NOT_SUPRTD; 1139 } 1140 1141 return PHYMOD_E_NONE; 1142 } 1143 1144 /** 1145 @brief Function to get autoneg remote advertisement information. 1146 @param pc handle to current TSCE context (#PHYMOD_ST) 1147 @param an_ability_st structurewith the remote abilities 1148 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 1149 @details Upper software layers call this function to get remote autoneg info. 1150 Call this function only after page exchange. 1151 */ 1152 1153 int temod_autoneg_remote_ability_get(PHYMOD_ST* pc, temod_an_ability_t *an_ability_st) 1154 { 1155 AN_X4_LP_MP1024_UP1r_t an_x4_up1; 1156 AN_X4_LP_MP1024_UP3r_t an_x4_up3; 1157 AN_X4_LP_MP1024_UP4r_t an_x4_up4; 1158 AN_X4_LP_BASE_PAGE1r_t an_x4_pg1; 1159 AN_X4_LP_BASE_PAGE2r_t an_x4_pg2; 1160 AN_X4_LP_BASE_PAGE3r_t an_x4_pg3; 1161 AN_X4_LP_MP5_UP3r_t an_x4_mp5_up3; 1162 AN_X4_LP_MP5_UP4r_t an_x4_mp5_up4; 1163 1164 uint32_t data; 1165 uint32_t user_code; 1166 int an_fec; 1167 1168 TEMOD_DBG_IN_FUNC_INFO(pc); 1169 1170 AN_X4_LP_MP1024_UP1r_CLR(an_x4_up1); 1171 AN_X4_LP_MP1024_UP3r_CLR(an_x4_up3); 1172 AN_X4_LP_MP1024_UP4r_CLR(an_x4_up4); 1173 AN_X4_LP_BASE_PAGE1r_CLR(an_x4_pg1); 1174 AN_X4_LP_BASE_PAGE2r_CLR(an_x4_pg2); 1175 AN_X4_LP_BASE_PAGE3r_CLR(an_x4_pg3); 1176 AN_X4_LP_MP5_UP3r_CLR(an_x4_mp5_up3); 1177 AN_X4_LP_MP5_UP4r_CLR(an_x4_mp5_up4); 1178 1179 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LP_MP1024_UP1r(pc, &an_x4_up1)); 1180 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LP_MP1024_UP3r(pc, &an_x4_up3)); 1181 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LP_MP1024_UP4r(pc, &an_x4_up4)); 1182 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LP_BASE_PAGE1r(pc, &an_x4_pg1)); 1183 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LP_BASE_PAGE2r(pc, &an_x4_pg2)); 1184 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LP_BASE_PAGE3r(pc, &an_x4_pg3)); 1185 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LP_MP5_UP3r(pc, &an_x4_mp5_up3)); 1186 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LP_MP5_UP4r(pc, &an_x4_mp5_up4)); 1187 1188 /* data: get the BAM_12GBASE_X4 and BAM_12p5GBASE_X4 */ 1189 data = AN_X4_LP_MP1024_UP1r_SPEED_ABILITY_12G_X4f_GET(an_x4_up1); 1190 data <<= TEMOD_CL37_BAM_12GBASE_X4; 1191 data |= (AN_X4_LP_MP1024_UP1r_SPEED_ABILITY_12P5G_X4f_GET(an_x4_up1) << TEMOD_CL37_BAM_12p5GBASE_X4); 1192 1193 /* data: get BAM_10GBASE_X2_CX4, BAM_10GBASE_X2_CX4 and BAM_10p5GBASE_X2 */ 1194 data |= (AN_X4_LP_MP1024_UP4r_SPEED_ABILITY_10P5G_X2f_GET(an_x4_up4) << TEMOD_CL37_BAM_BAM_10p5GBASE_X2); 1195 data |= (AN_X4_LP_MP1024_UP4r_SPEED_ABILITY_10G_CX2f_GET(an_x4_up4) << TEMOD_CL37_BAM_10GBASE_X2_CX4); 1196 data |= (AN_X4_LP_MP1024_UP4r_SPEED_ABILITY_10G_X2f_GET(an_x4_up4) << TEMOD_CL37_BAM_10GBASE_X2); 1197 1198 /* data: get BAM_12p7GBASE_X2 */ 1199 data |= (AN_X4_LP_MP1024_UP4r_SPEED_ABILITY_12P7G_X2f_GET(an_x4_up4) << TEMOD_CL37_BAM_12p7GBASE_X2); 1200 1201 /* data: get BAM_10GBASE_X4_CX4,BAM_10GBASE_X4,BAM_6GBASE_X4,BAM_5GBASE_X4 and BAM_2P5GBASE_X1 */ 1202 data |= AN_X4_LP_MP1024_UP1r_SPEED_ABILITY_2P5G_X1f_GET(an_x4_up1) << TEMOD_CL37_BAM_2p5GBASE_X; 1203 data |= AN_X4_LP_MP1024_UP1r_SPEED_ABILITY_5G_X4f_GET(an_x4_up1) << TEMOD_CL37_BAM_5GBASE_X4; 1204 data |= AN_X4_LP_MP1024_UP1r_SPEED_ABILITY_6G_X4f_GET(an_x4_up1) << TEMOD_CL37_BAM_6GBASE_X4; 1205 data |= AN_X4_LP_MP1024_UP1r_SPEED_ABILITY_10G_X4f_GET(an_x4_up1) << TEMOD_CL37_BAM_10GBASE_X4; 1206 data |= AN_X4_LP_MP1024_UP1r_SPEED_ABILITY_10G_CX4f_GET(an_x4_up1) << TEMOD_CL37_BAM_10GBASE_X4_CX4; 1207 an_ability_st->cl37_adv.an_bam_speed = data; 1208 1209 /* data - get BAM_13GBASE_X4, BAM_15GBASE_X4, BAM_16GBASE_X4 and BAM_20GBASE_CX4 */ 1210 data = AN_X4_LP_MP1024_UP1r_SPEED_ABILITY_13G_X4f_GET(an_x4_up1) << TEMOD_CL37_BAM_13GBASE_X4; 1211 data |= (AN_X4_LP_MP1024_UP1r_SPEED_ABILITY_15G_X4f_GET(an_x4_up1) << TEMOD_CL37_BAM_15GBASE_X4); 1212 data |= (AN_X4_LP_MP1024_UP1r_SPEED_ABILITY_16G_X4f_GET(an_x4_up1) << TEMOD_CL37_BAM_16GBASE_X4); 1213 data |= (AN_X4_LP_MP1024_UP1r_SPEED_ABILITY_20G_CX4f_GET(an_x4_up1) << TEMOD_CL37_BAM_20GBASE_X4_CX4); 1214 an_ability_st->cl37_adv.an_bam_speed1 = data; 1215 1216 /* data - BAM_15p75GBASE_X2 , BAM_20GBASE_X2*/ 1217 data = AN_X4_LP_MP1024_UP4r_SPEED_ABILITY_15P75G_X2f_GET(an_x4_up4) << TEMOD_CL37_BAM_15p75GBASE_X2; 1218 data |= (AN_X4_LP_MP1024_UP4r_SPEED_ABILITY_20G_CX2f_GET(an_x4_up4) << TEMOD_CL37_BAM_20GBASE_X2); 1219 an_ability_st->cl37_adv.an_bam_speed1 |= data; 1220 1221 /* data - - 21G-X4 , 25.45G-X4, 31.5G-X4, 32.7G, 40G-X4 */ 1222 data = AN_X4_LP_MP1024_UP3r_SPEED_ABILITY_21G_X4f_GET(an_x4_up3) << TEMOD_CL37_BAM_21GBASE_X4; 1223 data |= (AN_X4_LP_MP1024_UP3r_SPEED_ABILITY_25P45G_X4f_GET(an_x4_up3) << TEMOD_CL37_BAM_25p455GBASE_X4); 1224 data |= (AN_X4_LP_MP1024_UP3r_SPEED_ABILITY_31P5G_X4f_GET(an_x4_up3) << TEMOD_CL37_BAM_31p5GBASE_X4); 1225 data |= (AN_X4_LP_MP1024_UP3r_SPEED_ABILITY_32P7Gf_GET(an_x4_up3) << TEMOD_CL37_BAM_32p7GBASE_X4); 1226 data |= (AN_X4_LP_MP1024_UP3r_SPEED_ABILITY_40G_X4f_GET(an_x4_up3) << TEMOD_CL37_BAM_40GBASE_X4); 1227 an_ability_st->cl37_adv.an_bam_speed1 |= data; 1228 1229 1230 /*an_ability_st->cl73_adv.an_bam_speed = 0xdead;*/ 1231 an_ability_st->cl73_adv.an_bam_speed = 0x0; 1232 1233 /* User-Defined Code[19:11] contains BAM code */ 1234 user_code = AN_X4_LP_MP5_UP3r_USER_DEFINED_CODE_19_11f_GET(an_x4_mp5_up3) << 11; 1235 /* User-Defined Code[10:0] contains BAM abilities */ 1236 data = AN_X4_LP_MP5_UP4r_USER_DEFINED_CODE_10_0f_GET(an_x4_mp5_up4); 1237 1238 if (data & (1<<1)) { 1239 an_ability_st->cl73_adv.an_bam_speed |= (1 << TEMOD_CL73_BAM_20GBASE_KR2); 1240 } else { 1241 user_code |= data; 1242 if(user_code == 0xabe20){ 1243 an_ability_st->cl73_adv.an_bam_speed |= (1 << TEMOD_CL73_BAM_20GBASE_KR2); 1244 } 1245 } 1246 if (data & (1<<0)){ 1247 an_ability_st->cl73_adv.an_bam_speed |= (1<< TEMOD_CL73_BAM_20GBASE_CR2); 1248 } 1249 1250 data = AN_X4_LP_BASE_PAGE2r_SPEED_100G_CR10f_GET(an_x4_pg2) << TEMOD_CL73_100GBASE_CR10; 1251 data |= AN_X4_LP_BASE_PAGE2r_SPEED_40G_CR4f_GET(an_x4_pg2) << TEMOD_CL73_40GBASE_CR4; 1252 data |= AN_X4_LP_BASE_PAGE2r_SPEED_40G_KR4f_GET(an_x4_pg2) << TEMOD_CL73_40GBASE_KR4; 1253 data |= AN_X4_LP_BASE_PAGE2r_SPEED_10G_KR_ABILITYf_GET(an_x4_pg2) << TEMOD_CL73_10GBASE_KR; 1254 data |= AN_X4_LP_BASE_PAGE2r_SPEED_10G_KX4_ABILITYf_GET(an_x4_pg2) << TEMOD_CL73_10GBASE_KX4; 1255 data |= AN_X4_LP_BASE_PAGE2r_SPEED_1G_KX_ABILITYf_GET(an_x4_pg2) << TEMOD_CL73_1000BASE_KX; 1256 an_ability_st->cl73_adv.an_base_speed |= data; 1257 1258 /* check the speed ability and pass it as well */ 1259 an_ability_st->cl37_adv.cl37_sgmii_speed = (AN_X4_LP_BASE_PAGE1r_LP_BASE_PAGE1_PAGE_DATAf_GET(an_x4_pg1) >> 10) & 0x3; 1260 an_ability_st->cl37_adv.an_pause = (AN_X4_LP_BASE_PAGE1r_LP_BASE_PAGE1_PAGE_DATAf_GET(an_x4_pg1) >> 7) & 0x3; 1261 an_ability_st->cl37_adv.an_hg2 = AN_X4_LP_MP1024_UP3r_HIGIG_II_ABILITYf_GET(an_x4_up3); 1262 1263 if (AN_X4_LP_MP1024_UP3r_CL74_FEC_ABILITYf_GET(an_x4_up3)) { 1264 an_ability_st->cl37_adv.an_fec = TEMOD_FEC_CL74_SUPRTD_REQSTD; 1265 } else { 1266 an_ability_st->cl37_adv.an_fec = TEMOD_FEC_SUPRTD_NOT_REQSTD; 1267 } 1268 an_ability_st->cl37_adv.an_cl72 = AN_X4_LP_MP1024_UP3r_CL72_TRAINING_ABILITYf_GET(an_x4_up3); 1269 1270 an_ability_st->cl73_adv.an_pause = (AN_X4_LP_BASE_PAGE1r_LP_BASE_PAGE1_PAGE_DATAf_GET(an_x4_pg1) >> 10) & 0x3; 1271 1272 an_fec = (AN_X4_LP_BASE_PAGE3r_LP_BASE_PAGE3_PAGE_DATAf_GET(an_x4_pg3) >> 14) & 0x3; 1273 if (an_fec == 0x3) { 1274 an_ability_st->cl73_adv.an_fec = TEMOD_FEC_CL74_SUPRTD_REQSTD; 1275 } else if (an_fec == 0x1) { 1276 an_ability_st->cl73_adv.an_fec = TEMOD_FEC_SUPRTD_NOT_REQSTD; 1277 } else { 1278 an_ability_st->cl73_adv.an_fec = TEMOD_FEC_NOT_SUPRTD; 1279 } 1280 1281 return PHYMOD_E_NONE; 1282 } 1283 1284 /** 1285 @brief Controls setting/resetting of autoneg and enabling/disabling 1286 @param pc handle to current TSCE context (#PHYMOD_ST) 1287 @param an_control structure with AN controls 1288 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 1289 @details This function programs auto-negotiation (AN) modes for the TSCE. It can 1290 enable/disable clause37/clause73/BAM autonegotiation capabilities. Call this 1291 function once for combo mode and once per lane in independent lane mode. 1292 1293 The autonegotiation mode is indicated by setting an_type with 1294 1295 \li TEMOD_AN_NONE (disable AN) 1296 \li TEMOD_AN_MODE_CL73 1297 \li TEMOD_AN_MODE_CL73_BAM 1298 \li TEMOD_AN_MODE_HPAM 1299 */ 1300 1301 #ifdef _DV_TB_ 1302 int temod_autoneg_control(PHYMOD_ST* pc) 1303 { 1304 uint16_t data ; 1305 uint16_t an_setup_enable, num_advertised_lanes, cl37_bam_enable, cl73_bam_enable ; 1306 uint16_t cl73_hpam_enable, cl73_enable, cl37_sgmii_enable, cl37_enable; 1307 uint16_t cl73_nonce_match_over, cl73_nonce_match_val ,cl73_transmit_nonce; 1308 uint16_t base_selector, cl73_bam_code ; 1309 uint16_t hppam_20gkr2, next_page ; 1310 uint16_t cl37_next_page, cl37_full_duplex; 1311 uint16_t sgmii_full_duplex ; 1312 uint16_t cl37_bam_code, over1g_ability, over1g_page_count; 1313 uint16_t cl37_restart, cl73_restart ; 1314 int no_an ; 1315 AN_X4_LOC_DEV_CL37_BAM_ABILr_t reg_an_cl37_bam_abilities; 1316 /*AN_X4_LOC_DEV_CL73_BASE_ABIL0r_t reg_an_cl73_abl_0; */ 1317 AN_X4_LOC_DEV_CL73_BASE_ABIL1r_t reg_an_cl73_abl_1; 1318 /* AN_X4_LOC_DEV_CL73_BAM_ABILr_t reg_an_cl73_abl; */ 1319 /* UC_COMMAND3r_t reg_com3; */ 1320 AN_X4_ENSr_t reg_an_enb; 1321 TEMOD_DBG_IN_FUNC_INFO(pc); 1322 1323 /* TSCE_COMMANDr_t reg_com; 1324 */ 1325 1326 no_an = 0 ; 1327 1328 an_setup_enable = 0x1; 1329 num_advertised_lanes = 0x2; 1330 cl37_bam_enable = 0x0; 1331 cl73_bam_enable = 0x0; 1332 cl73_hpam_enable = 0x0; 1333 cl73_enable = 0x0; 1334 cl37_sgmii_enable = 0x0; 1335 cl37_enable = 0x0; 1336 cl73_nonce_match_over = 0x1; 1337 cl73_transmit_nonce = 0x0; 1338 cl73_nonce_match_val = 0x0; 1339 base_selector = 0x1; 1340 cl73_bam_code = 0x0; 1341 hppam_20gkr2 = 0x0; 1342 next_page = 0x0; 1343 cl37_next_page = 0x0; 1344 cl37_full_duplex = 0x1; 1345 sgmii_full_duplex = 0x1; 1346 cl37_bam_code = 0x0; 1347 over1g_ability = 0x0; 1348 over1g_page_count = 0x0; 1349 cl37_restart = 0x0; 1350 cl73_restart = 0x0; 1351 1352 num_advertised_lanes = pc->no_of_lanes; 1353 1354 /*if (pc-> an_type == TSCMOD_CL73) { 1355 cl73_restart = 0x1; 1356 cl73_enable = 0x1; 1357 cl73_nonce_match_over = 0x1; 1358 cl73_nonce_match_val = 0x0; 1359 base_selector = 0x1; 1360 } else if (pc-> an_type == TSCMOD_CL37) { 1361 cl37_restart = 0x1; 1362 cl37_enable = 0x1; 1363 cl37_bam_code = 0x0; 1364 over1g_ability = 0x0; 1365 over1g_page_count = 0x0; 1366 sgmii_full_duplex = 0x0; 1367 } else if (pc-> an_type == TSCMOD_CL37_BAM) { 1368 cl37_restart = 0x1; 1369 cl37_enable = 0x1; 1370 cl37_bam_enable = 0x1; 1371 cl37_bam_code = 0x1; 1372 over1g_ability = 0x1; 1373 over1g_page_count = 0x1; */ /* PHY-863: =1: 5 pages; =0: 3 pages; WC uses 3 pages */ 1374 /*sgmii_full_duplex = 0x0; 1375 cl37_next_page = 0x1; 1376 } else if (pc-> an_type == TSCMOD_CL37_SGMII) { 1377 cl37_restart = 0x1; 1378 cl37_sgmii_enable = 0x1; 1379 cl37_enable = 0x1; 1380 cl37_bam_code = 0x0; 1381 over1g_ability = 0x0; 1382 over1g_page_count = 0x0; 1383 } else if (pc-> an_type == TSCMOD_CL73_BAM) { 1384 cl73_restart = 0x1; 1385 cl73_enable = 0x1; 1386 cl73_bam_enable = 0x1; 1387 cl73_bam_code = 0x3; 1388 next_page = 0x1; 1389 cl73_nonce_match_over = 0x1; 1390 cl73_nonce_match_val = 0x0; 1391 base_selector = 0x1; 1392 } else if (pc-> an_type == TSCMOD_HPAM) { 1393 cl73_restart = 0x1; 1394 cl73_enable = 0x1; 1395 cl73_hpam_enable = 0x1; 1396 cl73_bam_code = 0x3; 1397 hppam_20gkr2 = 0x1; 1398 next_page = 0x1; 1399 cl73_nonce_match_over = 0x1; 1400 cl73_nonce_match_val = 0x0; 1401 base_selector = 0x1; 1402 } else { 1403 no_an = 1 ; 1404 printf("%-22s ERROR: u=%0d p=%0d Autoneg mode not defined\n", __func__, pc->unit, pc->port); 1405 }*/ 1406 #if defined (_DV_TB_) 1407 if (pc->sc_mode == TEMOD_SC_MODE_AN_CL37) { 1408 cl37_restart = 0x0; 1409 cl37_enable = pc->cl37_an_en; 1410 cl37_bam_enable = pc->cl37_bam_en; 1411 cl37_sgmii_enable = pc->cl37_sgmii_en; 1412 cl37_bam_code = pc->cl37_bam_code & 0x1ff; 1413 over1g_ability = pc->cl37_bam_ovr1g_en & 1; 1414 over1g_page_count = pc->cl37_bam_ovr1g_pgcnt & 3; /* PHY-863: =1: 5 pages; =0: 3 pages; WC uses 3 pages */ 1415 sgmii_full_duplex = pc->cl37_sgmii_duplex & 1; 1416 cl37_next_page = pc->cl37_an_np & 1; 1417 } else if (pc->sc_mode == TEMOD_SC_MODE_AN_CL73) { 1418 cl73_restart = 0x0; 1419 cl73_enable = pc->cl73_an_en; 1420 cl73_bam_enable = pc->cl73_bam_en; 1421 cl73_hpam_enable = pc->cl73_hpam_en; 1422 cl73_bam_code = pc->cl73_bam_code & 0x1ff; 1423 next_page = pc->cl73_nxt_page & 1; 1424 cl73_nonce_match_over = pc->cl73_nonce_match_over & 1; 1425 cl73_transmit_nonce = pc->transmit_nonce; 1426 cl73_nonce_match_val = pc->cl73_nonce_match_val & 1; 1427 base_selector = pc->base_selector & 0x1f; 1428 } else { 1429 no_an = 1 ; 1430 printf("%-22s ERROR: u=%0d p=%0d Autoneg mode not defined\n", __func__, pc->unit, pc->port); 1431 return PHYMOD_E_FAIL; 1432 } 1433 #endif /*_DV_TB_*/ 1434 1435 1436 /* cl37 bam abilities 0xc182 */ 1437 AN_X4_LOC_DEV_CL37_BAM_ABILr_CLR(reg_an_cl37_bam_abilities); 1438 AN_X4_LOC_DEV_CL37_BAM_ABILr_CL37_BAM_CODEf_SET(reg_an_cl37_bam_abilities, cl37_bam_code); 1439 AN_X4_LOC_DEV_CL37_BAM_ABILr_OVER1G_ABILITYf_SET(reg_an_cl37_bam_abilities, over1g_ability); 1440 AN_X4_LOC_DEV_CL37_BAM_ABILr_OVER1G_PAGE_COUNTf_SET(reg_an_cl37_bam_abilities, over1g_page_count); 1441 1442 PHYMOD_IF_ERR_RETURN 1443 (MODIFY_AN_X4_LOC_DEV_CL37_BAM_ABILr(pc, reg_an_cl37_bam_abilities)); 1444 1445 /* set next page bit set 0xc186 */ 1446 /* 1447 TSCE_READ_AN_LOCAL_DEVICE_CL73_BASE_ABILITIES_0r(pc, ®_an_cl73_abl_0); 1448 TSCE_AN_LOCAL_DEVICE_CL73_BASE_ABILITIES_0r_NEXT_PAGEf_SET(reg_an_cl73_abl_0, next_page); 1449 PHYMOD_IF_ERR_RETURN ( TSCE_WRITE_AN_LOCAL_DEVICE_CL73_BASE_ABILITIES_0r(pc, reg_an_cl73_abl_0)); 1450 */ 1451 1452 /* set cl73_bam_code set 0xc187 */ 1453 /* 1454 1455 TSCE_READ_AN_LOCAL_DEVICE_CL73_BAM_ABILITIESr(pc, ®_an_cl73_abl); 1456 TSCE_AN_LOCAL_DEVICE_CL73_BAM_ABILITIESr_CL73_BAM_CODEf_SET(reg_an_cl73_abl, cl73_bam_code); 1457 PHYMOD_IF_ERR_RETURN ( TSCE_WRITE_AN_LOCAL_DEVICE_CL73_BAM_ABILITIESr(pc, reg_an_cl73_abl)); 1458 */ 1459 /* disable ecc of uC 0xffcc */ 1460 /* 1461 TSCE_COMMAND3r_SET(reg_com3, 0x0c04); 1462 PHYMOD_IF_ERR_RETURN (TSCE_WRITE_COMMAND3r(pc, reg_com3)); 1463 */ 1464 1465 /* enable micro_controller 0xffc2 */ 1466 /* 1467 TSCE_READ_COMMANDr(pc, ®_com); 1468 TSCE_COMMANDr_MICRO_MDIO_DW8051_RESET_Nf_SET(reg_com,1); 1469 UC_COMMAND_MDIO_UC_RESET_N_MASK)); 1470 */ 1471 /* set cl73 nonce set 0xc340 */ 1472 AN_X4_LOC_DEV_CL73_BASE_ABIL1r_CLR(reg_an_cl73_abl_1); 1473 AN_X4_LOC_DEV_CL73_BASE_ABIL1r_CL73_NONCE_MATCH_OVERf_SET(reg_an_cl73_abl_1, cl73_nonce_match_over); 1474 AN_X4_LOC_DEV_CL73_BASE_ABIL1r_CL73_NONCE_MATCH_VALf_SET(reg_an_cl73_abl_1, cl73_nonce_match_val); 1475 PHYMOD_IF_ERR_RETURN ( MODIFY_AN_X4_LOC_DEV_CL73_BASE_ABIL1r(pc, reg_an_cl73_abl_1)); 1476 1477 /* set cl73 base_selector to 802.3 set 0xc185 */ 1478 AN_X4_LOC_DEV_CL73_BASE_ABIL1r_CLR(reg_an_cl73_abl_1); 1479 AN_X4_LOC_DEV_CL73_BASE_ABIL1r_BASE_SELECTORf_SET(reg_an_cl73_abl_1, base_selector); 1480 PHYMOD_IF_ERR_RETURN ( MODIFY_AN_X4_LOC_DEV_CL73_BASE_ABIL1r(pc, reg_an_cl73_abl_1)); 1481 1482 AN_X4_LOC_DEV_CL73_BASE_ABIL1r_CLR(reg_an_cl73_abl_1); 1483 AN_X4_LOC_DEV_CL73_BASE_ABIL1r_TRANSMIT_NONCEf_SET(reg_an_cl73_abl_1, ( cl73_transmit_nonce & 0x1f)); 1484 PHYMOD_IF_ERR_RETURN ( MODIFY_AN_X4_LOC_DEV_CL73_BASE_ABIL1r(pc, reg_an_cl73_abl_1)); 1485 1486 /* 0x924a for PHY_892 TBD*/ 1487 /*if((no_an==0)&&(pc->port_type==TSCMOD_SINGLE_PORT)) {*/ 1488 data = 0x1a0a ; /* 100ms TX_RESET_TIMER_PERIOD */ 1489 data = 0xd05 ; /* 50ms */ 1490 /*} else { 1491 data = 0x5 ; 1492 } 1493 PHYMOD_IF_ERR_RETURN 1494 TSC_REG_WRITE(pc->unit, pc, 0x00, 0x0000924a, data)) ;*/ 1495 1496 /*Disabling AN if already enabled required for dynamic speed change tests*/ 1497 1498 AN_X4_ENSr_CLR(reg_an_enb); 1499 1500 AN_X4_ENSr_CL37_ENABLEf_SET(reg_an_enb,0); 1501 AN_X4_ENSr_CL73_ENABLEf_SET(reg_an_enb,0); 1502 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_ENSr(pc, reg_an_enb)); 1503 1504 /*Setting X4 abilities*/ 1505 AN_X4_ENSr_CLR(reg_an_enb); 1506 AN_X4_ENSr_CL37_BAM_ENABLEf_SET(reg_an_enb,cl37_bam_enable); 1507 AN_X4_ENSr_CL73_BAM_ENABLEf_SET(reg_an_enb,cl73_bam_enable); 1508 AN_X4_ENSr_CL73_HPAM_ENABLEf_SET(reg_an_enb,cl73_hpam_enable); 1509 AN_X4_ENSr_CL73_ENABLEf_SET(reg_an_enb,cl73_enable); 1510 AN_X4_ENSr_CL37_SGMII_ENABLEf_SET(reg_an_enb,cl37_sgmii_enable); 1511 AN_X4_ENSr_CL37_ENABLEf_SET(reg_an_enb,cl37_enable); 1512 AN_X4_ENSr_CL37_AN_RESTARTf_SET(reg_an_enb,cl37_restart); 1513 AN_X4_ENSr_CL73_AN_RESTARTf_SET(reg_an_enb,cl73_restart); 1514 AN_X4_ENSr_HPAM_TO_CL73_AUTO_ENABLEf_SET(reg_an_enb,pc->hpam_to_cl73_auto_enable); 1515 AN_X4_ENSr_CL73_BAM_TO_HPAM_AUTO_ENABLEf_SET(reg_an_enb,pc->cl73_bam_to_hpam_auto_enable); 1516 AN_X4_ENSr_SGMII_TO_CL37_AUTO_ENABLEf_SET(reg_an_enb,pc->sgmii_to_cl37_auto_enable); 1517 AN_X4_ENSr_CL37_BAM_TO_SGMII_AUTO_ENABLEf_SET(reg_an_enb,pc->cl37_bam_to_sgmii_auto_enable); 1518 AN_X4_ENSr_NUM_ADVERTISED_LANESf_SET(reg_an_enb,num_advertised_lanes); 1519 1520 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_ENSr(pc, reg_an_enb)); 1521 1522 return PHYMOD_E_NONE; 1523 } /* temod_autoneg_control */ 1524 #endif 1525 #ifdef _SDK_TEMOD_ 1526 int temod_autoneg_restart(PHYMOD_ST* pc, temod_an_control_t *an_control) 1527 { 1528 AN_X4_ENSr_t reg_an_enb; 1529 uint16_t cl37_restart = 0 ; 1530 switch (an_control->an_type) { 1531 case TEMOD_AN_MODE_CL37_SGMII: 1532 cl37_restart = 1; 1533 break; 1534 default: 1535 break ; 1536 } 1537 if(cl37_restart) { 1538 AN_X4_ENSr_CLR(reg_an_enb); 1539 AN_X4_ENSr_CL37_AN_RESTARTf_SET(reg_an_enb,cl37_restart); 1540 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_ENSr(pc, reg_an_enb)); 1541 AN_X4_ENSr_CL37_AN_RESTARTf_SET(reg_an_enb,0); 1542 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_ENSr(pc, reg_an_enb)); 1543 } 1544 return PHYMOD_E_NONE; 1545 } 1546 #endif 1547 #ifdef _SDK_TEMOD_ 1548 int temod_autoneg_control(PHYMOD_ST* pc, temod_an_control_t *an_control) 1549 { 1550 uint16_t num_advertised_lanes, cl37_bam_enable, cl73_bam_enable ; 1551 uint16_t cl73_hpam_enable, cl73_enable, cl37_sgmii_enable, cl37_enable; 1552 uint16_t cl73_bam_code; 1553 uint16_t cl73_next_page; 1554 uint16_t cl37_next_page; 1555 uint16_t cl37_bam_code; 1556 uint16_t cl37_restart, cl73_restart ; 1557 phymod_access_t pa_copy; 1558 int i=0, start_lane=0, num_lane=0, sgmii_to_cl37=0 ; 1559 uint32_t enable=0; 1560 1561 AN_X4_LOC_DEV_CL37_BASE_ABILr_t reg_an_cl37_abl; 1562 AN_X4_LOC_DEV_CL37_BAM_ABILr_t reg_an_cl37_bam_abilities; 1563 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_t reg_an_cl73_abl_0; 1564 AN_X4_ENSr_t reg_an_enb; 1565 AN_X4_CTLSr_t an_x4_abl_ctrl; 1566 1567 AN_X4_LOC_DEV_CL73_BAM_ABILr_t reg_cl73_bam_abilities; 1568 1569 AN_X1_CL37_ERRr_t reg_cl37_err; 1570 AN_X1_CL73_ERRr_t reg_cl73_err; 1571 1572 TEMOD_DBG_IN_FUNC_INFO(pc); 1573 num_advertised_lanes = an_control->num_lane_adv; 1574 cl37_bam_enable = 0x0; 1575 cl73_bam_enable = 0x0; 1576 cl73_hpam_enable = 0x0; 1577 cl73_enable = 0x0; 1578 cl37_sgmii_enable = 0x0; 1579 cl37_enable = 0x0; 1580 cl73_bam_code = 0x0; 1581 cl73_next_page = 0x0; 1582 cl37_next_page = 0x0; 1583 cl37_bam_code = 0x0; 1584 cl37_restart = 0x0; 1585 cl73_restart = 0x0; 1586 1587 PHYMOD_MEMCPY(&pa_copy, pc, sizeof(pa_copy)); 1588 PHYMOD_IF_ERR_RETURN 1589 (phymod_util_lane_config_get(pc, &start_lane, &num_lane)); 1590 /* The pa_copy is used to clear the cl72 for all the lanes in the port. pc->>lane_mask will enable only one lane */ 1591 switch(num_advertised_lanes){ 1592 case 3: num_lane = 4; break; 1593 case 2: num_lane = 4; break; 1594 case 1: num_lane = 2; break; 1595 case 0: num_lane = 1; break; 1596 default: num_lane = 1; 1597 } 1598 pa_copy.lane_mask = 0; 1599 for(i=0; i<num_lane; i++) { 1600 pa_copy.lane_mask = pa_copy.lane_mask | 0x1 << (start_lane+i); 1601 } 1602 1603 switch (an_control->an_type) { 1604 case TEMOD_AN_MODE_CL73: 1605 { 1606 cl73_restart = an_control->enable; 1607 cl73_enable = an_control->enable; 1608 break; 1609 } 1610 case TEMOD_AN_MODE_CL37: 1611 cl37_restart = an_control->enable; 1612 cl37_enable = an_control->enable; 1613 cl37_bam_code = 0x0; 1614 break; 1615 case TEMOD_AN_MODE_CL37BAM: 1616 cl37_restart = an_control->enable; 1617 cl37_enable = an_control->enable; 1618 cl37_bam_enable = an_control->enable; 1619 cl37_bam_code = 0x1; 1620 cl37_next_page = 0x1; 1621 break; 1622 case TEMOD_AN_MODE_SGMII: 1623 cl37_restart = an_control->enable; 1624 cl37_sgmii_enable = an_control->enable; 1625 cl37_enable = an_control->enable; 1626 cl37_bam_code = 0x0; 1627 break; 1628 case TEMOD_AN_MODE_CL73BAM: 1629 cl73_restart = an_control->enable; 1630 cl73_enable = an_control->enable; 1631 cl73_bam_enable = an_control->enable; 1632 cl73_bam_code = 0x3; 1633 cl73_next_page = 0x1; 1634 break; 1635 case TEMOD_AN_MODE_HPAM: 1636 cl73_restart = an_control->enable; 1637 cl73_enable = an_control->enable; 1638 cl73_hpam_enable = an_control->enable; 1639 /* cl73_bam_code = 0x4; */ 1640 cl73_next_page = 0x1; 1641 break; 1642 case TEMOD_AN_MODE_CL37_SGMII: 1643 cl37_restart = an_control->enable; 1644 cl37_sgmii_enable = an_control->enable; 1645 cl37_enable = an_control->enable; 1646 if(cl37_enable) { 1647 sgmii_to_cl37 = 1; 1648 } 1649 cl37_bam_code = 0x0; 1650 break; 1651 default: 1652 return PHYMOD_E_FAIL; 1653 break; 1654 } 1655 1656 /* RESET Speed Change bit */ 1657 if(an_control->enable){ 1658 temod_disable_set(pc); 1659 } 1660 1661 1662 /* AN TIMERS */ 1663 /*0x9252 AN_X1_TIMERS_cl37_error */ 1664 AN_X1_CL37_ERRr_CLR(reg_cl37_err); 1665 if(an_control->an_type == TEMOD_AN_MODE_CL37){ 1666 AN_X1_CL37_ERRr_SET(reg_cl37_err, 0); 1667 } else if (an_control->an_type == TEMOD_AN_MODE_CL37BAM) { 1668 AN_X1_CL37_ERRr_SET(reg_cl37_err, 0x55d); 1669 } 1670 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_CL37_ERRr(pc, reg_cl37_err)); 1671 1672 /*0x9254 AN_X1_TIMERS_cl73_error*/ 1673 AN_X1_CL73_ERRr_CLR(reg_cl73_err); 1674 if(an_control->an_type == TEMOD_AN_MODE_CL73) { 1675 AN_X1_CL73_ERRr_SET(reg_cl73_err, 0); 1676 } else if(an_control->an_type == TEMOD_AN_MODE_HPAM){ 1677 AN_X1_CL73_ERRr_SET(reg_cl73_err, 0xfff0); 1678 } else if (an_control->an_type == TEMOD_AN_MODE_CL73BAM) { 1679 AN_X1_CL73_ERRr_SET(reg_cl73_err, 0x1a10); 1680 } 1681 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_CL73_ERRr(pc, reg_cl73_err)); 1682 1683 1684 /* cl37 bam abilities 0xc182 */ 1685 AN_X4_LOC_DEV_CL37_BAM_ABILr_CLR(reg_an_cl37_bam_abilities); 1686 AN_X4_LOC_DEV_CL37_BAM_ABILr_CL37_BAM_CODEf_SET(reg_an_cl37_bam_abilities, cl37_bam_code); 1687 PHYMOD_IF_ERR_RETURN 1688 (MODIFY_AN_X4_LOC_DEV_CL37_BAM_ABILr(pc, reg_an_cl37_bam_abilities)); 1689 1690 /*need to set the next page for cl37bam */ 1691 AN_X4_LOC_DEV_CL37_BASE_ABILr_CLR(reg_an_cl37_abl); 1692 if(an_control->an_property_type & TEMOD_AN_PROPERTY_ENABLE_SGMII_MASTER_MODE ) 1693 AN_X4_LOC_DEV_CL37_BASE_ABILr_SGMII_MASTER_MODEf_SET(reg_an_cl37_abl, 0x1); 1694 else 1695 AN_X4_LOC_DEV_CL37_BASE_ABILr_SGMII_MASTER_MODEf_SET(reg_an_cl37_abl, 0x0); 1696 AN_X4_LOC_DEV_CL37_BASE_ABILr_CL37_NEXT_PAGEf_SET(reg_an_cl37_abl, cl37_next_page); 1697 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_LOC_DEV_CL37_BASE_ABILr(pc, reg_an_cl37_abl)); 1698 1699 /*need to set cl73 BAM next page probably*/ 1700 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_CLR(reg_an_cl73_abl_0); 1701 AN_X4_LOC_DEV_CL73_BASE_ABIL0r_NEXT_PAGEf_SET(reg_an_cl73_abl_0, cl73_next_page & 1); 1702 PHYMOD_IF_ERR_RETURN ( MODIFY_AN_X4_LOC_DEV_CL73_BASE_ABIL0r(pc, reg_an_cl73_abl_0)); 1703 PHYMOD_IF_ERR_RETURN( READ_AN_X4_LOC_DEV_CL73_BAM_ABILr(pc, ®_cl73_bam_abilities)); 1704 AN_X4_LOC_DEV_CL73_BAM_ABILr_CL73_BAM_CODEf_SET(reg_cl73_bam_abilities, (cl73_bam_code & 0x1ff)); 1705 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_LOC_DEV_CL73_BAM_ABILr(pc, reg_cl73_bam_abilities)); 1706 1707 1708 1709 AN_X4_CTLSr_CLR(an_x4_abl_ctrl); 1710 AN_X4_CTLSr_PD_KX_ENf_SET(an_x4_abl_ctrl, an_control->pd_kx_en & 0x1); 1711 AN_X4_CTLSr_PD_KX4_ENf_SET(an_x4_abl_ctrl, an_control->pd_kx4_en & 0x1); 1712 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_CTLSr(pc, an_x4_abl_ctrl)); 1713 1714 AN_X4_ENSr_CLR(reg_an_enb); 1715 1716 AN_X4_ENSr_CL37_ENABLEf_SET(reg_an_enb,0); 1717 AN_X4_ENSr_CL73_ENABLEf_SET(reg_an_enb,0); 1718 AN_X4_ENSr_CL37_AN_RESTARTf_SET(reg_an_enb,0); 1719 AN_X4_ENSr_CL73_AN_RESTARTf_SET(reg_an_enb,0); 1720 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_ENSr(pc, reg_an_enb)); 1721 1722 /*Setting X4 abilities*/ 1723 AN_X4_ENSr_CLR(reg_an_enb); 1724 AN_X4_ENSr_CL37_BAM_ENABLEf_SET(reg_an_enb,cl37_bam_enable); 1725 AN_X4_ENSr_CL73_BAM_ENABLEf_SET(reg_an_enb,cl73_bam_enable); 1726 AN_X4_ENSr_CL73_HPAM_ENABLEf_SET(reg_an_enb,cl73_hpam_enable); 1727 AN_X4_ENSr_CL73_ENABLEf_SET(reg_an_enb,cl73_enable); 1728 AN_X4_ENSr_CL37_SGMII_ENABLEf_SET(reg_an_enb,cl37_sgmii_enable); 1729 AN_X4_ENSr_CL37_ENABLEf_SET(reg_an_enb,cl37_enable); 1730 AN_X4_ENSr_CL37_AN_RESTARTf_SET(reg_an_enb,cl37_restart); 1731 AN_X4_ENSr_CL73_AN_RESTARTf_SET(reg_an_enb,cl73_restart); 1732 if(an_control->an_property_type & TEMOD_AN_PROPERTY_ENABLE_HPAM_TO_CL73_AUTO ) 1733 AN_X4_ENSr_HPAM_TO_CL73_AUTO_ENABLEf_SET(reg_an_enb,0x1); 1734 else 1735 AN_X4_ENSr_HPAM_TO_CL73_AUTO_ENABLEf_SET(reg_an_enb,0x0); 1736 if(an_control->an_property_type & TEMOD_AN_PROPERTY_ENABLE_CL73_BAM_TO_HPAM_AUTO ) 1737 AN_X4_ENSr_CL73_BAM_TO_HPAM_AUTO_ENABLEf_SET(reg_an_enb,0x1); 1738 else 1739 AN_X4_ENSr_CL73_BAM_TO_HPAM_AUTO_ENABLEf_SET(reg_an_enb,0x0); 1740 if((an_control->an_property_type & TEMOD_AN_PROPERTY_ENABLE_SGMII_TO_CL37_AUTO)||sgmii_to_cl37) 1741 AN_X4_ENSr_SGMII_TO_CL37_AUTO_ENABLEf_SET(reg_an_enb,0x1); 1742 else 1743 AN_X4_ENSr_SGMII_TO_CL37_AUTO_ENABLEf_SET(reg_an_enb,0x0); 1744 if(an_control->an_property_type & TEMOD_AN_PROPERTY_ENABLE_CL37_BAM_to_SGMII_AUTO ) 1745 AN_X4_ENSr_CL37_BAM_TO_SGMII_AUTO_ENABLEf_SET(reg_an_enb,0x1); 1746 else 1747 AN_X4_ENSr_CL37_BAM_TO_SGMII_AUTO_ENABLEf_SET(reg_an_enb,0x0); 1748 AN_X4_ENSr_NUM_ADVERTISED_LANESf_SET(reg_an_enb,num_advertised_lanes); 1749 1750 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_ENSr(pc, reg_an_enb)); 1751 1752 /*next check if an enabled, restart bit needs to be cleared */ 1753 if (an_control->enable) { 1754 AN_X4_ENSr_CLR(reg_an_enb); 1755 AN_X4_ENSr_CL37_AN_RESTARTf_SET(reg_an_enb,0); 1756 AN_X4_ENSr_CL73_AN_RESTARTf_SET(reg_an_enb,0); 1757 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_ENSr(pc, reg_an_enb)); 1758 } 1759 1760 /* need to clean up the FIF */ 1761 if(an_control->enable == 0) { 1762 pa_copy.lane_mask = 1 << start_lane ; 1763 temod_disable_get(&pa_copy,&enable); 1764 if(enable == 0x1) { 1765 PHYMOD_IF_ERR_RETURN (temod_trigger_speed_change(&pa_copy)); 1766 } 1767 } 1768 return PHYMOD_E_NONE; 1769 } /* temod_autoneg_control */ 1770 #endif /* _SDK_TEMOD_*/ 1771 1772 #ifdef _DV_TB_ 1773 /* 1774 @brief Speeds up DSC and VGA functions for simulation purpose only 1775 @param pc handle to current TSCE context (#PHYMOD_ST) 1776 @returns The value PHYMOD_E_NONE upon successful completion. 1777 @details This function speeds up PLL, DSC and VGA functions for any speed mode. 1778 Please don't call this function in normal operation. Set 1779 #PHYMOD_ST::per_lane_control to 1 for speed up. 1780 1781 This function is controlled by the following register bit: 1782 1783 \li acq2_timeout, acq1_timeout, acqcdr_timeout (0xc210) -> 0x0421 1784 \li acqvga_timeout (0xc211) -> 0x0800 1785 1786 */ 1787 int temod_afe_speed_up_dsc_vga(PHYMOD_ST* pc, int pmd_touched) /* AFE_SPEED_UP_DSC_VGA */ 1788 { 1789 PLL_CAL_CTL0r_t reg_ctrl0; 1790 PLL_CAL_CTL1r_t reg_ctrl1; 1791 PLL_CAL_CTL2r_t reg_ctrl2; 1792 PLL_CAL_CTL5r_t reg_ctrl5; 1793 PLL_CAL_CTL6r_t reg_ctrl6; 1794 DSC_SM_CTL4r_t reg_ctrl4; 1795 1796 TEMOD_DBG_IN_FUNC_INFO(pc); 1797 PLL_CAL_CTL5r_CLR(reg_ctrl5); 1798 PLL_CAL_CTL6r_CLR(reg_ctrl6); 1799 PLL_CAL_CTL0r_CLR(reg_ctrl0); 1800 PLL_CAL_CTL1r_CLR(reg_ctrl1); 1801 PLL_CAL_CTL2r_CLR(reg_ctrl2); 1802 DSC_SM_CTL4r_CLR(reg_ctrl4); 1803 1804 if (pmd_touched == 0) { 1805 /* PLL speed_up begin */ 1806 /* refclk_divcnt = 5 (default 16'h186a ) */ 1807 PLL_CAL_CTL5r_REFCLK_DIVCNTf_SET(reg_ctrl5, 0x5); 1808 PHYMOD_IF_ERR_RETURN (MODIFY_PLL_CAL_CTL5r(pc, reg_ctrl5)); 1809 1810 /* refclk_divcnt_sel = 7 */ 1811 /* data = 0x7 << PLL_CAL_COM_CTL_6_REFCLK_DIVCNT_SEL_SHIFT ; */ 1812 PLL_CAL_CTL6r_REFCLK_DIVCNT_SELf_SET(reg_ctrl6, 0x7); 1813 PHYMOD_IF_ERR_RETURN (MODIFY_PLL_CAL_CTL6r(pc, reg_ctrl6)); 1814 1815 /* vco_start_time = 5 */ 1816 /* data = 0x5 << PLL_CAL_COM_CTL_0_VCO_START_TIME_SHIFT ; */ 1817 PLL_CAL_CTL0r_VCO_START_TIMEf_SET(reg_ctrl0, 0x5); 1818 PHYMOD_IF_ERR_RETURN (MODIFY_PLL_CAL_CTL0r(pc, reg_ctrl0)); 1819 1820 /* pre_freq_det_time = 8'd100 , retry_time = 8'd100 */ 1821 PLL_CAL_CTL1r_PRE_FREQ_DET_TIMEf_SET(reg_ctrl1, 0xc8); 1822 PLL_CAL_CTL1r_RETRY_TIMEf_SET(reg_ctrl1, 0xff); 1823 PHYMOD_IF_ERR_RETURN (MODIFY_PLL_CAL_CTL1r(pc, reg_ctrl1)); 1824 1825 /* res_cal_cntr = 0 win_cal_cntr=1 */ 1826 PLL_CAL_CTL2r_RES_CAL_CNTRf_SET(reg_ctrl2, 0x2); 1827 PLL_CAL_CTL2r_WIN_CAL_CNTRf_SET(reg_ctrl2, 0x1); 1828 1829 PHYMOD_IF_ERR_RETURN (MODIFY_PLL_CAL_CTL2r(pc, reg_ctrl2)); 1830 1831 } 1832 /* PLL speed_up end */ 1833 /* DSC speed_up begin */ 1834 1835 DSC_SM_CTL4r_HW_TUNE_TIMEOUTf_SET(reg_ctrl4, 0x1); 1836 DSC_SM_CTL4r_CDR_SETTLE_TIMEOUTf_SET(reg_ctrl4, 0x1); 1837 DSC_SM_CTL4r_ACQ_CDR_TIMEOUTf_SET(reg_ctrl4, 0x4); 1838 1839 PHYMOD_IF_ERR_RETURN (MODIFY_DSC_SM_CTL4r(pc, reg_ctrl4)); 1840 1841 /* DSC speed_up end */ 1842 return PHYMOD_E_NONE; 1843 } 1844 #endif /* _DV_TB_ */ 1845 1846 static int _temod_getRevDetails(PHYMOD_ST* pc) 1847 { 1848 MAIN0_SERDESIDr_t reg_serdesid; 1849 1850 MAIN0_SERDESIDr_CLR(reg_serdesid); 1851 PHYMOD_IF_ERR_RETURN(READ_MAIN0_SERDESIDr(pc,®_serdesid)); 1852 return (MAIN0_SERDESIDr_GET(reg_serdesid)); 1853 } 1854 1855 #ifdef _DV_TB_ 1856 /** 1857 @brief Set the PLL divider parameter in PMD for desired link speed. 1858 @param pc handle to current TSCE context (#PHYMOD_ST) 1859 @param pmd_touched Is this the first time we are visiting the PMD. 1860 @param spd_intf #temod_spd_intfc_type 1861 @param pll_mode to override the pll div 1862 @returns PHYMOD_E_NONE if successful. PHYMOD_E_FAIL else. 1863 @details This function is called once per TSCE. It cannot be called multiple times 1864 and should be called immediately after reset. Elements of #PHYMOD_ST should be 1865 initialized to required values prior to calling this function. The following 1866 sub-configurations are performed here. 1867 1868 \li Set pll divider for VCO setting in PMD. pll divider is calculated from max_speed. 1869 */ 1870 1871 int temod_set_pll_mode(PHYMOD_ST* pc, int pmd_touched, temod_spd_intfc_type spd_intf, int pll_mode) /* SET_PLL_MODE */ 1872 { 1873 PLL_CAL_CTL7r_t reg_ctl7; 1874 int speed; 1875 1876 TEMOD_DBG_IN_FUNC_INFO(pc); 1877 TEMOD_DBG_IN_FUNC_VIN_INFO(pc,("pmd_touched: %d, spd_intf: %d, pll_mode: %d", pmd_touched, spd_intf, pll_mode)); 1878 1879 PLL_CAL_CTL7r_CLR(reg_ctl7); 1880 if (pmd_touched == 0) { 1881 get_mapped_speed(spd_intf, &speed); 1882 /*Support Override PLL DIV */ 1883 if(pll_mode & TEMOD_OVERRIDE_CFG) { 1884 PLL_CAL_CTL7r_PLL_MODEf_SET(reg_ctl7, (pll_mode) & 0x0000ffff); 1885 } else { 1886 PLL_CAL_CTL7r_PLL_MODEf_SET(reg_ctl7, (eagle_sc_pmd_entry[speed].pll_mode)); 1887 } 1888 1889 #ifdef _DV_TB_ 1890 if( pc->verbosity) { 1891 printf("%-22s: plldiv:%d data:%x\n", __func__, pc->plldiv, PLL_CAL_CTL7r_PLL_MODEf_GET(reg_ctl7)); 1892 printf("%-22s: main0_setup=%x\n", __func__, PLL_CAL_CTL7r_PLL_MODEf_GET(reg_ctl7)); 1893 } 1894 #endif 1895 PHYMOD_IF_ERR_RETURN (MODIFY_PLL_CAL_CTL7r(pc, reg_ctl7)); 1896 } 1897 return PHYMOD_E_NONE; 1898 } /* temod_set_pll_mode(PHYMOD_ST* pc) */ 1899 #endif /* _DV_TB_ */ 1900 1901 1902 /** 1903 @brief This function gets the PLL divider information 1904 @param pc handle to current TSCE context (#PHYMOD_ST) 1905 @param pll_div the reference which is updated with the pll divider value 1906 @returns PHYMOD_E_NONE if successful. 1907 @details Get the PLL divider value. 1908 */ 1909 int temod_get_plldiv(PHYMOD_ST *pc, uint32_t *pll_div) 1910 { 1911 PLL_CAL_CTL7r_t reg_ctl7; 1912 READ_PLL_CAL_CTL7r(pc, ®_ctl7); 1913 *pll_div = PLL_CAL_CTL7r_PLL_MODEf_GET(reg_ctl7); 1914 TEMOD_DBG_IN_FUNC_VOUT_INFO(pc,("temod_get_pll_div: reg=0x%"PRIx32"\n", *pll_div)); 1915 1916 return PHYMOD_E_NONE; 1917 } 1918 1919 int temod_pll_config_set(const phymod_access_t *pa, temod_pll_mode_type pll_mode, phymod_ref_clk_t ref_clk) 1920 { 1921 enum eagle_tsc_pll_enum pll_cfg; 1922 1923 switch (pll_mode) { 1924 1925 case TEMOD_PLL_MODE_DIV_72: 1926 pll_cfg = EAGLE_TSC_pll_div_72x; 1927 break; 1928 case TEMOD_PLL_MODE_DIV_40: 1929 pll_cfg = EAGLE_TSC_pll_div_40x; 1930 break; 1931 case TEMOD_PLL_MODE_DIV_42: 1932 pll_cfg = EAGLE_TSC_pll_div_42x; 1933 break; 1934 case TEMOD_PLL_MODE_DIV_50: 1935 pll_cfg = EAGLE_TSC_pll_div_50x; 1936 break; 1937 case TEMOD_PLL_MODE_DIV_52: 1938 pll_cfg = EAGLE_TSC_pll_div_52x; 1939 break; 1940 case TEMOD_PLL_MODE_DIV_60: 1941 pll_cfg = EAGLE_TSC_pll_div_60x; 1942 break; 1943 case TEMOD_PLL_MODE_DIV_64: 1944 pll_cfg = EAGLE_TSC_pll_div_64x; 1945 break; 1946 case TEMOD_PLL_MODE_DIV_66: 1947 pll_cfg = EAGLE_TSC_pll_div_66x; 1948 break; 1949 case TEMOD_PLL_MODE_DIV_68: 1950 pll_cfg = EAGLE_TSC_pll_div_68x; 1951 break; 1952 case TEMOD_PLL_MODE_DIV_70: 1953 pll_cfg = EAGLE_TSC_pll_div_70x; 1954 break; 1955 case TEMOD_PLL_MODE_DIV_80: 1956 if (ref_clk == phymodRefClk125Mhz) { 1957 pll_cfg = EAGLE_TSC_pll_div_80x_refc125; 1958 } else { 1959 pll_cfg = EAGLE_TSC_pll_div_80x; 1960 } 1961 break; 1962 case TEMOD_PLL_MODE_DIV_82P5: 1963 pll_cfg = EAGLE_TSC_pll_div_82p5x; 1964 break; 1965 case TEMOD_PLL_MODE_DIV_87P5: 1966 pll_cfg = EAGLE_TSC_pll_div_87p5x; 1967 break; 1968 case TEMOD_PLL_MODE_DIV_92: 1969 pll_cfg = EAGLE_TSC_pll_div_92x; 1970 break; 1971 case TEMOD_PLL_MODE_DIV_100: 1972 pll_cfg = EAGLE_TSC_pll_div_100x; 1973 break; 1974 default: 1975 pll_cfg = EAGLE_TSC_pll_div_66x; 1976 break; 1977 } 1978 1979 eagle_tsc_configure_pll(pa, pll_cfg); 1980 1981 return PHYMOD_E_NONE; 1982 } 1983 1984 1985 1986 1987 1988 int temod_pll_config_get(const phymod_access_t *pa, temod_pll_mode_type *pll_mode) 1989 { 1990 err_code_t __err = 0; 1991 uint32_t fracn_sel; 1992 uint8_t fracn_ndiv; 1993 uint32_t pll_div; 1994 /* uint32_t pll_vco_div2; */ 1995 1996 pll_div=rdc_pll_mode(); 1997 fracn_sel=rdc_ams_pll_fracn_sel(); 1998 fracn_ndiv=rdc_ams_pll_fracn_ndiv_int(); 1999 /* pll_vco_div2=rdc_ams_pll_vco_div2(); */ 2000 2001 if(fracn_sel == 1) { 2002 switch(fracn_ndiv) { 2003 case 0x52: *pll_mode = TEMOD_PLL_MODE_DIV_82P5; 2004 break; 2005 case 0x57: *pll_mode = TEMOD_PLL_MODE_DIV_87P5; 2006 break; 2007 #if 0 2008 case 0x49: if(pll_vco_div2 == 0x1) 2009 *pll_mode = EAGLE_TSC_pll_div_36p8x; 2010 else 2011 *pll_mode = EAGLE_TSC_pll_div_73p6x; 2012 break; 2013 case 0xc7: *pll_mode = EAGLE_TSC_pll_div_199p04x; 2014 break; 2015 #endif 2016 default: return PHYMOD_E_CONFIG; 2017 2018 } 2019 } else { 2020 switch(pll_div){ 2021 case 0x1: *pll_mode = TEMOD_PLL_MODE_DIV_72; 2022 break; 2023 case 0xc: *pll_mode = TEMOD_PLL_MODE_DIV_70; 2024 break; 2025 case 0xa: *pll_mode = TEMOD_PLL_MODE_DIV_66; 2026 break; 2027 case 0x9: *pll_mode = TEMOD_PLL_MODE_DIV_64; 2028 break; 2029 case 0x8: *pll_mode = TEMOD_PLL_MODE_DIV_60; 2030 break; 2031 case 0x6: *pll_mode = TEMOD_PLL_MODE_DIV_52; 2032 break; 2033 case 0x3: *pll_mode = TEMOD_PLL_MODE_DIV_42; 2034 break; 2035 case 0x2: *pll_mode = TEMOD_PLL_MODE_DIV_40; 2036 break; 2037 case 0xf: *pll_mode = TEMOD_PLL_MODE_DIV_100; 2038 break; 2039 case 0xe: *pll_mode = TEMOD_PLL_MODE_DIV_92; 2040 break; 2041 case 0xb: *pll_mode = TEMOD_PLL_MODE_DIV_68; 2042 break; 2043 case 0x5: *pll_mode = TEMOD_PLL_MODE_DIV_50; 2044 break; 2045 /*case 0x0: *pll_mode = TEMOD_PLL_MODE_DIV_46; 2046 break; */ 2047 case 0xd: *pll_mode = TEMOD_PLL_MODE_DIV_80; 2048 break; 2049 default: return PHYMOD_E_NONE; 2050 break; 2051 } 2052 } 2053 2054 return PHYMOD_E_NONE; 2055 } 2056 2057 2058 #ifdef _DV_TB_ 2059 /** 2060 @brief set the AN tick overrides 2061 @param pc handle to current TSCE context (#PHYMOD_ST) 2062 @param tick_override 2063 @param numerator 2064 @param denominator 2065 @returns PHYMOD_E_NONE if successful. 2066 @details 2067 */ 2068 int temod_tick_override_set(PHYMOD_ST* pc, int tick_override, int numerator, int denominator) 2069 { 2070 MAIN0_TICK_CTL1r_t reg_ctrl1; 2071 MAIN0_TICK_CTL0r_t reg_ctrl0; 2072 2073 TEMOD_DBG_IN_FUNC_INFO(pc); 2074 MAIN0_TICK_CTL1r_CLR(reg_ctrl1); 2075 MAIN0_TICK_CTL0r_CLR(reg_ctrl0); 2076 2077 /*Tick over_write enable*/ 2078 MAIN0_TICK_CTL1r_TICK_OVERRIDEf_SET(reg_ctrl1, tick_override); 2079 MAIN0_TICK_CTL1r_TICK_NUMERATOR_UPPERf_SET(reg_ctrl1, (numerator & 0x7fff0)); 2080 PHYMOD_IF_ERR_RETURN(WRITE_MAIN0_TICK_CTL1r(pc, reg_ctrl1)); 2081 2082 MAIN0_TICK_CTL0r_TICK_DENOMINATORf_SET(reg_ctrl0, (denominator & 0x3ff) ); 2083 MAIN0_TICK_CTL0r_TICK_NUMERATOR_LOWERf_SET(reg_ctrl0, (numerator & 0xf)); 2084 PHYMOD_IF_ERR_RETURN(WRITE_MAIN0_TICK_CTL0r(pc, reg_ctrl0)); 2085 2086 return PHYMOD_E_NONE; 2087 2088 } 2089 #endif /* _DV_TB_ */ 2090 2091 #ifdef _DV_TB_ 2092 /** 2093 @brief Set the AN Portmode and Single Port for AN of TSCE. 2094 @param pc handle to current TSCE context (#PHYMOD_ST) 2095 @returns PHYMOD_E_NONE if successful. PHYMOD_E_FAIL else. 2096 @details 2097 2098 This function can be called multiple times.Elements of #PHYMOD_ST should be 2099 initialized to required values prior to calling this function. The following 2100 sub-configurations are performed here. 2101 2102 \li Set pll divider for VCO setting (0x9000[12, 11:8]). pll divider is calculated from max_speed. 2103 2104 */ 2105 int temod_set_an_port_mode(PHYMOD_ST* pc) /* SET_AN_PORT_MODE */ 2106 { 2107 uint16_t data, mask,rdata; 2108 PHYMOD_ST pc_10G_X1; 2109 PHYMOD_ST* pc_10G_X1_tmp; 2110 PHYMOD_ST pc_40G_X4; 2111 PHYMOD_ST* pc_40G_X4_tmp; 2112 PHYMOD_ST pc_100G_X4; 2113 PHYMOD_ST* pc_100G_X4_tmp; 2114 2115 MAIN0_SETUPr_t reg_main0_setup; 2116 AN_X1_CL37_RESTARTr_t reg_cl37_restart_timers; 2117 AN_X1_CL37_ACKr_t reg_cl37_ack_timers; 2118 AN_X1_CL37_ERRr_t reg_cl37_err_timers; 2119 AN_X1_CL73_BRK_LNKr_t reg_cl73_brk_lnk_timers; 2120 AN_X1_CL73_ERRr_t reg_cl73_err_timers; 2121 MAIN0_TICK_CTL1r_t reg_tick_ctrl; 2122 MAIN0_TICK_CTL0r_t reg_tick_ctrl0; 2123 2124 AN_X1_CFG_CTLr_t reg_an_retry_cnt; 2125 AN_X1_BAM_SPD_PRI_35_30r_t reg_pri35_30; 2126 AN_X1_BAM_SPD_PRI_29_24r_t reg_pri29_24; 2127 AN_X1_BAM_SPD_PRI_23_18r_t reg_pri23_18; 2128 AN_X1_BAM_SPD_PRI_17_12r_t reg_pri17_12; 2129 AN_X1_BAM_SPD_PRI_11_6r_t reg_pri11_6; 2130 AN_X1_BAM_SPD_PRI_5_0r_t reg_bam_pri5; 2131 AN_X1_OUI_LWRr_t reg_an_oui_lower; 2132 AN_X1_OUI_UPRr_t reg_an_oui_upper; 2133 SC_X1_TX_RST_CNTr_t reg_sc_rst_cnt; 2134 AN_X1_SGMII_CL73_TMR_TYPEr_t reg_an_cl73_sgmii_tmr; 2135 AN_X1_IGNORE_LNK_TMRr_t reg_an_ig_link_tmr; 2136 AN_X1_PD_TO_CL37_LNK_WAIT_TMRr_t reg_an_pd_to_cl37; 2137 AN_X1_CL37_SYNC_STS_FILTER_TMRr_t reg_an_sync_stat_fil_timer; 2138 AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72r_t reg_lk_fail_not72; 2139 AN_X1_CL73_DME_LOCKr_t reg_cl73_dme; 2140 AN_X1_LNK_UPr_t reg_an_lp; 2141 AN_X1_LNK_FAIL_INHBT_TMR_CL72r_t reg_lk_fail; 2142 AN_X1_PD_SD_TMRr_t reg_an_pd_sd_tmr; 2143 2144 TEMOD_DBG_IN_FUNC_INFO(pc); 2145 MAIN0_SETUPr_CLR(reg_main0_setup); 2146 2147 data=0; 2148 mask=0; 2149 2150 /*Selectng div 40 for CL37*/ 2151 /*if(pc->sc_mode == TEMOD_SC_MODE_AN_CL37) 2152 data = data | (MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_div40 << 2153 MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_SHIFT); */ 2154 /*Selectng div 66 for CL77*/ 2155 /*if(pc->sc_mode == TEMOD_SC_MODE_AN_CL73) 2156 data = data | (MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_div66 << 2157 MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_SHIFT);*/ 2158 2159 /*For AN port mode should be always QUAD*/ 2160 2161 PHYMOD_IF_ERR_RETURN (READ_MAIN0_SETUPr(pc, ®_main0_setup)); 2162 rdata = MAIN0_SETUPr_PORT_MODE_SELf_GET(reg_main0_setup); 2163 2164 data = 0; 2165 if((pc->no_of_lanes == 2) || (pc->no_of_lanes == 3)) { 2166 MAIN0_SETUPr_PORT_MODE_SELf_SET(reg_main0_setup, 0); 2167 } else { 2168 if(pc->this_lane == 0 || pc->this_lane == 1 || pc->this_lane == 4 || pc->this_lane == 5 || pc->this_lane == 8 || pc->this_lane == 9){ 2169 if(rdata == 0x1 || rdata == 0x2 || rdata == 0x3){ 2170 data = data | 0x1; 2171 } 2172 if(rdata == 0x4){ 2173 data = data | 0x0; 2174 } 2175 } 2176 if(pc->this_lane == 2 || pc->this_lane == 3 || pc->this_lane == 6 || pc->this_lane == 7 || pc->this_lane == 10 || pc->this_lane == 11){ 2177 if(rdata == 0x1 || rdata == 0x2 || rdata == 0x3){ 2178 data = data | 0x2 ; 2179 } 2180 if(rdata == 0x4){ 2181 data = data | 0x0 ; 2182 } 2183 } 2184 MAIN0_SETUPr_PORT_MODE_SELf_SET(reg_main0_setup, data); 2185 } 2186 2187 PHYMOD_IF_ERR_RETURN(MODIFY_MAIN0_SETUPr(pc,reg_main0_setup)); 2188 2189 /*Tick over_write enable*/ 2190 MAIN0_TICK_CTL1r_CLR(reg_tick_ctrl); 2191 MAIN0_TICK_CTL0r_CLR(reg_tick_ctrl0); 2192 2193 MAIN0_TICK_CTL1r_TICK_OVERRIDEf_SET(reg_tick_ctrl, pc->an_tick_override); 2194 MAIN0_TICK_CTL1r_TICK_NUMERATOR_UPPERf_SET(reg_tick_ctrl, (pc->an_tick_numerator & 0x7fff0) >> 4); 2195 PHYMOD_IF_ERR_RETURN(WRITE_MAIN0_TICK_CTL1r(pc, reg_tick_ctrl)); 2196 2197 data=0; 2198 if((pc->sc_mode == TEMOD_SC_MODE_AN_CL37)) 2199 { 2200 /*Setting numerator to 0x10 and denominator to 0x1 for CL37*/ 2201 MAIN0_TICK_CTL0r_TICK_DENOMINATORf_SET(reg_tick_ctrl0,(pc->an_tick_denominator & 0x3ff)); 2202 MAIN0_TICK_CTL0r_TICK_NUMERATOR_LOWERf_SET(reg_tick_ctrl0,(pc->an_tick_numerator & 0xf)); 2203 PHYMOD_IF_ERR_RETURN(WRITE_MAIN0_TICK_CTL0r(pc, reg_tick_ctrl0)); 2204 } 2205 if((pc->sc_mode == TEMOD_SC_MODE_AN_CL73)) 2206 { 2207 /*Setting numerator to 0x80 and denominator to 0x1 for CL37*/ 2208 MAIN0_TICK_CTL0r_TICK_DENOMINATORf_SET(reg_tick_ctrl0,(pc->an_tick_denominator & 0x3ff)); 2209 MAIN0_TICK_CTL0r_TICK_NUMERATOR_LOWERf_SET(reg_tick_ctrl0,(pc->an_tick_numerator & 0xf)); 2210 PHYMOD_IF_ERR_RETURN(WRITE_MAIN0_TICK_CTL0r(pc, reg_tick_ctrl0)); 2211 } 2212 2213 2214 #if defined (_DV_TB_) 2215 /*AN from ST */ 2216 if(pc->per_lane_control & 0x4) { 2217 pc_10G_X1 = *pc; 2218 pc_10G_X1.speed = digital_operationSpeeds_SPEED_10G_KR1; 2219 pc_10G_X1_tmp = &pc_10G_X1; 2220 temod_get_ht_entries(pc_10G_X1_tmp); 2221 if(pc->cl72_en & TEMOD_OVERRIDE_CFG) 2222 pc_10G_X1_tmp->cl72_en = 0x0; 2223 else 2224 pc_10G_X1_tmp->cl72_en = 0x1; 2225 pc_10G_X1_tmp->cl72_en = pc_10G_X1_tmp->cl72_en | 0x40000000; 2226 _configure_st_entry(1, digital_operationSpeeds_SPEED_40G_KR4, pc_10G_X1_tmp); 2227 } 2228 else if(pc->per_lane_control & 0x8) { 2229 pc_40G_X4 = *pc; 2230 pc_40G_X4.speed = digital_operationSpeeds_SPEED_40G_KR4; 2231 pc_40G_X4_tmp = &pc_40G_X4; 2232 temod_get_ht_entries(pc_40G_X4_tmp); 2233 if(pc->cl72_en & TEMOD_OVERRIDE_CFG) 2234 pc_40G_X4_tmp->cl72_en = 0x0; 2235 else 2236 pc_40G_X4_tmp->cl72_en = 0x1; 2237 pc_40G_X4_tmp->cl72_en = pc_40G_X4_tmp->cl72_en | 0x40000000; 2238 _configure_st_entry(1, digital_operationSpeeds_SPEED_10G_KR1, pc_40G_X4_tmp); 2239 } 2240 else if(pc->per_lane_control & 0x20) { 2241 pc_100G_X4 = *pc; 2242 pc_100G_X4.speed = digital_operationSpeeds_SPEED_100M; 2243 pc_100G_X4_tmp = &pc_100G_X4; 2244 temod_get_ht_entries(pc_100G_X4_tmp); 2245 pc_100G_X4_tmp->cl72_en = pc_100G_X4_tmp->cl72_en | 0x40000000; 2246 pc_100G_X4_tmp->this_lane = 0; 2247 pc_100G_X4_tmp->prt_ad = 1; 2248 _configure_st_entry(1, digital_operationSpeeds_SPEED_100G_CR10, pc_100G_X4_tmp); 2249 pc_100G_X4_tmp->this_lane = 4; 2250 pc_100G_X4_tmp->prt_ad = 5; 2251 _configure_st_entry(1, digital_operationSpeeds_SPEED_100G_CR10, pc_100G_X4_tmp); 2252 pc_100G_X4_tmp->this_lane = 8; 2253 pc_100G_X4_tmp->prt_ad = 9; 2254 _configure_st_entry(1, digital_operationSpeeds_SPEED_100G_CR10, pc_100G_X4_tmp); 2255 } 2256 #endif 2257 2258 2259 /*0x9250 AN_X1_TIMERS_cl37_restart */ 2260 AN_X1_CL37_RESTARTr_CLR(reg_cl37_restart_timers); 2261 data = pc->cl37_restart_timer_period; 2262 if(data == 0) 2263 data = 0x1f; 2264 AN_X1_CL37_RESTARTr_CL37_RESTART_TIMER_PERIODf_SET(reg_cl37_restart_timers, data); 2265 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_CL37_RESTARTr(pc, reg_cl37_restart_timers)); 2266 /*0x9251 AN_X1_TIMERS_cl37_ack */ 2267 AN_X1_CL37_ACKr_CLR(reg_cl37_ack_timers); 2268 data = pc->cl37_ack_timer_period; 2269 if(data == 0) 2270 data = 0x1f; 2271 AN_X1_CL37_ACKr_CL37_ACK_TIMER_PERIODf_SET(reg_cl37_ack_timers, data); 2272 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_CL37_ACKr(pc, reg_cl37_ack_timers)); 2273 /*0x9252 AN_X1_TIMERS_cl37_error */ 2274 AN_X1_CL37_ERRr_CLR(reg_cl37_err_timers); 2275 data = pc->cl37_error_timer_period; 2276 AN_X1_CL37_ERRr_CL37_ERROR_TIMER_PERIODf_SET(reg_cl37_err_timers, data); 2277 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_CL37_ERRr(pc, reg_cl37_err_timers)); 2278 /*0x9253 AN_X1_TIMERS_cl73_break_link */ 2279 AN_X1_CL73_BRK_LNKr_CLR(reg_cl73_brk_lnk_timers); 2280 data = pc->cl73_break_link_timer_period; 2281 AN_X1_CL73_BRK_LNKr_TX_DISABLE_TIMER_PERIODf_SET(reg_cl73_brk_lnk_timers, data); 2282 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_CL73_BRK_LNKr(pc, reg_cl73_brk_lnk_timers)); 2283 /*0x9254 AN_X1_TIMERS_cl73_error*/ 2284 AN_X1_CL73_ERRr_CLR(reg_cl73_err_timers); 2285 data = pc->cl73_error_timer_period; 2286 AN_X1_CL73_ERRr_CL73_ERROR_TIMER_PERIODf_SET(reg_cl73_err_timers, data); 2287 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_CL73_ERRr(pc, reg_cl73_err_timers)); 2288 /*TBD::0x9255 AN_X1_TIMERS_cl73_dme_lock*/ 2289 data = 100; 2290 AN_X1_CL73_DME_LOCKr_CLR(reg_cl73_dme); 2291 AN_X1_CL73_DME_LOCKr_PD_DME_LOCK_TIMER_PERIODf_SET(reg_cl73_dme, data); 2292 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_CL73_DME_LOCKr(pc, reg_cl73_dme)); 2293 /*TBD::0x9256 AN_X1_TIMERS_link_up*/ 2294 data = 32; 2295 AN_X1_LNK_UPr_CLR(reg_an_lp); 2296 AN_X1_LNK_UPr_CL73_LINK_UP_TIMER_PERIODf_SET(reg_an_lp, data); 2297 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_LNK_UPr(pc, reg_an_lp)); 2298 /*0x9257 AN_X1_TIMERS_link_fail_inhibit_timer_cl72*/ 2299 data = pc->link_fail_inhibit_timer_cl72_period; 2300 AN_X1_LNK_FAIL_INHBT_TMR_CL72r_CLR(reg_lk_fail); 2301 AN_X1_LNK_FAIL_INHBT_TMR_CL72r_LINK_FAIL_INHIBIT_TIMER_CL72_PERIODf_SET(reg_lk_fail, data); 2302 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_LNK_FAIL_INHBT_TMR_CL72r(pc, reg_lk_fail)); 2303 /*0x9258 AN_X1_TIMERS_link_fail_inhibit_timer_not_cl72*/ 2304 data = pc->link_fail_inhibit_timer_not_cl72_period; 2305 AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72r_CLR(reg_lk_fail_not72); 2306 AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72r_LINK_FAIL_INHIBIT_TIMER_NCL72_PERIODf_SET(reg_lk_fail_not72, data); 2307 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72r(pc, reg_lk_fail_not72)); 2308 /*0x9259 AN_X1_TIMERS_pd_sd_timer*/ 2309 data = pc->pd_sd_timer_period; 2310 AN_X1_PD_SD_TMRr_CLR(reg_an_pd_sd_tmr); 2311 AN_X1_PD_SD_TMRr_PD_SD_TIMER_PERIODf_SET(reg_an_pd_sd_tmr, data); 2312 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_PD_SD_TMRr(pc, reg_an_pd_sd_tmr)); 2313 /*0x925a AN_X1_TIMERS_cl72_max_wait_timer*/ 2314 data = pc->cl72_max_wait_timer; 2315 AN_X1_CL37_SYNC_STS_FILTER_TMRr_CLR(reg_an_sync_stat_fil_timer); 2316 AN_X1_CL37_SYNC_STS_FILTER_TMRr_CL37_SYNC_STATUS_FILTER_TIMER_PERIODf_SET(reg_an_sync_stat_fil_timer, data); 2317 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_CL37_SYNC_STS_FILTER_TMRr(pc, reg_an_sync_stat_fil_timer)); 2318 /*0x925b AN_X1_TIMERS_PD_TO_CL37_LINK_WAIT_TIMER*/ 2319 data = pc->pd_to_cl37_wait_timer; 2320 AN_X1_PD_TO_CL37_LNK_WAIT_TMRr_CLR(reg_an_pd_to_cl37); 2321 AN_X1_PD_TO_CL37_LNK_WAIT_TMRr_PD_TO_CL37_LINK_WAIT_TIMERf_SET(reg_an_pd_to_cl37, data); 2322 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_PD_TO_CL37_LNK_WAIT_TMRr(pc, reg_an_pd_to_cl37)); 2323 /*0x925c AN_X1_TIMERS_ignore_link_timer*/ 2324 data = pc->an_ignore_link_timer; 2325 AN_X1_IGNORE_LNK_TMRr_CLR(reg_an_ig_link_tmr); 2326 AN_X1_IGNORE_LNK_TMRr_IGNORE_LINK_TIMER_PERIODf_SET(reg_an_ig_link_tmr, data); 2327 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_IGNORE_LNK_TMRr(pc, reg_an_ig_link_tmr)); 2328 /*TBD::0x925d AN_X1_TIMERS_dme_page_timer*/ 2329 /* data = 100; 2330 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_TIMERS_DME_PAGE_TIMERr(pc->unit, pc, data)); 2331 */ 2332 /*TBD::0x925e AN_X1_TIMERS_sgmii_cl73_timer_type*/ 2333 data = 100; 2334 AN_X1_SGMII_CL73_TMR_TYPEr_CLR(reg_an_cl73_sgmii_tmr); 2335 AN_X1_SGMII_CL73_TMR_TYPEr_SGMII_TIMERf_SET(reg_an_cl73_sgmii_tmr, data); 2336 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_SGMII_CL73_TMR_TYPEr(pc, reg_an_cl73_sgmii_tmr)); 2337 /*TBD::0x9263 AN_X1_TIMERS_sgmii_cl73_timer_type*/ 2338 data = pc->tx_reset_count; 2339 SC_X1_TX_RST_CNTr_CLR(reg_sc_rst_cnt); 2340 SC_X1_TX_RST_CNTr_TX_RESET_COUNTf_SET(reg_sc_rst_cnt, data); 2341 PHYMOD_IF_ERR_RETURN(WRITE_SC_X1_TX_RST_CNTr(pc, reg_sc_rst_cnt)); 2342 /*TBD::0x924a AN_X1_CONTROL_tx_reset_timer_period*/ 2343 /*data = 20; 2344 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_CONTROL_TX_RESET_TIMER_PERIODr(pc->unit, pc, 2345 data)); */ 2346 /*TBD::0x924a AN_X1_CONTROL_pll_reset_timer */ 2347 /* data = 20; 2348 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_CONTROL_TX_RESET_TIMER_PERIODr(pc->unit, pc, 2349 data)); */ 2350 /*0x9240 AN_X1_CONTROL_oui_upper */ 2351 data = (pc->oui_upper_data & 0xff); 2352 AN_X1_OUI_UPRr_CLR(reg_an_oui_upper); 2353 AN_X1_OUI_UPRr_OUI_UPPER_DATAf_SET(reg_an_oui_upper, data); 2354 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_OUI_UPRr(pc, reg_an_oui_upper)); 2355 /*0x9241 AN_X1_CONTROL_oui_lower */ 2356 data = ((pc->oui_lower_data)); 2357 AN_X1_OUI_LWRr_CLR(reg_an_oui_lower); 2358 AN_X1_OUI_LWRr_OUI_LOWER_DATAf_SET(reg_an_oui_lower, data); 2359 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_OUI_LWRr(pc, reg_an_oui_lower)); 2360 /*0x9242 AN_X1_CONTROL_BAM_SPEED_PRI_5_0 */ 2361 data = ((pc->bam_spd_pri_5_0)); 2362 AN_X1_BAM_SPD_PRI_5_0r_CLR(reg_bam_pri5); 2363 AN_X1_BAM_SPD_PRI_5_0r_SET(reg_bam_pri5, data); 2364 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_BAM_SPD_PRI_5_0r(pc, reg_bam_pri5)); 2365 /*0x9243 AN_X1_CONTROL_BAM_SPEED_PRI_11_6 */ 2366 data = ((pc->bam_spd_pri_11_6)); 2367 AN_X1_BAM_SPD_PRI_11_6r_CLR(reg_pri11_6); 2368 AN_X1_BAM_SPD_PRI_11_6r_SET(reg_pri11_6, data); 2369 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_BAM_SPD_PRI_11_6r(pc, reg_pri11_6)); 2370 /*0x9244 AN_X1_CONTROL_BAM_SPEED_PRI_17_12 */ 2371 data = ((pc->bam_spd_pri_17_12)); 2372 AN_X1_BAM_SPD_PRI_17_12r_CLR(reg_pri17_12); 2373 AN_X1_BAM_SPD_PRI_17_12r_SET(reg_pri17_12, data); 2374 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_BAM_SPD_PRI_17_12r(pc, reg_pri17_12)); 2375 /*0x9245 AN_X1_CONTROL_BAM_SPEED_PRI_23_18 */ 2376 data = ((pc->bam_spd_pri_23_18) ); 2377 AN_X1_BAM_SPD_PRI_23_18r_CLR(reg_pri23_18); 2378 AN_X1_BAM_SPD_PRI_23_18r_SET(reg_pri23_18, data); 2379 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_BAM_SPD_PRI_23_18r(pc, reg_pri23_18)); 2380 /*0x9246 AN_X1_CONTROL_BAM_SPEED_PRI_29_24 */ 2381 data = ((pc->bam_spd_pri_29_24)); 2382 AN_X1_BAM_SPD_PRI_29_24r_CLR(reg_pri29_24); 2383 AN_X1_BAM_SPD_PRI_29_24r_SET(reg_pri29_24, data); 2384 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_BAM_SPD_PRI_29_24r(pc, reg_pri29_24)); 2385 /*0x9247 AN_X1_CONTROL_BAM_SPEED_PRI_35_30 */ 2386 data = ((pc->bam_spd_pri_35_30)); 2387 AN_X1_BAM_SPD_PRI_35_30r_CLR(reg_pri35_30); 2388 AN_X1_BAM_SPD_PRI_35_30r_SET(reg_pri35_30, data); 2389 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_BAM_SPD_PRI_35_30r(pc, reg_pri35_30)); 2390 /*0x9248 AN_X1_CONTROL_CONFIG_CONTROL */ 2391 data = pc->pd_to_cl37_retry_cnt; 2392 AN_X1_CFG_CTLr_CLR(reg_an_retry_cnt); 2393 AN_X1_CFG_CTLr_SET(reg_an_retry_cnt, data); 2394 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_CFG_CTLr(pc, reg_an_retry_cnt)); 2395 return PHYMOD_E_NONE; 2396 } /* temod_set_an_port_mode(PHYMOD_ST* pc) */ 2397 #endif 2398 2399 #ifdef _SDK_TEMOD_ 2400 /** 2401 @brief Set the Port mode related fields for AN enabled ports 2402 @param pc handle to current TSCE context (#PHYMOD_ST) 2403 @param nl_encoded Number of lanes in this port 2404 @param starting_lane first lane in the port 2405 @param single_port Single port or not 2406 @returns PHYMOD_E_NONE if successful. PHYMOD_E_FAIL else. 2407 @details This function sets up the port for an be called multiple times. Elements of #PHYMOD_ST 2408 should be initialized to required values prior to calling this function. The 2409 following sub-configurations are performed here. 2410 */ 2411 int temod_set_an_port_mode(PHYMOD_ST* pc, int enable, int nl_encoded, int starting_lane, int single_port) /* SET_AN_PORT_MODE */ 2412 { 2413 uint16_t rdata; 2414 uint32_t current_plldiv; 2415 MAIN0_SETUPr_t reg_setup; 2416 int new_portmode = -1 ; 2417 2418 TEMOD_DBG_IN_FUNC_INFO(pc); 2419 TEMOD_DBG_IN_FUNC_VIN_INFO(pc,("nl_encoded: %d, starting_lane: %d, single_port: %d\n", nl_encoded, starting_lane, single_port)); 2420 2421 MAIN0_SETUPr_CLR(reg_setup); 2422 PHYMOD_IF_ERR_RETURN (READ_MAIN0_SETUPr(pc, ®_setup)); 2423 2424 /*Ref clock selection tied to 156.25MHz */ 2425 2426 rdata = MAIN0_SETUPr_PORT_MODE_SELf_GET(reg_setup); 2427 2428 /* nl_encoded: encoded num of lanes adv: say 0->KR, 1->KR2, 2->KR4, 3->CR10*/ 2429 if((nl_encoded == 2) || (nl_encoded == 3)) { 2430 MAIN0_SETUPr_PORT_MODE_SELf_SET(reg_setup, 0); 2431 } else { 2432 if(starting_lane == 0 || starting_lane == 1){ 2433 switch(rdata) { 2434 case 0x2: new_portmode = 0; break ; 2435 case 0x3: new_portmode = 1; break ; 2436 case 0x4: new_portmode = 1; break ; 2437 default: break ; 2438 } 2439 } 2440 if(starting_lane == 2 || starting_lane == 3){ 2441 switch(rdata) { 2442 case 0x1: new_portmode = 0; break ; 2443 case 0x3: new_portmode = 2; break ; 2444 case 0x4: new_portmode = 2; break ; 2445 default: break ; 2446 } 2447 } 2448 if((enable>0) && (new_portmode>=0)) { /* only AN enable to change this field */ 2449 MAIN0_SETUPr_PORT_MODE_SELf_SET(reg_setup, new_portmode); 2450 } 2451 } 2452 /*Setting single port mode*/ 2453 MAIN0_SETUPr_SINGLE_PORT_MODEf_SET(reg_setup, single_port); 2454 2455 /* Setting CL37_HVCO bit */ 2456 temod_get_plldiv(pc,¤t_plldiv); 2457 if(current_plldiv == 0xa) 2458 MAIN0_SETUPr_CL37_HIGH_VCOf_SET(reg_setup, 1); 2459 else 2460 MAIN0_SETUPr_CL37_HIGH_VCOf_SET(reg_setup, 0); 2461 2462 2463 PHYMOD_IF_ERR_RETURN(MODIFY_MAIN0_SETUPr(pc,reg_setup)); 2464 2465 return PHYMOD_E_NONE; 2466 } /* temod_set_an_port_mode(PHYMOD_ST* pc, int num_of_lanes, int starting_lane, int single_port) */ 2467 #endif /* _SDK_TEMOD_ */ 2468 2469 #ifdef _SDK_TEMOD_ 2470 int temod_refclk_set(PHYMOD_ST* pc, phymod_ref_clk_t ref_clock) 2471 { 2472 MAIN0_SETUPr_t reg_setup; 2473 DIG_TOP_USER_CTL0r_t dig_top_user_reg; 2474 2475 2476 MAIN0_SETUPr_CLR(reg_setup); 2477 PHYMOD_IF_ERR_RETURN (READ_MAIN0_SETUPr(pc, ®_setup)); 2478 READ_DIG_TOP_USER_CTL0r(pc, &dig_top_user_reg); 2479 2480 if(ref_clock == phymodRefClk125Mhz) { 2481 MAIN0_SETUPr_REFCLK_SELf_SET(reg_setup, main0_refClkSelect_clk_125MHz); 2482 DIG_TOP_USER_CTL0r_HEARTBEAT_COUNT_1USf_SET(dig_top_user_reg, 0x1f4); 2483 } else { 2484 MAIN0_SETUPr_REFCLK_SELf_SET(reg_setup, main0_refClkSelect_clk_156p25MHz); 2485 DIG_TOP_USER_CTL0r_HEARTBEAT_COUNT_1USf_SET(dig_top_user_reg, 0x271); 2486 } 2487 2488 PHYMOD_IF_ERR_RETURN(MODIFY_MAIN0_SETUPr(pc,reg_setup)); 2489 MODIFY_DIG_TOP_USER_CTL0r(pc, dig_top_user_reg); 2490 2491 return PHYMOD_E_NONE; 2492 } 2493 #endif 2494 2495 int temod_cl37_high_vco_set(PHYMOD_ST* pc, int value) 2496 { 2497 MAIN0_SETUPr_t reg_setup; 2498 2499 MAIN0_SETUPr_CLR(reg_setup); 2500 2501 MAIN0_SETUPr_CL37_HIGH_VCOf_SET(reg_setup, value); 2502 2503 2504 PHYMOD_IF_ERR_RETURN(MODIFY_MAIN0_SETUPr(pc,reg_setup)); 2505 return PHYMOD_E_NONE; 2506 } 2507 2508 2509 2510 /** 2511 @brief Sets loopback mode at PCS/PMD parallel interface.(gloop). 2512 @param pc handle to current TSCE context (#PHYMOD_ST) 2513 @param enable controls enabling loopback 2514 @param starting_lane lane 0 of this port 2515 @param num_lanes Number of lanes of this port 2516 @returns The value PHYMOD_E_NONE upon successful completion 2517 @details This function sets the TX-to-RX digital loopback mode at the PCS/PMD parallel 2518 interface, which is set based on port_type. 2519 2520 \li 0:1 : Enable TX->RX loopback 2521 \li 0:0 : Disable TX->RX loopback 2522 */ 2523 int temod_tx_loopback_control(PHYMOD_ST* pc, int enable, int starting_lane, int num_lanes) /* TX_LOOPBACK_CONTROL */ 2524 { 2525 MAIN0_LPBK_CTLr_t reg_lb_ctrl; 2526 PMD_X4_OVRRr_t reg_pmd_ovr; 2527 PMD_X4_CTLr_t reg_pmd_ctrl; 2528 uint16_t lane_mask, i, data, tmp_data; 2529 2530 TEMOD_DBG_IN_FUNC_INFO(pc); 2531 TEMOD_DBG_IN_FUNC_VIN_INFO(pc,("enable: %d, starting_lane: %d, num_lane: %d", enable, starting_lane, num_lanes)); 2532 2533 lane_mask = 0; 2534 READ_MAIN0_LPBK_CTLr(pc, ®_lb_ctrl); 2535 tmp_data = MAIN0_LPBK_CTLr_LOCAL_PCS_LOOPBACK_ENABLEf_GET(reg_lb_ctrl); 2536 PMD_X4_OVRRr_CLR(reg_pmd_ovr); 2537 PMD_X4_CTLr_CLR(reg_pmd_ctrl); 2538 2539 lane_mask = 0; 2540 data = 0; 2541 for (i = 0; i < num_lanes; i++) { 2542 if (!PHYMOD_LANEPBMP_MEMBER(pc->lane_mask, starting_lane + i)) { 2543 continue; 2544 } 2545 lane_mask |= 1 << (starting_lane + i); 2546 data |= enable << (starting_lane + i); 2547 } 2548 2549 tmp_data &= ~lane_mask; 2550 tmp_data |= data; 2551 MAIN0_LPBK_CTLr_LOCAL_PCS_LOOPBACK_ENABLEf_SET(reg_lb_ctrl, tmp_data); 2552 #if 0 2553 switch(port_type) { 2554 case TEMOD_MULTI_PORT: lane_mask = (1 << (starting_lane%4)); break; 2555 case TEMOD_TRI1_PORT: lane_mask = ((starting_lane%4)==2)?0xc : (1 << (starting_lane%4)); break; 2556 case TEMOD_TRI2_PORT: lane_mask = ((starting_lane%4)==0)?0x3 : (1 << (starting_lane%4)); break; 2557 case TEMOD_DXGXS: lane_mask = ((starting_lane%4)==0)?0x3 : 0xc; break; 2558 case TEMOD_SINGLE_PORT: lane_mask = 0xf; break; 2559 default: break ; 2560 } 2561 MAIN0_LPBK_CTLr_LOCAL_PCS_LOOPBACK_ENABLEf_SET(reg_lb_ctrl, (enable ? lane_mask: 0)); 2562 #endif 2563 2564 PHYMOD_IF_ERR_RETURN 2565 (MODIFY_MAIN0_LPBK_CTLr(pc, reg_lb_ctrl)); 2566 2567 /* signal_detect and rx_lock */ 2568 if (enable) { 2569 PMD_X4_OVRRr_RX_LOCK_OVRDf_SET(reg_pmd_ovr, 1); 2570 PMD_X4_OVRRr_SIGNAL_DETECT_OVRDf_SET(reg_pmd_ovr, 1); 2571 PMD_X4_OVRRr_TX_DISABLE_OENf_SET(reg_pmd_ovr, 1); 2572 } else { 2573 PMD_X4_OVRRr_RX_LOCK_OVRDf_SET(reg_pmd_ovr, 0); 2574 PMD_X4_OVRRr_SIGNAL_DETECT_OVRDf_SET(reg_pmd_ovr, 0); 2575 PMD_X4_OVRRr_TX_DISABLE_OENf_SET(reg_pmd_ovr, 0); 2576 } 2577 2578 PHYMOD_IF_ERR_RETURN 2579 (MODIFY_PMD_X4_OVRRr(pc, reg_pmd_ovr)); 2580 2581 /* set tx_disable */ 2582 if (enable) { 2583 PMD_X4_CTLr_TX_DISABLEf_SET(reg_pmd_ctrl, 1); 2584 } else { 2585 PMD_X4_CTLr_TX_DISABLEf_SET(reg_pmd_ctrl, 0); 2586 } 2587 /* mask = PMD_X4_CONTROL_TX_DISABLE_MASK ; */ 2588 PHYMOD_IF_ERR_RETURN (MODIFY_PMD_X4_CTLr(pc, reg_pmd_ctrl)); 2589 2590 /* When the phy is put in gloop, the rx clk changes, so need to reset the rxp to clear the rx pipe */ 2591 temod_rx_lane_control_set(pc, 1); 2592 2593 /* Tscf uses following code but tsce needs above code */ 2594 /* related JIRA is SDK-80414 */ 2595 /* trigger speed change */ 2596 /* temod_trigger_speed_change(pc); */ 2597 2598 return PHYMOD_E_NONE; 2599 } 2600 2601 int temod_tx_loopback_get(PHYMOD_ST* pc, uint32_t *enable) /* TX_LOOPBACK_get */ 2602 { 2603 MAIN0_LPBK_CTLr_t loopReg; 2604 READ_MAIN0_LPBK_CTLr(pc, &loopReg); 2605 *enable = MAIN0_LPBK_CTLr_LOCAL_PCS_LOOPBACK_ENABLEf_GET(loopReg); 2606 2607 return PHYMOD_E_NONE; 2608 } 2609 2610 2611 #ifdef _DV_TB_ 2612 /*! 2613 @brief Sets loopback mode at PMD serial interface. (gloop(PCS) + PMD) 2614 @param pc handle to current TSCE context (#PHYMOD_ST) 2615 @param cntl select tx/rx loopback 2616 @returns The value PHYMOD_E_NONE upon successful completion 2617 2618 This function sets the PMD TX-to-RX digital loopback mode. 2619 2620 \li 0:1 : Enable TX->RX loopback 2621 \li 0:0 : Disable TX->RX loopback 2622 2623 Note that this function can program <B>multiple lanes simultaneously</B>. 2624 As an example, to enable gloop on all lanes, 2625 set #PHYMOD_ST::per_lane_control to 0x01010101 2626 2627 */ 2628 int temod_tx_pmd_loopback_control(PHYMOD_ST* pc, int cntl) /* TX_PMD_LOOPBACK_CONTROL */ 2629 { 2630 2631 TLB_RX_DIG_LPBK_CFGr_t reg_lpbk_cfg; 2632 2633 TEMOD_DBG_IN_FUNC_INFO(pc); 2634 TLB_RX_DIG_LPBK_CFGr_CLR(reg_lpbk_cfg); 2635 READ_TLB_RX_DIG_LPBK_CFGr(pc, ®_lpbk_cfg); 2636 TEMOD_DBG_IN_FUNC_VIN_INFO(pc,("cntl: %d", cntl)); 2637 2638 2639 /*cntl = (pc-> pmd_gloop);*/ 2640 if (cntl) { 2641 TLB_RX_DIG_LPBK_CFGr_DIG_LPBK_ENf_SET(reg_lpbk_cfg, 1); 2642 } else { 2643 TLB_RX_DIG_LPBK_CFGr_DIG_LPBK_ENf_SET(reg_lpbk_cfg, 0); 2644 } 2645 PHYMOD_IF_ERR_RETURN 2646 (WRITE_TLB_RX_DIG_LPBK_CFGr(pc, reg_lpbk_cfg)); 2647 2648 temod_rx_lane_control_set(pc, 1); 2649 2650 return PHYMOD_E_NONE; 2651 2652 } 2653 #endif 2654 2655 /** 2656 @brief Sets loopback mode at PMD serial interface. (pcs -> rloop) 2657 @param pc handle to current TSCE context (#PHYMOD_ST) 2658 @param enable Set of reset loopback 2659 @param starting_lane The first logical lane of this port 2660 @param port_type Port type (single/dual/quad) 2661 @returns The value PHYMOD_E_NONE upon successful completion 2662 2663 This function sets the RX-to-TX(PCS) Remote loopback mode, based on port_type. 2664 2665 \li 0:1 : Enable RX->TX loopback 2666 \li 0:0 : Disable RX->TX loopback 2667 */ 2668 int temod_rx_loopback_control(PHYMOD_ST* pc, int enable, int starting_lane, int port_type) /* RX_LOOPBACK_CONTROL */ 2669 { 2670 MAIN0_LPBK_CTLr_t reg_lb_ctrl; 2671 TLB_TX_TX_PI_LOOP_TIMING_CFGr_t reg_lb_timing; 2672 TX_PI_CTL0r_t reg_com_ctrl; 2673 uint16_t lane_mask; 2674 2675 TEMOD_DBG_IN_FUNC_INFO(pc); 2676 MAIN0_LPBK_CTLr_CLR(reg_lb_ctrl); 2677 TLB_TX_TX_PI_LOOP_TIMING_CFGr_CLR(reg_lb_timing); 2678 TX_PI_CTL0r_CLR(reg_com_ctrl); 2679 TEMOD_DBG_IN_FUNC_VIN_INFO(pc,("enable: %d, starting_lane: %d, port_type: %d", enable, starting_lane, port_type)); 2680 2681 2682 lane_mask = 0; 2683 switch(port_type) { 2684 case TEMOD_MULTI_PORT: lane_mask = (1 << (starting_lane%4)); break; 2685 case TEMOD_TRI1_PORT: lane_mask = ((starting_lane%4)==2)?0xc : (1 << (starting_lane%4)); break; 2686 case TEMOD_TRI2_PORT: lane_mask = ((starting_lane%4)==0)?0x3 : (1 << (starting_lane%4)); break; 2687 case TEMOD_DXGXS: lane_mask = ((starting_lane%4)==0)?0x3 : 0xc; break; 2688 case TEMOD_SINGLE_PORT: lane_mask = 0xf; break; 2689 default: break ; 2690 } 2691 2692 MAIN0_LPBK_CTLr_REMOTE_PCS_LOOPBACK_ENABLEf_SET(reg_lb_ctrl, (enable ? lane_mask : 0 )); 2693 PHYMOD_IF_ERR_RETURN 2694 (MODIFY_MAIN0_LPBK_CTLr(pc, reg_lb_ctrl)); 2695 2696 /* set Tx_PI */ 2697 TLB_TX_TX_PI_LOOP_TIMING_CFGr_TX_PI_LOOP_TIMING_SRC_SELf_SET(reg_lb_timing, 1); 2698 2699 PHYMOD_IF_ERR_RETURN 2700 (MODIFY_TLB_TX_TX_PI_LOOP_TIMING_CFGr(pc, reg_lb_timing)); 2701 2702 TX_PI_CTL0r_TX_PI_ENf_SET(reg_com_ctrl, 1); 2703 PHYMOD_IF_ERR_RETURN 2704 (MODIFY_TX_PI_CTL0r(pc, reg_com_ctrl)); 2705 2706 return PHYMOD_E_NONE; 2707 } 2708 2709 #ifdef _DV_TB_ 2710 /** 2711 @brief set tx encoder of any particular lane 2712 @param pc handle to current TSCE context (#PHYMOD_ST) 2713 @param spd_intf Speed info as provided by #temod_spd_intfc_type 2714 @returns The value PHYMOD_E_NONE upon successful completion. 2715 @details 2716 This function is used to select encoder of any transmit lane. 2717 It selects the encode type based on the speed of the port. 2718 */ 2719 int temod_encode_set(PHYMOD_ST* pc, temod_spd_intfc_type spd_intf) /* ENCODE_SET */ 2720 { 2721 uint16_t hg2_message_invalid_code_enable, hg2_codec, hg2_en ; 2722 TX_X4_ENC0r_t reg_encode; 2723 int cntl; 2724 2725 TEMOD_DBG_IN_FUNC_INFO(pc); 2726 TEMOD_DBG_IN_FUNC_VIN_INFO(pc,("spd_intf: %d", spd_intf)); 2727 TX_X4_ENC0r_CLR(reg_encode); 2728 2729 2730 printf("HiGig_Info : %-22s : pc->per_lane_control %08x : tx_higig2_en %08x : tx_higig2_codec %08x\n", __func__, pc->per_lane_control, pc->tx_higig2_en, pc->tx_higig2_codec) ; 2731 2732 cntl = pc->per_lane_control; 2733 2734 hg2_message_invalid_code_enable = 1 ; 2735 hg2_en = 0 ; /* 001 cl48 8b10b 2736 010 cl48 8b10b rxaui 2737 011 cl36 8b10b 2738 100 cl82 64b66b 2739 101 cl49 64b66b 2740 110 brcm 64b66b */ 2741 hg2_codec = 0 ; 2742 2743 if((spd_intf == TEMOD_SPD_10_SGMII) | 2744 (spd_intf == TEMOD_SPD_100_SGMII) | 2745 (spd_intf == TEMOD_SPD_1000_SGMII) | 2746 (spd_intf == TEMOD_SPD_2500)) { 2747 hg2_message_invalid_code_enable = 0x0 ; 2748 } else if((spd_intf == TEMOD_SPD_10000_XFI)|| 2749 (spd_intf == TEMOD_SPD_10600_XFI_HG)|| 2750 (spd_intf == TEMOD_SPD_5000)) { 2751 hg2_message_invalid_code_enable = 1 ; 2752 } else if (spd_intf == TEMOD_SPD_10000 ) { /* 10G XAUI */ 2753 hg2_message_invalid_code_enable = 0 ; 2754 } else if (spd_intf == TEMOD_SPD_10000_HI ) { /* 10.6G HI XAUI */ 2755 hg2_message_invalid_code_enable = 0 ; 2756 } else if (spd_intf == TEMOD_SPD_20G_MLD_DXGXS ) { 2757 hg2_message_invalid_code_enable = 1 ; 2758 } else if ((spd_intf ==TEMOD_SPD_21G_HI_MLD_DXGXS)|| 2759 (spd_intf ==TEMOD_SPD_12773_HI_DXGXS)) { 2760 hg2_message_invalid_code_enable = 1 ; 2761 hg2_en = 1 ; 2762 hg2_codec = 1 ; 2763 } else if ((spd_intf == TEMOD_SPD_20G_DXGXS)|| 2764 (spd_intf == TEMOD_SPD_21G_HI_DXGXS)) { 2765 hg2_message_invalid_code_enable = 0 ; 2766 } else if ((spd_intf == TEMOD_SPD_42G_X4)|| 2767 (spd_intf == TEMOD_SPD_40G_X4)|| 2768 (spd_intf == TEMOD_SPD_25455) || 2769 (spd_intf == TEMOD_SPD_12773_DXGXS)) { 2770 hg2_message_invalid_code_enable = 0 ; 2771 } else if (spd_intf == TEMOD_SPD_40G_XLAUI ) { 2772 hg2_message_invalid_code_enable = 1 ; 2773 } else if (spd_intf == TEMOD_SPD_42G_XLAUI ) { 2774 hg2_message_invalid_code_enable = 1 ; 2775 hg2_en = 1 ; 2776 hg2_codec = 1 ; 2777 } else if (spd_intf == TEMOD_SPD_127G_HG_CR12) { 2778 hg2_message_invalid_code_enable = 1 ; 2779 hg2_en = 1 ; 2780 hg2_codec = 1 ; 2781 } else if (spd_intf == TEMOD_SPD_107G_HG_CR10) { 2782 hg2_message_invalid_code_enable = 1 ; 2783 hg2_en = 1 ; 2784 hg2_codec = 1 ; 2785 } 2786 2787 /* NICK */ 2788 if(cntl & TEMOD_OVERRIDE_CFG) { 2789 READ_TX_X4_ENC0r(pc, ®_encode); 2790 printf("HiGig_Info : %-22s : pc->per_lane_control %08x : TX_X4_CONTROL0_ENCODE_0 0x%04x : tx_higig2_en %01x : tx_higig2_codec %01x\n", __func__, pc->per_lane_control, 2791 reg_encode, (TX_X4_ENC0r_HG2_ENABLEf_GET(reg_encode)) & 0x1, (TX_X4_ENC0r_HG2_CODECf_GET(reg_encode)) & 0x1) ; 2792 hg2_en = pc->tx_higig2_en ; 2793 hg2_codec = pc->tx_higig2_codec ; 2794 } 2795 /* set encoder 0xc111 */ 2796 TX_X4_ENC0r_HG2_MESSAGE_INVALID_CODE_ENABLEf_SET(reg_encode, hg2_message_invalid_code_enable); 2797 TX_X4_ENC0r_HG2_CODECf_SET(reg_encode, hg2_codec); 2798 TX_X4_ENC0r_HG2_ENABLEf_SET(reg_encode, hg2_en); 2799 2800 PHYMOD_IF_ERR_RETURN (MODIFY_TX_X4_ENC0r(pc, reg_encode)); 2801 2802 return PHYMOD_E_NONE; 2803 } 2804 #endif /* _DV_TB_ */ 2805 2806 #ifdef _SDK_TEMOD_ 2807 /** 2808 @brief set tx encoder of any particular lane 2809 @param pc handle to current TSCE context (#PHYMOD_ST) 2810 @param spd_intf Speed info as provided by #temod_spd_intfc_type 2811 @param enable enable or disable encoding type in consideration 2812 @returns The value PHYMOD_E_NONE upon successful completion. 2813 @details 2814 This function is used to select encoder of any transmit lane. 2815 It selects the encode type based on the speed of the port. 2816 */ 2817 int temod_encode_set(PHYMOD_ST* pc, temod_spd_intfc_type spd_intf, uint16_t enable) 2818 { 2819 uint16_t hg2_message_invalid_code_enable, hg2_codec, hg2_en ; 2820 TX_X4_ENC0r_t reg_encode; 2821 2822 TEMOD_DBG_IN_FUNC_INFO(pc); 2823 TX_X4_ENC0r_CLR(reg_encode); 2824 2825 hg2_message_invalid_code_enable = 0 ; 2826 hg2_en = 0 ; 2827 hg2_codec = 0 ; 2828 2829 if(enable == 1) { 2830 hg2_message_invalid_code_enable = 1; 2831 hg2_en = 1; 2832 hg2_codec = 1; 2833 } 2834 2835 /* set encoder 0xc111 */ 2836 TX_X4_ENC0r_HG2_MESSAGE_INVALID_CODE_ENABLEf_SET(reg_encode, hg2_message_invalid_code_enable); 2837 TX_X4_ENC0r_HG2_CODECf_SET(reg_encode, hg2_codec); 2838 TX_X4_ENC0r_HG2_ENABLEf_SET(reg_encode, hg2_en); 2839 2840 PHYMOD_IF_ERR_RETURN 2841 (MODIFY_TX_X4_ENC0r(pc, reg_encode)); 2842 2843 return PHYMOD_E_NONE; 2844 2845 } 2846 2847 int temod_hg_enable_get(PHYMOD_ST* pc, int *enable) 2848 { 2849 TX_X4_ENC0r_t reg_encode; 2850 2851 TEMOD_DBG_IN_FUNC_INFO(pc); 2852 TX_X4_ENC0r_CLR(reg_encode); 2853 2854 PHYMOD_IF_ERR_RETURN 2855 (READ_TX_X4_ENC0r(pc, ®_encode)); 2856 *enable = TX_X4_ENC0r_HG2_ENABLEf_GET(reg_encode); 2857 2858 return PHYMOD_E_NONE; 2859 2860 } 2861 2862 int temod_encode_mode_get(PHYMOD_ST* pc, temod_encoder_type_t *mode) 2863 { 2864 SC_X4_RSLVD0r_t reg_resolved; 2865 2866 TEMOD_DBG_IN_FUNC_INFO(pc); 2867 SC_X4_RSLVD0r_CLR(reg_resolved); 2868 2869 PHYMOD_IF_ERR_RETURN 2870 (READ_SC_X4_RSLVD0r(pc, ®_resolved)); 2871 *mode = SC_X4_RSLVD0r_ENCODEMODEf_GET(reg_resolved); 2872 2873 return PHYMOD_E_NONE; 2874 } 2875 2876 #endif /* _SDK_TEMOD_ */ 2877 2878 #ifdef _DV_TB_ 2879 /** 2880 @brief set rx decoder of any particular lane 2881 @param pc handle to current TSCE context (#PHYMOD_ST) 2882 @param spd_intf Speed info as provided by #temod_spd_intfc_type 2883 @returns The value PHYMOD_E_NONE upon successful completion. 2884 @details This function is used to select decoder of any receive lane. 2885 It selects the encode type based on the speed of the port. 2886 */ 2887 2888 int temod_decode_set(PHYMOD_ST* pc, temod_spd_intfc_type spd_intf) /* DECODE_SET */ 2889 { 2890 uint16_t hg2_message_ivalid_code_enable, hg2_en, hg2_codec; 2891 RX_X4_DEC_CTL0r_t reg_decode_ctrl; 2892 int cntl; 2893 2894 TEMOD_DBG_IN_FUNC_INFO(pc); 2895 RX_X4_DEC_CTL0r_CLR(reg_decode_ctrl); 2896 2897 /* NICK */ 2898 printf("HiGig_Info : %-22s : pc->per_lane_control %08x : rx_higig2_en %08x : rx_higig2_codec %08x\n", __func__, pc->per_lane_control, pc->rx_higig2_en, pc->rx_higig2_codec); 2899 2900 /* NICK */ 2901 cntl = pc->per_lane_control | 0x1 ; 2902 /* cntl = 1; */ 2903 2904 hg2_message_ivalid_code_enable = 0x1 ; 2905 hg2_en = 0 ; 2906 hg2_codec = 0 ; 2907 if (cntl) { /* set decoder */ 2908 2909 2910 if(spd_intf == TEMOD_SPD_10_SGMII) { 2911 hg2_message_ivalid_code_enable = 0x0 ; 2912 } else if(spd_intf == TEMOD_SPD_100_SGMII) { 2913 hg2_message_ivalid_code_enable = 0x0 ; 2914 } else if(spd_intf == TEMOD_SPD_1000_SGMII) { 2915 hg2_message_ivalid_code_enable = 0x0 ; 2916 } else if(spd_intf == TEMOD_SPD_2500) { 2917 hg2_message_ivalid_code_enable = 0x0 ; 2918 } else if((spd_intf == TEMOD_SPD_10000_XFI)|| 2919 (spd_intf == TEMOD_SPD_10600_XFI_HG)|| 2920 (spd_intf == TEMOD_SPD_5000)) { 2921 hg2_message_ivalid_code_enable = 0x1 ; 2922 } else if( spd_intf == TEMOD_SPD_10000 ) { /* 10G XAUI */ 2923 hg2_message_ivalid_code_enable = 0x0 ; 2924 } else if( spd_intf == TEMOD_SPD_10000_HI ) { /* 10G XAUI */ 2925 hg2_message_ivalid_code_enable = 0x0 ; 2926 } else if( spd_intf == TEMOD_SPD_20G_MLD_DXGXS ) { 2927 hg2_message_ivalid_code_enable = 0x1 ; 2928 } else if((spd_intf ==TEMOD_SPD_21G_HI_MLD_DXGXS)|| 2929 (spd_intf ==TEMOD_SPD_12773_HI_DXGXS)) { 2930 hg2_message_ivalid_code_enable = 0x1 ; 2931 hg2_en = 1 ; 2932 hg2_codec = 1 ; 2933 } else if((spd_intf == TEMOD_SPD_20G_DXGXS)|| 2934 (spd_intf == TEMOD_SPD_21G_HI_DXGXS)) { 2935 hg2_message_ivalid_code_enable = 0x0 ; 2936 } else if((spd_intf == TEMOD_SPD_42G_X4) || 2937 (spd_intf == TEMOD_SPD_40G_X4) || 2938 (spd_intf == TEMOD_SPD_25455) || 2939 (spd_intf == TEMOD_SPD_12773_DXGXS)) { 2940 hg2_message_ivalid_code_enable = 0x1 ; 2941 } else if( spd_intf == TEMOD_SPD_40G_XLAUI ) { 2942 hg2_message_ivalid_code_enable = 0x1 ; 2943 } else if( spd_intf == TEMOD_SPD_42G_XLAUI ) { /* 40 MLD Hig2 */ 2944 hg2_message_ivalid_code_enable = 0x1 ; 2945 hg2_en = 1 ; 2946 hg2_codec = 1 ; 2947 } else if( spd_intf == TEMOD_SPD_127G_HG_CR12 ) { 2948 hg2_message_ivalid_code_enable = 0x1 ; 2949 hg2_en = 1 ; 2950 hg2_codec = 1 ; 2951 } else if( spd_intf == TEMOD_SPD_107G_HG_CR10 ) { 2952 hg2_message_ivalid_code_enable = 0x1 ; 2953 hg2_en = 1 ; 2954 hg2_codec = 1 ; 2955 } else { 2956 printf("%-22s ERROR: p=%0d undefined spd_intf=%0d(%s)\n", __func__, pc->port, spd_intf, 2957 e2s_temod_spd_intfc_type[spd_intf]) ; 2958 } 2959 /* HG setting */ 2960 if((pc->ctrl_type & TEMOD_CTRL_TYPE_HG)) { 2961 /* not CL48 */ 2962 hg2_en = 1 ; 2963 hg2_codec = 1 ; 2964 } 2965 2966 /* NICK */ 2967 if(cntl & TEMOD_OVERRIDE_CFG) { 2968 READ_RX_X4_DEC_CTL0r(pc, ®_decode_ctrl); 2969 #ifdef _DV_TB_ 2970 printf("HiGig_Info : %-22s : pc->per_lane_control %08x : RX_X4_CONTROL0_DECODE_CONTROL_0 0x%04x : rx_higig2_en %01x : rx_higig2_codec %01x\n", __func__, pc->per_lane_control, reg_decode_ctrl, 2971 (RX_X4_DEC_CTL0r_HG2_ENABLEf_GET(reg_decode_ctrl)) & 0x1, (RX_X4_DEC_CTL0r_HG2_CODECf_GET(reg_decode_ctrl)) & 0x1) ; 2972 #endif 2973 2974 hg2_en = pc->rx_higig2_en ; 2975 hg2_codec = pc->rx_higig2_codec ; 2976 } 2977 2978 if(pc->sc_mode != TEMOD_SC_MODE_AN_CL37 && pc->sc_mode !=TEMOD_SC_MODE_AN_CL73){ 2979 2980 RX_X4_DEC_CTL0r_HG2_MESSAGE_INVALID_CODE_ENABLEf_SET(reg_decode_ctrl, hg2_message_ivalid_code_enable); 2981 RX_X4_DEC_CTL0r_HG2_ENABLEf_SET(reg_decode_ctrl, hg2_en); 2982 RX_X4_DEC_CTL0r_HG2_CODECf_SET(reg_decode_ctrl, hg2_codec); 2983 PHYMOD_IF_ERR_RETURN 2984 (MODIFY_RX_X4_DEC_CTL0r(pc, reg_decode_ctrl)); 2985 } 2986 } else { /* if ~cntl */ 2987 /* no op */ 2988 return PHYMOD_E_NONE; 2989 } 2990 if ((pc->pmd_reset_control) != 0) { 2991 temod_pmd_reset_bypass(pc, 1); 2992 } 2993 return PHYMOD_E_NONE; 2994 } /* DECODE_SET */ 2995 #endif 2996 #ifdef _SDK_TEMOD_ 2997 /** 2998 @brief set rx decoder of any particular lane 2999 @param pc handle to current TSCE context (#PHYMOD_ST) 3000 @param spd_intf Speed info as provided by #temod_spd_intfc_type 3001 @param enable enable or disable decode type 3002 @returns The value PHYMOD_E_NONE upon successful completion. 3003 @details This function is used to select decoder of any receive lane. 3004 It selects the encode type based on the speed of the port. 3005 */ 3006 3007 int temod_decode_set(PHYMOD_ST* pc, temod_spd_intfc_type spd_intf, uint16_t enable) 3008 { 3009 uint16_t hg2_message_ivalid_code_enable, hg2_en, hg2_codec; 3010 RX_X4_DEC_CTL0r_t reg_decode_ctrl; 3011 3012 TEMOD_DBG_IN_FUNC_INFO(pc); 3013 TEMOD_DBG_IN_FUNC_VIN_INFO(pc,("spd_intf: %d", spd_intf)); 3014 RX_X4_DEC_CTL0r_CLR(reg_decode_ctrl); 3015 3016 hg2_message_ivalid_code_enable = 0 ; 3017 hg2_en = 0 ; 3018 hg2_codec = 0 ; 3019 3020 if(enable == 1) { 3021 hg2_message_ivalid_code_enable = 1; 3022 hg2_en = 1; 3023 hg2_codec = 1; 3024 } 3025 3026 RX_X4_DEC_CTL0r_HG2_MESSAGE_INVALID_CODE_ENABLEf_SET(reg_decode_ctrl, hg2_message_ivalid_code_enable); 3027 RX_X4_DEC_CTL0r_HG2_ENABLEf_SET(reg_decode_ctrl, hg2_en); 3028 RX_X4_DEC_CTL0r_HG2_CODECf_SET(reg_decode_ctrl, hg2_codec); 3029 PHYMOD_IF_ERR_RETURN(MODIFY_RX_X4_DEC_CTL0r(pc, reg_decode_ctrl)); 3030 return PHYMOD_E_NONE; 3031 } /* DECODE_SET */ 3032 #endif /* SDK_TEMOD_ */ 3033 3034 /*! 3035 @brief get port speed id configured 3036 @param pc handle to current TSCE context (#PHYMOD_ST) 3037 @param speed_id Receives the the resolved speed cfg as recorded in h/w 3038 @returns The value PHYMOD_E_NONE upon successful completion. 3039 @details get port speed configured 3040 */ 3041 int temod_speed_id_get(PHYMOD_ST* pc, int *speed_id) 3042 { 3043 SC_X4_RSLVD_SPDr_t sc_final_resolved_speed; 3044 3045 TEMOD_DBG_IN_FUNC_INFO(pc); 3046 SC_X4_RSLVD_SPDr_CLR(sc_final_resolved_speed); 3047 READ_SC_X4_RSLVD_SPDr(pc,&sc_final_resolved_speed); 3048 *speed_id = SC_X4_RSLVD_SPDr_SPEEDf_GET(sc_final_resolved_speed); 3049 TEMOD_DBG_IN_FUNC_VOUT_INFO(pc,("speed_id: %d", *speed_id)); 3050 3051 return PHYMOD_E_NONE; 3052 } 3053 3054 /*! 3055 @brief get port speed intf configured 3056 @param pc handle to current TSCE context (#PHYMOD_ST) 3057 @param spd_intf A pointer to speed type. 3058 @returns The value PHYMOD_E_NONE upon successful completion. 3059 @details get port speed configured in the PHY. The value returned 3060 is the actual value in the resolved speed register and not the enumerated type 3061 used in the driver. 3062 */ 3063 int temod_spd_intf_get(PHYMOD_ST* pc, int *spd_intf) 3064 { 3065 SC_X4_RSLVD_SPDr_t sc_final_resolved_speed; 3066 3067 TEMOD_DBG_IN_FUNC_INFO(pc); 3068 SC_X4_RSLVD_SPDr_CLR(sc_final_resolved_speed); 3069 READ_SC_X4_RSLVD_SPDr(pc,&sc_final_resolved_speed); 3070 *spd_intf = get_actual_speed(SC_X4_RSLVD_SPDr_SPEEDf_GET(sc_final_resolved_speed), spd_intf); 3071 TEMOD_DBG_IN_FUNC_VOUT_INFO(pc,("spd_intf: %d", *spd_intf)); 3072 return PHYMOD_E_NONE; 3073 } 3074 3075 /*! 3076 @brief tx lane reset and enable of any particular lane 3077 @param pc handle to current TSCE context (#PHYMOD_ST) 3078 @param tx_dis_type enum type #tx_lane_disable_type_t 3079 @returns The value PHYMOD_E_NONE upon successful completion. 3080 @details 3081 This function is used to reset tx lane and enable/disable tx lane of any 3082 transmit lane. Set enable to enable the TX_LANE (1) or disable the TX lane (0). 3083 When diable TX lane, two types of operations are invoked independently. 3084 3085 If enable bit [7:4] = 1, only traffic is disabled. 3086 (TEMOD_TX_LANE_TRAFFIC =0x10) 3087 If bit [7:4] = 2, only reset function is invoked. 3088 (TEMOD_TX_LANE_RESET = 0x20) 3089 */ 3090 int temod_tx_lane_control_set(PHYMOD_ST* pc, tx_lane_disable_type_t tx_dis_type) /* TX_LANE_CONTROL */ 3091 { 3092 TX_X4_MISCr_t reg_misc_ctrl; 3093 3094 TEMOD_DBG_IN_FUNC_INFO(pc); 3095 TX_X4_MISCr_CLR(reg_misc_ctrl); 3096 TEMOD_DBG_IN_FUNC_VIN_INFO(pc,("tx_dis_type: %d", tx_dis_type)); 3097 3098 switch(tx_dis_type) { 3099 case TEMOD_TX_LANE_RESET: 3100 TX_X4_MISCr_RSTB_TX_LANEf_SET(reg_misc_ctrl, 0); 3101 PHYMOD_IF_ERR_RETURN (MODIFY_TX_X4_MISCr(pc, reg_misc_ctrl)); 3102 TX_X4_MISCr_CLR(reg_misc_ctrl); 3103 TX_X4_MISCr_RSTB_TX_LANEf_SET(reg_misc_ctrl, 1); 3104 PHYMOD_IF_ERR_RETURN (MODIFY_TX_X4_MISCr(pc, reg_misc_ctrl)); 3105 break; 3106 case TEMOD_TX_LANE_TRAFFIC_ENABLE: 3107 TX_X4_MISCr_ENABLE_TX_LANEf_SET(reg_misc_ctrl, 1); 3108 PHYMOD_IF_ERR_RETURN (MODIFY_TX_X4_MISCr(pc, reg_misc_ctrl)); 3109 break; 3110 case TEMOD_TX_LANE_TRAFFIC_DISABLE: 3111 TX_X4_MISCr_ENABLE_TX_LANEf_SET(reg_misc_ctrl, 0); 3112 PHYMOD_IF_ERR_RETURN (MODIFY_TX_X4_MISCr(pc, reg_misc_ctrl)); 3113 break; 3114 case TEMOD_TX_LANE_RESET_TRAFFIC_ENABLE: 3115 TX_X4_MISCr_RSTB_TX_LANEf_SET(reg_misc_ctrl, 1); 3116 PHYMOD_IF_ERR_RETURN (MODIFY_TX_X4_MISCr(pc, reg_misc_ctrl)); 3117 TX_X4_MISCr_CLR(reg_misc_ctrl); 3118 TX_X4_MISCr_ENABLE_TX_LANEf_SET(reg_misc_ctrl, 1); 3119 PHYMOD_IF_ERR_RETURN (MODIFY_TX_X4_MISCr(pc, reg_misc_ctrl)); 3120 break; 3121 case TEMOD_TX_LANE_RESET_TRAFFIC_DISABLE: 3122 TX_X4_MISCr_RSTB_TX_LANEf_SET(reg_misc_ctrl, 0); 3123 PHYMOD_IF_ERR_RETURN (MODIFY_TX_X4_MISCr(pc, reg_misc_ctrl)); 3124 TX_X4_MISCr_CLR(reg_misc_ctrl); 3125 TX_X4_MISCr_ENABLE_TX_LANEf_SET(reg_misc_ctrl, 0); 3126 PHYMOD_IF_ERR_RETURN (MODIFY_TX_X4_MISCr(pc, reg_misc_ctrl)); 3127 break; 3128 default: 3129 break; 3130 } 3131 return PHYMOD_E_NONE; 3132 } 3133 3134 /*! 3135 @brief tx lane reset and enable of any particular lane 3136 @param pc handle to current TSCE context (#PHYMOD_ST) 3137 @param *reset returns the tx_reset configured. 3138 @param *enable returns the tx_enable configured. 3139 @returns The value PHYMOD_E_NONE upon successful completion. 3140 @details 3141 returns the configured tx lane reset and enable of any particular lane 3142 */ 3143 int temod_tx_lane_control_get(PHYMOD_ST* pc, int *reset, int *enable) /* TX_LANE_CONTROL_GET */ 3144 { 3145 TX_X4_MISCr_t reg_misc_ctrl; 3146 3147 TEMOD_DBG_IN_FUNC_INFO(pc); 3148 TX_X4_MISCr_CLR(reg_misc_ctrl); 3149 3150 PHYMOD_IF_ERR_RETURN (READ_TX_X4_MISCr(pc, ®_misc_ctrl)); 3151 *reset = TX_X4_MISCr_RSTB_TX_LANEf_GET(reg_misc_ctrl); 3152 *enable = TX_X4_MISCr_ENABLE_TX_LANEf_GET(reg_misc_ctrl); 3153 3154 return PHYMOD_E_NONE; 3155 } 3156 3157 3158 /** 3159 @brief Read the 16 bit rev. id value etc. 3160 @param pc handle to current TSCE context (#PHYMOD_ST) 3161 @param *revid int ref. to return revision id to calling function. 3162 @returns The value PHYMOD_E_NONE upon successful completion. 3163 @details This function reads the revid register that contains core number, 3164 revision number and returns the 16-bit value in the revid 3165 */ 3166 3167 int temod_revid_read(PHYMOD_ST* pc, uint32_t *revid) /* REVID_READ */ 3168 { 3169 TEMOD_DBG_IN_FUNC_INFO(pc); 3170 *revid=_temod_getRevDetails(pc); 3171 TEMOD_DBG_IN_FUNC_VOUT_INFO(pc,("revid: %"PRIx32"", *revid)); 3172 return PHYMOD_E_NONE; 3173 } 3174 3175 #ifdef _DV_TB_ 3176 /** 3177 @brief Read the 16 bit rev. id value etc. 3178 @param pc handle to current TSCE context (#PHYMOD_ST) 3179 @returns The value PHYMOD_E_NONE upon successful completion 3180 @details Per Port PCS Init 3181 3182 */ 3183 int temod_init_pcs(PHYMOD_ST* pc) /* INIT_PCS */ 3184 { 3185 TEMOD_DBG_IN_FUNC_INFO(pc); 3186 _temod_set_port_mode_select(pc); 3187 temod_rx_lane_control_set(pc, 1); 3188 temod_tx_lane_control_set(pc, TEMOD_TX_LANE_RESET_TRAFFIC_ENABLE); /* TX_LANE_CONTROL */ 3189 3190 /*Re-Visit, Assuming the value is non xero in case mld only */ 3191 temod_mld_am_timers_set(pc, pc->rx_am_timer_init_val, pc->tx_am_timer_init_val); 3192 3193 if((pc->sc_mode == TEMOD_SC_MODE_AN_CL37) || (pc->sc_mode == TEMOD_SC_MODE_AN_CL73)) 3194 _init_pcs_an(pc); 3195 else /* Forced Speed */ 3196 _init_pcs_fs(pc); 3197 3198 return PHYMOD_E_NONE; 3199 } 3200 #endif 3201 3202 /** 3203 @brief Init the PMD 3204 @param pc handle to current TSCE context (#PHYMOD_ST) 3205 @param pmd_touched If the PMD is already initialized 3206 @returns The value PHYMOD_E_NONE upon successful completion 3207 @details Per core PMD resets (both datapath and entire core) 3208 We only intend to use this function if the PMD has never been initialized. 3209 */ 3210 int temod_pmd_reset_seq(PHYMOD_ST* pc, int pmd_touched) /* PMD_RESET_SEQ */ 3211 { 3212 PMD_X1_CTLr_t reg_pmd_x1_ctrl; 3213 TEMOD_DBG_IN_FUNC_INFO(pc); 3214 TEMOD_DBG_IN_FUNC_VIN_INFO(pc,("pmd_touched: %x", pmd_touched)); 3215 3216 PMD_X1_CTLr_CLR(reg_pmd_x1_ctrl); 3217 3218 if (pmd_touched == 0) { 3219 PMD_X1_CTLr_POR_H_RSTBf_SET(reg_pmd_x1_ctrl,0); 3220 PMD_X1_CTLr_CORE_DP_H_RSTBf_SET(reg_pmd_x1_ctrl,0); 3221 PHYMOD_IF_ERR_RETURN(WRITE_PMD_X1_CTLr(pc,reg_pmd_x1_ctrl)); 3222 PMD_X1_CTLr_POR_H_RSTBf_SET(reg_pmd_x1_ctrl,1); 3223 PMD_X1_CTLr_CORE_DP_H_RSTBf_SET(reg_pmd_x1_ctrl,1); 3224 PHYMOD_IF_ERR_RETURN(WRITE_PMD_X1_CTLr(pc,reg_pmd_x1_ctrl)); 3225 } 3226 return PHYMOD_E_NONE; 3227 } 3228 3229 #ifdef _DV_TB_ 3230 /** 3231 @brief Wait for SC done bit set. 3232 @param pc handle to current TSCE context (#PHYMOD_ST) 3233 @param data handle to return SC_X4_CONTROL_STATUS reg. 3234 @returns The value PHYMOD_E_NONE upon successful completion 3235 @details Wait for SC done bit set. This is a very short wait Hence we allow a 3236 loop here. We never allow looping in tier1 as a rule. All looping should be done 3237 in tier2 and above. 3238 */ 3239 int temod_wait_sc_done(PHYMOD_ST* pc, uint16_t *data) 3240 { 3241 static int timeOut = 15; 3242 int localTimeOut = timeOut; 3243 SC_X4_STSr_t reg_sc_ctrl_sts; 3244 3245 TEMOD_DBG_IN_FUNC_INFO(pc); 3246 SC_X4_STSr_CLR(reg_sc_ctrl_sts); 3247 3248 while(1) { 3249 localTimeOut--; 3250 PHYMOD_IF_ERR_RETURN(READ_SC_X4_STSr(pc, ®_sc_ctrl_sts)); 3251 if((SC_X4_STSr_SW_SPEED_CHANGE_DONEf_GET(reg_sc_ctrl_sts) == 1) || localTimeOut < 1) 3252 break; 3253 } 3254 TEMOD_DBG_IN_FUNC_VOUT_INFO(pc,("sc_done: %x", *data)); 3255 3256 return PHYMOD_E_NONE; 3257 } 3258 #endif /* _DV_TB_ */ 3259 3260 /** 3261 @brief Control pram ablity 3262 @param pc handle to current TSCE context (#PHYMOD_ST) 3263 @param enable Enable value for PRAM set. 3264 @returns The value PHYMOD_E_NONE upon successful completion 3265 @details Per core PMD resets (both datapath and entire core) 3266 We only intend to use this function if the PMD has never been initialized. 3267 */ 3268 int temod_pram_abl_enable_set(PHYMOD_ST* pc, int enable) /* PMD_RESET_SEQ */ 3269 { 3270 PMD_X1_CTLr_t reg_pmd_x1_ctrl; 3271 TEMOD_DBG_IN_FUNC_INFO(pc); 3272 3273 PMD_X1_CTLr_CLR(reg_pmd_x1_ctrl); 3274 3275 PMD_X1_CTLr_PRAM_ABILITYf_SET(reg_pmd_x1_ctrl,enable); 3276 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X1_CTLr(pc,reg_pmd_x1_ctrl)); 3277 3278 return PHYMOD_E_NONE; 3279 } 3280 3281 3282 3283 /** 3284 @brief Set the port speed and enable the port 3285 @param pc handle to current TSCE context (#PHYMOD_ST) 3286 @param spd_intf the speed to set the port enum #temod_set_spd_intf 3287 @returns The value PHYMOD_E_NONE upon successful completion 3288 @details Sets the port to the specified speed and triggers the port, and waits 3289 for the port to be configured 3290 */ 3291 int temod_set_spd_intf(PHYMOD_ST *pc, temod_spd_intfc_type spd_intf, int no_trig) 3292 { 3293 SC_X4_CTLr_t xgxs_x4_ctrl; 3294 phymod_access_t pa_copy; 3295 int speed_id = 0, start_lane = 0, num_lane = 0; 3296 3297 TEMOD_DBG_IN_FUNC_INFO(pc); 3298 TEMOD_DBG_IN_FUNC_VIN_INFO(pc,("spd_intf: %d", spd_intf)); 3299 3300 /* need to figure out what's the starting lane */ 3301 PHYMOD_MEMCPY(&pa_copy, pc, sizeof(pa_copy)); 3302 PHYMOD_IF_ERR_RETURN 3303 (phymod_util_lane_config_get(pc, &start_lane, &num_lane)); 3304 pa_copy.lane_mask = 0x1 << start_lane; 3305 3306 PHYMOD_IF_ERR_RETURN (get_mapped_speed(spd_intf, &speed_id)); 3307 /* write the speed_id into the speed_change register */ 3308 SC_X4_CTLr_CLR(xgxs_x4_ctrl); 3309 SC_X4_CTLr_SW_SPEEDf_SET(xgxs_x4_ctrl, speed_id); 3310 MODIFY_SC_X4_CTLr(pc, xgxs_x4_ctrl); 3311 /*next call the speed_change routine */ 3312 if(no_trig) { 3313 3314 } else { 3315 PHYMOD_IF_ERR_RETURN (temod_trigger_speed_change(&pa_copy)); 3316 /*check the speed_change_done nit*/ 3317 PHYMOD_IF_ERR_RETURN (_temod_wait_sc_stats_set(pc)); 3318 } 3319 return PHYMOD_E_NONE; 3320 } 3321 3322 /** 3323 @brief Checks config valid status for the port 3324 @param pc handle to current TSCE context (#PHYMOD_ST) 3325 @param port_num Port Number 3326 @returns The value PHYMOD_E_NONE upon successful completion 3327 @details This register bit indicates that PCS is now programmed as required by 3328 the HT entry for that speed 3329 */ 3330 int temod_master_port_num_set( PHYMOD_ST *pc, int port_num) 3331 { 3332 MAIN0_SETUPr_t main_reg; 3333 TEMOD_DBG_IN_FUNC_VIN_INFO(pc,("port_num: %d", port_num)); 3334 3335 MAIN0_SETUPr_CLR(main_reg); 3336 MAIN0_SETUPr_MASTER_PORT_NUMf_SET(main_reg, port_num); 3337 MODIFY_MAIN0_SETUPr(pc, main_reg); 3338 3339 return PHYMOD_E_NONE; 3340 } 3341 3342 /** 3343 @brief update the port mode 3344 @param pc handle to current TSCE context (#PHYMOD_ST) 3345 @param pll_restart Indicates if required to restart PLL. 3346 @returns The value PHYMOD_E_NONE upon successful completion 3347 */ 3348 int temod_update_port_mode( PHYMOD_ST *pc, int *pll_restart) 3349 { 3350 MAIN0_SETUPr_t mode_reg; 3351 int port_mode_sel, port_mode_sel_reg, temp_pll_restart; 3352 uint32_t single_port_mode; 3353 uint32_t first_couple_mode = 0, second_couple_mode = 0; 3354 3355 port_mode_sel = 0 ; 3356 single_port_mode = 0 ; 3357 temp_pll_restart = 0; 3358 3359 READ_MAIN0_SETUPr(pc, &mode_reg); 3360 port_mode_sel_reg = MAIN0_SETUPr_PORT_MODE_SELf_GET(mode_reg); 3361 3362 if(pc->lane_mask == 0xf){ 3363 port_mode_sel = 4; 3364 if( port_mode_sel_reg != 4){ 3365 temp_pll_restart = 1; 3366 } 3367 } else{ 3368 first_couple_mode = ((port_mode_sel_reg == 2) || (port_mode_sel_reg == 3) || (port_mode_sel_reg == 4)); 3369 second_couple_mode = ((port_mode_sel_reg == 1) || (port_mode_sel_reg == 3) || (port_mode_sel_reg == 4)); 3370 switch(pc->lane_mask){ 3371 case 1: 3372 case 2: 3373 first_couple_mode = 0; 3374 break; 3375 case 4: 3376 case 8: 3377 second_couple_mode = 0; 3378 break; 3379 case 3: 3380 first_couple_mode = 1; 3381 break; 3382 case 0xc: 3383 second_couple_mode = 1; 3384 break; 3385 default: 3386 /* dprintf("%-22s: ERROR port_mode_sel=%0d undefined\n", 3387 __func__, port_mode_sel_reg); */ 3388 break ; 3389 } 3390 3391 if(first_couple_mode ){ 3392 port_mode_sel =(second_couple_mode)? 3: 2; 3393 } 3394 else if(second_couple_mode){ 3395 port_mode_sel = 1; 3396 } 3397 else{ 3398 port_mode_sel = 0 ; 3399 } 3400 } 3401 3402 *pll_restart = temp_pll_restart; 3403 3404 /*if(pc->verbosity & TEMOD_DBG_INIT) 3405 dprintf("%-22s u=%0d p=%0d port_mode_sel old=%0d new=%0d\n", __func__, 3406 pc->unit, pc->port, port_mode_sel_reg, port_mode_sel) ; */ 3407 3408 MAIN0_SETUPr_SINGLE_PORT_MODEf_SET(mode_reg, single_port_mode); 3409 MAIN0_SETUPr_PORT_MODE_SELf_SET(mode_reg, port_mode_sel); 3410 MODIFY_MAIN0_SETUPr(pc, mode_reg); 3411 TEMOD_DBG_IN_FUNC_VOUT_INFO(pc,("pll_restart: %d", *pll_restart)); 3412 return PHYMOD_E_NONE ; 3413 } 3414 3415 /** 3416 @brief enable the pll reset bit 3417 @param pc handle to current TSCE context (#PHYMOD_ST) 3418 @param enable pll reset enable or not 3419 @returns The value PHYMOD_E_NONE upon successful completion 3420 */ 3421 int temod_pll_reset_enable_set (PHYMOD_ST *pc , int enable) 3422 { 3423 MAIN0_SETUPr_t main_reg; 3424 3425 MAIN0_SETUPr_CLR(main_reg); 3426 MAIN0_SETUPr_PLL_RESET_ENf_SET(main_reg, enable); 3427 MODIFY_MAIN0_SETUPr(pc, main_reg); 3428 return PHYMOD_E_NONE ; 3429 } 3430 3431 /** 3432 @brief Checks config valid status for the port 3433 @param pc handle to current TSCE context (#PHYMOD_ST) 3434 @returns The value PHYMOD_E_NONE upon successful completion 3435 @details This function is only used by other Tier1 functions. It is not exposed 3436 to Tier2s. It reads a specific register bit that indicates that PCS has 3437 configured all its blocks for the HT entry for the desired speed. 3438 */ 3439 int _temod_wait_sc_stats_set(PHYMOD_ST* pc) 3440 { 3441 uint16_t data; 3442 uint16_t i; 3443 SC_X4_STSr_t reg_sc_ctrl_sts; 3444 3445 SC_X4_STSr_CLR(reg_sc_ctrl_sts); 3446 3447 #ifdef _DV_TB_ 3448 while(1){ 3449 i=i+1; /* added only to eliminate compile warning */ 3450 PHYMOD_IF_ERR_RETURN(READ_SC_X4_STSr(pc, ®_sc_ctrl_sts)); 3451 data = SC_X4_STSr_SW_SPEED_CONFIG_VLDf_GET(reg_sc_ctrl_sts); 3452 if(data == 1) 3453 break; 3454 } 3455 return PHYMOD_E_NONE; 3456 #endif /* _DV_TB_ */ 3457 #ifdef _SDK_TEMOD_ 3458 for (i= 0; i < 10; i++) { 3459 PHYMOD_USLEEP(1); 3460 PHYMOD_IF_ERR_RETURN(READ_SC_X4_STSr(pc, ®_sc_ctrl_sts)); 3461 data = SC_X4_STSr_SW_SPEED_CONFIG_VLDf_GET(reg_sc_ctrl_sts); 3462 if(data == 1) 3463 break; 3464 } 3465 if (data != 1) { 3466 return PHYMOD_E_TIMEOUT; 3467 } 3468 else { 3469 return PHYMOD_E_NONE; 3470 } 3471 #endif /* _SDK_TEMOD_ */ 3472 } 3473 3474 /** 3475 @brief Read PCS Link status 3476 @param pc handle to current TSCE context (#PHYMOD_ST) 3477 @param *link Reference for Status of PCS Link 3478 @returns The value PHYMOD_E_NONE upon successful completion 3479 @details Return the status of the PCS link. The link up implies the PCS is able 3480 to decode the digital bits coming in on the serdes. It automatically implies 3481 that the PLL is stable and that the PMD sublayer has successfully recovered the 3482 clock on the receive line. 3483 */ 3484 int temod_get_pcs_link_status(PHYMOD_ST* pc, uint32_t *link) 3485 { 3486 RX_X4_PCS_LIVE_STSr_t reg_pcs_live_sts; 3487 3488 TEMOD_DBG_IN_FUNC_INFO(pc); 3489 RX_X4_PCS_LIVE_STSr_CLR(reg_pcs_live_sts); 3490 PHYMOD_IF_ERR_RETURN (READ_RX_X4_PCS_LIVE_STSr(pc, ®_pcs_live_sts)); 3491 *link = RX_X4_PCS_LIVE_STSr_LINK_STATUSf_GET(reg_pcs_live_sts); 3492 TEMOD_DBG_IN_FUNC_VOUT_INFO(pc,("pcs_live_stats_link: %d", (int)*link)); 3493 3494 return PHYMOD_E_NONE; 3495 } 3496 3497 /** 3498 @brief Read PCS latched Link status 3499 @param pc handle to current TSCE context (#PHYMOD_ST) 3500 @param *link Reference for Status of PCS Link 3501 @returns The value PHYMOD_E_NONE upon successful completion 3502 @details Return the status of the PCS link latched version. The link up implies the PCS is able 3503 to decode the digital bits coming in on the serdes. It automatically implies 3504 that the PLL is stable and that the PMD sublayer has successfully recovered the 3505 clock on the receive line. 3506 */ 3507 int temod_get_pcs_latched_link_status(PHYMOD_ST* pc, uint32_t *link) 3508 { 3509 RX_X4_PCS_LIVE_STSr_t reg_pcs_live_sts; 3510 RX_X4_PCS_LATCH_STS0r_t latched_sts ; 3511 int latched_val ; 3512 3513 TEMOD_DBG_IN_FUNC_INFO(pc); 3514 RX_X4_PCS_LIVE_STSr_CLR(reg_pcs_live_sts); 3515 RX_X4_PCS_LATCH_STS0r_CLR(latched_sts) ; 3516 3517 PHYMOD_IF_ERR_RETURN (READ_RX_X4_PCS_LIVE_STSr(pc, ®_pcs_live_sts)); 3518 PHYMOD_IF_ERR_RETURN (READ_RX_X4_PCS_LATCH_STS0r(pc, &latched_sts)) ; 3519 latched_val = RX_X4_PCS_LATCH_STS0r_LINK_STATUS_LLf_GET(latched_sts) ; 3520 if(latched_val) { 3521 *link = 0 ; 3522 } else { 3523 *link = RX_X4_PCS_LIVE_STSr_LINK_STATUSf_GET(reg_pcs_live_sts); 3524 } 3525 3526 TEMOD_DBG_IN_FUNC_VOUT_INFO(pc,("pcs_latched_stats_link: %d LL=%0d", (int)*link, latched_val)); 3527 3528 return PHYMOD_E_NONE; 3529 } 3530 3531 #ifdef _DV_TB_ 3532 /** 3533 @brief Read the 16 bit rev. id value etc. 3534 @param pc handle to current TSCE context (#PHYMOD_ST) 3535 @returns The value PHYMOD_E_NONE upon successful completion 3536 @details Timers are set for verifying and speeding up Verification 3537 */ 3538 int temod_mld_am_timers_set(PHYMOD_ST* pc,int rx_am_timer_init_val,int tx_am_timer_init_val) /*MLD_AM_TIMERS_SET */ 3539 { 3540 CL82_RX_AM_TMRr_t reg_rx_am_timer; 3541 TX_X2_MLD_SWP_CNTr_t reg_mld_swap_cnt; 3542 3543 TEMOD_DBG_IN_FUNC_INFO(pc); 3544 CL82_RX_AM_TMRr_CLR(reg_rx_am_timer); 3545 TX_X2_MLD_SWP_CNTr_CLR(reg_mld_swap_cnt); 3546 3547 if(rx_am_timer_init_val != 0) { 3548 CL82_RX_AM_TMRr_SET(reg_rx_am_timer, rx_am_timer_init_val); 3549 PHYMOD_IF_ERR_RETURN (WRITE_CL82_RX_AM_TMRr(pc, reg_rx_am_timer)); 3550 } 3551 if(tx_am_timer_init_val != 0) { 3552 TX_X2_MLD_SWP_CNTr_SET(reg_mld_swap_cnt, tx_am_timer_init_val); 3553 PHYMOD_IF_ERR_RETURN (WRITE_TX_X2_MLD_SWP_CNTr(pc, reg_mld_swap_cnt)); 3554 } 3555 return PHYMOD_E_NONE; 3556 } 3557 #endif 3558 3559 #ifdef _SDK_TEMOD_ 3560 /** 3561 @brief Set the MLD counters 3562 @param pc handle to current TSCE context (#PHYMOD_ST) 3563 @returns The value PHYMOD_E_NONE upon successful completion 3564 @details MLD Timers are set 3565 */ 3566 int temod_mld_am_timers_set(PHYMOD_ST* pc) /*MLD_AM_TIMERS_SET */ 3567 { 3568 TX_X2_MLD_SWP_CNTr_t reg_mld_swap_cnt; 3569 3570 TEMOD_DBG_IN_FUNC_INFO(pc); 3571 TX_X2_MLD_SWP_CNTr_CLR(reg_mld_swap_cnt); 3572 3573 TX_X2_MLD_SWP_CNTr_SET(reg_mld_swap_cnt, 0xfffc); 3574 PHYMOD_IF_ERR_RETURN (WRITE_TX_X2_MLD_SWP_CNTr(pc, reg_mld_swap_cnt)); 3575 return PHYMOD_E_NONE; 3576 } 3577 #endif 3578 3579 3580 /** 3581 @brief Get the Port status 3582 @param pc handle to current TSCE context (#PHYMOD_ST) 3583 @param enable receives disable status of the port. 3584 @returns The value PHYMOD_E_NONE upon successful completion 3585 @details Ports can be disabled in several ways. In this function we simply write 3586 0 to the speed change which will bring the PCS down for that lane. 3587 3588 */ 3589 int temod_disable_get(PHYMOD_ST* pc, uint32_t* enable) 3590 { 3591 SC_X4_CTLr_t reg_sc_ctrl; 3592 3593 TEMOD_DBG_IN_FUNC_INFO(pc); 3594 SC_X4_CTLr_CLR(reg_sc_ctrl); 3595 3596 PHYMOD_IF_ERR_RETURN(READ_SC_X4_CTLr(pc,®_sc_ctrl)); 3597 *enable = SC_X4_CTLr_SW_SPEED_CHANGEf_GET(reg_sc_ctrl); 3598 3599 return PHYMOD_E_NONE; 3600 } 3601 3602 /** 3603 @brief Get info on Disable status of the Port 3604 @param pc handle to current TSCE context (#PHYMOD_ST) 3605 @returns The value PHYMOD_E_NONE upon successful completion 3606 @details Disables the port by writing 0 to the speed config logic in PCS. 3607 This makes the PCS to bring down the PCS blocks and also apply lane datapath 3608 reset to the PMD. There is no control input to this function since it only does 3609 one thing. 3610 3611 */ 3612 int temod_disable_set(PHYMOD_ST* pc) 3613 { 3614 SC_X4_CTLr_t reg_sc_ctrl; 3615 3616 TEMOD_DBG_IN_FUNC_INFO(pc); 3617 SC_X4_CTLr_CLR(reg_sc_ctrl); 3618 READ_SC_X4_CTLr(pc, ®_sc_ctrl); 3619 3620 /* write 0 to the speed change */ 3621 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(reg_sc_ctrl, 0); 3622 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_CTLr(pc,reg_sc_ctrl)); 3623 3624 return PHYMOD_E_NONE; 3625 } 3626 3627 /** 3628 @brief Get the plldiv from lookup table 3629 @param pc handle to current TSCE context (#PHYMOD_ST) 3630 @param spd_intf speed as specified by enum #temod_spd_intfc_type 3631 @param plldiv Receives the pll divider value 3632 @param speed_vec Receives the speed id. 3633 @returns The value PHYMOD_E_NONE upon successful completion 3634 @details Get the plldiv from lookup table 3635 */ 3636 int temod_plldiv_lkup_get(PHYMOD_ST* pc, temod_spd_intfc_type spd_intf, phymod_ref_clk_t ref_clk, uint32_t *plldiv, uint16_t *speed_vec) 3637 { 3638 int speed_id; 3639 3640 get_mapped_speed(spd_intf, &speed_id); 3641 if (ref_clk == phymodRefClk125Mhz) { 3642 *plldiv = eagle_sc_pmd_entry_125M_refclk[speed_id].pll_mode; 3643 } else { 3644 *plldiv = eagle_sc_pmd_entry[speed_id].pll_mode; 3645 } 3646 *speed_vec = speed_id ; 3647 TEMOD_DBG_IN_FUNC_VOUT_INFO(pc,("plldiv: %d", *plldiv)); 3648 3649 return PHYMOD_E_NONE; 3650 } 3651 3652 /** 3653 @brief Get the osmode from lookup table for the given speed 3654 @param pc handle to current TSCE context (#PHYMOD_ST) 3655 @param spd_intf the speed type as in enum #temod_spd_intfc_type 3656 @param osmode receives the osmode 3657 @returns The value PHYMOD_E_NONE upon successful completion 3658 @details Get the osmode from software copy of Speed table 3659 */ 3660 int temod_osmode_lkup_get(PHYMOD_ST* pc, temod_spd_intfc_type spd_intf, uint32_t *osmode) 3661 { 3662 int speed_id; 3663 3664 get_mapped_speed(spd_intf, &speed_id); 3665 *osmode = eagle_sc_pmd_entry[speed_id].t_pma_os_mode; 3666 TEMOD_DBG_IN_FUNC_VOUT_INFO(pc,("osmode: %d", (int)*osmode)); 3667 3668 return PHYMOD_E_NONE; 3669 } 3670 3671 /** 3672 @brief Get the osdfe from lookup table for the given speed 3673 @param pc handle to current TSCE context (#PHYMOD_ST) 3674 @param spd_intf the speed type as in enum #temod_spd_intfc_type 3675 @param osdfe_on receives the osdfe_on 3676 @returns The value PHYMOD_E_NONE upon successful completion 3677 @details Get the osdfe_on from software copy of Speed table. Dfe_on:1, Dfe_off=0 3678 */ 3679 int temod_osdfe_on_lkup_get(PHYMOD_ST* pc, temod_spd_intfc_type spd_intf, uint32_t* osdfe_on) 3680 { 3681 int speed_id; 3682 3683 get_mapped_speed(spd_intf, &speed_id); 3684 *osdfe_on = eagle_sc_pmd_entry[speed_id].osdfe_on; 3685 TEMOD_DBG_IN_FUNC_VOUT_INFO(pc,("osdfe_on: %d", (int)*osdfe_on)); 3686 3687 return PHYMOD_E_NONE; 3688 } 3689 3690 /** 3691 @brief Get the scrambling_dis from lookup table for the given speed 3692 @param pc handle to current TSCE context (#PHYMOD_ST) 3693 @param spd_intf the speed type as in enum #temod_spd_intfc_type 3694 @param scrambling_dis receives the scrambling_dis 3695 @returns The value PHYMOD_E_NONE upon successful completion 3696 @details Get the scrambling_dis from software copy of Speed table. scrambling_dis:0, scrambling_dis : 1 3697 */ 3698 int temod_scrambling_dis_lkup_get(PHYMOD_ST* pc, temod_spd_intfc_type spd_intf, uint32_t* scrambling_dis) 3699 { 3700 int speed_id; 3701 3702 get_mapped_speed(spd_intf, &speed_id); 3703 *scrambling_dis = eagle_sc_pmd_entry[speed_id].scrambling_dis; 3704 TEMOD_DBG_IN_FUNC_VOUT_INFO(pc,("scrambling_dis: %d", (int)*scrambling_dis)); 3705 3706 return PHYMOD_E_NONE; 3707 } 3708 3709 3710 3711 #ifdef _DV_TB_ 3712 #endif /* _DV_TB_ */ 3713 3714 3715 /** 3716 @brief Select the ILKN path and bypass TSCF PCS 3717 @param pc handle to current TSCF context (#PHYMOD_ST) 3718 @returns The value PHYMOD_E_NONE upon successful completion 3719 @details This will enable ILKN path. PCS is set to bypass to relinquish PMD 3720 control. Expect PMD to be programmed elsewhere. 3721 */ 3722 int temod_pcs_ilkn_mode_set(PHYMOD_ST* pc) /* INIT_PCS_ILKN */ 3723 { 3724 SC_X4_BYPASSr_t reg_sc_bypass; 3725 3726 TEMOD_DBG_IN_FUNC_INFO(pc); 3727 SC_X4_BYPASSr_CLR(reg_sc_bypass); 3728 SC_X4_BYPASSr_SC_BYPASSf_SET(reg_sc_bypass, 1); 3729 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_BYPASSr(pc,reg_sc_bypass)); 3730 3731 return PHYMOD_E_NONE; 3732 } 3733 3734 /** 3735 @brief Select the ILKN path and bypass TSCE PCS 3736 @param pc handle to current TSCE context (#PHYMOD_ST) 3737 @returns The value PHYMOD_E_NONE upon successful completion 3738 @details This will enable ILKN path. PCS is set to bypass to relinquish PMD 3739 control. Expect PMD to be programmed elsewhere. If we need the QSGMII PCS expect 3740 the QSGMII to be already programmed at the port layer. If not, we will feed 3741 garbage to the ILKN path. 3742 */ 3743 int temod_init_pcs_ilkn(PHYMOD_ST* pc) /* INIT_PCS */ 3744 { 3745 ILKN_CTL0r_t reg_ilkn_ctrl0; 3746 3747 TEMOD_DBG_IN_FUNC_INFO(pc); 3748 ILKN_CTL0r_CLR(reg_ilkn_ctrl0); 3749 3750 ILKN_CTL0r_ILKN_SELf_SET(reg_ilkn_ctrl0, 1); 3751 ILKN_CTL0r_CREDIT_ENf_SET(reg_ilkn_ctrl0, 1); 3752 PHYMOD_IF_ERR_RETURN(MODIFY_ILKN_CTL0r(pc, reg_ilkn_ctrl0)); 3753 3754 return PHYMOD_E_NONE; 3755 } 3756 3757 /** 3758 @brief Check if ILKN is set 3759 @param pc handle to current TSCF context (#PHYMOD_ST), ilkn_set status 3760 @returns The value PHYMOD_E_NONE upon successful completion 3761 @details Check if ILKN is set, ilkn_set = 1 if it is set. 3762 */ 3763 int temod_pcs_ilkn_chk(PHYMOD_ST* pc, int *ilkn_set) /* INIT_PCS_ILKN */ 3764 { 3765 ILKN_CTL0r_t ILKN_CONTROL0r_reg; 3766 3767 TEMOD_DBG_IN_FUNC_INFO(pc); 3768 3769 PHYMOD_IF_ERR_RETURN(READ_ILKN_CTL0r(pc, &ILKN_CONTROL0r_reg)); 3770 3771 *ilkn_set = ILKN_CTL0r_ILKN_SELf_GET(ILKN_CONTROL0r_reg); 3772 3773 return PHYMOD_E_NONE; 3774 } 3775 3776 3777 /** 3778 @brief PMD per lane reset 3779 @param pc handle to current TSCE context (#PHYMOD_ST) 3780 @returns The value PHYMOD_E_NONE upon successful completion 3781 @details Per lane PMD ln_rst and ln_dp_rst by writing to PMD_X4_CONTROL in pcs space 3782 */ 3783 int temod_pmd_x4_reset(PHYMOD_ST* pc) /* PMD_X4_RESET */ 3784 { 3785 PMD_X4_CTLr_t reg_pmd_x4_ctrl; 3786 3787 TEMOD_DBG_IN_FUNC_INFO(pc); 3788 PMD_X4_CTLr_CLR(reg_pmd_x4_ctrl); 3789 PMD_X4_CTLr_LN_H_RSTBf_SET(reg_pmd_x4_ctrl,0); 3790 PMD_X4_CTLr_LN_DP_H_RSTBf_SET(reg_pmd_x4_ctrl,0); 3791 PHYMOD_IF_ERR_RETURN (MODIFY_PMD_X4_CTLr(pc, reg_pmd_x4_ctrl)); 3792 3793 PMD_X4_CTLr_CLR(reg_pmd_x4_ctrl); 3794 PMD_X4_CTLr_LN_H_RSTBf_SET(reg_pmd_x4_ctrl,1); 3795 PMD_X4_CTLr_LN_DP_H_RSTBf_SET(reg_pmd_x4_ctrl,1); 3796 PHYMOD_IF_ERR_RETURN (MODIFY_PMD_X4_CTLr(pc, reg_pmd_x4_ctrl)); 3797 3798 return PHYMOD_E_NONE; 3799 } 3800 3801 3802 /** 3803 @brief PMD per lane reset get 3804 @param pc handle to current TSCE context (#PHYMOD_ST) 3805 @returns The value PHYMOD_E_NONE upon successful completion 3806 @details Per lane PMD ln_rst and ln_dp_rst by writing to PMD_X4_CONTROL in pcs space 3807 */ 3808 int temod_pmd_x4_reset_get(PHYMOD_ST* pc, int *is_in_reset) /* PMD_X4_RESET */ 3809 { 3810 PMD_X4_CTLr_t reg_pmd_x4_ctrl; 3811 3812 TEMOD_DBG_IN_FUNC_INFO(pc); 3813 PMD_X4_CTLr_CLR(reg_pmd_x4_ctrl); 3814 PHYMOD_IF_ERR_RETURN (READ_PMD_X4_CTLr(pc, ®_pmd_x4_ctrl)); 3815 3816 if(PMD_X4_CTLr_LN_H_RSTBf_GET(reg_pmd_x4_ctrl) && 3817 PMD_X4_CTLr_LN_DP_H_RSTBf_GET(reg_pmd_x4_ctrl)) { 3818 *is_in_reset = 0 ; 3819 } else { 3820 *is_in_reset = 1 ; 3821 } 3822 return PHYMOD_E_NONE; 3823 } 3824 3825 #ifdef _DV_TB_ 3826 /** 3827 @brief Initialize the PMD in independent mode. (No PCS involved) 3828 @param pc handle to current TSCE context (#PHYMOD_ST) 3829 @param pmd_touched Is the pmd already programmed (i.e. pll running) 3830 @param uc_active Is the uctlr already active (implies firmware loaded) 3831 @param spd_intf enum #temod_spd_intfc_type 3832 @param t_pma_os_mode per lane OS Mode in PMD 3833 @returns The value PHYMOD_E_NONE upon successful completion 3834 @details Per Port PMD Init done by software 3835 */ 3836 int temod_init_pmd_sw(PHYMOD_ST* pc, int pmd_touched, int uc_active, 3837 temod_spd_intfc_type spd_intf, int t_pma_os_mode) /* INIT_PMD_SW */ 3838 { 3839 TEMOD_DBG_IN_FUNC_INFO(pc); 3840 temod_init_pmd(pc, pmd_touched, uc_active); 3841 temod_pmd_osmode_set(pc, spd_intf, t_pma_os_mode); 3842 3843 return PHYMOD_E_NONE; 3844 } 3845 #endif /* _DV_TB_ */ 3846 3847 3848 #ifdef _DV_TB_ 3849 /** 3850 @brief Initialize PMD. for both PCS and independent modes. 3851 @param pc handle to current TSCE context (#PHYMOD_ST) 3852 @param pmd_touched If set, indicates PMD was previously initialized for another 3853 port in the same core. 3854 @param uc_active implies the ucntlr is active 3855 @returns PHYMOD_E_NONE upon success, PHYMOD_E_FAIL else. 3856 @details Per Port PMD Init 3857 3858 */ 3859 int temod_init_pmd(PHYMOD_ST* pc, int pmd_touched, int uc_active) /* INIT_PMD */ 3860 { 3861 CKRST_LN_CLK_RST_N_PWRDWN_CTLr_t reg_pwrdwn_ctrl; 3862 DIG_TOP_USER_CTL0r_t reg_usr_ctrl; 3863 3864 TEMOD_DBG_IN_FUNC_INFO(pc); 3865 TEMOD_DBG_IN_FUNC_VIN_INFO(pc, ("pmd_touched: %d, uc_active: %d",pmd_touched, uc_active)); 3866 3867 CKRST_LN_CLK_RST_N_PWRDWN_CTLr_CLR(reg_pwrdwn_ctrl); 3868 DIG_TOP_USER_CTL0r_CLR(reg_usr_ctrl); 3869 3870 CKRST_LN_CLK_RST_N_PWRDWN_CTLr_LN_DP_S_RSTBf_SET(reg_pwrdwn_ctrl, 1); 3871 PHYMOD_IF_ERR_RETURN(MODIFY_CKRST_LN_CLK_RST_N_PWRDWN_CTLr(pc, reg_pwrdwn_ctrl)); 3872 3873 if (pmd_touched == 0) { 3874 if(uc_active == 1){ 3875 DIG_TOP_USER_CTL0r_UC_ACTIVEf_SET(reg_usr_ctrl, 1); 3876 DIG_TOP_USER_CTL0r_CORE_DP_S_RSTBf_SET(reg_usr_ctrl, 1); 3877 /* release reset to pll data path. TBD need for all lanes and uc_active set */ 3878 PHYMOD_IF_ERR_RETURN (MODIFY_DIG_TOP_USER_CTL0r(pc, reg_usr_ctrl)); 3879 } else{ 3880 DIG_TOP_USER_CTL0r_CORE_DP_S_RSTBf_SET(reg_usr_ctrl, 1); 3881 PHYMOD_IF_ERR_RETURN (MODIFY_DIG_TOP_USER_CTL0r(pc, reg_usr_ctrl)); 3882 } 3883 } 3884 return PHYMOD_E_NONE; 3885 } 3886 #endif /* _DV_TB_ */ 3887 3888 3889 /** 3890 @brief Set Per lane OS mode set in PMD 3891 @param pc handle to current TSCE context (#PHYMOD_ST) 3892 @param spd_intf speed type #temod_spd_intfc_type 3893 @param os_mode over sample rate. 3894 @returns The value PHYMOD_E_NONE upon successful completion 3895 @details Per Port PMD Init 3896 3897 */ 3898 int temod_pmd_osmode_set(PHYMOD_ST* pc, temod_spd_intfc_type spd_intf, int os_mode) /* INIT_PMD */ 3899 { 3900 CKRST_OSR_MODE_CTLr_t reg_osr_mode; 3901 int speed; 3902 3903 TEMOD_DBG_IN_FUNC_INFO(pc); 3904 CKRST_OSR_MODE_CTLr_CLR(reg_osr_mode); 3905 get_mapped_speed(spd_intf, &speed); 3906 3907 /*os_mode = 0x0; */ /* 0= OS MODE 1; 1= OS MODE 2; 2=OS MODE 3; 3908 3=OS MODE 3.3; 4=OS MODE 4; 5=OS MODE 5; 3909 6=OS MODE 8; 7=OS MODE 8.25; 8: OS MODE 10*/ 3910 if(os_mode & TEMOD_OVERRIDE_CFG) { 3911 os_mode = (os_mode) & 0x0000ffff; 3912 } 3913 else { 3914 os_mode = eagle_sc_pmd_entry[speed].t_pma_os_mode; 3915 } 3916 3917 CKRST_OSR_MODE_CTLr_OSR_MODE_FRCf_SET(reg_osr_mode, 1); 3918 CKRST_OSR_MODE_CTLr_OSR_MODE_FRC_VALf_SET(reg_osr_mode, os_mode); 3919 3920 PHYMOD_IF_ERR_RETURN 3921 (MODIFY_CKRST_OSR_MODE_CTLr(pc, reg_osr_mode)); 3922 3923 return PHYMOD_E_NONE; 3924 } 3925 3926 /** 3927 @brief Get Per lane OS mode set in PMD 3928 @param pc handle to current TSCE context (#PHYMOD_ST) 3929 @param os_mode over sample rate. 3930 @returns The value PHYMOD_E_NONE upon successful completion 3931 @details Per Port PMD Init 3932 3933 */ 3934 int temod_pmd_osmode_get(PHYMOD_ST* pc, int *os_mode) /* INIT_PMD */ 3935 { 3936 CKRST_OSR_MODE_CTLr_t reg_osr_mode; 3937 3938 TEMOD_DBG_IN_FUNC_INFO(pc); 3939 CKRST_OSR_MODE_CTLr_CLR(reg_osr_mode); 3940 3941 PHYMOD_IF_ERR_RETURN 3942 (READ_CKRST_OSR_MODE_CTLr(pc, ®_osr_mode)); 3943 3944 if(CKRST_OSR_MODE_CTLr_OSR_MODE_FRCf_GET(reg_osr_mode) == 1) 3945 *os_mode = CKRST_OSR_MODE_CTLr_OSR_MODE_FRC_VALf_GET(reg_osr_mode); 3946 else 3947 *os_mode = 0xff; 3948 3949 return PHYMOD_E_NONE; 3950 } 3951 3952 3953 /** 3954 @brief Enable FEC for forced Speeds. Will be rewritten in FEC_control 3955 @param pc handle to current TSCE context (#PHYMOD_ST) 3956 @param fec_enable To enable or not. 3957 @returns The value PHYMOD_E_NONE upon successful completion 3958 @details Enable FEC for forced speeds. 3959 */ 3960 int temod_fecmode_set(PHYMOD_ST* pc, int fec_enable) /* FECMODE_SET */ 3961 { 3962 TX_X4_MISCr_t reg_misc; 3963 RX_X4_DEC_CTL0r_t reg_decode; 3964 phymod_access_t pa_copy; 3965 int start_lane = 0, num_lane = 0; 3966 uint32_t enable=0; 3967 3968 TEMOD_DBG_IN_FUNC_INFO(pc); 3969 TX_X4_MISCr_CLR(reg_misc); 3970 RX_X4_DEC_CTL0r_CLR(reg_decode); 3971 3972 /* need to figure out what's the starting lane */ 3973 PHYMOD_MEMCPY(&pa_copy, pc, sizeof(pa_copy)); 3974 PHYMOD_IF_ERR_RETURN 3975 (phymod_util_lane_config_get(pc, &start_lane, &num_lane)); 3976 pa_copy.lane_mask = 0x1 << start_lane; 3977 3978 TX_X4_MISCr_FEC_ENABLEf_SET(reg_misc, fec_enable); 3979 PHYMOD_IF_ERR_RETURN (MODIFY_TX_X4_MISCr(pc, reg_misc)); 3980 3981 RX_X4_DEC_CTL0r_BLOCK_SYNC_MODEf_SET(reg_decode, (fec_enable << 2)); 3982 PHYMOD_IF_ERR_RETURN (MODIFY_RX_X4_DEC_CTL0r(pc, reg_decode)); 3983 3984 temod_disable_get(&pa_copy,&enable); 3985 if(enable == 0x1) { 3986 PHYMOD_IF_ERR_RETURN (temod_trigger_speed_change(&pa_copy)); 3987 } 3988 3989 return PHYMOD_E_NONE; 3990 } 3991 3992 /** 3993 @brief Get FEC Setting for forced Speeds. Will be rewritten in FEC_control 3994 @param pc handle to current TSCE context (#PHYMOD_ST) 3995 @param fec_enable To get status 3996 @returns The value PHYMOD_E_NONE upon successful completion 3997 @details FEC Status for forced speeds. 3998 */ 3999 int temod_fecmode_get(PHYMOD_ST* pc, uint32_t *fec_enable) /* FECMODE_GET */ 4000 { 4001 TX_X4_MISCr_t reg_misc; 4002 SC_X4_CTLr_t reg; 4003 AN_X4_ENSr_t reg_an_enb; 4004 AN_X4_AN_ABIL_RESOLUTION_STSr_t an_hcd_status; 4005 4006 4007 TEMOD_DBG_IN_FUNC_INFO(pc); 4008 TX_X4_MISCr_CLR(reg_misc); 4009 SC_X4_CTLr_CLR(reg); 4010 AN_X4_ENSr_CLR(reg_an_enb); 4011 4012 PHYMOD_IF_ERR_RETURN(READ_SC_X4_CTLr(pc, ®)); 4013 PHYMOD_IF_ERR_RETURN (READ_AN_X4_ENSr(pc, ®_an_enb)); 4014 4015 *fec_enable = 0; 4016 if(AN_X4_ENSr_CL73_ENABLEf_GET(reg_an_enb) == 1){ 4017 READ_AN_X4_AN_ABIL_RESOLUTION_STSr(pc,&an_hcd_status); 4018 *fec_enable = AN_X4_AN_ABIL_RESOLUTION_STSr_AN_HCD_FECf_GET(an_hcd_status); 4019 } else if(SC_X4_CTLr_SW_SPEED_CHANGEf_GET(reg) == 1) { 4020 PHYMOD_IF_ERR_RETURN (READ_TX_X4_MISCr(pc, ®_misc)); 4021 *fec_enable = TX_X4_MISCr_FEC_ENABLEf_GET(reg_misc); 4022 } 4023 4024 return PHYMOD_E_NONE; 4025 } 4026 4027 int temod_override_clear(PHYMOD_ST* pc, override_type_t or_type) 4028 { 4029 SC_X4_FLD_OVRR_EN0_TYPEr_t reg_or_en0; 4030 4031 TEMOD_DBG_IN_FUNC_INFO(pc); 4032 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(reg_or_en0); 4033 switch(or_type) { 4034 case TEMOD_OVERRIDE_SCR_MODE: 4035 /*Set the override disable*/ 4036 SC_X4_FLD_OVRR_EN0_TYPEr_SCR_MODE_OENf_SET(reg_or_en0,0); 4037 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc,reg_or_en0)); 4038 break; 4039 case TEMOD_OVERRIDE_DESCR_MODE: 4040 /*Set the override disable*/ 4041 SC_X4_FLD_OVRR_EN0_TYPEr_DESCRAMBLERMODE_OENf_SET(reg_or_en0,0); 4042 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc,reg_or_en0)); 4043 break; 4044 default: 4045 return PHYMOD_E_UNAVAIL; 4046 } 4047 return PHYMOD_E_NONE; 4048 } 4049 4050 /** 4051 @brief Generic Override mechanism. Any PCS parameter can be overridden. 4052 @param pc handle to current TSCE context (#PHYMOD_ST) 4053 @param or_type enum type #override_type_t 4054 @param or_val Value to override. (could be 1/0 or actual value) 4055 @returns The value PHYMOD_E_NONE upon successful completion 4056 @details The cntl encoding is as follows. 4057 NUM_LANES_OEN | 4058 OS_MODE_OEN | 4059 FEC_ENABLE_OEN | 4060 DESKEWMODE_OEN | 4061 DESC2_MODE_OEN | 4062 CL36BYTEDELETEMODE_OEN | 4063 BRCM64B66_DESCRAMBLER_ENABLE_OEN | 4064 CHK_END_EN_OEN | 4065 BLOCK_SYNC_MODE_OEN | 4066 DECODERMODE_OEN | 4067 ENCODEMODE_OEN | 4068 DESCRAMBLERMODE_OEN | 4069 SCR_MODE_OEN 4070 */ 4071 int temod_override_set(PHYMOD_ST* pc, override_type_t or_type, uint16_t or_val) /* OVERRIDE_SET */ 4072 { 4073 int or_value; 4074 SC_X4_FLD_OVRR_EN0_TYPEr_t reg_or_en0; 4075 SC_X4_FLD_OVRR_EN1_TYPEr_t reg_or_en1; 4076 CL72_LNK_CTLr_t reg_cl72_link_ctrl; 4077 SC_X4_LN_NUM_OVRRr_t reg_ln_num_or_val; 4078 RX_X4_PMA_CTL0r_t reg_os_mode_or_val; 4079 TX_X4_MISCr_t reg_misc_or_val; 4080 RX_X4_PCS_CTL0r_t reg_pcs_or_val; 4081 RX_X2_MISC0r_t reg_misc0_or_val; 4082 RX_X4_DEC_CTL0r_t reg_dec_or_val; 4083 RX_X4_CL36_RX0r_t reg_cl36_or_val; 4084 TX_X4_ENC0r_t reg_encode_or_val; 4085 4086 TEMOD_DBG_IN_FUNC_INFO(pc); 4087 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(reg_or_en0); 4088 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(reg_or_en1); 4089 4090 or_value = or_val & 0x0000ffff; 4091 switch(or_type) { 4092 case TEMOD_OVERRIDE_RESET : 4093 /* reset credits */ 4094 WRITE_SC_X4_FLD_OVRR_EN0_TYPEr(pc,reg_or_en0); 4095 4096 SC_X4_FLD_OVRR_EN1_TYPEr_CL72_EN_OENf_SET(reg_or_en1, 0); 4097 SC_X4_FLD_OVRR_EN1_TYPEr_REORDER_EN_OENf_SET(reg_or_en1, 0); 4098 SC_X4_FLD_OVRR_EN1_TYPEr_CL36_EN_OENf_SET(reg_or_en1, 0); 4099 MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc,reg_or_en1); 4100 break; 4101 case TEMOD_OVERRIDE_ALL : 4102 /* get info. from table and apply it to all credit regs. */ 4103 break; 4104 case TEMOD_OVERRIDE_SPDID : 4105 break; 4106 case TEMOD_OVERRIDE_CL72 : 4107 CL72_LNK_CTLr_CLR(reg_cl72_link_ctrl); 4108 CL72_LNK_CTLr_LINK_CONTROL_FORCEVALf_SET(reg_cl72_link_ctrl, or_value); 4109 MODIFY_CL72_LNK_CTLr(pc,reg_cl72_link_ctrl); 4110 /*Set the override enable*/ 4111 SC_X4_FLD_OVRR_EN1_TYPEr_CL72_EN_OENf_SET(reg_or_en1, 1); 4112 MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc,reg_or_en1); 4113 break; 4114 case TEMOD_OVERRIDE_NUM_LANES : 4115 SC_X4_LN_NUM_OVRRr_CLR(reg_ln_num_or_val); 4116 SC_X4_LN_NUM_OVRRr_NUM_LANES_OVERRIDE_VALUEf_SET(reg_ln_num_or_val,or_value); 4117 MODIFY_SC_X4_LN_NUM_OVRRr(pc,reg_ln_num_or_val); 4118 /*Set the override enable*/ 4119 SC_X4_FLD_OVRR_EN0_TYPEr_NUM_LANES_OENf_SET(reg_or_en0,1); 4120 MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc,reg_or_en0); 4121 break; 4122 case TEMOD_OVERRIDE_OS_MODE: 4123 RX_X4_PMA_CTL0r_CLR(reg_os_mode_or_val); 4124 RX_X4_PMA_CTL0r_OS_MODEf_SET(reg_os_mode_or_val,or_value); 4125 MODIFY_RX_X4_PMA_CTL0r(pc,reg_os_mode_or_val); 4126 /*Set the override enable*/ 4127 SC_X4_FLD_OVRR_EN0_TYPEr_OS_MODE_OENf_SET(reg_or_en0,1); 4128 MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc,reg_or_en0); 4129 break; 4130 case TEMOD_OVERRIDE_FEC_EN : 4131 TX_X4_MISCr_CLR(reg_misc_or_val); 4132 TX_X4_MISCr_FEC_ENABLEf_SET(reg_misc_or_val,or_value); 4133 MODIFY_TX_X4_MISCr(pc,reg_misc_or_val); 4134 /*Set the override enable*/ 4135 SC_X4_FLD_OVRR_EN0_TYPEr_FEC_ENABLE_OENf_SET(reg_or_en0,1); 4136 MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc,reg_or_en0); 4137 break; 4138 case TEMOD_OVERRIDE_DESKEW_MODE: 4139 RX_X4_PCS_CTL0r_CLR(reg_pcs_or_val); 4140 RX_X4_PCS_CTL0r_DESKEWMODEf_SET(reg_pcs_or_val,or_value); 4141 MODIFY_RX_X4_PCS_CTL0r(pc,reg_pcs_or_val); 4142 /*Set the override enable*/ 4143 SC_X4_FLD_OVRR_EN0_TYPEr_DESKEWMODE_OENf_SET(reg_or_en0,1); 4144 MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc,reg_or_en0); 4145 break; 4146 case TEMOD_OVERRIDE_DESC2_MODE : 4147 RX_X4_PCS_CTL0r_CLR(reg_pcs_or_val); 4148 RX_X4_PCS_CTL0r_DESC2_MODEf_SET(reg_pcs_or_val,or_value); 4149 MODIFY_RX_X4_PCS_CTL0r(pc,reg_pcs_or_val); 4150 /*Set the override enable*/ 4151 SC_X4_FLD_OVRR_EN0_TYPEr_DESC2_MODE_OENf_SET(reg_or_en0,1); 4152 MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc,reg_or_en0); 4153 break; 4154 case TEMOD_OVERRIDE_CL36BYTEDEL_MODE: 4155 RX_X4_PCS_CTL0r_CLR(reg_pcs_or_val); 4156 RX_X4_PCS_CTL0r_CL36BYTEDELETEMODEf_SET(reg_pcs_or_val,or_value); 4157 MODIFY_RX_X4_PCS_CTL0r(pc,reg_pcs_or_val); 4158 /*Set the override enable*/ 4159 SC_X4_FLD_OVRR_EN0_TYPEr_CL36BYTEDELETEMODE_OENf_SET(reg_or_en0,1); 4160 MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc,reg_or_en0); 4161 break; 4162 case TEMOD_OVERRIDE_BRCM64B66_DESCR_MODE: 4163 RX_X4_PCS_CTL0r_CLR(reg_pcs_or_val); 4164 RX_X4_PCS_CTL0r_BRCM64B66_DESCRAMBLER_ENABLEf_SET(reg_pcs_or_val,or_value); 4165 MODIFY_RX_X4_PCS_CTL0r(pc,reg_pcs_or_val); 4166 /*Set the override enable*/ 4167 SC_X4_FLD_OVRR_EN0_TYPEr_BRCM64B66_DESCRAMBLER_ENABLE_OENf_SET(reg_or_en0,1); 4168 MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc,reg_or_en0); 4169 break; 4170 case TEMOD_OVERRIDE_CHKEND_EN: 4171 RX_X2_MISC0r_CLR(reg_misc0_or_val); 4172 RX_X2_MISC0r_CHK_END_ENf_SET(reg_misc0_or_val, or_value); 4173 MODIFY_RX_X2_MISC0r(pc,reg_misc0_or_val); 4174 /*Set the override enable*/ 4175 SC_X4_FLD_OVRR_EN0_TYPEr_CHK_END_EN_OENf_SET(reg_or_en0,1); 4176 MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc,reg_or_en0); 4177 break; 4178 case TEMOD_OVERRIDE_BLKSYNC_MODE: 4179 RX_X4_DEC_CTL0r_CLR(reg_dec_or_val); 4180 RX_X4_DEC_CTL0r_BLOCK_SYNC_MODEf_SET(reg_dec_or_val,or_value); 4181 MODIFY_RX_X4_DEC_CTL0r(pc, reg_dec_or_val); 4182 /*Set the override enable*/ 4183 SC_X4_FLD_OVRR_EN0_TYPEr_BLOCK_SYNC_MODE_OENf_SET(reg_or_en0,1); 4184 MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc,reg_or_en0); 4185 break; 4186 case TEMOD_OVERRIDE_REORDER_EN : 4187 RX_X4_CL36_RX0r_CLR(reg_cl36_or_val); 4188 RX_X4_CL36_RX0r_REORDER_ENf_SET(reg_cl36_or_val, or_value); 4189 MODIFY_RX_X4_CL36_RX0r(pc,reg_cl36_or_val); 4190 /*Set the override enable*/ 4191 SC_X4_FLD_OVRR_EN1_TYPEr_REORDER_EN_OENf_SET(reg_or_en1, 1); 4192 MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc,reg_or_en1); 4193 break; 4194 case TEMOD_OVERRIDE_CL36_EN: 4195 RX_X4_CL36_RX0r_CLR(reg_cl36_or_val); 4196 RX_X4_CL36_RX0r_CL36_ENf_SET(reg_cl36_or_val, or_value); 4197 MODIFY_RX_X4_CL36_RX0r(pc,reg_cl36_or_val); 4198 /*Set the override enable*/ 4199 SC_X4_FLD_OVRR_EN1_TYPEr_CL36_EN_OENf_SET(reg_or_en1, 1); 4200 MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc,reg_or_en1); 4201 break; 4202 case TEMOD_OVERRIDE_SCR_MODE: 4203 TX_X4_MISCr_CLR(reg_misc_or_val); 4204 TX_X4_MISCr_SCR_MODEf_SET(reg_misc_or_val,or_value); 4205 MODIFY_TX_X4_MISCr(pc,reg_misc_or_val); 4206 /*Set the override enable*/ 4207 SC_X4_FLD_OVRR_EN0_TYPEr_SCR_MODE_OENf_SET(reg_or_en0,1); 4208 MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc,reg_or_en0); 4209 break; 4210 case TEMOD_OVERRIDE_DESCR_MODE: 4211 RX_X4_PCS_CTL0r_CLR(reg_pcs_or_val); 4212 RX_X4_PCS_CTL0r_DESCRAMBLERMODEf_SET(reg_pcs_or_val,or_value); 4213 MODIFY_RX_X4_PCS_CTL0r(pc,reg_pcs_or_val); 4214 /*Set the override enable*/ 4215 SC_X4_FLD_OVRR_EN0_TYPEr_DESCRAMBLERMODE_OENf_SET(reg_or_en0,1); 4216 MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc,reg_or_en0); 4217 break; 4218 case TEMOD_OVERRIDE_ENCODE_MODE: 4219 TX_X4_ENC0r_CLR(reg_encode_or_val); 4220 TX_X4_ENC0r_ENCODEMODEf_SET(reg_encode_or_val, or_value); 4221 MODIFY_TX_X4_ENC0r(pc,reg_encode_or_val); 4222 /*Set the override enable*/ 4223 SC_X4_FLD_OVRR_EN0_TYPEr_ENCODEMODE_OENf_SET(reg_or_en0,1); 4224 MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc,reg_or_en0); 4225 break; 4226 case TEMOD_OVERRIDE_DECODE_MODE: 4227 RX_X4_PCS_CTL0r_CLR(reg_pcs_or_val); 4228 RX_X4_PCS_CTL0r_DECODERMODEf_SET(reg_pcs_or_val,or_value); 4229 MODIFY_RX_X4_PCS_CTL0r(pc,reg_pcs_or_val); 4230 /*Set the override enable*/ 4231 SC_X4_FLD_OVRR_EN0_TYPEr_DECODERMODE_OENf_SET(reg_or_en0,1); 4232 MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc,reg_or_en0); 4233 break; 4234 } 4235 return PHYMOD_E_NONE; 4236 } 4237 4238 /** 4239 @brief Get the overriden PCS parameter overridden. 4240 @param pc handle to current TSCE context (#PHYMOD_ST) 4241 @param or_type enum type #override_type_t 4242 @param or_en enum type #override_type_t 4243 @param or_val Value to override. (could be 1/0 or actual value) 4244 @returns The value PHYMOD_E_NONE upon successful completion 4245 @details The cntl encoding is as follows. 4246 NUM_LANES_OEN | 4247 OS_MODE_OEN | 4248 FEC_ENABLE_OEN | 4249 DESKEWMODE_OEN | 4250 DESC2_MODE_OEN | 4251 CL36BYTEDELETEMODE_OEN | 4252 BRCM64B66_DESCRAMBLER_ENABLE_OEN | 4253 CHK_END_EN_OEN | 4254 BLOCK_SYNC_MODE_OEN | 4255 DECODERMODE_OEN | 4256 ENCODEMODE_OEN | 4257 DESCRAMBLERMODE_OEN | 4258 SCR_MODE_OEN 4259 */ 4260 int temod_override_get(PHYMOD_ST* pc, override_type_t or_type, uint16_t *or_en, uint16_t *or_val) /* OVERRIDE_GET */ 4261 { 4262 SC_X4_FLD_OVRR_EN0_TYPEr_t reg_or_en0; 4263 SC_X4_FLD_OVRR_EN1_TYPEr_t reg_or_en1; 4264 CL72_LNK_CTLr_t reg_cl72_link_ctrl; 4265 SC_X4_LN_NUM_OVRRr_t reg_ln_num_or_val; 4266 RX_X4_PMA_CTL0r_t reg_os_mode_or_val; 4267 TX_X4_MISCr_t reg_misc_or_val; 4268 RX_X4_PCS_CTL0r_t reg_pcs_or_val; 4269 RX_X2_MISC0r_t reg_misc0_or_val; 4270 RX_X4_DEC_CTL0r_t reg_dec_or_val; 4271 RX_X4_CL36_RX0r_t reg_cl36_or_val; 4272 TX_X4_ENC0r_t reg_encode_or_val; 4273 4274 TEMOD_DBG_IN_FUNC_INFO(pc); 4275 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(reg_or_en0); 4276 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(reg_or_en1); 4277 4278 switch(or_type) { 4279 case TEMOD_OVERRIDE_RESET : 4280 break; 4281 case TEMOD_OVERRIDE_ALL : 4282 /* get info. from table and apply it to all credit regs. */ 4283 break; 4284 case TEMOD_OVERRIDE_SPDID : 4285 break; 4286 case TEMOD_OVERRIDE_CL72 : 4287 CL72_LNK_CTLr_CLR(reg_cl72_link_ctrl); 4288 READ_CL72_LNK_CTLr(pc,®_cl72_link_ctrl); 4289 *or_val = CL72_LNK_CTLr_LINK_CONTROL_FORCEVALf_GET(reg_cl72_link_ctrl); 4290 /*Set the override enable*/ 4291 READ_SC_X4_FLD_OVRR_EN1_TYPEr(pc,®_or_en1); 4292 *or_en = SC_X4_FLD_OVRR_EN1_TYPEr_CL72_EN_OENf_GET(reg_or_en1); 4293 break; 4294 case TEMOD_OVERRIDE_NUM_LANES : 4295 SC_X4_LN_NUM_OVRRr_CLR(reg_ln_num_or_val); 4296 READ_SC_X4_LN_NUM_OVRRr(pc,®_ln_num_or_val); 4297 *or_val = SC_X4_LN_NUM_OVRRr_NUM_LANES_OVERRIDE_VALUEf_GET(reg_ln_num_or_val); 4298 /*Set the override enable*/ 4299 READ_SC_X4_FLD_OVRR_EN0_TYPEr(pc,®_or_en0); 4300 *or_en = SC_X4_FLD_OVRR_EN0_TYPEr_NUM_LANES_OENf_GET(reg_or_en0); 4301 break; 4302 case TEMOD_OVERRIDE_OS_MODE: 4303 RX_X4_PMA_CTL0r_CLR(reg_os_mode_or_val); 4304 READ_RX_X4_PMA_CTL0r(pc,®_os_mode_or_val); 4305 *or_val = RX_X4_PMA_CTL0r_OS_MODEf_GET(reg_os_mode_or_val); 4306 /*Set the override enable*/ 4307 READ_SC_X4_FLD_OVRR_EN0_TYPEr(pc,®_or_en0); 4308 *or_en = SC_X4_FLD_OVRR_EN0_TYPEr_OS_MODE_OENf_GET(reg_or_en0); 4309 break; 4310 case TEMOD_OVERRIDE_FEC_EN : 4311 TX_X4_MISCr_CLR(reg_misc_or_val); 4312 READ_TX_X4_MISCr(pc,®_misc_or_val); 4313 *or_val = TX_X4_MISCr_FEC_ENABLEf_GET(reg_misc_or_val); 4314 /*Set the override enable*/ 4315 READ_SC_X4_FLD_OVRR_EN0_TYPEr(pc,®_or_en0); 4316 *or_en = SC_X4_FLD_OVRR_EN0_TYPEr_FEC_ENABLE_OENf_GET(reg_or_en0); 4317 break; 4318 case TEMOD_OVERRIDE_DESKEW_MODE: 4319 RX_X4_PCS_CTL0r_CLR(reg_pcs_or_val); 4320 READ_RX_X4_PCS_CTL0r(pc,®_pcs_or_val); 4321 *or_val = RX_X4_PCS_CTL0r_DESKEWMODEf_GET(reg_pcs_or_val); 4322 /*Set the override enable*/ 4323 READ_SC_X4_FLD_OVRR_EN0_TYPEr(pc,®_or_en0); 4324 *or_en = SC_X4_FLD_OVRR_EN0_TYPEr_DESKEWMODE_OENf_GET(reg_or_en0); 4325 break; 4326 case TEMOD_OVERRIDE_DESC2_MODE : 4327 RX_X4_PCS_CTL0r_CLR(reg_pcs_or_val); 4328 READ_RX_X4_PCS_CTL0r(pc,®_pcs_or_val); 4329 *or_val = RX_X4_PCS_CTL0r_DESC2_MODEf_GET(reg_pcs_or_val); 4330 /*Set the override enable*/ 4331 READ_SC_X4_FLD_OVRR_EN0_TYPEr(pc,®_or_en0); 4332 *or_en = SC_X4_FLD_OVRR_EN0_TYPEr_DESC2_MODE_OENf_GET(reg_or_en0); 4333 break; 4334 case TEMOD_OVERRIDE_CL36BYTEDEL_MODE: 4335 RX_X4_PCS_CTL0r_CLR(reg_pcs_or_val); 4336 READ_RX_X4_PCS_CTL0r(pc,®_pcs_or_val); 4337 *or_val = RX_X4_PCS_CTL0r_CL36BYTEDELETEMODEf_GET(reg_pcs_or_val); 4338 /*Set the override enable*/ 4339 READ_SC_X4_FLD_OVRR_EN0_TYPEr(pc,®_or_en0); 4340 *or_en = SC_X4_FLD_OVRR_EN0_TYPEr_CL36BYTEDELETEMODE_OENf_GET(reg_or_en0); 4341 break; 4342 case TEMOD_OVERRIDE_BRCM64B66_DESCR_MODE: 4343 RX_X4_PCS_CTL0r_CLR(reg_pcs_or_val); 4344 READ_RX_X4_PCS_CTL0r(pc,®_pcs_or_val); 4345 *or_val = RX_X4_PCS_CTL0r_BRCM64B66_DESCRAMBLER_ENABLEf_GET(reg_pcs_or_val); 4346 /*Set the override enable*/ 4347 READ_SC_X4_FLD_OVRR_EN0_TYPEr(pc,®_or_en0); 4348 *or_en = SC_X4_FLD_OVRR_EN0_TYPEr_BRCM64B66_DESCRAMBLER_ENABLE_OENf_GET(reg_or_en0); 4349 break; 4350 case TEMOD_OVERRIDE_CHKEND_EN: 4351 RX_X2_MISC0r_CLR(reg_misc0_or_val); 4352 READ_RX_X2_MISC0r(pc,®_misc0_or_val); 4353 *or_val = RX_X2_MISC0r_CHK_END_ENf_GET(reg_misc0_or_val); 4354 /*Set the override enable*/ 4355 READ_SC_X4_FLD_OVRR_EN0_TYPEr(pc,®_or_en0); 4356 *or_en = SC_X4_FLD_OVRR_EN0_TYPEr_CHK_END_EN_OENf_GET(reg_or_en0); 4357 break; 4358 case TEMOD_OVERRIDE_BLKSYNC_MODE: 4359 RX_X4_DEC_CTL0r_CLR(reg_dec_or_val); 4360 READ_RX_X4_DEC_CTL0r(pc, ®_dec_or_val); 4361 *or_val = RX_X4_DEC_CTL0r_BLOCK_SYNC_MODEf_GET(reg_dec_or_val); 4362 /*Set the override enable*/ 4363 READ_SC_X4_FLD_OVRR_EN0_TYPEr(pc,®_or_en0); 4364 *or_en = SC_X4_FLD_OVRR_EN0_TYPEr_BLOCK_SYNC_MODE_OENf_GET(reg_or_en0); 4365 break; 4366 case TEMOD_OVERRIDE_REORDER_EN : 4367 RX_X4_CL36_RX0r_CLR(reg_cl36_or_val); 4368 READ_RX_X4_CL36_RX0r(pc,®_cl36_or_val); 4369 *or_val = RX_X4_CL36_RX0r_REORDER_ENf_GET(reg_cl36_or_val); 4370 /*Set the override enable*/ 4371 READ_SC_X4_FLD_OVRR_EN1_TYPEr(pc,®_or_en1); 4372 *or_en = SC_X4_FLD_OVRR_EN1_TYPEr_REORDER_EN_OENf_GET(reg_or_en1); 4373 break; 4374 case TEMOD_OVERRIDE_CL36_EN: 4375 RX_X4_CL36_RX0r_CLR(reg_cl36_or_val); 4376 READ_RX_X4_CL36_RX0r(pc,®_cl36_or_val); 4377 *or_val = RX_X4_CL36_RX0r_CL36_ENf_GET(reg_cl36_or_val); 4378 /*Set the override enable*/ 4379 READ_SC_X4_FLD_OVRR_EN1_TYPEr(pc,®_or_en1); 4380 *or_en = SC_X4_FLD_OVRR_EN1_TYPEr_CL36_EN_OENf_GET(reg_or_en1); 4381 break; 4382 case TEMOD_OVERRIDE_SCR_MODE: 4383 TX_X4_MISCr_CLR(reg_misc_or_val); 4384 READ_TX_X4_MISCr(pc,®_misc_or_val); 4385 *or_val = TX_X4_MISCr_SCR_MODEf_GET(reg_misc_or_val); 4386 /*Set the override enable*/ 4387 READ_SC_X4_FLD_OVRR_EN0_TYPEr(pc,®_or_en0); 4388 *or_en = SC_X4_FLD_OVRR_EN0_TYPEr_SCR_MODE_OENf_GET(reg_or_en0); 4389 break; 4390 case TEMOD_OVERRIDE_DESCR_MODE: 4391 RX_X4_PCS_CTL0r_CLR(reg_pcs_or_val); 4392 READ_RX_X4_PCS_CTL0r(pc,®_pcs_or_val); 4393 *or_val = RX_X4_PCS_CTL0r_DESCRAMBLERMODEf_GET(reg_pcs_or_val); 4394 /*Set the override enable*/ 4395 READ_SC_X4_FLD_OVRR_EN0_TYPEr(pc,®_or_en0); 4396 *or_en = SC_X4_FLD_OVRR_EN0_TYPEr_DESCRAMBLERMODE_OENf_GET(reg_or_en0); 4397 break; 4398 case TEMOD_OVERRIDE_ENCODE_MODE: 4399 TX_X4_ENC0r_CLR(reg_encode_or_val); 4400 READ_TX_X4_ENC0r(pc,®_encode_or_val); 4401 *or_val = TX_X4_ENC0r_ENCODEMODEf_GET(reg_encode_or_val); 4402 /*Set the override enable*/ 4403 READ_SC_X4_FLD_OVRR_EN0_TYPEr(pc,®_or_en0); 4404 *or_en = SC_X4_FLD_OVRR_EN0_TYPEr_ENCODEMODE_OENf_GET(reg_or_en0); 4405 break; 4406 case TEMOD_OVERRIDE_DECODE_MODE: 4407 RX_X4_PCS_CTL0r_CLR(reg_pcs_or_val); 4408 READ_RX_X4_PCS_CTL0r(pc,®_pcs_or_val); 4409 *or_val = RX_X4_PCS_CTL0r_DECODERMODEf_GET(reg_pcs_or_val); 4410 /*Set the override enable*/ 4411 READ_SC_X4_FLD_OVRR_EN0_TYPEr(pc,®_or_en0); 4412 *or_en = SC_X4_FLD_OVRR_EN0_TYPEr_DECODERMODE_OENf_GET(reg_or_en0); 4413 break; 4414 } 4415 return PHYMOD_E_NONE; 4416 } 4417 4418 /** 4419 @brief Override the credits. 4420 @param pc handle to current TSCE context (#PHYMOD_ST) 4421 @param credit_type type of credit to override #credit_type_t 4422 @param userCredit User override value 4423 @returns The value PHYMOD_E_NONE upon successful completion 4424 @details Credit override mechanism is a seperate function. However it is similar 4425 to other override mechanisms. 4426 */ 4427 int temod_credit_override_set(PHYMOD_ST* pc, credit_type_t credit_type, uint16_t userCredit) /* CREDIT_OVERRIDE_SET */ 4428 { 4429 SC_X4_FLD_OVRR_EN1_TYPEr_t reg_enable_type; 4430 TX_X4_CRED0r_t reg_credit0; 4431 TX_X4_CRED1r_t reg_credit1; 4432 TX_X4_LOOPCNTr_t reg_loopcnt; 4433 TX_X4_MAC_CREDGENCNTr_t reg_maccreditgen; 4434 TX_X4_PCS_CLKCNT0r_t reg_pcs_clk_cnt; 4435 TX_X4_PCS_CREDGENCNTr_t reg_pcs_creditgen; 4436 4437 TEMOD_DBG_IN_FUNC_INFO(pc); 4438 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(reg_enable_type); 4439 TX_X4_CRED0r_CLR(reg_credit0); 4440 TX_X4_CRED1r_CLR(reg_credit1); 4441 TX_X4_LOOPCNTr_CLR(reg_loopcnt); 4442 TX_X4_MAC_CREDGENCNTr_CLR(reg_maccreditgen); 4443 TX_X4_PCS_CLKCNT0r_CLR(reg_pcs_clk_cnt); 4444 TX_X4_PCS_CREDGENCNTr_CLR(reg_pcs_creditgen); 4445 4446 switch ( credit_type ) { 4447 case TEMOD_CREDIT_RESET: 4448 /* reset credits */ 4449 SC_X4_FLD_OVRR_EN1_TYPEr_CLOCKCNT0_OENf_SET(reg_enable_type, 0); 4450 SC_X4_FLD_OVRR_EN1_TYPEr_CLOCKCNT1_OENf_SET(reg_enable_type, 0); 4451 SC_X4_FLD_OVRR_EN1_TYPEr_LOOPCNT0_OENf_SET(reg_enable_type, 0); 4452 SC_X4_FLD_OVRR_EN1_TYPEr_LOOPCNT1_OENf_SET(reg_enable_type, 0); 4453 SC_X4_FLD_OVRR_EN1_TYPEr_REPLICATION_CNT_OENf_SET(reg_enable_type, 0); 4454 SC_X4_FLD_OVRR_EN1_TYPEr_MAC_CREDITGENCNT_OENf_SET(reg_enable_type, 0); 4455 SC_X4_FLD_OVRR_EN1_TYPEr_PCS_CREDITENABLE_OENf_SET(reg_enable_type, 0); 4456 SC_X4_FLD_OVRR_EN1_TYPEr_PCS_CLOCKCNT0_OENf_SET(reg_enable_type, 0); 4457 SC_X4_FLD_OVRR_EN1_TYPEr_PCS_CREDITGENCNT_OENf_SET(reg_enable_type, 0); 4458 SC_X4_FLD_OVRR_EN1_TYPEr_SGMII_SPD_SWITCH_OENf_SET(reg_enable_type, 0); 4459 4460 PHYMOD_IF_ERR_RETURN(WRITE_SC_X4_FLD_OVRR_EN1_TYPEr(pc, reg_enable_type)); 4461 break; 4462 case TEMOD_CREDIT_TABLE: 4463 /* get info. from table and apply it to all credit regs. */ 4464 break; 4465 case TEMOD_CREDIT_CLOCK_COUNT_0: 4466 /* write to clockcnt0 */ 4467 TX_X4_CRED0r_CLOCKCNT0f_SET(reg_credit0, userCredit); 4468 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_CRED0r(pc, reg_credit0)); 4469 /*Set the override enable*/ 4470 SC_X4_FLD_OVRR_EN1_TYPEr_CLOCKCNT0_OENf_SET(reg_enable_type, 1); 4471 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, reg_enable_type)); 4472 break; 4473 case TEMOD_CREDIT_CLOCK_COUNT_1: /* (cntl & 0x00020000) */ 4474 /* write to clockcnt1 */ 4475 TX_X4_CRED1r_CLOCKCNT1f_SET(reg_credit1, userCredit); 4476 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_CRED1r(pc, reg_credit1)); 4477 /*Set the override enable*/ 4478 SC_X4_FLD_OVRR_EN1_TYPEr_CLOCKCNT1_OENf_SET(reg_enable_type, 1); 4479 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, reg_enable_type)); 4480 break; 4481 case TEMOD_CREDIT_LOOP_COUNT_0: 4482 /* write to loopcnt0 */ 4483 TX_X4_LOOPCNTr_LOOPCNT0f_SET(reg_loopcnt, userCredit); 4484 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_LOOPCNTr(pc, reg_loopcnt)); 4485 /*Set the override enable*/ 4486 SC_X4_FLD_OVRR_EN1_TYPEr_LOOPCNT0_OENf_SET(reg_enable_type, 1); 4487 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, reg_enable_type)); 4488 break; 4489 case TEMOD_CREDIT_LOOP_COUNT_1: /* (cntl & 0x00080000) */ 4490 /* write to pcs_clockcnt0 */ 4491 TX_X4_LOOPCNTr_LOOPCNT1f_SET(reg_loopcnt, userCredit); 4492 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_LOOPCNTr(pc, reg_loopcnt)); 4493 /*Set the override enable*/ 4494 SC_X4_FLD_OVRR_EN1_TYPEr_LOOPCNT1_OENf_SET(reg_enable_type, 1); 4495 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, reg_enable_type)); 4496 break; 4497 case TEMOD_CREDIT_MAC: /* (cntl & 0x00100000) */ 4498 /* write to mac_creditgencnt */ 4499 TX_X4_MAC_CREDGENCNTr_MAC_CREDITGENCNTf_SET(reg_maccreditgen, userCredit); 4500 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_MAC_CREDGENCNTr(pc, reg_maccreditgen)); 4501 /*Set the override enable*/ 4502 SC_X4_FLD_OVRR_EN1_TYPEr_MAC_CREDITGENCNT_OENf_SET(reg_enable_type, 1); 4503 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, reg_enable_type)); 4504 break; 4505 case TEMOD_CREDIT_PCS_CLOCK_COUNT_0: /* (cntl & 0x00200000) */ 4506 /* write to pcs_clockcnt0 */ 4507 TX_X4_PCS_CLKCNT0r_PCS_CLOCKCNT0f_SET(reg_pcs_clk_cnt, userCredit); 4508 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_PCS_CLKCNT0r(pc, reg_pcs_clk_cnt)); 4509 /*Set the override enable*/ 4510 SC_X4_FLD_OVRR_EN1_TYPEr_PCS_CLOCKCNT0_OENf_SET(reg_enable_type, 1); 4511 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, reg_enable_type)); 4512 break; 4513 case TEMOD_CREDIT_PCS_GEN_COUNT: /* (cntl & 0x00400000) */ 4514 /* write to pcs_creditgencnt */ 4515 TX_X4_PCS_CREDGENCNTr_PCS_CREDITGENCNTf_SET(reg_pcs_creditgen, userCredit) ; 4516 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_PCS_CREDGENCNTr(pc, reg_pcs_creditgen)); 4517 /*Set the override enable*/ 4518 SC_X4_FLD_OVRR_EN1_TYPEr_PCS_CREDITGENCNT_OENf_SET(reg_enable_type, 1); 4519 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, reg_enable_type)); 4520 break; 4521 case TEMOD_CREDIT_EN: /* (cntl & 0x00800000) */ 4522 /* write to pcs_crden */ 4523 TX_X4_PCS_CLKCNT0r_PCS_CREDITENABLEf_SET(reg_pcs_clk_cnt, userCredit); 4524 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_PCS_CLKCNT0r(pc, reg_pcs_clk_cnt)); 4525 /*Set the override enable*/ 4526 SC_X4_FLD_OVRR_EN1_TYPEr_PCS_CREDITENABLE_OENf_SET(reg_enable_type, 1); 4527 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, reg_enable_type)); 4528 break; 4529 case TEMOD_CREDIT_PCS_REPCNT: /* (cntl & 0x01000000) */ 4530 /* write to pcs_repcnt */ 4531 TX_X4_PCS_CLKCNT0r_REPLICATION_CNTf_SET(reg_pcs_clk_cnt, userCredit); 4532 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_PCS_CLKCNT0r(pc, reg_pcs_clk_cnt)); 4533 /*Set the override enable*/ 4534 SC_X4_FLD_OVRR_EN1_TYPEr_REPLICATION_CNT_OENf_SET(reg_enable_type, 1); 4535 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, reg_enable_type)); 4536 break; 4537 case TEMOD_CREDIT_SGMII_SPD: /* (cntl & 0x02000000) */ 4538 /* write to sgmii */ 4539 TX_X4_CRED0r_SGMII_SPD_SWITCHf_SET(reg_credit0, userCredit); 4540 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_CRED0r(pc, reg_credit0)); 4541 /*Set the override enable*/ 4542 SC_X4_FLD_OVRR_EN1_TYPEr_SGMII_SPD_SWITCH_OENf_SET(reg_enable_type, 1); 4543 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN1_TYPEr(pc, reg_enable_type)); 4544 break; 4545 default: 4546 return PHYMOD_E_FAIL; 4547 break; 4548 } 4549 return PHYMOD_E_NONE; 4550 } /* CREDIT_SET */ 4551 4552 /** 4553 @brief Get the Override settings for credits. 4554 @param pc handle to current TSCE context (#PHYMOD_ST) 4555 @param credit_type type of credit to override #credit_type_t 4556 @param userCredit_en handle to return credit info to calling function 4557 @param userCredit User override value 4558 @returns The value PHYMOD_E_NONE upon successful completion 4559 @details Get the override credit config. Credit override get mechanism is a seperate function. However it is similar 4560 to other override get mechanisms. 4561 */ 4562 int temod_credit_override_get(PHYMOD_ST* pc, credit_type_t credit_type, uint16_t *userCredit_en, uint16_t *userCredit) 4563 { 4564 SC_X4_FLD_OVRR_EN1_TYPEr_t reg_enable_type; 4565 TX_X4_CRED0r_t reg_credit0; 4566 TX_X4_CRED1r_t reg_credit1; 4567 TX_X4_LOOPCNTr_t reg_loopcnt; 4568 TX_X4_MAC_CREDGENCNTr_t reg_maccreditgen; 4569 TX_X4_PCS_CLKCNT0r_t reg_pcs_clk_cnt; 4570 TX_X4_PCS_CREDGENCNTr_t reg_pcs_creditgen; 4571 4572 TEMOD_DBG_IN_FUNC_INFO(pc); 4573 SC_X4_FLD_OVRR_EN1_TYPEr_CLR(reg_enable_type); 4574 TX_X4_CRED0r_CLR(reg_credit0); 4575 TX_X4_CRED1r_CLR(reg_credit1); 4576 TX_X4_LOOPCNTr_CLR(reg_loopcnt); 4577 TX_X4_MAC_CREDGENCNTr_CLR(reg_maccreditgen); 4578 TX_X4_PCS_CLKCNT0r_CLR(reg_pcs_clk_cnt); 4579 TX_X4_PCS_CREDGENCNTr_CLR(reg_pcs_creditgen); 4580 4581 switch ( credit_type ) { 4582 case TEMOD_CREDIT_RESET: 4583 /* reset credits */ 4584 break; 4585 case TEMOD_CREDIT_TABLE: 4586 /* get info. from table and apply it to all credit regs. */ 4587 break; 4588 case TEMOD_CREDIT_CLOCK_COUNT_0: 4589 /* write to clockcnt0 */ 4590 PHYMOD_IF_ERR_RETURN(READ_TX_X4_CRED0r(pc, ®_credit0)); 4591 *userCredit = TX_X4_CRED0r_CLOCKCNT0f_GET(reg_credit0); 4592 /*Set the override enable*/ 4593 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FLD_OVRR_EN1_TYPEr(pc, ®_enable_type)); 4594 *userCredit_en = SC_X4_FLD_OVRR_EN1_TYPEr_CLOCKCNT0_OENf_GET(reg_enable_type); 4595 break; 4596 case TEMOD_CREDIT_CLOCK_COUNT_1: /* (cntl & 0x00020000) */ 4597 /* write to clockcnt1 */ 4598 PHYMOD_IF_ERR_RETURN(READ_TX_X4_CRED1r(pc, ®_credit1)); 4599 *userCredit = TX_X4_CRED1r_CLOCKCNT1f_GET(reg_credit1); 4600 /*Set the override enable*/ 4601 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FLD_OVRR_EN1_TYPEr(pc, ®_enable_type)); 4602 *userCredit_en = SC_X4_FLD_OVRR_EN1_TYPEr_CLOCKCNT1_OENf_GET(reg_enable_type); 4603 break; 4604 case TEMOD_CREDIT_LOOP_COUNT_0: 4605 /* write to loopcnt0 */ 4606 PHYMOD_IF_ERR_RETURN(READ_TX_X4_LOOPCNTr(pc, ®_loopcnt)); 4607 *userCredit = TX_X4_LOOPCNTr_LOOPCNT0f_GET(reg_loopcnt); 4608 /*Set the override enable*/ 4609 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FLD_OVRR_EN1_TYPEr(pc, ®_enable_type)); 4610 *userCredit_en = SC_X4_FLD_OVRR_EN1_TYPEr_LOOPCNT0_OENf_GET(reg_enable_type); 4611 break; 4612 case TEMOD_CREDIT_LOOP_COUNT_1: /* (cntl & 0x00080000) */ 4613 /* write to pcs_clockcnt0 */ 4614 PHYMOD_IF_ERR_RETURN(READ_TX_X4_LOOPCNTr(pc, ®_loopcnt)); 4615 *userCredit = TX_X4_LOOPCNTr_LOOPCNT1f_GET(reg_loopcnt); 4616 /*Set the override enable*/ 4617 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FLD_OVRR_EN1_TYPEr(pc, ®_enable_type)); 4618 *userCredit_en = SC_X4_FLD_OVRR_EN1_TYPEr_LOOPCNT1_OENf_GET(reg_enable_type); 4619 break; 4620 case TEMOD_CREDIT_MAC: /* (cntl & 0x00100000) */ 4621 /* write to mac_creditgencnt */ 4622 PHYMOD_IF_ERR_RETURN(READ_TX_X4_MAC_CREDGENCNTr(pc, ®_maccreditgen)); 4623 *userCredit = TX_X4_MAC_CREDGENCNTr_MAC_CREDITGENCNTf_GET(reg_maccreditgen); 4624 /*Set the override enable*/ 4625 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FLD_OVRR_EN1_TYPEr(pc, ®_enable_type)); 4626 *userCredit_en = SC_X4_FLD_OVRR_EN1_TYPEr_MAC_CREDITGENCNT_OENf_GET(reg_enable_type); 4627 break; 4628 case TEMOD_CREDIT_PCS_CLOCK_COUNT_0: /* (cntl & 0x00200000) */ 4629 /* write to pcs_clockcnt0 */ 4630 PHYMOD_IF_ERR_RETURN(READ_TX_X4_PCS_CLKCNT0r(pc, ®_pcs_clk_cnt)); 4631 *userCredit = TX_X4_PCS_CLKCNT0r_PCS_CLOCKCNT0f_GET(reg_pcs_clk_cnt); 4632 /*Set the override enable*/ 4633 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FLD_OVRR_EN1_TYPEr(pc, ®_enable_type)); 4634 *userCredit_en = SC_X4_FLD_OVRR_EN1_TYPEr_PCS_CLOCKCNT0_OENf_GET(reg_enable_type); 4635 break; 4636 case TEMOD_CREDIT_PCS_GEN_COUNT: /* (cntl & 0x00400000) */ 4637 /* write to pcs_creditgencnt */ 4638 PHYMOD_IF_ERR_RETURN(READ_TX_X4_PCS_CREDGENCNTr(pc, ®_pcs_creditgen)); 4639 *userCredit = TX_X4_PCS_CREDGENCNTr_PCS_CREDITGENCNTf_GET(reg_pcs_creditgen) ; 4640 /*Set the override enable*/ 4641 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FLD_OVRR_EN1_TYPEr(pc, ®_enable_type)); 4642 *userCredit_en = SC_X4_FLD_OVRR_EN1_TYPEr_PCS_CREDITGENCNT_OENf_GET(reg_enable_type); 4643 break; 4644 case TEMOD_CREDIT_EN: /* (cntl & 0x00800000) */ 4645 /* write to pcs_crden */ 4646 PHYMOD_IF_ERR_RETURN(READ_TX_X4_PCS_CLKCNT0r(pc, ®_pcs_clk_cnt)); 4647 *userCredit = TX_X4_PCS_CLKCNT0r_PCS_CREDITENABLEf_GET(reg_pcs_clk_cnt); 4648 /*Set the override enable*/ 4649 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FLD_OVRR_EN1_TYPEr(pc, ®_enable_type)); 4650 *userCredit_en = SC_X4_FLD_OVRR_EN1_TYPEr_PCS_CREDITENABLE_OENf_GET(reg_enable_type); 4651 break; 4652 case TEMOD_CREDIT_PCS_REPCNT: /* (cntl & 0x01000000) */ 4653 /* write to pcs_repcnt */ 4654 PHYMOD_IF_ERR_RETURN(READ_TX_X4_PCS_CLKCNT0r(pc, ®_pcs_clk_cnt)); 4655 *userCredit = TX_X4_PCS_CLKCNT0r_REPLICATION_CNTf_GET(reg_pcs_clk_cnt); 4656 /*Set the override enable*/ 4657 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FLD_OVRR_EN1_TYPEr(pc, ®_enable_type)); 4658 *userCredit_en = SC_X4_FLD_OVRR_EN1_TYPEr_REPLICATION_CNT_OENf_GET(reg_enable_type); 4659 break; 4660 case TEMOD_CREDIT_SGMII_SPD: /* (cntl & 0x02000000) */ 4661 /* write to sgmii */ 4662 PHYMOD_IF_ERR_RETURN(READ_TX_X4_CRED0r(pc, ®_credit0)); 4663 *userCredit = TX_X4_CRED0r_SGMII_SPD_SWITCHf_GET(reg_credit0); 4664 /*Set the override enable*/ 4665 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FLD_OVRR_EN1_TYPEr(pc, ®_enable_type)); 4666 *userCredit_en = SC_X4_FLD_OVRR_EN1_TYPEr_SGMII_SPD_SWITCH_OENf_GET(reg_enable_type); 4667 break; 4668 default: 4669 return PHYMOD_E_FAIL; 4670 break; 4671 } 4672 return PHYMOD_E_NONE; 4673 } /* CREDIT_GET */ 4674 4675 int temod_clause72_control(PHYMOD_ST* pc, uint32_t cl_72_en) /* CLAUSE_72_CONTROL */ 4676 { 4677 CL72_TXBASE_R_PMD_CTLr_t reg_cl72_ctrl ; 4678 phymod_access_t pa_copy; 4679 int start_lane = 0, num_lane = 0; 4680 int i = 0; 4681 uint32_t enable=0; 4682 int speed_id; 4683 4684 4685 TEMOD_DBG_IN_FUNC_INFO(pc); 4686 CL72_TXBASE_R_PMD_CTLr_CLR(reg_cl72_ctrl) ; 4687 4688 4689 PHYMOD_MEMCPY(&pa_copy, pc, sizeof(pa_copy)); 4690 PHYMOD_IF_ERR_RETURN 4691 (phymod_util_lane_config_get(pc, &start_lane, &num_lane)); 4692 pa_copy.lane_mask = 0x1 << start_lane; 4693 4694 for (i = (num_lane-1); i >= 0; i--) { 4695 pa_copy.lane_mask = 0x1 << (i + start_lane); 4696 if (cl_72_en & TEMOD_CL72_CONTROL_MASK ) { 4697 CL72_TXBASE_R_PMD_CTLr_CL72_IEEE_TRAINING_ENABLEf_SET(reg_cl72_ctrl, 1) ; 4698 PHYMOD_IF_ERR_RETURN (MODIFY_CL72_TXBASE_R_PMD_CTLr(&pa_copy, reg_cl72_ctrl)); 4699 CL72_TXBASE_R_PMD_CTLr_CL72_IEEE_RESTART_TRAININGf_SET(reg_cl72_ctrl, 1) ; 4700 PHYMOD_IF_ERR_RETURN (MODIFY_CL72_TXBASE_R_PMD_CTLr(&pa_copy, reg_cl72_ctrl)); 4701 } else { 4702 CL72_TXBASE_R_PMD_CTLr_CL72_IEEE_TRAINING_ENABLEf_SET(reg_cl72_ctrl, 0) ; 4703 PHYMOD_IF_ERR_RETURN (MODIFY_CL72_TXBASE_R_PMD_CTLr(&pa_copy, reg_cl72_ctrl)); 4704 CL72_TXBASE_R_PMD_CTLr_CL72_IEEE_RESTART_TRAININGf_SET(reg_cl72_ctrl, 0) ; 4705 PHYMOD_IF_ERR_RETURN (MODIFY_CL72_TXBASE_R_PMD_CTLr(&pa_copy, reg_cl72_ctrl)); 4706 } 4707 } 4708 4709 pa_copy.lane_mask = 0x1 << start_lane; 4710 if(!(cl_72_en & TEMOD_CL72_CONTROL_NO_TRIGER)) { 4711 PHYMOD_IF_ERR_RETURN(temod_speed_id_get(pc, &speed_id)); 4712 temod_disable_get(&pa_copy,&enable); 4713 /*If it`s 100G,always trigger speed change*/ 4714 if((enable == 0x1) || (speed_id >= 0x24 && speed_id <= 0x27)) { 4715 PHYMOD_IF_ERR_RETURN (temod_trigger_speed_change(&pa_copy)); 4716 } 4717 } 4718 4719 return PHYMOD_E_NONE; 4720 } 4721 4722 4723 4724 4725 4726 4727 #ifdef _DV_TB_ 4728 /** 4729 @brief Control per lane clause 72 auto tuning function (training patterns) 4730 @param pc handle to current TSCE context (#PHYMOD_ST) 4731 @param cl_72_type #cl72_type_t 4732 @returns The value PHYMOD_E_NONE upon successful completion 4733 @details 4734 This function enables/disables clause-72 auto-tuning per lane. It is used 4735 in 40G_KR4, 40G_CR4, 10G_KR modes etc. 4736 Lane is selected via #PHYMOD_ST::lane_select. 4737 This Function is controlled by cl_72_type as follows. 4738 4739 \li 0Xxxxxxxx3 (b11): Enable CL72 hardware block 4740 \li 0Xxxxxxxx2 (b01): Disable CL72 hardware block 4741 \li 0Xxxxxxxx0 (b00): no changed. 4742 \li 0Xxxxxxx3- (b011----): Forced enable CL72 under AN. 4743 \li 0Xxxxxxx7- (b111----): Forced disable CL72 under AN. 4744 \li 0Xxxxxxx1- (b001----): Default CL72 under AN. 4745 \li 0Xxxxxxx0- (b000----): no changed 4746 \li 0Xxxxxx100 : read back CL72 HW en bit and put in accData. 4747 4748 */ 4749 int temod_clause72_control(PHYMOD_ST* pc, cl72_type_t cl_72_type) /* CLAUSE_72_CONTROL */ 4750 { 4751 CL72_TXBASE_R_PMD_CTLr_t reg_cl72_ctrl ; 4752 CL72_RXMISC1_CTLr_t reg_misc1_ctrl ; 4753 4754 TEMOD_DBG_IN_FUNC_INFO(pc); 4755 CL72_TXBASE_R_PMD_CTLr_CLR(reg_cl72_ctrl) ; 4756 4757 CL72_RXMISC1_CTLr_CLR(reg_misc1_ctrl) ; 4758 4759 switch (cl_72_type) { 4760 case TSCMOD_CL72_HW_ENABLE: 4761 CL72_TXBASE_R_PMD_CTLr_CL72_IEEE_TRAINING_ENABLEf_SET(reg_cl72_ctrl, 1) ; 4762 PHYMOD_IF_ERR_RETURN (MODIFY_CL72_TXBASE_R_PMD_CTLr(pc, reg_cl72_ctrl)); 4763 break; 4764 case TSCMOD_CL72_HW_DISABLE: 4765 CL72_TXBASE_R_PMD_CTLr_CL72_IEEE_TRAINING_ENABLEf_SET(reg_cl72_ctrl, 0) ; 4766 PHYMOD_IF_ERR_RETURN (MODIFY_CL72_TXBASE_R_PMD_CTLr(pc, reg_cl72_ctrl)); 4767 break; 4768 case TSCMOD_CL72_HW_RESTART: 4769 CL72_TXBASE_R_PMD_CTLr_CL72_IEEE_RESTART_TRAININGf_SET(reg_cl72_ctrl, 1) ; 4770 PHYMOD_IF_ERR_RETURN (MODIFY_CL72_TXBASE_R_PMD_CTLr(pc, reg_cl72_ctrl)); 4771 break; 4772 case TSCMOD_CL72_HW_RESTART_STOP: 4773 CL72_TXBASE_R_PMD_CTLr_CL72_IEEE_RESTART_TRAININGf_SET(reg_cl72_ctrl, 0) ; 4774 PHYMOD_IF_ERR_RETURN (MODIFY_CL72_TXBASE_R_PMD_CTLr(pc, reg_cl72_ctrl)); 4775 break; 4776 default : 4777 break; 4778 } 4779 #ifdef _DV_TB_ 4780 /* this should be done by uC */ 4781 if (cl_72_type == TSCMOD_CL72_HW_RESTART) { 4782 CL72_TXMISC2_CTLr_t reg_misc2_ctrl ; 4783 CL72_TXMISC2_CTLr_CLR(reg_misc2_ctrl) ; 4784 4785 /* set coarse lock */ 4786 PHYMOD_IF_ERR_RETURN (READ_CL72_RXMISC1_CTLr(pc, ®_misc1_ctrl)); 4787 CL72_RXMISC1_CTLr_CL72_TR_COARSE_LOCKf_SET(reg_misc1_ctrl, 1); 4788 PHYMOD_IF_ERR_RETURN (WRITE_CL72_RXMISC1_CTLr(pc, reg_misc1_ctrl)); 4789 /* set rx_trained */ 4790 PHYMOD_IF_ERR_RETURN (READ_CL72_TXMISC2_CTLr(pc, ®_misc2_ctrl)); 4791 CL72_TXMISC2_CTLr_CL72_RX_TRAINEDf_SET(reg_misc2_ctrl, 1); 4792 PHYMOD_IF_ERR_RETURN (WRITE_CL72_TXMISC2_CTLr(pc, reg_misc2_ctrl)); 4793 } else { 4794 /* unset coarse lock */ 4795 /* unset rx_trained */ 4796 } 4797 #endif /* _DV_TB_ */ 4798 return PHYMOD_E_NONE; 4799 } /* clause72_control */ 4800 #endif /* _DV_TB_ */ 4801 4802 #ifdef _DV_TB_ 4803 4804 int temod_prbs_check(PHYMOD_ST* pc, int real_check, int *prbs_status) 4805 { 4806 TLB_RX_PRBS_CHK_LOCK_STSr_t reg_prbs_chk_lock; 4807 TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr_t reg_prbs_err_cnt_msb; 4808 TLB_RX_PRBS_CHK_ERR_CNT_LSB_STSr_t reg_prbs_err_cnt_lsb; 4809 int lock, lock_lost, err ; 4810 4811 TEMOD_DBG_IN_FUNC_INFO(pc); 4812 pc->accData = 0 ; 4813 4814 TLB_RX_PRBS_CHK_LOCK_STSr_CLR(reg_prbs_chk_lock); 4815 TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr_CLR(reg_prbs_err_cnt_msb); 4816 TLB_RX_PRBS_CHK_ERR_CNT_LSB_STSr_CLR(reg_prbs_err_cnt_lsb); 4817 4818 PHYMOD_IF_ERR_RETURN 4819 ( READ_TLB_RX_PRBS_CHK_LOCK_STSr(pc, ®_prbs_chk_lock)); 4820 PHYMOD_IF_ERR_RETURN 4821 (READ_TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr(pc, ®_prbs_err_cnt_msb)); 4822 PHYMOD_IF_ERR_RETURN 4823 (READ_TLB_RX_PRBS_CHK_ERR_CNT_LSB_STSr(pc, ®_prbs_err_cnt_lsb)); 4824 4825 lock = TLB_RX_PRBS_CHK_LOCK_STSr_PRBS_CHK_LOCKf_GET(reg_prbs_chk_lock) ? 1 : 0 ; 4826 lock_lost = TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr_PRBS_CHK_LOCK_LOST_LHf_GET(reg_prbs_err_cnt_msb) ? 1 : 0 ; 4827 err = TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr_PRBS_CHK_ERR_CNT_MSBf_GET(reg_prbs_err_cnt_msb) ; 4828 err = (err << 16) | TLB_RX_PRBS_CHK_ERR_CNT_LSB_STSr_PRBS_CHK_ERR_CNT_LSBf_GET(reg_prbs_err_cnt_lsb) ; 4829 4830 #ifdef _DV_TB_ 4831 printf("prbs_check u=%0d p=%0d ln=%0d lck=%0d lost=%0d err=%0d(H%x L%x)\n", 4832 pc->unit, pc->port, pc->this_lane, lock, lock_lost, err, reg_prbs_err_cnt_msb, reg_prbs_err_cnt_lsb); 4833 #endif 4834 4835 if (TLB_RX_PRBS_CHK_LOCK_STSr_PRBS_CHK_LOCKf_GET(reg_prbs_chk_lock)) { 4836 if (TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr_PRBS_CHK_LOCK_LOST_LHf_GET(reg_prbs_err_cnt_msb)) { 4837 /* locked now but lost before */ 4838 *prbs_status = TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr_PRBS_CHK_ERR_CNT_MSBf_GET(reg_prbs_err_cnt_msb); 4839 *prbs_status = (*prbs_status << 16) | TLB_RX_PRBS_CHK_ERR_CNT_LSB_STSr_PRBS_CHK_ERR_CNT_LSBf_GET(reg_prbs_err_cnt_lsb) | 1 ; /* locked once, so one error at least */ 4840 pc->accData = real_check ? 1 : 0 ; 4841 return PHYMOD_E_FAIL; 4842 } else { 4843 *prbs_status = TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr_PRBS_CHK_ERR_CNT_MSBf_GET(reg_prbs_err_cnt_msb) ; 4844 *prbs_status = (*prbs_status << 16)| TLB_RX_PRBS_CHK_ERR_CNT_LSB_STSr_PRBS_CHK_ERR_CNT_LSBf_GET(reg_prbs_err_cnt_lsb) ; 4845 if (err) { 4846 pc->accData = real_check ? 1 : 0 ; 4847 return PHYMOD_E_FAIL; 4848 } 4849 } 4850 } else { 4851 if(TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr_PRBS_CHK_LOCK_LOST_LHf_GET(reg_prbs_err_cnt_msb)) { 4852 *prbs_status = -2 ; /* locked before but lost now */ 4853 pc->accData = real_check ? 1 : 0 ; 4854 return PHYMOD_E_FAIL; 4855 } else { 4856 *prbs_status = -1 ; /* never locked */ 4857 pc->accData = real_check ? 1 : 0 ; 4858 return PHYMOD_E_FAIL; 4859 } 4860 } 4861 return PHYMOD_E_NONE ; 4862 } 4863 #endif /* _DV_TB_ */ 4864 4865 #ifdef _DV_TB_ 4866 4867 int temod_prbs_mode(PHYMOD_ST* pc, int port, int prbs_inv, int pattern_type, int prbs_check_mode) /* PRBS_MODE */ 4868 { 4869 TLB_TX_PRBS_GEN_CFGr_t reg_prbs_gen_cfg; 4870 TLB_RX_PRBS_CHK_CFGr_t reg_prbs_chk_cfg; 4871 /* SC_X4_BYPASSr_t reg_bypass; */ 4872 4873 /*int prbs_check_mode ; */ 4874 int prbs_sel_tx, prbs_inv_tx ; 4875 int prbs_sel_rx, prbs_inv_rx ; 4876 4877 4878 TEMOD_DBG_IN_FUNC_INFO(pc); 4879 TLB_TX_PRBS_GEN_CFGr_CLR(reg_prbs_gen_cfg); 4880 TLB_RX_PRBS_CHK_CFGr_CLR(reg_prbs_chk_cfg); 4881 4882 prbs_sel_tx = pattern_type; 4883 prbs_sel_rx = pattern_type; 4884 prbs_inv_tx = prbs_inv; 4885 prbs_inv_rx = prbs_inv; 4886 4887 TLB_TX_PRBS_GEN_CFGr_PRBS_GEN_MODE_SELf_SET(reg_prbs_gen_cfg, prbs_sel_tx); 4888 TLB_TX_PRBS_GEN_CFGr_PRBS_GEN_INVf_SET(reg_prbs_gen_cfg, prbs_inv_tx); 4889 4890 PHYMOD_IF_ERR_RETURN (MODIFY_TLB_TX_PRBS_GEN_CFGr(pc, reg_prbs_gen_cfg)); 4891 4892 TLB_RX_PRBS_CHK_CFGr_PRBS_CHK_MODEf_SET(reg_prbs_chk_cfg, prbs_check_mode); 4893 TLB_RX_PRBS_CHK_CFGr_PRBS_CHK_MODE_SELf_SET(reg_prbs_chk_cfg, prbs_sel_rx); 4894 TLB_RX_PRBS_CHK_CFGr_PRBS_CHK_INVf_SET(reg_prbs_chk_cfg, prbs_inv_rx); 4895 4896 PHYMOD_IF_ERR_RETURN (MODIFY_TLB_RX_PRBS_CHK_CFGr(pc, reg_prbs_chk_cfg)); 4897 4898 return PHYMOD_E_NONE; 4899 4900 } /* PRBS_MODE */ 4901 #endif /* _DV_TB_ */ 4902 4903 #ifdef _DV_TB_ 4904 4905 int temod_prbs_control(PHYMOD_ST* pc, int prbs_enable) /* PRBS_CONTROL */ 4906 { 4907 TLB_TX_PRBS_GEN_CFGr_t reg_prbs_gen_cfg; 4908 TLB_RX_PRBS_CHK_CFGr_t reg_prbs_chk_cfg; 4909 int prbs_rx_en, prbs_tx_en ; 4910 4911 TEMOD_DBG_IN_FUNC_INFO(pc); 4912 TLB_TX_PRBS_GEN_CFGr_CLR(reg_prbs_gen_cfg); 4913 TLB_RX_PRBS_CHK_CFGr_CLR(reg_prbs_chk_cfg); 4914 4915 prbs_tx_en = prbs_enable; 4916 prbs_rx_en = prbs_enable; 4917 4918 TLB_TX_PRBS_GEN_CFGr_PRBS_GEN_ENf_SET(reg_prbs_gen_cfg, prbs_tx_en); 4919 PHYMOD_IF_ERR_RETURN (MODIFY_TLB_TX_PRBS_GEN_CFGr(pc, reg_prbs_gen_cfg)); 4920 4921 TLB_RX_PRBS_CHK_CFGr_PRBS_CHK_ENf_SET(reg_prbs_chk_cfg, prbs_rx_en); 4922 PHYMOD_IF_ERR_RETURN (MODIFY_TLB_RX_PRBS_CHK_CFGr(pc, reg_prbs_chk_cfg)); 4923 4924 return PHYMOD_E_NONE; 4925 4926 } /* PRBS_CONTROL */ 4927 #endif /* _DV_TB_ */ 4928 4929 #ifdef _DV_TB_ 4930 /** 4931 @brief Sets CJPAT/CRPAT parameters for a particular port 4932 @param pc handle to current TSCE context (#PHYMOD_ST) 4933 @param spd_intf speed type #temod_spd_intfc_type 4934 @param port port num 4935 @param pattern_type type of CJPat 4936 @param pkt_number number of packets 4937 @param pkt_size size of packets 4938 @param ipg_size IPG between packets 4939 @returns The value PHYMOD_E_NONE upon successful completion 4940 4941 This function enables either a CJPAT or CRPAT for a particular port. 4942 The speed mode of the lane must be chosen from the enumerated type 4943 #temod_spd_intfc_type and set in the spd_intf field. 4944 To enable CJPAT, TBD 4945 To enable CRPAT, TBD 4946 This function is used along with temod_cjpat_crpat_check(). 4947 */ 4948 4949 int temod_cjpat_crpat_mode_set(PHYMOD_ST* pc, 4950 temod_spd_intfc_type spd_intf, 4951 int port, 4952 int pattern_type, 4953 int pkt_number, 4954 int pkt_size, 4955 int ipg_size) /* CJPAT_CRPAT_MODE_SET */ 4956 { 4957 int number_pkt, crc_check, intf_type, rx_port_sel, tx_port_sel, pkt_or_prtp ; 4958 int pkt_size_int, ipg_size_int, payload_type, prtp_data_pattern_sel, rx_prtp_en ; 4959 int tx_prtp_en; 4960 uint16_t data16 ; 4961 4962 int rand_num; 4963 4964 PKTGEN_CTL1r_t reg_pktctrl1; 4965 PKTGEN_CTL2r_t reg_pktctrl2; 4966 PKTGEN_PRTPCTLr_t reg_prtpctrl; 4967 PKTGEN_PCS_SEEDA0r_t reg_seeda0; 4968 PKTGEN_PCS_SEEDA1r_t reg_seeda1; 4969 PKTGEN_PCS_SEEDA2r_t reg_seeda2; 4970 PKTGEN_PCS_SEEDA3r_t reg_seeda3; 4971 PKTGEN_PCS_SEEDB0r_t reg_seedb0; 4972 PKTGEN_PCS_SEEDB1r_t reg_seedb1; 4973 PKTGEN_PCS_SEEDB2r_t reg_seedb2; 4974 PKTGEN_PCS_SEEDB3r_t reg_seedb3; 4975 PKTGEN_PAYLOADBYTESr_t reg_payload_b; 4976 4977 TEMOD_DBG_IN_FUNC_INFO(pc); 4978 PKTGEN_CTL1r_CLR(reg_pktctrl1); 4979 PKTGEN_CTL2r_CLR(reg_pktctrl2); 4980 PKTGEN_PRTPCTLr_CLR(reg_prtpctrl); 4981 PKTGEN_PCS_SEEDA0r_CLR(reg_seeda0); 4982 PKTGEN_PCS_SEEDA1r_CLR(reg_seeda1); 4983 PKTGEN_PCS_SEEDA2r_CLR(reg_seeda2); 4984 PKTGEN_PCS_SEEDA3r_CLR(reg_seeda3); 4985 PKTGEN_PCS_SEEDB0r_CLR(reg_seedb0); 4986 PKTGEN_PCS_SEEDB1r_CLR(reg_seedb1); 4987 PKTGEN_PCS_SEEDB2r_CLR(reg_seedb2); 4988 PKTGEN_PCS_SEEDB3r_CLR(reg_seedb3); 4989 PKTGEN_PAYLOADBYTESr_CLR(reg_payload_b); 4990 4991 number_pkt = pkt_number ; /* 2: unlimited, 0: idles, 1: single pkt */ 4992 crc_check = 1 ; 4993 rx_port_sel= port ; 4994 tx_port_sel= port ; 4995 pkt_or_prtp = 0 ; /* 0: pakcet generator; 1: PRTP(pseudo random test pattern) */ 4996 rx_prtp_en = 0; 4997 tx_prtp_en = 0; 4998 if ((pattern_type == 0x9) | (pattern_type == 0xA)) { 4999 pkt_or_prtp = 1; 5000 rx_prtp_en = 1; 5001 tx_prtp_en = 1; 5002 } 5003 5004 if (pattern_type == 0xA) { 5005 prtp_data_pattern_sel = 1; 5006 } else { 5007 prtp_data_pattern_sel = 0; 5008 } 5009 5010 /* pkt_size_int = pkt_size ; */ 5011 pkt_size_int = 1; 5012 ipg_size_int = 8 ; 5013 /* ipg_size_int = ipg_size ; */ 5014 5015 /* need to check the interface type */ 5016 if ((pattern_type == 0x9) | (pattern_type == 0xA)) { 5017 payload_type = 0; 5018 } else { 5019 payload_type = pattern_type; 5020 } 5021 5022 5023 /* intf_type 0: XLGMII/XGMII; 1: MIII/GMII */ 5024 5025 intf_type = ((spd_intf == TEMOD_SPD_10_X1_SGMII) | 5026 (spd_intf == TEMOD_SPD_100_X1_SGMII) | 5027 (spd_intf == TEMOD_SPD_1000_X1_SGMII) | 5028 (spd_intf == TEMOD_SPD_10_SGMII) | 5029 (spd_intf == TEMOD_SPD_100_SGMII) | 5030 (spd_intf == TEMOD_SPD_1000_SGMII) | 5031 (spd_intf == TEMOD_SPD_2500) | 5032 (spd_intf == TEMOD_SPD_2500_X1)) ? 1 : 0; 5033 5034 /* if payload type is Repeat 2 Bytes in 0x9040*/ 5035 5036 if (payload_type == 0) { 5037 data16 = 0x2323; 5038 PKTGEN_PAYLOADBYTESr_BYTE1f_SET(reg_payload_b, ((data16 >> 8) & 0xff)); 5039 PKTGEN_PAYLOADBYTESr_BYTE0f_SET(reg_payload_b, (data16 & 0xff)); 5040 WRITE_PKTGEN_PAYLOADBYTESr(pc, reg_payload_b); 5041 } 5042 5043 /* 0x9030 */ 5044 PKTGEN_CTL1r_PKT_OR_PRTPf_SET(reg_pktctrl1, pkt_or_prtp); 5045 PKTGEN_CTL1r_TX_TEST_PORT_SELf_SET(reg_pktctrl1, tx_port_sel); 5046 PKTGEN_CTL1r_RX_PORT_SELf_SET(reg_pktctrl1, rx_port_sel); 5047 PKTGEN_CTL1r_RX_PKT_CHECK_ENf_SET(reg_pktctrl1, crc_check); 5048 PKTGEN_CTL1r_RX_MSBUS_TYPEf_SET(reg_pktctrl1, intf_type); 5049 PKTGEN_CTL1r_NUMBER_PKTf_SET(reg_pktctrl1, number_pkt); 5050 PKTGEN_CTL1r_TX_PRTP_ENf_SET(reg_pktctrl1, tx_prtp_en); 5051 PKTGEN_CTL1r_PRTP_DATA_PATTERN_SELf_SET(reg_pktctrl1, prtp_data_pattern_sel); 5052 5053 PHYMOD_IF_ERR_RETURN 5054 (WRITE_PKTGEN_CTL1r(pc, reg_pktctrl1)); 5055 5056 /* 0x9031 */ 5057 PKTGEN_CTL2r_IPG_SIZEf_SET(reg_pktctrl2, ipg_size_int); 5058 PKTGEN_CTL2r_PKT_SIZEf_SET(reg_pktctrl2, pkt_size_int); 5059 PKTGEN_CTL2r_PAYLOAD_TYPEf_SET(reg_pktctrl2, payload_type); 5060 PKTGEN_CTL2r_TX_MSBUS_TYPEf_SET(reg_pktctrl2, intf_type); 5061 5062 PHYMOD_IF_ERR_RETURN 5063 (WRITE_PKTGEN_CTL2r(pc, reg_pktctrl2)); 5064 5065 /* 0x9032 */ 5066 PKTGEN_PRTPCTLr_RX_PRTP_ENf_SET(reg_prtpctrl,rx_prtp_en); 5067 PHYMOD_IF_ERR_RETURN 5068 (WRITE_PKTGEN_PRTPCTLr(pc, reg_prtpctrl)); 5069 5070 /* program seeds if necessary */ 5071 rand_num = 1234; /* assign random number */ 5072 #ifdef _DV_TB_ 5073 rand_num = rand (); 5074 #endif /* _DV_TB_ */ 5075 5076 data16 = rand_num & 0xFFFF; 5077 if ((pattern_type == 0x9) | (pattern_type == 0xA)) { 5078 PKTGEN_PCS_SEEDA0r_SEEDA0f_SET(reg_seeda0, data16); 5079 PHYMOD_IF_ERR_RETURN 5080 (WRITE_PKTGEN_PCS_SEEDA0r(pc, reg_seeda0)); 5081 data16 = data16 + 1; 5082 PKTGEN_PCS_SEEDA1r_SEEDA1f_SET(reg_seeda1, data16); 5083 PHYMOD_IF_ERR_RETURN 5084 (WRITE_PKTGEN_PCS_SEEDA1r(pc, reg_seeda1)); 5085 data16 = data16 + 1; 5086 PKTGEN_PCS_SEEDA2r_SEEDA2f_SET(reg_seeda2, data16); 5087 PHYMOD_IF_ERR_RETURN 5088 (WRITE_PKTGEN_PCS_SEEDA2r( pc, reg_seeda2)); 5089 data16 = data16 + 1; 5090 PKTGEN_PCS_SEEDA3r_SEEDA3f_SET(reg_seeda3, data16); 5091 PHYMOD_IF_ERR_RETURN 5092 (WRITE_PKTGEN_PCS_SEEDA3r(pc, reg_seeda3)); 5093 data16 = data16 + 1; 5094 PKTGEN_PCS_SEEDB0r_SEEDB0f_SET(reg_seedb0, data16); 5095 PHYMOD_IF_ERR_RETURN 5096 (WRITE_PKTGEN_PCS_SEEDB0r( pc, reg_seedb0)); 5097 data16 = data16 + 1; 5098 PKTGEN_PCS_SEEDB1r_SEEDB1f_SET(reg_seedb1, data16); 5099 PHYMOD_IF_ERR_RETURN 5100 (WRITE_PKTGEN_PCS_SEEDB1r( pc, reg_seedb1)); 5101 data16 = data16 + 1; 5102 PKTGEN_PCS_SEEDB2r_SEEDB2f_SET(reg_seedb2, data16); 5103 PHYMOD_IF_ERR_RETURN 5104 (WRITE_PKTGEN_PCS_SEEDB2r(pc, reg_seedb2)); 5105 data16 = data16 + 1; 5106 PKTGEN_PCS_SEEDB3r_SEEDB3f_SET(reg_seedb3, data16); 5107 PHYMOD_IF_ERR_RETURN 5108 (WRITE_PKTGEN_PCS_SEEDB3r( pc, reg_seedb3)); 5109 } 5110 return PHYMOD_E_NONE; 5111 } /* int temod_cjpat_crpat_mode_set */ 5112 5113 /** 5114 @brief Checks CJPAT/CRPAT parameters for a particular port 5115 @param pc handle to current TSCE context (#PHYMOD_ST) 5116 @returns The value PHYMOD_E_NONE upon successful completion 5117 5118 This function checks for CJPAT or CRPAT for a particular port. The speed mode 5119 of the lane is provided as enumerated type #temod_spd_intfc_type. CJPAT/CRPAT 5120 must first enabled using #temod_cjpat_crpat_control(). The duration of packet 5121 transmission is controlled externally and is the time duration between the two 5122 function calls above. 5123 5124 This function compares the CJPAT/CRPAT TX and RX counters and prints the 5125 results. Currently only packet count is supported. 5126 5127 This function reads the following registers: 5128 5129 \li PATGEN1_TXPKTCNT_U (0xC040) Upper 16b of count of Transmitted packets 5130 \li PATGEN1_TXPKTCNT_L (0xC041) Lower 16b of count of Transmitted packets 5131 \li PATGEN1_RXPKTCNT_U (0xC042) Upper 16b of count of Recieved packets 5132 \li PATGEN1_RXPKTCNT_L (0xC043) Lower 16b of count of Recieved packets 5133 \li PKTGEN0_CRCERRORCOUNT (0x9033) CRC error conunt 5134 5135 TBD: Make it return status/tx_cnt or something? 5136 */ 5137 5138 int temod_cjpat_crpat_check(PHYMOD_ST* pc) /* CJPAT_CRPAT_CHECK */ 5139 { 5140 uint32_t tx_cnt, rx_cnt ; 5141 5142 PATGEN_TXPKTCNT_Ur_t reg_tx_u; 5143 PATGEN_TXPKTCNT_Lr_t reg_tx_l; 5144 PATGEN_RXPKTCNT_Ur_t reg_rx_u; 5145 PATGEN_RXPKTCNT_Lr_t reg_rx_l; 5146 PKTGEN_CRCERRCNTr_t reg_crc_cnt; 5147 5148 TEMOD_DBG_IN_FUNC_INFO(pc); 5149 PATGEN_TXPKTCNT_Ur_CLR(reg_tx_u); 5150 READ_PATGEN_TXPKTCNT_Ur(pc, ®_tx_u); 5151 PATGEN_TXPKTCNT_Lr_CLR(reg_tx_l); 5152 READ_PATGEN_TXPKTCNT_Lr(pc, ®_tx_l); 5153 PATGEN_RXPKTCNT_Ur_CLR(reg_rx_u); 5154 READ_PATGEN_RXPKTCNT_Ur(pc, ®_rx_u); 5155 PATGEN_RXPKTCNT_Lr_CLR(reg_rx_l); 5156 READ_PATGEN_RXPKTCNT_Lr(pc, ®_rx_l); 5157 PKTGEN_CRCERRCNTr_CLR(reg_crc_cnt); 5158 READ_PKTGEN_CRCERRCNTr(pc, ®_crc_cnt); 5159 5160 tx_cnt = PATGEN_TXPKTCNT_Ur_GET(reg_tx_u) <<16; 5161 tx_cnt |= PATGEN_TXPKTCNT_Lr_GET(reg_tx_l); 5162 5163 rx_cnt = PATGEN_RXPKTCNT_Ur_GET(reg_rx_u) <<16; 5164 rx_cnt |= PATGEN_RXPKTCNT_Lr_GET(reg_rx_l); 5165 5166 #ifdef _DV_TB_ 5167 pc->accData = 1 ; 5168 #endif /* _DV_TB_ */ 5169 if( (tx_cnt != rx_cnt) ||(tx_cnt==0) ) { 5170 #ifdef _DV_TB_ 5171 5172 PHYMOD_DEBUG_ERROR(("%-22s ERROR: u=%0d p=%0d tx_cnt=%0d rx_cnt=%0d mismatch\n", __func__, pc->unit, pc->port, tx_cnt, rx_cnt)); 5173 pc->accData = 0; 5174 #endif /* _DV_TB_ */ 5175 return PHYMOD_E_FAIL; 5176 } 5177 5178 if(reg_crc_cnt.pktgen_crcerrcnt[0]) { 5179 #ifdef _DV_TB_ 5180 5181 PHYMOD_DEBUG_ERROR(("%-22s ERROR: u=%0d p=%0d crc error=%0d\n", __func__, pc->unit, pc->port, reg_crc_cnt.pktgen_crcerrcnt[0])); 5182 pc->accData = 0; 5183 #endif /* _DV_TB_ */ 5184 5185 return PHYMOD_E_FAIL; 5186 } 5187 return PHYMOD_E_NONE; 5188 } 5189 5190 5191 int temod_cjpat_crpat_control(PHYMOD_ST* pc, int enable) /* CJPAT_CRPAT_CONTROL */ 5192 { 5193 PKTGEN_CTL2r_t reg; 5194 5195 TEMOD_DBG_IN_FUNC_INFO(pc); 5196 PKTGEN_CTL2r_CLR(reg); 5197 /* 0x9031 */ 5198 PHYMOD_IF_ERR_RETURN 5199 (READ_PKTGEN_CTL2r(pc, ®)); 5200 5201 if(enable) { 5202 PKTGEN_CTL2r_PKTGEN_ENf_SET(reg, 1); 5203 } else { 5204 PKTGEN_CTL2r_PKTGEN_ENf_SET(reg, 0); 5205 } 5206 PHYMOD_IF_ERR_RETURN 5207 (WRITE_PKTGEN_CTL2r(pc, reg)); 5208 5209 return PHYMOD_E_NONE; 5210 } 5211 #endif /* _DV_TB_ */ 5212 5213 5214 int temod_pcs_lane_swap_get ( PHYMOD_ST *pc, uint32_t *tx_rx_swap) 5215 { 5216 unsigned int pcs_map; 5217 MAIN0_LN_SWPr_t reg; 5218 TEMOD_DBG_IN_FUNC_INFO(pc); 5219 5220 MAIN0_LN_SWPr_CLR(reg); 5221 5222 PHYMOD_IF_ERR_RETURN 5223 (READ_MAIN0_LN_SWPr(pc, ®)) ; 5224 5225 pcs_map = MAIN0_LN_SWPr_GET(reg); 5226 5227 *tx_rx_swap = (((pcs_map >> 0) & 0x3) << 0) | 5228 (((pcs_map >> 2) & 0x3) << 4) | 5229 (((pcs_map >> 4) & 0x3) << 8) | 5230 (((pcs_map >> 6) & 0x3) << 12) ; 5231 5232 return PHYMOD_E_NONE ; 5233 } 5234 5235 5236 5237 int temod_pcs_lane_swap(PHYMOD_ST *pc, int lane_map) 5238 { 5239 unsigned int pcs_map; 5240 MAIN0_LN_SWPr_t reg; 5241 TEMOD_DBG_IN_FUNC_INFO(pc); 5242 5243 MAIN0_LN_SWPr_CLR(reg); 5244 5245 pcs_map = (((lane_map >> 0) & 0x3) << 0) | 5246 (((lane_map >> 4) & 0x3) << 2) | 5247 (((lane_map >> 8) & 0x3) << 4) | 5248 (((lane_map >> 12) & 0x3) << 6) ; 5249 5250 MAIN0_LN_SWPr_SET(reg, pcs_map); 5251 5252 PHYMOD_IF_ERR_RETURN 5253 (WRITE_MAIN0_LN_SWPr(pc, reg)) ; 5254 5255 return PHYMOD_E_NONE ; 5256 } 5257 5258 /** 5259 @brief sets PMD TX lane swap values for all lanes simultaneously. 5260 @param pc handle to current TSCE context (#PHYMOD_ST) 5261 @param addr_lane_index lane swap info as described in description 5262 @returns The value PHYMOD_E_NONE upon successful completion 5263 5264 This function sets the TX lane swap values for all lanes simultaneously. 5265 5266 The TSCE has several two sets of lane swap registers per lane. This function 5267 uses the lane swap registers closest to the pads. For TX, the lane swap occurs 5268 after all other analog/digital functionality. For RX, the lane swap occurs 5269 prior to all other analog/digital functionality. 5270 5271 It is not advisable to swap lanes without going through reset. 5272 5273 How the swap is done is indicated in the lane control field; 5274 bits 0 through 15 represent the swap settings for RX while bits 16 5275 through 31 represent the swap settings for TX. 5276 5277 Each 4 bit chunk within both the RX and TX sections represent the swap settings 5278 for a particular lane as follows: 5279 5280 Bits lane assignment 5281 5282 \li 15:12 TX lane 3 5283 \li 11:8 TX lane 2 5284 \li 7:4 TX lane 1 5285 \li 3:0 TX lane 0 5286 5287 Each 4-bit value may be either 0, 1, 2 or 3, with the value indicating the lane 5288 mapping. By default, the equivalent addr_lane_index settings are 0x3210_3210, 5289 indicating that there is no re-routing of traffic. As an example, to swap lanes 5290 0 and 1 for both RX and TX, the addr_lane_index should be set to 0x3201_3201. 5291 To swap lanes 0 and 1, and also lanes 2 and 3 for both RX and TX, the 5292 addr_lane_index should be set to 0x2301_2301. 5293 5294 */ 5295 int temod_pmd_addr_lane_swap(PHYMOD_ST *pc, uint32_t addr_lane_index) 5296 { 5297 DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r_t reg_adr_01; 5298 DIG_LN_ADDR_2_3r_t reg_adr_23; 5299 unsigned int map; 5300 unsigned int lane_addr_0, lane_addr_1, lane_addr_2, lane_addr_3; 5301 5302 TEMOD_DBG_IN_FUNC_INFO(pc); 5303 DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r_CLR(reg_adr_01); 5304 DIG_LN_ADDR_2_3r_CLR(reg_adr_23); 5305 5306 #ifdef _DV_TB_ 5307 map = (unsigned int)pc->per_lane_control; 5308 5309 lane_addr_0 = (map >> 16) & 0xf; 5310 lane_addr_1 = (map >> 20) & 0xf; 5311 lane_addr_2 = (map >> 24) & 0xf; 5312 lane_addr_3 = (map >> 28) & 0xf; 5313 5314 #else 5315 map = addr_lane_index ; 5316 5317 lane_addr_0 = (map >> 0) & 0xf; 5318 lane_addr_1 = (map >> 4) & 0xf; 5319 lane_addr_2 = (map >> 8) & 0xf; 5320 lane_addr_3 = (map >> 12) & 0xf; 5321 #endif 5322 5323 #ifdef _DV_TB_ 5324 pc->adjust_port_mode = 1; 5325 #endif 5326 5327 #ifdef _SDK_TEMOD_ 5328 5329 #endif 5330 5331 DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r_LANE_ADDR_0f_SET(reg_adr_01, lane_addr_0); 5332 DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r_LANE_ADDR_1f_SET(reg_adr_01, lane_addr_1); 5333 PHYMOD_IF_ERR_RETURN 5334 (MODIFY_DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r(pc, reg_adr_01)); 5335 5336 DIG_LN_ADDR_2_3r_LANE_ADDR_2f_SET(reg_adr_23, lane_addr_2); 5337 DIG_LN_ADDR_2_3r_LANE_ADDR_3f_SET(reg_adr_23, lane_addr_3); 5338 5339 PHYMOD_IF_ERR_RETURN 5340 (WRITE_DIG_LN_ADDR_2_3r(pc, reg_adr_23)); 5341 5342 #ifdef _DV_TB_ 5343 pc->adjust_port_mode = 0; 5344 #endif 5345 #ifdef _SDK_TEMOD_ 5346 5347 #endif 5348 5349 return PHYMOD_E_NONE ; 5350 } 5351 5352 5353 /** 5354 @brief Gets PMD TX lane swap values for all lanes simultaneously. 5355 @param pc handle to current TSCE context (#PHYMOD_ST) 5356 @param tx_lane_map receives the pmd tx lane map 5357 @returns The value PHYMOD_E_NONE upon successful completion 5358 5359 This function gets the TX lane swap values for all lanes simultaneously. 5360 5361 The TSCE has several two sets of lane swap registers per lane. This function 5362 uses the lane swap registers closest to the pads. For TX, the lane swap occurs 5363 after all other analog/digital functionality. For RX, the lane swap occurs 5364 prior to all other analog/digital functionality. 5365 5366 It is not allowed to swap lanes without going through reset. 5367 5368 How the swap is done is indicated in the tx_lane_map arg. 5369 bits 0 through 15 represent the swap settings for RX while bits 16 5370 through 31 represent the swap settings for TX. 5371 5372 Each 4 bit chunk within both the RX and TX sections represent the swap settings 5373 for a particular lane as follows: 5374 5375 Bits lane assignment 5376 5377 \li 15:12 TX lane 3 5378 \li 11:8 TX lane 2 5379 \li 7:4 TX lane 1 5380 \li 3:0 TX lane 0 5381 5382 Each 4-bit value may be either 0, 1, 2 or 3, with the value indicating the lane 5383 mapping. By default, the equivalent per_lane_control settings are 0x3210_3210, 5384 indicating that there is no re-routing of traffic. As an example, to swap lanes 5385 0 and 1 for both RX and TX, the per_lane_control should be set to 0x3201_3201. 5386 To swap lanes 0 and 1, and also lanes 2 and 3 for both RX and TX, the 5387 per_lane_control should be set to 0x2301_2301. 5388 */ 5389 int temod_pmd_lane_swap_tx_get ( PHYMOD_ST *pc, uint32_t *tx_lane_map) 5390 { 5391 uint16_t tx_lane_map_0, tx_lane_map_1, tx_lane_map_2, tx_lane_map_3; 5392 DIG_TX_LN_MAP_0_1_2r_t reg; 5393 DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r_t reg1; 5394 5395 TEMOD_DBG_IN_FUNC_INFO(pc); 5396 DIG_TX_LN_MAP_0_1_2r_CLR(reg); 5397 DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r_CLR(reg1); 5398 5399 PHYMOD_IF_ERR_RETURN 5400 (READ_DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r(pc, ®1)); 5401 PHYMOD_IF_ERR_RETURN 5402 (READ_DIG_TX_LN_MAP_0_1_2r(pc, ®)); 5403 5404 5405 tx_lane_map_0 = DIG_TX_LN_MAP_0_1_2r_TX_LANE_MAP_0f_GET(reg); 5406 tx_lane_map_1 = DIG_TX_LN_MAP_0_1_2r_TX_LANE_MAP_1f_GET(reg); 5407 tx_lane_map_2 = DIG_TX_LN_MAP_0_1_2r_TX_LANE_MAP_2f_GET(reg); 5408 tx_lane_map_3 = DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r_TX_LANE_MAP_3f_GET(reg1); 5409 5410 *tx_lane_map = ((tx_lane_map_0 & 0xf) << 0) 5411 | ((tx_lane_map_1 & 0xf) << 4) 5412 | ((tx_lane_map_2 & 0xf) << 8) 5413 | ((tx_lane_map_3 & 0xf) << 12); 5414 5415 return PHYMOD_E_NONE ; 5416 5417 } 5418 5419 /** 5420 @brief sets PMD TX lane swap values for all lanes simultaneously. 5421 @param pc handle to current TSCE context (#PHYMOD_ST) 5422 @param tx_lane_map 5423 @returns The value PHYMOD_E_NONE upon successful completion 5424 5425 This function sets the TX lane swap values for all lanes simultaneously. 5426 5427 The TSCE has several two sets of lane swap registers per lane. This function 5428 uses the lane swap registers closest to the pads. For TX, the lane swap occurs 5429 after all other analog/digital functionality. For RX, the lane swap occurs 5430 prior to all other analog/digital functionality. 5431 5432 It is not allowed to swap lanes without going through reset. 5433 */ 5434 int temod_pmd_lane_swap_tx(PHYMOD_ST *pc, uint32_t tx_lane_map) 5435 { 5436 uint16_t tx_lane_map_0, tx_lane_map_1, tx_lane_map_2, tx_lane_map_3; 5437 DIG_TX_LN_MAP_0_1_2r_t reg; 5438 DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r_t reg1; 5439 5440 TEMOD_DBG_IN_FUNC_INFO(pc); 5441 DIG_TX_LN_MAP_0_1_2r_CLR(reg); 5442 DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r_CLR(reg1); 5443 5444 tx_lane_map_0 = (tx_lane_map >> 0) & 0xf; 5445 tx_lane_map_1 = (tx_lane_map >> 4) & 0xf; 5446 tx_lane_map_2 = (tx_lane_map >> 8) & 0xf; 5447 tx_lane_map_3 = (tx_lane_map >> 12) & 0xf; 5448 5449 #ifdef _DV_TB_ 5450 pc->adjust_port_mode = 1; 5451 #endif 5452 #ifdef _SDK_TEMOD_ 5453 5454 #endif 5455 5456 DIG_TX_LN_MAP_0_1_2r_TX_LANE_MAP_0f_SET(reg, tx_lane_map_0); 5457 DIG_TX_LN_MAP_0_1_2r_TX_LANE_MAP_1f_SET(reg, tx_lane_map_1); 5458 DIG_TX_LN_MAP_0_1_2r_TX_LANE_MAP_2f_SET(reg, tx_lane_map_2); 5459 5460 PHYMOD_IF_ERR_RETURN 5461 (WRITE_DIG_TX_LN_MAP_0_1_2r(pc, reg)); 5462 5463 DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r_TX_LANE_MAP_3f_SET(reg1, tx_lane_map_3); 5464 PHYMOD_IF_ERR_RETURN 5465 (MODIFY_DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r(pc, reg1)); 5466 5467 #ifdef _DV_TB_ 5468 pc->adjust_port_mode = 0; 5469 #endif 5470 #ifdef _SDK_TEMOD_ 5471 5472 #endif 5473 return PHYMOD_E_NONE ; 5474 } 5475 5476 #ifdef _DV_TB_ 5477 /** 5478 @brief Read the 16 bit rev. id value etc. 5479 @param pc handle to current TSCE context (#PHYMOD_ST) 5480 @returns The value PHYMOD_E_NONE upon successful 5481 @details PCS Init calls this Per Port PCS Init routine 5482 */ 5483 int temod_set_port_mode_select(PHYMOD_ST* pc) 5484 { 5485 5486 int port_mode_sel ; 5487 uint16_t single_port_mode; 5488 MAIN0_SETUPr_t reg ; 5489 5490 MAIN0_SETUPr_CLR(reg); 5491 port_mode_sel = 0 ; 5492 if(pc->tsc_touched == 1) { 5493 single_port_mode = 0 ; 5494 MAIN0_SETUPr_CLR(reg); 5495 } else { 5496 MAIN0_SETUPr_MASTER_PORT_NUMf_SET(reg, pc->master_portnum); 5497 MAIN0_SETUPr_PLL_RESET_ENf_SET(reg, 1); 5498 } 5499 5500 switch(pc->port_type) { 5501 case TEMOD_MULTI_PORT: port_mode_sel = 0; break ; 5502 case TEMOD_TRI1_PORT: port_mode_sel = 1; break ; 5503 case TEMOD_TRI2_PORT: port_mode_sel = 2; break ; 5504 case TEMOD_DXGXS: port_mode_sel = 3; break ; 5505 case TEMOD_SINGLE_PORT: port_mode_sel = 4; break ; 5506 default: break ; 5507 } 5508 5509 if((pc->sc_mode == TEMOD_SC_MODE_AN_CL37) || (pc->sc_mode == TEMOD_SC_MODE_AN_CL73)) { 5510 /*data = port_mode_sel << MAIN0_SETUP_PORT_MODE_SEL_SHIFT |*/ 5511 MAIN0_SETUPr_SINGLE_PORT_MODEf_SET(reg, pc->single_port_mode); 5512 MAIN0_SETUPr_CL37_HIGH_VCOf_SET(reg, pc->cl37_high_vco); 5513 MAIN0_SETUPr_CL73_LOW_VCOf_SET(reg, pc->cl73_low_vco); 5514 5515 PHYMOD_IF_ERR_RETURN (MODIFY_MAIN0_SETUPr(pc, reg)); 5516 } else { 5517 MAIN0_SETUPr_SINGLE_PORT_MODEf_SET(reg, pc->single_port_mode); 5518 MAIN0_SETUPr_CL37_HIGH_VCOf_SET(reg, pc->cl37_high_vco); 5519 MAIN0_SETUPr_CL73_LOW_VCOf_SET(reg, pc->cl73_low_vco); 5520 MAIN0_SETUPr_PORT_MODE_SELf_SET(reg, port_mode_sel); 5521 5522 PHYMOD_IF_ERR_RETURN (MODIFY_MAIN0_SETUPr(pc, reg)); 5523 } 5524 return PHYMOD_E_NONE; 5525 } 5526 #endif 5527 5528 #ifdef _DV_TB_ 5529 /** 5530 @brief Read the 16 bit rev. id value etc. 5531 @param pc handle to current TSCE context (#PHYMOD_ST) 5532 @returns The value PHYMOD_E_NONE upon successful completion 5533 @details Per Port PCS Init 5534 5535 */ 5536 /* TBD PARAMETERIZE CODE for SDK*/ 5537 int _configure_st_entry(int st_entry_num, int st_entry_speed, PHYMOD_ST* pc) 5538 { 5539 SC_X1_SPD_OVRR0_SPDr_t reg0_ovr_spd; 5540 sC_X1_SPD_OVRR0_0r_t reg0_ovr; 5541 SC_X1_SPD_OVRR0_1r_t reg0_ovr1; 5542 SC_X1_SPD_OVRR0_2r_t reg0_ovr2; 5543 SC_X1_SPD_OVRR0_3r_t reg0_ovr3; 5544 SC_X1_SPD_OVRR0_4r_t reg0_ovr4; 5545 SC_X1_SPD_OVRR0_5r_t reg0_ovr5; 5546 SC_X1_SPD_OVRR0_6r_t reg0_ovr6; 5547 SC_X1_SPD_OVRR0_7r_t reg0_ovr7; 5548 SC_X1_SPD_OVRR0_8r_t reg0_ovr8; 5549 5550 SC_X1_SPD_OVRR1_SPDr_t reg1_ovr_spd; 5551 SC_X1_SPD_OVRR1_0r_t reg1_ovr; 5552 SC_X1_SPD_OVRR1_1r_t reg1_ovr1; 5553 SC_X1_SPD_OVRR1_2r_t reg1_ovr2; 5554 SC_X1_SPD_OVRR1_3r_t reg1_ovr3; 5555 SC_X1_SPD_OVRR1_4r_t reg1_ovr4; 5556 SC_X1_SPD_OVRR1_5r_t reg1_ovr5; 5557 SC_X1_SPD_OVRR1_6r_t reg1_ovr6; 5558 SC_X1_SPD_OVRR1_7r_t reg1_ovr7; 5559 SC_X1_SPD_OVRR1_8r_t reg1_ovr8; 5560 5561 SC_X1_SPD_OVRR2_SPDr_t reg2_ovr_spd; 5562 SC_X1_SPD_OVRR2_0r_t reg2_ovr; 5563 SC_X1_SPD_OVRR2_1r_t reg2_ovr1; 5564 SC_X1_SPD_OVRR2_2r_t reg2_ovr2; 5565 SC_X1_SPD_OVRR2_3r_t reg2_ovr3; 5566 SC_X1_SPD_OVRR2_4r_t reg2_ovr4; 5567 SC_X1_SPD_OVRR2_5r_t reg2_ovr5; 5568 SC_X1_SPD_OVRR2_6r_t reg2_ovr6; 5569 SC_X1_SPD_OVRR2_7r_t reg2_ovr7; 5570 SC_X1_SPD_OVRR2_8r_t reg2_ovr8; 5571 5572 SC_X1_SPD_OVRR3_SPDr_t reg3_ovr_spd; 5573 SC_X1_SPD_OVRR3_0r_t reg3_ovr; 5574 SC_X1_SPD_OVRR3_1r_t reg3_ovr1; 5575 SC_X1_SPD_OVRR3_2r_t reg3_ovr2; 5576 SC_X1_SPD_OVRR3_3r_t reg3_ovr3; 5577 SC_X1_SPD_OVRR3_4r_t reg3_ovr4; 5578 SC_X1_SPD_OVRR3_5r_t reg3_ovr5; 5579 SC_X1_SPD_OVRR3_6r_t reg3_ovr6; 5580 SC_X1_SPD_OVRR3_7r_t reg3_ovr7; 5581 SC_X1_SPD_OVRR3_8r_t reg3_ovr8; 5582 5583 if(st_entry_num == 0) { 5584 5585 SC_X1_SPD_OVRR0_SPDr_CLR(reg0_ovr_spd); 5586 SC_X1_SPD_OVRR0_SPDr_NUM_LANESf_SET(reg0_ovr_spd, pc->num_lanes); 5587 SC_X1_SPD_OVRR0_SPDr_SPEEDf_SET(reg0_ovr_spd, st_entry_speed); 5588 5589 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_SPDr(pc, reg0_ovr_spd)); 5590 5591 SC_X1_SPD_OVRR0_0r_CLR(reg0_ovr); 5592 SC_X1_SPD_OVRR0_1r_CLR(reg0_ovr1); 5593 SC_X1_SPD_OVRR0_2r_CLR(reg0_ovr2); 5594 SC_X1_SPD_OVRR0_3r_CLR(reg0_ovr3); 5595 SC_X1_SPD_OVRR0_4r_CLR(reg0_ovr4); 5596 SC_X1_SPD_OVRR0_5r_CLR(reg0_ovr5); 5597 SC_X1_SPD_OVRR0_6r_CLR(reg0_ovr6); 5598 SC_X1_SPD_OVRR0_7r_CLR(reg0_ovr7); 5599 SC_X1_SPD_OVRR0_8r_CLR(reg0_ovr8); 5600 5601 SC_X1_SPD_OVRR0_0r_ENCODEMODEf_SET(reg0_ovr, pc->t_encode_mode); 5602 SC_X1_SPD_OVRR0_0r_SCR_MODEf_SET(reg0_ovr, pc->t_scr_mode); 5603 SC_X1_SPD_OVRR0_0r_OS_MODEf_SET(reg0_ovr, pc->t_pma_os_mode); 5604 5605 5606 if(pc->cl72_en & 0x40000000) 5607 SC_X1_SPD_OVRR0_0r_CL72_ENABLEf_SET(reg0_ovr, pc->cl72_en) ; 5608 5609 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_0r(pc, reg0_ovr)); 5610 5611 SC_X1_SPD_OVRR0_1r_BRCM64B66_DESCRAMBLER_ENABLEf_SET(reg0_ovr1, pc->r_dec1_brcm64b66_descr); 5612 SC_X1_SPD_OVRR0_1r_CL36BYTEDELETEMODEf_SET(reg0_ovr1, pc->r_desc2_byte_deletion); 5613 SC_X1_SPD_OVRR0_1r_DESC2_MODEf_SET(reg0_ovr1, pc->r_desc2_mode); 5614 SC_X1_SPD_OVRR0_1r_DESKEWMODEf_SET(reg0_ovr1, pc->r_deskew_mode); 5615 SC_X1_SPD_OVRR0_1r_DECODERMODEf_SET(reg0_ovr1, pc->r_dec1_mode); 5616 SC_X1_SPD_OVRR0_1r_DESCRAMBLERMODEf_SET(reg0_ovr1, pc->r_descr1_mode); 5617 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_1r(pc, reg0_ovr1)); 5618 5619 SC_X1_SPD_OVRR0_2r_CL36_ENf_SET(reg0_ovr2, pc->cl36_en); 5620 SC_X1_SPD_OVRR0_2r_REORDER_ENf_SET(reg0_ovr2, pc->r_reorder_mode); 5621 SC_X1_SPD_OVRR0_2r_BLOCK_SYNC_MODEf_SET(reg0_ovr2, pc->blk_sync_mode); 5622 SC_X1_SPD_OVRR0_2r_CHK_END_ENf_SET(reg0_ovr2, pc->cl48_check_end); 5623 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_2r(pc, reg0_ovr2)); 5624 5625 SC_X1_SPD_OVRR0_3r_CLOCKCNT0f_SET(reg0_ovr3, pc->clkcnt0); 5626 SC_X1_SPD_OVRR0_3r_SGMII_SPD_SWITCHf_SET(reg0_ovr3, pc->sgmii); 5627 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_3r(pc, reg0_ovr3)); 5628 5629 SC_X1_SPD_OVRR0_4r_CLOCKCNT1f_SET(reg0_ovr4, pc->clkcnt1); 5630 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_4r(pc, reg0_ovr4)); 5631 5632 SC_X1_SPD_OVRR0_5r_LOOPCNT1f_SET(reg0_ovr5, pc->lpcnt1); 5633 SC_X1_SPD_OVRR0_5r_LOOPCNT0f_SET(reg0_ovr5, pc->lpcnt0); 5634 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_5r(pc, reg0_ovr5)); 5635 5636 SC_X1_SPD_OVRR0_6r_MAC_CREDITGENCNTf_SET(reg0_ovr6, pc->mac_cgc); 5637 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_6r(pc, reg0_ovr6)); 5638 SC_X1_SPD_OVRR0_7r_PCS_CLOCKCNT0f_SET(reg0_ovr7, pc->pcs_clkcnt); 5639 SC_X1_SPD_OVRR0_7r_PCS_CREDITENABLEf_SET(reg0_ovr7, pc->pcs_crdten); 5640 SC_X1_SPD_OVRR0_7r_REPLICATION_CNTf_SET(reg0_ovr7, pc->pcs_repcnt); 5641 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_7r(pc, reg0_ovr7)); 5642 5643 SC_X1_SPD_OVRR0_8r_PCS_CREDITGENCNTf_SET(reg0_ovr8, pc->pcs_cgc); 5644 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_8r(pc, reg0_ovr8)); 5645 } /* (st_entry_num == 0) */ 5646 5647 else if(st_entry_num == 1) { 5648 5649 5650 SC_X1_SPD_OVRR1_SPDr_CLR(reg1_ovr_spd); 5651 SC_X1_SPD_OVRR1_SPDr_NUM_LANESf_SET(reg1_ovr_spd, pc->num_lanes); 5652 SC_X1_SPD_OVRR1_SPDr_SPEEDf_SET(reg1_ovr_spd, st_entry_speed); 5653 5654 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_SPDr(pc, reg1_ovr_spd)); 5655 5656 SC_X1_SPD_OVRR1_0r_CLR(reg1_ovr); 5657 SC_X1_SPD_OVRR1_1r_CLR(reg1_ovr1); 5658 SC_X1_SPD_OVRR1_2r_CLR(reg1_ovr2); 5659 SC_X1_SPD_OVRR1_3r_CLR(reg1_ovr3); 5660 SC_X1_SPD_OVRR1_4r_CLR(reg1_ovr4); 5661 SC_X1_SPD_OVRR1_5r_CLR(reg1_ovr5); 5662 SC_X1_SPD_OVRR1_6r_CLR(reg1_ovr6); 5663 SC_X1_SPD_OVRR1_7r_CLR(reg1_ovr7); 5664 SC_X1_SPD_OVRR1_8r_CLR(reg1_ovr8); 5665 5666 SC_X1_SPD_OVRR1_0r_ENCODEMODEf_SET(reg1_ovr, pc->t_encode_mode); 5667 SC_X1_SPD_OVRR1_0r_SCR_MODEf_SET(reg1_ovr, pc->t_scr_mode); 5668 SC_X1_SPD_OVRR1_0r_OS_MODEf_SET(reg1_ovr, pc->t_pma_os_mode); 5669 5670 5671 if(pc->cl72_en & 0x40000000) 5672 SC_X1_SPD_OVRR1_0r_CL72_ENABLEf_SET(reg1_ovr, pc->cl72_en) ; 5673 5674 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_0r(pc, reg1_ovr)); 5675 5676 SC_X1_SPD_OVRR1_1r_BRCM64B66_DESCRAMBLER_ENABLEf_SET(reg1_ovr1, pc->r_dec1_brcm64b66_descr); 5677 SC_X1_SPD_OVRR1_1r_CL36BYTEDELETEMODEf_SET(reg1_ovr1, pc->r_desc2_byte_deletion); 5678 SC_X1_SPD_OVRR1_1r_DESC2_MODEf_SET(reg1_ovr1, pc->r_desc2_mode); 5679 SC_X1_SPD_OVRR1_1r_DESKEWMODEf_SET(reg1_ovr1, pc->r_deskew_mode); 5680 SC_X1_SPD_OVRR1_1r_DECODERMODEf_SET(reg1_ovr1, pc->r_dec1_mode); 5681 SC_X1_SPD_OVRR1_1r_DESCRAMBLERMODEf_SET(reg1_ovr1, pc->r_descr1_mode); 5682 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_1r(pc, reg1_ovr1)); 5683 5684 SC_X1_SPD_OVRR1_2r_CL36_ENf_SET(reg1_ovr2, pc->cl36_en); 5685 SC_X1_SPD_OVRR1_2r_REORDER_ENf_SET(reg1_ovr2, pc->r_reorder_mode); 5686 SC_X1_SPD_OVRR1_2r_BLOCK_SYNC_MODEf_SET(reg1_ovr2, pc->blk_sync_mode); 5687 SC_X1_SPD_OVRR1_2r_CHK_END_ENf_SET(reg1_ovr2, pc->cl48_check_end); 5688 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_2r(pc, reg1_ovr2)); 5689 5690 SC_X1_SPD_OVRR1_3r_CLOCKCNT0f_SET(reg1_ovr3, pc->clkcnt0); 5691 SC_X1_SPD_OVRR1_3r_SGMII_SPD_SWITCHf_SET(reg1_ovr3, pc->sgmii); 5692 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_3r(pc, reg1_ovr3)); 5693 5694 SC_X1_SPD_OVRR1_4r_CLOCKCNT1f_SET(reg1_ovr4, pc->clkcnt1); 5695 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_4r(pc, reg1_ovr4)); 5696 5697 SC_X1_SPD_OVRR1_5r_LOOPCNT1f_SET(reg1_ovr5, pc->lpcnt1); 5698 SC_X1_SPD_OVRR1_5r_LOOPCNT0f_SET(reg1_ovr5, pc->lpcnt0); 5699 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_5r(pc, reg1_ovr5)); 5700 5701 SC_X1_SPD_OVRR1_6r_MAC_CREDITGENCNTf_SET(reg1_ovr6, pc->mac_cgc); 5702 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_6r(pc, reg1_ovr6)); 5703 SC_X1_SPD_OVRR1_7r_PCS_CLOCKCNT0f_SET(reg1_ovr7, pc->pcs_clkcnt); 5704 SC_X1_SPD_OVRR1_7r_PCS_CREDITENABLEf_SET(reg1_ovr7, pc->pcs_crdten); 5705 SC_X1_SPD_OVRR1_7r_REPLICATION_CNTf_SET(reg1_ovr7, pc->pcs_repcnt); 5706 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_7r(pc, reg1_ovr7)); 5707 5708 SC_X1_SPD_OVRR1_8r_PCS_CREDITGENCNTf_SET(reg1_ovr8, pc->pcs_cgc); 5709 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_8r(pc, reg1_ovr8)); 5710 5711 5712 5713 } /* (st_entry_num == 1) */ 5714 5715 else if(st_entry_num == 2) { 5716 5717 SC_X1_SPD_OVRR2_SPDr_CLR(reg2_ovr_spd); 5718 SC_X1_SPD_OVRR2_SPDr_NUM_LANESf_SET(reg2_ovr_spd, pc->num_lanes); 5719 SC_X1_SPD_OVRR2_SPDr_SPEEDf_SET(reg2_ovr_spd, st_entry_speed); 5720 5721 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_SPDr(pc, reg2_ovr_spd)); 5722 5723 SC_X1_SPD_OVRR2_0r_CLR(reg2_ovr); 5724 SC_X1_SPD_OVRR2_1r_CLR(reg2_ovr1); 5725 SC_X1_SPD_OVRR2_2r_CLR(reg2_ovr2); 5726 SC_X1_SPD_OVRR2_3r_CLR(reg2_ovr3); 5727 SC_X1_SPD_OVRR2_4r_CLR(reg2_ovr4); 5728 SC_X1_SPD_OVRR2_5r_CLR(reg2_ovr5); 5729 SC_X1_SPD_OVRR2_6r_CLR(reg2_ovr6); 5730 SC_X1_SPD_OVRR2_7r_CLR(reg2_ovr7); 5731 SC_X1_SPD_OVRR2_8r_CLR(reg2_ovr8); 5732 5733 SC_X1_SPD_OVRR2_0r_ENCODEMODEf_SET(reg2_ovr, pc->t_encode_mode); 5734 SC_X1_SPD_OVRR2_0r_SCR_MODEf_SET(reg2_ovr, pc->t_scr_mode); 5735 SC_X1_SPD_OVRR2_0r_OS_MODEf_SET(reg2_ovr, pc->t_pma_os_mode); 5736 5737 5738 if(pc->cl72_en & 0x40000000) 5739 SC_X1_SPD_OVRR2_0r_CL72_ENABLEf_SET(reg2_ovr, pc->cl72_en) ; 5740 5741 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_0r(pc, reg2_ovr)); 5742 5743 SC_X1_SPD_OVRR2_1r_BRCM64B66_DESCRAMBLER_ENABLEf_SET(reg2_ovr1, pc->r_dec1_brcm64b66_descr); 5744 SC_X1_SPD_OVRR2_1r_CL36BYTEDELETEMODEf_SET(reg2_ovr1, pc->r_desc2_byte_deletion); 5745 SC_X1_SPD_OVRR2_1r_DESC2_MODEf_SET(reg2_ovr1, pc->r_desc2_mode); 5746 SC_X1_SPD_OVRR2_1r_DESKEWMODEf_SET(reg2_ovr1, pc->r_deskew_mode); 5747 SC_X1_SPD_OVRR2_1r_DECODERMODEf_SET(reg2_ovr1, pc->r_dec1_mode); 5748 SC_X1_SPD_OVRR2_1r_DESCRAMBLERMODEf_SET(reg2_ovr1, pc->r_descr1_mode); 5749 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_1r(pc, reg2_ovr1)); 5750 5751 SC_X1_SPD_OVRR2_2r_CL36_ENf_SET(reg2_ovr2, pc->cl36_en); 5752 SC_X1_SPD_OVRR2_2r_REORDER_ENf_SET(reg2_ovr2, pc->r_reorder_mode); 5753 SC_X1_SPD_OVRR2_2r_BLOCK_SYNC_MODEf_SET(reg2_ovr2, pc->blk_sync_mode); 5754 SC_X1_SPD_OVRR2_2r_CHK_END_ENf_SET(reg2_ovr2, pc->cl48_check_end); 5755 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_2r(pc, reg2_ovr2)); 5756 5757 SC_X1_SPD_OVRR2_3r_CLOCKCNT0f_SET(reg2_ovr3, pc->clkcnt0); 5758 SC_X1_SPD_OVRR2_3r_SGMII_SPD_SWITCHf_SET(reg2_ovr3, pc->sgmii); 5759 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_3r(pc, reg2_ovr3)); 5760 5761 SC_X1_SPD_OVRR2_4r_CLOCKCNT1f_SET(reg2_ovr4, pc->clkcnt1); 5762 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_4r(pc, reg2_ovr4)); 5763 5764 SC_X1_SPD_OVRR2_5r_LOOPCNT1f_SET(reg2_ovr5, pc->lpcnt1); 5765 SC_X1_SPD_OVRR2_5r_LOOPCNT0f_SET(reg2_ovr5, pc->lpcnt0); 5766 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_5r(pc, reg2_ovr5)); 5767 5768 SC_X1_SPD_OVRR2_6r_MAC_CREDITGENCNTf_SET(reg2_ovr6, pc->mac_cgc); 5769 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_6r(pc, reg2_ovr6)); 5770 SC_X1_SPD_OVRR2_7r_PCS_CLOCKCNT0f_SET(reg2_ovr7, pc->pcs_clkcnt); 5771 SC_X1_SPD_OVRR2_7r_PCS_CREDITENABLEf_SET(reg2_ovr7, pc->pcs_crdten); 5772 SC_X1_SPD_OVRR2_7r_REPLICATION_CNTf_SET(reg2_ovr7, pc->pcs_repcnt); 5773 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_7r(pc, reg2_ovr7)); 5774 5775 SC_X1_SPD_OVRR2_8r_PCS_CREDITGENCNTf_SET(reg2_ovr8, pc->pcs_cgc); 5776 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_8r(pc, reg2_ovr8)); 5777 } /* (st_entry_num == 2) */ 5778 5779 else /*(st_entry_num == 3) */ { 5780 5781 SC_X1_SPD_OVRR3_SPDr_CLR(reg3_ovr_spd); 5782 SC_X1_SPD_OVRR3_SPDr_NUM_LANESf_SET(reg3_ovr_spd, pc->num_lanes); 5783 SC_X1_SPD_OVRR3_SPDr_SPEEDf_SET(reg3_ovr_spd, st_entry_speed); 5784 5785 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_SPDr(pc, reg3_ovr_spd)); 5786 5787 SC_X1_SPD_OVRR3_0r_CLR(reg3_ovr); 5788 SC_X1_SPD_OVRR3_1r_CLR(reg3_ovr1); 5789 SC_X1_SPD_OVRR3_2r_CLR(reg3_ovr2); 5790 SC_X1_SPD_OVRR3_3r_CLR(reg3_ovr3); 5791 SC_X1_SPD_OVRR3_4r_CLR(reg3_ovr4); 5792 SC_X1_SPD_OVRR3_5r_CLR(reg3_ovr5); 5793 SC_X1_SPD_OVRR3_6r_CLR(reg3_ovr6); 5794 SC_X1_SPD_OVRR3_7r_CLR(reg3_ovr7); 5795 SC_X1_SPD_OVRR3_8r_CLR(reg3_ovr8); 5796 5797 SC_X1_SPD_OVRR3_0r_ENCODEMODEf_SET(reg3_ovr, pc->t_encode_mode); 5798 SC_X1_SPD_OVRR3_0r_SCR_MODEf_SET(reg3_ovr, pc->t_scr_mode); 5799 SC_X1_SPD_OVRR3_0r_OS_MODEf_SET(reg3_ovr, pc->t_pma_os_mode); 5800 5801 5802 if(pc->cl72_en & 0x40000000) 5803 SC_X1_SPD_OVRR3_0r_CL72_ENABLEf_SET(reg3_ovr, pc->cl72_en) ; 5804 5805 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_0r(pc, reg3_ovr)); 5806 5807 SC_X1_SPD_OVRR3_1r_BRCM64B66_DESCRAMBLER_ENABLEf_SET(reg3_ovr1, pc->r_dec1_brcm64b66_descr); 5808 SC_X1_SPD_OVRR3_1r_CL36BYTEDELETEMODEf_SET(reg3_ovr1, pc->r_desc2_byte_deletion); 5809 SC_X1_SPD_OVRR3_1r_DESC2_MODEf_SET(reg3_ovr1, pc->r_desc2_mode); 5810 SC_X1_SPD_OVRR3_1r_DESKEWMODEf_SET(reg3_ovr1, pc->r_deskew_mode); 5811 SC_X1_SPD_OVRR3_1r_DECODERMODEf_SET(reg3_ovr1, pc->r_dec1_mode); 5812 SC_X1_SPD_OVRR3_1r_DESCRAMBLERMODEf_SET(reg3_ovr1, pc->r_descr1_mode); 5813 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_1r(pc, reg3_ovr1)); 5814 5815 SC_X1_SPD_OVRR3_2r_CL36_ENf_SET(reg3_ovr2, pc->cl36_en); 5816 SC_X1_SPD_OVRR3_2r_REORDER_ENf_SET(reg3_ovr2, pc->r_reorder_mode); 5817 SC_X1_SPD_OVRR3_2r_BLOCK_SYNC_MODEf_SET(reg3_ovr2, pc->blk_sync_mode); 5818 SC_X1_SPD_OVRR3_2r_CHK_END_ENf_SET(reg3_ovr2, pc->cl48_check_end); 5819 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_2r(pc, reg3_ovr2)); 5820 5821 SC_X1_SPD_OVRR3_3r_CLOCKCNT0f_SET(reg3_ovr3, pc->clkcnt0); 5822 SC_X1_SPD_OVRR3_3r_SGMII_SPD_SWITCHf_SET(reg3_ovr3, pc->sgmii); 5823 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_3r(pc, reg3_ovr3)); 5824 5825 SC_X1_SPD_OVRR3_4r_CLOCKCNT1f_SET(reg3_ovr4, pc->clkcnt1); 5826 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_4r(pc, reg3_ovr4)); 5827 5828 SC_X1_SPD_OVRR3_5r_LOOPCNT1f_SET(reg3_ovr5, pc->lpcnt1); 5829 SC_X1_SPD_OVRR3_5r_LOOPCNT0f_SET(reg3_ovr5, pc->lpcnt0); 5830 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_5r(pc, reg3_ovr5)); 5831 5832 SC_X1_SPD_OVRR3_6r_MAC_CREDITGENCNTf_SET(reg3_ovr6, pc->mac_cgc); 5833 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_6r(pc, reg3_ovr6)); 5834 SC_X1_SPD_OVRR3_7r_PCS_CLOCKCNT0f_SET(reg3_ovr7, pc->pcs_clkcnt); 5835 SC_X1_SPD_OVRR3_7r_PCS_CREDITENABLEf_SET(reg3_ovr7, pc->pcs_crdten); 5836 SC_X1_SPD_OVRR3_7r_REPLICATION_CNTf_SET(reg3_ovr7, pc->pcs_repcnt); 5837 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_7r(pc, reg3_ovr7)); 5838 5839 SC_X1_SPD_OVRR3_8r_PCS_CREDITGENCNTf_SET(reg3_ovr8, pc->pcs_cgc); 5840 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_8r(pc, reg3_ovr8)); 5841 } /* (st_entry_num == 3) */ 5842 5843 return PHYMOD_E_NONE; 5844 } 5845 #endif 5846 5847 #ifdef _DV_TB_ 5848 /** 5849 @brief Read the 16 bit rev. id value etc. 5850 @param pc handle to current TSCE context (#PHYMOD_ST) 5851 @returns The value PHYMOD_E_NONE upon successful completion 5852 @details Per Port PCS Init 5853 */ 5854 int _configure_sc_speed_configuration(PHYMOD_ST* pc) 5855 { 5856 int data =0; 5857 int mask =0; 5858 int st_entry =0; 5859 int speed_entry = 0; 5860 PHYMOD_ST pc_st_tmp; 5861 PHYMOD_ST* pc_st; 5862 5863 if(pc->sc_mode == TEMOD_SC_MODE_HT_WITH_BASIC_OVERRIDE){ 5864 /* Configure the ffec_eb regsiter */ 5865 data |= (1 << 10); 5866 mask |= 0x0400; 5867 5868 } 5869 else if(pc->sc_mode == TEMOD_SC_MODE_ST_OVERRIDE) { 5870 } 5871 else if(pc->sc_mode == TEMOD_SC_MODE_ST) { 5872 st_entry = pc->per_lane_control & 0xff; 5873 speed_entry = (pc->per_lane_control & 0xff00) >> 8; 5874 5875 /* 5876 A pc_st_tmp is created so the overriden expected values passed from SV are not 5877 loaded in ST, and teh ST has the same HT values 5878 */ 5879 init_temod_st(&pc_st_tmp); 5880 pc_st_tmp.spd_intf = pc->spd_intf; 5881 pc_st_tmp.prt_ad = pc->prt_ad; 5882 pc_st_tmp.unit = pc->unit; 5883 pc_st_tmp.port_type = pc->port_type; 5884 pc_st_tmp.this_lane = pc->this_lane; 5885 pc_st_tmp.sc_mode = pc->sc_mode; 5886 pc_st_tmp.cl72_en = pc->cl72_en; 5887 pc_st = &pc_st_tmp; 5888 temod_sc_lkup_table(pc_st); 5889 /*configure the ST regsiters */ 5890 _configure_st_entry(st_entry, speed_entry, pc_st); 5891 } 5892 return PHYMOD_E_NONE; 5893 } 5894 #endif 5895 5896 #ifdef _DV_TB_ 5897 /** 5898 @brief Read the 16 bit rev. id value etc. 5899 @param pc handle to current TSCE context (#PHYMOD_ST) 5900 @returns The value PHYMOD_E_NONE upon successful completion 5901 @details Per Port PCS Init 5902 */ 5903 int _init_pcs_an(PHYMOD_ST* pc) 5904 { 5905 UC_COMMAND4r_t reg_com4; 5906 UC_COMMANDr_t reg_com; 5907 5908 UC_COMMAND4r_CLR(reg_com4); 5909 UC_COMMANDr_CLR(reg_com); 5910 5911 UC_COMMAND4r_MICRO_SYSTEM_CLK_ENf_SET(reg_com4,1); 5912 UC_COMMAND4r_MICRO_SYSTEM_RESET_Nf_SET(reg_com4,1); 5913 PHYMOD_IF_ERR_RETURN(MODIFY_UC_COMMAND4r(pc, reg_com4)); 5914 5915 UC_COMMANDr_MICRO_MDIO_DW8051_RESET_Nf_SET(reg_com,1); 5916 PHYMOD_IF_ERR_RETURN(MODIFY_UC_COMMANDr(pc, reg_com)); 5917 5918 temod_set_an_port_mode(pc); 5919 pc->port_type=TEMOD_MULTI_PORT; 5920 temod_autoneg_set(pc); 5921 temod_autoneg_control(pc); 5922 5923 return PHYMOD_E_NONE; 5924 } 5925 #endif /* _DV_TB_ */ 5926 #ifdef _SDK_TEMOD_TEMP_ 5927 5928 int _init_pcs_an(PHYMOD_ST* pc) 5929 { 5930 temod_an_set_type_t ata_type; 5931 temod_tech_ability an_tech_ability = 0; 5932 temod_cl37bam_ability an_cl37bam_ability = 0; 5933 temod_an_mode_type_t an_mode = 0; 5934 int data; 5935 5936 /* temod_autoneg_init(pc); */ 5937 temod_autoneg_timer_init(pc); 5938 /* temod_tick_override_set(pc, pc->an_tick_override, pc->an_tick_numerator, pc->an_tick_denominator); */ 5939 temod_set_an_port_mode(pc, pc->no_of_lanes, pc->this_lane, pc->single_port); 5940 5941 /* TBD: add locgic to port the info from pc to an_ability_st and an_control */ 5942 temod_autoneg_set( pc, an_ability_st); 5943 temod_autoneg_control(pc, an_control) 5944 5945 return PHYMOD_E_NONE; 5946 } 5947 #endif /* _SDK_TEMOD_TEMP_ */ 5948 5949 /** 5950 @brief Function to control the configuration of PCS hardware blocks 5951 @param pc handle to current TSCE context (#PHYMOD_ST) 5952 @returns The value PHYMOD_E_NONE upon successful completion 5953 @details This function triggers the PCS speed-config logic to go ahead and 5954 configure various PCS blocks for the desired speed. The speed (which is an 5955 enumerated type) is already known. This trigger also controls PMD datapath 5956 resets. So sometimes we use this function just to toggle PMD datapath resets as 5957 well. 5958 */ 5959 5960 int temod_trigger_speed_change(PHYMOD_ST* pc) 5961 { 5962 SC_X4_CTLr_t reg; 5963 5964 TEMOD_DBG_IN_FUNC_INFO(pc); 5965 #ifdef _DV_TB_ 5966 pc->adjust_port_mode = 1; 5967 #endif /* _DV_TB_ */ 5968 5969 /* write 0 to the speed change */ 5970 SC_X4_CTLr_CLR(reg); 5971 PHYMOD_IF_ERR_RETURN(READ_SC_X4_CTLr(pc, ®)); 5972 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(reg, 0); 5973 PHYMOD_IF_ERR_RETURN(WRITE_SC_X4_CTLr(pc, reg)); 5974 5975 /* write 1 to the speed change. No need to read again before write*/ 5976 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(reg, 1); 5977 PHYMOD_IF_ERR_RETURN(WRITE_SC_X4_CTLr(pc, reg)); 5978 5979 #ifdef _DV_TB_ 5980 pc->adjust_port_mode = 0; 5981 #endif /* _DV_TB_ */ 5982 return PHYMOD_E_NONE; 5983 } 5984 5985 #ifdef _DV_TB_ 5986 /** 5987 @brief Compare status registers in PCS with reference values in TEMod 5988 @param pc handle to current TSCE context (#PHYMOD_ST) 5989 @returns The value PHYMOD_E_NONE upon successful completion 5990 @details After PCS programms various PCS blocks, the status is updated. This 5991 function reads out the updated status and validates them. 5992 */ 5993 int _read_and_compare_final_status(PHYMOD_ST* pc) 5994 { 5995 uint16_t fail; 5996 int actual_speed; 5997 PHYMOD_ST sc_final_stats_actual; 5998 PHYMOD_ST* sc_final_stats_actual_tmp; 5999 SC_X4_RSLVD_SPDr_t reg_resolved_spd; 6000 SC_X4_RSLVD0r_t reg_resolved_0; 6001 SC_X4_RSLVD1r_t reg_resolved_1; 6002 SC_X4_RSLVD2r_t reg_resolved_2; 6003 SC_X4_RSLVD3r_t reg_resolved_3; 6004 SC_X4_RSLVD4r_t reg_resolved_4; 6005 SC_X4_RSLVD5r_t reg_resolved_5; 6006 SC_X4_RSLVD6r_t reg_resolved_6; 6007 SC_X4_RSLVD7r_t reg_resolved_7; 6008 SC_X4_RSLVD8r_t reg_resolved_8; 6009 6010 SC_X4_RSLVD_SPDr_CLR(reg_resolved_spd); 6011 PHYMOD_IF_ERR_RETURN(READ_SC_X4_RSLVD_SPDr(pc, ®_resolved_spd)); 6012 sc_final_stats_actual.num_lanes = SC_X4_RSLVD_SPDr_NUM_LANESf_GET(reg_resolved_spd); 6013 actual_speed = SC_X4_RSLVD_SPDr_SPEEDf_GET(reg_resolved_spd); 6014 sc_final_stats_actual.speed = actual_speed; 6015 6016 SC_X4_RSLVD0r_CLR(reg_resolved_0); 6017 PHYMOD_IF_ERR_RETURN(READ_SC_X4_RSLVD0r(pc, ®_resolved_0)); 6018 sc_final_stats_actual.t_encode_mode = SC_X4_RSLVD0r_ENCODEMODEf_GET(reg_resolved_0); 6019 sc_final_stats_actual.cl72_en = SC_X4_RSLVD0r_CL72_ENABLEf_GET(reg_resolved_0); 6020 sc_final_stats_actual.fec_en = SC_X4_RSLVD0r_FEC_ENABLEf_GET(reg_resolved_0); 6021 sc_final_stats_actual.t_scr_mode = SC_X4_RSLVD0r_SCR_MODEf_GET(reg_resolved_0); 6022 sc_final_stats_actual.t_pma_os_mode = SC_X4_RSLVD0r_OS_MODEf_GET(reg_resolved_0); 6023 6024 SC_X4_RSLVD1r_CLR(reg_resolved_1); 6025 PHYMOD_IF_ERR_RETURN(READ_SC_X4_RSLVD1r(pc, ®_resolved_1)); 6026 sc_final_stats_actual.r_dec1_brcm64b66_descr = SC_X4_RSLVD1r_BRCM64B66_DESCRAMBLER_ENABLEf_GET(reg_resolved_1); 6027 sc_final_stats_actual.r_desc2_byte_deletion = SC_X4_RSLVD1r_CL36BYTEDELETEMODEf_GET(reg_resolved_1); 6028 sc_final_stats_actual.r_desc2_mode = SC_X4_RSLVD1r_DESC2_MODEf_GET(reg_resolved_1); 6029 sc_final_stats_actual.r_deskew_mode = SC_X4_RSLVD1r_DESKEWMODEf_GET(reg_resolved_1); 6030 sc_final_stats_actual.r_dec1_mode = SC_X4_RSLVD1r_DECODERMODEf_GET(reg_resolved_1); 6031 sc_final_stats_actual.r_descr1_mode = SC_X4_RSLVD1r_DESCRAMBLERMODEf_GET(reg_resolved_1); 6032 6033 SC_X4_RSLVD2r_CLR(reg_resolved_2); 6034 PHYMOD_IF_ERR_RETURN(READ_SC_X4_RSLVD2r(pc, ®_resolved_2)); 6035 sc_final_stats_actual.cl36_en = SC_X4_RSLVD2r_CL36_ENf_GET(reg_resolved_2); 6036 sc_final_stats_actual.r_reorder_mode = SC_X4_RSLVD2r_REORDER_ENf_GET(reg_resolved_2); 6037 sc_final_stats_actual.blk_sync_mode = SC_X4_RSLVD2r_BLOCK_SYNC_MODEf_GET(reg_resolved_2); 6038 sc_final_stats_actual.cl48_check_end = SC_X4_RSLVD2r_CHK_END_ENf_GET(reg_resolved_2); 6039 6040 SC_X4_RSLVD3r_CLR(reg_resolved_3); 6041 PHYMOD_IF_ERR_RETURN(READ_SC_X4_RSLVD3r(pc, ®_resolved_3)); 6042 sc_final_stats_actual.clkcnt0 = SC_X4_RSLVD3r_CLOCKCNT0f_GET(reg_resolved_3); 6043 sc_final_stats_actual.sgmii = SC_X4_RSLVD3r_SGMII_SPD_SWITCHf_GET(reg_resolved_3); 6044 6045 SC_X4_RSLVD4r_CLR(reg_resolved_4); 6046 PHYMOD_IF_ERR_RETURN(READ_SC_X4_RSLVD4r(pc, ®_resolved_4)); 6047 sc_final_stats_actual.clkcnt1 = SC_X4_RSLVD4r_CLOCKCNT1f_GET(reg_resolved_4); 6048 6049 SC_X4_RSLVD5r_CLR(reg_resolved_5); 6050 PHYMOD_IF_ERR_RETURN(READ_SC_X4_RSLVD5r(pc, ®_resolved_5)); 6051 sc_final_stats_actual.lpcnt1 = SC_X4_RSLVD5r_LOOPCNT1f_GET(reg_resolved_5); 6052 sc_final_stats_actual.lpcnt0 = SC_X4_RSLVD5r_LOOPCNT0f_GET(reg_resolved_5); 6053 6054 SC_X4_RSLVD6r_CLR(reg_resolved_6); 6055 PHYMOD_IF_ERR_RETURN(READ_SC_X4_RSLVD6r(pc, ®_resolved_6)); 6056 sc_final_stats_actual.mac_cgc = SC_X4_RSLVD6r_MAC_CREDITGENCNTf_GET(reg_resolved_6); 6057 6058 SC_X4_RSLVD7r_CLR(reg_resolved_7); 6059 PHYMOD_IF_ERR_RETURN(READ_SC_X4_RSLVD7r(pc, ®_resolved_7)); 6060 sc_final_stats_actual.pcs_clkcnt = SC_X4_RSLVD7r_PCS_CLOCKCNT0f_GET(reg_resolved_7); 6061 sc_final_stats_actual.pcs_crdten = SC_X4_RSLVD7r_PCS_CREDITENABLEf_GET(reg_resolved_7); 6062 sc_final_stats_actual.pcs_repcnt = SC_X4_RSLVD7r_REPLICATION_CNTf_GET(reg_resolved_7); 6063 6064 SC_X4_RSLVD8r_CLR(reg_resolved_8); 6065 PHYMOD_IF_ERR_RETURN(READ_SC_X4_RSLVD8r(pc, ®_resolved_8)); 6066 sc_final_stats_actual.pcs_cgc = SC_X4_RSLVD8r_PCS_CREDITGENCNTf_GET(reg_resolved_8); 6067 6068 /* Compare the actual and expected stats */ 6069 fail = 0; 6070 6071 6072 if(pc->sc_mode == TEMOD_SC_MODE_ST) { 6073 if(actual_speed != (pc->per_lane_control >> 8)) 6074 fail = 1; 6075 } else if((pc->per_lane_control & 0xffff) == (0x004 | (TEMOD_SPD_10000_XFI << 8))) { /* DV Verification Only */ 6076 if(actual_speed != digital_operationSpeeds_SPEED_10G_KR1) 6077 fail = 1; 6078 } else if((pc->per_lane_control & 0xffff) == (0x004 | (TEMOD_SPD_10_SGMII << 8))) { /* DV Verification Only */ 6079 if(actual_speed != digital_operationSpeeds_SPEED_10M) 6080 fail = 1; 6081 } else if((pc->per_lane_control & 0xffff) == (0x004 | (TEMOD_SPD_5000_XFI << 8))) { /* DV Verification Only */ 6082 if(actual_speed != digital_operationSpeeds_SPEED_5G_KR1) 6083 fail = 1; 6084 } else { 6085 if(actual_speed != pc->speed) 6086 fail = 1; 6087 } 6088 6089 if(sc_final_stats_actual.num_lanes != pc->num_lanes) 6090 fail = 1; 6091 if(sc_final_stats_actual.t_pma_os_mode != pc->t_pma_os_mode) 6092 fail = 1; 6093 if(sc_final_stats_actual.t_scr_mode != pc->t_scr_mode) 6094 fail = 1; 6095 if(sc_final_stats_actual.fec_en != pc->fec_en) 6096 fail = 1; 6097 if(sc_final_stats_actual.t_encode_mode != pc->t_encode_mode) 6098 fail = 1; 6099 6100 6101 if(pc->cl72_en & 0x08000000) { 6102 if(sc_final_stats_actual.cl72_en != (pc->cl72_en & 0xffff)) 6103 fail = 1; 6104 } 6105 6106 if(sc_final_stats_actual.r_descr1_mode != pc->r_descr1_mode) 6107 fail = 1; 6108 if(sc_final_stats_actual.r_dec1_mode != pc->r_dec1_mode) 6109 fail = 1; 6110 if(sc_final_stats_actual.r_deskew_mode != pc->r_deskew_mode) 6111 fail = 1; 6112 if(sc_final_stats_actual.r_desc2_mode != pc->r_desc2_mode) 6113 fail = 1; 6114 if(sc_final_stats_actual.r_desc2_byte_deletion != pc->r_desc2_byte_deletion) 6115 fail = 1; 6116 if(sc_final_stats_actual.r_dec1_brcm64b66_descr != pc->r_dec1_brcm64b66_descr) 6117 fail = 1; 6118 6119 if(sc_final_stats_actual.cl48_check_end != pc->cl48_check_end) 6120 fail = 1; 6121 if(sc_final_stats_actual.blk_sync_mode != pc->blk_sync_mode) 6122 fail = 1; 6123 if(sc_final_stats_actual.r_reorder_mode != pc->r_reorder_mode) 6124 fail = 1; 6125 if(sc_final_stats_actual.cl36_en != pc->cl36_en) 6126 fail = 1; 6127 6128 if(sc_final_stats_actual.sgmii != pc->sgmii) 6129 fail = 1; 6130 if(sc_final_stats_actual.clkcnt0 != pc->clkcnt0) 6131 fail = 1; 6132 if(sc_final_stats_actual.clkcnt1 != pc->clkcnt1) 6133 fail = 1; 6134 if(sc_final_stats_actual.lpcnt0 != pc->lpcnt0) 6135 fail = 1; 6136 if(sc_final_stats_actual.lpcnt1 != pc->lpcnt1) 6137 fail = 1; 6138 if(sc_final_stats_actual.mac_cgc != pc->mac_cgc) 6139 fail = 1; 6140 if(sc_final_stats_actual.pcs_repcnt != pc->pcs_repcnt) 6141 fail = 1; 6142 if(sc_final_stats_actual.pcs_crdten != pc->pcs_crdten) 6143 fail = 1; 6144 if(sc_final_stats_actual.pcs_clkcnt != pc->pcs_clkcnt) 6145 fail = 1; 6146 if(sc_final_stats_actual.pcs_cgc != pc->pcs_cgc) 6147 fail = 1; 6148 6149 pc->accData = fail; 6150 if(fail == 1) { 6151 #ifdef _DV_TB_ 6152 printf("Actual stats:\n"); 6153 sc_final_stats_actual_tmp = &sc_final_stats_actual; 6154 print_temod_sc_lkup_table(sc_final_stats_actual_tmp); 6155 printf("Expected stats:\n"); 6156 print_temod_sc_lkup_table(pc); 6157 #endif 6158 return PHYMOD_E_FAIL; 6159 } 6160 return PHYMOD_E_NONE; 6161 } 6162 #endif 6163 6164 #ifdef _DV_TB_ 6165 /** 6166 @brief A DV only Tier2 function to initialize the entire PCS 6167 @param pc handle to current TSCE context (#PHYMOD_ST) 6168 @returns The value PHYMOD_E_NONE upon successful completion 6169 @details Per Port PCS Init for forced speeds 6170 */ 6171 int _init_pcs_fs(PHYMOD_ST* pc) 6172 { 6173 uint16_t data; 6174 SC_X4_CTLr_t reg_swmode; 6175 6176 _get_sc_speed_configuration(pc); 6177 _configure_sc_speed_configuration(pc); 6178 6179 /* Set speed */ 6180 if(pc->sc_mode == TEMOD_SC_MODE_ST) 6181 data = (pc->per_lane_control & 0xff00) >> 8; 6182 else if((pc->per_lane_control & 0xffff) == (0x004 | (TEMOD_SPD_10000_XFI << 8))) /* DV Verification Only */ 6183 data = digital_operationSpeeds_SPEED_10G_KR1; 6184 else if((pc->per_lane_control & 0xffff) == (0x004 | (TEMOD_SPD_10_SGMII << 8))) /* DV Verification Only */ 6185 data = digital_operationSpeeds_SPEED_10M; 6186 else if((pc->per_lane_control & 0xffff) == (0x004 | (TEMOD_SPD_5000_XFI << 8))) /* DV Verification Only */ 6187 data = digital_operationSpeeds_SPEED_5G_KR1; 6188 else 6189 data = pc->speed; 6190 6191 SC_X4_CTLr_CLR(reg_swmode); 6192 SC_X4_CTLr_SW_SPEEDf_SET(reg_swmode, data); 6193 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_CTLr(pc, reg_swmode)); 6194 6195 temod_trigger_speed_change(pc); 6196 _temod_wait_sc_stats_set(pc); 6197 6198 return PHYMOD_E_NONE; 6199 } 6200 #endif 6201 6202 6203 #ifdef _DV_TB_ 6204 /** 6205 @brief Initialize the PMD for QSGMII PCS. (different from TSCE PCS) 6206 @param pc handle to current TSCE context (#PHYMOD_ST) 6207 @param pmd_touched Is this the first time we are visiting the PMD. 6208 @param uc_active is the uctlr already active (implies firmware loaded) 6209 @returns The value PHYMOD_E_NONE upon successful completion 6210 @details Details pending. 6211 */ 6212 int temod_init_pmd_qsgmii(PHYMOD_ST* pc, int pmd_touched, int uc_active) /* INIT_PMD_SGMII */ 6213 { 6214 CKRST_LN_CLK_RST_N_PWRDWN_CTLr_t reg_pwr_dwn_ctrl; 6215 DIG_TOP_USER_CTL0r_t reg_usr_ctrl; 6216 PLL_CAL_CTL7r_t reg_ctrl7; 6217 CKRST_OSR_MODE_CTLr_t reg_osr_mode_ctrl; 6218 6219 TEMOD_DBG_IN_FUNC_INFO(pc); 6220 6221 CKRST_LN_CLK_RST_N_PWRDWN_CTLr_CLR(reg_pwr_dwn_ctrl); 6222 CKRST_LN_CLK_RST_N_PWRDWN_CTLr_LN_DP_S_RSTBf_SET(reg_pwr_dwn_ctrl, 1); 6223 PHYMOD_IF_ERR_RETURN(MODIFY_CKRST_LN_CLK_RST_N_PWRDWN_CTLr(pc, reg_pwr_dwn_ctrl)); 6224 6225 if (pmd_touched == 0) { 6226 DIG_TOP_USER_CTL0r_CLR(reg_usr_ctrl); 6227 if(uc_active == 1){ 6228 6229 DIG_TOP_USER_CTL0r_UC_ACTIVEf_SET(reg_usr_ctrl, 1); 6230 DIG_TOP_USER_CTL0r_CORE_DP_S_RSTBf_SET(reg_usr_ctrl, 1); 6231 6232 /* release reset to pll data path. TBD need for all lanes and uc_active set */ 6233 PHYMOD_IF_ERR_RETURN (MODIFY_DIG_TOP_USER_CTL0r(pc, reg_usr_ctrl)); 6234 } 6235 else{ 6236 DIG_TOP_USER_CTL0r_CORE_DP_S_RSTBf_SET(reg_usr_ctrl, 1); 6237 PHYMOD_IF_ERR_RETURN (MODIFY_DIG_TOP_USER_CTL0r(pc, reg_usr_ctrl)); 6238 } 6239 } 6240 6241 /* set vco at 10G */ 6242 PLL_CAL_CTL7r_CLR(reg_ctrl7); 6243 PLL_CAL_CTL7r_PLL_MODEf_SET(reg_ctrl7, 0x9); 6244 PHYMOD_IF_ERR_RETURN (MODIFY_PLL_CAL_CTL7r(pc, reg_ctrl7)); 6245 6246 /* set OS2 mode */ 6247 CKRST_OSR_MODE_CTLr_CLR(reg_osr_mode_ctrl); 6248 CKRST_OSR_MODE_CTLr_OSR_MODE_FRCf_SET(reg_osr_mode_ctrl, 1); 6249 CKRST_OSR_MODE_CTLr_OSR_MODE_FRC_VALf_SET(reg_osr_mode_ctrl, 1); 6250 6251 PHYMOD_IF_ERR_RETURN(MODIFY_CKRST_OSR_MODE_CTLr(pc, reg_osr_mode_ctrl)); 6252 6253 return PHYMOD_E_NONE; 6254 } 6255 #endif /* _DV_TB_ */ 6256 6257 6258 /** 6259 @brief TSC12 DV stuff. Incomplete 6260 @param pc handle to current TSCE context (#PHYMOD_ST) 6261 @param cl82_multi_pipe_mode Multi Mode must be set when a core is part of 100G 6262 @param cl82_mld_phys_map lane allocation for this 100G setup 6263 @returns The value PHYMOD_E_NONE upon successful completion. 6264 @details Called to Configure tsc12 for 100G+ speeds. 6265 For 100/120G you will need to configure the triple-core-set to either have 20 or 24 6266 virtual lanes. Further for 100G you can have 3-4-3 or 2-4-4 or 4-4-2 type usage 6267 of lanes 6268 */ 6269 6270 int temod_tsc12_control(PHYMOD_ST* pc, int cl82_multi_pipe_mode, int cl82_mld_phys_map) /* TSC12_CONTROL */ 6271 { 6272 MAIN0_MISCr_t reg_misc; 6273 TEMOD_DBG_IN_FUNC_INFO(pc); 6274 MAIN0_MISCr_CLR(reg_misc); 6275 PHYMOD_IF_ERR_RETURN (READ_MAIN0_MISCr(pc, ®_misc)); 6276 6277 if(cl82_multi_pipe_mode>=0) { 6278 MAIN0_MISCr_CL82_MULTI_PIPE_MODEf_SET(reg_misc, (cl82_multi_pipe_mode & 0x3)); 6279 } 6280 if(cl82_mld_phys_map>=0) { 6281 MAIN0_MISCr_CL82_MLD_PHYS_MAPf_SET(reg_misc, (cl82_mld_phys_map & 0x3)); 6282 } 6283 6284 PHYMOD_IF_ERR_RETURN (MODIFY_MAIN0_MISCr(pc, reg_misc)); 6285 return PHYMOD_E_NONE; 6286 } 6287 6288 #ifdef _DV_TB_ 6289 /** 6290 @brief Checks to ensure SC has programmed the PCS as expected 6291 @param pc handle to current TSCE context (#PHYMOD_ST) 6292 @returns The value PHYMOD_E_NONE upon successful completion. 6293 @details Called to Configure tsc12 for 100G+ speeds 6294 */ 6295 6296 int temod_check_sc_stats(PHYMOD_ST* pc) /* CHECK_SC_STATS */ 6297 { 6298 uint16_t data ; 6299 6300 TEMOD_DBG_IN_FUNC_INFO(pc); 6301 data = _read_and_compare_final_status(pc); 6302 return PHYMOD_E_NONE; 6303 } 6304 #endif /* _DV_TB_ */ 6305 6306 /** 6307 @brief get the rx lane reset staus for any lane 6308 @param pc handle to current TSCE context (#PHYMOD_ST) 6309 @param value get the status as *value 6310 @returns The value PHYMOD_E_NONE upon successful completion. 6311 @details 6312 This function enables/disables rx lane (RSTB_LANE) or read back control bit for 6313 that based on per_lane_control being 1 or 0. If per_lane_control is 0xa, only 6314 read back RSTB_LANE. 6315 */ 6316 int temod_rx_lane_control_get(PHYMOD_ST* pc, int *value) /* RX_LANE_CONTROL */ 6317 { 6318 RX_X4_PMA_CTL0r_t reg_pma_ctrl; 6319 6320 TEMOD_DBG_IN_FUNC_INFO(pc); 6321 RX_X4_PMA_CTL0r_CLR(reg_pma_ctrl); 6322 6323 PHYMOD_IF_ERR_RETURN (READ_RX_X4_PMA_CTL0r(pc, ®_pma_ctrl)); 6324 if( RX_X4_PMA_CTL0r_RSTB_LANEf_GET(reg_pma_ctrl) ) 6325 *value = 1; 6326 else 6327 *value = 0; 6328 6329 return PHYMOD_E_NONE; 6330 } 6331 6332 6333 /** 6334 @brief rx lane reset and enable of any particular lane 6335 @param pc handle to current TSCE context (#PHYMOD_ST) 6336 @param enable to reset the lane. 6337 @returns The value PHYMOD_E_NONE upon successful completion. 6338 @details This function enables/disables rx lane (RSTB_LANE). 6339 */ 6340 int temod_rx_lane_control_set(PHYMOD_ST* pc, int enable) /* RX_LANE_CONTROL */ 6341 { 6342 RX_X4_PMA_CTL0r_t reg_pma_ctrl; 6343 6344 TEMOD_DBG_IN_FUNC_INFO(pc); 6345 RX_X4_PMA_CTL0r_CLR(reg_pma_ctrl); 6346 if (enable) { 6347 RX_X4_PMA_CTL0r_RSTB_LANEf_SET( reg_pma_ctrl, 0); 6348 PHYMOD_IF_ERR_RETURN (MODIFY_RX_X4_PMA_CTL0r(pc, reg_pma_ctrl)); 6349 RX_X4_PMA_CTL0r_CLR(reg_pma_ctrl); 6350 RX_X4_PMA_CTL0r_RSTB_LANEf_SET(reg_pma_ctrl, 1); 6351 PHYMOD_IF_ERR_RETURN (MODIFY_RX_X4_PMA_CTL0r(pc, reg_pma_ctrl)); 6352 } else { 6353 /* bit set to 0 for disabling RXP */ 6354 RX_X4_PMA_CTL0r_RSTB_LANEf_SET( reg_pma_ctrl, 0); 6355 PHYMOD_IF_ERR_RETURN (MODIFY_RX_X4_PMA_CTL0r(pc, reg_pma_ctrl)); 6356 } 6357 return PHYMOD_E_NONE; 6358 } 6359 6360 #ifdef _DV_TB_ 6361 int temod_prbs_rx_enable_set(PHYMOD_ST* pc, int enable) 6362 { 6363 TLB_RX_PRBS_CHK_CFGr_t reg_prbs_chk_cfg; 6364 6365 TEMOD_DBG_IN_FUNC_INFO(pc); 6366 TLB_RX_PRBS_CHK_CFGr_CLR(reg_prbs_chk_cfg); 6367 6368 TLB_RX_PRBS_CHK_CFGr_PRBS_CHK_ENf_SET(reg_prbs_chk_cfg, enable); 6369 PHYMOD_IF_ERR_RETURN (MODIFY_TLB_RX_PRBS_CHK_CFGr(pc, reg_prbs_chk_cfg)); 6370 6371 return PHYMOD_E_NONE; 6372 } 6373 #endif 6374 6375 #ifdef _DV_TB_ 6376 int temod_prbs_tx_enable_set(PHYMOD_ST* pc, int enable) /* PRBS_MODE */ 6377 { 6378 TLB_TX_PRBS_GEN_CFGr_t reg_prbs_gen_cfg; 6379 6380 TEMOD_DBG_IN_FUNC_INFO(pc); 6381 TLB_TX_PRBS_GEN_CFGr_CLR(reg_prbs_gen_cfg); 6382 6383 TLB_TX_PRBS_GEN_CFGr_PRBS_GEN_ENf_SET(reg_prbs_gen_cfg, enable); 6384 PHYMOD_IF_ERR_RETURN (MODIFY_TLB_TX_PRBS_GEN_CFGr(pc, reg_prbs_gen_cfg)); 6385 6386 return PHYMOD_E_NONE; 6387 6388 } /* PRBS_MODE */ 6389 #endif 6390 6391 #ifdef _DV_TB_ 6392 int temod_prbs_rx_invert_data_set(PHYMOD_ST* pc, int invert_data) /* PRBS_MODE */ 6393 { 6394 TLB_RX_PRBS_CHK_CFGr_t reg_prbs_chk_cfg; 6395 6396 TEMOD_DBG_IN_FUNC_INFO(pc); 6397 TLB_RX_PRBS_CHK_CFGr_CLR(reg_prbs_chk_cfg); 6398 6399 TLB_RX_PRBS_CHK_CFGr_PRBS_CHK_INVf_SET(reg_prbs_chk_cfg, invert_data) ; 6400 PHYMOD_IF_ERR_RETURN (MODIFY_TLB_RX_PRBS_CHK_CFGr(pc, reg_prbs_chk_cfg)); 6401 6402 return PHYMOD_E_NONE; 6403 6404 } /* PRBS_MODE */ 6405 #endif 6406 6407 #ifdef _DV_TB_ 6408 int temod_prbs_rx_check_mode_set(PHYMOD_ST* pc, int check_mode) /* PRBS_MODE */ 6409 { 6410 TLB_RX_PRBS_CHK_CFGr_t reg_prbs_chk_cfg; 6411 6412 TEMOD_DBG_IN_FUNC_INFO(pc); 6413 TLB_RX_PRBS_CHK_CFGr_CLR(reg_prbs_chk_cfg); 6414 6415 TLB_RX_PRBS_CHK_CFGr_PRBS_CHK_MODEf_SET(reg_prbs_chk_cfg, check_mode); 6416 PHYMOD_IF_ERR_RETURN (MODIFY_TLB_RX_PRBS_CHK_CFGr(pc, reg_prbs_chk_cfg)); 6417 6418 return PHYMOD_E_NONE; 6419 6420 } /* PRBS_MODE */ 6421 #endif 6422 6423 #ifdef _DV_TB_ 6424 int temod_prbs_tx_invert_data_set(PHYMOD_ST* pc, int invert_data) /* PRBS_MODE */ 6425 { 6426 TLB_TX_PRBS_GEN_CFGr_t reg_prbs_gen_cfg; 6427 6428 TEMOD_DBG_IN_FUNC_INFO(pc); 6429 TLB_TX_PRBS_GEN_CFGr_CLR(reg_prbs_gen_cfg); 6430 6431 TLB_TX_PRBS_GEN_CFGr_PRBS_GEN_INVf_SET(reg_prbs_gen_cfg, invert_data); 6432 PHYMOD_IF_ERR_RETURN(MODIFY_TLB_TX_PRBS_GEN_CFGr(pc, reg_prbs_gen_cfg)); 6433 6434 return PHYMOD_E_NONE; 6435 6436 } /* PRBS_MODE */ 6437 #endif 6438 6439 #ifdef _DV_TB_ 6440 int temod_prbs_tx_polynomial_set(PHYMOD_ST* pc, eagle_prbs_polynomial_type_t prbs_polynomial) /* PRBS_MODE */ 6441 { 6442 TLB_TX_PRBS_GEN_CFGr_t reg_prbs_gen_cfg; 6443 6444 TEMOD_DBG_IN_FUNC_INFO(pc); 6445 TLB_TX_PRBS_GEN_CFGr_CLR(reg_prbs_gen_cfg); 6446 6447 TLB_TX_PRBS_GEN_CFGr_PRBS_GEN_MODE_SELf_SET(reg_prbs_gen_cfg, prbs_polynomial); 6448 PHYMOD_IF_ERR_RETURN (MODIFY_TLB_TX_PRBS_GEN_CFGr(pc, reg_prbs_gen_cfg)); 6449 6450 return PHYMOD_E_NONE; 6451 6452 } /* PRBS_MODE */ 6453 #endif 6454 6455 #ifdef _DV_TB_ 6456 int temod_prbs_rx_polynomial_set(PHYMOD_ST* pc, eagle_prbs_polynomial_type_t prbs_polynomial) /* PRBS_MODE */ 6457 { 6458 TLB_RX_PRBS_CHK_CFGr_t reg_prbs_chk_cfg; 6459 6460 TEMOD_DBG_IN_FUNC_INFO(pc); 6461 TLB_RX_PRBS_CHK_CFGr_CLR(reg_prbs_chk_cfg); 6462 6463 TLB_RX_PRBS_CHK_CFGr_PRBS_CHK_MODE_SELf_SET(reg_prbs_chk_cfg, prbs_polynomial); 6464 PHYMOD_IF_ERR_RETURN (MODIFY_TLB_RX_PRBS_CHK_CFGr(pc, reg_prbs_chk_cfg)); 6465 6466 return PHYMOD_E_NONE; 6467 6468 } /* PRBS_MODE */ 6469 #endif 6470 6471 /*! 6472 @brief Override the default PCS reset controls on PMD. 6473 @param pc handle to current TSCE context (#PHYMOD_ST) 6474 @param cntl input (see details) 6475 @param value handle to current TSCE context (#PHYMOD_ST) 6476 @returns The value PHYMOD_E_NONE upon successful completion 6477 @details Per Port PMD Override. 6478 Can be enhanced to also configure per core PMD Override 6479 Various bits are enabled as bit encoded by the cntl parameter 6480 \li 0x8000 ln_dp_h_rstb_oen 6481 \li 0x4000 tx_disable_oen 6482 \li 0x2000 rx_dme_en_oen 6483 \li 0x1000 osr_mode_oen 6484 \li 0x0800 lane_mode_oen 6485 \li 0x0400 rx_clk_vld_ovrd 6486 \li 0x0200 signal_detect_ovrd 6487 \li 0x0100 rx_lock_ovrd 6488 */ 6489 int temod_pmd_override_control(PHYMOD_ST* pc, int cntl, int value) /* PMD_OVERRIDE_CONTROL */ 6490 { 6491 PMD_X4_OVRRr_t reg_ovr; 6492 6493 TEMOD_DBG_IN_FUNC_INFO(pc); 6494 PMD_X4_OVRRr_CLR(reg_ovr); 6495 6496 if(cntl & 0x8000) { /* ln_dp_h_rstb_oen */ 6497 PMD_X4_OVRRr_LN_DP_H_RSTB_OENf_SET(reg_ovr,(value & 0x0080) >> 7); 6498 } 6499 if(cntl & 0x4000) { /* tx_disable_oen */ 6500 PMD_X4_OVRRr_TX_DISABLE_OENf_SET(reg_ovr, (value & 0x0040) >> 6); 6501 } 6502 if(cntl & 0x2000) { /* rx_dme_en_oen */ 6503 PMD_X4_OVRRr_RX_DME_EN_OENf_SET (reg_ovr, (value & 0x0020) >> 5); 6504 } 6505 if(cntl & 0x1000) { /* osr_mode_oen */ 6506 PMD_X4_OVRRr_OSR_MODE_OENf_SET (reg_ovr, (value & 0x0010) >> 4); 6507 } 6508 if(cntl & 0x0800) { /* lane_mode_oen */ 6509 PMD_X4_OVRRr_LANE_MODE_OENf_SET (reg_ovr, (value & 0x0008) >> 3); 6510 } 6511 if(cntl & 0x0400) { /* rx_clk_vld_ovrd */ 6512 PMD_X4_OVRRr_RX_CLK_VLD_OVRDf_SET (reg_ovr, (value & 0x0004) >> 2); 6513 } 6514 if(cntl & 0x0200) { /* signal_detect_ovrd */ 6515 PMD_X4_OVRRr_SIGNAL_DETECT_OVRDf_SET (reg_ovr, (value & 0x0002) >> 1); 6516 } 6517 if(cntl & 0x0100) { /* rx_lock_ovrd */ 6518 PMD_X4_OVRRr_RX_LOCK_OVRDf_SET (reg_ovr, (value & 0x0001)); 6519 } 6520 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X4_OVRRr(pc, reg_ovr)); 6521 return PHYMOD_E_NONE; 6522 } 6523 6524 /** 6525 @brief Gets the TX And RX Polarity 6526 @param pc handle to current TSCE context (#PHYMOD_ST) 6527 @param tx_polarity Receive Polarity for TX side 6528 @param rx_polarity Receive Polarity for RX side 6529 @returns The value PHYMOD_E_NONE upon successful completion. 6530 @details Gets the TX And RX Polarity 6531 */ 6532 int temod_tx_rx_polarity_get ( PHYMOD_ST *pc, uint32_t* tx_polarity, uint32_t* rx_polarity) 6533 { 6534 TLB_TX_TLB_TX_MISC_CFGr_t tx_pol_inv; 6535 TLB_RX_TLB_RX_MISC_CFGr_t rx_pol_inv; 6536 6537 PHYMOD_IF_ERR_RETURN(READ_TLB_TX_TLB_TX_MISC_CFGr(pc, &tx_pol_inv)); 6538 *tx_polarity = TLB_TX_TLB_TX_MISC_CFGr_TX_PMD_DP_INVERTf_GET(tx_pol_inv); 6539 6540 PHYMOD_IF_ERR_RETURN(READ_TLB_RX_TLB_RX_MISC_CFGr(pc, &rx_pol_inv)); 6541 *rx_polarity = TLB_RX_TLB_RX_MISC_CFGr_RX_PMD_DP_INVERTf_GET(rx_pol_inv); 6542 6543 return PHYMOD_E_NONE; 6544 } 6545 6546 /** 6547 @brief Sets the TX And RX Polarity 6548 @param pc handle to current TSCE context (#PHYMOD_ST) 6549 @param tx_polarity Control Polarity for TX side 6550 @param rx_polarity Control Polarity for RX side 6551 @returns The value PHYMOD_E_NONE upon successful completion. 6552 @details Sets the TX And RX Polarity 6553 */ 6554 int temod_tx_rx_polarity_set ( PHYMOD_ST *pc, uint32_t tx_polarity, uint32_t rx_polarity) 6555 { 6556 TLB_TX_TLB_TX_MISC_CFGr_t tx_pol_inv; 6557 TLB_RX_TLB_RX_MISC_CFGr_t rx_pol_inv; 6558 6559 TLB_TX_TLB_TX_MISC_CFGr_CLR(tx_pol_inv); 6560 TLB_RX_TLB_RX_MISC_CFGr_CLR(rx_pol_inv); 6561 6562 TLB_TX_TLB_TX_MISC_CFGr_TX_PMD_DP_INVERTf_SET(tx_pol_inv, tx_polarity); 6563 PHYMOD_IF_ERR_RETURN(MODIFY_TLB_TX_TLB_TX_MISC_CFGr(pc, tx_pol_inv)); 6564 6565 TLB_RX_TLB_RX_MISC_CFGr_RX_PMD_DP_INVERTf_SET(rx_pol_inv, rx_polarity); 6566 PHYMOD_IF_ERR_RETURN(MODIFY_TLB_RX_TLB_RX_MISC_CFGr(pc, rx_pol_inv)); 6567 6568 return PHYMOD_E_NONE; 6569 } 6570 6571 /** 6572 @brief Controls port TX/RX squelch 6573 @param pc handle to current TSCE context (#PHYMOD_ST) 6574 @param enable is the control to TX/RX squelch. Enable=1 means enable the port,no squelch 6575 @returns The value PHYMOD_E_NONE upon successful completion. 6576 @details Controls port TX/RX squelch 6577 */ 6578 int temod_port_enable_set(PHYMOD_ST *pc, int enable) 6579 { 6580 if (enable) { 6581 temod_rx_squelch_set(pc, 0); 6582 temod_tx_squelch_set(pc, 0); 6583 } else { 6584 temod_rx_squelch_set(pc, 1); 6585 temod_tx_squelch_set(pc, 1); 6586 } 6587 6588 return PHYMOD_E_NONE; 6589 } 6590 6591 /** 6592 @brief Controls port TX squelch 6593 @param pc handle to current TSCE context (#PHYMOD_ST) 6594 @param enable is the control to TX squelch 6595 @returns The value PHYMOD_E_NONE upon successful completion. 6596 @details Controls port TX squelch 6597 */ 6598 int temod_tx_squelch_set(PHYMOD_ST *pc, int enable) 6599 { 6600 TXFIR_MISC_CTL1r_t tx_misc_ctl; 6601 6602 TXFIR_MISC_CTL1r_CLR(tx_misc_ctl); 6603 READ_TXFIR_MISC_CTL1r(pc, &tx_misc_ctl); 6604 TXFIR_MISC_CTL1r_SDK_TX_DISABLEf_SET(tx_misc_ctl, enable); 6605 PHYMOD_IF_ERR_RETURN(MODIFY_TXFIR_MISC_CTL1r(pc, tx_misc_ctl)); 6606 6607 return PHYMOD_E_NONE; 6608 } 6609 6610 /** 6611 @brief Controls port RX squelch 6612 @param pc handle to current TSCE context (#PHYMOD_ST) 6613 @param enable is the control to RX squelch 6614 @returns The value PHYMOD_E_NONE upon successful completion. 6615 @details Controls port RX squelch 6616 */ 6617 int temod_rx_squelch_set(PHYMOD_ST *pc, int enable) 6618 { 6619 SIGDET_CTL1r_t sigdet_ctl; 6620 6621 SIGDET_CTL1r_CLR(sigdet_ctl); 6622 READ_SIGDET_CTL1r(pc, &sigdet_ctl); 6623 if(enable){ 6624 SIGDET_CTL1r_SIGNAL_DETECT_FRCf_SET(sigdet_ctl, 1); 6625 SIGDET_CTL1r_SIGNAL_DETECT_FRC_VALf_SET(sigdet_ctl, 0); 6626 } else { 6627 SIGDET_CTL1r_SIGNAL_DETECT_FRCf_SET(sigdet_ctl, 0); 6628 SIGDET_CTL1r_SIGNAL_DETECT_FRC_VALf_SET(sigdet_ctl, 0); 6629 } 6630 PHYMOD_IF_ERR_RETURN(MODIFY_SIGDET_CTL1r(pc, sigdet_ctl)); 6631 6632 return PHYMOD_E_NONE; 6633 } 6634 6635 /** 6636 @brief Get port TX/RX squelch Settings 6637 @param pc handle to current TSCE context (#PHYMOD_ST) 6638 @param tx_enable - get the TX squelch settings 6639 @param rx_enable - get the RX squelch settings 6640 @returns The value PHYMOD_E_NONE upon successful completion. 6641 @details Controls port TX/RX squelch 6642 */ 6643 int temod_port_enable_get(PHYMOD_ST *pc, int *tx_enable, int *rx_enable) 6644 { 6645 6646 temod_rx_squelch_get(pc, rx_enable); 6647 temod_tx_squelch_get(pc, tx_enable); 6648 6649 return PHYMOD_E_NONE; 6650 } 6651 6652 /** 6653 @brief Get port TX squelch control settings 6654 @param pc handle to current TSCE context (#PHYMOD_ST) 6655 @param val Receiver for status of TX squelch 6656 @returns The value PHYMOD_E_NONE upon successful completion. 6657 @details Get port TX squelch control settings 6658 */ 6659 int temod_tx_squelch_get(PHYMOD_ST *pc, int *val) 6660 { 6661 TXFIR_MISC_CTL1r_t tx_misc_ctl; 6662 6663 TXFIR_MISC_CTL1r_CLR(tx_misc_ctl); 6664 6665 PHYMOD_IF_ERR_RETURN(READ_TXFIR_MISC_CTL1r(pc, &tx_misc_ctl)); 6666 *val = TXFIR_MISC_CTL1r_SDK_TX_DISABLEf_GET(tx_misc_ctl); 6667 6668 return PHYMOD_E_NONE; 6669 } 6670 6671 /** 6672 @brief Gets port RX squelch settings 6673 @param pc handle to current TSCE context (#PHYMOD_ST) 6674 @param val Receiver for status of RX squelch 6675 @returns The value PHYMOD_E_NONE upon successful completion. 6676 @details Gets port RX squelch settings 6677 */ 6678 int temod_rx_squelch_get(PHYMOD_ST *pc, int *val) 6679 { 6680 SIGDET_CTL1r_t sigdet_ctl; 6681 6682 SIGDET_CTL1r_CLR(sigdet_ctl); 6683 6684 PHYMOD_IF_ERR_RETURN(READ_SIGDET_CTL1r(pc, &sigdet_ctl)); 6685 *val = SIGDET_CTL1r_SIGNAL_DETECT_FRCf_GET(sigdet_ctl); 6686 6687 return PHYMOD_E_NONE; 6688 } 6689 6690 /** 6691 @brief Sets the field of the Soft Table 6692 @param pc handle to current TSCE context (#PHYMOD_ST) 6693 @param st_entry_no: The ST to write to(0..3) 6694 @param st_control_field: Reference to the ST override field #override_type_t 6695 @param st_field_value: The ST value to write to the field 6696 returns The value PHYMOD_E_NONE upon successful completion. 6697 @details Sets the field of the Soft Table 6698 */ 6699 int temod_st_control_field_set (PHYMOD_ST* pc,uint16_t st_entry_no, override_type_t st_control_field, uint16_t st_field_value){ 6700 6701 SC_X1_SPD_OVRR0_SPDr_t reg0_ovr_spd; 6702 SC_X1_SPD_OVRR0_0r_t reg0_ovr; 6703 SC_X1_SPD_OVRR0_1r_t reg0_ovr1; 6704 SC_X1_SPD_OVRR0_2r_t reg0_ovr2; 6705 6706 SC_X1_SPD_OVRR1_SPDr_t reg1_ovr_spd; 6707 SC_X1_SPD_OVRR1_0r_t reg1_ovr; 6708 SC_X1_SPD_OVRR1_1r_t reg1_ovr1; 6709 SC_X1_SPD_OVRR1_2r_t reg1_ovr2; 6710 6711 SC_X1_SPD_OVRR2_SPDr_t reg2_ovr_spd; 6712 SC_X1_SPD_OVRR2_0r_t reg2_ovr; 6713 SC_X1_SPD_OVRR2_1r_t reg2_ovr1; 6714 SC_X1_SPD_OVRR2_2r_t reg2_ovr2; 6715 6716 SC_X1_SPD_OVRR3_SPDr_t reg3_ovr_spd; 6717 SC_X1_SPD_OVRR3_0r_t reg3_ovr; 6718 SC_X1_SPD_OVRR3_1r_t reg3_ovr1; 6719 SC_X1_SPD_OVRR3_2r_t reg3_ovr2; 6720 6721 SC_X1_SPD_OVRR0_SPDr_CLR(reg0_ovr_spd); 6722 SC_X1_SPD_OVRR0_0r_CLR(reg0_ovr); 6723 SC_X1_SPD_OVRR0_1r_CLR(reg0_ovr1); 6724 SC_X1_SPD_OVRR0_2r_CLR(reg0_ovr2); 6725 6726 SC_X1_SPD_OVRR1_SPDr_CLR(reg1_ovr_spd); 6727 SC_X1_SPD_OVRR1_0r_CLR(reg1_ovr); 6728 SC_X1_SPD_OVRR1_1r_CLR(reg1_ovr1); 6729 SC_X1_SPD_OVRR1_2r_CLR(reg1_ovr2); 6730 6731 SC_X1_SPD_OVRR2_SPDr_CLR(reg2_ovr_spd); 6732 SC_X1_SPD_OVRR2_0r_CLR(reg2_ovr); 6733 SC_X1_SPD_OVRR2_1r_CLR(reg2_ovr1); 6734 SC_X1_SPD_OVRR2_2r_CLR(reg2_ovr2); 6735 6736 SC_X1_SPD_OVRR3_SPDr_CLR(reg3_ovr_spd); 6737 SC_X1_SPD_OVRR3_0r_CLR(reg3_ovr); 6738 SC_X1_SPD_OVRR3_1r_CLR(reg3_ovr1); 6739 SC_X1_SPD_OVRR3_2r_CLR(reg3_ovr2); 6740 6741 switch(st_control_field) { 6742 case TEMOD_OVERRIDE_RESET : 6743 /* CLear the table entry */ 6744 break; 6745 case TEMOD_OVERRIDE_ALL : 6746 /* NA */ 6747 break; 6748 case TEMOD_OVERRIDE_SPDID : 6749 switch(st_entry_no){ 6750 case 0: SC_X1_SPD_OVRR0_SPDr_SPEEDf_SET(reg0_ovr_spd, st_field_value); 6751 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_SPDr(pc, reg0_ovr_spd)); 6752 break; 6753 case 1: SC_X1_SPD_OVRR1_SPDr_SPEEDf_SET(reg1_ovr_spd, st_field_value); 6754 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_SPDr(pc, reg1_ovr_spd)); 6755 break; 6756 case 2: SC_X1_SPD_OVRR2_SPDr_SPEEDf_SET(reg2_ovr_spd, st_field_value); 6757 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_SPDr(pc, reg2_ovr_spd)); 6758 break; 6759 case 3: SC_X1_SPD_OVRR3_SPDr_SPEEDf_SET(reg3_ovr_spd, st_field_value); 6760 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_SPDr(pc, reg3_ovr_spd)); 6761 break; 6762 } 6763 break; 6764 case TEMOD_OVERRIDE_CL72 : 6765 switch(st_entry_no){ 6766 case 0: SC_X1_SPD_OVRR0_0r_CL72_ENABLEf_SET(reg0_ovr, st_field_value); 6767 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_0r(pc, reg0_ovr)); 6768 break; 6769 case 1: SC_X1_SPD_OVRR1_0r_CL72_ENABLEf_SET(reg1_ovr, st_field_value); 6770 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_0r(pc, reg1_ovr)); 6771 break; 6772 case 2: SC_X1_SPD_OVRR2_0r_CL72_ENABLEf_SET(reg2_ovr, st_field_value); 6773 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_0r(pc, reg2_ovr)); 6774 break; 6775 case 3: SC_X1_SPD_OVRR3_0r_CL72_ENABLEf_SET(reg3_ovr, st_field_value); 6776 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_0r(pc, reg3_ovr)); 6777 break; 6778 } 6779 break; 6780 case TEMOD_OVERRIDE_NUM_LANES : 6781 switch(st_entry_no){ 6782 case 0: SC_X1_SPD_OVRR0_SPDr_NUM_LANESf_SET(reg0_ovr_spd, st_field_value); 6783 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_SPDr(pc, reg0_ovr_spd)); 6784 break; 6785 case 1: SC_X1_SPD_OVRR1_SPDr_NUM_LANESf_SET(reg1_ovr_spd, st_field_value); 6786 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_SPDr(pc, reg1_ovr_spd)); 6787 break; 6788 case 2: SC_X1_SPD_OVRR2_SPDr_NUM_LANESf_SET(reg2_ovr_spd, st_field_value); 6789 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_SPDr(pc, reg2_ovr_spd)); 6790 break; 6791 case 3: SC_X1_SPD_OVRR3_SPDr_NUM_LANESf_SET(reg3_ovr_spd, st_field_value); 6792 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_SPDr(pc, reg3_ovr_spd)); 6793 break; 6794 } 6795 break; 6796 case TEMOD_OVERRIDE_OS_MODE: 6797 switch(st_entry_no){ 6798 case 0: SC_X1_SPD_OVRR0_0r_OS_MODEf_SET(reg0_ovr, st_field_value); 6799 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_0r(pc, reg0_ovr)); 6800 break; 6801 case 1: SC_X1_SPD_OVRR1_0r_OS_MODEf_SET(reg1_ovr, st_field_value); 6802 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_0r(pc, reg1_ovr)); 6803 break; 6804 case 2: SC_X1_SPD_OVRR2_0r_OS_MODEf_SET(reg2_ovr, st_field_value); 6805 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_0r(pc, reg2_ovr)); 6806 break; 6807 case 3: SC_X1_SPD_OVRR3_0r_OS_MODEf_SET(reg3_ovr, st_field_value); 6808 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_0r(pc, reg3_ovr)); 6809 break; 6810 } 6811 break; 6812 case TEMOD_OVERRIDE_FEC_EN : 6813 switch(st_entry_no){ 6814 case 0: SC_X1_SPD_OVRR0_0r_FEC_ENABLEf_SET(reg0_ovr, st_field_value); 6815 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_0r(pc, reg0_ovr)); 6816 break; 6817 case 1: SC_X1_SPD_OVRR1_0r_FEC_ENABLEf_SET(reg1_ovr, st_field_value); 6818 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_0r(pc, reg1_ovr)); 6819 break; 6820 case 2: SC_X1_SPD_OVRR2_0r_FEC_ENABLEf_SET(reg2_ovr, st_field_value); 6821 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_0r(pc, reg2_ovr)); 6822 break; 6823 case 3: SC_X1_SPD_OVRR3_0r_FEC_ENABLEf_SET(reg3_ovr, st_field_value); 6824 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_0r(pc, reg3_ovr)); 6825 break; 6826 } 6827 break; 6828 case TEMOD_OVERRIDE_DESKEW_MODE: 6829 switch(st_entry_no){ 6830 case 0: SC_X1_SPD_OVRR0_1r_DESKEWMODEf_SET(reg0_ovr1, st_field_value); 6831 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_1r(pc, reg0_ovr1)); 6832 break; 6833 case 1: SC_X1_SPD_OVRR1_1r_DESKEWMODEf_SET(reg1_ovr1, st_field_value); 6834 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_1r(pc, reg1_ovr1)); 6835 break; 6836 case 2: SC_X1_SPD_OVRR2_1r_DESKEWMODEf_SET(reg2_ovr1, st_field_value); 6837 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_1r(pc, reg2_ovr1)); 6838 break; 6839 case 3: SC_X1_SPD_OVRR3_1r_DESKEWMODEf_SET(reg3_ovr1, st_field_value); 6840 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_1r(pc, reg3_ovr1)); 6841 break; 6842 } 6843 break; 6844 case TEMOD_OVERRIDE_DESC2_MODE : 6845 switch(st_entry_no){ 6846 case 0: SC_X1_SPD_OVRR0_1r_DESC2_MODEf_SET(reg0_ovr1, st_field_value); 6847 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_1r(pc, reg0_ovr1)); 6848 break; 6849 case 1: SC_X1_SPD_OVRR1_1r_DESC2_MODEf_SET(reg1_ovr1, st_field_value); 6850 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_1r(pc, reg1_ovr1)); 6851 break; 6852 case 2: SC_X1_SPD_OVRR2_1r_DESC2_MODEf_SET(reg2_ovr1, st_field_value); 6853 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_1r(pc, reg2_ovr1)); 6854 break; 6855 case 3: SC_X1_SPD_OVRR3_1r_DESC2_MODEf_SET(reg3_ovr1, st_field_value); 6856 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_1r(pc, reg3_ovr1)); 6857 break; 6858 } 6859 break; 6860 case TEMOD_OVERRIDE_CL36BYTEDEL_MODE: 6861 switch(st_entry_no){ 6862 case 0: SC_X1_SPD_OVRR0_1r_CL36BYTEDELETEMODEf_SET(reg0_ovr1, st_field_value); 6863 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_1r(pc, reg0_ovr1)); 6864 break; 6865 case 1: SC_X1_SPD_OVRR1_1r_CL36BYTEDELETEMODEf_SET(reg1_ovr1, st_field_value); 6866 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_1r(pc, reg1_ovr1)); 6867 break; 6868 case 2: SC_X1_SPD_OVRR2_1r_CL36BYTEDELETEMODEf_SET(reg2_ovr1, st_field_value); 6869 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_1r(pc, reg2_ovr1)); 6870 break; 6871 case 3: SC_X1_SPD_OVRR3_1r_CL36BYTEDELETEMODEf_SET(reg3_ovr1, st_field_value); 6872 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_1r(pc, reg3_ovr1)); 6873 break; 6874 } 6875 break; 6876 case TEMOD_OVERRIDE_BRCM64B66_DESCR_MODE: 6877 switch(st_entry_no){ 6878 case 0: SC_X1_SPD_OVRR0_1r_BRCM64B66_DESCRAMBLER_ENABLEf_SET(reg0_ovr1, st_field_value); 6879 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_1r(pc, reg0_ovr1)); 6880 break; 6881 case 1: SC_X1_SPD_OVRR1_1r_BRCM64B66_DESCRAMBLER_ENABLEf_SET(reg1_ovr1, st_field_value); 6882 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_1r(pc, reg1_ovr1)); 6883 break; 6884 case 2: SC_X1_SPD_OVRR2_1r_BRCM64B66_DESCRAMBLER_ENABLEf_SET(reg2_ovr1, st_field_value); 6885 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_1r(pc, reg2_ovr1)); 6886 break; 6887 case 3: SC_X1_SPD_OVRR3_1r_BRCM64B66_DESCRAMBLER_ENABLEf_SET(reg3_ovr1, st_field_value); 6888 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_1r(pc, reg3_ovr1)); 6889 break; 6890 } 6891 break; 6892 case TEMOD_OVERRIDE_CHKEND_EN: 6893 switch(st_entry_no){ 6894 case 0: SC_X1_SPD_OVRR0_2r_CHK_END_ENf_SET(reg0_ovr2, st_field_value); 6895 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_2r(pc, reg0_ovr2)); 6896 break; 6897 case 1: SC_X1_SPD_OVRR1_2r_CHK_END_ENf_SET(reg1_ovr2, st_field_value); 6898 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_2r(pc, reg1_ovr2)); 6899 break; 6900 case 2: SC_X1_SPD_OVRR2_2r_CHK_END_ENf_SET(reg2_ovr2, st_field_value); 6901 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_2r(pc, reg2_ovr2)); 6902 break; 6903 case 3: SC_X1_SPD_OVRR3_2r_CHK_END_ENf_SET(reg3_ovr2, st_field_value); 6904 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_2r(pc, reg3_ovr2)); 6905 break; 6906 } 6907 break; 6908 case TEMOD_OVERRIDE_BLKSYNC_MODE: 6909 switch(st_entry_no){ 6910 case 0: SC_X1_SPD_OVRR0_2r_BLOCK_SYNC_MODEf_SET(reg0_ovr2, st_field_value); 6911 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_2r(pc, reg0_ovr2)); 6912 break; 6913 case 1: SC_X1_SPD_OVRR1_2r_BLOCK_SYNC_MODEf_SET(reg1_ovr2, st_field_value); 6914 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_2r(pc, reg1_ovr2)); 6915 break; 6916 case 2: SC_X1_SPD_OVRR2_2r_BLOCK_SYNC_MODEf_SET(reg2_ovr2, st_field_value); 6917 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_2r(pc, reg2_ovr2)); 6918 break; 6919 case 3: SC_X1_SPD_OVRR3_2r_BLOCK_SYNC_MODEf_SET(reg3_ovr2, st_field_value); 6920 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_2r(pc, reg3_ovr2)); 6921 break; 6922 } 6923 break; 6924 case TEMOD_OVERRIDE_REORDER_EN : 6925 switch(st_entry_no){ 6926 case 0: SC_X1_SPD_OVRR0_2r_REORDER_ENf_SET(reg0_ovr2, st_field_value); 6927 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_2r(pc, reg0_ovr2)); 6928 break; 6929 case 1: SC_X1_SPD_OVRR1_2r_REORDER_ENf_SET(reg1_ovr2, st_field_value); 6930 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_2r(pc, reg1_ovr2)); 6931 break; 6932 case 2: SC_X1_SPD_OVRR2_2r_REORDER_ENf_SET(reg2_ovr2, st_field_value); 6933 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_2r(pc, reg2_ovr2)); 6934 break; 6935 case 3: SC_X1_SPD_OVRR3_2r_REORDER_ENf_SET(reg3_ovr2, st_field_value); 6936 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_2r(pc, reg3_ovr2)); 6937 break; 6938 } 6939 break; 6940 case TEMOD_OVERRIDE_CL36_EN: 6941 switch(st_entry_no){ 6942 case 0: SC_X1_SPD_OVRR0_2r_CL36_ENf_SET(reg0_ovr2, st_field_value); 6943 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_2r(pc, reg0_ovr2)); 6944 break; 6945 case 1: SC_X1_SPD_OVRR1_2r_CL36_ENf_SET(reg1_ovr2, st_field_value); 6946 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_2r(pc, reg1_ovr2)); 6947 break; 6948 case 2: SC_X1_SPD_OVRR2_2r_CL36_ENf_SET(reg2_ovr2, st_field_value); 6949 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_2r(pc, reg2_ovr2)); 6950 break; 6951 case 3: SC_X1_SPD_OVRR3_2r_CL36_ENf_SET(reg3_ovr2, st_field_value); 6952 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_2r(pc, reg3_ovr2)); 6953 break; 6954 } 6955 6956 break; 6957 case TEMOD_OVERRIDE_SCR_MODE: 6958 switch(st_entry_no){ 6959 case 0: SC_X1_SPD_OVRR0_0r_SCR_MODEf_SET(reg0_ovr, st_field_value); 6960 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_0r(pc, reg0_ovr)); 6961 break; 6962 case 1: SC_X1_SPD_OVRR1_0r_SCR_MODEf_SET(reg1_ovr, st_field_value); 6963 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_0r(pc, reg1_ovr)); 6964 break; 6965 case 2: SC_X1_SPD_OVRR2_0r_SCR_MODEf_SET(reg2_ovr, st_field_value); 6966 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_0r(pc, reg2_ovr)); 6967 break; 6968 case 3: SC_X1_SPD_OVRR3_0r_SCR_MODEf_SET(reg3_ovr, st_field_value); 6969 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_0r(pc, reg3_ovr)); 6970 break; 6971 } 6972 break; 6973 case TEMOD_OVERRIDE_DESCR_MODE: 6974 switch(st_entry_no){ 6975 case 0: SC_X1_SPD_OVRR0_1r_DESCRAMBLERMODEf_SET(reg0_ovr1, st_field_value); 6976 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_1r(pc, reg0_ovr1)); 6977 break; 6978 case 1: SC_X1_SPD_OVRR1_1r_DESCRAMBLERMODEf_SET(reg1_ovr1, st_field_value); 6979 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_1r(pc, reg1_ovr1)); 6980 break; 6981 case 2: SC_X1_SPD_OVRR2_1r_DESCRAMBLERMODEf_SET(reg2_ovr1, st_field_value); 6982 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_1r(pc, reg2_ovr1)); 6983 break; 6984 case 3: SC_X1_SPD_OVRR3_1r_DESCRAMBLERMODEf_SET(reg3_ovr1, st_field_value); 6985 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_1r(pc, reg3_ovr1)); 6986 break; 6987 } 6988 break; 6989 case TEMOD_OVERRIDE_ENCODE_MODE: 6990 switch(st_entry_no){ 6991 case 0: SC_X1_SPD_OVRR0_0r_ENCODEMODEf_SET(reg0_ovr, st_field_value); 6992 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_0r(pc, reg0_ovr)); 6993 break; 6994 case 1: SC_X1_SPD_OVRR1_0r_ENCODEMODEf_SET(reg1_ovr, st_field_value); 6995 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_0r(pc, reg1_ovr)); 6996 break; 6997 case 2: SC_X1_SPD_OVRR2_0r_ENCODEMODEf_SET(reg2_ovr, st_field_value); 6998 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_0r(pc, reg2_ovr)); 6999 break; 7000 case 3: SC_X1_SPD_OVRR3_0r_ENCODEMODEf_SET(reg3_ovr, st_field_value); 7001 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_0r(pc, reg3_ovr)); 7002 break; 7003 } 7004 7005 break; 7006 case TEMOD_OVERRIDE_DECODE_MODE: 7007 switch(st_entry_no){ 7008 case 0: SC_X1_SPD_OVRR0_1r_DECODERMODEf_SET(reg0_ovr1, st_field_value); 7009 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_1r(pc, reg0_ovr1)); 7010 break; 7011 case 1: SC_X1_SPD_OVRR1_1r_DECODERMODEf_SET(reg1_ovr1, st_field_value); 7012 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_1r(pc, reg1_ovr1)); 7013 break; 7014 case 2: SC_X1_SPD_OVRR2_1r_DECODERMODEf_SET(reg2_ovr1, st_field_value); 7015 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_1r(pc, reg2_ovr1)); 7016 break; 7017 case 3: SC_X1_SPD_OVRR3_1r_DECODERMODEf_SET(reg3_ovr1, st_field_value); 7018 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_1r(pc, reg3_ovr1)); 7019 break; 7020 } 7021 break; 7022 } 7023 7024 return PHYMOD_E_NONE; 7025 7026 } 7027 7028 /** 7029 @brief Gets the field of the Soft Table 7030 @param pc handle to current TSCE context (#PHYMOD_ST) 7031 @param st_entry_no The ST to write to(0..3) 7032 @param st_control_field The ST field of enum override_type_t 7033 @param st_field_value The handle to ST field value 7034 returns The value PHYMOD_E_NONE upon successful completion. 7035 @details Gets the field of the Soft Table 7036 */ 7037 int temod_st_control_field_get (PHYMOD_ST* pc,uint16_t st_entry_no, override_type_t st_control_field, uint16_t *st_field_value){ 7038 7039 SC_X1_SPD_OVRR0_SPDr_t reg0_ovr_spd; 7040 SC_X1_SPD_OVRR0_0r_t reg0_ovr; 7041 SC_X1_SPD_OVRR0_1r_t reg0_ovr1; 7042 SC_X1_SPD_OVRR0_2r_t reg0_ovr2; 7043 7044 SC_X1_SPD_OVRR1_SPDr_t reg1_ovr_spd; 7045 SC_X1_SPD_OVRR1_0r_t reg1_ovr; 7046 SC_X1_SPD_OVRR1_1r_t reg1_ovr1; 7047 SC_X1_SPD_OVRR1_2r_t reg1_ovr2; 7048 7049 SC_X1_SPD_OVRR2_SPDr_t reg2_ovr_spd; 7050 SC_X1_SPD_OVRR2_0r_t reg2_ovr; 7051 SC_X1_SPD_OVRR2_1r_t reg2_ovr1; 7052 SC_X1_SPD_OVRR2_2r_t reg2_ovr2; 7053 7054 SC_X1_SPD_OVRR3_SPDr_t reg3_ovr_spd; 7055 SC_X1_SPD_OVRR3_0r_t reg3_ovr; 7056 SC_X1_SPD_OVRR3_1r_t reg3_ovr1; 7057 SC_X1_SPD_OVRR3_2r_t reg3_ovr2; 7058 7059 SC_X1_SPD_OVRR0_SPDr_CLR(reg0_ovr_spd); 7060 SC_X1_SPD_OVRR0_0r_CLR(reg0_ovr); 7061 SC_X1_SPD_OVRR0_1r_CLR(reg0_ovr1); 7062 SC_X1_SPD_OVRR0_2r_CLR(reg0_ovr2); 7063 7064 SC_X1_SPD_OVRR1_SPDr_CLR(reg1_ovr_spd); 7065 SC_X1_SPD_OVRR1_0r_CLR(reg1_ovr); 7066 SC_X1_SPD_OVRR1_1r_CLR(reg1_ovr1); 7067 SC_X1_SPD_OVRR1_2r_CLR(reg1_ovr2); 7068 7069 SC_X1_SPD_OVRR2_SPDr_CLR(reg2_ovr_spd); 7070 SC_X1_SPD_OVRR2_0r_CLR(reg2_ovr); 7071 SC_X1_SPD_OVRR2_1r_CLR(reg2_ovr1); 7072 SC_X1_SPD_OVRR2_2r_CLR(reg2_ovr2); 7073 7074 SC_X1_SPD_OVRR3_SPDr_CLR(reg3_ovr_spd); 7075 SC_X1_SPD_OVRR3_0r_CLR(reg3_ovr); 7076 SC_X1_SPD_OVRR3_1r_CLR(reg3_ovr1); 7077 SC_X1_SPD_OVRR3_2r_CLR(reg3_ovr2); 7078 7079 switch(st_control_field) { 7080 case TEMOD_OVERRIDE_RESET : 7081 /* CLear the table entry */ 7082 break; 7083 case TEMOD_OVERRIDE_ALL : 7084 /* NA */ 7085 break; 7086 case TEMOD_OVERRIDE_SPDID : 7087 switch(st_entry_no){ 7088 case 0: 7089 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR0_SPDr(pc, ®0_ovr_spd)); 7090 *st_field_value = SC_X1_SPD_OVRR0_SPDr_SPEEDf_GET(reg0_ovr_spd); 7091 break; 7092 case 1: 7093 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR1_SPDr(pc, ®1_ovr_spd)); 7094 *st_field_value = SC_X1_SPD_OVRR1_SPDr_SPEEDf_GET(reg1_ovr_spd); 7095 break; 7096 case 2: 7097 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR2_SPDr(pc, ®2_ovr_spd)); 7098 *st_field_value = SC_X1_SPD_OVRR2_SPDr_SPEEDf_GET(reg2_ovr_spd); 7099 break; 7100 case 3: 7101 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR3_SPDr(pc, ®3_ovr_spd)); 7102 *st_field_value = SC_X1_SPD_OVRR3_SPDr_SPEEDf_GET(reg3_ovr_spd); 7103 break; 7104 } 7105 break; 7106 case TEMOD_OVERRIDE_CL72 : 7107 switch(st_entry_no){ 7108 case 0: 7109 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR0_0r(pc, ®0_ovr)); 7110 *st_field_value = SC_X1_SPD_OVRR0_0r_CL72_ENABLEf_GET(reg0_ovr); 7111 break; 7112 case 1: 7113 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR1_0r(pc, ®1_ovr)); 7114 *st_field_value = SC_X1_SPD_OVRR1_0r_CL72_ENABLEf_GET(reg1_ovr); 7115 break; 7116 case 2: 7117 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR2_0r(pc, ®2_ovr)); 7118 *st_field_value = SC_X1_SPD_OVRR2_0r_CL72_ENABLEf_GET(reg2_ovr); 7119 break; 7120 case 3: 7121 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR3_0r(pc, ®3_ovr)); 7122 *st_field_value = SC_X1_SPD_OVRR3_0r_CL72_ENABLEf_GET(reg3_ovr); 7123 break; 7124 } 7125 break; 7126 case TEMOD_OVERRIDE_NUM_LANES : 7127 switch(st_entry_no){ 7128 case 0: 7129 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR0_SPDr(pc, ®0_ovr_spd)); 7130 *st_field_value = SC_X1_SPD_OVRR0_SPDr_NUM_LANESf_GET(reg0_ovr_spd); 7131 break; 7132 case 1: 7133 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR1_SPDr(pc, ®1_ovr_spd)); 7134 *st_field_value = SC_X1_SPD_OVRR1_SPDr_NUM_LANESf_GET(reg1_ovr_spd); 7135 break; 7136 case 2: 7137 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR2_SPDr(pc, ®2_ovr_spd)); 7138 *st_field_value = SC_X1_SPD_OVRR2_SPDr_NUM_LANESf_GET(reg2_ovr_spd); 7139 break; 7140 case 3: 7141 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR3_SPDr(pc, ®3_ovr_spd)); 7142 *st_field_value = SC_X1_SPD_OVRR3_SPDr_NUM_LANESf_GET(reg3_ovr_spd); 7143 break; 7144 } 7145 break; 7146 case TEMOD_OVERRIDE_OS_MODE: 7147 switch(st_entry_no){ 7148 case 0: 7149 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR0_0r(pc, ®0_ovr)); 7150 *st_field_value = SC_X1_SPD_OVRR0_0r_OS_MODEf_GET(reg0_ovr); 7151 break; 7152 case 1: 7153 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR1_0r(pc, ®1_ovr)); 7154 *st_field_value = SC_X1_SPD_OVRR1_0r_OS_MODEf_GET(reg1_ovr); 7155 break; 7156 case 2: 7157 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR2_0r(pc, ®2_ovr)); 7158 *st_field_value = SC_X1_SPD_OVRR2_0r_OS_MODEf_GET(reg2_ovr); 7159 break; 7160 case 3: 7161 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR3_0r(pc, ®3_ovr)); 7162 *st_field_value = SC_X1_SPD_OVRR3_0r_OS_MODEf_GET(reg3_ovr); 7163 break; 7164 } 7165 break; 7166 case TEMOD_OVERRIDE_FEC_EN : 7167 switch(st_entry_no){ 7168 case 0: 7169 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR0_0r(pc, ®0_ovr)); 7170 *st_field_value = SC_X1_SPD_OVRR0_0r_FEC_ENABLEf_GET(reg0_ovr); 7171 break; 7172 case 1: 7173 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR1_0r(pc, ®1_ovr)); 7174 *st_field_value = SC_X1_SPD_OVRR1_0r_FEC_ENABLEf_GET(reg1_ovr); 7175 break; 7176 case 2: 7177 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR2_0r(pc, ®2_ovr)); 7178 *st_field_value = SC_X1_SPD_OVRR2_0r_FEC_ENABLEf_GET(reg2_ovr); 7179 break; 7180 case 3: 7181 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR3_0r(pc, ®3_ovr)); 7182 *st_field_value = SC_X1_SPD_OVRR3_0r_FEC_ENABLEf_GET(reg3_ovr); 7183 break; 7184 } 7185 break; 7186 case TEMOD_OVERRIDE_DESKEW_MODE: 7187 switch(st_entry_no){ 7188 case 0: 7189 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR0_1r(pc, ®0_ovr1)); 7190 *st_field_value = SC_X1_SPD_OVRR0_1r_DESKEWMODEf_GET(reg0_ovr1); 7191 break; 7192 case 1: 7193 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR1_1r(pc, ®1_ovr1)); 7194 *st_field_value = SC_X1_SPD_OVRR1_1r_DESKEWMODEf_GET(reg1_ovr1); 7195 break; 7196 case 2: 7197 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR2_1r(pc, ®2_ovr1)); 7198 *st_field_value = SC_X1_SPD_OVRR2_1r_DESKEWMODEf_GET(reg2_ovr1); 7199 break; 7200 case 3: 7201 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR3_1r(pc, ®3_ovr1)); 7202 *st_field_value = SC_X1_SPD_OVRR3_1r_DESKEWMODEf_GET(reg3_ovr1); 7203 break; 7204 } 7205 break; 7206 case TEMOD_OVERRIDE_DESC2_MODE : 7207 switch(st_entry_no){ 7208 case 0: 7209 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR0_1r(pc, ®0_ovr1)); 7210 *st_field_value = SC_X1_SPD_OVRR0_1r_DESC2_MODEf_GET(reg0_ovr1); 7211 break; 7212 case 1: 7213 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR1_1r(pc, ®1_ovr1)); 7214 *st_field_value = SC_X1_SPD_OVRR1_1r_DESC2_MODEf_GET(reg1_ovr1); 7215 break; 7216 case 2: 7217 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR2_1r(pc, ®2_ovr1)); 7218 *st_field_value = SC_X1_SPD_OVRR2_1r_DESC2_MODEf_GET(reg2_ovr1); 7219 break; 7220 case 3: 7221 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR3_1r(pc, ®3_ovr1)); 7222 *st_field_value = SC_X1_SPD_OVRR3_1r_DESC2_MODEf_GET(reg3_ovr1); 7223 break; 7224 } 7225 break; 7226 case TEMOD_OVERRIDE_CL36BYTEDEL_MODE: 7227 switch(st_entry_no){ 7228 case 0: 7229 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR0_1r(pc, ®0_ovr1)); 7230 *st_field_value = SC_X1_SPD_OVRR0_1r_CL36BYTEDELETEMODEf_GET(reg0_ovr1); 7231 break; 7232 case 1: 7233 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR1_1r(pc, ®1_ovr1)); 7234 *st_field_value = SC_X1_SPD_OVRR1_1r_CL36BYTEDELETEMODEf_GET(reg1_ovr1); 7235 break; 7236 case 2: 7237 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR2_1r(pc, ®2_ovr1)); 7238 *st_field_value = SC_X1_SPD_OVRR2_1r_CL36BYTEDELETEMODEf_GET(reg2_ovr1); 7239 break; 7240 case 3: 7241 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR3_1r(pc, ®3_ovr1)); 7242 *st_field_value = SC_X1_SPD_OVRR3_1r_CL36BYTEDELETEMODEf_GET(reg3_ovr1); 7243 break; 7244 } 7245 break; 7246 case TEMOD_OVERRIDE_BRCM64B66_DESCR_MODE: 7247 switch(st_entry_no){ 7248 case 0: 7249 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR0_1r(pc, ®0_ovr1)); 7250 *st_field_value = SC_X1_SPD_OVRR0_1r_BRCM64B66_DESCRAMBLER_ENABLEf_GET(reg0_ovr1); 7251 break; 7252 case 1: 7253 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR1_1r(pc, ®1_ovr1)); 7254 *st_field_value = SC_X1_SPD_OVRR1_1r_BRCM64B66_DESCRAMBLER_ENABLEf_GET(reg1_ovr1); 7255 break; 7256 case 2: 7257 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR2_1r(pc, ®2_ovr1)); 7258 *st_field_value = SC_X1_SPD_OVRR2_1r_BRCM64B66_DESCRAMBLER_ENABLEf_GET(reg2_ovr1); 7259 break; 7260 case 3: 7261 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR3_1r(pc, ®3_ovr1)); 7262 *st_field_value = SC_X1_SPD_OVRR3_1r_BRCM64B66_DESCRAMBLER_ENABLEf_GET(reg3_ovr1); 7263 break; 7264 } 7265 break; 7266 case TEMOD_OVERRIDE_CHKEND_EN: 7267 switch(st_entry_no){ 7268 case 0: 7269 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR0_2r(pc, ®0_ovr2)); 7270 *st_field_value = SC_X1_SPD_OVRR0_2r_CHK_END_ENf_GET(reg0_ovr2); 7271 break; 7272 case 1: 7273 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR1_2r(pc, ®1_ovr2)); 7274 *st_field_value = SC_X1_SPD_OVRR1_2r_CHK_END_ENf_GET(reg1_ovr2); 7275 break; 7276 case 2: 7277 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR2_2r(pc, ®2_ovr2)); 7278 *st_field_value = SC_X1_SPD_OVRR2_2r_CHK_END_ENf_GET(reg2_ovr2); 7279 break; 7280 case 3: 7281 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR3_2r(pc, ®3_ovr2)); 7282 *st_field_value = SC_X1_SPD_OVRR3_2r_CHK_END_ENf_GET(reg3_ovr2); 7283 break; 7284 } 7285 break; 7286 case TEMOD_OVERRIDE_BLKSYNC_MODE: 7287 switch(st_entry_no){ 7288 case 0: 7289 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR0_2r(pc, ®0_ovr2)); 7290 *st_field_value = SC_X1_SPD_OVRR0_2r_BLOCK_SYNC_MODEf_GET(reg0_ovr2); 7291 break; 7292 case 1: 7293 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR1_2r(pc, ®1_ovr2)); 7294 *st_field_value = SC_X1_SPD_OVRR1_2r_BLOCK_SYNC_MODEf_GET(reg1_ovr2); 7295 break; 7296 case 2: 7297 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR2_2r(pc, ®2_ovr2)); 7298 *st_field_value = SC_X1_SPD_OVRR2_2r_BLOCK_SYNC_MODEf_GET(reg2_ovr2); 7299 break; 7300 case 3: 7301 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR3_2r(pc, ®3_ovr2)); 7302 *st_field_value = SC_X1_SPD_OVRR3_2r_BLOCK_SYNC_MODEf_GET(reg3_ovr2); 7303 break; 7304 } 7305 break; 7306 case TEMOD_OVERRIDE_REORDER_EN : 7307 switch(st_entry_no){ 7308 case 0: 7309 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR0_2r(pc, ®0_ovr2)); 7310 *st_field_value = SC_X1_SPD_OVRR0_2r_REORDER_ENf_GET(reg0_ovr2); 7311 break; 7312 case 1: 7313 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR1_2r(pc, ®1_ovr2)); 7314 *st_field_value = SC_X1_SPD_OVRR1_2r_REORDER_ENf_GET(reg1_ovr2); 7315 break; 7316 case 2: 7317 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR2_2r(pc, ®2_ovr2)); 7318 *st_field_value = SC_X1_SPD_OVRR2_2r_REORDER_ENf_GET(reg2_ovr2); 7319 break; 7320 case 3: 7321 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR3_2r(pc, ®3_ovr2)); 7322 *st_field_value = SC_X1_SPD_OVRR3_2r_REORDER_ENf_GET(reg3_ovr2); 7323 break; 7324 } 7325 break; 7326 case TEMOD_OVERRIDE_CL36_EN: 7327 switch(st_entry_no){ 7328 case 0: 7329 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR0_2r(pc, ®0_ovr2)); 7330 *st_field_value = SC_X1_SPD_OVRR0_2r_CL36_ENf_GET(reg0_ovr2); 7331 break; 7332 case 1: 7333 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR1_2r(pc, ®1_ovr2)); 7334 *st_field_value = SC_X1_SPD_OVRR1_2r_CL36_ENf_GET(reg1_ovr2); 7335 break; 7336 case 2: 7337 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR2_2r(pc, ®2_ovr2)); 7338 *st_field_value = SC_X1_SPD_OVRR2_2r_CL36_ENf_GET(reg2_ovr2); 7339 break; 7340 case 3: 7341 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR3_2r(pc, ®3_ovr2)); 7342 *st_field_value = SC_X1_SPD_OVRR3_2r_CL36_ENf_GET(reg3_ovr2); 7343 break; 7344 } 7345 7346 break; 7347 case TEMOD_OVERRIDE_SCR_MODE: 7348 switch(st_entry_no){ 7349 case 0: 7350 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR0_0r(pc, ®0_ovr)); 7351 *st_field_value = SC_X1_SPD_OVRR0_0r_SCR_MODEf_GET(reg0_ovr); 7352 break; 7353 case 1: 7354 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR1_0r(pc, ®1_ovr)); 7355 *st_field_value = SC_X1_SPD_OVRR1_0r_SCR_MODEf_GET(reg1_ovr); 7356 break; 7357 case 2: 7358 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR2_0r(pc, ®2_ovr)); 7359 *st_field_value = SC_X1_SPD_OVRR2_0r_SCR_MODEf_GET(reg2_ovr); 7360 break; 7361 case 3: 7362 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR3_0r(pc, ®3_ovr)); 7363 *st_field_value = SC_X1_SPD_OVRR3_0r_SCR_MODEf_GET(reg3_ovr); 7364 break; 7365 } 7366 break; 7367 case TEMOD_OVERRIDE_DESCR_MODE: 7368 switch(st_entry_no){ 7369 case 0: 7370 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR0_1r(pc, ®0_ovr1)); 7371 *st_field_value = SC_X1_SPD_OVRR0_1r_DESCRAMBLERMODEf_GET(reg0_ovr1); 7372 break; 7373 case 1: 7374 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR1_1r(pc, ®1_ovr1)); 7375 *st_field_value = SC_X1_SPD_OVRR1_1r_DESCRAMBLERMODEf_GET(reg1_ovr1); 7376 break; 7377 case 2: 7378 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR2_1r(pc, ®2_ovr1)); 7379 *st_field_value = SC_X1_SPD_OVRR2_1r_DESCRAMBLERMODEf_GET(reg2_ovr1); 7380 break; 7381 case 3: 7382 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR3_1r(pc, ®3_ovr1)); 7383 *st_field_value = SC_X1_SPD_OVRR3_1r_DESCRAMBLERMODEf_GET(reg3_ovr1); 7384 break; 7385 } 7386 break; 7387 case TEMOD_OVERRIDE_ENCODE_MODE: 7388 switch(st_entry_no){ 7389 case 0: 7390 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR0_0r(pc, ®0_ovr)); 7391 *st_field_value = SC_X1_SPD_OVRR0_0r_ENCODEMODEf_GET(reg0_ovr); 7392 break; 7393 case 1: 7394 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR1_0r(pc, ®1_ovr)); 7395 *st_field_value = SC_X1_SPD_OVRR1_0r_ENCODEMODEf_GET(reg1_ovr); 7396 break; 7397 case 2: 7398 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR2_0r(pc, ®2_ovr)); 7399 *st_field_value = SC_X1_SPD_OVRR2_0r_ENCODEMODEf_GET(reg2_ovr); 7400 break; 7401 case 3: 7402 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR3_0r(pc, ®3_ovr)); 7403 *st_field_value = SC_X1_SPD_OVRR3_0r_ENCODEMODEf_GET(reg3_ovr); 7404 break; 7405 } 7406 7407 break; 7408 case TEMOD_OVERRIDE_DECODE_MODE: 7409 switch(st_entry_no){ 7410 case 0: 7411 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR0_1r(pc, ®0_ovr1)); 7412 *st_field_value = SC_X1_SPD_OVRR0_1r_DECODERMODEf_GET(reg0_ovr1); 7413 break; 7414 case 1: 7415 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR1_1r(pc, ®1_ovr1)); 7416 *st_field_value = SC_X1_SPD_OVRR1_1r_DECODERMODEf_GET(reg1_ovr1); 7417 break; 7418 case 2: 7419 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR2_1r(pc, ®2_ovr1)); 7420 *st_field_value = SC_X1_SPD_OVRR2_1r_DECODERMODEf_GET(reg2_ovr1); 7421 break; 7422 case 3: 7423 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR3_1r(pc, ®3_ovr1)); 7424 *st_field_value = SC_X1_SPD_OVRR3_1r_DECODERMODEf_GET(reg3_ovr1); 7425 break; 7426 } 7427 break; 7428 } 7429 7430 return PHYMOD_E_NONE; 7431 7432 } 7433 7434 /** 7435 @brief Sets the credit field of the Soft Table 7436 @param pc handle to current TSCE context (#PHYMOD_ST) 7437 @param st_entry_no: The ST to write to(0..3) 7438 @param credit_type: The ST credit field to write to #credit_type_t 7439 @param st_field_value: The ST value to write to the field 7440 returns The value PHYMOD_E_NONE upon successful completion. 7441 @details Sets the field of the Soft Table 7442 */ 7443 int temod_st_credit_field_set (PHYMOD_ST* pc,uint16_t st_entry_no,credit_type_t credit_type,uint16_t st_field_value){ 7444 7445 SC_X1_SPD_OVRR0_3r_t reg0_ovr3; 7446 SC_X1_SPD_OVRR0_4r_t reg0_ovr4; 7447 SC_X1_SPD_OVRR0_5r_t reg0_ovr5; 7448 SC_X1_SPD_OVRR0_6r_t reg0_ovr6; 7449 SC_X1_SPD_OVRR0_7r_t reg0_ovr7; 7450 SC_X1_SPD_OVRR0_8r_t reg0_ovr8; 7451 7452 SC_X1_SPD_OVRR1_3r_t reg1_ovr3; 7453 SC_X1_SPD_OVRR1_4r_t reg1_ovr4; 7454 SC_X1_SPD_OVRR1_5r_t reg1_ovr5; 7455 SC_X1_SPD_OVRR1_6r_t reg1_ovr6; 7456 SC_X1_SPD_OVRR1_7r_t reg1_ovr7; 7457 SC_X1_SPD_OVRR1_8r_t reg1_ovr8; 7458 7459 SC_X1_SPD_OVRR2_3r_t reg2_ovr3; 7460 SC_X1_SPD_OVRR2_4r_t reg2_ovr4; 7461 SC_X1_SPD_OVRR2_5r_t reg2_ovr5; 7462 SC_X1_SPD_OVRR2_6r_t reg2_ovr6; 7463 SC_X1_SPD_OVRR2_7r_t reg2_ovr7; 7464 SC_X1_SPD_OVRR2_8r_t reg2_ovr8; 7465 7466 SC_X1_SPD_OVRR3_3r_t reg3_ovr3; 7467 SC_X1_SPD_OVRR3_4r_t reg3_ovr4; 7468 SC_X1_SPD_OVRR3_5r_t reg3_ovr5; 7469 SC_X1_SPD_OVRR3_6r_t reg3_ovr6; 7470 SC_X1_SPD_OVRR3_7r_t reg3_ovr7; 7471 SC_X1_SPD_OVRR3_8r_t reg3_ovr8; 7472 7473 SC_X1_SPD_OVRR0_3r_CLR(reg0_ovr3); 7474 SC_X1_SPD_OVRR0_4r_CLR(reg0_ovr4); 7475 SC_X1_SPD_OVRR0_5r_CLR(reg0_ovr5); 7476 SC_X1_SPD_OVRR0_6r_CLR(reg0_ovr6); 7477 SC_X1_SPD_OVRR0_7r_CLR(reg0_ovr7); 7478 SC_X1_SPD_OVRR0_8r_CLR(reg0_ovr8); 7479 7480 SC_X1_SPD_OVRR1_3r_CLR(reg1_ovr3); 7481 SC_X1_SPD_OVRR1_4r_CLR(reg1_ovr4); 7482 SC_X1_SPD_OVRR1_5r_CLR(reg1_ovr5); 7483 SC_X1_SPD_OVRR1_6r_CLR(reg1_ovr6); 7484 SC_X1_SPD_OVRR1_7r_CLR(reg1_ovr7); 7485 SC_X1_SPD_OVRR1_8r_CLR(reg1_ovr8); 7486 7487 SC_X1_SPD_OVRR2_3r_CLR(reg2_ovr3); 7488 SC_X1_SPD_OVRR2_4r_CLR(reg2_ovr4); 7489 SC_X1_SPD_OVRR2_5r_CLR(reg2_ovr5); 7490 SC_X1_SPD_OVRR2_6r_CLR(reg2_ovr6); 7491 SC_X1_SPD_OVRR2_7r_CLR(reg2_ovr7); 7492 SC_X1_SPD_OVRR2_8r_CLR(reg2_ovr8); 7493 7494 SC_X1_SPD_OVRR3_3r_CLR(reg3_ovr3); 7495 SC_X1_SPD_OVRR3_4r_CLR(reg3_ovr4); 7496 SC_X1_SPD_OVRR3_5r_CLR(reg3_ovr5); 7497 SC_X1_SPD_OVRR3_6r_CLR(reg3_ovr6); 7498 SC_X1_SPD_OVRR3_7r_CLR(reg3_ovr7); 7499 SC_X1_SPD_OVRR3_8r_CLR(reg3_ovr8); 7500 7501 switch ( credit_type ) { 7502 /* case TEMOD_CREDIT_RESET: 7503 //reset credits 7504 break; 7505 */ 7506 /*case TEMOD_CREDIT_TABLE: 7507 // get info. from table and apply it to all credit regs. */ 7508 case TEMOD_CREDIT_CLOCK_COUNT_0: 7509 switch(st_entry_no){ 7510 case 0: SC_X1_SPD_OVRR0_3r_CLOCKCNT0f_SET(reg0_ovr3, st_field_value); 7511 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_3r(pc, reg0_ovr3)); 7512 break; 7513 case 1: SC_X1_SPD_OVRR1_3r_CLOCKCNT0f_SET(reg1_ovr3, st_field_value); 7514 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_3r(pc, reg1_ovr3)); 7515 break; 7516 case 2: SC_X1_SPD_OVRR2_3r_CLOCKCNT0f_SET(reg2_ovr3, st_field_value); 7517 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_3r(pc, reg2_ovr3)); 7518 break; 7519 case 3: SC_X1_SPD_OVRR3_3r_CLOCKCNT0f_SET(reg3_ovr3, st_field_value); 7520 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_3r(pc, reg3_ovr3)); 7521 break; 7522 } 7523 break; 7524 case TEMOD_CREDIT_CLOCK_COUNT_1: 7525 switch(st_entry_no){ 7526 case 0: SC_X1_SPD_OVRR0_4r_CLOCKCNT1f_SET(reg0_ovr4, st_field_value); 7527 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_4r(pc, reg0_ovr4)); 7528 break; 7529 case 1: SC_X1_SPD_OVRR1_4r_CLOCKCNT1f_SET(reg1_ovr4, st_field_value); 7530 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_4r(pc, reg1_ovr4)); 7531 break; 7532 case 2: SC_X1_SPD_OVRR2_4r_CLOCKCNT1f_SET(reg2_ovr4, st_field_value); 7533 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_4r(pc, reg2_ovr4)); 7534 break; 7535 case 3: SC_X1_SPD_OVRR3_4r_CLOCKCNT1f_SET(reg3_ovr4, st_field_value); 7536 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_4r(pc, reg3_ovr4)); 7537 break; 7538 } 7539 break; 7540 case TEMOD_CREDIT_LOOP_COUNT_0: 7541 switch(st_entry_no){ 7542 case 0: SC_X1_SPD_OVRR0_5r_LOOPCNT0f_SET(reg0_ovr5, st_field_value); 7543 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_5r(pc, reg0_ovr5)); 7544 break; 7545 case 1: SC_X1_SPD_OVRR1_5r_LOOPCNT0f_SET(reg1_ovr5, st_field_value); 7546 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_5r(pc, reg1_ovr5)); 7547 break; 7548 case 2: SC_X1_SPD_OVRR2_5r_LOOPCNT0f_SET(reg2_ovr5, st_field_value); 7549 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_5r(pc, reg2_ovr5)); 7550 break; 7551 case 3: SC_X1_SPD_OVRR3_5r_LOOPCNT0f_SET(reg3_ovr5, st_field_value); 7552 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_5r(pc, reg3_ovr5)); 7553 break; 7554 } 7555 break; 7556 case TEMOD_CREDIT_LOOP_COUNT_1: 7557 switch(st_entry_no){ 7558 case 0: SC_X1_SPD_OVRR0_5r_LOOPCNT1f_SET(reg0_ovr5, st_field_value); 7559 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_5r(pc, reg0_ovr5)); 7560 break; 7561 case 1: SC_X1_SPD_OVRR1_5r_LOOPCNT1f_SET(reg1_ovr5, st_field_value); 7562 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_5r(pc, reg1_ovr5)); 7563 break; 7564 case 2: SC_X1_SPD_OVRR2_5r_LOOPCNT1f_SET(reg2_ovr5, st_field_value); 7565 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_5r(pc, reg2_ovr5)); 7566 break; 7567 case 3: SC_X1_SPD_OVRR3_5r_LOOPCNT1f_SET(reg3_ovr5, st_field_value); 7568 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_5r(pc, reg3_ovr5)); 7569 break; 7570 } 7571 break; 7572 case TEMOD_CREDIT_MAC: 7573 switch(st_entry_no){ 7574 case 0: SC_X1_SPD_OVRR0_6r_MAC_CREDITGENCNTf_SET(reg0_ovr6, st_field_value); 7575 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_6r(pc, reg0_ovr6)); 7576 break; 7577 case 1: SC_X1_SPD_OVRR1_6r_MAC_CREDITGENCNTf_SET(reg1_ovr6, st_field_value); 7578 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_6r(pc, reg1_ovr6)); 7579 break; 7580 case 2: SC_X1_SPD_OVRR2_6r_MAC_CREDITGENCNTf_SET(reg2_ovr6, st_field_value); 7581 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_6r(pc, reg2_ovr6)); 7582 break; 7583 case 3: SC_X1_SPD_OVRR3_6r_MAC_CREDITGENCNTf_SET(reg3_ovr6, st_field_value); 7584 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_6r(pc, reg3_ovr6)); 7585 break; 7586 } 7587 break; 7588 case TEMOD_CREDIT_PCS_CLOCK_COUNT_0: 7589 switch(st_entry_no){ 7590 case 0: SC_X1_SPD_OVRR0_7r_PCS_CLOCKCNT0f_SET(reg0_ovr7, st_field_value); 7591 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_7r(pc, reg0_ovr7)); 7592 break; 7593 case 1: SC_X1_SPD_OVRR1_7r_PCS_CLOCKCNT0f_SET(reg1_ovr7, st_field_value); 7594 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_7r(pc, reg1_ovr7)); 7595 break; 7596 case 2: SC_X1_SPD_OVRR2_7r_PCS_CLOCKCNT0f_SET(reg2_ovr7, st_field_value); 7597 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_7r(pc, reg2_ovr7)); 7598 break; 7599 case 3: SC_X1_SPD_OVRR3_7r_PCS_CLOCKCNT0f_SET(reg3_ovr7, st_field_value); 7600 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_7r(pc, reg3_ovr7)); 7601 break; 7602 } 7603 break; 7604 case TEMOD_CREDIT_PCS_GEN_COUNT: 7605 switch(st_entry_no){ 7606 case 0: SC_X1_SPD_OVRR0_8r_PCS_CREDITGENCNTf_SET(reg0_ovr8, st_field_value); 7607 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_8r(pc, reg0_ovr8)); 7608 break; 7609 case 1: SC_X1_SPD_OVRR1_8r_PCS_CREDITGENCNTf_SET(reg1_ovr8, st_field_value); 7610 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_8r(pc, reg1_ovr8)); 7611 break; 7612 case 2: SC_X1_SPD_OVRR2_8r_PCS_CREDITGENCNTf_SET(reg2_ovr8, st_field_value); 7613 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_8r(pc, reg2_ovr8)); 7614 break; 7615 case 3: SC_X1_SPD_OVRR3_8r_PCS_CREDITGENCNTf_SET(reg3_ovr8, st_field_value); 7616 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_8r(pc, reg3_ovr8)); 7617 break; 7618 } 7619 break; 7620 case TEMOD_CREDIT_EN: 7621 switch(st_entry_no){ 7622 case 0: SC_X1_SPD_OVRR0_7r_REPLICATION_CNTf_SET(reg0_ovr7, st_field_value); 7623 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_7r(pc, reg0_ovr7)); 7624 break; 7625 case 1: SC_X1_SPD_OVRR1_7r_REPLICATION_CNTf_SET(reg1_ovr7, st_field_value); 7626 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_7r(pc, reg1_ovr7)); 7627 break; 7628 case 2: SC_X1_SPD_OVRR2_7r_REPLICATION_CNTf_SET(reg2_ovr7, st_field_value); 7629 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_7r(pc, reg2_ovr7)); 7630 break; 7631 case 3: SC_X1_SPD_OVRR3_7r_REPLICATION_CNTf_SET(reg3_ovr7, st_field_value); 7632 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_7r(pc, reg3_ovr7)); 7633 break; 7634 } 7635 break; 7636 case TEMOD_CREDIT_PCS_REPCNT: 7637 switch(st_entry_no){ 7638 case 0: SC_X1_SPD_OVRR0_7r_REPLICATION_CNTf_SET(reg0_ovr7, st_field_value); 7639 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_7r(pc, reg0_ovr7)); 7640 break; 7641 case 1: SC_X1_SPD_OVRR1_7r_REPLICATION_CNTf_SET(reg1_ovr7, st_field_value); 7642 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_7r(pc, reg1_ovr7)); 7643 break; 7644 case 2: SC_X1_SPD_OVRR2_7r_REPLICATION_CNTf_SET(reg2_ovr7, st_field_value); 7645 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_7r(pc, reg2_ovr7)); 7646 break; 7647 case 3: SC_X1_SPD_OVRR3_7r_REPLICATION_CNTf_SET(reg3_ovr7, st_field_value); 7648 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_7r(pc, reg3_ovr7)); 7649 break; 7650 } 7651 break; 7652 case TEMOD_CREDIT_SGMII_SPD: 7653 switch(st_entry_no){ 7654 case 0: SC_X1_SPD_OVRR0_3r_SGMII_SPD_SWITCHf_SET(reg0_ovr3, st_field_value); 7655 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_3r(pc, reg0_ovr3)); 7656 break; 7657 case 1: SC_X1_SPD_OVRR1_3r_SGMII_SPD_SWITCHf_SET(reg1_ovr3, st_field_value); 7658 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_3r(pc, reg1_ovr3)); 7659 break; 7660 case 2: SC_X1_SPD_OVRR2_3r_SGMII_SPD_SWITCHf_SET(reg2_ovr3, st_field_value); 7661 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_3r(pc, reg2_ovr3)); 7662 break; 7663 case 3: SC_X1_SPD_OVRR3_3r_SGMII_SPD_SWITCHf_SET(reg3_ovr3, st_field_value); 7664 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_3r(pc, reg3_ovr3)); 7665 break; 7666 } 7667 break; 7668 default: 7669 return PHYMOD_E_FAIL; 7670 break; 7671 } 7672 return PHYMOD_E_NONE; 7673 } 7674 7675 7676 /** 7677 @brief Gets the credit field of the Soft Table 7678 @param pc handle to current TSCE context (#PHYMOD_ST) 7679 @param st_entry_no The ST to write to(0..3) 7680 @param credit_type The ST field to write to, of type #credit_type_t 7681 @param st_field_value The ST value of the field 7682 returns The value PHYMOD_E_NONE upon successful completion. 7683 @details Gets the field of the Soft Table 7684 */ 7685 int temod_st_credit_field_get (PHYMOD_ST* pc,uint16_t st_entry_no, credit_type_t credit_type, uint16_t* st_field_value){ 7686 7687 SC_X1_SPD_OVRR0_3r_t reg0_ovr3; 7688 SC_X1_SPD_OVRR0_4r_t reg0_ovr4; 7689 SC_X1_SPD_OVRR0_5r_t reg0_ovr5; 7690 SC_X1_SPD_OVRR0_6r_t reg0_ovr6; 7691 SC_X1_SPD_OVRR0_7r_t reg0_ovr7; 7692 SC_X1_SPD_OVRR0_8r_t reg0_ovr8; 7693 7694 SC_X1_SPD_OVRR1_3r_t reg1_ovr3; 7695 SC_X1_SPD_OVRR1_4r_t reg1_ovr4; 7696 SC_X1_SPD_OVRR1_5r_t reg1_ovr5; 7697 SC_X1_SPD_OVRR1_6r_t reg1_ovr6; 7698 SC_X1_SPD_OVRR1_7r_t reg1_ovr7; 7699 SC_X1_SPD_OVRR1_8r_t reg1_ovr8; 7700 7701 SC_X1_SPD_OVRR2_3r_t reg2_ovr3; 7702 SC_X1_SPD_OVRR2_4r_t reg2_ovr4; 7703 SC_X1_SPD_OVRR2_5r_t reg2_ovr5; 7704 SC_X1_SPD_OVRR2_6r_t reg2_ovr6; 7705 SC_X1_SPD_OVRR2_7r_t reg2_ovr7; 7706 SC_X1_SPD_OVRR2_8r_t reg2_ovr8; 7707 7708 SC_X1_SPD_OVRR3_3r_t reg3_ovr3; 7709 SC_X1_SPD_OVRR3_4r_t reg3_ovr4; 7710 SC_X1_SPD_OVRR3_5r_t reg3_ovr5; 7711 SC_X1_SPD_OVRR3_6r_t reg3_ovr6; 7712 SC_X1_SPD_OVRR3_7r_t reg3_ovr7; 7713 SC_X1_SPD_OVRR3_8r_t reg3_ovr8; 7714 7715 SC_X1_SPD_OVRR0_3r_CLR(reg0_ovr3); 7716 SC_X1_SPD_OVRR0_4r_CLR(reg0_ovr4); 7717 SC_X1_SPD_OVRR0_5r_CLR(reg0_ovr5); 7718 SC_X1_SPD_OVRR0_6r_CLR(reg0_ovr6); 7719 SC_X1_SPD_OVRR0_7r_CLR(reg0_ovr7); 7720 SC_X1_SPD_OVRR0_8r_CLR(reg0_ovr8); 7721 7722 SC_X1_SPD_OVRR1_3r_CLR(reg1_ovr3); 7723 SC_X1_SPD_OVRR1_4r_CLR(reg1_ovr4); 7724 SC_X1_SPD_OVRR1_5r_CLR(reg1_ovr5); 7725 SC_X1_SPD_OVRR1_6r_CLR(reg1_ovr6); 7726 SC_X1_SPD_OVRR1_7r_CLR(reg1_ovr7); 7727 SC_X1_SPD_OVRR1_8r_CLR(reg1_ovr8); 7728 7729 SC_X1_SPD_OVRR2_3r_CLR(reg2_ovr3); 7730 SC_X1_SPD_OVRR2_4r_CLR(reg2_ovr4); 7731 SC_X1_SPD_OVRR2_5r_CLR(reg2_ovr5); 7732 SC_X1_SPD_OVRR2_6r_CLR(reg2_ovr6); 7733 SC_X1_SPD_OVRR2_7r_CLR(reg2_ovr7); 7734 SC_X1_SPD_OVRR2_8r_CLR(reg2_ovr8); 7735 7736 SC_X1_SPD_OVRR3_3r_CLR(reg3_ovr3); 7737 SC_X1_SPD_OVRR3_4r_CLR(reg3_ovr4); 7738 SC_X1_SPD_OVRR3_5r_CLR(reg3_ovr5); 7739 SC_X1_SPD_OVRR3_6r_CLR(reg3_ovr6); 7740 SC_X1_SPD_OVRR3_7r_CLR(reg3_ovr7); 7741 SC_X1_SPD_OVRR3_8r_CLR(reg3_ovr8); 7742 7743 switch ( credit_type ) { 7744 /* case TEMOD_CREDIT_RESET: 7745 //reset credits 7746 break; 7747 */ 7748 /*case TEMOD_CREDIT_TABLE: 7749 // get info. from table and apply it to all credit regs. */ 7750 case TEMOD_CREDIT_CLOCK_COUNT_0: 7751 switch(st_entry_no){ 7752 case 0: 7753 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR0_3r(pc, ®0_ovr3)); 7754 *st_field_value = SC_X1_SPD_OVRR0_3r_CLOCKCNT0f_GET(reg0_ovr3); 7755 break; 7756 case 1: 7757 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR1_3r(pc, ®1_ovr3)); 7758 *st_field_value = SC_X1_SPD_OVRR1_3r_CLOCKCNT0f_GET(reg1_ovr3); 7759 break; 7760 case 2: 7761 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR2_3r(pc, ®2_ovr3)); 7762 *st_field_value = SC_X1_SPD_OVRR2_3r_CLOCKCNT0f_GET(reg2_ovr3); 7763 break; 7764 case 3: 7765 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR3_3r(pc, ®3_ovr3)); 7766 *st_field_value = SC_X1_SPD_OVRR3_3r_CLOCKCNT0f_GET(reg3_ovr3); 7767 break; 7768 } 7769 break; 7770 case TEMOD_CREDIT_CLOCK_COUNT_1: 7771 switch(st_entry_no){ 7772 case 0: 7773 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR0_4r(pc, ®0_ovr4)); 7774 *st_field_value = SC_X1_SPD_OVRR0_4r_CLOCKCNT1f_GET(reg0_ovr4); 7775 break; 7776 case 1: 7777 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR1_4r(pc, ®1_ovr4)); 7778 *st_field_value = SC_X1_SPD_OVRR1_4r_CLOCKCNT1f_GET(reg1_ovr4); 7779 break; 7780 case 2: 7781 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR2_4r(pc, ®2_ovr4)); 7782 *st_field_value = SC_X1_SPD_OVRR2_4r_CLOCKCNT1f_GET(reg2_ovr4); 7783 break; 7784 case 3: 7785 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR3_4r(pc, ®3_ovr4)); 7786 *st_field_value = SC_X1_SPD_OVRR3_4r_CLOCKCNT1f_GET(reg3_ovr4); 7787 break; 7788 } 7789 break; 7790 case TEMOD_CREDIT_LOOP_COUNT_0: 7791 switch(st_entry_no){ 7792 case 0: 7793 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR0_5r(pc, ®0_ovr5)); 7794 *st_field_value = SC_X1_SPD_OVRR0_5r_LOOPCNT0f_GET(reg0_ovr5); 7795 break; 7796 case 1: 7797 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR1_5r(pc, ®1_ovr5)); 7798 *st_field_value = SC_X1_SPD_OVRR1_5r_LOOPCNT0f_GET(reg1_ovr5); 7799 break; 7800 case 2: 7801 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR2_5r(pc, ®2_ovr5)); 7802 *st_field_value = SC_X1_SPD_OVRR2_5r_LOOPCNT0f_GET(reg2_ovr5); 7803 break; 7804 case 3: 7805 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR3_5r(pc, ®3_ovr5)); 7806 *st_field_value = SC_X1_SPD_OVRR3_5r_LOOPCNT0f_GET(reg3_ovr5); 7807 break; 7808 } 7809 break; 7810 case TEMOD_CREDIT_LOOP_COUNT_1: 7811 switch(st_entry_no){ 7812 case 0: 7813 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR0_5r(pc, ®0_ovr5)); 7814 *st_field_value = SC_X1_SPD_OVRR0_5r_LOOPCNT1f_GET(reg0_ovr5); 7815 break; 7816 case 1: 7817 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR1_5r(pc, ®1_ovr5)); 7818 *st_field_value = SC_X1_SPD_OVRR1_5r_LOOPCNT1f_GET(reg1_ovr5); 7819 break; 7820 case 2: 7821 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR2_5r(pc, ®2_ovr5)); 7822 *st_field_value = SC_X1_SPD_OVRR2_5r_LOOPCNT1f_GET(reg2_ovr5); 7823 break; 7824 case 3: 7825 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR3_5r(pc, ®3_ovr5)); 7826 *st_field_value = SC_X1_SPD_OVRR3_5r_LOOPCNT1f_GET(reg3_ovr5); 7827 break; 7828 } 7829 break; 7830 case TEMOD_CREDIT_MAC: 7831 switch(st_entry_no){ 7832 case 0: 7833 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR0_6r(pc, ®0_ovr6)); 7834 *st_field_value = SC_X1_SPD_OVRR0_6r_MAC_CREDITGENCNTf_GET(reg0_ovr6); 7835 break; 7836 case 1: 7837 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR1_6r(pc, ®1_ovr6)); 7838 *st_field_value = SC_X1_SPD_OVRR1_6r_MAC_CREDITGENCNTf_GET(reg1_ovr6); 7839 break; 7840 case 2: 7841 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR2_6r(pc, ®2_ovr6)); 7842 *st_field_value = SC_X1_SPD_OVRR2_6r_MAC_CREDITGENCNTf_GET(reg2_ovr6); 7843 break; 7844 case 3: 7845 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR3_6r(pc, ®3_ovr6)); 7846 *st_field_value = SC_X1_SPD_OVRR3_6r_MAC_CREDITGENCNTf_GET(reg3_ovr6); 7847 break; 7848 } 7849 break; 7850 case TEMOD_CREDIT_PCS_CLOCK_COUNT_0: 7851 switch(st_entry_no){ 7852 case 0: 7853 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR0_7r(pc, ®0_ovr7)); 7854 *st_field_value = SC_X1_SPD_OVRR0_7r_PCS_CLOCKCNT0f_GET(reg0_ovr7); 7855 break; 7856 case 1: 7857 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR1_7r(pc, ®1_ovr7)); 7858 *st_field_value = SC_X1_SPD_OVRR1_7r_PCS_CLOCKCNT0f_GET(reg1_ovr7); 7859 break; 7860 case 2: 7861 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR2_7r(pc, ®2_ovr7)); 7862 *st_field_value = SC_X1_SPD_OVRR2_7r_PCS_CLOCKCNT0f_GET(reg2_ovr7); 7863 break; 7864 case 3: 7865 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR3_7r(pc, ®3_ovr7)); 7866 *st_field_value = SC_X1_SPD_OVRR3_7r_PCS_CLOCKCNT0f_GET(reg3_ovr7); 7867 break; 7868 } 7869 break; 7870 case TEMOD_CREDIT_PCS_GEN_COUNT: 7871 switch(st_entry_no){ 7872 case 0: 7873 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR0_8r(pc, ®0_ovr8)); 7874 *st_field_value = SC_X1_SPD_OVRR0_8r_PCS_CREDITGENCNTf_GET(reg0_ovr8); 7875 break; 7876 case 1: 7877 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR1_8r(pc, ®1_ovr8)); 7878 *st_field_value = SC_X1_SPD_OVRR1_8r_PCS_CREDITGENCNTf_GET(reg1_ovr8); 7879 break; 7880 case 2: 7881 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR2_8r(pc, ®2_ovr8)); 7882 *st_field_value = SC_X1_SPD_OVRR2_8r_PCS_CREDITGENCNTf_GET(reg2_ovr8); 7883 break; 7884 case 3: 7885 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR3_8r(pc, ®3_ovr8)); 7886 *st_field_value = SC_X1_SPD_OVRR3_8r_PCS_CREDITGENCNTf_GET(reg3_ovr8); 7887 break; 7888 } 7889 break; 7890 case TEMOD_CREDIT_EN: 7891 switch(st_entry_no){ 7892 case 0: 7893 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR0_7r(pc, ®0_ovr7)); 7894 *st_field_value = SC_X1_SPD_OVRR0_7r_REPLICATION_CNTf_GET(reg0_ovr7); 7895 break; 7896 case 1: 7897 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR1_7r(pc, ®1_ovr7)); 7898 *st_field_value = SC_X1_SPD_OVRR1_7r_REPLICATION_CNTf_GET(reg1_ovr7); 7899 break; 7900 case 2: 7901 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR2_7r(pc, ®2_ovr7)); 7902 *st_field_value = SC_X1_SPD_OVRR2_7r_REPLICATION_CNTf_GET(reg2_ovr7); 7903 break; 7904 case 3: 7905 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR3_7r(pc, ®3_ovr7)); 7906 *st_field_value = SC_X1_SPD_OVRR3_7r_REPLICATION_CNTf_GET(reg3_ovr7); 7907 break; 7908 } 7909 break; 7910 case TEMOD_CREDIT_PCS_REPCNT: 7911 switch(st_entry_no){ 7912 case 0: 7913 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR0_7r(pc, ®0_ovr7)); 7914 *st_field_value = SC_X1_SPD_OVRR0_7r_REPLICATION_CNTf_GET(reg0_ovr7); 7915 break; 7916 case 1: 7917 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR1_7r(pc, ®1_ovr7)); 7918 *st_field_value = SC_X1_SPD_OVRR1_7r_REPLICATION_CNTf_GET(reg1_ovr7); 7919 break; 7920 case 2: 7921 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR2_7r(pc, ®2_ovr7)); 7922 *st_field_value = SC_X1_SPD_OVRR2_7r_REPLICATION_CNTf_GET(reg2_ovr7); 7923 break; 7924 case 3: 7925 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR3_7r(pc, ®3_ovr7)); 7926 *st_field_value = SC_X1_SPD_OVRR3_7r_REPLICATION_CNTf_GET(reg3_ovr7); 7927 break; 7928 } 7929 break; 7930 case TEMOD_CREDIT_SGMII_SPD: 7931 switch(st_entry_no){ 7932 case 0: 7933 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR0_3r(pc, ®0_ovr3)); 7934 *st_field_value = SC_X1_SPD_OVRR0_3r_SGMII_SPD_SWITCHf_GET(reg0_ovr3); 7935 break; 7936 case 1: 7937 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR1_3r(pc, ®1_ovr3)); 7938 *st_field_value = SC_X1_SPD_OVRR1_3r_SGMII_SPD_SWITCHf_GET(reg1_ovr3); 7939 break; 7940 case 2: 7941 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR2_3r(pc, ®2_ovr3)); 7942 *st_field_value = SC_X1_SPD_OVRR2_3r_SGMII_SPD_SWITCHf_GET(reg2_ovr3); 7943 break; 7944 case 3: 7945 PHYMOD_IF_ERR_RETURN (READ_SC_X1_SPD_OVRR3_3r(pc, ®3_ovr3)); 7946 *st_field_value = SC_X1_SPD_OVRR3_3r_SGMII_SPD_SWITCHf_GET(reg3_ovr3); 7947 break; 7948 } 7949 break; 7950 default: 7951 return PHYMOD_E_FAIL; 7952 break; 7953 } 7954 return PHYMOD_E_NONE; 7955 } 7956 7957 /** 7958 @brief EEE Control Set 7959 @param pc handle to current TSCE context (#PHYMOD_ST) 7960 @param enable enable or disable EEE control 7961 @returns The value PHYMOD_E_NONE upon successful completion 7962 @details EEE Control 7963 enable =1 : Allow LPI pass through. i.e. dont convert LPI. 7964 enable =0 : Convert LPI to idle. So MAC will not see it. 7965 7966 */ 7967 int temod_eee_control_set(PHYMOD_ST* pc, uint32_t enable) 7968 { 7969 RX_X4_PCS_CTL0r_t reg_pcs_ctrl0; 7970 7971 TEMOD_DBG_IN_FUNC_INFO(pc); 7972 RX_X4_PCS_CTL0r_CLR(reg_pcs_ctrl0); 7973 READ_RX_X4_PCS_CTL0r(pc, ®_pcs_ctrl0); 7974 7975 RX_X4_PCS_CTL0r_LPI_ENABLEf_SET(reg_pcs_ctrl0, enable & 0x1); 7976 PHYMOD_IF_ERR_RETURN (MODIFY_RX_X4_PCS_CTL0r(pc, reg_pcs_ctrl0)); 7977 return PHYMOD_E_NONE; 7978 } 7979 7980 /** 7981 @brief EEE Control Get 7982 @param pc handle to current TSCE context (#PHYMOD_ST) 7983 @param enable handle to pass back EEE control 7984 @returns The value PHYMOD_E_NONE upon successful completion 7985 @details EEE Control 7986 enable =1 : Allow LPI pass through. i.e. dont convert LPI. 7987 enable =0 : Convert LPI to idle. So MAC will not see it. 7988 7989 */ 7990 int temod_eee_control_get(PHYMOD_ST* pc, uint32_t *enable) 7991 { 7992 RX_X4_PCS_CTL0r_t reg_pcs_ctrl0; 7993 7994 TEMOD_DBG_IN_FUNC_INFO(pc); 7995 RX_X4_PCS_CTL0r_CLR(reg_pcs_ctrl0); 7996 7997 PHYMOD_IF_ERR_RETURN (READ_RX_X4_PCS_CTL0r(pc, ®_pcs_ctrl0)); 7998 *enable = RX_X4_PCS_CTL0r_LPI_ENABLEf_GET(reg_pcs_ctrl0); 7999 return PHYMOD_E_NONE; 8000 } 8001 8002 8003 /** 8004 @brief an_ncl72_inhibit timer Set 8005 @param pc handle to current TSCE context (#PHYMOD_ST) 8006 @param value the timer value for an_ncl72_inhibit_timer 8007 @returns The value PHYMOD_E_NONE upon successful completion 8008 @details an_ncl72_inhibit timer Set 8009 */ 8010 int temod_an_ncl72_inhibit_timer_set(PHYMOD_ST* pc, uint16_t value) 8011 { 8012 AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72r_t reg_inhibit_not_timer; 8013 8014 TEMOD_DBG_IN_FUNC_INFO(pc); 8015 8016 AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72r_CLR(reg_inhibit_not_timer); 8017 AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72r_SET(reg_inhibit_not_timer, value & 0xffff); 8018 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72r(pc, reg_inhibit_not_timer)); 8019 8020 return PHYMOD_E_NONE; 8021 } 8022 8023 /** 8024 @brief an_ncl72_inhibit timer Get 8025 @param pc handle to current TSCE context (#PHYMOD_ST) 8026 @param value handle to get the timer value for an_ncl72_inhibit_timer 8027 @returns The value PHYMOD_E_NONE upon successful completion 8028 @details an_ncl72_inhibit timer Set 8029 */ 8030 int temod_an_ncl72_inhibit_timer_get(PHYMOD_ST* pc, uint16_t *value) 8031 { 8032 AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72r_t reg_inhibit_not_timer; 8033 8034 TEMOD_DBG_IN_FUNC_INFO(pc); 8035 8036 AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72r_CLR(reg_inhibit_not_timer); 8037 PHYMOD_IF_ERR_RETURN(READ_AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72r(pc, ®_inhibit_not_timer)); 8038 *value = AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72r_GET(reg_inhibit_not_timer); 8039 8040 return PHYMOD_E_NONE; 8041 } 8042 8043 8044 /** 8045 @brief Setup the default for cl74 to ieee compliance 8046 @param pc handle to current TSCE context (#PHYMOD_ST) 8047 @returns The value PHYMOD_E_NONE upon successful completion 8048 @details cl74 control set to ieee compliance 8049 */ 8050 int temod_cl74_chng_default (PHYMOD_ST* pc) 8051 { 8052 RX_X4_FEC2r_t RX_X4_FEC2reg; 8053 phymod_access_t pa_copy; 8054 int i; 8055 8056 TEMOD_DBG_IN_FUNC_INFO(pc); 8057 8058 PHYMOD_MEMCPY(&pa_copy, pc, sizeof(pa_copy)); 8059 RX_X4_FEC2r_CLR(RX_X4_FEC2reg); 8060 8061 for (i = 0; i <4; i++) { 8062 pa_copy.lane_mask = 0x1 << i; 8063 PHYMOD_IF_ERR_RETURN(WRITE_RX_X4_FEC2r(&pa_copy, RX_X4_FEC2reg)); 8064 } 8065 return PHYMOD_E_NONE; 8066 } 8067 8068 #ifdef _SDK_TEMOD_ 8069 int temod_pll_sequencer_control(PHYMOD_ST *pa, int enable) { return 0; } 8070 /* 8071 int temod_pll_lock_wait ( PHYMOD_ST *pc, int timeOutValue) { return 0; } 8072 int temod_tx_pi_control_get ( PHYMOD_ST *pa, uint32_t *value) { return 0; } 8073 int temod_get_ht_entries(PHYMOD_ST *pa) { return 0; } 8074 */ 8075 8076 int temod_an_oui_set(PHYMOD_ST* pc, temod_an_oui_t oui) { 8077 8078 AN_X1_OUI_LWRr_t AN_X1_CONTROL_OUI_LOWERr_reg; 8079 AN_X1_OUI_UPRr_t AN_X1_CONTROL_OUI_UPPERr_reg; 8080 AN_X4_CTLSr_t AN_X4_CTLSr_t_reg; 8081 uint16_t oui_override; 8082 8083 oui_override = ((oui.oui_override_hpam_adv ) & 1) << 5; 8084 oui_override |= ((oui.oui_override_hpam_det ) & 1) << 4; 8085 oui_override |= ((oui.oui_override_bam73_adv) & 1) << 3; 8086 oui_override |= ((oui.oui_override_bam73_det) & 1) << 2; 8087 oui_override |= ((oui.oui_override_bam37_adv) & 1) << 1; 8088 oui_override |= ((oui.oui_override_bam37_det) & 1) << 0; 8089 8090 TEMOD_DBG_IN_FUNC_INFO(pc); 8091 8092 AN_X1_OUI_LWRr_CLR(AN_X1_CONTROL_OUI_LOWERr_reg); 8093 AN_X1_OUI_LWRr_SET(AN_X1_CONTROL_OUI_LOWERr_reg, oui.oui & 0xffff); 8094 /********Setting AN_X1_OUI_LWR 0x9241*****/ 8095 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_OUI_LWRr(pc, AN_X1_CONTROL_OUI_LOWERr_reg)); 8096 8097 AN_X1_OUI_UPRr_CLR(AN_X1_CONTROL_OUI_UPPERr_reg); 8098 AN_X1_OUI_UPRr_SET(AN_X1_CONTROL_OUI_UPPERr_reg, (oui.oui >> 16) & 0xff); 8099 /********Setting AN_X1_OUI_UPR 0x9240*****/ 8100 PHYMOD_IF_ERR_RETURN(WRITE_AN_X1_OUI_UPRr(pc, AN_X1_CONTROL_OUI_UPPERr_reg)); 8101 8102 AN_X4_CTLSr_CLR(AN_X4_CTLSr_t_reg); 8103 AN_X4_CTLSr_OUI_CONTROLf_SET(AN_X4_CTLSr_t_reg, oui_override); 8104 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_CTLSr(pc, AN_X4_CTLSr_t_reg)); 8105 8106 return PHYMOD_E_NONE; 8107 } 8108 8109 int temod_an_oui_get(PHYMOD_ST* pc, temod_an_oui_t* oui) { 8110 8111 AN_X1_OUI_LWRr_t AN_X1_CONTROL_OUI_LOWERr_reg; 8112 AN_X1_OUI_UPRr_t AN_X1_CONTROL_OUI_UPPERr_reg; 8113 AN_X4_CTLSr_t AN_X4_CTLSr_t_reg; 8114 uint16_t oui_override; 8115 8116 TEMOD_DBG_IN_FUNC_INFO(pc); 8117 8118 PHYMOD_IF_ERR_RETURN(READ_AN_X1_OUI_LWRr(pc, &AN_X1_CONTROL_OUI_LOWERr_reg)); 8119 PHYMOD_IF_ERR_RETURN(READ_AN_X1_OUI_UPRr(pc, &AN_X1_CONTROL_OUI_UPPERr_reg)); 8120 PHYMOD_IF_ERR_RETURN(READ_AN_X4_CTLSr(pc, &AN_X4_CTLSr_t_reg)); 8121 8122 oui->oui = AN_X1_OUI_LWRr_GET(AN_X1_CONTROL_OUI_LOWERr_reg); 8123 oui->oui |= ((AN_X1_OUI_UPRr_GET(AN_X1_CONTROL_OUI_UPPERr_reg)) << 16); 8124 8125 oui_override = AN_X4_CTLSr_OUI_CONTROLf_GET(AN_X4_CTLSr_t_reg); 8126 8127 oui->oui_override_hpam_adv = (oui_override >> 5) & 1; 8128 oui->oui_override_hpam_det = (oui_override >> 4) & 1; 8129 oui->oui_override_bam73_adv = (oui_override >> 3) & 1; 8130 oui->oui_override_bam73_det = (oui_override >> 2) & 1; 8131 oui->oui_override_bam37_adv = (oui_override >> 1) & 1; 8132 oui->oui_override_bam37_det = (oui_override >> 0) & 1; 8133 8134 return PHYMOD_E_NONE; 8135 } 8136 8137 int temod_fec_correctable_counter_get(PHYMOD_ST* pc, uint32_t* count) 8138 { 8139 RX_X4_FEC_CORRBLKSLr_t countl; 8140 RX_X4_FEC_CORRBLKSHr_t counth; 8141 RX_X4_T12_FEC_CORRBLKSLr_t count12l; 8142 RX_X4_T12_FEC_CORRBLKSHr_t count12h; 8143 uint32_t count_vl1 = 0, count_vl2 = 0; 8144 8145 /* Per lane based counter */ 8146 /* 1 physical lane can map to 2 virtual lane */ 8147 PHYMOD_IF_ERR_RETURN (READ_RX_X4_FEC_CORRBLKSLr(pc, &countl)); 8148 PHYMOD_IF_ERR_RETURN (READ_RX_X4_FEC_CORRBLKSHr(pc, &counth)); 8149 count_vl1 = (RX_X4_FEC_CORRBLKSHr_GET(counth) << 16) | (RX_X4_FEC_CORRBLKSLr_GET(countl) & 0xffff); 8150 8151 PHYMOD_IF_ERR_RETURN (READ_RX_X4_T12_FEC_CORRBLKSLr(pc, &count12l)); 8152 PHYMOD_IF_ERR_RETURN (READ_RX_X4_T12_FEC_CORRBLKSHr(pc, &count12h)); 8153 count_vl2 = (RX_X4_T12_FEC_CORRBLKSHr_GET(count12h) << 16) | (RX_X4_T12_FEC_CORRBLKSLr_GET(count12l) & 0xffff); 8154 8155 /* Check overflow */ 8156 /* If count_vl1 + count_vl2 > 0xffffffff, will casue overflow, return 0xffffffff */ 8157 if (count_vl2 > 0xffffffff - count_vl1) { 8158 *count = 0xffffffff; 8159 } else { 8160 *count = count_vl1 + count_vl2; 8161 } 8162 8163 return PHYMOD_E_NONE; 8164 } 8165 8166 int temod_fec_uncorrectable_counter_get(PHYMOD_ST* pc, uint32_t* count) 8167 { 8168 RX_X4_FEC_UNCORRBLKSLr_t countl; 8169 RX_X4_FEC_UNCORRBLKSHr_t counth; 8170 RX_X4_T12_FEC_UNCORRBLKSLr_t count12l; 8171 RX_X4_T12_FEC_UNCORRBLKSHr_t count12h; 8172 uint32_t count_vl1 = 0, count_vl2 = 0; 8173 8174 /* Per lane based counter */ 8175 /* 1 physical lane can map to 2 virtual lane */ 8176 PHYMOD_IF_ERR_RETURN(READ_RX_X4_FEC_UNCORRBLKSLr(pc, &countl)); 8177 PHYMOD_IF_ERR_RETURN(READ_RX_X4_FEC_UNCORRBLKSHr(pc, &counth)); 8178 count_vl1 = (RX_X4_FEC_UNCORRBLKSHr_GET(counth) << 16) | (RX_X4_FEC_UNCORRBLKSLr_GET(countl) & 0xffff); 8179 8180 PHYMOD_IF_ERR_RETURN(READ_RX_X4_T12_FEC_UNCORRBLKSLr(pc, &count12l)); 8181 PHYMOD_IF_ERR_RETURN(READ_RX_X4_T12_FEC_UNCORRBLKSHr(pc, &count12h)); 8182 count_vl2 = (RX_X4_T12_FEC_UNCORRBLKSHr_GET(count12h) << 16) | (RX_X4_T12_FEC_UNCORRBLKSLr_GET(count12l) & 0xffff); 8183 8184 /* Check overflow */ 8185 if (count_vl2 > 0xffffffff - count_vl1) { 8186 *count = 0xffffffff; 8187 } else { 8188 *count = count_vl1 + count_vl2; 8189 } 8190 8191 return PHYMOD_E_NONE; 8192 } 8193 8194 8195 /* The number of cl82 BIP error */ 8196 int temod_bip_error_counter_get(PHYMOD_ST* pc, uint32_t* count) 8197 { 8198 RX_X4_BERCNTr_t bercnt; 8199 8200 PHYMOD_IF_ERR_RETURN (READ_RX_X4_BERCNTr(pc, &bercnt)); 8201 *count = RX_X4_BERCNTr_BIP_ERROR_COUNT_PER_LANEf_GET(bercnt); 8202 8203 return PHYMOD_E_NONE; 8204 } 8205 8206 /* The number of times BER_BAD_SH state is entered for cl49. */ 8207 int temod_cl49_ber_counter_get(PHYMOD_ST* pc, uint32_t* count) 8208 { 8209 RX_X4_BERCNTr_t bercnt; 8210 8211 PHYMOD_IF_ERR_RETURN (READ_RX_X4_BERCNTr(pc, &bercnt)); 8212 *count = RX_X4_BERCNTr_BER_COUNT_PER_LNf_GET(bercnt); 8213 8214 return PHYMOD_E_NONE; 8215 } 8216 8217 /* The number of times BER_BAD_SH state is entered for cl82. */ 8218 int temod_cl82_ber_counter_get(PHYMOD_ST* pc, uint32_t* count) 8219 { 8220 RX_X4_BERCNTr_t count_lo; 8221 CL82_BER_HO_STSr_t count_ho; 8222 8223 PHYMOD_IF_ERR_RETURN (READ_RX_X4_BERCNTr(pc, &count_lo)); 8224 PHYMOD_IF_ERR_RETURN (READ_CL82_BER_HO_STSr(pc, &count_ho)); 8225 8226 *count = (CL82_BER_HO_STSr_BER_HOf_GET(count_ho) << 8) | (RX_X4_BERCNTr_BER_COUNT_PER_LNf_GET(count_lo)); 8227 8228 return PHYMOD_E_NONE; 8229 } 8230 8231 int temod_hg2_codec_set(PHYMOD_ST* pc, temod_hg2_codec_t hg2_codec) 8232 { 8233 TX_X4_ENC0r_t TX_X4_ENC0_reg; 8234 RX_X4_DEC_CTL0r_t RX_X4_DEC_CTL0_reg; 8235 8236 READ_TX_X4_ENC0r(pc, &TX_X4_ENC0_reg); 8237 READ_RX_X4_DEC_CTL0r(pc, &RX_X4_DEC_CTL0_reg); 8238 switch (hg2_codec) { 8239 case TEMOD_HG2_CODEC_OFF: 8240 TX_X4_ENC0r_HG2_ENABLEf_SET(TX_X4_ENC0_reg, 0); 8241 TX_X4_ENC0r_HG2_CODECf_SET(TX_X4_ENC0_reg, 1); 8242 TX_X4_ENC0r_HG2_MESSAGE_INVALID_CODE_ENABLEf_SET(TX_X4_ENC0_reg, 1); 8243 RX_X4_DEC_CTL0r_HG2_ENABLEf_SET(RX_X4_DEC_CTL0_reg, 0); 8244 RX_X4_DEC_CTL0r_HG2_CODECf_SET(RX_X4_DEC_CTL0_reg, 1); 8245 RX_X4_DEC_CTL0r_HG2_MESSAGE_INVALID_CODE_ENABLEf_SET(RX_X4_DEC_CTL0_reg, 1); 8246 break; 8247 case TEMOD_HG2_CODEC_ON_8BYTE_IPG: 8248 TX_X4_ENC0r_HG2_ENABLEf_SET(TX_X4_ENC0_reg, 1); 8249 TX_X4_ENC0r_HG2_CODECf_SET(TX_X4_ENC0_reg, 1); 8250 TX_X4_ENC0r_HG2_MESSAGE_INVALID_CODE_ENABLEf_SET(TX_X4_ENC0_reg, 1); 8251 RX_X4_DEC_CTL0r_HG2_ENABLEf_SET(RX_X4_DEC_CTL0_reg, 1); 8252 RX_X4_DEC_CTL0r_HG2_CODECf_SET(RX_X4_DEC_CTL0_reg, 1); 8253 RX_X4_DEC_CTL0r_HG2_MESSAGE_INVALID_CODE_ENABLEf_SET(RX_X4_DEC_CTL0_reg, 1); 8254 break; 8255 case TEMOD_HG2_CODEC_ON_9BYTE_IPG: 8256 TX_X4_ENC0r_HG2_ENABLEf_SET(TX_X4_ENC0_reg, 1); 8257 TX_X4_ENC0r_HG2_CODECf_SET(TX_X4_ENC0_reg, 0); 8258 TX_X4_ENC0r_HG2_MESSAGE_INVALID_CODE_ENABLEf_SET(TX_X4_ENC0_reg, 1); 8259 RX_X4_DEC_CTL0r_HG2_ENABLEf_SET(RX_X4_DEC_CTL0_reg, 1); 8260 RX_X4_DEC_CTL0r_HG2_CODECf_SET(RX_X4_DEC_CTL0_reg, 0); 8261 RX_X4_DEC_CTL0r_HG2_MESSAGE_INVALID_CODE_ENABLEf_SET(RX_X4_DEC_CTL0_reg, 1); 8262 break; 8263 default: 8264 TX_X4_ENC0r_HG2_ENABLEf_SET(TX_X4_ENC0_reg, 0); 8265 TX_X4_ENC0r_HG2_CODECf_SET(TX_X4_ENC0_reg, 1); 8266 TX_X4_ENC0r_HG2_MESSAGE_INVALID_CODE_ENABLEf_SET(TX_X4_ENC0_reg, 1); 8267 RX_X4_DEC_CTL0r_HG2_ENABLEf_SET(RX_X4_DEC_CTL0_reg, 0); 8268 RX_X4_DEC_CTL0r_HG2_CODECf_SET(RX_X4_DEC_CTL0_reg, 1); 8269 RX_X4_DEC_CTL0r_HG2_MESSAGE_INVALID_CODE_ENABLEf_SET(RX_X4_DEC_CTL0_reg, 1); 8270 break; 8271 } 8272 MODIFY_RX_X4_DEC_CTL0r(pc, RX_X4_DEC_CTL0_reg); 8273 MODIFY_TX_X4_ENC0r(pc,TX_X4_ENC0_reg); 8274 8275 return PHYMOD_E_NONE; 8276 } 8277 8278 int temod_hg2_codec_get(PHYMOD_ST* pc, temod_hg2_codec_t* hg2_codec) 8279 { 8280 TX_X4_ENC0r_t TX_X4_ENC0_reg; 8281 8282 READ_TX_X4_ENC0r(pc, &TX_X4_ENC0_reg); 8283 if (TX_X4_ENC0r_HG2_ENABLEf_GET(TX_X4_ENC0_reg)) { 8284 if (TX_X4_ENC0r_HG2_CODECf_GET(TX_X4_ENC0_reg)) { 8285 *hg2_codec = TEMOD_HG2_CODEC_ON_8BYTE_IPG; 8286 } else { 8287 *hg2_codec = TEMOD_HG2_CODEC_ON_9BYTE_IPG; 8288 } 8289 } else { 8290 *hg2_codec = TEMOD_HG2_CODEC_OFF; 8291 } 8292 return PHYMOD_E_NONE; 8293 } 8294 8295 int temod_sgmii_master_set(PHYMOD_ST* pc, int master) 8296 { 8297 AN_X4_LOC_DEV_CL37_BASE_ABILr_t reg_cl37_base_abilities; 8298 8299 AN_X4_LOC_DEV_CL37_BASE_ABILr_CLR(reg_cl37_base_abilities); 8300 AN_X4_LOC_DEV_CL37_BASE_ABILr_SGMII_MASTER_MODEf_SET(reg_cl37_base_abilities, master); 8301 8302 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_LOC_DEV_CL37_BASE_ABILr(pc, reg_cl37_base_abilities)); 8303 8304 return PHYMOD_E_NONE; 8305 } 8306 8307 int temod_sgmii_master_get(PHYMOD_ST* pc, int* master) 8308 { 8309 AN_X4_LOC_DEV_CL37_BASE_ABILr_t reg_cl37_base_abilities; 8310 8311 PHYMOD_IF_ERR_RETURN (READ_AN_X4_LOC_DEV_CL37_BASE_ABILr(pc, ®_cl37_base_abilities)); 8312 *master = AN_X4_LOC_DEV_CL37_BASE_ABILr_SGMII_MASTER_MODEf_GET(reg_cl37_base_abilities); 8313 8314 return PHYMOD_E_NONE; 8315 } 8316 8317 STATIC 8318 int _temod_rx_phy_lane_get(PHYMOD_ST *pc, int rx_logical_lane, int* rx_phy_lane) 8319 { 8320 MAIN0_LN_SWPr_t reg_lane_swap; 8321 phymod_access_t pa_copy; 8322 8323 PHYMOD_MEMCPY(&pa_copy, pc, sizeof(pa_copy)); 8324 8325 /*always use lane 0 copy since register is single copy */ 8326 pa_copy.lane_mask = 0x1; 8327 8328 PHYMOD_IF_ERR_RETURN 8329 (READ_MAIN0_LN_SWPr(&pa_copy, ®_lane_swap)); 8330 8331 switch (rx_logical_lane) { 8332 case 0: 8333 *rx_phy_lane = MAIN0_LN_SWPr_LOG0_TO_PHY_LNSWAP_SELf_GET(reg_lane_swap); 8334 break; 8335 case 1: 8336 *rx_phy_lane = MAIN0_LN_SWPr_LOG1_TO_PHY_LNSWAP_SELf_GET(reg_lane_swap); 8337 break; 8338 case 2: 8339 *rx_phy_lane = MAIN0_LN_SWPr_LOG2_TO_PHY_LNSWAP_SELf_GET(reg_lane_swap); 8340 break; 8341 case 3: 8342 *rx_phy_lane = MAIN0_LN_SWPr_LOG3_TO_PHY_LNSWAP_SELf_GET(reg_lane_swap); 8343 break; 8344 default: 8345 return PHYMOD_E_PARAM; 8346 } 8347 8348 return PHYMOD_E_NONE; 8349 } 8350 8351 int temod_synce_mode_set(PHYMOD_ST *pc, int mode) 8352 { 8353 int start_lane = 0, num_lane = 0, phy_lane = 0; 8354 MAIN0_SYNCE_CTLr_t reg_main0_synce_ctl; 8355 8356 PHYMOD_IF_ERR_RETURN 8357 (phymod_util_lane_config_get(pc, &start_lane, &num_lane)); 8358 8359 PHYMOD_IF_ERR_RETURN 8360 (_temod_rx_phy_lane_get(pc, start_lane, &phy_lane)); 8361 8362 MAIN0_SYNCE_CTLr_CLR(reg_main0_synce_ctl); 8363 PHYMOD_IF_ERR_RETURN(READ_MAIN0_SYNCE_CTLr(pc, ®_main0_synce_ctl)); 8364 8365 switch(phy_lane) { 8366 case 0: 8367 MAIN0_SYNCE_CTLr_SYNCE_MODE_PHY_LN0f_SET(reg_main0_synce_ctl, mode); 8368 break; 8369 case 1: 8370 MAIN0_SYNCE_CTLr_SYNCE_MODE_PHY_LN1f_SET(reg_main0_synce_ctl, mode); 8371 break; 8372 case 2: 8373 MAIN0_SYNCE_CTLr_SYNCE_MODE_PHY_LN2f_SET(reg_main0_synce_ctl, mode); 8374 break; 8375 case 3: 8376 MAIN0_SYNCE_CTLr_SYNCE_MODE_PHY_LN3f_SET(reg_main0_synce_ctl, mode); 8377 break; 8378 default: 8379 return PHYMOD_E_PARAM; 8380 } 8381 8382 PHYMOD_IF_ERR_RETURN(MODIFY_MAIN0_SYNCE_CTLr(pc, reg_main0_synce_ctl)); 8383 8384 return PHYMOD_E_NONE; 8385 } 8386 8387 int temod_synce_mode_get(PHYMOD_ST *pc, int *mode) 8388 { 8389 int start_lane = 0, num_lane = 0, phy_lane = 0; 8390 MAIN0_SYNCE_CTLr_t reg_main0_synce_ctl; 8391 8392 PHYMOD_IF_ERR_RETURN 8393 (phymod_util_lane_config_get(pc, &start_lane, &num_lane)); 8394 8395 PHYMOD_IF_ERR_RETURN 8396 (_temod_rx_phy_lane_get(pc, start_lane, &phy_lane)); 8397 8398 MAIN0_SYNCE_CTLr_CLR(reg_main0_synce_ctl); 8399 PHYMOD_IF_ERR_RETURN(READ_MAIN0_SYNCE_CTLr(pc, ®_main0_synce_ctl)); 8400 8401 switch(phy_lane) { 8402 case 0: 8403 *mode = MAIN0_SYNCE_CTLr_SYNCE_MODE_PHY_LN0f_GET(reg_main0_synce_ctl); 8404 break; 8405 case 1: 8406 *mode = MAIN0_SYNCE_CTLr_SYNCE_MODE_PHY_LN1f_GET(reg_main0_synce_ctl); 8407 break; 8408 case 2: 8409 *mode = MAIN0_SYNCE_CTLr_SYNCE_MODE_PHY_LN2f_GET(reg_main0_synce_ctl); 8410 break; 8411 case 3: 8412 *mode = MAIN0_SYNCE_CTLr_SYNCE_MODE_PHY_LN3f_GET(reg_main0_synce_ctl); 8413 break; 8414 default: 8415 return PHYMOD_E_PARAM; 8416 } 8417 8418 return PHYMOD_E_NONE; 8419 } 8420 #endif