tePCSRegEnums.h (255711B)
1 /*---------------------------------------------------------------------- 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * Broadcom Corporation 8 * Proprietary and Confidential information 9 * All rights reserved 10 * This source file is the property of Broadcom Corporation, and 11 * may not be copied or distributed in any isomorphic form without the 12 * prior written consent of Broadcom Corporation. 13 *---------------------------------------------------------------------*/ 14 15 #ifndef __PCS_ENUMS_H__ 16 #define __PCS_ENUMS_H__ 17 /**************************************************************************** 18 * Core Enums. 19 */ 20 /**************************************************************************** 21 * Enums: an_x4_sw_management_cl36TxEEEStates_l 22 */ 23 #define an_x4_sw_management_cl36TxEEEStates_l_TX_REFRESH 8 24 #define an_x4_sw_management_cl36TxEEEStates_l_TX_QUIET 4 25 #define an_x4_sw_management_cl36TxEEEStates_l_TX_SLEEP 2 26 #define an_x4_sw_management_cl36TxEEEStates_l_TX_ACTIVE 1 27 28 /**************************************************************************** 29 * Enums: an_x4_sw_management_cl36TxEEEStates_c 30 */ 31 #define an_x4_sw_management_cl36TxEEEStates_c_TX_REFRESH 3 32 #define an_x4_sw_management_cl36TxEEEStates_c_TX_QUIET 2 33 #define an_x4_sw_management_cl36TxEEEStates_c_TX_SLEEP 1 34 #define an_x4_sw_management_cl36TxEEEStates_c_TX_ACTIVE 0 35 36 /**************************************************************************** 37 * Enums: an_x4_sw_management_cl49TxEEEStates_l 38 */ 39 #define an_x4_sw_management_cl49TxEEEStates_l_SCR_RESET_2 64 40 #define an_x4_sw_management_cl49TxEEEStates_l_SCR_RESET_1 32 41 #define an_x4_sw_management_cl49TxEEEStates_l_TX_WAKE 16 42 #define an_x4_sw_management_cl49TxEEEStates_l_TX_REFRESH 8 43 #define an_x4_sw_management_cl49TxEEEStates_l_TX_QUIET 4 44 #define an_x4_sw_management_cl49TxEEEStates_l_TX_SLEEP 2 45 #define an_x4_sw_management_cl49TxEEEStates_l_TX_ACTIVE 1 46 47 /**************************************************************************** 48 * Enums: an_x4_sw_management_cl49TxEEEStates_c 49 */ 50 #define an_x4_sw_management_cl49TxEEEStates_c_SCR_RESET_2 6 51 #define an_x4_sw_management_cl49TxEEEStates_c_SCR_RESET_1 5 52 #define an_x4_sw_management_cl49TxEEEStates_c_TX_WAKE 4 53 #define an_x4_sw_management_cl49TxEEEStates_c_TX_REFRESH 3 54 #define an_x4_sw_management_cl49TxEEEStates_c_TX_QUIET 2 55 #define an_x4_sw_management_cl49TxEEEStates_c_TX_SLEEP 1 56 #define an_x4_sw_management_cl49TxEEEStates_c_TX_ACTIVE 0 57 58 /**************************************************************************** 59 * Enums: an_x4_sw_management_cl36RxEEEStates_l 60 */ 61 #define an_x4_sw_management_cl36RxEEEStates_l_RX_LINK_FAIL 32 62 #define an_x4_sw_management_cl36RxEEEStates_l_RX_WTF 16 63 #define an_x4_sw_management_cl36RxEEEStates_l_RX_WAKE 8 64 #define an_x4_sw_management_cl36RxEEEStates_l_RX_QUIET 4 65 #define an_x4_sw_management_cl36RxEEEStates_l_RX_SLEEP 2 66 #define an_x4_sw_management_cl36RxEEEStates_l_RX_ACTIVE 1 67 68 /**************************************************************************** 69 * Enums: an_x4_sw_management_cl36RxEEEStates_c 70 */ 71 #define an_x4_sw_management_cl36RxEEEStates_c_RX_LINK_FAIL 5 72 #define an_x4_sw_management_cl36RxEEEStates_c_RX_WTF 4 73 #define an_x4_sw_management_cl36RxEEEStates_c_RX_WAKE 3 74 #define an_x4_sw_management_cl36RxEEEStates_c_RX_QUIET 2 75 #define an_x4_sw_management_cl36RxEEEStates_c_RX_SLEEP 1 76 #define an_x4_sw_management_cl36RxEEEStates_c_RX_ACTIVE 0 77 78 /**************************************************************************** 79 * Enums: an_x4_sw_management_cl49RxEEEStates_l 80 */ 81 #define an_x4_sw_management_cl49RxEEEStates_l_RX_LINK_FAIL 32 82 #define an_x4_sw_management_cl49RxEEEStates_l_RX_WTF 16 83 #define an_x4_sw_management_cl49RxEEEStates_l_RX_WAKE 8 84 #define an_x4_sw_management_cl49RxEEEStates_l_RX_QUIET 4 85 #define an_x4_sw_management_cl49RxEEEStates_l_RX_SLEEP 2 86 #define an_x4_sw_management_cl49RxEEEStates_l_RX_ACTIVE 1 87 88 /**************************************************************************** 89 * Enums: an_x4_sw_management_cl49RxEEEStates_c 90 */ 91 #define an_x4_sw_management_cl49RxEEEStates_c_RX_LINK_FAIL 5 92 #define an_x4_sw_management_cl49RxEEEStates_c_RX_WTF 4 93 #define an_x4_sw_management_cl49RxEEEStates_c_RX_WAKE 3 94 #define an_x4_sw_management_cl49RxEEEStates_c_RX_QUIET 2 95 #define an_x4_sw_management_cl49RxEEEStates_c_RX_SLEEP 1 96 #define an_x4_sw_management_cl49RxEEEStates_c_RX_ACTIVE 0 97 98 /**************************************************************************** 99 * Enums: an_x4_sw_management_cl48TxEEEStates_l 100 */ 101 #define an_x4_sw_management_cl48TxEEEStates_l_TX_REFRESH 8 102 #define an_x4_sw_management_cl48TxEEEStates_l_TX_QUIET 4 103 #define an_x4_sw_management_cl48TxEEEStates_l_TX_SLEEP 2 104 #define an_x4_sw_management_cl48TxEEEStates_l_TX_ACTIVE 1 105 106 /**************************************************************************** 107 * Enums: an_x4_sw_management_cl48TxEEEStates_c 108 */ 109 #define an_x4_sw_management_cl48TxEEEStates_c_TX_REFRESH 3 110 #define an_x4_sw_management_cl48TxEEEStates_c_TX_QUIET 2 111 #define an_x4_sw_management_cl48TxEEEStates_c_TX_SLEEP 1 112 #define an_x4_sw_management_cl48TxEEEStates_c_TX_ACTIVE 0 113 114 /**************************************************************************** 115 * Enums: an_x4_sw_management_cl48RxEEEStates_l 116 */ 117 #define an_x4_sw_management_cl48RxEEEStates_l_RX_LINK_FAIL 32 118 #define an_x4_sw_management_cl48RxEEEStates_l_RX_WAKE 16 119 #define an_x4_sw_management_cl48RxEEEStates_l_RX_QUIET 8 120 #define an_x4_sw_management_cl48RxEEEStates_l_RX_DEACT 4 121 #define an_x4_sw_management_cl48RxEEEStates_l_RX_SLEEP 2 122 #define an_x4_sw_management_cl48RxEEEStates_l_RX_ACTIVE 1 123 124 /**************************************************************************** 125 * Enums: an_x4_sw_management_cl48RxEEEStates_c 126 */ 127 #define an_x4_sw_management_cl48RxEEEStates_c_RX_LINK_FAIL 5 128 #define an_x4_sw_management_cl48RxEEEStates_c_RX_WAKE 4 129 #define an_x4_sw_management_cl48RxEEEStates_c_RX_QUIET 3 130 #define an_x4_sw_management_cl48RxEEEStates_c_RX_DEACT 2 131 #define an_x4_sw_management_cl48RxEEEStates_c_RX_SLEEP 1 132 #define an_x4_sw_management_cl48RxEEEStates_c_RX_ACTIVE 0 133 134 /**************************************************************************** 135 * Enums: an_x4_sw_management_IQP_Options 136 */ 137 #define an_x4_sw_management_IQP_Options_i50uA 0 138 #define an_x4_sw_management_IQP_Options_i100uA 1 139 #define an_x4_sw_management_IQP_Options_i150uA 2 140 #define an_x4_sw_management_IQP_Options_i200uA 3 141 #define an_x4_sw_management_IQP_Options_i250uA 4 142 #define an_x4_sw_management_IQP_Options_i300uA 5 143 #define an_x4_sw_management_IQP_Options_i350uA 6 144 #define an_x4_sw_management_IQP_Options_i400uA 7 145 #define an_x4_sw_management_IQP_Options_i450uA 8 146 #define an_x4_sw_management_IQP_Options_i500uA 9 147 #define an_x4_sw_management_IQP_Options_i550uA 10 148 #define an_x4_sw_management_IQP_Options_i600uA 11 149 #define an_x4_sw_management_IQP_Options_i650uA 12 150 #define an_x4_sw_management_IQP_Options_i700uA 13 151 #define an_x4_sw_management_IQP_Options_i750uA 14 152 #define an_x4_sw_management_IQP_Options_i800uA 15 153 154 /**************************************************************************** 155 * Enums: an_x4_sw_management_IDriver_Options 156 */ 157 #define an_x4_sw_management_IDriver_Options_v680mV 0 158 #define an_x4_sw_management_IDriver_Options_v730mV 1 159 #define an_x4_sw_management_IDriver_Options_v780mV 2 160 #define an_x4_sw_management_IDriver_Options_v830mV 3 161 #define an_x4_sw_management_IDriver_Options_v880mV 4 162 #define an_x4_sw_management_IDriver_Options_v930mV 5 163 #define an_x4_sw_management_IDriver_Options_v980mV 6 164 #define an_x4_sw_management_IDriver_Options_v1010mV 7 165 #define an_x4_sw_management_IDriver_Options_v1040mV 8 166 #define an_x4_sw_management_IDriver_Options_v1060mV 9 167 #define an_x4_sw_management_IDriver_Options_v1070mV 10 168 #define an_x4_sw_management_IDriver_Options_v1080mV 11 169 #define an_x4_sw_management_IDriver_Options_v1085mV 12 170 #define an_x4_sw_management_IDriver_Options_v1090mV 13 171 #define an_x4_sw_management_IDriver_Options_v1095mV 14 172 #define an_x4_sw_management_IDriver_Options_v1100mV 15 173 174 /**************************************************************************** 175 * Enums: an_x4_sw_management_operationModes 176 */ 177 #define an_x4_sw_management_operationModes_XGXS 0 178 #define an_x4_sw_management_operationModes_XGXG_nCC 1 179 #define an_x4_sw_management_operationModes_Indlane_OS8 4 180 #define an_x4_sw_management_operationModes_IndLane_OS5 5 181 #define an_x4_sw_management_operationModes_PCI 7 182 #define an_x4_sw_management_operationModes_XGXS_nLQ 8 183 #define an_x4_sw_management_operationModes_XGXS_nLQnCC 9 184 #define an_x4_sw_management_operationModes_PBypass 10 185 #define an_x4_sw_management_operationModes_PBypass_nDSK 11 186 #define an_x4_sw_management_operationModes_ComboCoreMode 12 187 #define an_x4_sw_management_operationModes_Clocks_off 15 188 189 /**************************************************************************** 190 * Enums: an_x4_sw_management_synce_enum 191 */ 192 #define an_x4_sw_management_synce_enum_SYNCE_NO_DIV 0 193 #define an_x4_sw_management_synce_enum_SYNCE_DIV_7 1 194 #define an_x4_sw_management_synce_enum_SYNCE_DIV_11 2 195 196 /**************************************************************************** 197 * Enums: an_x4_sw_management_operationSpeeds 198 */ 199 #define an_x4_sw_management_operationSpeeds_SPEED_2p5G_X1_10p3125 56 200 #define an_x4_sw_management_operationSpeeds_SPEED_1000M_10p3125 55 201 #define an_x4_sw_management_operationSpeeds_SPEED_100M_10p3125 54 202 #define an_x4_sw_management_operationSpeeds_SPEED_10M_10p3125 53 203 #define an_x4_sw_management_operationSpeeds_SPEED_10p5G_X4 50 204 #define an_x4_sw_management_operationSpeeds_SPEED_5G_KR1 49 205 #define an_x4_sw_management_operationSpeeds_SPEED_127G_X12 39 206 #define an_x4_sw_management_operationSpeeds_SPEED_120G_X12 38 207 #define an_x4_sw_management_operationSpeeds_SPEED_107G_X10 37 208 #define an_x4_sw_management_operationSpeeds_SPEED_100G_CR10 36 209 #define an_x4_sw_management_operationSpeeds_SPEED_42G_X4 35 210 #define an_x4_sw_management_operationSpeeds_SPEED_40G_CR4 34 211 #define an_x4_sw_management_operationSpeeds_SPEED_40G_KR4 33 212 #define an_x4_sw_management_operationSpeeds_SPEED_21G_X2 32 213 #define an_x4_sw_management_operationSpeeds_SPEED_20G_CR2 31 214 #define an_x4_sw_management_operationSpeeds_SPEED_20G_KR2 30 215 #define an_x4_sw_management_operationSpeeds_SPEED_10p6_X1 29 216 #define an_x4_sw_management_operationSpeeds_SPEED_10G_KR1 28 217 #define an_x4_sw_management_operationSpeeds_SPEED_40G_X4 27 218 #define an_x4_sw_management_operationSpeeds_SPEED_20G_X2 26 219 #define an_x4_sw_management_operationSpeeds_SPEED_20G_CX2 25 220 #define an_x4_sw_management_operationSpeeds_SPEED_31p5G_KR4 24 221 #define an_x4_sw_management_operationSpeeds_SPEED_31p5G_X4 23 222 #define an_x4_sw_management_operationSpeeds_SPEED_15p75G_X2 22 223 #define an_x4_sw_management_operationSpeeds_SPEED_25p45G_X4 21 224 #define an_x4_sw_management_operationSpeeds_SPEED_12p7G_X2 20 225 #define an_x4_sw_management_operationSpeeds_SPEED_21G_X4 19 226 #define an_x4_sw_management_operationSpeeds_SPEED_10p5G_X2 18 227 #define an_x4_sw_management_operationSpeeds_SPEED_20G_X4 17 228 #define an_x4_sw_management_operationSpeeds_SPEED_10G_X2 16 229 #define an_x4_sw_management_operationSpeeds_SPEED_10G_CX2 15 230 #define an_x4_sw_management_operationSpeeds_SPEED_20G_CX4 14 231 #define an_x4_sw_management_operationSpeeds_SPEED_16G_X4 13 232 #define an_x4_sw_management_operationSpeeds_SPEED_15G_X4 12 233 #define an_x4_sw_management_operationSpeeds_SPEED_13G_X4 11 234 #define an_x4_sw_management_operationSpeeds_SPEED_10G_X4 10 235 #define an_x4_sw_management_operationSpeeds_SPEED_10G_KX4 9 236 #define an_x4_sw_management_operationSpeeds_SPEED_10G_CX4 8 237 #define an_x4_sw_management_operationSpeeds_SPEED_5G_X1 7 238 #define an_x4_sw_management_operationSpeeds_SPEED_2p5G_X1 6 239 #define an_x4_sw_management_operationSpeeds_SPEED_1G_KX1 5 240 #define an_x4_sw_management_operationSpeeds_SPEED_1G_CX1 4 241 #define an_x4_sw_management_operationSpeeds_SPEED_1000M 3 242 #define an_x4_sw_management_operationSpeeds_SPEED_100M 2 243 #define an_x4_sw_management_operationSpeeds_SPEED_10M 1 244 245 /**************************************************************************** 246 * Enums: an_x4_sw_management_actualSpeeds 247 */ 248 #define an_x4_sw_management_actualSpeeds_dr_10M 0 249 #define an_x4_sw_management_actualSpeeds_dr_100M 1 250 #define an_x4_sw_management_actualSpeeds_dr_1G 2 251 #define an_x4_sw_management_actualSpeeds_dr_2p5G 3 252 #define an_x4_sw_management_actualSpeeds_dr_5G_X4 4 253 #define an_x4_sw_management_actualSpeeds_dr_6G_X4 5 254 #define an_x4_sw_management_actualSpeeds_dr_10G_HiG 6 255 #define an_x4_sw_management_actualSpeeds_dr_10G_CX4 7 256 #define an_x4_sw_management_actualSpeeds_dr_12G_HiG 8 257 #define an_x4_sw_management_actualSpeeds_dr_12p5G_X4 9 258 #define an_x4_sw_management_actualSpeeds_dr_13G_X4 10 259 #define an_x4_sw_management_actualSpeeds_dr_15G_X4 11 260 #define an_x4_sw_management_actualSpeeds_dr_16G_X4 12 261 #define an_x4_sw_management_actualSpeeds_dr_1G_KX 13 262 #define an_x4_sw_management_actualSpeeds_dr_10G_KX4 14 263 #define an_x4_sw_management_actualSpeeds_dr_10G_KR 15 264 #define an_x4_sw_management_actualSpeeds_dr_5G 16 265 #define an_x4_sw_management_actualSpeeds_dr_6p4G 17 266 #define an_x4_sw_management_actualSpeeds_dr_20G_X4 18 267 #define an_x4_sw_management_actualSpeeds_dr_21G_X4 19 268 #define an_x4_sw_management_actualSpeeds_dr_25G_X4 20 269 #define an_x4_sw_management_actualSpeeds_dr_10G_HiG_DXGXS 21 270 #define an_x4_sw_management_actualSpeeds_dr_10G_DXGXS 22 271 #define an_x4_sw_management_actualSpeeds_dr_10p5G_HiG_DXGXS 23 272 #define an_x4_sw_management_actualSpeeds_dr_10p5G_DXGXS 24 273 #define an_x4_sw_management_actualSpeeds_dr_12p773G_HiG_DXGXS 25 274 #define an_x4_sw_management_actualSpeeds_dr_12p773G_DXGXS 26 275 #define an_x4_sw_management_actualSpeeds_dr_10G_XFI 27 276 #define an_x4_sw_management_actualSpeeds_dr_40G 28 277 #define an_x4_sw_management_actualSpeeds_dr_20G_HiG_DXGXS 29 278 #define an_x4_sw_management_actualSpeeds_dr_20G_DXGXS 30 279 #define an_x4_sw_management_actualSpeeds_dr_10G_SFI 31 280 #define an_x4_sw_management_actualSpeeds_dr_31p5G 32 281 #define an_x4_sw_management_actualSpeeds_dr_32p7G 33 282 #define an_x4_sw_management_actualSpeeds_dr_20G_SCR 34 283 #define an_x4_sw_management_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 284 #define an_x4_sw_management_actualSpeeds_dr_10G_DXGXS_SCR 36 285 #define an_x4_sw_management_actualSpeeds_dr_12G_R2 37 286 #define an_x4_sw_management_actualSpeeds_dr_10G_X2 38 287 #define an_x4_sw_management_actualSpeeds_dr_40G_KR4 39 288 #define an_x4_sw_management_actualSpeeds_dr_40G_CR4 40 289 #define an_x4_sw_management_actualSpeeds_dr_100G_CR10 41 290 #define an_x4_sw_management_actualSpeeds_dr_15p75G_DXGXS 44 291 #define an_x4_sw_management_actualSpeeds_dr_20G_KR2 57 292 #define an_x4_sw_management_actualSpeeds_dr_20G_CR2 58 293 294 /**************************************************************************** 295 * Enums: an_x4_sw_management_actualSpeedsMisc1 296 */ 297 #define an_x4_sw_management_actualSpeedsMisc1_dr_2500BRCM_X1 16 298 #define an_x4_sw_management_actualSpeedsMisc1_dr_5000BRCM_X4 17 299 #define an_x4_sw_management_actualSpeedsMisc1_dr_6000BRCM_X4 18 300 #define an_x4_sw_management_actualSpeedsMisc1_dr_10GHiGig_X4 19 301 #define an_x4_sw_management_actualSpeedsMisc1_dr_10GBASE_CX4 20 302 #define an_x4_sw_management_actualSpeedsMisc1_dr_12GHiGig_X4 21 303 #define an_x4_sw_management_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 304 #define an_x4_sw_management_actualSpeedsMisc1_dr_13GHiGig_X4 23 305 #define an_x4_sw_management_actualSpeedsMisc1_dr_15GHiGig_X4 24 306 #define an_x4_sw_management_actualSpeedsMisc1_dr_16GHiGig_X4 25 307 #define an_x4_sw_management_actualSpeedsMisc1_dr_5000BRCM_X1 26 308 #define an_x4_sw_management_actualSpeedsMisc1_dr_6363BRCM_X1 27 309 #define an_x4_sw_management_actualSpeedsMisc1_dr_20GHiGig_X4 28 310 #define an_x4_sw_management_actualSpeedsMisc1_dr_21GHiGig_X4 29 311 #define an_x4_sw_management_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 312 #define an_x4_sw_management_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 313 314 /**************************************************************************** 315 * Enums: an_x4_sw_management_IndLaneModes 316 */ 317 #define an_x4_sw_management_IndLaneModes_SWSDR_div2 0 318 #define an_x4_sw_management_IndLaneModes_SWSDR_div1 1 319 #define an_x4_sw_management_IndLaneModes_DWSDR_div2 2 320 #define an_x4_sw_management_IndLaneModes_DWSDR_div1 3 321 322 /**************************************************************************** 323 * Enums: an_x4_sw_management_prbsSelect 324 */ 325 #define an_x4_sw_management_prbsSelect_prbs7 0 326 #define an_x4_sw_management_prbsSelect_prbs15 1 327 #define an_x4_sw_management_prbsSelect_prbs23 2 328 #define an_x4_sw_management_prbsSelect_prbs31 3 329 330 /**************************************************************************** 331 * Enums: an_x4_sw_management_vcoDivider 332 */ 333 #define an_x4_sw_management_vcoDivider_div32 0 334 #define an_x4_sw_management_vcoDivider_div36 1 335 #define an_x4_sw_management_vcoDivider_div40 2 336 #define an_x4_sw_management_vcoDivider_div42 3 337 #define an_x4_sw_management_vcoDivider_div48 4 338 #define an_x4_sw_management_vcoDivider_div50 5 339 #define an_x4_sw_management_vcoDivider_div52 6 340 #define an_x4_sw_management_vcoDivider_div54 7 341 #define an_x4_sw_management_vcoDivider_div60 8 342 #define an_x4_sw_management_vcoDivider_div64 9 343 #define an_x4_sw_management_vcoDivider_div66 10 344 #define an_x4_sw_management_vcoDivider_div68 11 345 #define an_x4_sw_management_vcoDivider_div70 12 346 #define an_x4_sw_management_vcoDivider_div80 13 347 #define an_x4_sw_management_vcoDivider_div92 14 348 #define an_x4_sw_management_vcoDivider_div100 15 349 350 /**************************************************************************** 351 * Enums: an_x4_sw_management_refClkSelect 352 */ 353 #define an_x4_sw_management_refClkSelect_clk_25MHz 0 354 #define an_x4_sw_management_refClkSelect_clk_100MHz 1 355 #define an_x4_sw_management_refClkSelect_clk_125MHz 2 356 #define an_x4_sw_management_refClkSelect_clk_156p25MHz 3 357 #define an_x4_sw_management_refClkSelect_clk_187p5MHz 4 358 #define an_x4_sw_management_refClkSelect_clk_161p25Mhz 5 359 #define an_x4_sw_management_refClkSelect_clk_50Mhz 6 360 #define an_x4_sw_management_refClkSelect_clk_106p25Mhz 7 361 362 /**************************************************************************** 363 * Enums: an_x4_sw_management_aerMMDdevTypeSelect 364 */ 365 #define an_x4_sw_management_aerMMDdevTypeSelect_combo_core 0 366 #define an_x4_sw_management_aerMMDdevTypeSelect_PMA_PMD 1 367 #define an_x4_sw_management_aerMMDdevTypeSelect_PCS 3 368 #define an_x4_sw_management_aerMMDdevTypeSelect_PHY 4 369 #define an_x4_sw_management_aerMMDdevTypeSelect_DTE 5 370 #define an_x4_sw_management_aerMMDdevTypeSelect_CL73_AN 7 371 372 /**************************************************************************** 373 * Enums: an_x4_sw_management_aerMMDportSelect 374 */ 375 #define an_x4_sw_management_aerMMDportSelect_ln0 0 376 #define an_x4_sw_management_aerMMDportSelect_ln1 1 377 #define an_x4_sw_management_aerMMDportSelect_ln2 2 378 #define an_x4_sw_management_aerMMDportSelect_ln3 3 379 #define an_x4_sw_management_aerMMDportSelect_BCST_ln0_1_2_3 511 380 #define an_x4_sw_management_aerMMDportSelect_BCST_ln0_1 512 381 #define an_x4_sw_management_aerMMDportSelect_BCST_ln2_3 513 382 383 /**************************************************************************** 384 * Enums: an_x4_sw_management_firmwareModeSelect 385 */ 386 #define an_x4_sw_management_firmwareModeSelect_DEFAULT 0 387 #define an_x4_sw_management_firmwareModeSelect_SFP_OPT_LR 1 388 #define an_x4_sw_management_firmwareModeSelect_SFP_DAC 2 389 #define an_x4_sw_management_firmwareModeSelect_XLAUI 3 390 #define an_x4_sw_management_firmwareModeSelect_LONG_CH_6G 4 391 392 /**************************************************************************** 393 * Enums: an_x4_sw_management_tempIdxSelect 394 */ 395 #define an_x4_sw_management_tempIdxSelect_LTE__22p9C 15 396 #define an_x4_sw_management_tempIdxSelect_LTE__12p6C 14 397 #define an_x4_sw_management_tempIdxSelect_LTE__3p0C 13 398 #define an_x4_sw_management_tempIdxSelect_LTE_6p7C 12 399 #define an_x4_sw_management_tempIdxSelect_LTE_16p4C 11 400 #define an_x4_sw_management_tempIdxSelect_LTE_26p6C 10 401 #define an_x4_sw_management_tempIdxSelect_LTE_36p3C 9 402 #define an_x4_sw_management_tempIdxSelect_LTE_46p0C 8 403 #define an_x4_sw_management_tempIdxSelect_LTE_56p2C 7 404 #define an_x4_sw_management_tempIdxSelect_LTE_65p9C 6 405 #define an_x4_sw_management_tempIdxSelect_LTE_75p6C 5 406 #define an_x4_sw_management_tempIdxSelect_LTE_85p3C 4 407 #define an_x4_sw_management_tempIdxSelect_LTE_95p5C 3 408 #define an_x4_sw_management_tempIdxSelect_LTE_105p2C 2 409 #define an_x4_sw_management_tempIdxSelect_LTE_114p9C 1 410 #define an_x4_sw_management_tempIdxSelect_LTE_125p1C 0 411 412 /**************************************************************************** 413 * Enums: an_x4_sw_management_tla_ln_seq_status 414 */ 415 #define an_x4_sw_management_tla_ln_seq_status_INIT 1 416 #define an_x4_sw_management_tla_ln_seq_status_SET_AN_SPEED 2 417 #define an_x4_sw_management_tla_ln_seq_status_WAIT_AN_SPEED 4 418 #define an_x4_sw_management_tla_ln_seq_status_WAIT_AN_DONE 8 419 #define an_x4_sw_management_tla_ln_seq_status_SET_RS_SPEED 16 420 #define an_x4_sw_management_tla_ln_seq_status_WAIT_RS_CL72EN 32 421 #define an_x4_sw_management_tla_ln_seq_status_WAIT_RS_SPEED 64 422 #define an_x4_sw_management_tla_ln_seq_status_AN_IGNORE_LINK 128 423 #define an_x4_sw_management_tla_ln_seq_status_AN_GOOD_CHECK 256 424 #define an_x4_sw_management_tla_ln_seq_status_AN_GOOD 512 425 #define an_x4_sw_management_tla_ln_seq_status_AN_FAIL 1024 426 #define an_x4_sw_management_tla_ln_seq_status_AN_DEAD 2048 427 #define an_x4_sw_management_tla_ln_seq_status_SET_PD_SPEED 4096 428 #define an_x4_sw_management_tla_ln_seq_status_WAIT_PD_SPEED 8192 429 #define an_x4_sw_management_tla_ln_seq_status_PD_IGNORE_LINK 16384 430 #define an_x4_sw_management_tla_ln_seq_status_PD_GOOD_CHECK 32768 431 432 /**************************************************************************** 433 * Enums: an_x4_sw_management_tla_ln_seq_status1 434 */ 435 #define an_x4_sw_management_tla_ln_seq_status1_SW_SPEED_CHANGE 64 436 #define an_x4_sw_management_tla_ln_seq_status1_RELEASE_SW 32 437 #define an_x4_sw_management_tla_ln_seq_status1_RELEASE_DISABLE 16 438 #define an_x4_sw_management_tla_ln_seq_status1_PD_WAIT_LINK 8 439 #define an_x4_sw_management_tla_ln_seq_status1_PD_START_CL37_AN 4 440 #define an_x4_sw_management_tla_ln_seq_status1_PD_WAIT_CL37_AN_DONE 2 441 #define an_x4_sw_management_tla_ln_seq_status1_PD_DONE_CL37 1 442 443 /**************************************************************************** 444 * Enums: digital_cl36TxEEEStates_l 445 */ 446 #define digital_cl36TxEEEStates_l_TX_REFRESH 8 447 #define digital_cl36TxEEEStates_l_TX_QUIET 4 448 #define digital_cl36TxEEEStates_l_TX_SLEEP 2 449 #define digital_cl36TxEEEStates_l_TX_ACTIVE 1 450 451 /**************************************************************************** 452 * Enums: digital_cl36TxEEEStates_c 453 */ 454 #define digital_cl36TxEEEStates_c_TX_REFRESH 3 455 #define digital_cl36TxEEEStates_c_TX_QUIET 2 456 #define digital_cl36TxEEEStates_c_TX_SLEEP 1 457 #define digital_cl36TxEEEStates_c_TX_ACTIVE 0 458 459 /**************************************************************************** 460 * Enums: digital_cl49TxEEEStates_l 461 */ 462 #define digital_cl49TxEEEStates_l_SCR_RESET_2 64 463 #define digital_cl49TxEEEStates_l_SCR_RESET_1 32 464 #define digital_cl49TxEEEStates_l_TX_WAKE 16 465 #define digital_cl49TxEEEStates_l_TX_REFRESH 8 466 #define digital_cl49TxEEEStates_l_TX_QUIET 4 467 #define digital_cl49TxEEEStates_l_TX_SLEEP 2 468 #define digital_cl49TxEEEStates_l_TX_ACTIVE 1 469 470 /**************************************************************************** 471 * Enums: digital_cl49TxEEEStates_c 472 */ 473 #define digital_cl49TxEEEStates_c_SCR_RESET_2 6 474 #define digital_cl49TxEEEStates_c_SCR_RESET_1 5 475 #define digital_cl49TxEEEStates_c_TX_WAKE 4 476 #define digital_cl49TxEEEStates_c_TX_REFRESH 3 477 #define digital_cl49TxEEEStates_c_TX_QUIET 2 478 #define digital_cl49TxEEEStates_c_TX_SLEEP 1 479 #define digital_cl49TxEEEStates_c_TX_ACTIVE 0 480 481 /**************************************************************************** 482 * Enums: digital_cl36RxEEEStates_l 483 */ 484 #define digital_cl36RxEEEStates_l_RX_LINK_FAIL 32 485 #define digital_cl36RxEEEStates_l_RX_WTF 16 486 #define digital_cl36RxEEEStates_l_RX_WAKE 8 487 #define digital_cl36RxEEEStates_l_RX_QUIET 4 488 #define digital_cl36RxEEEStates_l_RX_SLEEP 2 489 #define digital_cl36RxEEEStates_l_RX_ACTIVE 1 490 491 /**************************************************************************** 492 * Enums: digital_cl36RxEEEStates_c 493 */ 494 #define digital_cl36RxEEEStates_c_RX_LINK_FAIL 5 495 #define digital_cl36RxEEEStates_c_RX_WTF 4 496 #define digital_cl36RxEEEStates_c_RX_WAKE 3 497 #define digital_cl36RxEEEStates_c_RX_QUIET 2 498 #define digital_cl36RxEEEStates_c_RX_SLEEP 1 499 #define digital_cl36RxEEEStates_c_RX_ACTIVE 0 500 501 /**************************************************************************** 502 * Enums: digital_cl49RxEEEStates_l 503 */ 504 #define digital_cl49RxEEEStates_l_RX_LINK_FAIL 32 505 #define digital_cl49RxEEEStates_l_RX_WTF 16 506 #define digital_cl49RxEEEStates_l_RX_WAKE 8 507 #define digital_cl49RxEEEStates_l_RX_QUIET 4 508 #define digital_cl49RxEEEStates_l_RX_SLEEP 2 509 #define digital_cl49RxEEEStates_l_RX_ACTIVE 1 510 511 /**************************************************************************** 512 * Enums: digital_cl49RxEEEStates_c 513 */ 514 #define digital_cl49RxEEEStates_c_RX_LINK_FAIL 5 515 #define digital_cl49RxEEEStates_c_RX_WTF 4 516 #define digital_cl49RxEEEStates_c_RX_WAKE 3 517 #define digital_cl49RxEEEStates_c_RX_QUIET 2 518 #define digital_cl49RxEEEStates_c_RX_SLEEP 1 519 #define digital_cl49RxEEEStates_c_RX_ACTIVE 0 520 521 /**************************************************************************** 522 * Enums: digital_cl48TxEEEStates_l 523 */ 524 #define digital_cl48TxEEEStates_l_TX_REFRESH 8 525 #define digital_cl48TxEEEStates_l_TX_QUIET 4 526 #define digital_cl48TxEEEStates_l_TX_SLEEP 2 527 #define digital_cl48TxEEEStates_l_TX_ACTIVE 1 528 529 /**************************************************************************** 530 * Enums: digital_cl48TxEEEStates_c 531 */ 532 #define digital_cl48TxEEEStates_c_TX_REFRESH 3 533 #define digital_cl48TxEEEStates_c_TX_QUIET 2 534 #define digital_cl48TxEEEStates_c_TX_SLEEP 1 535 #define digital_cl48TxEEEStates_c_TX_ACTIVE 0 536 537 /**************************************************************************** 538 * Enums: digital_cl48RxEEEStates_l 539 */ 540 #define digital_cl48RxEEEStates_l_RX_LINK_FAIL 32 541 #define digital_cl48RxEEEStates_l_RX_WAKE 16 542 #define digital_cl48RxEEEStates_l_RX_QUIET 8 543 #define digital_cl48RxEEEStates_l_RX_DEACT 4 544 #define digital_cl48RxEEEStates_l_RX_SLEEP 2 545 #define digital_cl48RxEEEStates_l_RX_ACTIVE 1 546 547 /**************************************************************************** 548 * Enums: digital_cl48RxEEEStates_c 549 */ 550 #define digital_cl48RxEEEStates_c_RX_LINK_FAIL 5 551 #define digital_cl48RxEEEStates_c_RX_WAKE 4 552 #define digital_cl48RxEEEStates_c_RX_QUIET 3 553 #define digital_cl48RxEEEStates_c_RX_DEACT 2 554 #define digital_cl48RxEEEStates_c_RX_SLEEP 1 555 #define digital_cl48RxEEEStates_c_RX_ACTIVE 0 556 557 /**************************************************************************** 558 * Enums: digital_IQP_Options 559 */ 560 #define digital_IQP_Options_i50uA 0 561 #define digital_IQP_Options_i100uA 1 562 #define digital_IQP_Options_i150uA 2 563 #define digital_IQP_Options_i200uA 3 564 #define digital_IQP_Options_i250uA 4 565 #define digital_IQP_Options_i300uA 5 566 #define digital_IQP_Options_i350uA 6 567 #define digital_IQP_Options_i400uA 7 568 #define digital_IQP_Options_i450uA 8 569 #define digital_IQP_Options_i500uA 9 570 #define digital_IQP_Options_i550uA 10 571 #define digital_IQP_Options_i600uA 11 572 #define digital_IQP_Options_i650uA 12 573 #define digital_IQP_Options_i700uA 13 574 #define digital_IQP_Options_i750uA 14 575 #define digital_IQP_Options_i800uA 15 576 577 /**************************************************************************** 578 * Enums: digital_IDriver_Options 579 */ 580 #define digital_IDriver_Options_v680mV 0 581 #define digital_IDriver_Options_v730mV 1 582 #define digital_IDriver_Options_v780mV 2 583 #define digital_IDriver_Options_v830mV 3 584 #define digital_IDriver_Options_v880mV 4 585 #define digital_IDriver_Options_v930mV 5 586 #define digital_IDriver_Options_v980mV 6 587 #define digital_IDriver_Options_v1010mV 7 588 #define digital_IDriver_Options_v1040mV 8 589 #define digital_IDriver_Options_v1060mV 9 590 #define digital_IDriver_Options_v1070mV 10 591 #define digital_IDriver_Options_v1080mV 11 592 #define digital_IDriver_Options_v1085mV 12 593 #define digital_IDriver_Options_v1090mV 13 594 #define digital_IDriver_Options_v1095mV 14 595 #define digital_IDriver_Options_v1100mV 15 596 597 /**************************************************************************** 598 * Enums: digital_operationModes 599 */ 600 #define digital_operationModes_XGXS 0 601 #define digital_operationModes_XGXG_nCC 1 602 #define digital_operationModes_Indlane_OS8 4 603 #define digital_operationModes_IndLane_OS5 5 604 #define digital_operationModes_PCI 7 605 #define digital_operationModes_XGXS_nLQ 8 606 #define digital_operationModes_XGXS_nLQnCC 9 607 #define digital_operationModes_PBypass 10 608 #define digital_operationModes_PBypass_nDSK 11 609 #define digital_operationModes_ComboCoreMode 12 610 #define digital_operationModes_Clocks_off 15 611 612 /**************************************************************************** 613 * Enums: digital_synce_enum 614 */ 615 #define digital_synce_enum_SYNCE_NO_DIV 0 616 #define digital_synce_enum_SYNCE_DIV_7 1 617 #define digital_synce_enum_SYNCE_DIV_11 2 618 619 /**************************************************************************** 620 * Enums: digital_operationSpeeds 621 */ 622 #define digital_operationSpeeds_SPEED_2p5G_X1_10p3125 56 623 #define digital_operationSpeeds_SPEED_1000M_10p3125 55 624 #define digital_operationSpeeds_SPEED_100M_10p3125 54 625 #define digital_operationSpeeds_SPEED_10M_10p3125 53 626 #define digital_operationSpeeds_SPEED_10p5G_X4 50 627 #define digital_operationSpeeds_SPEED_5G_KR1 49 628 #define digital_operationSpeeds_SPEED_127G_X12 39 629 #define digital_operationSpeeds_SPEED_120G_X12 38 630 #define digital_operationSpeeds_SPEED_107G_X10 37 631 #define digital_operationSpeeds_SPEED_100G_CR10 36 632 #define digital_operationSpeeds_SPEED_42G_X4 35 633 #define digital_operationSpeeds_SPEED_40G_CR4 34 634 #define digital_operationSpeeds_SPEED_40G_KR4 33 635 #define digital_operationSpeeds_SPEED_21G_X2 32 636 #define digital_operationSpeeds_SPEED_20G_CR2 31 637 #define digital_operationSpeeds_SPEED_20G_KR2 30 638 #define digital_operationSpeeds_SPEED_10p6_X1 29 639 #define digital_operationSpeeds_SPEED_10G_KR1 28 640 #define digital_operationSpeeds_SPEED_40G_X4 27 641 #define digital_operationSpeeds_SPEED_20G_X2 26 642 #define digital_operationSpeeds_SPEED_20G_CX2 25 643 #define digital_operationSpeeds_SPEED_31p5G_KR4 24 644 #define digital_operationSpeeds_SPEED_31p5G_X4 23 645 #define digital_operationSpeeds_SPEED_15p75G_X2 22 646 #define digital_operationSpeeds_SPEED_25p45G_X4 21 647 #define digital_operationSpeeds_SPEED_12p7G_X2 20 648 #define digital_operationSpeeds_SPEED_21G_X4 19 649 #define digital_operationSpeeds_SPEED_10p5G_X2 18 650 #define digital_operationSpeeds_SPEED_20G_X4 17 651 #define digital_operationSpeeds_SPEED_10G_X2 16 652 #define digital_operationSpeeds_SPEED_10G_CX2 15 653 #define digital_operationSpeeds_SPEED_20G_CX4 14 654 #define digital_operationSpeeds_SPEED_16G_X4 13 655 #define digital_operationSpeeds_SPEED_15G_X4 12 656 #define digital_operationSpeeds_SPEED_13G_X4 11 657 #define digital_operationSpeeds_SPEED_10G_X4 10 658 #define digital_operationSpeeds_SPEED_10G_KX4 9 659 #define digital_operationSpeeds_SPEED_10G_CX4 8 660 #define digital_operationSpeeds_SPEED_5G_X1 7 661 #define digital_operationSpeeds_SPEED_2p5G_X1 6 662 #define digital_operationSpeeds_SPEED_1G_KX1 5 663 #define digital_operationSpeeds_SPEED_1G_CX1 4 664 #define digital_operationSpeeds_SPEED_1000M 3 665 #define digital_operationSpeeds_SPEED_100M 2 666 #define digital_operationSpeeds_SPEED_10M 1 667 668 /**************************************************************************** 669 * Enums: digital_actualSpeeds 670 */ 671 #define digital_actualSpeeds_dr_10M 0 672 #define digital_actualSpeeds_dr_100M 1 673 #define digital_actualSpeeds_dr_1G 2 674 #define digital_actualSpeeds_dr_2p5G 3 675 #define digital_actualSpeeds_dr_5G_X4 4 676 #define digital_actualSpeeds_dr_6G_X4 5 677 #define digital_actualSpeeds_dr_10G_HiG 6 678 #define digital_actualSpeeds_dr_10G_CX4 7 679 #define digital_actualSpeeds_dr_12G_HiG 8 680 #define digital_actualSpeeds_dr_12p5G_X4 9 681 #define digital_actualSpeeds_dr_13G_X4 10 682 #define digital_actualSpeeds_dr_15G_X4 11 683 #define digital_actualSpeeds_dr_16G_X4 12 684 #define digital_actualSpeeds_dr_1G_KX 13 685 #define digital_actualSpeeds_dr_10G_KX4 14 686 #define digital_actualSpeeds_dr_10G_KR 15 687 #define digital_actualSpeeds_dr_5G 16 688 #define digital_actualSpeeds_dr_6p4G 17 689 #define digital_actualSpeeds_dr_20G_X4 18 690 #define digital_actualSpeeds_dr_21G_X4 19 691 #define digital_actualSpeeds_dr_25G_X4 20 692 #define digital_actualSpeeds_dr_10G_HiG_DXGXS 21 693 #define digital_actualSpeeds_dr_10G_DXGXS 22 694 #define digital_actualSpeeds_dr_10p5G_HiG_DXGXS 23 695 #define digital_actualSpeeds_dr_10p5G_DXGXS 24 696 #define digital_actualSpeeds_dr_12p773G_HiG_DXGXS 25 697 #define digital_actualSpeeds_dr_12p773G_DXGXS 26 698 #define digital_actualSpeeds_dr_10G_XFI 27 699 #define digital_actualSpeeds_dr_40G 28 700 #define digital_actualSpeeds_dr_20G_HiG_DXGXS 29 701 #define digital_actualSpeeds_dr_20G_DXGXS 30 702 #define digital_actualSpeeds_dr_10G_SFI 31 703 #define digital_actualSpeeds_dr_31p5G 32 704 #define digital_actualSpeeds_dr_32p7G 33 705 #define digital_actualSpeeds_dr_20G_SCR 34 706 #define digital_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 707 #define digital_actualSpeeds_dr_10G_DXGXS_SCR 36 708 #define digital_actualSpeeds_dr_12G_R2 37 709 #define digital_actualSpeeds_dr_10G_X2 38 710 #define digital_actualSpeeds_dr_40G_KR4 39 711 #define digital_actualSpeeds_dr_40G_CR4 40 712 #define digital_actualSpeeds_dr_100G_CR10 41 713 #define digital_actualSpeeds_dr_15p75G_DXGXS 44 714 #define digital_actualSpeeds_dr_20G_KR2 57 715 #define digital_actualSpeeds_dr_20G_CR2 58 716 717 /**************************************************************************** 718 * Enums: digital_actualSpeedsMisc1 719 */ 720 #define digital_actualSpeedsMisc1_dr_2500BRCM_X1 16 721 #define digital_actualSpeedsMisc1_dr_5000BRCM_X4 17 722 #define digital_actualSpeedsMisc1_dr_6000BRCM_X4 18 723 #define digital_actualSpeedsMisc1_dr_10GHiGig_X4 19 724 #define digital_actualSpeedsMisc1_dr_10GBASE_CX4 20 725 #define digital_actualSpeedsMisc1_dr_12GHiGig_X4 21 726 #define digital_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 727 #define digital_actualSpeedsMisc1_dr_13GHiGig_X4 23 728 #define digital_actualSpeedsMisc1_dr_15GHiGig_X4 24 729 #define digital_actualSpeedsMisc1_dr_16GHiGig_X4 25 730 #define digital_actualSpeedsMisc1_dr_5000BRCM_X1 26 731 #define digital_actualSpeedsMisc1_dr_6363BRCM_X1 27 732 #define digital_actualSpeedsMisc1_dr_20GHiGig_X4 28 733 #define digital_actualSpeedsMisc1_dr_21GHiGig_X4 29 734 #define digital_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 735 #define digital_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 736 737 /**************************************************************************** 738 * Enums: digital_IndLaneModes 739 */ 740 #define digital_IndLaneModes_SWSDR_div2 0 741 #define digital_IndLaneModes_SWSDR_div1 1 742 #define digital_IndLaneModes_DWSDR_div2 2 743 #define digital_IndLaneModes_DWSDR_div1 3 744 745 /**************************************************************************** 746 * Enums: digital_prbsSelect 747 */ 748 #define digital_prbsSelect_prbs7 0 749 #define digital_prbsSelect_prbs15 1 750 #define digital_prbsSelect_prbs23 2 751 #define digital_prbsSelect_prbs31 3 752 753 /**************************************************************************** 754 * Enums: digital_vcoDivider 755 */ 756 #define digital_vcoDivider_div32 0 757 #define digital_vcoDivider_div36 1 758 #define digital_vcoDivider_div40 2 759 #define digital_vcoDivider_div42 3 760 #define digital_vcoDivider_div48 4 761 #define digital_vcoDivider_div50 5 762 #define digital_vcoDivider_div52 6 763 #define digital_vcoDivider_div54 7 764 #define digital_vcoDivider_div60 8 765 #define digital_vcoDivider_div64 9 766 #define digital_vcoDivider_div66 10 767 #define digital_vcoDivider_div68 11 768 #define digital_vcoDivider_div70 12 769 #define digital_vcoDivider_div80 13 770 #define digital_vcoDivider_div92 14 771 #define digital_vcoDivider_div100 15 772 773 /**************************************************************************** 774 * Enums: digital_refClkSelect 775 */ 776 #define digital_refClkSelect_clk_25MHz 0 777 #define digital_refClkSelect_clk_100MHz 1 778 #define digital_refClkSelect_clk_125MHz 2 779 #define digital_refClkSelect_clk_156p25MHz 3 780 #define digital_refClkSelect_clk_187p5MHz 4 781 #define digital_refClkSelect_clk_161p25Mhz 5 782 #define digital_refClkSelect_clk_50Mhz 6 783 #define digital_refClkSelect_clk_106p25Mhz 7 784 785 /**************************************************************************** 786 * Enums: digital_aerMMDdevTypeSelect 787 */ 788 #define digital_aerMMDdevTypeSelect_combo_core 0 789 #define digital_aerMMDdevTypeSelect_PMA_PMD 1 790 #define digital_aerMMDdevTypeSelect_PCS 3 791 #define digital_aerMMDdevTypeSelect_PHY 4 792 #define digital_aerMMDdevTypeSelect_DTE 5 793 #define digital_aerMMDdevTypeSelect_CL73_AN 7 794 795 /**************************************************************************** 796 * Enums: digital_aerMMDportSelect 797 */ 798 #define digital_aerMMDportSelect_ln0 0 799 #define digital_aerMMDportSelect_ln1 1 800 #define digital_aerMMDportSelect_ln2 2 801 #define digital_aerMMDportSelect_ln3 3 802 #define digital_aerMMDportSelect_BCST_ln0_1_2_3 511 803 #define digital_aerMMDportSelect_BCST_ln0_1 512 804 #define digital_aerMMDportSelect_BCST_ln2_3 513 805 806 /**************************************************************************** 807 * Enums: digital_firmwareModeSelect 808 */ 809 #define digital_firmwareModeSelect_DEFAULT 0 810 #define digital_firmwareModeSelect_SFP_OPT_LR 1 811 #define digital_firmwareModeSelect_SFP_DAC 2 812 #define digital_firmwareModeSelect_XLAUI 3 813 #define digital_firmwareModeSelect_LONG_CH_6G 4 814 815 /**************************************************************************** 816 * Enums: digital_tempIdxSelect 817 */ 818 #define digital_tempIdxSelect_LTE__22p9C 15 819 #define digital_tempIdxSelect_LTE__12p6C 14 820 #define digital_tempIdxSelect_LTE__3p0C 13 821 #define digital_tempIdxSelect_LTE_6p7C 12 822 #define digital_tempIdxSelect_LTE_16p4C 11 823 #define digital_tempIdxSelect_LTE_26p6C 10 824 #define digital_tempIdxSelect_LTE_36p3C 9 825 #define digital_tempIdxSelect_LTE_46p0C 8 826 #define digital_tempIdxSelect_LTE_56p2C 7 827 #define digital_tempIdxSelect_LTE_65p9C 6 828 #define digital_tempIdxSelect_LTE_75p6C 5 829 #define digital_tempIdxSelect_LTE_85p3C 4 830 #define digital_tempIdxSelect_LTE_95p5C 3 831 #define digital_tempIdxSelect_LTE_105p2C 2 832 #define digital_tempIdxSelect_LTE_114p9C 1 833 #define digital_tempIdxSelect_LTE_125p1C 0 834 835 /**************************************************************************** 836 * Enums: generic_cl36TxEEEStates_l 837 */ 838 #define generic_cl36TxEEEStates_l_TX_REFRESH 8 839 #define generic_cl36TxEEEStates_l_TX_QUIET 4 840 #define generic_cl36TxEEEStates_l_TX_SLEEP 2 841 #define generic_cl36TxEEEStates_l_TX_ACTIVE 1 842 843 /**************************************************************************** 844 * Enums: generic_cl36TxEEEStates_c 845 */ 846 #define generic_cl36TxEEEStates_c_TX_REFRESH 3 847 #define generic_cl36TxEEEStates_c_TX_QUIET 2 848 #define generic_cl36TxEEEStates_c_TX_SLEEP 1 849 #define generic_cl36TxEEEStates_c_TX_ACTIVE 0 850 851 /**************************************************************************** 852 * Enums: generic_cl49TxEEEStates_l 853 */ 854 #define generic_cl49TxEEEStates_l_SCR_RESET_2 64 855 #define generic_cl49TxEEEStates_l_SCR_RESET_1 32 856 #define generic_cl49TxEEEStates_l_TX_WAKE 16 857 #define generic_cl49TxEEEStates_l_TX_REFRESH 8 858 #define generic_cl49TxEEEStates_l_TX_QUIET 4 859 #define generic_cl49TxEEEStates_l_TX_SLEEP 2 860 #define generic_cl49TxEEEStates_l_TX_ACTIVE 1 861 862 /**************************************************************************** 863 * Enums: generic_cl49TxEEEStates_c 864 */ 865 #define generic_cl49TxEEEStates_c_SCR_RESET_2 6 866 #define generic_cl49TxEEEStates_c_SCR_RESET_1 5 867 #define generic_cl49TxEEEStates_c_TX_WAKE 4 868 #define generic_cl49TxEEEStates_c_TX_REFRESH 3 869 #define generic_cl49TxEEEStates_c_TX_QUIET 2 870 #define generic_cl49TxEEEStates_c_TX_SLEEP 1 871 #define generic_cl49TxEEEStates_c_TX_ACTIVE 0 872 873 /**************************************************************************** 874 * Enums: generic_cl36RxEEEStates_l 875 */ 876 #define generic_cl36RxEEEStates_l_RX_LINK_FAIL 32 877 #define generic_cl36RxEEEStates_l_RX_WTF 16 878 #define generic_cl36RxEEEStates_l_RX_WAKE 8 879 #define generic_cl36RxEEEStates_l_RX_QUIET 4 880 #define generic_cl36RxEEEStates_l_RX_SLEEP 2 881 #define generic_cl36RxEEEStates_l_RX_ACTIVE 1 882 883 /**************************************************************************** 884 * Enums: generic_cl36RxEEEStates_c 885 */ 886 #define generic_cl36RxEEEStates_c_RX_LINK_FAIL 5 887 #define generic_cl36RxEEEStates_c_RX_WTF 4 888 #define generic_cl36RxEEEStates_c_RX_WAKE 3 889 #define generic_cl36RxEEEStates_c_RX_QUIET 2 890 #define generic_cl36RxEEEStates_c_RX_SLEEP 1 891 #define generic_cl36RxEEEStates_c_RX_ACTIVE 0 892 893 /**************************************************************************** 894 * Enums: generic_cl49RxEEEStates_l 895 */ 896 #define generic_cl49RxEEEStates_l_RX_LINK_FAIL 32 897 #define generic_cl49RxEEEStates_l_RX_WTF 16 898 #define generic_cl49RxEEEStates_l_RX_WAKE 8 899 #define generic_cl49RxEEEStates_l_RX_QUIET 4 900 #define generic_cl49RxEEEStates_l_RX_SLEEP 2 901 #define generic_cl49RxEEEStates_l_RX_ACTIVE 1 902 903 /**************************************************************************** 904 * Enums: generic_cl49RxEEEStates_c 905 */ 906 #define generic_cl49RxEEEStates_c_RX_LINK_FAIL 5 907 #define generic_cl49RxEEEStates_c_RX_WTF 4 908 #define generic_cl49RxEEEStates_c_RX_WAKE 3 909 #define generic_cl49RxEEEStates_c_RX_QUIET 2 910 #define generic_cl49RxEEEStates_c_RX_SLEEP 1 911 #define generic_cl49RxEEEStates_c_RX_ACTIVE 0 912 913 /**************************************************************************** 914 * Enums: generic_cl48TxEEEStates_l 915 */ 916 #define generic_cl48TxEEEStates_l_TX_REFRESH 8 917 #define generic_cl48TxEEEStates_l_TX_QUIET 4 918 #define generic_cl48TxEEEStates_l_TX_SLEEP 2 919 #define generic_cl48TxEEEStates_l_TX_ACTIVE 1 920 921 /**************************************************************************** 922 * Enums: generic_cl48TxEEEStates_c 923 */ 924 #define generic_cl48TxEEEStates_c_TX_REFRESH 3 925 #define generic_cl48TxEEEStates_c_TX_QUIET 2 926 #define generic_cl48TxEEEStates_c_TX_SLEEP 1 927 #define generic_cl48TxEEEStates_c_TX_ACTIVE 0 928 929 /**************************************************************************** 930 * Enums: generic_cl48RxEEEStates_l 931 */ 932 #define generic_cl48RxEEEStates_l_RX_LINK_FAIL 32 933 #define generic_cl48RxEEEStates_l_RX_WAKE 16 934 #define generic_cl48RxEEEStates_l_RX_QUIET 8 935 #define generic_cl48RxEEEStates_l_RX_DEACT 4 936 #define generic_cl48RxEEEStates_l_RX_SLEEP 2 937 #define generic_cl48RxEEEStates_l_RX_ACTIVE 1 938 939 /**************************************************************************** 940 * Enums: generic_cl48RxEEEStates_c 941 */ 942 #define generic_cl48RxEEEStates_c_RX_LINK_FAIL 5 943 #define generic_cl48RxEEEStates_c_RX_WAKE 4 944 #define generic_cl48RxEEEStates_c_RX_QUIET 3 945 #define generic_cl48RxEEEStates_c_RX_DEACT 2 946 #define generic_cl48RxEEEStates_c_RX_SLEEP 1 947 #define generic_cl48RxEEEStates_c_RX_ACTIVE 0 948 949 /**************************************************************************** 950 * Enums: generic_IQP_Options 951 */ 952 #define generic_IQP_Options_i50uA 0 953 #define generic_IQP_Options_i100uA 1 954 #define generic_IQP_Options_i150uA 2 955 #define generic_IQP_Options_i200uA 3 956 #define generic_IQP_Options_i250uA 4 957 #define generic_IQP_Options_i300uA 5 958 #define generic_IQP_Options_i350uA 6 959 #define generic_IQP_Options_i400uA 7 960 #define generic_IQP_Options_i450uA 8 961 #define generic_IQP_Options_i500uA 9 962 #define generic_IQP_Options_i550uA 10 963 #define generic_IQP_Options_i600uA 11 964 #define generic_IQP_Options_i650uA 12 965 #define generic_IQP_Options_i700uA 13 966 #define generic_IQP_Options_i750uA 14 967 #define generic_IQP_Options_i800uA 15 968 969 /**************************************************************************** 970 * Enums: generic_IDriver_Options 971 */ 972 #define generic_IDriver_Options_v680mV 0 973 #define generic_IDriver_Options_v730mV 1 974 #define generic_IDriver_Options_v780mV 2 975 #define generic_IDriver_Options_v830mV 3 976 #define generic_IDriver_Options_v880mV 4 977 #define generic_IDriver_Options_v930mV 5 978 #define generic_IDriver_Options_v980mV 6 979 #define generic_IDriver_Options_v1010mV 7 980 #define generic_IDriver_Options_v1040mV 8 981 #define generic_IDriver_Options_v1060mV 9 982 #define generic_IDriver_Options_v1070mV 10 983 #define generic_IDriver_Options_v1080mV 11 984 #define generic_IDriver_Options_v1085mV 12 985 #define generic_IDriver_Options_v1090mV 13 986 #define generic_IDriver_Options_v1095mV 14 987 #define generic_IDriver_Options_v1100mV 15 988 989 /**************************************************************************** 990 * Enums: generic_operationModes 991 */ 992 #define generic_operationModes_XGXS 0 993 #define generic_operationModes_XGXG_nCC 1 994 #define generic_operationModes_Indlane_OS8 4 995 #define generic_operationModes_IndLane_OS5 5 996 #define generic_operationModes_PCI 7 997 #define generic_operationModes_XGXS_nLQ 8 998 #define generic_operationModes_XGXS_nLQnCC 9 999 #define generic_operationModes_PBypass 10 1000 #define generic_operationModes_PBypass_nDSK 11 1001 #define generic_operationModes_ComboCoreMode 12 1002 #define generic_operationModes_Clocks_off 15 1003 1004 /**************************************************************************** 1005 * Enums: generic_synce_enum 1006 */ 1007 #define generic_synce_enum_SYNCE_NO_DIV 0 1008 #define generic_synce_enum_SYNCE_DIV_7 1 1009 #define generic_synce_enum_SYNCE_DIV_11 2 1010 1011 /**************************************************************************** 1012 * Enums: generic_operationSpeeds 1013 */ 1014 #define generic_operationSpeeds_SPEED_2p5G_X1_10p3125 56 1015 #define generic_operationSpeeds_SPEED_1000M_10p3125 55 1016 #define generic_operationSpeeds_SPEED_100M_10p3125 54 1017 #define generic_operationSpeeds_SPEED_10M_10p3125 53 1018 #define generic_operationSpeeds_SPEED_10p5G_X4 50 1019 #define generic_operationSpeeds_SPEED_5G_KR1 49 1020 #define generic_operationSpeeds_SPEED_127G_X12 39 1021 #define generic_operationSpeeds_SPEED_120G_X12 38 1022 #define generic_operationSpeeds_SPEED_107G_X10 37 1023 #define generic_operationSpeeds_SPEED_100G_CR10 36 1024 #define generic_operationSpeeds_SPEED_42G_X4 35 1025 #define generic_operationSpeeds_SPEED_40G_CR4 34 1026 #define generic_operationSpeeds_SPEED_40G_KR4 33 1027 #define generic_operationSpeeds_SPEED_21G_X2 32 1028 #define generic_operationSpeeds_SPEED_20G_CR2 31 1029 #define generic_operationSpeeds_SPEED_20G_KR2 30 1030 #define generic_operationSpeeds_SPEED_10p6_X1 29 1031 #define generic_operationSpeeds_SPEED_10G_KR1 28 1032 #define generic_operationSpeeds_SPEED_40G_X4 27 1033 #define generic_operationSpeeds_SPEED_20G_X2 26 1034 #define generic_operationSpeeds_SPEED_20G_CX2 25 1035 #define generic_operationSpeeds_SPEED_31p5G_KR4 24 1036 #define generic_operationSpeeds_SPEED_31p5G_X4 23 1037 #define generic_operationSpeeds_SPEED_15p75G_X2 22 1038 #define generic_operationSpeeds_SPEED_25p45G_X4 21 1039 #define generic_operationSpeeds_SPEED_12p7G_X2 20 1040 #define generic_operationSpeeds_SPEED_21G_X4 19 1041 #define generic_operationSpeeds_SPEED_10p5G_X2 18 1042 #define generic_operationSpeeds_SPEED_20G_X4 17 1043 #define generic_operationSpeeds_SPEED_10G_X2 16 1044 #define generic_operationSpeeds_SPEED_10G_CX2 15 1045 #define generic_operationSpeeds_SPEED_20G_CX4 14 1046 #define generic_operationSpeeds_SPEED_16G_X4 13 1047 #define generic_operationSpeeds_SPEED_15G_X4 12 1048 #define generic_operationSpeeds_SPEED_13G_X4 11 1049 #define generic_operationSpeeds_SPEED_10G_X4 10 1050 #define generic_operationSpeeds_SPEED_10G_KX4 9 1051 #define generic_operationSpeeds_SPEED_10G_CX4 8 1052 #define generic_operationSpeeds_SPEED_5G_X1 7 1053 #define generic_operationSpeeds_SPEED_2p5G_X1 6 1054 #define generic_operationSpeeds_SPEED_1G_KX1 5 1055 #define generic_operationSpeeds_SPEED_1G_CX1 4 1056 #define generic_operationSpeeds_SPEED_1000M 3 1057 #define generic_operationSpeeds_SPEED_100M 2 1058 #define generic_operationSpeeds_SPEED_10M 1 1059 1060 /**************************************************************************** 1061 * Enums: generic_actualSpeeds 1062 */ 1063 #define generic_actualSpeeds_dr_10M 0 1064 #define generic_actualSpeeds_dr_100M 1 1065 #define generic_actualSpeeds_dr_1G 2 1066 #define generic_actualSpeeds_dr_2p5G 3 1067 #define generic_actualSpeeds_dr_5G_X4 4 1068 #define generic_actualSpeeds_dr_6G_X4 5 1069 #define generic_actualSpeeds_dr_10G_HiG 6 1070 #define generic_actualSpeeds_dr_10G_CX4 7 1071 #define generic_actualSpeeds_dr_12G_HiG 8 1072 #define generic_actualSpeeds_dr_12p5G_X4 9 1073 #define generic_actualSpeeds_dr_13G_X4 10 1074 #define generic_actualSpeeds_dr_15G_X4 11 1075 #define generic_actualSpeeds_dr_16G_X4 12 1076 #define generic_actualSpeeds_dr_1G_KX 13 1077 #define generic_actualSpeeds_dr_10G_KX4 14 1078 #define generic_actualSpeeds_dr_10G_KR 15 1079 #define generic_actualSpeeds_dr_5G 16 1080 #define generic_actualSpeeds_dr_6p4G 17 1081 #define generic_actualSpeeds_dr_20G_X4 18 1082 #define generic_actualSpeeds_dr_21G_X4 19 1083 #define generic_actualSpeeds_dr_25G_X4 20 1084 #define generic_actualSpeeds_dr_10G_HiG_DXGXS 21 1085 #define generic_actualSpeeds_dr_10G_DXGXS 22 1086 #define generic_actualSpeeds_dr_10p5G_HiG_DXGXS 23 1087 #define generic_actualSpeeds_dr_10p5G_DXGXS 24 1088 #define generic_actualSpeeds_dr_12p773G_HiG_DXGXS 25 1089 #define generic_actualSpeeds_dr_12p773G_DXGXS 26 1090 #define generic_actualSpeeds_dr_10G_XFI 27 1091 #define generic_actualSpeeds_dr_40G 28 1092 #define generic_actualSpeeds_dr_20G_HiG_DXGXS 29 1093 #define generic_actualSpeeds_dr_20G_DXGXS 30 1094 #define generic_actualSpeeds_dr_10G_SFI 31 1095 #define generic_actualSpeeds_dr_31p5G 32 1096 #define generic_actualSpeeds_dr_32p7G 33 1097 #define generic_actualSpeeds_dr_20G_SCR 34 1098 #define generic_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 1099 #define generic_actualSpeeds_dr_10G_DXGXS_SCR 36 1100 #define generic_actualSpeeds_dr_12G_R2 37 1101 #define generic_actualSpeeds_dr_10G_X2 38 1102 #define generic_actualSpeeds_dr_40G_KR4 39 1103 #define generic_actualSpeeds_dr_40G_CR4 40 1104 #define generic_actualSpeeds_dr_100G_CR10 41 1105 #define generic_actualSpeeds_dr_15p75G_DXGXS 44 1106 #define generic_actualSpeeds_dr_20G_KR2 57 1107 #define generic_actualSpeeds_dr_20G_CR2 58 1108 1109 /**************************************************************************** 1110 * Enums: generic_actualSpeedsMisc1 1111 */ 1112 #define generic_actualSpeedsMisc1_dr_2500BRCM_X1 16 1113 #define generic_actualSpeedsMisc1_dr_5000BRCM_X4 17 1114 #define generic_actualSpeedsMisc1_dr_6000BRCM_X4 18 1115 #define generic_actualSpeedsMisc1_dr_10GHiGig_X4 19 1116 #define generic_actualSpeedsMisc1_dr_10GBASE_CX4 20 1117 #define generic_actualSpeedsMisc1_dr_12GHiGig_X4 21 1118 #define generic_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 1119 #define generic_actualSpeedsMisc1_dr_13GHiGig_X4 23 1120 #define generic_actualSpeedsMisc1_dr_15GHiGig_X4 24 1121 #define generic_actualSpeedsMisc1_dr_16GHiGig_X4 25 1122 #define generic_actualSpeedsMisc1_dr_5000BRCM_X1 26 1123 #define generic_actualSpeedsMisc1_dr_6363BRCM_X1 27 1124 #define generic_actualSpeedsMisc1_dr_20GHiGig_X4 28 1125 #define generic_actualSpeedsMisc1_dr_21GHiGig_X4 29 1126 #define generic_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 1127 #define generic_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 1128 1129 /**************************************************************************** 1130 * Enums: generic_IndLaneModes 1131 */ 1132 #define generic_IndLaneModes_SWSDR_div2 0 1133 #define generic_IndLaneModes_SWSDR_div1 1 1134 #define generic_IndLaneModes_DWSDR_div2 2 1135 #define generic_IndLaneModes_DWSDR_div1 3 1136 1137 /**************************************************************************** 1138 * Enums: generic_prbsSelect 1139 */ 1140 #define generic_prbsSelect_prbs7 0 1141 #define generic_prbsSelect_prbs15 1 1142 #define generic_prbsSelect_prbs23 2 1143 #define generic_prbsSelect_prbs31 3 1144 1145 /**************************************************************************** 1146 * Enums: generic_vcoDivider 1147 */ 1148 #define generic_vcoDivider_div32 0 1149 #define generic_vcoDivider_div36 1 1150 #define generic_vcoDivider_div40 2 1151 #define generic_vcoDivider_div42 3 1152 #define generic_vcoDivider_div48 4 1153 #define generic_vcoDivider_div50 5 1154 #define generic_vcoDivider_div52 6 1155 #define generic_vcoDivider_div54 7 1156 #define generic_vcoDivider_div60 8 1157 #define generic_vcoDivider_div64 9 1158 #define generic_vcoDivider_div66 10 1159 #define generic_vcoDivider_div68 11 1160 #define generic_vcoDivider_div70 12 1161 #define generic_vcoDivider_div80 13 1162 #define generic_vcoDivider_div92 14 1163 #define generic_vcoDivider_div100 15 1164 1165 /**************************************************************************** 1166 * Enums: generic_refClkSelect 1167 */ 1168 #define generic_refClkSelect_clk_25MHz 0 1169 #define generic_refClkSelect_clk_100MHz 1 1170 #define generic_refClkSelect_clk_125MHz 2 1171 #define generic_refClkSelect_clk_156p25MHz 3 1172 #define generic_refClkSelect_clk_187p5MHz 4 1173 #define generic_refClkSelect_clk_161p25Mhz 5 1174 #define generic_refClkSelect_clk_50Mhz 6 1175 #define generic_refClkSelect_clk_106p25Mhz 7 1176 1177 /**************************************************************************** 1178 * Enums: generic_aerMMDdevTypeSelect 1179 */ 1180 #define generic_aerMMDdevTypeSelect_combo_core 0 1181 #define generic_aerMMDdevTypeSelect_PMA_PMD 1 1182 #define generic_aerMMDdevTypeSelect_PCS 3 1183 #define generic_aerMMDdevTypeSelect_PHY 4 1184 #define generic_aerMMDdevTypeSelect_DTE 5 1185 #define generic_aerMMDdevTypeSelect_CL73_AN 7 1186 1187 /**************************************************************************** 1188 * Enums: generic_aerMMDportSelect 1189 */ 1190 #define generic_aerMMDportSelect_ln0 0 1191 #define generic_aerMMDportSelect_ln1 1 1192 #define generic_aerMMDportSelect_ln2 2 1193 #define generic_aerMMDportSelect_ln3 3 1194 #define generic_aerMMDportSelect_BCST_ln0_1_2_3 511 1195 #define generic_aerMMDportSelect_BCST_ln0_1 512 1196 #define generic_aerMMDportSelect_BCST_ln2_3 513 1197 1198 /**************************************************************************** 1199 * Enums: generic_firmwareModeSelect 1200 */ 1201 #define generic_firmwareModeSelect_DEFAULT 0 1202 #define generic_firmwareModeSelect_SFP_OPT_LR 1 1203 #define generic_firmwareModeSelect_SFP_DAC 2 1204 #define generic_firmwareModeSelect_XLAUI 3 1205 #define generic_firmwareModeSelect_LONG_CH_6G 4 1206 1207 /**************************************************************************** 1208 * Enums: generic_tempIdxSelect 1209 */ 1210 #define generic_tempIdxSelect_LTE__22p9C 15 1211 #define generic_tempIdxSelect_LTE__12p6C 14 1212 #define generic_tempIdxSelect_LTE__3p0C 13 1213 #define generic_tempIdxSelect_LTE_6p7C 12 1214 #define generic_tempIdxSelect_LTE_16p4C 11 1215 #define generic_tempIdxSelect_LTE_26p6C 10 1216 #define generic_tempIdxSelect_LTE_36p3C 9 1217 #define generic_tempIdxSelect_LTE_46p0C 8 1218 #define generic_tempIdxSelect_LTE_56p2C 7 1219 #define generic_tempIdxSelect_LTE_65p9C 6 1220 #define generic_tempIdxSelect_LTE_75p6C 5 1221 #define generic_tempIdxSelect_LTE_85p3C 4 1222 #define generic_tempIdxSelect_LTE_95p5C 3 1223 #define generic_tempIdxSelect_LTE_105p2C 2 1224 #define generic_tempIdxSelect_LTE_114p9C 1 1225 #define generic_tempIdxSelect_LTE_125p1C 0 1226 1227 /**************************************************************************** 1228 * Enums: main0_cl36TxEEEStates_l 1229 */ 1230 #define main0_cl36TxEEEStates_l_TX_REFRESH 8 1231 #define main0_cl36TxEEEStates_l_TX_QUIET 4 1232 #define main0_cl36TxEEEStates_l_TX_SLEEP 2 1233 #define main0_cl36TxEEEStates_l_TX_ACTIVE 1 1234 1235 /**************************************************************************** 1236 * Enums: main0_cl36TxEEEStates_c 1237 */ 1238 #define main0_cl36TxEEEStates_c_TX_REFRESH 3 1239 #define main0_cl36TxEEEStates_c_TX_QUIET 2 1240 #define main0_cl36TxEEEStates_c_TX_SLEEP 1 1241 #define main0_cl36TxEEEStates_c_TX_ACTIVE 0 1242 1243 /**************************************************************************** 1244 * Enums: main0_cl49TxEEEStates_l 1245 */ 1246 #define main0_cl49TxEEEStates_l_SCR_RESET_2 64 1247 #define main0_cl49TxEEEStates_l_SCR_RESET_1 32 1248 #define main0_cl49TxEEEStates_l_TX_WAKE 16 1249 #define main0_cl49TxEEEStates_l_TX_REFRESH 8 1250 #define main0_cl49TxEEEStates_l_TX_QUIET 4 1251 #define main0_cl49TxEEEStates_l_TX_SLEEP 2 1252 #define main0_cl49TxEEEStates_l_TX_ACTIVE 1 1253 1254 /**************************************************************************** 1255 * Enums: main0_cl49TxEEEStates_c 1256 */ 1257 #define main0_cl49TxEEEStates_c_SCR_RESET_2 6 1258 #define main0_cl49TxEEEStates_c_SCR_RESET_1 5 1259 #define main0_cl49TxEEEStates_c_TX_WAKE 4 1260 #define main0_cl49TxEEEStates_c_TX_REFRESH 3 1261 #define main0_cl49TxEEEStates_c_TX_QUIET 2 1262 #define main0_cl49TxEEEStates_c_TX_SLEEP 1 1263 #define main0_cl49TxEEEStates_c_TX_ACTIVE 0 1264 1265 /**************************************************************************** 1266 * Enums: main0_cl36RxEEEStates_l 1267 */ 1268 #define main0_cl36RxEEEStates_l_RX_LINK_FAIL 32 1269 #define main0_cl36RxEEEStates_l_RX_WTF 16 1270 #define main0_cl36RxEEEStates_l_RX_WAKE 8 1271 #define main0_cl36RxEEEStates_l_RX_QUIET 4 1272 #define main0_cl36RxEEEStates_l_RX_SLEEP 2 1273 #define main0_cl36RxEEEStates_l_RX_ACTIVE 1 1274 1275 /**************************************************************************** 1276 * Enums: main0_cl36RxEEEStates_c 1277 */ 1278 #define main0_cl36RxEEEStates_c_RX_LINK_FAIL 5 1279 #define main0_cl36RxEEEStates_c_RX_WTF 4 1280 #define main0_cl36RxEEEStates_c_RX_WAKE 3 1281 #define main0_cl36RxEEEStates_c_RX_QUIET 2 1282 #define main0_cl36RxEEEStates_c_RX_SLEEP 1 1283 #define main0_cl36RxEEEStates_c_RX_ACTIVE 0 1284 1285 /**************************************************************************** 1286 * Enums: main0_cl49RxEEEStates_l 1287 */ 1288 #define main0_cl49RxEEEStates_l_RX_LINK_FAIL 32 1289 #define main0_cl49RxEEEStates_l_RX_WTF 16 1290 #define main0_cl49RxEEEStates_l_RX_WAKE 8 1291 #define main0_cl49RxEEEStates_l_RX_QUIET 4 1292 #define main0_cl49RxEEEStates_l_RX_SLEEP 2 1293 #define main0_cl49RxEEEStates_l_RX_ACTIVE 1 1294 1295 /**************************************************************************** 1296 * Enums: main0_cl49RxEEEStates_c 1297 */ 1298 #define main0_cl49RxEEEStates_c_RX_LINK_FAIL 5 1299 #define main0_cl49RxEEEStates_c_RX_WTF 4 1300 #define main0_cl49RxEEEStates_c_RX_WAKE 3 1301 #define main0_cl49RxEEEStates_c_RX_QUIET 2 1302 #define main0_cl49RxEEEStates_c_RX_SLEEP 1 1303 #define main0_cl49RxEEEStates_c_RX_ACTIVE 0 1304 1305 /**************************************************************************** 1306 * Enums: main0_cl48TxEEEStates_l 1307 */ 1308 #define main0_cl48TxEEEStates_l_TX_REFRESH 8 1309 #define main0_cl48TxEEEStates_l_TX_QUIET 4 1310 #define main0_cl48TxEEEStates_l_TX_SLEEP 2 1311 #define main0_cl48TxEEEStates_l_TX_ACTIVE 1 1312 1313 /**************************************************************************** 1314 * Enums: main0_cl48TxEEEStates_c 1315 */ 1316 #define main0_cl48TxEEEStates_c_TX_REFRESH 3 1317 #define main0_cl48TxEEEStates_c_TX_QUIET 2 1318 #define main0_cl48TxEEEStates_c_TX_SLEEP 1 1319 #define main0_cl48TxEEEStates_c_TX_ACTIVE 0 1320 1321 /**************************************************************************** 1322 * Enums: main0_cl48RxEEEStates_l 1323 */ 1324 #define main0_cl48RxEEEStates_l_RX_LINK_FAIL 32 1325 #define main0_cl48RxEEEStates_l_RX_WAKE 16 1326 #define main0_cl48RxEEEStates_l_RX_QUIET 8 1327 #define main0_cl48RxEEEStates_l_RX_DEACT 4 1328 #define main0_cl48RxEEEStates_l_RX_SLEEP 2 1329 #define main0_cl48RxEEEStates_l_RX_ACTIVE 1 1330 1331 /**************************************************************************** 1332 * Enums: main0_cl48RxEEEStates_c 1333 */ 1334 #define main0_cl48RxEEEStates_c_RX_LINK_FAIL 5 1335 #define main0_cl48RxEEEStates_c_RX_WAKE 4 1336 #define main0_cl48RxEEEStates_c_RX_QUIET 3 1337 #define main0_cl48RxEEEStates_c_RX_DEACT 2 1338 #define main0_cl48RxEEEStates_c_RX_SLEEP 1 1339 #define main0_cl48RxEEEStates_c_RX_ACTIVE 0 1340 1341 /**************************************************************************** 1342 * Enums: main0_IQP_Options 1343 */ 1344 #define main0_IQP_Options_i50uA 0 1345 #define main0_IQP_Options_i100uA 1 1346 #define main0_IQP_Options_i150uA 2 1347 #define main0_IQP_Options_i200uA 3 1348 #define main0_IQP_Options_i250uA 4 1349 #define main0_IQP_Options_i300uA 5 1350 #define main0_IQP_Options_i350uA 6 1351 #define main0_IQP_Options_i400uA 7 1352 #define main0_IQP_Options_i450uA 8 1353 #define main0_IQP_Options_i500uA 9 1354 #define main0_IQP_Options_i550uA 10 1355 #define main0_IQP_Options_i600uA 11 1356 #define main0_IQP_Options_i650uA 12 1357 #define main0_IQP_Options_i700uA 13 1358 #define main0_IQP_Options_i750uA 14 1359 #define main0_IQP_Options_i800uA 15 1360 1361 /**************************************************************************** 1362 * Enums: main0_IDriver_Options 1363 */ 1364 #define main0_IDriver_Options_v680mV 0 1365 #define main0_IDriver_Options_v730mV 1 1366 #define main0_IDriver_Options_v780mV 2 1367 #define main0_IDriver_Options_v830mV 3 1368 #define main0_IDriver_Options_v880mV 4 1369 #define main0_IDriver_Options_v930mV 5 1370 #define main0_IDriver_Options_v980mV 6 1371 #define main0_IDriver_Options_v1010mV 7 1372 #define main0_IDriver_Options_v1040mV 8 1373 #define main0_IDriver_Options_v1060mV 9 1374 #define main0_IDriver_Options_v1070mV 10 1375 #define main0_IDriver_Options_v1080mV 11 1376 #define main0_IDriver_Options_v1085mV 12 1377 #define main0_IDriver_Options_v1090mV 13 1378 #define main0_IDriver_Options_v1095mV 14 1379 #define main0_IDriver_Options_v1100mV 15 1380 1381 /**************************************************************************** 1382 * Enums: main0_operationModes 1383 */ 1384 #define main0_operationModes_XGXS 0 1385 #define main0_operationModes_XGXG_nCC 1 1386 #define main0_operationModes_Indlane_OS8 4 1387 #define main0_operationModes_IndLane_OS5 5 1388 #define main0_operationModes_PCI 7 1389 #define main0_operationModes_XGXS_nLQ 8 1390 #define main0_operationModes_XGXS_nLQnCC 9 1391 #define main0_operationModes_PBypass 10 1392 #define main0_operationModes_PBypass_nDSK 11 1393 #define main0_operationModes_ComboCoreMode 12 1394 #define main0_operationModes_Clocks_off 15 1395 1396 /**************************************************************************** 1397 * Enums: main0_synce_enum 1398 */ 1399 #define main0_synce_enum_SYNCE_NO_DIV 0 1400 #define main0_synce_enum_SYNCE_DIV_7 1 1401 #define main0_synce_enum_SYNCE_DIV_11 2 1402 1403 /**************************************************************************** 1404 * Enums: main0_operationSpeeds 1405 */ 1406 #define main0_operationSpeeds_SPEED_2p5G_X1_10p3125 56 1407 #define main0_operationSpeeds_SPEED_1000M_10p3125 55 1408 #define main0_operationSpeeds_SPEED_100M_10p3125 54 1409 #define main0_operationSpeeds_SPEED_10M_10p3125 53 1410 #define main0_operationSpeeds_SPEED_10p5G_X4 50 1411 #define main0_operationSpeeds_SPEED_5G_KR1 49 1412 #define main0_operationSpeeds_SPEED_127G_X12 39 1413 #define main0_operationSpeeds_SPEED_120G_X12 38 1414 #define main0_operationSpeeds_SPEED_107G_X10 37 1415 #define main0_operationSpeeds_SPEED_100G_CR10 36 1416 #define main0_operationSpeeds_SPEED_42G_X4 35 1417 #define main0_operationSpeeds_SPEED_40G_CR4 34 1418 #define main0_operationSpeeds_SPEED_40G_KR4 33 1419 #define main0_operationSpeeds_SPEED_21G_X2 32 1420 #define main0_operationSpeeds_SPEED_20G_CR2 31 1421 #define main0_operationSpeeds_SPEED_20G_KR2 30 1422 #define main0_operationSpeeds_SPEED_10p6_X1 29 1423 #define main0_operationSpeeds_SPEED_10G_KR1 28 1424 #define main0_operationSpeeds_SPEED_40G_X4 27 1425 #define main0_operationSpeeds_SPEED_20G_X2 26 1426 #define main0_operationSpeeds_SPEED_20G_CX2 25 1427 #define main0_operationSpeeds_SPEED_31p5G_KR4 24 1428 #define main0_operationSpeeds_SPEED_31p5G_X4 23 1429 #define main0_operationSpeeds_SPEED_15p75G_X2 22 1430 #define main0_operationSpeeds_SPEED_25p45G_X4 21 1431 #define main0_operationSpeeds_SPEED_12p7G_X2 20 1432 #define main0_operationSpeeds_SPEED_21G_X4 19 1433 #define main0_operationSpeeds_SPEED_10p5G_X2 18 1434 #define main0_operationSpeeds_SPEED_20G_X4 17 1435 #define main0_operationSpeeds_SPEED_10G_X2 16 1436 #define main0_operationSpeeds_SPEED_10G_CX2 15 1437 #define main0_operationSpeeds_SPEED_20G_CX4 14 1438 #define main0_operationSpeeds_SPEED_16G_X4 13 1439 #define main0_operationSpeeds_SPEED_15G_X4 12 1440 #define main0_operationSpeeds_SPEED_13G_X4 11 1441 #define main0_operationSpeeds_SPEED_10G_X4 10 1442 #define main0_operationSpeeds_SPEED_10G_KX4 9 1443 #define main0_operationSpeeds_SPEED_10G_CX4 8 1444 #define main0_operationSpeeds_SPEED_5G_X1 7 1445 #define main0_operationSpeeds_SPEED_2p5G_X1 6 1446 #define main0_operationSpeeds_SPEED_1G_KX1 5 1447 #define main0_operationSpeeds_SPEED_1G_CX1 4 1448 #define main0_operationSpeeds_SPEED_1000M 3 1449 #define main0_operationSpeeds_SPEED_100M 2 1450 #define main0_operationSpeeds_SPEED_10M 1 1451 1452 /**************************************************************************** 1453 * Enums: main0_actualSpeeds 1454 */ 1455 #define main0_actualSpeeds_dr_10M 0 1456 #define main0_actualSpeeds_dr_100M 1 1457 #define main0_actualSpeeds_dr_1G 2 1458 #define main0_actualSpeeds_dr_2p5G 3 1459 #define main0_actualSpeeds_dr_5G_X4 4 1460 #define main0_actualSpeeds_dr_6G_X4 5 1461 #define main0_actualSpeeds_dr_10G_HiG 6 1462 #define main0_actualSpeeds_dr_10G_CX4 7 1463 #define main0_actualSpeeds_dr_12G_HiG 8 1464 #define main0_actualSpeeds_dr_12p5G_X4 9 1465 #define main0_actualSpeeds_dr_13G_X4 10 1466 #define main0_actualSpeeds_dr_15G_X4 11 1467 #define main0_actualSpeeds_dr_16G_X4 12 1468 #define main0_actualSpeeds_dr_1G_KX 13 1469 #define main0_actualSpeeds_dr_10G_KX4 14 1470 #define main0_actualSpeeds_dr_10G_KR 15 1471 #define main0_actualSpeeds_dr_5G 16 1472 #define main0_actualSpeeds_dr_6p4G 17 1473 #define main0_actualSpeeds_dr_20G_X4 18 1474 #define main0_actualSpeeds_dr_21G_X4 19 1475 #define main0_actualSpeeds_dr_25G_X4 20 1476 #define main0_actualSpeeds_dr_10G_HiG_DXGXS 21 1477 #define main0_actualSpeeds_dr_10G_DXGXS 22 1478 #define main0_actualSpeeds_dr_10p5G_HiG_DXGXS 23 1479 #define main0_actualSpeeds_dr_10p5G_DXGXS 24 1480 #define main0_actualSpeeds_dr_12p773G_HiG_DXGXS 25 1481 #define main0_actualSpeeds_dr_12p773G_DXGXS 26 1482 #define main0_actualSpeeds_dr_10G_XFI 27 1483 #define main0_actualSpeeds_dr_40G 28 1484 #define main0_actualSpeeds_dr_20G_HiG_DXGXS 29 1485 #define main0_actualSpeeds_dr_20G_DXGXS 30 1486 #define main0_actualSpeeds_dr_10G_SFI 31 1487 #define main0_actualSpeeds_dr_31p5G 32 1488 #define main0_actualSpeeds_dr_32p7G 33 1489 #define main0_actualSpeeds_dr_20G_SCR 34 1490 #define main0_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 1491 #define main0_actualSpeeds_dr_10G_DXGXS_SCR 36 1492 #define main0_actualSpeeds_dr_12G_R2 37 1493 #define main0_actualSpeeds_dr_10G_X2 38 1494 #define main0_actualSpeeds_dr_40G_KR4 39 1495 #define main0_actualSpeeds_dr_40G_CR4 40 1496 #define main0_actualSpeeds_dr_100G_CR10 41 1497 #define main0_actualSpeeds_dr_15p75G_DXGXS 44 1498 #define main0_actualSpeeds_dr_20G_KR2 57 1499 #define main0_actualSpeeds_dr_20G_CR2 58 1500 1501 /**************************************************************************** 1502 * Enums: main0_actualSpeedsMisc1 1503 */ 1504 #define main0_actualSpeedsMisc1_dr_2500BRCM_X1 16 1505 #define main0_actualSpeedsMisc1_dr_5000BRCM_X4 17 1506 #define main0_actualSpeedsMisc1_dr_6000BRCM_X4 18 1507 #define main0_actualSpeedsMisc1_dr_10GHiGig_X4 19 1508 #define main0_actualSpeedsMisc1_dr_10GBASE_CX4 20 1509 #define main0_actualSpeedsMisc1_dr_12GHiGig_X4 21 1510 #define main0_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 1511 #define main0_actualSpeedsMisc1_dr_13GHiGig_X4 23 1512 #define main0_actualSpeedsMisc1_dr_15GHiGig_X4 24 1513 #define main0_actualSpeedsMisc1_dr_16GHiGig_X4 25 1514 #define main0_actualSpeedsMisc1_dr_5000BRCM_X1 26 1515 #define main0_actualSpeedsMisc1_dr_6363BRCM_X1 27 1516 #define main0_actualSpeedsMisc1_dr_20GHiGig_X4 28 1517 #define main0_actualSpeedsMisc1_dr_21GHiGig_X4 29 1518 #define main0_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 1519 #define main0_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 1520 1521 /**************************************************************************** 1522 * Enums: main0_IndLaneModes 1523 */ 1524 #define main0_IndLaneModes_SWSDR_div2 0 1525 #define main0_IndLaneModes_SWSDR_div1 1 1526 #define main0_IndLaneModes_DWSDR_div2 2 1527 #define main0_IndLaneModes_DWSDR_div1 3 1528 1529 /**************************************************************************** 1530 * Enums: main0_prbsSelect 1531 */ 1532 #define main0_prbsSelect_prbs7 0 1533 #define main0_prbsSelect_prbs15 1 1534 #define main0_prbsSelect_prbs23 2 1535 #define main0_prbsSelect_prbs31 3 1536 1537 /**************************************************************************** 1538 * Enums: main0_vcoDivider 1539 */ 1540 #define main0_vcoDivider_div32 0 1541 #define main0_vcoDivider_div36 1 1542 #define main0_vcoDivider_div40 2 1543 #define main0_vcoDivider_div42 3 1544 #define main0_vcoDivider_div48 4 1545 #define main0_vcoDivider_div50 5 1546 #define main0_vcoDivider_div52 6 1547 #define main0_vcoDivider_div54 7 1548 #define main0_vcoDivider_div60 8 1549 #define main0_vcoDivider_div64 9 1550 #define main0_vcoDivider_div66 10 1551 #define main0_vcoDivider_div68 11 1552 #define main0_vcoDivider_div70 12 1553 #define main0_vcoDivider_div80 13 1554 #define main0_vcoDivider_div92 14 1555 #define main0_vcoDivider_div100 15 1556 1557 /**************************************************************************** 1558 * Enums: main0_refClkSelect 1559 */ 1560 #define main0_refClkSelect_clk_25MHz 0 1561 #define main0_refClkSelect_clk_100MHz 1 1562 #define main0_refClkSelect_clk_125MHz 2 1563 #define main0_refClkSelect_clk_156p25MHz 3 1564 #define main0_refClkSelect_clk_187p5MHz 4 1565 #define main0_refClkSelect_clk_161p25Mhz 5 1566 #define main0_refClkSelect_clk_50Mhz 6 1567 #define main0_refClkSelect_clk_106p25Mhz 7 1568 1569 /**************************************************************************** 1570 * Enums: main0_aerMMDdevTypeSelect 1571 */ 1572 #define main0_aerMMDdevTypeSelect_combo_core 0 1573 #define main0_aerMMDdevTypeSelect_PMA_PMD 1 1574 #define main0_aerMMDdevTypeSelect_PCS 3 1575 #define main0_aerMMDdevTypeSelect_PHY 4 1576 #define main0_aerMMDdevTypeSelect_DTE 5 1577 #define main0_aerMMDdevTypeSelect_CL73_AN 7 1578 1579 /**************************************************************************** 1580 * Enums: main0_aerMMDportSelect 1581 */ 1582 #define main0_aerMMDportSelect_ln0 0 1583 #define main0_aerMMDportSelect_ln1 1 1584 #define main0_aerMMDportSelect_ln2 2 1585 #define main0_aerMMDportSelect_ln3 3 1586 #define main0_aerMMDportSelect_BCST_ln0_1_2_3 511 1587 #define main0_aerMMDportSelect_BCST_ln0_1 512 1588 #define main0_aerMMDportSelect_BCST_ln2_3 513 1589 1590 /**************************************************************************** 1591 * Enums: main0_firmwareModeSelect 1592 */ 1593 #define main0_firmwareModeSelect_DEFAULT 0 1594 #define main0_firmwareModeSelect_SFP_OPT_LR 1 1595 #define main0_firmwareModeSelect_SFP_DAC 2 1596 #define main0_firmwareModeSelect_XLAUI 3 1597 #define main0_firmwareModeSelect_LONG_CH_6G 4 1598 1599 /**************************************************************************** 1600 * Enums: main0_tempIdxSelect 1601 */ 1602 #define main0_tempIdxSelect_LTE__22p9C 15 1603 #define main0_tempIdxSelect_LTE__12p6C 14 1604 #define main0_tempIdxSelect_LTE__3p0C 13 1605 #define main0_tempIdxSelect_LTE_6p7C 12 1606 #define main0_tempIdxSelect_LTE_16p4C 11 1607 #define main0_tempIdxSelect_LTE_26p6C 10 1608 #define main0_tempIdxSelect_LTE_36p3C 9 1609 #define main0_tempIdxSelect_LTE_46p0C 8 1610 #define main0_tempIdxSelect_LTE_56p2C 7 1611 #define main0_tempIdxSelect_LTE_65p9C 6 1612 #define main0_tempIdxSelect_LTE_75p6C 5 1613 #define main0_tempIdxSelect_LTE_85p3C 4 1614 #define main0_tempIdxSelect_LTE_95p5C 3 1615 #define main0_tempIdxSelect_LTE_105p2C 2 1616 #define main0_tempIdxSelect_LTE_114p9C 1 1617 #define main0_tempIdxSelect_LTE_125p1C 0 1618 1619 /**************************************************************************** 1620 * Enums: misc_cl36TxEEEStates_l 1621 */ 1622 #define misc_cl36TxEEEStates_l_TX_REFRESH 8 1623 #define misc_cl36TxEEEStates_l_TX_QUIET 4 1624 #define misc_cl36TxEEEStates_l_TX_SLEEP 2 1625 #define misc_cl36TxEEEStates_l_TX_ACTIVE 1 1626 1627 /**************************************************************************** 1628 * Enums: misc_cl36TxEEEStates_c 1629 */ 1630 #define misc_cl36TxEEEStates_c_TX_REFRESH 3 1631 #define misc_cl36TxEEEStates_c_TX_QUIET 2 1632 #define misc_cl36TxEEEStates_c_TX_SLEEP 1 1633 #define misc_cl36TxEEEStates_c_TX_ACTIVE 0 1634 1635 /**************************************************************************** 1636 * Enums: misc_cl49TxEEEStates_l 1637 */ 1638 #define misc_cl49TxEEEStates_l_SCR_RESET_2 64 1639 #define misc_cl49TxEEEStates_l_SCR_RESET_1 32 1640 #define misc_cl49TxEEEStates_l_TX_WAKE 16 1641 #define misc_cl49TxEEEStates_l_TX_REFRESH 8 1642 #define misc_cl49TxEEEStates_l_TX_QUIET 4 1643 #define misc_cl49TxEEEStates_l_TX_SLEEP 2 1644 #define misc_cl49TxEEEStates_l_TX_ACTIVE 1 1645 1646 /**************************************************************************** 1647 * Enums: misc_cl49TxEEEStates_c 1648 */ 1649 #define misc_cl49TxEEEStates_c_SCR_RESET_2 6 1650 #define misc_cl49TxEEEStates_c_SCR_RESET_1 5 1651 #define misc_cl49TxEEEStates_c_TX_WAKE 4 1652 #define misc_cl49TxEEEStates_c_TX_REFRESH 3 1653 #define misc_cl49TxEEEStates_c_TX_QUIET 2 1654 #define misc_cl49TxEEEStates_c_TX_SLEEP 1 1655 #define misc_cl49TxEEEStates_c_TX_ACTIVE 0 1656 1657 /**************************************************************************** 1658 * Enums: misc_cl36RxEEEStates_l 1659 */ 1660 #define misc_cl36RxEEEStates_l_RX_LINK_FAIL 32 1661 #define misc_cl36RxEEEStates_l_RX_WTF 16 1662 #define misc_cl36RxEEEStates_l_RX_WAKE 8 1663 #define misc_cl36RxEEEStates_l_RX_QUIET 4 1664 #define misc_cl36RxEEEStates_l_RX_SLEEP 2 1665 #define misc_cl36RxEEEStates_l_RX_ACTIVE 1 1666 1667 /**************************************************************************** 1668 * Enums: misc_cl36RxEEEStates_c 1669 */ 1670 #define misc_cl36RxEEEStates_c_RX_LINK_FAIL 5 1671 #define misc_cl36RxEEEStates_c_RX_WTF 4 1672 #define misc_cl36RxEEEStates_c_RX_WAKE 3 1673 #define misc_cl36RxEEEStates_c_RX_QUIET 2 1674 #define misc_cl36RxEEEStates_c_RX_SLEEP 1 1675 #define misc_cl36RxEEEStates_c_RX_ACTIVE 0 1676 1677 /**************************************************************************** 1678 * Enums: misc_cl49RxEEEStates_l 1679 */ 1680 #define misc_cl49RxEEEStates_l_RX_LINK_FAIL 32 1681 #define misc_cl49RxEEEStates_l_RX_WTF 16 1682 #define misc_cl49RxEEEStates_l_RX_WAKE 8 1683 #define misc_cl49RxEEEStates_l_RX_QUIET 4 1684 #define misc_cl49RxEEEStates_l_RX_SLEEP 2 1685 #define misc_cl49RxEEEStates_l_RX_ACTIVE 1 1686 1687 /**************************************************************************** 1688 * Enums: misc_cl49RxEEEStates_c 1689 */ 1690 #define misc_cl49RxEEEStates_c_RX_LINK_FAIL 5 1691 #define misc_cl49RxEEEStates_c_RX_WTF 4 1692 #define misc_cl49RxEEEStates_c_RX_WAKE 3 1693 #define misc_cl49RxEEEStates_c_RX_QUIET 2 1694 #define misc_cl49RxEEEStates_c_RX_SLEEP 1 1695 #define misc_cl49RxEEEStates_c_RX_ACTIVE 0 1696 1697 /**************************************************************************** 1698 * Enums: misc_cl48TxEEEStates_l 1699 */ 1700 #define misc_cl48TxEEEStates_l_TX_REFRESH 8 1701 #define misc_cl48TxEEEStates_l_TX_QUIET 4 1702 #define misc_cl48TxEEEStates_l_TX_SLEEP 2 1703 #define misc_cl48TxEEEStates_l_TX_ACTIVE 1 1704 1705 /**************************************************************************** 1706 * Enums: misc_cl48TxEEEStates_c 1707 */ 1708 #define misc_cl48TxEEEStates_c_TX_REFRESH 3 1709 #define misc_cl48TxEEEStates_c_TX_QUIET 2 1710 #define misc_cl48TxEEEStates_c_TX_SLEEP 1 1711 #define misc_cl48TxEEEStates_c_TX_ACTIVE 0 1712 1713 /**************************************************************************** 1714 * Enums: misc_cl48RxEEEStates_l 1715 */ 1716 #define misc_cl48RxEEEStates_l_RX_LINK_FAIL 32 1717 #define misc_cl48RxEEEStates_l_RX_WAKE 16 1718 #define misc_cl48RxEEEStates_l_RX_QUIET 8 1719 #define misc_cl48RxEEEStates_l_RX_DEACT 4 1720 #define misc_cl48RxEEEStates_l_RX_SLEEP 2 1721 #define misc_cl48RxEEEStates_l_RX_ACTIVE 1 1722 1723 /**************************************************************************** 1724 * Enums: misc_cl48RxEEEStates_c 1725 */ 1726 #define misc_cl48RxEEEStates_c_RX_LINK_FAIL 5 1727 #define misc_cl48RxEEEStates_c_RX_WAKE 4 1728 #define misc_cl48RxEEEStates_c_RX_QUIET 3 1729 #define misc_cl48RxEEEStates_c_RX_DEACT 2 1730 #define misc_cl48RxEEEStates_c_RX_SLEEP 1 1731 #define misc_cl48RxEEEStates_c_RX_ACTIVE 0 1732 1733 /**************************************************************************** 1734 * Enums: misc_IQP_Options 1735 */ 1736 #define misc_IQP_Options_i50uA 0 1737 #define misc_IQP_Options_i100uA 1 1738 #define misc_IQP_Options_i150uA 2 1739 #define misc_IQP_Options_i200uA 3 1740 #define misc_IQP_Options_i250uA 4 1741 #define misc_IQP_Options_i300uA 5 1742 #define misc_IQP_Options_i350uA 6 1743 #define misc_IQP_Options_i400uA 7 1744 #define misc_IQP_Options_i450uA 8 1745 #define misc_IQP_Options_i500uA 9 1746 #define misc_IQP_Options_i550uA 10 1747 #define misc_IQP_Options_i600uA 11 1748 #define misc_IQP_Options_i650uA 12 1749 #define misc_IQP_Options_i700uA 13 1750 #define misc_IQP_Options_i750uA 14 1751 #define misc_IQP_Options_i800uA 15 1752 1753 /**************************************************************************** 1754 * Enums: misc_IDriver_Options 1755 */ 1756 #define misc_IDriver_Options_v680mV 0 1757 #define misc_IDriver_Options_v730mV 1 1758 #define misc_IDriver_Options_v780mV 2 1759 #define misc_IDriver_Options_v830mV 3 1760 #define misc_IDriver_Options_v880mV 4 1761 #define misc_IDriver_Options_v930mV 5 1762 #define misc_IDriver_Options_v980mV 6 1763 #define misc_IDriver_Options_v1010mV 7 1764 #define misc_IDriver_Options_v1040mV 8 1765 #define misc_IDriver_Options_v1060mV 9 1766 #define misc_IDriver_Options_v1070mV 10 1767 #define misc_IDriver_Options_v1080mV 11 1768 #define misc_IDriver_Options_v1085mV 12 1769 #define misc_IDriver_Options_v1090mV 13 1770 #define misc_IDriver_Options_v1095mV 14 1771 #define misc_IDriver_Options_v1100mV 15 1772 1773 /**************************************************************************** 1774 * Enums: misc_operationModes 1775 */ 1776 #define misc_operationModes_XGXS 0 1777 #define misc_operationModes_XGXG_nCC 1 1778 #define misc_operationModes_Indlane_OS8 4 1779 #define misc_operationModes_IndLane_OS5 5 1780 #define misc_operationModes_PCI 7 1781 #define misc_operationModes_XGXS_nLQ 8 1782 #define misc_operationModes_XGXS_nLQnCC 9 1783 #define misc_operationModes_PBypass 10 1784 #define misc_operationModes_PBypass_nDSK 11 1785 #define misc_operationModes_ComboCoreMode 12 1786 #define misc_operationModes_Clocks_off 15 1787 1788 /**************************************************************************** 1789 * Enums: misc_synce_enum 1790 */ 1791 #define misc_synce_enum_SYNCE_NO_DIV 0 1792 #define misc_synce_enum_SYNCE_DIV_7 1 1793 #define misc_synce_enum_SYNCE_DIV_11 2 1794 1795 /**************************************************************************** 1796 * Enums: misc_operationSpeeds 1797 */ 1798 #define misc_operationSpeeds_SPEED_2p5G_X1_10p3125 56 1799 #define misc_operationSpeeds_SPEED_1000M_10p3125 55 1800 #define misc_operationSpeeds_SPEED_100M_10p3125 54 1801 #define misc_operationSpeeds_SPEED_10M_10p3125 53 1802 #define misc_operationSpeeds_SPEED_10p5G_X4 50 1803 #define misc_operationSpeeds_SPEED_5G_KR1 49 1804 #define misc_operationSpeeds_SPEED_127G_X12 39 1805 #define misc_operationSpeeds_SPEED_120G_X12 38 1806 #define misc_operationSpeeds_SPEED_107G_X10 37 1807 #define misc_operationSpeeds_SPEED_100G_CR10 36 1808 #define misc_operationSpeeds_SPEED_42G_X4 35 1809 #define misc_operationSpeeds_SPEED_40G_CR4 34 1810 #define misc_operationSpeeds_SPEED_40G_KR4 33 1811 #define misc_operationSpeeds_SPEED_21G_X2 32 1812 #define misc_operationSpeeds_SPEED_20G_CR2 31 1813 #define misc_operationSpeeds_SPEED_20G_KR2 30 1814 #define misc_operationSpeeds_SPEED_10p6_X1 29 1815 #define misc_operationSpeeds_SPEED_10G_KR1 28 1816 #define misc_operationSpeeds_SPEED_40G_X4 27 1817 #define misc_operationSpeeds_SPEED_20G_X2 26 1818 #define misc_operationSpeeds_SPEED_20G_CX2 25 1819 #define misc_operationSpeeds_SPEED_31p5G_KR4 24 1820 #define misc_operationSpeeds_SPEED_31p5G_X4 23 1821 #define misc_operationSpeeds_SPEED_15p75G_X2 22 1822 #define misc_operationSpeeds_SPEED_25p45G_X4 21 1823 #define misc_operationSpeeds_SPEED_12p7G_X2 20 1824 #define misc_operationSpeeds_SPEED_21G_X4 19 1825 #define misc_operationSpeeds_SPEED_10p5G_X2 18 1826 #define misc_operationSpeeds_SPEED_20G_X4 17 1827 #define misc_operationSpeeds_SPEED_10G_X2 16 1828 #define misc_operationSpeeds_SPEED_10G_CX2 15 1829 #define misc_operationSpeeds_SPEED_20G_CX4 14 1830 #define misc_operationSpeeds_SPEED_16G_X4 13 1831 #define misc_operationSpeeds_SPEED_15G_X4 12 1832 #define misc_operationSpeeds_SPEED_13G_X4 11 1833 #define misc_operationSpeeds_SPEED_10G_X4 10 1834 #define misc_operationSpeeds_SPEED_10G_KX4 9 1835 #define misc_operationSpeeds_SPEED_10G_CX4 8 1836 #define misc_operationSpeeds_SPEED_5G_X1 7 1837 #define misc_operationSpeeds_SPEED_2p5G_X1 6 1838 #define misc_operationSpeeds_SPEED_1G_KX1 5 1839 #define misc_operationSpeeds_SPEED_1G_CX1 4 1840 #define misc_operationSpeeds_SPEED_1000M 3 1841 #define misc_operationSpeeds_SPEED_100M 2 1842 #define misc_operationSpeeds_SPEED_10M 1 1843 1844 /**************************************************************************** 1845 * Enums: misc_actualSpeeds 1846 */ 1847 #define misc_actualSpeeds_dr_10M 0 1848 #define misc_actualSpeeds_dr_100M 1 1849 #define misc_actualSpeeds_dr_1G 2 1850 #define misc_actualSpeeds_dr_2p5G 3 1851 #define misc_actualSpeeds_dr_5G_X4 4 1852 #define misc_actualSpeeds_dr_6G_X4 5 1853 #define misc_actualSpeeds_dr_10G_HiG 6 1854 #define misc_actualSpeeds_dr_10G_CX4 7 1855 #define misc_actualSpeeds_dr_12G_HiG 8 1856 #define misc_actualSpeeds_dr_12p5G_X4 9 1857 #define misc_actualSpeeds_dr_13G_X4 10 1858 #define misc_actualSpeeds_dr_15G_X4 11 1859 #define misc_actualSpeeds_dr_16G_X4 12 1860 #define misc_actualSpeeds_dr_1G_KX 13 1861 #define misc_actualSpeeds_dr_10G_KX4 14 1862 #define misc_actualSpeeds_dr_10G_KR 15 1863 #define misc_actualSpeeds_dr_5G 16 1864 #define misc_actualSpeeds_dr_6p4G 17 1865 #define misc_actualSpeeds_dr_20G_X4 18 1866 #define misc_actualSpeeds_dr_21G_X4 19 1867 #define misc_actualSpeeds_dr_25G_X4 20 1868 #define misc_actualSpeeds_dr_10G_HiG_DXGXS 21 1869 #define misc_actualSpeeds_dr_10G_DXGXS 22 1870 #define misc_actualSpeeds_dr_10p5G_HiG_DXGXS 23 1871 #define misc_actualSpeeds_dr_10p5G_DXGXS 24 1872 #define misc_actualSpeeds_dr_12p773G_HiG_DXGXS 25 1873 #define misc_actualSpeeds_dr_12p773G_DXGXS 26 1874 #define misc_actualSpeeds_dr_10G_XFI 27 1875 #define misc_actualSpeeds_dr_40G 28 1876 #define misc_actualSpeeds_dr_20G_HiG_DXGXS 29 1877 #define misc_actualSpeeds_dr_20G_DXGXS 30 1878 #define misc_actualSpeeds_dr_10G_SFI 31 1879 #define misc_actualSpeeds_dr_31p5G 32 1880 #define misc_actualSpeeds_dr_32p7G 33 1881 #define misc_actualSpeeds_dr_20G_SCR 34 1882 #define misc_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 1883 #define misc_actualSpeeds_dr_10G_DXGXS_SCR 36 1884 #define misc_actualSpeeds_dr_12G_R2 37 1885 #define misc_actualSpeeds_dr_10G_X2 38 1886 #define misc_actualSpeeds_dr_40G_KR4 39 1887 #define misc_actualSpeeds_dr_40G_CR4 40 1888 #define misc_actualSpeeds_dr_100G_CR10 41 1889 #define misc_actualSpeeds_dr_15p75G_DXGXS 44 1890 #define misc_actualSpeeds_dr_20G_KR2 57 1891 #define misc_actualSpeeds_dr_20G_CR2 58 1892 1893 /**************************************************************************** 1894 * Enums: misc_actualSpeedsMisc1 1895 */ 1896 #define misc_actualSpeedsMisc1_dr_2500BRCM_X1 16 1897 #define misc_actualSpeedsMisc1_dr_5000BRCM_X4 17 1898 #define misc_actualSpeedsMisc1_dr_6000BRCM_X4 18 1899 #define misc_actualSpeedsMisc1_dr_10GHiGig_X4 19 1900 #define misc_actualSpeedsMisc1_dr_10GBASE_CX4 20 1901 #define misc_actualSpeedsMisc1_dr_12GHiGig_X4 21 1902 #define misc_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 1903 #define misc_actualSpeedsMisc1_dr_13GHiGig_X4 23 1904 #define misc_actualSpeedsMisc1_dr_15GHiGig_X4 24 1905 #define misc_actualSpeedsMisc1_dr_16GHiGig_X4 25 1906 #define misc_actualSpeedsMisc1_dr_5000BRCM_X1 26 1907 #define misc_actualSpeedsMisc1_dr_6363BRCM_X1 27 1908 #define misc_actualSpeedsMisc1_dr_20GHiGig_X4 28 1909 #define misc_actualSpeedsMisc1_dr_21GHiGig_X4 29 1910 #define misc_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 1911 #define misc_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 1912 1913 /**************************************************************************** 1914 * Enums: misc_IndLaneModes 1915 */ 1916 #define misc_IndLaneModes_SWSDR_div2 0 1917 #define misc_IndLaneModes_SWSDR_div1 1 1918 #define misc_IndLaneModes_DWSDR_div2 2 1919 #define misc_IndLaneModes_DWSDR_div1 3 1920 1921 /**************************************************************************** 1922 * Enums: misc_prbsSelect 1923 */ 1924 #define misc_prbsSelect_prbs7 0 1925 #define misc_prbsSelect_prbs15 1 1926 #define misc_prbsSelect_prbs23 2 1927 #define misc_prbsSelect_prbs31 3 1928 1929 /**************************************************************************** 1930 * Enums: misc_vcoDivider 1931 */ 1932 #define misc_vcoDivider_div32 0 1933 #define misc_vcoDivider_div36 1 1934 #define misc_vcoDivider_div40 2 1935 #define misc_vcoDivider_div42 3 1936 #define misc_vcoDivider_div48 4 1937 #define misc_vcoDivider_div50 5 1938 #define misc_vcoDivider_div52 6 1939 #define misc_vcoDivider_div54 7 1940 #define misc_vcoDivider_div60 8 1941 #define misc_vcoDivider_div64 9 1942 #define misc_vcoDivider_div66 10 1943 #define misc_vcoDivider_div68 11 1944 #define misc_vcoDivider_div70 12 1945 #define misc_vcoDivider_div80 13 1946 #define misc_vcoDivider_div92 14 1947 #define misc_vcoDivider_div100 15 1948 1949 /**************************************************************************** 1950 * Enums: misc_refClkSelect 1951 */ 1952 #define misc_refClkSelect_clk_25MHz 0 1953 #define misc_refClkSelect_clk_100MHz 1 1954 #define misc_refClkSelect_clk_125MHz 2 1955 #define misc_refClkSelect_clk_156p25MHz 3 1956 #define misc_refClkSelect_clk_187p5MHz 4 1957 #define misc_refClkSelect_clk_161p25Mhz 5 1958 #define misc_refClkSelect_clk_50Mhz 6 1959 #define misc_refClkSelect_clk_106p25Mhz 7 1960 1961 /**************************************************************************** 1962 * Enums: misc_aerMMDdevTypeSelect 1963 */ 1964 #define misc_aerMMDdevTypeSelect_combo_core 0 1965 #define misc_aerMMDdevTypeSelect_PMA_PMD 1 1966 #define misc_aerMMDdevTypeSelect_PCS 3 1967 #define misc_aerMMDdevTypeSelect_PHY 4 1968 #define misc_aerMMDdevTypeSelect_DTE 5 1969 #define misc_aerMMDdevTypeSelect_CL73_AN 7 1970 1971 /**************************************************************************** 1972 * Enums: misc_aerMMDportSelect 1973 */ 1974 #define misc_aerMMDportSelect_ln0 0 1975 #define misc_aerMMDportSelect_ln1 1 1976 #define misc_aerMMDportSelect_ln2 2 1977 #define misc_aerMMDportSelect_ln3 3 1978 #define misc_aerMMDportSelect_BCST_ln0_1_2_3 511 1979 #define misc_aerMMDportSelect_BCST_ln0_1 512 1980 #define misc_aerMMDportSelect_BCST_ln2_3 513 1981 1982 /**************************************************************************** 1983 * Enums: misc_firmwareModeSelect 1984 */ 1985 #define misc_firmwareModeSelect_DEFAULT 0 1986 #define misc_firmwareModeSelect_SFP_OPT_LR 1 1987 #define misc_firmwareModeSelect_SFP_DAC 2 1988 #define misc_firmwareModeSelect_XLAUI 3 1989 #define misc_firmwareModeSelect_LONG_CH_6G 4 1990 1991 /**************************************************************************** 1992 * Enums: misc_tempIdxSelect 1993 */ 1994 #define misc_tempIdxSelect_LTE__22p9C 15 1995 #define misc_tempIdxSelect_LTE__12p6C 14 1996 #define misc_tempIdxSelect_LTE__3p0C 13 1997 #define misc_tempIdxSelect_LTE_6p7C 12 1998 #define misc_tempIdxSelect_LTE_16p4C 11 1999 #define misc_tempIdxSelect_LTE_26p6C 10 2000 #define misc_tempIdxSelect_LTE_36p3C 9 2001 #define misc_tempIdxSelect_LTE_46p0C 8 2002 #define misc_tempIdxSelect_LTE_56p2C 7 2003 #define misc_tempIdxSelect_LTE_65p9C 6 2004 #define misc_tempIdxSelect_LTE_75p6C 5 2005 #define misc_tempIdxSelect_LTE_85p3C 4 2006 #define misc_tempIdxSelect_LTE_95p5C 3 2007 #define misc_tempIdxSelect_LTE_105p2C 2 2008 #define misc_tempIdxSelect_LTE_114p9C 1 2009 #define misc_tempIdxSelect_LTE_125p1C 0 2010 2011 /**************************************************************************** 2012 * Enums: sc_x1_speed_override0_cl36TxEEEStates_l 2013 */ 2014 #define sc_x1_speed_override0_cl36TxEEEStates_l_TX_REFRESH 8 2015 #define sc_x1_speed_override0_cl36TxEEEStates_l_TX_QUIET 4 2016 #define sc_x1_speed_override0_cl36TxEEEStates_l_TX_SLEEP 2 2017 #define sc_x1_speed_override0_cl36TxEEEStates_l_TX_ACTIVE 1 2018 2019 /**************************************************************************** 2020 * Enums: sc_x1_speed_override0_cl36TxEEEStates_c 2021 */ 2022 #define sc_x1_speed_override0_cl36TxEEEStates_c_TX_REFRESH 3 2023 #define sc_x1_speed_override0_cl36TxEEEStates_c_TX_QUIET 2 2024 #define sc_x1_speed_override0_cl36TxEEEStates_c_TX_SLEEP 1 2025 #define sc_x1_speed_override0_cl36TxEEEStates_c_TX_ACTIVE 0 2026 2027 /**************************************************************************** 2028 * Enums: sc_x1_speed_override0_cl49TxEEEStates_l 2029 */ 2030 #define sc_x1_speed_override0_cl49TxEEEStates_l_SCR_RESET_2 64 2031 #define sc_x1_speed_override0_cl49TxEEEStates_l_SCR_RESET_1 32 2032 #define sc_x1_speed_override0_cl49TxEEEStates_l_TX_WAKE 16 2033 #define sc_x1_speed_override0_cl49TxEEEStates_l_TX_REFRESH 8 2034 #define sc_x1_speed_override0_cl49TxEEEStates_l_TX_QUIET 4 2035 #define sc_x1_speed_override0_cl49TxEEEStates_l_TX_SLEEP 2 2036 #define sc_x1_speed_override0_cl49TxEEEStates_l_TX_ACTIVE 1 2037 2038 /**************************************************************************** 2039 * Enums: sc_x1_speed_override0_cl49TxEEEStates_c 2040 */ 2041 #define sc_x1_speed_override0_cl49TxEEEStates_c_SCR_RESET_2 6 2042 #define sc_x1_speed_override0_cl49TxEEEStates_c_SCR_RESET_1 5 2043 #define sc_x1_speed_override0_cl49TxEEEStates_c_TX_WAKE 4 2044 #define sc_x1_speed_override0_cl49TxEEEStates_c_TX_REFRESH 3 2045 #define sc_x1_speed_override0_cl49TxEEEStates_c_TX_QUIET 2 2046 #define sc_x1_speed_override0_cl49TxEEEStates_c_TX_SLEEP 1 2047 #define sc_x1_speed_override0_cl49TxEEEStates_c_TX_ACTIVE 0 2048 2049 /**************************************************************************** 2050 * Enums: sc_x1_speed_override0_cl36RxEEEStates_l 2051 */ 2052 #define sc_x1_speed_override0_cl36RxEEEStates_l_RX_LINK_FAIL 32 2053 #define sc_x1_speed_override0_cl36RxEEEStates_l_RX_WTF 16 2054 #define sc_x1_speed_override0_cl36RxEEEStates_l_RX_WAKE 8 2055 #define sc_x1_speed_override0_cl36RxEEEStates_l_RX_QUIET 4 2056 #define sc_x1_speed_override0_cl36RxEEEStates_l_RX_SLEEP 2 2057 #define sc_x1_speed_override0_cl36RxEEEStates_l_RX_ACTIVE 1 2058 2059 /**************************************************************************** 2060 * Enums: sc_x1_speed_override0_cl36RxEEEStates_c 2061 */ 2062 #define sc_x1_speed_override0_cl36RxEEEStates_c_RX_LINK_FAIL 5 2063 #define sc_x1_speed_override0_cl36RxEEEStates_c_RX_WTF 4 2064 #define sc_x1_speed_override0_cl36RxEEEStates_c_RX_WAKE 3 2065 #define sc_x1_speed_override0_cl36RxEEEStates_c_RX_QUIET 2 2066 #define sc_x1_speed_override0_cl36RxEEEStates_c_RX_SLEEP 1 2067 #define sc_x1_speed_override0_cl36RxEEEStates_c_RX_ACTIVE 0 2068 2069 /**************************************************************************** 2070 * Enums: sc_x1_speed_override0_cl49RxEEEStates_l 2071 */ 2072 #define sc_x1_speed_override0_cl49RxEEEStates_l_RX_LINK_FAIL 32 2073 #define sc_x1_speed_override0_cl49RxEEEStates_l_RX_WTF 16 2074 #define sc_x1_speed_override0_cl49RxEEEStates_l_RX_WAKE 8 2075 #define sc_x1_speed_override0_cl49RxEEEStates_l_RX_QUIET 4 2076 #define sc_x1_speed_override0_cl49RxEEEStates_l_RX_SLEEP 2 2077 #define sc_x1_speed_override0_cl49RxEEEStates_l_RX_ACTIVE 1 2078 2079 /**************************************************************************** 2080 * Enums: sc_x1_speed_override0_cl49RxEEEStates_c 2081 */ 2082 #define sc_x1_speed_override0_cl49RxEEEStates_c_RX_LINK_FAIL 5 2083 #define sc_x1_speed_override0_cl49RxEEEStates_c_RX_WTF 4 2084 #define sc_x1_speed_override0_cl49RxEEEStates_c_RX_WAKE 3 2085 #define sc_x1_speed_override0_cl49RxEEEStates_c_RX_QUIET 2 2086 #define sc_x1_speed_override0_cl49RxEEEStates_c_RX_SLEEP 1 2087 #define sc_x1_speed_override0_cl49RxEEEStates_c_RX_ACTIVE 0 2088 2089 /**************************************************************************** 2090 * Enums: sc_x1_speed_override0_cl48TxEEEStates_l 2091 */ 2092 #define sc_x1_speed_override0_cl48TxEEEStates_l_TX_REFRESH 8 2093 #define sc_x1_speed_override0_cl48TxEEEStates_l_TX_QUIET 4 2094 #define sc_x1_speed_override0_cl48TxEEEStates_l_TX_SLEEP 2 2095 #define sc_x1_speed_override0_cl48TxEEEStates_l_TX_ACTIVE 1 2096 2097 /**************************************************************************** 2098 * Enums: sc_x1_speed_override0_cl48TxEEEStates_c 2099 */ 2100 #define sc_x1_speed_override0_cl48TxEEEStates_c_TX_REFRESH 3 2101 #define sc_x1_speed_override0_cl48TxEEEStates_c_TX_QUIET 2 2102 #define sc_x1_speed_override0_cl48TxEEEStates_c_TX_SLEEP 1 2103 #define sc_x1_speed_override0_cl48TxEEEStates_c_TX_ACTIVE 0 2104 2105 /**************************************************************************** 2106 * Enums: sc_x1_speed_override0_cl48RxEEEStates_l 2107 */ 2108 #define sc_x1_speed_override0_cl48RxEEEStates_l_RX_LINK_FAIL 32 2109 #define sc_x1_speed_override0_cl48RxEEEStates_l_RX_WAKE 16 2110 #define sc_x1_speed_override0_cl48RxEEEStates_l_RX_QUIET 8 2111 #define sc_x1_speed_override0_cl48RxEEEStates_l_RX_DEACT 4 2112 #define sc_x1_speed_override0_cl48RxEEEStates_l_RX_SLEEP 2 2113 #define sc_x1_speed_override0_cl48RxEEEStates_l_RX_ACTIVE 1 2114 2115 /**************************************************************************** 2116 * Enums: sc_x1_speed_override0_cl48RxEEEStates_c 2117 */ 2118 #define sc_x1_speed_override0_cl48RxEEEStates_c_RX_LINK_FAIL 5 2119 #define sc_x1_speed_override0_cl48RxEEEStates_c_RX_WAKE 4 2120 #define sc_x1_speed_override0_cl48RxEEEStates_c_RX_QUIET 3 2121 #define sc_x1_speed_override0_cl48RxEEEStates_c_RX_DEACT 2 2122 #define sc_x1_speed_override0_cl48RxEEEStates_c_RX_SLEEP 1 2123 #define sc_x1_speed_override0_cl48RxEEEStates_c_RX_ACTIVE 0 2124 2125 /**************************************************************************** 2126 * Enums: sc_x1_speed_override0_IQP_Options 2127 */ 2128 #define sc_x1_speed_override0_IQP_Options_i50uA 0 2129 #define sc_x1_speed_override0_IQP_Options_i100uA 1 2130 #define sc_x1_speed_override0_IQP_Options_i150uA 2 2131 #define sc_x1_speed_override0_IQP_Options_i200uA 3 2132 #define sc_x1_speed_override0_IQP_Options_i250uA 4 2133 #define sc_x1_speed_override0_IQP_Options_i300uA 5 2134 #define sc_x1_speed_override0_IQP_Options_i350uA 6 2135 #define sc_x1_speed_override0_IQP_Options_i400uA 7 2136 #define sc_x1_speed_override0_IQP_Options_i450uA 8 2137 #define sc_x1_speed_override0_IQP_Options_i500uA 9 2138 #define sc_x1_speed_override0_IQP_Options_i550uA 10 2139 #define sc_x1_speed_override0_IQP_Options_i600uA 11 2140 #define sc_x1_speed_override0_IQP_Options_i650uA 12 2141 #define sc_x1_speed_override0_IQP_Options_i700uA 13 2142 #define sc_x1_speed_override0_IQP_Options_i750uA 14 2143 #define sc_x1_speed_override0_IQP_Options_i800uA 15 2144 2145 /**************************************************************************** 2146 * Enums: sc_x1_speed_override0_IDriver_Options 2147 */ 2148 #define sc_x1_speed_override0_IDriver_Options_v680mV 0 2149 #define sc_x1_speed_override0_IDriver_Options_v730mV 1 2150 #define sc_x1_speed_override0_IDriver_Options_v780mV 2 2151 #define sc_x1_speed_override0_IDriver_Options_v830mV 3 2152 #define sc_x1_speed_override0_IDriver_Options_v880mV 4 2153 #define sc_x1_speed_override0_IDriver_Options_v930mV 5 2154 #define sc_x1_speed_override0_IDriver_Options_v980mV 6 2155 #define sc_x1_speed_override0_IDriver_Options_v1010mV 7 2156 #define sc_x1_speed_override0_IDriver_Options_v1040mV 8 2157 #define sc_x1_speed_override0_IDriver_Options_v1060mV 9 2158 #define sc_x1_speed_override0_IDriver_Options_v1070mV 10 2159 #define sc_x1_speed_override0_IDriver_Options_v1080mV 11 2160 #define sc_x1_speed_override0_IDriver_Options_v1085mV 12 2161 #define sc_x1_speed_override0_IDriver_Options_v1090mV 13 2162 #define sc_x1_speed_override0_IDriver_Options_v1095mV 14 2163 #define sc_x1_speed_override0_IDriver_Options_v1100mV 15 2164 2165 /**************************************************************************** 2166 * Enums: sc_x1_speed_override0_operationModes 2167 */ 2168 #define sc_x1_speed_override0_operationModes_XGXS 0 2169 #define sc_x1_speed_override0_operationModes_XGXG_nCC 1 2170 #define sc_x1_speed_override0_operationModes_Indlane_OS8 4 2171 #define sc_x1_speed_override0_operationModes_IndLane_OS5 5 2172 #define sc_x1_speed_override0_operationModes_PCI 7 2173 #define sc_x1_speed_override0_operationModes_XGXS_nLQ 8 2174 #define sc_x1_speed_override0_operationModes_XGXS_nLQnCC 9 2175 #define sc_x1_speed_override0_operationModes_PBypass 10 2176 #define sc_x1_speed_override0_operationModes_PBypass_nDSK 11 2177 #define sc_x1_speed_override0_operationModes_ComboCoreMode 12 2178 #define sc_x1_speed_override0_operationModes_Clocks_off 15 2179 2180 /**************************************************************************** 2181 * Enums: sc_x1_speed_override0_synce_enum 2182 */ 2183 #define sc_x1_speed_override0_synce_enum_SYNCE_NO_DIV 0 2184 #define sc_x1_speed_override0_synce_enum_SYNCE_DIV_7 1 2185 #define sc_x1_speed_override0_synce_enum_SYNCE_DIV_11 2 2186 2187 /**************************************************************************** 2188 * Enums: sc_x1_speed_override0_operationSpeeds 2189 */ 2190 #define sc_x1_speed_override0_operationSpeeds_SPEED_2p5G_X1_10p3125 56 2191 #define sc_x1_speed_override0_operationSpeeds_SPEED_1000M_10p3125 55 2192 #define sc_x1_speed_override0_operationSpeeds_SPEED_100M_10p3125 54 2193 #define sc_x1_speed_override0_operationSpeeds_SPEED_10M_10p3125 53 2194 #define sc_x1_speed_override0_operationSpeeds_SPEED_10p5G_X4 50 2195 #define sc_x1_speed_override0_operationSpeeds_SPEED_5G_KR1 49 2196 #define sc_x1_speed_override0_operationSpeeds_SPEED_127G_X12 39 2197 #define sc_x1_speed_override0_operationSpeeds_SPEED_120G_X12 38 2198 #define sc_x1_speed_override0_operationSpeeds_SPEED_107G_X10 37 2199 #define sc_x1_speed_override0_operationSpeeds_SPEED_100G_CR10 36 2200 #define sc_x1_speed_override0_operationSpeeds_SPEED_42G_X4 35 2201 #define sc_x1_speed_override0_operationSpeeds_SPEED_40G_CR4 34 2202 #define sc_x1_speed_override0_operationSpeeds_SPEED_40G_KR4 33 2203 #define sc_x1_speed_override0_operationSpeeds_SPEED_21G_X2 32 2204 #define sc_x1_speed_override0_operationSpeeds_SPEED_20G_CR2 31 2205 #define sc_x1_speed_override0_operationSpeeds_SPEED_20G_KR2 30 2206 #define sc_x1_speed_override0_operationSpeeds_SPEED_10p6_X1 29 2207 #define sc_x1_speed_override0_operationSpeeds_SPEED_10G_KR1 28 2208 #define sc_x1_speed_override0_operationSpeeds_SPEED_40G_X4 27 2209 #define sc_x1_speed_override0_operationSpeeds_SPEED_20G_X2 26 2210 #define sc_x1_speed_override0_operationSpeeds_SPEED_20G_CX2 25 2211 #define sc_x1_speed_override0_operationSpeeds_SPEED_31p5G_KR4 24 2212 #define sc_x1_speed_override0_operationSpeeds_SPEED_31p5G_X4 23 2213 #define sc_x1_speed_override0_operationSpeeds_SPEED_15p75G_X2 22 2214 #define sc_x1_speed_override0_operationSpeeds_SPEED_25p45G_X4 21 2215 #define sc_x1_speed_override0_operationSpeeds_SPEED_12p7G_X2 20 2216 #define sc_x1_speed_override0_operationSpeeds_SPEED_21G_X4 19 2217 #define sc_x1_speed_override0_operationSpeeds_SPEED_10p5G_X2 18 2218 #define sc_x1_speed_override0_operationSpeeds_SPEED_20G_X4 17 2219 #define sc_x1_speed_override0_operationSpeeds_SPEED_10G_X2 16 2220 #define sc_x1_speed_override0_operationSpeeds_SPEED_10G_CX2 15 2221 #define sc_x1_speed_override0_operationSpeeds_SPEED_20G_CX4 14 2222 #define sc_x1_speed_override0_operationSpeeds_SPEED_16G_X4 13 2223 #define sc_x1_speed_override0_operationSpeeds_SPEED_15G_X4 12 2224 #define sc_x1_speed_override0_operationSpeeds_SPEED_13G_X4 11 2225 #define sc_x1_speed_override0_operationSpeeds_SPEED_10G_X4 10 2226 #define sc_x1_speed_override0_operationSpeeds_SPEED_10G_KX4 9 2227 #define sc_x1_speed_override0_operationSpeeds_SPEED_10G_CX4 8 2228 #define sc_x1_speed_override0_operationSpeeds_SPEED_5G_X1 7 2229 #define sc_x1_speed_override0_operationSpeeds_SPEED_2p5G_X1 6 2230 #define sc_x1_speed_override0_operationSpeeds_SPEED_1G_KX1 5 2231 #define sc_x1_speed_override0_operationSpeeds_SPEED_1G_CX1 4 2232 #define sc_x1_speed_override0_operationSpeeds_SPEED_1000M 3 2233 #define sc_x1_speed_override0_operationSpeeds_SPEED_100M 2 2234 #define sc_x1_speed_override0_operationSpeeds_SPEED_10M 1 2235 2236 /**************************************************************************** 2237 * Enums: sc_x1_speed_override0_actualSpeeds 2238 */ 2239 #define sc_x1_speed_override0_actualSpeeds_dr_10M 0 2240 #define sc_x1_speed_override0_actualSpeeds_dr_100M 1 2241 #define sc_x1_speed_override0_actualSpeeds_dr_1G 2 2242 #define sc_x1_speed_override0_actualSpeeds_dr_2p5G 3 2243 #define sc_x1_speed_override0_actualSpeeds_dr_5G_X4 4 2244 #define sc_x1_speed_override0_actualSpeeds_dr_6G_X4 5 2245 #define sc_x1_speed_override0_actualSpeeds_dr_10G_HiG 6 2246 #define sc_x1_speed_override0_actualSpeeds_dr_10G_CX4 7 2247 #define sc_x1_speed_override0_actualSpeeds_dr_12G_HiG 8 2248 #define sc_x1_speed_override0_actualSpeeds_dr_12p5G_X4 9 2249 #define sc_x1_speed_override0_actualSpeeds_dr_13G_X4 10 2250 #define sc_x1_speed_override0_actualSpeeds_dr_15G_X4 11 2251 #define sc_x1_speed_override0_actualSpeeds_dr_16G_X4 12 2252 #define sc_x1_speed_override0_actualSpeeds_dr_1G_KX 13 2253 #define sc_x1_speed_override0_actualSpeeds_dr_10G_KX4 14 2254 #define sc_x1_speed_override0_actualSpeeds_dr_10G_KR 15 2255 #define sc_x1_speed_override0_actualSpeeds_dr_5G 16 2256 #define sc_x1_speed_override0_actualSpeeds_dr_6p4G 17 2257 #define sc_x1_speed_override0_actualSpeeds_dr_20G_X4 18 2258 #define sc_x1_speed_override0_actualSpeeds_dr_21G_X4 19 2259 #define sc_x1_speed_override0_actualSpeeds_dr_25G_X4 20 2260 #define sc_x1_speed_override0_actualSpeeds_dr_10G_HiG_DXGXS 21 2261 #define sc_x1_speed_override0_actualSpeeds_dr_10G_DXGXS 22 2262 #define sc_x1_speed_override0_actualSpeeds_dr_10p5G_HiG_DXGXS 23 2263 #define sc_x1_speed_override0_actualSpeeds_dr_10p5G_DXGXS 24 2264 #define sc_x1_speed_override0_actualSpeeds_dr_12p773G_HiG_DXGXS 25 2265 #define sc_x1_speed_override0_actualSpeeds_dr_12p773G_DXGXS 26 2266 #define sc_x1_speed_override0_actualSpeeds_dr_10G_XFI 27 2267 #define sc_x1_speed_override0_actualSpeeds_dr_40G 28 2268 #define sc_x1_speed_override0_actualSpeeds_dr_20G_HiG_DXGXS 29 2269 #define sc_x1_speed_override0_actualSpeeds_dr_20G_DXGXS 30 2270 #define sc_x1_speed_override0_actualSpeeds_dr_10G_SFI 31 2271 #define sc_x1_speed_override0_actualSpeeds_dr_31p5G 32 2272 #define sc_x1_speed_override0_actualSpeeds_dr_32p7G 33 2273 #define sc_x1_speed_override0_actualSpeeds_dr_20G_SCR 34 2274 #define sc_x1_speed_override0_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 2275 #define sc_x1_speed_override0_actualSpeeds_dr_10G_DXGXS_SCR 36 2276 #define sc_x1_speed_override0_actualSpeeds_dr_12G_R2 37 2277 #define sc_x1_speed_override0_actualSpeeds_dr_10G_X2 38 2278 #define sc_x1_speed_override0_actualSpeeds_dr_40G_KR4 39 2279 #define sc_x1_speed_override0_actualSpeeds_dr_40G_CR4 40 2280 #define sc_x1_speed_override0_actualSpeeds_dr_100G_CR10 41 2281 #define sc_x1_speed_override0_actualSpeeds_dr_15p75G_DXGXS 44 2282 #define sc_x1_speed_override0_actualSpeeds_dr_20G_KR2 57 2283 #define sc_x1_speed_override0_actualSpeeds_dr_20G_CR2 58 2284 2285 /**************************************************************************** 2286 * Enums: sc_x1_speed_override0_actualSpeedsMisc1 2287 */ 2288 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_2500BRCM_X1 16 2289 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_5000BRCM_X4 17 2290 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_6000BRCM_X4 18 2291 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_10GHiGig_X4 19 2292 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_10GBASE_CX4 20 2293 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_12GHiGig_X4 21 2294 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 2295 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_13GHiGig_X4 23 2296 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_15GHiGig_X4 24 2297 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_16GHiGig_X4 25 2298 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_5000BRCM_X1 26 2299 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_6363BRCM_X1 27 2300 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_20GHiGig_X4 28 2301 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_21GHiGig_X4 29 2302 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 2303 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 2304 2305 /**************************************************************************** 2306 * Enums: sc_x1_speed_override0_IndLaneModes 2307 */ 2308 #define sc_x1_speed_override0_IndLaneModes_SWSDR_div2 0 2309 #define sc_x1_speed_override0_IndLaneModes_SWSDR_div1 1 2310 #define sc_x1_speed_override0_IndLaneModes_DWSDR_div2 2 2311 #define sc_x1_speed_override0_IndLaneModes_DWSDR_div1 3 2312 2313 /**************************************************************************** 2314 * Enums: sc_x1_speed_override0_prbsSelect 2315 */ 2316 #define sc_x1_speed_override0_prbsSelect_prbs7 0 2317 #define sc_x1_speed_override0_prbsSelect_prbs15 1 2318 #define sc_x1_speed_override0_prbsSelect_prbs23 2 2319 #define sc_x1_speed_override0_prbsSelect_prbs31 3 2320 2321 /**************************************************************************** 2322 * Enums: sc_x1_speed_override0_vcoDivider 2323 */ 2324 #define sc_x1_speed_override0_vcoDivider_div32 0 2325 #define sc_x1_speed_override0_vcoDivider_div36 1 2326 #define sc_x1_speed_override0_vcoDivider_div40 2 2327 #define sc_x1_speed_override0_vcoDivider_div42 3 2328 #define sc_x1_speed_override0_vcoDivider_div48 4 2329 #define sc_x1_speed_override0_vcoDivider_div50 5 2330 #define sc_x1_speed_override0_vcoDivider_div52 6 2331 #define sc_x1_speed_override0_vcoDivider_div54 7 2332 #define sc_x1_speed_override0_vcoDivider_div60 8 2333 #define sc_x1_speed_override0_vcoDivider_div64 9 2334 #define sc_x1_speed_override0_vcoDivider_div66 10 2335 #define sc_x1_speed_override0_vcoDivider_div68 11 2336 #define sc_x1_speed_override0_vcoDivider_div70 12 2337 #define sc_x1_speed_override0_vcoDivider_div80 13 2338 #define sc_x1_speed_override0_vcoDivider_div92 14 2339 #define sc_x1_speed_override0_vcoDivider_div100 15 2340 2341 /**************************************************************************** 2342 * Enums: sc_x1_speed_override0_refClkSelect 2343 */ 2344 #define sc_x1_speed_override0_refClkSelect_clk_25MHz 0 2345 #define sc_x1_speed_override0_refClkSelect_clk_100MHz 1 2346 #define sc_x1_speed_override0_refClkSelect_clk_125MHz 2 2347 #define sc_x1_speed_override0_refClkSelect_clk_156p25MHz 3 2348 #define sc_x1_speed_override0_refClkSelect_clk_187p5MHz 4 2349 #define sc_x1_speed_override0_refClkSelect_clk_161p25Mhz 5 2350 #define sc_x1_speed_override0_refClkSelect_clk_50Mhz 6 2351 #define sc_x1_speed_override0_refClkSelect_clk_106p25Mhz 7 2352 2353 /**************************************************************************** 2354 * Enums: sc_x1_speed_override0_aerMMDdevTypeSelect 2355 */ 2356 #define sc_x1_speed_override0_aerMMDdevTypeSelect_combo_core 0 2357 #define sc_x1_speed_override0_aerMMDdevTypeSelect_PMA_PMD 1 2358 #define sc_x1_speed_override0_aerMMDdevTypeSelect_PCS 3 2359 #define sc_x1_speed_override0_aerMMDdevTypeSelect_PHY 4 2360 #define sc_x1_speed_override0_aerMMDdevTypeSelect_DTE 5 2361 #define sc_x1_speed_override0_aerMMDdevTypeSelect_CL73_AN 7 2362 2363 /**************************************************************************** 2364 * Enums: sc_x1_speed_override0_aerMMDportSelect 2365 */ 2366 #define sc_x1_speed_override0_aerMMDportSelect_ln0 0 2367 #define sc_x1_speed_override0_aerMMDportSelect_ln1 1 2368 #define sc_x1_speed_override0_aerMMDportSelect_ln2 2 2369 #define sc_x1_speed_override0_aerMMDportSelect_ln3 3 2370 #define sc_x1_speed_override0_aerMMDportSelect_BCST_ln0_1_2_3 511 2371 #define sc_x1_speed_override0_aerMMDportSelect_BCST_ln0_1 512 2372 #define sc_x1_speed_override0_aerMMDportSelect_BCST_ln2_3 513 2373 2374 /**************************************************************************** 2375 * Enums: sc_x1_speed_override0_firmwareModeSelect 2376 */ 2377 #define sc_x1_speed_override0_firmwareModeSelect_DEFAULT 0 2378 #define sc_x1_speed_override0_firmwareModeSelect_SFP_OPT_LR 1 2379 #define sc_x1_speed_override0_firmwareModeSelect_SFP_DAC 2 2380 #define sc_x1_speed_override0_firmwareModeSelect_XLAUI 3 2381 #define sc_x1_speed_override0_firmwareModeSelect_LONG_CH_6G 4 2382 2383 /**************************************************************************** 2384 * Enums: sc_x1_speed_override0_tempIdxSelect 2385 */ 2386 #define sc_x1_speed_override0_tempIdxSelect_LTE__22p9C 15 2387 #define sc_x1_speed_override0_tempIdxSelect_LTE__12p6C 14 2388 #define sc_x1_speed_override0_tempIdxSelect_LTE__3p0C 13 2389 #define sc_x1_speed_override0_tempIdxSelect_LTE_6p7C 12 2390 #define sc_x1_speed_override0_tempIdxSelect_LTE_16p4C 11 2391 #define sc_x1_speed_override0_tempIdxSelect_LTE_26p6C 10 2392 #define sc_x1_speed_override0_tempIdxSelect_LTE_36p3C 9 2393 #define sc_x1_speed_override0_tempIdxSelect_LTE_46p0C 8 2394 #define sc_x1_speed_override0_tempIdxSelect_LTE_56p2C 7 2395 #define sc_x1_speed_override0_tempIdxSelect_LTE_65p9C 6 2396 #define sc_x1_speed_override0_tempIdxSelect_LTE_75p6C 5 2397 #define sc_x1_speed_override0_tempIdxSelect_LTE_85p3C 4 2398 #define sc_x1_speed_override0_tempIdxSelect_LTE_95p5C 3 2399 #define sc_x1_speed_override0_tempIdxSelect_LTE_105p2C 2 2400 #define sc_x1_speed_override0_tempIdxSelect_LTE_114p9C 1 2401 #define sc_x1_speed_override0_tempIdxSelect_LTE_125p1C 0 2402 2403 /**************************************************************************** 2404 * Enums: sc_x1_speed_override1_cl36TxEEEStates_l 2405 */ 2406 #define sc_x1_speed_override1_cl36TxEEEStates_l_TX_REFRESH 8 2407 #define sc_x1_speed_override1_cl36TxEEEStates_l_TX_QUIET 4 2408 #define sc_x1_speed_override1_cl36TxEEEStates_l_TX_SLEEP 2 2409 #define sc_x1_speed_override1_cl36TxEEEStates_l_TX_ACTIVE 1 2410 2411 /**************************************************************************** 2412 * Enums: sc_x1_speed_override1_cl36TxEEEStates_c 2413 */ 2414 #define sc_x1_speed_override1_cl36TxEEEStates_c_TX_REFRESH 3 2415 #define sc_x1_speed_override1_cl36TxEEEStates_c_TX_QUIET 2 2416 #define sc_x1_speed_override1_cl36TxEEEStates_c_TX_SLEEP 1 2417 #define sc_x1_speed_override1_cl36TxEEEStates_c_TX_ACTIVE 0 2418 2419 /**************************************************************************** 2420 * Enums: sc_x1_speed_override1_cl49TxEEEStates_l 2421 */ 2422 #define sc_x1_speed_override1_cl49TxEEEStates_l_SCR_RESET_2 64 2423 #define sc_x1_speed_override1_cl49TxEEEStates_l_SCR_RESET_1 32 2424 #define sc_x1_speed_override1_cl49TxEEEStates_l_TX_WAKE 16 2425 #define sc_x1_speed_override1_cl49TxEEEStates_l_TX_REFRESH 8 2426 #define sc_x1_speed_override1_cl49TxEEEStates_l_TX_QUIET 4 2427 #define sc_x1_speed_override1_cl49TxEEEStates_l_TX_SLEEP 2 2428 #define sc_x1_speed_override1_cl49TxEEEStates_l_TX_ACTIVE 1 2429 2430 /**************************************************************************** 2431 * Enums: sc_x1_speed_override1_cl49TxEEEStates_c 2432 */ 2433 #define sc_x1_speed_override1_cl49TxEEEStates_c_SCR_RESET_2 6 2434 #define sc_x1_speed_override1_cl49TxEEEStates_c_SCR_RESET_1 5 2435 #define sc_x1_speed_override1_cl49TxEEEStates_c_TX_WAKE 4 2436 #define sc_x1_speed_override1_cl49TxEEEStates_c_TX_REFRESH 3 2437 #define sc_x1_speed_override1_cl49TxEEEStates_c_TX_QUIET 2 2438 #define sc_x1_speed_override1_cl49TxEEEStates_c_TX_SLEEP 1 2439 #define sc_x1_speed_override1_cl49TxEEEStates_c_TX_ACTIVE 0 2440 2441 /**************************************************************************** 2442 * Enums: sc_x1_speed_override1_cl36RxEEEStates_l 2443 */ 2444 #define sc_x1_speed_override1_cl36RxEEEStates_l_RX_LINK_FAIL 32 2445 #define sc_x1_speed_override1_cl36RxEEEStates_l_RX_WTF 16 2446 #define sc_x1_speed_override1_cl36RxEEEStates_l_RX_WAKE 8 2447 #define sc_x1_speed_override1_cl36RxEEEStates_l_RX_QUIET 4 2448 #define sc_x1_speed_override1_cl36RxEEEStates_l_RX_SLEEP 2 2449 #define sc_x1_speed_override1_cl36RxEEEStates_l_RX_ACTIVE 1 2450 2451 /**************************************************************************** 2452 * Enums: sc_x1_speed_override1_cl36RxEEEStates_c 2453 */ 2454 #define sc_x1_speed_override1_cl36RxEEEStates_c_RX_LINK_FAIL 5 2455 #define sc_x1_speed_override1_cl36RxEEEStates_c_RX_WTF 4 2456 #define sc_x1_speed_override1_cl36RxEEEStates_c_RX_WAKE 3 2457 #define sc_x1_speed_override1_cl36RxEEEStates_c_RX_QUIET 2 2458 #define sc_x1_speed_override1_cl36RxEEEStates_c_RX_SLEEP 1 2459 #define sc_x1_speed_override1_cl36RxEEEStates_c_RX_ACTIVE 0 2460 2461 /**************************************************************************** 2462 * Enums: sc_x1_speed_override1_cl49RxEEEStates_l 2463 */ 2464 #define sc_x1_speed_override1_cl49RxEEEStates_l_RX_LINK_FAIL 32 2465 #define sc_x1_speed_override1_cl49RxEEEStates_l_RX_WTF 16 2466 #define sc_x1_speed_override1_cl49RxEEEStates_l_RX_WAKE 8 2467 #define sc_x1_speed_override1_cl49RxEEEStates_l_RX_QUIET 4 2468 #define sc_x1_speed_override1_cl49RxEEEStates_l_RX_SLEEP 2 2469 #define sc_x1_speed_override1_cl49RxEEEStates_l_RX_ACTIVE 1 2470 2471 /**************************************************************************** 2472 * Enums: sc_x1_speed_override1_cl49RxEEEStates_c 2473 */ 2474 #define sc_x1_speed_override1_cl49RxEEEStates_c_RX_LINK_FAIL 5 2475 #define sc_x1_speed_override1_cl49RxEEEStates_c_RX_WTF 4 2476 #define sc_x1_speed_override1_cl49RxEEEStates_c_RX_WAKE 3 2477 #define sc_x1_speed_override1_cl49RxEEEStates_c_RX_QUIET 2 2478 #define sc_x1_speed_override1_cl49RxEEEStates_c_RX_SLEEP 1 2479 #define sc_x1_speed_override1_cl49RxEEEStates_c_RX_ACTIVE 0 2480 2481 /**************************************************************************** 2482 * Enums: sc_x1_speed_override1_cl48TxEEEStates_l 2483 */ 2484 #define sc_x1_speed_override1_cl48TxEEEStates_l_TX_REFRESH 8 2485 #define sc_x1_speed_override1_cl48TxEEEStates_l_TX_QUIET 4 2486 #define sc_x1_speed_override1_cl48TxEEEStates_l_TX_SLEEP 2 2487 #define sc_x1_speed_override1_cl48TxEEEStates_l_TX_ACTIVE 1 2488 2489 /**************************************************************************** 2490 * Enums: sc_x1_speed_override1_cl48TxEEEStates_c 2491 */ 2492 #define sc_x1_speed_override1_cl48TxEEEStates_c_TX_REFRESH 3 2493 #define sc_x1_speed_override1_cl48TxEEEStates_c_TX_QUIET 2 2494 #define sc_x1_speed_override1_cl48TxEEEStates_c_TX_SLEEP 1 2495 #define sc_x1_speed_override1_cl48TxEEEStates_c_TX_ACTIVE 0 2496 2497 /**************************************************************************** 2498 * Enums: sc_x1_speed_override1_cl48RxEEEStates_l 2499 */ 2500 #define sc_x1_speed_override1_cl48RxEEEStates_l_RX_LINK_FAIL 32 2501 #define sc_x1_speed_override1_cl48RxEEEStates_l_RX_WAKE 16 2502 #define sc_x1_speed_override1_cl48RxEEEStates_l_RX_QUIET 8 2503 #define sc_x1_speed_override1_cl48RxEEEStates_l_RX_DEACT 4 2504 #define sc_x1_speed_override1_cl48RxEEEStates_l_RX_SLEEP 2 2505 #define sc_x1_speed_override1_cl48RxEEEStates_l_RX_ACTIVE 1 2506 2507 /**************************************************************************** 2508 * Enums: sc_x1_speed_override1_cl48RxEEEStates_c 2509 */ 2510 #define sc_x1_speed_override1_cl48RxEEEStates_c_RX_LINK_FAIL 5 2511 #define sc_x1_speed_override1_cl48RxEEEStates_c_RX_WAKE 4 2512 #define sc_x1_speed_override1_cl48RxEEEStates_c_RX_QUIET 3 2513 #define sc_x1_speed_override1_cl48RxEEEStates_c_RX_DEACT 2 2514 #define sc_x1_speed_override1_cl48RxEEEStates_c_RX_SLEEP 1 2515 #define sc_x1_speed_override1_cl48RxEEEStates_c_RX_ACTIVE 0 2516 2517 /**************************************************************************** 2518 * Enums: sc_x1_speed_override1_IQP_Options 2519 */ 2520 #define sc_x1_speed_override1_IQP_Options_i50uA 0 2521 #define sc_x1_speed_override1_IQP_Options_i100uA 1 2522 #define sc_x1_speed_override1_IQP_Options_i150uA 2 2523 #define sc_x1_speed_override1_IQP_Options_i200uA 3 2524 #define sc_x1_speed_override1_IQP_Options_i250uA 4 2525 #define sc_x1_speed_override1_IQP_Options_i300uA 5 2526 #define sc_x1_speed_override1_IQP_Options_i350uA 6 2527 #define sc_x1_speed_override1_IQP_Options_i400uA 7 2528 #define sc_x1_speed_override1_IQP_Options_i450uA 8 2529 #define sc_x1_speed_override1_IQP_Options_i500uA 9 2530 #define sc_x1_speed_override1_IQP_Options_i550uA 10 2531 #define sc_x1_speed_override1_IQP_Options_i600uA 11 2532 #define sc_x1_speed_override1_IQP_Options_i650uA 12 2533 #define sc_x1_speed_override1_IQP_Options_i700uA 13 2534 #define sc_x1_speed_override1_IQP_Options_i750uA 14 2535 #define sc_x1_speed_override1_IQP_Options_i800uA 15 2536 2537 /**************************************************************************** 2538 * Enums: sc_x1_speed_override1_IDriver_Options 2539 */ 2540 #define sc_x1_speed_override1_IDriver_Options_v680mV 0 2541 #define sc_x1_speed_override1_IDriver_Options_v730mV 1 2542 #define sc_x1_speed_override1_IDriver_Options_v780mV 2 2543 #define sc_x1_speed_override1_IDriver_Options_v830mV 3 2544 #define sc_x1_speed_override1_IDriver_Options_v880mV 4 2545 #define sc_x1_speed_override1_IDriver_Options_v930mV 5 2546 #define sc_x1_speed_override1_IDriver_Options_v980mV 6 2547 #define sc_x1_speed_override1_IDriver_Options_v1010mV 7 2548 #define sc_x1_speed_override1_IDriver_Options_v1040mV 8 2549 #define sc_x1_speed_override1_IDriver_Options_v1060mV 9 2550 #define sc_x1_speed_override1_IDriver_Options_v1070mV 10 2551 #define sc_x1_speed_override1_IDriver_Options_v1080mV 11 2552 #define sc_x1_speed_override1_IDriver_Options_v1085mV 12 2553 #define sc_x1_speed_override1_IDriver_Options_v1090mV 13 2554 #define sc_x1_speed_override1_IDriver_Options_v1095mV 14 2555 #define sc_x1_speed_override1_IDriver_Options_v1100mV 15 2556 2557 /**************************************************************************** 2558 * Enums: sc_x1_speed_override1_operationModes 2559 */ 2560 #define sc_x1_speed_override1_operationModes_XGXS 0 2561 #define sc_x1_speed_override1_operationModes_XGXG_nCC 1 2562 #define sc_x1_speed_override1_operationModes_Indlane_OS8 4 2563 #define sc_x1_speed_override1_operationModes_IndLane_OS5 5 2564 #define sc_x1_speed_override1_operationModes_PCI 7 2565 #define sc_x1_speed_override1_operationModes_XGXS_nLQ 8 2566 #define sc_x1_speed_override1_operationModes_XGXS_nLQnCC 9 2567 #define sc_x1_speed_override1_operationModes_PBypass 10 2568 #define sc_x1_speed_override1_operationModes_PBypass_nDSK 11 2569 #define sc_x1_speed_override1_operationModes_ComboCoreMode 12 2570 #define sc_x1_speed_override1_operationModes_Clocks_off 15 2571 2572 /**************************************************************************** 2573 * Enums: sc_x1_speed_override1_synce_enum 2574 */ 2575 #define sc_x1_speed_override1_synce_enum_SYNCE_NO_DIV 0 2576 #define sc_x1_speed_override1_synce_enum_SYNCE_DIV_7 1 2577 #define sc_x1_speed_override1_synce_enum_SYNCE_DIV_11 2 2578 2579 /**************************************************************************** 2580 * Enums: sc_x1_speed_override1_operationSpeeds 2581 */ 2582 #define sc_x1_speed_override1_operationSpeeds_SPEED_2p5G_X1_10p3125 56 2583 #define sc_x1_speed_override1_operationSpeeds_SPEED_1000M_10p3125 55 2584 #define sc_x1_speed_override1_operationSpeeds_SPEED_100M_10p3125 54 2585 #define sc_x1_speed_override1_operationSpeeds_SPEED_10M_10p3125 53 2586 #define sc_x1_speed_override1_operationSpeeds_SPEED_10p5G_X4 50 2587 #define sc_x1_speed_override1_operationSpeeds_SPEED_5G_KR1 49 2588 #define sc_x1_speed_override1_operationSpeeds_SPEED_127G_X12 39 2589 #define sc_x1_speed_override1_operationSpeeds_SPEED_120G_X12 38 2590 #define sc_x1_speed_override1_operationSpeeds_SPEED_107G_X10 37 2591 #define sc_x1_speed_override1_operationSpeeds_SPEED_100G_CR10 36 2592 #define sc_x1_speed_override1_operationSpeeds_SPEED_42G_X4 35 2593 #define sc_x1_speed_override1_operationSpeeds_SPEED_40G_CR4 34 2594 #define sc_x1_speed_override1_operationSpeeds_SPEED_40G_KR4 33 2595 #define sc_x1_speed_override1_operationSpeeds_SPEED_21G_X2 32 2596 #define sc_x1_speed_override1_operationSpeeds_SPEED_20G_CR2 31 2597 #define sc_x1_speed_override1_operationSpeeds_SPEED_20G_KR2 30 2598 #define sc_x1_speed_override1_operationSpeeds_SPEED_10p6_X1 29 2599 #define sc_x1_speed_override1_operationSpeeds_SPEED_10G_KR1 28 2600 #define sc_x1_speed_override1_operationSpeeds_SPEED_40G_X4 27 2601 #define sc_x1_speed_override1_operationSpeeds_SPEED_20G_X2 26 2602 #define sc_x1_speed_override1_operationSpeeds_SPEED_20G_CX2 25 2603 #define sc_x1_speed_override1_operationSpeeds_SPEED_31p5G_KR4 24 2604 #define sc_x1_speed_override1_operationSpeeds_SPEED_31p5G_X4 23 2605 #define sc_x1_speed_override1_operationSpeeds_SPEED_15p75G_X2 22 2606 #define sc_x1_speed_override1_operationSpeeds_SPEED_25p45G_X4 21 2607 #define sc_x1_speed_override1_operationSpeeds_SPEED_12p7G_X2 20 2608 #define sc_x1_speed_override1_operationSpeeds_SPEED_21G_X4 19 2609 #define sc_x1_speed_override1_operationSpeeds_SPEED_10p5G_X2 18 2610 #define sc_x1_speed_override1_operationSpeeds_SPEED_20G_X4 17 2611 #define sc_x1_speed_override1_operationSpeeds_SPEED_10G_X2 16 2612 #define sc_x1_speed_override1_operationSpeeds_SPEED_10G_CX2 15 2613 #define sc_x1_speed_override1_operationSpeeds_SPEED_20G_CX4 14 2614 #define sc_x1_speed_override1_operationSpeeds_SPEED_16G_X4 13 2615 #define sc_x1_speed_override1_operationSpeeds_SPEED_15G_X4 12 2616 #define sc_x1_speed_override1_operationSpeeds_SPEED_13G_X4 11 2617 #define sc_x1_speed_override1_operationSpeeds_SPEED_10G_X4 10 2618 #define sc_x1_speed_override1_operationSpeeds_SPEED_10G_KX4 9 2619 #define sc_x1_speed_override1_operationSpeeds_SPEED_10G_CX4 8 2620 #define sc_x1_speed_override1_operationSpeeds_SPEED_5G_X1 7 2621 #define sc_x1_speed_override1_operationSpeeds_SPEED_2p5G_X1 6 2622 #define sc_x1_speed_override1_operationSpeeds_SPEED_1G_KX1 5 2623 #define sc_x1_speed_override1_operationSpeeds_SPEED_1G_CX1 4 2624 #define sc_x1_speed_override1_operationSpeeds_SPEED_1000M 3 2625 #define sc_x1_speed_override1_operationSpeeds_SPEED_100M 2 2626 #define sc_x1_speed_override1_operationSpeeds_SPEED_10M 1 2627 2628 /**************************************************************************** 2629 * Enums: sc_x1_speed_override1_actualSpeeds 2630 */ 2631 #define sc_x1_speed_override1_actualSpeeds_dr_10M 0 2632 #define sc_x1_speed_override1_actualSpeeds_dr_100M 1 2633 #define sc_x1_speed_override1_actualSpeeds_dr_1G 2 2634 #define sc_x1_speed_override1_actualSpeeds_dr_2p5G 3 2635 #define sc_x1_speed_override1_actualSpeeds_dr_5G_X4 4 2636 #define sc_x1_speed_override1_actualSpeeds_dr_6G_X4 5 2637 #define sc_x1_speed_override1_actualSpeeds_dr_10G_HiG 6 2638 #define sc_x1_speed_override1_actualSpeeds_dr_10G_CX4 7 2639 #define sc_x1_speed_override1_actualSpeeds_dr_12G_HiG 8 2640 #define sc_x1_speed_override1_actualSpeeds_dr_12p5G_X4 9 2641 #define sc_x1_speed_override1_actualSpeeds_dr_13G_X4 10 2642 #define sc_x1_speed_override1_actualSpeeds_dr_15G_X4 11 2643 #define sc_x1_speed_override1_actualSpeeds_dr_16G_X4 12 2644 #define sc_x1_speed_override1_actualSpeeds_dr_1G_KX 13 2645 #define sc_x1_speed_override1_actualSpeeds_dr_10G_KX4 14 2646 #define sc_x1_speed_override1_actualSpeeds_dr_10G_KR 15 2647 #define sc_x1_speed_override1_actualSpeeds_dr_5G 16 2648 #define sc_x1_speed_override1_actualSpeeds_dr_6p4G 17 2649 #define sc_x1_speed_override1_actualSpeeds_dr_20G_X4 18 2650 #define sc_x1_speed_override1_actualSpeeds_dr_21G_X4 19 2651 #define sc_x1_speed_override1_actualSpeeds_dr_25G_X4 20 2652 #define sc_x1_speed_override1_actualSpeeds_dr_10G_HiG_DXGXS 21 2653 #define sc_x1_speed_override1_actualSpeeds_dr_10G_DXGXS 22 2654 #define sc_x1_speed_override1_actualSpeeds_dr_10p5G_HiG_DXGXS 23 2655 #define sc_x1_speed_override1_actualSpeeds_dr_10p5G_DXGXS 24 2656 #define sc_x1_speed_override1_actualSpeeds_dr_12p773G_HiG_DXGXS 25 2657 #define sc_x1_speed_override1_actualSpeeds_dr_12p773G_DXGXS 26 2658 #define sc_x1_speed_override1_actualSpeeds_dr_10G_XFI 27 2659 #define sc_x1_speed_override1_actualSpeeds_dr_40G 28 2660 #define sc_x1_speed_override1_actualSpeeds_dr_20G_HiG_DXGXS 29 2661 #define sc_x1_speed_override1_actualSpeeds_dr_20G_DXGXS 30 2662 #define sc_x1_speed_override1_actualSpeeds_dr_10G_SFI 31 2663 #define sc_x1_speed_override1_actualSpeeds_dr_31p5G 32 2664 #define sc_x1_speed_override1_actualSpeeds_dr_32p7G 33 2665 #define sc_x1_speed_override1_actualSpeeds_dr_20G_SCR 34 2666 #define sc_x1_speed_override1_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 2667 #define sc_x1_speed_override1_actualSpeeds_dr_10G_DXGXS_SCR 36 2668 #define sc_x1_speed_override1_actualSpeeds_dr_12G_R2 37 2669 #define sc_x1_speed_override1_actualSpeeds_dr_10G_X2 38 2670 #define sc_x1_speed_override1_actualSpeeds_dr_40G_KR4 39 2671 #define sc_x1_speed_override1_actualSpeeds_dr_40G_CR4 40 2672 #define sc_x1_speed_override1_actualSpeeds_dr_100G_CR10 41 2673 #define sc_x1_speed_override1_actualSpeeds_dr_15p75G_DXGXS 44 2674 #define sc_x1_speed_override1_actualSpeeds_dr_20G_KR2 57 2675 #define sc_x1_speed_override1_actualSpeeds_dr_20G_CR2 58 2676 2677 /**************************************************************************** 2678 * Enums: sc_x1_speed_override1_actualSpeedsMisc1 2679 */ 2680 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_2500BRCM_X1 16 2681 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_5000BRCM_X4 17 2682 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_6000BRCM_X4 18 2683 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_10GHiGig_X4 19 2684 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_10GBASE_CX4 20 2685 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_12GHiGig_X4 21 2686 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 2687 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_13GHiGig_X4 23 2688 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_15GHiGig_X4 24 2689 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_16GHiGig_X4 25 2690 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_5000BRCM_X1 26 2691 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_6363BRCM_X1 27 2692 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_20GHiGig_X4 28 2693 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_21GHiGig_X4 29 2694 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 2695 #define sc_x1_speed_override1_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 2696 2697 /**************************************************************************** 2698 * Enums: sc_x1_speed_override1_IndLaneModes 2699 */ 2700 #define sc_x1_speed_override1_IndLaneModes_SWSDR_div2 0 2701 #define sc_x1_speed_override1_IndLaneModes_SWSDR_div1 1 2702 #define sc_x1_speed_override1_IndLaneModes_DWSDR_div2 2 2703 #define sc_x1_speed_override1_IndLaneModes_DWSDR_div1 3 2704 2705 /**************************************************************************** 2706 * Enums: sc_x1_speed_override1_prbsSelect 2707 */ 2708 #define sc_x1_speed_override1_prbsSelect_prbs7 0 2709 #define sc_x1_speed_override1_prbsSelect_prbs15 1 2710 #define sc_x1_speed_override1_prbsSelect_prbs23 2 2711 #define sc_x1_speed_override1_prbsSelect_prbs31 3 2712 2713 /**************************************************************************** 2714 * Enums: sc_x1_speed_override1_vcoDivider 2715 */ 2716 #define sc_x1_speed_override1_vcoDivider_div32 0 2717 #define sc_x1_speed_override1_vcoDivider_div36 1 2718 #define sc_x1_speed_override1_vcoDivider_div40 2 2719 #define sc_x1_speed_override1_vcoDivider_div42 3 2720 #define sc_x1_speed_override1_vcoDivider_div48 4 2721 #define sc_x1_speed_override1_vcoDivider_div50 5 2722 #define sc_x1_speed_override1_vcoDivider_div52 6 2723 #define sc_x1_speed_override1_vcoDivider_div54 7 2724 #define sc_x1_speed_override1_vcoDivider_div60 8 2725 #define sc_x1_speed_override1_vcoDivider_div64 9 2726 #define sc_x1_speed_override1_vcoDivider_div66 10 2727 #define sc_x1_speed_override1_vcoDivider_div68 11 2728 #define sc_x1_speed_override1_vcoDivider_div70 12 2729 #define sc_x1_speed_override1_vcoDivider_div80 13 2730 #define sc_x1_speed_override1_vcoDivider_div92 14 2731 #define sc_x1_speed_override1_vcoDivider_div100 15 2732 2733 /**************************************************************************** 2734 * Enums: sc_x1_speed_override1_refClkSelect 2735 */ 2736 #define sc_x1_speed_override1_refClkSelect_clk_25MHz 0 2737 #define sc_x1_speed_override1_refClkSelect_clk_100MHz 1 2738 #define sc_x1_speed_override1_refClkSelect_clk_125MHz 2 2739 #define sc_x1_speed_override1_refClkSelect_clk_156p25MHz 3 2740 #define sc_x1_speed_override1_refClkSelect_clk_187p5MHz 4 2741 #define sc_x1_speed_override1_refClkSelect_clk_161p25Mhz 5 2742 #define sc_x1_speed_override1_refClkSelect_clk_50Mhz 6 2743 #define sc_x1_speed_override1_refClkSelect_clk_106p25Mhz 7 2744 2745 /**************************************************************************** 2746 * Enums: sc_x1_speed_override1_aerMMDdevTypeSelect 2747 */ 2748 #define sc_x1_speed_override1_aerMMDdevTypeSelect_combo_core 0 2749 #define sc_x1_speed_override1_aerMMDdevTypeSelect_PMA_PMD 1 2750 #define sc_x1_speed_override1_aerMMDdevTypeSelect_PCS 3 2751 #define sc_x1_speed_override1_aerMMDdevTypeSelect_PHY 4 2752 #define sc_x1_speed_override1_aerMMDdevTypeSelect_DTE 5 2753 #define sc_x1_speed_override1_aerMMDdevTypeSelect_CL73_AN 7 2754 2755 /**************************************************************************** 2756 * Enums: sc_x1_speed_override1_aerMMDportSelect 2757 */ 2758 #define sc_x1_speed_override1_aerMMDportSelect_ln0 0 2759 #define sc_x1_speed_override1_aerMMDportSelect_ln1 1 2760 #define sc_x1_speed_override1_aerMMDportSelect_ln2 2 2761 #define sc_x1_speed_override1_aerMMDportSelect_ln3 3 2762 #define sc_x1_speed_override1_aerMMDportSelect_BCST_ln0_1_2_3 511 2763 #define sc_x1_speed_override1_aerMMDportSelect_BCST_ln0_1 512 2764 #define sc_x1_speed_override1_aerMMDportSelect_BCST_ln2_3 513 2765 2766 /**************************************************************************** 2767 * Enums: sc_x1_speed_override1_firmwareModeSelect 2768 */ 2769 #define sc_x1_speed_override1_firmwareModeSelect_DEFAULT 0 2770 #define sc_x1_speed_override1_firmwareModeSelect_SFP_OPT_LR 1 2771 #define sc_x1_speed_override1_firmwareModeSelect_SFP_DAC 2 2772 #define sc_x1_speed_override1_firmwareModeSelect_XLAUI 3 2773 #define sc_x1_speed_override1_firmwareModeSelect_LONG_CH_6G 4 2774 2775 /**************************************************************************** 2776 * Enums: sc_x1_speed_override1_tempIdxSelect 2777 */ 2778 #define sc_x1_speed_override1_tempIdxSelect_LTE__22p9C 15 2779 #define sc_x1_speed_override1_tempIdxSelect_LTE__12p6C 14 2780 #define sc_x1_speed_override1_tempIdxSelect_LTE__3p0C 13 2781 #define sc_x1_speed_override1_tempIdxSelect_LTE_6p7C 12 2782 #define sc_x1_speed_override1_tempIdxSelect_LTE_16p4C 11 2783 #define sc_x1_speed_override1_tempIdxSelect_LTE_26p6C 10 2784 #define sc_x1_speed_override1_tempIdxSelect_LTE_36p3C 9 2785 #define sc_x1_speed_override1_tempIdxSelect_LTE_46p0C 8 2786 #define sc_x1_speed_override1_tempIdxSelect_LTE_56p2C 7 2787 #define sc_x1_speed_override1_tempIdxSelect_LTE_65p9C 6 2788 #define sc_x1_speed_override1_tempIdxSelect_LTE_75p6C 5 2789 #define sc_x1_speed_override1_tempIdxSelect_LTE_85p3C 4 2790 #define sc_x1_speed_override1_tempIdxSelect_LTE_95p5C 3 2791 #define sc_x1_speed_override1_tempIdxSelect_LTE_105p2C 2 2792 #define sc_x1_speed_override1_tempIdxSelect_LTE_114p9C 1 2793 #define sc_x1_speed_override1_tempIdxSelect_LTE_125p1C 0 2794 2795 /**************************************************************************** 2796 * Enums: sc_x1_speed_override2_cl36TxEEEStates_l 2797 */ 2798 #define sc_x1_speed_override2_cl36TxEEEStates_l_TX_REFRESH 8 2799 #define sc_x1_speed_override2_cl36TxEEEStates_l_TX_QUIET 4 2800 #define sc_x1_speed_override2_cl36TxEEEStates_l_TX_SLEEP 2 2801 #define sc_x1_speed_override2_cl36TxEEEStates_l_TX_ACTIVE 1 2802 2803 /**************************************************************************** 2804 * Enums: sc_x1_speed_override2_cl36TxEEEStates_c 2805 */ 2806 #define sc_x1_speed_override2_cl36TxEEEStates_c_TX_REFRESH 3 2807 #define sc_x1_speed_override2_cl36TxEEEStates_c_TX_QUIET 2 2808 #define sc_x1_speed_override2_cl36TxEEEStates_c_TX_SLEEP 1 2809 #define sc_x1_speed_override2_cl36TxEEEStates_c_TX_ACTIVE 0 2810 2811 /**************************************************************************** 2812 * Enums: sc_x1_speed_override2_cl49TxEEEStates_l 2813 */ 2814 #define sc_x1_speed_override2_cl49TxEEEStates_l_SCR_RESET_2 64 2815 #define sc_x1_speed_override2_cl49TxEEEStates_l_SCR_RESET_1 32 2816 #define sc_x1_speed_override2_cl49TxEEEStates_l_TX_WAKE 16 2817 #define sc_x1_speed_override2_cl49TxEEEStates_l_TX_REFRESH 8 2818 #define sc_x1_speed_override2_cl49TxEEEStates_l_TX_QUIET 4 2819 #define sc_x1_speed_override2_cl49TxEEEStates_l_TX_SLEEP 2 2820 #define sc_x1_speed_override2_cl49TxEEEStates_l_TX_ACTIVE 1 2821 2822 /**************************************************************************** 2823 * Enums: sc_x1_speed_override2_cl49TxEEEStates_c 2824 */ 2825 #define sc_x1_speed_override2_cl49TxEEEStates_c_SCR_RESET_2 6 2826 #define sc_x1_speed_override2_cl49TxEEEStates_c_SCR_RESET_1 5 2827 #define sc_x1_speed_override2_cl49TxEEEStates_c_TX_WAKE 4 2828 #define sc_x1_speed_override2_cl49TxEEEStates_c_TX_REFRESH 3 2829 #define sc_x1_speed_override2_cl49TxEEEStates_c_TX_QUIET 2 2830 #define sc_x1_speed_override2_cl49TxEEEStates_c_TX_SLEEP 1 2831 #define sc_x1_speed_override2_cl49TxEEEStates_c_TX_ACTIVE 0 2832 2833 /**************************************************************************** 2834 * Enums: sc_x1_speed_override2_cl36RxEEEStates_l 2835 */ 2836 #define sc_x1_speed_override2_cl36RxEEEStates_l_RX_LINK_FAIL 32 2837 #define sc_x1_speed_override2_cl36RxEEEStates_l_RX_WTF 16 2838 #define sc_x1_speed_override2_cl36RxEEEStates_l_RX_WAKE 8 2839 #define sc_x1_speed_override2_cl36RxEEEStates_l_RX_QUIET 4 2840 #define sc_x1_speed_override2_cl36RxEEEStates_l_RX_SLEEP 2 2841 #define sc_x1_speed_override2_cl36RxEEEStates_l_RX_ACTIVE 1 2842 2843 /**************************************************************************** 2844 * Enums: sc_x1_speed_override2_cl36RxEEEStates_c 2845 */ 2846 #define sc_x1_speed_override2_cl36RxEEEStates_c_RX_LINK_FAIL 5 2847 #define sc_x1_speed_override2_cl36RxEEEStates_c_RX_WTF 4 2848 #define sc_x1_speed_override2_cl36RxEEEStates_c_RX_WAKE 3 2849 #define sc_x1_speed_override2_cl36RxEEEStates_c_RX_QUIET 2 2850 #define sc_x1_speed_override2_cl36RxEEEStates_c_RX_SLEEP 1 2851 #define sc_x1_speed_override2_cl36RxEEEStates_c_RX_ACTIVE 0 2852 2853 /**************************************************************************** 2854 * Enums: sc_x1_speed_override2_cl49RxEEEStates_l 2855 */ 2856 #define sc_x1_speed_override2_cl49RxEEEStates_l_RX_LINK_FAIL 32 2857 #define sc_x1_speed_override2_cl49RxEEEStates_l_RX_WTF 16 2858 #define sc_x1_speed_override2_cl49RxEEEStates_l_RX_WAKE 8 2859 #define sc_x1_speed_override2_cl49RxEEEStates_l_RX_QUIET 4 2860 #define sc_x1_speed_override2_cl49RxEEEStates_l_RX_SLEEP 2 2861 #define sc_x1_speed_override2_cl49RxEEEStates_l_RX_ACTIVE 1 2862 2863 /**************************************************************************** 2864 * Enums: sc_x1_speed_override2_cl49RxEEEStates_c 2865 */ 2866 #define sc_x1_speed_override2_cl49RxEEEStates_c_RX_LINK_FAIL 5 2867 #define sc_x1_speed_override2_cl49RxEEEStates_c_RX_WTF 4 2868 #define sc_x1_speed_override2_cl49RxEEEStates_c_RX_WAKE 3 2869 #define sc_x1_speed_override2_cl49RxEEEStates_c_RX_QUIET 2 2870 #define sc_x1_speed_override2_cl49RxEEEStates_c_RX_SLEEP 1 2871 #define sc_x1_speed_override2_cl49RxEEEStates_c_RX_ACTIVE 0 2872 2873 /**************************************************************************** 2874 * Enums: sc_x1_speed_override2_cl48TxEEEStates_l 2875 */ 2876 #define sc_x1_speed_override2_cl48TxEEEStates_l_TX_REFRESH 8 2877 #define sc_x1_speed_override2_cl48TxEEEStates_l_TX_QUIET 4 2878 #define sc_x1_speed_override2_cl48TxEEEStates_l_TX_SLEEP 2 2879 #define sc_x1_speed_override2_cl48TxEEEStates_l_TX_ACTIVE 1 2880 2881 /**************************************************************************** 2882 * Enums: sc_x1_speed_override2_cl48TxEEEStates_c 2883 */ 2884 #define sc_x1_speed_override2_cl48TxEEEStates_c_TX_REFRESH 3 2885 #define sc_x1_speed_override2_cl48TxEEEStates_c_TX_QUIET 2 2886 #define sc_x1_speed_override2_cl48TxEEEStates_c_TX_SLEEP 1 2887 #define sc_x1_speed_override2_cl48TxEEEStates_c_TX_ACTIVE 0 2888 2889 /**************************************************************************** 2890 * Enums: sc_x1_speed_override2_cl48RxEEEStates_l 2891 */ 2892 #define sc_x1_speed_override2_cl48RxEEEStates_l_RX_LINK_FAIL 32 2893 #define sc_x1_speed_override2_cl48RxEEEStates_l_RX_WAKE 16 2894 #define sc_x1_speed_override2_cl48RxEEEStates_l_RX_QUIET 8 2895 #define sc_x1_speed_override2_cl48RxEEEStates_l_RX_DEACT 4 2896 #define sc_x1_speed_override2_cl48RxEEEStates_l_RX_SLEEP 2 2897 #define sc_x1_speed_override2_cl48RxEEEStates_l_RX_ACTIVE 1 2898 2899 /**************************************************************************** 2900 * Enums: sc_x1_speed_override2_cl48RxEEEStates_c 2901 */ 2902 #define sc_x1_speed_override2_cl48RxEEEStates_c_RX_LINK_FAIL 5 2903 #define sc_x1_speed_override2_cl48RxEEEStates_c_RX_WAKE 4 2904 #define sc_x1_speed_override2_cl48RxEEEStates_c_RX_QUIET 3 2905 #define sc_x1_speed_override2_cl48RxEEEStates_c_RX_DEACT 2 2906 #define sc_x1_speed_override2_cl48RxEEEStates_c_RX_SLEEP 1 2907 #define sc_x1_speed_override2_cl48RxEEEStates_c_RX_ACTIVE 0 2908 2909 /**************************************************************************** 2910 * Enums: sc_x1_speed_override2_IQP_Options 2911 */ 2912 #define sc_x1_speed_override2_IQP_Options_i50uA 0 2913 #define sc_x1_speed_override2_IQP_Options_i100uA 1 2914 #define sc_x1_speed_override2_IQP_Options_i150uA 2 2915 #define sc_x1_speed_override2_IQP_Options_i200uA 3 2916 #define sc_x1_speed_override2_IQP_Options_i250uA 4 2917 #define sc_x1_speed_override2_IQP_Options_i300uA 5 2918 #define sc_x1_speed_override2_IQP_Options_i350uA 6 2919 #define sc_x1_speed_override2_IQP_Options_i400uA 7 2920 #define sc_x1_speed_override2_IQP_Options_i450uA 8 2921 #define sc_x1_speed_override2_IQP_Options_i500uA 9 2922 #define sc_x1_speed_override2_IQP_Options_i550uA 10 2923 #define sc_x1_speed_override2_IQP_Options_i600uA 11 2924 #define sc_x1_speed_override2_IQP_Options_i650uA 12 2925 #define sc_x1_speed_override2_IQP_Options_i700uA 13 2926 #define sc_x1_speed_override2_IQP_Options_i750uA 14 2927 #define sc_x1_speed_override2_IQP_Options_i800uA 15 2928 2929 /**************************************************************************** 2930 * Enums: sc_x1_speed_override2_IDriver_Options 2931 */ 2932 #define sc_x1_speed_override2_IDriver_Options_v680mV 0 2933 #define sc_x1_speed_override2_IDriver_Options_v730mV 1 2934 #define sc_x1_speed_override2_IDriver_Options_v780mV 2 2935 #define sc_x1_speed_override2_IDriver_Options_v830mV 3 2936 #define sc_x1_speed_override2_IDriver_Options_v880mV 4 2937 #define sc_x1_speed_override2_IDriver_Options_v930mV 5 2938 #define sc_x1_speed_override2_IDriver_Options_v980mV 6 2939 #define sc_x1_speed_override2_IDriver_Options_v1010mV 7 2940 #define sc_x1_speed_override2_IDriver_Options_v1040mV 8 2941 #define sc_x1_speed_override2_IDriver_Options_v1060mV 9 2942 #define sc_x1_speed_override2_IDriver_Options_v1070mV 10 2943 #define sc_x1_speed_override2_IDriver_Options_v1080mV 11 2944 #define sc_x1_speed_override2_IDriver_Options_v1085mV 12 2945 #define sc_x1_speed_override2_IDriver_Options_v1090mV 13 2946 #define sc_x1_speed_override2_IDriver_Options_v1095mV 14 2947 #define sc_x1_speed_override2_IDriver_Options_v1100mV 15 2948 2949 /**************************************************************************** 2950 * Enums: sc_x1_speed_override2_operationModes 2951 */ 2952 #define sc_x1_speed_override2_operationModes_XGXS 0 2953 #define sc_x1_speed_override2_operationModes_XGXG_nCC 1 2954 #define sc_x1_speed_override2_operationModes_Indlane_OS8 4 2955 #define sc_x1_speed_override2_operationModes_IndLane_OS5 5 2956 #define sc_x1_speed_override2_operationModes_PCI 7 2957 #define sc_x1_speed_override2_operationModes_XGXS_nLQ 8 2958 #define sc_x1_speed_override2_operationModes_XGXS_nLQnCC 9 2959 #define sc_x1_speed_override2_operationModes_PBypass 10 2960 #define sc_x1_speed_override2_operationModes_PBypass_nDSK 11 2961 #define sc_x1_speed_override2_operationModes_ComboCoreMode 12 2962 #define sc_x1_speed_override2_operationModes_Clocks_off 15 2963 2964 /**************************************************************************** 2965 * Enums: sc_x1_speed_override2_synce_enum 2966 */ 2967 #define sc_x1_speed_override2_synce_enum_SYNCE_NO_DIV 0 2968 #define sc_x1_speed_override2_synce_enum_SYNCE_DIV_7 1 2969 #define sc_x1_speed_override2_synce_enum_SYNCE_DIV_11 2 2970 2971 /**************************************************************************** 2972 * Enums: sc_x1_speed_override2_operationSpeeds 2973 */ 2974 #define sc_x1_speed_override2_operationSpeeds_SPEED_2p5G_X1_10p3125 56 2975 #define sc_x1_speed_override2_operationSpeeds_SPEED_1000M_10p3125 55 2976 #define sc_x1_speed_override2_operationSpeeds_SPEED_100M_10p3125 54 2977 #define sc_x1_speed_override2_operationSpeeds_SPEED_10M_10p3125 53 2978 #define sc_x1_speed_override2_operationSpeeds_SPEED_10p5G_X4 50 2979 #define sc_x1_speed_override2_operationSpeeds_SPEED_5G_KR1 49 2980 #define sc_x1_speed_override2_operationSpeeds_SPEED_127G_X12 39 2981 #define sc_x1_speed_override2_operationSpeeds_SPEED_120G_X12 38 2982 #define sc_x1_speed_override2_operationSpeeds_SPEED_107G_X10 37 2983 #define sc_x1_speed_override2_operationSpeeds_SPEED_100G_CR10 36 2984 #define sc_x1_speed_override2_operationSpeeds_SPEED_42G_X4 35 2985 #define sc_x1_speed_override2_operationSpeeds_SPEED_40G_CR4 34 2986 #define sc_x1_speed_override2_operationSpeeds_SPEED_40G_KR4 33 2987 #define sc_x1_speed_override2_operationSpeeds_SPEED_21G_X2 32 2988 #define sc_x1_speed_override2_operationSpeeds_SPEED_20G_CR2 31 2989 #define sc_x1_speed_override2_operationSpeeds_SPEED_20G_KR2 30 2990 #define sc_x1_speed_override2_operationSpeeds_SPEED_10p6_X1 29 2991 #define sc_x1_speed_override2_operationSpeeds_SPEED_10G_KR1 28 2992 #define sc_x1_speed_override2_operationSpeeds_SPEED_40G_X4 27 2993 #define sc_x1_speed_override2_operationSpeeds_SPEED_20G_X2 26 2994 #define sc_x1_speed_override2_operationSpeeds_SPEED_20G_CX2 25 2995 #define sc_x1_speed_override2_operationSpeeds_SPEED_31p5G_KR4 24 2996 #define sc_x1_speed_override2_operationSpeeds_SPEED_31p5G_X4 23 2997 #define sc_x1_speed_override2_operationSpeeds_SPEED_15p75G_X2 22 2998 #define sc_x1_speed_override2_operationSpeeds_SPEED_25p45G_X4 21 2999 #define sc_x1_speed_override2_operationSpeeds_SPEED_12p7G_X2 20 3000 #define sc_x1_speed_override2_operationSpeeds_SPEED_21G_X4 19 3001 #define sc_x1_speed_override2_operationSpeeds_SPEED_10p5G_X2 18 3002 #define sc_x1_speed_override2_operationSpeeds_SPEED_20G_X4 17 3003 #define sc_x1_speed_override2_operationSpeeds_SPEED_10G_X2 16 3004 #define sc_x1_speed_override2_operationSpeeds_SPEED_10G_CX2 15 3005 #define sc_x1_speed_override2_operationSpeeds_SPEED_20G_CX4 14 3006 #define sc_x1_speed_override2_operationSpeeds_SPEED_16G_X4 13 3007 #define sc_x1_speed_override2_operationSpeeds_SPEED_15G_X4 12 3008 #define sc_x1_speed_override2_operationSpeeds_SPEED_13G_X4 11 3009 #define sc_x1_speed_override2_operationSpeeds_SPEED_10G_X4 10 3010 #define sc_x1_speed_override2_operationSpeeds_SPEED_10G_KX4 9 3011 #define sc_x1_speed_override2_operationSpeeds_SPEED_10G_CX4 8 3012 #define sc_x1_speed_override2_operationSpeeds_SPEED_5G_X1 7 3013 #define sc_x1_speed_override2_operationSpeeds_SPEED_2p5G_X1 6 3014 #define sc_x1_speed_override2_operationSpeeds_SPEED_1G_KX1 5 3015 #define sc_x1_speed_override2_operationSpeeds_SPEED_1G_CX1 4 3016 #define sc_x1_speed_override2_operationSpeeds_SPEED_1000M 3 3017 #define sc_x1_speed_override2_operationSpeeds_SPEED_100M 2 3018 #define sc_x1_speed_override2_operationSpeeds_SPEED_10M 1 3019 3020 /**************************************************************************** 3021 * Enums: sc_x1_speed_override2_actualSpeeds 3022 */ 3023 #define sc_x1_speed_override2_actualSpeeds_dr_10M 0 3024 #define sc_x1_speed_override2_actualSpeeds_dr_100M 1 3025 #define sc_x1_speed_override2_actualSpeeds_dr_1G 2 3026 #define sc_x1_speed_override2_actualSpeeds_dr_2p5G 3 3027 #define sc_x1_speed_override2_actualSpeeds_dr_5G_X4 4 3028 #define sc_x1_speed_override2_actualSpeeds_dr_6G_X4 5 3029 #define sc_x1_speed_override2_actualSpeeds_dr_10G_HiG 6 3030 #define sc_x1_speed_override2_actualSpeeds_dr_10G_CX4 7 3031 #define sc_x1_speed_override2_actualSpeeds_dr_12G_HiG 8 3032 #define sc_x1_speed_override2_actualSpeeds_dr_12p5G_X4 9 3033 #define sc_x1_speed_override2_actualSpeeds_dr_13G_X4 10 3034 #define sc_x1_speed_override2_actualSpeeds_dr_15G_X4 11 3035 #define sc_x1_speed_override2_actualSpeeds_dr_16G_X4 12 3036 #define sc_x1_speed_override2_actualSpeeds_dr_1G_KX 13 3037 #define sc_x1_speed_override2_actualSpeeds_dr_10G_KX4 14 3038 #define sc_x1_speed_override2_actualSpeeds_dr_10G_KR 15 3039 #define sc_x1_speed_override2_actualSpeeds_dr_5G 16 3040 #define sc_x1_speed_override2_actualSpeeds_dr_6p4G 17 3041 #define sc_x1_speed_override2_actualSpeeds_dr_20G_X4 18 3042 #define sc_x1_speed_override2_actualSpeeds_dr_21G_X4 19 3043 #define sc_x1_speed_override2_actualSpeeds_dr_25G_X4 20 3044 #define sc_x1_speed_override2_actualSpeeds_dr_10G_HiG_DXGXS 21 3045 #define sc_x1_speed_override2_actualSpeeds_dr_10G_DXGXS 22 3046 #define sc_x1_speed_override2_actualSpeeds_dr_10p5G_HiG_DXGXS 23 3047 #define sc_x1_speed_override2_actualSpeeds_dr_10p5G_DXGXS 24 3048 #define sc_x1_speed_override2_actualSpeeds_dr_12p773G_HiG_DXGXS 25 3049 #define sc_x1_speed_override2_actualSpeeds_dr_12p773G_DXGXS 26 3050 #define sc_x1_speed_override2_actualSpeeds_dr_10G_XFI 27 3051 #define sc_x1_speed_override2_actualSpeeds_dr_40G 28 3052 #define sc_x1_speed_override2_actualSpeeds_dr_20G_HiG_DXGXS 29 3053 #define sc_x1_speed_override2_actualSpeeds_dr_20G_DXGXS 30 3054 #define sc_x1_speed_override2_actualSpeeds_dr_10G_SFI 31 3055 #define sc_x1_speed_override2_actualSpeeds_dr_31p5G 32 3056 #define sc_x1_speed_override2_actualSpeeds_dr_32p7G 33 3057 #define sc_x1_speed_override2_actualSpeeds_dr_20G_SCR 34 3058 #define sc_x1_speed_override2_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 3059 #define sc_x1_speed_override2_actualSpeeds_dr_10G_DXGXS_SCR 36 3060 #define sc_x1_speed_override2_actualSpeeds_dr_12G_R2 37 3061 #define sc_x1_speed_override2_actualSpeeds_dr_10G_X2 38 3062 #define sc_x1_speed_override2_actualSpeeds_dr_40G_KR4 39 3063 #define sc_x1_speed_override2_actualSpeeds_dr_40G_CR4 40 3064 #define sc_x1_speed_override2_actualSpeeds_dr_100G_CR10 41 3065 #define sc_x1_speed_override2_actualSpeeds_dr_15p75G_DXGXS 44 3066 #define sc_x1_speed_override2_actualSpeeds_dr_20G_KR2 57 3067 #define sc_x1_speed_override2_actualSpeeds_dr_20G_CR2 58 3068 3069 /**************************************************************************** 3070 * Enums: sc_x1_speed_override2_actualSpeedsMisc1 3071 */ 3072 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_2500BRCM_X1 16 3073 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_5000BRCM_X4 17 3074 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_6000BRCM_X4 18 3075 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_10GHiGig_X4 19 3076 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_10GBASE_CX4 20 3077 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_12GHiGig_X4 21 3078 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 3079 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_13GHiGig_X4 23 3080 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_15GHiGig_X4 24 3081 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_16GHiGig_X4 25 3082 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_5000BRCM_X1 26 3083 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_6363BRCM_X1 27 3084 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_20GHiGig_X4 28 3085 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_21GHiGig_X4 29 3086 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 3087 #define sc_x1_speed_override2_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 3088 3089 /**************************************************************************** 3090 * Enums: sc_x1_speed_override2_IndLaneModes 3091 */ 3092 #define sc_x1_speed_override2_IndLaneModes_SWSDR_div2 0 3093 #define sc_x1_speed_override2_IndLaneModes_SWSDR_div1 1 3094 #define sc_x1_speed_override2_IndLaneModes_DWSDR_div2 2 3095 #define sc_x1_speed_override2_IndLaneModes_DWSDR_div1 3 3096 3097 /**************************************************************************** 3098 * Enums: sc_x1_speed_override2_prbsSelect 3099 */ 3100 #define sc_x1_speed_override2_prbsSelect_prbs7 0 3101 #define sc_x1_speed_override2_prbsSelect_prbs15 1 3102 #define sc_x1_speed_override2_prbsSelect_prbs23 2 3103 #define sc_x1_speed_override2_prbsSelect_prbs31 3 3104 3105 /**************************************************************************** 3106 * Enums: sc_x1_speed_override2_vcoDivider 3107 */ 3108 #define sc_x1_speed_override2_vcoDivider_div32 0 3109 #define sc_x1_speed_override2_vcoDivider_div36 1 3110 #define sc_x1_speed_override2_vcoDivider_div40 2 3111 #define sc_x1_speed_override2_vcoDivider_div42 3 3112 #define sc_x1_speed_override2_vcoDivider_div48 4 3113 #define sc_x1_speed_override2_vcoDivider_div50 5 3114 #define sc_x1_speed_override2_vcoDivider_div52 6 3115 #define sc_x1_speed_override2_vcoDivider_div54 7 3116 #define sc_x1_speed_override2_vcoDivider_div60 8 3117 #define sc_x1_speed_override2_vcoDivider_div64 9 3118 #define sc_x1_speed_override2_vcoDivider_div66 10 3119 #define sc_x1_speed_override2_vcoDivider_div68 11 3120 #define sc_x1_speed_override2_vcoDivider_div70 12 3121 #define sc_x1_speed_override2_vcoDivider_div80 13 3122 #define sc_x1_speed_override2_vcoDivider_div92 14 3123 #define sc_x1_speed_override2_vcoDivider_div100 15 3124 3125 /**************************************************************************** 3126 * Enums: sc_x1_speed_override2_refClkSelect 3127 */ 3128 #define sc_x1_speed_override2_refClkSelect_clk_25MHz 0 3129 #define sc_x1_speed_override2_refClkSelect_clk_100MHz 1 3130 #define sc_x1_speed_override2_refClkSelect_clk_125MHz 2 3131 #define sc_x1_speed_override2_refClkSelect_clk_156p25MHz 3 3132 #define sc_x1_speed_override2_refClkSelect_clk_187p5MHz 4 3133 #define sc_x1_speed_override2_refClkSelect_clk_161p25Mhz 5 3134 #define sc_x1_speed_override2_refClkSelect_clk_50Mhz 6 3135 #define sc_x1_speed_override2_refClkSelect_clk_106p25Mhz 7 3136 3137 /**************************************************************************** 3138 * Enums: sc_x1_speed_override2_aerMMDdevTypeSelect 3139 */ 3140 #define sc_x1_speed_override2_aerMMDdevTypeSelect_combo_core 0 3141 #define sc_x1_speed_override2_aerMMDdevTypeSelect_PMA_PMD 1 3142 #define sc_x1_speed_override2_aerMMDdevTypeSelect_PCS 3 3143 #define sc_x1_speed_override2_aerMMDdevTypeSelect_PHY 4 3144 #define sc_x1_speed_override2_aerMMDdevTypeSelect_DTE 5 3145 #define sc_x1_speed_override2_aerMMDdevTypeSelect_CL73_AN 7 3146 3147 /**************************************************************************** 3148 * Enums: sc_x1_speed_override2_aerMMDportSelect 3149 */ 3150 #define sc_x1_speed_override2_aerMMDportSelect_ln0 0 3151 #define sc_x1_speed_override2_aerMMDportSelect_ln1 1 3152 #define sc_x1_speed_override2_aerMMDportSelect_ln2 2 3153 #define sc_x1_speed_override2_aerMMDportSelect_ln3 3 3154 #define sc_x1_speed_override2_aerMMDportSelect_BCST_ln0_1_2_3 511 3155 #define sc_x1_speed_override2_aerMMDportSelect_BCST_ln0_1 512 3156 #define sc_x1_speed_override2_aerMMDportSelect_BCST_ln2_3 513 3157 3158 /**************************************************************************** 3159 * Enums: sc_x1_speed_override2_firmwareModeSelect 3160 */ 3161 #define sc_x1_speed_override2_firmwareModeSelect_DEFAULT 0 3162 #define sc_x1_speed_override2_firmwareModeSelect_SFP_OPT_LR 1 3163 #define sc_x1_speed_override2_firmwareModeSelect_SFP_DAC 2 3164 #define sc_x1_speed_override2_firmwareModeSelect_XLAUI 3 3165 #define sc_x1_speed_override2_firmwareModeSelect_LONG_CH_6G 4 3166 3167 /**************************************************************************** 3168 * Enums: sc_x1_speed_override2_tempIdxSelect 3169 */ 3170 #define sc_x1_speed_override2_tempIdxSelect_LTE__22p9C 15 3171 #define sc_x1_speed_override2_tempIdxSelect_LTE__12p6C 14 3172 #define sc_x1_speed_override2_tempIdxSelect_LTE__3p0C 13 3173 #define sc_x1_speed_override2_tempIdxSelect_LTE_6p7C 12 3174 #define sc_x1_speed_override2_tempIdxSelect_LTE_16p4C 11 3175 #define sc_x1_speed_override2_tempIdxSelect_LTE_26p6C 10 3176 #define sc_x1_speed_override2_tempIdxSelect_LTE_36p3C 9 3177 #define sc_x1_speed_override2_tempIdxSelect_LTE_46p0C 8 3178 #define sc_x1_speed_override2_tempIdxSelect_LTE_56p2C 7 3179 #define sc_x1_speed_override2_tempIdxSelect_LTE_65p9C 6 3180 #define sc_x1_speed_override2_tempIdxSelect_LTE_75p6C 5 3181 #define sc_x1_speed_override2_tempIdxSelect_LTE_85p3C 4 3182 #define sc_x1_speed_override2_tempIdxSelect_LTE_95p5C 3 3183 #define sc_x1_speed_override2_tempIdxSelect_LTE_105p2C 2 3184 #define sc_x1_speed_override2_tempIdxSelect_LTE_114p9C 1 3185 #define sc_x1_speed_override2_tempIdxSelect_LTE_125p1C 0 3186 3187 /**************************************************************************** 3188 * Enums: sc_x1_speed_override3_cl36TxEEEStates_l 3189 */ 3190 #define sc_x1_speed_override3_cl36TxEEEStates_l_TX_REFRESH 8 3191 #define sc_x1_speed_override3_cl36TxEEEStates_l_TX_QUIET 4 3192 #define sc_x1_speed_override3_cl36TxEEEStates_l_TX_SLEEP 2 3193 #define sc_x1_speed_override3_cl36TxEEEStates_l_TX_ACTIVE 1 3194 3195 /**************************************************************************** 3196 * Enums: sc_x1_speed_override3_cl36TxEEEStates_c 3197 */ 3198 #define sc_x1_speed_override3_cl36TxEEEStates_c_TX_REFRESH 3 3199 #define sc_x1_speed_override3_cl36TxEEEStates_c_TX_QUIET 2 3200 #define sc_x1_speed_override3_cl36TxEEEStates_c_TX_SLEEP 1 3201 #define sc_x1_speed_override3_cl36TxEEEStates_c_TX_ACTIVE 0 3202 3203 /**************************************************************************** 3204 * Enums: sc_x1_speed_override3_cl49TxEEEStates_l 3205 */ 3206 #define sc_x1_speed_override3_cl49TxEEEStates_l_SCR_RESET_2 64 3207 #define sc_x1_speed_override3_cl49TxEEEStates_l_SCR_RESET_1 32 3208 #define sc_x1_speed_override3_cl49TxEEEStates_l_TX_WAKE 16 3209 #define sc_x1_speed_override3_cl49TxEEEStates_l_TX_REFRESH 8 3210 #define sc_x1_speed_override3_cl49TxEEEStates_l_TX_QUIET 4 3211 #define sc_x1_speed_override3_cl49TxEEEStates_l_TX_SLEEP 2 3212 #define sc_x1_speed_override3_cl49TxEEEStates_l_TX_ACTIVE 1 3213 3214 /**************************************************************************** 3215 * Enums: sc_x1_speed_override3_cl49TxEEEStates_c 3216 */ 3217 #define sc_x1_speed_override3_cl49TxEEEStates_c_SCR_RESET_2 6 3218 #define sc_x1_speed_override3_cl49TxEEEStates_c_SCR_RESET_1 5 3219 #define sc_x1_speed_override3_cl49TxEEEStates_c_TX_WAKE 4 3220 #define sc_x1_speed_override3_cl49TxEEEStates_c_TX_REFRESH 3 3221 #define sc_x1_speed_override3_cl49TxEEEStates_c_TX_QUIET 2 3222 #define sc_x1_speed_override3_cl49TxEEEStates_c_TX_SLEEP 1 3223 #define sc_x1_speed_override3_cl49TxEEEStates_c_TX_ACTIVE 0 3224 3225 /**************************************************************************** 3226 * Enums: sc_x1_speed_override3_cl36RxEEEStates_l 3227 */ 3228 #define sc_x1_speed_override3_cl36RxEEEStates_l_RX_LINK_FAIL 32 3229 #define sc_x1_speed_override3_cl36RxEEEStates_l_RX_WTF 16 3230 #define sc_x1_speed_override3_cl36RxEEEStates_l_RX_WAKE 8 3231 #define sc_x1_speed_override3_cl36RxEEEStates_l_RX_QUIET 4 3232 #define sc_x1_speed_override3_cl36RxEEEStates_l_RX_SLEEP 2 3233 #define sc_x1_speed_override3_cl36RxEEEStates_l_RX_ACTIVE 1 3234 3235 /**************************************************************************** 3236 * Enums: sc_x1_speed_override3_cl36RxEEEStates_c 3237 */ 3238 #define sc_x1_speed_override3_cl36RxEEEStates_c_RX_LINK_FAIL 5 3239 #define sc_x1_speed_override3_cl36RxEEEStates_c_RX_WTF 4 3240 #define sc_x1_speed_override3_cl36RxEEEStates_c_RX_WAKE 3 3241 #define sc_x1_speed_override3_cl36RxEEEStates_c_RX_QUIET 2 3242 #define sc_x1_speed_override3_cl36RxEEEStates_c_RX_SLEEP 1 3243 #define sc_x1_speed_override3_cl36RxEEEStates_c_RX_ACTIVE 0 3244 3245 /**************************************************************************** 3246 * Enums: sc_x1_speed_override3_cl49RxEEEStates_l 3247 */ 3248 #define sc_x1_speed_override3_cl49RxEEEStates_l_RX_LINK_FAIL 32 3249 #define sc_x1_speed_override3_cl49RxEEEStates_l_RX_WTF 16 3250 #define sc_x1_speed_override3_cl49RxEEEStates_l_RX_WAKE 8 3251 #define sc_x1_speed_override3_cl49RxEEEStates_l_RX_QUIET 4 3252 #define sc_x1_speed_override3_cl49RxEEEStates_l_RX_SLEEP 2 3253 #define sc_x1_speed_override3_cl49RxEEEStates_l_RX_ACTIVE 1 3254 3255 /**************************************************************************** 3256 * Enums: sc_x1_speed_override3_cl49RxEEEStates_c 3257 */ 3258 #define sc_x1_speed_override3_cl49RxEEEStates_c_RX_LINK_FAIL 5 3259 #define sc_x1_speed_override3_cl49RxEEEStates_c_RX_WTF 4 3260 #define sc_x1_speed_override3_cl49RxEEEStates_c_RX_WAKE 3 3261 #define sc_x1_speed_override3_cl49RxEEEStates_c_RX_QUIET 2 3262 #define sc_x1_speed_override3_cl49RxEEEStates_c_RX_SLEEP 1 3263 #define sc_x1_speed_override3_cl49RxEEEStates_c_RX_ACTIVE 0 3264 3265 /**************************************************************************** 3266 * Enums: sc_x1_speed_override3_cl48TxEEEStates_l 3267 */ 3268 #define sc_x1_speed_override3_cl48TxEEEStates_l_TX_REFRESH 8 3269 #define sc_x1_speed_override3_cl48TxEEEStates_l_TX_QUIET 4 3270 #define sc_x1_speed_override3_cl48TxEEEStates_l_TX_SLEEP 2 3271 #define sc_x1_speed_override3_cl48TxEEEStates_l_TX_ACTIVE 1 3272 3273 /**************************************************************************** 3274 * Enums: sc_x1_speed_override3_cl48TxEEEStates_c 3275 */ 3276 #define sc_x1_speed_override3_cl48TxEEEStates_c_TX_REFRESH 3 3277 #define sc_x1_speed_override3_cl48TxEEEStates_c_TX_QUIET 2 3278 #define sc_x1_speed_override3_cl48TxEEEStates_c_TX_SLEEP 1 3279 #define sc_x1_speed_override3_cl48TxEEEStates_c_TX_ACTIVE 0 3280 3281 /**************************************************************************** 3282 * Enums: sc_x1_speed_override3_cl48RxEEEStates_l 3283 */ 3284 #define sc_x1_speed_override3_cl48RxEEEStates_l_RX_LINK_FAIL 32 3285 #define sc_x1_speed_override3_cl48RxEEEStates_l_RX_WAKE 16 3286 #define sc_x1_speed_override3_cl48RxEEEStates_l_RX_QUIET 8 3287 #define sc_x1_speed_override3_cl48RxEEEStates_l_RX_DEACT 4 3288 #define sc_x1_speed_override3_cl48RxEEEStates_l_RX_SLEEP 2 3289 #define sc_x1_speed_override3_cl48RxEEEStates_l_RX_ACTIVE 1 3290 3291 /**************************************************************************** 3292 * Enums: sc_x1_speed_override3_cl48RxEEEStates_c 3293 */ 3294 #define sc_x1_speed_override3_cl48RxEEEStates_c_RX_LINK_FAIL 5 3295 #define sc_x1_speed_override3_cl48RxEEEStates_c_RX_WAKE 4 3296 #define sc_x1_speed_override3_cl48RxEEEStates_c_RX_QUIET 3 3297 #define sc_x1_speed_override3_cl48RxEEEStates_c_RX_DEACT 2 3298 #define sc_x1_speed_override3_cl48RxEEEStates_c_RX_SLEEP 1 3299 #define sc_x1_speed_override3_cl48RxEEEStates_c_RX_ACTIVE 0 3300 3301 /**************************************************************************** 3302 * Enums: sc_x1_speed_override3_IQP_Options 3303 */ 3304 #define sc_x1_speed_override3_IQP_Options_i50uA 0 3305 #define sc_x1_speed_override3_IQP_Options_i100uA 1 3306 #define sc_x1_speed_override3_IQP_Options_i150uA 2 3307 #define sc_x1_speed_override3_IQP_Options_i200uA 3 3308 #define sc_x1_speed_override3_IQP_Options_i250uA 4 3309 #define sc_x1_speed_override3_IQP_Options_i300uA 5 3310 #define sc_x1_speed_override3_IQP_Options_i350uA 6 3311 #define sc_x1_speed_override3_IQP_Options_i400uA 7 3312 #define sc_x1_speed_override3_IQP_Options_i450uA 8 3313 #define sc_x1_speed_override3_IQP_Options_i500uA 9 3314 #define sc_x1_speed_override3_IQP_Options_i550uA 10 3315 #define sc_x1_speed_override3_IQP_Options_i600uA 11 3316 #define sc_x1_speed_override3_IQP_Options_i650uA 12 3317 #define sc_x1_speed_override3_IQP_Options_i700uA 13 3318 #define sc_x1_speed_override3_IQP_Options_i750uA 14 3319 #define sc_x1_speed_override3_IQP_Options_i800uA 15 3320 3321 /**************************************************************************** 3322 * Enums: sc_x1_speed_override3_IDriver_Options 3323 */ 3324 #define sc_x1_speed_override3_IDriver_Options_v680mV 0 3325 #define sc_x1_speed_override3_IDriver_Options_v730mV 1 3326 #define sc_x1_speed_override3_IDriver_Options_v780mV 2 3327 #define sc_x1_speed_override3_IDriver_Options_v830mV 3 3328 #define sc_x1_speed_override3_IDriver_Options_v880mV 4 3329 #define sc_x1_speed_override3_IDriver_Options_v930mV 5 3330 #define sc_x1_speed_override3_IDriver_Options_v980mV 6 3331 #define sc_x1_speed_override3_IDriver_Options_v1010mV 7 3332 #define sc_x1_speed_override3_IDriver_Options_v1040mV 8 3333 #define sc_x1_speed_override3_IDriver_Options_v1060mV 9 3334 #define sc_x1_speed_override3_IDriver_Options_v1070mV 10 3335 #define sc_x1_speed_override3_IDriver_Options_v1080mV 11 3336 #define sc_x1_speed_override3_IDriver_Options_v1085mV 12 3337 #define sc_x1_speed_override3_IDriver_Options_v1090mV 13 3338 #define sc_x1_speed_override3_IDriver_Options_v1095mV 14 3339 #define sc_x1_speed_override3_IDriver_Options_v1100mV 15 3340 3341 /**************************************************************************** 3342 * Enums: sc_x1_speed_override3_operationModes 3343 */ 3344 #define sc_x1_speed_override3_operationModes_XGXS 0 3345 #define sc_x1_speed_override3_operationModes_XGXG_nCC 1 3346 #define sc_x1_speed_override3_operationModes_Indlane_OS8 4 3347 #define sc_x1_speed_override3_operationModes_IndLane_OS5 5 3348 #define sc_x1_speed_override3_operationModes_PCI 7 3349 #define sc_x1_speed_override3_operationModes_XGXS_nLQ 8 3350 #define sc_x1_speed_override3_operationModes_XGXS_nLQnCC 9 3351 #define sc_x1_speed_override3_operationModes_PBypass 10 3352 #define sc_x1_speed_override3_operationModes_PBypass_nDSK 11 3353 #define sc_x1_speed_override3_operationModes_ComboCoreMode 12 3354 #define sc_x1_speed_override3_operationModes_Clocks_off 15 3355 3356 /**************************************************************************** 3357 * Enums: sc_x1_speed_override3_synce_enum 3358 */ 3359 #define sc_x1_speed_override3_synce_enum_SYNCE_NO_DIV 0 3360 #define sc_x1_speed_override3_synce_enum_SYNCE_DIV_7 1 3361 #define sc_x1_speed_override3_synce_enum_SYNCE_DIV_11 2 3362 3363 /**************************************************************************** 3364 * Enums: sc_x1_speed_override3_operationSpeeds 3365 */ 3366 #define sc_x1_speed_override3_operationSpeeds_SPEED_2p5G_X1_10p3125 56 3367 #define sc_x1_speed_override3_operationSpeeds_SPEED_1000M_10p3125 55 3368 #define sc_x1_speed_override3_operationSpeeds_SPEED_100M_10p3125 54 3369 #define sc_x1_speed_override3_operationSpeeds_SPEED_10M_10p3125 53 3370 #define sc_x1_speed_override3_operationSpeeds_SPEED_10p5G_X4 50 3371 #define sc_x1_speed_override3_operationSpeeds_SPEED_5G_KR1 49 3372 #define sc_x1_speed_override3_operationSpeeds_SPEED_127G_X12 39 3373 #define sc_x1_speed_override3_operationSpeeds_SPEED_120G_X12 38 3374 #define sc_x1_speed_override3_operationSpeeds_SPEED_107G_X10 37 3375 #define sc_x1_speed_override3_operationSpeeds_SPEED_100G_CR10 36 3376 #define sc_x1_speed_override3_operationSpeeds_SPEED_42G_X4 35 3377 #define sc_x1_speed_override3_operationSpeeds_SPEED_40G_CR4 34 3378 #define sc_x1_speed_override3_operationSpeeds_SPEED_40G_KR4 33 3379 #define sc_x1_speed_override3_operationSpeeds_SPEED_21G_X2 32 3380 #define sc_x1_speed_override3_operationSpeeds_SPEED_20G_CR2 31 3381 #define sc_x1_speed_override3_operationSpeeds_SPEED_20G_KR2 30 3382 #define sc_x1_speed_override3_operationSpeeds_SPEED_10p6_X1 29 3383 #define sc_x1_speed_override3_operationSpeeds_SPEED_10G_KR1 28 3384 #define sc_x1_speed_override3_operationSpeeds_SPEED_40G_X4 27 3385 #define sc_x1_speed_override3_operationSpeeds_SPEED_20G_X2 26 3386 #define sc_x1_speed_override3_operationSpeeds_SPEED_20G_CX2 25 3387 #define sc_x1_speed_override3_operationSpeeds_SPEED_31p5G_KR4 24 3388 #define sc_x1_speed_override3_operationSpeeds_SPEED_31p5G_X4 23 3389 #define sc_x1_speed_override3_operationSpeeds_SPEED_15p75G_X2 22 3390 #define sc_x1_speed_override3_operationSpeeds_SPEED_25p45G_X4 21 3391 #define sc_x1_speed_override3_operationSpeeds_SPEED_12p7G_X2 20 3392 #define sc_x1_speed_override3_operationSpeeds_SPEED_21G_X4 19 3393 #define sc_x1_speed_override3_operationSpeeds_SPEED_10p5G_X2 18 3394 #define sc_x1_speed_override3_operationSpeeds_SPEED_20G_X4 17 3395 #define sc_x1_speed_override3_operationSpeeds_SPEED_10G_X2 16 3396 #define sc_x1_speed_override3_operationSpeeds_SPEED_10G_CX2 15 3397 #define sc_x1_speed_override3_operationSpeeds_SPEED_20G_CX4 14 3398 #define sc_x1_speed_override3_operationSpeeds_SPEED_16G_X4 13 3399 #define sc_x1_speed_override3_operationSpeeds_SPEED_15G_X4 12 3400 #define sc_x1_speed_override3_operationSpeeds_SPEED_13G_X4 11 3401 #define sc_x1_speed_override3_operationSpeeds_SPEED_10G_X4 10 3402 #define sc_x1_speed_override3_operationSpeeds_SPEED_10G_KX4 9 3403 #define sc_x1_speed_override3_operationSpeeds_SPEED_10G_CX4 8 3404 #define sc_x1_speed_override3_operationSpeeds_SPEED_5G_X1 7 3405 #define sc_x1_speed_override3_operationSpeeds_SPEED_2p5G_X1 6 3406 #define sc_x1_speed_override3_operationSpeeds_SPEED_1G_KX1 5 3407 #define sc_x1_speed_override3_operationSpeeds_SPEED_1G_CX1 4 3408 #define sc_x1_speed_override3_operationSpeeds_SPEED_1000M 3 3409 #define sc_x1_speed_override3_operationSpeeds_SPEED_100M 2 3410 #define sc_x1_speed_override3_operationSpeeds_SPEED_10M 1 3411 3412 /**************************************************************************** 3413 * Enums: sc_x1_speed_override3_actualSpeeds 3414 */ 3415 #define sc_x1_speed_override3_actualSpeeds_dr_10M 0 3416 #define sc_x1_speed_override3_actualSpeeds_dr_100M 1 3417 #define sc_x1_speed_override3_actualSpeeds_dr_1G 2 3418 #define sc_x1_speed_override3_actualSpeeds_dr_2p5G 3 3419 #define sc_x1_speed_override3_actualSpeeds_dr_5G_X4 4 3420 #define sc_x1_speed_override3_actualSpeeds_dr_6G_X4 5 3421 #define sc_x1_speed_override3_actualSpeeds_dr_10G_HiG 6 3422 #define sc_x1_speed_override3_actualSpeeds_dr_10G_CX4 7 3423 #define sc_x1_speed_override3_actualSpeeds_dr_12G_HiG 8 3424 #define sc_x1_speed_override3_actualSpeeds_dr_12p5G_X4 9 3425 #define sc_x1_speed_override3_actualSpeeds_dr_13G_X4 10 3426 #define sc_x1_speed_override3_actualSpeeds_dr_15G_X4 11 3427 #define sc_x1_speed_override3_actualSpeeds_dr_16G_X4 12 3428 #define sc_x1_speed_override3_actualSpeeds_dr_1G_KX 13 3429 #define sc_x1_speed_override3_actualSpeeds_dr_10G_KX4 14 3430 #define sc_x1_speed_override3_actualSpeeds_dr_10G_KR 15 3431 #define sc_x1_speed_override3_actualSpeeds_dr_5G 16 3432 #define sc_x1_speed_override3_actualSpeeds_dr_6p4G 17 3433 #define sc_x1_speed_override3_actualSpeeds_dr_20G_X4 18 3434 #define sc_x1_speed_override3_actualSpeeds_dr_21G_X4 19 3435 #define sc_x1_speed_override3_actualSpeeds_dr_25G_X4 20 3436 #define sc_x1_speed_override3_actualSpeeds_dr_10G_HiG_DXGXS 21 3437 #define sc_x1_speed_override3_actualSpeeds_dr_10G_DXGXS 22 3438 #define sc_x1_speed_override3_actualSpeeds_dr_10p5G_HiG_DXGXS 23 3439 #define sc_x1_speed_override3_actualSpeeds_dr_10p5G_DXGXS 24 3440 #define sc_x1_speed_override3_actualSpeeds_dr_12p773G_HiG_DXGXS 25 3441 #define sc_x1_speed_override3_actualSpeeds_dr_12p773G_DXGXS 26 3442 #define sc_x1_speed_override3_actualSpeeds_dr_10G_XFI 27 3443 #define sc_x1_speed_override3_actualSpeeds_dr_40G 28 3444 #define sc_x1_speed_override3_actualSpeeds_dr_20G_HiG_DXGXS 29 3445 #define sc_x1_speed_override3_actualSpeeds_dr_20G_DXGXS 30 3446 #define sc_x1_speed_override3_actualSpeeds_dr_10G_SFI 31 3447 #define sc_x1_speed_override3_actualSpeeds_dr_31p5G 32 3448 #define sc_x1_speed_override3_actualSpeeds_dr_32p7G 33 3449 #define sc_x1_speed_override3_actualSpeeds_dr_20G_SCR 34 3450 #define sc_x1_speed_override3_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 3451 #define sc_x1_speed_override3_actualSpeeds_dr_10G_DXGXS_SCR 36 3452 #define sc_x1_speed_override3_actualSpeeds_dr_12G_R2 37 3453 #define sc_x1_speed_override3_actualSpeeds_dr_10G_X2 38 3454 #define sc_x1_speed_override3_actualSpeeds_dr_40G_KR4 39 3455 #define sc_x1_speed_override3_actualSpeeds_dr_40G_CR4 40 3456 #define sc_x1_speed_override3_actualSpeeds_dr_100G_CR10 41 3457 #define sc_x1_speed_override3_actualSpeeds_dr_15p75G_DXGXS 44 3458 #define sc_x1_speed_override3_actualSpeeds_dr_20G_KR2 57 3459 #define sc_x1_speed_override3_actualSpeeds_dr_20G_CR2 58 3460 3461 /**************************************************************************** 3462 * Enums: sc_x1_speed_override3_actualSpeedsMisc1 3463 */ 3464 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_2500BRCM_X1 16 3465 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_5000BRCM_X4 17 3466 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_6000BRCM_X4 18 3467 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_10GHiGig_X4 19 3468 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_10GBASE_CX4 20 3469 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_12GHiGig_X4 21 3470 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 3471 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_13GHiGig_X4 23 3472 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_15GHiGig_X4 24 3473 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_16GHiGig_X4 25 3474 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_5000BRCM_X1 26 3475 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_6363BRCM_X1 27 3476 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_20GHiGig_X4 28 3477 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_21GHiGig_X4 29 3478 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 3479 #define sc_x1_speed_override3_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 3480 3481 /**************************************************************************** 3482 * Enums: sc_x1_speed_override3_IndLaneModes 3483 */ 3484 #define sc_x1_speed_override3_IndLaneModes_SWSDR_div2 0 3485 #define sc_x1_speed_override3_IndLaneModes_SWSDR_div1 1 3486 #define sc_x1_speed_override3_IndLaneModes_DWSDR_div2 2 3487 #define sc_x1_speed_override3_IndLaneModes_DWSDR_div1 3 3488 3489 /**************************************************************************** 3490 * Enums: sc_x1_speed_override3_prbsSelect 3491 */ 3492 #define sc_x1_speed_override3_prbsSelect_prbs7 0 3493 #define sc_x1_speed_override3_prbsSelect_prbs15 1 3494 #define sc_x1_speed_override3_prbsSelect_prbs23 2 3495 #define sc_x1_speed_override3_prbsSelect_prbs31 3 3496 3497 /**************************************************************************** 3498 * Enums: sc_x1_speed_override3_vcoDivider 3499 */ 3500 #define sc_x1_speed_override3_vcoDivider_div32 0 3501 #define sc_x1_speed_override3_vcoDivider_div36 1 3502 #define sc_x1_speed_override3_vcoDivider_div40 2 3503 #define sc_x1_speed_override3_vcoDivider_div42 3 3504 #define sc_x1_speed_override3_vcoDivider_div48 4 3505 #define sc_x1_speed_override3_vcoDivider_div50 5 3506 #define sc_x1_speed_override3_vcoDivider_div52 6 3507 #define sc_x1_speed_override3_vcoDivider_div54 7 3508 #define sc_x1_speed_override3_vcoDivider_div60 8 3509 #define sc_x1_speed_override3_vcoDivider_div64 9 3510 #define sc_x1_speed_override3_vcoDivider_div66 10 3511 #define sc_x1_speed_override3_vcoDivider_div68 11 3512 #define sc_x1_speed_override3_vcoDivider_div70 12 3513 #define sc_x1_speed_override3_vcoDivider_div80 13 3514 #define sc_x1_speed_override3_vcoDivider_div92 14 3515 #define sc_x1_speed_override3_vcoDivider_div100 15 3516 3517 /**************************************************************************** 3518 * Enums: sc_x1_speed_override3_refClkSelect 3519 */ 3520 #define sc_x1_speed_override3_refClkSelect_clk_25MHz 0 3521 #define sc_x1_speed_override3_refClkSelect_clk_100MHz 1 3522 #define sc_x1_speed_override3_refClkSelect_clk_125MHz 2 3523 #define sc_x1_speed_override3_refClkSelect_clk_156p25MHz 3 3524 #define sc_x1_speed_override3_refClkSelect_clk_187p5MHz 4 3525 #define sc_x1_speed_override3_refClkSelect_clk_161p25Mhz 5 3526 #define sc_x1_speed_override3_refClkSelect_clk_50Mhz 6 3527 #define sc_x1_speed_override3_refClkSelect_clk_106p25Mhz 7 3528 3529 /**************************************************************************** 3530 * Enums: sc_x1_speed_override3_aerMMDdevTypeSelect 3531 */ 3532 #define sc_x1_speed_override3_aerMMDdevTypeSelect_combo_core 0 3533 #define sc_x1_speed_override3_aerMMDdevTypeSelect_PMA_PMD 1 3534 #define sc_x1_speed_override3_aerMMDdevTypeSelect_PCS 3 3535 #define sc_x1_speed_override3_aerMMDdevTypeSelect_PHY 4 3536 #define sc_x1_speed_override3_aerMMDdevTypeSelect_DTE 5 3537 #define sc_x1_speed_override3_aerMMDdevTypeSelect_CL73_AN 7 3538 3539 /**************************************************************************** 3540 * Enums: sc_x1_speed_override3_aerMMDportSelect 3541 */ 3542 #define sc_x1_speed_override3_aerMMDportSelect_ln0 0 3543 #define sc_x1_speed_override3_aerMMDportSelect_ln1 1 3544 #define sc_x1_speed_override3_aerMMDportSelect_ln2 2 3545 #define sc_x1_speed_override3_aerMMDportSelect_ln3 3 3546 #define sc_x1_speed_override3_aerMMDportSelect_BCST_ln0_1_2_3 511 3547 #define sc_x1_speed_override3_aerMMDportSelect_BCST_ln0_1 512 3548 #define sc_x1_speed_override3_aerMMDportSelect_BCST_ln2_3 513 3549 3550 /**************************************************************************** 3551 * Enums: sc_x1_speed_override3_firmwareModeSelect 3552 */ 3553 #define sc_x1_speed_override3_firmwareModeSelect_DEFAULT 0 3554 #define sc_x1_speed_override3_firmwareModeSelect_SFP_OPT_LR 1 3555 #define sc_x1_speed_override3_firmwareModeSelect_SFP_DAC 2 3556 #define sc_x1_speed_override3_firmwareModeSelect_XLAUI 3 3557 #define sc_x1_speed_override3_firmwareModeSelect_LONG_CH_6G 4 3558 3559 /**************************************************************************** 3560 * Enums: sc_x1_speed_override3_tempIdxSelect 3561 */ 3562 #define sc_x1_speed_override3_tempIdxSelect_LTE__22p9C 15 3563 #define sc_x1_speed_override3_tempIdxSelect_LTE__12p6C 14 3564 #define sc_x1_speed_override3_tempIdxSelect_LTE__3p0C 13 3565 #define sc_x1_speed_override3_tempIdxSelect_LTE_6p7C 12 3566 #define sc_x1_speed_override3_tempIdxSelect_LTE_16p4C 11 3567 #define sc_x1_speed_override3_tempIdxSelect_LTE_26p6C 10 3568 #define sc_x1_speed_override3_tempIdxSelect_LTE_36p3C 9 3569 #define sc_x1_speed_override3_tempIdxSelect_LTE_46p0C 8 3570 #define sc_x1_speed_override3_tempIdxSelect_LTE_56p2C 7 3571 #define sc_x1_speed_override3_tempIdxSelect_LTE_65p9C 6 3572 #define sc_x1_speed_override3_tempIdxSelect_LTE_75p6C 5 3573 #define sc_x1_speed_override3_tempIdxSelect_LTE_85p3C 4 3574 #define sc_x1_speed_override3_tempIdxSelect_LTE_95p5C 3 3575 #define sc_x1_speed_override3_tempIdxSelect_LTE_105p2C 2 3576 #define sc_x1_speed_override3_tempIdxSelect_LTE_114p9C 1 3577 #define sc_x1_speed_override3_tempIdxSelect_LTE_125p1C 0 3578 3579 /**************************************************************************** 3580 * Enums: sc_x4_control_cl36TxEEEStates_l 3581 */ 3582 #define sc_x4_control_cl36TxEEEStates_l_TX_REFRESH 8 3583 #define sc_x4_control_cl36TxEEEStates_l_TX_QUIET 4 3584 #define sc_x4_control_cl36TxEEEStates_l_TX_SLEEP 2 3585 #define sc_x4_control_cl36TxEEEStates_l_TX_ACTIVE 1 3586 3587 /**************************************************************************** 3588 * Enums: sc_x4_control_cl36TxEEEStates_c 3589 */ 3590 #define sc_x4_control_cl36TxEEEStates_c_TX_REFRESH 3 3591 #define sc_x4_control_cl36TxEEEStates_c_TX_QUIET 2 3592 #define sc_x4_control_cl36TxEEEStates_c_TX_SLEEP 1 3593 #define sc_x4_control_cl36TxEEEStates_c_TX_ACTIVE 0 3594 3595 /**************************************************************************** 3596 * Enums: sc_x4_control_cl49TxEEEStates_l 3597 */ 3598 #define sc_x4_control_cl49TxEEEStates_l_SCR_RESET_2 64 3599 #define sc_x4_control_cl49TxEEEStates_l_SCR_RESET_1 32 3600 #define sc_x4_control_cl49TxEEEStates_l_TX_WAKE 16 3601 #define sc_x4_control_cl49TxEEEStates_l_TX_REFRESH 8 3602 #define sc_x4_control_cl49TxEEEStates_l_TX_QUIET 4 3603 #define sc_x4_control_cl49TxEEEStates_l_TX_SLEEP 2 3604 #define sc_x4_control_cl49TxEEEStates_l_TX_ACTIVE 1 3605 3606 /**************************************************************************** 3607 * Enums: sc_x4_control_cl49TxEEEStates_c 3608 */ 3609 #define sc_x4_control_cl49TxEEEStates_c_SCR_RESET_2 6 3610 #define sc_x4_control_cl49TxEEEStates_c_SCR_RESET_1 5 3611 #define sc_x4_control_cl49TxEEEStates_c_TX_WAKE 4 3612 #define sc_x4_control_cl49TxEEEStates_c_TX_REFRESH 3 3613 #define sc_x4_control_cl49TxEEEStates_c_TX_QUIET 2 3614 #define sc_x4_control_cl49TxEEEStates_c_TX_SLEEP 1 3615 #define sc_x4_control_cl49TxEEEStates_c_TX_ACTIVE 0 3616 3617 /**************************************************************************** 3618 * Enums: sc_x4_control_cl36RxEEEStates_l 3619 */ 3620 #define sc_x4_control_cl36RxEEEStates_l_RX_LINK_FAIL 32 3621 #define sc_x4_control_cl36RxEEEStates_l_RX_WTF 16 3622 #define sc_x4_control_cl36RxEEEStates_l_RX_WAKE 8 3623 #define sc_x4_control_cl36RxEEEStates_l_RX_QUIET 4 3624 #define sc_x4_control_cl36RxEEEStates_l_RX_SLEEP 2 3625 #define sc_x4_control_cl36RxEEEStates_l_RX_ACTIVE 1 3626 3627 /**************************************************************************** 3628 * Enums: sc_x4_control_cl36RxEEEStates_c 3629 */ 3630 #define sc_x4_control_cl36RxEEEStates_c_RX_LINK_FAIL 5 3631 #define sc_x4_control_cl36RxEEEStates_c_RX_WTF 4 3632 #define sc_x4_control_cl36RxEEEStates_c_RX_WAKE 3 3633 #define sc_x4_control_cl36RxEEEStates_c_RX_QUIET 2 3634 #define sc_x4_control_cl36RxEEEStates_c_RX_SLEEP 1 3635 #define sc_x4_control_cl36RxEEEStates_c_RX_ACTIVE 0 3636 3637 /**************************************************************************** 3638 * Enums: sc_x4_control_cl49RxEEEStates_l 3639 */ 3640 #define sc_x4_control_cl49RxEEEStates_l_RX_LINK_FAIL 32 3641 #define sc_x4_control_cl49RxEEEStates_l_RX_WTF 16 3642 #define sc_x4_control_cl49RxEEEStates_l_RX_WAKE 8 3643 #define sc_x4_control_cl49RxEEEStates_l_RX_QUIET 4 3644 #define sc_x4_control_cl49RxEEEStates_l_RX_SLEEP 2 3645 #define sc_x4_control_cl49RxEEEStates_l_RX_ACTIVE 1 3646 3647 /**************************************************************************** 3648 * Enums: sc_x4_control_cl49RxEEEStates_c 3649 */ 3650 #define sc_x4_control_cl49RxEEEStates_c_RX_LINK_FAIL 5 3651 #define sc_x4_control_cl49RxEEEStates_c_RX_WTF 4 3652 #define sc_x4_control_cl49RxEEEStates_c_RX_WAKE 3 3653 #define sc_x4_control_cl49RxEEEStates_c_RX_QUIET 2 3654 #define sc_x4_control_cl49RxEEEStates_c_RX_SLEEP 1 3655 #define sc_x4_control_cl49RxEEEStates_c_RX_ACTIVE 0 3656 3657 /**************************************************************************** 3658 * Enums: sc_x4_control_cl48TxEEEStates_l 3659 */ 3660 #define sc_x4_control_cl48TxEEEStates_l_TX_REFRESH 8 3661 #define sc_x4_control_cl48TxEEEStates_l_TX_QUIET 4 3662 #define sc_x4_control_cl48TxEEEStates_l_TX_SLEEP 2 3663 #define sc_x4_control_cl48TxEEEStates_l_TX_ACTIVE 1 3664 3665 /**************************************************************************** 3666 * Enums: sc_x4_control_cl48TxEEEStates_c 3667 */ 3668 #define sc_x4_control_cl48TxEEEStates_c_TX_REFRESH 3 3669 #define sc_x4_control_cl48TxEEEStates_c_TX_QUIET 2 3670 #define sc_x4_control_cl48TxEEEStates_c_TX_SLEEP 1 3671 #define sc_x4_control_cl48TxEEEStates_c_TX_ACTIVE 0 3672 3673 /**************************************************************************** 3674 * Enums: sc_x4_control_cl48RxEEEStates_l 3675 */ 3676 #define sc_x4_control_cl48RxEEEStates_l_RX_LINK_FAIL 32 3677 #define sc_x4_control_cl48RxEEEStates_l_RX_WAKE 16 3678 #define sc_x4_control_cl48RxEEEStates_l_RX_QUIET 8 3679 #define sc_x4_control_cl48RxEEEStates_l_RX_DEACT 4 3680 #define sc_x4_control_cl48RxEEEStates_l_RX_SLEEP 2 3681 #define sc_x4_control_cl48RxEEEStates_l_RX_ACTIVE 1 3682 3683 /**************************************************************************** 3684 * Enums: sc_x4_control_cl48RxEEEStates_c 3685 */ 3686 #define sc_x4_control_cl48RxEEEStates_c_RX_LINK_FAIL 5 3687 #define sc_x4_control_cl48RxEEEStates_c_RX_WAKE 4 3688 #define sc_x4_control_cl48RxEEEStates_c_RX_QUIET 3 3689 #define sc_x4_control_cl48RxEEEStates_c_RX_DEACT 2 3690 #define sc_x4_control_cl48RxEEEStates_c_RX_SLEEP 1 3691 #define sc_x4_control_cl48RxEEEStates_c_RX_ACTIVE 0 3692 3693 /**************************************************************************** 3694 * Enums: sc_x4_control_IQP_Options 3695 */ 3696 #define sc_x4_control_IQP_Options_i50uA 0 3697 #define sc_x4_control_IQP_Options_i100uA 1 3698 #define sc_x4_control_IQP_Options_i150uA 2 3699 #define sc_x4_control_IQP_Options_i200uA 3 3700 #define sc_x4_control_IQP_Options_i250uA 4 3701 #define sc_x4_control_IQP_Options_i300uA 5 3702 #define sc_x4_control_IQP_Options_i350uA 6 3703 #define sc_x4_control_IQP_Options_i400uA 7 3704 #define sc_x4_control_IQP_Options_i450uA 8 3705 #define sc_x4_control_IQP_Options_i500uA 9 3706 #define sc_x4_control_IQP_Options_i550uA 10 3707 #define sc_x4_control_IQP_Options_i600uA 11 3708 #define sc_x4_control_IQP_Options_i650uA 12 3709 #define sc_x4_control_IQP_Options_i700uA 13 3710 #define sc_x4_control_IQP_Options_i750uA 14 3711 #define sc_x4_control_IQP_Options_i800uA 15 3712 3713 /**************************************************************************** 3714 * Enums: sc_x4_control_IDriver_Options 3715 */ 3716 #define sc_x4_control_IDriver_Options_v680mV 0 3717 #define sc_x4_control_IDriver_Options_v730mV 1 3718 #define sc_x4_control_IDriver_Options_v780mV 2 3719 #define sc_x4_control_IDriver_Options_v830mV 3 3720 #define sc_x4_control_IDriver_Options_v880mV 4 3721 #define sc_x4_control_IDriver_Options_v930mV 5 3722 #define sc_x4_control_IDriver_Options_v980mV 6 3723 #define sc_x4_control_IDriver_Options_v1010mV 7 3724 #define sc_x4_control_IDriver_Options_v1040mV 8 3725 #define sc_x4_control_IDriver_Options_v1060mV 9 3726 #define sc_x4_control_IDriver_Options_v1070mV 10 3727 #define sc_x4_control_IDriver_Options_v1080mV 11 3728 #define sc_x4_control_IDriver_Options_v1085mV 12 3729 #define sc_x4_control_IDriver_Options_v1090mV 13 3730 #define sc_x4_control_IDriver_Options_v1095mV 14 3731 #define sc_x4_control_IDriver_Options_v1100mV 15 3732 3733 /**************************************************************************** 3734 * Enums: sc_x4_control_operationModes 3735 */ 3736 #define sc_x4_control_operationModes_XGXS 0 3737 #define sc_x4_control_operationModes_XGXG_nCC 1 3738 #define sc_x4_control_operationModes_Indlane_OS8 4 3739 #define sc_x4_control_operationModes_IndLane_OS5 5 3740 #define sc_x4_control_operationModes_PCI 7 3741 #define sc_x4_control_operationModes_XGXS_nLQ 8 3742 #define sc_x4_control_operationModes_XGXS_nLQnCC 9 3743 #define sc_x4_control_operationModes_PBypass 10 3744 #define sc_x4_control_operationModes_PBypass_nDSK 11 3745 #define sc_x4_control_operationModes_ComboCoreMode 12 3746 #define sc_x4_control_operationModes_Clocks_off 15 3747 3748 /**************************************************************************** 3749 * Enums: sc_x4_control_synce_enum 3750 */ 3751 #define sc_x4_control_synce_enum_SYNCE_NO_DIV 0 3752 #define sc_x4_control_synce_enum_SYNCE_DIV_7 1 3753 #define sc_x4_control_synce_enum_SYNCE_DIV_11 2 3754 3755 /**************************************************************************** 3756 * Enums: sc_x4_control_operationSpeeds 3757 */ 3758 #define sc_x4_control_operationSpeeds_SPEED_2p5G_X1_10p3125 56 3759 #define sc_x4_control_operationSpeeds_SPEED_1000M_10p3125 55 3760 #define sc_x4_control_operationSpeeds_SPEED_100M_10p3125 54 3761 #define sc_x4_control_operationSpeeds_SPEED_10M_10p3125 53 3762 #define sc_x4_control_operationSpeeds_SPEED_10p5G_X4 50 3763 #define sc_x4_control_operationSpeeds_SPEED_5G_KR1 49 3764 #define sc_x4_control_operationSpeeds_SPEED_127G_X12 39 3765 #define sc_x4_control_operationSpeeds_SPEED_120G_X12 38 3766 #define sc_x4_control_operationSpeeds_SPEED_107G_X10 37 3767 #define sc_x4_control_operationSpeeds_SPEED_100G_CR10 36 3768 #define sc_x4_control_operationSpeeds_SPEED_42G_X4 35 3769 #define sc_x4_control_operationSpeeds_SPEED_40G_CR4 34 3770 #define sc_x4_control_operationSpeeds_SPEED_40G_KR4 33 3771 #define sc_x4_control_operationSpeeds_SPEED_21G_X2 32 3772 #define sc_x4_control_operationSpeeds_SPEED_20G_CR2 31 3773 #define sc_x4_control_operationSpeeds_SPEED_20G_KR2 30 3774 #define sc_x4_control_operationSpeeds_SPEED_10p6_X1 29 3775 #define sc_x4_control_operationSpeeds_SPEED_10G_KR1 28 3776 #define sc_x4_control_operationSpeeds_SPEED_40G_X4 27 3777 #define sc_x4_control_operationSpeeds_SPEED_20G_X2 26 3778 #define sc_x4_control_operationSpeeds_SPEED_20G_CX2 25 3779 #define sc_x4_control_operationSpeeds_SPEED_31p5G_KR4 24 3780 #define sc_x4_control_operationSpeeds_SPEED_31p5G_X4 23 3781 #define sc_x4_control_operationSpeeds_SPEED_15p75G_X2 22 3782 #define sc_x4_control_operationSpeeds_SPEED_25p45G_X4 21 3783 #define sc_x4_control_operationSpeeds_SPEED_12p7G_X2 20 3784 #define sc_x4_control_operationSpeeds_SPEED_21G_X4 19 3785 #define sc_x4_control_operationSpeeds_SPEED_10p5G_X2 18 3786 #define sc_x4_control_operationSpeeds_SPEED_20G_X4 17 3787 #define sc_x4_control_operationSpeeds_SPEED_10G_X2 16 3788 #define sc_x4_control_operationSpeeds_SPEED_10G_CX2 15 3789 #define sc_x4_control_operationSpeeds_SPEED_20G_CX4 14 3790 #define sc_x4_control_operationSpeeds_SPEED_16G_X4 13 3791 #define sc_x4_control_operationSpeeds_SPEED_15G_X4 12 3792 #define sc_x4_control_operationSpeeds_SPEED_13G_X4 11 3793 #define sc_x4_control_operationSpeeds_SPEED_10G_X4 10 3794 #define sc_x4_control_operationSpeeds_SPEED_10G_KX4 9 3795 #define sc_x4_control_operationSpeeds_SPEED_10G_CX4 8 3796 #define sc_x4_control_operationSpeeds_SPEED_5G_X1 7 3797 #define sc_x4_control_operationSpeeds_SPEED_2p5G_X1 6 3798 #define sc_x4_control_operationSpeeds_SPEED_1G_KX1 5 3799 #define sc_x4_control_operationSpeeds_SPEED_1G_CX1 4 3800 #define sc_x4_control_operationSpeeds_SPEED_1000M 3 3801 #define sc_x4_control_operationSpeeds_SPEED_100M 2 3802 #define sc_x4_control_operationSpeeds_SPEED_10M 1 3803 3804 /**************************************************************************** 3805 * Enums: sc_x4_control_actualSpeeds 3806 */ 3807 #define sc_x4_control_actualSpeeds_dr_10M 0 3808 #define sc_x4_control_actualSpeeds_dr_100M 1 3809 #define sc_x4_control_actualSpeeds_dr_1G 2 3810 #define sc_x4_control_actualSpeeds_dr_2p5G 3 3811 #define sc_x4_control_actualSpeeds_dr_5G_X4 4 3812 #define sc_x4_control_actualSpeeds_dr_6G_X4 5 3813 #define sc_x4_control_actualSpeeds_dr_10G_HiG 6 3814 #define sc_x4_control_actualSpeeds_dr_10G_CX4 7 3815 #define sc_x4_control_actualSpeeds_dr_12G_HiG 8 3816 #define sc_x4_control_actualSpeeds_dr_12p5G_X4 9 3817 #define sc_x4_control_actualSpeeds_dr_13G_X4 10 3818 #define sc_x4_control_actualSpeeds_dr_15G_X4 11 3819 #define sc_x4_control_actualSpeeds_dr_16G_X4 12 3820 #define sc_x4_control_actualSpeeds_dr_1G_KX 13 3821 #define sc_x4_control_actualSpeeds_dr_10G_KX4 14 3822 #define sc_x4_control_actualSpeeds_dr_10G_KR 15 3823 #define sc_x4_control_actualSpeeds_dr_5G 16 3824 #define sc_x4_control_actualSpeeds_dr_6p4G 17 3825 #define sc_x4_control_actualSpeeds_dr_20G_X4 18 3826 #define sc_x4_control_actualSpeeds_dr_21G_X4 19 3827 #define sc_x4_control_actualSpeeds_dr_25G_X4 20 3828 #define sc_x4_control_actualSpeeds_dr_10G_HiG_DXGXS 21 3829 #define sc_x4_control_actualSpeeds_dr_10G_DXGXS 22 3830 #define sc_x4_control_actualSpeeds_dr_10p5G_HiG_DXGXS 23 3831 #define sc_x4_control_actualSpeeds_dr_10p5G_DXGXS 24 3832 #define sc_x4_control_actualSpeeds_dr_12p773G_HiG_DXGXS 25 3833 #define sc_x4_control_actualSpeeds_dr_12p773G_DXGXS 26 3834 #define sc_x4_control_actualSpeeds_dr_10G_XFI 27 3835 #define sc_x4_control_actualSpeeds_dr_40G 28 3836 #define sc_x4_control_actualSpeeds_dr_20G_HiG_DXGXS 29 3837 #define sc_x4_control_actualSpeeds_dr_20G_DXGXS 30 3838 #define sc_x4_control_actualSpeeds_dr_10G_SFI 31 3839 #define sc_x4_control_actualSpeeds_dr_31p5G 32 3840 #define sc_x4_control_actualSpeeds_dr_32p7G 33 3841 #define sc_x4_control_actualSpeeds_dr_20G_SCR 34 3842 #define sc_x4_control_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 3843 #define sc_x4_control_actualSpeeds_dr_10G_DXGXS_SCR 36 3844 #define sc_x4_control_actualSpeeds_dr_12G_R2 37 3845 #define sc_x4_control_actualSpeeds_dr_10G_X2 38 3846 #define sc_x4_control_actualSpeeds_dr_40G_KR4 39 3847 #define sc_x4_control_actualSpeeds_dr_40G_CR4 40 3848 #define sc_x4_control_actualSpeeds_dr_100G_CR10 41 3849 #define sc_x4_control_actualSpeeds_dr_15p75G_DXGXS 44 3850 #define sc_x4_control_actualSpeeds_dr_20G_KR2 57 3851 #define sc_x4_control_actualSpeeds_dr_20G_CR2 58 3852 3853 /**************************************************************************** 3854 * Enums: sc_x4_control_actualSpeedsMisc1 3855 */ 3856 #define sc_x4_control_actualSpeedsMisc1_dr_2500BRCM_X1 16 3857 #define sc_x4_control_actualSpeedsMisc1_dr_5000BRCM_X4 17 3858 #define sc_x4_control_actualSpeedsMisc1_dr_6000BRCM_X4 18 3859 #define sc_x4_control_actualSpeedsMisc1_dr_10GHiGig_X4 19 3860 #define sc_x4_control_actualSpeedsMisc1_dr_10GBASE_CX4 20 3861 #define sc_x4_control_actualSpeedsMisc1_dr_12GHiGig_X4 21 3862 #define sc_x4_control_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 3863 #define sc_x4_control_actualSpeedsMisc1_dr_13GHiGig_X4 23 3864 #define sc_x4_control_actualSpeedsMisc1_dr_15GHiGig_X4 24 3865 #define sc_x4_control_actualSpeedsMisc1_dr_16GHiGig_X4 25 3866 #define sc_x4_control_actualSpeedsMisc1_dr_5000BRCM_X1 26 3867 #define sc_x4_control_actualSpeedsMisc1_dr_6363BRCM_X1 27 3868 #define sc_x4_control_actualSpeedsMisc1_dr_20GHiGig_X4 28 3869 #define sc_x4_control_actualSpeedsMisc1_dr_21GHiGig_X4 29 3870 #define sc_x4_control_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 3871 #define sc_x4_control_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 3872 3873 /**************************************************************************** 3874 * Enums: sc_x4_control_IndLaneModes 3875 */ 3876 #define sc_x4_control_IndLaneModes_SWSDR_div2 0 3877 #define sc_x4_control_IndLaneModes_SWSDR_div1 1 3878 #define sc_x4_control_IndLaneModes_DWSDR_div2 2 3879 #define sc_x4_control_IndLaneModes_DWSDR_div1 3 3880 3881 /**************************************************************************** 3882 * Enums: sc_x4_control_prbsSelect 3883 */ 3884 #define sc_x4_control_prbsSelect_prbs7 0 3885 #define sc_x4_control_prbsSelect_prbs15 1 3886 #define sc_x4_control_prbsSelect_prbs23 2 3887 #define sc_x4_control_prbsSelect_prbs31 3 3888 3889 /**************************************************************************** 3890 * Enums: sc_x4_control_vcoDivider 3891 */ 3892 #define sc_x4_control_vcoDivider_div32 0 3893 #define sc_x4_control_vcoDivider_div36 1 3894 #define sc_x4_control_vcoDivider_div40 2 3895 #define sc_x4_control_vcoDivider_div42 3 3896 #define sc_x4_control_vcoDivider_div48 4 3897 #define sc_x4_control_vcoDivider_div50 5 3898 #define sc_x4_control_vcoDivider_div52 6 3899 #define sc_x4_control_vcoDivider_div54 7 3900 #define sc_x4_control_vcoDivider_div60 8 3901 #define sc_x4_control_vcoDivider_div64 9 3902 #define sc_x4_control_vcoDivider_div66 10 3903 #define sc_x4_control_vcoDivider_div68 11 3904 #define sc_x4_control_vcoDivider_div70 12 3905 #define sc_x4_control_vcoDivider_div80 13 3906 #define sc_x4_control_vcoDivider_div92 14 3907 #define sc_x4_control_vcoDivider_div100 15 3908 3909 /**************************************************************************** 3910 * Enums: sc_x4_control_refClkSelect 3911 */ 3912 #define sc_x4_control_refClkSelect_clk_25MHz 0 3913 #define sc_x4_control_refClkSelect_clk_100MHz 1 3914 #define sc_x4_control_refClkSelect_clk_125MHz 2 3915 #define sc_x4_control_refClkSelect_clk_156p25MHz 3 3916 #define sc_x4_control_refClkSelect_clk_187p5MHz 4 3917 #define sc_x4_control_refClkSelect_clk_161p25Mhz 5 3918 #define sc_x4_control_refClkSelect_clk_50Mhz 6 3919 #define sc_x4_control_refClkSelect_clk_106p25Mhz 7 3920 3921 /**************************************************************************** 3922 * Enums: sc_x4_control_aerMMDdevTypeSelect 3923 */ 3924 #define sc_x4_control_aerMMDdevTypeSelect_combo_core 0 3925 #define sc_x4_control_aerMMDdevTypeSelect_PMA_PMD 1 3926 #define sc_x4_control_aerMMDdevTypeSelect_PCS 3 3927 #define sc_x4_control_aerMMDdevTypeSelect_PHY 4 3928 #define sc_x4_control_aerMMDdevTypeSelect_DTE 5 3929 #define sc_x4_control_aerMMDdevTypeSelect_CL73_AN 7 3930 3931 /**************************************************************************** 3932 * Enums: sc_x4_control_aerMMDportSelect 3933 */ 3934 #define sc_x4_control_aerMMDportSelect_ln0 0 3935 #define sc_x4_control_aerMMDportSelect_ln1 1 3936 #define sc_x4_control_aerMMDportSelect_ln2 2 3937 #define sc_x4_control_aerMMDportSelect_ln3 3 3938 #define sc_x4_control_aerMMDportSelect_BCST_ln0_1_2_3 511 3939 #define sc_x4_control_aerMMDportSelect_BCST_ln0_1 512 3940 #define sc_x4_control_aerMMDportSelect_BCST_ln2_3 513 3941 3942 /**************************************************************************** 3943 * Enums: sc_x4_control_firmwareModeSelect 3944 */ 3945 #define sc_x4_control_firmwareModeSelect_DEFAULT 0 3946 #define sc_x4_control_firmwareModeSelect_SFP_OPT_LR 1 3947 #define sc_x4_control_firmwareModeSelect_SFP_DAC 2 3948 #define sc_x4_control_firmwareModeSelect_XLAUI 3 3949 #define sc_x4_control_firmwareModeSelect_LONG_CH_6G 4 3950 3951 /**************************************************************************** 3952 * Enums: sc_x4_control_tempIdxSelect 3953 */ 3954 #define sc_x4_control_tempIdxSelect_LTE__22p9C 15 3955 #define sc_x4_control_tempIdxSelect_LTE__12p6C 14 3956 #define sc_x4_control_tempIdxSelect_LTE__3p0C 13 3957 #define sc_x4_control_tempIdxSelect_LTE_6p7C 12 3958 #define sc_x4_control_tempIdxSelect_LTE_16p4C 11 3959 #define sc_x4_control_tempIdxSelect_LTE_26p6C 10 3960 #define sc_x4_control_tempIdxSelect_LTE_36p3C 9 3961 #define sc_x4_control_tempIdxSelect_LTE_46p0C 8 3962 #define sc_x4_control_tempIdxSelect_LTE_56p2C 7 3963 #define sc_x4_control_tempIdxSelect_LTE_65p9C 6 3964 #define sc_x4_control_tempIdxSelect_LTE_75p6C 5 3965 #define sc_x4_control_tempIdxSelect_LTE_85p3C 4 3966 #define sc_x4_control_tempIdxSelect_LTE_95p5C 3 3967 #define sc_x4_control_tempIdxSelect_LTE_105p2C 2 3968 #define sc_x4_control_tempIdxSelect_LTE_114p9C 1 3969 #define sc_x4_control_tempIdxSelect_LTE_125p1C 0 3970 3971 /**************************************************************************** 3972 * Enums: sc_x4_control_sc_seq_status 3973 */ 3974 #define sc_x4_control_sc_seq_status_START 32768 3975 #define sc_x4_control_sc_seq_status_RESET_PCS 16384 3976 #define sc_x4_control_sc_seq_status_RESET_PMD_LANE 8192 3977 #define sc_x4_control_sc_seq_status_RESET_PMD_PLL 4096 3978 #define sc_x4_control_sc_seq_status_APPLY_SPEED_CFG 2048 3979 #define sc_x4_control_sc_seq_status_WAIT_CFG_DONE 1024 3980 #define sc_x4_control_sc_seq_status_ACTIVATE_PMD 512 3981 #define sc_x4_control_sc_seq_status_WAIT_PLL_RESET 256 3982 #define sc_x4_control_sc_seq_status_PLL_LOCK_FAIL 128 3983 #define sc_x4_control_sc_seq_status_ACTIVATE_TX 64 3984 #define sc_x4_control_sc_seq_status_WAIT_PMD_LOCK 32 3985 #define sc_x4_control_sc_seq_status_ACTIVATE_RX 16 3986 #define sc_x4_control_sc_seq_status_PMD_LOCK_FAIL 8 3987 #define sc_x4_control_sc_seq_status_DONE 4 3988 #define sc_x4_control_sc_seq_status_STOP 2 3989 #define sc_x4_control_sc_seq_status_BYPASS 1 3990 3991 /**************************************************************************** 3992 * Enums: sc_x4_final_config_status_cl36TxEEEStates_l 3993 */ 3994 #define sc_x4_final_config_status_cl36TxEEEStates_l_TX_REFRESH 8 3995 #define sc_x4_final_config_status_cl36TxEEEStates_l_TX_QUIET 4 3996 #define sc_x4_final_config_status_cl36TxEEEStates_l_TX_SLEEP 2 3997 #define sc_x4_final_config_status_cl36TxEEEStates_l_TX_ACTIVE 1 3998 3999 /**************************************************************************** 4000 * Enums: sc_x4_final_config_status_cl36TxEEEStates_c 4001 */ 4002 #define sc_x4_final_config_status_cl36TxEEEStates_c_TX_REFRESH 3 4003 #define sc_x4_final_config_status_cl36TxEEEStates_c_TX_QUIET 2 4004 #define sc_x4_final_config_status_cl36TxEEEStates_c_TX_SLEEP 1 4005 #define sc_x4_final_config_status_cl36TxEEEStates_c_TX_ACTIVE 0 4006 4007 /**************************************************************************** 4008 * Enums: sc_x4_final_config_status_cl49TxEEEStates_l 4009 */ 4010 #define sc_x4_final_config_status_cl49TxEEEStates_l_SCR_RESET_2 64 4011 #define sc_x4_final_config_status_cl49TxEEEStates_l_SCR_RESET_1 32 4012 #define sc_x4_final_config_status_cl49TxEEEStates_l_TX_WAKE 16 4013 #define sc_x4_final_config_status_cl49TxEEEStates_l_TX_REFRESH 8 4014 #define sc_x4_final_config_status_cl49TxEEEStates_l_TX_QUIET 4 4015 #define sc_x4_final_config_status_cl49TxEEEStates_l_TX_SLEEP 2 4016 #define sc_x4_final_config_status_cl49TxEEEStates_l_TX_ACTIVE 1 4017 4018 /**************************************************************************** 4019 * Enums: sc_x4_final_config_status_cl49TxEEEStates_c 4020 */ 4021 #define sc_x4_final_config_status_cl49TxEEEStates_c_SCR_RESET_2 6 4022 #define sc_x4_final_config_status_cl49TxEEEStates_c_SCR_RESET_1 5 4023 #define sc_x4_final_config_status_cl49TxEEEStates_c_TX_WAKE 4 4024 #define sc_x4_final_config_status_cl49TxEEEStates_c_TX_REFRESH 3 4025 #define sc_x4_final_config_status_cl49TxEEEStates_c_TX_QUIET 2 4026 #define sc_x4_final_config_status_cl49TxEEEStates_c_TX_SLEEP 1 4027 #define sc_x4_final_config_status_cl49TxEEEStates_c_TX_ACTIVE 0 4028 4029 /**************************************************************************** 4030 * Enums: sc_x4_final_config_status_cl36RxEEEStates_l 4031 */ 4032 #define sc_x4_final_config_status_cl36RxEEEStates_l_RX_LINK_FAIL 32 4033 #define sc_x4_final_config_status_cl36RxEEEStates_l_RX_WTF 16 4034 #define sc_x4_final_config_status_cl36RxEEEStates_l_RX_WAKE 8 4035 #define sc_x4_final_config_status_cl36RxEEEStates_l_RX_QUIET 4 4036 #define sc_x4_final_config_status_cl36RxEEEStates_l_RX_SLEEP 2 4037 #define sc_x4_final_config_status_cl36RxEEEStates_l_RX_ACTIVE 1 4038 4039 /**************************************************************************** 4040 * Enums: sc_x4_final_config_status_cl36RxEEEStates_c 4041 */ 4042 #define sc_x4_final_config_status_cl36RxEEEStates_c_RX_LINK_FAIL 5 4043 #define sc_x4_final_config_status_cl36RxEEEStates_c_RX_WTF 4 4044 #define sc_x4_final_config_status_cl36RxEEEStates_c_RX_WAKE 3 4045 #define sc_x4_final_config_status_cl36RxEEEStates_c_RX_QUIET 2 4046 #define sc_x4_final_config_status_cl36RxEEEStates_c_RX_SLEEP 1 4047 #define sc_x4_final_config_status_cl36RxEEEStates_c_RX_ACTIVE 0 4048 4049 /**************************************************************************** 4050 * Enums: sc_x4_final_config_status_cl49RxEEEStates_l 4051 */ 4052 #define sc_x4_final_config_status_cl49RxEEEStates_l_RX_LINK_FAIL 32 4053 #define sc_x4_final_config_status_cl49RxEEEStates_l_RX_WTF 16 4054 #define sc_x4_final_config_status_cl49RxEEEStates_l_RX_WAKE 8 4055 #define sc_x4_final_config_status_cl49RxEEEStates_l_RX_QUIET 4 4056 #define sc_x4_final_config_status_cl49RxEEEStates_l_RX_SLEEP 2 4057 #define sc_x4_final_config_status_cl49RxEEEStates_l_RX_ACTIVE 1 4058 4059 /**************************************************************************** 4060 * Enums: sc_x4_final_config_status_cl49RxEEEStates_c 4061 */ 4062 #define sc_x4_final_config_status_cl49RxEEEStates_c_RX_LINK_FAIL 5 4063 #define sc_x4_final_config_status_cl49RxEEEStates_c_RX_WTF 4 4064 #define sc_x4_final_config_status_cl49RxEEEStates_c_RX_WAKE 3 4065 #define sc_x4_final_config_status_cl49RxEEEStates_c_RX_QUIET 2 4066 #define sc_x4_final_config_status_cl49RxEEEStates_c_RX_SLEEP 1 4067 #define sc_x4_final_config_status_cl49RxEEEStates_c_RX_ACTIVE 0 4068 4069 /**************************************************************************** 4070 * Enums: sc_x4_final_config_status_cl48TxEEEStates_l 4071 */ 4072 #define sc_x4_final_config_status_cl48TxEEEStates_l_TX_REFRESH 8 4073 #define sc_x4_final_config_status_cl48TxEEEStates_l_TX_QUIET 4 4074 #define sc_x4_final_config_status_cl48TxEEEStates_l_TX_SLEEP 2 4075 #define sc_x4_final_config_status_cl48TxEEEStates_l_TX_ACTIVE 1 4076 4077 /**************************************************************************** 4078 * Enums: sc_x4_final_config_status_cl48TxEEEStates_c 4079 */ 4080 #define sc_x4_final_config_status_cl48TxEEEStates_c_TX_REFRESH 3 4081 #define sc_x4_final_config_status_cl48TxEEEStates_c_TX_QUIET 2 4082 #define sc_x4_final_config_status_cl48TxEEEStates_c_TX_SLEEP 1 4083 #define sc_x4_final_config_status_cl48TxEEEStates_c_TX_ACTIVE 0 4084 4085 /**************************************************************************** 4086 * Enums: sc_x4_final_config_status_cl48RxEEEStates_l 4087 */ 4088 #define sc_x4_final_config_status_cl48RxEEEStates_l_RX_LINK_FAIL 32 4089 #define sc_x4_final_config_status_cl48RxEEEStates_l_RX_WAKE 16 4090 #define sc_x4_final_config_status_cl48RxEEEStates_l_RX_QUIET 8 4091 #define sc_x4_final_config_status_cl48RxEEEStates_l_RX_DEACT 4 4092 #define sc_x4_final_config_status_cl48RxEEEStates_l_RX_SLEEP 2 4093 #define sc_x4_final_config_status_cl48RxEEEStates_l_RX_ACTIVE 1 4094 4095 /**************************************************************************** 4096 * Enums: sc_x4_final_config_status_cl48RxEEEStates_c 4097 */ 4098 #define sc_x4_final_config_status_cl48RxEEEStates_c_RX_LINK_FAIL 5 4099 #define sc_x4_final_config_status_cl48RxEEEStates_c_RX_WAKE 4 4100 #define sc_x4_final_config_status_cl48RxEEEStates_c_RX_QUIET 3 4101 #define sc_x4_final_config_status_cl48RxEEEStates_c_RX_DEACT 2 4102 #define sc_x4_final_config_status_cl48RxEEEStates_c_RX_SLEEP 1 4103 #define sc_x4_final_config_status_cl48RxEEEStates_c_RX_ACTIVE 0 4104 4105 /**************************************************************************** 4106 * Enums: sc_x4_final_config_status_IQP_Options 4107 */ 4108 #define sc_x4_final_config_status_IQP_Options_i50uA 0 4109 #define sc_x4_final_config_status_IQP_Options_i100uA 1 4110 #define sc_x4_final_config_status_IQP_Options_i150uA 2 4111 #define sc_x4_final_config_status_IQP_Options_i200uA 3 4112 #define sc_x4_final_config_status_IQP_Options_i250uA 4 4113 #define sc_x4_final_config_status_IQP_Options_i300uA 5 4114 #define sc_x4_final_config_status_IQP_Options_i350uA 6 4115 #define sc_x4_final_config_status_IQP_Options_i400uA 7 4116 #define sc_x4_final_config_status_IQP_Options_i450uA 8 4117 #define sc_x4_final_config_status_IQP_Options_i500uA 9 4118 #define sc_x4_final_config_status_IQP_Options_i550uA 10 4119 #define sc_x4_final_config_status_IQP_Options_i600uA 11 4120 #define sc_x4_final_config_status_IQP_Options_i650uA 12 4121 #define sc_x4_final_config_status_IQP_Options_i700uA 13 4122 #define sc_x4_final_config_status_IQP_Options_i750uA 14 4123 #define sc_x4_final_config_status_IQP_Options_i800uA 15 4124 4125 /**************************************************************************** 4126 * Enums: sc_x4_final_config_status_IDriver_Options 4127 */ 4128 #define sc_x4_final_config_status_IDriver_Options_v680mV 0 4129 #define sc_x4_final_config_status_IDriver_Options_v730mV 1 4130 #define sc_x4_final_config_status_IDriver_Options_v780mV 2 4131 #define sc_x4_final_config_status_IDriver_Options_v830mV 3 4132 #define sc_x4_final_config_status_IDriver_Options_v880mV 4 4133 #define sc_x4_final_config_status_IDriver_Options_v930mV 5 4134 #define sc_x4_final_config_status_IDriver_Options_v980mV 6 4135 #define sc_x4_final_config_status_IDriver_Options_v1010mV 7 4136 #define sc_x4_final_config_status_IDriver_Options_v1040mV 8 4137 #define sc_x4_final_config_status_IDriver_Options_v1060mV 9 4138 #define sc_x4_final_config_status_IDriver_Options_v1070mV 10 4139 #define sc_x4_final_config_status_IDriver_Options_v1080mV 11 4140 #define sc_x4_final_config_status_IDriver_Options_v1085mV 12 4141 #define sc_x4_final_config_status_IDriver_Options_v1090mV 13 4142 #define sc_x4_final_config_status_IDriver_Options_v1095mV 14 4143 #define sc_x4_final_config_status_IDriver_Options_v1100mV 15 4144 4145 /**************************************************************************** 4146 * Enums: sc_x4_final_config_status_operationModes 4147 */ 4148 #define sc_x4_final_config_status_operationModes_XGXS 0 4149 #define sc_x4_final_config_status_operationModes_XGXG_nCC 1 4150 #define sc_x4_final_config_status_operationModes_Indlane_OS8 4 4151 #define sc_x4_final_config_status_operationModes_IndLane_OS5 5 4152 #define sc_x4_final_config_status_operationModes_PCI 7 4153 #define sc_x4_final_config_status_operationModes_XGXS_nLQ 8 4154 #define sc_x4_final_config_status_operationModes_XGXS_nLQnCC 9 4155 #define sc_x4_final_config_status_operationModes_PBypass 10 4156 #define sc_x4_final_config_status_operationModes_PBypass_nDSK 11 4157 #define sc_x4_final_config_status_operationModes_ComboCoreMode 12 4158 #define sc_x4_final_config_status_operationModes_Clocks_off 15 4159 4160 /**************************************************************************** 4161 * Enums: sc_x4_final_config_status_synce_enum 4162 */ 4163 #define sc_x4_final_config_status_synce_enum_SYNCE_NO_DIV 0 4164 #define sc_x4_final_config_status_synce_enum_SYNCE_DIV_7 1 4165 #define sc_x4_final_config_status_synce_enum_SYNCE_DIV_11 2 4166 4167 /**************************************************************************** 4168 * Enums: sc_x4_final_config_status_operationSpeeds 4169 */ 4170 #define sc_x4_final_config_status_operationSpeeds_SPEED_2p5G_X1_10p3125 56 4171 #define sc_x4_final_config_status_operationSpeeds_SPEED_1000M_10p3125 55 4172 #define sc_x4_final_config_status_operationSpeeds_SPEED_100M_10p3125 54 4173 #define sc_x4_final_config_status_operationSpeeds_SPEED_10M_10p3125 53 4174 #define sc_x4_final_config_status_operationSpeeds_SPEED_10p5G_X4 50 4175 #define sc_x4_final_config_status_operationSpeeds_SPEED_5G_KR1 49 4176 #define sc_x4_final_config_status_operationSpeeds_SPEED_127G_X12 39 4177 #define sc_x4_final_config_status_operationSpeeds_SPEED_120G_X12 38 4178 #define sc_x4_final_config_status_operationSpeeds_SPEED_107G_X10 37 4179 #define sc_x4_final_config_status_operationSpeeds_SPEED_100G_CR10 36 4180 #define sc_x4_final_config_status_operationSpeeds_SPEED_42G_X4 35 4181 #define sc_x4_final_config_status_operationSpeeds_SPEED_40G_CR4 34 4182 #define sc_x4_final_config_status_operationSpeeds_SPEED_40G_KR4 33 4183 #define sc_x4_final_config_status_operationSpeeds_SPEED_21G_X2 32 4184 #define sc_x4_final_config_status_operationSpeeds_SPEED_20G_CR2 31 4185 #define sc_x4_final_config_status_operationSpeeds_SPEED_20G_KR2 30 4186 #define sc_x4_final_config_status_operationSpeeds_SPEED_10p6_X1 29 4187 #define sc_x4_final_config_status_operationSpeeds_SPEED_10G_KR1 28 4188 #define sc_x4_final_config_status_operationSpeeds_SPEED_40G_X4 27 4189 #define sc_x4_final_config_status_operationSpeeds_SPEED_20G_X2 26 4190 #define sc_x4_final_config_status_operationSpeeds_SPEED_20G_CX2 25 4191 #define sc_x4_final_config_status_operationSpeeds_SPEED_31p5G_KR4 24 4192 #define sc_x4_final_config_status_operationSpeeds_SPEED_31p5G_X4 23 4193 #define sc_x4_final_config_status_operationSpeeds_SPEED_15p75G_X2 22 4194 #define sc_x4_final_config_status_operationSpeeds_SPEED_25p45G_X4 21 4195 #define sc_x4_final_config_status_operationSpeeds_SPEED_12p7G_X2 20 4196 #define sc_x4_final_config_status_operationSpeeds_SPEED_21G_X4 19 4197 #define sc_x4_final_config_status_operationSpeeds_SPEED_10p5G_X2 18 4198 #define sc_x4_final_config_status_operationSpeeds_SPEED_20G_X4 17 4199 #define sc_x4_final_config_status_operationSpeeds_SPEED_10G_X2 16 4200 #define sc_x4_final_config_status_operationSpeeds_SPEED_10G_CX2 15 4201 #define sc_x4_final_config_status_operationSpeeds_SPEED_20G_CX4 14 4202 #define sc_x4_final_config_status_operationSpeeds_SPEED_16G_X4 13 4203 #define sc_x4_final_config_status_operationSpeeds_SPEED_15G_X4 12 4204 #define sc_x4_final_config_status_operationSpeeds_SPEED_13G_X4 11 4205 #define sc_x4_final_config_status_operationSpeeds_SPEED_10G_X4 10 4206 #define sc_x4_final_config_status_operationSpeeds_SPEED_10G_KX4 9 4207 #define sc_x4_final_config_status_operationSpeeds_SPEED_10G_CX4 8 4208 #define sc_x4_final_config_status_operationSpeeds_SPEED_5G_X1 7 4209 #define sc_x4_final_config_status_operationSpeeds_SPEED_2p5G_X1 6 4210 #define sc_x4_final_config_status_operationSpeeds_SPEED_1G_KX1 5 4211 #define sc_x4_final_config_status_operationSpeeds_SPEED_1G_CX1 4 4212 #define sc_x4_final_config_status_operationSpeeds_SPEED_1000M 3 4213 #define sc_x4_final_config_status_operationSpeeds_SPEED_100M 2 4214 #define sc_x4_final_config_status_operationSpeeds_SPEED_10M 1 4215 4216 /**************************************************************************** 4217 * Enums: sc_x4_final_config_status_actualSpeeds 4218 */ 4219 #define sc_x4_final_config_status_actualSpeeds_dr_10M 0 4220 #define sc_x4_final_config_status_actualSpeeds_dr_100M 1 4221 #define sc_x4_final_config_status_actualSpeeds_dr_1G 2 4222 #define sc_x4_final_config_status_actualSpeeds_dr_2p5G 3 4223 #define sc_x4_final_config_status_actualSpeeds_dr_5G_X4 4 4224 #define sc_x4_final_config_status_actualSpeeds_dr_6G_X4 5 4225 #define sc_x4_final_config_status_actualSpeeds_dr_10G_HiG 6 4226 #define sc_x4_final_config_status_actualSpeeds_dr_10G_CX4 7 4227 #define sc_x4_final_config_status_actualSpeeds_dr_12G_HiG 8 4228 #define sc_x4_final_config_status_actualSpeeds_dr_12p5G_X4 9 4229 #define sc_x4_final_config_status_actualSpeeds_dr_13G_X4 10 4230 #define sc_x4_final_config_status_actualSpeeds_dr_15G_X4 11 4231 #define sc_x4_final_config_status_actualSpeeds_dr_16G_X4 12 4232 #define sc_x4_final_config_status_actualSpeeds_dr_1G_KX 13 4233 #define sc_x4_final_config_status_actualSpeeds_dr_10G_KX4 14 4234 #define sc_x4_final_config_status_actualSpeeds_dr_10G_KR 15 4235 #define sc_x4_final_config_status_actualSpeeds_dr_5G 16 4236 #define sc_x4_final_config_status_actualSpeeds_dr_6p4G 17 4237 #define sc_x4_final_config_status_actualSpeeds_dr_20G_X4 18 4238 #define sc_x4_final_config_status_actualSpeeds_dr_21G_X4 19 4239 #define sc_x4_final_config_status_actualSpeeds_dr_25G_X4 20 4240 #define sc_x4_final_config_status_actualSpeeds_dr_10G_HiG_DXGXS 21 4241 #define sc_x4_final_config_status_actualSpeeds_dr_10G_DXGXS 22 4242 #define sc_x4_final_config_status_actualSpeeds_dr_10p5G_HiG_DXGXS 23 4243 #define sc_x4_final_config_status_actualSpeeds_dr_10p5G_DXGXS 24 4244 #define sc_x4_final_config_status_actualSpeeds_dr_12p773G_HiG_DXGXS 25 4245 #define sc_x4_final_config_status_actualSpeeds_dr_12p773G_DXGXS 26 4246 #define sc_x4_final_config_status_actualSpeeds_dr_10G_XFI 27 4247 #define sc_x4_final_config_status_actualSpeeds_dr_40G 28 4248 #define sc_x4_final_config_status_actualSpeeds_dr_20G_HiG_DXGXS 29 4249 #define sc_x4_final_config_status_actualSpeeds_dr_20G_DXGXS 30 4250 #define sc_x4_final_config_status_actualSpeeds_dr_10G_SFI 31 4251 #define sc_x4_final_config_status_actualSpeeds_dr_31p5G 32 4252 #define sc_x4_final_config_status_actualSpeeds_dr_32p7G 33 4253 #define sc_x4_final_config_status_actualSpeeds_dr_20G_SCR 34 4254 #define sc_x4_final_config_status_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 4255 #define sc_x4_final_config_status_actualSpeeds_dr_10G_DXGXS_SCR 36 4256 #define sc_x4_final_config_status_actualSpeeds_dr_12G_R2 37 4257 #define sc_x4_final_config_status_actualSpeeds_dr_10G_X2 38 4258 #define sc_x4_final_config_status_actualSpeeds_dr_40G_KR4 39 4259 #define sc_x4_final_config_status_actualSpeeds_dr_40G_CR4 40 4260 #define sc_x4_final_config_status_actualSpeeds_dr_100G_CR10 41 4261 #define sc_x4_final_config_status_actualSpeeds_dr_15p75G_DXGXS 44 4262 #define sc_x4_final_config_status_actualSpeeds_dr_20G_KR2 57 4263 #define sc_x4_final_config_status_actualSpeeds_dr_20G_CR2 58 4264 4265 /**************************************************************************** 4266 * Enums: sc_x4_final_config_status_actualSpeedsMisc1 4267 */ 4268 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_2500BRCM_X1 16 4269 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_5000BRCM_X4 17 4270 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_6000BRCM_X4 18 4271 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_10GHiGig_X4 19 4272 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_10GBASE_CX4 20 4273 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_12GHiGig_X4 21 4274 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 4275 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_13GHiGig_X4 23 4276 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_15GHiGig_X4 24 4277 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_16GHiGig_X4 25 4278 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_5000BRCM_X1 26 4279 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_6363BRCM_X1 27 4280 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_20GHiGig_X4 28 4281 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_21GHiGig_X4 29 4282 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 4283 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 4284 4285 /**************************************************************************** 4286 * Enums: sc_x4_final_config_status_IndLaneModes 4287 */ 4288 #define sc_x4_final_config_status_IndLaneModes_SWSDR_div2 0 4289 #define sc_x4_final_config_status_IndLaneModes_SWSDR_div1 1 4290 #define sc_x4_final_config_status_IndLaneModes_DWSDR_div2 2 4291 #define sc_x4_final_config_status_IndLaneModes_DWSDR_div1 3 4292 4293 /**************************************************************************** 4294 * Enums: sc_x4_final_config_status_prbsSelect 4295 */ 4296 #define sc_x4_final_config_status_prbsSelect_prbs7 0 4297 #define sc_x4_final_config_status_prbsSelect_prbs15 1 4298 #define sc_x4_final_config_status_prbsSelect_prbs23 2 4299 #define sc_x4_final_config_status_prbsSelect_prbs31 3 4300 4301 /**************************************************************************** 4302 * Enums: sc_x4_final_config_status_vcoDivider 4303 */ 4304 #define sc_x4_final_config_status_vcoDivider_div32 0 4305 #define sc_x4_final_config_status_vcoDivider_div36 1 4306 #define sc_x4_final_config_status_vcoDivider_div40 2 4307 #define sc_x4_final_config_status_vcoDivider_div42 3 4308 #define sc_x4_final_config_status_vcoDivider_div48 4 4309 #define sc_x4_final_config_status_vcoDivider_div50 5 4310 #define sc_x4_final_config_status_vcoDivider_div52 6 4311 #define sc_x4_final_config_status_vcoDivider_div54 7 4312 #define sc_x4_final_config_status_vcoDivider_div60 8 4313 #define sc_x4_final_config_status_vcoDivider_div64 9 4314 #define sc_x4_final_config_status_vcoDivider_div66 10 4315 #define sc_x4_final_config_status_vcoDivider_div68 11 4316 #define sc_x4_final_config_status_vcoDivider_div70 12 4317 #define sc_x4_final_config_status_vcoDivider_div80 13 4318 #define sc_x4_final_config_status_vcoDivider_div92 14 4319 #define sc_x4_final_config_status_vcoDivider_div100 15 4320 4321 /**************************************************************************** 4322 * Enums: sc_x4_final_config_status_refClkSelect 4323 */ 4324 #define sc_x4_final_config_status_refClkSelect_clk_25MHz 0 4325 #define sc_x4_final_config_status_refClkSelect_clk_100MHz 1 4326 #define sc_x4_final_config_status_refClkSelect_clk_125MHz 2 4327 #define sc_x4_final_config_status_refClkSelect_clk_156p25MHz 3 4328 #define sc_x4_final_config_status_refClkSelect_clk_187p5MHz 4 4329 #define sc_x4_final_config_status_refClkSelect_clk_161p25Mhz 5 4330 #define sc_x4_final_config_status_refClkSelect_clk_50Mhz 6 4331 #define sc_x4_final_config_status_refClkSelect_clk_106p25Mhz 7 4332 4333 /**************************************************************************** 4334 * Enums: sc_x4_final_config_status_aerMMDdevTypeSelect 4335 */ 4336 #define sc_x4_final_config_status_aerMMDdevTypeSelect_combo_core 0 4337 #define sc_x4_final_config_status_aerMMDdevTypeSelect_PMA_PMD 1 4338 #define sc_x4_final_config_status_aerMMDdevTypeSelect_PCS 3 4339 #define sc_x4_final_config_status_aerMMDdevTypeSelect_PHY 4 4340 #define sc_x4_final_config_status_aerMMDdevTypeSelect_DTE 5 4341 #define sc_x4_final_config_status_aerMMDdevTypeSelect_CL73_AN 7 4342 4343 /**************************************************************************** 4344 * Enums: sc_x4_final_config_status_aerMMDportSelect 4345 */ 4346 #define sc_x4_final_config_status_aerMMDportSelect_ln0 0 4347 #define sc_x4_final_config_status_aerMMDportSelect_ln1 1 4348 #define sc_x4_final_config_status_aerMMDportSelect_ln2 2 4349 #define sc_x4_final_config_status_aerMMDportSelect_ln3 3 4350 #define sc_x4_final_config_status_aerMMDportSelect_BCST_ln0_1_2_3 511 4351 #define sc_x4_final_config_status_aerMMDportSelect_BCST_ln0_1 512 4352 #define sc_x4_final_config_status_aerMMDportSelect_BCST_ln2_3 513 4353 4354 /**************************************************************************** 4355 * Enums: sc_x4_final_config_status_firmwareModeSelect 4356 */ 4357 #define sc_x4_final_config_status_firmwareModeSelect_DEFAULT 0 4358 #define sc_x4_final_config_status_firmwareModeSelect_SFP_OPT_LR 1 4359 #define sc_x4_final_config_status_firmwareModeSelect_SFP_DAC 2 4360 #define sc_x4_final_config_status_firmwareModeSelect_XLAUI 3 4361 #define sc_x4_final_config_status_firmwareModeSelect_LONG_CH_6G 4 4362 4363 /**************************************************************************** 4364 * Enums: sc_x4_final_config_status_tempIdxSelect 4365 */ 4366 #define sc_x4_final_config_status_tempIdxSelect_LTE__22p9C 15 4367 #define sc_x4_final_config_status_tempIdxSelect_LTE__12p6C 14 4368 #define sc_x4_final_config_status_tempIdxSelect_LTE__3p0C 13 4369 #define sc_x4_final_config_status_tempIdxSelect_LTE_6p7C 12 4370 #define sc_x4_final_config_status_tempIdxSelect_LTE_16p4C 11 4371 #define sc_x4_final_config_status_tempIdxSelect_LTE_26p6C 10 4372 #define sc_x4_final_config_status_tempIdxSelect_LTE_36p3C 9 4373 #define sc_x4_final_config_status_tempIdxSelect_LTE_46p0C 8 4374 #define sc_x4_final_config_status_tempIdxSelect_LTE_56p2C 7 4375 #define sc_x4_final_config_status_tempIdxSelect_LTE_65p9C 6 4376 #define sc_x4_final_config_status_tempIdxSelect_LTE_75p6C 5 4377 #define sc_x4_final_config_status_tempIdxSelect_LTE_85p3C 4 4378 #define sc_x4_final_config_status_tempIdxSelect_LTE_95p5C 3 4379 #define sc_x4_final_config_status_tempIdxSelect_LTE_105p2C 2 4380 #define sc_x4_final_config_status_tempIdxSelect_LTE_114p9C 1 4381 #define sc_x4_final_config_status_tempIdxSelect_LTE_125p1C 0 4382 4383 /**************************************************************************** 4384 * Enums: tx_x1_status0_tla_pll_status 4385 */ 4386 #define tx_x1_status0_tla_pll_status_INIT 1 4387 #define tx_x1_status0_tla_pll_status_PLL_LOCKED 2 4388 #define tx_x1_status0_tla_pll_status_RESET_PLL 4 4389 #define tx_x1_status0_tla_pll_status_CHANGE_PLL_MODE 8 4390 #define tx_x1_status0_tla_pll_status_PLL_SWITCH 16 4391 4392 /**************************************************************************** 4393 * Enums: tx_x4_credit_gen0_cl36TxEEEStates_l 4394 */ 4395 #define tx_x4_credit_gen0_cl36TxEEEStates_l_TX_REFRESH 8 4396 #define tx_x4_credit_gen0_cl36TxEEEStates_l_TX_QUIET 4 4397 #define tx_x4_credit_gen0_cl36TxEEEStates_l_TX_SLEEP 2 4398 #define tx_x4_credit_gen0_cl36TxEEEStates_l_TX_ACTIVE 1 4399 4400 /**************************************************************************** 4401 * Enums: tx_x4_credit_gen0_cl36TxEEEStates_c 4402 */ 4403 #define tx_x4_credit_gen0_cl36TxEEEStates_c_TX_REFRESH 3 4404 #define tx_x4_credit_gen0_cl36TxEEEStates_c_TX_QUIET 2 4405 #define tx_x4_credit_gen0_cl36TxEEEStates_c_TX_SLEEP 1 4406 #define tx_x4_credit_gen0_cl36TxEEEStates_c_TX_ACTIVE 0 4407 4408 /**************************************************************************** 4409 * Enums: tx_x4_credit_gen0_cl49TxEEEStates_l 4410 */ 4411 #define tx_x4_credit_gen0_cl49TxEEEStates_l_SCR_RESET_2 64 4412 #define tx_x4_credit_gen0_cl49TxEEEStates_l_SCR_RESET_1 32 4413 #define tx_x4_credit_gen0_cl49TxEEEStates_l_TX_WAKE 16 4414 #define tx_x4_credit_gen0_cl49TxEEEStates_l_TX_REFRESH 8 4415 #define tx_x4_credit_gen0_cl49TxEEEStates_l_TX_QUIET 4 4416 #define tx_x4_credit_gen0_cl49TxEEEStates_l_TX_SLEEP 2 4417 #define tx_x4_credit_gen0_cl49TxEEEStates_l_TX_ACTIVE 1 4418 4419 /**************************************************************************** 4420 * Enums: tx_x4_credit_gen0_cl49TxEEEStates_c 4421 */ 4422 #define tx_x4_credit_gen0_cl49TxEEEStates_c_SCR_RESET_2 6 4423 #define tx_x4_credit_gen0_cl49TxEEEStates_c_SCR_RESET_1 5 4424 #define tx_x4_credit_gen0_cl49TxEEEStates_c_TX_WAKE 4 4425 #define tx_x4_credit_gen0_cl49TxEEEStates_c_TX_REFRESH 3 4426 #define tx_x4_credit_gen0_cl49TxEEEStates_c_TX_QUIET 2 4427 #define tx_x4_credit_gen0_cl49TxEEEStates_c_TX_SLEEP 1 4428 #define tx_x4_credit_gen0_cl49TxEEEStates_c_TX_ACTIVE 0 4429 4430 /**************************************************************************** 4431 * Enums: tx_x4_credit_gen0_cl36RxEEEStates_l 4432 */ 4433 #define tx_x4_credit_gen0_cl36RxEEEStates_l_RX_LINK_FAIL 32 4434 #define tx_x4_credit_gen0_cl36RxEEEStates_l_RX_WTF 16 4435 #define tx_x4_credit_gen0_cl36RxEEEStates_l_RX_WAKE 8 4436 #define tx_x4_credit_gen0_cl36RxEEEStates_l_RX_QUIET 4 4437 #define tx_x4_credit_gen0_cl36RxEEEStates_l_RX_SLEEP 2 4438 #define tx_x4_credit_gen0_cl36RxEEEStates_l_RX_ACTIVE 1 4439 4440 /**************************************************************************** 4441 * Enums: tx_x4_credit_gen0_cl36RxEEEStates_c 4442 */ 4443 #define tx_x4_credit_gen0_cl36RxEEEStates_c_RX_LINK_FAIL 5 4444 #define tx_x4_credit_gen0_cl36RxEEEStates_c_RX_WTF 4 4445 #define tx_x4_credit_gen0_cl36RxEEEStates_c_RX_WAKE 3 4446 #define tx_x4_credit_gen0_cl36RxEEEStates_c_RX_QUIET 2 4447 #define tx_x4_credit_gen0_cl36RxEEEStates_c_RX_SLEEP 1 4448 #define tx_x4_credit_gen0_cl36RxEEEStates_c_RX_ACTIVE 0 4449 4450 /**************************************************************************** 4451 * Enums: tx_x4_credit_gen0_cl49RxEEEStates_l 4452 */ 4453 #define tx_x4_credit_gen0_cl49RxEEEStates_l_RX_LINK_FAIL 32 4454 #define tx_x4_credit_gen0_cl49RxEEEStates_l_RX_WTF 16 4455 #define tx_x4_credit_gen0_cl49RxEEEStates_l_RX_WAKE 8 4456 #define tx_x4_credit_gen0_cl49RxEEEStates_l_RX_QUIET 4 4457 #define tx_x4_credit_gen0_cl49RxEEEStates_l_RX_SLEEP 2 4458 #define tx_x4_credit_gen0_cl49RxEEEStates_l_RX_ACTIVE 1 4459 4460 /**************************************************************************** 4461 * Enums: tx_x4_credit_gen0_cl49RxEEEStates_c 4462 */ 4463 #define tx_x4_credit_gen0_cl49RxEEEStates_c_RX_LINK_FAIL 5 4464 #define tx_x4_credit_gen0_cl49RxEEEStates_c_RX_WTF 4 4465 #define tx_x4_credit_gen0_cl49RxEEEStates_c_RX_WAKE 3 4466 #define tx_x4_credit_gen0_cl49RxEEEStates_c_RX_QUIET 2 4467 #define tx_x4_credit_gen0_cl49RxEEEStates_c_RX_SLEEP 1 4468 #define tx_x4_credit_gen0_cl49RxEEEStates_c_RX_ACTIVE 0 4469 4470 /**************************************************************************** 4471 * Enums: tx_x4_credit_gen0_cl48TxEEEStates_l 4472 */ 4473 #define tx_x4_credit_gen0_cl48TxEEEStates_l_TX_REFRESH 8 4474 #define tx_x4_credit_gen0_cl48TxEEEStates_l_TX_QUIET 4 4475 #define tx_x4_credit_gen0_cl48TxEEEStates_l_TX_SLEEP 2 4476 #define tx_x4_credit_gen0_cl48TxEEEStates_l_TX_ACTIVE 1 4477 4478 /**************************************************************************** 4479 * Enums: tx_x4_credit_gen0_cl48TxEEEStates_c 4480 */ 4481 #define tx_x4_credit_gen0_cl48TxEEEStates_c_TX_REFRESH 3 4482 #define tx_x4_credit_gen0_cl48TxEEEStates_c_TX_QUIET 2 4483 #define tx_x4_credit_gen0_cl48TxEEEStates_c_TX_SLEEP 1 4484 #define tx_x4_credit_gen0_cl48TxEEEStates_c_TX_ACTIVE 0 4485 4486 /**************************************************************************** 4487 * Enums: tx_x4_credit_gen0_cl48RxEEEStates_l 4488 */ 4489 #define tx_x4_credit_gen0_cl48RxEEEStates_l_RX_LINK_FAIL 32 4490 #define tx_x4_credit_gen0_cl48RxEEEStates_l_RX_WAKE 16 4491 #define tx_x4_credit_gen0_cl48RxEEEStates_l_RX_QUIET 8 4492 #define tx_x4_credit_gen0_cl48RxEEEStates_l_RX_DEACT 4 4493 #define tx_x4_credit_gen0_cl48RxEEEStates_l_RX_SLEEP 2 4494 #define tx_x4_credit_gen0_cl48RxEEEStates_l_RX_ACTIVE 1 4495 4496 /**************************************************************************** 4497 * Enums: tx_x4_credit_gen0_cl48RxEEEStates_c 4498 */ 4499 #define tx_x4_credit_gen0_cl48RxEEEStates_c_RX_LINK_FAIL 5 4500 #define tx_x4_credit_gen0_cl48RxEEEStates_c_RX_WAKE 4 4501 #define tx_x4_credit_gen0_cl48RxEEEStates_c_RX_QUIET 3 4502 #define tx_x4_credit_gen0_cl48RxEEEStates_c_RX_DEACT 2 4503 #define tx_x4_credit_gen0_cl48RxEEEStates_c_RX_SLEEP 1 4504 #define tx_x4_credit_gen0_cl48RxEEEStates_c_RX_ACTIVE 0 4505 4506 /**************************************************************************** 4507 * Enums: tx_x4_credit_gen0_IQP_Options 4508 */ 4509 #define tx_x4_credit_gen0_IQP_Options_i50uA 0 4510 #define tx_x4_credit_gen0_IQP_Options_i100uA 1 4511 #define tx_x4_credit_gen0_IQP_Options_i150uA 2 4512 #define tx_x4_credit_gen0_IQP_Options_i200uA 3 4513 #define tx_x4_credit_gen0_IQP_Options_i250uA 4 4514 #define tx_x4_credit_gen0_IQP_Options_i300uA 5 4515 #define tx_x4_credit_gen0_IQP_Options_i350uA 6 4516 #define tx_x4_credit_gen0_IQP_Options_i400uA 7 4517 #define tx_x4_credit_gen0_IQP_Options_i450uA 8 4518 #define tx_x4_credit_gen0_IQP_Options_i500uA 9 4519 #define tx_x4_credit_gen0_IQP_Options_i550uA 10 4520 #define tx_x4_credit_gen0_IQP_Options_i600uA 11 4521 #define tx_x4_credit_gen0_IQP_Options_i650uA 12 4522 #define tx_x4_credit_gen0_IQP_Options_i700uA 13 4523 #define tx_x4_credit_gen0_IQP_Options_i750uA 14 4524 #define tx_x4_credit_gen0_IQP_Options_i800uA 15 4525 4526 /**************************************************************************** 4527 * Enums: tx_x4_credit_gen0_IDriver_Options 4528 */ 4529 #define tx_x4_credit_gen0_IDriver_Options_v680mV 0 4530 #define tx_x4_credit_gen0_IDriver_Options_v730mV 1 4531 #define tx_x4_credit_gen0_IDriver_Options_v780mV 2 4532 #define tx_x4_credit_gen0_IDriver_Options_v830mV 3 4533 #define tx_x4_credit_gen0_IDriver_Options_v880mV 4 4534 #define tx_x4_credit_gen0_IDriver_Options_v930mV 5 4535 #define tx_x4_credit_gen0_IDriver_Options_v980mV 6 4536 #define tx_x4_credit_gen0_IDriver_Options_v1010mV 7 4537 #define tx_x4_credit_gen0_IDriver_Options_v1040mV 8 4538 #define tx_x4_credit_gen0_IDriver_Options_v1060mV 9 4539 #define tx_x4_credit_gen0_IDriver_Options_v1070mV 10 4540 #define tx_x4_credit_gen0_IDriver_Options_v1080mV 11 4541 #define tx_x4_credit_gen0_IDriver_Options_v1085mV 12 4542 #define tx_x4_credit_gen0_IDriver_Options_v1090mV 13 4543 #define tx_x4_credit_gen0_IDriver_Options_v1095mV 14 4544 #define tx_x4_credit_gen0_IDriver_Options_v1100mV 15 4545 4546 /**************************************************************************** 4547 * Enums: tx_x4_credit_gen0_operationModes 4548 */ 4549 #define tx_x4_credit_gen0_operationModes_XGXS 0 4550 #define tx_x4_credit_gen0_operationModes_XGXG_nCC 1 4551 #define tx_x4_credit_gen0_operationModes_Indlane_OS8 4 4552 #define tx_x4_credit_gen0_operationModes_IndLane_OS5 5 4553 #define tx_x4_credit_gen0_operationModes_PCI 7 4554 #define tx_x4_credit_gen0_operationModes_XGXS_nLQ 8 4555 #define tx_x4_credit_gen0_operationModes_XGXS_nLQnCC 9 4556 #define tx_x4_credit_gen0_operationModes_PBypass 10 4557 #define tx_x4_credit_gen0_operationModes_PBypass_nDSK 11 4558 #define tx_x4_credit_gen0_operationModes_ComboCoreMode 12 4559 #define tx_x4_credit_gen0_operationModes_Clocks_off 15 4560 4561 /**************************************************************************** 4562 * Enums: tx_x4_credit_gen0_synce_enum 4563 */ 4564 #define tx_x4_credit_gen0_synce_enum_SYNCE_NO_DIV 0 4565 #define tx_x4_credit_gen0_synce_enum_SYNCE_DIV_7 1 4566 #define tx_x4_credit_gen0_synce_enum_SYNCE_DIV_11 2 4567 4568 /**************************************************************************** 4569 * Enums: tx_x4_credit_gen0_operationSpeeds 4570 */ 4571 #define tx_x4_credit_gen0_operationSpeeds_SPEED_2p5G_X1_10p3125 56 4572 #define tx_x4_credit_gen0_operationSpeeds_SPEED_1000M_10p3125 55 4573 #define tx_x4_credit_gen0_operationSpeeds_SPEED_100M_10p3125 54 4574 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10M_10p3125 53 4575 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10p5G_X4 50 4576 #define tx_x4_credit_gen0_operationSpeeds_SPEED_5G_KR1 49 4577 #define tx_x4_credit_gen0_operationSpeeds_SPEED_127G_X12 39 4578 #define tx_x4_credit_gen0_operationSpeeds_SPEED_120G_X12 38 4579 #define tx_x4_credit_gen0_operationSpeeds_SPEED_107G_X10 37 4580 #define tx_x4_credit_gen0_operationSpeeds_SPEED_100G_CR10 36 4581 #define tx_x4_credit_gen0_operationSpeeds_SPEED_42G_X4 35 4582 #define tx_x4_credit_gen0_operationSpeeds_SPEED_40G_CR4 34 4583 #define tx_x4_credit_gen0_operationSpeeds_SPEED_40G_KR4 33 4584 #define tx_x4_credit_gen0_operationSpeeds_SPEED_21G_X2 32 4585 #define tx_x4_credit_gen0_operationSpeeds_SPEED_20G_CR2 31 4586 #define tx_x4_credit_gen0_operationSpeeds_SPEED_20G_KR2 30 4587 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10p6_X1 29 4588 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10G_KR1 28 4589 #define tx_x4_credit_gen0_operationSpeeds_SPEED_40G_X4 27 4590 #define tx_x4_credit_gen0_operationSpeeds_SPEED_20G_X2 26 4591 #define tx_x4_credit_gen0_operationSpeeds_SPEED_20G_CX2 25 4592 #define tx_x4_credit_gen0_operationSpeeds_SPEED_31p5G_KR4 24 4593 #define tx_x4_credit_gen0_operationSpeeds_SPEED_31p5G_X4 23 4594 #define tx_x4_credit_gen0_operationSpeeds_SPEED_15p75G_X2 22 4595 #define tx_x4_credit_gen0_operationSpeeds_SPEED_25p45G_X4 21 4596 #define tx_x4_credit_gen0_operationSpeeds_SPEED_12p7G_X2 20 4597 #define tx_x4_credit_gen0_operationSpeeds_SPEED_21G_X4 19 4598 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10p5G_X2 18 4599 #define tx_x4_credit_gen0_operationSpeeds_SPEED_20G_X4 17 4600 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10G_X2 16 4601 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10G_CX2 15 4602 #define tx_x4_credit_gen0_operationSpeeds_SPEED_20G_CX4 14 4603 #define tx_x4_credit_gen0_operationSpeeds_SPEED_16G_X4 13 4604 #define tx_x4_credit_gen0_operationSpeeds_SPEED_15G_X4 12 4605 #define tx_x4_credit_gen0_operationSpeeds_SPEED_13G_X4 11 4606 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10G_X4 10 4607 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10G_KX4 9 4608 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10G_CX4 8 4609 #define tx_x4_credit_gen0_operationSpeeds_SPEED_5G_X1 7 4610 #define tx_x4_credit_gen0_operationSpeeds_SPEED_2p5G_X1 6 4611 #define tx_x4_credit_gen0_operationSpeeds_SPEED_1G_KX1 5 4612 #define tx_x4_credit_gen0_operationSpeeds_SPEED_1G_CX1 4 4613 #define tx_x4_credit_gen0_operationSpeeds_SPEED_1000M 3 4614 #define tx_x4_credit_gen0_operationSpeeds_SPEED_100M 2 4615 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10M 1 4616 4617 /**************************************************************************** 4618 * Enums: tx_x4_credit_gen0_actualSpeeds 4619 */ 4620 #define tx_x4_credit_gen0_actualSpeeds_dr_10M 0 4621 #define tx_x4_credit_gen0_actualSpeeds_dr_100M 1 4622 #define tx_x4_credit_gen0_actualSpeeds_dr_1G 2 4623 #define tx_x4_credit_gen0_actualSpeeds_dr_2p5G 3 4624 #define tx_x4_credit_gen0_actualSpeeds_dr_5G_X4 4 4625 #define tx_x4_credit_gen0_actualSpeeds_dr_6G_X4 5 4626 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_HiG 6 4627 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_CX4 7 4628 #define tx_x4_credit_gen0_actualSpeeds_dr_12G_HiG 8 4629 #define tx_x4_credit_gen0_actualSpeeds_dr_12p5G_X4 9 4630 #define tx_x4_credit_gen0_actualSpeeds_dr_13G_X4 10 4631 #define tx_x4_credit_gen0_actualSpeeds_dr_15G_X4 11 4632 #define tx_x4_credit_gen0_actualSpeeds_dr_16G_X4 12 4633 #define tx_x4_credit_gen0_actualSpeeds_dr_1G_KX 13 4634 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_KX4 14 4635 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_KR 15 4636 #define tx_x4_credit_gen0_actualSpeeds_dr_5G 16 4637 #define tx_x4_credit_gen0_actualSpeeds_dr_6p4G 17 4638 #define tx_x4_credit_gen0_actualSpeeds_dr_20G_X4 18 4639 #define tx_x4_credit_gen0_actualSpeeds_dr_21G_X4 19 4640 #define tx_x4_credit_gen0_actualSpeeds_dr_25G_X4 20 4641 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_HiG_DXGXS 21 4642 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_DXGXS 22 4643 #define tx_x4_credit_gen0_actualSpeeds_dr_10p5G_HiG_DXGXS 23 4644 #define tx_x4_credit_gen0_actualSpeeds_dr_10p5G_DXGXS 24 4645 #define tx_x4_credit_gen0_actualSpeeds_dr_12p773G_HiG_DXGXS 25 4646 #define tx_x4_credit_gen0_actualSpeeds_dr_12p773G_DXGXS 26 4647 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_XFI 27 4648 #define tx_x4_credit_gen0_actualSpeeds_dr_40G 28 4649 #define tx_x4_credit_gen0_actualSpeeds_dr_20G_HiG_DXGXS 29 4650 #define tx_x4_credit_gen0_actualSpeeds_dr_20G_DXGXS 30 4651 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_SFI 31 4652 #define tx_x4_credit_gen0_actualSpeeds_dr_31p5G 32 4653 #define tx_x4_credit_gen0_actualSpeeds_dr_32p7G 33 4654 #define tx_x4_credit_gen0_actualSpeeds_dr_20G_SCR 34 4655 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 4656 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_DXGXS_SCR 36 4657 #define tx_x4_credit_gen0_actualSpeeds_dr_12G_R2 37 4658 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_X2 38 4659 #define tx_x4_credit_gen0_actualSpeeds_dr_40G_KR4 39 4660 #define tx_x4_credit_gen0_actualSpeeds_dr_40G_CR4 40 4661 #define tx_x4_credit_gen0_actualSpeeds_dr_100G_CR10 41 4662 #define tx_x4_credit_gen0_actualSpeeds_dr_15p75G_DXGXS 44 4663 #define tx_x4_credit_gen0_actualSpeeds_dr_20G_KR2 57 4664 #define tx_x4_credit_gen0_actualSpeeds_dr_20G_CR2 58 4665 4666 /**************************************************************************** 4667 * Enums: tx_x4_credit_gen0_actualSpeedsMisc1 4668 */ 4669 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_2500BRCM_X1 16 4670 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_5000BRCM_X4 17 4671 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_6000BRCM_X4 18 4672 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_10GHiGig_X4 19 4673 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_10GBASE_CX4 20 4674 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_12GHiGig_X4 21 4675 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 4676 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_13GHiGig_X4 23 4677 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_15GHiGig_X4 24 4678 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_16GHiGig_X4 25 4679 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_5000BRCM_X1 26 4680 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_6363BRCM_X1 27 4681 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_20GHiGig_X4 28 4682 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_21GHiGig_X4 29 4683 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 4684 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 4685 4686 /**************************************************************************** 4687 * Enums: tx_x4_credit_gen0_IndLaneModes 4688 */ 4689 #define tx_x4_credit_gen0_IndLaneModes_SWSDR_div2 0 4690 #define tx_x4_credit_gen0_IndLaneModes_SWSDR_div1 1 4691 #define tx_x4_credit_gen0_IndLaneModes_DWSDR_div2 2 4692 #define tx_x4_credit_gen0_IndLaneModes_DWSDR_div1 3 4693 4694 /**************************************************************************** 4695 * Enums: tx_x4_credit_gen0_prbsSelect 4696 */ 4697 #define tx_x4_credit_gen0_prbsSelect_prbs7 0 4698 #define tx_x4_credit_gen0_prbsSelect_prbs15 1 4699 #define tx_x4_credit_gen0_prbsSelect_prbs23 2 4700 #define tx_x4_credit_gen0_prbsSelect_prbs31 3 4701 4702 /**************************************************************************** 4703 * Enums: tx_x4_credit_gen0_vcoDivider 4704 */ 4705 #define tx_x4_credit_gen0_vcoDivider_div32 0 4706 #define tx_x4_credit_gen0_vcoDivider_div36 1 4707 #define tx_x4_credit_gen0_vcoDivider_div40 2 4708 #define tx_x4_credit_gen0_vcoDivider_div42 3 4709 #define tx_x4_credit_gen0_vcoDivider_div48 4 4710 #define tx_x4_credit_gen0_vcoDivider_div50 5 4711 #define tx_x4_credit_gen0_vcoDivider_div52 6 4712 #define tx_x4_credit_gen0_vcoDivider_div54 7 4713 #define tx_x4_credit_gen0_vcoDivider_div60 8 4714 #define tx_x4_credit_gen0_vcoDivider_div64 9 4715 #define tx_x4_credit_gen0_vcoDivider_div66 10 4716 #define tx_x4_credit_gen0_vcoDivider_div68 11 4717 #define tx_x4_credit_gen0_vcoDivider_div70 12 4718 #define tx_x4_credit_gen0_vcoDivider_div80 13 4719 #define tx_x4_credit_gen0_vcoDivider_div92 14 4720 #define tx_x4_credit_gen0_vcoDivider_div100 15 4721 4722 /**************************************************************************** 4723 * Enums: tx_x4_credit_gen0_refClkSelect 4724 */ 4725 #define tx_x4_credit_gen0_refClkSelect_clk_25MHz 0 4726 #define tx_x4_credit_gen0_refClkSelect_clk_100MHz 1 4727 #define tx_x4_credit_gen0_refClkSelect_clk_125MHz 2 4728 #define tx_x4_credit_gen0_refClkSelect_clk_156p25MHz 3 4729 #define tx_x4_credit_gen0_refClkSelect_clk_187p5MHz 4 4730 #define tx_x4_credit_gen0_refClkSelect_clk_161p25Mhz 5 4731 #define tx_x4_credit_gen0_refClkSelect_clk_50Mhz 6 4732 #define tx_x4_credit_gen0_refClkSelect_clk_106p25Mhz 7 4733 4734 /**************************************************************************** 4735 * Enums: tx_x4_credit_gen0_aerMMDdevTypeSelect 4736 */ 4737 #define tx_x4_credit_gen0_aerMMDdevTypeSelect_combo_core 0 4738 #define tx_x4_credit_gen0_aerMMDdevTypeSelect_PMA_PMD 1 4739 #define tx_x4_credit_gen0_aerMMDdevTypeSelect_PCS 3 4740 #define tx_x4_credit_gen0_aerMMDdevTypeSelect_PHY 4 4741 #define tx_x4_credit_gen0_aerMMDdevTypeSelect_DTE 5 4742 #define tx_x4_credit_gen0_aerMMDdevTypeSelect_CL73_AN 7 4743 4744 /**************************************************************************** 4745 * Enums: tx_x4_credit_gen0_aerMMDportSelect 4746 */ 4747 #define tx_x4_credit_gen0_aerMMDportSelect_ln0 0 4748 #define tx_x4_credit_gen0_aerMMDportSelect_ln1 1 4749 #define tx_x4_credit_gen0_aerMMDportSelect_ln2 2 4750 #define tx_x4_credit_gen0_aerMMDportSelect_ln3 3 4751 #define tx_x4_credit_gen0_aerMMDportSelect_BCST_ln0_1_2_3 511 4752 #define tx_x4_credit_gen0_aerMMDportSelect_BCST_ln0_1 512 4753 #define tx_x4_credit_gen0_aerMMDportSelect_BCST_ln2_3 513 4754 4755 /**************************************************************************** 4756 * Enums: tx_x4_credit_gen0_firmwareModeSelect 4757 */ 4758 #define tx_x4_credit_gen0_firmwareModeSelect_DEFAULT 0 4759 #define tx_x4_credit_gen0_firmwareModeSelect_SFP_OPT_LR 1 4760 #define tx_x4_credit_gen0_firmwareModeSelect_SFP_DAC 2 4761 #define tx_x4_credit_gen0_firmwareModeSelect_XLAUI 3 4762 #define tx_x4_credit_gen0_firmwareModeSelect_LONG_CH_6G 4 4763 4764 /**************************************************************************** 4765 * Enums: tx_x4_credit_gen0_tempIdxSelect 4766 */ 4767 #define tx_x4_credit_gen0_tempIdxSelect_LTE__22p9C 15 4768 #define tx_x4_credit_gen0_tempIdxSelect_LTE__12p6C 14 4769 #define tx_x4_credit_gen0_tempIdxSelect_LTE__3p0C 13 4770 #define tx_x4_credit_gen0_tempIdxSelect_LTE_6p7C 12 4771 #define tx_x4_credit_gen0_tempIdxSelect_LTE_16p4C 11 4772 #define tx_x4_credit_gen0_tempIdxSelect_LTE_26p6C 10 4773 #define tx_x4_credit_gen0_tempIdxSelect_LTE_36p3C 9 4774 #define tx_x4_credit_gen0_tempIdxSelect_LTE_46p0C 8 4775 #define tx_x4_credit_gen0_tempIdxSelect_LTE_56p2C 7 4776 #define tx_x4_credit_gen0_tempIdxSelect_LTE_65p9C 6 4777 #define tx_x4_credit_gen0_tempIdxSelect_LTE_75p6C 5 4778 #define tx_x4_credit_gen0_tempIdxSelect_LTE_85p3C 4 4779 #define tx_x4_credit_gen0_tempIdxSelect_LTE_95p5C 3 4780 #define tx_x4_credit_gen0_tempIdxSelect_LTE_105p2C 2 4781 #define tx_x4_credit_gen0_tempIdxSelect_LTE_114p9C 1 4782 #define tx_x4_credit_gen0_tempIdxSelect_LTE_125p1C 0 4783 4784 /**************************************************************************** 4785 * End of RDB defined Enums *******************************************/ 4786 #endif /* __PCS_ENUMS_H__ */