sc_field_defines.h (8711B)
1 /*---------------------------------------------------------------------- 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * Broadcom Corporation 8 * Proprietary and Confidential information 9 * All rights reserved 10 * This source file is the property of Broadcom Corporation, and 11 * may not be copied or distributed in any isomorphic form without the 12 * prior written consent of Broadcom Corporation. 13 *--------------------------------------------------------------------- 14 * File : sc_field_defines.h 15 * Description: 16 *---------------------------------------------------------------------*/ 17 18 /*############################################################################## 19 ############################################################################# */ 20 #define TEMOD_PLL_MODE_DIV_40 2 21 #define TEMOD_PLL_MODE_DIV_42 3 22 #define TEMOD_PLL_MODE_DIV_48 4 23 #define TEMOD_PLL_MODE_DIV_50 5 24 #define TEMOD_PLL_MODE_DIV_52 6 25 #define TEMOD_PLL_MODE_DIV_54 7 26 #define TEMOD_PLL_MODE_DIV_60 8 27 #define TEMOD_PLL_MODE_DIV_64 9 28 #define TEMOD_PLL_MODE_DIV_66 10 29 #define TEMOD_PLL_MODE_DIV_68 11 30 #define TEMOD_PLL_MODE_DIV_70 12 31 #define TEMOD_PLL_MODE_DIV_80 13 32 #define TEMOD_PLL_MODE_DIV_92 14 33 #define TEMOD_PLL_MODE_DIV_100 15 34 #define TEMOD_PLL_MODE_DIV_82P5 16 35 #define TEMOD_PLL_MODE_DIV_87P5 17 36 #define TEMOD_PLL_MODE_ILLEGAL 0 37 38 39 /*############################################################################# */ 40 #define TEMOD_SCR_MODE_BYPASS 0 41 #define TEMOD_SCR_MODE_66B 1 42 #define TEMOD_SCR_MODE_80B 2 43 #define TEMOD_SCR_MODE_64B 3 44 45 /*############################################################################# */ 46 #define TEMOD_ENCODE_MODE_NONE 0 47 #define TEMOD_ENCODE_MODE_CL48 1 48 #define TEMOD_ENCODE_MODE_CL48_2_LANE 2 49 #define TEMOD_ENCODE_MODE_CL36 3 50 #define TEMOD_ENCODE_MODE_CL82 4 51 #define TEMOD_ENCODE_MODE_CL49 5 52 #define TEMOD_ENCODE_MODE_BRCM 6 53 #define TEMOD_ENCODE_MODE_ILLEGAL 7 54 55 56 /*############################################################################# */ 57 #define TEMOD_CL48_CHECK_END_OFF 0 58 #define TEMOD_CL48_CHECK_END_ON 1 59 60 /*############################################################################# */ 61 #define TEMOD_SIGDET_FILTER_NONCX4 0 62 #define TEMOD_SIGDET_FILTER_CX4 1 63 64 /*############################################################################# */ 65 #define TEMOD_BLOCKSYNC_MODE_NONE 0 66 #define TEMOD_BLOCKSYNC_MODE_CL49 1 67 #define TEMOD_BLOCKSYNC_MODE_CL82 2 68 #define TEMOD_BLOCKSYNC_MODE_8B10B 3 69 #define TEMOD_BLOCKSYNC_MODE_FEC 4 70 #define TEMOD_BLOCKSYNC_MODE_BRCM 5 71 #define TEMOD_BLOCKSYNC_MODE_ILLEGAL 7 72 73 /*############################################################################# */ 74 #define TEMOD_R_REORDER_MODE_NONE 0 75 #define TEMOD_R_REORDER_MODE_CL48 1 76 #define TEMOD_R_REORDER_MODE_CL36 2 77 #define TEMOD_R_REORDER_MODE_CL36_CL48 3 78 79 /*############################################################################# */ 80 #define TEMOD_CL36_DISABLE 0 81 #define TEMOD_CL36_ENABLE 1 82 83 /*############################################################################# */ 84 #define TEMOD_R_DESCR1_MODE_BYPASS 0 85 #define TEMOD_R_DESCR1_MODE_66B 1 86 #define TEMOD_R_DESCR1_MODE_10B 2 87 #define TEMOD_R_DESCR1_MODE_ILLEGAL 3 88 89 90 /*############################################################################# */ 91 #define TEMOD_DECODER_MODE_NONE 0 92 #define TEMOD_DECODER_MODE_CL49 1 93 #define TEMOD_DECODER_MODE_BRCM 2 94 #define TEMOD_DECODER_MODE_ALU 3 95 #define TEMOD_DECODER_MODE_CL48 4 96 #define TEMOD_DECODER_MODE_CL36 5 97 #define TEMOD_DECODER_MODE_CL82 6 98 #define TEMOD_DECODER_MODE_ILLEGAL 7 99 100 /*############################################################################# */ 101 #define TEMOD_R_DESKEW_MODE_BYPASS 0 102 #define TEMOD_R_DESKEW_MODE_8B_10B 1 103 #define TEMOD_R_DESKEW_MODE_BRCM_66B 2 104 #define TEMOD_R_DESKEW_MODE_CL82_66B 3 105 #define TEMOD_R_DESKEW_MODE_CL36_10B 4 106 #define TEMOD_R_DESKEW_MODE_ILLEGAL 7 107 108 /*#############################################################################*/ 109 #define TEMOD_DESC2_MODE_NONE 0 110 #define TEMOD_DESC2_MODE_CL49 1 111 #define TEMOD_DESC2_MODE_BRCM 2 112 #define TEMOD_DESC2_MODE_ALU 3 113 #define TEMOD_DESC2_MODE_CL48 4 114 #define TEMOD_DESC2_MODE_CL36 5 115 #define TEMOD_DESC2_MODE_CL82 6 116 #define TEMOD_DESC2_MODE_ILLEGAL 7 117 118 119 /*#############################################################################*/ 120 121 #define TEMOD_R_DESC2_BYTE_DELETION_100M 0 122 #define TEMOD_R_DESC2_BYTE_DELETION_10M 1 123 #define TEMOD_R_DESC2_BYTE_DELETION_NONE 2 124 125 /*############################################################################*/ 126 127 #define TEMOD_R_DEC1_DESCR_MODE_NONE 0 128 #define TEMOD_R_DEC1_DESCR_MODE_BRCM64B66B 1 129 130 /*#############################################################################*/ 131 132 #define RTL_SPEED_100G_CR10 0x29 133 #define RTL_SPEED_40G_CR4 0x28 134 #define RTL_SPEED_40G_KR4 0x27 135 #define RTL_SPEED_40G_X4 0x1C 136 #define RTL_SPEED_32p7G_X4 0x21 137 #define RTL_SPEED_31p5G_X4 0x20 138 #define RTL_SPEED_25p45G_X4 0x14 139 #define RTL_SPEED_21G_X4 0x13 140 #define RTL_SPEED_20G_CR2 0x3A 141 #define RTL_SPEED_20G_KR2 0x39 142 #define RTL_SPEED_20G_X2 0x1D 143 #define RTL_SPEED_20G_X4 0x22 144 #define RTL_SPEED_20G_CX2 0x1E 145 #define RTL_SPEED_20G_CX4 0x12 146 #define RTL_SPEED_16G_X4 0x0C 147 #define RTL_SPEED_15p75G_X2 0x2C 148 #define RTL_SPEED_15G_X4 0x0B 149 #define RTL_SPEED_13G_X4 0x0A 150 #define RTL_SPEED_12p7G_X2 0x19 151 #define RTL_SPEED_12p5G_X4 0x09 152 #define RTL_SPEED_12G_X4 0x08 153 #define RTL_SPEED_10p5G_X2 0x17 154 #define RTL_SPEED_10G_KR1 0x0F 155 #define RTL_SPEED_10G_CX2 0x24 156 #define RTL_SPEED_10G_X2 0x23 157 #define RTL_SPEED_10G_KX4 0x0E 158 #define RTL_SPEED_10G_CX4 0x07 159 #define RTL_SPEED_10G_X4 0x06 160 #define RTL_SPEED_10G_CX1 0x33 161 #define RTL_SPEED_6G_X4 0x05 162 #define RTL_SPEED_5G_X4 0x04 163 #define RTL_SPEED_5G_X2 0x2A 164 #define RTL_SPEED_2p5G_X1 0x03 165 #define RTL_SPEED_1G_KX1 0x0D 166 #define RTL_SPEED_1000M 0x02 167 #define RTL_SPEED_1G_CX1 0x34 168 #define RTL_SPEED_100M 0x01 169 #define RTL_SPEED_10M 0x00 170 #define RTL_SPEED_5G_X1 0x10 171 #define RTL_SPEED_6p36G_X1 0x11 172 #define RTL_SPEED_10G_X2_NOSCRAMBLE 0x15 173 #define RTL_SPEED_10G_CX2_NOSCRAMBLE 0x16 174 #define RTL_SPEED_10p5G_CX2_NOSCRAMBLE 0x18 175 #define RTL_SPEED_12p7G_CX2 0x1A 176 #define RTL_SPEED_10G_X1 0x1B 177 #define RTL_SPEED_10G_SFI 0x1F 178 #define RTL_SPEED_3p125G_IL 0x3C 179 #define RTL_SPEED_6p25_IL 0x3D 180 #define RTL_SPEED_10p31G_IL 0x3E 181 #define RTL_SPEED_10p96G_IL 0x3F 182 #define RTL_SPEED_12p5G_IL 0x40 183 #define RTL_SPEED_11p5G_IL 0x41 184 #define RTL_SPEED_1p25G_IL 0x42 185 #define RTL_SPEED_2G_FC 0x2E 186 #define RTL_SPEED_4G_FC 0x2F 187 #define RTL_SPEED_8G_FC 0x30 188 #define RTL_SPEED_1G_CL73 0x3B 189 #define RTL_SPEED_1000M_SGMII 0x2D 190 #define RTL_SPEED_NONE 0x2B 191 192 193 /*#############################################################################*/