tbhPCSRegEnums.h (1323195B)
1 /**************************************************************************** 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * 8 * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE 9 * AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR 10 * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT. 11 * 12 * $brcm_Workfile: $ 13 * $brcm_Revision: $ 14 * $brcm_Date: $ 15 * 16 * Module Description: 17 * DO NOT EDIT THIS FILE DIRECTLY 18 * 19 * This module was generated magically with RDB from a source description 20 * file. You must edit the source file for changes to be made to this file. 21 * 22 * 23 * Date: Generated on Tue Jan 31 10:55:48 2017 24 * MD5 Checksum 463c5df2ea6edf9e4be8433dc1a4412a 25 * 26 * Compiled with: RDB Utility 5.0 27 * RDB Parser 3.0 28 * rdb2macro.pm 4.0 29 * Perl Interpreter 5.014001 30 * Operating System linux 31 * 32 * Spec Versions: an_x1_control 1 33 * an_x1_sw_mgmt 1 34 * an_x1_timers 1 35 * an_x4_abilities 1 36 * an_x4_status 1 37 * an_x4_sw_mgmt 1 38 * cl82 1 39 * ieee0_cl22 1 40 * ilkn_x4_control0 1 41 * ilkn_x4_status0 1 42 * main0 1 43 * pmd_x1 1 44 * pmd_x4 1 45 * rx_x1_control0 1 46 * rx_x1_ecc 1 47 * rx_x1_status0 1 48 * rx_x2_control0 1 49 * rx_x2_status0 1 50 * rx_x4_control0 1 51 * rx_x4_ecc 1 52 * rx_x4_fec_control 1 53 * rx_x4_rs_fec_status0 1 54 * rx_x4_rs_fec_status1 1 55 * rx_x4_status0 1 56 * rx_x4_status1 1 57 * rx_x4_status2 1 58 * rx_x4_status3 1 59 * rx_x4_status4 1 60 * rx_x4_status5 1 61 * rx_x4_test_status0 1 62 * sc_x1_control 1 63 * sc_x4_control 1 64 * sc_x4_final_config_status1 65 * synce_x4 1 66 * testshared0 1 67 * testshared1 1 68 * tx_x1_control0 1 69 * tx_x2_control0 1 70 * tx_x2_status0 1 71 * tx_x4_control0 1 72 * tx_x4_status0 1 73 * 74 * RDB Files: /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/WC4_TSC_ALL.rdb 75 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/ieee0_cl22_regs.rdb 76 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/testshared0_regs.rdb 77 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/enum_inc.rdb 78 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/testshared1_regs.rdb 79 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/main0_regs.rdb 80 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/enum_inc.rdb 81 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/rx_x1_control0_regs.rdb 82 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/rx_x1_ecc_regs.rdb 83 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/rx_x1_status0_regs.rdb 84 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/enum_inc.rdb 85 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/pmd_x1_regs.rdb 86 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/pmd_x4_regs.rdb 87 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/an_x1_control_regs.rdb 88 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/an_x4_abilities_regs.rdb 89 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/enum_inc.rdb 90 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/an_x1_timers_regs.rdb 91 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/an_x4_status_regs.rdb 92 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/an_x4_sw_mgmt_regs.rdb 93 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/an_x1_sw_mgmt_regs.rdb 94 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/cl82_user_regs.rdb 95 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/enum_inc.rdb 96 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/tx_x2_control0_regs.rdb 97 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/enum_inc.rdb 98 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/tx_x2_status0_regs.rdb 99 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/enum_inc.rdb 100 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/rx_x2_control0_regs.rdb 101 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/rx_x2_status0_regs.rdb 102 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/enum_inc.rdb 103 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/tx_x4_control0_regs.rdb 104 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/enum_inc.rdb 105 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/tx_x4_status0_regs.rdb 106 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/enum_inc.rdb 107 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/synce_x4_regs.rdb 108 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/enum_inc.rdb 109 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/rx_x4_control0_regs.rdb 110 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/enum_inc.rdb 111 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/rx_x4_fec_control_regs.rdb 112 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/enum_inc.rdb 113 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/rx_x4_status0_regs.rdb 114 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/rx_x4_test_status0_regs.rdb 115 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/rx_x4_status1_regs.rdb 116 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/enum_inc.rdb 117 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/rx_x4_status2_regs.rdb 118 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/enum_inc.rdb 119 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/rx_x4_status3_regs.rdb 120 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/enum_inc.rdb 121 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/rx_x4_status4_regs.rdb 122 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/enum_inc.rdb 123 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/rx_x4_status5_regs.rdb 124 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/enum_inc.rdb 125 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/rx_x4_rs_fec_status0_regs.rdb 126 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/enum_inc.rdb 127 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/rx_x4_rs_fec_status1_regs.rdb 128 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/enum_inc.rdb 129 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/tx_x1_control0_regs.rdb 130 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/ilkn_x4_control0_regs.rdb 131 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/ilkn_x4_status0_regs.rdb 132 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/rx_x4_ecc_regs.rdb 133 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/sc_x4_control_regs.rdb 134 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/enum_inc.rdb 135 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/sc_x1_control_regs.rdb 136 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/sc_x4_final_config_status_regs.rdb 137 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/sc_x1_speed_override_common.rdb 138 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/enum_inc.rdb 139 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/WC4_ieeeBlockCL22.rdb 140 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/WC4_userBlocks1.rdb 141 * /projects/TSC_ext10/amarachi/tsc400g/tscbh/rtl/rdb/WC4_userBlocks4.rdb 142 * 143 * Revision History: 144 * 145 * $brcm_Log: $ 146 */ 147 148 #ifndef TEF_TMP__ 149 #define TEF_TMP__ 150 151 /** 152 * m = memory, c = core, r = register, f = field, d = data. 153 */ 154 #if !defined(GET_FIELD) && !defined(SET_FIELD) 155 #define BRCM_ALIGN(c,r,f) c##_##r##_##f##_ALIGN 156 #define BRCM_BITS(c,r,f) c##_##r##_##f##_BITS 157 #define BRCM_MASK(c,r,f) c##_##r##_##f##_MASK 158 #define BRCM_SHIFT(c,r,f) c##_##r##_##f##_SHIFT 159 160 #define GET_FIELD(m,c,r,f) \ 161 ((((m) & BRCM_MASK(c,r,f)) >> BRCM_SHIFT(c,r,f)) << BRCM_ALIGN(c,r,f)) 162 163 #define SET_FIELD(m,c,r,f,d) \ 164 ((m) = (((m) & ~BRCM_MASK(c,r,f)) | ((((d) >> BRCM_ALIGN(c,r,f)) << \ 165 BRCM_SHIFT(c,r,f)) & BRCM_MASK(c,r,f))) \ 166 ) 167 168 #define SET_TYPE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##d) 169 #define SET_NAME_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##r##_##f##_##d) 170 #define SET_VALUE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,d) 171 172 #endif /* GET & SET */ 173 174 /**************************************************************************** 175 * Core Enums. 176 */ 177 /**************************************************************************** 178 * Enums: an_x4_abilities_cl36TxEEEStates_l 179 */ 180 #define an_x4_abilities_cl36TxEEEStates_l_TX_REFRESH 8 181 #define an_x4_abilities_cl36TxEEEStates_l_TX_QUIET 4 182 #define an_x4_abilities_cl36TxEEEStates_l_TX_SLEEP 2 183 #define an_x4_abilities_cl36TxEEEStates_l_TX_ACTIVE 1 184 185 /**************************************************************************** 186 * Enums: an_x4_abilities_cl36TxEEEStates_c 187 */ 188 #define an_x4_abilities_cl36TxEEEStates_c_TX_REFRESH 3 189 #define an_x4_abilities_cl36TxEEEStates_c_TX_QUIET 2 190 #define an_x4_abilities_cl36TxEEEStates_c_TX_SLEEP 1 191 #define an_x4_abilities_cl36TxEEEStates_c_TX_ACTIVE 0 192 193 /**************************************************************************** 194 * Enums: an_x4_abilities_cl49TxEEEStates_l 195 */ 196 #define an_x4_abilities_cl49TxEEEStates_l_SCR_RESET_2 64 197 #define an_x4_abilities_cl49TxEEEStates_l_SCR_RESET_1 32 198 #define an_x4_abilities_cl49TxEEEStates_l_TX_WAKE 16 199 #define an_x4_abilities_cl49TxEEEStates_l_TX_REFRESH 8 200 #define an_x4_abilities_cl49TxEEEStates_l_TX_QUIET 4 201 #define an_x4_abilities_cl49TxEEEStates_l_TX_SLEEP 2 202 #define an_x4_abilities_cl49TxEEEStates_l_TX_ACTIVE 1 203 204 /**************************************************************************** 205 * Enums: an_x4_abilities_fec_req_enum 206 */ 207 #define an_x4_abilities_fec_req_enum_FEC_not_supported 0 208 #define an_x4_abilities_fec_req_enum_FEC_supported_but_not_requested 1 209 #define an_x4_abilities_fec_req_enum_invalid_setting 2 210 #define an_x4_abilities_fec_req_enum_FEC_supported_and_requested 3 211 212 /**************************************************************************** 213 * Enums: an_x4_abilities_cl73_pause_enum 214 */ 215 #define an_x4_abilities_cl73_pause_enum_No_PAUSE_ability 0 216 #define an_x4_abilities_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 217 #define an_x4_abilities_cl73_pause_enum_Symmetric_PAUSE_ability 1 218 #define an_x4_abilities_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 219 220 /**************************************************************************** 221 * Enums: an_x4_abilities_cl49TxEEEStates_c 222 */ 223 #define an_x4_abilities_cl49TxEEEStates_c_SCR_RESET_2 6 224 #define an_x4_abilities_cl49TxEEEStates_c_SCR_RESET_1 5 225 #define an_x4_abilities_cl49TxEEEStates_c_TX_WAKE 4 226 #define an_x4_abilities_cl49TxEEEStates_c_TX_REFRESH 3 227 #define an_x4_abilities_cl49TxEEEStates_c_TX_QUIET 2 228 #define an_x4_abilities_cl49TxEEEStates_c_TX_SLEEP 1 229 #define an_x4_abilities_cl49TxEEEStates_c_TX_ACTIVE 0 230 231 /**************************************************************************** 232 * Enums: an_x4_abilities_cl36RxEEEStates_l 233 */ 234 #define an_x4_abilities_cl36RxEEEStates_l_RX_LINK_FAIL 32 235 #define an_x4_abilities_cl36RxEEEStates_l_RX_WTF 16 236 #define an_x4_abilities_cl36RxEEEStates_l_RX_WAKE 8 237 #define an_x4_abilities_cl36RxEEEStates_l_RX_QUIET 4 238 #define an_x4_abilities_cl36RxEEEStates_l_RX_SLEEP 2 239 #define an_x4_abilities_cl36RxEEEStates_l_RX_ACTIVE 1 240 241 /**************************************************************************** 242 * Enums: an_x4_abilities_cl36RxEEEStates_c 243 */ 244 #define an_x4_abilities_cl36RxEEEStates_c_RX_LINK_FAIL 5 245 #define an_x4_abilities_cl36RxEEEStates_c_RX_WTF 4 246 #define an_x4_abilities_cl36RxEEEStates_c_RX_WAKE 3 247 #define an_x4_abilities_cl36RxEEEStates_c_RX_QUIET 2 248 #define an_x4_abilities_cl36RxEEEStates_c_RX_SLEEP 1 249 #define an_x4_abilities_cl36RxEEEStates_c_RX_ACTIVE 0 250 251 /**************************************************************************** 252 * Enums: an_x4_abilities_cl49RxEEEStates_l 253 */ 254 #define an_x4_abilities_cl49RxEEEStates_l_RX_LINK_FAIL 32 255 #define an_x4_abilities_cl49RxEEEStates_l_RX_WTF 16 256 #define an_x4_abilities_cl49RxEEEStates_l_RX_WAKE 8 257 #define an_x4_abilities_cl49RxEEEStates_l_RX_QUIET 4 258 #define an_x4_abilities_cl49RxEEEStates_l_RX_SLEEP 2 259 #define an_x4_abilities_cl49RxEEEStates_l_RX_ACTIVE 1 260 261 /**************************************************************************** 262 * Enums: an_x4_abilities_cl49RxEEEStates_c 263 */ 264 #define an_x4_abilities_cl49RxEEEStates_c_RX_LINK_FAIL 5 265 #define an_x4_abilities_cl49RxEEEStates_c_RX_WTF 4 266 #define an_x4_abilities_cl49RxEEEStates_c_RX_WAKE 3 267 #define an_x4_abilities_cl49RxEEEStates_c_RX_QUIET 2 268 #define an_x4_abilities_cl49RxEEEStates_c_RX_SLEEP 1 269 #define an_x4_abilities_cl49RxEEEStates_c_RX_ACTIVE 0 270 271 /**************************************************************************** 272 * Enums: an_x4_abilities_cl48TxEEEStates_l 273 */ 274 #define an_x4_abilities_cl48TxEEEStates_l_TX_REFRESH 8 275 #define an_x4_abilities_cl48TxEEEStates_l_TX_QUIET 4 276 #define an_x4_abilities_cl48TxEEEStates_l_TX_SLEEP 2 277 #define an_x4_abilities_cl48TxEEEStates_l_TX_ACTIVE 1 278 279 /**************************************************************************** 280 * Enums: an_x4_abilities_cl48TxEEEStates_c 281 */ 282 #define an_x4_abilities_cl48TxEEEStates_c_TX_REFRESH 3 283 #define an_x4_abilities_cl48TxEEEStates_c_TX_QUIET 2 284 #define an_x4_abilities_cl48TxEEEStates_c_TX_SLEEP 1 285 #define an_x4_abilities_cl48TxEEEStates_c_TX_ACTIVE 0 286 287 /**************************************************************************** 288 * Enums: an_x4_abilities_cl48RxEEEStates_l 289 */ 290 #define an_x4_abilities_cl48RxEEEStates_l_RX_LINK_FAIL 32 291 #define an_x4_abilities_cl48RxEEEStates_l_RX_WAKE 16 292 #define an_x4_abilities_cl48RxEEEStates_l_RX_QUIET 8 293 #define an_x4_abilities_cl48RxEEEStates_l_RX_DEACT 4 294 #define an_x4_abilities_cl48RxEEEStates_l_RX_SLEEP 2 295 #define an_x4_abilities_cl48RxEEEStates_l_RX_ACTIVE 1 296 297 /**************************************************************************** 298 * Enums: an_x4_abilities_cl48RxEEEStates_c 299 */ 300 #define an_x4_abilities_cl48RxEEEStates_c_RX_LINK_FAIL 5 301 #define an_x4_abilities_cl48RxEEEStates_c_RX_WAKE 4 302 #define an_x4_abilities_cl48RxEEEStates_c_RX_QUIET 3 303 #define an_x4_abilities_cl48RxEEEStates_c_RX_DEACT 2 304 #define an_x4_abilities_cl48RxEEEStates_c_RX_SLEEP 1 305 #define an_x4_abilities_cl48RxEEEStates_c_RX_ACTIVE 0 306 307 /**************************************************************************** 308 * Enums: an_x4_abilities_IQP_Options 309 */ 310 #define an_x4_abilities_IQP_Options_i50uA 0 311 #define an_x4_abilities_IQP_Options_i100uA 1 312 #define an_x4_abilities_IQP_Options_i150uA 2 313 #define an_x4_abilities_IQP_Options_i200uA 3 314 #define an_x4_abilities_IQP_Options_i250uA 4 315 #define an_x4_abilities_IQP_Options_i300uA 5 316 #define an_x4_abilities_IQP_Options_i350uA 6 317 #define an_x4_abilities_IQP_Options_i400uA 7 318 #define an_x4_abilities_IQP_Options_i450uA 8 319 #define an_x4_abilities_IQP_Options_i500uA 9 320 #define an_x4_abilities_IQP_Options_i550uA 10 321 #define an_x4_abilities_IQP_Options_i600uA 11 322 #define an_x4_abilities_IQP_Options_i650uA 12 323 #define an_x4_abilities_IQP_Options_i700uA 13 324 #define an_x4_abilities_IQP_Options_i750uA 14 325 #define an_x4_abilities_IQP_Options_i800uA 15 326 327 /**************************************************************************** 328 * Enums: an_x4_abilities_IDriver_Options 329 */ 330 #define an_x4_abilities_IDriver_Options_v680mV 0 331 #define an_x4_abilities_IDriver_Options_v730mV 1 332 #define an_x4_abilities_IDriver_Options_v780mV 2 333 #define an_x4_abilities_IDriver_Options_v830mV 3 334 #define an_x4_abilities_IDriver_Options_v880mV 4 335 #define an_x4_abilities_IDriver_Options_v930mV 5 336 #define an_x4_abilities_IDriver_Options_v980mV 6 337 #define an_x4_abilities_IDriver_Options_v1010mV 7 338 #define an_x4_abilities_IDriver_Options_v1040mV 8 339 #define an_x4_abilities_IDriver_Options_v1060mV 9 340 #define an_x4_abilities_IDriver_Options_v1070mV 10 341 #define an_x4_abilities_IDriver_Options_v1080mV 11 342 #define an_x4_abilities_IDriver_Options_v1085mV 12 343 #define an_x4_abilities_IDriver_Options_v1090mV 13 344 #define an_x4_abilities_IDriver_Options_v1095mV 14 345 #define an_x4_abilities_IDriver_Options_v1100mV 15 346 347 /**************************************************************************** 348 * Enums: an_x4_abilities_operationModes 349 */ 350 #define an_x4_abilities_operationModes_XGXS 0 351 #define an_x4_abilities_operationModes_XGXG_nCC 1 352 #define an_x4_abilities_operationModes_Indlane_OS8 4 353 #define an_x4_abilities_operationModes_IndLane_OS5 5 354 #define an_x4_abilities_operationModes_PCI 7 355 #define an_x4_abilities_operationModes_XGXS_nLQ 8 356 #define an_x4_abilities_operationModes_XGXS_nLQnCC 9 357 #define an_x4_abilities_operationModes_PBypass 10 358 #define an_x4_abilities_operationModes_PBypass_nDSK 11 359 #define an_x4_abilities_operationModes_ComboCoreMode 12 360 #define an_x4_abilities_operationModes_Clocks_off 15 361 362 /**************************************************************************** 363 * Enums: an_x4_abilities_actualSpeeds 364 */ 365 #define an_x4_abilities_actualSpeeds_dr_10M 0 366 #define an_x4_abilities_actualSpeeds_dr_100M 1 367 #define an_x4_abilities_actualSpeeds_dr_1G 2 368 #define an_x4_abilities_actualSpeeds_dr_2p5G 3 369 #define an_x4_abilities_actualSpeeds_dr_5G_X4 4 370 #define an_x4_abilities_actualSpeeds_dr_6G_X4 5 371 #define an_x4_abilities_actualSpeeds_dr_10G_HiG 6 372 #define an_x4_abilities_actualSpeeds_dr_10G_CX4 7 373 #define an_x4_abilities_actualSpeeds_dr_12G_HiG 8 374 #define an_x4_abilities_actualSpeeds_dr_12p5G_X4 9 375 #define an_x4_abilities_actualSpeeds_dr_13G_X4 10 376 #define an_x4_abilities_actualSpeeds_dr_15G_X4 11 377 #define an_x4_abilities_actualSpeeds_dr_16G_X4 12 378 #define an_x4_abilities_actualSpeeds_dr_1G_KX 13 379 #define an_x4_abilities_actualSpeeds_dr_10G_KX4 14 380 #define an_x4_abilities_actualSpeeds_dr_10G_KR 15 381 #define an_x4_abilities_actualSpeeds_dr_5G 16 382 #define an_x4_abilities_actualSpeeds_dr_6p4G 17 383 #define an_x4_abilities_actualSpeeds_dr_20G_X4 18 384 #define an_x4_abilities_actualSpeeds_dr_21G_X4 19 385 #define an_x4_abilities_actualSpeeds_dr_25G_X4 20 386 #define an_x4_abilities_actualSpeeds_dr_10G_HiG_DXGXS 21 387 #define an_x4_abilities_actualSpeeds_dr_10G_DXGXS 22 388 #define an_x4_abilities_actualSpeeds_dr_10p5G_HiG_DXGXS 23 389 #define an_x4_abilities_actualSpeeds_dr_10p5G_DXGXS 24 390 #define an_x4_abilities_actualSpeeds_dr_12p773G_HiG_DXGXS 25 391 #define an_x4_abilities_actualSpeeds_dr_12p773G_DXGXS 26 392 #define an_x4_abilities_actualSpeeds_dr_10G_XFI 27 393 #define an_x4_abilities_actualSpeeds_dr_40G 28 394 #define an_x4_abilities_actualSpeeds_dr_20G_HiG_DXGXS 29 395 #define an_x4_abilities_actualSpeeds_dr_20G_DXGXS 30 396 #define an_x4_abilities_actualSpeeds_dr_10G_SFI 31 397 #define an_x4_abilities_actualSpeeds_dr_31p5G 32 398 #define an_x4_abilities_actualSpeeds_dr_32p7G 33 399 #define an_x4_abilities_actualSpeeds_dr_20G_SCR 34 400 #define an_x4_abilities_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 401 #define an_x4_abilities_actualSpeeds_dr_10G_DXGXS_SCR 36 402 #define an_x4_abilities_actualSpeeds_dr_12G_R2 37 403 #define an_x4_abilities_actualSpeeds_dr_10G_X2 38 404 #define an_x4_abilities_actualSpeeds_dr_40G_KR4 39 405 #define an_x4_abilities_actualSpeeds_dr_40G_CR4 40 406 #define an_x4_abilities_actualSpeeds_dr_100G_CR10 41 407 #define an_x4_abilities_actualSpeeds_dr_15p75G_DXGXS 44 408 #define an_x4_abilities_actualSpeeds_dr_20G_KR2 57 409 #define an_x4_abilities_actualSpeeds_dr_20G_CR2 58 410 411 /**************************************************************************** 412 * Enums: an_x4_abilities_actualSpeedsMisc1 413 */ 414 #define an_x4_abilities_actualSpeedsMisc1_dr_2500BRCM_X1 16 415 #define an_x4_abilities_actualSpeedsMisc1_dr_5000BRCM_X4 17 416 #define an_x4_abilities_actualSpeedsMisc1_dr_6000BRCM_X4 18 417 #define an_x4_abilities_actualSpeedsMisc1_dr_10GHiGig_X4 19 418 #define an_x4_abilities_actualSpeedsMisc1_dr_10GBASE_CX4 20 419 #define an_x4_abilities_actualSpeedsMisc1_dr_12GHiGig_X4 21 420 #define an_x4_abilities_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 421 #define an_x4_abilities_actualSpeedsMisc1_dr_13GHiGig_X4 23 422 #define an_x4_abilities_actualSpeedsMisc1_dr_15GHiGig_X4 24 423 #define an_x4_abilities_actualSpeedsMisc1_dr_16GHiGig_X4 25 424 #define an_x4_abilities_actualSpeedsMisc1_dr_5000BRCM_X1 26 425 #define an_x4_abilities_actualSpeedsMisc1_dr_6363BRCM_X1 27 426 #define an_x4_abilities_actualSpeedsMisc1_dr_20GHiGig_X4 28 427 #define an_x4_abilities_actualSpeedsMisc1_dr_21GHiGig_X4 29 428 #define an_x4_abilities_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 429 #define an_x4_abilities_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 430 431 /**************************************************************************** 432 * Enums: an_x4_abilities_IndLaneModes 433 */ 434 #define an_x4_abilities_IndLaneModes_SWSDR_div2 0 435 #define an_x4_abilities_IndLaneModes_SWSDR_div1 1 436 #define an_x4_abilities_IndLaneModes_DWSDR_div2 2 437 #define an_x4_abilities_IndLaneModes_DWSDR_div1 3 438 439 /**************************************************************************** 440 * Enums: an_x4_abilities_prbsSelect 441 */ 442 #define an_x4_abilities_prbsSelect_prbs7 0 443 #define an_x4_abilities_prbsSelect_prbs15 1 444 #define an_x4_abilities_prbsSelect_prbs23 2 445 #define an_x4_abilities_prbsSelect_prbs31 3 446 447 /**************************************************************************** 448 * Enums: an_x4_abilities_vcoDivider 449 */ 450 #define an_x4_abilities_vcoDivider_div32 0 451 #define an_x4_abilities_vcoDivider_div36 1 452 #define an_x4_abilities_vcoDivider_div40 2 453 #define an_x4_abilities_vcoDivider_div42 3 454 #define an_x4_abilities_vcoDivider_div48 4 455 #define an_x4_abilities_vcoDivider_div50 5 456 #define an_x4_abilities_vcoDivider_div52 6 457 #define an_x4_abilities_vcoDivider_div54 7 458 #define an_x4_abilities_vcoDivider_div60 8 459 #define an_x4_abilities_vcoDivider_div64 9 460 #define an_x4_abilities_vcoDivider_div66 10 461 #define an_x4_abilities_vcoDivider_div68 11 462 #define an_x4_abilities_vcoDivider_div70 12 463 #define an_x4_abilities_vcoDivider_div80 13 464 #define an_x4_abilities_vcoDivider_div92 14 465 #define an_x4_abilities_vcoDivider_div100 15 466 467 /**************************************************************************** 468 * Enums: an_x4_abilities_refClkSelect 469 */ 470 #define an_x4_abilities_refClkSelect_clk_156p25MHz 1 471 #define an_x4_abilities_refClkSelect_clk_312p5Mhz 2 472 473 /**************************************************************************** 474 * Enums: an_x4_abilities_aerMMDdevTypeSelect 475 */ 476 #define an_x4_abilities_aerMMDdevTypeSelect_combo_core 0 477 #define an_x4_abilities_aerMMDdevTypeSelect_PMA_PMD 1 478 #define an_x4_abilities_aerMMDdevTypeSelect_PCS 3 479 #define an_x4_abilities_aerMMDdevTypeSelect_PHY 4 480 #define an_x4_abilities_aerMMDdevTypeSelect_DTE 5 481 #define an_x4_abilities_aerMMDdevTypeSelect_CL73_AN 7 482 483 /**************************************************************************** 484 * Enums: an_x4_abilities_aerMMDportSelect 485 */ 486 #define an_x4_abilities_aerMMDportSelect_ln0 0 487 #define an_x4_abilities_aerMMDportSelect_ln1 1 488 #define an_x4_abilities_aerMMDportSelect_ln2 2 489 #define an_x4_abilities_aerMMDportSelect_ln3 3 490 #define an_x4_abilities_aerMMDportSelect_BCST_ln0_1_2_3 511 491 #define an_x4_abilities_aerMMDportSelect_BCST_ln0_1 512 492 #define an_x4_abilities_aerMMDportSelect_BCST_ln2_3 513 493 494 /**************************************************************************** 495 * Enums: an_x4_abilities_firmwareModeSelect 496 */ 497 #define an_x4_abilities_firmwareModeSelect_DEFAULT 0 498 #define an_x4_abilities_firmwareModeSelect_SFP_OPT_LR 1 499 #define an_x4_abilities_firmwareModeSelect_SFP_DAC 2 500 #define an_x4_abilities_firmwareModeSelect_XLAUI 3 501 #define an_x4_abilities_firmwareModeSelect_LONG_CH_6G 4 502 503 /**************************************************************************** 504 * Enums: an_x4_abilities_tempIdxSelect 505 */ 506 #define an_x4_abilities_tempIdxSelect_LTE__22p9C 15 507 #define an_x4_abilities_tempIdxSelect_LTE__12p6C 14 508 #define an_x4_abilities_tempIdxSelect_LTE__3p0C 13 509 #define an_x4_abilities_tempIdxSelect_LTE_6p7C 12 510 #define an_x4_abilities_tempIdxSelect_LTE_16p4C 11 511 #define an_x4_abilities_tempIdxSelect_LTE_26p6C 10 512 #define an_x4_abilities_tempIdxSelect_LTE_36p3C 9 513 #define an_x4_abilities_tempIdxSelect_LTE_46p0C 8 514 #define an_x4_abilities_tempIdxSelect_LTE_56p2C 7 515 #define an_x4_abilities_tempIdxSelect_LTE_65p9C 6 516 #define an_x4_abilities_tempIdxSelect_LTE_75p6C 5 517 #define an_x4_abilities_tempIdxSelect_LTE_85p3C 4 518 #define an_x4_abilities_tempIdxSelect_LTE_95p5C 3 519 #define an_x4_abilities_tempIdxSelect_LTE_105p2C 2 520 #define an_x4_abilities_tempIdxSelect_LTE_114p9C 1 521 #define an_x4_abilities_tempIdxSelect_LTE_125p1C 0 522 523 /**************************************************************************** 524 * Enums: an_x4_abilities_port_mode 525 */ 526 #define an_x4_abilities_port_mode_QUAD_PORT 0 527 #define an_x4_abilities_port_mode_TRI_1_PORT 1 528 #define an_x4_abilities_port_mode_TRI_2_PORT 2 529 #define an_x4_abilities_port_mode_DUAL_PORT 3 530 #define an_x4_abilities_port_mode_SINGLE_PORT 4 531 #define an_x4_abilities_port_mode_SINGLE_OCTAL_PORT 5 532 533 /**************************************************************************** 534 * Enums: an_x4_abilities_rev_letter_enum 535 */ 536 #define an_x4_abilities_rev_letter_enum_REV_A 0 537 #define an_x4_abilities_rev_letter_enum_REV_B 1 538 #define an_x4_abilities_rev_letter_enum_REV_C 2 539 #define an_x4_abilities_rev_letter_enum_REV_D 3 540 541 /**************************************************************************** 542 * Enums: an_x4_abilities_rev_number_enum 543 */ 544 #define an_x4_abilities_rev_number_enum_REV_0 0 545 #define an_x4_abilities_rev_number_enum_REV_1 1 546 #define an_x4_abilities_rev_number_enum_REV_2 2 547 #define an_x4_abilities_rev_number_enum_REV_3 3 548 #define an_x4_abilities_rev_number_enum_REV_4 4 549 #define an_x4_abilities_rev_number_enum_REV_5 5 550 #define an_x4_abilities_rev_number_enum_REV_6 6 551 #define an_x4_abilities_rev_number_enum_REV_7 7 552 553 /**************************************************************************** 554 * Enums: an_x4_abilities_bonding_enum 555 */ 556 #define an_x4_abilities_bonding_enum_WIRE_BOND 0 557 #define an_x4_abilities_bonding_enum_FLIP_CHIP 1 558 559 /**************************************************************************** 560 * Enums: an_x4_abilities_tech_process 561 */ 562 #define an_x4_abilities_tech_process_PROCESS_90NM 0 563 #define an_x4_abilities_tech_process_PROCESS_65NM 1 564 #define an_x4_abilities_tech_process_PROCESS_40NM 2 565 #define an_x4_abilities_tech_process_PROCESS_28NM 3 566 #define an_x4_abilities_tech_process_PROCESS_16NM 4 567 568 /**************************************************************************** 569 * Enums: an_x4_abilities_model_num 570 */ 571 #define an_x4_abilities_model_num_SERDES_CL73 0 572 #define an_x4_abilities_model_num_XGXS_16G 1 573 #define an_x4_abilities_model_num_HYPERCORE 2 574 #define an_x4_abilities_model_num_HYPERLITE 3 575 #define an_x4_abilities_model_num_PCIE_G2_PIPE 4 576 #define an_x4_abilities_model_num_SERDES_1p25GBd 5 577 #define an_x4_abilities_model_num_SATA2 6 578 #define an_x4_abilities_model_num_QSGMII 7 579 #define an_x4_abilities_model_num_XGXS10G 8 580 #define an_x4_abilities_model_num_WARPCORE 9 581 #define an_x4_abilities_model_num_XFICORE 10 582 #define an_x4_abilities_model_num_RXFI 11 583 #define an_x4_abilities_model_num_WARPLITE 12 584 #define an_x4_abilities_model_num_PENTACORE 13 585 #define an_x4_abilities_model_num_ESM 14 586 #define an_x4_abilities_model_num_QUAD_SGMII 15 587 #define an_x4_abilities_model_num_WARPCORE_3 16 588 #define an_x4_abilities_model_num_TSC 17 589 #define an_x4_abilities_model_num_TSC4E 18 590 #define an_x4_abilities_model_num_TSC12E 19 591 #define an_x4_abilities_model_num_TSC4F 20 592 #define an_x4_abilities_model_num_TSC4F_GEN2 21 593 #define an_x4_abilities_model_num_XGXS_CL73_90NM 29 594 #define an_x4_abilities_model_num_SERDES_CL73_90NM 30 595 #define an_x4_abilities_model_num_WARPCORE3 32 596 #define an_x4_abilities_model_num_WARPCORE4_TSC 33 597 #define an_x4_abilities_model_num_RXAUI 34 598 #define an_x4_abilities_model_num_TSCE_GEN3 35 599 #define an_x4_abilities_model_num_TSC4F_GEN3 36 600 #define an_x4_abilities_model_num_TSCBH 37 601 602 /**************************************************************************** 603 * Enums: an_x4_abilities_payload 604 */ 605 #define an_x4_abilities_payload_REPEAT_2_BYTES 0 606 #define an_x4_abilities_payload_RAMPING 1 607 #define an_x4_abilities_payload_CL48_CRPAT 2 608 #define an_x4_abilities_payload_CL48_CJPAT 3 609 #define an_x4_abilities_payload_CL36_LONG_CRPAT 4 610 #define an_x4_abilities_payload_CL36_SHORT_CRPAT 5 611 612 /**************************************************************************** 613 * Enums: an_x4_abilities_sc 614 */ 615 #define an_x4_abilities_sc_SPEED_10G_IEEE_KR1 0 616 #define an_x4_abilities_sc_SPEED_25G_IEEE_KS1_CS1 1 617 #define an_x4_abilities_sc_SPEED_25G_IEEE_KR1_CR1 2 618 #define an_x4_abilities_sc_SPEED_40G_IEEE_KR4 3 619 #define an_x4_abilities_sc_SPEED_40G_IEEE_CR4 4 620 #define an_x4_abilities_sc_SPEED_50G_IEEE_KR1_CR1 5 621 #define an_x4_abilities_sc_SPEED_100G_IEEE_KR4 6 622 #define an_x4_abilities_sc_SPEED_100G_IEEE_CR4 7 623 #define an_x4_abilities_sc_SPEED_100G_IEEE_KR2_CR2 8 624 #define an_x4_abilities_sc_SPEED_200G_IEEE_KR4_CR4 9 625 #define an_x4_abilities_sc_SPEED_400G_IEEE_X8 10 626 #define an_x4_abilities_sc_SPEED_CL73_IEEE_20GVCO 11 627 #define an_x4_abilities_sc_SPEED_CL73_IEEE_25GVCO 12 628 #define an_x4_abilities_sc_SPEED_CL73_IEEE_26GVCO 13 629 #define an_x4_abilities_sc_SPEED_20G_BRCM_CR1 14 630 #define an_x4_abilities_sc_SPEED_20G_BRCM_KR1 15 631 #define an_x4_abilities_sc_SPEED_25G_BRCM_CR1 16 632 #define an_x4_abilities_sc_SPEED_25G_BRCM_KR1 17 633 #define an_x4_abilities_sc_SPEED_40G_BRCM_CR2 18 634 #define an_x4_abilities_sc_SPEED_40G_BRCM_KR2 19 635 #define an_x4_abilities_sc_SPEED_50G_BRCM_CR2 20 636 #define an_x4_abilities_sc_SPEED_50G_BRCM_KR2 21 637 #define an_x4_abilities_sc_SPEED_50G_BRCM_CR4 22 638 #define an_x4_abilities_sc_SPEED_50G_BRCM_KR4 23 639 #define an_x4_abilities_sc_SPEED_50G_BRCM_FEC_544_CR2_KR2 24 640 #define an_x4_abilities_sc_SPEED_RESERVED_19 25 641 #define an_x4_abilities_sc_SPEED_50G_BRCM_FEC_544_CR1_KR1 26 642 #define an_x4_abilities_sc_SPEED_50G_BRCM_NO_FEC_CR1_KR1 27 643 #define an_x4_abilities_sc_SPEED_50G_BRCM_FEC_528_CR1_KR1 28 644 #define an_x4_abilities_sc_SPEED_400G_BRCM_NO_FEC_KR8_CR8 29 645 #define an_x4_abilities_sc_SPEED_400G_BRCM_FEC_KR8_CR8 30 646 #define an_x4_abilities_sc_SPEED_200G_BRCM_NO_FEC_KR4_CR4 31 647 #define an_x4_abilities_sc_SPEED_200G_BRCM_KR4_CR4 32 648 #define an_x4_abilities_sc_SPEED_100G_BRCM_KR4_CR4 33 649 #define an_x4_abilities_sc_SPEED_RESERVED_22 34 650 #define an_x4_abilities_sc_SPEED_100G_BRCM_FEC_528_KR2_CR2 35 651 #define an_x4_abilities_sc_SPEED_100G_BRCM_NO_FEC_KR2_CR2 36 652 #define an_x4_abilities_sc_SPEED_100G_BRCM_NO_FEC_X4 37 653 654 /**************************************************************************** 655 * Enums: an_x4_abilities_t_fifo_modes 656 */ 657 #define an_x4_abilities_t_fifo_modes_T_FIFO_INSERT_NO_AM 0 658 #define an_x4_abilities_t_fifo_modes_T_FIFO_INSERT_4_AM 1 659 #define an_x4_abilities_t_fifo_modes_T_FIFO_INSERT_20_AM 2 660 #define an_x4_abilities_t_fifo_modes_T_FIFO_INSERT_2_AM 3 661 662 /**************************************************************************** 663 * Enums: an_x4_abilities_t_enc_modes 664 */ 665 #define an_x4_abilities_t_enc_modes_T_ENC_MODE_BYPASS 0 666 #define an_x4_abilities_t_enc_modes_T_ENC_MODE_CL49 1 667 #define an_x4_abilities_t_enc_modes_T_ENC_MODE_CL82 2 668 669 /**************************************************************************** 670 * Enums: an_x4_abilities_btmx_mode 671 */ 672 #define an_x4_abilities_btmx_mode_BS_BTMX_MODE_1to1 0 673 #define an_x4_abilities_btmx_mode_BS_BTMX_MODE_2to1 1 674 #define an_x4_abilities_btmx_mode_BS_BTMX_MODE_5to1 2 675 676 /**************************************************************************** 677 * Enums: an_x4_abilities_t_type_cl82 678 */ 679 #define an_x4_abilities_t_type_cl82_T_TYPE_B1 5 680 #define an_x4_abilities_t_type_cl82_T_TYPE_C 4 681 #define an_x4_abilities_t_type_cl82_T_TYPE_S 3 682 #define an_x4_abilities_t_type_cl82_T_TYPE_T 2 683 #define an_x4_abilities_t_type_cl82_T_TYPE_D 1 684 #define an_x4_abilities_t_type_cl82_T_TYPE_E 0 685 686 /**************************************************************************** 687 * Enums: an_x4_abilities_txsm_state_cl82 688 */ 689 #define an_x4_abilities_txsm_state_cl82_TX_E 4 690 #define an_x4_abilities_txsm_state_cl82_TX_T 3 691 #define an_x4_abilities_txsm_state_cl82_TX_D 2 692 #define an_x4_abilities_txsm_state_cl82_TX_C 1 693 #define an_x4_abilities_txsm_state_cl82_TX_INIT 0 694 695 /**************************************************************************** 696 * Enums: an_x4_abilities_ltxsm_state_cl82 697 */ 698 #define an_x4_abilities_ltxsm_state_cl82_TX_E 16 699 #define an_x4_abilities_ltxsm_state_cl82_TX_T 8 700 #define an_x4_abilities_ltxsm_state_cl82_TX_D 4 701 #define an_x4_abilities_ltxsm_state_cl82_TX_C 2 702 #define an_x4_abilities_ltxsm_state_cl82_TX_INIT 1 703 704 /**************************************************************************** 705 * Enums: an_x4_abilities_r_type_coded_cl82 706 */ 707 #define an_x4_abilities_r_type_coded_cl82_R_TYPE_B1 32 708 #define an_x4_abilities_r_type_coded_cl82_R_TYPE_C 16 709 #define an_x4_abilities_r_type_coded_cl82_R_TYPE_S 8 710 #define an_x4_abilities_r_type_coded_cl82_R_TYPE_T 4 711 #define an_x4_abilities_r_type_coded_cl82_R_TYPE_D 2 712 #define an_x4_abilities_r_type_coded_cl82_R_TYPE_E 1 713 714 /**************************************************************************** 715 * Enums: an_x4_abilities_rxsm_state_cl82 716 */ 717 #define an_x4_abilities_rxsm_state_cl82_RX_E 16 718 #define an_x4_abilities_rxsm_state_cl82_RX_T 8 719 #define an_x4_abilities_rxsm_state_cl82_RX_D 4 720 #define an_x4_abilities_rxsm_state_cl82_RX_C 2 721 #define an_x4_abilities_rxsm_state_cl82_RX_INIT 1 722 723 /**************************************************************************** 724 * Enums: an_x4_abilities_deskew_state 725 */ 726 #define an_x4_abilities_deskew_state_ALIGN_ACQUIRED 2 727 #define an_x4_abilities_deskew_state_LOSS_OF_ALIGNMENT 1 728 729 /**************************************************************************** 730 * Enums: an_x4_abilities_os_mode_enum 731 */ 732 #define an_x4_abilities_os_mode_enum_OS_MODE_1 0 733 #define an_x4_abilities_os_mode_enum_OS_MODE_2 1 734 #define an_x4_abilities_os_mode_enum_OS_MODE_4 2 735 #define an_x4_abilities_os_mode_enum_OS_MODE_16p5 8 736 #define an_x4_abilities_os_mode_enum_OS_MODE_20p625 12 737 738 /**************************************************************************** 739 * Enums: an_x4_abilities_scr_modes 740 */ 741 #define an_x4_abilities_scr_modes_T_SCR_MODE_BYPASS 0 742 #define an_x4_abilities_scr_modes_T_SCR_MODE_CL49 1 743 #define an_x4_abilities_scr_modes_T_SCR_MODE_40G_2_LANE 2 744 #define an_x4_abilities_scr_modes_T_SCR_MODE_100G 3 745 #define an_x4_abilities_scr_modes_T_SCR_MODE_20G 4 746 #define an_x4_abilities_scr_modes_T_SCR_MODE_40G_4_LANE 5 747 748 /**************************************************************************** 749 * Enums: an_x4_abilities_descr_modes 750 */ 751 #define an_x4_abilities_descr_modes_R_DESCR_MODE_BYPASS 0 752 #define an_x4_abilities_descr_modes_R_DESCR_MODE_CL49 1 753 #define an_x4_abilities_descr_modes_R_DESCR_MODE_CL82 2 754 755 /**************************************************************************** 756 * Enums: an_x4_abilities_r_dec_tl_mode 757 */ 758 #define an_x4_abilities_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 759 #define an_x4_abilities_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 760 #define an_x4_abilities_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 761 762 /**************************************************************************** 763 * Enums: an_x4_abilities_r_dec_fsm_mode 764 */ 765 #define an_x4_abilities_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 766 #define an_x4_abilities_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 767 #define an_x4_abilities_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 768 769 /**************************************************************************** 770 * Enums: an_x4_abilities_r_deskew_mode 771 */ 772 #define an_x4_abilities_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 773 #define an_x4_abilities_r_deskew_mode_R_DESKEW_MODE_20G 1 774 #define an_x4_abilities_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 775 #define an_x4_abilities_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 776 #define an_x4_abilities_r_deskew_mode_R_DESKEW_MODE_100G 4 777 #define an_x4_abilities_r_deskew_mode_R_DESKEW_MODE_CL49 5 778 #define an_x4_abilities_r_deskew_mode_R_DESKEW_MODE_CL91_QUAD 6 779 #define an_x4_abilities_r_deskew_mode_R_DESKEW_MODE_CL91_SINGLE_BRCM 7 780 #define an_x4_abilities_r_deskew_mode_R_DESKEW_MODE_CL91_DUAL_BRCM 8 781 #define an_x4_abilities_r_deskew_mode_R_DESKEW_MODE_CL91_FC 9 782 783 /**************************************************************************** 784 * Enums: an_x4_abilities_bs_dist_modes 785 */ 786 #define an_x4_abilities_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 787 #define an_x4_abilities_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 788 #define an_x4_abilities_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 789 #define an_x4_abilities_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 790 791 /**************************************************************************** 792 * Enums: an_x4_abilities_cl49_t_type 793 */ 794 #define an_x4_abilities_cl49_t_type_BAD_T_TYPE 15 795 #define an_x4_abilities_cl49_t_type_T_TYPE_B0 11 796 #define an_x4_abilities_cl49_t_type_T_TYPE_OB 10 797 #define an_x4_abilities_cl49_t_type_T_TYPE_B1 9 798 #define an_x4_abilities_cl49_t_type_T_TYPE_DB 8 799 #define an_x4_abilities_cl49_t_type_T_TYPE_FC 7 800 #define an_x4_abilities_cl49_t_type_T_TYPE_TB 6 801 #define an_x4_abilities_cl49_t_type_T_TYPE_LI 5 802 #define an_x4_abilities_cl49_t_type_T_TYPE_C 4 803 #define an_x4_abilities_cl49_t_type_T_TYPE_S 3 804 #define an_x4_abilities_cl49_t_type_T_TYPE_T 2 805 #define an_x4_abilities_cl49_t_type_T_TYPE_D 1 806 #define an_x4_abilities_cl49_t_type_T_TYPE_E 0 807 808 /**************************************************************************** 809 * Enums: an_x4_abilities_cl49_txsm_states 810 */ 811 #define an_x4_abilities_cl49_txsm_states_TX_LI 5 812 #define an_x4_abilities_cl49_txsm_states_TX_E 4 813 #define an_x4_abilities_cl49_txsm_states_TX_T 3 814 #define an_x4_abilities_cl49_txsm_states_TX_D 2 815 #define an_x4_abilities_cl49_txsm_states_TX_C 1 816 #define an_x4_abilities_cl49_txsm_states_TX_INIT 0 817 818 /**************************************************************************** 819 * Enums: an_x4_abilities_cl49_ltxsm_states 820 */ 821 #define an_x4_abilities_cl49_ltxsm_states_TX_LI 32 822 #define an_x4_abilities_cl49_ltxsm_states_TX_E 16 823 #define an_x4_abilities_cl49_ltxsm_states_TX_T 8 824 #define an_x4_abilities_cl49_ltxsm_states_TX_D 4 825 #define an_x4_abilities_cl49_ltxsm_states_TX_C 2 826 #define an_x4_abilities_cl49_ltxsm_states_TX_INIT 1 827 828 /**************************************************************************** 829 * Enums: an_x4_abilities_burst_error_mode 830 */ 831 #define an_x4_abilities_burst_error_mode_BURST_ERROR_11_BITS 0 832 #define an_x4_abilities_burst_error_mode_BURST_ERROR_16_BITS 1 833 #define an_x4_abilities_burst_error_mode_BURST_ERROR_17_BITS 2 834 #define an_x4_abilities_burst_error_mode_BURST_ERROR_18_BITS 3 835 #define an_x4_abilities_burst_error_mode_BURST_ERROR_19_BITS 4 836 #define an_x4_abilities_burst_error_mode_BURST_ERROR_20_BITS 5 837 #define an_x4_abilities_burst_error_mode_BURST_ERROR_21_BITS 6 838 #define an_x4_abilities_burst_error_mode_BURST_ERROR_22_BITS 7 839 #define an_x4_abilities_burst_error_mode_BURST_ERROR_23_BITS 8 840 #define an_x4_abilities_burst_error_mode_BURST_ERROR_24_BITS 9 841 #define an_x4_abilities_burst_error_mode_BURST_ERROR_25_BITS 10 842 #define an_x4_abilities_burst_error_mode_BURST_ERROR_26_BITS 11 843 #define an_x4_abilities_burst_error_mode_BURST_ERROR_27_BITS 12 844 #define an_x4_abilities_burst_error_mode_BURST_ERROR_28_BITS 13 845 #define an_x4_abilities_burst_error_mode_BURST_ERROR_29_BITS 14 846 #define an_x4_abilities_burst_error_mode_BURST_ERROR_30_BITS 15 847 #define an_x4_abilities_burst_error_mode_BURST_ERROR_31_BITS 16 848 #define an_x4_abilities_burst_error_mode_BURST_ERROR_32_BITS 17 849 #define an_x4_abilities_burst_error_mode_BURST_ERROR_33_BITS 18 850 #define an_x4_abilities_burst_error_mode_BURST_ERROR_34_BITS 19 851 #define an_x4_abilities_burst_error_mode_BURST_ERROR_35_BITS 20 852 #define an_x4_abilities_burst_error_mode_BURST_ERROR_36_BITS 21 853 #define an_x4_abilities_burst_error_mode_BURST_ERROR_37_BITS 22 854 #define an_x4_abilities_burst_error_mode_BURST_ERROR_38_BITS 23 855 #define an_x4_abilities_burst_error_mode_BURST_ERROR_39_BITS 24 856 #define an_x4_abilities_burst_error_mode_BURST_ERROR_40_BITS 25 857 #define an_x4_abilities_burst_error_mode_BURST_ERROR_41_BITS 26 858 859 /**************************************************************************** 860 * Enums: an_x4_abilities_bermon_state 861 */ 862 #define an_x4_abilities_bermon_state_HI_BER 4 863 #define an_x4_abilities_bermon_state_GOOD_BER 3 864 #define an_x4_abilities_bermon_state_BER_TEST_SH 2 865 #define an_x4_abilities_bermon_state_START_TIMER 1 866 #define an_x4_abilities_bermon_state_BER_MT_INIT 0 867 868 /**************************************************************************** 869 * Enums: an_x4_abilities_rxsm_state_cl49 870 */ 871 #define an_x4_abilities_rxsm_state_cl49_RX_LI 32 872 #define an_x4_abilities_rxsm_state_cl49_RX_E 16 873 #define an_x4_abilities_rxsm_state_cl49_RX_T 8 874 #define an_x4_abilities_rxsm_state_cl49_RX_D 4 875 #define an_x4_abilities_rxsm_state_cl49_RX_C 2 876 #define an_x4_abilities_rxsm_state_cl49_RX_INIT 1 877 878 /**************************************************************************** 879 * Enums: an_x4_abilities_r_type 880 */ 881 #define an_x4_abilities_r_type_BAD_R_TYPE 15 882 #define an_x4_abilities_r_type_R_TYPE_B0 11 883 #define an_x4_abilities_r_type_R_TYPE_OB 10 884 #define an_x4_abilities_r_type_R_TYPE_B1 9 885 #define an_x4_abilities_r_type_R_TYPE_DB 8 886 #define an_x4_abilities_r_type_R_TYPE_FC 7 887 #define an_x4_abilities_r_type_R_TYPE_TB 6 888 #define an_x4_abilities_r_type_R_TYPE_LI 5 889 #define an_x4_abilities_r_type_R_TYPE_C 4 890 #define an_x4_abilities_r_type_R_TYPE_S 3 891 #define an_x4_abilities_r_type_R_TYPE_T 2 892 #define an_x4_abilities_r_type_R_TYPE_D 1 893 #define an_x4_abilities_r_type_R_TYPE_E 0 894 895 /**************************************************************************** 896 * Enums: an_x4_abilities_am_lock_state 897 */ 898 #define an_x4_abilities_am_lock_state_INVALID_AM 512 899 #define an_x4_abilities_am_lock_state_GOOD_AM 256 900 #define an_x4_abilities_am_lock_state_COMP_AM 128 901 #define an_x4_abilities_am_lock_state_TIMER_2 64 902 #define an_x4_abilities_am_lock_state_AM_2_GOOD 32 903 #define an_x4_abilities_am_lock_state_COMP_2ND 16 904 #define an_x4_abilities_am_lock_state_TIMER_1 8 905 #define an_x4_abilities_am_lock_state_FIND_1ST 4 906 #define an_x4_abilities_am_lock_state_AM_RESET_CNT 2 907 #define an_x4_abilities_am_lock_state_AM_LOCK_INIT 1 908 909 /**************************************************************************** 910 * Enums: an_x4_abilities_msg_selector 911 */ 912 #define an_x4_abilities_msg_selector_RESERVED 0 913 #define an_x4_abilities_msg_selector_VALUE_802p3 1 914 #define an_x4_abilities_msg_selector_VALUE_802p9 2 915 #define an_x4_abilities_msg_selector_VALUE_802p5 3 916 #define an_x4_abilities_msg_selector_VALUE_1394 4 917 918 /**************************************************************************** 919 * Enums: an_x4_abilities_synce_enum_stage1 920 */ 921 #define an_x4_abilities_synce_enum_stage1_SYNCE_NO_DIV 0 922 #define an_x4_abilities_synce_enum_stage1_SYNCE_DIV_7 1 923 #define an_x4_abilities_synce_enum_stage1_SYNCE_DIV_11 2 924 925 /**************************************************************************** 926 * Enums: an_x4_abilities_synce_enum_stage0 927 */ 928 #define an_x4_abilities_synce_enum_stage0_SYNCE_NO_DIV 0 929 #define an_x4_abilities_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 930 #define an_x4_abilities_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 931 932 /**************************************************************************** 933 * Enums: an_x4_abilities_cl91_sync_state 934 */ 935 #define an_x4_abilities_cl91_sync_state_FIND_1ST 0 936 #define an_x4_abilities_cl91_sync_state_COUNT_NEXT 1 937 #define an_x4_abilities_cl91_sync_state_COMP_2ND 2 938 #define an_x4_abilities_cl91_sync_state_TWO_GOOD 3 939 940 /**************************************************************************** 941 * Enums: an_x4_abilities_RS_FEC_sync_state 942 */ 943 #define an_x4_abilities_RS_FEC_sync_state_LOCK_INIT 0 944 #define an_x4_abilities_RS_FEC_sync_state_FIND_1ST 1 945 #define an_x4_abilities_RS_FEC_sync_state_COUNT_NEXT 2 946 #define an_x4_abilities_RS_FEC_sync_state_COMP_2ND 3 947 #define an_x4_abilities_RS_FEC_sync_state_TWO_GOOD 4 948 949 /**************************************************************************** 950 * Enums: an_x4_abilities_cl91_algn_state 951 */ 952 #define an_x4_abilities_cl91_algn_state_LOSS_OF_ALIGNMENT 0 953 #define an_x4_abilities_cl91_algn_state_DESKEW 1 954 #define an_x4_abilities_cl91_algn_state_DESKEW_FAIL 2 955 #define an_x4_abilities_cl91_algn_state_ALIGN_ACQUIRED 3 956 #define an_x4_abilities_cl91_algn_state_CW_GOOD 4 957 #define an_x4_abilities_cl91_algn_state_CW_BAD 5 958 #define an_x4_abilities_cl91_algn_state_THREE_BAD 6 959 960 /**************************************************************************** 961 * Enums: an_x4_abilities_RS_FEC_algn_state 962 */ 963 #define an_x4_abilities_RS_FEC_algn_state_LOSS_OF_ALIGNMENT 0 964 #define an_x4_abilities_RS_FEC_algn_state_DESKEW 1 965 #define an_x4_abilities_RS_FEC_algn_state_DESKEW_FAIL 2 966 #define an_x4_abilities_RS_FEC_algn_state_ALIGN_ACQUIRED 3 967 #define an_x4_abilities_RS_FEC_algn_state_CW_GOOD 4 968 #define an_x4_abilities_RS_FEC_algn_state_CW_BAD 5 969 #define an_x4_abilities_RS_FEC_algn_state_THREE_BAD 6 970 971 /**************************************************************************** 972 * Enums: an_x4_abilities_fec_sel_override 973 */ 974 #define an_x4_abilities_fec_sel_override_NO_OVERRIDE 0 975 #define an_x4_abilities_fec_sel_override_NO_FEC 1 976 #define an_x4_abilities_fec_sel_override_FEC_CL74 2 977 #define an_x4_abilities_fec_sel_override_FEC_CL91 3 978 979 /**************************************************************************** 980 * Enums: an_x4_abilities_cl91_blksync_mode 981 */ 982 #define an_x4_abilities_cl91_blksync_mode_R_BLKSYNC_NO_CL91_FEC 0 983 #define an_x4_abilities_cl91_blksync_mode_R_BLKSYNC_CL91_QUAD_LANE_FEC 1 984 #define an_x4_abilities_cl91_blksync_mode_R_BLKSYNC_CL91_DUAL_LANE_FEC 2 985 #define an_x4_abilities_cl91_blksync_mode_R_BLKSYNC_CL91_SINGLE_LANE_FEC 3 986 #define an_x4_abilities_cl91_blksync_mode_R_BLKSYNC_CL91_FC_FEC 4 987 988 /**************************************************************************** 989 * Enums: an_x4_abilities_r_merge_mode 990 */ 991 #define an_x4_abilities_r_merge_mode_R_MERGE_MODE_BYPASS 0 992 #define an_x4_abilities_r_merge_mode_R_MERGE_MODE_CL91_FC 1 993 #define an_x4_abilities_r_merge_mode_R_MERGE_MODE_CL91_SINGLE_LANE 2 994 #define an_x4_abilities_r_merge_mode_R_MERGE_MODE_CL91_DUAL_LANE 3 995 #define an_x4_abilities_r_merge_mode_R_MERGE_MODE_CL91_QUAD_LANE 4 996 997 /**************************************************************************** 998 * Enums: an_x4_abilities_r_tc_mode 999 */ 1000 #define an_x4_abilities_r_tc_mode_R_TC_MODE_SINGLE 0 1001 #define an_x4_abilities_r_tc_mode_R_TC_MODE_DUAL 1 1002 #define an_x4_abilities_r_tc_mode_R_TC_MODE_QUAD 2 1003 1004 /**************************************************************************** 1005 * Enums: an_x4_abilities_r_tc_out_mode 1006 */ 1007 #define an_x4_abilities_r_tc_out_mode_R_TC_OUT_MODE_SINGLE 0 1008 #define an_x4_abilities_r_tc_out_mode_R_TC_OUT_MODE_DUAL 1 1009 #define an_x4_abilities_r_tc_out_mode_R_TC_OUT_MODE_QUAD 2 1010 1011 /**************************************************************************** 1012 * Enums: an_x4_abilities_cl91_fec_mode 1013 */ 1014 #define an_x4_abilities_cl91_fec_mode_NO_CL91_FEC 0 1015 #define an_x4_abilities_cl91_fec_mode_CL91_SINGLE_LANE_FC 1 1016 #define an_x4_abilities_cl91_fec_mode_CL91_SINGLE_LANE_BRCM_PROP 2 1017 #define an_x4_abilities_cl91_fec_mode_CL91_DUAL_LANE_BRCM_PROP 3 1018 #define an_x4_abilities_cl91_fec_mode_CL91_QUAD_LANE 4 1019 #define an_x4_abilities_cl91_fec_mode_IEEE_25G_CL91_SINGLE_LANE 5 1020 1021 /**************************************************************************** 1022 * Enums: an_x4_abilities_RS_FEC_fec_mode 1023 */ 1024 #define an_x4_abilities_RS_FEC_fec_mode_NO_RS_FEC_FEC 0 1025 #define an_x4_abilities_RS_FEC_fec_mode_N_A 1 1026 #define an_x4_abilities_RS_FEC_fec_mode_RS_FEC_SINGLE_LANE_BRCM_PROP 2 1027 #define an_x4_abilities_RS_FEC_fec_mode_RS_FEC_DUAL_LANE_BRCM_PROP 3 1028 #define an_x4_abilities_RS_FEC_fec_mode_RS_FEC_QUAD_LANE 4 1029 #define an_x4_abilities_RS_FEC_fec_mode_IEEE_25G_RS_FEC_SINGLE_LANE 5 1030 1031 /**************************************************************************** 1032 * Enums: an_x4_abilities_am_spacing_mul 1033 */ 1034 #define an_x4_abilities_am_spacing_mul_AM_SPACING_MUL_2 0 1035 #define an_x4_abilities_am_spacing_mul_AM_SPACING_MUL_4 1 1036 #define an_x4_abilities_am_spacing_mul_AM_SPACING_MUL_5 2 1037 #define an_x4_abilities_am_spacing_mul_AM_SPACING_MUL_20 3 1038 1039 /**************************************************************************** 1040 * Enums: an_x4_sw_mgmt_tla_ln_seq_status 1041 */ 1042 #define an_x4_sw_mgmt_tla_ln_seq_status_INIT 1 1043 #define an_x4_sw_mgmt_tla_ln_seq_status_SET_AN_SPEED 2 1044 #define an_x4_sw_mgmt_tla_ln_seq_status_WAIT_AN_SPEED 4 1045 #define an_x4_sw_mgmt_tla_ln_seq_status_WAIT_AN_DONE 8 1046 #define an_x4_sw_mgmt_tla_ln_seq_status_SET_RS_SPEED 16 1047 #define an_x4_sw_mgmt_tla_ln_seq_status_WAIT_RS_CL72EN 32 1048 #define an_x4_sw_mgmt_tla_ln_seq_status_WAIT_RS_SPEED 64 1049 #define an_x4_sw_mgmt_tla_ln_seq_status_AN_IGNORE_LINK 128 1050 #define an_x4_sw_mgmt_tla_ln_seq_status_AN_GOOD_CHECK 256 1051 #define an_x4_sw_mgmt_tla_ln_seq_status_AN_GOOD 512 1052 #define an_x4_sw_mgmt_tla_ln_seq_status_AN_FAIL 1024 1053 #define an_x4_sw_mgmt_tla_ln_seq_status_AN_DEAD 2048 1054 #define an_x4_sw_mgmt_tla_ln_seq_status_SW_SPEED_CHANGE 32768 1055 1056 /**************************************************************************** 1057 * Enums: cl82_cl36TxEEEStates_l 1058 */ 1059 #define cl82_cl36TxEEEStates_l_TX_REFRESH 8 1060 #define cl82_cl36TxEEEStates_l_TX_QUIET 4 1061 #define cl82_cl36TxEEEStates_l_TX_SLEEP 2 1062 #define cl82_cl36TxEEEStates_l_TX_ACTIVE 1 1063 1064 /**************************************************************************** 1065 * Enums: cl82_cl36TxEEEStates_c 1066 */ 1067 #define cl82_cl36TxEEEStates_c_TX_REFRESH 3 1068 #define cl82_cl36TxEEEStates_c_TX_QUIET 2 1069 #define cl82_cl36TxEEEStates_c_TX_SLEEP 1 1070 #define cl82_cl36TxEEEStates_c_TX_ACTIVE 0 1071 1072 /**************************************************************************** 1073 * Enums: cl82_cl49TxEEEStates_l 1074 */ 1075 #define cl82_cl49TxEEEStates_l_SCR_RESET_2 64 1076 #define cl82_cl49TxEEEStates_l_SCR_RESET_1 32 1077 #define cl82_cl49TxEEEStates_l_TX_WAKE 16 1078 #define cl82_cl49TxEEEStates_l_TX_REFRESH 8 1079 #define cl82_cl49TxEEEStates_l_TX_QUIET 4 1080 #define cl82_cl49TxEEEStates_l_TX_SLEEP 2 1081 #define cl82_cl49TxEEEStates_l_TX_ACTIVE 1 1082 1083 /**************************************************************************** 1084 * Enums: cl82_fec_req_enum 1085 */ 1086 #define cl82_fec_req_enum_FEC_not_supported 0 1087 #define cl82_fec_req_enum_FEC_supported_but_not_requested 1 1088 #define cl82_fec_req_enum_invalid_setting 2 1089 #define cl82_fec_req_enum_FEC_supported_and_requested 3 1090 1091 /**************************************************************************** 1092 * Enums: cl82_cl73_pause_enum 1093 */ 1094 #define cl82_cl73_pause_enum_No_PAUSE_ability 0 1095 #define cl82_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 1096 #define cl82_cl73_pause_enum_Symmetric_PAUSE_ability 1 1097 #define cl82_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 1098 1099 /**************************************************************************** 1100 * Enums: cl82_cl49TxEEEStates_c 1101 */ 1102 #define cl82_cl49TxEEEStates_c_SCR_RESET_2 6 1103 #define cl82_cl49TxEEEStates_c_SCR_RESET_1 5 1104 #define cl82_cl49TxEEEStates_c_TX_WAKE 4 1105 #define cl82_cl49TxEEEStates_c_TX_REFRESH 3 1106 #define cl82_cl49TxEEEStates_c_TX_QUIET 2 1107 #define cl82_cl49TxEEEStates_c_TX_SLEEP 1 1108 #define cl82_cl49TxEEEStates_c_TX_ACTIVE 0 1109 1110 /**************************************************************************** 1111 * Enums: cl82_cl36RxEEEStates_l 1112 */ 1113 #define cl82_cl36RxEEEStates_l_RX_LINK_FAIL 32 1114 #define cl82_cl36RxEEEStates_l_RX_WTF 16 1115 #define cl82_cl36RxEEEStates_l_RX_WAKE 8 1116 #define cl82_cl36RxEEEStates_l_RX_QUIET 4 1117 #define cl82_cl36RxEEEStates_l_RX_SLEEP 2 1118 #define cl82_cl36RxEEEStates_l_RX_ACTIVE 1 1119 1120 /**************************************************************************** 1121 * Enums: cl82_cl36RxEEEStates_c 1122 */ 1123 #define cl82_cl36RxEEEStates_c_RX_LINK_FAIL 5 1124 #define cl82_cl36RxEEEStates_c_RX_WTF 4 1125 #define cl82_cl36RxEEEStates_c_RX_WAKE 3 1126 #define cl82_cl36RxEEEStates_c_RX_QUIET 2 1127 #define cl82_cl36RxEEEStates_c_RX_SLEEP 1 1128 #define cl82_cl36RxEEEStates_c_RX_ACTIVE 0 1129 1130 /**************************************************************************** 1131 * Enums: cl82_cl49RxEEEStates_l 1132 */ 1133 #define cl82_cl49RxEEEStates_l_RX_LINK_FAIL 32 1134 #define cl82_cl49RxEEEStates_l_RX_WTF 16 1135 #define cl82_cl49RxEEEStates_l_RX_WAKE 8 1136 #define cl82_cl49RxEEEStates_l_RX_QUIET 4 1137 #define cl82_cl49RxEEEStates_l_RX_SLEEP 2 1138 #define cl82_cl49RxEEEStates_l_RX_ACTIVE 1 1139 1140 /**************************************************************************** 1141 * Enums: cl82_cl49RxEEEStates_c 1142 */ 1143 #define cl82_cl49RxEEEStates_c_RX_LINK_FAIL 5 1144 #define cl82_cl49RxEEEStates_c_RX_WTF 4 1145 #define cl82_cl49RxEEEStates_c_RX_WAKE 3 1146 #define cl82_cl49RxEEEStates_c_RX_QUIET 2 1147 #define cl82_cl49RxEEEStates_c_RX_SLEEP 1 1148 #define cl82_cl49RxEEEStates_c_RX_ACTIVE 0 1149 1150 /**************************************************************************** 1151 * Enums: cl82_cl48TxEEEStates_l 1152 */ 1153 #define cl82_cl48TxEEEStates_l_TX_REFRESH 8 1154 #define cl82_cl48TxEEEStates_l_TX_QUIET 4 1155 #define cl82_cl48TxEEEStates_l_TX_SLEEP 2 1156 #define cl82_cl48TxEEEStates_l_TX_ACTIVE 1 1157 1158 /**************************************************************************** 1159 * Enums: cl82_cl48TxEEEStates_c 1160 */ 1161 #define cl82_cl48TxEEEStates_c_TX_REFRESH 3 1162 #define cl82_cl48TxEEEStates_c_TX_QUIET 2 1163 #define cl82_cl48TxEEEStates_c_TX_SLEEP 1 1164 #define cl82_cl48TxEEEStates_c_TX_ACTIVE 0 1165 1166 /**************************************************************************** 1167 * Enums: cl82_cl48RxEEEStates_l 1168 */ 1169 #define cl82_cl48RxEEEStates_l_RX_LINK_FAIL 32 1170 #define cl82_cl48RxEEEStates_l_RX_WAKE 16 1171 #define cl82_cl48RxEEEStates_l_RX_QUIET 8 1172 #define cl82_cl48RxEEEStates_l_RX_DEACT 4 1173 #define cl82_cl48RxEEEStates_l_RX_SLEEP 2 1174 #define cl82_cl48RxEEEStates_l_RX_ACTIVE 1 1175 1176 /**************************************************************************** 1177 * Enums: cl82_cl48RxEEEStates_c 1178 */ 1179 #define cl82_cl48RxEEEStates_c_RX_LINK_FAIL 5 1180 #define cl82_cl48RxEEEStates_c_RX_WAKE 4 1181 #define cl82_cl48RxEEEStates_c_RX_QUIET 3 1182 #define cl82_cl48RxEEEStates_c_RX_DEACT 2 1183 #define cl82_cl48RxEEEStates_c_RX_SLEEP 1 1184 #define cl82_cl48RxEEEStates_c_RX_ACTIVE 0 1185 1186 /**************************************************************************** 1187 * Enums: cl82_IQP_Options 1188 */ 1189 #define cl82_IQP_Options_i50uA 0 1190 #define cl82_IQP_Options_i100uA 1 1191 #define cl82_IQP_Options_i150uA 2 1192 #define cl82_IQP_Options_i200uA 3 1193 #define cl82_IQP_Options_i250uA 4 1194 #define cl82_IQP_Options_i300uA 5 1195 #define cl82_IQP_Options_i350uA 6 1196 #define cl82_IQP_Options_i400uA 7 1197 #define cl82_IQP_Options_i450uA 8 1198 #define cl82_IQP_Options_i500uA 9 1199 #define cl82_IQP_Options_i550uA 10 1200 #define cl82_IQP_Options_i600uA 11 1201 #define cl82_IQP_Options_i650uA 12 1202 #define cl82_IQP_Options_i700uA 13 1203 #define cl82_IQP_Options_i750uA 14 1204 #define cl82_IQP_Options_i800uA 15 1205 1206 /**************************************************************************** 1207 * Enums: cl82_IDriver_Options 1208 */ 1209 #define cl82_IDriver_Options_v680mV 0 1210 #define cl82_IDriver_Options_v730mV 1 1211 #define cl82_IDriver_Options_v780mV 2 1212 #define cl82_IDriver_Options_v830mV 3 1213 #define cl82_IDriver_Options_v880mV 4 1214 #define cl82_IDriver_Options_v930mV 5 1215 #define cl82_IDriver_Options_v980mV 6 1216 #define cl82_IDriver_Options_v1010mV 7 1217 #define cl82_IDriver_Options_v1040mV 8 1218 #define cl82_IDriver_Options_v1060mV 9 1219 #define cl82_IDriver_Options_v1070mV 10 1220 #define cl82_IDriver_Options_v1080mV 11 1221 #define cl82_IDriver_Options_v1085mV 12 1222 #define cl82_IDriver_Options_v1090mV 13 1223 #define cl82_IDriver_Options_v1095mV 14 1224 #define cl82_IDriver_Options_v1100mV 15 1225 1226 /**************************************************************************** 1227 * Enums: cl82_operationModes 1228 */ 1229 #define cl82_operationModes_XGXS 0 1230 #define cl82_operationModes_XGXG_nCC 1 1231 #define cl82_operationModes_Indlane_OS8 4 1232 #define cl82_operationModes_IndLane_OS5 5 1233 #define cl82_operationModes_PCI 7 1234 #define cl82_operationModes_XGXS_nLQ 8 1235 #define cl82_operationModes_XGXS_nLQnCC 9 1236 #define cl82_operationModes_PBypass 10 1237 #define cl82_operationModes_PBypass_nDSK 11 1238 #define cl82_operationModes_ComboCoreMode 12 1239 #define cl82_operationModes_Clocks_off 15 1240 1241 /**************************************************************************** 1242 * Enums: cl82_actualSpeeds 1243 */ 1244 #define cl82_actualSpeeds_dr_10M 0 1245 #define cl82_actualSpeeds_dr_100M 1 1246 #define cl82_actualSpeeds_dr_1G 2 1247 #define cl82_actualSpeeds_dr_2p5G 3 1248 #define cl82_actualSpeeds_dr_5G_X4 4 1249 #define cl82_actualSpeeds_dr_6G_X4 5 1250 #define cl82_actualSpeeds_dr_10G_HiG 6 1251 #define cl82_actualSpeeds_dr_10G_CX4 7 1252 #define cl82_actualSpeeds_dr_12G_HiG 8 1253 #define cl82_actualSpeeds_dr_12p5G_X4 9 1254 #define cl82_actualSpeeds_dr_13G_X4 10 1255 #define cl82_actualSpeeds_dr_15G_X4 11 1256 #define cl82_actualSpeeds_dr_16G_X4 12 1257 #define cl82_actualSpeeds_dr_1G_KX 13 1258 #define cl82_actualSpeeds_dr_10G_KX4 14 1259 #define cl82_actualSpeeds_dr_10G_KR 15 1260 #define cl82_actualSpeeds_dr_5G 16 1261 #define cl82_actualSpeeds_dr_6p4G 17 1262 #define cl82_actualSpeeds_dr_20G_X4 18 1263 #define cl82_actualSpeeds_dr_21G_X4 19 1264 #define cl82_actualSpeeds_dr_25G_X4 20 1265 #define cl82_actualSpeeds_dr_10G_HiG_DXGXS 21 1266 #define cl82_actualSpeeds_dr_10G_DXGXS 22 1267 #define cl82_actualSpeeds_dr_10p5G_HiG_DXGXS 23 1268 #define cl82_actualSpeeds_dr_10p5G_DXGXS 24 1269 #define cl82_actualSpeeds_dr_12p773G_HiG_DXGXS 25 1270 #define cl82_actualSpeeds_dr_12p773G_DXGXS 26 1271 #define cl82_actualSpeeds_dr_10G_XFI 27 1272 #define cl82_actualSpeeds_dr_40G 28 1273 #define cl82_actualSpeeds_dr_20G_HiG_DXGXS 29 1274 #define cl82_actualSpeeds_dr_20G_DXGXS 30 1275 #define cl82_actualSpeeds_dr_10G_SFI 31 1276 #define cl82_actualSpeeds_dr_31p5G 32 1277 #define cl82_actualSpeeds_dr_32p7G 33 1278 #define cl82_actualSpeeds_dr_20G_SCR 34 1279 #define cl82_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 1280 #define cl82_actualSpeeds_dr_10G_DXGXS_SCR 36 1281 #define cl82_actualSpeeds_dr_12G_R2 37 1282 #define cl82_actualSpeeds_dr_10G_X2 38 1283 #define cl82_actualSpeeds_dr_40G_KR4 39 1284 #define cl82_actualSpeeds_dr_40G_CR4 40 1285 #define cl82_actualSpeeds_dr_100G_CR10 41 1286 #define cl82_actualSpeeds_dr_15p75G_DXGXS 44 1287 #define cl82_actualSpeeds_dr_20G_KR2 57 1288 #define cl82_actualSpeeds_dr_20G_CR2 58 1289 1290 /**************************************************************************** 1291 * Enums: cl82_actualSpeedsMisc1 1292 */ 1293 #define cl82_actualSpeedsMisc1_dr_2500BRCM_X1 16 1294 #define cl82_actualSpeedsMisc1_dr_5000BRCM_X4 17 1295 #define cl82_actualSpeedsMisc1_dr_6000BRCM_X4 18 1296 #define cl82_actualSpeedsMisc1_dr_10GHiGig_X4 19 1297 #define cl82_actualSpeedsMisc1_dr_10GBASE_CX4 20 1298 #define cl82_actualSpeedsMisc1_dr_12GHiGig_X4 21 1299 #define cl82_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 1300 #define cl82_actualSpeedsMisc1_dr_13GHiGig_X4 23 1301 #define cl82_actualSpeedsMisc1_dr_15GHiGig_X4 24 1302 #define cl82_actualSpeedsMisc1_dr_16GHiGig_X4 25 1303 #define cl82_actualSpeedsMisc1_dr_5000BRCM_X1 26 1304 #define cl82_actualSpeedsMisc1_dr_6363BRCM_X1 27 1305 #define cl82_actualSpeedsMisc1_dr_20GHiGig_X4 28 1306 #define cl82_actualSpeedsMisc1_dr_21GHiGig_X4 29 1307 #define cl82_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 1308 #define cl82_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 1309 1310 /**************************************************************************** 1311 * Enums: cl82_IndLaneModes 1312 */ 1313 #define cl82_IndLaneModes_SWSDR_div2 0 1314 #define cl82_IndLaneModes_SWSDR_div1 1 1315 #define cl82_IndLaneModes_DWSDR_div2 2 1316 #define cl82_IndLaneModes_DWSDR_div1 3 1317 1318 /**************************************************************************** 1319 * Enums: cl82_prbsSelect 1320 */ 1321 #define cl82_prbsSelect_prbs7 0 1322 #define cl82_prbsSelect_prbs15 1 1323 #define cl82_prbsSelect_prbs23 2 1324 #define cl82_prbsSelect_prbs31 3 1325 1326 /**************************************************************************** 1327 * Enums: cl82_vcoDivider 1328 */ 1329 #define cl82_vcoDivider_div32 0 1330 #define cl82_vcoDivider_div36 1 1331 #define cl82_vcoDivider_div40 2 1332 #define cl82_vcoDivider_div42 3 1333 #define cl82_vcoDivider_div48 4 1334 #define cl82_vcoDivider_div50 5 1335 #define cl82_vcoDivider_div52 6 1336 #define cl82_vcoDivider_div54 7 1337 #define cl82_vcoDivider_div60 8 1338 #define cl82_vcoDivider_div64 9 1339 #define cl82_vcoDivider_div66 10 1340 #define cl82_vcoDivider_div68 11 1341 #define cl82_vcoDivider_div70 12 1342 #define cl82_vcoDivider_div80 13 1343 #define cl82_vcoDivider_div92 14 1344 #define cl82_vcoDivider_div100 15 1345 1346 /**************************************************************************** 1347 * Enums: cl82_refClkSelect 1348 */ 1349 #define cl82_refClkSelect_clk_156p25MHz 1 1350 #define cl82_refClkSelect_clk_312p5Mhz 2 1351 1352 /**************************************************************************** 1353 * Enums: cl82_aerMMDdevTypeSelect 1354 */ 1355 #define cl82_aerMMDdevTypeSelect_combo_core 0 1356 #define cl82_aerMMDdevTypeSelect_PMA_PMD 1 1357 #define cl82_aerMMDdevTypeSelect_PCS 3 1358 #define cl82_aerMMDdevTypeSelect_PHY 4 1359 #define cl82_aerMMDdevTypeSelect_DTE 5 1360 #define cl82_aerMMDdevTypeSelect_CL73_AN 7 1361 1362 /**************************************************************************** 1363 * Enums: cl82_aerMMDportSelect 1364 */ 1365 #define cl82_aerMMDportSelect_ln0 0 1366 #define cl82_aerMMDportSelect_ln1 1 1367 #define cl82_aerMMDportSelect_ln2 2 1368 #define cl82_aerMMDportSelect_ln3 3 1369 #define cl82_aerMMDportSelect_BCST_ln0_1_2_3 511 1370 #define cl82_aerMMDportSelect_BCST_ln0_1 512 1371 #define cl82_aerMMDportSelect_BCST_ln2_3 513 1372 1373 /**************************************************************************** 1374 * Enums: cl82_firmwareModeSelect 1375 */ 1376 #define cl82_firmwareModeSelect_DEFAULT 0 1377 #define cl82_firmwareModeSelect_SFP_OPT_LR 1 1378 #define cl82_firmwareModeSelect_SFP_DAC 2 1379 #define cl82_firmwareModeSelect_XLAUI 3 1380 #define cl82_firmwareModeSelect_LONG_CH_6G 4 1381 1382 /**************************************************************************** 1383 * Enums: cl82_tempIdxSelect 1384 */ 1385 #define cl82_tempIdxSelect_LTE__22p9C 15 1386 #define cl82_tempIdxSelect_LTE__12p6C 14 1387 #define cl82_tempIdxSelect_LTE__3p0C 13 1388 #define cl82_tempIdxSelect_LTE_6p7C 12 1389 #define cl82_tempIdxSelect_LTE_16p4C 11 1390 #define cl82_tempIdxSelect_LTE_26p6C 10 1391 #define cl82_tempIdxSelect_LTE_36p3C 9 1392 #define cl82_tempIdxSelect_LTE_46p0C 8 1393 #define cl82_tempIdxSelect_LTE_56p2C 7 1394 #define cl82_tempIdxSelect_LTE_65p9C 6 1395 #define cl82_tempIdxSelect_LTE_75p6C 5 1396 #define cl82_tempIdxSelect_LTE_85p3C 4 1397 #define cl82_tempIdxSelect_LTE_95p5C 3 1398 #define cl82_tempIdxSelect_LTE_105p2C 2 1399 #define cl82_tempIdxSelect_LTE_114p9C 1 1400 #define cl82_tempIdxSelect_LTE_125p1C 0 1401 1402 /**************************************************************************** 1403 * Enums: cl82_port_mode 1404 */ 1405 #define cl82_port_mode_QUAD_PORT 0 1406 #define cl82_port_mode_TRI_1_PORT 1 1407 #define cl82_port_mode_TRI_2_PORT 2 1408 #define cl82_port_mode_DUAL_PORT 3 1409 #define cl82_port_mode_SINGLE_PORT 4 1410 #define cl82_port_mode_SINGLE_OCTAL_PORT 5 1411 1412 /**************************************************************************** 1413 * Enums: cl82_rev_letter_enum 1414 */ 1415 #define cl82_rev_letter_enum_REV_A 0 1416 #define cl82_rev_letter_enum_REV_B 1 1417 #define cl82_rev_letter_enum_REV_C 2 1418 #define cl82_rev_letter_enum_REV_D 3 1419 1420 /**************************************************************************** 1421 * Enums: cl82_rev_number_enum 1422 */ 1423 #define cl82_rev_number_enum_REV_0 0 1424 #define cl82_rev_number_enum_REV_1 1 1425 #define cl82_rev_number_enum_REV_2 2 1426 #define cl82_rev_number_enum_REV_3 3 1427 #define cl82_rev_number_enum_REV_4 4 1428 #define cl82_rev_number_enum_REV_5 5 1429 #define cl82_rev_number_enum_REV_6 6 1430 #define cl82_rev_number_enum_REV_7 7 1431 1432 /**************************************************************************** 1433 * Enums: cl82_bonding_enum 1434 */ 1435 #define cl82_bonding_enum_WIRE_BOND 0 1436 #define cl82_bonding_enum_FLIP_CHIP 1 1437 1438 /**************************************************************************** 1439 * Enums: cl82_tech_process 1440 */ 1441 #define cl82_tech_process_PROCESS_90NM 0 1442 #define cl82_tech_process_PROCESS_65NM 1 1443 #define cl82_tech_process_PROCESS_40NM 2 1444 #define cl82_tech_process_PROCESS_28NM 3 1445 #define cl82_tech_process_PROCESS_16NM 4 1446 1447 /**************************************************************************** 1448 * Enums: cl82_model_num 1449 */ 1450 #define cl82_model_num_SERDES_CL73 0 1451 #define cl82_model_num_XGXS_16G 1 1452 #define cl82_model_num_HYPERCORE 2 1453 #define cl82_model_num_HYPERLITE 3 1454 #define cl82_model_num_PCIE_G2_PIPE 4 1455 #define cl82_model_num_SERDES_1p25GBd 5 1456 #define cl82_model_num_SATA2 6 1457 #define cl82_model_num_QSGMII 7 1458 #define cl82_model_num_XGXS10G 8 1459 #define cl82_model_num_WARPCORE 9 1460 #define cl82_model_num_XFICORE 10 1461 #define cl82_model_num_RXFI 11 1462 #define cl82_model_num_WARPLITE 12 1463 #define cl82_model_num_PENTACORE 13 1464 #define cl82_model_num_ESM 14 1465 #define cl82_model_num_QUAD_SGMII 15 1466 #define cl82_model_num_WARPCORE_3 16 1467 #define cl82_model_num_TSC 17 1468 #define cl82_model_num_TSC4E 18 1469 #define cl82_model_num_TSC12E 19 1470 #define cl82_model_num_TSC4F 20 1471 #define cl82_model_num_TSC4F_GEN2 21 1472 #define cl82_model_num_XGXS_CL73_90NM 29 1473 #define cl82_model_num_SERDES_CL73_90NM 30 1474 #define cl82_model_num_WARPCORE3 32 1475 #define cl82_model_num_WARPCORE4_TSC 33 1476 #define cl82_model_num_RXAUI 34 1477 #define cl82_model_num_TSCE_GEN3 35 1478 #define cl82_model_num_TSC4F_GEN3 36 1479 #define cl82_model_num_TSCBH 37 1480 1481 /**************************************************************************** 1482 * Enums: cl82_payload 1483 */ 1484 #define cl82_payload_REPEAT_2_BYTES 0 1485 #define cl82_payload_RAMPING 1 1486 #define cl82_payload_CL48_CRPAT 2 1487 #define cl82_payload_CL48_CJPAT 3 1488 #define cl82_payload_CL36_LONG_CRPAT 4 1489 #define cl82_payload_CL36_SHORT_CRPAT 5 1490 1491 /**************************************************************************** 1492 * Enums: cl82_sc 1493 */ 1494 #define cl82_sc_SPEED_10G_IEEE_KR1 0 1495 #define cl82_sc_SPEED_25G_IEEE_KS1_CS1 1 1496 #define cl82_sc_SPEED_25G_IEEE_KR1_CR1 2 1497 #define cl82_sc_SPEED_40G_IEEE_KR4 3 1498 #define cl82_sc_SPEED_40G_IEEE_CR4 4 1499 #define cl82_sc_SPEED_50G_IEEE_KR1_CR1 5 1500 #define cl82_sc_SPEED_100G_IEEE_KR4 6 1501 #define cl82_sc_SPEED_100G_IEEE_CR4 7 1502 #define cl82_sc_SPEED_100G_IEEE_KR2_CR2 8 1503 #define cl82_sc_SPEED_200G_IEEE_KR4_CR4 9 1504 #define cl82_sc_SPEED_400G_IEEE_X8 10 1505 #define cl82_sc_SPEED_CL73_IEEE_20GVCO 11 1506 #define cl82_sc_SPEED_CL73_IEEE_25GVCO 12 1507 #define cl82_sc_SPEED_CL73_IEEE_26GVCO 13 1508 #define cl82_sc_SPEED_20G_BRCM_CR1 14 1509 #define cl82_sc_SPEED_20G_BRCM_KR1 15 1510 #define cl82_sc_SPEED_25G_BRCM_CR1 16 1511 #define cl82_sc_SPEED_25G_BRCM_KR1 17 1512 #define cl82_sc_SPEED_40G_BRCM_CR2 18 1513 #define cl82_sc_SPEED_40G_BRCM_KR2 19 1514 #define cl82_sc_SPEED_50G_BRCM_CR2 20 1515 #define cl82_sc_SPEED_50G_BRCM_KR2 21 1516 #define cl82_sc_SPEED_50G_BRCM_CR4 22 1517 #define cl82_sc_SPEED_50G_BRCM_KR4 23 1518 #define cl82_sc_SPEED_50G_BRCM_FEC_544_CR2_KR2 24 1519 #define cl82_sc_SPEED_RESERVED_19 25 1520 #define cl82_sc_SPEED_50G_BRCM_FEC_544_CR1_KR1 26 1521 #define cl82_sc_SPEED_50G_BRCM_NO_FEC_CR1_KR1 27 1522 #define cl82_sc_SPEED_50G_BRCM_FEC_528_CR1_KR1 28 1523 #define cl82_sc_SPEED_400G_BRCM_NO_FEC_KR8_CR8 29 1524 #define cl82_sc_SPEED_400G_BRCM_FEC_KR8_CR8 30 1525 #define cl82_sc_SPEED_200G_BRCM_NO_FEC_KR4_CR4 31 1526 #define cl82_sc_SPEED_200G_BRCM_KR4_CR4 32 1527 #define cl82_sc_SPEED_100G_BRCM_KR4_CR4 33 1528 #define cl82_sc_SPEED_RESERVED_22 34 1529 #define cl82_sc_SPEED_100G_BRCM_FEC_528_KR2_CR2 35 1530 #define cl82_sc_SPEED_100G_BRCM_NO_FEC_KR2_CR2 36 1531 #define cl82_sc_SPEED_100G_BRCM_NO_FEC_X4 37 1532 1533 /**************************************************************************** 1534 * Enums: cl82_t_fifo_modes 1535 */ 1536 #define cl82_t_fifo_modes_T_FIFO_INSERT_NO_AM 0 1537 #define cl82_t_fifo_modes_T_FIFO_INSERT_4_AM 1 1538 #define cl82_t_fifo_modes_T_FIFO_INSERT_20_AM 2 1539 #define cl82_t_fifo_modes_T_FIFO_INSERT_2_AM 3 1540 1541 /**************************************************************************** 1542 * Enums: cl82_t_enc_modes 1543 */ 1544 #define cl82_t_enc_modes_T_ENC_MODE_BYPASS 0 1545 #define cl82_t_enc_modes_T_ENC_MODE_CL49 1 1546 #define cl82_t_enc_modes_T_ENC_MODE_CL82 2 1547 1548 /**************************************************************************** 1549 * Enums: cl82_btmx_mode 1550 */ 1551 #define cl82_btmx_mode_BS_BTMX_MODE_1to1 0 1552 #define cl82_btmx_mode_BS_BTMX_MODE_2to1 1 1553 #define cl82_btmx_mode_BS_BTMX_MODE_5to1 2 1554 1555 /**************************************************************************** 1556 * Enums: cl82_t_type_cl82 1557 */ 1558 #define cl82_t_type_cl82_T_TYPE_B1 5 1559 #define cl82_t_type_cl82_T_TYPE_C 4 1560 #define cl82_t_type_cl82_T_TYPE_S 3 1561 #define cl82_t_type_cl82_T_TYPE_T 2 1562 #define cl82_t_type_cl82_T_TYPE_D 1 1563 #define cl82_t_type_cl82_T_TYPE_E 0 1564 1565 /**************************************************************************** 1566 * Enums: cl82_txsm_state_cl82 1567 */ 1568 #define cl82_txsm_state_cl82_TX_E 4 1569 #define cl82_txsm_state_cl82_TX_T 3 1570 #define cl82_txsm_state_cl82_TX_D 2 1571 #define cl82_txsm_state_cl82_TX_C 1 1572 #define cl82_txsm_state_cl82_TX_INIT 0 1573 1574 /**************************************************************************** 1575 * Enums: cl82_ltxsm_state_cl82 1576 */ 1577 #define cl82_ltxsm_state_cl82_TX_E 16 1578 #define cl82_ltxsm_state_cl82_TX_T 8 1579 #define cl82_ltxsm_state_cl82_TX_D 4 1580 #define cl82_ltxsm_state_cl82_TX_C 2 1581 #define cl82_ltxsm_state_cl82_TX_INIT 1 1582 1583 /**************************************************************************** 1584 * Enums: cl82_r_type_coded_cl82 1585 */ 1586 #define cl82_r_type_coded_cl82_R_TYPE_B1 32 1587 #define cl82_r_type_coded_cl82_R_TYPE_C 16 1588 #define cl82_r_type_coded_cl82_R_TYPE_S 8 1589 #define cl82_r_type_coded_cl82_R_TYPE_T 4 1590 #define cl82_r_type_coded_cl82_R_TYPE_D 2 1591 #define cl82_r_type_coded_cl82_R_TYPE_E 1 1592 1593 /**************************************************************************** 1594 * Enums: cl82_rxsm_state_cl82 1595 */ 1596 #define cl82_rxsm_state_cl82_RX_E 16 1597 #define cl82_rxsm_state_cl82_RX_T 8 1598 #define cl82_rxsm_state_cl82_RX_D 4 1599 #define cl82_rxsm_state_cl82_RX_C 2 1600 #define cl82_rxsm_state_cl82_RX_INIT 1 1601 1602 /**************************************************************************** 1603 * Enums: cl82_deskew_state 1604 */ 1605 #define cl82_deskew_state_ALIGN_ACQUIRED 2 1606 #define cl82_deskew_state_LOSS_OF_ALIGNMENT 1 1607 1608 /**************************************************************************** 1609 * Enums: cl82_os_mode_enum 1610 */ 1611 #define cl82_os_mode_enum_OS_MODE_1 0 1612 #define cl82_os_mode_enum_OS_MODE_2 1 1613 #define cl82_os_mode_enum_OS_MODE_4 2 1614 #define cl82_os_mode_enum_OS_MODE_16p5 8 1615 #define cl82_os_mode_enum_OS_MODE_20p625 12 1616 1617 /**************************************************************************** 1618 * Enums: cl82_scr_modes 1619 */ 1620 #define cl82_scr_modes_T_SCR_MODE_BYPASS 0 1621 #define cl82_scr_modes_T_SCR_MODE_CL49 1 1622 #define cl82_scr_modes_T_SCR_MODE_40G_2_LANE 2 1623 #define cl82_scr_modes_T_SCR_MODE_100G 3 1624 #define cl82_scr_modes_T_SCR_MODE_20G 4 1625 #define cl82_scr_modes_T_SCR_MODE_40G_4_LANE 5 1626 1627 /**************************************************************************** 1628 * Enums: cl82_descr_modes 1629 */ 1630 #define cl82_descr_modes_R_DESCR_MODE_BYPASS 0 1631 #define cl82_descr_modes_R_DESCR_MODE_CL49 1 1632 #define cl82_descr_modes_R_DESCR_MODE_CL82 2 1633 1634 /**************************************************************************** 1635 * Enums: cl82_r_dec_tl_mode 1636 */ 1637 #define cl82_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 1638 #define cl82_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 1639 #define cl82_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 1640 1641 /**************************************************************************** 1642 * Enums: cl82_r_dec_fsm_mode 1643 */ 1644 #define cl82_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 1645 #define cl82_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 1646 #define cl82_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 1647 1648 /**************************************************************************** 1649 * Enums: cl82_r_deskew_mode 1650 */ 1651 #define cl82_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 1652 #define cl82_r_deskew_mode_R_DESKEW_MODE_20G 1 1653 #define cl82_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 1654 #define cl82_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 1655 #define cl82_r_deskew_mode_R_DESKEW_MODE_100G 4 1656 #define cl82_r_deskew_mode_R_DESKEW_MODE_CL49 5 1657 #define cl82_r_deskew_mode_R_DESKEW_MODE_CL91_QUAD 6 1658 #define cl82_r_deskew_mode_R_DESKEW_MODE_CL91_SINGLE_BRCM 7 1659 #define cl82_r_deskew_mode_R_DESKEW_MODE_CL91_DUAL_BRCM 8 1660 #define cl82_r_deskew_mode_R_DESKEW_MODE_CL91_FC 9 1661 1662 /**************************************************************************** 1663 * Enums: cl82_bs_dist_modes 1664 */ 1665 #define cl82_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 1666 #define cl82_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 1667 #define cl82_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 1668 #define cl82_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 1669 1670 /**************************************************************************** 1671 * Enums: cl82_cl49_t_type 1672 */ 1673 #define cl82_cl49_t_type_BAD_T_TYPE 15 1674 #define cl82_cl49_t_type_T_TYPE_B0 11 1675 #define cl82_cl49_t_type_T_TYPE_OB 10 1676 #define cl82_cl49_t_type_T_TYPE_B1 9 1677 #define cl82_cl49_t_type_T_TYPE_DB 8 1678 #define cl82_cl49_t_type_T_TYPE_FC 7 1679 #define cl82_cl49_t_type_T_TYPE_TB 6 1680 #define cl82_cl49_t_type_T_TYPE_LI 5 1681 #define cl82_cl49_t_type_T_TYPE_C 4 1682 #define cl82_cl49_t_type_T_TYPE_S 3 1683 #define cl82_cl49_t_type_T_TYPE_T 2 1684 #define cl82_cl49_t_type_T_TYPE_D 1 1685 #define cl82_cl49_t_type_T_TYPE_E 0 1686 1687 /**************************************************************************** 1688 * Enums: cl82_cl49_txsm_states 1689 */ 1690 #define cl82_cl49_txsm_states_TX_LI 5 1691 #define cl82_cl49_txsm_states_TX_E 4 1692 #define cl82_cl49_txsm_states_TX_T 3 1693 #define cl82_cl49_txsm_states_TX_D 2 1694 #define cl82_cl49_txsm_states_TX_C 1 1695 #define cl82_cl49_txsm_states_TX_INIT 0 1696 1697 /**************************************************************************** 1698 * Enums: cl82_cl49_ltxsm_states 1699 */ 1700 #define cl82_cl49_ltxsm_states_TX_LI 32 1701 #define cl82_cl49_ltxsm_states_TX_E 16 1702 #define cl82_cl49_ltxsm_states_TX_T 8 1703 #define cl82_cl49_ltxsm_states_TX_D 4 1704 #define cl82_cl49_ltxsm_states_TX_C 2 1705 #define cl82_cl49_ltxsm_states_TX_INIT 1 1706 1707 /**************************************************************************** 1708 * Enums: cl82_burst_error_mode 1709 */ 1710 #define cl82_burst_error_mode_BURST_ERROR_11_BITS 0 1711 #define cl82_burst_error_mode_BURST_ERROR_16_BITS 1 1712 #define cl82_burst_error_mode_BURST_ERROR_17_BITS 2 1713 #define cl82_burst_error_mode_BURST_ERROR_18_BITS 3 1714 #define cl82_burst_error_mode_BURST_ERROR_19_BITS 4 1715 #define cl82_burst_error_mode_BURST_ERROR_20_BITS 5 1716 #define cl82_burst_error_mode_BURST_ERROR_21_BITS 6 1717 #define cl82_burst_error_mode_BURST_ERROR_22_BITS 7 1718 #define cl82_burst_error_mode_BURST_ERROR_23_BITS 8 1719 #define cl82_burst_error_mode_BURST_ERROR_24_BITS 9 1720 #define cl82_burst_error_mode_BURST_ERROR_25_BITS 10 1721 #define cl82_burst_error_mode_BURST_ERROR_26_BITS 11 1722 #define cl82_burst_error_mode_BURST_ERROR_27_BITS 12 1723 #define cl82_burst_error_mode_BURST_ERROR_28_BITS 13 1724 #define cl82_burst_error_mode_BURST_ERROR_29_BITS 14 1725 #define cl82_burst_error_mode_BURST_ERROR_30_BITS 15 1726 #define cl82_burst_error_mode_BURST_ERROR_31_BITS 16 1727 #define cl82_burst_error_mode_BURST_ERROR_32_BITS 17 1728 #define cl82_burst_error_mode_BURST_ERROR_33_BITS 18 1729 #define cl82_burst_error_mode_BURST_ERROR_34_BITS 19 1730 #define cl82_burst_error_mode_BURST_ERROR_35_BITS 20 1731 #define cl82_burst_error_mode_BURST_ERROR_36_BITS 21 1732 #define cl82_burst_error_mode_BURST_ERROR_37_BITS 22 1733 #define cl82_burst_error_mode_BURST_ERROR_38_BITS 23 1734 #define cl82_burst_error_mode_BURST_ERROR_39_BITS 24 1735 #define cl82_burst_error_mode_BURST_ERROR_40_BITS 25 1736 #define cl82_burst_error_mode_BURST_ERROR_41_BITS 26 1737 1738 /**************************************************************************** 1739 * Enums: cl82_bermon_state 1740 */ 1741 #define cl82_bermon_state_HI_BER 4 1742 #define cl82_bermon_state_GOOD_BER 3 1743 #define cl82_bermon_state_BER_TEST_SH 2 1744 #define cl82_bermon_state_START_TIMER 1 1745 #define cl82_bermon_state_BER_MT_INIT 0 1746 1747 /**************************************************************************** 1748 * Enums: cl82_rxsm_state_cl49 1749 */ 1750 #define cl82_rxsm_state_cl49_RX_LI 32 1751 #define cl82_rxsm_state_cl49_RX_E 16 1752 #define cl82_rxsm_state_cl49_RX_T 8 1753 #define cl82_rxsm_state_cl49_RX_D 4 1754 #define cl82_rxsm_state_cl49_RX_C 2 1755 #define cl82_rxsm_state_cl49_RX_INIT 1 1756 1757 /**************************************************************************** 1758 * Enums: cl82_r_type 1759 */ 1760 #define cl82_r_type_BAD_R_TYPE 15 1761 #define cl82_r_type_R_TYPE_B0 11 1762 #define cl82_r_type_R_TYPE_OB 10 1763 #define cl82_r_type_R_TYPE_B1 9 1764 #define cl82_r_type_R_TYPE_DB 8 1765 #define cl82_r_type_R_TYPE_FC 7 1766 #define cl82_r_type_R_TYPE_TB 6 1767 #define cl82_r_type_R_TYPE_LI 5 1768 #define cl82_r_type_R_TYPE_C 4 1769 #define cl82_r_type_R_TYPE_S 3 1770 #define cl82_r_type_R_TYPE_T 2 1771 #define cl82_r_type_R_TYPE_D 1 1772 #define cl82_r_type_R_TYPE_E 0 1773 1774 /**************************************************************************** 1775 * Enums: cl82_am_lock_state 1776 */ 1777 #define cl82_am_lock_state_INVALID_AM 512 1778 #define cl82_am_lock_state_GOOD_AM 256 1779 #define cl82_am_lock_state_COMP_AM 128 1780 #define cl82_am_lock_state_TIMER_2 64 1781 #define cl82_am_lock_state_AM_2_GOOD 32 1782 #define cl82_am_lock_state_COMP_2ND 16 1783 #define cl82_am_lock_state_TIMER_1 8 1784 #define cl82_am_lock_state_FIND_1ST 4 1785 #define cl82_am_lock_state_AM_RESET_CNT 2 1786 #define cl82_am_lock_state_AM_LOCK_INIT 1 1787 1788 /**************************************************************************** 1789 * Enums: cl82_msg_selector 1790 */ 1791 #define cl82_msg_selector_RESERVED 0 1792 #define cl82_msg_selector_VALUE_802p3 1 1793 #define cl82_msg_selector_VALUE_802p9 2 1794 #define cl82_msg_selector_VALUE_802p5 3 1795 #define cl82_msg_selector_VALUE_1394 4 1796 1797 /**************************************************************************** 1798 * Enums: cl82_synce_enum_stage1 1799 */ 1800 #define cl82_synce_enum_stage1_SYNCE_NO_DIV 0 1801 #define cl82_synce_enum_stage1_SYNCE_DIV_7 1 1802 #define cl82_synce_enum_stage1_SYNCE_DIV_11 2 1803 1804 /**************************************************************************** 1805 * Enums: cl82_synce_enum_stage0 1806 */ 1807 #define cl82_synce_enum_stage0_SYNCE_NO_DIV 0 1808 #define cl82_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 1809 #define cl82_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 1810 1811 /**************************************************************************** 1812 * Enums: cl82_cl91_sync_state 1813 */ 1814 #define cl82_cl91_sync_state_FIND_1ST 0 1815 #define cl82_cl91_sync_state_COUNT_NEXT 1 1816 #define cl82_cl91_sync_state_COMP_2ND 2 1817 #define cl82_cl91_sync_state_TWO_GOOD 3 1818 1819 /**************************************************************************** 1820 * Enums: cl82_RS_FEC_sync_state 1821 */ 1822 #define cl82_RS_FEC_sync_state_LOCK_INIT 0 1823 #define cl82_RS_FEC_sync_state_FIND_1ST 1 1824 #define cl82_RS_FEC_sync_state_COUNT_NEXT 2 1825 #define cl82_RS_FEC_sync_state_COMP_2ND 3 1826 #define cl82_RS_FEC_sync_state_TWO_GOOD 4 1827 1828 /**************************************************************************** 1829 * Enums: cl82_cl91_algn_state 1830 */ 1831 #define cl82_cl91_algn_state_LOSS_OF_ALIGNMENT 0 1832 #define cl82_cl91_algn_state_DESKEW 1 1833 #define cl82_cl91_algn_state_DESKEW_FAIL 2 1834 #define cl82_cl91_algn_state_ALIGN_ACQUIRED 3 1835 #define cl82_cl91_algn_state_CW_GOOD 4 1836 #define cl82_cl91_algn_state_CW_BAD 5 1837 #define cl82_cl91_algn_state_THREE_BAD 6 1838 1839 /**************************************************************************** 1840 * Enums: cl82_RS_FEC_algn_state 1841 */ 1842 #define cl82_RS_FEC_algn_state_LOSS_OF_ALIGNMENT 0 1843 #define cl82_RS_FEC_algn_state_DESKEW 1 1844 #define cl82_RS_FEC_algn_state_DESKEW_FAIL 2 1845 #define cl82_RS_FEC_algn_state_ALIGN_ACQUIRED 3 1846 #define cl82_RS_FEC_algn_state_CW_GOOD 4 1847 #define cl82_RS_FEC_algn_state_CW_BAD 5 1848 #define cl82_RS_FEC_algn_state_THREE_BAD 6 1849 1850 /**************************************************************************** 1851 * Enums: cl82_fec_sel_override 1852 */ 1853 #define cl82_fec_sel_override_NO_OVERRIDE 0 1854 #define cl82_fec_sel_override_NO_FEC 1 1855 #define cl82_fec_sel_override_FEC_CL74 2 1856 #define cl82_fec_sel_override_FEC_CL91 3 1857 1858 /**************************************************************************** 1859 * Enums: cl82_cl91_blksync_mode 1860 */ 1861 #define cl82_cl91_blksync_mode_R_BLKSYNC_NO_CL91_FEC 0 1862 #define cl82_cl91_blksync_mode_R_BLKSYNC_CL91_QUAD_LANE_FEC 1 1863 #define cl82_cl91_blksync_mode_R_BLKSYNC_CL91_DUAL_LANE_FEC 2 1864 #define cl82_cl91_blksync_mode_R_BLKSYNC_CL91_SINGLE_LANE_FEC 3 1865 #define cl82_cl91_blksync_mode_R_BLKSYNC_CL91_FC_FEC 4 1866 1867 /**************************************************************************** 1868 * Enums: cl82_r_merge_mode 1869 */ 1870 #define cl82_r_merge_mode_R_MERGE_MODE_BYPASS 0 1871 #define cl82_r_merge_mode_R_MERGE_MODE_CL91_FC 1 1872 #define cl82_r_merge_mode_R_MERGE_MODE_CL91_SINGLE_LANE 2 1873 #define cl82_r_merge_mode_R_MERGE_MODE_CL91_DUAL_LANE 3 1874 #define cl82_r_merge_mode_R_MERGE_MODE_CL91_QUAD_LANE 4 1875 1876 /**************************************************************************** 1877 * Enums: cl82_r_tc_mode 1878 */ 1879 #define cl82_r_tc_mode_R_TC_MODE_SINGLE 0 1880 #define cl82_r_tc_mode_R_TC_MODE_DUAL 1 1881 #define cl82_r_tc_mode_R_TC_MODE_QUAD 2 1882 1883 /**************************************************************************** 1884 * Enums: cl82_r_tc_out_mode 1885 */ 1886 #define cl82_r_tc_out_mode_R_TC_OUT_MODE_SINGLE 0 1887 #define cl82_r_tc_out_mode_R_TC_OUT_MODE_DUAL 1 1888 #define cl82_r_tc_out_mode_R_TC_OUT_MODE_QUAD 2 1889 1890 /**************************************************************************** 1891 * Enums: cl82_cl91_fec_mode 1892 */ 1893 #define cl82_cl91_fec_mode_NO_CL91_FEC 0 1894 #define cl82_cl91_fec_mode_CL91_SINGLE_LANE_FC 1 1895 #define cl82_cl91_fec_mode_CL91_SINGLE_LANE_BRCM_PROP 2 1896 #define cl82_cl91_fec_mode_CL91_DUAL_LANE_BRCM_PROP 3 1897 #define cl82_cl91_fec_mode_CL91_QUAD_LANE 4 1898 #define cl82_cl91_fec_mode_IEEE_25G_CL91_SINGLE_LANE 5 1899 1900 /**************************************************************************** 1901 * Enums: cl82_RS_FEC_fec_mode 1902 */ 1903 #define cl82_RS_FEC_fec_mode_NO_RS_FEC_FEC 0 1904 #define cl82_RS_FEC_fec_mode_N_A 1 1905 #define cl82_RS_FEC_fec_mode_RS_FEC_SINGLE_LANE_BRCM_PROP 2 1906 #define cl82_RS_FEC_fec_mode_RS_FEC_DUAL_LANE_BRCM_PROP 3 1907 #define cl82_RS_FEC_fec_mode_RS_FEC_QUAD_LANE 4 1908 #define cl82_RS_FEC_fec_mode_IEEE_25G_RS_FEC_SINGLE_LANE 5 1909 1910 /**************************************************************************** 1911 * Enums: cl82_am_spacing_mul 1912 */ 1913 #define cl82_am_spacing_mul_AM_SPACING_MUL_2 0 1914 #define cl82_am_spacing_mul_AM_SPACING_MUL_4 1 1915 #define cl82_am_spacing_mul_AM_SPACING_MUL_5 2 1916 #define cl82_am_spacing_mul_AM_SPACING_MUL_20 3 1917 1918 /**************************************************************************** 1919 * Enums: main0_cl36TxEEEStates_l 1920 */ 1921 #define main0_cl36TxEEEStates_l_TX_REFRESH 8 1922 #define main0_cl36TxEEEStates_l_TX_QUIET 4 1923 #define main0_cl36TxEEEStates_l_TX_SLEEP 2 1924 #define main0_cl36TxEEEStates_l_TX_ACTIVE 1 1925 1926 /**************************************************************************** 1927 * Enums: main0_cl36TxEEEStates_c 1928 */ 1929 #define main0_cl36TxEEEStates_c_TX_REFRESH 3 1930 #define main0_cl36TxEEEStates_c_TX_QUIET 2 1931 #define main0_cl36TxEEEStates_c_TX_SLEEP 1 1932 #define main0_cl36TxEEEStates_c_TX_ACTIVE 0 1933 1934 /**************************************************************************** 1935 * Enums: main0_cl49TxEEEStates_l 1936 */ 1937 #define main0_cl49TxEEEStates_l_SCR_RESET_2 64 1938 #define main0_cl49TxEEEStates_l_SCR_RESET_1 32 1939 #define main0_cl49TxEEEStates_l_TX_WAKE 16 1940 #define main0_cl49TxEEEStates_l_TX_REFRESH 8 1941 #define main0_cl49TxEEEStates_l_TX_QUIET 4 1942 #define main0_cl49TxEEEStates_l_TX_SLEEP 2 1943 #define main0_cl49TxEEEStates_l_TX_ACTIVE 1 1944 1945 /**************************************************************************** 1946 * Enums: main0_fec_req_enum 1947 */ 1948 #define main0_fec_req_enum_FEC_not_supported 0 1949 #define main0_fec_req_enum_FEC_supported_but_not_requested 1 1950 #define main0_fec_req_enum_invalid_setting 2 1951 #define main0_fec_req_enum_FEC_supported_and_requested 3 1952 1953 /**************************************************************************** 1954 * Enums: main0_cl73_pause_enum 1955 */ 1956 #define main0_cl73_pause_enum_No_PAUSE_ability 0 1957 #define main0_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 1958 #define main0_cl73_pause_enum_Symmetric_PAUSE_ability 1 1959 #define main0_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 1960 1961 /**************************************************************************** 1962 * Enums: main0_cl49TxEEEStates_c 1963 */ 1964 #define main0_cl49TxEEEStates_c_SCR_RESET_2 6 1965 #define main0_cl49TxEEEStates_c_SCR_RESET_1 5 1966 #define main0_cl49TxEEEStates_c_TX_WAKE 4 1967 #define main0_cl49TxEEEStates_c_TX_REFRESH 3 1968 #define main0_cl49TxEEEStates_c_TX_QUIET 2 1969 #define main0_cl49TxEEEStates_c_TX_SLEEP 1 1970 #define main0_cl49TxEEEStates_c_TX_ACTIVE 0 1971 1972 /**************************************************************************** 1973 * Enums: main0_cl36RxEEEStates_l 1974 */ 1975 #define main0_cl36RxEEEStates_l_RX_LINK_FAIL 32 1976 #define main0_cl36RxEEEStates_l_RX_WTF 16 1977 #define main0_cl36RxEEEStates_l_RX_WAKE 8 1978 #define main0_cl36RxEEEStates_l_RX_QUIET 4 1979 #define main0_cl36RxEEEStates_l_RX_SLEEP 2 1980 #define main0_cl36RxEEEStates_l_RX_ACTIVE 1 1981 1982 /**************************************************************************** 1983 * Enums: main0_cl36RxEEEStates_c 1984 */ 1985 #define main0_cl36RxEEEStates_c_RX_LINK_FAIL 5 1986 #define main0_cl36RxEEEStates_c_RX_WTF 4 1987 #define main0_cl36RxEEEStates_c_RX_WAKE 3 1988 #define main0_cl36RxEEEStates_c_RX_QUIET 2 1989 #define main0_cl36RxEEEStates_c_RX_SLEEP 1 1990 #define main0_cl36RxEEEStates_c_RX_ACTIVE 0 1991 1992 /**************************************************************************** 1993 * Enums: main0_cl49RxEEEStates_l 1994 */ 1995 #define main0_cl49RxEEEStates_l_RX_LINK_FAIL 32 1996 #define main0_cl49RxEEEStates_l_RX_WTF 16 1997 #define main0_cl49RxEEEStates_l_RX_WAKE 8 1998 #define main0_cl49RxEEEStates_l_RX_QUIET 4 1999 #define main0_cl49RxEEEStates_l_RX_SLEEP 2 2000 #define main0_cl49RxEEEStates_l_RX_ACTIVE 1 2001 2002 /**************************************************************************** 2003 * Enums: main0_cl49RxEEEStates_c 2004 */ 2005 #define main0_cl49RxEEEStates_c_RX_LINK_FAIL 5 2006 #define main0_cl49RxEEEStates_c_RX_WTF 4 2007 #define main0_cl49RxEEEStates_c_RX_WAKE 3 2008 #define main0_cl49RxEEEStates_c_RX_QUIET 2 2009 #define main0_cl49RxEEEStates_c_RX_SLEEP 1 2010 #define main0_cl49RxEEEStates_c_RX_ACTIVE 0 2011 2012 /**************************************************************************** 2013 * Enums: main0_cl48TxEEEStates_l 2014 */ 2015 #define main0_cl48TxEEEStates_l_TX_REFRESH 8 2016 #define main0_cl48TxEEEStates_l_TX_QUIET 4 2017 #define main0_cl48TxEEEStates_l_TX_SLEEP 2 2018 #define main0_cl48TxEEEStates_l_TX_ACTIVE 1 2019 2020 /**************************************************************************** 2021 * Enums: main0_cl48TxEEEStates_c 2022 */ 2023 #define main0_cl48TxEEEStates_c_TX_REFRESH 3 2024 #define main0_cl48TxEEEStates_c_TX_QUIET 2 2025 #define main0_cl48TxEEEStates_c_TX_SLEEP 1 2026 #define main0_cl48TxEEEStates_c_TX_ACTIVE 0 2027 2028 /**************************************************************************** 2029 * Enums: main0_cl48RxEEEStates_l 2030 */ 2031 #define main0_cl48RxEEEStates_l_RX_LINK_FAIL 32 2032 #define main0_cl48RxEEEStates_l_RX_WAKE 16 2033 #define main0_cl48RxEEEStates_l_RX_QUIET 8 2034 #define main0_cl48RxEEEStates_l_RX_DEACT 4 2035 #define main0_cl48RxEEEStates_l_RX_SLEEP 2 2036 #define main0_cl48RxEEEStates_l_RX_ACTIVE 1 2037 2038 /**************************************************************************** 2039 * Enums: main0_cl48RxEEEStates_c 2040 */ 2041 #define main0_cl48RxEEEStates_c_RX_LINK_FAIL 5 2042 #define main0_cl48RxEEEStates_c_RX_WAKE 4 2043 #define main0_cl48RxEEEStates_c_RX_QUIET 3 2044 #define main0_cl48RxEEEStates_c_RX_DEACT 2 2045 #define main0_cl48RxEEEStates_c_RX_SLEEP 1 2046 #define main0_cl48RxEEEStates_c_RX_ACTIVE 0 2047 2048 /**************************************************************************** 2049 * Enums: main0_IQP_Options 2050 */ 2051 #define main0_IQP_Options_i50uA 0 2052 #define main0_IQP_Options_i100uA 1 2053 #define main0_IQP_Options_i150uA 2 2054 #define main0_IQP_Options_i200uA 3 2055 #define main0_IQP_Options_i250uA 4 2056 #define main0_IQP_Options_i300uA 5 2057 #define main0_IQP_Options_i350uA 6 2058 #define main0_IQP_Options_i400uA 7 2059 #define main0_IQP_Options_i450uA 8 2060 #define main0_IQP_Options_i500uA 9 2061 #define main0_IQP_Options_i550uA 10 2062 #define main0_IQP_Options_i600uA 11 2063 #define main0_IQP_Options_i650uA 12 2064 #define main0_IQP_Options_i700uA 13 2065 #define main0_IQP_Options_i750uA 14 2066 #define main0_IQP_Options_i800uA 15 2067 2068 /**************************************************************************** 2069 * Enums: main0_IDriver_Options 2070 */ 2071 #define main0_IDriver_Options_v680mV 0 2072 #define main0_IDriver_Options_v730mV 1 2073 #define main0_IDriver_Options_v780mV 2 2074 #define main0_IDriver_Options_v830mV 3 2075 #define main0_IDriver_Options_v880mV 4 2076 #define main0_IDriver_Options_v930mV 5 2077 #define main0_IDriver_Options_v980mV 6 2078 #define main0_IDriver_Options_v1010mV 7 2079 #define main0_IDriver_Options_v1040mV 8 2080 #define main0_IDriver_Options_v1060mV 9 2081 #define main0_IDriver_Options_v1070mV 10 2082 #define main0_IDriver_Options_v1080mV 11 2083 #define main0_IDriver_Options_v1085mV 12 2084 #define main0_IDriver_Options_v1090mV 13 2085 #define main0_IDriver_Options_v1095mV 14 2086 #define main0_IDriver_Options_v1100mV 15 2087 2088 /**************************************************************************** 2089 * Enums: main0_operationModes 2090 */ 2091 #define main0_operationModes_XGXS 0 2092 #define main0_operationModes_XGXG_nCC 1 2093 #define main0_operationModes_Indlane_OS8 4 2094 #define main0_operationModes_IndLane_OS5 5 2095 #define main0_operationModes_PCI 7 2096 #define main0_operationModes_XGXS_nLQ 8 2097 #define main0_operationModes_XGXS_nLQnCC 9 2098 #define main0_operationModes_PBypass 10 2099 #define main0_operationModes_PBypass_nDSK 11 2100 #define main0_operationModes_ComboCoreMode 12 2101 #define main0_operationModes_Clocks_off 15 2102 2103 /**************************************************************************** 2104 * Enums: main0_actualSpeeds 2105 */ 2106 #define main0_actualSpeeds_dr_10M 0 2107 #define main0_actualSpeeds_dr_100M 1 2108 #define main0_actualSpeeds_dr_1G 2 2109 #define main0_actualSpeeds_dr_2p5G 3 2110 #define main0_actualSpeeds_dr_5G_X4 4 2111 #define main0_actualSpeeds_dr_6G_X4 5 2112 #define main0_actualSpeeds_dr_10G_HiG 6 2113 #define main0_actualSpeeds_dr_10G_CX4 7 2114 #define main0_actualSpeeds_dr_12G_HiG 8 2115 #define main0_actualSpeeds_dr_12p5G_X4 9 2116 #define main0_actualSpeeds_dr_13G_X4 10 2117 #define main0_actualSpeeds_dr_15G_X4 11 2118 #define main0_actualSpeeds_dr_16G_X4 12 2119 #define main0_actualSpeeds_dr_1G_KX 13 2120 #define main0_actualSpeeds_dr_10G_KX4 14 2121 #define main0_actualSpeeds_dr_10G_KR 15 2122 #define main0_actualSpeeds_dr_5G 16 2123 #define main0_actualSpeeds_dr_6p4G 17 2124 #define main0_actualSpeeds_dr_20G_X4 18 2125 #define main0_actualSpeeds_dr_21G_X4 19 2126 #define main0_actualSpeeds_dr_25G_X4 20 2127 #define main0_actualSpeeds_dr_10G_HiG_DXGXS 21 2128 #define main0_actualSpeeds_dr_10G_DXGXS 22 2129 #define main0_actualSpeeds_dr_10p5G_HiG_DXGXS 23 2130 #define main0_actualSpeeds_dr_10p5G_DXGXS 24 2131 #define main0_actualSpeeds_dr_12p773G_HiG_DXGXS 25 2132 #define main0_actualSpeeds_dr_12p773G_DXGXS 26 2133 #define main0_actualSpeeds_dr_10G_XFI 27 2134 #define main0_actualSpeeds_dr_40G 28 2135 #define main0_actualSpeeds_dr_20G_HiG_DXGXS 29 2136 #define main0_actualSpeeds_dr_20G_DXGXS 30 2137 #define main0_actualSpeeds_dr_10G_SFI 31 2138 #define main0_actualSpeeds_dr_31p5G 32 2139 #define main0_actualSpeeds_dr_32p7G 33 2140 #define main0_actualSpeeds_dr_20G_SCR 34 2141 #define main0_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 2142 #define main0_actualSpeeds_dr_10G_DXGXS_SCR 36 2143 #define main0_actualSpeeds_dr_12G_R2 37 2144 #define main0_actualSpeeds_dr_10G_X2 38 2145 #define main0_actualSpeeds_dr_40G_KR4 39 2146 #define main0_actualSpeeds_dr_40G_CR4 40 2147 #define main0_actualSpeeds_dr_100G_CR10 41 2148 #define main0_actualSpeeds_dr_15p75G_DXGXS 44 2149 #define main0_actualSpeeds_dr_20G_KR2 57 2150 #define main0_actualSpeeds_dr_20G_CR2 58 2151 2152 /**************************************************************************** 2153 * Enums: main0_actualSpeedsMisc1 2154 */ 2155 #define main0_actualSpeedsMisc1_dr_2500BRCM_X1 16 2156 #define main0_actualSpeedsMisc1_dr_5000BRCM_X4 17 2157 #define main0_actualSpeedsMisc1_dr_6000BRCM_X4 18 2158 #define main0_actualSpeedsMisc1_dr_10GHiGig_X4 19 2159 #define main0_actualSpeedsMisc1_dr_10GBASE_CX4 20 2160 #define main0_actualSpeedsMisc1_dr_12GHiGig_X4 21 2161 #define main0_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 2162 #define main0_actualSpeedsMisc1_dr_13GHiGig_X4 23 2163 #define main0_actualSpeedsMisc1_dr_15GHiGig_X4 24 2164 #define main0_actualSpeedsMisc1_dr_16GHiGig_X4 25 2165 #define main0_actualSpeedsMisc1_dr_5000BRCM_X1 26 2166 #define main0_actualSpeedsMisc1_dr_6363BRCM_X1 27 2167 #define main0_actualSpeedsMisc1_dr_20GHiGig_X4 28 2168 #define main0_actualSpeedsMisc1_dr_21GHiGig_X4 29 2169 #define main0_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 2170 #define main0_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 2171 2172 /**************************************************************************** 2173 * Enums: main0_IndLaneModes 2174 */ 2175 #define main0_IndLaneModes_SWSDR_div2 0 2176 #define main0_IndLaneModes_SWSDR_div1 1 2177 #define main0_IndLaneModes_DWSDR_div2 2 2178 #define main0_IndLaneModes_DWSDR_div1 3 2179 2180 /**************************************************************************** 2181 * Enums: main0_prbsSelect 2182 */ 2183 #define main0_prbsSelect_prbs7 0 2184 #define main0_prbsSelect_prbs15 1 2185 #define main0_prbsSelect_prbs23 2 2186 #define main0_prbsSelect_prbs31 3 2187 2188 /**************************************************************************** 2189 * Enums: main0_vcoDivider 2190 */ 2191 #define main0_vcoDivider_div32 0 2192 #define main0_vcoDivider_div36 1 2193 #define main0_vcoDivider_div40 2 2194 #define main0_vcoDivider_div42 3 2195 #define main0_vcoDivider_div48 4 2196 #define main0_vcoDivider_div50 5 2197 #define main0_vcoDivider_div52 6 2198 #define main0_vcoDivider_div54 7 2199 #define main0_vcoDivider_div60 8 2200 #define main0_vcoDivider_div64 9 2201 #define main0_vcoDivider_div66 10 2202 #define main0_vcoDivider_div68 11 2203 #define main0_vcoDivider_div70 12 2204 #define main0_vcoDivider_div80 13 2205 #define main0_vcoDivider_div92 14 2206 #define main0_vcoDivider_div100 15 2207 2208 /**************************************************************************** 2209 * Enums: main0_refClkSelect 2210 */ 2211 #define main0_refClkSelect_clk_156p25MHz 1 2212 #define main0_refClkSelect_clk_312p5Mhz 2 2213 2214 /**************************************************************************** 2215 * Enums: main0_aerMMDdevTypeSelect 2216 */ 2217 #define main0_aerMMDdevTypeSelect_combo_core 0 2218 #define main0_aerMMDdevTypeSelect_PMA_PMD 1 2219 #define main0_aerMMDdevTypeSelect_PCS 3 2220 #define main0_aerMMDdevTypeSelect_PHY 4 2221 #define main0_aerMMDdevTypeSelect_DTE 5 2222 #define main0_aerMMDdevTypeSelect_CL73_AN 7 2223 2224 /**************************************************************************** 2225 * Enums: main0_aerMMDportSelect 2226 */ 2227 #define main0_aerMMDportSelect_ln0 0 2228 #define main0_aerMMDportSelect_ln1 1 2229 #define main0_aerMMDportSelect_ln2 2 2230 #define main0_aerMMDportSelect_ln3 3 2231 #define main0_aerMMDportSelect_BCST_ln0_1_2_3 511 2232 #define main0_aerMMDportSelect_BCST_ln0_1 512 2233 #define main0_aerMMDportSelect_BCST_ln2_3 513 2234 2235 /**************************************************************************** 2236 * Enums: main0_firmwareModeSelect 2237 */ 2238 #define main0_firmwareModeSelect_DEFAULT 0 2239 #define main0_firmwareModeSelect_SFP_OPT_LR 1 2240 #define main0_firmwareModeSelect_SFP_DAC 2 2241 #define main0_firmwareModeSelect_XLAUI 3 2242 #define main0_firmwareModeSelect_LONG_CH_6G 4 2243 2244 /**************************************************************************** 2245 * Enums: main0_tempIdxSelect 2246 */ 2247 #define main0_tempIdxSelect_LTE__22p9C 15 2248 #define main0_tempIdxSelect_LTE__12p6C 14 2249 #define main0_tempIdxSelect_LTE__3p0C 13 2250 #define main0_tempIdxSelect_LTE_6p7C 12 2251 #define main0_tempIdxSelect_LTE_16p4C 11 2252 #define main0_tempIdxSelect_LTE_26p6C 10 2253 #define main0_tempIdxSelect_LTE_36p3C 9 2254 #define main0_tempIdxSelect_LTE_46p0C 8 2255 #define main0_tempIdxSelect_LTE_56p2C 7 2256 #define main0_tempIdxSelect_LTE_65p9C 6 2257 #define main0_tempIdxSelect_LTE_75p6C 5 2258 #define main0_tempIdxSelect_LTE_85p3C 4 2259 #define main0_tempIdxSelect_LTE_95p5C 3 2260 #define main0_tempIdxSelect_LTE_105p2C 2 2261 #define main0_tempIdxSelect_LTE_114p9C 1 2262 #define main0_tempIdxSelect_LTE_125p1C 0 2263 2264 /**************************************************************************** 2265 * Enums: main0_port_mode 2266 */ 2267 #define main0_port_mode_QUAD_PORT 0 2268 #define main0_port_mode_TRI_1_PORT 1 2269 #define main0_port_mode_TRI_2_PORT 2 2270 #define main0_port_mode_DUAL_PORT 3 2271 #define main0_port_mode_SINGLE_PORT 4 2272 #define main0_port_mode_SINGLE_OCTAL_PORT 5 2273 2274 /**************************************************************************** 2275 * Enums: main0_rev_letter_enum 2276 */ 2277 #define main0_rev_letter_enum_REV_A 0 2278 #define main0_rev_letter_enum_REV_B 1 2279 #define main0_rev_letter_enum_REV_C 2 2280 #define main0_rev_letter_enum_REV_D 3 2281 2282 /**************************************************************************** 2283 * Enums: main0_rev_number_enum 2284 */ 2285 #define main0_rev_number_enum_REV_0 0 2286 #define main0_rev_number_enum_REV_1 1 2287 #define main0_rev_number_enum_REV_2 2 2288 #define main0_rev_number_enum_REV_3 3 2289 #define main0_rev_number_enum_REV_4 4 2290 #define main0_rev_number_enum_REV_5 5 2291 #define main0_rev_number_enum_REV_6 6 2292 #define main0_rev_number_enum_REV_7 7 2293 2294 /**************************************************************************** 2295 * Enums: main0_bonding_enum 2296 */ 2297 #define main0_bonding_enum_WIRE_BOND 0 2298 #define main0_bonding_enum_FLIP_CHIP 1 2299 2300 /**************************************************************************** 2301 * Enums: main0_tech_process 2302 */ 2303 #define main0_tech_process_PROCESS_90NM 0 2304 #define main0_tech_process_PROCESS_65NM 1 2305 #define main0_tech_process_PROCESS_40NM 2 2306 #define main0_tech_process_PROCESS_28NM 3 2307 #define main0_tech_process_PROCESS_16NM 4 2308 2309 /**************************************************************************** 2310 * Enums: main0_model_num 2311 */ 2312 #define main0_model_num_SERDES_CL73 0 2313 #define main0_model_num_XGXS_16G 1 2314 #define main0_model_num_HYPERCORE 2 2315 #define main0_model_num_HYPERLITE 3 2316 #define main0_model_num_PCIE_G2_PIPE 4 2317 #define main0_model_num_SERDES_1p25GBd 5 2318 #define main0_model_num_SATA2 6 2319 #define main0_model_num_QSGMII 7 2320 #define main0_model_num_XGXS10G 8 2321 #define main0_model_num_WARPCORE 9 2322 #define main0_model_num_XFICORE 10 2323 #define main0_model_num_RXFI 11 2324 #define main0_model_num_WARPLITE 12 2325 #define main0_model_num_PENTACORE 13 2326 #define main0_model_num_ESM 14 2327 #define main0_model_num_QUAD_SGMII 15 2328 #define main0_model_num_WARPCORE_3 16 2329 #define main0_model_num_TSC 17 2330 #define main0_model_num_TSC4E 18 2331 #define main0_model_num_TSC12E 19 2332 #define main0_model_num_TSC4F 20 2333 #define main0_model_num_TSC4F_GEN2 21 2334 #define main0_model_num_XGXS_CL73_90NM 29 2335 #define main0_model_num_SERDES_CL73_90NM 30 2336 #define main0_model_num_WARPCORE3 32 2337 #define main0_model_num_WARPCORE4_TSC 33 2338 #define main0_model_num_RXAUI 34 2339 #define main0_model_num_TSCE_GEN3 35 2340 #define main0_model_num_TSC4F_GEN3 36 2341 #define main0_model_num_TSCBH 37 2342 2343 /**************************************************************************** 2344 * Enums: main0_payload 2345 */ 2346 #define main0_payload_REPEAT_2_BYTES 0 2347 #define main0_payload_RAMPING 1 2348 #define main0_payload_CL48_CRPAT 2 2349 #define main0_payload_CL48_CJPAT 3 2350 #define main0_payload_CL36_LONG_CRPAT 4 2351 #define main0_payload_CL36_SHORT_CRPAT 5 2352 2353 /**************************************************************************** 2354 * Enums: main0_sc 2355 */ 2356 #define main0_sc_SPEED_10G_IEEE_KR1 0 2357 #define main0_sc_SPEED_25G_IEEE_KS1_CS1 1 2358 #define main0_sc_SPEED_25G_IEEE_KR1_CR1 2 2359 #define main0_sc_SPEED_40G_IEEE_KR4 3 2360 #define main0_sc_SPEED_40G_IEEE_CR4 4 2361 #define main0_sc_SPEED_50G_IEEE_KR1_CR1 5 2362 #define main0_sc_SPEED_100G_IEEE_KR4 6 2363 #define main0_sc_SPEED_100G_IEEE_CR4 7 2364 #define main0_sc_SPEED_100G_IEEE_KR2_CR2 8 2365 #define main0_sc_SPEED_200G_IEEE_KR4_CR4 9 2366 #define main0_sc_SPEED_400G_IEEE_X8 10 2367 #define main0_sc_SPEED_CL73_IEEE_20GVCO 11 2368 #define main0_sc_SPEED_CL73_IEEE_25GVCO 12 2369 #define main0_sc_SPEED_CL73_IEEE_26GVCO 13 2370 #define main0_sc_SPEED_20G_BRCM_CR1 14 2371 #define main0_sc_SPEED_20G_BRCM_KR1 15 2372 #define main0_sc_SPEED_25G_BRCM_CR1 16 2373 #define main0_sc_SPEED_25G_BRCM_KR1 17 2374 #define main0_sc_SPEED_40G_BRCM_CR2 18 2375 #define main0_sc_SPEED_40G_BRCM_KR2 19 2376 #define main0_sc_SPEED_50G_BRCM_CR2 20 2377 #define main0_sc_SPEED_50G_BRCM_KR2 21 2378 #define main0_sc_SPEED_50G_BRCM_CR4 22 2379 #define main0_sc_SPEED_50G_BRCM_KR4 23 2380 #define main0_sc_SPEED_50G_BRCM_FEC_544_CR2_KR2 24 2381 #define main0_sc_SPEED_RESERVED_19 25 2382 #define main0_sc_SPEED_50G_BRCM_FEC_544_CR1_KR1 26 2383 #define main0_sc_SPEED_50G_BRCM_NO_FEC_CR1_KR1 27 2384 #define main0_sc_SPEED_50G_BRCM_FEC_528_CR1_KR1 28 2385 #define main0_sc_SPEED_400G_BRCM_NO_FEC_KR8_CR8 29 2386 #define main0_sc_SPEED_400G_BRCM_FEC_KR8_CR8 30 2387 #define main0_sc_SPEED_200G_BRCM_NO_FEC_KR4_CR4 31 2388 #define main0_sc_SPEED_200G_BRCM_KR4_CR4 32 2389 #define main0_sc_SPEED_100G_BRCM_KR4_CR4 33 2390 #define main0_sc_SPEED_RESERVED_22 34 2391 #define main0_sc_SPEED_100G_BRCM_FEC_528_KR2_CR2 35 2392 #define main0_sc_SPEED_100G_BRCM_NO_FEC_KR2_CR2 36 2393 #define main0_sc_SPEED_100G_BRCM_NO_FEC_X4 37 2394 2395 /**************************************************************************** 2396 * Enums: main0_t_fifo_modes 2397 */ 2398 #define main0_t_fifo_modes_T_FIFO_INSERT_NO_AM 0 2399 #define main0_t_fifo_modes_T_FIFO_INSERT_4_AM 1 2400 #define main0_t_fifo_modes_T_FIFO_INSERT_20_AM 2 2401 #define main0_t_fifo_modes_T_FIFO_INSERT_2_AM 3 2402 2403 /**************************************************************************** 2404 * Enums: main0_t_enc_modes 2405 */ 2406 #define main0_t_enc_modes_T_ENC_MODE_BYPASS 0 2407 #define main0_t_enc_modes_T_ENC_MODE_CL49 1 2408 #define main0_t_enc_modes_T_ENC_MODE_CL82 2 2409 2410 /**************************************************************************** 2411 * Enums: main0_btmx_mode 2412 */ 2413 #define main0_btmx_mode_BS_BTMX_MODE_1to1 0 2414 #define main0_btmx_mode_BS_BTMX_MODE_2to1 1 2415 #define main0_btmx_mode_BS_BTMX_MODE_5to1 2 2416 2417 /**************************************************************************** 2418 * Enums: main0_t_type_cl82 2419 */ 2420 #define main0_t_type_cl82_T_TYPE_B1 5 2421 #define main0_t_type_cl82_T_TYPE_C 4 2422 #define main0_t_type_cl82_T_TYPE_S 3 2423 #define main0_t_type_cl82_T_TYPE_T 2 2424 #define main0_t_type_cl82_T_TYPE_D 1 2425 #define main0_t_type_cl82_T_TYPE_E 0 2426 2427 /**************************************************************************** 2428 * Enums: main0_txsm_state_cl82 2429 */ 2430 #define main0_txsm_state_cl82_TX_E 4 2431 #define main0_txsm_state_cl82_TX_T 3 2432 #define main0_txsm_state_cl82_TX_D 2 2433 #define main0_txsm_state_cl82_TX_C 1 2434 #define main0_txsm_state_cl82_TX_INIT 0 2435 2436 /**************************************************************************** 2437 * Enums: main0_ltxsm_state_cl82 2438 */ 2439 #define main0_ltxsm_state_cl82_TX_E 16 2440 #define main0_ltxsm_state_cl82_TX_T 8 2441 #define main0_ltxsm_state_cl82_TX_D 4 2442 #define main0_ltxsm_state_cl82_TX_C 2 2443 #define main0_ltxsm_state_cl82_TX_INIT 1 2444 2445 /**************************************************************************** 2446 * Enums: main0_r_type_coded_cl82 2447 */ 2448 #define main0_r_type_coded_cl82_R_TYPE_B1 32 2449 #define main0_r_type_coded_cl82_R_TYPE_C 16 2450 #define main0_r_type_coded_cl82_R_TYPE_S 8 2451 #define main0_r_type_coded_cl82_R_TYPE_T 4 2452 #define main0_r_type_coded_cl82_R_TYPE_D 2 2453 #define main0_r_type_coded_cl82_R_TYPE_E 1 2454 2455 /**************************************************************************** 2456 * Enums: main0_rxsm_state_cl82 2457 */ 2458 #define main0_rxsm_state_cl82_RX_E 16 2459 #define main0_rxsm_state_cl82_RX_T 8 2460 #define main0_rxsm_state_cl82_RX_D 4 2461 #define main0_rxsm_state_cl82_RX_C 2 2462 #define main0_rxsm_state_cl82_RX_INIT 1 2463 2464 /**************************************************************************** 2465 * Enums: main0_deskew_state 2466 */ 2467 #define main0_deskew_state_ALIGN_ACQUIRED 2 2468 #define main0_deskew_state_LOSS_OF_ALIGNMENT 1 2469 2470 /**************************************************************************** 2471 * Enums: main0_os_mode_enum 2472 */ 2473 #define main0_os_mode_enum_OS_MODE_1 0 2474 #define main0_os_mode_enum_OS_MODE_2 1 2475 #define main0_os_mode_enum_OS_MODE_4 2 2476 #define main0_os_mode_enum_OS_MODE_16p5 8 2477 #define main0_os_mode_enum_OS_MODE_20p625 12 2478 2479 /**************************************************************************** 2480 * Enums: main0_scr_modes 2481 */ 2482 #define main0_scr_modes_T_SCR_MODE_BYPASS 0 2483 #define main0_scr_modes_T_SCR_MODE_CL49 1 2484 #define main0_scr_modes_T_SCR_MODE_40G_2_LANE 2 2485 #define main0_scr_modes_T_SCR_MODE_100G 3 2486 #define main0_scr_modes_T_SCR_MODE_20G 4 2487 #define main0_scr_modes_T_SCR_MODE_40G_4_LANE 5 2488 2489 /**************************************************************************** 2490 * Enums: main0_descr_modes 2491 */ 2492 #define main0_descr_modes_R_DESCR_MODE_BYPASS 0 2493 #define main0_descr_modes_R_DESCR_MODE_CL49 1 2494 #define main0_descr_modes_R_DESCR_MODE_CL82 2 2495 2496 /**************************************************************************** 2497 * Enums: main0_r_dec_tl_mode 2498 */ 2499 #define main0_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 2500 #define main0_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 2501 #define main0_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 2502 2503 /**************************************************************************** 2504 * Enums: main0_r_dec_fsm_mode 2505 */ 2506 #define main0_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 2507 #define main0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 2508 #define main0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 2509 2510 /**************************************************************************** 2511 * Enums: main0_r_deskew_mode 2512 */ 2513 #define main0_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 2514 #define main0_r_deskew_mode_R_DESKEW_MODE_20G 1 2515 #define main0_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 2516 #define main0_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 2517 #define main0_r_deskew_mode_R_DESKEW_MODE_100G 4 2518 #define main0_r_deskew_mode_R_DESKEW_MODE_CL49 5 2519 #define main0_r_deskew_mode_R_DESKEW_MODE_CL91_QUAD 6 2520 #define main0_r_deskew_mode_R_DESKEW_MODE_CL91_SINGLE_BRCM 7 2521 #define main0_r_deskew_mode_R_DESKEW_MODE_CL91_DUAL_BRCM 8 2522 #define main0_r_deskew_mode_R_DESKEW_MODE_CL91_FC 9 2523 2524 /**************************************************************************** 2525 * Enums: main0_bs_dist_modes 2526 */ 2527 #define main0_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 2528 #define main0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 2529 #define main0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 2530 #define main0_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 2531 2532 /**************************************************************************** 2533 * Enums: main0_cl49_t_type 2534 */ 2535 #define main0_cl49_t_type_BAD_T_TYPE 15 2536 #define main0_cl49_t_type_T_TYPE_B0 11 2537 #define main0_cl49_t_type_T_TYPE_OB 10 2538 #define main0_cl49_t_type_T_TYPE_B1 9 2539 #define main0_cl49_t_type_T_TYPE_DB 8 2540 #define main0_cl49_t_type_T_TYPE_FC 7 2541 #define main0_cl49_t_type_T_TYPE_TB 6 2542 #define main0_cl49_t_type_T_TYPE_LI 5 2543 #define main0_cl49_t_type_T_TYPE_C 4 2544 #define main0_cl49_t_type_T_TYPE_S 3 2545 #define main0_cl49_t_type_T_TYPE_T 2 2546 #define main0_cl49_t_type_T_TYPE_D 1 2547 #define main0_cl49_t_type_T_TYPE_E 0 2548 2549 /**************************************************************************** 2550 * Enums: main0_cl49_txsm_states 2551 */ 2552 #define main0_cl49_txsm_states_TX_LI 5 2553 #define main0_cl49_txsm_states_TX_E 4 2554 #define main0_cl49_txsm_states_TX_T 3 2555 #define main0_cl49_txsm_states_TX_D 2 2556 #define main0_cl49_txsm_states_TX_C 1 2557 #define main0_cl49_txsm_states_TX_INIT 0 2558 2559 /**************************************************************************** 2560 * Enums: main0_cl49_ltxsm_states 2561 */ 2562 #define main0_cl49_ltxsm_states_TX_LI 32 2563 #define main0_cl49_ltxsm_states_TX_E 16 2564 #define main0_cl49_ltxsm_states_TX_T 8 2565 #define main0_cl49_ltxsm_states_TX_D 4 2566 #define main0_cl49_ltxsm_states_TX_C 2 2567 #define main0_cl49_ltxsm_states_TX_INIT 1 2568 2569 /**************************************************************************** 2570 * Enums: main0_burst_error_mode 2571 */ 2572 #define main0_burst_error_mode_BURST_ERROR_11_BITS 0 2573 #define main0_burst_error_mode_BURST_ERROR_16_BITS 1 2574 #define main0_burst_error_mode_BURST_ERROR_17_BITS 2 2575 #define main0_burst_error_mode_BURST_ERROR_18_BITS 3 2576 #define main0_burst_error_mode_BURST_ERROR_19_BITS 4 2577 #define main0_burst_error_mode_BURST_ERROR_20_BITS 5 2578 #define main0_burst_error_mode_BURST_ERROR_21_BITS 6 2579 #define main0_burst_error_mode_BURST_ERROR_22_BITS 7 2580 #define main0_burst_error_mode_BURST_ERROR_23_BITS 8 2581 #define main0_burst_error_mode_BURST_ERROR_24_BITS 9 2582 #define main0_burst_error_mode_BURST_ERROR_25_BITS 10 2583 #define main0_burst_error_mode_BURST_ERROR_26_BITS 11 2584 #define main0_burst_error_mode_BURST_ERROR_27_BITS 12 2585 #define main0_burst_error_mode_BURST_ERROR_28_BITS 13 2586 #define main0_burst_error_mode_BURST_ERROR_29_BITS 14 2587 #define main0_burst_error_mode_BURST_ERROR_30_BITS 15 2588 #define main0_burst_error_mode_BURST_ERROR_31_BITS 16 2589 #define main0_burst_error_mode_BURST_ERROR_32_BITS 17 2590 #define main0_burst_error_mode_BURST_ERROR_33_BITS 18 2591 #define main0_burst_error_mode_BURST_ERROR_34_BITS 19 2592 #define main0_burst_error_mode_BURST_ERROR_35_BITS 20 2593 #define main0_burst_error_mode_BURST_ERROR_36_BITS 21 2594 #define main0_burst_error_mode_BURST_ERROR_37_BITS 22 2595 #define main0_burst_error_mode_BURST_ERROR_38_BITS 23 2596 #define main0_burst_error_mode_BURST_ERROR_39_BITS 24 2597 #define main0_burst_error_mode_BURST_ERROR_40_BITS 25 2598 #define main0_burst_error_mode_BURST_ERROR_41_BITS 26 2599 2600 /**************************************************************************** 2601 * Enums: main0_bermon_state 2602 */ 2603 #define main0_bermon_state_HI_BER 4 2604 #define main0_bermon_state_GOOD_BER 3 2605 #define main0_bermon_state_BER_TEST_SH 2 2606 #define main0_bermon_state_START_TIMER 1 2607 #define main0_bermon_state_BER_MT_INIT 0 2608 2609 /**************************************************************************** 2610 * Enums: main0_rxsm_state_cl49 2611 */ 2612 #define main0_rxsm_state_cl49_RX_LI 32 2613 #define main0_rxsm_state_cl49_RX_E 16 2614 #define main0_rxsm_state_cl49_RX_T 8 2615 #define main0_rxsm_state_cl49_RX_D 4 2616 #define main0_rxsm_state_cl49_RX_C 2 2617 #define main0_rxsm_state_cl49_RX_INIT 1 2618 2619 /**************************************************************************** 2620 * Enums: main0_r_type 2621 */ 2622 #define main0_r_type_BAD_R_TYPE 15 2623 #define main0_r_type_R_TYPE_B0 11 2624 #define main0_r_type_R_TYPE_OB 10 2625 #define main0_r_type_R_TYPE_B1 9 2626 #define main0_r_type_R_TYPE_DB 8 2627 #define main0_r_type_R_TYPE_FC 7 2628 #define main0_r_type_R_TYPE_TB 6 2629 #define main0_r_type_R_TYPE_LI 5 2630 #define main0_r_type_R_TYPE_C 4 2631 #define main0_r_type_R_TYPE_S 3 2632 #define main0_r_type_R_TYPE_T 2 2633 #define main0_r_type_R_TYPE_D 1 2634 #define main0_r_type_R_TYPE_E 0 2635 2636 /**************************************************************************** 2637 * Enums: main0_am_lock_state 2638 */ 2639 #define main0_am_lock_state_INVALID_AM 512 2640 #define main0_am_lock_state_GOOD_AM 256 2641 #define main0_am_lock_state_COMP_AM 128 2642 #define main0_am_lock_state_TIMER_2 64 2643 #define main0_am_lock_state_AM_2_GOOD 32 2644 #define main0_am_lock_state_COMP_2ND 16 2645 #define main0_am_lock_state_TIMER_1 8 2646 #define main0_am_lock_state_FIND_1ST 4 2647 #define main0_am_lock_state_AM_RESET_CNT 2 2648 #define main0_am_lock_state_AM_LOCK_INIT 1 2649 2650 /**************************************************************************** 2651 * Enums: main0_msg_selector 2652 */ 2653 #define main0_msg_selector_RESERVED 0 2654 #define main0_msg_selector_VALUE_802p3 1 2655 #define main0_msg_selector_VALUE_802p9 2 2656 #define main0_msg_selector_VALUE_802p5 3 2657 #define main0_msg_selector_VALUE_1394 4 2658 2659 /**************************************************************************** 2660 * Enums: main0_synce_enum_stage1 2661 */ 2662 #define main0_synce_enum_stage1_SYNCE_NO_DIV 0 2663 #define main0_synce_enum_stage1_SYNCE_DIV_7 1 2664 #define main0_synce_enum_stage1_SYNCE_DIV_11 2 2665 2666 /**************************************************************************** 2667 * Enums: main0_synce_enum_stage0 2668 */ 2669 #define main0_synce_enum_stage0_SYNCE_NO_DIV 0 2670 #define main0_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 2671 #define main0_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 2672 2673 /**************************************************************************** 2674 * Enums: main0_cl91_sync_state 2675 */ 2676 #define main0_cl91_sync_state_FIND_1ST 0 2677 #define main0_cl91_sync_state_COUNT_NEXT 1 2678 #define main0_cl91_sync_state_COMP_2ND 2 2679 #define main0_cl91_sync_state_TWO_GOOD 3 2680 2681 /**************************************************************************** 2682 * Enums: main0_RS_FEC_sync_state 2683 */ 2684 #define main0_RS_FEC_sync_state_LOCK_INIT 0 2685 #define main0_RS_FEC_sync_state_FIND_1ST 1 2686 #define main0_RS_FEC_sync_state_COUNT_NEXT 2 2687 #define main0_RS_FEC_sync_state_COMP_2ND 3 2688 #define main0_RS_FEC_sync_state_TWO_GOOD 4 2689 2690 /**************************************************************************** 2691 * Enums: main0_cl91_algn_state 2692 */ 2693 #define main0_cl91_algn_state_LOSS_OF_ALIGNMENT 0 2694 #define main0_cl91_algn_state_DESKEW 1 2695 #define main0_cl91_algn_state_DESKEW_FAIL 2 2696 #define main0_cl91_algn_state_ALIGN_ACQUIRED 3 2697 #define main0_cl91_algn_state_CW_GOOD 4 2698 #define main0_cl91_algn_state_CW_BAD 5 2699 #define main0_cl91_algn_state_THREE_BAD 6 2700 2701 /**************************************************************************** 2702 * Enums: main0_RS_FEC_algn_state 2703 */ 2704 #define main0_RS_FEC_algn_state_LOSS_OF_ALIGNMENT 0 2705 #define main0_RS_FEC_algn_state_DESKEW 1 2706 #define main0_RS_FEC_algn_state_DESKEW_FAIL 2 2707 #define main0_RS_FEC_algn_state_ALIGN_ACQUIRED 3 2708 #define main0_RS_FEC_algn_state_CW_GOOD 4 2709 #define main0_RS_FEC_algn_state_CW_BAD 5 2710 #define main0_RS_FEC_algn_state_THREE_BAD 6 2711 2712 /**************************************************************************** 2713 * Enums: main0_fec_sel_override 2714 */ 2715 #define main0_fec_sel_override_NO_OVERRIDE 0 2716 #define main0_fec_sel_override_NO_FEC 1 2717 #define main0_fec_sel_override_FEC_CL74 2 2718 #define main0_fec_sel_override_FEC_CL91 3 2719 2720 /**************************************************************************** 2721 * Enums: main0_cl91_blksync_mode 2722 */ 2723 #define main0_cl91_blksync_mode_R_BLKSYNC_NO_CL91_FEC 0 2724 #define main0_cl91_blksync_mode_R_BLKSYNC_CL91_QUAD_LANE_FEC 1 2725 #define main0_cl91_blksync_mode_R_BLKSYNC_CL91_DUAL_LANE_FEC 2 2726 #define main0_cl91_blksync_mode_R_BLKSYNC_CL91_SINGLE_LANE_FEC 3 2727 #define main0_cl91_blksync_mode_R_BLKSYNC_CL91_FC_FEC 4 2728 2729 /**************************************************************************** 2730 * Enums: main0_r_merge_mode 2731 */ 2732 #define main0_r_merge_mode_R_MERGE_MODE_BYPASS 0 2733 #define main0_r_merge_mode_R_MERGE_MODE_CL91_FC 1 2734 #define main0_r_merge_mode_R_MERGE_MODE_CL91_SINGLE_LANE 2 2735 #define main0_r_merge_mode_R_MERGE_MODE_CL91_DUAL_LANE 3 2736 #define main0_r_merge_mode_R_MERGE_MODE_CL91_QUAD_LANE 4 2737 2738 /**************************************************************************** 2739 * Enums: main0_r_tc_mode 2740 */ 2741 #define main0_r_tc_mode_R_TC_MODE_SINGLE 0 2742 #define main0_r_tc_mode_R_TC_MODE_DUAL 1 2743 #define main0_r_tc_mode_R_TC_MODE_QUAD 2 2744 2745 /**************************************************************************** 2746 * Enums: main0_r_tc_out_mode 2747 */ 2748 #define main0_r_tc_out_mode_R_TC_OUT_MODE_SINGLE 0 2749 #define main0_r_tc_out_mode_R_TC_OUT_MODE_DUAL 1 2750 #define main0_r_tc_out_mode_R_TC_OUT_MODE_QUAD 2 2751 2752 /**************************************************************************** 2753 * Enums: main0_cl91_fec_mode 2754 */ 2755 #define main0_cl91_fec_mode_NO_CL91_FEC 0 2756 #define main0_cl91_fec_mode_CL91_SINGLE_LANE_FC 1 2757 #define main0_cl91_fec_mode_CL91_SINGLE_LANE_BRCM_PROP 2 2758 #define main0_cl91_fec_mode_CL91_DUAL_LANE_BRCM_PROP 3 2759 #define main0_cl91_fec_mode_CL91_QUAD_LANE 4 2760 #define main0_cl91_fec_mode_IEEE_25G_CL91_SINGLE_LANE 5 2761 2762 /**************************************************************************** 2763 * Enums: main0_RS_FEC_fec_mode 2764 */ 2765 #define main0_RS_FEC_fec_mode_NO_RS_FEC_FEC 0 2766 #define main0_RS_FEC_fec_mode_N_A 1 2767 #define main0_RS_FEC_fec_mode_RS_FEC_SINGLE_LANE_BRCM_PROP 2 2768 #define main0_RS_FEC_fec_mode_RS_FEC_DUAL_LANE_BRCM_PROP 3 2769 #define main0_RS_FEC_fec_mode_RS_FEC_QUAD_LANE 4 2770 #define main0_RS_FEC_fec_mode_IEEE_25G_RS_FEC_SINGLE_LANE 5 2771 2772 /**************************************************************************** 2773 * Enums: main0_am_spacing_mul 2774 */ 2775 #define main0_am_spacing_mul_AM_SPACING_MUL_2 0 2776 #define main0_am_spacing_mul_AM_SPACING_MUL_4 1 2777 #define main0_am_spacing_mul_AM_SPACING_MUL_5 2 2778 #define main0_am_spacing_mul_AM_SPACING_MUL_20 3 2779 2780 /**************************************************************************** 2781 * Enums: rx_x1_status0_cl36TxEEEStates_l 2782 */ 2783 #define rx_x1_status0_cl36TxEEEStates_l_TX_REFRESH 8 2784 #define rx_x1_status0_cl36TxEEEStates_l_TX_QUIET 4 2785 #define rx_x1_status0_cl36TxEEEStates_l_TX_SLEEP 2 2786 #define rx_x1_status0_cl36TxEEEStates_l_TX_ACTIVE 1 2787 2788 /**************************************************************************** 2789 * Enums: rx_x1_status0_cl36TxEEEStates_c 2790 */ 2791 #define rx_x1_status0_cl36TxEEEStates_c_TX_REFRESH 3 2792 #define rx_x1_status0_cl36TxEEEStates_c_TX_QUIET 2 2793 #define rx_x1_status0_cl36TxEEEStates_c_TX_SLEEP 1 2794 #define rx_x1_status0_cl36TxEEEStates_c_TX_ACTIVE 0 2795 2796 /**************************************************************************** 2797 * Enums: rx_x1_status0_cl49TxEEEStates_l 2798 */ 2799 #define rx_x1_status0_cl49TxEEEStates_l_SCR_RESET_2 64 2800 #define rx_x1_status0_cl49TxEEEStates_l_SCR_RESET_1 32 2801 #define rx_x1_status0_cl49TxEEEStates_l_TX_WAKE 16 2802 #define rx_x1_status0_cl49TxEEEStates_l_TX_REFRESH 8 2803 #define rx_x1_status0_cl49TxEEEStates_l_TX_QUIET 4 2804 #define rx_x1_status0_cl49TxEEEStates_l_TX_SLEEP 2 2805 #define rx_x1_status0_cl49TxEEEStates_l_TX_ACTIVE 1 2806 2807 /**************************************************************************** 2808 * Enums: rx_x1_status0_fec_req_enum 2809 */ 2810 #define rx_x1_status0_fec_req_enum_FEC_not_supported 0 2811 #define rx_x1_status0_fec_req_enum_FEC_supported_but_not_requested 1 2812 #define rx_x1_status0_fec_req_enum_invalid_setting 2 2813 #define rx_x1_status0_fec_req_enum_FEC_supported_and_requested 3 2814 2815 /**************************************************************************** 2816 * Enums: rx_x1_status0_cl73_pause_enum 2817 */ 2818 #define rx_x1_status0_cl73_pause_enum_No_PAUSE_ability 0 2819 #define rx_x1_status0_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 2820 #define rx_x1_status0_cl73_pause_enum_Symmetric_PAUSE_ability 1 2821 #define rx_x1_status0_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 2822 2823 /**************************************************************************** 2824 * Enums: rx_x1_status0_cl49TxEEEStates_c 2825 */ 2826 #define rx_x1_status0_cl49TxEEEStates_c_SCR_RESET_2 6 2827 #define rx_x1_status0_cl49TxEEEStates_c_SCR_RESET_1 5 2828 #define rx_x1_status0_cl49TxEEEStates_c_TX_WAKE 4 2829 #define rx_x1_status0_cl49TxEEEStates_c_TX_REFRESH 3 2830 #define rx_x1_status0_cl49TxEEEStates_c_TX_QUIET 2 2831 #define rx_x1_status0_cl49TxEEEStates_c_TX_SLEEP 1 2832 #define rx_x1_status0_cl49TxEEEStates_c_TX_ACTIVE 0 2833 2834 /**************************************************************************** 2835 * Enums: rx_x1_status0_cl36RxEEEStates_l 2836 */ 2837 #define rx_x1_status0_cl36RxEEEStates_l_RX_LINK_FAIL 32 2838 #define rx_x1_status0_cl36RxEEEStates_l_RX_WTF 16 2839 #define rx_x1_status0_cl36RxEEEStates_l_RX_WAKE 8 2840 #define rx_x1_status0_cl36RxEEEStates_l_RX_QUIET 4 2841 #define rx_x1_status0_cl36RxEEEStates_l_RX_SLEEP 2 2842 #define rx_x1_status0_cl36RxEEEStates_l_RX_ACTIVE 1 2843 2844 /**************************************************************************** 2845 * Enums: rx_x1_status0_cl36RxEEEStates_c 2846 */ 2847 #define rx_x1_status0_cl36RxEEEStates_c_RX_LINK_FAIL 5 2848 #define rx_x1_status0_cl36RxEEEStates_c_RX_WTF 4 2849 #define rx_x1_status0_cl36RxEEEStates_c_RX_WAKE 3 2850 #define rx_x1_status0_cl36RxEEEStates_c_RX_QUIET 2 2851 #define rx_x1_status0_cl36RxEEEStates_c_RX_SLEEP 1 2852 #define rx_x1_status0_cl36RxEEEStates_c_RX_ACTIVE 0 2853 2854 /**************************************************************************** 2855 * Enums: rx_x1_status0_cl49RxEEEStates_l 2856 */ 2857 #define rx_x1_status0_cl49RxEEEStates_l_RX_LINK_FAIL 32 2858 #define rx_x1_status0_cl49RxEEEStates_l_RX_WTF 16 2859 #define rx_x1_status0_cl49RxEEEStates_l_RX_WAKE 8 2860 #define rx_x1_status0_cl49RxEEEStates_l_RX_QUIET 4 2861 #define rx_x1_status0_cl49RxEEEStates_l_RX_SLEEP 2 2862 #define rx_x1_status0_cl49RxEEEStates_l_RX_ACTIVE 1 2863 2864 /**************************************************************************** 2865 * Enums: rx_x1_status0_cl49RxEEEStates_c 2866 */ 2867 #define rx_x1_status0_cl49RxEEEStates_c_RX_LINK_FAIL 5 2868 #define rx_x1_status0_cl49RxEEEStates_c_RX_WTF 4 2869 #define rx_x1_status0_cl49RxEEEStates_c_RX_WAKE 3 2870 #define rx_x1_status0_cl49RxEEEStates_c_RX_QUIET 2 2871 #define rx_x1_status0_cl49RxEEEStates_c_RX_SLEEP 1 2872 #define rx_x1_status0_cl49RxEEEStates_c_RX_ACTIVE 0 2873 2874 /**************************************************************************** 2875 * Enums: rx_x1_status0_cl48TxEEEStates_l 2876 */ 2877 #define rx_x1_status0_cl48TxEEEStates_l_TX_REFRESH 8 2878 #define rx_x1_status0_cl48TxEEEStates_l_TX_QUIET 4 2879 #define rx_x1_status0_cl48TxEEEStates_l_TX_SLEEP 2 2880 #define rx_x1_status0_cl48TxEEEStates_l_TX_ACTIVE 1 2881 2882 /**************************************************************************** 2883 * Enums: rx_x1_status0_cl48TxEEEStates_c 2884 */ 2885 #define rx_x1_status0_cl48TxEEEStates_c_TX_REFRESH 3 2886 #define rx_x1_status0_cl48TxEEEStates_c_TX_QUIET 2 2887 #define rx_x1_status0_cl48TxEEEStates_c_TX_SLEEP 1 2888 #define rx_x1_status0_cl48TxEEEStates_c_TX_ACTIVE 0 2889 2890 /**************************************************************************** 2891 * Enums: rx_x1_status0_cl48RxEEEStates_l 2892 */ 2893 #define rx_x1_status0_cl48RxEEEStates_l_RX_LINK_FAIL 32 2894 #define rx_x1_status0_cl48RxEEEStates_l_RX_WAKE 16 2895 #define rx_x1_status0_cl48RxEEEStates_l_RX_QUIET 8 2896 #define rx_x1_status0_cl48RxEEEStates_l_RX_DEACT 4 2897 #define rx_x1_status0_cl48RxEEEStates_l_RX_SLEEP 2 2898 #define rx_x1_status0_cl48RxEEEStates_l_RX_ACTIVE 1 2899 2900 /**************************************************************************** 2901 * Enums: rx_x1_status0_cl48RxEEEStates_c 2902 */ 2903 #define rx_x1_status0_cl48RxEEEStates_c_RX_LINK_FAIL 5 2904 #define rx_x1_status0_cl48RxEEEStates_c_RX_WAKE 4 2905 #define rx_x1_status0_cl48RxEEEStates_c_RX_QUIET 3 2906 #define rx_x1_status0_cl48RxEEEStates_c_RX_DEACT 2 2907 #define rx_x1_status0_cl48RxEEEStates_c_RX_SLEEP 1 2908 #define rx_x1_status0_cl48RxEEEStates_c_RX_ACTIVE 0 2909 2910 /**************************************************************************** 2911 * Enums: rx_x1_status0_IQP_Options 2912 */ 2913 #define rx_x1_status0_IQP_Options_i50uA 0 2914 #define rx_x1_status0_IQP_Options_i100uA 1 2915 #define rx_x1_status0_IQP_Options_i150uA 2 2916 #define rx_x1_status0_IQP_Options_i200uA 3 2917 #define rx_x1_status0_IQP_Options_i250uA 4 2918 #define rx_x1_status0_IQP_Options_i300uA 5 2919 #define rx_x1_status0_IQP_Options_i350uA 6 2920 #define rx_x1_status0_IQP_Options_i400uA 7 2921 #define rx_x1_status0_IQP_Options_i450uA 8 2922 #define rx_x1_status0_IQP_Options_i500uA 9 2923 #define rx_x1_status0_IQP_Options_i550uA 10 2924 #define rx_x1_status0_IQP_Options_i600uA 11 2925 #define rx_x1_status0_IQP_Options_i650uA 12 2926 #define rx_x1_status0_IQP_Options_i700uA 13 2927 #define rx_x1_status0_IQP_Options_i750uA 14 2928 #define rx_x1_status0_IQP_Options_i800uA 15 2929 2930 /**************************************************************************** 2931 * Enums: rx_x1_status0_IDriver_Options 2932 */ 2933 #define rx_x1_status0_IDriver_Options_v680mV 0 2934 #define rx_x1_status0_IDriver_Options_v730mV 1 2935 #define rx_x1_status0_IDriver_Options_v780mV 2 2936 #define rx_x1_status0_IDriver_Options_v830mV 3 2937 #define rx_x1_status0_IDriver_Options_v880mV 4 2938 #define rx_x1_status0_IDriver_Options_v930mV 5 2939 #define rx_x1_status0_IDriver_Options_v980mV 6 2940 #define rx_x1_status0_IDriver_Options_v1010mV 7 2941 #define rx_x1_status0_IDriver_Options_v1040mV 8 2942 #define rx_x1_status0_IDriver_Options_v1060mV 9 2943 #define rx_x1_status0_IDriver_Options_v1070mV 10 2944 #define rx_x1_status0_IDriver_Options_v1080mV 11 2945 #define rx_x1_status0_IDriver_Options_v1085mV 12 2946 #define rx_x1_status0_IDriver_Options_v1090mV 13 2947 #define rx_x1_status0_IDriver_Options_v1095mV 14 2948 #define rx_x1_status0_IDriver_Options_v1100mV 15 2949 2950 /**************************************************************************** 2951 * Enums: rx_x1_status0_operationModes 2952 */ 2953 #define rx_x1_status0_operationModes_XGXS 0 2954 #define rx_x1_status0_operationModes_XGXG_nCC 1 2955 #define rx_x1_status0_operationModes_Indlane_OS8 4 2956 #define rx_x1_status0_operationModes_IndLane_OS5 5 2957 #define rx_x1_status0_operationModes_PCI 7 2958 #define rx_x1_status0_operationModes_XGXS_nLQ 8 2959 #define rx_x1_status0_operationModes_XGXS_nLQnCC 9 2960 #define rx_x1_status0_operationModes_PBypass 10 2961 #define rx_x1_status0_operationModes_PBypass_nDSK 11 2962 #define rx_x1_status0_operationModes_ComboCoreMode 12 2963 #define rx_x1_status0_operationModes_Clocks_off 15 2964 2965 /**************************************************************************** 2966 * Enums: rx_x1_status0_actualSpeeds 2967 */ 2968 #define rx_x1_status0_actualSpeeds_dr_10M 0 2969 #define rx_x1_status0_actualSpeeds_dr_100M 1 2970 #define rx_x1_status0_actualSpeeds_dr_1G 2 2971 #define rx_x1_status0_actualSpeeds_dr_2p5G 3 2972 #define rx_x1_status0_actualSpeeds_dr_5G_X4 4 2973 #define rx_x1_status0_actualSpeeds_dr_6G_X4 5 2974 #define rx_x1_status0_actualSpeeds_dr_10G_HiG 6 2975 #define rx_x1_status0_actualSpeeds_dr_10G_CX4 7 2976 #define rx_x1_status0_actualSpeeds_dr_12G_HiG 8 2977 #define rx_x1_status0_actualSpeeds_dr_12p5G_X4 9 2978 #define rx_x1_status0_actualSpeeds_dr_13G_X4 10 2979 #define rx_x1_status0_actualSpeeds_dr_15G_X4 11 2980 #define rx_x1_status0_actualSpeeds_dr_16G_X4 12 2981 #define rx_x1_status0_actualSpeeds_dr_1G_KX 13 2982 #define rx_x1_status0_actualSpeeds_dr_10G_KX4 14 2983 #define rx_x1_status0_actualSpeeds_dr_10G_KR 15 2984 #define rx_x1_status0_actualSpeeds_dr_5G 16 2985 #define rx_x1_status0_actualSpeeds_dr_6p4G 17 2986 #define rx_x1_status0_actualSpeeds_dr_20G_X4 18 2987 #define rx_x1_status0_actualSpeeds_dr_21G_X4 19 2988 #define rx_x1_status0_actualSpeeds_dr_25G_X4 20 2989 #define rx_x1_status0_actualSpeeds_dr_10G_HiG_DXGXS 21 2990 #define rx_x1_status0_actualSpeeds_dr_10G_DXGXS 22 2991 #define rx_x1_status0_actualSpeeds_dr_10p5G_HiG_DXGXS 23 2992 #define rx_x1_status0_actualSpeeds_dr_10p5G_DXGXS 24 2993 #define rx_x1_status0_actualSpeeds_dr_12p773G_HiG_DXGXS 25 2994 #define rx_x1_status0_actualSpeeds_dr_12p773G_DXGXS 26 2995 #define rx_x1_status0_actualSpeeds_dr_10G_XFI 27 2996 #define rx_x1_status0_actualSpeeds_dr_40G 28 2997 #define rx_x1_status0_actualSpeeds_dr_20G_HiG_DXGXS 29 2998 #define rx_x1_status0_actualSpeeds_dr_20G_DXGXS 30 2999 #define rx_x1_status0_actualSpeeds_dr_10G_SFI 31 3000 #define rx_x1_status0_actualSpeeds_dr_31p5G 32 3001 #define rx_x1_status0_actualSpeeds_dr_32p7G 33 3002 #define rx_x1_status0_actualSpeeds_dr_20G_SCR 34 3003 #define rx_x1_status0_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 3004 #define rx_x1_status0_actualSpeeds_dr_10G_DXGXS_SCR 36 3005 #define rx_x1_status0_actualSpeeds_dr_12G_R2 37 3006 #define rx_x1_status0_actualSpeeds_dr_10G_X2 38 3007 #define rx_x1_status0_actualSpeeds_dr_40G_KR4 39 3008 #define rx_x1_status0_actualSpeeds_dr_40G_CR4 40 3009 #define rx_x1_status0_actualSpeeds_dr_100G_CR10 41 3010 #define rx_x1_status0_actualSpeeds_dr_15p75G_DXGXS 44 3011 #define rx_x1_status0_actualSpeeds_dr_20G_KR2 57 3012 #define rx_x1_status0_actualSpeeds_dr_20G_CR2 58 3013 3014 /**************************************************************************** 3015 * Enums: rx_x1_status0_actualSpeedsMisc1 3016 */ 3017 #define rx_x1_status0_actualSpeedsMisc1_dr_2500BRCM_X1 16 3018 #define rx_x1_status0_actualSpeedsMisc1_dr_5000BRCM_X4 17 3019 #define rx_x1_status0_actualSpeedsMisc1_dr_6000BRCM_X4 18 3020 #define rx_x1_status0_actualSpeedsMisc1_dr_10GHiGig_X4 19 3021 #define rx_x1_status0_actualSpeedsMisc1_dr_10GBASE_CX4 20 3022 #define rx_x1_status0_actualSpeedsMisc1_dr_12GHiGig_X4 21 3023 #define rx_x1_status0_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 3024 #define rx_x1_status0_actualSpeedsMisc1_dr_13GHiGig_X4 23 3025 #define rx_x1_status0_actualSpeedsMisc1_dr_15GHiGig_X4 24 3026 #define rx_x1_status0_actualSpeedsMisc1_dr_16GHiGig_X4 25 3027 #define rx_x1_status0_actualSpeedsMisc1_dr_5000BRCM_X1 26 3028 #define rx_x1_status0_actualSpeedsMisc1_dr_6363BRCM_X1 27 3029 #define rx_x1_status0_actualSpeedsMisc1_dr_20GHiGig_X4 28 3030 #define rx_x1_status0_actualSpeedsMisc1_dr_21GHiGig_X4 29 3031 #define rx_x1_status0_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 3032 #define rx_x1_status0_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 3033 3034 /**************************************************************************** 3035 * Enums: rx_x1_status0_IndLaneModes 3036 */ 3037 #define rx_x1_status0_IndLaneModes_SWSDR_div2 0 3038 #define rx_x1_status0_IndLaneModes_SWSDR_div1 1 3039 #define rx_x1_status0_IndLaneModes_DWSDR_div2 2 3040 #define rx_x1_status0_IndLaneModes_DWSDR_div1 3 3041 3042 /**************************************************************************** 3043 * Enums: rx_x1_status0_prbsSelect 3044 */ 3045 #define rx_x1_status0_prbsSelect_prbs7 0 3046 #define rx_x1_status0_prbsSelect_prbs15 1 3047 #define rx_x1_status0_prbsSelect_prbs23 2 3048 #define rx_x1_status0_prbsSelect_prbs31 3 3049 3050 /**************************************************************************** 3051 * Enums: rx_x1_status0_vcoDivider 3052 */ 3053 #define rx_x1_status0_vcoDivider_div32 0 3054 #define rx_x1_status0_vcoDivider_div36 1 3055 #define rx_x1_status0_vcoDivider_div40 2 3056 #define rx_x1_status0_vcoDivider_div42 3 3057 #define rx_x1_status0_vcoDivider_div48 4 3058 #define rx_x1_status0_vcoDivider_div50 5 3059 #define rx_x1_status0_vcoDivider_div52 6 3060 #define rx_x1_status0_vcoDivider_div54 7 3061 #define rx_x1_status0_vcoDivider_div60 8 3062 #define rx_x1_status0_vcoDivider_div64 9 3063 #define rx_x1_status0_vcoDivider_div66 10 3064 #define rx_x1_status0_vcoDivider_div68 11 3065 #define rx_x1_status0_vcoDivider_div70 12 3066 #define rx_x1_status0_vcoDivider_div80 13 3067 #define rx_x1_status0_vcoDivider_div92 14 3068 #define rx_x1_status0_vcoDivider_div100 15 3069 3070 /**************************************************************************** 3071 * Enums: rx_x1_status0_refClkSelect 3072 */ 3073 #define rx_x1_status0_refClkSelect_clk_156p25MHz 1 3074 #define rx_x1_status0_refClkSelect_clk_312p5Mhz 2 3075 3076 /**************************************************************************** 3077 * Enums: rx_x1_status0_aerMMDdevTypeSelect 3078 */ 3079 #define rx_x1_status0_aerMMDdevTypeSelect_combo_core 0 3080 #define rx_x1_status0_aerMMDdevTypeSelect_PMA_PMD 1 3081 #define rx_x1_status0_aerMMDdevTypeSelect_PCS 3 3082 #define rx_x1_status0_aerMMDdevTypeSelect_PHY 4 3083 #define rx_x1_status0_aerMMDdevTypeSelect_DTE 5 3084 #define rx_x1_status0_aerMMDdevTypeSelect_CL73_AN 7 3085 3086 /**************************************************************************** 3087 * Enums: rx_x1_status0_aerMMDportSelect 3088 */ 3089 #define rx_x1_status0_aerMMDportSelect_ln0 0 3090 #define rx_x1_status0_aerMMDportSelect_ln1 1 3091 #define rx_x1_status0_aerMMDportSelect_ln2 2 3092 #define rx_x1_status0_aerMMDportSelect_ln3 3 3093 #define rx_x1_status0_aerMMDportSelect_BCST_ln0_1_2_3 511 3094 #define rx_x1_status0_aerMMDportSelect_BCST_ln0_1 512 3095 #define rx_x1_status0_aerMMDportSelect_BCST_ln2_3 513 3096 3097 /**************************************************************************** 3098 * Enums: rx_x1_status0_firmwareModeSelect 3099 */ 3100 #define rx_x1_status0_firmwareModeSelect_DEFAULT 0 3101 #define rx_x1_status0_firmwareModeSelect_SFP_OPT_LR 1 3102 #define rx_x1_status0_firmwareModeSelect_SFP_DAC 2 3103 #define rx_x1_status0_firmwareModeSelect_XLAUI 3 3104 #define rx_x1_status0_firmwareModeSelect_LONG_CH_6G 4 3105 3106 /**************************************************************************** 3107 * Enums: rx_x1_status0_tempIdxSelect 3108 */ 3109 #define rx_x1_status0_tempIdxSelect_LTE__22p9C 15 3110 #define rx_x1_status0_tempIdxSelect_LTE__12p6C 14 3111 #define rx_x1_status0_tempIdxSelect_LTE__3p0C 13 3112 #define rx_x1_status0_tempIdxSelect_LTE_6p7C 12 3113 #define rx_x1_status0_tempIdxSelect_LTE_16p4C 11 3114 #define rx_x1_status0_tempIdxSelect_LTE_26p6C 10 3115 #define rx_x1_status0_tempIdxSelect_LTE_36p3C 9 3116 #define rx_x1_status0_tempIdxSelect_LTE_46p0C 8 3117 #define rx_x1_status0_tempIdxSelect_LTE_56p2C 7 3118 #define rx_x1_status0_tempIdxSelect_LTE_65p9C 6 3119 #define rx_x1_status0_tempIdxSelect_LTE_75p6C 5 3120 #define rx_x1_status0_tempIdxSelect_LTE_85p3C 4 3121 #define rx_x1_status0_tempIdxSelect_LTE_95p5C 3 3122 #define rx_x1_status0_tempIdxSelect_LTE_105p2C 2 3123 #define rx_x1_status0_tempIdxSelect_LTE_114p9C 1 3124 #define rx_x1_status0_tempIdxSelect_LTE_125p1C 0 3125 3126 /**************************************************************************** 3127 * Enums: rx_x1_status0_port_mode 3128 */ 3129 #define rx_x1_status0_port_mode_QUAD_PORT 0 3130 #define rx_x1_status0_port_mode_TRI_1_PORT 1 3131 #define rx_x1_status0_port_mode_TRI_2_PORT 2 3132 #define rx_x1_status0_port_mode_DUAL_PORT 3 3133 #define rx_x1_status0_port_mode_SINGLE_PORT 4 3134 #define rx_x1_status0_port_mode_SINGLE_OCTAL_PORT 5 3135 3136 /**************************************************************************** 3137 * Enums: rx_x1_status0_rev_letter_enum 3138 */ 3139 #define rx_x1_status0_rev_letter_enum_REV_A 0 3140 #define rx_x1_status0_rev_letter_enum_REV_B 1 3141 #define rx_x1_status0_rev_letter_enum_REV_C 2 3142 #define rx_x1_status0_rev_letter_enum_REV_D 3 3143 3144 /**************************************************************************** 3145 * Enums: rx_x1_status0_rev_number_enum 3146 */ 3147 #define rx_x1_status0_rev_number_enum_REV_0 0 3148 #define rx_x1_status0_rev_number_enum_REV_1 1 3149 #define rx_x1_status0_rev_number_enum_REV_2 2 3150 #define rx_x1_status0_rev_number_enum_REV_3 3 3151 #define rx_x1_status0_rev_number_enum_REV_4 4 3152 #define rx_x1_status0_rev_number_enum_REV_5 5 3153 #define rx_x1_status0_rev_number_enum_REV_6 6 3154 #define rx_x1_status0_rev_number_enum_REV_7 7 3155 3156 /**************************************************************************** 3157 * Enums: rx_x1_status0_bonding_enum 3158 */ 3159 #define rx_x1_status0_bonding_enum_WIRE_BOND 0 3160 #define rx_x1_status0_bonding_enum_FLIP_CHIP 1 3161 3162 /**************************************************************************** 3163 * Enums: rx_x1_status0_tech_process 3164 */ 3165 #define rx_x1_status0_tech_process_PROCESS_90NM 0 3166 #define rx_x1_status0_tech_process_PROCESS_65NM 1 3167 #define rx_x1_status0_tech_process_PROCESS_40NM 2 3168 #define rx_x1_status0_tech_process_PROCESS_28NM 3 3169 #define rx_x1_status0_tech_process_PROCESS_16NM 4 3170 3171 /**************************************************************************** 3172 * Enums: rx_x1_status0_model_num 3173 */ 3174 #define rx_x1_status0_model_num_SERDES_CL73 0 3175 #define rx_x1_status0_model_num_XGXS_16G 1 3176 #define rx_x1_status0_model_num_HYPERCORE 2 3177 #define rx_x1_status0_model_num_HYPERLITE 3 3178 #define rx_x1_status0_model_num_PCIE_G2_PIPE 4 3179 #define rx_x1_status0_model_num_SERDES_1p25GBd 5 3180 #define rx_x1_status0_model_num_SATA2 6 3181 #define rx_x1_status0_model_num_QSGMII 7 3182 #define rx_x1_status0_model_num_XGXS10G 8 3183 #define rx_x1_status0_model_num_WARPCORE 9 3184 #define rx_x1_status0_model_num_XFICORE 10 3185 #define rx_x1_status0_model_num_RXFI 11 3186 #define rx_x1_status0_model_num_WARPLITE 12 3187 #define rx_x1_status0_model_num_PENTACORE 13 3188 #define rx_x1_status0_model_num_ESM 14 3189 #define rx_x1_status0_model_num_QUAD_SGMII 15 3190 #define rx_x1_status0_model_num_WARPCORE_3 16 3191 #define rx_x1_status0_model_num_TSC 17 3192 #define rx_x1_status0_model_num_TSC4E 18 3193 #define rx_x1_status0_model_num_TSC12E 19 3194 #define rx_x1_status0_model_num_TSC4F 20 3195 #define rx_x1_status0_model_num_TSC4F_GEN2 21 3196 #define rx_x1_status0_model_num_XGXS_CL73_90NM 29 3197 #define rx_x1_status0_model_num_SERDES_CL73_90NM 30 3198 #define rx_x1_status0_model_num_WARPCORE3 32 3199 #define rx_x1_status0_model_num_WARPCORE4_TSC 33 3200 #define rx_x1_status0_model_num_RXAUI 34 3201 #define rx_x1_status0_model_num_TSCE_GEN3 35 3202 #define rx_x1_status0_model_num_TSC4F_GEN3 36 3203 #define rx_x1_status0_model_num_TSCBH 37 3204 3205 /**************************************************************************** 3206 * Enums: rx_x1_status0_payload 3207 */ 3208 #define rx_x1_status0_payload_REPEAT_2_BYTES 0 3209 #define rx_x1_status0_payload_RAMPING 1 3210 #define rx_x1_status0_payload_CL48_CRPAT 2 3211 #define rx_x1_status0_payload_CL48_CJPAT 3 3212 #define rx_x1_status0_payload_CL36_LONG_CRPAT 4 3213 #define rx_x1_status0_payload_CL36_SHORT_CRPAT 5 3214 3215 /**************************************************************************** 3216 * Enums: rx_x1_status0_sc 3217 */ 3218 #define rx_x1_status0_sc_SPEED_10G_IEEE_KR1 0 3219 #define rx_x1_status0_sc_SPEED_25G_IEEE_KS1_CS1 1 3220 #define rx_x1_status0_sc_SPEED_25G_IEEE_KR1_CR1 2 3221 #define rx_x1_status0_sc_SPEED_40G_IEEE_KR4 3 3222 #define rx_x1_status0_sc_SPEED_40G_IEEE_CR4 4 3223 #define rx_x1_status0_sc_SPEED_50G_IEEE_KR1_CR1 5 3224 #define rx_x1_status0_sc_SPEED_100G_IEEE_KR4 6 3225 #define rx_x1_status0_sc_SPEED_100G_IEEE_CR4 7 3226 #define rx_x1_status0_sc_SPEED_100G_IEEE_KR2_CR2 8 3227 #define rx_x1_status0_sc_SPEED_200G_IEEE_KR4_CR4 9 3228 #define rx_x1_status0_sc_SPEED_400G_IEEE_X8 10 3229 #define rx_x1_status0_sc_SPEED_CL73_IEEE_20GVCO 11 3230 #define rx_x1_status0_sc_SPEED_CL73_IEEE_25GVCO 12 3231 #define rx_x1_status0_sc_SPEED_CL73_IEEE_26GVCO 13 3232 #define rx_x1_status0_sc_SPEED_20G_BRCM_CR1 14 3233 #define rx_x1_status0_sc_SPEED_20G_BRCM_KR1 15 3234 #define rx_x1_status0_sc_SPEED_25G_BRCM_CR1 16 3235 #define rx_x1_status0_sc_SPEED_25G_BRCM_KR1 17 3236 #define rx_x1_status0_sc_SPEED_40G_BRCM_CR2 18 3237 #define rx_x1_status0_sc_SPEED_40G_BRCM_KR2 19 3238 #define rx_x1_status0_sc_SPEED_50G_BRCM_CR2 20 3239 #define rx_x1_status0_sc_SPEED_50G_BRCM_KR2 21 3240 #define rx_x1_status0_sc_SPEED_50G_BRCM_CR4 22 3241 #define rx_x1_status0_sc_SPEED_50G_BRCM_KR4 23 3242 #define rx_x1_status0_sc_SPEED_50G_BRCM_FEC_544_CR2_KR2 24 3243 #define rx_x1_status0_sc_SPEED_RESERVED_19 25 3244 #define rx_x1_status0_sc_SPEED_50G_BRCM_FEC_544_CR1_KR1 26 3245 #define rx_x1_status0_sc_SPEED_50G_BRCM_NO_FEC_CR1_KR1 27 3246 #define rx_x1_status0_sc_SPEED_50G_BRCM_FEC_528_CR1_KR1 28 3247 #define rx_x1_status0_sc_SPEED_400G_BRCM_NO_FEC_KR8_CR8 29 3248 #define rx_x1_status0_sc_SPEED_400G_BRCM_FEC_KR8_CR8 30 3249 #define rx_x1_status0_sc_SPEED_200G_BRCM_NO_FEC_KR4_CR4 31 3250 #define rx_x1_status0_sc_SPEED_200G_BRCM_KR4_CR4 32 3251 #define rx_x1_status0_sc_SPEED_100G_BRCM_KR4_CR4 33 3252 #define rx_x1_status0_sc_SPEED_RESERVED_22 34 3253 #define rx_x1_status0_sc_SPEED_100G_BRCM_FEC_528_KR2_CR2 35 3254 #define rx_x1_status0_sc_SPEED_100G_BRCM_NO_FEC_KR2_CR2 36 3255 #define rx_x1_status0_sc_SPEED_100G_BRCM_NO_FEC_X4 37 3256 3257 /**************************************************************************** 3258 * Enums: rx_x1_status0_t_fifo_modes 3259 */ 3260 #define rx_x1_status0_t_fifo_modes_T_FIFO_INSERT_NO_AM 0 3261 #define rx_x1_status0_t_fifo_modes_T_FIFO_INSERT_4_AM 1 3262 #define rx_x1_status0_t_fifo_modes_T_FIFO_INSERT_20_AM 2 3263 #define rx_x1_status0_t_fifo_modes_T_FIFO_INSERT_2_AM 3 3264 3265 /**************************************************************************** 3266 * Enums: rx_x1_status0_t_enc_modes 3267 */ 3268 #define rx_x1_status0_t_enc_modes_T_ENC_MODE_BYPASS 0 3269 #define rx_x1_status0_t_enc_modes_T_ENC_MODE_CL49 1 3270 #define rx_x1_status0_t_enc_modes_T_ENC_MODE_CL82 2 3271 3272 /**************************************************************************** 3273 * Enums: rx_x1_status0_btmx_mode 3274 */ 3275 #define rx_x1_status0_btmx_mode_BS_BTMX_MODE_1to1 0 3276 #define rx_x1_status0_btmx_mode_BS_BTMX_MODE_2to1 1 3277 #define rx_x1_status0_btmx_mode_BS_BTMX_MODE_5to1 2 3278 3279 /**************************************************************************** 3280 * Enums: rx_x1_status0_t_type_cl82 3281 */ 3282 #define rx_x1_status0_t_type_cl82_T_TYPE_B1 5 3283 #define rx_x1_status0_t_type_cl82_T_TYPE_C 4 3284 #define rx_x1_status0_t_type_cl82_T_TYPE_S 3 3285 #define rx_x1_status0_t_type_cl82_T_TYPE_T 2 3286 #define rx_x1_status0_t_type_cl82_T_TYPE_D 1 3287 #define rx_x1_status0_t_type_cl82_T_TYPE_E 0 3288 3289 /**************************************************************************** 3290 * Enums: rx_x1_status0_txsm_state_cl82 3291 */ 3292 #define rx_x1_status0_txsm_state_cl82_TX_E 4 3293 #define rx_x1_status0_txsm_state_cl82_TX_T 3 3294 #define rx_x1_status0_txsm_state_cl82_TX_D 2 3295 #define rx_x1_status0_txsm_state_cl82_TX_C 1 3296 #define rx_x1_status0_txsm_state_cl82_TX_INIT 0 3297 3298 /**************************************************************************** 3299 * Enums: rx_x1_status0_ltxsm_state_cl82 3300 */ 3301 #define rx_x1_status0_ltxsm_state_cl82_TX_E 16 3302 #define rx_x1_status0_ltxsm_state_cl82_TX_T 8 3303 #define rx_x1_status0_ltxsm_state_cl82_TX_D 4 3304 #define rx_x1_status0_ltxsm_state_cl82_TX_C 2 3305 #define rx_x1_status0_ltxsm_state_cl82_TX_INIT 1 3306 3307 /**************************************************************************** 3308 * Enums: rx_x1_status0_r_type_coded_cl82 3309 */ 3310 #define rx_x1_status0_r_type_coded_cl82_R_TYPE_B1 32 3311 #define rx_x1_status0_r_type_coded_cl82_R_TYPE_C 16 3312 #define rx_x1_status0_r_type_coded_cl82_R_TYPE_S 8 3313 #define rx_x1_status0_r_type_coded_cl82_R_TYPE_T 4 3314 #define rx_x1_status0_r_type_coded_cl82_R_TYPE_D 2 3315 #define rx_x1_status0_r_type_coded_cl82_R_TYPE_E 1 3316 3317 /**************************************************************************** 3318 * Enums: rx_x1_status0_rxsm_state_cl82 3319 */ 3320 #define rx_x1_status0_rxsm_state_cl82_RX_E 16 3321 #define rx_x1_status0_rxsm_state_cl82_RX_T 8 3322 #define rx_x1_status0_rxsm_state_cl82_RX_D 4 3323 #define rx_x1_status0_rxsm_state_cl82_RX_C 2 3324 #define rx_x1_status0_rxsm_state_cl82_RX_INIT 1 3325 3326 /**************************************************************************** 3327 * Enums: rx_x1_status0_deskew_state 3328 */ 3329 #define rx_x1_status0_deskew_state_ALIGN_ACQUIRED 2 3330 #define rx_x1_status0_deskew_state_LOSS_OF_ALIGNMENT 1 3331 3332 /**************************************************************************** 3333 * Enums: rx_x1_status0_os_mode_enum 3334 */ 3335 #define rx_x1_status0_os_mode_enum_OS_MODE_1 0 3336 #define rx_x1_status0_os_mode_enum_OS_MODE_2 1 3337 #define rx_x1_status0_os_mode_enum_OS_MODE_4 2 3338 #define rx_x1_status0_os_mode_enum_OS_MODE_16p5 8 3339 #define rx_x1_status0_os_mode_enum_OS_MODE_20p625 12 3340 3341 /**************************************************************************** 3342 * Enums: rx_x1_status0_scr_modes 3343 */ 3344 #define rx_x1_status0_scr_modes_T_SCR_MODE_BYPASS 0 3345 #define rx_x1_status0_scr_modes_T_SCR_MODE_CL49 1 3346 #define rx_x1_status0_scr_modes_T_SCR_MODE_40G_2_LANE 2 3347 #define rx_x1_status0_scr_modes_T_SCR_MODE_100G 3 3348 #define rx_x1_status0_scr_modes_T_SCR_MODE_20G 4 3349 #define rx_x1_status0_scr_modes_T_SCR_MODE_40G_4_LANE 5 3350 3351 /**************************************************************************** 3352 * Enums: rx_x1_status0_descr_modes 3353 */ 3354 #define rx_x1_status0_descr_modes_R_DESCR_MODE_BYPASS 0 3355 #define rx_x1_status0_descr_modes_R_DESCR_MODE_CL49 1 3356 #define rx_x1_status0_descr_modes_R_DESCR_MODE_CL82 2 3357 3358 /**************************************************************************** 3359 * Enums: rx_x1_status0_r_dec_tl_mode 3360 */ 3361 #define rx_x1_status0_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 3362 #define rx_x1_status0_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 3363 #define rx_x1_status0_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 3364 3365 /**************************************************************************** 3366 * Enums: rx_x1_status0_r_dec_fsm_mode 3367 */ 3368 #define rx_x1_status0_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 3369 #define rx_x1_status0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 3370 #define rx_x1_status0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 3371 3372 /**************************************************************************** 3373 * Enums: rx_x1_status0_r_deskew_mode 3374 */ 3375 #define rx_x1_status0_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 3376 #define rx_x1_status0_r_deskew_mode_R_DESKEW_MODE_20G 1 3377 #define rx_x1_status0_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 3378 #define rx_x1_status0_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 3379 #define rx_x1_status0_r_deskew_mode_R_DESKEW_MODE_100G 4 3380 #define rx_x1_status0_r_deskew_mode_R_DESKEW_MODE_CL49 5 3381 #define rx_x1_status0_r_deskew_mode_R_DESKEW_MODE_CL91_QUAD 6 3382 #define rx_x1_status0_r_deskew_mode_R_DESKEW_MODE_CL91_SINGLE_BRCM 7 3383 #define rx_x1_status0_r_deskew_mode_R_DESKEW_MODE_CL91_DUAL_BRCM 8 3384 #define rx_x1_status0_r_deskew_mode_R_DESKEW_MODE_CL91_FC 9 3385 3386 /**************************************************************************** 3387 * Enums: rx_x1_status0_bs_dist_modes 3388 */ 3389 #define rx_x1_status0_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 3390 #define rx_x1_status0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 3391 #define rx_x1_status0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 3392 #define rx_x1_status0_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 3393 3394 /**************************************************************************** 3395 * Enums: rx_x1_status0_cl49_t_type 3396 */ 3397 #define rx_x1_status0_cl49_t_type_BAD_T_TYPE 15 3398 #define rx_x1_status0_cl49_t_type_T_TYPE_B0 11 3399 #define rx_x1_status0_cl49_t_type_T_TYPE_OB 10 3400 #define rx_x1_status0_cl49_t_type_T_TYPE_B1 9 3401 #define rx_x1_status0_cl49_t_type_T_TYPE_DB 8 3402 #define rx_x1_status0_cl49_t_type_T_TYPE_FC 7 3403 #define rx_x1_status0_cl49_t_type_T_TYPE_TB 6 3404 #define rx_x1_status0_cl49_t_type_T_TYPE_LI 5 3405 #define rx_x1_status0_cl49_t_type_T_TYPE_C 4 3406 #define rx_x1_status0_cl49_t_type_T_TYPE_S 3 3407 #define rx_x1_status0_cl49_t_type_T_TYPE_T 2 3408 #define rx_x1_status0_cl49_t_type_T_TYPE_D 1 3409 #define rx_x1_status0_cl49_t_type_T_TYPE_E 0 3410 3411 /**************************************************************************** 3412 * Enums: rx_x1_status0_cl49_txsm_states 3413 */ 3414 #define rx_x1_status0_cl49_txsm_states_TX_LI 5 3415 #define rx_x1_status0_cl49_txsm_states_TX_E 4 3416 #define rx_x1_status0_cl49_txsm_states_TX_T 3 3417 #define rx_x1_status0_cl49_txsm_states_TX_D 2 3418 #define rx_x1_status0_cl49_txsm_states_TX_C 1 3419 #define rx_x1_status0_cl49_txsm_states_TX_INIT 0 3420 3421 /**************************************************************************** 3422 * Enums: rx_x1_status0_cl49_ltxsm_states 3423 */ 3424 #define rx_x1_status0_cl49_ltxsm_states_TX_LI 32 3425 #define rx_x1_status0_cl49_ltxsm_states_TX_E 16 3426 #define rx_x1_status0_cl49_ltxsm_states_TX_T 8 3427 #define rx_x1_status0_cl49_ltxsm_states_TX_D 4 3428 #define rx_x1_status0_cl49_ltxsm_states_TX_C 2 3429 #define rx_x1_status0_cl49_ltxsm_states_TX_INIT 1 3430 3431 /**************************************************************************** 3432 * Enums: rx_x1_status0_burst_error_mode 3433 */ 3434 #define rx_x1_status0_burst_error_mode_BURST_ERROR_11_BITS 0 3435 #define rx_x1_status0_burst_error_mode_BURST_ERROR_16_BITS 1 3436 #define rx_x1_status0_burst_error_mode_BURST_ERROR_17_BITS 2 3437 #define rx_x1_status0_burst_error_mode_BURST_ERROR_18_BITS 3 3438 #define rx_x1_status0_burst_error_mode_BURST_ERROR_19_BITS 4 3439 #define rx_x1_status0_burst_error_mode_BURST_ERROR_20_BITS 5 3440 #define rx_x1_status0_burst_error_mode_BURST_ERROR_21_BITS 6 3441 #define rx_x1_status0_burst_error_mode_BURST_ERROR_22_BITS 7 3442 #define rx_x1_status0_burst_error_mode_BURST_ERROR_23_BITS 8 3443 #define rx_x1_status0_burst_error_mode_BURST_ERROR_24_BITS 9 3444 #define rx_x1_status0_burst_error_mode_BURST_ERROR_25_BITS 10 3445 #define rx_x1_status0_burst_error_mode_BURST_ERROR_26_BITS 11 3446 #define rx_x1_status0_burst_error_mode_BURST_ERROR_27_BITS 12 3447 #define rx_x1_status0_burst_error_mode_BURST_ERROR_28_BITS 13 3448 #define rx_x1_status0_burst_error_mode_BURST_ERROR_29_BITS 14 3449 #define rx_x1_status0_burst_error_mode_BURST_ERROR_30_BITS 15 3450 #define rx_x1_status0_burst_error_mode_BURST_ERROR_31_BITS 16 3451 #define rx_x1_status0_burst_error_mode_BURST_ERROR_32_BITS 17 3452 #define rx_x1_status0_burst_error_mode_BURST_ERROR_33_BITS 18 3453 #define rx_x1_status0_burst_error_mode_BURST_ERROR_34_BITS 19 3454 #define rx_x1_status0_burst_error_mode_BURST_ERROR_35_BITS 20 3455 #define rx_x1_status0_burst_error_mode_BURST_ERROR_36_BITS 21 3456 #define rx_x1_status0_burst_error_mode_BURST_ERROR_37_BITS 22 3457 #define rx_x1_status0_burst_error_mode_BURST_ERROR_38_BITS 23 3458 #define rx_x1_status0_burst_error_mode_BURST_ERROR_39_BITS 24 3459 #define rx_x1_status0_burst_error_mode_BURST_ERROR_40_BITS 25 3460 #define rx_x1_status0_burst_error_mode_BURST_ERROR_41_BITS 26 3461 3462 /**************************************************************************** 3463 * Enums: rx_x1_status0_bermon_state 3464 */ 3465 #define rx_x1_status0_bermon_state_HI_BER 4 3466 #define rx_x1_status0_bermon_state_GOOD_BER 3 3467 #define rx_x1_status0_bermon_state_BER_TEST_SH 2 3468 #define rx_x1_status0_bermon_state_START_TIMER 1 3469 #define rx_x1_status0_bermon_state_BER_MT_INIT 0 3470 3471 /**************************************************************************** 3472 * Enums: rx_x1_status0_rxsm_state_cl49 3473 */ 3474 #define rx_x1_status0_rxsm_state_cl49_RX_LI 32 3475 #define rx_x1_status0_rxsm_state_cl49_RX_E 16 3476 #define rx_x1_status0_rxsm_state_cl49_RX_T 8 3477 #define rx_x1_status0_rxsm_state_cl49_RX_D 4 3478 #define rx_x1_status0_rxsm_state_cl49_RX_C 2 3479 #define rx_x1_status0_rxsm_state_cl49_RX_INIT 1 3480 3481 /**************************************************************************** 3482 * Enums: rx_x1_status0_r_type 3483 */ 3484 #define rx_x1_status0_r_type_BAD_R_TYPE 15 3485 #define rx_x1_status0_r_type_R_TYPE_B0 11 3486 #define rx_x1_status0_r_type_R_TYPE_OB 10 3487 #define rx_x1_status0_r_type_R_TYPE_B1 9 3488 #define rx_x1_status0_r_type_R_TYPE_DB 8 3489 #define rx_x1_status0_r_type_R_TYPE_FC 7 3490 #define rx_x1_status0_r_type_R_TYPE_TB 6 3491 #define rx_x1_status0_r_type_R_TYPE_LI 5 3492 #define rx_x1_status0_r_type_R_TYPE_C 4 3493 #define rx_x1_status0_r_type_R_TYPE_S 3 3494 #define rx_x1_status0_r_type_R_TYPE_T 2 3495 #define rx_x1_status0_r_type_R_TYPE_D 1 3496 #define rx_x1_status0_r_type_R_TYPE_E 0 3497 3498 /**************************************************************************** 3499 * Enums: rx_x1_status0_am_lock_state 3500 */ 3501 #define rx_x1_status0_am_lock_state_INVALID_AM 512 3502 #define rx_x1_status0_am_lock_state_GOOD_AM 256 3503 #define rx_x1_status0_am_lock_state_COMP_AM 128 3504 #define rx_x1_status0_am_lock_state_TIMER_2 64 3505 #define rx_x1_status0_am_lock_state_AM_2_GOOD 32 3506 #define rx_x1_status0_am_lock_state_COMP_2ND 16 3507 #define rx_x1_status0_am_lock_state_TIMER_1 8 3508 #define rx_x1_status0_am_lock_state_FIND_1ST 4 3509 #define rx_x1_status0_am_lock_state_AM_RESET_CNT 2 3510 #define rx_x1_status0_am_lock_state_AM_LOCK_INIT 1 3511 3512 /**************************************************************************** 3513 * Enums: rx_x1_status0_msg_selector 3514 */ 3515 #define rx_x1_status0_msg_selector_RESERVED 0 3516 #define rx_x1_status0_msg_selector_VALUE_802p3 1 3517 #define rx_x1_status0_msg_selector_VALUE_802p9 2 3518 #define rx_x1_status0_msg_selector_VALUE_802p5 3 3519 #define rx_x1_status0_msg_selector_VALUE_1394 4 3520 3521 /**************************************************************************** 3522 * Enums: rx_x1_status0_synce_enum_stage1 3523 */ 3524 #define rx_x1_status0_synce_enum_stage1_SYNCE_NO_DIV 0 3525 #define rx_x1_status0_synce_enum_stage1_SYNCE_DIV_7 1 3526 #define rx_x1_status0_synce_enum_stage1_SYNCE_DIV_11 2 3527 3528 /**************************************************************************** 3529 * Enums: rx_x1_status0_synce_enum_stage0 3530 */ 3531 #define rx_x1_status0_synce_enum_stage0_SYNCE_NO_DIV 0 3532 #define rx_x1_status0_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 3533 #define rx_x1_status0_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 3534 3535 /**************************************************************************** 3536 * Enums: rx_x1_status0_cl91_sync_state 3537 */ 3538 #define rx_x1_status0_cl91_sync_state_FIND_1ST 0 3539 #define rx_x1_status0_cl91_sync_state_COUNT_NEXT 1 3540 #define rx_x1_status0_cl91_sync_state_COMP_2ND 2 3541 #define rx_x1_status0_cl91_sync_state_TWO_GOOD 3 3542 3543 /**************************************************************************** 3544 * Enums: rx_x1_status0_RS_FEC_sync_state 3545 */ 3546 #define rx_x1_status0_RS_FEC_sync_state_LOCK_INIT 0 3547 #define rx_x1_status0_RS_FEC_sync_state_FIND_1ST 1 3548 #define rx_x1_status0_RS_FEC_sync_state_COUNT_NEXT 2 3549 #define rx_x1_status0_RS_FEC_sync_state_COMP_2ND 3 3550 #define rx_x1_status0_RS_FEC_sync_state_TWO_GOOD 4 3551 3552 /**************************************************************************** 3553 * Enums: rx_x1_status0_cl91_algn_state 3554 */ 3555 #define rx_x1_status0_cl91_algn_state_LOSS_OF_ALIGNMENT 0 3556 #define rx_x1_status0_cl91_algn_state_DESKEW 1 3557 #define rx_x1_status0_cl91_algn_state_DESKEW_FAIL 2 3558 #define rx_x1_status0_cl91_algn_state_ALIGN_ACQUIRED 3 3559 #define rx_x1_status0_cl91_algn_state_CW_GOOD 4 3560 #define rx_x1_status0_cl91_algn_state_CW_BAD 5 3561 #define rx_x1_status0_cl91_algn_state_THREE_BAD 6 3562 3563 /**************************************************************************** 3564 * Enums: rx_x1_status0_RS_FEC_algn_state 3565 */ 3566 #define rx_x1_status0_RS_FEC_algn_state_LOSS_OF_ALIGNMENT 0 3567 #define rx_x1_status0_RS_FEC_algn_state_DESKEW 1 3568 #define rx_x1_status0_RS_FEC_algn_state_DESKEW_FAIL 2 3569 #define rx_x1_status0_RS_FEC_algn_state_ALIGN_ACQUIRED 3 3570 #define rx_x1_status0_RS_FEC_algn_state_CW_GOOD 4 3571 #define rx_x1_status0_RS_FEC_algn_state_CW_BAD 5 3572 #define rx_x1_status0_RS_FEC_algn_state_THREE_BAD 6 3573 3574 /**************************************************************************** 3575 * Enums: rx_x1_status0_fec_sel_override 3576 */ 3577 #define rx_x1_status0_fec_sel_override_NO_OVERRIDE 0 3578 #define rx_x1_status0_fec_sel_override_NO_FEC 1 3579 #define rx_x1_status0_fec_sel_override_FEC_CL74 2 3580 #define rx_x1_status0_fec_sel_override_FEC_CL91 3 3581 3582 /**************************************************************************** 3583 * Enums: rx_x1_status0_cl91_blksync_mode 3584 */ 3585 #define rx_x1_status0_cl91_blksync_mode_R_BLKSYNC_NO_CL91_FEC 0 3586 #define rx_x1_status0_cl91_blksync_mode_R_BLKSYNC_CL91_QUAD_LANE_FEC 1 3587 #define rx_x1_status0_cl91_blksync_mode_R_BLKSYNC_CL91_DUAL_LANE_FEC 2 3588 #define rx_x1_status0_cl91_blksync_mode_R_BLKSYNC_CL91_SINGLE_LANE_FEC 3 3589 #define rx_x1_status0_cl91_blksync_mode_R_BLKSYNC_CL91_FC_FEC 4 3590 3591 /**************************************************************************** 3592 * Enums: rx_x1_status0_r_merge_mode 3593 */ 3594 #define rx_x1_status0_r_merge_mode_R_MERGE_MODE_BYPASS 0 3595 #define rx_x1_status0_r_merge_mode_R_MERGE_MODE_CL91_FC 1 3596 #define rx_x1_status0_r_merge_mode_R_MERGE_MODE_CL91_SINGLE_LANE 2 3597 #define rx_x1_status0_r_merge_mode_R_MERGE_MODE_CL91_DUAL_LANE 3 3598 #define rx_x1_status0_r_merge_mode_R_MERGE_MODE_CL91_QUAD_LANE 4 3599 3600 /**************************************************************************** 3601 * Enums: rx_x1_status0_r_tc_mode 3602 */ 3603 #define rx_x1_status0_r_tc_mode_R_TC_MODE_SINGLE 0 3604 #define rx_x1_status0_r_tc_mode_R_TC_MODE_DUAL 1 3605 #define rx_x1_status0_r_tc_mode_R_TC_MODE_QUAD 2 3606 3607 /**************************************************************************** 3608 * Enums: rx_x1_status0_r_tc_out_mode 3609 */ 3610 #define rx_x1_status0_r_tc_out_mode_R_TC_OUT_MODE_SINGLE 0 3611 #define rx_x1_status0_r_tc_out_mode_R_TC_OUT_MODE_DUAL 1 3612 #define rx_x1_status0_r_tc_out_mode_R_TC_OUT_MODE_QUAD 2 3613 3614 /**************************************************************************** 3615 * Enums: rx_x1_status0_cl91_fec_mode 3616 */ 3617 #define rx_x1_status0_cl91_fec_mode_NO_CL91_FEC 0 3618 #define rx_x1_status0_cl91_fec_mode_CL91_SINGLE_LANE_FC 1 3619 #define rx_x1_status0_cl91_fec_mode_CL91_SINGLE_LANE_BRCM_PROP 2 3620 #define rx_x1_status0_cl91_fec_mode_CL91_DUAL_LANE_BRCM_PROP 3 3621 #define rx_x1_status0_cl91_fec_mode_CL91_QUAD_LANE 4 3622 #define rx_x1_status0_cl91_fec_mode_IEEE_25G_CL91_SINGLE_LANE 5 3623 3624 /**************************************************************************** 3625 * Enums: rx_x1_status0_RS_FEC_fec_mode 3626 */ 3627 #define rx_x1_status0_RS_FEC_fec_mode_NO_RS_FEC_FEC 0 3628 #define rx_x1_status0_RS_FEC_fec_mode_N_A 1 3629 #define rx_x1_status0_RS_FEC_fec_mode_RS_FEC_SINGLE_LANE_BRCM_PROP 2 3630 #define rx_x1_status0_RS_FEC_fec_mode_RS_FEC_DUAL_LANE_BRCM_PROP 3 3631 #define rx_x1_status0_RS_FEC_fec_mode_RS_FEC_QUAD_LANE 4 3632 #define rx_x1_status0_RS_FEC_fec_mode_IEEE_25G_RS_FEC_SINGLE_LANE 5 3633 3634 /**************************************************************************** 3635 * Enums: rx_x1_status0_am_spacing_mul 3636 */ 3637 #define rx_x1_status0_am_spacing_mul_AM_SPACING_MUL_2 0 3638 #define rx_x1_status0_am_spacing_mul_AM_SPACING_MUL_4 1 3639 #define rx_x1_status0_am_spacing_mul_AM_SPACING_MUL_5 2 3640 #define rx_x1_status0_am_spacing_mul_AM_SPACING_MUL_20 3 3641 3642 /**************************************************************************** 3643 * Enums: rx_x2_status0_cl36TxEEEStates_l 3644 */ 3645 #define rx_x2_status0_cl36TxEEEStates_l_TX_REFRESH 8 3646 #define rx_x2_status0_cl36TxEEEStates_l_TX_QUIET 4 3647 #define rx_x2_status0_cl36TxEEEStates_l_TX_SLEEP 2 3648 #define rx_x2_status0_cl36TxEEEStates_l_TX_ACTIVE 1 3649 3650 /**************************************************************************** 3651 * Enums: rx_x2_status0_cl36TxEEEStates_c 3652 */ 3653 #define rx_x2_status0_cl36TxEEEStates_c_TX_REFRESH 3 3654 #define rx_x2_status0_cl36TxEEEStates_c_TX_QUIET 2 3655 #define rx_x2_status0_cl36TxEEEStates_c_TX_SLEEP 1 3656 #define rx_x2_status0_cl36TxEEEStates_c_TX_ACTIVE 0 3657 3658 /**************************************************************************** 3659 * Enums: rx_x2_status0_cl49TxEEEStates_l 3660 */ 3661 #define rx_x2_status0_cl49TxEEEStates_l_SCR_RESET_2 64 3662 #define rx_x2_status0_cl49TxEEEStates_l_SCR_RESET_1 32 3663 #define rx_x2_status0_cl49TxEEEStates_l_TX_WAKE 16 3664 #define rx_x2_status0_cl49TxEEEStates_l_TX_REFRESH 8 3665 #define rx_x2_status0_cl49TxEEEStates_l_TX_QUIET 4 3666 #define rx_x2_status0_cl49TxEEEStates_l_TX_SLEEP 2 3667 #define rx_x2_status0_cl49TxEEEStates_l_TX_ACTIVE 1 3668 3669 /**************************************************************************** 3670 * Enums: rx_x2_status0_fec_req_enum 3671 */ 3672 #define rx_x2_status0_fec_req_enum_FEC_not_supported 0 3673 #define rx_x2_status0_fec_req_enum_FEC_supported_but_not_requested 1 3674 #define rx_x2_status0_fec_req_enum_invalid_setting 2 3675 #define rx_x2_status0_fec_req_enum_FEC_supported_and_requested 3 3676 3677 /**************************************************************************** 3678 * Enums: rx_x2_status0_cl73_pause_enum 3679 */ 3680 #define rx_x2_status0_cl73_pause_enum_No_PAUSE_ability 0 3681 #define rx_x2_status0_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 3682 #define rx_x2_status0_cl73_pause_enum_Symmetric_PAUSE_ability 1 3683 #define rx_x2_status0_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 3684 3685 /**************************************************************************** 3686 * Enums: rx_x2_status0_cl49TxEEEStates_c 3687 */ 3688 #define rx_x2_status0_cl49TxEEEStates_c_SCR_RESET_2 6 3689 #define rx_x2_status0_cl49TxEEEStates_c_SCR_RESET_1 5 3690 #define rx_x2_status0_cl49TxEEEStates_c_TX_WAKE 4 3691 #define rx_x2_status0_cl49TxEEEStates_c_TX_REFRESH 3 3692 #define rx_x2_status0_cl49TxEEEStates_c_TX_QUIET 2 3693 #define rx_x2_status0_cl49TxEEEStates_c_TX_SLEEP 1 3694 #define rx_x2_status0_cl49TxEEEStates_c_TX_ACTIVE 0 3695 3696 /**************************************************************************** 3697 * Enums: rx_x2_status0_cl36RxEEEStates_l 3698 */ 3699 #define rx_x2_status0_cl36RxEEEStates_l_RX_LINK_FAIL 32 3700 #define rx_x2_status0_cl36RxEEEStates_l_RX_WTF 16 3701 #define rx_x2_status0_cl36RxEEEStates_l_RX_WAKE 8 3702 #define rx_x2_status0_cl36RxEEEStates_l_RX_QUIET 4 3703 #define rx_x2_status0_cl36RxEEEStates_l_RX_SLEEP 2 3704 #define rx_x2_status0_cl36RxEEEStates_l_RX_ACTIVE 1 3705 3706 /**************************************************************************** 3707 * Enums: rx_x2_status0_cl36RxEEEStates_c 3708 */ 3709 #define rx_x2_status0_cl36RxEEEStates_c_RX_LINK_FAIL 5 3710 #define rx_x2_status0_cl36RxEEEStates_c_RX_WTF 4 3711 #define rx_x2_status0_cl36RxEEEStates_c_RX_WAKE 3 3712 #define rx_x2_status0_cl36RxEEEStates_c_RX_QUIET 2 3713 #define rx_x2_status0_cl36RxEEEStates_c_RX_SLEEP 1 3714 #define rx_x2_status0_cl36RxEEEStates_c_RX_ACTIVE 0 3715 3716 /**************************************************************************** 3717 * Enums: rx_x2_status0_cl49RxEEEStates_l 3718 */ 3719 #define rx_x2_status0_cl49RxEEEStates_l_RX_LINK_FAIL 32 3720 #define rx_x2_status0_cl49RxEEEStates_l_RX_WTF 16 3721 #define rx_x2_status0_cl49RxEEEStates_l_RX_WAKE 8 3722 #define rx_x2_status0_cl49RxEEEStates_l_RX_QUIET 4 3723 #define rx_x2_status0_cl49RxEEEStates_l_RX_SLEEP 2 3724 #define rx_x2_status0_cl49RxEEEStates_l_RX_ACTIVE 1 3725 3726 /**************************************************************************** 3727 * Enums: rx_x2_status0_cl49RxEEEStates_c 3728 */ 3729 #define rx_x2_status0_cl49RxEEEStates_c_RX_LINK_FAIL 5 3730 #define rx_x2_status0_cl49RxEEEStates_c_RX_WTF 4 3731 #define rx_x2_status0_cl49RxEEEStates_c_RX_WAKE 3 3732 #define rx_x2_status0_cl49RxEEEStates_c_RX_QUIET 2 3733 #define rx_x2_status0_cl49RxEEEStates_c_RX_SLEEP 1 3734 #define rx_x2_status0_cl49RxEEEStates_c_RX_ACTIVE 0 3735 3736 /**************************************************************************** 3737 * Enums: rx_x2_status0_cl48TxEEEStates_l 3738 */ 3739 #define rx_x2_status0_cl48TxEEEStates_l_TX_REFRESH 8 3740 #define rx_x2_status0_cl48TxEEEStates_l_TX_QUIET 4 3741 #define rx_x2_status0_cl48TxEEEStates_l_TX_SLEEP 2 3742 #define rx_x2_status0_cl48TxEEEStates_l_TX_ACTIVE 1 3743 3744 /**************************************************************************** 3745 * Enums: rx_x2_status0_cl48TxEEEStates_c 3746 */ 3747 #define rx_x2_status0_cl48TxEEEStates_c_TX_REFRESH 3 3748 #define rx_x2_status0_cl48TxEEEStates_c_TX_QUIET 2 3749 #define rx_x2_status0_cl48TxEEEStates_c_TX_SLEEP 1 3750 #define rx_x2_status0_cl48TxEEEStates_c_TX_ACTIVE 0 3751 3752 /**************************************************************************** 3753 * Enums: rx_x2_status0_cl48RxEEEStates_l 3754 */ 3755 #define rx_x2_status0_cl48RxEEEStates_l_RX_LINK_FAIL 32 3756 #define rx_x2_status0_cl48RxEEEStates_l_RX_WAKE 16 3757 #define rx_x2_status0_cl48RxEEEStates_l_RX_QUIET 8 3758 #define rx_x2_status0_cl48RxEEEStates_l_RX_DEACT 4 3759 #define rx_x2_status0_cl48RxEEEStates_l_RX_SLEEP 2 3760 #define rx_x2_status0_cl48RxEEEStates_l_RX_ACTIVE 1 3761 3762 /**************************************************************************** 3763 * Enums: rx_x2_status0_cl48RxEEEStates_c 3764 */ 3765 #define rx_x2_status0_cl48RxEEEStates_c_RX_LINK_FAIL 5 3766 #define rx_x2_status0_cl48RxEEEStates_c_RX_WAKE 4 3767 #define rx_x2_status0_cl48RxEEEStates_c_RX_QUIET 3 3768 #define rx_x2_status0_cl48RxEEEStates_c_RX_DEACT 2 3769 #define rx_x2_status0_cl48RxEEEStates_c_RX_SLEEP 1 3770 #define rx_x2_status0_cl48RxEEEStates_c_RX_ACTIVE 0 3771 3772 /**************************************************************************** 3773 * Enums: rx_x2_status0_IQP_Options 3774 */ 3775 #define rx_x2_status0_IQP_Options_i50uA 0 3776 #define rx_x2_status0_IQP_Options_i100uA 1 3777 #define rx_x2_status0_IQP_Options_i150uA 2 3778 #define rx_x2_status0_IQP_Options_i200uA 3 3779 #define rx_x2_status0_IQP_Options_i250uA 4 3780 #define rx_x2_status0_IQP_Options_i300uA 5 3781 #define rx_x2_status0_IQP_Options_i350uA 6 3782 #define rx_x2_status0_IQP_Options_i400uA 7 3783 #define rx_x2_status0_IQP_Options_i450uA 8 3784 #define rx_x2_status0_IQP_Options_i500uA 9 3785 #define rx_x2_status0_IQP_Options_i550uA 10 3786 #define rx_x2_status0_IQP_Options_i600uA 11 3787 #define rx_x2_status0_IQP_Options_i650uA 12 3788 #define rx_x2_status0_IQP_Options_i700uA 13 3789 #define rx_x2_status0_IQP_Options_i750uA 14 3790 #define rx_x2_status0_IQP_Options_i800uA 15 3791 3792 /**************************************************************************** 3793 * Enums: rx_x2_status0_IDriver_Options 3794 */ 3795 #define rx_x2_status0_IDriver_Options_v680mV 0 3796 #define rx_x2_status0_IDriver_Options_v730mV 1 3797 #define rx_x2_status0_IDriver_Options_v780mV 2 3798 #define rx_x2_status0_IDriver_Options_v830mV 3 3799 #define rx_x2_status0_IDriver_Options_v880mV 4 3800 #define rx_x2_status0_IDriver_Options_v930mV 5 3801 #define rx_x2_status0_IDriver_Options_v980mV 6 3802 #define rx_x2_status0_IDriver_Options_v1010mV 7 3803 #define rx_x2_status0_IDriver_Options_v1040mV 8 3804 #define rx_x2_status0_IDriver_Options_v1060mV 9 3805 #define rx_x2_status0_IDriver_Options_v1070mV 10 3806 #define rx_x2_status0_IDriver_Options_v1080mV 11 3807 #define rx_x2_status0_IDriver_Options_v1085mV 12 3808 #define rx_x2_status0_IDriver_Options_v1090mV 13 3809 #define rx_x2_status0_IDriver_Options_v1095mV 14 3810 #define rx_x2_status0_IDriver_Options_v1100mV 15 3811 3812 /**************************************************************************** 3813 * Enums: rx_x2_status0_operationModes 3814 */ 3815 #define rx_x2_status0_operationModes_XGXS 0 3816 #define rx_x2_status0_operationModes_XGXG_nCC 1 3817 #define rx_x2_status0_operationModes_Indlane_OS8 4 3818 #define rx_x2_status0_operationModes_IndLane_OS5 5 3819 #define rx_x2_status0_operationModes_PCI 7 3820 #define rx_x2_status0_operationModes_XGXS_nLQ 8 3821 #define rx_x2_status0_operationModes_XGXS_nLQnCC 9 3822 #define rx_x2_status0_operationModes_PBypass 10 3823 #define rx_x2_status0_operationModes_PBypass_nDSK 11 3824 #define rx_x2_status0_operationModes_ComboCoreMode 12 3825 #define rx_x2_status0_operationModes_Clocks_off 15 3826 3827 /**************************************************************************** 3828 * Enums: rx_x2_status0_actualSpeeds 3829 */ 3830 #define rx_x2_status0_actualSpeeds_dr_10M 0 3831 #define rx_x2_status0_actualSpeeds_dr_100M 1 3832 #define rx_x2_status0_actualSpeeds_dr_1G 2 3833 #define rx_x2_status0_actualSpeeds_dr_2p5G 3 3834 #define rx_x2_status0_actualSpeeds_dr_5G_X4 4 3835 #define rx_x2_status0_actualSpeeds_dr_6G_X4 5 3836 #define rx_x2_status0_actualSpeeds_dr_10G_HiG 6 3837 #define rx_x2_status0_actualSpeeds_dr_10G_CX4 7 3838 #define rx_x2_status0_actualSpeeds_dr_12G_HiG 8 3839 #define rx_x2_status0_actualSpeeds_dr_12p5G_X4 9 3840 #define rx_x2_status0_actualSpeeds_dr_13G_X4 10 3841 #define rx_x2_status0_actualSpeeds_dr_15G_X4 11 3842 #define rx_x2_status0_actualSpeeds_dr_16G_X4 12 3843 #define rx_x2_status0_actualSpeeds_dr_1G_KX 13 3844 #define rx_x2_status0_actualSpeeds_dr_10G_KX4 14 3845 #define rx_x2_status0_actualSpeeds_dr_10G_KR 15 3846 #define rx_x2_status0_actualSpeeds_dr_5G 16 3847 #define rx_x2_status0_actualSpeeds_dr_6p4G 17 3848 #define rx_x2_status0_actualSpeeds_dr_20G_X4 18 3849 #define rx_x2_status0_actualSpeeds_dr_21G_X4 19 3850 #define rx_x2_status0_actualSpeeds_dr_25G_X4 20 3851 #define rx_x2_status0_actualSpeeds_dr_10G_HiG_DXGXS 21 3852 #define rx_x2_status0_actualSpeeds_dr_10G_DXGXS 22 3853 #define rx_x2_status0_actualSpeeds_dr_10p5G_HiG_DXGXS 23 3854 #define rx_x2_status0_actualSpeeds_dr_10p5G_DXGXS 24 3855 #define rx_x2_status0_actualSpeeds_dr_12p773G_HiG_DXGXS 25 3856 #define rx_x2_status0_actualSpeeds_dr_12p773G_DXGXS 26 3857 #define rx_x2_status0_actualSpeeds_dr_10G_XFI 27 3858 #define rx_x2_status0_actualSpeeds_dr_40G 28 3859 #define rx_x2_status0_actualSpeeds_dr_20G_HiG_DXGXS 29 3860 #define rx_x2_status0_actualSpeeds_dr_20G_DXGXS 30 3861 #define rx_x2_status0_actualSpeeds_dr_10G_SFI 31 3862 #define rx_x2_status0_actualSpeeds_dr_31p5G 32 3863 #define rx_x2_status0_actualSpeeds_dr_32p7G 33 3864 #define rx_x2_status0_actualSpeeds_dr_20G_SCR 34 3865 #define rx_x2_status0_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 3866 #define rx_x2_status0_actualSpeeds_dr_10G_DXGXS_SCR 36 3867 #define rx_x2_status0_actualSpeeds_dr_12G_R2 37 3868 #define rx_x2_status0_actualSpeeds_dr_10G_X2 38 3869 #define rx_x2_status0_actualSpeeds_dr_40G_KR4 39 3870 #define rx_x2_status0_actualSpeeds_dr_40G_CR4 40 3871 #define rx_x2_status0_actualSpeeds_dr_100G_CR10 41 3872 #define rx_x2_status0_actualSpeeds_dr_15p75G_DXGXS 44 3873 #define rx_x2_status0_actualSpeeds_dr_20G_KR2 57 3874 #define rx_x2_status0_actualSpeeds_dr_20G_CR2 58 3875 3876 /**************************************************************************** 3877 * Enums: rx_x2_status0_actualSpeedsMisc1 3878 */ 3879 #define rx_x2_status0_actualSpeedsMisc1_dr_2500BRCM_X1 16 3880 #define rx_x2_status0_actualSpeedsMisc1_dr_5000BRCM_X4 17 3881 #define rx_x2_status0_actualSpeedsMisc1_dr_6000BRCM_X4 18 3882 #define rx_x2_status0_actualSpeedsMisc1_dr_10GHiGig_X4 19 3883 #define rx_x2_status0_actualSpeedsMisc1_dr_10GBASE_CX4 20 3884 #define rx_x2_status0_actualSpeedsMisc1_dr_12GHiGig_X4 21 3885 #define rx_x2_status0_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 3886 #define rx_x2_status0_actualSpeedsMisc1_dr_13GHiGig_X4 23 3887 #define rx_x2_status0_actualSpeedsMisc1_dr_15GHiGig_X4 24 3888 #define rx_x2_status0_actualSpeedsMisc1_dr_16GHiGig_X4 25 3889 #define rx_x2_status0_actualSpeedsMisc1_dr_5000BRCM_X1 26 3890 #define rx_x2_status0_actualSpeedsMisc1_dr_6363BRCM_X1 27 3891 #define rx_x2_status0_actualSpeedsMisc1_dr_20GHiGig_X4 28 3892 #define rx_x2_status0_actualSpeedsMisc1_dr_21GHiGig_X4 29 3893 #define rx_x2_status0_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 3894 #define rx_x2_status0_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 3895 3896 /**************************************************************************** 3897 * Enums: rx_x2_status0_IndLaneModes 3898 */ 3899 #define rx_x2_status0_IndLaneModes_SWSDR_div2 0 3900 #define rx_x2_status0_IndLaneModes_SWSDR_div1 1 3901 #define rx_x2_status0_IndLaneModes_DWSDR_div2 2 3902 #define rx_x2_status0_IndLaneModes_DWSDR_div1 3 3903 3904 /**************************************************************************** 3905 * Enums: rx_x2_status0_prbsSelect 3906 */ 3907 #define rx_x2_status0_prbsSelect_prbs7 0 3908 #define rx_x2_status0_prbsSelect_prbs15 1 3909 #define rx_x2_status0_prbsSelect_prbs23 2 3910 #define rx_x2_status0_prbsSelect_prbs31 3 3911 3912 /**************************************************************************** 3913 * Enums: rx_x2_status0_vcoDivider 3914 */ 3915 #define rx_x2_status0_vcoDivider_div32 0 3916 #define rx_x2_status0_vcoDivider_div36 1 3917 #define rx_x2_status0_vcoDivider_div40 2 3918 #define rx_x2_status0_vcoDivider_div42 3 3919 #define rx_x2_status0_vcoDivider_div48 4 3920 #define rx_x2_status0_vcoDivider_div50 5 3921 #define rx_x2_status0_vcoDivider_div52 6 3922 #define rx_x2_status0_vcoDivider_div54 7 3923 #define rx_x2_status0_vcoDivider_div60 8 3924 #define rx_x2_status0_vcoDivider_div64 9 3925 #define rx_x2_status0_vcoDivider_div66 10 3926 #define rx_x2_status0_vcoDivider_div68 11 3927 #define rx_x2_status0_vcoDivider_div70 12 3928 #define rx_x2_status0_vcoDivider_div80 13 3929 #define rx_x2_status0_vcoDivider_div92 14 3930 #define rx_x2_status0_vcoDivider_div100 15 3931 3932 /**************************************************************************** 3933 * Enums: rx_x2_status0_refClkSelect 3934 */ 3935 #define rx_x2_status0_refClkSelect_clk_156p25MHz 1 3936 #define rx_x2_status0_refClkSelect_clk_312p5Mhz 2 3937 3938 /**************************************************************************** 3939 * Enums: rx_x2_status0_aerMMDdevTypeSelect 3940 */ 3941 #define rx_x2_status0_aerMMDdevTypeSelect_combo_core 0 3942 #define rx_x2_status0_aerMMDdevTypeSelect_PMA_PMD 1 3943 #define rx_x2_status0_aerMMDdevTypeSelect_PCS 3 3944 #define rx_x2_status0_aerMMDdevTypeSelect_PHY 4 3945 #define rx_x2_status0_aerMMDdevTypeSelect_DTE 5 3946 #define rx_x2_status0_aerMMDdevTypeSelect_CL73_AN 7 3947 3948 /**************************************************************************** 3949 * Enums: rx_x2_status0_aerMMDportSelect 3950 */ 3951 #define rx_x2_status0_aerMMDportSelect_ln0 0 3952 #define rx_x2_status0_aerMMDportSelect_ln1 1 3953 #define rx_x2_status0_aerMMDportSelect_ln2 2 3954 #define rx_x2_status0_aerMMDportSelect_ln3 3 3955 #define rx_x2_status0_aerMMDportSelect_BCST_ln0_1_2_3 511 3956 #define rx_x2_status0_aerMMDportSelect_BCST_ln0_1 512 3957 #define rx_x2_status0_aerMMDportSelect_BCST_ln2_3 513 3958 3959 /**************************************************************************** 3960 * Enums: rx_x2_status0_firmwareModeSelect 3961 */ 3962 #define rx_x2_status0_firmwareModeSelect_DEFAULT 0 3963 #define rx_x2_status0_firmwareModeSelect_SFP_OPT_LR 1 3964 #define rx_x2_status0_firmwareModeSelect_SFP_DAC 2 3965 #define rx_x2_status0_firmwareModeSelect_XLAUI 3 3966 #define rx_x2_status0_firmwareModeSelect_LONG_CH_6G 4 3967 3968 /**************************************************************************** 3969 * Enums: rx_x2_status0_tempIdxSelect 3970 */ 3971 #define rx_x2_status0_tempIdxSelect_LTE__22p9C 15 3972 #define rx_x2_status0_tempIdxSelect_LTE__12p6C 14 3973 #define rx_x2_status0_tempIdxSelect_LTE__3p0C 13 3974 #define rx_x2_status0_tempIdxSelect_LTE_6p7C 12 3975 #define rx_x2_status0_tempIdxSelect_LTE_16p4C 11 3976 #define rx_x2_status0_tempIdxSelect_LTE_26p6C 10 3977 #define rx_x2_status0_tempIdxSelect_LTE_36p3C 9 3978 #define rx_x2_status0_tempIdxSelect_LTE_46p0C 8 3979 #define rx_x2_status0_tempIdxSelect_LTE_56p2C 7 3980 #define rx_x2_status0_tempIdxSelect_LTE_65p9C 6 3981 #define rx_x2_status0_tempIdxSelect_LTE_75p6C 5 3982 #define rx_x2_status0_tempIdxSelect_LTE_85p3C 4 3983 #define rx_x2_status0_tempIdxSelect_LTE_95p5C 3 3984 #define rx_x2_status0_tempIdxSelect_LTE_105p2C 2 3985 #define rx_x2_status0_tempIdxSelect_LTE_114p9C 1 3986 #define rx_x2_status0_tempIdxSelect_LTE_125p1C 0 3987 3988 /**************************************************************************** 3989 * Enums: rx_x2_status0_port_mode 3990 */ 3991 #define rx_x2_status0_port_mode_QUAD_PORT 0 3992 #define rx_x2_status0_port_mode_TRI_1_PORT 1 3993 #define rx_x2_status0_port_mode_TRI_2_PORT 2 3994 #define rx_x2_status0_port_mode_DUAL_PORT 3 3995 #define rx_x2_status0_port_mode_SINGLE_PORT 4 3996 #define rx_x2_status0_port_mode_SINGLE_OCTAL_PORT 5 3997 3998 /**************************************************************************** 3999 * Enums: rx_x2_status0_rev_letter_enum 4000 */ 4001 #define rx_x2_status0_rev_letter_enum_REV_A 0 4002 #define rx_x2_status0_rev_letter_enum_REV_B 1 4003 #define rx_x2_status0_rev_letter_enum_REV_C 2 4004 #define rx_x2_status0_rev_letter_enum_REV_D 3 4005 4006 /**************************************************************************** 4007 * Enums: rx_x2_status0_rev_number_enum 4008 */ 4009 #define rx_x2_status0_rev_number_enum_REV_0 0 4010 #define rx_x2_status0_rev_number_enum_REV_1 1 4011 #define rx_x2_status0_rev_number_enum_REV_2 2 4012 #define rx_x2_status0_rev_number_enum_REV_3 3 4013 #define rx_x2_status0_rev_number_enum_REV_4 4 4014 #define rx_x2_status0_rev_number_enum_REV_5 5 4015 #define rx_x2_status0_rev_number_enum_REV_6 6 4016 #define rx_x2_status0_rev_number_enum_REV_7 7 4017 4018 /**************************************************************************** 4019 * Enums: rx_x2_status0_bonding_enum 4020 */ 4021 #define rx_x2_status0_bonding_enum_WIRE_BOND 0 4022 #define rx_x2_status0_bonding_enum_FLIP_CHIP 1 4023 4024 /**************************************************************************** 4025 * Enums: rx_x2_status0_tech_process 4026 */ 4027 #define rx_x2_status0_tech_process_PROCESS_90NM 0 4028 #define rx_x2_status0_tech_process_PROCESS_65NM 1 4029 #define rx_x2_status0_tech_process_PROCESS_40NM 2 4030 #define rx_x2_status0_tech_process_PROCESS_28NM 3 4031 #define rx_x2_status0_tech_process_PROCESS_16NM 4 4032 4033 /**************************************************************************** 4034 * Enums: rx_x2_status0_model_num 4035 */ 4036 #define rx_x2_status0_model_num_SERDES_CL73 0 4037 #define rx_x2_status0_model_num_XGXS_16G 1 4038 #define rx_x2_status0_model_num_HYPERCORE 2 4039 #define rx_x2_status0_model_num_HYPERLITE 3 4040 #define rx_x2_status0_model_num_PCIE_G2_PIPE 4 4041 #define rx_x2_status0_model_num_SERDES_1p25GBd 5 4042 #define rx_x2_status0_model_num_SATA2 6 4043 #define rx_x2_status0_model_num_QSGMII 7 4044 #define rx_x2_status0_model_num_XGXS10G 8 4045 #define rx_x2_status0_model_num_WARPCORE 9 4046 #define rx_x2_status0_model_num_XFICORE 10 4047 #define rx_x2_status0_model_num_RXFI 11 4048 #define rx_x2_status0_model_num_WARPLITE 12 4049 #define rx_x2_status0_model_num_PENTACORE 13 4050 #define rx_x2_status0_model_num_ESM 14 4051 #define rx_x2_status0_model_num_QUAD_SGMII 15 4052 #define rx_x2_status0_model_num_WARPCORE_3 16 4053 #define rx_x2_status0_model_num_TSC 17 4054 #define rx_x2_status0_model_num_TSC4E 18 4055 #define rx_x2_status0_model_num_TSC12E 19 4056 #define rx_x2_status0_model_num_TSC4F 20 4057 #define rx_x2_status0_model_num_TSC4F_GEN2 21 4058 #define rx_x2_status0_model_num_XGXS_CL73_90NM 29 4059 #define rx_x2_status0_model_num_SERDES_CL73_90NM 30 4060 #define rx_x2_status0_model_num_WARPCORE3 32 4061 #define rx_x2_status0_model_num_WARPCORE4_TSC 33 4062 #define rx_x2_status0_model_num_RXAUI 34 4063 #define rx_x2_status0_model_num_TSCE_GEN3 35 4064 #define rx_x2_status0_model_num_TSC4F_GEN3 36 4065 #define rx_x2_status0_model_num_TSCBH 37 4066 4067 /**************************************************************************** 4068 * Enums: rx_x2_status0_payload 4069 */ 4070 #define rx_x2_status0_payload_REPEAT_2_BYTES 0 4071 #define rx_x2_status0_payload_RAMPING 1 4072 #define rx_x2_status0_payload_CL48_CRPAT 2 4073 #define rx_x2_status0_payload_CL48_CJPAT 3 4074 #define rx_x2_status0_payload_CL36_LONG_CRPAT 4 4075 #define rx_x2_status0_payload_CL36_SHORT_CRPAT 5 4076 4077 /**************************************************************************** 4078 * Enums: rx_x2_status0_sc 4079 */ 4080 #define rx_x2_status0_sc_SPEED_10G_IEEE_KR1 0 4081 #define rx_x2_status0_sc_SPEED_25G_IEEE_KS1_CS1 1 4082 #define rx_x2_status0_sc_SPEED_25G_IEEE_KR1_CR1 2 4083 #define rx_x2_status0_sc_SPEED_40G_IEEE_KR4 3 4084 #define rx_x2_status0_sc_SPEED_40G_IEEE_CR4 4 4085 #define rx_x2_status0_sc_SPEED_50G_IEEE_KR1_CR1 5 4086 #define rx_x2_status0_sc_SPEED_100G_IEEE_KR4 6 4087 #define rx_x2_status0_sc_SPEED_100G_IEEE_CR4 7 4088 #define rx_x2_status0_sc_SPEED_100G_IEEE_KR2_CR2 8 4089 #define rx_x2_status0_sc_SPEED_200G_IEEE_KR4_CR4 9 4090 #define rx_x2_status0_sc_SPEED_400G_IEEE_X8 10 4091 #define rx_x2_status0_sc_SPEED_CL73_IEEE_20GVCO 11 4092 #define rx_x2_status0_sc_SPEED_CL73_IEEE_25GVCO 12 4093 #define rx_x2_status0_sc_SPEED_CL73_IEEE_26GVCO 13 4094 #define rx_x2_status0_sc_SPEED_20G_BRCM_CR1 14 4095 #define rx_x2_status0_sc_SPEED_20G_BRCM_KR1 15 4096 #define rx_x2_status0_sc_SPEED_25G_BRCM_CR1 16 4097 #define rx_x2_status0_sc_SPEED_25G_BRCM_KR1 17 4098 #define rx_x2_status0_sc_SPEED_40G_BRCM_CR2 18 4099 #define rx_x2_status0_sc_SPEED_40G_BRCM_KR2 19 4100 #define rx_x2_status0_sc_SPEED_50G_BRCM_CR2 20 4101 #define rx_x2_status0_sc_SPEED_50G_BRCM_KR2 21 4102 #define rx_x2_status0_sc_SPEED_50G_BRCM_CR4 22 4103 #define rx_x2_status0_sc_SPEED_50G_BRCM_KR4 23 4104 #define rx_x2_status0_sc_SPEED_50G_BRCM_FEC_544_CR2_KR2 24 4105 #define rx_x2_status0_sc_SPEED_RESERVED_19 25 4106 #define rx_x2_status0_sc_SPEED_50G_BRCM_FEC_544_CR1_KR1 26 4107 #define rx_x2_status0_sc_SPEED_50G_BRCM_NO_FEC_CR1_KR1 27 4108 #define rx_x2_status0_sc_SPEED_50G_BRCM_FEC_528_CR1_KR1 28 4109 #define rx_x2_status0_sc_SPEED_400G_BRCM_NO_FEC_KR8_CR8 29 4110 #define rx_x2_status0_sc_SPEED_400G_BRCM_FEC_KR8_CR8 30 4111 #define rx_x2_status0_sc_SPEED_200G_BRCM_NO_FEC_KR4_CR4 31 4112 #define rx_x2_status0_sc_SPEED_200G_BRCM_KR4_CR4 32 4113 #define rx_x2_status0_sc_SPEED_100G_BRCM_KR4_CR4 33 4114 #define rx_x2_status0_sc_SPEED_RESERVED_22 34 4115 #define rx_x2_status0_sc_SPEED_100G_BRCM_FEC_528_KR2_CR2 35 4116 #define rx_x2_status0_sc_SPEED_100G_BRCM_NO_FEC_KR2_CR2 36 4117 #define rx_x2_status0_sc_SPEED_100G_BRCM_NO_FEC_X4 37 4118 4119 /**************************************************************************** 4120 * Enums: rx_x2_status0_t_fifo_modes 4121 */ 4122 #define rx_x2_status0_t_fifo_modes_T_FIFO_INSERT_NO_AM 0 4123 #define rx_x2_status0_t_fifo_modes_T_FIFO_INSERT_4_AM 1 4124 #define rx_x2_status0_t_fifo_modes_T_FIFO_INSERT_20_AM 2 4125 #define rx_x2_status0_t_fifo_modes_T_FIFO_INSERT_2_AM 3 4126 4127 /**************************************************************************** 4128 * Enums: rx_x2_status0_t_enc_modes 4129 */ 4130 #define rx_x2_status0_t_enc_modes_T_ENC_MODE_BYPASS 0 4131 #define rx_x2_status0_t_enc_modes_T_ENC_MODE_CL49 1 4132 #define rx_x2_status0_t_enc_modes_T_ENC_MODE_CL82 2 4133 4134 /**************************************************************************** 4135 * Enums: rx_x2_status0_btmx_mode 4136 */ 4137 #define rx_x2_status0_btmx_mode_BS_BTMX_MODE_1to1 0 4138 #define rx_x2_status0_btmx_mode_BS_BTMX_MODE_2to1 1 4139 #define rx_x2_status0_btmx_mode_BS_BTMX_MODE_5to1 2 4140 4141 /**************************************************************************** 4142 * Enums: rx_x2_status0_t_type_cl82 4143 */ 4144 #define rx_x2_status0_t_type_cl82_T_TYPE_B1 5 4145 #define rx_x2_status0_t_type_cl82_T_TYPE_C 4 4146 #define rx_x2_status0_t_type_cl82_T_TYPE_S 3 4147 #define rx_x2_status0_t_type_cl82_T_TYPE_T 2 4148 #define rx_x2_status0_t_type_cl82_T_TYPE_D 1 4149 #define rx_x2_status0_t_type_cl82_T_TYPE_E 0 4150 4151 /**************************************************************************** 4152 * Enums: rx_x2_status0_txsm_state_cl82 4153 */ 4154 #define rx_x2_status0_txsm_state_cl82_TX_E 4 4155 #define rx_x2_status0_txsm_state_cl82_TX_T 3 4156 #define rx_x2_status0_txsm_state_cl82_TX_D 2 4157 #define rx_x2_status0_txsm_state_cl82_TX_C 1 4158 #define rx_x2_status0_txsm_state_cl82_TX_INIT 0 4159 4160 /**************************************************************************** 4161 * Enums: rx_x2_status0_ltxsm_state_cl82 4162 */ 4163 #define rx_x2_status0_ltxsm_state_cl82_TX_E 16 4164 #define rx_x2_status0_ltxsm_state_cl82_TX_T 8 4165 #define rx_x2_status0_ltxsm_state_cl82_TX_D 4 4166 #define rx_x2_status0_ltxsm_state_cl82_TX_C 2 4167 #define rx_x2_status0_ltxsm_state_cl82_TX_INIT 1 4168 4169 /**************************************************************************** 4170 * Enums: rx_x2_status0_r_type_coded_cl82 4171 */ 4172 #define rx_x2_status0_r_type_coded_cl82_R_TYPE_B1 32 4173 #define rx_x2_status0_r_type_coded_cl82_R_TYPE_C 16 4174 #define rx_x2_status0_r_type_coded_cl82_R_TYPE_S 8 4175 #define rx_x2_status0_r_type_coded_cl82_R_TYPE_T 4 4176 #define rx_x2_status0_r_type_coded_cl82_R_TYPE_D 2 4177 #define rx_x2_status0_r_type_coded_cl82_R_TYPE_E 1 4178 4179 /**************************************************************************** 4180 * Enums: rx_x2_status0_rxsm_state_cl82 4181 */ 4182 #define rx_x2_status0_rxsm_state_cl82_RX_E 16 4183 #define rx_x2_status0_rxsm_state_cl82_RX_T 8 4184 #define rx_x2_status0_rxsm_state_cl82_RX_D 4 4185 #define rx_x2_status0_rxsm_state_cl82_RX_C 2 4186 #define rx_x2_status0_rxsm_state_cl82_RX_INIT 1 4187 4188 /**************************************************************************** 4189 * Enums: rx_x2_status0_deskew_state 4190 */ 4191 #define rx_x2_status0_deskew_state_ALIGN_ACQUIRED 2 4192 #define rx_x2_status0_deskew_state_LOSS_OF_ALIGNMENT 1 4193 4194 /**************************************************************************** 4195 * Enums: rx_x2_status0_os_mode_enum 4196 */ 4197 #define rx_x2_status0_os_mode_enum_OS_MODE_1 0 4198 #define rx_x2_status0_os_mode_enum_OS_MODE_2 1 4199 #define rx_x2_status0_os_mode_enum_OS_MODE_4 2 4200 #define rx_x2_status0_os_mode_enum_OS_MODE_16p5 8 4201 #define rx_x2_status0_os_mode_enum_OS_MODE_20p625 12 4202 4203 /**************************************************************************** 4204 * Enums: rx_x2_status0_scr_modes 4205 */ 4206 #define rx_x2_status0_scr_modes_T_SCR_MODE_BYPASS 0 4207 #define rx_x2_status0_scr_modes_T_SCR_MODE_CL49 1 4208 #define rx_x2_status0_scr_modes_T_SCR_MODE_40G_2_LANE 2 4209 #define rx_x2_status0_scr_modes_T_SCR_MODE_100G 3 4210 #define rx_x2_status0_scr_modes_T_SCR_MODE_20G 4 4211 #define rx_x2_status0_scr_modes_T_SCR_MODE_40G_4_LANE 5 4212 4213 /**************************************************************************** 4214 * Enums: rx_x2_status0_descr_modes 4215 */ 4216 #define rx_x2_status0_descr_modes_R_DESCR_MODE_BYPASS 0 4217 #define rx_x2_status0_descr_modes_R_DESCR_MODE_CL49 1 4218 #define rx_x2_status0_descr_modes_R_DESCR_MODE_CL82 2 4219 4220 /**************************************************************************** 4221 * Enums: rx_x2_status0_r_dec_tl_mode 4222 */ 4223 #define rx_x2_status0_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 4224 #define rx_x2_status0_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 4225 #define rx_x2_status0_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 4226 4227 /**************************************************************************** 4228 * Enums: rx_x2_status0_r_dec_fsm_mode 4229 */ 4230 #define rx_x2_status0_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 4231 #define rx_x2_status0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 4232 #define rx_x2_status0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 4233 4234 /**************************************************************************** 4235 * Enums: rx_x2_status0_r_deskew_mode 4236 */ 4237 #define rx_x2_status0_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 4238 #define rx_x2_status0_r_deskew_mode_R_DESKEW_MODE_20G 1 4239 #define rx_x2_status0_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 4240 #define rx_x2_status0_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 4241 #define rx_x2_status0_r_deskew_mode_R_DESKEW_MODE_100G 4 4242 #define rx_x2_status0_r_deskew_mode_R_DESKEW_MODE_CL49 5 4243 #define rx_x2_status0_r_deskew_mode_R_DESKEW_MODE_CL91_QUAD 6 4244 #define rx_x2_status0_r_deskew_mode_R_DESKEW_MODE_CL91_SINGLE_BRCM 7 4245 #define rx_x2_status0_r_deskew_mode_R_DESKEW_MODE_CL91_DUAL_BRCM 8 4246 #define rx_x2_status0_r_deskew_mode_R_DESKEW_MODE_CL91_FC 9 4247 4248 /**************************************************************************** 4249 * Enums: rx_x2_status0_bs_dist_modes 4250 */ 4251 #define rx_x2_status0_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 4252 #define rx_x2_status0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 4253 #define rx_x2_status0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 4254 #define rx_x2_status0_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 4255 4256 /**************************************************************************** 4257 * Enums: rx_x2_status0_cl49_t_type 4258 */ 4259 #define rx_x2_status0_cl49_t_type_BAD_T_TYPE 15 4260 #define rx_x2_status0_cl49_t_type_T_TYPE_B0 11 4261 #define rx_x2_status0_cl49_t_type_T_TYPE_OB 10 4262 #define rx_x2_status0_cl49_t_type_T_TYPE_B1 9 4263 #define rx_x2_status0_cl49_t_type_T_TYPE_DB 8 4264 #define rx_x2_status0_cl49_t_type_T_TYPE_FC 7 4265 #define rx_x2_status0_cl49_t_type_T_TYPE_TB 6 4266 #define rx_x2_status0_cl49_t_type_T_TYPE_LI 5 4267 #define rx_x2_status0_cl49_t_type_T_TYPE_C 4 4268 #define rx_x2_status0_cl49_t_type_T_TYPE_S 3 4269 #define rx_x2_status0_cl49_t_type_T_TYPE_T 2 4270 #define rx_x2_status0_cl49_t_type_T_TYPE_D 1 4271 #define rx_x2_status0_cl49_t_type_T_TYPE_E 0 4272 4273 /**************************************************************************** 4274 * Enums: rx_x2_status0_cl49_txsm_states 4275 */ 4276 #define rx_x2_status0_cl49_txsm_states_TX_LI 5 4277 #define rx_x2_status0_cl49_txsm_states_TX_E 4 4278 #define rx_x2_status0_cl49_txsm_states_TX_T 3 4279 #define rx_x2_status0_cl49_txsm_states_TX_D 2 4280 #define rx_x2_status0_cl49_txsm_states_TX_C 1 4281 #define rx_x2_status0_cl49_txsm_states_TX_INIT 0 4282 4283 /**************************************************************************** 4284 * Enums: rx_x2_status0_cl49_ltxsm_states 4285 */ 4286 #define rx_x2_status0_cl49_ltxsm_states_TX_LI 32 4287 #define rx_x2_status0_cl49_ltxsm_states_TX_E 16 4288 #define rx_x2_status0_cl49_ltxsm_states_TX_T 8 4289 #define rx_x2_status0_cl49_ltxsm_states_TX_D 4 4290 #define rx_x2_status0_cl49_ltxsm_states_TX_C 2 4291 #define rx_x2_status0_cl49_ltxsm_states_TX_INIT 1 4292 4293 /**************************************************************************** 4294 * Enums: rx_x2_status0_burst_error_mode 4295 */ 4296 #define rx_x2_status0_burst_error_mode_BURST_ERROR_11_BITS 0 4297 #define rx_x2_status0_burst_error_mode_BURST_ERROR_16_BITS 1 4298 #define rx_x2_status0_burst_error_mode_BURST_ERROR_17_BITS 2 4299 #define rx_x2_status0_burst_error_mode_BURST_ERROR_18_BITS 3 4300 #define rx_x2_status0_burst_error_mode_BURST_ERROR_19_BITS 4 4301 #define rx_x2_status0_burst_error_mode_BURST_ERROR_20_BITS 5 4302 #define rx_x2_status0_burst_error_mode_BURST_ERROR_21_BITS 6 4303 #define rx_x2_status0_burst_error_mode_BURST_ERROR_22_BITS 7 4304 #define rx_x2_status0_burst_error_mode_BURST_ERROR_23_BITS 8 4305 #define rx_x2_status0_burst_error_mode_BURST_ERROR_24_BITS 9 4306 #define rx_x2_status0_burst_error_mode_BURST_ERROR_25_BITS 10 4307 #define rx_x2_status0_burst_error_mode_BURST_ERROR_26_BITS 11 4308 #define rx_x2_status0_burst_error_mode_BURST_ERROR_27_BITS 12 4309 #define rx_x2_status0_burst_error_mode_BURST_ERROR_28_BITS 13 4310 #define rx_x2_status0_burst_error_mode_BURST_ERROR_29_BITS 14 4311 #define rx_x2_status0_burst_error_mode_BURST_ERROR_30_BITS 15 4312 #define rx_x2_status0_burst_error_mode_BURST_ERROR_31_BITS 16 4313 #define rx_x2_status0_burst_error_mode_BURST_ERROR_32_BITS 17 4314 #define rx_x2_status0_burst_error_mode_BURST_ERROR_33_BITS 18 4315 #define rx_x2_status0_burst_error_mode_BURST_ERROR_34_BITS 19 4316 #define rx_x2_status0_burst_error_mode_BURST_ERROR_35_BITS 20 4317 #define rx_x2_status0_burst_error_mode_BURST_ERROR_36_BITS 21 4318 #define rx_x2_status0_burst_error_mode_BURST_ERROR_37_BITS 22 4319 #define rx_x2_status0_burst_error_mode_BURST_ERROR_38_BITS 23 4320 #define rx_x2_status0_burst_error_mode_BURST_ERROR_39_BITS 24 4321 #define rx_x2_status0_burst_error_mode_BURST_ERROR_40_BITS 25 4322 #define rx_x2_status0_burst_error_mode_BURST_ERROR_41_BITS 26 4323 4324 /**************************************************************************** 4325 * Enums: rx_x2_status0_bermon_state 4326 */ 4327 #define rx_x2_status0_bermon_state_HI_BER 4 4328 #define rx_x2_status0_bermon_state_GOOD_BER 3 4329 #define rx_x2_status0_bermon_state_BER_TEST_SH 2 4330 #define rx_x2_status0_bermon_state_START_TIMER 1 4331 #define rx_x2_status0_bermon_state_BER_MT_INIT 0 4332 4333 /**************************************************************************** 4334 * Enums: rx_x2_status0_rxsm_state_cl49 4335 */ 4336 #define rx_x2_status0_rxsm_state_cl49_RX_LI 32 4337 #define rx_x2_status0_rxsm_state_cl49_RX_E 16 4338 #define rx_x2_status0_rxsm_state_cl49_RX_T 8 4339 #define rx_x2_status0_rxsm_state_cl49_RX_D 4 4340 #define rx_x2_status0_rxsm_state_cl49_RX_C 2 4341 #define rx_x2_status0_rxsm_state_cl49_RX_INIT 1 4342 4343 /**************************************************************************** 4344 * Enums: rx_x2_status0_r_type 4345 */ 4346 #define rx_x2_status0_r_type_BAD_R_TYPE 15 4347 #define rx_x2_status0_r_type_R_TYPE_B0 11 4348 #define rx_x2_status0_r_type_R_TYPE_OB 10 4349 #define rx_x2_status0_r_type_R_TYPE_B1 9 4350 #define rx_x2_status0_r_type_R_TYPE_DB 8 4351 #define rx_x2_status0_r_type_R_TYPE_FC 7 4352 #define rx_x2_status0_r_type_R_TYPE_TB 6 4353 #define rx_x2_status0_r_type_R_TYPE_LI 5 4354 #define rx_x2_status0_r_type_R_TYPE_C 4 4355 #define rx_x2_status0_r_type_R_TYPE_S 3 4356 #define rx_x2_status0_r_type_R_TYPE_T 2 4357 #define rx_x2_status0_r_type_R_TYPE_D 1 4358 #define rx_x2_status0_r_type_R_TYPE_E 0 4359 4360 /**************************************************************************** 4361 * Enums: rx_x2_status0_am_lock_state 4362 */ 4363 #define rx_x2_status0_am_lock_state_INVALID_AM 512 4364 #define rx_x2_status0_am_lock_state_GOOD_AM 256 4365 #define rx_x2_status0_am_lock_state_COMP_AM 128 4366 #define rx_x2_status0_am_lock_state_TIMER_2 64 4367 #define rx_x2_status0_am_lock_state_AM_2_GOOD 32 4368 #define rx_x2_status0_am_lock_state_COMP_2ND 16 4369 #define rx_x2_status0_am_lock_state_TIMER_1 8 4370 #define rx_x2_status0_am_lock_state_FIND_1ST 4 4371 #define rx_x2_status0_am_lock_state_AM_RESET_CNT 2 4372 #define rx_x2_status0_am_lock_state_AM_LOCK_INIT 1 4373 4374 /**************************************************************************** 4375 * Enums: rx_x2_status0_msg_selector 4376 */ 4377 #define rx_x2_status0_msg_selector_RESERVED 0 4378 #define rx_x2_status0_msg_selector_VALUE_802p3 1 4379 #define rx_x2_status0_msg_selector_VALUE_802p9 2 4380 #define rx_x2_status0_msg_selector_VALUE_802p5 3 4381 #define rx_x2_status0_msg_selector_VALUE_1394 4 4382 4383 /**************************************************************************** 4384 * Enums: rx_x2_status0_synce_enum_stage1 4385 */ 4386 #define rx_x2_status0_synce_enum_stage1_SYNCE_NO_DIV 0 4387 #define rx_x2_status0_synce_enum_stage1_SYNCE_DIV_7 1 4388 #define rx_x2_status0_synce_enum_stage1_SYNCE_DIV_11 2 4389 4390 /**************************************************************************** 4391 * Enums: rx_x2_status0_synce_enum_stage0 4392 */ 4393 #define rx_x2_status0_synce_enum_stage0_SYNCE_NO_DIV 0 4394 #define rx_x2_status0_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 4395 #define rx_x2_status0_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 4396 4397 /**************************************************************************** 4398 * Enums: rx_x2_status0_cl91_sync_state 4399 */ 4400 #define rx_x2_status0_cl91_sync_state_FIND_1ST 0 4401 #define rx_x2_status0_cl91_sync_state_COUNT_NEXT 1 4402 #define rx_x2_status0_cl91_sync_state_COMP_2ND 2 4403 #define rx_x2_status0_cl91_sync_state_TWO_GOOD 3 4404 4405 /**************************************************************************** 4406 * Enums: rx_x2_status0_RS_FEC_sync_state 4407 */ 4408 #define rx_x2_status0_RS_FEC_sync_state_LOCK_INIT 0 4409 #define rx_x2_status0_RS_FEC_sync_state_FIND_1ST 1 4410 #define rx_x2_status0_RS_FEC_sync_state_COUNT_NEXT 2 4411 #define rx_x2_status0_RS_FEC_sync_state_COMP_2ND 3 4412 #define rx_x2_status0_RS_FEC_sync_state_TWO_GOOD 4 4413 4414 /**************************************************************************** 4415 * Enums: rx_x2_status0_cl91_algn_state 4416 */ 4417 #define rx_x2_status0_cl91_algn_state_LOSS_OF_ALIGNMENT 0 4418 #define rx_x2_status0_cl91_algn_state_DESKEW 1 4419 #define rx_x2_status0_cl91_algn_state_DESKEW_FAIL 2 4420 #define rx_x2_status0_cl91_algn_state_ALIGN_ACQUIRED 3 4421 #define rx_x2_status0_cl91_algn_state_CW_GOOD 4 4422 #define rx_x2_status0_cl91_algn_state_CW_BAD 5 4423 #define rx_x2_status0_cl91_algn_state_THREE_BAD 6 4424 4425 /**************************************************************************** 4426 * Enums: rx_x2_status0_RS_FEC_algn_state 4427 */ 4428 #define rx_x2_status0_RS_FEC_algn_state_LOSS_OF_ALIGNMENT 0 4429 #define rx_x2_status0_RS_FEC_algn_state_DESKEW 1 4430 #define rx_x2_status0_RS_FEC_algn_state_DESKEW_FAIL 2 4431 #define rx_x2_status0_RS_FEC_algn_state_ALIGN_ACQUIRED 3 4432 #define rx_x2_status0_RS_FEC_algn_state_CW_GOOD 4 4433 #define rx_x2_status0_RS_FEC_algn_state_CW_BAD 5 4434 #define rx_x2_status0_RS_FEC_algn_state_THREE_BAD 6 4435 4436 /**************************************************************************** 4437 * Enums: rx_x2_status0_fec_sel_override 4438 */ 4439 #define rx_x2_status0_fec_sel_override_NO_OVERRIDE 0 4440 #define rx_x2_status0_fec_sel_override_NO_FEC 1 4441 #define rx_x2_status0_fec_sel_override_FEC_CL74 2 4442 #define rx_x2_status0_fec_sel_override_FEC_CL91 3 4443 4444 /**************************************************************************** 4445 * Enums: rx_x2_status0_cl91_blksync_mode 4446 */ 4447 #define rx_x2_status0_cl91_blksync_mode_R_BLKSYNC_NO_CL91_FEC 0 4448 #define rx_x2_status0_cl91_blksync_mode_R_BLKSYNC_CL91_QUAD_LANE_FEC 1 4449 #define rx_x2_status0_cl91_blksync_mode_R_BLKSYNC_CL91_DUAL_LANE_FEC 2 4450 #define rx_x2_status0_cl91_blksync_mode_R_BLKSYNC_CL91_SINGLE_LANE_FEC 3 4451 #define rx_x2_status0_cl91_blksync_mode_R_BLKSYNC_CL91_FC_FEC 4 4452 4453 /**************************************************************************** 4454 * Enums: rx_x2_status0_r_merge_mode 4455 */ 4456 #define rx_x2_status0_r_merge_mode_R_MERGE_MODE_BYPASS 0 4457 #define rx_x2_status0_r_merge_mode_R_MERGE_MODE_CL91_FC 1 4458 #define rx_x2_status0_r_merge_mode_R_MERGE_MODE_CL91_SINGLE_LANE 2 4459 #define rx_x2_status0_r_merge_mode_R_MERGE_MODE_CL91_DUAL_LANE 3 4460 #define rx_x2_status0_r_merge_mode_R_MERGE_MODE_CL91_QUAD_LANE 4 4461 4462 /**************************************************************************** 4463 * Enums: rx_x2_status0_r_tc_mode 4464 */ 4465 #define rx_x2_status0_r_tc_mode_R_TC_MODE_SINGLE 0 4466 #define rx_x2_status0_r_tc_mode_R_TC_MODE_DUAL 1 4467 #define rx_x2_status0_r_tc_mode_R_TC_MODE_QUAD 2 4468 4469 /**************************************************************************** 4470 * Enums: rx_x2_status0_r_tc_out_mode 4471 */ 4472 #define rx_x2_status0_r_tc_out_mode_R_TC_OUT_MODE_SINGLE 0 4473 #define rx_x2_status0_r_tc_out_mode_R_TC_OUT_MODE_DUAL 1 4474 #define rx_x2_status0_r_tc_out_mode_R_TC_OUT_MODE_QUAD 2 4475 4476 /**************************************************************************** 4477 * Enums: rx_x2_status0_cl91_fec_mode 4478 */ 4479 #define rx_x2_status0_cl91_fec_mode_NO_CL91_FEC 0 4480 #define rx_x2_status0_cl91_fec_mode_CL91_SINGLE_LANE_FC 1 4481 #define rx_x2_status0_cl91_fec_mode_CL91_SINGLE_LANE_BRCM_PROP 2 4482 #define rx_x2_status0_cl91_fec_mode_CL91_DUAL_LANE_BRCM_PROP 3 4483 #define rx_x2_status0_cl91_fec_mode_CL91_QUAD_LANE 4 4484 #define rx_x2_status0_cl91_fec_mode_IEEE_25G_CL91_SINGLE_LANE 5 4485 4486 /**************************************************************************** 4487 * Enums: rx_x2_status0_RS_FEC_fec_mode 4488 */ 4489 #define rx_x2_status0_RS_FEC_fec_mode_NO_RS_FEC_FEC 0 4490 #define rx_x2_status0_RS_FEC_fec_mode_N_A 1 4491 #define rx_x2_status0_RS_FEC_fec_mode_RS_FEC_SINGLE_LANE_BRCM_PROP 2 4492 #define rx_x2_status0_RS_FEC_fec_mode_RS_FEC_DUAL_LANE_BRCM_PROP 3 4493 #define rx_x2_status0_RS_FEC_fec_mode_RS_FEC_QUAD_LANE 4 4494 #define rx_x2_status0_RS_FEC_fec_mode_IEEE_25G_RS_FEC_SINGLE_LANE 5 4495 4496 /**************************************************************************** 4497 * Enums: rx_x2_status0_am_spacing_mul 4498 */ 4499 #define rx_x2_status0_am_spacing_mul_AM_SPACING_MUL_2 0 4500 #define rx_x2_status0_am_spacing_mul_AM_SPACING_MUL_4 1 4501 #define rx_x2_status0_am_spacing_mul_AM_SPACING_MUL_5 2 4502 #define rx_x2_status0_am_spacing_mul_AM_SPACING_MUL_20 3 4503 4504 /**************************************************************************** 4505 * Enums: rx_x4_control0_cl36TxEEEStates_l 4506 */ 4507 #define rx_x4_control0_cl36TxEEEStates_l_TX_REFRESH 8 4508 #define rx_x4_control0_cl36TxEEEStates_l_TX_QUIET 4 4509 #define rx_x4_control0_cl36TxEEEStates_l_TX_SLEEP 2 4510 #define rx_x4_control0_cl36TxEEEStates_l_TX_ACTIVE 1 4511 4512 /**************************************************************************** 4513 * Enums: rx_x4_control0_cl36TxEEEStates_c 4514 */ 4515 #define rx_x4_control0_cl36TxEEEStates_c_TX_REFRESH 3 4516 #define rx_x4_control0_cl36TxEEEStates_c_TX_QUIET 2 4517 #define rx_x4_control0_cl36TxEEEStates_c_TX_SLEEP 1 4518 #define rx_x4_control0_cl36TxEEEStates_c_TX_ACTIVE 0 4519 4520 /**************************************************************************** 4521 * Enums: rx_x4_control0_cl49TxEEEStates_l 4522 */ 4523 #define rx_x4_control0_cl49TxEEEStates_l_SCR_RESET_2 64 4524 #define rx_x4_control0_cl49TxEEEStates_l_SCR_RESET_1 32 4525 #define rx_x4_control0_cl49TxEEEStates_l_TX_WAKE 16 4526 #define rx_x4_control0_cl49TxEEEStates_l_TX_REFRESH 8 4527 #define rx_x4_control0_cl49TxEEEStates_l_TX_QUIET 4 4528 #define rx_x4_control0_cl49TxEEEStates_l_TX_SLEEP 2 4529 #define rx_x4_control0_cl49TxEEEStates_l_TX_ACTIVE 1 4530 4531 /**************************************************************************** 4532 * Enums: rx_x4_control0_fec_req_enum 4533 */ 4534 #define rx_x4_control0_fec_req_enum_FEC_not_supported 0 4535 #define rx_x4_control0_fec_req_enum_FEC_supported_but_not_requested 1 4536 #define rx_x4_control0_fec_req_enum_invalid_setting 2 4537 #define rx_x4_control0_fec_req_enum_FEC_supported_and_requested 3 4538 4539 /**************************************************************************** 4540 * Enums: rx_x4_control0_cl73_pause_enum 4541 */ 4542 #define rx_x4_control0_cl73_pause_enum_No_PAUSE_ability 0 4543 #define rx_x4_control0_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 4544 #define rx_x4_control0_cl73_pause_enum_Symmetric_PAUSE_ability 1 4545 #define rx_x4_control0_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 4546 4547 /**************************************************************************** 4548 * Enums: rx_x4_control0_cl49TxEEEStates_c 4549 */ 4550 #define rx_x4_control0_cl49TxEEEStates_c_SCR_RESET_2 6 4551 #define rx_x4_control0_cl49TxEEEStates_c_SCR_RESET_1 5 4552 #define rx_x4_control0_cl49TxEEEStates_c_TX_WAKE 4 4553 #define rx_x4_control0_cl49TxEEEStates_c_TX_REFRESH 3 4554 #define rx_x4_control0_cl49TxEEEStates_c_TX_QUIET 2 4555 #define rx_x4_control0_cl49TxEEEStates_c_TX_SLEEP 1 4556 #define rx_x4_control0_cl49TxEEEStates_c_TX_ACTIVE 0 4557 4558 /**************************************************************************** 4559 * Enums: rx_x4_control0_cl36RxEEEStates_l 4560 */ 4561 #define rx_x4_control0_cl36RxEEEStates_l_RX_LINK_FAIL 32 4562 #define rx_x4_control0_cl36RxEEEStates_l_RX_WTF 16 4563 #define rx_x4_control0_cl36RxEEEStates_l_RX_WAKE 8 4564 #define rx_x4_control0_cl36RxEEEStates_l_RX_QUIET 4 4565 #define rx_x4_control0_cl36RxEEEStates_l_RX_SLEEP 2 4566 #define rx_x4_control0_cl36RxEEEStates_l_RX_ACTIVE 1 4567 4568 /**************************************************************************** 4569 * Enums: rx_x4_control0_cl36RxEEEStates_c 4570 */ 4571 #define rx_x4_control0_cl36RxEEEStates_c_RX_LINK_FAIL 5 4572 #define rx_x4_control0_cl36RxEEEStates_c_RX_WTF 4 4573 #define rx_x4_control0_cl36RxEEEStates_c_RX_WAKE 3 4574 #define rx_x4_control0_cl36RxEEEStates_c_RX_QUIET 2 4575 #define rx_x4_control0_cl36RxEEEStates_c_RX_SLEEP 1 4576 #define rx_x4_control0_cl36RxEEEStates_c_RX_ACTIVE 0 4577 4578 /**************************************************************************** 4579 * Enums: rx_x4_control0_cl49RxEEEStates_l 4580 */ 4581 #define rx_x4_control0_cl49RxEEEStates_l_RX_LINK_FAIL 32 4582 #define rx_x4_control0_cl49RxEEEStates_l_RX_WTF 16 4583 #define rx_x4_control0_cl49RxEEEStates_l_RX_WAKE 8 4584 #define rx_x4_control0_cl49RxEEEStates_l_RX_QUIET 4 4585 #define rx_x4_control0_cl49RxEEEStates_l_RX_SLEEP 2 4586 #define rx_x4_control0_cl49RxEEEStates_l_RX_ACTIVE 1 4587 4588 /**************************************************************************** 4589 * Enums: rx_x4_control0_cl49RxEEEStates_c 4590 */ 4591 #define rx_x4_control0_cl49RxEEEStates_c_RX_LINK_FAIL 5 4592 #define rx_x4_control0_cl49RxEEEStates_c_RX_WTF 4 4593 #define rx_x4_control0_cl49RxEEEStates_c_RX_WAKE 3 4594 #define rx_x4_control0_cl49RxEEEStates_c_RX_QUIET 2 4595 #define rx_x4_control0_cl49RxEEEStates_c_RX_SLEEP 1 4596 #define rx_x4_control0_cl49RxEEEStates_c_RX_ACTIVE 0 4597 4598 /**************************************************************************** 4599 * Enums: rx_x4_control0_cl48TxEEEStates_l 4600 */ 4601 #define rx_x4_control0_cl48TxEEEStates_l_TX_REFRESH 8 4602 #define rx_x4_control0_cl48TxEEEStates_l_TX_QUIET 4 4603 #define rx_x4_control0_cl48TxEEEStates_l_TX_SLEEP 2 4604 #define rx_x4_control0_cl48TxEEEStates_l_TX_ACTIVE 1 4605 4606 /**************************************************************************** 4607 * Enums: rx_x4_control0_cl48TxEEEStates_c 4608 */ 4609 #define rx_x4_control0_cl48TxEEEStates_c_TX_REFRESH 3 4610 #define rx_x4_control0_cl48TxEEEStates_c_TX_QUIET 2 4611 #define rx_x4_control0_cl48TxEEEStates_c_TX_SLEEP 1 4612 #define rx_x4_control0_cl48TxEEEStates_c_TX_ACTIVE 0 4613 4614 /**************************************************************************** 4615 * Enums: rx_x4_control0_cl48RxEEEStates_l 4616 */ 4617 #define rx_x4_control0_cl48RxEEEStates_l_RX_LINK_FAIL 32 4618 #define rx_x4_control0_cl48RxEEEStates_l_RX_WAKE 16 4619 #define rx_x4_control0_cl48RxEEEStates_l_RX_QUIET 8 4620 #define rx_x4_control0_cl48RxEEEStates_l_RX_DEACT 4 4621 #define rx_x4_control0_cl48RxEEEStates_l_RX_SLEEP 2 4622 #define rx_x4_control0_cl48RxEEEStates_l_RX_ACTIVE 1 4623 4624 /**************************************************************************** 4625 * Enums: rx_x4_control0_cl48RxEEEStates_c 4626 */ 4627 #define rx_x4_control0_cl48RxEEEStates_c_RX_LINK_FAIL 5 4628 #define rx_x4_control0_cl48RxEEEStates_c_RX_WAKE 4 4629 #define rx_x4_control0_cl48RxEEEStates_c_RX_QUIET 3 4630 #define rx_x4_control0_cl48RxEEEStates_c_RX_DEACT 2 4631 #define rx_x4_control0_cl48RxEEEStates_c_RX_SLEEP 1 4632 #define rx_x4_control0_cl48RxEEEStates_c_RX_ACTIVE 0 4633 4634 /**************************************************************************** 4635 * Enums: rx_x4_control0_IQP_Options 4636 */ 4637 #define rx_x4_control0_IQP_Options_i50uA 0 4638 #define rx_x4_control0_IQP_Options_i100uA 1 4639 #define rx_x4_control0_IQP_Options_i150uA 2 4640 #define rx_x4_control0_IQP_Options_i200uA 3 4641 #define rx_x4_control0_IQP_Options_i250uA 4 4642 #define rx_x4_control0_IQP_Options_i300uA 5 4643 #define rx_x4_control0_IQP_Options_i350uA 6 4644 #define rx_x4_control0_IQP_Options_i400uA 7 4645 #define rx_x4_control0_IQP_Options_i450uA 8 4646 #define rx_x4_control0_IQP_Options_i500uA 9 4647 #define rx_x4_control0_IQP_Options_i550uA 10 4648 #define rx_x4_control0_IQP_Options_i600uA 11 4649 #define rx_x4_control0_IQP_Options_i650uA 12 4650 #define rx_x4_control0_IQP_Options_i700uA 13 4651 #define rx_x4_control0_IQP_Options_i750uA 14 4652 #define rx_x4_control0_IQP_Options_i800uA 15 4653 4654 /**************************************************************************** 4655 * Enums: rx_x4_control0_IDriver_Options 4656 */ 4657 #define rx_x4_control0_IDriver_Options_v680mV 0 4658 #define rx_x4_control0_IDriver_Options_v730mV 1 4659 #define rx_x4_control0_IDriver_Options_v780mV 2 4660 #define rx_x4_control0_IDriver_Options_v830mV 3 4661 #define rx_x4_control0_IDriver_Options_v880mV 4 4662 #define rx_x4_control0_IDriver_Options_v930mV 5 4663 #define rx_x4_control0_IDriver_Options_v980mV 6 4664 #define rx_x4_control0_IDriver_Options_v1010mV 7 4665 #define rx_x4_control0_IDriver_Options_v1040mV 8 4666 #define rx_x4_control0_IDriver_Options_v1060mV 9 4667 #define rx_x4_control0_IDriver_Options_v1070mV 10 4668 #define rx_x4_control0_IDriver_Options_v1080mV 11 4669 #define rx_x4_control0_IDriver_Options_v1085mV 12 4670 #define rx_x4_control0_IDriver_Options_v1090mV 13 4671 #define rx_x4_control0_IDriver_Options_v1095mV 14 4672 #define rx_x4_control0_IDriver_Options_v1100mV 15 4673 4674 /**************************************************************************** 4675 * Enums: rx_x4_control0_operationModes 4676 */ 4677 #define rx_x4_control0_operationModes_XGXS 0 4678 #define rx_x4_control0_operationModes_XGXG_nCC 1 4679 #define rx_x4_control0_operationModes_Indlane_OS8 4 4680 #define rx_x4_control0_operationModes_IndLane_OS5 5 4681 #define rx_x4_control0_operationModes_PCI 7 4682 #define rx_x4_control0_operationModes_XGXS_nLQ 8 4683 #define rx_x4_control0_operationModes_XGXS_nLQnCC 9 4684 #define rx_x4_control0_operationModes_PBypass 10 4685 #define rx_x4_control0_operationModes_PBypass_nDSK 11 4686 #define rx_x4_control0_operationModes_ComboCoreMode 12 4687 #define rx_x4_control0_operationModes_Clocks_off 15 4688 4689 /**************************************************************************** 4690 * Enums: rx_x4_control0_actualSpeeds 4691 */ 4692 #define rx_x4_control0_actualSpeeds_dr_10M 0 4693 #define rx_x4_control0_actualSpeeds_dr_100M 1 4694 #define rx_x4_control0_actualSpeeds_dr_1G 2 4695 #define rx_x4_control0_actualSpeeds_dr_2p5G 3 4696 #define rx_x4_control0_actualSpeeds_dr_5G_X4 4 4697 #define rx_x4_control0_actualSpeeds_dr_6G_X4 5 4698 #define rx_x4_control0_actualSpeeds_dr_10G_HiG 6 4699 #define rx_x4_control0_actualSpeeds_dr_10G_CX4 7 4700 #define rx_x4_control0_actualSpeeds_dr_12G_HiG 8 4701 #define rx_x4_control0_actualSpeeds_dr_12p5G_X4 9 4702 #define rx_x4_control0_actualSpeeds_dr_13G_X4 10 4703 #define rx_x4_control0_actualSpeeds_dr_15G_X4 11 4704 #define rx_x4_control0_actualSpeeds_dr_16G_X4 12 4705 #define rx_x4_control0_actualSpeeds_dr_1G_KX 13 4706 #define rx_x4_control0_actualSpeeds_dr_10G_KX4 14 4707 #define rx_x4_control0_actualSpeeds_dr_10G_KR 15 4708 #define rx_x4_control0_actualSpeeds_dr_5G 16 4709 #define rx_x4_control0_actualSpeeds_dr_6p4G 17 4710 #define rx_x4_control0_actualSpeeds_dr_20G_X4 18 4711 #define rx_x4_control0_actualSpeeds_dr_21G_X4 19 4712 #define rx_x4_control0_actualSpeeds_dr_25G_X4 20 4713 #define rx_x4_control0_actualSpeeds_dr_10G_HiG_DXGXS 21 4714 #define rx_x4_control0_actualSpeeds_dr_10G_DXGXS 22 4715 #define rx_x4_control0_actualSpeeds_dr_10p5G_HiG_DXGXS 23 4716 #define rx_x4_control0_actualSpeeds_dr_10p5G_DXGXS 24 4717 #define rx_x4_control0_actualSpeeds_dr_12p773G_HiG_DXGXS 25 4718 #define rx_x4_control0_actualSpeeds_dr_12p773G_DXGXS 26 4719 #define rx_x4_control0_actualSpeeds_dr_10G_XFI 27 4720 #define rx_x4_control0_actualSpeeds_dr_40G 28 4721 #define rx_x4_control0_actualSpeeds_dr_20G_HiG_DXGXS 29 4722 #define rx_x4_control0_actualSpeeds_dr_20G_DXGXS 30 4723 #define rx_x4_control0_actualSpeeds_dr_10G_SFI 31 4724 #define rx_x4_control0_actualSpeeds_dr_31p5G 32 4725 #define rx_x4_control0_actualSpeeds_dr_32p7G 33 4726 #define rx_x4_control0_actualSpeeds_dr_20G_SCR 34 4727 #define rx_x4_control0_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 4728 #define rx_x4_control0_actualSpeeds_dr_10G_DXGXS_SCR 36 4729 #define rx_x4_control0_actualSpeeds_dr_12G_R2 37 4730 #define rx_x4_control0_actualSpeeds_dr_10G_X2 38 4731 #define rx_x4_control0_actualSpeeds_dr_40G_KR4 39 4732 #define rx_x4_control0_actualSpeeds_dr_40G_CR4 40 4733 #define rx_x4_control0_actualSpeeds_dr_100G_CR10 41 4734 #define rx_x4_control0_actualSpeeds_dr_15p75G_DXGXS 44 4735 #define rx_x4_control0_actualSpeeds_dr_20G_KR2 57 4736 #define rx_x4_control0_actualSpeeds_dr_20G_CR2 58 4737 4738 /**************************************************************************** 4739 * Enums: rx_x4_control0_actualSpeedsMisc1 4740 */ 4741 #define rx_x4_control0_actualSpeedsMisc1_dr_2500BRCM_X1 16 4742 #define rx_x4_control0_actualSpeedsMisc1_dr_5000BRCM_X4 17 4743 #define rx_x4_control0_actualSpeedsMisc1_dr_6000BRCM_X4 18 4744 #define rx_x4_control0_actualSpeedsMisc1_dr_10GHiGig_X4 19 4745 #define rx_x4_control0_actualSpeedsMisc1_dr_10GBASE_CX4 20 4746 #define rx_x4_control0_actualSpeedsMisc1_dr_12GHiGig_X4 21 4747 #define rx_x4_control0_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 4748 #define rx_x4_control0_actualSpeedsMisc1_dr_13GHiGig_X4 23 4749 #define rx_x4_control0_actualSpeedsMisc1_dr_15GHiGig_X4 24 4750 #define rx_x4_control0_actualSpeedsMisc1_dr_16GHiGig_X4 25 4751 #define rx_x4_control0_actualSpeedsMisc1_dr_5000BRCM_X1 26 4752 #define rx_x4_control0_actualSpeedsMisc1_dr_6363BRCM_X1 27 4753 #define rx_x4_control0_actualSpeedsMisc1_dr_20GHiGig_X4 28 4754 #define rx_x4_control0_actualSpeedsMisc1_dr_21GHiGig_X4 29 4755 #define rx_x4_control0_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 4756 #define rx_x4_control0_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 4757 4758 /**************************************************************************** 4759 * Enums: rx_x4_control0_IndLaneModes 4760 */ 4761 #define rx_x4_control0_IndLaneModes_SWSDR_div2 0 4762 #define rx_x4_control0_IndLaneModes_SWSDR_div1 1 4763 #define rx_x4_control0_IndLaneModes_DWSDR_div2 2 4764 #define rx_x4_control0_IndLaneModes_DWSDR_div1 3 4765 4766 /**************************************************************************** 4767 * Enums: rx_x4_control0_prbsSelect 4768 */ 4769 #define rx_x4_control0_prbsSelect_prbs7 0 4770 #define rx_x4_control0_prbsSelect_prbs15 1 4771 #define rx_x4_control0_prbsSelect_prbs23 2 4772 #define rx_x4_control0_prbsSelect_prbs31 3 4773 4774 /**************************************************************************** 4775 * Enums: rx_x4_control0_vcoDivider 4776 */ 4777 #define rx_x4_control0_vcoDivider_div32 0 4778 #define rx_x4_control0_vcoDivider_div36 1 4779 #define rx_x4_control0_vcoDivider_div40 2 4780 #define rx_x4_control0_vcoDivider_div42 3 4781 #define rx_x4_control0_vcoDivider_div48 4 4782 #define rx_x4_control0_vcoDivider_div50 5 4783 #define rx_x4_control0_vcoDivider_div52 6 4784 #define rx_x4_control0_vcoDivider_div54 7 4785 #define rx_x4_control0_vcoDivider_div60 8 4786 #define rx_x4_control0_vcoDivider_div64 9 4787 #define rx_x4_control0_vcoDivider_div66 10 4788 #define rx_x4_control0_vcoDivider_div68 11 4789 #define rx_x4_control0_vcoDivider_div70 12 4790 #define rx_x4_control0_vcoDivider_div80 13 4791 #define rx_x4_control0_vcoDivider_div92 14 4792 #define rx_x4_control0_vcoDivider_div100 15 4793 4794 /**************************************************************************** 4795 * Enums: rx_x4_control0_refClkSelect 4796 */ 4797 #define rx_x4_control0_refClkSelect_clk_156p25MHz 1 4798 #define rx_x4_control0_refClkSelect_clk_312p5Mhz 2 4799 4800 /**************************************************************************** 4801 * Enums: rx_x4_control0_aerMMDdevTypeSelect 4802 */ 4803 #define rx_x4_control0_aerMMDdevTypeSelect_combo_core 0 4804 #define rx_x4_control0_aerMMDdevTypeSelect_PMA_PMD 1 4805 #define rx_x4_control0_aerMMDdevTypeSelect_PCS 3 4806 #define rx_x4_control0_aerMMDdevTypeSelect_PHY 4 4807 #define rx_x4_control0_aerMMDdevTypeSelect_DTE 5 4808 #define rx_x4_control0_aerMMDdevTypeSelect_CL73_AN 7 4809 4810 /**************************************************************************** 4811 * Enums: rx_x4_control0_aerMMDportSelect 4812 */ 4813 #define rx_x4_control0_aerMMDportSelect_ln0 0 4814 #define rx_x4_control0_aerMMDportSelect_ln1 1 4815 #define rx_x4_control0_aerMMDportSelect_ln2 2 4816 #define rx_x4_control0_aerMMDportSelect_ln3 3 4817 #define rx_x4_control0_aerMMDportSelect_BCST_ln0_1_2_3 511 4818 #define rx_x4_control0_aerMMDportSelect_BCST_ln0_1 512 4819 #define rx_x4_control0_aerMMDportSelect_BCST_ln2_3 513 4820 4821 /**************************************************************************** 4822 * Enums: rx_x4_control0_firmwareModeSelect 4823 */ 4824 #define rx_x4_control0_firmwareModeSelect_DEFAULT 0 4825 #define rx_x4_control0_firmwareModeSelect_SFP_OPT_LR 1 4826 #define rx_x4_control0_firmwareModeSelect_SFP_DAC 2 4827 #define rx_x4_control0_firmwareModeSelect_XLAUI 3 4828 #define rx_x4_control0_firmwareModeSelect_LONG_CH_6G 4 4829 4830 /**************************************************************************** 4831 * Enums: rx_x4_control0_tempIdxSelect 4832 */ 4833 #define rx_x4_control0_tempIdxSelect_LTE__22p9C 15 4834 #define rx_x4_control0_tempIdxSelect_LTE__12p6C 14 4835 #define rx_x4_control0_tempIdxSelect_LTE__3p0C 13 4836 #define rx_x4_control0_tempIdxSelect_LTE_6p7C 12 4837 #define rx_x4_control0_tempIdxSelect_LTE_16p4C 11 4838 #define rx_x4_control0_tempIdxSelect_LTE_26p6C 10 4839 #define rx_x4_control0_tempIdxSelect_LTE_36p3C 9 4840 #define rx_x4_control0_tempIdxSelect_LTE_46p0C 8 4841 #define rx_x4_control0_tempIdxSelect_LTE_56p2C 7 4842 #define rx_x4_control0_tempIdxSelect_LTE_65p9C 6 4843 #define rx_x4_control0_tempIdxSelect_LTE_75p6C 5 4844 #define rx_x4_control0_tempIdxSelect_LTE_85p3C 4 4845 #define rx_x4_control0_tempIdxSelect_LTE_95p5C 3 4846 #define rx_x4_control0_tempIdxSelect_LTE_105p2C 2 4847 #define rx_x4_control0_tempIdxSelect_LTE_114p9C 1 4848 #define rx_x4_control0_tempIdxSelect_LTE_125p1C 0 4849 4850 /**************************************************************************** 4851 * Enums: rx_x4_control0_port_mode 4852 */ 4853 #define rx_x4_control0_port_mode_QUAD_PORT 0 4854 #define rx_x4_control0_port_mode_TRI_1_PORT 1 4855 #define rx_x4_control0_port_mode_TRI_2_PORT 2 4856 #define rx_x4_control0_port_mode_DUAL_PORT 3 4857 #define rx_x4_control0_port_mode_SINGLE_PORT 4 4858 #define rx_x4_control0_port_mode_SINGLE_OCTAL_PORT 5 4859 4860 /**************************************************************************** 4861 * Enums: rx_x4_control0_rev_letter_enum 4862 */ 4863 #define rx_x4_control0_rev_letter_enum_REV_A 0 4864 #define rx_x4_control0_rev_letter_enum_REV_B 1 4865 #define rx_x4_control0_rev_letter_enum_REV_C 2 4866 #define rx_x4_control0_rev_letter_enum_REV_D 3 4867 4868 /**************************************************************************** 4869 * Enums: rx_x4_control0_rev_number_enum 4870 */ 4871 #define rx_x4_control0_rev_number_enum_REV_0 0 4872 #define rx_x4_control0_rev_number_enum_REV_1 1 4873 #define rx_x4_control0_rev_number_enum_REV_2 2 4874 #define rx_x4_control0_rev_number_enum_REV_3 3 4875 #define rx_x4_control0_rev_number_enum_REV_4 4 4876 #define rx_x4_control0_rev_number_enum_REV_5 5 4877 #define rx_x4_control0_rev_number_enum_REV_6 6 4878 #define rx_x4_control0_rev_number_enum_REV_7 7 4879 4880 /**************************************************************************** 4881 * Enums: rx_x4_control0_bonding_enum 4882 */ 4883 #define rx_x4_control0_bonding_enum_WIRE_BOND 0 4884 #define rx_x4_control0_bonding_enum_FLIP_CHIP 1 4885 4886 /**************************************************************************** 4887 * Enums: rx_x4_control0_tech_process 4888 */ 4889 #define rx_x4_control0_tech_process_PROCESS_90NM 0 4890 #define rx_x4_control0_tech_process_PROCESS_65NM 1 4891 #define rx_x4_control0_tech_process_PROCESS_40NM 2 4892 #define rx_x4_control0_tech_process_PROCESS_28NM 3 4893 #define rx_x4_control0_tech_process_PROCESS_16NM 4 4894 4895 /**************************************************************************** 4896 * Enums: rx_x4_control0_model_num 4897 */ 4898 #define rx_x4_control0_model_num_SERDES_CL73 0 4899 #define rx_x4_control0_model_num_XGXS_16G 1 4900 #define rx_x4_control0_model_num_HYPERCORE 2 4901 #define rx_x4_control0_model_num_HYPERLITE 3 4902 #define rx_x4_control0_model_num_PCIE_G2_PIPE 4 4903 #define rx_x4_control0_model_num_SERDES_1p25GBd 5 4904 #define rx_x4_control0_model_num_SATA2 6 4905 #define rx_x4_control0_model_num_QSGMII 7 4906 #define rx_x4_control0_model_num_XGXS10G 8 4907 #define rx_x4_control0_model_num_WARPCORE 9 4908 #define rx_x4_control0_model_num_XFICORE 10 4909 #define rx_x4_control0_model_num_RXFI 11 4910 #define rx_x4_control0_model_num_WARPLITE 12 4911 #define rx_x4_control0_model_num_PENTACORE 13 4912 #define rx_x4_control0_model_num_ESM 14 4913 #define rx_x4_control0_model_num_QUAD_SGMII 15 4914 #define rx_x4_control0_model_num_WARPCORE_3 16 4915 #define rx_x4_control0_model_num_TSC 17 4916 #define rx_x4_control0_model_num_TSC4E 18 4917 #define rx_x4_control0_model_num_TSC12E 19 4918 #define rx_x4_control0_model_num_TSC4F 20 4919 #define rx_x4_control0_model_num_TSC4F_GEN2 21 4920 #define rx_x4_control0_model_num_XGXS_CL73_90NM 29 4921 #define rx_x4_control0_model_num_SERDES_CL73_90NM 30 4922 #define rx_x4_control0_model_num_WARPCORE3 32 4923 #define rx_x4_control0_model_num_WARPCORE4_TSC 33 4924 #define rx_x4_control0_model_num_RXAUI 34 4925 #define rx_x4_control0_model_num_TSCE_GEN3 35 4926 #define rx_x4_control0_model_num_TSC4F_GEN3 36 4927 #define rx_x4_control0_model_num_TSCBH 37 4928 4929 /**************************************************************************** 4930 * Enums: rx_x4_control0_payload 4931 */ 4932 #define rx_x4_control0_payload_REPEAT_2_BYTES 0 4933 #define rx_x4_control0_payload_RAMPING 1 4934 #define rx_x4_control0_payload_CL48_CRPAT 2 4935 #define rx_x4_control0_payload_CL48_CJPAT 3 4936 #define rx_x4_control0_payload_CL36_LONG_CRPAT 4 4937 #define rx_x4_control0_payload_CL36_SHORT_CRPAT 5 4938 4939 /**************************************************************************** 4940 * Enums: rx_x4_control0_sc 4941 */ 4942 #define rx_x4_control0_sc_SPEED_10G_IEEE_KR1 0 4943 #define rx_x4_control0_sc_SPEED_25G_IEEE_KS1_CS1 1 4944 #define rx_x4_control0_sc_SPEED_25G_IEEE_KR1_CR1 2 4945 #define rx_x4_control0_sc_SPEED_40G_IEEE_KR4 3 4946 #define rx_x4_control0_sc_SPEED_40G_IEEE_CR4 4 4947 #define rx_x4_control0_sc_SPEED_50G_IEEE_KR1_CR1 5 4948 #define rx_x4_control0_sc_SPEED_100G_IEEE_KR4 6 4949 #define rx_x4_control0_sc_SPEED_100G_IEEE_CR4 7 4950 #define rx_x4_control0_sc_SPEED_100G_IEEE_KR2_CR2 8 4951 #define rx_x4_control0_sc_SPEED_200G_IEEE_KR4_CR4 9 4952 #define rx_x4_control0_sc_SPEED_400G_IEEE_X8 10 4953 #define rx_x4_control0_sc_SPEED_CL73_IEEE_20GVCO 11 4954 #define rx_x4_control0_sc_SPEED_CL73_IEEE_25GVCO 12 4955 #define rx_x4_control0_sc_SPEED_CL73_IEEE_26GVCO 13 4956 #define rx_x4_control0_sc_SPEED_20G_BRCM_CR1 14 4957 #define rx_x4_control0_sc_SPEED_20G_BRCM_KR1 15 4958 #define rx_x4_control0_sc_SPEED_25G_BRCM_CR1 16 4959 #define rx_x4_control0_sc_SPEED_25G_BRCM_KR1 17 4960 #define rx_x4_control0_sc_SPEED_40G_BRCM_CR2 18 4961 #define rx_x4_control0_sc_SPEED_40G_BRCM_KR2 19 4962 #define rx_x4_control0_sc_SPEED_50G_BRCM_CR2 20 4963 #define rx_x4_control0_sc_SPEED_50G_BRCM_KR2 21 4964 #define rx_x4_control0_sc_SPEED_50G_BRCM_CR4 22 4965 #define rx_x4_control0_sc_SPEED_50G_BRCM_KR4 23 4966 #define rx_x4_control0_sc_SPEED_50G_BRCM_FEC_544_CR2_KR2 24 4967 #define rx_x4_control0_sc_SPEED_RESERVED_19 25 4968 #define rx_x4_control0_sc_SPEED_50G_BRCM_FEC_544_CR1_KR1 26 4969 #define rx_x4_control0_sc_SPEED_50G_BRCM_NO_FEC_CR1_KR1 27 4970 #define rx_x4_control0_sc_SPEED_50G_BRCM_FEC_528_CR1_KR1 28 4971 #define rx_x4_control0_sc_SPEED_400G_BRCM_NO_FEC_KR8_CR8 29 4972 #define rx_x4_control0_sc_SPEED_400G_BRCM_FEC_KR8_CR8 30 4973 #define rx_x4_control0_sc_SPEED_200G_BRCM_NO_FEC_KR4_CR4 31 4974 #define rx_x4_control0_sc_SPEED_200G_BRCM_KR4_CR4 32 4975 #define rx_x4_control0_sc_SPEED_100G_BRCM_KR4_CR4 33 4976 #define rx_x4_control0_sc_SPEED_RESERVED_22 34 4977 #define rx_x4_control0_sc_SPEED_100G_BRCM_FEC_528_KR2_CR2 35 4978 #define rx_x4_control0_sc_SPEED_100G_BRCM_NO_FEC_KR2_CR2 36 4979 #define rx_x4_control0_sc_SPEED_100G_BRCM_NO_FEC_X4 37 4980 4981 /**************************************************************************** 4982 * Enums: rx_x4_control0_t_fifo_modes 4983 */ 4984 #define rx_x4_control0_t_fifo_modes_T_FIFO_INSERT_NO_AM 0 4985 #define rx_x4_control0_t_fifo_modes_T_FIFO_INSERT_4_AM 1 4986 #define rx_x4_control0_t_fifo_modes_T_FIFO_INSERT_20_AM 2 4987 #define rx_x4_control0_t_fifo_modes_T_FIFO_INSERT_2_AM 3 4988 4989 /**************************************************************************** 4990 * Enums: rx_x4_control0_t_enc_modes 4991 */ 4992 #define rx_x4_control0_t_enc_modes_T_ENC_MODE_BYPASS 0 4993 #define rx_x4_control0_t_enc_modes_T_ENC_MODE_CL49 1 4994 #define rx_x4_control0_t_enc_modes_T_ENC_MODE_CL82 2 4995 4996 /**************************************************************************** 4997 * Enums: rx_x4_control0_btmx_mode 4998 */ 4999 #define rx_x4_control0_btmx_mode_BS_BTMX_MODE_1to1 0 5000 #define rx_x4_control0_btmx_mode_BS_BTMX_MODE_2to1 1 5001 #define rx_x4_control0_btmx_mode_BS_BTMX_MODE_5to1 2 5002 5003 /**************************************************************************** 5004 * Enums: rx_x4_control0_t_type_cl82 5005 */ 5006 #define rx_x4_control0_t_type_cl82_T_TYPE_B1 5 5007 #define rx_x4_control0_t_type_cl82_T_TYPE_C 4 5008 #define rx_x4_control0_t_type_cl82_T_TYPE_S 3 5009 #define rx_x4_control0_t_type_cl82_T_TYPE_T 2 5010 #define rx_x4_control0_t_type_cl82_T_TYPE_D 1 5011 #define rx_x4_control0_t_type_cl82_T_TYPE_E 0 5012 5013 /**************************************************************************** 5014 * Enums: rx_x4_control0_txsm_state_cl82 5015 */ 5016 #define rx_x4_control0_txsm_state_cl82_TX_E 4 5017 #define rx_x4_control0_txsm_state_cl82_TX_T 3 5018 #define rx_x4_control0_txsm_state_cl82_TX_D 2 5019 #define rx_x4_control0_txsm_state_cl82_TX_C 1 5020 #define rx_x4_control0_txsm_state_cl82_TX_INIT 0 5021 5022 /**************************************************************************** 5023 * Enums: rx_x4_control0_ltxsm_state_cl82 5024 */ 5025 #define rx_x4_control0_ltxsm_state_cl82_TX_E 16 5026 #define rx_x4_control0_ltxsm_state_cl82_TX_T 8 5027 #define rx_x4_control0_ltxsm_state_cl82_TX_D 4 5028 #define rx_x4_control0_ltxsm_state_cl82_TX_C 2 5029 #define rx_x4_control0_ltxsm_state_cl82_TX_INIT 1 5030 5031 /**************************************************************************** 5032 * Enums: rx_x4_control0_r_type_coded_cl82 5033 */ 5034 #define rx_x4_control0_r_type_coded_cl82_R_TYPE_B1 32 5035 #define rx_x4_control0_r_type_coded_cl82_R_TYPE_C 16 5036 #define rx_x4_control0_r_type_coded_cl82_R_TYPE_S 8 5037 #define rx_x4_control0_r_type_coded_cl82_R_TYPE_T 4 5038 #define rx_x4_control0_r_type_coded_cl82_R_TYPE_D 2 5039 #define rx_x4_control0_r_type_coded_cl82_R_TYPE_E 1 5040 5041 /**************************************************************************** 5042 * Enums: rx_x4_control0_rxsm_state_cl82 5043 */ 5044 #define rx_x4_control0_rxsm_state_cl82_RX_E 16 5045 #define rx_x4_control0_rxsm_state_cl82_RX_T 8 5046 #define rx_x4_control0_rxsm_state_cl82_RX_D 4 5047 #define rx_x4_control0_rxsm_state_cl82_RX_C 2 5048 #define rx_x4_control0_rxsm_state_cl82_RX_INIT 1 5049 5050 /**************************************************************************** 5051 * Enums: rx_x4_control0_deskew_state 5052 */ 5053 #define rx_x4_control0_deskew_state_ALIGN_ACQUIRED 2 5054 #define rx_x4_control0_deskew_state_LOSS_OF_ALIGNMENT 1 5055 5056 /**************************************************************************** 5057 * Enums: rx_x4_control0_os_mode_enum 5058 */ 5059 #define rx_x4_control0_os_mode_enum_OS_MODE_1 0 5060 #define rx_x4_control0_os_mode_enum_OS_MODE_2 1 5061 #define rx_x4_control0_os_mode_enum_OS_MODE_4 2 5062 #define rx_x4_control0_os_mode_enum_OS_MODE_16p5 8 5063 #define rx_x4_control0_os_mode_enum_OS_MODE_20p625 12 5064 5065 /**************************************************************************** 5066 * Enums: rx_x4_control0_scr_modes 5067 */ 5068 #define rx_x4_control0_scr_modes_T_SCR_MODE_BYPASS 0 5069 #define rx_x4_control0_scr_modes_T_SCR_MODE_CL49 1 5070 #define rx_x4_control0_scr_modes_T_SCR_MODE_40G_2_LANE 2 5071 #define rx_x4_control0_scr_modes_T_SCR_MODE_100G 3 5072 #define rx_x4_control0_scr_modes_T_SCR_MODE_20G 4 5073 #define rx_x4_control0_scr_modes_T_SCR_MODE_40G_4_LANE 5 5074 5075 /**************************************************************************** 5076 * Enums: rx_x4_control0_descr_modes 5077 */ 5078 #define rx_x4_control0_descr_modes_R_DESCR_MODE_BYPASS 0 5079 #define rx_x4_control0_descr_modes_R_DESCR_MODE_CL49 1 5080 #define rx_x4_control0_descr_modes_R_DESCR_MODE_CL82 2 5081 5082 /**************************************************************************** 5083 * Enums: rx_x4_control0_r_dec_tl_mode 5084 */ 5085 #define rx_x4_control0_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 5086 #define rx_x4_control0_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 5087 #define rx_x4_control0_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 5088 5089 /**************************************************************************** 5090 * Enums: rx_x4_control0_r_dec_fsm_mode 5091 */ 5092 #define rx_x4_control0_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 5093 #define rx_x4_control0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 5094 #define rx_x4_control0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 5095 5096 /**************************************************************************** 5097 * Enums: rx_x4_control0_r_deskew_mode 5098 */ 5099 #define rx_x4_control0_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 5100 #define rx_x4_control0_r_deskew_mode_R_DESKEW_MODE_20G 1 5101 #define rx_x4_control0_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 5102 #define rx_x4_control0_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 5103 #define rx_x4_control0_r_deskew_mode_R_DESKEW_MODE_100G 4 5104 #define rx_x4_control0_r_deskew_mode_R_DESKEW_MODE_CL49 5 5105 #define rx_x4_control0_r_deskew_mode_R_DESKEW_MODE_CL91_QUAD 6 5106 #define rx_x4_control0_r_deskew_mode_R_DESKEW_MODE_CL91_SINGLE_BRCM 7 5107 #define rx_x4_control0_r_deskew_mode_R_DESKEW_MODE_CL91_DUAL_BRCM 8 5108 #define rx_x4_control0_r_deskew_mode_R_DESKEW_MODE_CL91_FC 9 5109 5110 /**************************************************************************** 5111 * Enums: rx_x4_control0_bs_dist_modes 5112 */ 5113 #define rx_x4_control0_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 5114 #define rx_x4_control0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 5115 #define rx_x4_control0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 5116 #define rx_x4_control0_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 5117 5118 /**************************************************************************** 5119 * Enums: rx_x4_control0_cl49_t_type 5120 */ 5121 #define rx_x4_control0_cl49_t_type_BAD_T_TYPE 15 5122 #define rx_x4_control0_cl49_t_type_T_TYPE_B0 11 5123 #define rx_x4_control0_cl49_t_type_T_TYPE_OB 10 5124 #define rx_x4_control0_cl49_t_type_T_TYPE_B1 9 5125 #define rx_x4_control0_cl49_t_type_T_TYPE_DB 8 5126 #define rx_x4_control0_cl49_t_type_T_TYPE_FC 7 5127 #define rx_x4_control0_cl49_t_type_T_TYPE_TB 6 5128 #define rx_x4_control0_cl49_t_type_T_TYPE_LI 5 5129 #define rx_x4_control0_cl49_t_type_T_TYPE_C 4 5130 #define rx_x4_control0_cl49_t_type_T_TYPE_S 3 5131 #define rx_x4_control0_cl49_t_type_T_TYPE_T 2 5132 #define rx_x4_control0_cl49_t_type_T_TYPE_D 1 5133 #define rx_x4_control0_cl49_t_type_T_TYPE_E 0 5134 5135 /**************************************************************************** 5136 * Enums: rx_x4_control0_cl49_txsm_states 5137 */ 5138 #define rx_x4_control0_cl49_txsm_states_TX_LI 5 5139 #define rx_x4_control0_cl49_txsm_states_TX_E 4 5140 #define rx_x4_control0_cl49_txsm_states_TX_T 3 5141 #define rx_x4_control0_cl49_txsm_states_TX_D 2 5142 #define rx_x4_control0_cl49_txsm_states_TX_C 1 5143 #define rx_x4_control0_cl49_txsm_states_TX_INIT 0 5144 5145 /**************************************************************************** 5146 * Enums: rx_x4_control0_cl49_ltxsm_states 5147 */ 5148 #define rx_x4_control0_cl49_ltxsm_states_TX_LI 32 5149 #define rx_x4_control0_cl49_ltxsm_states_TX_E 16 5150 #define rx_x4_control0_cl49_ltxsm_states_TX_T 8 5151 #define rx_x4_control0_cl49_ltxsm_states_TX_D 4 5152 #define rx_x4_control0_cl49_ltxsm_states_TX_C 2 5153 #define rx_x4_control0_cl49_ltxsm_states_TX_INIT 1 5154 5155 /**************************************************************************** 5156 * Enums: rx_x4_control0_burst_error_mode 5157 */ 5158 #define rx_x4_control0_burst_error_mode_BURST_ERROR_11_BITS 0 5159 #define rx_x4_control0_burst_error_mode_BURST_ERROR_16_BITS 1 5160 #define rx_x4_control0_burst_error_mode_BURST_ERROR_17_BITS 2 5161 #define rx_x4_control0_burst_error_mode_BURST_ERROR_18_BITS 3 5162 #define rx_x4_control0_burst_error_mode_BURST_ERROR_19_BITS 4 5163 #define rx_x4_control0_burst_error_mode_BURST_ERROR_20_BITS 5 5164 #define rx_x4_control0_burst_error_mode_BURST_ERROR_21_BITS 6 5165 #define rx_x4_control0_burst_error_mode_BURST_ERROR_22_BITS 7 5166 #define rx_x4_control0_burst_error_mode_BURST_ERROR_23_BITS 8 5167 #define rx_x4_control0_burst_error_mode_BURST_ERROR_24_BITS 9 5168 #define rx_x4_control0_burst_error_mode_BURST_ERROR_25_BITS 10 5169 #define rx_x4_control0_burst_error_mode_BURST_ERROR_26_BITS 11 5170 #define rx_x4_control0_burst_error_mode_BURST_ERROR_27_BITS 12 5171 #define rx_x4_control0_burst_error_mode_BURST_ERROR_28_BITS 13 5172 #define rx_x4_control0_burst_error_mode_BURST_ERROR_29_BITS 14 5173 #define rx_x4_control0_burst_error_mode_BURST_ERROR_30_BITS 15 5174 #define rx_x4_control0_burst_error_mode_BURST_ERROR_31_BITS 16 5175 #define rx_x4_control0_burst_error_mode_BURST_ERROR_32_BITS 17 5176 #define rx_x4_control0_burst_error_mode_BURST_ERROR_33_BITS 18 5177 #define rx_x4_control0_burst_error_mode_BURST_ERROR_34_BITS 19 5178 #define rx_x4_control0_burst_error_mode_BURST_ERROR_35_BITS 20 5179 #define rx_x4_control0_burst_error_mode_BURST_ERROR_36_BITS 21 5180 #define rx_x4_control0_burst_error_mode_BURST_ERROR_37_BITS 22 5181 #define rx_x4_control0_burst_error_mode_BURST_ERROR_38_BITS 23 5182 #define rx_x4_control0_burst_error_mode_BURST_ERROR_39_BITS 24 5183 #define rx_x4_control0_burst_error_mode_BURST_ERROR_40_BITS 25 5184 #define rx_x4_control0_burst_error_mode_BURST_ERROR_41_BITS 26 5185 5186 /**************************************************************************** 5187 * Enums: rx_x4_control0_bermon_state 5188 */ 5189 #define rx_x4_control0_bermon_state_HI_BER 4 5190 #define rx_x4_control0_bermon_state_GOOD_BER 3 5191 #define rx_x4_control0_bermon_state_BER_TEST_SH 2 5192 #define rx_x4_control0_bermon_state_START_TIMER 1 5193 #define rx_x4_control0_bermon_state_BER_MT_INIT 0 5194 5195 /**************************************************************************** 5196 * Enums: rx_x4_control0_rxsm_state_cl49 5197 */ 5198 #define rx_x4_control0_rxsm_state_cl49_RX_LI 32 5199 #define rx_x4_control0_rxsm_state_cl49_RX_E 16 5200 #define rx_x4_control0_rxsm_state_cl49_RX_T 8 5201 #define rx_x4_control0_rxsm_state_cl49_RX_D 4 5202 #define rx_x4_control0_rxsm_state_cl49_RX_C 2 5203 #define rx_x4_control0_rxsm_state_cl49_RX_INIT 1 5204 5205 /**************************************************************************** 5206 * Enums: rx_x4_control0_r_type 5207 */ 5208 #define rx_x4_control0_r_type_BAD_R_TYPE 15 5209 #define rx_x4_control0_r_type_R_TYPE_B0 11 5210 #define rx_x4_control0_r_type_R_TYPE_OB 10 5211 #define rx_x4_control0_r_type_R_TYPE_B1 9 5212 #define rx_x4_control0_r_type_R_TYPE_DB 8 5213 #define rx_x4_control0_r_type_R_TYPE_FC 7 5214 #define rx_x4_control0_r_type_R_TYPE_TB 6 5215 #define rx_x4_control0_r_type_R_TYPE_LI 5 5216 #define rx_x4_control0_r_type_R_TYPE_C 4 5217 #define rx_x4_control0_r_type_R_TYPE_S 3 5218 #define rx_x4_control0_r_type_R_TYPE_T 2 5219 #define rx_x4_control0_r_type_R_TYPE_D 1 5220 #define rx_x4_control0_r_type_R_TYPE_E 0 5221 5222 /**************************************************************************** 5223 * Enums: rx_x4_control0_am_lock_state 5224 */ 5225 #define rx_x4_control0_am_lock_state_INVALID_AM 512 5226 #define rx_x4_control0_am_lock_state_GOOD_AM 256 5227 #define rx_x4_control0_am_lock_state_COMP_AM 128 5228 #define rx_x4_control0_am_lock_state_TIMER_2 64 5229 #define rx_x4_control0_am_lock_state_AM_2_GOOD 32 5230 #define rx_x4_control0_am_lock_state_COMP_2ND 16 5231 #define rx_x4_control0_am_lock_state_TIMER_1 8 5232 #define rx_x4_control0_am_lock_state_FIND_1ST 4 5233 #define rx_x4_control0_am_lock_state_AM_RESET_CNT 2 5234 #define rx_x4_control0_am_lock_state_AM_LOCK_INIT 1 5235 5236 /**************************************************************************** 5237 * Enums: rx_x4_control0_msg_selector 5238 */ 5239 #define rx_x4_control0_msg_selector_RESERVED 0 5240 #define rx_x4_control0_msg_selector_VALUE_802p3 1 5241 #define rx_x4_control0_msg_selector_VALUE_802p9 2 5242 #define rx_x4_control0_msg_selector_VALUE_802p5 3 5243 #define rx_x4_control0_msg_selector_VALUE_1394 4 5244 5245 /**************************************************************************** 5246 * Enums: rx_x4_control0_synce_enum_stage1 5247 */ 5248 #define rx_x4_control0_synce_enum_stage1_SYNCE_NO_DIV 0 5249 #define rx_x4_control0_synce_enum_stage1_SYNCE_DIV_7 1 5250 #define rx_x4_control0_synce_enum_stage1_SYNCE_DIV_11 2 5251 5252 /**************************************************************************** 5253 * Enums: rx_x4_control0_synce_enum_stage0 5254 */ 5255 #define rx_x4_control0_synce_enum_stage0_SYNCE_NO_DIV 0 5256 #define rx_x4_control0_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 5257 #define rx_x4_control0_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 5258 5259 /**************************************************************************** 5260 * Enums: rx_x4_control0_cl91_sync_state 5261 */ 5262 #define rx_x4_control0_cl91_sync_state_FIND_1ST 0 5263 #define rx_x4_control0_cl91_sync_state_COUNT_NEXT 1 5264 #define rx_x4_control0_cl91_sync_state_COMP_2ND 2 5265 #define rx_x4_control0_cl91_sync_state_TWO_GOOD 3 5266 5267 /**************************************************************************** 5268 * Enums: rx_x4_control0_RS_FEC_sync_state 5269 */ 5270 #define rx_x4_control0_RS_FEC_sync_state_LOCK_INIT 0 5271 #define rx_x4_control0_RS_FEC_sync_state_FIND_1ST 1 5272 #define rx_x4_control0_RS_FEC_sync_state_COUNT_NEXT 2 5273 #define rx_x4_control0_RS_FEC_sync_state_COMP_2ND 3 5274 #define rx_x4_control0_RS_FEC_sync_state_TWO_GOOD 4 5275 5276 /**************************************************************************** 5277 * Enums: rx_x4_control0_cl91_algn_state 5278 */ 5279 #define rx_x4_control0_cl91_algn_state_LOSS_OF_ALIGNMENT 0 5280 #define rx_x4_control0_cl91_algn_state_DESKEW 1 5281 #define rx_x4_control0_cl91_algn_state_DESKEW_FAIL 2 5282 #define rx_x4_control0_cl91_algn_state_ALIGN_ACQUIRED 3 5283 #define rx_x4_control0_cl91_algn_state_CW_GOOD 4 5284 #define rx_x4_control0_cl91_algn_state_CW_BAD 5 5285 #define rx_x4_control0_cl91_algn_state_THREE_BAD 6 5286 5287 /**************************************************************************** 5288 * Enums: rx_x4_control0_RS_FEC_algn_state 5289 */ 5290 #define rx_x4_control0_RS_FEC_algn_state_LOSS_OF_ALIGNMENT 0 5291 #define rx_x4_control0_RS_FEC_algn_state_DESKEW 1 5292 #define rx_x4_control0_RS_FEC_algn_state_DESKEW_FAIL 2 5293 #define rx_x4_control0_RS_FEC_algn_state_ALIGN_ACQUIRED 3 5294 #define rx_x4_control0_RS_FEC_algn_state_CW_GOOD 4 5295 #define rx_x4_control0_RS_FEC_algn_state_CW_BAD 5 5296 #define rx_x4_control0_RS_FEC_algn_state_THREE_BAD 6 5297 5298 /**************************************************************************** 5299 * Enums: rx_x4_control0_fec_sel_override 5300 */ 5301 #define rx_x4_control0_fec_sel_override_NO_OVERRIDE 0 5302 #define rx_x4_control0_fec_sel_override_NO_FEC 1 5303 #define rx_x4_control0_fec_sel_override_FEC_CL74 2 5304 #define rx_x4_control0_fec_sel_override_FEC_CL91 3 5305 5306 /**************************************************************************** 5307 * Enums: rx_x4_control0_cl91_blksync_mode 5308 */ 5309 #define rx_x4_control0_cl91_blksync_mode_R_BLKSYNC_NO_CL91_FEC 0 5310 #define rx_x4_control0_cl91_blksync_mode_R_BLKSYNC_CL91_QUAD_LANE_FEC 1 5311 #define rx_x4_control0_cl91_blksync_mode_R_BLKSYNC_CL91_DUAL_LANE_FEC 2 5312 #define rx_x4_control0_cl91_blksync_mode_R_BLKSYNC_CL91_SINGLE_LANE_FEC 3 5313 #define rx_x4_control0_cl91_blksync_mode_R_BLKSYNC_CL91_FC_FEC 4 5314 5315 /**************************************************************************** 5316 * Enums: rx_x4_control0_r_merge_mode 5317 */ 5318 #define rx_x4_control0_r_merge_mode_R_MERGE_MODE_BYPASS 0 5319 #define rx_x4_control0_r_merge_mode_R_MERGE_MODE_CL91_FC 1 5320 #define rx_x4_control0_r_merge_mode_R_MERGE_MODE_CL91_SINGLE_LANE 2 5321 #define rx_x4_control0_r_merge_mode_R_MERGE_MODE_CL91_DUAL_LANE 3 5322 #define rx_x4_control0_r_merge_mode_R_MERGE_MODE_CL91_QUAD_LANE 4 5323 5324 /**************************************************************************** 5325 * Enums: rx_x4_control0_r_tc_mode 5326 */ 5327 #define rx_x4_control0_r_tc_mode_R_TC_MODE_SINGLE 0 5328 #define rx_x4_control0_r_tc_mode_R_TC_MODE_DUAL 1 5329 #define rx_x4_control0_r_tc_mode_R_TC_MODE_QUAD 2 5330 5331 /**************************************************************************** 5332 * Enums: rx_x4_control0_r_tc_out_mode 5333 */ 5334 #define rx_x4_control0_r_tc_out_mode_R_TC_OUT_MODE_SINGLE 0 5335 #define rx_x4_control0_r_tc_out_mode_R_TC_OUT_MODE_DUAL 1 5336 #define rx_x4_control0_r_tc_out_mode_R_TC_OUT_MODE_QUAD 2 5337 5338 /**************************************************************************** 5339 * Enums: rx_x4_control0_cl91_fec_mode 5340 */ 5341 #define rx_x4_control0_cl91_fec_mode_NO_CL91_FEC 0 5342 #define rx_x4_control0_cl91_fec_mode_CL91_SINGLE_LANE_FC 1 5343 #define rx_x4_control0_cl91_fec_mode_CL91_SINGLE_LANE_BRCM_PROP 2 5344 #define rx_x4_control0_cl91_fec_mode_CL91_DUAL_LANE_BRCM_PROP 3 5345 #define rx_x4_control0_cl91_fec_mode_CL91_QUAD_LANE 4 5346 #define rx_x4_control0_cl91_fec_mode_IEEE_25G_CL91_SINGLE_LANE 5 5347 5348 /**************************************************************************** 5349 * Enums: rx_x4_control0_RS_FEC_fec_mode 5350 */ 5351 #define rx_x4_control0_RS_FEC_fec_mode_NO_RS_FEC_FEC 0 5352 #define rx_x4_control0_RS_FEC_fec_mode_N_A 1 5353 #define rx_x4_control0_RS_FEC_fec_mode_RS_FEC_SINGLE_LANE_BRCM_PROP 2 5354 #define rx_x4_control0_RS_FEC_fec_mode_RS_FEC_DUAL_LANE_BRCM_PROP 3 5355 #define rx_x4_control0_RS_FEC_fec_mode_RS_FEC_QUAD_LANE 4 5356 #define rx_x4_control0_RS_FEC_fec_mode_IEEE_25G_RS_FEC_SINGLE_LANE 5 5357 5358 /**************************************************************************** 5359 * Enums: rx_x4_control0_am_spacing_mul 5360 */ 5361 #define rx_x4_control0_am_spacing_mul_AM_SPACING_MUL_2 0 5362 #define rx_x4_control0_am_spacing_mul_AM_SPACING_MUL_4 1 5363 #define rx_x4_control0_am_spacing_mul_AM_SPACING_MUL_5 2 5364 #define rx_x4_control0_am_spacing_mul_AM_SPACING_MUL_20 3 5365 5366 /**************************************************************************** 5367 * Enums: rx_x4_fec_control_cl36TxEEEStates_l 5368 */ 5369 #define rx_x4_fec_control_cl36TxEEEStates_l_TX_REFRESH 8 5370 #define rx_x4_fec_control_cl36TxEEEStates_l_TX_QUIET 4 5371 #define rx_x4_fec_control_cl36TxEEEStates_l_TX_SLEEP 2 5372 #define rx_x4_fec_control_cl36TxEEEStates_l_TX_ACTIVE 1 5373 5374 /**************************************************************************** 5375 * Enums: rx_x4_fec_control_cl36TxEEEStates_c 5376 */ 5377 #define rx_x4_fec_control_cl36TxEEEStates_c_TX_REFRESH 3 5378 #define rx_x4_fec_control_cl36TxEEEStates_c_TX_QUIET 2 5379 #define rx_x4_fec_control_cl36TxEEEStates_c_TX_SLEEP 1 5380 #define rx_x4_fec_control_cl36TxEEEStates_c_TX_ACTIVE 0 5381 5382 /**************************************************************************** 5383 * Enums: rx_x4_fec_control_cl49TxEEEStates_l 5384 */ 5385 #define rx_x4_fec_control_cl49TxEEEStates_l_SCR_RESET_2 64 5386 #define rx_x4_fec_control_cl49TxEEEStates_l_SCR_RESET_1 32 5387 #define rx_x4_fec_control_cl49TxEEEStates_l_TX_WAKE 16 5388 #define rx_x4_fec_control_cl49TxEEEStates_l_TX_REFRESH 8 5389 #define rx_x4_fec_control_cl49TxEEEStates_l_TX_QUIET 4 5390 #define rx_x4_fec_control_cl49TxEEEStates_l_TX_SLEEP 2 5391 #define rx_x4_fec_control_cl49TxEEEStates_l_TX_ACTIVE 1 5392 5393 /**************************************************************************** 5394 * Enums: rx_x4_fec_control_fec_req_enum 5395 */ 5396 #define rx_x4_fec_control_fec_req_enum_FEC_not_supported 0 5397 #define rx_x4_fec_control_fec_req_enum_FEC_supported_but_not_requested 1 5398 #define rx_x4_fec_control_fec_req_enum_invalid_setting 2 5399 #define rx_x4_fec_control_fec_req_enum_FEC_supported_and_requested 3 5400 5401 /**************************************************************************** 5402 * Enums: rx_x4_fec_control_cl73_pause_enum 5403 */ 5404 #define rx_x4_fec_control_cl73_pause_enum_No_PAUSE_ability 0 5405 #define rx_x4_fec_control_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 5406 #define rx_x4_fec_control_cl73_pause_enum_Symmetric_PAUSE_ability 1 5407 #define rx_x4_fec_control_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 5408 5409 /**************************************************************************** 5410 * Enums: rx_x4_fec_control_cl49TxEEEStates_c 5411 */ 5412 #define rx_x4_fec_control_cl49TxEEEStates_c_SCR_RESET_2 6 5413 #define rx_x4_fec_control_cl49TxEEEStates_c_SCR_RESET_1 5 5414 #define rx_x4_fec_control_cl49TxEEEStates_c_TX_WAKE 4 5415 #define rx_x4_fec_control_cl49TxEEEStates_c_TX_REFRESH 3 5416 #define rx_x4_fec_control_cl49TxEEEStates_c_TX_QUIET 2 5417 #define rx_x4_fec_control_cl49TxEEEStates_c_TX_SLEEP 1 5418 #define rx_x4_fec_control_cl49TxEEEStates_c_TX_ACTIVE 0 5419 5420 /**************************************************************************** 5421 * Enums: rx_x4_fec_control_cl36RxEEEStates_l 5422 */ 5423 #define rx_x4_fec_control_cl36RxEEEStates_l_RX_LINK_FAIL 32 5424 #define rx_x4_fec_control_cl36RxEEEStates_l_RX_WTF 16 5425 #define rx_x4_fec_control_cl36RxEEEStates_l_RX_WAKE 8 5426 #define rx_x4_fec_control_cl36RxEEEStates_l_RX_QUIET 4 5427 #define rx_x4_fec_control_cl36RxEEEStates_l_RX_SLEEP 2 5428 #define rx_x4_fec_control_cl36RxEEEStates_l_RX_ACTIVE 1 5429 5430 /**************************************************************************** 5431 * Enums: rx_x4_fec_control_cl36RxEEEStates_c 5432 */ 5433 #define rx_x4_fec_control_cl36RxEEEStates_c_RX_LINK_FAIL 5 5434 #define rx_x4_fec_control_cl36RxEEEStates_c_RX_WTF 4 5435 #define rx_x4_fec_control_cl36RxEEEStates_c_RX_WAKE 3 5436 #define rx_x4_fec_control_cl36RxEEEStates_c_RX_QUIET 2 5437 #define rx_x4_fec_control_cl36RxEEEStates_c_RX_SLEEP 1 5438 #define rx_x4_fec_control_cl36RxEEEStates_c_RX_ACTIVE 0 5439 5440 /**************************************************************************** 5441 * Enums: rx_x4_fec_control_cl49RxEEEStates_l 5442 */ 5443 #define rx_x4_fec_control_cl49RxEEEStates_l_RX_LINK_FAIL 32 5444 #define rx_x4_fec_control_cl49RxEEEStates_l_RX_WTF 16 5445 #define rx_x4_fec_control_cl49RxEEEStates_l_RX_WAKE 8 5446 #define rx_x4_fec_control_cl49RxEEEStates_l_RX_QUIET 4 5447 #define rx_x4_fec_control_cl49RxEEEStates_l_RX_SLEEP 2 5448 #define rx_x4_fec_control_cl49RxEEEStates_l_RX_ACTIVE 1 5449 5450 /**************************************************************************** 5451 * Enums: rx_x4_fec_control_cl49RxEEEStates_c 5452 */ 5453 #define rx_x4_fec_control_cl49RxEEEStates_c_RX_LINK_FAIL 5 5454 #define rx_x4_fec_control_cl49RxEEEStates_c_RX_WTF 4 5455 #define rx_x4_fec_control_cl49RxEEEStates_c_RX_WAKE 3 5456 #define rx_x4_fec_control_cl49RxEEEStates_c_RX_QUIET 2 5457 #define rx_x4_fec_control_cl49RxEEEStates_c_RX_SLEEP 1 5458 #define rx_x4_fec_control_cl49RxEEEStates_c_RX_ACTIVE 0 5459 5460 /**************************************************************************** 5461 * Enums: rx_x4_fec_control_cl48TxEEEStates_l 5462 */ 5463 #define rx_x4_fec_control_cl48TxEEEStates_l_TX_REFRESH 8 5464 #define rx_x4_fec_control_cl48TxEEEStates_l_TX_QUIET 4 5465 #define rx_x4_fec_control_cl48TxEEEStates_l_TX_SLEEP 2 5466 #define rx_x4_fec_control_cl48TxEEEStates_l_TX_ACTIVE 1 5467 5468 /**************************************************************************** 5469 * Enums: rx_x4_fec_control_cl48TxEEEStates_c 5470 */ 5471 #define rx_x4_fec_control_cl48TxEEEStates_c_TX_REFRESH 3 5472 #define rx_x4_fec_control_cl48TxEEEStates_c_TX_QUIET 2 5473 #define rx_x4_fec_control_cl48TxEEEStates_c_TX_SLEEP 1 5474 #define rx_x4_fec_control_cl48TxEEEStates_c_TX_ACTIVE 0 5475 5476 /**************************************************************************** 5477 * Enums: rx_x4_fec_control_cl48RxEEEStates_l 5478 */ 5479 #define rx_x4_fec_control_cl48RxEEEStates_l_RX_LINK_FAIL 32 5480 #define rx_x4_fec_control_cl48RxEEEStates_l_RX_WAKE 16 5481 #define rx_x4_fec_control_cl48RxEEEStates_l_RX_QUIET 8 5482 #define rx_x4_fec_control_cl48RxEEEStates_l_RX_DEACT 4 5483 #define rx_x4_fec_control_cl48RxEEEStates_l_RX_SLEEP 2 5484 #define rx_x4_fec_control_cl48RxEEEStates_l_RX_ACTIVE 1 5485 5486 /**************************************************************************** 5487 * Enums: rx_x4_fec_control_cl48RxEEEStates_c 5488 */ 5489 #define rx_x4_fec_control_cl48RxEEEStates_c_RX_LINK_FAIL 5 5490 #define rx_x4_fec_control_cl48RxEEEStates_c_RX_WAKE 4 5491 #define rx_x4_fec_control_cl48RxEEEStates_c_RX_QUIET 3 5492 #define rx_x4_fec_control_cl48RxEEEStates_c_RX_DEACT 2 5493 #define rx_x4_fec_control_cl48RxEEEStates_c_RX_SLEEP 1 5494 #define rx_x4_fec_control_cl48RxEEEStates_c_RX_ACTIVE 0 5495 5496 /**************************************************************************** 5497 * Enums: rx_x4_fec_control_IQP_Options 5498 */ 5499 #define rx_x4_fec_control_IQP_Options_i50uA 0 5500 #define rx_x4_fec_control_IQP_Options_i100uA 1 5501 #define rx_x4_fec_control_IQP_Options_i150uA 2 5502 #define rx_x4_fec_control_IQP_Options_i200uA 3 5503 #define rx_x4_fec_control_IQP_Options_i250uA 4 5504 #define rx_x4_fec_control_IQP_Options_i300uA 5 5505 #define rx_x4_fec_control_IQP_Options_i350uA 6 5506 #define rx_x4_fec_control_IQP_Options_i400uA 7 5507 #define rx_x4_fec_control_IQP_Options_i450uA 8 5508 #define rx_x4_fec_control_IQP_Options_i500uA 9 5509 #define rx_x4_fec_control_IQP_Options_i550uA 10 5510 #define rx_x4_fec_control_IQP_Options_i600uA 11 5511 #define rx_x4_fec_control_IQP_Options_i650uA 12 5512 #define rx_x4_fec_control_IQP_Options_i700uA 13 5513 #define rx_x4_fec_control_IQP_Options_i750uA 14 5514 #define rx_x4_fec_control_IQP_Options_i800uA 15 5515 5516 /**************************************************************************** 5517 * Enums: rx_x4_fec_control_IDriver_Options 5518 */ 5519 #define rx_x4_fec_control_IDriver_Options_v680mV 0 5520 #define rx_x4_fec_control_IDriver_Options_v730mV 1 5521 #define rx_x4_fec_control_IDriver_Options_v780mV 2 5522 #define rx_x4_fec_control_IDriver_Options_v830mV 3 5523 #define rx_x4_fec_control_IDriver_Options_v880mV 4 5524 #define rx_x4_fec_control_IDriver_Options_v930mV 5 5525 #define rx_x4_fec_control_IDriver_Options_v980mV 6 5526 #define rx_x4_fec_control_IDriver_Options_v1010mV 7 5527 #define rx_x4_fec_control_IDriver_Options_v1040mV 8 5528 #define rx_x4_fec_control_IDriver_Options_v1060mV 9 5529 #define rx_x4_fec_control_IDriver_Options_v1070mV 10 5530 #define rx_x4_fec_control_IDriver_Options_v1080mV 11 5531 #define rx_x4_fec_control_IDriver_Options_v1085mV 12 5532 #define rx_x4_fec_control_IDriver_Options_v1090mV 13 5533 #define rx_x4_fec_control_IDriver_Options_v1095mV 14 5534 #define rx_x4_fec_control_IDriver_Options_v1100mV 15 5535 5536 /**************************************************************************** 5537 * Enums: rx_x4_fec_control_operationModes 5538 */ 5539 #define rx_x4_fec_control_operationModes_XGXS 0 5540 #define rx_x4_fec_control_operationModes_XGXG_nCC 1 5541 #define rx_x4_fec_control_operationModes_Indlane_OS8 4 5542 #define rx_x4_fec_control_operationModes_IndLane_OS5 5 5543 #define rx_x4_fec_control_operationModes_PCI 7 5544 #define rx_x4_fec_control_operationModes_XGXS_nLQ 8 5545 #define rx_x4_fec_control_operationModes_XGXS_nLQnCC 9 5546 #define rx_x4_fec_control_operationModes_PBypass 10 5547 #define rx_x4_fec_control_operationModes_PBypass_nDSK 11 5548 #define rx_x4_fec_control_operationModes_ComboCoreMode 12 5549 #define rx_x4_fec_control_operationModes_Clocks_off 15 5550 5551 /**************************************************************************** 5552 * Enums: rx_x4_fec_control_actualSpeeds 5553 */ 5554 #define rx_x4_fec_control_actualSpeeds_dr_10M 0 5555 #define rx_x4_fec_control_actualSpeeds_dr_100M 1 5556 #define rx_x4_fec_control_actualSpeeds_dr_1G 2 5557 #define rx_x4_fec_control_actualSpeeds_dr_2p5G 3 5558 #define rx_x4_fec_control_actualSpeeds_dr_5G_X4 4 5559 #define rx_x4_fec_control_actualSpeeds_dr_6G_X4 5 5560 #define rx_x4_fec_control_actualSpeeds_dr_10G_HiG 6 5561 #define rx_x4_fec_control_actualSpeeds_dr_10G_CX4 7 5562 #define rx_x4_fec_control_actualSpeeds_dr_12G_HiG 8 5563 #define rx_x4_fec_control_actualSpeeds_dr_12p5G_X4 9 5564 #define rx_x4_fec_control_actualSpeeds_dr_13G_X4 10 5565 #define rx_x4_fec_control_actualSpeeds_dr_15G_X4 11 5566 #define rx_x4_fec_control_actualSpeeds_dr_16G_X4 12 5567 #define rx_x4_fec_control_actualSpeeds_dr_1G_KX 13 5568 #define rx_x4_fec_control_actualSpeeds_dr_10G_KX4 14 5569 #define rx_x4_fec_control_actualSpeeds_dr_10G_KR 15 5570 #define rx_x4_fec_control_actualSpeeds_dr_5G 16 5571 #define rx_x4_fec_control_actualSpeeds_dr_6p4G 17 5572 #define rx_x4_fec_control_actualSpeeds_dr_20G_X4 18 5573 #define rx_x4_fec_control_actualSpeeds_dr_21G_X4 19 5574 #define rx_x4_fec_control_actualSpeeds_dr_25G_X4 20 5575 #define rx_x4_fec_control_actualSpeeds_dr_10G_HiG_DXGXS 21 5576 #define rx_x4_fec_control_actualSpeeds_dr_10G_DXGXS 22 5577 #define rx_x4_fec_control_actualSpeeds_dr_10p5G_HiG_DXGXS 23 5578 #define rx_x4_fec_control_actualSpeeds_dr_10p5G_DXGXS 24 5579 #define rx_x4_fec_control_actualSpeeds_dr_12p773G_HiG_DXGXS 25 5580 #define rx_x4_fec_control_actualSpeeds_dr_12p773G_DXGXS 26 5581 #define rx_x4_fec_control_actualSpeeds_dr_10G_XFI 27 5582 #define rx_x4_fec_control_actualSpeeds_dr_40G 28 5583 #define rx_x4_fec_control_actualSpeeds_dr_20G_HiG_DXGXS 29 5584 #define rx_x4_fec_control_actualSpeeds_dr_20G_DXGXS 30 5585 #define rx_x4_fec_control_actualSpeeds_dr_10G_SFI 31 5586 #define rx_x4_fec_control_actualSpeeds_dr_31p5G 32 5587 #define rx_x4_fec_control_actualSpeeds_dr_32p7G 33 5588 #define rx_x4_fec_control_actualSpeeds_dr_20G_SCR 34 5589 #define rx_x4_fec_control_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 5590 #define rx_x4_fec_control_actualSpeeds_dr_10G_DXGXS_SCR 36 5591 #define rx_x4_fec_control_actualSpeeds_dr_12G_R2 37 5592 #define rx_x4_fec_control_actualSpeeds_dr_10G_X2 38 5593 #define rx_x4_fec_control_actualSpeeds_dr_40G_KR4 39 5594 #define rx_x4_fec_control_actualSpeeds_dr_40G_CR4 40 5595 #define rx_x4_fec_control_actualSpeeds_dr_100G_CR10 41 5596 #define rx_x4_fec_control_actualSpeeds_dr_15p75G_DXGXS 44 5597 #define rx_x4_fec_control_actualSpeeds_dr_20G_KR2 57 5598 #define rx_x4_fec_control_actualSpeeds_dr_20G_CR2 58 5599 5600 /**************************************************************************** 5601 * Enums: rx_x4_fec_control_actualSpeedsMisc1 5602 */ 5603 #define rx_x4_fec_control_actualSpeedsMisc1_dr_2500BRCM_X1 16 5604 #define rx_x4_fec_control_actualSpeedsMisc1_dr_5000BRCM_X4 17 5605 #define rx_x4_fec_control_actualSpeedsMisc1_dr_6000BRCM_X4 18 5606 #define rx_x4_fec_control_actualSpeedsMisc1_dr_10GHiGig_X4 19 5607 #define rx_x4_fec_control_actualSpeedsMisc1_dr_10GBASE_CX4 20 5608 #define rx_x4_fec_control_actualSpeedsMisc1_dr_12GHiGig_X4 21 5609 #define rx_x4_fec_control_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 5610 #define rx_x4_fec_control_actualSpeedsMisc1_dr_13GHiGig_X4 23 5611 #define rx_x4_fec_control_actualSpeedsMisc1_dr_15GHiGig_X4 24 5612 #define rx_x4_fec_control_actualSpeedsMisc1_dr_16GHiGig_X4 25 5613 #define rx_x4_fec_control_actualSpeedsMisc1_dr_5000BRCM_X1 26 5614 #define rx_x4_fec_control_actualSpeedsMisc1_dr_6363BRCM_X1 27 5615 #define rx_x4_fec_control_actualSpeedsMisc1_dr_20GHiGig_X4 28 5616 #define rx_x4_fec_control_actualSpeedsMisc1_dr_21GHiGig_X4 29 5617 #define rx_x4_fec_control_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 5618 #define rx_x4_fec_control_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 5619 5620 /**************************************************************************** 5621 * Enums: rx_x4_fec_control_IndLaneModes 5622 */ 5623 #define rx_x4_fec_control_IndLaneModes_SWSDR_div2 0 5624 #define rx_x4_fec_control_IndLaneModes_SWSDR_div1 1 5625 #define rx_x4_fec_control_IndLaneModes_DWSDR_div2 2 5626 #define rx_x4_fec_control_IndLaneModes_DWSDR_div1 3 5627 5628 /**************************************************************************** 5629 * Enums: rx_x4_fec_control_prbsSelect 5630 */ 5631 #define rx_x4_fec_control_prbsSelect_prbs7 0 5632 #define rx_x4_fec_control_prbsSelect_prbs15 1 5633 #define rx_x4_fec_control_prbsSelect_prbs23 2 5634 #define rx_x4_fec_control_prbsSelect_prbs31 3 5635 5636 /**************************************************************************** 5637 * Enums: rx_x4_fec_control_vcoDivider 5638 */ 5639 #define rx_x4_fec_control_vcoDivider_div32 0 5640 #define rx_x4_fec_control_vcoDivider_div36 1 5641 #define rx_x4_fec_control_vcoDivider_div40 2 5642 #define rx_x4_fec_control_vcoDivider_div42 3 5643 #define rx_x4_fec_control_vcoDivider_div48 4 5644 #define rx_x4_fec_control_vcoDivider_div50 5 5645 #define rx_x4_fec_control_vcoDivider_div52 6 5646 #define rx_x4_fec_control_vcoDivider_div54 7 5647 #define rx_x4_fec_control_vcoDivider_div60 8 5648 #define rx_x4_fec_control_vcoDivider_div64 9 5649 #define rx_x4_fec_control_vcoDivider_div66 10 5650 #define rx_x4_fec_control_vcoDivider_div68 11 5651 #define rx_x4_fec_control_vcoDivider_div70 12 5652 #define rx_x4_fec_control_vcoDivider_div80 13 5653 #define rx_x4_fec_control_vcoDivider_div92 14 5654 #define rx_x4_fec_control_vcoDivider_div100 15 5655 5656 /**************************************************************************** 5657 * Enums: rx_x4_fec_control_refClkSelect 5658 */ 5659 #define rx_x4_fec_control_refClkSelect_clk_156p25MHz 1 5660 #define rx_x4_fec_control_refClkSelect_clk_312p5Mhz 2 5661 5662 /**************************************************************************** 5663 * Enums: rx_x4_fec_control_aerMMDdevTypeSelect 5664 */ 5665 #define rx_x4_fec_control_aerMMDdevTypeSelect_combo_core 0 5666 #define rx_x4_fec_control_aerMMDdevTypeSelect_PMA_PMD 1 5667 #define rx_x4_fec_control_aerMMDdevTypeSelect_PCS 3 5668 #define rx_x4_fec_control_aerMMDdevTypeSelect_PHY 4 5669 #define rx_x4_fec_control_aerMMDdevTypeSelect_DTE 5 5670 #define rx_x4_fec_control_aerMMDdevTypeSelect_CL73_AN 7 5671 5672 /**************************************************************************** 5673 * Enums: rx_x4_fec_control_aerMMDportSelect 5674 */ 5675 #define rx_x4_fec_control_aerMMDportSelect_ln0 0 5676 #define rx_x4_fec_control_aerMMDportSelect_ln1 1 5677 #define rx_x4_fec_control_aerMMDportSelect_ln2 2 5678 #define rx_x4_fec_control_aerMMDportSelect_ln3 3 5679 #define rx_x4_fec_control_aerMMDportSelect_BCST_ln0_1_2_3 511 5680 #define rx_x4_fec_control_aerMMDportSelect_BCST_ln0_1 512 5681 #define rx_x4_fec_control_aerMMDportSelect_BCST_ln2_3 513 5682 5683 /**************************************************************************** 5684 * Enums: rx_x4_fec_control_firmwareModeSelect 5685 */ 5686 #define rx_x4_fec_control_firmwareModeSelect_DEFAULT 0 5687 #define rx_x4_fec_control_firmwareModeSelect_SFP_OPT_LR 1 5688 #define rx_x4_fec_control_firmwareModeSelect_SFP_DAC 2 5689 #define rx_x4_fec_control_firmwareModeSelect_XLAUI 3 5690 #define rx_x4_fec_control_firmwareModeSelect_LONG_CH_6G 4 5691 5692 /**************************************************************************** 5693 * Enums: rx_x4_fec_control_tempIdxSelect 5694 */ 5695 #define rx_x4_fec_control_tempIdxSelect_LTE__22p9C 15 5696 #define rx_x4_fec_control_tempIdxSelect_LTE__12p6C 14 5697 #define rx_x4_fec_control_tempIdxSelect_LTE__3p0C 13 5698 #define rx_x4_fec_control_tempIdxSelect_LTE_6p7C 12 5699 #define rx_x4_fec_control_tempIdxSelect_LTE_16p4C 11 5700 #define rx_x4_fec_control_tempIdxSelect_LTE_26p6C 10 5701 #define rx_x4_fec_control_tempIdxSelect_LTE_36p3C 9 5702 #define rx_x4_fec_control_tempIdxSelect_LTE_46p0C 8 5703 #define rx_x4_fec_control_tempIdxSelect_LTE_56p2C 7 5704 #define rx_x4_fec_control_tempIdxSelect_LTE_65p9C 6 5705 #define rx_x4_fec_control_tempIdxSelect_LTE_75p6C 5 5706 #define rx_x4_fec_control_tempIdxSelect_LTE_85p3C 4 5707 #define rx_x4_fec_control_tempIdxSelect_LTE_95p5C 3 5708 #define rx_x4_fec_control_tempIdxSelect_LTE_105p2C 2 5709 #define rx_x4_fec_control_tempIdxSelect_LTE_114p9C 1 5710 #define rx_x4_fec_control_tempIdxSelect_LTE_125p1C 0 5711 5712 /**************************************************************************** 5713 * Enums: rx_x4_fec_control_port_mode 5714 */ 5715 #define rx_x4_fec_control_port_mode_QUAD_PORT 0 5716 #define rx_x4_fec_control_port_mode_TRI_1_PORT 1 5717 #define rx_x4_fec_control_port_mode_TRI_2_PORT 2 5718 #define rx_x4_fec_control_port_mode_DUAL_PORT 3 5719 #define rx_x4_fec_control_port_mode_SINGLE_PORT 4 5720 #define rx_x4_fec_control_port_mode_SINGLE_OCTAL_PORT 5 5721 5722 /**************************************************************************** 5723 * Enums: rx_x4_fec_control_rev_letter_enum 5724 */ 5725 #define rx_x4_fec_control_rev_letter_enum_REV_A 0 5726 #define rx_x4_fec_control_rev_letter_enum_REV_B 1 5727 #define rx_x4_fec_control_rev_letter_enum_REV_C 2 5728 #define rx_x4_fec_control_rev_letter_enum_REV_D 3 5729 5730 /**************************************************************************** 5731 * Enums: rx_x4_fec_control_rev_number_enum 5732 */ 5733 #define rx_x4_fec_control_rev_number_enum_REV_0 0 5734 #define rx_x4_fec_control_rev_number_enum_REV_1 1 5735 #define rx_x4_fec_control_rev_number_enum_REV_2 2 5736 #define rx_x4_fec_control_rev_number_enum_REV_3 3 5737 #define rx_x4_fec_control_rev_number_enum_REV_4 4 5738 #define rx_x4_fec_control_rev_number_enum_REV_5 5 5739 #define rx_x4_fec_control_rev_number_enum_REV_6 6 5740 #define rx_x4_fec_control_rev_number_enum_REV_7 7 5741 5742 /**************************************************************************** 5743 * Enums: rx_x4_fec_control_bonding_enum 5744 */ 5745 #define rx_x4_fec_control_bonding_enum_WIRE_BOND 0 5746 #define rx_x4_fec_control_bonding_enum_FLIP_CHIP 1 5747 5748 /**************************************************************************** 5749 * Enums: rx_x4_fec_control_tech_process 5750 */ 5751 #define rx_x4_fec_control_tech_process_PROCESS_90NM 0 5752 #define rx_x4_fec_control_tech_process_PROCESS_65NM 1 5753 #define rx_x4_fec_control_tech_process_PROCESS_40NM 2 5754 #define rx_x4_fec_control_tech_process_PROCESS_28NM 3 5755 #define rx_x4_fec_control_tech_process_PROCESS_16NM 4 5756 5757 /**************************************************************************** 5758 * Enums: rx_x4_fec_control_model_num 5759 */ 5760 #define rx_x4_fec_control_model_num_SERDES_CL73 0 5761 #define rx_x4_fec_control_model_num_XGXS_16G 1 5762 #define rx_x4_fec_control_model_num_HYPERCORE 2 5763 #define rx_x4_fec_control_model_num_HYPERLITE 3 5764 #define rx_x4_fec_control_model_num_PCIE_G2_PIPE 4 5765 #define rx_x4_fec_control_model_num_SERDES_1p25GBd 5 5766 #define rx_x4_fec_control_model_num_SATA2 6 5767 #define rx_x4_fec_control_model_num_QSGMII 7 5768 #define rx_x4_fec_control_model_num_XGXS10G 8 5769 #define rx_x4_fec_control_model_num_WARPCORE 9 5770 #define rx_x4_fec_control_model_num_XFICORE 10 5771 #define rx_x4_fec_control_model_num_RXFI 11 5772 #define rx_x4_fec_control_model_num_WARPLITE 12 5773 #define rx_x4_fec_control_model_num_PENTACORE 13 5774 #define rx_x4_fec_control_model_num_ESM 14 5775 #define rx_x4_fec_control_model_num_QUAD_SGMII 15 5776 #define rx_x4_fec_control_model_num_WARPCORE_3 16 5777 #define rx_x4_fec_control_model_num_TSC 17 5778 #define rx_x4_fec_control_model_num_TSC4E 18 5779 #define rx_x4_fec_control_model_num_TSC12E 19 5780 #define rx_x4_fec_control_model_num_TSC4F 20 5781 #define rx_x4_fec_control_model_num_TSC4F_GEN2 21 5782 #define rx_x4_fec_control_model_num_XGXS_CL73_90NM 29 5783 #define rx_x4_fec_control_model_num_SERDES_CL73_90NM 30 5784 #define rx_x4_fec_control_model_num_WARPCORE3 32 5785 #define rx_x4_fec_control_model_num_WARPCORE4_TSC 33 5786 #define rx_x4_fec_control_model_num_RXAUI 34 5787 #define rx_x4_fec_control_model_num_TSCE_GEN3 35 5788 #define rx_x4_fec_control_model_num_TSC4F_GEN3 36 5789 #define rx_x4_fec_control_model_num_TSCBH 37 5790 5791 /**************************************************************************** 5792 * Enums: rx_x4_fec_control_payload 5793 */ 5794 #define rx_x4_fec_control_payload_REPEAT_2_BYTES 0 5795 #define rx_x4_fec_control_payload_RAMPING 1 5796 #define rx_x4_fec_control_payload_CL48_CRPAT 2 5797 #define rx_x4_fec_control_payload_CL48_CJPAT 3 5798 #define rx_x4_fec_control_payload_CL36_LONG_CRPAT 4 5799 #define rx_x4_fec_control_payload_CL36_SHORT_CRPAT 5 5800 5801 /**************************************************************************** 5802 * Enums: rx_x4_fec_control_sc 5803 */ 5804 #define rx_x4_fec_control_sc_SPEED_10G_IEEE_KR1 0 5805 #define rx_x4_fec_control_sc_SPEED_25G_IEEE_KS1_CS1 1 5806 #define rx_x4_fec_control_sc_SPEED_25G_IEEE_KR1_CR1 2 5807 #define rx_x4_fec_control_sc_SPEED_40G_IEEE_KR4 3 5808 #define rx_x4_fec_control_sc_SPEED_40G_IEEE_CR4 4 5809 #define rx_x4_fec_control_sc_SPEED_50G_IEEE_KR1_CR1 5 5810 #define rx_x4_fec_control_sc_SPEED_100G_IEEE_KR4 6 5811 #define rx_x4_fec_control_sc_SPEED_100G_IEEE_CR4 7 5812 #define rx_x4_fec_control_sc_SPEED_100G_IEEE_KR2_CR2 8 5813 #define rx_x4_fec_control_sc_SPEED_200G_IEEE_KR4_CR4 9 5814 #define rx_x4_fec_control_sc_SPEED_400G_IEEE_X8 10 5815 #define rx_x4_fec_control_sc_SPEED_CL73_IEEE_20GVCO 11 5816 #define rx_x4_fec_control_sc_SPEED_CL73_IEEE_25GVCO 12 5817 #define rx_x4_fec_control_sc_SPEED_CL73_IEEE_26GVCO 13 5818 #define rx_x4_fec_control_sc_SPEED_20G_BRCM_CR1 14 5819 #define rx_x4_fec_control_sc_SPEED_20G_BRCM_KR1 15 5820 #define rx_x4_fec_control_sc_SPEED_25G_BRCM_CR1 16 5821 #define rx_x4_fec_control_sc_SPEED_25G_BRCM_KR1 17 5822 #define rx_x4_fec_control_sc_SPEED_40G_BRCM_CR2 18 5823 #define rx_x4_fec_control_sc_SPEED_40G_BRCM_KR2 19 5824 #define rx_x4_fec_control_sc_SPEED_50G_BRCM_CR2 20 5825 #define rx_x4_fec_control_sc_SPEED_50G_BRCM_KR2 21 5826 #define rx_x4_fec_control_sc_SPEED_50G_BRCM_CR4 22 5827 #define rx_x4_fec_control_sc_SPEED_50G_BRCM_KR4 23 5828 #define rx_x4_fec_control_sc_SPEED_50G_BRCM_FEC_544_CR2_KR2 24 5829 #define rx_x4_fec_control_sc_SPEED_RESERVED_19 25 5830 #define rx_x4_fec_control_sc_SPEED_50G_BRCM_FEC_544_CR1_KR1 26 5831 #define rx_x4_fec_control_sc_SPEED_50G_BRCM_NO_FEC_CR1_KR1 27 5832 #define rx_x4_fec_control_sc_SPEED_50G_BRCM_FEC_528_CR1_KR1 28 5833 #define rx_x4_fec_control_sc_SPEED_400G_BRCM_NO_FEC_KR8_CR8 29 5834 #define rx_x4_fec_control_sc_SPEED_400G_BRCM_FEC_KR8_CR8 30 5835 #define rx_x4_fec_control_sc_SPEED_200G_BRCM_NO_FEC_KR4_CR4 31 5836 #define rx_x4_fec_control_sc_SPEED_200G_BRCM_KR4_CR4 32 5837 #define rx_x4_fec_control_sc_SPEED_100G_BRCM_KR4_CR4 33 5838 #define rx_x4_fec_control_sc_SPEED_RESERVED_22 34 5839 #define rx_x4_fec_control_sc_SPEED_100G_BRCM_FEC_528_KR2_CR2 35 5840 #define rx_x4_fec_control_sc_SPEED_100G_BRCM_NO_FEC_KR2_CR2 36 5841 #define rx_x4_fec_control_sc_SPEED_100G_BRCM_NO_FEC_X4 37 5842 5843 /**************************************************************************** 5844 * Enums: rx_x4_fec_control_t_fifo_modes 5845 */ 5846 #define rx_x4_fec_control_t_fifo_modes_T_FIFO_INSERT_NO_AM 0 5847 #define rx_x4_fec_control_t_fifo_modes_T_FIFO_INSERT_4_AM 1 5848 #define rx_x4_fec_control_t_fifo_modes_T_FIFO_INSERT_20_AM 2 5849 #define rx_x4_fec_control_t_fifo_modes_T_FIFO_INSERT_2_AM 3 5850 5851 /**************************************************************************** 5852 * Enums: rx_x4_fec_control_t_enc_modes 5853 */ 5854 #define rx_x4_fec_control_t_enc_modes_T_ENC_MODE_BYPASS 0 5855 #define rx_x4_fec_control_t_enc_modes_T_ENC_MODE_CL49 1 5856 #define rx_x4_fec_control_t_enc_modes_T_ENC_MODE_CL82 2 5857 5858 /**************************************************************************** 5859 * Enums: rx_x4_fec_control_btmx_mode 5860 */ 5861 #define rx_x4_fec_control_btmx_mode_BS_BTMX_MODE_1to1 0 5862 #define rx_x4_fec_control_btmx_mode_BS_BTMX_MODE_2to1 1 5863 #define rx_x4_fec_control_btmx_mode_BS_BTMX_MODE_5to1 2 5864 5865 /**************************************************************************** 5866 * Enums: rx_x4_fec_control_t_type_cl82 5867 */ 5868 #define rx_x4_fec_control_t_type_cl82_T_TYPE_B1 5 5869 #define rx_x4_fec_control_t_type_cl82_T_TYPE_C 4 5870 #define rx_x4_fec_control_t_type_cl82_T_TYPE_S 3 5871 #define rx_x4_fec_control_t_type_cl82_T_TYPE_T 2 5872 #define rx_x4_fec_control_t_type_cl82_T_TYPE_D 1 5873 #define rx_x4_fec_control_t_type_cl82_T_TYPE_E 0 5874 5875 /**************************************************************************** 5876 * Enums: rx_x4_fec_control_txsm_state_cl82 5877 */ 5878 #define rx_x4_fec_control_txsm_state_cl82_TX_E 4 5879 #define rx_x4_fec_control_txsm_state_cl82_TX_T 3 5880 #define rx_x4_fec_control_txsm_state_cl82_TX_D 2 5881 #define rx_x4_fec_control_txsm_state_cl82_TX_C 1 5882 #define rx_x4_fec_control_txsm_state_cl82_TX_INIT 0 5883 5884 /**************************************************************************** 5885 * Enums: rx_x4_fec_control_ltxsm_state_cl82 5886 */ 5887 #define rx_x4_fec_control_ltxsm_state_cl82_TX_E 16 5888 #define rx_x4_fec_control_ltxsm_state_cl82_TX_T 8 5889 #define rx_x4_fec_control_ltxsm_state_cl82_TX_D 4 5890 #define rx_x4_fec_control_ltxsm_state_cl82_TX_C 2 5891 #define rx_x4_fec_control_ltxsm_state_cl82_TX_INIT 1 5892 5893 /**************************************************************************** 5894 * Enums: rx_x4_fec_control_r_type_coded_cl82 5895 */ 5896 #define rx_x4_fec_control_r_type_coded_cl82_R_TYPE_B1 32 5897 #define rx_x4_fec_control_r_type_coded_cl82_R_TYPE_C 16 5898 #define rx_x4_fec_control_r_type_coded_cl82_R_TYPE_S 8 5899 #define rx_x4_fec_control_r_type_coded_cl82_R_TYPE_T 4 5900 #define rx_x4_fec_control_r_type_coded_cl82_R_TYPE_D 2 5901 #define rx_x4_fec_control_r_type_coded_cl82_R_TYPE_E 1 5902 5903 /**************************************************************************** 5904 * Enums: rx_x4_fec_control_rxsm_state_cl82 5905 */ 5906 #define rx_x4_fec_control_rxsm_state_cl82_RX_E 16 5907 #define rx_x4_fec_control_rxsm_state_cl82_RX_T 8 5908 #define rx_x4_fec_control_rxsm_state_cl82_RX_D 4 5909 #define rx_x4_fec_control_rxsm_state_cl82_RX_C 2 5910 #define rx_x4_fec_control_rxsm_state_cl82_RX_INIT 1 5911 5912 /**************************************************************************** 5913 * Enums: rx_x4_fec_control_deskew_state 5914 */ 5915 #define rx_x4_fec_control_deskew_state_ALIGN_ACQUIRED 2 5916 #define rx_x4_fec_control_deskew_state_LOSS_OF_ALIGNMENT 1 5917 5918 /**************************************************************************** 5919 * Enums: rx_x4_fec_control_os_mode_enum 5920 */ 5921 #define rx_x4_fec_control_os_mode_enum_OS_MODE_1 0 5922 #define rx_x4_fec_control_os_mode_enum_OS_MODE_2 1 5923 #define rx_x4_fec_control_os_mode_enum_OS_MODE_4 2 5924 #define rx_x4_fec_control_os_mode_enum_OS_MODE_16p5 8 5925 #define rx_x4_fec_control_os_mode_enum_OS_MODE_20p625 12 5926 5927 /**************************************************************************** 5928 * Enums: rx_x4_fec_control_scr_modes 5929 */ 5930 #define rx_x4_fec_control_scr_modes_T_SCR_MODE_BYPASS 0 5931 #define rx_x4_fec_control_scr_modes_T_SCR_MODE_CL49 1 5932 #define rx_x4_fec_control_scr_modes_T_SCR_MODE_40G_2_LANE 2 5933 #define rx_x4_fec_control_scr_modes_T_SCR_MODE_100G 3 5934 #define rx_x4_fec_control_scr_modes_T_SCR_MODE_20G 4 5935 #define rx_x4_fec_control_scr_modes_T_SCR_MODE_40G_4_LANE 5 5936 5937 /**************************************************************************** 5938 * Enums: rx_x4_fec_control_descr_modes 5939 */ 5940 #define rx_x4_fec_control_descr_modes_R_DESCR_MODE_BYPASS 0 5941 #define rx_x4_fec_control_descr_modes_R_DESCR_MODE_CL49 1 5942 #define rx_x4_fec_control_descr_modes_R_DESCR_MODE_CL82 2 5943 5944 /**************************************************************************** 5945 * Enums: rx_x4_fec_control_r_dec_tl_mode 5946 */ 5947 #define rx_x4_fec_control_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 5948 #define rx_x4_fec_control_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 5949 #define rx_x4_fec_control_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 5950 5951 /**************************************************************************** 5952 * Enums: rx_x4_fec_control_r_dec_fsm_mode 5953 */ 5954 #define rx_x4_fec_control_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 5955 #define rx_x4_fec_control_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 5956 #define rx_x4_fec_control_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 5957 5958 /**************************************************************************** 5959 * Enums: rx_x4_fec_control_r_deskew_mode 5960 */ 5961 #define rx_x4_fec_control_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 5962 #define rx_x4_fec_control_r_deskew_mode_R_DESKEW_MODE_20G 1 5963 #define rx_x4_fec_control_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 5964 #define rx_x4_fec_control_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 5965 #define rx_x4_fec_control_r_deskew_mode_R_DESKEW_MODE_100G 4 5966 #define rx_x4_fec_control_r_deskew_mode_R_DESKEW_MODE_CL49 5 5967 #define rx_x4_fec_control_r_deskew_mode_R_DESKEW_MODE_CL91_QUAD 6 5968 #define rx_x4_fec_control_r_deskew_mode_R_DESKEW_MODE_CL91_SINGLE_BRCM 7 5969 #define rx_x4_fec_control_r_deskew_mode_R_DESKEW_MODE_CL91_DUAL_BRCM 8 5970 #define rx_x4_fec_control_r_deskew_mode_R_DESKEW_MODE_CL91_FC 9 5971 5972 /**************************************************************************** 5973 * Enums: rx_x4_fec_control_bs_dist_modes 5974 */ 5975 #define rx_x4_fec_control_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 5976 #define rx_x4_fec_control_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 5977 #define rx_x4_fec_control_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 5978 #define rx_x4_fec_control_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 5979 5980 /**************************************************************************** 5981 * Enums: rx_x4_fec_control_cl49_t_type 5982 */ 5983 #define rx_x4_fec_control_cl49_t_type_BAD_T_TYPE 15 5984 #define rx_x4_fec_control_cl49_t_type_T_TYPE_B0 11 5985 #define rx_x4_fec_control_cl49_t_type_T_TYPE_OB 10 5986 #define rx_x4_fec_control_cl49_t_type_T_TYPE_B1 9 5987 #define rx_x4_fec_control_cl49_t_type_T_TYPE_DB 8 5988 #define rx_x4_fec_control_cl49_t_type_T_TYPE_FC 7 5989 #define rx_x4_fec_control_cl49_t_type_T_TYPE_TB 6 5990 #define rx_x4_fec_control_cl49_t_type_T_TYPE_LI 5 5991 #define rx_x4_fec_control_cl49_t_type_T_TYPE_C 4 5992 #define rx_x4_fec_control_cl49_t_type_T_TYPE_S 3 5993 #define rx_x4_fec_control_cl49_t_type_T_TYPE_T 2 5994 #define rx_x4_fec_control_cl49_t_type_T_TYPE_D 1 5995 #define rx_x4_fec_control_cl49_t_type_T_TYPE_E 0 5996 5997 /**************************************************************************** 5998 * Enums: rx_x4_fec_control_cl49_txsm_states 5999 */ 6000 #define rx_x4_fec_control_cl49_txsm_states_TX_LI 5 6001 #define rx_x4_fec_control_cl49_txsm_states_TX_E 4 6002 #define rx_x4_fec_control_cl49_txsm_states_TX_T 3 6003 #define rx_x4_fec_control_cl49_txsm_states_TX_D 2 6004 #define rx_x4_fec_control_cl49_txsm_states_TX_C 1 6005 #define rx_x4_fec_control_cl49_txsm_states_TX_INIT 0 6006 6007 /**************************************************************************** 6008 * Enums: rx_x4_fec_control_cl49_ltxsm_states 6009 */ 6010 #define rx_x4_fec_control_cl49_ltxsm_states_TX_LI 32 6011 #define rx_x4_fec_control_cl49_ltxsm_states_TX_E 16 6012 #define rx_x4_fec_control_cl49_ltxsm_states_TX_T 8 6013 #define rx_x4_fec_control_cl49_ltxsm_states_TX_D 4 6014 #define rx_x4_fec_control_cl49_ltxsm_states_TX_C 2 6015 #define rx_x4_fec_control_cl49_ltxsm_states_TX_INIT 1 6016 6017 /**************************************************************************** 6018 * Enums: rx_x4_fec_control_burst_error_mode 6019 */ 6020 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_11_BITS 0 6021 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_16_BITS 1 6022 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_17_BITS 2 6023 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_18_BITS 3 6024 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_19_BITS 4 6025 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_20_BITS 5 6026 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_21_BITS 6 6027 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_22_BITS 7 6028 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_23_BITS 8 6029 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_24_BITS 9 6030 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_25_BITS 10 6031 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_26_BITS 11 6032 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_27_BITS 12 6033 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_28_BITS 13 6034 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_29_BITS 14 6035 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_30_BITS 15 6036 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_31_BITS 16 6037 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_32_BITS 17 6038 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_33_BITS 18 6039 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_34_BITS 19 6040 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_35_BITS 20 6041 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_36_BITS 21 6042 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_37_BITS 22 6043 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_38_BITS 23 6044 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_39_BITS 24 6045 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_40_BITS 25 6046 #define rx_x4_fec_control_burst_error_mode_BURST_ERROR_41_BITS 26 6047 6048 /**************************************************************************** 6049 * Enums: rx_x4_fec_control_bermon_state 6050 */ 6051 #define rx_x4_fec_control_bermon_state_HI_BER 4 6052 #define rx_x4_fec_control_bermon_state_GOOD_BER 3 6053 #define rx_x4_fec_control_bermon_state_BER_TEST_SH 2 6054 #define rx_x4_fec_control_bermon_state_START_TIMER 1 6055 #define rx_x4_fec_control_bermon_state_BER_MT_INIT 0 6056 6057 /**************************************************************************** 6058 * Enums: rx_x4_fec_control_rxsm_state_cl49 6059 */ 6060 #define rx_x4_fec_control_rxsm_state_cl49_RX_LI 32 6061 #define rx_x4_fec_control_rxsm_state_cl49_RX_E 16 6062 #define rx_x4_fec_control_rxsm_state_cl49_RX_T 8 6063 #define rx_x4_fec_control_rxsm_state_cl49_RX_D 4 6064 #define rx_x4_fec_control_rxsm_state_cl49_RX_C 2 6065 #define rx_x4_fec_control_rxsm_state_cl49_RX_INIT 1 6066 6067 /**************************************************************************** 6068 * Enums: rx_x4_fec_control_r_type 6069 */ 6070 #define rx_x4_fec_control_r_type_BAD_R_TYPE 15 6071 #define rx_x4_fec_control_r_type_R_TYPE_B0 11 6072 #define rx_x4_fec_control_r_type_R_TYPE_OB 10 6073 #define rx_x4_fec_control_r_type_R_TYPE_B1 9 6074 #define rx_x4_fec_control_r_type_R_TYPE_DB 8 6075 #define rx_x4_fec_control_r_type_R_TYPE_FC 7 6076 #define rx_x4_fec_control_r_type_R_TYPE_TB 6 6077 #define rx_x4_fec_control_r_type_R_TYPE_LI 5 6078 #define rx_x4_fec_control_r_type_R_TYPE_C 4 6079 #define rx_x4_fec_control_r_type_R_TYPE_S 3 6080 #define rx_x4_fec_control_r_type_R_TYPE_T 2 6081 #define rx_x4_fec_control_r_type_R_TYPE_D 1 6082 #define rx_x4_fec_control_r_type_R_TYPE_E 0 6083 6084 /**************************************************************************** 6085 * Enums: rx_x4_fec_control_am_lock_state 6086 */ 6087 #define rx_x4_fec_control_am_lock_state_INVALID_AM 512 6088 #define rx_x4_fec_control_am_lock_state_GOOD_AM 256 6089 #define rx_x4_fec_control_am_lock_state_COMP_AM 128 6090 #define rx_x4_fec_control_am_lock_state_TIMER_2 64 6091 #define rx_x4_fec_control_am_lock_state_AM_2_GOOD 32 6092 #define rx_x4_fec_control_am_lock_state_COMP_2ND 16 6093 #define rx_x4_fec_control_am_lock_state_TIMER_1 8 6094 #define rx_x4_fec_control_am_lock_state_FIND_1ST 4 6095 #define rx_x4_fec_control_am_lock_state_AM_RESET_CNT 2 6096 #define rx_x4_fec_control_am_lock_state_AM_LOCK_INIT 1 6097 6098 /**************************************************************************** 6099 * Enums: rx_x4_fec_control_msg_selector 6100 */ 6101 #define rx_x4_fec_control_msg_selector_RESERVED 0 6102 #define rx_x4_fec_control_msg_selector_VALUE_802p3 1 6103 #define rx_x4_fec_control_msg_selector_VALUE_802p9 2 6104 #define rx_x4_fec_control_msg_selector_VALUE_802p5 3 6105 #define rx_x4_fec_control_msg_selector_VALUE_1394 4 6106 6107 /**************************************************************************** 6108 * Enums: rx_x4_fec_control_synce_enum_stage1 6109 */ 6110 #define rx_x4_fec_control_synce_enum_stage1_SYNCE_NO_DIV 0 6111 #define rx_x4_fec_control_synce_enum_stage1_SYNCE_DIV_7 1 6112 #define rx_x4_fec_control_synce_enum_stage1_SYNCE_DIV_11 2 6113 6114 /**************************************************************************** 6115 * Enums: rx_x4_fec_control_synce_enum_stage0 6116 */ 6117 #define rx_x4_fec_control_synce_enum_stage0_SYNCE_NO_DIV 0 6118 #define rx_x4_fec_control_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 6119 #define rx_x4_fec_control_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 6120 6121 /**************************************************************************** 6122 * Enums: rx_x4_fec_control_cl91_sync_state 6123 */ 6124 #define rx_x4_fec_control_cl91_sync_state_FIND_1ST 0 6125 #define rx_x4_fec_control_cl91_sync_state_COUNT_NEXT 1 6126 #define rx_x4_fec_control_cl91_sync_state_COMP_2ND 2 6127 #define rx_x4_fec_control_cl91_sync_state_TWO_GOOD 3 6128 6129 /**************************************************************************** 6130 * Enums: rx_x4_fec_control_RS_FEC_sync_state 6131 */ 6132 #define rx_x4_fec_control_RS_FEC_sync_state_LOCK_INIT 0 6133 #define rx_x4_fec_control_RS_FEC_sync_state_FIND_1ST 1 6134 #define rx_x4_fec_control_RS_FEC_sync_state_COUNT_NEXT 2 6135 #define rx_x4_fec_control_RS_FEC_sync_state_COMP_2ND 3 6136 #define rx_x4_fec_control_RS_FEC_sync_state_TWO_GOOD 4 6137 6138 /**************************************************************************** 6139 * Enums: rx_x4_fec_control_cl91_algn_state 6140 */ 6141 #define rx_x4_fec_control_cl91_algn_state_LOSS_OF_ALIGNMENT 0 6142 #define rx_x4_fec_control_cl91_algn_state_DESKEW 1 6143 #define rx_x4_fec_control_cl91_algn_state_DESKEW_FAIL 2 6144 #define rx_x4_fec_control_cl91_algn_state_ALIGN_ACQUIRED 3 6145 #define rx_x4_fec_control_cl91_algn_state_CW_GOOD 4 6146 #define rx_x4_fec_control_cl91_algn_state_CW_BAD 5 6147 #define rx_x4_fec_control_cl91_algn_state_THREE_BAD 6 6148 6149 /**************************************************************************** 6150 * Enums: rx_x4_fec_control_RS_FEC_algn_state 6151 */ 6152 #define rx_x4_fec_control_RS_FEC_algn_state_LOSS_OF_ALIGNMENT 0 6153 #define rx_x4_fec_control_RS_FEC_algn_state_DESKEW 1 6154 #define rx_x4_fec_control_RS_FEC_algn_state_DESKEW_FAIL 2 6155 #define rx_x4_fec_control_RS_FEC_algn_state_ALIGN_ACQUIRED 3 6156 #define rx_x4_fec_control_RS_FEC_algn_state_CW_GOOD 4 6157 #define rx_x4_fec_control_RS_FEC_algn_state_CW_BAD 5 6158 #define rx_x4_fec_control_RS_FEC_algn_state_THREE_BAD 6 6159 6160 /**************************************************************************** 6161 * Enums: rx_x4_fec_control_fec_sel_override 6162 */ 6163 #define rx_x4_fec_control_fec_sel_override_NO_OVERRIDE 0 6164 #define rx_x4_fec_control_fec_sel_override_NO_FEC 1 6165 #define rx_x4_fec_control_fec_sel_override_FEC_CL74 2 6166 #define rx_x4_fec_control_fec_sel_override_FEC_CL91 3 6167 6168 /**************************************************************************** 6169 * Enums: rx_x4_fec_control_cl91_blksync_mode 6170 */ 6171 #define rx_x4_fec_control_cl91_blksync_mode_R_BLKSYNC_NO_CL91_FEC 0 6172 #define rx_x4_fec_control_cl91_blksync_mode_R_BLKSYNC_CL91_QUAD_LANE_FEC 1 6173 #define rx_x4_fec_control_cl91_blksync_mode_R_BLKSYNC_CL91_DUAL_LANE_FEC 2 6174 #define rx_x4_fec_control_cl91_blksync_mode_R_BLKSYNC_CL91_SINGLE_LANE_FEC 3 6175 #define rx_x4_fec_control_cl91_blksync_mode_R_BLKSYNC_CL91_FC_FEC 4 6176 6177 /**************************************************************************** 6178 * Enums: rx_x4_fec_control_r_merge_mode 6179 */ 6180 #define rx_x4_fec_control_r_merge_mode_R_MERGE_MODE_BYPASS 0 6181 #define rx_x4_fec_control_r_merge_mode_R_MERGE_MODE_CL91_FC 1 6182 #define rx_x4_fec_control_r_merge_mode_R_MERGE_MODE_CL91_SINGLE_LANE 2 6183 #define rx_x4_fec_control_r_merge_mode_R_MERGE_MODE_CL91_DUAL_LANE 3 6184 #define rx_x4_fec_control_r_merge_mode_R_MERGE_MODE_CL91_QUAD_LANE 4 6185 6186 /**************************************************************************** 6187 * Enums: rx_x4_fec_control_r_tc_mode 6188 */ 6189 #define rx_x4_fec_control_r_tc_mode_R_TC_MODE_SINGLE 0 6190 #define rx_x4_fec_control_r_tc_mode_R_TC_MODE_DUAL 1 6191 #define rx_x4_fec_control_r_tc_mode_R_TC_MODE_QUAD 2 6192 6193 /**************************************************************************** 6194 * Enums: rx_x4_fec_control_r_tc_out_mode 6195 */ 6196 #define rx_x4_fec_control_r_tc_out_mode_R_TC_OUT_MODE_SINGLE 0 6197 #define rx_x4_fec_control_r_tc_out_mode_R_TC_OUT_MODE_DUAL 1 6198 #define rx_x4_fec_control_r_tc_out_mode_R_TC_OUT_MODE_QUAD 2 6199 6200 /**************************************************************************** 6201 * Enums: rx_x4_fec_control_cl91_fec_mode 6202 */ 6203 #define rx_x4_fec_control_cl91_fec_mode_NO_CL91_FEC 0 6204 #define rx_x4_fec_control_cl91_fec_mode_CL91_SINGLE_LANE_FC 1 6205 #define rx_x4_fec_control_cl91_fec_mode_CL91_SINGLE_LANE_BRCM_PROP 2 6206 #define rx_x4_fec_control_cl91_fec_mode_CL91_DUAL_LANE_BRCM_PROP 3 6207 #define rx_x4_fec_control_cl91_fec_mode_CL91_QUAD_LANE 4 6208 #define rx_x4_fec_control_cl91_fec_mode_IEEE_25G_CL91_SINGLE_LANE 5 6209 6210 /**************************************************************************** 6211 * Enums: rx_x4_fec_control_RS_FEC_fec_mode 6212 */ 6213 #define rx_x4_fec_control_RS_FEC_fec_mode_NO_RS_FEC_FEC 0 6214 #define rx_x4_fec_control_RS_FEC_fec_mode_N_A 1 6215 #define rx_x4_fec_control_RS_FEC_fec_mode_RS_FEC_SINGLE_LANE_BRCM_PROP 2 6216 #define rx_x4_fec_control_RS_FEC_fec_mode_RS_FEC_DUAL_LANE_BRCM_PROP 3 6217 #define rx_x4_fec_control_RS_FEC_fec_mode_RS_FEC_QUAD_LANE 4 6218 #define rx_x4_fec_control_RS_FEC_fec_mode_IEEE_25G_RS_FEC_SINGLE_LANE 5 6219 6220 /**************************************************************************** 6221 * Enums: rx_x4_fec_control_am_spacing_mul 6222 */ 6223 #define rx_x4_fec_control_am_spacing_mul_AM_SPACING_MUL_2 0 6224 #define rx_x4_fec_control_am_spacing_mul_AM_SPACING_MUL_4 1 6225 #define rx_x4_fec_control_am_spacing_mul_AM_SPACING_MUL_5 2 6226 #define rx_x4_fec_control_am_spacing_mul_AM_SPACING_MUL_20 3 6227 6228 /**************************************************************************** 6229 * Enums: rx_x4_rs_fec_status0_cl36TxEEEStates_l 6230 */ 6231 #define rx_x4_rs_fec_status0_cl36TxEEEStates_l_TX_REFRESH 8 6232 #define rx_x4_rs_fec_status0_cl36TxEEEStates_l_TX_QUIET 4 6233 #define rx_x4_rs_fec_status0_cl36TxEEEStates_l_TX_SLEEP 2 6234 #define rx_x4_rs_fec_status0_cl36TxEEEStates_l_TX_ACTIVE 1 6235 6236 /**************************************************************************** 6237 * Enums: rx_x4_rs_fec_status0_cl36TxEEEStates_c 6238 */ 6239 #define rx_x4_rs_fec_status0_cl36TxEEEStates_c_TX_REFRESH 3 6240 #define rx_x4_rs_fec_status0_cl36TxEEEStates_c_TX_QUIET 2 6241 #define rx_x4_rs_fec_status0_cl36TxEEEStates_c_TX_SLEEP 1 6242 #define rx_x4_rs_fec_status0_cl36TxEEEStates_c_TX_ACTIVE 0 6243 6244 /**************************************************************************** 6245 * Enums: rx_x4_rs_fec_status0_cl49TxEEEStates_l 6246 */ 6247 #define rx_x4_rs_fec_status0_cl49TxEEEStates_l_SCR_RESET_2 64 6248 #define rx_x4_rs_fec_status0_cl49TxEEEStates_l_SCR_RESET_1 32 6249 #define rx_x4_rs_fec_status0_cl49TxEEEStates_l_TX_WAKE 16 6250 #define rx_x4_rs_fec_status0_cl49TxEEEStates_l_TX_REFRESH 8 6251 #define rx_x4_rs_fec_status0_cl49TxEEEStates_l_TX_QUIET 4 6252 #define rx_x4_rs_fec_status0_cl49TxEEEStates_l_TX_SLEEP 2 6253 #define rx_x4_rs_fec_status0_cl49TxEEEStates_l_TX_ACTIVE 1 6254 6255 /**************************************************************************** 6256 * Enums: rx_x4_rs_fec_status0_fec_req_enum 6257 */ 6258 #define rx_x4_rs_fec_status0_fec_req_enum_FEC_not_supported 0 6259 #define rx_x4_rs_fec_status0_fec_req_enum_FEC_supported_but_not_requested 1 6260 #define rx_x4_rs_fec_status0_fec_req_enum_invalid_setting 2 6261 #define rx_x4_rs_fec_status0_fec_req_enum_FEC_supported_and_requested 3 6262 6263 /**************************************************************************** 6264 * Enums: rx_x4_rs_fec_status0_cl73_pause_enum 6265 */ 6266 #define rx_x4_rs_fec_status0_cl73_pause_enum_No_PAUSE_ability 0 6267 #define rx_x4_rs_fec_status0_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 6268 #define rx_x4_rs_fec_status0_cl73_pause_enum_Symmetric_PAUSE_ability 1 6269 #define rx_x4_rs_fec_status0_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 6270 6271 /**************************************************************************** 6272 * Enums: rx_x4_rs_fec_status0_cl49TxEEEStates_c 6273 */ 6274 #define rx_x4_rs_fec_status0_cl49TxEEEStates_c_SCR_RESET_2 6 6275 #define rx_x4_rs_fec_status0_cl49TxEEEStates_c_SCR_RESET_1 5 6276 #define rx_x4_rs_fec_status0_cl49TxEEEStates_c_TX_WAKE 4 6277 #define rx_x4_rs_fec_status0_cl49TxEEEStates_c_TX_REFRESH 3 6278 #define rx_x4_rs_fec_status0_cl49TxEEEStates_c_TX_QUIET 2 6279 #define rx_x4_rs_fec_status0_cl49TxEEEStates_c_TX_SLEEP 1 6280 #define rx_x4_rs_fec_status0_cl49TxEEEStates_c_TX_ACTIVE 0 6281 6282 /**************************************************************************** 6283 * Enums: rx_x4_rs_fec_status0_cl36RxEEEStates_l 6284 */ 6285 #define rx_x4_rs_fec_status0_cl36RxEEEStates_l_RX_LINK_FAIL 32 6286 #define rx_x4_rs_fec_status0_cl36RxEEEStates_l_RX_WTF 16 6287 #define rx_x4_rs_fec_status0_cl36RxEEEStates_l_RX_WAKE 8 6288 #define rx_x4_rs_fec_status0_cl36RxEEEStates_l_RX_QUIET 4 6289 #define rx_x4_rs_fec_status0_cl36RxEEEStates_l_RX_SLEEP 2 6290 #define rx_x4_rs_fec_status0_cl36RxEEEStates_l_RX_ACTIVE 1 6291 6292 /**************************************************************************** 6293 * Enums: rx_x4_rs_fec_status0_cl36RxEEEStates_c 6294 */ 6295 #define rx_x4_rs_fec_status0_cl36RxEEEStates_c_RX_LINK_FAIL 5 6296 #define rx_x4_rs_fec_status0_cl36RxEEEStates_c_RX_WTF 4 6297 #define rx_x4_rs_fec_status0_cl36RxEEEStates_c_RX_WAKE 3 6298 #define rx_x4_rs_fec_status0_cl36RxEEEStates_c_RX_QUIET 2 6299 #define rx_x4_rs_fec_status0_cl36RxEEEStates_c_RX_SLEEP 1 6300 #define rx_x4_rs_fec_status0_cl36RxEEEStates_c_RX_ACTIVE 0 6301 6302 /**************************************************************************** 6303 * Enums: rx_x4_rs_fec_status0_cl49RxEEEStates_l 6304 */ 6305 #define rx_x4_rs_fec_status0_cl49RxEEEStates_l_RX_LINK_FAIL 32 6306 #define rx_x4_rs_fec_status0_cl49RxEEEStates_l_RX_WTF 16 6307 #define rx_x4_rs_fec_status0_cl49RxEEEStates_l_RX_WAKE 8 6308 #define rx_x4_rs_fec_status0_cl49RxEEEStates_l_RX_QUIET 4 6309 #define rx_x4_rs_fec_status0_cl49RxEEEStates_l_RX_SLEEP 2 6310 #define rx_x4_rs_fec_status0_cl49RxEEEStates_l_RX_ACTIVE 1 6311 6312 /**************************************************************************** 6313 * Enums: rx_x4_rs_fec_status0_cl49RxEEEStates_c 6314 */ 6315 #define rx_x4_rs_fec_status0_cl49RxEEEStates_c_RX_LINK_FAIL 5 6316 #define rx_x4_rs_fec_status0_cl49RxEEEStates_c_RX_WTF 4 6317 #define rx_x4_rs_fec_status0_cl49RxEEEStates_c_RX_WAKE 3 6318 #define rx_x4_rs_fec_status0_cl49RxEEEStates_c_RX_QUIET 2 6319 #define rx_x4_rs_fec_status0_cl49RxEEEStates_c_RX_SLEEP 1 6320 #define rx_x4_rs_fec_status0_cl49RxEEEStates_c_RX_ACTIVE 0 6321 6322 /**************************************************************************** 6323 * Enums: rx_x4_rs_fec_status0_cl48TxEEEStates_l 6324 */ 6325 #define rx_x4_rs_fec_status0_cl48TxEEEStates_l_TX_REFRESH 8 6326 #define rx_x4_rs_fec_status0_cl48TxEEEStates_l_TX_QUIET 4 6327 #define rx_x4_rs_fec_status0_cl48TxEEEStates_l_TX_SLEEP 2 6328 #define rx_x4_rs_fec_status0_cl48TxEEEStates_l_TX_ACTIVE 1 6329 6330 /**************************************************************************** 6331 * Enums: rx_x4_rs_fec_status0_cl48TxEEEStates_c 6332 */ 6333 #define rx_x4_rs_fec_status0_cl48TxEEEStates_c_TX_REFRESH 3 6334 #define rx_x4_rs_fec_status0_cl48TxEEEStates_c_TX_QUIET 2 6335 #define rx_x4_rs_fec_status0_cl48TxEEEStates_c_TX_SLEEP 1 6336 #define rx_x4_rs_fec_status0_cl48TxEEEStates_c_TX_ACTIVE 0 6337 6338 /**************************************************************************** 6339 * Enums: rx_x4_rs_fec_status0_cl48RxEEEStates_l 6340 */ 6341 #define rx_x4_rs_fec_status0_cl48RxEEEStates_l_RX_LINK_FAIL 32 6342 #define rx_x4_rs_fec_status0_cl48RxEEEStates_l_RX_WAKE 16 6343 #define rx_x4_rs_fec_status0_cl48RxEEEStates_l_RX_QUIET 8 6344 #define rx_x4_rs_fec_status0_cl48RxEEEStates_l_RX_DEACT 4 6345 #define rx_x4_rs_fec_status0_cl48RxEEEStates_l_RX_SLEEP 2 6346 #define rx_x4_rs_fec_status0_cl48RxEEEStates_l_RX_ACTIVE 1 6347 6348 /**************************************************************************** 6349 * Enums: rx_x4_rs_fec_status0_cl48RxEEEStates_c 6350 */ 6351 #define rx_x4_rs_fec_status0_cl48RxEEEStates_c_RX_LINK_FAIL 5 6352 #define rx_x4_rs_fec_status0_cl48RxEEEStates_c_RX_WAKE 4 6353 #define rx_x4_rs_fec_status0_cl48RxEEEStates_c_RX_QUIET 3 6354 #define rx_x4_rs_fec_status0_cl48RxEEEStates_c_RX_DEACT 2 6355 #define rx_x4_rs_fec_status0_cl48RxEEEStates_c_RX_SLEEP 1 6356 #define rx_x4_rs_fec_status0_cl48RxEEEStates_c_RX_ACTIVE 0 6357 6358 /**************************************************************************** 6359 * Enums: rx_x4_rs_fec_status0_IQP_Options 6360 */ 6361 #define rx_x4_rs_fec_status0_IQP_Options_i50uA 0 6362 #define rx_x4_rs_fec_status0_IQP_Options_i100uA 1 6363 #define rx_x4_rs_fec_status0_IQP_Options_i150uA 2 6364 #define rx_x4_rs_fec_status0_IQP_Options_i200uA 3 6365 #define rx_x4_rs_fec_status0_IQP_Options_i250uA 4 6366 #define rx_x4_rs_fec_status0_IQP_Options_i300uA 5 6367 #define rx_x4_rs_fec_status0_IQP_Options_i350uA 6 6368 #define rx_x4_rs_fec_status0_IQP_Options_i400uA 7 6369 #define rx_x4_rs_fec_status0_IQP_Options_i450uA 8 6370 #define rx_x4_rs_fec_status0_IQP_Options_i500uA 9 6371 #define rx_x4_rs_fec_status0_IQP_Options_i550uA 10 6372 #define rx_x4_rs_fec_status0_IQP_Options_i600uA 11 6373 #define rx_x4_rs_fec_status0_IQP_Options_i650uA 12 6374 #define rx_x4_rs_fec_status0_IQP_Options_i700uA 13 6375 #define rx_x4_rs_fec_status0_IQP_Options_i750uA 14 6376 #define rx_x4_rs_fec_status0_IQP_Options_i800uA 15 6377 6378 /**************************************************************************** 6379 * Enums: rx_x4_rs_fec_status0_IDriver_Options 6380 */ 6381 #define rx_x4_rs_fec_status0_IDriver_Options_v680mV 0 6382 #define rx_x4_rs_fec_status0_IDriver_Options_v730mV 1 6383 #define rx_x4_rs_fec_status0_IDriver_Options_v780mV 2 6384 #define rx_x4_rs_fec_status0_IDriver_Options_v830mV 3 6385 #define rx_x4_rs_fec_status0_IDriver_Options_v880mV 4 6386 #define rx_x4_rs_fec_status0_IDriver_Options_v930mV 5 6387 #define rx_x4_rs_fec_status0_IDriver_Options_v980mV 6 6388 #define rx_x4_rs_fec_status0_IDriver_Options_v1010mV 7 6389 #define rx_x4_rs_fec_status0_IDriver_Options_v1040mV 8 6390 #define rx_x4_rs_fec_status0_IDriver_Options_v1060mV 9 6391 #define rx_x4_rs_fec_status0_IDriver_Options_v1070mV 10 6392 #define rx_x4_rs_fec_status0_IDriver_Options_v1080mV 11 6393 #define rx_x4_rs_fec_status0_IDriver_Options_v1085mV 12 6394 #define rx_x4_rs_fec_status0_IDriver_Options_v1090mV 13 6395 #define rx_x4_rs_fec_status0_IDriver_Options_v1095mV 14 6396 #define rx_x4_rs_fec_status0_IDriver_Options_v1100mV 15 6397 6398 /**************************************************************************** 6399 * Enums: rx_x4_rs_fec_status0_operationModes 6400 */ 6401 #define rx_x4_rs_fec_status0_operationModes_XGXS 0 6402 #define rx_x4_rs_fec_status0_operationModes_XGXG_nCC 1 6403 #define rx_x4_rs_fec_status0_operationModes_Indlane_OS8 4 6404 #define rx_x4_rs_fec_status0_operationModes_IndLane_OS5 5 6405 #define rx_x4_rs_fec_status0_operationModes_PCI 7 6406 #define rx_x4_rs_fec_status0_operationModes_XGXS_nLQ 8 6407 #define rx_x4_rs_fec_status0_operationModes_XGXS_nLQnCC 9 6408 #define rx_x4_rs_fec_status0_operationModes_PBypass 10 6409 #define rx_x4_rs_fec_status0_operationModes_PBypass_nDSK 11 6410 #define rx_x4_rs_fec_status0_operationModes_ComboCoreMode 12 6411 #define rx_x4_rs_fec_status0_operationModes_Clocks_off 15 6412 6413 /**************************************************************************** 6414 * Enums: rx_x4_rs_fec_status0_actualSpeeds 6415 */ 6416 #define rx_x4_rs_fec_status0_actualSpeeds_dr_10M 0 6417 #define rx_x4_rs_fec_status0_actualSpeeds_dr_100M 1 6418 #define rx_x4_rs_fec_status0_actualSpeeds_dr_1G 2 6419 #define rx_x4_rs_fec_status0_actualSpeeds_dr_2p5G 3 6420 #define rx_x4_rs_fec_status0_actualSpeeds_dr_5G_X4 4 6421 #define rx_x4_rs_fec_status0_actualSpeeds_dr_6G_X4 5 6422 #define rx_x4_rs_fec_status0_actualSpeeds_dr_10G_HiG 6 6423 #define rx_x4_rs_fec_status0_actualSpeeds_dr_10G_CX4 7 6424 #define rx_x4_rs_fec_status0_actualSpeeds_dr_12G_HiG 8 6425 #define rx_x4_rs_fec_status0_actualSpeeds_dr_12p5G_X4 9 6426 #define rx_x4_rs_fec_status0_actualSpeeds_dr_13G_X4 10 6427 #define rx_x4_rs_fec_status0_actualSpeeds_dr_15G_X4 11 6428 #define rx_x4_rs_fec_status0_actualSpeeds_dr_16G_X4 12 6429 #define rx_x4_rs_fec_status0_actualSpeeds_dr_1G_KX 13 6430 #define rx_x4_rs_fec_status0_actualSpeeds_dr_10G_KX4 14 6431 #define rx_x4_rs_fec_status0_actualSpeeds_dr_10G_KR 15 6432 #define rx_x4_rs_fec_status0_actualSpeeds_dr_5G 16 6433 #define rx_x4_rs_fec_status0_actualSpeeds_dr_6p4G 17 6434 #define rx_x4_rs_fec_status0_actualSpeeds_dr_20G_X4 18 6435 #define rx_x4_rs_fec_status0_actualSpeeds_dr_21G_X4 19 6436 #define rx_x4_rs_fec_status0_actualSpeeds_dr_25G_X4 20 6437 #define rx_x4_rs_fec_status0_actualSpeeds_dr_10G_HiG_DXGXS 21 6438 #define rx_x4_rs_fec_status0_actualSpeeds_dr_10G_DXGXS 22 6439 #define rx_x4_rs_fec_status0_actualSpeeds_dr_10p5G_HiG_DXGXS 23 6440 #define rx_x4_rs_fec_status0_actualSpeeds_dr_10p5G_DXGXS 24 6441 #define rx_x4_rs_fec_status0_actualSpeeds_dr_12p773G_HiG_DXGXS 25 6442 #define rx_x4_rs_fec_status0_actualSpeeds_dr_12p773G_DXGXS 26 6443 #define rx_x4_rs_fec_status0_actualSpeeds_dr_10G_XFI 27 6444 #define rx_x4_rs_fec_status0_actualSpeeds_dr_40G 28 6445 #define rx_x4_rs_fec_status0_actualSpeeds_dr_20G_HiG_DXGXS 29 6446 #define rx_x4_rs_fec_status0_actualSpeeds_dr_20G_DXGXS 30 6447 #define rx_x4_rs_fec_status0_actualSpeeds_dr_10G_SFI 31 6448 #define rx_x4_rs_fec_status0_actualSpeeds_dr_31p5G 32 6449 #define rx_x4_rs_fec_status0_actualSpeeds_dr_32p7G 33 6450 #define rx_x4_rs_fec_status0_actualSpeeds_dr_20G_SCR 34 6451 #define rx_x4_rs_fec_status0_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 6452 #define rx_x4_rs_fec_status0_actualSpeeds_dr_10G_DXGXS_SCR 36 6453 #define rx_x4_rs_fec_status0_actualSpeeds_dr_12G_R2 37 6454 #define rx_x4_rs_fec_status0_actualSpeeds_dr_10G_X2 38 6455 #define rx_x4_rs_fec_status0_actualSpeeds_dr_40G_KR4 39 6456 #define rx_x4_rs_fec_status0_actualSpeeds_dr_40G_CR4 40 6457 #define rx_x4_rs_fec_status0_actualSpeeds_dr_100G_CR10 41 6458 #define rx_x4_rs_fec_status0_actualSpeeds_dr_15p75G_DXGXS 44 6459 #define rx_x4_rs_fec_status0_actualSpeeds_dr_20G_KR2 57 6460 #define rx_x4_rs_fec_status0_actualSpeeds_dr_20G_CR2 58 6461 6462 /**************************************************************************** 6463 * Enums: rx_x4_rs_fec_status0_actualSpeedsMisc1 6464 */ 6465 #define rx_x4_rs_fec_status0_actualSpeedsMisc1_dr_2500BRCM_X1 16 6466 #define rx_x4_rs_fec_status0_actualSpeedsMisc1_dr_5000BRCM_X4 17 6467 #define rx_x4_rs_fec_status0_actualSpeedsMisc1_dr_6000BRCM_X4 18 6468 #define rx_x4_rs_fec_status0_actualSpeedsMisc1_dr_10GHiGig_X4 19 6469 #define rx_x4_rs_fec_status0_actualSpeedsMisc1_dr_10GBASE_CX4 20 6470 #define rx_x4_rs_fec_status0_actualSpeedsMisc1_dr_12GHiGig_X4 21 6471 #define rx_x4_rs_fec_status0_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 6472 #define rx_x4_rs_fec_status0_actualSpeedsMisc1_dr_13GHiGig_X4 23 6473 #define rx_x4_rs_fec_status0_actualSpeedsMisc1_dr_15GHiGig_X4 24 6474 #define rx_x4_rs_fec_status0_actualSpeedsMisc1_dr_16GHiGig_X4 25 6475 #define rx_x4_rs_fec_status0_actualSpeedsMisc1_dr_5000BRCM_X1 26 6476 #define rx_x4_rs_fec_status0_actualSpeedsMisc1_dr_6363BRCM_X1 27 6477 #define rx_x4_rs_fec_status0_actualSpeedsMisc1_dr_20GHiGig_X4 28 6478 #define rx_x4_rs_fec_status0_actualSpeedsMisc1_dr_21GHiGig_X4 29 6479 #define rx_x4_rs_fec_status0_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 6480 #define rx_x4_rs_fec_status0_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 6481 6482 /**************************************************************************** 6483 * Enums: rx_x4_rs_fec_status0_IndLaneModes 6484 */ 6485 #define rx_x4_rs_fec_status0_IndLaneModes_SWSDR_div2 0 6486 #define rx_x4_rs_fec_status0_IndLaneModes_SWSDR_div1 1 6487 #define rx_x4_rs_fec_status0_IndLaneModes_DWSDR_div2 2 6488 #define rx_x4_rs_fec_status0_IndLaneModes_DWSDR_div1 3 6489 6490 /**************************************************************************** 6491 * Enums: rx_x4_rs_fec_status0_prbsSelect 6492 */ 6493 #define rx_x4_rs_fec_status0_prbsSelect_prbs7 0 6494 #define rx_x4_rs_fec_status0_prbsSelect_prbs15 1 6495 #define rx_x4_rs_fec_status0_prbsSelect_prbs23 2 6496 #define rx_x4_rs_fec_status0_prbsSelect_prbs31 3 6497 6498 /**************************************************************************** 6499 * Enums: rx_x4_rs_fec_status0_vcoDivider 6500 */ 6501 #define rx_x4_rs_fec_status0_vcoDivider_div32 0 6502 #define rx_x4_rs_fec_status0_vcoDivider_div36 1 6503 #define rx_x4_rs_fec_status0_vcoDivider_div40 2 6504 #define rx_x4_rs_fec_status0_vcoDivider_div42 3 6505 #define rx_x4_rs_fec_status0_vcoDivider_div48 4 6506 #define rx_x4_rs_fec_status0_vcoDivider_div50 5 6507 #define rx_x4_rs_fec_status0_vcoDivider_div52 6 6508 #define rx_x4_rs_fec_status0_vcoDivider_div54 7 6509 #define rx_x4_rs_fec_status0_vcoDivider_div60 8 6510 #define rx_x4_rs_fec_status0_vcoDivider_div64 9 6511 #define rx_x4_rs_fec_status0_vcoDivider_div66 10 6512 #define rx_x4_rs_fec_status0_vcoDivider_div68 11 6513 #define rx_x4_rs_fec_status0_vcoDivider_div70 12 6514 #define rx_x4_rs_fec_status0_vcoDivider_div80 13 6515 #define rx_x4_rs_fec_status0_vcoDivider_div92 14 6516 #define rx_x4_rs_fec_status0_vcoDivider_div100 15 6517 6518 /**************************************************************************** 6519 * Enums: rx_x4_rs_fec_status0_refClkSelect 6520 */ 6521 #define rx_x4_rs_fec_status0_refClkSelect_clk_156p25MHz 1 6522 #define rx_x4_rs_fec_status0_refClkSelect_clk_312p5Mhz 2 6523 6524 /**************************************************************************** 6525 * Enums: rx_x4_rs_fec_status0_aerMMDdevTypeSelect 6526 */ 6527 #define rx_x4_rs_fec_status0_aerMMDdevTypeSelect_combo_core 0 6528 #define rx_x4_rs_fec_status0_aerMMDdevTypeSelect_PMA_PMD 1 6529 #define rx_x4_rs_fec_status0_aerMMDdevTypeSelect_PCS 3 6530 #define rx_x4_rs_fec_status0_aerMMDdevTypeSelect_PHY 4 6531 #define rx_x4_rs_fec_status0_aerMMDdevTypeSelect_DTE 5 6532 #define rx_x4_rs_fec_status0_aerMMDdevTypeSelect_CL73_AN 7 6533 6534 /**************************************************************************** 6535 * Enums: rx_x4_rs_fec_status0_aerMMDportSelect 6536 */ 6537 #define rx_x4_rs_fec_status0_aerMMDportSelect_ln0 0 6538 #define rx_x4_rs_fec_status0_aerMMDportSelect_ln1 1 6539 #define rx_x4_rs_fec_status0_aerMMDportSelect_ln2 2 6540 #define rx_x4_rs_fec_status0_aerMMDportSelect_ln3 3 6541 #define rx_x4_rs_fec_status0_aerMMDportSelect_BCST_ln0_1_2_3 511 6542 #define rx_x4_rs_fec_status0_aerMMDportSelect_BCST_ln0_1 512 6543 #define rx_x4_rs_fec_status0_aerMMDportSelect_BCST_ln2_3 513 6544 6545 /**************************************************************************** 6546 * Enums: rx_x4_rs_fec_status0_firmwareModeSelect 6547 */ 6548 #define rx_x4_rs_fec_status0_firmwareModeSelect_DEFAULT 0 6549 #define rx_x4_rs_fec_status0_firmwareModeSelect_SFP_OPT_LR 1 6550 #define rx_x4_rs_fec_status0_firmwareModeSelect_SFP_DAC 2 6551 #define rx_x4_rs_fec_status0_firmwareModeSelect_XLAUI 3 6552 #define rx_x4_rs_fec_status0_firmwareModeSelect_LONG_CH_6G 4 6553 6554 /**************************************************************************** 6555 * Enums: rx_x4_rs_fec_status0_tempIdxSelect 6556 */ 6557 #define rx_x4_rs_fec_status0_tempIdxSelect_LTE__22p9C 15 6558 #define rx_x4_rs_fec_status0_tempIdxSelect_LTE__12p6C 14 6559 #define rx_x4_rs_fec_status0_tempIdxSelect_LTE__3p0C 13 6560 #define rx_x4_rs_fec_status0_tempIdxSelect_LTE_6p7C 12 6561 #define rx_x4_rs_fec_status0_tempIdxSelect_LTE_16p4C 11 6562 #define rx_x4_rs_fec_status0_tempIdxSelect_LTE_26p6C 10 6563 #define rx_x4_rs_fec_status0_tempIdxSelect_LTE_36p3C 9 6564 #define rx_x4_rs_fec_status0_tempIdxSelect_LTE_46p0C 8 6565 #define rx_x4_rs_fec_status0_tempIdxSelect_LTE_56p2C 7 6566 #define rx_x4_rs_fec_status0_tempIdxSelect_LTE_65p9C 6 6567 #define rx_x4_rs_fec_status0_tempIdxSelect_LTE_75p6C 5 6568 #define rx_x4_rs_fec_status0_tempIdxSelect_LTE_85p3C 4 6569 #define rx_x4_rs_fec_status0_tempIdxSelect_LTE_95p5C 3 6570 #define rx_x4_rs_fec_status0_tempIdxSelect_LTE_105p2C 2 6571 #define rx_x4_rs_fec_status0_tempIdxSelect_LTE_114p9C 1 6572 #define rx_x4_rs_fec_status0_tempIdxSelect_LTE_125p1C 0 6573 6574 /**************************************************************************** 6575 * Enums: rx_x4_rs_fec_status0_port_mode 6576 */ 6577 #define rx_x4_rs_fec_status0_port_mode_QUAD_PORT 0 6578 #define rx_x4_rs_fec_status0_port_mode_TRI_1_PORT 1 6579 #define rx_x4_rs_fec_status0_port_mode_TRI_2_PORT 2 6580 #define rx_x4_rs_fec_status0_port_mode_DUAL_PORT 3 6581 #define rx_x4_rs_fec_status0_port_mode_SINGLE_PORT 4 6582 #define rx_x4_rs_fec_status0_port_mode_SINGLE_OCTAL_PORT 5 6583 6584 /**************************************************************************** 6585 * Enums: rx_x4_rs_fec_status0_rev_letter_enum 6586 */ 6587 #define rx_x4_rs_fec_status0_rev_letter_enum_REV_A 0 6588 #define rx_x4_rs_fec_status0_rev_letter_enum_REV_B 1 6589 #define rx_x4_rs_fec_status0_rev_letter_enum_REV_C 2 6590 #define rx_x4_rs_fec_status0_rev_letter_enum_REV_D 3 6591 6592 /**************************************************************************** 6593 * Enums: rx_x4_rs_fec_status0_rev_number_enum 6594 */ 6595 #define rx_x4_rs_fec_status0_rev_number_enum_REV_0 0 6596 #define rx_x4_rs_fec_status0_rev_number_enum_REV_1 1 6597 #define rx_x4_rs_fec_status0_rev_number_enum_REV_2 2 6598 #define rx_x4_rs_fec_status0_rev_number_enum_REV_3 3 6599 #define rx_x4_rs_fec_status0_rev_number_enum_REV_4 4 6600 #define rx_x4_rs_fec_status0_rev_number_enum_REV_5 5 6601 #define rx_x4_rs_fec_status0_rev_number_enum_REV_6 6 6602 #define rx_x4_rs_fec_status0_rev_number_enum_REV_7 7 6603 6604 /**************************************************************************** 6605 * Enums: rx_x4_rs_fec_status0_bonding_enum 6606 */ 6607 #define rx_x4_rs_fec_status0_bonding_enum_WIRE_BOND 0 6608 #define rx_x4_rs_fec_status0_bonding_enum_FLIP_CHIP 1 6609 6610 /**************************************************************************** 6611 * Enums: rx_x4_rs_fec_status0_tech_process 6612 */ 6613 #define rx_x4_rs_fec_status0_tech_process_PROCESS_90NM 0 6614 #define rx_x4_rs_fec_status0_tech_process_PROCESS_65NM 1 6615 #define rx_x4_rs_fec_status0_tech_process_PROCESS_40NM 2 6616 #define rx_x4_rs_fec_status0_tech_process_PROCESS_28NM 3 6617 #define rx_x4_rs_fec_status0_tech_process_PROCESS_16NM 4 6618 6619 /**************************************************************************** 6620 * Enums: rx_x4_rs_fec_status0_model_num 6621 */ 6622 #define rx_x4_rs_fec_status0_model_num_SERDES_CL73 0 6623 #define rx_x4_rs_fec_status0_model_num_XGXS_16G 1 6624 #define rx_x4_rs_fec_status0_model_num_HYPERCORE 2 6625 #define rx_x4_rs_fec_status0_model_num_HYPERLITE 3 6626 #define rx_x4_rs_fec_status0_model_num_PCIE_G2_PIPE 4 6627 #define rx_x4_rs_fec_status0_model_num_SERDES_1p25GBd 5 6628 #define rx_x4_rs_fec_status0_model_num_SATA2 6 6629 #define rx_x4_rs_fec_status0_model_num_QSGMII 7 6630 #define rx_x4_rs_fec_status0_model_num_XGXS10G 8 6631 #define rx_x4_rs_fec_status0_model_num_WARPCORE 9 6632 #define rx_x4_rs_fec_status0_model_num_XFICORE 10 6633 #define rx_x4_rs_fec_status0_model_num_RXFI 11 6634 #define rx_x4_rs_fec_status0_model_num_WARPLITE 12 6635 #define rx_x4_rs_fec_status0_model_num_PENTACORE 13 6636 #define rx_x4_rs_fec_status0_model_num_ESM 14 6637 #define rx_x4_rs_fec_status0_model_num_QUAD_SGMII 15 6638 #define rx_x4_rs_fec_status0_model_num_WARPCORE_3 16 6639 #define rx_x4_rs_fec_status0_model_num_TSC 17 6640 #define rx_x4_rs_fec_status0_model_num_TSC4E 18 6641 #define rx_x4_rs_fec_status0_model_num_TSC12E 19 6642 #define rx_x4_rs_fec_status0_model_num_TSC4F 20 6643 #define rx_x4_rs_fec_status0_model_num_TSC4F_GEN2 21 6644 #define rx_x4_rs_fec_status0_model_num_XGXS_CL73_90NM 29 6645 #define rx_x4_rs_fec_status0_model_num_SERDES_CL73_90NM 30 6646 #define rx_x4_rs_fec_status0_model_num_WARPCORE3 32 6647 #define rx_x4_rs_fec_status0_model_num_WARPCORE4_TSC 33 6648 #define rx_x4_rs_fec_status0_model_num_RXAUI 34 6649 #define rx_x4_rs_fec_status0_model_num_TSCE_GEN3 35 6650 #define rx_x4_rs_fec_status0_model_num_TSC4F_GEN3 36 6651 #define rx_x4_rs_fec_status0_model_num_TSCBH 37 6652 6653 /**************************************************************************** 6654 * Enums: rx_x4_rs_fec_status0_payload 6655 */ 6656 #define rx_x4_rs_fec_status0_payload_REPEAT_2_BYTES 0 6657 #define rx_x4_rs_fec_status0_payload_RAMPING 1 6658 #define rx_x4_rs_fec_status0_payload_CL48_CRPAT 2 6659 #define rx_x4_rs_fec_status0_payload_CL48_CJPAT 3 6660 #define rx_x4_rs_fec_status0_payload_CL36_LONG_CRPAT 4 6661 #define rx_x4_rs_fec_status0_payload_CL36_SHORT_CRPAT 5 6662 6663 /**************************************************************************** 6664 * Enums: rx_x4_rs_fec_status0_sc 6665 */ 6666 #define rx_x4_rs_fec_status0_sc_SPEED_10G_IEEE_KR1 0 6667 #define rx_x4_rs_fec_status0_sc_SPEED_25G_IEEE_KS1_CS1 1 6668 #define rx_x4_rs_fec_status0_sc_SPEED_25G_IEEE_KR1_CR1 2 6669 #define rx_x4_rs_fec_status0_sc_SPEED_40G_IEEE_KR4 3 6670 #define rx_x4_rs_fec_status0_sc_SPEED_40G_IEEE_CR4 4 6671 #define rx_x4_rs_fec_status0_sc_SPEED_50G_IEEE_KR1_CR1 5 6672 #define rx_x4_rs_fec_status0_sc_SPEED_100G_IEEE_KR4 6 6673 #define rx_x4_rs_fec_status0_sc_SPEED_100G_IEEE_CR4 7 6674 #define rx_x4_rs_fec_status0_sc_SPEED_100G_IEEE_KR2_CR2 8 6675 #define rx_x4_rs_fec_status0_sc_SPEED_200G_IEEE_KR4_CR4 9 6676 #define rx_x4_rs_fec_status0_sc_SPEED_400G_IEEE_X8 10 6677 #define rx_x4_rs_fec_status0_sc_SPEED_CL73_IEEE_20GVCO 11 6678 #define rx_x4_rs_fec_status0_sc_SPEED_CL73_IEEE_25GVCO 12 6679 #define rx_x4_rs_fec_status0_sc_SPEED_CL73_IEEE_26GVCO 13 6680 #define rx_x4_rs_fec_status0_sc_SPEED_20G_BRCM_CR1 14 6681 #define rx_x4_rs_fec_status0_sc_SPEED_20G_BRCM_KR1 15 6682 #define rx_x4_rs_fec_status0_sc_SPEED_25G_BRCM_CR1 16 6683 #define rx_x4_rs_fec_status0_sc_SPEED_25G_BRCM_KR1 17 6684 #define rx_x4_rs_fec_status0_sc_SPEED_40G_BRCM_CR2 18 6685 #define rx_x4_rs_fec_status0_sc_SPEED_40G_BRCM_KR2 19 6686 #define rx_x4_rs_fec_status0_sc_SPEED_50G_BRCM_CR2 20 6687 #define rx_x4_rs_fec_status0_sc_SPEED_50G_BRCM_KR2 21 6688 #define rx_x4_rs_fec_status0_sc_SPEED_50G_BRCM_CR4 22 6689 #define rx_x4_rs_fec_status0_sc_SPEED_50G_BRCM_KR4 23 6690 #define rx_x4_rs_fec_status0_sc_SPEED_50G_BRCM_FEC_544_CR2_KR2 24 6691 #define rx_x4_rs_fec_status0_sc_SPEED_RESERVED_19 25 6692 #define rx_x4_rs_fec_status0_sc_SPEED_50G_BRCM_FEC_544_CR1_KR1 26 6693 #define rx_x4_rs_fec_status0_sc_SPEED_50G_BRCM_NO_FEC_CR1_KR1 27 6694 #define rx_x4_rs_fec_status0_sc_SPEED_50G_BRCM_FEC_528_CR1_KR1 28 6695 #define rx_x4_rs_fec_status0_sc_SPEED_400G_BRCM_NO_FEC_KR8_CR8 29 6696 #define rx_x4_rs_fec_status0_sc_SPEED_400G_BRCM_FEC_KR8_CR8 30 6697 #define rx_x4_rs_fec_status0_sc_SPEED_200G_BRCM_NO_FEC_KR4_CR4 31 6698 #define rx_x4_rs_fec_status0_sc_SPEED_200G_BRCM_KR4_CR4 32 6699 #define rx_x4_rs_fec_status0_sc_SPEED_100G_BRCM_KR4_CR4 33 6700 #define rx_x4_rs_fec_status0_sc_SPEED_RESERVED_22 34 6701 #define rx_x4_rs_fec_status0_sc_SPEED_100G_BRCM_FEC_528_KR2_CR2 35 6702 #define rx_x4_rs_fec_status0_sc_SPEED_100G_BRCM_NO_FEC_KR2_CR2 36 6703 #define rx_x4_rs_fec_status0_sc_SPEED_100G_BRCM_NO_FEC_X4 37 6704 6705 /**************************************************************************** 6706 * Enums: rx_x4_rs_fec_status0_t_fifo_modes 6707 */ 6708 #define rx_x4_rs_fec_status0_t_fifo_modes_T_FIFO_INSERT_NO_AM 0 6709 #define rx_x4_rs_fec_status0_t_fifo_modes_T_FIFO_INSERT_4_AM 1 6710 #define rx_x4_rs_fec_status0_t_fifo_modes_T_FIFO_INSERT_20_AM 2 6711 #define rx_x4_rs_fec_status0_t_fifo_modes_T_FIFO_INSERT_2_AM 3 6712 6713 /**************************************************************************** 6714 * Enums: rx_x4_rs_fec_status0_t_enc_modes 6715 */ 6716 #define rx_x4_rs_fec_status0_t_enc_modes_T_ENC_MODE_BYPASS 0 6717 #define rx_x4_rs_fec_status0_t_enc_modes_T_ENC_MODE_CL49 1 6718 #define rx_x4_rs_fec_status0_t_enc_modes_T_ENC_MODE_CL82 2 6719 6720 /**************************************************************************** 6721 * Enums: rx_x4_rs_fec_status0_btmx_mode 6722 */ 6723 #define rx_x4_rs_fec_status0_btmx_mode_BS_BTMX_MODE_1to1 0 6724 #define rx_x4_rs_fec_status0_btmx_mode_BS_BTMX_MODE_2to1 1 6725 #define rx_x4_rs_fec_status0_btmx_mode_BS_BTMX_MODE_5to1 2 6726 6727 /**************************************************************************** 6728 * Enums: rx_x4_rs_fec_status0_t_type_cl82 6729 */ 6730 #define rx_x4_rs_fec_status0_t_type_cl82_T_TYPE_B1 5 6731 #define rx_x4_rs_fec_status0_t_type_cl82_T_TYPE_C 4 6732 #define rx_x4_rs_fec_status0_t_type_cl82_T_TYPE_S 3 6733 #define rx_x4_rs_fec_status0_t_type_cl82_T_TYPE_T 2 6734 #define rx_x4_rs_fec_status0_t_type_cl82_T_TYPE_D 1 6735 #define rx_x4_rs_fec_status0_t_type_cl82_T_TYPE_E 0 6736 6737 /**************************************************************************** 6738 * Enums: rx_x4_rs_fec_status0_txsm_state_cl82 6739 */ 6740 #define rx_x4_rs_fec_status0_txsm_state_cl82_TX_E 4 6741 #define rx_x4_rs_fec_status0_txsm_state_cl82_TX_T 3 6742 #define rx_x4_rs_fec_status0_txsm_state_cl82_TX_D 2 6743 #define rx_x4_rs_fec_status0_txsm_state_cl82_TX_C 1 6744 #define rx_x4_rs_fec_status0_txsm_state_cl82_TX_INIT 0 6745 6746 /**************************************************************************** 6747 * Enums: rx_x4_rs_fec_status0_ltxsm_state_cl82 6748 */ 6749 #define rx_x4_rs_fec_status0_ltxsm_state_cl82_TX_E 16 6750 #define rx_x4_rs_fec_status0_ltxsm_state_cl82_TX_T 8 6751 #define rx_x4_rs_fec_status0_ltxsm_state_cl82_TX_D 4 6752 #define rx_x4_rs_fec_status0_ltxsm_state_cl82_TX_C 2 6753 #define rx_x4_rs_fec_status0_ltxsm_state_cl82_TX_INIT 1 6754 6755 /**************************************************************************** 6756 * Enums: rx_x4_rs_fec_status0_r_type_coded_cl82 6757 */ 6758 #define rx_x4_rs_fec_status0_r_type_coded_cl82_R_TYPE_B1 32 6759 #define rx_x4_rs_fec_status0_r_type_coded_cl82_R_TYPE_C 16 6760 #define rx_x4_rs_fec_status0_r_type_coded_cl82_R_TYPE_S 8 6761 #define rx_x4_rs_fec_status0_r_type_coded_cl82_R_TYPE_T 4 6762 #define rx_x4_rs_fec_status0_r_type_coded_cl82_R_TYPE_D 2 6763 #define rx_x4_rs_fec_status0_r_type_coded_cl82_R_TYPE_E 1 6764 6765 /**************************************************************************** 6766 * Enums: rx_x4_rs_fec_status0_rxsm_state_cl82 6767 */ 6768 #define rx_x4_rs_fec_status0_rxsm_state_cl82_RX_E 16 6769 #define rx_x4_rs_fec_status0_rxsm_state_cl82_RX_T 8 6770 #define rx_x4_rs_fec_status0_rxsm_state_cl82_RX_D 4 6771 #define rx_x4_rs_fec_status0_rxsm_state_cl82_RX_C 2 6772 #define rx_x4_rs_fec_status0_rxsm_state_cl82_RX_INIT 1 6773 6774 /**************************************************************************** 6775 * Enums: rx_x4_rs_fec_status0_deskew_state 6776 */ 6777 #define rx_x4_rs_fec_status0_deskew_state_ALIGN_ACQUIRED 2 6778 #define rx_x4_rs_fec_status0_deskew_state_LOSS_OF_ALIGNMENT 1 6779 6780 /**************************************************************************** 6781 * Enums: rx_x4_rs_fec_status0_os_mode_enum 6782 */ 6783 #define rx_x4_rs_fec_status0_os_mode_enum_OS_MODE_1 0 6784 #define rx_x4_rs_fec_status0_os_mode_enum_OS_MODE_2 1 6785 #define rx_x4_rs_fec_status0_os_mode_enum_OS_MODE_4 2 6786 #define rx_x4_rs_fec_status0_os_mode_enum_OS_MODE_16p5 8 6787 #define rx_x4_rs_fec_status0_os_mode_enum_OS_MODE_20p625 12 6788 6789 /**************************************************************************** 6790 * Enums: rx_x4_rs_fec_status0_scr_modes 6791 */ 6792 #define rx_x4_rs_fec_status0_scr_modes_T_SCR_MODE_BYPASS 0 6793 #define rx_x4_rs_fec_status0_scr_modes_T_SCR_MODE_CL49 1 6794 #define rx_x4_rs_fec_status0_scr_modes_T_SCR_MODE_40G_2_LANE 2 6795 #define rx_x4_rs_fec_status0_scr_modes_T_SCR_MODE_100G 3 6796 #define rx_x4_rs_fec_status0_scr_modes_T_SCR_MODE_20G 4 6797 #define rx_x4_rs_fec_status0_scr_modes_T_SCR_MODE_40G_4_LANE 5 6798 6799 /**************************************************************************** 6800 * Enums: rx_x4_rs_fec_status0_descr_modes 6801 */ 6802 #define rx_x4_rs_fec_status0_descr_modes_R_DESCR_MODE_BYPASS 0 6803 #define rx_x4_rs_fec_status0_descr_modes_R_DESCR_MODE_CL49 1 6804 #define rx_x4_rs_fec_status0_descr_modes_R_DESCR_MODE_CL82 2 6805 6806 /**************************************************************************** 6807 * Enums: rx_x4_rs_fec_status0_r_dec_tl_mode 6808 */ 6809 #define rx_x4_rs_fec_status0_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 6810 #define rx_x4_rs_fec_status0_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 6811 #define rx_x4_rs_fec_status0_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 6812 6813 /**************************************************************************** 6814 * Enums: rx_x4_rs_fec_status0_r_dec_fsm_mode 6815 */ 6816 #define rx_x4_rs_fec_status0_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 6817 #define rx_x4_rs_fec_status0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 6818 #define rx_x4_rs_fec_status0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 6819 6820 /**************************************************************************** 6821 * Enums: rx_x4_rs_fec_status0_r_deskew_mode 6822 */ 6823 #define rx_x4_rs_fec_status0_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 6824 #define rx_x4_rs_fec_status0_r_deskew_mode_R_DESKEW_MODE_20G 1 6825 #define rx_x4_rs_fec_status0_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 6826 #define rx_x4_rs_fec_status0_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 6827 #define rx_x4_rs_fec_status0_r_deskew_mode_R_DESKEW_MODE_100G 4 6828 #define rx_x4_rs_fec_status0_r_deskew_mode_R_DESKEW_MODE_CL49 5 6829 #define rx_x4_rs_fec_status0_r_deskew_mode_R_DESKEW_MODE_CL91_QUAD 6 6830 #define rx_x4_rs_fec_status0_r_deskew_mode_R_DESKEW_MODE_CL91_SINGLE_BRCM 7 6831 #define rx_x4_rs_fec_status0_r_deskew_mode_R_DESKEW_MODE_CL91_DUAL_BRCM 8 6832 #define rx_x4_rs_fec_status0_r_deskew_mode_R_DESKEW_MODE_CL91_FC 9 6833 6834 /**************************************************************************** 6835 * Enums: rx_x4_rs_fec_status0_bs_dist_modes 6836 */ 6837 #define rx_x4_rs_fec_status0_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 6838 #define rx_x4_rs_fec_status0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 6839 #define rx_x4_rs_fec_status0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 6840 #define rx_x4_rs_fec_status0_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 6841 6842 /**************************************************************************** 6843 * Enums: rx_x4_rs_fec_status0_cl49_t_type 6844 */ 6845 #define rx_x4_rs_fec_status0_cl49_t_type_BAD_T_TYPE 15 6846 #define rx_x4_rs_fec_status0_cl49_t_type_T_TYPE_B0 11 6847 #define rx_x4_rs_fec_status0_cl49_t_type_T_TYPE_OB 10 6848 #define rx_x4_rs_fec_status0_cl49_t_type_T_TYPE_B1 9 6849 #define rx_x4_rs_fec_status0_cl49_t_type_T_TYPE_DB 8 6850 #define rx_x4_rs_fec_status0_cl49_t_type_T_TYPE_FC 7 6851 #define rx_x4_rs_fec_status0_cl49_t_type_T_TYPE_TB 6 6852 #define rx_x4_rs_fec_status0_cl49_t_type_T_TYPE_LI 5 6853 #define rx_x4_rs_fec_status0_cl49_t_type_T_TYPE_C 4 6854 #define rx_x4_rs_fec_status0_cl49_t_type_T_TYPE_S 3 6855 #define rx_x4_rs_fec_status0_cl49_t_type_T_TYPE_T 2 6856 #define rx_x4_rs_fec_status0_cl49_t_type_T_TYPE_D 1 6857 #define rx_x4_rs_fec_status0_cl49_t_type_T_TYPE_E 0 6858 6859 /**************************************************************************** 6860 * Enums: rx_x4_rs_fec_status0_cl49_txsm_states 6861 */ 6862 #define rx_x4_rs_fec_status0_cl49_txsm_states_TX_LI 5 6863 #define rx_x4_rs_fec_status0_cl49_txsm_states_TX_E 4 6864 #define rx_x4_rs_fec_status0_cl49_txsm_states_TX_T 3 6865 #define rx_x4_rs_fec_status0_cl49_txsm_states_TX_D 2 6866 #define rx_x4_rs_fec_status0_cl49_txsm_states_TX_C 1 6867 #define rx_x4_rs_fec_status0_cl49_txsm_states_TX_INIT 0 6868 6869 /**************************************************************************** 6870 * Enums: rx_x4_rs_fec_status0_cl49_ltxsm_states 6871 */ 6872 #define rx_x4_rs_fec_status0_cl49_ltxsm_states_TX_LI 32 6873 #define rx_x4_rs_fec_status0_cl49_ltxsm_states_TX_E 16 6874 #define rx_x4_rs_fec_status0_cl49_ltxsm_states_TX_T 8 6875 #define rx_x4_rs_fec_status0_cl49_ltxsm_states_TX_D 4 6876 #define rx_x4_rs_fec_status0_cl49_ltxsm_states_TX_C 2 6877 #define rx_x4_rs_fec_status0_cl49_ltxsm_states_TX_INIT 1 6878 6879 /**************************************************************************** 6880 * Enums: rx_x4_rs_fec_status0_burst_error_mode 6881 */ 6882 #define rx_x4_rs_fec_status0_burst_error_mode_BURST_ERROR_11_BITS 0 6883 #define rx_x4_rs_fec_status0_burst_error_mode_BURST_ERROR_16_BITS 1 6884 #define rx_x4_rs_fec_status0_burst_error_mode_BURST_ERROR_17_BITS 2 6885 #define rx_x4_rs_fec_status0_burst_error_mode_BURST_ERROR_18_BITS 3 6886 #define rx_x4_rs_fec_status0_burst_error_mode_BURST_ERROR_19_BITS 4 6887 #define rx_x4_rs_fec_status0_burst_error_mode_BURST_ERROR_20_BITS 5 6888 #define rx_x4_rs_fec_status0_burst_error_mode_BURST_ERROR_21_BITS 6 6889 #define rx_x4_rs_fec_status0_burst_error_mode_BURST_ERROR_22_BITS 7 6890 #define rx_x4_rs_fec_status0_burst_error_mode_BURST_ERROR_23_BITS 8 6891 #define rx_x4_rs_fec_status0_burst_error_mode_BURST_ERROR_24_BITS 9 6892 #define rx_x4_rs_fec_status0_burst_error_mode_BURST_ERROR_25_BITS 10 6893 #define rx_x4_rs_fec_status0_burst_error_mode_BURST_ERROR_26_BITS 11 6894 #define rx_x4_rs_fec_status0_burst_error_mode_BURST_ERROR_27_BITS 12 6895 #define rx_x4_rs_fec_status0_burst_error_mode_BURST_ERROR_28_BITS 13 6896 #define rx_x4_rs_fec_status0_burst_error_mode_BURST_ERROR_29_BITS 14 6897 #define rx_x4_rs_fec_status0_burst_error_mode_BURST_ERROR_30_BITS 15 6898 #define rx_x4_rs_fec_status0_burst_error_mode_BURST_ERROR_31_BITS 16 6899 #define rx_x4_rs_fec_status0_burst_error_mode_BURST_ERROR_32_BITS 17 6900 #define rx_x4_rs_fec_status0_burst_error_mode_BURST_ERROR_33_BITS 18 6901 #define rx_x4_rs_fec_status0_burst_error_mode_BURST_ERROR_34_BITS 19 6902 #define rx_x4_rs_fec_status0_burst_error_mode_BURST_ERROR_35_BITS 20 6903 #define rx_x4_rs_fec_status0_burst_error_mode_BURST_ERROR_36_BITS 21 6904 #define rx_x4_rs_fec_status0_burst_error_mode_BURST_ERROR_37_BITS 22 6905 #define rx_x4_rs_fec_status0_burst_error_mode_BURST_ERROR_38_BITS 23 6906 #define rx_x4_rs_fec_status0_burst_error_mode_BURST_ERROR_39_BITS 24 6907 #define rx_x4_rs_fec_status0_burst_error_mode_BURST_ERROR_40_BITS 25 6908 #define rx_x4_rs_fec_status0_burst_error_mode_BURST_ERROR_41_BITS 26 6909 6910 /**************************************************************************** 6911 * Enums: rx_x4_rs_fec_status0_bermon_state 6912 */ 6913 #define rx_x4_rs_fec_status0_bermon_state_HI_BER 4 6914 #define rx_x4_rs_fec_status0_bermon_state_GOOD_BER 3 6915 #define rx_x4_rs_fec_status0_bermon_state_BER_TEST_SH 2 6916 #define rx_x4_rs_fec_status0_bermon_state_START_TIMER 1 6917 #define rx_x4_rs_fec_status0_bermon_state_BER_MT_INIT 0 6918 6919 /**************************************************************************** 6920 * Enums: rx_x4_rs_fec_status0_rxsm_state_cl49 6921 */ 6922 #define rx_x4_rs_fec_status0_rxsm_state_cl49_RX_LI 32 6923 #define rx_x4_rs_fec_status0_rxsm_state_cl49_RX_E 16 6924 #define rx_x4_rs_fec_status0_rxsm_state_cl49_RX_T 8 6925 #define rx_x4_rs_fec_status0_rxsm_state_cl49_RX_D 4 6926 #define rx_x4_rs_fec_status0_rxsm_state_cl49_RX_C 2 6927 #define rx_x4_rs_fec_status0_rxsm_state_cl49_RX_INIT 1 6928 6929 /**************************************************************************** 6930 * Enums: rx_x4_rs_fec_status0_r_type 6931 */ 6932 #define rx_x4_rs_fec_status0_r_type_BAD_R_TYPE 15 6933 #define rx_x4_rs_fec_status0_r_type_R_TYPE_B0 11 6934 #define rx_x4_rs_fec_status0_r_type_R_TYPE_OB 10 6935 #define rx_x4_rs_fec_status0_r_type_R_TYPE_B1 9 6936 #define rx_x4_rs_fec_status0_r_type_R_TYPE_DB 8 6937 #define rx_x4_rs_fec_status0_r_type_R_TYPE_FC 7 6938 #define rx_x4_rs_fec_status0_r_type_R_TYPE_TB 6 6939 #define rx_x4_rs_fec_status0_r_type_R_TYPE_LI 5 6940 #define rx_x4_rs_fec_status0_r_type_R_TYPE_C 4 6941 #define rx_x4_rs_fec_status0_r_type_R_TYPE_S 3 6942 #define rx_x4_rs_fec_status0_r_type_R_TYPE_T 2 6943 #define rx_x4_rs_fec_status0_r_type_R_TYPE_D 1 6944 #define rx_x4_rs_fec_status0_r_type_R_TYPE_E 0 6945 6946 /**************************************************************************** 6947 * Enums: rx_x4_rs_fec_status0_am_lock_state 6948 */ 6949 #define rx_x4_rs_fec_status0_am_lock_state_INVALID_AM 512 6950 #define rx_x4_rs_fec_status0_am_lock_state_GOOD_AM 256 6951 #define rx_x4_rs_fec_status0_am_lock_state_COMP_AM 128 6952 #define rx_x4_rs_fec_status0_am_lock_state_TIMER_2 64 6953 #define rx_x4_rs_fec_status0_am_lock_state_AM_2_GOOD 32 6954 #define rx_x4_rs_fec_status0_am_lock_state_COMP_2ND 16 6955 #define rx_x4_rs_fec_status0_am_lock_state_TIMER_1 8 6956 #define rx_x4_rs_fec_status0_am_lock_state_FIND_1ST 4 6957 #define rx_x4_rs_fec_status0_am_lock_state_AM_RESET_CNT 2 6958 #define rx_x4_rs_fec_status0_am_lock_state_AM_LOCK_INIT 1 6959 6960 /**************************************************************************** 6961 * Enums: rx_x4_rs_fec_status0_msg_selector 6962 */ 6963 #define rx_x4_rs_fec_status0_msg_selector_RESERVED 0 6964 #define rx_x4_rs_fec_status0_msg_selector_VALUE_802p3 1 6965 #define rx_x4_rs_fec_status0_msg_selector_VALUE_802p9 2 6966 #define rx_x4_rs_fec_status0_msg_selector_VALUE_802p5 3 6967 #define rx_x4_rs_fec_status0_msg_selector_VALUE_1394 4 6968 6969 /**************************************************************************** 6970 * Enums: rx_x4_rs_fec_status0_synce_enum_stage1 6971 */ 6972 #define rx_x4_rs_fec_status0_synce_enum_stage1_SYNCE_NO_DIV 0 6973 #define rx_x4_rs_fec_status0_synce_enum_stage1_SYNCE_DIV_7 1 6974 #define rx_x4_rs_fec_status0_synce_enum_stage1_SYNCE_DIV_11 2 6975 6976 /**************************************************************************** 6977 * Enums: rx_x4_rs_fec_status0_synce_enum_stage0 6978 */ 6979 #define rx_x4_rs_fec_status0_synce_enum_stage0_SYNCE_NO_DIV 0 6980 #define rx_x4_rs_fec_status0_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 6981 #define rx_x4_rs_fec_status0_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 6982 6983 /**************************************************************************** 6984 * Enums: rx_x4_rs_fec_status0_cl91_sync_state 6985 */ 6986 #define rx_x4_rs_fec_status0_cl91_sync_state_FIND_1ST 0 6987 #define rx_x4_rs_fec_status0_cl91_sync_state_COUNT_NEXT 1 6988 #define rx_x4_rs_fec_status0_cl91_sync_state_COMP_2ND 2 6989 #define rx_x4_rs_fec_status0_cl91_sync_state_TWO_GOOD 3 6990 6991 /**************************************************************************** 6992 * Enums: rx_x4_rs_fec_status0_RS_FEC_sync_state 6993 */ 6994 #define rx_x4_rs_fec_status0_RS_FEC_sync_state_LOCK_INIT 0 6995 #define rx_x4_rs_fec_status0_RS_FEC_sync_state_FIND_1ST 1 6996 #define rx_x4_rs_fec_status0_RS_FEC_sync_state_COUNT_NEXT 2 6997 #define rx_x4_rs_fec_status0_RS_FEC_sync_state_COMP_2ND 3 6998 #define rx_x4_rs_fec_status0_RS_FEC_sync_state_TWO_GOOD 4 6999 7000 /**************************************************************************** 7001 * Enums: rx_x4_rs_fec_status0_cl91_algn_state 7002 */ 7003 #define rx_x4_rs_fec_status0_cl91_algn_state_LOSS_OF_ALIGNMENT 0 7004 #define rx_x4_rs_fec_status0_cl91_algn_state_DESKEW 1 7005 #define rx_x4_rs_fec_status0_cl91_algn_state_DESKEW_FAIL 2 7006 #define rx_x4_rs_fec_status0_cl91_algn_state_ALIGN_ACQUIRED 3 7007 #define rx_x4_rs_fec_status0_cl91_algn_state_CW_GOOD 4 7008 #define rx_x4_rs_fec_status0_cl91_algn_state_CW_BAD 5 7009 #define rx_x4_rs_fec_status0_cl91_algn_state_THREE_BAD 6 7010 7011 /**************************************************************************** 7012 * Enums: rx_x4_rs_fec_status0_RS_FEC_algn_state 7013 */ 7014 #define rx_x4_rs_fec_status0_RS_FEC_algn_state_LOSS_OF_ALIGNMENT 0 7015 #define rx_x4_rs_fec_status0_RS_FEC_algn_state_DESKEW 1 7016 #define rx_x4_rs_fec_status0_RS_FEC_algn_state_DESKEW_FAIL 2 7017 #define rx_x4_rs_fec_status0_RS_FEC_algn_state_ALIGN_ACQUIRED 3 7018 #define rx_x4_rs_fec_status0_RS_FEC_algn_state_CW_GOOD 4 7019 #define rx_x4_rs_fec_status0_RS_FEC_algn_state_CW_BAD 5 7020 #define rx_x4_rs_fec_status0_RS_FEC_algn_state_THREE_BAD 6 7021 7022 /**************************************************************************** 7023 * Enums: rx_x4_rs_fec_status0_fec_sel_override 7024 */ 7025 #define rx_x4_rs_fec_status0_fec_sel_override_NO_OVERRIDE 0 7026 #define rx_x4_rs_fec_status0_fec_sel_override_NO_FEC 1 7027 #define rx_x4_rs_fec_status0_fec_sel_override_FEC_CL74 2 7028 #define rx_x4_rs_fec_status0_fec_sel_override_FEC_CL91 3 7029 7030 /**************************************************************************** 7031 * Enums: rx_x4_rs_fec_status0_cl91_blksync_mode 7032 */ 7033 #define rx_x4_rs_fec_status0_cl91_blksync_mode_R_BLKSYNC_NO_CL91_FEC 0 7034 #define rx_x4_rs_fec_status0_cl91_blksync_mode_R_BLKSYNC_CL91_QUAD_LANE_FEC 1 7035 #define rx_x4_rs_fec_status0_cl91_blksync_mode_R_BLKSYNC_CL91_DUAL_LANE_FEC 2 7036 #define rx_x4_rs_fec_status0_cl91_blksync_mode_R_BLKSYNC_CL91_SINGLE_LANE_FEC 3 7037 #define rx_x4_rs_fec_status0_cl91_blksync_mode_R_BLKSYNC_CL91_FC_FEC 4 7038 7039 /**************************************************************************** 7040 * Enums: rx_x4_rs_fec_status0_r_merge_mode 7041 */ 7042 #define rx_x4_rs_fec_status0_r_merge_mode_R_MERGE_MODE_BYPASS 0 7043 #define rx_x4_rs_fec_status0_r_merge_mode_R_MERGE_MODE_CL91_FC 1 7044 #define rx_x4_rs_fec_status0_r_merge_mode_R_MERGE_MODE_CL91_SINGLE_LANE 2 7045 #define rx_x4_rs_fec_status0_r_merge_mode_R_MERGE_MODE_CL91_DUAL_LANE 3 7046 #define rx_x4_rs_fec_status0_r_merge_mode_R_MERGE_MODE_CL91_QUAD_LANE 4 7047 7048 /**************************************************************************** 7049 * Enums: rx_x4_rs_fec_status0_r_tc_mode 7050 */ 7051 #define rx_x4_rs_fec_status0_r_tc_mode_R_TC_MODE_SINGLE 0 7052 #define rx_x4_rs_fec_status0_r_tc_mode_R_TC_MODE_DUAL 1 7053 #define rx_x4_rs_fec_status0_r_tc_mode_R_TC_MODE_QUAD 2 7054 7055 /**************************************************************************** 7056 * Enums: rx_x4_rs_fec_status0_r_tc_out_mode 7057 */ 7058 #define rx_x4_rs_fec_status0_r_tc_out_mode_R_TC_OUT_MODE_SINGLE 0 7059 #define rx_x4_rs_fec_status0_r_tc_out_mode_R_TC_OUT_MODE_DUAL 1 7060 #define rx_x4_rs_fec_status0_r_tc_out_mode_R_TC_OUT_MODE_QUAD 2 7061 7062 /**************************************************************************** 7063 * Enums: rx_x4_rs_fec_status0_cl91_fec_mode 7064 */ 7065 #define rx_x4_rs_fec_status0_cl91_fec_mode_NO_CL91_FEC 0 7066 #define rx_x4_rs_fec_status0_cl91_fec_mode_CL91_SINGLE_LANE_FC 1 7067 #define rx_x4_rs_fec_status0_cl91_fec_mode_CL91_SINGLE_LANE_BRCM_PROP 2 7068 #define rx_x4_rs_fec_status0_cl91_fec_mode_CL91_DUAL_LANE_BRCM_PROP 3 7069 #define rx_x4_rs_fec_status0_cl91_fec_mode_CL91_QUAD_LANE 4 7070 #define rx_x4_rs_fec_status0_cl91_fec_mode_IEEE_25G_CL91_SINGLE_LANE 5 7071 7072 /**************************************************************************** 7073 * Enums: rx_x4_rs_fec_status0_RS_FEC_fec_mode 7074 */ 7075 #define rx_x4_rs_fec_status0_RS_FEC_fec_mode_NO_RS_FEC_FEC 0 7076 #define rx_x4_rs_fec_status0_RS_FEC_fec_mode_N_A 1 7077 #define rx_x4_rs_fec_status0_RS_FEC_fec_mode_RS_FEC_SINGLE_LANE_BRCM_PROP 2 7078 #define rx_x4_rs_fec_status0_RS_FEC_fec_mode_RS_FEC_DUAL_LANE_BRCM_PROP 3 7079 #define rx_x4_rs_fec_status0_RS_FEC_fec_mode_RS_FEC_QUAD_LANE 4 7080 #define rx_x4_rs_fec_status0_RS_FEC_fec_mode_IEEE_25G_RS_FEC_SINGLE_LANE 5 7081 7082 /**************************************************************************** 7083 * Enums: rx_x4_rs_fec_status0_am_spacing_mul 7084 */ 7085 #define rx_x4_rs_fec_status0_am_spacing_mul_AM_SPACING_MUL_2 0 7086 #define rx_x4_rs_fec_status0_am_spacing_mul_AM_SPACING_MUL_4 1 7087 #define rx_x4_rs_fec_status0_am_spacing_mul_AM_SPACING_MUL_5 2 7088 #define rx_x4_rs_fec_status0_am_spacing_mul_AM_SPACING_MUL_20 3 7089 7090 /**************************************************************************** 7091 * Enums: rx_x4_rs_fec_status1_cl36TxEEEStates_l 7092 */ 7093 #define rx_x4_rs_fec_status1_cl36TxEEEStates_l_TX_REFRESH 8 7094 #define rx_x4_rs_fec_status1_cl36TxEEEStates_l_TX_QUIET 4 7095 #define rx_x4_rs_fec_status1_cl36TxEEEStates_l_TX_SLEEP 2 7096 #define rx_x4_rs_fec_status1_cl36TxEEEStates_l_TX_ACTIVE 1 7097 7098 /**************************************************************************** 7099 * Enums: rx_x4_rs_fec_status1_cl36TxEEEStates_c 7100 */ 7101 #define rx_x4_rs_fec_status1_cl36TxEEEStates_c_TX_REFRESH 3 7102 #define rx_x4_rs_fec_status1_cl36TxEEEStates_c_TX_QUIET 2 7103 #define rx_x4_rs_fec_status1_cl36TxEEEStates_c_TX_SLEEP 1 7104 #define rx_x4_rs_fec_status1_cl36TxEEEStates_c_TX_ACTIVE 0 7105 7106 /**************************************************************************** 7107 * Enums: rx_x4_rs_fec_status1_cl49TxEEEStates_l 7108 */ 7109 #define rx_x4_rs_fec_status1_cl49TxEEEStates_l_SCR_RESET_2 64 7110 #define rx_x4_rs_fec_status1_cl49TxEEEStates_l_SCR_RESET_1 32 7111 #define rx_x4_rs_fec_status1_cl49TxEEEStates_l_TX_WAKE 16 7112 #define rx_x4_rs_fec_status1_cl49TxEEEStates_l_TX_REFRESH 8 7113 #define rx_x4_rs_fec_status1_cl49TxEEEStates_l_TX_QUIET 4 7114 #define rx_x4_rs_fec_status1_cl49TxEEEStates_l_TX_SLEEP 2 7115 #define rx_x4_rs_fec_status1_cl49TxEEEStates_l_TX_ACTIVE 1 7116 7117 /**************************************************************************** 7118 * Enums: rx_x4_rs_fec_status1_fec_req_enum 7119 */ 7120 #define rx_x4_rs_fec_status1_fec_req_enum_FEC_not_supported 0 7121 #define rx_x4_rs_fec_status1_fec_req_enum_FEC_supported_but_not_requested 1 7122 #define rx_x4_rs_fec_status1_fec_req_enum_invalid_setting 2 7123 #define rx_x4_rs_fec_status1_fec_req_enum_FEC_supported_and_requested 3 7124 7125 /**************************************************************************** 7126 * Enums: rx_x4_rs_fec_status1_cl73_pause_enum 7127 */ 7128 #define rx_x4_rs_fec_status1_cl73_pause_enum_No_PAUSE_ability 0 7129 #define rx_x4_rs_fec_status1_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 7130 #define rx_x4_rs_fec_status1_cl73_pause_enum_Symmetric_PAUSE_ability 1 7131 #define rx_x4_rs_fec_status1_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 7132 7133 /**************************************************************************** 7134 * Enums: rx_x4_rs_fec_status1_cl49TxEEEStates_c 7135 */ 7136 #define rx_x4_rs_fec_status1_cl49TxEEEStates_c_SCR_RESET_2 6 7137 #define rx_x4_rs_fec_status1_cl49TxEEEStates_c_SCR_RESET_1 5 7138 #define rx_x4_rs_fec_status1_cl49TxEEEStates_c_TX_WAKE 4 7139 #define rx_x4_rs_fec_status1_cl49TxEEEStates_c_TX_REFRESH 3 7140 #define rx_x4_rs_fec_status1_cl49TxEEEStates_c_TX_QUIET 2 7141 #define rx_x4_rs_fec_status1_cl49TxEEEStates_c_TX_SLEEP 1 7142 #define rx_x4_rs_fec_status1_cl49TxEEEStates_c_TX_ACTIVE 0 7143 7144 /**************************************************************************** 7145 * Enums: rx_x4_rs_fec_status1_cl36RxEEEStates_l 7146 */ 7147 #define rx_x4_rs_fec_status1_cl36RxEEEStates_l_RX_LINK_FAIL 32 7148 #define rx_x4_rs_fec_status1_cl36RxEEEStates_l_RX_WTF 16 7149 #define rx_x4_rs_fec_status1_cl36RxEEEStates_l_RX_WAKE 8 7150 #define rx_x4_rs_fec_status1_cl36RxEEEStates_l_RX_QUIET 4 7151 #define rx_x4_rs_fec_status1_cl36RxEEEStates_l_RX_SLEEP 2 7152 #define rx_x4_rs_fec_status1_cl36RxEEEStates_l_RX_ACTIVE 1 7153 7154 /**************************************************************************** 7155 * Enums: rx_x4_rs_fec_status1_cl36RxEEEStates_c 7156 */ 7157 #define rx_x4_rs_fec_status1_cl36RxEEEStates_c_RX_LINK_FAIL 5 7158 #define rx_x4_rs_fec_status1_cl36RxEEEStates_c_RX_WTF 4 7159 #define rx_x4_rs_fec_status1_cl36RxEEEStates_c_RX_WAKE 3 7160 #define rx_x4_rs_fec_status1_cl36RxEEEStates_c_RX_QUIET 2 7161 #define rx_x4_rs_fec_status1_cl36RxEEEStates_c_RX_SLEEP 1 7162 #define rx_x4_rs_fec_status1_cl36RxEEEStates_c_RX_ACTIVE 0 7163 7164 /**************************************************************************** 7165 * Enums: rx_x4_rs_fec_status1_cl49RxEEEStates_l 7166 */ 7167 #define rx_x4_rs_fec_status1_cl49RxEEEStates_l_RX_LINK_FAIL 32 7168 #define rx_x4_rs_fec_status1_cl49RxEEEStates_l_RX_WTF 16 7169 #define rx_x4_rs_fec_status1_cl49RxEEEStates_l_RX_WAKE 8 7170 #define rx_x4_rs_fec_status1_cl49RxEEEStates_l_RX_QUIET 4 7171 #define rx_x4_rs_fec_status1_cl49RxEEEStates_l_RX_SLEEP 2 7172 #define rx_x4_rs_fec_status1_cl49RxEEEStates_l_RX_ACTIVE 1 7173 7174 /**************************************************************************** 7175 * Enums: rx_x4_rs_fec_status1_cl49RxEEEStates_c 7176 */ 7177 #define rx_x4_rs_fec_status1_cl49RxEEEStates_c_RX_LINK_FAIL 5 7178 #define rx_x4_rs_fec_status1_cl49RxEEEStates_c_RX_WTF 4 7179 #define rx_x4_rs_fec_status1_cl49RxEEEStates_c_RX_WAKE 3 7180 #define rx_x4_rs_fec_status1_cl49RxEEEStates_c_RX_QUIET 2 7181 #define rx_x4_rs_fec_status1_cl49RxEEEStates_c_RX_SLEEP 1 7182 #define rx_x4_rs_fec_status1_cl49RxEEEStates_c_RX_ACTIVE 0 7183 7184 /**************************************************************************** 7185 * Enums: rx_x4_rs_fec_status1_cl48TxEEEStates_l 7186 */ 7187 #define rx_x4_rs_fec_status1_cl48TxEEEStates_l_TX_REFRESH 8 7188 #define rx_x4_rs_fec_status1_cl48TxEEEStates_l_TX_QUIET 4 7189 #define rx_x4_rs_fec_status1_cl48TxEEEStates_l_TX_SLEEP 2 7190 #define rx_x4_rs_fec_status1_cl48TxEEEStates_l_TX_ACTIVE 1 7191 7192 /**************************************************************************** 7193 * Enums: rx_x4_rs_fec_status1_cl48TxEEEStates_c 7194 */ 7195 #define rx_x4_rs_fec_status1_cl48TxEEEStates_c_TX_REFRESH 3 7196 #define rx_x4_rs_fec_status1_cl48TxEEEStates_c_TX_QUIET 2 7197 #define rx_x4_rs_fec_status1_cl48TxEEEStates_c_TX_SLEEP 1 7198 #define rx_x4_rs_fec_status1_cl48TxEEEStates_c_TX_ACTIVE 0 7199 7200 /**************************************************************************** 7201 * Enums: rx_x4_rs_fec_status1_cl48RxEEEStates_l 7202 */ 7203 #define rx_x4_rs_fec_status1_cl48RxEEEStates_l_RX_LINK_FAIL 32 7204 #define rx_x4_rs_fec_status1_cl48RxEEEStates_l_RX_WAKE 16 7205 #define rx_x4_rs_fec_status1_cl48RxEEEStates_l_RX_QUIET 8 7206 #define rx_x4_rs_fec_status1_cl48RxEEEStates_l_RX_DEACT 4 7207 #define rx_x4_rs_fec_status1_cl48RxEEEStates_l_RX_SLEEP 2 7208 #define rx_x4_rs_fec_status1_cl48RxEEEStates_l_RX_ACTIVE 1 7209 7210 /**************************************************************************** 7211 * Enums: rx_x4_rs_fec_status1_cl48RxEEEStates_c 7212 */ 7213 #define rx_x4_rs_fec_status1_cl48RxEEEStates_c_RX_LINK_FAIL 5 7214 #define rx_x4_rs_fec_status1_cl48RxEEEStates_c_RX_WAKE 4 7215 #define rx_x4_rs_fec_status1_cl48RxEEEStates_c_RX_QUIET 3 7216 #define rx_x4_rs_fec_status1_cl48RxEEEStates_c_RX_DEACT 2 7217 #define rx_x4_rs_fec_status1_cl48RxEEEStates_c_RX_SLEEP 1 7218 #define rx_x4_rs_fec_status1_cl48RxEEEStates_c_RX_ACTIVE 0 7219 7220 /**************************************************************************** 7221 * Enums: rx_x4_rs_fec_status1_IQP_Options 7222 */ 7223 #define rx_x4_rs_fec_status1_IQP_Options_i50uA 0 7224 #define rx_x4_rs_fec_status1_IQP_Options_i100uA 1 7225 #define rx_x4_rs_fec_status1_IQP_Options_i150uA 2 7226 #define rx_x4_rs_fec_status1_IQP_Options_i200uA 3 7227 #define rx_x4_rs_fec_status1_IQP_Options_i250uA 4 7228 #define rx_x4_rs_fec_status1_IQP_Options_i300uA 5 7229 #define rx_x4_rs_fec_status1_IQP_Options_i350uA 6 7230 #define rx_x4_rs_fec_status1_IQP_Options_i400uA 7 7231 #define rx_x4_rs_fec_status1_IQP_Options_i450uA 8 7232 #define rx_x4_rs_fec_status1_IQP_Options_i500uA 9 7233 #define rx_x4_rs_fec_status1_IQP_Options_i550uA 10 7234 #define rx_x4_rs_fec_status1_IQP_Options_i600uA 11 7235 #define rx_x4_rs_fec_status1_IQP_Options_i650uA 12 7236 #define rx_x4_rs_fec_status1_IQP_Options_i700uA 13 7237 #define rx_x4_rs_fec_status1_IQP_Options_i750uA 14 7238 #define rx_x4_rs_fec_status1_IQP_Options_i800uA 15 7239 7240 /**************************************************************************** 7241 * Enums: rx_x4_rs_fec_status1_IDriver_Options 7242 */ 7243 #define rx_x4_rs_fec_status1_IDriver_Options_v680mV 0 7244 #define rx_x4_rs_fec_status1_IDriver_Options_v730mV 1 7245 #define rx_x4_rs_fec_status1_IDriver_Options_v780mV 2 7246 #define rx_x4_rs_fec_status1_IDriver_Options_v830mV 3 7247 #define rx_x4_rs_fec_status1_IDriver_Options_v880mV 4 7248 #define rx_x4_rs_fec_status1_IDriver_Options_v930mV 5 7249 #define rx_x4_rs_fec_status1_IDriver_Options_v980mV 6 7250 #define rx_x4_rs_fec_status1_IDriver_Options_v1010mV 7 7251 #define rx_x4_rs_fec_status1_IDriver_Options_v1040mV 8 7252 #define rx_x4_rs_fec_status1_IDriver_Options_v1060mV 9 7253 #define rx_x4_rs_fec_status1_IDriver_Options_v1070mV 10 7254 #define rx_x4_rs_fec_status1_IDriver_Options_v1080mV 11 7255 #define rx_x4_rs_fec_status1_IDriver_Options_v1085mV 12 7256 #define rx_x4_rs_fec_status1_IDriver_Options_v1090mV 13 7257 #define rx_x4_rs_fec_status1_IDriver_Options_v1095mV 14 7258 #define rx_x4_rs_fec_status1_IDriver_Options_v1100mV 15 7259 7260 /**************************************************************************** 7261 * Enums: rx_x4_rs_fec_status1_operationModes 7262 */ 7263 #define rx_x4_rs_fec_status1_operationModes_XGXS 0 7264 #define rx_x4_rs_fec_status1_operationModes_XGXG_nCC 1 7265 #define rx_x4_rs_fec_status1_operationModes_Indlane_OS8 4 7266 #define rx_x4_rs_fec_status1_operationModes_IndLane_OS5 5 7267 #define rx_x4_rs_fec_status1_operationModes_PCI 7 7268 #define rx_x4_rs_fec_status1_operationModes_XGXS_nLQ 8 7269 #define rx_x4_rs_fec_status1_operationModes_XGXS_nLQnCC 9 7270 #define rx_x4_rs_fec_status1_operationModes_PBypass 10 7271 #define rx_x4_rs_fec_status1_operationModes_PBypass_nDSK 11 7272 #define rx_x4_rs_fec_status1_operationModes_ComboCoreMode 12 7273 #define rx_x4_rs_fec_status1_operationModes_Clocks_off 15 7274 7275 /**************************************************************************** 7276 * Enums: rx_x4_rs_fec_status1_actualSpeeds 7277 */ 7278 #define rx_x4_rs_fec_status1_actualSpeeds_dr_10M 0 7279 #define rx_x4_rs_fec_status1_actualSpeeds_dr_100M 1 7280 #define rx_x4_rs_fec_status1_actualSpeeds_dr_1G 2 7281 #define rx_x4_rs_fec_status1_actualSpeeds_dr_2p5G 3 7282 #define rx_x4_rs_fec_status1_actualSpeeds_dr_5G_X4 4 7283 #define rx_x4_rs_fec_status1_actualSpeeds_dr_6G_X4 5 7284 #define rx_x4_rs_fec_status1_actualSpeeds_dr_10G_HiG 6 7285 #define rx_x4_rs_fec_status1_actualSpeeds_dr_10G_CX4 7 7286 #define rx_x4_rs_fec_status1_actualSpeeds_dr_12G_HiG 8 7287 #define rx_x4_rs_fec_status1_actualSpeeds_dr_12p5G_X4 9 7288 #define rx_x4_rs_fec_status1_actualSpeeds_dr_13G_X4 10 7289 #define rx_x4_rs_fec_status1_actualSpeeds_dr_15G_X4 11 7290 #define rx_x4_rs_fec_status1_actualSpeeds_dr_16G_X4 12 7291 #define rx_x4_rs_fec_status1_actualSpeeds_dr_1G_KX 13 7292 #define rx_x4_rs_fec_status1_actualSpeeds_dr_10G_KX4 14 7293 #define rx_x4_rs_fec_status1_actualSpeeds_dr_10G_KR 15 7294 #define rx_x4_rs_fec_status1_actualSpeeds_dr_5G 16 7295 #define rx_x4_rs_fec_status1_actualSpeeds_dr_6p4G 17 7296 #define rx_x4_rs_fec_status1_actualSpeeds_dr_20G_X4 18 7297 #define rx_x4_rs_fec_status1_actualSpeeds_dr_21G_X4 19 7298 #define rx_x4_rs_fec_status1_actualSpeeds_dr_25G_X4 20 7299 #define rx_x4_rs_fec_status1_actualSpeeds_dr_10G_HiG_DXGXS 21 7300 #define rx_x4_rs_fec_status1_actualSpeeds_dr_10G_DXGXS 22 7301 #define rx_x4_rs_fec_status1_actualSpeeds_dr_10p5G_HiG_DXGXS 23 7302 #define rx_x4_rs_fec_status1_actualSpeeds_dr_10p5G_DXGXS 24 7303 #define rx_x4_rs_fec_status1_actualSpeeds_dr_12p773G_HiG_DXGXS 25 7304 #define rx_x4_rs_fec_status1_actualSpeeds_dr_12p773G_DXGXS 26 7305 #define rx_x4_rs_fec_status1_actualSpeeds_dr_10G_XFI 27 7306 #define rx_x4_rs_fec_status1_actualSpeeds_dr_40G 28 7307 #define rx_x4_rs_fec_status1_actualSpeeds_dr_20G_HiG_DXGXS 29 7308 #define rx_x4_rs_fec_status1_actualSpeeds_dr_20G_DXGXS 30 7309 #define rx_x4_rs_fec_status1_actualSpeeds_dr_10G_SFI 31 7310 #define rx_x4_rs_fec_status1_actualSpeeds_dr_31p5G 32 7311 #define rx_x4_rs_fec_status1_actualSpeeds_dr_32p7G 33 7312 #define rx_x4_rs_fec_status1_actualSpeeds_dr_20G_SCR 34 7313 #define rx_x4_rs_fec_status1_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 7314 #define rx_x4_rs_fec_status1_actualSpeeds_dr_10G_DXGXS_SCR 36 7315 #define rx_x4_rs_fec_status1_actualSpeeds_dr_12G_R2 37 7316 #define rx_x4_rs_fec_status1_actualSpeeds_dr_10G_X2 38 7317 #define rx_x4_rs_fec_status1_actualSpeeds_dr_40G_KR4 39 7318 #define rx_x4_rs_fec_status1_actualSpeeds_dr_40G_CR4 40 7319 #define rx_x4_rs_fec_status1_actualSpeeds_dr_100G_CR10 41 7320 #define rx_x4_rs_fec_status1_actualSpeeds_dr_15p75G_DXGXS 44 7321 #define rx_x4_rs_fec_status1_actualSpeeds_dr_20G_KR2 57 7322 #define rx_x4_rs_fec_status1_actualSpeeds_dr_20G_CR2 58 7323 7324 /**************************************************************************** 7325 * Enums: rx_x4_rs_fec_status1_actualSpeedsMisc1 7326 */ 7327 #define rx_x4_rs_fec_status1_actualSpeedsMisc1_dr_2500BRCM_X1 16 7328 #define rx_x4_rs_fec_status1_actualSpeedsMisc1_dr_5000BRCM_X4 17 7329 #define rx_x4_rs_fec_status1_actualSpeedsMisc1_dr_6000BRCM_X4 18 7330 #define rx_x4_rs_fec_status1_actualSpeedsMisc1_dr_10GHiGig_X4 19 7331 #define rx_x4_rs_fec_status1_actualSpeedsMisc1_dr_10GBASE_CX4 20 7332 #define rx_x4_rs_fec_status1_actualSpeedsMisc1_dr_12GHiGig_X4 21 7333 #define rx_x4_rs_fec_status1_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 7334 #define rx_x4_rs_fec_status1_actualSpeedsMisc1_dr_13GHiGig_X4 23 7335 #define rx_x4_rs_fec_status1_actualSpeedsMisc1_dr_15GHiGig_X4 24 7336 #define rx_x4_rs_fec_status1_actualSpeedsMisc1_dr_16GHiGig_X4 25 7337 #define rx_x4_rs_fec_status1_actualSpeedsMisc1_dr_5000BRCM_X1 26 7338 #define rx_x4_rs_fec_status1_actualSpeedsMisc1_dr_6363BRCM_X1 27 7339 #define rx_x4_rs_fec_status1_actualSpeedsMisc1_dr_20GHiGig_X4 28 7340 #define rx_x4_rs_fec_status1_actualSpeedsMisc1_dr_21GHiGig_X4 29 7341 #define rx_x4_rs_fec_status1_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 7342 #define rx_x4_rs_fec_status1_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 7343 7344 /**************************************************************************** 7345 * Enums: rx_x4_rs_fec_status1_IndLaneModes 7346 */ 7347 #define rx_x4_rs_fec_status1_IndLaneModes_SWSDR_div2 0 7348 #define rx_x4_rs_fec_status1_IndLaneModes_SWSDR_div1 1 7349 #define rx_x4_rs_fec_status1_IndLaneModes_DWSDR_div2 2 7350 #define rx_x4_rs_fec_status1_IndLaneModes_DWSDR_div1 3 7351 7352 /**************************************************************************** 7353 * Enums: rx_x4_rs_fec_status1_prbsSelect 7354 */ 7355 #define rx_x4_rs_fec_status1_prbsSelect_prbs7 0 7356 #define rx_x4_rs_fec_status1_prbsSelect_prbs15 1 7357 #define rx_x4_rs_fec_status1_prbsSelect_prbs23 2 7358 #define rx_x4_rs_fec_status1_prbsSelect_prbs31 3 7359 7360 /**************************************************************************** 7361 * Enums: rx_x4_rs_fec_status1_vcoDivider 7362 */ 7363 #define rx_x4_rs_fec_status1_vcoDivider_div32 0 7364 #define rx_x4_rs_fec_status1_vcoDivider_div36 1 7365 #define rx_x4_rs_fec_status1_vcoDivider_div40 2 7366 #define rx_x4_rs_fec_status1_vcoDivider_div42 3 7367 #define rx_x4_rs_fec_status1_vcoDivider_div48 4 7368 #define rx_x4_rs_fec_status1_vcoDivider_div50 5 7369 #define rx_x4_rs_fec_status1_vcoDivider_div52 6 7370 #define rx_x4_rs_fec_status1_vcoDivider_div54 7 7371 #define rx_x4_rs_fec_status1_vcoDivider_div60 8 7372 #define rx_x4_rs_fec_status1_vcoDivider_div64 9 7373 #define rx_x4_rs_fec_status1_vcoDivider_div66 10 7374 #define rx_x4_rs_fec_status1_vcoDivider_div68 11 7375 #define rx_x4_rs_fec_status1_vcoDivider_div70 12 7376 #define rx_x4_rs_fec_status1_vcoDivider_div80 13 7377 #define rx_x4_rs_fec_status1_vcoDivider_div92 14 7378 #define rx_x4_rs_fec_status1_vcoDivider_div100 15 7379 7380 /**************************************************************************** 7381 * Enums: rx_x4_rs_fec_status1_refClkSelect 7382 */ 7383 #define rx_x4_rs_fec_status1_refClkSelect_clk_156p25MHz 1 7384 #define rx_x4_rs_fec_status1_refClkSelect_clk_312p5Mhz 2 7385 7386 /**************************************************************************** 7387 * Enums: rx_x4_rs_fec_status1_aerMMDdevTypeSelect 7388 */ 7389 #define rx_x4_rs_fec_status1_aerMMDdevTypeSelect_combo_core 0 7390 #define rx_x4_rs_fec_status1_aerMMDdevTypeSelect_PMA_PMD 1 7391 #define rx_x4_rs_fec_status1_aerMMDdevTypeSelect_PCS 3 7392 #define rx_x4_rs_fec_status1_aerMMDdevTypeSelect_PHY 4 7393 #define rx_x4_rs_fec_status1_aerMMDdevTypeSelect_DTE 5 7394 #define rx_x4_rs_fec_status1_aerMMDdevTypeSelect_CL73_AN 7 7395 7396 /**************************************************************************** 7397 * Enums: rx_x4_rs_fec_status1_aerMMDportSelect 7398 */ 7399 #define rx_x4_rs_fec_status1_aerMMDportSelect_ln0 0 7400 #define rx_x4_rs_fec_status1_aerMMDportSelect_ln1 1 7401 #define rx_x4_rs_fec_status1_aerMMDportSelect_ln2 2 7402 #define rx_x4_rs_fec_status1_aerMMDportSelect_ln3 3 7403 #define rx_x4_rs_fec_status1_aerMMDportSelect_BCST_ln0_1_2_3 511 7404 #define rx_x4_rs_fec_status1_aerMMDportSelect_BCST_ln0_1 512 7405 #define rx_x4_rs_fec_status1_aerMMDportSelect_BCST_ln2_3 513 7406 7407 /**************************************************************************** 7408 * Enums: rx_x4_rs_fec_status1_firmwareModeSelect 7409 */ 7410 #define rx_x4_rs_fec_status1_firmwareModeSelect_DEFAULT 0 7411 #define rx_x4_rs_fec_status1_firmwareModeSelect_SFP_OPT_LR 1 7412 #define rx_x4_rs_fec_status1_firmwareModeSelect_SFP_DAC 2 7413 #define rx_x4_rs_fec_status1_firmwareModeSelect_XLAUI 3 7414 #define rx_x4_rs_fec_status1_firmwareModeSelect_LONG_CH_6G 4 7415 7416 /**************************************************************************** 7417 * Enums: rx_x4_rs_fec_status1_tempIdxSelect 7418 */ 7419 #define rx_x4_rs_fec_status1_tempIdxSelect_LTE__22p9C 15 7420 #define rx_x4_rs_fec_status1_tempIdxSelect_LTE__12p6C 14 7421 #define rx_x4_rs_fec_status1_tempIdxSelect_LTE__3p0C 13 7422 #define rx_x4_rs_fec_status1_tempIdxSelect_LTE_6p7C 12 7423 #define rx_x4_rs_fec_status1_tempIdxSelect_LTE_16p4C 11 7424 #define rx_x4_rs_fec_status1_tempIdxSelect_LTE_26p6C 10 7425 #define rx_x4_rs_fec_status1_tempIdxSelect_LTE_36p3C 9 7426 #define rx_x4_rs_fec_status1_tempIdxSelect_LTE_46p0C 8 7427 #define rx_x4_rs_fec_status1_tempIdxSelect_LTE_56p2C 7 7428 #define rx_x4_rs_fec_status1_tempIdxSelect_LTE_65p9C 6 7429 #define rx_x4_rs_fec_status1_tempIdxSelect_LTE_75p6C 5 7430 #define rx_x4_rs_fec_status1_tempIdxSelect_LTE_85p3C 4 7431 #define rx_x4_rs_fec_status1_tempIdxSelect_LTE_95p5C 3 7432 #define rx_x4_rs_fec_status1_tempIdxSelect_LTE_105p2C 2 7433 #define rx_x4_rs_fec_status1_tempIdxSelect_LTE_114p9C 1 7434 #define rx_x4_rs_fec_status1_tempIdxSelect_LTE_125p1C 0 7435 7436 /**************************************************************************** 7437 * Enums: rx_x4_rs_fec_status1_port_mode 7438 */ 7439 #define rx_x4_rs_fec_status1_port_mode_QUAD_PORT 0 7440 #define rx_x4_rs_fec_status1_port_mode_TRI_1_PORT 1 7441 #define rx_x4_rs_fec_status1_port_mode_TRI_2_PORT 2 7442 #define rx_x4_rs_fec_status1_port_mode_DUAL_PORT 3 7443 #define rx_x4_rs_fec_status1_port_mode_SINGLE_PORT 4 7444 #define rx_x4_rs_fec_status1_port_mode_SINGLE_OCTAL_PORT 5 7445 7446 /**************************************************************************** 7447 * Enums: rx_x4_rs_fec_status1_rev_letter_enum 7448 */ 7449 #define rx_x4_rs_fec_status1_rev_letter_enum_REV_A 0 7450 #define rx_x4_rs_fec_status1_rev_letter_enum_REV_B 1 7451 #define rx_x4_rs_fec_status1_rev_letter_enum_REV_C 2 7452 #define rx_x4_rs_fec_status1_rev_letter_enum_REV_D 3 7453 7454 /**************************************************************************** 7455 * Enums: rx_x4_rs_fec_status1_rev_number_enum 7456 */ 7457 #define rx_x4_rs_fec_status1_rev_number_enum_REV_0 0 7458 #define rx_x4_rs_fec_status1_rev_number_enum_REV_1 1 7459 #define rx_x4_rs_fec_status1_rev_number_enum_REV_2 2 7460 #define rx_x4_rs_fec_status1_rev_number_enum_REV_3 3 7461 #define rx_x4_rs_fec_status1_rev_number_enum_REV_4 4 7462 #define rx_x4_rs_fec_status1_rev_number_enum_REV_5 5 7463 #define rx_x4_rs_fec_status1_rev_number_enum_REV_6 6 7464 #define rx_x4_rs_fec_status1_rev_number_enum_REV_7 7 7465 7466 /**************************************************************************** 7467 * Enums: rx_x4_rs_fec_status1_bonding_enum 7468 */ 7469 #define rx_x4_rs_fec_status1_bonding_enum_WIRE_BOND 0 7470 #define rx_x4_rs_fec_status1_bonding_enum_FLIP_CHIP 1 7471 7472 /**************************************************************************** 7473 * Enums: rx_x4_rs_fec_status1_tech_process 7474 */ 7475 #define rx_x4_rs_fec_status1_tech_process_PROCESS_90NM 0 7476 #define rx_x4_rs_fec_status1_tech_process_PROCESS_65NM 1 7477 #define rx_x4_rs_fec_status1_tech_process_PROCESS_40NM 2 7478 #define rx_x4_rs_fec_status1_tech_process_PROCESS_28NM 3 7479 #define rx_x4_rs_fec_status1_tech_process_PROCESS_16NM 4 7480 7481 /**************************************************************************** 7482 * Enums: rx_x4_rs_fec_status1_model_num 7483 */ 7484 #define rx_x4_rs_fec_status1_model_num_SERDES_CL73 0 7485 #define rx_x4_rs_fec_status1_model_num_XGXS_16G 1 7486 #define rx_x4_rs_fec_status1_model_num_HYPERCORE 2 7487 #define rx_x4_rs_fec_status1_model_num_HYPERLITE 3 7488 #define rx_x4_rs_fec_status1_model_num_PCIE_G2_PIPE 4 7489 #define rx_x4_rs_fec_status1_model_num_SERDES_1p25GBd 5 7490 #define rx_x4_rs_fec_status1_model_num_SATA2 6 7491 #define rx_x4_rs_fec_status1_model_num_QSGMII 7 7492 #define rx_x4_rs_fec_status1_model_num_XGXS10G 8 7493 #define rx_x4_rs_fec_status1_model_num_WARPCORE 9 7494 #define rx_x4_rs_fec_status1_model_num_XFICORE 10 7495 #define rx_x4_rs_fec_status1_model_num_RXFI 11 7496 #define rx_x4_rs_fec_status1_model_num_WARPLITE 12 7497 #define rx_x4_rs_fec_status1_model_num_PENTACORE 13 7498 #define rx_x4_rs_fec_status1_model_num_ESM 14 7499 #define rx_x4_rs_fec_status1_model_num_QUAD_SGMII 15 7500 #define rx_x4_rs_fec_status1_model_num_WARPCORE_3 16 7501 #define rx_x4_rs_fec_status1_model_num_TSC 17 7502 #define rx_x4_rs_fec_status1_model_num_TSC4E 18 7503 #define rx_x4_rs_fec_status1_model_num_TSC12E 19 7504 #define rx_x4_rs_fec_status1_model_num_TSC4F 20 7505 #define rx_x4_rs_fec_status1_model_num_TSC4F_GEN2 21 7506 #define rx_x4_rs_fec_status1_model_num_XGXS_CL73_90NM 29 7507 #define rx_x4_rs_fec_status1_model_num_SERDES_CL73_90NM 30 7508 #define rx_x4_rs_fec_status1_model_num_WARPCORE3 32 7509 #define rx_x4_rs_fec_status1_model_num_WARPCORE4_TSC 33 7510 #define rx_x4_rs_fec_status1_model_num_RXAUI 34 7511 #define rx_x4_rs_fec_status1_model_num_TSCE_GEN3 35 7512 #define rx_x4_rs_fec_status1_model_num_TSC4F_GEN3 36 7513 #define rx_x4_rs_fec_status1_model_num_TSCBH 37 7514 7515 /**************************************************************************** 7516 * Enums: rx_x4_rs_fec_status1_payload 7517 */ 7518 #define rx_x4_rs_fec_status1_payload_REPEAT_2_BYTES 0 7519 #define rx_x4_rs_fec_status1_payload_RAMPING 1 7520 #define rx_x4_rs_fec_status1_payload_CL48_CRPAT 2 7521 #define rx_x4_rs_fec_status1_payload_CL48_CJPAT 3 7522 #define rx_x4_rs_fec_status1_payload_CL36_LONG_CRPAT 4 7523 #define rx_x4_rs_fec_status1_payload_CL36_SHORT_CRPAT 5 7524 7525 /**************************************************************************** 7526 * Enums: rx_x4_rs_fec_status1_sc 7527 */ 7528 #define rx_x4_rs_fec_status1_sc_SPEED_10G_IEEE_KR1 0 7529 #define rx_x4_rs_fec_status1_sc_SPEED_25G_IEEE_KS1_CS1 1 7530 #define rx_x4_rs_fec_status1_sc_SPEED_25G_IEEE_KR1_CR1 2 7531 #define rx_x4_rs_fec_status1_sc_SPEED_40G_IEEE_KR4 3 7532 #define rx_x4_rs_fec_status1_sc_SPEED_40G_IEEE_CR4 4 7533 #define rx_x4_rs_fec_status1_sc_SPEED_50G_IEEE_KR1_CR1 5 7534 #define rx_x4_rs_fec_status1_sc_SPEED_100G_IEEE_KR4 6 7535 #define rx_x4_rs_fec_status1_sc_SPEED_100G_IEEE_CR4 7 7536 #define rx_x4_rs_fec_status1_sc_SPEED_100G_IEEE_KR2_CR2 8 7537 #define rx_x4_rs_fec_status1_sc_SPEED_200G_IEEE_KR4_CR4 9 7538 #define rx_x4_rs_fec_status1_sc_SPEED_400G_IEEE_X8 10 7539 #define rx_x4_rs_fec_status1_sc_SPEED_CL73_IEEE_20GVCO 11 7540 #define rx_x4_rs_fec_status1_sc_SPEED_CL73_IEEE_25GVCO 12 7541 #define rx_x4_rs_fec_status1_sc_SPEED_CL73_IEEE_26GVCO 13 7542 #define rx_x4_rs_fec_status1_sc_SPEED_20G_BRCM_CR1 14 7543 #define rx_x4_rs_fec_status1_sc_SPEED_20G_BRCM_KR1 15 7544 #define rx_x4_rs_fec_status1_sc_SPEED_25G_BRCM_CR1 16 7545 #define rx_x4_rs_fec_status1_sc_SPEED_25G_BRCM_KR1 17 7546 #define rx_x4_rs_fec_status1_sc_SPEED_40G_BRCM_CR2 18 7547 #define rx_x4_rs_fec_status1_sc_SPEED_40G_BRCM_KR2 19 7548 #define rx_x4_rs_fec_status1_sc_SPEED_50G_BRCM_CR2 20 7549 #define rx_x4_rs_fec_status1_sc_SPEED_50G_BRCM_KR2 21 7550 #define rx_x4_rs_fec_status1_sc_SPEED_50G_BRCM_CR4 22 7551 #define rx_x4_rs_fec_status1_sc_SPEED_50G_BRCM_KR4 23 7552 #define rx_x4_rs_fec_status1_sc_SPEED_50G_BRCM_FEC_544_CR2_KR2 24 7553 #define rx_x4_rs_fec_status1_sc_SPEED_RESERVED_19 25 7554 #define rx_x4_rs_fec_status1_sc_SPEED_50G_BRCM_FEC_544_CR1_KR1 26 7555 #define rx_x4_rs_fec_status1_sc_SPEED_50G_BRCM_NO_FEC_CR1_KR1 27 7556 #define rx_x4_rs_fec_status1_sc_SPEED_50G_BRCM_FEC_528_CR1_KR1 28 7557 #define rx_x4_rs_fec_status1_sc_SPEED_400G_BRCM_NO_FEC_KR8_CR8 29 7558 #define rx_x4_rs_fec_status1_sc_SPEED_400G_BRCM_FEC_KR8_CR8 30 7559 #define rx_x4_rs_fec_status1_sc_SPEED_200G_BRCM_NO_FEC_KR4_CR4 31 7560 #define rx_x4_rs_fec_status1_sc_SPEED_200G_BRCM_KR4_CR4 32 7561 #define rx_x4_rs_fec_status1_sc_SPEED_100G_BRCM_KR4_CR4 33 7562 #define rx_x4_rs_fec_status1_sc_SPEED_RESERVED_22 34 7563 #define rx_x4_rs_fec_status1_sc_SPEED_100G_BRCM_FEC_528_KR2_CR2 35 7564 #define rx_x4_rs_fec_status1_sc_SPEED_100G_BRCM_NO_FEC_KR2_CR2 36 7565 #define rx_x4_rs_fec_status1_sc_SPEED_100G_BRCM_NO_FEC_X4 37 7566 7567 /**************************************************************************** 7568 * Enums: rx_x4_rs_fec_status1_t_fifo_modes 7569 */ 7570 #define rx_x4_rs_fec_status1_t_fifo_modes_T_FIFO_INSERT_NO_AM 0 7571 #define rx_x4_rs_fec_status1_t_fifo_modes_T_FIFO_INSERT_4_AM 1 7572 #define rx_x4_rs_fec_status1_t_fifo_modes_T_FIFO_INSERT_20_AM 2 7573 #define rx_x4_rs_fec_status1_t_fifo_modes_T_FIFO_INSERT_2_AM 3 7574 7575 /**************************************************************************** 7576 * Enums: rx_x4_rs_fec_status1_t_enc_modes 7577 */ 7578 #define rx_x4_rs_fec_status1_t_enc_modes_T_ENC_MODE_BYPASS 0 7579 #define rx_x4_rs_fec_status1_t_enc_modes_T_ENC_MODE_CL49 1 7580 #define rx_x4_rs_fec_status1_t_enc_modes_T_ENC_MODE_CL82 2 7581 7582 /**************************************************************************** 7583 * Enums: rx_x4_rs_fec_status1_btmx_mode 7584 */ 7585 #define rx_x4_rs_fec_status1_btmx_mode_BS_BTMX_MODE_1to1 0 7586 #define rx_x4_rs_fec_status1_btmx_mode_BS_BTMX_MODE_2to1 1 7587 #define rx_x4_rs_fec_status1_btmx_mode_BS_BTMX_MODE_5to1 2 7588 7589 /**************************************************************************** 7590 * Enums: rx_x4_rs_fec_status1_t_type_cl82 7591 */ 7592 #define rx_x4_rs_fec_status1_t_type_cl82_T_TYPE_B1 5 7593 #define rx_x4_rs_fec_status1_t_type_cl82_T_TYPE_C 4 7594 #define rx_x4_rs_fec_status1_t_type_cl82_T_TYPE_S 3 7595 #define rx_x4_rs_fec_status1_t_type_cl82_T_TYPE_T 2 7596 #define rx_x4_rs_fec_status1_t_type_cl82_T_TYPE_D 1 7597 #define rx_x4_rs_fec_status1_t_type_cl82_T_TYPE_E 0 7598 7599 /**************************************************************************** 7600 * Enums: rx_x4_rs_fec_status1_txsm_state_cl82 7601 */ 7602 #define rx_x4_rs_fec_status1_txsm_state_cl82_TX_E 4 7603 #define rx_x4_rs_fec_status1_txsm_state_cl82_TX_T 3 7604 #define rx_x4_rs_fec_status1_txsm_state_cl82_TX_D 2 7605 #define rx_x4_rs_fec_status1_txsm_state_cl82_TX_C 1 7606 #define rx_x4_rs_fec_status1_txsm_state_cl82_TX_INIT 0 7607 7608 /**************************************************************************** 7609 * Enums: rx_x4_rs_fec_status1_ltxsm_state_cl82 7610 */ 7611 #define rx_x4_rs_fec_status1_ltxsm_state_cl82_TX_E 16 7612 #define rx_x4_rs_fec_status1_ltxsm_state_cl82_TX_T 8 7613 #define rx_x4_rs_fec_status1_ltxsm_state_cl82_TX_D 4 7614 #define rx_x4_rs_fec_status1_ltxsm_state_cl82_TX_C 2 7615 #define rx_x4_rs_fec_status1_ltxsm_state_cl82_TX_INIT 1 7616 7617 /**************************************************************************** 7618 * Enums: rx_x4_rs_fec_status1_r_type_coded_cl82 7619 */ 7620 #define rx_x4_rs_fec_status1_r_type_coded_cl82_R_TYPE_B1 32 7621 #define rx_x4_rs_fec_status1_r_type_coded_cl82_R_TYPE_C 16 7622 #define rx_x4_rs_fec_status1_r_type_coded_cl82_R_TYPE_S 8 7623 #define rx_x4_rs_fec_status1_r_type_coded_cl82_R_TYPE_T 4 7624 #define rx_x4_rs_fec_status1_r_type_coded_cl82_R_TYPE_D 2 7625 #define rx_x4_rs_fec_status1_r_type_coded_cl82_R_TYPE_E 1 7626 7627 /**************************************************************************** 7628 * Enums: rx_x4_rs_fec_status1_rxsm_state_cl82 7629 */ 7630 #define rx_x4_rs_fec_status1_rxsm_state_cl82_RX_E 16 7631 #define rx_x4_rs_fec_status1_rxsm_state_cl82_RX_T 8 7632 #define rx_x4_rs_fec_status1_rxsm_state_cl82_RX_D 4 7633 #define rx_x4_rs_fec_status1_rxsm_state_cl82_RX_C 2 7634 #define rx_x4_rs_fec_status1_rxsm_state_cl82_RX_INIT 1 7635 7636 /**************************************************************************** 7637 * Enums: rx_x4_rs_fec_status1_deskew_state 7638 */ 7639 #define rx_x4_rs_fec_status1_deskew_state_ALIGN_ACQUIRED 2 7640 #define rx_x4_rs_fec_status1_deskew_state_LOSS_OF_ALIGNMENT 1 7641 7642 /**************************************************************************** 7643 * Enums: rx_x4_rs_fec_status1_os_mode_enum 7644 */ 7645 #define rx_x4_rs_fec_status1_os_mode_enum_OS_MODE_1 0 7646 #define rx_x4_rs_fec_status1_os_mode_enum_OS_MODE_2 1 7647 #define rx_x4_rs_fec_status1_os_mode_enum_OS_MODE_4 2 7648 #define rx_x4_rs_fec_status1_os_mode_enum_OS_MODE_16p5 8 7649 #define rx_x4_rs_fec_status1_os_mode_enum_OS_MODE_20p625 12 7650 7651 /**************************************************************************** 7652 * Enums: rx_x4_rs_fec_status1_scr_modes 7653 */ 7654 #define rx_x4_rs_fec_status1_scr_modes_T_SCR_MODE_BYPASS 0 7655 #define rx_x4_rs_fec_status1_scr_modes_T_SCR_MODE_CL49 1 7656 #define rx_x4_rs_fec_status1_scr_modes_T_SCR_MODE_40G_2_LANE 2 7657 #define rx_x4_rs_fec_status1_scr_modes_T_SCR_MODE_100G 3 7658 #define rx_x4_rs_fec_status1_scr_modes_T_SCR_MODE_20G 4 7659 #define rx_x4_rs_fec_status1_scr_modes_T_SCR_MODE_40G_4_LANE 5 7660 7661 /**************************************************************************** 7662 * Enums: rx_x4_rs_fec_status1_descr_modes 7663 */ 7664 #define rx_x4_rs_fec_status1_descr_modes_R_DESCR_MODE_BYPASS 0 7665 #define rx_x4_rs_fec_status1_descr_modes_R_DESCR_MODE_CL49 1 7666 #define rx_x4_rs_fec_status1_descr_modes_R_DESCR_MODE_CL82 2 7667 7668 /**************************************************************************** 7669 * Enums: rx_x4_rs_fec_status1_r_dec_tl_mode 7670 */ 7671 #define rx_x4_rs_fec_status1_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 7672 #define rx_x4_rs_fec_status1_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 7673 #define rx_x4_rs_fec_status1_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 7674 7675 /**************************************************************************** 7676 * Enums: rx_x4_rs_fec_status1_r_dec_fsm_mode 7677 */ 7678 #define rx_x4_rs_fec_status1_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 7679 #define rx_x4_rs_fec_status1_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 7680 #define rx_x4_rs_fec_status1_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 7681 7682 /**************************************************************************** 7683 * Enums: rx_x4_rs_fec_status1_r_deskew_mode 7684 */ 7685 #define rx_x4_rs_fec_status1_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 7686 #define rx_x4_rs_fec_status1_r_deskew_mode_R_DESKEW_MODE_20G 1 7687 #define rx_x4_rs_fec_status1_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 7688 #define rx_x4_rs_fec_status1_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 7689 #define rx_x4_rs_fec_status1_r_deskew_mode_R_DESKEW_MODE_100G 4 7690 #define rx_x4_rs_fec_status1_r_deskew_mode_R_DESKEW_MODE_CL49 5 7691 #define rx_x4_rs_fec_status1_r_deskew_mode_R_DESKEW_MODE_CL91_QUAD 6 7692 #define rx_x4_rs_fec_status1_r_deskew_mode_R_DESKEW_MODE_CL91_SINGLE_BRCM 7 7693 #define rx_x4_rs_fec_status1_r_deskew_mode_R_DESKEW_MODE_CL91_DUAL_BRCM 8 7694 #define rx_x4_rs_fec_status1_r_deskew_mode_R_DESKEW_MODE_CL91_FC 9 7695 7696 /**************************************************************************** 7697 * Enums: rx_x4_rs_fec_status1_bs_dist_modes 7698 */ 7699 #define rx_x4_rs_fec_status1_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 7700 #define rx_x4_rs_fec_status1_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 7701 #define rx_x4_rs_fec_status1_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 7702 #define rx_x4_rs_fec_status1_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 7703 7704 /**************************************************************************** 7705 * Enums: rx_x4_rs_fec_status1_cl49_t_type 7706 */ 7707 #define rx_x4_rs_fec_status1_cl49_t_type_BAD_T_TYPE 15 7708 #define rx_x4_rs_fec_status1_cl49_t_type_T_TYPE_B0 11 7709 #define rx_x4_rs_fec_status1_cl49_t_type_T_TYPE_OB 10 7710 #define rx_x4_rs_fec_status1_cl49_t_type_T_TYPE_B1 9 7711 #define rx_x4_rs_fec_status1_cl49_t_type_T_TYPE_DB 8 7712 #define rx_x4_rs_fec_status1_cl49_t_type_T_TYPE_FC 7 7713 #define rx_x4_rs_fec_status1_cl49_t_type_T_TYPE_TB 6 7714 #define rx_x4_rs_fec_status1_cl49_t_type_T_TYPE_LI 5 7715 #define rx_x4_rs_fec_status1_cl49_t_type_T_TYPE_C 4 7716 #define rx_x4_rs_fec_status1_cl49_t_type_T_TYPE_S 3 7717 #define rx_x4_rs_fec_status1_cl49_t_type_T_TYPE_T 2 7718 #define rx_x4_rs_fec_status1_cl49_t_type_T_TYPE_D 1 7719 #define rx_x4_rs_fec_status1_cl49_t_type_T_TYPE_E 0 7720 7721 /**************************************************************************** 7722 * Enums: rx_x4_rs_fec_status1_cl49_txsm_states 7723 */ 7724 #define rx_x4_rs_fec_status1_cl49_txsm_states_TX_LI 5 7725 #define rx_x4_rs_fec_status1_cl49_txsm_states_TX_E 4 7726 #define rx_x4_rs_fec_status1_cl49_txsm_states_TX_T 3 7727 #define rx_x4_rs_fec_status1_cl49_txsm_states_TX_D 2 7728 #define rx_x4_rs_fec_status1_cl49_txsm_states_TX_C 1 7729 #define rx_x4_rs_fec_status1_cl49_txsm_states_TX_INIT 0 7730 7731 /**************************************************************************** 7732 * Enums: rx_x4_rs_fec_status1_cl49_ltxsm_states 7733 */ 7734 #define rx_x4_rs_fec_status1_cl49_ltxsm_states_TX_LI 32 7735 #define rx_x4_rs_fec_status1_cl49_ltxsm_states_TX_E 16 7736 #define rx_x4_rs_fec_status1_cl49_ltxsm_states_TX_T 8 7737 #define rx_x4_rs_fec_status1_cl49_ltxsm_states_TX_D 4 7738 #define rx_x4_rs_fec_status1_cl49_ltxsm_states_TX_C 2 7739 #define rx_x4_rs_fec_status1_cl49_ltxsm_states_TX_INIT 1 7740 7741 /**************************************************************************** 7742 * Enums: rx_x4_rs_fec_status1_burst_error_mode 7743 */ 7744 #define rx_x4_rs_fec_status1_burst_error_mode_BURST_ERROR_11_BITS 0 7745 #define rx_x4_rs_fec_status1_burst_error_mode_BURST_ERROR_16_BITS 1 7746 #define rx_x4_rs_fec_status1_burst_error_mode_BURST_ERROR_17_BITS 2 7747 #define rx_x4_rs_fec_status1_burst_error_mode_BURST_ERROR_18_BITS 3 7748 #define rx_x4_rs_fec_status1_burst_error_mode_BURST_ERROR_19_BITS 4 7749 #define rx_x4_rs_fec_status1_burst_error_mode_BURST_ERROR_20_BITS 5 7750 #define rx_x4_rs_fec_status1_burst_error_mode_BURST_ERROR_21_BITS 6 7751 #define rx_x4_rs_fec_status1_burst_error_mode_BURST_ERROR_22_BITS 7 7752 #define rx_x4_rs_fec_status1_burst_error_mode_BURST_ERROR_23_BITS 8 7753 #define rx_x4_rs_fec_status1_burst_error_mode_BURST_ERROR_24_BITS 9 7754 #define rx_x4_rs_fec_status1_burst_error_mode_BURST_ERROR_25_BITS 10 7755 #define rx_x4_rs_fec_status1_burst_error_mode_BURST_ERROR_26_BITS 11 7756 #define rx_x4_rs_fec_status1_burst_error_mode_BURST_ERROR_27_BITS 12 7757 #define rx_x4_rs_fec_status1_burst_error_mode_BURST_ERROR_28_BITS 13 7758 #define rx_x4_rs_fec_status1_burst_error_mode_BURST_ERROR_29_BITS 14 7759 #define rx_x4_rs_fec_status1_burst_error_mode_BURST_ERROR_30_BITS 15 7760 #define rx_x4_rs_fec_status1_burst_error_mode_BURST_ERROR_31_BITS 16 7761 #define rx_x4_rs_fec_status1_burst_error_mode_BURST_ERROR_32_BITS 17 7762 #define rx_x4_rs_fec_status1_burst_error_mode_BURST_ERROR_33_BITS 18 7763 #define rx_x4_rs_fec_status1_burst_error_mode_BURST_ERROR_34_BITS 19 7764 #define rx_x4_rs_fec_status1_burst_error_mode_BURST_ERROR_35_BITS 20 7765 #define rx_x4_rs_fec_status1_burst_error_mode_BURST_ERROR_36_BITS 21 7766 #define rx_x4_rs_fec_status1_burst_error_mode_BURST_ERROR_37_BITS 22 7767 #define rx_x4_rs_fec_status1_burst_error_mode_BURST_ERROR_38_BITS 23 7768 #define rx_x4_rs_fec_status1_burst_error_mode_BURST_ERROR_39_BITS 24 7769 #define rx_x4_rs_fec_status1_burst_error_mode_BURST_ERROR_40_BITS 25 7770 #define rx_x4_rs_fec_status1_burst_error_mode_BURST_ERROR_41_BITS 26 7771 7772 /**************************************************************************** 7773 * Enums: rx_x4_rs_fec_status1_bermon_state 7774 */ 7775 #define rx_x4_rs_fec_status1_bermon_state_HI_BER 4 7776 #define rx_x4_rs_fec_status1_bermon_state_GOOD_BER 3 7777 #define rx_x4_rs_fec_status1_bermon_state_BER_TEST_SH 2 7778 #define rx_x4_rs_fec_status1_bermon_state_START_TIMER 1 7779 #define rx_x4_rs_fec_status1_bermon_state_BER_MT_INIT 0 7780 7781 /**************************************************************************** 7782 * Enums: rx_x4_rs_fec_status1_rxsm_state_cl49 7783 */ 7784 #define rx_x4_rs_fec_status1_rxsm_state_cl49_RX_LI 32 7785 #define rx_x4_rs_fec_status1_rxsm_state_cl49_RX_E 16 7786 #define rx_x4_rs_fec_status1_rxsm_state_cl49_RX_T 8 7787 #define rx_x4_rs_fec_status1_rxsm_state_cl49_RX_D 4 7788 #define rx_x4_rs_fec_status1_rxsm_state_cl49_RX_C 2 7789 #define rx_x4_rs_fec_status1_rxsm_state_cl49_RX_INIT 1 7790 7791 /**************************************************************************** 7792 * Enums: rx_x4_rs_fec_status1_r_type 7793 */ 7794 #define rx_x4_rs_fec_status1_r_type_BAD_R_TYPE 15 7795 #define rx_x4_rs_fec_status1_r_type_R_TYPE_B0 11 7796 #define rx_x4_rs_fec_status1_r_type_R_TYPE_OB 10 7797 #define rx_x4_rs_fec_status1_r_type_R_TYPE_B1 9 7798 #define rx_x4_rs_fec_status1_r_type_R_TYPE_DB 8 7799 #define rx_x4_rs_fec_status1_r_type_R_TYPE_FC 7 7800 #define rx_x4_rs_fec_status1_r_type_R_TYPE_TB 6 7801 #define rx_x4_rs_fec_status1_r_type_R_TYPE_LI 5 7802 #define rx_x4_rs_fec_status1_r_type_R_TYPE_C 4 7803 #define rx_x4_rs_fec_status1_r_type_R_TYPE_S 3 7804 #define rx_x4_rs_fec_status1_r_type_R_TYPE_T 2 7805 #define rx_x4_rs_fec_status1_r_type_R_TYPE_D 1 7806 #define rx_x4_rs_fec_status1_r_type_R_TYPE_E 0 7807 7808 /**************************************************************************** 7809 * Enums: rx_x4_rs_fec_status1_am_lock_state 7810 */ 7811 #define rx_x4_rs_fec_status1_am_lock_state_INVALID_AM 512 7812 #define rx_x4_rs_fec_status1_am_lock_state_GOOD_AM 256 7813 #define rx_x4_rs_fec_status1_am_lock_state_COMP_AM 128 7814 #define rx_x4_rs_fec_status1_am_lock_state_TIMER_2 64 7815 #define rx_x4_rs_fec_status1_am_lock_state_AM_2_GOOD 32 7816 #define rx_x4_rs_fec_status1_am_lock_state_COMP_2ND 16 7817 #define rx_x4_rs_fec_status1_am_lock_state_TIMER_1 8 7818 #define rx_x4_rs_fec_status1_am_lock_state_FIND_1ST 4 7819 #define rx_x4_rs_fec_status1_am_lock_state_AM_RESET_CNT 2 7820 #define rx_x4_rs_fec_status1_am_lock_state_AM_LOCK_INIT 1 7821 7822 /**************************************************************************** 7823 * Enums: rx_x4_rs_fec_status1_msg_selector 7824 */ 7825 #define rx_x4_rs_fec_status1_msg_selector_RESERVED 0 7826 #define rx_x4_rs_fec_status1_msg_selector_VALUE_802p3 1 7827 #define rx_x4_rs_fec_status1_msg_selector_VALUE_802p9 2 7828 #define rx_x4_rs_fec_status1_msg_selector_VALUE_802p5 3 7829 #define rx_x4_rs_fec_status1_msg_selector_VALUE_1394 4 7830 7831 /**************************************************************************** 7832 * Enums: rx_x4_rs_fec_status1_synce_enum_stage1 7833 */ 7834 #define rx_x4_rs_fec_status1_synce_enum_stage1_SYNCE_NO_DIV 0 7835 #define rx_x4_rs_fec_status1_synce_enum_stage1_SYNCE_DIV_7 1 7836 #define rx_x4_rs_fec_status1_synce_enum_stage1_SYNCE_DIV_11 2 7837 7838 /**************************************************************************** 7839 * Enums: rx_x4_rs_fec_status1_synce_enum_stage0 7840 */ 7841 #define rx_x4_rs_fec_status1_synce_enum_stage0_SYNCE_NO_DIV 0 7842 #define rx_x4_rs_fec_status1_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 7843 #define rx_x4_rs_fec_status1_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 7844 7845 /**************************************************************************** 7846 * Enums: rx_x4_rs_fec_status1_cl91_sync_state 7847 */ 7848 #define rx_x4_rs_fec_status1_cl91_sync_state_FIND_1ST 0 7849 #define rx_x4_rs_fec_status1_cl91_sync_state_COUNT_NEXT 1 7850 #define rx_x4_rs_fec_status1_cl91_sync_state_COMP_2ND 2 7851 #define rx_x4_rs_fec_status1_cl91_sync_state_TWO_GOOD 3 7852 7853 /**************************************************************************** 7854 * Enums: rx_x4_rs_fec_status1_RS_FEC_sync_state 7855 */ 7856 #define rx_x4_rs_fec_status1_RS_FEC_sync_state_LOCK_INIT 0 7857 #define rx_x4_rs_fec_status1_RS_FEC_sync_state_FIND_1ST 1 7858 #define rx_x4_rs_fec_status1_RS_FEC_sync_state_COUNT_NEXT 2 7859 #define rx_x4_rs_fec_status1_RS_FEC_sync_state_COMP_2ND 3 7860 #define rx_x4_rs_fec_status1_RS_FEC_sync_state_TWO_GOOD 4 7861 7862 /**************************************************************************** 7863 * Enums: rx_x4_rs_fec_status1_cl91_algn_state 7864 */ 7865 #define rx_x4_rs_fec_status1_cl91_algn_state_LOSS_OF_ALIGNMENT 0 7866 #define rx_x4_rs_fec_status1_cl91_algn_state_DESKEW 1 7867 #define rx_x4_rs_fec_status1_cl91_algn_state_DESKEW_FAIL 2 7868 #define rx_x4_rs_fec_status1_cl91_algn_state_ALIGN_ACQUIRED 3 7869 #define rx_x4_rs_fec_status1_cl91_algn_state_CW_GOOD 4 7870 #define rx_x4_rs_fec_status1_cl91_algn_state_CW_BAD 5 7871 #define rx_x4_rs_fec_status1_cl91_algn_state_THREE_BAD 6 7872 7873 /**************************************************************************** 7874 * Enums: rx_x4_rs_fec_status1_RS_FEC_algn_state 7875 */ 7876 #define rx_x4_rs_fec_status1_RS_FEC_algn_state_LOSS_OF_ALIGNMENT 0 7877 #define rx_x4_rs_fec_status1_RS_FEC_algn_state_DESKEW 1 7878 #define rx_x4_rs_fec_status1_RS_FEC_algn_state_DESKEW_FAIL 2 7879 #define rx_x4_rs_fec_status1_RS_FEC_algn_state_ALIGN_ACQUIRED 3 7880 #define rx_x4_rs_fec_status1_RS_FEC_algn_state_CW_GOOD 4 7881 #define rx_x4_rs_fec_status1_RS_FEC_algn_state_CW_BAD 5 7882 #define rx_x4_rs_fec_status1_RS_FEC_algn_state_THREE_BAD 6 7883 7884 /**************************************************************************** 7885 * Enums: rx_x4_rs_fec_status1_fec_sel_override 7886 */ 7887 #define rx_x4_rs_fec_status1_fec_sel_override_NO_OVERRIDE 0 7888 #define rx_x4_rs_fec_status1_fec_sel_override_NO_FEC 1 7889 #define rx_x4_rs_fec_status1_fec_sel_override_FEC_CL74 2 7890 #define rx_x4_rs_fec_status1_fec_sel_override_FEC_CL91 3 7891 7892 /**************************************************************************** 7893 * Enums: rx_x4_rs_fec_status1_cl91_blksync_mode 7894 */ 7895 #define rx_x4_rs_fec_status1_cl91_blksync_mode_R_BLKSYNC_NO_CL91_FEC 0 7896 #define rx_x4_rs_fec_status1_cl91_blksync_mode_R_BLKSYNC_CL91_QUAD_LANE_FEC 1 7897 #define rx_x4_rs_fec_status1_cl91_blksync_mode_R_BLKSYNC_CL91_DUAL_LANE_FEC 2 7898 #define rx_x4_rs_fec_status1_cl91_blksync_mode_R_BLKSYNC_CL91_SINGLE_LANE_FEC 3 7899 #define rx_x4_rs_fec_status1_cl91_blksync_mode_R_BLKSYNC_CL91_FC_FEC 4 7900 7901 /**************************************************************************** 7902 * Enums: rx_x4_rs_fec_status1_r_merge_mode 7903 */ 7904 #define rx_x4_rs_fec_status1_r_merge_mode_R_MERGE_MODE_BYPASS 0 7905 #define rx_x4_rs_fec_status1_r_merge_mode_R_MERGE_MODE_CL91_FC 1 7906 #define rx_x4_rs_fec_status1_r_merge_mode_R_MERGE_MODE_CL91_SINGLE_LANE 2 7907 #define rx_x4_rs_fec_status1_r_merge_mode_R_MERGE_MODE_CL91_DUAL_LANE 3 7908 #define rx_x4_rs_fec_status1_r_merge_mode_R_MERGE_MODE_CL91_QUAD_LANE 4 7909 7910 /**************************************************************************** 7911 * Enums: rx_x4_rs_fec_status1_r_tc_mode 7912 */ 7913 #define rx_x4_rs_fec_status1_r_tc_mode_R_TC_MODE_SINGLE 0 7914 #define rx_x4_rs_fec_status1_r_tc_mode_R_TC_MODE_DUAL 1 7915 #define rx_x4_rs_fec_status1_r_tc_mode_R_TC_MODE_QUAD 2 7916 7917 /**************************************************************************** 7918 * Enums: rx_x4_rs_fec_status1_r_tc_out_mode 7919 */ 7920 #define rx_x4_rs_fec_status1_r_tc_out_mode_R_TC_OUT_MODE_SINGLE 0 7921 #define rx_x4_rs_fec_status1_r_tc_out_mode_R_TC_OUT_MODE_DUAL 1 7922 #define rx_x4_rs_fec_status1_r_tc_out_mode_R_TC_OUT_MODE_QUAD 2 7923 7924 /**************************************************************************** 7925 * Enums: rx_x4_rs_fec_status1_cl91_fec_mode 7926 */ 7927 #define rx_x4_rs_fec_status1_cl91_fec_mode_NO_CL91_FEC 0 7928 #define rx_x4_rs_fec_status1_cl91_fec_mode_CL91_SINGLE_LANE_FC 1 7929 #define rx_x4_rs_fec_status1_cl91_fec_mode_CL91_SINGLE_LANE_BRCM_PROP 2 7930 #define rx_x4_rs_fec_status1_cl91_fec_mode_CL91_DUAL_LANE_BRCM_PROP 3 7931 #define rx_x4_rs_fec_status1_cl91_fec_mode_CL91_QUAD_LANE 4 7932 #define rx_x4_rs_fec_status1_cl91_fec_mode_IEEE_25G_CL91_SINGLE_LANE 5 7933 7934 /**************************************************************************** 7935 * Enums: rx_x4_rs_fec_status1_RS_FEC_fec_mode 7936 */ 7937 #define rx_x4_rs_fec_status1_RS_FEC_fec_mode_NO_RS_FEC_FEC 0 7938 #define rx_x4_rs_fec_status1_RS_FEC_fec_mode_N_A 1 7939 #define rx_x4_rs_fec_status1_RS_FEC_fec_mode_RS_FEC_SINGLE_LANE_BRCM_PROP 2 7940 #define rx_x4_rs_fec_status1_RS_FEC_fec_mode_RS_FEC_DUAL_LANE_BRCM_PROP 3 7941 #define rx_x4_rs_fec_status1_RS_FEC_fec_mode_RS_FEC_QUAD_LANE 4 7942 #define rx_x4_rs_fec_status1_RS_FEC_fec_mode_IEEE_25G_RS_FEC_SINGLE_LANE 5 7943 7944 /**************************************************************************** 7945 * Enums: rx_x4_rs_fec_status1_am_spacing_mul 7946 */ 7947 #define rx_x4_rs_fec_status1_am_spacing_mul_AM_SPACING_MUL_2 0 7948 #define rx_x4_rs_fec_status1_am_spacing_mul_AM_SPACING_MUL_4 1 7949 #define rx_x4_rs_fec_status1_am_spacing_mul_AM_SPACING_MUL_5 2 7950 #define rx_x4_rs_fec_status1_am_spacing_mul_AM_SPACING_MUL_20 3 7951 7952 /**************************************************************************** 7953 * Enums: rx_x4_status1_cl36TxEEEStates_l 7954 */ 7955 #define rx_x4_status1_cl36TxEEEStates_l_TX_REFRESH 8 7956 #define rx_x4_status1_cl36TxEEEStates_l_TX_QUIET 4 7957 #define rx_x4_status1_cl36TxEEEStates_l_TX_SLEEP 2 7958 #define rx_x4_status1_cl36TxEEEStates_l_TX_ACTIVE 1 7959 7960 /**************************************************************************** 7961 * Enums: rx_x4_status1_cl36TxEEEStates_c 7962 */ 7963 #define rx_x4_status1_cl36TxEEEStates_c_TX_REFRESH 3 7964 #define rx_x4_status1_cl36TxEEEStates_c_TX_QUIET 2 7965 #define rx_x4_status1_cl36TxEEEStates_c_TX_SLEEP 1 7966 #define rx_x4_status1_cl36TxEEEStates_c_TX_ACTIVE 0 7967 7968 /**************************************************************************** 7969 * Enums: rx_x4_status1_cl49TxEEEStates_l 7970 */ 7971 #define rx_x4_status1_cl49TxEEEStates_l_SCR_RESET_2 64 7972 #define rx_x4_status1_cl49TxEEEStates_l_SCR_RESET_1 32 7973 #define rx_x4_status1_cl49TxEEEStates_l_TX_WAKE 16 7974 #define rx_x4_status1_cl49TxEEEStates_l_TX_REFRESH 8 7975 #define rx_x4_status1_cl49TxEEEStates_l_TX_QUIET 4 7976 #define rx_x4_status1_cl49TxEEEStates_l_TX_SLEEP 2 7977 #define rx_x4_status1_cl49TxEEEStates_l_TX_ACTIVE 1 7978 7979 /**************************************************************************** 7980 * Enums: rx_x4_status1_fec_req_enum 7981 */ 7982 #define rx_x4_status1_fec_req_enum_FEC_not_supported 0 7983 #define rx_x4_status1_fec_req_enum_FEC_supported_but_not_requested 1 7984 #define rx_x4_status1_fec_req_enum_invalid_setting 2 7985 #define rx_x4_status1_fec_req_enum_FEC_supported_and_requested 3 7986 7987 /**************************************************************************** 7988 * Enums: rx_x4_status1_cl73_pause_enum 7989 */ 7990 #define rx_x4_status1_cl73_pause_enum_No_PAUSE_ability 0 7991 #define rx_x4_status1_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 7992 #define rx_x4_status1_cl73_pause_enum_Symmetric_PAUSE_ability 1 7993 #define rx_x4_status1_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 7994 7995 /**************************************************************************** 7996 * Enums: rx_x4_status1_cl49TxEEEStates_c 7997 */ 7998 #define rx_x4_status1_cl49TxEEEStates_c_SCR_RESET_2 6 7999 #define rx_x4_status1_cl49TxEEEStates_c_SCR_RESET_1 5 8000 #define rx_x4_status1_cl49TxEEEStates_c_TX_WAKE 4 8001 #define rx_x4_status1_cl49TxEEEStates_c_TX_REFRESH 3 8002 #define rx_x4_status1_cl49TxEEEStates_c_TX_QUIET 2 8003 #define rx_x4_status1_cl49TxEEEStates_c_TX_SLEEP 1 8004 #define rx_x4_status1_cl49TxEEEStates_c_TX_ACTIVE 0 8005 8006 /**************************************************************************** 8007 * Enums: rx_x4_status1_cl36RxEEEStates_l 8008 */ 8009 #define rx_x4_status1_cl36RxEEEStates_l_RX_LINK_FAIL 32 8010 #define rx_x4_status1_cl36RxEEEStates_l_RX_WTF 16 8011 #define rx_x4_status1_cl36RxEEEStates_l_RX_WAKE 8 8012 #define rx_x4_status1_cl36RxEEEStates_l_RX_QUIET 4 8013 #define rx_x4_status1_cl36RxEEEStates_l_RX_SLEEP 2 8014 #define rx_x4_status1_cl36RxEEEStates_l_RX_ACTIVE 1 8015 8016 /**************************************************************************** 8017 * Enums: rx_x4_status1_cl36RxEEEStates_c 8018 */ 8019 #define rx_x4_status1_cl36RxEEEStates_c_RX_LINK_FAIL 5 8020 #define rx_x4_status1_cl36RxEEEStates_c_RX_WTF 4 8021 #define rx_x4_status1_cl36RxEEEStates_c_RX_WAKE 3 8022 #define rx_x4_status1_cl36RxEEEStates_c_RX_QUIET 2 8023 #define rx_x4_status1_cl36RxEEEStates_c_RX_SLEEP 1 8024 #define rx_x4_status1_cl36RxEEEStates_c_RX_ACTIVE 0 8025 8026 /**************************************************************************** 8027 * Enums: rx_x4_status1_cl49RxEEEStates_l 8028 */ 8029 #define rx_x4_status1_cl49RxEEEStates_l_RX_LINK_FAIL 32 8030 #define rx_x4_status1_cl49RxEEEStates_l_RX_WTF 16 8031 #define rx_x4_status1_cl49RxEEEStates_l_RX_WAKE 8 8032 #define rx_x4_status1_cl49RxEEEStates_l_RX_QUIET 4 8033 #define rx_x4_status1_cl49RxEEEStates_l_RX_SLEEP 2 8034 #define rx_x4_status1_cl49RxEEEStates_l_RX_ACTIVE 1 8035 8036 /**************************************************************************** 8037 * Enums: rx_x4_status1_cl49RxEEEStates_c 8038 */ 8039 #define rx_x4_status1_cl49RxEEEStates_c_RX_LINK_FAIL 5 8040 #define rx_x4_status1_cl49RxEEEStates_c_RX_WTF 4 8041 #define rx_x4_status1_cl49RxEEEStates_c_RX_WAKE 3 8042 #define rx_x4_status1_cl49RxEEEStates_c_RX_QUIET 2 8043 #define rx_x4_status1_cl49RxEEEStates_c_RX_SLEEP 1 8044 #define rx_x4_status1_cl49RxEEEStates_c_RX_ACTIVE 0 8045 8046 /**************************************************************************** 8047 * Enums: rx_x4_status1_cl48TxEEEStates_l 8048 */ 8049 #define rx_x4_status1_cl48TxEEEStates_l_TX_REFRESH 8 8050 #define rx_x4_status1_cl48TxEEEStates_l_TX_QUIET 4 8051 #define rx_x4_status1_cl48TxEEEStates_l_TX_SLEEP 2 8052 #define rx_x4_status1_cl48TxEEEStates_l_TX_ACTIVE 1 8053 8054 /**************************************************************************** 8055 * Enums: rx_x4_status1_cl48TxEEEStates_c 8056 */ 8057 #define rx_x4_status1_cl48TxEEEStates_c_TX_REFRESH 3 8058 #define rx_x4_status1_cl48TxEEEStates_c_TX_QUIET 2 8059 #define rx_x4_status1_cl48TxEEEStates_c_TX_SLEEP 1 8060 #define rx_x4_status1_cl48TxEEEStates_c_TX_ACTIVE 0 8061 8062 /**************************************************************************** 8063 * Enums: rx_x4_status1_cl48RxEEEStates_l 8064 */ 8065 #define rx_x4_status1_cl48RxEEEStates_l_RX_LINK_FAIL 32 8066 #define rx_x4_status1_cl48RxEEEStates_l_RX_WAKE 16 8067 #define rx_x4_status1_cl48RxEEEStates_l_RX_QUIET 8 8068 #define rx_x4_status1_cl48RxEEEStates_l_RX_DEACT 4 8069 #define rx_x4_status1_cl48RxEEEStates_l_RX_SLEEP 2 8070 #define rx_x4_status1_cl48RxEEEStates_l_RX_ACTIVE 1 8071 8072 /**************************************************************************** 8073 * Enums: rx_x4_status1_cl48RxEEEStates_c 8074 */ 8075 #define rx_x4_status1_cl48RxEEEStates_c_RX_LINK_FAIL 5 8076 #define rx_x4_status1_cl48RxEEEStates_c_RX_WAKE 4 8077 #define rx_x4_status1_cl48RxEEEStates_c_RX_QUIET 3 8078 #define rx_x4_status1_cl48RxEEEStates_c_RX_DEACT 2 8079 #define rx_x4_status1_cl48RxEEEStates_c_RX_SLEEP 1 8080 #define rx_x4_status1_cl48RxEEEStates_c_RX_ACTIVE 0 8081 8082 /**************************************************************************** 8083 * Enums: rx_x4_status1_IQP_Options 8084 */ 8085 #define rx_x4_status1_IQP_Options_i50uA 0 8086 #define rx_x4_status1_IQP_Options_i100uA 1 8087 #define rx_x4_status1_IQP_Options_i150uA 2 8088 #define rx_x4_status1_IQP_Options_i200uA 3 8089 #define rx_x4_status1_IQP_Options_i250uA 4 8090 #define rx_x4_status1_IQP_Options_i300uA 5 8091 #define rx_x4_status1_IQP_Options_i350uA 6 8092 #define rx_x4_status1_IQP_Options_i400uA 7 8093 #define rx_x4_status1_IQP_Options_i450uA 8 8094 #define rx_x4_status1_IQP_Options_i500uA 9 8095 #define rx_x4_status1_IQP_Options_i550uA 10 8096 #define rx_x4_status1_IQP_Options_i600uA 11 8097 #define rx_x4_status1_IQP_Options_i650uA 12 8098 #define rx_x4_status1_IQP_Options_i700uA 13 8099 #define rx_x4_status1_IQP_Options_i750uA 14 8100 #define rx_x4_status1_IQP_Options_i800uA 15 8101 8102 /**************************************************************************** 8103 * Enums: rx_x4_status1_IDriver_Options 8104 */ 8105 #define rx_x4_status1_IDriver_Options_v680mV 0 8106 #define rx_x4_status1_IDriver_Options_v730mV 1 8107 #define rx_x4_status1_IDriver_Options_v780mV 2 8108 #define rx_x4_status1_IDriver_Options_v830mV 3 8109 #define rx_x4_status1_IDriver_Options_v880mV 4 8110 #define rx_x4_status1_IDriver_Options_v930mV 5 8111 #define rx_x4_status1_IDriver_Options_v980mV 6 8112 #define rx_x4_status1_IDriver_Options_v1010mV 7 8113 #define rx_x4_status1_IDriver_Options_v1040mV 8 8114 #define rx_x4_status1_IDriver_Options_v1060mV 9 8115 #define rx_x4_status1_IDriver_Options_v1070mV 10 8116 #define rx_x4_status1_IDriver_Options_v1080mV 11 8117 #define rx_x4_status1_IDriver_Options_v1085mV 12 8118 #define rx_x4_status1_IDriver_Options_v1090mV 13 8119 #define rx_x4_status1_IDriver_Options_v1095mV 14 8120 #define rx_x4_status1_IDriver_Options_v1100mV 15 8121 8122 /**************************************************************************** 8123 * Enums: rx_x4_status1_operationModes 8124 */ 8125 #define rx_x4_status1_operationModes_XGXS 0 8126 #define rx_x4_status1_operationModes_XGXG_nCC 1 8127 #define rx_x4_status1_operationModes_Indlane_OS8 4 8128 #define rx_x4_status1_operationModes_IndLane_OS5 5 8129 #define rx_x4_status1_operationModes_PCI 7 8130 #define rx_x4_status1_operationModes_XGXS_nLQ 8 8131 #define rx_x4_status1_operationModes_XGXS_nLQnCC 9 8132 #define rx_x4_status1_operationModes_PBypass 10 8133 #define rx_x4_status1_operationModes_PBypass_nDSK 11 8134 #define rx_x4_status1_operationModes_ComboCoreMode 12 8135 #define rx_x4_status1_operationModes_Clocks_off 15 8136 8137 /**************************************************************************** 8138 * Enums: rx_x4_status1_actualSpeeds 8139 */ 8140 #define rx_x4_status1_actualSpeeds_dr_10M 0 8141 #define rx_x4_status1_actualSpeeds_dr_100M 1 8142 #define rx_x4_status1_actualSpeeds_dr_1G 2 8143 #define rx_x4_status1_actualSpeeds_dr_2p5G 3 8144 #define rx_x4_status1_actualSpeeds_dr_5G_X4 4 8145 #define rx_x4_status1_actualSpeeds_dr_6G_X4 5 8146 #define rx_x4_status1_actualSpeeds_dr_10G_HiG 6 8147 #define rx_x4_status1_actualSpeeds_dr_10G_CX4 7 8148 #define rx_x4_status1_actualSpeeds_dr_12G_HiG 8 8149 #define rx_x4_status1_actualSpeeds_dr_12p5G_X4 9 8150 #define rx_x4_status1_actualSpeeds_dr_13G_X4 10 8151 #define rx_x4_status1_actualSpeeds_dr_15G_X4 11 8152 #define rx_x4_status1_actualSpeeds_dr_16G_X4 12 8153 #define rx_x4_status1_actualSpeeds_dr_1G_KX 13 8154 #define rx_x4_status1_actualSpeeds_dr_10G_KX4 14 8155 #define rx_x4_status1_actualSpeeds_dr_10G_KR 15 8156 #define rx_x4_status1_actualSpeeds_dr_5G 16 8157 #define rx_x4_status1_actualSpeeds_dr_6p4G 17 8158 #define rx_x4_status1_actualSpeeds_dr_20G_X4 18 8159 #define rx_x4_status1_actualSpeeds_dr_21G_X4 19 8160 #define rx_x4_status1_actualSpeeds_dr_25G_X4 20 8161 #define rx_x4_status1_actualSpeeds_dr_10G_HiG_DXGXS 21 8162 #define rx_x4_status1_actualSpeeds_dr_10G_DXGXS 22 8163 #define rx_x4_status1_actualSpeeds_dr_10p5G_HiG_DXGXS 23 8164 #define rx_x4_status1_actualSpeeds_dr_10p5G_DXGXS 24 8165 #define rx_x4_status1_actualSpeeds_dr_12p773G_HiG_DXGXS 25 8166 #define rx_x4_status1_actualSpeeds_dr_12p773G_DXGXS 26 8167 #define rx_x4_status1_actualSpeeds_dr_10G_XFI 27 8168 #define rx_x4_status1_actualSpeeds_dr_40G 28 8169 #define rx_x4_status1_actualSpeeds_dr_20G_HiG_DXGXS 29 8170 #define rx_x4_status1_actualSpeeds_dr_20G_DXGXS 30 8171 #define rx_x4_status1_actualSpeeds_dr_10G_SFI 31 8172 #define rx_x4_status1_actualSpeeds_dr_31p5G 32 8173 #define rx_x4_status1_actualSpeeds_dr_32p7G 33 8174 #define rx_x4_status1_actualSpeeds_dr_20G_SCR 34 8175 #define rx_x4_status1_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 8176 #define rx_x4_status1_actualSpeeds_dr_10G_DXGXS_SCR 36 8177 #define rx_x4_status1_actualSpeeds_dr_12G_R2 37 8178 #define rx_x4_status1_actualSpeeds_dr_10G_X2 38 8179 #define rx_x4_status1_actualSpeeds_dr_40G_KR4 39 8180 #define rx_x4_status1_actualSpeeds_dr_40G_CR4 40 8181 #define rx_x4_status1_actualSpeeds_dr_100G_CR10 41 8182 #define rx_x4_status1_actualSpeeds_dr_15p75G_DXGXS 44 8183 #define rx_x4_status1_actualSpeeds_dr_20G_KR2 57 8184 #define rx_x4_status1_actualSpeeds_dr_20G_CR2 58 8185 8186 /**************************************************************************** 8187 * Enums: rx_x4_status1_actualSpeedsMisc1 8188 */ 8189 #define rx_x4_status1_actualSpeedsMisc1_dr_2500BRCM_X1 16 8190 #define rx_x4_status1_actualSpeedsMisc1_dr_5000BRCM_X4 17 8191 #define rx_x4_status1_actualSpeedsMisc1_dr_6000BRCM_X4 18 8192 #define rx_x4_status1_actualSpeedsMisc1_dr_10GHiGig_X4 19 8193 #define rx_x4_status1_actualSpeedsMisc1_dr_10GBASE_CX4 20 8194 #define rx_x4_status1_actualSpeedsMisc1_dr_12GHiGig_X4 21 8195 #define rx_x4_status1_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 8196 #define rx_x4_status1_actualSpeedsMisc1_dr_13GHiGig_X4 23 8197 #define rx_x4_status1_actualSpeedsMisc1_dr_15GHiGig_X4 24 8198 #define rx_x4_status1_actualSpeedsMisc1_dr_16GHiGig_X4 25 8199 #define rx_x4_status1_actualSpeedsMisc1_dr_5000BRCM_X1 26 8200 #define rx_x4_status1_actualSpeedsMisc1_dr_6363BRCM_X1 27 8201 #define rx_x4_status1_actualSpeedsMisc1_dr_20GHiGig_X4 28 8202 #define rx_x4_status1_actualSpeedsMisc1_dr_21GHiGig_X4 29 8203 #define rx_x4_status1_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 8204 #define rx_x4_status1_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 8205 8206 /**************************************************************************** 8207 * Enums: rx_x4_status1_IndLaneModes 8208 */ 8209 #define rx_x4_status1_IndLaneModes_SWSDR_div2 0 8210 #define rx_x4_status1_IndLaneModes_SWSDR_div1 1 8211 #define rx_x4_status1_IndLaneModes_DWSDR_div2 2 8212 #define rx_x4_status1_IndLaneModes_DWSDR_div1 3 8213 8214 /**************************************************************************** 8215 * Enums: rx_x4_status1_prbsSelect 8216 */ 8217 #define rx_x4_status1_prbsSelect_prbs7 0 8218 #define rx_x4_status1_prbsSelect_prbs15 1 8219 #define rx_x4_status1_prbsSelect_prbs23 2 8220 #define rx_x4_status1_prbsSelect_prbs31 3 8221 8222 /**************************************************************************** 8223 * Enums: rx_x4_status1_vcoDivider 8224 */ 8225 #define rx_x4_status1_vcoDivider_div32 0 8226 #define rx_x4_status1_vcoDivider_div36 1 8227 #define rx_x4_status1_vcoDivider_div40 2 8228 #define rx_x4_status1_vcoDivider_div42 3 8229 #define rx_x4_status1_vcoDivider_div48 4 8230 #define rx_x4_status1_vcoDivider_div50 5 8231 #define rx_x4_status1_vcoDivider_div52 6 8232 #define rx_x4_status1_vcoDivider_div54 7 8233 #define rx_x4_status1_vcoDivider_div60 8 8234 #define rx_x4_status1_vcoDivider_div64 9 8235 #define rx_x4_status1_vcoDivider_div66 10 8236 #define rx_x4_status1_vcoDivider_div68 11 8237 #define rx_x4_status1_vcoDivider_div70 12 8238 #define rx_x4_status1_vcoDivider_div80 13 8239 #define rx_x4_status1_vcoDivider_div92 14 8240 #define rx_x4_status1_vcoDivider_div100 15 8241 8242 /**************************************************************************** 8243 * Enums: rx_x4_status1_refClkSelect 8244 */ 8245 #define rx_x4_status1_refClkSelect_clk_156p25MHz 1 8246 #define rx_x4_status1_refClkSelect_clk_312p5Mhz 2 8247 8248 /**************************************************************************** 8249 * Enums: rx_x4_status1_aerMMDdevTypeSelect 8250 */ 8251 #define rx_x4_status1_aerMMDdevTypeSelect_combo_core 0 8252 #define rx_x4_status1_aerMMDdevTypeSelect_PMA_PMD 1 8253 #define rx_x4_status1_aerMMDdevTypeSelect_PCS 3 8254 #define rx_x4_status1_aerMMDdevTypeSelect_PHY 4 8255 #define rx_x4_status1_aerMMDdevTypeSelect_DTE 5 8256 #define rx_x4_status1_aerMMDdevTypeSelect_CL73_AN 7 8257 8258 /**************************************************************************** 8259 * Enums: rx_x4_status1_aerMMDportSelect 8260 */ 8261 #define rx_x4_status1_aerMMDportSelect_ln0 0 8262 #define rx_x4_status1_aerMMDportSelect_ln1 1 8263 #define rx_x4_status1_aerMMDportSelect_ln2 2 8264 #define rx_x4_status1_aerMMDportSelect_ln3 3 8265 #define rx_x4_status1_aerMMDportSelect_BCST_ln0_1_2_3 511 8266 #define rx_x4_status1_aerMMDportSelect_BCST_ln0_1 512 8267 #define rx_x4_status1_aerMMDportSelect_BCST_ln2_3 513 8268 8269 /**************************************************************************** 8270 * Enums: rx_x4_status1_firmwareModeSelect 8271 */ 8272 #define rx_x4_status1_firmwareModeSelect_DEFAULT 0 8273 #define rx_x4_status1_firmwareModeSelect_SFP_OPT_LR 1 8274 #define rx_x4_status1_firmwareModeSelect_SFP_DAC 2 8275 #define rx_x4_status1_firmwareModeSelect_XLAUI 3 8276 #define rx_x4_status1_firmwareModeSelect_LONG_CH_6G 4 8277 8278 /**************************************************************************** 8279 * Enums: rx_x4_status1_tempIdxSelect 8280 */ 8281 #define rx_x4_status1_tempIdxSelect_LTE__22p9C 15 8282 #define rx_x4_status1_tempIdxSelect_LTE__12p6C 14 8283 #define rx_x4_status1_tempIdxSelect_LTE__3p0C 13 8284 #define rx_x4_status1_tempIdxSelect_LTE_6p7C 12 8285 #define rx_x4_status1_tempIdxSelect_LTE_16p4C 11 8286 #define rx_x4_status1_tempIdxSelect_LTE_26p6C 10 8287 #define rx_x4_status1_tempIdxSelect_LTE_36p3C 9 8288 #define rx_x4_status1_tempIdxSelect_LTE_46p0C 8 8289 #define rx_x4_status1_tempIdxSelect_LTE_56p2C 7 8290 #define rx_x4_status1_tempIdxSelect_LTE_65p9C 6 8291 #define rx_x4_status1_tempIdxSelect_LTE_75p6C 5 8292 #define rx_x4_status1_tempIdxSelect_LTE_85p3C 4 8293 #define rx_x4_status1_tempIdxSelect_LTE_95p5C 3 8294 #define rx_x4_status1_tempIdxSelect_LTE_105p2C 2 8295 #define rx_x4_status1_tempIdxSelect_LTE_114p9C 1 8296 #define rx_x4_status1_tempIdxSelect_LTE_125p1C 0 8297 8298 /**************************************************************************** 8299 * Enums: rx_x4_status1_port_mode 8300 */ 8301 #define rx_x4_status1_port_mode_QUAD_PORT 0 8302 #define rx_x4_status1_port_mode_TRI_1_PORT 1 8303 #define rx_x4_status1_port_mode_TRI_2_PORT 2 8304 #define rx_x4_status1_port_mode_DUAL_PORT 3 8305 #define rx_x4_status1_port_mode_SINGLE_PORT 4 8306 #define rx_x4_status1_port_mode_SINGLE_OCTAL_PORT 5 8307 8308 /**************************************************************************** 8309 * Enums: rx_x4_status1_rev_letter_enum 8310 */ 8311 #define rx_x4_status1_rev_letter_enum_REV_A 0 8312 #define rx_x4_status1_rev_letter_enum_REV_B 1 8313 #define rx_x4_status1_rev_letter_enum_REV_C 2 8314 #define rx_x4_status1_rev_letter_enum_REV_D 3 8315 8316 /**************************************************************************** 8317 * Enums: rx_x4_status1_rev_number_enum 8318 */ 8319 #define rx_x4_status1_rev_number_enum_REV_0 0 8320 #define rx_x4_status1_rev_number_enum_REV_1 1 8321 #define rx_x4_status1_rev_number_enum_REV_2 2 8322 #define rx_x4_status1_rev_number_enum_REV_3 3 8323 #define rx_x4_status1_rev_number_enum_REV_4 4 8324 #define rx_x4_status1_rev_number_enum_REV_5 5 8325 #define rx_x4_status1_rev_number_enum_REV_6 6 8326 #define rx_x4_status1_rev_number_enum_REV_7 7 8327 8328 /**************************************************************************** 8329 * Enums: rx_x4_status1_bonding_enum 8330 */ 8331 #define rx_x4_status1_bonding_enum_WIRE_BOND 0 8332 #define rx_x4_status1_bonding_enum_FLIP_CHIP 1 8333 8334 /**************************************************************************** 8335 * Enums: rx_x4_status1_tech_process 8336 */ 8337 #define rx_x4_status1_tech_process_PROCESS_90NM 0 8338 #define rx_x4_status1_tech_process_PROCESS_65NM 1 8339 #define rx_x4_status1_tech_process_PROCESS_40NM 2 8340 #define rx_x4_status1_tech_process_PROCESS_28NM 3 8341 #define rx_x4_status1_tech_process_PROCESS_16NM 4 8342 8343 /**************************************************************************** 8344 * Enums: rx_x4_status1_model_num 8345 */ 8346 #define rx_x4_status1_model_num_SERDES_CL73 0 8347 #define rx_x4_status1_model_num_XGXS_16G 1 8348 #define rx_x4_status1_model_num_HYPERCORE 2 8349 #define rx_x4_status1_model_num_HYPERLITE 3 8350 #define rx_x4_status1_model_num_PCIE_G2_PIPE 4 8351 #define rx_x4_status1_model_num_SERDES_1p25GBd 5 8352 #define rx_x4_status1_model_num_SATA2 6 8353 #define rx_x4_status1_model_num_QSGMII 7 8354 #define rx_x4_status1_model_num_XGXS10G 8 8355 #define rx_x4_status1_model_num_WARPCORE 9 8356 #define rx_x4_status1_model_num_XFICORE 10 8357 #define rx_x4_status1_model_num_RXFI 11 8358 #define rx_x4_status1_model_num_WARPLITE 12 8359 #define rx_x4_status1_model_num_PENTACORE 13 8360 #define rx_x4_status1_model_num_ESM 14 8361 #define rx_x4_status1_model_num_QUAD_SGMII 15 8362 #define rx_x4_status1_model_num_WARPCORE_3 16 8363 #define rx_x4_status1_model_num_TSC 17 8364 #define rx_x4_status1_model_num_TSC4E 18 8365 #define rx_x4_status1_model_num_TSC12E 19 8366 #define rx_x4_status1_model_num_TSC4F 20 8367 #define rx_x4_status1_model_num_TSC4F_GEN2 21 8368 #define rx_x4_status1_model_num_XGXS_CL73_90NM 29 8369 #define rx_x4_status1_model_num_SERDES_CL73_90NM 30 8370 #define rx_x4_status1_model_num_WARPCORE3 32 8371 #define rx_x4_status1_model_num_WARPCORE4_TSC 33 8372 #define rx_x4_status1_model_num_RXAUI 34 8373 #define rx_x4_status1_model_num_TSCE_GEN3 35 8374 #define rx_x4_status1_model_num_TSC4F_GEN3 36 8375 #define rx_x4_status1_model_num_TSCBH 37 8376 8377 /**************************************************************************** 8378 * Enums: rx_x4_status1_payload 8379 */ 8380 #define rx_x4_status1_payload_REPEAT_2_BYTES 0 8381 #define rx_x4_status1_payload_RAMPING 1 8382 #define rx_x4_status1_payload_CL48_CRPAT 2 8383 #define rx_x4_status1_payload_CL48_CJPAT 3 8384 #define rx_x4_status1_payload_CL36_LONG_CRPAT 4 8385 #define rx_x4_status1_payload_CL36_SHORT_CRPAT 5 8386 8387 /**************************************************************************** 8388 * Enums: rx_x4_status1_sc 8389 */ 8390 #define rx_x4_status1_sc_SPEED_10G_IEEE_KR1 0 8391 #define rx_x4_status1_sc_SPEED_25G_IEEE_KS1_CS1 1 8392 #define rx_x4_status1_sc_SPEED_25G_IEEE_KR1_CR1 2 8393 #define rx_x4_status1_sc_SPEED_40G_IEEE_KR4 3 8394 #define rx_x4_status1_sc_SPEED_40G_IEEE_CR4 4 8395 #define rx_x4_status1_sc_SPEED_50G_IEEE_KR1_CR1 5 8396 #define rx_x4_status1_sc_SPEED_100G_IEEE_KR4 6 8397 #define rx_x4_status1_sc_SPEED_100G_IEEE_CR4 7 8398 #define rx_x4_status1_sc_SPEED_100G_IEEE_KR2_CR2 8 8399 #define rx_x4_status1_sc_SPEED_200G_IEEE_KR4_CR4 9 8400 #define rx_x4_status1_sc_SPEED_400G_IEEE_X8 10 8401 #define rx_x4_status1_sc_SPEED_CL73_IEEE_20GVCO 11 8402 #define rx_x4_status1_sc_SPEED_CL73_IEEE_25GVCO 12 8403 #define rx_x4_status1_sc_SPEED_CL73_IEEE_26GVCO 13 8404 #define rx_x4_status1_sc_SPEED_20G_BRCM_CR1 14 8405 #define rx_x4_status1_sc_SPEED_20G_BRCM_KR1 15 8406 #define rx_x4_status1_sc_SPEED_25G_BRCM_CR1 16 8407 #define rx_x4_status1_sc_SPEED_25G_BRCM_KR1 17 8408 #define rx_x4_status1_sc_SPEED_40G_BRCM_CR2 18 8409 #define rx_x4_status1_sc_SPEED_40G_BRCM_KR2 19 8410 #define rx_x4_status1_sc_SPEED_50G_BRCM_CR2 20 8411 #define rx_x4_status1_sc_SPEED_50G_BRCM_KR2 21 8412 #define rx_x4_status1_sc_SPEED_50G_BRCM_CR4 22 8413 #define rx_x4_status1_sc_SPEED_50G_BRCM_KR4 23 8414 #define rx_x4_status1_sc_SPEED_50G_BRCM_FEC_544_CR2_KR2 24 8415 #define rx_x4_status1_sc_SPEED_RESERVED_19 25 8416 #define rx_x4_status1_sc_SPEED_50G_BRCM_FEC_544_CR1_KR1 26 8417 #define rx_x4_status1_sc_SPEED_50G_BRCM_NO_FEC_CR1_KR1 27 8418 #define rx_x4_status1_sc_SPEED_50G_BRCM_FEC_528_CR1_KR1 28 8419 #define rx_x4_status1_sc_SPEED_400G_BRCM_NO_FEC_KR8_CR8 29 8420 #define rx_x4_status1_sc_SPEED_400G_BRCM_FEC_KR8_CR8 30 8421 #define rx_x4_status1_sc_SPEED_200G_BRCM_NO_FEC_KR4_CR4 31 8422 #define rx_x4_status1_sc_SPEED_200G_BRCM_KR4_CR4 32 8423 #define rx_x4_status1_sc_SPEED_100G_BRCM_KR4_CR4 33 8424 #define rx_x4_status1_sc_SPEED_RESERVED_22 34 8425 #define rx_x4_status1_sc_SPEED_100G_BRCM_FEC_528_KR2_CR2 35 8426 #define rx_x4_status1_sc_SPEED_100G_BRCM_NO_FEC_KR2_CR2 36 8427 #define rx_x4_status1_sc_SPEED_100G_BRCM_NO_FEC_X4 37 8428 8429 /**************************************************************************** 8430 * Enums: rx_x4_status1_t_fifo_modes 8431 */ 8432 #define rx_x4_status1_t_fifo_modes_T_FIFO_INSERT_NO_AM 0 8433 #define rx_x4_status1_t_fifo_modes_T_FIFO_INSERT_4_AM 1 8434 #define rx_x4_status1_t_fifo_modes_T_FIFO_INSERT_20_AM 2 8435 #define rx_x4_status1_t_fifo_modes_T_FIFO_INSERT_2_AM 3 8436 8437 /**************************************************************************** 8438 * Enums: rx_x4_status1_t_enc_modes 8439 */ 8440 #define rx_x4_status1_t_enc_modes_T_ENC_MODE_BYPASS 0 8441 #define rx_x4_status1_t_enc_modes_T_ENC_MODE_CL49 1 8442 #define rx_x4_status1_t_enc_modes_T_ENC_MODE_CL82 2 8443 8444 /**************************************************************************** 8445 * Enums: rx_x4_status1_btmx_mode 8446 */ 8447 #define rx_x4_status1_btmx_mode_BS_BTMX_MODE_1to1 0 8448 #define rx_x4_status1_btmx_mode_BS_BTMX_MODE_2to1 1 8449 #define rx_x4_status1_btmx_mode_BS_BTMX_MODE_5to1 2 8450 8451 /**************************************************************************** 8452 * Enums: rx_x4_status1_t_type_cl82 8453 */ 8454 #define rx_x4_status1_t_type_cl82_T_TYPE_B1 5 8455 #define rx_x4_status1_t_type_cl82_T_TYPE_C 4 8456 #define rx_x4_status1_t_type_cl82_T_TYPE_S 3 8457 #define rx_x4_status1_t_type_cl82_T_TYPE_T 2 8458 #define rx_x4_status1_t_type_cl82_T_TYPE_D 1 8459 #define rx_x4_status1_t_type_cl82_T_TYPE_E 0 8460 8461 /**************************************************************************** 8462 * Enums: rx_x4_status1_txsm_state_cl82 8463 */ 8464 #define rx_x4_status1_txsm_state_cl82_TX_E 4 8465 #define rx_x4_status1_txsm_state_cl82_TX_T 3 8466 #define rx_x4_status1_txsm_state_cl82_TX_D 2 8467 #define rx_x4_status1_txsm_state_cl82_TX_C 1 8468 #define rx_x4_status1_txsm_state_cl82_TX_INIT 0 8469 8470 /**************************************************************************** 8471 * Enums: rx_x4_status1_ltxsm_state_cl82 8472 */ 8473 #define rx_x4_status1_ltxsm_state_cl82_TX_E 16 8474 #define rx_x4_status1_ltxsm_state_cl82_TX_T 8 8475 #define rx_x4_status1_ltxsm_state_cl82_TX_D 4 8476 #define rx_x4_status1_ltxsm_state_cl82_TX_C 2 8477 #define rx_x4_status1_ltxsm_state_cl82_TX_INIT 1 8478 8479 /**************************************************************************** 8480 * Enums: rx_x4_status1_r_type_coded_cl82 8481 */ 8482 #define rx_x4_status1_r_type_coded_cl82_R_TYPE_B1 32 8483 #define rx_x4_status1_r_type_coded_cl82_R_TYPE_C 16 8484 #define rx_x4_status1_r_type_coded_cl82_R_TYPE_S 8 8485 #define rx_x4_status1_r_type_coded_cl82_R_TYPE_T 4 8486 #define rx_x4_status1_r_type_coded_cl82_R_TYPE_D 2 8487 #define rx_x4_status1_r_type_coded_cl82_R_TYPE_E 1 8488 8489 /**************************************************************************** 8490 * Enums: rx_x4_status1_rxsm_state_cl82 8491 */ 8492 #define rx_x4_status1_rxsm_state_cl82_RX_E 16 8493 #define rx_x4_status1_rxsm_state_cl82_RX_T 8 8494 #define rx_x4_status1_rxsm_state_cl82_RX_D 4 8495 #define rx_x4_status1_rxsm_state_cl82_RX_C 2 8496 #define rx_x4_status1_rxsm_state_cl82_RX_INIT 1 8497 8498 /**************************************************************************** 8499 * Enums: rx_x4_status1_deskew_state 8500 */ 8501 #define rx_x4_status1_deskew_state_ALIGN_ACQUIRED 2 8502 #define rx_x4_status1_deskew_state_LOSS_OF_ALIGNMENT 1 8503 8504 /**************************************************************************** 8505 * Enums: rx_x4_status1_os_mode_enum 8506 */ 8507 #define rx_x4_status1_os_mode_enum_OS_MODE_1 0 8508 #define rx_x4_status1_os_mode_enum_OS_MODE_2 1 8509 #define rx_x4_status1_os_mode_enum_OS_MODE_4 2 8510 #define rx_x4_status1_os_mode_enum_OS_MODE_16p5 8 8511 #define rx_x4_status1_os_mode_enum_OS_MODE_20p625 12 8512 8513 /**************************************************************************** 8514 * Enums: rx_x4_status1_scr_modes 8515 */ 8516 #define rx_x4_status1_scr_modes_T_SCR_MODE_BYPASS 0 8517 #define rx_x4_status1_scr_modes_T_SCR_MODE_CL49 1 8518 #define rx_x4_status1_scr_modes_T_SCR_MODE_40G_2_LANE 2 8519 #define rx_x4_status1_scr_modes_T_SCR_MODE_100G 3 8520 #define rx_x4_status1_scr_modes_T_SCR_MODE_20G 4 8521 #define rx_x4_status1_scr_modes_T_SCR_MODE_40G_4_LANE 5 8522 8523 /**************************************************************************** 8524 * Enums: rx_x4_status1_descr_modes 8525 */ 8526 #define rx_x4_status1_descr_modes_R_DESCR_MODE_BYPASS 0 8527 #define rx_x4_status1_descr_modes_R_DESCR_MODE_CL49 1 8528 #define rx_x4_status1_descr_modes_R_DESCR_MODE_CL82 2 8529 8530 /**************************************************************************** 8531 * Enums: rx_x4_status1_r_dec_tl_mode 8532 */ 8533 #define rx_x4_status1_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 8534 #define rx_x4_status1_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 8535 #define rx_x4_status1_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 8536 8537 /**************************************************************************** 8538 * Enums: rx_x4_status1_r_dec_fsm_mode 8539 */ 8540 #define rx_x4_status1_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 8541 #define rx_x4_status1_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 8542 #define rx_x4_status1_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 8543 8544 /**************************************************************************** 8545 * Enums: rx_x4_status1_r_deskew_mode 8546 */ 8547 #define rx_x4_status1_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 8548 #define rx_x4_status1_r_deskew_mode_R_DESKEW_MODE_20G 1 8549 #define rx_x4_status1_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 8550 #define rx_x4_status1_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 8551 #define rx_x4_status1_r_deskew_mode_R_DESKEW_MODE_100G 4 8552 #define rx_x4_status1_r_deskew_mode_R_DESKEW_MODE_CL49 5 8553 #define rx_x4_status1_r_deskew_mode_R_DESKEW_MODE_CL91_QUAD 6 8554 #define rx_x4_status1_r_deskew_mode_R_DESKEW_MODE_CL91_SINGLE_BRCM 7 8555 #define rx_x4_status1_r_deskew_mode_R_DESKEW_MODE_CL91_DUAL_BRCM 8 8556 #define rx_x4_status1_r_deskew_mode_R_DESKEW_MODE_CL91_FC 9 8557 8558 /**************************************************************************** 8559 * Enums: rx_x4_status1_bs_dist_modes 8560 */ 8561 #define rx_x4_status1_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 8562 #define rx_x4_status1_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 8563 #define rx_x4_status1_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 8564 #define rx_x4_status1_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 8565 8566 /**************************************************************************** 8567 * Enums: rx_x4_status1_cl49_t_type 8568 */ 8569 #define rx_x4_status1_cl49_t_type_BAD_T_TYPE 15 8570 #define rx_x4_status1_cl49_t_type_T_TYPE_B0 11 8571 #define rx_x4_status1_cl49_t_type_T_TYPE_OB 10 8572 #define rx_x4_status1_cl49_t_type_T_TYPE_B1 9 8573 #define rx_x4_status1_cl49_t_type_T_TYPE_DB 8 8574 #define rx_x4_status1_cl49_t_type_T_TYPE_FC 7 8575 #define rx_x4_status1_cl49_t_type_T_TYPE_TB 6 8576 #define rx_x4_status1_cl49_t_type_T_TYPE_LI 5 8577 #define rx_x4_status1_cl49_t_type_T_TYPE_C 4 8578 #define rx_x4_status1_cl49_t_type_T_TYPE_S 3 8579 #define rx_x4_status1_cl49_t_type_T_TYPE_T 2 8580 #define rx_x4_status1_cl49_t_type_T_TYPE_D 1 8581 #define rx_x4_status1_cl49_t_type_T_TYPE_E 0 8582 8583 /**************************************************************************** 8584 * Enums: rx_x4_status1_cl49_txsm_states 8585 */ 8586 #define rx_x4_status1_cl49_txsm_states_TX_LI 5 8587 #define rx_x4_status1_cl49_txsm_states_TX_E 4 8588 #define rx_x4_status1_cl49_txsm_states_TX_T 3 8589 #define rx_x4_status1_cl49_txsm_states_TX_D 2 8590 #define rx_x4_status1_cl49_txsm_states_TX_C 1 8591 #define rx_x4_status1_cl49_txsm_states_TX_INIT 0 8592 8593 /**************************************************************************** 8594 * Enums: rx_x4_status1_cl49_ltxsm_states 8595 */ 8596 #define rx_x4_status1_cl49_ltxsm_states_TX_LI 32 8597 #define rx_x4_status1_cl49_ltxsm_states_TX_E 16 8598 #define rx_x4_status1_cl49_ltxsm_states_TX_T 8 8599 #define rx_x4_status1_cl49_ltxsm_states_TX_D 4 8600 #define rx_x4_status1_cl49_ltxsm_states_TX_C 2 8601 #define rx_x4_status1_cl49_ltxsm_states_TX_INIT 1 8602 8603 /**************************************************************************** 8604 * Enums: rx_x4_status1_burst_error_mode 8605 */ 8606 #define rx_x4_status1_burst_error_mode_BURST_ERROR_11_BITS 0 8607 #define rx_x4_status1_burst_error_mode_BURST_ERROR_16_BITS 1 8608 #define rx_x4_status1_burst_error_mode_BURST_ERROR_17_BITS 2 8609 #define rx_x4_status1_burst_error_mode_BURST_ERROR_18_BITS 3 8610 #define rx_x4_status1_burst_error_mode_BURST_ERROR_19_BITS 4 8611 #define rx_x4_status1_burst_error_mode_BURST_ERROR_20_BITS 5 8612 #define rx_x4_status1_burst_error_mode_BURST_ERROR_21_BITS 6 8613 #define rx_x4_status1_burst_error_mode_BURST_ERROR_22_BITS 7 8614 #define rx_x4_status1_burst_error_mode_BURST_ERROR_23_BITS 8 8615 #define rx_x4_status1_burst_error_mode_BURST_ERROR_24_BITS 9 8616 #define rx_x4_status1_burst_error_mode_BURST_ERROR_25_BITS 10 8617 #define rx_x4_status1_burst_error_mode_BURST_ERROR_26_BITS 11 8618 #define rx_x4_status1_burst_error_mode_BURST_ERROR_27_BITS 12 8619 #define rx_x4_status1_burst_error_mode_BURST_ERROR_28_BITS 13 8620 #define rx_x4_status1_burst_error_mode_BURST_ERROR_29_BITS 14 8621 #define rx_x4_status1_burst_error_mode_BURST_ERROR_30_BITS 15 8622 #define rx_x4_status1_burst_error_mode_BURST_ERROR_31_BITS 16 8623 #define rx_x4_status1_burst_error_mode_BURST_ERROR_32_BITS 17 8624 #define rx_x4_status1_burst_error_mode_BURST_ERROR_33_BITS 18 8625 #define rx_x4_status1_burst_error_mode_BURST_ERROR_34_BITS 19 8626 #define rx_x4_status1_burst_error_mode_BURST_ERROR_35_BITS 20 8627 #define rx_x4_status1_burst_error_mode_BURST_ERROR_36_BITS 21 8628 #define rx_x4_status1_burst_error_mode_BURST_ERROR_37_BITS 22 8629 #define rx_x4_status1_burst_error_mode_BURST_ERROR_38_BITS 23 8630 #define rx_x4_status1_burst_error_mode_BURST_ERROR_39_BITS 24 8631 #define rx_x4_status1_burst_error_mode_BURST_ERROR_40_BITS 25 8632 #define rx_x4_status1_burst_error_mode_BURST_ERROR_41_BITS 26 8633 8634 /**************************************************************************** 8635 * Enums: rx_x4_status1_bermon_state 8636 */ 8637 #define rx_x4_status1_bermon_state_HI_BER 4 8638 #define rx_x4_status1_bermon_state_GOOD_BER 3 8639 #define rx_x4_status1_bermon_state_BER_TEST_SH 2 8640 #define rx_x4_status1_bermon_state_START_TIMER 1 8641 #define rx_x4_status1_bermon_state_BER_MT_INIT 0 8642 8643 /**************************************************************************** 8644 * Enums: rx_x4_status1_rxsm_state_cl49 8645 */ 8646 #define rx_x4_status1_rxsm_state_cl49_RX_LI 32 8647 #define rx_x4_status1_rxsm_state_cl49_RX_E 16 8648 #define rx_x4_status1_rxsm_state_cl49_RX_T 8 8649 #define rx_x4_status1_rxsm_state_cl49_RX_D 4 8650 #define rx_x4_status1_rxsm_state_cl49_RX_C 2 8651 #define rx_x4_status1_rxsm_state_cl49_RX_INIT 1 8652 8653 /**************************************************************************** 8654 * Enums: rx_x4_status1_r_type 8655 */ 8656 #define rx_x4_status1_r_type_BAD_R_TYPE 15 8657 #define rx_x4_status1_r_type_R_TYPE_B0 11 8658 #define rx_x4_status1_r_type_R_TYPE_OB 10 8659 #define rx_x4_status1_r_type_R_TYPE_B1 9 8660 #define rx_x4_status1_r_type_R_TYPE_DB 8 8661 #define rx_x4_status1_r_type_R_TYPE_FC 7 8662 #define rx_x4_status1_r_type_R_TYPE_TB 6 8663 #define rx_x4_status1_r_type_R_TYPE_LI 5 8664 #define rx_x4_status1_r_type_R_TYPE_C 4 8665 #define rx_x4_status1_r_type_R_TYPE_S 3 8666 #define rx_x4_status1_r_type_R_TYPE_T 2 8667 #define rx_x4_status1_r_type_R_TYPE_D 1 8668 #define rx_x4_status1_r_type_R_TYPE_E 0 8669 8670 /**************************************************************************** 8671 * Enums: rx_x4_status1_am_lock_state 8672 */ 8673 #define rx_x4_status1_am_lock_state_INVALID_AM 512 8674 #define rx_x4_status1_am_lock_state_GOOD_AM 256 8675 #define rx_x4_status1_am_lock_state_COMP_AM 128 8676 #define rx_x4_status1_am_lock_state_TIMER_2 64 8677 #define rx_x4_status1_am_lock_state_AM_2_GOOD 32 8678 #define rx_x4_status1_am_lock_state_COMP_2ND 16 8679 #define rx_x4_status1_am_lock_state_TIMER_1 8 8680 #define rx_x4_status1_am_lock_state_FIND_1ST 4 8681 #define rx_x4_status1_am_lock_state_AM_RESET_CNT 2 8682 #define rx_x4_status1_am_lock_state_AM_LOCK_INIT 1 8683 8684 /**************************************************************************** 8685 * Enums: rx_x4_status1_msg_selector 8686 */ 8687 #define rx_x4_status1_msg_selector_RESERVED 0 8688 #define rx_x4_status1_msg_selector_VALUE_802p3 1 8689 #define rx_x4_status1_msg_selector_VALUE_802p9 2 8690 #define rx_x4_status1_msg_selector_VALUE_802p5 3 8691 #define rx_x4_status1_msg_selector_VALUE_1394 4 8692 8693 /**************************************************************************** 8694 * Enums: rx_x4_status1_synce_enum_stage1 8695 */ 8696 #define rx_x4_status1_synce_enum_stage1_SYNCE_NO_DIV 0 8697 #define rx_x4_status1_synce_enum_stage1_SYNCE_DIV_7 1 8698 #define rx_x4_status1_synce_enum_stage1_SYNCE_DIV_11 2 8699 8700 /**************************************************************************** 8701 * Enums: rx_x4_status1_synce_enum_stage0 8702 */ 8703 #define rx_x4_status1_synce_enum_stage0_SYNCE_NO_DIV 0 8704 #define rx_x4_status1_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 8705 #define rx_x4_status1_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 8706 8707 /**************************************************************************** 8708 * Enums: rx_x4_status1_cl91_sync_state 8709 */ 8710 #define rx_x4_status1_cl91_sync_state_FIND_1ST 0 8711 #define rx_x4_status1_cl91_sync_state_COUNT_NEXT 1 8712 #define rx_x4_status1_cl91_sync_state_COMP_2ND 2 8713 #define rx_x4_status1_cl91_sync_state_TWO_GOOD 3 8714 8715 /**************************************************************************** 8716 * Enums: rx_x4_status1_RS_FEC_sync_state 8717 */ 8718 #define rx_x4_status1_RS_FEC_sync_state_LOCK_INIT 0 8719 #define rx_x4_status1_RS_FEC_sync_state_FIND_1ST 1 8720 #define rx_x4_status1_RS_FEC_sync_state_COUNT_NEXT 2 8721 #define rx_x4_status1_RS_FEC_sync_state_COMP_2ND 3 8722 #define rx_x4_status1_RS_FEC_sync_state_TWO_GOOD 4 8723 8724 /**************************************************************************** 8725 * Enums: rx_x4_status1_cl91_algn_state 8726 */ 8727 #define rx_x4_status1_cl91_algn_state_LOSS_OF_ALIGNMENT 0 8728 #define rx_x4_status1_cl91_algn_state_DESKEW 1 8729 #define rx_x4_status1_cl91_algn_state_DESKEW_FAIL 2 8730 #define rx_x4_status1_cl91_algn_state_ALIGN_ACQUIRED 3 8731 #define rx_x4_status1_cl91_algn_state_CW_GOOD 4 8732 #define rx_x4_status1_cl91_algn_state_CW_BAD 5 8733 #define rx_x4_status1_cl91_algn_state_THREE_BAD 6 8734 8735 /**************************************************************************** 8736 * Enums: rx_x4_status1_RS_FEC_algn_state 8737 */ 8738 #define rx_x4_status1_RS_FEC_algn_state_LOSS_OF_ALIGNMENT 0 8739 #define rx_x4_status1_RS_FEC_algn_state_DESKEW 1 8740 #define rx_x4_status1_RS_FEC_algn_state_DESKEW_FAIL 2 8741 #define rx_x4_status1_RS_FEC_algn_state_ALIGN_ACQUIRED 3 8742 #define rx_x4_status1_RS_FEC_algn_state_CW_GOOD 4 8743 #define rx_x4_status1_RS_FEC_algn_state_CW_BAD 5 8744 #define rx_x4_status1_RS_FEC_algn_state_THREE_BAD 6 8745 8746 /**************************************************************************** 8747 * Enums: rx_x4_status1_fec_sel_override 8748 */ 8749 #define rx_x4_status1_fec_sel_override_NO_OVERRIDE 0 8750 #define rx_x4_status1_fec_sel_override_NO_FEC 1 8751 #define rx_x4_status1_fec_sel_override_FEC_CL74 2 8752 #define rx_x4_status1_fec_sel_override_FEC_CL91 3 8753 8754 /**************************************************************************** 8755 * Enums: rx_x4_status1_cl91_blksync_mode 8756 */ 8757 #define rx_x4_status1_cl91_blksync_mode_R_BLKSYNC_NO_CL91_FEC 0 8758 #define rx_x4_status1_cl91_blksync_mode_R_BLKSYNC_CL91_QUAD_LANE_FEC 1 8759 #define rx_x4_status1_cl91_blksync_mode_R_BLKSYNC_CL91_DUAL_LANE_FEC 2 8760 #define rx_x4_status1_cl91_blksync_mode_R_BLKSYNC_CL91_SINGLE_LANE_FEC 3 8761 #define rx_x4_status1_cl91_blksync_mode_R_BLKSYNC_CL91_FC_FEC 4 8762 8763 /**************************************************************************** 8764 * Enums: rx_x4_status1_r_merge_mode 8765 */ 8766 #define rx_x4_status1_r_merge_mode_R_MERGE_MODE_BYPASS 0 8767 #define rx_x4_status1_r_merge_mode_R_MERGE_MODE_CL91_FC 1 8768 #define rx_x4_status1_r_merge_mode_R_MERGE_MODE_CL91_SINGLE_LANE 2 8769 #define rx_x4_status1_r_merge_mode_R_MERGE_MODE_CL91_DUAL_LANE 3 8770 #define rx_x4_status1_r_merge_mode_R_MERGE_MODE_CL91_QUAD_LANE 4 8771 8772 /**************************************************************************** 8773 * Enums: rx_x4_status1_r_tc_mode 8774 */ 8775 #define rx_x4_status1_r_tc_mode_R_TC_MODE_SINGLE 0 8776 #define rx_x4_status1_r_tc_mode_R_TC_MODE_DUAL 1 8777 #define rx_x4_status1_r_tc_mode_R_TC_MODE_QUAD 2 8778 8779 /**************************************************************************** 8780 * Enums: rx_x4_status1_r_tc_out_mode 8781 */ 8782 #define rx_x4_status1_r_tc_out_mode_R_TC_OUT_MODE_SINGLE 0 8783 #define rx_x4_status1_r_tc_out_mode_R_TC_OUT_MODE_DUAL 1 8784 #define rx_x4_status1_r_tc_out_mode_R_TC_OUT_MODE_QUAD 2 8785 8786 /**************************************************************************** 8787 * Enums: rx_x4_status1_cl91_fec_mode 8788 */ 8789 #define rx_x4_status1_cl91_fec_mode_NO_CL91_FEC 0 8790 #define rx_x4_status1_cl91_fec_mode_CL91_SINGLE_LANE_FC 1 8791 #define rx_x4_status1_cl91_fec_mode_CL91_SINGLE_LANE_BRCM_PROP 2 8792 #define rx_x4_status1_cl91_fec_mode_CL91_DUAL_LANE_BRCM_PROP 3 8793 #define rx_x4_status1_cl91_fec_mode_CL91_QUAD_LANE 4 8794 #define rx_x4_status1_cl91_fec_mode_IEEE_25G_CL91_SINGLE_LANE 5 8795 8796 /**************************************************************************** 8797 * Enums: rx_x4_status1_RS_FEC_fec_mode 8798 */ 8799 #define rx_x4_status1_RS_FEC_fec_mode_NO_RS_FEC_FEC 0 8800 #define rx_x4_status1_RS_FEC_fec_mode_N_A 1 8801 #define rx_x4_status1_RS_FEC_fec_mode_RS_FEC_SINGLE_LANE_BRCM_PROP 2 8802 #define rx_x4_status1_RS_FEC_fec_mode_RS_FEC_DUAL_LANE_BRCM_PROP 3 8803 #define rx_x4_status1_RS_FEC_fec_mode_RS_FEC_QUAD_LANE 4 8804 #define rx_x4_status1_RS_FEC_fec_mode_IEEE_25G_RS_FEC_SINGLE_LANE 5 8805 8806 /**************************************************************************** 8807 * Enums: rx_x4_status1_am_spacing_mul 8808 */ 8809 #define rx_x4_status1_am_spacing_mul_AM_SPACING_MUL_2 0 8810 #define rx_x4_status1_am_spacing_mul_AM_SPACING_MUL_4 1 8811 #define rx_x4_status1_am_spacing_mul_AM_SPACING_MUL_5 2 8812 #define rx_x4_status1_am_spacing_mul_AM_SPACING_MUL_20 3 8813 8814 /**************************************************************************** 8815 * Enums: rx_x4_status2_cl36TxEEEStates_l 8816 */ 8817 #define rx_x4_status2_cl36TxEEEStates_l_TX_REFRESH 8 8818 #define rx_x4_status2_cl36TxEEEStates_l_TX_QUIET 4 8819 #define rx_x4_status2_cl36TxEEEStates_l_TX_SLEEP 2 8820 #define rx_x4_status2_cl36TxEEEStates_l_TX_ACTIVE 1 8821 8822 /**************************************************************************** 8823 * Enums: rx_x4_status2_cl36TxEEEStates_c 8824 */ 8825 #define rx_x4_status2_cl36TxEEEStates_c_TX_REFRESH 3 8826 #define rx_x4_status2_cl36TxEEEStates_c_TX_QUIET 2 8827 #define rx_x4_status2_cl36TxEEEStates_c_TX_SLEEP 1 8828 #define rx_x4_status2_cl36TxEEEStates_c_TX_ACTIVE 0 8829 8830 /**************************************************************************** 8831 * Enums: rx_x4_status2_cl49TxEEEStates_l 8832 */ 8833 #define rx_x4_status2_cl49TxEEEStates_l_SCR_RESET_2 64 8834 #define rx_x4_status2_cl49TxEEEStates_l_SCR_RESET_1 32 8835 #define rx_x4_status2_cl49TxEEEStates_l_TX_WAKE 16 8836 #define rx_x4_status2_cl49TxEEEStates_l_TX_REFRESH 8 8837 #define rx_x4_status2_cl49TxEEEStates_l_TX_QUIET 4 8838 #define rx_x4_status2_cl49TxEEEStates_l_TX_SLEEP 2 8839 #define rx_x4_status2_cl49TxEEEStates_l_TX_ACTIVE 1 8840 8841 /**************************************************************************** 8842 * Enums: rx_x4_status2_fec_req_enum 8843 */ 8844 #define rx_x4_status2_fec_req_enum_FEC_not_supported 0 8845 #define rx_x4_status2_fec_req_enum_FEC_supported_but_not_requested 1 8846 #define rx_x4_status2_fec_req_enum_invalid_setting 2 8847 #define rx_x4_status2_fec_req_enum_FEC_supported_and_requested 3 8848 8849 /**************************************************************************** 8850 * Enums: rx_x4_status2_cl73_pause_enum 8851 */ 8852 #define rx_x4_status2_cl73_pause_enum_No_PAUSE_ability 0 8853 #define rx_x4_status2_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 8854 #define rx_x4_status2_cl73_pause_enum_Symmetric_PAUSE_ability 1 8855 #define rx_x4_status2_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 8856 8857 /**************************************************************************** 8858 * Enums: rx_x4_status2_cl49TxEEEStates_c 8859 */ 8860 #define rx_x4_status2_cl49TxEEEStates_c_SCR_RESET_2 6 8861 #define rx_x4_status2_cl49TxEEEStates_c_SCR_RESET_1 5 8862 #define rx_x4_status2_cl49TxEEEStates_c_TX_WAKE 4 8863 #define rx_x4_status2_cl49TxEEEStates_c_TX_REFRESH 3 8864 #define rx_x4_status2_cl49TxEEEStates_c_TX_QUIET 2 8865 #define rx_x4_status2_cl49TxEEEStates_c_TX_SLEEP 1 8866 #define rx_x4_status2_cl49TxEEEStates_c_TX_ACTIVE 0 8867 8868 /**************************************************************************** 8869 * Enums: rx_x4_status2_cl36RxEEEStates_l 8870 */ 8871 #define rx_x4_status2_cl36RxEEEStates_l_RX_LINK_FAIL 32 8872 #define rx_x4_status2_cl36RxEEEStates_l_RX_WTF 16 8873 #define rx_x4_status2_cl36RxEEEStates_l_RX_WAKE 8 8874 #define rx_x4_status2_cl36RxEEEStates_l_RX_QUIET 4 8875 #define rx_x4_status2_cl36RxEEEStates_l_RX_SLEEP 2 8876 #define rx_x4_status2_cl36RxEEEStates_l_RX_ACTIVE 1 8877 8878 /**************************************************************************** 8879 * Enums: rx_x4_status2_cl36RxEEEStates_c 8880 */ 8881 #define rx_x4_status2_cl36RxEEEStates_c_RX_LINK_FAIL 5 8882 #define rx_x4_status2_cl36RxEEEStates_c_RX_WTF 4 8883 #define rx_x4_status2_cl36RxEEEStates_c_RX_WAKE 3 8884 #define rx_x4_status2_cl36RxEEEStates_c_RX_QUIET 2 8885 #define rx_x4_status2_cl36RxEEEStates_c_RX_SLEEP 1 8886 #define rx_x4_status2_cl36RxEEEStates_c_RX_ACTIVE 0 8887 8888 /**************************************************************************** 8889 * Enums: rx_x4_status2_cl49RxEEEStates_l 8890 */ 8891 #define rx_x4_status2_cl49RxEEEStates_l_RX_LINK_FAIL 32 8892 #define rx_x4_status2_cl49RxEEEStates_l_RX_WTF 16 8893 #define rx_x4_status2_cl49RxEEEStates_l_RX_WAKE 8 8894 #define rx_x4_status2_cl49RxEEEStates_l_RX_QUIET 4 8895 #define rx_x4_status2_cl49RxEEEStates_l_RX_SLEEP 2 8896 #define rx_x4_status2_cl49RxEEEStates_l_RX_ACTIVE 1 8897 8898 /**************************************************************************** 8899 * Enums: rx_x4_status2_cl49RxEEEStates_c 8900 */ 8901 #define rx_x4_status2_cl49RxEEEStates_c_RX_LINK_FAIL 5 8902 #define rx_x4_status2_cl49RxEEEStates_c_RX_WTF 4 8903 #define rx_x4_status2_cl49RxEEEStates_c_RX_WAKE 3 8904 #define rx_x4_status2_cl49RxEEEStates_c_RX_QUIET 2 8905 #define rx_x4_status2_cl49RxEEEStates_c_RX_SLEEP 1 8906 #define rx_x4_status2_cl49RxEEEStates_c_RX_ACTIVE 0 8907 8908 /**************************************************************************** 8909 * Enums: rx_x4_status2_cl48TxEEEStates_l 8910 */ 8911 #define rx_x4_status2_cl48TxEEEStates_l_TX_REFRESH 8 8912 #define rx_x4_status2_cl48TxEEEStates_l_TX_QUIET 4 8913 #define rx_x4_status2_cl48TxEEEStates_l_TX_SLEEP 2 8914 #define rx_x4_status2_cl48TxEEEStates_l_TX_ACTIVE 1 8915 8916 /**************************************************************************** 8917 * Enums: rx_x4_status2_cl48TxEEEStates_c 8918 */ 8919 #define rx_x4_status2_cl48TxEEEStates_c_TX_REFRESH 3 8920 #define rx_x4_status2_cl48TxEEEStates_c_TX_QUIET 2 8921 #define rx_x4_status2_cl48TxEEEStates_c_TX_SLEEP 1 8922 #define rx_x4_status2_cl48TxEEEStates_c_TX_ACTIVE 0 8923 8924 /**************************************************************************** 8925 * Enums: rx_x4_status2_cl48RxEEEStates_l 8926 */ 8927 #define rx_x4_status2_cl48RxEEEStates_l_RX_LINK_FAIL 32 8928 #define rx_x4_status2_cl48RxEEEStates_l_RX_WAKE 16 8929 #define rx_x4_status2_cl48RxEEEStates_l_RX_QUIET 8 8930 #define rx_x4_status2_cl48RxEEEStates_l_RX_DEACT 4 8931 #define rx_x4_status2_cl48RxEEEStates_l_RX_SLEEP 2 8932 #define rx_x4_status2_cl48RxEEEStates_l_RX_ACTIVE 1 8933 8934 /**************************************************************************** 8935 * Enums: rx_x4_status2_cl48RxEEEStates_c 8936 */ 8937 #define rx_x4_status2_cl48RxEEEStates_c_RX_LINK_FAIL 5 8938 #define rx_x4_status2_cl48RxEEEStates_c_RX_WAKE 4 8939 #define rx_x4_status2_cl48RxEEEStates_c_RX_QUIET 3 8940 #define rx_x4_status2_cl48RxEEEStates_c_RX_DEACT 2 8941 #define rx_x4_status2_cl48RxEEEStates_c_RX_SLEEP 1 8942 #define rx_x4_status2_cl48RxEEEStates_c_RX_ACTIVE 0 8943 8944 /**************************************************************************** 8945 * Enums: rx_x4_status2_IQP_Options 8946 */ 8947 #define rx_x4_status2_IQP_Options_i50uA 0 8948 #define rx_x4_status2_IQP_Options_i100uA 1 8949 #define rx_x4_status2_IQP_Options_i150uA 2 8950 #define rx_x4_status2_IQP_Options_i200uA 3 8951 #define rx_x4_status2_IQP_Options_i250uA 4 8952 #define rx_x4_status2_IQP_Options_i300uA 5 8953 #define rx_x4_status2_IQP_Options_i350uA 6 8954 #define rx_x4_status2_IQP_Options_i400uA 7 8955 #define rx_x4_status2_IQP_Options_i450uA 8 8956 #define rx_x4_status2_IQP_Options_i500uA 9 8957 #define rx_x4_status2_IQP_Options_i550uA 10 8958 #define rx_x4_status2_IQP_Options_i600uA 11 8959 #define rx_x4_status2_IQP_Options_i650uA 12 8960 #define rx_x4_status2_IQP_Options_i700uA 13 8961 #define rx_x4_status2_IQP_Options_i750uA 14 8962 #define rx_x4_status2_IQP_Options_i800uA 15 8963 8964 /**************************************************************************** 8965 * Enums: rx_x4_status2_IDriver_Options 8966 */ 8967 #define rx_x4_status2_IDriver_Options_v680mV 0 8968 #define rx_x4_status2_IDriver_Options_v730mV 1 8969 #define rx_x4_status2_IDriver_Options_v780mV 2 8970 #define rx_x4_status2_IDriver_Options_v830mV 3 8971 #define rx_x4_status2_IDriver_Options_v880mV 4 8972 #define rx_x4_status2_IDriver_Options_v930mV 5 8973 #define rx_x4_status2_IDriver_Options_v980mV 6 8974 #define rx_x4_status2_IDriver_Options_v1010mV 7 8975 #define rx_x4_status2_IDriver_Options_v1040mV 8 8976 #define rx_x4_status2_IDriver_Options_v1060mV 9 8977 #define rx_x4_status2_IDriver_Options_v1070mV 10 8978 #define rx_x4_status2_IDriver_Options_v1080mV 11 8979 #define rx_x4_status2_IDriver_Options_v1085mV 12 8980 #define rx_x4_status2_IDriver_Options_v1090mV 13 8981 #define rx_x4_status2_IDriver_Options_v1095mV 14 8982 #define rx_x4_status2_IDriver_Options_v1100mV 15 8983 8984 /**************************************************************************** 8985 * Enums: rx_x4_status2_operationModes 8986 */ 8987 #define rx_x4_status2_operationModes_XGXS 0 8988 #define rx_x4_status2_operationModes_XGXG_nCC 1 8989 #define rx_x4_status2_operationModes_Indlane_OS8 4 8990 #define rx_x4_status2_operationModes_IndLane_OS5 5 8991 #define rx_x4_status2_operationModes_PCI 7 8992 #define rx_x4_status2_operationModes_XGXS_nLQ 8 8993 #define rx_x4_status2_operationModes_XGXS_nLQnCC 9 8994 #define rx_x4_status2_operationModes_PBypass 10 8995 #define rx_x4_status2_operationModes_PBypass_nDSK 11 8996 #define rx_x4_status2_operationModes_ComboCoreMode 12 8997 #define rx_x4_status2_operationModes_Clocks_off 15 8998 8999 /**************************************************************************** 9000 * Enums: rx_x4_status2_actualSpeeds 9001 */ 9002 #define rx_x4_status2_actualSpeeds_dr_10M 0 9003 #define rx_x4_status2_actualSpeeds_dr_100M 1 9004 #define rx_x4_status2_actualSpeeds_dr_1G 2 9005 #define rx_x4_status2_actualSpeeds_dr_2p5G 3 9006 #define rx_x4_status2_actualSpeeds_dr_5G_X4 4 9007 #define rx_x4_status2_actualSpeeds_dr_6G_X4 5 9008 #define rx_x4_status2_actualSpeeds_dr_10G_HiG 6 9009 #define rx_x4_status2_actualSpeeds_dr_10G_CX4 7 9010 #define rx_x4_status2_actualSpeeds_dr_12G_HiG 8 9011 #define rx_x4_status2_actualSpeeds_dr_12p5G_X4 9 9012 #define rx_x4_status2_actualSpeeds_dr_13G_X4 10 9013 #define rx_x4_status2_actualSpeeds_dr_15G_X4 11 9014 #define rx_x4_status2_actualSpeeds_dr_16G_X4 12 9015 #define rx_x4_status2_actualSpeeds_dr_1G_KX 13 9016 #define rx_x4_status2_actualSpeeds_dr_10G_KX4 14 9017 #define rx_x4_status2_actualSpeeds_dr_10G_KR 15 9018 #define rx_x4_status2_actualSpeeds_dr_5G 16 9019 #define rx_x4_status2_actualSpeeds_dr_6p4G 17 9020 #define rx_x4_status2_actualSpeeds_dr_20G_X4 18 9021 #define rx_x4_status2_actualSpeeds_dr_21G_X4 19 9022 #define rx_x4_status2_actualSpeeds_dr_25G_X4 20 9023 #define rx_x4_status2_actualSpeeds_dr_10G_HiG_DXGXS 21 9024 #define rx_x4_status2_actualSpeeds_dr_10G_DXGXS 22 9025 #define rx_x4_status2_actualSpeeds_dr_10p5G_HiG_DXGXS 23 9026 #define rx_x4_status2_actualSpeeds_dr_10p5G_DXGXS 24 9027 #define rx_x4_status2_actualSpeeds_dr_12p773G_HiG_DXGXS 25 9028 #define rx_x4_status2_actualSpeeds_dr_12p773G_DXGXS 26 9029 #define rx_x4_status2_actualSpeeds_dr_10G_XFI 27 9030 #define rx_x4_status2_actualSpeeds_dr_40G 28 9031 #define rx_x4_status2_actualSpeeds_dr_20G_HiG_DXGXS 29 9032 #define rx_x4_status2_actualSpeeds_dr_20G_DXGXS 30 9033 #define rx_x4_status2_actualSpeeds_dr_10G_SFI 31 9034 #define rx_x4_status2_actualSpeeds_dr_31p5G 32 9035 #define rx_x4_status2_actualSpeeds_dr_32p7G 33 9036 #define rx_x4_status2_actualSpeeds_dr_20G_SCR 34 9037 #define rx_x4_status2_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 9038 #define rx_x4_status2_actualSpeeds_dr_10G_DXGXS_SCR 36 9039 #define rx_x4_status2_actualSpeeds_dr_12G_R2 37 9040 #define rx_x4_status2_actualSpeeds_dr_10G_X2 38 9041 #define rx_x4_status2_actualSpeeds_dr_40G_KR4 39 9042 #define rx_x4_status2_actualSpeeds_dr_40G_CR4 40 9043 #define rx_x4_status2_actualSpeeds_dr_100G_CR10 41 9044 #define rx_x4_status2_actualSpeeds_dr_15p75G_DXGXS 44 9045 #define rx_x4_status2_actualSpeeds_dr_20G_KR2 57 9046 #define rx_x4_status2_actualSpeeds_dr_20G_CR2 58 9047 9048 /**************************************************************************** 9049 * Enums: rx_x4_status2_actualSpeedsMisc1 9050 */ 9051 #define rx_x4_status2_actualSpeedsMisc1_dr_2500BRCM_X1 16 9052 #define rx_x4_status2_actualSpeedsMisc1_dr_5000BRCM_X4 17 9053 #define rx_x4_status2_actualSpeedsMisc1_dr_6000BRCM_X4 18 9054 #define rx_x4_status2_actualSpeedsMisc1_dr_10GHiGig_X4 19 9055 #define rx_x4_status2_actualSpeedsMisc1_dr_10GBASE_CX4 20 9056 #define rx_x4_status2_actualSpeedsMisc1_dr_12GHiGig_X4 21 9057 #define rx_x4_status2_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 9058 #define rx_x4_status2_actualSpeedsMisc1_dr_13GHiGig_X4 23 9059 #define rx_x4_status2_actualSpeedsMisc1_dr_15GHiGig_X4 24 9060 #define rx_x4_status2_actualSpeedsMisc1_dr_16GHiGig_X4 25 9061 #define rx_x4_status2_actualSpeedsMisc1_dr_5000BRCM_X1 26 9062 #define rx_x4_status2_actualSpeedsMisc1_dr_6363BRCM_X1 27 9063 #define rx_x4_status2_actualSpeedsMisc1_dr_20GHiGig_X4 28 9064 #define rx_x4_status2_actualSpeedsMisc1_dr_21GHiGig_X4 29 9065 #define rx_x4_status2_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 9066 #define rx_x4_status2_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 9067 9068 /**************************************************************************** 9069 * Enums: rx_x4_status2_IndLaneModes 9070 */ 9071 #define rx_x4_status2_IndLaneModes_SWSDR_div2 0 9072 #define rx_x4_status2_IndLaneModes_SWSDR_div1 1 9073 #define rx_x4_status2_IndLaneModes_DWSDR_div2 2 9074 #define rx_x4_status2_IndLaneModes_DWSDR_div1 3 9075 9076 /**************************************************************************** 9077 * Enums: rx_x4_status2_prbsSelect 9078 */ 9079 #define rx_x4_status2_prbsSelect_prbs7 0 9080 #define rx_x4_status2_prbsSelect_prbs15 1 9081 #define rx_x4_status2_prbsSelect_prbs23 2 9082 #define rx_x4_status2_prbsSelect_prbs31 3 9083 9084 /**************************************************************************** 9085 * Enums: rx_x4_status2_vcoDivider 9086 */ 9087 #define rx_x4_status2_vcoDivider_div32 0 9088 #define rx_x4_status2_vcoDivider_div36 1 9089 #define rx_x4_status2_vcoDivider_div40 2 9090 #define rx_x4_status2_vcoDivider_div42 3 9091 #define rx_x4_status2_vcoDivider_div48 4 9092 #define rx_x4_status2_vcoDivider_div50 5 9093 #define rx_x4_status2_vcoDivider_div52 6 9094 #define rx_x4_status2_vcoDivider_div54 7 9095 #define rx_x4_status2_vcoDivider_div60 8 9096 #define rx_x4_status2_vcoDivider_div64 9 9097 #define rx_x4_status2_vcoDivider_div66 10 9098 #define rx_x4_status2_vcoDivider_div68 11 9099 #define rx_x4_status2_vcoDivider_div70 12 9100 #define rx_x4_status2_vcoDivider_div80 13 9101 #define rx_x4_status2_vcoDivider_div92 14 9102 #define rx_x4_status2_vcoDivider_div100 15 9103 9104 /**************************************************************************** 9105 * Enums: rx_x4_status2_refClkSelect 9106 */ 9107 #define rx_x4_status2_refClkSelect_clk_156p25MHz 1 9108 #define rx_x4_status2_refClkSelect_clk_312p5Mhz 2 9109 9110 /**************************************************************************** 9111 * Enums: rx_x4_status2_aerMMDdevTypeSelect 9112 */ 9113 #define rx_x4_status2_aerMMDdevTypeSelect_combo_core 0 9114 #define rx_x4_status2_aerMMDdevTypeSelect_PMA_PMD 1 9115 #define rx_x4_status2_aerMMDdevTypeSelect_PCS 3 9116 #define rx_x4_status2_aerMMDdevTypeSelect_PHY 4 9117 #define rx_x4_status2_aerMMDdevTypeSelect_DTE 5 9118 #define rx_x4_status2_aerMMDdevTypeSelect_CL73_AN 7 9119 9120 /**************************************************************************** 9121 * Enums: rx_x4_status2_aerMMDportSelect 9122 */ 9123 #define rx_x4_status2_aerMMDportSelect_ln0 0 9124 #define rx_x4_status2_aerMMDportSelect_ln1 1 9125 #define rx_x4_status2_aerMMDportSelect_ln2 2 9126 #define rx_x4_status2_aerMMDportSelect_ln3 3 9127 #define rx_x4_status2_aerMMDportSelect_BCST_ln0_1_2_3 511 9128 #define rx_x4_status2_aerMMDportSelect_BCST_ln0_1 512 9129 #define rx_x4_status2_aerMMDportSelect_BCST_ln2_3 513 9130 9131 /**************************************************************************** 9132 * Enums: rx_x4_status2_firmwareModeSelect 9133 */ 9134 #define rx_x4_status2_firmwareModeSelect_DEFAULT 0 9135 #define rx_x4_status2_firmwareModeSelect_SFP_OPT_LR 1 9136 #define rx_x4_status2_firmwareModeSelect_SFP_DAC 2 9137 #define rx_x4_status2_firmwareModeSelect_XLAUI 3 9138 #define rx_x4_status2_firmwareModeSelect_LONG_CH_6G 4 9139 9140 /**************************************************************************** 9141 * Enums: rx_x4_status2_tempIdxSelect 9142 */ 9143 #define rx_x4_status2_tempIdxSelect_LTE__22p9C 15 9144 #define rx_x4_status2_tempIdxSelect_LTE__12p6C 14 9145 #define rx_x4_status2_tempIdxSelect_LTE__3p0C 13 9146 #define rx_x4_status2_tempIdxSelect_LTE_6p7C 12 9147 #define rx_x4_status2_tempIdxSelect_LTE_16p4C 11 9148 #define rx_x4_status2_tempIdxSelect_LTE_26p6C 10 9149 #define rx_x4_status2_tempIdxSelect_LTE_36p3C 9 9150 #define rx_x4_status2_tempIdxSelect_LTE_46p0C 8 9151 #define rx_x4_status2_tempIdxSelect_LTE_56p2C 7 9152 #define rx_x4_status2_tempIdxSelect_LTE_65p9C 6 9153 #define rx_x4_status2_tempIdxSelect_LTE_75p6C 5 9154 #define rx_x4_status2_tempIdxSelect_LTE_85p3C 4 9155 #define rx_x4_status2_tempIdxSelect_LTE_95p5C 3 9156 #define rx_x4_status2_tempIdxSelect_LTE_105p2C 2 9157 #define rx_x4_status2_tempIdxSelect_LTE_114p9C 1 9158 #define rx_x4_status2_tempIdxSelect_LTE_125p1C 0 9159 9160 /**************************************************************************** 9161 * Enums: rx_x4_status2_port_mode 9162 */ 9163 #define rx_x4_status2_port_mode_QUAD_PORT 0 9164 #define rx_x4_status2_port_mode_TRI_1_PORT 1 9165 #define rx_x4_status2_port_mode_TRI_2_PORT 2 9166 #define rx_x4_status2_port_mode_DUAL_PORT 3 9167 #define rx_x4_status2_port_mode_SINGLE_PORT 4 9168 #define rx_x4_status2_port_mode_SINGLE_OCTAL_PORT 5 9169 9170 /**************************************************************************** 9171 * Enums: rx_x4_status2_rev_letter_enum 9172 */ 9173 #define rx_x4_status2_rev_letter_enum_REV_A 0 9174 #define rx_x4_status2_rev_letter_enum_REV_B 1 9175 #define rx_x4_status2_rev_letter_enum_REV_C 2 9176 #define rx_x4_status2_rev_letter_enum_REV_D 3 9177 9178 /**************************************************************************** 9179 * Enums: rx_x4_status2_rev_number_enum 9180 */ 9181 #define rx_x4_status2_rev_number_enum_REV_0 0 9182 #define rx_x4_status2_rev_number_enum_REV_1 1 9183 #define rx_x4_status2_rev_number_enum_REV_2 2 9184 #define rx_x4_status2_rev_number_enum_REV_3 3 9185 #define rx_x4_status2_rev_number_enum_REV_4 4 9186 #define rx_x4_status2_rev_number_enum_REV_5 5 9187 #define rx_x4_status2_rev_number_enum_REV_6 6 9188 #define rx_x4_status2_rev_number_enum_REV_7 7 9189 9190 /**************************************************************************** 9191 * Enums: rx_x4_status2_bonding_enum 9192 */ 9193 #define rx_x4_status2_bonding_enum_WIRE_BOND 0 9194 #define rx_x4_status2_bonding_enum_FLIP_CHIP 1 9195 9196 /**************************************************************************** 9197 * Enums: rx_x4_status2_tech_process 9198 */ 9199 #define rx_x4_status2_tech_process_PROCESS_90NM 0 9200 #define rx_x4_status2_tech_process_PROCESS_65NM 1 9201 #define rx_x4_status2_tech_process_PROCESS_40NM 2 9202 #define rx_x4_status2_tech_process_PROCESS_28NM 3 9203 #define rx_x4_status2_tech_process_PROCESS_16NM 4 9204 9205 /**************************************************************************** 9206 * Enums: rx_x4_status2_model_num 9207 */ 9208 #define rx_x4_status2_model_num_SERDES_CL73 0 9209 #define rx_x4_status2_model_num_XGXS_16G 1 9210 #define rx_x4_status2_model_num_HYPERCORE 2 9211 #define rx_x4_status2_model_num_HYPERLITE 3 9212 #define rx_x4_status2_model_num_PCIE_G2_PIPE 4 9213 #define rx_x4_status2_model_num_SERDES_1p25GBd 5 9214 #define rx_x4_status2_model_num_SATA2 6 9215 #define rx_x4_status2_model_num_QSGMII 7 9216 #define rx_x4_status2_model_num_XGXS10G 8 9217 #define rx_x4_status2_model_num_WARPCORE 9 9218 #define rx_x4_status2_model_num_XFICORE 10 9219 #define rx_x4_status2_model_num_RXFI 11 9220 #define rx_x4_status2_model_num_WARPLITE 12 9221 #define rx_x4_status2_model_num_PENTACORE 13 9222 #define rx_x4_status2_model_num_ESM 14 9223 #define rx_x4_status2_model_num_QUAD_SGMII 15 9224 #define rx_x4_status2_model_num_WARPCORE_3 16 9225 #define rx_x4_status2_model_num_TSC 17 9226 #define rx_x4_status2_model_num_TSC4E 18 9227 #define rx_x4_status2_model_num_TSC12E 19 9228 #define rx_x4_status2_model_num_TSC4F 20 9229 #define rx_x4_status2_model_num_TSC4F_GEN2 21 9230 #define rx_x4_status2_model_num_XGXS_CL73_90NM 29 9231 #define rx_x4_status2_model_num_SERDES_CL73_90NM 30 9232 #define rx_x4_status2_model_num_WARPCORE3 32 9233 #define rx_x4_status2_model_num_WARPCORE4_TSC 33 9234 #define rx_x4_status2_model_num_RXAUI 34 9235 #define rx_x4_status2_model_num_TSCE_GEN3 35 9236 #define rx_x4_status2_model_num_TSC4F_GEN3 36 9237 #define rx_x4_status2_model_num_TSCBH 37 9238 9239 /**************************************************************************** 9240 * Enums: rx_x4_status2_payload 9241 */ 9242 #define rx_x4_status2_payload_REPEAT_2_BYTES 0 9243 #define rx_x4_status2_payload_RAMPING 1 9244 #define rx_x4_status2_payload_CL48_CRPAT 2 9245 #define rx_x4_status2_payload_CL48_CJPAT 3 9246 #define rx_x4_status2_payload_CL36_LONG_CRPAT 4 9247 #define rx_x4_status2_payload_CL36_SHORT_CRPAT 5 9248 9249 /**************************************************************************** 9250 * Enums: rx_x4_status2_sc 9251 */ 9252 #define rx_x4_status2_sc_SPEED_10G_IEEE_KR1 0 9253 #define rx_x4_status2_sc_SPEED_25G_IEEE_KS1_CS1 1 9254 #define rx_x4_status2_sc_SPEED_25G_IEEE_KR1_CR1 2 9255 #define rx_x4_status2_sc_SPEED_40G_IEEE_KR4 3 9256 #define rx_x4_status2_sc_SPEED_40G_IEEE_CR4 4 9257 #define rx_x4_status2_sc_SPEED_50G_IEEE_KR1_CR1 5 9258 #define rx_x4_status2_sc_SPEED_100G_IEEE_KR4 6 9259 #define rx_x4_status2_sc_SPEED_100G_IEEE_CR4 7 9260 #define rx_x4_status2_sc_SPEED_100G_IEEE_KR2_CR2 8 9261 #define rx_x4_status2_sc_SPEED_200G_IEEE_KR4_CR4 9 9262 #define rx_x4_status2_sc_SPEED_400G_IEEE_X8 10 9263 #define rx_x4_status2_sc_SPEED_CL73_IEEE_20GVCO 11 9264 #define rx_x4_status2_sc_SPEED_CL73_IEEE_25GVCO 12 9265 #define rx_x4_status2_sc_SPEED_CL73_IEEE_26GVCO 13 9266 #define rx_x4_status2_sc_SPEED_20G_BRCM_CR1 14 9267 #define rx_x4_status2_sc_SPEED_20G_BRCM_KR1 15 9268 #define rx_x4_status2_sc_SPEED_25G_BRCM_CR1 16 9269 #define rx_x4_status2_sc_SPEED_25G_BRCM_KR1 17 9270 #define rx_x4_status2_sc_SPEED_40G_BRCM_CR2 18 9271 #define rx_x4_status2_sc_SPEED_40G_BRCM_KR2 19 9272 #define rx_x4_status2_sc_SPEED_50G_BRCM_CR2 20 9273 #define rx_x4_status2_sc_SPEED_50G_BRCM_KR2 21 9274 #define rx_x4_status2_sc_SPEED_50G_BRCM_CR4 22 9275 #define rx_x4_status2_sc_SPEED_50G_BRCM_KR4 23 9276 #define rx_x4_status2_sc_SPEED_50G_BRCM_FEC_544_CR2_KR2 24 9277 #define rx_x4_status2_sc_SPEED_RESERVED_19 25 9278 #define rx_x4_status2_sc_SPEED_50G_BRCM_FEC_544_CR1_KR1 26 9279 #define rx_x4_status2_sc_SPEED_50G_BRCM_NO_FEC_CR1_KR1 27 9280 #define rx_x4_status2_sc_SPEED_50G_BRCM_FEC_528_CR1_KR1 28 9281 #define rx_x4_status2_sc_SPEED_400G_BRCM_NO_FEC_KR8_CR8 29 9282 #define rx_x4_status2_sc_SPEED_400G_BRCM_FEC_KR8_CR8 30 9283 #define rx_x4_status2_sc_SPEED_200G_BRCM_NO_FEC_KR4_CR4 31 9284 #define rx_x4_status2_sc_SPEED_200G_BRCM_KR4_CR4 32 9285 #define rx_x4_status2_sc_SPEED_100G_BRCM_KR4_CR4 33 9286 #define rx_x4_status2_sc_SPEED_RESERVED_22 34 9287 #define rx_x4_status2_sc_SPEED_100G_BRCM_FEC_528_KR2_CR2 35 9288 #define rx_x4_status2_sc_SPEED_100G_BRCM_NO_FEC_KR2_CR2 36 9289 #define rx_x4_status2_sc_SPEED_100G_BRCM_NO_FEC_X4 37 9290 9291 /**************************************************************************** 9292 * Enums: rx_x4_status2_t_fifo_modes 9293 */ 9294 #define rx_x4_status2_t_fifo_modes_T_FIFO_INSERT_NO_AM 0 9295 #define rx_x4_status2_t_fifo_modes_T_FIFO_INSERT_4_AM 1 9296 #define rx_x4_status2_t_fifo_modes_T_FIFO_INSERT_20_AM 2 9297 #define rx_x4_status2_t_fifo_modes_T_FIFO_INSERT_2_AM 3 9298 9299 /**************************************************************************** 9300 * Enums: rx_x4_status2_t_enc_modes 9301 */ 9302 #define rx_x4_status2_t_enc_modes_T_ENC_MODE_BYPASS 0 9303 #define rx_x4_status2_t_enc_modes_T_ENC_MODE_CL49 1 9304 #define rx_x4_status2_t_enc_modes_T_ENC_MODE_CL82 2 9305 9306 /**************************************************************************** 9307 * Enums: rx_x4_status2_btmx_mode 9308 */ 9309 #define rx_x4_status2_btmx_mode_BS_BTMX_MODE_1to1 0 9310 #define rx_x4_status2_btmx_mode_BS_BTMX_MODE_2to1 1 9311 #define rx_x4_status2_btmx_mode_BS_BTMX_MODE_5to1 2 9312 9313 /**************************************************************************** 9314 * Enums: rx_x4_status2_t_type_cl82 9315 */ 9316 #define rx_x4_status2_t_type_cl82_T_TYPE_B1 5 9317 #define rx_x4_status2_t_type_cl82_T_TYPE_C 4 9318 #define rx_x4_status2_t_type_cl82_T_TYPE_S 3 9319 #define rx_x4_status2_t_type_cl82_T_TYPE_T 2 9320 #define rx_x4_status2_t_type_cl82_T_TYPE_D 1 9321 #define rx_x4_status2_t_type_cl82_T_TYPE_E 0 9322 9323 /**************************************************************************** 9324 * Enums: rx_x4_status2_txsm_state_cl82 9325 */ 9326 #define rx_x4_status2_txsm_state_cl82_TX_E 4 9327 #define rx_x4_status2_txsm_state_cl82_TX_T 3 9328 #define rx_x4_status2_txsm_state_cl82_TX_D 2 9329 #define rx_x4_status2_txsm_state_cl82_TX_C 1 9330 #define rx_x4_status2_txsm_state_cl82_TX_INIT 0 9331 9332 /**************************************************************************** 9333 * Enums: rx_x4_status2_ltxsm_state_cl82 9334 */ 9335 #define rx_x4_status2_ltxsm_state_cl82_TX_E 16 9336 #define rx_x4_status2_ltxsm_state_cl82_TX_T 8 9337 #define rx_x4_status2_ltxsm_state_cl82_TX_D 4 9338 #define rx_x4_status2_ltxsm_state_cl82_TX_C 2 9339 #define rx_x4_status2_ltxsm_state_cl82_TX_INIT 1 9340 9341 /**************************************************************************** 9342 * Enums: rx_x4_status2_r_type_coded_cl82 9343 */ 9344 #define rx_x4_status2_r_type_coded_cl82_R_TYPE_B1 32 9345 #define rx_x4_status2_r_type_coded_cl82_R_TYPE_C 16 9346 #define rx_x4_status2_r_type_coded_cl82_R_TYPE_S 8 9347 #define rx_x4_status2_r_type_coded_cl82_R_TYPE_T 4 9348 #define rx_x4_status2_r_type_coded_cl82_R_TYPE_D 2 9349 #define rx_x4_status2_r_type_coded_cl82_R_TYPE_E 1 9350 9351 /**************************************************************************** 9352 * Enums: rx_x4_status2_rxsm_state_cl82 9353 */ 9354 #define rx_x4_status2_rxsm_state_cl82_RX_E 16 9355 #define rx_x4_status2_rxsm_state_cl82_RX_T 8 9356 #define rx_x4_status2_rxsm_state_cl82_RX_D 4 9357 #define rx_x4_status2_rxsm_state_cl82_RX_C 2 9358 #define rx_x4_status2_rxsm_state_cl82_RX_INIT 1 9359 9360 /**************************************************************************** 9361 * Enums: rx_x4_status2_deskew_state 9362 */ 9363 #define rx_x4_status2_deskew_state_ALIGN_ACQUIRED 2 9364 #define rx_x4_status2_deskew_state_LOSS_OF_ALIGNMENT 1 9365 9366 /**************************************************************************** 9367 * Enums: rx_x4_status2_os_mode_enum 9368 */ 9369 #define rx_x4_status2_os_mode_enum_OS_MODE_1 0 9370 #define rx_x4_status2_os_mode_enum_OS_MODE_2 1 9371 #define rx_x4_status2_os_mode_enum_OS_MODE_4 2 9372 #define rx_x4_status2_os_mode_enum_OS_MODE_16p5 8 9373 #define rx_x4_status2_os_mode_enum_OS_MODE_20p625 12 9374 9375 /**************************************************************************** 9376 * Enums: rx_x4_status2_scr_modes 9377 */ 9378 #define rx_x4_status2_scr_modes_T_SCR_MODE_BYPASS 0 9379 #define rx_x4_status2_scr_modes_T_SCR_MODE_CL49 1 9380 #define rx_x4_status2_scr_modes_T_SCR_MODE_40G_2_LANE 2 9381 #define rx_x4_status2_scr_modes_T_SCR_MODE_100G 3 9382 #define rx_x4_status2_scr_modes_T_SCR_MODE_20G 4 9383 #define rx_x4_status2_scr_modes_T_SCR_MODE_40G_4_LANE 5 9384 9385 /**************************************************************************** 9386 * Enums: rx_x4_status2_descr_modes 9387 */ 9388 #define rx_x4_status2_descr_modes_R_DESCR_MODE_BYPASS 0 9389 #define rx_x4_status2_descr_modes_R_DESCR_MODE_CL49 1 9390 #define rx_x4_status2_descr_modes_R_DESCR_MODE_CL82 2 9391 9392 /**************************************************************************** 9393 * Enums: rx_x4_status2_r_dec_tl_mode 9394 */ 9395 #define rx_x4_status2_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 9396 #define rx_x4_status2_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 9397 #define rx_x4_status2_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 9398 9399 /**************************************************************************** 9400 * Enums: rx_x4_status2_r_dec_fsm_mode 9401 */ 9402 #define rx_x4_status2_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 9403 #define rx_x4_status2_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 9404 #define rx_x4_status2_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 9405 9406 /**************************************************************************** 9407 * Enums: rx_x4_status2_r_deskew_mode 9408 */ 9409 #define rx_x4_status2_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 9410 #define rx_x4_status2_r_deskew_mode_R_DESKEW_MODE_20G 1 9411 #define rx_x4_status2_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 9412 #define rx_x4_status2_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 9413 #define rx_x4_status2_r_deskew_mode_R_DESKEW_MODE_100G 4 9414 #define rx_x4_status2_r_deskew_mode_R_DESKEW_MODE_CL49 5 9415 #define rx_x4_status2_r_deskew_mode_R_DESKEW_MODE_CL91_QUAD 6 9416 #define rx_x4_status2_r_deskew_mode_R_DESKEW_MODE_CL91_SINGLE_BRCM 7 9417 #define rx_x4_status2_r_deskew_mode_R_DESKEW_MODE_CL91_DUAL_BRCM 8 9418 #define rx_x4_status2_r_deskew_mode_R_DESKEW_MODE_CL91_FC 9 9419 9420 /**************************************************************************** 9421 * Enums: rx_x4_status2_bs_dist_modes 9422 */ 9423 #define rx_x4_status2_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 9424 #define rx_x4_status2_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 9425 #define rx_x4_status2_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 9426 #define rx_x4_status2_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 9427 9428 /**************************************************************************** 9429 * Enums: rx_x4_status2_cl49_t_type 9430 */ 9431 #define rx_x4_status2_cl49_t_type_BAD_T_TYPE 15 9432 #define rx_x4_status2_cl49_t_type_T_TYPE_B0 11 9433 #define rx_x4_status2_cl49_t_type_T_TYPE_OB 10 9434 #define rx_x4_status2_cl49_t_type_T_TYPE_B1 9 9435 #define rx_x4_status2_cl49_t_type_T_TYPE_DB 8 9436 #define rx_x4_status2_cl49_t_type_T_TYPE_FC 7 9437 #define rx_x4_status2_cl49_t_type_T_TYPE_TB 6 9438 #define rx_x4_status2_cl49_t_type_T_TYPE_LI 5 9439 #define rx_x4_status2_cl49_t_type_T_TYPE_C 4 9440 #define rx_x4_status2_cl49_t_type_T_TYPE_S 3 9441 #define rx_x4_status2_cl49_t_type_T_TYPE_T 2 9442 #define rx_x4_status2_cl49_t_type_T_TYPE_D 1 9443 #define rx_x4_status2_cl49_t_type_T_TYPE_E 0 9444 9445 /**************************************************************************** 9446 * Enums: rx_x4_status2_cl49_txsm_states 9447 */ 9448 #define rx_x4_status2_cl49_txsm_states_TX_LI 5 9449 #define rx_x4_status2_cl49_txsm_states_TX_E 4 9450 #define rx_x4_status2_cl49_txsm_states_TX_T 3 9451 #define rx_x4_status2_cl49_txsm_states_TX_D 2 9452 #define rx_x4_status2_cl49_txsm_states_TX_C 1 9453 #define rx_x4_status2_cl49_txsm_states_TX_INIT 0 9454 9455 /**************************************************************************** 9456 * Enums: rx_x4_status2_cl49_ltxsm_states 9457 */ 9458 #define rx_x4_status2_cl49_ltxsm_states_TX_LI 32 9459 #define rx_x4_status2_cl49_ltxsm_states_TX_E 16 9460 #define rx_x4_status2_cl49_ltxsm_states_TX_T 8 9461 #define rx_x4_status2_cl49_ltxsm_states_TX_D 4 9462 #define rx_x4_status2_cl49_ltxsm_states_TX_C 2 9463 #define rx_x4_status2_cl49_ltxsm_states_TX_INIT 1 9464 9465 /**************************************************************************** 9466 * Enums: rx_x4_status2_burst_error_mode 9467 */ 9468 #define rx_x4_status2_burst_error_mode_BURST_ERROR_11_BITS 0 9469 #define rx_x4_status2_burst_error_mode_BURST_ERROR_16_BITS 1 9470 #define rx_x4_status2_burst_error_mode_BURST_ERROR_17_BITS 2 9471 #define rx_x4_status2_burst_error_mode_BURST_ERROR_18_BITS 3 9472 #define rx_x4_status2_burst_error_mode_BURST_ERROR_19_BITS 4 9473 #define rx_x4_status2_burst_error_mode_BURST_ERROR_20_BITS 5 9474 #define rx_x4_status2_burst_error_mode_BURST_ERROR_21_BITS 6 9475 #define rx_x4_status2_burst_error_mode_BURST_ERROR_22_BITS 7 9476 #define rx_x4_status2_burst_error_mode_BURST_ERROR_23_BITS 8 9477 #define rx_x4_status2_burst_error_mode_BURST_ERROR_24_BITS 9 9478 #define rx_x4_status2_burst_error_mode_BURST_ERROR_25_BITS 10 9479 #define rx_x4_status2_burst_error_mode_BURST_ERROR_26_BITS 11 9480 #define rx_x4_status2_burst_error_mode_BURST_ERROR_27_BITS 12 9481 #define rx_x4_status2_burst_error_mode_BURST_ERROR_28_BITS 13 9482 #define rx_x4_status2_burst_error_mode_BURST_ERROR_29_BITS 14 9483 #define rx_x4_status2_burst_error_mode_BURST_ERROR_30_BITS 15 9484 #define rx_x4_status2_burst_error_mode_BURST_ERROR_31_BITS 16 9485 #define rx_x4_status2_burst_error_mode_BURST_ERROR_32_BITS 17 9486 #define rx_x4_status2_burst_error_mode_BURST_ERROR_33_BITS 18 9487 #define rx_x4_status2_burst_error_mode_BURST_ERROR_34_BITS 19 9488 #define rx_x4_status2_burst_error_mode_BURST_ERROR_35_BITS 20 9489 #define rx_x4_status2_burst_error_mode_BURST_ERROR_36_BITS 21 9490 #define rx_x4_status2_burst_error_mode_BURST_ERROR_37_BITS 22 9491 #define rx_x4_status2_burst_error_mode_BURST_ERROR_38_BITS 23 9492 #define rx_x4_status2_burst_error_mode_BURST_ERROR_39_BITS 24 9493 #define rx_x4_status2_burst_error_mode_BURST_ERROR_40_BITS 25 9494 #define rx_x4_status2_burst_error_mode_BURST_ERROR_41_BITS 26 9495 9496 /**************************************************************************** 9497 * Enums: rx_x4_status2_bermon_state 9498 */ 9499 #define rx_x4_status2_bermon_state_HI_BER 4 9500 #define rx_x4_status2_bermon_state_GOOD_BER 3 9501 #define rx_x4_status2_bermon_state_BER_TEST_SH 2 9502 #define rx_x4_status2_bermon_state_START_TIMER 1 9503 #define rx_x4_status2_bermon_state_BER_MT_INIT 0 9504 9505 /**************************************************************************** 9506 * Enums: rx_x4_status2_rxsm_state_cl49 9507 */ 9508 #define rx_x4_status2_rxsm_state_cl49_RX_LI 32 9509 #define rx_x4_status2_rxsm_state_cl49_RX_E 16 9510 #define rx_x4_status2_rxsm_state_cl49_RX_T 8 9511 #define rx_x4_status2_rxsm_state_cl49_RX_D 4 9512 #define rx_x4_status2_rxsm_state_cl49_RX_C 2 9513 #define rx_x4_status2_rxsm_state_cl49_RX_INIT 1 9514 9515 /**************************************************************************** 9516 * Enums: rx_x4_status2_r_type 9517 */ 9518 #define rx_x4_status2_r_type_BAD_R_TYPE 15 9519 #define rx_x4_status2_r_type_R_TYPE_B0 11 9520 #define rx_x4_status2_r_type_R_TYPE_OB 10 9521 #define rx_x4_status2_r_type_R_TYPE_B1 9 9522 #define rx_x4_status2_r_type_R_TYPE_DB 8 9523 #define rx_x4_status2_r_type_R_TYPE_FC 7 9524 #define rx_x4_status2_r_type_R_TYPE_TB 6 9525 #define rx_x4_status2_r_type_R_TYPE_LI 5 9526 #define rx_x4_status2_r_type_R_TYPE_C 4 9527 #define rx_x4_status2_r_type_R_TYPE_S 3 9528 #define rx_x4_status2_r_type_R_TYPE_T 2 9529 #define rx_x4_status2_r_type_R_TYPE_D 1 9530 #define rx_x4_status2_r_type_R_TYPE_E 0 9531 9532 /**************************************************************************** 9533 * Enums: rx_x4_status2_am_lock_state 9534 */ 9535 #define rx_x4_status2_am_lock_state_INVALID_AM 512 9536 #define rx_x4_status2_am_lock_state_GOOD_AM 256 9537 #define rx_x4_status2_am_lock_state_COMP_AM 128 9538 #define rx_x4_status2_am_lock_state_TIMER_2 64 9539 #define rx_x4_status2_am_lock_state_AM_2_GOOD 32 9540 #define rx_x4_status2_am_lock_state_COMP_2ND 16 9541 #define rx_x4_status2_am_lock_state_TIMER_1 8 9542 #define rx_x4_status2_am_lock_state_FIND_1ST 4 9543 #define rx_x4_status2_am_lock_state_AM_RESET_CNT 2 9544 #define rx_x4_status2_am_lock_state_AM_LOCK_INIT 1 9545 9546 /**************************************************************************** 9547 * Enums: rx_x4_status2_msg_selector 9548 */ 9549 #define rx_x4_status2_msg_selector_RESERVED 0 9550 #define rx_x4_status2_msg_selector_VALUE_802p3 1 9551 #define rx_x4_status2_msg_selector_VALUE_802p9 2 9552 #define rx_x4_status2_msg_selector_VALUE_802p5 3 9553 #define rx_x4_status2_msg_selector_VALUE_1394 4 9554 9555 /**************************************************************************** 9556 * Enums: rx_x4_status2_synce_enum_stage1 9557 */ 9558 #define rx_x4_status2_synce_enum_stage1_SYNCE_NO_DIV 0 9559 #define rx_x4_status2_synce_enum_stage1_SYNCE_DIV_7 1 9560 #define rx_x4_status2_synce_enum_stage1_SYNCE_DIV_11 2 9561 9562 /**************************************************************************** 9563 * Enums: rx_x4_status2_synce_enum_stage0 9564 */ 9565 #define rx_x4_status2_synce_enum_stage0_SYNCE_NO_DIV 0 9566 #define rx_x4_status2_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 9567 #define rx_x4_status2_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 9568 9569 /**************************************************************************** 9570 * Enums: rx_x4_status2_cl91_sync_state 9571 */ 9572 #define rx_x4_status2_cl91_sync_state_FIND_1ST 0 9573 #define rx_x4_status2_cl91_sync_state_COUNT_NEXT 1 9574 #define rx_x4_status2_cl91_sync_state_COMP_2ND 2 9575 #define rx_x4_status2_cl91_sync_state_TWO_GOOD 3 9576 9577 /**************************************************************************** 9578 * Enums: rx_x4_status2_RS_FEC_sync_state 9579 */ 9580 #define rx_x4_status2_RS_FEC_sync_state_LOCK_INIT 0 9581 #define rx_x4_status2_RS_FEC_sync_state_FIND_1ST 1 9582 #define rx_x4_status2_RS_FEC_sync_state_COUNT_NEXT 2 9583 #define rx_x4_status2_RS_FEC_sync_state_COMP_2ND 3 9584 #define rx_x4_status2_RS_FEC_sync_state_TWO_GOOD 4 9585 9586 /**************************************************************************** 9587 * Enums: rx_x4_status2_cl91_algn_state 9588 */ 9589 #define rx_x4_status2_cl91_algn_state_LOSS_OF_ALIGNMENT 0 9590 #define rx_x4_status2_cl91_algn_state_DESKEW 1 9591 #define rx_x4_status2_cl91_algn_state_DESKEW_FAIL 2 9592 #define rx_x4_status2_cl91_algn_state_ALIGN_ACQUIRED 3 9593 #define rx_x4_status2_cl91_algn_state_CW_GOOD 4 9594 #define rx_x4_status2_cl91_algn_state_CW_BAD 5 9595 #define rx_x4_status2_cl91_algn_state_THREE_BAD 6 9596 9597 /**************************************************************************** 9598 * Enums: rx_x4_status2_RS_FEC_algn_state 9599 */ 9600 #define rx_x4_status2_RS_FEC_algn_state_LOSS_OF_ALIGNMENT 0 9601 #define rx_x4_status2_RS_FEC_algn_state_DESKEW 1 9602 #define rx_x4_status2_RS_FEC_algn_state_DESKEW_FAIL 2 9603 #define rx_x4_status2_RS_FEC_algn_state_ALIGN_ACQUIRED 3 9604 #define rx_x4_status2_RS_FEC_algn_state_CW_GOOD 4 9605 #define rx_x4_status2_RS_FEC_algn_state_CW_BAD 5 9606 #define rx_x4_status2_RS_FEC_algn_state_THREE_BAD 6 9607 9608 /**************************************************************************** 9609 * Enums: rx_x4_status2_fec_sel_override 9610 */ 9611 #define rx_x4_status2_fec_sel_override_NO_OVERRIDE 0 9612 #define rx_x4_status2_fec_sel_override_NO_FEC 1 9613 #define rx_x4_status2_fec_sel_override_FEC_CL74 2 9614 #define rx_x4_status2_fec_sel_override_FEC_CL91 3 9615 9616 /**************************************************************************** 9617 * Enums: rx_x4_status2_cl91_blksync_mode 9618 */ 9619 #define rx_x4_status2_cl91_blksync_mode_R_BLKSYNC_NO_CL91_FEC 0 9620 #define rx_x4_status2_cl91_blksync_mode_R_BLKSYNC_CL91_QUAD_LANE_FEC 1 9621 #define rx_x4_status2_cl91_blksync_mode_R_BLKSYNC_CL91_DUAL_LANE_FEC 2 9622 #define rx_x4_status2_cl91_blksync_mode_R_BLKSYNC_CL91_SINGLE_LANE_FEC 3 9623 #define rx_x4_status2_cl91_blksync_mode_R_BLKSYNC_CL91_FC_FEC 4 9624 9625 /**************************************************************************** 9626 * Enums: rx_x4_status2_r_merge_mode 9627 */ 9628 #define rx_x4_status2_r_merge_mode_R_MERGE_MODE_BYPASS 0 9629 #define rx_x4_status2_r_merge_mode_R_MERGE_MODE_CL91_FC 1 9630 #define rx_x4_status2_r_merge_mode_R_MERGE_MODE_CL91_SINGLE_LANE 2 9631 #define rx_x4_status2_r_merge_mode_R_MERGE_MODE_CL91_DUAL_LANE 3 9632 #define rx_x4_status2_r_merge_mode_R_MERGE_MODE_CL91_QUAD_LANE 4 9633 9634 /**************************************************************************** 9635 * Enums: rx_x4_status2_r_tc_mode 9636 */ 9637 #define rx_x4_status2_r_tc_mode_R_TC_MODE_SINGLE 0 9638 #define rx_x4_status2_r_tc_mode_R_TC_MODE_DUAL 1 9639 #define rx_x4_status2_r_tc_mode_R_TC_MODE_QUAD 2 9640 9641 /**************************************************************************** 9642 * Enums: rx_x4_status2_r_tc_out_mode 9643 */ 9644 #define rx_x4_status2_r_tc_out_mode_R_TC_OUT_MODE_SINGLE 0 9645 #define rx_x4_status2_r_tc_out_mode_R_TC_OUT_MODE_DUAL 1 9646 #define rx_x4_status2_r_tc_out_mode_R_TC_OUT_MODE_QUAD 2 9647 9648 /**************************************************************************** 9649 * Enums: rx_x4_status2_cl91_fec_mode 9650 */ 9651 #define rx_x4_status2_cl91_fec_mode_NO_CL91_FEC 0 9652 #define rx_x4_status2_cl91_fec_mode_CL91_SINGLE_LANE_FC 1 9653 #define rx_x4_status2_cl91_fec_mode_CL91_SINGLE_LANE_BRCM_PROP 2 9654 #define rx_x4_status2_cl91_fec_mode_CL91_DUAL_LANE_BRCM_PROP 3 9655 #define rx_x4_status2_cl91_fec_mode_CL91_QUAD_LANE 4 9656 #define rx_x4_status2_cl91_fec_mode_IEEE_25G_CL91_SINGLE_LANE 5 9657 9658 /**************************************************************************** 9659 * Enums: rx_x4_status2_RS_FEC_fec_mode 9660 */ 9661 #define rx_x4_status2_RS_FEC_fec_mode_NO_RS_FEC_FEC 0 9662 #define rx_x4_status2_RS_FEC_fec_mode_N_A 1 9663 #define rx_x4_status2_RS_FEC_fec_mode_RS_FEC_SINGLE_LANE_BRCM_PROP 2 9664 #define rx_x4_status2_RS_FEC_fec_mode_RS_FEC_DUAL_LANE_BRCM_PROP 3 9665 #define rx_x4_status2_RS_FEC_fec_mode_RS_FEC_QUAD_LANE 4 9666 #define rx_x4_status2_RS_FEC_fec_mode_IEEE_25G_RS_FEC_SINGLE_LANE 5 9667 9668 /**************************************************************************** 9669 * Enums: rx_x4_status2_am_spacing_mul 9670 */ 9671 #define rx_x4_status2_am_spacing_mul_AM_SPACING_MUL_2 0 9672 #define rx_x4_status2_am_spacing_mul_AM_SPACING_MUL_4 1 9673 #define rx_x4_status2_am_spacing_mul_AM_SPACING_MUL_5 2 9674 #define rx_x4_status2_am_spacing_mul_AM_SPACING_MUL_20 3 9675 9676 /**************************************************************************** 9677 * Enums: rx_x4_status3_cl36TxEEEStates_l 9678 */ 9679 #define rx_x4_status3_cl36TxEEEStates_l_TX_REFRESH 8 9680 #define rx_x4_status3_cl36TxEEEStates_l_TX_QUIET 4 9681 #define rx_x4_status3_cl36TxEEEStates_l_TX_SLEEP 2 9682 #define rx_x4_status3_cl36TxEEEStates_l_TX_ACTIVE 1 9683 9684 /**************************************************************************** 9685 * Enums: rx_x4_status3_cl36TxEEEStates_c 9686 */ 9687 #define rx_x4_status3_cl36TxEEEStates_c_TX_REFRESH 3 9688 #define rx_x4_status3_cl36TxEEEStates_c_TX_QUIET 2 9689 #define rx_x4_status3_cl36TxEEEStates_c_TX_SLEEP 1 9690 #define rx_x4_status3_cl36TxEEEStates_c_TX_ACTIVE 0 9691 9692 /**************************************************************************** 9693 * Enums: rx_x4_status3_cl49TxEEEStates_l 9694 */ 9695 #define rx_x4_status3_cl49TxEEEStates_l_SCR_RESET_2 64 9696 #define rx_x4_status3_cl49TxEEEStates_l_SCR_RESET_1 32 9697 #define rx_x4_status3_cl49TxEEEStates_l_TX_WAKE 16 9698 #define rx_x4_status3_cl49TxEEEStates_l_TX_REFRESH 8 9699 #define rx_x4_status3_cl49TxEEEStates_l_TX_QUIET 4 9700 #define rx_x4_status3_cl49TxEEEStates_l_TX_SLEEP 2 9701 #define rx_x4_status3_cl49TxEEEStates_l_TX_ACTIVE 1 9702 9703 /**************************************************************************** 9704 * Enums: rx_x4_status3_fec_req_enum 9705 */ 9706 #define rx_x4_status3_fec_req_enum_FEC_not_supported 0 9707 #define rx_x4_status3_fec_req_enum_FEC_supported_but_not_requested 1 9708 #define rx_x4_status3_fec_req_enum_invalid_setting 2 9709 #define rx_x4_status3_fec_req_enum_FEC_supported_and_requested 3 9710 9711 /**************************************************************************** 9712 * Enums: rx_x4_status3_cl73_pause_enum 9713 */ 9714 #define rx_x4_status3_cl73_pause_enum_No_PAUSE_ability 0 9715 #define rx_x4_status3_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 9716 #define rx_x4_status3_cl73_pause_enum_Symmetric_PAUSE_ability 1 9717 #define rx_x4_status3_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 9718 9719 /**************************************************************************** 9720 * Enums: rx_x4_status3_cl49TxEEEStates_c 9721 */ 9722 #define rx_x4_status3_cl49TxEEEStates_c_SCR_RESET_2 6 9723 #define rx_x4_status3_cl49TxEEEStates_c_SCR_RESET_1 5 9724 #define rx_x4_status3_cl49TxEEEStates_c_TX_WAKE 4 9725 #define rx_x4_status3_cl49TxEEEStates_c_TX_REFRESH 3 9726 #define rx_x4_status3_cl49TxEEEStates_c_TX_QUIET 2 9727 #define rx_x4_status3_cl49TxEEEStates_c_TX_SLEEP 1 9728 #define rx_x4_status3_cl49TxEEEStates_c_TX_ACTIVE 0 9729 9730 /**************************************************************************** 9731 * Enums: rx_x4_status3_cl36RxEEEStates_l 9732 */ 9733 #define rx_x4_status3_cl36RxEEEStates_l_RX_LINK_FAIL 32 9734 #define rx_x4_status3_cl36RxEEEStates_l_RX_WTF 16 9735 #define rx_x4_status3_cl36RxEEEStates_l_RX_WAKE 8 9736 #define rx_x4_status3_cl36RxEEEStates_l_RX_QUIET 4 9737 #define rx_x4_status3_cl36RxEEEStates_l_RX_SLEEP 2 9738 #define rx_x4_status3_cl36RxEEEStates_l_RX_ACTIVE 1 9739 9740 /**************************************************************************** 9741 * Enums: rx_x4_status3_cl36RxEEEStates_c 9742 */ 9743 #define rx_x4_status3_cl36RxEEEStates_c_RX_LINK_FAIL 5 9744 #define rx_x4_status3_cl36RxEEEStates_c_RX_WTF 4 9745 #define rx_x4_status3_cl36RxEEEStates_c_RX_WAKE 3 9746 #define rx_x4_status3_cl36RxEEEStates_c_RX_QUIET 2 9747 #define rx_x4_status3_cl36RxEEEStates_c_RX_SLEEP 1 9748 #define rx_x4_status3_cl36RxEEEStates_c_RX_ACTIVE 0 9749 9750 /**************************************************************************** 9751 * Enums: rx_x4_status3_cl49RxEEEStates_l 9752 */ 9753 #define rx_x4_status3_cl49RxEEEStates_l_RX_LINK_FAIL 32 9754 #define rx_x4_status3_cl49RxEEEStates_l_RX_WTF 16 9755 #define rx_x4_status3_cl49RxEEEStates_l_RX_WAKE 8 9756 #define rx_x4_status3_cl49RxEEEStates_l_RX_QUIET 4 9757 #define rx_x4_status3_cl49RxEEEStates_l_RX_SLEEP 2 9758 #define rx_x4_status3_cl49RxEEEStates_l_RX_ACTIVE 1 9759 9760 /**************************************************************************** 9761 * Enums: rx_x4_status3_cl49RxEEEStates_c 9762 */ 9763 #define rx_x4_status3_cl49RxEEEStates_c_RX_LINK_FAIL 5 9764 #define rx_x4_status3_cl49RxEEEStates_c_RX_WTF 4 9765 #define rx_x4_status3_cl49RxEEEStates_c_RX_WAKE 3 9766 #define rx_x4_status3_cl49RxEEEStates_c_RX_QUIET 2 9767 #define rx_x4_status3_cl49RxEEEStates_c_RX_SLEEP 1 9768 #define rx_x4_status3_cl49RxEEEStates_c_RX_ACTIVE 0 9769 9770 /**************************************************************************** 9771 * Enums: rx_x4_status3_cl48TxEEEStates_l 9772 */ 9773 #define rx_x4_status3_cl48TxEEEStates_l_TX_REFRESH 8 9774 #define rx_x4_status3_cl48TxEEEStates_l_TX_QUIET 4 9775 #define rx_x4_status3_cl48TxEEEStates_l_TX_SLEEP 2 9776 #define rx_x4_status3_cl48TxEEEStates_l_TX_ACTIVE 1 9777 9778 /**************************************************************************** 9779 * Enums: rx_x4_status3_cl48TxEEEStates_c 9780 */ 9781 #define rx_x4_status3_cl48TxEEEStates_c_TX_REFRESH 3 9782 #define rx_x4_status3_cl48TxEEEStates_c_TX_QUIET 2 9783 #define rx_x4_status3_cl48TxEEEStates_c_TX_SLEEP 1 9784 #define rx_x4_status3_cl48TxEEEStates_c_TX_ACTIVE 0 9785 9786 /**************************************************************************** 9787 * Enums: rx_x4_status3_cl48RxEEEStates_l 9788 */ 9789 #define rx_x4_status3_cl48RxEEEStates_l_RX_LINK_FAIL 32 9790 #define rx_x4_status3_cl48RxEEEStates_l_RX_WAKE 16 9791 #define rx_x4_status3_cl48RxEEEStates_l_RX_QUIET 8 9792 #define rx_x4_status3_cl48RxEEEStates_l_RX_DEACT 4 9793 #define rx_x4_status3_cl48RxEEEStates_l_RX_SLEEP 2 9794 #define rx_x4_status3_cl48RxEEEStates_l_RX_ACTIVE 1 9795 9796 /**************************************************************************** 9797 * Enums: rx_x4_status3_cl48RxEEEStates_c 9798 */ 9799 #define rx_x4_status3_cl48RxEEEStates_c_RX_LINK_FAIL 5 9800 #define rx_x4_status3_cl48RxEEEStates_c_RX_WAKE 4 9801 #define rx_x4_status3_cl48RxEEEStates_c_RX_QUIET 3 9802 #define rx_x4_status3_cl48RxEEEStates_c_RX_DEACT 2 9803 #define rx_x4_status3_cl48RxEEEStates_c_RX_SLEEP 1 9804 #define rx_x4_status3_cl48RxEEEStates_c_RX_ACTIVE 0 9805 9806 /**************************************************************************** 9807 * Enums: rx_x4_status3_IQP_Options 9808 */ 9809 #define rx_x4_status3_IQP_Options_i50uA 0 9810 #define rx_x4_status3_IQP_Options_i100uA 1 9811 #define rx_x4_status3_IQP_Options_i150uA 2 9812 #define rx_x4_status3_IQP_Options_i200uA 3 9813 #define rx_x4_status3_IQP_Options_i250uA 4 9814 #define rx_x4_status3_IQP_Options_i300uA 5 9815 #define rx_x4_status3_IQP_Options_i350uA 6 9816 #define rx_x4_status3_IQP_Options_i400uA 7 9817 #define rx_x4_status3_IQP_Options_i450uA 8 9818 #define rx_x4_status3_IQP_Options_i500uA 9 9819 #define rx_x4_status3_IQP_Options_i550uA 10 9820 #define rx_x4_status3_IQP_Options_i600uA 11 9821 #define rx_x4_status3_IQP_Options_i650uA 12 9822 #define rx_x4_status3_IQP_Options_i700uA 13 9823 #define rx_x4_status3_IQP_Options_i750uA 14 9824 #define rx_x4_status3_IQP_Options_i800uA 15 9825 9826 /**************************************************************************** 9827 * Enums: rx_x4_status3_IDriver_Options 9828 */ 9829 #define rx_x4_status3_IDriver_Options_v680mV 0 9830 #define rx_x4_status3_IDriver_Options_v730mV 1 9831 #define rx_x4_status3_IDriver_Options_v780mV 2 9832 #define rx_x4_status3_IDriver_Options_v830mV 3 9833 #define rx_x4_status3_IDriver_Options_v880mV 4 9834 #define rx_x4_status3_IDriver_Options_v930mV 5 9835 #define rx_x4_status3_IDriver_Options_v980mV 6 9836 #define rx_x4_status3_IDriver_Options_v1010mV 7 9837 #define rx_x4_status3_IDriver_Options_v1040mV 8 9838 #define rx_x4_status3_IDriver_Options_v1060mV 9 9839 #define rx_x4_status3_IDriver_Options_v1070mV 10 9840 #define rx_x4_status3_IDriver_Options_v1080mV 11 9841 #define rx_x4_status3_IDriver_Options_v1085mV 12 9842 #define rx_x4_status3_IDriver_Options_v1090mV 13 9843 #define rx_x4_status3_IDriver_Options_v1095mV 14 9844 #define rx_x4_status3_IDriver_Options_v1100mV 15 9845 9846 /**************************************************************************** 9847 * Enums: rx_x4_status3_operationModes 9848 */ 9849 #define rx_x4_status3_operationModes_XGXS 0 9850 #define rx_x4_status3_operationModes_XGXG_nCC 1 9851 #define rx_x4_status3_operationModes_Indlane_OS8 4 9852 #define rx_x4_status3_operationModes_IndLane_OS5 5 9853 #define rx_x4_status3_operationModes_PCI 7 9854 #define rx_x4_status3_operationModes_XGXS_nLQ 8 9855 #define rx_x4_status3_operationModes_XGXS_nLQnCC 9 9856 #define rx_x4_status3_operationModes_PBypass 10 9857 #define rx_x4_status3_operationModes_PBypass_nDSK 11 9858 #define rx_x4_status3_operationModes_ComboCoreMode 12 9859 #define rx_x4_status3_operationModes_Clocks_off 15 9860 9861 /**************************************************************************** 9862 * Enums: rx_x4_status3_actualSpeeds 9863 */ 9864 #define rx_x4_status3_actualSpeeds_dr_10M 0 9865 #define rx_x4_status3_actualSpeeds_dr_100M 1 9866 #define rx_x4_status3_actualSpeeds_dr_1G 2 9867 #define rx_x4_status3_actualSpeeds_dr_2p5G 3 9868 #define rx_x4_status3_actualSpeeds_dr_5G_X4 4 9869 #define rx_x4_status3_actualSpeeds_dr_6G_X4 5 9870 #define rx_x4_status3_actualSpeeds_dr_10G_HiG 6 9871 #define rx_x4_status3_actualSpeeds_dr_10G_CX4 7 9872 #define rx_x4_status3_actualSpeeds_dr_12G_HiG 8 9873 #define rx_x4_status3_actualSpeeds_dr_12p5G_X4 9 9874 #define rx_x4_status3_actualSpeeds_dr_13G_X4 10 9875 #define rx_x4_status3_actualSpeeds_dr_15G_X4 11 9876 #define rx_x4_status3_actualSpeeds_dr_16G_X4 12 9877 #define rx_x4_status3_actualSpeeds_dr_1G_KX 13 9878 #define rx_x4_status3_actualSpeeds_dr_10G_KX4 14 9879 #define rx_x4_status3_actualSpeeds_dr_10G_KR 15 9880 #define rx_x4_status3_actualSpeeds_dr_5G 16 9881 #define rx_x4_status3_actualSpeeds_dr_6p4G 17 9882 #define rx_x4_status3_actualSpeeds_dr_20G_X4 18 9883 #define rx_x4_status3_actualSpeeds_dr_21G_X4 19 9884 #define rx_x4_status3_actualSpeeds_dr_25G_X4 20 9885 #define rx_x4_status3_actualSpeeds_dr_10G_HiG_DXGXS 21 9886 #define rx_x4_status3_actualSpeeds_dr_10G_DXGXS 22 9887 #define rx_x4_status3_actualSpeeds_dr_10p5G_HiG_DXGXS 23 9888 #define rx_x4_status3_actualSpeeds_dr_10p5G_DXGXS 24 9889 #define rx_x4_status3_actualSpeeds_dr_12p773G_HiG_DXGXS 25 9890 #define rx_x4_status3_actualSpeeds_dr_12p773G_DXGXS 26 9891 #define rx_x4_status3_actualSpeeds_dr_10G_XFI 27 9892 #define rx_x4_status3_actualSpeeds_dr_40G 28 9893 #define rx_x4_status3_actualSpeeds_dr_20G_HiG_DXGXS 29 9894 #define rx_x4_status3_actualSpeeds_dr_20G_DXGXS 30 9895 #define rx_x4_status3_actualSpeeds_dr_10G_SFI 31 9896 #define rx_x4_status3_actualSpeeds_dr_31p5G 32 9897 #define rx_x4_status3_actualSpeeds_dr_32p7G 33 9898 #define rx_x4_status3_actualSpeeds_dr_20G_SCR 34 9899 #define rx_x4_status3_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 9900 #define rx_x4_status3_actualSpeeds_dr_10G_DXGXS_SCR 36 9901 #define rx_x4_status3_actualSpeeds_dr_12G_R2 37 9902 #define rx_x4_status3_actualSpeeds_dr_10G_X2 38 9903 #define rx_x4_status3_actualSpeeds_dr_40G_KR4 39 9904 #define rx_x4_status3_actualSpeeds_dr_40G_CR4 40 9905 #define rx_x4_status3_actualSpeeds_dr_100G_CR10 41 9906 #define rx_x4_status3_actualSpeeds_dr_15p75G_DXGXS 44 9907 #define rx_x4_status3_actualSpeeds_dr_20G_KR2 57 9908 #define rx_x4_status3_actualSpeeds_dr_20G_CR2 58 9909 9910 /**************************************************************************** 9911 * Enums: rx_x4_status3_actualSpeedsMisc1 9912 */ 9913 #define rx_x4_status3_actualSpeedsMisc1_dr_2500BRCM_X1 16 9914 #define rx_x4_status3_actualSpeedsMisc1_dr_5000BRCM_X4 17 9915 #define rx_x4_status3_actualSpeedsMisc1_dr_6000BRCM_X4 18 9916 #define rx_x4_status3_actualSpeedsMisc1_dr_10GHiGig_X4 19 9917 #define rx_x4_status3_actualSpeedsMisc1_dr_10GBASE_CX4 20 9918 #define rx_x4_status3_actualSpeedsMisc1_dr_12GHiGig_X4 21 9919 #define rx_x4_status3_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 9920 #define rx_x4_status3_actualSpeedsMisc1_dr_13GHiGig_X4 23 9921 #define rx_x4_status3_actualSpeedsMisc1_dr_15GHiGig_X4 24 9922 #define rx_x4_status3_actualSpeedsMisc1_dr_16GHiGig_X4 25 9923 #define rx_x4_status3_actualSpeedsMisc1_dr_5000BRCM_X1 26 9924 #define rx_x4_status3_actualSpeedsMisc1_dr_6363BRCM_X1 27 9925 #define rx_x4_status3_actualSpeedsMisc1_dr_20GHiGig_X4 28 9926 #define rx_x4_status3_actualSpeedsMisc1_dr_21GHiGig_X4 29 9927 #define rx_x4_status3_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 9928 #define rx_x4_status3_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 9929 9930 /**************************************************************************** 9931 * Enums: rx_x4_status3_IndLaneModes 9932 */ 9933 #define rx_x4_status3_IndLaneModes_SWSDR_div2 0 9934 #define rx_x4_status3_IndLaneModes_SWSDR_div1 1 9935 #define rx_x4_status3_IndLaneModes_DWSDR_div2 2 9936 #define rx_x4_status3_IndLaneModes_DWSDR_div1 3 9937 9938 /**************************************************************************** 9939 * Enums: rx_x4_status3_prbsSelect 9940 */ 9941 #define rx_x4_status3_prbsSelect_prbs7 0 9942 #define rx_x4_status3_prbsSelect_prbs15 1 9943 #define rx_x4_status3_prbsSelect_prbs23 2 9944 #define rx_x4_status3_prbsSelect_prbs31 3 9945 9946 /**************************************************************************** 9947 * Enums: rx_x4_status3_vcoDivider 9948 */ 9949 #define rx_x4_status3_vcoDivider_div32 0 9950 #define rx_x4_status3_vcoDivider_div36 1 9951 #define rx_x4_status3_vcoDivider_div40 2 9952 #define rx_x4_status3_vcoDivider_div42 3 9953 #define rx_x4_status3_vcoDivider_div48 4 9954 #define rx_x4_status3_vcoDivider_div50 5 9955 #define rx_x4_status3_vcoDivider_div52 6 9956 #define rx_x4_status3_vcoDivider_div54 7 9957 #define rx_x4_status3_vcoDivider_div60 8 9958 #define rx_x4_status3_vcoDivider_div64 9 9959 #define rx_x4_status3_vcoDivider_div66 10 9960 #define rx_x4_status3_vcoDivider_div68 11 9961 #define rx_x4_status3_vcoDivider_div70 12 9962 #define rx_x4_status3_vcoDivider_div80 13 9963 #define rx_x4_status3_vcoDivider_div92 14 9964 #define rx_x4_status3_vcoDivider_div100 15 9965 9966 /**************************************************************************** 9967 * Enums: rx_x4_status3_refClkSelect 9968 */ 9969 #define rx_x4_status3_refClkSelect_clk_156p25MHz 1 9970 #define rx_x4_status3_refClkSelect_clk_312p5Mhz 2 9971 9972 /**************************************************************************** 9973 * Enums: rx_x4_status3_aerMMDdevTypeSelect 9974 */ 9975 #define rx_x4_status3_aerMMDdevTypeSelect_combo_core 0 9976 #define rx_x4_status3_aerMMDdevTypeSelect_PMA_PMD 1 9977 #define rx_x4_status3_aerMMDdevTypeSelect_PCS 3 9978 #define rx_x4_status3_aerMMDdevTypeSelect_PHY 4 9979 #define rx_x4_status3_aerMMDdevTypeSelect_DTE 5 9980 #define rx_x4_status3_aerMMDdevTypeSelect_CL73_AN 7 9981 9982 /**************************************************************************** 9983 * Enums: rx_x4_status3_aerMMDportSelect 9984 */ 9985 #define rx_x4_status3_aerMMDportSelect_ln0 0 9986 #define rx_x4_status3_aerMMDportSelect_ln1 1 9987 #define rx_x4_status3_aerMMDportSelect_ln2 2 9988 #define rx_x4_status3_aerMMDportSelect_ln3 3 9989 #define rx_x4_status3_aerMMDportSelect_BCST_ln0_1_2_3 511 9990 #define rx_x4_status3_aerMMDportSelect_BCST_ln0_1 512 9991 #define rx_x4_status3_aerMMDportSelect_BCST_ln2_3 513 9992 9993 /**************************************************************************** 9994 * Enums: rx_x4_status3_firmwareModeSelect 9995 */ 9996 #define rx_x4_status3_firmwareModeSelect_DEFAULT 0 9997 #define rx_x4_status3_firmwareModeSelect_SFP_OPT_LR 1 9998 #define rx_x4_status3_firmwareModeSelect_SFP_DAC 2 9999 #define rx_x4_status3_firmwareModeSelect_XLAUI 3 10000 #define rx_x4_status3_firmwareModeSelect_LONG_CH_6G 4 10001 10002 /**************************************************************************** 10003 * Enums: rx_x4_status3_tempIdxSelect 10004 */ 10005 #define rx_x4_status3_tempIdxSelect_LTE__22p9C 15 10006 #define rx_x4_status3_tempIdxSelect_LTE__12p6C 14 10007 #define rx_x4_status3_tempIdxSelect_LTE__3p0C 13 10008 #define rx_x4_status3_tempIdxSelect_LTE_6p7C 12 10009 #define rx_x4_status3_tempIdxSelect_LTE_16p4C 11 10010 #define rx_x4_status3_tempIdxSelect_LTE_26p6C 10 10011 #define rx_x4_status3_tempIdxSelect_LTE_36p3C 9 10012 #define rx_x4_status3_tempIdxSelect_LTE_46p0C 8 10013 #define rx_x4_status3_tempIdxSelect_LTE_56p2C 7 10014 #define rx_x4_status3_tempIdxSelect_LTE_65p9C 6 10015 #define rx_x4_status3_tempIdxSelect_LTE_75p6C 5 10016 #define rx_x4_status3_tempIdxSelect_LTE_85p3C 4 10017 #define rx_x4_status3_tempIdxSelect_LTE_95p5C 3 10018 #define rx_x4_status3_tempIdxSelect_LTE_105p2C 2 10019 #define rx_x4_status3_tempIdxSelect_LTE_114p9C 1 10020 #define rx_x4_status3_tempIdxSelect_LTE_125p1C 0 10021 10022 /**************************************************************************** 10023 * Enums: rx_x4_status3_port_mode 10024 */ 10025 #define rx_x4_status3_port_mode_QUAD_PORT 0 10026 #define rx_x4_status3_port_mode_TRI_1_PORT 1 10027 #define rx_x4_status3_port_mode_TRI_2_PORT 2 10028 #define rx_x4_status3_port_mode_DUAL_PORT 3 10029 #define rx_x4_status3_port_mode_SINGLE_PORT 4 10030 #define rx_x4_status3_port_mode_SINGLE_OCTAL_PORT 5 10031 10032 /**************************************************************************** 10033 * Enums: rx_x4_status3_rev_letter_enum 10034 */ 10035 #define rx_x4_status3_rev_letter_enum_REV_A 0 10036 #define rx_x4_status3_rev_letter_enum_REV_B 1 10037 #define rx_x4_status3_rev_letter_enum_REV_C 2 10038 #define rx_x4_status3_rev_letter_enum_REV_D 3 10039 10040 /**************************************************************************** 10041 * Enums: rx_x4_status3_rev_number_enum 10042 */ 10043 #define rx_x4_status3_rev_number_enum_REV_0 0 10044 #define rx_x4_status3_rev_number_enum_REV_1 1 10045 #define rx_x4_status3_rev_number_enum_REV_2 2 10046 #define rx_x4_status3_rev_number_enum_REV_3 3 10047 #define rx_x4_status3_rev_number_enum_REV_4 4 10048 #define rx_x4_status3_rev_number_enum_REV_5 5 10049 #define rx_x4_status3_rev_number_enum_REV_6 6 10050 #define rx_x4_status3_rev_number_enum_REV_7 7 10051 10052 /**************************************************************************** 10053 * Enums: rx_x4_status3_bonding_enum 10054 */ 10055 #define rx_x4_status3_bonding_enum_WIRE_BOND 0 10056 #define rx_x4_status3_bonding_enum_FLIP_CHIP 1 10057 10058 /**************************************************************************** 10059 * Enums: rx_x4_status3_tech_process 10060 */ 10061 #define rx_x4_status3_tech_process_PROCESS_90NM 0 10062 #define rx_x4_status3_tech_process_PROCESS_65NM 1 10063 #define rx_x4_status3_tech_process_PROCESS_40NM 2 10064 #define rx_x4_status3_tech_process_PROCESS_28NM 3 10065 #define rx_x4_status3_tech_process_PROCESS_16NM 4 10066 10067 /**************************************************************************** 10068 * Enums: rx_x4_status3_model_num 10069 */ 10070 #define rx_x4_status3_model_num_SERDES_CL73 0 10071 #define rx_x4_status3_model_num_XGXS_16G 1 10072 #define rx_x4_status3_model_num_HYPERCORE 2 10073 #define rx_x4_status3_model_num_HYPERLITE 3 10074 #define rx_x4_status3_model_num_PCIE_G2_PIPE 4 10075 #define rx_x4_status3_model_num_SERDES_1p25GBd 5 10076 #define rx_x4_status3_model_num_SATA2 6 10077 #define rx_x4_status3_model_num_QSGMII 7 10078 #define rx_x4_status3_model_num_XGXS10G 8 10079 #define rx_x4_status3_model_num_WARPCORE 9 10080 #define rx_x4_status3_model_num_XFICORE 10 10081 #define rx_x4_status3_model_num_RXFI 11 10082 #define rx_x4_status3_model_num_WARPLITE 12 10083 #define rx_x4_status3_model_num_PENTACORE 13 10084 #define rx_x4_status3_model_num_ESM 14 10085 #define rx_x4_status3_model_num_QUAD_SGMII 15 10086 #define rx_x4_status3_model_num_WARPCORE_3 16 10087 #define rx_x4_status3_model_num_TSC 17 10088 #define rx_x4_status3_model_num_TSC4E 18 10089 #define rx_x4_status3_model_num_TSC12E 19 10090 #define rx_x4_status3_model_num_TSC4F 20 10091 #define rx_x4_status3_model_num_TSC4F_GEN2 21 10092 #define rx_x4_status3_model_num_XGXS_CL73_90NM 29 10093 #define rx_x4_status3_model_num_SERDES_CL73_90NM 30 10094 #define rx_x4_status3_model_num_WARPCORE3 32 10095 #define rx_x4_status3_model_num_WARPCORE4_TSC 33 10096 #define rx_x4_status3_model_num_RXAUI 34 10097 #define rx_x4_status3_model_num_TSCE_GEN3 35 10098 #define rx_x4_status3_model_num_TSC4F_GEN3 36 10099 #define rx_x4_status3_model_num_TSCBH 37 10100 10101 /**************************************************************************** 10102 * Enums: rx_x4_status3_payload 10103 */ 10104 #define rx_x4_status3_payload_REPEAT_2_BYTES 0 10105 #define rx_x4_status3_payload_RAMPING 1 10106 #define rx_x4_status3_payload_CL48_CRPAT 2 10107 #define rx_x4_status3_payload_CL48_CJPAT 3 10108 #define rx_x4_status3_payload_CL36_LONG_CRPAT 4 10109 #define rx_x4_status3_payload_CL36_SHORT_CRPAT 5 10110 10111 /**************************************************************************** 10112 * Enums: rx_x4_status3_sc 10113 */ 10114 #define rx_x4_status3_sc_SPEED_10G_IEEE_KR1 0 10115 #define rx_x4_status3_sc_SPEED_25G_IEEE_KS1_CS1 1 10116 #define rx_x4_status3_sc_SPEED_25G_IEEE_KR1_CR1 2 10117 #define rx_x4_status3_sc_SPEED_40G_IEEE_KR4 3 10118 #define rx_x4_status3_sc_SPEED_40G_IEEE_CR4 4 10119 #define rx_x4_status3_sc_SPEED_50G_IEEE_KR1_CR1 5 10120 #define rx_x4_status3_sc_SPEED_100G_IEEE_KR4 6 10121 #define rx_x4_status3_sc_SPEED_100G_IEEE_CR4 7 10122 #define rx_x4_status3_sc_SPEED_100G_IEEE_KR2_CR2 8 10123 #define rx_x4_status3_sc_SPEED_200G_IEEE_KR4_CR4 9 10124 #define rx_x4_status3_sc_SPEED_400G_IEEE_X8 10 10125 #define rx_x4_status3_sc_SPEED_CL73_IEEE_20GVCO 11 10126 #define rx_x4_status3_sc_SPEED_CL73_IEEE_25GVCO 12 10127 #define rx_x4_status3_sc_SPEED_CL73_IEEE_26GVCO 13 10128 #define rx_x4_status3_sc_SPEED_20G_BRCM_CR1 14 10129 #define rx_x4_status3_sc_SPEED_20G_BRCM_KR1 15 10130 #define rx_x4_status3_sc_SPEED_25G_BRCM_CR1 16 10131 #define rx_x4_status3_sc_SPEED_25G_BRCM_KR1 17 10132 #define rx_x4_status3_sc_SPEED_40G_BRCM_CR2 18 10133 #define rx_x4_status3_sc_SPEED_40G_BRCM_KR2 19 10134 #define rx_x4_status3_sc_SPEED_50G_BRCM_CR2 20 10135 #define rx_x4_status3_sc_SPEED_50G_BRCM_KR2 21 10136 #define rx_x4_status3_sc_SPEED_50G_BRCM_CR4 22 10137 #define rx_x4_status3_sc_SPEED_50G_BRCM_KR4 23 10138 #define rx_x4_status3_sc_SPEED_50G_BRCM_FEC_544_CR2_KR2 24 10139 #define rx_x4_status3_sc_SPEED_RESERVED_19 25 10140 #define rx_x4_status3_sc_SPEED_50G_BRCM_FEC_544_CR1_KR1 26 10141 #define rx_x4_status3_sc_SPEED_50G_BRCM_NO_FEC_CR1_KR1 27 10142 #define rx_x4_status3_sc_SPEED_50G_BRCM_FEC_528_CR1_KR1 28 10143 #define rx_x4_status3_sc_SPEED_400G_BRCM_NO_FEC_KR8_CR8 29 10144 #define rx_x4_status3_sc_SPEED_400G_BRCM_FEC_KR8_CR8 30 10145 #define rx_x4_status3_sc_SPEED_200G_BRCM_NO_FEC_KR4_CR4 31 10146 #define rx_x4_status3_sc_SPEED_200G_BRCM_KR4_CR4 32 10147 #define rx_x4_status3_sc_SPEED_100G_BRCM_KR4_CR4 33 10148 #define rx_x4_status3_sc_SPEED_RESERVED_22 34 10149 #define rx_x4_status3_sc_SPEED_100G_BRCM_FEC_528_KR2_CR2 35 10150 #define rx_x4_status3_sc_SPEED_100G_BRCM_NO_FEC_KR2_CR2 36 10151 #define rx_x4_status3_sc_SPEED_100G_BRCM_NO_FEC_X4 37 10152 10153 /**************************************************************************** 10154 * Enums: rx_x4_status3_t_fifo_modes 10155 */ 10156 #define rx_x4_status3_t_fifo_modes_T_FIFO_INSERT_NO_AM 0 10157 #define rx_x4_status3_t_fifo_modes_T_FIFO_INSERT_4_AM 1 10158 #define rx_x4_status3_t_fifo_modes_T_FIFO_INSERT_20_AM 2 10159 #define rx_x4_status3_t_fifo_modes_T_FIFO_INSERT_2_AM 3 10160 10161 /**************************************************************************** 10162 * Enums: rx_x4_status3_t_enc_modes 10163 */ 10164 #define rx_x4_status3_t_enc_modes_T_ENC_MODE_BYPASS 0 10165 #define rx_x4_status3_t_enc_modes_T_ENC_MODE_CL49 1 10166 #define rx_x4_status3_t_enc_modes_T_ENC_MODE_CL82 2 10167 10168 /**************************************************************************** 10169 * Enums: rx_x4_status3_btmx_mode 10170 */ 10171 #define rx_x4_status3_btmx_mode_BS_BTMX_MODE_1to1 0 10172 #define rx_x4_status3_btmx_mode_BS_BTMX_MODE_2to1 1 10173 #define rx_x4_status3_btmx_mode_BS_BTMX_MODE_5to1 2 10174 10175 /**************************************************************************** 10176 * Enums: rx_x4_status3_t_type_cl82 10177 */ 10178 #define rx_x4_status3_t_type_cl82_T_TYPE_B1 5 10179 #define rx_x4_status3_t_type_cl82_T_TYPE_C 4 10180 #define rx_x4_status3_t_type_cl82_T_TYPE_S 3 10181 #define rx_x4_status3_t_type_cl82_T_TYPE_T 2 10182 #define rx_x4_status3_t_type_cl82_T_TYPE_D 1 10183 #define rx_x4_status3_t_type_cl82_T_TYPE_E 0 10184 10185 /**************************************************************************** 10186 * Enums: rx_x4_status3_txsm_state_cl82 10187 */ 10188 #define rx_x4_status3_txsm_state_cl82_TX_E 4 10189 #define rx_x4_status3_txsm_state_cl82_TX_T 3 10190 #define rx_x4_status3_txsm_state_cl82_TX_D 2 10191 #define rx_x4_status3_txsm_state_cl82_TX_C 1 10192 #define rx_x4_status3_txsm_state_cl82_TX_INIT 0 10193 10194 /**************************************************************************** 10195 * Enums: rx_x4_status3_ltxsm_state_cl82 10196 */ 10197 #define rx_x4_status3_ltxsm_state_cl82_TX_E 16 10198 #define rx_x4_status3_ltxsm_state_cl82_TX_T 8 10199 #define rx_x4_status3_ltxsm_state_cl82_TX_D 4 10200 #define rx_x4_status3_ltxsm_state_cl82_TX_C 2 10201 #define rx_x4_status3_ltxsm_state_cl82_TX_INIT 1 10202 10203 /**************************************************************************** 10204 * Enums: rx_x4_status3_r_type_coded_cl82 10205 */ 10206 #define rx_x4_status3_r_type_coded_cl82_R_TYPE_B1 32 10207 #define rx_x4_status3_r_type_coded_cl82_R_TYPE_C 16 10208 #define rx_x4_status3_r_type_coded_cl82_R_TYPE_S 8 10209 #define rx_x4_status3_r_type_coded_cl82_R_TYPE_T 4 10210 #define rx_x4_status3_r_type_coded_cl82_R_TYPE_D 2 10211 #define rx_x4_status3_r_type_coded_cl82_R_TYPE_E 1 10212 10213 /**************************************************************************** 10214 * Enums: rx_x4_status3_rxsm_state_cl82 10215 */ 10216 #define rx_x4_status3_rxsm_state_cl82_RX_E 16 10217 #define rx_x4_status3_rxsm_state_cl82_RX_T 8 10218 #define rx_x4_status3_rxsm_state_cl82_RX_D 4 10219 #define rx_x4_status3_rxsm_state_cl82_RX_C 2 10220 #define rx_x4_status3_rxsm_state_cl82_RX_INIT 1 10221 10222 /**************************************************************************** 10223 * Enums: rx_x4_status3_deskew_state 10224 */ 10225 #define rx_x4_status3_deskew_state_ALIGN_ACQUIRED 2 10226 #define rx_x4_status3_deskew_state_LOSS_OF_ALIGNMENT 1 10227 10228 /**************************************************************************** 10229 * Enums: rx_x4_status3_os_mode_enum 10230 */ 10231 #define rx_x4_status3_os_mode_enum_OS_MODE_1 0 10232 #define rx_x4_status3_os_mode_enum_OS_MODE_2 1 10233 #define rx_x4_status3_os_mode_enum_OS_MODE_4 2 10234 #define rx_x4_status3_os_mode_enum_OS_MODE_16p5 8 10235 #define rx_x4_status3_os_mode_enum_OS_MODE_20p625 12 10236 10237 /**************************************************************************** 10238 * Enums: rx_x4_status3_scr_modes 10239 */ 10240 #define rx_x4_status3_scr_modes_T_SCR_MODE_BYPASS 0 10241 #define rx_x4_status3_scr_modes_T_SCR_MODE_CL49 1 10242 #define rx_x4_status3_scr_modes_T_SCR_MODE_40G_2_LANE 2 10243 #define rx_x4_status3_scr_modes_T_SCR_MODE_100G 3 10244 #define rx_x4_status3_scr_modes_T_SCR_MODE_20G 4 10245 #define rx_x4_status3_scr_modes_T_SCR_MODE_40G_4_LANE 5 10246 10247 /**************************************************************************** 10248 * Enums: rx_x4_status3_descr_modes 10249 */ 10250 #define rx_x4_status3_descr_modes_R_DESCR_MODE_BYPASS 0 10251 #define rx_x4_status3_descr_modes_R_DESCR_MODE_CL49 1 10252 #define rx_x4_status3_descr_modes_R_DESCR_MODE_CL82 2 10253 10254 /**************************************************************************** 10255 * Enums: rx_x4_status3_r_dec_tl_mode 10256 */ 10257 #define rx_x4_status3_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 10258 #define rx_x4_status3_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 10259 #define rx_x4_status3_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 10260 10261 /**************************************************************************** 10262 * Enums: rx_x4_status3_r_dec_fsm_mode 10263 */ 10264 #define rx_x4_status3_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 10265 #define rx_x4_status3_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 10266 #define rx_x4_status3_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 10267 10268 /**************************************************************************** 10269 * Enums: rx_x4_status3_r_deskew_mode 10270 */ 10271 #define rx_x4_status3_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 10272 #define rx_x4_status3_r_deskew_mode_R_DESKEW_MODE_20G 1 10273 #define rx_x4_status3_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 10274 #define rx_x4_status3_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 10275 #define rx_x4_status3_r_deskew_mode_R_DESKEW_MODE_100G 4 10276 #define rx_x4_status3_r_deskew_mode_R_DESKEW_MODE_CL49 5 10277 #define rx_x4_status3_r_deskew_mode_R_DESKEW_MODE_CL91_QUAD 6 10278 #define rx_x4_status3_r_deskew_mode_R_DESKEW_MODE_CL91_SINGLE_BRCM 7 10279 #define rx_x4_status3_r_deskew_mode_R_DESKEW_MODE_CL91_DUAL_BRCM 8 10280 #define rx_x4_status3_r_deskew_mode_R_DESKEW_MODE_CL91_FC 9 10281 10282 /**************************************************************************** 10283 * Enums: rx_x4_status3_bs_dist_modes 10284 */ 10285 #define rx_x4_status3_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 10286 #define rx_x4_status3_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 10287 #define rx_x4_status3_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 10288 #define rx_x4_status3_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 10289 10290 /**************************************************************************** 10291 * Enums: rx_x4_status3_cl49_t_type 10292 */ 10293 #define rx_x4_status3_cl49_t_type_BAD_T_TYPE 15 10294 #define rx_x4_status3_cl49_t_type_T_TYPE_B0 11 10295 #define rx_x4_status3_cl49_t_type_T_TYPE_OB 10 10296 #define rx_x4_status3_cl49_t_type_T_TYPE_B1 9 10297 #define rx_x4_status3_cl49_t_type_T_TYPE_DB 8 10298 #define rx_x4_status3_cl49_t_type_T_TYPE_FC 7 10299 #define rx_x4_status3_cl49_t_type_T_TYPE_TB 6 10300 #define rx_x4_status3_cl49_t_type_T_TYPE_LI 5 10301 #define rx_x4_status3_cl49_t_type_T_TYPE_C 4 10302 #define rx_x4_status3_cl49_t_type_T_TYPE_S 3 10303 #define rx_x4_status3_cl49_t_type_T_TYPE_T 2 10304 #define rx_x4_status3_cl49_t_type_T_TYPE_D 1 10305 #define rx_x4_status3_cl49_t_type_T_TYPE_E 0 10306 10307 /**************************************************************************** 10308 * Enums: rx_x4_status3_cl49_txsm_states 10309 */ 10310 #define rx_x4_status3_cl49_txsm_states_TX_LI 5 10311 #define rx_x4_status3_cl49_txsm_states_TX_E 4 10312 #define rx_x4_status3_cl49_txsm_states_TX_T 3 10313 #define rx_x4_status3_cl49_txsm_states_TX_D 2 10314 #define rx_x4_status3_cl49_txsm_states_TX_C 1 10315 #define rx_x4_status3_cl49_txsm_states_TX_INIT 0 10316 10317 /**************************************************************************** 10318 * Enums: rx_x4_status3_cl49_ltxsm_states 10319 */ 10320 #define rx_x4_status3_cl49_ltxsm_states_TX_LI 32 10321 #define rx_x4_status3_cl49_ltxsm_states_TX_E 16 10322 #define rx_x4_status3_cl49_ltxsm_states_TX_T 8 10323 #define rx_x4_status3_cl49_ltxsm_states_TX_D 4 10324 #define rx_x4_status3_cl49_ltxsm_states_TX_C 2 10325 #define rx_x4_status3_cl49_ltxsm_states_TX_INIT 1 10326 10327 /**************************************************************************** 10328 * Enums: rx_x4_status3_burst_error_mode 10329 */ 10330 #define rx_x4_status3_burst_error_mode_BURST_ERROR_11_BITS 0 10331 #define rx_x4_status3_burst_error_mode_BURST_ERROR_16_BITS 1 10332 #define rx_x4_status3_burst_error_mode_BURST_ERROR_17_BITS 2 10333 #define rx_x4_status3_burst_error_mode_BURST_ERROR_18_BITS 3 10334 #define rx_x4_status3_burst_error_mode_BURST_ERROR_19_BITS 4 10335 #define rx_x4_status3_burst_error_mode_BURST_ERROR_20_BITS 5 10336 #define rx_x4_status3_burst_error_mode_BURST_ERROR_21_BITS 6 10337 #define rx_x4_status3_burst_error_mode_BURST_ERROR_22_BITS 7 10338 #define rx_x4_status3_burst_error_mode_BURST_ERROR_23_BITS 8 10339 #define rx_x4_status3_burst_error_mode_BURST_ERROR_24_BITS 9 10340 #define rx_x4_status3_burst_error_mode_BURST_ERROR_25_BITS 10 10341 #define rx_x4_status3_burst_error_mode_BURST_ERROR_26_BITS 11 10342 #define rx_x4_status3_burst_error_mode_BURST_ERROR_27_BITS 12 10343 #define rx_x4_status3_burst_error_mode_BURST_ERROR_28_BITS 13 10344 #define rx_x4_status3_burst_error_mode_BURST_ERROR_29_BITS 14 10345 #define rx_x4_status3_burst_error_mode_BURST_ERROR_30_BITS 15 10346 #define rx_x4_status3_burst_error_mode_BURST_ERROR_31_BITS 16 10347 #define rx_x4_status3_burst_error_mode_BURST_ERROR_32_BITS 17 10348 #define rx_x4_status3_burst_error_mode_BURST_ERROR_33_BITS 18 10349 #define rx_x4_status3_burst_error_mode_BURST_ERROR_34_BITS 19 10350 #define rx_x4_status3_burst_error_mode_BURST_ERROR_35_BITS 20 10351 #define rx_x4_status3_burst_error_mode_BURST_ERROR_36_BITS 21 10352 #define rx_x4_status3_burst_error_mode_BURST_ERROR_37_BITS 22 10353 #define rx_x4_status3_burst_error_mode_BURST_ERROR_38_BITS 23 10354 #define rx_x4_status3_burst_error_mode_BURST_ERROR_39_BITS 24 10355 #define rx_x4_status3_burst_error_mode_BURST_ERROR_40_BITS 25 10356 #define rx_x4_status3_burst_error_mode_BURST_ERROR_41_BITS 26 10357 10358 /**************************************************************************** 10359 * Enums: rx_x4_status3_bermon_state 10360 */ 10361 #define rx_x4_status3_bermon_state_HI_BER 4 10362 #define rx_x4_status3_bermon_state_GOOD_BER 3 10363 #define rx_x4_status3_bermon_state_BER_TEST_SH 2 10364 #define rx_x4_status3_bermon_state_START_TIMER 1 10365 #define rx_x4_status3_bermon_state_BER_MT_INIT 0 10366 10367 /**************************************************************************** 10368 * Enums: rx_x4_status3_rxsm_state_cl49 10369 */ 10370 #define rx_x4_status3_rxsm_state_cl49_RX_LI 32 10371 #define rx_x4_status3_rxsm_state_cl49_RX_E 16 10372 #define rx_x4_status3_rxsm_state_cl49_RX_T 8 10373 #define rx_x4_status3_rxsm_state_cl49_RX_D 4 10374 #define rx_x4_status3_rxsm_state_cl49_RX_C 2 10375 #define rx_x4_status3_rxsm_state_cl49_RX_INIT 1 10376 10377 /**************************************************************************** 10378 * Enums: rx_x4_status3_r_type 10379 */ 10380 #define rx_x4_status3_r_type_BAD_R_TYPE 15 10381 #define rx_x4_status3_r_type_R_TYPE_B0 11 10382 #define rx_x4_status3_r_type_R_TYPE_OB 10 10383 #define rx_x4_status3_r_type_R_TYPE_B1 9 10384 #define rx_x4_status3_r_type_R_TYPE_DB 8 10385 #define rx_x4_status3_r_type_R_TYPE_FC 7 10386 #define rx_x4_status3_r_type_R_TYPE_TB 6 10387 #define rx_x4_status3_r_type_R_TYPE_LI 5 10388 #define rx_x4_status3_r_type_R_TYPE_C 4 10389 #define rx_x4_status3_r_type_R_TYPE_S 3 10390 #define rx_x4_status3_r_type_R_TYPE_T 2 10391 #define rx_x4_status3_r_type_R_TYPE_D 1 10392 #define rx_x4_status3_r_type_R_TYPE_E 0 10393 10394 /**************************************************************************** 10395 * Enums: rx_x4_status3_am_lock_state 10396 */ 10397 #define rx_x4_status3_am_lock_state_INVALID_AM 512 10398 #define rx_x4_status3_am_lock_state_GOOD_AM 256 10399 #define rx_x4_status3_am_lock_state_COMP_AM 128 10400 #define rx_x4_status3_am_lock_state_TIMER_2 64 10401 #define rx_x4_status3_am_lock_state_AM_2_GOOD 32 10402 #define rx_x4_status3_am_lock_state_COMP_2ND 16 10403 #define rx_x4_status3_am_lock_state_TIMER_1 8 10404 #define rx_x4_status3_am_lock_state_FIND_1ST 4 10405 #define rx_x4_status3_am_lock_state_AM_RESET_CNT 2 10406 #define rx_x4_status3_am_lock_state_AM_LOCK_INIT 1 10407 10408 /**************************************************************************** 10409 * Enums: rx_x4_status3_msg_selector 10410 */ 10411 #define rx_x4_status3_msg_selector_RESERVED 0 10412 #define rx_x4_status3_msg_selector_VALUE_802p3 1 10413 #define rx_x4_status3_msg_selector_VALUE_802p9 2 10414 #define rx_x4_status3_msg_selector_VALUE_802p5 3 10415 #define rx_x4_status3_msg_selector_VALUE_1394 4 10416 10417 /**************************************************************************** 10418 * Enums: rx_x4_status3_synce_enum_stage1 10419 */ 10420 #define rx_x4_status3_synce_enum_stage1_SYNCE_NO_DIV 0 10421 #define rx_x4_status3_synce_enum_stage1_SYNCE_DIV_7 1 10422 #define rx_x4_status3_synce_enum_stage1_SYNCE_DIV_11 2 10423 10424 /**************************************************************************** 10425 * Enums: rx_x4_status3_synce_enum_stage0 10426 */ 10427 #define rx_x4_status3_synce_enum_stage0_SYNCE_NO_DIV 0 10428 #define rx_x4_status3_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 10429 #define rx_x4_status3_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 10430 10431 /**************************************************************************** 10432 * Enums: rx_x4_status3_cl91_sync_state 10433 */ 10434 #define rx_x4_status3_cl91_sync_state_FIND_1ST 0 10435 #define rx_x4_status3_cl91_sync_state_COUNT_NEXT 1 10436 #define rx_x4_status3_cl91_sync_state_COMP_2ND 2 10437 #define rx_x4_status3_cl91_sync_state_TWO_GOOD 3 10438 10439 /**************************************************************************** 10440 * Enums: rx_x4_status3_RS_FEC_sync_state 10441 */ 10442 #define rx_x4_status3_RS_FEC_sync_state_LOCK_INIT 0 10443 #define rx_x4_status3_RS_FEC_sync_state_FIND_1ST 1 10444 #define rx_x4_status3_RS_FEC_sync_state_COUNT_NEXT 2 10445 #define rx_x4_status3_RS_FEC_sync_state_COMP_2ND 3 10446 #define rx_x4_status3_RS_FEC_sync_state_TWO_GOOD 4 10447 10448 /**************************************************************************** 10449 * Enums: rx_x4_status3_cl91_algn_state 10450 */ 10451 #define rx_x4_status3_cl91_algn_state_LOSS_OF_ALIGNMENT 0 10452 #define rx_x4_status3_cl91_algn_state_DESKEW 1 10453 #define rx_x4_status3_cl91_algn_state_DESKEW_FAIL 2 10454 #define rx_x4_status3_cl91_algn_state_ALIGN_ACQUIRED 3 10455 #define rx_x4_status3_cl91_algn_state_CW_GOOD 4 10456 #define rx_x4_status3_cl91_algn_state_CW_BAD 5 10457 #define rx_x4_status3_cl91_algn_state_THREE_BAD 6 10458 10459 /**************************************************************************** 10460 * Enums: rx_x4_status3_RS_FEC_algn_state 10461 */ 10462 #define rx_x4_status3_RS_FEC_algn_state_LOSS_OF_ALIGNMENT 0 10463 #define rx_x4_status3_RS_FEC_algn_state_DESKEW 1 10464 #define rx_x4_status3_RS_FEC_algn_state_DESKEW_FAIL 2 10465 #define rx_x4_status3_RS_FEC_algn_state_ALIGN_ACQUIRED 3 10466 #define rx_x4_status3_RS_FEC_algn_state_CW_GOOD 4 10467 #define rx_x4_status3_RS_FEC_algn_state_CW_BAD 5 10468 #define rx_x4_status3_RS_FEC_algn_state_THREE_BAD 6 10469 10470 /**************************************************************************** 10471 * Enums: rx_x4_status3_fec_sel_override 10472 */ 10473 #define rx_x4_status3_fec_sel_override_NO_OVERRIDE 0 10474 #define rx_x4_status3_fec_sel_override_NO_FEC 1 10475 #define rx_x4_status3_fec_sel_override_FEC_CL74 2 10476 #define rx_x4_status3_fec_sel_override_FEC_CL91 3 10477 10478 /**************************************************************************** 10479 * Enums: rx_x4_status3_cl91_blksync_mode 10480 */ 10481 #define rx_x4_status3_cl91_blksync_mode_R_BLKSYNC_NO_CL91_FEC 0 10482 #define rx_x4_status3_cl91_blksync_mode_R_BLKSYNC_CL91_QUAD_LANE_FEC 1 10483 #define rx_x4_status3_cl91_blksync_mode_R_BLKSYNC_CL91_DUAL_LANE_FEC 2 10484 #define rx_x4_status3_cl91_blksync_mode_R_BLKSYNC_CL91_SINGLE_LANE_FEC 3 10485 #define rx_x4_status3_cl91_blksync_mode_R_BLKSYNC_CL91_FC_FEC 4 10486 10487 /**************************************************************************** 10488 * Enums: rx_x4_status3_r_merge_mode 10489 */ 10490 #define rx_x4_status3_r_merge_mode_R_MERGE_MODE_BYPASS 0 10491 #define rx_x4_status3_r_merge_mode_R_MERGE_MODE_CL91_FC 1 10492 #define rx_x4_status3_r_merge_mode_R_MERGE_MODE_CL91_SINGLE_LANE 2 10493 #define rx_x4_status3_r_merge_mode_R_MERGE_MODE_CL91_DUAL_LANE 3 10494 #define rx_x4_status3_r_merge_mode_R_MERGE_MODE_CL91_QUAD_LANE 4 10495 10496 /**************************************************************************** 10497 * Enums: rx_x4_status3_r_tc_mode 10498 */ 10499 #define rx_x4_status3_r_tc_mode_R_TC_MODE_SINGLE 0 10500 #define rx_x4_status3_r_tc_mode_R_TC_MODE_DUAL 1 10501 #define rx_x4_status3_r_tc_mode_R_TC_MODE_QUAD 2 10502 10503 /**************************************************************************** 10504 * Enums: rx_x4_status3_r_tc_out_mode 10505 */ 10506 #define rx_x4_status3_r_tc_out_mode_R_TC_OUT_MODE_SINGLE 0 10507 #define rx_x4_status3_r_tc_out_mode_R_TC_OUT_MODE_DUAL 1 10508 #define rx_x4_status3_r_tc_out_mode_R_TC_OUT_MODE_QUAD 2 10509 10510 /**************************************************************************** 10511 * Enums: rx_x4_status3_cl91_fec_mode 10512 */ 10513 #define rx_x4_status3_cl91_fec_mode_NO_CL91_FEC 0 10514 #define rx_x4_status3_cl91_fec_mode_CL91_SINGLE_LANE_FC 1 10515 #define rx_x4_status3_cl91_fec_mode_CL91_SINGLE_LANE_BRCM_PROP 2 10516 #define rx_x4_status3_cl91_fec_mode_CL91_DUAL_LANE_BRCM_PROP 3 10517 #define rx_x4_status3_cl91_fec_mode_CL91_QUAD_LANE 4 10518 #define rx_x4_status3_cl91_fec_mode_IEEE_25G_CL91_SINGLE_LANE 5 10519 10520 /**************************************************************************** 10521 * Enums: rx_x4_status3_RS_FEC_fec_mode 10522 */ 10523 #define rx_x4_status3_RS_FEC_fec_mode_NO_RS_FEC_FEC 0 10524 #define rx_x4_status3_RS_FEC_fec_mode_N_A 1 10525 #define rx_x4_status3_RS_FEC_fec_mode_RS_FEC_SINGLE_LANE_BRCM_PROP 2 10526 #define rx_x4_status3_RS_FEC_fec_mode_RS_FEC_DUAL_LANE_BRCM_PROP 3 10527 #define rx_x4_status3_RS_FEC_fec_mode_RS_FEC_QUAD_LANE 4 10528 #define rx_x4_status3_RS_FEC_fec_mode_IEEE_25G_RS_FEC_SINGLE_LANE 5 10529 10530 /**************************************************************************** 10531 * Enums: rx_x4_status3_am_spacing_mul 10532 */ 10533 #define rx_x4_status3_am_spacing_mul_AM_SPACING_MUL_2 0 10534 #define rx_x4_status3_am_spacing_mul_AM_SPACING_MUL_4 1 10535 #define rx_x4_status3_am_spacing_mul_AM_SPACING_MUL_5 2 10536 #define rx_x4_status3_am_spacing_mul_AM_SPACING_MUL_20 3 10537 10538 /**************************************************************************** 10539 * Enums: rx_x4_status4_cl36TxEEEStates_l 10540 */ 10541 #define rx_x4_status4_cl36TxEEEStates_l_TX_REFRESH 8 10542 #define rx_x4_status4_cl36TxEEEStates_l_TX_QUIET 4 10543 #define rx_x4_status4_cl36TxEEEStates_l_TX_SLEEP 2 10544 #define rx_x4_status4_cl36TxEEEStates_l_TX_ACTIVE 1 10545 10546 /**************************************************************************** 10547 * Enums: rx_x4_status4_cl36TxEEEStates_c 10548 */ 10549 #define rx_x4_status4_cl36TxEEEStates_c_TX_REFRESH 3 10550 #define rx_x4_status4_cl36TxEEEStates_c_TX_QUIET 2 10551 #define rx_x4_status4_cl36TxEEEStates_c_TX_SLEEP 1 10552 #define rx_x4_status4_cl36TxEEEStates_c_TX_ACTIVE 0 10553 10554 /**************************************************************************** 10555 * Enums: rx_x4_status4_cl49TxEEEStates_l 10556 */ 10557 #define rx_x4_status4_cl49TxEEEStates_l_SCR_RESET_2 64 10558 #define rx_x4_status4_cl49TxEEEStates_l_SCR_RESET_1 32 10559 #define rx_x4_status4_cl49TxEEEStates_l_TX_WAKE 16 10560 #define rx_x4_status4_cl49TxEEEStates_l_TX_REFRESH 8 10561 #define rx_x4_status4_cl49TxEEEStates_l_TX_QUIET 4 10562 #define rx_x4_status4_cl49TxEEEStates_l_TX_SLEEP 2 10563 #define rx_x4_status4_cl49TxEEEStates_l_TX_ACTIVE 1 10564 10565 /**************************************************************************** 10566 * Enums: rx_x4_status4_fec_req_enum 10567 */ 10568 #define rx_x4_status4_fec_req_enum_FEC_not_supported 0 10569 #define rx_x4_status4_fec_req_enum_FEC_supported_but_not_requested 1 10570 #define rx_x4_status4_fec_req_enum_invalid_setting 2 10571 #define rx_x4_status4_fec_req_enum_FEC_supported_and_requested 3 10572 10573 /**************************************************************************** 10574 * Enums: rx_x4_status4_cl73_pause_enum 10575 */ 10576 #define rx_x4_status4_cl73_pause_enum_No_PAUSE_ability 0 10577 #define rx_x4_status4_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 10578 #define rx_x4_status4_cl73_pause_enum_Symmetric_PAUSE_ability 1 10579 #define rx_x4_status4_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 10580 10581 /**************************************************************************** 10582 * Enums: rx_x4_status4_cl49TxEEEStates_c 10583 */ 10584 #define rx_x4_status4_cl49TxEEEStates_c_SCR_RESET_2 6 10585 #define rx_x4_status4_cl49TxEEEStates_c_SCR_RESET_1 5 10586 #define rx_x4_status4_cl49TxEEEStates_c_TX_WAKE 4 10587 #define rx_x4_status4_cl49TxEEEStates_c_TX_REFRESH 3 10588 #define rx_x4_status4_cl49TxEEEStates_c_TX_QUIET 2 10589 #define rx_x4_status4_cl49TxEEEStates_c_TX_SLEEP 1 10590 #define rx_x4_status4_cl49TxEEEStates_c_TX_ACTIVE 0 10591 10592 /**************************************************************************** 10593 * Enums: rx_x4_status4_cl36RxEEEStates_l 10594 */ 10595 #define rx_x4_status4_cl36RxEEEStates_l_RX_LINK_FAIL 32 10596 #define rx_x4_status4_cl36RxEEEStates_l_RX_WTF 16 10597 #define rx_x4_status4_cl36RxEEEStates_l_RX_WAKE 8 10598 #define rx_x4_status4_cl36RxEEEStates_l_RX_QUIET 4 10599 #define rx_x4_status4_cl36RxEEEStates_l_RX_SLEEP 2 10600 #define rx_x4_status4_cl36RxEEEStates_l_RX_ACTIVE 1 10601 10602 /**************************************************************************** 10603 * Enums: rx_x4_status4_cl36RxEEEStates_c 10604 */ 10605 #define rx_x4_status4_cl36RxEEEStates_c_RX_LINK_FAIL 5 10606 #define rx_x4_status4_cl36RxEEEStates_c_RX_WTF 4 10607 #define rx_x4_status4_cl36RxEEEStates_c_RX_WAKE 3 10608 #define rx_x4_status4_cl36RxEEEStates_c_RX_QUIET 2 10609 #define rx_x4_status4_cl36RxEEEStates_c_RX_SLEEP 1 10610 #define rx_x4_status4_cl36RxEEEStates_c_RX_ACTIVE 0 10611 10612 /**************************************************************************** 10613 * Enums: rx_x4_status4_cl49RxEEEStates_l 10614 */ 10615 #define rx_x4_status4_cl49RxEEEStates_l_RX_LINK_FAIL 32 10616 #define rx_x4_status4_cl49RxEEEStates_l_RX_WTF 16 10617 #define rx_x4_status4_cl49RxEEEStates_l_RX_WAKE 8 10618 #define rx_x4_status4_cl49RxEEEStates_l_RX_QUIET 4 10619 #define rx_x4_status4_cl49RxEEEStates_l_RX_SLEEP 2 10620 #define rx_x4_status4_cl49RxEEEStates_l_RX_ACTIVE 1 10621 10622 /**************************************************************************** 10623 * Enums: rx_x4_status4_cl49RxEEEStates_c 10624 */ 10625 #define rx_x4_status4_cl49RxEEEStates_c_RX_LINK_FAIL 5 10626 #define rx_x4_status4_cl49RxEEEStates_c_RX_WTF 4 10627 #define rx_x4_status4_cl49RxEEEStates_c_RX_WAKE 3 10628 #define rx_x4_status4_cl49RxEEEStates_c_RX_QUIET 2 10629 #define rx_x4_status4_cl49RxEEEStates_c_RX_SLEEP 1 10630 #define rx_x4_status4_cl49RxEEEStates_c_RX_ACTIVE 0 10631 10632 /**************************************************************************** 10633 * Enums: rx_x4_status4_cl48TxEEEStates_l 10634 */ 10635 #define rx_x4_status4_cl48TxEEEStates_l_TX_REFRESH 8 10636 #define rx_x4_status4_cl48TxEEEStates_l_TX_QUIET 4 10637 #define rx_x4_status4_cl48TxEEEStates_l_TX_SLEEP 2 10638 #define rx_x4_status4_cl48TxEEEStates_l_TX_ACTIVE 1 10639 10640 /**************************************************************************** 10641 * Enums: rx_x4_status4_cl48TxEEEStates_c 10642 */ 10643 #define rx_x4_status4_cl48TxEEEStates_c_TX_REFRESH 3 10644 #define rx_x4_status4_cl48TxEEEStates_c_TX_QUIET 2 10645 #define rx_x4_status4_cl48TxEEEStates_c_TX_SLEEP 1 10646 #define rx_x4_status4_cl48TxEEEStates_c_TX_ACTIVE 0 10647 10648 /**************************************************************************** 10649 * Enums: rx_x4_status4_cl48RxEEEStates_l 10650 */ 10651 #define rx_x4_status4_cl48RxEEEStates_l_RX_LINK_FAIL 32 10652 #define rx_x4_status4_cl48RxEEEStates_l_RX_WAKE 16 10653 #define rx_x4_status4_cl48RxEEEStates_l_RX_QUIET 8 10654 #define rx_x4_status4_cl48RxEEEStates_l_RX_DEACT 4 10655 #define rx_x4_status4_cl48RxEEEStates_l_RX_SLEEP 2 10656 #define rx_x4_status4_cl48RxEEEStates_l_RX_ACTIVE 1 10657 10658 /**************************************************************************** 10659 * Enums: rx_x4_status4_cl48RxEEEStates_c 10660 */ 10661 #define rx_x4_status4_cl48RxEEEStates_c_RX_LINK_FAIL 5 10662 #define rx_x4_status4_cl48RxEEEStates_c_RX_WAKE 4 10663 #define rx_x4_status4_cl48RxEEEStates_c_RX_QUIET 3 10664 #define rx_x4_status4_cl48RxEEEStates_c_RX_DEACT 2 10665 #define rx_x4_status4_cl48RxEEEStates_c_RX_SLEEP 1 10666 #define rx_x4_status4_cl48RxEEEStates_c_RX_ACTIVE 0 10667 10668 /**************************************************************************** 10669 * Enums: rx_x4_status4_IQP_Options 10670 */ 10671 #define rx_x4_status4_IQP_Options_i50uA 0 10672 #define rx_x4_status4_IQP_Options_i100uA 1 10673 #define rx_x4_status4_IQP_Options_i150uA 2 10674 #define rx_x4_status4_IQP_Options_i200uA 3 10675 #define rx_x4_status4_IQP_Options_i250uA 4 10676 #define rx_x4_status4_IQP_Options_i300uA 5 10677 #define rx_x4_status4_IQP_Options_i350uA 6 10678 #define rx_x4_status4_IQP_Options_i400uA 7 10679 #define rx_x4_status4_IQP_Options_i450uA 8 10680 #define rx_x4_status4_IQP_Options_i500uA 9 10681 #define rx_x4_status4_IQP_Options_i550uA 10 10682 #define rx_x4_status4_IQP_Options_i600uA 11 10683 #define rx_x4_status4_IQP_Options_i650uA 12 10684 #define rx_x4_status4_IQP_Options_i700uA 13 10685 #define rx_x4_status4_IQP_Options_i750uA 14 10686 #define rx_x4_status4_IQP_Options_i800uA 15 10687 10688 /**************************************************************************** 10689 * Enums: rx_x4_status4_IDriver_Options 10690 */ 10691 #define rx_x4_status4_IDriver_Options_v680mV 0 10692 #define rx_x4_status4_IDriver_Options_v730mV 1 10693 #define rx_x4_status4_IDriver_Options_v780mV 2 10694 #define rx_x4_status4_IDriver_Options_v830mV 3 10695 #define rx_x4_status4_IDriver_Options_v880mV 4 10696 #define rx_x4_status4_IDriver_Options_v930mV 5 10697 #define rx_x4_status4_IDriver_Options_v980mV 6 10698 #define rx_x4_status4_IDriver_Options_v1010mV 7 10699 #define rx_x4_status4_IDriver_Options_v1040mV 8 10700 #define rx_x4_status4_IDriver_Options_v1060mV 9 10701 #define rx_x4_status4_IDriver_Options_v1070mV 10 10702 #define rx_x4_status4_IDriver_Options_v1080mV 11 10703 #define rx_x4_status4_IDriver_Options_v1085mV 12 10704 #define rx_x4_status4_IDriver_Options_v1090mV 13 10705 #define rx_x4_status4_IDriver_Options_v1095mV 14 10706 #define rx_x4_status4_IDriver_Options_v1100mV 15 10707 10708 /**************************************************************************** 10709 * Enums: rx_x4_status4_operationModes 10710 */ 10711 #define rx_x4_status4_operationModes_XGXS 0 10712 #define rx_x4_status4_operationModes_XGXG_nCC 1 10713 #define rx_x4_status4_operationModes_Indlane_OS8 4 10714 #define rx_x4_status4_operationModes_IndLane_OS5 5 10715 #define rx_x4_status4_operationModes_PCI 7 10716 #define rx_x4_status4_operationModes_XGXS_nLQ 8 10717 #define rx_x4_status4_operationModes_XGXS_nLQnCC 9 10718 #define rx_x4_status4_operationModes_PBypass 10 10719 #define rx_x4_status4_operationModes_PBypass_nDSK 11 10720 #define rx_x4_status4_operationModes_ComboCoreMode 12 10721 #define rx_x4_status4_operationModes_Clocks_off 15 10722 10723 /**************************************************************************** 10724 * Enums: rx_x4_status4_actualSpeeds 10725 */ 10726 #define rx_x4_status4_actualSpeeds_dr_10M 0 10727 #define rx_x4_status4_actualSpeeds_dr_100M 1 10728 #define rx_x4_status4_actualSpeeds_dr_1G 2 10729 #define rx_x4_status4_actualSpeeds_dr_2p5G 3 10730 #define rx_x4_status4_actualSpeeds_dr_5G_X4 4 10731 #define rx_x4_status4_actualSpeeds_dr_6G_X4 5 10732 #define rx_x4_status4_actualSpeeds_dr_10G_HiG 6 10733 #define rx_x4_status4_actualSpeeds_dr_10G_CX4 7 10734 #define rx_x4_status4_actualSpeeds_dr_12G_HiG 8 10735 #define rx_x4_status4_actualSpeeds_dr_12p5G_X4 9 10736 #define rx_x4_status4_actualSpeeds_dr_13G_X4 10 10737 #define rx_x4_status4_actualSpeeds_dr_15G_X4 11 10738 #define rx_x4_status4_actualSpeeds_dr_16G_X4 12 10739 #define rx_x4_status4_actualSpeeds_dr_1G_KX 13 10740 #define rx_x4_status4_actualSpeeds_dr_10G_KX4 14 10741 #define rx_x4_status4_actualSpeeds_dr_10G_KR 15 10742 #define rx_x4_status4_actualSpeeds_dr_5G 16 10743 #define rx_x4_status4_actualSpeeds_dr_6p4G 17 10744 #define rx_x4_status4_actualSpeeds_dr_20G_X4 18 10745 #define rx_x4_status4_actualSpeeds_dr_21G_X4 19 10746 #define rx_x4_status4_actualSpeeds_dr_25G_X4 20 10747 #define rx_x4_status4_actualSpeeds_dr_10G_HiG_DXGXS 21 10748 #define rx_x4_status4_actualSpeeds_dr_10G_DXGXS 22 10749 #define rx_x4_status4_actualSpeeds_dr_10p5G_HiG_DXGXS 23 10750 #define rx_x4_status4_actualSpeeds_dr_10p5G_DXGXS 24 10751 #define rx_x4_status4_actualSpeeds_dr_12p773G_HiG_DXGXS 25 10752 #define rx_x4_status4_actualSpeeds_dr_12p773G_DXGXS 26 10753 #define rx_x4_status4_actualSpeeds_dr_10G_XFI 27 10754 #define rx_x4_status4_actualSpeeds_dr_40G 28 10755 #define rx_x4_status4_actualSpeeds_dr_20G_HiG_DXGXS 29 10756 #define rx_x4_status4_actualSpeeds_dr_20G_DXGXS 30 10757 #define rx_x4_status4_actualSpeeds_dr_10G_SFI 31 10758 #define rx_x4_status4_actualSpeeds_dr_31p5G 32 10759 #define rx_x4_status4_actualSpeeds_dr_32p7G 33 10760 #define rx_x4_status4_actualSpeeds_dr_20G_SCR 34 10761 #define rx_x4_status4_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 10762 #define rx_x4_status4_actualSpeeds_dr_10G_DXGXS_SCR 36 10763 #define rx_x4_status4_actualSpeeds_dr_12G_R2 37 10764 #define rx_x4_status4_actualSpeeds_dr_10G_X2 38 10765 #define rx_x4_status4_actualSpeeds_dr_40G_KR4 39 10766 #define rx_x4_status4_actualSpeeds_dr_40G_CR4 40 10767 #define rx_x4_status4_actualSpeeds_dr_100G_CR10 41 10768 #define rx_x4_status4_actualSpeeds_dr_15p75G_DXGXS 44 10769 #define rx_x4_status4_actualSpeeds_dr_20G_KR2 57 10770 #define rx_x4_status4_actualSpeeds_dr_20G_CR2 58 10771 10772 /**************************************************************************** 10773 * Enums: rx_x4_status4_actualSpeedsMisc1 10774 */ 10775 #define rx_x4_status4_actualSpeedsMisc1_dr_2500BRCM_X1 16 10776 #define rx_x4_status4_actualSpeedsMisc1_dr_5000BRCM_X4 17 10777 #define rx_x4_status4_actualSpeedsMisc1_dr_6000BRCM_X4 18 10778 #define rx_x4_status4_actualSpeedsMisc1_dr_10GHiGig_X4 19 10779 #define rx_x4_status4_actualSpeedsMisc1_dr_10GBASE_CX4 20 10780 #define rx_x4_status4_actualSpeedsMisc1_dr_12GHiGig_X4 21 10781 #define rx_x4_status4_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 10782 #define rx_x4_status4_actualSpeedsMisc1_dr_13GHiGig_X4 23 10783 #define rx_x4_status4_actualSpeedsMisc1_dr_15GHiGig_X4 24 10784 #define rx_x4_status4_actualSpeedsMisc1_dr_16GHiGig_X4 25 10785 #define rx_x4_status4_actualSpeedsMisc1_dr_5000BRCM_X1 26 10786 #define rx_x4_status4_actualSpeedsMisc1_dr_6363BRCM_X1 27 10787 #define rx_x4_status4_actualSpeedsMisc1_dr_20GHiGig_X4 28 10788 #define rx_x4_status4_actualSpeedsMisc1_dr_21GHiGig_X4 29 10789 #define rx_x4_status4_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 10790 #define rx_x4_status4_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 10791 10792 /**************************************************************************** 10793 * Enums: rx_x4_status4_IndLaneModes 10794 */ 10795 #define rx_x4_status4_IndLaneModes_SWSDR_div2 0 10796 #define rx_x4_status4_IndLaneModes_SWSDR_div1 1 10797 #define rx_x4_status4_IndLaneModes_DWSDR_div2 2 10798 #define rx_x4_status4_IndLaneModes_DWSDR_div1 3 10799 10800 /**************************************************************************** 10801 * Enums: rx_x4_status4_prbsSelect 10802 */ 10803 #define rx_x4_status4_prbsSelect_prbs7 0 10804 #define rx_x4_status4_prbsSelect_prbs15 1 10805 #define rx_x4_status4_prbsSelect_prbs23 2 10806 #define rx_x4_status4_prbsSelect_prbs31 3 10807 10808 /**************************************************************************** 10809 * Enums: rx_x4_status4_vcoDivider 10810 */ 10811 #define rx_x4_status4_vcoDivider_div32 0 10812 #define rx_x4_status4_vcoDivider_div36 1 10813 #define rx_x4_status4_vcoDivider_div40 2 10814 #define rx_x4_status4_vcoDivider_div42 3 10815 #define rx_x4_status4_vcoDivider_div48 4 10816 #define rx_x4_status4_vcoDivider_div50 5 10817 #define rx_x4_status4_vcoDivider_div52 6 10818 #define rx_x4_status4_vcoDivider_div54 7 10819 #define rx_x4_status4_vcoDivider_div60 8 10820 #define rx_x4_status4_vcoDivider_div64 9 10821 #define rx_x4_status4_vcoDivider_div66 10 10822 #define rx_x4_status4_vcoDivider_div68 11 10823 #define rx_x4_status4_vcoDivider_div70 12 10824 #define rx_x4_status4_vcoDivider_div80 13 10825 #define rx_x4_status4_vcoDivider_div92 14 10826 #define rx_x4_status4_vcoDivider_div100 15 10827 10828 /**************************************************************************** 10829 * Enums: rx_x4_status4_refClkSelect 10830 */ 10831 #define rx_x4_status4_refClkSelect_clk_156p25MHz 1 10832 #define rx_x4_status4_refClkSelect_clk_312p5Mhz 2 10833 10834 /**************************************************************************** 10835 * Enums: rx_x4_status4_aerMMDdevTypeSelect 10836 */ 10837 #define rx_x4_status4_aerMMDdevTypeSelect_combo_core 0 10838 #define rx_x4_status4_aerMMDdevTypeSelect_PMA_PMD 1 10839 #define rx_x4_status4_aerMMDdevTypeSelect_PCS 3 10840 #define rx_x4_status4_aerMMDdevTypeSelect_PHY 4 10841 #define rx_x4_status4_aerMMDdevTypeSelect_DTE 5 10842 #define rx_x4_status4_aerMMDdevTypeSelect_CL73_AN 7 10843 10844 /**************************************************************************** 10845 * Enums: rx_x4_status4_aerMMDportSelect 10846 */ 10847 #define rx_x4_status4_aerMMDportSelect_ln0 0 10848 #define rx_x4_status4_aerMMDportSelect_ln1 1 10849 #define rx_x4_status4_aerMMDportSelect_ln2 2 10850 #define rx_x4_status4_aerMMDportSelect_ln3 3 10851 #define rx_x4_status4_aerMMDportSelect_BCST_ln0_1_2_3 511 10852 #define rx_x4_status4_aerMMDportSelect_BCST_ln0_1 512 10853 #define rx_x4_status4_aerMMDportSelect_BCST_ln2_3 513 10854 10855 /**************************************************************************** 10856 * Enums: rx_x4_status4_firmwareModeSelect 10857 */ 10858 #define rx_x4_status4_firmwareModeSelect_DEFAULT 0 10859 #define rx_x4_status4_firmwareModeSelect_SFP_OPT_LR 1 10860 #define rx_x4_status4_firmwareModeSelect_SFP_DAC 2 10861 #define rx_x4_status4_firmwareModeSelect_XLAUI 3 10862 #define rx_x4_status4_firmwareModeSelect_LONG_CH_6G 4 10863 10864 /**************************************************************************** 10865 * Enums: rx_x4_status4_tempIdxSelect 10866 */ 10867 #define rx_x4_status4_tempIdxSelect_LTE__22p9C 15 10868 #define rx_x4_status4_tempIdxSelect_LTE__12p6C 14 10869 #define rx_x4_status4_tempIdxSelect_LTE__3p0C 13 10870 #define rx_x4_status4_tempIdxSelect_LTE_6p7C 12 10871 #define rx_x4_status4_tempIdxSelect_LTE_16p4C 11 10872 #define rx_x4_status4_tempIdxSelect_LTE_26p6C 10 10873 #define rx_x4_status4_tempIdxSelect_LTE_36p3C 9 10874 #define rx_x4_status4_tempIdxSelect_LTE_46p0C 8 10875 #define rx_x4_status4_tempIdxSelect_LTE_56p2C 7 10876 #define rx_x4_status4_tempIdxSelect_LTE_65p9C 6 10877 #define rx_x4_status4_tempIdxSelect_LTE_75p6C 5 10878 #define rx_x4_status4_tempIdxSelect_LTE_85p3C 4 10879 #define rx_x4_status4_tempIdxSelect_LTE_95p5C 3 10880 #define rx_x4_status4_tempIdxSelect_LTE_105p2C 2 10881 #define rx_x4_status4_tempIdxSelect_LTE_114p9C 1 10882 #define rx_x4_status4_tempIdxSelect_LTE_125p1C 0 10883 10884 /**************************************************************************** 10885 * Enums: rx_x4_status4_port_mode 10886 */ 10887 #define rx_x4_status4_port_mode_QUAD_PORT 0 10888 #define rx_x4_status4_port_mode_TRI_1_PORT 1 10889 #define rx_x4_status4_port_mode_TRI_2_PORT 2 10890 #define rx_x4_status4_port_mode_DUAL_PORT 3 10891 #define rx_x4_status4_port_mode_SINGLE_PORT 4 10892 #define rx_x4_status4_port_mode_SINGLE_OCTAL_PORT 5 10893 10894 /**************************************************************************** 10895 * Enums: rx_x4_status4_rev_letter_enum 10896 */ 10897 #define rx_x4_status4_rev_letter_enum_REV_A 0 10898 #define rx_x4_status4_rev_letter_enum_REV_B 1 10899 #define rx_x4_status4_rev_letter_enum_REV_C 2 10900 #define rx_x4_status4_rev_letter_enum_REV_D 3 10901 10902 /**************************************************************************** 10903 * Enums: rx_x4_status4_rev_number_enum 10904 */ 10905 #define rx_x4_status4_rev_number_enum_REV_0 0 10906 #define rx_x4_status4_rev_number_enum_REV_1 1 10907 #define rx_x4_status4_rev_number_enum_REV_2 2 10908 #define rx_x4_status4_rev_number_enum_REV_3 3 10909 #define rx_x4_status4_rev_number_enum_REV_4 4 10910 #define rx_x4_status4_rev_number_enum_REV_5 5 10911 #define rx_x4_status4_rev_number_enum_REV_6 6 10912 #define rx_x4_status4_rev_number_enum_REV_7 7 10913 10914 /**************************************************************************** 10915 * Enums: rx_x4_status4_bonding_enum 10916 */ 10917 #define rx_x4_status4_bonding_enum_WIRE_BOND 0 10918 #define rx_x4_status4_bonding_enum_FLIP_CHIP 1 10919 10920 /**************************************************************************** 10921 * Enums: rx_x4_status4_tech_process 10922 */ 10923 #define rx_x4_status4_tech_process_PROCESS_90NM 0 10924 #define rx_x4_status4_tech_process_PROCESS_65NM 1 10925 #define rx_x4_status4_tech_process_PROCESS_40NM 2 10926 #define rx_x4_status4_tech_process_PROCESS_28NM 3 10927 #define rx_x4_status4_tech_process_PROCESS_16NM 4 10928 10929 /**************************************************************************** 10930 * Enums: rx_x4_status4_model_num 10931 */ 10932 #define rx_x4_status4_model_num_SERDES_CL73 0 10933 #define rx_x4_status4_model_num_XGXS_16G 1 10934 #define rx_x4_status4_model_num_HYPERCORE 2 10935 #define rx_x4_status4_model_num_HYPERLITE 3 10936 #define rx_x4_status4_model_num_PCIE_G2_PIPE 4 10937 #define rx_x4_status4_model_num_SERDES_1p25GBd 5 10938 #define rx_x4_status4_model_num_SATA2 6 10939 #define rx_x4_status4_model_num_QSGMII 7 10940 #define rx_x4_status4_model_num_XGXS10G 8 10941 #define rx_x4_status4_model_num_WARPCORE 9 10942 #define rx_x4_status4_model_num_XFICORE 10 10943 #define rx_x4_status4_model_num_RXFI 11 10944 #define rx_x4_status4_model_num_WARPLITE 12 10945 #define rx_x4_status4_model_num_PENTACORE 13 10946 #define rx_x4_status4_model_num_ESM 14 10947 #define rx_x4_status4_model_num_QUAD_SGMII 15 10948 #define rx_x4_status4_model_num_WARPCORE_3 16 10949 #define rx_x4_status4_model_num_TSC 17 10950 #define rx_x4_status4_model_num_TSC4E 18 10951 #define rx_x4_status4_model_num_TSC12E 19 10952 #define rx_x4_status4_model_num_TSC4F 20 10953 #define rx_x4_status4_model_num_TSC4F_GEN2 21 10954 #define rx_x4_status4_model_num_XGXS_CL73_90NM 29 10955 #define rx_x4_status4_model_num_SERDES_CL73_90NM 30 10956 #define rx_x4_status4_model_num_WARPCORE3 32 10957 #define rx_x4_status4_model_num_WARPCORE4_TSC 33 10958 #define rx_x4_status4_model_num_RXAUI 34 10959 #define rx_x4_status4_model_num_TSCE_GEN3 35 10960 #define rx_x4_status4_model_num_TSC4F_GEN3 36 10961 #define rx_x4_status4_model_num_TSCBH 37 10962 10963 /**************************************************************************** 10964 * Enums: rx_x4_status4_payload 10965 */ 10966 #define rx_x4_status4_payload_REPEAT_2_BYTES 0 10967 #define rx_x4_status4_payload_RAMPING 1 10968 #define rx_x4_status4_payload_CL48_CRPAT 2 10969 #define rx_x4_status4_payload_CL48_CJPAT 3 10970 #define rx_x4_status4_payload_CL36_LONG_CRPAT 4 10971 #define rx_x4_status4_payload_CL36_SHORT_CRPAT 5 10972 10973 /**************************************************************************** 10974 * Enums: rx_x4_status4_sc 10975 */ 10976 #define rx_x4_status4_sc_SPEED_10G_IEEE_KR1 0 10977 #define rx_x4_status4_sc_SPEED_25G_IEEE_KS1_CS1 1 10978 #define rx_x4_status4_sc_SPEED_25G_IEEE_KR1_CR1 2 10979 #define rx_x4_status4_sc_SPEED_40G_IEEE_KR4 3 10980 #define rx_x4_status4_sc_SPEED_40G_IEEE_CR4 4 10981 #define rx_x4_status4_sc_SPEED_50G_IEEE_KR1_CR1 5 10982 #define rx_x4_status4_sc_SPEED_100G_IEEE_KR4 6 10983 #define rx_x4_status4_sc_SPEED_100G_IEEE_CR4 7 10984 #define rx_x4_status4_sc_SPEED_100G_IEEE_KR2_CR2 8 10985 #define rx_x4_status4_sc_SPEED_200G_IEEE_KR4_CR4 9 10986 #define rx_x4_status4_sc_SPEED_400G_IEEE_X8 10 10987 #define rx_x4_status4_sc_SPEED_CL73_IEEE_20GVCO 11 10988 #define rx_x4_status4_sc_SPEED_CL73_IEEE_25GVCO 12 10989 #define rx_x4_status4_sc_SPEED_CL73_IEEE_26GVCO 13 10990 #define rx_x4_status4_sc_SPEED_20G_BRCM_CR1 14 10991 #define rx_x4_status4_sc_SPEED_20G_BRCM_KR1 15 10992 #define rx_x4_status4_sc_SPEED_25G_BRCM_CR1 16 10993 #define rx_x4_status4_sc_SPEED_25G_BRCM_KR1 17 10994 #define rx_x4_status4_sc_SPEED_40G_BRCM_CR2 18 10995 #define rx_x4_status4_sc_SPEED_40G_BRCM_KR2 19 10996 #define rx_x4_status4_sc_SPEED_50G_BRCM_CR2 20 10997 #define rx_x4_status4_sc_SPEED_50G_BRCM_KR2 21 10998 #define rx_x4_status4_sc_SPEED_50G_BRCM_CR4 22 10999 #define rx_x4_status4_sc_SPEED_50G_BRCM_KR4 23 11000 #define rx_x4_status4_sc_SPEED_50G_BRCM_FEC_544_CR2_KR2 24 11001 #define rx_x4_status4_sc_SPEED_RESERVED_19 25 11002 #define rx_x4_status4_sc_SPEED_50G_BRCM_FEC_544_CR1_KR1 26 11003 #define rx_x4_status4_sc_SPEED_50G_BRCM_NO_FEC_CR1_KR1 27 11004 #define rx_x4_status4_sc_SPEED_50G_BRCM_FEC_528_CR1_KR1 28 11005 #define rx_x4_status4_sc_SPEED_400G_BRCM_NO_FEC_KR8_CR8 29 11006 #define rx_x4_status4_sc_SPEED_400G_BRCM_FEC_KR8_CR8 30 11007 #define rx_x4_status4_sc_SPEED_200G_BRCM_NO_FEC_KR4_CR4 31 11008 #define rx_x4_status4_sc_SPEED_200G_BRCM_KR4_CR4 32 11009 #define rx_x4_status4_sc_SPEED_100G_BRCM_KR4_CR4 33 11010 #define rx_x4_status4_sc_SPEED_RESERVED_22 34 11011 #define rx_x4_status4_sc_SPEED_100G_BRCM_FEC_528_KR2_CR2 35 11012 #define rx_x4_status4_sc_SPEED_100G_BRCM_NO_FEC_KR2_CR2 36 11013 #define rx_x4_status4_sc_SPEED_100G_BRCM_NO_FEC_X4 37 11014 11015 /**************************************************************************** 11016 * Enums: rx_x4_status4_t_fifo_modes 11017 */ 11018 #define rx_x4_status4_t_fifo_modes_T_FIFO_INSERT_NO_AM 0 11019 #define rx_x4_status4_t_fifo_modes_T_FIFO_INSERT_4_AM 1 11020 #define rx_x4_status4_t_fifo_modes_T_FIFO_INSERT_20_AM 2 11021 #define rx_x4_status4_t_fifo_modes_T_FIFO_INSERT_2_AM 3 11022 11023 /**************************************************************************** 11024 * Enums: rx_x4_status4_t_enc_modes 11025 */ 11026 #define rx_x4_status4_t_enc_modes_T_ENC_MODE_BYPASS 0 11027 #define rx_x4_status4_t_enc_modes_T_ENC_MODE_CL49 1 11028 #define rx_x4_status4_t_enc_modes_T_ENC_MODE_CL82 2 11029 11030 /**************************************************************************** 11031 * Enums: rx_x4_status4_btmx_mode 11032 */ 11033 #define rx_x4_status4_btmx_mode_BS_BTMX_MODE_1to1 0 11034 #define rx_x4_status4_btmx_mode_BS_BTMX_MODE_2to1 1 11035 #define rx_x4_status4_btmx_mode_BS_BTMX_MODE_5to1 2 11036 11037 /**************************************************************************** 11038 * Enums: rx_x4_status4_t_type_cl82 11039 */ 11040 #define rx_x4_status4_t_type_cl82_T_TYPE_B1 5 11041 #define rx_x4_status4_t_type_cl82_T_TYPE_C 4 11042 #define rx_x4_status4_t_type_cl82_T_TYPE_S 3 11043 #define rx_x4_status4_t_type_cl82_T_TYPE_T 2 11044 #define rx_x4_status4_t_type_cl82_T_TYPE_D 1 11045 #define rx_x4_status4_t_type_cl82_T_TYPE_E 0 11046 11047 /**************************************************************************** 11048 * Enums: rx_x4_status4_txsm_state_cl82 11049 */ 11050 #define rx_x4_status4_txsm_state_cl82_TX_E 4 11051 #define rx_x4_status4_txsm_state_cl82_TX_T 3 11052 #define rx_x4_status4_txsm_state_cl82_TX_D 2 11053 #define rx_x4_status4_txsm_state_cl82_TX_C 1 11054 #define rx_x4_status4_txsm_state_cl82_TX_INIT 0 11055 11056 /**************************************************************************** 11057 * Enums: rx_x4_status4_ltxsm_state_cl82 11058 */ 11059 #define rx_x4_status4_ltxsm_state_cl82_TX_E 16 11060 #define rx_x4_status4_ltxsm_state_cl82_TX_T 8 11061 #define rx_x4_status4_ltxsm_state_cl82_TX_D 4 11062 #define rx_x4_status4_ltxsm_state_cl82_TX_C 2 11063 #define rx_x4_status4_ltxsm_state_cl82_TX_INIT 1 11064 11065 /**************************************************************************** 11066 * Enums: rx_x4_status4_r_type_coded_cl82 11067 */ 11068 #define rx_x4_status4_r_type_coded_cl82_R_TYPE_B1 32 11069 #define rx_x4_status4_r_type_coded_cl82_R_TYPE_C 16 11070 #define rx_x4_status4_r_type_coded_cl82_R_TYPE_S 8 11071 #define rx_x4_status4_r_type_coded_cl82_R_TYPE_T 4 11072 #define rx_x4_status4_r_type_coded_cl82_R_TYPE_D 2 11073 #define rx_x4_status4_r_type_coded_cl82_R_TYPE_E 1 11074 11075 /**************************************************************************** 11076 * Enums: rx_x4_status4_rxsm_state_cl82 11077 */ 11078 #define rx_x4_status4_rxsm_state_cl82_RX_E 16 11079 #define rx_x4_status4_rxsm_state_cl82_RX_T 8 11080 #define rx_x4_status4_rxsm_state_cl82_RX_D 4 11081 #define rx_x4_status4_rxsm_state_cl82_RX_C 2 11082 #define rx_x4_status4_rxsm_state_cl82_RX_INIT 1 11083 11084 /**************************************************************************** 11085 * Enums: rx_x4_status4_deskew_state 11086 */ 11087 #define rx_x4_status4_deskew_state_ALIGN_ACQUIRED 2 11088 #define rx_x4_status4_deskew_state_LOSS_OF_ALIGNMENT 1 11089 11090 /**************************************************************************** 11091 * Enums: rx_x4_status4_os_mode_enum 11092 */ 11093 #define rx_x4_status4_os_mode_enum_OS_MODE_1 0 11094 #define rx_x4_status4_os_mode_enum_OS_MODE_2 1 11095 #define rx_x4_status4_os_mode_enum_OS_MODE_4 2 11096 #define rx_x4_status4_os_mode_enum_OS_MODE_16p5 8 11097 #define rx_x4_status4_os_mode_enum_OS_MODE_20p625 12 11098 11099 /**************************************************************************** 11100 * Enums: rx_x4_status4_scr_modes 11101 */ 11102 #define rx_x4_status4_scr_modes_T_SCR_MODE_BYPASS 0 11103 #define rx_x4_status4_scr_modes_T_SCR_MODE_CL49 1 11104 #define rx_x4_status4_scr_modes_T_SCR_MODE_40G_2_LANE 2 11105 #define rx_x4_status4_scr_modes_T_SCR_MODE_100G 3 11106 #define rx_x4_status4_scr_modes_T_SCR_MODE_20G 4 11107 #define rx_x4_status4_scr_modes_T_SCR_MODE_40G_4_LANE 5 11108 11109 /**************************************************************************** 11110 * Enums: rx_x4_status4_descr_modes 11111 */ 11112 #define rx_x4_status4_descr_modes_R_DESCR_MODE_BYPASS 0 11113 #define rx_x4_status4_descr_modes_R_DESCR_MODE_CL49 1 11114 #define rx_x4_status4_descr_modes_R_DESCR_MODE_CL82 2 11115 11116 /**************************************************************************** 11117 * Enums: rx_x4_status4_r_dec_tl_mode 11118 */ 11119 #define rx_x4_status4_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 11120 #define rx_x4_status4_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 11121 #define rx_x4_status4_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 11122 11123 /**************************************************************************** 11124 * Enums: rx_x4_status4_r_dec_fsm_mode 11125 */ 11126 #define rx_x4_status4_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 11127 #define rx_x4_status4_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 11128 #define rx_x4_status4_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 11129 11130 /**************************************************************************** 11131 * Enums: rx_x4_status4_r_deskew_mode 11132 */ 11133 #define rx_x4_status4_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 11134 #define rx_x4_status4_r_deskew_mode_R_DESKEW_MODE_20G 1 11135 #define rx_x4_status4_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 11136 #define rx_x4_status4_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 11137 #define rx_x4_status4_r_deskew_mode_R_DESKEW_MODE_100G 4 11138 #define rx_x4_status4_r_deskew_mode_R_DESKEW_MODE_CL49 5 11139 #define rx_x4_status4_r_deskew_mode_R_DESKEW_MODE_CL91_QUAD 6 11140 #define rx_x4_status4_r_deskew_mode_R_DESKEW_MODE_CL91_SINGLE_BRCM 7 11141 #define rx_x4_status4_r_deskew_mode_R_DESKEW_MODE_CL91_DUAL_BRCM 8 11142 #define rx_x4_status4_r_deskew_mode_R_DESKEW_MODE_CL91_FC 9 11143 11144 /**************************************************************************** 11145 * Enums: rx_x4_status4_bs_dist_modes 11146 */ 11147 #define rx_x4_status4_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 11148 #define rx_x4_status4_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 11149 #define rx_x4_status4_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 11150 #define rx_x4_status4_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 11151 11152 /**************************************************************************** 11153 * Enums: rx_x4_status4_cl49_t_type 11154 */ 11155 #define rx_x4_status4_cl49_t_type_BAD_T_TYPE 15 11156 #define rx_x4_status4_cl49_t_type_T_TYPE_B0 11 11157 #define rx_x4_status4_cl49_t_type_T_TYPE_OB 10 11158 #define rx_x4_status4_cl49_t_type_T_TYPE_B1 9 11159 #define rx_x4_status4_cl49_t_type_T_TYPE_DB 8 11160 #define rx_x4_status4_cl49_t_type_T_TYPE_FC 7 11161 #define rx_x4_status4_cl49_t_type_T_TYPE_TB 6 11162 #define rx_x4_status4_cl49_t_type_T_TYPE_LI 5 11163 #define rx_x4_status4_cl49_t_type_T_TYPE_C 4 11164 #define rx_x4_status4_cl49_t_type_T_TYPE_S 3 11165 #define rx_x4_status4_cl49_t_type_T_TYPE_T 2 11166 #define rx_x4_status4_cl49_t_type_T_TYPE_D 1 11167 #define rx_x4_status4_cl49_t_type_T_TYPE_E 0 11168 11169 /**************************************************************************** 11170 * Enums: rx_x4_status4_cl49_txsm_states 11171 */ 11172 #define rx_x4_status4_cl49_txsm_states_TX_LI 5 11173 #define rx_x4_status4_cl49_txsm_states_TX_E 4 11174 #define rx_x4_status4_cl49_txsm_states_TX_T 3 11175 #define rx_x4_status4_cl49_txsm_states_TX_D 2 11176 #define rx_x4_status4_cl49_txsm_states_TX_C 1 11177 #define rx_x4_status4_cl49_txsm_states_TX_INIT 0 11178 11179 /**************************************************************************** 11180 * Enums: rx_x4_status4_cl49_ltxsm_states 11181 */ 11182 #define rx_x4_status4_cl49_ltxsm_states_TX_LI 32 11183 #define rx_x4_status4_cl49_ltxsm_states_TX_E 16 11184 #define rx_x4_status4_cl49_ltxsm_states_TX_T 8 11185 #define rx_x4_status4_cl49_ltxsm_states_TX_D 4 11186 #define rx_x4_status4_cl49_ltxsm_states_TX_C 2 11187 #define rx_x4_status4_cl49_ltxsm_states_TX_INIT 1 11188 11189 /**************************************************************************** 11190 * Enums: rx_x4_status4_burst_error_mode 11191 */ 11192 #define rx_x4_status4_burst_error_mode_BURST_ERROR_11_BITS 0 11193 #define rx_x4_status4_burst_error_mode_BURST_ERROR_16_BITS 1 11194 #define rx_x4_status4_burst_error_mode_BURST_ERROR_17_BITS 2 11195 #define rx_x4_status4_burst_error_mode_BURST_ERROR_18_BITS 3 11196 #define rx_x4_status4_burst_error_mode_BURST_ERROR_19_BITS 4 11197 #define rx_x4_status4_burst_error_mode_BURST_ERROR_20_BITS 5 11198 #define rx_x4_status4_burst_error_mode_BURST_ERROR_21_BITS 6 11199 #define rx_x4_status4_burst_error_mode_BURST_ERROR_22_BITS 7 11200 #define rx_x4_status4_burst_error_mode_BURST_ERROR_23_BITS 8 11201 #define rx_x4_status4_burst_error_mode_BURST_ERROR_24_BITS 9 11202 #define rx_x4_status4_burst_error_mode_BURST_ERROR_25_BITS 10 11203 #define rx_x4_status4_burst_error_mode_BURST_ERROR_26_BITS 11 11204 #define rx_x4_status4_burst_error_mode_BURST_ERROR_27_BITS 12 11205 #define rx_x4_status4_burst_error_mode_BURST_ERROR_28_BITS 13 11206 #define rx_x4_status4_burst_error_mode_BURST_ERROR_29_BITS 14 11207 #define rx_x4_status4_burst_error_mode_BURST_ERROR_30_BITS 15 11208 #define rx_x4_status4_burst_error_mode_BURST_ERROR_31_BITS 16 11209 #define rx_x4_status4_burst_error_mode_BURST_ERROR_32_BITS 17 11210 #define rx_x4_status4_burst_error_mode_BURST_ERROR_33_BITS 18 11211 #define rx_x4_status4_burst_error_mode_BURST_ERROR_34_BITS 19 11212 #define rx_x4_status4_burst_error_mode_BURST_ERROR_35_BITS 20 11213 #define rx_x4_status4_burst_error_mode_BURST_ERROR_36_BITS 21 11214 #define rx_x4_status4_burst_error_mode_BURST_ERROR_37_BITS 22 11215 #define rx_x4_status4_burst_error_mode_BURST_ERROR_38_BITS 23 11216 #define rx_x4_status4_burst_error_mode_BURST_ERROR_39_BITS 24 11217 #define rx_x4_status4_burst_error_mode_BURST_ERROR_40_BITS 25 11218 #define rx_x4_status4_burst_error_mode_BURST_ERROR_41_BITS 26 11219 11220 /**************************************************************************** 11221 * Enums: rx_x4_status4_bermon_state 11222 */ 11223 #define rx_x4_status4_bermon_state_HI_BER 4 11224 #define rx_x4_status4_bermon_state_GOOD_BER 3 11225 #define rx_x4_status4_bermon_state_BER_TEST_SH 2 11226 #define rx_x4_status4_bermon_state_START_TIMER 1 11227 #define rx_x4_status4_bermon_state_BER_MT_INIT 0 11228 11229 /**************************************************************************** 11230 * Enums: rx_x4_status4_rxsm_state_cl49 11231 */ 11232 #define rx_x4_status4_rxsm_state_cl49_RX_LI 32 11233 #define rx_x4_status4_rxsm_state_cl49_RX_E 16 11234 #define rx_x4_status4_rxsm_state_cl49_RX_T 8 11235 #define rx_x4_status4_rxsm_state_cl49_RX_D 4 11236 #define rx_x4_status4_rxsm_state_cl49_RX_C 2 11237 #define rx_x4_status4_rxsm_state_cl49_RX_INIT 1 11238 11239 /**************************************************************************** 11240 * Enums: rx_x4_status4_r_type 11241 */ 11242 #define rx_x4_status4_r_type_BAD_R_TYPE 15 11243 #define rx_x4_status4_r_type_R_TYPE_B0 11 11244 #define rx_x4_status4_r_type_R_TYPE_OB 10 11245 #define rx_x4_status4_r_type_R_TYPE_B1 9 11246 #define rx_x4_status4_r_type_R_TYPE_DB 8 11247 #define rx_x4_status4_r_type_R_TYPE_FC 7 11248 #define rx_x4_status4_r_type_R_TYPE_TB 6 11249 #define rx_x4_status4_r_type_R_TYPE_LI 5 11250 #define rx_x4_status4_r_type_R_TYPE_C 4 11251 #define rx_x4_status4_r_type_R_TYPE_S 3 11252 #define rx_x4_status4_r_type_R_TYPE_T 2 11253 #define rx_x4_status4_r_type_R_TYPE_D 1 11254 #define rx_x4_status4_r_type_R_TYPE_E 0 11255 11256 /**************************************************************************** 11257 * Enums: rx_x4_status4_am_lock_state 11258 */ 11259 #define rx_x4_status4_am_lock_state_INVALID_AM 512 11260 #define rx_x4_status4_am_lock_state_GOOD_AM 256 11261 #define rx_x4_status4_am_lock_state_COMP_AM 128 11262 #define rx_x4_status4_am_lock_state_TIMER_2 64 11263 #define rx_x4_status4_am_lock_state_AM_2_GOOD 32 11264 #define rx_x4_status4_am_lock_state_COMP_2ND 16 11265 #define rx_x4_status4_am_lock_state_TIMER_1 8 11266 #define rx_x4_status4_am_lock_state_FIND_1ST 4 11267 #define rx_x4_status4_am_lock_state_AM_RESET_CNT 2 11268 #define rx_x4_status4_am_lock_state_AM_LOCK_INIT 1 11269 11270 /**************************************************************************** 11271 * Enums: rx_x4_status4_msg_selector 11272 */ 11273 #define rx_x4_status4_msg_selector_RESERVED 0 11274 #define rx_x4_status4_msg_selector_VALUE_802p3 1 11275 #define rx_x4_status4_msg_selector_VALUE_802p9 2 11276 #define rx_x4_status4_msg_selector_VALUE_802p5 3 11277 #define rx_x4_status4_msg_selector_VALUE_1394 4 11278 11279 /**************************************************************************** 11280 * Enums: rx_x4_status4_synce_enum_stage1 11281 */ 11282 #define rx_x4_status4_synce_enum_stage1_SYNCE_NO_DIV 0 11283 #define rx_x4_status4_synce_enum_stage1_SYNCE_DIV_7 1 11284 #define rx_x4_status4_synce_enum_stage1_SYNCE_DIV_11 2 11285 11286 /**************************************************************************** 11287 * Enums: rx_x4_status4_synce_enum_stage0 11288 */ 11289 #define rx_x4_status4_synce_enum_stage0_SYNCE_NO_DIV 0 11290 #define rx_x4_status4_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 11291 #define rx_x4_status4_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 11292 11293 /**************************************************************************** 11294 * Enums: rx_x4_status4_cl91_sync_state 11295 */ 11296 #define rx_x4_status4_cl91_sync_state_FIND_1ST 0 11297 #define rx_x4_status4_cl91_sync_state_COUNT_NEXT 1 11298 #define rx_x4_status4_cl91_sync_state_COMP_2ND 2 11299 #define rx_x4_status4_cl91_sync_state_TWO_GOOD 3 11300 11301 /**************************************************************************** 11302 * Enums: rx_x4_status4_RS_FEC_sync_state 11303 */ 11304 #define rx_x4_status4_RS_FEC_sync_state_LOCK_INIT 0 11305 #define rx_x4_status4_RS_FEC_sync_state_FIND_1ST 1 11306 #define rx_x4_status4_RS_FEC_sync_state_COUNT_NEXT 2 11307 #define rx_x4_status4_RS_FEC_sync_state_COMP_2ND 3 11308 #define rx_x4_status4_RS_FEC_sync_state_TWO_GOOD 4 11309 11310 /**************************************************************************** 11311 * Enums: rx_x4_status4_cl91_algn_state 11312 */ 11313 #define rx_x4_status4_cl91_algn_state_LOSS_OF_ALIGNMENT 0 11314 #define rx_x4_status4_cl91_algn_state_DESKEW 1 11315 #define rx_x4_status4_cl91_algn_state_DESKEW_FAIL 2 11316 #define rx_x4_status4_cl91_algn_state_ALIGN_ACQUIRED 3 11317 #define rx_x4_status4_cl91_algn_state_CW_GOOD 4 11318 #define rx_x4_status4_cl91_algn_state_CW_BAD 5 11319 #define rx_x4_status4_cl91_algn_state_THREE_BAD 6 11320 11321 /**************************************************************************** 11322 * Enums: rx_x4_status4_RS_FEC_algn_state 11323 */ 11324 #define rx_x4_status4_RS_FEC_algn_state_LOSS_OF_ALIGNMENT 0 11325 #define rx_x4_status4_RS_FEC_algn_state_DESKEW 1 11326 #define rx_x4_status4_RS_FEC_algn_state_DESKEW_FAIL 2 11327 #define rx_x4_status4_RS_FEC_algn_state_ALIGN_ACQUIRED 3 11328 #define rx_x4_status4_RS_FEC_algn_state_CW_GOOD 4 11329 #define rx_x4_status4_RS_FEC_algn_state_CW_BAD 5 11330 #define rx_x4_status4_RS_FEC_algn_state_THREE_BAD 6 11331 11332 /**************************************************************************** 11333 * Enums: rx_x4_status4_fec_sel_override 11334 */ 11335 #define rx_x4_status4_fec_sel_override_NO_OVERRIDE 0 11336 #define rx_x4_status4_fec_sel_override_NO_FEC 1 11337 #define rx_x4_status4_fec_sel_override_FEC_CL74 2 11338 #define rx_x4_status4_fec_sel_override_FEC_CL91 3 11339 11340 /**************************************************************************** 11341 * Enums: rx_x4_status4_cl91_blksync_mode 11342 */ 11343 #define rx_x4_status4_cl91_blksync_mode_R_BLKSYNC_NO_CL91_FEC 0 11344 #define rx_x4_status4_cl91_blksync_mode_R_BLKSYNC_CL91_QUAD_LANE_FEC 1 11345 #define rx_x4_status4_cl91_blksync_mode_R_BLKSYNC_CL91_DUAL_LANE_FEC 2 11346 #define rx_x4_status4_cl91_blksync_mode_R_BLKSYNC_CL91_SINGLE_LANE_FEC 3 11347 #define rx_x4_status4_cl91_blksync_mode_R_BLKSYNC_CL91_FC_FEC 4 11348 11349 /**************************************************************************** 11350 * Enums: rx_x4_status4_r_merge_mode 11351 */ 11352 #define rx_x4_status4_r_merge_mode_R_MERGE_MODE_BYPASS 0 11353 #define rx_x4_status4_r_merge_mode_R_MERGE_MODE_CL91_FC 1 11354 #define rx_x4_status4_r_merge_mode_R_MERGE_MODE_CL91_SINGLE_LANE 2 11355 #define rx_x4_status4_r_merge_mode_R_MERGE_MODE_CL91_DUAL_LANE 3 11356 #define rx_x4_status4_r_merge_mode_R_MERGE_MODE_CL91_QUAD_LANE 4 11357 11358 /**************************************************************************** 11359 * Enums: rx_x4_status4_r_tc_mode 11360 */ 11361 #define rx_x4_status4_r_tc_mode_R_TC_MODE_SINGLE 0 11362 #define rx_x4_status4_r_tc_mode_R_TC_MODE_DUAL 1 11363 #define rx_x4_status4_r_tc_mode_R_TC_MODE_QUAD 2 11364 11365 /**************************************************************************** 11366 * Enums: rx_x4_status4_r_tc_out_mode 11367 */ 11368 #define rx_x4_status4_r_tc_out_mode_R_TC_OUT_MODE_SINGLE 0 11369 #define rx_x4_status4_r_tc_out_mode_R_TC_OUT_MODE_DUAL 1 11370 #define rx_x4_status4_r_tc_out_mode_R_TC_OUT_MODE_QUAD 2 11371 11372 /**************************************************************************** 11373 * Enums: rx_x4_status4_cl91_fec_mode 11374 */ 11375 #define rx_x4_status4_cl91_fec_mode_NO_CL91_FEC 0 11376 #define rx_x4_status4_cl91_fec_mode_CL91_SINGLE_LANE_FC 1 11377 #define rx_x4_status4_cl91_fec_mode_CL91_SINGLE_LANE_BRCM_PROP 2 11378 #define rx_x4_status4_cl91_fec_mode_CL91_DUAL_LANE_BRCM_PROP 3 11379 #define rx_x4_status4_cl91_fec_mode_CL91_QUAD_LANE 4 11380 #define rx_x4_status4_cl91_fec_mode_IEEE_25G_CL91_SINGLE_LANE 5 11381 11382 /**************************************************************************** 11383 * Enums: rx_x4_status4_RS_FEC_fec_mode 11384 */ 11385 #define rx_x4_status4_RS_FEC_fec_mode_NO_RS_FEC_FEC 0 11386 #define rx_x4_status4_RS_FEC_fec_mode_N_A 1 11387 #define rx_x4_status4_RS_FEC_fec_mode_RS_FEC_SINGLE_LANE_BRCM_PROP 2 11388 #define rx_x4_status4_RS_FEC_fec_mode_RS_FEC_DUAL_LANE_BRCM_PROP 3 11389 #define rx_x4_status4_RS_FEC_fec_mode_RS_FEC_QUAD_LANE 4 11390 #define rx_x4_status4_RS_FEC_fec_mode_IEEE_25G_RS_FEC_SINGLE_LANE 5 11391 11392 /**************************************************************************** 11393 * Enums: rx_x4_status4_am_spacing_mul 11394 */ 11395 #define rx_x4_status4_am_spacing_mul_AM_SPACING_MUL_2 0 11396 #define rx_x4_status4_am_spacing_mul_AM_SPACING_MUL_4 1 11397 #define rx_x4_status4_am_spacing_mul_AM_SPACING_MUL_5 2 11398 #define rx_x4_status4_am_spacing_mul_AM_SPACING_MUL_20 3 11399 11400 /**************************************************************************** 11401 * Enums: rx_x4_status5_cl36TxEEEStates_l 11402 */ 11403 #define rx_x4_status5_cl36TxEEEStates_l_TX_REFRESH 8 11404 #define rx_x4_status5_cl36TxEEEStates_l_TX_QUIET 4 11405 #define rx_x4_status5_cl36TxEEEStates_l_TX_SLEEP 2 11406 #define rx_x4_status5_cl36TxEEEStates_l_TX_ACTIVE 1 11407 11408 /**************************************************************************** 11409 * Enums: rx_x4_status5_cl36TxEEEStates_c 11410 */ 11411 #define rx_x4_status5_cl36TxEEEStates_c_TX_REFRESH 3 11412 #define rx_x4_status5_cl36TxEEEStates_c_TX_QUIET 2 11413 #define rx_x4_status5_cl36TxEEEStates_c_TX_SLEEP 1 11414 #define rx_x4_status5_cl36TxEEEStates_c_TX_ACTIVE 0 11415 11416 /**************************************************************************** 11417 * Enums: rx_x4_status5_cl49TxEEEStates_l 11418 */ 11419 #define rx_x4_status5_cl49TxEEEStates_l_SCR_RESET_2 64 11420 #define rx_x4_status5_cl49TxEEEStates_l_SCR_RESET_1 32 11421 #define rx_x4_status5_cl49TxEEEStates_l_TX_WAKE 16 11422 #define rx_x4_status5_cl49TxEEEStates_l_TX_REFRESH 8 11423 #define rx_x4_status5_cl49TxEEEStates_l_TX_QUIET 4 11424 #define rx_x4_status5_cl49TxEEEStates_l_TX_SLEEP 2 11425 #define rx_x4_status5_cl49TxEEEStates_l_TX_ACTIVE 1 11426 11427 /**************************************************************************** 11428 * Enums: rx_x4_status5_fec_req_enum 11429 */ 11430 #define rx_x4_status5_fec_req_enum_FEC_not_supported 0 11431 #define rx_x4_status5_fec_req_enum_FEC_supported_but_not_requested 1 11432 #define rx_x4_status5_fec_req_enum_invalid_setting 2 11433 #define rx_x4_status5_fec_req_enum_FEC_supported_and_requested 3 11434 11435 /**************************************************************************** 11436 * Enums: rx_x4_status5_cl73_pause_enum 11437 */ 11438 #define rx_x4_status5_cl73_pause_enum_No_PAUSE_ability 0 11439 #define rx_x4_status5_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 11440 #define rx_x4_status5_cl73_pause_enum_Symmetric_PAUSE_ability 1 11441 #define rx_x4_status5_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 11442 11443 /**************************************************************************** 11444 * Enums: rx_x4_status5_cl49TxEEEStates_c 11445 */ 11446 #define rx_x4_status5_cl49TxEEEStates_c_SCR_RESET_2 6 11447 #define rx_x4_status5_cl49TxEEEStates_c_SCR_RESET_1 5 11448 #define rx_x4_status5_cl49TxEEEStates_c_TX_WAKE 4 11449 #define rx_x4_status5_cl49TxEEEStates_c_TX_REFRESH 3 11450 #define rx_x4_status5_cl49TxEEEStates_c_TX_QUIET 2 11451 #define rx_x4_status5_cl49TxEEEStates_c_TX_SLEEP 1 11452 #define rx_x4_status5_cl49TxEEEStates_c_TX_ACTIVE 0 11453 11454 /**************************************************************************** 11455 * Enums: rx_x4_status5_cl36RxEEEStates_l 11456 */ 11457 #define rx_x4_status5_cl36RxEEEStates_l_RX_LINK_FAIL 32 11458 #define rx_x4_status5_cl36RxEEEStates_l_RX_WTF 16 11459 #define rx_x4_status5_cl36RxEEEStates_l_RX_WAKE 8 11460 #define rx_x4_status5_cl36RxEEEStates_l_RX_QUIET 4 11461 #define rx_x4_status5_cl36RxEEEStates_l_RX_SLEEP 2 11462 #define rx_x4_status5_cl36RxEEEStates_l_RX_ACTIVE 1 11463 11464 /**************************************************************************** 11465 * Enums: rx_x4_status5_cl36RxEEEStates_c 11466 */ 11467 #define rx_x4_status5_cl36RxEEEStates_c_RX_LINK_FAIL 5 11468 #define rx_x4_status5_cl36RxEEEStates_c_RX_WTF 4 11469 #define rx_x4_status5_cl36RxEEEStates_c_RX_WAKE 3 11470 #define rx_x4_status5_cl36RxEEEStates_c_RX_QUIET 2 11471 #define rx_x4_status5_cl36RxEEEStates_c_RX_SLEEP 1 11472 #define rx_x4_status5_cl36RxEEEStates_c_RX_ACTIVE 0 11473 11474 /**************************************************************************** 11475 * Enums: rx_x4_status5_cl49RxEEEStates_l 11476 */ 11477 #define rx_x4_status5_cl49RxEEEStates_l_RX_LINK_FAIL 32 11478 #define rx_x4_status5_cl49RxEEEStates_l_RX_WTF 16 11479 #define rx_x4_status5_cl49RxEEEStates_l_RX_WAKE 8 11480 #define rx_x4_status5_cl49RxEEEStates_l_RX_QUIET 4 11481 #define rx_x4_status5_cl49RxEEEStates_l_RX_SLEEP 2 11482 #define rx_x4_status5_cl49RxEEEStates_l_RX_ACTIVE 1 11483 11484 /**************************************************************************** 11485 * Enums: rx_x4_status5_cl49RxEEEStates_c 11486 */ 11487 #define rx_x4_status5_cl49RxEEEStates_c_RX_LINK_FAIL 5 11488 #define rx_x4_status5_cl49RxEEEStates_c_RX_WTF 4 11489 #define rx_x4_status5_cl49RxEEEStates_c_RX_WAKE 3 11490 #define rx_x4_status5_cl49RxEEEStates_c_RX_QUIET 2 11491 #define rx_x4_status5_cl49RxEEEStates_c_RX_SLEEP 1 11492 #define rx_x4_status5_cl49RxEEEStates_c_RX_ACTIVE 0 11493 11494 /**************************************************************************** 11495 * Enums: rx_x4_status5_cl48TxEEEStates_l 11496 */ 11497 #define rx_x4_status5_cl48TxEEEStates_l_TX_REFRESH 8 11498 #define rx_x4_status5_cl48TxEEEStates_l_TX_QUIET 4 11499 #define rx_x4_status5_cl48TxEEEStates_l_TX_SLEEP 2 11500 #define rx_x4_status5_cl48TxEEEStates_l_TX_ACTIVE 1 11501 11502 /**************************************************************************** 11503 * Enums: rx_x4_status5_cl48TxEEEStates_c 11504 */ 11505 #define rx_x4_status5_cl48TxEEEStates_c_TX_REFRESH 3 11506 #define rx_x4_status5_cl48TxEEEStates_c_TX_QUIET 2 11507 #define rx_x4_status5_cl48TxEEEStates_c_TX_SLEEP 1 11508 #define rx_x4_status5_cl48TxEEEStates_c_TX_ACTIVE 0 11509 11510 /**************************************************************************** 11511 * Enums: rx_x4_status5_cl48RxEEEStates_l 11512 */ 11513 #define rx_x4_status5_cl48RxEEEStates_l_RX_LINK_FAIL 32 11514 #define rx_x4_status5_cl48RxEEEStates_l_RX_WAKE 16 11515 #define rx_x4_status5_cl48RxEEEStates_l_RX_QUIET 8 11516 #define rx_x4_status5_cl48RxEEEStates_l_RX_DEACT 4 11517 #define rx_x4_status5_cl48RxEEEStates_l_RX_SLEEP 2 11518 #define rx_x4_status5_cl48RxEEEStates_l_RX_ACTIVE 1 11519 11520 /**************************************************************************** 11521 * Enums: rx_x4_status5_cl48RxEEEStates_c 11522 */ 11523 #define rx_x4_status5_cl48RxEEEStates_c_RX_LINK_FAIL 5 11524 #define rx_x4_status5_cl48RxEEEStates_c_RX_WAKE 4 11525 #define rx_x4_status5_cl48RxEEEStates_c_RX_QUIET 3 11526 #define rx_x4_status5_cl48RxEEEStates_c_RX_DEACT 2 11527 #define rx_x4_status5_cl48RxEEEStates_c_RX_SLEEP 1 11528 #define rx_x4_status5_cl48RxEEEStates_c_RX_ACTIVE 0 11529 11530 /**************************************************************************** 11531 * Enums: rx_x4_status5_IQP_Options 11532 */ 11533 #define rx_x4_status5_IQP_Options_i50uA 0 11534 #define rx_x4_status5_IQP_Options_i100uA 1 11535 #define rx_x4_status5_IQP_Options_i150uA 2 11536 #define rx_x4_status5_IQP_Options_i200uA 3 11537 #define rx_x4_status5_IQP_Options_i250uA 4 11538 #define rx_x4_status5_IQP_Options_i300uA 5 11539 #define rx_x4_status5_IQP_Options_i350uA 6 11540 #define rx_x4_status5_IQP_Options_i400uA 7 11541 #define rx_x4_status5_IQP_Options_i450uA 8 11542 #define rx_x4_status5_IQP_Options_i500uA 9 11543 #define rx_x4_status5_IQP_Options_i550uA 10 11544 #define rx_x4_status5_IQP_Options_i600uA 11 11545 #define rx_x4_status5_IQP_Options_i650uA 12 11546 #define rx_x4_status5_IQP_Options_i700uA 13 11547 #define rx_x4_status5_IQP_Options_i750uA 14 11548 #define rx_x4_status5_IQP_Options_i800uA 15 11549 11550 /**************************************************************************** 11551 * Enums: rx_x4_status5_IDriver_Options 11552 */ 11553 #define rx_x4_status5_IDriver_Options_v680mV 0 11554 #define rx_x4_status5_IDriver_Options_v730mV 1 11555 #define rx_x4_status5_IDriver_Options_v780mV 2 11556 #define rx_x4_status5_IDriver_Options_v830mV 3 11557 #define rx_x4_status5_IDriver_Options_v880mV 4 11558 #define rx_x4_status5_IDriver_Options_v930mV 5 11559 #define rx_x4_status5_IDriver_Options_v980mV 6 11560 #define rx_x4_status5_IDriver_Options_v1010mV 7 11561 #define rx_x4_status5_IDriver_Options_v1040mV 8 11562 #define rx_x4_status5_IDriver_Options_v1060mV 9 11563 #define rx_x4_status5_IDriver_Options_v1070mV 10 11564 #define rx_x4_status5_IDriver_Options_v1080mV 11 11565 #define rx_x4_status5_IDriver_Options_v1085mV 12 11566 #define rx_x4_status5_IDriver_Options_v1090mV 13 11567 #define rx_x4_status5_IDriver_Options_v1095mV 14 11568 #define rx_x4_status5_IDriver_Options_v1100mV 15 11569 11570 /**************************************************************************** 11571 * Enums: rx_x4_status5_operationModes 11572 */ 11573 #define rx_x4_status5_operationModes_XGXS 0 11574 #define rx_x4_status5_operationModes_XGXG_nCC 1 11575 #define rx_x4_status5_operationModes_Indlane_OS8 4 11576 #define rx_x4_status5_operationModes_IndLane_OS5 5 11577 #define rx_x4_status5_operationModes_PCI 7 11578 #define rx_x4_status5_operationModes_XGXS_nLQ 8 11579 #define rx_x4_status5_operationModes_XGXS_nLQnCC 9 11580 #define rx_x4_status5_operationModes_PBypass 10 11581 #define rx_x4_status5_operationModes_PBypass_nDSK 11 11582 #define rx_x4_status5_operationModes_ComboCoreMode 12 11583 #define rx_x4_status5_operationModes_Clocks_off 15 11584 11585 /**************************************************************************** 11586 * Enums: rx_x4_status5_actualSpeeds 11587 */ 11588 #define rx_x4_status5_actualSpeeds_dr_10M 0 11589 #define rx_x4_status5_actualSpeeds_dr_100M 1 11590 #define rx_x4_status5_actualSpeeds_dr_1G 2 11591 #define rx_x4_status5_actualSpeeds_dr_2p5G 3 11592 #define rx_x4_status5_actualSpeeds_dr_5G_X4 4 11593 #define rx_x4_status5_actualSpeeds_dr_6G_X4 5 11594 #define rx_x4_status5_actualSpeeds_dr_10G_HiG 6 11595 #define rx_x4_status5_actualSpeeds_dr_10G_CX4 7 11596 #define rx_x4_status5_actualSpeeds_dr_12G_HiG 8 11597 #define rx_x4_status5_actualSpeeds_dr_12p5G_X4 9 11598 #define rx_x4_status5_actualSpeeds_dr_13G_X4 10 11599 #define rx_x4_status5_actualSpeeds_dr_15G_X4 11 11600 #define rx_x4_status5_actualSpeeds_dr_16G_X4 12 11601 #define rx_x4_status5_actualSpeeds_dr_1G_KX 13 11602 #define rx_x4_status5_actualSpeeds_dr_10G_KX4 14 11603 #define rx_x4_status5_actualSpeeds_dr_10G_KR 15 11604 #define rx_x4_status5_actualSpeeds_dr_5G 16 11605 #define rx_x4_status5_actualSpeeds_dr_6p4G 17 11606 #define rx_x4_status5_actualSpeeds_dr_20G_X4 18 11607 #define rx_x4_status5_actualSpeeds_dr_21G_X4 19 11608 #define rx_x4_status5_actualSpeeds_dr_25G_X4 20 11609 #define rx_x4_status5_actualSpeeds_dr_10G_HiG_DXGXS 21 11610 #define rx_x4_status5_actualSpeeds_dr_10G_DXGXS 22 11611 #define rx_x4_status5_actualSpeeds_dr_10p5G_HiG_DXGXS 23 11612 #define rx_x4_status5_actualSpeeds_dr_10p5G_DXGXS 24 11613 #define rx_x4_status5_actualSpeeds_dr_12p773G_HiG_DXGXS 25 11614 #define rx_x4_status5_actualSpeeds_dr_12p773G_DXGXS 26 11615 #define rx_x4_status5_actualSpeeds_dr_10G_XFI 27 11616 #define rx_x4_status5_actualSpeeds_dr_40G 28 11617 #define rx_x4_status5_actualSpeeds_dr_20G_HiG_DXGXS 29 11618 #define rx_x4_status5_actualSpeeds_dr_20G_DXGXS 30 11619 #define rx_x4_status5_actualSpeeds_dr_10G_SFI 31 11620 #define rx_x4_status5_actualSpeeds_dr_31p5G 32 11621 #define rx_x4_status5_actualSpeeds_dr_32p7G 33 11622 #define rx_x4_status5_actualSpeeds_dr_20G_SCR 34 11623 #define rx_x4_status5_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 11624 #define rx_x4_status5_actualSpeeds_dr_10G_DXGXS_SCR 36 11625 #define rx_x4_status5_actualSpeeds_dr_12G_R2 37 11626 #define rx_x4_status5_actualSpeeds_dr_10G_X2 38 11627 #define rx_x4_status5_actualSpeeds_dr_40G_KR4 39 11628 #define rx_x4_status5_actualSpeeds_dr_40G_CR4 40 11629 #define rx_x4_status5_actualSpeeds_dr_100G_CR10 41 11630 #define rx_x4_status5_actualSpeeds_dr_15p75G_DXGXS 44 11631 #define rx_x4_status5_actualSpeeds_dr_20G_KR2 57 11632 #define rx_x4_status5_actualSpeeds_dr_20G_CR2 58 11633 11634 /**************************************************************************** 11635 * Enums: rx_x4_status5_actualSpeedsMisc1 11636 */ 11637 #define rx_x4_status5_actualSpeedsMisc1_dr_2500BRCM_X1 16 11638 #define rx_x4_status5_actualSpeedsMisc1_dr_5000BRCM_X4 17 11639 #define rx_x4_status5_actualSpeedsMisc1_dr_6000BRCM_X4 18 11640 #define rx_x4_status5_actualSpeedsMisc1_dr_10GHiGig_X4 19 11641 #define rx_x4_status5_actualSpeedsMisc1_dr_10GBASE_CX4 20 11642 #define rx_x4_status5_actualSpeedsMisc1_dr_12GHiGig_X4 21 11643 #define rx_x4_status5_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 11644 #define rx_x4_status5_actualSpeedsMisc1_dr_13GHiGig_X4 23 11645 #define rx_x4_status5_actualSpeedsMisc1_dr_15GHiGig_X4 24 11646 #define rx_x4_status5_actualSpeedsMisc1_dr_16GHiGig_X4 25 11647 #define rx_x4_status5_actualSpeedsMisc1_dr_5000BRCM_X1 26 11648 #define rx_x4_status5_actualSpeedsMisc1_dr_6363BRCM_X1 27 11649 #define rx_x4_status5_actualSpeedsMisc1_dr_20GHiGig_X4 28 11650 #define rx_x4_status5_actualSpeedsMisc1_dr_21GHiGig_X4 29 11651 #define rx_x4_status5_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 11652 #define rx_x4_status5_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 11653 11654 /**************************************************************************** 11655 * Enums: rx_x4_status5_IndLaneModes 11656 */ 11657 #define rx_x4_status5_IndLaneModes_SWSDR_div2 0 11658 #define rx_x4_status5_IndLaneModes_SWSDR_div1 1 11659 #define rx_x4_status5_IndLaneModes_DWSDR_div2 2 11660 #define rx_x4_status5_IndLaneModes_DWSDR_div1 3 11661 11662 /**************************************************************************** 11663 * Enums: rx_x4_status5_prbsSelect 11664 */ 11665 #define rx_x4_status5_prbsSelect_prbs7 0 11666 #define rx_x4_status5_prbsSelect_prbs15 1 11667 #define rx_x4_status5_prbsSelect_prbs23 2 11668 #define rx_x4_status5_prbsSelect_prbs31 3 11669 11670 /**************************************************************************** 11671 * Enums: rx_x4_status5_vcoDivider 11672 */ 11673 #define rx_x4_status5_vcoDivider_div32 0 11674 #define rx_x4_status5_vcoDivider_div36 1 11675 #define rx_x4_status5_vcoDivider_div40 2 11676 #define rx_x4_status5_vcoDivider_div42 3 11677 #define rx_x4_status5_vcoDivider_div48 4 11678 #define rx_x4_status5_vcoDivider_div50 5 11679 #define rx_x4_status5_vcoDivider_div52 6 11680 #define rx_x4_status5_vcoDivider_div54 7 11681 #define rx_x4_status5_vcoDivider_div60 8 11682 #define rx_x4_status5_vcoDivider_div64 9 11683 #define rx_x4_status5_vcoDivider_div66 10 11684 #define rx_x4_status5_vcoDivider_div68 11 11685 #define rx_x4_status5_vcoDivider_div70 12 11686 #define rx_x4_status5_vcoDivider_div80 13 11687 #define rx_x4_status5_vcoDivider_div92 14 11688 #define rx_x4_status5_vcoDivider_div100 15 11689 11690 /**************************************************************************** 11691 * Enums: rx_x4_status5_refClkSelect 11692 */ 11693 #define rx_x4_status5_refClkSelect_clk_156p25MHz 1 11694 #define rx_x4_status5_refClkSelect_clk_312p5Mhz 2 11695 11696 /**************************************************************************** 11697 * Enums: rx_x4_status5_aerMMDdevTypeSelect 11698 */ 11699 #define rx_x4_status5_aerMMDdevTypeSelect_combo_core 0 11700 #define rx_x4_status5_aerMMDdevTypeSelect_PMA_PMD 1 11701 #define rx_x4_status5_aerMMDdevTypeSelect_PCS 3 11702 #define rx_x4_status5_aerMMDdevTypeSelect_PHY 4 11703 #define rx_x4_status5_aerMMDdevTypeSelect_DTE 5 11704 #define rx_x4_status5_aerMMDdevTypeSelect_CL73_AN 7 11705 11706 /**************************************************************************** 11707 * Enums: rx_x4_status5_aerMMDportSelect 11708 */ 11709 #define rx_x4_status5_aerMMDportSelect_ln0 0 11710 #define rx_x4_status5_aerMMDportSelect_ln1 1 11711 #define rx_x4_status5_aerMMDportSelect_ln2 2 11712 #define rx_x4_status5_aerMMDportSelect_ln3 3 11713 #define rx_x4_status5_aerMMDportSelect_BCST_ln0_1_2_3 511 11714 #define rx_x4_status5_aerMMDportSelect_BCST_ln0_1 512 11715 #define rx_x4_status5_aerMMDportSelect_BCST_ln2_3 513 11716 11717 /**************************************************************************** 11718 * Enums: rx_x4_status5_firmwareModeSelect 11719 */ 11720 #define rx_x4_status5_firmwareModeSelect_DEFAULT 0 11721 #define rx_x4_status5_firmwareModeSelect_SFP_OPT_LR 1 11722 #define rx_x4_status5_firmwareModeSelect_SFP_DAC 2 11723 #define rx_x4_status5_firmwareModeSelect_XLAUI 3 11724 #define rx_x4_status5_firmwareModeSelect_LONG_CH_6G 4 11725 11726 /**************************************************************************** 11727 * Enums: rx_x4_status5_tempIdxSelect 11728 */ 11729 #define rx_x4_status5_tempIdxSelect_LTE__22p9C 15 11730 #define rx_x4_status5_tempIdxSelect_LTE__12p6C 14 11731 #define rx_x4_status5_tempIdxSelect_LTE__3p0C 13 11732 #define rx_x4_status5_tempIdxSelect_LTE_6p7C 12 11733 #define rx_x4_status5_tempIdxSelect_LTE_16p4C 11 11734 #define rx_x4_status5_tempIdxSelect_LTE_26p6C 10 11735 #define rx_x4_status5_tempIdxSelect_LTE_36p3C 9 11736 #define rx_x4_status5_tempIdxSelect_LTE_46p0C 8 11737 #define rx_x4_status5_tempIdxSelect_LTE_56p2C 7 11738 #define rx_x4_status5_tempIdxSelect_LTE_65p9C 6 11739 #define rx_x4_status5_tempIdxSelect_LTE_75p6C 5 11740 #define rx_x4_status5_tempIdxSelect_LTE_85p3C 4 11741 #define rx_x4_status5_tempIdxSelect_LTE_95p5C 3 11742 #define rx_x4_status5_tempIdxSelect_LTE_105p2C 2 11743 #define rx_x4_status5_tempIdxSelect_LTE_114p9C 1 11744 #define rx_x4_status5_tempIdxSelect_LTE_125p1C 0 11745 11746 /**************************************************************************** 11747 * Enums: rx_x4_status5_port_mode 11748 */ 11749 #define rx_x4_status5_port_mode_QUAD_PORT 0 11750 #define rx_x4_status5_port_mode_TRI_1_PORT 1 11751 #define rx_x4_status5_port_mode_TRI_2_PORT 2 11752 #define rx_x4_status5_port_mode_DUAL_PORT 3 11753 #define rx_x4_status5_port_mode_SINGLE_PORT 4 11754 #define rx_x4_status5_port_mode_SINGLE_OCTAL_PORT 5 11755 11756 /**************************************************************************** 11757 * Enums: rx_x4_status5_rev_letter_enum 11758 */ 11759 #define rx_x4_status5_rev_letter_enum_REV_A 0 11760 #define rx_x4_status5_rev_letter_enum_REV_B 1 11761 #define rx_x4_status5_rev_letter_enum_REV_C 2 11762 #define rx_x4_status5_rev_letter_enum_REV_D 3 11763 11764 /**************************************************************************** 11765 * Enums: rx_x4_status5_rev_number_enum 11766 */ 11767 #define rx_x4_status5_rev_number_enum_REV_0 0 11768 #define rx_x4_status5_rev_number_enum_REV_1 1 11769 #define rx_x4_status5_rev_number_enum_REV_2 2 11770 #define rx_x4_status5_rev_number_enum_REV_3 3 11771 #define rx_x4_status5_rev_number_enum_REV_4 4 11772 #define rx_x4_status5_rev_number_enum_REV_5 5 11773 #define rx_x4_status5_rev_number_enum_REV_6 6 11774 #define rx_x4_status5_rev_number_enum_REV_7 7 11775 11776 /**************************************************************************** 11777 * Enums: rx_x4_status5_bonding_enum 11778 */ 11779 #define rx_x4_status5_bonding_enum_WIRE_BOND 0 11780 #define rx_x4_status5_bonding_enum_FLIP_CHIP 1 11781 11782 /**************************************************************************** 11783 * Enums: rx_x4_status5_tech_process 11784 */ 11785 #define rx_x4_status5_tech_process_PROCESS_90NM 0 11786 #define rx_x4_status5_tech_process_PROCESS_65NM 1 11787 #define rx_x4_status5_tech_process_PROCESS_40NM 2 11788 #define rx_x4_status5_tech_process_PROCESS_28NM 3 11789 #define rx_x4_status5_tech_process_PROCESS_16NM 4 11790 11791 /**************************************************************************** 11792 * Enums: rx_x4_status5_model_num 11793 */ 11794 #define rx_x4_status5_model_num_SERDES_CL73 0 11795 #define rx_x4_status5_model_num_XGXS_16G 1 11796 #define rx_x4_status5_model_num_HYPERCORE 2 11797 #define rx_x4_status5_model_num_HYPERLITE 3 11798 #define rx_x4_status5_model_num_PCIE_G2_PIPE 4 11799 #define rx_x4_status5_model_num_SERDES_1p25GBd 5 11800 #define rx_x4_status5_model_num_SATA2 6 11801 #define rx_x4_status5_model_num_QSGMII 7 11802 #define rx_x4_status5_model_num_XGXS10G 8 11803 #define rx_x4_status5_model_num_WARPCORE 9 11804 #define rx_x4_status5_model_num_XFICORE 10 11805 #define rx_x4_status5_model_num_RXFI 11 11806 #define rx_x4_status5_model_num_WARPLITE 12 11807 #define rx_x4_status5_model_num_PENTACORE 13 11808 #define rx_x4_status5_model_num_ESM 14 11809 #define rx_x4_status5_model_num_QUAD_SGMII 15 11810 #define rx_x4_status5_model_num_WARPCORE_3 16 11811 #define rx_x4_status5_model_num_TSC 17 11812 #define rx_x4_status5_model_num_TSC4E 18 11813 #define rx_x4_status5_model_num_TSC12E 19 11814 #define rx_x4_status5_model_num_TSC4F 20 11815 #define rx_x4_status5_model_num_TSC4F_GEN2 21 11816 #define rx_x4_status5_model_num_XGXS_CL73_90NM 29 11817 #define rx_x4_status5_model_num_SERDES_CL73_90NM 30 11818 #define rx_x4_status5_model_num_WARPCORE3 32 11819 #define rx_x4_status5_model_num_WARPCORE4_TSC 33 11820 #define rx_x4_status5_model_num_RXAUI 34 11821 #define rx_x4_status5_model_num_TSCE_GEN3 35 11822 #define rx_x4_status5_model_num_TSC4F_GEN3 36 11823 #define rx_x4_status5_model_num_TSCBH 37 11824 11825 /**************************************************************************** 11826 * Enums: rx_x4_status5_payload 11827 */ 11828 #define rx_x4_status5_payload_REPEAT_2_BYTES 0 11829 #define rx_x4_status5_payload_RAMPING 1 11830 #define rx_x4_status5_payload_CL48_CRPAT 2 11831 #define rx_x4_status5_payload_CL48_CJPAT 3 11832 #define rx_x4_status5_payload_CL36_LONG_CRPAT 4 11833 #define rx_x4_status5_payload_CL36_SHORT_CRPAT 5 11834 11835 /**************************************************************************** 11836 * Enums: rx_x4_status5_sc 11837 */ 11838 #define rx_x4_status5_sc_SPEED_10G_IEEE_KR1 0 11839 #define rx_x4_status5_sc_SPEED_25G_IEEE_KS1_CS1 1 11840 #define rx_x4_status5_sc_SPEED_25G_IEEE_KR1_CR1 2 11841 #define rx_x4_status5_sc_SPEED_40G_IEEE_KR4 3 11842 #define rx_x4_status5_sc_SPEED_40G_IEEE_CR4 4 11843 #define rx_x4_status5_sc_SPEED_50G_IEEE_KR1_CR1 5 11844 #define rx_x4_status5_sc_SPEED_100G_IEEE_KR4 6 11845 #define rx_x4_status5_sc_SPEED_100G_IEEE_CR4 7 11846 #define rx_x4_status5_sc_SPEED_100G_IEEE_KR2_CR2 8 11847 #define rx_x4_status5_sc_SPEED_200G_IEEE_KR4_CR4 9 11848 #define rx_x4_status5_sc_SPEED_400G_IEEE_X8 10 11849 #define rx_x4_status5_sc_SPEED_CL73_IEEE_20GVCO 11 11850 #define rx_x4_status5_sc_SPEED_CL73_IEEE_25GVCO 12 11851 #define rx_x4_status5_sc_SPEED_CL73_IEEE_26GVCO 13 11852 #define rx_x4_status5_sc_SPEED_20G_BRCM_CR1 14 11853 #define rx_x4_status5_sc_SPEED_20G_BRCM_KR1 15 11854 #define rx_x4_status5_sc_SPEED_25G_BRCM_CR1 16 11855 #define rx_x4_status5_sc_SPEED_25G_BRCM_KR1 17 11856 #define rx_x4_status5_sc_SPEED_40G_BRCM_CR2 18 11857 #define rx_x4_status5_sc_SPEED_40G_BRCM_KR2 19 11858 #define rx_x4_status5_sc_SPEED_50G_BRCM_CR2 20 11859 #define rx_x4_status5_sc_SPEED_50G_BRCM_KR2 21 11860 #define rx_x4_status5_sc_SPEED_50G_BRCM_CR4 22 11861 #define rx_x4_status5_sc_SPEED_50G_BRCM_KR4 23 11862 #define rx_x4_status5_sc_SPEED_50G_BRCM_FEC_544_CR2_KR2 24 11863 #define rx_x4_status5_sc_SPEED_RESERVED_19 25 11864 #define rx_x4_status5_sc_SPEED_50G_BRCM_FEC_544_CR1_KR1 26 11865 #define rx_x4_status5_sc_SPEED_50G_BRCM_NO_FEC_CR1_KR1 27 11866 #define rx_x4_status5_sc_SPEED_50G_BRCM_FEC_528_CR1_KR1 28 11867 #define rx_x4_status5_sc_SPEED_400G_BRCM_NO_FEC_KR8_CR8 29 11868 #define rx_x4_status5_sc_SPEED_400G_BRCM_FEC_KR8_CR8 30 11869 #define rx_x4_status5_sc_SPEED_200G_BRCM_NO_FEC_KR4_CR4 31 11870 #define rx_x4_status5_sc_SPEED_200G_BRCM_KR4_CR4 32 11871 #define rx_x4_status5_sc_SPEED_100G_BRCM_KR4_CR4 33 11872 #define rx_x4_status5_sc_SPEED_RESERVED_22 34 11873 #define rx_x4_status5_sc_SPEED_100G_BRCM_FEC_528_KR2_CR2 35 11874 #define rx_x4_status5_sc_SPEED_100G_BRCM_NO_FEC_KR2_CR2 36 11875 #define rx_x4_status5_sc_SPEED_100G_BRCM_NO_FEC_X4 37 11876 11877 /**************************************************************************** 11878 * Enums: rx_x4_status5_t_fifo_modes 11879 */ 11880 #define rx_x4_status5_t_fifo_modes_T_FIFO_INSERT_NO_AM 0 11881 #define rx_x4_status5_t_fifo_modes_T_FIFO_INSERT_4_AM 1 11882 #define rx_x4_status5_t_fifo_modes_T_FIFO_INSERT_20_AM 2 11883 #define rx_x4_status5_t_fifo_modes_T_FIFO_INSERT_2_AM 3 11884 11885 /**************************************************************************** 11886 * Enums: rx_x4_status5_t_enc_modes 11887 */ 11888 #define rx_x4_status5_t_enc_modes_T_ENC_MODE_BYPASS 0 11889 #define rx_x4_status5_t_enc_modes_T_ENC_MODE_CL49 1 11890 #define rx_x4_status5_t_enc_modes_T_ENC_MODE_CL82 2 11891 11892 /**************************************************************************** 11893 * Enums: rx_x4_status5_btmx_mode 11894 */ 11895 #define rx_x4_status5_btmx_mode_BS_BTMX_MODE_1to1 0 11896 #define rx_x4_status5_btmx_mode_BS_BTMX_MODE_2to1 1 11897 #define rx_x4_status5_btmx_mode_BS_BTMX_MODE_5to1 2 11898 11899 /**************************************************************************** 11900 * Enums: rx_x4_status5_t_type_cl82 11901 */ 11902 #define rx_x4_status5_t_type_cl82_T_TYPE_B1 5 11903 #define rx_x4_status5_t_type_cl82_T_TYPE_C 4 11904 #define rx_x4_status5_t_type_cl82_T_TYPE_S 3 11905 #define rx_x4_status5_t_type_cl82_T_TYPE_T 2 11906 #define rx_x4_status5_t_type_cl82_T_TYPE_D 1 11907 #define rx_x4_status5_t_type_cl82_T_TYPE_E 0 11908 11909 /**************************************************************************** 11910 * Enums: rx_x4_status5_txsm_state_cl82 11911 */ 11912 #define rx_x4_status5_txsm_state_cl82_TX_E 4 11913 #define rx_x4_status5_txsm_state_cl82_TX_T 3 11914 #define rx_x4_status5_txsm_state_cl82_TX_D 2 11915 #define rx_x4_status5_txsm_state_cl82_TX_C 1 11916 #define rx_x4_status5_txsm_state_cl82_TX_INIT 0 11917 11918 /**************************************************************************** 11919 * Enums: rx_x4_status5_ltxsm_state_cl82 11920 */ 11921 #define rx_x4_status5_ltxsm_state_cl82_TX_E 16 11922 #define rx_x4_status5_ltxsm_state_cl82_TX_T 8 11923 #define rx_x4_status5_ltxsm_state_cl82_TX_D 4 11924 #define rx_x4_status5_ltxsm_state_cl82_TX_C 2 11925 #define rx_x4_status5_ltxsm_state_cl82_TX_INIT 1 11926 11927 /**************************************************************************** 11928 * Enums: rx_x4_status5_r_type_coded_cl82 11929 */ 11930 #define rx_x4_status5_r_type_coded_cl82_R_TYPE_B1 32 11931 #define rx_x4_status5_r_type_coded_cl82_R_TYPE_C 16 11932 #define rx_x4_status5_r_type_coded_cl82_R_TYPE_S 8 11933 #define rx_x4_status5_r_type_coded_cl82_R_TYPE_T 4 11934 #define rx_x4_status5_r_type_coded_cl82_R_TYPE_D 2 11935 #define rx_x4_status5_r_type_coded_cl82_R_TYPE_E 1 11936 11937 /**************************************************************************** 11938 * Enums: rx_x4_status5_rxsm_state_cl82 11939 */ 11940 #define rx_x4_status5_rxsm_state_cl82_RX_E 16 11941 #define rx_x4_status5_rxsm_state_cl82_RX_T 8 11942 #define rx_x4_status5_rxsm_state_cl82_RX_D 4 11943 #define rx_x4_status5_rxsm_state_cl82_RX_C 2 11944 #define rx_x4_status5_rxsm_state_cl82_RX_INIT 1 11945 11946 /**************************************************************************** 11947 * Enums: rx_x4_status5_deskew_state 11948 */ 11949 #define rx_x4_status5_deskew_state_ALIGN_ACQUIRED 2 11950 #define rx_x4_status5_deskew_state_LOSS_OF_ALIGNMENT 1 11951 11952 /**************************************************************************** 11953 * Enums: rx_x4_status5_os_mode_enum 11954 */ 11955 #define rx_x4_status5_os_mode_enum_OS_MODE_1 0 11956 #define rx_x4_status5_os_mode_enum_OS_MODE_2 1 11957 #define rx_x4_status5_os_mode_enum_OS_MODE_4 2 11958 #define rx_x4_status5_os_mode_enum_OS_MODE_16p5 8 11959 #define rx_x4_status5_os_mode_enum_OS_MODE_20p625 12 11960 11961 /**************************************************************************** 11962 * Enums: rx_x4_status5_scr_modes 11963 */ 11964 #define rx_x4_status5_scr_modes_T_SCR_MODE_BYPASS 0 11965 #define rx_x4_status5_scr_modes_T_SCR_MODE_CL49 1 11966 #define rx_x4_status5_scr_modes_T_SCR_MODE_40G_2_LANE 2 11967 #define rx_x4_status5_scr_modes_T_SCR_MODE_100G 3 11968 #define rx_x4_status5_scr_modes_T_SCR_MODE_20G 4 11969 #define rx_x4_status5_scr_modes_T_SCR_MODE_40G_4_LANE 5 11970 11971 /**************************************************************************** 11972 * Enums: rx_x4_status5_descr_modes 11973 */ 11974 #define rx_x4_status5_descr_modes_R_DESCR_MODE_BYPASS 0 11975 #define rx_x4_status5_descr_modes_R_DESCR_MODE_CL49 1 11976 #define rx_x4_status5_descr_modes_R_DESCR_MODE_CL82 2 11977 11978 /**************************************************************************** 11979 * Enums: rx_x4_status5_r_dec_tl_mode 11980 */ 11981 #define rx_x4_status5_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 11982 #define rx_x4_status5_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 11983 #define rx_x4_status5_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 11984 11985 /**************************************************************************** 11986 * Enums: rx_x4_status5_r_dec_fsm_mode 11987 */ 11988 #define rx_x4_status5_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 11989 #define rx_x4_status5_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 11990 #define rx_x4_status5_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 11991 11992 /**************************************************************************** 11993 * Enums: rx_x4_status5_r_deskew_mode 11994 */ 11995 #define rx_x4_status5_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 11996 #define rx_x4_status5_r_deskew_mode_R_DESKEW_MODE_20G 1 11997 #define rx_x4_status5_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 11998 #define rx_x4_status5_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 11999 #define rx_x4_status5_r_deskew_mode_R_DESKEW_MODE_100G 4 12000 #define rx_x4_status5_r_deskew_mode_R_DESKEW_MODE_CL49 5 12001 #define rx_x4_status5_r_deskew_mode_R_DESKEW_MODE_CL91_QUAD 6 12002 #define rx_x4_status5_r_deskew_mode_R_DESKEW_MODE_CL91_SINGLE_BRCM 7 12003 #define rx_x4_status5_r_deskew_mode_R_DESKEW_MODE_CL91_DUAL_BRCM 8 12004 #define rx_x4_status5_r_deskew_mode_R_DESKEW_MODE_CL91_FC 9 12005 12006 /**************************************************************************** 12007 * Enums: rx_x4_status5_bs_dist_modes 12008 */ 12009 #define rx_x4_status5_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 12010 #define rx_x4_status5_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 12011 #define rx_x4_status5_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 12012 #define rx_x4_status5_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 12013 12014 /**************************************************************************** 12015 * Enums: rx_x4_status5_cl49_t_type 12016 */ 12017 #define rx_x4_status5_cl49_t_type_BAD_T_TYPE 15 12018 #define rx_x4_status5_cl49_t_type_T_TYPE_B0 11 12019 #define rx_x4_status5_cl49_t_type_T_TYPE_OB 10 12020 #define rx_x4_status5_cl49_t_type_T_TYPE_B1 9 12021 #define rx_x4_status5_cl49_t_type_T_TYPE_DB 8 12022 #define rx_x4_status5_cl49_t_type_T_TYPE_FC 7 12023 #define rx_x4_status5_cl49_t_type_T_TYPE_TB 6 12024 #define rx_x4_status5_cl49_t_type_T_TYPE_LI 5 12025 #define rx_x4_status5_cl49_t_type_T_TYPE_C 4 12026 #define rx_x4_status5_cl49_t_type_T_TYPE_S 3 12027 #define rx_x4_status5_cl49_t_type_T_TYPE_T 2 12028 #define rx_x4_status5_cl49_t_type_T_TYPE_D 1 12029 #define rx_x4_status5_cl49_t_type_T_TYPE_E 0 12030 12031 /**************************************************************************** 12032 * Enums: rx_x4_status5_cl49_txsm_states 12033 */ 12034 #define rx_x4_status5_cl49_txsm_states_TX_LI 5 12035 #define rx_x4_status5_cl49_txsm_states_TX_E 4 12036 #define rx_x4_status5_cl49_txsm_states_TX_T 3 12037 #define rx_x4_status5_cl49_txsm_states_TX_D 2 12038 #define rx_x4_status5_cl49_txsm_states_TX_C 1 12039 #define rx_x4_status5_cl49_txsm_states_TX_INIT 0 12040 12041 /**************************************************************************** 12042 * Enums: rx_x4_status5_cl49_ltxsm_states 12043 */ 12044 #define rx_x4_status5_cl49_ltxsm_states_TX_LI 32 12045 #define rx_x4_status5_cl49_ltxsm_states_TX_E 16 12046 #define rx_x4_status5_cl49_ltxsm_states_TX_T 8 12047 #define rx_x4_status5_cl49_ltxsm_states_TX_D 4 12048 #define rx_x4_status5_cl49_ltxsm_states_TX_C 2 12049 #define rx_x4_status5_cl49_ltxsm_states_TX_INIT 1 12050 12051 /**************************************************************************** 12052 * Enums: rx_x4_status5_burst_error_mode 12053 */ 12054 #define rx_x4_status5_burst_error_mode_BURST_ERROR_11_BITS 0 12055 #define rx_x4_status5_burst_error_mode_BURST_ERROR_16_BITS 1 12056 #define rx_x4_status5_burst_error_mode_BURST_ERROR_17_BITS 2 12057 #define rx_x4_status5_burst_error_mode_BURST_ERROR_18_BITS 3 12058 #define rx_x4_status5_burst_error_mode_BURST_ERROR_19_BITS 4 12059 #define rx_x4_status5_burst_error_mode_BURST_ERROR_20_BITS 5 12060 #define rx_x4_status5_burst_error_mode_BURST_ERROR_21_BITS 6 12061 #define rx_x4_status5_burst_error_mode_BURST_ERROR_22_BITS 7 12062 #define rx_x4_status5_burst_error_mode_BURST_ERROR_23_BITS 8 12063 #define rx_x4_status5_burst_error_mode_BURST_ERROR_24_BITS 9 12064 #define rx_x4_status5_burst_error_mode_BURST_ERROR_25_BITS 10 12065 #define rx_x4_status5_burst_error_mode_BURST_ERROR_26_BITS 11 12066 #define rx_x4_status5_burst_error_mode_BURST_ERROR_27_BITS 12 12067 #define rx_x4_status5_burst_error_mode_BURST_ERROR_28_BITS 13 12068 #define rx_x4_status5_burst_error_mode_BURST_ERROR_29_BITS 14 12069 #define rx_x4_status5_burst_error_mode_BURST_ERROR_30_BITS 15 12070 #define rx_x4_status5_burst_error_mode_BURST_ERROR_31_BITS 16 12071 #define rx_x4_status5_burst_error_mode_BURST_ERROR_32_BITS 17 12072 #define rx_x4_status5_burst_error_mode_BURST_ERROR_33_BITS 18 12073 #define rx_x4_status5_burst_error_mode_BURST_ERROR_34_BITS 19 12074 #define rx_x4_status5_burst_error_mode_BURST_ERROR_35_BITS 20 12075 #define rx_x4_status5_burst_error_mode_BURST_ERROR_36_BITS 21 12076 #define rx_x4_status5_burst_error_mode_BURST_ERROR_37_BITS 22 12077 #define rx_x4_status5_burst_error_mode_BURST_ERROR_38_BITS 23 12078 #define rx_x4_status5_burst_error_mode_BURST_ERROR_39_BITS 24 12079 #define rx_x4_status5_burst_error_mode_BURST_ERROR_40_BITS 25 12080 #define rx_x4_status5_burst_error_mode_BURST_ERROR_41_BITS 26 12081 12082 /**************************************************************************** 12083 * Enums: rx_x4_status5_bermon_state 12084 */ 12085 #define rx_x4_status5_bermon_state_HI_BER 4 12086 #define rx_x4_status5_bermon_state_GOOD_BER 3 12087 #define rx_x4_status5_bermon_state_BER_TEST_SH 2 12088 #define rx_x4_status5_bermon_state_START_TIMER 1 12089 #define rx_x4_status5_bermon_state_BER_MT_INIT 0 12090 12091 /**************************************************************************** 12092 * Enums: rx_x4_status5_rxsm_state_cl49 12093 */ 12094 #define rx_x4_status5_rxsm_state_cl49_RX_LI 32 12095 #define rx_x4_status5_rxsm_state_cl49_RX_E 16 12096 #define rx_x4_status5_rxsm_state_cl49_RX_T 8 12097 #define rx_x4_status5_rxsm_state_cl49_RX_D 4 12098 #define rx_x4_status5_rxsm_state_cl49_RX_C 2 12099 #define rx_x4_status5_rxsm_state_cl49_RX_INIT 1 12100 12101 /**************************************************************************** 12102 * Enums: rx_x4_status5_r_type 12103 */ 12104 #define rx_x4_status5_r_type_BAD_R_TYPE 15 12105 #define rx_x4_status5_r_type_R_TYPE_B0 11 12106 #define rx_x4_status5_r_type_R_TYPE_OB 10 12107 #define rx_x4_status5_r_type_R_TYPE_B1 9 12108 #define rx_x4_status5_r_type_R_TYPE_DB 8 12109 #define rx_x4_status5_r_type_R_TYPE_FC 7 12110 #define rx_x4_status5_r_type_R_TYPE_TB 6 12111 #define rx_x4_status5_r_type_R_TYPE_LI 5 12112 #define rx_x4_status5_r_type_R_TYPE_C 4 12113 #define rx_x4_status5_r_type_R_TYPE_S 3 12114 #define rx_x4_status5_r_type_R_TYPE_T 2 12115 #define rx_x4_status5_r_type_R_TYPE_D 1 12116 #define rx_x4_status5_r_type_R_TYPE_E 0 12117 12118 /**************************************************************************** 12119 * Enums: rx_x4_status5_am_lock_state 12120 */ 12121 #define rx_x4_status5_am_lock_state_INVALID_AM 512 12122 #define rx_x4_status5_am_lock_state_GOOD_AM 256 12123 #define rx_x4_status5_am_lock_state_COMP_AM 128 12124 #define rx_x4_status5_am_lock_state_TIMER_2 64 12125 #define rx_x4_status5_am_lock_state_AM_2_GOOD 32 12126 #define rx_x4_status5_am_lock_state_COMP_2ND 16 12127 #define rx_x4_status5_am_lock_state_TIMER_1 8 12128 #define rx_x4_status5_am_lock_state_FIND_1ST 4 12129 #define rx_x4_status5_am_lock_state_AM_RESET_CNT 2 12130 #define rx_x4_status5_am_lock_state_AM_LOCK_INIT 1 12131 12132 /**************************************************************************** 12133 * Enums: rx_x4_status5_msg_selector 12134 */ 12135 #define rx_x4_status5_msg_selector_RESERVED 0 12136 #define rx_x4_status5_msg_selector_VALUE_802p3 1 12137 #define rx_x4_status5_msg_selector_VALUE_802p9 2 12138 #define rx_x4_status5_msg_selector_VALUE_802p5 3 12139 #define rx_x4_status5_msg_selector_VALUE_1394 4 12140 12141 /**************************************************************************** 12142 * Enums: rx_x4_status5_synce_enum_stage1 12143 */ 12144 #define rx_x4_status5_synce_enum_stage1_SYNCE_NO_DIV 0 12145 #define rx_x4_status5_synce_enum_stage1_SYNCE_DIV_7 1 12146 #define rx_x4_status5_synce_enum_stage1_SYNCE_DIV_11 2 12147 12148 /**************************************************************************** 12149 * Enums: rx_x4_status5_synce_enum_stage0 12150 */ 12151 #define rx_x4_status5_synce_enum_stage0_SYNCE_NO_DIV 0 12152 #define rx_x4_status5_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 12153 #define rx_x4_status5_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 12154 12155 /**************************************************************************** 12156 * Enums: rx_x4_status5_cl91_sync_state 12157 */ 12158 #define rx_x4_status5_cl91_sync_state_FIND_1ST 0 12159 #define rx_x4_status5_cl91_sync_state_COUNT_NEXT 1 12160 #define rx_x4_status5_cl91_sync_state_COMP_2ND 2 12161 #define rx_x4_status5_cl91_sync_state_TWO_GOOD 3 12162 12163 /**************************************************************************** 12164 * Enums: rx_x4_status5_RS_FEC_sync_state 12165 */ 12166 #define rx_x4_status5_RS_FEC_sync_state_LOCK_INIT 0 12167 #define rx_x4_status5_RS_FEC_sync_state_FIND_1ST 1 12168 #define rx_x4_status5_RS_FEC_sync_state_COUNT_NEXT 2 12169 #define rx_x4_status5_RS_FEC_sync_state_COMP_2ND 3 12170 #define rx_x4_status5_RS_FEC_sync_state_TWO_GOOD 4 12171 12172 /**************************************************************************** 12173 * Enums: rx_x4_status5_cl91_algn_state 12174 */ 12175 #define rx_x4_status5_cl91_algn_state_LOSS_OF_ALIGNMENT 0 12176 #define rx_x4_status5_cl91_algn_state_DESKEW 1 12177 #define rx_x4_status5_cl91_algn_state_DESKEW_FAIL 2 12178 #define rx_x4_status5_cl91_algn_state_ALIGN_ACQUIRED 3 12179 #define rx_x4_status5_cl91_algn_state_CW_GOOD 4 12180 #define rx_x4_status5_cl91_algn_state_CW_BAD 5 12181 #define rx_x4_status5_cl91_algn_state_THREE_BAD 6 12182 12183 /**************************************************************************** 12184 * Enums: rx_x4_status5_RS_FEC_algn_state 12185 */ 12186 #define rx_x4_status5_RS_FEC_algn_state_LOSS_OF_ALIGNMENT 0 12187 #define rx_x4_status5_RS_FEC_algn_state_DESKEW 1 12188 #define rx_x4_status5_RS_FEC_algn_state_DESKEW_FAIL 2 12189 #define rx_x4_status5_RS_FEC_algn_state_ALIGN_ACQUIRED 3 12190 #define rx_x4_status5_RS_FEC_algn_state_CW_GOOD 4 12191 #define rx_x4_status5_RS_FEC_algn_state_CW_BAD 5 12192 #define rx_x4_status5_RS_FEC_algn_state_THREE_BAD 6 12193 12194 /**************************************************************************** 12195 * Enums: rx_x4_status5_fec_sel_override 12196 */ 12197 #define rx_x4_status5_fec_sel_override_NO_OVERRIDE 0 12198 #define rx_x4_status5_fec_sel_override_NO_FEC 1 12199 #define rx_x4_status5_fec_sel_override_FEC_CL74 2 12200 #define rx_x4_status5_fec_sel_override_FEC_CL91 3 12201 12202 /**************************************************************************** 12203 * Enums: rx_x4_status5_cl91_blksync_mode 12204 */ 12205 #define rx_x4_status5_cl91_blksync_mode_R_BLKSYNC_NO_CL91_FEC 0 12206 #define rx_x4_status5_cl91_blksync_mode_R_BLKSYNC_CL91_QUAD_LANE_FEC 1 12207 #define rx_x4_status5_cl91_blksync_mode_R_BLKSYNC_CL91_DUAL_LANE_FEC 2 12208 #define rx_x4_status5_cl91_blksync_mode_R_BLKSYNC_CL91_SINGLE_LANE_FEC 3 12209 #define rx_x4_status5_cl91_blksync_mode_R_BLKSYNC_CL91_FC_FEC 4 12210 12211 /**************************************************************************** 12212 * Enums: rx_x4_status5_r_merge_mode 12213 */ 12214 #define rx_x4_status5_r_merge_mode_R_MERGE_MODE_BYPASS 0 12215 #define rx_x4_status5_r_merge_mode_R_MERGE_MODE_CL91_FC 1 12216 #define rx_x4_status5_r_merge_mode_R_MERGE_MODE_CL91_SINGLE_LANE 2 12217 #define rx_x4_status5_r_merge_mode_R_MERGE_MODE_CL91_DUAL_LANE 3 12218 #define rx_x4_status5_r_merge_mode_R_MERGE_MODE_CL91_QUAD_LANE 4 12219 12220 /**************************************************************************** 12221 * Enums: rx_x4_status5_r_tc_mode 12222 */ 12223 #define rx_x4_status5_r_tc_mode_R_TC_MODE_SINGLE 0 12224 #define rx_x4_status5_r_tc_mode_R_TC_MODE_DUAL 1 12225 #define rx_x4_status5_r_tc_mode_R_TC_MODE_QUAD 2 12226 12227 /**************************************************************************** 12228 * Enums: rx_x4_status5_r_tc_out_mode 12229 */ 12230 #define rx_x4_status5_r_tc_out_mode_R_TC_OUT_MODE_SINGLE 0 12231 #define rx_x4_status5_r_tc_out_mode_R_TC_OUT_MODE_DUAL 1 12232 #define rx_x4_status5_r_tc_out_mode_R_TC_OUT_MODE_QUAD 2 12233 12234 /**************************************************************************** 12235 * Enums: rx_x4_status5_cl91_fec_mode 12236 */ 12237 #define rx_x4_status5_cl91_fec_mode_NO_CL91_FEC 0 12238 #define rx_x4_status5_cl91_fec_mode_CL91_SINGLE_LANE_FC 1 12239 #define rx_x4_status5_cl91_fec_mode_CL91_SINGLE_LANE_BRCM_PROP 2 12240 #define rx_x4_status5_cl91_fec_mode_CL91_DUAL_LANE_BRCM_PROP 3 12241 #define rx_x4_status5_cl91_fec_mode_CL91_QUAD_LANE 4 12242 #define rx_x4_status5_cl91_fec_mode_IEEE_25G_CL91_SINGLE_LANE 5 12243 12244 /**************************************************************************** 12245 * Enums: rx_x4_status5_RS_FEC_fec_mode 12246 */ 12247 #define rx_x4_status5_RS_FEC_fec_mode_NO_RS_FEC_FEC 0 12248 #define rx_x4_status5_RS_FEC_fec_mode_N_A 1 12249 #define rx_x4_status5_RS_FEC_fec_mode_RS_FEC_SINGLE_LANE_BRCM_PROP 2 12250 #define rx_x4_status5_RS_FEC_fec_mode_RS_FEC_DUAL_LANE_BRCM_PROP 3 12251 #define rx_x4_status5_RS_FEC_fec_mode_RS_FEC_QUAD_LANE 4 12252 #define rx_x4_status5_RS_FEC_fec_mode_IEEE_25G_RS_FEC_SINGLE_LANE 5 12253 12254 /**************************************************************************** 12255 * Enums: rx_x4_status5_am_spacing_mul 12256 */ 12257 #define rx_x4_status5_am_spacing_mul_AM_SPACING_MUL_2 0 12258 #define rx_x4_status5_am_spacing_mul_AM_SPACING_MUL_4 1 12259 #define rx_x4_status5_am_spacing_mul_AM_SPACING_MUL_5 2 12260 #define rx_x4_status5_am_spacing_mul_AM_SPACING_MUL_20 3 12261 12262 /**************************************************************************** 12263 * Enums: sc_x4_control_cl36TxEEEStates_l 12264 */ 12265 #define sc_x4_control_cl36TxEEEStates_l_TX_REFRESH 8 12266 #define sc_x4_control_cl36TxEEEStates_l_TX_QUIET 4 12267 #define sc_x4_control_cl36TxEEEStates_l_TX_SLEEP 2 12268 #define sc_x4_control_cl36TxEEEStates_l_TX_ACTIVE 1 12269 12270 /**************************************************************************** 12271 * Enums: sc_x4_control_cl36TxEEEStates_c 12272 */ 12273 #define sc_x4_control_cl36TxEEEStates_c_TX_REFRESH 3 12274 #define sc_x4_control_cl36TxEEEStates_c_TX_QUIET 2 12275 #define sc_x4_control_cl36TxEEEStates_c_TX_SLEEP 1 12276 #define sc_x4_control_cl36TxEEEStates_c_TX_ACTIVE 0 12277 12278 /**************************************************************************** 12279 * Enums: sc_x4_control_cl49TxEEEStates_l 12280 */ 12281 #define sc_x4_control_cl49TxEEEStates_l_SCR_RESET_2 64 12282 #define sc_x4_control_cl49TxEEEStates_l_SCR_RESET_1 32 12283 #define sc_x4_control_cl49TxEEEStates_l_TX_WAKE 16 12284 #define sc_x4_control_cl49TxEEEStates_l_TX_REFRESH 8 12285 #define sc_x4_control_cl49TxEEEStates_l_TX_QUIET 4 12286 #define sc_x4_control_cl49TxEEEStates_l_TX_SLEEP 2 12287 #define sc_x4_control_cl49TxEEEStates_l_TX_ACTIVE 1 12288 12289 /**************************************************************************** 12290 * Enums: sc_x4_control_fec_req_enum 12291 */ 12292 #define sc_x4_control_fec_req_enum_FEC_not_supported 0 12293 #define sc_x4_control_fec_req_enum_FEC_supported_but_not_requested 1 12294 #define sc_x4_control_fec_req_enum_invalid_setting 2 12295 #define sc_x4_control_fec_req_enum_FEC_supported_and_requested 3 12296 12297 /**************************************************************************** 12298 * Enums: sc_x4_control_cl73_pause_enum 12299 */ 12300 #define sc_x4_control_cl73_pause_enum_No_PAUSE_ability 0 12301 #define sc_x4_control_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 12302 #define sc_x4_control_cl73_pause_enum_Symmetric_PAUSE_ability 1 12303 #define sc_x4_control_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 12304 12305 /**************************************************************************** 12306 * Enums: sc_x4_control_cl49TxEEEStates_c 12307 */ 12308 #define sc_x4_control_cl49TxEEEStates_c_SCR_RESET_2 6 12309 #define sc_x4_control_cl49TxEEEStates_c_SCR_RESET_1 5 12310 #define sc_x4_control_cl49TxEEEStates_c_TX_WAKE 4 12311 #define sc_x4_control_cl49TxEEEStates_c_TX_REFRESH 3 12312 #define sc_x4_control_cl49TxEEEStates_c_TX_QUIET 2 12313 #define sc_x4_control_cl49TxEEEStates_c_TX_SLEEP 1 12314 #define sc_x4_control_cl49TxEEEStates_c_TX_ACTIVE 0 12315 12316 /**************************************************************************** 12317 * Enums: sc_x4_control_cl36RxEEEStates_l 12318 */ 12319 #define sc_x4_control_cl36RxEEEStates_l_RX_LINK_FAIL 32 12320 #define sc_x4_control_cl36RxEEEStates_l_RX_WTF 16 12321 #define sc_x4_control_cl36RxEEEStates_l_RX_WAKE 8 12322 #define sc_x4_control_cl36RxEEEStates_l_RX_QUIET 4 12323 #define sc_x4_control_cl36RxEEEStates_l_RX_SLEEP 2 12324 #define sc_x4_control_cl36RxEEEStates_l_RX_ACTIVE 1 12325 12326 /**************************************************************************** 12327 * Enums: sc_x4_control_cl36RxEEEStates_c 12328 */ 12329 #define sc_x4_control_cl36RxEEEStates_c_RX_LINK_FAIL 5 12330 #define sc_x4_control_cl36RxEEEStates_c_RX_WTF 4 12331 #define sc_x4_control_cl36RxEEEStates_c_RX_WAKE 3 12332 #define sc_x4_control_cl36RxEEEStates_c_RX_QUIET 2 12333 #define sc_x4_control_cl36RxEEEStates_c_RX_SLEEP 1 12334 #define sc_x4_control_cl36RxEEEStates_c_RX_ACTIVE 0 12335 12336 /**************************************************************************** 12337 * Enums: sc_x4_control_cl49RxEEEStates_l 12338 */ 12339 #define sc_x4_control_cl49RxEEEStates_l_RX_LINK_FAIL 32 12340 #define sc_x4_control_cl49RxEEEStates_l_RX_WTF 16 12341 #define sc_x4_control_cl49RxEEEStates_l_RX_WAKE 8 12342 #define sc_x4_control_cl49RxEEEStates_l_RX_QUIET 4 12343 #define sc_x4_control_cl49RxEEEStates_l_RX_SLEEP 2 12344 #define sc_x4_control_cl49RxEEEStates_l_RX_ACTIVE 1 12345 12346 /**************************************************************************** 12347 * Enums: sc_x4_control_cl49RxEEEStates_c 12348 */ 12349 #define sc_x4_control_cl49RxEEEStates_c_RX_LINK_FAIL 5 12350 #define sc_x4_control_cl49RxEEEStates_c_RX_WTF 4 12351 #define sc_x4_control_cl49RxEEEStates_c_RX_WAKE 3 12352 #define sc_x4_control_cl49RxEEEStates_c_RX_QUIET 2 12353 #define sc_x4_control_cl49RxEEEStates_c_RX_SLEEP 1 12354 #define sc_x4_control_cl49RxEEEStates_c_RX_ACTIVE 0 12355 12356 /**************************************************************************** 12357 * Enums: sc_x4_control_cl48TxEEEStates_l 12358 */ 12359 #define sc_x4_control_cl48TxEEEStates_l_TX_REFRESH 8 12360 #define sc_x4_control_cl48TxEEEStates_l_TX_QUIET 4 12361 #define sc_x4_control_cl48TxEEEStates_l_TX_SLEEP 2 12362 #define sc_x4_control_cl48TxEEEStates_l_TX_ACTIVE 1 12363 12364 /**************************************************************************** 12365 * Enums: sc_x4_control_cl48TxEEEStates_c 12366 */ 12367 #define sc_x4_control_cl48TxEEEStates_c_TX_REFRESH 3 12368 #define sc_x4_control_cl48TxEEEStates_c_TX_QUIET 2 12369 #define sc_x4_control_cl48TxEEEStates_c_TX_SLEEP 1 12370 #define sc_x4_control_cl48TxEEEStates_c_TX_ACTIVE 0 12371 12372 /**************************************************************************** 12373 * Enums: sc_x4_control_cl48RxEEEStates_l 12374 */ 12375 #define sc_x4_control_cl48RxEEEStates_l_RX_LINK_FAIL 32 12376 #define sc_x4_control_cl48RxEEEStates_l_RX_WAKE 16 12377 #define sc_x4_control_cl48RxEEEStates_l_RX_QUIET 8 12378 #define sc_x4_control_cl48RxEEEStates_l_RX_DEACT 4 12379 #define sc_x4_control_cl48RxEEEStates_l_RX_SLEEP 2 12380 #define sc_x4_control_cl48RxEEEStates_l_RX_ACTIVE 1 12381 12382 /**************************************************************************** 12383 * Enums: sc_x4_control_cl48RxEEEStates_c 12384 */ 12385 #define sc_x4_control_cl48RxEEEStates_c_RX_LINK_FAIL 5 12386 #define sc_x4_control_cl48RxEEEStates_c_RX_WAKE 4 12387 #define sc_x4_control_cl48RxEEEStates_c_RX_QUIET 3 12388 #define sc_x4_control_cl48RxEEEStates_c_RX_DEACT 2 12389 #define sc_x4_control_cl48RxEEEStates_c_RX_SLEEP 1 12390 #define sc_x4_control_cl48RxEEEStates_c_RX_ACTIVE 0 12391 12392 /**************************************************************************** 12393 * Enums: sc_x4_control_IQP_Options 12394 */ 12395 #define sc_x4_control_IQP_Options_i50uA 0 12396 #define sc_x4_control_IQP_Options_i100uA 1 12397 #define sc_x4_control_IQP_Options_i150uA 2 12398 #define sc_x4_control_IQP_Options_i200uA 3 12399 #define sc_x4_control_IQP_Options_i250uA 4 12400 #define sc_x4_control_IQP_Options_i300uA 5 12401 #define sc_x4_control_IQP_Options_i350uA 6 12402 #define sc_x4_control_IQP_Options_i400uA 7 12403 #define sc_x4_control_IQP_Options_i450uA 8 12404 #define sc_x4_control_IQP_Options_i500uA 9 12405 #define sc_x4_control_IQP_Options_i550uA 10 12406 #define sc_x4_control_IQP_Options_i600uA 11 12407 #define sc_x4_control_IQP_Options_i650uA 12 12408 #define sc_x4_control_IQP_Options_i700uA 13 12409 #define sc_x4_control_IQP_Options_i750uA 14 12410 #define sc_x4_control_IQP_Options_i800uA 15 12411 12412 /**************************************************************************** 12413 * Enums: sc_x4_control_IDriver_Options 12414 */ 12415 #define sc_x4_control_IDriver_Options_v680mV 0 12416 #define sc_x4_control_IDriver_Options_v730mV 1 12417 #define sc_x4_control_IDriver_Options_v780mV 2 12418 #define sc_x4_control_IDriver_Options_v830mV 3 12419 #define sc_x4_control_IDriver_Options_v880mV 4 12420 #define sc_x4_control_IDriver_Options_v930mV 5 12421 #define sc_x4_control_IDriver_Options_v980mV 6 12422 #define sc_x4_control_IDriver_Options_v1010mV 7 12423 #define sc_x4_control_IDriver_Options_v1040mV 8 12424 #define sc_x4_control_IDriver_Options_v1060mV 9 12425 #define sc_x4_control_IDriver_Options_v1070mV 10 12426 #define sc_x4_control_IDriver_Options_v1080mV 11 12427 #define sc_x4_control_IDriver_Options_v1085mV 12 12428 #define sc_x4_control_IDriver_Options_v1090mV 13 12429 #define sc_x4_control_IDriver_Options_v1095mV 14 12430 #define sc_x4_control_IDriver_Options_v1100mV 15 12431 12432 /**************************************************************************** 12433 * Enums: sc_x4_control_operationModes 12434 */ 12435 #define sc_x4_control_operationModes_XGXS 0 12436 #define sc_x4_control_operationModes_XGXG_nCC 1 12437 #define sc_x4_control_operationModes_Indlane_OS8 4 12438 #define sc_x4_control_operationModes_IndLane_OS5 5 12439 #define sc_x4_control_operationModes_PCI 7 12440 #define sc_x4_control_operationModes_XGXS_nLQ 8 12441 #define sc_x4_control_operationModes_XGXS_nLQnCC 9 12442 #define sc_x4_control_operationModes_PBypass 10 12443 #define sc_x4_control_operationModes_PBypass_nDSK 11 12444 #define sc_x4_control_operationModes_ComboCoreMode 12 12445 #define sc_x4_control_operationModes_Clocks_off 15 12446 12447 /**************************************************************************** 12448 * Enums: sc_x4_control_actualSpeeds 12449 */ 12450 #define sc_x4_control_actualSpeeds_dr_10M 0 12451 #define sc_x4_control_actualSpeeds_dr_100M 1 12452 #define sc_x4_control_actualSpeeds_dr_1G 2 12453 #define sc_x4_control_actualSpeeds_dr_2p5G 3 12454 #define sc_x4_control_actualSpeeds_dr_5G_X4 4 12455 #define sc_x4_control_actualSpeeds_dr_6G_X4 5 12456 #define sc_x4_control_actualSpeeds_dr_10G_HiG 6 12457 #define sc_x4_control_actualSpeeds_dr_10G_CX4 7 12458 #define sc_x4_control_actualSpeeds_dr_12G_HiG 8 12459 #define sc_x4_control_actualSpeeds_dr_12p5G_X4 9 12460 #define sc_x4_control_actualSpeeds_dr_13G_X4 10 12461 #define sc_x4_control_actualSpeeds_dr_15G_X4 11 12462 #define sc_x4_control_actualSpeeds_dr_16G_X4 12 12463 #define sc_x4_control_actualSpeeds_dr_1G_KX 13 12464 #define sc_x4_control_actualSpeeds_dr_10G_KX4 14 12465 #define sc_x4_control_actualSpeeds_dr_10G_KR 15 12466 #define sc_x4_control_actualSpeeds_dr_5G 16 12467 #define sc_x4_control_actualSpeeds_dr_6p4G 17 12468 #define sc_x4_control_actualSpeeds_dr_20G_X4 18 12469 #define sc_x4_control_actualSpeeds_dr_21G_X4 19 12470 #define sc_x4_control_actualSpeeds_dr_25G_X4 20 12471 #define sc_x4_control_actualSpeeds_dr_10G_HiG_DXGXS 21 12472 #define sc_x4_control_actualSpeeds_dr_10G_DXGXS 22 12473 #define sc_x4_control_actualSpeeds_dr_10p5G_HiG_DXGXS 23 12474 #define sc_x4_control_actualSpeeds_dr_10p5G_DXGXS 24 12475 #define sc_x4_control_actualSpeeds_dr_12p773G_HiG_DXGXS 25 12476 #define sc_x4_control_actualSpeeds_dr_12p773G_DXGXS 26 12477 #define sc_x4_control_actualSpeeds_dr_10G_XFI 27 12478 #define sc_x4_control_actualSpeeds_dr_40G 28 12479 #define sc_x4_control_actualSpeeds_dr_20G_HiG_DXGXS 29 12480 #define sc_x4_control_actualSpeeds_dr_20G_DXGXS 30 12481 #define sc_x4_control_actualSpeeds_dr_10G_SFI 31 12482 #define sc_x4_control_actualSpeeds_dr_31p5G 32 12483 #define sc_x4_control_actualSpeeds_dr_32p7G 33 12484 #define sc_x4_control_actualSpeeds_dr_20G_SCR 34 12485 #define sc_x4_control_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 12486 #define sc_x4_control_actualSpeeds_dr_10G_DXGXS_SCR 36 12487 #define sc_x4_control_actualSpeeds_dr_12G_R2 37 12488 #define sc_x4_control_actualSpeeds_dr_10G_X2 38 12489 #define sc_x4_control_actualSpeeds_dr_40G_KR4 39 12490 #define sc_x4_control_actualSpeeds_dr_40G_CR4 40 12491 #define sc_x4_control_actualSpeeds_dr_100G_CR10 41 12492 #define sc_x4_control_actualSpeeds_dr_15p75G_DXGXS 44 12493 #define sc_x4_control_actualSpeeds_dr_20G_KR2 57 12494 #define sc_x4_control_actualSpeeds_dr_20G_CR2 58 12495 12496 /**************************************************************************** 12497 * Enums: sc_x4_control_actualSpeedsMisc1 12498 */ 12499 #define sc_x4_control_actualSpeedsMisc1_dr_2500BRCM_X1 16 12500 #define sc_x4_control_actualSpeedsMisc1_dr_5000BRCM_X4 17 12501 #define sc_x4_control_actualSpeedsMisc1_dr_6000BRCM_X4 18 12502 #define sc_x4_control_actualSpeedsMisc1_dr_10GHiGig_X4 19 12503 #define sc_x4_control_actualSpeedsMisc1_dr_10GBASE_CX4 20 12504 #define sc_x4_control_actualSpeedsMisc1_dr_12GHiGig_X4 21 12505 #define sc_x4_control_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 12506 #define sc_x4_control_actualSpeedsMisc1_dr_13GHiGig_X4 23 12507 #define sc_x4_control_actualSpeedsMisc1_dr_15GHiGig_X4 24 12508 #define sc_x4_control_actualSpeedsMisc1_dr_16GHiGig_X4 25 12509 #define sc_x4_control_actualSpeedsMisc1_dr_5000BRCM_X1 26 12510 #define sc_x4_control_actualSpeedsMisc1_dr_6363BRCM_X1 27 12511 #define sc_x4_control_actualSpeedsMisc1_dr_20GHiGig_X4 28 12512 #define sc_x4_control_actualSpeedsMisc1_dr_21GHiGig_X4 29 12513 #define sc_x4_control_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 12514 #define sc_x4_control_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 12515 12516 /**************************************************************************** 12517 * Enums: sc_x4_control_IndLaneModes 12518 */ 12519 #define sc_x4_control_IndLaneModes_SWSDR_div2 0 12520 #define sc_x4_control_IndLaneModes_SWSDR_div1 1 12521 #define sc_x4_control_IndLaneModes_DWSDR_div2 2 12522 #define sc_x4_control_IndLaneModes_DWSDR_div1 3 12523 12524 /**************************************************************************** 12525 * Enums: sc_x4_control_prbsSelect 12526 */ 12527 #define sc_x4_control_prbsSelect_prbs7 0 12528 #define sc_x4_control_prbsSelect_prbs15 1 12529 #define sc_x4_control_prbsSelect_prbs23 2 12530 #define sc_x4_control_prbsSelect_prbs31 3 12531 12532 /**************************************************************************** 12533 * Enums: sc_x4_control_vcoDivider 12534 */ 12535 #define sc_x4_control_vcoDivider_div32 0 12536 #define sc_x4_control_vcoDivider_div36 1 12537 #define sc_x4_control_vcoDivider_div40 2 12538 #define sc_x4_control_vcoDivider_div42 3 12539 #define sc_x4_control_vcoDivider_div48 4 12540 #define sc_x4_control_vcoDivider_div50 5 12541 #define sc_x4_control_vcoDivider_div52 6 12542 #define sc_x4_control_vcoDivider_div54 7 12543 #define sc_x4_control_vcoDivider_div60 8 12544 #define sc_x4_control_vcoDivider_div64 9 12545 #define sc_x4_control_vcoDivider_div66 10 12546 #define sc_x4_control_vcoDivider_div68 11 12547 #define sc_x4_control_vcoDivider_div70 12 12548 #define sc_x4_control_vcoDivider_div80 13 12549 #define sc_x4_control_vcoDivider_div92 14 12550 #define sc_x4_control_vcoDivider_div100 15 12551 12552 /**************************************************************************** 12553 * Enums: sc_x4_control_refClkSelect 12554 */ 12555 #define sc_x4_control_refClkSelect_clk_156p25MHz 1 12556 #define sc_x4_control_refClkSelect_clk_312p5Mhz 2 12557 12558 /**************************************************************************** 12559 * Enums: sc_x4_control_aerMMDdevTypeSelect 12560 */ 12561 #define sc_x4_control_aerMMDdevTypeSelect_combo_core 0 12562 #define sc_x4_control_aerMMDdevTypeSelect_PMA_PMD 1 12563 #define sc_x4_control_aerMMDdevTypeSelect_PCS 3 12564 #define sc_x4_control_aerMMDdevTypeSelect_PHY 4 12565 #define sc_x4_control_aerMMDdevTypeSelect_DTE 5 12566 #define sc_x4_control_aerMMDdevTypeSelect_CL73_AN 7 12567 12568 /**************************************************************************** 12569 * Enums: sc_x4_control_aerMMDportSelect 12570 */ 12571 #define sc_x4_control_aerMMDportSelect_ln0 0 12572 #define sc_x4_control_aerMMDportSelect_ln1 1 12573 #define sc_x4_control_aerMMDportSelect_ln2 2 12574 #define sc_x4_control_aerMMDportSelect_ln3 3 12575 #define sc_x4_control_aerMMDportSelect_BCST_ln0_1_2_3 511 12576 #define sc_x4_control_aerMMDportSelect_BCST_ln0_1 512 12577 #define sc_x4_control_aerMMDportSelect_BCST_ln2_3 513 12578 12579 /**************************************************************************** 12580 * Enums: sc_x4_control_firmwareModeSelect 12581 */ 12582 #define sc_x4_control_firmwareModeSelect_DEFAULT 0 12583 #define sc_x4_control_firmwareModeSelect_SFP_OPT_LR 1 12584 #define sc_x4_control_firmwareModeSelect_SFP_DAC 2 12585 #define sc_x4_control_firmwareModeSelect_XLAUI 3 12586 #define sc_x4_control_firmwareModeSelect_LONG_CH_6G 4 12587 12588 /**************************************************************************** 12589 * Enums: sc_x4_control_tempIdxSelect 12590 */ 12591 #define sc_x4_control_tempIdxSelect_LTE__22p9C 15 12592 #define sc_x4_control_tempIdxSelect_LTE__12p6C 14 12593 #define sc_x4_control_tempIdxSelect_LTE__3p0C 13 12594 #define sc_x4_control_tempIdxSelect_LTE_6p7C 12 12595 #define sc_x4_control_tempIdxSelect_LTE_16p4C 11 12596 #define sc_x4_control_tempIdxSelect_LTE_26p6C 10 12597 #define sc_x4_control_tempIdxSelect_LTE_36p3C 9 12598 #define sc_x4_control_tempIdxSelect_LTE_46p0C 8 12599 #define sc_x4_control_tempIdxSelect_LTE_56p2C 7 12600 #define sc_x4_control_tempIdxSelect_LTE_65p9C 6 12601 #define sc_x4_control_tempIdxSelect_LTE_75p6C 5 12602 #define sc_x4_control_tempIdxSelect_LTE_85p3C 4 12603 #define sc_x4_control_tempIdxSelect_LTE_95p5C 3 12604 #define sc_x4_control_tempIdxSelect_LTE_105p2C 2 12605 #define sc_x4_control_tempIdxSelect_LTE_114p9C 1 12606 #define sc_x4_control_tempIdxSelect_LTE_125p1C 0 12607 12608 /**************************************************************************** 12609 * Enums: sc_x4_control_port_mode 12610 */ 12611 #define sc_x4_control_port_mode_QUAD_PORT 0 12612 #define sc_x4_control_port_mode_TRI_1_PORT 1 12613 #define sc_x4_control_port_mode_TRI_2_PORT 2 12614 #define sc_x4_control_port_mode_DUAL_PORT 3 12615 #define sc_x4_control_port_mode_SINGLE_PORT 4 12616 #define sc_x4_control_port_mode_SINGLE_OCTAL_PORT 5 12617 12618 /**************************************************************************** 12619 * Enums: sc_x4_control_rev_letter_enum 12620 */ 12621 #define sc_x4_control_rev_letter_enum_REV_A 0 12622 #define sc_x4_control_rev_letter_enum_REV_B 1 12623 #define sc_x4_control_rev_letter_enum_REV_C 2 12624 #define sc_x4_control_rev_letter_enum_REV_D 3 12625 12626 /**************************************************************************** 12627 * Enums: sc_x4_control_rev_number_enum 12628 */ 12629 #define sc_x4_control_rev_number_enum_REV_0 0 12630 #define sc_x4_control_rev_number_enum_REV_1 1 12631 #define sc_x4_control_rev_number_enum_REV_2 2 12632 #define sc_x4_control_rev_number_enum_REV_3 3 12633 #define sc_x4_control_rev_number_enum_REV_4 4 12634 #define sc_x4_control_rev_number_enum_REV_5 5 12635 #define sc_x4_control_rev_number_enum_REV_6 6 12636 #define sc_x4_control_rev_number_enum_REV_7 7 12637 12638 /**************************************************************************** 12639 * Enums: sc_x4_control_bonding_enum 12640 */ 12641 #define sc_x4_control_bonding_enum_WIRE_BOND 0 12642 #define sc_x4_control_bonding_enum_FLIP_CHIP 1 12643 12644 /**************************************************************************** 12645 * Enums: sc_x4_control_tech_process 12646 */ 12647 #define sc_x4_control_tech_process_PROCESS_90NM 0 12648 #define sc_x4_control_tech_process_PROCESS_65NM 1 12649 #define sc_x4_control_tech_process_PROCESS_40NM 2 12650 #define sc_x4_control_tech_process_PROCESS_28NM 3 12651 #define sc_x4_control_tech_process_PROCESS_16NM 4 12652 12653 /**************************************************************************** 12654 * Enums: sc_x4_control_model_num 12655 */ 12656 #define sc_x4_control_model_num_SERDES_CL73 0 12657 #define sc_x4_control_model_num_XGXS_16G 1 12658 #define sc_x4_control_model_num_HYPERCORE 2 12659 #define sc_x4_control_model_num_HYPERLITE 3 12660 #define sc_x4_control_model_num_PCIE_G2_PIPE 4 12661 #define sc_x4_control_model_num_SERDES_1p25GBd 5 12662 #define sc_x4_control_model_num_SATA2 6 12663 #define sc_x4_control_model_num_QSGMII 7 12664 #define sc_x4_control_model_num_XGXS10G 8 12665 #define sc_x4_control_model_num_WARPCORE 9 12666 #define sc_x4_control_model_num_XFICORE 10 12667 #define sc_x4_control_model_num_RXFI 11 12668 #define sc_x4_control_model_num_WARPLITE 12 12669 #define sc_x4_control_model_num_PENTACORE 13 12670 #define sc_x4_control_model_num_ESM 14 12671 #define sc_x4_control_model_num_QUAD_SGMII 15 12672 #define sc_x4_control_model_num_WARPCORE_3 16 12673 #define sc_x4_control_model_num_TSC 17 12674 #define sc_x4_control_model_num_TSC4E 18 12675 #define sc_x4_control_model_num_TSC12E 19 12676 #define sc_x4_control_model_num_TSC4F 20 12677 #define sc_x4_control_model_num_TSC4F_GEN2 21 12678 #define sc_x4_control_model_num_XGXS_CL73_90NM 29 12679 #define sc_x4_control_model_num_SERDES_CL73_90NM 30 12680 #define sc_x4_control_model_num_WARPCORE3 32 12681 #define sc_x4_control_model_num_WARPCORE4_TSC 33 12682 #define sc_x4_control_model_num_RXAUI 34 12683 #define sc_x4_control_model_num_TSCE_GEN3 35 12684 #define sc_x4_control_model_num_TSC4F_GEN3 36 12685 #define sc_x4_control_model_num_TSCBH 37 12686 12687 /**************************************************************************** 12688 * Enums: sc_x4_control_payload 12689 */ 12690 #define sc_x4_control_payload_REPEAT_2_BYTES 0 12691 #define sc_x4_control_payload_RAMPING 1 12692 #define sc_x4_control_payload_CL48_CRPAT 2 12693 #define sc_x4_control_payload_CL48_CJPAT 3 12694 #define sc_x4_control_payload_CL36_LONG_CRPAT 4 12695 #define sc_x4_control_payload_CL36_SHORT_CRPAT 5 12696 12697 /**************************************************************************** 12698 * Enums: sc_x4_control_sc 12699 */ 12700 #define sc_x4_control_sc_SPEED_10G_IEEE_KR1 0 12701 #define sc_x4_control_sc_SPEED_25G_IEEE_KS1_CS1 1 12702 #define sc_x4_control_sc_SPEED_25G_IEEE_KR1_CR1 2 12703 #define sc_x4_control_sc_SPEED_40G_IEEE_KR4 3 12704 #define sc_x4_control_sc_SPEED_40G_IEEE_CR4 4 12705 #define sc_x4_control_sc_SPEED_50G_IEEE_KR1_CR1 5 12706 #define sc_x4_control_sc_SPEED_100G_IEEE_KR4 6 12707 #define sc_x4_control_sc_SPEED_100G_IEEE_CR4 7 12708 #define sc_x4_control_sc_SPEED_100G_IEEE_KR2_CR2 8 12709 #define sc_x4_control_sc_SPEED_200G_IEEE_KR4_CR4 9 12710 #define sc_x4_control_sc_SPEED_400G_IEEE_X8 10 12711 #define sc_x4_control_sc_SPEED_CL73_IEEE_20GVCO 11 12712 #define sc_x4_control_sc_SPEED_CL73_IEEE_25GVCO 12 12713 #define sc_x4_control_sc_SPEED_CL73_IEEE_26GVCO 13 12714 #define sc_x4_control_sc_SPEED_20G_BRCM_CR1 14 12715 #define sc_x4_control_sc_SPEED_20G_BRCM_KR1 15 12716 #define sc_x4_control_sc_SPEED_25G_BRCM_CR1 16 12717 #define sc_x4_control_sc_SPEED_25G_BRCM_KR1 17 12718 #define sc_x4_control_sc_SPEED_40G_BRCM_CR2 18 12719 #define sc_x4_control_sc_SPEED_40G_BRCM_KR2 19 12720 #define sc_x4_control_sc_SPEED_50G_BRCM_CR2 20 12721 #define sc_x4_control_sc_SPEED_50G_BRCM_KR2 21 12722 #define sc_x4_control_sc_SPEED_50G_BRCM_CR4 22 12723 #define sc_x4_control_sc_SPEED_50G_BRCM_KR4 23 12724 #define sc_x4_control_sc_SPEED_50G_BRCM_FEC_544_CR2_KR2 24 12725 #define sc_x4_control_sc_SPEED_RESERVED_19 25 12726 #define sc_x4_control_sc_SPEED_50G_BRCM_FEC_544_CR1_KR1 26 12727 #define sc_x4_control_sc_SPEED_50G_BRCM_NO_FEC_CR1_KR1 27 12728 #define sc_x4_control_sc_SPEED_50G_BRCM_FEC_528_CR1_KR1 28 12729 #define sc_x4_control_sc_SPEED_400G_BRCM_NO_FEC_KR8_CR8 29 12730 #define sc_x4_control_sc_SPEED_400G_BRCM_FEC_KR8_CR8 30 12731 #define sc_x4_control_sc_SPEED_200G_BRCM_NO_FEC_KR4_CR4 31 12732 #define sc_x4_control_sc_SPEED_200G_BRCM_KR4_CR4 32 12733 #define sc_x4_control_sc_SPEED_100G_BRCM_KR4_CR4 33 12734 #define sc_x4_control_sc_SPEED_RESERVED_22 34 12735 #define sc_x4_control_sc_SPEED_100G_BRCM_FEC_528_KR2_CR2 35 12736 #define sc_x4_control_sc_SPEED_100G_BRCM_NO_FEC_KR2_CR2 36 12737 #define sc_x4_control_sc_SPEED_100G_BRCM_NO_FEC_X4 37 12738 12739 /**************************************************************************** 12740 * Enums: sc_x4_control_t_fifo_modes 12741 */ 12742 #define sc_x4_control_t_fifo_modes_T_FIFO_INSERT_NO_AM 0 12743 #define sc_x4_control_t_fifo_modes_T_FIFO_INSERT_4_AM 1 12744 #define sc_x4_control_t_fifo_modes_T_FIFO_INSERT_20_AM 2 12745 #define sc_x4_control_t_fifo_modes_T_FIFO_INSERT_2_AM 3 12746 12747 /**************************************************************************** 12748 * Enums: sc_x4_control_t_enc_modes 12749 */ 12750 #define sc_x4_control_t_enc_modes_T_ENC_MODE_BYPASS 0 12751 #define sc_x4_control_t_enc_modes_T_ENC_MODE_CL49 1 12752 #define sc_x4_control_t_enc_modes_T_ENC_MODE_CL82 2 12753 12754 /**************************************************************************** 12755 * Enums: sc_x4_control_btmx_mode 12756 */ 12757 #define sc_x4_control_btmx_mode_BS_BTMX_MODE_1to1 0 12758 #define sc_x4_control_btmx_mode_BS_BTMX_MODE_2to1 1 12759 #define sc_x4_control_btmx_mode_BS_BTMX_MODE_5to1 2 12760 12761 /**************************************************************************** 12762 * Enums: sc_x4_control_t_type_cl82 12763 */ 12764 #define sc_x4_control_t_type_cl82_T_TYPE_B1 5 12765 #define sc_x4_control_t_type_cl82_T_TYPE_C 4 12766 #define sc_x4_control_t_type_cl82_T_TYPE_S 3 12767 #define sc_x4_control_t_type_cl82_T_TYPE_T 2 12768 #define sc_x4_control_t_type_cl82_T_TYPE_D 1 12769 #define sc_x4_control_t_type_cl82_T_TYPE_E 0 12770 12771 /**************************************************************************** 12772 * Enums: sc_x4_control_txsm_state_cl82 12773 */ 12774 #define sc_x4_control_txsm_state_cl82_TX_E 4 12775 #define sc_x4_control_txsm_state_cl82_TX_T 3 12776 #define sc_x4_control_txsm_state_cl82_TX_D 2 12777 #define sc_x4_control_txsm_state_cl82_TX_C 1 12778 #define sc_x4_control_txsm_state_cl82_TX_INIT 0 12779 12780 /**************************************************************************** 12781 * Enums: sc_x4_control_ltxsm_state_cl82 12782 */ 12783 #define sc_x4_control_ltxsm_state_cl82_TX_E 16 12784 #define sc_x4_control_ltxsm_state_cl82_TX_T 8 12785 #define sc_x4_control_ltxsm_state_cl82_TX_D 4 12786 #define sc_x4_control_ltxsm_state_cl82_TX_C 2 12787 #define sc_x4_control_ltxsm_state_cl82_TX_INIT 1 12788 12789 /**************************************************************************** 12790 * Enums: sc_x4_control_r_type_coded_cl82 12791 */ 12792 #define sc_x4_control_r_type_coded_cl82_R_TYPE_B1 32 12793 #define sc_x4_control_r_type_coded_cl82_R_TYPE_C 16 12794 #define sc_x4_control_r_type_coded_cl82_R_TYPE_S 8 12795 #define sc_x4_control_r_type_coded_cl82_R_TYPE_T 4 12796 #define sc_x4_control_r_type_coded_cl82_R_TYPE_D 2 12797 #define sc_x4_control_r_type_coded_cl82_R_TYPE_E 1 12798 12799 /**************************************************************************** 12800 * Enums: sc_x4_control_rxsm_state_cl82 12801 */ 12802 #define sc_x4_control_rxsm_state_cl82_RX_E 16 12803 #define sc_x4_control_rxsm_state_cl82_RX_T 8 12804 #define sc_x4_control_rxsm_state_cl82_RX_D 4 12805 #define sc_x4_control_rxsm_state_cl82_RX_C 2 12806 #define sc_x4_control_rxsm_state_cl82_RX_INIT 1 12807 12808 /**************************************************************************** 12809 * Enums: sc_x4_control_deskew_state 12810 */ 12811 #define sc_x4_control_deskew_state_ALIGN_ACQUIRED 2 12812 #define sc_x4_control_deskew_state_LOSS_OF_ALIGNMENT 1 12813 12814 /**************************************************************************** 12815 * Enums: sc_x4_control_os_mode_enum 12816 */ 12817 #define sc_x4_control_os_mode_enum_OS_MODE_1 0 12818 #define sc_x4_control_os_mode_enum_OS_MODE_2 1 12819 #define sc_x4_control_os_mode_enum_OS_MODE_4 2 12820 #define sc_x4_control_os_mode_enum_OS_MODE_16p5 8 12821 #define sc_x4_control_os_mode_enum_OS_MODE_20p625 12 12822 12823 /**************************************************************************** 12824 * Enums: sc_x4_control_scr_modes 12825 */ 12826 #define sc_x4_control_scr_modes_T_SCR_MODE_BYPASS 0 12827 #define sc_x4_control_scr_modes_T_SCR_MODE_CL49 1 12828 #define sc_x4_control_scr_modes_T_SCR_MODE_40G_2_LANE 2 12829 #define sc_x4_control_scr_modes_T_SCR_MODE_100G 3 12830 #define sc_x4_control_scr_modes_T_SCR_MODE_20G 4 12831 #define sc_x4_control_scr_modes_T_SCR_MODE_40G_4_LANE 5 12832 12833 /**************************************************************************** 12834 * Enums: sc_x4_control_descr_modes 12835 */ 12836 #define sc_x4_control_descr_modes_R_DESCR_MODE_BYPASS 0 12837 #define sc_x4_control_descr_modes_R_DESCR_MODE_CL49 1 12838 #define sc_x4_control_descr_modes_R_DESCR_MODE_CL82 2 12839 12840 /**************************************************************************** 12841 * Enums: sc_x4_control_r_dec_tl_mode 12842 */ 12843 #define sc_x4_control_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 12844 #define sc_x4_control_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 12845 #define sc_x4_control_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 12846 12847 /**************************************************************************** 12848 * Enums: sc_x4_control_r_dec_fsm_mode 12849 */ 12850 #define sc_x4_control_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 12851 #define sc_x4_control_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 12852 #define sc_x4_control_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 12853 12854 /**************************************************************************** 12855 * Enums: sc_x4_control_r_deskew_mode 12856 */ 12857 #define sc_x4_control_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 12858 #define sc_x4_control_r_deskew_mode_R_DESKEW_MODE_20G 1 12859 #define sc_x4_control_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 12860 #define sc_x4_control_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 12861 #define sc_x4_control_r_deskew_mode_R_DESKEW_MODE_100G 4 12862 #define sc_x4_control_r_deskew_mode_R_DESKEW_MODE_CL49 5 12863 #define sc_x4_control_r_deskew_mode_R_DESKEW_MODE_CL91_QUAD 6 12864 #define sc_x4_control_r_deskew_mode_R_DESKEW_MODE_CL91_SINGLE_BRCM 7 12865 #define sc_x4_control_r_deskew_mode_R_DESKEW_MODE_CL91_DUAL_BRCM 8 12866 #define sc_x4_control_r_deskew_mode_R_DESKEW_MODE_CL91_FC 9 12867 12868 /**************************************************************************** 12869 * Enums: sc_x4_control_bs_dist_modes 12870 */ 12871 #define sc_x4_control_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 12872 #define sc_x4_control_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 12873 #define sc_x4_control_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 12874 #define sc_x4_control_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 12875 12876 /**************************************************************************** 12877 * Enums: sc_x4_control_cl49_t_type 12878 */ 12879 #define sc_x4_control_cl49_t_type_BAD_T_TYPE 15 12880 #define sc_x4_control_cl49_t_type_T_TYPE_B0 11 12881 #define sc_x4_control_cl49_t_type_T_TYPE_OB 10 12882 #define sc_x4_control_cl49_t_type_T_TYPE_B1 9 12883 #define sc_x4_control_cl49_t_type_T_TYPE_DB 8 12884 #define sc_x4_control_cl49_t_type_T_TYPE_FC 7 12885 #define sc_x4_control_cl49_t_type_T_TYPE_TB 6 12886 #define sc_x4_control_cl49_t_type_T_TYPE_LI 5 12887 #define sc_x4_control_cl49_t_type_T_TYPE_C 4 12888 #define sc_x4_control_cl49_t_type_T_TYPE_S 3 12889 #define sc_x4_control_cl49_t_type_T_TYPE_T 2 12890 #define sc_x4_control_cl49_t_type_T_TYPE_D 1 12891 #define sc_x4_control_cl49_t_type_T_TYPE_E 0 12892 12893 /**************************************************************************** 12894 * Enums: sc_x4_control_cl49_txsm_states 12895 */ 12896 #define sc_x4_control_cl49_txsm_states_TX_LI 5 12897 #define sc_x4_control_cl49_txsm_states_TX_E 4 12898 #define sc_x4_control_cl49_txsm_states_TX_T 3 12899 #define sc_x4_control_cl49_txsm_states_TX_D 2 12900 #define sc_x4_control_cl49_txsm_states_TX_C 1 12901 #define sc_x4_control_cl49_txsm_states_TX_INIT 0 12902 12903 /**************************************************************************** 12904 * Enums: sc_x4_control_cl49_ltxsm_states 12905 */ 12906 #define sc_x4_control_cl49_ltxsm_states_TX_LI 32 12907 #define sc_x4_control_cl49_ltxsm_states_TX_E 16 12908 #define sc_x4_control_cl49_ltxsm_states_TX_T 8 12909 #define sc_x4_control_cl49_ltxsm_states_TX_D 4 12910 #define sc_x4_control_cl49_ltxsm_states_TX_C 2 12911 #define sc_x4_control_cl49_ltxsm_states_TX_INIT 1 12912 12913 /**************************************************************************** 12914 * Enums: sc_x4_control_burst_error_mode 12915 */ 12916 #define sc_x4_control_burst_error_mode_BURST_ERROR_11_BITS 0 12917 #define sc_x4_control_burst_error_mode_BURST_ERROR_16_BITS 1 12918 #define sc_x4_control_burst_error_mode_BURST_ERROR_17_BITS 2 12919 #define sc_x4_control_burst_error_mode_BURST_ERROR_18_BITS 3 12920 #define sc_x4_control_burst_error_mode_BURST_ERROR_19_BITS 4 12921 #define sc_x4_control_burst_error_mode_BURST_ERROR_20_BITS 5 12922 #define sc_x4_control_burst_error_mode_BURST_ERROR_21_BITS 6 12923 #define sc_x4_control_burst_error_mode_BURST_ERROR_22_BITS 7 12924 #define sc_x4_control_burst_error_mode_BURST_ERROR_23_BITS 8 12925 #define sc_x4_control_burst_error_mode_BURST_ERROR_24_BITS 9 12926 #define sc_x4_control_burst_error_mode_BURST_ERROR_25_BITS 10 12927 #define sc_x4_control_burst_error_mode_BURST_ERROR_26_BITS 11 12928 #define sc_x4_control_burst_error_mode_BURST_ERROR_27_BITS 12 12929 #define sc_x4_control_burst_error_mode_BURST_ERROR_28_BITS 13 12930 #define sc_x4_control_burst_error_mode_BURST_ERROR_29_BITS 14 12931 #define sc_x4_control_burst_error_mode_BURST_ERROR_30_BITS 15 12932 #define sc_x4_control_burst_error_mode_BURST_ERROR_31_BITS 16 12933 #define sc_x4_control_burst_error_mode_BURST_ERROR_32_BITS 17 12934 #define sc_x4_control_burst_error_mode_BURST_ERROR_33_BITS 18 12935 #define sc_x4_control_burst_error_mode_BURST_ERROR_34_BITS 19 12936 #define sc_x4_control_burst_error_mode_BURST_ERROR_35_BITS 20 12937 #define sc_x4_control_burst_error_mode_BURST_ERROR_36_BITS 21 12938 #define sc_x4_control_burst_error_mode_BURST_ERROR_37_BITS 22 12939 #define sc_x4_control_burst_error_mode_BURST_ERROR_38_BITS 23 12940 #define sc_x4_control_burst_error_mode_BURST_ERROR_39_BITS 24 12941 #define sc_x4_control_burst_error_mode_BURST_ERROR_40_BITS 25 12942 #define sc_x4_control_burst_error_mode_BURST_ERROR_41_BITS 26 12943 12944 /**************************************************************************** 12945 * Enums: sc_x4_control_bermon_state 12946 */ 12947 #define sc_x4_control_bermon_state_HI_BER 4 12948 #define sc_x4_control_bermon_state_GOOD_BER 3 12949 #define sc_x4_control_bermon_state_BER_TEST_SH 2 12950 #define sc_x4_control_bermon_state_START_TIMER 1 12951 #define sc_x4_control_bermon_state_BER_MT_INIT 0 12952 12953 /**************************************************************************** 12954 * Enums: sc_x4_control_rxsm_state_cl49 12955 */ 12956 #define sc_x4_control_rxsm_state_cl49_RX_LI 32 12957 #define sc_x4_control_rxsm_state_cl49_RX_E 16 12958 #define sc_x4_control_rxsm_state_cl49_RX_T 8 12959 #define sc_x4_control_rxsm_state_cl49_RX_D 4 12960 #define sc_x4_control_rxsm_state_cl49_RX_C 2 12961 #define sc_x4_control_rxsm_state_cl49_RX_INIT 1 12962 12963 /**************************************************************************** 12964 * Enums: sc_x4_control_r_type 12965 */ 12966 #define sc_x4_control_r_type_BAD_R_TYPE 15 12967 #define sc_x4_control_r_type_R_TYPE_B0 11 12968 #define sc_x4_control_r_type_R_TYPE_OB 10 12969 #define sc_x4_control_r_type_R_TYPE_B1 9 12970 #define sc_x4_control_r_type_R_TYPE_DB 8 12971 #define sc_x4_control_r_type_R_TYPE_FC 7 12972 #define sc_x4_control_r_type_R_TYPE_TB 6 12973 #define sc_x4_control_r_type_R_TYPE_LI 5 12974 #define sc_x4_control_r_type_R_TYPE_C 4 12975 #define sc_x4_control_r_type_R_TYPE_S 3 12976 #define sc_x4_control_r_type_R_TYPE_T 2 12977 #define sc_x4_control_r_type_R_TYPE_D 1 12978 #define sc_x4_control_r_type_R_TYPE_E 0 12979 12980 /**************************************************************************** 12981 * Enums: sc_x4_control_am_lock_state 12982 */ 12983 #define sc_x4_control_am_lock_state_INVALID_AM 512 12984 #define sc_x4_control_am_lock_state_GOOD_AM 256 12985 #define sc_x4_control_am_lock_state_COMP_AM 128 12986 #define sc_x4_control_am_lock_state_TIMER_2 64 12987 #define sc_x4_control_am_lock_state_AM_2_GOOD 32 12988 #define sc_x4_control_am_lock_state_COMP_2ND 16 12989 #define sc_x4_control_am_lock_state_TIMER_1 8 12990 #define sc_x4_control_am_lock_state_FIND_1ST 4 12991 #define sc_x4_control_am_lock_state_AM_RESET_CNT 2 12992 #define sc_x4_control_am_lock_state_AM_LOCK_INIT 1 12993 12994 /**************************************************************************** 12995 * Enums: sc_x4_control_msg_selector 12996 */ 12997 #define sc_x4_control_msg_selector_RESERVED 0 12998 #define sc_x4_control_msg_selector_VALUE_802p3 1 12999 #define sc_x4_control_msg_selector_VALUE_802p9 2 13000 #define sc_x4_control_msg_selector_VALUE_802p5 3 13001 #define sc_x4_control_msg_selector_VALUE_1394 4 13002 13003 /**************************************************************************** 13004 * Enums: sc_x4_control_synce_enum_stage1 13005 */ 13006 #define sc_x4_control_synce_enum_stage1_SYNCE_NO_DIV 0 13007 #define sc_x4_control_synce_enum_stage1_SYNCE_DIV_7 1 13008 #define sc_x4_control_synce_enum_stage1_SYNCE_DIV_11 2 13009 13010 /**************************************************************************** 13011 * Enums: sc_x4_control_synce_enum_stage0 13012 */ 13013 #define sc_x4_control_synce_enum_stage0_SYNCE_NO_DIV 0 13014 #define sc_x4_control_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 13015 #define sc_x4_control_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 13016 13017 /**************************************************************************** 13018 * Enums: sc_x4_control_cl91_sync_state 13019 */ 13020 #define sc_x4_control_cl91_sync_state_FIND_1ST 0 13021 #define sc_x4_control_cl91_sync_state_COUNT_NEXT 1 13022 #define sc_x4_control_cl91_sync_state_COMP_2ND 2 13023 #define sc_x4_control_cl91_sync_state_TWO_GOOD 3 13024 13025 /**************************************************************************** 13026 * Enums: sc_x4_control_RS_FEC_sync_state 13027 */ 13028 #define sc_x4_control_RS_FEC_sync_state_LOCK_INIT 0 13029 #define sc_x4_control_RS_FEC_sync_state_FIND_1ST 1 13030 #define sc_x4_control_RS_FEC_sync_state_COUNT_NEXT 2 13031 #define sc_x4_control_RS_FEC_sync_state_COMP_2ND 3 13032 #define sc_x4_control_RS_FEC_sync_state_TWO_GOOD 4 13033 13034 /**************************************************************************** 13035 * Enums: sc_x4_control_cl91_algn_state 13036 */ 13037 #define sc_x4_control_cl91_algn_state_LOSS_OF_ALIGNMENT 0 13038 #define sc_x4_control_cl91_algn_state_DESKEW 1 13039 #define sc_x4_control_cl91_algn_state_DESKEW_FAIL 2 13040 #define sc_x4_control_cl91_algn_state_ALIGN_ACQUIRED 3 13041 #define sc_x4_control_cl91_algn_state_CW_GOOD 4 13042 #define sc_x4_control_cl91_algn_state_CW_BAD 5 13043 #define sc_x4_control_cl91_algn_state_THREE_BAD 6 13044 13045 /**************************************************************************** 13046 * Enums: sc_x4_control_RS_FEC_algn_state 13047 */ 13048 #define sc_x4_control_RS_FEC_algn_state_LOSS_OF_ALIGNMENT 0 13049 #define sc_x4_control_RS_FEC_algn_state_DESKEW 1 13050 #define sc_x4_control_RS_FEC_algn_state_DESKEW_FAIL 2 13051 #define sc_x4_control_RS_FEC_algn_state_ALIGN_ACQUIRED 3 13052 #define sc_x4_control_RS_FEC_algn_state_CW_GOOD 4 13053 #define sc_x4_control_RS_FEC_algn_state_CW_BAD 5 13054 #define sc_x4_control_RS_FEC_algn_state_THREE_BAD 6 13055 13056 /**************************************************************************** 13057 * Enums: sc_x4_control_fec_sel_override 13058 */ 13059 #define sc_x4_control_fec_sel_override_NO_OVERRIDE 0 13060 #define sc_x4_control_fec_sel_override_NO_FEC 1 13061 #define sc_x4_control_fec_sel_override_FEC_CL74 2 13062 #define sc_x4_control_fec_sel_override_FEC_CL91 3 13063 13064 /**************************************************************************** 13065 * Enums: sc_x4_control_cl91_blksync_mode 13066 */ 13067 #define sc_x4_control_cl91_blksync_mode_R_BLKSYNC_NO_CL91_FEC 0 13068 #define sc_x4_control_cl91_blksync_mode_R_BLKSYNC_CL91_QUAD_LANE_FEC 1 13069 #define sc_x4_control_cl91_blksync_mode_R_BLKSYNC_CL91_DUAL_LANE_FEC 2 13070 #define sc_x4_control_cl91_blksync_mode_R_BLKSYNC_CL91_SINGLE_LANE_FEC 3 13071 #define sc_x4_control_cl91_blksync_mode_R_BLKSYNC_CL91_FC_FEC 4 13072 13073 /**************************************************************************** 13074 * Enums: sc_x4_control_r_merge_mode 13075 */ 13076 #define sc_x4_control_r_merge_mode_R_MERGE_MODE_BYPASS 0 13077 #define sc_x4_control_r_merge_mode_R_MERGE_MODE_CL91_FC 1 13078 #define sc_x4_control_r_merge_mode_R_MERGE_MODE_CL91_SINGLE_LANE 2 13079 #define sc_x4_control_r_merge_mode_R_MERGE_MODE_CL91_DUAL_LANE 3 13080 #define sc_x4_control_r_merge_mode_R_MERGE_MODE_CL91_QUAD_LANE 4 13081 13082 /**************************************************************************** 13083 * Enums: sc_x4_control_r_tc_mode 13084 */ 13085 #define sc_x4_control_r_tc_mode_R_TC_MODE_SINGLE 0 13086 #define sc_x4_control_r_tc_mode_R_TC_MODE_DUAL 1 13087 #define sc_x4_control_r_tc_mode_R_TC_MODE_QUAD 2 13088 13089 /**************************************************************************** 13090 * Enums: sc_x4_control_r_tc_out_mode 13091 */ 13092 #define sc_x4_control_r_tc_out_mode_R_TC_OUT_MODE_SINGLE 0 13093 #define sc_x4_control_r_tc_out_mode_R_TC_OUT_MODE_DUAL 1 13094 #define sc_x4_control_r_tc_out_mode_R_TC_OUT_MODE_QUAD 2 13095 13096 /**************************************************************************** 13097 * Enums: sc_x4_control_cl91_fec_mode 13098 */ 13099 #define sc_x4_control_cl91_fec_mode_NO_CL91_FEC 0 13100 #define sc_x4_control_cl91_fec_mode_CL91_SINGLE_LANE_FC 1 13101 #define sc_x4_control_cl91_fec_mode_CL91_SINGLE_LANE_BRCM_PROP 2 13102 #define sc_x4_control_cl91_fec_mode_CL91_DUAL_LANE_BRCM_PROP 3 13103 #define sc_x4_control_cl91_fec_mode_CL91_QUAD_LANE 4 13104 #define sc_x4_control_cl91_fec_mode_IEEE_25G_CL91_SINGLE_LANE 5 13105 13106 /**************************************************************************** 13107 * Enums: sc_x4_control_RS_FEC_fec_mode 13108 */ 13109 #define sc_x4_control_RS_FEC_fec_mode_NO_RS_FEC_FEC 0 13110 #define sc_x4_control_RS_FEC_fec_mode_N_A 1 13111 #define sc_x4_control_RS_FEC_fec_mode_RS_FEC_SINGLE_LANE_BRCM_PROP 2 13112 #define sc_x4_control_RS_FEC_fec_mode_RS_FEC_DUAL_LANE_BRCM_PROP 3 13113 #define sc_x4_control_RS_FEC_fec_mode_RS_FEC_QUAD_LANE 4 13114 #define sc_x4_control_RS_FEC_fec_mode_IEEE_25G_RS_FEC_SINGLE_LANE 5 13115 13116 /**************************************************************************** 13117 * Enums: sc_x4_control_am_spacing_mul 13118 */ 13119 #define sc_x4_control_am_spacing_mul_AM_SPACING_MUL_2 0 13120 #define sc_x4_control_am_spacing_mul_AM_SPACING_MUL_4 1 13121 #define sc_x4_control_am_spacing_mul_AM_SPACING_MUL_5 2 13122 #define sc_x4_control_am_spacing_mul_AM_SPACING_MUL_20 3 13123 13124 /**************************************************************************** 13125 * Enums: sc_x4_final_config_status_cl36TxEEEStates_l 13126 */ 13127 #define sc_x4_final_config_status_cl36TxEEEStates_l_TX_REFRESH 8 13128 #define sc_x4_final_config_status_cl36TxEEEStates_l_TX_QUIET 4 13129 #define sc_x4_final_config_status_cl36TxEEEStates_l_TX_SLEEP 2 13130 #define sc_x4_final_config_status_cl36TxEEEStates_l_TX_ACTIVE 1 13131 13132 /**************************************************************************** 13133 * Enums: sc_x4_final_config_status_cl36TxEEEStates_c 13134 */ 13135 #define sc_x4_final_config_status_cl36TxEEEStates_c_TX_REFRESH 3 13136 #define sc_x4_final_config_status_cl36TxEEEStates_c_TX_QUIET 2 13137 #define sc_x4_final_config_status_cl36TxEEEStates_c_TX_SLEEP 1 13138 #define sc_x4_final_config_status_cl36TxEEEStates_c_TX_ACTIVE 0 13139 13140 /**************************************************************************** 13141 * Enums: sc_x4_final_config_status_cl49TxEEEStates_l 13142 */ 13143 #define sc_x4_final_config_status_cl49TxEEEStates_l_SCR_RESET_2 64 13144 #define sc_x4_final_config_status_cl49TxEEEStates_l_SCR_RESET_1 32 13145 #define sc_x4_final_config_status_cl49TxEEEStates_l_TX_WAKE 16 13146 #define sc_x4_final_config_status_cl49TxEEEStates_l_TX_REFRESH 8 13147 #define sc_x4_final_config_status_cl49TxEEEStates_l_TX_QUIET 4 13148 #define sc_x4_final_config_status_cl49TxEEEStates_l_TX_SLEEP 2 13149 #define sc_x4_final_config_status_cl49TxEEEStates_l_TX_ACTIVE 1 13150 13151 /**************************************************************************** 13152 * Enums: sc_x4_final_config_status_fec_req_enum 13153 */ 13154 #define sc_x4_final_config_status_fec_req_enum_FEC_not_supported 0 13155 #define sc_x4_final_config_status_fec_req_enum_FEC_supported_but_not_requested 1 13156 #define sc_x4_final_config_status_fec_req_enum_invalid_setting 2 13157 #define sc_x4_final_config_status_fec_req_enum_FEC_supported_and_requested 3 13158 13159 /**************************************************************************** 13160 * Enums: sc_x4_final_config_status_cl73_pause_enum 13161 */ 13162 #define sc_x4_final_config_status_cl73_pause_enum_No_PAUSE_ability 0 13163 #define sc_x4_final_config_status_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 13164 #define sc_x4_final_config_status_cl73_pause_enum_Symmetric_PAUSE_ability 1 13165 #define sc_x4_final_config_status_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 13166 13167 /**************************************************************************** 13168 * Enums: sc_x4_final_config_status_cl49TxEEEStates_c 13169 */ 13170 #define sc_x4_final_config_status_cl49TxEEEStates_c_SCR_RESET_2 6 13171 #define sc_x4_final_config_status_cl49TxEEEStates_c_SCR_RESET_1 5 13172 #define sc_x4_final_config_status_cl49TxEEEStates_c_TX_WAKE 4 13173 #define sc_x4_final_config_status_cl49TxEEEStates_c_TX_REFRESH 3 13174 #define sc_x4_final_config_status_cl49TxEEEStates_c_TX_QUIET 2 13175 #define sc_x4_final_config_status_cl49TxEEEStates_c_TX_SLEEP 1 13176 #define sc_x4_final_config_status_cl49TxEEEStates_c_TX_ACTIVE 0 13177 13178 /**************************************************************************** 13179 * Enums: sc_x4_final_config_status_cl36RxEEEStates_l 13180 */ 13181 #define sc_x4_final_config_status_cl36RxEEEStates_l_RX_LINK_FAIL 32 13182 #define sc_x4_final_config_status_cl36RxEEEStates_l_RX_WTF 16 13183 #define sc_x4_final_config_status_cl36RxEEEStates_l_RX_WAKE 8 13184 #define sc_x4_final_config_status_cl36RxEEEStates_l_RX_QUIET 4 13185 #define sc_x4_final_config_status_cl36RxEEEStates_l_RX_SLEEP 2 13186 #define sc_x4_final_config_status_cl36RxEEEStates_l_RX_ACTIVE 1 13187 13188 /**************************************************************************** 13189 * Enums: sc_x4_final_config_status_cl36RxEEEStates_c 13190 */ 13191 #define sc_x4_final_config_status_cl36RxEEEStates_c_RX_LINK_FAIL 5 13192 #define sc_x4_final_config_status_cl36RxEEEStates_c_RX_WTF 4 13193 #define sc_x4_final_config_status_cl36RxEEEStates_c_RX_WAKE 3 13194 #define sc_x4_final_config_status_cl36RxEEEStates_c_RX_QUIET 2 13195 #define sc_x4_final_config_status_cl36RxEEEStates_c_RX_SLEEP 1 13196 #define sc_x4_final_config_status_cl36RxEEEStates_c_RX_ACTIVE 0 13197 13198 /**************************************************************************** 13199 * Enums: sc_x4_final_config_status_cl49RxEEEStates_l 13200 */ 13201 #define sc_x4_final_config_status_cl49RxEEEStates_l_RX_LINK_FAIL 32 13202 #define sc_x4_final_config_status_cl49RxEEEStates_l_RX_WTF 16 13203 #define sc_x4_final_config_status_cl49RxEEEStates_l_RX_WAKE 8 13204 #define sc_x4_final_config_status_cl49RxEEEStates_l_RX_QUIET 4 13205 #define sc_x4_final_config_status_cl49RxEEEStates_l_RX_SLEEP 2 13206 #define sc_x4_final_config_status_cl49RxEEEStates_l_RX_ACTIVE 1 13207 13208 /**************************************************************************** 13209 * Enums: sc_x4_final_config_status_cl49RxEEEStates_c 13210 */ 13211 #define sc_x4_final_config_status_cl49RxEEEStates_c_RX_LINK_FAIL 5 13212 #define sc_x4_final_config_status_cl49RxEEEStates_c_RX_WTF 4 13213 #define sc_x4_final_config_status_cl49RxEEEStates_c_RX_WAKE 3 13214 #define sc_x4_final_config_status_cl49RxEEEStates_c_RX_QUIET 2 13215 #define sc_x4_final_config_status_cl49RxEEEStates_c_RX_SLEEP 1 13216 #define sc_x4_final_config_status_cl49RxEEEStates_c_RX_ACTIVE 0 13217 13218 /**************************************************************************** 13219 * Enums: sc_x4_final_config_status_cl48TxEEEStates_l 13220 */ 13221 #define sc_x4_final_config_status_cl48TxEEEStates_l_TX_REFRESH 8 13222 #define sc_x4_final_config_status_cl48TxEEEStates_l_TX_QUIET 4 13223 #define sc_x4_final_config_status_cl48TxEEEStates_l_TX_SLEEP 2 13224 #define sc_x4_final_config_status_cl48TxEEEStates_l_TX_ACTIVE 1 13225 13226 /**************************************************************************** 13227 * Enums: sc_x4_final_config_status_cl48TxEEEStates_c 13228 */ 13229 #define sc_x4_final_config_status_cl48TxEEEStates_c_TX_REFRESH 3 13230 #define sc_x4_final_config_status_cl48TxEEEStates_c_TX_QUIET 2 13231 #define sc_x4_final_config_status_cl48TxEEEStates_c_TX_SLEEP 1 13232 #define sc_x4_final_config_status_cl48TxEEEStates_c_TX_ACTIVE 0 13233 13234 /**************************************************************************** 13235 * Enums: sc_x4_final_config_status_cl48RxEEEStates_l 13236 */ 13237 #define sc_x4_final_config_status_cl48RxEEEStates_l_RX_LINK_FAIL 32 13238 #define sc_x4_final_config_status_cl48RxEEEStates_l_RX_WAKE 16 13239 #define sc_x4_final_config_status_cl48RxEEEStates_l_RX_QUIET 8 13240 #define sc_x4_final_config_status_cl48RxEEEStates_l_RX_DEACT 4 13241 #define sc_x4_final_config_status_cl48RxEEEStates_l_RX_SLEEP 2 13242 #define sc_x4_final_config_status_cl48RxEEEStates_l_RX_ACTIVE 1 13243 13244 /**************************************************************************** 13245 * Enums: sc_x4_final_config_status_cl48RxEEEStates_c 13246 */ 13247 #define sc_x4_final_config_status_cl48RxEEEStates_c_RX_LINK_FAIL 5 13248 #define sc_x4_final_config_status_cl48RxEEEStates_c_RX_WAKE 4 13249 #define sc_x4_final_config_status_cl48RxEEEStates_c_RX_QUIET 3 13250 #define sc_x4_final_config_status_cl48RxEEEStates_c_RX_DEACT 2 13251 #define sc_x4_final_config_status_cl48RxEEEStates_c_RX_SLEEP 1 13252 #define sc_x4_final_config_status_cl48RxEEEStates_c_RX_ACTIVE 0 13253 13254 /**************************************************************************** 13255 * Enums: sc_x4_final_config_status_IQP_Options 13256 */ 13257 #define sc_x4_final_config_status_IQP_Options_i50uA 0 13258 #define sc_x4_final_config_status_IQP_Options_i100uA 1 13259 #define sc_x4_final_config_status_IQP_Options_i150uA 2 13260 #define sc_x4_final_config_status_IQP_Options_i200uA 3 13261 #define sc_x4_final_config_status_IQP_Options_i250uA 4 13262 #define sc_x4_final_config_status_IQP_Options_i300uA 5 13263 #define sc_x4_final_config_status_IQP_Options_i350uA 6 13264 #define sc_x4_final_config_status_IQP_Options_i400uA 7 13265 #define sc_x4_final_config_status_IQP_Options_i450uA 8 13266 #define sc_x4_final_config_status_IQP_Options_i500uA 9 13267 #define sc_x4_final_config_status_IQP_Options_i550uA 10 13268 #define sc_x4_final_config_status_IQP_Options_i600uA 11 13269 #define sc_x4_final_config_status_IQP_Options_i650uA 12 13270 #define sc_x4_final_config_status_IQP_Options_i700uA 13 13271 #define sc_x4_final_config_status_IQP_Options_i750uA 14 13272 #define sc_x4_final_config_status_IQP_Options_i800uA 15 13273 13274 /**************************************************************************** 13275 * Enums: sc_x4_final_config_status_IDriver_Options 13276 */ 13277 #define sc_x4_final_config_status_IDriver_Options_v680mV 0 13278 #define sc_x4_final_config_status_IDriver_Options_v730mV 1 13279 #define sc_x4_final_config_status_IDriver_Options_v780mV 2 13280 #define sc_x4_final_config_status_IDriver_Options_v830mV 3 13281 #define sc_x4_final_config_status_IDriver_Options_v880mV 4 13282 #define sc_x4_final_config_status_IDriver_Options_v930mV 5 13283 #define sc_x4_final_config_status_IDriver_Options_v980mV 6 13284 #define sc_x4_final_config_status_IDriver_Options_v1010mV 7 13285 #define sc_x4_final_config_status_IDriver_Options_v1040mV 8 13286 #define sc_x4_final_config_status_IDriver_Options_v1060mV 9 13287 #define sc_x4_final_config_status_IDriver_Options_v1070mV 10 13288 #define sc_x4_final_config_status_IDriver_Options_v1080mV 11 13289 #define sc_x4_final_config_status_IDriver_Options_v1085mV 12 13290 #define sc_x4_final_config_status_IDriver_Options_v1090mV 13 13291 #define sc_x4_final_config_status_IDriver_Options_v1095mV 14 13292 #define sc_x4_final_config_status_IDriver_Options_v1100mV 15 13293 13294 /**************************************************************************** 13295 * Enums: sc_x4_final_config_status_operationModes 13296 */ 13297 #define sc_x4_final_config_status_operationModes_XGXS 0 13298 #define sc_x4_final_config_status_operationModes_XGXG_nCC 1 13299 #define sc_x4_final_config_status_operationModes_Indlane_OS8 4 13300 #define sc_x4_final_config_status_operationModes_IndLane_OS5 5 13301 #define sc_x4_final_config_status_operationModes_PCI 7 13302 #define sc_x4_final_config_status_operationModes_XGXS_nLQ 8 13303 #define sc_x4_final_config_status_operationModes_XGXS_nLQnCC 9 13304 #define sc_x4_final_config_status_operationModes_PBypass 10 13305 #define sc_x4_final_config_status_operationModes_PBypass_nDSK 11 13306 #define sc_x4_final_config_status_operationModes_ComboCoreMode 12 13307 #define sc_x4_final_config_status_operationModes_Clocks_off 15 13308 13309 /**************************************************************************** 13310 * Enums: sc_x4_final_config_status_actualSpeeds 13311 */ 13312 #define sc_x4_final_config_status_actualSpeeds_dr_10M 0 13313 #define sc_x4_final_config_status_actualSpeeds_dr_100M 1 13314 #define sc_x4_final_config_status_actualSpeeds_dr_1G 2 13315 #define sc_x4_final_config_status_actualSpeeds_dr_2p5G 3 13316 #define sc_x4_final_config_status_actualSpeeds_dr_5G_X4 4 13317 #define sc_x4_final_config_status_actualSpeeds_dr_6G_X4 5 13318 #define sc_x4_final_config_status_actualSpeeds_dr_10G_HiG 6 13319 #define sc_x4_final_config_status_actualSpeeds_dr_10G_CX4 7 13320 #define sc_x4_final_config_status_actualSpeeds_dr_12G_HiG 8 13321 #define sc_x4_final_config_status_actualSpeeds_dr_12p5G_X4 9 13322 #define sc_x4_final_config_status_actualSpeeds_dr_13G_X4 10 13323 #define sc_x4_final_config_status_actualSpeeds_dr_15G_X4 11 13324 #define sc_x4_final_config_status_actualSpeeds_dr_16G_X4 12 13325 #define sc_x4_final_config_status_actualSpeeds_dr_1G_KX 13 13326 #define sc_x4_final_config_status_actualSpeeds_dr_10G_KX4 14 13327 #define sc_x4_final_config_status_actualSpeeds_dr_10G_KR 15 13328 #define sc_x4_final_config_status_actualSpeeds_dr_5G 16 13329 #define sc_x4_final_config_status_actualSpeeds_dr_6p4G 17 13330 #define sc_x4_final_config_status_actualSpeeds_dr_20G_X4 18 13331 #define sc_x4_final_config_status_actualSpeeds_dr_21G_X4 19 13332 #define sc_x4_final_config_status_actualSpeeds_dr_25G_X4 20 13333 #define sc_x4_final_config_status_actualSpeeds_dr_10G_HiG_DXGXS 21 13334 #define sc_x4_final_config_status_actualSpeeds_dr_10G_DXGXS 22 13335 #define sc_x4_final_config_status_actualSpeeds_dr_10p5G_HiG_DXGXS 23 13336 #define sc_x4_final_config_status_actualSpeeds_dr_10p5G_DXGXS 24 13337 #define sc_x4_final_config_status_actualSpeeds_dr_12p773G_HiG_DXGXS 25 13338 #define sc_x4_final_config_status_actualSpeeds_dr_12p773G_DXGXS 26 13339 #define sc_x4_final_config_status_actualSpeeds_dr_10G_XFI 27 13340 #define sc_x4_final_config_status_actualSpeeds_dr_40G 28 13341 #define sc_x4_final_config_status_actualSpeeds_dr_20G_HiG_DXGXS 29 13342 #define sc_x4_final_config_status_actualSpeeds_dr_20G_DXGXS 30 13343 #define sc_x4_final_config_status_actualSpeeds_dr_10G_SFI 31 13344 #define sc_x4_final_config_status_actualSpeeds_dr_31p5G 32 13345 #define sc_x4_final_config_status_actualSpeeds_dr_32p7G 33 13346 #define sc_x4_final_config_status_actualSpeeds_dr_20G_SCR 34 13347 #define sc_x4_final_config_status_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 13348 #define sc_x4_final_config_status_actualSpeeds_dr_10G_DXGXS_SCR 36 13349 #define sc_x4_final_config_status_actualSpeeds_dr_12G_R2 37 13350 #define sc_x4_final_config_status_actualSpeeds_dr_10G_X2 38 13351 #define sc_x4_final_config_status_actualSpeeds_dr_40G_KR4 39 13352 #define sc_x4_final_config_status_actualSpeeds_dr_40G_CR4 40 13353 #define sc_x4_final_config_status_actualSpeeds_dr_100G_CR10 41 13354 #define sc_x4_final_config_status_actualSpeeds_dr_15p75G_DXGXS 44 13355 #define sc_x4_final_config_status_actualSpeeds_dr_20G_KR2 57 13356 #define sc_x4_final_config_status_actualSpeeds_dr_20G_CR2 58 13357 13358 /**************************************************************************** 13359 * Enums: sc_x4_final_config_status_actualSpeedsMisc1 13360 */ 13361 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_2500BRCM_X1 16 13362 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_5000BRCM_X4 17 13363 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_6000BRCM_X4 18 13364 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_10GHiGig_X4 19 13365 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_10GBASE_CX4 20 13366 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_12GHiGig_X4 21 13367 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 13368 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_13GHiGig_X4 23 13369 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_15GHiGig_X4 24 13370 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_16GHiGig_X4 25 13371 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_5000BRCM_X1 26 13372 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_6363BRCM_X1 27 13373 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_20GHiGig_X4 28 13374 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_21GHiGig_X4 29 13375 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 13376 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 13377 13378 /**************************************************************************** 13379 * Enums: sc_x4_final_config_status_IndLaneModes 13380 */ 13381 #define sc_x4_final_config_status_IndLaneModes_SWSDR_div2 0 13382 #define sc_x4_final_config_status_IndLaneModes_SWSDR_div1 1 13383 #define sc_x4_final_config_status_IndLaneModes_DWSDR_div2 2 13384 #define sc_x4_final_config_status_IndLaneModes_DWSDR_div1 3 13385 13386 /**************************************************************************** 13387 * Enums: sc_x4_final_config_status_prbsSelect 13388 */ 13389 #define sc_x4_final_config_status_prbsSelect_prbs7 0 13390 #define sc_x4_final_config_status_prbsSelect_prbs15 1 13391 #define sc_x4_final_config_status_prbsSelect_prbs23 2 13392 #define sc_x4_final_config_status_prbsSelect_prbs31 3 13393 13394 /**************************************************************************** 13395 * Enums: sc_x4_final_config_status_vcoDivider 13396 */ 13397 #define sc_x4_final_config_status_vcoDivider_div32 0 13398 #define sc_x4_final_config_status_vcoDivider_div36 1 13399 #define sc_x4_final_config_status_vcoDivider_div40 2 13400 #define sc_x4_final_config_status_vcoDivider_div42 3 13401 #define sc_x4_final_config_status_vcoDivider_div48 4 13402 #define sc_x4_final_config_status_vcoDivider_div50 5 13403 #define sc_x4_final_config_status_vcoDivider_div52 6 13404 #define sc_x4_final_config_status_vcoDivider_div54 7 13405 #define sc_x4_final_config_status_vcoDivider_div60 8 13406 #define sc_x4_final_config_status_vcoDivider_div64 9 13407 #define sc_x4_final_config_status_vcoDivider_div66 10 13408 #define sc_x4_final_config_status_vcoDivider_div68 11 13409 #define sc_x4_final_config_status_vcoDivider_div70 12 13410 #define sc_x4_final_config_status_vcoDivider_div80 13 13411 #define sc_x4_final_config_status_vcoDivider_div92 14 13412 #define sc_x4_final_config_status_vcoDivider_div100 15 13413 13414 /**************************************************************************** 13415 * Enums: sc_x4_final_config_status_refClkSelect 13416 */ 13417 #define sc_x4_final_config_status_refClkSelect_clk_156p25MHz 1 13418 #define sc_x4_final_config_status_refClkSelect_clk_312p5Mhz 2 13419 13420 /**************************************************************************** 13421 * Enums: sc_x4_final_config_status_aerMMDdevTypeSelect 13422 */ 13423 #define sc_x4_final_config_status_aerMMDdevTypeSelect_combo_core 0 13424 #define sc_x4_final_config_status_aerMMDdevTypeSelect_PMA_PMD 1 13425 #define sc_x4_final_config_status_aerMMDdevTypeSelect_PCS 3 13426 #define sc_x4_final_config_status_aerMMDdevTypeSelect_PHY 4 13427 #define sc_x4_final_config_status_aerMMDdevTypeSelect_DTE 5 13428 #define sc_x4_final_config_status_aerMMDdevTypeSelect_CL73_AN 7 13429 13430 /**************************************************************************** 13431 * Enums: sc_x4_final_config_status_aerMMDportSelect 13432 */ 13433 #define sc_x4_final_config_status_aerMMDportSelect_ln0 0 13434 #define sc_x4_final_config_status_aerMMDportSelect_ln1 1 13435 #define sc_x4_final_config_status_aerMMDportSelect_ln2 2 13436 #define sc_x4_final_config_status_aerMMDportSelect_ln3 3 13437 #define sc_x4_final_config_status_aerMMDportSelect_BCST_ln0_1_2_3 511 13438 #define sc_x4_final_config_status_aerMMDportSelect_BCST_ln0_1 512 13439 #define sc_x4_final_config_status_aerMMDportSelect_BCST_ln2_3 513 13440 13441 /**************************************************************************** 13442 * Enums: sc_x4_final_config_status_firmwareModeSelect 13443 */ 13444 #define sc_x4_final_config_status_firmwareModeSelect_DEFAULT 0 13445 #define sc_x4_final_config_status_firmwareModeSelect_SFP_OPT_LR 1 13446 #define sc_x4_final_config_status_firmwareModeSelect_SFP_DAC 2 13447 #define sc_x4_final_config_status_firmwareModeSelect_XLAUI 3 13448 #define sc_x4_final_config_status_firmwareModeSelect_LONG_CH_6G 4 13449 13450 /**************************************************************************** 13451 * Enums: sc_x4_final_config_status_tempIdxSelect 13452 */ 13453 #define sc_x4_final_config_status_tempIdxSelect_LTE__22p9C 15 13454 #define sc_x4_final_config_status_tempIdxSelect_LTE__12p6C 14 13455 #define sc_x4_final_config_status_tempIdxSelect_LTE__3p0C 13 13456 #define sc_x4_final_config_status_tempIdxSelect_LTE_6p7C 12 13457 #define sc_x4_final_config_status_tempIdxSelect_LTE_16p4C 11 13458 #define sc_x4_final_config_status_tempIdxSelect_LTE_26p6C 10 13459 #define sc_x4_final_config_status_tempIdxSelect_LTE_36p3C 9 13460 #define sc_x4_final_config_status_tempIdxSelect_LTE_46p0C 8 13461 #define sc_x4_final_config_status_tempIdxSelect_LTE_56p2C 7 13462 #define sc_x4_final_config_status_tempIdxSelect_LTE_65p9C 6 13463 #define sc_x4_final_config_status_tempIdxSelect_LTE_75p6C 5 13464 #define sc_x4_final_config_status_tempIdxSelect_LTE_85p3C 4 13465 #define sc_x4_final_config_status_tempIdxSelect_LTE_95p5C 3 13466 #define sc_x4_final_config_status_tempIdxSelect_LTE_105p2C 2 13467 #define sc_x4_final_config_status_tempIdxSelect_LTE_114p9C 1 13468 #define sc_x4_final_config_status_tempIdxSelect_LTE_125p1C 0 13469 13470 /**************************************************************************** 13471 * Enums: sc_x4_final_config_status_port_mode 13472 */ 13473 #define sc_x4_final_config_status_port_mode_QUAD_PORT 0 13474 #define sc_x4_final_config_status_port_mode_TRI_1_PORT 1 13475 #define sc_x4_final_config_status_port_mode_TRI_2_PORT 2 13476 #define sc_x4_final_config_status_port_mode_DUAL_PORT 3 13477 #define sc_x4_final_config_status_port_mode_SINGLE_PORT 4 13478 #define sc_x4_final_config_status_port_mode_SINGLE_OCTAL_PORT 5 13479 13480 /**************************************************************************** 13481 * Enums: sc_x4_final_config_status_rev_letter_enum 13482 */ 13483 #define sc_x4_final_config_status_rev_letter_enum_REV_A 0 13484 #define sc_x4_final_config_status_rev_letter_enum_REV_B 1 13485 #define sc_x4_final_config_status_rev_letter_enum_REV_C 2 13486 #define sc_x4_final_config_status_rev_letter_enum_REV_D 3 13487 13488 /**************************************************************************** 13489 * Enums: sc_x4_final_config_status_rev_number_enum 13490 */ 13491 #define sc_x4_final_config_status_rev_number_enum_REV_0 0 13492 #define sc_x4_final_config_status_rev_number_enum_REV_1 1 13493 #define sc_x4_final_config_status_rev_number_enum_REV_2 2 13494 #define sc_x4_final_config_status_rev_number_enum_REV_3 3 13495 #define sc_x4_final_config_status_rev_number_enum_REV_4 4 13496 #define sc_x4_final_config_status_rev_number_enum_REV_5 5 13497 #define sc_x4_final_config_status_rev_number_enum_REV_6 6 13498 #define sc_x4_final_config_status_rev_number_enum_REV_7 7 13499 13500 /**************************************************************************** 13501 * Enums: sc_x4_final_config_status_bonding_enum 13502 */ 13503 #define sc_x4_final_config_status_bonding_enum_WIRE_BOND 0 13504 #define sc_x4_final_config_status_bonding_enum_FLIP_CHIP 1 13505 13506 /**************************************************************************** 13507 * Enums: sc_x4_final_config_status_tech_process 13508 */ 13509 #define sc_x4_final_config_status_tech_process_PROCESS_90NM 0 13510 #define sc_x4_final_config_status_tech_process_PROCESS_65NM 1 13511 #define sc_x4_final_config_status_tech_process_PROCESS_40NM 2 13512 #define sc_x4_final_config_status_tech_process_PROCESS_28NM 3 13513 #define sc_x4_final_config_status_tech_process_PROCESS_16NM 4 13514 13515 /**************************************************************************** 13516 * Enums: sc_x4_final_config_status_model_num 13517 */ 13518 #define sc_x4_final_config_status_model_num_SERDES_CL73 0 13519 #define sc_x4_final_config_status_model_num_XGXS_16G 1 13520 #define sc_x4_final_config_status_model_num_HYPERCORE 2 13521 #define sc_x4_final_config_status_model_num_HYPERLITE 3 13522 #define sc_x4_final_config_status_model_num_PCIE_G2_PIPE 4 13523 #define sc_x4_final_config_status_model_num_SERDES_1p25GBd 5 13524 #define sc_x4_final_config_status_model_num_SATA2 6 13525 #define sc_x4_final_config_status_model_num_QSGMII 7 13526 #define sc_x4_final_config_status_model_num_XGXS10G 8 13527 #define sc_x4_final_config_status_model_num_WARPCORE 9 13528 #define sc_x4_final_config_status_model_num_XFICORE 10 13529 #define sc_x4_final_config_status_model_num_RXFI 11 13530 #define sc_x4_final_config_status_model_num_WARPLITE 12 13531 #define sc_x4_final_config_status_model_num_PENTACORE 13 13532 #define sc_x4_final_config_status_model_num_ESM 14 13533 #define sc_x4_final_config_status_model_num_QUAD_SGMII 15 13534 #define sc_x4_final_config_status_model_num_WARPCORE_3 16 13535 #define sc_x4_final_config_status_model_num_TSC 17 13536 #define sc_x4_final_config_status_model_num_TSC4E 18 13537 #define sc_x4_final_config_status_model_num_TSC12E 19 13538 #define sc_x4_final_config_status_model_num_TSC4F 20 13539 #define sc_x4_final_config_status_model_num_TSC4F_GEN2 21 13540 #define sc_x4_final_config_status_model_num_XGXS_CL73_90NM 29 13541 #define sc_x4_final_config_status_model_num_SERDES_CL73_90NM 30 13542 #define sc_x4_final_config_status_model_num_WARPCORE3 32 13543 #define sc_x4_final_config_status_model_num_WARPCORE4_TSC 33 13544 #define sc_x4_final_config_status_model_num_RXAUI 34 13545 #define sc_x4_final_config_status_model_num_TSCE_GEN3 35 13546 #define sc_x4_final_config_status_model_num_TSC4F_GEN3 36 13547 #define sc_x4_final_config_status_model_num_TSCBH 37 13548 13549 /**************************************************************************** 13550 * Enums: sc_x4_final_config_status_payload 13551 */ 13552 #define sc_x4_final_config_status_payload_REPEAT_2_BYTES 0 13553 #define sc_x4_final_config_status_payload_RAMPING 1 13554 #define sc_x4_final_config_status_payload_CL48_CRPAT 2 13555 #define sc_x4_final_config_status_payload_CL48_CJPAT 3 13556 #define sc_x4_final_config_status_payload_CL36_LONG_CRPAT 4 13557 #define sc_x4_final_config_status_payload_CL36_SHORT_CRPAT 5 13558 13559 /**************************************************************************** 13560 * Enums: sc_x4_final_config_status_sc 13561 */ 13562 #define sc_x4_final_config_status_sc_SPEED_10G_IEEE_KR1 0 13563 #define sc_x4_final_config_status_sc_SPEED_25G_IEEE_KS1_CS1 1 13564 #define sc_x4_final_config_status_sc_SPEED_25G_IEEE_KR1_CR1 2 13565 #define sc_x4_final_config_status_sc_SPEED_40G_IEEE_KR4 3 13566 #define sc_x4_final_config_status_sc_SPEED_40G_IEEE_CR4 4 13567 #define sc_x4_final_config_status_sc_SPEED_50G_IEEE_KR1_CR1 5 13568 #define sc_x4_final_config_status_sc_SPEED_100G_IEEE_KR4 6 13569 #define sc_x4_final_config_status_sc_SPEED_100G_IEEE_CR4 7 13570 #define sc_x4_final_config_status_sc_SPEED_100G_IEEE_KR2_CR2 8 13571 #define sc_x4_final_config_status_sc_SPEED_200G_IEEE_KR4_CR4 9 13572 #define sc_x4_final_config_status_sc_SPEED_400G_IEEE_X8 10 13573 #define sc_x4_final_config_status_sc_SPEED_CL73_IEEE_20GVCO 11 13574 #define sc_x4_final_config_status_sc_SPEED_CL73_IEEE_25GVCO 12 13575 #define sc_x4_final_config_status_sc_SPEED_CL73_IEEE_26GVCO 13 13576 #define sc_x4_final_config_status_sc_SPEED_20G_BRCM_CR1 14 13577 #define sc_x4_final_config_status_sc_SPEED_20G_BRCM_KR1 15 13578 #define sc_x4_final_config_status_sc_SPEED_25G_BRCM_CR1 16 13579 #define sc_x4_final_config_status_sc_SPEED_25G_BRCM_KR1 17 13580 #define sc_x4_final_config_status_sc_SPEED_40G_BRCM_CR2 18 13581 #define sc_x4_final_config_status_sc_SPEED_40G_BRCM_KR2 19 13582 #define sc_x4_final_config_status_sc_SPEED_50G_BRCM_CR2 20 13583 #define sc_x4_final_config_status_sc_SPEED_50G_BRCM_KR2 21 13584 #define sc_x4_final_config_status_sc_SPEED_50G_BRCM_CR4 22 13585 #define sc_x4_final_config_status_sc_SPEED_50G_BRCM_KR4 23 13586 #define sc_x4_final_config_status_sc_SPEED_50G_BRCM_FEC_544_CR2_KR2 24 13587 #define sc_x4_final_config_status_sc_SPEED_RESERVED_19 25 13588 #define sc_x4_final_config_status_sc_SPEED_50G_BRCM_FEC_544_CR1_KR1 26 13589 #define sc_x4_final_config_status_sc_SPEED_50G_BRCM_NO_FEC_CR1_KR1 27 13590 #define sc_x4_final_config_status_sc_SPEED_50G_BRCM_FEC_528_CR1_KR1 28 13591 #define sc_x4_final_config_status_sc_SPEED_400G_BRCM_NO_FEC_KR8_CR8 29 13592 #define sc_x4_final_config_status_sc_SPEED_400G_BRCM_FEC_KR8_CR8 30 13593 #define sc_x4_final_config_status_sc_SPEED_200G_BRCM_NO_FEC_KR4_CR4 31 13594 #define sc_x4_final_config_status_sc_SPEED_200G_BRCM_KR4_CR4 32 13595 #define sc_x4_final_config_status_sc_SPEED_100G_BRCM_KR4_CR4 33 13596 #define sc_x4_final_config_status_sc_SPEED_RESERVED_22 34 13597 #define sc_x4_final_config_status_sc_SPEED_100G_BRCM_FEC_528_KR2_CR2 35 13598 #define sc_x4_final_config_status_sc_SPEED_100G_BRCM_NO_FEC_KR2_CR2 36 13599 #define sc_x4_final_config_status_sc_SPEED_100G_BRCM_NO_FEC_X4 37 13600 13601 /**************************************************************************** 13602 * Enums: sc_x4_final_config_status_t_fifo_modes 13603 */ 13604 #define sc_x4_final_config_status_t_fifo_modes_T_FIFO_INSERT_NO_AM 0 13605 #define sc_x4_final_config_status_t_fifo_modes_T_FIFO_INSERT_4_AM 1 13606 #define sc_x4_final_config_status_t_fifo_modes_T_FIFO_INSERT_20_AM 2 13607 #define sc_x4_final_config_status_t_fifo_modes_T_FIFO_INSERT_2_AM 3 13608 13609 /**************************************************************************** 13610 * Enums: sc_x4_final_config_status_t_enc_modes 13611 */ 13612 #define sc_x4_final_config_status_t_enc_modes_T_ENC_MODE_BYPASS 0 13613 #define sc_x4_final_config_status_t_enc_modes_T_ENC_MODE_CL49 1 13614 #define sc_x4_final_config_status_t_enc_modes_T_ENC_MODE_CL82 2 13615 13616 /**************************************************************************** 13617 * Enums: sc_x4_final_config_status_btmx_mode 13618 */ 13619 #define sc_x4_final_config_status_btmx_mode_BS_BTMX_MODE_1to1 0 13620 #define sc_x4_final_config_status_btmx_mode_BS_BTMX_MODE_2to1 1 13621 #define sc_x4_final_config_status_btmx_mode_BS_BTMX_MODE_5to1 2 13622 13623 /**************************************************************************** 13624 * Enums: sc_x4_final_config_status_t_type_cl82 13625 */ 13626 #define sc_x4_final_config_status_t_type_cl82_T_TYPE_B1 5 13627 #define sc_x4_final_config_status_t_type_cl82_T_TYPE_C 4 13628 #define sc_x4_final_config_status_t_type_cl82_T_TYPE_S 3 13629 #define sc_x4_final_config_status_t_type_cl82_T_TYPE_T 2 13630 #define sc_x4_final_config_status_t_type_cl82_T_TYPE_D 1 13631 #define sc_x4_final_config_status_t_type_cl82_T_TYPE_E 0 13632 13633 /**************************************************************************** 13634 * Enums: sc_x4_final_config_status_txsm_state_cl82 13635 */ 13636 #define sc_x4_final_config_status_txsm_state_cl82_TX_E 4 13637 #define sc_x4_final_config_status_txsm_state_cl82_TX_T 3 13638 #define sc_x4_final_config_status_txsm_state_cl82_TX_D 2 13639 #define sc_x4_final_config_status_txsm_state_cl82_TX_C 1 13640 #define sc_x4_final_config_status_txsm_state_cl82_TX_INIT 0 13641 13642 /**************************************************************************** 13643 * Enums: sc_x4_final_config_status_ltxsm_state_cl82 13644 */ 13645 #define sc_x4_final_config_status_ltxsm_state_cl82_TX_E 16 13646 #define sc_x4_final_config_status_ltxsm_state_cl82_TX_T 8 13647 #define sc_x4_final_config_status_ltxsm_state_cl82_TX_D 4 13648 #define sc_x4_final_config_status_ltxsm_state_cl82_TX_C 2 13649 #define sc_x4_final_config_status_ltxsm_state_cl82_TX_INIT 1 13650 13651 /**************************************************************************** 13652 * Enums: sc_x4_final_config_status_r_type_coded_cl82 13653 */ 13654 #define sc_x4_final_config_status_r_type_coded_cl82_R_TYPE_B1 32 13655 #define sc_x4_final_config_status_r_type_coded_cl82_R_TYPE_C 16 13656 #define sc_x4_final_config_status_r_type_coded_cl82_R_TYPE_S 8 13657 #define sc_x4_final_config_status_r_type_coded_cl82_R_TYPE_T 4 13658 #define sc_x4_final_config_status_r_type_coded_cl82_R_TYPE_D 2 13659 #define sc_x4_final_config_status_r_type_coded_cl82_R_TYPE_E 1 13660 13661 /**************************************************************************** 13662 * Enums: sc_x4_final_config_status_rxsm_state_cl82 13663 */ 13664 #define sc_x4_final_config_status_rxsm_state_cl82_RX_E 16 13665 #define sc_x4_final_config_status_rxsm_state_cl82_RX_T 8 13666 #define sc_x4_final_config_status_rxsm_state_cl82_RX_D 4 13667 #define sc_x4_final_config_status_rxsm_state_cl82_RX_C 2 13668 #define sc_x4_final_config_status_rxsm_state_cl82_RX_INIT 1 13669 13670 /**************************************************************************** 13671 * Enums: sc_x4_final_config_status_deskew_state 13672 */ 13673 #define sc_x4_final_config_status_deskew_state_ALIGN_ACQUIRED 2 13674 #define sc_x4_final_config_status_deskew_state_LOSS_OF_ALIGNMENT 1 13675 13676 /**************************************************************************** 13677 * Enums: sc_x4_final_config_status_os_mode_enum 13678 */ 13679 #define sc_x4_final_config_status_os_mode_enum_OS_MODE_1 0 13680 #define sc_x4_final_config_status_os_mode_enum_OS_MODE_2 1 13681 #define sc_x4_final_config_status_os_mode_enum_OS_MODE_4 2 13682 #define sc_x4_final_config_status_os_mode_enum_OS_MODE_16p5 8 13683 #define sc_x4_final_config_status_os_mode_enum_OS_MODE_20p625 12 13684 13685 /**************************************************************************** 13686 * Enums: sc_x4_final_config_status_scr_modes 13687 */ 13688 #define sc_x4_final_config_status_scr_modes_T_SCR_MODE_BYPASS 0 13689 #define sc_x4_final_config_status_scr_modes_T_SCR_MODE_CL49 1 13690 #define sc_x4_final_config_status_scr_modes_T_SCR_MODE_40G_2_LANE 2 13691 #define sc_x4_final_config_status_scr_modes_T_SCR_MODE_100G 3 13692 #define sc_x4_final_config_status_scr_modes_T_SCR_MODE_20G 4 13693 #define sc_x4_final_config_status_scr_modes_T_SCR_MODE_40G_4_LANE 5 13694 13695 /**************************************************************************** 13696 * Enums: sc_x4_final_config_status_descr_modes 13697 */ 13698 #define sc_x4_final_config_status_descr_modes_R_DESCR_MODE_BYPASS 0 13699 #define sc_x4_final_config_status_descr_modes_R_DESCR_MODE_CL49 1 13700 #define sc_x4_final_config_status_descr_modes_R_DESCR_MODE_CL82 2 13701 13702 /**************************************************************************** 13703 * Enums: sc_x4_final_config_status_r_dec_tl_mode 13704 */ 13705 #define sc_x4_final_config_status_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 13706 #define sc_x4_final_config_status_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 13707 #define sc_x4_final_config_status_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 13708 13709 /**************************************************************************** 13710 * Enums: sc_x4_final_config_status_r_dec_fsm_mode 13711 */ 13712 #define sc_x4_final_config_status_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 13713 #define sc_x4_final_config_status_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 13714 #define sc_x4_final_config_status_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 13715 13716 /**************************************************************************** 13717 * Enums: sc_x4_final_config_status_r_deskew_mode 13718 */ 13719 #define sc_x4_final_config_status_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 13720 #define sc_x4_final_config_status_r_deskew_mode_R_DESKEW_MODE_20G 1 13721 #define sc_x4_final_config_status_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 13722 #define sc_x4_final_config_status_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 13723 #define sc_x4_final_config_status_r_deskew_mode_R_DESKEW_MODE_100G 4 13724 #define sc_x4_final_config_status_r_deskew_mode_R_DESKEW_MODE_CL49 5 13725 #define sc_x4_final_config_status_r_deskew_mode_R_DESKEW_MODE_CL91_QUAD 6 13726 #define sc_x4_final_config_status_r_deskew_mode_R_DESKEW_MODE_CL91_SINGLE_BRCM 7 13727 #define sc_x4_final_config_status_r_deskew_mode_R_DESKEW_MODE_CL91_DUAL_BRCM 8 13728 #define sc_x4_final_config_status_r_deskew_mode_R_DESKEW_MODE_CL91_FC 9 13729 13730 /**************************************************************************** 13731 * Enums: sc_x4_final_config_status_bs_dist_modes 13732 */ 13733 #define sc_x4_final_config_status_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 13734 #define sc_x4_final_config_status_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 13735 #define sc_x4_final_config_status_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 13736 #define sc_x4_final_config_status_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 13737 13738 /**************************************************************************** 13739 * Enums: sc_x4_final_config_status_cl49_t_type 13740 */ 13741 #define sc_x4_final_config_status_cl49_t_type_BAD_T_TYPE 15 13742 #define sc_x4_final_config_status_cl49_t_type_T_TYPE_B0 11 13743 #define sc_x4_final_config_status_cl49_t_type_T_TYPE_OB 10 13744 #define sc_x4_final_config_status_cl49_t_type_T_TYPE_B1 9 13745 #define sc_x4_final_config_status_cl49_t_type_T_TYPE_DB 8 13746 #define sc_x4_final_config_status_cl49_t_type_T_TYPE_FC 7 13747 #define sc_x4_final_config_status_cl49_t_type_T_TYPE_TB 6 13748 #define sc_x4_final_config_status_cl49_t_type_T_TYPE_LI 5 13749 #define sc_x4_final_config_status_cl49_t_type_T_TYPE_C 4 13750 #define sc_x4_final_config_status_cl49_t_type_T_TYPE_S 3 13751 #define sc_x4_final_config_status_cl49_t_type_T_TYPE_T 2 13752 #define sc_x4_final_config_status_cl49_t_type_T_TYPE_D 1 13753 #define sc_x4_final_config_status_cl49_t_type_T_TYPE_E 0 13754 13755 /**************************************************************************** 13756 * Enums: sc_x4_final_config_status_cl49_txsm_states 13757 */ 13758 #define sc_x4_final_config_status_cl49_txsm_states_TX_LI 5 13759 #define sc_x4_final_config_status_cl49_txsm_states_TX_E 4 13760 #define sc_x4_final_config_status_cl49_txsm_states_TX_T 3 13761 #define sc_x4_final_config_status_cl49_txsm_states_TX_D 2 13762 #define sc_x4_final_config_status_cl49_txsm_states_TX_C 1 13763 #define sc_x4_final_config_status_cl49_txsm_states_TX_INIT 0 13764 13765 /**************************************************************************** 13766 * Enums: sc_x4_final_config_status_cl49_ltxsm_states 13767 */ 13768 #define sc_x4_final_config_status_cl49_ltxsm_states_TX_LI 32 13769 #define sc_x4_final_config_status_cl49_ltxsm_states_TX_E 16 13770 #define sc_x4_final_config_status_cl49_ltxsm_states_TX_T 8 13771 #define sc_x4_final_config_status_cl49_ltxsm_states_TX_D 4 13772 #define sc_x4_final_config_status_cl49_ltxsm_states_TX_C 2 13773 #define sc_x4_final_config_status_cl49_ltxsm_states_TX_INIT 1 13774 13775 /**************************************************************************** 13776 * Enums: sc_x4_final_config_status_burst_error_mode 13777 */ 13778 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_11_BITS 0 13779 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_16_BITS 1 13780 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_17_BITS 2 13781 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_18_BITS 3 13782 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_19_BITS 4 13783 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_20_BITS 5 13784 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_21_BITS 6 13785 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_22_BITS 7 13786 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_23_BITS 8 13787 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_24_BITS 9 13788 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_25_BITS 10 13789 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_26_BITS 11 13790 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_27_BITS 12 13791 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_28_BITS 13 13792 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_29_BITS 14 13793 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_30_BITS 15 13794 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_31_BITS 16 13795 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_32_BITS 17 13796 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_33_BITS 18 13797 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_34_BITS 19 13798 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_35_BITS 20 13799 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_36_BITS 21 13800 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_37_BITS 22 13801 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_38_BITS 23 13802 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_39_BITS 24 13803 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_40_BITS 25 13804 #define sc_x4_final_config_status_burst_error_mode_BURST_ERROR_41_BITS 26 13805 13806 /**************************************************************************** 13807 * Enums: sc_x4_final_config_status_bermon_state 13808 */ 13809 #define sc_x4_final_config_status_bermon_state_HI_BER 4 13810 #define sc_x4_final_config_status_bermon_state_GOOD_BER 3 13811 #define sc_x4_final_config_status_bermon_state_BER_TEST_SH 2 13812 #define sc_x4_final_config_status_bermon_state_START_TIMER 1 13813 #define sc_x4_final_config_status_bermon_state_BER_MT_INIT 0 13814 13815 /**************************************************************************** 13816 * Enums: sc_x4_final_config_status_rxsm_state_cl49 13817 */ 13818 #define sc_x4_final_config_status_rxsm_state_cl49_RX_LI 32 13819 #define sc_x4_final_config_status_rxsm_state_cl49_RX_E 16 13820 #define sc_x4_final_config_status_rxsm_state_cl49_RX_T 8 13821 #define sc_x4_final_config_status_rxsm_state_cl49_RX_D 4 13822 #define sc_x4_final_config_status_rxsm_state_cl49_RX_C 2 13823 #define sc_x4_final_config_status_rxsm_state_cl49_RX_INIT 1 13824 13825 /**************************************************************************** 13826 * Enums: sc_x4_final_config_status_r_type 13827 */ 13828 #define sc_x4_final_config_status_r_type_BAD_R_TYPE 15 13829 #define sc_x4_final_config_status_r_type_R_TYPE_B0 11 13830 #define sc_x4_final_config_status_r_type_R_TYPE_OB 10 13831 #define sc_x4_final_config_status_r_type_R_TYPE_B1 9 13832 #define sc_x4_final_config_status_r_type_R_TYPE_DB 8 13833 #define sc_x4_final_config_status_r_type_R_TYPE_FC 7 13834 #define sc_x4_final_config_status_r_type_R_TYPE_TB 6 13835 #define sc_x4_final_config_status_r_type_R_TYPE_LI 5 13836 #define sc_x4_final_config_status_r_type_R_TYPE_C 4 13837 #define sc_x4_final_config_status_r_type_R_TYPE_S 3 13838 #define sc_x4_final_config_status_r_type_R_TYPE_T 2 13839 #define sc_x4_final_config_status_r_type_R_TYPE_D 1 13840 #define sc_x4_final_config_status_r_type_R_TYPE_E 0 13841 13842 /**************************************************************************** 13843 * Enums: sc_x4_final_config_status_am_lock_state 13844 */ 13845 #define sc_x4_final_config_status_am_lock_state_INVALID_AM 512 13846 #define sc_x4_final_config_status_am_lock_state_GOOD_AM 256 13847 #define sc_x4_final_config_status_am_lock_state_COMP_AM 128 13848 #define sc_x4_final_config_status_am_lock_state_TIMER_2 64 13849 #define sc_x4_final_config_status_am_lock_state_AM_2_GOOD 32 13850 #define sc_x4_final_config_status_am_lock_state_COMP_2ND 16 13851 #define sc_x4_final_config_status_am_lock_state_TIMER_1 8 13852 #define sc_x4_final_config_status_am_lock_state_FIND_1ST 4 13853 #define sc_x4_final_config_status_am_lock_state_AM_RESET_CNT 2 13854 #define sc_x4_final_config_status_am_lock_state_AM_LOCK_INIT 1 13855 13856 /**************************************************************************** 13857 * Enums: sc_x4_final_config_status_msg_selector 13858 */ 13859 #define sc_x4_final_config_status_msg_selector_RESERVED 0 13860 #define sc_x4_final_config_status_msg_selector_VALUE_802p3 1 13861 #define sc_x4_final_config_status_msg_selector_VALUE_802p9 2 13862 #define sc_x4_final_config_status_msg_selector_VALUE_802p5 3 13863 #define sc_x4_final_config_status_msg_selector_VALUE_1394 4 13864 13865 /**************************************************************************** 13866 * Enums: sc_x4_final_config_status_synce_enum_stage1 13867 */ 13868 #define sc_x4_final_config_status_synce_enum_stage1_SYNCE_NO_DIV 0 13869 #define sc_x4_final_config_status_synce_enum_stage1_SYNCE_DIV_7 1 13870 #define sc_x4_final_config_status_synce_enum_stage1_SYNCE_DIV_11 2 13871 13872 /**************************************************************************** 13873 * Enums: sc_x4_final_config_status_synce_enum_stage0 13874 */ 13875 #define sc_x4_final_config_status_synce_enum_stage0_SYNCE_NO_DIV 0 13876 #define sc_x4_final_config_status_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 13877 #define sc_x4_final_config_status_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 13878 13879 /**************************************************************************** 13880 * Enums: sc_x4_final_config_status_cl91_sync_state 13881 */ 13882 #define sc_x4_final_config_status_cl91_sync_state_FIND_1ST 0 13883 #define sc_x4_final_config_status_cl91_sync_state_COUNT_NEXT 1 13884 #define sc_x4_final_config_status_cl91_sync_state_COMP_2ND 2 13885 #define sc_x4_final_config_status_cl91_sync_state_TWO_GOOD 3 13886 13887 /**************************************************************************** 13888 * Enums: sc_x4_final_config_status_RS_FEC_sync_state 13889 */ 13890 #define sc_x4_final_config_status_RS_FEC_sync_state_LOCK_INIT 0 13891 #define sc_x4_final_config_status_RS_FEC_sync_state_FIND_1ST 1 13892 #define sc_x4_final_config_status_RS_FEC_sync_state_COUNT_NEXT 2 13893 #define sc_x4_final_config_status_RS_FEC_sync_state_COMP_2ND 3 13894 #define sc_x4_final_config_status_RS_FEC_sync_state_TWO_GOOD 4 13895 13896 /**************************************************************************** 13897 * Enums: sc_x4_final_config_status_cl91_algn_state 13898 */ 13899 #define sc_x4_final_config_status_cl91_algn_state_LOSS_OF_ALIGNMENT 0 13900 #define sc_x4_final_config_status_cl91_algn_state_DESKEW 1 13901 #define sc_x4_final_config_status_cl91_algn_state_DESKEW_FAIL 2 13902 #define sc_x4_final_config_status_cl91_algn_state_ALIGN_ACQUIRED 3 13903 #define sc_x4_final_config_status_cl91_algn_state_CW_GOOD 4 13904 #define sc_x4_final_config_status_cl91_algn_state_CW_BAD 5 13905 #define sc_x4_final_config_status_cl91_algn_state_THREE_BAD 6 13906 13907 /**************************************************************************** 13908 * Enums: sc_x4_final_config_status_RS_FEC_algn_state 13909 */ 13910 #define sc_x4_final_config_status_RS_FEC_algn_state_LOSS_OF_ALIGNMENT 0 13911 #define sc_x4_final_config_status_RS_FEC_algn_state_DESKEW 1 13912 #define sc_x4_final_config_status_RS_FEC_algn_state_DESKEW_FAIL 2 13913 #define sc_x4_final_config_status_RS_FEC_algn_state_ALIGN_ACQUIRED 3 13914 #define sc_x4_final_config_status_RS_FEC_algn_state_CW_GOOD 4 13915 #define sc_x4_final_config_status_RS_FEC_algn_state_CW_BAD 5 13916 #define sc_x4_final_config_status_RS_FEC_algn_state_THREE_BAD 6 13917 13918 /**************************************************************************** 13919 * Enums: sc_x4_final_config_status_fec_sel_override 13920 */ 13921 #define sc_x4_final_config_status_fec_sel_override_NO_OVERRIDE 0 13922 #define sc_x4_final_config_status_fec_sel_override_NO_FEC 1 13923 #define sc_x4_final_config_status_fec_sel_override_FEC_CL74 2 13924 #define sc_x4_final_config_status_fec_sel_override_FEC_CL91 3 13925 13926 /**************************************************************************** 13927 * Enums: sc_x4_final_config_status_cl91_blksync_mode 13928 */ 13929 #define sc_x4_final_config_status_cl91_blksync_mode_R_BLKSYNC_NO_CL91_FEC 0 13930 #define sc_x4_final_config_status_cl91_blksync_mode_R_BLKSYNC_CL91_QUAD_LANE_FEC 1 13931 #define sc_x4_final_config_status_cl91_blksync_mode_R_BLKSYNC_CL91_DUAL_LANE_FEC 2 13932 #define sc_x4_final_config_status_cl91_blksync_mode_R_BLKSYNC_CL91_SINGLE_LANE_FEC 3 13933 #define sc_x4_final_config_status_cl91_blksync_mode_R_BLKSYNC_CL91_FC_FEC 4 13934 13935 /**************************************************************************** 13936 * Enums: sc_x4_final_config_status_r_merge_mode 13937 */ 13938 #define sc_x4_final_config_status_r_merge_mode_R_MERGE_MODE_BYPASS 0 13939 #define sc_x4_final_config_status_r_merge_mode_R_MERGE_MODE_CL91_FC 1 13940 #define sc_x4_final_config_status_r_merge_mode_R_MERGE_MODE_CL91_SINGLE_LANE 2 13941 #define sc_x4_final_config_status_r_merge_mode_R_MERGE_MODE_CL91_DUAL_LANE 3 13942 #define sc_x4_final_config_status_r_merge_mode_R_MERGE_MODE_CL91_QUAD_LANE 4 13943 13944 /**************************************************************************** 13945 * Enums: sc_x4_final_config_status_r_tc_mode 13946 */ 13947 #define sc_x4_final_config_status_r_tc_mode_R_TC_MODE_SINGLE 0 13948 #define sc_x4_final_config_status_r_tc_mode_R_TC_MODE_DUAL 1 13949 #define sc_x4_final_config_status_r_tc_mode_R_TC_MODE_QUAD 2 13950 13951 /**************************************************************************** 13952 * Enums: sc_x4_final_config_status_r_tc_out_mode 13953 */ 13954 #define sc_x4_final_config_status_r_tc_out_mode_R_TC_OUT_MODE_SINGLE 0 13955 #define sc_x4_final_config_status_r_tc_out_mode_R_TC_OUT_MODE_DUAL 1 13956 #define sc_x4_final_config_status_r_tc_out_mode_R_TC_OUT_MODE_QUAD 2 13957 13958 /**************************************************************************** 13959 * Enums: sc_x4_final_config_status_cl91_fec_mode 13960 */ 13961 #define sc_x4_final_config_status_cl91_fec_mode_NO_CL91_FEC 0 13962 #define sc_x4_final_config_status_cl91_fec_mode_CL91_SINGLE_LANE_FC 1 13963 #define sc_x4_final_config_status_cl91_fec_mode_CL91_SINGLE_LANE_BRCM_PROP 2 13964 #define sc_x4_final_config_status_cl91_fec_mode_CL91_DUAL_LANE_BRCM_PROP 3 13965 #define sc_x4_final_config_status_cl91_fec_mode_CL91_QUAD_LANE 4 13966 #define sc_x4_final_config_status_cl91_fec_mode_IEEE_25G_CL91_SINGLE_LANE 5 13967 13968 /**************************************************************************** 13969 * Enums: sc_x4_final_config_status_RS_FEC_fec_mode 13970 */ 13971 #define sc_x4_final_config_status_RS_FEC_fec_mode_NO_RS_FEC_FEC 0 13972 #define sc_x4_final_config_status_RS_FEC_fec_mode_N_A 1 13973 #define sc_x4_final_config_status_RS_FEC_fec_mode_RS_FEC_SINGLE_LANE_BRCM_PROP 2 13974 #define sc_x4_final_config_status_RS_FEC_fec_mode_RS_FEC_DUAL_LANE_BRCM_PROP 3 13975 #define sc_x4_final_config_status_RS_FEC_fec_mode_RS_FEC_QUAD_LANE 4 13976 #define sc_x4_final_config_status_RS_FEC_fec_mode_IEEE_25G_RS_FEC_SINGLE_LANE 5 13977 13978 /**************************************************************************** 13979 * Enums: sc_x4_final_config_status_am_spacing_mul 13980 */ 13981 #define sc_x4_final_config_status_am_spacing_mul_AM_SPACING_MUL_2 0 13982 #define sc_x4_final_config_status_am_spacing_mul_AM_SPACING_MUL_4 1 13983 #define sc_x4_final_config_status_am_spacing_mul_AM_SPACING_MUL_5 2 13984 #define sc_x4_final_config_status_am_spacing_mul_AM_SPACING_MUL_20 3 13985 13986 /**************************************************************************** 13987 * Enums: synce_x4_cl36TxEEEStates_l 13988 */ 13989 #define synce_x4_cl36TxEEEStates_l_TX_REFRESH 8 13990 #define synce_x4_cl36TxEEEStates_l_TX_QUIET 4 13991 #define synce_x4_cl36TxEEEStates_l_TX_SLEEP 2 13992 #define synce_x4_cl36TxEEEStates_l_TX_ACTIVE 1 13993 13994 /**************************************************************************** 13995 * Enums: synce_x4_cl36TxEEEStates_c 13996 */ 13997 #define synce_x4_cl36TxEEEStates_c_TX_REFRESH 3 13998 #define synce_x4_cl36TxEEEStates_c_TX_QUIET 2 13999 #define synce_x4_cl36TxEEEStates_c_TX_SLEEP 1 14000 #define synce_x4_cl36TxEEEStates_c_TX_ACTIVE 0 14001 14002 /**************************************************************************** 14003 * Enums: synce_x4_cl49TxEEEStates_l 14004 */ 14005 #define synce_x4_cl49TxEEEStates_l_SCR_RESET_2 64 14006 #define synce_x4_cl49TxEEEStates_l_SCR_RESET_1 32 14007 #define synce_x4_cl49TxEEEStates_l_TX_WAKE 16 14008 #define synce_x4_cl49TxEEEStates_l_TX_REFRESH 8 14009 #define synce_x4_cl49TxEEEStates_l_TX_QUIET 4 14010 #define synce_x4_cl49TxEEEStates_l_TX_SLEEP 2 14011 #define synce_x4_cl49TxEEEStates_l_TX_ACTIVE 1 14012 14013 /**************************************************************************** 14014 * Enums: synce_x4_fec_req_enum 14015 */ 14016 #define synce_x4_fec_req_enum_FEC_not_supported 0 14017 #define synce_x4_fec_req_enum_FEC_supported_but_not_requested 1 14018 #define synce_x4_fec_req_enum_invalid_setting 2 14019 #define synce_x4_fec_req_enum_FEC_supported_and_requested 3 14020 14021 /**************************************************************************** 14022 * Enums: synce_x4_cl73_pause_enum 14023 */ 14024 #define synce_x4_cl73_pause_enum_No_PAUSE_ability 0 14025 #define synce_x4_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 14026 #define synce_x4_cl73_pause_enum_Symmetric_PAUSE_ability 1 14027 #define synce_x4_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 14028 14029 /**************************************************************************** 14030 * Enums: synce_x4_cl49TxEEEStates_c 14031 */ 14032 #define synce_x4_cl49TxEEEStates_c_SCR_RESET_2 6 14033 #define synce_x4_cl49TxEEEStates_c_SCR_RESET_1 5 14034 #define synce_x4_cl49TxEEEStates_c_TX_WAKE 4 14035 #define synce_x4_cl49TxEEEStates_c_TX_REFRESH 3 14036 #define synce_x4_cl49TxEEEStates_c_TX_QUIET 2 14037 #define synce_x4_cl49TxEEEStates_c_TX_SLEEP 1 14038 #define synce_x4_cl49TxEEEStates_c_TX_ACTIVE 0 14039 14040 /**************************************************************************** 14041 * Enums: synce_x4_cl36RxEEEStates_l 14042 */ 14043 #define synce_x4_cl36RxEEEStates_l_RX_LINK_FAIL 32 14044 #define synce_x4_cl36RxEEEStates_l_RX_WTF 16 14045 #define synce_x4_cl36RxEEEStates_l_RX_WAKE 8 14046 #define synce_x4_cl36RxEEEStates_l_RX_QUIET 4 14047 #define synce_x4_cl36RxEEEStates_l_RX_SLEEP 2 14048 #define synce_x4_cl36RxEEEStates_l_RX_ACTIVE 1 14049 14050 /**************************************************************************** 14051 * Enums: synce_x4_cl36RxEEEStates_c 14052 */ 14053 #define synce_x4_cl36RxEEEStates_c_RX_LINK_FAIL 5 14054 #define synce_x4_cl36RxEEEStates_c_RX_WTF 4 14055 #define synce_x4_cl36RxEEEStates_c_RX_WAKE 3 14056 #define synce_x4_cl36RxEEEStates_c_RX_QUIET 2 14057 #define synce_x4_cl36RxEEEStates_c_RX_SLEEP 1 14058 #define synce_x4_cl36RxEEEStates_c_RX_ACTIVE 0 14059 14060 /**************************************************************************** 14061 * Enums: synce_x4_cl49RxEEEStates_l 14062 */ 14063 #define synce_x4_cl49RxEEEStates_l_RX_LINK_FAIL 32 14064 #define synce_x4_cl49RxEEEStates_l_RX_WTF 16 14065 #define synce_x4_cl49RxEEEStates_l_RX_WAKE 8 14066 #define synce_x4_cl49RxEEEStates_l_RX_QUIET 4 14067 #define synce_x4_cl49RxEEEStates_l_RX_SLEEP 2 14068 #define synce_x4_cl49RxEEEStates_l_RX_ACTIVE 1 14069 14070 /**************************************************************************** 14071 * Enums: synce_x4_cl49RxEEEStates_c 14072 */ 14073 #define synce_x4_cl49RxEEEStates_c_RX_LINK_FAIL 5 14074 #define synce_x4_cl49RxEEEStates_c_RX_WTF 4 14075 #define synce_x4_cl49RxEEEStates_c_RX_WAKE 3 14076 #define synce_x4_cl49RxEEEStates_c_RX_QUIET 2 14077 #define synce_x4_cl49RxEEEStates_c_RX_SLEEP 1 14078 #define synce_x4_cl49RxEEEStates_c_RX_ACTIVE 0 14079 14080 /**************************************************************************** 14081 * Enums: synce_x4_cl48TxEEEStates_l 14082 */ 14083 #define synce_x4_cl48TxEEEStates_l_TX_REFRESH 8 14084 #define synce_x4_cl48TxEEEStates_l_TX_QUIET 4 14085 #define synce_x4_cl48TxEEEStates_l_TX_SLEEP 2 14086 #define synce_x4_cl48TxEEEStates_l_TX_ACTIVE 1 14087 14088 /**************************************************************************** 14089 * Enums: synce_x4_cl48TxEEEStates_c 14090 */ 14091 #define synce_x4_cl48TxEEEStates_c_TX_REFRESH 3 14092 #define synce_x4_cl48TxEEEStates_c_TX_QUIET 2 14093 #define synce_x4_cl48TxEEEStates_c_TX_SLEEP 1 14094 #define synce_x4_cl48TxEEEStates_c_TX_ACTIVE 0 14095 14096 /**************************************************************************** 14097 * Enums: synce_x4_cl48RxEEEStates_l 14098 */ 14099 #define synce_x4_cl48RxEEEStates_l_RX_LINK_FAIL 32 14100 #define synce_x4_cl48RxEEEStates_l_RX_WAKE 16 14101 #define synce_x4_cl48RxEEEStates_l_RX_QUIET 8 14102 #define synce_x4_cl48RxEEEStates_l_RX_DEACT 4 14103 #define synce_x4_cl48RxEEEStates_l_RX_SLEEP 2 14104 #define synce_x4_cl48RxEEEStates_l_RX_ACTIVE 1 14105 14106 /**************************************************************************** 14107 * Enums: synce_x4_cl48RxEEEStates_c 14108 */ 14109 #define synce_x4_cl48RxEEEStates_c_RX_LINK_FAIL 5 14110 #define synce_x4_cl48RxEEEStates_c_RX_WAKE 4 14111 #define synce_x4_cl48RxEEEStates_c_RX_QUIET 3 14112 #define synce_x4_cl48RxEEEStates_c_RX_DEACT 2 14113 #define synce_x4_cl48RxEEEStates_c_RX_SLEEP 1 14114 #define synce_x4_cl48RxEEEStates_c_RX_ACTIVE 0 14115 14116 /**************************************************************************** 14117 * Enums: synce_x4_IQP_Options 14118 */ 14119 #define synce_x4_IQP_Options_i50uA 0 14120 #define synce_x4_IQP_Options_i100uA 1 14121 #define synce_x4_IQP_Options_i150uA 2 14122 #define synce_x4_IQP_Options_i200uA 3 14123 #define synce_x4_IQP_Options_i250uA 4 14124 #define synce_x4_IQP_Options_i300uA 5 14125 #define synce_x4_IQP_Options_i350uA 6 14126 #define synce_x4_IQP_Options_i400uA 7 14127 #define synce_x4_IQP_Options_i450uA 8 14128 #define synce_x4_IQP_Options_i500uA 9 14129 #define synce_x4_IQP_Options_i550uA 10 14130 #define synce_x4_IQP_Options_i600uA 11 14131 #define synce_x4_IQP_Options_i650uA 12 14132 #define synce_x4_IQP_Options_i700uA 13 14133 #define synce_x4_IQP_Options_i750uA 14 14134 #define synce_x4_IQP_Options_i800uA 15 14135 14136 /**************************************************************************** 14137 * Enums: synce_x4_IDriver_Options 14138 */ 14139 #define synce_x4_IDriver_Options_v680mV 0 14140 #define synce_x4_IDriver_Options_v730mV 1 14141 #define synce_x4_IDriver_Options_v780mV 2 14142 #define synce_x4_IDriver_Options_v830mV 3 14143 #define synce_x4_IDriver_Options_v880mV 4 14144 #define synce_x4_IDriver_Options_v930mV 5 14145 #define synce_x4_IDriver_Options_v980mV 6 14146 #define synce_x4_IDriver_Options_v1010mV 7 14147 #define synce_x4_IDriver_Options_v1040mV 8 14148 #define synce_x4_IDriver_Options_v1060mV 9 14149 #define synce_x4_IDriver_Options_v1070mV 10 14150 #define synce_x4_IDriver_Options_v1080mV 11 14151 #define synce_x4_IDriver_Options_v1085mV 12 14152 #define synce_x4_IDriver_Options_v1090mV 13 14153 #define synce_x4_IDriver_Options_v1095mV 14 14154 #define synce_x4_IDriver_Options_v1100mV 15 14155 14156 /**************************************************************************** 14157 * Enums: synce_x4_operationModes 14158 */ 14159 #define synce_x4_operationModes_XGXS 0 14160 #define synce_x4_operationModes_XGXG_nCC 1 14161 #define synce_x4_operationModes_Indlane_OS8 4 14162 #define synce_x4_operationModes_IndLane_OS5 5 14163 #define synce_x4_operationModes_PCI 7 14164 #define synce_x4_operationModes_XGXS_nLQ 8 14165 #define synce_x4_operationModes_XGXS_nLQnCC 9 14166 #define synce_x4_operationModes_PBypass 10 14167 #define synce_x4_operationModes_PBypass_nDSK 11 14168 #define synce_x4_operationModes_ComboCoreMode 12 14169 #define synce_x4_operationModes_Clocks_off 15 14170 14171 /**************************************************************************** 14172 * Enums: synce_x4_actualSpeeds 14173 */ 14174 #define synce_x4_actualSpeeds_dr_10M 0 14175 #define synce_x4_actualSpeeds_dr_100M 1 14176 #define synce_x4_actualSpeeds_dr_1G 2 14177 #define synce_x4_actualSpeeds_dr_2p5G 3 14178 #define synce_x4_actualSpeeds_dr_5G_X4 4 14179 #define synce_x4_actualSpeeds_dr_6G_X4 5 14180 #define synce_x4_actualSpeeds_dr_10G_HiG 6 14181 #define synce_x4_actualSpeeds_dr_10G_CX4 7 14182 #define synce_x4_actualSpeeds_dr_12G_HiG 8 14183 #define synce_x4_actualSpeeds_dr_12p5G_X4 9 14184 #define synce_x4_actualSpeeds_dr_13G_X4 10 14185 #define synce_x4_actualSpeeds_dr_15G_X4 11 14186 #define synce_x4_actualSpeeds_dr_16G_X4 12 14187 #define synce_x4_actualSpeeds_dr_1G_KX 13 14188 #define synce_x4_actualSpeeds_dr_10G_KX4 14 14189 #define synce_x4_actualSpeeds_dr_10G_KR 15 14190 #define synce_x4_actualSpeeds_dr_5G 16 14191 #define synce_x4_actualSpeeds_dr_6p4G 17 14192 #define synce_x4_actualSpeeds_dr_20G_X4 18 14193 #define synce_x4_actualSpeeds_dr_21G_X4 19 14194 #define synce_x4_actualSpeeds_dr_25G_X4 20 14195 #define synce_x4_actualSpeeds_dr_10G_HiG_DXGXS 21 14196 #define synce_x4_actualSpeeds_dr_10G_DXGXS 22 14197 #define synce_x4_actualSpeeds_dr_10p5G_HiG_DXGXS 23 14198 #define synce_x4_actualSpeeds_dr_10p5G_DXGXS 24 14199 #define synce_x4_actualSpeeds_dr_12p773G_HiG_DXGXS 25 14200 #define synce_x4_actualSpeeds_dr_12p773G_DXGXS 26 14201 #define synce_x4_actualSpeeds_dr_10G_XFI 27 14202 #define synce_x4_actualSpeeds_dr_40G 28 14203 #define synce_x4_actualSpeeds_dr_20G_HiG_DXGXS 29 14204 #define synce_x4_actualSpeeds_dr_20G_DXGXS 30 14205 #define synce_x4_actualSpeeds_dr_10G_SFI 31 14206 #define synce_x4_actualSpeeds_dr_31p5G 32 14207 #define synce_x4_actualSpeeds_dr_32p7G 33 14208 #define synce_x4_actualSpeeds_dr_20G_SCR 34 14209 #define synce_x4_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 14210 #define synce_x4_actualSpeeds_dr_10G_DXGXS_SCR 36 14211 #define synce_x4_actualSpeeds_dr_12G_R2 37 14212 #define synce_x4_actualSpeeds_dr_10G_X2 38 14213 #define synce_x4_actualSpeeds_dr_40G_KR4 39 14214 #define synce_x4_actualSpeeds_dr_40G_CR4 40 14215 #define synce_x4_actualSpeeds_dr_100G_CR10 41 14216 #define synce_x4_actualSpeeds_dr_15p75G_DXGXS 44 14217 #define synce_x4_actualSpeeds_dr_20G_KR2 57 14218 #define synce_x4_actualSpeeds_dr_20G_CR2 58 14219 14220 /**************************************************************************** 14221 * Enums: synce_x4_actualSpeedsMisc1 14222 */ 14223 #define synce_x4_actualSpeedsMisc1_dr_2500BRCM_X1 16 14224 #define synce_x4_actualSpeedsMisc1_dr_5000BRCM_X4 17 14225 #define synce_x4_actualSpeedsMisc1_dr_6000BRCM_X4 18 14226 #define synce_x4_actualSpeedsMisc1_dr_10GHiGig_X4 19 14227 #define synce_x4_actualSpeedsMisc1_dr_10GBASE_CX4 20 14228 #define synce_x4_actualSpeedsMisc1_dr_12GHiGig_X4 21 14229 #define synce_x4_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 14230 #define synce_x4_actualSpeedsMisc1_dr_13GHiGig_X4 23 14231 #define synce_x4_actualSpeedsMisc1_dr_15GHiGig_X4 24 14232 #define synce_x4_actualSpeedsMisc1_dr_16GHiGig_X4 25 14233 #define synce_x4_actualSpeedsMisc1_dr_5000BRCM_X1 26 14234 #define synce_x4_actualSpeedsMisc1_dr_6363BRCM_X1 27 14235 #define synce_x4_actualSpeedsMisc1_dr_20GHiGig_X4 28 14236 #define synce_x4_actualSpeedsMisc1_dr_21GHiGig_X4 29 14237 #define synce_x4_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 14238 #define synce_x4_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 14239 14240 /**************************************************************************** 14241 * Enums: synce_x4_IndLaneModes 14242 */ 14243 #define synce_x4_IndLaneModes_SWSDR_div2 0 14244 #define synce_x4_IndLaneModes_SWSDR_div1 1 14245 #define synce_x4_IndLaneModes_DWSDR_div2 2 14246 #define synce_x4_IndLaneModes_DWSDR_div1 3 14247 14248 /**************************************************************************** 14249 * Enums: synce_x4_prbsSelect 14250 */ 14251 #define synce_x4_prbsSelect_prbs7 0 14252 #define synce_x4_prbsSelect_prbs15 1 14253 #define synce_x4_prbsSelect_prbs23 2 14254 #define synce_x4_prbsSelect_prbs31 3 14255 14256 /**************************************************************************** 14257 * Enums: synce_x4_vcoDivider 14258 */ 14259 #define synce_x4_vcoDivider_div32 0 14260 #define synce_x4_vcoDivider_div36 1 14261 #define synce_x4_vcoDivider_div40 2 14262 #define synce_x4_vcoDivider_div42 3 14263 #define synce_x4_vcoDivider_div48 4 14264 #define synce_x4_vcoDivider_div50 5 14265 #define synce_x4_vcoDivider_div52 6 14266 #define synce_x4_vcoDivider_div54 7 14267 #define synce_x4_vcoDivider_div60 8 14268 #define synce_x4_vcoDivider_div64 9 14269 #define synce_x4_vcoDivider_div66 10 14270 #define synce_x4_vcoDivider_div68 11 14271 #define synce_x4_vcoDivider_div70 12 14272 #define synce_x4_vcoDivider_div80 13 14273 #define synce_x4_vcoDivider_div92 14 14274 #define synce_x4_vcoDivider_div100 15 14275 14276 /**************************************************************************** 14277 * Enums: synce_x4_refClkSelect 14278 */ 14279 #define synce_x4_refClkSelect_clk_156p25MHz 1 14280 #define synce_x4_refClkSelect_clk_312p5Mhz 2 14281 14282 /**************************************************************************** 14283 * Enums: synce_x4_aerMMDdevTypeSelect 14284 */ 14285 #define synce_x4_aerMMDdevTypeSelect_combo_core 0 14286 #define synce_x4_aerMMDdevTypeSelect_PMA_PMD 1 14287 #define synce_x4_aerMMDdevTypeSelect_PCS 3 14288 #define synce_x4_aerMMDdevTypeSelect_PHY 4 14289 #define synce_x4_aerMMDdevTypeSelect_DTE 5 14290 #define synce_x4_aerMMDdevTypeSelect_CL73_AN 7 14291 14292 /**************************************************************************** 14293 * Enums: synce_x4_aerMMDportSelect 14294 */ 14295 #define synce_x4_aerMMDportSelect_ln0 0 14296 #define synce_x4_aerMMDportSelect_ln1 1 14297 #define synce_x4_aerMMDportSelect_ln2 2 14298 #define synce_x4_aerMMDportSelect_ln3 3 14299 #define synce_x4_aerMMDportSelect_BCST_ln0_1_2_3 511 14300 #define synce_x4_aerMMDportSelect_BCST_ln0_1 512 14301 #define synce_x4_aerMMDportSelect_BCST_ln2_3 513 14302 14303 /**************************************************************************** 14304 * Enums: synce_x4_firmwareModeSelect 14305 */ 14306 #define synce_x4_firmwareModeSelect_DEFAULT 0 14307 #define synce_x4_firmwareModeSelect_SFP_OPT_LR 1 14308 #define synce_x4_firmwareModeSelect_SFP_DAC 2 14309 #define synce_x4_firmwareModeSelect_XLAUI 3 14310 #define synce_x4_firmwareModeSelect_LONG_CH_6G 4 14311 14312 /**************************************************************************** 14313 * Enums: synce_x4_tempIdxSelect 14314 */ 14315 #define synce_x4_tempIdxSelect_LTE__22p9C 15 14316 #define synce_x4_tempIdxSelect_LTE__12p6C 14 14317 #define synce_x4_tempIdxSelect_LTE__3p0C 13 14318 #define synce_x4_tempIdxSelect_LTE_6p7C 12 14319 #define synce_x4_tempIdxSelect_LTE_16p4C 11 14320 #define synce_x4_tempIdxSelect_LTE_26p6C 10 14321 #define synce_x4_tempIdxSelect_LTE_36p3C 9 14322 #define synce_x4_tempIdxSelect_LTE_46p0C 8 14323 #define synce_x4_tempIdxSelect_LTE_56p2C 7 14324 #define synce_x4_tempIdxSelect_LTE_65p9C 6 14325 #define synce_x4_tempIdxSelect_LTE_75p6C 5 14326 #define synce_x4_tempIdxSelect_LTE_85p3C 4 14327 #define synce_x4_tempIdxSelect_LTE_95p5C 3 14328 #define synce_x4_tempIdxSelect_LTE_105p2C 2 14329 #define synce_x4_tempIdxSelect_LTE_114p9C 1 14330 #define synce_x4_tempIdxSelect_LTE_125p1C 0 14331 14332 /**************************************************************************** 14333 * Enums: synce_x4_port_mode 14334 */ 14335 #define synce_x4_port_mode_QUAD_PORT 0 14336 #define synce_x4_port_mode_TRI_1_PORT 1 14337 #define synce_x4_port_mode_TRI_2_PORT 2 14338 #define synce_x4_port_mode_DUAL_PORT 3 14339 #define synce_x4_port_mode_SINGLE_PORT 4 14340 #define synce_x4_port_mode_SINGLE_OCTAL_PORT 5 14341 14342 /**************************************************************************** 14343 * Enums: synce_x4_rev_letter_enum 14344 */ 14345 #define synce_x4_rev_letter_enum_REV_A 0 14346 #define synce_x4_rev_letter_enum_REV_B 1 14347 #define synce_x4_rev_letter_enum_REV_C 2 14348 #define synce_x4_rev_letter_enum_REV_D 3 14349 14350 /**************************************************************************** 14351 * Enums: synce_x4_rev_number_enum 14352 */ 14353 #define synce_x4_rev_number_enum_REV_0 0 14354 #define synce_x4_rev_number_enum_REV_1 1 14355 #define synce_x4_rev_number_enum_REV_2 2 14356 #define synce_x4_rev_number_enum_REV_3 3 14357 #define synce_x4_rev_number_enum_REV_4 4 14358 #define synce_x4_rev_number_enum_REV_5 5 14359 #define synce_x4_rev_number_enum_REV_6 6 14360 #define synce_x4_rev_number_enum_REV_7 7 14361 14362 /**************************************************************************** 14363 * Enums: synce_x4_bonding_enum 14364 */ 14365 #define synce_x4_bonding_enum_WIRE_BOND 0 14366 #define synce_x4_bonding_enum_FLIP_CHIP 1 14367 14368 /**************************************************************************** 14369 * Enums: synce_x4_tech_process 14370 */ 14371 #define synce_x4_tech_process_PROCESS_90NM 0 14372 #define synce_x4_tech_process_PROCESS_65NM 1 14373 #define synce_x4_tech_process_PROCESS_40NM 2 14374 #define synce_x4_tech_process_PROCESS_28NM 3 14375 #define synce_x4_tech_process_PROCESS_16NM 4 14376 14377 /**************************************************************************** 14378 * Enums: synce_x4_model_num 14379 */ 14380 #define synce_x4_model_num_SERDES_CL73 0 14381 #define synce_x4_model_num_XGXS_16G 1 14382 #define synce_x4_model_num_HYPERCORE 2 14383 #define synce_x4_model_num_HYPERLITE 3 14384 #define synce_x4_model_num_PCIE_G2_PIPE 4 14385 #define synce_x4_model_num_SERDES_1p25GBd 5 14386 #define synce_x4_model_num_SATA2 6 14387 #define synce_x4_model_num_QSGMII 7 14388 #define synce_x4_model_num_XGXS10G 8 14389 #define synce_x4_model_num_WARPCORE 9 14390 #define synce_x4_model_num_XFICORE 10 14391 #define synce_x4_model_num_RXFI 11 14392 #define synce_x4_model_num_WARPLITE 12 14393 #define synce_x4_model_num_PENTACORE 13 14394 #define synce_x4_model_num_ESM 14 14395 #define synce_x4_model_num_QUAD_SGMII 15 14396 #define synce_x4_model_num_WARPCORE_3 16 14397 #define synce_x4_model_num_TSC 17 14398 #define synce_x4_model_num_TSC4E 18 14399 #define synce_x4_model_num_TSC12E 19 14400 #define synce_x4_model_num_TSC4F 20 14401 #define synce_x4_model_num_TSC4F_GEN2 21 14402 #define synce_x4_model_num_XGXS_CL73_90NM 29 14403 #define synce_x4_model_num_SERDES_CL73_90NM 30 14404 #define synce_x4_model_num_WARPCORE3 32 14405 #define synce_x4_model_num_WARPCORE4_TSC 33 14406 #define synce_x4_model_num_RXAUI 34 14407 #define synce_x4_model_num_TSCE_GEN3 35 14408 #define synce_x4_model_num_TSC4F_GEN3 36 14409 #define synce_x4_model_num_TSCBH 37 14410 14411 /**************************************************************************** 14412 * Enums: synce_x4_payload 14413 */ 14414 #define synce_x4_payload_REPEAT_2_BYTES 0 14415 #define synce_x4_payload_RAMPING 1 14416 #define synce_x4_payload_CL48_CRPAT 2 14417 #define synce_x4_payload_CL48_CJPAT 3 14418 #define synce_x4_payload_CL36_LONG_CRPAT 4 14419 #define synce_x4_payload_CL36_SHORT_CRPAT 5 14420 14421 /**************************************************************************** 14422 * Enums: synce_x4_sc 14423 */ 14424 #define synce_x4_sc_SPEED_10G_IEEE_KR1 0 14425 #define synce_x4_sc_SPEED_25G_IEEE_KS1_CS1 1 14426 #define synce_x4_sc_SPEED_25G_IEEE_KR1_CR1 2 14427 #define synce_x4_sc_SPEED_40G_IEEE_KR4 3 14428 #define synce_x4_sc_SPEED_40G_IEEE_CR4 4 14429 #define synce_x4_sc_SPEED_50G_IEEE_KR1_CR1 5 14430 #define synce_x4_sc_SPEED_100G_IEEE_KR4 6 14431 #define synce_x4_sc_SPEED_100G_IEEE_CR4 7 14432 #define synce_x4_sc_SPEED_100G_IEEE_KR2_CR2 8 14433 #define synce_x4_sc_SPEED_200G_IEEE_KR4_CR4 9 14434 #define synce_x4_sc_SPEED_400G_IEEE_X8 10 14435 #define synce_x4_sc_SPEED_CL73_IEEE_20GVCO 11 14436 #define synce_x4_sc_SPEED_CL73_IEEE_25GVCO 12 14437 #define synce_x4_sc_SPEED_CL73_IEEE_26GVCO 13 14438 #define synce_x4_sc_SPEED_20G_BRCM_CR1 14 14439 #define synce_x4_sc_SPEED_20G_BRCM_KR1 15 14440 #define synce_x4_sc_SPEED_25G_BRCM_CR1 16 14441 #define synce_x4_sc_SPEED_25G_BRCM_KR1 17 14442 #define synce_x4_sc_SPEED_40G_BRCM_CR2 18 14443 #define synce_x4_sc_SPEED_40G_BRCM_KR2 19 14444 #define synce_x4_sc_SPEED_50G_BRCM_CR2 20 14445 #define synce_x4_sc_SPEED_50G_BRCM_KR2 21 14446 #define synce_x4_sc_SPEED_50G_BRCM_CR4 22 14447 #define synce_x4_sc_SPEED_50G_BRCM_KR4 23 14448 #define synce_x4_sc_SPEED_50G_BRCM_FEC_544_CR2_KR2 24 14449 #define synce_x4_sc_SPEED_RESERVED_19 25 14450 #define synce_x4_sc_SPEED_50G_BRCM_FEC_544_CR1_KR1 26 14451 #define synce_x4_sc_SPEED_50G_BRCM_NO_FEC_CR1_KR1 27 14452 #define synce_x4_sc_SPEED_50G_BRCM_FEC_528_CR1_KR1 28 14453 #define synce_x4_sc_SPEED_400G_BRCM_NO_FEC_KR8_CR8 29 14454 #define synce_x4_sc_SPEED_400G_BRCM_FEC_KR8_CR8 30 14455 #define synce_x4_sc_SPEED_200G_BRCM_NO_FEC_KR4_CR4 31 14456 #define synce_x4_sc_SPEED_200G_BRCM_KR4_CR4 32 14457 #define synce_x4_sc_SPEED_100G_BRCM_KR4_CR4 33 14458 #define synce_x4_sc_SPEED_RESERVED_22 34 14459 #define synce_x4_sc_SPEED_100G_BRCM_FEC_528_KR2_CR2 35 14460 #define synce_x4_sc_SPEED_100G_BRCM_NO_FEC_KR2_CR2 36 14461 #define synce_x4_sc_SPEED_100G_BRCM_NO_FEC_X4 37 14462 14463 /**************************************************************************** 14464 * Enums: synce_x4_t_fifo_modes 14465 */ 14466 #define synce_x4_t_fifo_modes_T_FIFO_INSERT_NO_AM 0 14467 #define synce_x4_t_fifo_modes_T_FIFO_INSERT_4_AM 1 14468 #define synce_x4_t_fifo_modes_T_FIFO_INSERT_20_AM 2 14469 #define synce_x4_t_fifo_modes_T_FIFO_INSERT_2_AM 3 14470 14471 /**************************************************************************** 14472 * Enums: synce_x4_t_enc_modes 14473 */ 14474 #define synce_x4_t_enc_modes_T_ENC_MODE_BYPASS 0 14475 #define synce_x4_t_enc_modes_T_ENC_MODE_CL49 1 14476 #define synce_x4_t_enc_modes_T_ENC_MODE_CL82 2 14477 14478 /**************************************************************************** 14479 * Enums: synce_x4_btmx_mode 14480 */ 14481 #define synce_x4_btmx_mode_BS_BTMX_MODE_1to1 0 14482 #define synce_x4_btmx_mode_BS_BTMX_MODE_2to1 1 14483 #define synce_x4_btmx_mode_BS_BTMX_MODE_5to1 2 14484 14485 /**************************************************************************** 14486 * Enums: synce_x4_t_type_cl82 14487 */ 14488 #define synce_x4_t_type_cl82_T_TYPE_B1 5 14489 #define synce_x4_t_type_cl82_T_TYPE_C 4 14490 #define synce_x4_t_type_cl82_T_TYPE_S 3 14491 #define synce_x4_t_type_cl82_T_TYPE_T 2 14492 #define synce_x4_t_type_cl82_T_TYPE_D 1 14493 #define synce_x4_t_type_cl82_T_TYPE_E 0 14494 14495 /**************************************************************************** 14496 * Enums: synce_x4_txsm_state_cl82 14497 */ 14498 #define synce_x4_txsm_state_cl82_TX_E 4 14499 #define synce_x4_txsm_state_cl82_TX_T 3 14500 #define synce_x4_txsm_state_cl82_TX_D 2 14501 #define synce_x4_txsm_state_cl82_TX_C 1 14502 #define synce_x4_txsm_state_cl82_TX_INIT 0 14503 14504 /**************************************************************************** 14505 * Enums: synce_x4_ltxsm_state_cl82 14506 */ 14507 #define synce_x4_ltxsm_state_cl82_TX_E 16 14508 #define synce_x4_ltxsm_state_cl82_TX_T 8 14509 #define synce_x4_ltxsm_state_cl82_TX_D 4 14510 #define synce_x4_ltxsm_state_cl82_TX_C 2 14511 #define synce_x4_ltxsm_state_cl82_TX_INIT 1 14512 14513 /**************************************************************************** 14514 * Enums: synce_x4_r_type_coded_cl82 14515 */ 14516 #define synce_x4_r_type_coded_cl82_R_TYPE_B1 32 14517 #define synce_x4_r_type_coded_cl82_R_TYPE_C 16 14518 #define synce_x4_r_type_coded_cl82_R_TYPE_S 8 14519 #define synce_x4_r_type_coded_cl82_R_TYPE_T 4 14520 #define synce_x4_r_type_coded_cl82_R_TYPE_D 2 14521 #define synce_x4_r_type_coded_cl82_R_TYPE_E 1 14522 14523 /**************************************************************************** 14524 * Enums: synce_x4_rxsm_state_cl82 14525 */ 14526 #define synce_x4_rxsm_state_cl82_RX_E 16 14527 #define synce_x4_rxsm_state_cl82_RX_T 8 14528 #define synce_x4_rxsm_state_cl82_RX_D 4 14529 #define synce_x4_rxsm_state_cl82_RX_C 2 14530 #define synce_x4_rxsm_state_cl82_RX_INIT 1 14531 14532 /**************************************************************************** 14533 * Enums: synce_x4_deskew_state 14534 */ 14535 #define synce_x4_deskew_state_ALIGN_ACQUIRED 2 14536 #define synce_x4_deskew_state_LOSS_OF_ALIGNMENT 1 14537 14538 /**************************************************************************** 14539 * Enums: synce_x4_os_mode_enum 14540 */ 14541 #define synce_x4_os_mode_enum_OS_MODE_1 0 14542 #define synce_x4_os_mode_enum_OS_MODE_2 1 14543 #define synce_x4_os_mode_enum_OS_MODE_4 2 14544 #define synce_x4_os_mode_enum_OS_MODE_16p5 8 14545 #define synce_x4_os_mode_enum_OS_MODE_20p625 12 14546 14547 /**************************************************************************** 14548 * Enums: synce_x4_scr_modes 14549 */ 14550 #define synce_x4_scr_modes_T_SCR_MODE_BYPASS 0 14551 #define synce_x4_scr_modes_T_SCR_MODE_CL49 1 14552 #define synce_x4_scr_modes_T_SCR_MODE_40G_2_LANE 2 14553 #define synce_x4_scr_modes_T_SCR_MODE_100G 3 14554 #define synce_x4_scr_modes_T_SCR_MODE_20G 4 14555 #define synce_x4_scr_modes_T_SCR_MODE_40G_4_LANE 5 14556 14557 /**************************************************************************** 14558 * Enums: synce_x4_descr_modes 14559 */ 14560 #define synce_x4_descr_modes_R_DESCR_MODE_BYPASS 0 14561 #define synce_x4_descr_modes_R_DESCR_MODE_CL49 1 14562 #define synce_x4_descr_modes_R_DESCR_MODE_CL82 2 14563 14564 /**************************************************************************** 14565 * Enums: synce_x4_r_dec_tl_mode 14566 */ 14567 #define synce_x4_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 14568 #define synce_x4_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 14569 #define synce_x4_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 14570 14571 /**************************************************************************** 14572 * Enums: synce_x4_r_dec_fsm_mode 14573 */ 14574 #define synce_x4_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 14575 #define synce_x4_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 14576 #define synce_x4_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 14577 14578 /**************************************************************************** 14579 * Enums: synce_x4_r_deskew_mode 14580 */ 14581 #define synce_x4_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 14582 #define synce_x4_r_deskew_mode_R_DESKEW_MODE_20G 1 14583 #define synce_x4_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 14584 #define synce_x4_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 14585 #define synce_x4_r_deskew_mode_R_DESKEW_MODE_100G 4 14586 #define synce_x4_r_deskew_mode_R_DESKEW_MODE_CL49 5 14587 #define synce_x4_r_deskew_mode_R_DESKEW_MODE_CL91_QUAD 6 14588 #define synce_x4_r_deskew_mode_R_DESKEW_MODE_CL91_SINGLE_BRCM 7 14589 #define synce_x4_r_deskew_mode_R_DESKEW_MODE_CL91_DUAL_BRCM 8 14590 #define synce_x4_r_deskew_mode_R_DESKEW_MODE_CL91_FC 9 14591 14592 /**************************************************************************** 14593 * Enums: synce_x4_bs_dist_modes 14594 */ 14595 #define synce_x4_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 14596 #define synce_x4_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 14597 #define synce_x4_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 14598 #define synce_x4_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 14599 14600 /**************************************************************************** 14601 * Enums: synce_x4_cl49_t_type 14602 */ 14603 #define synce_x4_cl49_t_type_BAD_T_TYPE 15 14604 #define synce_x4_cl49_t_type_T_TYPE_B0 11 14605 #define synce_x4_cl49_t_type_T_TYPE_OB 10 14606 #define synce_x4_cl49_t_type_T_TYPE_B1 9 14607 #define synce_x4_cl49_t_type_T_TYPE_DB 8 14608 #define synce_x4_cl49_t_type_T_TYPE_FC 7 14609 #define synce_x4_cl49_t_type_T_TYPE_TB 6 14610 #define synce_x4_cl49_t_type_T_TYPE_LI 5 14611 #define synce_x4_cl49_t_type_T_TYPE_C 4 14612 #define synce_x4_cl49_t_type_T_TYPE_S 3 14613 #define synce_x4_cl49_t_type_T_TYPE_T 2 14614 #define synce_x4_cl49_t_type_T_TYPE_D 1 14615 #define synce_x4_cl49_t_type_T_TYPE_E 0 14616 14617 /**************************************************************************** 14618 * Enums: synce_x4_cl49_txsm_states 14619 */ 14620 #define synce_x4_cl49_txsm_states_TX_LI 5 14621 #define synce_x4_cl49_txsm_states_TX_E 4 14622 #define synce_x4_cl49_txsm_states_TX_T 3 14623 #define synce_x4_cl49_txsm_states_TX_D 2 14624 #define synce_x4_cl49_txsm_states_TX_C 1 14625 #define synce_x4_cl49_txsm_states_TX_INIT 0 14626 14627 /**************************************************************************** 14628 * Enums: synce_x4_cl49_ltxsm_states 14629 */ 14630 #define synce_x4_cl49_ltxsm_states_TX_LI 32 14631 #define synce_x4_cl49_ltxsm_states_TX_E 16 14632 #define synce_x4_cl49_ltxsm_states_TX_T 8 14633 #define synce_x4_cl49_ltxsm_states_TX_D 4 14634 #define synce_x4_cl49_ltxsm_states_TX_C 2 14635 #define synce_x4_cl49_ltxsm_states_TX_INIT 1 14636 14637 /**************************************************************************** 14638 * Enums: synce_x4_burst_error_mode 14639 */ 14640 #define synce_x4_burst_error_mode_BURST_ERROR_11_BITS 0 14641 #define synce_x4_burst_error_mode_BURST_ERROR_16_BITS 1 14642 #define synce_x4_burst_error_mode_BURST_ERROR_17_BITS 2 14643 #define synce_x4_burst_error_mode_BURST_ERROR_18_BITS 3 14644 #define synce_x4_burst_error_mode_BURST_ERROR_19_BITS 4 14645 #define synce_x4_burst_error_mode_BURST_ERROR_20_BITS 5 14646 #define synce_x4_burst_error_mode_BURST_ERROR_21_BITS 6 14647 #define synce_x4_burst_error_mode_BURST_ERROR_22_BITS 7 14648 #define synce_x4_burst_error_mode_BURST_ERROR_23_BITS 8 14649 #define synce_x4_burst_error_mode_BURST_ERROR_24_BITS 9 14650 #define synce_x4_burst_error_mode_BURST_ERROR_25_BITS 10 14651 #define synce_x4_burst_error_mode_BURST_ERROR_26_BITS 11 14652 #define synce_x4_burst_error_mode_BURST_ERROR_27_BITS 12 14653 #define synce_x4_burst_error_mode_BURST_ERROR_28_BITS 13 14654 #define synce_x4_burst_error_mode_BURST_ERROR_29_BITS 14 14655 #define synce_x4_burst_error_mode_BURST_ERROR_30_BITS 15 14656 #define synce_x4_burst_error_mode_BURST_ERROR_31_BITS 16 14657 #define synce_x4_burst_error_mode_BURST_ERROR_32_BITS 17 14658 #define synce_x4_burst_error_mode_BURST_ERROR_33_BITS 18 14659 #define synce_x4_burst_error_mode_BURST_ERROR_34_BITS 19 14660 #define synce_x4_burst_error_mode_BURST_ERROR_35_BITS 20 14661 #define synce_x4_burst_error_mode_BURST_ERROR_36_BITS 21 14662 #define synce_x4_burst_error_mode_BURST_ERROR_37_BITS 22 14663 #define synce_x4_burst_error_mode_BURST_ERROR_38_BITS 23 14664 #define synce_x4_burst_error_mode_BURST_ERROR_39_BITS 24 14665 #define synce_x4_burst_error_mode_BURST_ERROR_40_BITS 25 14666 #define synce_x4_burst_error_mode_BURST_ERROR_41_BITS 26 14667 14668 /**************************************************************************** 14669 * Enums: synce_x4_bermon_state 14670 */ 14671 #define synce_x4_bermon_state_HI_BER 4 14672 #define synce_x4_bermon_state_GOOD_BER 3 14673 #define synce_x4_bermon_state_BER_TEST_SH 2 14674 #define synce_x4_bermon_state_START_TIMER 1 14675 #define synce_x4_bermon_state_BER_MT_INIT 0 14676 14677 /**************************************************************************** 14678 * Enums: synce_x4_rxsm_state_cl49 14679 */ 14680 #define synce_x4_rxsm_state_cl49_RX_LI 32 14681 #define synce_x4_rxsm_state_cl49_RX_E 16 14682 #define synce_x4_rxsm_state_cl49_RX_T 8 14683 #define synce_x4_rxsm_state_cl49_RX_D 4 14684 #define synce_x4_rxsm_state_cl49_RX_C 2 14685 #define synce_x4_rxsm_state_cl49_RX_INIT 1 14686 14687 /**************************************************************************** 14688 * Enums: synce_x4_r_type 14689 */ 14690 #define synce_x4_r_type_BAD_R_TYPE 15 14691 #define synce_x4_r_type_R_TYPE_B0 11 14692 #define synce_x4_r_type_R_TYPE_OB 10 14693 #define synce_x4_r_type_R_TYPE_B1 9 14694 #define synce_x4_r_type_R_TYPE_DB 8 14695 #define synce_x4_r_type_R_TYPE_FC 7 14696 #define synce_x4_r_type_R_TYPE_TB 6 14697 #define synce_x4_r_type_R_TYPE_LI 5 14698 #define synce_x4_r_type_R_TYPE_C 4 14699 #define synce_x4_r_type_R_TYPE_S 3 14700 #define synce_x4_r_type_R_TYPE_T 2 14701 #define synce_x4_r_type_R_TYPE_D 1 14702 #define synce_x4_r_type_R_TYPE_E 0 14703 14704 /**************************************************************************** 14705 * Enums: synce_x4_am_lock_state 14706 */ 14707 #define synce_x4_am_lock_state_INVALID_AM 512 14708 #define synce_x4_am_lock_state_GOOD_AM 256 14709 #define synce_x4_am_lock_state_COMP_AM 128 14710 #define synce_x4_am_lock_state_TIMER_2 64 14711 #define synce_x4_am_lock_state_AM_2_GOOD 32 14712 #define synce_x4_am_lock_state_COMP_2ND 16 14713 #define synce_x4_am_lock_state_TIMER_1 8 14714 #define synce_x4_am_lock_state_FIND_1ST 4 14715 #define synce_x4_am_lock_state_AM_RESET_CNT 2 14716 #define synce_x4_am_lock_state_AM_LOCK_INIT 1 14717 14718 /**************************************************************************** 14719 * Enums: synce_x4_msg_selector 14720 */ 14721 #define synce_x4_msg_selector_RESERVED 0 14722 #define synce_x4_msg_selector_VALUE_802p3 1 14723 #define synce_x4_msg_selector_VALUE_802p9 2 14724 #define synce_x4_msg_selector_VALUE_802p5 3 14725 #define synce_x4_msg_selector_VALUE_1394 4 14726 14727 /**************************************************************************** 14728 * Enums: synce_x4_synce_enum_stage1 14729 */ 14730 #define synce_x4_synce_enum_stage1_SYNCE_NO_DIV 0 14731 #define synce_x4_synce_enum_stage1_SYNCE_DIV_7 1 14732 #define synce_x4_synce_enum_stage1_SYNCE_DIV_11 2 14733 14734 /**************************************************************************** 14735 * Enums: synce_x4_synce_enum_stage0 14736 */ 14737 #define synce_x4_synce_enum_stage0_SYNCE_NO_DIV 0 14738 #define synce_x4_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 14739 #define synce_x4_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 14740 14741 /**************************************************************************** 14742 * Enums: synce_x4_cl91_sync_state 14743 */ 14744 #define synce_x4_cl91_sync_state_FIND_1ST 0 14745 #define synce_x4_cl91_sync_state_COUNT_NEXT 1 14746 #define synce_x4_cl91_sync_state_COMP_2ND 2 14747 #define synce_x4_cl91_sync_state_TWO_GOOD 3 14748 14749 /**************************************************************************** 14750 * Enums: synce_x4_RS_FEC_sync_state 14751 */ 14752 #define synce_x4_RS_FEC_sync_state_LOCK_INIT 0 14753 #define synce_x4_RS_FEC_sync_state_FIND_1ST 1 14754 #define synce_x4_RS_FEC_sync_state_COUNT_NEXT 2 14755 #define synce_x4_RS_FEC_sync_state_COMP_2ND 3 14756 #define synce_x4_RS_FEC_sync_state_TWO_GOOD 4 14757 14758 /**************************************************************************** 14759 * Enums: synce_x4_cl91_algn_state 14760 */ 14761 #define synce_x4_cl91_algn_state_LOSS_OF_ALIGNMENT 0 14762 #define synce_x4_cl91_algn_state_DESKEW 1 14763 #define synce_x4_cl91_algn_state_DESKEW_FAIL 2 14764 #define synce_x4_cl91_algn_state_ALIGN_ACQUIRED 3 14765 #define synce_x4_cl91_algn_state_CW_GOOD 4 14766 #define synce_x4_cl91_algn_state_CW_BAD 5 14767 #define synce_x4_cl91_algn_state_THREE_BAD 6 14768 14769 /**************************************************************************** 14770 * Enums: synce_x4_RS_FEC_algn_state 14771 */ 14772 #define synce_x4_RS_FEC_algn_state_LOSS_OF_ALIGNMENT 0 14773 #define synce_x4_RS_FEC_algn_state_DESKEW 1 14774 #define synce_x4_RS_FEC_algn_state_DESKEW_FAIL 2 14775 #define synce_x4_RS_FEC_algn_state_ALIGN_ACQUIRED 3 14776 #define synce_x4_RS_FEC_algn_state_CW_GOOD 4 14777 #define synce_x4_RS_FEC_algn_state_CW_BAD 5 14778 #define synce_x4_RS_FEC_algn_state_THREE_BAD 6 14779 14780 /**************************************************************************** 14781 * Enums: synce_x4_fec_sel_override 14782 */ 14783 #define synce_x4_fec_sel_override_NO_OVERRIDE 0 14784 #define synce_x4_fec_sel_override_NO_FEC 1 14785 #define synce_x4_fec_sel_override_FEC_CL74 2 14786 #define synce_x4_fec_sel_override_FEC_CL91 3 14787 14788 /**************************************************************************** 14789 * Enums: synce_x4_cl91_blksync_mode 14790 */ 14791 #define synce_x4_cl91_blksync_mode_R_BLKSYNC_NO_CL91_FEC 0 14792 #define synce_x4_cl91_blksync_mode_R_BLKSYNC_CL91_QUAD_LANE_FEC 1 14793 #define synce_x4_cl91_blksync_mode_R_BLKSYNC_CL91_DUAL_LANE_FEC 2 14794 #define synce_x4_cl91_blksync_mode_R_BLKSYNC_CL91_SINGLE_LANE_FEC 3 14795 #define synce_x4_cl91_blksync_mode_R_BLKSYNC_CL91_FC_FEC 4 14796 14797 /**************************************************************************** 14798 * Enums: synce_x4_r_merge_mode 14799 */ 14800 #define synce_x4_r_merge_mode_R_MERGE_MODE_BYPASS 0 14801 #define synce_x4_r_merge_mode_R_MERGE_MODE_CL91_FC 1 14802 #define synce_x4_r_merge_mode_R_MERGE_MODE_CL91_SINGLE_LANE 2 14803 #define synce_x4_r_merge_mode_R_MERGE_MODE_CL91_DUAL_LANE 3 14804 #define synce_x4_r_merge_mode_R_MERGE_MODE_CL91_QUAD_LANE 4 14805 14806 /**************************************************************************** 14807 * Enums: synce_x4_r_tc_mode 14808 */ 14809 #define synce_x4_r_tc_mode_R_TC_MODE_SINGLE 0 14810 #define synce_x4_r_tc_mode_R_TC_MODE_DUAL 1 14811 #define synce_x4_r_tc_mode_R_TC_MODE_QUAD 2 14812 14813 /**************************************************************************** 14814 * Enums: synce_x4_r_tc_out_mode 14815 */ 14816 #define synce_x4_r_tc_out_mode_R_TC_OUT_MODE_SINGLE 0 14817 #define synce_x4_r_tc_out_mode_R_TC_OUT_MODE_DUAL 1 14818 #define synce_x4_r_tc_out_mode_R_TC_OUT_MODE_QUAD 2 14819 14820 /**************************************************************************** 14821 * Enums: synce_x4_cl91_fec_mode 14822 */ 14823 #define synce_x4_cl91_fec_mode_NO_CL91_FEC 0 14824 #define synce_x4_cl91_fec_mode_CL91_SINGLE_LANE_FC 1 14825 #define synce_x4_cl91_fec_mode_CL91_SINGLE_LANE_BRCM_PROP 2 14826 #define synce_x4_cl91_fec_mode_CL91_DUAL_LANE_BRCM_PROP 3 14827 #define synce_x4_cl91_fec_mode_CL91_QUAD_LANE 4 14828 #define synce_x4_cl91_fec_mode_IEEE_25G_CL91_SINGLE_LANE 5 14829 14830 /**************************************************************************** 14831 * Enums: synce_x4_RS_FEC_fec_mode 14832 */ 14833 #define synce_x4_RS_FEC_fec_mode_NO_RS_FEC_FEC 0 14834 #define synce_x4_RS_FEC_fec_mode_N_A 1 14835 #define synce_x4_RS_FEC_fec_mode_RS_FEC_SINGLE_LANE_BRCM_PROP 2 14836 #define synce_x4_RS_FEC_fec_mode_RS_FEC_DUAL_LANE_BRCM_PROP 3 14837 #define synce_x4_RS_FEC_fec_mode_RS_FEC_QUAD_LANE 4 14838 #define synce_x4_RS_FEC_fec_mode_IEEE_25G_RS_FEC_SINGLE_LANE 5 14839 14840 /**************************************************************************** 14841 * Enums: synce_x4_am_spacing_mul 14842 */ 14843 #define synce_x4_am_spacing_mul_AM_SPACING_MUL_2 0 14844 #define synce_x4_am_spacing_mul_AM_SPACING_MUL_4 1 14845 #define synce_x4_am_spacing_mul_AM_SPACING_MUL_5 2 14846 #define synce_x4_am_spacing_mul_AM_SPACING_MUL_20 3 14847 14848 /**************************************************************************** 14849 * Enums: testshared0_cl36TxEEEStates_l 14850 */ 14851 #define testshared0_cl36TxEEEStates_l_TX_REFRESH 8 14852 #define testshared0_cl36TxEEEStates_l_TX_QUIET 4 14853 #define testshared0_cl36TxEEEStates_l_TX_SLEEP 2 14854 #define testshared0_cl36TxEEEStates_l_TX_ACTIVE 1 14855 14856 /**************************************************************************** 14857 * Enums: testshared0_cl36TxEEEStates_c 14858 */ 14859 #define testshared0_cl36TxEEEStates_c_TX_REFRESH 3 14860 #define testshared0_cl36TxEEEStates_c_TX_QUIET 2 14861 #define testshared0_cl36TxEEEStates_c_TX_SLEEP 1 14862 #define testshared0_cl36TxEEEStates_c_TX_ACTIVE 0 14863 14864 /**************************************************************************** 14865 * Enums: testshared0_cl49TxEEEStates_l 14866 */ 14867 #define testshared0_cl49TxEEEStates_l_SCR_RESET_2 64 14868 #define testshared0_cl49TxEEEStates_l_SCR_RESET_1 32 14869 #define testshared0_cl49TxEEEStates_l_TX_WAKE 16 14870 #define testshared0_cl49TxEEEStates_l_TX_REFRESH 8 14871 #define testshared0_cl49TxEEEStates_l_TX_QUIET 4 14872 #define testshared0_cl49TxEEEStates_l_TX_SLEEP 2 14873 #define testshared0_cl49TxEEEStates_l_TX_ACTIVE 1 14874 14875 /**************************************************************************** 14876 * Enums: testshared0_fec_req_enum 14877 */ 14878 #define testshared0_fec_req_enum_FEC_not_supported 0 14879 #define testshared0_fec_req_enum_FEC_supported_but_not_requested 1 14880 #define testshared0_fec_req_enum_invalid_setting 2 14881 #define testshared0_fec_req_enum_FEC_supported_and_requested 3 14882 14883 /**************************************************************************** 14884 * Enums: testshared0_cl73_pause_enum 14885 */ 14886 #define testshared0_cl73_pause_enum_No_PAUSE_ability 0 14887 #define testshared0_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 14888 #define testshared0_cl73_pause_enum_Symmetric_PAUSE_ability 1 14889 #define testshared0_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 14890 14891 /**************************************************************************** 14892 * Enums: testshared0_cl49TxEEEStates_c 14893 */ 14894 #define testshared0_cl49TxEEEStates_c_SCR_RESET_2 6 14895 #define testshared0_cl49TxEEEStates_c_SCR_RESET_1 5 14896 #define testshared0_cl49TxEEEStates_c_TX_WAKE 4 14897 #define testshared0_cl49TxEEEStates_c_TX_REFRESH 3 14898 #define testshared0_cl49TxEEEStates_c_TX_QUIET 2 14899 #define testshared0_cl49TxEEEStates_c_TX_SLEEP 1 14900 #define testshared0_cl49TxEEEStates_c_TX_ACTIVE 0 14901 14902 /**************************************************************************** 14903 * Enums: testshared0_cl36RxEEEStates_l 14904 */ 14905 #define testshared0_cl36RxEEEStates_l_RX_LINK_FAIL 32 14906 #define testshared0_cl36RxEEEStates_l_RX_WTF 16 14907 #define testshared0_cl36RxEEEStates_l_RX_WAKE 8 14908 #define testshared0_cl36RxEEEStates_l_RX_QUIET 4 14909 #define testshared0_cl36RxEEEStates_l_RX_SLEEP 2 14910 #define testshared0_cl36RxEEEStates_l_RX_ACTIVE 1 14911 14912 /**************************************************************************** 14913 * Enums: testshared0_cl36RxEEEStates_c 14914 */ 14915 #define testshared0_cl36RxEEEStates_c_RX_LINK_FAIL 5 14916 #define testshared0_cl36RxEEEStates_c_RX_WTF 4 14917 #define testshared0_cl36RxEEEStates_c_RX_WAKE 3 14918 #define testshared0_cl36RxEEEStates_c_RX_QUIET 2 14919 #define testshared0_cl36RxEEEStates_c_RX_SLEEP 1 14920 #define testshared0_cl36RxEEEStates_c_RX_ACTIVE 0 14921 14922 /**************************************************************************** 14923 * Enums: testshared0_cl49RxEEEStates_l 14924 */ 14925 #define testshared0_cl49RxEEEStates_l_RX_LINK_FAIL 32 14926 #define testshared0_cl49RxEEEStates_l_RX_WTF 16 14927 #define testshared0_cl49RxEEEStates_l_RX_WAKE 8 14928 #define testshared0_cl49RxEEEStates_l_RX_QUIET 4 14929 #define testshared0_cl49RxEEEStates_l_RX_SLEEP 2 14930 #define testshared0_cl49RxEEEStates_l_RX_ACTIVE 1 14931 14932 /**************************************************************************** 14933 * Enums: testshared0_cl49RxEEEStates_c 14934 */ 14935 #define testshared0_cl49RxEEEStates_c_RX_LINK_FAIL 5 14936 #define testshared0_cl49RxEEEStates_c_RX_WTF 4 14937 #define testshared0_cl49RxEEEStates_c_RX_WAKE 3 14938 #define testshared0_cl49RxEEEStates_c_RX_QUIET 2 14939 #define testshared0_cl49RxEEEStates_c_RX_SLEEP 1 14940 #define testshared0_cl49RxEEEStates_c_RX_ACTIVE 0 14941 14942 /**************************************************************************** 14943 * Enums: testshared0_cl48TxEEEStates_l 14944 */ 14945 #define testshared0_cl48TxEEEStates_l_TX_REFRESH 8 14946 #define testshared0_cl48TxEEEStates_l_TX_QUIET 4 14947 #define testshared0_cl48TxEEEStates_l_TX_SLEEP 2 14948 #define testshared0_cl48TxEEEStates_l_TX_ACTIVE 1 14949 14950 /**************************************************************************** 14951 * Enums: testshared0_cl48TxEEEStates_c 14952 */ 14953 #define testshared0_cl48TxEEEStates_c_TX_REFRESH 3 14954 #define testshared0_cl48TxEEEStates_c_TX_QUIET 2 14955 #define testshared0_cl48TxEEEStates_c_TX_SLEEP 1 14956 #define testshared0_cl48TxEEEStates_c_TX_ACTIVE 0 14957 14958 /**************************************************************************** 14959 * Enums: testshared0_cl48RxEEEStates_l 14960 */ 14961 #define testshared0_cl48RxEEEStates_l_RX_LINK_FAIL 32 14962 #define testshared0_cl48RxEEEStates_l_RX_WAKE 16 14963 #define testshared0_cl48RxEEEStates_l_RX_QUIET 8 14964 #define testshared0_cl48RxEEEStates_l_RX_DEACT 4 14965 #define testshared0_cl48RxEEEStates_l_RX_SLEEP 2 14966 #define testshared0_cl48RxEEEStates_l_RX_ACTIVE 1 14967 14968 /**************************************************************************** 14969 * Enums: testshared0_cl48RxEEEStates_c 14970 */ 14971 #define testshared0_cl48RxEEEStates_c_RX_LINK_FAIL 5 14972 #define testshared0_cl48RxEEEStates_c_RX_WAKE 4 14973 #define testshared0_cl48RxEEEStates_c_RX_QUIET 3 14974 #define testshared0_cl48RxEEEStates_c_RX_DEACT 2 14975 #define testshared0_cl48RxEEEStates_c_RX_SLEEP 1 14976 #define testshared0_cl48RxEEEStates_c_RX_ACTIVE 0 14977 14978 /**************************************************************************** 14979 * Enums: testshared0_IQP_Options 14980 */ 14981 #define testshared0_IQP_Options_i50uA 0 14982 #define testshared0_IQP_Options_i100uA 1 14983 #define testshared0_IQP_Options_i150uA 2 14984 #define testshared0_IQP_Options_i200uA 3 14985 #define testshared0_IQP_Options_i250uA 4 14986 #define testshared0_IQP_Options_i300uA 5 14987 #define testshared0_IQP_Options_i350uA 6 14988 #define testshared0_IQP_Options_i400uA 7 14989 #define testshared0_IQP_Options_i450uA 8 14990 #define testshared0_IQP_Options_i500uA 9 14991 #define testshared0_IQP_Options_i550uA 10 14992 #define testshared0_IQP_Options_i600uA 11 14993 #define testshared0_IQP_Options_i650uA 12 14994 #define testshared0_IQP_Options_i700uA 13 14995 #define testshared0_IQP_Options_i750uA 14 14996 #define testshared0_IQP_Options_i800uA 15 14997 14998 /**************************************************************************** 14999 * Enums: testshared0_IDriver_Options 15000 */ 15001 #define testshared0_IDriver_Options_v680mV 0 15002 #define testshared0_IDriver_Options_v730mV 1 15003 #define testshared0_IDriver_Options_v780mV 2 15004 #define testshared0_IDriver_Options_v830mV 3 15005 #define testshared0_IDriver_Options_v880mV 4 15006 #define testshared0_IDriver_Options_v930mV 5 15007 #define testshared0_IDriver_Options_v980mV 6 15008 #define testshared0_IDriver_Options_v1010mV 7 15009 #define testshared0_IDriver_Options_v1040mV 8 15010 #define testshared0_IDriver_Options_v1060mV 9 15011 #define testshared0_IDriver_Options_v1070mV 10 15012 #define testshared0_IDriver_Options_v1080mV 11 15013 #define testshared0_IDriver_Options_v1085mV 12 15014 #define testshared0_IDriver_Options_v1090mV 13 15015 #define testshared0_IDriver_Options_v1095mV 14 15016 #define testshared0_IDriver_Options_v1100mV 15 15017 15018 /**************************************************************************** 15019 * Enums: testshared0_operationModes 15020 */ 15021 #define testshared0_operationModes_XGXS 0 15022 #define testshared0_operationModes_XGXG_nCC 1 15023 #define testshared0_operationModes_Indlane_OS8 4 15024 #define testshared0_operationModes_IndLane_OS5 5 15025 #define testshared0_operationModes_PCI 7 15026 #define testshared0_operationModes_XGXS_nLQ 8 15027 #define testshared0_operationModes_XGXS_nLQnCC 9 15028 #define testshared0_operationModes_PBypass 10 15029 #define testshared0_operationModes_PBypass_nDSK 11 15030 #define testshared0_operationModes_ComboCoreMode 12 15031 #define testshared0_operationModes_Clocks_off 15 15032 15033 /**************************************************************************** 15034 * Enums: testshared0_actualSpeeds 15035 */ 15036 #define testshared0_actualSpeeds_dr_10M 0 15037 #define testshared0_actualSpeeds_dr_100M 1 15038 #define testshared0_actualSpeeds_dr_1G 2 15039 #define testshared0_actualSpeeds_dr_2p5G 3 15040 #define testshared0_actualSpeeds_dr_5G_X4 4 15041 #define testshared0_actualSpeeds_dr_6G_X4 5 15042 #define testshared0_actualSpeeds_dr_10G_HiG 6 15043 #define testshared0_actualSpeeds_dr_10G_CX4 7 15044 #define testshared0_actualSpeeds_dr_12G_HiG 8 15045 #define testshared0_actualSpeeds_dr_12p5G_X4 9 15046 #define testshared0_actualSpeeds_dr_13G_X4 10 15047 #define testshared0_actualSpeeds_dr_15G_X4 11 15048 #define testshared0_actualSpeeds_dr_16G_X4 12 15049 #define testshared0_actualSpeeds_dr_1G_KX 13 15050 #define testshared0_actualSpeeds_dr_10G_KX4 14 15051 #define testshared0_actualSpeeds_dr_10G_KR 15 15052 #define testshared0_actualSpeeds_dr_5G 16 15053 #define testshared0_actualSpeeds_dr_6p4G 17 15054 #define testshared0_actualSpeeds_dr_20G_X4 18 15055 #define testshared0_actualSpeeds_dr_21G_X4 19 15056 #define testshared0_actualSpeeds_dr_25G_X4 20 15057 #define testshared0_actualSpeeds_dr_10G_HiG_DXGXS 21 15058 #define testshared0_actualSpeeds_dr_10G_DXGXS 22 15059 #define testshared0_actualSpeeds_dr_10p5G_HiG_DXGXS 23 15060 #define testshared0_actualSpeeds_dr_10p5G_DXGXS 24 15061 #define testshared0_actualSpeeds_dr_12p773G_HiG_DXGXS 25 15062 #define testshared0_actualSpeeds_dr_12p773G_DXGXS 26 15063 #define testshared0_actualSpeeds_dr_10G_XFI 27 15064 #define testshared0_actualSpeeds_dr_40G 28 15065 #define testshared0_actualSpeeds_dr_20G_HiG_DXGXS 29 15066 #define testshared0_actualSpeeds_dr_20G_DXGXS 30 15067 #define testshared0_actualSpeeds_dr_10G_SFI 31 15068 #define testshared0_actualSpeeds_dr_31p5G 32 15069 #define testshared0_actualSpeeds_dr_32p7G 33 15070 #define testshared0_actualSpeeds_dr_20G_SCR 34 15071 #define testshared0_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 15072 #define testshared0_actualSpeeds_dr_10G_DXGXS_SCR 36 15073 #define testshared0_actualSpeeds_dr_12G_R2 37 15074 #define testshared0_actualSpeeds_dr_10G_X2 38 15075 #define testshared0_actualSpeeds_dr_40G_KR4 39 15076 #define testshared0_actualSpeeds_dr_40G_CR4 40 15077 #define testshared0_actualSpeeds_dr_100G_CR10 41 15078 #define testshared0_actualSpeeds_dr_15p75G_DXGXS 44 15079 #define testshared0_actualSpeeds_dr_20G_KR2 57 15080 #define testshared0_actualSpeeds_dr_20G_CR2 58 15081 15082 /**************************************************************************** 15083 * Enums: testshared0_actualSpeedsMisc1 15084 */ 15085 #define testshared0_actualSpeedsMisc1_dr_2500BRCM_X1 16 15086 #define testshared0_actualSpeedsMisc1_dr_5000BRCM_X4 17 15087 #define testshared0_actualSpeedsMisc1_dr_6000BRCM_X4 18 15088 #define testshared0_actualSpeedsMisc1_dr_10GHiGig_X4 19 15089 #define testshared0_actualSpeedsMisc1_dr_10GBASE_CX4 20 15090 #define testshared0_actualSpeedsMisc1_dr_12GHiGig_X4 21 15091 #define testshared0_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 15092 #define testshared0_actualSpeedsMisc1_dr_13GHiGig_X4 23 15093 #define testshared0_actualSpeedsMisc1_dr_15GHiGig_X4 24 15094 #define testshared0_actualSpeedsMisc1_dr_16GHiGig_X4 25 15095 #define testshared0_actualSpeedsMisc1_dr_5000BRCM_X1 26 15096 #define testshared0_actualSpeedsMisc1_dr_6363BRCM_X1 27 15097 #define testshared0_actualSpeedsMisc1_dr_20GHiGig_X4 28 15098 #define testshared0_actualSpeedsMisc1_dr_21GHiGig_X4 29 15099 #define testshared0_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 15100 #define testshared0_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 15101 15102 /**************************************************************************** 15103 * Enums: testshared0_IndLaneModes 15104 */ 15105 #define testshared0_IndLaneModes_SWSDR_div2 0 15106 #define testshared0_IndLaneModes_SWSDR_div1 1 15107 #define testshared0_IndLaneModes_DWSDR_div2 2 15108 #define testshared0_IndLaneModes_DWSDR_div1 3 15109 15110 /**************************************************************************** 15111 * Enums: testshared0_prbsSelect 15112 */ 15113 #define testshared0_prbsSelect_prbs7 0 15114 #define testshared0_prbsSelect_prbs15 1 15115 #define testshared0_prbsSelect_prbs23 2 15116 #define testshared0_prbsSelect_prbs31 3 15117 15118 /**************************************************************************** 15119 * Enums: testshared0_vcoDivider 15120 */ 15121 #define testshared0_vcoDivider_div32 0 15122 #define testshared0_vcoDivider_div36 1 15123 #define testshared0_vcoDivider_div40 2 15124 #define testshared0_vcoDivider_div42 3 15125 #define testshared0_vcoDivider_div48 4 15126 #define testshared0_vcoDivider_div50 5 15127 #define testshared0_vcoDivider_div52 6 15128 #define testshared0_vcoDivider_div54 7 15129 #define testshared0_vcoDivider_div60 8 15130 #define testshared0_vcoDivider_div64 9 15131 #define testshared0_vcoDivider_div66 10 15132 #define testshared0_vcoDivider_div68 11 15133 #define testshared0_vcoDivider_div70 12 15134 #define testshared0_vcoDivider_div80 13 15135 #define testshared0_vcoDivider_div92 14 15136 #define testshared0_vcoDivider_div100 15 15137 15138 /**************************************************************************** 15139 * Enums: testshared0_refClkSelect 15140 */ 15141 #define testshared0_refClkSelect_clk_156p25MHz 1 15142 #define testshared0_refClkSelect_clk_312p5Mhz 2 15143 15144 /**************************************************************************** 15145 * Enums: testshared0_aerMMDdevTypeSelect 15146 */ 15147 #define testshared0_aerMMDdevTypeSelect_combo_core 0 15148 #define testshared0_aerMMDdevTypeSelect_PMA_PMD 1 15149 #define testshared0_aerMMDdevTypeSelect_PCS 3 15150 #define testshared0_aerMMDdevTypeSelect_PHY 4 15151 #define testshared0_aerMMDdevTypeSelect_DTE 5 15152 #define testshared0_aerMMDdevTypeSelect_CL73_AN 7 15153 15154 /**************************************************************************** 15155 * Enums: testshared0_aerMMDportSelect 15156 */ 15157 #define testshared0_aerMMDportSelect_ln0 0 15158 #define testshared0_aerMMDportSelect_ln1 1 15159 #define testshared0_aerMMDportSelect_ln2 2 15160 #define testshared0_aerMMDportSelect_ln3 3 15161 #define testshared0_aerMMDportSelect_BCST_ln0_1_2_3 511 15162 #define testshared0_aerMMDportSelect_BCST_ln0_1 512 15163 #define testshared0_aerMMDportSelect_BCST_ln2_3 513 15164 15165 /**************************************************************************** 15166 * Enums: testshared0_firmwareModeSelect 15167 */ 15168 #define testshared0_firmwareModeSelect_DEFAULT 0 15169 #define testshared0_firmwareModeSelect_SFP_OPT_LR 1 15170 #define testshared0_firmwareModeSelect_SFP_DAC 2 15171 #define testshared0_firmwareModeSelect_XLAUI 3 15172 #define testshared0_firmwareModeSelect_LONG_CH_6G 4 15173 15174 /**************************************************************************** 15175 * Enums: testshared0_tempIdxSelect 15176 */ 15177 #define testshared0_tempIdxSelect_LTE__22p9C 15 15178 #define testshared0_tempIdxSelect_LTE__12p6C 14 15179 #define testshared0_tempIdxSelect_LTE__3p0C 13 15180 #define testshared0_tempIdxSelect_LTE_6p7C 12 15181 #define testshared0_tempIdxSelect_LTE_16p4C 11 15182 #define testshared0_tempIdxSelect_LTE_26p6C 10 15183 #define testshared0_tempIdxSelect_LTE_36p3C 9 15184 #define testshared0_tempIdxSelect_LTE_46p0C 8 15185 #define testshared0_tempIdxSelect_LTE_56p2C 7 15186 #define testshared0_tempIdxSelect_LTE_65p9C 6 15187 #define testshared0_tempIdxSelect_LTE_75p6C 5 15188 #define testshared0_tempIdxSelect_LTE_85p3C 4 15189 #define testshared0_tempIdxSelect_LTE_95p5C 3 15190 #define testshared0_tempIdxSelect_LTE_105p2C 2 15191 #define testshared0_tempIdxSelect_LTE_114p9C 1 15192 #define testshared0_tempIdxSelect_LTE_125p1C 0 15193 15194 /**************************************************************************** 15195 * Enums: testshared0_port_mode 15196 */ 15197 #define testshared0_port_mode_QUAD_PORT 0 15198 #define testshared0_port_mode_TRI_1_PORT 1 15199 #define testshared0_port_mode_TRI_2_PORT 2 15200 #define testshared0_port_mode_DUAL_PORT 3 15201 #define testshared0_port_mode_SINGLE_PORT 4 15202 #define testshared0_port_mode_SINGLE_OCTAL_PORT 5 15203 15204 /**************************************************************************** 15205 * Enums: testshared0_rev_letter_enum 15206 */ 15207 #define testshared0_rev_letter_enum_REV_A 0 15208 #define testshared0_rev_letter_enum_REV_B 1 15209 #define testshared0_rev_letter_enum_REV_C 2 15210 #define testshared0_rev_letter_enum_REV_D 3 15211 15212 /**************************************************************************** 15213 * Enums: testshared0_rev_number_enum 15214 */ 15215 #define testshared0_rev_number_enum_REV_0 0 15216 #define testshared0_rev_number_enum_REV_1 1 15217 #define testshared0_rev_number_enum_REV_2 2 15218 #define testshared0_rev_number_enum_REV_3 3 15219 #define testshared0_rev_number_enum_REV_4 4 15220 #define testshared0_rev_number_enum_REV_5 5 15221 #define testshared0_rev_number_enum_REV_6 6 15222 #define testshared0_rev_number_enum_REV_7 7 15223 15224 /**************************************************************************** 15225 * Enums: testshared0_bonding_enum 15226 */ 15227 #define testshared0_bonding_enum_WIRE_BOND 0 15228 #define testshared0_bonding_enum_FLIP_CHIP 1 15229 15230 /**************************************************************************** 15231 * Enums: testshared0_tech_process 15232 */ 15233 #define testshared0_tech_process_PROCESS_90NM 0 15234 #define testshared0_tech_process_PROCESS_65NM 1 15235 #define testshared0_tech_process_PROCESS_40NM 2 15236 #define testshared0_tech_process_PROCESS_28NM 3 15237 #define testshared0_tech_process_PROCESS_16NM 4 15238 15239 /**************************************************************************** 15240 * Enums: testshared0_model_num 15241 */ 15242 #define testshared0_model_num_SERDES_CL73 0 15243 #define testshared0_model_num_XGXS_16G 1 15244 #define testshared0_model_num_HYPERCORE 2 15245 #define testshared0_model_num_HYPERLITE 3 15246 #define testshared0_model_num_PCIE_G2_PIPE 4 15247 #define testshared0_model_num_SERDES_1p25GBd 5 15248 #define testshared0_model_num_SATA2 6 15249 #define testshared0_model_num_QSGMII 7 15250 #define testshared0_model_num_XGXS10G 8 15251 #define testshared0_model_num_WARPCORE 9 15252 #define testshared0_model_num_XFICORE 10 15253 #define testshared0_model_num_RXFI 11 15254 #define testshared0_model_num_WARPLITE 12 15255 #define testshared0_model_num_PENTACORE 13 15256 #define testshared0_model_num_ESM 14 15257 #define testshared0_model_num_QUAD_SGMII 15 15258 #define testshared0_model_num_WARPCORE_3 16 15259 #define testshared0_model_num_TSC 17 15260 #define testshared0_model_num_TSC4E 18 15261 #define testshared0_model_num_TSC12E 19 15262 #define testshared0_model_num_TSC4F 20 15263 #define testshared0_model_num_TSC4F_GEN2 21 15264 #define testshared0_model_num_XGXS_CL73_90NM 29 15265 #define testshared0_model_num_SERDES_CL73_90NM 30 15266 #define testshared0_model_num_WARPCORE3 32 15267 #define testshared0_model_num_WARPCORE4_TSC 33 15268 #define testshared0_model_num_RXAUI 34 15269 #define testshared0_model_num_TSCE_GEN3 35 15270 #define testshared0_model_num_TSC4F_GEN3 36 15271 #define testshared0_model_num_TSCBH 37 15272 15273 /**************************************************************************** 15274 * Enums: testshared0_payload 15275 */ 15276 #define testshared0_payload_REPEAT_2_BYTES 0 15277 #define testshared0_payload_RAMPING 1 15278 #define testshared0_payload_CL48_CRPAT 2 15279 #define testshared0_payload_CL48_CJPAT 3 15280 #define testshared0_payload_CL36_LONG_CRPAT 4 15281 #define testshared0_payload_CL36_SHORT_CRPAT 5 15282 15283 /**************************************************************************** 15284 * Enums: testshared0_sc 15285 */ 15286 #define testshared0_sc_SPEED_10G_IEEE_KR1 0 15287 #define testshared0_sc_SPEED_25G_IEEE_KS1_CS1 1 15288 #define testshared0_sc_SPEED_25G_IEEE_KR1_CR1 2 15289 #define testshared0_sc_SPEED_40G_IEEE_KR4 3 15290 #define testshared0_sc_SPEED_40G_IEEE_CR4 4 15291 #define testshared0_sc_SPEED_50G_IEEE_KR1_CR1 5 15292 #define testshared0_sc_SPEED_100G_IEEE_KR4 6 15293 #define testshared0_sc_SPEED_100G_IEEE_CR4 7 15294 #define testshared0_sc_SPEED_100G_IEEE_KR2_CR2 8 15295 #define testshared0_sc_SPEED_200G_IEEE_KR4_CR4 9 15296 #define testshared0_sc_SPEED_400G_IEEE_X8 10 15297 #define testshared0_sc_SPEED_CL73_IEEE_20GVCO 11 15298 #define testshared0_sc_SPEED_CL73_IEEE_25GVCO 12 15299 #define testshared0_sc_SPEED_CL73_IEEE_26GVCO 13 15300 #define testshared0_sc_SPEED_20G_BRCM_CR1 14 15301 #define testshared0_sc_SPEED_20G_BRCM_KR1 15 15302 #define testshared0_sc_SPEED_25G_BRCM_CR1 16 15303 #define testshared0_sc_SPEED_25G_BRCM_KR1 17 15304 #define testshared0_sc_SPEED_40G_BRCM_CR2 18 15305 #define testshared0_sc_SPEED_40G_BRCM_KR2 19 15306 #define testshared0_sc_SPEED_50G_BRCM_CR2 20 15307 #define testshared0_sc_SPEED_50G_BRCM_KR2 21 15308 #define testshared0_sc_SPEED_50G_BRCM_CR4 22 15309 #define testshared0_sc_SPEED_50G_BRCM_KR4 23 15310 #define testshared0_sc_SPEED_50G_BRCM_FEC_544_CR2_KR2 24 15311 #define testshared0_sc_SPEED_RESERVED_19 25 15312 #define testshared0_sc_SPEED_50G_BRCM_FEC_544_CR1_KR1 26 15313 #define testshared0_sc_SPEED_50G_BRCM_NO_FEC_CR1_KR1 27 15314 #define testshared0_sc_SPEED_50G_BRCM_FEC_528_CR1_KR1 28 15315 #define testshared0_sc_SPEED_400G_BRCM_NO_FEC_KR8_CR8 29 15316 #define testshared0_sc_SPEED_400G_BRCM_FEC_KR8_CR8 30 15317 #define testshared0_sc_SPEED_200G_BRCM_NO_FEC_KR4_CR4 31 15318 #define testshared0_sc_SPEED_200G_BRCM_KR4_CR4 32 15319 #define testshared0_sc_SPEED_100G_BRCM_KR4_CR4 33 15320 #define testshared0_sc_SPEED_RESERVED_22 34 15321 #define testshared0_sc_SPEED_100G_BRCM_FEC_528_KR2_CR2 35 15322 #define testshared0_sc_SPEED_100G_BRCM_NO_FEC_KR2_CR2 36 15323 #define testshared0_sc_SPEED_100G_BRCM_NO_FEC_X4 37 15324 15325 /**************************************************************************** 15326 * Enums: testshared0_t_fifo_modes 15327 */ 15328 #define testshared0_t_fifo_modes_T_FIFO_INSERT_NO_AM 0 15329 #define testshared0_t_fifo_modes_T_FIFO_INSERT_4_AM 1 15330 #define testshared0_t_fifo_modes_T_FIFO_INSERT_20_AM 2 15331 #define testshared0_t_fifo_modes_T_FIFO_INSERT_2_AM 3 15332 15333 /**************************************************************************** 15334 * Enums: testshared0_t_enc_modes 15335 */ 15336 #define testshared0_t_enc_modes_T_ENC_MODE_BYPASS 0 15337 #define testshared0_t_enc_modes_T_ENC_MODE_CL49 1 15338 #define testshared0_t_enc_modes_T_ENC_MODE_CL82 2 15339 15340 /**************************************************************************** 15341 * Enums: testshared0_btmx_mode 15342 */ 15343 #define testshared0_btmx_mode_BS_BTMX_MODE_1to1 0 15344 #define testshared0_btmx_mode_BS_BTMX_MODE_2to1 1 15345 #define testshared0_btmx_mode_BS_BTMX_MODE_5to1 2 15346 15347 /**************************************************************************** 15348 * Enums: testshared0_t_type_cl82 15349 */ 15350 #define testshared0_t_type_cl82_T_TYPE_B1 5 15351 #define testshared0_t_type_cl82_T_TYPE_C 4 15352 #define testshared0_t_type_cl82_T_TYPE_S 3 15353 #define testshared0_t_type_cl82_T_TYPE_T 2 15354 #define testshared0_t_type_cl82_T_TYPE_D 1 15355 #define testshared0_t_type_cl82_T_TYPE_E 0 15356 15357 /**************************************************************************** 15358 * Enums: testshared0_txsm_state_cl82 15359 */ 15360 #define testshared0_txsm_state_cl82_TX_E 4 15361 #define testshared0_txsm_state_cl82_TX_T 3 15362 #define testshared0_txsm_state_cl82_TX_D 2 15363 #define testshared0_txsm_state_cl82_TX_C 1 15364 #define testshared0_txsm_state_cl82_TX_INIT 0 15365 15366 /**************************************************************************** 15367 * Enums: testshared0_ltxsm_state_cl82 15368 */ 15369 #define testshared0_ltxsm_state_cl82_TX_E 16 15370 #define testshared0_ltxsm_state_cl82_TX_T 8 15371 #define testshared0_ltxsm_state_cl82_TX_D 4 15372 #define testshared0_ltxsm_state_cl82_TX_C 2 15373 #define testshared0_ltxsm_state_cl82_TX_INIT 1 15374 15375 /**************************************************************************** 15376 * Enums: testshared0_r_type_coded_cl82 15377 */ 15378 #define testshared0_r_type_coded_cl82_R_TYPE_B1 32 15379 #define testshared0_r_type_coded_cl82_R_TYPE_C 16 15380 #define testshared0_r_type_coded_cl82_R_TYPE_S 8 15381 #define testshared0_r_type_coded_cl82_R_TYPE_T 4 15382 #define testshared0_r_type_coded_cl82_R_TYPE_D 2 15383 #define testshared0_r_type_coded_cl82_R_TYPE_E 1 15384 15385 /**************************************************************************** 15386 * Enums: testshared0_rxsm_state_cl82 15387 */ 15388 #define testshared0_rxsm_state_cl82_RX_E 16 15389 #define testshared0_rxsm_state_cl82_RX_T 8 15390 #define testshared0_rxsm_state_cl82_RX_D 4 15391 #define testshared0_rxsm_state_cl82_RX_C 2 15392 #define testshared0_rxsm_state_cl82_RX_INIT 1 15393 15394 /**************************************************************************** 15395 * Enums: testshared0_deskew_state 15396 */ 15397 #define testshared0_deskew_state_ALIGN_ACQUIRED 2 15398 #define testshared0_deskew_state_LOSS_OF_ALIGNMENT 1 15399 15400 /**************************************************************************** 15401 * Enums: testshared0_os_mode_enum 15402 */ 15403 #define testshared0_os_mode_enum_OS_MODE_1 0 15404 #define testshared0_os_mode_enum_OS_MODE_2 1 15405 #define testshared0_os_mode_enum_OS_MODE_4 2 15406 #define testshared0_os_mode_enum_OS_MODE_16p5 8 15407 #define testshared0_os_mode_enum_OS_MODE_20p625 12 15408 15409 /**************************************************************************** 15410 * Enums: testshared0_scr_modes 15411 */ 15412 #define testshared0_scr_modes_T_SCR_MODE_BYPASS 0 15413 #define testshared0_scr_modes_T_SCR_MODE_CL49 1 15414 #define testshared0_scr_modes_T_SCR_MODE_40G_2_LANE 2 15415 #define testshared0_scr_modes_T_SCR_MODE_100G 3 15416 #define testshared0_scr_modes_T_SCR_MODE_20G 4 15417 #define testshared0_scr_modes_T_SCR_MODE_40G_4_LANE 5 15418 15419 /**************************************************************************** 15420 * Enums: testshared0_descr_modes 15421 */ 15422 #define testshared0_descr_modes_R_DESCR_MODE_BYPASS 0 15423 #define testshared0_descr_modes_R_DESCR_MODE_CL49 1 15424 #define testshared0_descr_modes_R_DESCR_MODE_CL82 2 15425 15426 /**************************************************************************** 15427 * Enums: testshared0_r_dec_tl_mode 15428 */ 15429 #define testshared0_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 15430 #define testshared0_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 15431 #define testshared0_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 15432 15433 /**************************************************************************** 15434 * Enums: testshared0_r_dec_fsm_mode 15435 */ 15436 #define testshared0_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 15437 #define testshared0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 15438 #define testshared0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 15439 15440 /**************************************************************************** 15441 * Enums: testshared0_r_deskew_mode 15442 */ 15443 #define testshared0_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 15444 #define testshared0_r_deskew_mode_R_DESKEW_MODE_20G 1 15445 #define testshared0_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 15446 #define testshared0_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 15447 #define testshared0_r_deskew_mode_R_DESKEW_MODE_100G 4 15448 #define testshared0_r_deskew_mode_R_DESKEW_MODE_CL49 5 15449 #define testshared0_r_deskew_mode_R_DESKEW_MODE_CL91_QUAD 6 15450 #define testshared0_r_deskew_mode_R_DESKEW_MODE_CL91_SINGLE_BRCM 7 15451 #define testshared0_r_deskew_mode_R_DESKEW_MODE_CL91_DUAL_BRCM 8 15452 #define testshared0_r_deskew_mode_R_DESKEW_MODE_CL91_FC 9 15453 15454 /**************************************************************************** 15455 * Enums: testshared0_bs_dist_modes 15456 */ 15457 #define testshared0_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 15458 #define testshared0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 15459 #define testshared0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 15460 #define testshared0_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 15461 15462 /**************************************************************************** 15463 * Enums: testshared0_cl49_t_type 15464 */ 15465 #define testshared0_cl49_t_type_BAD_T_TYPE 15 15466 #define testshared0_cl49_t_type_T_TYPE_B0 11 15467 #define testshared0_cl49_t_type_T_TYPE_OB 10 15468 #define testshared0_cl49_t_type_T_TYPE_B1 9 15469 #define testshared0_cl49_t_type_T_TYPE_DB 8 15470 #define testshared0_cl49_t_type_T_TYPE_FC 7 15471 #define testshared0_cl49_t_type_T_TYPE_TB 6 15472 #define testshared0_cl49_t_type_T_TYPE_LI 5 15473 #define testshared0_cl49_t_type_T_TYPE_C 4 15474 #define testshared0_cl49_t_type_T_TYPE_S 3 15475 #define testshared0_cl49_t_type_T_TYPE_T 2 15476 #define testshared0_cl49_t_type_T_TYPE_D 1 15477 #define testshared0_cl49_t_type_T_TYPE_E 0 15478 15479 /**************************************************************************** 15480 * Enums: testshared0_cl49_txsm_states 15481 */ 15482 #define testshared0_cl49_txsm_states_TX_LI 5 15483 #define testshared0_cl49_txsm_states_TX_E 4 15484 #define testshared0_cl49_txsm_states_TX_T 3 15485 #define testshared0_cl49_txsm_states_TX_D 2 15486 #define testshared0_cl49_txsm_states_TX_C 1 15487 #define testshared0_cl49_txsm_states_TX_INIT 0 15488 15489 /**************************************************************************** 15490 * Enums: testshared0_cl49_ltxsm_states 15491 */ 15492 #define testshared0_cl49_ltxsm_states_TX_LI 32 15493 #define testshared0_cl49_ltxsm_states_TX_E 16 15494 #define testshared0_cl49_ltxsm_states_TX_T 8 15495 #define testshared0_cl49_ltxsm_states_TX_D 4 15496 #define testshared0_cl49_ltxsm_states_TX_C 2 15497 #define testshared0_cl49_ltxsm_states_TX_INIT 1 15498 15499 /**************************************************************************** 15500 * Enums: testshared0_burst_error_mode 15501 */ 15502 #define testshared0_burst_error_mode_BURST_ERROR_11_BITS 0 15503 #define testshared0_burst_error_mode_BURST_ERROR_16_BITS 1 15504 #define testshared0_burst_error_mode_BURST_ERROR_17_BITS 2 15505 #define testshared0_burst_error_mode_BURST_ERROR_18_BITS 3 15506 #define testshared0_burst_error_mode_BURST_ERROR_19_BITS 4 15507 #define testshared0_burst_error_mode_BURST_ERROR_20_BITS 5 15508 #define testshared0_burst_error_mode_BURST_ERROR_21_BITS 6 15509 #define testshared0_burst_error_mode_BURST_ERROR_22_BITS 7 15510 #define testshared0_burst_error_mode_BURST_ERROR_23_BITS 8 15511 #define testshared0_burst_error_mode_BURST_ERROR_24_BITS 9 15512 #define testshared0_burst_error_mode_BURST_ERROR_25_BITS 10 15513 #define testshared0_burst_error_mode_BURST_ERROR_26_BITS 11 15514 #define testshared0_burst_error_mode_BURST_ERROR_27_BITS 12 15515 #define testshared0_burst_error_mode_BURST_ERROR_28_BITS 13 15516 #define testshared0_burst_error_mode_BURST_ERROR_29_BITS 14 15517 #define testshared0_burst_error_mode_BURST_ERROR_30_BITS 15 15518 #define testshared0_burst_error_mode_BURST_ERROR_31_BITS 16 15519 #define testshared0_burst_error_mode_BURST_ERROR_32_BITS 17 15520 #define testshared0_burst_error_mode_BURST_ERROR_33_BITS 18 15521 #define testshared0_burst_error_mode_BURST_ERROR_34_BITS 19 15522 #define testshared0_burst_error_mode_BURST_ERROR_35_BITS 20 15523 #define testshared0_burst_error_mode_BURST_ERROR_36_BITS 21 15524 #define testshared0_burst_error_mode_BURST_ERROR_37_BITS 22 15525 #define testshared0_burst_error_mode_BURST_ERROR_38_BITS 23 15526 #define testshared0_burst_error_mode_BURST_ERROR_39_BITS 24 15527 #define testshared0_burst_error_mode_BURST_ERROR_40_BITS 25 15528 #define testshared0_burst_error_mode_BURST_ERROR_41_BITS 26 15529 15530 /**************************************************************************** 15531 * Enums: testshared0_bermon_state 15532 */ 15533 #define testshared0_bermon_state_HI_BER 4 15534 #define testshared0_bermon_state_GOOD_BER 3 15535 #define testshared0_bermon_state_BER_TEST_SH 2 15536 #define testshared0_bermon_state_START_TIMER 1 15537 #define testshared0_bermon_state_BER_MT_INIT 0 15538 15539 /**************************************************************************** 15540 * Enums: testshared0_rxsm_state_cl49 15541 */ 15542 #define testshared0_rxsm_state_cl49_RX_LI 32 15543 #define testshared0_rxsm_state_cl49_RX_E 16 15544 #define testshared0_rxsm_state_cl49_RX_T 8 15545 #define testshared0_rxsm_state_cl49_RX_D 4 15546 #define testshared0_rxsm_state_cl49_RX_C 2 15547 #define testshared0_rxsm_state_cl49_RX_INIT 1 15548 15549 /**************************************************************************** 15550 * Enums: testshared0_r_type 15551 */ 15552 #define testshared0_r_type_BAD_R_TYPE 15 15553 #define testshared0_r_type_R_TYPE_B0 11 15554 #define testshared0_r_type_R_TYPE_OB 10 15555 #define testshared0_r_type_R_TYPE_B1 9 15556 #define testshared0_r_type_R_TYPE_DB 8 15557 #define testshared0_r_type_R_TYPE_FC 7 15558 #define testshared0_r_type_R_TYPE_TB 6 15559 #define testshared0_r_type_R_TYPE_LI 5 15560 #define testshared0_r_type_R_TYPE_C 4 15561 #define testshared0_r_type_R_TYPE_S 3 15562 #define testshared0_r_type_R_TYPE_T 2 15563 #define testshared0_r_type_R_TYPE_D 1 15564 #define testshared0_r_type_R_TYPE_E 0 15565 15566 /**************************************************************************** 15567 * Enums: testshared0_am_lock_state 15568 */ 15569 #define testshared0_am_lock_state_INVALID_AM 512 15570 #define testshared0_am_lock_state_GOOD_AM 256 15571 #define testshared0_am_lock_state_COMP_AM 128 15572 #define testshared0_am_lock_state_TIMER_2 64 15573 #define testshared0_am_lock_state_AM_2_GOOD 32 15574 #define testshared0_am_lock_state_COMP_2ND 16 15575 #define testshared0_am_lock_state_TIMER_1 8 15576 #define testshared0_am_lock_state_FIND_1ST 4 15577 #define testshared0_am_lock_state_AM_RESET_CNT 2 15578 #define testshared0_am_lock_state_AM_LOCK_INIT 1 15579 15580 /**************************************************************************** 15581 * Enums: testshared0_msg_selector 15582 */ 15583 #define testshared0_msg_selector_RESERVED 0 15584 #define testshared0_msg_selector_VALUE_802p3 1 15585 #define testshared0_msg_selector_VALUE_802p9 2 15586 #define testshared0_msg_selector_VALUE_802p5 3 15587 #define testshared0_msg_selector_VALUE_1394 4 15588 15589 /**************************************************************************** 15590 * Enums: testshared0_synce_enum_stage1 15591 */ 15592 #define testshared0_synce_enum_stage1_SYNCE_NO_DIV 0 15593 #define testshared0_synce_enum_stage1_SYNCE_DIV_7 1 15594 #define testshared0_synce_enum_stage1_SYNCE_DIV_11 2 15595 15596 /**************************************************************************** 15597 * Enums: testshared0_synce_enum_stage0 15598 */ 15599 #define testshared0_synce_enum_stage0_SYNCE_NO_DIV 0 15600 #define testshared0_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 15601 #define testshared0_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 15602 15603 /**************************************************************************** 15604 * Enums: testshared0_cl91_sync_state 15605 */ 15606 #define testshared0_cl91_sync_state_FIND_1ST 0 15607 #define testshared0_cl91_sync_state_COUNT_NEXT 1 15608 #define testshared0_cl91_sync_state_COMP_2ND 2 15609 #define testshared0_cl91_sync_state_TWO_GOOD 3 15610 15611 /**************************************************************************** 15612 * Enums: testshared0_RS_FEC_sync_state 15613 */ 15614 #define testshared0_RS_FEC_sync_state_LOCK_INIT 0 15615 #define testshared0_RS_FEC_sync_state_FIND_1ST 1 15616 #define testshared0_RS_FEC_sync_state_COUNT_NEXT 2 15617 #define testshared0_RS_FEC_sync_state_COMP_2ND 3 15618 #define testshared0_RS_FEC_sync_state_TWO_GOOD 4 15619 15620 /**************************************************************************** 15621 * Enums: testshared0_cl91_algn_state 15622 */ 15623 #define testshared0_cl91_algn_state_LOSS_OF_ALIGNMENT 0 15624 #define testshared0_cl91_algn_state_DESKEW 1 15625 #define testshared0_cl91_algn_state_DESKEW_FAIL 2 15626 #define testshared0_cl91_algn_state_ALIGN_ACQUIRED 3 15627 #define testshared0_cl91_algn_state_CW_GOOD 4 15628 #define testshared0_cl91_algn_state_CW_BAD 5 15629 #define testshared0_cl91_algn_state_THREE_BAD 6 15630 15631 /**************************************************************************** 15632 * Enums: testshared0_RS_FEC_algn_state 15633 */ 15634 #define testshared0_RS_FEC_algn_state_LOSS_OF_ALIGNMENT 0 15635 #define testshared0_RS_FEC_algn_state_DESKEW 1 15636 #define testshared0_RS_FEC_algn_state_DESKEW_FAIL 2 15637 #define testshared0_RS_FEC_algn_state_ALIGN_ACQUIRED 3 15638 #define testshared0_RS_FEC_algn_state_CW_GOOD 4 15639 #define testshared0_RS_FEC_algn_state_CW_BAD 5 15640 #define testshared0_RS_FEC_algn_state_THREE_BAD 6 15641 15642 /**************************************************************************** 15643 * Enums: testshared0_fec_sel_override 15644 */ 15645 #define testshared0_fec_sel_override_NO_OVERRIDE 0 15646 #define testshared0_fec_sel_override_NO_FEC 1 15647 #define testshared0_fec_sel_override_FEC_CL74 2 15648 #define testshared0_fec_sel_override_FEC_CL91 3 15649 15650 /**************************************************************************** 15651 * Enums: testshared0_cl91_blksync_mode 15652 */ 15653 #define testshared0_cl91_blksync_mode_R_BLKSYNC_NO_CL91_FEC 0 15654 #define testshared0_cl91_blksync_mode_R_BLKSYNC_CL91_QUAD_LANE_FEC 1 15655 #define testshared0_cl91_blksync_mode_R_BLKSYNC_CL91_DUAL_LANE_FEC 2 15656 #define testshared0_cl91_blksync_mode_R_BLKSYNC_CL91_SINGLE_LANE_FEC 3 15657 #define testshared0_cl91_blksync_mode_R_BLKSYNC_CL91_FC_FEC 4 15658 15659 /**************************************************************************** 15660 * Enums: testshared0_r_merge_mode 15661 */ 15662 #define testshared0_r_merge_mode_R_MERGE_MODE_BYPASS 0 15663 #define testshared0_r_merge_mode_R_MERGE_MODE_CL91_FC 1 15664 #define testshared0_r_merge_mode_R_MERGE_MODE_CL91_SINGLE_LANE 2 15665 #define testshared0_r_merge_mode_R_MERGE_MODE_CL91_DUAL_LANE 3 15666 #define testshared0_r_merge_mode_R_MERGE_MODE_CL91_QUAD_LANE 4 15667 15668 /**************************************************************************** 15669 * Enums: testshared0_r_tc_mode 15670 */ 15671 #define testshared0_r_tc_mode_R_TC_MODE_SINGLE 0 15672 #define testshared0_r_tc_mode_R_TC_MODE_DUAL 1 15673 #define testshared0_r_tc_mode_R_TC_MODE_QUAD 2 15674 15675 /**************************************************************************** 15676 * Enums: testshared0_r_tc_out_mode 15677 */ 15678 #define testshared0_r_tc_out_mode_R_TC_OUT_MODE_SINGLE 0 15679 #define testshared0_r_tc_out_mode_R_TC_OUT_MODE_DUAL 1 15680 #define testshared0_r_tc_out_mode_R_TC_OUT_MODE_QUAD 2 15681 15682 /**************************************************************************** 15683 * Enums: testshared0_cl91_fec_mode 15684 */ 15685 #define testshared0_cl91_fec_mode_NO_CL91_FEC 0 15686 #define testshared0_cl91_fec_mode_CL91_SINGLE_LANE_FC 1 15687 #define testshared0_cl91_fec_mode_CL91_SINGLE_LANE_BRCM_PROP 2 15688 #define testshared0_cl91_fec_mode_CL91_DUAL_LANE_BRCM_PROP 3 15689 #define testshared0_cl91_fec_mode_CL91_QUAD_LANE 4 15690 #define testshared0_cl91_fec_mode_IEEE_25G_CL91_SINGLE_LANE 5 15691 15692 /**************************************************************************** 15693 * Enums: testshared0_RS_FEC_fec_mode 15694 */ 15695 #define testshared0_RS_FEC_fec_mode_NO_RS_FEC_FEC 0 15696 #define testshared0_RS_FEC_fec_mode_N_A 1 15697 #define testshared0_RS_FEC_fec_mode_RS_FEC_SINGLE_LANE_BRCM_PROP 2 15698 #define testshared0_RS_FEC_fec_mode_RS_FEC_DUAL_LANE_BRCM_PROP 3 15699 #define testshared0_RS_FEC_fec_mode_RS_FEC_QUAD_LANE 4 15700 #define testshared0_RS_FEC_fec_mode_IEEE_25G_RS_FEC_SINGLE_LANE 5 15701 15702 /**************************************************************************** 15703 * Enums: testshared0_am_spacing_mul 15704 */ 15705 #define testshared0_am_spacing_mul_AM_SPACING_MUL_2 0 15706 #define testshared0_am_spacing_mul_AM_SPACING_MUL_4 1 15707 #define testshared0_am_spacing_mul_AM_SPACING_MUL_5 2 15708 #define testshared0_am_spacing_mul_AM_SPACING_MUL_20 3 15709 15710 /**************************************************************************** 15711 * Enums: tx_x2_control0_cl36TxEEEStates_l 15712 */ 15713 #define tx_x2_control0_cl36TxEEEStates_l_TX_REFRESH 8 15714 #define tx_x2_control0_cl36TxEEEStates_l_TX_QUIET 4 15715 #define tx_x2_control0_cl36TxEEEStates_l_TX_SLEEP 2 15716 #define tx_x2_control0_cl36TxEEEStates_l_TX_ACTIVE 1 15717 15718 /**************************************************************************** 15719 * Enums: tx_x2_control0_cl36TxEEEStates_c 15720 */ 15721 #define tx_x2_control0_cl36TxEEEStates_c_TX_REFRESH 3 15722 #define tx_x2_control0_cl36TxEEEStates_c_TX_QUIET 2 15723 #define tx_x2_control0_cl36TxEEEStates_c_TX_SLEEP 1 15724 #define tx_x2_control0_cl36TxEEEStates_c_TX_ACTIVE 0 15725 15726 /**************************************************************************** 15727 * Enums: tx_x2_control0_cl49TxEEEStates_l 15728 */ 15729 #define tx_x2_control0_cl49TxEEEStates_l_SCR_RESET_2 64 15730 #define tx_x2_control0_cl49TxEEEStates_l_SCR_RESET_1 32 15731 #define tx_x2_control0_cl49TxEEEStates_l_TX_WAKE 16 15732 #define tx_x2_control0_cl49TxEEEStates_l_TX_REFRESH 8 15733 #define tx_x2_control0_cl49TxEEEStates_l_TX_QUIET 4 15734 #define tx_x2_control0_cl49TxEEEStates_l_TX_SLEEP 2 15735 #define tx_x2_control0_cl49TxEEEStates_l_TX_ACTIVE 1 15736 15737 /**************************************************************************** 15738 * Enums: tx_x2_control0_fec_req_enum 15739 */ 15740 #define tx_x2_control0_fec_req_enum_FEC_not_supported 0 15741 #define tx_x2_control0_fec_req_enum_FEC_supported_but_not_requested 1 15742 #define tx_x2_control0_fec_req_enum_invalid_setting 2 15743 #define tx_x2_control0_fec_req_enum_FEC_supported_and_requested 3 15744 15745 /**************************************************************************** 15746 * Enums: tx_x2_control0_cl73_pause_enum 15747 */ 15748 #define tx_x2_control0_cl73_pause_enum_No_PAUSE_ability 0 15749 #define tx_x2_control0_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 15750 #define tx_x2_control0_cl73_pause_enum_Symmetric_PAUSE_ability 1 15751 #define tx_x2_control0_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 15752 15753 /**************************************************************************** 15754 * Enums: tx_x2_control0_cl49TxEEEStates_c 15755 */ 15756 #define tx_x2_control0_cl49TxEEEStates_c_SCR_RESET_2 6 15757 #define tx_x2_control0_cl49TxEEEStates_c_SCR_RESET_1 5 15758 #define tx_x2_control0_cl49TxEEEStates_c_TX_WAKE 4 15759 #define tx_x2_control0_cl49TxEEEStates_c_TX_REFRESH 3 15760 #define tx_x2_control0_cl49TxEEEStates_c_TX_QUIET 2 15761 #define tx_x2_control0_cl49TxEEEStates_c_TX_SLEEP 1 15762 #define tx_x2_control0_cl49TxEEEStates_c_TX_ACTIVE 0 15763 15764 /**************************************************************************** 15765 * Enums: tx_x2_control0_cl36RxEEEStates_l 15766 */ 15767 #define tx_x2_control0_cl36RxEEEStates_l_RX_LINK_FAIL 32 15768 #define tx_x2_control0_cl36RxEEEStates_l_RX_WTF 16 15769 #define tx_x2_control0_cl36RxEEEStates_l_RX_WAKE 8 15770 #define tx_x2_control0_cl36RxEEEStates_l_RX_QUIET 4 15771 #define tx_x2_control0_cl36RxEEEStates_l_RX_SLEEP 2 15772 #define tx_x2_control0_cl36RxEEEStates_l_RX_ACTIVE 1 15773 15774 /**************************************************************************** 15775 * Enums: tx_x2_control0_cl36RxEEEStates_c 15776 */ 15777 #define tx_x2_control0_cl36RxEEEStates_c_RX_LINK_FAIL 5 15778 #define tx_x2_control0_cl36RxEEEStates_c_RX_WTF 4 15779 #define tx_x2_control0_cl36RxEEEStates_c_RX_WAKE 3 15780 #define tx_x2_control0_cl36RxEEEStates_c_RX_QUIET 2 15781 #define tx_x2_control0_cl36RxEEEStates_c_RX_SLEEP 1 15782 #define tx_x2_control0_cl36RxEEEStates_c_RX_ACTIVE 0 15783 15784 /**************************************************************************** 15785 * Enums: tx_x2_control0_cl49RxEEEStates_l 15786 */ 15787 #define tx_x2_control0_cl49RxEEEStates_l_RX_LINK_FAIL 32 15788 #define tx_x2_control0_cl49RxEEEStates_l_RX_WTF 16 15789 #define tx_x2_control0_cl49RxEEEStates_l_RX_WAKE 8 15790 #define tx_x2_control0_cl49RxEEEStates_l_RX_QUIET 4 15791 #define tx_x2_control0_cl49RxEEEStates_l_RX_SLEEP 2 15792 #define tx_x2_control0_cl49RxEEEStates_l_RX_ACTIVE 1 15793 15794 /**************************************************************************** 15795 * Enums: tx_x2_control0_cl49RxEEEStates_c 15796 */ 15797 #define tx_x2_control0_cl49RxEEEStates_c_RX_LINK_FAIL 5 15798 #define tx_x2_control0_cl49RxEEEStates_c_RX_WTF 4 15799 #define tx_x2_control0_cl49RxEEEStates_c_RX_WAKE 3 15800 #define tx_x2_control0_cl49RxEEEStates_c_RX_QUIET 2 15801 #define tx_x2_control0_cl49RxEEEStates_c_RX_SLEEP 1 15802 #define tx_x2_control0_cl49RxEEEStates_c_RX_ACTIVE 0 15803 15804 /**************************************************************************** 15805 * Enums: tx_x2_control0_cl48TxEEEStates_l 15806 */ 15807 #define tx_x2_control0_cl48TxEEEStates_l_TX_REFRESH 8 15808 #define tx_x2_control0_cl48TxEEEStates_l_TX_QUIET 4 15809 #define tx_x2_control0_cl48TxEEEStates_l_TX_SLEEP 2 15810 #define tx_x2_control0_cl48TxEEEStates_l_TX_ACTIVE 1 15811 15812 /**************************************************************************** 15813 * Enums: tx_x2_control0_cl48TxEEEStates_c 15814 */ 15815 #define tx_x2_control0_cl48TxEEEStates_c_TX_REFRESH 3 15816 #define tx_x2_control0_cl48TxEEEStates_c_TX_QUIET 2 15817 #define tx_x2_control0_cl48TxEEEStates_c_TX_SLEEP 1 15818 #define tx_x2_control0_cl48TxEEEStates_c_TX_ACTIVE 0 15819 15820 /**************************************************************************** 15821 * Enums: tx_x2_control0_cl48RxEEEStates_l 15822 */ 15823 #define tx_x2_control0_cl48RxEEEStates_l_RX_LINK_FAIL 32 15824 #define tx_x2_control0_cl48RxEEEStates_l_RX_WAKE 16 15825 #define tx_x2_control0_cl48RxEEEStates_l_RX_QUIET 8 15826 #define tx_x2_control0_cl48RxEEEStates_l_RX_DEACT 4 15827 #define tx_x2_control0_cl48RxEEEStates_l_RX_SLEEP 2 15828 #define tx_x2_control0_cl48RxEEEStates_l_RX_ACTIVE 1 15829 15830 /**************************************************************************** 15831 * Enums: tx_x2_control0_cl48RxEEEStates_c 15832 */ 15833 #define tx_x2_control0_cl48RxEEEStates_c_RX_LINK_FAIL 5 15834 #define tx_x2_control0_cl48RxEEEStates_c_RX_WAKE 4 15835 #define tx_x2_control0_cl48RxEEEStates_c_RX_QUIET 3 15836 #define tx_x2_control0_cl48RxEEEStates_c_RX_DEACT 2 15837 #define tx_x2_control0_cl48RxEEEStates_c_RX_SLEEP 1 15838 #define tx_x2_control0_cl48RxEEEStates_c_RX_ACTIVE 0 15839 15840 /**************************************************************************** 15841 * Enums: tx_x2_control0_IQP_Options 15842 */ 15843 #define tx_x2_control0_IQP_Options_i50uA 0 15844 #define tx_x2_control0_IQP_Options_i100uA 1 15845 #define tx_x2_control0_IQP_Options_i150uA 2 15846 #define tx_x2_control0_IQP_Options_i200uA 3 15847 #define tx_x2_control0_IQP_Options_i250uA 4 15848 #define tx_x2_control0_IQP_Options_i300uA 5 15849 #define tx_x2_control0_IQP_Options_i350uA 6 15850 #define tx_x2_control0_IQP_Options_i400uA 7 15851 #define tx_x2_control0_IQP_Options_i450uA 8 15852 #define tx_x2_control0_IQP_Options_i500uA 9 15853 #define tx_x2_control0_IQP_Options_i550uA 10 15854 #define tx_x2_control0_IQP_Options_i600uA 11 15855 #define tx_x2_control0_IQP_Options_i650uA 12 15856 #define tx_x2_control0_IQP_Options_i700uA 13 15857 #define tx_x2_control0_IQP_Options_i750uA 14 15858 #define tx_x2_control0_IQP_Options_i800uA 15 15859 15860 /**************************************************************************** 15861 * Enums: tx_x2_control0_IDriver_Options 15862 */ 15863 #define tx_x2_control0_IDriver_Options_v680mV 0 15864 #define tx_x2_control0_IDriver_Options_v730mV 1 15865 #define tx_x2_control0_IDriver_Options_v780mV 2 15866 #define tx_x2_control0_IDriver_Options_v830mV 3 15867 #define tx_x2_control0_IDriver_Options_v880mV 4 15868 #define tx_x2_control0_IDriver_Options_v930mV 5 15869 #define tx_x2_control0_IDriver_Options_v980mV 6 15870 #define tx_x2_control0_IDriver_Options_v1010mV 7 15871 #define tx_x2_control0_IDriver_Options_v1040mV 8 15872 #define tx_x2_control0_IDriver_Options_v1060mV 9 15873 #define tx_x2_control0_IDriver_Options_v1070mV 10 15874 #define tx_x2_control0_IDriver_Options_v1080mV 11 15875 #define tx_x2_control0_IDriver_Options_v1085mV 12 15876 #define tx_x2_control0_IDriver_Options_v1090mV 13 15877 #define tx_x2_control0_IDriver_Options_v1095mV 14 15878 #define tx_x2_control0_IDriver_Options_v1100mV 15 15879 15880 /**************************************************************************** 15881 * Enums: tx_x2_control0_operationModes 15882 */ 15883 #define tx_x2_control0_operationModes_XGXS 0 15884 #define tx_x2_control0_operationModes_XGXG_nCC 1 15885 #define tx_x2_control0_operationModes_Indlane_OS8 4 15886 #define tx_x2_control0_operationModes_IndLane_OS5 5 15887 #define tx_x2_control0_operationModes_PCI 7 15888 #define tx_x2_control0_operationModes_XGXS_nLQ 8 15889 #define tx_x2_control0_operationModes_XGXS_nLQnCC 9 15890 #define tx_x2_control0_operationModes_PBypass 10 15891 #define tx_x2_control0_operationModes_PBypass_nDSK 11 15892 #define tx_x2_control0_operationModes_ComboCoreMode 12 15893 #define tx_x2_control0_operationModes_Clocks_off 15 15894 15895 /**************************************************************************** 15896 * Enums: tx_x2_control0_actualSpeeds 15897 */ 15898 #define tx_x2_control0_actualSpeeds_dr_10M 0 15899 #define tx_x2_control0_actualSpeeds_dr_100M 1 15900 #define tx_x2_control0_actualSpeeds_dr_1G 2 15901 #define tx_x2_control0_actualSpeeds_dr_2p5G 3 15902 #define tx_x2_control0_actualSpeeds_dr_5G_X4 4 15903 #define tx_x2_control0_actualSpeeds_dr_6G_X4 5 15904 #define tx_x2_control0_actualSpeeds_dr_10G_HiG 6 15905 #define tx_x2_control0_actualSpeeds_dr_10G_CX4 7 15906 #define tx_x2_control0_actualSpeeds_dr_12G_HiG 8 15907 #define tx_x2_control0_actualSpeeds_dr_12p5G_X4 9 15908 #define tx_x2_control0_actualSpeeds_dr_13G_X4 10 15909 #define tx_x2_control0_actualSpeeds_dr_15G_X4 11 15910 #define tx_x2_control0_actualSpeeds_dr_16G_X4 12 15911 #define tx_x2_control0_actualSpeeds_dr_1G_KX 13 15912 #define tx_x2_control0_actualSpeeds_dr_10G_KX4 14 15913 #define tx_x2_control0_actualSpeeds_dr_10G_KR 15 15914 #define tx_x2_control0_actualSpeeds_dr_5G 16 15915 #define tx_x2_control0_actualSpeeds_dr_6p4G 17 15916 #define tx_x2_control0_actualSpeeds_dr_20G_X4 18 15917 #define tx_x2_control0_actualSpeeds_dr_21G_X4 19 15918 #define tx_x2_control0_actualSpeeds_dr_25G_X4 20 15919 #define tx_x2_control0_actualSpeeds_dr_10G_HiG_DXGXS 21 15920 #define tx_x2_control0_actualSpeeds_dr_10G_DXGXS 22 15921 #define tx_x2_control0_actualSpeeds_dr_10p5G_HiG_DXGXS 23 15922 #define tx_x2_control0_actualSpeeds_dr_10p5G_DXGXS 24 15923 #define tx_x2_control0_actualSpeeds_dr_12p773G_HiG_DXGXS 25 15924 #define tx_x2_control0_actualSpeeds_dr_12p773G_DXGXS 26 15925 #define tx_x2_control0_actualSpeeds_dr_10G_XFI 27 15926 #define tx_x2_control0_actualSpeeds_dr_40G 28 15927 #define tx_x2_control0_actualSpeeds_dr_20G_HiG_DXGXS 29 15928 #define tx_x2_control0_actualSpeeds_dr_20G_DXGXS 30 15929 #define tx_x2_control0_actualSpeeds_dr_10G_SFI 31 15930 #define tx_x2_control0_actualSpeeds_dr_31p5G 32 15931 #define tx_x2_control0_actualSpeeds_dr_32p7G 33 15932 #define tx_x2_control0_actualSpeeds_dr_20G_SCR 34 15933 #define tx_x2_control0_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 15934 #define tx_x2_control0_actualSpeeds_dr_10G_DXGXS_SCR 36 15935 #define tx_x2_control0_actualSpeeds_dr_12G_R2 37 15936 #define tx_x2_control0_actualSpeeds_dr_10G_X2 38 15937 #define tx_x2_control0_actualSpeeds_dr_40G_KR4 39 15938 #define tx_x2_control0_actualSpeeds_dr_40G_CR4 40 15939 #define tx_x2_control0_actualSpeeds_dr_100G_CR10 41 15940 #define tx_x2_control0_actualSpeeds_dr_15p75G_DXGXS 44 15941 #define tx_x2_control0_actualSpeeds_dr_20G_KR2 57 15942 #define tx_x2_control0_actualSpeeds_dr_20G_CR2 58 15943 15944 /**************************************************************************** 15945 * Enums: tx_x2_control0_actualSpeedsMisc1 15946 */ 15947 #define tx_x2_control0_actualSpeedsMisc1_dr_2500BRCM_X1 16 15948 #define tx_x2_control0_actualSpeedsMisc1_dr_5000BRCM_X4 17 15949 #define tx_x2_control0_actualSpeedsMisc1_dr_6000BRCM_X4 18 15950 #define tx_x2_control0_actualSpeedsMisc1_dr_10GHiGig_X4 19 15951 #define tx_x2_control0_actualSpeedsMisc1_dr_10GBASE_CX4 20 15952 #define tx_x2_control0_actualSpeedsMisc1_dr_12GHiGig_X4 21 15953 #define tx_x2_control0_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 15954 #define tx_x2_control0_actualSpeedsMisc1_dr_13GHiGig_X4 23 15955 #define tx_x2_control0_actualSpeedsMisc1_dr_15GHiGig_X4 24 15956 #define tx_x2_control0_actualSpeedsMisc1_dr_16GHiGig_X4 25 15957 #define tx_x2_control0_actualSpeedsMisc1_dr_5000BRCM_X1 26 15958 #define tx_x2_control0_actualSpeedsMisc1_dr_6363BRCM_X1 27 15959 #define tx_x2_control0_actualSpeedsMisc1_dr_20GHiGig_X4 28 15960 #define tx_x2_control0_actualSpeedsMisc1_dr_21GHiGig_X4 29 15961 #define tx_x2_control0_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 15962 #define tx_x2_control0_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 15963 15964 /**************************************************************************** 15965 * Enums: tx_x2_control0_IndLaneModes 15966 */ 15967 #define tx_x2_control0_IndLaneModes_SWSDR_div2 0 15968 #define tx_x2_control0_IndLaneModes_SWSDR_div1 1 15969 #define tx_x2_control0_IndLaneModes_DWSDR_div2 2 15970 #define tx_x2_control0_IndLaneModes_DWSDR_div1 3 15971 15972 /**************************************************************************** 15973 * Enums: tx_x2_control0_prbsSelect 15974 */ 15975 #define tx_x2_control0_prbsSelect_prbs7 0 15976 #define tx_x2_control0_prbsSelect_prbs15 1 15977 #define tx_x2_control0_prbsSelect_prbs23 2 15978 #define tx_x2_control0_prbsSelect_prbs31 3 15979 15980 /**************************************************************************** 15981 * Enums: tx_x2_control0_vcoDivider 15982 */ 15983 #define tx_x2_control0_vcoDivider_div32 0 15984 #define tx_x2_control0_vcoDivider_div36 1 15985 #define tx_x2_control0_vcoDivider_div40 2 15986 #define tx_x2_control0_vcoDivider_div42 3 15987 #define tx_x2_control0_vcoDivider_div48 4 15988 #define tx_x2_control0_vcoDivider_div50 5 15989 #define tx_x2_control0_vcoDivider_div52 6 15990 #define tx_x2_control0_vcoDivider_div54 7 15991 #define tx_x2_control0_vcoDivider_div60 8 15992 #define tx_x2_control0_vcoDivider_div64 9 15993 #define tx_x2_control0_vcoDivider_div66 10 15994 #define tx_x2_control0_vcoDivider_div68 11 15995 #define tx_x2_control0_vcoDivider_div70 12 15996 #define tx_x2_control0_vcoDivider_div80 13 15997 #define tx_x2_control0_vcoDivider_div92 14 15998 #define tx_x2_control0_vcoDivider_div100 15 15999 16000 /**************************************************************************** 16001 * Enums: tx_x2_control0_refClkSelect 16002 */ 16003 #define tx_x2_control0_refClkSelect_clk_156p25MHz 1 16004 #define tx_x2_control0_refClkSelect_clk_312p5Mhz 2 16005 16006 /**************************************************************************** 16007 * Enums: tx_x2_control0_aerMMDdevTypeSelect 16008 */ 16009 #define tx_x2_control0_aerMMDdevTypeSelect_combo_core 0 16010 #define tx_x2_control0_aerMMDdevTypeSelect_PMA_PMD 1 16011 #define tx_x2_control0_aerMMDdevTypeSelect_PCS 3 16012 #define tx_x2_control0_aerMMDdevTypeSelect_PHY 4 16013 #define tx_x2_control0_aerMMDdevTypeSelect_DTE 5 16014 #define tx_x2_control0_aerMMDdevTypeSelect_CL73_AN 7 16015 16016 /**************************************************************************** 16017 * Enums: tx_x2_control0_aerMMDportSelect 16018 */ 16019 #define tx_x2_control0_aerMMDportSelect_ln0 0 16020 #define tx_x2_control0_aerMMDportSelect_ln1 1 16021 #define tx_x2_control0_aerMMDportSelect_ln2 2 16022 #define tx_x2_control0_aerMMDportSelect_ln3 3 16023 #define tx_x2_control0_aerMMDportSelect_BCST_ln0_1_2_3 511 16024 #define tx_x2_control0_aerMMDportSelect_BCST_ln0_1 512 16025 #define tx_x2_control0_aerMMDportSelect_BCST_ln2_3 513 16026 16027 /**************************************************************************** 16028 * Enums: tx_x2_control0_firmwareModeSelect 16029 */ 16030 #define tx_x2_control0_firmwareModeSelect_DEFAULT 0 16031 #define tx_x2_control0_firmwareModeSelect_SFP_OPT_LR 1 16032 #define tx_x2_control0_firmwareModeSelect_SFP_DAC 2 16033 #define tx_x2_control0_firmwareModeSelect_XLAUI 3 16034 #define tx_x2_control0_firmwareModeSelect_LONG_CH_6G 4 16035 16036 /**************************************************************************** 16037 * Enums: tx_x2_control0_tempIdxSelect 16038 */ 16039 #define tx_x2_control0_tempIdxSelect_LTE__22p9C 15 16040 #define tx_x2_control0_tempIdxSelect_LTE__12p6C 14 16041 #define tx_x2_control0_tempIdxSelect_LTE__3p0C 13 16042 #define tx_x2_control0_tempIdxSelect_LTE_6p7C 12 16043 #define tx_x2_control0_tempIdxSelect_LTE_16p4C 11 16044 #define tx_x2_control0_tempIdxSelect_LTE_26p6C 10 16045 #define tx_x2_control0_tempIdxSelect_LTE_36p3C 9 16046 #define tx_x2_control0_tempIdxSelect_LTE_46p0C 8 16047 #define tx_x2_control0_tempIdxSelect_LTE_56p2C 7 16048 #define tx_x2_control0_tempIdxSelect_LTE_65p9C 6 16049 #define tx_x2_control0_tempIdxSelect_LTE_75p6C 5 16050 #define tx_x2_control0_tempIdxSelect_LTE_85p3C 4 16051 #define tx_x2_control0_tempIdxSelect_LTE_95p5C 3 16052 #define tx_x2_control0_tempIdxSelect_LTE_105p2C 2 16053 #define tx_x2_control0_tempIdxSelect_LTE_114p9C 1 16054 #define tx_x2_control0_tempIdxSelect_LTE_125p1C 0 16055 16056 /**************************************************************************** 16057 * Enums: tx_x2_control0_port_mode 16058 */ 16059 #define tx_x2_control0_port_mode_QUAD_PORT 0 16060 #define tx_x2_control0_port_mode_TRI_1_PORT 1 16061 #define tx_x2_control0_port_mode_TRI_2_PORT 2 16062 #define tx_x2_control0_port_mode_DUAL_PORT 3 16063 #define tx_x2_control0_port_mode_SINGLE_PORT 4 16064 #define tx_x2_control0_port_mode_SINGLE_OCTAL_PORT 5 16065 16066 /**************************************************************************** 16067 * Enums: tx_x2_control0_rev_letter_enum 16068 */ 16069 #define tx_x2_control0_rev_letter_enum_REV_A 0 16070 #define tx_x2_control0_rev_letter_enum_REV_B 1 16071 #define tx_x2_control0_rev_letter_enum_REV_C 2 16072 #define tx_x2_control0_rev_letter_enum_REV_D 3 16073 16074 /**************************************************************************** 16075 * Enums: tx_x2_control0_rev_number_enum 16076 */ 16077 #define tx_x2_control0_rev_number_enum_REV_0 0 16078 #define tx_x2_control0_rev_number_enum_REV_1 1 16079 #define tx_x2_control0_rev_number_enum_REV_2 2 16080 #define tx_x2_control0_rev_number_enum_REV_3 3 16081 #define tx_x2_control0_rev_number_enum_REV_4 4 16082 #define tx_x2_control0_rev_number_enum_REV_5 5 16083 #define tx_x2_control0_rev_number_enum_REV_6 6 16084 #define tx_x2_control0_rev_number_enum_REV_7 7 16085 16086 /**************************************************************************** 16087 * Enums: tx_x2_control0_bonding_enum 16088 */ 16089 #define tx_x2_control0_bonding_enum_WIRE_BOND 0 16090 #define tx_x2_control0_bonding_enum_FLIP_CHIP 1 16091 16092 /**************************************************************************** 16093 * Enums: tx_x2_control0_tech_process 16094 */ 16095 #define tx_x2_control0_tech_process_PROCESS_90NM 0 16096 #define tx_x2_control0_tech_process_PROCESS_65NM 1 16097 #define tx_x2_control0_tech_process_PROCESS_40NM 2 16098 #define tx_x2_control0_tech_process_PROCESS_28NM 3 16099 #define tx_x2_control0_tech_process_PROCESS_16NM 4 16100 16101 /**************************************************************************** 16102 * Enums: tx_x2_control0_model_num 16103 */ 16104 #define tx_x2_control0_model_num_SERDES_CL73 0 16105 #define tx_x2_control0_model_num_XGXS_16G 1 16106 #define tx_x2_control0_model_num_HYPERCORE 2 16107 #define tx_x2_control0_model_num_HYPERLITE 3 16108 #define tx_x2_control0_model_num_PCIE_G2_PIPE 4 16109 #define tx_x2_control0_model_num_SERDES_1p25GBd 5 16110 #define tx_x2_control0_model_num_SATA2 6 16111 #define tx_x2_control0_model_num_QSGMII 7 16112 #define tx_x2_control0_model_num_XGXS10G 8 16113 #define tx_x2_control0_model_num_WARPCORE 9 16114 #define tx_x2_control0_model_num_XFICORE 10 16115 #define tx_x2_control0_model_num_RXFI 11 16116 #define tx_x2_control0_model_num_WARPLITE 12 16117 #define tx_x2_control0_model_num_PENTACORE 13 16118 #define tx_x2_control0_model_num_ESM 14 16119 #define tx_x2_control0_model_num_QUAD_SGMII 15 16120 #define tx_x2_control0_model_num_WARPCORE_3 16 16121 #define tx_x2_control0_model_num_TSC 17 16122 #define tx_x2_control0_model_num_TSC4E 18 16123 #define tx_x2_control0_model_num_TSC12E 19 16124 #define tx_x2_control0_model_num_TSC4F 20 16125 #define tx_x2_control0_model_num_TSC4F_GEN2 21 16126 #define tx_x2_control0_model_num_XGXS_CL73_90NM 29 16127 #define tx_x2_control0_model_num_SERDES_CL73_90NM 30 16128 #define tx_x2_control0_model_num_WARPCORE3 32 16129 #define tx_x2_control0_model_num_WARPCORE4_TSC 33 16130 #define tx_x2_control0_model_num_RXAUI 34 16131 #define tx_x2_control0_model_num_TSCE_GEN3 35 16132 #define tx_x2_control0_model_num_TSC4F_GEN3 36 16133 #define tx_x2_control0_model_num_TSCBH 37 16134 16135 /**************************************************************************** 16136 * Enums: tx_x2_control0_payload 16137 */ 16138 #define tx_x2_control0_payload_REPEAT_2_BYTES 0 16139 #define tx_x2_control0_payload_RAMPING 1 16140 #define tx_x2_control0_payload_CL48_CRPAT 2 16141 #define tx_x2_control0_payload_CL48_CJPAT 3 16142 #define tx_x2_control0_payload_CL36_LONG_CRPAT 4 16143 #define tx_x2_control0_payload_CL36_SHORT_CRPAT 5 16144 16145 /**************************************************************************** 16146 * Enums: tx_x2_control0_sc 16147 */ 16148 #define tx_x2_control0_sc_SPEED_10G_IEEE_KR1 0 16149 #define tx_x2_control0_sc_SPEED_25G_IEEE_KS1_CS1 1 16150 #define tx_x2_control0_sc_SPEED_25G_IEEE_KR1_CR1 2 16151 #define tx_x2_control0_sc_SPEED_40G_IEEE_KR4 3 16152 #define tx_x2_control0_sc_SPEED_40G_IEEE_CR4 4 16153 #define tx_x2_control0_sc_SPEED_50G_IEEE_KR1_CR1 5 16154 #define tx_x2_control0_sc_SPEED_100G_IEEE_KR4 6 16155 #define tx_x2_control0_sc_SPEED_100G_IEEE_CR4 7 16156 #define tx_x2_control0_sc_SPEED_100G_IEEE_KR2_CR2 8 16157 #define tx_x2_control0_sc_SPEED_200G_IEEE_KR4_CR4 9 16158 #define tx_x2_control0_sc_SPEED_400G_IEEE_X8 10 16159 #define tx_x2_control0_sc_SPEED_CL73_IEEE_20GVCO 11 16160 #define tx_x2_control0_sc_SPEED_CL73_IEEE_25GVCO 12 16161 #define tx_x2_control0_sc_SPEED_CL73_IEEE_26GVCO 13 16162 #define tx_x2_control0_sc_SPEED_20G_BRCM_CR1 14 16163 #define tx_x2_control0_sc_SPEED_20G_BRCM_KR1 15 16164 #define tx_x2_control0_sc_SPEED_25G_BRCM_CR1 16 16165 #define tx_x2_control0_sc_SPEED_25G_BRCM_KR1 17 16166 #define tx_x2_control0_sc_SPEED_40G_BRCM_CR2 18 16167 #define tx_x2_control0_sc_SPEED_40G_BRCM_KR2 19 16168 #define tx_x2_control0_sc_SPEED_50G_BRCM_CR2 20 16169 #define tx_x2_control0_sc_SPEED_50G_BRCM_KR2 21 16170 #define tx_x2_control0_sc_SPEED_50G_BRCM_CR4 22 16171 #define tx_x2_control0_sc_SPEED_50G_BRCM_KR4 23 16172 #define tx_x2_control0_sc_SPEED_50G_BRCM_FEC_544_CR2_KR2 24 16173 #define tx_x2_control0_sc_SPEED_RESERVED_19 25 16174 #define tx_x2_control0_sc_SPEED_50G_BRCM_FEC_544_CR1_KR1 26 16175 #define tx_x2_control0_sc_SPEED_50G_BRCM_NO_FEC_CR1_KR1 27 16176 #define tx_x2_control0_sc_SPEED_50G_BRCM_FEC_528_CR1_KR1 28 16177 #define tx_x2_control0_sc_SPEED_400G_BRCM_NO_FEC_KR8_CR8 29 16178 #define tx_x2_control0_sc_SPEED_400G_BRCM_FEC_KR8_CR8 30 16179 #define tx_x2_control0_sc_SPEED_200G_BRCM_NO_FEC_KR4_CR4 31 16180 #define tx_x2_control0_sc_SPEED_200G_BRCM_KR4_CR4 32 16181 #define tx_x2_control0_sc_SPEED_100G_BRCM_KR4_CR4 33 16182 #define tx_x2_control0_sc_SPEED_RESERVED_22 34 16183 #define tx_x2_control0_sc_SPEED_100G_BRCM_FEC_528_KR2_CR2 35 16184 #define tx_x2_control0_sc_SPEED_100G_BRCM_NO_FEC_KR2_CR2 36 16185 #define tx_x2_control0_sc_SPEED_100G_BRCM_NO_FEC_X4 37 16186 16187 /**************************************************************************** 16188 * Enums: tx_x2_control0_t_fifo_modes 16189 */ 16190 #define tx_x2_control0_t_fifo_modes_T_FIFO_INSERT_NO_AM 0 16191 #define tx_x2_control0_t_fifo_modes_T_FIFO_INSERT_4_AM 1 16192 #define tx_x2_control0_t_fifo_modes_T_FIFO_INSERT_20_AM 2 16193 #define tx_x2_control0_t_fifo_modes_T_FIFO_INSERT_2_AM 3 16194 16195 /**************************************************************************** 16196 * Enums: tx_x2_control0_t_enc_modes 16197 */ 16198 #define tx_x2_control0_t_enc_modes_T_ENC_MODE_BYPASS 0 16199 #define tx_x2_control0_t_enc_modes_T_ENC_MODE_CL49 1 16200 #define tx_x2_control0_t_enc_modes_T_ENC_MODE_CL82 2 16201 16202 /**************************************************************************** 16203 * Enums: tx_x2_control0_btmx_mode 16204 */ 16205 #define tx_x2_control0_btmx_mode_BS_BTMX_MODE_1to1 0 16206 #define tx_x2_control0_btmx_mode_BS_BTMX_MODE_2to1 1 16207 #define tx_x2_control0_btmx_mode_BS_BTMX_MODE_5to1 2 16208 16209 /**************************************************************************** 16210 * Enums: tx_x2_control0_t_type_cl82 16211 */ 16212 #define tx_x2_control0_t_type_cl82_T_TYPE_B1 5 16213 #define tx_x2_control0_t_type_cl82_T_TYPE_C 4 16214 #define tx_x2_control0_t_type_cl82_T_TYPE_S 3 16215 #define tx_x2_control0_t_type_cl82_T_TYPE_T 2 16216 #define tx_x2_control0_t_type_cl82_T_TYPE_D 1 16217 #define tx_x2_control0_t_type_cl82_T_TYPE_E 0 16218 16219 /**************************************************************************** 16220 * Enums: tx_x2_control0_txsm_state_cl82 16221 */ 16222 #define tx_x2_control0_txsm_state_cl82_TX_E 4 16223 #define tx_x2_control0_txsm_state_cl82_TX_T 3 16224 #define tx_x2_control0_txsm_state_cl82_TX_D 2 16225 #define tx_x2_control0_txsm_state_cl82_TX_C 1 16226 #define tx_x2_control0_txsm_state_cl82_TX_INIT 0 16227 16228 /**************************************************************************** 16229 * Enums: tx_x2_control0_ltxsm_state_cl82 16230 */ 16231 #define tx_x2_control0_ltxsm_state_cl82_TX_E 16 16232 #define tx_x2_control0_ltxsm_state_cl82_TX_T 8 16233 #define tx_x2_control0_ltxsm_state_cl82_TX_D 4 16234 #define tx_x2_control0_ltxsm_state_cl82_TX_C 2 16235 #define tx_x2_control0_ltxsm_state_cl82_TX_INIT 1 16236 16237 /**************************************************************************** 16238 * Enums: tx_x2_control0_r_type_coded_cl82 16239 */ 16240 #define tx_x2_control0_r_type_coded_cl82_R_TYPE_B1 32 16241 #define tx_x2_control0_r_type_coded_cl82_R_TYPE_C 16 16242 #define tx_x2_control0_r_type_coded_cl82_R_TYPE_S 8 16243 #define tx_x2_control0_r_type_coded_cl82_R_TYPE_T 4 16244 #define tx_x2_control0_r_type_coded_cl82_R_TYPE_D 2 16245 #define tx_x2_control0_r_type_coded_cl82_R_TYPE_E 1 16246 16247 /**************************************************************************** 16248 * Enums: tx_x2_control0_rxsm_state_cl82 16249 */ 16250 #define tx_x2_control0_rxsm_state_cl82_RX_E 16 16251 #define tx_x2_control0_rxsm_state_cl82_RX_T 8 16252 #define tx_x2_control0_rxsm_state_cl82_RX_D 4 16253 #define tx_x2_control0_rxsm_state_cl82_RX_C 2 16254 #define tx_x2_control0_rxsm_state_cl82_RX_INIT 1 16255 16256 /**************************************************************************** 16257 * Enums: tx_x2_control0_deskew_state 16258 */ 16259 #define tx_x2_control0_deskew_state_ALIGN_ACQUIRED 2 16260 #define tx_x2_control0_deskew_state_LOSS_OF_ALIGNMENT 1 16261 16262 /**************************************************************************** 16263 * Enums: tx_x2_control0_os_mode_enum 16264 */ 16265 #define tx_x2_control0_os_mode_enum_OS_MODE_1 0 16266 #define tx_x2_control0_os_mode_enum_OS_MODE_2 1 16267 #define tx_x2_control0_os_mode_enum_OS_MODE_4 2 16268 #define tx_x2_control0_os_mode_enum_OS_MODE_16p5 8 16269 #define tx_x2_control0_os_mode_enum_OS_MODE_20p625 12 16270 16271 /**************************************************************************** 16272 * Enums: tx_x2_control0_scr_modes 16273 */ 16274 #define tx_x2_control0_scr_modes_T_SCR_MODE_BYPASS 0 16275 #define tx_x2_control0_scr_modes_T_SCR_MODE_CL49 1 16276 #define tx_x2_control0_scr_modes_T_SCR_MODE_40G_2_LANE 2 16277 #define tx_x2_control0_scr_modes_T_SCR_MODE_100G 3 16278 #define tx_x2_control0_scr_modes_T_SCR_MODE_20G 4 16279 #define tx_x2_control0_scr_modes_T_SCR_MODE_40G_4_LANE 5 16280 16281 /**************************************************************************** 16282 * Enums: tx_x2_control0_descr_modes 16283 */ 16284 #define tx_x2_control0_descr_modes_R_DESCR_MODE_BYPASS 0 16285 #define tx_x2_control0_descr_modes_R_DESCR_MODE_CL49 1 16286 #define tx_x2_control0_descr_modes_R_DESCR_MODE_CL82 2 16287 16288 /**************************************************************************** 16289 * Enums: tx_x2_control0_r_dec_tl_mode 16290 */ 16291 #define tx_x2_control0_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 16292 #define tx_x2_control0_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 16293 #define tx_x2_control0_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 16294 16295 /**************************************************************************** 16296 * Enums: tx_x2_control0_r_dec_fsm_mode 16297 */ 16298 #define tx_x2_control0_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 16299 #define tx_x2_control0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 16300 #define tx_x2_control0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 16301 16302 /**************************************************************************** 16303 * Enums: tx_x2_control0_r_deskew_mode 16304 */ 16305 #define tx_x2_control0_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 16306 #define tx_x2_control0_r_deskew_mode_R_DESKEW_MODE_20G 1 16307 #define tx_x2_control0_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 16308 #define tx_x2_control0_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 16309 #define tx_x2_control0_r_deskew_mode_R_DESKEW_MODE_100G 4 16310 #define tx_x2_control0_r_deskew_mode_R_DESKEW_MODE_CL49 5 16311 #define tx_x2_control0_r_deskew_mode_R_DESKEW_MODE_CL91_QUAD 6 16312 #define tx_x2_control0_r_deskew_mode_R_DESKEW_MODE_CL91_SINGLE_BRCM 7 16313 #define tx_x2_control0_r_deskew_mode_R_DESKEW_MODE_CL91_DUAL_BRCM 8 16314 #define tx_x2_control0_r_deskew_mode_R_DESKEW_MODE_CL91_FC 9 16315 16316 /**************************************************************************** 16317 * Enums: tx_x2_control0_bs_dist_modes 16318 */ 16319 #define tx_x2_control0_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 16320 #define tx_x2_control0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 16321 #define tx_x2_control0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 16322 #define tx_x2_control0_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 16323 16324 /**************************************************************************** 16325 * Enums: tx_x2_control0_cl49_t_type 16326 */ 16327 #define tx_x2_control0_cl49_t_type_BAD_T_TYPE 15 16328 #define tx_x2_control0_cl49_t_type_T_TYPE_B0 11 16329 #define tx_x2_control0_cl49_t_type_T_TYPE_OB 10 16330 #define tx_x2_control0_cl49_t_type_T_TYPE_B1 9 16331 #define tx_x2_control0_cl49_t_type_T_TYPE_DB 8 16332 #define tx_x2_control0_cl49_t_type_T_TYPE_FC 7 16333 #define tx_x2_control0_cl49_t_type_T_TYPE_TB 6 16334 #define tx_x2_control0_cl49_t_type_T_TYPE_LI 5 16335 #define tx_x2_control0_cl49_t_type_T_TYPE_C 4 16336 #define tx_x2_control0_cl49_t_type_T_TYPE_S 3 16337 #define tx_x2_control0_cl49_t_type_T_TYPE_T 2 16338 #define tx_x2_control0_cl49_t_type_T_TYPE_D 1 16339 #define tx_x2_control0_cl49_t_type_T_TYPE_E 0 16340 16341 /**************************************************************************** 16342 * Enums: tx_x2_control0_cl49_txsm_states 16343 */ 16344 #define tx_x2_control0_cl49_txsm_states_TX_LI 5 16345 #define tx_x2_control0_cl49_txsm_states_TX_E 4 16346 #define tx_x2_control0_cl49_txsm_states_TX_T 3 16347 #define tx_x2_control0_cl49_txsm_states_TX_D 2 16348 #define tx_x2_control0_cl49_txsm_states_TX_C 1 16349 #define tx_x2_control0_cl49_txsm_states_TX_INIT 0 16350 16351 /**************************************************************************** 16352 * Enums: tx_x2_control0_cl49_ltxsm_states 16353 */ 16354 #define tx_x2_control0_cl49_ltxsm_states_TX_LI 32 16355 #define tx_x2_control0_cl49_ltxsm_states_TX_E 16 16356 #define tx_x2_control0_cl49_ltxsm_states_TX_T 8 16357 #define tx_x2_control0_cl49_ltxsm_states_TX_D 4 16358 #define tx_x2_control0_cl49_ltxsm_states_TX_C 2 16359 #define tx_x2_control0_cl49_ltxsm_states_TX_INIT 1 16360 16361 /**************************************************************************** 16362 * Enums: tx_x2_control0_burst_error_mode 16363 */ 16364 #define tx_x2_control0_burst_error_mode_BURST_ERROR_11_BITS 0 16365 #define tx_x2_control0_burst_error_mode_BURST_ERROR_16_BITS 1 16366 #define tx_x2_control0_burst_error_mode_BURST_ERROR_17_BITS 2 16367 #define tx_x2_control0_burst_error_mode_BURST_ERROR_18_BITS 3 16368 #define tx_x2_control0_burst_error_mode_BURST_ERROR_19_BITS 4 16369 #define tx_x2_control0_burst_error_mode_BURST_ERROR_20_BITS 5 16370 #define tx_x2_control0_burst_error_mode_BURST_ERROR_21_BITS 6 16371 #define tx_x2_control0_burst_error_mode_BURST_ERROR_22_BITS 7 16372 #define tx_x2_control0_burst_error_mode_BURST_ERROR_23_BITS 8 16373 #define tx_x2_control0_burst_error_mode_BURST_ERROR_24_BITS 9 16374 #define tx_x2_control0_burst_error_mode_BURST_ERROR_25_BITS 10 16375 #define tx_x2_control0_burst_error_mode_BURST_ERROR_26_BITS 11 16376 #define tx_x2_control0_burst_error_mode_BURST_ERROR_27_BITS 12 16377 #define tx_x2_control0_burst_error_mode_BURST_ERROR_28_BITS 13 16378 #define tx_x2_control0_burst_error_mode_BURST_ERROR_29_BITS 14 16379 #define tx_x2_control0_burst_error_mode_BURST_ERROR_30_BITS 15 16380 #define tx_x2_control0_burst_error_mode_BURST_ERROR_31_BITS 16 16381 #define tx_x2_control0_burst_error_mode_BURST_ERROR_32_BITS 17 16382 #define tx_x2_control0_burst_error_mode_BURST_ERROR_33_BITS 18 16383 #define tx_x2_control0_burst_error_mode_BURST_ERROR_34_BITS 19 16384 #define tx_x2_control0_burst_error_mode_BURST_ERROR_35_BITS 20 16385 #define tx_x2_control0_burst_error_mode_BURST_ERROR_36_BITS 21 16386 #define tx_x2_control0_burst_error_mode_BURST_ERROR_37_BITS 22 16387 #define tx_x2_control0_burst_error_mode_BURST_ERROR_38_BITS 23 16388 #define tx_x2_control0_burst_error_mode_BURST_ERROR_39_BITS 24 16389 #define tx_x2_control0_burst_error_mode_BURST_ERROR_40_BITS 25 16390 #define tx_x2_control0_burst_error_mode_BURST_ERROR_41_BITS 26 16391 16392 /**************************************************************************** 16393 * Enums: tx_x2_control0_bermon_state 16394 */ 16395 #define tx_x2_control0_bermon_state_HI_BER 4 16396 #define tx_x2_control0_bermon_state_GOOD_BER 3 16397 #define tx_x2_control0_bermon_state_BER_TEST_SH 2 16398 #define tx_x2_control0_bermon_state_START_TIMER 1 16399 #define tx_x2_control0_bermon_state_BER_MT_INIT 0 16400 16401 /**************************************************************************** 16402 * Enums: tx_x2_control0_rxsm_state_cl49 16403 */ 16404 #define tx_x2_control0_rxsm_state_cl49_RX_LI 32 16405 #define tx_x2_control0_rxsm_state_cl49_RX_E 16 16406 #define tx_x2_control0_rxsm_state_cl49_RX_T 8 16407 #define tx_x2_control0_rxsm_state_cl49_RX_D 4 16408 #define tx_x2_control0_rxsm_state_cl49_RX_C 2 16409 #define tx_x2_control0_rxsm_state_cl49_RX_INIT 1 16410 16411 /**************************************************************************** 16412 * Enums: tx_x2_control0_r_type 16413 */ 16414 #define tx_x2_control0_r_type_BAD_R_TYPE 15 16415 #define tx_x2_control0_r_type_R_TYPE_B0 11 16416 #define tx_x2_control0_r_type_R_TYPE_OB 10 16417 #define tx_x2_control0_r_type_R_TYPE_B1 9 16418 #define tx_x2_control0_r_type_R_TYPE_DB 8 16419 #define tx_x2_control0_r_type_R_TYPE_FC 7 16420 #define tx_x2_control0_r_type_R_TYPE_TB 6 16421 #define tx_x2_control0_r_type_R_TYPE_LI 5 16422 #define tx_x2_control0_r_type_R_TYPE_C 4 16423 #define tx_x2_control0_r_type_R_TYPE_S 3 16424 #define tx_x2_control0_r_type_R_TYPE_T 2 16425 #define tx_x2_control0_r_type_R_TYPE_D 1 16426 #define tx_x2_control0_r_type_R_TYPE_E 0 16427 16428 /**************************************************************************** 16429 * Enums: tx_x2_control0_am_lock_state 16430 */ 16431 #define tx_x2_control0_am_lock_state_INVALID_AM 512 16432 #define tx_x2_control0_am_lock_state_GOOD_AM 256 16433 #define tx_x2_control0_am_lock_state_COMP_AM 128 16434 #define tx_x2_control0_am_lock_state_TIMER_2 64 16435 #define tx_x2_control0_am_lock_state_AM_2_GOOD 32 16436 #define tx_x2_control0_am_lock_state_COMP_2ND 16 16437 #define tx_x2_control0_am_lock_state_TIMER_1 8 16438 #define tx_x2_control0_am_lock_state_FIND_1ST 4 16439 #define tx_x2_control0_am_lock_state_AM_RESET_CNT 2 16440 #define tx_x2_control0_am_lock_state_AM_LOCK_INIT 1 16441 16442 /**************************************************************************** 16443 * Enums: tx_x2_control0_msg_selector 16444 */ 16445 #define tx_x2_control0_msg_selector_RESERVED 0 16446 #define tx_x2_control0_msg_selector_VALUE_802p3 1 16447 #define tx_x2_control0_msg_selector_VALUE_802p9 2 16448 #define tx_x2_control0_msg_selector_VALUE_802p5 3 16449 #define tx_x2_control0_msg_selector_VALUE_1394 4 16450 16451 /**************************************************************************** 16452 * Enums: tx_x2_control0_synce_enum_stage1 16453 */ 16454 #define tx_x2_control0_synce_enum_stage1_SYNCE_NO_DIV 0 16455 #define tx_x2_control0_synce_enum_stage1_SYNCE_DIV_7 1 16456 #define tx_x2_control0_synce_enum_stage1_SYNCE_DIV_11 2 16457 16458 /**************************************************************************** 16459 * Enums: tx_x2_control0_synce_enum_stage0 16460 */ 16461 #define tx_x2_control0_synce_enum_stage0_SYNCE_NO_DIV 0 16462 #define tx_x2_control0_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 16463 #define tx_x2_control0_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 16464 16465 /**************************************************************************** 16466 * Enums: tx_x2_control0_cl91_sync_state 16467 */ 16468 #define tx_x2_control0_cl91_sync_state_FIND_1ST 0 16469 #define tx_x2_control0_cl91_sync_state_COUNT_NEXT 1 16470 #define tx_x2_control0_cl91_sync_state_COMP_2ND 2 16471 #define tx_x2_control0_cl91_sync_state_TWO_GOOD 3 16472 16473 /**************************************************************************** 16474 * Enums: tx_x2_control0_RS_FEC_sync_state 16475 */ 16476 #define tx_x2_control0_RS_FEC_sync_state_LOCK_INIT 0 16477 #define tx_x2_control0_RS_FEC_sync_state_FIND_1ST 1 16478 #define tx_x2_control0_RS_FEC_sync_state_COUNT_NEXT 2 16479 #define tx_x2_control0_RS_FEC_sync_state_COMP_2ND 3 16480 #define tx_x2_control0_RS_FEC_sync_state_TWO_GOOD 4 16481 16482 /**************************************************************************** 16483 * Enums: tx_x2_control0_cl91_algn_state 16484 */ 16485 #define tx_x2_control0_cl91_algn_state_LOSS_OF_ALIGNMENT 0 16486 #define tx_x2_control0_cl91_algn_state_DESKEW 1 16487 #define tx_x2_control0_cl91_algn_state_DESKEW_FAIL 2 16488 #define tx_x2_control0_cl91_algn_state_ALIGN_ACQUIRED 3 16489 #define tx_x2_control0_cl91_algn_state_CW_GOOD 4 16490 #define tx_x2_control0_cl91_algn_state_CW_BAD 5 16491 #define tx_x2_control0_cl91_algn_state_THREE_BAD 6 16492 16493 /**************************************************************************** 16494 * Enums: tx_x2_control0_RS_FEC_algn_state 16495 */ 16496 #define tx_x2_control0_RS_FEC_algn_state_LOSS_OF_ALIGNMENT 0 16497 #define tx_x2_control0_RS_FEC_algn_state_DESKEW 1 16498 #define tx_x2_control0_RS_FEC_algn_state_DESKEW_FAIL 2 16499 #define tx_x2_control0_RS_FEC_algn_state_ALIGN_ACQUIRED 3 16500 #define tx_x2_control0_RS_FEC_algn_state_CW_GOOD 4 16501 #define tx_x2_control0_RS_FEC_algn_state_CW_BAD 5 16502 #define tx_x2_control0_RS_FEC_algn_state_THREE_BAD 6 16503 16504 /**************************************************************************** 16505 * Enums: tx_x2_control0_fec_sel_override 16506 */ 16507 #define tx_x2_control0_fec_sel_override_NO_OVERRIDE 0 16508 #define tx_x2_control0_fec_sel_override_NO_FEC 1 16509 #define tx_x2_control0_fec_sel_override_FEC_CL74 2 16510 #define tx_x2_control0_fec_sel_override_FEC_CL91 3 16511 16512 /**************************************************************************** 16513 * Enums: tx_x2_control0_cl91_blksync_mode 16514 */ 16515 #define tx_x2_control0_cl91_blksync_mode_R_BLKSYNC_NO_CL91_FEC 0 16516 #define tx_x2_control0_cl91_blksync_mode_R_BLKSYNC_CL91_QUAD_LANE_FEC 1 16517 #define tx_x2_control0_cl91_blksync_mode_R_BLKSYNC_CL91_DUAL_LANE_FEC 2 16518 #define tx_x2_control0_cl91_blksync_mode_R_BLKSYNC_CL91_SINGLE_LANE_FEC 3 16519 #define tx_x2_control0_cl91_blksync_mode_R_BLKSYNC_CL91_FC_FEC 4 16520 16521 /**************************************************************************** 16522 * Enums: tx_x2_control0_r_merge_mode 16523 */ 16524 #define tx_x2_control0_r_merge_mode_R_MERGE_MODE_BYPASS 0 16525 #define tx_x2_control0_r_merge_mode_R_MERGE_MODE_CL91_FC 1 16526 #define tx_x2_control0_r_merge_mode_R_MERGE_MODE_CL91_SINGLE_LANE 2 16527 #define tx_x2_control0_r_merge_mode_R_MERGE_MODE_CL91_DUAL_LANE 3 16528 #define tx_x2_control0_r_merge_mode_R_MERGE_MODE_CL91_QUAD_LANE 4 16529 16530 /**************************************************************************** 16531 * Enums: tx_x2_control0_r_tc_mode 16532 */ 16533 #define tx_x2_control0_r_tc_mode_R_TC_MODE_SINGLE 0 16534 #define tx_x2_control0_r_tc_mode_R_TC_MODE_DUAL 1 16535 #define tx_x2_control0_r_tc_mode_R_TC_MODE_QUAD 2 16536 16537 /**************************************************************************** 16538 * Enums: tx_x2_control0_r_tc_out_mode 16539 */ 16540 #define tx_x2_control0_r_tc_out_mode_R_TC_OUT_MODE_SINGLE 0 16541 #define tx_x2_control0_r_tc_out_mode_R_TC_OUT_MODE_DUAL 1 16542 #define tx_x2_control0_r_tc_out_mode_R_TC_OUT_MODE_QUAD 2 16543 16544 /**************************************************************************** 16545 * Enums: tx_x2_control0_cl91_fec_mode 16546 */ 16547 #define tx_x2_control0_cl91_fec_mode_NO_CL91_FEC 0 16548 #define tx_x2_control0_cl91_fec_mode_CL91_SINGLE_LANE_FC 1 16549 #define tx_x2_control0_cl91_fec_mode_CL91_SINGLE_LANE_BRCM_PROP 2 16550 #define tx_x2_control0_cl91_fec_mode_CL91_DUAL_LANE_BRCM_PROP 3 16551 #define tx_x2_control0_cl91_fec_mode_CL91_QUAD_LANE 4 16552 #define tx_x2_control0_cl91_fec_mode_IEEE_25G_CL91_SINGLE_LANE 5 16553 16554 /**************************************************************************** 16555 * Enums: tx_x2_control0_RS_FEC_fec_mode 16556 */ 16557 #define tx_x2_control0_RS_FEC_fec_mode_NO_RS_FEC_FEC 0 16558 #define tx_x2_control0_RS_FEC_fec_mode_N_A 1 16559 #define tx_x2_control0_RS_FEC_fec_mode_RS_FEC_SINGLE_LANE_BRCM_PROP 2 16560 #define tx_x2_control0_RS_FEC_fec_mode_RS_FEC_DUAL_LANE_BRCM_PROP 3 16561 #define tx_x2_control0_RS_FEC_fec_mode_RS_FEC_QUAD_LANE 4 16562 #define tx_x2_control0_RS_FEC_fec_mode_IEEE_25G_RS_FEC_SINGLE_LANE 5 16563 16564 /**************************************************************************** 16565 * Enums: tx_x2_control0_am_spacing_mul 16566 */ 16567 #define tx_x2_control0_am_spacing_mul_AM_SPACING_MUL_2 0 16568 #define tx_x2_control0_am_spacing_mul_AM_SPACING_MUL_4 1 16569 #define tx_x2_control0_am_spacing_mul_AM_SPACING_MUL_5 2 16570 #define tx_x2_control0_am_spacing_mul_AM_SPACING_MUL_20 3 16571 16572 /**************************************************************************** 16573 * Enums: tx_x2_status0_cl36TxEEEStates_l 16574 */ 16575 #define tx_x2_status0_cl36TxEEEStates_l_TX_REFRESH 8 16576 #define tx_x2_status0_cl36TxEEEStates_l_TX_QUIET 4 16577 #define tx_x2_status0_cl36TxEEEStates_l_TX_SLEEP 2 16578 #define tx_x2_status0_cl36TxEEEStates_l_TX_ACTIVE 1 16579 16580 /**************************************************************************** 16581 * Enums: tx_x2_status0_cl36TxEEEStates_c 16582 */ 16583 #define tx_x2_status0_cl36TxEEEStates_c_TX_REFRESH 3 16584 #define tx_x2_status0_cl36TxEEEStates_c_TX_QUIET 2 16585 #define tx_x2_status0_cl36TxEEEStates_c_TX_SLEEP 1 16586 #define tx_x2_status0_cl36TxEEEStates_c_TX_ACTIVE 0 16587 16588 /**************************************************************************** 16589 * Enums: tx_x2_status0_cl49TxEEEStates_l 16590 */ 16591 #define tx_x2_status0_cl49TxEEEStates_l_SCR_RESET_2 64 16592 #define tx_x2_status0_cl49TxEEEStates_l_SCR_RESET_1 32 16593 #define tx_x2_status0_cl49TxEEEStates_l_TX_WAKE 16 16594 #define tx_x2_status0_cl49TxEEEStates_l_TX_REFRESH 8 16595 #define tx_x2_status0_cl49TxEEEStates_l_TX_QUIET 4 16596 #define tx_x2_status0_cl49TxEEEStates_l_TX_SLEEP 2 16597 #define tx_x2_status0_cl49TxEEEStates_l_TX_ACTIVE 1 16598 16599 /**************************************************************************** 16600 * Enums: tx_x2_status0_fec_req_enum 16601 */ 16602 #define tx_x2_status0_fec_req_enum_FEC_not_supported 0 16603 #define tx_x2_status0_fec_req_enum_FEC_supported_but_not_requested 1 16604 #define tx_x2_status0_fec_req_enum_invalid_setting 2 16605 #define tx_x2_status0_fec_req_enum_FEC_supported_and_requested 3 16606 16607 /**************************************************************************** 16608 * Enums: tx_x2_status0_cl73_pause_enum 16609 */ 16610 #define tx_x2_status0_cl73_pause_enum_No_PAUSE_ability 0 16611 #define tx_x2_status0_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 16612 #define tx_x2_status0_cl73_pause_enum_Symmetric_PAUSE_ability 1 16613 #define tx_x2_status0_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 16614 16615 /**************************************************************************** 16616 * Enums: tx_x2_status0_cl49TxEEEStates_c 16617 */ 16618 #define tx_x2_status0_cl49TxEEEStates_c_SCR_RESET_2 6 16619 #define tx_x2_status0_cl49TxEEEStates_c_SCR_RESET_1 5 16620 #define tx_x2_status0_cl49TxEEEStates_c_TX_WAKE 4 16621 #define tx_x2_status0_cl49TxEEEStates_c_TX_REFRESH 3 16622 #define tx_x2_status0_cl49TxEEEStates_c_TX_QUIET 2 16623 #define tx_x2_status0_cl49TxEEEStates_c_TX_SLEEP 1 16624 #define tx_x2_status0_cl49TxEEEStates_c_TX_ACTIVE 0 16625 16626 /**************************************************************************** 16627 * Enums: tx_x2_status0_cl36RxEEEStates_l 16628 */ 16629 #define tx_x2_status0_cl36RxEEEStates_l_RX_LINK_FAIL 32 16630 #define tx_x2_status0_cl36RxEEEStates_l_RX_WTF 16 16631 #define tx_x2_status0_cl36RxEEEStates_l_RX_WAKE 8 16632 #define tx_x2_status0_cl36RxEEEStates_l_RX_QUIET 4 16633 #define tx_x2_status0_cl36RxEEEStates_l_RX_SLEEP 2 16634 #define tx_x2_status0_cl36RxEEEStates_l_RX_ACTIVE 1 16635 16636 /**************************************************************************** 16637 * Enums: tx_x2_status0_cl36RxEEEStates_c 16638 */ 16639 #define tx_x2_status0_cl36RxEEEStates_c_RX_LINK_FAIL 5 16640 #define tx_x2_status0_cl36RxEEEStates_c_RX_WTF 4 16641 #define tx_x2_status0_cl36RxEEEStates_c_RX_WAKE 3 16642 #define tx_x2_status0_cl36RxEEEStates_c_RX_QUIET 2 16643 #define tx_x2_status0_cl36RxEEEStates_c_RX_SLEEP 1 16644 #define tx_x2_status0_cl36RxEEEStates_c_RX_ACTIVE 0 16645 16646 /**************************************************************************** 16647 * Enums: tx_x2_status0_cl49RxEEEStates_l 16648 */ 16649 #define tx_x2_status0_cl49RxEEEStates_l_RX_LINK_FAIL 32 16650 #define tx_x2_status0_cl49RxEEEStates_l_RX_WTF 16 16651 #define tx_x2_status0_cl49RxEEEStates_l_RX_WAKE 8 16652 #define tx_x2_status0_cl49RxEEEStates_l_RX_QUIET 4 16653 #define tx_x2_status0_cl49RxEEEStates_l_RX_SLEEP 2 16654 #define tx_x2_status0_cl49RxEEEStates_l_RX_ACTIVE 1 16655 16656 /**************************************************************************** 16657 * Enums: tx_x2_status0_cl49RxEEEStates_c 16658 */ 16659 #define tx_x2_status0_cl49RxEEEStates_c_RX_LINK_FAIL 5 16660 #define tx_x2_status0_cl49RxEEEStates_c_RX_WTF 4 16661 #define tx_x2_status0_cl49RxEEEStates_c_RX_WAKE 3 16662 #define tx_x2_status0_cl49RxEEEStates_c_RX_QUIET 2 16663 #define tx_x2_status0_cl49RxEEEStates_c_RX_SLEEP 1 16664 #define tx_x2_status0_cl49RxEEEStates_c_RX_ACTIVE 0 16665 16666 /**************************************************************************** 16667 * Enums: tx_x2_status0_cl48TxEEEStates_l 16668 */ 16669 #define tx_x2_status0_cl48TxEEEStates_l_TX_REFRESH 8 16670 #define tx_x2_status0_cl48TxEEEStates_l_TX_QUIET 4 16671 #define tx_x2_status0_cl48TxEEEStates_l_TX_SLEEP 2 16672 #define tx_x2_status0_cl48TxEEEStates_l_TX_ACTIVE 1 16673 16674 /**************************************************************************** 16675 * Enums: tx_x2_status0_cl48TxEEEStates_c 16676 */ 16677 #define tx_x2_status0_cl48TxEEEStates_c_TX_REFRESH 3 16678 #define tx_x2_status0_cl48TxEEEStates_c_TX_QUIET 2 16679 #define tx_x2_status0_cl48TxEEEStates_c_TX_SLEEP 1 16680 #define tx_x2_status0_cl48TxEEEStates_c_TX_ACTIVE 0 16681 16682 /**************************************************************************** 16683 * Enums: tx_x2_status0_cl48RxEEEStates_l 16684 */ 16685 #define tx_x2_status0_cl48RxEEEStates_l_RX_LINK_FAIL 32 16686 #define tx_x2_status0_cl48RxEEEStates_l_RX_WAKE 16 16687 #define tx_x2_status0_cl48RxEEEStates_l_RX_QUIET 8 16688 #define tx_x2_status0_cl48RxEEEStates_l_RX_DEACT 4 16689 #define tx_x2_status0_cl48RxEEEStates_l_RX_SLEEP 2 16690 #define tx_x2_status0_cl48RxEEEStates_l_RX_ACTIVE 1 16691 16692 /**************************************************************************** 16693 * Enums: tx_x2_status0_cl48RxEEEStates_c 16694 */ 16695 #define tx_x2_status0_cl48RxEEEStates_c_RX_LINK_FAIL 5 16696 #define tx_x2_status0_cl48RxEEEStates_c_RX_WAKE 4 16697 #define tx_x2_status0_cl48RxEEEStates_c_RX_QUIET 3 16698 #define tx_x2_status0_cl48RxEEEStates_c_RX_DEACT 2 16699 #define tx_x2_status0_cl48RxEEEStates_c_RX_SLEEP 1 16700 #define tx_x2_status0_cl48RxEEEStates_c_RX_ACTIVE 0 16701 16702 /**************************************************************************** 16703 * Enums: tx_x2_status0_IQP_Options 16704 */ 16705 #define tx_x2_status0_IQP_Options_i50uA 0 16706 #define tx_x2_status0_IQP_Options_i100uA 1 16707 #define tx_x2_status0_IQP_Options_i150uA 2 16708 #define tx_x2_status0_IQP_Options_i200uA 3 16709 #define tx_x2_status0_IQP_Options_i250uA 4 16710 #define tx_x2_status0_IQP_Options_i300uA 5 16711 #define tx_x2_status0_IQP_Options_i350uA 6 16712 #define tx_x2_status0_IQP_Options_i400uA 7 16713 #define tx_x2_status0_IQP_Options_i450uA 8 16714 #define tx_x2_status0_IQP_Options_i500uA 9 16715 #define tx_x2_status0_IQP_Options_i550uA 10 16716 #define tx_x2_status0_IQP_Options_i600uA 11 16717 #define tx_x2_status0_IQP_Options_i650uA 12 16718 #define tx_x2_status0_IQP_Options_i700uA 13 16719 #define tx_x2_status0_IQP_Options_i750uA 14 16720 #define tx_x2_status0_IQP_Options_i800uA 15 16721 16722 /**************************************************************************** 16723 * Enums: tx_x2_status0_IDriver_Options 16724 */ 16725 #define tx_x2_status0_IDriver_Options_v680mV 0 16726 #define tx_x2_status0_IDriver_Options_v730mV 1 16727 #define tx_x2_status0_IDriver_Options_v780mV 2 16728 #define tx_x2_status0_IDriver_Options_v830mV 3 16729 #define tx_x2_status0_IDriver_Options_v880mV 4 16730 #define tx_x2_status0_IDriver_Options_v930mV 5 16731 #define tx_x2_status0_IDriver_Options_v980mV 6 16732 #define tx_x2_status0_IDriver_Options_v1010mV 7 16733 #define tx_x2_status0_IDriver_Options_v1040mV 8 16734 #define tx_x2_status0_IDriver_Options_v1060mV 9 16735 #define tx_x2_status0_IDriver_Options_v1070mV 10 16736 #define tx_x2_status0_IDriver_Options_v1080mV 11 16737 #define tx_x2_status0_IDriver_Options_v1085mV 12 16738 #define tx_x2_status0_IDriver_Options_v1090mV 13 16739 #define tx_x2_status0_IDriver_Options_v1095mV 14 16740 #define tx_x2_status0_IDriver_Options_v1100mV 15 16741 16742 /**************************************************************************** 16743 * Enums: tx_x2_status0_operationModes 16744 */ 16745 #define tx_x2_status0_operationModes_XGXS 0 16746 #define tx_x2_status0_operationModes_XGXG_nCC 1 16747 #define tx_x2_status0_operationModes_Indlane_OS8 4 16748 #define tx_x2_status0_operationModes_IndLane_OS5 5 16749 #define tx_x2_status0_operationModes_PCI 7 16750 #define tx_x2_status0_operationModes_XGXS_nLQ 8 16751 #define tx_x2_status0_operationModes_XGXS_nLQnCC 9 16752 #define tx_x2_status0_operationModes_PBypass 10 16753 #define tx_x2_status0_operationModes_PBypass_nDSK 11 16754 #define tx_x2_status0_operationModes_ComboCoreMode 12 16755 #define tx_x2_status0_operationModes_Clocks_off 15 16756 16757 /**************************************************************************** 16758 * Enums: tx_x2_status0_actualSpeeds 16759 */ 16760 #define tx_x2_status0_actualSpeeds_dr_10M 0 16761 #define tx_x2_status0_actualSpeeds_dr_100M 1 16762 #define tx_x2_status0_actualSpeeds_dr_1G 2 16763 #define tx_x2_status0_actualSpeeds_dr_2p5G 3 16764 #define tx_x2_status0_actualSpeeds_dr_5G_X4 4 16765 #define tx_x2_status0_actualSpeeds_dr_6G_X4 5 16766 #define tx_x2_status0_actualSpeeds_dr_10G_HiG 6 16767 #define tx_x2_status0_actualSpeeds_dr_10G_CX4 7 16768 #define tx_x2_status0_actualSpeeds_dr_12G_HiG 8 16769 #define tx_x2_status0_actualSpeeds_dr_12p5G_X4 9 16770 #define tx_x2_status0_actualSpeeds_dr_13G_X4 10 16771 #define tx_x2_status0_actualSpeeds_dr_15G_X4 11 16772 #define tx_x2_status0_actualSpeeds_dr_16G_X4 12 16773 #define tx_x2_status0_actualSpeeds_dr_1G_KX 13 16774 #define tx_x2_status0_actualSpeeds_dr_10G_KX4 14 16775 #define tx_x2_status0_actualSpeeds_dr_10G_KR 15 16776 #define tx_x2_status0_actualSpeeds_dr_5G 16 16777 #define tx_x2_status0_actualSpeeds_dr_6p4G 17 16778 #define tx_x2_status0_actualSpeeds_dr_20G_X4 18 16779 #define tx_x2_status0_actualSpeeds_dr_21G_X4 19 16780 #define tx_x2_status0_actualSpeeds_dr_25G_X4 20 16781 #define tx_x2_status0_actualSpeeds_dr_10G_HiG_DXGXS 21 16782 #define tx_x2_status0_actualSpeeds_dr_10G_DXGXS 22 16783 #define tx_x2_status0_actualSpeeds_dr_10p5G_HiG_DXGXS 23 16784 #define tx_x2_status0_actualSpeeds_dr_10p5G_DXGXS 24 16785 #define tx_x2_status0_actualSpeeds_dr_12p773G_HiG_DXGXS 25 16786 #define tx_x2_status0_actualSpeeds_dr_12p773G_DXGXS 26 16787 #define tx_x2_status0_actualSpeeds_dr_10G_XFI 27 16788 #define tx_x2_status0_actualSpeeds_dr_40G 28 16789 #define tx_x2_status0_actualSpeeds_dr_20G_HiG_DXGXS 29 16790 #define tx_x2_status0_actualSpeeds_dr_20G_DXGXS 30 16791 #define tx_x2_status0_actualSpeeds_dr_10G_SFI 31 16792 #define tx_x2_status0_actualSpeeds_dr_31p5G 32 16793 #define tx_x2_status0_actualSpeeds_dr_32p7G 33 16794 #define tx_x2_status0_actualSpeeds_dr_20G_SCR 34 16795 #define tx_x2_status0_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 16796 #define tx_x2_status0_actualSpeeds_dr_10G_DXGXS_SCR 36 16797 #define tx_x2_status0_actualSpeeds_dr_12G_R2 37 16798 #define tx_x2_status0_actualSpeeds_dr_10G_X2 38 16799 #define tx_x2_status0_actualSpeeds_dr_40G_KR4 39 16800 #define tx_x2_status0_actualSpeeds_dr_40G_CR4 40 16801 #define tx_x2_status0_actualSpeeds_dr_100G_CR10 41 16802 #define tx_x2_status0_actualSpeeds_dr_15p75G_DXGXS 44 16803 #define tx_x2_status0_actualSpeeds_dr_20G_KR2 57 16804 #define tx_x2_status0_actualSpeeds_dr_20G_CR2 58 16805 16806 /**************************************************************************** 16807 * Enums: tx_x2_status0_actualSpeedsMisc1 16808 */ 16809 #define tx_x2_status0_actualSpeedsMisc1_dr_2500BRCM_X1 16 16810 #define tx_x2_status0_actualSpeedsMisc1_dr_5000BRCM_X4 17 16811 #define tx_x2_status0_actualSpeedsMisc1_dr_6000BRCM_X4 18 16812 #define tx_x2_status0_actualSpeedsMisc1_dr_10GHiGig_X4 19 16813 #define tx_x2_status0_actualSpeedsMisc1_dr_10GBASE_CX4 20 16814 #define tx_x2_status0_actualSpeedsMisc1_dr_12GHiGig_X4 21 16815 #define tx_x2_status0_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 16816 #define tx_x2_status0_actualSpeedsMisc1_dr_13GHiGig_X4 23 16817 #define tx_x2_status0_actualSpeedsMisc1_dr_15GHiGig_X4 24 16818 #define tx_x2_status0_actualSpeedsMisc1_dr_16GHiGig_X4 25 16819 #define tx_x2_status0_actualSpeedsMisc1_dr_5000BRCM_X1 26 16820 #define tx_x2_status0_actualSpeedsMisc1_dr_6363BRCM_X1 27 16821 #define tx_x2_status0_actualSpeedsMisc1_dr_20GHiGig_X4 28 16822 #define tx_x2_status0_actualSpeedsMisc1_dr_21GHiGig_X4 29 16823 #define tx_x2_status0_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 16824 #define tx_x2_status0_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 16825 16826 /**************************************************************************** 16827 * Enums: tx_x2_status0_IndLaneModes 16828 */ 16829 #define tx_x2_status0_IndLaneModes_SWSDR_div2 0 16830 #define tx_x2_status0_IndLaneModes_SWSDR_div1 1 16831 #define tx_x2_status0_IndLaneModes_DWSDR_div2 2 16832 #define tx_x2_status0_IndLaneModes_DWSDR_div1 3 16833 16834 /**************************************************************************** 16835 * Enums: tx_x2_status0_prbsSelect 16836 */ 16837 #define tx_x2_status0_prbsSelect_prbs7 0 16838 #define tx_x2_status0_prbsSelect_prbs15 1 16839 #define tx_x2_status0_prbsSelect_prbs23 2 16840 #define tx_x2_status0_prbsSelect_prbs31 3 16841 16842 /**************************************************************************** 16843 * Enums: tx_x2_status0_vcoDivider 16844 */ 16845 #define tx_x2_status0_vcoDivider_div32 0 16846 #define tx_x2_status0_vcoDivider_div36 1 16847 #define tx_x2_status0_vcoDivider_div40 2 16848 #define tx_x2_status0_vcoDivider_div42 3 16849 #define tx_x2_status0_vcoDivider_div48 4 16850 #define tx_x2_status0_vcoDivider_div50 5 16851 #define tx_x2_status0_vcoDivider_div52 6 16852 #define tx_x2_status0_vcoDivider_div54 7 16853 #define tx_x2_status0_vcoDivider_div60 8 16854 #define tx_x2_status0_vcoDivider_div64 9 16855 #define tx_x2_status0_vcoDivider_div66 10 16856 #define tx_x2_status0_vcoDivider_div68 11 16857 #define tx_x2_status0_vcoDivider_div70 12 16858 #define tx_x2_status0_vcoDivider_div80 13 16859 #define tx_x2_status0_vcoDivider_div92 14 16860 #define tx_x2_status0_vcoDivider_div100 15 16861 16862 /**************************************************************************** 16863 * Enums: tx_x2_status0_refClkSelect 16864 */ 16865 #define tx_x2_status0_refClkSelect_clk_156p25MHz 1 16866 #define tx_x2_status0_refClkSelect_clk_312p5Mhz 2 16867 16868 /**************************************************************************** 16869 * Enums: tx_x2_status0_aerMMDdevTypeSelect 16870 */ 16871 #define tx_x2_status0_aerMMDdevTypeSelect_combo_core 0 16872 #define tx_x2_status0_aerMMDdevTypeSelect_PMA_PMD 1 16873 #define tx_x2_status0_aerMMDdevTypeSelect_PCS 3 16874 #define tx_x2_status0_aerMMDdevTypeSelect_PHY 4 16875 #define tx_x2_status0_aerMMDdevTypeSelect_DTE 5 16876 #define tx_x2_status0_aerMMDdevTypeSelect_CL73_AN 7 16877 16878 /**************************************************************************** 16879 * Enums: tx_x2_status0_aerMMDportSelect 16880 */ 16881 #define tx_x2_status0_aerMMDportSelect_ln0 0 16882 #define tx_x2_status0_aerMMDportSelect_ln1 1 16883 #define tx_x2_status0_aerMMDportSelect_ln2 2 16884 #define tx_x2_status0_aerMMDportSelect_ln3 3 16885 #define tx_x2_status0_aerMMDportSelect_BCST_ln0_1_2_3 511 16886 #define tx_x2_status0_aerMMDportSelect_BCST_ln0_1 512 16887 #define tx_x2_status0_aerMMDportSelect_BCST_ln2_3 513 16888 16889 /**************************************************************************** 16890 * Enums: tx_x2_status0_firmwareModeSelect 16891 */ 16892 #define tx_x2_status0_firmwareModeSelect_DEFAULT 0 16893 #define tx_x2_status0_firmwareModeSelect_SFP_OPT_LR 1 16894 #define tx_x2_status0_firmwareModeSelect_SFP_DAC 2 16895 #define tx_x2_status0_firmwareModeSelect_XLAUI 3 16896 #define tx_x2_status0_firmwareModeSelect_LONG_CH_6G 4 16897 16898 /**************************************************************************** 16899 * Enums: tx_x2_status0_tempIdxSelect 16900 */ 16901 #define tx_x2_status0_tempIdxSelect_LTE__22p9C 15 16902 #define tx_x2_status0_tempIdxSelect_LTE__12p6C 14 16903 #define tx_x2_status0_tempIdxSelect_LTE__3p0C 13 16904 #define tx_x2_status0_tempIdxSelect_LTE_6p7C 12 16905 #define tx_x2_status0_tempIdxSelect_LTE_16p4C 11 16906 #define tx_x2_status0_tempIdxSelect_LTE_26p6C 10 16907 #define tx_x2_status0_tempIdxSelect_LTE_36p3C 9 16908 #define tx_x2_status0_tempIdxSelect_LTE_46p0C 8 16909 #define tx_x2_status0_tempIdxSelect_LTE_56p2C 7 16910 #define tx_x2_status0_tempIdxSelect_LTE_65p9C 6 16911 #define tx_x2_status0_tempIdxSelect_LTE_75p6C 5 16912 #define tx_x2_status0_tempIdxSelect_LTE_85p3C 4 16913 #define tx_x2_status0_tempIdxSelect_LTE_95p5C 3 16914 #define tx_x2_status0_tempIdxSelect_LTE_105p2C 2 16915 #define tx_x2_status0_tempIdxSelect_LTE_114p9C 1 16916 #define tx_x2_status0_tempIdxSelect_LTE_125p1C 0 16917 16918 /**************************************************************************** 16919 * Enums: tx_x2_status0_port_mode 16920 */ 16921 #define tx_x2_status0_port_mode_QUAD_PORT 0 16922 #define tx_x2_status0_port_mode_TRI_1_PORT 1 16923 #define tx_x2_status0_port_mode_TRI_2_PORT 2 16924 #define tx_x2_status0_port_mode_DUAL_PORT 3 16925 #define tx_x2_status0_port_mode_SINGLE_PORT 4 16926 #define tx_x2_status0_port_mode_SINGLE_OCTAL_PORT 5 16927 16928 /**************************************************************************** 16929 * Enums: tx_x2_status0_rev_letter_enum 16930 */ 16931 #define tx_x2_status0_rev_letter_enum_REV_A 0 16932 #define tx_x2_status0_rev_letter_enum_REV_B 1 16933 #define tx_x2_status0_rev_letter_enum_REV_C 2 16934 #define tx_x2_status0_rev_letter_enum_REV_D 3 16935 16936 /**************************************************************************** 16937 * Enums: tx_x2_status0_rev_number_enum 16938 */ 16939 #define tx_x2_status0_rev_number_enum_REV_0 0 16940 #define tx_x2_status0_rev_number_enum_REV_1 1 16941 #define tx_x2_status0_rev_number_enum_REV_2 2 16942 #define tx_x2_status0_rev_number_enum_REV_3 3 16943 #define tx_x2_status0_rev_number_enum_REV_4 4 16944 #define tx_x2_status0_rev_number_enum_REV_5 5 16945 #define tx_x2_status0_rev_number_enum_REV_6 6 16946 #define tx_x2_status0_rev_number_enum_REV_7 7 16947 16948 /**************************************************************************** 16949 * Enums: tx_x2_status0_bonding_enum 16950 */ 16951 #define tx_x2_status0_bonding_enum_WIRE_BOND 0 16952 #define tx_x2_status0_bonding_enum_FLIP_CHIP 1 16953 16954 /**************************************************************************** 16955 * Enums: tx_x2_status0_tech_process 16956 */ 16957 #define tx_x2_status0_tech_process_PROCESS_90NM 0 16958 #define tx_x2_status0_tech_process_PROCESS_65NM 1 16959 #define tx_x2_status0_tech_process_PROCESS_40NM 2 16960 #define tx_x2_status0_tech_process_PROCESS_28NM 3 16961 #define tx_x2_status0_tech_process_PROCESS_16NM 4 16962 16963 /**************************************************************************** 16964 * Enums: tx_x2_status0_model_num 16965 */ 16966 #define tx_x2_status0_model_num_SERDES_CL73 0 16967 #define tx_x2_status0_model_num_XGXS_16G 1 16968 #define tx_x2_status0_model_num_HYPERCORE 2 16969 #define tx_x2_status0_model_num_HYPERLITE 3 16970 #define tx_x2_status0_model_num_PCIE_G2_PIPE 4 16971 #define tx_x2_status0_model_num_SERDES_1p25GBd 5 16972 #define tx_x2_status0_model_num_SATA2 6 16973 #define tx_x2_status0_model_num_QSGMII 7 16974 #define tx_x2_status0_model_num_XGXS10G 8 16975 #define tx_x2_status0_model_num_WARPCORE 9 16976 #define tx_x2_status0_model_num_XFICORE 10 16977 #define tx_x2_status0_model_num_RXFI 11 16978 #define tx_x2_status0_model_num_WARPLITE 12 16979 #define tx_x2_status0_model_num_PENTACORE 13 16980 #define tx_x2_status0_model_num_ESM 14 16981 #define tx_x2_status0_model_num_QUAD_SGMII 15 16982 #define tx_x2_status0_model_num_WARPCORE_3 16 16983 #define tx_x2_status0_model_num_TSC 17 16984 #define tx_x2_status0_model_num_TSC4E 18 16985 #define tx_x2_status0_model_num_TSC12E 19 16986 #define tx_x2_status0_model_num_TSC4F 20 16987 #define tx_x2_status0_model_num_TSC4F_GEN2 21 16988 #define tx_x2_status0_model_num_XGXS_CL73_90NM 29 16989 #define tx_x2_status0_model_num_SERDES_CL73_90NM 30 16990 #define tx_x2_status0_model_num_WARPCORE3 32 16991 #define tx_x2_status0_model_num_WARPCORE4_TSC 33 16992 #define tx_x2_status0_model_num_RXAUI 34 16993 #define tx_x2_status0_model_num_TSCE_GEN3 35 16994 #define tx_x2_status0_model_num_TSC4F_GEN3 36 16995 #define tx_x2_status0_model_num_TSCBH 37 16996 16997 /**************************************************************************** 16998 * Enums: tx_x2_status0_payload 16999 */ 17000 #define tx_x2_status0_payload_REPEAT_2_BYTES 0 17001 #define tx_x2_status0_payload_RAMPING 1 17002 #define tx_x2_status0_payload_CL48_CRPAT 2 17003 #define tx_x2_status0_payload_CL48_CJPAT 3 17004 #define tx_x2_status0_payload_CL36_LONG_CRPAT 4 17005 #define tx_x2_status0_payload_CL36_SHORT_CRPAT 5 17006 17007 /**************************************************************************** 17008 * Enums: tx_x2_status0_sc 17009 */ 17010 #define tx_x2_status0_sc_SPEED_10G_IEEE_KR1 0 17011 #define tx_x2_status0_sc_SPEED_25G_IEEE_KS1_CS1 1 17012 #define tx_x2_status0_sc_SPEED_25G_IEEE_KR1_CR1 2 17013 #define tx_x2_status0_sc_SPEED_40G_IEEE_KR4 3 17014 #define tx_x2_status0_sc_SPEED_40G_IEEE_CR4 4 17015 #define tx_x2_status0_sc_SPEED_50G_IEEE_KR1_CR1 5 17016 #define tx_x2_status0_sc_SPEED_100G_IEEE_KR4 6 17017 #define tx_x2_status0_sc_SPEED_100G_IEEE_CR4 7 17018 #define tx_x2_status0_sc_SPEED_100G_IEEE_KR2_CR2 8 17019 #define tx_x2_status0_sc_SPEED_200G_IEEE_KR4_CR4 9 17020 #define tx_x2_status0_sc_SPEED_400G_IEEE_X8 10 17021 #define tx_x2_status0_sc_SPEED_CL73_IEEE_20GVCO 11 17022 #define tx_x2_status0_sc_SPEED_CL73_IEEE_25GVCO 12 17023 #define tx_x2_status0_sc_SPEED_CL73_IEEE_26GVCO 13 17024 #define tx_x2_status0_sc_SPEED_20G_BRCM_CR1 14 17025 #define tx_x2_status0_sc_SPEED_20G_BRCM_KR1 15 17026 #define tx_x2_status0_sc_SPEED_25G_BRCM_CR1 16 17027 #define tx_x2_status0_sc_SPEED_25G_BRCM_KR1 17 17028 #define tx_x2_status0_sc_SPEED_40G_BRCM_CR2 18 17029 #define tx_x2_status0_sc_SPEED_40G_BRCM_KR2 19 17030 #define tx_x2_status0_sc_SPEED_50G_BRCM_CR2 20 17031 #define tx_x2_status0_sc_SPEED_50G_BRCM_KR2 21 17032 #define tx_x2_status0_sc_SPEED_50G_BRCM_CR4 22 17033 #define tx_x2_status0_sc_SPEED_50G_BRCM_KR4 23 17034 #define tx_x2_status0_sc_SPEED_50G_BRCM_FEC_544_CR2_KR2 24 17035 #define tx_x2_status0_sc_SPEED_RESERVED_19 25 17036 #define tx_x2_status0_sc_SPEED_50G_BRCM_FEC_544_CR1_KR1 26 17037 #define tx_x2_status0_sc_SPEED_50G_BRCM_NO_FEC_CR1_KR1 27 17038 #define tx_x2_status0_sc_SPEED_50G_BRCM_FEC_528_CR1_KR1 28 17039 #define tx_x2_status0_sc_SPEED_400G_BRCM_NO_FEC_KR8_CR8 29 17040 #define tx_x2_status0_sc_SPEED_400G_BRCM_FEC_KR8_CR8 30 17041 #define tx_x2_status0_sc_SPEED_200G_BRCM_NO_FEC_KR4_CR4 31 17042 #define tx_x2_status0_sc_SPEED_200G_BRCM_KR4_CR4 32 17043 #define tx_x2_status0_sc_SPEED_100G_BRCM_KR4_CR4 33 17044 #define tx_x2_status0_sc_SPEED_RESERVED_22 34 17045 #define tx_x2_status0_sc_SPEED_100G_BRCM_FEC_528_KR2_CR2 35 17046 #define tx_x2_status0_sc_SPEED_100G_BRCM_NO_FEC_KR2_CR2 36 17047 #define tx_x2_status0_sc_SPEED_100G_BRCM_NO_FEC_X4 37 17048 17049 /**************************************************************************** 17050 * Enums: tx_x2_status0_t_fifo_modes 17051 */ 17052 #define tx_x2_status0_t_fifo_modes_T_FIFO_INSERT_NO_AM 0 17053 #define tx_x2_status0_t_fifo_modes_T_FIFO_INSERT_4_AM 1 17054 #define tx_x2_status0_t_fifo_modes_T_FIFO_INSERT_20_AM 2 17055 #define tx_x2_status0_t_fifo_modes_T_FIFO_INSERT_2_AM 3 17056 17057 /**************************************************************************** 17058 * Enums: tx_x2_status0_t_enc_modes 17059 */ 17060 #define tx_x2_status0_t_enc_modes_T_ENC_MODE_BYPASS 0 17061 #define tx_x2_status0_t_enc_modes_T_ENC_MODE_CL49 1 17062 #define tx_x2_status0_t_enc_modes_T_ENC_MODE_CL82 2 17063 17064 /**************************************************************************** 17065 * Enums: tx_x2_status0_btmx_mode 17066 */ 17067 #define tx_x2_status0_btmx_mode_BS_BTMX_MODE_1to1 0 17068 #define tx_x2_status0_btmx_mode_BS_BTMX_MODE_2to1 1 17069 #define tx_x2_status0_btmx_mode_BS_BTMX_MODE_5to1 2 17070 17071 /**************************************************************************** 17072 * Enums: tx_x2_status0_t_type_cl82 17073 */ 17074 #define tx_x2_status0_t_type_cl82_T_TYPE_B1 5 17075 #define tx_x2_status0_t_type_cl82_T_TYPE_C 4 17076 #define tx_x2_status0_t_type_cl82_T_TYPE_S 3 17077 #define tx_x2_status0_t_type_cl82_T_TYPE_T 2 17078 #define tx_x2_status0_t_type_cl82_T_TYPE_D 1 17079 #define tx_x2_status0_t_type_cl82_T_TYPE_E 0 17080 17081 /**************************************************************************** 17082 * Enums: tx_x2_status0_txsm_state_cl82 17083 */ 17084 #define tx_x2_status0_txsm_state_cl82_TX_E 4 17085 #define tx_x2_status0_txsm_state_cl82_TX_T 3 17086 #define tx_x2_status0_txsm_state_cl82_TX_D 2 17087 #define tx_x2_status0_txsm_state_cl82_TX_C 1 17088 #define tx_x2_status0_txsm_state_cl82_TX_INIT 0 17089 17090 /**************************************************************************** 17091 * Enums: tx_x2_status0_ltxsm_state_cl82 17092 */ 17093 #define tx_x2_status0_ltxsm_state_cl82_TX_E 16 17094 #define tx_x2_status0_ltxsm_state_cl82_TX_T 8 17095 #define tx_x2_status0_ltxsm_state_cl82_TX_D 4 17096 #define tx_x2_status0_ltxsm_state_cl82_TX_C 2 17097 #define tx_x2_status0_ltxsm_state_cl82_TX_INIT 1 17098 17099 /**************************************************************************** 17100 * Enums: tx_x2_status0_r_type_coded_cl82 17101 */ 17102 #define tx_x2_status0_r_type_coded_cl82_R_TYPE_B1 32 17103 #define tx_x2_status0_r_type_coded_cl82_R_TYPE_C 16 17104 #define tx_x2_status0_r_type_coded_cl82_R_TYPE_S 8 17105 #define tx_x2_status0_r_type_coded_cl82_R_TYPE_T 4 17106 #define tx_x2_status0_r_type_coded_cl82_R_TYPE_D 2 17107 #define tx_x2_status0_r_type_coded_cl82_R_TYPE_E 1 17108 17109 /**************************************************************************** 17110 * Enums: tx_x2_status0_rxsm_state_cl82 17111 */ 17112 #define tx_x2_status0_rxsm_state_cl82_RX_E 16 17113 #define tx_x2_status0_rxsm_state_cl82_RX_T 8 17114 #define tx_x2_status0_rxsm_state_cl82_RX_D 4 17115 #define tx_x2_status0_rxsm_state_cl82_RX_C 2 17116 #define tx_x2_status0_rxsm_state_cl82_RX_INIT 1 17117 17118 /**************************************************************************** 17119 * Enums: tx_x2_status0_deskew_state 17120 */ 17121 #define tx_x2_status0_deskew_state_ALIGN_ACQUIRED 2 17122 #define tx_x2_status0_deskew_state_LOSS_OF_ALIGNMENT 1 17123 17124 /**************************************************************************** 17125 * Enums: tx_x2_status0_os_mode_enum 17126 */ 17127 #define tx_x2_status0_os_mode_enum_OS_MODE_1 0 17128 #define tx_x2_status0_os_mode_enum_OS_MODE_2 1 17129 #define tx_x2_status0_os_mode_enum_OS_MODE_4 2 17130 #define tx_x2_status0_os_mode_enum_OS_MODE_16p5 8 17131 #define tx_x2_status0_os_mode_enum_OS_MODE_20p625 12 17132 17133 /**************************************************************************** 17134 * Enums: tx_x2_status0_scr_modes 17135 */ 17136 #define tx_x2_status0_scr_modes_T_SCR_MODE_BYPASS 0 17137 #define tx_x2_status0_scr_modes_T_SCR_MODE_CL49 1 17138 #define tx_x2_status0_scr_modes_T_SCR_MODE_40G_2_LANE 2 17139 #define tx_x2_status0_scr_modes_T_SCR_MODE_100G 3 17140 #define tx_x2_status0_scr_modes_T_SCR_MODE_20G 4 17141 #define tx_x2_status0_scr_modes_T_SCR_MODE_40G_4_LANE 5 17142 17143 /**************************************************************************** 17144 * Enums: tx_x2_status0_descr_modes 17145 */ 17146 #define tx_x2_status0_descr_modes_R_DESCR_MODE_BYPASS 0 17147 #define tx_x2_status0_descr_modes_R_DESCR_MODE_CL49 1 17148 #define tx_x2_status0_descr_modes_R_DESCR_MODE_CL82 2 17149 17150 /**************************************************************************** 17151 * Enums: tx_x2_status0_r_dec_tl_mode 17152 */ 17153 #define tx_x2_status0_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 17154 #define tx_x2_status0_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 17155 #define tx_x2_status0_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 17156 17157 /**************************************************************************** 17158 * Enums: tx_x2_status0_r_dec_fsm_mode 17159 */ 17160 #define tx_x2_status0_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 17161 #define tx_x2_status0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 17162 #define tx_x2_status0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 17163 17164 /**************************************************************************** 17165 * Enums: tx_x2_status0_r_deskew_mode 17166 */ 17167 #define tx_x2_status0_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 17168 #define tx_x2_status0_r_deskew_mode_R_DESKEW_MODE_20G 1 17169 #define tx_x2_status0_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 17170 #define tx_x2_status0_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 17171 #define tx_x2_status0_r_deskew_mode_R_DESKEW_MODE_100G 4 17172 #define tx_x2_status0_r_deskew_mode_R_DESKEW_MODE_CL49 5 17173 #define tx_x2_status0_r_deskew_mode_R_DESKEW_MODE_CL91_QUAD 6 17174 #define tx_x2_status0_r_deskew_mode_R_DESKEW_MODE_CL91_SINGLE_BRCM 7 17175 #define tx_x2_status0_r_deskew_mode_R_DESKEW_MODE_CL91_DUAL_BRCM 8 17176 #define tx_x2_status0_r_deskew_mode_R_DESKEW_MODE_CL91_FC 9 17177 17178 /**************************************************************************** 17179 * Enums: tx_x2_status0_bs_dist_modes 17180 */ 17181 #define tx_x2_status0_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 17182 #define tx_x2_status0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 17183 #define tx_x2_status0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 17184 #define tx_x2_status0_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 17185 17186 /**************************************************************************** 17187 * Enums: tx_x2_status0_cl49_t_type 17188 */ 17189 #define tx_x2_status0_cl49_t_type_BAD_T_TYPE 15 17190 #define tx_x2_status0_cl49_t_type_T_TYPE_B0 11 17191 #define tx_x2_status0_cl49_t_type_T_TYPE_OB 10 17192 #define tx_x2_status0_cl49_t_type_T_TYPE_B1 9 17193 #define tx_x2_status0_cl49_t_type_T_TYPE_DB 8 17194 #define tx_x2_status0_cl49_t_type_T_TYPE_FC 7 17195 #define tx_x2_status0_cl49_t_type_T_TYPE_TB 6 17196 #define tx_x2_status0_cl49_t_type_T_TYPE_LI 5 17197 #define tx_x2_status0_cl49_t_type_T_TYPE_C 4 17198 #define tx_x2_status0_cl49_t_type_T_TYPE_S 3 17199 #define tx_x2_status0_cl49_t_type_T_TYPE_T 2 17200 #define tx_x2_status0_cl49_t_type_T_TYPE_D 1 17201 #define tx_x2_status0_cl49_t_type_T_TYPE_E 0 17202 17203 /**************************************************************************** 17204 * Enums: tx_x2_status0_cl49_txsm_states 17205 */ 17206 #define tx_x2_status0_cl49_txsm_states_TX_LI 5 17207 #define tx_x2_status0_cl49_txsm_states_TX_E 4 17208 #define tx_x2_status0_cl49_txsm_states_TX_T 3 17209 #define tx_x2_status0_cl49_txsm_states_TX_D 2 17210 #define tx_x2_status0_cl49_txsm_states_TX_C 1 17211 #define tx_x2_status0_cl49_txsm_states_TX_INIT 0 17212 17213 /**************************************************************************** 17214 * Enums: tx_x2_status0_cl49_ltxsm_states 17215 */ 17216 #define tx_x2_status0_cl49_ltxsm_states_TX_LI 32 17217 #define tx_x2_status0_cl49_ltxsm_states_TX_E 16 17218 #define tx_x2_status0_cl49_ltxsm_states_TX_T 8 17219 #define tx_x2_status0_cl49_ltxsm_states_TX_D 4 17220 #define tx_x2_status0_cl49_ltxsm_states_TX_C 2 17221 #define tx_x2_status0_cl49_ltxsm_states_TX_INIT 1 17222 17223 /**************************************************************************** 17224 * Enums: tx_x2_status0_burst_error_mode 17225 */ 17226 #define tx_x2_status0_burst_error_mode_BURST_ERROR_11_BITS 0 17227 #define tx_x2_status0_burst_error_mode_BURST_ERROR_16_BITS 1 17228 #define tx_x2_status0_burst_error_mode_BURST_ERROR_17_BITS 2 17229 #define tx_x2_status0_burst_error_mode_BURST_ERROR_18_BITS 3 17230 #define tx_x2_status0_burst_error_mode_BURST_ERROR_19_BITS 4 17231 #define tx_x2_status0_burst_error_mode_BURST_ERROR_20_BITS 5 17232 #define tx_x2_status0_burst_error_mode_BURST_ERROR_21_BITS 6 17233 #define tx_x2_status0_burst_error_mode_BURST_ERROR_22_BITS 7 17234 #define tx_x2_status0_burst_error_mode_BURST_ERROR_23_BITS 8 17235 #define tx_x2_status0_burst_error_mode_BURST_ERROR_24_BITS 9 17236 #define tx_x2_status0_burst_error_mode_BURST_ERROR_25_BITS 10 17237 #define tx_x2_status0_burst_error_mode_BURST_ERROR_26_BITS 11 17238 #define tx_x2_status0_burst_error_mode_BURST_ERROR_27_BITS 12 17239 #define tx_x2_status0_burst_error_mode_BURST_ERROR_28_BITS 13 17240 #define tx_x2_status0_burst_error_mode_BURST_ERROR_29_BITS 14 17241 #define tx_x2_status0_burst_error_mode_BURST_ERROR_30_BITS 15 17242 #define tx_x2_status0_burst_error_mode_BURST_ERROR_31_BITS 16 17243 #define tx_x2_status0_burst_error_mode_BURST_ERROR_32_BITS 17 17244 #define tx_x2_status0_burst_error_mode_BURST_ERROR_33_BITS 18 17245 #define tx_x2_status0_burst_error_mode_BURST_ERROR_34_BITS 19 17246 #define tx_x2_status0_burst_error_mode_BURST_ERROR_35_BITS 20 17247 #define tx_x2_status0_burst_error_mode_BURST_ERROR_36_BITS 21 17248 #define tx_x2_status0_burst_error_mode_BURST_ERROR_37_BITS 22 17249 #define tx_x2_status0_burst_error_mode_BURST_ERROR_38_BITS 23 17250 #define tx_x2_status0_burst_error_mode_BURST_ERROR_39_BITS 24 17251 #define tx_x2_status0_burst_error_mode_BURST_ERROR_40_BITS 25 17252 #define tx_x2_status0_burst_error_mode_BURST_ERROR_41_BITS 26 17253 17254 /**************************************************************************** 17255 * Enums: tx_x2_status0_bermon_state 17256 */ 17257 #define tx_x2_status0_bermon_state_HI_BER 4 17258 #define tx_x2_status0_bermon_state_GOOD_BER 3 17259 #define tx_x2_status0_bermon_state_BER_TEST_SH 2 17260 #define tx_x2_status0_bermon_state_START_TIMER 1 17261 #define tx_x2_status0_bermon_state_BER_MT_INIT 0 17262 17263 /**************************************************************************** 17264 * Enums: tx_x2_status0_rxsm_state_cl49 17265 */ 17266 #define tx_x2_status0_rxsm_state_cl49_RX_LI 32 17267 #define tx_x2_status0_rxsm_state_cl49_RX_E 16 17268 #define tx_x2_status0_rxsm_state_cl49_RX_T 8 17269 #define tx_x2_status0_rxsm_state_cl49_RX_D 4 17270 #define tx_x2_status0_rxsm_state_cl49_RX_C 2 17271 #define tx_x2_status0_rxsm_state_cl49_RX_INIT 1 17272 17273 /**************************************************************************** 17274 * Enums: tx_x2_status0_r_type 17275 */ 17276 #define tx_x2_status0_r_type_BAD_R_TYPE 15 17277 #define tx_x2_status0_r_type_R_TYPE_B0 11 17278 #define tx_x2_status0_r_type_R_TYPE_OB 10 17279 #define tx_x2_status0_r_type_R_TYPE_B1 9 17280 #define tx_x2_status0_r_type_R_TYPE_DB 8 17281 #define tx_x2_status0_r_type_R_TYPE_FC 7 17282 #define tx_x2_status0_r_type_R_TYPE_TB 6 17283 #define tx_x2_status0_r_type_R_TYPE_LI 5 17284 #define tx_x2_status0_r_type_R_TYPE_C 4 17285 #define tx_x2_status0_r_type_R_TYPE_S 3 17286 #define tx_x2_status0_r_type_R_TYPE_T 2 17287 #define tx_x2_status0_r_type_R_TYPE_D 1 17288 #define tx_x2_status0_r_type_R_TYPE_E 0 17289 17290 /**************************************************************************** 17291 * Enums: tx_x2_status0_am_lock_state 17292 */ 17293 #define tx_x2_status0_am_lock_state_INVALID_AM 512 17294 #define tx_x2_status0_am_lock_state_GOOD_AM 256 17295 #define tx_x2_status0_am_lock_state_COMP_AM 128 17296 #define tx_x2_status0_am_lock_state_TIMER_2 64 17297 #define tx_x2_status0_am_lock_state_AM_2_GOOD 32 17298 #define tx_x2_status0_am_lock_state_COMP_2ND 16 17299 #define tx_x2_status0_am_lock_state_TIMER_1 8 17300 #define tx_x2_status0_am_lock_state_FIND_1ST 4 17301 #define tx_x2_status0_am_lock_state_AM_RESET_CNT 2 17302 #define tx_x2_status0_am_lock_state_AM_LOCK_INIT 1 17303 17304 /**************************************************************************** 17305 * Enums: tx_x2_status0_msg_selector 17306 */ 17307 #define tx_x2_status0_msg_selector_RESERVED 0 17308 #define tx_x2_status0_msg_selector_VALUE_802p3 1 17309 #define tx_x2_status0_msg_selector_VALUE_802p9 2 17310 #define tx_x2_status0_msg_selector_VALUE_802p5 3 17311 #define tx_x2_status0_msg_selector_VALUE_1394 4 17312 17313 /**************************************************************************** 17314 * Enums: tx_x2_status0_synce_enum_stage1 17315 */ 17316 #define tx_x2_status0_synce_enum_stage1_SYNCE_NO_DIV 0 17317 #define tx_x2_status0_synce_enum_stage1_SYNCE_DIV_7 1 17318 #define tx_x2_status0_synce_enum_stage1_SYNCE_DIV_11 2 17319 17320 /**************************************************************************** 17321 * Enums: tx_x2_status0_synce_enum_stage0 17322 */ 17323 #define tx_x2_status0_synce_enum_stage0_SYNCE_NO_DIV 0 17324 #define tx_x2_status0_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 17325 #define tx_x2_status0_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 17326 17327 /**************************************************************************** 17328 * Enums: tx_x2_status0_cl91_sync_state 17329 */ 17330 #define tx_x2_status0_cl91_sync_state_FIND_1ST 0 17331 #define tx_x2_status0_cl91_sync_state_COUNT_NEXT 1 17332 #define tx_x2_status0_cl91_sync_state_COMP_2ND 2 17333 #define tx_x2_status0_cl91_sync_state_TWO_GOOD 3 17334 17335 /**************************************************************************** 17336 * Enums: tx_x2_status0_RS_FEC_sync_state 17337 */ 17338 #define tx_x2_status0_RS_FEC_sync_state_LOCK_INIT 0 17339 #define tx_x2_status0_RS_FEC_sync_state_FIND_1ST 1 17340 #define tx_x2_status0_RS_FEC_sync_state_COUNT_NEXT 2 17341 #define tx_x2_status0_RS_FEC_sync_state_COMP_2ND 3 17342 #define tx_x2_status0_RS_FEC_sync_state_TWO_GOOD 4 17343 17344 /**************************************************************************** 17345 * Enums: tx_x2_status0_cl91_algn_state 17346 */ 17347 #define tx_x2_status0_cl91_algn_state_LOSS_OF_ALIGNMENT 0 17348 #define tx_x2_status0_cl91_algn_state_DESKEW 1 17349 #define tx_x2_status0_cl91_algn_state_DESKEW_FAIL 2 17350 #define tx_x2_status0_cl91_algn_state_ALIGN_ACQUIRED 3 17351 #define tx_x2_status0_cl91_algn_state_CW_GOOD 4 17352 #define tx_x2_status0_cl91_algn_state_CW_BAD 5 17353 #define tx_x2_status0_cl91_algn_state_THREE_BAD 6 17354 17355 /**************************************************************************** 17356 * Enums: tx_x2_status0_RS_FEC_algn_state 17357 */ 17358 #define tx_x2_status0_RS_FEC_algn_state_LOSS_OF_ALIGNMENT 0 17359 #define tx_x2_status0_RS_FEC_algn_state_DESKEW 1 17360 #define tx_x2_status0_RS_FEC_algn_state_DESKEW_FAIL 2 17361 #define tx_x2_status0_RS_FEC_algn_state_ALIGN_ACQUIRED 3 17362 #define tx_x2_status0_RS_FEC_algn_state_CW_GOOD 4 17363 #define tx_x2_status0_RS_FEC_algn_state_CW_BAD 5 17364 #define tx_x2_status0_RS_FEC_algn_state_THREE_BAD 6 17365 17366 /**************************************************************************** 17367 * Enums: tx_x2_status0_fec_sel_override 17368 */ 17369 #define tx_x2_status0_fec_sel_override_NO_OVERRIDE 0 17370 #define tx_x2_status0_fec_sel_override_NO_FEC 1 17371 #define tx_x2_status0_fec_sel_override_FEC_CL74 2 17372 #define tx_x2_status0_fec_sel_override_FEC_CL91 3 17373 17374 /**************************************************************************** 17375 * Enums: tx_x2_status0_cl91_blksync_mode 17376 */ 17377 #define tx_x2_status0_cl91_blksync_mode_R_BLKSYNC_NO_CL91_FEC 0 17378 #define tx_x2_status0_cl91_blksync_mode_R_BLKSYNC_CL91_QUAD_LANE_FEC 1 17379 #define tx_x2_status0_cl91_blksync_mode_R_BLKSYNC_CL91_DUAL_LANE_FEC 2 17380 #define tx_x2_status0_cl91_blksync_mode_R_BLKSYNC_CL91_SINGLE_LANE_FEC 3 17381 #define tx_x2_status0_cl91_blksync_mode_R_BLKSYNC_CL91_FC_FEC 4 17382 17383 /**************************************************************************** 17384 * Enums: tx_x2_status0_r_merge_mode 17385 */ 17386 #define tx_x2_status0_r_merge_mode_R_MERGE_MODE_BYPASS 0 17387 #define tx_x2_status0_r_merge_mode_R_MERGE_MODE_CL91_FC 1 17388 #define tx_x2_status0_r_merge_mode_R_MERGE_MODE_CL91_SINGLE_LANE 2 17389 #define tx_x2_status0_r_merge_mode_R_MERGE_MODE_CL91_DUAL_LANE 3 17390 #define tx_x2_status0_r_merge_mode_R_MERGE_MODE_CL91_QUAD_LANE 4 17391 17392 /**************************************************************************** 17393 * Enums: tx_x2_status0_r_tc_mode 17394 */ 17395 #define tx_x2_status0_r_tc_mode_R_TC_MODE_SINGLE 0 17396 #define tx_x2_status0_r_tc_mode_R_TC_MODE_DUAL 1 17397 #define tx_x2_status0_r_tc_mode_R_TC_MODE_QUAD 2 17398 17399 /**************************************************************************** 17400 * Enums: tx_x2_status0_r_tc_out_mode 17401 */ 17402 #define tx_x2_status0_r_tc_out_mode_R_TC_OUT_MODE_SINGLE 0 17403 #define tx_x2_status0_r_tc_out_mode_R_TC_OUT_MODE_DUAL 1 17404 #define tx_x2_status0_r_tc_out_mode_R_TC_OUT_MODE_QUAD 2 17405 17406 /**************************************************************************** 17407 * Enums: tx_x2_status0_cl91_fec_mode 17408 */ 17409 #define tx_x2_status0_cl91_fec_mode_NO_CL91_FEC 0 17410 #define tx_x2_status0_cl91_fec_mode_CL91_SINGLE_LANE_FC 1 17411 #define tx_x2_status0_cl91_fec_mode_CL91_SINGLE_LANE_BRCM_PROP 2 17412 #define tx_x2_status0_cl91_fec_mode_CL91_DUAL_LANE_BRCM_PROP 3 17413 #define tx_x2_status0_cl91_fec_mode_CL91_QUAD_LANE 4 17414 #define tx_x2_status0_cl91_fec_mode_IEEE_25G_CL91_SINGLE_LANE 5 17415 17416 /**************************************************************************** 17417 * Enums: tx_x2_status0_RS_FEC_fec_mode 17418 */ 17419 #define tx_x2_status0_RS_FEC_fec_mode_NO_RS_FEC_FEC 0 17420 #define tx_x2_status0_RS_FEC_fec_mode_N_A 1 17421 #define tx_x2_status0_RS_FEC_fec_mode_RS_FEC_SINGLE_LANE_BRCM_PROP 2 17422 #define tx_x2_status0_RS_FEC_fec_mode_RS_FEC_DUAL_LANE_BRCM_PROP 3 17423 #define tx_x2_status0_RS_FEC_fec_mode_RS_FEC_QUAD_LANE 4 17424 #define tx_x2_status0_RS_FEC_fec_mode_IEEE_25G_RS_FEC_SINGLE_LANE 5 17425 17426 /**************************************************************************** 17427 * Enums: tx_x2_status0_am_spacing_mul 17428 */ 17429 #define tx_x2_status0_am_spacing_mul_AM_SPACING_MUL_2 0 17430 #define tx_x2_status0_am_spacing_mul_AM_SPACING_MUL_4 1 17431 #define tx_x2_status0_am_spacing_mul_AM_SPACING_MUL_5 2 17432 #define tx_x2_status0_am_spacing_mul_AM_SPACING_MUL_20 3 17433 17434 /**************************************************************************** 17435 * Enums: tx_x4_control0_cl36TxEEEStates_l 17436 */ 17437 #define tx_x4_control0_cl36TxEEEStates_l_TX_REFRESH 8 17438 #define tx_x4_control0_cl36TxEEEStates_l_TX_QUIET 4 17439 #define tx_x4_control0_cl36TxEEEStates_l_TX_SLEEP 2 17440 #define tx_x4_control0_cl36TxEEEStates_l_TX_ACTIVE 1 17441 17442 /**************************************************************************** 17443 * Enums: tx_x4_control0_cl36TxEEEStates_c 17444 */ 17445 #define tx_x4_control0_cl36TxEEEStates_c_TX_REFRESH 3 17446 #define tx_x4_control0_cl36TxEEEStates_c_TX_QUIET 2 17447 #define tx_x4_control0_cl36TxEEEStates_c_TX_SLEEP 1 17448 #define tx_x4_control0_cl36TxEEEStates_c_TX_ACTIVE 0 17449 17450 /**************************************************************************** 17451 * Enums: tx_x4_control0_cl49TxEEEStates_l 17452 */ 17453 #define tx_x4_control0_cl49TxEEEStates_l_SCR_RESET_2 64 17454 #define tx_x4_control0_cl49TxEEEStates_l_SCR_RESET_1 32 17455 #define tx_x4_control0_cl49TxEEEStates_l_TX_WAKE 16 17456 #define tx_x4_control0_cl49TxEEEStates_l_TX_REFRESH 8 17457 #define tx_x4_control0_cl49TxEEEStates_l_TX_QUIET 4 17458 #define tx_x4_control0_cl49TxEEEStates_l_TX_SLEEP 2 17459 #define tx_x4_control0_cl49TxEEEStates_l_TX_ACTIVE 1 17460 17461 /**************************************************************************** 17462 * Enums: tx_x4_control0_fec_req_enum 17463 */ 17464 #define tx_x4_control0_fec_req_enum_FEC_not_supported 0 17465 #define tx_x4_control0_fec_req_enum_FEC_supported_but_not_requested 1 17466 #define tx_x4_control0_fec_req_enum_invalid_setting 2 17467 #define tx_x4_control0_fec_req_enum_FEC_supported_and_requested 3 17468 17469 /**************************************************************************** 17470 * Enums: tx_x4_control0_cl73_pause_enum 17471 */ 17472 #define tx_x4_control0_cl73_pause_enum_No_PAUSE_ability 0 17473 #define tx_x4_control0_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 17474 #define tx_x4_control0_cl73_pause_enum_Symmetric_PAUSE_ability 1 17475 #define tx_x4_control0_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 17476 17477 /**************************************************************************** 17478 * Enums: tx_x4_control0_cl49TxEEEStates_c 17479 */ 17480 #define tx_x4_control0_cl49TxEEEStates_c_SCR_RESET_2 6 17481 #define tx_x4_control0_cl49TxEEEStates_c_SCR_RESET_1 5 17482 #define tx_x4_control0_cl49TxEEEStates_c_TX_WAKE 4 17483 #define tx_x4_control0_cl49TxEEEStates_c_TX_REFRESH 3 17484 #define tx_x4_control0_cl49TxEEEStates_c_TX_QUIET 2 17485 #define tx_x4_control0_cl49TxEEEStates_c_TX_SLEEP 1 17486 #define tx_x4_control0_cl49TxEEEStates_c_TX_ACTIVE 0 17487 17488 /**************************************************************************** 17489 * Enums: tx_x4_control0_cl36RxEEEStates_l 17490 */ 17491 #define tx_x4_control0_cl36RxEEEStates_l_RX_LINK_FAIL 32 17492 #define tx_x4_control0_cl36RxEEEStates_l_RX_WTF 16 17493 #define tx_x4_control0_cl36RxEEEStates_l_RX_WAKE 8 17494 #define tx_x4_control0_cl36RxEEEStates_l_RX_QUIET 4 17495 #define tx_x4_control0_cl36RxEEEStates_l_RX_SLEEP 2 17496 #define tx_x4_control0_cl36RxEEEStates_l_RX_ACTIVE 1 17497 17498 /**************************************************************************** 17499 * Enums: tx_x4_control0_cl36RxEEEStates_c 17500 */ 17501 #define tx_x4_control0_cl36RxEEEStates_c_RX_LINK_FAIL 5 17502 #define tx_x4_control0_cl36RxEEEStates_c_RX_WTF 4 17503 #define tx_x4_control0_cl36RxEEEStates_c_RX_WAKE 3 17504 #define tx_x4_control0_cl36RxEEEStates_c_RX_QUIET 2 17505 #define tx_x4_control0_cl36RxEEEStates_c_RX_SLEEP 1 17506 #define tx_x4_control0_cl36RxEEEStates_c_RX_ACTIVE 0 17507 17508 /**************************************************************************** 17509 * Enums: tx_x4_control0_cl49RxEEEStates_l 17510 */ 17511 #define tx_x4_control0_cl49RxEEEStates_l_RX_LINK_FAIL 32 17512 #define tx_x4_control0_cl49RxEEEStates_l_RX_WTF 16 17513 #define tx_x4_control0_cl49RxEEEStates_l_RX_WAKE 8 17514 #define tx_x4_control0_cl49RxEEEStates_l_RX_QUIET 4 17515 #define tx_x4_control0_cl49RxEEEStates_l_RX_SLEEP 2 17516 #define tx_x4_control0_cl49RxEEEStates_l_RX_ACTIVE 1 17517 17518 /**************************************************************************** 17519 * Enums: tx_x4_control0_cl49RxEEEStates_c 17520 */ 17521 #define tx_x4_control0_cl49RxEEEStates_c_RX_LINK_FAIL 5 17522 #define tx_x4_control0_cl49RxEEEStates_c_RX_WTF 4 17523 #define tx_x4_control0_cl49RxEEEStates_c_RX_WAKE 3 17524 #define tx_x4_control0_cl49RxEEEStates_c_RX_QUIET 2 17525 #define tx_x4_control0_cl49RxEEEStates_c_RX_SLEEP 1 17526 #define tx_x4_control0_cl49RxEEEStates_c_RX_ACTIVE 0 17527 17528 /**************************************************************************** 17529 * Enums: tx_x4_control0_cl48TxEEEStates_l 17530 */ 17531 #define tx_x4_control0_cl48TxEEEStates_l_TX_REFRESH 8 17532 #define tx_x4_control0_cl48TxEEEStates_l_TX_QUIET 4 17533 #define tx_x4_control0_cl48TxEEEStates_l_TX_SLEEP 2 17534 #define tx_x4_control0_cl48TxEEEStates_l_TX_ACTIVE 1 17535 17536 /**************************************************************************** 17537 * Enums: tx_x4_control0_cl48TxEEEStates_c 17538 */ 17539 #define tx_x4_control0_cl48TxEEEStates_c_TX_REFRESH 3 17540 #define tx_x4_control0_cl48TxEEEStates_c_TX_QUIET 2 17541 #define tx_x4_control0_cl48TxEEEStates_c_TX_SLEEP 1 17542 #define tx_x4_control0_cl48TxEEEStates_c_TX_ACTIVE 0 17543 17544 /**************************************************************************** 17545 * Enums: tx_x4_control0_cl48RxEEEStates_l 17546 */ 17547 #define tx_x4_control0_cl48RxEEEStates_l_RX_LINK_FAIL 32 17548 #define tx_x4_control0_cl48RxEEEStates_l_RX_WAKE 16 17549 #define tx_x4_control0_cl48RxEEEStates_l_RX_QUIET 8 17550 #define tx_x4_control0_cl48RxEEEStates_l_RX_DEACT 4 17551 #define tx_x4_control0_cl48RxEEEStates_l_RX_SLEEP 2 17552 #define tx_x4_control0_cl48RxEEEStates_l_RX_ACTIVE 1 17553 17554 /**************************************************************************** 17555 * Enums: tx_x4_control0_cl48RxEEEStates_c 17556 */ 17557 #define tx_x4_control0_cl48RxEEEStates_c_RX_LINK_FAIL 5 17558 #define tx_x4_control0_cl48RxEEEStates_c_RX_WAKE 4 17559 #define tx_x4_control0_cl48RxEEEStates_c_RX_QUIET 3 17560 #define tx_x4_control0_cl48RxEEEStates_c_RX_DEACT 2 17561 #define tx_x4_control0_cl48RxEEEStates_c_RX_SLEEP 1 17562 #define tx_x4_control0_cl48RxEEEStates_c_RX_ACTIVE 0 17563 17564 /**************************************************************************** 17565 * Enums: tx_x4_control0_IQP_Options 17566 */ 17567 #define tx_x4_control0_IQP_Options_i50uA 0 17568 #define tx_x4_control0_IQP_Options_i100uA 1 17569 #define tx_x4_control0_IQP_Options_i150uA 2 17570 #define tx_x4_control0_IQP_Options_i200uA 3 17571 #define tx_x4_control0_IQP_Options_i250uA 4 17572 #define tx_x4_control0_IQP_Options_i300uA 5 17573 #define tx_x4_control0_IQP_Options_i350uA 6 17574 #define tx_x4_control0_IQP_Options_i400uA 7 17575 #define tx_x4_control0_IQP_Options_i450uA 8 17576 #define tx_x4_control0_IQP_Options_i500uA 9 17577 #define tx_x4_control0_IQP_Options_i550uA 10 17578 #define tx_x4_control0_IQP_Options_i600uA 11 17579 #define tx_x4_control0_IQP_Options_i650uA 12 17580 #define tx_x4_control0_IQP_Options_i700uA 13 17581 #define tx_x4_control0_IQP_Options_i750uA 14 17582 #define tx_x4_control0_IQP_Options_i800uA 15 17583 17584 /**************************************************************************** 17585 * Enums: tx_x4_control0_IDriver_Options 17586 */ 17587 #define tx_x4_control0_IDriver_Options_v680mV 0 17588 #define tx_x4_control0_IDriver_Options_v730mV 1 17589 #define tx_x4_control0_IDriver_Options_v780mV 2 17590 #define tx_x4_control0_IDriver_Options_v830mV 3 17591 #define tx_x4_control0_IDriver_Options_v880mV 4 17592 #define tx_x4_control0_IDriver_Options_v930mV 5 17593 #define tx_x4_control0_IDriver_Options_v980mV 6 17594 #define tx_x4_control0_IDriver_Options_v1010mV 7 17595 #define tx_x4_control0_IDriver_Options_v1040mV 8 17596 #define tx_x4_control0_IDriver_Options_v1060mV 9 17597 #define tx_x4_control0_IDriver_Options_v1070mV 10 17598 #define tx_x4_control0_IDriver_Options_v1080mV 11 17599 #define tx_x4_control0_IDriver_Options_v1085mV 12 17600 #define tx_x4_control0_IDriver_Options_v1090mV 13 17601 #define tx_x4_control0_IDriver_Options_v1095mV 14 17602 #define tx_x4_control0_IDriver_Options_v1100mV 15 17603 17604 /**************************************************************************** 17605 * Enums: tx_x4_control0_operationModes 17606 */ 17607 #define tx_x4_control0_operationModes_XGXS 0 17608 #define tx_x4_control0_operationModes_XGXG_nCC 1 17609 #define tx_x4_control0_operationModes_Indlane_OS8 4 17610 #define tx_x4_control0_operationModes_IndLane_OS5 5 17611 #define tx_x4_control0_operationModes_PCI 7 17612 #define tx_x4_control0_operationModes_XGXS_nLQ 8 17613 #define tx_x4_control0_operationModes_XGXS_nLQnCC 9 17614 #define tx_x4_control0_operationModes_PBypass 10 17615 #define tx_x4_control0_operationModes_PBypass_nDSK 11 17616 #define tx_x4_control0_operationModes_ComboCoreMode 12 17617 #define tx_x4_control0_operationModes_Clocks_off 15 17618 17619 /**************************************************************************** 17620 * Enums: tx_x4_control0_actualSpeeds 17621 */ 17622 #define tx_x4_control0_actualSpeeds_dr_10M 0 17623 #define tx_x4_control0_actualSpeeds_dr_100M 1 17624 #define tx_x4_control0_actualSpeeds_dr_1G 2 17625 #define tx_x4_control0_actualSpeeds_dr_2p5G 3 17626 #define tx_x4_control0_actualSpeeds_dr_5G_X4 4 17627 #define tx_x4_control0_actualSpeeds_dr_6G_X4 5 17628 #define tx_x4_control0_actualSpeeds_dr_10G_HiG 6 17629 #define tx_x4_control0_actualSpeeds_dr_10G_CX4 7 17630 #define tx_x4_control0_actualSpeeds_dr_12G_HiG 8 17631 #define tx_x4_control0_actualSpeeds_dr_12p5G_X4 9 17632 #define tx_x4_control0_actualSpeeds_dr_13G_X4 10 17633 #define tx_x4_control0_actualSpeeds_dr_15G_X4 11 17634 #define tx_x4_control0_actualSpeeds_dr_16G_X4 12 17635 #define tx_x4_control0_actualSpeeds_dr_1G_KX 13 17636 #define tx_x4_control0_actualSpeeds_dr_10G_KX4 14 17637 #define tx_x4_control0_actualSpeeds_dr_10G_KR 15 17638 #define tx_x4_control0_actualSpeeds_dr_5G 16 17639 #define tx_x4_control0_actualSpeeds_dr_6p4G 17 17640 #define tx_x4_control0_actualSpeeds_dr_20G_X4 18 17641 #define tx_x4_control0_actualSpeeds_dr_21G_X4 19 17642 #define tx_x4_control0_actualSpeeds_dr_25G_X4 20 17643 #define tx_x4_control0_actualSpeeds_dr_10G_HiG_DXGXS 21 17644 #define tx_x4_control0_actualSpeeds_dr_10G_DXGXS 22 17645 #define tx_x4_control0_actualSpeeds_dr_10p5G_HiG_DXGXS 23 17646 #define tx_x4_control0_actualSpeeds_dr_10p5G_DXGXS 24 17647 #define tx_x4_control0_actualSpeeds_dr_12p773G_HiG_DXGXS 25 17648 #define tx_x4_control0_actualSpeeds_dr_12p773G_DXGXS 26 17649 #define tx_x4_control0_actualSpeeds_dr_10G_XFI 27 17650 #define tx_x4_control0_actualSpeeds_dr_40G 28 17651 #define tx_x4_control0_actualSpeeds_dr_20G_HiG_DXGXS 29 17652 #define tx_x4_control0_actualSpeeds_dr_20G_DXGXS 30 17653 #define tx_x4_control0_actualSpeeds_dr_10G_SFI 31 17654 #define tx_x4_control0_actualSpeeds_dr_31p5G 32 17655 #define tx_x4_control0_actualSpeeds_dr_32p7G 33 17656 #define tx_x4_control0_actualSpeeds_dr_20G_SCR 34 17657 #define tx_x4_control0_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 17658 #define tx_x4_control0_actualSpeeds_dr_10G_DXGXS_SCR 36 17659 #define tx_x4_control0_actualSpeeds_dr_12G_R2 37 17660 #define tx_x4_control0_actualSpeeds_dr_10G_X2 38 17661 #define tx_x4_control0_actualSpeeds_dr_40G_KR4 39 17662 #define tx_x4_control0_actualSpeeds_dr_40G_CR4 40 17663 #define tx_x4_control0_actualSpeeds_dr_100G_CR10 41 17664 #define tx_x4_control0_actualSpeeds_dr_15p75G_DXGXS 44 17665 #define tx_x4_control0_actualSpeeds_dr_20G_KR2 57 17666 #define tx_x4_control0_actualSpeeds_dr_20G_CR2 58 17667 17668 /**************************************************************************** 17669 * Enums: tx_x4_control0_actualSpeedsMisc1 17670 */ 17671 #define tx_x4_control0_actualSpeedsMisc1_dr_2500BRCM_X1 16 17672 #define tx_x4_control0_actualSpeedsMisc1_dr_5000BRCM_X4 17 17673 #define tx_x4_control0_actualSpeedsMisc1_dr_6000BRCM_X4 18 17674 #define tx_x4_control0_actualSpeedsMisc1_dr_10GHiGig_X4 19 17675 #define tx_x4_control0_actualSpeedsMisc1_dr_10GBASE_CX4 20 17676 #define tx_x4_control0_actualSpeedsMisc1_dr_12GHiGig_X4 21 17677 #define tx_x4_control0_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 17678 #define tx_x4_control0_actualSpeedsMisc1_dr_13GHiGig_X4 23 17679 #define tx_x4_control0_actualSpeedsMisc1_dr_15GHiGig_X4 24 17680 #define tx_x4_control0_actualSpeedsMisc1_dr_16GHiGig_X4 25 17681 #define tx_x4_control0_actualSpeedsMisc1_dr_5000BRCM_X1 26 17682 #define tx_x4_control0_actualSpeedsMisc1_dr_6363BRCM_X1 27 17683 #define tx_x4_control0_actualSpeedsMisc1_dr_20GHiGig_X4 28 17684 #define tx_x4_control0_actualSpeedsMisc1_dr_21GHiGig_X4 29 17685 #define tx_x4_control0_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 17686 #define tx_x4_control0_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 17687 17688 /**************************************************************************** 17689 * Enums: tx_x4_control0_IndLaneModes 17690 */ 17691 #define tx_x4_control0_IndLaneModes_SWSDR_div2 0 17692 #define tx_x4_control0_IndLaneModes_SWSDR_div1 1 17693 #define tx_x4_control0_IndLaneModes_DWSDR_div2 2 17694 #define tx_x4_control0_IndLaneModes_DWSDR_div1 3 17695 17696 /**************************************************************************** 17697 * Enums: tx_x4_control0_prbsSelect 17698 */ 17699 #define tx_x4_control0_prbsSelect_prbs7 0 17700 #define tx_x4_control0_prbsSelect_prbs15 1 17701 #define tx_x4_control0_prbsSelect_prbs23 2 17702 #define tx_x4_control0_prbsSelect_prbs31 3 17703 17704 /**************************************************************************** 17705 * Enums: tx_x4_control0_vcoDivider 17706 */ 17707 #define tx_x4_control0_vcoDivider_div32 0 17708 #define tx_x4_control0_vcoDivider_div36 1 17709 #define tx_x4_control0_vcoDivider_div40 2 17710 #define tx_x4_control0_vcoDivider_div42 3 17711 #define tx_x4_control0_vcoDivider_div48 4 17712 #define tx_x4_control0_vcoDivider_div50 5 17713 #define tx_x4_control0_vcoDivider_div52 6 17714 #define tx_x4_control0_vcoDivider_div54 7 17715 #define tx_x4_control0_vcoDivider_div60 8 17716 #define tx_x4_control0_vcoDivider_div64 9 17717 #define tx_x4_control0_vcoDivider_div66 10 17718 #define tx_x4_control0_vcoDivider_div68 11 17719 #define tx_x4_control0_vcoDivider_div70 12 17720 #define tx_x4_control0_vcoDivider_div80 13 17721 #define tx_x4_control0_vcoDivider_div92 14 17722 #define tx_x4_control0_vcoDivider_div100 15 17723 17724 /**************************************************************************** 17725 * Enums: tx_x4_control0_refClkSelect 17726 */ 17727 #define tx_x4_control0_refClkSelect_clk_156p25MHz 1 17728 #define tx_x4_control0_refClkSelect_clk_312p5Mhz 2 17729 17730 /**************************************************************************** 17731 * Enums: tx_x4_control0_aerMMDdevTypeSelect 17732 */ 17733 #define tx_x4_control0_aerMMDdevTypeSelect_combo_core 0 17734 #define tx_x4_control0_aerMMDdevTypeSelect_PMA_PMD 1 17735 #define tx_x4_control0_aerMMDdevTypeSelect_PCS 3 17736 #define tx_x4_control0_aerMMDdevTypeSelect_PHY 4 17737 #define tx_x4_control0_aerMMDdevTypeSelect_DTE 5 17738 #define tx_x4_control0_aerMMDdevTypeSelect_CL73_AN 7 17739 17740 /**************************************************************************** 17741 * Enums: tx_x4_control0_aerMMDportSelect 17742 */ 17743 #define tx_x4_control0_aerMMDportSelect_ln0 0 17744 #define tx_x4_control0_aerMMDportSelect_ln1 1 17745 #define tx_x4_control0_aerMMDportSelect_ln2 2 17746 #define tx_x4_control0_aerMMDportSelect_ln3 3 17747 #define tx_x4_control0_aerMMDportSelect_BCST_ln0_1_2_3 511 17748 #define tx_x4_control0_aerMMDportSelect_BCST_ln0_1 512 17749 #define tx_x4_control0_aerMMDportSelect_BCST_ln2_3 513 17750 17751 /**************************************************************************** 17752 * Enums: tx_x4_control0_firmwareModeSelect 17753 */ 17754 #define tx_x4_control0_firmwareModeSelect_DEFAULT 0 17755 #define tx_x4_control0_firmwareModeSelect_SFP_OPT_LR 1 17756 #define tx_x4_control0_firmwareModeSelect_SFP_DAC 2 17757 #define tx_x4_control0_firmwareModeSelect_XLAUI 3 17758 #define tx_x4_control0_firmwareModeSelect_LONG_CH_6G 4 17759 17760 /**************************************************************************** 17761 * Enums: tx_x4_control0_tempIdxSelect 17762 */ 17763 #define tx_x4_control0_tempIdxSelect_LTE__22p9C 15 17764 #define tx_x4_control0_tempIdxSelect_LTE__12p6C 14 17765 #define tx_x4_control0_tempIdxSelect_LTE__3p0C 13 17766 #define tx_x4_control0_tempIdxSelect_LTE_6p7C 12 17767 #define tx_x4_control0_tempIdxSelect_LTE_16p4C 11 17768 #define tx_x4_control0_tempIdxSelect_LTE_26p6C 10 17769 #define tx_x4_control0_tempIdxSelect_LTE_36p3C 9 17770 #define tx_x4_control0_tempIdxSelect_LTE_46p0C 8 17771 #define tx_x4_control0_tempIdxSelect_LTE_56p2C 7 17772 #define tx_x4_control0_tempIdxSelect_LTE_65p9C 6 17773 #define tx_x4_control0_tempIdxSelect_LTE_75p6C 5 17774 #define tx_x4_control0_tempIdxSelect_LTE_85p3C 4 17775 #define tx_x4_control0_tempIdxSelect_LTE_95p5C 3 17776 #define tx_x4_control0_tempIdxSelect_LTE_105p2C 2 17777 #define tx_x4_control0_tempIdxSelect_LTE_114p9C 1 17778 #define tx_x4_control0_tempIdxSelect_LTE_125p1C 0 17779 17780 /**************************************************************************** 17781 * Enums: tx_x4_control0_port_mode 17782 */ 17783 #define tx_x4_control0_port_mode_QUAD_PORT 0 17784 #define tx_x4_control0_port_mode_TRI_1_PORT 1 17785 #define tx_x4_control0_port_mode_TRI_2_PORT 2 17786 #define tx_x4_control0_port_mode_DUAL_PORT 3 17787 #define tx_x4_control0_port_mode_SINGLE_PORT 4 17788 #define tx_x4_control0_port_mode_SINGLE_OCTAL_PORT 5 17789 17790 /**************************************************************************** 17791 * Enums: tx_x4_control0_rev_letter_enum 17792 */ 17793 #define tx_x4_control0_rev_letter_enum_REV_A 0 17794 #define tx_x4_control0_rev_letter_enum_REV_B 1 17795 #define tx_x4_control0_rev_letter_enum_REV_C 2 17796 #define tx_x4_control0_rev_letter_enum_REV_D 3 17797 17798 /**************************************************************************** 17799 * Enums: tx_x4_control0_rev_number_enum 17800 */ 17801 #define tx_x4_control0_rev_number_enum_REV_0 0 17802 #define tx_x4_control0_rev_number_enum_REV_1 1 17803 #define tx_x4_control0_rev_number_enum_REV_2 2 17804 #define tx_x4_control0_rev_number_enum_REV_3 3 17805 #define tx_x4_control0_rev_number_enum_REV_4 4 17806 #define tx_x4_control0_rev_number_enum_REV_5 5 17807 #define tx_x4_control0_rev_number_enum_REV_6 6 17808 #define tx_x4_control0_rev_number_enum_REV_7 7 17809 17810 /**************************************************************************** 17811 * Enums: tx_x4_control0_bonding_enum 17812 */ 17813 #define tx_x4_control0_bonding_enum_WIRE_BOND 0 17814 #define tx_x4_control0_bonding_enum_FLIP_CHIP 1 17815 17816 /**************************************************************************** 17817 * Enums: tx_x4_control0_tech_process 17818 */ 17819 #define tx_x4_control0_tech_process_PROCESS_90NM 0 17820 #define tx_x4_control0_tech_process_PROCESS_65NM 1 17821 #define tx_x4_control0_tech_process_PROCESS_40NM 2 17822 #define tx_x4_control0_tech_process_PROCESS_28NM 3 17823 #define tx_x4_control0_tech_process_PROCESS_16NM 4 17824 17825 /**************************************************************************** 17826 * Enums: tx_x4_control0_model_num 17827 */ 17828 #define tx_x4_control0_model_num_SERDES_CL73 0 17829 #define tx_x4_control0_model_num_XGXS_16G 1 17830 #define tx_x4_control0_model_num_HYPERCORE 2 17831 #define tx_x4_control0_model_num_HYPERLITE 3 17832 #define tx_x4_control0_model_num_PCIE_G2_PIPE 4 17833 #define tx_x4_control0_model_num_SERDES_1p25GBd 5 17834 #define tx_x4_control0_model_num_SATA2 6 17835 #define tx_x4_control0_model_num_QSGMII 7 17836 #define tx_x4_control0_model_num_XGXS10G 8 17837 #define tx_x4_control0_model_num_WARPCORE 9 17838 #define tx_x4_control0_model_num_XFICORE 10 17839 #define tx_x4_control0_model_num_RXFI 11 17840 #define tx_x4_control0_model_num_WARPLITE 12 17841 #define tx_x4_control0_model_num_PENTACORE 13 17842 #define tx_x4_control0_model_num_ESM 14 17843 #define tx_x4_control0_model_num_QUAD_SGMII 15 17844 #define tx_x4_control0_model_num_WARPCORE_3 16 17845 #define tx_x4_control0_model_num_TSC 17 17846 #define tx_x4_control0_model_num_TSC4E 18 17847 #define tx_x4_control0_model_num_TSC12E 19 17848 #define tx_x4_control0_model_num_TSC4F 20 17849 #define tx_x4_control0_model_num_TSC4F_GEN2 21 17850 #define tx_x4_control0_model_num_XGXS_CL73_90NM 29 17851 #define tx_x4_control0_model_num_SERDES_CL73_90NM 30 17852 #define tx_x4_control0_model_num_WARPCORE3 32 17853 #define tx_x4_control0_model_num_WARPCORE4_TSC 33 17854 #define tx_x4_control0_model_num_RXAUI 34 17855 #define tx_x4_control0_model_num_TSCE_GEN3 35 17856 #define tx_x4_control0_model_num_TSC4F_GEN3 36 17857 #define tx_x4_control0_model_num_TSCBH 37 17858 17859 /**************************************************************************** 17860 * Enums: tx_x4_control0_payload 17861 */ 17862 #define tx_x4_control0_payload_REPEAT_2_BYTES 0 17863 #define tx_x4_control0_payload_RAMPING 1 17864 #define tx_x4_control0_payload_CL48_CRPAT 2 17865 #define tx_x4_control0_payload_CL48_CJPAT 3 17866 #define tx_x4_control0_payload_CL36_LONG_CRPAT 4 17867 #define tx_x4_control0_payload_CL36_SHORT_CRPAT 5 17868 17869 /**************************************************************************** 17870 * Enums: tx_x4_control0_sc 17871 */ 17872 #define tx_x4_control0_sc_SPEED_10G_IEEE_KR1 0 17873 #define tx_x4_control0_sc_SPEED_25G_IEEE_KS1_CS1 1 17874 #define tx_x4_control0_sc_SPEED_25G_IEEE_KR1_CR1 2 17875 #define tx_x4_control0_sc_SPEED_40G_IEEE_KR4 3 17876 #define tx_x4_control0_sc_SPEED_40G_IEEE_CR4 4 17877 #define tx_x4_control0_sc_SPEED_50G_IEEE_KR1_CR1 5 17878 #define tx_x4_control0_sc_SPEED_100G_IEEE_KR4 6 17879 #define tx_x4_control0_sc_SPEED_100G_IEEE_CR4 7 17880 #define tx_x4_control0_sc_SPEED_100G_IEEE_KR2_CR2 8 17881 #define tx_x4_control0_sc_SPEED_200G_IEEE_KR4_CR4 9 17882 #define tx_x4_control0_sc_SPEED_400G_IEEE_X8 10 17883 #define tx_x4_control0_sc_SPEED_CL73_IEEE_20GVCO 11 17884 #define tx_x4_control0_sc_SPEED_CL73_IEEE_25GVCO 12 17885 #define tx_x4_control0_sc_SPEED_CL73_IEEE_26GVCO 13 17886 #define tx_x4_control0_sc_SPEED_20G_BRCM_CR1 14 17887 #define tx_x4_control0_sc_SPEED_20G_BRCM_KR1 15 17888 #define tx_x4_control0_sc_SPEED_25G_BRCM_CR1 16 17889 #define tx_x4_control0_sc_SPEED_25G_BRCM_KR1 17 17890 #define tx_x4_control0_sc_SPEED_40G_BRCM_CR2 18 17891 #define tx_x4_control0_sc_SPEED_40G_BRCM_KR2 19 17892 #define tx_x4_control0_sc_SPEED_50G_BRCM_CR2 20 17893 #define tx_x4_control0_sc_SPEED_50G_BRCM_KR2 21 17894 #define tx_x4_control0_sc_SPEED_50G_BRCM_CR4 22 17895 #define tx_x4_control0_sc_SPEED_50G_BRCM_KR4 23 17896 #define tx_x4_control0_sc_SPEED_50G_BRCM_FEC_544_CR2_KR2 24 17897 #define tx_x4_control0_sc_SPEED_RESERVED_19 25 17898 #define tx_x4_control0_sc_SPEED_50G_BRCM_FEC_544_CR1_KR1 26 17899 #define tx_x4_control0_sc_SPEED_50G_BRCM_NO_FEC_CR1_KR1 27 17900 #define tx_x4_control0_sc_SPEED_50G_BRCM_FEC_528_CR1_KR1 28 17901 #define tx_x4_control0_sc_SPEED_400G_BRCM_NO_FEC_KR8_CR8 29 17902 #define tx_x4_control0_sc_SPEED_400G_BRCM_FEC_KR8_CR8 30 17903 #define tx_x4_control0_sc_SPEED_200G_BRCM_NO_FEC_KR4_CR4 31 17904 #define tx_x4_control0_sc_SPEED_200G_BRCM_KR4_CR4 32 17905 #define tx_x4_control0_sc_SPEED_100G_BRCM_KR4_CR4 33 17906 #define tx_x4_control0_sc_SPEED_RESERVED_22 34 17907 #define tx_x4_control0_sc_SPEED_100G_BRCM_FEC_528_KR2_CR2 35 17908 #define tx_x4_control0_sc_SPEED_100G_BRCM_NO_FEC_KR2_CR2 36 17909 #define tx_x4_control0_sc_SPEED_100G_BRCM_NO_FEC_X4 37 17910 17911 /**************************************************************************** 17912 * Enums: tx_x4_control0_t_fifo_modes 17913 */ 17914 #define tx_x4_control0_t_fifo_modes_T_FIFO_INSERT_NO_AM 0 17915 #define tx_x4_control0_t_fifo_modes_T_FIFO_INSERT_4_AM 1 17916 #define tx_x4_control0_t_fifo_modes_T_FIFO_INSERT_20_AM 2 17917 #define tx_x4_control0_t_fifo_modes_T_FIFO_INSERT_2_AM 3 17918 17919 /**************************************************************************** 17920 * Enums: tx_x4_control0_t_enc_modes 17921 */ 17922 #define tx_x4_control0_t_enc_modes_T_ENC_MODE_BYPASS 0 17923 #define tx_x4_control0_t_enc_modes_T_ENC_MODE_CL49 1 17924 #define tx_x4_control0_t_enc_modes_T_ENC_MODE_CL82 2 17925 17926 /**************************************************************************** 17927 * Enums: tx_x4_control0_btmx_mode 17928 */ 17929 #define tx_x4_control0_btmx_mode_BS_BTMX_MODE_1to1 0 17930 #define tx_x4_control0_btmx_mode_BS_BTMX_MODE_2to1 1 17931 #define tx_x4_control0_btmx_mode_BS_BTMX_MODE_5to1 2 17932 17933 /**************************************************************************** 17934 * Enums: tx_x4_control0_t_type_cl82 17935 */ 17936 #define tx_x4_control0_t_type_cl82_T_TYPE_B1 5 17937 #define tx_x4_control0_t_type_cl82_T_TYPE_C 4 17938 #define tx_x4_control0_t_type_cl82_T_TYPE_S 3 17939 #define tx_x4_control0_t_type_cl82_T_TYPE_T 2 17940 #define tx_x4_control0_t_type_cl82_T_TYPE_D 1 17941 #define tx_x4_control0_t_type_cl82_T_TYPE_E 0 17942 17943 /**************************************************************************** 17944 * Enums: tx_x4_control0_txsm_state_cl82 17945 */ 17946 #define tx_x4_control0_txsm_state_cl82_TX_E 4 17947 #define tx_x4_control0_txsm_state_cl82_TX_T 3 17948 #define tx_x4_control0_txsm_state_cl82_TX_D 2 17949 #define tx_x4_control0_txsm_state_cl82_TX_C 1 17950 #define tx_x4_control0_txsm_state_cl82_TX_INIT 0 17951 17952 /**************************************************************************** 17953 * Enums: tx_x4_control0_ltxsm_state_cl82 17954 */ 17955 #define tx_x4_control0_ltxsm_state_cl82_TX_E 16 17956 #define tx_x4_control0_ltxsm_state_cl82_TX_T 8 17957 #define tx_x4_control0_ltxsm_state_cl82_TX_D 4 17958 #define tx_x4_control0_ltxsm_state_cl82_TX_C 2 17959 #define tx_x4_control0_ltxsm_state_cl82_TX_INIT 1 17960 17961 /**************************************************************************** 17962 * Enums: tx_x4_control0_r_type_coded_cl82 17963 */ 17964 #define tx_x4_control0_r_type_coded_cl82_R_TYPE_B1 32 17965 #define tx_x4_control0_r_type_coded_cl82_R_TYPE_C 16 17966 #define tx_x4_control0_r_type_coded_cl82_R_TYPE_S 8 17967 #define tx_x4_control0_r_type_coded_cl82_R_TYPE_T 4 17968 #define tx_x4_control0_r_type_coded_cl82_R_TYPE_D 2 17969 #define tx_x4_control0_r_type_coded_cl82_R_TYPE_E 1 17970 17971 /**************************************************************************** 17972 * Enums: tx_x4_control0_rxsm_state_cl82 17973 */ 17974 #define tx_x4_control0_rxsm_state_cl82_RX_E 16 17975 #define tx_x4_control0_rxsm_state_cl82_RX_T 8 17976 #define tx_x4_control0_rxsm_state_cl82_RX_D 4 17977 #define tx_x4_control0_rxsm_state_cl82_RX_C 2 17978 #define tx_x4_control0_rxsm_state_cl82_RX_INIT 1 17979 17980 /**************************************************************************** 17981 * Enums: tx_x4_control0_deskew_state 17982 */ 17983 #define tx_x4_control0_deskew_state_ALIGN_ACQUIRED 2 17984 #define tx_x4_control0_deskew_state_LOSS_OF_ALIGNMENT 1 17985 17986 /**************************************************************************** 17987 * Enums: tx_x4_control0_os_mode_enum 17988 */ 17989 #define tx_x4_control0_os_mode_enum_OS_MODE_1 0 17990 #define tx_x4_control0_os_mode_enum_OS_MODE_2 1 17991 #define tx_x4_control0_os_mode_enum_OS_MODE_4 2 17992 #define tx_x4_control0_os_mode_enum_OS_MODE_16p5 8 17993 #define tx_x4_control0_os_mode_enum_OS_MODE_20p625 12 17994 17995 /**************************************************************************** 17996 * Enums: tx_x4_control0_scr_modes 17997 */ 17998 #define tx_x4_control0_scr_modes_T_SCR_MODE_BYPASS 0 17999 #define tx_x4_control0_scr_modes_T_SCR_MODE_CL49 1 18000 #define tx_x4_control0_scr_modes_T_SCR_MODE_40G_2_LANE 2 18001 #define tx_x4_control0_scr_modes_T_SCR_MODE_100G 3 18002 #define tx_x4_control0_scr_modes_T_SCR_MODE_20G 4 18003 #define tx_x4_control0_scr_modes_T_SCR_MODE_40G_4_LANE 5 18004 18005 /**************************************************************************** 18006 * Enums: tx_x4_control0_descr_modes 18007 */ 18008 #define tx_x4_control0_descr_modes_R_DESCR_MODE_BYPASS 0 18009 #define tx_x4_control0_descr_modes_R_DESCR_MODE_CL49 1 18010 #define tx_x4_control0_descr_modes_R_DESCR_MODE_CL82 2 18011 18012 /**************************************************************************** 18013 * Enums: tx_x4_control0_r_dec_tl_mode 18014 */ 18015 #define tx_x4_control0_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 18016 #define tx_x4_control0_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 18017 #define tx_x4_control0_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 18018 18019 /**************************************************************************** 18020 * Enums: tx_x4_control0_r_dec_fsm_mode 18021 */ 18022 #define tx_x4_control0_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 18023 #define tx_x4_control0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 18024 #define tx_x4_control0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 18025 18026 /**************************************************************************** 18027 * Enums: tx_x4_control0_r_deskew_mode 18028 */ 18029 #define tx_x4_control0_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 18030 #define tx_x4_control0_r_deskew_mode_R_DESKEW_MODE_20G 1 18031 #define tx_x4_control0_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 18032 #define tx_x4_control0_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 18033 #define tx_x4_control0_r_deskew_mode_R_DESKEW_MODE_100G 4 18034 #define tx_x4_control0_r_deskew_mode_R_DESKEW_MODE_CL49 5 18035 #define tx_x4_control0_r_deskew_mode_R_DESKEW_MODE_CL91_QUAD 6 18036 #define tx_x4_control0_r_deskew_mode_R_DESKEW_MODE_CL91_SINGLE_BRCM 7 18037 #define tx_x4_control0_r_deskew_mode_R_DESKEW_MODE_CL91_DUAL_BRCM 8 18038 #define tx_x4_control0_r_deskew_mode_R_DESKEW_MODE_CL91_FC 9 18039 18040 /**************************************************************************** 18041 * Enums: tx_x4_control0_bs_dist_modes 18042 */ 18043 #define tx_x4_control0_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 18044 #define tx_x4_control0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 18045 #define tx_x4_control0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 18046 #define tx_x4_control0_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 18047 18048 /**************************************************************************** 18049 * Enums: tx_x4_control0_cl49_t_type 18050 */ 18051 #define tx_x4_control0_cl49_t_type_BAD_T_TYPE 15 18052 #define tx_x4_control0_cl49_t_type_T_TYPE_B0 11 18053 #define tx_x4_control0_cl49_t_type_T_TYPE_OB 10 18054 #define tx_x4_control0_cl49_t_type_T_TYPE_B1 9 18055 #define tx_x4_control0_cl49_t_type_T_TYPE_DB 8 18056 #define tx_x4_control0_cl49_t_type_T_TYPE_FC 7 18057 #define tx_x4_control0_cl49_t_type_T_TYPE_TB 6 18058 #define tx_x4_control0_cl49_t_type_T_TYPE_LI 5 18059 #define tx_x4_control0_cl49_t_type_T_TYPE_C 4 18060 #define tx_x4_control0_cl49_t_type_T_TYPE_S 3 18061 #define tx_x4_control0_cl49_t_type_T_TYPE_T 2 18062 #define tx_x4_control0_cl49_t_type_T_TYPE_D 1 18063 #define tx_x4_control0_cl49_t_type_T_TYPE_E 0 18064 18065 /**************************************************************************** 18066 * Enums: tx_x4_control0_cl49_txsm_states 18067 */ 18068 #define tx_x4_control0_cl49_txsm_states_TX_LI 5 18069 #define tx_x4_control0_cl49_txsm_states_TX_E 4 18070 #define tx_x4_control0_cl49_txsm_states_TX_T 3 18071 #define tx_x4_control0_cl49_txsm_states_TX_D 2 18072 #define tx_x4_control0_cl49_txsm_states_TX_C 1 18073 #define tx_x4_control0_cl49_txsm_states_TX_INIT 0 18074 18075 /**************************************************************************** 18076 * Enums: tx_x4_control0_cl49_ltxsm_states 18077 */ 18078 #define tx_x4_control0_cl49_ltxsm_states_TX_LI 32 18079 #define tx_x4_control0_cl49_ltxsm_states_TX_E 16 18080 #define tx_x4_control0_cl49_ltxsm_states_TX_T 8 18081 #define tx_x4_control0_cl49_ltxsm_states_TX_D 4 18082 #define tx_x4_control0_cl49_ltxsm_states_TX_C 2 18083 #define tx_x4_control0_cl49_ltxsm_states_TX_INIT 1 18084 18085 /**************************************************************************** 18086 * Enums: tx_x4_control0_burst_error_mode 18087 */ 18088 #define tx_x4_control0_burst_error_mode_BURST_ERROR_11_BITS 0 18089 #define tx_x4_control0_burst_error_mode_BURST_ERROR_16_BITS 1 18090 #define tx_x4_control0_burst_error_mode_BURST_ERROR_17_BITS 2 18091 #define tx_x4_control0_burst_error_mode_BURST_ERROR_18_BITS 3 18092 #define tx_x4_control0_burst_error_mode_BURST_ERROR_19_BITS 4 18093 #define tx_x4_control0_burst_error_mode_BURST_ERROR_20_BITS 5 18094 #define tx_x4_control0_burst_error_mode_BURST_ERROR_21_BITS 6 18095 #define tx_x4_control0_burst_error_mode_BURST_ERROR_22_BITS 7 18096 #define tx_x4_control0_burst_error_mode_BURST_ERROR_23_BITS 8 18097 #define tx_x4_control0_burst_error_mode_BURST_ERROR_24_BITS 9 18098 #define tx_x4_control0_burst_error_mode_BURST_ERROR_25_BITS 10 18099 #define tx_x4_control0_burst_error_mode_BURST_ERROR_26_BITS 11 18100 #define tx_x4_control0_burst_error_mode_BURST_ERROR_27_BITS 12 18101 #define tx_x4_control0_burst_error_mode_BURST_ERROR_28_BITS 13 18102 #define tx_x4_control0_burst_error_mode_BURST_ERROR_29_BITS 14 18103 #define tx_x4_control0_burst_error_mode_BURST_ERROR_30_BITS 15 18104 #define tx_x4_control0_burst_error_mode_BURST_ERROR_31_BITS 16 18105 #define tx_x4_control0_burst_error_mode_BURST_ERROR_32_BITS 17 18106 #define tx_x4_control0_burst_error_mode_BURST_ERROR_33_BITS 18 18107 #define tx_x4_control0_burst_error_mode_BURST_ERROR_34_BITS 19 18108 #define tx_x4_control0_burst_error_mode_BURST_ERROR_35_BITS 20 18109 #define tx_x4_control0_burst_error_mode_BURST_ERROR_36_BITS 21 18110 #define tx_x4_control0_burst_error_mode_BURST_ERROR_37_BITS 22 18111 #define tx_x4_control0_burst_error_mode_BURST_ERROR_38_BITS 23 18112 #define tx_x4_control0_burst_error_mode_BURST_ERROR_39_BITS 24 18113 #define tx_x4_control0_burst_error_mode_BURST_ERROR_40_BITS 25 18114 #define tx_x4_control0_burst_error_mode_BURST_ERROR_41_BITS 26 18115 18116 /**************************************************************************** 18117 * Enums: tx_x4_control0_bermon_state 18118 */ 18119 #define tx_x4_control0_bermon_state_HI_BER 4 18120 #define tx_x4_control0_bermon_state_GOOD_BER 3 18121 #define tx_x4_control0_bermon_state_BER_TEST_SH 2 18122 #define tx_x4_control0_bermon_state_START_TIMER 1 18123 #define tx_x4_control0_bermon_state_BER_MT_INIT 0 18124 18125 /**************************************************************************** 18126 * Enums: tx_x4_control0_rxsm_state_cl49 18127 */ 18128 #define tx_x4_control0_rxsm_state_cl49_RX_LI 32 18129 #define tx_x4_control0_rxsm_state_cl49_RX_E 16 18130 #define tx_x4_control0_rxsm_state_cl49_RX_T 8 18131 #define tx_x4_control0_rxsm_state_cl49_RX_D 4 18132 #define tx_x4_control0_rxsm_state_cl49_RX_C 2 18133 #define tx_x4_control0_rxsm_state_cl49_RX_INIT 1 18134 18135 /**************************************************************************** 18136 * Enums: tx_x4_control0_r_type 18137 */ 18138 #define tx_x4_control0_r_type_BAD_R_TYPE 15 18139 #define tx_x4_control0_r_type_R_TYPE_B0 11 18140 #define tx_x4_control0_r_type_R_TYPE_OB 10 18141 #define tx_x4_control0_r_type_R_TYPE_B1 9 18142 #define tx_x4_control0_r_type_R_TYPE_DB 8 18143 #define tx_x4_control0_r_type_R_TYPE_FC 7 18144 #define tx_x4_control0_r_type_R_TYPE_TB 6 18145 #define tx_x4_control0_r_type_R_TYPE_LI 5 18146 #define tx_x4_control0_r_type_R_TYPE_C 4 18147 #define tx_x4_control0_r_type_R_TYPE_S 3 18148 #define tx_x4_control0_r_type_R_TYPE_T 2 18149 #define tx_x4_control0_r_type_R_TYPE_D 1 18150 #define tx_x4_control0_r_type_R_TYPE_E 0 18151 18152 /**************************************************************************** 18153 * Enums: tx_x4_control0_am_lock_state 18154 */ 18155 #define tx_x4_control0_am_lock_state_INVALID_AM 512 18156 #define tx_x4_control0_am_lock_state_GOOD_AM 256 18157 #define tx_x4_control0_am_lock_state_COMP_AM 128 18158 #define tx_x4_control0_am_lock_state_TIMER_2 64 18159 #define tx_x4_control0_am_lock_state_AM_2_GOOD 32 18160 #define tx_x4_control0_am_lock_state_COMP_2ND 16 18161 #define tx_x4_control0_am_lock_state_TIMER_1 8 18162 #define tx_x4_control0_am_lock_state_FIND_1ST 4 18163 #define tx_x4_control0_am_lock_state_AM_RESET_CNT 2 18164 #define tx_x4_control0_am_lock_state_AM_LOCK_INIT 1 18165 18166 /**************************************************************************** 18167 * Enums: tx_x4_control0_msg_selector 18168 */ 18169 #define tx_x4_control0_msg_selector_RESERVED 0 18170 #define tx_x4_control0_msg_selector_VALUE_802p3 1 18171 #define tx_x4_control0_msg_selector_VALUE_802p9 2 18172 #define tx_x4_control0_msg_selector_VALUE_802p5 3 18173 #define tx_x4_control0_msg_selector_VALUE_1394 4 18174 18175 /**************************************************************************** 18176 * Enums: tx_x4_control0_synce_enum_stage1 18177 */ 18178 #define tx_x4_control0_synce_enum_stage1_SYNCE_NO_DIV 0 18179 #define tx_x4_control0_synce_enum_stage1_SYNCE_DIV_7 1 18180 #define tx_x4_control0_synce_enum_stage1_SYNCE_DIV_11 2 18181 18182 /**************************************************************************** 18183 * Enums: tx_x4_control0_synce_enum_stage0 18184 */ 18185 #define tx_x4_control0_synce_enum_stage0_SYNCE_NO_DIV 0 18186 #define tx_x4_control0_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 18187 #define tx_x4_control0_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 18188 18189 /**************************************************************************** 18190 * Enums: tx_x4_control0_cl91_sync_state 18191 */ 18192 #define tx_x4_control0_cl91_sync_state_FIND_1ST 0 18193 #define tx_x4_control0_cl91_sync_state_COUNT_NEXT 1 18194 #define tx_x4_control0_cl91_sync_state_COMP_2ND 2 18195 #define tx_x4_control0_cl91_sync_state_TWO_GOOD 3 18196 18197 /**************************************************************************** 18198 * Enums: tx_x4_control0_RS_FEC_sync_state 18199 */ 18200 #define tx_x4_control0_RS_FEC_sync_state_LOCK_INIT 0 18201 #define tx_x4_control0_RS_FEC_sync_state_FIND_1ST 1 18202 #define tx_x4_control0_RS_FEC_sync_state_COUNT_NEXT 2 18203 #define tx_x4_control0_RS_FEC_sync_state_COMP_2ND 3 18204 #define tx_x4_control0_RS_FEC_sync_state_TWO_GOOD 4 18205 18206 /**************************************************************************** 18207 * Enums: tx_x4_control0_cl91_algn_state 18208 */ 18209 #define tx_x4_control0_cl91_algn_state_LOSS_OF_ALIGNMENT 0 18210 #define tx_x4_control0_cl91_algn_state_DESKEW 1 18211 #define tx_x4_control0_cl91_algn_state_DESKEW_FAIL 2 18212 #define tx_x4_control0_cl91_algn_state_ALIGN_ACQUIRED 3 18213 #define tx_x4_control0_cl91_algn_state_CW_GOOD 4 18214 #define tx_x4_control0_cl91_algn_state_CW_BAD 5 18215 #define tx_x4_control0_cl91_algn_state_THREE_BAD 6 18216 18217 /**************************************************************************** 18218 * Enums: tx_x4_control0_RS_FEC_algn_state 18219 */ 18220 #define tx_x4_control0_RS_FEC_algn_state_LOSS_OF_ALIGNMENT 0 18221 #define tx_x4_control0_RS_FEC_algn_state_DESKEW 1 18222 #define tx_x4_control0_RS_FEC_algn_state_DESKEW_FAIL 2 18223 #define tx_x4_control0_RS_FEC_algn_state_ALIGN_ACQUIRED 3 18224 #define tx_x4_control0_RS_FEC_algn_state_CW_GOOD 4 18225 #define tx_x4_control0_RS_FEC_algn_state_CW_BAD 5 18226 #define tx_x4_control0_RS_FEC_algn_state_THREE_BAD 6 18227 18228 /**************************************************************************** 18229 * Enums: tx_x4_control0_fec_sel_override 18230 */ 18231 #define tx_x4_control0_fec_sel_override_NO_OVERRIDE 0 18232 #define tx_x4_control0_fec_sel_override_NO_FEC 1 18233 #define tx_x4_control0_fec_sel_override_FEC_CL74 2 18234 #define tx_x4_control0_fec_sel_override_FEC_CL91 3 18235 18236 /**************************************************************************** 18237 * Enums: tx_x4_control0_cl91_blksync_mode 18238 */ 18239 #define tx_x4_control0_cl91_blksync_mode_R_BLKSYNC_NO_CL91_FEC 0 18240 #define tx_x4_control0_cl91_blksync_mode_R_BLKSYNC_CL91_QUAD_LANE_FEC 1 18241 #define tx_x4_control0_cl91_blksync_mode_R_BLKSYNC_CL91_DUAL_LANE_FEC 2 18242 #define tx_x4_control0_cl91_blksync_mode_R_BLKSYNC_CL91_SINGLE_LANE_FEC 3 18243 #define tx_x4_control0_cl91_blksync_mode_R_BLKSYNC_CL91_FC_FEC 4 18244 18245 /**************************************************************************** 18246 * Enums: tx_x4_control0_r_merge_mode 18247 */ 18248 #define tx_x4_control0_r_merge_mode_R_MERGE_MODE_BYPASS 0 18249 #define tx_x4_control0_r_merge_mode_R_MERGE_MODE_CL91_FC 1 18250 #define tx_x4_control0_r_merge_mode_R_MERGE_MODE_CL91_SINGLE_LANE 2 18251 #define tx_x4_control0_r_merge_mode_R_MERGE_MODE_CL91_DUAL_LANE 3 18252 #define tx_x4_control0_r_merge_mode_R_MERGE_MODE_CL91_QUAD_LANE 4 18253 18254 /**************************************************************************** 18255 * Enums: tx_x4_control0_r_tc_mode 18256 */ 18257 #define tx_x4_control0_r_tc_mode_R_TC_MODE_SINGLE 0 18258 #define tx_x4_control0_r_tc_mode_R_TC_MODE_DUAL 1 18259 #define tx_x4_control0_r_tc_mode_R_TC_MODE_QUAD 2 18260 18261 /**************************************************************************** 18262 * Enums: tx_x4_control0_r_tc_out_mode 18263 */ 18264 #define tx_x4_control0_r_tc_out_mode_R_TC_OUT_MODE_SINGLE 0 18265 #define tx_x4_control0_r_tc_out_mode_R_TC_OUT_MODE_DUAL 1 18266 #define tx_x4_control0_r_tc_out_mode_R_TC_OUT_MODE_QUAD 2 18267 18268 /**************************************************************************** 18269 * Enums: tx_x4_control0_cl91_fec_mode 18270 */ 18271 #define tx_x4_control0_cl91_fec_mode_NO_CL91_FEC 0 18272 #define tx_x4_control0_cl91_fec_mode_CL91_SINGLE_LANE_FC 1 18273 #define tx_x4_control0_cl91_fec_mode_CL91_SINGLE_LANE_BRCM_PROP 2 18274 #define tx_x4_control0_cl91_fec_mode_CL91_DUAL_LANE_BRCM_PROP 3 18275 #define tx_x4_control0_cl91_fec_mode_CL91_QUAD_LANE 4 18276 #define tx_x4_control0_cl91_fec_mode_IEEE_25G_CL91_SINGLE_LANE 5 18277 18278 /**************************************************************************** 18279 * Enums: tx_x4_control0_RS_FEC_fec_mode 18280 */ 18281 #define tx_x4_control0_RS_FEC_fec_mode_NO_RS_FEC_FEC 0 18282 #define tx_x4_control0_RS_FEC_fec_mode_N_A 1 18283 #define tx_x4_control0_RS_FEC_fec_mode_RS_FEC_SINGLE_LANE_BRCM_PROP 2 18284 #define tx_x4_control0_RS_FEC_fec_mode_RS_FEC_DUAL_LANE_BRCM_PROP 3 18285 #define tx_x4_control0_RS_FEC_fec_mode_RS_FEC_QUAD_LANE 4 18286 #define tx_x4_control0_RS_FEC_fec_mode_IEEE_25G_RS_FEC_SINGLE_LANE 5 18287 18288 /**************************************************************************** 18289 * Enums: tx_x4_control0_am_spacing_mul 18290 */ 18291 #define tx_x4_control0_am_spacing_mul_AM_SPACING_MUL_2 0 18292 #define tx_x4_control0_am_spacing_mul_AM_SPACING_MUL_4 1 18293 #define tx_x4_control0_am_spacing_mul_AM_SPACING_MUL_5 2 18294 #define tx_x4_control0_am_spacing_mul_AM_SPACING_MUL_20 3 18295 18296 /**************************************************************************** 18297 * Enums: tx_x4_status0_cl36TxEEEStates_l 18298 */ 18299 #define tx_x4_status0_cl36TxEEEStates_l_TX_REFRESH 8 18300 #define tx_x4_status0_cl36TxEEEStates_l_TX_QUIET 4 18301 #define tx_x4_status0_cl36TxEEEStates_l_TX_SLEEP 2 18302 #define tx_x4_status0_cl36TxEEEStates_l_TX_ACTIVE 1 18303 18304 /**************************************************************************** 18305 * Enums: tx_x4_status0_cl36TxEEEStates_c 18306 */ 18307 #define tx_x4_status0_cl36TxEEEStates_c_TX_REFRESH 3 18308 #define tx_x4_status0_cl36TxEEEStates_c_TX_QUIET 2 18309 #define tx_x4_status0_cl36TxEEEStates_c_TX_SLEEP 1 18310 #define tx_x4_status0_cl36TxEEEStates_c_TX_ACTIVE 0 18311 18312 /**************************************************************************** 18313 * Enums: tx_x4_status0_cl49TxEEEStates_l 18314 */ 18315 #define tx_x4_status0_cl49TxEEEStates_l_SCR_RESET_2 64 18316 #define tx_x4_status0_cl49TxEEEStates_l_SCR_RESET_1 32 18317 #define tx_x4_status0_cl49TxEEEStates_l_TX_WAKE 16 18318 #define tx_x4_status0_cl49TxEEEStates_l_TX_REFRESH 8 18319 #define tx_x4_status0_cl49TxEEEStates_l_TX_QUIET 4 18320 #define tx_x4_status0_cl49TxEEEStates_l_TX_SLEEP 2 18321 #define tx_x4_status0_cl49TxEEEStates_l_TX_ACTIVE 1 18322 18323 /**************************************************************************** 18324 * Enums: tx_x4_status0_fec_req_enum 18325 */ 18326 #define tx_x4_status0_fec_req_enum_FEC_not_supported 0 18327 #define tx_x4_status0_fec_req_enum_FEC_supported_but_not_requested 1 18328 #define tx_x4_status0_fec_req_enum_invalid_setting 2 18329 #define tx_x4_status0_fec_req_enum_FEC_supported_and_requested 3 18330 18331 /**************************************************************************** 18332 * Enums: tx_x4_status0_cl73_pause_enum 18333 */ 18334 #define tx_x4_status0_cl73_pause_enum_No_PAUSE_ability 0 18335 #define tx_x4_status0_cl73_pause_enum_Asymmetric_toward_link_partner_PAUSE_ability 2 18336 #define tx_x4_status0_cl73_pause_enum_Symmetric_PAUSE_ability 1 18337 #define tx_x4_status0_cl73_pause_enum_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 18338 18339 /**************************************************************************** 18340 * Enums: tx_x4_status0_cl49TxEEEStates_c 18341 */ 18342 #define tx_x4_status0_cl49TxEEEStates_c_SCR_RESET_2 6 18343 #define tx_x4_status0_cl49TxEEEStates_c_SCR_RESET_1 5 18344 #define tx_x4_status0_cl49TxEEEStates_c_TX_WAKE 4 18345 #define tx_x4_status0_cl49TxEEEStates_c_TX_REFRESH 3 18346 #define tx_x4_status0_cl49TxEEEStates_c_TX_QUIET 2 18347 #define tx_x4_status0_cl49TxEEEStates_c_TX_SLEEP 1 18348 #define tx_x4_status0_cl49TxEEEStates_c_TX_ACTIVE 0 18349 18350 /**************************************************************************** 18351 * Enums: tx_x4_status0_cl36RxEEEStates_l 18352 */ 18353 #define tx_x4_status0_cl36RxEEEStates_l_RX_LINK_FAIL 32 18354 #define tx_x4_status0_cl36RxEEEStates_l_RX_WTF 16 18355 #define tx_x4_status0_cl36RxEEEStates_l_RX_WAKE 8 18356 #define tx_x4_status0_cl36RxEEEStates_l_RX_QUIET 4 18357 #define tx_x4_status0_cl36RxEEEStates_l_RX_SLEEP 2 18358 #define tx_x4_status0_cl36RxEEEStates_l_RX_ACTIVE 1 18359 18360 /**************************************************************************** 18361 * Enums: tx_x4_status0_cl36RxEEEStates_c 18362 */ 18363 #define tx_x4_status0_cl36RxEEEStates_c_RX_LINK_FAIL 5 18364 #define tx_x4_status0_cl36RxEEEStates_c_RX_WTF 4 18365 #define tx_x4_status0_cl36RxEEEStates_c_RX_WAKE 3 18366 #define tx_x4_status0_cl36RxEEEStates_c_RX_QUIET 2 18367 #define tx_x4_status0_cl36RxEEEStates_c_RX_SLEEP 1 18368 #define tx_x4_status0_cl36RxEEEStates_c_RX_ACTIVE 0 18369 18370 /**************************************************************************** 18371 * Enums: tx_x4_status0_cl49RxEEEStates_l 18372 */ 18373 #define tx_x4_status0_cl49RxEEEStates_l_RX_LINK_FAIL 32 18374 #define tx_x4_status0_cl49RxEEEStates_l_RX_WTF 16 18375 #define tx_x4_status0_cl49RxEEEStates_l_RX_WAKE 8 18376 #define tx_x4_status0_cl49RxEEEStates_l_RX_QUIET 4 18377 #define tx_x4_status0_cl49RxEEEStates_l_RX_SLEEP 2 18378 #define tx_x4_status0_cl49RxEEEStates_l_RX_ACTIVE 1 18379 18380 /**************************************************************************** 18381 * Enums: tx_x4_status0_cl49RxEEEStates_c 18382 */ 18383 #define tx_x4_status0_cl49RxEEEStates_c_RX_LINK_FAIL 5 18384 #define tx_x4_status0_cl49RxEEEStates_c_RX_WTF 4 18385 #define tx_x4_status0_cl49RxEEEStates_c_RX_WAKE 3 18386 #define tx_x4_status0_cl49RxEEEStates_c_RX_QUIET 2 18387 #define tx_x4_status0_cl49RxEEEStates_c_RX_SLEEP 1 18388 #define tx_x4_status0_cl49RxEEEStates_c_RX_ACTIVE 0 18389 18390 /**************************************************************************** 18391 * Enums: tx_x4_status0_cl48TxEEEStates_l 18392 */ 18393 #define tx_x4_status0_cl48TxEEEStates_l_TX_REFRESH 8 18394 #define tx_x4_status0_cl48TxEEEStates_l_TX_QUIET 4 18395 #define tx_x4_status0_cl48TxEEEStates_l_TX_SLEEP 2 18396 #define tx_x4_status0_cl48TxEEEStates_l_TX_ACTIVE 1 18397 18398 /**************************************************************************** 18399 * Enums: tx_x4_status0_cl48TxEEEStates_c 18400 */ 18401 #define tx_x4_status0_cl48TxEEEStates_c_TX_REFRESH 3 18402 #define tx_x4_status0_cl48TxEEEStates_c_TX_QUIET 2 18403 #define tx_x4_status0_cl48TxEEEStates_c_TX_SLEEP 1 18404 #define tx_x4_status0_cl48TxEEEStates_c_TX_ACTIVE 0 18405 18406 /**************************************************************************** 18407 * Enums: tx_x4_status0_cl48RxEEEStates_l 18408 */ 18409 #define tx_x4_status0_cl48RxEEEStates_l_RX_LINK_FAIL 32 18410 #define tx_x4_status0_cl48RxEEEStates_l_RX_WAKE 16 18411 #define tx_x4_status0_cl48RxEEEStates_l_RX_QUIET 8 18412 #define tx_x4_status0_cl48RxEEEStates_l_RX_DEACT 4 18413 #define tx_x4_status0_cl48RxEEEStates_l_RX_SLEEP 2 18414 #define tx_x4_status0_cl48RxEEEStates_l_RX_ACTIVE 1 18415 18416 /**************************************************************************** 18417 * Enums: tx_x4_status0_cl48RxEEEStates_c 18418 */ 18419 #define tx_x4_status0_cl48RxEEEStates_c_RX_LINK_FAIL 5 18420 #define tx_x4_status0_cl48RxEEEStates_c_RX_WAKE 4 18421 #define tx_x4_status0_cl48RxEEEStates_c_RX_QUIET 3 18422 #define tx_x4_status0_cl48RxEEEStates_c_RX_DEACT 2 18423 #define tx_x4_status0_cl48RxEEEStates_c_RX_SLEEP 1 18424 #define tx_x4_status0_cl48RxEEEStates_c_RX_ACTIVE 0 18425 18426 /**************************************************************************** 18427 * Enums: tx_x4_status0_IQP_Options 18428 */ 18429 #define tx_x4_status0_IQP_Options_i50uA 0 18430 #define tx_x4_status0_IQP_Options_i100uA 1 18431 #define tx_x4_status0_IQP_Options_i150uA 2 18432 #define tx_x4_status0_IQP_Options_i200uA 3 18433 #define tx_x4_status0_IQP_Options_i250uA 4 18434 #define tx_x4_status0_IQP_Options_i300uA 5 18435 #define tx_x4_status0_IQP_Options_i350uA 6 18436 #define tx_x4_status0_IQP_Options_i400uA 7 18437 #define tx_x4_status0_IQP_Options_i450uA 8 18438 #define tx_x4_status0_IQP_Options_i500uA 9 18439 #define tx_x4_status0_IQP_Options_i550uA 10 18440 #define tx_x4_status0_IQP_Options_i600uA 11 18441 #define tx_x4_status0_IQP_Options_i650uA 12 18442 #define tx_x4_status0_IQP_Options_i700uA 13 18443 #define tx_x4_status0_IQP_Options_i750uA 14 18444 #define tx_x4_status0_IQP_Options_i800uA 15 18445 18446 /**************************************************************************** 18447 * Enums: tx_x4_status0_IDriver_Options 18448 */ 18449 #define tx_x4_status0_IDriver_Options_v680mV 0 18450 #define tx_x4_status0_IDriver_Options_v730mV 1 18451 #define tx_x4_status0_IDriver_Options_v780mV 2 18452 #define tx_x4_status0_IDriver_Options_v830mV 3 18453 #define tx_x4_status0_IDriver_Options_v880mV 4 18454 #define tx_x4_status0_IDriver_Options_v930mV 5 18455 #define tx_x4_status0_IDriver_Options_v980mV 6 18456 #define tx_x4_status0_IDriver_Options_v1010mV 7 18457 #define tx_x4_status0_IDriver_Options_v1040mV 8 18458 #define tx_x4_status0_IDriver_Options_v1060mV 9 18459 #define tx_x4_status0_IDriver_Options_v1070mV 10 18460 #define tx_x4_status0_IDriver_Options_v1080mV 11 18461 #define tx_x4_status0_IDriver_Options_v1085mV 12 18462 #define tx_x4_status0_IDriver_Options_v1090mV 13 18463 #define tx_x4_status0_IDriver_Options_v1095mV 14 18464 #define tx_x4_status0_IDriver_Options_v1100mV 15 18465 18466 /**************************************************************************** 18467 * Enums: tx_x4_status0_operationModes 18468 */ 18469 #define tx_x4_status0_operationModes_XGXS 0 18470 #define tx_x4_status0_operationModes_XGXG_nCC 1 18471 #define tx_x4_status0_operationModes_Indlane_OS8 4 18472 #define tx_x4_status0_operationModes_IndLane_OS5 5 18473 #define tx_x4_status0_operationModes_PCI 7 18474 #define tx_x4_status0_operationModes_XGXS_nLQ 8 18475 #define tx_x4_status0_operationModes_XGXS_nLQnCC 9 18476 #define tx_x4_status0_operationModes_PBypass 10 18477 #define tx_x4_status0_operationModes_PBypass_nDSK 11 18478 #define tx_x4_status0_operationModes_ComboCoreMode 12 18479 #define tx_x4_status0_operationModes_Clocks_off 15 18480 18481 /**************************************************************************** 18482 * Enums: tx_x4_status0_actualSpeeds 18483 */ 18484 #define tx_x4_status0_actualSpeeds_dr_10M 0 18485 #define tx_x4_status0_actualSpeeds_dr_100M 1 18486 #define tx_x4_status0_actualSpeeds_dr_1G 2 18487 #define tx_x4_status0_actualSpeeds_dr_2p5G 3 18488 #define tx_x4_status0_actualSpeeds_dr_5G_X4 4 18489 #define tx_x4_status0_actualSpeeds_dr_6G_X4 5 18490 #define tx_x4_status0_actualSpeeds_dr_10G_HiG 6 18491 #define tx_x4_status0_actualSpeeds_dr_10G_CX4 7 18492 #define tx_x4_status0_actualSpeeds_dr_12G_HiG 8 18493 #define tx_x4_status0_actualSpeeds_dr_12p5G_X4 9 18494 #define tx_x4_status0_actualSpeeds_dr_13G_X4 10 18495 #define tx_x4_status0_actualSpeeds_dr_15G_X4 11 18496 #define tx_x4_status0_actualSpeeds_dr_16G_X4 12 18497 #define tx_x4_status0_actualSpeeds_dr_1G_KX 13 18498 #define tx_x4_status0_actualSpeeds_dr_10G_KX4 14 18499 #define tx_x4_status0_actualSpeeds_dr_10G_KR 15 18500 #define tx_x4_status0_actualSpeeds_dr_5G 16 18501 #define tx_x4_status0_actualSpeeds_dr_6p4G 17 18502 #define tx_x4_status0_actualSpeeds_dr_20G_X4 18 18503 #define tx_x4_status0_actualSpeeds_dr_21G_X4 19 18504 #define tx_x4_status0_actualSpeeds_dr_25G_X4 20 18505 #define tx_x4_status0_actualSpeeds_dr_10G_HiG_DXGXS 21 18506 #define tx_x4_status0_actualSpeeds_dr_10G_DXGXS 22 18507 #define tx_x4_status0_actualSpeeds_dr_10p5G_HiG_DXGXS 23 18508 #define tx_x4_status0_actualSpeeds_dr_10p5G_DXGXS 24 18509 #define tx_x4_status0_actualSpeeds_dr_12p773G_HiG_DXGXS 25 18510 #define tx_x4_status0_actualSpeeds_dr_12p773G_DXGXS 26 18511 #define tx_x4_status0_actualSpeeds_dr_10G_XFI 27 18512 #define tx_x4_status0_actualSpeeds_dr_40G 28 18513 #define tx_x4_status0_actualSpeeds_dr_20G_HiG_DXGXS 29 18514 #define tx_x4_status0_actualSpeeds_dr_20G_DXGXS 30 18515 #define tx_x4_status0_actualSpeeds_dr_10G_SFI 31 18516 #define tx_x4_status0_actualSpeeds_dr_31p5G 32 18517 #define tx_x4_status0_actualSpeeds_dr_32p7G 33 18518 #define tx_x4_status0_actualSpeeds_dr_20G_SCR 34 18519 #define tx_x4_status0_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 18520 #define tx_x4_status0_actualSpeeds_dr_10G_DXGXS_SCR 36 18521 #define tx_x4_status0_actualSpeeds_dr_12G_R2 37 18522 #define tx_x4_status0_actualSpeeds_dr_10G_X2 38 18523 #define tx_x4_status0_actualSpeeds_dr_40G_KR4 39 18524 #define tx_x4_status0_actualSpeeds_dr_40G_CR4 40 18525 #define tx_x4_status0_actualSpeeds_dr_100G_CR10 41 18526 #define tx_x4_status0_actualSpeeds_dr_15p75G_DXGXS 44 18527 #define tx_x4_status0_actualSpeeds_dr_20G_KR2 57 18528 #define tx_x4_status0_actualSpeeds_dr_20G_CR2 58 18529 18530 /**************************************************************************** 18531 * Enums: tx_x4_status0_actualSpeedsMisc1 18532 */ 18533 #define tx_x4_status0_actualSpeedsMisc1_dr_2500BRCM_X1 16 18534 #define tx_x4_status0_actualSpeedsMisc1_dr_5000BRCM_X4 17 18535 #define tx_x4_status0_actualSpeedsMisc1_dr_6000BRCM_X4 18 18536 #define tx_x4_status0_actualSpeedsMisc1_dr_10GHiGig_X4 19 18537 #define tx_x4_status0_actualSpeedsMisc1_dr_10GBASE_CX4 20 18538 #define tx_x4_status0_actualSpeedsMisc1_dr_12GHiGig_X4 21 18539 #define tx_x4_status0_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 18540 #define tx_x4_status0_actualSpeedsMisc1_dr_13GHiGig_X4 23 18541 #define tx_x4_status0_actualSpeedsMisc1_dr_15GHiGig_X4 24 18542 #define tx_x4_status0_actualSpeedsMisc1_dr_16GHiGig_X4 25 18543 #define tx_x4_status0_actualSpeedsMisc1_dr_5000BRCM_X1 26 18544 #define tx_x4_status0_actualSpeedsMisc1_dr_6363BRCM_X1 27 18545 #define tx_x4_status0_actualSpeedsMisc1_dr_20GHiGig_X4 28 18546 #define tx_x4_status0_actualSpeedsMisc1_dr_21GHiGig_X4 29 18547 #define tx_x4_status0_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 18548 #define tx_x4_status0_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 18549 18550 /**************************************************************************** 18551 * Enums: tx_x4_status0_IndLaneModes 18552 */ 18553 #define tx_x4_status0_IndLaneModes_SWSDR_div2 0 18554 #define tx_x4_status0_IndLaneModes_SWSDR_div1 1 18555 #define tx_x4_status0_IndLaneModes_DWSDR_div2 2 18556 #define tx_x4_status0_IndLaneModes_DWSDR_div1 3 18557 18558 /**************************************************************************** 18559 * Enums: tx_x4_status0_prbsSelect 18560 */ 18561 #define tx_x4_status0_prbsSelect_prbs7 0 18562 #define tx_x4_status0_prbsSelect_prbs15 1 18563 #define tx_x4_status0_prbsSelect_prbs23 2 18564 #define tx_x4_status0_prbsSelect_prbs31 3 18565 18566 /**************************************************************************** 18567 * Enums: tx_x4_status0_vcoDivider 18568 */ 18569 #define tx_x4_status0_vcoDivider_div32 0 18570 #define tx_x4_status0_vcoDivider_div36 1 18571 #define tx_x4_status0_vcoDivider_div40 2 18572 #define tx_x4_status0_vcoDivider_div42 3 18573 #define tx_x4_status0_vcoDivider_div48 4 18574 #define tx_x4_status0_vcoDivider_div50 5 18575 #define tx_x4_status0_vcoDivider_div52 6 18576 #define tx_x4_status0_vcoDivider_div54 7 18577 #define tx_x4_status0_vcoDivider_div60 8 18578 #define tx_x4_status0_vcoDivider_div64 9 18579 #define tx_x4_status0_vcoDivider_div66 10 18580 #define tx_x4_status0_vcoDivider_div68 11 18581 #define tx_x4_status0_vcoDivider_div70 12 18582 #define tx_x4_status0_vcoDivider_div80 13 18583 #define tx_x4_status0_vcoDivider_div92 14 18584 #define tx_x4_status0_vcoDivider_div100 15 18585 18586 /**************************************************************************** 18587 * Enums: tx_x4_status0_refClkSelect 18588 */ 18589 #define tx_x4_status0_refClkSelect_clk_156p25MHz 1 18590 #define tx_x4_status0_refClkSelect_clk_312p5Mhz 2 18591 18592 /**************************************************************************** 18593 * Enums: tx_x4_status0_aerMMDdevTypeSelect 18594 */ 18595 #define tx_x4_status0_aerMMDdevTypeSelect_combo_core 0 18596 #define tx_x4_status0_aerMMDdevTypeSelect_PMA_PMD 1 18597 #define tx_x4_status0_aerMMDdevTypeSelect_PCS 3 18598 #define tx_x4_status0_aerMMDdevTypeSelect_PHY 4 18599 #define tx_x4_status0_aerMMDdevTypeSelect_DTE 5 18600 #define tx_x4_status0_aerMMDdevTypeSelect_CL73_AN 7 18601 18602 /**************************************************************************** 18603 * Enums: tx_x4_status0_aerMMDportSelect 18604 */ 18605 #define tx_x4_status0_aerMMDportSelect_ln0 0 18606 #define tx_x4_status0_aerMMDportSelect_ln1 1 18607 #define tx_x4_status0_aerMMDportSelect_ln2 2 18608 #define tx_x4_status0_aerMMDportSelect_ln3 3 18609 #define tx_x4_status0_aerMMDportSelect_BCST_ln0_1_2_3 511 18610 #define tx_x4_status0_aerMMDportSelect_BCST_ln0_1 512 18611 #define tx_x4_status0_aerMMDportSelect_BCST_ln2_3 513 18612 18613 /**************************************************************************** 18614 * Enums: tx_x4_status0_firmwareModeSelect 18615 */ 18616 #define tx_x4_status0_firmwareModeSelect_DEFAULT 0 18617 #define tx_x4_status0_firmwareModeSelect_SFP_OPT_LR 1 18618 #define tx_x4_status0_firmwareModeSelect_SFP_DAC 2 18619 #define tx_x4_status0_firmwareModeSelect_XLAUI 3 18620 #define tx_x4_status0_firmwareModeSelect_LONG_CH_6G 4 18621 18622 /**************************************************************************** 18623 * Enums: tx_x4_status0_tempIdxSelect 18624 */ 18625 #define tx_x4_status0_tempIdxSelect_LTE__22p9C 15 18626 #define tx_x4_status0_tempIdxSelect_LTE__12p6C 14 18627 #define tx_x4_status0_tempIdxSelect_LTE__3p0C 13 18628 #define tx_x4_status0_tempIdxSelect_LTE_6p7C 12 18629 #define tx_x4_status0_tempIdxSelect_LTE_16p4C 11 18630 #define tx_x4_status0_tempIdxSelect_LTE_26p6C 10 18631 #define tx_x4_status0_tempIdxSelect_LTE_36p3C 9 18632 #define tx_x4_status0_tempIdxSelect_LTE_46p0C 8 18633 #define tx_x4_status0_tempIdxSelect_LTE_56p2C 7 18634 #define tx_x4_status0_tempIdxSelect_LTE_65p9C 6 18635 #define tx_x4_status0_tempIdxSelect_LTE_75p6C 5 18636 #define tx_x4_status0_tempIdxSelect_LTE_85p3C 4 18637 #define tx_x4_status0_tempIdxSelect_LTE_95p5C 3 18638 #define tx_x4_status0_tempIdxSelect_LTE_105p2C 2 18639 #define tx_x4_status0_tempIdxSelect_LTE_114p9C 1 18640 #define tx_x4_status0_tempIdxSelect_LTE_125p1C 0 18641 18642 /**************************************************************************** 18643 * Enums: tx_x4_status0_port_mode 18644 */ 18645 #define tx_x4_status0_port_mode_QUAD_PORT 0 18646 #define tx_x4_status0_port_mode_TRI_1_PORT 1 18647 #define tx_x4_status0_port_mode_TRI_2_PORT 2 18648 #define tx_x4_status0_port_mode_DUAL_PORT 3 18649 #define tx_x4_status0_port_mode_SINGLE_PORT 4 18650 #define tx_x4_status0_port_mode_SINGLE_OCTAL_PORT 5 18651 18652 /**************************************************************************** 18653 * Enums: tx_x4_status0_rev_letter_enum 18654 */ 18655 #define tx_x4_status0_rev_letter_enum_REV_A 0 18656 #define tx_x4_status0_rev_letter_enum_REV_B 1 18657 #define tx_x4_status0_rev_letter_enum_REV_C 2 18658 #define tx_x4_status0_rev_letter_enum_REV_D 3 18659 18660 /**************************************************************************** 18661 * Enums: tx_x4_status0_rev_number_enum 18662 */ 18663 #define tx_x4_status0_rev_number_enum_REV_0 0 18664 #define tx_x4_status0_rev_number_enum_REV_1 1 18665 #define tx_x4_status0_rev_number_enum_REV_2 2 18666 #define tx_x4_status0_rev_number_enum_REV_3 3 18667 #define tx_x4_status0_rev_number_enum_REV_4 4 18668 #define tx_x4_status0_rev_number_enum_REV_5 5 18669 #define tx_x4_status0_rev_number_enum_REV_6 6 18670 #define tx_x4_status0_rev_number_enum_REV_7 7 18671 18672 /**************************************************************************** 18673 * Enums: tx_x4_status0_bonding_enum 18674 */ 18675 #define tx_x4_status0_bonding_enum_WIRE_BOND 0 18676 #define tx_x4_status0_bonding_enum_FLIP_CHIP 1 18677 18678 /**************************************************************************** 18679 * Enums: tx_x4_status0_tech_process 18680 */ 18681 #define tx_x4_status0_tech_process_PROCESS_90NM 0 18682 #define tx_x4_status0_tech_process_PROCESS_65NM 1 18683 #define tx_x4_status0_tech_process_PROCESS_40NM 2 18684 #define tx_x4_status0_tech_process_PROCESS_28NM 3 18685 #define tx_x4_status0_tech_process_PROCESS_16NM 4 18686 18687 /**************************************************************************** 18688 * Enums: tx_x4_status0_model_num 18689 */ 18690 #define tx_x4_status0_model_num_SERDES_CL73 0 18691 #define tx_x4_status0_model_num_XGXS_16G 1 18692 #define tx_x4_status0_model_num_HYPERCORE 2 18693 #define tx_x4_status0_model_num_HYPERLITE 3 18694 #define tx_x4_status0_model_num_PCIE_G2_PIPE 4 18695 #define tx_x4_status0_model_num_SERDES_1p25GBd 5 18696 #define tx_x4_status0_model_num_SATA2 6 18697 #define tx_x4_status0_model_num_QSGMII 7 18698 #define tx_x4_status0_model_num_XGXS10G 8 18699 #define tx_x4_status0_model_num_WARPCORE 9 18700 #define tx_x4_status0_model_num_XFICORE 10 18701 #define tx_x4_status0_model_num_RXFI 11 18702 #define tx_x4_status0_model_num_WARPLITE 12 18703 #define tx_x4_status0_model_num_PENTACORE 13 18704 #define tx_x4_status0_model_num_ESM 14 18705 #define tx_x4_status0_model_num_QUAD_SGMII 15 18706 #define tx_x4_status0_model_num_WARPCORE_3 16 18707 #define tx_x4_status0_model_num_TSC 17 18708 #define tx_x4_status0_model_num_TSC4E 18 18709 #define tx_x4_status0_model_num_TSC12E 19 18710 #define tx_x4_status0_model_num_TSC4F 20 18711 #define tx_x4_status0_model_num_TSC4F_GEN2 21 18712 #define tx_x4_status0_model_num_XGXS_CL73_90NM 29 18713 #define tx_x4_status0_model_num_SERDES_CL73_90NM 30 18714 #define tx_x4_status0_model_num_WARPCORE3 32 18715 #define tx_x4_status0_model_num_WARPCORE4_TSC 33 18716 #define tx_x4_status0_model_num_RXAUI 34 18717 #define tx_x4_status0_model_num_TSCE_GEN3 35 18718 #define tx_x4_status0_model_num_TSC4F_GEN3 36 18719 #define tx_x4_status0_model_num_TSCBH 37 18720 18721 /**************************************************************************** 18722 * Enums: tx_x4_status0_payload 18723 */ 18724 #define tx_x4_status0_payload_REPEAT_2_BYTES 0 18725 #define tx_x4_status0_payload_RAMPING 1 18726 #define tx_x4_status0_payload_CL48_CRPAT 2 18727 #define tx_x4_status0_payload_CL48_CJPAT 3 18728 #define tx_x4_status0_payload_CL36_LONG_CRPAT 4 18729 #define tx_x4_status0_payload_CL36_SHORT_CRPAT 5 18730 18731 /**************************************************************************** 18732 * Enums: tx_x4_status0_sc 18733 */ 18734 #define tx_x4_status0_sc_SPEED_10G_IEEE_KR1 0 18735 #define tx_x4_status0_sc_SPEED_25G_IEEE_KS1_CS1 1 18736 #define tx_x4_status0_sc_SPEED_25G_IEEE_KR1_CR1 2 18737 #define tx_x4_status0_sc_SPEED_40G_IEEE_KR4 3 18738 #define tx_x4_status0_sc_SPEED_40G_IEEE_CR4 4 18739 #define tx_x4_status0_sc_SPEED_50G_IEEE_KR1_CR1 5 18740 #define tx_x4_status0_sc_SPEED_100G_IEEE_KR4 6 18741 #define tx_x4_status0_sc_SPEED_100G_IEEE_CR4 7 18742 #define tx_x4_status0_sc_SPEED_100G_IEEE_KR2_CR2 8 18743 #define tx_x4_status0_sc_SPEED_200G_IEEE_KR4_CR4 9 18744 #define tx_x4_status0_sc_SPEED_400G_IEEE_X8 10 18745 #define tx_x4_status0_sc_SPEED_CL73_IEEE_20GVCO 11 18746 #define tx_x4_status0_sc_SPEED_CL73_IEEE_25GVCO 12 18747 #define tx_x4_status0_sc_SPEED_CL73_IEEE_26GVCO 13 18748 #define tx_x4_status0_sc_SPEED_20G_BRCM_CR1 14 18749 #define tx_x4_status0_sc_SPEED_20G_BRCM_KR1 15 18750 #define tx_x4_status0_sc_SPEED_25G_BRCM_CR1 16 18751 #define tx_x4_status0_sc_SPEED_25G_BRCM_KR1 17 18752 #define tx_x4_status0_sc_SPEED_40G_BRCM_CR2 18 18753 #define tx_x4_status0_sc_SPEED_40G_BRCM_KR2 19 18754 #define tx_x4_status0_sc_SPEED_50G_BRCM_CR2 20 18755 #define tx_x4_status0_sc_SPEED_50G_BRCM_KR2 21 18756 #define tx_x4_status0_sc_SPEED_50G_BRCM_CR4 22 18757 #define tx_x4_status0_sc_SPEED_50G_BRCM_KR4 23 18758 #define tx_x4_status0_sc_SPEED_50G_BRCM_FEC_544_CR2_KR2 24 18759 #define tx_x4_status0_sc_SPEED_RESERVED_19 25 18760 #define tx_x4_status0_sc_SPEED_50G_BRCM_FEC_544_CR1_KR1 26 18761 #define tx_x4_status0_sc_SPEED_50G_BRCM_NO_FEC_CR1_KR1 27 18762 #define tx_x4_status0_sc_SPEED_50G_BRCM_FEC_528_CR1_KR1 28 18763 #define tx_x4_status0_sc_SPEED_400G_BRCM_NO_FEC_KR8_CR8 29 18764 #define tx_x4_status0_sc_SPEED_400G_BRCM_FEC_KR8_CR8 30 18765 #define tx_x4_status0_sc_SPEED_200G_BRCM_NO_FEC_KR4_CR4 31 18766 #define tx_x4_status0_sc_SPEED_200G_BRCM_KR4_CR4 32 18767 #define tx_x4_status0_sc_SPEED_100G_BRCM_KR4_CR4 33 18768 #define tx_x4_status0_sc_SPEED_RESERVED_22 34 18769 #define tx_x4_status0_sc_SPEED_100G_BRCM_FEC_528_KR2_CR2 35 18770 #define tx_x4_status0_sc_SPEED_100G_BRCM_NO_FEC_KR2_CR2 36 18771 #define tx_x4_status0_sc_SPEED_100G_BRCM_NO_FEC_X4 37 18772 18773 /**************************************************************************** 18774 * Enums: tx_x4_status0_t_fifo_modes 18775 */ 18776 #define tx_x4_status0_t_fifo_modes_T_FIFO_INSERT_NO_AM 0 18777 #define tx_x4_status0_t_fifo_modes_T_FIFO_INSERT_4_AM 1 18778 #define tx_x4_status0_t_fifo_modes_T_FIFO_INSERT_20_AM 2 18779 #define tx_x4_status0_t_fifo_modes_T_FIFO_INSERT_2_AM 3 18780 18781 /**************************************************************************** 18782 * Enums: tx_x4_status0_t_enc_modes 18783 */ 18784 #define tx_x4_status0_t_enc_modes_T_ENC_MODE_BYPASS 0 18785 #define tx_x4_status0_t_enc_modes_T_ENC_MODE_CL49 1 18786 #define tx_x4_status0_t_enc_modes_T_ENC_MODE_CL82 2 18787 18788 /**************************************************************************** 18789 * Enums: tx_x4_status0_btmx_mode 18790 */ 18791 #define tx_x4_status0_btmx_mode_BS_BTMX_MODE_1to1 0 18792 #define tx_x4_status0_btmx_mode_BS_BTMX_MODE_2to1 1 18793 #define tx_x4_status0_btmx_mode_BS_BTMX_MODE_5to1 2 18794 18795 /**************************************************************************** 18796 * Enums: tx_x4_status0_t_type_cl82 18797 */ 18798 #define tx_x4_status0_t_type_cl82_T_TYPE_B1 5 18799 #define tx_x4_status0_t_type_cl82_T_TYPE_C 4 18800 #define tx_x4_status0_t_type_cl82_T_TYPE_S 3 18801 #define tx_x4_status0_t_type_cl82_T_TYPE_T 2 18802 #define tx_x4_status0_t_type_cl82_T_TYPE_D 1 18803 #define tx_x4_status0_t_type_cl82_T_TYPE_E 0 18804 18805 /**************************************************************************** 18806 * Enums: tx_x4_status0_txsm_state_cl82 18807 */ 18808 #define tx_x4_status0_txsm_state_cl82_TX_E 4 18809 #define tx_x4_status0_txsm_state_cl82_TX_T 3 18810 #define tx_x4_status0_txsm_state_cl82_TX_D 2 18811 #define tx_x4_status0_txsm_state_cl82_TX_C 1 18812 #define tx_x4_status0_txsm_state_cl82_TX_INIT 0 18813 18814 /**************************************************************************** 18815 * Enums: tx_x4_status0_ltxsm_state_cl82 18816 */ 18817 #define tx_x4_status0_ltxsm_state_cl82_TX_E 16 18818 #define tx_x4_status0_ltxsm_state_cl82_TX_T 8 18819 #define tx_x4_status0_ltxsm_state_cl82_TX_D 4 18820 #define tx_x4_status0_ltxsm_state_cl82_TX_C 2 18821 #define tx_x4_status0_ltxsm_state_cl82_TX_INIT 1 18822 18823 /**************************************************************************** 18824 * Enums: tx_x4_status0_r_type_coded_cl82 18825 */ 18826 #define tx_x4_status0_r_type_coded_cl82_R_TYPE_B1 32 18827 #define tx_x4_status0_r_type_coded_cl82_R_TYPE_C 16 18828 #define tx_x4_status0_r_type_coded_cl82_R_TYPE_S 8 18829 #define tx_x4_status0_r_type_coded_cl82_R_TYPE_T 4 18830 #define tx_x4_status0_r_type_coded_cl82_R_TYPE_D 2 18831 #define tx_x4_status0_r_type_coded_cl82_R_TYPE_E 1 18832 18833 /**************************************************************************** 18834 * Enums: tx_x4_status0_rxsm_state_cl82 18835 */ 18836 #define tx_x4_status0_rxsm_state_cl82_RX_E 16 18837 #define tx_x4_status0_rxsm_state_cl82_RX_T 8 18838 #define tx_x4_status0_rxsm_state_cl82_RX_D 4 18839 #define tx_x4_status0_rxsm_state_cl82_RX_C 2 18840 #define tx_x4_status0_rxsm_state_cl82_RX_INIT 1 18841 18842 /**************************************************************************** 18843 * Enums: tx_x4_status0_deskew_state 18844 */ 18845 #define tx_x4_status0_deskew_state_ALIGN_ACQUIRED 2 18846 #define tx_x4_status0_deskew_state_LOSS_OF_ALIGNMENT 1 18847 18848 /**************************************************************************** 18849 * Enums: tx_x4_status0_os_mode_enum 18850 */ 18851 #define tx_x4_status0_os_mode_enum_OS_MODE_1 0 18852 #define tx_x4_status0_os_mode_enum_OS_MODE_2 1 18853 #define tx_x4_status0_os_mode_enum_OS_MODE_4 2 18854 #define tx_x4_status0_os_mode_enum_OS_MODE_16p5 8 18855 #define tx_x4_status0_os_mode_enum_OS_MODE_20p625 12 18856 18857 /**************************************************************************** 18858 * Enums: tx_x4_status0_scr_modes 18859 */ 18860 #define tx_x4_status0_scr_modes_T_SCR_MODE_BYPASS 0 18861 #define tx_x4_status0_scr_modes_T_SCR_MODE_CL49 1 18862 #define tx_x4_status0_scr_modes_T_SCR_MODE_40G_2_LANE 2 18863 #define tx_x4_status0_scr_modes_T_SCR_MODE_100G 3 18864 #define tx_x4_status0_scr_modes_T_SCR_MODE_20G 4 18865 #define tx_x4_status0_scr_modes_T_SCR_MODE_40G_4_LANE 5 18866 18867 /**************************************************************************** 18868 * Enums: tx_x4_status0_descr_modes 18869 */ 18870 #define tx_x4_status0_descr_modes_R_DESCR_MODE_BYPASS 0 18871 #define tx_x4_status0_descr_modes_R_DESCR_MODE_CL49 1 18872 #define tx_x4_status0_descr_modes_R_DESCR_MODE_CL82 2 18873 18874 /**************************************************************************** 18875 * Enums: tx_x4_status0_r_dec_tl_mode 18876 */ 18877 #define tx_x4_status0_r_dec_tl_mode_R_DEC_TL_MODE_BYPASS 0 18878 #define tx_x4_status0_r_dec_tl_mode_R_DEC_TL_MODE_CL49 1 18879 #define tx_x4_status0_r_dec_tl_mode_R_DEC_TL_MODE_CL82 2 18880 18881 /**************************************************************************** 18882 * Enums: tx_x4_status0_r_dec_fsm_mode 18883 */ 18884 #define tx_x4_status0_r_dec_fsm_mode_R_DEC_FSM_MODE_BYPASS 0 18885 #define tx_x4_status0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL49 1 18886 #define tx_x4_status0_r_dec_fsm_mode_R_DEC_FSM_MODE_CL82 2 18887 18888 /**************************************************************************** 18889 * Enums: tx_x4_status0_r_deskew_mode 18890 */ 18891 #define tx_x4_status0_r_deskew_mode_R_DESKEW_MODE_BYPASS 0 18892 #define tx_x4_status0_r_deskew_mode_R_DESKEW_MODE_20G 1 18893 #define tx_x4_status0_r_deskew_mode_R_DESKEW_MODE_40G_4_LANE 2 18894 #define tx_x4_status0_r_deskew_mode_R_DESKEW_MODE_40G_2_LANE 3 18895 #define tx_x4_status0_r_deskew_mode_R_DESKEW_MODE_100G 4 18896 #define tx_x4_status0_r_deskew_mode_R_DESKEW_MODE_CL49 5 18897 #define tx_x4_status0_r_deskew_mode_R_DESKEW_MODE_CL91_QUAD 6 18898 #define tx_x4_status0_r_deskew_mode_R_DESKEW_MODE_CL91_SINGLE_BRCM 7 18899 #define tx_x4_status0_r_deskew_mode_R_DESKEW_MODE_CL91_DUAL_BRCM 8 18900 #define tx_x4_status0_r_deskew_mode_R_DESKEW_MODE_CL91_FC 9 18901 18902 /**************************************************************************** 18903 * Enums: tx_x4_status0_bs_dist_modes 18904 */ 18905 #define tx_x4_status0_bs_dist_modes_BS_DIST_MODE_5_LANE_TDM 0 18906 #define tx_x4_status0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_2_VLANE 1 18907 #define tx_x4_status0_bs_dist_modes_BS_DIST_MODE_2_LANE_TDM_1_VLANE 2 18908 #define tx_x4_status0_bs_dist_modes_BS_DIST_MODE_NO_TDM 3 18909 18910 /**************************************************************************** 18911 * Enums: tx_x4_status0_cl49_t_type 18912 */ 18913 #define tx_x4_status0_cl49_t_type_BAD_T_TYPE 15 18914 #define tx_x4_status0_cl49_t_type_T_TYPE_B0 11 18915 #define tx_x4_status0_cl49_t_type_T_TYPE_OB 10 18916 #define tx_x4_status0_cl49_t_type_T_TYPE_B1 9 18917 #define tx_x4_status0_cl49_t_type_T_TYPE_DB 8 18918 #define tx_x4_status0_cl49_t_type_T_TYPE_FC 7 18919 #define tx_x4_status0_cl49_t_type_T_TYPE_TB 6 18920 #define tx_x4_status0_cl49_t_type_T_TYPE_LI 5 18921 #define tx_x4_status0_cl49_t_type_T_TYPE_C 4 18922 #define tx_x4_status0_cl49_t_type_T_TYPE_S 3 18923 #define tx_x4_status0_cl49_t_type_T_TYPE_T 2 18924 #define tx_x4_status0_cl49_t_type_T_TYPE_D 1 18925 #define tx_x4_status0_cl49_t_type_T_TYPE_E 0 18926 18927 /**************************************************************************** 18928 * Enums: tx_x4_status0_cl49_txsm_states 18929 */ 18930 #define tx_x4_status0_cl49_txsm_states_TX_LI 5 18931 #define tx_x4_status0_cl49_txsm_states_TX_E 4 18932 #define tx_x4_status0_cl49_txsm_states_TX_T 3 18933 #define tx_x4_status0_cl49_txsm_states_TX_D 2 18934 #define tx_x4_status0_cl49_txsm_states_TX_C 1 18935 #define tx_x4_status0_cl49_txsm_states_TX_INIT 0 18936 18937 /**************************************************************************** 18938 * Enums: tx_x4_status0_cl49_ltxsm_states 18939 */ 18940 #define tx_x4_status0_cl49_ltxsm_states_TX_LI 32 18941 #define tx_x4_status0_cl49_ltxsm_states_TX_E 16 18942 #define tx_x4_status0_cl49_ltxsm_states_TX_T 8 18943 #define tx_x4_status0_cl49_ltxsm_states_TX_D 4 18944 #define tx_x4_status0_cl49_ltxsm_states_TX_C 2 18945 #define tx_x4_status0_cl49_ltxsm_states_TX_INIT 1 18946 18947 /**************************************************************************** 18948 * Enums: tx_x4_status0_burst_error_mode 18949 */ 18950 #define tx_x4_status0_burst_error_mode_BURST_ERROR_11_BITS 0 18951 #define tx_x4_status0_burst_error_mode_BURST_ERROR_16_BITS 1 18952 #define tx_x4_status0_burst_error_mode_BURST_ERROR_17_BITS 2 18953 #define tx_x4_status0_burst_error_mode_BURST_ERROR_18_BITS 3 18954 #define tx_x4_status0_burst_error_mode_BURST_ERROR_19_BITS 4 18955 #define tx_x4_status0_burst_error_mode_BURST_ERROR_20_BITS 5 18956 #define tx_x4_status0_burst_error_mode_BURST_ERROR_21_BITS 6 18957 #define tx_x4_status0_burst_error_mode_BURST_ERROR_22_BITS 7 18958 #define tx_x4_status0_burst_error_mode_BURST_ERROR_23_BITS 8 18959 #define tx_x4_status0_burst_error_mode_BURST_ERROR_24_BITS 9 18960 #define tx_x4_status0_burst_error_mode_BURST_ERROR_25_BITS 10 18961 #define tx_x4_status0_burst_error_mode_BURST_ERROR_26_BITS 11 18962 #define tx_x4_status0_burst_error_mode_BURST_ERROR_27_BITS 12 18963 #define tx_x4_status0_burst_error_mode_BURST_ERROR_28_BITS 13 18964 #define tx_x4_status0_burst_error_mode_BURST_ERROR_29_BITS 14 18965 #define tx_x4_status0_burst_error_mode_BURST_ERROR_30_BITS 15 18966 #define tx_x4_status0_burst_error_mode_BURST_ERROR_31_BITS 16 18967 #define tx_x4_status0_burst_error_mode_BURST_ERROR_32_BITS 17 18968 #define tx_x4_status0_burst_error_mode_BURST_ERROR_33_BITS 18 18969 #define tx_x4_status0_burst_error_mode_BURST_ERROR_34_BITS 19 18970 #define tx_x4_status0_burst_error_mode_BURST_ERROR_35_BITS 20 18971 #define tx_x4_status0_burst_error_mode_BURST_ERROR_36_BITS 21 18972 #define tx_x4_status0_burst_error_mode_BURST_ERROR_37_BITS 22 18973 #define tx_x4_status0_burst_error_mode_BURST_ERROR_38_BITS 23 18974 #define tx_x4_status0_burst_error_mode_BURST_ERROR_39_BITS 24 18975 #define tx_x4_status0_burst_error_mode_BURST_ERROR_40_BITS 25 18976 #define tx_x4_status0_burst_error_mode_BURST_ERROR_41_BITS 26 18977 18978 /**************************************************************************** 18979 * Enums: tx_x4_status0_bermon_state 18980 */ 18981 #define tx_x4_status0_bermon_state_HI_BER 4 18982 #define tx_x4_status0_bermon_state_GOOD_BER 3 18983 #define tx_x4_status0_bermon_state_BER_TEST_SH 2 18984 #define tx_x4_status0_bermon_state_START_TIMER 1 18985 #define tx_x4_status0_bermon_state_BER_MT_INIT 0 18986 18987 /**************************************************************************** 18988 * Enums: tx_x4_status0_rxsm_state_cl49 18989 */ 18990 #define tx_x4_status0_rxsm_state_cl49_RX_LI 32 18991 #define tx_x4_status0_rxsm_state_cl49_RX_E 16 18992 #define tx_x4_status0_rxsm_state_cl49_RX_T 8 18993 #define tx_x4_status0_rxsm_state_cl49_RX_D 4 18994 #define tx_x4_status0_rxsm_state_cl49_RX_C 2 18995 #define tx_x4_status0_rxsm_state_cl49_RX_INIT 1 18996 18997 /**************************************************************************** 18998 * Enums: tx_x4_status0_r_type 18999 */ 19000 #define tx_x4_status0_r_type_BAD_R_TYPE 15 19001 #define tx_x4_status0_r_type_R_TYPE_B0 11 19002 #define tx_x4_status0_r_type_R_TYPE_OB 10 19003 #define tx_x4_status0_r_type_R_TYPE_B1 9 19004 #define tx_x4_status0_r_type_R_TYPE_DB 8 19005 #define tx_x4_status0_r_type_R_TYPE_FC 7 19006 #define tx_x4_status0_r_type_R_TYPE_TB 6 19007 #define tx_x4_status0_r_type_R_TYPE_LI 5 19008 #define tx_x4_status0_r_type_R_TYPE_C 4 19009 #define tx_x4_status0_r_type_R_TYPE_S 3 19010 #define tx_x4_status0_r_type_R_TYPE_T 2 19011 #define tx_x4_status0_r_type_R_TYPE_D 1 19012 #define tx_x4_status0_r_type_R_TYPE_E 0 19013 19014 /**************************************************************************** 19015 * Enums: tx_x4_status0_am_lock_state 19016 */ 19017 #define tx_x4_status0_am_lock_state_INVALID_AM 512 19018 #define tx_x4_status0_am_lock_state_GOOD_AM 256 19019 #define tx_x4_status0_am_lock_state_COMP_AM 128 19020 #define tx_x4_status0_am_lock_state_TIMER_2 64 19021 #define tx_x4_status0_am_lock_state_AM_2_GOOD 32 19022 #define tx_x4_status0_am_lock_state_COMP_2ND 16 19023 #define tx_x4_status0_am_lock_state_TIMER_1 8 19024 #define tx_x4_status0_am_lock_state_FIND_1ST 4 19025 #define tx_x4_status0_am_lock_state_AM_RESET_CNT 2 19026 #define tx_x4_status0_am_lock_state_AM_LOCK_INIT 1 19027 19028 /**************************************************************************** 19029 * Enums: tx_x4_status0_msg_selector 19030 */ 19031 #define tx_x4_status0_msg_selector_RESERVED 0 19032 #define tx_x4_status0_msg_selector_VALUE_802p3 1 19033 #define tx_x4_status0_msg_selector_VALUE_802p9 2 19034 #define tx_x4_status0_msg_selector_VALUE_802p5 3 19035 #define tx_x4_status0_msg_selector_VALUE_1394 4 19036 19037 /**************************************************************************** 19038 * Enums: tx_x4_status0_synce_enum_stage1 19039 */ 19040 #define tx_x4_status0_synce_enum_stage1_SYNCE_NO_DIV 0 19041 #define tx_x4_status0_synce_enum_stage1_SYNCE_DIV_7 1 19042 #define tx_x4_status0_synce_enum_stage1_SYNCE_DIV_11 2 19043 19044 /**************************************************************************** 19045 * Enums: tx_x4_status0_synce_enum_stage0 19046 */ 19047 #define tx_x4_status0_synce_enum_stage0_SYNCE_NO_DIV 0 19048 #define tx_x4_status0_synce_enum_stage0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 19049 #define tx_x4_status0_synce_enum_stage0_SYNCE_DIV_SDM_FRAC_DIV 2 19050 19051 /**************************************************************************** 19052 * Enums: tx_x4_status0_cl91_sync_state 19053 */ 19054 #define tx_x4_status0_cl91_sync_state_FIND_1ST 0 19055 #define tx_x4_status0_cl91_sync_state_COUNT_NEXT 1 19056 #define tx_x4_status0_cl91_sync_state_COMP_2ND 2 19057 #define tx_x4_status0_cl91_sync_state_TWO_GOOD 3 19058 19059 /**************************************************************************** 19060 * Enums: tx_x4_status0_RS_FEC_sync_state 19061 */ 19062 #define tx_x4_status0_RS_FEC_sync_state_LOCK_INIT 0 19063 #define tx_x4_status0_RS_FEC_sync_state_FIND_1ST 1 19064 #define tx_x4_status0_RS_FEC_sync_state_COUNT_NEXT 2 19065 #define tx_x4_status0_RS_FEC_sync_state_COMP_2ND 3 19066 #define tx_x4_status0_RS_FEC_sync_state_TWO_GOOD 4 19067 19068 /**************************************************************************** 19069 * Enums: tx_x4_status0_cl91_algn_state 19070 */ 19071 #define tx_x4_status0_cl91_algn_state_LOSS_OF_ALIGNMENT 0 19072 #define tx_x4_status0_cl91_algn_state_DESKEW 1 19073 #define tx_x4_status0_cl91_algn_state_DESKEW_FAIL 2 19074 #define tx_x4_status0_cl91_algn_state_ALIGN_ACQUIRED 3 19075 #define tx_x4_status0_cl91_algn_state_CW_GOOD 4 19076 #define tx_x4_status0_cl91_algn_state_CW_BAD 5 19077 #define tx_x4_status0_cl91_algn_state_THREE_BAD 6 19078 19079 /**************************************************************************** 19080 * Enums: tx_x4_status0_RS_FEC_algn_state 19081 */ 19082 #define tx_x4_status0_RS_FEC_algn_state_LOSS_OF_ALIGNMENT 0 19083 #define tx_x4_status0_RS_FEC_algn_state_DESKEW 1 19084 #define tx_x4_status0_RS_FEC_algn_state_DESKEW_FAIL 2 19085 #define tx_x4_status0_RS_FEC_algn_state_ALIGN_ACQUIRED 3 19086 #define tx_x4_status0_RS_FEC_algn_state_CW_GOOD 4 19087 #define tx_x4_status0_RS_FEC_algn_state_CW_BAD 5 19088 #define tx_x4_status0_RS_FEC_algn_state_THREE_BAD 6 19089 19090 /**************************************************************************** 19091 * Enums: tx_x4_status0_fec_sel_override 19092 */ 19093 #define tx_x4_status0_fec_sel_override_NO_OVERRIDE 0 19094 #define tx_x4_status0_fec_sel_override_NO_FEC 1 19095 #define tx_x4_status0_fec_sel_override_FEC_CL74 2 19096 #define tx_x4_status0_fec_sel_override_FEC_CL91 3 19097 19098 /**************************************************************************** 19099 * Enums: tx_x4_status0_cl91_blksync_mode 19100 */ 19101 #define tx_x4_status0_cl91_blksync_mode_R_BLKSYNC_NO_CL91_FEC 0 19102 #define tx_x4_status0_cl91_blksync_mode_R_BLKSYNC_CL91_QUAD_LANE_FEC 1 19103 #define tx_x4_status0_cl91_blksync_mode_R_BLKSYNC_CL91_DUAL_LANE_FEC 2 19104 #define tx_x4_status0_cl91_blksync_mode_R_BLKSYNC_CL91_SINGLE_LANE_FEC 3 19105 #define tx_x4_status0_cl91_blksync_mode_R_BLKSYNC_CL91_FC_FEC 4 19106 19107 /**************************************************************************** 19108 * Enums: tx_x4_status0_r_merge_mode 19109 */ 19110 #define tx_x4_status0_r_merge_mode_R_MERGE_MODE_BYPASS 0 19111 #define tx_x4_status0_r_merge_mode_R_MERGE_MODE_CL91_FC 1 19112 #define tx_x4_status0_r_merge_mode_R_MERGE_MODE_CL91_SINGLE_LANE 2 19113 #define tx_x4_status0_r_merge_mode_R_MERGE_MODE_CL91_DUAL_LANE 3 19114 #define tx_x4_status0_r_merge_mode_R_MERGE_MODE_CL91_QUAD_LANE 4 19115 19116 /**************************************************************************** 19117 * Enums: tx_x4_status0_r_tc_mode 19118 */ 19119 #define tx_x4_status0_r_tc_mode_R_TC_MODE_SINGLE 0 19120 #define tx_x4_status0_r_tc_mode_R_TC_MODE_DUAL 1 19121 #define tx_x4_status0_r_tc_mode_R_TC_MODE_QUAD 2 19122 19123 /**************************************************************************** 19124 * Enums: tx_x4_status0_r_tc_out_mode 19125 */ 19126 #define tx_x4_status0_r_tc_out_mode_R_TC_OUT_MODE_SINGLE 0 19127 #define tx_x4_status0_r_tc_out_mode_R_TC_OUT_MODE_DUAL 1 19128 #define tx_x4_status0_r_tc_out_mode_R_TC_OUT_MODE_QUAD 2 19129 19130 /**************************************************************************** 19131 * Enums: tx_x4_status0_cl91_fec_mode 19132 */ 19133 #define tx_x4_status0_cl91_fec_mode_NO_CL91_FEC 0 19134 #define tx_x4_status0_cl91_fec_mode_CL91_SINGLE_LANE_FC 1 19135 #define tx_x4_status0_cl91_fec_mode_CL91_SINGLE_LANE_BRCM_PROP 2 19136 #define tx_x4_status0_cl91_fec_mode_CL91_DUAL_LANE_BRCM_PROP 3 19137 #define tx_x4_status0_cl91_fec_mode_CL91_QUAD_LANE 4 19138 #define tx_x4_status0_cl91_fec_mode_IEEE_25G_CL91_SINGLE_LANE 5 19139 19140 /**************************************************************************** 19141 * Enums: tx_x4_status0_RS_FEC_fec_mode 19142 */ 19143 #define tx_x4_status0_RS_FEC_fec_mode_NO_RS_FEC_FEC 0 19144 #define tx_x4_status0_RS_FEC_fec_mode_N_A 1 19145 #define tx_x4_status0_RS_FEC_fec_mode_RS_FEC_SINGLE_LANE_BRCM_PROP 2 19146 #define tx_x4_status0_RS_FEC_fec_mode_RS_FEC_DUAL_LANE_BRCM_PROP 3 19147 #define tx_x4_status0_RS_FEC_fec_mode_RS_FEC_QUAD_LANE 4 19148 #define tx_x4_status0_RS_FEC_fec_mode_IEEE_25G_RS_FEC_SINGLE_LANE 5 19149 19150 /**************************************************************************** 19151 * Enums: tx_x4_status0_am_spacing_mul 19152 */ 19153 #define tx_x4_status0_am_spacing_mul_AM_SPACING_MUL_2 0 19154 #define tx_x4_status0_am_spacing_mul_AM_SPACING_MUL_4 1 19155 #define tx_x4_status0_am_spacing_mul_AM_SPACING_MUL_5 2 19156 #define tx_x4_status0_am_spacing_mul_AM_SPACING_MUL_20 3 19157 19158 19159 19160 19161 /**************************************************************************** 19162 * TSC_IEEE_CL22_CL22_B0 19163 */ 19164 /**************************************************************************** 19165 * CL22_B0 :: phyid2 19166 */ 19167 /* CL22_B0 :: phyid2 :: regid1 [15:00] */ 19168 #define CL22_B0_PHYID2_REGID1_MASK 0xffff 19169 #define CL22_B0_PHYID2_REGID1_ALIGN 0 19170 #define CL22_B0_PHYID2_REGID1_BITS 16 19171 #define CL22_B0_PHYID2_REGID1_SHIFT 0 19172 19173 19174 /**************************************************************************** 19175 * CL22_B0 :: phyid3 19176 */ 19177 /* CL22_B0 :: phyid3 :: regid2 [15:00] */ 19178 #define CL22_B0_PHYID3_REGID2_MASK 0xffff 19179 #define CL22_B0_PHYID3_REGID2_ALIGN 0 19180 #define CL22_B0_PHYID3_REGID2_BITS 16 19181 #define CL22_B0_PHYID3_REGID2_SHIFT 0 19182 19183 19184 /**************************************************************************** 19185 * TSC_TSC_USER1_Main0 19186 */ 19187 /**************************************************************************** 19188 * Main0 :: setup 19189 */ 19190 /* Main0 :: setup :: reserved0 [15:10] */ 19191 #define MAIN0_SETUP_RESERVED0_MASK 0xfc00 19192 #define MAIN0_SETUP_RESERVED0_ALIGN 0 19193 #define MAIN0_SETUP_RESERVED0_BITS 6 19194 #define MAIN0_SETUP_RESERVED0_SHIFT 10 19195 19196 /* Main0 :: setup :: refclk_sel [09:07] */ 19197 #define MAIN0_SETUP_REFCLK_SEL_MASK 0x0380 19198 #define MAIN0_SETUP_REFCLK_SEL_ALIGN 0 19199 #define MAIN0_SETUP_REFCLK_SEL_BITS 3 19200 #define MAIN0_SETUP_REFCLK_SEL_SHIFT 7 19201 #define MAIN0_SETUP_REFCLK_SEL_clk_156p25MHz 1 19202 #define MAIN0_SETUP_REFCLK_SEL_clk_312p5Mhz 2 19203 19204 /* Main0 :: setup :: port_mode_sel [06:04] */ 19205 #define MAIN0_SETUP_PORT_MODE_SEL_MASK 0x0070 19206 #define MAIN0_SETUP_PORT_MODE_SEL_ALIGN 0 19207 #define MAIN0_SETUP_PORT_MODE_SEL_BITS 3 19208 #define MAIN0_SETUP_PORT_MODE_SEL_SHIFT 4 19209 #define MAIN0_SETUP_PORT_MODE_SEL_QUAD_PORT 0 19210 #define MAIN0_SETUP_PORT_MODE_SEL_TRI_1_PORT 1 19211 #define MAIN0_SETUP_PORT_MODE_SEL_TRI_2_PORT 2 19212 #define MAIN0_SETUP_PORT_MODE_SEL_DUAL_PORT 3 19213 #define MAIN0_SETUP_PORT_MODE_SEL_SINGLE_PORT 4 19214 #define MAIN0_SETUP_PORT_MODE_SEL_SINGLE_OCTAL_PORT 5 19215 19216 /* Main0 :: setup :: resolved_port_mode_control [03:03] */ 19217 #define MAIN0_SETUP_RESOLVED_PORT_MODE_CONTROL_MASK 0x0008 19218 #define MAIN0_SETUP_RESOLVED_PORT_MODE_CONTROL_ALIGN 0 19219 #define MAIN0_SETUP_RESOLVED_PORT_MODE_CONTROL_BITS 1 19220 #define MAIN0_SETUP_RESOLVED_PORT_MODE_CONTROL_SHIFT 3 19221 19222 /* Main0 :: setup :: reserved1 [02:00] */ 19223 #define MAIN0_SETUP_RESERVED1_MASK 0x0007 19224 #define MAIN0_SETUP_RESERVED1_ALIGN 0 19225 #define MAIN0_SETUP_RESERVED1_BITS 3 19226 #define MAIN0_SETUP_RESERVED1_SHIFT 0 19227 19228 19229 /**************************************************************************** 19230 * Main0 :: speed_ctrl 19231 */ 19232 /* Main0 :: speed_ctrl :: reserved0 [15:09] */ 19233 #define MAIN0_SPEED_CTRL_RESERVED0_MASK 0xfe00 19234 #define MAIN0_SPEED_CTRL_RESERVED0_ALIGN 0 19235 #define MAIN0_SPEED_CTRL_RESERVED0_BITS 7 19236 #define MAIN0_SPEED_CTRL_RESERVED0_SHIFT 9 19237 19238 /* Main0 :: speed_ctrl :: pll_reset_en [08:08] */ 19239 #define MAIN0_SPEED_CTRL_PLL_RESET_EN_MASK 0x0100 19240 #define MAIN0_SPEED_CTRL_PLL_RESET_EN_ALIGN 0 19241 #define MAIN0_SPEED_CTRL_PLL_RESET_EN_BITS 1 19242 #define MAIN0_SPEED_CTRL_PLL_RESET_EN_SHIFT 8 19243 19244 /* Main0 :: speed_ctrl :: reserved1 [07:00] */ 19245 #define MAIN0_SPEED_CTRL_RESERVED1_MASK 0x00ff 19246 #define MAIN0_SPEED_CTRL_RESERVED1_ALIGN 0 19247 #define MAIN0_SPEED_CTRL_RESERVED1_BITS 8 19248 #define MAIN0_SPEED_CTRL_RESERVED1_SHIFT 0 19249 19250 19251 /**************************************************************************** 19252 * Main0 :: deviceInPkg5 19253 */ 19254 /* Main0 :: deviceInPkg5 :: reserved0 [15:08] */ 19255 #define MAIN0_DEVICEINPKG5_RESERVED0_MASK 0xff00 19256 #define MAIN0_DEVICEINPKG5_RESERVED0_ALIGN 0 19257 #define MAIN0_DEVICEINPKG5_RESERVED0_BITS 8 19258 #define MAIN0_DEVICEINPKG5_RESERVED0_SHIFT 8 19259 19260 /* Main0 :: deviceInPkg5 :: AN [07:07] */ 19261 #define MAIN0_DEVICEINPKG5_AN_MASK 0x0080 19262 #define MAIN0_DEVICEINPKG5_AN_ALIGN 0 19263 #define MAIN0_DEVICEINPKG5_AN_BITS 1 19264 #define MAIN0_DEVICEINPKG5_AN_SHIFT 7 19265 19266 /* Main0 :: deviceInPkg5 :: TC [06:06] */ 19267 #define MAIN0_DEVICEINPKG5_TC_MASK 0x0040 19268 #define MAIN0_DEVICEINPKG5_TC_ALIGN 0 19269 #define MAIN0_DEVICEINPKG5_TC_BITS 1 19270 #define MAIN0_DEVICEINPKG5_TC_SHIFT 6 19271 19272 /* Main0 :: deviceInPkg5 :: DTE_XS [05:05] */ 19273 #define MAIN0_DEVICEINPKG5_DTE_XS_MASK 0x0020 19274 #define MAIN0_DEVICEINPKG5_DTE_XS_ALIGN 0 19275 #define MAIN0_DEVICEINPKG5_DTE_XS_BITS 1 19276 #define MAIN0_DEVICEINPKG5_DTE_XS_SHIFT 5 19277 19278 /* Main0 :: deviceInPkg5 :: PHY_XS [04:04] */ 19279 #define MAIN0_DEVICEINPKG5_PHY_XS_MASK 0x0010 19280 #define MAIN0_DEVICEINPKG5_PHY_XS_ALIGN 0 19281 #define MAIN0_DEVICEINPKG5_PHY_XS_BITS 1 19282 #define MAIN0_DEVICEINPKG5_PHY_XS_SHIFT 4 19283 19284 /* Main0 :: deviceInPkg5 :: PCS_XS [03:03] */ 19285 #define MAIN0_DEVICEINPKG5_PCS_XS_MASK 0x0008 19286 #define MAIN0_DEVICEINPKG5_PCS_XS_ALIGN 0 19287 #define MAIN0_DEVICEINPKG5_PCS_XS_BITS 1 19288 #define MAIN0_DEVICEINPKG5_PCS_XS_SHIFT 3 19289 19290 /* Main0 :: deviceInPkg5 :: WIS [02:02] */ 19291 #define MAIN0_DEVICEINPKG5_WIS_MASK 0x0004 19292 #define MAIN0_DEVICEINPKG5_WIS_ALIGN 0 19293 #define MAIN0_DEVICEINPKG5_WIS_BITS 1 19294 #define MAIN0_DEVICEINPKG5_WIS_SHIFT 2 19295 19296 /* Main0 :: deviceInPkg5 :: PMA_PMD [01:01] */ 19297 #define MAIN0_DEVICEINPKG5_PMA_PMD_MASK 0x0002 19298 #define MAIN0_DEVICEINPKG5_PMA_PMD_ALIGN 0 19299 #define MAIN0_DEVICEINPKG5_PMA_PMD_BITS 1 19300 #define MAIN0_DEVICEINPKG5_PMA_PMD_SHIFT 1 19301 19302 /* Main0 :: deviceInPkg5 :: Clause22 [00:00] */ 19303 #define MAIN0_DEVICEINPKG5_CLAUSE22_MASK 0x0001 19304 #define MAIN0_DEVICEINPKG5_CLAUSE22_ALIGN 0 19305 #define MAIN0_DEVICEINPKG5_CLAUSE22_BITS 1 19306 #define MAIN0_DEVICEINPKG5_CLAUSE22_SHIFT 0 19307 19308 19309 /**************************************************************************** 19310 * Main0 :: tick_control_1 19311 */ 19312 /* Main0 :: tick_control_1 :: tick_override [15:15] */ 19313 #define MAIN0_TICK_CONTROL_1_TICK_OVERRIDE_MASK 0x8000 19314 #define MAIN0_TICK_CONTROL_1_TICK_OVERRIDE_ALIGN 0 19315 #define MAIN0_TICK_CONTROL_1_TICK_OVERRIDE_BITS 1 19316 #define MAIN0_TICK_CONTROL_1_TICK_OVERRIDE_SHIFT 15 19317 19318 /* Main0 :: tick_control_1 :: tick_numerator_upper [14:00] */ 19319 #define MAIN0_TICK_CONTROL_1_TICK_NUMERATOR_UPPER_MASK 0x7fff 19320 #define MAIN0_TICK_CONTROL_1_TICK_NUMERATOR_UPPER_ALIGN 0 19321 #define MAIN0_TICK_CONTROL_1_TICK_NUMERATOR_UPPER_BITS 15 19322 #define MAIN0_TICK_CONTROL_1_TICK_NUMERATOR_UPPER_SHIFT 0 19323 19324 19325 /**************************************************************************** 19326 * Main0 :: tick_control_0 19327 */ 19328 /* Main0 :: tick_control_0 :: tick_numerator_lower [15:12] */ 19329 #define MAIN0_TICK_CONTROL_0_TICK_NUMERATOR_LOWER_MASK 0xf000 19330 #define MAIN0_TICK_CONTROL_0_TICK_NUMERATOR_LOWER_ALIGN 0 19331 #define MAIN0_TICK_CONTROL_0_TICK_NUMERATOR_LOWER_BITS 4 19332 #define MAIN0_TICK_CONTROL_0_TICK_NUMERATOR_LOWER_SHIFT 12 19333 19334 /* Main0 :: tick_control_0 :: tick_denominator [11:02] */ 19335 #define MAIN0_TICK_CONTROL_0_TICK_DENOMINATOR_MASK 0x0ffc 19336 #define MAIN0_TICK_CONTROL_0_TICK_DENOMINATOR_ALIGN 0 19337 #define MAIN0_TICK_CONTROL_0_TICK_DENOMINATOR_BITS 10 19338 #define MAIN0_TICK_CONTROL_0_TICK_DENOMINATOR_SHIFT 2 19339 19340 /* Main0 :: tick_control_0 :: reserved0 [01:00] */ 19341 #define MAIN0_TICK_CONTROL_0_RESERVED0_MASK 0x0003 19342 #define MAIN0_TICK_CONTROL_0_RESERVED0_ALIGN 0 19343 #define MAIN0_TICK_CONTROL_0_RESERVED0_BITS 2 19344 #define MAIN0_TICK_CONTROL_0_RESERVED0_SHIFT 0 19345 19346 19347 /**************************************************************************** 19348 * Main0 :: serdesID 19349 */ 19350 /* Main0 :: serdesID :: rev_letter [15:14] */ 19351 #define MAIN0_SERDESID_REV_LETTER_MASK 0xc000 19352 #define MAIN0_SERDESID_REV_LETTER_ALIGN 0 19353 #define MAIN0_SERDESID_REV_LETTER_BITS 2 19354 #define MAIN0_SERDESID_REV_LETTER_SHIFT 14 19355 #define MAIN0_SERDESID_REV_LETTER_REV_A 0 19356 #define MAIN0_SERDESID_REV_LETTER_REV_B 1 19357 #define MAIN0_SERDESID_REV_LETTER_REV_C 2 19358 #define MAIN0_SERDESID_REV_LETTER_REV_D 3 19359 19360 /* Main0 :: serdesID :: rev_number [13:11] */ 19361 #define MAIN0_SERDESID_REV_NUMBER_MASK 0x3800 19362 #define MAIN0_SERDESID_REV_NUMBER_ALIGN 0 19363 #define MAIN0_SERDESID_REV_NUMBER_BITS 3 19364 #define MAIN0_SERDESID_REV_NUMBER_SHIFT 11 19365 #define MAIN0_SERDESID_REV_NUMBER_REV_0 0 19366 #define MAIN0_SERDESID_REV_NUMBER_REV_1 1 19367 #define MAIN0_SERDESID_REV_NUMBER_REV_2 2 19368 #define MAIN0_SERDESID_REV_NUMBER_REV_3 3 19369 #define MAIN0_SERDESID_REV_NUMBER_REV_4 4 19370 #define MAIN0_SERDESID_REV_NUMBER_REV_5 5 19371 #define MAIN0_SERDESID_REV_NUMBER_REV_6 6 19372 #define MAIN0_SERDESID_REV_NUMBER_REV_7 7 19373 19374 /* Main0 :: serdesID :: bonding [10:09] */ 19375 #define MAIN0_SERDESID_BONDING_MASK 0x0600 19376 #define MAIN0_SERDESID_BONDING_ALIGN 0 19377 #define MAIN0_SERDESID_BONDING_BITS 2 19378 #define MAIN0_SERDESID_BONDING_SHIFT 9 19379 #define MAIN0_SERDESID_BONDING_WIRE_BOND 0 19380 #define MAIN0_SERDESID_BONDING_FLIP_CHIP 1 19381 19382 /* Main0 :: serdesID :: tech_proc [08:06] */ 19383 #define MAIN0_SERDESID_TECH_PROC_MASK 0x01c0 19384 #define MAIN0_SERDESID_TECH_PROC_ALIGN 0 19385 #define MAIN0_SERDESID_TECH_PROC_BITS 3 19386 #define MAIN0_SERDESID_TECH_PROC_SHIFT 6 19387 #define MAIN0_SERDESID_TECH_PROC_PROCESS_90NM 0 19388 #define MAIN0_SERDESID_TECH_PROC_PROCESS_65NM 1 19389 #define MAIN0_SERDESID_TECH_PROC_PROCESS_40NM 2 19390 #define MAIN0_SERDESID_TECH_PROC_PROCESS_28NM 3 19391 #define MAIN0_SERDESID_TECH_PROC_PROCESS_16NM 4 19392 19393 /* Main0 :: serdesID :: model_number [05:00] */ 19394 #define MAIN0_SERDESID_MODEL_NUMBER_MASK 0x003f 19395 #define MAIN0_SERDESID_MODEL_NUMBER_ALIGN 0 19396 #define MAIN0_SERDESID_MODEL_NUMBER_BITS 6 19397 #define MAIN0_SERDESID_MODEL_NUMBER_SHIFT 0 19398 #define MAIN0_SERDESID_MODEL_NUMBER_SERDES_CL73 0 19399 #define MAIN0_SERDESID_MODEL_NUMBER_XGXS_16G 1 19400 #define MAIN0_SERDESID_MODEL_NUMBER_HYPERCORE 2 19401 #define MAIN0_SERDESID_MODEL_NUMBER_HYPERLITE 3 19402 #define MAIN0_SERDESID_MODEL_NUMBER_PCIE_G2_PIPE 4 19403 #define MAIN0_SERDESID_MODEL_NUMBER_SERDES_1p25GBd 5 19404 #define MAIN0_SERDESID_MODEL_NUMBER_SATA2 6 19405 #define MAIN0_SERDESID_MODEL_NUMBER_QSGMII 7 19406 #define MAIN0_SERDESID_MODEL_NUMBER_XGXS10G 8 19407 #define MAIN0_SERDESID_MODEL_NUMBER_WARPCORE 9 19408 #define MAIN0_SERDESID_MODEL_NUMBER_XFICORE 10 19409 #define MAIN0_SERDESID_MODEL_NUMBER_RXFI 11 19410 #define MAIN0_SERDESID_MODEL_NUMBER_WARPLITE 12 19411 #define MAIN0_SERDESID_MODEL_NUMBER_PENTACORE 13 19412 #define MAIN0_SERDESID_MODEL_NUMBER_ESM 14 19413 #define MAIN0_SERDESID_MODEL_NUMBER_QUAD_SGMII 15 19414 #define MAIN0_SERDESID_MODEL_NUMBER_WARPCORE_3 16 19415 #define MAIN0_SERDESID_MODEL_NUMBER_TSC 17 19416 #define MAIN0_SERDESID_MODEL_NUMBER_TSC4E 18 19417 #define MAIN0_SERDESID_MODEL_NUMBER_TSC12E 19 19418 #define MAIN0_SERDESID_MODEL_NUMBER_TSC4F 20 19419 #define MAIN0_SERDESID_MODEL_NUMBER_TSC4F_GEN2 21 19420 #define MAIN0_SERDESID_MODEL_NUMBER_XGXS_CL73_90NM 29 19421 #define MAIN0_SERDESID_MODEL_NUMBER_SERDES_CL73_90NM 30 19422 #define MAIN0_SERDESID_MODEL_NUMBER_WARPCORE3 32 19423 #define MAIN0_SERDESID_MODEL_NUMBER_WARPCORE4_TSC 33 19424 #define MAIN0_SERDESID_MODEL_NUMBER_RXAUI 34 19425 #define MAIN0_SERDESID_MODEL_NUMBER_TSCE_GEN3 35 19426 #define MAIN0_SERDESID_MODEL_NUMBER_TSC4F_GEN3 36 19427 #define MAIN0_SERDESID_MODEL_NUMBER_TSCBH 37 19428 19429 19430 /**************************************************************************** 19431 * TSC_TSC_USER1_pmd_x1 19432 */ 19433 /**************************************************************************** 19434 * pmd_x1 :: control 19435 */ 19436 /* pmd_x1 :: control :: reserved0 [15:15] */ 19437 #define PMD_X1_CONTROL_RESERVED0_MASK 0x8000 19438 #define PMD_X1_CONTROL_RESERVED0_ALIGN 0 19439 #define PMD_X1_CONTROL_RESERVED0_BITS 1 19440 #define PMD_X1_CONTROL_RESERVED0_SHIFT 15 19441 19442 /* pmd_x1 :: control :: core_mode_spare [14:09] */ 19443 #define PMD_X1_CONTROL_CORE_MODE_SPARE_MASK 0x7e00 19444 #define PMD_X1_CONTROL_CORE_MODE_SPARE_ALIGN 0 19445 #define PMD_X1_CONTROL_CORE_MODE_SPARE_BITS 6 19446 #define PMD_X1_CONTROL_CORE_MODE_SPARE_SHIFT 9 19447 19448 /* pmd_x1 :: control :: core_mode_speed_id [08:03] */ 19449 #define PMD_X1_CONTROL_CORE_MODE_SPEED_ID_MASK 0x01f8 19450 #define PMD_X1_CONTROL_CORE_MODE_SPEED_ID_ALIGN 0 19451 #define PMD_X1_CONTROL_CORE_MODE_SPEED_ID_BITS 6 19452 #define PMD_X1_CONTROL_CORE_MODE_SPEED_ID_SHIFT 3 19453 19454 /* pmd_x1 :: control :: por_h_rstb [02:02] */ 19455 #define PMD_X1_CONTROL_POR_H_RSTB_MASK 0x0004 19456 #define PMD_X1_CONTROL_POR_H_RSTB_ALIGN 0 19457 #define PMD_X1_CONTROL_POR_H_RSTB_BITS 1 19458 #define PMD_X1_CONTROL_POR_H_RSTB_SHIFT 2 19459 19460 /* pmd_x1 :: control :: core_dp_h_rstb [01:01] */ 19461 #define PMD_X1_CONTROL_CORE_DP_H_RSTB_MASK 0x0002 19462 #define PMD_X1_CONTROL_CORE_DP_H_RSTB_ALIGN 0 19463 #define PMD_X1_CONTROL_CORE_DP_H_RSTB_BITS 1 19464 #define PMD_X1_CONTROL_CORE_DP_H_RSTB_SHIFT 1 19465 19466 /* pmd_x1 :: control :: core_dp_h_rstb_oen [00:00] */ 19467 #define PMD_X1_CONTROL_CORE_DP_H_RSTB_OEN_MASK 0x0001 19468 #define PMD_X1_CONTROL_CORE_DP_H_RSTB_OEN_ALIGN 0 19469 #define PMD_X1_CONTROL_CORE_DP_H_RSTB_OEN_BITS 1 19470 #define PMD_X1_CONTROL_CORE_DP_H_RSTB_OEN_SHIFT 0 19471 19472 19473 /**************************************************************************** 19474 * pmd_x1 :: pm_timer_offset 19475 */ 19476 /* pmd_x1 :: pm_timer_offset :: PM_offset_in_ns [15:08] */ 19477 #define PMD_X1_PM_TIMER_OFFSET_PM_OFFSET_IN_NS_MASK 0xff00 19478 #define PMD_X1_PM_TIMER_OFFSET_PM_OFFSET_IN_NS_ALIGN 0 19479 #define PMD_X1_PM_TIMER_OFFSET_PM_OFFSET_IN_NS_BITS 8 19480 #define PMD_X1_PM_TIMER_OFFSET_PM_OFFSET_IN_NS_SHIFT 8 19481 19482 /* pmd_x1 :: pm_timer_offset :: PM_offset_sub_ns [07:00] */ 19483 #define PMD_X1_PM_TIMER_OFFSET_PM_OFFSET_SUB_NS_MASK 0x00ff 19484 #define PMD_X1_PM_TIMER_OFFSET_PM_OFFSET_SUB_NS_ALIGN 0 19485 #define PMD_X1_PM_TIMER_OFFSET_PM_OFFSET_SUB_NS_BITS 8 19486 #define PMD_X1_PM_TIMER_OFFSET_PM_OFFSET_SUB_NS_SHIFT 0 19487 19488 19489 /**************************************************************************** 19490 * pmd_x1 :: fclk_period 19491 */ 19492 /* pmd_x1 :: fclk_period :: fclk_frac_ns [15:00] */ 19493 #define PMD_X1_FCLK_PERIOD_FCLK_FRAC_NS_MASK 0xffff 19494 #define PMD_X1_FCLK_PERIOD_FCLK_FRAC_NS_ALIGN 0 19495 #define PMD_X1_FCLK_PERIOD_FCLK_FRAC_NS_BITS 16 19496 #define PMD_X1_FCLK_PERIOD_FCLK_FRAC_NS_SHIFT 0 19497 19498 19499 /**************************************************************************** 19500 * TSC_TSC_USER1_PktGen0 19501 */ 19502 /**************************************************************************** 19503 * PktGen0 :: PktGenCtrl1 19504 */ 19505 /* PktGen0 :: PktGenCtrl1 :: reserved0 [15:09] */ 19506 #define PKTGEN0_PKTGENCTRL1_RESERVED0_MASK 0xfe00 19507 #define PKTGEN0_PKTGENCTRL1_RESERVED0_ALIGN 0 19508 #define PKTGEN0_PKTGENCTRL1_RESERVED0_BITS 7 19509 #define PKTGEN0_PKTGENCTRL1_RESERVED0_SHIFT 9 19510 19511 /* PktGen0 :: PktGenCtrl1 :: rx_port_sel [08:07] */ 19512 #define PKTGEN0_PKTGENCTRL1_RX_PORT_SEL_MASK 0x0180 19513 #define PKTGEN0_PKTGENCTRL1_RX_PORT_SEL_ALIGN 0 19514 #define PKTGEN0_PKTGENCTRL1_RX_PORT_SEL_BITS 2 19515 #define PKTGEN0_PKTGENCTRL1_RX_PORT_SEL_SHIFT 7 19516 19517 /* PktGen0 :: PktGenCtrl1 :: prtp_data_pattern_sel [06:03] */ 19518 #define PKTGEN0_PKTGENCTRL1_PRTP_DATA_PATTERN_SEL_MASK 0x0078 19519 #define PKTGEN0_PKTGENCTRL1_PRTP_DATA_PATTERN_SEL_ALIGN 0 19520 #define PKTGEN0_PKTGENCTRL1_PRTP_DATA_PATTERN_SEL_BITS 4 19521 #define PKTGEN0_PKTGENCTRL1_PRTP_DATA_PATTERN_SEL_SHIFT 3 19522 19523 /* PktGen0 :: PktGenCtrl1 :: reserved1 [02:02] */ 19524 #define PKTGEN0_PKTGENCTRL1_RESERVED1_MASK 0x0004 19525 #define PKTGEN0_PKTGENCTRL1_RESERVED1_ALIGN 0 19526 #define PKTGEN0_PKTGENCTRL1_RESERVED1_BITS 1 19527 #define PKTGEN0_PKTGENCTRL1_RESERVED1_SHIFT 2 19528 19529 /* PktGen0 :: PktGenCtrl1 :: tx_test_port_sel [01:00] */ 19530 #define PKTGEN0_PKTGENCTRL1_TX_TEST_PORT_SEL_MASK 0x0003 19531 #define PKTGEN0_PKTGENCTRL1_TX_TEST_PORT_SEL_ALIGN 0 19532 #define PKTGEN0_PKTGENCTRL1_TX_TEST_PORT_SEL_BITS 2 19533 #define PKTGEN0_PKTGENCTRL1_TX_TEST_PORT_SEL_SHIFT 0 19534 19535 19536 /**************************************************************************** 19537 * PktGen0 :: PrtpControl 19538 */ 19539 /* PktGen0 :: PrtpControl :: tx_prtp_en [15:12] */ 19540 #define PKTGEN0_PRTPCONTROL_TX_PRTP_EN_MASK 0xf000 19541 #define PKTGEN0_PRTPCONTROL_TX_PRTP_EN_ALIGN 0 19542 #define PKTGEN0_PRTPCONTROL_TX_PRTP_EN_BITS 4 19543 #define PKTGEN0_PRTPCONTROL_TX_PRTP_EN_SHIFT 12 19544 19545 /* PktGen0 :: PrtpControl :: rx_prtp_en [11:08] */ 19546 #define PKTGEN0_PRTPCONTROL_RX_PRTP_EN_MASK 0x0f00 19547 #define PKTGEN0_PRTPCONTROL_RX_PRTP_EN_ALIGN 0 19548 #define PKTGEN0_PRTPCONTROL_RX_PRTP_EN_BITS 4 19549 #define PKTGEN0_PRTPCONTROL_RX_PRTP_EN_SHIFT 8 19550 19551 /* PktGen0 :: PrtpControl :: reserved0 [07:00] */ 19552 #define PKTGEN0_PRTPCONTROL_RESERVED0_MASK 0x00ff 19553 #define PKTGEN0_PRTPCONTROL_RESERVED0_ALIGN 0 19554 #define PKTGEN0_PRTPCONTROL_RESERVED0_BITS 8 19555 #define PKTGEN0_PRTPCONTROL_RESERVED0_SHIFT 0 19556 19557 19558 /**************************************************************************** 19559 * PktGen0 :: PCS_seedA0 19560 */ 19561 /* PktGen0 :: PCS_seedA0 :: seedA0 [15:00] */ 19562 #define PKTGEN0_PCS_SEEDA0_SEEDA0_MASK 0xffff 19563 #define PKTGEN0_PCS_SEEDA0_SEEDA0_ALIGN 0 19564 #define PKTGEN0_PCS_SEEDA0_SEEDA0_BITS 16 19565 #define PKTGEN0_PCS_SEEDA0_SEEDA0_SHIFT 0 19566 19567 19568 /**************************************************************************** 19569 * PktGen0 :: PCS_seedA1 19570 */ 19571 /* PktGen0 :: PCS_seedA1 :: seedA1 [15:00] */ 19572 #define PKTGEN0_PCS_SEEDA1_SEEDA1_MASK 0xffff 19573 #define PKTGEN0_PCS_SEEDA1_SEEDA1_ALIGN 0 19574 #define PKTGEN0_PCS_SEEDA1_SEEDA1_BITS 16 19575 #define PKTGEN0_PCS_SEEDA1_SEEDA1_SHIFT 0 19576 19577 19578 /**************************************************************************** 19579 * PktGen0 :: PCS_seedA2 19580 */ 19581 /* PktGen0 :: PCS_seedA2 :: seedA2 [15:00] */ 19582 #define PKTGEN0_PCS_SEEDA2_SEEDA2_MASK 0xffff 19583 #define PKTGEN0_PCS_SEEDA2_SEEDA2_ALIGN 0 19584 #define PKTGEN0_PCS_SEEDA2_SEEDA2_BITS 16 19585 #define PKTGEN0_PCS_SEEDA2_SEEDA2_SHIFT 0 19586 19587 19588 /**************************************************************************** 19589 * PktGen0 :: PCS_seedA3 19590 */ 19591 /* PktGen0 :: PCS_seedA3 :: reserved0 [15:10] */ 19592 #define PKTGEN0_PCS_SEEDA3_RESERVED0_MASK 0xfc00 19593 #define PKTGEN0_PCS_SEEDA3_RESERVED0_ALIGN 0 19594 #define PKTGEN0_PCS_SEEDA3_RESERVED0_BITS 6 19595 #define PKTGEN0_PCS_SEEDA3_RESERVED0_SHIFT 10 19596 19597 /* PktGen0 :: PCS_seedA3 :: seedA3 [09:00] */ 19598 #define PKTGEN0_PCS_SEEDA3_SEEDA3_MASK 0x03ff 19599 #define PKTGEN0_PCS_SEEDA3_SEEDA3_ALIGN 0 19600 #define PKTGEN0_PCS_SEEDA3_SEEDA3_BITS 10 19601 #define PKTGEN0_PCS_SEEDA3_SEEDA3_SHIFT 0 19602 19603 19604 /**************************************************************************** 19605 * PktGen0 :: PCS_seedB0 19606 */ 19607 /* PktGen0 :: PCS_seedB0 :: seedB0 [15:00] */ 19608 #define PKTGEN0_PCS_SEEDB0_SEEDB0_MASK 0xffff 19609 #define PKTGEN0_PCS_SEEDB0_SEEDB0_ALIGN 0 19610 #define PKTGEN0_PCS_SEEDB0_SEEDB0_BITS 16 19611 #define PKTGEN0_PCS_SEEDB0_SEEDB0_SHIFT 0 19612 19613 19614 /**************************************************************************** 19615 * PktGen0 :: PCS_seedB1 19616 */ 19617 /* PktGen0 :: PCS_seedB1 :: seedB1 [15:00] */ 19618 #define PKTGEN0_PCS_SEEDB1_SEEDB1_MASK 0xffff 19619 #define PKTGEN0_PCS_SEEDB1_SEEDB1_ALIGN 0 19620 #define PKTGEN0_PCS_SEEDB1_SEEDB1_BITS 16 19621 #define PKTGEN0_PCS_SEEDB1_SEEDB1_SHIFT 0 19622 19623 19624 /**************************************************************************** 19625 * PktGen0 :: PCS_seedB2 19626 */ 19627 /* PktGen0 :: PCS_seedB2 :: seedB2 [15:00] */ 19628 #define PKTGEN0_PCS_SEEDB2_SEEDB2_MASK 0xffff 19629 #define PKTGEN0_PCS_SEEDB2_SEEDB2_ALIGN 0 19630 #define PKTGEN0_PCS_SEEDB2_SEEDB2_BITS 16 19631 #define PKTGEN0_PCS_SEEDB2_SEEDB2_SHIFT 0 19632 19633 19634 /**************************************************************************** 19635 * PktGen0 :: PCS_seedB3 19636 */ 19637 /* PktGen0 :: PCS_seedB3 :: reserved0 [15:10] */ 19638 #define PKTGEN0_PCS_SEEDB3_RESERVED0_MASK 0xfc00 19639 #define PKTGEN0_PCS_SEEDB3_RESERVED0_ALIGN 0 19640 #define PKTGEN0_PCS_SEEDB3_RESERVED0_BITS 6 19641 #define PKTGEN0_PCS_SEEDB3_RESERVED0_SHIFT 10 19642 19643 /* PktGen0 :: PCS_seedB3 :: seedB3 [09:00] */ 19644 #define PKTGEN0_PCS_SEEDB3_SEEDB3_MASK 0x03ff 19645 #define PKTGEN0_PCS_SEEDB3_SEEDB3_ALIGN 0 19646 #define PKTGEN0_PCS_SEEDB3_SEEDB3_BITS 10 19647 #define PKTGEN0_PCS_SEEDB3_SEEDB3_SHIFT 0 19648 19649 19650 /**************************************************************************** 19651 * TSC_TSC_USER1_PktGen1 19652 */ 19653 /**************************************************************************** 19654 * PktGen1 :: ErrorMask4 19655 */ 19656 /* PktGen1 :: ErrorMask4 :: reserved0 [15:02] */ 19657 #define PKTGEN1_ERRORMASK4_RESERVED0_MASK 0xfffc 19658 #define PKTGEN1_ERRORMASK4_RESERVED0_ALIGN 0 19659 #define PKTGEN1_ERRORMASK4_RESERVED0_BITS 14 19660 #define PKTGEN1_ERRORMASK4_RESERVED0_SHIFT 2 19661 19662 /* PktGen1 :: ErrorMask4 :: error_mask_65_64 [01:00] */ 19663 #define PKTGEN1_ERRORMASK4_ERROR_MASK_65_64_MASK 0x0003 19664 #define PKTGEN1_ERRORMASK4_ERROR_MASK_65_64_ALIGN 0 19665 #define PKTGEN1_ERRORMASK4_ERROR_MASK_65_64_BITS 2 19666 #define PKTGEN1_ERRORMASK4_ERROR_MASK_65_64_SHIFT 0 19667 19668 19669 /**************************************************************************** 19670 * PktGen1 :: ErrorMask3 19671 */ 19672 /* PktGen1 :: ErrorMask3 :: error_mask_63_48 [15:00] */ 19673 #define PKTGEN1_ERRORMASK3_ERROR_MASK_63_48_MASK 0xffff 19674 #define PKTGEN1_ERRORMASK3_ERROR_MASK_63_48_ALIGN 0 19675 #define PKTGEN1_ERRORMASK3_ERROR_MASK_63_48_BITS 16 19676 #define PKTGEN1_ERRORMASK3_ERROR_MASK_63_48_SHIFT 0 19677 19678 19679 /**************************************************************************** 19680 * PktGen1 :: ErrorMask2 19681 */ 19682 /* PktGen1 :: ErrorMask2 :: error_mask_47_32 [15:00] */ 19683 #define PKTGEN1_ERRORMASK2_ERROR_MASK_47_32_MASK 0xffff 19684 #define PKTGEN1_ERRORMASK2_ERROR_MASK_47_32_ALIGN 0 19685 #define PKTGEN1_ERRORMASK2_ERROR_MASK_47_32_BITS 16 19686 #define PKTGEN1_ERRORMASK2_ERROR_MASK_47_32_SHIFT 0 19687 19688 19689 /**************************************************************************** 19690 * PktGen1 :: ErrorMask1 19691 */ 19692 /* PktGen1 :: ErrorMask1 :: error_mask_31_16 [15:00] */ 19693 #define PKTGEN1_ERRORMASK1_ERROR_MASK_31_16_MASK 0xffff 19694 #define PKTGEN1_ERRORMASK1_ERROR_MASK_31_16_ALIGN 0 19695 #define PKTGEN1_ERRORMASK1_ERROR_MASK_31_16_BITS 16 19696 #define PKTGEN1_ERRORMASK1_ERROR_MASK_31_16_SHIFT 0 19697 19698 19699 /**************************************************************************** 19700 * PktGen1 :: ErrorMask0 19701 */ 19702 /* PktGen1 :: ErrorMask0 :: error_mask_15_0 [15:00] */ 19703 #define PKTGEN1_ERRORMASK0_ERROR_MASK_15_0_MASK 0xffff 19704 #define PKTGEN1_ERRORMASK0_ERROR_MASK_15_0_ALIGN 0 19705 #define PKTGEN1_ERRORMASK0_ERROR_MASK_15_0_BITS 16 19706 #define PKTGEN1_ERRORMASK0_ERROR_MASK_15_0_SHIFT 0 19707 19708 19709 /**************************************************************************** 19710 * PktGen1 :: Err_inj_en0 19711 */ 19712 /* PktGen1 :: Err_inj_en0 :: reserved0 [15:15] */ 19713 #define PKTGEN1_ERR_INJ_EN0_RESERVED0_MASK 0x8000 19714 #define PKTGEN1_ERR_INJ_EN0_RESERVED0_ALIGN 0 19715 #define PKTGEN1_ERR_INJ_EN0_RESERVED0_BITS 1 19716 #define PKTGEN1_ERR_INJ_EN0_RESERVED0_SHIFT 15 19717 19718 /* PktGen1 :: Err_inj_en0 :: errgen_en_ph2 [14:10] */ 19719 #define PKTGEN1_ERR_INJ_EN0_ERRGEN_EN_PH2_MASK 0x7c00 19720 #define PKTGEN1_ERR_INJ_EN0_ERRGEN_EN_PH2_ALIGN 0 19721 #define PKTGEN1_ERR_INJ_EN0_ERRGEN_EN_PH2_BITS 5 19722 #define PKTGEN1_ERR_INJ_EN0_ERRGEN_EN_PH2_SHIFT 10 19723 19724 /* PktGen1 :: Err_inj_en0 :: errgen_en_ph1 [09:05] */ 19725 #define PKTGEN1_ERR_INJ_EN0_ERRGEN_EN_PH1_MASK 0x03e0 19726 #define PKTGEN1_ERR_INJ_EN0_ERRGEN_EN_PH1_ALIGN 0 19727 #define PKTGEN1_ERR_INJ_EN0_ERRGEN_EN_PH1_BITS 5 19728 #define PKTGEN1_ERR_INJ_EN0_ERRGEN_EN_PH1_SHIFT 5 19729 19730 /* PktGen1 :: Err_inj_en0 :: errgen_en_ph0 [04:00] */ 19731 #define PKTGEN1_ERR_INJ_EN0_ERRGEN_EN_PH0_MASK 0x001f 19732 #define PKTGEN1_ERR_INJ_EN0_ERRGEN_EN_PH0_ALIGN 0 19733 #define PKTGEN1_ERR_INJ_EN0_ERRGEN_EN_PH0_BITS 5 19734 #define PKTGEN1_ERR_INJ_EN0_ERRGEN_EN_PH0_SHIFT 0 19735 19736 19737 /**************************************************************************** 19738 * PktGen1 :: Err_inj_en1 19739 */ 19740 /* PktGen1 :: Err_inj_en1 :: reserved0 [15:13] */ 19741 #define PKTGEN1_ERR_INJ_EN1_RESERVED0_MASK 0xe000 19742 #define PKTGEN1_ERR_INJ_EN1_RESERVED0_ALIGN 0 19743 #define PKTGEN1_ERR_INJ_EN1_RESERVED0_BITS 3 19744 #define PKTGEN1_ERR_INJ_EN1_RESERVED0_SHIFT 13 19745 19746 /* PktGen1 :: Err_inj_en1 :: RS_FEC_80b_errgen_en_p3 [12:12] */ 19747 #define PKTGEN1_ERR_INJ_EN1_RS_FEC_80B_ERRGEN_EN_P3_MASK 0x1000 19748 #define PKTGEN1_ERR_INJ_EN1_RS_FEC_80B_ERRGEN_EN_P3_ALIGN 0 19749 #define PKTGEN1_ERR_INJ_EN1_RS_FEC_80B_ERRGEN_EN_P3_BITS 1 19750 #define PKTGEN1_ERR_INJ_EN1_RS_FEC_80B_ERRGEN_EN_P3_SHIFT 12 19751 19752 /* PktGen1 :: Err_inj_en1 :: RS_FEC_80b_errgen_en_p2 [11:11] */ 19753 #define PKTGEN1_ERR_INJ_EN1_RS_FEC_80B_ERRGEN_EN_P2_MASK 0x0800 19754 #define PKTGEN1_ERR_INJ_EN1_RS_FEC_80B_ERRGEN_EN_P2_ALIGN 0 19755 #define PKTGEN1_ERR_INJ_EN1_RS_FEC_80B_ERRGEN_EN_P2_BITS 1 19756 #define PKTGEN1_ERR_INJ_EN1_RS_FEC_80B_ERRGEN_EN_P2_SHIFT 11 19757 19758 /* PktGen1 :: Err_inj_en1 :: RS_FEC_80b_errgen_en_p1 [10:10] */ 19759 #define PKTGEN1_ERR_INJ_EN1_RS_FEC_80B_ERRGEN_EN_P1_MASK 0x0400 19760 #define PKTGEN1_ERR_INJ_EN1_RS_FEC_80B_ERRGEN_EN_P1_ALIGN 0 19761 #define PKTGEN1_ERR_INJ_EN1_RS_FEC_80B_ERRGEN_EN_P1_BITS 1 19762 #define PKTGEN1_ERR_INJ_EN1_RS_FEC_80B_ERRGEN_EN_P1_SHIFT 10 19763 19764 /* PktGen1 :: Err_inj_en1 :: RS_FEC_80b_errgen_en_p0 [09:09] */ 19765 #define PKTGEN1_ERR_INJ_EN1_RS_FEC_80B_ERRGEN_EN_P0_MASK 0x0200 19766 #define PKTGEN1_ERR_INJ_EN1_RS_FEC_80B_ERRGEN_EN_P0_ALIGN 0 19767 #define PKTGEN1_ERR_INJ_EN1_RS_FEC_80B_ERRGEN_EN_P0_BITS 1 19768 #define PKTGEN1_ERR_INJ_EN1_RS_FEC_80B_ERRGEN_EN_P0_SHIFT 9 19769 19770 /* PktGen1 :: Err_inj_en1 :: RS_FEC_40b_errgen_en_p3 [08:08] */ 19771 #define PKTGEN1_ERR_INJ_EN1_RS_FEC_40B_ERRGEN_EN_P3_MASK 0x0100 19772 #define PKTGEN1_ERR_INJ_EN1_RS_FEC_40B_ERRGEN_EN_P3_ALIGN 0 19773 #define PKTGEN1_ERR_INJ_EN1_RS_FEC_40B_ERRGEN_EN_P3_BITS 1 19774 #define PKTGEN1_ERR_INJ_EN1_RS_FEC_40B_ERRGEN_EN_P3_SHIFT 8 19775 19776 /* PktGen1 :: Err_inj_en1 :: RS_FEC_40b_errgen_en_p2 [07:07] */ 19777 #define PKTGEN1_ERR_INJ_EN1_RS_FEC_40B_ERRGEN_EN_P2_MASK 0x0080 19778 #define PKTGEN1_ERR_INJ_EN1_RS_FEC_40B_ERRGEN_EN_P2_ALIGN 0 19779 #define PKTGEN1_ERR_INJ_EN1_RS_FEC_40B_ERRGEN_EN_P2_BITS 1 19780 #define PKTGEN1_ERR_INJ_EN1_RS_FEC_40B_ERRGEN_EN_P2_SHIFT 7 19781 19782 /* PktGen1 :: Err_inj_en1 :: RS_FEC_40b_errgen_en_p1 [06:06] */ 19783 #define PKTGEN1_ERR_INJ_EN1_RS_FEC_40B_ERRGEN_EN_P1_MASK 0x0040 19784 #define PKTGEN1_ERR_INJ_EN1_RS_FEC_40B_ERRGEN_EN_P1_ALIGN 0 19785 #define PKTGEN1_ERR_INJ_EN1_RS_FEC_40B_ERRGEN_EN_P1_BITS 1 19786 #define PKTGEN1_ERR_INJ_EN1_RS_FEC_40B_ERRGEN_EN_P1_SHIFT 6 19787 19788 /* PktGen1 :: Err_inj_en1 :: RS_FEC_40b_errgen_en_p0 [05:05] */ 19789 #define PKTGEN1_ERR_INJ_EN1_RS_FEC_40B_ERRGEN_EN_P0_MASK 0x0020 19790 #define PKTGEN1_ERR_INJ_EN1_RS_FEC_40B_ERRGEN_EN_P0_ALIGN 0 19791 #define PKTGEN1_ERR_INJ_EN1_RS_FEC_40B_ERRGEN_EN_P0_BITS 1 19792 #define PKTGEN1_ERR_INJ_EN1_RS_FEC_40B_ERRGEN_EN_P0_SHIFT 5 19793 19794 /* PktGen1 :: Err_inj_en1 :: errgen_en_ph3 [04:00] */ 19795 #define PKTGEN1_ERR_INJ_EN1_ERRGEN_EN_PH3_MASK 0x001f 19796 #define PKTGEN1_ERR_INJ_EN1_ERRGEN_EN_PH3_ALIGN 0 19797 #define PKTGEN1_ERR_INJ_EN1_ERRGEN_EN_PH3_BITS 5 19798 #define PKTGEN1_ERR_INJ_EN1_ERRGEN_EN_PH3_SHIFT 0 19799 19800 19801 /**************************************************************************** 19802 * TSC_TSC_USER1_TX_X1_Control0 19803 */ 19804 /**************************************************************************** 19805 * TX_X1_Control0 :: tx_lane_swap 19806 */ 19807 /* TX_X1_Control0 :: tx_lane_swap :: reserved0 [15:12] */ 19808 #define TX_X1_CONTROL0_TX_LANE_SWAP_RESERVED0_MASK 0xf000 19809 #define TX_X1_CONTROL0_TX_LANE_SWAP_RESERVED0_ALIGN 0 19810 #define TX_X1_CONTROL0_TX_LANE_SWAP_RESERVED0_BITS 4 19811 #define TX_X1_CONTROL0_TX_LANE_SWAP_RESERVED0_SHIFT 12 19812 19813 /* TX_X1_Control0 :: tx_lane_swap :: logical_to_physical3_sel [11:09] */ 19814 #define TX_X1_CONTROL0_TX_LANE_SWAP_LOGICAL_TO_PHYSICAL3_SEL_MASK 0x0e00 19815 #define TX_X1_CONTROL0_TX_LANE_SWAP_LOGICAL_TO_PHYSICAL3_SEL_ALIGN 0 19816 #define TX_X1_CONTROL0_TX_LANE_SWAP_LOGICAL_TO_PHYSICAL3_SEL_BITS 3 19817 #define TX_X1_CONTROL0_TX_LANE_SWAP_LOGICAL_TO_PHYSICAL3_SEL_SHIFT 9 19818 19819 /* TX_X1_Control0 :: tx_lane_swap :: logical_to_physical2_sel [08:06] */ 19820 #define TX_X1_CONTROL0_TX_LANE_SWAP_LOGICAL_TO_PHYSICAL2_SEL_MASK 0x01c0 19821 #define TX_X1_CONTROL0_TX_LANE_SWAP_LOGICAL_TO_PHYSICAL2_SEL_ALIGN 0 19822 #define TX_X1_CONTROL0_TX_LANE_SWAP_LOGICAL_TO_PHYSICAL2_SEL_BITS 3 19823 #define TX_X1_CONTROL0_TX_LANE_SWAP_LOGICAL_TO_PHYSICAL2_SEL_SHIFT 6 19824 19825 /* TX_X1_Control0 :: tx_lane_swap :: logical_to_physical1_sel [05:03] */ 19826 #define TX_X1_CONTROL0_TX_LANE_SWAP_LOGICAL_TO_PHYSICAL1_SEL_MASK 0x0038 19827 #define TX_X1_CONTROL0_TX_LANE_SWAP_LOGICAL_TO_PHYSICAL1_SEL_ALIGN 0 19828 #define TX_X1_CONTROL0_TX_LANE_SWAP_LOGICAL_TO_PHYSICAL1_SEL_BITS 3 19829 #define TX_X1_CONTROL0_TX_LANE_SWAP_LOGICAL_TO_PHYSICAL1_SEL_SHIFT 3 19830 19831 /* TX_X1_Control0 :: tx_lane_swap :: logical_to_physical0_sel [02:00] */ 19832 #define TX_X1_CONTROL0_TX_LANE_SWAP_LOGICAL_TO_PHYSICAL0_SEL_MASK 0x0007 19833 #define TX_X1_CONTROL0_TX_LANE_SWAP_LOGICAL_TO_PHYSICAL0_SEL_ALIGN 0 19834 #define TX_X1_CONTROL0_TX_LANE_SWAP_LOGICAL_TO_PHYSICAL0_SEL_BITS 3 19835 #define TX_X1_CONTROL0_TX_LANE_SWAP_LOGICAL_TO_PHYSICAL0_SEL_SHIFT 0 19836 19837 19838 /**************************************************************************** 19839 * TX_X1_Control0 :: glas_tpma_control 19840 */ 19841 /* TX_X1_Control0 :: glas_tpma_control :: reserved0 [15:10] */ 19842 #define TX_X1_CONTROL0_GLAS_TPMA_CONTROL_RESERVED0_MASK 0xfc00 19843 #define TX_X1_CONTROL0_GLAS_TPMA_CONTROL_RESERVED0_ALIGN 0 19844 #define TX_X1_CONTROL0_GLAS_TPMA_CONTROL_RESERVED0_BITS 6 19845 #define TX_X1_CONTROL0_GLAS_TPMA_CONTROL_RESERVED0_SHIFT 10 19846 19847 /* TX_X1_Control0 :: glas_tpma_control :: glas_tpma_capture_logical [09:09] */ 19848 #define TX_X1_CONTROL0_GLAS_TPMA_CONTROL_GLAS_TPMA_CAPTURE_LOGICAL_MASK 0x0200 19849 #define TX_X1_CONTROL0_GLAS_TPMA_CONTROL_GLAS_TPMA_CAPTURE_LOGICAL_ALIGN 0 19850 #define TX_X1_CONTROL0_GLAS_TPMA_CONTROL_GLAS_TPMA_CAPTURE_LOGICAL_BITS 1 19851 #define TX_X1_CONTROL0_GLAS_TPMA_CONTROL_GLAS_TPMA_CAPTURE_LOGICAL_SHIFT 9 19852 19853 /* TX_X1_Control0 :: glas_tpma_control :: glas_tpma_capture_mask [08:01] */ 19854 #define TX_X1_CONTROL0_GLAS_TPMA_CONTROL_GLAS_TPMA_CAPTURE_MASK_MASK 0x01fe 19855 #define TX_X1_CONTROL0_GLAS_TPMA_CONTROL_GLAS_TPMA_CAPTURE_MASK_ALIGN 0 19856 #define TX_X1_CONTROL0_GLAS_TPMA_CONTROL_GLAS_TPMA_CAPTURE_MASK_BITS 8 19857 #define TX_X1_CONTROL0_GLAS_TPMA_CONTROL_GLAS_TPMA_CAPTURE_MASK_SHIFT 1 19858 19859 /* TX_X1_Control0 :: glas_tpma_control :: glas_tpma_capture_en [00:00] */ 19860 #define TX_X1_CONTROL0_GLAS_TPMA_CONTROL_GLAS_TPMA_CAPTURE_EN_MASK 0x0001 19861 #define TX_X1_CONTROL0_GLAS_TPMA_CONTROL_GLAS_TPMA_CAPTURE_EN_ALIGN 0 19862 #define TX_X1_CONTROL0_GLAS_TPMA_CONTROL_GLAS_TPMA_CAPTURE_EN_BITS 1 19863 #define TX_X1_CONTROL0_GLAS_TPMA_CONTROL_GLAS_TPMA_CAPTURE_EN_SHIFT 0 19864 19865 19866 /**************************************************************************** 19867 * TX_X1_Control0 :: glas_tpma_data_0 19868 */ 19869 /* TX_X1_Control0 :: glas_tpma_data_0 :: glas_tpma_capture_data_0 [15:00] */ 19870 #define TX_X1_CONTROL0_GLAS_TPMA_DATA_0_GLAS_TPMA_CAPTURE_DATA_0_MASK 0xffff 19871 #define TX_X1_CONTROL0_GLAS_TPMA_DATA_0_GLAS_TPMA_CAPTURE_DATA_0_ALIGN 0 19872 #define TX_X1_CONTROL0_GLAS_TPMA_DATA_0_GLAS_TPMA_CAPTURE_DATA_0_BITS 16 19873 #define TX_X1_CONTROL0_GLAS_TPMA_DATA_0_GLAS_TPMA_CAPTURE_DATA_0_SHIFT 0 19874 19875 19876 /**************************************************************************** 19877 * TX_X1_Control0 :: glas_tpma_data_1 19878 */ 19879 /* TX_X1_Control0 :: glas_tpma_data_1 :: glas_tpma_capture_data_1 [15:00] */ 19880 #define TX_X1_CONTROL0_GLAS_TPMA_DATA_1_GLAS_TPMA_CAPTURE_DATA_1_MASK 0xffff 19881 #define TX_X1_CONTROL0_GLAS_TPMA_DATA_1_GLAS_TPMA_CAPTURE_DATA_1_ALIGN 0 19882 #define TX_X1_CONTROL0_GLAS_TPMA_DATA_1_GLAS_TPMA_CAPTURE_DATA_1_BITS 16 19883 #define TX_X1_CONTROL0_GLAS_TPMA_DATA_1_GLAS_TPMA_CAPTURE_DATA_1_SHIFT 0 19884 19885 19886 /**************************************************************************** 19887 * TX_X1_Control0 :: glas_tpma_data_2 19888 */ 19889 /* TX_X1_Control0 :: glas_tpma_data_2 :: glas_tpma_capture_data_2 [15:00] */ 19890 #define TX_X1_CONTROL0_GLAS_TPMA_DATA_2_GLAS_TPMA_CAPTURE_DATA_2_MASK 0xffff 19891 #define TX_X1_CONTROL0_GLAS_TPMA_DATA_2_GLAS_TPMA_CAPTURE_DATA_2_ALIGN 0 19892 #define TX_X1_CONTROL0_GLAS_TPMA_DATA_2_GLAS_TPMA_CAPTURE_DATA_2_BITS 16 19893 #define TX_X1_CONTROL0_GLAS_TPMA_DATA_2_GLAS_TPMA_CAPTURE_DATA_2_SHIFT 0 19894 19895 19896 /**************************************************************************** 19897 * TX_X1_Control0 :: glas_tpma_data_3 19898 */ 19899 /* TX_X1_Control0 :: glas_tpma_data_3 :: glas_tpma_capture_data_3 [15:00] */ 19900 #define TX_X1_CONTROL0_GLAS_TPMA_DATA_3_GLAS_TPMA_CAPTURE_DATA_3_MASK 0xffff 19901 #define TX_X1_CONTROL0_GLAS_TPMA_DATA_3_GLAS_TPMA_CAPTURE_DATA_3_ALIGN 0 19902 #define TX_X1_CONTROL0_GLAS_TPMA_DATA_3_GLAS_TPMA_CAPTURE_DATA_3_BITS 16 19903 #define TX_X1_CONTROL0_GLAS_TPMA_DATA_3_GLAS_TPMA_CAPTURE_DATA_3_SHIFT 0 19904 19905 19906 /**************************************************************************** 19907 * TX_X1_Control0 :: glas_tpma_data_4 19908 */ 19909 /* TX_X1_Control0 :: glas_tpma_data_4 :: glas_tpma_capture_data_4 [15:00] */ 19910 #define TX_X1_CONTROL0_GLAS_TPMA_DATA_4_GLAS_TPMA_CAPTURE_DATA_4_MASK 0xffff 19911 #define TX_X1_CONTROL0_GLAS_TPMA_DATA_4_GLAS_TPMA_CAPTURE_DATA_4_ALIGN 0 19912 #define TX_X1_CONTROL0_GLAS_TPMA_DATA_4_GLAS_TPMA_CAPTURE_DATA_4_BITS 16 19913 #define TX_X1_CONTROL0_GLAS_TPMA_DATA_4_GLAS_TPMA_CAPTURE_DATA_4_SHIFT 0 19914 19915 19916 /**************************************************************************** 19917 * TX_X1_Control0 :: glas_tpma_data_5 19918 */ 19919 /* TX_X1_Control0 :: glas_tpma_data_5 :: glas_tpma_capture_data_5 [15:00] */ 19920 #define TX_X1_CONTROL0_GLAS_TPMA_DATA_5_GLAS_TPMA_CAPTURE_DATA_5_MASK 0xffff 19921 #define TX_X1_CONTROL0_GLAS_TPMA_DATA_5_GLAS_TPMA_CAPTURE_DATA_5_ALIGN 0 19922 #define TX_X1_CONTROL0_GLAS_TPMA_DATA_5_GLAS_TPMA_CAPTURE_DATA_5_BITS 16 19923 #define TX_X1_CONTROL0_GLAS_TPMA_DATA_5_GLAS_TPMA_CAPTURE_DATA_5_SHIFT 0 19924 19925 19926 /**************************************************************************** 19927 * TX_X1_Control0 :: glas_tpma_data_6 19928 */ 19929 /* TX_X1_Control0 :: glas_tpma_data_6 :: glas_tpma_capture_data_6 [15:00] */ 19930 #define TX_X1_CONTROL0_GLAS_TPMA_DATA_6_GLAS_TPMA_CAPTURE_DATA_6_MASK 0xffff 19931 #define TX_X1_CONTROL0_GLAS_TPMA_DATA_6_GLAS_TPMA_CAPTURE_DATA_6_ALIGN 0 19932 #define TX_X1_CONTROL0_GLAS_TPMA_DATA_6_GLAS_TPMA_CAPTURE_DATA_6_BITS 16 19933 #define TX_X1_CONTROL0_GLAS_TPMA_DATA_6_GLAS_TPMA_CAPTURE_DATA_6_SHIFT 0 19934 19935 19936 /**************************************************************************** 19937 * TX_X1_Control0 :: glas_tpma_data_7 19938 */ 19939 /* TX_X1_Control0 :: glas_tpma_data_7 :: glas_tpma_capture_data_7 [15:00] */ 19940 #define TX_X1_CONTROL0_GLAS_TPMA_DATA_7_GLAS_TPMA_CAPTURE_DATA_7_MASK 0xffff 19941 #define TX_X1_CONTROL0_GLAS_TPMA_DATA_7_GLAS_TPMA_CAPTURE_DATA_7_ALIGN 0 19942 #define TX_X1_CONTROL0_GLAS_TPMA_DATA_7_GLAS_TPMA_CAPTURE_DATA_7_BITS 16 19943 #define TX_X1_CONTROL0_GLAS_TPMA_DATA_7_GLAS_TPMA_CAPTURE_DATA_7_SHIFT 0 19944 19945 19946 /**************************************************************************** 19947 * TX_X1_Control0 :: glas_tpma_adj_0_1 19948 */ 19949 /* TX_X1_Control0 :: glas_tpma_adj_0_1 :: glas_tpma_capture_adj_1 [15:08] */ 19950 #define TX_X1_CONTROL0_GLAS_TPMA_ADJ_0_1_GLAS_TPMA_CAPTURE_ADJ_1_MASK 0xff00 19951 #define TX_X1_CONTROL0_GLAS_TPMA_ADJ_0_1_GLAS_TPMA_CAPTURE_ADJ_1_ALIGN 0 19952 #define TX_X1_CONTROL0_GLAS_TPMA_ADJ_0_1_GLAS_TPMA_CAPTURE_ADJ_1_BITS 8 19953 #define TX_X1_CONTROL0_GLAS_TPMA_ADJ_0_1_GLAS_TPMA_CAPTURE_ADJ_1_SHIFT 8 19954 19955 /* TX_X1_Control0 :: glas_tpma_adj_0_1 :: glas_tpma_capture_adj_0 [07:00] */ 19956 #define TX_X1_CONTROL0_GLAS_TPMA_ADJ_0_1_GLAS_TPMA_CAPTURE_ADJ_0_MASK 0x00ff 19957 #define TX_X1_CONTROL0_GLAS_TPMA_ADJ_0_1_GLAS_TPMA_CAPTURE_ADJ_0_ALIGN 0 19958 #define TX_X1_CONTROL0_GLAS_TPMA_ADJ_0_1_GLAS_TPMA_CAPTURE_ADJ_0_BITS 8 19959 #define TX_X1_CONTROL0_GLAS_TPMA_ADJ_0_1_GLAS_TPMA_CAPTURE_ADJ_0_SHIFT 0 19960 19961 19962 /**************************************************************************** 19963 * TX_X1_Control0 :: glas_tpma_adj_2_3 19964 */ 19965 /* TX_X1_Control0 :: glas_tpma_adj_2_3 :: glas_tpma_capture_adj_3 [15:08] */ 19966 #define TX_X1_CONTROL0_GLAS_TPMA_ADJ_2_3_GLAS_TPMA_CAPTURE_ADJ_3_MASK 0xff00 19967 #define TX_X1_CONTROL0_GLAS_TPMA_ADJ_2_3_GLAS_TPMA_CAPTURE_ADJ_3_ALIGN 0 19968 #define TX_X1_CONTROL0_GLAS_TPMA_ADJ_2_3_GLAS_TPMA_CAPTURE_ADJ_3_BITS 8 19969 #define TX_X1_CONTROL0_GLAS_TPMA_ADJ_2_3_GLAS_TPMA_CAPTURE_ADJ_3_SHIFT 8 19970 19971 /* TX_X1_Control0 :: glas_tpma_adj_2_3 :: glas_tpma_capture_adj_2 [07:00] */ 19972 #define TX_X1_CONTROL0_GLAS_TPMA_ADJ_2_3_GLAS_TPMA_CAPTURE_ADJ_2_MASK 0x00ff 19973 #define TX_X1_CONTROL0_GLAS_TPMA_ADJ_2_3_GLAS_TPMA_CAPTURE_ADJ_2_ALIGN 0 19974 #define TX_X1_CONTROL0_GLAS_TPMA_ADJ_2_3_GLAS_TPMA_CAPTURE_ADJ_2_BITS 8 19975 #define TX_X1_CONTROL0_GLAS_TPMA_ADJ_2_3_GLAS_TPMA_CAPTURE_ADJ_2_SHIFT 0 19976 19977 19978 /**************************************************************************** 19979 * TX_X1_Control0 :: glas_tpma_adj_4_5 19980 */ 19981 /* TX_X1_Control0 :: glas_tpma_adj_4_5 :: glas_tpma_capture_adj_5 [15:08] */ 19982 #define TX_X1_CONTROL0_GLAS_TPMA_ADJ_4_5_GLAS_TPMA_CAPTURE_ADJ_5_MASK 0xff00 19983 #define TX_X1_CONTROL0_GLAS_TPMA_ADJ_4_5_GLAS_TPMA_CAPTURE_ADJ_5_ALIGN 0 19984 #define TX_X1_CONTROL0_GLAS_TPMA_ADJ_4_5_GLAS_TPMA_CAPTURE_ADJ_5_BITS 8 19985 #define TX_X1_CONTROL0_GLAS_TPMA_ADJ_4_5_GLAS_TPMA_CAPTURE_ADJ_5_SHIFT 8 19986 19987 /* TX_X1_Control0 :: glas_tpma_adj_4_5 :: glas_tpma_capture_adj_4 [07:00] */ 19988 #define TX_X1_CONTROL0_GLAS_TPMA_ADJ_4_5_GLAS_TPMA_CAPTURE_ADJ_4_MASK 0x00ff 19989 #define TX_X1_CONTROL0_GLAS_TPMA_ADJ_4_5_GLAS_TPMA_CAPTURE_ADJ_4_ALIGN 0 19990 #define TX_X1_CONTROL0_GLAS_TPMA_ADJ_4_5_GLAS_TPMA_CAPTURE_ADJ_4_BITS 8 19991 #define TX_X1_CONTROL0_GLAS_TPMA_ADJ_4_5_GLAS_TPMA_CAPTURE_ADJ_4_SHIFT 0 19992 19993 19994 /**************************************************************************** 19995 * TX_X1_Control0 :: glas_tpma_adj_6_7 19996 */ 19997 /* TX_X1_Control0 :: glas_tpma_adj_6_7 :: glas_tpma_capture_adj_7 [15:08] */ 19998 #define TX_X1_CONTROL0_GLAS_TPMA_ADJ_6_7_GLAS_TPMA_CAPTURE_ADJ_7_MASK 0xff00 19999 #define TX_X1_CONTROL0_GLAS_TPMA_ADJ_6_7_GLAS_TPMA_CAPTURE_ADJ_7_ALIGN 0 20000 #define TX_X1_CONTROL0_GLAS_TPMA_ADJ_6_7_GLAS_TPMA_CAPTURE_ADJ_7_BITS 8 20001 #define TX_X1_CONTROL0_GLAS_TPMA_ADJ_6_7_GLAS_TPMA_CAPTURE_ADJ_7_SHIFT 8 20002 20003 /* TX_X1_Control0 :: glas_tpma_adj_6_7 :: glas_tpma_capture_adj_6 [07:00] */ 20004 #define TX_X1_CONTROL0_GLAS_TPMA_ADJ_6_7_GLAS_TPMA_CAPTURE_ADJ_6_MASK 0x00ff 20005 #define TX_X1_CONTROL0_GLAS_TPMA_ADJ_6_7_GLAS_TPMA_CAPTURE_ADJ_6_ALIGN 0 20006 #define TX_X1_CONTROL0_GLAS_TPMA_ADJ_6_7_GLAS_TPMA_CAPTURE_ADJ_6_BITS 8 20007 #define TX_X1_CONTROL0_GLAS_TPMA_ADJ_6_7_GLAS_TPMA_CAPTURE_ADJ_6_SHIFT 0 20008 20009 20010 /**************************************************************************** 20011 * TSC_TSC_USER1_RX_X1_Control0 20012 */ 20013 /**************************************************************************** 20014 * RX_X1_Control0 :: RS_FEC_config 20015 */ 20016 /* RX_X1_Control0 :: RS_FEC_config :: reserved0 [15:02] */ 20017 #define RX_X1_CONTROL0_RS_FEC_CONFIG_RESERVED0_MASK 0xfffc 20018 #define RX_X1_CONTROL0_RS_FEC_CONFIG_RESERVED0_ALIGN 0 20019 #define RX_X1_CONTROL0_RS_FEC_CONFIG_RESERVED0_BITS 14 20020 #define RX_X1_CONTROL0_RS_FEC_CONFIG_RESERVED0_SHIFT 2 20021 20022 /* RX_X1_Control0 :: RS_FEC_config :: RS_FEC_CORRECTION_ENABLE [01:01] */ 20023 #define RX_X1_CONTROL0_RS_FEC_CONFIG_RS_FEC_CORRECTION_ENABLE_MASK 0x0002 20024 #define RX_X1_CONTROL0_RS_FEC_CONFIG_RS_FEC_CORRECTION_ENABLE_ALIGN 0 20025 #define RX_X1_CONTROL0_RS_FEC_CONFIG_RS_FEC_CORRECTION_ENABLE_BITS 1 20026 #define RX_X1_CONTROL0_RS_FEC_CONFIG_RS_FEC_CORRECTION_ENABLE_SHIFT 1 20027 20028 /* RX_X1_Control0 :: RS_FEC_config :: RS_FEC_CW_TYPE [00:00] */ 20029 #define RX_X1_CONTROL0_RS_FEC_CONFIG_RS_FEC_CW_TYPE_MASK 0x0001 20030 #define RX_X1_CONTROL0_RS_FEC_CONFIG_RS_FEC_CW_TYPE_ALIGN 0 20031 #define RX_X1_CONTROL0_RS_FEC_CONFIG_RS_FEC_CW_TYPE_BITS 1 20032 #define RX_X1_CONTROL0_RS_FEC_CONFIG_RS_FEC_CW_TYPE_SHIFT 0 20033 20034 20035 /**************************************************************************** 20036 * RX_X1_Control0 :: rx_lane_swap 20037 */ 20038 /* RX_X1_Control0 :: rx_lane_swap :: reserved0 [15:12] */ 20039 #define RX_X1_CONTROL0_RX_LANE_SWAP_RESERVED0_MASK 0xf000 20040 #define RX_X1_CONTROL0_RX_LANE_SWAP_RESERVED0_ALIGN 0 20041 #define RX_X1_CONTROL0_RX_LANE_SWAP_RESERVED0_BITS 4 20042 #define RX_X1_CONTROL0_RX_LANE_SWAP_RESERVED0_SHIFT 12 20043 20044 /* RX_X1_Control0 :: rx_lane_swap :: physical3_to_logical_sel [11:09] */ 20045 #define RX_X1_CONTROL0_RX_LANE_SWAP_PHYSICAL3_TO_LOGICAL_SEL_MASK 0x0e00 20046 #define RX_X1_CONTROL0_RX_LANE_SWAP_PHYSICAL3_TO_LOGICAL_SEL_ALIGN 0 20047 #define RX_X1_CONTROL0_RX_LANE_SWAP_PHYSICAL3_TO_LOGICAL_SEL_BITS 3 20048 #define RX_X1_CONTROL0_RX_LANE_SWAP_PHYSICAL3_TO_LOGICAL_SEL_SHIFT 9 20049 20050 /* RX_X1_Control0 :: rx_lane_swap :: physical2_to_logical_sel [08:06] */ 20051 #define RX_X1_CONTROL0_RX_LANE_SWAP_PHYSICAL2_TO_LOGICAL_SEL_MASK 0x01c0 20052 #define RX_X1_CONTROL0_RX_LANE_SWAP_PHYSICAL2_TO_LOGICAL_SEL_ALIGN 0 20053 #define RX_X1_CONTROL0_RX_LANE_SWAP_PHYSICAL2_TO_LOGICAL_SEL_BITS 3 20054 #define RX_X1_CONTROL0_RX_LANE_SWAP_PHYSICAL2_TO_LOGICAL_SEL_SHIFT 6 20055 20056 /* RX_X1_Control0 :: rx_lane_swap :: physical1_to_logical_sel [05:03] */ 20057 #define RX_X1_CONTROL0_RX_LANE_SWAP_PHYSICAL1_TO_LOGICAL_SEL_MASK 0x0038 20058 #define RX_X1_CONTROL0_RX_LANE_SWAP_PHYSICAL1_TO_LOGICAL_SEL_ALIGN 0 20059 #define RX_X1_CONTROL0_RX_LANE_SWAP_PHYSICAL1_TO_LOGICAL_SEL_BITS 3 20060 #define RX_X1_CONTROL0_RX_LANE_SWAP_PHYSICAL1_TO_LOGICAL_SEL_SHIFT 3 20061 20062 /* RX_X1_Control0 :: rx_lane_swap :: physical0_to_logical_sel [02:00] */ 20063 #define RX_X1_CONTROL0_RX_LANE_SWAP_PHYSICAL0_TO_LOGICAL_SEL_MASK 0x0007 20064 #define RX_X1_CONTROL0_RX_LANE_SWAP_PHYSICAL0_TO_LOGICAL_SEL_ALIGN 0 20065 #define RX_X1_CONTROL0_RX_LANE_SWAP_PHYSICAL0_TO_LOGICAL_SEL_BITS 3 20066 #define RX_X1_CONTROL0_RX_LANE_SWAP_PHYSICAL0_TO_LOGICAL_SEL_SHIFT 0 20067 20068 20069 /**************************************************************************** 20070 * RX_X1_Control0 :: srf_mem_ctrl 20071 */ 20072 /* RX_X1_Control0 :: srf_mem_ctrl :: reserved0 [15:12] */ 20073 #define RX_X1_CONTROL0_SRF_MEM_CTRL_RESERVED0_MASK 0xf000 20074 #define RX_X1_CONTROL0_SRF_MEM_CTRL_RESERVED0_ALIGN 0 20075 #define RX_X1_CONTROL0_SRF_MEM_CTRL_RESERVED0_BITS 4 20076 #define RX_X1_CONTROL0_SRF_MEM_CTRL_RESERVED0_SHIFT 12 20077 20078 /* RX_X1_Control0 :: srf_mem_ctrl :: srf_mem_TM [11:00] */ 20079 #define RX_X1_CONTROL0_SRF_MEM_CTRL_SRF_MEM_TM_MASK 0x0fff 20080 #define RX_X1_CONTROL0_SRF_MEM_CTRL_SRF_MEM_TM_ALIGN 0 20081 #define RX_X1_CONTROL0_SRF_MEM_CTRL_SRF_MEM_TM_BITS 12 20082 #define RX_X1_CONTROL0_SRF_MEM_CTRL_SRF_MEM_TM_SHIFT 0 20083 20084 20085 /**************************************************************************** 20086 * RX_X1_Control0 :: rf_mem_ctrl 20087 */ 20088 /* RX_X1_Control0 :: rf_mem_ctrl :: reserved0 [15:10] */ 20089 #define RX_X1_CONTROL0_RF_MEM_CTRL_RESERVED0_MASK 0xfc00 20090 #define RX_X1_CONTROL0_RF_MEM_CTRL_RESERVED0_ALIGN 0 20091 #define RX_X1_CONTROL0_RF_MEM_CTRL_RESERVED0_BITS 6 20092 #define RX_X1_CONTROL0_RF_MEM_CTRL_RESERVED0_SHIFT 10 20093 20094 /* RX_X1_Control0 :: rf_mem_ctrl :: rf_mem_TM [09:00] */ 20095 #define RX_X1_CONTROL0_RF_MEM_CTRL_RF_MEM_TM_MASK 0x03ff 20096 #define RX_X1_CONTROL0_RF_MEM_CTRL_RF_MEM_TM_ALIGN 0 20097 #define RX_X1_CONTROL0_RF_MEM_CTRL_RF_MEM_TM_BITS 10 20098 #define RX_X1_CONTROL0_RF_MEM_CTRL_RF_MEM_TM_SHIFT 0 20099 20100 20101 /**************************************************************************** 20102 * TSC_TSC_USER1_RX_X1_ECC 20103 */ 20104 /**************************************************************************** 20105 * RX_X1_ECC :: status_fec_mem_0 20106 */ 20107 /* RX_X1_ECC :: status_fec_mem_0 :: two_bit_err_event_fec_0 [15:15] */ 20108 #define RX_X1_ECC_STATUS_FEC_MEM_0_TWO_BIT_ERR_EVENT_FEC_0_MASK 0x8000 20109 #define RX_X1_ECC_STATUS_FEC_MEM_0_TWO_BIT_ERR_EVENT_FEC_0_ALIGN 0 20110 #define RX_X1_ECC_STATUS_FEC_MEM_0_TWO_BIT_ERR_EVENT_FEC_0_BITS 1 20111 #define RX_X1_ECC_STATUS_FEC_MEM_0_TWO_BIT_ERR_EVENT_FEC_0_SHIFT 15 20112 20113 /* RX_X1_ECC :: status_fec_mem_0 :: one_bit_err_event_fec_0 [14:14] */ 20114 #define RX_X1_ECC_STATUS_FEC_MEM_0_ONE_BIT_ERR_EVENT_FEC_0_MASK 0x4000 20115 #define RX_X1_ECC_STATUS_FEC_MEM_0_ONE_BIT_ERR_EVENT_FEC_0_ALIGN 0 20116 #define RX_X1_ECC_STATUS_FEC_MEM_0_ONE_BIT_ERR_EVENT_FEC_0_BITS 1 20117 #define RX_X1_ECC_STATUS_FEC_MEM_0_ONE_BIT_ERR_EVENT_FEC_0_SHIFT 14 20118 20119 /* RX_X1_ECC :: status_fec_mem_0 :: err_event_address_fec_0 [13:00] */ 20120 #define RX_X1_ECC_STATUS_FEC_MEM_0_ERR_EVENT_ADDRESS_FEC_0_MASK 0x3fff 20121 #define RX_X1_ECC_STATUS_FEC_MEM_0_ERR_EVENT_ADDRESS_FEC_0_ALIGN 0 20122 #define RX_X1_ECC_STATUS_FEC_MEM_0_ERR_EVENT_ADDRESS_FEC_0_BITS 14 20123 #define RX_X1_ECC_STATUS_FEC_MEM_0_ERR_EVENT_ADDRESS_FEC_0_SHIFT 0 20124 20125 20126 /**************************************************************************** 20127 * RX_X1_ECC :: status_fec_mem_1 20128 */ 20129 /* RX_X1_ECC :: status_fec_mem_1 :: two_bit_err_event_fec_1 [15:15] */ 20130 #define RX_X1_ECC_STATUS_FEC_MEM_1_TWO_BIT_ERR_EVENT_FEC_1_MASK 0x8000 20131 #define RX_X1_ECC_STATUS_FEC_MEM_1_TWO_BIT_ERR_EVENT_FEC_1_ALIGN 0 20132 #define RX_X1_ECC_STATUS_FEC_MEM_1_TWO_BIT_ERR_EVENT_FEC_1_BITS 1 20133 #define RX_X1_ECC_STATUS_FEC_MEM_1_TWO_BIT_ERR_EVENT_FEC_1_SHIFT 15 20134 20135 /* RX_X1_ECC :: status_fec_mem_1 :: one_bit_err_event_fec_1 [14:14] */ 20136 #define RX_X1_ECC_STATUS_FEC_MEM_1_ONE_BIT_ERR_EVENT_FEC_1_MASK 0x4000 20137 #define RX_X1_ECC_STATUS_FEC_MEM_1_ONE_BIT_ERR_EVENT_FEC_1_ALIGN 0 20138 #define RX_X1_ECC_STATUS_FEC_MEM_1_ONE_BIT_ERR_EVENT_FEC_1_BITS 1 20139 #define RX_X1_ECC_STATUS_FEC_MEM_1_ONE_BIT_ERR_EVENT_FEC_1_SHIFT 14 20140 20141 /* RX_X1_ECC :: status_fec_mem_1 :: err_event_address_fec_1 [13:00] */ 20142 #define RX_X1_ECC_STATUS_FEC_MEM_1_ERR_EVENT_ADDRESS_FEC_1_MASK 0x3fff 20143 #define RX_X1_ECC_STATUS_FEC_MEM_1_ERR_EVENT_ADDRESS_FEC_1_ALIGN 0 20144 #define RX_X1_ECC_STATUS_FEC_MEM_1_ERR_EVENT_ADDRESS_FEC_1_BITS 14 20145 #define RX_X1_ECC_STATUS_FEC_MEM_1_ERR_EVENT_ADDRESS_FEC_1_SHIFT 0 20146 20147 20148 /**************************************************************************** 20149 * RX_X1_ECC :: status_fec_mem_2 20150 */ 20151 /* RX_X1_ECC :: status_fec_mem_2 :: two_bit_err_event_fec_2 [15:15] */ 20152 #define RX_X1_ECC_STATUS_FEC_MEM_2_TWO_BIT_ERR_EVENT_FEC_2_MASK 0x8000 20153 #define RX_X1_ECC_STATUS_FEC_MEM_2_TWO_BIT_ERR_EVENT_FEC_2_ALIGN 0 20154 #define RX_X1_ECC_STATUS_FEC_MEM_2_TWO_BIT_ERR_EVENT_FEC_2_BITS 1 20155 #define RX_X1_ECC_STATUS_FEC_MEM_2_TWO_BIT_ERR_EVENT_FEC_2_SHIFT 15 20156 20157 /* RX_X1_ECC :: status_fec_mem_2 :: one_bit_err_event_fec_2 [14:14] */ 20158 #define RX_X1_ECC_STATUS_FEC_MEM_2_ONE_BIT_ERR_EVENT_FEC_2_MASK 0x4000 20159 #define RX_X1_ECC_STATUS_FEC_MEM_2_ONE_BIT_ERR_EVENT_FEC_2_ALIGN 0 20160 #define RX_X1_ECC_STATUS_FEC_MEM_2_ONE_BIT_ERR_EVENT_FEC_2_BITS 1 20161 #define RX_X1_ECC_STATUS_FEC_MEM_2_ONE_BIT_ERR_EVENT_FEC_2_SHIFT 14 20162 20163 /* RX_X1_ECC :: status_fec_mem_2 :: err_event_address_fec_2 [13:00] */ 20164 #define RX_X1_ECC_STATUS_FEC_MEM_2_ERR_EVENT_ADDRESS_FEC_2_MASK 0x3fff 20165 #define RX_X1_ECC_STATUS_FEC_MEM_2_ERR_EVENT_ADDRESS_FEC_2_ALIGN 0 20166 #define RX_X1_ECC_STATUS_FEC_MEM_2_ERR_EVENT_ADDRESS_FEC_2_BITS 14 20167 #define RX_X1_ECC_STATUS_FEC_MEM_2_ERR_EVENT_ADDRESS_FEC_2_SHIFT 0 20168 20169 20170 /**************************************************************************** 20171 * RX_X1_ECC :: status_fec_mem_3 20172 */ 20173 /* RX_X1_ECC :: status_fec_mem_3 :: two_bit_err_event_fec_3 [15:15] */ 20174 #define RX_X1_ECC_STATUS_FEC_MEM_3_TWO_BIT_ERR_EVENT_FEC_3_MASK 0x8000 20175 #define RX_X1_ECC_STATUS_FEC_MEM_3_TWO_BIT_ERR_EVENT_FEC_3_ALIGN 0 20176 #define RX_X1_ECC_STATUS_FEC_MEM_3_TWO_BIT_ERR_EVENT_FEC_3_BITS 1 20177 #define RX_X1_ECC_STATUS_FEC_MEM_3_TWO_BIT_ERR_EVENT_FEC_3_SHIFT 15 20178 20179 /* RX_X1_ECC :: status_fec_mem_3 :: one_bit_err_event_fec_3 [14:14] */ 20180 #define RX_X1_ECC_STATUS_FEC_MEM_3_ONE_BIT_ERR_EVENT_FEC_3_MASK 0x4000 20181 #define RX_X1_ECC_STATUS_FEC_MEM_3_ONE_BIT_ERR_EVENT_FEC_3_ALIGN 0 20182 #define RX_X1_ECC_STATUS_FEC_MEM_3_ONE_BIT_ERR_EVENT_FEC_3_BITS 1 20183 #define RX_X1_ECC_STATUS_FEC_MEM_3_ONE_BIT_ERR_EVENT_FEC_3_SHIFT 14 20184 20185 /* RX_X1_ECC :: status_fec_mem_3 :: err_event_address_fec_3 [13:00] */ 20186 #define RX_X1_ECC_STATUS_FEC_MEM_3_ERR_EVENT_ADDRESS_FEC_3_MASK 0x3fff 20187 #define RX_X1_ECC_STATUS_FEC_MEM_3_ERR_EVENT_ADDRESS_FEC_3_ALIGN 0 20188 #define RX_X1_ECC_STATUS_FEC_MEM_3_ERR_EVENT_ADDRESS_FEC_3_BITS 14 20189 #define RX_X1_ECC_STATUS_FEC_MEM_3_ERR_EVENT_ADDRESS_FEC_3_SHIFT 0 20190 20191 20192 /**************************************************************************** 20193 * RX_X1_ECC :: interrupt_status_1bit 20194 */ 20195 /* RX_X1_ECC :: interrupt_status_1bit :: reserved0 [15:08] */ 20196 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_RESERVED0_MASK 0xff00 20197 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_RESERVED0_ALIGN 0 20198 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_RESERVED0_BITS 8 20199 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_RESERVED0_SHIFT 8 20200 20201 /* RX_X1_ECC :: interrupt_status_1bit :: RS_FEC_fec_ram2_hi_1bit_int_status [07:07] */ 20202 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_RS_FEC_FEC_RAM2_HI_1BIT_INT_STATUS_MASK 0x0080 20203 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_RS_FEC_FEC_RAM2_HI_1BIT_INT_STATUS_ALIGN 0 20204 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_RS_FEC_FEC_RAM2_HI_1BIT_INT_STATUS_BITS 1 20205 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_RS_FEC_FEC_RAM2_HI_1BIT_INT_STATUS_SHIFT 7 20206 20207 /* RX_X1_ECC :: interrupt_status_1bit :: RS_FEC_fec_ram2_lo_1bit_int_status [06:06] */ 20208 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_RS_FEC_FEC_RAM2_LO_1BIT_INT_STATUS_MASK 0x0040 20209 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_RS_FEC_FEC_RAM2_LO_1BIT_INT_STATUS_ALIGN 0 20210 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_RS_FEC_FEC_RAM2_LO_1BIT_INT_STATUS_BITS 1 20211 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_RS_FEC_FEC_RAM2_LO_1BIT_INT_STATUS_SHIFT 6 20212 20213 /* RX_X1_ECC :: interrupt_status_1bit :: RS_FEC_fec_ram1_hi_1bit_int_status [05:05] */ 20214 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_RS_FEC_FEC_RAM1_HI_1BIT_INT_STATUS_MASK 0x0020 20215 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_RS_FEC_FEC_RAM1_HI_1BIT_INT_STATUS_ALIGN 0 20216 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_RS_FEC_FEC_RAM1_HI_1BIT_INT_STATUS_BITS 1 20217 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_RS_FEC_FEC_RAM1_HI_1BIT_INT_STATUS_SHIFT 5 20218 20219 /* RX_X1_ECC :: interrupt_status_1bit :: RS_FEC_fec_ram1_lo_1bit_int_status [04:04] */ 20220 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_RS_FEC_FEC_RAM1_LO_1BIT_INT_STATUS_MASK 0x0010 20221 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_RS_FEC_FEC_RAM1_LO_1BIT_INT_STATUS_ALIGN 0 20222 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_RS_FEC_FEC_RAM1_LO_1BIT_INT_STATUS_BITS 1 20223 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_RS_FEC_FEC_RAM1_LO_1BIT_INT_STATUS_SHIFT 4 20224 20225 /* RX_X1_ECC :: interrupt_status_1bit :: fec_mem_3_1bit_int_status [03:03] */ 20226 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_FEC_MEM_3_1BIT_INT_STATUS_MASK 0x0008 20227 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_FEC_MEM_3_1BIT_INT_STATUS_ALIGN 0 20228 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_FEC_MEM_3_1BIT_INT_STATUS_BITS 1 20229 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_FEC_MEM_3_1BIT_INT_STATUS_SHIFT 3 20230 20231 /* RX_X1_ECC :: interrupt_status_1bit :: fec_mem_2_1bit_int_status [02:02] */ 20232 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_FEC_MEM_2_1BIT_INT_STATUS_MASK 0x0004 20233 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_FEC_MEM_2_1BIT_INT_STATUS_ALIGN 0 20234 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_FEC_MEM_2_1BIT_INT_STATUS_BITS 1 20235 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_FEC_MEM_2_1BIT_INT_STATUS_SHIFT 2 20236 20237 /* RX_X1_ECC :: interrupt_status_1bit :: fec_mem_1_1bit_int_status [01:01] */ 20238 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_FEC_MEM_1_1BIT_INT_STATUS_MASK 0x0002 20239 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_FEC_MEM_1_1BIT_INT_STATUS_ALIGN 0 20240 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_FEC_MEM_1_1BIT_INT_STATUS_BITS 1 20241 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_FEC_MEM_1_1BIT_INT_STATUS_SHIFT 1 20242 20243 /* RX_X1_ECC :: interrupt_status_1bit :: fec_mem_0_1bit_int_status [00:00] */ 20244 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_FEC_MEM_0_1BIT_INT_STATUS_MASK 0x0001 20245 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_FEC_MEM_0_1BIT_INT_STATUS_ALIGN 0 20246 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_FEC_MEM_0_1BIT_INT_STATUS_BITS 1 20247 #define RX_X1_ECC_INTERRUPT_STATUS_1BIT_FEC_MEM_0_1BIT_INT_STATUS_SHIFT 0 20248 20249 20250 /**************************************************************************** 20251 * RX_X1_ECC :: interrupt_status_2bit 20252 */ 20253 /* RX_X1_ECC :: interrupt_status_2bit :: reserved0 [15:08] */ 20254 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_RESERVED0_MASK 0xff00 20255 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_RESERVED0_ALIGN 0 20256 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_RESERVED0_BITS 8 20257 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_RESERVED0_SHIFT 8 20258 20259 /* RX_X1_ECC :: interrupt_status_2bit :: RS_FEC_fec_ram2_hi_2bit_int_status [07:07] */ 20260 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_RS_FEC_FEC_RAM2_HI_2BIT_INT_STATUS_MASK 0x0080 20261 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_RS_FEC_FEC_RAM2_HI_2BIT_INT_STATUS_ALIGN 0 20262 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_RS_FEC_FEC_RAM2_HI_2BIT_INT_STATUS_BITS 1 20263 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_RS_FEC_FEC_RAM2_HI_2BIT_INT_STATUS_SHIFT 7 20264 20265 /* RX_X1_ECC :: interrupt_status_2bit :: RS_FEC_fec_ram2_lo_2bit_int_status [06:06] */ 20266 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_RS_FEC_FEC_RAM2_LO_2BIT_INT_STATUS_MASK 0x0040 20267 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_RS_FEC_FEC_RAM2_LO_2BIT_INT_STATUS_ALIGN 0 20268 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_RS_FEC_FEC_RAM2_LO_2BIT_INT_STATUS_BITS 1 20269 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_RS_FEC_FEC_RAM2_LO_2BIT_INT_STATUS_SHIFT 6 20270 20271 /* RX_X1_ECC :: interrupt_status_2bit :: RS_FEC_fec_ram1_hi_2bit_int_status [05:05] */ 20272 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_RS_FEC_FEC_RAM1_HI_2BIT_INT_STATUS_MASK 0x0020 20273 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_RS_FEC_FEC_RAM1_HI_2BIT_INT_STATUS_ALIGN 0 20274 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_RS_FEC_FEC_RAM1_HI_2BIT_INT_STATUS_BITS 1 20275 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_RS_FEC_FEC_RAM1_HI_2BIT_INT_STATUS_SHIFT 5 20276 20277 /* RX_X1_ECC :: interrupt_status_2bit :: RS_FEC_fec_ram1_lo_2bit_int_status [04:04] */ 20278 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_RS_FEC_FEC_RAM1_LO_2BIT_INT_STATUS_MASK 0x0010 20279 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_RS_FEC_FEC_RAM1_LO_2BIT_INT_STATUS_ALIGN 0 20280 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_RS_FEC_FEC_RAM1_LO_2BIT_INT_STATUS_BITS 1 20281 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_RS_FEC_FEC_RAM1_LO_2BIT_INT_STATUS_SHIFT 4 20282 20283 /* RX_X1_ECC :: interrupt_status_2bit :: fec_mem_3_2bit_int_status [03:03] */ 20284 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_FEC_MEM_3_2BIT_INT_STATUS_MASK 0x0008 20285 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_FEC_MEM_3_2BIT_INT_STATUS_ALIGN 0 20286 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_FEC_MEM_3_2BIT_INT_STATUS_BITS 1 20287 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_FEC_MEM_3_2BIT_INT_STATUS_SHIFT 3 20288 20289 /* RX_X1_ECC :: interrupt_status_2bit :: fec_mem_2_2bit_int_status [02:02] */ 20290 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_FEC_MEM_2_2BIT_INT_STATUS_MASK 0x0004 20291 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_FEC_MEM_2_2BIT_INT_STATUS_ALIGN 0 20292 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_FEC_MEM_2_2BIT_INT_STATUS_BITS 1 20293 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_FEC_MEM_2_2BIT_INT_STATUS_SHIFT 2 20294 20295 /* RX_X1_ECC :: interrupt_status_2bit :: fec_mem_1_2bit_int_status [01:01] */ 20296 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_FEC_MEM_1_2BIT_INT_STATUS_MASK 0x0002 20297 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_FEC_MEM_1_2BIT_INT_STATUS_ALIGN 0 20298 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_FEC_MEM_1_2BIT_INT_STATUS_BITS 1 20299 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_FEC_MEM_1_2BIT_INT_STATUS_SHIFT 1 20300 20301 /* RX_X1_ECC :: interrupt_status_2bit :: fec_mem_0_2bit_int_status [00:00] */ 20302 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_FEC_MEM_0_2BIT_INT_STATUS_MASK 0x0001 20303 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_FEC_MEM_0_2BIT_INT_STATUS_ALIGN 0 20304 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_FEC_MEM_0_2BIT_INT_STATUS_BITS 1 20305 #define RX_X1_ECC_INTERRUPT_STATUS_2BIT_FEC_MEM_0_2BIT_INT_STATUS_SHIFT 0 20306 20307 20308 /**************************************************************************** 20309 * RX_X1_ECC :: interrupt_en_1bit 20310 */ 20311 /* RX_X1_ECC :: interrupt_en_1bit :: reserved0 [15:08] */ 20312 #define RX_X1_ECC_INTERRUPT_EN_1BIT_RESERVED0_MASK 0xff00 20313 #define RX_X1_ECC_INTERRUPT_EN_1BIT_RESERVED0_ALIGN 0 20314 #define RX_X1_ECC_INTERRUPT_EN_1BIT_RESERVED0_BITS 8 20315 #define RX_X1_ECC_INTERRUPT_EN_1BIT_RESERVED0_SHIFT 8 20316 20317 /* RX_X1_ECC :: interrupt_en_1bit :: RS_FEC_fec_ram2_hi_1bit_int_en [07:07] */ 20318 #define RX_X1_ECC_INTERRUPT_EN_1BIT_RS_FEC_FEC_RAM2_HI_1BIT_INT_EN_MASK 0x0080 20319 #define RX_X1_ECC_INTERRUPT_EN_1BIT_RS_FEC_FEC_RAM2_HI_1BIT_INT_EN_ALIGN 0 20320 #define RX_X1_ECC_INTERRUPT_EN_1BIT_RS_FEC_FEC_RAM2_HI_1BIT_INT_EN_BITS 1 20321 #define RX_X1_ECC_INTERRUPT_EN_1BIT_RS_FEC_FEC_RAM2_HI_1BIT_INT_EN_SHIFT 7 20322 20323 /* RX_X1_ECC :: interrupt_en_1bit :: RS_FEC_fec_ram2_lo_1bit_int_en [06:06] */ 20324 #define RX_X1_ECC_INTERRUPT_EN_1BIT_RS_FEC_FEC_RAM2_LO_1BIT_INT_EN_MASK 0x0040 20325 #define RX_X1_ECC_INTERRUPT_EN_1BIT_RS_FEC_FEC_RAM2_LO_1BIT_INT_EN_ALIGN 0 20326 #define RX_X1_ECC_INTERRUPT_EN_1BIT_RS_FEC_FEC_RAM2_LO_1BIT_INT_EN_BITS 1 20327 #define RX_X1_ECC_INTERRUPT_EN_1BIT_RS_FEC_FEC_RAM2_LO_1BIT_INT_EN_SHIFT 6 20328 20329 /* RX_X1_ECC :: interrupt_en_1bit :: RS_FEC_fec_ram1_hi_1bit_int_en [05:05] */ 20330 #define RX_X1_ECC_INTERRUPT_EN_1BIT_RS_FEC_FEC_RAM1_HI_1BIT_INT_EN_MASK 0x0020 20331 #define RX_X1_ECC_INTERRUPT_EN_1BIT_RS_FEC_FEC_RAM1_HI_1BIT_INT_EN_ALIGN 0 20332 #define RX_X1_ECC_INTERRUPT_EN_1BIT_RS_FEC_FEC_RAM1_HI_1BIT_INT_EN_BITS 1 20333 #define RX_X1_ECC_INTERRUPT_EN_1BIT_RS_FEC_FEC_RAM1_HI_1BIT_INT_EN_SHIFT 5 20334 20335 /* RX_X1_ECC :: interrupt_en_1bit :: RS_FEC_fec_ram1_lo_1bit_int_en [04:04] */ 20336 #define RX_X1_ECC_INTERRUPT_EN_1BIT_RS_FEC_FEC_RAM1_LO_1BIT_INT_EN_MASK 0x0010 20337 #define RX_X1_ECC_INTERRUPT_EN_1BIT_RS_FEC_FEC_RAM1_LO_1BIT_INT_EN_ALIGN 0 20338 #define RX_X1_ECC_INTERRUPT_EN_1BIT_RS_FEC_FEC_RAM1_LO_1BIT_INT_EN_BITS 1 20339 #define RX_X1_ECC_INTERRUPT_EN_1BIT_RS_FEC_FEC_RAM1_LO_1BIT_INT_EN_SHIFT 4 20340 20341 /* RX_X1_ECC :: interrupt_en_1bit :: fec_mem_3_1bit_int_en [03:03] */ 20342 #define RX_X1_ECC_INTERRUPT_EN_1BIT_FEC_MEM_3_1BIT_INT_EN_MASK 0x0008 20343 #define RX_X1_ECC_INTERRUPT_EN_1BIT_FEC_MEM_3_1BIT_INT_EN_ALIGN 0 20344 #define RX_X1_ECC_INTERRUPT_EN_1BIT_FEC_MEM_3_1BIT_INT_EN_BITS 1 20345 #define RX_X1_ECC_INTERRUPT_EN_1BIT_FEC_MEM_3_1BIT_INT_EN_SHIFT 3 20346 20347 /* RX_X1_ECC :: interrupt_en_1bit :: fec_mem_2_1bit_int_en [02:02] */ 20348 #define RX_X1_ECC_INTERRUPT_EN_1BIT_FEC_MEM_2_1BIT_INT_EN_MASK 0x0004 20349 #define RX_X1_ECC_INTERRUPT_EN_1BIT_FEC_MEM_2_1BIT_INT_EN_ALIGN 0 20350 #define RX_X1_ECC_INTERRUPT_EN_1BIT_FEC_MEM_2_1BIT_INT_EN_BITS 1 20351 #define RX_X1_ECC_INTERRUPT_EN_1BIT_FEC_MEM_2_1BIT_INT_EN_SHIFT 2 20352 20353 /* RX_X1_ECC :: interrupt_en_1bit :: fec_mem_1_1bit_int_en [01:01] */ 20354 #define RX_X1_ECC_INTERRUPT_EN_1BIT_FEC_MEM_1_1BIT_INT_EN_MASK 0x0002 20355 #define RX_X1_ECC_INTERRUPT_EN_1BIT_FEC_MEM_1_1BIT_INT_EN_ALIGN 0 20356 #define RX_X1_ECC_INTERRUPT_EN_1BIT_FEC_MEM_1_1BIT_INT_EN_BITS 1 20357 #define RX_X1_ECC_INTERRUPT_EN_1BIT_FEC_MEM_1_1BIT_INT_EN_SHIFT 1 20358 20359 /* RX_X1_ECC :: interrupt_en_1bit :: fec_mem_0_1bit_int_en [00:00] */ 20360 #define RX_X1_ECC_INTERRUPT_EN_1BIT_FEC_MEM_0_1BIT_INT_EN_MASK 0x0001 20361 #define RX_X1_ECC_INTERRUPT_EN_1BIT_FEC_MEM_0_1BIT_INT_EN_ALIGN 0 20362 #define RX_X1_ECC_INTERRUPT_EN_1BIT_FEC_MEM_0_1BIT_INT_EN_BITS 1 20363 #define RX_X1_ECC_INTERRUPT_EN_1BIT_FEC_MEM_0_1BIT_INT_EN_SHIFT 0 20364 20365 20366 /**************************************************************************** 20367 * RX_X1_ECC :: interrupt_en_2bit 20368 */ 20369 /* RX_X1_ECC :: interrupt_en_2bit :: reserved0 [15:08] */ 20370 #define RX_X1_ECC_INTERRUPT_EN_2BIT_RESERVED0_MASK 0xff00 20371 #define RX_X1_ECC_INTERRUPT_EN_2BIT_RESERVED0_ALIGN 0 20372 #define RX_X1_ECC_INTERRUPT_EN_2BIT_RESERVED0_BITS 8 20373 #define RX_X1_ECC_INTERRUPT_EN_2BIT_RESERVED0_SHIFT 8 20374 20375 /* RX_X1_ECC :: interrupt_en_2bit :: RS_FEC_fec_ram2_hi_2bit_int_en [07:07] */ 20376 #define RX_X1_ECC_INTERRUPT_EN_2BIT_RS_FEC_FEC_RAM2_HI_2BIT_INT_EN_MASK 0x0080 20377 #define RX_X1_ECC_INTERRUPT_EN_2BIT_RS_FEC_FEC_RAM2_HI_2BIT_INT_EN_ALIGN 0 20378 #define RX_X1_ECC_INTERRUPT_EN_2BIT_RS_FEC_FEC_RAM2_HI_2BIT_INT_EN_BITS 1 20379 #define RX_X1_ECC_INTERRUPT_EN_2BIT_RS_FEC_FEC_RAM2_HI_2BIT_INT_EN_SHIFT 7 20380 20381 /* RX_X1_ECC :: interrupt_en_2bit :: RS_FEC_fec_ram2_lo_2bit_int_en [06:06] */ 20382 #define RX_X1_ECC_INTERRUPT_EN_2BIT_RS_FEC_FEC_RAM2_LO_2BIT_INT_EN_MASK 0x0040 20383 #define RX_X1_ECC_INTERRUPT_EN_2BIT_RS_FEC_FEC_RAM2_LO_2BIT_INT_EN_ALIGN 0 20384 #define RX_X1_ECC_INTERRUPT_EN_2BIT_RS_FEC_FEC_RAM2_LO_2BIT_INT_EN_BITS 1 20385 #define RX_X1_ECC_INTERRUPT_EN_2BIT_RS_FEC_FEC_RAM2_LO_2BIT_INT_EN_SHIFT 6 20386 20387 /* RX_X1_ECC :: interrupt_en_2bit :: RS_FEC_fec_ram1_hi_2bit_int_en [05:05] */ 20388 #define RX_X1_ECC_INTERRUPT_EN_2BIT_RS_FEC_FEC_RAM1_HI_2BIT_INT_EN_MASK 0x0020 20389 #define RX_X1_ECC_INTERRUPT_EN_2BIT_RS_FEC_FEC_RAM1_HI_2BIT_INT_EN_ALIGN 0 20390 #define RX_X1_ECC_INTERRUPT_EN_2BIT_RS_FEC_FEC_RAM1_HI_2BIT_INT_EN_BITS 1 20391 #define RX_X1_ECC_INTERRUPT_EN_2BIT_RS_FEC_FEC_RAM1_HI_2BIT_INT_EN_SHIFT 5 20392 20393 /* RX_X1_ECC :: interrupt_en_2bit :: RS_FEC_fec_ram1_lo_2bit_int_en [04:04] */ 20394 #define RX_X1_ECC_INTERRUPT_EN_2BIT_RS_FEC_FEC_RAM1_LO_2BIT_INT_EN_MASK 0x0010 20395 #define RX_X1_ECC_INTERRUPT_EN_2BIT_RS_FEC_FEC_RAM1_LO_2BIT_INT_EN_ALIGN 0 20396 #define RX_X1_ECC_INTERRUPT_EN_2BIT_RS_FEC_FEC_RAM1_LO_2BIT_INT_EN_BITS 1 20397 #define RX_X1_ECC_INTERRUPT_EN_2BIT_RS_FEC_FEC_RAM1_LO_2BIT_INT_EN_SHIFT 4 20398 20399 /* RX_X1_ECC :: interrupt_en_2bit :: fec_mem_3_2bit_int_en [03:03] */ 20400 #define RX_X1_ECC_INTERRUPT_EN_2BIT_FEC_MEM_3_2BIT_INT_EN_MASK 0x0008 20401 #define RX_X1_ECC_INTERRUPT_EN_2BIT_FEC_MEM_3_2BIT_INT_EN_ALIGN 0 20402 #define RX_X1_ECC_INTERRUPT_EN_2BIT_FEC_MEM_3_2BIT_INT_EN_BITS 1 20403 #define RX_X1_ECC_INTERRUPT_EN_2BIT_FEC_MEM_3_2BIT_INT_EN_SHIFT 3 20404 20405 /* RX_X1_ECC :: interrupt_en_2bit :: fec_mem_2_2bit_int_en [02:02] */ 20406 #define RX_X1_ECC_INTERRUPT_EN_2BIT_FEC_MEM_2_2BIT_INT_EN_MASK 0x0004 20407 #define RX_X1_ECC_INTERRUPT_EN_2BIT_FEC_MEM_2_2BIT_INT_EN_ALIGN 0 20408 #define RX_X1_ECC_INTERRUPT_EN_2BIT_FEC_MEM_2_2BIT_INT_EN_BITS 1 20409 #define RX_X1_ECC_INTERRUPT_EN_2BIT_FEC_MEM_2_2BIT_INT_EN_SHIFT 2 20410 20411 /* RX_X1_ECC :: interrupt_en_2bit :: fec_mem_1_2bit_int_en [01:01] */ 20412 #define RX_X1_ECC_INTERRUPT_EN_2BIT_FEC_MEM_1_2BIT_INT_EN_MASK 0x0002 20413 #define RX_X1_ECC_INTERRUPT_EN_2BIT_FEC_MEM_1_2BIT_INT_EN_ALIGN 0 20414 #define RX_X1_ECC_INTERRUPT_EN_2BIT_FEC_MEM_1_2BIT_INT_EN_BITS 1 20415 #define RX_X1_ECC_INTERRUPT_EN_2BIT_FEC_MEM_1_2BIT_INT_EN_SHIFT 1 20416 20417 /* RX_X1_ECC :: interrupt_en_2bit :: fec_mem_0_2bit_int_en [00:00] */ 20418 #define RX_X1_ECC_INTERRUPT_EN_2BIT_FEC_MEM_0_2BIT_INT_EN_MASK 0x0001 20419 #define RX_X1_ECC_INTERRUPT_EN_2BIT_FEC_MEM_0_2BIT_INT_EN_ALIGN 0 20420 #define RX_X1_ECC_INTERRUPT_EN_2BIT_FEC_MEM_0_2BIT_INT_EN_BITS 1 20421 #define RX_X1_ECC_INTERRUPT_EN_2BIT_FEC_MEM_0_2BIT_INT_EN_SHIFT 0 20422 20423 20424 /**************************************************************************** 20425 * RX_X1_ECC :: disable_ecc_mem 20426 */ 20427 /* RX_X1_ECC :: disable_ecc_mem :: reserved0 [15:08] */ 20428 #define RX_X1_ECC_DISABLE_ECC_MEM_RESERVED0_MASK 0xff00 20429 #define RX_X1_ECC_DISABLE_ECC_MEM_RESERVED0_ALIGN 0 20430 #define RX_X1_ECC_DISABLE_ECC_MEM_RESERVED0_BITS 8 20431 #define RX_X1_ECC_DISABLE_ECC_MEM_RESERVED0_SHIFT 8 20432 20433 /* RX_X1_ECC :: disable_ecc_mem :: disable_ecc_RS_FEC_fec_ram2_hi [07:07] */ 20434 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_RS_FEC_FEC_RAM2_HI_MASK 0x0080 20435 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_RS_FEC_FEC_RAM2_HI_ALIGN 0 20436 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_RS_FEC_FEC_RAM2_HI_BITS 1 20437 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_RS_FEC_FEC_RAM2_HI_SHIFT 7 20438 20439 /* RX_X1_ECC :: disable_ecc_mem :: disable_ecc_RS_FEC_fec_ram2_lo [06:06] */ 20440 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_RS_FEC_FEC_RAM2_LO_MASK 0x0040 20441 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_RS_FEC_FEC_RAM2_LO_ALIGN 0 20442 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_RS_FEC_FEC_RAM2_LO_BITS 1 20443 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_RS_FEC_FEC_RAM2_LO_SHIFT 6 20444 20445 /* RX_X1_ECC :: disable_ecc_mem :: disable_ecc_RS_FEC_fec_ram1_hi [05:05] */ 20446 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_RS_FEC_FEC_RAM1_HI_MASK 0x0020 20447 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_RS_FEC_FEC_RAM1_HI_ALIGN 0 20448 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_RS_FEC_FEC_RAM1_HI_BITS 1 20449 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_RS_FEC_FEC_RAM1_HI_SHIFT 5 20450 20451 /* RX_X1_ECC :: disable_ecc_mem :: disable_ecc_RS_FEC_fec_ram1_lo [04:04] */ 20452 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_RS_FEC_FEC_RAM1_LO_MASK 0x0010 20453 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_RS_FEC_FEC_RAM1_LO_ALIGN 0 20454 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_RS_FEC_FEC_RAM1_LO_BITS 1 20455 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_RS_FEC_FEC_RAM1_LO_SHIFT 4 20456 20457 /* RX_X1_ECC :: disable_ecc_mem :: disable_ecc_fec_mem_3 [03:03] */ 20458 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_FEC_MEM_3_MASK 0x0008 20459 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_FEC_MEM_3_ALIGN 0 20460 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_FEC_MEM_3_BITS 1 20461 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_FEC_MEM_3_SHIFT 3 20462 20463 /* RX_X1_ECC :: disable_ecc_mem :: disable_ecc_fec_mem_2 [02:02] */ 20464 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_FEC_MEM_2_MASK 0x0004 20465 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_FEC_MEM_2_ALIGN 0 20466 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_FEC_MEM_2_BITS 1 20467 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_FEC_MEM_2_SHIFT 2 20468 20469 /* RX_X1_ECC :: disable_ecc_mem :: disable_ecc_fec_mem_1 [01:01] */ 20470 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_FEC_MEM_1_MASK 0x0002 20471 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_FEC_MEM_1_ALIGN 0 20472 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_FEC_MEM_1_BITS 1 20473 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_FEC_MEM_1_SHIFT 1 20474 20475 /* RX_X1_ECC :: disable_ecc_mem :: disable_ecc_fec_mem_0 [00:00] */ 20476 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_FEC_MEM_0_MASK 0x0001 20477 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_FEC_MEM_0_ALIGN 0 20478 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_FEC_MEM_0_BITS 1 20479 #define RX_X1_ECC_DISABLE_ECC_MEM_DISABLE_ECC_FEC_MEM_0_SHIFT 0 20480 20481 20482 /**************************************************************************** 20483 * RX_X1_ECC :: corrupt_0 20484 */ 20485 /* RX_X1_ECC :: corrupt_0 :: corrupt_ecc_RS_FEC_fec_ram2_hi [15:14] */ 20486 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_RS_FEC_FEC_RAM2_HI_MASK 0xc000 20487 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_RS_FEC_FEC_RAM2_HI_ALIGN 0 20488 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_RS_FEC_FEC_RAM2_HI_BITS 2 20489 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_RS_FEC_FEC_RAM2_HI_SHIFT 14 20490 20491 /* RX_X1_ECC :: corrupt_0 :: corrupt_ecc_RS_FEC_fec_ram2_lo [13:12] */ 20492 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_RS_FEC_FEC_RAM2_LO_MASK 0x3000 20493 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_RS_FEC_FEC_RAM2_LO_ALIGN 0 20494 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_RS_FEC_FEC_RAM2_LO_BITS 2 20495 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_RS_FEC_FEC_RAM2_LO_SHIFT 12 20496 20497 /* RX_X1_ECC :: corrupt_0 :: corrupt_ecc_RS_FEC_fec_ram1_hi [11:10] */ 20498 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_RS_FEC_FEC_RAM1_HI_MASK 0x0c00 20499 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_RS_FEC_FEC_RAM1_HI_ALIGN 0 20500 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_RS_FEC_FEC_RAM1_HI_BITS 2 20501 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_RS_FEC_FEC_RAM1_HI_SHIFT 10 20502 20503 /* RX_X1_ECC :: corrupt_0 :: corrupt_ecc_RS_FEC_fec_ram1_lo [09:08] */ 20504 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_RS_FEC_FEC_RAM1_LO_MASK 0x0300 20505 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_RS_FEC_FEC_RAM1_LO_ALIGN 0 20506 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_RS_FEC_FEC_RAM1_LO_BITS 2 20507 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_RS_FEC_FEC_RAM1_LO_SHIFT 8 20508 20509 /* RX_X1_ECC :: corrupt_0 :: corrupt_ecc_fec_mem_3 [07:06] */ 20510 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_FEC_MEM_3_MASK 0x00c0 20511 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_FEC_MEM_3_ALIGN 0 20512 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_FEC_MEM_3_BITS 2 20513 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_FEC_MEM_3_SHIFT 6 20514 20515 /* RX_X1_ECC :: corrupt_0 :: corrupt_ecc_fec_mem_2 [05:04] */ 20516 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_FEC_MEM_2_MASK 0x0030 20517 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_FEC_MEM_2_ALIGN 0 20518 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_FEC_MEM_2_BITS 2 20519 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_FEC_MEM_2_SHIFT 4 20520 20521 /* RX_X1_ECC :: corrupt_0 :: corrupt_ecc_fec_mem_1 [03:02] */ 20522 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_FEC_MEM_1_MASK 0x000c 20523 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_FEC_MEM_1_ALIGN 0 20524 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_FEC_MEM_1_BITS 2 20525 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_FEC_MEM_1_SHIFT 2 20526 20527 /* RX_X1_ECC :: corrupt_0 :: corrupt_ecc_fec_mem_0 [01:00] */ 20528 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_FEC_MEM_0_MASK 0x0003 20529 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_FEC_MEM_0_ALIGN 0 20530 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_FEC_MEM_0_BITS 2 20531 #define RX_X1_ECC_CORRUPT_0_CORRUPT_ECC_FEC_MEM_0_SHIFT 0 20532 20533 20534 /**************************************************************************** 20535 * TSC_TSC_USER1_AN_X1_CONTROL 20536 */ 20537 /**************************************************************************** 20538 * AN_X1_CONTROL :: oui_upper 20539 */ 20540 /* AN_X1_CONTROL :: oui_upper :: reserved0 [15:08] */ 20541 #define AN_X1_CONTROL_OUI_UPPER_RESERVED0_MASK 0xff00 20542 #define AN_X1_CONTROL_OUI_UPPER_RESERVED0_ALIGN 0 20543 #define AN_X1_CONTROL_OUI_UPPER_RESERVED0_BITS 8 20544 #define AN_X1_CONTROL_OUI_UPPER_RESERVED0_SHIFT 8 20545 20546 /* AN_X1_CONTROL :: oui_upper :: oui_upper_data [07:00] */ 20547 #define AN_X1_CONTROL_OUI_UPPER_OUI_UPPER_DATA_MASK 0x00ff 20548 #define AN_X1_CONTROL_OUI_UPPER_OUI_UPPER_DATA_ALIGN 0 20549 #define AN_X1_CONTROL_OUI_UPPER_OUI_UPPER_DATA_BITS 8 20550 #define AN_X1_CONTROL_OUI_UPPER_OUI_UPPER_DATA_SHIFT 0 20551 20552 20553 /**************************************************************************** 20554 * AN_X1_CONTROL :: oui_lower 20555 */ 20556 /* AN_X1_CONTROL :: oui_lower :: oui_lower_data [15:00] */ 20557 #define AN_X1_CONTROL_OUI_LOWER_OUI_LOWER_DATA_MASK 0xffff 20558 #define AN_X1_CONTROL_OUI_LOWER_OUI_LOWER_DATA_ALIGN 0 20559 #define AN_X1_CONTROL_OUI_LOWER_OUI_LOWER_DATA_BITS 16 20560 #define AN_X1_CONTROL_OUI_LOWER_OUI_LOWER_DATA_SHIFT 0 20561 20562 20563 /**************************************************************************** 20564 * TSC_TSC_USER1_AN_X1_TIMERS 20565 */ 20566 /**************************************************************************** 20567 * AN_X1_TIMERS :: cl73_break_link 20568 */ 20569 /* AN_X1_TIMERS :: cl73_break_link :: cl73_break_timer_period [15:00] */ 20570 #define AN_X1_TIMERS_CL73_BREAK_LINK_CL73_BREAK_TIMER_PERIOD_MASK 0xffff 20571 #define AN_X1_TIMERS_CL73_BREAK_LINK_CL73_BREAK_TIMER_PERIOD_ALIGN 0 20572 #define AN_X1_TIMERS_CL73_BREAK_LINK_CL73_BREAK_TIMER_PERIOD_BITS 16 20573 #define AN_X1_TIMERS_CL73_BREAK_LINK_CL73_BREAK_TIMER_PERIOD_SHIFT 0 20574 20575 20576 /**************************************************************************** 20577 * AN_X1_TIMERS :: cl73_error 20578 */ 20579 /* AN_X1_TIMERS :: cl73_error :: cl73_error_timer_period [15:00] */ 20580 #define AN_X1_TIMERS_CL73_ERROR_CL73_ERROR_TIMER_PERIOD_MASK 0xffff 20581 #define AN_X1_TIMERS_CL73_ERROR_CL73_ERROR_TIMER_PERIOD_ALIGN 0 20582 #define AN_X1_TIMERS_CL73_ERROR_CL73_ERROR_TIMER_PERIOD_BITS 16 20583 #define AN_X1_TIMERS_CL73_ERROR_CL73_ERROR_TIMER_PERIOD_SHIFT 0 20584 20585 20586 /**************************************************************************** 20587 * AN_X1_TIMERS :: ignore_link_timer 20588 */ 20589 /* AN_X1_TIMERS :: ignore_link_timer :: ignore_link_timer_period [15:00] */ 20590 #define AN_X1_TIMERS_IGNORE_LINK_TIMER_IGNORE_LINK_TIMER_PERIOD_MASK 0xffff 20591 #define AN_X1_TIMERS_IGNORE_LINK_TIMER_IGNORE_LINK_TIMER_PERIOD_ALIGN 0 20592 #define AN_X1_TIMERS_IGNORE_LINK_TIMER_IGNORE_LINK_TIMER_PERIOD_BITS 16 20593 #define AN_X1_TIMERS_IGNORE_LINK_TIMER_IGNORE_LINK_TIMER_PERIOD_SHIFT 0 20594 20595 20596 /**************************************************************************** 20597 * AN_X1_TIMERS :: link_fail_inhibit_timer_cl72 20598 */ 20599 /* AN_X1_TIMERS :: link_fail_inhibit_timer_cl72 :: link_fail_inhibit_timer_cl72_period [15:00] */ 20600 #define AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_CL72_LINK_FAIL_INHIBIT_TIMER_CL72_PERIOD_MASK 0xffff 20601 #define AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_CL72_LINK_FAIL_INHIBIT_TIMER_CL72_PERIOD_ALIGN 0 20602 #define AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_CL72_LINK_FAIL_INHIBIT_TIMER_CL72_PERIOD_BITS 16 20603 #define AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_CL72_LINK_FAIL_INHIBIT_TIMER_CL72_PERIOD_SHIFT 0 20604 20605 20606 /**************************************************************************** 20607 * AN_X1_TIMERS :: link_fail_inhibit_timer_not_cl72 20608 */ 20609 /* AN_X1_TIMERS :: link_fail_inhibit_timer_not_cl72 :: link_fail_inhibit_timer_ncl72_period [15:00] */ 20610 #define AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_NOT_CL72_LINK_FAIL_INHIBIT_TIMER_NCL72_PERIOD_MASK 0xffff 20611 #define AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_NOT_CL72_LINK_FAIL_INHIBIT_TIMER_NCL72_PERIOD_ALIGN 0 20612 #define AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_NOT_CL72_LINK_FAIL_INHIBIT_TIMER_NCL72_PERIOD_BITS 16 20613 #define AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_NOT_CL72_LINK_FAIL_INHIBIT_TIMER_NCL72_PERIOD_SHIFT 0 20614 20615 20616 /**************************************************************************** 20617 * AN_X1_TIMERS :: dme_page_timer_type 20618 */ 20619 /* AN_X1_TIMERS :: dme_page_timer_type :: reserved0 [15:14] */ 20620 #define AN_X1_TIMERS_DME_PAGE_TIMER_TYPE_RESERVED0_MASK 0xc000 20621 #define AN_X1_TIMERS_DME_PAGE_TIMER_TYPE_RESERVED0_ALIGN 0 20622 #define AN_X1_TIMERS_DME_PAGE_TIMER_TYPE_RESERVED0_BITS 2 20623 #define AN_X1_TIMERS_DME_PAGE_TIMER_TYPE_RESERVED0_SHIFT 14 20624 20625 /* AN_X1_TIMERS :: dme_page_timer_type :: cl73_page_test_max_timer [13:07] */ 20626 #define AN_X1_TIMERS_DME_PAGE_TIMER_TYPE_CL73_PAGE_TEST_MAX_TIMER_MASK 0x3f80 20627 #define AN_X1_TIMERS_DME_PAGE_TIMER_TYPE_CL73_PAGE_TEST_MAX_TIMER_ALIGN 0 20628 #define AN_X1_TIMERS_DME_PAGE_TIMER_TYPE_CL73_PAGE_TEST_MAX_TIMER_BITS 7 20629 #define AN_X1_TIMERS_DME_PAGE_TIMER_TYPE_CL73_PAGE_TEST_MAX_TIMER_SHIFT 7 20630 20631 /* AN_X1_TIMERS :: dme_page_timer_type :: cl73_page_test_min_timer [06:00] */ 20632 #define AN_X1_TIMERS_DME_PAGE_TIMER_TYPE_CL73_PAGE_TEST_MIN_TIMER_MASK 0x007f 20633 #define AN_X1_TIMERS_DME_PAGE_TIMER_TYPE_CL73_PAGE_TEST_MIN_TIMER_ALIGN 0 20634 #define AN_X1_TIMERS_DME_PAGE_TIMER_TYPE_CL73_PAGE_TEST_MIN_TIMER_BITS 7 20635 #define AN_X1_TIMERS_DME_PAGE_TIMER_TYPE_CL73_PAGE_TEST_MIN_TIMER_SHIFT 0 20636 20637 20638 /**************************************************************************** 20639 * AN_X1_TIMERS :: ignore_link_timer_PAM4 20640 */ 20641 /* AN_X1_TIMERS :: ignore_link_timer_PAM4 :: ignore_link_timer_period_pam4 [15:00] */ 20642 #define AN_X1_TIMERS_IGNORE_LINK_TIMER_PAM4_IGNORE_LINK_TIMER_PERIOD_PAM4_MASK 0xffff 20643 #define AN_X1_TIMERS_IGNORE_LINK_TIMER_PAM4_IGNORE_LINK_TIMER_PERIOD_PAM4_ALIGN 0 20644 #define AN_X1_TIMERS_IGNORE_LINK_TIMER_PAM4_IGNORE_LINK_TIMER_PERIOD_PAM4_BITS 16 20645 #define AN_X1_TIMERS_IGNORE_LINK_TIMER_PAM4_IGNORE_LINK_TIMER_PERIOD_PAM4_SHIFT 0 20646 20647 20648 /**************************************************************************** 20649 * AN_X1_TIMERS :: link_fail_inhibit_timer_cl72_PAM4 20650 */ 20651 /* AN_X1_TIMERS :: link_fail_inhibit_timer_cl72_PAM4 :: link_fail_inhibit_timer_cl72_period_pam4 [15:00] */ 20652 #define AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_CL72_PAM4_LINK_FAIL_INHIBIT_TIMER_CL72_PERIOD_PAM4_MASK 0xffff 20653 #define AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_CL72_PAM4_LINK_FAIL_INHIBIT_TIMER_CL72_PERIOD_PAM4_ALIGN 0 20654 #define AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_CL72_PAM4_LINK_FAIL_INHIBIT_TIMER_CL72_PERIOD_PAM4_BITS 16 20655 #define AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_CL72_PAM4_LINK_FAIL_INHIBIT_TIMER_CL72_PERIOD_PAM4_SHIFT 0 20656 20657 20658 /**************************************************************************** 20659 * AN_X1_TIMERS :: link_fail_inhibit_timer_not_cl72_PAM4 20660 */ 20661 /* AN_X1_TIMERS :: link_fail_inhibit_timer_not_cl72_PAM4 :: link_fail_inhibit_timer_ncl72_period_pam4 [15:00] */ 20662 #define AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_NOT_CL72_PAM4_LINK_FAIL_INHIBIT_TIMER_NCL72_PERIOD_PAM4_MASK 0xffff 20663 #define AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_NOT_CL72_PAM4_LINK_FAIL_INHIBIT_TIMER_NCL72_PERIOD_PAM4_ALIGN 0 20664 #define AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_NOT_CL72_PAM4_LINK_FAIL_INHIBIT_TIMER_NCL72_PERIOD_PAM4_BITS 16 20665 #define AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_NOT_CL72_PAM4_LINK_FAIL_INHIBIT_TIMER_NCL72_PERIOD_PAM4_SHIFT 0 20666 20667 20668 /**************************************************************************** 20669 * TSC_TSC_USER1_sc_x1_control 20670 */ 20671 /**************************************************************************** 20672 * sc_x1_control :: pipeline_reset_count 20673 */ 20674 /* sc_x1_control :: pipeline_reset_count :: pipeline_reset_count [15:00] */ 20675 #define SC_X1_CONTROL_PIPELINE_RESET_COUNT_PIPELINE_RESET_COUNT_MASK 0xffff 20676 #define SC_X1_CONTROL_PIPELINE_RESET_COUNT_PIPELINE_RESET_COUNT_ALIGN 0 20677 #define SC_X1_CONTROL_PIPELINE_RESET_COUNT_PIPELINE_RESET_COUNT_BITS 16 20678 #define SC_X1_CONTROL_PIPELINE_RESET_COUNT_PIPELINE_RESET_COUNT_SHIFT 0 20679 20680 20681 /**************************************************************************** 20682 * sc_x1_control :: tx_reset_count 20683 */ 20684 /* sc_x1_control :: tx_reset_count :: tx_reset_count [15:00] */ 20685 #define SC_X1_CONTROL_TX_RESET_COUNT_TX_RESET_COUNT_MASK 0xffff 20686 #define SC_X1_CONTROL_TX_RESET_COUNT_TX_RESET_COUNT_ALIGN 0 20687 #define SC_X1_CONTROL_TX_RESET_COUNT_TX_RESET_COUNT_BITS 16 20688 #define SC_X1_CONTROL_TX_RESET_COUNT_TX_RESET_COUNT_SHIFT 0 20689 20690 20691 /**************************************************************************** 20692 * sc_x1_control :: status 20693 */ 20694 /* sc_x1_control :: status :: reserved0 [15:03] */ 20695 #define SC_X1_CONTROL_STATUS_RESERVED0_MASK 0xfff8 20696 #define SC_X1_CONTROL_STATUS_RESERVED0_ALIGN 0 20697 #define SC_X1_CONTROL_STATUS_RESERVED0_BITS 13 20698 #define SC_X1_CONTROL_STATUS_RESERVED0_SHIFT 3 20699 20700 /* sc_x1_control :: status :: resolved_port_mode [02:00] */ 20701 #define SC_X1_CONTROL_STATUS_RESOLVED_PORT_MODE_MASK 0x0007 20702 #define SC_X1_CONTROL_STATUS_RESOLVED_PORT_MODE_ALIGN 0 20703 #define SC_X1_CONTROL_STATUS_RESOLVED_PORT_MODE_BITS 3 20704 #define SC_X1_CONTROL_STATUS_RESOLVED_PORT_MODE_SHIFT 0 20705 20706 20707 /**************************************************************************** 20708 * TSC_TSC_USER1_rx_x1_status0 20709 */ 20710 /**************************************************************************** 20711 * rx_x1_status0 :: status_RS_FEC_fec_ram1_lo 20712 */ 20713 /* rx_x1_status0 :: status_RS_FEC_fec_ram1_lo :: two_bit_err_event_RS_FEC_fec_ram1_lo [15:15] */ 20714 #define RX_X1_STATUS0_STATUS_RS_FEC_FEC_RAM1_LO_TWO_BIT_ERR_EVENT_RS_FEC_FEC_RAM1_LO_MASK 0x8000 20715 #define RX_X1_STATUS0_STATUS_RS_FEC_FEC_RAM1_LO_TWO_BIT_ERR_EVENT_RS_FEC_FEC_RAM1_LO_ALIGN 0 20716 #define RX_X1_STATUS0_STATUS_RS_FEC_FEC_RAM1_LO_TWO_BIT_ERR_EVENT_RS_FEC_FEC_RAM1_LO_BITS 1 20717 #define RX_X1_STATUS0_STATUS_RS_FEC_FEC_RAM1_LO_TWO_BIT_ERR_EVENT_RS_FEC_FEC_RAM1_LO_SHIFT 15 20718 20719 /* rx_x1_status0 :: status_RS_FEC_fec_ram1_lo :: one_bit_err_event_RS_FEC_fec_ram1_lo [14:14] */ 20720 #define RX_X1_STATUS0_STATUS_RS_FEC_FEC_RAM1_LO_ONE_BIT_ERR_EVENT_RS_FEC_FEC_RAM1_LO_MASK 0x4000 20721 #define RX_X1_STATUS0_STATUS_RS_FEC_FEC_RAM1_LO_ONE_BIT_ERR_EVENT_RS_FEC_FEC_RAM1_LO_ALIGN 0 20722 #define RX_X1_STATUS0_STATUS_RS_FEC_FEC_RAM1_LO_ONE_BIT_ERR_EVENT_RS_FEC_FEC_RAM1_LO_BITS 1 20723 #define RX_X1_STATUS0_STATUS_RS_FEC_FEC_RAM1_LO_ONE_BIT_ERR_EVENT_RS_FEC_FEC_RAM1_LO_SHIFT 14 20724 20725 /* rx_x1_status0 :: status_RS_FEC_fec_ram1_lo :: err_event_address_RS_FEC_fec_ram1_lo [13:00] */ 20726 #define RX_X1_STATUS0_STATUS_RS_FEC_FEC_RAM1_LO_ERR_EVENT_ADDRESS_RS_FEC_FEC_RAM1_LO_MASK 0x3fff 20727 #define RX_X1_STATUS0_STATUS_RS_FEC_FEC_RAM1_LO_ERR_EVENT_ADDRESS_RS_FEC_FEC_RAM1_LO_ALIGN 0 20728 #define RX_X1_STATUS0_STATUS_RS_FEC_FEC_RAM1_LO_ERR_EVENT_ADDRESS_RS_FEC_FEC_RAM1_LO_BITS 14 20729 #define RX_X1_STATUS0_STATUS_RS_FEC_FEC_RAM1_LO_ERR_EVENT_ADDRESS_RS_FEC_FEC_RAM1_LO_SHIFT 0 20730 20731 20732 /**************************************************************************** 20733 * rx_x1_status0 :: status_RS_FEC_fec_ram1_hi 20734 */ 20735 /* rx_x1_status0 :: status_RS_FEC_fec_ram1_hi :: two_bit_err_event_RS_FEC_fec_ram1_hi [15:15] */ 20736 #define RX_X1_STATUS0_STATUS_RS_FEC_FEC_RAM1_HI_TWO_BIT_ERR_EVENT_RS_FEC_FEC_RAM1_HI_MASK 0x8000 20737 #define RX_X1_STATUS0_STATUS_RS_FEC_FEC_RAM1_HI_TWO_BIT_ERR_EVENT_RS_FEC_FEC_RAM1_HI_ALIGN 0 20738 #define RX_X1_STATUS0_STATUS_RS_FEC_FEC_RAM1_HI_TWO_BIT_ERR_EVENT_RS_FEC_FEC_RAM1_HI_BITS 1 20739 #define RX_X1_STATUS0_STATUS_RS_FEC_FEC_RAM1_HI_TWO_BIT_ERR_EVENT_RS_FEC_FEC_RAM1_HI_SHIFT 15 20740 20741 /* rx_x1_status0 :: status_RS_FEC_fec_ram1_hi :: one_bit_err_event_RS_FEC_fec_ram1_hi [14:14] */ 20742 #define RX_X1_STATUS0_STATUS_RS_FEC_FEC_RAM1_HI_ONE_BIT_ERR_EVENT_RS_FEC_FEC_RAM1_HI_MASK 0x4000 20743 #define RX_X1_STATUS0_STATUS_RS_FEC_FEC_RAM1_HI_ONE_BIT_ERR_EVENT_RS_FEC_FEC_RAM1_HI_ALIGN 0 20744 #define RX_X1_STATUS0_STATUS_RS_FEC_FEC_RAM1_HI_ONE_BIT_ERR_EVENT_RS_FEC_FEC_RAM1_HI_BITS 1 20745 #define RX_X1_STATUS0_STATUS_RS_FEC_FEC_RAM1_HI_ONE_BIT_ERR_EVENT_RS_FEC_FEC_RAM1_HI_SHIFT 14 20746 20747 /* rx_x1_status0 :: status_RS_FEC_fec_ram1_hi :: err_event_address_RS_FEC_fec_ram1_hi [13:00] */ 20748 #define RX_X1_STATUS0_STATUS_RS_FEC_FEC_RAM1_HI_ERR_EVENT_ADDRESS_RS_FEC_FEC_RAM1_HI_MASK 0x3fff 20749 #define RX_X1_STATUS0_STATUS_RS_FEC_FEC_RAM1_HI_ERR_EVENT_ADDRESS_RS_FEC_FEC_RAM1_HI_ALIGN 0 20750 #define RX_X1_STATUS0_STATUS_RS_FEC_FEC_RAM1_HI_ERR_EVENT_ADDRESS_RS_FEC_FEC_RAM1_HI_BITS 14 20751 #define RX_X1_STATUS0_STATUS_RS_FEC_FEC_RAM1_HI_ERR_EVENT_ADDRESS_RS_FEC_FEC_RAM1_HI_SHIFT 0 20752 20753 20754 /**************************************************************************** 20755 * rx_x1_status0 :: status_RS_FEC_fec_ram2_lo 20756 */ 20757 /* rx_x1_status0 :: status_RS_FEC_fec_ram2_lo :: two_bit_err_event_RS_FEC_fec_ram2_lo [15:15] */ 20758 #define RX_X1_STATUS0_STATUS_RS_FEC_FEC_RAM2_LO_TWO_BIT_ERR_EVENT_RS_FEC_FEC_RAM2_LO_MASK 0x8000 20759 #define RX_X1_STATUS0_STATUS_RS_FEC_FEC_RAM2_LO_TWO_BIT_ERR_EVENT_RS_FEC_FEC_RAM2_LO_ALIGN 0 20760 #define RX_X1_STATUS0_STATUS_RS_FEC_FEC_RAM2_LO_TWO_BIT_ERR_EVENT_RS_FEC_FEC_RAM2_LO_BITS 1 20761 #define RX_X1_STATUS0_STATUS_RS_FEC_FEC_RAM2_LO_TWO_BIT_ERR_EVENT_RS_FEC_FEC_RAM2_LO_SHIFT 15 20762 20763 /* rx_x1_status0 :: status_RS_FEC_fec_ram2_lo :: one_bit_err_event_RS_FEC_fec_ram2_lo [14:14] */ 20764 #define RX_X1_STATUS0_STATUS_RS_FEC_FEC_RAM2_LO_ONE_BIT_ERR_EVENT_RS_FEC_FEC_RAM2_LO_MASK 0x4000 20765 #define RX_X1_STATUS0_STATUS_RS_FEC_FEC_RAM2_LO_ONE_BIT_ERR_EVENT_RS_FEC_FEC_RAM2_LO_ALIGN 0 20766 #define RX_X1_STATUS0_STATUS_RS_FEC_FEC_RAM2_LO_ONE_BIT_ERR_EVENT_RS_FEC_FEC_RAM2_LO_BITS 1 20767 #define RX_X1_STATUS0_STATUS_RS_FEC_FEC_RAM2_LO_ONE_BIT_ERR_EVENT_RS_FEC_FEC_RAM2_LO_SHIFT 14 20768 20769 /* rx_x1_status0 :: status_RS_FEC_fec_ram2_lo :: err_event_address_RS_FEC_fec_ram2_lo [13:00] */ 20770 #define RX_X1_STATUS0_STATUS_RS_FEC_FEC_RAM2_LO_ERR_EVENT_ADDRESS_RS_FEC_FEC_RAM2_LO_MASK 0x3fff 20771 #define RX_X1_STATUS0_STATUS_RS_FEC_FEC_RAM2_LO_ERR_EVENT_ADDRESS_RS_FEC_FEC_RAM2_LO_ALIGN 0 20772 #define RX_X1_STATUS0_STATUS_RS_FEC_FEC_RAM2_LO_ERR_EVENT_ADDRESS_RS_FEC_FEC_RAM2_LO_BITS 14 20773 #define RX_X1_STATUS0_STATUS_RS_FEC_FEC_RAM2_LO_ERR_EVENT_ADDRESS_RS_FEC_FEC_RAM2_LO_SHIFT 0 20774 20775 20776 /**************************************************************************** 20777 * rx_x1_status0 :: status_RS_FEC_fec_ram2_hi 20778 */ 20779 /* rx_x1_status0 :: status_RS_FEC_fec_ram2_hi :: two_bit_err_event_RS_FEC_fec_ram2_hi [15:15] */ 20780 #define RX_X1_STATUS0_STATUS_RS_FEC_FEC_RAM2_HI_TWO_BIT_ERR_EVENT_RS_FEC_FEC_RAM2_HI_MASK 0x8000 20781 #define RX_X1_STATUS0_STATUS_RS_FEC_FEC_RAM2_HI_TWO_BIT_ERR_EVENT_RS_FEC_FEC_RAM2_HI_ALIGN 0 20782 #define RX_X1_STATUS0_STATUS_RS_FEC_FEC_RAM2_HI_TWO_BIT_ERR_EVENT_RS_FEC_FEC_RAM2_HI_BITS 1 20783 #define RX_X1_STATUS0_STATUS_RS_FEC_FEC_RAM2_HI_TWO_BIT_ERR_EVENT_RS_FEC_FEC_RAM2_HI_SHIFT 15 20784 20785 /* rx_x1_status0 :: status_RS_FEC_fec_ram2_hi :: one_bit_err_event_RS_FEC_fec_ram2_hi [14:14] */ 20786 #define RX_X1_STATUS0_STATUS_RS_FEC_FEC_RAM2_HI_ONE_BIT_ERR_EVENT_RS_FEC_FEC_RAM2_HI_MASK 0x4000 20787 #define RX_X1_STATUS0_STATUS_RS_FEC_FEC_RAM2_HI_ONE_BIT_ERR_EVENT_RS_FEC_FEC_RAM2_HI_ALIGN 0 20788 #define RX_X1_STATUS0_STATUS_RS_FEC_FEC_RAM2_HI_ONE_BIT_ERR_EVENT_RS_FEC_FEC_RAM2_HI_BITS 1 20789 #define RX_X1_STATUS0_STATUS_RS_FEC_FEC_RAM2_HI_ONE_BIT_ERR_EVENT_RS_FEC_FEC_RAM2_HI_SHIFT 14 20790 20791 /* rx_x1_status0 :: status_RS_FEC_fec_ram2_hi :: err_event_address_RS_FEC_fec_ram2_hi [13:00] */ 20792 #define RX_X1_STATUS0_STATUS_RS_FEC_FEC_RAM2_HI_ERR_EVENT_ADDRESS_RS_FEC_FEC_RAM2_HI_MASK 0x3fff 20793 #define RX_X1_STATUS0_STATUS_RS_FEC_FEC_RAM2_HI_ERR_EVENT_ADDRESS_RS_FEC_FEC_RAM2_HI_ALIGN 0 20794 #define RX_X1_STATUS0_STATUS_RS_FEC_FEC_RAM2_HI_ERR_EVENT_ADDRESS_RS_FEC_FEC_RAM2_HI_BITS 14 20795 #define RX_X1_STATUS0_STATUS_RS_FEC_FEC_RAM2_HI_ERR_EVENT_ADDRESS_RS_FEC_FEC_RAM2_HI_SHIFT 0 20796 20797 20798 /**************************************************************************** 20799 * TSC_TSC_USER1_AN_X1_SW_MGMT 20800 */ 20801 /**************************************************************************** 20802 * AN_X1_SW_MGMT :: glb_int 20803 */ 20804 /* AN_X1_SW_MGMT :: glb_int :: reserved0 [15:04] */ 20805 #define AN_X1_SW_MGMT_GLB_INT_RESERVED0_MASK 0xfff0 20806 #define AN_X1_SW_MGMT_GLB_INT_RESERVED0_ALIGN 0 20807 #define AN_X1_SW_MGMT_GLB_INT_RESERVED0_BITS 12 20808 #define AN_X1_SW_MGMT_GLB_INT_RESERVED0_SHIFT 4 20809 20810 /* AN_X1_SW_MGMT :: glb_int :: int_port3 [03:03] */ 20811 #define AN_X1_SW_MGMT_GLB_INT_INT_PORT3_MASK 0x0008 20812 #define AN_X1_SW_MGMT_GLB_INT_INT_PORT3_ALIGN 0 20813 #define AN_X1_SW_MGMT_GLB_INT_INT_PORT3_BITS 1 20814 #define AN_X1_SW_MGMT_GLB_INT_INT_PORT3_SHIFT 3 20815 20816 /* AN_X1_SW_MGMT :: glb_int :: int_port2 [02:02] */ 20817 #define AN_X1_SW_MGMT_GLB_INT_INT_PORT2_MASK 0x0004 20818 #define AN_X1_SW_MGMT_GLB_INT_INT_PORT2_ALIGN 0 20819 #define AN_X1_SW_MGMT_GLB_INT_INT_PORT2_BITS 1 20820 #define AN_X1_SW_MGMT_GLB_INT_INT_PORT2_SHIFT 2 20821 20822 /* AN_X1_SW_MGMT :: glb_int :: int_port1 [01:01] */ 20823 #define AN_X1_SW_MGMT_GLB_INT_INT_PORT1_MASK 0x0002 20824 #define AN_X1_SW_MGMT_GLB_INT_INT_PORT1_ALIGN 0 20825 #define AN_X1_SW_MGMT_GLB_INT_INT_PORT1_BITS 1 20826 #define AN_X1_SW_MGMT_GLB_INT_INT_PORT1_SHIFT 1 20827 20828 /* AN_X1_SW_MGMT :: glb_int :: int_port0 [00:00] */ 20829 #define AN_X1_SW_MGMT_GLB_INT_INT_PORT0_MASK 0x0001 20830 #define AN_X1_SW_MGMT_GLB_INT_INT_PORT0_ALIGN 0 20831 #define AN_X1_SW_MGMT_GLB_INT_INT_PORT0_BITS 1 20832 #define AN_X1_SW_MGMT_GLB_INT_INT_PORT0_SHIFT 0 20833 20834 20835 /**************************************************************************** 20836 * AN_X1_SW_MGMT :: glb_mask 20837 */ 20838 /* AN_X1_SW_MGMT :: glb_mask :: reserved0 [15:04] */ 20839 #define AN_X1_SW_MGMT_GLB_MASK_RESERVED0_MASK 0xfff0 20840 #define AN_X1_SW_MGMT_GLB_MASK_RESERVED0_ALIGN 0 20841 #define AN_X1_SW_MGMT_GLB_MASK_RESERVED0_BITS 12 20842 #define AN_X1_SW_MGMT_GLB_MASK_RESERVED0_SHIFT 4 20843 20844 /* AN_X1_SW_MGMT :: glb_mask :: int_port3_mask [03:03] */ 20845 #define AN_X1_SW_MGMT_GLB_MASK_INT_PORT3_MASK_MASK 0x0008 20846 #define AN_X1_SW_MGMT_GLB_MASK_INT_PORT3_MASK_ALIGN 0 20847 #define AN_X1_SW_MGMT_GLB_MASK_INT_PORT3_MASK_BITS 1 20848 #define AN_X1_SW_MGMT_GLB_MASK_INT_PORT3_MASK_SHIFT 3 20849 20850 /* AN_X1_SW_MGMT :: glb_mask :: int_port2_mask [02:02] */ 20851 #define AN_X1_SW_MGMT_GLB_MASK_INT_PORT2_MASK_MASK 0x0004 20852 #define AN_X1_SW_MGMT_GLB_MASK_INT_PORT2_MASK_ALIGN 0 20853 #define AN_X1_SW_MGMT_GLB_MASK_INT_PORT2_MASK_BITS 1 20854 #define AN_X1_SW_MGMT_GLB_MASK_INT_PORT2_MASK_SHIFT 2 20855 20856 /* AN_X1_SW_MGMT :: glb_mask :: int_port1_mask [01:01] */ 20857 #define AN_X1_SW_MGMT_GLB_MASK_INT_PORT1_MASK_MASK 0x0002 20858 #define AN_X1_SW_MGMT_GLB_MASK_INT_PORT1_MASK_ALIGN 0 20859 #define AN_X1_SW_MGMT_GLB_MASK_INT_PORT1_MASK_BITS 1 20860 #define AN_X1_SW_MGMT_GLB_MASK_INT_PORT1_MASK_SHIFT 1 20861 20862 /* AN_X1_SW_MGMT :: glb_mask :: int_port0_mask [00:00] */ 20863 #define AN_X1_SW_MGMT_GLB_MASK_INT_PORT0_MASK_MASK 0x0001 20864 #define AN_X1_SW_MGMT_GLB_MASK_INT_PORT0_MASK_ALIGN 0 20865 #define AN_X1_SW_MGMT_GLB_MASK_INT_PORT0_MASK_BITS 1 20866 #define AN_X1_SW_MGMT_GLB_MASK_INT_PORT0_MASK_SHIFT 0 20867 20868 20869 /**************************************************************************** 20870 * TSC_TSC_USER4_pmd_x4 20871 */ 20872 /**************************************************************************** 20873 * pmd_x4 :: control 20874 */ 20875 /* pmd_x4 :: control :: pam4_mode [15:13] */ 20876 #define PMD_X4_CONTROL_PAM4_MODE_MASK 0xe000 20877 #define PMD_X4_CONTROL_PAM4_MODE_ALIGN 0 20878 #define PMD_X4_CONTROL_PAM4_MODE_BITS 3 20879 #define PMD_X4_CONTROL_PAM4_MODE_SHIFT 13 20880 20881 /* pmd_x4 :: control :: osr_mode [12:09] */ 20882 #define PMD_X4_CONTROL_OSR_MODE_MASK 0x1e00 20883 #define PMD_X4_CONTROL_OSR_MODE_ALIGN 0 20884 #define PMD_X4_CONTROL_OSR_MODE_BITS 4 20885 #define PMD_X4_CONTROL_OSR_MODE_SHIFT 9 20886 20887 /* pmd_x4 :: control :: tx_disable [08:08] */ 20888 #define PMD_X4_CONTROL_TX_DISABLE_MASK 0x0100 20889 #define PMD_X4_CONTROL_TX_DISABLE_ALIGN 0 20890 #define PMD_X4_CONTROL_TX_DISABLE_BITS 1 20891 #define PMD_X4_CONTROL_TX_DISABLE_SHIFT 8 20892 20893 /* pmd_x4 :: control :: reserved0 [07:04] */ 20894 #define PMD_X4_CONTROL_RESERVED0_MASK 0x00f0 20895 #define PMD_X4_CONTROL_RESERVED0_ALIGN 0 20896 #define PMD_X4_CONTROL_RESERVED0_BITS 4 20897 #define PMD_X4_CONTROL_RESERVED0_SHIFT 4 20898 20899 /* pmd_x4 :: control :: ln_rx_h_pwrdn [03:03] */ 20900 #define PMD_X4_CONTROL_LN_RX_H_PWRDN_MASK 0x0008 20901 #define PMD_X4_CONTROL_LN_RX_H_PWRDN_ALIGN 0 20902 #define PMD_X4_CONTROL_LN_RX_H_PWRDN_BITS 1 20903 #define PMD_X4_CONTROL_LN_RX_H_PWRDN_SHIFT 3 20904 20905 /* pmd_x4 :: control :: ln_tx_h_pwrdn [02:02] */ 20906 #define PMD_X4_CONTROL_LN_TX_H_PWRDN_MASK 0x0004 20907 #define PMD_X4_CONTROL_LN_TX_H_PWRDN_ALIGN 0 20908 #define PMD_X4_CONTROL_LN_TX_H_PWRDN_BITS 1 20909 #define PMD_X4_CONTROL_LN_TX_H_PWRDN_SHIFT 2 20910 20911 /* pmd_x4 :: control :: ln_h_rstb [01:01] */ 20912 #define PMD_X4_CONTROL_LN_H_RSTB_MASK 0x0002 20913 #define PMD_X4_CONTROL_LN_H_RSTB_ALIGN 0 20914 #define PMD_X4_CONTROL_LN_H_RSTB_BITS 1 20915 #define PMD_X4_CONTROL_LN_H_RSTB_SHIFT 1 20916 20917 /* pmd_x4 :: control :: ln_dp_h_rstb [00:00] */ 20918 #define PMD_X4_CONTROL_LN_DP_H_RSTB_MASK 0x0001 20919 #define PMD_X4_CONTROL_LN_DP_H_RSTB_ALIGN 0 20920 #define PMD_X4_CONTROL_LN_DP_H_RSTB_BITS 1 20921 #define PMD_X4_CONTROL_LN_DP_H_RSTB_SHIFT 0 20922 20923 20924 /**************************************************************************** 20925 * pmd_x4 :: mode 20926 */ 20927 /* pmd_x4 :: mode :: lane_mode [15:00] */ 20928 #define PMD_X4_MODE_LANE_MODE_MASK 0xffff 20929 #define PMD_X4_MODE_LANE_MODE_ALIGN 0 20930 #define PMD_X4_MODE_LANE_MODE_BITS 16 20931 #define PMD_X4_MODE_LANE_MODE_SHIFT 0 20932 20933 20934 /**************************************************************************** 20935 * pmd_x4 :: status 20936 */ 20937 /* pmd_x4 :: status :: reserved0 [15:05] */ 20938 #define PMD_X4_STATUS_RESERVED0_MASK 0xffe0 20939 #define PMD_X4_STATUS_RESERVED0_ALIGN 0 20940 #define PMD_X4_STATUS_RESERVED0_BITS 11 20941 #define PMD_X4_STATUS_RESERVED0_SHIFT 5 20942 20943 /* pmd_x4 :: status :: tx_disable_live [04:04] */ 20944 #define PMD_X4_STATUS_TX_DISABLE_LIVE_MASK 0x0010 20945 #define PMD_X4_STATUS_TX_DISABLE_LIVE_ALIGN 0 20946 #define PMD_X4_STATUS_TX_DISABLE_LIVE_BITS 1 20947 #define PMD_X4_STATUS_TX_DISABLE_LIVE_SHIFT 4 20948 20949 /* pmd_x4 :: status :: tx_clk_vld_sts [03:03] */ 20950 #define PMD_X4_STATUS_TX_CLK_VLD_STS_MASK 0x0008 20951 #define PMD_X4_STATUS_TX_CLK_VLD_STS_ALIGN 0 20952 #define PMD_X4_STATUS_TX_CLK_VLD_STS_BITS 1 20953 #define PMD_X4_STATUS_TX_CLK_VLD_STS_SHIFT 3 20954 20955 /* pmd_x4 :: status :: rx_clk_vld_sts [02:02] */ 20956 #define PMD_X4_STATUS_RX_CLK_VLD_STS_MASK 0x0004 20957 #define PMD_X4_STATUS_RX_CLK_VLD_STS_ALIGN 0 20958 #define PMD_X4_STATUS_RX_CLK_VLD_STS_BITS 1 20959 #define PMD_X4_STATUS_RX_CLK_VLD_STS_SHIFT 2 20960 20961 /* pmd_x4 :: status :: signal_detect_sts [01:01] */ 20962 #define PMD_X4_STATUS_SIGNAL_DETECT_STS_MASK 0x0002 20963 #define PMD_X4_STATUS_SIGNAL_DETECT_STS_ALIGN 0 20964 #define PMD_X4_STATUS_SIGNAL_DETECT_STS_BITS 1 20965 #define PMD_X4_STATUS_SIGNAL_DETECT_STS_SHIFT 1 20966 20967 /* pmd_x4 :: status :: rx_lock_sts [00:00] */ 20968 #define PMD_X4_STATUS_RX_LOCK_STS_MASK 0x0001 20969 #define PMD_X4_STATUS_RX_LOCK_STS_ALIGN 0 20970 #define PMD_X4_STATUS_RX_LOCK_STS_BITS 1 20971 #define PMD_X4_STATUS_RX_LOCK_STS_SHIFT 0 20972 20973 20974 /**************************************************************************** 20975 * pmd_x4 :: latch_status 20976 */ 20977 /* pmd_x4 :: latch_status :: reserved0 [15:13] */ 20978 #define PMD_X4_LATCH_STATUS_RESERVED0_MASK 0xe000 20979 #define PMD_X4_LATCH_STATUS_RESERVED0_ALIGN 0 20980 #define PMD_X4_LATCH_STATUS_RESERVED0_BITS 3 20981 #define PMD_X4_LATCH_STATUS_RESERVED0_SHIFT 13 20982 20983 /* pmd_x4 :: latch_status :: tx_disable_LH [12:12] */ 20984 #define PMD_X4_LATCH_STATUS_TX_DISABLE_LH_MASK 0x1000 20985 #define PMD_X4_LATCH_STATUS_TX_DISABLE_LH_ALIGN 0 20986 #define PMD_X4_LATCH_STATUS_TX_DISABLE_LH_BITS 1 20987 #define PMD_X4_LATCH_STATUS_TX_DISABLE_LH_SHIFT 12 20988 20989 /* pmd_x4 :: latch_status :: tx_disable_LL [11:11] */ 20990 #define PMD_X4_LATCH_STATUS_TX_DISABLE_LL_MASK 0x0800 20991 #define PMD_X4_LATCH_STATUS_TX_DISABLE_LL_ALIGN 0 20992 #define PMD_X4_LATCH_STATUS_TX_DISABLE_LL_BITS 1 20993 #define PMD_X4_LATCH_STATUS_TX_DISABLE_LL_SHIFT 11 20994 20995 /* pmd_x4 :: latch_status :: rx_clk_vld_live [10:10] */ 20996 #define PMD_X4_LATCH_STATUS_RX_CLK_VLD_LIVE_MASK 0x0400 20997 #define PMD_X4_LATCH_STATUS_RX_CLK_VLD_LIVE_ALIGN 0 20998 #define PMD_X4_LATCH_STATUS_RX_CLK_VLD_LIVE_BITS 1 20999 #define PMD_X4_LATCH_STATUS_RX_CLK_VLD_LIVE_SHIFT 10 21000 21001 /* pmd_x4 :: latch_status :: signal_detect_live [09:09] */ 21002 #define PMD_X4_LATCH_STATUS_SIGNAL_DETECT_LIVE_MASK 0x0200 21003 #define PMD_X4_LATCH_STATUS_SIGNAL_DETECT_LIVE_ALIGN 0 21004 #define PMD_X4_LATCH_STATUS_SIGNAL_DETECT_LIVE_BITS 1 21005 #define PMD_X4_LATCH_STATUS_SIGNAL_DETECT_LIVE_SHIFT 9 21006 21007 /* pmd_x4 :: latch_status :: rx_lock_live [08:08] */ 21008 #define PMD_X4_LATCH_STATUS_RX_LOCK_LIVE_MASK 0x0100 21009 #define PMD_X4_LATCH_STATUS_RX_LOCK_LIVE_ALIGN 0 21010 #define PMD_X4_LATCH_STATUS_RX_LOCK_LIVE_BITS 1 21011 #define PMD_X4_LATCH_STATUS_RX_LOCK_LIVE_SHIFT 8 21012 21013 /* pmd_x4 :: latch_status :: reserved1 [07:06] */ 21014 #define PMD_X4_LATCH_STATUS_RESERVED1_MASK 0x00c0 21015 #define PMD_X4_LATCH_STATUS_RESERVED1_ALIGN 0 21016 #define PMD_X4_LATCH_STATUS_RESERVED1_BITS 2 21017 #define PMD_X4_LATCH_STATUS_RESERVED1_SHIFT 6 21018 21019 /* pmd_x4 :: latch_status :: rx_clk_vld_LH [05:05] */ 21020 #define PMD_X4_LATCH_STATUS_RX_CLK_VLD_LH_MASK 0x0020 21021 #define PMD_X4_LATCH_STATUS_RX_CLK_VLD_LH_ALIGN 0 21022 #define PMD_X4_LATCH_STATUS_RX_CLK_VLD_LH_BITS 1 21023 #define PMD_X4_LATCH_STATUS_RX_CLK_VLD_LH_SHIFT 5 21024 21025 /* pmd_x4 :: latch_status :: rx_clk_vld_LL [04:04] */ 21026 #define PMD_X4_LATCH_STATUS_RX_CLK_VLD_LL_MASK 0x0010 21027 #define PMD_X4_LATCH_STATUS_RX_CLK_VLD_LL_ALIGN 0 21028 #define PMD_X4_LATCH_STATUS_RX_CLK_VLD_LL_BITS 1 21029 #define PMD_X4_LATCH_STATUS_RX_CLK_VLD_LL_SHIFT 4 21030 21031 /* pmd_x4 :: latch_status :: signal_detect_LH [03:03] */ 21032 #define PMD_X4_LATCH_STATUS_SIGNAL_DETECT_LH_MASK 0x0008 21033 #define PMD_X4_LATCH_STATUS_SIGNAL_DETECT_LH_ALIGN 0 21034 #define PMD_X4_LATCH_STATUS_SIGNAL_DETECT_LH_BITS 1 21035 #define PMD_X4_LATCH_STATUS_SIGNAL_DETECT_LH_SHIFT 3 21036 21037 /* pmd_x4 :: latch_status :: signal_detect_LL [02:02] */ 21038 #define PMD_X4_LATCH_STATUS_SIGNAL_DETECT_LL_MASK 0x0004 21039 #define PMD_X4_LATCH_STATUS_SIGNAL_DETECT_LL_ALIGN 0 21040 #define PMD_X4_LATCH_STATUS_SIGNAL_DETECT_LL_BITS 1 21041 #define PMD_X4_LATCH_STATUS_SIGNAL_DETECT_LL_SHIFT 2 21042 21043 /* pmd_x4 :: latch_status :: rx_lock_LH [01:01] */ 21044 #define PMD_X4_LATCH_STATUS_RX_LOCK_LH_MASK 0x0002 21045 #define PMD_X4_LATCH_STATUS_RX_LOCK_LH_ALIGN 0 21046 #define PMD_X4_LATCH_STATUS_RX_LOCK_LH_BITS 1 21047 #define PMD_X4_LATCH_STATUS_RX_LOCK_LH_SHIFT 1 21048 21049 /* pmd_x4 :: latch_status :: rx_lock_LL [00:00] */ 21050 #define PMD_X4_LATCH_STATUS_RX_LOCK_LL_MASK 0x0001 21051 #define PMD_X4_LATCH_STATUS_RX_LOCK_LL_ALIGN 0 21052 #define PMD_X4_LATCH_STATUS_RX_LOCK_LL_BITS 1 21053 #define PMD_X4_LATCH_STATUS_RX_LOCK_LL_SHIFT 0 21054 21055 21056 /**************************************************************************** 21057 * pmd_x4 :: override 21058 */ 21059 /* pmd_x4 :: override :: reserved0 [15:08] */ 21060 #define PMD_X4_OVERRIDE_RESERVED0_MASK 0xff00 21061 #define PMD_X4_OVERRIDE_RESERVED0_ALIGN 0 21062 #define PMD_X4_OVERRIDE_RESERVED0_BITS 8 21063 #define PMD_X4_OVERRIDE_RESERVED0_SHIFT 8 21064 21065 /* pmd_x4 :: override :: tx_clk_vld_ovrd [07:07] */ 21066 #define PMD_X4_OVERRIDE_TX_CLK_VLD_OVRD_MASK 0x0080 21067 #define PMD_X4_OVERRIDE_TX_CLK_VLD_OVRD_ALIGN 0 21068 #define PMD_X4_OVERRIDE_TX_CLK_VLD_OVRD_BITS 1 21069 #define PMD_X4_OVERRIDE_TX_CLK_VLD_OVRD_SHIFT 7 21070 21071 /* pmd_x4 :: override :: ln_dp_h_rstb_oen [06:06] */ 21072 #define PMD_X4_OVERRIDE_LN_DP_H_RSTB_OEN_MASK 0x0040 21073 #define PMD_X4_OVERRIDE_LN_DP_H_RSTB_OEN_ALIGN 0 21074 #define PMD_X4_OVERRIDE_LN_DP_H_RSTB_OEN_BITS 1 21075 #define PMD_X4_OVERRIDE_LN_DP_H_RSTB_OEN_SHIFT 6 21076 21077 /* pmd_x4 :: override :: tx_disable_oen [05:05] */ 21078 #define PMD_X4_OVERRIDE_TX_DISABLE_OEN_MASK 0x0020 21079 #define PMD_X4_OVERRIDE_TX_DISABLE_OEN_ALIGN 0 21080 #define PMD_X4_OVERRIDE_TX_DISABLE_OEN_BITS 1 21081 #define PMD_X4_OVERRIDE_TX_DISABLE_OEN_SHIFT 5 21082 21083 /* pmd_x4 :: override :: osr_mode_oen [04:04] */ 21084 #define PMD_X4_OVERRIDE_OSR_MODE_OEN_MASK 0x0010 21085 #define PMD_X4_OVERRIDE_OSR_MODE_OEN_ALIGN 0 21086 #define PMD_X4_OVERRIDE_OSR_MODE_OEN_BITS 1 21087 #define PMD_X4_OVERRIDE_OSR_MODE_OEN_SHIFT 4 21088 21089 /* pmd_x4 :: override :: lane_mode_oen [03:03] */ 21090 #define PMD_X4_OVERRIDE_LANE_MODE_OEN_MASK 0x0008 21091 #define PMD_X4_OVERRIDE_LANE_MODE_OEN_ALIGN 0 21092 #define PMD_X4_OVERRIDE_LANE_MODE_OEN_BITS 1 21093 #define PMD_X4_OVERRIDE_LANE_MODE_OEN_SHIFT 3 21094 21095 /* pmd_x4 :: override :: rx_clk_vld_ovrd [02:02] */ 21096 #define PMD_X4_OVERRIDE_RX_CLK_VLD_OVRD_MASK 0x0004 21097 #define PMD_X4_OVERRIDE_RX_CLK_VLD_OVRD_ALIGN 0 21098 #define PMD_X4_OVERRIDE_RX_CLK_VLD_OVRD_BITS 1 21099 #define PMD_X4_OVERRIDE_RX_CLK_VLD_OVRD_SHIFT 2 21100 21101 /* pmd_x4 :: override :: signal_detect_ovrd [01:01] */ 21102 #define PMD_X4_OVERRIDE_SIGNAL_DETECT_OVRD_MASK 0x0002 21103 #define PMD_X4_OVERRIDE_SIGNAL_DETECT_OVRD_ALIGN 0 21104 #define PMD_X4_OVERRIDE_SIGNAL_DETECT_OVRD_BITS 1 21105 #define PMD_X4_OVERRIDE_SIGNAL_DETECT_OVRD_SHIFT 1 21106 21107 /* pmd_x4 :: override :: rx_lock_ovrd [00:00] */ 21108 #define PMD_X4_OVERRIDE_RX_LOCK_OVRD_MASK 0x0001 21109 #define PMD_X4_OVERRIDE_RX_LOCK_OVRD_ALIGN 0 21110 #define PMD_X4_OVERRIDE_RX_LOCK_OVRD_BITS 1 21111 #define PMD_X4_OVERRIDE_RX_LOCK_OVRD_SHIFT 0 21112 21113 21114 /**************************************************************************** 21115 * pmd_x4 :: eee_control 21116 */ 21117 /* pmd_x4 :: eee_control :: reserved0 [15:03] */ 21118 #define PMD_X4_EEE_CONTROL_RESERVED0_MASK 0xfff8 21119 #define PMD_X4_EEE_CONTROL_RESERVED0_ALIGN 0 21120 #define PMD_X4_EEE_CONTROL_RESERVED0_BITS 13 21121 #define PMD_X4_EEE_CONTROL_RESERVED0_SHIFT 3 21122 21123 /* pmd_x4 :: eee_control :: rx_mode [02:02] */ 21124 #define PMD_X4_EEE_CONTROL_RX_MODE_MASK 0x0004 21125 #define PMD_X4_EEE_CONTROL_RX_MODE_ALIGN 0 21126 #define PMD_X4_EEE_CONTROL_RX_MODE_BITS 1 21127 #define PMD_X4_EEE_CONTROL_RX_MODE_SHIFT 2 21128 21129 /* pmd_x4 :: eee_control :: tx_mode [01:00] */ 21130 #define PMD_X4_EEE_CONTROL_TX_MODE_MASK 0x0003 21131 #define PMD_X4_EEE_CONTROL_TX_MODE_ALIGN 0 21132 #define PMD_X4_EEE_CONTROL_TX_MODE_BITS 2 21133 #define PMD_X4_EEE_CONTROL_TX_MODE_SHIFT 0 21134 21135 21136 /**************************************************************************** 21137 * pmd_x4 :: eee_status 21138 */ 21139 /* pmd_x4 :: eee_status :: reserved0 [15:01] */ 21140 #define PMD_X4_EEE_STATUS_RESERVED0_MASK 0xfffe 21141 #define PMD_X4_EEE_STATUS_RESERVED0_ALIGN 0 21142 #define PMD_X4_EEE_STATUS_RESERVED0_BITS 15 21143 #define PMD_X4_EEE_STATUS_RESERVED0_SHIFT 1 21144 21145 /* pmd_x4 :: eee_status :: energy_detect [00:00] */ 21146 #define PMD_X4_EEE_STATUS_ENERGY_DETECT_MASK 0x0001 21147 #define PMD_X4_EEE_STATUS_ENERGY_DETECT_ALIGN 0 21148 #define PMD_X4_EEE_STATUS_ENERGY_DETECT_BITS 1 21149 #define PMD_X4_EEE_STATUS_ENERGY_DETECT_SHIFT 0 21150 21151 21152 /**************************************************************************** 21153 * pmd_x4 :: ui_value_hi 21154 */ 21155 /* pmd_x4 :: ui_value_hi :: ui_frac_m1_to_m16 [15:00] */ 21156 #define PMD_X4_UI_VALUE_HI_UI_FRAC_M1_TO_M16_MASK 0xffff 21157 #define PMD_X4_UI_VALUE_HI_UI_FRAC_M1_TO_M16_ALIGN 0 21158 #define PMD_X4_UI_VALUE_HI_UI_FRAC_M1_TO_M16_BITS 16 21159 #define PMD_X4_UI_VALUE_HI_UI_FRAC_M1_TO_M16_SHIFT 0 21160 21161 21162 /**************************************************************************** 21163 * pmd_x4 :: ui_value_lo 21164 */ 21165 /* pmd_x4 :: ui_value_lo :: ui_frac_m17_to_m23 [15:09] */ 21166 #define PMD_X4_UI_VALUE_LO_UI_FRAC_M17_TO_M23_MASK 0xfe00 21167 #define PMD_X4_UI_VALUE_LO_UI_FRAC_M17_TO_M23_ALIGN 0 21168 #define PMD_X4_UI_VALUE_LO_UI_FRAC_M17_TO_M23_BITS 7 21169 #define PMD_X4_UI_VALUE_LO_UI_FRAC_M17_TO_M23_SHIFT 9 21170 21171 /* pmd_x4 :: ui_value_lo :: reserved0 [08:00] */ 21172 #define PMD_X4_UI_VALUE_LO_RESERVED0_MASK 0x01ff 21173 #define PMD_X4_UI_VALUE_LO_RESERVED0_ALIGN 0 21174 #define PMD_X4_UI_VALUE_LO_RESERVED0_BITS 9 21175 #define PMD_X4_UI_VALUE_LO_RESERVED0_SHIFT 0 21176 21177 21178 /**************************************************************************** 21179 * pmd_x4 :: rx_fixed_latency 21180 */ 21181 /* pmd_x4 :: rx_fixed_latency :: rx_pmd_latency_in_ns [15:10] */ 21182 #define PMD_X4_RX_FIXED_LATENCY_RX_PMD_LATENCY_IN_NS_MASK 0xfc00 21183 #define PMD_X4_RX_FIXED_LATENCY_RX_PMD_LATENCY_IN_NS_ALIGN 0 21184 #define PMD_X4_RX_FIXED_LATENCY_RX_PMD_LATENCY_IN_NS_BITS 6 21185 #define PMD_X4_RX_FIXED_LATENCY_RX_PMD_LATENCY_IN_NS_SHIFT 10 21186 21187 /* pmd_x4 :: rx_fixed_latency :: rx_pmd_latency_in_frac_ns [09:00] */ 21188 #define PMD_X4_RX_FIXED_LATENCY_RX_PMD_LATENCY_IN_FRAC_NS_MASK 0x03ff 21189 #define PMD_X4_RX_FIXED_LATENCY_RX_PMD_LATENCY_IN_FRAC_NS_ALIGN 0 21190 #define PMD_X4_RX_FIXED_LATENCY_RX_PMD_LATENCY_IN_FRAC_NS_BITS 10 21191 #define PMD_X4_RX_FIXED_LATENCY_RX_PMD_LATENCY_IN_FRAC_NS_SHIFT 0 21192 21193 21194 /**************************************************************************** 21195 * pmd_x4 :: tx_fixed_latency 21196 */ 21197 /* pmd_x4 :: tx_fixed_latency :: tx_pmd_latency_in_ns [15:10] */ 21198 #define PMD_X4_TX_FIXED_LATENCY_TX_PMD_LATENCY_IN_NS_MASK 0xfc00 21199 #define PMD_X4_TX_FIXED_LATENCY_TX_PMD_LATENCY_IN_NS_ALIGN 0 21200 #define PMD_X4_TX_FIXED_LATENCY_TX_PMD_LATENCY_IN_NS_BITS 6 21201 #define PMD_X4_TX_FIXED_LATENCY_TX_PMD_LATENCY_IN_NS_SHIFT 10 21202 21203 /* pmd_x4 :: tx_fixed_latency :: tx_pmd_latency_in_frac_ns [09:00] */ 21204 #define PMD_X4_TX_FIXED_LATENCY_TX_PMD_LATENCY_IN_FRAC_NS_MASK 0x03ff 21205 #define PMD_X4_TX_FIXED_LATENCY_TX_PMD_LATENCY_IN_FRAC_NS_ALIGN 0 21206 #define PMD_X4_TX_FIXED_LATENCY_TX_PMD_LATENCY_IN_FRAC_NS_BITS 10 21207 #define PMD_X4_TX_FIXED_LATENCY_TX_PMD_LATENCY_IN_FRAC_NS_SHIFT 0 21208 21209 21210 /**************************************************************************** 21211 * TSC_TSC_USER4_sc_x4_control 21212 */ 21213 /**************************************************************************** 21214 * sc_x4_control :: control 21215 */ 21216 /* sc_x4_control :: control :: reserved0 [15:10] */ 21217 #define SC_X4_CONTROL_CONTROL_RESERVED0_MASK 0xfc00 21218 #define SC_X4_CONTROL_CONTROL_RESERVED0_ALIGN 0 21219 #define SC_X4_CONTROL_CONTROL_RESERVED0_BITS 6 21220 #define SC_X4_CONTROL_CONTROL_RESERVED0_SHIFT 10 21221 21222 /* sc_x4_control :: control :: sc_ignore_tx_data_vld [09:09] */ 21223 #define SC_X4_CONTROL_CONTROL_SC_IGNORE_TX_DATA_VLD_MASK 0x0200 21224 #define SC_X4_CONTROL_CONTROL_SC_IGNORE_TX_DATA_VLD_ALIGN 0 21225 #define SC_X4_CONTROL_CONTROL_SC_IGNORE_TX_DATA_VLD_BITS 1 21226 #define SC_X4_CONTROL_CONTROL_SC_IGNORE_TX_DATA_VLD_SHIFT 9 21227 21228 /* sc_x4_control :: control :: sw_speed_change [08:08] */ 21229 #define SC_X4_CONTROL_CONTROL_SW_SPEED_CHANGE_MASK 0x0100 21230 #define SC_X4_CONTROL_CONTROL_SW_SPEED_CHANGE_ALIGN 0 21231 #define SC_X4_CONTROL_CONTROL_SW_SPEED_CHANGE_BITS 1 21232 #define SC_X4_CONTROL_CONTROL_SW_SPEED_CHANGE_SHIFT 8 21233 21234 /* sc_x4_control :: control :: reserved1 [07:06] */ 21235 #define SC_X4_CONTROL_CONTROL_RESERVED1_MASK 0x00c0 21236 #define SC_X4_CONTROL_CONTROL_RESERVED1_ALIGN 0 21237 #define SC_X4_CONTROL_CONTROL_RESERVED1_BITS 2 21238 #define SC_X4_CONTROL_CONTROL_RESERVED1_SHIFT 6 21239 21240 /* sc_x4_control :: control :: SW_SPEED_ID [05:00] */ 21241 #define SC_X4_CONTROL_CONTROL_SW_SPEED_ID_MASK 0x003f 21242 #define SC_X4_CONTROL_CONTROL_SW_SPEED_ID_ALIGN 0 21243 #define SC_X4_CONTROL_CONTROL_SW_SPEED_ID_BITS 6 21244 #define SC_X4_CONTROL_CONTROL_SW_SPEED_ID_SHIFT 0 21245 21246 21247 /**************************************************************************** 21248 * sc_x4_control :: status 21249 */ 21250 /* sc_x4_control :: status :: reserved0 [15:02] */ 21251 #define SC_X4_CONTROL_STATUS_RESERVED0_MASK 0xfffc 21252 #define SC_X4_CONTROL_STATUS_RESERVED0_ALIGN 0 21253 #define SC_X4_CONTROL_STATUS_RESERVED0_BITS 14 21254 #define SC_X4_CONTROL_STATUS_RESERVED0_SHIFT 2 21255 21256 /* sc_x4_control :: status :: sw_speed_config_vld [01:01] */ 21257 #define SC_X4_CONTROL_STATUS_SW_SPEED_CONFIG_VLD_MASK 0x0002 21258 #define SC_X4_CONTROL_STATUS_SW_SPEED_CONFIG_VLD_ALIGN 0 21259 #define SC_X4_CONTROL_STATUS_SW_SPEED_CONFIG_VLD_BITS 1 21260 #define SC_X4_CONTROL_STATUS_SW_SPEED_CONFIG_VLD_SHIFT 1 21261 21262 /* sc_x4_control :: status :: sw_speed_change_done [00:00] */ 21263 #define SC_X4_CONTROL_STATUS_SW_SPEED_CHANGE_DONE_MASK 0x0001 21264 #define SC_X4_CONTROL_STATUS_SW_SPEED_CHANGE_DONE_ALIGN 0 21265 #define SC_X4_CONTROL_STATUS_SW_SPEED_CHANGE_DONE_BITS 1 21266 #define SC_X4_CONTROL_STATUS_SW_SPEED_CHANGE_DONE_SHIFT 0 21267 21268 21269 /**************************************************************************** 21270 * sc_x4_control :: debug 21271 */ 21272 /* sc_x4_control :: debug :: sc_fsm_status [15:00] */ 21273 #define SC_X4_CONTROL_DEBUG_SC_FSM_STATUS_MASK 0xffff 21274 #define SC_X4_CONTROL_DEBUG_SC_FSM_STATUS_ALIGN 0 21275 #define SC_X4_CONTROL_DEBUG_SC_FSM_STATUS_BITS 16 21276 #define SC_X4_CONTROL_DEBUG_SC_FSM_STATUS_SHIFT 0 21277 21278 21279 /**************************************************************************** 21280 * sc_x4_control :: spare0 21281 */ 21282 /* sc_x4_control :: spare0 :: spare0 [15:00] */ 21283 #define SC_X4_CONTROL_SPARE0_SPARE0_MASK 0xffff 21284 #define SC_X4_CONTROL_SPARE0_SPARE0_ALIGN 0 21285 #define SC_X4_CONTROL_SPARE0_SPARE0_BITS 16 21286 #define SC_X4_CONTROL_SPARE0_SPARE0_SHIFT 0 21287 21288 21289 /**************************************************************************** 21290 * sc_x4_control :: SW_spare1 21291 */ 21292 /* sc_x4_control :: SW_spare1 :: spare1 [15:00] */ 21293 #define SC_X4_CONTROL_SW_SPARE1_SPARE1_MASK 0xffff 21294 #define SC_X4_CONTROL_SW_SPARE1_SPARE1_ALIGN 0 21295 #define SC_X4_CONTROL_SW_SPARE1_SPARE1_BITS 16 21296 #define SC_X4_CONTROL_SW_SPARE1_SPARE1_SHIFT 0 21297 21298 21299 /**************************************************************************** 21300 * TSC_TSC_USER4_sc_x4_final_config_status 21301 */ 21302 /**************************************************************************** 21303 * sc_x4_final_config_status :: resolved_speed 21304 */ 21305 /* sc_x4_final_config_status :: resolved_speed :: speed [15:10] */ 21306 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_MASK 0xfc00 21307 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_ALIGN 0 21308 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_BITS 6 21309 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_SPEED_SHIFT 10 21310 21311 /* sc_x4_final_config_status :: resolved_speed :: reserved0 [09:00] */ 21312 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_RESERVED0_MASK 0x03ff 21313 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_RESERVED0_ALIGN 0 21314 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_RESERVED0_BITS 10 21315 #define SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED_RESERVED0_SHIFT 0 21316 21317 21318 /**************************************************************************** 21319 * sc_x4_final_config_status :: fec_status 21320 */ 21321 /* sc_x4_final_config_status :: fec_status :: reserved0 [15:08] */ 21322 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_RESERVED0_MASK 0xff00 21323 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_RESERVED0_ALIGN 0 21324 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_RESERVED0_BITS 8 21325 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_RESERVED0_SHIFT 8 21326 21327 /* sc_x4_final_config_status :: fec_status :: t_RS_FEC_fec_mode [07:05] */ 21328 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_T_RS_FEC_FEC_MODE_MASK 0x00e0 21329 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_T_RS_FEC_FEC_MODE_ALIGN 0 21330 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_T_RS_FEC_FEC_MODE_BITS 3 21331 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_T_RS_FEC_FEC_MODE_SHIFT 5 21332 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_T_RS_FEC_FEC_MODE_NO_RS_FEC_FEC 0 21333 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_T_RS_FEC_FEC_MODE_N_A 1 21334 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_T_RS_FEC_FEC_MODE_RS_FEC_SINGLE_LANE_BRCM_PROP 2 21335 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_T_RS_FEC_FEC_MODE_RS_FEC_DUAL_LANE_BRCM_PROP 3 21336 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_T_RS_FEC_FEC_MODE_RS_FEC_QUAD_LANE 4 21337 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_T_RS_FEC_FEC_MODE_IEEE_25G_RS_FEC_SINGLE_LANE 5 21338 21339 /* sc_x4_final_config_status :: fec_status :: r_RS_FEC_fec_mode [04:02] */ 21340 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_R_RS_FEC_FEC_MODE_MASK 0x001c 21341 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_R_RS_FEC_FEC_MODE_ALIGN 0 21342 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_R_RS_FEC_FEC_MODE_BITS 3 21343 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_R_RS_FEC_FEC_MODE_SHIFT 2 21344 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_R_RS_FEC_FEC_MODE_NO_RS_FEC_FEC 0 21345 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_R_RS_FEC_FEC_MODE_N_A 1 21346 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_R_RS_FEC_FEC_MODE_RS_FEC_SINGLE_LANE_BRCM_PROP 2 21347 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_R_RS_FEC_FEC_MODE_RS_FEC_DUAL_LANE_BRCM_PROP 3 21348 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_R_RS_FEC_FEC_MODE_RS_FEC_QUAD_LANE 4 21349 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_R_RS_FEC_FEC_MODE_IEEE_25G_RS_FEC_SINGLE_LANE 5 21350 21351 /* sc_x4_final_config_status :: fec_status :: t_fec_enable [01:01] */ 21352 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_T_FEC_ENABLE_MASK 0x0002 21353 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_T_FEC_ENABLE_ALIGN 0 21354 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_T_FEC_ENABLE_BITS 1 21355 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_T_FEC_ENABLE_SHIFT 1 21356 21357 /* sc_x4_final_config_status :: fec_status :: r_fec_enable [00:00] */ 21358 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_R_FEC_ENABLE_MASK 0x0001 21359 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_R_FEC_ENABLE_ALIGN 0 21360 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_R_FEC_ENABLE_BITS 1 21361 #define SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS_R_FEC_ENABLE_SHIFT 0 21362 21363 21364 /**************************************************************************** 21365 * TSC_TSC_USER4_TX_X4_Control0 21366 */ 21367 /**************************************************************************** 21368 * TX_X4_Control0 :: RS_SYMBOL 21369 */ 21370 /* TX_X4_Control0 :: RS_SYMBOL :: reserved0 [15:10] */ 21371 #define TX_X4_CONTROL0_RS_SYMBOL_RESERVED0_MASK 0xfc00 21372 #define TX_X4_CONTROL0_RS_SYMBOL_RESERVED0_ALIGN 0 21373 #define TX_X4_CONTROL0_RS_SYMBOL_RESERVED0_BITS 6 21374 #define TX_X4_CONTROL0_RS_SYMBOL_RESERVED0_SHIFT 10 21375 21376 /* TX_X4_Control0 :: RS_SYMBOL :: symbol_value [09:00] */ 21377 #define TX_X4_CONTROL0_RS_SYMBOL_SYMBOL_VALUE_MASK 0x03ff 21378 #define TX_X4_CONTROL0_RS_SYMBOL_SYMBOL_VALUE_ALIGN 0 21379 #define TX_X4_CONTROL0_RS_SYMBOL_SYMBOL_VALUE_BITS 10 21380 #define TX_X4_CONTROL0_RS_SYMBOL_SYMBOL_VALUE_SHIFT 0 21381 21382 21383 /**************************************************************************** 21384 * TX_X4_Control0 :: misc 21385 */ 21386 /* TX_X4_Control0 :: misc :: reserved0 [15:05] */ 21387 #define TX_X4_CONTROL0_MISC_RESERVED0_MASK 0xffe0 21388 #define TX_X4_CONTROL0_MISC_RESERVED0_ALIGN 0 21389 #define TX_X4_CONTROL0_MISC_RESERVED0_BITS 11 21390 #define TX_X4_CONTROL0_MISC_RESERVED0_SHIFT 5 21391 21392 /* TX_X4_Control0 :: misc :: tx_li_enable [04:04] */ 21393 #define TX_X4_CONTROL0_MISC_TX_LI_ENABLE_MASK 0x0010 21394 #define TX_X4_CONTROL0_MISC_TX_LI_ENABLE_ALIGN 0 21395 #define TX_X4_CONTROL0_MISC_TX_LI_ENABLE_BITS 1 21396 #define TX_X4_CONTROL0_MISC_TX_LI_ENABLE_SHIFT 4 21397 21398 /* TX_X4_Control0 :: misc :: tx_lf_enable [03:03] */ 21399 #define TX_X4_CONTROL0_MISC_TX_LF_ENABLE_MASK 0x0008 21400 #define TX_X4_CONTROL0_MISC_TX_LF_ENABLE_ALIGN 0 21401 #define TX_X4_CONTROL0_MISC_TX_LF_ENABLE_BITS 1 21402 #define TX_X4_CONTROL0_MISC_TX_LF_ENABLE_SHIFT 3 21403 21404 /* TX_X4_Control0 :: misc :: tx_rf_enable [02:02] */ 21405 #define TX_X4_CONTROL0_MISC_TX_RF_ENABLE_MASK 0x0004 21406 #define TX_X4_CONTROL0_MISC_TX_RF_ENABLE_ALIGN 0 21407 #define TX_X4_CONTROL0_MISC_TX_RF_ENABLE_BITS 1 21408 #define TX_X4_CONTROL0_MISC_TX_RF_ENABLE_SHIFT 2 21409 21410 /* TX_X4_Control0 :: misc :: rstb_tx_lane [01:01] */ 21411 #define TX_X4_CONTROL0_MISC_RSTB_TX_LANE_MASK 0x0002 21412 #define TX_X4_CONTROL0_MISC_RSTB_TX_LANE_ALIGN 0 21413 #define TX_X4_CONTROL0_MISC_RSTB_TX_LANE_BITS 1 21414 #define TX_X4_CONTROL0_MISC_RSTB_TX_LANE_SHIFT 1 21415 21416 /* TX_X4_Control0 :: misc :: enable_tx_lane [00:00] */ 21417 #define TX_X4_CONTROL0_MISC_ENABLE_TX_LANE_MASK 0x0001 21418 #define TX_X4_CONTROL0_MISC_ENABLE_TX_LANE_ALIGN 0 21419 #define TX_X4_CONTROL0_MISC_ENABLE_TX_LANE_BITS 1 21420 #define TX_X4_CONTROL0_MISC_ENABLE_TX_LANE_SHIFT 0 21421 21422 21423 /**************************************************************************** 21424 * TX_X4_Control0 :: tx_ts_control 21425 */ 21426 /* TX_X4_Control0 :: tx_ts_control :: reserved0 [15:03] */ 21427 #define TX_X4_CONTROL0_TX_TS_CONTROL_RESERVED0_MASK 0xfff8 21428 #define TX_X4_CONTROL0_TX_TS_CONTROL_RESERVED0_ALIGN 0 21429 #define TX_X4_CONTROL0_TX_TS_CONTROL_RESERVED0_BITS 13 21430 #define TX_X4_CONTROL0_TX_TS_CONTROL_RESERVED0_SHIFT 3 21431 21432 /* TX_X4_Control0 :: tx_ts_control :: tsts_interrupt_en [02:02] */ 21433 #define TX_X4_CONTROL0_TX_TS_CONTROL_TSTS_INTERRUPT_EN_MASK 0x0004 21434 #define TX_X4_CONTROL0_TX_TS_CONTROL_TSTS_INTERRUPT_EN_ALIGN 0 21435 #define TX_X4_CONTROL0_TX_TS_CONTROL_TSTS_INTERRUPT_EN_BITS 1 21436 #define TX_X4_CONTROL0_TX_TS_CONTROL_TSTS_INTERRUPT_EN_SHIFT 2 21437 21438 /* TX_X4_Control0 :: tx_ts_control :: tx_sfd_ts_en [01:01] */ 21439 #define TX_X4_CONTROL0_TX_TS_CONTROL_TX_SFD_TS_EN_MASK 0x0002 21440 #define TX_X4_CONTROL0_TX_TS_CONTROL_TX_SFD_TS_EN_ALIGN 0 21441 #define TX_X4_CONTROL0_TX_TS_CONTROL_TX_SFD_TS_EN_BITS 1 21442 #define TX_X4_CONTROL0_TX_TS_CONTROL_TX_SFD_TS_EN_SHIFT 1 21443 21444 /* TX_X4_Control0 :: tx_ts_control :: OSTS_Pipeline_Enable [00:00] */ 21445 #define TX_X4_CONTROL0_TX_TS_CONTROL_OSTS_PIPELINE_ENABLE_MASK 0x0001 21446 #define TX_X4_CONTROL0_TX_TS_CONTROL_OSTS_PIPELINE_ENABLE_ALIGN 0 21447 #define TX_X4_CONTROL0_TX_TS_CONTROL_OSTS_PIPELINE_ENABLE_BITS 1 21448 #define TX_X4_CONTROL0_TX_TS_CONTROL_OSTS_PIPELINE_ENABLE_SHIFT 0 21449 21450 21451 /**************************************************************************** 21452 * TSC_TSC_USER4_TX_X4_Status0 21453 */ 21454 /**************************************************************************** 21455 * TX_X4_Status0 :: encode_status_0 21456 */ 21457 /* TX_X4_Status0 :: encode_status_0 :: reserved0 [15:13] */ 21458 #define TX_X4_STATUS0_ENCODE_STATUS_0_RESERVED0_MASK 0xe000 21459 #define TX_X4_STATUS0_ENCODE_STATUS_0_RESERVED0_ALIGN 0 21460 #define TX_X4_STATUS0_ENCODE_STATUS_0_RESERVED0_BITS 3 21461 #define TX_X4_STATUS0_ENCODE_STATUS_0_RESERVED0_SHIFT 13 21462 21463 /* TX_X4_Status0 :: encode_status_0 :: cl82_t_type_coded [12:10] */ 21464 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL82_T_TYPE_CODED_MASK 0x1c00 21465 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL82_T_TYPE_CODED_ALIGN 0 21466 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL82_T_TYPE_CODED_BITS 3 21467 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL82_T_TYPE_CODED_SHIFT 10 21468 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL82_T_TYPE_CODED_T_TYPE_B1 5 21469 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL82_T_TYPE_CODED_T_TYPE_C 4 21470 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL82_T_TYPE_CODED_T_TYPE_S 3 21471 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL82_T_TYPE_CODED_T_TYPE_T 2 21472 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL82_T_TYPE_CODED_T_TYPE_D 1 21473 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL82_T_TYPE_CODED_T_TYPE_E 0 21474 21475 /* TX_X4_Status0 :: encode_status_0 :: cl82_txsm_state [09:07] */ 21476 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL82_TXSM_STATE_MASK 0x0380 21477 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL82_TXSM_STATE_ALIGN 0 21478 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL82_TXSM_STATE_BITS 3 21479 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL82_TXSM_STATE_SHIFT 7 21480 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL82_TXSM_STATE_TX_E 4 21481 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL82_TXSM_STATE_TX_T 3 21482 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL82_TXSM_STATE_TX_D 2 21483 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL82_TXSM_STATE_TX_C 1 21484 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL82_TXSM_STATE_TX_INIT 0 21485 21486 /* TX_X4_Status0 :: encode_status_0 :: cl49_t_type_coded [06:03] */ 21487 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_T_TYPE_CODED_MASK 0x0078 21488 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_T_TYPE_CODED_ALIGN 0 21489 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_T_TYPE_CODED_BITS 4 21490 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_T_TYPE_CODED_SHIFT 3 21491 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_T_TYPE_CODED_BAD_T_TYPE 15 21492 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_T_TYPE_CODED_T_TYPE_B0 11 21493 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_T_TYPE_CODED_T_TYPE_OB 10 21494 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_T_TYPE_CODED_T_TYPE_B1 9 21495 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_T_TYPE_CODED_T_TYPE_DB 8 21496 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_T_TYPE_CODED_T_TYPE_FC 7 21497 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_T_TYPE_CODED_T_TYPE_TB 6 21498 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_T_TYPE_CODED_T_TYPE_LI 5 21499 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_T_TYPE_CODED_T_TYPE_C 4 21500 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_T_TYPE_CODED_T_TYPE_S 3 21501 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_T_TYPE_CODED_T_TYPE_T 2 21502 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_T_TYPE_CODED_T_TYPE_D 1 21503 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_T_TYPE_CODED_T_TYPE_E 0 21504 21505 /* TX_X4_Status0 :: encode_status_0 :: cl49_txsm_state [02:00] */ 21506 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_TXSM_STATE_MASK 0x0007 21507 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_TXSM_STATE_ALIGN 0 21508 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_TXSM_STATE_BITS 3 21509 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_TXSM_STATE_SHIFT 0 21510 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_TXSM_STATE_TX_LI 5 21511 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_TXSM_STATE_TX_E 4 21512 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_TXSM_STATE_TX_T 3 21513 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_TXSM_STATE_TX_D 2 21514 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_TXSM_STATE_TX_C 1 21515 #define TX_X4_STATUS0_ENCODE_STATUS_0_CL49_TXSM_STATE_TX_INIT 0 21516 21517 21518 /**************************************************************************** 21519 * TX_X4_Status0 :: encode_status_1 21520 */ 21521 /* TX_X4_Status0 :: encode_status_1 :: reserved0 [15:12] */ 21522 #define TX_X4_STATUS0_ENCODE_STATUS_1_RESERVED0_MASK 0xf000 21523 #define TX_X4_STATUS0_ENCODE_STATUS_1_RESERVED0_ALIGN 0 21524 #define TX_X4_STATUS0_ENCODE_STATUS_1_RESERVED0_BITS 4 21525 #define TX_X4_STATUS0_ENCODE_STATUS_1_RESERVED0_SHIFT 12 21526 21527 /* TX_X4_Status0 :: encode_status_1 :: ltxsm_state [11:07] */ 21528 #define TX_X4_STATUS0_ENCODE_STATUS_1_LTXSM_STATE_MASK 0x0f80 21529 #define TX_X4_STATUS0_ENCODE_STATUS_1_LTXSM_STATE_ALIGN 0 21530 #define TX_X4_STATUS0_ENCODE_STATUS_1_LTXSM_STATE_BITS 5 21531 #define TX_X4_STATUS0_ENCODE_STATUS_1_LTXSM_STATE_SHIFT 7 21532 #define TX_X4_STATUS0_ENCODE_STATUS_1_LTXSM_STATE_TX_E 16 21533 #define TX_X4_STATUS0_ENCODE_STATUS_1_LTXSM_STATE_TX_T 8 21534 #define TX_X4_STATUS0_ENCODE_STATUS_1_LTXSM_STATE_TX_D 4 21535 #define TX_X4_STATUS0_ENCODE_STATUS_1_LTXSM_STATE_TX_C 2 21536 #define TX_X4_STATUS0_ENCODE_STATUS_1_LTXSM_STATE_TX_INIT 1 21537 21538 /* TX_X4_Status0 :: encode_status_1 :: cl49_tx_fault_det [06:06] */ 21539 #define TX_X4_STATUS0_ENCODE_STATUS_1_CL49_TX_FAULT_DET_MASK 0x0040 21540 #define TX_X4_STATUS0_ENCODE_STATUS_1_CL49_TX_FAULT_DET_ALIGN 0 21541 #define TX_X4_STATUS0_ENCODE_STATUS_1_CL49_TX_FAULT_DET_BITS 1 21542 #define TX_X4_STATUS0_ENCODE_STATUS_1_CL49_TX_FAULT_DET_SHIFT 6 21543 21544 /* TX_X4_Status0 :: encode_status_1 :: cl49_ltxsm_state [05:00] */ 21545 #define TX_X4_STATUS0_ENCODE_STATUS_1_CL49_LTXSM_STATE_MASK 0x003f 21546 #define TX_X4_STATUS0_ENCODE_STATUS_1_CL49_LTXSM_STATE_ALIGN 0 21547 #define TX_X4_STATUS0_ENCODE_STATUS_1_CL49_LTXSM_STATE_BITS 6 21548 #define TX_X4_STATUS0_ENCODE_STATUS_1_CL49_LTXSM_STATE_SHIFT 0 21549 #define TX_X4_STATUS0_ENCODE_STATUS_1_CL49_LTXSM_STATE_TX_LI 32 21550 #define TX_X4_STATUS0_ENCODE_STATUS_1_CL49_LTXSM_STATE_TX_E 16 21551 #define TX_X4_STATUS0_ENCODE_STATUS_1_CL49_LTXSM_STATE_TX_T 8 21552 #define TX_X4_STATUS0_ENCODE_STATUS_1_CL49_LTXSM_STATE_TX_D 4 21553 #define TX_X4_STATUS0_ENCODE_STATUS_1_CL49_LTXSM_STATE_TX_C 2 21554 #define TX_X4_STATUS0_ENCODE_STATUS_1_CL49_LTXSM_STATE_TX_INIT 1 21555 21556 21557 /**************************************************************************** 21558 * TX_X4_Status0 :: pcs_status_live 21559 */ 21560 /* TX_X4_Status0 :: pcs_status_live :: reserved0 [15:04] */ 21561 #define TX_X4_STATUS0_PCS_STATUS_LIVE_RESERVED0_MASK 0xfff0 21562 #define TX_X4_STATUS0_PCS_STATUS_LIVE_RESERVED0_ALIGN 0 21563 #define TX_X4_STATUS0_PCS_STATUS_LIVE_RESERVED0_BITS 12 21564 #define TX_X4_STATUS0_PCS_STATUS_LIVE_RESERVED0_SHIFT 4 21565 21566 /* TX_X4_Status0 :: pcs_status_live :: tx_LOCAL_FAULT [03:03] */ 21567 #define TX_X4_STATUS0_PCS_STATUS_LIVE_TX_LOCAL_FAULT_MASK 0x0008 21568 #define TX_X4_STATUS0_PCS_STATUS_LIVE_TX_LOCAL_FAULT_ALIGN 0 21569 #define TX_X4_STATUS0_PCS_STATUS_LIVE_TX_LOCAL_FAULT_BITS 1 21570 #define TX_X4_STATUS0_PCS_STATUS_LIVE_TX_LOCAL_FAULT_SHIFT 3 21571 21572 /* TX_X4_Status0 :: pcs_status_live :: tx_REMOTE_FAULT [02:02] */ 21573 #define TX_X4_STATUS0_PCS_STATUS_LIVE_TX_REMOTE_FAULT_MASK 0x0004 21574 #define TX_X4_STATUS0_PCS_STATUS_LIVE_TX_REMOTE_FAULT_ALIGN 0 21575 #define TX_X4_STATUS0_PCS_STATUS_LIVE_TX_REMOTE_FAULT_BITS 1 21576 #define TX_X4_STATUS0_PCS_STATUS_LIVE_TX_REMOTE_FAULT_SHIFT 2 21577 21578 /* TX_X4_Status0 :: pcs_status_live :: tx_LINK_INTERRUPT [01:01] */ 21579 #define TX_X4_STATUS0_PCS_STATUS_LIVE_TX_LINK_INTERRUPT_MASK 0x0002 21580 #define TX_X4_STATUS0_PCS_STATUS_LIVE_TX_LINK_INTERRUPT_ALIGN 0 21581 #define TX_X4_STATUS0_PCS_STATUS_LIVE_TX_LINK_INTERRUPT_BITS 1 21582 #define TX_X4_STATUS0_PCS_STATUS_LIVE_TX_LINK_INTERRUPT_SHIFT 1 21583 21584 /* TX_X4_Status0 :: pcs_status_live :: tx_LPI_RECEIVED [00:00] */ 21585 #define TX_X4_STATUS0_PCS_STATUS_LIVE_TX_LPI_RECEIVED_MASK 0x0001 21586 #define TX_X4_STATUS0_PCS_STATUS_LIVE_TX_LPI_RECEIVED_ALIGN 0 21587 #define TX_X4_STATUS0_PCS_STATUS_LIVE_TX_LPI_RECEIVED_BITS 1 21588 #define TX_X4_STATUS0_PCS_STATUS_LIVE_TX_LPI_RECEIVED_SHIFT 0 21589 21590 21591 /**************************************************************************** 21592 * TX_X4_Status0 :: pcs_status_latched 21593 */ 21594 /* TX_X4_Status0 :: pcs_status_latched :: reserved0 [15:04] */ 21595 #define TX_X4_STATUS0_PCS_STATUS_LATCHED_RESERVED0_MASK 0xfff0 21596 #define TX_X4_STATUS0_PCS_STATUS_LATCHED_RESERVED0_ALIGN 0 21597 #define TX_X4_STATUS0_PCS_STATUS_LATCHED_RESERVED0_BITS 12 21598 #define TX_X4_STATUS0_PCS_STATUS_LATCHED_RESERVED0_SHIFT 4 21599 21600 /* TX_X4_Status0 :: pcs_status_latched :: LINK_INTERRUPT_LH [03:03] */ 21601 #define TX_X4_STATUS0_PCS_STATUS_LATCHED_LINK_INTERRUPT_LH_MASK 0x0008 21602 #define TX_X4_STATUS0_PCS_STATUS_LATCHED_LINK_INTERRUPT_LH_ALIGN 0 21603 #define TX_X4_STATUS0_PCS_STATUS_LATCHED_LINK_INTERRUPT_LH_BITS 1 21604 #define TX_X4_STATUS0_PCS_STATUS_LATCHED_LINK_INTERRUPT_LH_SHIFT 3 21605 21606 /* TX_X4_Status0 :: pcs_status_latched :: LOCAL_FAULT_LH [02:02] */ 21607 #define TX_X4_STATUS0_PCS_STATUS_LATCHED_LOCAL_FAULT_LH_MASK 0x0004 21608 #define TX_X4_STATUS0_PCS_STATUS_LATCHED_LOCAL_FAULT_LH_ALIGN 0 21609 #define TX_X4_STATUS0_PCS_STATUS_LATCHED_LOCAL_FAULT_LH_BITS 1 21610 #define TX_X4_STATUS0_PCS_STATUS_LATCHED_LOCAL_FAULT_LH_SHIFT 2 21611 21612 /* TX_X4_Status0 :: pcs_status_latched :: REMOTE_FAULT_LH [01:01] */ 21613 #define TX_X4_STATUS0_PCS_STATUS_LATCHED_REMOTE_FAULT_LH_MASK 0x0002 21614 #define TX_X4_STATUS0_PCS_STATUS_LATCHED_REMOTE_FAULT_LH_ALIGN 0 21615 #define TX_X4_STATUS0_PCS_STATUS_LATCHED_REMOTE_FAULT_LH_BITS 1 21616 #define TX_X4_STATUS0_PCS_STATUS_LATCHED_REMOTE_FAULT_LH_SHIFT 1 21617 21618 /* TX_X4_Status0 :: pcs_status_latched :: LPI_RECEIVED_LH [00:00] */ 21619 #define TX_X4_STATUS0_PCS_STATUS_LATCHED_LPI_RECEIVED_LH_MASK 0x0001 21620 #define TX_X4_STATUS0_PCS_STATUS_LATCHED_LPI_RECEIVED_LH_ALIGN 0 21621 #define TX_X4_STATUS0_PCS_STATUS_LATCHED_LPI_RECEIVED_LH_BITS 1 21622 #define TX_X4_STATUS0_PCS_STATUS_LATCHED_LPI_RECEIVED_LH_SHIFT 0 21623 21624 21625 /**************************************************************************** 21626 * TX_X4_Status0 :: tx_1588_timestamp_status 21627 */ 21628 /* TX_X4_Status0 :: tx_1588_timestamp_status :: ts_entry_valid [15:15] */ 21629 #define TX_X4_STATUS0_TX_1588_TIMESTAMP_STATUS_TS_ENTRY_VALID_MASK 0x8000 21630 #define TX_X4_STATUS0_TX_1588_TIMESTAMP_STATUS_TS_ENTRY_VALID_ALIGN 0 21631 #define TX_X4_STATUS0_TX_1588_TIMESTAMP_STATUS_TS_ENTRY_VALID_BITS 1 21632 #define TX_X4_STATUS0_TX_1588_TIMESTAMP_STATUS_TS_ENTRY_VALID_SHIFT 15 21633 21634 /* TX_X4_Status0 :: tx_1588_timestamp_status :: reserved0 [14:05] */ 21635 #define TX_X4_STATUS0_TX_1588_TIMESTAMP_STATUS_RESERVED0_MASK 0x7fe0 21636 #define TX_X4_STATUS0_TX_1588_TIMESTAMP_STATUS_RESERVED0_ALIGN 0 21637 #define TX_X4_STATUS0_TX_1588_TIMESTAMP_STATUS_RESERVED0_BITS 10 21638 #define TX_X4_STATUS0_TX_1588_TIMESTAMP_STATUS_RESERVED0_SHIFT 5 21639 21640 /* TX_X4_Status0 :: tx_1588_timestamp_status :: tsts_interrupt_status [04:04] */ 21641 #define TX_X4_STATUS0_TX_1588_TIMESTAMP_STATUS_TSTS_INTERRUPT_STATUS_MASK 0x0010 21642 #define TX_X4_STATUS0_TX_1588_TIMESTAMP_STATUS_TSTS_INTERRUPT_STATUS_ALIGN 0 21643 #define TX_X4_STATUS0_TX_1588_TIMESTAMP_STATUS_TSTS_INTERRUPT_STATUS_BITS 1 21644 #define TX_X4_STATUS0_TX_1588_TIMESTAMP_STATUS_TSTS_INTERRUPT_STATUS_SHIFT 4 21645 21646 /* TX_X4_Status0 :: tx_1588_timestamp_status :: ts_sub_ns [03:00] */ 21647 #define TX_X4_STATUS0_TX_1588_TIMESTAMP_STATUS_TS_SUB_NS_MASK 0x000f 21648 #define TX_X4_STATUS0_TX_1588_TIMESTAMP_STATUS_TS_SUB_NS_ALIGN 0 21649 #define TX_X4_STATUS0_TX_1588_TIMESTAMP_STATUS_TS_SUB_NS_BITS 4 21650 #define TX_X4_STATUS0_TX_1588_TIMESTAMP_STATUS_TS_SUB_NS_SHIFT 0 21651 21652 21653 /**************************************************************************** 21654 * TX_X4_Status0 :: tx_1588_timestamp_hi 21655 */ 21656 /* TX_X4_Status0 :: tx_1588_timestamp_hi :: ts_in_ns_hi [15:00] */ 21657 #define TX_X4_STATUS0_TX_1588_TIMESTAMP_HI_TS_IN_NS_HI_MASK 0xffff 21658 #define TX_X4_STATUS0_TX_1588_TIMESTAMP_HI_TS_IN_NS_HI_ALIGN 0 21659 #define TX_X4_STATUS0_TX_1588_TIMESTAMP_HI_TS_IN_NS_HI_BITS 16 21660 #define TX_X4_STATUS0_TX_1588_TIMESTAMP_HI_TS_IN_NS_HI_SHIFT 0 21661 21662 21663 /**************************************************************************** 21664 * TX_X4_Status0 :: tx_1588_timestamp_lo 21665 */ 21666 /* TX_X4_Status0 :: tx_1588_timestamp_lo :: ts_in_ns_lo [15:00] */ 21667 #define TX_X4_STATUS0_TX_1588_TIMESTAMP_LO_TS_IN_NS_LO_MASK 0xffff 21668 #define TX_X4_STATUS0_TX_1588_TIMESTAMP_LO_TS_IN_NS_LO_ALIGN 0 21669 #define TX_X4_STATUS0_TX_1588_TIMESTAMP_LO_TS_IN_NS_LO_BITS 16 21670 #define TX_X4_STATUS0_TX_1588_TIMESTAMP_LO_TS_IN_NS_LO_SHIFT 0 21671 21672 21673 /**************************************************************************** 21674 * TX_X4_Status0 :: tx_ts_seq_id 21675 */ 21676 /* TX_X4_Status0 :: tx_ts_seq_id :: ts_seqid [15:00] */ 21677 #define TX_X4_STATUS0_TX_TS_SEQ_ID_TS_SEQID_MASK 0xffff 21678 #define TX_X4_STATUS0_TX_TS_SEQ_ID_TS_SEQID_ALIGN 0 21679 #define TX_X4_STATUS0_TX_TS_SEQ_ID_TS_SEQID_BITS 16 21680 #define TX_X4_STATUS0_TX_TS_SEQ_ID_TS_SEQID_SHIFT 0 21681 21682 21683 /**************************************************************************** 21684 * TSC_TSC_USER4_RX_X4_Control0 21685 */ 21686 /**************************************************************************** 21687 * RX_X4_Control0 :: RS_FEC_timer 21688 */ 21689 /* RX_X4_Control0 :: RS_FEC_timer :: reserved0 [15:13] */ 21690 #define RX_X4_CONTROL0_RS_FEC_TIMER_RESERVED0_MASK 0xe000 21691 #define RX_X4_CONTROL0_RS_FEC_TIMER_RESERVED0_ALIGN 0 21692 #define RX_X4_CONTROL0_RS_FEC_TIMER_RESERVED0_BITS 3 21693 #define RX_X4_CONTROL0_RS_FEC_TIMER_RESERVED0_SHIFT 13 21694 21695 /* RX_X4_Control0 :: RS_FEC_timer :: corruption_period [12:00] */ 21696 #define RX_X4_CONTROL0_RS_FEC_TIMER_CORRUPTION_PERIOD_MASK 0x1fff 21697 #define RX_X4_CONTROL0_RS_FEC_TIMER_CORRUPTION_PERIOD_ALIGN 0 21698 #define RX_X4_CONTROL0_RS_FEC_TIMER_CORRUPTION_PERIOD_BITS 13 21699 #define RX_X4_CONTROL0_RS_FEC_TIMER_CORRUPTION_PERIOD_SHIFT 0 21700 21701 21702 /**************************************************************************** 21703 * RX_X4_Control0 :: RS_FEC_rx_control_0 21704 */ 21705 /* RX_X4_Control0 :: RS_FEC_rx_control_0 :: CW_BAD_ENABLE [15:15] */ 21706 #define RX_X4_CONTROL0_RS_FEC_RX_CONTROL_0_CW_BAD_ENABLE_MASK 0x8000 21707 #define RX_X4_CONTROL0_RS_FEC_RX_CONTROL_0_CW_BAD_ENABLE_ALIGN 0 21708 #define RX_X4_CONTROL0_RS_FEC_RX_CONTROL_0_CW_BAD_ENABLE_BITS 1 21709 #define RX_X4_CONTROL0_RS_FEC_RX_CONTROL_0_CW_BAD_ENABLE_SHIFT 15 21710 21711 /* RX_X4_Control0 :: RS_FEC_rx_control_0 :: reserved0 [14:00] */ 21712 #define RX_X4_CONTROL0_RS_FEC_RX_CONTROL_0_RESERVED0_MASK 0x7fff 21713 #define RX_X4_CONTROL0_RS_FEC_RX_CONTROL_0_RESERVED0_ALIGN 0 21714 #define RX_X4_CONTROL0_RS_FEC_RX_CONTROL_0_RESERVED0_BITS 15 21715 #define RX_X4_CONTROL0_RS_FEC_RX_CONTROL_0_RESERVED0_SHIFT 0 21716 21717 21718 /**************************************************************************** 21719 * RX_X4_Control0 :: decode_control_0 21720 */ 21721 /* RX_X4_Control0 :: decode_control_0 :: reserved0 [15:05] */ 21722 #define RX_X4_CONTROL0_DECODE_CONTROL_0_RESERVED0_MASK 0xffe0 21723 #define RX_X4_CONTROL0_DECODE_CONTROL_0_RESERVED0_ALIGN 0 21724 #define RX_X4_CONTROL0_DECODE_CONTROL_0_RESERVED0_BITS 11 21725 #define RX_X4_CONTROL0_DECODE_CONTROL_0_RESERVED0_SHIFT 5 21726 21727 /* RX_X4_Control0 :: decode_control_0 :: r_test_mode_cfg [04:04] */ 21728 #define RX_X4_CONTROL0_DECODE_CONTROL_0_R_TEST_MODE_CFG_MASK 0x0010 21729 #define RX_X4_CONTROL0_DECODE_CONTROL_0_R_TEST_MODE_CFG_ALIGN 0 21730 #define RX_X4_CONTROL0_DECODE_CONTROL_0_R_TEST_MODE_CFG_BITS 1 21731 #define RX_X4_CONTROL0_DECODE_CONTROL_0_R_TEST_MODE_CFG_SHIFT 4 21732 21733 /* RX_X4_Control0 :: decode_control_0 :: rx_li_enable [03:03] */ 21734 #define RX_X4_CONTROL0_DECODE_CONTROL_0_RX_LI_ENABLE_MASK 0x0008 21735 #define RX_X4_CONTROL0_DECODE_CONTROL_0_RX_LI_ENABLE_ALIGN 0 21736 #define RX_X4_CONTROL0_DECODE_CONTROL_0_RX_LI_ENABLE_BITS 1 21737 #define RX_X4_CONTROL0_DECODE_CONTROL_0_RX_LI_ENABLE_SHIFT 3 21738 21739 /* RX_X4_Control0 :: decode_control_0 :: rx_lf_enable [02:02] */ 21740 #define RX_X4_CONTROL0_DECODE_CONTROL_0_RX_LF_ENABLE_MASK 0x0004 21741 #define RX_X4_CONTROL0_DECODE_CONTROL_0_RX_LF_ENABLE_ALIGN 0 21742 #define RX_X4_CONTROL0_DECODE_CONTROL_0_RX_LF_ENABLE_BITS 1 21743 #define RX_X4_CONTROL0_DECODE_CONTROL_0_RX_LF_ENABLE_SHIFT 2 21744 21745 /* RX_X4_Control0 :: decode_control_0 :: rx_rf_enable [01:01] */ 21746 #define RX_X4_CONTROL0_DECODE_CONTROL_0_RX_RF_ENABLE_MASK 0x0002 21747 #define RX_X4_CONTROL0_DECODE_CONTROL_0_RX_RF_ENABLE_ALIGN 0 21748 #define RX_X4_CONTROL0_DECODE_CONTROL_0_RX_RF_ENABLE_BITS 1 21749 #define RX_X4_CONTROL0_DECODE_CONTROL_0_RX_RF_ENABLE_SHIFT 1 21750 21751 /* RX_X4_Control0 :: decode_control_0 :: LPI_ENABLE [00:00] */ 21752 #define RX_X4_CONTROL0_DECODE_CONTROL_0_LPI_ENABLE_MASK 0x0001 21753 #define RX_X4_CONTROL0_DECODE_CONTROL_0_LPI_ENABLE_ALIGN 0 21754 #define RX_X4_CONTROL0_DECODE_CONTROL_0_LPI_ENABLE_BITS 1 21755 #define RX_X4_CONTROL0_DECODE_CONTROL_0_LPI_ENABLE_SHIFT 0 21756 21757 21758 /**************************************************************************** 21759 * RX_X4_Control0 :: pma_control_0 21760 */ 21761 /* RX_X4_Control0 :: pma_control_0 :: reserved0 [15:01] */ 21762 #define RX_X4_CONTROL0_PMA_CONTROL_0_RESERVED0_MASK 0xfffe 21763 #define RX_X4_CONTROL0_PMA_CONTROL_0_RESERVED0_ALIGN 0 21764 #define RX_X4_CONTROL0_PMA_CONTROL_0_RESERVED0_BITS 15 21765 #define RX_X4_CONTROL0_PMA_CONTROL_0_RESERVED0_SHIFT 1 21766 21767 /* RX_X4_Control0 :: pma_control_0 :: rstb_lane [00:00] */ 21768 #define RX_X4_CONTROL0_PMA_CONTROL_0_RSTB_LANE_MASK 0x0001 21769 #define RX_X4_CONTROL0_PMA_CONTROL_0_RSTB_LANE_ALIGN 0 21770 #define RX_X4_CONTROL0_PMA_CONTROL_0_RSTB_LANE_BITS 1 21771 #define RX_X4_CONTROL0_PMA_CONTROL_0_RSTB_LANE_SHIFT 0 21772 21773 21774 /**************************************************************************** 21775 * RX_X4_Control0 :: link_control 21776 */ 21777 /* RX_X4_Control0 :: link_control :: reserved0 [15:01] */ 21778 #define RX_X4_CONTROL0_LINK_CONTROL_RESERVED0_MASK 0xfffe 21779 #define RX_X4_CONTROL0_LINK_CONTROL_RESERVED0_ALIGN 0 21780 #define RX_X4_CONTROL0_LINK_CONTROL_RESERVED0_BITS 15 21781 #define RX_X4_CONTROL0_LINK_CONTROL_RESERVED0_SHIFT 1 21782 21783 /* RX_X4_Control0 :: link_control :: latch_linkdown_enable [00:00] */ 21784 #define RX_X4_CONTROL0_LINK_CONTROL_LATCH_LINKDOWN_ENABLE_MASK 0x0001 21785 #define RX_X4_CONTROL0_LINK_CONTROL_LATCH_LINKDOWN_ENABLE_ALIGN 0 21786 #define RX_X4_CONTROL0_LINK_CONTROL_LATCH_LINKDOWN_ENABLE_BITS 1 21787 #define RX_X4_CONTROL0_LINK_CONTROL_LATCH_LINKDOWN_ENABLE_SHIFT 0 21788 21789 21790 /**************************************************************************** 21791 * RX_X4_Control0 :: rx_ts_control 21792 */ 21793 /* RX_X4_Control0 :: rx_ts_control :: reserved0 [15:02] */ 21794 #define RX_X4_CONTROL0_RX_TS_CONTROL_RESERVED0_MASK 0xfffc 21795 #define RX_X4_CONTROL0_RX_TS_CONTROL_RESERVED0_ALIGN 0 21796 #define RX_X4_CONTROL0_RX_TS_CONTROL_RESERVED0_BITS 14 21797 #define RX_X4_CONTROL0_RX_TS_CONTROL_RESERVED0_SHIFT 2 21798 21799 /* RX_X4_Control0 :: rx_ts_control :: ts_update_enable [01:01] */ 21800 #define RX_X4_CONTROL0_RX_TS_CONTROL_TS_UPDATE_ENABLE_MASK 0x0002 21801 #define RX_X4_CONTROL0_RX_TS_CONTROL_TS_UPDATE_ENABLE_ALIGN 0 21802 #define RX_X4_CONTROL0_RX_TS_CONTROL_TS_UPDATE_ENABLE_BITS 1 21803 #define RX_X4_CONTROL0_RX_TS_CONTROL_TS_UPDATE_ENABLE_SHIFT 1 21804 21805 /* RX_X4_Control0 :: rx_ts_control :: rx_sfd_ts_en [00:00] */ 21806 #define RX_X4_CONTROL0_RX_TS_CONTROL_RX_SFD_TS_EN_MASK 0x0001 21807 #define RX_X4_CONTROL0_RX_TS_CONTROL_RX_SFD_TS_EN_ALIGN 0 21808 #define RX_X4_CONTROL0_RX_TS_CONTROL_RX_SFD_TS_EN_BITS 1 21809 #define RX_X4_CONTROL0_RX_TS_CONTROL_RX_SFD_TS_EN_SHIFT 0 21810 21811 21812 /**************************************************************************** 21813 * RX_X4_Control0 :: deskew_vl_0_offset 21814 */ 21815 /* RX_X4_Control0 :: deskew_vl_0_offset :: rx_deskew_vl0_int_offset [15:07] */ 21816 #define RX_X4_CONTROL0_DESKEW_VL_0_OFFSET_RX_DESKEW_VL0_INT_OFFSET_MASK 0xff80 21817 #define RX_X4_CONTROL0_DESKEW_VL_0_OFFSET_RX_DESKEW_VL0_INT_OFFSET_ALIGN 0 21818 #define RX_X4_CONTROL0_DESKEW_VL_0_OFFSET_RX_DESKEW_VL0_INT_OFFSET_BITS 9 21819 #define RX_X4_CONTROL0_DESKEW_VL_0_OFFSET_RX_DESKEW_VL0_INT_OFFSET_SHIFT 7 21820 21821 /* RX_X4_Control0 :: deskew_vl_0_offset :: rx_deskew_vl0_frac_offset [06:00] */ 21822 #define RX_X4_CONTROL0_DESKEW_VL_0_OFFSET_RX_DESKEW_VL0_FRAC_OFFSET_MASK 0x007f 21823 #define RX_X4_CONTROL0_DESKEW_VL_0_OFFSET_RX_DESKEW_VL0_FRAC_OFFSET_ALIGN 0 21824 #define RX_X4_CONTROL0_DESKEW_VL_0_OFFSET_RX_DESKEW_VL0_FRAC_OFFSET_BITS 7 21825 #define RX_X4_CONTROL0_DESKEW_VL_0_OFFSET_RX_DESKEW_VL0_FRAC_OFFSET_SHIFT 0 21826 21827 21828 /**************************************************************************** 21829 * RX_X4_Control0 :: deskew_vl_1_offset 21830 */ 21831 /* RX_X4_Control0 :: deskew_vl_1_offset :: rx_deskew_vl1_int_offset [15:07] */ 21832 #define RX_X4_CONTROL0_DESKEW_VL_1_OFFSET_RX_DESKEW_VL1_INT_OFFSET_MASK 0xff80 21833 #define RX_X4_CONTROL0_DESKEW_VL_1_OFFSET_RX_DESKEW_VL1_INT_OFFSET_ALIGN 0 21834 #define RX_X4_CONTROL0_DESKEW_VL_1_OFFSET_RX_DESKEW_VL1_INT_OFFSET_BITS 9 21835 #define RX_X4_CONTROL0_DESKEW_VL_1_OFFSET_RX_DESKEW_VL1_INT_OFFSET_SHIFT 7 21836 21837 /* RX_X4_Control0 :: deskew_vl_1_offset :: rx_deskew_vl1_frac_offset [06:00] */ 21838 #define RX_X4_CONTROL0_DESKEW_VL_1_OFFSET_RX_DESKEW_VL1_FRAC_OFFSET_MASK 0x007f 21839 #define RX_X4_CONTROL0_DESKEW_VL_1_OFFSET_RX_DESKEW_VL1_FRAC_OFFSET_ALIGN 0 21840 #define RX_X4_CONTROL0_DESKEW_VL_1_OFFSET_RX_DESKEW_VL1_FRAC_OFFSET_BITS 7 21841 #define RX_X4_CONTROL0_DESKEW_VL_1_OFFSET_RX_DESKEW_VL1_FRAC_OFFSET_SHIFT 0 21842 21843 21844 /**************************************************************************** 21845 * RX_X4_Control0 :: deskew_vl_2_offset 21846 */ 21847 /* RX_X4_Control0 :: deskew_vl_2_offset :: rx_deskew_vl2_int_offset [15:07] */ 21848 #define RX_X4_CONTROL0_DESKEW_VL_2_OFFSET_RX_DESKEW_VL2_INT_OFFSET_MASK 0xff80 21849 #define RX_X4_CONTROL0_DESKEW_VL_2_OFFSET_RX_DESKEW_VL2_INT_OFFSET_ALIGN 0 21850 #define RX_X4_CONTROL0_DESKEW_VL_2_OFFSET_RX_DESKEW_VL2_INT_OFFSET_BITS 9 21851 #define RX_X4_CONTROL0_DESKEW_VL_2_OFFSET_RX_DESKEW_VL2_INT_OFFSET_SHIFT 7 21852 21853 /* RX_X4_Control0 :: deskew_vl_2_offset :: rx_deskew_vl2_frac_offset [06:00] */ 21854 #define RX_X4_CONTROL0_DESKEW_VL_2_OFFSET_RX_DESKEW_VL2_FRAC_OFFSET_MASK 0x007f 21855 #define RX_X4_CONTROL0_DESKEW_VL_2_OFFSET_RX_DESKEW_VL2_FRAC_OFFSET_ALIGN 0 21856 #define RX_X4_CONTROL0_DESKEW_VL_2_OFFSET_RX_DESKEW_VL2_FRAC_OFFSET_BITS 7 21857 #define RX_X4_CONTROL0_DESKEW_VL_2_OFFSET_RX_DESKEW_VL2_FRAC_OFFSET_SHIFT 0 21858 21859 21860 /**************************************************************************** 21861 * RX_X4_Control0 :: deskew_vl_3_offset 21862 */ 21863 /* RX_X4_Control0 :: deskew_vl_3_offset :: rx_deskew_vl3_int_offset [15:07] */ 21864 #define RX_X4_CONTROL0_DESKEW_VL_3_OFFSET_RX_DESKEW_VL3_INT_OFFSET_MASK 0xff80 21865 #define RX_X4_CONTROL0_DESKEW_VL_3_OFFSET_RX_DESKEW_VL3_INT_OFFSET_ALIGN 0 21866 #define RX_X4_CONTROL0_DESKEW_VL_3_OFFSET_RX_DESKEW_VL3_INT_OFFSET_BITS 9 21867 #define RX_X4_CONTROL0_DESKEW_VL_3_OFFSET_RX_DESKEW_VL3_INT_OFFSET_SHIFT 7 21868 21869 /* RX_X4_Control0 :: deskew_vl_3_offset :: rx_deskew_vl3_frac_offset [06:00] */ 21870 #define RX_X4_CONTROL0_DESKEW_VL_3_OFFSET_RX_DESKEW_VL3_FRAC_OFFSET_MASK 0x007f 21871 #define RX_X4_CONTROL0_DESKEW_VL_3_OFFSET_RX_DESKEW_VL3_FRAC_OFFSET_ALIGN 0 21872 #define RX_X4_CONTROL0_DESKEW_VL_3_OFFSET_RX_DESKEW_VL3_FRAC_OFFSET_BITS 7 21873 #define RX_X4_CONTROL0_DESKEW_VL_3_OFFSET_RX_DESKEW_VL3_FRAC_OFFSET_SHIFT 0 21874 21875 21876 /**************************************************************************** 21877 * RX_X4_Control0 :: deskew_vl_4_offset 21878 */ 21879 /* RX_X4_Control0 :: deskew_vl_4_offset :: rx_deskew_vl4_int_offset [15:07] */ 21880 #define RX_X4_CONTROL0_DESKEW_VL_4_OFFSET_RX_DESKEW_VL4_INT_OFFSET_MASK 0xff80 21881 #define RX_X4_CONTROL0_DESKEW_VL_4_OFFSET_RX_DESKEW_VL4_INT_OFFSET_ALIGN 0 21882 #define RX_X4_CONTROL0_DESKEW_VL_4_OFFSET_RX_DESKEW_VL4_INT_OFFSET_BITS 9 21883 #define RX_X4_CONTROL0_DESKEW_VL_4_OFFSET_RX_DESKEW_VL4_INT_OFFSET_SHIFT 7 21884 21885 /* RX_X4_Control0 :: deskew_vl_4_offset :: rx_deskew_vl4_frac_offset [06:00] */ 21886 #define RX_X4_CONTROL0_DESKEW_VL_4_OFFSET_RX_DESKEW_VL4_FRAC_OFFSET_MASK 0x007f 21887 #define RX_X4_CONTROL0_DESKEW_VL_4_OFFSET_RX_DESKEW_VL4_FRAC_OFFSET_ALIGN 0 21888 #define RX_X4_CONTROL0_DESKEW_VL_4_OFFSET_RX_DESKEW_VL4_FRAC_OFFSET_BITS 7 21889 #define RX_X4_CONTROL0_DESKEW_VL_4_OFFSET_RX_DESKEW_VL4_FRAC_OFFSET_SHIFT 0 21890 21891 21892 /**************************************************************************** 21893 * TSC_TSC_USER4_RX_X4_Fec_Control 21894 */ 21895 /**************************************************************************** 21896 * RX_X4_Fec_Control :: fec_0 21897 */ 21898 /* RX_X4_Fec_Control :: fec_0 :: reserved0 [15:15] */ 21899 #define RX_X4_FEC_CONTROL_FEC_0_RESERVED0_MASK 0x8000 21900 #define RX_X4_FEC_CONTROL_FEC_0_RESERVED0_ALIGN 0 21901 #define RX_X4_FEC_CONTROL_FEC_0_RESERVED0_BITS 1 21902 #define RX_X4_FEC_CONTROL_FEC_0_RESERVED0_SHIFT 15 21903 21904 /* RX_X4_Fec_Control :: fec_0 :: good_parity_cnt [14:12] */ 21905 #define RX_X4_FEC_CONTROL_FEC_0_GOOD_PARITY_CNT_MASK 0x7000 21906 #define RX_X4_FEC_CONTROL_FEC_0_GOOD_PARITY_CNT_ALIGN 0 21907 #define RX_X4_FEC_CONTROL_FEC_0_GOOD_PARITY_CNT_BITS 3 21908 #define RX_X4_FEC_CONTROL_FEC_0_GOOD_PARITY_CNT_SHIFT 12 21909 21910 /* RX_X4_Fec_Control :: fec_0 :: invalid_parity_cnt [11:08] */ 21911 #define RX_X4_FEC_CONTROL_FEC_0_INVALID_PARITY_CNT_MASK 0x0f00 21912 #define RX_X4_FEC_CONTROL_FEC_0_INVALID_PARITY_CNT_ALIGN 0 21913 #define RX_X4_FEC_CONTROL_FEC_0_INVALID_PARITY_CNT_BITS 4 21914 #define RX_X4_FEC_CONTROL_FEC_0_INVALID_PARITY_CNT_SHIFT 8 21915 21916 /* RX_X4_Fec_Control :: fec_0 :: dec_max_pm [07:02] */ 21917 #define RX_X4_FEC_CONTROL_FEC_0_DEC_MAX_PM_MASK 0x00fc 21918 #define RX_X4_FEC_CONTROL_FEC_0_DEC_MAX_PM_ALIGN 0 21919 #define RX_X4_FEC_CONTROL_FEC_0_DEC_MAX_PM_BITS 6 21920 #define RX_X4_FEC_CONTROL_FEC_0_DEC_MAX_PM_SHIFT 2 21921 21922 /* RX_X4_Fec_Control :: fec_0 :: burst_err_status_mode [01:01] */ 21923 #define RX_X4_FEC_CONTROL_FEC_0_BURST_ERR_STATUS_MODE_MASK 0x0002 21924 #define RX_X4_FEC_CONTROL_FEC_0_BURST_ERR_STATUS_MODE_ALIGN 0 21925 #define RX_X4_FEC_CONTROL_FEC_0_BURST_ERR_STATUS_MODE_BITS 1 21926 #define RX_X4_FEC_CONTROL_FEC_0_BURST_ERR_STATUS_MODE_SHIFT 1 21927 21928 /* RX_X4_Fec_Control :: fec_0 :: dbg_err_mode [00:00] */ 21929 #define RX_X4_FEC_CONTROL_FEC_0_DBG_ERR_MODE_MASK 0x0001 21930 #define RX_X4_FEC_CONTROL_FEC_0_DBG_ERR_MODE_ALIGN 0 21931 #define RX_X4_FEC_CONTROL_FEC_0_DBG_ERR_MODE_BITS 1 21932 #define RX_X4_FEC_CONTROL_FEC_0_DBG_ERR_MODE_SHIFT 0 21933 21934 21935 /**************************************************************************** 21936 * RX_X4_Fec_Control :: fec_1 21937 */ 21938 /* RX_X4_Fec_Control :: fec_1 :: dec_pm_mode [15:11] */ 21939 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_MASK 0xf800 21940 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_ALIGN 0 21941 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_BITS 5 21942 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_SHIFT 11 21943 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_BURST_ERROR_11_BITS 0 21944 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_BURST_ERROR_16_BITS 1 21945 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_BURST_ERROR_17_BITS 2 21946 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_BURST_ERROR_18_BITS 3 21947 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_BURST_ERROR_19_BITS 4 21948 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_BURST_ERROR_20_BITS 5 21949 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_BURST_ERROR_21_BITS 6 21950 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_BURST_ERROR_22_BITS 7 21951 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_BURST_ERROR_23_BITS 8 21952 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_BURST_ERROR_24_BITS 9 21953 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_BURST_ERROR_25_BITS 10 21954 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_BURST_ERROR_26_BITS 11 21955 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_BURST_ERROR_27_BITS 12 21956 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_BURST_ERROR_28_BITS 13 21957 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_BURST_ERROR_29_BITS 14 21958 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_BURST_ERROR_30_BITS 15 21959 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_BURST_ERROR_31_BITS 16 21960 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_BURST_ERROR_32_BITS 17 21961 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_BURST_ERROR_33_BITS 18 21962 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_BURST_ERROR_34_BITS 19 21963 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_BURST_ERROR_35_BITS 20 21964 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_BURST_ERROR_36_BITS 21 21965 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_BURST_ERROR_37_BITS 22 21966 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_BURST_ERROR_38_BITS 23 21967 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_BURST_ERROR_39_BITS 24 21968 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_BURST_ERROR_40_BITS 25 21969 #define RX_X4_FEC_CONTROL_FEC_1_DEC_PM_MODE_BURST_ERROR_41_BITS 26 21970 21971 /* RX_X4_Fec_Control :: fec_1 :: dec_19b_burst_gap_count [10:08] */ 21972 #define RX_X4_FEC_CONTROL_FEC_1_DEC_19B_BURST_GAP_COUNT_MASK 0x0700 21973 #define RX_X4_FEC_CONTROL_FEC_1_DEC_19B_BURST_GAP_COUNT_ALIGN 0 21974 #define RX_X4_FEC_CONTROL_FEC_1_DEC_19B_BURST_GAP_COUNT_BITS 3 21975 #define RX_X4_FEC_CONTROL_FEC_1_DEC_19B_BURST_GAP_COUNT_SHIFT 8 21976 21977 /* RX_X4_Fec_Control :: fec_1 :: dec_18b_burst_gap_count [07:05] */ 21978 #define RX_X4_FEC_CONTROL_FEC_1_DEC_18B_BURST_GAP_COUNT_MASK 0x00e0 21979 #define RX_X4_FEC_CONTROL_FEC_1_DEC_18B_BURST_GAP_COUNT_ALIGN 0 21980 #define RX_X4_FEC_CONTROL_FEC_1_DEC_18B_BURST_GAP_COUNT_BITS 3 21981 #define RX_X4_FEC_CONTROL_FEC_1_DEC_18B_BURST_GAP_COUNT_SHIFT 5 21982 21983 /* RX_X4_Fec_Control :: fec_1 :: dec_17b_burst_gap_count [04:02] */ 21984 #define RX_X4_FEC_CONTROL_FEC_1_DEC_17B_BURST_GAP_COUNT_MASK 0x001c 21985 #define RX_X4_FEC_CONTROL_FEC_1_DEC_17B_BURST_GAP_COUNT_ALIGN 0 21986 #define RX_X4_FEC_CONTROL_FEC_1_DEC_17B_BURST_GAP_COUNT_BITS 3 21987 #define RX_X4_FEC_CONTROL_FEC_1_DEC_17B_BURST_GAP_COUNT_SHIFT 2 21988 21989 /* RX_X4_Fec_Control :: fec_1 :: dec_gap_count_mode [01:01] */ 21990 #define RX_X4_FEC_CONTROL_FEC_1_DEC_GAP_COUNT_MODE_MASK 0x0002 21991 #define RX_X4_FEC_CONTROL_FEC_1_DEC_GAP_COUNT_MODE_ALIGN 0 21992 #define RX_X4_FEC_CONTROL_FEC_1_DEC_GAP_COUNT_MODE_BITS 1 21993 #define RX_X4_FEC_CONTROL_FEC_1_DEC_GAP_COUNT_MODE_SHIFT 1 21994 21995 /* RX_X4_Fec_Control :: fec_1 :: reserved0 [00:00] */ 21996 #define RX_X4_FEC_CONTROL_FEC_1_RESERVED0_MASK 0x0001 21997 #define RX_X4_FEC_CONTROL_FEC_1_RESERVED0_ALIGN 0 21998 #define RX_X4_FEC_CONTROL_FEC_1_RESERVED0_BITS 1 21999 #define RX_X4_FEC_CONTROL_FEC_1_RESERVED0_SHIFT 0 22000 22001 22002 /**************************************************************************** 22003 * RX_X4_Fec_Control :: fec_2 22004 */ 22005 /* RX_X4_Fec_Control :: fec_2 :: reserved0 [15:03] */ 22006 #define RX_X4_FEC_CONTROL_FEC_2_RESERVED0_MASK 0xfff8 22007 #define RX_X4_FEC_CONTROL_FEC_2_RESERVED0_ALIGN 0 22008 #define RX_X4_FEC_CONTROL_FEC_2_RESERVED0_BITS 13 22009 #define RX_X4_FEC_CONTROL_FEC_2_RESERVED0_SHIFT 3 22010 22011 /* RX_X4_Fec_Control :: fec_2 :: fec_err_enable [02:02] */ 22012 #define RX_X4_FEC_CONTROL_FEC_2_FEC_ERR_ENABLE_MASK 0x0004 22013 #define RX_X4_FEC_CONTROL_FEC_2_FEC_ERR_ENABLE_ALIGN 0 22014 #define RX_X4_FEC_CONTROL_FEC_2_FEC_ERR_ENABLE_BITS 1 22015 #define RX_X4_FEC_CONTROL_FEC_2_FEC_ERR_ENABLE_SHIFT 2 22016 22017 /* RX_X4_Fec_Control :: fec_2 :: dbg_enable [01:01] */ 22018 #define RX_X4_FEC_CONTROL_FEC_2_DBG_ENABLE_MASK 0x0002 22019 #define RX_X4_FEC_CONTROL_FEC_2_DBG_ENABLE_ALIGN 0 22020 #define RX_X4_FEC_CONTROL_FEC_2_DBG_ENABLE_BITS 1 22021 #define RX_X4_FEC_CONTROL_FEC_2_DBG_ENABLE_SHIFT 1 22022 22023 /* RX_X4_Fec_Control :: fec_2 :: fec_error_code_all [00:00] */ 22024 #define RX_X4_FEC_CONTROL_FEC_2_FEC_ERROR_CODE_ALL_MASK 0x0001 22025 #define RX_X4_FEC_CONTROL_FEC_2_FEC_ERROR_CODE_ALL_ALIGN 0 22026 #define RX_X4_FEC_CONTROL_FEC_2_FEC_ERROR_CODE_ALL_BITS 1 22027 #define RX_X4_FEC_CONTROL_FEC_2_FEC_ERROR_CODE_ALL_SHIFT 0 22028 22029 22030 /**************************************************************************** 22031 * TSC_TSC_USER4_RX_X4_Status0 22032 */ 22033 /**************************************************************************** 22034 * RX_X4_Status0 :: blksync_status 22035 */ 22036 /* RX_X4_Status0 :: blksync_status :: reserved0 [15:06] */ 22037 #define RX_X4_STATUS0_BLKSYNC_STATUS_RESERVED0_MASK 0xffc0 22038 #define RX_X4_STATUS0_BLKSYNC_STATUS_RESERVED0_ALIGN 0 22039 #define RX_X4_STATUS0_BLKSYNC_STATUS_RESERVED0_BITS 10 22040 #define RX_X4_STATUS0_BLKSYNC_STATUS_RESERVED0_SHIFT 6 22041 22042 /* RX_X4_Status0 :: blksync_status :: bs_pmd_lock [05:05] */ 22043 #define RX_X4_STATUS0_BLKSYNC_STATUS_BS_PMD_LOCK_MASK 0x0020 22044 #define RX_X4_STATUS0_BLKSYNC_STATUS_BS_PMD_LOCK_ALIGN 0 22045 #define RX_X4_STATUS0_BLKSYNC_STATUS_BS_PMD_LOCK_BITS 1 22046 #define RX_X4_STATUS0_BLKSYNC_STATUS_BS_PMD_LOCK_SHIFT 5 22047 22048 /* RX_X4_Status0 :: blksync_status :: bs_status [04:00] */ 22049 #define RX_X4_STATUS0_BLKSYNC_STATUS_BS_STATUS_MASK 0x001f 22050 #define RX_X4_STATUS0_BLKSYNC_STATUS_BS_STATUS_ALIGN 0 22051 #define RX_X4_STATUS0_BLKSYNC_STATUS_BS_STATUS_BITS 5 22052 #define RX_X4_STATUS0_BLKSYNC_STATUS_BS_STATUS_SHIFT 0 22053 22054 22055 /**************************************************************************** 22056 * RX_X4_Status0 :: blksync_dbg0 22057 */ 22058 /* RX_X4_Status0 :: blksync_dbg0 :: lane1_debug_info [15:08] */ 22059 #define RX_X4_STATUS0_BLKSYNC_DBG0_LANE1_DEBUG_INFO_MASK 0xff00 22060 #define RX_X4_STATUS0_BLKSYNC_DBG0_LANE1_DEBUG_INFO_ALIGN 0 22061 #define RX_X4_STATUS0_BLKSYNC_DBG0_LANE1_DEBUG_INFO_BITS 8 22062 #define RX_X4_STATUS0_BLKSYNC_DBG0_LANE1_DEBUG_INFO_SHIFT 8 22063 22064 /* RX_X4_Status0 :: blksync_dbg0 :: lane0_debug_info [07:00] */ 22065 #define RX_X4_STATUS0_BLKSYNC_DBG0_LANE0_DEBUG_INFO_MASK 0x00ff 22066 #define RX_X4_STATUS0_BLKSYNC_DBG0_LANE0_DEBUG_INFO_ALIGN 0 22067 #define RX_X4_STATUS0_BLKSYNC_DBG0_LANE0_DEBUG_INFO_BITS 8 22068 #define RX_X4_STATUS0_BLKSYNC_DBG0_LANE0_DEBUG_INFO_SHIFT 0 22069 22070 22071 /**************************************************************************** 22072 * RX_X4_Status0 :: blksync_dbg1 22073 */ 22074 /* RX_X4_Status0 :: blksync_dbg1 :: lane3_debug_info [15:08] */ 22075 #define RX_X4_STATUS0_BLKSYNC_DBG1_LANE3_DEBUG_INFO_MASK 0xff00 22076 #define RX_X4_STATUS0_BLKSYNC_DBG1_LANE3_DEBUG_INFO_ALIGN 0 22077 #define RX_X4_STATUS0_BLKSYNC_DBG1_LANE3_DEBUG_INFO_BITS 8 22078 #define RX_X4_STATUS0_BLKSYNC_DBG1_LANE3_DEBUG_INFO_SHIFT 8 22079 22080 /* RX_X4_Status0 :: blksync_dbg1 :: lane2_debug_info [07:00] */ 22081 #define RX_X4_STATUS0_BLKSYNC_DBG1_LANE2_DEBUG_INFO_MASK 0x00ff 22082 #define RX_X4_STATUS0_BLKSYNC_DBG1_LANE2_DEBUG_INFO_ALIGN 0 22083 #define RX_X4_STATUS0_BLKSYNC_DBG1_LANE2_DEBUG_INFO_BITS 8 22084 #define RX_X4_STATUS0_BLKSYNC_DBG1_LANE2_DEBUG_INFO_SHIFT 0 22085 22086 22087 /**************************************************************************** 22088 * RX_X4_Status0 :: blksync_dbg2 22089 */ 22090 /* RX_X4_Status0 :: blksync_dbg2 :: reserved0 [15:08] */ 22091 #define RX_X4_STATUS0_BLKSYNC_DBG2_RESERVED0_MASK 0xff00 22092 #define RX_X4_STATUS0_BLKSYNC_DBG2_RESERVED0_ALIGN 0 22093 #define RX_X4_STATUS0_BLKSYNC_DBG2_RESERVED0_BITS 8 22094 #define RX_X4_STATUS0_BLKSYNC_DBG2_RESERVED0_SHIFT 8 22095 22096 /* RX_X4_Status0 :: blksync_dbg2 :: lane4_debug_info [07:00] */ 22097 #define RX_X4_STATUS0_BLKSYNC_DBG2_LANE4_DEBUG_INFO_MASK 0x00ff 22098 #define RX_X4_STATUS0_BLKSYNC_DBG2_LANE4_DEBUG_INFO_ALIGN 0 22099 #define RX_X4_STATUS0_BLKSYNC_DBG2_LANE4_DEBUG_INFO_BITS 8 22100 #define RX_X4_STATUS0_BLKSYNC_DBG2_LANE4_DEBUG_INFO_SHIFT 0 22101 22102 22103 /**************************************************************************** 22104 * RX_X4_Status0 :: block_lock_latched_status 22105 */ 22106 /* RX_X4_Status0 :: block_lock_latched_status :: reserved0 [15:10] */ 22107 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_RESERVED0_MASK 0xfc00 22108 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_RESERVED0_ALIGN 0 22109 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_RESERVED0_BITS 6 22110 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_RESERVED0_SHIFT 10 22111 22112 /* RX_X4_Status0 :: block_lock_latched_status :: BLOCK_LOCK_LH_4 [09:09] */ 22113 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LH_4_MASK 0x0200 22114 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LH_4_ALIGN 0 22115 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LH_4_BITS 1 22116 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LH_4_SHIFT 9 22117 22118 /* RX_X4_Status0 :: block_lock_latched_status :: BLOCK_LOCK_LL_4 [08:08] */ 22119 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LL_4_MASK 0x0100 22120 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LL_4_ALIGN 0 22121 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LL_4_BITS 1 22122 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LL_4_SHIFT 8 22123 22124 /* RX_X4_Status0 :: block_lock_latched_status :: BLOCK_LOCK_LH_3 [07:07] */ 22125 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LH_3_MASK 0x0080 22126 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LH_3_ALIGN 0 22127 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LH_3_BITS 1 22128 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LH_3_SHIFT 7 22129 22130 /* RX_X4_Status0 :: block_lock_latched_status :: BLOCK_LOCK_LL_3 [06:06] */ 22131 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LL_3_MASK 0x0040 22132 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LL_3_ALIGN 0 22133 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LL_3_BITS 1 22134 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LL_3_SHIFT 6 22135 22136 /* RX_X4_Status0 :: block_lock_latched_status :: BLOCK_LOCK_LH_2 [05:05] */ 22137 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LH_2_MASK 0x0020 22138 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LH_2_ALIGN 0 22139 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LH_2_BITS 1 22140 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LH_2_SHIFT 5 22141 22142 /* RX_X4_Status0 :: block_lock_latched_status :: BLOCK_LOCK_LL_2 [04:04] */ 22143 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LL_2_MASK 0x0010 22144 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LL_2_ALIGN 0 22145 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LL_2_BITS 1 22146 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LL_2_SHIFT 4 22147 22148 /* RX_X4_Status0 :: block_lock_latched_status :: BLOCK_LOCK_LH_1 [03:03] */ 22149 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LH_1_MASK 0x0008 22150 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LH_1_ALIGN 0 22151 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LH_1_BITS 1 22152 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LH_1_SHIFT 3 22153 22154 /* RX_X4_Status0 :: block_lock_latched_status :: BLOCK_LOCK_LL_1 [02:02] */ 22155 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LL_1_MASK 0x0004 22156 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LL_1_ALIGN 0 22157 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LL_1_BITS 1 22158 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LL_1_SHIFT 2 22159 22160 /* RX_X4_Status0 :: block_lock_latched_status :: BLOCK_LOCK_LH_0 [01:01] */ 22161 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LH_0_MASK 0x0002 22162 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LH_0_ALIGN 0 22163 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LH_0_BITS 1 22164 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LH_0_SHIFT 1 22165 22166 /* RX_X4_Status0 :: block_lock_latched_status :: BLOCK_LOCK_LL_0 [00:00] */ 22167 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LL_0_MASK 0x0001 22168 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LL_0_ALIGN 0 22169 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LL_0_BITS 1 22170 #define RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS_BLOCK_LOCK_LL_0_SHIFT 0 22171 22172 22173 /**************************************************************************** 22174 * RX_X4_Status0 :: am_lock_latched_status 22175 */ 22176 /* RX_X4_Status0 :: am_lock_latched_status :: reserved0 [15:10] */ 22177 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_RESERVED0_MASK 0xfc00 22178 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_RESERVED0_ALIGN 0 22179 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_RESERVED0_BITS 6 22180 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_RESERVED0_SHIFT 10 22181 22182 /* RX_X4_Status0 :: am_lock_latched_status :: AM_LOCK_LH_4 [09:09] */ 22183 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LH_4_MASK 0x0200 22184 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LH_4_ALIGN 0 22185 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LH_4_BITS 1 22186 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LH_4_SHIFT 9 22187 22188 /* RX_X4_Status0 :: am_lock_latched_status :: AM_LOCK_LL_4 [08:08] */ 22189 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LL_4_MASK 0x0100 22190 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LL_4_ALIGN 0 22191 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LL_4_BITS 1 22192 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LL_4_SHIFT 8 22193 22194 /* RX_X4_Status0 :: am_lock_latched_status :: AM_LOCK_LH_3 [07:07] */ 22195 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LH_3_MASK 0x0080 22196 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LH_3_ALIGN 0 22197 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LH_3_BITS 1 22198 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LH_3_SHIFT 7 22199 22200 /* RX_X4_Status0 :: am_lock_latched_status :: AM_LOCK_LL_3 [06:06] */ 22201 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LL_3_MASK 0x0040 22202 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LL_3_ALIGN 0 22203 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LL_3_BITS 1 22204 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LL_3_SHIFT 6 22205 22206 /* RX_X4_Status0 :: am_lock_latched_status :: AM_LOCK_LH_2 [05:05] */ 22207 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LH_2_MASK 0x0020 22208 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LH_2_ALIGN 0 22209 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LH_2_BITS 1 22210 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LH_2_SHIFT 5 22211 22212 /* RX_X4_Status0 :: am_lock_latched_status :: AM_LOCK_LL_2 [04:04] */ 22213 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LL_2_MASK 0x0010 22214 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LL_2_ALIGN 0 22215 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LL_2_BITS 1 22216 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LL_2_SHIFT 4 22217 22218 /* RX_X4_Status0 :: am_lock_latched_status :: AM_LOCK_LH_1 [03:03] */ 22219 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LH_1_MASK 0x0008 22220 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LH_1_ALIGN 0 22221 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LH_1_BITS 1 22222 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LH_1_SHIFT 3 22223 22224 /* RX_X4_Status0 :: am_lock_latched_status :: AM_LOCK_LL_1 [02:02] */ 22225 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LL_1_MASK 0x0004 22226 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LL_1_ALIGN 0 22227 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LL_1_BITS 1 22228 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LL_1_SHIFT 2 22229 22230 /* RX_X4_Status0 :: am_lock_latched_status :: AM_LOCK_LH_0 [01:01] */ 22231 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LH_0_MASK 0x0002 22232 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LH_0_ALIGN 0 22233 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LH_0_BITS 1 22234 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LH_0_SHIFT 1 22235 22236 /* RX_X4_Status0 :: am_lock_latched_status :: AM_LOCK_LL_0 [00:00] */ 22237 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LL_0_MASK 0x0001 22238 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LL_0_ALIGN 0 22239 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LL_0_BITS 1 22240 #define RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS_AM_LOCK_LL_0_SHIFT 0 22241 22242 22243 /**************************************************************************** 22244 * RX_X4_Status0 :: pcs_live_status_0 22245 */ 22246 /* RX_X4_Status0 :: pcs_live_status_0 :: reserved0 [15:10] */ 22247 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_RESERVED0_MASK 0xfc00 22248 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_RESERVED0_ALIGN 0 22249 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_RESERVED0_BITS 6 22250 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_RESERVED0_SHIFT 10 22251 22252 /* RX_X4_Status0 :: pcs_live_status_0 :: BLOCK_LOCK_4 [09:09] */ 22253 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_BLOCK_LOCK_4_MASK 0x0200 22254 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_BLOCK_LOCK_4_ALIGN 0 22255 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_BLOCK_LOCK_4_BITS 1 22256 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_BLOCK_LOCK_4_SHIFT 9 22257 22258 /* RX_X4_Status0 :: pcs_live_status_0 :: BLOCK_LOCK_3 [08:08] */ 22259 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_BLOCK_LOCK_3_MASK 0x0100 22260 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_BLOCK_LOCK_3_ALIGN 0 22261 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_BLOCK_LOCK_3_BITS 1 22262 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_BLOCK_LOCK_3_SHIFT 8 22263 22264 /* RX_X4_Status0 :: pcs_live_status_0 :: BLOCK_LOCK_2 [07:07] */ 22265 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_BLOCK_LOCK_2_MASK 0x0080 22266 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_BLOCK_LOCK_2_ALIGN 0 22267 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_BLOCK_LOCK_2_BITS 1 22268 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_BLOCK_LOCK_2_SHIFT 7 22269 22270 /* RX_X4_Status0 :: pcs_live_status_0 :: BLOCK_LOCK_1 [06:06] */ 22271 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_BLOCK_LOCK_1_MASK 0x0040 22272 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_BLOCK_LOCK_1_ALIGN 0 22273 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_BLOCK_LOCK_1_BITS 1 22274 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_BLOCK_LOCK_1_SHIFT 6 22275 22276 /* RX_X4_Status0 :: pcs_live_status_0 :: BLOCK_LOCK_0 [05:05] */ 22277 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_BLOCK_LOCK_0_MASK 0x0020 22278 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_BLOCK_LOCK_0_ALIGN 0 22279 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_BLOCK_LOCK_0_BITS 1 22280 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_BLOCK_LOCK_0_SHIFT 5 22281 22282 /* RX_X4_Status0 :: pcs_live_status_0 :: AM_LOCK_4 [04:04] */ 22283 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_AM_LOCK_4_MASK 0x0010 22284 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_AM_LOCK_4_ALIGN 0 22285 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_AM_LOCK_4_BITS 1 22286 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_AM_LOCK_4_SHIFT 4 22287 22288 /* RX_X4_Status0 :: pcs_live_status_0 :: AM_LOCK_3 [03:03] */ 22289 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_AM_LOCK_3_MASK 0x0008 22290 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_AM_LOCK_3_ALIGN 0 22291 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_AM_LOCK_3_BITS 1 22292 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_AM_LOCK_3_SHIFT 3 22293 22294 /* RX_X4_Status0 :: pcs_live_status_0 :: AM_LOCK_2 [02:02] */ 22295 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_AM_LOCK_2_MASK 0x0004 22296 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_AM_LOCK_2_ALIGN 0 22297 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_AM_LOCK_2_BITS 1 22298 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_AM_LOCK_2_SHIFT 2 22299 22300 /* RX_X4_Status0 :: pcs_live_status_0 :: AM_LOCK_1 [01:01] */ 22301 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_AM_LOCK_1_MASK 0x0002 22302 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_AM_LOCK_1_ALIGN 0 22303 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_AM_LOCK_1_BITS 1 22304 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_AM_LOCK_1_SHIFT 1 22305 22306 /* RX_X4_Status0 :: pcs_live_status_0 :: AM_LOCK_0 [00:00] */ 22307 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_AM_LOCK_0_MASK 0x0001 22308 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_AM_LOCK_0_ALIGN 0 22309 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_AM_LOCK_0_BITS 1 22310 #define RX_X4_STATUS0_PCS_LIVE_STATUS_0_AM_LOCK_0_SHIFT 0 22311 22312 22313 /**************************************************************************** 22314 * RX_X4_Status0 :: bipcount_0 22315 */ 22316 /* RX_X4_Status0 :: bipcount_0 :: BIP_ERROR_COUNT_1 [15:08] */ 22317 #define RX_X4_STATUS0_BIPCOUNT_0_BIP_ERROR_COUNT_1_MASK 0xff00 22318 #define RX_X4_STATUS0_BIPCOUNT_0_BIP_ERROR_COUNT_1_ALIGN 0 22319 #define RX_X4_STATUS0_BIPCOUNT_0_BIP_ERROR_COUNT_1_BITS 8 22320 #define RX_X4_STATUS0_BIPCOUNT_0_BIP_ERROR_COUNT_1_SHIFT 8 22321 22322 /* RX_X4_Status0 :: bipcount_0 :: BIP_ERROR_COUNT_0 [07:00] */ 22323 #define RX_X4_STATUS0_BIPCOUNT_0_BIP_ERROR_COUNT_0_MASK 0x00ff 22324 #define RX_X4_STATUS0_BIPCOUNT_0_BIP_ERROR_COUNT_0_ALIGN 0 22325 #define RX_X4_STATUS0_BIPCOUNT_0_BIP_ERROR_COUNT_0_BITS 8 22326 #define RX_X4_STATUS0_BIPCOUNT_0_BIP_ERROR_COUNT_0_SHIFT 0 22327 22328 22329 /**************************************************************************** 22330 * RX_X4_Status0 :: bipcount_1 22331 */ 22332 /* RX_X4_Status0 :: bipcount_1 :: BIP_ERROR_COUNT_3 [15:08] */ 22333 #define RX_X4_STATUS0_BIPCOUNT_1_BIP_ERROR_COUNT_3_MASK 0xff00 22334 #define RX_X4_STATUS0_BIPCOUNT_1_BIP_ERROR_COUNT_3_ALIGN 0 22335 #define RX_X4_STATUS0_BIPCOUNT_1_BIP_ERROR_COUNT_3_BITS 8 22336 #define RX_X4_STATUS0_BIPCOUNT_1_BIP_ERROR_COUNT_3_SHIFT 8 22337 22338 /* RX_X4_Status0 :: bipcount_1 :: BIP_ERROR_COUNT_2 [07:00] */ 22339 #define RX_X4_STATUS0_BIPCOUNT_1_BIP_ERROR_COUNT_2_MASK 0x00ff 22340 #define RX_X4_STATUS0_BIPCOUNT_1_BIP_ERROR_COUNT_2_ALIGN 0 22341 #define RX_X4_STATUS0_BIPCOUNT_1_BIP_ERROR_COUNT_2_BITS 8 22342 #define RX_X4_STATUS0_BIPCOUNT_1_BIP_ERROR_COUNT_2_SHIFT 0 22343 22344 22345 /**************************************************************************** 22346 * RX_X4_Status0 :: bipcount_2 22347 */ 22348 /* RX_X4_Status0 :: bipcount_2 :: reserved0 [15:08] */ 22349 #define RX_X4_STATUS0_BIPCOUNT_2_RESERVED0_MASK 0xff00 22350 #define RX_X4_STATUS0_BIPCOUNT_2_RESERVED0_ALIGN 0 22351 #define RX_X4_STATUS0_BIPCOUNT_2_RESERVED0_BITS 8 22352 #define RX_X4_STATUS0_BIPCOUNT_2_RESERVED0_SHIFT 8 22353 22354 /* RX_X4_Status0 :: bipcount_2 :: BIP_ERROR_COUNT_4 [07:00] */ 22355 #define RX_X4_STATUS0_BIPCOUNT_2_BIP_ERROR_COUNT_4_MASK 0x00ff 22356 #define RX_X4_STATUS0_BIPCOUNT_2_BIP_ERROR_COUNT_4_ALIGN 0 22357 #define RX_X4_STATUS0_BIPCOUNT_2_BIP_ERROR_COUNT_4_BITS 8 22358 #define RX_X4_STATUS0_BIPCOUNT_2_BIP_ERROR_COUNT_4_SHIFT 0 22359 22360 22361 /**************************************************************************** 22362 * RX_X4_Status0 :: psll_to_vl_mapping_0 22363 */ 22364 /* RX_X4_Status0 :: psll_to_vl_mapping_0 :: reserved0 [15:15] */ 22365 #define RX_X4_STATUS0_PSLL_TO_VL_MAPPING_0_RESERVED0_MASK 0x8000 22366 #define RX_X4_STATUS0_PSLL_TO_VL_MAPPING_0_RESERVED0_ALIGN 0 22367 #define RX_X4_STATUS0_PSLL_TO_VL_MAPPING_0_RESERVED0_BITS 1 22368 #define RX_X4_STATUS0_PSLL_TO_VL_MAPPING_0_RESERVED0_SHIFT 15 22369 22370 /* RX_X4_Status0 :: psll_to_vl_mapping_0 :: psll2_to_vl_mapping [14:10] */ 22371 #define RX_X4_STATUS0_PSLL_TO_VL_MAPPING_0_PSLL2_TO_VL_MAPPING_MASK 0x7c00 22372 #define RX_X4_STATUS0_PSLL_TO_VL_MAPPING_0_PSLL2_TO_VL_MAPPING_ALIGN 0 22373 #define RX_X4_STATUS0_PSLL_TO_VL_MAPPING_0_PSLL2_TO_VL_MAPPING_BITS 5 22374 #define RX_X4_STATUS0_PSLL_TO_VL_MAPPING_0_PSLL2_TO_VL_MAPPING_SHIFT 10 22375 22376 /* RX_X4_Status0 :: psll_to_vl_mapping_0 :: psll1_to_vl_mapping [09:05] */ 22377 #define RX_X4_STATUS0_PSLL_TO_VL_MAPPING_0_PSLL1_TO_VL_MAPPING_MASK 0x03e0 22378 #define RX_X4_STATUS0_PSLL_TO_VL_MAPPING_0_PSLL1_TO_VL_MAPPING_ALIGN 0 22379 #define RX_X4_STATUS0_PSLL_TO_VL_MAPPING_0_PSLL1_TO_VL_MAPPING_BITS 5 22380 #define RX_X4_STATUS0_PSLL_TO_VL_MAPPING_0_PSLL1_TO_VL_MAPPING_SHIFT 5 22381 22382 /* RX_X4_Status0 :: psll_to_vl_mapping_0 :: psll0_to_vl_mapping [04:00] */ 22383 #define RX_X4_STATUS0_PSLL_TO_VL_MAPPING_0_PSLL0_TO_VL_MAPPING_MASK 0x001f 22384 #define RX_X4_STATUS0_PSLL_TO_VL_MAPPING_0_PSLL0_TO_VL_MAPPING_ALIGN 0 22385 #define RX_X4_STATUS0_PSLL_TO_VL_MAPPING_0_PSLL0_TO_VL_MAPPING_BITS 5 22386 #define RX_X4_STATUS0_PSLL_TO_VL_MAPPING_0_PSLL0_TO_VL_MAPPING_SHIFT 0 22387 22388 22389 /**************************************************************************** 22390 * RX_X4_Status0 :: psll_to_vl_mapping_1 22391 */ 22392 /* RX_X4_Status0 :: psll_to_vl_mapping_1 :: reserved0 [15:10] */ 22393 #define RX_X4_STATUS0_PSLL_TO_VL_MAPPING_1_RESERVED0_MASK 0xfc00 22394 #define RX_X4_STATUS0_PSLL_TO_VL_MAPPING_1_RESERVED0_ALIGN 0 22395 #define RX_X4_STATUS0_PSLL_TO_VL_MAPPING_1_RESERVED0_BITS 6 22396 #define RX_X4_STATUS0_PSLL_TO_VL_MAPPING_1_RESERVED0_SHIFT 10 22397 22398 /* RX_X4_Status0 :: psll_to_vl_mapping_1 :: psll4_to_vl_mapping [09:05] */ 22399 #define RX_X4_STATUS0_PSLL_TO_VL_MAPPING_1_PSLL4_TO_VL_MAPPING_MASK 0x03e0 22400 #define RX_X4_STATUS0_PSLL_TO_VL_MAPPING_1_PSLL4_TO_VL_MAPPING_ALIGN 0 22401 #define RX_X4_STATUS0_PSLL_TO_VL_MAPPING_1_PSLL4_TO_VL_MAPPING_BITS 5 22402 #define RX_X4_STATUS0_PSLL_TO_VL_MAPPING_1_PSLL4_TO_VL_MAPPING_SHIFT 5 22403 22404 /* RX_X4_Status0 :: psll_to_vl_mapping_1 :: psll3_to_vl_mapping [04:00] */ 22405 #define RX_X4_STATUS0_PSLL_TO_VL_MAPPING_1_PSLL3_TO_VL_MAPPING_MASK 0x001f 22406 #define RX_X4_STATUS0_PSLL_TO_VL_MAPPING_1_PSLL3_TO_VL_MAPPING_ALIGN 0 22407 #define RX_X4_STATUS0_PSLL_TO_VL_MAPPING_1_PSLL3_TO_VL_MAPPING_BITS 5 22408 #define RX_X4_STATUS0_PSLL_TO_VL_MAPPING_1_PSLL3_TO_VL_MAPPING_SHIFT 0 22409 22410 22411 /**************************************************************************** 22412 * RX_X4_Status0 :: RS_SYMBOL 22413 */ 22414 /* RX_X4_Status0 :: RS_SYMBOL :: reserved0 [15:10] */ 22415 #define RX_X4_STATUS0_RS_SYMBOL_RESERVED0_MASK 0xfc00 22416 #define RX_X4_STATUS0_RS_SYMBOL_RESERVED0_ALIGN 0 22417 #define RX_X4_STATUS0_RS_SYMBOL_RESERVED0_BITS 6 22418 #define RX_X4_STATUS0_RS_SYMBOL_RESERVED0_SHIFT 10 22419 22420 /* RX_X4_Status0 :: RS_SYMBOL :: symbol_value [09:00] */ 22421 #define RX_X4_STATUS0_RS_SYMBOL_SYMBOL_VALUE_MASK 0x03ff 22422 #define RX_X4_STATUS0_RS_SYMBOL_SYMBOL_VALUE_ALIGN 0 22423 #define RX_X4_STATUS0_RS_SYMBOL_SYMBOL_VALUE_BITS 10 22424 #define RX_X4_STATUS0_RS_SYMBOL_SYMBOL_VALUE_SHIFT 0 22425 22426 22427 /**************************************************************************** 22428 * TSC_TSC_USER4_RX_X4_Status1 22429 */ 22430 /**************************************************************************** 22431 * RX_X4_Status1 :: pcs_latched_status_1 22432 */ 22433 /* RX_X4_Status1 :: pcs_latched_status_1 :: reserved0 [15:10] */ 22434 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_RESERVED0_MASK 0xfc00 22435 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_RESERVED0_ALIGN 0 22436 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_RESERVED0_BITS 6 22437 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_RESERVED0_SHIFT 10 22438 22439 /* RX_X4_Status1 :: pcs_latched_status_1 :: LOCAL_FAULT_LH [09:09] */ 22440 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LOCAL_FAULT_LH_MASK 0x0200 22441 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LOCAL_FAULT_LH_ALIGN 0 22442 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LOCAL_FAULT_LH_BITS 1 22443 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LOCAL_FAULT_LH_SHIFT 9 22444 22445 /* RX_X4_Status1 :: pcs_latched_status_1 :: REMOTE_FAULT_LH [08:08] */ 22446 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_REMOTE_FAULT_LH_MASK 0x0100 22447 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_REMOTE_FAULT_LH_ALIGN 0 22448 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_REMOTE_FAULT_LH_BITS 1 22449 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_REMOTE_FAULT_LH_SHIFT 8 22450 22451 /* RX_X4_Status1 :: pcs_latched_status_1 :: LINK_INTERRUPT_LH [07:07] */ 22452 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LINK_INTERRUPT_LH_MASK 0x0080 22453 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LINK_INTERRUPT_LH_ALIGN 0 22454 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LINK_INTERRUPT_LH_BITS 1 22455 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LINK_INTERRUPT_LH_SHIFT 7 22456 22457 /* RX_X4_Status1 :: pcs_latched_status_1 :: LPI_RECEIVED_LH [06:06] */ 22458 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LPI_RECEIVED_LH_MASK 0x0040 22459 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LPI_RECEIVED_LH_ALIGN 0 22460 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LPI_RECEIVED_LH_BITS 1 22461 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LPI_RECEIVED_LH_SHIFT 6 22462 22463 /* RX_X4_Status1 :: pcs_latched_status_1 :: HI_BER_LH [05:05] */ 22464 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_HI_BER_LH_MASK 0x0020 22465 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_HI_BER_LH_ALIGN 0 22466 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_HI_BER_LH_BITS 1 22467 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_HI_BER_LH_SHIFT 5 22468 22469 /* RX_X4_Status1 :: pcs_latched_status_1 :: HI_BER_LL [04:04] */ 22470 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_HI_BER_LL_MASK 0x0010 22471 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_HI_BER_LL_ALIGN 0 22472 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_HI_BER_LL_BITS 1 22473 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_HI_BER_LL_SHIFT 4 22474 22475 /* RX_X4_Status1 :: pcs_latched_status_1 :: LINK_STATUS_LH [03:03] */ 22476 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LINK_STATUS_LH_MASK 0x0008 22477 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LINK_STATUS_LH_ALIGN 0 22478 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LINK_STATUS_LH_BITS 1 22479 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LINK_STATUS_LH_SHIFT 3 22480 22481 /* RX_X4_Status1 :: pcs_latched_status_1 :: LINK_STATUS_LL [02:02] */ 22482 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LINK_STATUS_LL_MASK 0x0004 22483 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LINK_STATUS_LL_ALIGN 0 22484 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LINK_STATUS_LL_BITS 1 22485 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_LINK_STATUS_LL_SHIFT 2 22486 22487 /* RX_X4_Status1 :: pcs_latched_status_1 :: DESKEW_STATUS_LH [01:01] */ 22488 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_DESKEW_STATUS_LH_MASK 0x0002 22489 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_DESKEW_STATUS_LH_ALIGN 0 22490 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_DESKEW_STATUS_LH_BITS 1 22491 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_DESKEW_STATUS_LH_SHIFT 1 22492 22493 /* RX_X4_Status1 :: pcs_latched_status_1 :: DESKEW_STATUS_LL [00:00] */ 22494 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_DESKEW_STATUS_LL_MASK 0x0001 22495 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_DESKEW_STATUS_LL_ALIGN 0 22496 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_DESKEW_STATUS_LL_BITS 1 22497 #define RX_X4_STATUS1_PCS_LATCHED_STATUS_1_DESKEW_STATUS_LL_SHIFT 0 22498 22499 22500 /**************************************************************************** 22501 * RX_X4_Status1 :: pcs_live_status_1 22502 */ 22503 /* RX_X4_Status1 :: pcs_live_status_1 :: reserved0 [15:07] */ 22504 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_RESERVED0_MASK 0xff80 22505 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_RESERVED0_ALIGN 0 22506 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_RESERVED0_BITS 9 22507 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_RESERVED0_SHIFT 7 22508 22509 /* RX_X4_Status1 :: pcs_live_status_1 :: LOCAL_FAULT [06:06] */ 22510 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_LOCAL_FAULT_MASK 0x0040 22511 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_LOCAL_FAULT_ALIGN 0 22512 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_LOCAL_FAULT_BITS 1 22513 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_LOCAL_FAULT_SHIFT 6 22514 22515 /* RX_X4_Status1 :: pcs_live_status_1 :: REMOTE_FAULT [05:05] */ 22516 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_REMOTE_FAULT_MASK 0x0020 22517 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_REMOTE_FAULT_ALIGN 0 22518 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_REMOTE_FAULT_BITS 1 22519 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_REMOTE_FAULT_SHIFT 5 22520 22521 /* RX_X4_Status1 :: pcs_live_status_1 :: LINK_INTERRUPT [04:04] */ 22522 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_LINK_INTERRUPT_MASK 0x0010 22523 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_LINK_INTERRUPT_ALIGN 0 22524 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_LINK_INTERRUPT_BITS 1 22525 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_LINK_INTERRUPT_SHIFT 4 22526 22527 /* RX_X4_Status1 :: pcs_live_status_1 :: LPI_RECEIVED [03:03] */ 22528 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_LPI_RECEIVED_MASK 0x0008 22529 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_LPI_RECEIVED_ALIGN 0 22530 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_LPI_RECEIVED_BITS 1 22531 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_LPI_RECEIVED_SHIFT 3 22532 22533 /* RX_X4_Status1 :: pcs_live_status_1 :: HI_BER [02:02] */ 22534 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_HI_BER_MASK 0x0004 22535 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_HI_BER_ALIGN 0 22536 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_HI_BER_BITS 1 22537 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_HI_BER_SHIFT 2 22538 22539 /* RX_X4_Status1 :: pcs_live_status_1 :: LINK_STATUS [01:01] */ 22540 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_LINK_STATUS_MASK 0x0002 22541 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_LINK_STATUS_ALIGN 0 22542 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_LINK_STATUS_BITS 1 22543 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_LINK_STATUS_SHIFT 1 22544 22545 /* RX_X4_Status1 :: pcs_live_status_1 :: DESKEW_STATUS [00:00] */ 22546 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_DESKEW_STATUS_MASK 0x0001 22547 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_DESKEW_STATUS_ALIGN 0 22548 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_DESKEW_STATUS_BITS 1 22549 #define RX_X4_STATUS1_PCS_LIVE_STATUS_1_DESKEW_STATUS_SHIFT 0 22550 22551 22552 /**************************************************************************** 22553 * RX_X4_Status1 :: decode_status_0 22554 */ 22555 /* RX_X4_Status1 :: decode_status_0 :: reserved0 [15:05] */ 22556 #define RX_X4_STATUS1_DECODE_STATUS_0_RESERVED0_MASK 0xffe0 22557 #define RX_X4_STATUS1_DECODE_STATUS_0_RESERVED0_ALIGN 0 22558 #define RX_X4_STATUS1_DECODE_STATUS_0_RESERVED0_BITS 11 22559 #define RX_X4_STATUS1_DECODE_STATUS_0_RESERVED0_SHIFT 5 22560 22561 /* RX_X4_Status1 :: decode_status_0 :: bermon_current_state [04:00] */ 22562 #define RX_X4_STATUS1_DECODE_STATUS_0_BERMON_CURRENT_STATE_MASK 0x001f 22563 #define RX_X4_STATUS1_DECODE_STATUS_0_BERMON_CURRENT_STATE_ALIGN 0 22564 #define RX_X4_STATUS1_DECODE_STATUS_0_BERMON_CURRENT_STATE_BITS 5 22565 #define RX_X4_STATUS1_DECODE_STATUS_0_BERMON_CURRENT_STATE_SHIFT 0 22566 #define RX_X4_STATUS1_DECODE_STATUS_0_BERMON_CURRENT_STATE_HI_BER 4 22567 #define RX_X4_STATUS1_DECODE_STATUS_0_BERMON_CURRENT_STATE_GOOD_BER 3 22568 #define RX_X4_STATUS1_DECODE_STATUS_0_BERMON_CURRENT_STATE_BER_TEST_SH 2 22569 #define RX_X4_STATUS1_DECODE_STATUS_0_BERMON_CURRENT_STATE_START_TIMER 1 22570 #define RX_X4_STATUS1_DECODE_STATUS_0_BERMON_CURRENT_STATE_BER_MT_INIT 0 22571 22572 22573 /**************************************************************************** 22574 * RX_X4_Status1 :: decode_status_1 22575 */ 22576 /* RX_X4_Status1 :: decode_status_1 :: reserved0 [15:11] */ 22577 #define RX_X4_STATUS1_DECODE_STATUS_1_RESERVED0_MASK 0xf800 22578 #define RX_X4_STATUS1_DECODE_STATUS_1_RESERVED0_ALIGN 0 22579 #define RX_X4_STATUS1_DECODE_STATUS_1_RESERVED0_BITS 5 22580 #define RX_X4_STATUS1_DECODE_STATUS_1_RESERVED0_SHIFT 11 22581 22582 /* RX_X4_Status1 :: decode_status_1 :: cl49_rxsm_history_state [10:05] */ 22583 #define RX_X4_STATUS1_DECODE_STATUS_1_CL49_RXSM_HISTORY_STATE_MASK 0x07e0 22584 #define RX_X4_STATUS1_DECODE_STATUS_1_CL49_RXSM_HISTORY_STATE_ALIGN 0 22585 #define RX_X4_STATUS1_DECODE_STATUS_1_CL49_RXSM_HISTORY_STATE_BITS 6 22586 #define RX_X4_STATUS1_DECODE_STATUS_1_CL49_RXSM_HISTORY_STATE_SHIFT 5 22587 #define RX_X4_STATUS1_DECODE_STATUS_1_CL49_RXSM_HISTORY_STATE_RX_LI 32 22588 #define RX_X4_STATUS1_DECODE_STATUS_1_CL49_RXSM_HISTORY_STATE_RX_E 16 22589 #define RX_X4_STATUS1_DECODE_STATUS_1_CL49_RXSM_HISTORY_STATE_RX_T 8 22590 #define RX_X4_STATUS1_DECODE_STATUS_1_CL49_RXSM_HISTORY_STATE_RX_D 4 22591 #define RX_X4_STATUS1_DECODE_STATUS_1_CL49_RXSM_HISTORY_STATE_RX_C 2 22592 #define RX_X4_STATUS1_DECODE_STATUS_1_CL49_RXSM_HISTORY_STATE_RX_INIT 1 22593 22594 /* RX_X4_Status1 :: decode_status_1 :: bermon_history_state [04:00] */ 22595 #define RX_X4_STATUS1_DECODE_STATUS_1_BERMON_HISTORY_STATE_MASK 0x001f 22596 #define RX_X4_STATUS1_DECODE_STATUS_1_BERMON_HISTORY_STATE_ALIGN 0 22597 #define RX_X4_STATUS1_DECODE_STATUS_1_BERMON_HISTORY_STATE_BITS 5 22598 #define RX_X4_STATUS1_DECODE_STATUS_1_BERMON_HISTORY_STATE_SHIFT 0 22599 #define RX_X4_STATUS1_DECODE_STATUS_1_BERMON_HISTORY_STATE_HI_BER 4 22600 #define RX_X4_STATUS1_DECODE_STATUS_1_BERMON_HISTORY_STATE_GOOD_BER 3 22601 #define RX_X4_STATUS1_DECODE_STATUS_1_BERMON_HISTORY_STATE_BER_TEST_SH 2 22602 #define RX_X4_STATUS1_DECODE_STATUS_1_BERMON_HISTORY_STATE_START_TIMER 1 22603 #define RX_X4_STATUS1_DECODE_STATUS_1_BERMON_HISTORY_STATE_BER_MT_INIT 0 22604 22605 22606 /**************************************************************************** 22607 * RX_X4_Status1 :: decode_status_2 22608 */ 22609 /* RX_X4_Status1 :: decode_status_2 :: reserved0 [15:10] */ 22610 #define RX_X4_STATUS1_DECODE_STATUS_2_RESERVED0_MASK 0xfc00 22611 #define RX_X4_STATUS1_DECODE_STATUS_2_RESERVED0_ALIGN 0 22612 #define RX_X4_STATUS1_DECODE_STATUS_2_RESERVED0_BITS 6 22613 #define RX_X4_STATUS1_DECODE_STATUS_2_RESERVED0_SHIFT 10 22614 22615 /* RX_X4_Status1 :: decode_status_2 :: cl49_r_type_coded [09:06] */ 22616 #define RX_X4_STATUS1_DECODE_STATUS_2_CL49_R_TYPE_CODED_MASK 0x03c0 22617 #define RX_X4_STATUS1_DECODE_STATUS_2_CL49_R_TYPE_CODED_ALIGN 0 22618 #define RX_X4_STATUS1_DECODE_STATUS_2_CL49_R_TYPE_CODED_BITS 4 22619 #define RX_X4_STATUS1_DECODE_STATUS_2_CL49_R_TYPE_CODED_SHIFT 6 22620 22621 /* RX_X4_Status1 :: decode_status_2 :: cl49_rxsm_current_state [05:00] */ 22622 #define RX_X4_STATUS1_DECODE_STATUS_2_CL49_RXSM_CURRENT_STATE_MASK 0x003f 22623 #define RX_X4_STATUS1_DECODE_STATUS_2_CL49_RXSM_CURRENT_STATE_ALIGN 0 22624 #define RX_X4_STATUS1_DECODE_STATUS_2_CL49_RXSM_CURRENT_STATE_BITS 6 22625 #define RX_X4_STATUS1_DECODE_STATUS_2_CL49_RXSM_CURRENT_STATE_SHIFT 0 22626 #define RX_X4_STATUS1_DECODE_STATUS_2_CL49_RXSM_CURRENT_STATE_RX_LI 32 22627 #define RX_X4_STATUS1_DECODE_STATUS_2_CL49_RXSM_CURRENT_STATE_RX_E 16 22628 #define RX_X4_STATUS1_DECODE_STATUS_2_CL49_RXSM_CURRENT_STATE_RX_T 8 22629 #define RX_X4_STATUS1_DECODE_STATUS_2_CL49_RXSM_CURRENT_STATE_RX_D 4 22630 #define RX_X4_STATUS1_DECODE_STATUS_2_CL49_RXSM_CURRENT_STATE_RX_C 2 22631 #define RX_X4_STATUS1_DECODE_STATUS_2_CL49_RXSM_CURRENT_STATE_RX_INIT 1 22632 22633 22634 /**************************************************************************** 22635 * RX_X4_Status1 :: decode_status_3 22636 */ 22637 /* RX_X4_Status1 :: decode_status_3 :: reserved0 [15:14] */ 22638 #define RX_X4_STATUS1_DECODE_STATUS_3_RESERVED0_MASK 0xc000 22639 #define RX_X4_STATUS1_DECODE_STATUS_3_RESERVED0_ALIGN 0 22640 #define RX_X4_STATUS1_DECODE_STATUS_3_RESERVED0_BITS 2 22641 #define RX_X4_STATUS1_DECODE_STATUS_3_RESERVED0_SHIFT 14 22642 22643 /* RX_X4_Status1 :: decode_status_3 :: cl49_ber_count [13:08] */ 22644 #define RX_X4_STATUS1_DECODE_STATUS_3_CL49_BER_COUNT_MASK 0x3f00 22645 #define RX_X4_STATUS1_DECODE_STATUS_3_CL49_BER_COUNT_ALIGN 0 22646 #define RX_X4_STATUS1_DECODE_STATUS_3_CL49_BER_COUNT_BITS 6 22647 #define RX_X4_STATUS1_DECODE_STATUS_3_CL49_BER_COUNT_SHIFT 8 22648 22649 /* RX_X4_Status1 :: decode_status_3 :: ieee_errored_blocks [07:00] */ 22650 #define RX_X4_STATUS1_DECODE_STATUS_3_IEEE_ERRORED_BLOCKS_MASK 0x00ff 22651 #define RX_X4_STATUS1_DECODE_STATUS_3_IEEE_ERRORED_BLOCKS_ALIGN 0 22652 #define RX_X4_STATUS1_DECODE_STATUS_3_IEEE_ERRORED_BLOCKS_BITS 8 22653 #define RX_X4_STATUS1_DECODE_STATUS_3_IEEE_ERRORED_BLOCKS_SHIFT 0 22654 22655 22656 /**************************************************************************** 22657 * RX_X4_Status1 :: rx_live_status 22658 */ 22659 /* RX_X4_Status1 :: rx_live_status :: reserved0 [15:14] */ 22660 #define RX_X4_STATUS1_RX_LIVE_STATUS_RESERVED0_MASK 0xc000 22661 #define RX_X4_STATUS1_RX_LIVE_STATUS_RESERVED0_ALIGN 0 22662 #define RX_X4_STATUS1_RX_LIVE_STATUS_RESERVED0_BITS 2 22663 #define RX_X4_STATUS1_RX_LIVE_STATUS_RESERVED0_SHIFT 14 22664 22665 /* RX_X4_Status1 :: rx_live_status :: deskew_state [13:11] */ 22666 #define RX_X4_STATUS1_RX_LIVE_STATUS_DESKEW_STATE_MASK 0x3800 22667 #define RX_X4_STATUS1_RX_LIVE_STATUS_DESKEW_STATE_ALIGN 0 22668 #define RX_X4_STATUS1_RX_LIVE_STATUS_DESKEW_STATE_BITS 3 22669 #define RX_X4_STATUS1_RX_LIVE_STATUS_DESKEW_STATE_SHIFT 11 22670 22671 /* RX_X4_Status1 :: rx_live_status :: r_type_coded [10:05] */ 22672 #define RX_X4_STATUS1_RX_LIVE_STATUS_R_TYPE_CODED_MASK 0x07e0 22673 #define RX_X4_STATUS1_RX_LIVE_STATUS_R_TYPE_CODED_ALIGN 0 22674 #define RX_X4_STATUS1_RX_LIVE_STATUS_R_TYPE_CODED_BITS 6 22675 #define RX_X4_STATUS1_RX_LIVE_STATUS_R_TYPE_CODED_SHIFT 5 22676 #define RX_X4_STATUS1_RX_LIVE_STATUS_R_TYPE_CODED_R_TYPE_B1 32 22677 #define RX_X4_STATUS1_RX_LIVE_STATUS_R_TYPE_CODED_R_TYPE_C 16 22678 #define RX_X4_STATUS1_RX_LIVE_STATUS_R_TYPE_CODED_R_TYPE_S 8 22679 #define RX_X4_STATUS1_RX_LIVE_STATUS_R_TYPE_CODED_R_TYPE_T 4 22680 #define RX_X4_STATUS1_RX_LIVE_STATUS_R_TYPE_CODED_R_TYPE_D 2 22681 #define RX_X4_STATUS1_RX_LIVE_STATUS_R_TYPE_CODED_R_TYPE_E 1 22682 22683 /* RX_X4_Status1 :: rx_live_status :: current_rxsm_state [04:00] */ 22684 #define RX_X4_STATUS1_RX_LIVE_STATUS_CURRENT_RXSM_STATE_MASK 0x001f 22685 #define RX_X4_STATUS1_RX_LIVE_STATUS_CURRENT_RXSM_STATE_ALIGN 0 22686 #define RX_X4_STATUS1_RX_LIVE_STATUS_CURRENT_RXSM_STATE_BITS 5 22687 #define RX_X4_STATUS1_RX_LIVE_STATUS_CURRENT_RXSM_STATE_SHIFT 0 22688 #define RX_X4_STATUS1_RX_LIVE_STATUS_CURRENT_RXSM_STATE_RX_E 16 22689 #define RX_X4_STATUS1_RX_LIVE_STATUS_CURRENT_RXSM_STATE_RX_T 8 22690 #define RX_X4_STATUS1_RX_LIVE_STATUS_CURRENT_RXSM_STATE_RX_D 4 22691 #define RX_X4_STATUS1_RX_LIVE_STATUS_CURRENT_RXSM_STATE_RX_C 2 22692 #define RX_X4_STATUS1_RX_LIVE_STATUS_CURRENT_RXSM_STATE_RX_INIT 1 22693 22694 22695 /**************************************************************************** 22696 * RX_X4_Status1 :: rx_latched_status 22697 */ 22698 /* RX_X4_Status1 :: rx_latched_status :: reserved0 [15:11] */ 22699 #define RX_X4_STATUS1_RX_LATCHED_STATUS_RESERVED0_MASK 0xf800 22700 #define RX_X4_STATUS1_RX_LATCHED_STATUS_RESERVED0_ALIGN 0 22701 #define RX_X4_STATUS1_RX_LATCHED_STATUS_RESERVED0_BITS 5 22702 #define RX_X4_STATUS1_RX_LATCHED_STATUS_RESERVED0_SHIFT 11 22703 22704 /* RX_X4_Status1 :: rx_latched_status :: history_rxsm_state [10:06] */ 22705 #define RX_X4_STATUS1_RX_LATCHED_STATUS_HISTORY_RXSM_STATE_MASK 0x07c0 22706 #define RX_X4_STATUS1_RX_LATCHED_STATUS_HISTORY_RXSM_STATE_ALIGN 0 22707 #define RX_X4_STATUS1_RX_LATCHED_STATUS_HISTORY_RXSM_STATE_BITS 5 22708 #define RX_X4_STATUS1_RX_LATCHED_STATUS_HISTORY_RXSM_STATE_SHIFT 6 22709 #define RX_X4_STATUS1_RX_LATCHED_STATUS_HISTORY_RXSM_STATE_RX_E 16 22710 #define RX_X4_STATUS1_RX_LATCHED_STATUS_HISTORY_RXSM_STATE_RX_T 8 22711 #define RX_X4_STATUS1_RX_LATCHED_STATUS_HISTORY_RXSM_STATE_RX_D 4 22712 #define RX_X4_STATUS1_RX_LATCHED_STATUS_HISTORY_RXSM_STATE_RX_C 2 22713 #define RX_X4_STATUS1_RX_LATCHED_STATUS_HISTORY_RXSM_STATE_RX_INIT 1 22714 22715 /* RX_X4_Status1 :: rx_latched_status :: deskew_his_state [05:00] */ 22716 #define RX_X4_STATUS1_RX_LATCHED_STATUS_DESKEW_HIS_STATE_MASK 0x003f 22717 #define RX_X4_STATUS1_RX_LATCHED_STATUS_DESKEW_HIS_STATE_ALIGN 0 22718 #define RX_X4_STATUS1_RX_LATCHED_STATUS_DESKEW_HIS_STATE_BITS 6 22719 #define RX_X4_STATUS1_RX_LATCHED_STATUS_DESKEW_HIS_STATE_SHIFT 0 22720 22721 22722 /**************************************************************************** 22723 * RX_X4_Status1 :: ber_lo 22724 */ 22725 /* RX_X4_Status1 :: ber_lo :: reserved0 [15:08] */ 22726 #define RX_X4_STATUS1_BER_LO_RESERVED0_MASK 0xff00 22727 #define RX_X4_STATUS1_BER_LO_RESERVED0_ALIGN 0 22728 #define RX_X4_STATUS1_BER_LO_RESERVED0_BITS 8 22729 #define RX_X4_STATUS1_BER_LO_RESERVED0_SHIFT 8 22730 22731 /* RX_X4_Status1 :: ber_lo :: ber_lo [07:00] */ 22732 #define RX_X4_STATUS1_BER_LO_BER_LO_MASK 0x00ff 22733 #define RX_X4_STATUS1_BER_LO_BER_LO_ALIGN 0 22734 #define RX_X4_STATUS1_BER_LO_BER_LO_BITS 8 22735 #define RX_X4_STATUS1_BER_LO_BER_LO_SHIFT 0 22736 22737 22738 /**************************************************************************** 22739 * RX_X4_Status1 :: ber_ho 22740 */ 22741 /* RX_X4_Status1 :: ber_ho :: reserved0 [15:14] */ 22742 #define RX_X4_STATUS1_BER_HO_RESERVED0_MASK 0xc000 22743 #define RX_X4_STATUS1_BER_HO_RESERVED0_ALIGN 0 22744 #define RX_X4_STATUS1_BER_HO_RESERVED0_BITS 2 22745 #define RX_X4_STATUS1_BER_HO_RESERVED0_SHIFT 14 22746 22747 /* RX_X4_Status1 :: ber_ho :: ber_ho [13:00] */ 22748 #define RX_X4_STATUS1_BER_HO_BER_HO_MASK 0x3fff 22749 #define RX_X4_STATUS1_BER_HO_BER_HO_ALIGN 0 22750 #define RX_X4_STATUS1_BER_HO_BER_HO_BITS 14 22751 #define RX_X4_STATUS1_BER_HO_BER_HO_SHIFT 0 22752 22753 22754 /**************************************************************************** 22755 * RX_X4_Status1 :: errored_blocks_ho 22756 */ 22757 /* RX_X4_Status1 :: errored_blocks_ho :: errored_blocks_ho_present [15:15] */ 22758 #define RX_X4_STATUS1_ERRORED_BLOCKS_HO_ERRORED_BLOCKS_HO_PRESENT_MASK 0x8000 22759 #define RX_X4_STATUS1_ERRORED_BLOCKS_HO_ERRORED_BLOCKS_HO_PRESENT_ALIGN 0 22760 #define RX_X4_STATUS1_ERRORED_BLOCKS_HO_ERRORED_BLOCKS_HO_PRESENT_BITS 1 22761 #define RX_X4_STATUS1_ERRORED_BLOCKS_HO_ERRORED_BLOCKS_HO_PRESENT_SHIFT 15 22762 22763 /* RX_X4_Status1 :: errored_blocks_ho :: reserved0 [14:14] */ 22764 #define RX_X4_STATUS1_ERRORED_BLOCKS_HO_RESERVED0_MASK 0x4000 22765 #define RX_X4_STATUS1_ERRORED_BLOCKS_HO_RESERVED0_ALIGN 0 22766 #define RX_X4_STATUS1_ERRORED_BLOCKS_HO_RESERVED0_BITS 1 22767 #define RX_X4_STATUS1_ERRORED_BLOCKS_HO_RESERVED0_SHIFT 14 22768 22769 /* RX_X4_Status1 :: errored_blocks_ho :: errored_blocks_ho [13:00] */ 22770 #define RX_X4_STATUS1_ERRORED_BLOCKS_HO_ERRORED_BLOCKS_HO_MASK 0x3fff 22771 #define RX_X4_STATUS1_ERRORED_BLOCKS_HO_ERRORED_BLOCKS_HO_ALIGN 0 22772 #define RX_X4_STATUS1_ERRORED_BLOCKS_HO_ERRORED_BLOCKS_HO_BITS 14 22773 #define RX_X4_STATUS1_ERRORED_BLOCKS_HO_ERRORED_BLOCKS_HO_SHIFT 0 22774 22775 22776 /**************************************************************************** 22777 * RX_X4_Status1 :: cl49_scridle_test_err 22778 */ 22779 /* RX_X4_Status1 :: cl49_scridle_test_err :: cl49_scridle_test_err [15:00] */ 22780 #define RX_X4_STATUS1_CL49_SCRIDLE_TEST_ERR_CL49_SCRIDLE_TEST_ERR_MASK 0xffff 22781 #define RX_X4_STATUS1_CL49_SCRIDLE_TEST_ERR_CL49_SCRIDLE_TEST_ERR_ALIGN 0 22782 #define RX_X4_STATUS1_CL49_SCRIDLE_TEST_ERR_CL49_SCRIDLE_TEST_ERR_BITS 16 22783 #define RX_X4_STATUS1_CL49_SCRIDLE_TEST_ERR_CL49_SCRIDLE_TEST_ERR_SHIFT 0 22784 22785 22786 /**************************************************************************** 22787 * TSC_TSC_USER4_RX_X4_Status2 22788 */ 22789 /**************************************************************************** 22790 * RX_X4_Status2 :: cl82_rx_am_latched_status_psll_0 22791 */ 22792 /* RX_X4_Status2 :: cl82_rx_am_latched_status_psll_0 :: reserved0 [15:12] */ 22793 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_0_RESERVED0_MASK 0xf000 22794 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_0_RESERVED0_ALIGN 0 22795 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_0_RESERVED0_BITS 4 22796 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_0_RESERVED0_SHIFT 12 22797 22798 /* RX_X4_Status2 :: cl82_rx_am_latched_status_psll_0 :: common_mrkr_spacing_err_latch_fecl_0 [11:11] */ 22799 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_0_COMMON_MRKR_SPACING_ERR_LATCH_FECL_0_MASK 0x0800 22800 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_0_COMMON_MRKR_SPACING_ERR_LATCH_FECL_0_ALIGN 0 22801 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_0_COMMON_MRKR_SPACING_ERR_LATCH_FECL_0_BITS 1 22802 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_0_COMMON_MRKR_SPACING_ERR_LATCH_FECL_0_SHIFT 11 22803 22804 /* RX_X4_Status2 :: cl82_rx_am_latched_status_psll_0 :: amrkr_spacing_err_latch_mux_psll_0 [10:10] */ 22805 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_0_AMRKR_SPACING_ERR_LATCH_MUX_PSLL_0_MASK 0x0400 22806 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_0_AMRKR_SPACING_ERR_LATCH_MUX_PSLL_0_ALIGN 0 22807 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_0_AMRKR_SPACING_ERR_LATCH_MUX_PSLL_0_BITS 1 22808 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_0_AMRKR_SPACING_ERR_LATCH_MUX_PSLL_0_SHIFT 10 22809 22810 /* RX_X4_Status2 :: cl82_rx_am_latched_status_psll_0 :: am_lock_his_state_psll_0 [09:00] */ 22811 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_0_AM_LOCK_HIS_STATE_PSLL_0_MASK 0x03ff 22812 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_0_AM_LOCK_HIS_STATE_PSLL_0_ALIGN 0 22813 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_0_AM_LOCK_HIS_STATE_PSLL_0_BITS 10 22814 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_0_AM_LOCK_HIS_STATE_PSLL_0_SHIFT 0 22815 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_0_AM_LOCK_HIS_STATE_PSLL_0_INVALID_AM 512 22816 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_0_AM_LOCK_HIS_STATE_PSLL_0_GOOD_AM 256 22817 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_0_AM_LOCK_HIS_STATE_PSLL_0_COMP_AM 128 22818 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_0_AM_LOCK_HIS_STATE_PSLL_0_TIMER_2 64 22819 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_0_AM_LOCK_HIS_STATE_PSLL_0_AM_2_GOOD 32 22820 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_0_AM_LOCK_HIS_STATE_PSLL_0_COMP_2ND 16 22821 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_0_AM_LOCK_HIS_STATE_PSLL_0_TIMER_1 8 22822 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_0_AM_LOCK_HIS_STATE_PSLL_0_FIND_1ST 4 22823 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_0_AM_LOCK_HIS_STATE_PSLL_0_AM_RESET_CNT 2 22824 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_0_AM_LOCK_HIS_STATE_PSLL_0_AM_LOCK_INIT 1 22825 22826 22827 /**************************************************************************** 22828 * RX_X4_Status2 :: cl82_rx_am_latched_status_psll_1 22829 */ 22830 /* RX_X4_Status2 :: cl82_rx_am_latched_status_psll_1 :: reserved0 [15:12] */ 22831 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_1_RESERVED0_MASK 0xf000 22832 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_1_RESERVED0_ALIGN 0 22833 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_1_RESERVED0_BITS 4 22834 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_1_RESERVED0_SHIFT 12 22835 22836 /* RX_X4_Status2 :: cl82_rx_am_latched_status_psll_1 :: common_mrkr_spacing_err_latch_fecl_1 [11:11] */ 22837 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_1_COMMON_MRKR_SPACING_ERR_LATCH_FECL_1_MASK 0x0800 22838 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_1_COMMON_MRKR_SPACING_ERR_LATCH_FECL_1_ALIGN 0 22839 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_1_COMMON_MRKR_SPACING_ERR_LATCH_FECL_1_BITS 1 22840 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_1_COMMON_MRKR_SPACING_ERR_LATCH_FECL_1_SHIFT 11 22841 22842 /* RX_X4_Status2 :: cl82_rx_am_latched_status_psll_1 :: amrkr_spacing_err_latch_mux_psll_1 [10:10] */ 22843 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_1_AMRKR_SPACING_ERR_LATCH_MUX_PSLL_1_MASK 0x0400 22844 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_1_AMRKR_SPACING_ERR_LATCH_MUX_PSLL_1_ALIGN 0 22845 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_1_AMRKR_SPACING_ERR_LATCH_MUX_PSLL_1_BITS 1 22846 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_1_AMRKR_SPACING_ERR_LATCH_MUX_PSLL_1_SHIFT 10 22847 22848 /* RX_X4_Status2 :: cl82_rx_am_latched_status_psll_1 :: am_lock_his_state_psll_1 [09:00] */ 22849 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_1_AM_LOCK_HIS_STATE_PSLL_1_MASK 0x03ff 22850 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_1_AM_LOCK_HIS_STATE_PSLL_1_ALIGN 0 22851 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_1_AM_LOCK_HIS_STATE_PSLL_1_BITS 10 22852 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_1_AM_LOCK_HIS_STATE_PSLL_1_SHIFT 0 22853 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_1_AM_LOCK_HIS_STATE_PSLL_1_INVALID_AM 512 22854 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_1_AM_LOCK_HIS_STATE_PSLL_1_GOOD_AM 256 22855 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_1_AM_LOCK_HIS_STATE_PSLL_1_COMP_AM 128 22856 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_1_AM_LOCK_HIS_STATE_PSLL_1_TIMER_2 64 22857 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_1_AM_LOCK_HIS_STATE_PSLL_1_AM_2_GOOD 32 22858 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_1_AM_LOCK_HIS_STATE_PSLL_1_COMP_2ND 16 22859 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_1_AM_LOCK_HIS_STATE_PSLL_1_TIMER_1 8 22860 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_1_AM_LOCK_HIS_STATE_PSLL_1_FIND_1ST 4 22861 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_1_AM_LOCK_HIS_STATE_PSLL_1_AM_RESET_CNT 2 22862 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_1_AM_LOCK_HIS_STATE_PSLL_1_AM_LOCK_INIT 1 22863 22864 22865 /**************************************************************************** 22866 * RX_X4_Status2 :: cl82_rx_am_latched_status_psll_2 22867 */ 22868 /* RX_X4_Status2 :: cl82_rx_am_latched_status_psll_2 :: reserved0 [15:11] */ 22869 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_2_RESERVED0_MASK 0xf800 22870 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_2_RESERVED0_ALIGN 0 22871 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_2_RESERVED0_BITS 5 22872 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_2_RESERVED0_SHIFT 11 22873 22874 /* RX_X4_Status2 :: cl82_rx_am_latched_status_psll_2 :: amrkr_spacing_err_latch_mux_psll_2 [10:10] */ 22875 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_2_AMRKR_SPACING_ERR_LATCH_MUX_PSLL_2_MASK 0x0400 22876 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_2_AMRKR_SPACING_ERR_LATCH_MUX_PSLL_2_ALIGN 0 22877 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_2_AMRKR_SPACING_ERR_LATCH_MUX_PSLL_2_BITS 1 22878 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_2_AMRKR_SPACING_ERR_LATCH_MUX_PSLL_2_SHIFT 10 22879 22880 /* RX_X4_Status2 :: cl82_rx_am_latched_status_psll_2 :: am_lock_his_state_psll_2 [09:00] */ 22881 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_2_AM_LOCK_HIS_STATE_PSLL_2_MASK 0x03ff 22882 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_2_AM_LOCK_HIS_STATE_PSLL_2_ALIGN 0 22883 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_2_AM_LOCK_HIS_STATE_PSLL_2_BITS 10 22884 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_2_AM_LOCK_HIS_STATE_PSLL_2_SHIFT 0 22885 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_2_AM_LOCK_HIS_STATE_PSLL_2_INVALID_AM 512 22886 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_2_AM_LOCK_HIS_STATE_PSLL_2_GOOD_AM 256 22887 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_2_AM_LOCK_HIS_STATE_PSLL_2_COMP_AM 128 22888 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_2_AM_LOCK_HIS_STATE_PSLL_2_TIMER_2 64 22889 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_2_AM_LOCK_HIS_STATE_PSLL_2_AM_2_GOOD 32 22890 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_2_AM_LOCK_HIS_STATE_PSLL_2_COMP_2ND 16 22891 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_2_AM_LOCK_HIS_STATE_PSLL_2_TIMER_1 8 22892 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_2_AM_LOCK_HIS_STATE_PSLL_2_FIND_1ST 4 22893 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_2_AM_LOCK_HIS_STATE_PSLL_2_AM_RESET_CNT 2 22894 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_2_AM_LOCK_HIS_STATE_PSLL_2_AM_LOCK_INIT 1 22895 22896 22897 /**************************************************************************** 22898 * RX_X4_Status2 :: cl82_rx_am_latched_status_psll_3 22899 */ 22900 /* RX_X4_Status2 :: cl82_rx_am_latched_status_psll_3 :: reserved0 [15:11] */ 22901 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_3_RESERVED0_MASK 0xf800 22902 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_3_RESERVED0_ALIGN 0 22903 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_3_RESERVED0_BITS 5 22904 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_3_RESERVED0_SHIFT 11 22905 22906 /* RX_X4_Status2 :: cl82_rx_am_latched_status_psll_3 :: amrkr_spacing_err_latch_mux_psll_3 [10:10] */ 22907 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_3_AMRKR_SPACING_ERR_LATCH_MUX_PSLL_3_MASK 0x0400 22908 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_3_AMRKR_SPACING_ERR_LATCH_MUX_PSLL_3_ALIGN 0 22909 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_3_AMRKR_SPACING_ERR_LATCH_MUX_PSLL_3_BITS 1 22910 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_3_AMRKR_SPACING_ERR_LATCH_MUX_PSLL_3_SHIFT 10 22911 22912 /* RX_X4_Status2 :: cl82_rx_am_latched_status_psll_3 :: am_lock_his_state_psll_3 [09:00] */ 22913 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_3_AM_LOCK_HIS_STATE_PSLL_3_MASK 0x03ff 22914 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_3_AM_LOCK_HIS_STATE_PSLL_3_ALIGN 0 22915 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_3_AM_LOCK_HIS_STATE_PSLL_3_BITS 10 22916 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_3_AM_LOCK_HIS_STATE_PSLL_3_SHIFT 0 22917 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_3_AM_LOCK_HIS_STATE_PSLL_3_INVALID_AM 512 22918 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_3_AM_LOCK_HIS_STATE_PSLL_3_GOOD_AM 256 22919 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_3_AM_LOCK_HIS_STATE_PSLL_3_COMP_AM 128 22920 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_3_AM_LOCK_HIS_STATE_PSLL_3_TIMER_2 64 22921 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_3_AM_LOCK_HIS_STATE_PSLL_3_AM_2_GOOD 32 22922 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_3_AM_LOCK_HIS_STATE_PSLL_3_COMP_2ND 16 22923 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_3_AM_LOCK_HIS_STATE_PSLL_3_TIMER_1 8 22924 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_3_AM_LOCK_HIS_STATE_PSLL_3_FIND_1ST 4 22925 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_3_AM_LOCK_HIS_STATE_PSLL_3_AM_RESET_CNT 2 22926 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_3_AM_LOCK_HIS_STATE_PSLL_3_AM_LOCK_INIT 1 22927 22928 22929 /**************************************************************************** 22930 * RX_X4_Status2 :: cl82_rx_am_latched_status_psll_4 22931 */ 22932 /* RX_X4_Status2 :: cl82_rx_am_latched_status_psll_4 :: reserved0 [15:11] */ 22933 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_4_RESERVED0_MASK 0xf800 22934 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_4_RESERVED0_ALIGN 0 22935 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_4_RESERVED0_BITS 5 22936 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_4_RESERVED0_SHIFT 11 22937 22938 /* RX_X4_Status2 :: cl82_rx_am_latched_status_psll_4 :: amrkr_spacing_err_latch_mux_psll_4 [10:10] */ 22939 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_4_AMRKR_SPACING_ERR_LATCH_MUX_PSLL_4_MASK 0x0400 22940 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_4_AMRKR_SPACING_ERR_LATCH_MUX_PSLL_4_ALIGN 0 22941 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_4_AMRKR_SPACING_ERR_LATCH_MUX_PSLL_4_BITS 1 22942 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_4_AMRKR_SPACING_ERR_LATCH_MUX_PSLL_4_SHIFT 10 22943 22944 /* RX_X4_Status2 :: cl82_rx_am_latched_status_psll_4 :: am_lock_his_state_psll_4 [09:00] */ 22945 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_4_AM_LOCK_HIS_STATE_PSLL_4_MASK 0x03ff 22946 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_4_AM_LOCK_HIS_STATE_PSLL_4_ALIGN 0 22947 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_4_AM_LOCK_HIS_STATE_PSLL_4_BITS 10 22948 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_4_AM_LOCK_HIS_STATE_PSLL_4_SHIFT 0 22949 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_4_AM_LOCK_HIS_STATE_PSLL_4_INVALID_AM 512 22950 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_4_AM_LOCK_HIS_STATE_PSLL_4_GOOD_AM 256 22951 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_4_AM_LOCK_HIS_STATE_PSLL_4_COMP_AM 128 22952 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_4_AM_LOCK_HIS_STATE_PSLL_4_TIMER_2 64 22953 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_4_AM_LOCK_HIS_STATE_PSLL_4_AM_2_GOOD 32 22954 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_4_AM_LOCK_HIS_STATE_PSLL_4_COMP_2ND 16 22955 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_4_AM_LOCK_HIS_STATE_PSLL_4_TIMER_1 8 22956 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_4_AM_LOCK_HIS_STATE_PSLL_4_FIND_1ST 4 22957 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_4_AM_LOCK_HIS_STATE_PSLL_4_AM_RESET_CNT 2 22958 #define RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_4_AM_LOCK_HIS_STATE_PSLL_4_AM_LOCK_INIT 1 22959 22960 22961 /**************************************************************************** 22962 * RX_X4_Status2 :: cl82_rx_am_live_status_psll_0 22963 */ 22964 /* RX_X4_Status2 :: cl82_rx_am_live_status_psll_0 :: reserved0 [15:10] */ 22965 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_0_RESERVED0_MASK 0xfc00 22966 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_0_RESERVED0_ALIGN 0 22967 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_0_RESERVED0_BITS 6 22968 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_0_RESERVED0_SHIFT 10 22969 22970 /* RX_X4_Status2 :: cl82_rx_am_live_status_psll_0 :: am_lock_state_psll_0 [09:00] */ 22971 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_0_AM_LOCK_STATE_PSLL_0_MASK 0x03ff 22972 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_0_AM_LOCK_STATE_PSLL_0_ALIGN 0 22973 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_0_AM_LOCK_STATE_PSLL_0_BITS 10 22974 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_0_AM_LOCK_STATE_PSLL_0_SHIFT 0 22975 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_0_AM_LOCK_STATE_PSLL_0_INVALID_AM 512 22976 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_0_AM_LOCK_STATE_PSLL_0_GOOD_AM 256 22977 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_0_AM_LOCK_STATE_PSLL_0_COMP_AM 128 22978 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_0_AM_LOCK_STATE_PSLL_0_TIMER_2 64 22979 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_0_AM_LOCK_STATE_PSLL_0_AM_2_GOOD 32 22980 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_0_AM_LOCK_STATE_PSLL_0_COMP_2ND 16 22981 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_0_AM_LOCK_STATE_PSLL_0_TIMER_1 8 22982 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_0_AM_LOCK_STATE_PSLL_0_FIND_1ST 4 22983 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_0_AM_LOCK_STATE_PSLL_0_AM_RESET_CNT 2 22984 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_0_AM_LOCK_STATE_PSLL_0_AM_LOCK_INIT 1 22985 22986 22987 /**************************************************************************** 22988 * RX_X4_Status2 :: cl82_rx_am_live_status_psll_1 22989 */ 22990 /* RX_X4_Status2 :: cl82_rx_am_live_status_psll_1 :: reserved0 [15:10] */ 22991 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_1_RESERVED0_MASK 0xfc00 22992 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_1_RESERVED0_ALIGN 0 22993 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_1_RESERVED0_BITS 6 22994 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_1_RESERVED0_SHIFT 10 22995 22996 /* RX_X4_Status2 :: cl82_rx_am_live_status_psll_1 :: am_lock_state_psll_1 [09:00] */ 22997 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_1_AM_LOCK_STATE_PSLL_1_MASK 0x03ff 22998 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_1_AM_LOCK_STATE_PSLL_1_ALIGN 0 22999 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_1_AM_LOCK_STATE_PSLL_1_BITS 10 23000 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_1_AM_LOCK_STATE_PSLL_1_SHIFT 0 23001 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_1_AM_LOCK_STATE_PSLL_1_INVALID_AM 512 23002 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_1_AM_LOCK_STATE_PSLL_1_GOOD_AM 256 23003 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_1_AM_LOCK_STATE_PSLL_1_COMP_AM 128 23004 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_1_AM_LOCK_STATE_PSLL_1_TIMER_2 64 23005 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_1_AM_LOCK_STATE_PSLL_1_AM_2_GOOD 32 23006 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_1_AM_LOCK_STATE_PSLL_1_COMP_2ND 16 23007 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_1_AM_LOCK_STATE_PSLL_1_TIMER_1 8 23008 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_1_AM_LOCK_STATE_PSLL_1_FIND_1ST 4 23009 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_1_AM_LOCK_STATE_PSLL_1_AM_RESET_CNT 2 23010 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_1_AM_LOCK_STATE_PSLL_1_AM_LOCK_INIT 1 23011 23012 23013 /**************************************************************************** 23014 * RX_X4_Status2 :: cl82_rx_am_live_status_psll_2 23015 */ 23016 /* RX_X4_Status2 :: cl82_rx_am_live_status_psll_2 :: reserved0 [15:10] */ 23017 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_2_RESERVED0_MASK 0xfc00 23018 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_2_RESERVED0_ALIGN 0 23019 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_2_RESERVED0_BITS 6 23020 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_2_RESERVED0_SHIFT 10 23021 23022 /* RX_X4_Status2 :: cl82_rx_am_live_status_psll_2 :: am_lock_state_psll_2 [09:00] */ 23023 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_2_AM_LOCK_STATE_PSLL_2_MASK 0x03ff 23024 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_2_AM_LOCK_STATE_PSLL_2_ALIGN 0 23025 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_2_AM_LOCK_STATE_PSLL_2_BITS 10 23026 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_2_AM_LOCK_STATE_PSLL_2_SHIFT 0 23027 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_2_AM_LOCK_STATE_PSLL_2_INVALID_AM 512 23028 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_2_AM_LOCK_STATE_PSLL_2_GOOD_AM 256 23029 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_2_AM_LOCK_STATE_PSLL_2_COMP_AM 128 23030 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_2_AM_LOCK_STATE_PSLL_2_TIMER_2 64 23031 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_2_AM_LOCK_STATE_PSLL_2_AM_2_GOOD 32 23032 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_2_AM_LOCK_STATE_PSLL_2_COMP_2ND 16 23033 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_2_AM_LOCK_STATE_PSLL_2_TIMER_1 8 23034 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_2_AM_LOCK_STATE_PSLL_2_FIND_1ST 4 23035 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_2_AM_LOCK_STATE_PSLL_2_AM_RESET_CNT 2 23036 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_2_AM_LOCK_STATE_PSLL_2_AM_LOCK_INIT 1 23037 23038 23039 /**************************************************************************** 23040 * RX_X4_Status2 :: cl82_rx_am_live_status_psll_3 23041 */ 23042 /* RX_X4_Status2 :: cl82_rx_am_live_status_psll_3 :: reserved0 [15:10] */ 23043 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_3_RESERVED0_MASK 0xfc00 23044 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_3_RESERVED0_ALIGN 0 23045 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_3_RESERVED0_BITS 6 23046 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_3_RESERVED0_SHIFT 10 23047 23048 /* RX_X4_Status2 :: cl82_rx_am_live_status_psll_3 :: am_lock_state_psll_3 [09:00] */ 23049 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_3_AM_LOCK_STATE_PSLL_3_MASK 0x03ff 23050 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_3_AM_LOCK_STATE_PSLL_3_ALIGN 0 23051 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_3_AM_LOCK_STATE_PSLL_3_BITS 10 23052 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_3_AM_LOCK_STATE_PSLL_3_SHIFT 0 23053 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_3_AM_LOCK_STATE_PSLL_3_INVALID_AM 512 23054 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_3_AM_LOCK_STATE_PSLL_3_GOOD_AM 256 23055 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_3_AM_LOCK_STATE_PSLL_3_COMP_AM 128 23056 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_3_AM_LOCK_STATE_PSLL_3_TIMER_2 64 23057 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_3_AM_LOCK_STATE_PSLL_3_AM_2_GOOD 32 23058 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_3_AM_LOCK_STATE_PSLL_3_COMP_2ND 16 23059 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_3_AM_LOCK_STATE_PSLL_3_TIMER_1 8 23060 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_3_AM_LOCK_STATE_PSLL_3_FIND_1ST 4 23061 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_3_AM_LOCK_STATE_PSLL_3_AM_RESET_CNT 2 23062 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_3_AM_LOCK_STATE_PSLL_3_AM_LOCK_INIT 1 23063 23064 23065 /**************************************************************************** 23066 * RX_X4_Status2 :: cl82_rx_am_live_status_psll_4 23067 */ 23068 /* RX_X4_Status2 :: cl82_rx_am_live_status_psll_4 :: reserved0 [15:10] */ 23069 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_4_RESERVED0_MASK 0xfc00 23070 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_4_RESERVED0_ALIGN 0 23071 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_4_RESERVED0_BITS 6 23072 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_4_RESERVED0_SHIFT 10 23073 23074 /* RX_X4_Status2 :: cl82_rx_am_live_status_psll_4 :: am_lock_state_psll_4 [09:00] */ 23075 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_4_AM_LOCK_STATE_PSLL_4_MASK 0x03ff 23076 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_4_AM_LOCK_STATE_PSLL_4_ALIGN 0 23077 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_4_AM_LOCK_STATE_PSLL_4_BITS 10 23078 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_4_AM_LOCK_STATE_PSLL_4_SHIFT 0 23079 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_4_AM_LOCK_STATE_PSLL_4_INVALID_AM 512 23080 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_4_AM_LOCK_STATE_PSLL_4_GOOD_AM 256 23081 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_4_AM_LOCK_STATE_PSLL_4_COMP_AM 128 23082 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_4_AM_LOCK_STATE_PSLL_4_TIMER_2 64 23083 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_4_AM_LOCK_STATE_PSLL_4_AM_2_GOOD 32 23084 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_4_AM_LOCK_STATE_PSLL_4_COMP_2ND 16 23085 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_4_AM_LOCK_STATE_PSLL_4_TIMER_1 8 23086 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_4_AM_LOCK_STATE_PSLL_4_FIND_1ST 4 23087 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_4_AM_LOCK_STATE_PSLL_4_AM_RESET_CNT 2 23088 #define RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_4_AM_LOCK_STATE_PSLL_4_AM_LOCK_INIT 1 23089 23090 23091 /**************************************************************************** 23092 * RX_X4_Status2 :: RS_FEC_sync_status 23093 */ 23094 /* RX_X4_Status2 :: RS_FEC_sync_status :: RS_FEC_fec_lane_map_valid_1 [15:15] */ 23095 #define RX_X4_STATUS2_RS_FEC_SYNC_STATUS_RS_FEC_FEC_LANE_MAP_VALID_1_MASK 0x8000 23096 #define RX_X4_STATUS2_RS_FEC_SYNC_STATUS_RS_FEC_FEC_LANE_MAP_VALID_1_ALIGN 0 23097 #define RX_X4_STATUS2_RS_FEC_SYNC_STATUS_RS_FEC_FEC_LANE_MAP_VALID_1_BITS 1 23098 #define RX_X4_STATUS2_RS_FEC_SYNC_STATUS_RS_FEC_FEC_LANE_MAP_VALID_1_SHIFT 15 23099 23100 /* RX_X4_Status2 :: RS_FEC_sync_status :: RS_FEC_fec_lane_map_1 [14:11] */ 23101 #define RX_X4_STATUS2_RS_FEC_SYNC_STATUS_RS_FEC_FEC_LANE_MAP_1_MASK 0x7800 23102 #define RX_X4_STATUS2_RS_FEC_SYNC_STATUS_RS_FEC_FEC_LANE_MAP_1_ALIGN 0 23103 #define RX_X4_STATUS2_RS_FEC_SYNC_STATUS_RS_FEC_FEC_LANE_MAP_1_BITS 4 23104 #define RX_X4_STATUS2_RS_FEC_SYNC_STATUS_RS_FEC_FEC_LANE_MAP_1_SHIFT 11 23105 23106 /* RX_X4_Status2 :: RS_FEC_sync_status :: RS_FEC_amps_lock_LH_1 [10:10] */ 23107 #define RX_X4_STATUS2_RS_FEC_SYNC_STATUS_RS_FEC_AMPS_LOCK_LH_1_MASK 0x0400 23108 #define RX_X4_STATUS2_RS_FEC_SYNC_STATUS_RS_FEC_AMPS_LOCK_LH_1_ALIGN 0 23109 #define RX_X4_STATUS2_RS_FEC_SYNC_STATUS_RS_FEC_AMPS_LOCK_LH_1_BITS 1 23110 #define RX_X4_STATUS2_RS_FEC_SYNC_STATUS_RS_FEC_AMPS_LOCK_LH_1_SHIFT 10 23111 23112 /* RX_X4_Status2 :: RS_FEC_sync_status :: RS_FEC_amps_lock_LL_1 [09:09] */ 23113 #define RX_X4_STATUS2_RS_FEC_SYNC_STATUS_RS_FEC_AMPS_LOCK_LL_1_MASK 0x0200 23114 #define RX_X4_STATUS2_RS_FEC_SYNC_STATUS_RS_FEC_AMPS_LOCK_LL_1_ALIGN 0 23115 #define RX_X4_STATUS2_RS_FEC_SYNC_STATUS_RS_FEC_AMPS_LOCK_LL_1_BITS 1 23116 #define RX_X4_STATUS2_RS_FEC_SYNC_STATUS_RS_FEC_AMPS_LOCK_LL_1_SHIFT 9 23117 23118 /* RX_X4_Status2 :: RS_FEC_sync_status :: RS_FEC_amps_lock_live_1 [08:08] */ 23119 #define RX_X4_STATUS2_RS_FEC_SYNC_STATUS_RS_FEC_AMPS_LOCK_LIVE_1_MASK 0x0100 23120 #define RX_X4_STATUS2_RS_FEC_SYNC_STATUS_RS_FEC_AMPS_LOCK_LIVE_1_ALIGN 0 23121 #define RX_X4_STATUS2_RS_FEC_SYNC_STATUS_RS_FEC_AMPS_LOCK_LIVE_1_BITS 1 23122 #define RX_X4_STATUS2_RS_FEC_SYNC_STATUS_RS_FEC_AMPS_LOCK_LIVE_1_SHIFT 8 23123 23124 /* RX_X4_Status2 :: RS_FEC_sync_status :: RS_FEC_fec_lane_map_valid_0 [07:07] */ 23125 #define RX_X4_STATUS2_RS_FEC_SYNC_STATUS_RS_FEC_FEC_LANE_MAP_VALID_0_MASK 0x0080 23126 #define RX_X4_STATUS2_RS_FEC_SYNC_STATUS_RS_FEC_FEC_LANE_MAP_VALID_0_ALIGN 0 23127 #define RX_X4_STATUS2_RS_FEC_SYNC_STATUS_RS_FEC_FEC_LANE_MAP_VALID_0_BITS 1 23128 #define RX_X4_STATUS2_RS_FEC_SYNC_STATUS_RS_FEC_FEC_LANE_MAP_VALID_0_SHIFT 7 23129 23130 /* RX_X4_Status2 :: RS_FEC_sync_status :: RS_FEC_fec_lane_map_0 [06:03] */ 23131 #define RX_X4_STATUS2_RS_FEC_SYNC_STATUS_RS_FEC_FEC_LANE_MAP_0_MASK 0x0078 23132 #define RX_X4_STATUS2_RS_FEC_SYNC_STATUS_RS_FEC_FEC_LANE_MAP_0_ALIGN 0 23133 #define RX_X4_STATUS2_RS_FEC_SYNC_STATUS_RS_FEC_FEC_LANE_MAP_0_BITS 4 23134 #define RX_X4_STATUS2_RS_FEC_SYNC_STATUS_RS_FEC_FEC_LANE_MAP_0_SHIFT 3 23135 23136 /* RX_X4_Status2 :: RS_FEC_sync_status :: RS_FEC_amps_lock_LH_0 [02:02] */ 23137 #define RX_X4_STATUS2_RS_FEC_SYNC_STATUS_RS_FEC_AMPS_LOCK_LH_0_MASK 0x0004 23138 #define RX_X4_STATUS2_RS_FEC_SYNC_STATUS_RS_FEC_AMPS_LOCK_LH_0_ALIGN 0 23139 #define RX_X4_STATUS2_RS_FEC_SYNC_STATUS_RS_FEC_AMPS_LOCK_LH_0_BITS 1 23140 #define RX_X4_STATUS2_RS_FEC_SYNC_STATUS_RS_FEC_AMPS_LOCK_LH_0_SHIFT 2 23141 23142 /* RX_X4_Status2 :: RS_FEC_sync_status :: RS_FEC_amps_lock_LL_0 [01:01] */ 23143 #define RX_X4_STATUS2_RS_FEC_SYNC_STATUS_RS_FEC_AMPS_LOCK_LL_0_MASK 0x0002 23144 #define RX_X4_STATUS2_RS_FEC_SYNC_STATUS_RS_FEC_AMPS_LOCK_LL_0_ALIGN 0 23145 #define RX_X4_STATUS2_RS_FEC_SYNC_STATUS_RS_FEC_AMPS_LOCK_LL_0_BITS 1 23146 #define RX_X4_STATUS2_RS_FEC_SYNC_STATUS_RS_FEC_AMPS_LOCK_LL_0_SHIFT 1 23147 23148 /* RX_X4_Status2 :: RS_FEC_sync_status :: RS_FEC_amps_lock_live_0 [00:00] */ 23149 #define RX_X4_STATUS2_RS_FEC_SYNC_STATUS_RS_FEC_AMPS_LOCK_LIVE_0_MASK 0x0001 23150 #define RX_X4_STATUS2_RS_FEC_SYNC_STATUS_RS_FEC_AMPS_LOCK_LIVE_0_ALIGN 0 23151 #define RX_X4_STATUS2_RS_FEC_SYNC_STATUS_RS_FEC_AMPS_LOCK_LIVE_0_BITS 1 23152 #define RX_X4_STATUS2_RS_FEC_SYNC_STATUS_RS_FEC_AMPS_LOCK_LIVE_0_SHIFT 0 23153 23154 23155 /**************************************************************************** 23156 * RX_X4_Status2 :: fec_sync_fsm_state 23157 */ 23158 /* RX_X4_Status2 :: fec_sync_fsm_state :: RS_FEC_fec_sync_fsm_latched_state_hi [15:11] */ 23159 #define RX_X4_STATUS2_FEC_SYNC_FSM_STATE_RS_FEC_FEC_SYNC_FSM_LATCHED_STATE_HI_MASK 0xf800 23160 #define RX_X4_STATUS2_FEC_SYNC_FSM_STATE_RS_FEC_FEC_SYNC_FSM_LATCHED_STATE_HI_ALIGN 0 23161 #define RX_X4_STATUS2_FEC_SYNC_FSM_STATE_RS_FEC_FEC_SYNC_FSM_LATCHED_STATE_HI_BITS 5 23162 #define RX_X4_STATUS2_FEC_SYNC_FSM_STATE_RS_FEC_FEC_SYNC_FSM_LATCHED_STATE_HI_SHIFT 11 23163 #define RX_X4_STATUS2_FEC_SYNC_FSM_STATE_RS_FEC_FEC_SYNC_FSM_LATCHED_STATE_HI_LOCK_INIT 0 23164 #define RX_X4_STATUS2_FEC_SYNC_FSM_STATE_RS_FEC_FEC_SYNC_FSM_LATCHED_STATE_HI_FIND_1ST 1 23165 #define RX_X4_STATUS2_FEC_SYNC_FSM_STATE_RS_FEC_FEC_SYNC_FSM_LATCHED_STATE_HI_COUNT_NEXT 2 23166 #define RX_X4_STATUS2_FEC_SYNC_FSM_STATE_RS_FEC_FEC_SYNC_FSM_LATCHED_STATE_HI_COMP_2ND 3 23167 #define RX_X4_STATUS2_FEC_SYNC_FSM_STATE_RS_FEC_FEC_SYNC_FSM_LATCHED_STATE_HI_TWO_GOOD 4 23168 23169 /* RX_X4_Status2 :: fec_sync_fsm_state :: RS_FEC_fec_sync_fsm_live_state_hi [10:08] */ 23170 #define RX_X4_STATUS2_FEC_SYNC_FSM_STATE_RS_FEC_FEC_SYNC_FSM_LIVE_STATE_HI_MASK 0x0700 23171 #define RX_X4_STATUS2_FEC_SYNC_FSM_STATE_RS_FEC_FEC_SYNC_FSM_LIVE_STATE_HI_ALIGN 0 23172 #define RX_X4_STATUS2_FEC_SYNC_FSM_STATE_RS_FEC_FEC_SYNC_FSM_LIVE_STATE_HI_BITS 3 23173 #define RX_X4_STATUS2_FEC_SYNC_FSM_STATE_RS_FEC_FEC_SYNC_FSM_LIVE_STATE_HI_SHIFT 8 23174 #define RX_X4_STATUS2_FEC_SYNC_FSM_STATE_RS_FEC_FEC_SYNC_FSM_LIVE_STATE_HI_LOCK_INIT 0 23175 #define RX_X4_STATUS2_FEC_SYNC_FSM_STATE_RS_FEC_FEC_SYNC_FSM_LIVE_STATE_HI_FIND_1ST 1 23176 #define RX_X4_STATUS2_FEC_SYNC_FSM_STATE_RS_FEC_FEC_SYNC_FSM_LIVE_STATE_HI_COUNT_NEXT 2 23177 #define RX_X4_STATUS2_FEC_SYNC_FSM_STATE_RS_FEC_FEC_SYNC_FSM_LIVE_STATE_HI_COMP_2ND 3 23178 #define RX_X4_STATUS2_FEC_SYNC_FSM_STATE_RS_FEC_FEC_SYNC_FSM_LIVE_STATE_HI_TWO_GOOD 4 23179 23180 /* RX_X4_Status2 :: fec_sync_fsm_state :: RS_FEC_fec_sync_fsm_latched_state_lo [07:03] */ 23181 #define RX_X4_STATUS2_FEC_SYNC_FSM_STATE_RS_FEC_FEC_SYNC_FSM_LATCHED_STATE_LO_MASK 0x00f8 23182 #define RX_X4_STATUS2_FEC_SYNC_FSM_STATE_RS_FEC_FEC_SYNC_FSM_LATCHED_STATE_LO_ALIGN 0 23183 #define RX_X4_STATUS2_FEC_SYNC_FSM_STATE_RS_FEC_FEC_SYNC_FSM_LATCHED_STATE_LO_BITS 5 23184 #define RX_X4_STATUS2_FEC_SYNC_FSM_STATE_RS_FEC_FEC_SYNC_FSM_LATCHED_STATE_LO_SHIFT 3 23185 #define RX_X4_STATUS2_FEC_SYNC_FSM_STATE_RS_FEC_FEC_SYNC_FSM_LATCHED_STATE_LO_LOCK_INIT 0 23186 #define RX_X4_STATUS2_FEC_SYNC_FSM_STATE_RS_FEC_FEC_SYNC_FSM_LATCHED_STATE_LO_FIND_1ST 1 23187 #define RX_X4_STATUS2_FEC_SYNC_FSM_STATE_RS_FEC_FEC_SYNC_FSM_LATCHED_STATE_LO_COUNT_NEXT 2 23188 #define RX_X4_STATUS2_FEC_SYNC_FSM_STATE_RS_FEC_FEC_SYNC_FSM_LATCHED_STATE_LO_COMP_2ND 3 23189 #define RX_X4_STATUS2_FEC_SYNC_FSM_STATE_RS_FEC_FEC_SYNC_FSM_LATCHED_STATE_LO_TWO_GOOD 4 23190 23191 /* RX_X4_Status2 :: fec_sync_fsm_state :: RS_FEC_fec_sync_fsm_live_state_lo [02:00] */ 23192 #define RX_X4_STATUS2_FEC_SYNC_FSM_STATE_RS_FEC_FEC_SYNC_FSM_LIVE_STATE_LO_MASK 0x0007 23193 #define RX_X4_STATUS2_FEC_SYNC_FSM_STATE_RS_FEC_FEC_SYNC_FSM_LIVE_STATE_LO_ALIGN 0 23194 #define RX_X4_STATUS2_FEC_SYNC_FSM_STATE_RS_FEC_FEC_SYNC_FSM_LIVE_STATE_LO_BITS 3 23195 #define RX_X4_STATUS2_FEC_SYNC_FSM_STATE_RS_FEC_FEC_SYNC_FSM_LIVE_STATE_LO_SHIFT 0 23196 #define RX_X4_STATUS2_FEC_SYNC_FSM_STATE_RS_FEC_FEC_SYNC_FSM_LIVE_STATE_LO_LOCK_INIT 0 23197 #define RX_X4_STATUS2_FEC_SYNC_FSM_STATE_RS_FEC_FEC_SYNC_FSM_LIVE_STATE_LO_FIND_1ST 1 23198 #define RX_X4_STATUS2_FEC_SYNC_FSM_STATE_RS_FEC_FEC_SYNC_FSM_LIVE_STATE_LO_COUNT_NEXT 2 23199 #define RX_X4_STATUS2_FEC_SYNC_FSM_STATE_RS_FEC_FEC_SYNC_FSM_LIVE_STATE_LO_COMP_2ND 3 23200 #define RX_X4_STATUS2_FEC_SYNC_FSM_STATE_RS_FEC_FEC_SYNC_FSM_LIVE_STATE_LO_TWO_GOOD 4 23201 23202 23203 /**************************************************************************** 23204 * TSC_TSC_USER4_RX_X4_Status3 23205 */ 23206 /**************************************************************************** 23207 * RX_X4_Status3 :: fec_dbg_errL_0 23208 */ 23209 /* RX_X4_Status3 :: fec_dbg_errL_0 :: dbg_errL_stream0 [15:00] */ 23210 #define RX_X4_STATUS3_FEC_DBG_ERRL_0_DBG_ERRL_STREAM0_MASK 0xffff 23211 #define RX_X4_STATUS3_FEC_DBG_ERRL_0_DBG_ERRL_STREAM0_ALIGN 0 23212 #define RX_X4_STATUS3_FEC_DBG_ERRL_0_DBG_ERRL_STREAM0_BITS 16 23213 #define RX_X4_STATUS3_FEC_DBG_ERRL_0_DBG_ERRL_STREAM0_SHIFT 0 23214 23215 23216 /**************************************************************************** 23217 * RX_X4_Status3 :: fec_dbg_erraH_0 23218 */ 23219 /* RX_X4_Status3 :: fec_dbg_erraH_0 :: dbg_errH_stream0 [15:00] */ 23220 #define RX_X4_STATUS3_FEC_DBG_ERRAH_0_DBG_ERRH_STREAM0_MASK 0xffff 23221 #define RX_X4_STATUS3_FEC_DBG_ERRAH_0_DBG_ERRH_STREAM0_ALIGN 0 23222 #define RX_X4_STATUS3_FEC_DBG_ERRAH_0_DBG_ERRH_STREAM0_BITS 16 23223 #define RX_X4_STATUS3_FEC_DBG_ERRAH_0_DBG_ERRH_STREAM0_SHIFT 0 23224 23225 23226 /**************************************************************************** 23227 * RX_X4_Status3 :: fec_burst_err_statusL_0 23228 */ 23229 /* RX_X4_Status3 :: fec_burst_err_statusL_0 :: burst_err_statusL_stream0 [15:00] */ 23230 #define RX_X4_STATUS3_FEC_BURST_ERR_STATUSL_0_BURST_ERR_STATUSL_STREAM0_MASK 0xffff 23231 #define RX_X4_STATUS3_FEC_BURST_ERR_STATUSL_0_BURST_ERR_STATUSL_STREAM0_ALIGN 0 23232 #define RX_X4_STATUS3_FEC_BURST_ERR_STATUSL_0_BURST_ERR_STATUSL_STREAM0_BITS 16 23233 #define RX_X4_STATUS3_FEC_BURST_ERR_STATUSL_0_BURST_ERR_STATUSL_STREAM0_SHIFT 0 23234 23235 23236 /**************************************************************************** 23237 * TSC_TSC_USER4_RX_X4_Status4 23238 */ 23239 /**************************************************************************** 23240 * RX_X4_Status4 :: fec_burst_err_statusH_0 23241 */ 23242 /* RX_X4_Status4 :: fec_burst_err_statusH_0 :: burst_err_statusH_stream0 [15:00] */ 23243 #define RX_X4_STATUS4_FEC_BURST_ERR_STATUSH_0_BURST_ERR_STATUSH_STREAM0_MASK 0xffff 23244 #define RX_X4_STATUS4_FEC_BURST_ERR_STATUSH_0_BURST_ERR_STATUSH_STREAM0_ALIGN 0 23245 #define RX_X4_STATUS4_FEC_BURST_ERR_STATUSH_0_BURST_ERR_STATUSH_STREAM0_BITS 16 23246 #define RX_X4_STATUS4_FEC_BURST_ERR_STATUSH_0_BURST_ERR_STATUSH_STREAM0_SHIFT 0 23247 23248 23249 /**************************************************************************** 23250 * RX_X4_Status4 :: fec_CorrectedBlksL_0 23251 */ 23252 /* RX_X4_Status4 :: fec_CorrectedBlksL_0 :: corCountL_stream0 [15:00] */ 23253 #define RX_X4_STATUS4_FEC_CORRECTEDBLKSL_0_CORCOUNTL_STREAM0_MASK 0xffff 23254 #define RX_X4_STATUS4_FEC_CORRECTEDBLKSL_0_CORCOUNTL_STREAM0_ALIGN 0 23255 #define RX_X4_STATUS4_FEC_CORRECTEDBLKSL_0_CORCOUNTL_STREAM0_BITS 16 23256 #define RX_X4_STATUS4_FEC_CORRECTEDBLKSL_0_CORCOUNTL_STREAM0_SHIFT 0 23257 23258 23259 /**************************************************************************** 23260 * RX_X4_Status4 :: fec_CorrectedBlksH_0 23261 */ 23262 /* RX_X4_Status4 :: fec_CorrectedBlksH_0 :: corCountH_stream0 [15:00] */ 23263 #define RX_X4_STATUS4_FEC_CORRECTEDBLKSH_0_CORCOUNTH_STREAM0_MASK 0xffff 23264 #define RX_X4_STATUS4_FEC_CORRECTEDBLKSH_0_CORCOUNTH_STREAM0_ALIGN 0 23265 #define RX_X4_STATUS4_FEC_CORRECTEDBLKSH_0_CORCOUNTH_STREAM0_BITS 16 23266 #define RX_X4_STATUS4_FEC_CORRECTEDBLKSH_0_CORCOUNTH_STREAM0_SHIFT 0 23267 23268 23269 /**************************************************************************** 23270 * TSC_TSC_USER4_RX_X4_Status5 23271 */ 23272 /**************************************************************************** 23273 * RX_X4_Status5 :: fec_UncorrectedBlksL_0 23274 */ 23275 /* RX_X4_Status5 :: fec_UncorrectedBlksL_0 :: uncorCountL_stream0 [15:00] */ 23276 #define RX_X4_STATUS5_FEC_UNCORRECTEDBLKSL_0_UNCORCOUNTL_STREAM0_MASK 0xffff 23277 #define RX_X4_STATUS5_FEC_UNCORRECTEDBLKSL_0_UNCORCOUNTL_STREAM0_ALIGN 0 23278 #define RX_X4_STATUS5_FEC_UNCORRECTEDBLKSL_0_UNCORCOUNTL_STREAM0_BITS 16 23279 #define RX_X4_STATUS5_FEC_UNCORRECTEDBLKSL_0_UNCORCOUNTL_STREAM0_SHIFT 0 23280 23281 23282 /**************************************************************************** 23283 * RX_X4_Status5 :: fec_UncorrectedBlksH_0 23284 */ 23285 /* RX_X4_Status5 :: fec_UncorrectedBlksH_0 :: uncorCountH_stream0 [15:00] */ 23286 #define RX_X4_STATUS5_FEC_UNCORRECTEDBLKSH_0_UNCORCOUNTH_STREAM0_MASK 0xffff 23287 #define RX_X4_STATUS5_FEC_UNCORRECTEDBLKSH_0_UNCORCOUNTH_STREAM0_ALIGN 0 23288 #define RX_X4_STATUS5_FEC_UNCORRECTEDBLKSH_0_UNCORCOUNTH_STREAM0_BITS 16 23289 #define RX_X4_STATUS5_FEC_UNCORRECTEDBLKSH_0_UNCORCOUNTH_STREAM0_SHIFT 0 23290 23291 23292 /**************************************************************************** 23293 * TSC_TSC_USER4_RX_X4_TEST_Status0 23294 */ 23295 /**************************************************************************** 23296 * RX_X4_TEST_Status0 :: PrtpErrorCounter 23297 */ 23298 /* RX_X4_TEST_Status0 :: PrtpErrorCounter :: prtp_err_count [15:00] */ 23299 #define RX_X4_TEST_STATUS0_PRTPERRORCOUNTER_PRTP_ERR_COUNT_MASK 0xffff 23300 #define RX_X4_TEST_STATUS0_PRTPERRORCOUNTER_PRTP_ERR_COUNT_ALIGN 0 23301 #define RX_X4_TEST_STATUS0_PRTPERRORCOUNTER_PRTP_ERR_COUNT_BITS 16 23302 #define RX_X4_TEST_STATUS0_PRTPERRORCOUNTER_PRTP_ERR_COUNT_SHIFT 0 23303 23304 23305 /**************************************************************************** 23306 * RX_X4_TEST_Status0 :: PrtpStatus 23307 */ 23308 /* RX_X4_TEST_Status0 :: PrtpStatus :: reserved0 [15:01] */ 23309 #define RX_X4_TEST_STATUS0_PRTPSTATUS_RESERVED0_MASK 0xfffe 23310 #define RX_X4_TEST_STATUS0_PRTPSTATUS_RESERVED0_ALIGN 0 23311 #define RX_X4_TEST_STATUS0_PRTPSTATUS_RESERVED0_BITS 15 23312 #define RX_X4_TEST_STATUS0_PRTPSTATUS_RESERVED0_SHIFT 1 23313 23314 /* RX_X4_TEST_Status0 :: PrtpStatus :: prtp_lock [00:00] */ 23315 #define RX_X4_TEST_STATUS0_PRTPSTATUS_PRTP_LOCK_MASK 0x0001 23316 #define RX_X4_TEST_STATUS0_PRTPSTATUS_PRTP_LOCK_ALIGN 0 23317 #define RX_X4_TEST_STATUS0_PRTPSTATUS_PRTP_LOCK_BITS 1 23318 #define RX_X4_TEST_STATUS0_PRTPSTATUS_PRTP_LOCK_SHIFT 0 23319 23320 23321 /**************************************************************************** 23322 * RX_X4_TEST_Status0 :: cl82_scridle_test_err 23323 */ 23324 /* RX_X4_TEST_Status0 :: cl82_scridle_test_err :: cl82_scridle_test_err [15:00] */ 23325 #define RX_X4_TEST_STATUS0_CL82_SCRIDLE_TEST_ERR_CL82_SCRIDLE_TEST_ERR_MASK 0xffff 23326 #define RX_X4_TEST_STATUS0_CL82_SCRIDLE_TEST_ERR_CL82_SCRIDLE_TEST_ERR_ALIGN 0 23327 #define RX_X4_TEST_STATUS0_CL82_SCRIDLE_TEST_ERR_CL82_SCRIDLE_TEST_ERR_BITS 16 23328 #define RX_X4_TEST_STATUS0_CL82_SCRIDLE_TEST_ERR_CL82_SCRIDLE_TEST_ERR_SHIFT 0 23329 23330 23331 /**************************************************************************** 23332 * TSC_TSC_USER4_AN_X4_ABILITIES 23333 */ 23334 /**************************************************************************** 23335 * AN_X4_ABILITIES :: cl73_cfg 23336 */ 23337 /* AN_X4_ABILITIES :: cl73_cfg :: reserved0 [15:14] */ 23338 #define AN_X4_ABILITIES_CL73_CFG_RESERVED0_MASK 0xc000 23339 #define AN_X4_ABILITIES_CL73_CFG_RESERVED0_ALIGN 0 23340 #define AN_X4_ABILITIES_CL73_CFG_RESERVED0_BITS 2 23341 #define AN_X4_ABILITIES_CL73_CFG_RESERVED0_SHIFT 14 23342 23343 /* AN_X4_ABILITIES :: cl73_cfg :: disable_remote_fault [13:13] */ 23344 #define AN_X4_ABILITIES_CL73_CFG_DISABLE_REMOTE_FAULT_MASK 0x2000 23345 #define AN_X4_ABILITIES_CL73_CFG_DISABLE_REMOTE_FAULT_ALIGN 0 23346 #define AN_X4_ABILITIES_CL73_CFG_DISABLE_REMOTE_FAULT_BITS 1 23347 #define AN_X4_ABILITIES_CL73_CFG_DISABLE_REMOTE_FAULT_SHIFT 13 23348 23349 /* AN_X4_ABILITIES :: cl73_cfg :: num_advertised_lanes [12:11] */ 23350 #define AN_X4_ABILITIES_CL73_CFG_NUM_ADVERTISED_LANES_MASK 0x1800 23351 #define AN_X4_ABILITIES_CL73_CFG_NUM_ADVERTISED_LANES_ALIGN 0 23352 #define AN_X4_ABILITIES_CL73_CFG_NUM_ADVERTISED_LANES_BITS 2 23353 #define AN_X4_ABILITIES_CL73_CFG_NUM_ADVERTISED_LANES_SHIFT 11 23354 23355 /* AN_X4_ABILITIES :: cl73_cfg :: cl73_bam_enable [10:10] */ 23356 #define AN_X4_ABILITIES_CL73_CFG_CL73_BAM_ENABLE_MASK 0x0400 23357 #define AN_X4_ABILITIES_CL73_CFG_CL73_BAM_ENABLE_ALIGN 0 23358 #define AN_X4_ABILITIES_CL73_CFG_CL73_BAM_ENABLE_BITS 1 23359 #define AN_X4_ABILITIES_CL73_CFG_CL73_BAM_ENABLE_SHIFT 10 23360 23361 /* AN_X4_ABILITIES :: cl73_cfg :: MSA_Fec_Mapping [09:09] */ 23362 #define AN_X4_ABILITIES_CL73_CFG_MSA_FEC_MAPPING_MASK 0x0200 23363 #define AN_X4_ABILITIES_CL73_CFG_MSA_FEC_MAPPING_ALIGN 0 23364 #define AN_X4_ABILITIES_CL73_CFG_MSA_FEC_MAPPING_BITS 1 23365 #define AN_X4_ABILITIES_CL73_CFG_MSA_FEC_MAPPING_SHIFT 9 23366 23367 /* AN_X4_ABILITIES :: cl73_cfg :: cl73_enable [08:08] */ 23368 #define AN_X4_ABILITIES_CL73_CFG_CL73_ENABLE_MASK 0x0100 23369 #define AN_X4_ABILITIES_CL73_CFG_CL73_ENABLE_ALIGN 0 23370 #define AN_X4_ABILITIES_CL73_CFG_CL73_ENABLE_BITS 1 23371 #define AN_X4_ABILITIES_CL73_CFG_CL73_ENABLE_SHIFT 8 23372 23373 /* AN_X4_ABILITIES :: cl73_cfg :: reserved1 [07:07] */ 23374 #define AN_X4_ABILITIES_CL73_CFG_RESERVED1_MASK 0x0080 23375 #define AN_X4_ABILITIES_CL73_CFG_RESERVED1_ALIGN 0 23376 #define AN_X4_ABILITIES_CL73_CFG_RESERVED1_BITS 1 23377 #define AN_X4_ABILITIES_CL73_CFG_RESERVED1_SHIFT 7 23378 23379 /* AN_X4_ABILITIES :: cl73_cfg :: cl73_nonce_match_over [06:06] */ 23380 #define AN_X4_ABILITIES_CL73_CFG_CL73_NONCE_MATCH_OVER_MASK 0x0040 23381 #define AN_X4_ABILITIES_CL73_CFG_CL73_NONCE_MATCH_OVER_ALIGN 0 23382 #define AN_X4_ABILITIES_CL73_CFG_CL73_NONCE_MATCH_OVER_BITS 1 23383 #define AN_X4_ABILITIES_CL73_CFG_CL73_NONCE_MATCH_OVER_SHIFT 6 23384 23385 /* AN_X4_ABILITIES :: cl73_cfg :: cl73_nonce_match_val [05:05] */ 23386 #define AN_X4_ABILITIES_CL73_CFG_CL73_NONCE_MATCH_VAL_MASK 0x0020 23387 #define AN_X4_ABILITIES_CL73_CFG_CL73_NONCE_MATCH_VAL_ALIGN 0 23388 #define AN_X4_ABILITIES_CL73_CFG_CL73_NONCE_MATCH_VAL_BITS 1 23389 #define AN_X4_ABILITIES_CL73_CFG_CL73_NONCE_MATCH_VAL_SHIFT 5 23390 23391 /* AN_X4_ABILITIES :: cl73_cfg :: reserved2 [04:01] */ 23392 #define AN_X4_ABILITIES_CL73_CFG_RESERVED2_MASK 0x001e 23393 #define AN_X4_ABILITIES_CL73_CFG_RESERVED2_ALIGN 0 23394 #define AN_X4_ABILITIES_CL73_CFG_RESERVED2_BITS 4 23395 #define AN_X4_ABILITIES_CL73_CFG_RESERVED2_SHIFT 1 23396 23397 /* AN_X4_ABILITIES :: cl73_cfg :: cl73_an_restart [00:00] */ 23398 #define AN_X4_ABILITIES_CL73_CFG_CL73_AN_RESTART_MASK 0x0001 23399 #define AN_X4_ABILITIES_CL73_CFG_CL73_AN_RESTART_ALIGN 0 23400 #define AN_X4_ABILITIES_CL73_CFG_CL73_AN_RESTART_BITS 1 23401 #define AN_X4_ABILITIES_CL73_CFG_CL73_AN_RESTART_SHIFT 0 23402 23403 23404 /**************************************************************************** 23405 * AN_X4_ABILITIES :: ld_up1_abilities_0 23406 */ 23407 /* AN_X4_ABILITIES :: ld_up1_abilities_0 :: BAM_50G_BRCM_FEC_544_CR2_KR2 [15:15] */ 23408 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_50G_BRCM_FEC_544_CR2_KR2_MASK 0x8000 23409 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_50G_BRCM_FEC_544_CR2_KR2_ALIGN 0 23410 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_50G_BRCM_FEC_544_CR2_KR2_BITS 1 23411 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_50G_BRCM_FEC_544_CR2_KR2_SHIFT 15 23412 23413 /* AN_X4_ABILITIES :: ld_up1_abilities_0 :: RESERVED_19 [14:14] */ 23414 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_RESERVED_19_MASK 0x4000 23415 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_RESERVED_19_ALIGN 0 23416 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_RESERVED_19_BITS 1 23417 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_RESERVED_19_SHIFT 14 23418 23419 /* AN_X4_ABILITIES :: ld_up1_abilities_0 :: RESERVED_22 [13:13] */ 23420 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_RESERVED_22_MASK 0x2000 23421 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_RESERVED_22_ALIGN 0 23422 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_RESERVED_22_BITS 1 23423 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_RESERVED_22_SHIFT 13 23424 23425 /* AN_X4_ABILITIES :: ld_up1_abilities_0 :: BAM_50G_BRCM_FEC_544_CR1_KR1 [12:12] */ 23426 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_50G_BRCM_FEC_544_CR1_KR1_MASK 0x1000 23427 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_50G_BRCM_FEC_544_CR1_KR1_ALIGN 0 23428 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_50G_BRCM_FEC_544_CR1_KR1_BITS 1 23429 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_50G_BRCM_FEC_544_CR1_KR1_SHIFT 12 23430 23431 /* AN_X4_ABILITIES :: ld_up1_abilities_0 :: BAM_50G_BRCM_NO_FEC_CR1_KR1 [11:11] */ 23432 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_50G_BRCM_NO_FEC_CR1_KR1_MASK 0x0800 23433 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_50G_BRCM_NO_FEC_CR1_KR1_ALIGN 0 23434 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_50G_BRCM_NO_FEC_CR1_KR1_BITS 1 23435 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_50G_BRCM_NO_FEC_CR1_KR1_SHIFT 11 23436 23437 /* AN_X4_ABILITIES :: ld_up1_abilities_0 :: BAM_50G_BRCM_FEC_528_CR1_KR1 [10:10] */ 23438 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_50G_BRCM_FEC_528_CR1_KR1_MASK 0x0400 23439 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_50G_BRCM_FEC_528_CR1_KR1_ALIGN 0 23440 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_50G_BRCM_FEC_528_CR1_KR1_BITS 1 23441 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_50G_BRCM_FEC_528_CR1_KR1_SHIFT 10 23442 23443 /* AN_X4_ABILITIES :: ld_up1_abilities_0 :: BAM_50G_CR4 [09:09] */ 23444 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_50G_CR4_MASK 0x0200 23445 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_50G_CR4_ALIGN 0 23446 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_50G_CR4_BITS 1 23447 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_50G_CR4_SHIFT 9 23448 23449 /* AN_X4_ABILITIES :: ld_up1_abilities_0 :: BAM_50G_KR4 [08:08] */ 23450 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_50G_KR4_MASK 0x0100 23451 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_50G_KR4_ALIGN 0 23452 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_50G_KR4_BITS 1 23453 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_50G_KR4_SHIFT 8 23454 23455 /* AN_X4_ABILITIES :: ld_up1_abilities_0 :: BAM_50G_CR2 [07:07] */ 23456 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_50G_CR2_MASK 0x0080 23457 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_50G_CR2_ALIGN 0 23458 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_50G_CR2_BITS 1 23459 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_50G_CR2_SHIFT 7 23460 23461 /* AN_X4_ABILITIES :: ld_up1_abilities_0 :: BAM_50G_KR2 [06:06] */ 23462 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_50G_KR2_MASK 0x0040 23463 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_50G_KR2_ALIGN 0 23464 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_50G_KR2_BITS 1 23465 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_50G_KR2_SHIFT 6 23466 23467 /* AN_X4_ABILITIES :: ld_up1_abilities_0 :: BAM_400G_BRCM_NO_FEC_KR8_CR8 [05:05] */ 23468 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_400G_BRCM_NO_FEC_KR8_CR8_MASK 0x0020 23469 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_400G_BRCM_NO_FEC_KR8_CR8_ALIGN 0 23470 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_400G_BRCM_NO_FEC_KR8_CR8_BITS 1 23471 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_400G_BRCM_NO_FEC_KR8_CR8_SHIFT 5 23472 23473 /* AN_X4_ABILITIES :: ld_up1_abilities_0 :: BAM_400G_BRCM_FEC_KR8_CR8 [04:04] */ 23474 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_400G_BRCM_FEC_KR8_CR8_MASK 0x0010 23475 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_400G_BRCM_FEC_KR8_CR8_ALIGN 0 23476 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_400G_BRCM_FEC_KR8_CR8_BITS 1 23477 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_400G_BRCM_FEC_KR8_CR8_SHIFT 4 23478 23479 /* AN_X4_ABILITIES :: ld_up1_abilities_0 :: BAM_40G_CR2 [03:03] */ 23480 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_40G_CR2_MASK 0x0008 23481 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_40G_CR2_ALIGN 0 23482 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_40G_CR2_BITS 1 23483 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_40G_CR2_SHIFT 3 23484 23485 /* AN_X4_ABILITIES :: ld_up1_abilities_0 :: BAM_40G_KR2 [02:02] */ 23486 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_40G_KR2_MASK 0x0004 23487 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_40G_KR2_ALIGN 0 23488 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_40G_KR2_BITS 1 23489 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_40G_KR2_SHIFT 2 23490 23491 /* AN_X4_ABILITIES :: ld_up1_abilities_0 :: BAM_20G_CR2 [01:01] */ 23492 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_20G_CR2_MASK 0x0002 23493 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_20G_CR2_ALIGN 0 23494 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_20G_CR2_BITS 1 23495 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_20G_CR2_SHIFT 1 23496 23497 /* AN_X4_ABILITIES :: ld_up1_abilities_0 :: BAM_20G_KR2 [00:00] */ 23498 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_20G_KR2_MASK 0x0001 23499 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_20G_KR2_ALIGN 0 23500 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_20G_KR2_BITS 1 23501 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_0_BAM_20G_KR2_SHIFT 0 23502 23503 23504 /**************************************************************************** 23505 * AN_X4_ABILITIES :: ld_up1_abilities_1 23506 */ 23507 /* AN_X4_ABILITIES :: ld_up1_abilities_1 :: cl74_req [15:14] */ 23508 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_CL74_REQ_MASK 0xc000 23509 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_CL74_REQ_ALIGN 0 23510 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_CL74_REQ_BITS 2 23511 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_CL74_REQ_SHIFT 14 23512 23513 /* AN_X4_ABILITIES :: ld_up1_abilities_1 :: RS_FEC_req [13:12] */ 23514 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_RS_FEC_REQ_MASK 0x3000 23515 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_RS_FEC_REQ_ALIGN 0 23516 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_RS_FEC_REQ_BITS 2 23517 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_RS_FEC_REQ_SHIFT 12 23518 23519 /* AN_X4_ABILITIES :: ld_up1_abilities_1 :: reserved0 [11:11] */ 23520 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_RESERVED0_MASK 0x0800 23521 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_RESERVED0_ALIGN 0 23522 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_RESERVED0_BITS 1 23523 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_RESERVED0_SHIFT 11 23524 23525 /* AN_X4_ABILITIES :: ld_up1_abilities_1 :: BAM_200G_BRCM_NO_FEC_KR4_CR4 [10:10] */ 23526 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_BAM_200G_BRCM_NO_FEC_KR4_CR4_MASK 0x0400 23527 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_BAM_200G_BRCM_NO_FEC_KR4_CR4_ALIGN 0 23528 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_BAM_200G_BRCM_NO_FEC_KR4_CR4_BITS 1 23529 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_BAM_200G_BRCM_NO_FEC_KR4_CR4_SHIFT 10 23530 23531 /* AN_X4_ABILITIES :: ld_up1_abilities_1 :: BAM_200G_BRCM_KR4_CR4 [09:09] */ 23532 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_BAM_200G_BRCM_KR4_CR4_MASK 0x0200 23533 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_BAM_200G_BRCM_KR4_CR4_ALIGN 0 23534 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_BAM_200G_BRCM_KR4_CR4_BITS 1 23535 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_BAM_200G_BRCM_KR4_CR4_SHIFT 9 23536 23537 /* AN_X4_ABILITIES :: ld_up1_abilities_1 :: BAM_100G_BRCM_KR4_CR4 [08:08] */ 23538 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_BAM_100G_BRCM_KR4_CR4_MASK 0x0100 23539 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_BAM_100G_BRCM_KR4_CR4_ALIGN 0 23540 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_BAM_100G_BRCM_KR4_CR4_BITS 1 23541 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_BAM_100G_BRCM_KR4_CR4_SHIFT 8 23542 23543 /* AN_X4_ABILITIES :: ld_up1_abilities_1 :: BAM_100G_BRCM_FEC_528_KR2_CR2 [07:07] */ 23544 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_BAM_100G_BRCM_FEC_528_KR2_CR2_MASK 0x0080 23545 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_BAM_100G_BRCM_FEC_528_KR2_CR2_ALIGN 0 23546 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_BAM_100G_BRCM_FEC_528_KR2_CR2_BITS 1 23547 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_BAM_100G_BRCM_FEC_528_KR2_CR2_SHIFT 7 23548 23549 /* AN_X4_ABILITIES :: ld_up1_abilities_1 :: BAM_100G_BRCM_NO_FEC_KR2_CR2 [06:06] */ 23550 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_BAM_100G_BRCM_NO_FEC_KR2_CR2_MASK 0x0040 23551 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_BAM_100G_BRCM_NO_FEC_KR2_CR2_ALIGN 0 23552 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_BAM_100G_BRCM_NO_FEC_KR2_CR2_BITS 1 23553 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_BAM_100G_BRCM_NO_FEC_KR2_CR2_SHIFT 6 23554 23555 /* AN_X4_ABILITIES :: ld_up1_abilities_1 :: BAM_100G_BRCM_NO_FEC_X4 [05:05] */ 23556 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_BAM_100G_BRCM_NO_FEC_X4_MASK 0x0020 23557 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_BAM_100G_BRCM_NO_FEC_X4_ALIGN 0 23558 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_BAM_100G_BRCM_NO_FEC_X4_BITS 1 23559 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_BAM_100G_BRCM_NO_FEC_X4_SHIFT 5 23560 23561 /* AN_X4_ABILITIES :: ld_up1_abilities_1 :: BAM_25G_CR1 [04:04] */ 23562 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_BAM_25G_CR1_MASK 0x0010 23563 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_BAM_25G_CR1_ALIGN 0 23564 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_BAM_25G_CR1_BITS 1 23565 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_BAM_25G_CR1_SHIFT 4 23566 23567 /* AN_X4_ABILITIES :: ld_up1_abilities_1 :: BAM_25G_KR1 [03:03] */ 23568 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_BAM_25G_KR1_MASK 0x0008 23569 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_BAM_25G_KR1_ALIGN 0 23570 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_BAM_25G_KR1_BITS 1 23571 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_BAM_25G_KR1_SHIFT 3 23572 23573 /* AN_X4_ABILITIES :: ld_up1_abilities_1 :: BAM_20G_CR1 [02:02] */ 23574 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_BAM_20G_CR1_MASK 0x0004 23575 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_BAM_20G_CR1_ALIGN 0 23576 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_BAM_20G_CR1_BITS 1 23577 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_BAM_20G_CR1_SHIFT 2 23578 23579 /* AN_X4_ABILITIES :: ld_up1_abilities_1 :: BAM_20G_KR1 [01:01] */ 23580 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_BAM_20G_KR1_MASK 0x0002 23581 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_BAM_20G_KR1_ALIGN 0 23582 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_BAM_20G_KR1_BITS 1 23583 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_BAM_20G_KR1_SHIFT 1 23584 23585 /* AN_X4_ABILITIES :: ld_up1_abilities_1 :: reserved1 [00:00] */ 23586 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_RESERVED1_MASK 0x0001 23587 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_RESERVED1_ALIGN 0 23588 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_RESERVED1_BITS 1 23589 #define AN_X4_ABILITIES_LD_UP1_ABILITIES_1_RESERVED1_SHIFT 0 23590 23591 23592 /**************************************************************************** 23593 * AN_X4_ABILITIES :: ld_base_abilities_0 23594 */ 23595 /* AN_X4_ABILITIES :: ld_base_abilities_0 :: reserved0 [15:10] */ 23596 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_0_RESERVED0_MASK 0xfc00 23597 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_0_RESERVED0_ALIGN 0 23598 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_0_RESERVED0_BITS 6 23599 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_0_RESERVED0_SHIFT 10 23600 23601 /* AN_X4_ABILITIES :: ld_base_abilities_0 :: tx_nonce [09:05] */ 23602 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_0_TX_NONCE_MASK 0x03e0 23603 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_0_TX_NONCE_ALIGN 0 23604 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_0_TX_NONCE_BITS 5 23605 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_0_TX_NONCE_SHIFT 5 23606 23607 /* AN_X4_ABILITIES :: ld_base_abilities_0 :: cl73_base_selector [04:00] */ 23608 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_0_CL73_BASE_SELECTOR_MASK 0x001f 23609 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_0_CL73_BASE_SELECTOR_ALIGN 0 23610 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_0_CL73_BASE_SELECTOR_BITS 5 23611 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_0_CL73_BASE_SELECTOR_SHIFT 0 23612 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_0_CL73_BASE_SELECTOR_RESERVED 0 23613 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_0_CL73_BASE_SELECTOR_VALUE_802p3 1 23614 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_0_CL73_BASE_SELECTOR_VALUE_802p9 2 23615 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_0_CL73_BASE_SELECTOR_VALUE_802p5 3 23616 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_0_CL73_BASE_SELECTOR_VALUE_1394 4 23617 23618 23619 /**************************************************************************** 23620 * AN_X4_ABILITIES :: ld_base_abilities_1 23621 */ 23622 /* AN_X4_ABILITIES :: ld_base_abilities_1 :: BASE_25G_CRS_KRS [15:15] */ 23623 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_BASE_25G_CRS_KRS_MASK 0x8000 23624 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_BASE_25G_CRS_KRS_ALIGN 0 23625 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_BASE_25G_CRS_KRS_BITS 1 23626 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_BASE_25G_CRS_KRS_SHIFT 15 23627 23628 /* AN_X4_ABILITIES :: ld_base_abilities_1 :: BASE_25G_CR_KR [14:14] */ 23629 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_BASE_25G_CR_KR_MASK 0x4000 23630 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_BASE_25G_CR_KR_ALIGN 0 23631 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_BASE_25G_CR_KR_BITS 1 23632 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_BASE_25G_CR_KR_SHIFT 14 23633 23634 /* AN_X4_ABILITIES :: ld_base_abilities_1 :: BASE_25G_RS_FEC_REQ [13:13] */ 23635 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_BASE_25G_RS_FEC_REQ_MASK 0x2000 23636 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_BASE_25G_RS_FEC_REQ_ALIGN 0 23637 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_BASE_25G_RS_FEC_REQ_BITS 1 23638 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_BASE_25G_RS_FEC_REQ_SHIFT 13 23639 23640 /* AN_X4_ABILITIES :: ld_base_abilities_1 :: BASE_25G_BASE_R_FEC_REQ [12:12] */ 23641 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_BASE_25G_BASE_R_FEC_REQ_MASK 0x1000 23642 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_BASE_25G_BASE_R_FEC_REQ_ALIGN 0 23643 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_BASE_25G_BASE_R_FEC_REQ_BITS 1 23644 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_BASE_25G_BASE_R_FEC_REQ_SHIFT 12 23645 23646 /* AN_X4_ABILITIES :: ld_base_abilities_1 :: cl73_remote_fault [11:11] */ 23647 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_CL73_REMOTE_FAULT_MASK 0x0800 23648 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_CL73_REMOTE_FAULT_ALIGN 0 23649 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_CL73_REMOTE_FAULT_BITS 1 23650 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_CL73_REMOTE_FAULT_SHIFT 11 23651 23652 /* AN_X4_ABILITIES :: ld_base_abilities_1 :: next_page [10:10] */ 23653 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_NEXT_PAGE_MASK 0x0400 23654 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_NEXT_PAGE_ALIGN 0 23655 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_NEXT_PAGE_BITS 1 23656 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_NEXT_PAGE_SHIFT 10 23657 23658 /* AN_X4_ABILITIES :: ld_base_abilities_1 :: fec_req [09:08] */ 23659 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_FEC_REQ_MASK 0x0300 23660 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_FEC_REQ_ALIGN 0 23661 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_FEC_REQ_BITS 2 23662 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_FEC_REQ_SHIFT 8 23663 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_FEC_REQ_FEC_not_supported 0 23664 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_FEC_REQ_FEC_supported_but_not_requested 1 23665 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_FEC_REQ_invalid_setting 2 23666 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_FEC_REQ_FEC_supported_and_requested 3 23667 23668 /* AN_X4_ABILITIES :: ld_base_abilities_1 :: cl73_pause [07:06] */ 23669 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_CL73_PAUSE_MASK 0x00c0 23670 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_CL73_PAUSE_ALIGN 0 23671 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_CL73_PAUSE_BITS 2 23672 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_CL73_PAUSE_SHIFT 6 23673 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_CL73_PAUSE_No_PAUSE_ability 0 23674 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_CL73_PAUSE_Asymmetric_toward_link_partner_PAUSE_ability 2 23675 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_CL73_PAUSE_Symmetric_PAUSE_ability 1 23676 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_CL73_PAUSE_Both_symmetric_and_asymmetric_toward_local_device_PAUSE_ability 3 23677 23678 /* AN_X4_ABILITIES :: ld_base_abilities_1 :: reserved0 [05:05] */ 23679 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_RESERVED0_MASK 0x0020 23680 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_RESERVED0_ALIGN 0 23681 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_RESERVED0_BITS 1 23682 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_RESERVED0_SHIFT 5 23683 23684 /* AN_X4_ABILITIES :: ld_base_abilities_1 :: BASE_100G_CR4 [04:04] */ 23685 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_BASE_100G_CR4_MASK 0x0010 23686 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_BASE_100G_CR4_ALIGN 0 23687 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_BASE_100G_CR4_BITS 1 23688 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_BASE_100G_CR4_SHIFT 4 23689 23690 /* AN_X4_ABILITIES :: ld_base_abilities_1 :: BASE_100G_KR4 [03:03] */ 23691 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_BASE_100G_KR4_MASK 0x0008 23692 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_BASE_100G_KR4_ALIGN 0 23693 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_BASE_100G_KR4_BITS 1 23694 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_BASE_100G_KR4_SHIFT 3 23695 23696 /* AN_X4_ABILITIES :: ld_base_abilities_1 :: BASE_40G_CR4 [02:02] */ 23697 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_BASE_40G_CR4_MASK 0x0004 23698 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_BASE_40G_CR4_ALIGN 0 23699 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_BASE_40G_CR4_BITS 1 23700 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_BASE_40G_CR4_SHIFT 2 23701 23702 /* AN_X4_ABILITIES :: ld_base_abilities_1 :: BASE_40G_KR4 [01:01] */ 23703 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_BASE_40G_KR4_MASK 0x0002 23704 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_BASE_40G_KR4_ALIGN 0 23705 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_BASE_40G_KR4_BITS 1 23706 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_BASE_40G_KR4_SHIFT 1 23707 23708 /* AN_X4_ABILITIES :: ld_base_abilities_1 :: BASE_10G_KR1 [00:00] */ 23709 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_BASE_10G_KR1_MASK 0x0001 23710 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_BASE_10G_KR1_ALIGN 0 23711 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_BASE_10G_KR1_BITS 1 23712 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_1_BASE_10G_KR1_SHIFT 0 23713 23714 23715 /**************************************************************************** 23716 * AN_X4_ABILITIES :: ld_bam_abilities 23717 */ 23718 /* AN_X4_ABILITIES :: ld_bam_abilities :: reserved0 [15:09] */ 23719 #define AN_X4_ABILITIES_LD_BAM_ABILITIES_RESERVED0_MASK 0xfe00 23720 #define AN_X4_ABILITIES_LD_BAM_ABILITIES_RESERVED0_ALIGN 0 23721 #define AN_X4_ABILITIES_LD_BAM_ABILITIES_RESERVED0_BITS 7 23722 #define AN_X4_ABILITIES_LD_BAM_ABILITIES_RESERVED0_SHIFT 9 23723 23724 /* AN_X4_ABILITIES :: ld_bam_abilities :: cl73_bam_code [08:00] */ 23725 #define AN_X4_ABILITIES_LD_BAM_ABILITIES_CL73_BAM_CODE_MASK 0x01ff 23726 #define AN_X4_ABILITIES_LD_BAM_ABILITIES_CL73_BAM_CODE_ALIGN 0 23727 #define AN_X4_ABILITIES_LD_BAM_ABILITIES_CL73_BAM_CODE_BITS 9 23728 #define AN_X4_ABILITIES_LD_BAM_ABILITIES_CL73_BAM_CODE_SHIFT 0 23729 23730 23731 /**************************************************************************** 23732 * AN_X4_ABILITIES :: cl73_controls 23733 */ 23734 /* AN_X4_ABILITIES :: cl73_controls :: reserved0 [15:10] */ 23735 #define AN_X4_ABILITIES_CL73_CONTROLS_RESERVED0_MASK 0xfc00 23736 #define AN_X4_ABILITIES_CL73_CONTROLS_RESERVED0_ALIGN 0 23737 #define AN_X4_ABILITIES_CL73_CONTROLS_RESERVED0_BITS 6 23738 #define AN_X4_ABILITIES_CL73_CONTROLS_RESERVED0_SHIFT 10 23739 23740 /* AN_X4_ABILITIES :: cl73_controls :: an_fail_count_limit [09:06] */ 23741 #define AN_X4_ABILITIES_CL73_CONTROLS_AN_FAIL_COUNT_LIMIT_MASK 0x03c0 23742 #define AN_X4_ABILITIES_CL73_CONTROLS_AN_FAIL_COUNT_LIMIT_ALIGN 0 23743 #define AN_X4_ABILITIES_CL73_CONTROLS_AN_FAIL_COUNT_LIMIT_BITS 4 23744 #define AN_X4_ABILITIES_CL73_CONTROLS_AN_FAIL_COUNT_LIMIT_SHIFT 6 23745 23746 /* AN_X4_ABILITIES :: cl73_controls :: linkFailTimerQual_en [05:05] */ 23747 #define AN_X4_ABILITIES_CL73_CONTROLS_LINKFAILTIMERQUAL_EN_MASK 0x0020 23748 #define AN_X4_ABILITIES_CL73_CONTROLS_LINKFAILTIMERQUAL_EN_ALIGN 0 23749 #define AN_X4_ABILITIES_CL73_CONTROLS_LINKFAILTIMERQUAL_EN_BITS 1 23750 #define AN_X4_ABILITIES_CL73_CONTROLS_LINKFAILTIMERQUAL_EN_SHIFT 5 23751 23752 /* AN_X4_ABILITIES :: cl73_controls :: linkFailTimer_dis [04:04] */ 23753 #define AN_X4_ABILITIES_CL73_CONTROLS_LINKFAILTIMER_DIS_MASK 0x0010 23754 #define AN_X4_ABILITIES_CL73_CONTROLS_LINKFAILTIMER_DIS_ALIGN 0 23755 #define AN_X4_ABILITIES_CL73_CONTROLS_LINKFAILTIMER_DIS_BITS 1 23756 #define AN_X4_ABILITIES_CL73_CONTROLS_LINKFAILTIMER_DIS_SHIFT 4 23757 23758 /* AN_X4_ABILITIES :: cl73_controls :: an_good_check_trap [03:03] */ 23759 #define AN_X4_ABILITIES_CL73_CONTROLS_AN_GOOD_CHECK_TRAP_MASK 0x0008 23760 #define AN_X4_ABILITIES_CL73_CONTROLS_AN_GOOD_CHECK_TRAP_ALIGN 0 23761 #define AN_X4_ABILITIES_CL73_CONTROLS_AN_GOOD_CHECK_TRAP_BITS 1 23762 #define AN_X4_ABILITIES_CL73_CONTROLS_AN_GOOD_CHECK_TRAP_SHIFT 3 23763 23764 /* AN_X4_ABILITIES :: cl73_controls :: an_good_trap [02:02] */ 23765 #define AN_X4_ABILITIES_CL73_CONTROLS_AN_GOOD_TRAP_MASK 0x0004 23766 #define AN_X4_ABILITIES_CL73_CONTROLS_AN_GOOD_TRAP_ALIGN 0 23767 #define AN_X4_ABILITIES_CL73_CONTROLS_AN_GOOD_TRAP_BITS 1 23768 #define AN_X4_ABILITIES_CL73_CONTROLS_AN_GOOD_TRAP_SHIFT 2 23769 23770 /* AN_X4_ABILITIES :: cl73_controls :: reserved1 [01:00] */ 23771 #define AN_X4_ABILITIES_CL73_CONTROLS_RESERVED1_MASK 0x0003 23772 #define AN_X4_ABILITIES_CL73_CONTROLS_RESERVED1_ALIGN 0 23773 #define AN_X4_ABILITIES_CL73_CONTROLS_RESERVED1_BITS 2 23774 #define AN_X4_ABILITIES_CL73_CONTROLS_RESERVED1_SHIFT 0 23775 23776 23777 /**************************************************************************** 23778 * AN_X4_ABILITIES :: ld_base_abilities_2 23779 */ 23780 /* AN_X4_ABILITIES :: ld_base_abilities_2 :: reserved0 [15:12] */ 23781 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_2_RESERVED0_MASK 0xf000 23782 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_2_RESERVED0_ALIGN 0 23783 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_2_RESERVED0_BITS 4 23784 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_2_RESERVED0_SHIFT 12 23785 23786 /* AN_X4_ABILITIES :: ld_base_abilities_2 :: BASE_50G_KR_CR_SEL [11:07] */ 23787 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_2_BASE_50G_KR_CR_SEL_MASK 0x0f80 23788 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_2_BASE_50G_KR_CR_SEL_ALIGN 0 23789 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_2_BASE_50G_KR_CR_SEL_BITS 5 23790 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_2_BASE_50G_KR_CR_SEL_SHIFT 7 23791 23792 /* AN_X4_ABILITIES :: ld_base_abilities_2 :: BASE_50G_KR_CR_EN [06:06] */ 23793 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_2_BASE_50G_KR_CR_EN_MASK 0x0040 23794 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_2_BASE_50G_KR_CR_EN_ALIGN 0 23795 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_2_BASE_50G_KR_CR_EN_BITS 1 23796 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_2_BASE_50G_KR_CR_EN_SHIFT 6 23797 23798 /* AN_X4_ABILITIES :: ld_base_abilities_2 :: BASE_100G_KR2_CR2_SEL [05:01] */ 23799 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_2_BASE_100G_KR2_CR2_SEL_MASK 0x003e 23800 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_2_BASE_100G_KR2_CR2_SEL_ALIGN 0 23801 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_2_BASE_100G_KR2_CR2_SEL_BITS 5 23802 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_2_BASE_100G_KR2_CR2_SEL_SHIFT 1 23803 23804 /* AN_X4_ABILITIES :: ld_base_abilities_2 :: BASE_100G_KR2_CR2_EN [00:00] */ 23805 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_2_BASE_100G_KR2_CR2_EN_MASK 0x0001 23806 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_2_BASE_100G_KR2_CR2_EN_ALIGN 0 23807 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_2_BASE_100G_KR2_CR2_EN_BITS 1 23808 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_2_BASE_100G_KR2_CR2_EN_SHIFT 0 23809 23810 23811 /**************************************************************************** 23812 * AN_X4_ABILITIES :: ld_base_abilities_3 23813 */ 23814 /* AN_X4_ABILITIES :: ld_base_abilities_3 :: reserved0 [15:06] */ 23815 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_3_RESERVED0_MASK 0xffc0 23816 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_3_RESERVED0_ALIGN 0 23817 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_3_RESERVED0_BITS 10 23818 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_3_RESERVED0_SHIFT 6 23819 23820 /* AN_X4_ABILITIES :: ld_base_abilities_3 :: BASE_200G_KR4_CR4_SEL [05:01] */ 23821 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_3_BASE_200G_KR4_CR4_SEL_MASK 0x003e 23822 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_3_BASE_200G_KR4_CR4_SEL_ALIGN 0 23823 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_3_BASE_200G_KR4_CR4_SEL_BITS 5 23824 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_3_BASE_200G_KR4_CR4_SEL_SHIFT 1 23825 23826 /* AN_X4_ABILITIES :: ld_base_abilities_3 :: BASE_200G_KR4_CR4_EN [00:00] */ 23827 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_3_BASE_200G_KR4_CR4_EN_MASK 0x0001 23828 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_3_BASE_200G_KR4_CR4_EN_ALIGN 0 23829 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_3_BASE_200G_KR4_CR4_EN_BITS 1 23830 #define AN_X4_ABILITIES_LD_BASE_ABILITIES_3_BASE_200G_KR4_CR4_EN_SHIFT 0 23831 23832 23833 /**************************************************************************** 23834 * AN_X4_ABILITIES :: sw_an_base_page_0 23835 */ 23836 /* AN_X4_ABILITIES :: sw_an_base_page_0 :: sw_an_bp_0 [15:00] */ 23837 #define AN_X4_ABILITIES_SW_AN_BASE_PAGE_0_SW_AN_BP_0_MASK 0xffff 23838 #define AN_X4_ABILITIES_SW_AN_BASE_PAGE_0_SW_AN_BP_0_ALIGN 0 23839 #define AN_X4_ABILITIES_SW_AN_BASE_PAGE_0_SW_AN_BP_0_BITS 16 23840 #define AN_X4_ABILITIES_SW_AN_BASE_PAGE_0_SW_AN_BP_0_SHIFT 0 23841 23842 23843 /**************************************************************************** 23844 * AN_X4_ABILITIES :: sw_an_base_page_1 23845 */ 23846 /* AN_X4_ABILITIES :: sw_an_base_page_1 :: sw_an_bp_1 [15:00] */ 23847 #define AN_X4_ABILITIES_SW_AN_BASE_PAGE_1_SW_AN_BP_1_MASK 0xffff 23848 #define AN_X4_ABILITIES_SW_AN_BASE_PAGE_1_SW_AN_BP_1_ALIGN 0 23849 #define AN_X4_ABILITIES_SW_AN_BASE_PAGE_1_SW_AN_BP_1_BITS 16 23850 #define AN_X4_ABILITIES_SW_AN_BASE_PAGE_1_SW_AN_BP_1_SHIFT 0 23851 23852 23853 /**************************************************************************** 23854 * AN_X4_ABILITIES :: sw_an_base_page_2 23855 */ 23856 /* AN_X4_ABILITIES :: sw_an_base_page_2 :: sw_an_bp_2 [15:00] */ 23857 #define AN_X4_ABILITIES_SW_AN_BASE_PAGE_2_SW_AN_BP_2_MASK 0xffff 23858 #define AN_X4_ABILITIES_SW_AN_BASE_PAGE_2_SW_AN_BP_2_ALIGN 0 23859 #define AN_X4_ABILITIES_SW_AN_BASE_PAGE_2_SW_AN_BP_2_BITS 16 23860 #define AN_X4_ABILITIES_SW_AN_BASE_PAGE_2_SW_AN_BP_2_SHIFT 0 23861 23862 23863 /**************************************************************************** 23864 * TSC_TSC_USER4_AN_X4_STATUS 23865 */ 23866 /**************************************************************************** 23867 * AN_X4_STATUS :: r_cl73_status 23868 */ 23869 /* AN_X4_STATUS :: r_cl73_status :: reserved0 [15:12] */ 23870 #define AN_X4_STATUS_R_CL73_STATUS_RESERVED0_MASK 0xf000 23871 #define AN_X4_STATUS_R_CL73_STATUS_RESERVED0_ALIGN 0 23872 #define AN_X4_STATUS_R_CL73_STATUS_RESERVED0_BITS 4 23873 #define AN_X4_STATUS_R_CL73_STATUS_RESERVED0_SHIFT 12 23874 23875 /* AN_X4_STATUS :: r_cl73_status :: cl73_fifo_full [11:11] */ 23876 #define AN_X4_STATUS_R_CL73_STATUS_CL73_FIFO_FULL_MASK 0x0800 23877 #define AN_X4_STATUS_R_CL73_STATUS_CL73_FIFO_FULL_ALIGN 0 23878 #define AN_X4_STATUS_R_CL73_STATUS_CL73_FIFO_FULL_BITS 1 23879 #define AN_X4_STATUS_R_CL73_STATUS_CL73_FIFO_FULL_SHIFT 11 23880 23881 /* AN_X4_STATUS :: r_cl73_status :: dme_locked [10:10] */ 23882 #define AN_X4_STATUS_R_CL73_STATUS_DME_LOCKED_MASK 0x0400 23883 #define AN_X4_STATUS_R_CL73_STATUS_DME_LOCKED_ALIGN 0 23884 #define AN_X4_STATUS_R_CL73_STATUS_DME_LOCKED_BITS 1 23885 #define AN_X4_STATUS_R_CL73_STATUS_DME_LOCKED_SHIFT 10 23886 23887 /* AN_X4_STATUS :: r_cl73_status :: pulse_too_short [09:09] */ 23888 #define AN_X4_STATUS_R_CL73_STATUS_PULSE_TOO_SHORT_MASK 0x0200 23889 #define AN_X4_STATUS_R_CL73_STATUS_PULSE_TOO_SHORT_ALIGN 0 23890 #define AN_X4_STATUS_R_CL73_STATUS_PULSE_TOO_SHORT_BITS 1 23891 #define AN_X4_STATUS_R_CL73_STATUS_PULSE_TOO_SHORT_SHIFT 9 23892 23893 /* AN_X4_STATUS :: r_cl73_status :: pulse_too_moderate [08:08] */ 23894 #define AN_X4_STATUS_R_CL73_STATUS_PULSE_TOO_MODERATE_MASK 0x0100 23895 #define AN_X4_STATUS_R_CL73_STATUS_PULSE_TOO_MODERATE_ALIGN 0 23896 #define AN_X4_STATUS_R_CL73_STATUS_PULSE_TOO_MODERATE_BITS 1 23897 #define AN_X4_STATUS_R_CL73_STATUS_PULSE_TOO_MODERATE_SHIFT 8 23898 23899 /* AN_X4_STATUS :: r_cl73_status :: pulse_too_long [07:07] */ 23900 #define AN_X4_STATUS_R_CL73_STATUS_PULSE_TOO_LONG_MASK 0x0080 23901 #define AN_X4_STATUS_R_CL73_STATUS_PULSE_TOO_LONG_ALIGN 0 23902 #define AN_X4_STATUS_R_CL73_STATUS_PULSE_TOO_LONG_BITS 1 23903 #define AN_X4_STATUS_R_CL73_STATUS_PULSE_TOO_LONG_SHIFT 7 23904 23905 /* AN_X4_STATUS :: r_cl73_status :: page_too_short [06:06] */ 23906 #define AN_X4_STATUS_R_CL73_STATUS_PAGE_TOO_SHORT_MASK 0x0040 23907 #define AN_X4_STATUS_R_CL73_STATUS_PAGE_TOO_SHORT_ALIGN 0 23908 #define AN_X4_STATUS_R_CL73_STATUS_PAGE_TOO_SHORT_BITS 1 23909 #define AN_X4_STATUS_R_CL73_STATUS_PAGE_TOO_SHORT_SHIFT 6 23910 23911 /* AN_X4_STATUS :: r_cl73_status :: page_too_long [05:05] */ 23912 #define AN_X4_STATUS_R_CL73_STATUS_PAGE_TOO_LONG_MASK 0x0020 23913 #define AN_X4_STATUS_R_CL73_STATUS_PAGE_TOO_LONG_ALIGN 0 23914 #define AN_X4_STATUS_R_CL73_STATUS_PAGE_TOO_LONG_BITS 1 23915 #define AN_X4_STATUS_R_CL73_STATUS_PAGE_TOO_LONG_SHIFT 5 23916 23917 /* AN_X4_STATUS :: r_cl73_status :: clk_trans_miss [04:04] */ 23918 #define AN_X4_STATUS_R_CL73_STATUS_CLK_TRANS_MISS_MASK 0x0010 23919 #define AN_X4_STATUS_R_CL73_STATUS_CLK_TRANS_MISS_ALIGN 0 23920 #define AN_X4_STATUS_R_CL73_STATUS_CLK_TRANS_MISS_BITS 1 23921 #define AN_X4_STATUS_R_CL73_STATUS_CLK_TRANS_MISS_SHIFT 4 23922 23923 /* AN_X4_STATUS :: r_cl73_status :: dme_mv_pair [03:03] */ 23924 #define AN_X4_STATUS_R_CL73_STATUS_DME_MV_PAIR_MASK 0x0008 23925 #define AN_X4_STATUS_R_CL73_STATUS_DME_MV_PAIR_ALIGN 0 23926 #define AN_X4_STATUS_R_CL73_STATUS_DME_MV_PAIR_BITS 1 23927 #define AN_X4_STATUS_R_CL73_STATUS_DME_MV_PAIR_SHIFT 3 23928 23929 /* AN_X4_STATUS :: r_cl73_status :: dme_page [02:02] */ 23930 #define AN_X4_STATUS_R_CL73_STATUS_DME_PAGE_MASK 0x0004 23931 #define AN_X4_STATUS_R_CL73_STATUS_DME_PAGE_ALIGN 0 23932 #define AN_X4_STATUS_R_CL73_STATUS_DME_PAGE_BITS 1 23933 #define AN_X4_STATUS_R_CL73_STATUS_DME_PAGE_SHIFT 2 23934 23935 /* AN_X4_STATUS :: r_cl73_status :: dme_state [01:00] */ 23936 #define AN_X4_STATUS_R_CL73_STATUS_DME_STATE_MASK 0x0003 23937 #define AN_X4_STATUS_R_CL73_STATUS_DME_STATE_ALIGN 0 23938 #define AN_X4_STATUS_R_CL73_STATUS_DME_STATE_BITS 2 23939 #define AN_X4_STATUS_R_CL73_STATUS_DME_STATE_SHIFT 0 23940 23941 23942 /**************************************************************************** 23943 * AN_X4_STATUS :: pxng_status 23944 */ 23945 /* AN_X4_STATUS :: pxng_status :: reserved0 [15:09] */ 23946 #define AN_X4_STATUS_PXNG_STATUS_RESERVED0_MASK 0xfe00 23947 #define AN_X4_STATUS_PXNG_STATUS_RESERVED0_ALIGN 0 23948 #define AN_X4_STATUS_PXNG_STATUS_RESERVED0_BITS 7 23949 #define AN_X4_STATUS_PXNG_STATUS_RESERVED0_SHIFT 9 23950 23951 /* AN_X4_STATUS :: pxng_status :: an_good_check [08:08] */ 23952 #define AN_X4_STATUS_PXNG_STATUS_AN_GOOD_CHECK_MASK 0x0100 23953 #define AN_X4_STATUS_PXNG_STATUS_AN_GOOD_CHECK_ALIGN 0 23954 #define AN_X4_STATUS_PXNG_STATUS_AN_GOOD_CHECK_BITS 1 23955 #define AN_X4_STATUS_PXNG_STATUS_AN_GOOD_CHECK_SHIFT 8 23956 23957 /* AN_X4_STATUS :: pxng_status :: next_page_wait [07:07] */ 23958 #define AN_X4_STATUS_PXNG_STATUS_NEXT_PAGE_WAIT_MASK 0x0080 23959 #define AN_X4_STATUS_PXNG_STATUS_NEXT_PAGE_WAIT_ALIGN 0 23960 #define AN_X4_STATUS_PXNG_STATUS_NEXT_PAGE_WAIT_BITS 1 23961 #define AN_X4_STATUS_PXNG_STATUS_NEXT_PAGE_WAIT_SHIFT 7 23962 23963 /* AN_X4_STATUS :: pxng_status :: transmit_disable [06:06] */ 23964 #define AN_X4_STATUS_PXNG_STATUS_TRANSMIT_DISABLE_MASK 0x0040 23965 #define AN_X4_STATUS_PXNG_STATUS_TRANSMIT_DISABLE_ALIGN 0 23966 #define AN_X4_STATUS_PXNG_STATUS_TRANSMIT_DISABLE_BITS 1 23967 #define AN_X4_STATUS_PXNG_STATUS_TRANSMIT_DISABLE_SHIFT 6 23968 23969 /* AN_X4_STATUS :: pxng_status :: error_state [05:05] */ 23970 #define AN_X4_STATUS_PXNG_STATUS_ERROR_STATE_MASK 0x0020 23971 #define AN_X4_STATUS_PXNG_STATUS_ERROR_STATE_ALIGN 0 23972 #define AN_X4_STATUS_PXNG_STATUS_ERROR_STATE_BITS 1 23973 #define AN_X4_STATUS_PXNG_STATUS_ERROR_STATE_SHIFT 5 23974 23975 /* AN_X4_STATUS :: pxng_status :: an_enable [04:04] */ 23976 #define AN_X4_STATUS_PXNG_STATUS_AN_ENABLE_MASK 0x0010 23977 #define AN_X4_STATUS_PXNG_STATUS_AN_ENABLE_ALIGN 0 23978 #define AN_X4_STATUS_PXNG_STATUS_AN_ENABLE_BITS 1 23979 #define AN_X4_STATUS_PXNG_STATUS_AN_ENABLE_SHIFT 4 23980 23981 /* AN_X4_STATUS :: pxng_status :: ability_detect [03:03] */ 23982 #define AN_X4_STATUS_PXNG_STATUS_ABILITY_DETECT_MASK 0x0008 23983 #define AN_X4_STATUS_PXNG_STATUS_ABILITY_DETECT_ALIGN 0 23984 #define AN_X4_STATUS_PXNG_STATUS_ABILITY_DETECT_BITS 1 23985 #define AN_X4_STATUS_PXNG_STATUS_ABILITY_DETECT_SHIFT 3 23986 23987 /* AN_X4_STATUS :: pxng_status :: ack_detect [02:02] */ 23988 #define AN_X4_STATUS_PXNG_STATUS_ACK_DETECT_MASK 0x0004 23989 #define AN_X4_STATUS_PXNG_STATUS_ACK_DETECT_ALIGN 0 23990 #define AN_X4_STATUS_PXNG_STATUS_ACK_DETECT_BITS 1 23991 #define AN_X4_STATUS_PXNG_STATUS_ACK_DETECT_SHIFT 2 23992 23993 /* AN_X4_STATUS :: pxng_status :: complete_ack [01:01] */ 23994 #define AN_X4_STATUS_PXNG_STATUS_COMPLETE_ACK_MASK 0x0002 23995 #define AN_X4_STATUS_PXNG_STATUS_COMPLETE_ACK_ALIGN 0 23996 #define AN_X4_STATUS_PXNG_STATUS_COMPLETE_ACK_BITS 1 23997 #define AN_X4_STATUS_PXNG_STATUS_COMPLETE_ACK_SHIFT 1 23998 23999 /* AN_X4_STATUS :: pxng_status :: consistency_mismatch [00:00] */ 24000 #define AN_X4_STATUS_PXNG_STATUS_CONSISTENCY_MISMATCH_MASK 0x0001 24001 #define AN_X4_STATUS_PXNG_STATUS_CONSISTENCY_MISMATCH_ALIGN 0 24002 #define AN_X4_STATUS_PXNG_STATUS_CONSISTENCY_MISMATCH_BITS 1 24003 #define AN_X4_STATUS_PXNG_STATUS_CONSISTENCY_MISMATCH_SHIFT 0 24004 24005 24006 /**************************************************************************** 24007 * AN_X4_STATUS :: pseq_status 24008 */ 24009 /* AN_X4_STATUS :: pseq_status :: reserved0 [15:11] */ 24010 #define AN_X4_STATUS_PSEQ_STATUS_RESERVED0_MASK 0xf800 24011 #define AN_X4_STATUS_PSEQ_STATUS_RESERVED0_ALIGN 0 24012 #define AN_X4_STATUS_PSEQ_STATUS_RESERVED0_BITS 5 24013 #define AN_X4_STATUS_PSEQ_STATUS_RESERVED0_SHIFT 11 24014 24015 /* AN_X4_STATUS :: pseq_status :: cl73_an_complete [10:10] */ 24016 #define AN_X4_STATUS_PSEQ_STATUS_CL73_AN_COMPLETE_MASK 0x0400 24017 #define AN_X4_STATUS_PSEQ_STATUS_CL73_AN_COMPLETE_ALIGN 0 24018 #define AN_X4_STATUS_PSEQ_STATUS_CL73_AN_COMPLETE_BITS 1 24019 #define AN_X4_STATUS_PSEQ_STATUS_CL73_AN_COMPLETE_SHIFT 10 24020 24021 /* AN_X4_STATUS :: pseq_status :: rx_np_toggle_err [09:09] */ 24022 #define AN_X4_STATUS_PSEQ_STATUS_RX_NP_TOGGLE_ERR_MASK 0x0200 24023 #define AN_X4_STATUS_PSEQ_STATUS_RX_NP_TOGGLE_ERR_ALIGN 0 24024 #define AN_X4_STATUS_PSEQ_STATUS_RX_NP_TOGGLE_ERR_BITS 1 24025 #define AN_X4_STATUS_PSEQ_STATUS_RX_NP_TOGGLE_ERR_SHIFT 9 24026 24027 /* AN_X4_STATUS :: pseq_status :: rx_invalid_seq [08:08] */ 24028 #define AN_X4_STATUS_PSEQ_STATUS_RX_INVALID_SEQ_MASK 0x0100 24029 #define AN_X4_STATUS_PSEQ_STATUS_RX_INVALID_SEQ_ALIGN 0 24030 #define AN_X4_STATUS_PSEQ_STATUS_RX_INVALID_SEQ_BITS 1 24031 #define AN_X4_STATUS_PSEQ_STATUS_RX_INVALID_SEQ_SHIFT 8 24032 24033 /* AN_X4_STATUS :: pseq_status :: rx_up_oui_match [07:07] */ 24034 #define AN_X4_STATUS_PSEQ_STATUS_RX_UP_OUI_MATCH_MASK 0x0080 24035 #define AN_X4_STATUS_PSEQ_STATUS_RX_UP_OUI_MATCH_ALIGN 0 24036 #define AN_X4_STATUS_PSEQ_STATUS_RX_UP_OUI_MATCH_BITS 1 24037 #define AN_X4_STATUS_PSEQ_STATUS_RX_UP_OUI_MATCH_SHIFT 7 24038 24039 /* AN_X4_STATUS :: pseq_status :: rx_up_oui_mismatch [06:06] */ 24040 #define AN_X4_STATUS_PSEQ_STATUS_RX_UP_OUI_MISMATCH_MASK 0x0040 24041 #define AN_X4_STATUS_PSEQ_STATUS_RX_UP_OUI_MISMATCH_ALIGN 0 24042 #define AN_X4_STATUS_PSEQ_STATUS_RX_UP_OUI_MISMATCH_BITS 1 24043 #define AN_X4_STATUS_PSEQ_STATUS_RX_UP_OUI_MISMATCH_SHIFT 6 24044 24045 /* AN_X4_STATUS :: pseq_status :: rx_mp_mismatch [05:05] */ 24046 #define AN_X4_STATUS_PSEQ_STATUS_RX_MP_MISMATCH_MASK 0x0020 24047 #define AN_X4_STATUS_PSEQ_STATUS_RX_MP_MISMATCH_ALIGN 0 24048 #define AN_X4_STATUS_PSEQ_STATUS_RX_MP_MISMATCH_BITS 1 24049 #define AN_X4_STATUS_PSEQ_STATUS_RX_MP_MISMATCH_SHIFT 5 24050 24051 /* AN_X4_STATUS :: pseq_status :: rx_mp_oui [04:04] */ 24052 #define AN_X4_STATUS_PSEQ_STATUS_RX_MP_OUI_MASK 0x0010 24053 #define AN_X4_STATUS_PSEQ_STATUS_RX_MP_OUI_ALIGN 0 24054 #define AN_X4_STATUS_PSEQ_STATUS_RX_MP_OUI_BITS 1 24055 #define AN_X4_STATUS_PSEQ_STATUS_RX_MP_OUI_SHIFT 4 24056 24057 /* AN_X4_STATUS :: pseq_status :: rx_mp_null [03:03] */ 24058 #define AN_X4_STATUS_PSEQ_STATUS_RX_MP_NULL_MASK 0x0008 24059 #define AN_X4_STATUS_PSEQ_STATUS_RX_MP_NULL_ALIGN 0 24060 #define AN_X4_STATUS_PSEQ_STATUS_RX_MP_NULL_BITS 1 24061 #define AN_X4_STATUS_PSEQ_STATUS_RX_MP_NULL_SHIFT 3 24062 24063 /* AN_X4_STATUS :: pseq_status :: rx_np [02:02] */ 24064 #define AN_X4_STATUS_PSEQ_STATUS_RX_NP_MASK 0x0004 24065 #define AN_X4_STATUS_PSEQ_STATUS_RX_NP_ALIGN 0 24066 #define AN_X4_STATUS_PSEQ_STATUS_RX_NP_BITS 1 24067 #define AN_X4_STATUS_PSEQ_STATUS_RX_NP_SHIFT 2 24068 24069 /* AN_X4_STATUS :: pseq_status :: rx_bp [01:01] */ 24070 #define AN_X4_STATUS_PSEQ_STATUS_RX_BP_MASK 0x0002 24071 #define AN_X4_STATUS_PSEQ_STATUS_RX_BP_ALIGN 0 24072 #define AN_X4_STATUS_PSEQ_STATUS_RX_BP_BITS 1 24073 #define AN_X4_STATUS_PSEQ_STATUS_RX_BP_SHIFT 1 24074 24075 /* AN_X4_STATUS :: pseq_status :: hp_mode [00:00] */ 24076 #define AN_X4_STATUS_PSEQ_STATUS_HP_MODE_MASK 0x0001 24077 #define AN_X4_STATUS_PSEQ_STATUS_HP_MODE_ALIGN 0 24078 #define AN_X4_STATUS_PSEQ_STATUS_HP_MODE_BITS 1 24079 #define AN_X4_STATUS_PSEQ_STATUS_HP_MODE_SHIFT 0 24080 24081 24082 /**************************************************************************** 24083 * AN_X4_STATUS :: lp_base1 24084 */ 24085 /* AN_X4_STATUS :: lp_base1 :: lp_base1 [15:00] */ 24086 #define AN_X4_STATUS_LP_BASE1_LP_BASE1_MASK 0xffff 24087 #define AN_X4_STATUS_LP_BASE1_LP_BASE1_ALIGN 0 24088 #define AN_X4_STATUS_LP_BASE1_LP_BASE1_BITS 16 24089 #define AN_X4_STATUS_LP_BASE1_LP_BASE1_SHIFT 0 24090 24091 24092 /**************************************************************************** 24093 * AN_X4_STATUS :: lp_base2 24094 */ 24095 /* AN_X4_STATUS :: lp_base2 :: lp_base2 [15:00] */ 24096 #define AN_X4_STATUS_LP_BASE2_LP_BASE2_MASK 0xffff 24097 #define AN_X4_STATUS_LP_BASE2_LP_BASE2_ALIGN 0 24098 #define AN_X4_STATUS_LP_BASE2_LP_BASE2_BITS 16 24099 #define AN_X4_STATUS_LP_BASE2_LP_BASE2_SHIFT 0 24100 24101 24102 /**************************************************************************** 24103 * AN_X4_STATUS :: lp_base3 24104 */ 24105 /* AN_X4_STATUS :: lp_base3 :: lp_base3 [15:00] */ 24106 #define AN_X4_STATUS_LP_BASE3_LP_BASE3_MASK 0xffff 24107 #define AN_X4_STATUS_LP_BASE3_LP_BASE3_ALIGN 0 24108 #define AN_X4_STATUS_LP_BASE3_LP_BASE3_BITS 16 24109 #define AN_X4_STATUS_LP_BASE3_LP_BASE3_SHIFT 0 24110 24111 24112 /**************************************************************************** 24113 * AN_X4_STATUS :: lp_MP5_lower 24114 */ 24115 /* AN_X4_STATUS :: lp_MP5_lower :: MP5_15_0 [15:00] */ 24116 #define AN_X4_STATUS_LP_MP5_LOWER_MP5_15_0_MASK 0xffff 24117 #define AN_X4_STATUS_LP_MP5_LOWER_MP5_15_0_ALIGN 0 24118 #define AN_X4_STATUS_LP_MP5_LOWER_MP5_15_0_BITS 16 24119 #define AN_X4_STATUS_LP_MP5_LOWER_MP5_15_0_SHIFT 0 24120 24121 24122 /**************************************************************************** 24123 * AN_X4_STATUS :: lp_MP5_middle 24124 */ 24125 /* AN_X4_STATUS :: lp_MP5_middle :: MP5_31_16 [15:00] */ 24126 #define AN_X4_STATUS_LP_MP5_MIDDLE_MP5_31_16_MASK 0xffff 24127 #define AN_X4_STATUS_LP_MP5_MIDDLE_MP5_31_16_ALIGN 0 24128 #define AN_X4_STATUS_LP_MP5_MIDDLE_MP5_31_16_BITS 16 24129 #define AN_X4_STATUS_LP_MP5_MIDDLE_MP5_31_16_SHIFT 0 24130 24131 24132 /**************************************************************************** 24133 * AN_X4_STATUS :: lp_MP5_upper 24134 */ 24135 /* AN_X4_STATUS :: lp_MP5_upper :: MP5_47_16 [15:00] */ 24136 #define AN_X4_STATUS_LP_MP5_UPPER_MP5_47_16_MASK 0xffff 24137 #define AN_X4_STATUS_LP_MP5_UPPER_MP5_47_16_ALIGN 0 24138 #define AN_X4_STATUS_LP_MP5_UPPER_MP5_47_16_BITS 16 24139 #define AN_X4_STATUS_LP_MP5_UPPER_MP5_47_16_SHIFT 0 24140 24141 24142 /**************************************************************************** 24143 * AN_X4_STATUS :: lp_UP_lower 24144 */ 24145 /* AN_X4_STATUS :: lp_UP_lower :: UP_15_0 [15:00] */ 24146 #define AN_X4_STATUS_LP_UP_LOWER_UP_15_0_MASK 0xffff 24147 #define AN_X4_STATUS_LP_UP_LOWER_UP_15_0_ALIGN 0 24148 #define AN_X4_STATUS_LP_UP_LOWER_UP_15_0_BITS 16 24149 #define AN_X4_STATUS_LP_UP_LOWER_UP_15_0_SHIFT 0 24150 24151 24152 /**************************************************************************** 24153 * AN_X4_STATUS :: lp_UP_middle 24154 */ 24155 /* AN_X4_STATUS :: lp_UP_middle :: UP_31_16 [15:00] */ 24156 #define AN_X4_STATUS_LP_UP_MIDDLE_UP_31_16_MASK 0xffff 24157 #define AN_X4_STATUS_LP_UP_MIDDLE_UP_31_16_ALIGN 0 24158 #define AN_X4_STATUS_LP_UP_MIDDLE_UP_31_16_BITS 16 24159 #define AN_X4_STATUS_LP_UP_MIDDLE_UP_31_16_SHIFT 0 24160 24161 24162 /**************************************************************************** 24163 * AN_X4_STATUS :: lp_UP_upper 24164 */ 24165 /* AN_X4_STATUS :: lp_UP_upper :: UP_47_32 [15:00] */ 24166 #define AN_X4_STATUS_LP_UP_UPPER_UP_47_32_MASK 0xffff 24167 #define AN_X4_STATUS_LP_UP_UPPER_UP_47_32_ALIGN 0 24168 #define AN_X4_STATUS_LP_UP_UPPER_UP_47_32_BITS 16 24169 #define AN_X4_STATUS_LP_UP_UPPER_UP_47_32_SHIFT 0 24170 24171 24172 /**************************************************************************** 24173 * AN_X4_STATUS :: res_err 24174 */ 24175 /* AN_X4_STATUS :: res_err :: reserved0 [15:01] */ 24176 #define AN_X4_STATUS_RES_ERR_RESERVED0_MASK 0xfffe 24177 #define AN_X4_STATUS_RES_ERR_RESERVED0_ALIGN 0 24178 #define AN_X4_STATUS_RES_ERR_RESERVED0_BITS 15 24179 #define AN_X4_STATUS_RES_ERR_RESERVED0_SHIFT 1 24180 24181 /* AN_X4_STATUS :: res_err :: resolution_error [00:00] */ 24182 #define AN_X4_STATUS_RES_ERR_RESOLUTION_ERROR_MASK 0x0001 24183 #define AN_X4_STATUS_RES_ERR_RESOLUTION_ERROR_ALIGN 0 24184 #define AN_X4_STATUS_RES_ERR_RESOLUTION_ERROR_BITS 1 24185 #define AN_X4_STATUS_RES_ERR_RESOLUTION_ERROR_SHIFT 0 24186 24187 24188 /**************************************************************************** 24189 * TSC_TSC_USER4_AN_X4_SW_MGMT 24190 */ 24191 /**************************************************************************** 24192 * AN_X4_SW_MGMT :: ld_page_2 24193 */ 24194 /* AN_X4_SW_MGMT :: ld_page_2 :: ld_page_2 [15:00] */ 24195 #define AN_X4_SW_MGMT_LD_PAGE_2_LD_PAGE_2_MASK 0xffff 24196 #define AN_X4_SW_MGMT_LD_PAGE_2_LD_PAGE_2_ALIGN 0 24197 #define AN_X4_SW_MGMT_LD_PAGE_2_LD_PAGE_2_BITS 16 24198 #define AN_X4_SW_MGMT_LD_PAGE_2_LD_PAGE_2_SHIFT 0 24199 24200 24201 /**************************************************************************** 24202 * AN_X4_SW_MGMT :: ld_page_1 24203 */ 24204 /* AN_X4_SW_MGMT :: ld_page_1 :: ld_page_1 [15:00] */ 24205 #define AN_X4_SW_MGMT_LD_PAGE_1_LD_PAGE_1_MASK 0xffff 24206 #define AN_X4_SW_MGMT_LD_PAGE_1_LD_PAGE_1_ALIGN 0 24207 #define AN_X4_SW_MGMT_LD_PAGE_1_LD_PAGE_1_BITS 16 24208 #define AN_X4_SW_MGMT_LD_PAGE_1_LD_PAGE_1_SHIFT 0 24209 24210 24211 /**************************************************************************** 24212 * AN_X4_SW_MGMT :: ld_page_0 24213 */ 24214 /* AN_X4_SW_MGMT :: ld_page_0 :: ld_page_0 [15:00] */ 24215 #define AN_X4_SW_MGMT_LD_PAGE_0_LD_PAGE_0_MASK 0xffff 24216 #define AN_X4_SW_MGMT_LD_PAGE_0_LD_PAGE_0_ALIGN 0 24217 #define AN_X4_SW_MGMT_LD_PAGE_0_LD_PAGE_0_BITS 16 24218 #define AN_X4_SW_MGMT_LD_PAGE_0_LD_PAGE_0_SHIFT 0 24219 24220 24221 /**************************************************************************** 24222 * AN_X4_SW_MGMT :: lp_page_2 24223 */ 24224 /* AN_X4_SW_MGMT :: lp_page_2 :: lp_page_2 [15:00] */ 24225 #define AN_X4_SW_MGMT_LP_PAGE_2_LP_PAGE_2_MASK 0xffff 24226 #define AN_X4_SW_MGMT_LP_PAGE_2_LP_PAGE_2_ALIGN 0 24227 #define AN_X4_SW_MGMT_LP_PAGE_2_LP_PAGE_2_BITS 16 24228 #define AN_X4_SW_MGMT_LP_PAGE_2_LP_PAGE_2_SHIFT 0 24229 24230 24231 /**************************************************************************** 24232 * AN_X4_SW_MGMT :: lp_page_1 24233 */ 24234 /* AN_X4_SW_MGMT :: lp_page_1 :: lp_page_1 [15:00] */ 24235 #define AN_X4_SW_MGMT_LP_PAGE_1_LP_PAGE_1_MASK 0xffff 24236 #define AN_X4_SW_MGMT_LP_PAGE_1_LP_PAGE_1_ALIGN 0 24237 #define AN_X4_SW_MGMT_LP_PAGE_1_LP_PAGE_1_BITS 16 24238 #define AN_X4_SW_MGMT_LP_PAGE_1_LP_PAGE_1_SHIFT 0 24239 24240 24241 /**************************************************************************** 24242 * AN_X4_SW_MGMT :: lp_page_0 24243 */ 24244 /* AN_X4_SW_MGMT :: lp_page_0 :: lp_page_0 [15:00] */ 24245 #define AN_X4_SW_MGMT_LP_PAGE_0_LP_PAGE_0_MASK 0xffff 24246 #define AN_X4_SW_MGMT_LP_PAGE_0_LP_PAGE_0_ALIGN 0 24247 #define AN_X4_SW_MGMT_LP_PAGE_0_LP_PAGE_0_BITS 16 24248 #define AN_X4_SW_MGMT_LP_PAGE_0_LP_PAGE_0_SHIFT 0 24249 24250 24251 /**************************************************************************** 24252 * AN_X4_SW_MGMT :: sw_control_status 24253 */ 24254 /* AN_X4_SW_MGMT :: sw_control_status :: an_completed [15:15] */ 24255 #define AN_X4_SW_MGMT_SW_CONTROL_STATUS_AN_COMPLETED_MASK 0x8000 24256 #define AN_X4_SW_MGMT_SW_CONTROL_STATUS_AN_COMPLETED_ALIGN 0 24257 #define AN_X4_SW_MGMT_SW_CONTROL_STATUS_AN_COMPLETED_BITS 1 24258 #define AN_X4_SW_MGMT_SW_CONTROL_STATUS_AN_COMPLETED_SHIFT 15 24259 24260 /* AN_X4_SW_MGMT :: sw_control_status :: ld_control_valid [14:14] */ 24261 #define AN_X4_SW_MGMT_SW_CONTROL_STATUS_LD_CONTROL_VALID_MASK 0x4000 24262 #define AN_X4_SW_MGMT_SW_CONTROL_STATUS_LD_CONTROL_VALID_ALIGN 0 24263 #define AN_X4_SW_MGMT_SW_CONTROL_STATUS_LD_CONTROL_VALID_BITS 1 24264 #define AN_X4_SW_MGMT_SW_CONTROL_STATUS_LD_CONTROL_VALID_SHIFT 14 24265 24266 /* AN_X4_SW_MGMT :: sw_control_status :: reserved0 [13:13] */ 24267 #define AN_X4_SW_MGMT_SW_CONTROL_STATUS_RESERVED0_MASK 0x2000 24268 #define AN_X4_SW_MGMT_SW_CONTROL_STATUS_RESERVED0_ALIGN 0 24269 #define AN_X4_SW_MGMT_SW_CONTROL_STATUS_RESERVED0_BITS 1 24270 #define AN_X4_SW_MGMT_SW_CONTROL_STATUS_RESERVED0_SHIFT 13 24271 24272 /* AN_X4_SW_MGMT :: sw_control_status :: lp_page_rdy [12:12] */ 24273 #define AN_X4_SW_MGMT_SW_CONTROL_STATUS_LP_PAGE_RDY_MASK 0x1000 24274 #define AN_X4_SW_MGMT_SW_CONTROL_STATUS_LP_PAGE_RDY_ALIGN 0 24275 #define AN_X4_SW_MGMT_SW_CONTROL_STATUS_LP_PAGE_RDY_BITS 1 24276 #define AN_X4_SW_MGMT_SW_CONTROL_STATUS_LP_PAGE_RDY_SHIFT 12 24277 24278 /* AN_X4_SW_MGMT :: sw_control_status :: ld_seq_restart [11:11] */ 24279 #define AN_X4_SW_MGMT_SW_CONTROL_STATUS_LD_SEQ_RESTART_MASK 0x0800 24280 #define AN_X4_SW_MGMT_SW_CONTROL_STATUS_LD_SEQ_RESTART_ALIGN 0 24281 #define AN_X4_SW_MGMT_SW_CONTROL_STATUS_LD_SEQ_RESTART_BITS 1 24282 #define AN_X4_SW_MGMT_SW_CONTROL_STATUS_LD_SEQ_RESTART_SHIFT 11 24283 24284 /* AN_X4_SW_MGMT :: sw_control_status :: reserved1 [10:08] */ 24285 #define AN_X4_SW_MGMT_SW_CONTROL_STATUS_RESERVED1_MASK 0x0700 24286 #define AN_X4_SW_MGMT_SW_CONTROL_STATUS_RESERVED1_ALIGN 0 24287 #define AN_X4_SW_MGMT_SW_CONTROL_STATUS_RESERVED1_BITS 3 24288 #define AN_X4_SW_MGMT_SW_CONTROL_STATUS_RESERVED1_SHIFT 8 24289 24290 /* AN_X4_SW_MGMT :: sw_control_status :: tla_ln_sequencer_fsm_status1 [07:00] */ 24291 #define AN_X4_SW_MGMT_SW_CONTROL_STATUS_TLA_LN_SEQUENCER_FSM_STATUS1_MASK 0x00ff 24292 #define AN_X4_SW_MGMT_SW_CONTROL_STATUS_TLA_LN_SEQUENCER_FSM_STATUS1_ALIGN 0 24293 #define AN_X4_SW_MGMT_SW_CONTROL_STATUS_TLA_LN_SEQUENCER_FSM_STATUS1_BITS 8 24294 #define AN_X4_SW_MGMT_SW_CONTROL_STATUS_TLA_LN_SEQUENCER_FSM_STATUS1_SHIFT 0 24295 24296 24297 /**************************************************************************** 24298 * AN_X4_SW_MGMT :: ld_control 24299 */ 24300 /* AN_X4_SW_MGMT :: ld_control :: reserved0 [15:02] */ 24301 #define AN_X4_SW_MGMT_LD_CONTROL_RESERVED0_MASK 0xfffc 24302 #define AN_X4_SW_MGMT_LD_CONTROL_RESERVED0_ALIGN 0 24303 #define AN_X4_SW_MGMT_LD_CONTROL_RESERVED0_BITS 14 24304 #define AN_X4_SW_MGMT_LD_CONTROL_RESERVED0_SHIFT 2 24305 24306 /* AN_X4_SW_MGMT :: ld_control :: an_type_sw [01:01] */ 24307 #define AN_X4_SW_MGMT_LD_CONTROL_AN_TYPE_SW_MASK 0x0002 24308 #define AN_X4_SW_MGMT_LD_CONTROL_AN_TYPE_SW_ALIGN 0 24309 #define AN_X4_SW_MGMT_LD_CONTROL_AN_TYPE_SW_BITS 1 24310 #define AN_X4_SW_MGMT_LD_CONTROL_AN_TYPE_SW_SHIFT 1 24311 24312 /* AN_X4_SW_MGMT :: ld_control :: an_hcd_res_disable [00:00] */ 24313 #define AN_X4_SW_MGMT_LD_CONTROL_AN_HCD_RES_DISABLE_MASK 0x0001 24314 #define AN_X4_SW_MGMT_LD_CONTROL_AN_HCD_RES_DISABLE_ALIGN 0 24315 #define AN_X4_SW_MGMT_LD_CONTROL_AN_HCD_RES_DISABLE_BITS 1 24316 #define AN_X4_SW_MGMT_LD_CONTROL_AN_HCD_RES_DISABLE_SHIFT 0 24317 24318 24319 /**************************************************************************** 24320 * AN_X4_SW_MGMT :: an_ability_resolution_status 24321 */ 24322 /* AN_X4_SW_MGMT :: an_ability_resolution_status :: reserved0 [15:15] */ 24323 #define AN_X4_SW_MGMT_AN_ABILITY_RESOLUTION_STATUS_RESERVED0_MASK 0x8000 24324 #define AN_X4_SW_MGMT_AN_ABILITY_RESOLUTION_STATUS_RESERVED0_ALIGN 0 24325 #define AN_X4_SW_MGMT_AN_ABILITY_RESOLUTION_STATUS_RESERVED0_BITS 1 24326 #define AN_X4_SW_MGMT_AN_ABILITY_RESOLUTION_STATUS_RESERVED0_SHIFT 15 24327 24328 /* AN_X4_SW_MGMT :: an_ability_resolution_status :: an_hcd_duplex [14:14] */ 24329 #define AN_X4_SW_MGMT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_DUPLEX_MASK 0x4000 24330 #define AN_X4_SW_MGMT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_DUPLEX_ALIGN 0 24331 #define AN_X4_SW_MGMT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_DUPLEX_BITS 1 24332 #define AN_X4_SW_MGMT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_DUPLEX_SHIFT 14 24333 24334 /* AN_X4_SW_MGMT :: an_ability_resolution_status :: an_hcd_pause [13:12] */ 24335 #define AN_X4_SW_MGMT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_PAUSE_MASK 0x3000 24336 #define AN_X4_SW_MGMT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_PAUSE_ALIGN 0 24337 #define AN_X4_SW_MGMT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_PAUSE_BITS 2 24338 #define AN_X4_SW_MGMT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_PAUSE_SHIFT 12 24339 24340 /* AN_X4_SW_MGMT :: an_ability_resolution_status :: an_hcd_speed [11:04] */ 24341 #define AN_X4_SW_MGMT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_MASK 0x0ff0 24342 #define AN_X4_SW_MGMT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_ALIGN 0 24343 #define AN_X4_SW_MGMT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_BITS 8 24344 #define AN_X4_SW_MGMT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_SPEED_SHIFT 4 24345 24346 /* AN_X4_SW_MGMT :: an_ability_resolution_status :: an_hcd_fec_arch [03:01] */ 24347 #define AN_X4_SW_MGMT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_FEC_ARCH_MASK 0x000e 24348 #define AN_X4_SW_MGMT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_FEC_ARCH_ALIGN 0 24349 #define AN_X4_SW_MGMT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_FEC_ARCH_BITS 3 24350 #define AN_X4_SW_MGMT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_FEC_ARCH_SHIFT 1 24351 24352 /* AN_X4_SW_MGMT :: an_ability_resolution_status :: an_hcd_cl72 [00:00] */ 24353 #define AN_X4_SW_MGMT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_CL72_MASK 0x0001 24354 #define AN_X4_SW_MGMT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_CL72_ALIGN 0 24355 #define AN_X4_SW_MGMT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_CL72_BITS 1 24356 #define AN_X4_SW_MGMT_AN_ABILITY_RESOLUTION_STATUS_AN_HCD_CL72_SHIFT 0 24357 24358 24359 /**************************************************************************** 24360 * AN_X4_SW_MGMT :: an_misc_status 24361 */ 24362 /* AN_X4_SW_MGMT :: an_misc_status :: an_complete [15:15] */ 24363 #define AN_X4_SW_MGMT_AN_MISC_STATUS_AN_COMPLETE_MASK 0x8000 24364 #define AN_X4_SW_MGMT_AN_MISC_STATUS_AN_COMPLETE_ALIGN 0 24365 #define AN_X4_SW_MGMT_AN_MISC_STATUS_AN_COMPLETE_BITS 1 24366 #define AN_X4_SW_MGMT_AN_MISC_STATUS_AN_COMPLETE_SHIFT 15 24367 24368 /* AN_X4_SW_MGMT :: an_misc_status :: an_retry_count [14:09] */ 24369 #define AN_X4_SW_MGMT_AN_MISC_STATUS_AN_RETRY_COUNT_MASK 0x7e00 24370 #define AN_X4_SW_MGMT_AN_MISC_STATUS_AN_RETRY_COUNT_ALIGN 0 24371 #define AN_X4_SW_MGMT_AN_MISC_STATUS_AN_RETRY_COUNT_BITS 6 24372 #define AN_X4_SW_MGMT_AN_MISC_STATUS_AN_RETRY_COUNT_SHIFT 9 24373 24374 /* AN_X4_SW_MGMT :: an_misc_status :: reserved0 [08:07] */ 24375 #define AN_X4_SW_MGMT_AN_MISC_STATUS_RESERVED0_MASK 0x0180 24376 #define AN_X4_SW_MGMT_AN_MISC_STATUS_RESERVED0_ALIGN 0 24377 #define AN_X4_SW_MGMT_AN_MISC_STATUS_RESERVED0_BITS 2 24378 #define AN_X4_SW_MGMT_AN_MISC_STATUS_RESERVED0_SHIFT 7 24379 24380 /* AN_X4_SW_MGMT :: an_misc_status :: an_active [06:06] */ 24381 #define AN_X4_SW_MGMT_AN_MISC_STATUS_AN_ACTIVE_MASK 0x0040 24382 #define AN_X4_SW_MGMT_AN_MISC_STATUS_AN_ACTIVE_ALIGN 0 24383 #define AN_X4_SW_MGMT_AN_MISC_STATUS_AN_ACTIVE_BITS 1 24384 #define AN_X4_SW_MGMT_AN_MISC_STATUS_AN_ACTIVE_SHIFT 6 24385 24386 /* AN_X4_SW_MGMT :: an_misc_status :: an_fail_count [05:02] */ 24387 #define AN_X4_SW_MGMT_AN_MISC_STATUS_AN_FAIL_COUNT_MASK 0x003c 24388 #define AN_X4_SW_MGMT_AN_MISC_STATUS_AN_FAIL_COUNT_ALIGN 0 24389 #define AN_X4_SW_MGMT_AN_MISC_STATUS_AN_FAIL_COUNT_BITS 4 24390 #define AN_X4_SW_MGMT_AN_MISC_STATUS_AN_FAIL_COUNT_SHIFT 2 24391 24392 /* AN_X4_SW_MGMT :: an_misc_status :: reserved1 [01:00] */ 24393 #define AN_X4_SW_MGMT_AN_MISC_STATUS_RESERVED1_MASK 0x0003 24394 #define AN_X4_SW_MGMT_AN_MISC_STATUS_RESERVED1_ALIGN 0 24395 #define AN_X4_SW_MGMT_AN_MISC_STATUS_RESERVED1_BITS 2 24396 #define AN_X4_SW_MGMT_AN_MISC_STATUS_RESERVED1_SHIFT 0 24397 24398 24399 /**************************************************************************** 24400 * AN_X4_SW_MGMT :: tla_sequencer_status 24401 */ 24402 /* AN_X4_SW_MGMT :: tla_sequencer_status :: tla_seq_fsm_status [15:00] */ 24403 #define AN_X4_SW_MGMT_TLA_SEQUENCER_STATUS_TLA_SEQ_FSM_STATUS_MASK 0xffff 24404 #define AN_X4_SW_MGMT_TLA_SEQUENCER_STATUS_TLA_SEQ_FSM_STATUS_ALIGN 0 24405 #define AN_X4_SW_MGMT_TLA_SEQUENCER_STATUS_TLA_SEQ_FSM_STATUS_BITS 16 24406 #define AN_X4_SW_MGMT_TLA_SEQUENCER_STATUS_TLA_SEQ_FSM_STATUS_SHIFT 0 24407 #define AN_X4_SW_MGMT_TLA_SEQUENCER_STATUS_TLA_SEQ_FSM_STATUS_INIT 1 24408 #define AN_X4_SW_MGMT_TLA_SEQUENCER_STATUS_TLA_SEQ_FSM_STATUS_SET_AN_SPEED 2 24409 #define AN_X4_SW_MGMT_TLA_SEQUENCER_STATUS_TLA_SEQ_FSM_STATUS_WAIT_AN_SPEED 4 24410 #define AN_X4_SW_MGMT_TLA_SEQUENCER_STATUS_TLA_SEQ_FSM_STATUS_WAIT_AN_DONE 8 24411 #define AN_X4_SW_MGMT_TLA_SEQUENCER_STATUS_TLA_SEQ_FSM_STATUS_SET_RS_SPEED 16 24412 #define AN_X4_SW_MGMT_TLA_SEQUENCER_STATUS_TLA_SEQ_FSM_STATUS_WAIT_RS_CL72EN 32 24413 #define AN_X4_SW_MGMT_TLA_SEQUENCER_STATUS_TLA_SEQ_FSM_STATUS_WAIT_RS_SPEED 64 24414 #define AN_X4_SW_MGMT_TLA_SEQUENCER_STATUS_TLA_SEQ_FSM_STATUS_AN_IGNORE_LINK 128 24415 #define AN_X4_SW_MGMT_TLA_SEQUENCER_STATUS_TLA_SEQ_FSM_STATUS_AN_GOOD_CHECK 256 24416 #define AN_X4_SW_MGMT_TLA_SEQUENCER_STATUS_TLA_SEQ_FSM_STATUS_AN_GOOD 512 24417 #define AN_X4_SW_MGMT_TLA_SEQUENCER_STATUS_TLA_SEQ_FSM_STATUS_AN_FAIL 1024 24418 #define AN_X4_SW_MGMT_TLA_SEQUENCER_STATUS_TLA_SEQ_FSM_STATUS_AN_DEAD 2048 24419 #define AN_X4_SW_MGMT_TLA_SEQUENCER_STATUS_TLA_SEQ_FSM_STATUS_SW_SPEED_CHANGE 32768 24420 24421 24422 /**************************************************************************** 24423 * AN_X4_SW_MGMT :: int 24424 */ 24425 /* AN_X4_SW_MGMT :: int :: reserved0 [15:03] */ 24426 #define AN_X4_SW_MGMT_INT_RESERVED0_MASK 0xfff8 24427 #define AN_X4_SW_MGMT_INT_RESERVED0_ALIGN 0 24428 #define AN_X4_SW_MGMT_INT_RESERVED0_BITS 13 24429 #define AN_X4_SW_MGMT_INT_RESERVED0_SHIFT 3 24430 24431 /* AN_X4_SW_MGMT :: int :: an_good_chk_int [02:02] */ 24432 #define AN_X4_SW_MGMT_INT_AN_GOOD_CHK_INT_MASK 0x0004 24433 #define AN_X4_SW_MGMT_INT_AN_GOOD_CHK_INT_ALIGN 0 24434 #define AN_X4_SW_MGMT_INT_AN_GOOD_CHK_INT_BITS 1 24435 #define AN_X4_SW_MGMT_INT_AN_GOOD_CHK_INT_SHIFT 2 24436 24437 /* AN_X4_SW_MGMT :: int :: an_completed_sw_int [01:01] */ 24438 #define AN_X4_SW_MGMT_INT_AN_COMPLETED_SW_INT_MASK 0x0002 24439 #define AN_X4_SW_MGMT_INT_AN_COMPLETED_SW_INT_ALIGN 0 24440 #define AN_X4_SW_MGMT_INT_AN_COMPLETED_SW_INT_BITS 1 24441 #define AN_X4_SW_MGMT_INT_AN_COMPLETED_SW_INT_SHIFT 1 24442 24443 /* AN_X4_SW_MGMT :: int :: lp_page_rdy_int [00:00] */ 24444 #define AN_X4_SW_MGMT_INT_LP_PAGE_RDY_INT_MASK 0x0001 24445 #define AN_X4_SW_MGMT_INT_LP_PAGE_RDY_INT_ALIGN 0 24446 #define AN_X4_SW_MGMT_INT_LP_PAGE_RDY_INT_BITS 1 24447 #define AN_X4_SW_MGMT_INT_LP_PAGE_RDY_INT_SHIFT 0 24448 24449 24450 /**************************************************************************** 24451 * AN_X4_SW_MGMT :: int_en 24452 */ 24453 /* AN_X4_SW_MGMT :: int_en :: reserved0 [15:03] */ 24454 #define AN_X4_SW_MGMT_INT_EN_RESERVED0_MASK 0xfff8 24455 #define AN_X4_SW_MGMT_INT_EN_RESERVED0_ALIGN 0 24456 #define AN_X4_SW_MGMT_INT_EN_RESERVED0_BITS 13 24457 #define AN_X4_SW_MGMT_INT_EN_RESERVED0_SHIFT 3 24458 24459 /* AN_X4_SW_MGMT :: int_en :: an_good_chk_en [02:02] */ 24460 #define AN_X4_SW_MGMT_INT_EN_AN_GOOD_CHK_EN_MASK 0x0004 24461 #define AN_X4_SW_MGMT_INT_EN_AN_GOOD_CHK_EN_ALIGN 0 24462 #define AN_X4_SW_MGMT_INT_EN_AN_GOOD_CHK_EN_BITS 1 24463 #define AN_X4_SW_MGMT_INT_EN_AN_GOOD_CHK_EN_SHIFT 2 24464 24465 /* AN_X4_SW_MGMT :: int_en :: an_completed_sw_en [01:01] */ 24466 #define AN_X4_SW_MGMT_INT_EN_AN_COMPLETED_SW_EN_MASK 0x0002 24467 #define AN_X4_SW_MGMT_INT_EN_AN_COMPLETED_SW_EN_ALIGN 0 24468 #define AN_X4_SW_MGMT_INT_EN_AN_COMPLETED_SW_EN_BITS 1 24469 #define AN_X4_SW_MGMT_INT_EN_AN_COMPLETED_SW_EN_SHIFT 1 24470 24471 /* AN_X4_SW_MGMT :: int_en :: lp_page_rdy_en [00:00] */ 24472 #define AN_X4_SW_MGMT_INT_EN_LP_PAGE_RDY_EN_MASK 0x0001 24473 #define AN_X4_SW_MGMT_INT_EN_LP_PAGE_RDY_EN_ALIGN 0 24474 #define AN_X4_SW_MGMT_INT_EN_LP_PAGE_RDY_EN_BITS 1 24475 #define AN_X4_SW_MGMT_INT_EN_LP_PAGE_RDY_EN_SHIFT 0 24476 24477 24478 /**************************************************************************** 24479 * AN_X4_SW_MGMT :: wait_ack_complete 24480 */ 24481 /* AN_X4_SW_MGMT :: wait_ack_complete :: reserved0 [15:02] */ 24482 #define AN_X4_SW_MGMT_WAIT_ACK_COMPLETE_RESERVED0_MASK 0xfffc 24483 #define AN_X4_SW_MGMT_WAIT_ACK_COMPLETE_RESERVED0_ALIGN 0 24484 #define AN_X4_SW_MGMT_WAIT_ACK_COMPLETE_RESERVED0_BITS 14 24485 #define AN_X4_SW_MGMT_WAIT_ACK_COMPLETE_RESERVED0_SHIFT 2 24486 24487 /* AN_X4_SW_MGMT :: wait_ack_complete :: send_ack [01:01] */ 24488 #define AN_X4_SW_MGMT_WAIT_ACK_COMPLETE_SEND_ACK_MASK 0x0002 24489 #define AN_X4_SW_MGMT_WAIT_ACK_COMPLETE_SEND_ACK_ALIGN 0 24490 #define AN_X4_SW_MGMT_WAIT_ACK_COMPLETE_SEND_ACK_BITS 1 24491 #define AN_X4_SW_MGMT_WAIT_ACK_COMPLETE_SEND_ACK_SHIFT 1 24492 24493 /* AN_X4_SW_MGMT :: wait_ack_complete :: wait_for_ack_en [00:00] */ 24494 #define AN_X4_SW_MGMT_WAIT_ACK_COMPLETE_WAIT_FOR_ACK_EN_MASK 0x0001 24495 #define AN_X4_SW_MGMT_WAIT_ACK_COMPLETE_WAIT_FOR_ACK_EN_ALIGN 0 24496 #define AN_X4_SW_MGMT_WAIT_ACK_COMPLETE_WAIT_FOR_ACK_EN_BITS 1 24497 #define AN_X4_SW_MGMT_WAIT_ACK_COMPLETE_WAIT_FOR_ACK_EN_SHIFT 0 24498 24499 24500 /**************************************************************************** 24501 * TSC_TSC_USER4_SYNCE_X4 24502 */ 24503 /**************************************************************************** 24504 * SYNCE_X4 :: integer_div 24505 */ 24506 /* SYNCE_X4 :: integer_div :: reserved0 [15:04] */ 24507 #define SYNCE_X4_INTEGER_DIV_RESERVED0_MASK 0xfff0 24508 #define SYNCE_X4_INTEGER_DIV_RESERVED0_ALIGN 0 24509 #define SYNCE_X4_INTEGER_DIV_RESERVED0_BITS 12 24510 #define SYNCE_X4_INTEGER_DIV_RESERVED0_SHIFT 4 24511 24512 /* SYNCE_X4 :: integer_div :: synce_mode_stage1 [03:02] */ 24513 #define SYNCE_X4_INTEGER_DIV_SYNCE_MODE_STAGE1_MASK 0x000c 24514 #define SYNCE_X4_INTEGER_DIV_SYNCE_MODE_STAGE1_ALIGN 0 24515 #define SYNCE_X4_INTEGER_DIV_SYNCE_MODE_STAGE1_BITS 2 24516 #define SYNCE_X4_INTEGER_DIV_SYNCE_MODE_STAGE1_SHIFT 2 24517 #define SYNCE_X4_INTEGER_DIV_SYNCE_MODE_STAGE1_SYNCE_NO_DIV 0 24518 #define SYNCE_X4_INTEGER_DIV_SYNCE_MODE_STAGE1_SYNCE_DIV_7 1 24519 #define SYNCE_X4_INTEGER_DIV_SYNCE_MODE_STAGE1_SYNCE_DIV_11 2 24520 24521 /* SYNCE_X4 :: integer_div :: synce_mode_stage0 [01:00] */ 24522 #define SYNCE_X4_INTEGER_DIV_SYNCE_MODE_STAGE0_MASK 0x0003 24523 #define SYNCE_X4_INTEGER_DIV_SYNCE_MODE_STAGE0_ALIGN 0 24524 #define SYNCE_X4_INTEGER_DIV_SYNCE_MODE_STAGE0_BITS 2 24525 #define SYNCE_X4_INTEGER_DIV_SYNCE_MODE_STAGE0_SHIFT 0 24526 #define SYNCE_X4_INTEGER_DIV_SYNCE_MODE_STAGE0_SYNCE_NO_DIV 0 24527 #define SYNCE_X4_INTEGER_DIV_SYNCE_MODE_STAGE0_SYNCE_DIV_GAP_CLK_4_OVER_5 1 24528 #define SYNCE_X4_INTEGER_DIV_SYNCE_MODE_STAGE0_SYNCE_DIV_SDM_FRAC_DIV 2 24529 24530 24531 /**************************************************************************** 24532 * SYNCE_X4 :: fractional_div 24533 */ 24534 /* SYNCE_X4 :: fractional_div :: syncE_fractional_divsor_cfg [15:00] */ 24535 #define SYNCE_X4_FRACTIONAL_DIV_SYNCE_FRACTIONAL_DIVSOR_CFG_MASK 0xffff 24536 #define SYNCE_X4_FRACTIONAL_DIV_SYNCE_FRACTIONAL_DIVSOR_CFG_ALIGN 0 24537 #define SYNCE_X4_FRACTIONAL_DIV_SYNCE_FRACTIONAL_DIVSOR_CFG_BITS 16 24538 #define SYNCE_X4_FRACTIONAL_DIV_SYNCE_FRACTIONAL_DIVSOR_CFG_SHIFT 0 24539 24540 24541 /**************************************************************************** 24542 * TSC_TSC_USER4_ilkn_x4_control0 24543 */ 24544 /**************************************************************************** 24545 * ilkn_x4_control0 :: ilkn_control0 24546 */ 24547 /* ilkn_x4_control0 :: ilkn_control0 :: credit_en [15:15] */ 24548 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_CREDIT_EN_MASK 0x8000 24549 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_CREDIT_EN_ALIGN 0 24550 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_CREDIT_EN_BITS 1 24551 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_CREDIT_EN_SHIFT 15 24552 24553 /* ilkn_x4_control0 :: ilkn_control0 :: reserved0 [14:10] */ 24554 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_RESERVED0_MASK 0x7c00 24555 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_RESERVED0_ALIGN 0 24556 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_RESERVED0_BITS 5 24557 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_RESERVED0_SHIFT 10 24558 24559 /* ilkn_x4_control0 :: ilkn_control0 :: soft_rst_rx [09:09] */ 24560 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_SOFT_RST_RX_MASK 0x0200 24561 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_SOFT_RST_RX_ALIGN 0 24562 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_SOFT_RST_RX_BITS 1 24563 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_SOFT_RST_RX_SHIFT 9 24564 24565 /* ilkn_x4_control0 :: ilkn_control0 :: soft_rst_tx [08:08] */ 24566 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_SOFT_RST_TX_MASK 0x0100 24567 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_SOFT_RST_TX_ALIGN 0 24568 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_SOFT_RST_TX_BITS 1 24569 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_SOFT_RST_TX_SHIFT 8 24570 24571 /* ilkn_x4_control0 :: ilkn_control0 :: reserved1 [07:05] */ 24572 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_RESERVED1_MASK 0x00e0 24573 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_RESERVED1_ALIGN 0 24574 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_RESERVED1_BITS 3 24575 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_RESERVED1_SHIFT 5 24576 24577 /* ilkn_x4_control0 :: ilkn_control0 :: ilkn_sel [04:04] */ 24578 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_ILKN_SEL_MASK 0x0010 24579 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_ILKN_SEL_ALIGN 0 24580 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_ILKN_SEL_BITS 1 24581 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_ILKN_SEL_SHIFT 4 24582 24583 /* ilkn_x4_control0 :: ilkn_control0 :: wm [03:00] */ 24584 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_WM_MASK 0x000f 24585 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_WM_ALIGN 0 24586 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_WM_BITS 4 24587 #define ILKN_X4_CONTROL0_ILKN_CONTROL0_WM_SHIFT 0 24588 24589 24590 /**************************************************************************** 24591 * TSC_TSC_USER4_ilkn_x4_status0 24592 */ 24593 /**************************************************************************** 24594 * ilkn_x4_status0 :: ilkn_status0 24595 */ 24596 /* ilkn_x4_status0 :: ilkn_status0 :: reserved0 [15:07] */ 24597 #define ILKN_X4_STATUS0_ILKN_STATUS0_RESERVED0_MASK 0xff80 24598 #define ILKN_X4_STATUS0_ILKN_STATUS0_RESERVED0_ALIGN 0 24599 #define ILKN_X4_STATUS0_ILKN_STATUS0_RESERVED0_BITS 9 24600 #define ILKN_X4_STATUS0_ILKN_STATUS0_RESERVED0_SHIFT 7 24601 24602 /* ilkn_x4_status0 :: ilkn_status0 :: txfifo_underrun [06:06] */ 24603 #define ILKN_X4_STATUS0_ILKN_STATUS0_TXFIFO_UNDERRUN_MASK 0x0040 24604 #define ILKN_X4_STATUS0_ILKN_STATUS0_TXFIFO_UNDERRUN_ALIGN 0 24605 #define ILKN_X4_STATUS0_ILKN_STATUS0_TXFIFO_UNDERRUN_BITS 1 24606 #define ILKN_X4_STATUS0_ILKN_STATUS0_TXFIFO_UNDERRUN_SHIFT 6 24607 24608 /* ilkn_x4_status0 :: ilkn_status0 :: txfifo_overrun [05:05] */ 24609 #define ILKN_X4_STATUS0_ILKN_STATUS0_TXFIFO_OVERRUN_MASK 0x0020 24610 #define ILKN_X4_STATUS0_ILKN_STATUS0_TXFIFO_OVERRUN_ALIGN 0 24611 #define ILKN_X4_STATUS0_ILKN_STATUS0_TXFIFO_OVERRUN_BITS 1 24612 #define ILKN_X4_STATUS0_ILKN_STATUS0_TXFIFO_OVERRUN_SHIFT 5 24613 24614 /* ilkn_x4_status0 :: ilkn_status0 :: txfifo_full [04:04] */ 24615 #define ILKN_X4_STATUS0_ILKN_STATUS0_TXFIFO_FULL_MASK 0x0010 24616 #define ILKN_X4_STATUS0_ILKN_STATUS0_TXFIFO_FULL_ALIGN 0 24617 #define ILKN_X4_STATUS0_ILKN_STATUS0_TXFIFO_FULL_BITS 1 24618 #define ILKN_X4_STATUS0_ILKN_STATUS0_TXFIFO_FULL_SHIFT 4 24619 24620 /* ilkn_x4_status0 :: ilkn_status0 :: txfifo_empty [03:03] */ 24621 #define ILKN_X4_STATUS0_ILKN_STATUS0_TXFIFO_EMPTY_MASK 0x0008 24622 #define ILKN_X4_STATUS0_ILKN_STATUS0_TXFIFO_EMPTY_ALIGN 0 24623 #define ILKN_X4_STATUS0_ILKN_STATUS0_TXFIFO_EMPTY_BITS 1 24624 #define ILKN_X4_STATUS0_ILKN_STATUS0_TXFIFO_EMPTY_SHIFT 3 24625 24626 /* ilkn_x4_status0 :: ilkn_status0 :: rxfifo_not_empty [02:02] */ 24627 #define ILKN_X4_STATUS0_ILKN_STATUS0_RXFIFO_NOT_EMPTY_MASK 0x0004 24628 #define ILKN_X4_STATUS0_ILKN_STATUS0_RXFIFO_NOT_EMPTY_ALIGN 0 24629 #define ILKN_X4_STATUS0_ILKN_STATUS0_RXFIFO_NOT_EMPTY_BITS 1 24630 #define ILKN_X4_STATUS0_ILKN_STATUS0_RXFIFO_NOT_EMPTY_SHIFT 2 24631 24632 /* ilkn_x4_status0 :: ilkn_status0 :: rxfifo_full [01:01] */ 24633 #define ILKN_X4_STATUS0_ILKN_STATUS0_RXFIFO_FULL_MASK 0x0002 24634 #define ILKN_X4_STATUS0_ILKN_STATUS0_RXFIFO_FULL_ALIGN 0 24635 #define ILKN_X4_STATUS0_ILKN_STATUS0_RXFIFO_FULL_BITS 1 24636 #define ILKN_X4_STATUS0_ILKN_STATUS0_RXFIFO_FULL_SHIFT 1 24637 24638 /* ilkn_x4_status0 :: ilkn_status0 :: rxfifo_empty [00:00] */ 24639 #define ILKN_X4_STATUS0_ILKN_STATUS0_RXFIFO_EMPTY_MASK 0x0001 24640 #define ILKN_X4_STATUS0_ILKN_STATUS0_RXFIFO_EMPTY_ALIGN 0 24641 #define ILKN_X4_STATUS0_ILKN_STATUS0_RXFIFO_EMPTY_BITS 1 24642 #define ILKN_X4_STATUS0_ILKN_STATUS0_RXFIFO_EMPTY_SHIFT 0 24643 24644 24645 /**************************************************************************** 24646 * TSC_TSC_USER4_RX_X4_RS_FEC_Status0 24647 */ 24648 /**************************************************************************** 24649 * RX_X4_RS_FEC_Status0 :: RS_FEC_rxp_status 24650 */ 24651 /* RX_X4_RS_FEC_Status0 :: RS_FEC_rxp_status :: reserved0 [15:09] */ 24652 #define RX_X4_RS_FEC_STATUS0_RS_FEC_RXP_STATUS_RESERVED0_MASK 0xfe00 24653 #define RX_X4_RS_FEC_STATUS0_RS_FEC_RXP_STATUS_RESERVED0_ALIGN 0 24654 #define RX_X4_RS_FEC_STATUS0_RS_FEC_RXP_STATUS_RESERVED0_BITS 7 24655 #define RX_X4_RS_FEC_STATUS0_RS_FEC_RXP_STATUS_RESERVED0_SHIFT 9 24656 24657 /* RX_X4_RS_FEC_Status0 :: RS_FEC_rxp_status :: hi_ser_LH [08:08] */ 24658 #define RX_X4_RS_FEC_STATUS0_RS_FEC_RXP_STATUS_HI_SER_LH_MASK 0x0100 24659 #define RX_X4_RS_FEC_STATUS0_RS_FEC_RXP_STATUS_HI_SER_LH_ALIGN 0 24660 #define RX_X4_RS_FEC_STATUS0_RS_FEC_RXP_STATUS_HI_SER_LH_BITS 1 24661 #define RX_X4_RS_FEC_STATUS0_RS_FEC_RXP_STATUS_HI_SER_LH_SHIFT 8 24662 24663 /* RX_X4_RS_FEC_Status0 :: RS_FEC_rxp_status :: hi_ser_LL [07:07] */ 24664 #define RX_X4_RS_FEC_STATUS0_RS_FEC_RXP_STATUS_HI_SER_LL_MASK 0x0080 24665 #define RX_X4_RS_FEC_STATUS0_RS_FEC_RXP_STATUS_HI_SER_LL_ALIGN 0 24666 #define RX_X4_RS_FEC_STATUS0_RS_FEC_RXP_STATUS_HI_SER_LL_BITS 1 24667 #define RX_X4_RS_FEC_STATUS0_RS_FEC_RXP_STATUS_HI_SER_LL_SHIFT 7 24668 24669 /* RX_X4_RS_FEC_Status0 :: RS_FEC_rxp_status :: hi_ser_live [06:06] */ 24670 #define RX_X4_RS_FEC_STATUS0_RS_FEC_RXP_STATUS_HI_SER_LIVE_MASK 0x0040 24671 #define RX_X4_RS_FEC_STATUS0_RS_FEC_RXP_STATUS_HI_SER_LIVE_ALIGN 0 24672 #define RX_X4_RS_FEC_STATUS0_RS_FEC_RXP_STATUS_HI_SER_LIVE_BITS 1 24673 #define RX_X4_RS_FEC_STATUS0_RS_FEC_RXP_STATUS_HI_SER_LIVE_SHIFT 6 24674 24675 /* RX_X4_RS_FEC_Status0 :: RS_FEC_rxp_status :: fec_align_status_LH [05:05] */ 24676 #define RX_X4_RS_FEC_STATUS0_RS_FEC_RXP_STATUS_FEC_ALIGN_STATUS_LH_MASK 0x0020 24677 #define RX_X4_RS_FEC_STATUS0_RS_FEC_RXP_STATUS_FEC_ALIGN_STATUS_LH_ALIGN 0 24678 #define RX_X4_RS_FEC_STATUS0_RS_FEC_RXP_STATUS_FEC_ALIGN_STATUS_LH_BITS 1 24679 #define RX_X4_RS_FEC_STATUS0_RS_FEC_RXP_STATUS_FEC_ALIGN_STATUS_LH_SHIFT 5 24680 24681 /* RX_X4_RS_FEC_Status0 :: RS_FEC_rxp_status :: fec_align_status_LL [04:04] */ 24682 #define RX_X4_RS_FEC_STATUS0_RS_FEC_RXP_STATUS_FEC_ALIGN_STATUS_LL_MASK 0x0010 24683 #define RX_X4_RS_FEC_STATUS0_RS_FEC_RXP_STATUS_FEC_ALIGN_STATUS_LL_ALIGN 0 24684 #define RX_X4_RS_FEC_STATUS0_RS_FEC_RXP_STATUS_FEC_ALIGN_STATUS_LL_BITS 1 24685 #define RX_X4_RS_FEC_STATUS0_RS_FEC_RXP_STATUS_FEC_ALIGN_STATUS_LL_SHIFT 4 24686 24687 /* RX_X4_RS_FEC_Status0 :: RS_FEC_rxp_status :: fec_align_status_live [03:03] */ 24688 #define RX_X4_RS_FEC_STATUS0_RS_FEC_RXP_STATUS_FEC_ALIGN_STATUS_LIVE_MASK 0x0008 24689 #define RX_X4_RS_FEC_STATUS0_RS_FEC_RXP_STATUS_FEC_ALIGN_STATUS_LIVE_ALIGN 0 24690 #define RX_X4_RS_FEC_STATUS0_RS_FEC_RXP_STATUS_FEC_ALIGN_STATUS_LIVE_BITS 1 24691 #define RX_X4_RS_FEC_STATUS0_RS_FEC_RXP_STATUS_FEC_ALIGN_STATUS_LIVE_SHIFT 3 24692 24693 /* RX_X4_RS_FEC_Status0 :: RS_FEC_rxp_status :: restart_lock_LH [02:02] */ 24694 #define RX_X4_RS_FEC_STATUS0_RS_FEC_RXP_STATUS_RESTART_LOCK_LH_MASK 0x0004 24695 #define RX_X4_RS_FEC_STATUS0_RS_FEC_RXP_STATUS_RESTART_LOCK_LH_ALIGN 0 24696 #define RX_X4_RS_FEC_STATUS0_RS_FEC_RXP_STATUS_RESTART_LOCK_LH_BITS 1 24697 #define RX_X4_RS_FEC_STATUS0_RS_FEC_RXP_STATUS_RESTART_LOCK_LH_SHIFT 2 24698 24699 /* RX_X4_RS_FEC_Status0 :: RS_FEC_rxp_status :: restart_lock_LL [01:01] */ 24700 #define RX_X4_RS_FEC_STATUS0_RS_FEC_RXP_STATUS_RESTART_LOCK_LL_MASK 0x0002 24701 #define RX_X4_RS_FEC_STATUS0_RS_FEC_RXP_STATUS_RESTART_LOCK_LL_ALIGN 0 24702 #define RX_X4_RS_FEC_STATUS0_RS_FEC_RXP_STATUS_RESTART_LOCK_LL_BITS 1 24703 #define RX_X4_RS_FEC_STATUS0_RS_FEC_RXP_STATUS_RESTART_LOCK_LL_SHIFT 1 24704 24705 /* RX_X4_RS_FEC_Status0 :: RS_FEC_rxp_status :: restart_lock_live [00:00] */ 24706 #define RX_X4_RS_FEC_STATUS0_RS_FEC_RXP_STATUS_RESTART_LOCK_LIVE_MASK 0x0001 24707 #define RX_X4_RS_FEC_STATUS0_RS_FEC_RXP_STATUS_RESTART_LOCK_LIVE_ALIGN 0 24708 #define RX_X4_RS_FEC_STATUS0_RS_FEC_RXP_STATUS_RESTART_LOCK_LIVE_BITS 1 24709 #define RX_X4_RS_FEC_STATUS0_RS_FEC_RXP_STATUS_RESTART_LOCK_LIVE_SHIFT 0 24710 24711 24712 /**************************************************************************** 24713 * RX_X4_RS_FEC_Status0 :: fec_corrected_counter_0 24714 */ 24715 /* RX_X4_RS_FEC_Status0 :: fec_corrected_counter_0 :: RS_FEC_fec_corr_cw_cntr_lower [15:00] */ 24716 #define RX_X4_RS_FEC_STATUS0_FEC_CORRECTED_COUNTER_0_RS_FEC_FEC_CORR_CW_CNTR_LOWER_MASK 0xffff 24717 #define RX_X4_RS_FEC_STATUS0_FEC_CORRECTED_COUNTER_0_RS_FEC_FEC_CORR_CW_CNTR_LOWER_ALIGN 0 24718 #define RX_X4_RS_FEC_STATUS0_FEC_CORRECTED_COUNTER_0_RS_FEC_FEC_CORR_CW_CNTR_LOWER_BITS 16 24719 #define RX_X4_RS_FEC_STATUS0_FEC_CORRECTED_COUNTER_0_RS_FEC_FEC_CORR_CW_CNTR_LOWER_SHIFT 0 24720 24721 24722 /**************************************************************************** 24723 * RX_X4_RS_FEC_Status0 :: fec_corrected_counter_1 24724 */ 24725 /* RX_X4_RS_FEC_Status0 :: fec_corrected_counter_1 :: RS_FEC_fec_corr_cw_cntr_upper [15:00] */ 24726 #define RX_X4_RS_FEC_STATUS0_FEC_CORRECTED_COUNTER_1_RS_FEC_FEC_CORR_CW_CNTR_UPPER_MASK 0xffff 24727 #define RX_X4_RS_FEC_STATUS0_FEC_CORRECTED_COUNTER_1_RS_FEC_FEC_CORR_CW_CNTR_UPPER_ALIGN 0 24728 #define RX_X4_RS_FEC_STATUS0_FEC_CORRECTED_COUNTER_1_RS_FEC_FEC_CORR_CW_CNTR_UPPER_BITS 16 24729 #define RX_X4_RS_FEC_STATUS0_FEC_CORRECTED_COUNTER_1_RS_FEC_FEC_CORR_CW_CNTR_UPPER_SHIFT 0 24730 24731 24732 /**************************************************************************** 24733 * RX_X4_RS_FEC_Status0 :: fec_uncorrected_counter_0 24734 */ 24735 /* RX_X4_RS_FEC_Status0 :: fec_uncorrected_counter_0 :: RS_FEC_fec_uncorr_cw_cntr_lower [15:00] */ 24736 #define RX_X4_RS_FEC_STATUS0_FEC_UNCORRECTED_COUNTER_0_RS_FEC_FEC_UNCORR_CW_CNTR_LOWER_MASK 0xffff 24737 #define RX_X4_RS_FEC_STATUS0_FEC_UNCORRECTED_COUNTER_0_RS_FEC_FEC_UNCORR_CW_CNTR_LOWER_ALIGN 0 24738 #define RX_X4_RS_FEC_STATUS0_FEC_UNCORRECTED_COUNTER_0_RS_FEC_FEC_UNCORR_CW_CNTR_LOWER_BITS 16 24739 #define RX_X4_RS_FEC_STATUS0_FEC_UNCORRECTED_COUNTER_0_RS_FEC_FEC_UNCORR_CW_CNTR_LOWER_SHIFT 0 24740 24741 24742 /**************************************************************************** 24743 * RX_X4_RS_FEC_Status0 :: fec_uncorrected_counter_1 24744 */ 24745 /* RX_X4_RS_FEC_Status0 :: fec_uncorrected_counter_1 :: RS_FEC_fec_uncorr_cw_cntr_upper [15:00] */ 24746 #define RX_X4_RS_FEC_STATUS0_FEC_UNCORRECTED_COUNTER_1_RS_FEC_FEC_UNCORR_CW_CNTR_UPPER_MASK 0xffff 24747 #define RX_X4_RS_FEC_STATUS0_FEC_UNCORRECTED_COUNTER_1_RS_FEC_FEC_UNCORR_CW_CNTR_UPPER_ALIGN 0 24748 #define RX_X4_RS_FEC_STATUS0_FEC_UNCORRECTED_COUNTER_1_RS_FEC_FEC_UNCORR_CW_CNTR_UPPER_BITS 16 24749 #define RX_X4_RS_FEC_STATUS0_FEC_UNCORRECTED_COUNTER_1_RS_FEC_FEC_UNCORR_CW_CNTR_UPPER_SHIFT 0 24750 24751 24752 /**************************************************************************** 24753 * RX_X4_RS_FEC_Status0 :: fec_bit_error_counter_0 24754 */ 24755 /* RX_X4_RS_FEC_Status0 :: fec_bit_error_counter_0 :: RS_FEC_fec_corr_bit_cntr_lower [15:00] */ 24756 #define RX_X4_RS_FEC_STATUS0_FEC_BIT_ERROR_COUNTER_0_RS_FEC_FEC_CORR_BIT_CNTR_LOWER_MASK 0xffff 24757 #define RX_X4_RS_FEC_STATUS0_FEC_BIT_ERROR_COUNTER_0_RS_FEC_FEC_CORR_BIT_CNTR_LOWER_ALIGN 0 24758 #define RX_X4_RS_FEC_STATUS0_FEC_BIT_ERROR_COUNTER_0_RS_FEC_FEC_CORR_BIT_CNTR_LOWER_BITS 16 24759 #define RX_X4_RS_FEC_STATUS0_FEC_BIT_ERROR_COUNTER_0_RS_FEC_FEC_CORR_BIT_CNTR_LOWER_SHIFT 0 24760 24761 24762 /**************************************************************************** 24763 * RX_X4_RS_FEC_Status0 :: fec_bit_error_counter_1 24764 */ 24765 /* RX_X4_RS_FEC_Status0 :: fec_bit_error_counter_1 :: RS_FEC_fec_corr_bit_cntr_upper [15:00] */ 24766 #define RX_X4_RS_FEC_STATUS0_FEC_BIT_ERROR_COUNTER_1_RS_FEC_FEC_CORR_BIT_CNTR_UPPER_MASK 0xffff 24767 #define RX_X4_RS_FEC_STATUS0_FEC_BIT_ERROR_COUNTER_1_RS_FEC_FEC_CORR_BIT_CNTR_UPPER_ALIGN 0 24768 #define RX_X4_RS_FEC_STATUS0_FEC_BIT_ERROR_COUNTER_1_RS_FEC_FEC_CORR_BIT_CNTR_UPPER_BITS 16 24769 #define RX_X4_RS_FEC_STATUS0_FEC_BIT_ERROR_COUNTER_1_RS_FEC_FEC_CORR_BIT_CNTR_UPPER_SHIFT 0 24770 24771 24772 /**************************************************************************** 24773 * TSC_TSC_USER4_RX_X4_RS_FEC_Status1 24774 */ 24775 /**************************************************************************** 24776 * RX_X4_RS_FEC_Status1 :: RS_FEC_fec_symb_err_cntr_low_0 24777 */ 24778 /* RX_X4_RS_FEC_Status1 :: RS_FEC_fec_symb_err_cntr_low_0 :: fec_symbol_error_counter_lower_0 [15:00] */ 24779 #define RX_X4_RS_FEC_STATUS1_RS_FEC_FEC_SYMB_ERR_CNTR_LOW_0_FEC_SYMBOL_ERROR_COUNTER_LOWER_0_MASK 0xffff 24780 #define RX_X4_RS_FEC_STATUS1_RS_FEC_FEC_SYMB_ERR_CNTR_LOW_0_FEC_SYMBOL_ERROR_COUNTER_LOWER_0_ALIGN 0 24781 #define RX_X4_RS_FEC_STATUS1_RS_FEC_FEC_SYMB_ERR_CNTR_LOW_0_FEC_SYMBOL_ERROR_COUNTER_LOWER_0_BITS 16 24782 #define RX_X4_RS_FEC_STATUS1_RS_FEC_FEC_SYMB_ERR_CNTR_LOW_0_FEC_SYMBOL_ERROR_COUNTER_LOWER_0_SHIFT 0 24783 24784 24785 /**************************************************************************** 24786 * RX_X4_RS_FEC_Status1 :: RS_FEC_fec_symb_err_cntr_up_0 24787 */ 24788 /* RX_X4_RS_FEC_Status1 :: RS_FEC_fec_symb_err_cntr_up_0 :: fec_symbol_error_counter_upper_0 [15:00] */ 24789 #define RX_X4_RS_FEC_STATUS1_RS_FEC_FEC_SYMB_ERR_CNTR_UP_0_FEC_SYMBOL_ERROR_COUNTER_UPPER_0_MASK 0xffff 24790 #define RX_X4_RS_FEC_STATUS1_RS_FEC_FEC_SYMB_ERR_CNTR_UP_0_FEC_SYMBOL_ERROR_COUNTER_UPPER_0_ALIGN 0 24791 #define RX_X4_RS_FEC_STATUS1_RS_FEC_FEC_SYMB_ERR_CNTR_UP_0_FEC_SYMBOL_ERROR_COUNTER_UPPER_0_BITS 16 24792 #define RX_X4_RS_FEC_STATUS1_RS_FEC_FEC_SYMB_ERR_CNTR_UP_0_FEC_SYMBOL_ERROR_COUNTER_UPPER_0_SHIFT 0 24793 24794 24795 /**************************************************************************** 24796 * RX_X4_RS_FEC_Status1 :: RS_FEC_fec_symb_err_cntr_low_1 24797 */ 24798 /* RX_X4_RS_FEC_Status1 :: RS_FEC_fec_symb_err_cntr_low_1 :: fec_symbol_error_counter_lower_1 [15:00] */ 24799 #define RX_X4_RS_FEC_STATUS1_RS_FEC_FEC_SYMB_ERR_CNTR_LOW_1_FEC_SYMBOL_ERROR_COUNTER_LOWER_1_MASK 0xffff 24800 #define RX_X4_RS_FEC_STATUS1_RS_FEC_FEC_SYMB_ERR_CNTR_LOW_1_FEC_SYMBOL_ERROR_COUNTER_LOWER_1_ALIGN 0 24801 #define RX_X4_RS_FEC_STATUS1_RS_FEC_FEC_SYMB_ERR_CNTR_LOW_1_FEC_SYMBOL_ERROR_COUNTER_LOWER_1_BITS 16 24802 #define RX_X4_RS_FEC_STATUS1_RS_FEC_FEC_SYMB_ERR_CNTR_LOW_1_FEC_SYMBOL_ERROR_COUNTER_LOWER_1_SHIFT 0 24803 24804 24805 /**************************************************************************** 24806 * RX_X4_RS_FEC_Status1 :: RS_FEC_fec_symb_err_cntr_up_1 24807 */ 24808 /* RX_X4_RS_FEC_Status1 :: RS_FEC_fec_symb_err_cntr_up_1 :: fec_symbol_error_counter_upper_1 [15:00] */ 24809 #define RX_X4_RS_FEC_STATUS1_RS_FEC_FEC_SYMB_ERR_CNTR_UP_1_FEC_SYMBOL_ERROR_COUNTER_UPPER_1_MASK 0xffff 24810 #define RX_X4_RS_FEC_STATUS1_RS_FEC_FEC_SYMB_ERR_CNTR_UP_1_FEC_SYMBOL_ERROR_COUNTER_UPPER_1_ALIGN 0 24811 #define RX_X4_RS_FEC_STATUS1_RS_FEC_FEC_SYMB_ERR_CNTR_UP_1_FEC_SYMBOL_ERROR_COUNTER_UPPER_1_BITS 16 24812 #define RX_X4_RS_FEC_STATUS1_RS_FEC_FEC_SYMB_ERR_CNTR_UP_1_FEC_SYMBOL_ERROR_COUNTER_UPPER_1_SHIFT 0 24813 24814 24815 /**************************************************************************** 24816 * RX_X4_RS_FEC_Status1 :: RS_FEC_fec_symb_err_cntr_low_2 24817 */ 24818 /* RX_X4_RS_FEC_Status1 :: RS_FEC_fec_symb_err_cntr_low_2 :: fec_symbol_error_counter_lower_2 [15:00] */ 24819 #define RX_X4_RS_FEC_STATUS1_RS_FEC_FEC_SYMB_ERR_CNTR_LOW_2_FEC_SYMBOL_ERROR_COUNTER_LOWER_2_MASK 0xffff 24820 #define RX_X4_RS_FEC_STATUS1_RS_FEC_FEC_SYMB_ERR_CNTR_LOW_2_FEC_SYMBOL_ERROR_COUNTER_LOWER_2_ALIGN 0 24821 #define RX_X4_RS_FEC_STATUS1_RS_FEC_FEC_SYMB_ERR_CNTR_LOW_2_FEC_SYMBOL_ERROR_COUNTER_LOWER_2_BITS 16 24822 #define RX_X4_RS_FEC_STATUS1_RS_FEC_FEC_SYMB_ERR_CNTR_LOW_2_FEC_SYMBOL_ERROR_COUNTER_LOWER_2_SHIFT 0 24823 24824 24825 /**************************************************************************** 24826 * RX_X4_RS_FEC_Status1 :: RS_FEC_fec_symb_err_cntr_up_2 24827 */ 24828 /* RX_X4_RS_FEC_Status1 :: RS_FEC_fec_symb_err_cntr_up_2 :: fec_symbol_error_counter_upper_2 [15:00] */ 24829 #define RX_X4_RS_FEC_STATUS1_RS_FEC_FEC_SYMB_ERR_CNTR_UP_2_FEC_SYMBOL_ERROR_COUNTER_UPPER_2_MASK 0xffff 24830 #define RX_X4_RS_FEC_STATUS1_RS_FEC_FEC_SYMB_ERR_CNTR_UP_2_FEC_SYMBOL_ERROR_COUNTER_UPPER_2_ALIGN 0 24831 #define RX_X4_RS_FEC_STATUS1_RS_FEC_FEC_SYMB_ERR_CNTR_UP_2_FEC_SYMBOL_ERROR_COUNTER_UPPER_2_BITS 16 24832 #define RX_X4_RS_FEC_STATUS1_RS_FEC_FEC_SYMB_ERR_CNTR_UP_2_FEC_SYMBOL_ERROR_COUNTER_UPPER_2_SHIFT 0 24833 24834 24835 /**************************************************************************** 24836 * RX_X4_RS_FEC_Status1 :: RS_FEC_fec_symb_err_cntr_low_3 24837 */ 24838 /* RX_X4_RS_FEC_Status1 :: RS_FEC_fec_symb_err_cntr_low_3 :: fec_symbol_error_counter_lower_3 [15:00] */ 24839 #define RX_X4_RS_FEC_STATUS1_RS_FEC_FEC_SYMB_ERR_CNTR_LOW_3_FEC_SYMBOL_ERROR_COUNTER_LOWER_3_MASK 0xffff 24840 #define RX_X4_RS_FEC_STATUS1_RS_FEC_FEC_SYMB_ERR_CNTR_LOW_3_FEC_SYMBOL_ERROR_COUNTER_LOWER_3_ALIGN 0 24841 #define RX_X4_RS_FEC_STATUS1_RS_FEC_FEC_SYMB_ERR_CNTR_LOW_3_FEC_SYMBOL_ERROR_COUNTER_LOWER_3_BITS 16 24842 #define RX_X4_RS_FEC_STATUS1_RS_FEC_FEC_SYMB_ERR_CNTR_LOW_3_FEC_SYMBOL_ERROR_COUNTER_LOWER_3_SHIFT 0 24843 24844 24845 /**************************************************************************** 24846 * RX_X4_RS_FEC_Status1 :: RS_FEC_fec_symb_err_cntr_up_3 24847 */ 24848 /* RX_X4_RS_FEC_Status1 :: RS_FEC_fec_symb_err_cntr_up_3 :: fec_symbol_error_counter_upper_3 [15:00] */ 24849 #define RX_X4_RS_FEC_STATUS1_RS_FEC_FEC_SYMB_ERR_CNTR_UP_3_FEC_SYMBOL_ERROR_COUNTER_UPPER_3_MASK 0xffff 24850 #define RX_X4_RS_FEC_STATUS1_RS_FEC_FEC_SYMB_ERR_CNTR_UP_3_FEC_SYMBOL_ERROR_COUNTER_UPPER_3_ALIGN 0 24851 #define RX_X4_RS_FEC_STATUS1_RS_FEC_FEC_SYMB_ERR_CNTR_UP_3_FEC_SYMBOL_ERROR_COUNTER_UPPER_3_BITS 16 24852 #define RX_X4_RS_FEC_STATUS1_RS_FEC_FEC_SYMB_ERR_CNTR_UP_3_FEC_SYMBOL_ERROR_COUNTER_UPPER_3_SHIFT 0 24853 24854 24855 /**************************************************************************** 24856 * TSC_TSC_USER4_RX_X4_ECC 24857 */ 24858 /**************************************************************************** 24859 * RX_X4_ECC :: status_RS_FEC_buffer_blk_0 24860 */ 24861 /* RX_X4_ECC :: status_RS_FEC_buffer_blk_0 :: two_bit_err_event_RS_FEC_buffer_blk_0 [15:15] */ 24862 #define RX_X4_ECC_STATUS_RS_FEC_BUFFER_BLK_0_TWO_BIT_ERR_EVENT_RS_FEC_BUFFER_BLK_0_MASK 0x8000 24863 #define RX_X4_ECC_STATUS_RS_FEC_BUFFER_BLK_0_TWO_BIT_ERR_EVENT_RS_FEC_BUFFER_BLK_0_ALIGN 0 24864 #define RX_X4_ECC_STATUS_RS_FEC_BUFFER_BLK_0_TWO_BIT_ERR_EVENT_RS_FEC_BUFFER_BLK_0_BITS 1 24865 #define RX_X4_ECC_STATUS_RS_FEC_BUFFER_BLK_0_TWO_BIT_ERR_EVENT_RS_FEC_BUFFER_BLK_0_SHIFT 15 24866 24867 /* RX_X4_ECC :: status_RS_FEC_buffer_blk_0 :: one_bit_err_event_RS_FEC_buffer_blk_0 [14:14] */ 24868 #define RX_X4_ECC_STATUS_RS_FEC_BUFFER_BLK_0_ONE_BIT_ERR_EVENT_RS_FEC_BUFFER_BLK_0_MASK 0x4000 24869 #define RX_X4_ECC_STATUS_RS_FEC_BUFFER_BLK_0_ONE_BIT_ERR_EVENT_RS_FEC_BUFFER_BLK_0_ALIGN 0 24870 #define RX_X4_ECC_STATUS_RS_FEC_BUFFER_BLK_0_ONE_BIT_ERR_EVENT_RS_FEC_BUFFER_BLK_0_BITS 1 24871 #define RX_X4_ECC_STATUS_RS_FEC_BUFFER_BLK_0_ONE_BIT_ERR_EVENT_RS_FEC_BUFFER_BLK_0_SHIFT 14 24872 24873 /* RX_X4_ECC :: status_RS_FEC_buffer_blk_0 :: err_event_address_RS_FEC_buffer_blk_0 [13:00] */ 24874 #define RX_X4_ECC_STATUS_RS_FEC_BUFFER_BLK_0_ERR_EVENT_ADDRESS_RS_FEC_BUFFER_BLK_0_MASK 0x3fff 24875 #define RX_X4_ECC_STATUS_RS_FEC_BUFFER_BLK_0_ERR_EVENT_ADDRESS_RS_FEC_BUFFER_BLK_0_ALIGN 0 24876 #define RX_X4_ECC_STATUS_RS_FEC_BUFFER_BLK_0_ERR_EVENT_ADDRESS_RS_FEC_BUFFER_BLK_0_BITS 14 24877 #define RX_X4_ECC_STATUS_RS_FEC_BUFFER_BLK_0_ERR_EVENT_ADDRESS_RS_FEC_BUFFER_BLK_0_SHIFT 0 24878 24879 24880 /**************************************************************************** 24881 * RX_X4_ECC :: status_RS_FEC_buffer_blk_1 24882 */ 24883 /* RX_X4_ECC :: status_RS_FEC_buffer_blk_1 :: two_bit_err_event_RS_FEC_buffer_blk_1 [15:15] */ 24884 #define RX_X4_ECC_STATUS_RS_FEC_BUFFER_BLK_1_TWO_BIT_ERR_EVENT_RS_FEC_BUFFER_BLK_1_MASK 0x8000 24885 #define RX_X4_ECC_STATUS_RS_FEC_BUFFER_BLK_1_TWO_BIT_ERR_EVENT_RS_FEC_BUFFER_BLK_1_ALIGN 0 24886 #define RX_X4_ECC_STATUS_RS_FEC_BUFFER_BLK_1_TWO_BIT_ERR_EVENT_RS_FEC_BUFFER_BLK_1_BITS 1 24887 #define RX_X4_ECC_STATUS_RS_FEC_BUFFER_BLK_1_TWO_BIT_ERR_EVENT_RS_FEC_BUFFER_BLK_1_SHIFT 15 24888 24889 /* RX_X4_ECC :: status_RS_FEC_buffer_blk_1 :: one_bit_err_event_RS_FEC_buffer_blk_1 [14:14] */ 24890 #define RX_X4_ECC_STATUS_RS_FEC_BUFFER_BLK_1_ONE_BIT_ERR_EVENT_RS_FEC_BUFFER_BLK_1_MASK 0x4000 24891 #define RX_X4_ECC_STATUS_RS_FEC_BUFFER_BLK_1_ONE_BIT_ERR_EVENT_RS_FEC_BUFFER_BLK_1_ALIGN 0 24892 #define RX_X4_ECC_STATUS_RS_FEC_BUFFER_BLK_1_ONE_BIT_ERR_EVENT_RS_FEC_BUFFER_BLK_1_BITS 1 24893 #define RX_X4_ECC_STATUS_RS_FEC_BUFFER_BLK_1_ONE_BIT_ERR_EVENT_RS_FEC_BUFFER_BLK_1_SHIFT 14 24894 24895 /* RX_X4_ECC :: status_RS_FEC_buffer_blk_1 :: err_event_address_RS_FEC_buffer_blk_1 [13:00] */ 24896 #define RX_X4_ECC_STATUS_RS_FEC_BUFFER_BLK_1_ERR_EVENT_ADDRESS_RS_FEC_BUFFER_BLK_1_MASK 0x3fff 24897 #define RX_X4_ECC_STATUS_RS_FEC_BUFFER_BLK_1_ERR_EVENT_ADDRESS_RS_FEC_BUFFER_BLK_1_ALIGN 0 24898 #define RX_X4_ECC_STATUS_RS_FEC_BUFFER_BLK_1_ERR_EVENT_ADDRESS_RS_FEC_BUFFER_BLK_1_BITS 14 24899 #define RX_X4_ECC_STATUS_RS_FEC_BUFFER_BLK_1_ERR_EVENT_ADDRESS_RS_FEC_BUFFER_BLK_1_SHIFT 0 24900 24901 24902 /**************************************************************************** 24903 * RX_X4_ECC :: status_RS_FEC_buffer_blk_2 24904 */ 24905 /* RX_X4_ECC :: status_RS_FEC_buffer_blk_2 :: two_bit_err_event_RS_FEC_buffer_blk_2 [15:15] */ 24906 #define RX_X4_ECC_STATUS_RS_FEC_BUFFER_BLK_2_TWO_BIT_ERR_EVENT_RS_FEC_BUFFER_BLK_2_MASK 0x8000 24907 #define RX_X4_ECC_STATUS_RS_FEC_BUFFER_BLK_2_TWO_BIT_ERR_EVENT_RS_FEC_BUFFER_BLK_2_ALIGN 0 24908 #define RX_X4_ECC_STATUS_RS_FEC_BUFFER_BLK_2_TWO_BIT_ERR_EVENT_RS_FEC_BUFFER_BLK_2_BITS 1 24909 #define RX_X4_ECC_STATUS_RS_FEC_BUFFER_BLK_2_TWO_BIT_ERR_EVENT_RS_FEC_BUFFER_BLK_2_SHIFT 15 24910 24911 /* RX_X4_ECC :: status_RS_FEC_buffer_blk_2 :: one_bit_err_event_RS_FEC_buffer_blk_2 [14:14] */ 24912 #define RX_X4_ECC_STATUS_RS_FEC_BUFFER_BLK_2_ONE_BIT_ERR_EVENT_RS_FEC_BUFFER_BLK_2_MASK 0x4000 24913 #define RX_X4_ECC_STATUS_RS_FEC_BUFFER_BLK_2_ONE_BIT_ERR_EVENT_RS_FEC_BUFFER_BLK_2_ALIGN 0 24914 #define RX_X4_ECC_STATUS_RS_FEC_BUFFER_BLK_2_ONE_BIT_ERR_EVENT_RS_FEC_BUFFER_BLK_2_BITS 1 24915 #define RX_X4_ECC_STATUS_RS_FEC_BUFFER_BLK_2_ONE_BIT_ERR_EVENT_RS_FEC_BUFFER_BLK_2_SHIFT 14 24916 24917 /* RX_X4_ECC :: status_RS_FEC_buffer_blk_2 :: err_event_address_RS_FEC_buffer_blk_2 [13:00] */ 24918 #define RX_X4_ECC_STATUS_RS_FEC_BUFFER_BLK_2_ERR_EVENT_ADDRESS_RS_FEC_BUFFER_BLK_2_MASK 0x3fff 24919 #define RX_X4_ECC_STATUS_RS_FEC_BUFFER_BLK_2_ERR_EVENT_ADDRESS_RS_FEC_BUFFER_BLK_2_ALIGN 0 24920 #define RX_X4_ECC_STATUS_RS_FEC_BUFFER_BLK_2_ERR_EVENT_ADDRESS_RS_FEC_BUFFER_BLK_2_BITS 14 24921 #define RX_X4_ECC_STATUS_RS_FEC_BUFFER_BLK_2_ERR_EVENT_ADDRESS_RS_FEC_BUFFER_BLK_2_SHIFT 0 24922 24923 24924 /**************************************************************************** 24925 * RX_X4_ECC :: status_deskew_mem_0 24926 */ 24927 /* RX_X4_ECC :: status_deskew_mem_0 :: two_bit_err_event_deskew_0 [15:15] */ 24928 #define RX_X4_ECC_STATUS_DESKEW_MEM_0_TWO_BIT_ERR_EVENT_DESKEW_0_MASK 0x8000 24929 #define RX_X4_ECC_STATUS_DESKEW_MEM_0_TWO_BIT_ERR_EVENT_DESKEW_0_ALIGN 0 24930 #define RX_X4_ECC_STATUS_DESKEW_MEM_0_TWO_BIT_ERR_EVENT_DESKEW_0_BITS 1 24931 #define RX_X4_ECC_STATUS_DESKEW_MEM_0_TWO_BIT_ERR_EVENT_DESKEW_0_SHIFT 15 24932 24933 /* RX_X4_ECC :: status_deskew_mem_0 :: one_bit_err_event_deskew_0 [14:14] */ 24934 #define RX_X4_ECC_STATUS_DESKEW_MEM_0_ONE_BIT_ERR_EVENT_DESKEW_0_MASK 0x4000 24935 #define RX_X4_ECC_STATUS_DESKEW_MEM_0_ONE_BIT_ERR_EVENT_DESKEW_0_ALIGN 0 24936 #define RX_X4_ECC_STATUS_DESKEW_MEM_0_ONE_BIT_ERR_EVENT_DESKEW_0_BITS 1 24937 #define RX_X4_ECC_STATUS_DESKEW_MEM_0_ONE_BIT_ERR_EVENT_DESKEW_0_SHIFT 14 24938 24939 /* RX_X4_ECC :: status_deskew_mem_0 :: err_event_address_deskew_0 [13:00] */ 24940 #define RX_X4_ECC_STATUS_DESKEW_MEM_0_ERR_EVENT_ADDRESS_DESKEW_0_MASK 0x3fff 24941 #define RX_X4_ECC_STATUS_DESKEW_MEM_0_ERR_EVENT_ADDRESS_DESKEW_0_ALIGN 0 24942 #define RX_X4_ECC_STATUS_DESKEW_MEM_0_ERR_EVENT_ADDRESS_DESKEW_0_BITS 14 24943 #define RX_X4_ECC_STATUS_DESKEW_MEM_0_ERR_EVENT_ADDRESS_DESKEW_0_SHIFT 0 24944 24945 24946 /**************************************************************************** 24947 * RX_X4_ECC :: status_deskew_mem_1 24948 */ 24949 /* RX_X4_ECC :: status_deskew_mem_1 :: two_bit_err_event_deskew_1 [15:15] */ 24950 #define RX_X4_ECC_STATUS_DESKEW_MEM_1_TWO_BIT_ERR_EVENT_DESKEW_1_MASK 0x8000 24951 #define RX_X4_ECC_STATUS_DESKEW_MEM_1_TWO_BIT_ERR_EVENT_DESKEW_1_ALIGN 0 24952 #define RX_X4_ECC_STATUS_DESKEW_MEM_1_TWO_BIT_ERR_EVENT_DESKEW_1_BITS 1 24953 #define RX_X4_ECC_STATUS_DESKEW_MEM_1_TWO_BIT_ERR_EVENT_DESKEW_1_SHIFT 15 24954 24955 /* RX_X4_ECC :: status_deskew_mem_1 :: one_bit_err_event_deskew_1 [14:14] */ 24956 #define RX_X4_ECC_STATUS_DESKEW_MEM_1_ONE_BIT_ERR_EVENT_DESKEW_1_MASK 0x4000 24957 #define RX_X4_ECC_STATUS_DESKEW_MEM_1_ONE_BIT_ERR_EVENT_DESKEW_1_ALIGN 0 24958 #define RX_X4_ECC_STATUS_DESKEW_MEM_1_ONE_BIT_ERR_EVENT_DESKEW_1_BITS 1 24959 #define RX_X4_ECC_STATUS_DESKEW_MEM_1_ONE_BIT_ERR_EVENT_DESKEW_1_SHIFT 14 24960 24961 /* RX_X4_ECC :: status_deskew_mem_1 :: err_event_address_deskew_1 [13:00] */ 24962 #define RX_X4_ECC_STATUS_DESKEW_MEM_1_ERR_EVENT_ADDRESS_DESKEW_1_MASK 0x3fff 24963 #define RX_X4_ECC_STATUS_DESKEW_MEM_1_ERR_EVENT_ADDRESS_DESKEW_1_ALIGN 0 24964 #define RX_X4_ECC_STATUS_DESKEW_MEM_1_ERR_EVENT_ADDRESS_DESKEW_1_BITS 14 24965 #define RX_X4_ECC_STATUS_DESKEW_MEM_1_ERR_EVENT_ADDRESS_DESKEW_1_SHIFT 0 24966 24967 24968 /**************************************************************************** 24969 * RX_X4_ECC :: status_deskew_mem_2 24970 */ 24971 /* RX_X4_ECC :: status_deskew_mem_2 :: two_bit_err_event_deskew_2 [15:15] */ 24972 #define RX_X4_ECC_STATUS_DESKEW_MEM_2_TWO_BIT_ERR_EVENT_DESKEW_2_MASK 0x8000 24973 #define RX_X4_ECC_STATUS_DESKEW_MEM_2_TWO_BIT_ERR_EVENT_DESKEW_2_ALIGN 0 24974 #define RX_X4_ECC_STATUS_DESKEW_MEM_2_TWO_BIT_ERR_EVENT_DESKEW_2_BITS 1 24975 #define RX_X4_ECC_STATUS_DESKEW_MEM_2_TWO_BIT_ERR_EVENT_DESKEW_2_SHIFT 15 24976 24977 /* RX_X4_ECC :: status_deskew_mem_2 :: one_bit_err_event_deskew_2 [14:14] */ 24978 #define RX_X4_ECC_STATUS_DESKEW_MEM_2_ONE_BIT_ERR_EVENT_DESKEW_2_MASK 0x4000 24979 #define RX_X4_ECC_STATUS_DESKEW_MEM_2_ONE_BIT_ERR_EVENT_DESKEW_2_ALIGN 0 24980 #define RX_X4_ECC_STATUS_DESKEW_MEM_2_ONE_BIT_ERR_EVENT_DESKEW_2_BITS 1 24981 #define RX_X4_ECC_STATUS_DESKEW_MEM_2_ONE_BIT_ERR_EVENT_DESKEW_2_SHIFT 14 24982 24983 /* RX_X4_ECC :: status_deskew_mem_2 :: err_event_address_deskew_2 [13:00] */ 24984 #define RX_X4_ECC_STATUS_DESKEW_MEM_2_ERR_EVENT_ADDRESS_DESKEW_2_MASK 0x3fff 24985 #define RX_X4_ECC_STATUS_DESKEW_MEM_2_ERR_EVENT_ADDRESS_DESKEW_2_ALIGN 0 24986 #define RX_X4_ECC_STATUS_DESKEW_MEM_2_ERR_EVENT_ADDRESS_DESKEW_2_BITS 14 24987 #define RX_X4_ECC_STATUS_DESKEW_MEM_2_ERR_EVENT_ADDRESS_DESKEW_2_SHIFT 0 24988 24989 24990 /**************************************************************************** 24991 * RX_X4_ECC :: interrupt_status_1bit 24992 */ 24993 /* RX_X4_ECC :: interrupt_status_1bit :: reserved0 [15:06] */ 24994 #define RX_X4_ECC_INTERRUPT_STATUS_1BIT_RESERVED0_MASK 0xffc0 24995 #define RX_X4_ECC_INTERRUPT_STATUS_1BIT_RESERVED0_ALIGN 0 24996 #define RX_X4_ECC_INTERRUPT_STATUS_1BIT_RESERVED0_BITS 10 24997 #define RX_X4_ECC_INTERRUPT_STATUS_1BIT_RESERVED0_SHIFT 6 24998 24999 /* RX_X4_ECC :: interrupt_status_1bit :: deskew_mem_2_1bit_int_status [05:05] */ 25000 #define RX_X4_ECC_INTERRUPT_STATUS_1BIT_DESKEW_MEM_2_1BIT_INT_STATUS_MASK 0x0020 25001 #define RX_X4_ECC_INTERRUPT_STATUS_1BIT_DESKEW_MEM_2_1BIT_INT_STATUS_ALIGN 0 25002 #define RX_X4_ECC_INTERRUPT_STATUS_1BIT_DESKEW_MEM_2_1BIT_INT_STATUS_BITS 1 25003 #define RX_X4_ECC_INTERRUPT_STATUS_1BIT_DESKEW_MEM_2_1BIT_INT_STATUS_SHIFT 5 25004 25005 /* RX_X4_ECC :: interrupt_status_1bit :: deskew_mem_1_1bit_int_status [04:04] */ 25006 #define RX_X4_ECC_INTERRUPT_STATUS_1BIT_DESKEW_MEM_1_1BIT_INT_STATUS_MASK 0x0010 25007 #define RX_X4_ECC_INTERRUPT_STATUS_1BIT_DESKEW_MEM_1_1BIT_INT_STATUS_ALIGN 0 25008 #define RX_X4_ECC_INTERRUPT_STATUS_1BIT_DESKEW_MEM_1_1BIT_INT_STATUS_BITS 1 25009 #define RX_X4_ECC_INTERRUPT_STATUS_1BIT_DESKEW_MEM_1_1BIT_INT_STATUS_SHIFT 4 25010 25011 /* RX_X4_ECC :: interrupt_status_1bit :: deskew_mem_0_1bit_int_status [03:03] */ 25012 #define RX_X4_ECC_INTERRUPT_STATUS_1BIT_DESKEW_MEM_0_1BIT_INT_STATUS_MASK 0x0008 25013 #define RX_X4_ECC_INTERRUPT_STATUS_1BIT_DESKEW_MEM_0_1BIT_INT_STATUS_ALIGN 0 25014 #define RX_X4_ECC_INTERRUPT_STATUS_1BIT_DESKEW_MEM_0_1BIT_INT_STATUS_BITS 1 25015 #define RX_X4_ECC_INTERRUPT_STATUS_1BIT_DESKEW_MEM_0_1BIT_INT_STATUS_SHIFT 3 25016 25017 /* RX_X4_ECC :: interrupt_status_1bit :: RS_FEC_buffer_blk2_1bit_int_status [02:02] */ 25018 #define RX_X4_ECC_INTERRUPT_STATUS_1BIT_RS_FEC_BUFFER_BLK2_1BIT_INT_STATUS_MASK 0x0004 25019 #define RX_X4_ECC_INTERRUPT_STATUS_1BIT_RS_FEC_BUFFER_BLK2_1BIT_INT_STATUS_ALIGN 0 25020 #define RX_X4_ECC_INTERRUPT_STATUS_1BIT_RS_FEC_BUFFER_BLK2_1BIT_INT_STATUS_BITS 1 25021 #define RX_X4_ECC_INTERRUPT_STATUS_1BIT_RS_FEC_BUFFER_BLK2_1BIT_INT_STATUS_SHIFT 2 25022 25023 /* RX_X4_ECC :: interrupt_status_1bit :: RS_FEC_buffer_blk1_1bit_int_status [01:01] */ 25024 #define RX_X4_ECC_INTERRUPT_STATUS_1BIT_RS_FEC_BUFFER_BLK1_1BIT_INT_STATUS_MASK 0x0002 25025 #define RX_X4_ECC_INTERRUPT_STATUS_1BIT_RS_FEC_BUFFER_BLK1_1BIT_INT_STATUS_ALIGN 0 25026 #define RX_X4_ECC_INTERRUPT_STATUS_1BIT_RS_FEC_BUFFER_BLK1_1BIT_INT_STATUS_BITS 1 25027 #define RX_X4_ECC_INTERRUPT_STATUS_1BIT_RS_FEC_BUFFER_BLK1_1BIT_INT_STATUS_SHIFT 1 25028 25029 /* RX_X4_ECC :: interrupt_status_1bit :: RS_FEC_buffer_blk0_1bit_int_status [00:00] */ 25030 #define RX_X4_ECC_INTERRUPT_STATUS_1BIT_RS_FEC_BUFFER_BLK0_1BIT_INT_STATUS_MASK 0x0001 25031 #define RX_X4_ECC_INTERRUPT_STATUS_1BIT_RS_FEC_BUFFER_BLK0_1BIT_INT_STATUS_ALIGN 0 25032 #define RX_X4_ECC_INTERRUPT_STATUS_1BIT_RS_FEC_BUFFER_BLK0_1BIT_INT_STATUS_BITS 1 25033 #define RX_X4_ECC_INTERRUPT_STATUS_1BIT_RS_FEC_BUFFER_BLK0_1BIT_INT_STATUS_SHIFT 0 25034 25035 25036 /**************************************************************************** 25037 * RX_X4_ECC :: interrupt_status_2bit 25038 */ 25039 /* RX_X4_ECC :: interrupt_status_2bit :: reserved0 [15:06] */ 25040 #define RX_X4_ECC_INTERRUPT_STATUS_2BIT_RESERVED0_MASK 0xffc0 25041 #define RX_X4_ECC_INTERRUPT_STATUS_2BIT_RESERVED0_ALIGN 0 25042 #define RX_X4_ECC_INTERRUPT_STATUS_2BIT_RESERVED0_BITS 10 25043 #define RX_X4_ECC_INTERRUPT_STATUS_2BIT_RESERVED0_SHIFT 6 25044 25045 /* RX_X4_ECC :: interrupt_status_2bit :: deskew_mem_2_2bit_int_status [05:05] */ 25046 #define RX_X4_ECC_INTERRUPT_STATUS_2BIT_DESKEW_MEM_2_2BIT_INT_STATUS_MASK 0x0020 25047 #define RX_X4_ECC_INTERRUPT_STATUS_2BIT_DESKEW_MEM_2_2BIT_INT_STATUS_ALIGN 0 25048 #define RX_X4_ECC_INTERRUPT_STATUS_2BIT_DESKEW_MEM_2_2BIT_INT_STATUS_BITS 1 25049 #define RX_X4_ECC_INTERRUPT_STATUS_2BIT_DESKEW_MEM_2_2BIT_INT_STATUS_SHIFT 5 25050 25051 /* RX_X4_ECC :: interrupt_status_2bit :: deskew_mem_1_2bit_int_status [04:04] */ 25052 #define RX_X4_ECC_INTERRUPT_STATUS_2BIT_DESKEW_MEM_1_2BIT_INT_STATUS_MASK 0x0010 25053 #define RX_X4_ECC_INTERRUPT_STATUS_2BIT_DESKEW_MEM_1_2BIT_INT_STATUS_ALIGN 0 25054 #define RX_X4_ECC_INTERRUPT_STATUS_2BIT_DESKEW_MEM_1_2BIT_INT_STATUS_BITS 1 25055 #define RX_X4_ECC_INTERRUPT_STATUS_2BIT_DESKEW_MEM_1_2BIT_INT_STATUS_SHIFT 4 25056 25057 /* RX_X4_ECC :: interrupt_status_2bit :: deskew_mem_0_2bit_int_status [03:03] */ 25058 #define RX_X4_ECC_INTERRUPT_STATUS_2BIT_DESKEW_MEM_0_2BIT_INT_STATUS_MASK 0x0008 25059 #define RX_X4_ECC_INTERRUPT_STATUS_2BIT_DESKEW_MEM_0_2BIT_INT_STATUS_ALIGN 0 25060 #define RX_X4_ECC_INTERRUPT_STATUS_2BIT_DESKEW_MEM_0_2BIT_INT_STATUS_BITS 1 25061 #define RX_X4_ECC_INTERRUPT_STATUS_2BIT_DESKEW_MEM_0_2BIT_INT_STATUS_SHIFT 3 25062 25063 /* RX_X4_ECC :: interrupt_status_2bit :: RS_FEC_buffer_blk2_2bit_int_status [02:02] */ 25064 #define RX_X4_ECC_INTERRUPT_STATUS_2BIT_RS_FEC_BUFFER_BLK2_2BIT_INT_STATUS_MASK 0x0004 25065 #define RX_X4_ECC_INTERRUPT_STATUS_2BIT_RS_FEC_BUFFER_BLK2_2BIT_INT_STATUS_ALIGN 0 25066 #define RX_X4_ECC_INTERRUPT_STATUS_2BIT_RS_FEC_BUFFER_BLK2_2BIT_INT_STATUS_BITS 1 25067 #define RX_X4_ECC_INTERRUPT_STATUS_2BIT_RS_FEC_BUFFER_BLK2_2BIT_INT_STATUS_SHIFT 2 25068 25069 /* RX_X4_ECC :: interrupt_status_2bit :: RS_FEC_buffer_blk1_2bit_int_status [01:01] */ 25070 #define RX_X4_ECC_INTERRUPT_STATUS_2BIT_RS_FEC_BUFFER_BLK1_2BIT_INT_STATUS_MASK 0x0002 25071 #define RX_X4_ECC_INTERRUPT_STATUS_2BIT_RS_FEC_BUFFER_BLK1_2BIT_INT_STATUS_ALIGN 0 25072 #define RX_X4_ECC_INTERRUPT_STATUS_2BIT_RS_FEC_BUFFER_BLK1_2BIT_INT_STATUS_BITS 1 25073 #define RX_X4_ECC_INTERRUPT_STATUS_2BIT_RS_FEC_BUFFER_BLK1_2BIT_INT_STATUS_SHIFT 1 25074 25075 /* RX_X4_ECC :: interrupt_status_2bit :: RS_FEC_buffer_blk0_2bit_int_status [00:00] */ 25076 #define RX_X4_ECC_INTERRUPT_STATUS_2BIT_RS_FEC_BUFFER_BLK0_2BIT_INT_STATUS_MASK 0x0001 25077 #define RX_X4_ECC_INTERRUPT_STATUS_2BIT_RS_FEC_BUFFER_BLK0_2BIT_INT_STATUS_ALIGN 0 25078 #define RX_X4_ECC_INTERRUPT_STATUS_2BIT_RS_FEC_BUFFER_BLK0_2BIT_INT_STATUS_BITS 1 25079 #define RX_X4_ECC_INTERRUPT_STATUS_2BIT_RS_FEC_BUFFER_BLK0_2BIT_INT_STATUS_SHIFT 0 25080 25081 25082 /**************************************************************************** 25083 * RX_X4_ECC :: interrupt_en_1bit 25084 */ 25085 /* RX_X4_ECC :: interrupt_en_1bit :: reserved0 [15:06] */ 25086 #define RX_X4_ECC_INTERRUPT_EN_1BIT_RESERVED0_MASK 0xffc0 25087 #define RX_X4_ECC_INTERRUPT_EN_1BIT_RESERVED0_ALIGN 0 25088 #define RX_X4_ECC_INTERRUPT_EN_1BIT_RESERVED0_BITS 10 25089 #define RX_X4_ECC_INTERRUPT_EN_1BIT_RESERVED0_SHIFT 6 25090 25091 /* RX_X4_ECC :: interrupt_en_1bit :: deskew_mem_2_1bit_int_en [05:05] */ 25092 #define RX_X4_ECC_INTERRUPT_EN_1BIT_DESKEW_MEM_2_1BIT_INT_EN_MASK 0x0020 25093 #define RX_X4_ECC_INTERRUPT_EN_1BIT_DESKEW_MEM_2_1BIT_INT_EN_ALIGN 0 25094 #define RX_X4_ECC_INTERRUPT_EN_1BIT_DESKEW_MEM_2_1BIT_INT_EN_BITS 1 25095 #define RX_X4_ECC_INTERRUPT_EN_1BIT_DESKEW_MEM_2_1BIT_INT_EN_SHIFT 5 25096 25097 /* RX_X4_ECC :: interrupt_en_1bit :: deskew_mem_1_1bit_int_en [04:04] */ 25098 #define RX_X4_ECC_INTERRUPT_EN_1BIT_DESKEW_MEM_1_1BIT_INT_EN_MASK 0x0010 25099 #define RX_X4_ECC_INTERRUPT_EN_1BIT_DESKEW_MEM_1_1BIT_INT_EN_ALIGN 0 25100 #define RX_X4_ECC_INTERRUPT_EN_1BIT_DESKEW_MEM_1_1BIT_INT_EN_BITS 1 25101 #define RX_X4_ECC_INTERRUPT_EN_1BIT_DESKEW_MEM_1_1BIT_INT_EN_SHIFT 4 25102 25103 /* RX_X4_ECC :: interrupt_en_1bit :: deskew_mem_0_1bit_int_en [03:03] */ 25104 #define RX_X4_ECC_INTERRUPT_EN_1BIT_DESKEW_MEM_0_1BIT_INT_EN_MASK 0x0008 25105 #define RX_X4_ECC_INTERRUPT_EN_1BIT_DESKEW_MEM_0_1BIT_INT_EN_ALIGN 0 25106 #define RX_X4_ECC_INTERRUPT_EN_1BIT_DESKEW_MEM_0_1BIT_INT_EN_BITS 1 25107 #define RX_X4_ECC_INTERRUPT_EN_1BIT_DESKEW_MEM_0_1BIT_INT_EN_SHIFT 3 25108 25109 /* RX_X4_ECC :: interrupt_en_1bit :: RS_FEC_buffer_blk2_1bit_int_en [02:02] */ 25110 #define RX_X4_ECC_INTERRUPT_EN_1BIT_RS_FEC_BUFFER_BLK2_1BIT_INT_EN_MASK 0x0004 25111 #define RX_X4_ECC_INTERRUPT_EN_1BIT_RS_FEC_BUFFER_BLK2_1BIT_INT_EN_ALIGN 0 25112 #define RX_X4_ECC_INTERRUPT_EN_1BIT_RS_FEC_BUFFER_BLK2_1BIT_INT_EN_BITS 1 25113 #define RX_X4_ECC_INTERRUPT_EN_1BIT_RS_FEC_BUFFER_BLK2_1BIT_INT_EN_SHIFT 2 25114 25115 /* RX_X4_ECC :: interrupt_en_1bit :: RS_FEC_buffer_blk1_1bit_int_en [01:01] */ 25116 #define RX_X4_ECC_INTERRUPT_EN_1BIT_RS_FEC_BUFFER_BLK1_1BIT_INT_EN_MASK 0x0002 25117 #define RX_X4_ECC_INTERRUPT_EN_1BIT_RS_FEC_BUFFER_BLK1_1BIT_INT_EN_ALIGN 0 25118 #define RX_X4_ECC_INTERRUPT_EN_1BIT_RS_FEC_BUFFER_BLK1_1BIT_INT_EN_BITS 1 25119 #define RX_X4_ECC_INTERRUPT_EN_1BIT_RS_FEC_BUFFER_BLK1_1BIT_INT_EN_SHIFT 1 25120 25121 /* RX_X4_ECC :: interrupt_en_1bit :: RS_FEC_buffer_blk0_1bit_int_en [00:00] */ 25122 #define RX_X4_ECC_INTERRUPT_EN_1BIT_RS_FEC_BUFFER_BLK0_1BIT_INT_EN_MASK 0x0001 25123 #define RX_X4_ECC_INTERRUPT_EN_1BIT_RS_FEC_BUFFER_BLK0_1BIT_INT_EN_ALIGN 0 25124 #define RX_X4_ECC_INTERRUPT_EN_1BIT_RS_FEC_BUFFER_BLK0_1BIT_INT_EN_BITS 1 25125 #define RX_X4_ECC_INTERRUPT_EN_1BIT_RS_FEC_BUFFER_BLK0_1BIT_INT_EN_SHIFT 0 25126 25127 25128 /**************************************************************************** 25129 * RX_X4_ECC :: interrupt_en_2bit 25130 */ 25131 /* RX_X4_ECC :: interrupt_en_2bit :: reserved0 [15:06] */ 25132 #define RX_X4_ECC_INTERRUPT_EN_2BIT_RESERVED0_MASK 0xffc0 25133 #define RX_X4_ECC_INTERRUPT_EN_2BIT_RESERVED0_ALIGN 0 25134 #define RX_X4_ECC_INTERRUPT_EN_2BIT_RESERVED0_BITS 10 25135 #define RX_X4_ECC_INTERRUPT_EN_2BIT_RESERVED0_SHIFT 6 25136 25137 /* RX_X4_ECC :: interrupt_en_2bit :: deskew_mem_2_2bit_int_en [05:05] */ 25138 #define RX_X4_ECC_INTERRUPT_EN_2BIT_DESKEW_MEM_2_2BIT_INT_EN_MASK 0x0020 25139 #define RX_X4_ECC_INTERRUPT_EN_2BIT_DESKEW_MEM_2_2BIT_INT_EN_ALIGN 0 25140 #define RX_X4_ECC_INTERRUPT_EN_2BIT_DESKEW_MEM_2_2BIT_INT_EN_BITS 1 25141 #define RX_X4_ECC_INTERRUPT_EN_2BIT_DESKEW_MEM_2_2BIT_INT_EN_SHIFT 5 25142 25143 /* RX_X4_ECC :: interrupt_en_2bit :: deskew_mem_1_2bit_int_en [04:04] */ 25144 #define RX_X4_ECC_INTERRUPT_EN_2BIT_DESKEW_MEM_1_2BIT_INT_EN_MASK 0x0010 25145 #define RX_X4_ECC_INTERRUPT_EN_2BIT_DESKEW_MEM_1_2BIT_INT_EN_ALIGN 0 25146 #define RX_X4_ECC_INTERRUPT_EN_2BIT_DESKEW_MEM_1_2BIT_INT_EN_BITS 1 25147 #define RX_X4_ECC_INTERRUPT_EN_2BIT_DESKEW_MEM_1_2BIT_INT_EN_SHIFT 4 25148 25149 /* RX_X4_ECC :: interrupt_en_2bit :: deskew_mem_0_2bit_int_en [03:03] */ 25150 #define RX_X4_ECC_INTERRUPT_EN_2BIT_DESKEW_MEM_0_2BIT_INT_EN_MASK 0x0008 25151 #define RX_X4_ECC_INTERRUPT_EN_2BIT_DESKEW_MEM_0_2BIT_INT_EN_ALIGN 0 25152 #define RX_X4_ECC_INTERRUPT_EN_2BIT_DESKEW_MEM_0_2BIT_INT_EN_BITS 1 25153 #define RX_X4_ECC_INTERRUPT_EN_2BIT_DESKEW_MEM_0_2BIT_INT_EN_SHIFT 3 25154 25155 /* RX_X4_ECC :: interrupt_en_2bit :: RS_FEC_buffer_blk2_2bit_int_en [02:02] */ 25156 #define RX_X4_ECC_INTERRUPT_EN_2BIT_RS_FEC_BUFFER_BLK2_2BIT_INT_EN_MASK 0x0004 25157 #define RX_X4_ECC_INTERRUPT_EN_2BIT_RS_FEC_BUFFER_BLK2_2BIT_INT_EN_ALIGN 0 25158 #define RX_X4_ECC_INTERRUPT_EN_2BIT_RS_FEC_BUFFER_BLK2_2BIT_INT_EN_BITS 1 25159 #define RX_X4_ECC_INTERRUPT_EN_2BIT_RS_FEC_BUFFER_BLK2_2BIT_INT_EN_SHIFT 2 25160 25161 /* RX_X4_ECC :: interrupt_en_2bit :: RS_FEC_buffer_blk1_2bit_int_en [01:01] */ 25162 #define RX_X4_ECC_INTERRUPT_EN_2BIT_RS_FEC_BUFFER_BLK1_2BIT_INT_EN_MASK 0x0002 25163 #define RX_X4_ECC_INTERRUPT_EN_2BIT_RS_FEC_BUFFER_BLK1_2BIT_INT_EN_ALIGN 0 25164 #define RX_X4_ECC_INTERRUPT_EN_2BIT_RS_FEC_BUFFER_BLK1_2BIT_INT_EN_BITS 1 25165 #define RX_X4_ECC_INTERRUPT_EN_2BIT_RS_FEC_BUFFER_BLK1_2BIT_INT_EN_SHIFT 1 25166 25167 /* RX_X4_ECC :: interrupt_en_2bit :: RS_FEC_buffer_blk0_2bit_int_en [00:00] */ 25168 #define RX_X4_ECC_INTERRUPT_EN_2BIT_RS_FEC_BUFFER_BLK0_2BIT_INT_EN_MASK 0x0001 25169 #define RX_X4_ECC_INTERRUPT_EN_2BIT_RS_FEC_BUFFER_BLK0_2BIT_INT_EN_ALIGN 0 25170 #define RX_X4_ECC_INTERRUPT_EN_2BIT_RS_FEC_BUFFER_BLK0_2BIT_INT_EN_BITS 1 25171 #define RX_X4_ECC_INTERRUPT_EN_2BIT_RS_FEC_BUFFER_BLK0_2BIT_INT_EN_SHIFT 0 25172 25173 25174 /**************************************************************************** 25175 * RX_X4_ECC :: disable_ecc_mem 25176 */ 25177 /* RX_X4_ECC :: disable_ecc_mem :: reserved0 [15:06] */ 25178 #define RX_X4_ECC_DISABLE_ECC_MEM_RESERVED0_MASK 0xffc0 25179 #define RX_X4_ECC_DISABLE_ECC_MEM_RESERVED0_ALIGN 0 25180 #define RX_X4_ECC_DISABLE_ECC_MEM_RESERVED0_BITS 10 25181 #define RX_X4_ECC_DISABLE_ECC_MEM_RESERVED0_SHIFT 6 25182 25183 /* RX_X4_ECC :: disable_ecc_mem :: disable_ecc_deskew_mem_2 [05:05] */ 25184 #define RX_X4_ECC_DISABLE_ECC_MEM_DISABLE_ECC_DESKEW_MEM_2_MASK 0x0020 25185 #define RX_X4_ECC_DISABLE_ECC_MEM_DISABLE_ECC_DESKEW_MEM_2_ALIGN 0 25186 #define RX_X4_ECC_DISABLE_ECC_MEM_DISABLE_ECC_DESKEW_MEM_2_BITS 1 25187 #define RX_X4_ECC_DISABLE_ECC_MEM_DISABLE_ECC_DESKEW_MEM_2_SHIFT 5 25188 25189 /* RX_X4_ECC :: disable_ecc_mem :: disable_ecc_deskew_mem_1 [04:04] */ 25190 #define RX_X4_ECC_DISABLE_ECC_MEM_DISABLE_ECC_DESKEW_MEM_1_MASK 0x0010 25191 #define RX_X4_ECC_DISABLE_ECC_MEM_DISABLE_ECC_DESKEW_MEM_1_ALIGN 0 25192 #define RX_X4_ECC_DISABLE_ECC_MEM_DISABLE_ECC_DESKEW_MEM_1_BITS 1 25193 #define RX_X4_ECC_DISABLE_ECC_MEM_DISABLE_ECC_DESKEW_MEM_1_SHIFT 4 25194 25195 /* RX_X4_ECC :: disable_ecc_mem :: disable_ecc_deskew_mem_0 [03:03] */ 25196 #define RX_X4_ECC_DISABLE_ECC_MEM_DISABLE_ECC_DESKEW_MEM_0_MASK 0x0008 25197 #define RX_X4_ECC_DISABLE_ECC_MEM_DISABLE_ECC_DESKEW_MEM_0_ALIGN 0 25198 #define RX_X4_ECC_DISABLE_ECC_MEM_DISABLE_ECC_DESKEW_MEM_0_BITS 1 25199 #define RX_X4_ECC_DISABLE_ECC_MEM_DISABLE_ECC_DESKEW_MEM_0_SHIFT 3 25200 25201 /* RX_X4_ECC :: disable_ecc_mem :: disable_ecc_RS_FEC_buffer_blk2 [02:02] */ 25202 #define RX_X4_ECC_DISABLE_ECC_MEM_DISABLE_ECC_RS_FEC_BUFFER_BLK2_MASK 0x0004 25203 #define RX_X4_ECC_DISABLE_ECC_MEM_DISABLE_ECC_RS_FEC_BUFFER_BLK2_ALIGN 0 25204 #define RX_X4_ECC_DISABLE_ECC_MEM_DISABLE_ECC_RS_FEC_BUFFER_BLK2_BITS 1 25205 #define RX_X4_ECC_DISABLE_ECC_MEM_DISABLE_ECC_RS_FEC_BUFFER_BLK2_SHIFT 2 25206 25207 /* RX_X4_ECC :: disable_ecc_mem :: disable_ecc_RS_FEC_buffer_blk1 [01:01] */ 25208 #define RX_X4_ECC_DISABLE_ECC_MEM_DISABLE_ECC_RS_FEC_BUFFER_BLK1_MASK 0x0002 25209 #define RX_X4_ECC_DISABLE_ECC_MEM_DISABLE_ECC_RS_FEC_BUFFER_BLK1_ALIGN 0 25210 #define RX_X4_ECC_DISABLE_ECC_MEM_DISABLE_ECC_RS_FEC_BUFFER_BLK1_BITS 1 25211 #define RX_X4_ECC_DISABLE_ECC_MEM_DISABLE_ECC_RS_FEC_BUFFER_BLK1_SHIFT 1 25212 25213 /* RX_X4_ECC :: disable_ecc_mem :: disable_ecc_RS_FEC_buffer_blk0 [00:00] */ 25214 #define RX_X4_ECC_DISABLE_ECC_MEM_DISABLE_ECC_RS_FEC_BUFFER_BLK0_MASK 0x0001 25215 #define RX_X4_ECC_DISABLE_ECC_MEM_DISABLE_ECC_RS_FEC_BUFFER_BLK0_ALIGN 0 25216 #define RX_X4_ECC_DISABLE_ECC_MEM_DISABLE_ECC_RS_FEC_BUFFER_BLK0_BITS 1 25217 #define RX_X4_ECC_DISABLE_ECC_MEM_DISABLE_ECC_RS_FEC_BUFFER_BLK0_SHIFT 0 25218 25219 25220 /**************************************************************************** 25221 * RX_X4_ECC :: corrupt 25222 */ 25223 /* RX_X4_ECC :: corrupt :: reserved0 [15:12] */ 25224 #define RX_X4_ECC_CORRUPT_RESERVED0_MASK 0xf000 25225 #define RX_X4_ECC_CORRUPT_RESERVED0_ALIGN 0 25226 #define RX_X4_ECC_CORRUPT_RESERVED0_BITS 4 25227 #define RX_X4_ECC_CORRUPT_RESERVED0_SHIFT 12 25228 25229 /* RX_X4_ECC :: corrupt :: corrupt_ecc_deskew_mem_2 [11:10] */ 25230 #define RX_X4_ECC_CORRUPT_CORRUPT_ECC_DESKEW_MEM_2_MASK 0x0c00 25231 #define RX_X4_ECC_CORRUPT_CORRUPT_ECC_DESKEW_MEM_2_ALIGN 0 25232 #define RX_X4_ECC_CORRUPT_CORRUPT_ECC_DESKEW_MEM_2_BITS 2 25233 #define RX_X4_ECC_CORRUPT_CORRUPT_ECC_DESKEW_MEM_2_SHIFT 10 25234 25235 /* RX_X4_ECC :: corrupt :: corrupt_ecc_deskew_mem_1 [09:08] */ 25236 #define RX_X4_ECC_CORRUPT_CORRUPT_ECC_DESKEW_MEM_1_MASK 0x0300 25237 #define RX_X4_ECC_CORRUPT_CORRUPT_ECC_DESKEW_MEM_1_ALIGN 0 25238 #define RX_X4_ECC_CORRUPT_CORRUPT_ECC_DESKEW_MEM_1_BITS 2 25239 #define RX_X4_ECC_CORRUPT_CORRUPT_ECC_DESKEW_MEM_1_SHIFT 8 25240 25241 /* RX_X4_ECC :: corrupt :: corrupt_ecc_deskew_mem_0 [07:06] */ 25242 #define RX_X4_ECC_CORRUPT_CORRUPT_ECC_DESKEW_MEM_0_MASK 0x00c0 25243 #define RX_X4_ECC_CORRUPT_CORRUPT_ECC_DESKEW_MEM_0_ALIGN 0 25244 #define RX_X4_ECC_CORRUPT_CORRUPT_ECC_DESKEW_MEM_0_BITS 2 25245 #define RX_X4_ECC_CORRUPT_CORRUPT_ECC_DESKEW_MEM_0_SHIFT 6 25246 25247 /* RX_X4_ECC :: corrupt :: corrupt_ecc_RS_FEC_buffer_blk2 [05:04] */ 25248 #define RX_X4_ECC_CORRUPT_CORRUPT_ECC_RS_FEC_BUFFER_BLK2_MASK 0x0030 25249 #define RX_X4_ECC_CORRUPT_CORRUPT_ECC_RS_FEC_BUFFER_BLK2_ALIGN 0 25250 #define RX_X4_ECC_CORRUPT_CORRUPT_ECC_RS_FEC_BUFFER_BLK2_BITS 2 25251 #define RX_X4_ECC_CORRUPT_CORRUPT_ECC_RS_FEC_BUFFER_BLK2_SHIFT 4 25252 25253 /* RX_X4_ECC :: corrupt :: corrupt_ecc_RS_FEC_buffer_blk1 [03:02] */ 25254 #define RX_X4_ECC_CORRUPT_CORRUPT_ECC_RS_FEC_BUFFER_BLK1_MASK 0x000c 25255 #define RX_X4_ECC_CORRUPT_CORRUPT_ECC_RS_FEC_BUFFER_BLK1_ALIGN 0 25256 #define RX_X4_ECC_CORRUPT_CORRUPT_ECC_RS_FEC_BUFFER_BLK1_BITS 2 25257 #define RX_X4_ECC_CORRUPT_CORRUPT_ECC_RS_FEC_BUFFER_BLK1_SHIFT 2 25258 25259 /* RX_X4_ECC :: corrupt :: corrupt_ecc_RS_FEC_buffer_blk0 [01:00] */ 25260 #define RX_X4_ECC_CORRUPT_CORRUPT_ECC_RS_FEC_BUFFER_BLK0_MASK 0x0003 25261 #define RX_X4_ECC_CORRUPT_CORRUPT_ECC_RS_FEC_BUFFER_BLK0_ALIGN 0 25262 #define RX_X4_ECC_CORRUPT_CORRUPT_ECC_RS_FEC_BUFFER_BLK0_BITS 2 25263 #define RX_X4_ECC_CORRUPT_CORRUPT_ECC_RS_FEC_BUFFER_BLK0_SHIFT 0 25264 25265 25266 /**************************************************************************** 25267 * Datatype Definitions. 25268 */ 25269 #endif /* #ifndef TEF_TMP__ */ 25270 25271 /* End of File */ 25272