sesto.c (46117B)
1 /* 2 * 3 * 4 * 5 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 6 * 7 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 8 */ 9 10 #include <phymod/phymod.h> 11 #include <phymod/phymod_system.h> 12 #include <phymod/phymod_dispatch.h> 13 #include <phymod/phymod_util.h> 14 15 #include "../tier1/sesto_address_defines.h" 16 #include "../tier1/sesto_reg_structs.h" 17 #include "../tier1/sesto_cfg_seq.h" 18 19 /** Core identify 20 * This function reads PMD Identifiers, Set is identified if 21 * sesto identified. 22 * 23 * @param core Pointer to phymod core access structure 24 * @param core_id Core ID which is supplied by interface layer 25 * @param is_identified Flag variable to return device 26 * identification status 27 * 28 * @return PHYMOD_E_NONE successful function execution 29 */ 30 int sesto_core_identify(const phymod_core_access_t* core, uint32_t core_id, uint32_t* is_identified) 31 { 32 const phymod_access_t *pm_acc = &core->access; 33 uint32_t id0 = 0, chip_id = 0; 34 uint32_t id1 = 0; 35 uint32_t rev = 0; 36 int rv = PHYMOD_E_NONE; 37 38 *is_identified = 0; 39 40 SESTO_RESET_SLICE(pm_acc, SESTO_DEV_PMA_PMD); 41 if (core_id == 0) { 42 READ_SESTO_PMA_PMD_REG(pm_acc, IEEE_PMA_PMD_BLK0_PMD_IDENTIFIER_REGISTER_0_ADR, id0); 43 READ_SESTO_PMA_PMD_REG(pm_acc, IEEE_PMA_PMD_BLK0_PMD_IDENTIFIER_REGISTER_1_ADR, id1); 44 } else { 45 id0 = (core_id >> 16) & 0xffff; 46 id1 = core_id & 0xffff; 47 } 48 if (id0 == SESTO_PMD_ID0 && id1 == SESTO_PMD_ID1) { 49 /* PHY IDs match - now check model */ 50 SESTO_IF_ERR_RETURN(sesto_get_chipid(pm_acc, &chip_id, &rev)); 51 if (chip_id == SESTO_CHIP_ID_82764 || chip_id == SESTO_CHIP_ID_82792 || 52 chip_id == SESTO_CHIP_ID_82790 || chip_id == SESTO_CHIP_ID_82796) { 53 if (rev == 0xA0) { 54 *is_identified = 1; 55 } else { 56 /* enable Broadcast */ 57 *is_identified = 0x80000001; 58 } 59 } 60 } 61 62 ERR: 63 return rv; 64 } 65 66 /** Core information 67 * This function gives the core version 68 * 69 * @param core Pointer to phymod core access structure 70 * @param info Pointer to core version 71 * 72 * @return PHYMOD_E_NONE successful function execution 73 */ 74 int sesto_core_info_get(const phymod_core_access_t* core, phymod_core_info_t* info) 75 { 76 const phymod_access_t *pm_acc = &core->access; 77 uint32_t chip_id = 0; 78 uint32_t id0 = 0; 79 uint32_t id1 = 0; 80 uint32_t rev = 0; 81 char core_name[15]="Sesto"; 82 int rv = PHYMOD_E_NONE; 83 84 SESTO_IF_ERR_RETURN(sesto_get_chipid(pm_acc, &chip_id, &rev)); 85 info->serdes_id = chip_id; 86 info->core_version = phymodCoreVersionSestoA0; 87 if (rev == 0xA0) { 88 info->core_version = phymodCoreVersionSestoA0; 89 PHYMOD_STRCAT(core_name, "A0"); 90 } else if (rev == 0xB0){ 91 info->core_version = phymodCoreVersionSestoB0; 92 PHYMOD_STRCAT(core_name, "B0"); 93 } 94 PHYMOD_STRCPY(info->name, core_name); 95 96 READ_SESTO_PMA_PMD_REG(pm_acc, IEEE_PMA_PMD_BLK0_PMD_IDENTIFIER_REGISTER_0_ADR, id0); 97 info->phy_id0 = id0; 98 READ_SESTO_PMA_PMD_REG(pm_acc, IEEE_PMA_PMD_BLK0_PMD_IDENTIFIER_REGISTER_1_ADR, id1); 99 info->phy_id1 = id1; 100 101 ERR: 102 return rv; 103 } 104 105 106 int sesto_core_lane_map_set(const phymod_core_access_t* core, const phymod_lane_map_t* lane_map) 107 { 108 109 110 /* Place your code here */ 111 112 113 return PHYMOD_E_UNAVAIL; 114 115 } 116 117 int sesto_core_lane_map_get(const phymod_core_access_t* core, phymod_lane_map_t* lane_map) 118 { 119 120 121 /* Place your code here */ 122 123 124 return PHYMOD_E_UNAVAIL; 125 126 } 127 128 /** Core Reset 129 * This function reset sesto core, it support hard and soft reset 130 * 131 * @param core Pointer to phymod core access structure 132 * @param reset_mode Represent hard/soft reset to perform 133 * @param direction Represet direction of reset. Sesto ignore this parameter 134 * 135 * @return PHYMOD_E_NONE successful function execution 136 */ 137 int sesto_core_reset_set(const phymod_core_access_t* core, phymod_reset_mode_t reset_mode, phymod_reset_direction_t direction) 138 { 139 return _sesto_core_reset_set(&core->access, reset_mode, direction); 140 141 } 142 143 int sesto_core_reset_get(const phymod_core_access_t* core, phymod_reset_mode_t reset_mode, phymod_reset_direction_t* direction) 144 { 145 146 147 /* Place your code here */ 148 149 150 return PHYMOD_E_UNAVAIL; 151 152 } 153 154 /** Get Firmware info 155 * This function get the firmware information such as master firmware version and master checksum 156 * 157 * @param core Pointer to phymod core access structure 158 * @param fw_info Represent firmware version and checksum. 159 * 160 * @return PHYMOD_E_NONE successful function execution 161 */ 162 int sesto_core_firmware_info_get(const phymod_core_access_t* core, phymod_core_firmware_info_t* fw_info) 163 { 164 int rv = PHYMOD_E_NONE; 165 166 SES_GEN_CNTRLS_FIRMWARE_VERSION_TYPE_T firmware_version; 167 SES_GEN_CNTRLS_MST_RUNNING_CHKSUM_TYPE_T mst_running_chksum; 168 169 /* Read the firmware version */ 170 READ_SESTO_PMA_PMD_REG(&core->access, SES_GEN_CNTRLS_FIRMWARE_VERSION_ADR, 171 firmware_version.data); 172 fw_info->fw_version = firmware_version.data; 173 174 READ_SESTO_PMA_PMD_REG(&core->access, 175 SES_GEN_CNTRLS_MST_RUNNING_CHKSUM_ADR, 176 mst_running_chksum.data); 177 178 fw_info->fw_crc = mst_running_chksum.data; 179 180 ERR: 181 return rv; 182 } 183 184 int sesto_phy_firmware_core_config_set(const phymod_phy_access_t* phy, phymod_firmware_core_config_t fw_config) 185 { 186 /* Place your code here */ 187 188 return PHYMOD_E_UNAVAIL; 189 } 190 191 192 int sesto_phy_firmware_core_config_get(const phymod_phy_access_t* phy, phymod_firmware_core_config_t* fw_config) 193 { 194 /* Place your code here */ 195 196 return PHYMOD_E_UNAVAIL; 197 } 198 199 200 int sesto_phy_firmware_lane_config_set(const phymod_phy_access_t* phy, phymod_firmware_lane_config_t fw_config) 201 { 202 return _sesto_firmware_lane_config_set(phy, fw_config); 203 } 204 205 206 int sesto_phy_firmware_lane_config_get(const phymod_phy_access_t* phy, phymod_firmware_lane_config_t* fw_config) 207 { 208 return _sesto_firmware_lane_config_get(phy, fw_config); 209 } 210 211 /** Restart PLL Sequecer 212 * This function is used to get restart the PLL sequencer 213 * 214 * 215 * @param core Pointer to phymod core access structure 216 * @param flags Reserved for Furtuer use 217 * @param operation Operation to perform on PLL sequencer 218 * 219 * @return PHYMOD_E_NONE successful function execution 220 */ 221 222 int sesto_core_pll_sequencer_restart(const phymod_core_access_t* core, uint32_t flags, phymod_sequencer_operation_t operation) 223 { 224 return _sesto_pll_sequencer_restart(core, operation); 225 } 226 227 228 int sesto_core_wait_event(const phymod_core_access_t* core, phymod_core_event_t event, uint32_t timeout) 229 { 230 231 232 /* Place your code here */ 233 234 235 return PHYMOD_E_UNAVAIL; 236 237 } 238 239 240 int sesto_phy_rx_restart(const phymod_phy_access_t* phy) 241 { 242 phymod_core_access_t core; 243 PHYMOD_MEMCPY(&core, phy, sizeof(phymod_core_access_t)); 244 245 return _sesto_pll_sequencer_restart(&core, phymodSeqOpRestart); 246 } 247 248 /** PHY polarity set 249 * This function is used to set the lane polarity 250 * 251 * @param phy Pointer to phymod phy access structure 252 * @param polarity Pointer to phymod_polarity_t for rx and tx 253 * 254 * @return PHYMOD_E_NONE successful function execution 255 */ 256 257 258 int sesto_phy_polarity_set(const phymod_phy_access_t* phy, const phymod_polarity_t* polarity) 259 { 260 return _sesto_tx_rx_polarity_set(phy, polarity->tx_polarity, polarity->rx_polarity); 261 } 262 263 /** PHY polarity get 264 * This function is used to get the lane polarity 265 * 266 * @param phy Pointer to phymod phy access structure 267 * @param polarity Pointer to phymod_polarity_t for rx and tx 268 * 269 * @return PHYMOD_E_NONE successful function execution 270 */ 271 272 int sesto_phy_polarity_get(const phymod_phy_access_t* phy, phymod_polarity_t* polarity) 273 { 274 return _sesto_tx_rx_polarity_get(phy, &polarity->tx_polarity, &polarity->rx_polarity); 275 } 276 277 /** Tx set 278 * This function is used to set transmitter analog parameters 279 * 280 * @param phy Pointer to phymod phy access structure 281 * @param tx Pointer to tx param structure 282 * 283 * @return PHYMOD_E_NONE successful function execution 284 */ 285 int sesto_phy_tx_set(const phymod_phy_access_t* phy, const phymod_tx_t* tx) 286 { 287 return _sesto_tx_set(phy, tx); 288 } 289 290 /** Tx get 291 * This function is used to get transmitter analog parameters 292 * 293 * @param phy Pointer to phymod phy access structure 294 * @param tx Pointer to tx param structure 295 * 296 * @return PHYMOD_E_NONE successful function execution 297 */ 298 int sesto_phy_tx_get(const phymod_phy_access_t* phy, phymod_tx_t* tx) 299 { 300 return _sesto_tx_get(phy, tx); 301 } 302 303 304 305 306 int sesto_phy_media_type_tx_get(const phymod_phy_access_t* phy, phymod_media_typed_t media, phymod_tx_t* tx) 307 { 308 phymod_phy_access_t phy_copy; 309 310 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phymod_phy_access_t)); 311 /* system side interface bit shift */ 312 phy_copy.port_loc = phymodPortLocSys; 313 314 return _sesto_tx_get(&phy_copy, tx); 315 } 316 317 318 int sesto_phy_tx_override_set(const phymod_phy_access_t* phy, const phymod_tx_override_t* tx_override) 319 { 320 321 322 /* Place your code here */ 323 324 325 return PHYMOD_E_UNAVAIL; 326 327 } 328 329 int sesto_phy_tx_override_get(const phymod_phy_access_t* phy, phymod_tx_override_t* tx_override) 330 { 331 332 333 /* Place your code here */ 334 335 336 return PHYMOD_E_UNAVAIL; 337 338 } 339 340 /** Rx set 341 * This function is used to set receiver analog parameters 342 * 343 * @param phy Pointer to phymod phy access structure 344 * @param rx Pointer to rx param structure 345 * 346 * @return PHYMOD_E_NONE successful function execution 347 */ 348 int sesto_phy_rx_set(const phymod_phy_access_t* phy, const phymod_rx_t* rx) 349 { 350 return _sesto_rx_set(phy, rx); 351 } 352 353 /** Rx get 354 * This function is used to get receiver analog parameters 355 * 356 * @param phy Pointer to phymod phy access structure 357 * @param rx Pointer to rx param structure 358 * 359 * @return PHYMOD_E_NONE successful function execution 360 */ 361 int sesto_phy_rx_get(const phymod_phy_access_t* phy, phymod_rx_t* rx) 362 { 363 return _sesto_rx_get(phy, rx); 364 } 365 366 /** PHY Rx adaptation resume 367 * This function is used to perform PHY reset 368 * 369 * @param phy Pointer to phymod phy access structure 370 * 371 * @return PHYMOD_E_NONE successful function execution 372 */ 373 int sesto_phy_rx_adaptation_resume(const phymod_phy_access_t* phy) 374 { 375 return _sesto_rx_adaptation_resume(phy); 376 } 377 378 379 /** Tx Rx Phy Reset Set 380 * This function is used to set TX/RX Phy Reset options 381 * 382 * @param phy Pointer to phymod phy access structure 383 * @param reset Pointer to phymod phy reset structure 384 * to set TX Reset and RX Reset 385 * 386 * @return PHYMOD_E_NONE successful function execution 387 */ 388 389 int sesto_phy_reset_set(const phymod_phy_access_t* phy, const phymod_phy_reset_t* reset) 390 { 391 return _sesto_phy_reset_set(phy, reset); 392 } 393 /** Tx Rx Phy Reset Get 394 * This function is used to get TX/RX Phy Reset options 395 * 396 * @param phy Pointer to phymod phy access structure 397 * @param reset Pointer to phymod phy reset structure 398 * to get TX Reset and RX Reset 399 * 400 * @return PHYMOD_E_NONE successful function execution 401 */ 402 int sesto_phy_reset_get(const phymod_phy_access_t* phy, phymod_phy_reset_t* reset) 403 { 404 return _sesto_phy_reset_get(phy, reset); 405 } 406 407 /** Tx Rx power Set 408 * This function is used to set TX/RX power options 409 * 410 * @param phy Pointer to phymod phy access structure 411 * @param power Pointer to phymod phy power structure 412 * to set TX Power and RX Power 413 * 414 * @return PHYMOD_E_NONE successful function execution 415 */ 416 417 int sesto_phy_power_set(const phymod_phy_access_t* phy, const phymod_phy_power_t* power) 418 { 419 int rv = PHYMOD_E_NONE; 420 421 SESTO_IF_ERR_RETURN(_sesto_tx_power_set(phy, power->tx)); 422 SESTO_IF_ERR_RETURN(_sesto_rx_power_set(phy, power->rx)); 423 424 ERR: 425 return rv; 426 } 427 428 /** Tx Rx power Get 429 * This function is used to get TX/RX power options 430 * 431 * @param phy Pointer to phymod phy access structure 432 * @param power Pointer to phymod phy power structure 433 * to get TX Power and RX Power 434 * 435 * @return PHYMOD_E_NONE successful function execution 436 */ 437 438 int sesto_phy_power_get(const phymod_phy_access_t* phy, phymod_phy_power_t* power) 439 { 440 return _sesto_tx_rx_power_get(phy, power); 441 } 442 443 /** Tx lane control set 444 * This function is used to set the lane control for example 445 * resetting the traffic 446 * 447 * @param phy Pointer to phymod phy access structure 448 * @param tx_control Tx lane control 449 * 0 - Traffic disable, currently not available 450 * 1 - Traffic enable, currently not available 451 * 2 - Tx Datapath reset 452 * 3 - Tx Squelch on 453 * 4 - Tx Squelch off 454 * 455 * @return PHYMOD_E_NONE successful function execution 456 */ 457 458 int sesto_phy_tx_lane_control_set(const phymod_phy_access_t* phy, phymod_phy_tx_lane_control_t tx_control) 459 { 460 return _sesto_tx_lane_control_set(phy, tx_control); 461 } 462 463 /** Tx lane control get 464 * This function is used to get the lane control for example 465 * resetting the traffic 466 * 467 * @param phy Pointer to phymod phy access structure 468 * @param tx_control 469 * 0 - Traffic disable, currently not available 470 * 1 - Traffic enable, currently not available 471 * 2 - Tx Datapath reset 472 * 3 - Tx Squelch on 473 * 4 - Tx Squelch off 474 * 475 * Return value of tx_control is enable or disable of specified lane control option 476 * 477 * @return PHYMOD_E_NONE successful function execution 478 */ 479 480 481 int sesto_phy_tx_lane_control_get(const phymod_phy_access_t* phy, phymod_phy_tx_lane_control_t* tx_control) 482 { 483 return _sesto_tx_lane_control_get(phy, tx_control); 484 } 485 486 /** Rx lane control set 487 * This function is used to set the lane control for example 488 * resetting the traffic 489 * 490 * @param phy Pointer to phymod phy access structure 491 * @param rx_control Rx lane control 492 * 0 - Rx datapath reset 493 * 1 - Rx squelch on 494 * 2 - Rx squelch off 495 * 496 * @return PHYMOD_E_NONE successful function execution 497 */ 498 int sesto_phy_rx_lane_control_set(const phymod_phy_access_t* phy, phymod_phy_rx_lane_control_t rx_control) 499 { 500 return _sesto_rx_lane_control_set(phy, rx_control); 501 } 502 /** Rx lane control get 503 * This function is used to set the lane control for example 504 * resetting the traffic 505 * 506 * @param phy Pointer to phymod phy access structure 507 * @param rx_control Rx lane control 508 * 0 - Rx datapath reset 509 * 1 - Rx squelch on 510 * 2 - Rx squelch off 511 * 512 * Return value of tx_control is enable or disable of specified lane control option 513 * 514 * @return PHYMOD_E_NONE successful function execution 515 */ 516 517 int sesto_phy_rx_lane_control_get(const phymod_phy_access_t* phy, phymod_phy_rx_lane_control_t* rx_control) 518 { 519 return _sesto_rx_lane_control_get(phy, rx_control); 520 } 521 522 /** Set interface config 523 * This function sets interface configuration (interface, speed, frequency of 524 * operation, PT mode, BCM84793 etc). 525 * This is requried to put the chip into specific mode specified 526 * 527 * NOTE: Default system side interface type will be IEEE mode and speed is compatible with lane side configured speed. 528 * Ex: User configured 40G speed with interface type KR4 on lane side then system side speed is 40G and interface type is IEEE mode. 529 * 530 * @param phy Pointer to phymod phy access structure 531 * @param flags Reserved for future use 532 * @param config Interface config structure where user specifies 533 * - Interface Type 534 * - Speed 535 * - Frequency. 536 * - device_aux_modes : a structure that have auxilary mode details 537 * -> pass_thru : To enable repeater on 10/40G mode of operation 538 * -> gearbox_100g_inverse_mode : Applicable only for 100G mode, 25G lanes on system side and 539 * 10G lanes on line side 540 * -> BCM84793_capablity : To enable BCM84793 compatible on lanes 541 * -> passthru_sys_side_core : When pass through is enabled user are allowed to configure system side 542 * core i.e. 25G lanes or 10G lanes 543 * -> reserved: Only for future use 544 * 545 * @return PHYMOD_E_NONE successful function execution 546 */ 547 548 int sesto_phy_interface_config_set(const phymod_phy_access_t* phy, uint32_t flags, const phymod_phy_inf_config_t* config) 549 { 550 uint16_t data1 = 0, retry_cnt = SESTO_FW_DLOAD_RETRY_CNT; 551 uint32_t chip_id = 0, rev = 0; 552 phymod_phy_inf_config_t cfg; 553 SESTO_DEVICE_AUX_MODE_T *aux_mode; 554 uint16_t lane = 0, lane_mask = 0; 555 int rv = PHYMOD_E_NONE; 556 557 PHYMOD_MEMSET(&cfg, 0, sizeof(phymod_phy_inf_config_t)); 558 PHYMOD_MEMCPY(&cfg, config, sizeof(phymod_phy_inf_config_t)); 559 cfg.device_aux_modes = PHYMOD_MALLOC(sizeof(SESTO_DEVICE_AUX_MODE_T), "sesto_device_aux_mode"); 560 aux_mode = (SESTO_DEVICE_AUX_MODE_T*) cfg.device_aux_modes; 561 if (aux_mode == NULL) { 562 PHYMOD_DEBUG_VERBOSE(("AUX MODE MEM NOT ALLOC\n")); 563 return PHYMOD_E_PARAM; 564 } 565 566 PHYMOD_MEMSET(aux_mode, 0, sizeof(SESTO_DEVICE_AUX_MODE_T)); 567 /* Filling device aux mode */ 568 SESTO_IF_ERR_RETURN(sesto_get_chipid(&phy->access, &chip_id, &rev)); 569 if (chip_id != SESTO_CHIP_ID_82764) { 570 aux_mode->passthru_sys_side_core = PHYMOD_INTF_CONFIG_PORT_PHY_MODE_REVERSE_GET(phy) ? SESTO_FALCON_CORE: SESTO_MERLIN_CORE; 571 } else { 572 aux_mode->passthru_sys_side_core = PHYMOD_INTF_CONFIG_PORT_PHY_MODE_REVERSE_GET(phy) ? SESTO_MERLIN_CORE: SESTO_FALCON_CORE; 573 } 574 aux_mode->BCM84793_capablity = PHYMOD_INTF_CONFIG_PHY_PIN_COMPATIBILITY_ENABLE_GET(phy); 575 aux_mode->pass_thru = (!PHYMOD_INTF_CONFIG_PHY_GEARBOX_ENABLE_GET(phy)); 576 577 if ((config->data_rate == SESTO_SPD_1G) && (aux_mode->passthru_sys_side_core != SESTO_FALCON_CORE)) { 578 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_INIT, 579 (_PHYMOD_MSG("ERR:: 1G datarate is supported only if Merlin is on line side\n"))); 580 } 581 582 SESTO_IF_ERR_RETURN( 583 _sesto_phy_interface_config_set(phy, flags, &cfg)); 584 585 /* Enable FW After configuring mode */ 586 SESTO_IF_ERR_RETURN( 587 _sesto_fw_enable(&phy->access, SESTO_ENABLE)); 588 do { 589 SESTO_CHIP_FIELD_READ(&phy->access, SES_GEN_CNTRLS_FIRMWARE_ENABLE, fw_enable_val, data1); 590 591 PHYMOD_DEBUG_VERBOSE(("FW Clear:%d\n",data1)); 592 retry_cnt--; 593 } while((data1 != 0) && (retry_cnt)); 594 if (retry_cnt == 0) { 595 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_INIT, 596 (_PHYMOD_MSG("WARN:: FW Enable not cleared\n"))); 597 } 598 599 /* For 1G support */ 600 lane_mask = PHYMOD_ACC_LANE_MASK(&phy->access); 601 if (config->data_rate == SESTO_SPD_1G) { 602 for (lane = 0; lane < SESTO_MAX_MERLIN_LANE; lane ++) { 603 if (lane_mask & (1 << lane)) { 604 SESTO_IF_ERR_RETURN(_sesto_set_slice_reg (&phy->access, 605 SESTO_SLICE_UNICAST, SESTO_MERLIN_CORE, SESTO_DEV_PMA_PMD, 0, lane)); 606 /* Merlin specific register to disable ucode monitor controls */ 607 WRITE_SESTO_PMA_PMD_REG(&phy->access, 0xD00E, 0x000D); 608 WRITE_SESTO_PMA_PMD_REG(&phy->access, 0xD00D, 0x7F07); 609 WRITE_SESTO_PMA_PMD_REG(&phy->access, 0xD001, 0x215); 610 WRITE_SESTO_PMA_PMD_REG(&phy->access, 0xD004, 0x901); 611 } 612 } 613 } 614 615 ERR: 616 SESTO_RESET_SLICE(&phy->access, SESTO_DEV_PMA_PMD); 617 PHYMOD_FREE(cfg.device_aux_modes); 618 619 return rv; 620 } 621 622 /** Get interface config 623 * This function gets interface configuration (interface, speed, frequency of 624 * operation, PT mode, BCM84793 etc). 625 * 626 * NOTE: Default system side interface type will be IEEE mode and speed is compatible with lane side configured speed. 627 * Ex: User configured 40G speed with interface type KR4 on lane side then system side speed is 40G and interface type is IEEE mode. 628 * 629 * @param phy Pointer to phymod phy access structure 630 * @param flags Reserved for future use 631 * @param config Gets Interface config such as, 632 * - Interface Type 633 * - Speed 634 * - Frequency. 635 * - device_aux_modes : a structure that have auxilary mode details 636 * -> pass_thru : To enable repeater on 10/40G mode of operation 637 * -> gearbox_100g_inverse_mode : Applicable only for 100G mode, 25G lanes on system side and 638 * 10G lanes on line side 639 * -> BCM84793_capablity : To enable BCM84793 compatible on lanes 640 * -> passthru_sys_side_core : When pass through is enabled user are allowed to configure system side 641 * core i.e. 25G lanes or 10G lanes 642 * -> reserved: Only for future use 643 * 644 * @return PHYMOD_E_NONE successful function execution 645 */ 646 647 int sesto_phy_interface_config_get(const phymod_phy_access_t* phy, uint32_t flags, uint32_t ref_clock, phymod_phy_inf_config_t* config) 648 { 649 SESTO_DEVICE_AUX_MODE_T *aux_mode; 650 int rv = PHYMOD_E_NONE; 651 652 config->device_aux_modes = PHYMOD_MALLOC(sizeof(SESTO_DEVICE_AUX_MODE_T), "sesto_device_aux_mode"); 653 aux_mode = (SESTO_DEVICE_AUX_MODE_T*) config->device_aux_modes; 654 if (aux_mode == NULL) { 655 PHYMOD_DEBUG_VERBOSE(("AUX MODE MEM NOT ALLOC\n")); 656 return PHYMOD_E_PARAM; 657 } 658 PHYMOD_MEMSET(aux_mode, 0, sizeof(SESTO_DEVICE_AUX_MODE_T)); 659 660 SESTO_IF_ERR_RETURN ( 661 _sesto_phy_interface_config_get(phy, flags, config)); 662 663 ERR: 664 PHYMOD_FREE(config->device_aux_modes); 665 666 return rv; 667 } 668 669 /** PHY CL73 ability Set 670 * This function is used to set the CL73 ability of a lane 671 * 672 * @param phy Pointer to phymod phy access structure 673 * @param an_ability Pointer to the ability of cl73 674 * 675 * @return PHYMOD_E_NONE successful function execution 676 */ 677 678 int sesto_phy_autoneg_ability_set(const phymod_phy_access_t* phy, const phymod_autoneg_ability_t* an_ability) 679 { 680 sesto_an_ability_t value; 681 int rv = PHYMOD_E_NONE; 682 683 PHYMOD_MEMSET(&value, 0, sizeof(value)); 684 value.cl73_adv.an_fec = an_ability->an_fec; 685 value.cl73_adv.an_cl72 = an_ability->an_cl72; 686 value.an_master_lane = an_ability->an_master_lane; 687 /*check if sgmii or not */ 688 if (PHYMOD_AN_CAP_SGMII_GET(an_ability)){ 689 return rv; 690 } 691 692 /*next check pause */ 693 if (PHYMOD_AN_CAP_SYMM_PAUSE_GET(an_ability)) { 694 value.cl73_adv.an_pause = SESTO_SYMM_PAUSE; 695 } else if (PHYMOD_AN_CAP_ASYM_PAUSE_GET(an_ability)) { 696 value.cl73_adv.an_pause = SESTO_ASYM_PAUSE; 697 } else { 698 value.cl73_adv.an_pause = SESTO_NO_PAUSE; 699 } 700 701 /*check cl73 and cl73 bam ability */ 702 if (PHYMOD_AN_CAP_1G_KX_GET(an_ability->an_cap)) { 703 value.cl73_adv.an_base_speed = SESTO_CL73_1000BASE_KX; 704 } else if (PHYMOD_AN_CAP_10G_KX4_GET(an_ability->an_cap)) { 705 value.cl73_adv.an_base_speed = SESTO_CL73_10GBASE_KX4; 706 } else if (PHYMOD_AN_CAP_10G_KR_GET(an_ability->an_cap)) { 707 value.cl73_adv.an_base_speed = SESTO_CL73_10GBASE_KR; 708 } else if (PHYMOD_AN_CAP_40G_KR4_GET(an_ability->an_cap)) { 709 value.cl73_adv.an_base_speed = SESTO_CL73_40GBASE_KR4; 710 } else if (PHYMOD_AN_CAP_40G_CR4_GET(an_ability->an_cap)) { 711 value.cl73_adv.an_base_speed = SESTO_CL73_40GBASE_CR4; 712 } else if (PHYMOD_AN_CAP_100G_CR4_GET(an_ability->an_cap)) { 713 value.cl73_adv.an_base_speed = SESTO_CL73_100GBASE_CR4; 714 } else if (PHYMOD_AN_CAP_100G_KR4_GET(an_ability->an_cap)) { 715 value.cl73_adv.an_base_speed = SESTO_CL73_100GBASE_KR4; 716 } else if (an_ability->an_cap == 0) { 717 return rv; 718 } else { 719 return PHYMOD_E_PARAM; 720 } 721 722 SESTO_IF_ERR_RETURN 723 (_sesto_autoneg_ability_set(phy, &value)); 724 725 ERR: 726 return rv; 727 } 728 729 /** PHY CL73 remote ability get 730 * This function is used to get the CL73 remote ability of a lane 731 * 732 * @param phy Pointer to phymod phy access structure 733 * @param an_ability Pointer to the ability of cl73 734 * 735 * @return PHYMOD_E_NONE successful function execution 736 */ 737 int sesto_phy_autoneg_remote_ability_get(const phymod_phy_access_t* phy, phymod_autoneg_ability_t* an_ability_get) 738 { 739 int rv = PHYMOD_E_NONE; 740 741 SESTO_IF_ERR_RETURN( 742 _sesto_autoneg_remote_ability_get(phy, an_ability_get)); 743 744 ERR: 745 return rv; 746 } 747 748 /** PHY CL73 ability get 749 * This function is used to get the CL73 ability of a lane 750 * 751 * @param phy Pointer to phymod phy access structure 752 * @param an_ability Pointer to the ability of cl73 753 * 754 * @return PHYMOD_E_NONE successful function execution 755 */ 756 757 int sesto_phy_autoneg_ability_get(const phymod_phy_access_t* phy, phymod_autoneg_ability_t* an_ability_get_type) 758 { 759 sesto_an_ability_t value; 760 int rv = PHYMOD_E_NONE; 761 762 SESTO_IF_ERR_RETURN( 763 _sesto_autoneg_ability_get(phy, &value)); 764 765 an_ability_get_type->an_fec = value.cl73_adv.an_fec; 766 switch (value.cl73_adv.an_pause) { 767 case SESTO_ASYM_PAUSE: 768 PHYMOD_AN_CAP_ASYM_PAUSE_SET(an_ability_get_type); 769 break; 770 case SESTO_SYMM_PAUSE: 771 PHYMOD_AN_CAP_SYMM_PAUSE_SET(an_ability_get_type); 772 break; 773 default: 774 break; 775 } 776 777 /*first check cl73 ability*/ 778 switch (value.cl73_adv.an_base_speed) { 779 case SESTO_CL73_40GBASE_CR4: 780 PHYMOD_AN_CAP_40G_CR4_SET(an_ability_get_type->an_cap); 781 break; 782 case SESTO_CL73_40GBASE_KR4: 783 PHYMOD_AN_CAP_40G_KR4_SET(an_ability_get_type->an_cap); 784 break; 785 case SESTO_CL73_100GBASE_CR4: 786 PHYMOD_AN_CAP_100G_CR4_SET(an_ability_get_type->an_cap); 787 break; 788 case SESTO_CL73_100GBASE_KR4: 789 PHYMOD_AN_CAP_100G_KR4_SET(an_ability_get_type->an_cap); 790 break; 791 default: 792 break; 793 } 794 795 ERR: 796 return rv; 797 } 798 799 /** PHY enable/Disable CL73 800 * This function is used to enable/disable CL73 of a lane 801 * 802 * @param phy Pointer to phymod phy access structure 803 * @param an Pointer to the AN control 804 * 805 * @return PHYMOD_E_NONE successful function execution 806 */ 807 808 int sesto_phy_autoneg_set(const phymod_phy_access_t* phy, const phymod_autoneg_control_t* an) 809 { 810 return (_sesto_autoneg_set(phy, an)); 811 } 812 813 /** Get CL73 completion state 814 * This function is used get CL73 completion state of a lane 815 * 816 * @param phy Pointer to phymod phy access structure 817 * @param an Pointer to the AN control 818 * @param an_done Pointer to the AN completion state 819 * 820 * @return PHYMOD_E_NONE successful function execution 821 */ 822 823 int sesto_phy_autoneg_get(const phymod_phy_access_t* phy, phymod_autoneg_control_t* an, uint32_t* an_done) 824 { 825 return (_sesto_autoneg_get(phy, an, an_done)); 826 } 827 828 829 int sesto_phy_autoneg_status_get(const phymod_phy_access_t* phy, phymod_autoneg_status_t* status) 830 { 831 832 833 /* Place your code here */ 834 835 836 return PHYMOD_E_UNAVAIL; 837 838 } 839 840 /** Sesto core initialization 841 * This function initialize the sesto core by downlaoding the firmware. 842 * 843 * @param core Pointer to phymod core access structure 844 * @param init_config Init configuration specified by user 845 * @param core_status PMD status read from PHY chip 846 * 847 * @return PHYMOD_E_NONE successful function execution 848 */ 849 850 int sesto_core_init(const phymod_core_access_t* core, const phymod_core_init_config_t* init_config, const phymod_core_status_t* core_status) 851 { 852 uint32_t chip_id = 0, rev = 0; 853 uint8_t sys_side_core = 0; 854 int rv = PHYMOD_E_NONE; 855 856 SESTO_IF_ERR_RETURN( 857 _sesto_core_init(core, init_config)); 858 859 SESTO_IF_ERR_RETURN(sesto_get_chipid(&core->access, &chip_id, &rev)); 860 861 if (chip_id != SESTO_CHIP_ID_82764) { 862 sys_side_core = PHYMOD_INTF_CONFIG_PORT_PHY_MODE_REVERSE_GET(core) ? SESTO_FALCON_CORE: SESTO_MERLIN_CORE; 863 } else { 864 sys_side_core = PHYMOD_INTF_CONFIG_PORT_PHY_MODE_REVERSE_GET(core) ? SESTO_MERLIN_CORE: SESTO_FALCON_CORE; 865 } 866 /* Added chip restriction fix: 867 The line side core selection(whether 10G or 20G/25G is the line side) 868 should be made first with the Mode Config API before enabling any other configuration.*/ 869 SESTO_CHIP_FIELD_WRITE(&core->access, DP_SESTO_MODE_CTRL0, mode_falcon_line, !sys_side_core); 870 871 ERR: 872 return rv; 873 874 } 875 876 877 int sesto_phy_init(const phymod_phy_access_t* phy, const phymod_phy_init_config_t* init_config) 878 { 879 int rv = PHYMOD_E_NONE; 880 phymod_phy_access_t phy_copy; 881 882 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phymod_phy_access_t)); 883 884 SESTO_IF_ERR_RETURN 885 (sesto_phy_interface_config_set(phy, 0 /*flags*/, &init_config->interface)); 886 SESTO_IF_ERR_RETURN 887 (_sesto_core_cfg_polarity_set(phy, init_config->polarity.tx_polarity, init_config->polarity.rx_polarity)); 888 SESTO_IF_ERR_RETURN 889 (_sesto_phy_repeater_mode_set(phy, init_config->op_mode)); 890 SESTO_IF_ERR_RETURN 891 (_sesto_core_cfg_tx_set(phy,init_config->tx)); 892 /* Looback disable during phy_init to be defult */ 893 SESTO_IF_ERR_RETURN 894 (_sesto_loopback_set(phy, phymodLoopbackGlobalPMD, SESTO_DISABLE)); 895 SESTO_IF_ERR_RETURN 896 (_sesto_loopback_set(phy, phymodLoopbackRemotePMD, SESTO_DISABLE)); 897 /* system side interface bit shift */ 898 phy_copy.port_loc = phymodPortLocSys; 899 SESTO_IF_ERR_RETURN 900 (_sesto_loopback_set(&phy_copy, phymodLoopbackGlobalPMD, SESTO_DISABLE)); 901 SESTO_IF_ERR_RETURN 902 (_sesto_loopback_set(&phy_copy, phymodLoopbackRemotePMD, SESTO_DISABLE)); 903 904 ERR: 905 return rv; 906 } 907 908 /** Set loopback 909 * This function is used to set a particular loopback mode 910 * 911 * @param phy Pointer to phymod phy access structure 912 * @param loopback Type of loopback 913 * 0 - Global loopback 914 * 1 - Global PMD loopback 915 * 2 - Remote PMD loopback 916 * 3 - Remote PCS loopback 917 * 4 - Digital PMD loopback 918 * @enable Enable or disable 919 * 0 - disable 920 * 1 - enable 921 * 922 * @return PHYMOD_E_NONE successful function execution 923 */ 924 int sesto_phy_loopback_set(const phymod_phy_access_t* phy, phymod_loopback_mode_t loopback, uint32_t enable) 925 { 926 return _sesto_loopback_set(phy, loopback, enable); 927 } 928 929 /** Get loopback 930 * This function is used to get the status of a particular loopback mode 931 * whether or not enabled 932 * 933 * @param phy Pointer to phymod phy access structure 934 * @param loopback Type of loopback 935 * 0 - Global loopback 936 * 1 - Global PMD loopback 937 * 2 - Remote PMD loopback 938 * 3 - Remote PCS loopback 939 * 4 - Digital PMD loopback 940 * @enable Enable or disable 941 * 0 - disable 942 * 1 - enable 943 * 944 * @return PHYMOD_E_NONE successful function execution 945 */ 946 int sesto_phy_loopback_get(const phymod_phy_access_t* phy, phymod_loopback_mode_t loopback, uint32_t* enable) 947 { 948 return _sesto_loopback_get(phy, loopback, enable); 949 } 950 /** Get PHY RX PMD link status 951 * This function retrieves RX PMD lock status of sesto 952 * 953 * @param phy Pointer to phymod phy access structure 954 * @param rx_pmd_locked Rx PMD Link status retrieved from Sesto 955 * 956 * @return PHYMOD_E_NONE successful function execution 957 */ 958 959 int sesto_phy_rx_pmd_locked_get(const phymod_phy_access_t* phy, uint32_t* rx_pmd_locked) 960 { 961 return (_sesto_rx_pmd_lock_get(phy, rx_pmd_locked)); 962 } 963 964 /** Get PCS link status 965 * This function retrieves PCS link status of sesto when PCS Monitor is enabled, 966 * This function return PMD lock when PCS monitor is disabled. 967 * 968 * @param phy Pointer to phymod phy access structure 969 * @param link_status Retrives PCS Link of Sesto 970 * 971 * @return PHYMOD_E_NONE successful function execution 972 */ 973 974 int sesto_phy_link_status_get(const phymod_phy_access_t* phy, uint32_t* link_status) 975 { 976 return _sesto_phy_pcs_link_get(phy, link_status); 977 } 978 979 /** Read Register 980 * This function read user specified register based on the specified Device type 981 * 982 * @param phy Pointer to phymod phy access structure. 983 * @param reg_addr Sesto register address 984 * @param val Output parameter, represents the value of address specified 985 * 986 * @return PHYMOD_E_NONE successful function execution 987 */ 988 int sesto_phy_reg_read(const phymod_phy_access_t* phy, uint32_t reg_addr, uint32_t* val) 989 { 990 uint16_t dev_add = 0; 991 int rv = PHYMOD_E_NONE; 992 993 dev_add = (phy->access.devad) ? phy->access.devad : SESTO_DEV_PMA_PMD; 994 995 if (dev_add == SESTO_DEV_PMA_PMD) { 996 READ_SESTO_PMA_PMD_REG(&phy->access, reg_addr, *val); 997 } else { 998 READ_SESTO_AN_REG(&phy->access, reg_addr, *val); 999 } 1000 1001 ERR: 1002 return rv; 1003 } 1004 1005 /** Write Register 1006 * This function write user specified value to the specified address 1007 * based on the specified Device type 1008 * 1009 * @param phy Pointer to phymod phy access structure. 1010 * @param reg_addr Sesto register address 1011 * @param val Represents the value to be written 1012 * 1013 * @return PHYMOD_E_NONE successful function execution 1014 */ 1015 int sesto_phy_reg_write(const phymod_phy_access_t* phy, uint32_t reg_addr, uint32_t val) 1016 { 1017 uint16_t dev_add = 0; 1018 int rv = PHYMOD_E_NONE; 1019 1020 dev_add = (phy->access.devad) ? phy->access.devad : SESTO_DEV_PMA_PMD; 1021 PHYMOD_DEBUG_VERBOSE(("WRITE reg:%x data:%x\n", reg_addr, val)); 1022 if (dev_add == SESTO_DEV_PMA_PMD) { 1023 WRITE_SESTO_PMA_PMD_REG(&phy->access, reg_addr, val); 1024 } else { 1025 WRITE_SESTO_AN_REG(&phy->access, reg_addr, val); 1026 } 1027 1028 ERR: 1029 return rv; 1030 } 1031 1032 /** Retrives Revision 1033 * This function retrives sesto revision ID 1034 * 1035 * @param phy Pointer to phymod phy access structure. 1036 * @param rev_id Output parameter, Represents the revision ID of sesto. 1037 * 1038 * @return PHYMOD_E_NONE successful function execution 1039 */ 1040 int sesto_phy_rev_id(const phymod_phy_access_t* phy, uint32_t *rev_id) 1041 { 1042 uint32_t chip_id = 0; 1043 int rv = PHYMOD_E_NONE; 1044 1045 SESTO_IF_ERR_RETURN ( 1046 sesto_get_chipid(&phy->access, &chip_id, rev_id)); 1047 1048 PHYMOD_DEBUG_VERBOSE(("CHIPID : 0x%x\n", chip_id)); 1049 1050 ERR: 1051 return rv; 1052 } 1053 1054 /** Set CL72 1055 * This function is used to enable/disable forced Tx training 1056 * 1057 * @param phy Pointer to phymod phy access structure 1058 * @param enable enable / disable force Tx training 1059 * 1 - enable 1060 * 0 - disable 1061 * 1062 * @return PHYMOD_E_NONE successful function execution 1063 */ 1064 int sesto_phy_cl72_set(const phymod_phy_access_t* phy, uint32_t enable) 1065 { 1066 return _sesto_force_tx_training_set(phy, enable); 1067 } 1068 1069 1070 /** Get CL72 1071 * This function is used to get the status whether Tx training is enabled or disabled 1072 * 1073 * @param phy Pointer to phymod phy access structure 1074 * @param enable enable or disable 1075 * 1 - enable 1076 * 0 - disable 1077 * 1078 * @return PHYMOD_E_NONE successful function execution 1079 */ 1080 int sesto_phy_cl72_get(const phymod_phy_access_t* phy, uint32_t *enable) 1081 { 1082 return _sesto_force_tx_training_get(phy, enable); 1083 } 1084 1085 /** Get CL72 status 1086 * This function is used to get the status of Tx training 1087 * 1088 * @param phy Pointer to phymod phy access structure 1089 * @param status CL72 Training status 1090 * 1091 * @return PHYMOD_E_NONE successful function execution 1092 */ 1093 int sesto_phy_cl72_status_get(const phymod_phy_access_t* phy, phymod_cl72_status_t* status) 1094 { 1095 return _sesto_force_tx_training_status_get(phy, status); 1096 } 1097 1098 /** Interrupt status get 1099 * This function is used to check whether or not particualr interrupt is pending 1100 * 1101 * @param phy Pointer to phymod phy access structure 1102 * 1103 * @param intr_status Pending status 1104 * 1 - Pending 1105 * 0 - Serviced 1106 * 1107 * @return PHYMOD_E_NONE successful function execution 1108 */ 1109 int sesto_phy_intr_status_get(const phymod_phy_access_t *phy, uint32_t* intr_status) 1110 { 1111 uint32_t intr_index = 0; 1112 uint32_t value = 0; 1113 int rv = PHYMOD_E_NONE; 1114 *intr_status = 0; 1115 1116 for (intr_index = 0; intr_index < SESTO_MAX_INTRS_SUPPORT; intr_index ++) { 1117 SESTO_IF_ERR_RETURN( 1118 _sesto_ext_intr_status_get(phy, (0x1 << intr_index), &value)); 1119 if (value) { 1120 *intr_status |= (0x1 << intr_index); 1121 } 1122 } 1123 ERR: 1124 return rv; 1125 } 1126 /** Interrupt enable set 1127 * This function is used to enable or disable particular interrupt 1128 * 1129 * @param phy Pointer to phymod phy access structure 1130 * 1131 * @param enable Enable or disable 1132 * 1 - enable 1133 * 0 - disable 1134 * 1135 * @return PHYMOD_E_NONE successful function execution 1136 */ 1137 int sesto_phy_intr_enable_set(const phymod_phy_access_t *phy, uint32_t enable) 1138 { 1139 uint32_t intr_index = 0; 1140 int rv = PHYMOD_E_NONE; 1141 1142 for (intr_index = 0; intr_index < SESTO_MAX_INTRS_SUPPORT; intr_index ++) { 1143 if (enable & (0x1 << intr_index)) { 1144 SESTO_IF_ERR_RETURN(_sesto_ext_intr_enable_set(phy, (0x1 << intr_index), 1)); 1145 } else { 1146 SESTO_IF_ERR_RETURN(_sesto_ext_intr_enable_set(phy, (0x1 << intr_index), 0)); 1147 } 1148 } 1149 ERR: 1150 return rv; 1151 } 1152 /** Interrupt enable get 1153 * This function is used to check whether or not particular interrupt is enabled 1154 * 1155 * @param phy Pointer to phymod phy access structure 1156 * 1157 * @param enable Enable or disable 1158 * 1 - enable 1159 * 0 - disable 1160 * 1161 * @return PHYMOD_E_NONE successful function execution 1162 */ 1163 int sesto_phy_intr_enable_get(const phymod_phy_access_t *phy, uint32_t* enable) 1164 { 1165 uint32_t intr_index = 0; 1166 uint32_t value = 0; 1167 int rv = PHYMOD_E_NONE; 1168 1169 *enable = 0; 1170 for (intr_index = 0; intr_index < SESTO_MAX_INTRS_SUPPORT; intr_index ++) { 1171 SESTO_IF_ERR_RETURN( 1172 _sesto_ext_intr_enable_get(phy, (0x1 << intr_index), &value)); 1173 if (value) { 1174 *enable |= (0x1 << intr_index); 1175 } 1176 } 1177 ERR: 1178 return rv; 1179 } 1180 /** Interrupt status clear 1181 * This function is used for clearing interrupt status 1182 * 1183 * @param phy Pointer to phymod phy access structure 1184 * 1185 * @return PHYMOD_E_NONE successful function execution 1186 */ 1187 int sesto_phy_intr_status_clear(const phymod_phy_access_t *phy, uint32_t intr_clear) 1188 { 1189 uint32_t intr_index = 0; 1190 int rv = PHYMOD_E_NONE; 1191 1192 for (intr_index = 0; intr_index < SESTO_MAX_INTRS_SUPPORT; intr_index ++) { 1193 if (intr_clear & (0x1 << intr_index)) { 1194 SESTO_IF_ERR_RETURN( 1195 _sesto_ext_intr_status_clear(phy, (0x1 << intr_index))); 1196 } 1197 } 1198 ERR: 1199 return rv; 1200 } 1201 1202 /** PHY status dump 1203 * This function is used to display status dump of a core and for given lane 1204 * 1205 * @param phy Pointer to phymod phy access structure 1206 * 1207 * @return PHYMOD_E_NONE successful function execution 1208 */ 1209 int sesto_phy_status_dump(const phymod_phy_access_t* phy) 1210 { 1211 return _sesto_phy_status_dump(phy); 1212 } 1213 1214 /** FEC enable set 1215 * This function is used to enable the FEC 1216 * 1217 * @param phy Pointer to phymod phy access structure 1218 * @param enable enable or disable 1219 * 1 - enable 1220 * 0 - disable 1221 * 1222 * @return PHYMOD_E_NONE successful function execution 1223 */ 1224 int sesto_phy_fec_enable_set(const phymod_phy_access_t* phy, uint32_t enable) 1225 { 1226 return _sesto_fec_enable_set(phy, enable); 1227 } 1228 /** FEC enable get 1229 * This function is used to check whether or not FEC is enabled 1230 * 1231 * @param phy Pointer to phymod phy access structure 1232 * @param enable enable or disable 1233 * 1 - enable 1234 * 0 - disable 1235 * 1236 * @return PHYMOD_E_NONE successful function execution 1237 */ 1238 int sesto_phy_fec_enable_get(const phymod_phy_access_t* phy, uint32_t* enable) 1239 { 1240 return _sesto_fec_enable_get(phy, enable); 1241 } 1242 1243 /** FC/PCS checker enable set 1244 * This function is used to enable or disable FC/PCS checker 1245 * 1246 * @param phy Pointer to phymod phy access structure 1247 * @param fcpcs_chkr_mode FC/PCS checker mode 1248 * @param enable Enable or disable 1249 * 1 - enable 1250 * 0 - disable 1251 * 1252 * @return PHYMOD_E_NONE successful function execution 1253 */ 1254 int sesto_phy_fc_pcs_chkr_enable_set(const phymod_phy_access_t* phy, uint32_t fcpcs_chkr_mode, uint32_t enable) 1255 { 1256 return _sesto_pcs_link_monitor_enable_set(phy, enable); 1257 } 1258 /** FC/PCS checker enable get 1259 * This function is used to check whether or not FC/PCS checker enabled 1260 * 1261 * @param phy Pointer to phymod phy access structure 1262 * @param fcpcs_chkr_mode FC/PCS checker mode 1263 * @param enable Enable or disable 1264 * 1 - enable 1265 * 0 - disable 1266 */ 1267 int sesto_phy_fc_pcs_chkr_enable_get(const phymod_phy_access_t* phy, uint32_t fcpcs_chkr_mode, uint32_t *enable) 1268 { 1269 return _sesto_pcs_link_monitor_enable_get(phy, enable); 1270 } 1271 /** FC/PCS checker status get 1272 * This function is used to lock, loss of lock, error count status of the FC/PCS checker 1273 * 1274 * @param phy Pointer to phymod phy access structure 1275 * @param lock_status Live lock status 1276 * 1 - Locked 1277 * 0 - Not locked 1278 * @param lock_lost_lh Loss of lock 1279 * 1 - Loss of lock happened 1280 * 0 - No Loss of lock happended 1281 * @param error_count Error count 1282 * 1283 * @return PHYMOD_E_NONE successful function execution 1284 */ 1285 int sesto_phy_fc_pcs_chkr_status_get(const phymod_phy_access_t* phy, uint32_t* lock_status, uint32_t* lock_lost_lh, uint32_t* error_count) 1286 { 1287 return _sesto_get_pcs_link_status(phy, lock_status, lock_lost_lh, error_count); 1288 } 1289 1290 /*Read data from I2C device attached to PHY*/ 1291 int sesto_phy_i2c_read(const phymod_phy_access_t* phy, uint32_t flags, uint32_t addr, uint32_t offset, uint32_t size, uint8_t* data) 1292 { 1293 return _sesto_module_read(&phy->access, addr, offset, size, data); 1294 } 1295 1296 /*Write data to I2C device attached to PHY*/ 1297 int sesto_phy_i2c_write(const phymod_phy_access_t* phy, uint32_t flags, uint32_t addr, uint32_t offset, uint32_t size, const uint8_t* data) 1298 { 1299 return _sesto_module_write(&phy->access, addr, offset, size, data); 1300 } 1301 1302 /*Set/Get the output/input value of a PHY GPIO pin*/ 1303 int sesto_phy_gpio_pin_value_set(const phymod_phy_access_t* phy, int pin_no, int value) 1304 { 1305 return _sesto_gpio_pin_value_set(&phy->access, pin_no, value); 1306 } 1307 int sesto_phy_gpio_pin_value_get(const phymod_phy_access_t* phy, int pin_no, int* value) 1308 { 1309 return _sesto_gpio_pin_value_get(&phy->access, pin_no, value); 1310 } 1311 1312 /*Set/Get the configuration of a PHY GPIO pin*/ 1313 int sesto_phy_gpio_config_set(const phymod_phy_access_t* phy, int pin_no, phymod_gpio_mode_t gpio_mode) 1314 { 1315 return _sesto_gpio_config_set(&phy->access, pin_no, gpio_mode); 1316 } 1317 int sesto_phy_gpio_config_get(const phymod_phy_access_t* phy, int pin_no, phymod_gpio_mode_t* gpio_mode) 1318 { 1319 return _sesto_gpio_config_get(&phy->access, pin_no, gpio_mode); 1320 } 1321 int sesto_phy_short_chn_mode_enable_set(const phymod_phy_access_t* phy, uint32_t enable) 1322 { 1323 return _sesto_phy_short_channel_mode_set(phy, enable); 1324 } 1325 int sesto_phy_short_chn_mode_enable_get(const phymod_phy_access_t* phy, uint32_t *enable, uint32_t *status) 1326 { 1327 return _sesto_phy_short_channel_mode_get(phy, enable, status); 1328 } 1329 int sesto_phy_multi_get(const phymod_phy_access_t* phy, phymod_multi_data_t* multi_data) 1330 { 1331 int rv=PHYMOD_E_NONE; 1332 SESTO_IF_ERR_RETURN 1333 (_sesto_module_read(&phy->access, multi_data->dev_addr, multi_data->offset, multi_data->max_size, multi_data->data)); 1334 if(multi_data->actual_size){ 1335 (*(multi_data->actual_size)) = multi_data->max_size; 1336 } 1337 ERR: 1338 return rv; 1339 } 1340 1341 int sesto_phy_eye_margin_est_get(const phymod_phy_access_t* phy, phymod_eye_margin_mode_t eye_margin_mode, uint32_t* value) 1342 { 1343 int hz_l, hz_r, vt_u, vt_d; 1344 PHYMOD_IF_ERR_RETURN 1345 (_sesto_phy_eye_margin_est_get(phy,&hz_l, &hz_r, &vt_u, &vt_d) ); 1346 switch (eye_margin_mode) { 1347 case phymod_eye_marign_HZ_L: 1348 *value = hz_l; 1349 break; 1350 case phymod_eye_marign_HZ_R: 1351 *value = hz_r; 1352 break; 1353 case phymod_eye_marign_VT_U: 1354 *value = vt_u; 1355 break; 1356 case phymod_eye_marign_VT_D: 1357 *value = vt_d; 1358 break; 1359 default: 1360 *value = 0; 1361 break; 1362 } 1363 1364 return PHYMOD_E_NONE; 1365 } 1366 1367 int sesto_phy_op_mode_get(const phymod_phy_access_t* phy, phymod_operation_mode_t* op_mode) 1368 { 1369 return PHYMOD_E_UNAVAIL; 1370 } 1371